1988_National_Series_32000_Microprocessors_Databook 1988 National Series 32000 Microprocessors Databook
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~
National
~ Semiconductor
400093
Rev. 1
MICROPROCESSOR
DATABOOK
• Series 32000
• NSC800
1988 Edition
Series 32000 Overview
CPU-Central Processing Units
Slave Processors
Peripherals
Board Level Family
Development Tools
Software Support
Application Notes
NSC800 Family
Physical Dimensions! Appendices
iii
III
•II•
II
II
II
II
II
III
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iv
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Product Status Definitions
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Definition of Terms
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Data Sheet Identification
Product Status
Advance Information
Formative or
In Design
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Definition
Preliminary
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reserves the right to make changes at any time without notice in order
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Production
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Corporation reserves the right to make changes at any time without
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v
Table of Contents
Alphanumeric Index .......................................................... .
viii
Section 1 Series 32000 Overview
Introduction ................................................................. .
Key Features of Series 32000 ................................................. .
Series 32000 Component Descriptions ......................................... .
Hardware Chart ............................................................. .
Systems and Software Chart .................................................. .
Support Devices ............................................................. .
Military Aerospace Program ................................................... .
Series 32000 Programs and Services .......................................... .
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-12
Section 2 CPU-Central Processing Units
NS32532-20, NS32532-25, NS32532-30 High-Performance 32-Bit Microprocessors .. .
NS32332-10, NS32332-15 32-Bit Advanced Microprocessor ...................... .
NS32C032-10, NS32C032-15 High-Performance Microprocessors ................. .
NS32032-10 High-Performance Microprocessor ................................. .
NS32CG16-10, NS32CG16-15 High-Performance Printer/Display Processor ........ .
NS32C016-10, NS32C016-15 High-Performance Microprocessors ................. .
NS32016-10 High-Performance Microprocessor ................................. .
NS32008-10 High-Performance 8-Bit Microprocessor ............................ .
2-3
2-94
2-168
2-233
2-298
2-299
2-363
2-427
Section 3 Slave Processors
NS32382-10, NS32382-15 Memory Management Units (MMU) .................... .
NS32082-10 Memory Management Unit (MMU) ................................. .
NS32381-15, NS32381-20 Floating-Point Units .................................. .
NS32081-10, NS32081-15 Floating-Point Units .................................. .
NS32580-20, NS32580-25, NS32580-30 Floating-Point Controllers ................ .
3-3
3-42
3-81
3-111
3-128
Section 4 Peripherals
NS32C201-10, NS32C201-15 Timing Control Units .............................. .
NS32202-10 Interrupt Control Unit ............................................. .
NS32203-10 Direct Memory Access Controller (DMAC) ........................... .
4-3
4-25
4-50
Section 5 Board Level Products
VME532 High Performance 32-Bit CPU VME Board with Cache, Memory Management
and Floating Point ......................................................... .
DB332-PLUS Development Board ............................................. .
DB32000 Development Board ................................................. .
DB32016 Development Board ................................................. .
5-3
5-6
5-10
5-15
Section 6 Development Systems and Tools
SYS32/30 PC-Add-In Development Package .................................... .
SYS32/20 PC Add-In Development Package .................................... .
ISE32 NS32032 In-System Emulator ........................................... .
SPLICE Development Tool ................................................... .
6-3
6-9
6-12
6-21
Section 7 Software Support
Series 32000 GENIX Native and Cross-Support (GNX) Language Tools (Release 2) .. .
Series 32000 Ada Cross-Development System for SYS32/20 Host ................. .
Series 32000 Ada Cross-Development System for VAXIVMS Host ................. .
GENIX V.3 Operating System ................................................. .
Series 32000 Real-Time Software Components VRTX, lOX, FMX and TRACER ...... .
Series 32000 EXEC ROMabie Real-Time Multitasking Executive ................... .
7-3
7-7
7-11
7-16
7-19
7-39
Section 8 Application Notes
AB-26 Instruction Execution Times of FPU NS32081 Considered for Stand-Alone
Configurations ................................... . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
8-3
Table of Contents (Continued)
Section 8 Application Notes (Continued)
AB-27 Use of the NS32332 with the NS32082 and the NS32201 . . . . . . . . . . . . . . . . . . . .
AN-383 Interfacing the NS32081 as a Floating-Point Peripheral. . . . . . . . . . . . . . . . . . . . .
AN-404 10 MHz, No Wait States NS32016 System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-405 Using Dynamic RAM with Series 32000 CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-406 Interfacing the Series 32000 CPUs to the MULTIBUS ......................
AN-464 Effects of NS32082 Memory Management Unit on Processor Through Put. . . .
AN-513 Interfacing Memory to the NS32532 .....................................
AN-524 Introduction to Bresenham's Line Algorithm Using the SBIT Instruction; Series
32000 Note 5 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-526 Block Move Optimization Techniques; Series 32000 Graphics Note 2 ........
AN-527 Clearing Memory with the 32000; Series 32000 Graphics Note 3 . . . . . . . . . . . . .
AN-528 Image Rotation Algorithm; Series 32000 Graphics Note 4 . . . . . . . . . . . . . . . . . . .
AN-529 80 x 86 to Series 32000 Translation; Series 32000 Graphics Note 6 . . . . . . . . . .
AN-530 Bit Mirror Routine; Series 32000 Graphics Note 7 . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 9 NSC800
NSC800 High-Performance Low-Power CMOS Microprocessor. . . . . . . . . . . . . . . . . . . . .
NSC810A RAM-I/O-Timer.....................................................
NSC831 Parallel 1/0 .. ... .. . . .... .. . .. .. .. . ... . .. .. . . . .. ... .. .. . ... .. .. .. .... .
NSC888 NSC800 Evaluation Board.. . .. . . .. .. .. . .. .. . . . .. .. ... .. .. .. .. . ... .... .
Comparison Study NSC800 vs. 8085/80C85/Z80/Z80 CMOS.. .... ... . ... .... .... .
Software Comparison NSC800 vs. 8085, Z80 ....................................
Section 10 Physical Dimensionsl Appendices
Glossary of Terms. ... . .... . . ... . ... .. . . .. .. .. . .. .. . . . .. ..... .. .. . . .. . ... .... .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
vii
8-4
8-6
8-14
8-25
8-32
8-37
8-41
8-67
8-77
8-80
8-84
8-93
8-99
9-3
9-76
9-97
9-111
9-115
9-118
10-3
10-10
Alpha-Numeric Index
AB-26 Instruction Execution Times of FPU NS32081 Considered for Stand-Alone Configurations ..... 8-3
AB-27 Use of the NS32332 with the NS32082 and the NS32201 ................................. 8-4
AN-383 Interfacing the NS32081 as a Floating-Point Peripheral .................................. 8-6
AN-404 10 MHz, No Wait States NS32016 System ............................................ 8-14
AN-405 Using Dynamic RAM with Series 32000 CPUs ......................................... 8-25
AN-406 Interfacing the Series 32000 CPUs to the MULTIBUS .................................. 8-32
AN-464 Effects of NS32082 Memory Management Unit on Processor Through Put ................ 8-37
AN-513 Interfacing Memory to the NS32532 ................................................. 8-41
AN-524 Introduction to Bresenham's Line Algorithm Using the SBIT Instruction;
Series 32000 Note 5 .................................................................... 8-67
AN-526 Block Move Optimization Techniques; Series 32000 Graphics Note 2 .................... 8-77
AN-527 Clearing Memory with the 32000; Series 32000 Graphics Note 3 ......................... 8-80
AN-528 Image Rotation Algorithm; Series 32000 Graphics Note 4 ............................... 8-84
AN-529 80 x 86 to Series 32000 Translation; Series 32000 Graphics Note 6 ...................... 8-93
AN-530 Bit Mirror Routine; Series 32000 Graphics Note 7 ...................................... 8-99
Comparison Study NSC800 vs. 8085/80C85/Z80/Z80 CMOS ................................ 9-115
DB332-PLUS Development Board ........................................................... 5-6
DB32000 Development Board .............................................................. 5-10
DB32016 Development Board .............................................................. 5-15
GENIX V.3 Operating System .............................................................. 7-16
ISE32 NS32032 In-System Emulator ........................................................ 6-12
NS32C016-10 High-Performance Microprocessor ........................................... 2-299
NS32C016-15 High-Performance Microprocessor ........................................... 2-299
NS32C032-10 High-Performance Microprocessor ........................................... 2-168
NS32C032-15 High-Performance Microprocessor ........................................... 2-168
NS32C201-10 Timing Control Unit ........................................................... 4-3
NS32C201-15 Timing Control Unit ........................................................... 4-3
NS32CG16-10 High-Performance Printer/Display Processor .................................. 2-298
NS32CG16-15 High-Performance Printer/Display Processor .................................. 2-298
NS32008-10 High-Performance 8-Bit Microprocessor ........................................ 2-427
NS32016-10 High-Performance Microprocessor ............................................. 2-363
NS32032-10 High-Performance Microprocessor ............................................. 2-233
NS32081-10 Floating-Point Unit ........................................................... 3-111
NS32081-15 Floating-Point Unit ........................................................... 3-111
NS32082-10 Memory Management Unit (MMU) .............................................. 3-42
NS32202-10 Interrupt Control Unit .......................................................... 4-25
NS32203-1 0 Direct Memory Access Controller (DMAC) ........................................ 4-50
NS32332-10 32-Bit Advanced Microprocessor ............................................... 2-94
NS32332-15 32-Bit Advanced Microprocessor ............................................... 2-94
NS32381-15 Floating-Point Unit ............................................................ 3-81
NS32381-20 Floating-Point Unit ............................................................ 3-81
NS32382-10 Memory Management Unit (MMU) ............................................... 3-3
NS32382-15 Memory Management Unit (MMU) ............................................... 3-3
NS32532-20 High-Performance 32-Bit Microprocessor ......................................... 2-3
NS32532-25 High-Performance 32-Bit Microprocessor ......................................... 2-3
NS32532-30 High-Performance 32-Bit Microprocessor ......................................... 2-3
NS32580-20 Floating-Point Controller ...................................................... 3-128
NS32580-25 Floating-Point Controller ...................................................... 3-128
NS32580-30 Floating-Point Controller ...................................................... 3-128
NSC800 High-Performance Low-Power CMOS Microprocessor .................................. 9-3
NSC810A RAM-IIO-Timer ................................................................. 9-76
viii
Alpha-Numeric
Index(continUed)
NSC831 Parallel 1/0 ...................................................................... 9-97
NSC888 NSC800 Evaluation Board ........................................................ 9-111
Series 32000 Ada Cross-Development System for SYS32/20 Host ............................... 7-7
Series 32000 Ada Cross-Development System for VAXIVMS Host .............................. 7-11
Series 32000 EXEC ROMabie Real-Time Multitasking Executive ................................ 7-39
Series 32000 GENIX Native and Cross-Support (GNX) Language Tools (Release 2) ................ 7-3
Series 32000 Real-Time Software Components VRTX, lOX, FMX and TRACER ................... 7-19
Software Comparison NSC800 vs. 8085, Z80 ............................................... 9-118
SPLICE Development Tool ................................................................ 6-21
SYS32/20 PC Add-In Development Package .................................................. 6-9
SYS32/30 PC-Add-In Development Package .................................................. 6-3
VME532 High Performance 32-Bit CPU VME Board with Cache, Memory Management and
Floating Point ........................................................................... 5-3
ix
Section 1
Series 32000 Overview
•
Section 1 Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Features of Series 32000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 32000 Component Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Systems and Software Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
Support Devices ...................................................................
Military Aerospace Program. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .
Series 32000 Programs and Services .................................................
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-12
Introduction
Series 32000 offers the most complete solution to your 32-bit microprocessor needs via CPUs, slave processors, system peripherals,
evaluation/ development tools and software.
We at National Semiconductor firmly believe that it takes a total family
of microprocessors to effectively meet the needs of a system designer.
This Series 32000 Databook presents technical descriptions of Series
320008-, 16- and 32-bit microprocessors, slave processors, peripherals, software and development tools. It is designed to be updated
frequently so that our customers can have the latest technical information on the Series 32000.
Series 32000 leads the way in state-of-the-art microprocessor designs because of its advanced architecture, which includes:
• 32-Bit Architecture
• Demand Paged Virtual Memory
• Fast Floating-Point Capability
• High-Level Language Support
• Symmetrical Architecture
When we at National Semiconductor began the design of the Series
32000 microprocessor family, we decided to take a radical departure
from popular trends in architectural deSign that dated back more than
a decade. We chose to take the time to design it properly.
Working from the top down, we analyzed the issues and anticipated
the computing needs of the 80's and 90's. The result is an advanced
and efficient family of microprocessor hardware and software products.
Clearly, software productivity has become a major issue in computerrelated product development. In microprocessor-based systems this
issue centers around the capability of the microprocessor to maximize
the utility of software relative to shorter development cycles, improved software reliability and extended software life cycles.
In short, the degree to which the microprocessor can maximize software utility directly affects the cost of a product, its reliability, and time
to market. It also affects future software modification for product enhancement or rapid advances in hardware technology.
Our approach has been to define an architecture addressing these
software issues most effectively. Series 32000 combines 32-bit performance with efficient management of large address space. It facilitates high-level language program development and efficient instruction execution. Floating-point is integrated into the architecture.
This combination gives the user large system computing power at two
orders of magnitude less cost.
But we didn't stop there. Advanced architecture isn't enough. Our topdown approach includes the hardware, software, and development
support products necessary for your design. The evaluation board, insystem emulator, software development tools, including a VAX-11
cross-software package, and third party software are also available
now for your evaluation and development.
The Series 32000 is a solid foundation from which National Semiconductor can build solutions for your future designs while satisfying your
needs today.
For further information please contact your local sales office.
1-3
•
~National
~ Semiconductor
Key Features of Series 32000®
Some of the features that set the Series 32000 family apart
as the best choice for 32-bit designs are as follows:
FLOATING-POINT SUPPORT
The Series 32000 offers a complete set of floating-point
solutions. This includes the NS32081 Floating-Point Unit,
the NS32381 Floating-Point Unit and the NS32580 FloatingPoint Controller. The NS32081 provides high-speed arithmetic computation with high preCision and accuracy at low
cost. The NS32381 provides low power consumption and
even greater performance than the NS32081 while maintaining high-precision and accuracy.
The NS32580 is a floating-point controller that provides a
direct interface between the Weitek WTL 3164 FloatingPoint Data Path and the NS32532 CPU. This two chip combination, NS32580/WTL3164, provides optimum performance for speed critical floating-point applications.
FAMILY OF MICROPROCESSOR CHIP SETS
Series 32000 is more than just a single chip set, it is a family
of chip sets. By mixing and matching Series 32000 CPUs
with compatible slave processors and support chips, a system designer has an unprecedented degree of flexibility in
matching price/performance to the end product.
CLEANEST 32-BIT SUPER MINI COMPUTER
ARCHITECTURE
Series 32000 was designed around a 32-bit architecture
from the beginning. It has a fully symmetrical instruction set
so that all addressing modes and all data types can be operated on by all instructions. This makes it easy to learn the
architecture, easy to program in assembly language, and
easy to write code-efficient, high-level language compilers.
OPERATING SYSTEM SUPPORT
Series 32000 features such as hardware support for Demand-Paged Virtual memory management, user software
protection and modular programming make it much easier
to implement powerful, reliable and efficient operating systems. These features along with its symmetrical architecture
and powerful instruction set make the Series 32000 the
most efficient and highest performance UNIX engine.
DEMAND-PAGED VIRTUAL MEMORY MANAGEMENT
Series 32000 provides hardware support for Demand-Paged
Virtual Memory Management. This allows use of low-cost
disk storage to increase the apparent size of main memory,
and is an efficient method of managing very large address
spaces. It is also the same popular memory management
method used by DEC and IBM in their minicomputers and
mainframes.
HIGH· LEVEL LANGUAGE SUPPORT
Series 32000 has special features that support high-level
languages, thus improving software productivity and reducing development costs. For example, there are special instructions that help the compiler deal with structured data
types such as Arrays, Strings, Records, and Stacks. Also,
modular programming is supported by special hardware registers, software instructions, an external addressing mode,
and architecturally supported link tables.
APPLICATION·SPECIFIC SLAVE PROCESSORS
Series 32000 architecture allows users to deSign their own
application-specific slave processors to interface with the
existing chip set. These processors can be used to increase
the overall system performance by accelerating customized
CPU instructions that would otherwise be implemented in
software. At the same time, software compatibility is maintained, i.e., it is always possible to substitute lower-cost software modules in place of the slave processor.
1-4
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Series 32000® Component Descriptions
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Description
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External
Internal
Process
Address
Data
Package
Type
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0'
CENTRAL PROCESSING UNITS (CPU's)
NS32532
High-Performance 32-Bit Microprocessor
32
32
32
M2CMOS
175-pin PGA
NS32332
32-Bit Advanced Microprocessor
32
32
32
XMOS
(NMOS)
84-pin PGA
NS32C032
High-Performance Microprocessor
32
24
32
CMOS
68-pin LCC
Leadless
Chip Carrier
NS32032
High-Performance Microprocessor
32
24
32
XMOS
(NMOS)
68-pin LCC
Leadless
Chip Carrier
NS32C016
High-Performance Microprocessor
32
24
16
CMOS
48-pin DIP
Dual-In-Line
Package
NS32016
High-Performance Microprocessor
32
24
16
XMOS
(NMOS)
48-pin DIP
Dual-In-Line
Package
NS32008
High Performance 8-Bit Microprocessor
32
24
8
XMOS
(NMOS)
48-pin DIP
Dual-In-Line
Package
NS32CG16
High Performance PrinterIDisplay Processor
32
24
16
CMOS
68-pinPCC
SLAVE PROCESSORS
NS32382
Memory Management Unit
32
32
32
XMOS
(NMOS)
PGA
NS32082
Memory Management Unit
32
24
16
XMOS
(NMOS)
48-pin DIP
Package
NS32081
Floating-Point Unit
64
-
16
XMOS
24-pin DIP
Dual-In-Line
Package
NS32381
Floating-Point Unit
64
CMOS
68-pin PGA
Floating-Point Controller
64
-
16
NS32580
16or32
CMOS
172-pin PGA
CMOS
24-pin DIP
Dual-In-Line
Package
PERIPHERALS
NS32C201
CMOS Timing Control Unit
-
-
-
NS32202
Interrupt Control Unit
32
-
16
XMOS
(NMOS)
40-pin DIP
Dual-In-Line
Package
NS32203
Direct Memory Access Controller
-
-
16
XMOS
(NMOS)
48-pin DIP
Dual-In-Line
Package
1-5
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~ Semiconductor
Hardware Chart
PROCESSORS
SLAVE
PROCESSORS
PERIPHERALS
NS32C032
CMOS NS32032
NS32C016
CMOS NS32016
NS32081
Flce.tIng Point Unft
NSI6450
UART with
nrc
NS32580 with
Wll3164 Floating Point
Controller
CUSTOM
TL/XX/OOB4-1
1-6
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Support Devices Chart
SUPPORT
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DP8455
Disk Daia Synchronizer
DP8390
LAN Interface Controller
DP8461
Disk Data Separator
DP8391
Serial Network Interface
DP8462
Disk Daia Synchronizer
For 27 RLL Code
DP8392
COAX Transceiver Interface
DP84648
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MilitaryI Aerospace Programs
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This section is intended to provide a brief overview of military products available from National Semiconductor. For
further information, refer to our t 986 Reliability Handbook
which is expected to be available by mid t 986.
MIL-STD-883
Although originally intended to establish uniform test methods and procedures, MIL-STD-883 has also become the
general specification for non-JAN military product. Revision
C of this document defines minimum requirements for a device to be marked and advertised as 883-compliant. Included are design and construction criteria, documentation controls, electrical and mechanical screening requirements,
and quality control procedures. Details can be found in paragraph 1.2.1 of MIL-STD-883.
MIL-M-38510
The MIL-M-38510 Program, which is sometimes called the
JAN IC Program, is administered by the Defense Electronics
Supply Center (DESC). The purpose of this program is to
provide the military community with standardized products
that have been manufactured and screened to governmentcontrolled specifications in government certified facilities.
All 3851 0 manufacturers must be formally qualified and their
products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN products.
There are two processing levels specified within MIL-M38510: Classes Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft
and ground systems. National is a major supplier of both
classes of devices. Screening requirements are outlined in
Table III.
Tables I and II explain the JAN device marking system.
National offers both 883 Class Band 883 Class S product.
The screening requirements for both classes of product are
outlined in Table III.
As with DESC specifications, a manufacturer is allowed to
use his standard electrical tests provided that all critical parameters are tested. Also, the electrical test parameters,
test conditions, test limits, and test temperatures must be
clearly documented. At National Semiconductor, this information is available via our RETS (Reliability Electrical Test
Specification) program. The RETS document is a complete
description of the electrical tests performed and is controlled by our QA department. Individual copies are available
upon request.
Some of National's older products are not completely compliant with MIL-STD-883, but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked
"-Mil".
Copies of MIL-M-38510, the QPL, and other related documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179
DESC Specifications
Military Screening Program (MSP)
DESC specifications are issued to provide standardized versions of devices which are not yet available as JAN product.
MIL-STD-883 Class B screening is coupled with tightly controlled electrical specifications which have been written to
allow a manufacturer to use his standard electrical tests. A
current listing of National's DESC specification offerings can
be obtained from our franchised distributors, sales representatives, or DESC. DESC is located in Dayton, Ohio.
National's Military Screening Program was developed to
make screened versions of advanced products such as gate
arrays and microprocessors available more quickly than is
possible for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
brassboards prior to or during the JAN or 883 qualification
activities. MSP products receive the 100% screening of
Table III, but are not subjected to group C and D quality
conformance testing. Other criteria such as electrical testing
and temperature range will vary depending upon individual
device status and capability.
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TABLE I. The MIL-M-38510 Part Marking
TABLE II. JAN Package Codes
C'-
JM38!1 ~ O/XXXXXYVY
38510
Package
Designation
A= Solder Dipped
B=Tin Plate
C = Gold Plate
X= Any lead finish above
is acceptable
Dovlce Package
(see Table III)
'-- Screening Lovel
S, B, or C
'--- Dovice Number on
Slash Sheet
' - - - - Slash Sheet Number
For radiation hard devices
this slash is replaced by the
Radiation Hardness Assurance
Designator (M, D, R, or H per
paragraph 3.4.1.3 of MIL-M38510)
MIL-M-38510
JAN Prefix
(which may be applied only to
a fully conformant device per
paragraphs 3.6.2.1 and 3.6.7 of
MIL-M-38510)
A
B
C
D
E
F
G
H
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Microcircuit Industry
Description
14-pin 1/4" x 1/4" (metal) flat pack
14-pin 3/16" x 1/4" flat pack
14-pin 1/4" x3/4" dual-in-line
14-pin 1/4" x 3/8" (ceramic) flat pack
16-pin 1/4" x 7/8" dual-in-line
16-pin 1/4" x3/8"
(metal or ceramic) flat pack
8-pin TO-99 can or header
10-pin1/4" x1/4" (metal) flat pack
1O-pin TO-1 00 can or header
24-pin 1/2" x 1-1/4" dual-in-line
24-pin 3/8" x 5/8" flat pack
24-pin 1/4" x 1-1/4" dual-in-line
12-pin TO-1 01 can or header
(Note 1)
8-pin 1/4" X 3/8" dual-in-line
40-pin 3/16" X 2-1/16" dual-in-line
20-pin 1/4" X 1-1/16" dual-in-line
20-pin 1/4" x 1/2" flat pack
(Note 1)
(Note 1)
18-pin 3/8" x 15/16" dual-in-line
22-pin 3/8" x 1-1/8" dual-in-line
(Note 1)
(Note 1)
(Note 1)
20-terminal 0.350" x 0.350" chip carrier
28-terminal 0.450" x 0.450" chip carrier
Note 1: These letters are assigned to packages by individual detail specifi·
cations and may be assigned to different packages in different specifica-
tions.
TABLE 111.100% Screening Requirements
ClassB
ClassS
Screen
Reqmt
Method
Method
Reqmt
1. Wafer Lot Acceptance
5007
All Lots
2. Nondestructive
Bond Pull
2023
3. Internal Visual (Note 1)
2010, Condition A
100%
2010, Condition B
100%
4. Stabilization Bake
1008, Condition C,
Min, 24 Hrs. Min
100%
1008, Condition C,
Min, 24 Hrs. Min
100%
5. Temp. Cycling (Note 2)
1010, Condition C
100%
1010, Condition C
100%
6. Constant Acceleration
2001, Condition E (Min)
y 1 Orientation Only
100%
2001, Condition E (Min)
Y1 Orientation Only
100%
100%
7. Visual Inspection (Note 3)
8. Particle Impact Noise
Detection (PIND)
9. Serialization
100%
2020, Condition A
(Note 4)
100%
(NoteS)
100%
10. Interim (Pre-Bum-In)
Electrical Parameters
Per Applicable Device
Specification (Note 13)
100%
11. Burn-In Test
1015240 Hrs. at 125'C
Min (Cond. F Not Allowed)
100%
1-10
100%
Per Applicable Device
Specification (Note 6)
1015, 160 Hrs. at 125'C Min
100%
TABLE III. 100% Screening Requirements (Continued)
ClassB
ClassS
Screen
Method
Reqmt
12. Interim (Post-Burn-In)
Electrical Parameters
Per Applicable Device
Specification (Note 13)
100%
13. Reverse Bias Burn-In
(Note7)
1015; Test Condition A, C,
72 Hrs. at 150'C Min
(Cond. F Not Allowed)
100%
14. Interim (Post-Burn-In)
Electrical Parameters
Per Applicable Device
Specification (Note 13)
100%
15. PDA Calculation
5% Parametric (Note 14)
3% Functional- 25'C
16. Final Electrical Test
a) Static Tests
1) 25'C (Subgroup 1,
Table I, 5005)
2) Max & Min Rated
Operating Temp
(Subgroups 2, 3,
Table I, 5005)
b) Dynamic Tests &
Switching Tests,
25'C (Subgroups 4, 9,
Table I, 5005)
c) Functional Test,
25'C (Subgroup 7,
Table I, 5005)
Per Applicable Device
Specification
17. Seal Fine, Gross
1014
18. Radiographic (Note 10)
2012 Two Views
19. Qualification or Quality
Conformance Inspection
Test Sample Selection
(Note 11)
20. External Visual
(Note 12)
2009
All Lots
Method
Per Applicable Device
Specification
5% Parametric (Note 14)
Reqmt
100%
All Lots
Per Applicable Device
Specification
100%
100%
100%
100%
100%
100%
1000/0
1000/0
100%
(Note 8)
1014
1000/0
(Note 9)
1000/0
(Note 11)
Samp.
Samp.
1000/0
1000/0
Note 1: Unless otherwise specified, at the manufacturer's option, test samples for Group B, bond strength (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004), prior to sealing provided all other specification requirements are satisfied (e.g. bond strength requirements shall apply to
each inspection lot, bond failures shall be counted even if the bond would have failed internal visual).
Note 2: For Class B devices, this test may be replaced with thermal shock method 1011, test condition A, minimum.
Note 3: At the manufacturer's option, visual inspection for castastrophic failures may be conducted after each of the thermal/mechanical screens, after the
sequence or after seal test. Catastrophic failures are defined as missing leads, broken packages or lids off.
Note 4: The PI NO test may be performed in any sequence after step 9 and prior to step 16. See MIL·M-38510, paragraph 4.6.3.
Note 5: Class S devices shall be serialized prior to interim electrical parameter measurements.
Note 6: When specified, all devices shall be tested for those parameters requiring delta calculations.
Note 7: Reverse bias burn-in is a requirement only when specified in the applicable device specification. The order of performing burn-in and reverse bias burn-in
may be inverted.
Note 8: For Class S devices, the seal test may be performed in any sequence between step t 6 and step 19, but it shall be performed after all shearing and forming
operations on the terminals.
Nate 9: For Class B devices, the fine and gross seal tests shall be performed separate or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming operations on the terminals. When 100% seal screen cannot be performed after shearing and forming
(e.g. lIatpacks and chip carriers) the seal screen shall be done 100% prior to those operations and a sample test (LTPO = 5) shall be performed on each
inspection lot following these operations. If the sample fails, 100% rescreening shall be required.
Note 10: The radiographic screen may be performed in any sequence after step 9.
Note 11: Samples shall be selected for testing in accordance with the specific device class and lot requirements of Method 5005.
Nate 12: External visual shall be performed on the lot any time after step 19 and prior to shipment.
Note 13: Read and Record when post bum-in data measurements are specified.
Note 14: PDA shall apply to all static, dynamic, functional and switching measurements at either 25°C or maximum rated operating temperature.
1-11
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Series 32000 Programs and Services
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Technical Support Engineering
Center (TSEC)
National Semiconductors Technical Support Engineering
Center offers full aftersales service support. The Technical
Support Staff is available to answer technical questions,
and has the ability to utilize all of the resources within the
company to resolve issues or problems. Extended maintenance contracts are available extending the warranty period
of the product one full year, allowing full technical support,
software and/or hardware maintenance.
details and qualifications on the evaluation program, please
call one of the Service Center phone numbers listed above
or your local sales office.
The University Program
Begun as merely a concept several years ago, National
Semiconductor's University Program has now emerged as
one of the company's most successful programs. The University Program was originally created to establish a relationship between National and the academic community
that would foster the exchange of information and keep students abreast of modern advancements in technology.
The University Program catalog provides a complete, up-todate list of all student/university services as well as program application forms and course materials to guide instructors in introducing students to advanced microprocessors.
Because tomorrow's technology is dependent upon today's
nurturing of up-and-coming scientists and engineers, National is committed to supporting universities, particularly in
the area of microprocessor technology. National hopes that
more universities will share in this commitment by becoming
a part of the University Program.
For more information on any of these programs, contact the
Series 32000 University Program Manager, National Semiconductor Corporation, P.O. Box 58090, M/S D3-667, Santa
Clara, California 95052-8090, 408-721-7295.
HIGHLIGHTS OF THE EXTENDED MAINTENANCE
PROGRAM
1. Unlimited Technical Assistance-access to 24 hour Hot
Line and factory engineering staff'
2. Automatic Software Updates allowing customers to receive all software enhancements or bug fixes free of
charge whenever they become available for the products
covered.
3. Software Bulletin-Informative newsletter showing current software revisions, bug listings, work arounds, and
new product information.
4. Equipment repairs-Factory repair for all products covered, including equipment on loan.
OBTAINING A MAINTENANCE CONTRACT
1. Determine which product(s) are to be placed under maintenance (refer to the Service Products Guide).
2. Fill out the Maintenance Contract and return to the Service Center along with a purchase order, or call any of the
TSEC 800 numbers and a completed contract will be sent
to your attention for signature. Return the contract along
with a purchase order to us.
Microcomputer Systems Division
The Microcomputer Systems Division's goal is to become a
leading force in the microcomputer systems marketplace.
To achieve this goal, a total systems approach has been
taken on the Series 32000 program to provide the customer
with the necessary hardware and software support, evaluation and development tools, training, service and technical
literature.
The focus is on upward migration paths, system integration
at all levels and the preservation of the user's software investment.
Three groups (Microprocessor, Software Products and Development Systems) offer a broad capability to solve customer needs at various levels of performance and integration.
TOLL-FREE NUMBERS
(800) 538-1866 (OutSide of California)
(800) 672-1811 (Inside California)
(800) 223-3248 (Canada)
(408) 749-7306 (Rest of World)
49-08141-103-0 (Europe)
FACTORY REPAIRS
The Service Center provides highly trained technicians and
a complete range of Depot Services to meet your service
needs. For more information on depot services and pricing,
call one of the Service Center phone numbers listed above.
EVALUATION PROGRAM
The Series 32000 Development hardware and software
products are available for a free 30 day evaluation. For full
1-12
Section 2
CPU-Central Processing
Units
fII
Section 2 Contents
NS32532-20, NS32532-25, NS32532-30 High-Performance 32-Bit Microprocessors. . . . . . . . .
NS32332-10, NS32332-15 32-Bit Advanced Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS32C032-10, NS32C032-15 High-Performance Microprocessors. . . . . . . . . . . . . . . . . . . . . . . .
NS32032-10 High-Performance Microprocessor. .. . . ... . .. .. . . . .. . .... .. ... . .. .. . . .. ...
NS32CG16-10, NS32CG16-15 High-Performance Printer/Display Processor...............
NS32C016-10, NS32C016-15 High-Performance Microprocessors........................
NS32016-10 High-Performance Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NS32008-10 High-Performance 8-Bit Microprocessor.. .. . .. . . .. .. .. .... . ... .. .. . .. .. ...
2-2
2-3
2-94
2-168
2-233
2-298
2-299
2-363
2-427
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PRELIMINARY
~ Semiconductor
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NS32532-20/NS32532-25/NS32532-30
High-Performance 32-Bit Microprocessor
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General Description
Features
The NS32532 is a high-performance 32-bit microprocessor
in the Series 32000® family. It is software compatible with
the previous microprocessors in the family but with a greally
enhanced internal implementation.
III Software compatible with the Series 32000 family
II 4-GByte uniform addressing space
II
II
II
II
The NS32532 integrates more than 370,000 transistors fabricated in a 1.25 I-'m double-metal CMOS technology. The
advanced technology and mainframe-like design of the device enable it to achieve more than 10 times the throughput
of the NS32032 in typical applications.
In addition to generally improved performance, the
NS32532 offers much faster interrupt service and task
switching for real-time applications.
II
II
II
II
translation look-aside buffer
4-Stage instruction pipeline
512-Byte on-chip instruction cache
1024-Byte on-chip data cache
High-performance bus
- Separate 32-bit address and data lines
- Burst mode memory accessing
- Dynamic bus sizing
Extensive multiprocessing support
Floating-point support via the NS32381 or NS32580
1.25 I-'m double-metal CMOS technology
175-pin PGA package
Block Diagram
4-STAGE
INSTRUCTION PIPELINE
LOADER
INSTRUCTION
CACHE
(IC)
CONTROL
'--=--"\I7TT.rT7"TT:I---'\ ADDRESS
BUS
INTERFACE
UNIT
(BIU)
DATA
CACHE
(DC)
DATA INTERFACE
DATA
TL/EE/9354-1
FIGURE 1
2-3
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II On-chip memory management unit with 64-entry
The high-performance specifications are the result of a fourstage instruction pipeline, on-chip instruction and data
caches, on-chip memory management unit and a significantly increased clock frequency. In addition, the system
interface provides optimal support for applications spanning
a wide range, from low-cost, real-time controllers to highly
sophisticated, general purpose multiprocessor systems.
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II 32-bit architecture and implementation
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Table of Contents
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1.0 PRODUCT INTRODUCTION
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2.0 ARCHITECTURAL DESCRIPTION
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3.0 FUNCTIONAL DESCRIPTION (Continued)
3.1.3 Instruction Pipeline
3.1.3.1 Branch Prediction
2.1 Register Set
3.1.3.2 Memory Mapped lID
2.1.1 General Purpose Registers
3.1.3.3 Serializing Operations
2.1.2 Address Registers
3.1.4 Slave Processor Instructions
2.1.3 Processor Status Register
3.1.4.1 Regular Slave Instruction Protocol
2.1.4 Configuration Register
3.1.4.2 Pipelined Slave Instruction Protocol
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2.1.5 Memory Management Registers
3.1.4.3 Instruction Flow and Exceptions
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2.1.6 Debug Registers
3.1.4.4 Floating-Point Instructions
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3.1.4.5 Custom Slave Instructions
2.2 Memory Organization
3.2 Exception Processing
2.2.1 Address Mapping
3.2.1 Exception Acknowledge Sequence
2.3 Modular Software Support
3.2.2 Returning from an Exception Service Procedure
2.4 Memory Management
3.2.3 Maskable Interrupts
3.2.3.1 Non-Vectored Mode
2.4.1 Page Tables Structure
2.4.2 Virtual Address Spaces
3.2.3.2 Vectored Mode: Non-Cascaded Case
2.4.3 Page Table Entry Formats
3.2.3.3 Vectored Mode: Cascaded Case
2.4.4 Physical Address Generation
3.2.4 Non-Maskable Interrupt
2.4.5 Address Translation Algorithm
3.2.5 Traps
3.2.6 Bus Errors
2.5 Instruction Set
3.2.7 Priority Among Exceptions
2.5.1 General Instruction Format
3.2.8 Exception Acknowledge Sequences:
Detailed Flow
2.5.2 Addressing Modes
3.2.8.1 Maskable/Non-Maskable Interrupt
Sequence
2.5.3 Instruction Set Summary
3.0 FUNCTIONAL DESCRIPTION
3.2.8.2 Abort/Restartable Bus Error Sequence
3.1.1 Operating States
3.2.8.3 SLAVE/ILL/SVC/DVZlFLG/BPT lUND
Trap Sequence
3.1.2 Instruction Endings
3.2.8.4 Trace Trap Sequence
3.1 Instruction Execution
3.1.2.1 Completed Instructions
3.1.2.2 Suspended Instructions
3.1.2.3 Terminated Instructions
3.1.2.4 Partially Completed Instructions
2-4
Table of Contents (Continued)
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.0 FUNCTIONAL DESCRIPTION (Continued)
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3.2.B.5 Integer-Overflow Trap Sequence
3.5.B Interfacing Memory-Mapped I/O Devices
3.2.B.6 Debug Trap Sequence
3.5.9 Interrupt and Debug Trap Requests
3.2.B.7 Non-Restartable Bus Error Sequence
3.5.10 Cache Invalidation Requests
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3.5.11 Internal Status
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3.3 Debugging Support
4.0 DEVICE SPECIFICATIONS
3.3.1 Instruction Tracing
3.3.2 Debug Trap Capability
4.1 Pin Descriptions
3.4 On-Chip Caches
4.1.1 Supplies
3.4.1 Instruction Cache (IC)
4.1.2 Input Signals
3.4.2 Data Cache (DC)
4.1.3 Output Signals
3.4.3 Cache Coherence Support
4.1.4 Input/Output Signals
3.4.4 Translation Look-aside Buffer (TLB)
4.2 Absolute Maximum Ratings
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4.3 Electrical Characteristics
3.5 System Interface
4.4 SWitching Characteristics
3.5.1 Power and Grounding
3.5.2 Clocking
4.4.1 Definitions
3.5.3 Resetting
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
3.5.4 Bus Cycles
3.5.4.1 Bus Status
4.4.2.2 Input Signal Requirements
3.5.4.2 Basic Read and Write Cycles
4.4.3 Timing Diagrams
3.5.4.3 Burst Cycles
3.5.4.4 Cycle Extension
Appendix A: Instruction Formats
3.5.4.5 Interlocked Bus Cycles
B: Compatibility Issues
3.5.4.6 Interrupt Control Cycles
B.1 Restrictions on Compatibility
3.5.4.7 Slave Processor Bus Cycles
B.2 Architecture Extensions
3.5.5 Bus Exceptions
B.3 Integer-Overflow Trap
3.5.6 Dynamic Bus Configuration
B.4 Self-Modifying Code
3.5.6.1 Instruction Fetch Sequences
B.5 Memory-Mapped I/O
3.5.6.2 Data Read Sequences
C: Instruction Set Extensions
3.5.6.3 Data Write Sequences
C.1 Processor Service Instructions
3.5.7 Bus Access Control
C.2 Memory Management Instructions
C.3 Instruction Definitions
2-5
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List of Illustrations
CPU Block Diagram ............................................................•................................ 1
NS32532 Internal Registers .................................................................................... 2-1
Processor Status Register (PSR) ....•.....•...................•................................................. 2-2
Configuration Register (CFG) ................................................................................... 2-3
Page Table Base Registers (PTBn) .......•.......................•.............................................. 2-4
Memory Management Control Register (MCR) .................................................................... 2-5
Memory Management Status Register (MSR) ......•..............•..........................•.................... 2-6
Debug Condition Register (DCR) .................................................................•.............. 2-7
Debug Status Register (DSR) ................................................................................... 2-8
NS32532 Address Mapping .....................•................•............................................. 2-9
NS32532 Run-Time Environment ............•................................................................. 2-10
Two-Level Page Tables ..................•.................................................................•.. 2-11
Page Table Entries (PTE's) ............................................•....................................•.. 2-12
Virtual to Physical Address Translation .......................................................................... 2-13
General Instruction Format .................................................................................... 2-14
Index Byte Format ..•........................................................................................ 2-15
Displacement Encodings .......................•......•.......•............................................... 2-16
Operating States ............................................................•................................. 3-1
NS32532 Internal Instruction Pipeline ...•........................................................................ 3-2
Memory References for Consecutive Instructions .............•.........................•......................... 3·3
Memory References aiter Serialization ......................•.•.................................................. 3-4
Regular Slave Instruction Protocol: CPU Actions .................................................................. 3-5
ID and Operation Word ......................................................................................... 3-6
Slave Processor Status Word ................................................................................... 3-7
Instruction Flow in Pipelined Floating·Point Mode .................................................................. 3-8
Interrupt Dispatch Table ....................................................................................... 3·9
Exception Acknowledge Sequence: Direct-Exception Mode Disabled ............................................... 3-10
Exception Acknowledge Sequence: Direct·Exception Mode Enabled ................................................ 3-11
Return From Trap (RETIn) Instruction Flow: Direct-Exception Mode Disabled ........................................ 3·12
Return From Interrupt (RETI) Instruction Flow: Direct-Exception Mode Disabled ...................................... 3-13
Exception Processing Flowchart ............................................................................... 3-14
Service Sequence ........................................................................................... 3·15
Instruction Cache Structure ................................................................................... 3·16
Data Cache Structure ......................................................................................... 3·17
TLB Model .................................................................................................. 3-18
Power and Ground Connections ............................................................................... 3-19
Bus Clock Synchronization .................................................................................... 3·20
Power·On Reset Requirements ................................................................................ 3·21
General Reset Timing ...............................•........................................................ 3-22
Basic Read Cycle ............................................................................................ 3·23
Write Cycle .................................................................................................. 3·24
Burst Read cycles ............................................................................................ 3-25
Cycle Extension of a Basic Read Cycle ......................................................................... 3·26
Slave Processor Write Cycle ................................................................................... 3·27
Slave Processor Read Cycle .................................................................................. 3-28
Bus Retry During a Basic Read Cycle ........................................................................... 3-29
Basic Interface for 32·Bit Memories ...............•............................................................ 3·30
Basic Interface for 16-Bit Memories ............................................................................ 3-31
Hold Acknowledge: (Bus Initially Idle) ........................................................................... 3·32
Typical 1/0 Device Interface ................................................................................... 3-33
2-6
List of Illustrations
(Continued)
NS32532 Interface Signals ..................................................................................... 4-1
z
en
(0)
I\)
CJ1
(0)
I\)
I
175-Pin PGA Package ......................................................................................... 4-2
I\)
Timing Specification Standard (Signal Valid after Clock Edge) ....................................................... 4-3
.......
Timing Specification Standard (Signal Valid before Clock Edge) ..................................................... 4-4
en
Basic Read Cycle Timing ....................................................................................... 4-5
Write Cycle Timing ............................................................................................ 4-6
Interlocked Read and Write Cycles .............................................................................. 4-7
Burst Read Cycles ............................................................................................ 4-8
External Termination of Burst Cycles ............................................................................ 4-9
Bus Error or Retry During Burst Cycles .......................................................................... 4-10
Extended Retry Timing ....................................................................................... 4-11
HOLD Timing (Bus Initially Idle) ................................................................................ 4-12
HOLD Acknowledge Timing (Bus Initially Nolldle) ................................................................ 4-13
Q
Z
(0)
I\)
CJ1
(0)
I\)
I
I\)
CJ1
.......
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en
(0)
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CJ1
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I\)
I
(0)
Q
Slave Processor Read Timing ................................................................................. 4-14
Slave Processor Write Timing .................................................................................. 4-15
Slave Processor Done ........................................................................................ 4-16
FSSR Signal Timing .......................................................................................... 4-17
Cache Invalidation Request ................................................................................... 4-18
INT and NMI Signals Sampling ................................................................................. 4-19
Debug Trap Request ......................................................................................... 4-20
PFS Signal Timing ........................................................................................... 4-21
ISF Signal Timing ............................................................................................ 4-22
Break Point Signal Timing ..................................................................................... 4-23
Clock Waveforms ............................................................................................ 4-24
Bus Clock Synchronization .................................................................................... 4-25
Power-On Reset ............................................................................................. 4-26
Non-Power-On Reset ......................................................................................... 4-27
LPRilSPRi Instruction Formats ................................................................................. C-1
CINV Instruction Format ....................................................................................... C-2
LMRISMR Instruction Formats ................................................................................. C-3
List of Tables
Access Protection Levels ...................................................................................... 2-1
NS32532 Addressing Modes ................................................................................... 2-2
NS32532 Instruction Set Summary .............................................................................. 2-3
Floating-Poinllnstruction Protocol ............................................................................... 3-1
Custom Slave Instruction Protocols .............................................................................. 3-2
Summary of Exception Processing .............................................................................. 3-3
Interrupt Sequences ........................................................................................... 3-4
Cacheable/Non-Cacheable Instruction Fetches from a 32-Bit Bus ................................................... 3-5
Cacheable/Non-Cacheable Instruction Fetches from a 16-Bit Bus ................................................... 3-6
Cacheable/Non-Cacheable Instruction Fetches from an 8-Bit Bus ................................................... 3-7
Cacheable/Non-Cacheable Data Reads from a 32-Bit Bus ......................................................... 3-8
Cacheable/Non-Cacheable Data Reads from a 16-Bit Bus ......................................................... 3-9
Cacheable/Non-Cacheable Data Reads from an 8-Bit Bus ........................................................ 3-10
Data Writes to a 32-Bit Bus .................................................................................... 3-11
Data Writes to a 16-Bit Bus .................................................................................... 3-12
Data Writes to an 8-Bit Bus .................................................................................... 3-13
LPRi/SPRi New 'Short' Field Encodings ......................................................................... C-1
LMRISMR 'Short' Field Encodings .............................................................................. C-2
2-7
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1.0 Product Introduction
The NS32532 is an extremely sophisticated microprocessor
in the Series 32000 family with a full 32-bit architecture and
implementation optimized for high-performance applications.
Large, Uniform Addressing. The NS32532 has 32-bit address pointers that can address up to 4 gigabytes without
requiring any segmentation; this addressing scheme provides flexible memory management without added-on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a Significant reduction in hardware and
software costs.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
By employing a number of mainframe-like features, the device can deliver 15 MIPS peaks performance with no wait
states at a frequency of 30 MHz.
The NS32532 is fully software compatible will all the other
Series 32000 CPUs. The architectural features of the Series
32000 family and particularly the NS32532 CPU, are described briefly below.
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
Symmetric Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 architecture incorporates powerful instructions for control operations, such as array indexing and external procedure
calls, which save considerable space and time for compiled
code.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
• High-level language support
• Easy future growth path
Memory-to·Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided.
• Application flexibility
2.0 Architectural Description
This powerful memory-to-memory architecture permits
memory locations to be treated as registers for all usefull
operations. This is important for temporary operands as well
as for context switching.
2.1 REGISTER SET
The NS32532 CPU has 28 internal registers grouped according to functions as follows: 8 general purpose, 7 address, 1 processor status, 1 configuration, 7 memory management and 4 debug. All registers are 32 bits wide except
for the module and processor status, which are each 16 bits
wide. Figure 2-1 shows the NS32532 internal registers.
Memory Management. The NS32532 on-Chip memory
management unit provides advanced operating system support functions, including dynamic address translation, virtual
memory management, and memory protection.
+-
Address
32Bits
PC
SPO
SP1
FP
SB
INTBASE
I
I
General Purpose
32 Bits ~
RO
R1
R2
R3
R4
R5
R6
R7
+-
~
MOD
Processor Status
PSR
I
Debug
DCR
DSR
CAR
BPC
Memory Management
PTBO
PTB1
IVARO
IVAR1
TEAR
MCR
MSR
Configuration
CFG
FIGURE 2-1. NS32532 Internal Registers
2-8
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2.0 Architectural Description
CJ)
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(Continued)
N
U1
.
Co)
2.1.1 General Purpose Registers
INTBASE-Interrupt Base. The INT8ASE register holds
the address of the dispatch table for interrupts and traps
(Section 3.2.1).
There are eight registers (RO-R7) used for satisfying the
high speed general storage requirements, such as holding
temporary variables and addresses. The general purpose
registers are free for any use by the programmer. They are
32 bits in length. If a general purpose register is specified for
an operand that is eight or 16 bits long, only the low part of
the register is used; the high part is not referenced or modi·
fied.
MOD-Module. The MOD register holds the address of the
module descriptor of the currently executing software module. The MOD register is 16 bits long, therefore the module
table must be contained within the first 64 kbytes of memory.
The Processor Status Register (PSR) holds status information for the microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all programs, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
C The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used
with the AD DC and SU8C instructions to perform multiple-precision integer arithmetic calculations. It may
have a setting of 0 (no carry or borrow) or 1 (carry or
borrow).
sPa, SP1-Stack Pointers. The SPO register points to the
lowest address of the last item stored on the INTERRUPT
STACK. This stack is normally used only by the operating
system. It is used primarily for storing temporary data, and
holding return information for operating system subroutines
and interrupt and trap service routines. The SP1 register
pOints to the lowest address of the last item stored on the
USER STACK. This stack is used by normal user programs
to hold temporary data and subroutine return information.
When a reference is made to the selected Stack Pointer
(see PSR S-bit), the terms 'SP Register' or 'SP' are used.
SP refers to either SPO or SP1, depending on the setting of
the S bit in the PSR register. If the S bit in the PSR is 0, SP
refers to SPO. If the S bit in the PSR is 1 then SP refers to
SP1.
The NS32532 also allows the SP1 register to be directly
loaded and stored using privileged forms of the LPRi and
SPRi instructions, regardless of the setting of the PSR S-bit.
When SP1 is accessed in this manner, it is referred to as
'USP Register' or Simply 'USP'.
Stacks in the Series 32000 family grow downward in memory. A Push operation pre-decrements the Stack Pointer by
the operand length. A Pop operation post-increments the
Stack Pointer by the operand length.
The T bit causes program tracing. If this bit is set to 1, a
TRC trap is executed after every instruction (Section
3.3.1).
L
The L bit is altered by comparison instructions. In a
comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as unsigned integers. Otherwise, it is set to "0". In Floating-Point comparisons, this
bit is always cleared.
The V-bit enables generation of a trap (OVF) when an
integer arithmetic operation overflows.
F
Z
N
FP-Frame Pointer. The FP register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
The frame pointer holds the address in memory occupied by
the old contents of the frame pOinter.
SB-Static Base. The S8 register points to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The S8
register holds the lowest address in memory occupied by
the global variables of a module.
P
T
V
U
S
The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
The Z bit is altered by comparison instructions. In a
comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is
set to "0".
The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to "0".
If the U bit is "1" no privileged instructions may be executed. If the U bit is "0" then all instructions may be
executed. When U = 0 the processor is said to be in
Supervisor Mode; when U = 1 the processor is said to
Z
F
FIGURE 2·2. Processor Status Register (PSR)
2-9
V
N
o
.......
Z
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N
U1
.
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N
N
U1
.......
2.1.3 Processor Status Register
2.1.2 Address Registers
The seven address registers are used by the processor to
implement specific address functions. A description of them
follows.
PC-Program Counter. The PC register is a pOinter to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section.
N
L
T
Z
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2.0 Architectural Description (Continued)
S
P
be in User Mode. A User Mode program is restricted
from executing certain instructions and accessing certain registers which could interfere with the operating
system. For example, a User Mode program is prevented from changing the setting of the flag used to indicate
its own privilege mode. A Supervisor Mode program is
assumed to be a trusted part of the operating system,
hence it has no such restrictions.
The S bit specifies whether the SPO register or SP1
register is used as the Stack Pointer. The bit is automatically cleared on interrupts and traps. It may have a
setting of 0 (use the SPO register) or 1 (use the SP1
register).
The P bit prevents a TRC trap from occuring more than
once for an instruction (Section 3.3.1). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
If I = 1, then all interrupts will be accepted. If I = 0,
only the NMI interrupt is accepted. Trap enables are not
affected by this bit.
F
Floating-point instruction set. This bit indicates
whether a floating-point unit (FPU) is present to execute floating-point instructions. If this bit is 0 when the
CPU executes a floating-point instruction, a Trap
(UNO) occurs. If this bit is 1, then the CPU transfers
the instruction and any necessary operands to the
FPU using the slave-processor protocol described in
Section 3.1.4.1.
M
Memory management instruction set. This bit enables the execution of memory management instructions. If this bit is 0 when the CPU executes an LMR,
SMR, RDVAL, or WRVAL instruction, a Trap (UNO)
occurs. If this bit is 1, the CPU executes LMR, SMR,
RDVAL, and WRVAL instructions using the on-chip
MMU.
Custom instruction set. This bit indicates whether a
custom slave processor is present to execute custom
instructions. If this bit is 0 when the CPU executes a
custom instruction, a Trap (UNO) occurs. If this bit is
1, the CPU transfers the instruction and any necessary operands to the custom slave processor using
the slave-processor protocol described in Section
3.1.4.1.
C
2.1.4 Configuration Register
The Configuration Register (CFG) is 32 bits wide, of which
nine bits are implemented. The implemented bits enable
various operating modes for the CPU, including vectoring of
interrupts, execution of slave instructions, and control of the
on-chip caches. In the NS32332 bits 4 through 7 of the CFG
register selected between the 16-bit and 32-bit slave protocols and between 512-byte and 4-Kbyte page sizes. The
NS32532 supports only the 32-bit slave protocol and
4-Kbyte page size: consequently these bits are forced to 1.
DE
DC
Data Cache enable. This bit enables the on-Chip Data
Cache to be accessed for data reads and writes. Refer to Section 3.4.2 for more information.
LDC Lock Data Cache. This bit controls whether the contents of the on-chip Data Cache are locked to fixed
memory locations (LDC = 1), or updated when a data
read is missing from the cache (LDC=O).
IC
Instruction Cache enable. This bit enables the onchip Instruction Cache to be accessed for instruction
fetches. Refer to Section 3.4.1 for more information.
LIC Lock Instruction Cache. This bit controls whether the
contents of the on-chip Instruction Cache are locked
to fixed memory locations (LlC= 1), or updated when
an instruction fetch is misSing from the cache
(LlC=O).
When the CFG register is loaded using the LPRi instruction,
bits 13 through 31 should be set to O. Bits 4 through 7 are
ignored during loading, and are always returned as 1's when
CFG is stored via the SPRi instruction. When the SETCFG
instruction is executed, the contents of the CFG register bits
o through 3 are loaded from the instruction's short field, bits
4 through 7 are ignored and bits 8 through 12 are forced to
O.
The format of the CFG register is shown in Figure 2-3. The
various control bits are described below.
I
Interrupt vectoring. This bit controls whether maskable interrupts are handled in nonvectored (I = 0) or
vectored (I = 1) mode. Refer to Section 3.2.3 for more
information.
I
Reserved
I
PF
I LlC I
IC
I LDC I DC I
DE
Direct-Exception mode enable. This bit enables the
Direct-Exception mode for processing exceptions.
When this mode is selected, the CPU response time
to interrupts and other exceptions is significantly improved. Refer to Section 3.2.1 for more information.
PF
I
1
Pipelined Floating-point execution. This bit indicates
whether the floating-point unit uses the pipelined
slave protocol. When PF is 1 the pipelined protocol is
selected. PF is ignored if the F bit is O. Refer to Section 3.1.4.2 for more information.
I
1
I
1
I
FIGURE 2-3. Configuration Register (CFG) Bits
13 to 31 are Reserved; Bits 4 to 7 are Forced to 1.
2-10
01
I
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2.0 Architectural Description
(J)
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(Continued)
~
2.1.5 Memory Management Registers
OS
Dual Space. While this bitis 1, then PTB1 contains the
level-I page table base address of all addresses specified in User-Mode, and PTBO contains the level-I
page table base address of all addresses specified in
Supervisor Mode. While this bit is 0, then PTBO contains the level-I page table base address of all addresses specified in both User and Supervisor Modes.
AO Access Level Override. When this bit is set to 1, UserMode accesses are given Supervisor Mode privilege.
The NS32532 provides 7 registers to support memory management functions. They are accessed by means of the
LMR and SMR instructions. All of them can be read and
written except IVARO and IVARI that are write-only. A description of the memory management registers is given in
the following sections.
PTBO, PTB1-Page Table Base Pointers. The PTBn registers hold the physical addresses of the level-I page tables
used in address translation. The least significant 12 bits are
permanently zero, so that each register always points to a
4-Kbyte boundary in memory.
Base Address
11
000000000000
I
~
Z
(J)
w
~
(J1
W
~
~
Z
(J)
Reserved
FIGURE 2-5. Memory Management
Control Register (MCR)
w
~
(J1
w
~
I
W
MSR-Memory Management Status. The MSR register
provides status information related to the occurrence of a
translation exception. Only eight bits are implemented. Bits
8 to 31 are ignored when MSR is loaded and are returned
as zeroes when it is read as a 32-bit word. MSR is only
updated by the MMU when a protection violation or page
fault is detected while translating an address for a reference
required to execute an instruction. It is not updated if a page
fault is detected during either an operand or an instruction
prefetch, if the data being prefetched is not needed due to a
change in the instruction execution sequence. The format of
MSR is shown in Figure 2-6. Details on the function of each
bit are given below.
°
FIGURE 2-4. Page Table Base Registers (PTBn)
IVARO, IVARI-invalidate Virtual Address. The Invalidate
Virtual Address registers are write-only registers. When a
virtual address is written to IVARO or IVARI using the LMR
instruction, the translation for that virtual address is purged,
if present, from the TLB. This must be done whenever a
Page Table Entry has been changed in memory, since the
TLB might otherwise contain an incorrect translation value.
TEX
Another technique for purging TLB entries is to load a PTBn
register. Turning off translation (clearing the MCR TU and/
or TS bits) does not purge any entries from the TLB.
DDT
UST
Translate Supervisor. While this bit is 1, address translation is enabled for Supervisor Mode memory references. While this bit is 0, address translation is disabled for Supervisor-Mode memory references.
2-11
o
Translation Exception. This two-bit field specifies the
cause of the current address translation exception.
(Trap(ABT)). Combinations appearing in this field
are summarized below.
00
01
TEAR-Translation Exception Address Register. The
TEAR register is laoded by the on-chip MMU when a translation exception occurs. It contains the 32-bit virtual address
that caused the translation exception.
TEAR is not updated if a page fault is detected while prefetching an instruction that is not executed because the previous instruction caused a trap.
MCR-Memory Management Control. The MCR register
controls the operation of the MMU. Only four bits are implemented. Bits 4 to 31 are reserved for future use and must be
loaded with zeroes.
When MCR is read as a 32-bit word, bits 4 to 31 are returned as zeroes. The format of MCR is shown in Figure 2-5.
Details on the control bits are given below.
TU Translate User. While this bit is 1, address translation
is enabled for User-Mode memory references. While
this bit is 0, address translations is disabled for UserMode memory references.
TS
~
o
........
........
The format of the PTBn registers is shown in Figure 2-4.
12
w
(J1
When either PTBO or PTBI is loaded by executing an LMR
instruction, the MMU automatically invalidates all entries in
the TLB that had been translated using the old value in the
selected PTBn register.
31
(J1
No Translation Exception
First Level PTE Invalid
10 Second Level PTE Invalid
11 Protection Violation
During address translation, if a protection violation
and an invalid PTE are detected at the same time,
the TEX field is set to indicate a protection violation.
Data Direction. This bit indicates the direction of the
transfer that the CPU was attempting when the
translation exception occurred.
DDT = 0 = > Read Cycle
DDT = 1 = > Write Cycle
User/Supervisor. This bit indicates whether the
Translation Exception was caused by a User-Mode
or Supervisor Mode reference. If UST is 1, then the
exception was caused by a User-Mode reference;
otherwise it was caused by a Supervisor Mode reference.
fII
2.0 Architectural Description
31
(Continued)
'I'
Reserved
1
DDT
"I
FIGURE 2-6. Memory Management Status Register (MSR)
STT
CPU Status. This four bit field is set on an address
translation exception according to the following encodings.
1000 Sequential Instruction Fetch
1001 Non-Sequential Instruction Fetch
If a reference for an Interrupt-Acknowledge or Endof-Interrupt bus cycle (either Master of Cascaded)
causes a Translation Exception, then the value of
the STT-field is undefined.
2.1.6 Debug Registers
15
Enable debug conditions
BCP
Bus interface unit FIFO disable. When this bit is 1,
all data references, including Data Cache hits, appear on the system interface.
Single-Instruction mode enable. This bit, when set
to 1, inhibits the overlapping of instruction's execution.
Branch Condition Prediction disable. When this bit is
1, the branch prediction mechanism is disabled. See
Section 3.1.3.1.
DSR-Debug Status Register. The DSR Register indicates
debug conditions that have been detected. When the CPU
detects an enabled debug condition, it sets the corresponding bit (BC, BEX, BCA) in the DSR to 1. When an addresscompare condition is detected, then the RD-bit is loaded to
indicate whether a read or write reference was performed.
Software must clear all the bits in the DSR when appropri·
ate. The format of the DSR is shown in Figure 2-8; the various fields are described below.
RO
CBE2 Compare Byte Enable 2; when set, BYTE2 of an
aligned double-word is included in the address comparison
CBE3 Compare Byte Enable 3; when set, BYTE3 of an
aligned double-word is included in the address comparison
VNP Compare virtual address (VNP = 1) or physical address (VNP = 0)
Enable Trap (DBG) when a debug condition is detected
DEN
SI
CBE1 Compare Byte Enable 1; when set, BYTEl of an
aligned double-word is included in the address comparison
TR
Enable debug conditions in User-Mode
Enable debug conditions in Supervisor Mode
BF
The NS32532 contains 4 registers dedicated for debugging
functions.
These registers are accessed using privileged forms of the
LPRi and SPRi instructions.
OCR-Debug Condition Register. The DCR Register en·
abies detection of debug conditions. The format of the DCR
is shown in Figure 2-1; the various bits are described below.
A debug condition is enabled when the related bit is set to 1.
CBEO Compare Byte Enable 0; when set, BYTEO of an
aligned double-word is included in the address comparison
Address-compare enable for write references
Address-compare enable for read references
Address·compare enable
PC-match enable
UO
SO
The following 3 bits control testing features that can be
used during initial system debugging. These features are
unique to the NS32532 implementation of the Series 32000
architecture; as such, they may not be supported in future
implementations. For normal operation these 3 bits should
be set to O.
1010 Data Transfer
1011 Read Read-Modify-Write Operand
1100 Read for Effective Address
CWR
CRO
CAE
PCE
BPC
Indicates whether the last address-compare condition was for a read (RD = 1) or write (RD = 0)
reference
PC-match condition detected
BEX
BCA
External condition detected
Address-compare condition detected
CAR-Compare Address Register. The CAR Register
contains the address that is compared to operand reference
addresses to detect an address-compare condition. The ad·
dress must be double-word aligned; that is, the two leastsignificant bits must be O. The CAR is 32 bits wide.
9
Reserved
31
Reserved
FIGURE 2-7. Debug Condition Register (OCR)
BPC
BEX
Reserved
FIGURE 2-8. Debug Status Register (DSR)
2-12
r--------------------------------------------------------------------------.z
en
eN
2.0 Architectural Description (Continued)
BPC-Breakpoint Program Counter. The BPC Register
contains the address that is compared with the PC contents
to detect a PC-match condition. The BPC Register is 32 bits
wide.
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher. In
memory, the address of a double-word is the address of its
least significant byte, and a double·word may start at any
address.
2.2 MEMORY ORGANIZATION
The NS32532 implements full 32·bit virtual addresses. This
allows the CPU to access up to 4 Gbytes of virtual memory.
The memory is a uniform linear address space. Memory locations are numbered sequentially starting at zero and ending at 2 32 -1. The number specifying a memory location is
called an address. The contents of each memory location is
a byte consisting of eight bits. Unless otherwise noted, diagrams in this document show data stored in memory with
the lowest address on the right and the highest address on
the left. Also, when data is shown vertically, the lowest address is at the top of a diagram and the highest address at
the bottom of the diagram. When bits are numbered in a
diagram, the least significant bit is given the number zero,
and is shown at the right of the diagram. Bits are numbered
in increasing significance and toward the left.
A+3
24 23
1
A+2
16 15
1
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(.J1
A+1
A
LSB
I\)
(.J1
I\)
I
MSB
Double-Word at Address A
Although memory is addressed as bytes, it is actually organized as double-words. Note that access time to a word or a
double-word depends upon its address, e.g. double-words
that are aligned to start at addresses that are multiples of
four will be accessed more quickly than those not so
aligned. This also applies to words that cross a double-word
boundary.
2.2.1 Address Mapping
The NS32532 supports the use of memory-mapped peripheral devices and coprocessors. Such memory-mapped devices can be located at arbitrary locations in the address
space except for the upper 8 Mbytes of virtual memory (addresses between FF800000 (hex) and FFFFFFFF (hex), inclusive), which are reserved by National Semiconductor
Corporation. Nevertheless, it is recommended that high-performance peripheral devices and coprocessors be located
in a specific 8 Mbyte region of virtual memory (addresses
between FFOOOOOO (hex) and FF7FFFFF (hex), inclusive),
that is dedicated for memory-mapped I/O. This is because
the NS32532 detects references to the dedicated locations
and serializes reads and writes. See Section 3.1.3.3. When
making I/O references to addresses outside the dedicated
region, external hardware must indicate to the NS32532
that special handling is required.
A
Byte at Address A
Two contiguous bytes are called a word. Except where noted, the least significant byte of a word is stored at the lower
address, and the most significant byte of the word is stored
at the next higher address. In memory, the address of a
word is the address of its least significant byte, and a word
may start at any address.
A
A+1
I\)
o
......
eN
Figure 2-9 shows the NS32532 address mapping.
MSB
I\)
(.J1
eN
LSB
In this case a small performance degradation will also result. Refer to Section 3.1.3.2 for more information on memory-mapped I/O.
Word at Address A
Two contiguous words are called a double-word. Except
where noted, the least significant word of a double-word is
Address (Hex)
00000000
Memory and I/O
FFOOOOOO
Memory-Mapped I/O
FF800000
Reserved by NSC
FFFFFEOO
Interrupt Control
FFFFFFFF
FIGURE 2-9. NS32532 Address Mapping
2-13
......
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I\)
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o
2.0 Architectural Description
(Continued)
2.3 MODULAR SOFTWARE SUPPORT
The NS32532 provides special support for software modules and modular programs.
The Module Table is located within the first 64 kbytes of
virtual memory. This table contains a Module Descriptor
(also called a Module Table Entry) for each module in the
address space of the program. A Module Descriptor has
four 32-bit entries corresponding to each component of a
module:
• The Static Base entry contains the address of the beginning of the module's static data segment.
Each module in a NS32532 software environment consists
of three components:
1. Program Code Segment.
This segment contains the module's code and constant
data.
2. Static Data Segment.
• The Link Table Base pOints to the beginning of the module's Link Table.
Used to store variables and data that may be accessed
by all procedures within the module.
3. Link Table.
• The Program Base is the address of the beginning of the
code and constant data for the module.
• A fourth entry is currently unused but reserved.
The MOD Register in the CPU contains the address of the
Module Descriptor for the currently executing module.
This component contains two types of entries: Absolute
Addresses and Procedure Descriptors.
An Absolute Address is used in the external addressing
mode, in conjunction with a displacement and the current
MOD Register contents to compute the effective address
of an external variable belonging to another module.
The Static Base Register (SB) contains a copy of the Static
Base entry in the Module Descriptor of the currently executing module, i.e., it points to the beginning of the current
module's static data area.
This register is implemented in the CPU for efficiency purposes. By having a copy of the static base entry or chip, the
CPU can avoid reading it from memory each time a data
item in the static data segment is accessed.
The Procedure Descriptor is used in the call external procedure (CXP) instruction to compute the address of an
external procedure.
Normally, the linker program specifies the locations of the
three components. The Static Data and Link Table typically
reside in RAM; the code component can be either in RAM or
in ROM. The three components can be mapped into noncontiguous locations in memory, and each can be independently relocated. Since the Link Table contains the absolute
addresses of external variables, the linker need not assign
absolute memory addresses for these in the module itself;
they may be assigned at load time.
To handle the transfer of control from one module to another, the NS32532 uses a module table in memory and two
registers in the CPU.
In an NS32532 software environment modules need not be
linked together prior to loading. As modules are loaded, a
linking loader simply updates the Module Table and fills the
Link Table entries with the appropriate values. No modification of a module's code is required. Thus, modules may be
stored in read-only memory and may be added to a system
independently of each other, without regard to their individual addressing. Rgurs 2-10 shows a typical NS32532 runtime environment.
STATIC DATA
SEGMENT
SB REGISTER
DISP
I
I
I
31
I
I
I
LINK TABLE
a
ABSOLUTE ADDRESS
I
OFFSET--+q)+-~
I
I
I
I
I
I
I
I
I
DISP1.4
PROGRAM CODE
SEGMENT
DISP2
EXT. VARIABLE
TL/EE/9354-2
Note: Dashed lines indicate information copied to registers during transfer of control between modules.
FIGURE 2-10. NS32532 Run-Time Environment
2-14
z
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2.0 Architectural Description (Continued)
N
2.4 MEMORY MANAGEMENT
The Memory Mangement Unit of the NS32532 provides
support for demand-paged virtual memory. The MMU translates 32-bit virtual addresses into 32-bit physical addresses.
The page size is 4096 bytes.
The mapping from virtual to physical addresses is defined
by means of sets of tables in physical memory. These tables
are found by the MMU using one of its two Page Table Base
registers: PTBO or PTB 1. Which register is used depends on
the currently selected address space. See Section 2.4.2.
Level-2 Page Tables contain 1024 32-bit Page Table entries, and so occupy 4 Kbytes (1 page). Each Level-2 Page
Table Entry points to a final 4-Kbyte physical page frame. In
other words, its PFN provides the Page Frame Number portion (bits 12-31) of the translated address (Figure 2-13).
The OFFSET field of the translated address is taken directly
from the corresponding field of the virtual address.
2.4.2 Virtual Address Spaces
When the Dual Space option is selected for address translation in the MCR (Section 2.1.5) the on-chip MMU uses two
maps: one for translating addresses presented to it in Supervisor Mode and another for User Mode addresses. Each
map is referenced by the MMU using one of the two Page
Table Base registers: PTBO or PTB1. The MMU determines
the map to be used by applying the following rules.
1) While the CPU is in Supervisor Mode (UIS pin = 0), the
CPU is said to be generating virtual addresses belonging
to Address Space 0, and the MMU uses the PTBO register as its reference for looking up translations from memory.
2) While the CPU is in User Mode (UIS pin = 1), and the
MCR DS bit is set to enable Dual Space translation, the
CPU is said to be generating virtual addresses belonging
to Address Space 1, and the MMU uses the PTB1 register to look up translations.
3) If Dual Space translation is not selected in the MCR,
there is no Adress Space 1, and all virtual addresses generated in both Supervisor and User modes are considered by the MMU to be in Address Space O. The privilege
level of the CPU is used then only for access level checking.
Translation efficiency is improved by means of an on-chip
64-entry translation look-aside buffer (TLB). Refer to Section 3.4.4 for details.
If the MMU detects a protection violation or page fault while
translating an address for a reference required to execute
an instruction, a translation exception {Trap (ABT)) will result.
2.4.1 Page Tables Structure
The page tables are arranged in a two-level structure, as
shown in Figure 2-". Each of the MMU's PTBn registers
may point to a Level-1 page table. Each entry of the Level-1
page table may in turn point to a Level-2 page table. Each
Level-2 page table entry contains translation information for
one page of the virtual space.
The Level-1 page table must remain in physical memory
while the PTBn register contains its address and translation
is enabled. Level-2 Page Tables need not reside in physical
memory permanently, but may be swapped into physical
memory on demand as is done with the pages of the virtual
space.
The Level-1 Page Table contains 1024 32-bit Page Table
Entries (PTE's) and therefore occupies 4 Kbytes. Each entry
of the Level-1 Page Table contains a field used to construct
the physical base address of a Level-2 Page Table. This
field is a 20-bit PFN field, providing bits 12-31 of the physical address. The remaining bits (O-ll) are assumed zero,
placing a Level-2 Page Table always on a 4-Kbyte (page)
boundary.
~
L-_ _ _- - l
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.......
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W
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en
.......
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W
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W
C)
fII
4KBYTES
~-328ITS-
10Z4
11------1
1024
LEVEL·1
PAGE TA8LE
.
W
Note: When the CPU executes a Dual-Space Move instruction (MOVUSi or
MOVSUi), it temporarily enters User Mode by switching 1he state of
the ufs pin. Accesses made by the CPU during this time are treated
by the MMU as User·Mode accesses for both mapping and access
level checking. It is possible, however, to force the MMU to assume
Supervisor Mode privilege on such accesses by setting the Access
Override (AO) bit in the MCR (Section 2.t.5).
-328ITS--
PT8n
en
N
N
ENI . . ____. . /
MEMORY
LEVEL·2
PAGE TABLES
TL/EE/9354-3
FIGURE 2-11. Two-Level Page Tables
2-15
.
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(I)
2.0 Architectural Description (Continued)
R
2.4.3 Page Table Entry Formats
Figure 2-12 shows the formats of Level-l and Level-2 Page
Table Entries (PTE's).
Z
.....
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The bits are defined as follows:
~
V
N
Valid. The V bit is set and cleared only by software.
V = 1 = > The PTE is valid and may be used for
translation by the MMU.
(I)
V= 0 =
N
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.
N
N
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~
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(I)
> The
PTE does not represent a valid translation. Any attempt to use this PTE to translate and address will cause the MMU to
generate an Abort trap.
PL Protection Level. This two-bit field establishes the
types of accesses permitted for the page in both User
Mode and Supervisor Mode, as shown in Table 2-1.
Z
R
M
TABLE 2-1. Access Protection Levels
U/S
Protection Level Bits (PL)
00
01
10
11
User
1
no
access
no
access
read
only
full
access
Supervisor
0
read
only
full
access
full
access
full
access
NU
CI
' I'
'I'
USR
1
=>
The page has been referenced since the
R bit was last cleared.
>
The page has not been referenced since
the R bit was last cleared.
Modified. This is a status bit, set by the MMU whenever a write cycle is successfully performed to the
page mapped by this PTE. It is initialized to zero by
the operating system when the page is brought into
physical memory.
M = 1 = > The page has been modified since it was
last brought into physical memory.
M = 0 = > The page has not been modified since it
was last brought into physical memory.
In Level-l Page Table Entries, this bit position is undefined, and is unaltered.
USR User bits. These bits are ignored by the MMU and
their values are not changed.
Not Used. These bits are reserved by National for
future enhancements. Their values should be set to
zero.
Cache Inhibit. This bit appears only in Level-2 PTE's.
It is used to specify non-cacheable pages.
PFN
=
R= 0 =
The PL field is modified only by software. In a Level-l
PTE, it limits the maximum access level allowed for all
pages mapped through that PTE.
Mode
Referenced. This is a status bit, set by the MMU and
cleared by the operating system, that indicates
whether the page mapped by this PTE has been referenced within a period of time determined by the
operating system. It is intended to assist in implementing memory allocation strategies. In a Level-l
PTE, the R bit indicates only that the Level-2 Page
Table has been referenced for a translation, without
necessarily implying that the translation was successful. In a Level·2 PTE, it indicates that the page
mapped by the PTE has been sucessfully referenced.
PFN
They can be used by the user software.
Page Frame Number. This 20·bit field provides bits
12-31 of the physical address. See Figure 2-13.
R
NU
:
First Level PTE
8
31
1
PFN
"1"
USR
:
'I
M
R
CI
Second Level PTE
FIGURE 2-12. Page Table Entries (PTE's)
2-16
+
NU
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+ 'I
V
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2.0 Architectural Description
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(J1
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VIRTUAL ADDRESS
2221
1211
31
l
(J)
(Continued)
INDEX 1
INDEX 2
I
OFFSET
N
I
N
I
~
I
Z
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,. BI I-I I
lEVEl·1 PAGE TABLE
N
lEVEl·1 PTE
N
I
N
~
PTBn
31
INDEX 1
1211
PFN
DO
21
0
(J1
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I USR I NU IR IN+lv
31
0
ct
(1) SElECT 1ST PTE
IF 05=0 THEN
--,
Z
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(J)
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I
1024
PTEs
n=D
~
I
N
(J1
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~
ELSE
n = 1 FOR USER MODE
n = 0 FOR SUPV MODE
I I
PFN
4 BYTES-
~
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I I
PFN
31
1211
"
INDEX 2
000000000000
I
lEVEl·2 PAGE TABLE
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lEVEl·2 PTE
I I
•
00
21
N
~
0
PFN
lus~ M I RICI \"uIPll V
1024
0
prEs
31
(2) SELECT 2ND PTE
~
PHYSICAL ADDRESS
I
31
,.
PFN
I
12 11
"'
OFFSET
(3) GENERATE PHYSICAL
ADDRESS
TL/EE/9354-4
FIGURE 2-13. Virtual to Physical Address Translation
2.4.4 Physical Address Generation
by 4) to the base address taken from the Level-1 Page Table Entry. The PFN field of the selected entry provides the
entire Page Frame Number of the translated address.
The offset field of the virtual address is then appended to
this frame number to generate the final physical address.
When a virtual address is presented to the MMU and the
translation information is not in the TLB, the MMU performs
a page table lookup in order to generate the physical address.
The Page Table structure is traversed by the MMU using
fields taken from the virtual address. This sequence is diagrammed in Figure 2-13.
2.4.5. Address Translation Algorithm
The MMU either translates the 32-bit virtual address to a 32bit physical address or generates an abort trap to report a
translation error. The algorithm used by the MMU to perform
the translation is compatible with that of the NS32382. Refer to Appendix C for differences between the two MMUs.
Bits 12-31 of the virtual address hold the 20·bit Page Number, which in the course of the translation is replaced with
the 20·bit Page Frame Number of the physical address. The
virtual Page Number field is further divided into two fields,
INDEX 1 and INDEX 2.
Bits 0-11 constitute the OFFSET field, which identifies a
byte's position within the accessed page. Since the byte
pOSition within a page does not change with translation, this
value is not used, and is simply echoed by the MMU as bits
0-11 of the final physical address.
In the description that follows, the symbol 'u' takes the value 1 for a User-Mode memory reference. A reference is a
User-Mode reference in the following cases:
I. The reference is performed while executing in UserMode.
2. The reference is for the source operand of a MOVUS
instruction.
3. The reference is for the destination operand of a MOVSU
instruction.
The 10-bit INDEX 1 field of the virtual address is used as an
index into the Level·l Page Table, selecting one of its 1024
entries. The address of the entry is computed by adding
INDEX 1 (scaled by 4) to the contents of the current Page
Table Base register. The PFN field of that entry gives the
base address of the selected Level·2 Page Table.
The INDEX 2 field of the virtual address (10 bits) is used as
the index into the Level·2 Page Table, by adding it (scaled
The following notations are used in the algorithm.
•
•
•
•
2·17
AIIB --+ A concatenated with B
A.B --+ B is a field inside register A
(A) --+ object pointed to by address A
(A).B --+ B field of the object pointed to by address A
2.0 Architectural Description (Continued)
Each access is associated with one of two Address Spaces
(AS), defined as follows:
AS = U AND MCR.OS
If AS = 1, Page Table Base Register 1 (PTB1) is used to
select the first·level page table. If AS = 0, PTBO is used to
select the first·level page table.
• If (PTEV = 0) then
• ,. PTE2 Invalid"
-
The access-level is a 2-bit value used to specify the privilege level of an access. It is determined as follows:
• BIT1 = U AND (NOT(MCR.AO))
START TRANSLATION:
If (U = 0 AND MCR.TS = 0 OR U = 1 AND MCR.TU = 0)
• If ((write OR interlocked read) AND (PTER = 0 OR
PTE.M = 0) then Read-Modify-Write a double-word interlocked (PTE Pointer).R = 1, (PTE Pointer).M = 1;
then
/* address translation disabled .,
6. Generate Physical address:
• physical address -
(physical address virtual address; ClOUT pin = 0);
,. Note: ClOUT = 0 in all MMU generated accesses
'*
*'
*'
• Select entry for replacement;
• TLB. Virtual Page Number AS;
• TLB.AS • TLB. Physical Frame Number • TLB.PL -
• else (PTB = PTBO. AS = 0);
2. Fetch first level PTE:
• Effective PL PTEPL
3. Validate First Level PTE:
<
access level) then
*'
,. Protection Exception
TEAR virtual address,
clock MSR with MSR.TEX = 11,
terminate translation;
Note 2: If the MMU is translating a virtual address to check protection while
executing a RDVAL or WRVAL instruction. then Trap (ABT) occurs
only if the level·1 PTE is invalid and the access is permitted by the
PL-field.
2.5 INSTRUCTION SET
2.5.1 General Instruction Format
TEAR virtual address,
clock MSR with MSR.TEX = 01,
terminate translation;
Figure 2-14 shows the general format of a Series 32000
instruction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Addressing Mode (uGen") fields. Following the Basic Instruction field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes selected.
• If (PTER = 0) then
- Write a Byte (PTE Pointer) .R = 1;
•
4.
•
•
•
PTE.PFN
Effective PL
Note 1: The TEAR and MSR are only updated when a Trap (ABT) occurs. It
is possible that the MMU detects a page fault or protection violation
on a reference for an instruction that is not executed, for example
on a prefetch. In that event. Trap (ABT) does not occur. and the
TEAR and MSR are not updated.
• If (PTEV = 0) then
• ,. PTE1 Invalid .,
-
INDEX111INDEX2;
• TLB.CI PTECI
• TLB.M (PTE Pointer) .M
• Enable entry
END
• PTE Pointer = PTB.BASE ADDRESsIIINDEX11!00;
• PTE (PTE POinter); /* Fetch PTE1 .,
•
-
PTEPFNlloFFSET
• ClOUT pin PTECI
7. Update Translation Buffer:
• If (MCR.DS = 1 AND U = 1) then
- PTB = PTB1,
- AS = 1;
• If (PTEPL
TEAR virtual address,
clock MSR with MSR.TEX = 10,
terminate translation;
• If (read AND NOT interlocked) AND PTE.R = 0) then
Read-Modify-Write a double-word interlocked (PTE
Pointer).R = 1;
• BITO = 1 for write, or read with 'RMW' status
o otherwise
else BEGIN
(see also Figure 2-13)
1. Select PTB:
virtual address,
TEAR clock MSR with MSR.TEX = 11,
terminate translation;
-
Effective PL PTEPL
Fetch second level PTE:
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-15.
PTE Pointer = PTE.PFNIIINDEX21100;
'*
PTE (PTE Pointer);
Fetch PTE2 .,
If (PTEPL < effective PL) then
- Effective PL PTEPL;
5. Validate Second Level PTE:
• If (PTEPL < access level) then
• 1* Protection Exception .,
2-18
,--------------------------------------------------------------------------, z
2.0 Architectural Description
en
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(Continued)
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OPTIONAL
EXTENSIONS
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BASIC
INSTRUCTION
~
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r~----------------~A~----------------~\r~--------~~
~
IMPUED
IMMEDIATE
OPERAND(S)
DISP
IMM
DISP
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DISP2 DISPI DISP21DISPI
~
INDEX
BYTE
GEN
ADDR
MODE
A
INDEX
BYTE
IMM
~
l
1
I
I
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I
~
I
:
GEN
ADDR
MODE
B
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OPCODE
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TL/EE/9354-5
I'
l
GEN. ADDR. MODE
REG. NO.
'I
TL/EE/9354-6
FIGURE 2-15. Index Byte Format
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded with the top bits of that
field, as shown in Figure 2-16, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most significant byte first. Note that this is different from the memory
representation of data (Section 2.2).
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Byte Displacement: Range -64 to +63
SIGNED DISPLACEMENT
Word Displacement: Range -8192 to +8191
Some instructions require additional, 'implied" immediates
and/or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Section 2.5.3).
2.5.2 Addressing Modes
The CPU generally accesses an operand by calculating its
Effective Address based on information available when the
operand is to be accessed. The method to be used in performing this calculation is specified by the programmer as
an "addressing mode."
Double Word Displacement:
Range -(229 - 224) to + (2 29 - 1)*
0
7
Addressing modes are designed to optimally support highlevel language accesses to variables. In nearly all cases, a
variable access requires only one addressing mode, within
the instruction that acts upon that variable. Extraneous data
movement is therefore minimized.
1
I
I
1
I
~/-
Addressing Modes fall into nine basic types:
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated registers
~
TLlEE/9354-7
FIGURE 2-16. Displacement Encodlngs
'Note: The pattern "11100000" for the most significant byte of the displace-
ment is reserved by National for future enhancements. Therefore. it
should never be used by the user program. This causes the lower
limit of the displacement range to be -(229 -224) instead of -229.
2-19
w
CI
FIGURE 2-14. General Instruction Format
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2.0 Architectural Description (Continued)
Memory Relative: A pointer variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pOinter to generate the Effective Address of the operand.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written .
CO)
Absolute: The address of the operand is specified by a
displacement field in the instruction.
"o
External: A pOinter value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
en
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~
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en
z
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
Notations:
i = Integer length suffix: B = Byte
W = Word
o = Double Word
f
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
=
Floating Point length suffix: F = Standard Floating
L = Long Floating
gen = General operand. Any addressing mode can be
specified.
short = A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
imm = Implied immediate operand. An 8-bit value appended aiter any addressing extensions.
disp = Displacement (addressing constant): 8, 16 or 32
bits. All three lengths legal.
reg = Any General Purpose Register: RO-R7.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
Table 2-2 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
areg = Any Processor Register: Address, Debug, Status,
Configuration.
mreg = Any Memory Management Register.
creg = A Custom Slave Processor Register (Implementation Dependent).
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
2_5.3 Instruction Set Summary
Table 2-3 presents a brief description of the NS32532 instruction set. The Format column refers to the Instruction
2-20
z
2.0 Architectural Description
(J)
w
(Continued)
I\)
UI
w
TABLE 2-2. NS32532 Addressing Modes
I\)
I
ENCODING
Register
00000
00001
00010
00011
00100
00101
00110
00111
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO or FO
R1 or F1
R2 or F2
R3 or F3
R40rF4
R5 or F5
R60rF6
R7 or F7
None: Operand is in the
specified register.
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Memory Relative
10000
10001
10010
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (S8))
Disp2 + POinter; Pointer found at
address Disp1 + Register. "SP" is either
SPO or SP1, as selected in PSR.
Reserved
10011
(Reserved for Future Use)
Immediate
10100
Immediate
value
None. Operand is input from
instruction queue.
Absolute
10101
Absolute
@disp
Disp.
External
10110
External
EXT(disp1) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Top of Stack
10111
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Memory Space
11000
11001
11010
11011
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(S8)
*+disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Scaled Index
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:8]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2 x Rn.
EA (mode) + 4 X Rn.
EA (mode) + 8 x Rn.
"Mode' and 'n' are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
I\)
0
.......
Z
(J)
w
I\)
UI
W
I\)
I
I\)
UI
.......
Z
(J)
w
I\)
UI
w
w
I\)
2-21
I
0
0
·
CO)
N
CO)
2.0 Architectural Description
Ln
TABLE 2-3. NS32532 Instruction Set Summary
N
CO)
(J)
Z
......
Ln
N
N•
CO)
Ln
N
CO)
(J)
Z
......
0
·
N
N
CO)
Ln
N
CO)
(J)
Z
(Continued)
MOVES
Format
4
2
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4-bit constant.
Move Multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move Effective Address.
INTEGER ARITHMETIC
Format
Operation
4
ADDI
2
ADDQi
4
ADDCi
SUBi
4
4
SUBCi
6
NEGi
6
ABSi
7
MULi
7
QUOi
7
REMi
7
DIVi
7
MODi
7
MEli
7
DEli
Operands
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to Extended Integer.
Divide Extended Integer.
PACKED DECIMAL (BCD)
Format
Operation
6
ADDPi
6
SUBPi
ARITHMETIC
Operands
gen,gen
gen,gen
Description
Add Packed.
Subtract Packed.
INTEGER COMPARISON
Format
Operation
4
CMPi
2
CMPQi
7
CMPMi
Operands
gen,gen
short,gen
gen,gen,disp
Description
Compare.
Compare to signed 4-bit constant.
Compare Multiple: disp bytes (1 to 16).
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
LOGICAL AND BOOLEAN
Format
Operation
Operands
4
gen,gen
ANDi
4
ORi
gen,gen
4
gen,gen
BICi
4
XORi
gen,gen
gen,gen
6
COMi
6
NOTi
gen,gen
2
gen
Scondi
SHIFTS
Format
6
6
6
Operation
LSHi
ASHi
ROTi
Operands
gen,gen
gen,gen
gen,gen
Description
Logical AND.
Logical OR.
Clear selected bits.
Logical Exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
Description
Logical Shift, left or right.
Arithmetic Shift, left or right.
Rotate, left or right.
2-22
z
2.0 Architectural Description
(J)
Co)
(Continued)
TABLE 2-3. NS32532 Instruction Set Summary (Continued)
BITS
Format
4
6
6
6
6
6
8
8
8
5
5
N
I
Operation
TBITi
SBITi
SBITIi
CBITi
CBITli
IBITi
FFSi
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Operation
CHECKi
INDEXi
Operands
reg,gen,gen
reg,gen,gen
STRINGS
String instructions assign specific functions to
the General Purpose Registers:
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
RI - String I Pointer
RO - Limit Count
Format
5
Co)
N
Description
Test bit.
Test and set bit.
Test and set bit, interlocked.
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit.
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records used in
Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned source.
Format
Operation
Operands
Description
8
EXTi
reg,gen,gen,disp
Extract bit field (array oriented).
INSi
reg,gen,gen,disp
Insert bit field (array oriented).
8
7
EXTSi
gen,gen,imm,imm
Extract bit field (short form).
7
INSSi
gen,gen,imm,imm
Insert bit field (short form).
8
CVTP
reg,gen,gen
Convert to Bit Field Pointer.
ARRAYS
Format
N
C1I
Operation
MOVSi
MOVST
CMPSi
CMPST
SKPSi
SKPST
Operands
options
options
options
options
options
options
Description
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
Options on all string instructions are:
B (Backward):
Decrement string pointers after each step
rather than incrementing.
End instruction if String I entry
U (Until match):
matchesR4.
W (While match):
End instruction if String I entry
does not match R4.
All string instructions end when RO decrements to zero.
Description
Move String I to String 2.
Move string, translating bytes.
Compare String I to String 2.
Compare translating, String I bytes.
Skip over String I entries.
Skip, translating bytes for Until/While.
2-23
o
Z
(J)
Co)
N
C1I
Co)
N
I
N
C1I
Z
(J)
Co)
N
C1I
Co)
N
I
Co)
o
C)
C')
r---------------------------------------------------------------------------------,
~
an
2.0 Architectural Description
(I)
JUMPS AND LINKAGE
Format
Operation
3
JUMP
0
BR
0
Bcond
3
CASEi
2
ACBi
3
JSR
BSR
CXP
3
CXPD
1
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
~
Z
......
an
.
N
N
C')
an
N
C')
(I)
Z
.....
C)
N
~
C')
an
N
C')
(I)
Z
(Continued)
TABLE 2-3. NS32532 Instruction Set Summary (Continued)
Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
[reg listl,disp
[reg list]
disp
disp
disp
CPU REGISTER MANIPULATION
Format
Operation
Operands
1
[reg list]
SAVE
[reg list]
1
RESTORE
2
LPRi
areg,gen
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor Call.
Flag Trap.
Breakpoint Trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
2
SPRi
areg,gen
3
ADJSPi
BISPSRi
BICPSRi
SETCFG
gen
gen
gen
[option list]
Description
Save General Purpose Registers.
Restore General Purpose Registers.
Load Processor Register. (Privileged if PSR, INTBASE, USP, CFG
or Debug Registers).
Store Processor Register. (Privileged if PSR, INTBASE, USP, CFG
or Debug Registers).
Adjust Stack Pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set Configuration Register. (Privileged)
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Description
Move a Floating Point value.
Move and shorten a Long value to Standard.
Move and lengthen a Standard value to Long.
Convert any integer to Standard or Long Floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Load FSR.
Store FSR.
3
3
5
FLOATING POINT
Format
Operation
11
MOVf
9
MOVLF
9
MOVFL
9
MOVfi
9
ROUNDfi
9
TRUNCfi
9
FLOORfi
11
ADDf
11
SUBf
11
MUll
11
DIVf
11
CMPf
11
NEGf
11
ABSf
9
LFSR
9
SFSR
2-24
z
2.0 Architectural Description
(J)
w
(Continued)
TABLE 2-3. NS32532 Instruction Set Summary (Continued)
MEMORY MANAGEMENT
Format
Operation
14
LMR
14
SMR
14
RDVAL
14
WRVAL
8
MOVSUi
8
MOVUSi
MISCELLANEOUS
Format
Operation
1
NOP
WAIT
DIA
14
CINV
CUSTOM SLAVE
Format
Operation
15.5
CCALOc
15.5
CCAL1c
15.5
CCAL2c
15.5
CCAL3c
15.5
CMOVOc
15.5
CMOV1c
15.5
CMOV2c
CMOV3c
15.5
15.5
CCMPOc
15.5
CCMP1c
15.1
CCVOci
15.1
CCV1ci
15.1
CCV2ci
15.1
CCV3ic
15.1
CCV4DQ
15.1
CCV5QD
15.1
LCSR
15.1
SCSR
15.0
LCR
15.0
SCR
Operands
mreg,gen
mreg,gen
gen
gen
gen,gen
gen,gen
Operands
options,gen
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
creg,gen
creg,gen
Description
Load Memory Management Register. (Privileged)
Store Memory Management Register. (Privileged)
Validate address for reading. (Privileged)
Validate address for writing. (Privileged)
Move a value from Supervisor
Space to User Space. (Privileged)
Move a value from User Space
to Supervisor Space. (Privileged)
Description
No Operation.
Wait for interrupt.
Diagnose. Single·byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
Cache Invalidate. (Privileged)
Description
Custom Calculate.
Custom Move.
Custom Compare.
Custom Convert.
Load Custom Status Register.
Store Custom Status Register.
Load Custom Register. (Privileged)
Store Custom Register. (Privileged)
2·25
N
U1
w
·
N
N
0
......
Z
(J)
w
N
U1
w
N
N
U1
•
......
Z
(J)
w
N
U1
w
N
w
·
0
3.0 Functional Description
This chapter provides details on the functional characteristics of the NS32532 microprocessor.
RST ACTIVE
The chapter is divided into five main sections:
Instruction Execution, Exception Processing, Debugging,
On-Chip Caches and System Interface.
3.1 INSTRUCTION EXECUTION
To execute an instruction, the NS32532 performs the following operations:
• Fetch the instruction
• Read source operands, if any (1)
• Calculate results
• Write result operands, if any
• Modify flags, if necessary
• Update the program counter
Under most circumstances, the CPU can be conceived to
execute instructions by completing the operations above in
strict sequence for one instruction and then beginning the
sequence of operations for the next instruction. However,
due to the internal instruction pipelining, as well as the occurrence of exceptions, the sequence of operations performed during the execution of an instruction may be altered. Furthermore, exceptions also break the sequentiality
of the instructions executed by the CPU.
Details on the effects of the internal pipelining, as well as
the occurrence of exceptions on the instruction execution,
are provided in the following sections.
TL/EE/9354-B
FIGURE 3-1. Operating States
tion is detected, the CPU enters the Processing-An-Exception state.
The CPU enters the Halted state when a bus error or abort
is detected while the CPU is processing an exception, thereby preventing the transfer of control to an appropriate exception service procedure. The CPU remains in the Halted
state until reset occurs. A special status identifying this state
is presented on the system interface.
Note: 1 In this and following sections, memory locations read by the CPU to
calculate effective addresses for Memory·Relative and External ad·
dressing modes are considered like source operands, even if the
effective address Is being calculated for an operand with access
class of write.
3.1.1 Operating States
The CPU has five operating states regarding the execution
of instructions and the processing of exceptions: Reset, Executing Instructions, Processing An Exception, Waiting-ForAn-Interrupt, and Halted. The various states and transitions
.
between them are shown in Figure 3-1.
Note: When the Direct·Exception mode is enabled. the CPU does not save
the MOD Register contents nor does it read the module linkage infor·
mation for the exception service procedure. Refer to Section 3.2 for
details.
Whenever the RST Signal is asserted, the CPU enters the
reset state. The CPU remains in the reset state until the
RSf signal is driven inactive, at which time it enters the
Executing-Instructions state. In the Reset state the contents
of certain registers are initialized. Refer to Section 3.5.3 for
details.
3.1.2 Instruction Endings
The NS32532 checks for exceptions at various points while
executing instructions. Certain exceptions, like interrupts,
are in most cases recognized between instructions. Other
exceptions, like Divide-8y-Zero Trap, are recognized during
execution of an instruction. When an exception is recognized during execution of an instruction, the instruction ends
in one of four possible ways: completed, suspended, terminated, or partially completed. Each type of exception causes a particular ending, as specified in Section 3.2.
In the Executing-Instructions state, the CPU executes instructions. It will exit this state when an exception is recognized or a WAIT instruction is encountered. At which time it
enters the Processing-An-Exception state or the WaitingFor-An-Interrupt state respectively.
While in the Processing-An-Exception state, the CPU saves
the PC, PSR and MOD register contents on the stack and
reads the new PC and module linkage information to begin
execution of the exception service procedure (see note).
3.1.2.1 Completed Instructions
When an exception is recognized after an instruction is
completed, the CPU has performed all of the operations for
that instruction and for all other instructions executed since
the last exception occurred. Result operands have been
written, flags have been modified, and the PC saved on the
Interrupt Stack contains the address of the next instruction
to execute. The exception service procedure can, at its conclusion, execute the RETT instruction (or the RETI instruction for vectored interrupts), and the CPU will begin executing the instruction following the completed instruction.
Following the completion of all data references required to
process an exception, the CPU enters the Executing-Instructions state.
In the Waiting-For-An-Interrupt state, the CPU is idle. A special status identifying this state is presented on the system
interface (Section 3.5). When an interrupt or a debug condi-
2-26
z
3.0 Functional Description
(J)
Co)
(Continued)
3.1.2.2 Suspended Instructions
An instruction is suspended when one of several trap conditions or a restartable bus error is detected during execution
of the instruction. A suspended instruction has not been
completed, but all other instructions executed since the last
exception occurred have been completed. Result operands
and flags due to be affected by the instruction may have
been modified, but only modifications that allow the instruction to be executed again and completed can occur. For
certain exceptions (Trap (AST), Trap (UND), Trap (ILL), and
bus errors) the CPU clears the P-f1ag in the PSR before
saving the copy that is pushed on the Interrupt Stack. The
PC saved on the Interrupt Stack contains the address of the
suspended instruction.
For example, the RESTORE instruction pops up to 8 general-purpose registers from the stack. If an invalid page table
entry is detected on one of the references to the stack, then
the instruction is suspended. The general-purpose registers
due to be loaded by the instruction may have been modified,
but the stack pOinter still holds the same value that it did
when the instruction began.
1. The service procedure can simulate the suspended in·
3.1.2.4 Partially Completed Instructions
(J)
When a restartable bus error, interrupt, abort, or debug condition is recognized during execution of a string instruction,
the instruction is said to be partially completed. A partially
completed instruction has not completed, but all other instructions executed since the last exception occurred have
been completed. Result operands and flags due to be affected by the instruction may have been modified, but the
values stored in the string pOinters and other general-purpose registers used during the instruction's execution allow
the instruction to be executed again and completed.
N
U1
The NS32532 executes instructions in a heavily pipelined
fashion. This allows a significant performance enhancement
since the operations of several instructions are performed
simultaneously rather than in a strictly sequential manner.
The CPU provides a four-stage internal instruction pipeline.
As shown in Figure 3-2, a write buffer, that can hold up to
two operands, is also provided to allow write operations to
be performed off-line.
I....._-..,..-----'I
2. The suspended instruction can be executed again after
the service procedure has eliminated the trap condition
that caused the instruction to be suspended. The service
procedure should execute the RETT instruction at its conclusion; then the CPU begins executing the suspended
instruction again. This is the action taken by a debugger
when it encounters a SPT instruction that was temporarily
placed in another instruction's location in order to set a
breakpoint.
Fetch Instruction
._______t_______ .
:
8 Byte Queue
Decode Instruction
._______t_______ .
Note 1: Although the NS32532 allows a suspended instruction to be execut·
ed again and completed, the CPU may have read a source operand
for the instruction from a memory.mapped peripheral port before
the exception was recognized. In such a casa, the characteristics of
the peripheral device may prevent correct reexecution of the instruction.
Note 2: It may be necessary for the exception service procedure to alter the
P·flag in the PSR copy saved on the Interrupt Stack: If the exception
service procedure simulates the suspended instruction and the p.
flag was cleared by the CPU before saving the PSR copy, then the
saved T·flag must be copied to the saved P·flag (like the floating·
point instruction simulation described above). Or if the exception
service procedure executes the suspended instruction again and
the P·flag was not cleared by the CPU before saving the PSR copy,
then the saved P·flag must be cleared (like the breakpoint trap de·
scribed above). Otherwise, no alteration to the saved P·flag is nec·
essary.
:
1 Decoded Instruction
Stage 1
: Buffer
--------1-------·
I
I
Stage 2
: Buffer
--------1-------·
I
Calculate Results
Write Destination Operands
I
Stage 4
._______t_______ .
:
2 Memory Results
: Buffer
._-------------_.
TL/EE/9354-9
FIGURE 3-2. NS32532 Internal Instruction Pipeline
3.1.2.3 Terminated Instructions
Due to the pipe lining, operations like fetching one instruction, reading the source operands of a second instruction,
calculating the results of a third instruction and storing the
results of a fourth instruction, can all occur in parallel.
An instruction being executed is terminated when reset or a
nonrestartable bus error occurs. Any result operands and
flags due to be affected by the instruction are undefined, as
2-27
Co)
N
N
Z
Co)
3.1.3 Instruction Pipeline
struction's execution. After calculating and writing the in·
struction's results, the flags in the PSR copy saved on the
Interrupt Stack should be modified, and the PC saved on
the Interrupt Stack should be updated to point to the next
instruction to execute. The service procedure can then
execute the RETT instruction, and the CPU begins executing the instruction following the suspended instruction.
This is the action taken when floating-point instructions
are simulated by software in systems without a hardware
floating-point unit.
.
o
.....
The CPU clears the P-f1ag in the PSR before saving the
copy that is pushed on the Interrupt Stack. The PC saved on
the Interrupt Stack contains the address of the partially
completed instruction. The exception service procedure
can, at its conclusion, simply execute the RETT instruction
(or the RETI instruction for vectored interrupts), and the
CPU will resume executing the partially completed instruction.
To complete a suspended instruction, the exception service
procedure takes either of two actions:
N
U1
is the contents of the PC. The result operands of other in·
structions executed since the last serializing operation may
not have been written to memory. A terminated instruction
cannot be completed.
Co)
~
N
U1
.....
Z
(J)
Co)
N
U1
Co)
N
•
Co)
o
3.0 Functional Description
(Continued)
The order of memory references performed by the CPU may
also differ from that related to a strictly sequential instruction execution. In fact, when an instruction is being executed, some of the source operands may be read from memory
before the instruction is completely fetched. For example,
the CPU may read the first source operand for an instruction
before it has fetched a displacement used in calculating the
address of the second source operand. The CPU, however,
always completes fetching an instruction and reading its
source operands before writing its results. When more than
one source operand must be read from memory to execute
an instruction, the operands may be read in any order. Similarly, when more than one result operand is written to memory to execute an instruction, the operands may be written
in any order.
formed in the order implied by the program. Refer to Section
3.1.3.2 for details.
It is also to be noted that the CPU does not check for dependencies between the fetching of an instruction and the
writing of previous instructions' results. Therefore, special
care is required when executing self-modifying code.
3.1.3.1 Branch Prediction
One problem inherent to all pipelined machines is what is
called '"Pipeline Breakage".
This occurs every time the sequentiality of the instructions is
broken, due to the execution of certain instructions or the
occurrence of exceptions.
The result of a pipeline breakage is a performance degradation, due to the fact that a certain portion of the pipeline
must be flushed and new data must be brought in.
The NS32532 provides a special mechanism, called branch
prediction, that helps minimize this performance penalty.
When a conditional branch instruction is decoded in the early stages of the pipeline, a prediction on the execution of the
instruction is performed.
More precisely, the prediction mechanism predicts backward branches as taken and forward branches as not taken,
except for the branch instructions BLE and BNE that are
always predicted as taken.
Thus, the resulting probability of correct prediction is fairly
high, especially for branch instructions placed at the end of
loops.
An instruction is fetched only after all previous instructions
have been completely fetched. However, the CPU may begin fetching an instruction before all of the source operands
have been read and results written for previous instructions.
The source operands for an instruction are read only after
all previous instructions have been fetched and their source
operands read. A source operand for an instruction may be
read before all results of previous instructions have been
written, except when the source operand's value depends
on a result not yet written. The CPU compares the physical
address and length of a source operand with those of any
results not yet written, and delays reading the source operand until after writing all results on which the source operand depends. Also, the CPU ensures that the interlocked
read and write references to execute an SBITli or CBITli
instruction occur after writing all results of previous instructions and before reading any source operands for subsequent instructions.
The sequence of operations performed by the loader and
execution units in the CPU is given below:
• Loader detects branches and calculates destination addresses
The result operands for an instruction are written after all
results of previous instructions have been written.
• Loader uses branch opcode and direction to select between sequential and non-sequential streams
The description above is summarized in Figure 3-3, which
shows the precedence of memory references for two consecutive instructions.
INSTRUCTION N
• Loader saves address for alternate stream
• Execution unit resolves branch decision
Due to the branch predicition, some special care is required
when writing self-modifying code. Refer to the appropriate
section in Appendix B for more information on this subject.
INSTRUCTION N+ 1
INSTRUCTION FETCH ~UCTION FETCH
\
~\WO
DATA WRITE
• ~"\'l
~
3.1.3.2 Memory-Mapped I/O
The characteristics of certain peripheral devices and the
overlapping of instruction execution in the pipeline of the
NS32532 require that special handling be applied to memory-mapped 110 references. 110 references differ from memory references in two significant ways, imposing the following requirements:
DATA WRITE
TLlEE/9354-10
FIGURE 3-3. Memory References for
Consecutive Instructions
(An arrow from one reference to another indicates that
the first reference always precedes the second.)
Another consequence of overlapping the operations for several instructions, is that the CPU may fetch an instruction
and read its source operands, even though the instruction is
not executed (e.g., due to the occurrence of an exception).
In such a case, the MMU may update the R-bit in Page
Table Entries used in referring to the fetched instruction and
its source operands.
1. Reading from a peripheral port can alter the value read
on the next reference to the same port or another port in
the same device. (A characteristic called here '"destructive-reading".) Serial communication controllers and
FIFO buffers commonly operate in this manner. As explained in '"Instruction Pipeline" above, the NS32532 can
read the source operands for one instruction while the
previous instruction is executing. Because the previous
instruction may cause a trap, an interrupt may be recognized, or the flow of control may be otherwise altered, it is
a requirement that destructive-reading of source operands before the execution of an instruction be avoided.
Special care is needed in the handling of memory-mapped
110 devices. The CPU provides special mechanisms to ensure that the references to these devices are always per-
2-28
z
3.0 Functional Description
en
Co)
(Continued)
N
2. Writing to a peripheral port can alter the value read from
another port of the same device. (A characteristic called
here "side-effects of writing"). For example, before reading the counter's value from the NS32202 Interrupt Control Unit it is first necessary to freeze the value by writing
to another control register.
serializing operation takes place. This is necessary since
the privilege level might have changed and the instructions
following the LPRW instruction must be fetched again with
the new privilege level and possibly with a different MMU
mapping. See Section 2.4.2.
The CPU serializes instruction execution after executing one
of the following instructions: BICPSRW, BISPSRW, BPT,
CINV, DIA, FLAG (trap taken), LMR, LPR (CFG, INTBASE,
PSR, UPSR, DCR, BPC, DSR, and CAR only), RETT, RETI,
and SVC. Figure 3-4 shows the memory references after
serialization.
However, as mentioned above, the NS32532 can read the
source operands for one instruction before writing the results of previous instructions unless the addresses indicate
a dependency between the read and write references. Consequently, it is a requirement that read and write references
to peripheral that exhibit side-effects of writing must occur in
the order dictated by the instructions.
Note 1: LPRB UPSR can be executed in User Mode to serialize instruction
execution.
Note 2: After an instruction that writes a result to memory is executed, the
updating of the result's memory location may be delayed until the
next serializing operation.
The NS32532 supports 2 methods for handling memorymapped 1/0. The first method is more general; it satisfies
both requirements listed above and places no restriction on
the location of memory-mapped peripheral devices. The
second method satisfies only the requirement for side effects of writing, and it restricts the location of memorymapped 1/0 devices, but it is more efficient for devices that
do not have destructive-read ports.
Note 3: When reset or a nonrestartable bus error exception occurs, the CPU
discards any results that have not yet been written to memory.
INSTRUCTION N
INSTRUCTION N+ 1
INSTRUCTION FETCH
INSTRUCTION rETCH
U1
Co)
N
I
N
o
......
Z
en
Co)
N
U1
Co)
N
I
N
U1
......
Z
en
Co)
N
U1
Co)
N
I
Co)
o
~R\ /~R\
The first method for handling memory-mapped 1/0 uses two
signals: 10lNH and 10DEC. When the NS32532 generates a
read bus cycle, it asserts the output signal 10lNH if either of
the 1/0 requirements listed above is not satisfied. That is,
10lNH is asserted during a read bus cycle when (1) the read
reference is for an instruction that may not be executed or
(2) the read reference occurs while a write reference is
pending for a previous instruction. When the read reference
is to a peripheral device that implements ports with destructive-reading or side-effects of writing, the input signal
10DEC must be asserted; in addition, the device must not
be selected if 10lNH is active. When the CPU detects that
the 10DEC input signal is active while the 10lNH output signal is also active, it discards the data read during the bus
cycle and serializes instruction execution. See the next section for details on serializing operations. The CPU then generates the read bus cycle again, this time satisfying the requirements for 1/0 and driving 10lNH inactive.
The second method for handling memory-mapped 1/0 uses
a dedicated region of virtual memory. The NS32532 treats
all references to the memory range from address FFOOOOOO
to address FFFFFFFF inclusive in a special manner.
DATA WRITE
DATA WRITE
TL/EE/93S4-11
FIGURE 3-4. Memory References after Serialization
3.1.4 Slave Processor Instructions
The NS32532 recognizes two groups of instructions being
executable by external slave processors:
• Floating Point Instructions
• Custom Slave Instructions
Each Slave Instruction Set is enabled by a bit in the Configuration Register (Section 2.1.4). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
Note that the Memory Management Instructions, like Floating Point and Custom Slave Instructions, have to be enabled through an appropriate bit in the configuration register
in order to be executable.
However, they are not considered here as Slave Instructions, since the NS32532 integrates the MMU on-chip and
the execution of them does not follow the protocol of the
Slave Instructions.
While a write to a location in this range is pending, reads
from locations in the same range are delayed. However,
reads from locations with addresses lower than FFOOOOOO
may occur. Similarly, reads from locations in the above
range may occur while writes to locations outside of the
range are pending.
It is to be noted that the CPU may assert 10lNH even when
the reference is within the dedicated region. Refer to Section 3.5.B for more information on the handling of 1/0 devices.
3.1.4.1 Regular Slave Instruction Protocol
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an ID Byte followed by an Operation Word. The ID Byte has three functions:
1) It identifies the instruction as being a Slave Processor
instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word
of the instruction.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-5. While applying
Status code 11111 (Broadcast ID Section 3.5.4.1), the CPU
transfers the ID Byte on bits AD24-AD31, the operation
3.1.3.3 Serializing Operations
After executing certain instructions or processing an exception, the CPU serializes instruction execution. Serializing instruction execution means that the CPU completes writing
all previous instructions' results to memory, then begins
fetching and executing the next instruction.
For example, when a new value is loaded into the PSR by
executing an LPRW instruction, the pipeline is flushed and a
2-29
•
I
C)
C?
C'I
C')
r---------------------------------------------------------------------------------,
3.0 Functional Description
(Continued)
Ln
C'I
~
Z
......
Ln
~
C'I
C')
Ln
C'I
~
......
Z
~
SEND OPERAND
(BUS STATUS = 11101)
~
Ln
C'I
C')
U)
z
READ RESULT
(BUS STATUS = 11101)
TUEE/9354-12
FIGURE 3-5. Regular Slave Instruction Protocol: CPU Actions
2-30
3.0 Functional Description (Continued)
o
31
IDBYTE
OPCODE (LOW)
OPCODE (HIGH)
XXXXXXXX
FIGURE 3-6. 10 and Operation Word
31
15
ZERO
TS
7
ZERO
N
Z
o
o
o
L
o
~I
FIGURE 3-7. Slave Processor Status Word
word on bits AD8-AD23 in a swapped order of bytes and a
non-used byte XXXXXXXX (X = don't care) on bits ADOAD? (Figure 3-6).
3.1.4.2 Pipelined Slave Instruction Protocol
In order to increase performance of floating-point instructions while maintaining full software compatibility with the
Series 32000 architecture, the NS32532 incorporates a
pipelined floating-point protocol. This protocol is deSigned
to operate in conjunction with the NS32580 FPC, or any
other floating·point slave which conforms to the protocol
and the Series 32000 architecture. The protocol is enabled
by the PF bit in the CFG register.
All slave processors observe the bus cycle and inspect the
identification code. The slave selected by the identification
code continues with the protocol; other slaves wait for the
next slave instruction to be broadcast.
After transferring the slave instruction, the CPU sends to the
slave any source operands that are located in memory or
the General-Purpose registers. The CPU then waits for the
slave to assert SDN or FSSR. While the CPU is waiting, it
can perform bus cycles to fetch instructions and read
source operands for instructions that follow the slave instruction being executed. If there are no bus cycles to perform, the CPU is idle with a special Status indicating that it is
waiting for a slave processor. After the slave asserts SDN or
FSSR, the CPU follows one of the two sequences described
below.
If the slave asserts SDN, then the CPU checks whether the
instruction stores any results to memory or the General-Purpose registers. The CPU reads any such results from the
slave by means of 1 or 2 bus cycles and updates the destination.
If the slave asserts FSSR, then the NS32532 reads a 32-bit
status word from the slave. The CPU checks bit 0 in the
slave's status word to determine whether to update the PSR
flags or to process an exception. Figure 3-7 shows the format of the slave's status word.
If the Q bit in the status word is 0, the CPU updates the N, Z
and L flags in the PSR.
If the Q bit in the status word is set to 1, the CPU processes
either a Trap (UND) if TS is 1 or a Trap (SLAVE) if TS is O.
The basic methods of transferring data and control information between the CPU and the FPC, are the same as in the
regular slave protocol.
However, in pipelined mode, the CPU may send a new floating-point instruction to the FPC before the previous instruction has been completed.
Although the CPU can advance as many as four floatingpoint instructions before receiving a completion pulse on
SDN for the first instruction, full exception recovery is assured. This is accomplished through a FIFO mechanism
which maintains the addresses of all the floating-point instructions sent to the FPC for execution.
Pipe lined execution can occur only for instructions which do
not require a result to be read from the FPC.
In cases where a result is to be read back, the CPU will wait
for instruction completion before issuing the next instruction. Instructions can be divided into three groups, depending on the amount of pipe lining permitted.
Group A. Fully-Pipelined Instructions
Instructions in this group can be sent to the FPC before
previous group A instructions are completed. No instruction
completion indication from the FPC is required in order to
continue to another group A or group B instruction.
Group A contains floating-point instructions satisfying all of
the following conditions.
1. The destination operand is in a floating-point register.
Note 1: Only the floating~point and custom compare instructions afe allowed
to return a value 01 0 lor the Q bit when the FSSR Signal is activat·
ed. All other instructions must always set the Q bit to 1 (to Signal a
Trap). when activating FSSR.
Note 2: While executing an LMR or CINV instruction, the CPU displays the
operation code and source operand using slave processor write bus
cycles, as described in the protocol above. Nevertheless. the CPU
does not wait lor SON or FSSR to be asserted while executing
these instructions. This information can be used to monitor the contents 01 the on-chip TLB, Instruction Cache, and Data Cache.
2. The source operand is not of type TOS or IMM.
3. The instruction format is either 11 or 12.
Group B. Half-Pipelined Instructions
Group B instructions can begin execution before previous
group A instructions are completed. However, they cannot
complete before the FPC signals completion of all the previous floating-point instructions.
Group B contains floating-point instructions satisfying at
least one of the following conditions.
1. The destination operand is either in memory or in a CPU
register (this includes the CMPf instruction which modifies
the PSR register).
Note 3: The slave processor must be ready to accept new slave instruction
at any time, even while the slave is executing another instruction or
waiting lor the CPU to read results. For example. the CPU may
terminate an instruction being executed by a slave because a nonrestartable bus error is detected while the MMU is updating a Page
Table Entry lor an instruction being preletched.
Note 4: II a slave instruction stores a result to memory, the CPU checks
whether Trap (ABn would occur on the store operation belore read·
ing the result from the slave. For quad-word destination operands,
the CPU checks that both double·words 01 the destination can be
stored without an abort before reading either double-word of the
result from the slave.
2. The source operand is of type TOS or IMM.
3. The instruction format is 9.
2-31
•
3.0 Functional Description
(Continued)
PROCESS TRAP.
GET
INSTRUCTION
ADDRESS
FROM FIFO
REMOVE
INSTRUCTION
ADDRESS
FROM FIFO
PROCESS TRAP.
GET
INSTRUCTION
ADDRESS
FROM FIFO
TL/EE/9354-73
FIGURE 3-8. Instruction Flow in Pipelined Floating·Point Mode
2-32
3.0 Functional Description
z
en
Co)
(Continued)
specifies a Floating Point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR-Bits-Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-7).
Group C. Non-Pipelined Instructions
Group C instructions can begin execution only after all other
instructions have been completed. The CPU cannot proceed to other instructions before their execution is completed.
Group C contains all the floating-point/integer conversion
instructions.
3.1.4.3 Instruction Flow and Exceptions
When operating in pipelined mode, the CPU will push the
address of group A instructions into a five-entry FIFO after
the ID, opcode and source operands have been sent to the
FPC. The address will be pushed into the FIFO only if no
exception is detected during the transfer of the source operands needed for the execution of the instruction.
Other exceptions may occur while the FIFO is not empty.
This may be the case when an interrupt is received or a
translation exception is detected in the access of an operand needed for the execution of the next floating-point instruction. These exceptions will be processed as soon as
the FIFO becomes empty, and after any floating-point exception has been acknowledged.
Exceptions are special events that alter the sequence of
instruction execution. The CPU recognizes three basic types
of exceptions: interrupts, traps and bus errors.
An interrupt occurs in response to an event signalled by
activating the NMI or INT input signals. Interrupts are typically requested by peripheral devices that require the CPU's
attention.
Traps occur as a result either of exceptional conditions
(e.g., attempted division by zero) or of specific instructions
whose purpose is to cause a trap to occur (e.g., supervisor
call instruction).
A bus error exception occurs when the BER signal is activated during an instruction fetch or data transfer required by
the CPU to execute an instruction.
When an exception is recognized, the CPU saves the PC,
PSR and optionally the MOD register contents on the interrupt stack and then it transfers control to an exception service procedure.
Details on the operations performed in the various cases by
the CPU to enter and exit the exception service procedure
are given in the following sections.
It is to be noted that the reset operation is not treated here
as an exception. Even though, like any exception, it alters
the instruction execution sequence.
3.1.4.4 Floating Point Instructions
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Instruction Set Reference Manual).
The Operand Issued columns show the sizes of the operands issued to the Floating Point Unit by the CPU. "D" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, D = Double Word). "f" indicates that the instruction
The reason being that the CPU handles reset in a significantly different way than it does for exceptions.
Refer to Section 3.5.3 for details on the reset operation.
2-33
Z
en
Co)
N
U1
Co)
N
U1
For the instruction encodings, see Appendix A.
Table 3-1 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
o
3.1.4.5 Custom Slave Instructions
3.2 EXCEPTION PROCESSING
In the event of a non-restartable bus error, the acknowledge
will occur immediately. The CPU will flush the internal FIFO
and will reset the FPC by performing a dummy read of the
slave status word. This operation is performed for both the
regular and pipe lined floating-point protocol and regardless
of whether any floating-point instruction is pending in the
FPC instruction queue.
The CPU may cancel the last instruction sent to the FPC by
sending another ID and opcode, before the last source operand for that instruction has been sent. Figure 3-8 shows
the instruction flow in pipelined floating-point mode.
N
I
N
-
Table 3-2 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
operand which can be a 32-bit ("D") or 64-bit ("Q") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type "c" will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
A floating-point exception may be received and serviced at
any time after the CPU has sent the ID and opcode for the
first instruction and until the FPC has signalled completion
for the last instruction.
Co)
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
Provided in the NS32532 is the capability of communicating
with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
Group A instructions are only stalled when the FIFO is full,
in which case the CPU will wait before sending the next
instruction. Group B instructions can begin execution while
some entries are still in the FIFO, but cannot complete before the FIFO is empty (Le., before all previous instructions
are completed). Group C instructions cannot begin execution until the FIFO is empty. When a normal completion indication is received, the instruction address at the bottom of
the FIFO is dropped. If a trap indication is received and the
FIFO is not empty, the instruction address at the bottom of
the FIFO is copied to the PC register and the floating-point
exception is serviced. The remaining entries in the FIFO are
discarded.
N
U1
N
I
N
U1
Z
en
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Co)
N
I
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(:)
C')
~
C')
3.0 Functional Description
an
(Continued)
TABLE 3-1. Floating Point Instruction Protocols
C'I
C')
en
Z
....
an
Mnemonic
C'I
C'I
ADDI
SUBI
MUll
DIVI
MOVI
ASSf
NEGf
CMPf
FLOORfi
TRUNCfi
ROUNDfi
MOVFL
MOVLF
MOVil
LFSR
SFSR
•
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an
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C')
en
....z
(:)
C'I
C'I
•
.C')
an
C'I
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en
z
Operand 1
Class
read.1
read.!
read.!
read.!
read.f
read.!
read.f
read.f
read.f
read.f
read.f
read.F
read.L
read.i
read.D
Operand 2
Class
rmw.!
rmw.!
rmw.!
rmw.!
write.f
write.f
write.!
read.!
write.i
write.i
write.i
write.L
write.F
write.!
Operand 1
Issued
I
N/A
f
F
L
i
0
N/A
write.D
N/A
Operand 2
Issued
I
N/A
N/A
N/A
Returned Value
Type and Dest •
ItoOp.2
ftoOp.2
Ito Op.2
ItoOp.2
ftoOp.2
ftoOp.2
ftoOp.2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
L toOp.2
FtoOp.2
ftoOp.2
N/A
DtoOp.2
PSR Bits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
TABLE 3-2. Custom Slave Instruction Protocols
Mnemonic
CCALOc
CCAL1c
CCAL2c
CCAL3c
CMOVOc
CMOV1c
CMOV2c
CMOV3c
CCMPOc
CCMP1c
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCVSQD
LCSR
SCSR
LCR·
SCR·
Operand 1
Class
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.i
read.D
read.Q
read.D
Operand 2
Class
rmw.c
rmw.c
rmw.c
rmw.c
write.c
write.c
write.c
write.c
read.c
read.c
write.i
write.i
write.i
write.c
write.Q
write.D
N/A
0
Q
0
N/A
write.D
N/A
read.D
write. 0
N/A
N/A
N/A
Operand 1
Issued
c
c
c
c
c
c
c
c
c
c
c
c
c
0
Note:
= Double Word
i = Integer size (B,W,D) specified in mnemonic.
o
c = Custom size (D:32 bits or Q:64 bits) specified in mnemonic.
• = Privileged instruction: will trap if CPU is in User Mode.
NI A = Not Applicable to this instruction.
2-34
Operand 2
Issued
c
c
c
c
N/A
N/A
N/A
N/A
Returned Value
Type and Dest.
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
c
c
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
i toOp.2
itoOp.2
itoOp.2
ctoOp.2
QtoOp.2
DtoOp.2
N/A
DtoOp.2
N/A
DtoOp.1
PSR Bits
Affected
none
none
none
none
none
none
none
none
N,Z,L
N,Z,L
none
none
none
none
none
none
none
none
none
none
z
(J)
3.0 Functional Description
(Continued)
3.2.1 Exception Acknowledge Sequence
reads the double-word entry from the Interrupt Dispatch table at address 'INTBASE + vector x 4'. See Figures 3-9
and 3-10. The CPU uses this entry to call the exception
service procedure, interpreting the entry as an external procedure descriptor.
A new module number is loaded into the MOD register from
the least-significant word of the descriptor, and the staticbase pointer for the new module is read from memory and
loaded into the SB register. Then the program-base pointer
for the new module is read from memory and added to the
most-significant word of the module descriptor, which is interpreted as an unsigned value. Finally, the result is loaded
into the PC register.
When an exception is recognized, the CPU goes through
three major steps:
1) Adjustment of Registers. Depending on the source of the
exception, the CPU may restore and/or adjust the contents of the Program Counter (PC), the Processor Status
Register (PSR) and the currently·selected Stack Pointer
(SP). A copy of the PSR is made, and the PSR is then set
to reflect Supervisor Mode and selection of the Interrupt
Stack. Trap (TRC) and Trap (OVF) are always disabled.
Maskable interrupts are also disabled if the exception is
caused by an interrupt, Trap (DBG), Trap (ABT) or bus
error.
2) Vector Acquisition. A vector is either obtained from the
data bus or is supplied internally by default.
3) Service Call. The CPU performs one of two sequences
common to all exceptions to complete the acknowledge
process and enter the appropriate service procedure.
The selection between the two sequences depends on
whether the Direct-Exception mode is disabled or enabled.
Direct-Exception Mode Enabled
The Direct-Exception mode is enabled when the DE bit in
the CFG register is set to 1. In this case the CPU first
pushes the saved PSR copy along with the contents of the
PC register on the Interrupt Stack. The word stored on the
Interrupt Stack between the saved PSR and PC register is
reserved for future use; its contents are undefined. The CPU
then reads the double-word entry from the Interrupt Dispatch Table at address 'INTBASE + vector x 4'. The CPU
uses this entry to call the exception service procedure, interpreting the entry as an absolute address that is simply loaded into the PC register. Figure 3-11 provides a pictorial of
the acknowledge sequence. It is to be noted that while the
Direct-Exception Mode Disabled
The Direct-Exception mode is disabled while the DE bit in
the CFG register is 0 (Section 2.1.4). In this case the CPU
first pushes the saved PSR copy along with the contents of
the MOD and PC registers on the interrupt stack. Then it
,.~
MEMORY
/
CASCADE TABLE
t
..
I"""""'..~I!
REGISTER
1
~
N
<:)
.......
Z
(J)
W
N
CJ1
W
N
I
N
CJ1
.......
Z
(J)
W
N
CJ1
W
~
W
<:)
rv
iiI'"
rIJ1
0
NVI
1
NMI
NON-MASKABLE INTERRUPT
2
ABT
ABORT
3
SLAVE
S LAVE PROCESSOR TRAP
4
ILL
I LLEGAL OPERATION TRAP
5
SVC
S UPERVISOR CALL TRAP
6
DVZ
DIVIDE BY ZERO TRAP
7
FLG
FLAG TRAP
8
BPT
BREAKPOINT TRAP
9
TRC
T RACE TRAP
10
UNO
UNDEFINED INSTRUCTION TRAP
11
RBE
RESTARTABLE BUS ERROR
12
NBE
NON-RESTARTABLE BUS ERROR
13
DVF
I NTEGER OVERFLOW TRAP
14
DBG
DEBUG TRAP
15
RESERVED
CASCADE ADDR 0
~
W
N
CJ1
W
NON-VECTORED INTERRUPT
~~
0
CASCADE ADDR 14
CASCADE ADDR 15
FIXED INTERRUPTS
ANOTRAPS
VECTORED
INTERRUPTS
I
DISPATCH TABLE
l:
16
VECTORED
INTERRUPTS
r~
r'"
TLlEE/9354-13
FIGURE 3·9. Interrupt Dispatch Table
2-35
FII
CI
~
C')
3.0 Functional Description
(Continued)
In
~
U)
Z
.....
In
1--32BITS-
N
N
C')
In
N
C')
U)
Z
.....
CI
~
I
I
I (PUSH)
RETURN ADDRESS
PC
I
STATUS
I
I
MODULE
PSR
LOWER
ADDRESSES
I(PUSH)
I
PSR
MOD
MOD
INTERRUPT
STACK
C')
In
N
HIGHER
ADDRESSES
C')
TL/EE/9354-14
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DESCRIPTOR (32 BITS)
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DESCRIPTOR
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OFFSET
MODULE
0
MOD REGISTER ~
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MODULE TABLE
NEW MODULE
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MODULE TABLE ENTRY
J
MODULE TiBlE ENTRY
32
- ----.,
STATIC BASE POINTER
UNK BASE POINTER
+
PROGRAM BASE POINTER
(RESERVED)
SBREGISTER
PROGRAM COUNTER
I
4-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3·10. Exception Acknowledge Sequence.
Direct·Exceptlon Mode Disabled.
2-36
I
Tl/EE/9354-15
z
3.0 Functional Description
~
N
(Continued)
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32 BITS
Co)
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(PUSH)
RETURN ADDRESS
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PC
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STATUS
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DISPATCH
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ABSOLUTE ADDRESS
)
PROGRAM COUNTER
ENTRY POINT ADDRESS
J
TL/EE/9354-17
FIGURE 3-11. Exception Acknowledge Sequence.
Direct-Exception Mode Enabled.
direct-exception mode is enabled, the CPU can respond
more quickly to interrupts and other exceptions because
fewer memory references are required to process an exception. The MOD and SB registers, however, are not initialized
before the CPU transfers control to the service procedure.
Consequently, the service procedure is restricted from executing any instructions, such as CXP, that use the contents
of the MOD or SB registers in effective address calculations.
mode procedures, RETT can also adjust the Stack Pointer
(SP) to discard a specified number of bytes from the original
stack as surplus parameter space.
RETI is used to return from a maskable interrupt service
procedure. A difference of RETT, RETI also informs any
external interrupt control units that interrupt service has
completed. Since interrupts are generally asynchronous external events, RETI does not discard parameters from the
stack.
Both of the above instructions always restore the Program
Counter (PC) and the Processor Status Register from the
interrupt stack. If the Direct-Exception mode is disabled,
they also restore the MOD and SB register contents. Figures 3-12 and 3-13 show the RETT and RETI instruction
flows when the Direct-Exception mode is disabled.
3.2.2 Returning from an Exception Service Procedure
To return control to an interrupted program, one of two instructions can be used: RETT (Return from Trap) and RETI
(Return from Interrupt).
RETT is used to return from any trap, non-maskable interrupt or bus error service procedure. Since some traps are
often used deliberately as a call mechanism for supervisor
2-37
•
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3.0 Functional Description
(Continued)
N
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PROGRAM COUNTER
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I
RETURN ADDRESS
STATUS
PSR
I
MODULE
MOD
·1
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(POP)
- - - - - - - - - i r - - P SR
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INTERRUPT
HIGHER
ADDRESSES
STACK
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MODULE
TABLE
MODULE TABLE ENTRY
MODULE
T~BLE
ENTRY
STATIC BASE POINTER
-h
LINK BASE POINTER
LOWER
ADDRESSES
PROGRAM BASE POINTER
(RESERVED)
PARAMETERS
/
n
BYTES
SBREGISTER
STATIC BASE
STACK SELECTED
IN NEWLY·
POPPEDPSR.
HIGHER
ADDRESSES
POP AND
DISCARD
TL/EE/9354-18
FIGURE 3-12. Return from Trap (RETT n) Instruction Flow.
Direct-Exception Mode Disabled.
3,2.3 Maskable Interrupts
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests. The input is maskable, and is therefore enabled to generate interrupt requests only while the Processor Status Register I bit
is set. The I bit is automatically cleared during service of an
INT, NMI, Trap (DBG), Trap (ABT) or Bus Error request, and
is restored to its original setting upon return from the interrupt service routine via the RETT or RETI instruction.
3.2.3.2 Vectored Mode: Non-Cascaded Case
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize many interrupt requests. Upon receipt
of an interrupt request on the INT pin, the CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Section
3.5.4.6) reading a vector value from the low-order byte of
the Data Bus. This vector is then used as an index into the
Dispatch Table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI) instruction, which performs an End of Interrupt
bus cycle, informing the ICU that it may re-prioritize any interrupt requests still pending. The ICU provides the vector
number again, which the CPU uses to determine whether it
needs also to inform a Cascaded ICU (see below).
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I = 0) or Vectored (bit I = 1).
3,2,3.1 Non-Vectored Mode
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
2-38
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3.0 Functional Description
en
IN
(Continued)
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IN
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.......
"END OF INTERRUPT"
z
en
BUS CYCLE
IN
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U1
IN
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.......
INTERRUPT
CONTROL
UNIT
z
en
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U1
IN
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PROGRAM COUNTER
I
LOWER
ADDRESSES
IN
o
(POP)
RETURN ADDRESS
STATUS
1
MODULE
PSR
PC
(POP)
-t-----------+PSR
I
MOD
MOD
INTERRUPT
STACK
HIGHER
ADDRESSES
MODULE
TABLE
MODULE TABLE ENTRY
•
MOOULE TABLE ENTRY
STATIC BASE POINTER
-r-------
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STATIC BASE
SBREGISTER
TL/EE/9354-19
FIGURE 3-13. Return from Interrupt (RETI) Instruction Flow.
Direct-Exception Mode Disabled.
2·39
3.0 Functional Description
(Continued)
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
3.5.4.6) when processing of this interrupt actually begins.
The Interrupt Acknowledge cycle differs from that provided
for Maskable Interrupts in that the address presented is
FFFFFFOOI6. The vector value used for the Non-Maskable
Interrupt is taken as 1, regardless of the value read from the
bus.
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETI) instruction. No
special bus cycles occur on return.
3.2.3.3 Vectored Mode: Cascaded Case
In order to allow more levels of interrupt, provision is made
in the CPU to transparently support cascading. Note that
the Interrupt output from a Cascaded ICU goes to an Inter·
rupt Request input of the Master ICU, which is the only ICU
which drives the CPU INT pin. Refer to the ICU data sheet
for details.
3.2.5 Traps
In a system which uses cascading, two tasks must be per·
formed upon initialization:
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number on which it receives
the cascaded requests.
Traps are processing exceptions that are generated as di·
rect results of the execution of an instruction.
The return address saved on the stack by any trap except
Trap (TRC) and Trap (DBG) is the address of the first bye of
the instruction during which the trap occurred.
2) A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (INT·
BASE) Register. Its entries are 32·bit addresses, pointing
to the Vector Registers of each of up to 16 Cascaded
ICUs.
Figure 3·9 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32-bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
When a trap is recognized, maskable interrupts are not disabled except for the case of Trap (ABT) and Trap (DBG).
There are 11 trap conditions recognized by the NS32532 as
described below.
Trap (ABT): An abort trap occurs when an invalid page table entry or a protection level violation is detected for any of
the memory references required to execute an instruction.
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Section 3.1.4.1).
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle,
reading the final vector value. This vector is interpreted by
the CPU as an unsigned byte, and can therefore be in the
range of 0 through 255.
Trap (SVC): The Supervisor Call (SVC) instruction was executed.
Trap (OVZ): An attempt was made to divide an integer by
zero. (The FPU trap is used for Floating Point division by
zero.)
Trap (FLG): The FLAG instruction detected a "1" in the
PSR F bit.
Trap (BPT): The Breakpoint (BPT) instruction was executed.
Trap (TRC): The instruction just completed is being traced.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle, whereupon the
Master ICU again provides the negative Cascade Table index. The CPU, seeing a negative value, uses it to find the
corresponding Cascade Address from the Cascade Table.
Applying this address, it performs an "End of Interrupt, Cas·
caded" bus cycle, informing the Cascaded ICU of the com·
pletion of the service routine. The byte read from the Cascaded ICU is discarded.
Refer to Section 3.3.1 for details.
Trap (UNO): An Undefined-Instruction trap occurs when an
attempt to execute an instruction is made and one or more
of the following conditions is detected:
the INT line before the ICU deasserted it. This could cause the ICU to
provide an invalid vector. To avoid this problem the above operation
should be performed with the CPU interrupt disabled.
1. The instruction is undefined. Refer to Appendix A for a
description of the codes that the CPU recognizes to be
undefined.
2. The instruction is a floating point instruction and the F-bit
in the CFG register is O.
3. The instruction is a custom slave instruction and the C-bit
in the CFG register is O.
4. The instruction is a memory·management instruction and
the M-bit in the CFG register is O.
5. An LMR or SMR instruction is executed while the U-flag
in the PSR is 0 and the most significant bit of the instruc·
tion's short field is O.
3.2.4 Non-Maskable Interrupt
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Section
6. The reserved general adressing mode encoding (10011)
is used.
7. Immediate addressing mode is used for an operand that
has access class different from read.
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit in the interrupt mask register of the interrupt con·
troller.
However, if an interrupt is set pending during the CPU instruction that
masks off that interrupt, the CPU may still perform an interrupt acknowledge cycle following that instruction since it might have sampled
2-40
z
en
w
3.0 Functional Description (Continued)
8. Scaled Indexing is used and the base mode is also Scaled
Indexing.
9. The instruction is a floating-point or custom slave instruction that the FPU or custom slave detects to be undefined. Refer to Section 3.1.4.1 for more information.
Trap (OVF): An Integer-Overflow trap occurs when the V-bit
in the PSR register is set to 1 and an Integer-Overflow condition is detected during the execution of an instruction. An
Integer-Overflow condition is detected in the following cases:
1. The F-flag is 1 following execution of an ADDi, ADDQi,
ADDCi, SUBi, SUBCi, NEGi, ABSi, or CHECKi instruction.
Trap (DBG) for external condition, are eliminated. The PC
value saved on the stack is undefined.
The NS32532 does not respond to bus errors indicated for
instructions that are not executed. For example, no bus error exception occurs in response to asserting the BER signal during a bus cycle to prefetch an instruction that is not
executed because the previous instruction caused a trap.
An exception to this rule occurs if the bus error is detected
during an MMU write cycle to update the R-bit in a page
table entry.
In this case the CPU recognizes the bus error and considers
it as non-restartable even though the bus cycle that caused
it belongs to a non-executed instruction.
If a bus error is detected during a data transfer required for
the processing of another exception or during the ICU read
cycle of a RETI instruction, then the CPU considers it as a
fatal bus error and enters the 'HALTED' state.
2. The product resulting from a MULi instruction cannot be
represented exactly in the destination operand's location.
3. The quotient resulting from a DEli, DIVi, or QUOi instruction cannot be represented exactly in the destination operand's location.
4. The result of an ASHi instruction cannot be represented
exactly in the destination operand's location.
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Note 1: If the address and control signals associated with the last bus cycle
that caused a bus error are latched by external hardware, then the
information they provide can be used by the service procedure for
restartable bus errors to analyze and resolve the exception recog-
5. The sum of the 'INC' value and the 'INDEX' operand for
an ACBi instruction cannot be represented exactly in the
index operand's location.
Trap (DBG): A debug trap occurs when one or more of the
conditions selected by the settings of the bits in the DCR
register is detected. This trap can also be requested by activating the input signal DBG. Refer to Section 3.3.2 for more
information.
nized by the CPU. This can be accomplished because upon detecting a restartable bus error, the NS32532 stops making memory references for subsequent instructions until it determines whether the
instruction that caused the bus error is executed and the exception
is processed.
Note 2: When a non-restartable bus error is recognized, the service procedure must execute the CINV and LMR instructions to invalidate the
on-chip caches and TLB. This is necessary to maintain coherence
between them and external memory.
Note 1: Following execution of the WAIT instruction, then a Trap (DBG) can
3.2.7 Priority Among Exceptions
be pending for a PC-match condition. In such an event, the Trap
(OBG) is processed immediately.
The CPU checks for specific exceptions at various points
while executing an instruction. It is possible that several exceptions occur simultaneously. In that event, the CPU responds to the exception with highest priority.
Figure 3-14 shows an exception processing flowchart. A
non-restartable bus error is assigned highest priority and is
serviced immediately regardless of the execution state of
the CPU.
Before executing an instruction, the CPU checks for pending Trap (DBG), interrupts, and Trap (TRG), in that order. If a
Trap (DBG) is pending, then the CPU processes that exception, otherwise the CPU checks for pending interrupts. At
this pOint, the CPU responds to any pending interrupt requests; nonmaskable interrupts are recongized with higher
priority than maskable interrupts. If no interrupts are pending, then the CPU checks the P-flag in the PSR to determine
whether a Trap (TRC) is pending. If the P-flag is 1, a Trap
(TRG) is processed. If no Trap (DBG), interrupt or Trap
(TRG) is pending, the CPU begins executing the instruction.
Note 2: If an attempt is made to execute a memory-management instruction
while in User·Mode and the M·bit in the CFG register is 0, then Trap
(UNO) occurs.
Note 3: If an attempt is made to execute a privileged custom instruction
while in User-Mode and the C-bit in the CFG register is 0, then Trap
(UNO) occurs.
Note 4: While operating in User-Mode, if an attempt is made to execute a
privileged instruction with an undefined use of a general addressing
mode (either the reserved encoding is used or else scaled-index or
immediate modes are incorrectly used), the Trap (UND) occurs.
Note 5: If an undefined instruction or illegal operation is detected, then no
data references are performed for the instruction.
Note 6: For certain instructions that Bre relatively long to execute, such as
OEIO, the CPU checks for pending interrupts during execution of the
instruction. In order to reduce interrupt latency, the NS2532 can
suspend executing the instruction and process the interrupt. Refer
to Section 8.5 in Appendix B for more informa~ion about recognizing
interrupts in this manner.
3.2.6 Bus Errors
A bus error exception occurs when the BER signal is asserted in response to an instruction fetch or data transfer that is
required to execute an instruction.
While executing an instruction, the CPU may recognize up
to four exceptions:
1. trap (ABT)
Two types of bus errors are recognized: Restartable and
Non-Restartable. Restartable bus errors are recognized during read bus cycles, except for MMU read cycles (from Page
Tables) needed to translate the address of a result being
stored into memory. All other bus errors are non-restartable.
The CPU responds to restartable bus errors by suspending
the instruction that it was executing. When a non-restartable
bus error is detected, the CPU responds immediately and
the instruction being executed is terminated.
In this case, any results that have not yet been written to
memory are discarded, and any pending traps other than
2. restartable bus error
3. trap (DBG) or interrupt, if the instruction is interruptible
4. one of 7 mutually exclusive traps: SLAVE, ILL, SVC, DVZ,
FLG, BPT, UND
Trap (ABT) and restartable bus error have equal priority; the
CPU responds to the first one detected.
If no exception is detected while the instruction is executing,
then the instruction is completed and the PC is updated to
point to the next instruction. If a Trap (OVF) is detected,
then it is processed at this time.
2-41
•
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3.0 Functional Description
(Continued)
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TLfEEf9354-20
FIGURE 3-14. Exception Processing Flowchart
2·42
3.0 Functional Description
(Continued)
While executing the instruction, the CPU checks for enabled
debug conditions. If an enabled debug condition is met, a
Trap (DBG) is held pending until after the instruction is completed (see Note 3). If another exception is detected before
the instruction is completed, the pending Trap (DBG) is removed and the DSR register is not updated.
7. If "Byte" is in the range -16 through -1, then the interrupt source is Cascaded. (More negative values are reserved for future use.) Perform the following:
a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE + 4* Byte.
b. Read "Vector," applying the Cascade Address just
read and Status Code 00101 (Interrupt Acknowledge,
Cascaded).
8. Perform Service (Vector, Return Address), Figure 3-15.
Note 1: Trap (DBG) can be detected simultaneously with Trap (OVF). In this
event, the Trap (OVF) is processed before the Trap (DBG).
Note 2: An address-compare debug condition can be detected while processing a bus error, interrupt, or trap. In this event, the Trap (DBG)
is held pending until after the CPU has processed the first excep-
3.2.8.2 AbortlRestartable Bus Error Sequence
tion.
1. Suspend instruction and restore the currently selected
Stack Pointer to its original contents at the beginning of
the instruction.
2. Clear the PSR P bit.
3. Copy the PSR into a temmporary register, then clear PSR
bits T, V, U, S and I.
4. Set "Vector" to the value corresponding to the exception
type:
Abort:
Vector = 2
Restartable Bus Error: Vector = 11
Note 3: Between operations of a string instruction. the CPU responds to
pending operand address compare and external debug conditions
as well as interrupts. If a PC-match debug condition is detected
while executing a string instruction, then Trap (DBG) is held pending
until the instruction has completed.
3.2.8 Exception Acknowledge Sequences: Detailed Flow
For purposes of the following detailed discussion of exception acknowledge sequences, a single sequence called
"service" is defined in Figure 3-15.
Upon detecting any interrupt request, trap or bus error condition, the CPU first performs a sequence dependent upon
the type of exception. This sequence will include saving a
copy of the Processor Status Register and establishing a
vector and a return address. The CPU then performs the
service sequence.
5. Set "Return Address" to the address of the first byte of
the suspended instruction.
6. Perform Service (Vector, Return Address), Figure 3-15.
3.2.8.3 SLAVE/ILL/SVC/DVZ/FLG/BPTlUND Trap
Sequence
3.2.8.1 Maskable/Non-Maskable Interrupt Sequence
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of an interruptible instruction (e.g., string instruction), at the next interruptible point during its execution.
1. If an interruptible instruction was interrupted and not yet
completed:
a. Clear the Processor Status Register P bit.
b. Set "Return Address" to the address of the first byte of
the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
3. If the interrupt is Non-Maskable:
1. Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2. Set "Vector" to the value corresponding to the trap type.
SLAVE: Vector = 3.
ILL:
Vector = 4.
SVC:
Vector = 5.
DVZ:
Vector = 6.
FLG:
Vector = 7.
BPT:
Vector = 8.
UND:
Vector = 10.
3. If Trap (ILL) or Trap (UND)
a. Clear the Processor Status Register P bit.
4. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, Sand P.
5. Set "Return Address" to the address of the first byte of
the trapped instruction.
6. Perform Service (Vector, Return Address), Figure 3-15.
a. Read a byte from address FFFFFF0016, applying
Status Code 00100 (Interrupt Acknowledge, Master).
Discard the byte read.
b. Set "Vector" to 1.
c. Go to Step 8.
4. If the interrupt is Non-Vectored:
3.2.8.4 Trace Trap Sequence
1. In the Processor Status Register (PSR), clear the P bit.
2. Copy the PSR into a temporary register, then clear PSR
bits T, V, U and S.
3. Set "Vector" to 9.
a. Read a byte from address FFFFFE0016, applying
Status Code 00100 (Interrupt Acknowledge, Master).
Discard the byte read.
4. Set "Return Address" to the address of the next instruction.
5. Perform Service (Vector, Return Address), Figure 3-15.
b. Set "Vector" to O.
c. Go to Step 8.
5. Here the interrupt is Vectored. Read "Byte" from address
3.2.8.5 Integer-Overflow Trap Sequence
FFFFFE0016, applying Status Code 00100 (Interrupt Acknowledge, Master).
1. Copy the PSR into a temporary register, then clear PSR
bits T, V, U, Sand P.
6. If "Byte" ;;, 0, then set "Vector" to "Byte" and go to Step
2. Set "Vector" to 13.
8.
2-43
C)
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r---------------------------------------------------------------------------------,
~
3.0 Functional Description (Continued)
C'II
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3. Set "Return Address" to the address of the next instruction.
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4. Perform Service (Vector, Return Address), Figure 3-15.
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1. If PC-match condition, then go to Step 3.
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Besides the Breakpoint (BPT) instruction that can be used
to generate soft breaks, the CPU also provides instruction
tracing as well as debug trap (or hardware breakpoints) capabilities. Details on these features are provided in the following sub-sections.
3.2.8.6 Debug Trap Sequence
2. If a String instruction was interrupted and not yet completed:
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The NS32532 provides serveral features to assist in program debugging.
A debug condition can be recognized either at the next instruction boundary or, in the case of the String instructions,
at the next interruptible point during its execution.
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3.3 DEBUGGING SUPPORT
3.3.1 Instruction Tracing
Instruction tracing is a very useful feature that can be used
during debugging to single-step through selected portions of
a program. Tracing is enabled by setting the T -bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRC) after the execution of each instruction.
a. Clear the Processor Status Register P bit.
b. Set "Return Address" to the address of the first byte of
the instruction.
c. Go to Step 4.
At the beginning of each instruction, the T bit is copied into
the PSR P (Trace "Pending") bit. If the P bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced instruction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap sequence handles the P bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
3. Set "Return Address" to the address of the next instruction.
4. Set "Vector" to 14.
5. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
6. Perform Service (Vector, Return Address), Figure 3-15.
3.2.8.7 Non-Restartable Bus Error Sequence
1. Set "Vector" to 12.
Due to the fact that some instructions can clear the T and P
bits in the PSR, in some cases a Trace Trap may not occur
at the end of the instruction. This happens when one of the
privileged instructions BICPSRW or LPRW PSR is executed.
2. Set "Return Address" to "Undefined".
3. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
4. Perform a dummy read of the Slave Status Word to reset
the Slave Processor.
5. Perform Service (Vector, Return Address), Figure 3-15.
TABLE 3-3. Summary of Exception Processing
Instruction
Ending
Cleared Before
SavingPSR
Cleared After
SavingPSR
Suspended
Terminated
P
Undefined
TVUSI
TVUSPI
Interrupt
Before Instruction
None/P·
TVUSPI
ABT
ILL, UND
SLAVE,SVC, DVZ, FLG,BPT
OVF
TRC
DBG
Suspended
Suspended
Suspended
Completed
Before Instruction
Before Instruction
P
P
None
None
P
None/P·
TVUSI
TVUS
TVUSP
TVUSP
TVUS
TVUSPI
Exception
Restartable Bus Error
Nonrestartable Bus Error
..
*Nate: The P bit of the saved PSR IS cleared In case the exception IS acknowledged before the Instruction IS completed (e.g., Interrupted stnng instruction). ThiS IS
to avoid a mid-instruction trace trap upon return from the Exception Service Routine.
Service (Vector, Return Address):
1) Push the PSR copy onto the Interrupt Stack as a 16-blt value.
2) If Direct-Exception mode Is selected, then go to step 4.
3) Push MOD Register Into the Interrupt Stack as a lB-blt value.
4) Read 32·blt Interrupt Dispatch Table (lOT) entry at address 'INTBASE
+
vector x 4'.
5) If Dlrect·Exceptlon mode Is selected, then go to Step 10.
6) Move the LS. word of the lOT entry (Module Field) Into the MOD register.
7) Read the Program Base pOinter from memory address 'MOD
Program Counter.
+ 8', and add to It the M.S. word of the lOT entry (Offset Field), placing the result In the
8) Read the new Static Base pOinter from the memory address contained In MOD, placing it into the SB Register.
9) Go to Step 11.
10) Place lOT entry in the Program Counter.
11) Push the Return Address onto the Interrupt Stack as a 32-blt quantity.
12) Serialize: Non·sequentially fetch first Instruction of Exception Service Routine.
Note: Some of the Memory Accesses indicated in the service sequence may be performed in an order different from the one shown.
FIGURE 3-15. Service Sequence
2-44
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3.0 Functional Description
(0)
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(Continued)
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that special care is taken before returning from the Trace Trap Service Procedure. In case a BICPSRB instruction has been executed, the service procedure should make sure that the T
bit in the PSR copy saved on the Interrupt Stack is set before executing the RETT instruction to return to the program
begin traced. If the RETT or RETI instructions have to be
traced, the Trace Trap Service Procedure should set the P
and T bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
Iy with PFS. If the instruction is not completed because a
higher priority trap (I.e., ABORT) is detected, the BP signal
mayor may not be asserted.
Note 1: While executing the MOVUS and MOVSU instructions, the campare-address condition is enabled for the User space memory reference under control of the UD-bit in the DCA.
Note 2: When the LPRi instruction is executed to load a new value into the
BPC. CAR or OCR, it is undefined whether the address-compare
and PC-match conditions, in effect while executing the instruction,
are detected under control of the old or new contents of the loaded
register. Therefore, any LPRi instruction that alters the control of the
address·compare or PC·match conditions should use register or im·
mediate addressing mode for the source operand.
Note: If instruction tracing is enabled while the WAIT instruction is executed,
the Trap (fRC) occurs after the next interrupt, when the interrupt
3.4 ON-CHIP CACHES
service procedure has returned.
The NS32532 provides three on-chip caches: the Instruction Cache (IC), the Data Cache (DC) and the Translation
Look-aside Buffer (TLB).
3.3.2 Debug Trap Capability
The CPU recognizes three different conditions to generate a
Debug Trap:
The first two are used to hold the contents of frequently
used memory locations, while the TLB holds address-translation information.
The IC and DC can be individually enabled by setting appropriate bits in the CFG Register (See Section 2.1.4); the TLB
is automatically enabled when address-translation is enabled.
The CPU also provides a locking feature that allows the
contents of the IC and DC to be locked to specific memory
locations. This is accomplished by setting the LlC and LDC
bits in the CFG register.
1) Address Compare
2) PC Match
3) External
These conditions can be enabled and monitored through
the CPU Debug Registers.
An address-compare condition is detected when certain
memory locations are either read or written. The doubleword address used for the comparison is specified in the
CAR Register. The address-compare condition can be separately enabled for each of the bytes in the specified double-word, under control of the CBE bits of the DCR Register.
The VNP bit in the DCR controls whether virtual or physical
addresses are compared. The CRD and CWR bits in the
DCR separately enable the address compare condition for
read and write references; the CAE bit in the DCR can be
used to disable the compare-address condition independently from the other control bits. The CPU examines the
address compare condition for all data reads and writes,
reads of memory locations for effective address calculations, Interrupt-Acknowledge and End-of-Interrupt bus cycles, and memory references for exception processing. An
address-compare condition is not detected for MMU references to Page Table Entries.
Cache locking can be successfully used in real-time applications to guarantee fast access to critical instruction and data
areas.
Details on the organization and function of each of the
caches are provided in the following sections.
Note: The size and organization of the on-Chip caches may change in future
Series 32000 microprocessors. This however, will not affect software
compatibility.
3.4.1 Instruction Cache (IC)
The basic structure of the instruction cache (IC) is shown in
Figure 3-16.
The IC stores 512 bytes of code in a direct-mapped organization with 32 sets. Direct-mapped means that each set
contains only one block, thus each memory location can be
loaded into the IC in only one place.
The PC-match condition is detected when the address of
the instruction equals the value specified in the BPC register. The PC-match condition is enabled by the PCE bit in the
DCR.
Detection of address-compare and PC-match conditions is
enabled for User and Supervisor Modes by the UD and SD
bits in the DCR. The DEN-bit can be used to disable detection of these two conditions independently from the other
control bits.
An external condition is recognized whenever the DBG signal is activated.
When the CPU detects an address-compare or PC-match
condition while executing an instruction or processing an
exception, then Trap (DBG) occurs if the TR bit in the DCR
is 1. When an external debug condition is detected, Trap
(DBG) occurs regardless of the TR bit. The cause of the
Trap (DBG) is indicated in the DSR Register.
Each block contains a 23-bit tag, which holds the most-significant bits of the physical address for the locations stored
in the block, along with 4 double-words and 4 validity bits
(one for each double-word).
A 4-double-word instruction buffer is also provided, which is
loaded either from a selected cache block or from external
memory. Instructions are read from this buffer by the loader
unit and transferred to an 8-byte instruction queue.
The IC mayor may not be enabled to cache an instruction
being fetched by the CPU. It is enabled when the IC bit in
the CFG Register is set to 1 and either the address translation is disabled or the CI bit in the Level-2 PTE used to
translate the virtual address of the instruction is set to o.
If the IC is disabled, the CPU bypasses it during the instruction fetch and its contents are not affected. The instruction
is read directly from external memory into the instruction
buffer.
When an address-compare or PC-match condition is detected while executing an instruction, the CPU asserts the BP
signal at the beginning of the next instruction, synchronous-
2-45
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3.0 Functional Description (Continued)
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MEMORY
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INSTRUCTION
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INSTRUCTION AOORESS
INSTRUCTION OOUBLE-WORD
TL/EE/9354-21
FIGURE 3-16. Instruction Cache Structure
When the IC is enabled, the instruction address bits 4 to 8
are used to select the IC set where the instruction may be
stored. The tag corresponding to the single block in the set
is compared with the 23 most-significant bits of the instruction's physical address. The 4 double-words in this block are
loaded into the instruction buffer and the 4 validity bits are
also retrieved. Bits 2 and 3 of the instruction's physical address select one of these double-words and the associated
validity bit.
3.4.2 Data Cache (DC)
The Data Cache (DC) stores 1,024 bytes of data in a twoway set associative organization as shown in Figure 3-17.
Each of the 32 sets has 2 cache blocks. Each block contains a 23-bit tag, which holds the most-significant bits of
the physical address for the locations stored in the block,
along with 4 double-words and 4 validity bits (one for each
double-word).
The DC is enabled for a data read when all of the following
conditions are satisfied.
• The DC bit in the CFG Register is set to 1.
If the tag matches and the selected double-word is valid, a
cache 'hit' occurs and the double-word is directly transferred to the instruction queue for decoding; otherwise a
cache 'miss' will result.
• Either the address translation is disabled or the CI bit in
the Level-2 PTE used to translate the virtual address of
the data reference is set to O.
In the latter case, if the cache is not locked, the CPU will
take the following actions.
• The reference is not an interlocked read resulting from
executing a CBITI or SBITI instruction.
If the DC is disabled, the CPU bypasses it during the data
read and its contents are not affected. The data is read
directly from external memory. The DC is also bypassed for
MMU reads from Page Table entries during address translation and for Interrupt-Acknowledge and End-of-Interrupt bus
cycles.
When the DC is enabled for a data read, the address bits 4
to 8 are used to select the DC set where the data may be
stored.
The tags corresponding to the two blocks in the set are
compared to the 23 most-significant bits of the phYSical address. Bits 2 and 3 of the address select one double-word in
each block and the associated validity bit.
First, if the tag of the selected block does not match, the tag
is loaded with the 23 most-significant bits of the instruction
address and all the validity bits are cleared. Then, the instruction is read from external memory into the instruction
buffer.
If the CII N input signal is not active during the fetching of the
missing instruction, then the IC is updated and the instruction double-words fetched from memory are stored into it
with the validity bits set.
If the cache is locked, its contents are not affected, as the
CPU reads the missing instruction from external memory.
Whenever the CPU accesses external memory, whether or
not the IC is enabled, it always fetches instruction double·
words in a non-wrap-around fashion. Refer to Sections
3.5.4.3 and 3.5.6 for more information.
If one of the tag matches and the selected double-word in
the corresponding block is valid, a cache 'hit' occurs and
the data is used to execute the instruction; otherwise a
cache 'miss' will result. In the latter case, if the cache is not
locked, the CPU will take the following actions.
The contents of the instruction cache can be invalidated by
software through the CINV instruction or by hardware
through the appropriate cache invalidation input signals.
Clearing the IC bit in the CFG Register also invaiidates the
instruction cache. Refer to Sections 3.5.10 and C.3 for details.
Note: If the IC is enabled for a certain Inslruction and a 'miss' occurs due 10
a tag mismalch, the CPU will updale the tag and clear all the validity
bHs before fetching the Instruction from external memory. If the CIIN
Input signal is activated during the fetching of that instruction, the
validity bits are not set and the IC is not updated.
2-46
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3.0 Functional Description
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(Continued)
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DATA ADDRESS
DATA
TL/EE/9354-22
FIGURE 3-17. Data Cache Structure
First, if the tag of either block in the set matches the data
address, that block is selected for updating. Otherwise, if
neither tag matches, then the least recently used block is
selected; its tag is loaded with the 23 most-significant bits of
the data address, and all the validity bits are cleared.
ory. In software, the use of caches can be inhibited for individual pages using the CI-bit in the level-2 Page Table Entries. The CINV instruction can be executed to invalidate
entriely the Instruction Cache and/or Data Cache; the CINV
instruction can also be executed to invalidate a single
16-byte block in either or both caches.
Then, the data is read from external memory; up to 4 double-word bits are read into the cache in a wrap-around fashion. Refer to Sections 3.5.4.3 and 3.5.6 for more information.
If the CIIN and IODEC input signals are both inactive during
the bus cycles performed to read the missing data, then the
DC is updated, as each double-word is read from memory,
and the corresponding validity bit is set. If the cache is
locked, its contents are not affected, as the CPU reads the
missing data from external memory.
In hardware, the use of the caches can be inhibited for individual locations using the CIIN input signal. A cache invalidation request can cause the entire Instruction Cache and/
or Data Cache to be invalidated; a cache invalidation request can also cause invalidation of a single set in either or
both caches. Refer to Section 3.5.7 for more information.
An external "Bus Watcher" circuit can also be used to help
maintain cache coherence. The Bus Watcher observes the
CPU's bus cycles to maintain a copy of the on-chip cache
tags while also monitoring writes to main memory by DMA
controllers and other microprocessors in the system. When
the Bus Watcher detects that a location in one of the onchip caches has been modified in main memory, it issues an
invalidation request to the CPU. The CPU provides the necessary information on the system interface to help maintain
an external copy of the on-Chip tags.
The DC is enabled for a data write whenever the DC bit in
the CFG Register is set to 1, including interlocked writes
resulting from executing the CBITI and SBITI instructions,
and MMU writes to Page Table entries during address translation.
The DC does not use write allocation. This means that, during a write, if a cache 'hit' occurs, the DC is updated, otherwise it is unaffected. The data is always written through to
external memory.
The status codes differentiate between instruction fetches
and data reads.
The set, affected during the bus access (if ClOUT is low), as
well as the tag can be determined from the address bits A4
through AS and A9 through A31 respectively.
The contents of the data cache can be invalidated by software through the CINV instruction or by hardware through
the appropriate cache invalidation input signals. Clearing
the DC bit in the CFG Register also invalidates the data
cache. Refer to Sections 3.5.10 and C.3 for details.
During a data read the CPU also indicates, by means of the
CASEC signal, which block in the set is being updated.
Note: If Ihe DC is enabled for a certain data reference and a "miss" occurs
due to tag mismatch, the CPU will update the tag of the least recently
used block and clear all the validity bits before reading the data from
external memory. If either CIIN or IODEC are activated during the data
Whenever a CINV instruction is executed, the operation
code and operand appear on the system interface using
slave processor bus cycles. Thus, invalidations of the onchip caches by software can be monitored externally.
read bus cycles, the validity bits are not set and the DC is not updated.
Note, however, that the software is responsible for communicating to the external circuitry the values of the cache enable and lock bits in the CFG Register, since the CPU does
not generate any special cycle (e.g., Slave Cycle) when the
CFG Register is loaded.
3.4.3 Cache Coherence Support
The NS32532 provides several mechanisms for maintaining
coherence between the on-chip caches and external mem-
2-47
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3.0 Functional Description
(Continued)
3.4.4 Translation Look·aside Buffer (TLB)
were not already set. For these reasons, there is no need to
replicate either the V bit or the R bit in the TLB entries.
Whenever a Page Table Entry in memory is altered by software, it is necessary to purge any matching entry from the
TLB, otherwise the corresponding addresses would be
translated according to obsolete information. TLB entries
may be selectively purged by writing a virtual address to one
of the IVARn registers using the LMR instruction. The TLB
entry (if any) that matches that virtual address is then
purged, and its space is made available for another translation. Purging is also performed whenever an address space
is remapped by altering the contents of the PTBO or PTBI
register. When this is done, all the TLB entries corresponding to the address space mapped by that register are
purged. Turning translation on or off (via the MCR TU and
TS bits) does not affect the contents of the TLB.
It is possible to maintain an external copy of the valid contents of the on-chip TLB by observing the CPU's system
interface during the replacement and invalidation of TLB entries. Whenever the CPU replaces a TLB entry, the page
tables are accessed in external memory using bus cycles
with a special Status. Because a FIFO replacement algorithm is used, it is possible to determine which entry is being
replaced by using a 6-bit counter that is incremented whenever a Level-l PTE is accessed. The contents of the new
entry can be found as follows:
The Translation Look-aside Buffer is an on-chip fully associative memory. It provides direct virtual to physical mapping
for 64 pages, thus minimizing the time needed to perform
the address translation.
The efficiency of the on-chip MMU is greatly increased by
the TLB, which bypasses the much longer Page Table lookup in over 99% of the accesses made by the CPU.
Entries in the TLB are allocated and replaced automatically;
the operating system is not involved. The TLB entries cannot be read or written by software; however, they can be
purged from it under program control.
Figure 3-18 shows a model of the TLB. Information is
placed into the TLB whenever a Page Table lookup is performed. If the retrieved mapping is valid (V = 1 in both
levels of the Page Tables), and the access attempted is
permitted by the protection level, an entry of the TLB is
loaded from the information retrieved from memory.
The on-chip MMU places the Virtual Page Number (VPN)
and the Address Space qualifier (AS) into the tag portion of
the TLB entry.
The value portion of the entry is loaded from the Page Tables as follows:
• The PFN field (20 bits) as well as the CI and M bits are
loaded from the Level-2 Page Table Entry (PTE2).
• The PL field (2 bits) is loaded to reflect the most restrictive of the protection levels imposed by the PL fields of
the Level-l and Level-2 Page Table Entries (PTE 1 and
PTE2).
• VPN appears on A2 through All during the PTEI and
PTE2 accesses. The most-significant 10 bits appear during the PTEI access, and the least-significant 10 bits
appear during the PTE2 access.
• AS can be determined from the U/S signal during the
PTEI access.
Not shown in the figure is an additional bit associated with
each TLB entry which indicates whether the entry is valid.
• PFN, M and CI can be determined from the PTE2 value
read on the Data Bus. PL can be determined from the
most restrictive of the PTEI and PTE2 values read on
the Data Bus.
Whenever a LMR instruction is executed, the operation
code and operand appear on the system interface using
slave processor bus cycles. Thus, the information is available externally to determine the translation modes controlled by the MCR and to identify that a TLB entry has been
invalidated.
When the PTBO register is loaded by executing the 'LMR
PTBO src' instruction, the internal FIFO pointer is also reset
to point to the first TLB entry.
Address translation can be either enabled or disabled for a
memory reference. If translation is disabled, then the TLB is
bypassed and the physical address is identical to the virtual
address.
When translation is enabled and a virtual address needs to
be translated, the high-order 20 bits (VPN) and the Address
Space qualifier are compared associatively to the corresponding fields in all entries of the TLB.
For a read reference, if the tag portion of a valid TLB entry,
completely matches the input values, then the value portion
of the entry is used to complete the address translation and
protection checking.
For a write reference, if a valid entry with a matching tag is
present in the TLB, then the M bit is examined. If the M bit is
1, the value portion of the entry is used to complete the
address translation and protection checking. If the M bit is 0,
the entry is invalidated.
Note that the contents of the TLB maintained externally include copies of all valid entries in the on-chip TLB, but the
external copy may include some entries that are invalid in
the on-chip TLB. For example, when the TLB is searched
for a write reference and a matching entry is found with the
M bit clear, then the on-chip entry is invalidated and a miss
is processed. It is not possible to detect externally that the
old matching entry on-chip has been invalidated.
In either case, if a protection level violation is detected, a
translation exception (Trap (ABT)) is generated. When no
matching entry is found or a matching entry is invalidated
because the M bit is 0 in a write reference, a Page Table
lookup is performed. The virtual address is translated according to the algorithm given in Section 2.4.5 and the
translation information is loaded into the TLB.
The recipient entry is selected by an on-chip circuit that implements a First-In-First-Out (FIFO) algorithm.
3.5 SYSTEM INTERFACE
This section provides general information on the NS32532
interface to the external world. Descriptions of the CPU requirements as well as the various bus characteristics are
provided here. Details on other device characteristics including timing are given in Chapter 4.
Note that for a translation to be loaded into the TLB it is
necessary that the Level-l and Level-2 Page Table Entries
be valid (V bit = 1). Also, it is guaranteed that in the process of loading a TLB entry (during a Page Table lookup)
the Level-l and Level-2 R bits will be set in memory if they
3.5.1 Power and Grounding
The NS32532 requires a single 5-volt power supply, applied
on 21 pins. The logic voltage pins (VCCL 1 to VCCL6) supply
2-48
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3.0 Functional Description
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(Continued)
TAG
,
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VALUE
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AS· VPN (20 BITS) PL
VIRTUAL
ADDRESS
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the power to the on-chip logic. The buffer voltage pins
(VCCBl to VCCB14) supply the power to the output drivers
of the chip. The bus clock power pin (VCCClK) is the power
supply for the on-chip clock drivers. All the voltage pins
should be connected together by a power (VCC) plane on
the printed circuit board.
3.5.2 Clocking
The NS32532 requires a single-phase input clock Signal
(ClK) with frequency twice the CPU's operating frequency.
This clock Signal is internally divided by two to generate two
non-overlapping phases PHil and PHI2. One single-phase
clock signal BClK in phase with PHil and its complement
BClK, are also generated and output by the CPU for timing
reference.
The NS32532 grounding connections are made on 20 pins.
The logic ground pins (GNDll to GNDl6) are the ground
pins for the on-chip logic. The buffer ground pins (GNDBI to
GNDB13) are the ground pins for the output drivers of the
chip. The bus clock ground pin (GNDClK) is the ground
connection for the on-chip clock drivers. All the ground pins
should be connected together by a ground plane on the
printed circuit board.
Following power-on, the phase relationship between BClK
and ClK is undefined. Nevertheless, in some systems it
may be necessary to synchronize the CPU bus timing to an
external reference. The SYNC input signal can be used to
initialize the phase relationship between ClK and BClK.
SYNC can also be used to stretch BClK (low) while ClK is
toggling.
Both power and ground connections are shown in Figure
3-19.
SYNC is sampled on each rising edge of ClK. As shown in
Figure 3-20, whenever SYNC is sampled low, BClK stops
toggling and stays low. On the first rising edge that SYNC is
sampled high, BClK is driven high and then toggles on each
subsequent rising edge of ClK.
Every riSing edge of BClK defines a transition in the timing
state (ooT-State") of the CPU.
+5V
VCCL1 _ 6
14
veeBI-14
OTHER Vee
VCCCLK
I--+-+ CONNECTIONS
One T -State represents the execution of one microinstruction within the CPU and/or one step of an external bus
transfer.
(Vee PLANE)
NS32532
CPU
Not.: The CPU requirement on the maximum period of BCLK must be satisfied when SYNC is asserted at times other than reset.
3.5.3 Resetting
The RST input pin is used to reset the NS32532. The CPU
samples RST synchronously on the rising edge of BClK.
Whenever a low level is detected, the CPU responds immediately. Any instruction being executed is terminated; any
results that have not yet been written to memory are discarded; and any pending bus errors, interrupts, and traps
are eliminated. The internal latches for the edge-sensitive
NMI and DBG signals are cleared.
GNDL1- 6
GNDBI-13
OTHER GROUND
GNDCLK
I--+-+ (GND
CONNECTIONS
PLANE)
1..-_ _ _ _ _.....
TL/EE/9354-24
FIGURE 3-19. Power and Ground Connections
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2-49
TLlEE/9354-25
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3.0 Functional Description (Continued)
The CPU stores the PC contents in the RO Register and the
PSR contents in the least-significant word of R1, leaving the
most-significant word undefined. The PC is then cleared to 0
and so are all the implemented bits in the PSR, MSR, MCR
and CFG registers. The DEN-bit in the OCR Register is also
cleared to O. After reset, the remaining implemented bits in
OCR and the contents of all other registers are undefined.
The CPU begins executing the instruction at Address O.
On application of power, RST must be held low for at least
50 /Ls after Vee is stable. This is to ensure that all on-chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 BCLK cycles. See Figures 3-21 and 3-22.
3.5.4.1 Bus Status
The CPU presents five bits of Bus Status information on
pins STO-ST4. The various combinations on these pins indicate why the CPU is performing a bus cycle, or, if it is idle
on the bus, then why is it idle.
The Bus Status pins are interpreted as a five·bit value, with
STO the least significant bit. Their values decode as follows:
00000 The bus is idle because the CPU does not yet need
to access the bus.
00001 The bus is idle because the CPU is waiting for an
interrupt following execution of the WAIT instruc·
tion.
While in ~Reset state, the CPU drives the Signals ADS,
BEO-3, BMT, CONF and HLDA inactive. The data bus is
floated and the state of all other output signals is undefined.
00010 The bus is idle because the CPU has halted after
detecting an abort or bus error while processing an
exception.
Note: If SYNC is asserted while the CPU is being rese~ then BClK does not
toggle. Consequently. SYNC must be high for at least 200 ClK cycles
while RST is low.
00011 The bus is idle because the CPU is waiting for a
Slave Processor to complete executing an instruction.
00100 Interrupt Acknowledge, Master.
The CPU is reading an interrupt vector to acknowledge an interrupt request.
00101 Interrupt Acknowledge, Cascaded.
JLSL
BCLK[._......j-......
R~[.
The CPU is reading an interrupt vector to acknowl·
edge a maskable interrupt request from a Cascaded Interrupt Control Unit.
00110 End of Interrupt, Master.
i..-O!: 100 CLo;aCK
____~_______~__
CL__
ES
-
The CPU is performing a read cycle to indicate that
it is executing a Return from Interrupt (RETI) instruction at the completion of an interrupt's service
procedure.
00111 End of Interrupt, Cascaded.
The CPU is performing a read cycle from a Cascaded Interrupt Control Unit to indicate that it is executing a Return from Interrupt (RETI) instruction at the
completion of an interrupt's service procedure.
01000 Sequential Instruction Fetch.
; - - - - O!: 50 S's
TL/EE/9354-26
FIGURE 3-21. Power-On Reset Requirements
c
_______......1.[
RST
\\~
O!: 1
0
CLOCK
:=r-0
CYCLES
S
The CPU is fetching the next double-word in sequence from the instruction stream.
TUEE/9354-27
FIGURE 3-22. General Reset Timing
01001
3.5.4 Bus Cycles
The NS32532 CPU will perform bus cycles for one of the
following reasons:
1. To fetch instructions from memory.
2. To write or read data to or from memory or peripheral
devices. Peripheral input and output are memory mapped
in the Series 32000 family.
Non-Sequential Instruction Fetch.
The CPU is fetching the first double-word of a new
sequence of instruction. This will occur as a result
of any JUMP or BRANCH, any exception, or after
the execution of certain instructions.
01010 Data Transfer.
The CPU is reading or writing an operand for an
instruction, or it is referring to memory while processing an exception.
01011 Read RMW Class Operand.
3. To read and update Page Table Entries in memory to
perform memory management functions.
4. To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
5. To transfer information to or from a Slave Processor.
The CPU is reading an operand with access class
of read-modify-write.
01100 Read for Effective Address Calculation.
The CPU is reading a pOinter from memory in order
to calculate an effective address for Memory Relative or External addressing modes.
In terms of bus timing, cases 1 through 4 above are identical. For timing specifications, see Section 4. The only external difference between them is the 5-bit code placed on the
Bus Status pins (STO-ST4). Slave Processor cycles differ in
that separate control signals are applied (Section 3.5.4.7).
01101 Access PTE1 by MMU.
The CPU is reading or writing a Level-1 Page Table
Entry while the on-chip MMU is translating virtual
address.
2-50
3.0 Functional Description
z
~
N
(Continued)
01110 Access PTE2 by MMU.
The CPU is reading or writing a Level-2 Page Table
Entry while the on-chip MMU is translating a virtual
address.
11101 Transfer Slave Processor Operand.
T2
I T1 OR
c.:I
nI
~
N
o
.....
- IX:
-
AO-3{
00-31 [ '/,
The CPU is reading a status word from a slave
processor after the slave processor has activated
the FSSR signal.
+
Tl
BCLK [
The CPU is transferring an operand to or from a
Slave Processor.
11110 Read Slave Processor Status.
11111 Broadcast Slave Processor ID
U1
ANY
IT-STATE I
Z
rl/. 'I/, ~-
c.:I
IX
---- rG>- - _.
N
U1
c.:I
N
N
U1
.....
Z
~
N
I
\.
ODIN [
OPCODE.
CJ)
I-)(
I--
U1
c.:I
The CPU is initiating the execution of a Slave Instruction by transferring the first 3 bytes of the instruction, which specify the Slave Processor identification and operation.
ADS [
BIIT [
3.5.4.2 Basic Read and Write Cycles
The sequence of events occurring during a basic CPU access to either memory or peripheral device is shown in Figure 3-23 for a read cycle, and Figure 3-24 for a write cycle.
The cases shown assume that the selected memory or peripheral device is capable of communicating with the CPU at
full speed. If not, then cycle extension may be requested
through the RDY line. See Section 3.5.4.4.
\.. I
I\.V
Vb
I~
/
CONr [
ROY [
A full speed bus cycle is performed in two cycles of the
BCLK clock, labeled T1 and T2. For both read and write bus
cycles the CPU asserts ADS during the first half of T1 indicating the beginning of the bus cycle. From the beginning of
T1 until the completion of the bus cycle the CPU drives the
Address Bus and other relevant control signals as indicated
in the timing diagrams. For cacheable data read cycles the
CPU also drives the CASEC signal to indicate the block in
the DC set where the data will be stored. If the bus cycle is
not cancelled (e.g., state T2 is entered in the next clock
cycle), the confirm signal (CONF) is asserted in the middle
of T1. Note that due to a bus cycle cancellation, the BMT
signal may be asserted at the beginning of T1, and then
deasserted before the time in which it is guaranteed valid
(see Section 4.4.2).
o
v.tI
II
'/, If/, rl/. 'Iii 'Iii 'Iii 'A
/J VLL 011
rl/. rl/. 'Iii 'Iii Vii V
'< 'Iii 'IlL
BRT [ '/,
BER [
-I
~
\. J
Z Vii 'Iii 'Iii Vii VI..
~ 'Iii 'II!
/
BOUT [
BiN [ IJ 'Iii 'Iii 'Iii Vii 'II- '/Ii 'Iii 'Iii VII
BWO-l, [
CIIN,IOOEC
A confirmed bus cycle is completed at the end of T2, unless
a cycle extension is requested. Following state T2 is either
state T1 of the next bus cycle, or an idle T-state, if the CPU
has no bus cycle to perform.
In case of a read cycle the CPU samples the data bus at the
end of state T2.
If a bus exception is detected, the data is ignored.
BEO- 3, STO- 4, [
U;S, CIOUT,IOINH
CASEC [
'J '1/ II/ VI; VII 7X )G 'II- rl/. Iff.
'-0- Y.... X
'-- IX: )(
0-I--
I--
I--
X I-- X
I-I--
-
~TLlEE/9354-28
FIGURE 3·23. Basic Read Cycle
For write bus cycles, valid data is output from the middle of
T1 until the end of the cycle. When a write bus cycle is
immediately followed by another write cycle, the CPU keeps
driving the bus with the data related to the previous cycle
until the middle of state T1 of the second bus cycle.
The CPU always inserts an idle state before a write cycle
when the write immediately follows a read cycle.
Note: The CPU can initiate a bus cycle with a n·state and then cancel the
cycle, such as when a TLB miss or a Cache hit occurs. In such a case,
the CONF signal remains High and the eMT signal is driven High; the
n·slale is followed by anolher noslale or an Idle Toslale.
2-51
•
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
C")
~
en
z
iij
N
C")
an
3.0 Functional Description (Continued)
3.5.4.3 Burst Cycles
The NS32532 is capable of performing burst cycles in order
to increase the bus transfer rate. Burst is only available in
instruction fetch cycles and data read cycle from 32-bit wide
memories. Burst is not supported in operand write cycles or
slave cycles.
The sequence of events for burst cycles is shown in Figure
3-25. The case shown assumes that the selected memory is
capable of communicating with the CPU at full speed. If not,
then cycle extension can be requested through the ROY
line. See Section 3.5.4.4.
A Burst cycle is composed of two parts. The first part is a
regular cycle (opening cycle), in which the CPU outputs the
new status and asserts all the other relevant control signals.
In addition, the Burst Out Signal (BOUn is activated by the
CPU indicating that the CPU can perform Burst cycles. If the
selected memory allows Burst cycles, it will notify the CPU
by activating the burst in signal (BIN). BIN is sampled by the
CPU in the middle of T2 on the falling edge of BClK. If the
memory does not allow burst (BIN high), the cycle will terminate at the end of T2 and BOUT will go inactive immediately. If the memory allows burst (BIN low), and the CPU has
not deasserted BOUT, the second part of the Burst cycle
will be performed and BOUT will remain active until termination of the Burst.
The second part consists of up to 3 nibbles, labeled T2B. In
each of them a data item is read by the CPU. For each
nibble in the burst sequence the CPU forces the 2 least-significant bits of the address to 0 and increments address bits
2 and 3 to select the next double-word; all the byte enable
signals (BEO-3) are activated.
As shown in Figures 3-25 and 4-8 (in Section 4), the CPU
samples ROY at the end of each nibble and extends the
access time for the burst transfer if ROY is inactive.
The CPU initiates burst read cycles in the following cases.
1. An instruction must be fetched (Status = 01000 or
0(001), and the instruction address does not fall within
the last double-word in an aligned 16-byte block (e.g.,
address bits 2 and 3 are not both equal to 1).
2.A data item must be read (Status = 01010,01011 or
0(100), and all of the following conditions are met.
ANY
,T- STATE,
Tl
T2
,T10RTI,
BCLK[
IX
AO-3{
X
N
C")
en
z
~
N
C")
an
'l. 'II, 'II, ~ K
DO-3{
DATA OUT
I
ODIN [
"-
N
~
Z
\. / \. /
ADS [
XU
BtoIT [
i
~
\. /
-I
"
'II, 'II, 'II. 'II, 'II,
~
/
CDNF [
1/
...... /
\. -
ROY [
'l.
~
II //J 11/
BRT [
'I 'II, 'II, '(fh rL!J '1h 'I
'(; 'Iii 'Lit
BER[Z'Iii Vii Vii '1h 'I/,
XI VII VII
I
BOUT [
BiN [ IJ 'IIJ 'IIJ 'II. VIJ VIJ VI.
BWO-{ '/,
X
-- -
B[o-3, [~STO-4,U/S
'1/ 'II 'II 'II ~
VIJ IIJ V//
ex'II, 'II, 'II,
')(
• The data cache is enabled and not locked. (DC = 1
and lOC = 0 in the CFG register.)
X
• The addressed page is cacheable as indicated in the
level-2 Page Table Entry.
TUEE/9354-29
• The bus cycle is not an interlocked data access performed while executing a CBITI or SBITI instruction.
FIGURE 3-24. Write Cycle
The Burst sequence will be terminated when one of the
following events occurs.
1. The last instruction double-word in an aligned 16-byte
block has been fetched.
2. The CPU detects that the instructions being prefetched
are no longer needed due to an alteration of the flow of
control. This happens, for example, when a Branch instruction is executed or an exception occurs.
3. 4 double-words of data have been read by the CPU. The
double-words are transferred within an aligned 16-byte
block in a wrap-around order. For example, if a source
operand is located at address 104, then the burst read
cycle transfers the double-words at 104, 108, 112, and
100, in that order.
2-52
,----------------------------------------------------------,z
3.0 Functional Description
en
(0)
(Continued)
ANY
IT - STATE I
T1
I
T2
I
T28
I
T28
I
T28
I\)
(11
(0)
I\)
I T1 OR Ti I
I
I\)
o
.....
8CLK [
AO-3{
DO- 31 [
ADS [
CONF [
RDY [
8EO- 3 [
I~
8WO-I,
CIIN,IODEC
STO - 4,U/S
ClOUT, 10lNH
CASEC
I'"'-
I\)
(11
(0)
I\)
I
~
I\)
(11
.....
z
en
(0)
1\
1/
\.V
.\... /
1'% +--V
I~ ~V
II
l/ I\.+--
1: ~ V~ V~ VI; VI; VA Ii ~ h ~ Ii ~
lX
1\
BfN[Ii. 'ILl 'II; 'II, Vii VA
80UT [
r-r--
I'"'-
~ K! D- ~ p- ~ fJ
I; VI; VII
DDIN [
st,tT [
z
en
(0)
X D< pc tx
r-r--
I\)
(11
(0)
I\)
w
o
II VI; VI,
/
Ii ~ Ii IA
II VI; f// III, rl/ VI
V
1\
[i, ru f/I, VI, VI; VII V/
~ {/
[1: ~ fj~ 'Iii Vh VII V/
~
'- - -.
......
Z
en
Co)
N
U1
L
\.
DDIN [
N
U1
lX
AO-3{
Co)
N
I
Co)
ADS [
\.V I\..V
\. ..I
Bt.H [
~
~
I~ t--V
\1 \
CONF [
V
o
-/
I\.
~
RDY [
'J VII III III 'I/, r//, rl
~~
fl VLi rtiL
8RT [
'/ rll (II (I/, (I/, rfiL rfh '(fi- rI
'< r.tL r'!i
8ER [
'/ '1/ 'II 'II If/, 'fL, 'L/. V/,
~ 'fL, 'ffL
\1
BOUT [
BiN [ IJ VI/ VI/ VII VII VI/, 'II
8WO-l, [
CIIN,IODEC
1/ VI/ VI/ '1/ 'II '1/ II/
~
--
8£0- 3, STO- 4, [
U/S, CIOUT,IOINH
'II 'I/, 'I/, ,/1 II~
- Dc
t-t--
P< [fL; rLL(fl
X
X
-- +-- t--- +-- pc t-- D<
CASEC [
3-26. Cycle Extension of a Basic Read Cycle
2-55
+--
DC +--
TLlEE/9354-31
. r---------------------------------------------------------------------------------,
3.0 Functional Description
C)
C")
(Continued)
C'\I
C")
In
C'\I
TABLE 3-4. Interrupt Sequences
C")
Data Bus
r~------------~·------------~\
(f)
z
.....
In
~
Cycle
Status
Address
C'\I
C")
In
C'\I
C")
(f)
z
.....
C)
~
C")
In
C'\I
C")
(f)
z
ODIN
BE3
BE2
BE1
BED
Byte 3
A. Non-Maskable Interrupt Control Sequences
Interrupt Acknowledge
1
00100 FFFFFF0016
0
0
X
Interrupt Return
None: Performed through Return from Trap (RETT) instruction .
B. Non-Vectored Interrupt Control Sequences
Interrupt Acknowledge
1
00100 FFFFFE0016
0
0
X
Interrupt Return
1
00110 FFFFFE0016
X
0
0
C. Vectored Interrupt Sequences: Non-Cascaded
Interrupt Acknowledge
1
00100 FFFFFE0016
0
0
X
Interrupt Return
1
00110
FFFFFE0016
0
0
X
Byte 2
Byte 1
ByteD
X
X
X
X
X
X
X
X
X
X
X
Vector:
Range: 0-127
X
X
Vector: Same as
in Previous Int.
Ack. Cycle
X
X
Cascade Index:
range -16to-1
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
1
00100 FFFFFE0016
0
0
(The CPU here uses the Cascade Index to find the Cascade Address)
001101
Cascade
0
See Note
2
Address
Interrupt Return
1
00110 FFFFFE0016
o
(The CPU here uses the Cascade Index to find the Cascade Address)
00111
Cascade
0
See Note
2
Address
X = Don't Care
Note: BEQ-BE3 signals will be activated according to the cascaded leu address
2-56
X
Vector, range 16-255; on appropriate byte of
data bus.
o
X
X
X
X
X
X
Cascade Index:
Same as in
previouslnt.
Ack.Cycle
X
z
(J)
3.0 Functional Description (Continued)
ANY
IT - STATEI
T1
Co)
N
en
Co)
ANY
IT - STATE I
T2
T1
T2
I T1 or TI I
00-3{
SPC [
I
}- K
.....
I\.I--V
SPC [
Z
E3
00-3{
DATA OUT
~
N
C
BClK [
(J)
Co)
N
en
Co)
.
N
N
en
.....
\.
Z
(J)
ODIN [
/
\.
X
X
ODIN [
\.
Co)
/
N
en
Co)
~
STO-4 [
STO-4[
Co)
X
C
TL/EE/9354-33
TLlEE/9354-32
FIGURE 3-27. Slave Processor Write Cycle
FIGURE 3-28. Slave Processor Read Cycle
activating the BER signal. BER is sampled by the CPU at
the end of state T2 or T2B on the rising edge of BCLK.
When BER is sampled active, the CPU completes the bus
cycle normally. If a bus error occurs during a bus cycle for a
reference required to execute an instruction, then a bus error exception is recognized. However, if an error occurs during an acknowledge cycle of another exception or during
the ICU read cycle of a RETI instruction, the CPU interprets
the event as a fatal bus error and enters the 'halted' state.
3.5.5 Bus Exceptions
The NS32532 has the capability of handling errors occurring
during the execution of a bus cycle. These errors can be
either correctable or incorrectable, and the CPU can be notified of their occurrence through the input signals BRT and!
or BER.
Bus Retry
If a bus error can be corrected, the CPU may be requested
to repeat the erroneous bus cycle. The request is done by
asserting the BRT signal. BRT is sampled at the end of
state T2 or T2B.
In this state the CPU floats its address and data buses and
places a special status code on the STO-4 lines. The CPU
can exit this condition only through a hardware reset. Refer
to Section 3.2.6 for more details on bus error.
When the CPU detects that BRT is active, it completes the
bus cycle normally, but ignores the data read in case of a
read cycle, and maintains a copy of the data to be written in
case of a write cycle. Then, after a delay of two clock cycles, it will start executing the bus cycle again.
If the transfer cycle is multiple (e.g., for non-aligned data),
only the problematic part will be repeated.
Note 1: If the erroneous bus cycle is extended by means of wait states, then
the CPU uses the values of BRT and/or BER sampled during the
last wait state.
Note 2: If the CPU samples both BRT and BER active. BRT has higher
priority. The bus error indication is ignored, and the bus cycle is
repeated.
Note 3: If BER is asserted during a bus cycle of a multi·cycle data transfer.
the CPU completes the entire transfer normally, but the data will be
ignored. The CPU also ignores any subsequent assertion of BER
during the same data transfer.
For instance, if a non-aligned double-word is being trans·
ferred and the second half of the transfer fails, only the
second part will be repeated.
Note 4: Neither BRT nor BER should be asserted during the T2 state of a
slave processor bus cycle.
The same applies for a retry during a burst sequence. The
repeated cycle will begin where the read operation failed
(rather than the first address of the burst) and will finish the
original burst.
Figures 3-29 and 4-10 (in Section 4) show the BRT timing
for a basic access cycle and for burst cycles respectively.
The CPU always waits for BRT to be HIGH before repeating
the bus cycle. While BRT is LOW, the CPU places all the
output signals shown in Figure 4-11 in a TRI-STATE® condi·
tion.
3.5.6 Dynamic Bus Configuration
The NS32532 is tuned to operate with 32-bit wide memory
and peripheral devices. The bus also supports S-bit and
l6-bit data widths, but at reduced efficiency. The CPU can
switch from one bus width to another dynamically; the only
restriction is that the bus width cannot change for locations
within an aligned l6-byte block.
The CPU determines the bus width in effect for a bus cycle
by using the values of the BWO and BWl signals sampled
during the last T2 state. Values of BWO and BWl sampled
before the last T2 state or during T2B states are ignored.
Whenever a bus width other than 32·bit is sampled by the
CPU, the bus remains idle for 2 clock cycles before the next
bus cycle can be initiated.
Bus Error
If a bus error is incorrectable the CPU may be requested to
interrupt the current process and branch to an appropriate
procedure to handle the error. The request is performed by
2-57
tI
3.0 Functional Description (Continued)
ANY
IT - STATE I
T1
I
T2
I T1 OR TI I
-X- ~
TI
I
T1
I
T2
I T1 or TI I
X
X DC ~ .-(
00-3{'I. 'II. 'II. /)'- -- _. ~ .. -- I-- _. -- I-- _. ~ .. -- _.
~
~
AO-3{
I
\.
ODIN [
\. / \. /
ADS [
BtotT [
~
~
r'0
-V
/ \.
CONF [
I
\.
\. J
I\.V
\.V
~
I~ ~V
~ I--V
.f \. I -
/
Iv I/V I,
ROY [
'l. 'II. 'II. 'Ih rll. 'II. ~ IJ VII III Iii Iii 'III 'III ~
BRT [
'1'1/ '1/ 'II. 'II. '1/ ~
I-r/h 'II. 'IJ VI) II- 'Iii V ~ 7l. ~
BER [
Z 'II. 'Ih 'Ih Vii 'II.
'G Vii Vii Vii 'Iii 'Ih 'Iii 'I
~~~
/
BOUT [
~[iJ 'I!J 'I!J 'Ih 'I!J 'III 'I!J I!J Iii III III VII VII III II) III VIJ V/
BWO-1, [
CIIN,IOOEC
BEO-3,STO- 4, [
U/S, CIOUT,IOINH
CASEC [
..
..
'/ VIJ 'I) II) (II vX ~
'Ih 'I!J rh
'II. 'II 'IJ 'IJ 'I) 'I) vX ~
~
~
.-he ....- X
.- ...
---
~
~
~
X...
~ X
~
~
,.....
~
X --
')(
- ~ ....- X- X
FIGURE 3·29. Bus Retry During a Basic Read Cycle
2-58
X
- X-TL/EE/93S4-34
z
en
Co)
3.0 Functional Description (Continued)
N
The various combinations for BWO and BW1 are shown below.
The following subsections provide detailed descriptions of
the access sequences performed in the various cases.
.-
BW1
BWO
0
0
0
1
1
0
1
1
Note: Although the NS32532 ignores the BIN signal for B·bit and 16-bit bus
widths, it is recommended that BIN be asserted only if the system
supports burst transfers. This is to ensure compatibility with future
versions of the CPU that might support burst transfers for 8·bit and
16-bit buses.
Reserved
8-Bit Bus
16-Bit Bus
32-Bit Bus
CI1
Co)
N
I
N
o
......
Z
en
Co)
N
CI1
Co)
N
Al
BE2 -""';;"---L...-;
BEO--------,
BE3---.....,
The bus width must always be 32 bits during slave cycles.
An important feature of the NS32532 is that it does not
impose any restrictions on the data alignment, regardless of
the bus width.
Bus accesses are performed in double-word units. Accesses of data operands that cross double-word boundaries are
decomposed into two or more aligned double-word accesses.
The CPU provides four byte enable signals (BEO-3) which
facilitate individual byte accessing on either a 32-bit or a
16-bit bus.
I
N
CI1
......
Z
en
Co)
8El-----.,
N
CACH----~H_-_,
CI1
Co)
~
Co)
o
Figures 3-30 and 3-31 show the basic interfaces for 32-bit
and 16-bit memories. An 8-bit memory interface (not shown)
is even simpler since it does not use any of the BEO-3
signals and its single bank is always enabled whenever the
memory is selected. Each byte location in this case is selected by address bits AO-31.
AI-31
The NS32532 does not keep track of the bus width used in
previous instruction fetches or data accesses. At the beginning of every memory transaction, the CPU always assumes
that the bus is 32-bit wide and the BEO-3 signals are activated accordingly.
The BOUT signal is also asserted during instruction fetches
or data reads if the conditions for bursting are satisfied. If
the bus is other than 32-bit wide, the BIN signal is ignored
and BOUT is deasserted at the beginning of the T state
following T2, since burst cycles are not allowed for 8-bit or
16-bit buses.
00-15 \,.._ _ _ _ _ _..J
TL/EE/9354-36
FIGURE 3-31. Basic Interface for 16-Blt Memories
3.5.6.1 Instruction Fetch Sequences
The CPU performs two types of Instruction fetch cycles: sequential and non-sequential. These can be distinguished
from each other by the differing status combinations on pins
STO-4. For non-sequential instruction fetches the CPU
presents on the address bus the exact byte address of the
first instruction in the instruction stream that is about to begin; for sequential instruction fetches, the address of the
next aligned instruction double-word is presented on the address bus. The CPU always activates all byte enable signals
(BEO-3) for both sequential and non-sequential fetches.
BOUT is also asserted during T2 if the addressed doubleword is not the last in an aligned 16-byte block. Tables 3-5
to 3-7 show the fetch sequence for the various bus widths.
A2-31
32-Blt Bus Width
The CPU reads the entire double-word present on the data
bus into its internal instruction buffer.
If BOUT and BIN are both active, the CPU reads up to 3
consecutive double-words using burst cycles. Burst cycles
are used for instruction fetches regardless of whether the
accesses are cacheable.
DO-31\r______________________
~
TL/EE/9354-35
FIGURE 3-30. Basic Interface for 32-Blt Memories
Note: The CACH signal must be asserted during cacheable read accesses.
2-59
•
3.0 Functional Description (Continued)
Example: JUMP @5
Example JUMP @6
• The CPU performs a fetch cycle at address 5 with BEO-3
all active.
• A fetch cycle is performed at address 6 with BEO-3 all
active.
• Two burst cycles are then performed and addresses 8 and
12 are output while BEO-3 are kept active.
16-Bit Bus Width
• The word at address 4 is then fetched if the access is
cacheable.
8-Blt Bus Width
The instruction byte on the bus lines DO-7 is fetched. The
CPU performs three consecutive cycles to read the remaining bytes within the required double-word, while keeping
BEO-3 all active. The 4 bytes are then assembled into a
double-word and transferred into the instruction buffer. For
a non-sequential fetch, if the access is not cacheable, the
CPU will only read the upper bytes within the instruction
double-word starting with the byte at the instruction address.
Example: JUMP @7
The word on the least-significant half of the data bus is read
by the CPU. This is either the even or the odd word within
the required instruction double-word, as determined by address bit 1.
The CPU then complements address bit 1, clears address
bit 0 and initiates a bus cycle to read the other word, while
keeping all the BEO-3 signals active.
These two words are then assembled into a double-word
and transferred into the instruction buffer.
In case of a non-sequential fetch, if the access is not cacheable and the instruction address selects the odd word within
the instruction double-word, the even word is not fetched.
• The CPU performs a fetch cycle at address 7 with BEO-3
all active.
• Bytes at addresses 4, 5 and 6 are then fetched consecutively if the access is cacheable.
1.
2.
TABLE 3-5. Cacheable/Non-Cacheable Instruction Fetches from a 32-Bit Bus
In a burst access four bytes are fetched with the L.S. bits of the address set to 00.
A 'C' on the data bus refers to cacheable fetches and indicates that the byte is placed in the instruction cache. An 'I' refers
to non-cacheable fetches and indicates that the byte is ignored.
Number
of Bytes
Address
LSB
1
11
Address
Bus
Bytes to be Fetched
-
2
10
81
BO
-
3
01
B2
B1
BO
-
A
4
00
B3
B2
B1
BO
A
BO
-
A
A
BEO-3
LLLL
LLLL
LLLL
LLLL
Data Bus
BO
C/I
C/I
CII
B1
BO
CII
C/I
B2
B1
BO
C/I
B3
B2
B1
BO
TABLE 3-6. Cacheable/Non-Cacheable Instruction Fetches from a 16-Blt Bus
1. A bus access marked with '0' in the 'Address Bus' column Is performed only if the fetch is cacheable.
Number
of Bytes
Address
LSB
1
11
Address
Bus
Bytes to be Fetched
BO
-
-
-
A
°A - 3
2
10
B1
BO
-
-
A
°A - 2
3
01
B2
B1
BO
-
A
A+1
4
00
B3
B2
B1
BO
A
A+2
2-60
BEO-3
LlLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
Data Bus
-
-
BO
C
C/I
C
B1
C
BO
C
-
BO
B2
C/I
B1
-
B1
B3
BO
B2
-
-
-
-
-
z
3.0 Functional Description
en
Co)
(Continued)
I\)
U1
Co)
I\)
TABLE 3·7. CacheablelNon-Cacheable Instruction Fetches from an 8-Bit Bus
Number
of Bytes
Address
LSB
1
11
Address
Bus
Bytes to be Fetched
BO
-
-
-
•A - 1
LLLL
LLLL
LLLL
LLLL
A
A+1
•A - 2
*A - 1
LLLL
LLLL
LLLL
LLLL
A
A+1
A+2
'A - 1
LLLL
LLLL
LLLL
LLLL
A
A+ 1
A+2
A+3
LLLL
LLLL
LLLL
LLLL
A
*A - 3
*A - 2
2
3
4
10
01
00
B1
B2
B3
BO
B1
B2
-
BO
B1
-
-
BO
3.5.6.2 Data Read Sequences
·
I\)
BEO-3
Data Bus
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
.......
Z
BO
C
C
C
BO
B1
C
C
BO
B1
B2
C
BO
B1
B2
B3
16-Bit Bus Width
The word on the least·significant half of the data bus is read
by the CPU. The CPU can then perform another access
cycle with address bit 1 complemented and address bit 0
cleared to read the other word within the addressed doubleword.
If the access is cacheable, the entire double-word is read
and stored into the cache.
If the access is not cacheable, the CPU ignores the bytes in
the double-word not selected by BEO-3. In this case, the
second access cycle is not performed, unless selected
bytes are contained in the second word.
Example: MOVB @5, RO
The CPU starts a data read access by placing the exact
address of the operand on the address bus. The byte enable lines are activated to select only the bytes required by
the instruction being executed. This prevents spurious accesses to peripheral devices that might be sensitive to read
accesses, such as those which exhibit the characteristic of
destructive reading. If the on-chip data cache is internally
enabled for the read access, the BOUT signal is asserted at
the beginning of state T2. BOUT will be deasserted if the
data cache is externally inhibited (through CIiN or IODEC),
or the bus width is other than 32 bits. During cacheable
accesses the CPU always reads all the bytes in the doubleword, whether or not they are needed to execute the instruction, and stores them into the data cache. The external
memory, in this case, must place the data on the bus reo
gardless of the state of the byte enable signals.
• The CPU reads a word at address 5 while keeping BE1
active.
o If the access is not cacheable, the CPU ignores byte O.
o If the access is cacheable, the CPU performs another access cycle, with BEO-3 all active, to read the word at
address 6.
8-Bit Bus Width
The data byte on the bus lines DO-7 is read by the CPU.
The CPU can then perform up to 3 access cycles to read
the remaining bytes in the double-word.
If the data cache is either internally or externally inhibited
during the access, the CPU ignores the bytes not selected
by the BEO-3 signals. Data read sequences for the various
bus widths are shown in tables 3-8 to 3·10.
32-Bit Bus Width
The entire double·word present on the bus is read by the
CPU. If the access is cacheable and the memory allows
burst accesses, the CPU reads up to 3 additional doublewords within the aligned 16-byte block containing the first
byte of the operand. These burst accesses are performed in
a wrap·around fashion within the 16·byte block.
Example: MOVW @5, RO
If the access is cacheable, the entire double-word is read
and stored into the cache.
If the access is not cacheable, the CPU will only perform
those access cycles needed to read the selected bytes.
Example: MOVW @5, RO
• The CPU reads a double-word at address 5 while keeping
BE1 and BE2 active.
o The CPU reads the byte at address 5 while keeping BE1
and BE2 active.
• If the access is not cacheable, the CPU activates BE2 and
reads the byte at address 6.
o If the access is cacheable, the CPU performs three bus
cycles with BEO-3 all active, to read the bytes at addresses 6, 7 and 4.
• If the access is not-cacheable, BOUT is deasserted and
the data bytes 0 and 3 are ignored.
• If the access is cacheable, the CPU performs burst cycles
with BEO-3 all active, to read the double·words at ad·
dresses 8, 12, and O.
2-61
en
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U1
Co)
I\)
·
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U1
.......
Z
en
Co)
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U1
Co)
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•
Co)
0
3.0 Functional Description
1.
2.
(Continued)
TABLE 3·8. Cacheable/Non·Cacheable Data Reads from a 32·Bit Bus
In a burst access four bytes are read with the L.S. bits of the address set to 00.
A 'C' on the data bus refers to cacheable reads and indicates that the byte is placed in the data cache. An 'I' refers to non·
cacheable reads and indicates that the byte is ignored.
Number
of Bytes
Address
LSB
Bytes to be Read
Address
Bus
BEO-3
Data Bus
1
00
-
BO
A
HHHL
C/I
C/I
C/I
BO
01
-
-
1
BO
-
A
HHLH
C/I
C/I
BO
CII
1
10
-
BO
-
-
A
HLHH
CII
BO
C/I
C/I
C/I
1
11
BO
-
A
LH H H
BO
C/I
C/I
00
-
-
-
2
B1
BO
A
HH LL
C/I
CII
B1
BO
2
01
-
B1
BO
A
HLLH
C/I
B1
BO
C/I
2
10
B1
BO
-
-
A
LLH H
B1
BO
C/I
C/I
3
00
-
B2
B1
BO
A
HLLL
CII
B2
B1
BO
3
01
B2
B1
BO
-
A
LLLH
B2
B1
BO
C/I
4
00
B3
B2
B1
BO
A
LLLL
B3
B2
B1
80
TABLE 3·9. Cacheable/Non·Cacheable Data Reads from a 16·Bit Bus
1. A bus access marked with '.' in the 'Address Bus' column is performed only if the read is cacheable.
Number
of Bytes
Address
LSB
1
00
1
1
01
10
Address
Bus
Data to be Read
-
-
-
-
-
BO
-
BO
-
BEO-3
NonCach.
HHHL
LLLL
HHHL
•A+ 2
-
-
A
*A + 1
HHLH
LLLL
HHLH
-
-
A
*A - 2
HLHH
LLLL
HLHH
-
-
-
.-
BO
A
1
11
BO
-
-
-
A
•A- 3
LHHH
LLLL
LHHH
2
00
-
-
B1
BO
A
*A + 2
HH LL
LLLL
HHLL
A
A+1
HLLH
LLLL
HLLH
HLHH
A
LLHH
LLLL
LLH H
•A- 2
2
2
01
10
-
81
B1
BO
BO
-
Data Bus
Cach.
-
-
C/I
C
BO
C
BO
C
C/I
C
-
C/I
C
BO
C
-
BO
C
C/I
C
-
B1
C
BO
C
-
-
-
-
80
C/I
C/I
81
-
-
B1
C
BO
C
-
3
00
-
B2
B1
BO
A
A+2
HLLL
LLLL
HLLL
HLHH
-
-
81
C/I
BO
82
3
01
82
B1
BO
-
A
A+1
LLLH
LLLL
LLLH
LLH H
-
-
BO
B2
C/I
B1
A
A+2
LLLL
LLLL
LLLL
LLH H
-
B1
B3
80
82
4
00
B3
B2
81
BO
2-62
-
-
z
3.0 Functional Description
en
w
(Continued)
N
U1
W
N
TABLE 3-10. CacheableINon-Cacheable Data Reads from an 8-Bit Bus 08-12
I
Number
of Bytes
Address
LSB
1
00
1
1
1
2
2
2
3
3
4
01
10
11
00
01
10
00
01
00
Address
Bus
Data to be Read
-
-
-
BO
-
-
Bl
-
B2
B3
-
-
BO
-
-
Bl
BO
B2
Bl
B2
-
BO
-
-
Bl
BO
-
Bl
BO
Bl
BO
-
-
-
BO
-
-
BO
-
BO
N
BEO-3
o
.......
Data Bus
Z
Cacho
NonCach.
A
*A + 1
*A + 2
*A + 3
HHHL
LLLL
LLLL
LLLL
HHHL
A
'A + 1
'A + 2
'A-1
HHLH
LLLL
LLLL
LLLL
HHLH
A
'A+ 1
*A - 2
'A - 1
HLHH
LLLL
LLLL
LLLL
HLHH
A
'A - 3
*A - 2
*A - 1
LH H H
LLLL
LLLL
LLLL
LH H H
A
A+l
*A + 2
*A + 3
H H LL
LLLL
LLLL
LLLL
H H LL
HHLH
-
A
A+l
*A+ 2
'A - 1
HLLH
LLLL
LLLL
LLLL
HLLH
HLHH
-
-
-
A
A+l
*A - 2
'A - 1
LLH H
LLLL
LLLL
LLLL
LLH H
LHHH
A
A+l
A+2
*A + 3
HLLL
LLLL
LLLL
LLLL
HLLL
HLLH
HLHH
A
A+l
A+2
*A - 1
LLLH
LLLL
LLLL
LLLL
LLLH
LLHH
LHHH
A
A+1
A+2
A+3
LLLL
LLLL
LLLL
LLLL
LLLL
LLLH
LLH H
LHHH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BO
C
C
C
BO
C
C
C
BO
C
C
C
BO
C
C
C
BO
Bl
C
C
BO
Bl
C
C
BO
Bl
C
C
-
BO
Bl
B2
C
-
BO
Bl
B2
C
-
BO
Bl
B2
B3
-
-
-
-
-
3.5.6.3 Data Write Sequences
32-Bit Bus Width
In a write access the CPU outputs the operand address and
asserts only the byte enable lines needed to select the specific bytes to be written.
The CPU performs only one access cycle to write the selected bytes within the addressed double-word.
Example: MOVB RO, @6
• The CPU duplicates byte 2 of the data bus into byte 0 and
performs a write cycle at address 6 with BE2 active.
In addition, the CPU duplicates the data to be written on the
appropriate bytes of the data bus in order to handle 8-bit
and 16-bit buses.
The various access sequences as well as the duplication of
data are summarized in tables 3-11 to 3-13.
16-Bit Bus Width
Up to two access cycles are needed to complete the write
operation.
2-63
en
w
N
U1
W
N
I
N
U1
.......
Z
en
w
N
U1
W
N
~
o
oCO)
'"
CO)
Ln
N
CO)
U)
Z
......
Ln
N
'"
CO)
Ln
N
CO)
(f)
Z
~
I
N
CO)
Ln
N
CO)
(f)
Z
3.0 Functional Description (Continued)
Example: MOVW RO, @5
signals. By asserting HOLD, an external device requests access to the bus. On receipt of HLDA from the CPU, the
device may perform bus cycles, as the CPU at this point has
placed all the output signals shown in Figure 3-32 into the
TRI-STATE condition.
To return control of the bus to the CPU, the external device
sets HOLD inactive, and the CPU acknowledges return of
the bus by setting HLDA inactive.
The CPU samples HOLD in the middle of each T-state on
the falling edge of BCLK. If HOLD is asserted when the bus
is idle between access sequences, then the bus is granted
immediately (see Figure 3-31). If HOLD is asserted during
an access sequence, then the bus is granted immediately
after the access sequence, including any retried bus cycles,
has completed (see Figure 4-13). Note that an access sequence can be composed of several bus cycles if the bus
width is 8 or 16 bits.
o The CPU duplicates byte 1 of the data bus into byte 0 and
performs a write cycle at address 5 with BE1 and BE2
active.
o A write at address 6 is then performed with BE2 active
and the original byte 2 of the data bus placed on byte O.
8-Bit Bus Width
Up to 4 access cycles are needed in this case to complete
the write operation.
Example: MOVB RO, @7
• The CPU duplicates byte 3 of the data bus into bytes 0
and 1, and then performs a write cycle at address 7 with
BE3 active.
3.5_7 Bus Access Control
The NS32532 has the capability of relinquishing its control
of the bus upon request from a DMA device or another CPU.
This capability is implemented with the HOLD and HLDA
TABLE 3-11. Data Writes to a 32-Bit Bus
1. Bytes on the data bus marked with '.' are undefined.
Number
of By1es
Address
LSB
1
00
1
01
1
Data to be Written
-
10
-
1
11
BO
2
00
2
2
3
3
Address
Bus
BEO-3
Data Bus
-
BO
A
HHHL
•
•
•
BO
BO
-
A
HHLH
0
0
BO
BO
-
A
HLHH
0
BO
•
BO
A
LHHH
BO
•
BO
BO
B1
BO
A
H HLL
•
0
B1
BO
01
-
-
-
B1
BO
HLLH
•
B1
BO
BO
B1
BO
-
-
A
10
A
LLH H
B1
BO
B1
BO
00
-
B2
B1
BO
A
HLLL
•
B2
B1
BO
01
B2
B1
BO
-
A
LLLH
B2
B1
BO
BO
4
00
B3
B2
B1
BO
A
LLLL
B3
B2
B1
BO
Number
of Bytes
Address
LSB
1
00
-
1
01
1
10
-
BO
TABLE 3·12. Data Writes to a 16·Bit Bus
Data to be Written
-
•
BO
•
•
BO
BO
B1
BO
0
B1
BO
•
•
•
BO
B1
B1
BO
B1
BO
•
•
B2
B1
•
•
BO
B2
LLLH
LLH H
B2
B1
•
0
BO
B2
BO
B1
LLLL
LLH H
B3
B2
0
•
B1
B3
BO
B2
A
HLHH
•
•
•
A
LHHH
BO
A
H H LL
0
A
A+1
HLLH
HLHH
A
LLH H
A
A+2
HLLL
HLHH
A
A+1
A
A+2
-
-
-
B1
BO
2
01
-
B1
BO
-
2
10
B1
BO
-
-
3
00
-
B2
B1
BO
B2
B1
B2
BO
BO
HHLH
BO
B3
BO
HHHL
A
11
00
•
BO
A
-
00
4
•
•
BO
1
01
Data Bus
-
2
3
BEO-3
BO
-
BO
Address
Bus
BO
B1
BO
2-64
z
(J)
3.0 Functional Description (Continued)
(0)
N
c.n
TABLE 3-13. Data Writes to an 8-Bit Bus
Number
of Bytes
1
1
1
1
2
2
Address
LSB
00
01
10
11
00
01
-
-
80
80
-
-
-
-
81
-
80
80
-
-
81
80
80
-
2
10
81
80
-
-
3
00
-
B2
B1
BO
3
4
01
00
Address
Bus
A
A
A
A
A
A+1
Data to be Written
82
B3
B1
82
BO
B1
A
A+1
A
A+1
A
A+1
A+2
A
A+1
A+2
A
A+1
A+2
A+3
-
BO
(0)
N
BEO-3
HHHL
HHLH
HLHH
LH HH
HH LL
HHLH
HLLH
HLHH
LLHH
LHHH
HLLL
HLLH
HLHH
LLLH
LLHH
LHHH
LLLL
LLLH
LLH H
LHHH
N
o
......
Data Bus
•
•
·• ·
80
•
80
•
80
•
•
•
•
•
•
80
81
B1
•
•
81
80
•
•
BO
B1
•
•
•
•
82
B1
•
•
•
•
•
•
B2
81
BO
•
•
•
•
•
•
B3
82
B1
•
•
•
•
•
•
•
•
•
Z
80
80
80
80
80
81
80
81
BO
B1
BO
B1
B2
BO
B1
82
BO
B1
B2
B3
(J)
(0)
N
c.n
(0)
N
I
N
c.n
......
Z
(J)
(0)
N
c.n
(0)
N
~
o
fJI
2-65
3.0 Functional Description
TI
(Continued)
TI
TI
T1Jif[h
TI
BCLK [
}
AO-31 [
00-3{.-- ~
-- - -- --
I--
ODIN [
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ADS [
'\"
BI.tT [
'\"
CONF [
'\"
-- -- ----- ---- -. -- -1--.
--
I--
- -- -
-
- -- - (- -- - Iex -- -- --
~S-
~S-
~S-
..IJ I\. /
~S-
-
J
~S-
-
J
I' /
~
--
I\,
r-
V
I\,
HOLD [
_. I.{ X
~S-
ir
HLDA [
\.
BOUT [
'\"
BEO-3[
~
- -- _. -- --
CASEC [
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- -- r--
ir
-V
~S-
- IJ
~S-
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STO-4[
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TL/EE/9354-37
FIGURE 3·32. Hold Acknowledge. (Bus Initially Idle.)
Not.: The status Indicates 'IDLE' while the bus is granted. II the cause 01 the IDLE changes (e.g., CPU starts waiting lor an Interrupt), the status also changes.
The CPU will never grant the bus between interlocked read
and write bus cycles.
Note: II an external device requires a very short latency to get control 01 the
When 10DEC Is active during a bus cycle for which 10lNH is
asserted, the CPU discards the data and applies the special
handling required for 110 devices. Figure 3-33 shows a possible implementation of an 1/0 device interface where the
address mapping of the 1/0 devices is fixed.
bus, the bus retry signal (BRT) can be used instead 01 hold. See
Section 3.5.5.
3,5.B Interfacing Memory-Mapped 1/0 Devices
In an open system configuration, 10DEC could be generated
by the decoding logic of each 1/0 device subsystem.
In Section 3.1,3.2 it was mentioned that some special precautions are needed when interfacing 1/0 devices to the
NS32532 due to its internal pipe lined implementation. Two
special signals are provided for this purpose: IOINH and
10DEC. The CPU asserts 10lNH during a read bus cycle to
indicate that the bus cycle should be ignored if an 110 device is selected. The system responds by asserting 10DEC
to indicate to the CPU that an 110 device has been selected. 10DEC is sampled by the CPU in the middle of state T2.
If the cycle is extended, then the CPU uses the IODEC value sampled during the last wait state. If a bus error or a bus
retry occurs, the sampled 10DEC value is ignored. 10DEC
must be kept high during burst transfer cycles.
When the on-chip MMU is enabled, the ClOUT signal could
also be used for this purpose, since 1/0 devices are located
in noncacheable areas. In this case however, a small performance degradation could result, due to the fact that the
special 1/0 handling is also applied on references to noncacheable program andlor data areas.
Note 1: When IODEC is active in response to a read bus cycle, the CPU
treats the reference as noncacheable.
Note 2: lOiNR is kept inactive during write cycles.
2-66
3.0 Functional Description
(Continued)
CHIP
SELECT
10lNH
I/o
DEVICE
NS32532
CPU
ADDRESS ~
.)1 DECODE
INVIC, INVDC, INVSET and CIAO-CIA6 are all sampled
synchronously by the CPU on the rising edge of BClK. The
CPU can respond to cache invalidation requests at a rate of
one per BClK cycle.
As shown in Figures 3-16 and 3-17, the validity bits of the
on-Chip caches are dual-ported. One port is used for acceSSing and updating the caches, while the other port is
used independently for invalidation requests. Consequently,
invalidation of the on-Chip caches occurs with no interference to on-going cache accesses or bus cycles.
A cache invalidation request can occur during a read bus
cycle for a location affected by the invalidation. In such a
case, the data will be invalid in the cache if the invalidation
request occurs during or after the T2- or T2B-state of the
bus cycle.
I
L
t'"
TL/EE/9354-3B
FIGURE 3·33. Typical 1/0 Device Interface
3.5.9 Interrupt and Debug Trap Requests
Three signals are provided by the CPU to externally request
interrupts and lor a debug trap. INT and NMi are for maskable and non-maskable interrupts respectively. DBG is used
for requesting an external debug trap.
The CPU samples INT and NMI on every other rising edge
of BClK, starting with the second rising edge of BClK after
RST goes high.
Refer to Figure 4-18 in Section 4 for timing details.
3.5.11 Internal Status
The NS32532 provides information on the system interface
concerning its internal activity.
The U/S signal indicates the Address Space for a memory
reference (See Section 2.4.2).
NMI is edge-sensitive; a high-to-Iow transition on it is detected by the CPU and stored in an internal latch, so that there
is no need to keep it asserted until it is acknowledged.
Note that U/S does not necessarily reflect the value of the
U bit in the PSR register. For example, U/S is high during
the memory access used to store the destination operand of
a MOVSU instruction.
INT is level-sensitive and, as such, once asserted, it must
be kept asserted until it is acknowledged.
The DBG signal, like NMI, is edge-sensitive; it differs from
NMI in that the CPU samples it on each rising edge of
BClK. DBG can be asserted asynchronously to the CPU
clock, but it should be at least 1.5 clock cycles wide in order
to be recognized.
If DBG meets the specified setup and hold times, it will be
recognized on the rising edge of BClK deterministically.
Refer to Figures 4-19 and 4-20 for more details on the timing of the above signals.
The PFS signal is asserted for one BClK cycle when the
CPU begins executing a new instruction. The ISF signal is
driven High along with PFS if the new instruction does not
follow the previous instruction in sequence. More specifically, ISF is High along with PFS after processing an exception
or after executing one of the following instructions: ACB
(branch taken), Bcond (branch taken), BR, BSR, CASE,
CXP, CXPD, DIA, JSR, JUMP, RET, RETT, RETI, and RXP.
Note: If the NMI signal is pulsed to request a non-maskable interrupt. it may
be necessary to keep it asserted for a minimum of two clock cycles to
The BP Signal is asserted for one BClK cycle when an address-compare or PC-match condition is detected. If the BP
signal is asserted one BClK cycle after PFS, it indicates
that an address-compare debug condition has been detected. If BP is asserted at any other time, it indicates that a PCMatch debug condition has been detected.
While executing an lMR or CINV instruction, the CPU displays the operation code and source operand using slave
processor write bus cycles. This information can be used to
monitor the contents of the on-chip TlB, Instruction Cache
and Data Cache.
During idle bus cycles, the Signals STO-ST4 indicate whether the CPU is waiting for an interrupt, waiting for a Slave
Processor to complete executing an instruction or halted.
guarantee its detection, unless extra logic ensures that the pulse oc-
curs around the BCLK sampling edge.
3.5.10 Cache Invalidation Requests
The contents of the on-chip Instruction and Data Caches
can be invalidated by external requests from the system. It
is possible to invalidate a single set or all sets in the Instruction Cache, Data Cache or both. The input signals INVIC
and INVDC request invalidation of the Instruction Cache
and Data Cache respectively. The input signal INVSET indicates whether the invalidation applies to a single set (16
bytes for the Instruction Cache and 32 bytes for the Data
Cache) or to the entire cache. When only a single set is
invalidated, the set number is specified on CIAO-CIA6.
2-67
4.0 Device Specifications
AOORESS
CLOCKING {
DATA
BUS ACCESS {
CONTROL
RESET
EXCEPTION {
REQUEST
INTERNAL {
STATUS
BUS TIMING AND
CONTROL OUlPUTS
NS32532
SLAVE TIMING
} AND CONTROL
TL/EE/9354-39
FIGURE 4-1. NS32532 Interface Signals
4.1 NS32532 PIN DESCRIPTIONS
Descriptions of the NS32532 pins are given in the following
sections.
Included are also references to portions of the functional
description, Section 3.
Figure 4·1 shows the NS32532 interface signals grouped
according to related functions.
4.1.2 Input Signals
ClK
Clock.
Input Clock used to derive all CPU Timing.
Synchronize.
When SYNC is active, BCLK will stop toggling. This signal can be used to synchronize
two or more CPUs (Section 3.5.2).
Hold Request.
When active, causes the CPU to release the
bus for DMA or multiprocessing purposes
(Section 3.5.7).
Note: An asterisk next to the signal name indicates a TRI-STATE condition
for that signal when FKll1i is acknowledged or during an extended
retry.
4.1.1 Supplies
VCCl1-6
logic Power.
+ 5V positive supplies for on-chip logic.
VCCB1-14 Buffers Power_
+ 5V positive supplies for on-chip output
buffers.
VCCClK
Bus Clock Power.
+ 5V positive supply for on-Chip clock drivers.
GNDl1-6
logic Ground.
Ground references for on-chip logic.
GNDB1-13 Buffers Ground.
Ground references for on-chip output buffers.
GNDClK
Bus Clock Ground.
Ground reference for on-Chip clock drivers.
Note:
If the FKll1i signal is generated asynchronously. its set
up and hold times may be violated. In this case it is recommended to synchronize it with CLK to minimize the
possibility of metastable states.
The CPU provides only one synchronization stage to minimize the HLDA latency. This is to avoid speed degradations In cases of heavy HOLD activity (i.e. DMA oontroller
cycles interleaved with CPU cycles).
Reset.
When RST is active, the CPU is initialized to
a known state (Section 3_5.3).
Interrupt.
A low level on this signal requests a maskable interrupt (Section 3.5.9).
NMI
2-68
Nonmaskable Interrupt.
A High-to-Low transition of this signal requests a nonmaskable interrupt (Section
3.5.9).
z
en
Co)
4.0 Device Specifications (Continued)
DBG
CIAO-6
CIIN
BWO-1
N
Debug Trap Request.
A High·to·Low transition of this signal reo
quests a debug trap (Section 3.5.9).
Cache Invalidation Address Bus.
Bits 0 through 4 specify the set address to
invalidate in the on-chip caches. CIAO is the
least significant. Bits 5 and 6 are reserved
(Section 3.5.10).
Invalidate Set.
When Low, only a set in the on-chip cache(s)
is invalidated; when High, the entire cache(s)
is (are) invalidated.
Invalidate Data Cache.
When Low, the Data Cache contents are invalidated. INVSET determines whether a single set or the entire Data Cache is invalidated.
Invalidate Instruction Cache.
When Low, the Instruction Cache contents
are invalidated. INVSET determines whether
a single set or the entire Instruction Cache is
invalidated.
Cache Inhibit In.
When active, indicates that the location referenced in the current bus cycle is not cacheable. CIIN must not change within an aligned
16-byte block.
I/O Decode.
Indicates to the CPU that a peripheral device
is addressed by the current bus cycle. The
value of IODEC must not change within an
aligned 16-byte block (Section 3.5.8).
Force Slave Status Read.
When asserted, indicates that the slave
status word should be read by the CPU (Section 3.1.4.1). An external 10 kn resistor
should be connected between FSSR and
Vee·
Slave Done.
Used by a slave processor to signal the completion of a slave instruction (Section
3.1.4.1). An external 10 kn resistor should be
connected between SON and Vee.
Burst In.
When active, indicates to the CPU that the
memory supports burst cycles (Section
3.5.4.3).
Ready.
While this Signal is not active, the CPU extends the current bus cycle to support a slow
memory or peripheral device.
Bus Width.
These lines define the bus width (8, 16 or 32
bits) for each data transfer; BWO is the least
significant bit. The bus width must not
change within an aligned 16-byte block-encodings are:
OO-Reserved
01-8 Bits
BRT
BER
10-16 Bits
11-32 Bits
Bus Retry.
When active, the CPU will reexecute the last
bus cycle (Section 3.5.5).
Bus Error.
When active, indicates that an error occurred
during a bus cycle. It is treated by the CPU as
the highest priority exception after reset.
4.1.3 Output Signals
BCLK
U/S
CASEC
ClOUT
2·69
Bus Clock.
Output clock for bus timing (Section 3.5.2).
Bus Clock Inverse.
Inverted output clock.
Hold Acknowledge.
Activated by the CPU in response to the
HOLD input to indicate that the CPU has released the bus.
Program Flow Status.
A pulse on this signal indicates the beginning
of execution for each instruction (Section
3.5.11).
Internal Sequential Fetch.
Indicates along with PFS that the instruction
beginning execution is sequential (ISF Low)
or non·sequential (ISF High).
User/Supervisor.
User or supervisor mode status.
Break Point.
This signal is activated when the CPU detects a PC or operand-address match debug
condition (Section 3.3.2).
'Cache Section.
For cacheable data read bus cycles indicates
the Section of the on·chip Data Cache where
the data will be placed; undefined for other
bus cycles. This signal can be used for external monitoring of the data cache contents.
Cache Inhibit Out.
This signal reflects the state of the CI bit in
the second level page table entry (PTE). It is
used to specify non-cacheable pages. It is
held low while address translation is disabled
and for MMU references to page table entries.
I/O Inhibit.
Indicates that the current bus cycle should
be ignored if a peripheral device is ad·
dressed.
Slave Processor Control.
Data strobe for slave processor transfers.
"Burst Out.
When active, indicates that the CPU is requesting to perform burst cycles.
Interlocked Operation.
When active, indicates that interlocked cycles are being performed (Section 3.5.4.5).
c.n
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·
N
N
o
......
Z
en
Co)
N
c.n
Co)
·
N
N
c.n
......
Z
en
Co)
N
c.n
Co)
·
N
Co)
o
4.0 Device Specifications (Continued)
ODIN
CONF
"Data Direction.
Indicates the direction of a data transfer. It is
low for reads and high for writes.
"Confirm Bus Cycle.
00101-lnterrupt Acknowledge, Cascaded.
00110-End of Interrupt, Master.
00111-End of Interrupt, Cascaded.
01000-8equentiallnstruction Fetch.
01001-Non-Sequentiallnstruction Fetch.
01 01 O-Data Transfer.
When active, indicates that a bus cycle initiated by ADS is valid; that is, the bus cycle has
not been cancelled (Section 3.S.4.2).
BMT
ADS
·Begln Memory Transaction.
When Stable Low indicates that the current
bus cycle is valid; that is, the bus cycle has
not been cancelled (Section 3.S.4.2).
• Address Strobe.
BED-3
When active, indicates that a bus cycle has
begun and a valid address is on the address
bus.
·Byte Enables.
01 011-Read Read-Modify-Write Operand.
0110o-Read for Effective Address.
01101-Access PTE1 by MMU.
01110-Access PTE2 by MMU.
~"" }
Reserved.
11100
11101-Transfer Slave Operand.
1111O-Read Slave Status Word.
Used to selectively enable data transfers on
bytes 0-3 of the data bus.
STD-4
Status.
Bus cycle status code; STO is the least significant. Encodings are:
AO-31
11111-Broadcast Slave 10.
• Address Bus.
Used by the CPU to output a 32-bit address
at the beginning of a bus cycle. AO is the
least significant.
OOOOO-idle: CPU Inactive on Bus.
00001-ldle: WAIT Instruction.
00010-ldle: Halted.
4.1.4 Input/Output Signals
00-31
·Data Bus.
Used by the CPU to input or output data during a read or write cycle respectively.
00011-ldle: The bus is idle while the slave
processor is executing an instruction.
0010o-Interrupt Acknowledge, Master.
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O·Cto +70·C
Storage Temperature
-6S·C to + IS0·C
All Input or Output Voltages with
-O.SVto +7V
Respect to GND
Power Dissipation
4W
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
4.3 ELECTRICAL CHARACTERISTICS TA = O· to + 70·C, Vee = SV ± S%, GND = OV
Symbol
Parameter
Conditions
Max
Units
High Level Input Voltage
2.0
Vee + O.S
V
VIL
Low Level Input Voltage
-O.S
O.B
V
. VOH
High Level Output Voltage
IOH = - 400 /LA
VOL
Low Level Output Voltage
AO-11, 00-31, ODIN
CONF, BMT
BCLK, BCLK
All Other Outputs
IOL=4mA
IOL = 6mA
IOL = 16mA
IOL = 2mA
IL
Input Load Current
0';; VIN';; Vee
IL
Leakage Current (Output and
110 pins in TRI-STATElinput Mode)
0.4 ,;; VIN ,;; Vee
lee
Active Supply Current
lOUT = 0, TA = 2S·C
2-70
Min
Typ
VIH
2.4
V
0.4
0.4
0.4
0.4
V
V
V
V
-20
20
/LA
-20
20
/LA
7S0
mA
r--------------------------------------------------------------------,z
en
4.0 Device Specifications (Continued)
(0)
I\)
CJ'I
(0)
I\)
Connection Diagram
I
I\)
o
.......
s@@@@@@@@@@@@@@@@
R@@@@@@@@@@@@@@@@
p@@@@@@@@@@@@@@@@
N@@@@@@@@@@@@@@@@
M@@@
@@@
L@@@
@@@
K@@@
@@@
J @@ @
NS32532
@@@
@@@
H@@@
G@@@
@@@
F@@@
@@@
E@@@
@@@
D@@@@@@@@@@@@@@@@
c@@@@@@@@@@@@@@@@
B@@@@@@@@@@@@@@@@
A@@@@@@@@@@@@@@@
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
z
en
(0)
I\)
CJ'I
(0)
I\)
I
I\)
CJ'I
.......
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en
(0)
I\)
CJ'I
(0)
I\)
I
(0)
o
TLlEE/9354-40
Bottom View
FIGURE 4-2. 175-Pin PGA Package
NS32532 Pinout Descriptions
Dese
Pin
Dese
Pin
Dese
Pin
Dese
Pin
Dese
Pin
Dese
Pin
Reserved
Reserved
Reserved
BP
18F
R8T
NMI
GNOBl
Reserved
VCCB2
INVIC
Reserved (1)
CIAl
CIA4
VCCBl
Reserved
VCCB4
Reserved
Reserved
VCCB3
F88R
INT
VCCLl
GNOL2
INV8ET
INVOC
CIA3
CIA5
030
028
Al
A2
A3
A4
A5
A6
A7
026
Reserved
Reserved
VCCL2
Reserved
PF8
80N
Reserved
BCLK
VCCCLK
8YNC
CIAO
CIA6
VCCL6
029
027
025
U/S
Reserved
Reserved
GNOL3
GNOB2
OBG
Reserved
BCLK
GNOCLK
CLK
CIA2
031
GNOLl
B16
Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12
C13
C14
C15
C16
01
02
03
04
05
06
07
08
09
010
011
012
013
GNOB13
VCCB14
023
IOINH
ILO
GNOB3
024
022
020
A30
CA8EC
Reserved
021
019
018
A29
A31
VCCB5
GNOB12
017
016
A27
A28
GNOB4
VCCB13
015
014
A26
A25
A24
014
015
016
El
E2
E3
E14
E15
E16
Fl
F2
F3
F14
F15
F16
Gl
G2
G3
G14
G15
G16
Hl
H2
H3
H14
H15
H16
Jl
J2
J3
GNOL6
VCCL5
013
VCCB6
A23
GNOL4
GNOBll
011
012
A22
A21
VCCL3
08
09
010
A20
GNOB5
A17
05
07
VCCB12
A19
A18
A14
All
VCCB8
GNOB7
8T4
HLOA
J14
J15
J16
Kl
K2
K3
K14
K15
K16
Ll
L2
L3
L14
L15
L16
Ml
M2
M3
M14
M15
M16
Nl
N2
N3
N4
N5
N6
N7
N8
GNOL5
CONF
ROY
HOLO
VCCBll
GNOB10
04
06
A16
VCCB7
GNOB6
Al0
A6
A2
8T3
GNOB8
VCCL4
BEl
GNOB9
BWO
BIN
Reserved
00
03
A15
A12
A9
A7
A4
N9
Nl0
Nll
N12
N13
N14
N15
N16
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
Rl
R2
R3
R4
R5
AO
VCCB9
ClOUT
8PC
BE3
VCCB10
A08
BWl
BER
CIIN
02
A13
A8
A5
A3
Al
8T2
8Tl
8TO
BOUT
OOIN
BE2
BEO
BMT
BRT
IOOEC
01
R6
R7
R8
R9
Rl0
Rll
R12
R13
R14
R15
R16
81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816
AS
A9
Al0
All
A12
A13
A14
A15
Bl
B2
B3
B4
B5
B6
B7
B8
B9
Bl0
Bll
B12
B13
B14
B15
Note 1: This pin should be grounded.
All other reserved pins should be left open.
2·71
oC')
N
C')
4.0 Device Specifications
II)
4.4 SWITCHING CHARACTERISTICS
N
C')
(Continued)
ABBREVIATIONS:
CJ)
4.4.1 Definitions
L.E.-Ieading edge
T.E.-training edge F.E.-falling edge
II)
All the timing specifications given in this section refer to
O.BV or 2.0V on all the signals as illustrated below. unless
specifically stated otherwise.
....Z
N
N
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II)
N
C')
CJ)
BCLK
....Zo
N
N
C')
II)
N
SlG1
C')
CJ)
[)
[-
O.BV
SlG1
\-~.~v24V
O.45V
Z
51G2
[
I
ISIG2h
1'"
~K=
[
[
BCLK
2.0V
ISIG11
R.E.-rising edge
O.BV
..~
[
24V
SIG2
2.0V
--2.4V
ISIG11
O.45V
2.4V
/
ISIG2h
-------O.45V
TL/EE/9354-42
FIGURE 4-4. Timing Specification Standard
(Signal Valid before Clock Edge)
---------045V
TLlEE/9354-41
FIGURE 4-3. Timing Specification Standard
(Signal Valid after Clock Edge)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32532-20, NS32532-25, NS32532-30
Maximum times assume capacitive loading of 100 pF on the clock signals and 50 pF on all the other signals. A minimum
capacitance load of 50 pF on BClK and BClK is also assumed.
Name
Figure
Description
NS32532-20
Reference/Conditions
NS32532-25
NS32532-30
Units
Min
Max
Min
Max
Min
Max
50
100
40
100
33.3
100
ns
tBCp
4-24
Bus Clock Period
R.E., BClK to Next
R.E., BClK
tBCh
4-24
BClK High Time
At 2.0V on BClK
(Both Edges)
0.5 tBC p
-5 ns
0.5 tBC p
-4ns
0.5 tBCp
-3 ns
tBCI
4-24
BClK low Time
At O.BV on BClK
(Both Edges)
0.5 tBC p
-5 ns
0.5 tBC p
-4 ns
0.5 tBC p
-3 ns
tBC r
4-24
BClK Rise Time
O.BV to 2.0V on
R.E., BClK
5
4
3
ns
tBCt
4-24
BClK Fall Time
2.0V to O.BV on
F.E., BCLK
5
4
3
ns
tNBCh
4-24
BCLK High Time
At 2.0V on BCLK
(Both Edges)
0.5 tNBC p
-5 ns
0.5 tNBC p
-4ns
0.5 tNBCp
-3ns
tNBC,
4-24
BClK Low Time
At O.BV on BCLK
(Both Edges)
0.5 tNBC p
-5 ns
0.5 tNBC p
-4 ns
0.5 tNBCp
-3ns
tNBC r
4-24
BClK Rise Time
O.BV to 2.0V on
R.E., BClK
5
4
3
ns
tNBCt
4-24
BCLK Fall Time
2.0V to O.BV on
F.E., BCLK
5
4
3
ns
tCBCdr
4-24
ClKto BClK
R.E. Delay
2.0V on R.E., ClK to
2.0V on R.E., BClK
17
14
12
ns
tCBCdt
4-24
ClKto BCLK
F.E. Delay
2.0V on R.E., ClK to
O.BV on F.E., BCLK
17
14
12
ns
tCNBCdr
4-24
CLKto BCLK
R.E. Delay
2.0V on R.E., ClK to
O.BV on R.E., BCLK
17
14
12
ns
2-72
z
en
4.0 Device Specifications (Continued)
Co)
N
.
(II
Co)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32532-20, NS32532-25, NS32532-30 (Continued)
Name
Figure
Description
Reference/Conditions
NS32532-20
NS32532-25
NS32532-30
Min
Min
Min
Max
Max
N
N
Units
Max
o
.......
Z
en
Co)
tCNSCd!
4-24
CLKto BCLK
F.E. Delay
2.0V on R.E., CLK to
O.BV on F.E., BCLK
tSCNSCrf
4-24
Bus Clocks Skew
2.0Von R.E., BCLK to
O.BVon F.E., BCLK
-2
+2
-2
+2
tSCNBClr
4-24
Bus Clocks Skew
O.BV on F.E., BCLK to
2.0V on R.E., BCLK
-2
+2
-2
+2
4-5,4-6
Address Bits 0-31
Valid
After R.E., BCLK T1
tAy
tAh
4-5,4-6
Address Bits 0-31
Hold
After R.E., BCLK T1 or Ti
tAl
4-11,4-12
Address Bits 0-31
Floating
After F. E., BCLK Ti
tAnl
4-11,4-12
Address Bits 0-31
Not Floating
After F.E., BCLK Ti
tABy
4-8
Address Bits A2, A3
Valid (Burst Cycle)
After R.E., BCLK T2B
tASh
4-8
Address Bits A2, A3
Hold (Burst Cycle)
After R.E., BCLK T2B
toOy
4-6,4-15
Data Out Valid
After F.E., BCLK T1
tOOh
4-6,4-15
Data Out Hold
After R.E., BCLK T1 or Ti
toospc
4-15
Data Out Setup
(Slave Write)
Before SPC T.E.
tOOl
4-7
Data Bus Floating
After R.E., BCLK
T10rTi
tOOnl
4-7
Data Bus
Not Floating
After F.E., BCLK T1
tSMTy
4-5,4-7
BMT Signal Valid
After R.E., BCLK T1
tSMTh
4-5,4-7
BMT Signal Hold
After R.E., BCLK T2
tSMTI
4-11,4-12
BMT Signal Floating
After F.E., BCLK Ti
tSMThl
4-11,4-12
BMTSignal
Not Floating
After F.E., BCLK Ti
tCONFa
4-5,4-B
CONF Signal Active
After F.E., BCLK T1
17
14
(II
Co)
-1
+1
ns
(II
-1
+1
ns
11
B
0
0
0
11.
0
13
7
B
0
12
13
11
ns
B
6
5
ns
0
32
21
17
11
13
9
B
ns
ns
ns
11
9
17
13
tCONFnl
4-11,4-12
CONFSignal
Not Floating
After F.E., BCLK Ti
After R.E., BCLK T1
After F.E., BCLK T1
tAOSw
tAOSI
4-11,4-12
ADS Signal Floating
After F.E., BCLK Ti
2-73
B
8
11
21
7
ns
7
ns
1a
12
15
ns
a
a
11
ns
ns
a
21
a
ns
ns
0
a
a
23
27
0
ns
ns
a
0
0
13
17
After R.E., BCLK T1 or Ti
At a.8V (Both Edges)
ns
0
After F.E., BCLK Ti
ADS Pulse Width
ns
0
21
17
~
Co)
o
ns
0
CONF Signal Floating
ADS Signal Inactive
ns
ns
0
CONF Signal Inactive
4-6
~
ns
0
4-5,4-B
4-5,4-B
en
ns
0
17
21
0
7
4-11,4-12
tAOSia
.......
(II
Co)
tCONFI
ADS Signal Active
N
N
Z
tCONFia
4-5,4-B
.
ns
8
tAOS a
N
12
ns
13
ns
•
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32532-20, NS32532-25, NS32532-30 (Continued)
Name
Figure
Description
Reference/Conditions
NS32532-20
Min
tAOS n!
4-11,4-12 ADS Signal
Not Floating
After F.E., BCLK Ti
tBEv
4-6,4-8
BEn Signals Valid
After R.E., BCLK T1
tBEh
4-6,4-8
BEn Signals Hold
After R.E., BCLK T1,
TiorT2B
tBE!
4-11,4-12
BEn Signals Floating
After F.E., BCLK Ti
tBEn!
4-11,4-12 BEn Signals
Not Floating
After F.E., BCLK Ti
tOOINv
4-5,4-6
DDIN Signal Valid
After R.E., BCLK T1
tOOINh
4-5,4-6
DDIN Signal Hold
After R.E., BCLK T1 or Ti
Max
0
NS32532-25
Min
Max
0
21
0
11
0
ns
0
17
13
ns
ns
7
8
ns
ns
0
0
0
Units
Max
8
9
0
0
Min
0
0
11
NS32532-30
ns
ns
tOOIN!
4-11,4-12 DDIN Signal Floating
After F.E., BCLK Ti
tOOINn!
4-11,4-12 DDINSignal
Not Floating
After F.E., BCLK Ti
tSPca
4-14,4-15 SPC Signal Active
After R.E., BCLK T1
19
15
12
ns
tSPCia
4-14,4-15 SPC Signal Inactive
After R.E., BCLK Ti, T1 or T2
19
15
12
ns
toosPC
4-14
DDIN Valid to
SPCActive
4-12,4-13 HLDA Signal Active
Before SPC L.E.
21
0
0
0
13
17
0
0
ns
ns
0
ns
After F.E., BCLK Ti
15
11
10
ns
4-12
HLDA Signal Inactive
After F.E., BCLK Ti
15
11
10
ns
tSTv
4-5,4-14
Status (STO-4) Valid
After R.E., BCLK T1
11
8
7
ns
tSTh
4-5,4-14
Status (STO-4) Hold
After R.E., BCLK T1 or Ti
tBOUTa
4-8,4-9
BOUT Signal Active
After R.E., BCLK T2
15
12
11
ns
tBOUTia
4-8,4-9
BOUT Signal Inactive
After R.E., BCLK
Last T2B, T1 or Ti
15
12
11
ns
After F.E., BCLK Ti
21
17
13
ns
tHLOAa
tHLDAia
tBOUT!
4-11,4-12 BOUT Signal Floating
tBOUTn! 4-11,4-12 BOUT Signal
Not Floating
After F.E., BCLK Ti
0
0
0
0
0
ns
0
ns
tlLOa
4-7
Interlock Signal Active
tlLOia
4-7
Interlock Signal Inactive After F.E., BCLK Ti
11
9
8
ns
tpFSa
4-21
PFS Signal Active
After F.E., BCLK
15
11
10
ns
tPFSia
4-21
PFS Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tlSFa
4-22
ISF Signal Active
After F.E., BCLK
15
11
10
ns
tlSFia
4-22
ISF Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tBPa
4-23
BP Signal Active
After F.E., BCLK
15
11
10
ns
tBPia
4-23
BP Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tusv
4-5
U/S Signal Valid
After R.E., BCLK T1
8
ns
tUSh
4-5
U/S Signal Hold
After R.E., BCLK T1 or Ti
After F.E., BCLK Ti
2-74
11
9
11
0
8
9
0
0
ns
ns
I
z
4.0 Device Specifications
en
Co)
(Continued)
I\)
c.n
Co)
I\)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32532-20, NS32532-25, NS32532-30 (Continued)
I
Name
Figure
Description
Reference/Conditions
tCASv
4-5
CASEC Signal Valid
After F.E., BClK T1
tCASh
4-5
CASEC Signal Hold
After F.E., BlCK T1 or Ti
NS32532-20
NS32532-25
NS32532-30
Min
Min
Min
Max
15
a
Max
11
a
I\)
Units
Max
10
a
o
......
z
en
Co)
ns
ns
I\)
c.n
Co)
I\)
I
I\)
tCASt
4-11,4-12
CASEC Signal Floating
After F.E., BlCK Ti
tCASnt
4-11,4-12
CASEC Signal
Not Floating
After F.E., BlCK Ti
tCIOv
4-5
ClOUT Signal Valid
After R.E., BLCK T1
ICIOh
4-5
ClOUT Signal Hold
After R.E., BlCK T1 or Ti
, tlOl v
4-5
IOINH Signal Valid
After R.E., BlCK T1
tlOl h
4-5
IOINH Signal Hold
After R.E., BlCK T1 or Ti
21
17
a
a
13
ns
c.n
......
ns
en
Co)
ns
c.n
Co)
z
a
I\)
15
a
11
a
11
a
I\)
I
a
15
0
10
ns
10
a
Co)
o
ns
ns
4.4.2.2 Input Signal Requirements: NS32532-20, NS32532-25, NS32532-30
Name
Figure
Description
Reference/Conditions
NS32532-20
NS32532-25
NS32532-30
Units
Min
Max
Min
Max
Min
Max
25
100
20
100
16.6
100
ns
tc p
4-24
Input Clock Period
R.E., ClK to Next
R.E., ClK
tCh
4-24
ClK High Time
At 2.0V on ClK
(Both Edges)
0.5 tc p
-5 ns
0.5 tc p
-5 ns
0.5 tc p
-4ns
tCI
4-24
ClK low Time
At O.BV on ClK
(Both Edges)
0.5 tc p
-5 ns
0.5 tc p
-5ns
0.5tc p
-4ns
tc,
4-24
ClK Rise Time
O.BV to 2.0V on R.E., ClK
5
4
3
ns
tCt
4-24
ClK Fall Time
2.0V to O.BV on F.E., ClK
5
4
3
ns
tOls
4-5,4-14
Data In Setup
Before R.E., BlCK T1 or Ti
tOlh
4-5,4-14
Data In Hold
tROYs
4-5
tROYh
tsws
tSWh
tHO LOs
13
11
9
ns
After R.E., BClK T1 or Ti
1
1
1
ns
ROY Setup Time
Before R.E., BClK T2(W),
T10rTi
22
1B
15
ns
4-5
ROY Hold Time
Ater R.E., BClK T2(W).
T10rTi
1
1
1
ns
4-5
BWO-1 Setup Time Before F.E., BClK T2 or T2(W)
21
17
14
ns
4-5
BWO-1 Hold Time
4-12,4-13 HOLD Setup Time
After F.E., BClK T2 or T2(W)
Before F.E., BClK
tHOLOh
4-12
HOLD Hold Time
After F.E., BClK
tSINs
4-B
BIN Setup Time
Before F.E., BClK T2 or T2(W)
tSINh
4-B
BIN Hold Time
After F.E., BClK T2 or T2(W)
2-75
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
•
4.0 Device Specifications (Continued)
4.4.2.2 Input Signal Requirements: NS32532-20, NS32532-25, NS32532-30 (Continued)
Name
Figure
Description
Reference/Conditions
tBERs
4-6,4-8
BER Setup Time
Before R.E., BCLK Tl or Ti
NS32532-20
NS32532-25
NS32532-30
Min
Min
Min
21
Max
17
tBERh
4-6,4-8
BER Hold Time
After R.E., BCLK Tl or Ti
tBRTs
4-6,4-8
BRT Setup Time
Before R.E., BCLK Tl or Ti
tBRTh
4-6,4-8
BRT Hold Time
After R.E., BCLK Tl or Ti
tlODs
4-5
IODEC Setup Time
Before F.E., BCLK T2 or T2(W)
tlODh
4-5
IODEC Hold Time
After F.E., BCLK T2 or T2(W)
tPWR
4-26
Power Stable to
R.E.of RST
After VCC Reaches 4.5V
tRSTs
4-27
RST Setup Time
Before R.E., BCLK
14
tRSTw
4-27
RST Pulse Width
At 0.8V (Both Edges)
64
tells
4-5
CUN Setup Time
Before F.E., BCLK T2
21
17
tClih
4-5
CUN Hold Time
After F.E., BCLK T2
1
tiNTs
4-19
INT Setup Time
Before R.E., BCLK
14
tlNTh
4-19
INT Hold Time
After R.E., BCLK
tNMls
4-19
NMI Setup Time
Before R.E., BCLK
tNMlh
4-19
NMI Hold Time
tSD.
4-16
tSDh
4-16
tFSSR.
4-17
tFSSRh
4-17
tSYNC.
4-25
tSYNCh
4-25
tCIAs
4-18
CIAO-6 Setup Time
tCIAh
4-18
CIAO-6 Hold Time
tINVS.
4-18
INVSET Setup Time
tlNVSh
4-18
INVSET Hold Time
tlNVls
4-18
INVIC Setup Time
tlNVlh
4-18
INVIC Hold Time
tlNVDs
4-18
INVDC Setup Time
Before R.E., BCLK
tlNVDh
4-18
INVDC Hold Time
After R.E., BClK
tDBG s
4-20
DBG Setup Time
tDBGh
4-20
DBG Hold Time
Max
Units
Max
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
50
40
30
IJ.s
12
11
ns
64
64
tBCp
14
ns
1
1
ns
12
11
ns
ns
1
1
1
20
17
16
ns
After R.E., BCLK
1
1
1
ns
SDN Setup Time
Before R.E., BCLK
14
12
11
ns
SON Hold Time
After R.E., BCLK
1
1
1
ns
FSSR Setup Time
Before R.E., BCLK
14
12
11
ns
FSSR Hold Time
After R.E., BCLK
1
1
1
ns
SYNC Setup Time
Before R.E., CLK
10
8
7
ns
SYNC Hold Time
After R.E., ClK
1
1
1
ns
Before R.E., BClK
16
13
11
ns
After R.E., BClK
1
1
1
ns
Before R.E., BClK
16
13
11
ns
After R.E., BClK
1
1
1
ns
Before R.E., BCLK
14
12
11
ns
After R.E., BCLK
1
1
1
ns
16
13
11
ns
1
1
1
ns
Before R.E., BClK
14
12
11
ns
After R.E., BClK
1
1
1
ns
2-76
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
ANY
IT-STATE I
11
T2
I T2(W) 111 OR Til
BCLK [
-- X-.......:IXr-
AO-3{
-- Xr-I
- It.,- '0t-\. -.
lAy
IAh
~
I}-
00-3{
- -- --
IN
.... {[IDDINY
--
IDlh
¥
ODIN [
IADSa ....
ADS [
BI,n[
~~
r
{~
IADSia
~
I
r-lcAsy
IOOEC [
IOINH[
br~~
IIOIDh'=
r
X
~ !+- ICASh
Xl--
liDOs
IIOIY-
X
tr: 1<
-- X
CASEC [
lUSh
~IClih
j4 \clOY
X
ClOUT [
15Th
X
X
ujS [
IBWh
-
j4 IsTY
- Xr
I- IROYh
-
r-~IOlh
X
I
I
FIGURE 4·5. Basic Read Cycle Timing
2-77
I
TL/EE/9354-43
C)
C')
I
N
C')
Lt)
r---------------------------------------------------------------------------______
4.0 Device Specifications
(Continued)
N
C')
ANY
I T- STATE I
(/)
Z
.....
Lt)
N
N
C')
Lt)
N
~
N
C')
Z
ADS [
Bt.H[
~
.....
\. JO~ ~
1'0
CONF [
~tODINh
I\.V
I~ l -V
~ po-
/
/
V
I\.-
\. /
ROY [
)( D<
BWO-1 [
.....
t"
tBEv '"
BEO-3 [
tOOh
DATA OUT
I'
tOOINv-"
(/)
....
j+
I)- K
ODIN [
tAh
](
tJov-"
00-3{
N
...
IX
C')
C')
Lt)
T21T10RTii
t
tAd
AO-31 [
(/)
Z
......
C)
T1
BCLK [
X
tSEh
](
lSRTs H lI)'
BRT [
tSERs
1)1'
BER [
STO- 4 [
U/s[
f.t
--
X
j
tSRTI
~
,:...tSERh
X
TL/EE/9354-44
Note: An Idle State is always inserted before a Write Cycle when the Write immediately follows a Read Cycle.
FIGURE 4·6. Write Cycle Timing
2·78
~
,--------------------------------------------------------------------------, z
en
w
4.0 Device Specifications (Continued)
N
U1
W
TI
T1
T2
TI
T1
T2
~
TI
C)
BCLK [
"zrn
I I
AO-
w
X
3{~-+__+'''+___!-+--+-I--+_+-+_+~''"+_+-
[l::t:!>-+-+-~~~
~
00- 31
-- {
tDDINv
-- btooni -- .1
~
t DOf
N
U1
DATA OUT
f{DDIN~/
DDIN[-+_~~~-+_~~~+__¥
--
N
U1
W
'I
"rnZ
\.
N
w
U1
w
2!
C)
ADS [
Bt.tT [
I\,
/
-} -
t lLOIa
BWO -
~
{-+-+-r-+--+I"Xr-H-1"K''+--+--+-+--fIX t-"
BEO- 3
... r
- ..
tBEv
~ tSEh
X
[_+-I--+,XlI-+-+-+__I--+-+--+-+-+_+'l-I--+-
B~[-+--+-+---+__I---~/ \."+--+----+---+_~/
\.
BER[-+-~~~__~¥/ \.~-+--+~__~/
\.
STO- 4
[-+-+_joI'X'+-+_r-+-+--+-+~~+-~~I---+--
U/S
[~~--+,'X,+-+~~__~~+--+-~~X,+--+-_
•
TL/EE/9354-45
FIGURE 4·7. Interlocked Read and Write Cycles
2·79
0,-----------------------------------------------------------------,
~
4.0 Device Specifications (Continued)
II)
C'I
~
ANY
IT-STATE I
Z
.....
II)
~
11
I
T2
I
....
}4 tAv
00-31
~
~
I
12B
I
12B
I -....::: ..r-~
~r- X
t ABv -
X
AO-3{
I T1 OR
nI
1/
\.
ODIN [
C")
I'"
ADS [
I\..V
{./
BtolT [
I'- -t-H
CI)
en
z
~
N
CI)
LI)
AOS [
SPC [
CONF [--+-+--l'
ODIN
C\I
~
Z
,
...
HOLD [
[....,_+--+++-+___-~--+--+--
STO-4[_--+-~__+_,~+_~-~~~-+__
TL/EE/9354-52
HLDA [
FIGURE 4·14. Slave Processor Read Timing
TUEE/9354-51
FIGURE 4·13. HOLD Acknowledge Timing
(Bus Initially Not Idle)
ANY
IT - STATEI
I
T1
T21110rTII
I
I
BCLK[SUUL
BCLK [
I
tsOs I
I
tSOh
DO - 3{__+_-+--+,
SON [
TL/EE/9354-54
SPC [
ODIN
STO- 4
FIGURE 4·16. Slave Processor Done
I
[.-1--+--1'
I
I
BCLK[SUUL
[~--1_+',"+-+~_I"'+-+_
t~SR.
I
I I
trsSRh
FSSR [
TL/EE/9354-53
FIGURE 4·15. Slave Processor Write Timing
TL/EE/9354-55
FIGURE 4·17. FSSR Signal Timing
2·84
z
en
Co)
4.0 Device Specifications (Continued)
I
I
I
N
U1
.
I
Co)
BCLK[nsuu
tc~s
CIAO- 6
N
N
o
.....
I-; tclAh
I
Z
[.~-+~-"''1'-r~''fo:--r-
en
Co)
N
.
U1
Co)
INVS~[~_~~_~~-+~,~-+_
N
N
U1
.....
Z
en
Co)
INVIC [
N
U1
Co)
~
IHVDC [
Co)
o
TL/EE/9354-56
FIGURE 4-18. Cache Invalidation Request
Note 1: CIAO-6 and INVSET are only relevant when INVIC and/or INVDC are asserted.
Note 2: If a memory location is being read at the same time an invalidation request for that location occurs, the data will be invalid in the cache if the invalidation
request occurs during or after state T2 or T2B of the read cycle.
BCLK [
I
I
1/ I.
RST [
tiNTs
oo[
i -....
+-
~....
i
NMIS
Nt'lI[
I
tlNTh
~
+-I NMlh
K~
~ r-~I -
+-
-..,;
...
~r--
r-- I~ r~ r-- l-
-
TLlEE/9354-57
FIGURE 4-19. INT and NMI Signals Sampling
Note 1: INT and NMI are sampled on every other riSing edge of BClK, starting with the second rising edge of BClK after RST goes high.
Note 2: INT is level sensitive, and once asserted, it should not be deasserted until it is acknowledged.
I
I
I
I
I
BCLK[nnnn
I I
'OBGST1
I
I
I
tPF~a
I
I I
BCLK[nnnn
IOBGh
IPFSla
DBG [
TL/EE/9354-58
TL/EE/9354-59
FIGURE 4-20. Debug Trap Request
I
I
I
I
tls~a
I
I I
FIGURE 4-21. PFS Signal Timing
BCLK[nnnn
IISFia
~[
8P[
TL/EE/9354-60
TL/EE/9354-61
FIGURE 4-22. ISF Signal Timing
FIGURE 4-23. Break Point Signal Timing
2-85
oC")
~
f3
r--------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
~
en
z
......
~
C")
~
en
BCLK [
z
......
o
N
~
C")
an
N
~
i+-----tNBCp.-----I
TL/EE/9354-62
Z
FIGURE 4-24. Clock Waveforms
CLK[~h.h..h.ht~YNCs I
I tsYNCh
I
SYNC [
I
~YNC'
~-+--I--+--1-+--
BCLK [
TL/EE/9354-63
FIGURE 4-25. Bus Clock Synchronization
BCLK [, _ _-1-_
nrL:J'
tRSTS.1
RST[
.----------~!
TUEE/9354-64
FIGURE 4-26. Power-On Reset
TL/EE/9354-65
FIGURE 4-27. Non-Power-On Reset
2·86
z
(J)
Appendix A: Instruction Formats
Co)
N
NOTATIONS:
C1I
Options: in String Instructions
Co)
-
IU/W I BIT I
i = Integer Type Field
B = 00 (Byte)
W = 01 (Word)
D = 11 (Double Word)
N
I
N
o
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
f = Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L = 0 (Long Floating: 64 bits)
Z
(J)
Co)
N
C1I
Co)
N
I
Configuration bits, in SETCFG Instruction:
c = Custom Type Field
D = 1 (Double Word)
Q = 0 (Quad Word)
I
C
1
I
N
C1I
M
F
Z
(J)
Co)
mreg: MMU Register number, in LMR, SMR.
op = Operation Code
Valid encodings shown with each format.
~=
gen, gen 1, gen 2 = General Addressing Mode Field
See Section 2.2 for encodings.
N
C1I
Co)
N
I
0
}
Co)
Trap (UND)
o
reg = General Purpose Register Number
cond
0111
1000
1001
1010
1011
1100
1101
1110
1111
= Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = CarrySet:C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
=
=
=
=
=
=
=
=
=
=
Greater Than: N = 1
Less or Equal: N = 0
Flag Set: F = 1
Flag Clear: F = 0
LOwer: L = 0 and Z = 0
Higher or Same: L = 1 or Z = 1
Less Than: N = 0 and Z = 0
Greater or Equal: N = 1 or Z = 1
(Unconditionally True)
(Unconditionally False)
= Reserved
=
=
=
=
=
=
=
MCR
MSR
TEAR
PTBO
PTB1
IVARO
IVAR1
7
0
co'nd'
11'0'1'01
~p'
10' 0' 1 ' 01
Format 0
(BR)
Bcond
7
short = Short Immediate value. May contain:
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ, ACB.
0
Format 1
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPR.
0000 = US
0001 = DCR
0010 = BPC
0011 = DSR
0100 = CAR
0101-0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = USP
1100 = CFG
1101 = PSR
1110 = INTBASE
1111 = MOD
15
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
, ,
gen
ADDQ
CMPQ
SPR
Scond
2-87
ENTER
EXIT
NOP
WAIT
DIA
FLAG
SVC
BPT
, ,
81 7
,
sh~rt
Format
-000
-001
-010
-011
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
1
2
ACB
MOVQ
LPR
op
0
11 ' 1 1
-100
-101
-110
o ,--------------------------------------------------------------------------,
~
CW)
."
N
CW)
tJ)
Z
......
."
N
~
CW)
."
N
CW)
tJ)
Z
~
Format 3
TLlEE/9354-66
CXPD
BICPSR
JUMP
BISPSR
-0000
-0010
-0100
-0110
Trap (UND) on XXX1, 1000
~
ADJSP
JSR
CASE
-1010
-1100
-1110
sI7
II g~nll I II I I I I I I
CW)
1S
."
N
~
gen2
Z
FormatS
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
0
-000
-001
-010
-011
-110,reg
-110, reg
INDEX
FFS
= 001
= 011
op
0
Format 4
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
-100
-101
1 1 1 1 0
SUB
AD DR
AND
SUBC
TBIT
XOR
-1000
-1001
-1010
-1100
-1101
-1110
Format 9
MOVif
LFSR
MOVLF
MOVFL
-000
-001
-010
-011
ROUND
TRUNC
SFSR
FLOOR
-100
-101
-110
-111
7
0
0
i
---I
I I I I I I I 1
___ 0 1 1 1 1 1 1
0 000 1 110
~
TL/EE/9354-67
FormatS
MOVS
CMPS
-0000
-0001
Format 10
-0010
-0011
SETCFG
SKPS
Trap (UND) Always
o
Trap (UND) on lXXX, 01XX
o
11110
001 1 1 0
Format 11
ADD!
MOV!
CMP!
Note 3
SUB!
NEG!
Note 2
Note 1
Format 6
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
NEG
NOT
Trap (UND)
SUBP
ABS
COM
IBIT
ADDP
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
0
00111 0
Format 7
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
DIV
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
2-88
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
DIV!
Note 1
Note 3
Note 1
MUll
ABSf
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
z
(J)
Appendix A: Instruction Formats (Continued)
1 1 1 1 1 0
Format 12
Note 2
Note 1
Note 3
Note 3
Note 2
Note 1
Note 2
Note 1
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
Note 2
Note 1
Note 3
Note 1
Note 2
Note 1
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
7
---I
Co)
I I I I I I I
-000
-001
-010
-011
(J)
Co)
N
CJ1
N
N
CJ1
.....
Z
CCALO
CMOVO
CCMPO
CCMP1
CCAL1
CMOV2
Note 2
Note 1
Co)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
N
CJ1
CCAL3
CMOV3
Note 3
Note 1
CCAL2
CMOV1
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Q
Format 15.7
LMR
SMR
CINV
-0010
-0011
-1001
Trap (UNO) on 01XX, 1000, 101X, 11XX
16 115
8 :'n'
n'1'o'1'1':1
1
10 Byte
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
Note 2
Note 1
Note 3
Note 3
Note 2
Note 1
Note 2
Note 1
If nnn
~
Note 2
Note 1
Note 3
Note 1
Note 2
Note 1
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
010.011.100.110 then Trap (UNO) Always.
Format 15
---I
(Custom Slave)
7
0
___ 0 I1i 0 " 1 1 " 1 1 I 0
Operation Word Format
1
TLlEE/9354-69
Format 16
000
Trap (UNO) Always
7
Format 15.0
LCR
SCR
·
N
Co)
111
Format 14
nnn
Co)
0
0001111 0
Operation Word
Z
(J)
Trap (UNO) Always
23
1
Q
Format 15.5
TUEE/9354-68
-0000
-0001
·
.....
•
Format 13
ROVAL
WRVAL
Co)
N
N
-100
-101
-110
-111
CCV2
CCV1
SCSR
CCVO
101
1
8 7
CCV3
LCSR
CCV5
CCV4
Co)
0
___ 1 0 0 1 1 1 1 0
N
CJ1
Format 15.1
0
7
0
---I " " "
___ 1 1 0 1 1 1 1 I 0
-0010
-0011
1
TL/EE/9354-7D
Format 17
Trap (UNO) on all others
Trap (UNO) Always
---I
001
___
7
1 I 0 "0
0
0 I 1 I 1 Ii
1 0
1
TL/EE/9354-71
2-89
fII
C)
i
r-----------------------------------------------------------------------------------------~
Appendix A: Instruction Formats (Continued)
(I)
z
......
3. Either the program does not depend on the use of a
Memory Management Unit (MMU), or it is written for operation with the NS323B2 MMU and does not use the
bus-error or debugging features of the NS323B2.
Format 18
CO)
Trap (UNO) Always
;
7
0
---I
___ xI xI xI 0 I 0 I 1 I 1 I 0
I
4. The program does not depend on the detection of bus
errors according to the implementation of the NS32332.
For example, the NS32532 distinguishes between restartable and nonrestartable bus errors by transferring
control to the appropriate bus-error exception service
procedure through one of two distinct entries in the Interrupt Dispatch Table. In contrast, the NS32332 uses a
single entry in the Interrupt Dispatch Table for all bus
errors.
5. The program does not modify itself. Refer to Section B.4
for more information.
6. The program does not depend on the execution of certain complex instructions to be non-interruptible. Refer
to Section B.5 on. "Memory-Mapped 1/0" for more information.
7. The program does not use the custom slave instructions
CATSTO and CATST1, as they are not supported by the
NS32532 and will result in a Trap (UNO) when their execution is attempted.
TL/EE/9354-72
N
CO)
en
z
~an
CO)
Format 19
Trap (UNO) Always
Implied Immediate Encodlngs:
o
7
~
rl
en
z
rO
Register Mark, Appended to SAVE, ENTER
o
7
Register Mark, Appended to RESTORE, EXIT
o
7
: offset:
Nole 1: Opcode not defined; CPU treats like MOVf or CMOVc. First operand
has access class of read; second operand has access class of write; f or c
field selects 32· or 64·bft data.
Nole 2: Opcode not defined; CPU treats like ADDf or CCAL". First operand
has access class of read;, second operand has access class of read· modify·
write; f or c field selects 32· or 64·bft data.
Nole 3: Opcode not defined; CPU treats like CMPf or CCMPc. First operand
has access class of read;, second operand has access class of read; f or c
field selects 32· or 64·bit data.
B.2 ARCHITECTURE EXTENSIONS
The NS32532 implements the following extensions of the
Series 32000 architecture using previously reserved control
bits, instruction encodings, and memory locations. Extensions implemented earlier in the NS32332, such as 32-bit
addressing, are not listed.
1. The DC, LDC, IC, and LlC bits in the CFG register have
been defined to control the on-chip Instruction and Data
Caches. The DE·bit in the CFG register has been defined to enable Direct-Exception Mode.
Appendix B. Compatibility Issues
2. The V-flag in the PSR register has been defined to enable the Integer-Overflow Trap.
OffsetlLength Modifier Appended to INSS, EXTS
The NS32532 is compatible with the Series 32000 architecture implemented by the NS32032, NS32332, and previous
microprocessors in the family. Compatibility means that
within certain limited constraints, programs that execute on
one of the earlier Series 32000 microprocessors will produce identical results when executed on the NS32532.
Compatibility applies to privileged operating systems programs, as well as to non-privileged applications programs.
This appendix explains both the restrictions on compatibility
with previous Series 32000 microprocessors and the extensions to the architecture that are implemented by the
NS32532.
3. The OCR, BPC, DSR, and CAR registers have been defined to control debugging features. Access to these
registers has been added to the definition of the LPR
and SPR instructions.
4. Access to the CFG and SPI registers has been added
to the definition of the LPR and SPR instructions.
5. The CINV instruction has been defined to invalidate
control of the on·chip Instruction and Data Caches.
6. Direct·Exception Mode has been added to support faster interrupt service time and systems without module
tables.
7. A new entry has been added to the Interrupt Dispatch
Table for supporting vectors to distinguish between restartable and nonrestartable bus errors. Two additional
entries support Trap (OVF) and Trap (DBG).
B.l RESTRICTIONS ON COMPATIBILITY
If the following restrictions are observed, then a program
that executes on an earlier Series 32000 microprocessor
will produce identical results when executed on the
NS32532 in an appropriately configured system:
1. The program is not time-dependent. For example, the
program should not use instruction loops to control realtime delays.
2. The program does not use any encodings of instructions, operands, addresses, or control fields identified to
be reserved or undefined. For example, if the count operand's value for an LSHi instruction is not within the
range specified by the Series 32000 Instruction Set Reference Manual. then the results produced by the
NS32532 may differ from those of the NS32032.
B.
Restrictions have been eliminated for recovery from
Trap (ABT) for operands with access class of write that
cross page boundaries. Restrictions still exist however,
for the operands of the MOVMi instruction.
B.3INTEGER OVERFLOW TRAP
A new trap condition is recognized for integer arithmetic
overflow. Trap (OVF) is enabled by the V-flag in the PSR.
This new trap is important because detection of integer
overflow conditions is required for certain programming languages, such as ADA, and the PSR flags do not indicate the
occurrence of overflow for ASHi, DIVi and MUll instructions.
2-90
z
en
Co)
Appendix B. Compatibility Issues (Continued)
More details on integer overflow are given in Section 3.2.5,
where a description of all the cases in which an overflow
condition is detected is also provided.
INTEGER ARITHMETIC
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an integer arithmetic instruction whose result
cannot be represented exactly in the destination operand's
location.
If the number of bits required to represent the resulting quotient of a DEI instruction exceeds half the number of bits of
the destination, then the contents of both the quotient and
remainder stored in the destination are undefined.
The ADDR instruction can be used in place of integer arithmetic instructions to perform certain calculations. In this
case however, integer overflow is not detected by the CPU.
LOGICAL INSTRUCTIONS
3. The device cannot be used for instruction fetches, reads
of effective addresses, or Page Table Entries.
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an ASHi instruction whose result cannot be
represented exactly in the destination operand's location.
4.
If an instruction that reads a source operand from the
device crosses a page boundary, then no Trap (ABT) or
restartable bus error can occur during fetches from the
page with higher addresses.
5. No Trap (ABT) for a data reference or other exception
can occur during execution of an instruction that reads a
source operand from the device. (Exceptions that are
recognized after completion of an instruction, like Trap
(OVF) and Trap (DBG), cause no problem.)
ARRAY INSTRUCTIONS
The V-flag in the PSR enables Trap (OVF) to occur following
execution of a CHECKi instruction whose source operand is
out of bounds.
PROCESSOR CONTROL INSTRUCTIONS
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an ACBi instruction if the sum of the "inc" value and the "index" operand cannot be represented exactly
in the "index" operand's location.
6. The device can be used as a source operand only for
instructions in the list below.
ABSi
CBITi
MOVMi
SBITli
ADDi
CBITIi
MOVXi
SUBi
ADDCi
CMPi
MOVZi
SUBCi
ADDPi
CMPQi
NEGi
SUBPi
NOTi
ADDQi
COMi
TBITi
ANDi
IBITi
ORi
XORi
LSHi
ROTi
ASHi
BICi
MOVi
SBITi
This restriction arises because the CPU can respond to
interrupt requests during the execution of complex instruction in order to reduce interrupt latency. Thus, the
CPU may read the source operands for a DEID instruction (extended-precision divide), begin calculating the instruction's results, and then respond to an interrupt request before completing the instruction. In such an
event, the instruction can be executed again and completed correctly after the interrupt service procedure returns unless one of the source operands was altered by
destructive-reading.
B.4 SELF·MODIFYING CODE
The Series 32000 architecture does not have special provisions to optimally support self-modifying programs.
Nevertheless, on the NS32332 and previous Series 32000
microprocessors it is possible to execute self-modifying
code according to the following sequence:
1. Modify the appropriate instruction.
2. Execute a JUMP instruction or other instruction that
causes the microprocessor's instruction queue to be
flushed.
3. Execute the modified instruction.
For example, an interactive debugger may follow the sequence above after reaching a breakpoint in a program being monitored.
The same program may not produce identical results when
executed on the NS32532 due to effects of the Instruction
Cache and branch prediction. In order to execute self-modifying code on the NS32532 it is necessary to do the following:
1. Modify the appropriate instruction.
2.
N
ing" and "side·effects of writing" that impose requirements
for special handling of memory-mapped I/O references.
The NS32532 supports two methods to use on references
to memory-mapped peripheral devices that exhibit either or
both of these characteristics.
For peripheral devices that exhibit only side-effects of writing, correct operation can be ensured either by locating the
device between addresses FFOOOOOO (hex) and FF7FFFFF
(hex) in the virtual address space or by observing the first 2
restrictions listed below. For peripheral devices that exhibit
destructive-reading, all the following restrictions must be observed to ensure correct operation:
1. References to the device must be inhibited while the
CPU asserts the output signal 101NH.
2. The input signal 10DEC must be asserted by the system
on references to the device.
Appendix C. Instruction Set
Extensions
If the modified instruction is on a cacheable page, execute CINV to invalidate the contents of the Instruction
Cache.
The following sections describe the differences and extensions to the Series 32000 instruction set (as presented in the "Series 32000 Instruction Set Reference Manual") implemented by the NS32352.
3.
Execute an instruction that causes a serializing operation. See Section 3.1.3.3.
4. Execute the modified instruction.
No changes or additions have been made to the usermode instruction set, and only a few privileged instructions have been added.
B.5 MEMORY·MAPPED 1/0
As was mentioned in Section 3.1.3.2, certain peripheral devices exhibit characteristics identified as "destructive·read-
2-91
(It
Co)
~
N
o
......
Z
en
Co)
N
(It
Co)
N
~
(It
......
z
en
Co)
N
.
(It
Co)
N
Co)
o
oCO)
•
N
CO)
II)
Appendix C.lnstruction Set Extensions
N
C.l PROCESSOR SERVICE INSTRUCTIONS
en
z
.......
The CFG register, User Stack Pointer (SP1), and Debug
Registers can be loaded and stored using privileged forms
of the LPRi and SPRi instructions.
N
When the SETCFG instruction is executed, the CFG register
bits 0 through 3 are loaded from the instruction's short field,
bits 4 through 7 are forced to 1, and bits 8 through 12 are
forced to O.
CO)
II)
~
CO)
II)
N
CO)
en
z
.......
o
N
~
CO)
II)
N
CO)
en
z
11~
[
I
7, 1 '1 ,0 ,1 ,1 , :01
, ' ,8 1
gen
short
src
procreg
11~ "
.
gen
LPRi
1
",8
short 7"",
0 1 0 1 1I
dest
procreg
SPRi
FIGURE C-l. LPRi/SPRi Instruction Formats
The contents of the on·chip Instruction Cache and Data
Cache can be invalidated by executing the privileged instruction CINV. While executing the CINV instruction, the
CPU generates 2 slave bus cycles on the system interface
to display the first 3 bytes of the instruction and the source
operand. External circuitry can thereby detect the execution
of the CINV instruction for use in monitoring the contents of
the on-chip caches.
TABLE C-l. LPRi/SPRi New 'Short' Field Encodings
Register
C.2 MEMORY MANAGEMENT INSTRUCTIONS
The NS32532 on-chip MMU does not implement the BAR,
BDR, BEAR, and BMR registers of the NS32382. These
registers are used in the NS32382 to support bus error and
debugging features. When an attempt is made to access
one of these 4 registers by executing an LMR or SMR instruction, a Trap (UND) occurs. More generally, a Trap
(UND) occurs whenever an attempt is made to execute an
LMR or SMR instruction and the most-significant bit of the
short-field is O.
procreg
short field
Debug Condition Register
DCR
0001
Breakpoint Program Counter
BPC
0010
Debug Status Register
DSR
0011
Compare Address Register
CAR
0100
User Stack Pointer
USP
1011
Configuration Register
CFG
1100
Cache Invalidate
Syntax:
options, src
gen
read. D
The CI NV instruction invalidates the contents of locations in
the on-chip Instruction Cache and Data Cache. The instruction can be used to invalidate either the entire contents of
the on-chip caches or only a 16-byte block. In the latter
case, the 28 most-significant bits of the source operand
specify the physical address of the aligned 16-byte block;
the 4 least-significant bits of the source operand are ignored. If the specified block is not located in the on-chip
caches, then the instruction has no effect. If the entire
cache contents is to be invalidated, then the source operand is read, but its value is ignored.
Options are specified by listing the letters A (invalidate All), I
(Instruction Cache), and D (Data Cache). If neither the I nor
D option is specified, the instruction has no effect.
In the instruction encoding, the options are represented in
the A, I, and D fields as follows:
A: O-invalidate only a 16-byte block
1-invalidate the entire cache
I: O-do not affect the Instruction Cache
1-invalidate the Instruction Cache
D: O-do not affect the Data Cache
1-invalidate the Data Cache
Flags Affected: None
Illegal Operation Trap (ILL) occurs if an atTraps:
tempt is made to execute this instruction
while the U-flag is 1.
While executing an LMR instruction, the CPU generates 2
slave bus cycles on the system interface to display the first
3 bytes of the instruction and the source operand. External
circuitry can thereby detect the execution of an LMR instruction for use in monitoring the contents of the on-chip
Translation Lookaside Buffer.
Like the NS32382 MMU, the F-flag in the PSR is set and no
Trap (ABT) occurs when a RDVAL or WRVAL instruction is
executed and the Protection Level in the Level-l Page Table Entry indicates that the access is not allowed. In the
NS32082 MMU, an abort occurs when the Level-l PTE is
invalid, regardless of the Protection Level.
C.3 INSTRUCTION DEFINITIONS
This section provides a description of the operations and
encodings of the new NS32532 privileged instructions.
Load and Store Processor Registers
Syntax: LPRi
procreg,
src
short
gen
read.i
SPRi
(Continued)
procreg
short
dest
gen
write.i
The LPRi and SPRi instructions can be used to load and
store the User Stack Pointer (USP or SP1), the Configuration Register (CFG) and the Debug Registers in addition to
the Processor Registers supported by the previous Series
32000 CPUs. Access to these registers is privileged.
CINV
Examples:
1.CINVA,D,I,R3
2. CINV I, R3
Figure C-t and Table C-l show the instruction formats and
the new 'short' field encodings for LPRi and SPRi.
Flags Affected: No flags affected by loading or storing the
USP, CFG, or Debug Registers.
Traps:
Illegal Instruction Trap (ILL) occurs if an
attempt is made to load or store the USP,
CFG or Debug Registers while the U·flag
is 1.
lEA71B
1E 27 19
Example 1 invalidates the entire Instruction Cache and Data
Cache.
Example 2 invalidates the 16-byte block whose physical address in the Instruction Cache is contained in R3.
2-92
z
Appendix C. Instruction Set Extensions
~3
'
~e~'
src
en
Co)
(Continued)
I\)
o
\15
817
0\
10iAII 010'1'0'0'1'1'1 0'0'0'1'1'1'1'0
1 000 1 1 1 1 0
src
options
CINV
FIGURE C-2. CINV Instruction Format
mmureg
LMR
LMR
I
I\)
o
.......
z
en
Co)
I\)
Load.:.land Store Memory Management Register
Syntax:
U1
Co)
I\)
U1
mmreg,
short
src
gen
read.O
SMR
mmureg,
dest
short
gen
write.O
The LMR and SMR instruction load and store the on-chip
MMU registers as 32-bit quantities to and from any general
operand. For reasons of system security, these instructions
are privileged. In order to be executable, they must also be
enabled by setting the M bit in the CFG register.
dest
mmureg
SMR
FIGURE C-3. LMRISMR Instruction Formats
TABLE C-2. LMRISMR 'Short' Field Encodings
Register
The instruction formats as well as the 'short' field encodings
are shown in Figure C-3 and Table C-2 respectively.
It is to be noted that the IVARO and IVAR1 registers are
write'only, and as such, they can only be loaded by the LMR
instruction.
Flags Affected: none
Traps:
Undefined Instruction Trap (UNO) occurs if
an attempt is made to execute this instruc·
tion while either of the following conditions
is true:
1. The M-bit in the CFG register is O.
2. The U-Flag in the PSR is 0 and the
most-significant bit of the short field is O.
mmureg
short field
Memory Management
Control Reg
MCR
1001
Memory Management
Status Reg
MSR
1010
Translation Exception
Address Reg
TEAR
1011
Page Table Base
Register 0
PTBO
1100
Page Table Base
Register 1
PTB1
1101
Invalidate Virtual
Address 0
IVARO
1110
Invalidate Virtual
Address 1
IVAR1
1111
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Illegal Instruction Trap (ILL) occurs if an attempt is made to execute this instruction
while the M-bit in the CFG register and the
U-flag in the PSR are both 1.
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PRELIMINARY
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NS32332-10/NS32332-15
32-Bit Advanced Microprocessors
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General Description
Features
The NS32332 is a 32-bit, virtual memory microprocessor
with 4 GByte addressing and an enhanced internal implementation. It is fully object code compatible with other Series 32000® microprocessors, and it has the added features
of 32-bit addressing, higher instruction execution throughput, cache support, and expanded bus handling capabilities.
The new bus features include bus error and retry support,
dynamic bus sizing, burst mode memory accessing, and enhanced slave processor communication protocol. The higher clock frequency and added features of the NS32332 enable it to deliver 2 to 3 times the performance of the
NS32032.
•
•
•
•
•
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The NS32332 microprocessor is designed to work with both
the 16- and 32-bit slave processors of the Series 32000
family.
•
•
32-bit architecture and implementation
4 Gbyte uniform addressing space
Software compatible with the Series 32000 Family
Powerful instruction set
- General 2-address capability
- Very high degree of symmetry
- Address modes optimized for high level languages
Supports both 16- and 32-bit Slave Processor Protocol
- Memory management support via NS32082 or
NS32382
- Floating pOint support via NS32081 or NS32381
Extensive bus feature
- Burst mode memory accessing
- Cache memory support
- Dynamic bus configuration (8-, 16-, 32-bits)
- Fast bus protocol
High speed XMOSTM technology
84 Pin grid array package
Block Diagram
ADD/DATA
32·BIT
INTERNAL BUS
CONTROLS & STATUS
DATA
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MICROCODE ROM
AND
CONTROL LOGIC
WIM
III!
CFG REGISTER
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FIGURE 1
·Shaded areas indicate enhancements from the NS32032.
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Table of Contents
1.0 PRODUCT INTRODUCTION
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3.0 FUNCTIONAL DESCRIPTION (Continued)
3.6 Bus Access Control
1.1 NS32332 Key Features
2.0 ARCHITECTURAL DESCRIPTION
2.1 Programming Model
3.7 Instruction Status
3.8 NS32332 Interrupt Structure
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3.B.2 Interrupt/Trap Return
2.1.2 Dedicated Registers
3.B.3 Maskable Interrupts (The INT Pin)
2.1.3 The Configuration Register (CFG)
3.B.3.1 Non-Vectored Mode
2.1.4 Memory Organization
3.B.3.2 Vectored Mode: Non-Cascaded Case
2.1.5 Dedicated Tables
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3.B.1 General Interrupt/Trap Sequence
2.1.1 General Purpose Registers
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3.B.3.3 Vectored Mode: Cascaded Case
2.2 Instruction Set
3.B.4 Non-Maskable Interrupt (The NMI Pin)
2.2.1 General Instruction Format
3.8.5 Traps
2.2.2 Addressing Modes
3.8.6 Prioritization
2.2.3 Instruction Set Summary
3.B.7 Interrupt/Trap Sequences: Detailed Flow
3.8.7.1 Maskable/Non-Maskable Interrupt
Sequence
3.0 FUNCTIONAL DESCRIPTION
3.1 Power and Grounding
3.B.7.2 Trap Sequence: Traps Other than Trace
3.3 Clocking
3.B.7.3 Trace Trap Sequence
3.3 Resetting
3.B. 7.4 Abort Sequence
3.4 Bus Cycles
3.9 Slave Processor Instructions
3.4.1 Cycle Extension
3.9.1 16-Bit Slave Processor Protocol
3.4.2 Burst Cycles
3.9.2 32-Bit Fast Slave Protocol
3.4.3 Bus Status
3.9.3 Floating Point Instructions
3.4.4 Data Access Sequences
3.9.4 Memory Management Instructions
3.4.4.1 Bit Accesses
3.9.5 Custom Slave Instructions
3.4.4.2 Bit Field Accesses
4.0 DEVICE SPECIFICATIONS
3.4.4.3 Extending Multiple Accesses
4.1 Pin Descriptions
3.4.5 Instruction Fetches
3.4.6 Interrupt Control Cycles
4.1.1 Supplies
3.4.7 Dynamic Bus Configuration
4.1.2 Input Signals
4.1.3 Output Signals
3.4.B Bus Exceptions
4.1.4 Input-Output Signals
3.4.8.1 Bus Retry
3.4.B.2 Bus Error
4.2 Absolute Maximum Ratings
3.4.B.3 Fatal Bus Error
4.3 Electrical Characteristics
4.4 Switching Characteristics
3.4.9 Slave Processor Communication
3.4.9.1 Slave Processor Bus Cycles
4.4.1 Definitions
3.4.9.2 Slave Operand Transfer Sequence
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
3.5 Memory Management Option
3.5.1 The FLT (Float) Pin
4.4.2.2 Clocking Requirements
3.5.2 Aborting Bus Cycles
4.4.2.3 Input Signal Requirements
3.5.2.1 Instruction Abort
4.4.3 Timing Diagrams
3.5.2.2 Hardware Considerations
Appendix A: Instruction Formats
B: Interfacing Suggestions
2-95
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List of Illustrations
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CPU Block Diagram ..............................................................................................1
The General and Dedicated Registers ............................................................................2-1
Processor Status Register .......................................................................................2-2
CFG Register ..................................................................................................2-3
Module Descriptor Format. ......................................................................................2-4
A Sample Link Table ...........................................................................................2-5
General Instruction Format ......................................................................................2-6
Index Byte Format .............................................................................................2-7
Displacement Encodings ........................................................................................2-8
Recommended Supply Connections .............................................................................. 3-1
Clock Timing Relationships ......................................................................................3-2
Power-on Reset Requirements ...................................................................................3-3
General Reset Timing ..........................................................................................3-4
Recommended Reset Connections, Non-Memory Managed System ................................................. 3-5a
Recommended Reset Connections, Memory Managed System ..................................................... 3-5b
Read-cycle Timing .............................................................................................3-6
Write-cycle Timing .............................................................................................3-7
Bus Connections ...............................................................................................3-8
RDY Pin Timing ................................................................................................3-9
Extended Cycle Example ......................................................................................3-10
Burst Cycles; Normal Termination of Burst ...................................................................... 3-11 a
Burst Cycles; External Termination of Burst. ..................................................................... 3-11 b
BOUT Timing Resulting from a Bus Width Change ................................................................. 3-12
Memory Interface .............................................................................................3-13
Bus Width Changes ...........................................................................................3-14
Bus Cycle Retry; Bus Cycle Not Retried ......................................................................... 3-15a
Bus Cycle Retry; Bus Cycle Retried ............................................................................3-15b
Bus Error During Read or Write Cycle ............................................................................ 3-16
Slave Processor Connections .................................................................................. 3-17
CPU Read from Slave Processor ................................................................................ 3-18
CPU Write to Slave Processor .................................................................................. 3-19
Read (Write) Cycle with Address Translation ...................................................................... 3-20
FLT Timing ...................................................................................................3-21
HOLD Timing, Bus Initially Idle .................................................................................. 3-22
HOLD Timing, Bus Initially Not Idle .............................................................................. 3-23
ILO Timing ...................................................................................•.....•.........3-24
Non-Aligned Write Cycle-MC/EXS Timing ....................................................................... 3-25
Interrupt Dispatch Table .......................................................................................3-26
Interrupt/Trap Service Routine Calling Sequence .................................................................3-27
Return from Trap (RETTn) Instruction Flow ....................................................................... 3-28
Return from Interrupt (RETI) Instruction Flow ..................................................................... 3-29
Service Sequence ............................................................................................3-30
Slave Processor Protocol ......................................................................................3-31
Fast Slave Protocol ...........................................................................................3-32
ID and Opcode Format for Fast Slave Protocol. ................................................................... 3-33
Slave Processor Status Word Format ............................................................................ 3-34
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List of Illustrations (Continued)
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Connection Diagram, Pin Grid Array Package ...................................................................... 4-1
.....
Timing Specification Standard (Signal Valid After Clock Edge) ........................................................ 4-2
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Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
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NS32332 Read Cycle Timing ....................................................................................4-4
NS32332 Write Cycle Timing ....................................................................................4-5
NS32332 Burst Cycle Timing ....................................................................................4-6
External Termination of Burst Cycle .................................•........................................... .4-7
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NS32332 Bus Retry During Normal Bus Cycle ...................................................................... 4-8
BRT Activated, but No Bus Retry ................................................................................. 4-9
Bus Retry During Burst Bus Cycle ............................................................................... 4-10
BRT Activated During Burst Bus Cycle, but No Bus Retry ........................................................... 4-11
Bus Error During Normal Bus Cycle .............................................................................. 4-12
Bus Error During Burst Bus Cycle .............................................................................. .4-13
Timing of Interlocked Bus Transactions ......................................................................... .4-14
Floating by HOLD Timing (CPU not Idle Initially) ................................................................... 4-15
Floating by HOLD Timing (Burst Cycle Ended by HOLD Assertion) .................................................. .4-16
Floating by HOLD Timing (CPU Initially Idle) ...................................................................... 4-17
Release from HOLD .......................................................................................... .4-18
FLT Initiated Cycle Timing ...................................................................................... 4-19
Release from FLT Timing (CPU Write Cycle) ......................................................................4-20
Slave Processor Write Timing ...................................................................................4-21
Slave Processor Read Timing ..................................................................................4-22
DTISDONE Timing (32-Bit Slave Protocol) ...................................................................... .4-23
SPC Timing (16-Bit Slave Protocol) ..............................................................................4-24
Clock Waveforms ............................................................................................ .4-25
Relationship of PFS to Clock Cycles .............................................................................4-26
Guaranteed Delay, PFS to Non-Sequential Fetch ..................................................................4-27
Guaranteed Delay, Non-Sequential Fetch to PFS ................................................................. .4-28
Abort Timing, FLT Not Applied ..................................................................................4-29
Abort Timing, FLT Applied ..................................................................................... .4-30
Power-on Reset ..............................................................................................4-31
Non-Power-on Reset ..........................................................................................4-32
U/S Relationship to Any Bus Cycle, Guaranteed Valid Interval ..................................................... .4-33
INT Interrupt Signal Detection ................................................................................. .4-34
NMllnterrupt Signal Timing .................................................................................... .4-35
System Connection Diagram (32332, 32081 & 32082) .............................................................. B-1
System Connection Diagram (32332, 32381 & 32382) .............................................................. B-2
List of Tables
NS32332 Addressing Modes ....................................................................................2-1
Series 32000 Instruction Set Summary ............................................................................2-2
Bus Access Types .............................................................................................3-1
Access Sequences .............................................................................................3-2
Interrupt Sequences ............................................................................................3-3
2-97
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1.0 Product Introduction
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The Series 32000 Microprocessor family is a new generation of devices using National's XMOS and CMOS technologies. By combining state-of-the-art MOS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
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• High-Level Language Support
• Easy Future Growth Path
• Application Flexibility
1.1 NS32332 KEY FEATURES
The NS32332 is a 32-bit CPU in the Series 32000 family. It
is totally software compatible with the NS32032, NS32016,
and NS32008 CPUs but with an enhanced internal implementation.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. The family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
The NS32332 design goals were to achieve two to three
times the throughput of the NS32032 and to provide the full
32-bit addreSSing inherent in the architecture.
The basic approaches to higher throughput were: fewer
clock cycles per instruction, better bus use, and higher
clock frequency.
An examination of the block diagram of the NS32332 shows
it to be identical to that of the NS32032, except for enhanced bus interface control, a 20-byte (rather than 8-byte)
instruction prefetch queue, and special hardware in the address unit. The new addressing hardware consists of a highspeed ALU, a barrel shifter on one of its inputs, and an
address register. Of the throughput improvement not due to
increased clock frequency, about 15% is derived from the
new address unit hardware, 15% from the bus enhancements, 10% from the larger prefetch queue, and 60% from
microcode improvements.
Other important aspects of the enhanced bus interface circuitry of the NS32332 are a burst access mode, designed to
work with nibble and static column RAMs, read and write
timing designed to support caches, and support for bus error processing.
An enhanced slave processor communication protocol is
designed to achieve improved performance with the
NS32382 MMU and NS32381 FPU, while still working directly with the previous NS32082 MMU and NS32081 FPU.
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
Symmetric Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided. This powerful memory-to-memory architecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
Memory Management. Either the NS32382 or the
NS32082 Memory Management Unit may be added to the
system to provide advanced operating system support functions, including dynamic address translation, virtual memory
management, and memory protection.
Large, Uniform Addressing. The NS32332 has 32-bit address pointers that can address up to 4 gigabytes without
requiring any segmentation; this addreSSing scheme provides flexible memory management without added-on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a significant reduction in hardware and
software cost.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture has 8 general purpose and 8
dedicated registers. All registers are 32 bits wide except the
STATUS and MODULE register. These two registers are
each 16 bits wide.
2.1.1 General Purpose Registers
There are eight registers for meeting high speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are thirty-two bits in
length. If a general register is specified for an operand that
is eight or sixteen bits long, only the low part of the register
is used; the high part is not referenced or modified.
2.1.2 Dedicated Registers
The eight dedicated registers of the processor are assigned
specific functions.
PC: The PROGRAM COUNTER register is a pOinter to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section.
sPa, SP1: The SPO register points to the lowest address of
the last item stored on the INTERRUPT STACK. This stack
is normally used only by the operating system. It is used
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
2-98
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2.0 Architectural Description
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GENERAL
DEDICATED
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32
PROGRAM COUNTER
PC
STATIC BASE
SB
FRAME POINTER
USER STACK PTR.
INTERRUPT STACK PTR.
INTERRUPT BASE
0
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SP1 }
SP
R4
SPD
RS
INTBASE
PSR
MOD
R6
STATUS
MODULE
R7
TLlEE/8673-2
FIGURE 2-1. The General and Dedicated Registers
primarily for storing temporary data, and holding return information for operating system subroutines and interrupt and
trap service routines. The SP1 register pOints to the lowest
address of the last item stored on the USER STACK. This
stack is used by normal user programs to hold temporary
data and subroutine return information.
grams, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
C: The C bit indicates that a carry or borrow occurred
after an addition or subtraction instruction. It can be
used with the ADDC and SUBC instructions to perform
multiple-precision integer arithmetic calculations. It may
have a setting of 0 (no carry or borrow) or 1 (carry or
borrow).
In this document, reference is made to the SP register. The
terms "SP register" or "SP" refer to either SPO or SP1,
depending on the setting of the S bit in the PSR register. If
the S bit in the PSR is 0 the SP refers to SPO. If the S bit in
the PSR is 1 then SP refers to SP1.
T: The T bit causes program tracing. If this bit is a 1, a
TRC trap is executed after every instruction (Sec. 3.8.5).
L: The L bit is altered by comparison instructions. In a
comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as unsigned integers. Otherwise, it is set to "0". In Floating Point comparisons, this
bit is always cleared.
Stacks in the Series 32000 family grow downward in memory. A Push operation pre-decrements the Stack Pointer by
the operand length. A Pop operation post-increments the
Stack Pointer by the operand length.
FP: The FRAME POINTER register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
F: The F bit is a general condition flag, which is altered
by many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
Z: The Z bit is altered by comparison instructions. In a
comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is
set to "0".
The frame pointer holds the address in memory occupied by
the old contents of the frame pointer.
SB: The STATIC BASE register pOints to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module.
N: The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to "0".
INTBASE: The INTERRUPT BASE register holds the address of the dispatch table for interrupts and traps (Sec.
3.8). The INTBASE register holds the lowest address in
memory occupied by the dispatch table.
U: If the U bit is "1" no privileged instructions may be
executed. If the U bit is "0" then all instructions may be
executed. When U = 0 the processor is said to be in
Supervisor Mode; when U = 1 the processor is said to
be in User Mode. A User Mode program is restricted
from executing certain instructions and accessing certain registers which could interfere with the operating
system. For example, a User Mode program is prevented from changing the setting of the flag used to indicate
its own privilege mode. A Supervisor Mode program is
assumed to be a trusted part of the operating system,
hence it has no such restrictions.
MOD: The MODULE register holds the address of the module descriptor of the currently executing software module.
The MOD register is sixteen bits long, therefore the module
table must be contained within the first 64K bytes of memory.
PSR: The PROCESSOR STATUS REGISTER (PSR) holds
the status codes for the microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all pro15
8
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S: The S bit specifies whether the SPO register or SP1
register is used as the stack pointer. The bit is automatically cleared on interrupts and traps. It may have a setting of 0 (use the SPO register) or 1 (use the SP1 register).
0
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TLlEE/8673-3
FIGURE 2-2. Processor Status Register
2-99
•
2.0 Architectural Description
(Continued)
P: The P bit prevents a TRC trap from occurring more
than once for an instruction (Sec. 3.B.5.). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
115 MSB's BI7
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A+1
A
Word at Address A
Two contiguous words are called a double word. Except
where noted (Sec. 2.2.1), the least significant word of a double word is stored at the lowest address and the most significant word of the double word is stored at the address two
greater. In memory, the address of a double word is the
address of its least significant byte, and a double word may
start at any address.
I: If I = 1, then all interrupts will be accepted (Sec. 3.B.).
If I = 0, only the NMI interrupt is accepted. Trap enables are not affected by this bit.
2.1.3 The Configuration Register (CFG)*
Within the Control section of the CPU is the CFG Register,
which declares the presence and type of external devices. It
is referenced by only one instruction, SETCFG, which is intended to be executed only as part of system initialization
after reset. The format of the CFG Register is shown in
Figure 2-3.
131 MSB's 24123
'The NS32332 CPU has four new bits in the CFG Register, namely P, FC,
FM and FF.
A+3
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LSB's
BI7
LSB's
01
A
A+2
A+1
Double Word at Address A
Although memory is addressed as bytes, it is actually organized as double-words. Note that access time to a word or a
double·word depends upon its address, e.g. double-words
that are aligned to start at addresses that are multiples of
four will be accessed more quickly than those not so
aligned. This also applies to words that cross a double·word
boundary.
FIGURE 2-3. CFG Register
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the Interrupt Control Unit). If
the CFG I bit is set, interrupts requested through the INT pin
are "Vectored." If it is clear, these interrupts are "Non-Vectored." See Sec. 3.B.
The F, M and C bits declare the presence of the FPU, MMU
and Custom Slave Processors. If these bits are not set, the
corresponding instructions are trapped as being undefined.
2.1.5 Dedicated Tables
Two of the dedicated registers (MOD and INTBASE) serve
as pOinters to dedicated tables in memory.
The INTBASE register pOints to the Interrupt Dispatch and
Cascade tables.
The MOD register contains a pOinter into the Module Table,
whose entries are called Module Descriptors. A Module Descriptor contains four pointers. The MOD register contains
the address of the Module Descriptor for the currently running module. It is automatically up·dated by the Call External Procedure instructions (CXP and CXPD).
The FF, FM, FC bits define the Slave Communication Proto·
col to be used in FPU, MMU and Custom Slave instructions
(Sec. 3.4.9). If these bits are not set, the corresponding instructions will use the 16-bit protocol (32032 compatible). If
these bits are set, the corresponding instructions will use
the new (fast) 32·bit protocol.
The P bit improves the efficiency of the Write Validation
Buffer in the CPU. It is set if the Virtual Memory has page
size(s) larger than or equal to 4 Kbytes. It is reset otherwise.
In Systems where the MMU is not present, the P bit is not
used.
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2.1.4 Memory Organization
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The main memory is a uniform linear address space. Memo·
ry locations are numbered sequentially starting at zero and
ending at 232 • 1. The number specifying a memory location
is called an address. The contents of each memory location
is a byte conSisting of eight bits. Unless otherwise noted,
diagrams in this document show data stored in memory with
the lowest address on the right and the highest address on
the left. Also, when data is shown vertically, the lowest ad·
dress is at the top of a diagram and the highest address at
the bottom of the diagram. When bits are numbered in a
diagram, the least Significant bit is given the number zero,
and is shown at the right of the diagram. Bits are numbered
in increasing significance and toward the left.
31
STATIC BASE
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LINK TABLE ADDRESS
PROGRAM BASE
RESERVED
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TL/EE/8673-4
FIGURE 2-4. Module Descriptor Format
01
A
Byte at Address A
Two contiguous bytes are called a word. Except where noted (Sec. 2.2.1), the least significant byte of a word is stored
at the lower address, and the most significant byte of the
word is stored at the next higher address. In memory, the
address of a word is the address of its least significant byte,
and a word may start at any address.
2·100
The format of a Module Descriptor is shown in Figure 2-4.
The Static Base entry contains the address of static data
aSSigned to the running module. It is loaded into the CPU
Static Base register by the CXP and CXPD instructions. The
Program Base entry contains the address of the first byte of
instruction code in the module. Since a module may have
multiple entry points, the Program Base pointer serves only
as a reference to find them.
2.0 Architectural Description
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(Continued)
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The Link Table Address points to the Link Table for the
currently running module. The Link Table provides the information needed for:
1) Sharing variables between modules. Such variables are
accessed through the Link Table via the External addressing mode.
The format of a Link Table is given in Figure 2-5. A Link
Table Entry for an external variable contains the 32-bit address of that variable. An entry for an external procedure
contains two 16-bit fields: Module and Offset. The Module
field contains the new MOD register contents for the module being entered. The Offset field is an unsigned number
giving the position of the entry point relative to the new
module's Program Base pointer.
ENTRY
(VARIABLE)
ABSOLUTE ADDRESS
_....
OFFSET
I
TL/EE/8673-7
( PROCEDURE)
_....
TL/EE/8673-5
2.2 INSTRUCTION SET
2.2.1 General Instruction Format
Figure 2-6 shows the general format of a Series 32000 instruction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to, two 5-bit General Addressing Mode ("Gen") fields. Following the Basic Instruction field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes selected.
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Memory Space. Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-7.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selectOPTIONAL
EXTENSIONS
BASIC
INSTRUCTION
r~----------------~A~----------------~\I~--------~~
I
DISP2 DISPl DISP21DISP1
DISP
IMM
DISP
I
z
en
w
N
W
W
~
......
en
2.2.2 Addressing Modes
FIGURE 2-5. A Sample Link Table
IMPLIED
IMMEDIATE
OPERAND(S)
......
<:)
.......
The CPU generally accesses an operand by calculating its
Effective Address based on information available when the
operand is to be accessed. The method to be used in performing this calculation is specified by the programmer as
an "addressing mode."
Addressing modes are designed to optimally support highlevel language accesses to variables. In nearly all cases, a
variable access requires only one addressing mode, within
the instruction that acts upon that variable. Extraneous data
movement is therefore minimized.
Addressing Modes fall into nine basic types:
(VARIABLE)
MODULE
"I
W
N
Some instructions require additional, "implied" immediates
and/or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Sec. 2.2.3).
For further details of the functions of these tables, see the
Series 32000 Instruction Set Reference Manual.
0-1'"'
-131
ABSOLUTE ADDRESS
l
REG. NO.
FIGURE 2-7. Index Byte Format
ed address modes. Each Displlmm field may contain one or
two displacements, or one immediate value. The size of a
Displacement field is encoded with the top bits of that field,
as shown in Figure 2-8, with the remaining bits interpreted
as a Signed (two's complement) value. The size of an immediate value is determined from the Opcode field. Both Displacement and Immediate fields are stored most significant
byte first. Note that this is different from the memory representation of data (Sec. 2,1.4).
2) Transferring control from one module to another. This is
done via the Call External Procedure (CXP) instruction.
o
GEN. ADDR. MODE
N
W
INDEX
BYTE
INDEX
BYTE
GEN
ADDR
MODE
A
IMM
t
~
iI
I
I
I
i
I
I
GEN
ADDR
MODE
B
OPCODE
j
TL/EE/8673-6
FIGURE 2-6. General Instruction Format
2-101
•
....
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
C')
C')
2.0 Architectural Description
(Continued)
BYTE DISPLACEMENT: RANGE -64 TO + 63
C'I
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode.
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
C')
U)
z
C;
SIGNED DISPLACEMENT
....
~
C')
C')
C'I
C')
U)
z
WORD DISPLACEMENT: RANGE -8192 TO + 8191
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
2.2.3 Instruction Set Summary
Table 2-2 presents a brief description of the Series 32000
instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
Notations:
i = Integer length suffix: B = Byte
W = Word
DOUBLE WORD DISPLACEMENT:
RANGE -(229 -2 24) to +(229 -1).
0
7
1
I
I
1
I
//-
D = Double Word
f = Floating Point length suffix: F = Standard Floating
L = Long Floating
TL/EE/8673-8
gen = General operand. Any addressing mode can be
specified.
FIGURE 2·8. Displacement Encodlngs
'Note: The pattern "11100000" for the most significant byte of the displacement Is reserved by National for future enhancements.
Therefore. It should never be used by the user program. This
causes the lower limit of the displacement range to be
- (229 - 224) Instead of - 229.
short = A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
imm = Implied immediate operand. An 8-bit value appended after any addressing extensions.
Memory Relative: A pOinter variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pOinter to generate the Effec·
tive Address of the operand.
disp = Displacement (addressing constant): 8, 16 or 32
bits. All three lengths legal.
reg = Any General Purpose Register: RO-R?
areg = Any Dedicated/ Address Register: SP, SB, FP,
MOD, INTBASE, PSR, US (bottom 8 PSR bits).
mreg = Any Memory Management Status/Control Register.
creg = A Custom Slave Processor Register (Implementation Dependent).
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
2-102
r--------------------------------------------------------------------------,
2.0 Architectural Description
Z
UJ
(0)
(Continued)
N
(0)
(0)
N
TABLE 2-1
.....
I
o
......
NS32332 Addressing Modes
ENCODING
Register
00000
OOOOt
00010
00011
00100
00101
00110
00111
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Memory Relative
10000
10001
10010
Reserved
10011
Immediate
10100
Absolute
10101
External
10110
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
N
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO or FO
RlorFl
R2 or F2
R3 or F3
R40rF4
R5 or F5
R60r F6
R7 or F7
None: Operand is in the specified
register
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(Rl)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Frame memory relative
Stack memory relative
Static memory relative
disp2(displ (FP))
disp2(displ (SP))
disp2(displ (SB))
Disp2 + Pointer; Pointer found at
address Displ + Register. "SP"
is either SPO or SPI , as selected
in PSR.
Immediate
value
None: Operand is input from
instruction queue.
Absolute
@disp
Disp.
External
EXT (displ) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Displ.
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Memory Space
11000
11001
11010
11011
Scaled Index
11100
11101
11110
11111
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
• +disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2x Rn.
EA (mode) + 4X Rn.
EA (mode) + B X Rn.
'Mode' and 'n' are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
(0)
(0)
~
.....
U1
(Reserved for Future Use)
Top of Stack
10111
Z
UJ
(0)
2-103
•
U)
.-
~
r---------------------------------------------------------------------------------~
2.0 Architectural Description
(Continued)
~
C")
TABLE 2-2
~
Series 32000 Instruction Set Summary
Ci
.~
C")
C")
('II
~
Z
MOVES
Format
4
2
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4-bit constant.
Move Multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move Effective Address.
INTEGER ARITHMETIC
Format
4
2
4
4
4
6
6
7
7
7
7
7
7
7
Operation
Operands
Description
ADDI
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEIi
DEli
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to Extended Integer.
Divide Extended Integer.
PACKED DECIMAL (BCD) ARITHMETIC
Format
6
6
Operation
Operands
Description
ADDPi
SUBPi
gen,gen
gen,gen
Add Packed.
Subtract Packed.
Operation
Operands
Description
CMPi
CMPQi
CMPMi
gen,gen
short,gen
gen,gen,disp
Compare.
Compare to signed 4-bit constant.
Compare Multiple: disp bytes (1 to 16).
Operation
Operands
Description
ANDi
ORi
BICi
XORi
COMi
NOTi
Scondi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Logical AND.
Logical OR.
Clear selected bits.
Logical Exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
INTEGER COMPARISON
Format
4
2
7
LOGICAL AND BOOLEAN
Format
4
4
4
4
6
6
2
2-104
z
2.0 Architectural Description
CJ)
Co)
I\)
Co)
Co)
I\)
(Continued)
SHIFTS
Format
6
6
6
....
I
Operation
LSHi
ASHi
ROTi
Operands
gen,gen
gen,gen
gen,gen
Description
Logical Shift, left or right.
Arithmetic Shift, left or right.
Rotate, left or right.
0
.......
Operation
Operands
Description
U1
TBITi
SBITi
SBITIi
CBITi
CBITli
IBITi
FFSi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Test bit.
Test and set bit.
Test and set bit, interlocked
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit
Z
CJ)
Co)
I\)
Co)
Co)
I\)
BITS
....
I
Format
4
6
6
6
6
6
8
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records
used in Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned
source.
Format
Operation
Operands
Description
8
8
7
7
8
EXTi
INSi
EXTSi
INSSi
CVTP
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm,imm
reg,gen,gen
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to Bit Field Pointer.
ARRAYS
Format
8
8
Operation
Operands
Description
CHECKi
INDEXi
reg,gen,gen
reg,gen,gen
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
STRINGS
String instructions assign specific functions to the General Purpose Registers:
Options on all string instructions are:
B (Backward):
Decrement string pOinters after each step
rather than incrementing.
U (Until match):
End instruction if String 1 entry matches
R4.
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
W (While match): End instruction if String 1 entry does not
match R4.
R1 - String 1 Pointer
RO - Limit Count
All string instructions end when RO decrements to zero.
Format
5
Operation
MOVSi
MOVST
Operands
options
options
Descriptions
Move String 1 to String 2.
Move string, translating bytes.
5
CMPSi
CMPST
options
options
Compare String 1 to String 2.
Compare translating, String 1 bytes.
5
SKPSi
SKPST
options
options
Skip over String 1 entries
Skip, translating bytes for Until/While.
2-105
an
,..
•
C'I
CO)
CO)
C'I
CO)
en
Z
......
0,..
•
C'I
CO)
CO)
C'I
CO)
en
Z
2.0 Architectural Description (Continued)
JUMPS AND LINKAGE
Format
Operation
3
JUMP
0
BR
0
Bcond
3
CASEi
2
ACBi
3
JSR
BSR
1
CXP
3
CXPD
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
1
RETI
Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
[reg IistJ.disp
[reg listl
disp
disp
disp
CPU REGISTER MANIPULATION
Format
Operands
Operation
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor Call.
Flag Trap.
Breakpoint Trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
Description
SAVE
RESTORE
LPRi
SPRi
ADJSPi
BISPSRi
BICPSRi
SETCFG
[reg listl
[reg listl
areg,gen
areg,gen
gen
gen
gen
[option listl
Save General Purpose Registers.
Restore General Purpose Registers.
Load Dedicated Register. (Privileged if PSR or INTBASE)
Store Dedicated Register. (Privileged if PSR or INTBASE)
Adjust Stack Pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set Configuration Register. (Privileged)
FLOATING POINT
Format
Operation
Operands
Description
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Move a Floating Point value.
Move and shorten a Long value to Standard.
Move and lengthen a Standard value to Long.
Convert any integer to Standard or Long Floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Polynomial Step.
Dot Product.
Binary Scale.
Binary Log.
Load FSR.
Store FSR.
2
2
3
3
3
5
11
9
9
9
9
9
9
11
11
11
11
11
11
11
12
12
12
12
9
9
MOVf
MOVLF
MOVFL
MOVif
ROUNDfi
TRUNCfi
FLOORfi
ADDf
SUBf
MULf
DIVf
CMPf
NEGf
ABSf
POLYf
DOn
SCALBf
LOGBf
LFSR
SFSR
2-106
z
2.0 Architectural Description
en
w
(Continued)
N
W
W
MEMORY MANAGEMENT
Format
14
14
14
14
8
8
Operation
Operands
Description
LMR
SMR
RDVAL
WRVAL
MOVSUi
mreg,gen
mreg,gen
gen
gen
gen,gen
Load Memory Management Register. (Privileged)
Store Memory Management Register. (Privileged)
Validate address for reading. (Privileged)
Validate address for writing. (Privileged)
Move a value from Supervisor
Space to User Space. (Privileged)
Move a value from User Space
to Supervisor Space. (Privileged)
MOVUSi
gen,gen
....~
o
.......
z
en
w
N
W
W
N
....•
CI1
MISCELLANEOUS
Format
Operation
Operands
NOP
WAIT
DIA
Description
No Operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
CUSTOM SLAVE
Format
Operation
Operands
Description
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.1
15.1
15.1
15.1
15.1
15.1
CCALOc
CCALlc
CCAL2c
CCAL3c
CMOVOc
CMOVlc
CMOV2c
CMOV3c
CCMPOc
CCMPlc
CCVOci
CCVlci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Custom Calculate.
15.1
15.1
LCSR
SCSR
gen
gen
Load Custom Status Register.
Store Custom Status Register.
15.0
15.0
CATSTO
CATSTI
gen
gen
Custom Address/Test. (Privileged)
(Privileged)
15.0
15.0
LCR
SCR
creg,gen
creg,gen
Load Custom Register. (Privileged)
Store Custom Register. (Privileged)
Custom Move.
Custom Compare.
Custom Convert.
2-107
fJI
.,...
it)
N
C")
3.0 Functional Description
C")
The following is a functional description of the NS32332
CPU.
N
C")
en
z
.....
CI
.,...
N
C")
C")
~
en
z
Each rising edge of PHI1 defines a transition in the timing
state ("T-State") of the CPU. One T-State represents the
execution of one microinstruction within the CPU, and/or
one step of an external bus transfer. See Sec. 4 for complete specifications of PHI1 and PHI2.
3.1 POWER AND GROUNDING
The NS32332 requires a single 5-volt power supply, applied
on 7 pins. The Logic Voltage pins (VeeL 1 and VeeL2) supply the power to the on-chip logic. The Buffer Voltage pins
(VeeBl to VeeB5) supply the power to the output drivers of
the chip. The Logic Voltage pins and the Buffer Voltage pins
should be connected together by a power (Vecl plane on
the printed circuit board.
PHil
The NS32332 grounding connections are made on 8 pins.
The Logic Ground pins (GNDL1 and GNDL2) are the ground
pins for the on-chip logic. The Buffer Ground pins (GNDB1
to GNDB6) are the ground pins for the output drivers of the
chip. The Logic Ground pins and the Buffer Ground pins
should be connected together by a ground plane on the
printed circuit board.
PHI2
In addition to Vee and Ground, the NS32332 CPU uses an
internally-generated negative voltage. It is necessary to filter
this voltage externally by attaching a pair of capacitors (Figure 3. 1) from the BBG pin to Ground.
TLlEE/B673-9
FIGURE 3-2. Clock Timing Relationships
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHI1 and PHI2
be kept as short as pOSSible, and that they not be connected anywhere except from the TCU to the CPU and, if present, the MMU. A TTL Clock signal (CTTL) is provided by the
TCU for all other clocking.
Recommended values for these are:
C1: 1 ,..F, Tantalum
C2: 1000 pF, Low inductance. This should be either a disc
or monolithic capaCitor.
3.3 RESETTING
The RST / ABT pin serves both as a Reset for on-chip logic
and as the Abort input for Memory-Managed systems. For
its use as the Abort Command, see Sec. 3.5.2.
The DT/SDONE pin is sampled on the riSing edge of PHI1,
one cycle before the reset signal is deasserted to select the
data timing during write cycles. If DT/SDONE is sampled
high, ADO-AD31 are floated during state T2 and the data is
output during state T3. This mode must be selected if an
MMU is used (Section 3.5). If DT/SDONE is sampled low,
the data is output during state T2. See Figure 3-7.
The CPU may be reset at any time by pulling the RSf / ABT
pin low for at least 64 clock cycles. Upon detecting a reset,
the CPU terminates instruction proceSSing, resets its inter·
nal logic, and clears the Program Counter (PC) and Processor Status Register (PSR) to all zeroes.
On application of power, RST/ABT must be held low for at
least 50 ,..sec after Vee is stable. This is to ensure that all
+5V
TLlEE/B673-11
FIGURE 3-1_ Recommended Supply Connections
3.2 CLOCKING
The NS32332 inputs clocking signals from the Timing Control Unit (TCU), which presents two non-overlapping phases
of a single clock frequency. These phases are called PHI1
(pin A7) and PHI2 (pin B8). Their relationship to each other
is shown in Figure 3-2.
vee
PHil ---t--~
RsT/ABr
----t---------fJ-JI
TL/EE/B673-l0
FIGURE 3-3. Power·on Reset Requirements
2-108
z
3.0 Functional Description
en
Co)
(Continued)
N
on-chip voltages are completely stable before operation.
Whenever a Reset is applied, it must also remain active for
not less than 64 clock cycles. See Figures 3-3 and 3-4.
The Timing Control Unit (TCU) provides circuitry to meet the
Reset requirements of the NS32332 CPU. Figure 3-5a
shows the recommended connections for a non-MemoryManaged system. Figure 3-5b shows the connections for a
Memory-Managed system.
PHll~Jl-Jl
I---
iiST/ABT---....,~.................
l!:
I
64 CLOCK-I
C~CLES
Co)
Co)
....~
o
.......
z
en
Co)
N
TL/EE/8673-12
FIGURE 3-4. General Reset Timing
Co)
Co)
N
....•
U1
VCC
cpu
TCU
1"-------------.
I
I
II mr--SET
t:~+I-~_1--~---~~~----.~
I
RsTO
RSTI
1----------1 RsT/ABr
!L. _____________ .J:
EXTERNAL RESET
(OPTIONAL)
l!: 501'88C
RESET SWITCH
(OPTIONAL)
SYSTEM RESET
TLlEE/8673-13
FIGURE 3-5a. Recommended Reset Connections, Non-Memory-Managed System
VCC
MMU
TCU
CPU
1"-------------.
I
I
II RESET
E>--+I-~_1--~--.....~+-----~
iiSri
RsTO
!L. _____________ .JI
EXTERNAL RESET
(OPTIONAL)
i!: 50p.sec
RESET SWITCH
(OPTIONAL)
TL/EE/8673-14
FIGURE 3-5b. Recommended Reset Connections, Memory-Managed System
difference between them is the 4·bit code placed on the Bus
Status pins (STO-ST3). Slave Processor cycles differ in that
separate control signals are applied (Sec. 3.4.6).
3.4 BUS CYCLES
The NS32332 CPU will perform Bus cycles for one of the
following reasons:
1) To write or read data to or from memory or peripheral
interface device. Peripheral input and output are memory
mapped in the Series 32000 family.
2) To fetch instructions into the 20·byte instruction queue.
This happens whenever the bus would otherwise be idle
and the queue is not already full.
For case 1 (only Read) and case 2, the NS32332 supports
Burst cycles which are suitable for memories that can handle "nibble mode" accesses. (Sec. 3.4.2).
The sequence of events in a non-Slave, non-Burst Bus cycle is shown in Figure 3-6 for a Read cycle, and Figure 3-7
for a Write cycle. The cases shown assume that the selected memory or interface device is capable of communicating
with the CPU at full speed. If it is not, then cycle extension
may be requested through the RDY line (Sec. 3.4.1).
A full speed Bus cycle is performed in four cycles of the
PHI1 clock,labeled T1 through T4. Clock cycles not associated with a Bus cycle are designated Ti (for idle).
3) To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
4) To transfer information to or from a Slave Processor.
In terms of bus timing, cases 1 through 3 above are identical. For timing speCifications, see Sec. 4. The only external
2·109
3.0 Functional Description (Continued)
NS32332 CPU BUS SIGNALS
Tl
PHil
[
PHI 2
[
ADO-AD31
[
STS
[
ADS
[
STD-ST3
T3
T4
I
TlORTi
I
[
ODiN
[
iEii-i'E3
[
BWO-BWI
[
ROY
T2
[
TL/EE/B673-15
FIGURE 3-6_ Read Cycle Timing
2-110
3.0 Functional Description
zCJ)
Co)
(Continued)
N
Co)
Co)
N
....o
NS32332 CPU BUS SIGNALS
I
Z
CJ)
Co)
N
Co)
Co)
N
....
I
en
fII
TLlEE/B673-16
FIGURE 3-7. Write Cycle Timing
2-111
~
po
~
C")
C")
C'I
C")
U)
z
......
Q
po
~
C")
C")
C'I
C")
U)
z
r---------------------------------------------------------------------------------,
3.0 Functional Description (Continued)
During T4 or Ti which preceed T1 of the current Bus cycle,
the CPU applies a Status Code on pins STO-ST3. It also
provides a low-going pulse on the STS pin to indicate that
the status code is valid.
If the CPU is performing a Read cycle, the Data Bus (ADOAD31) is sampled on the falling edge of PHI2 of the last T3
state. See Sec. 4. Data must, however, be held at least until
the beginning of T4. The T4 state finishes the Bus cycle .
Data from the CPU during Write cycles remains valid
throughout T4. Note that the Bus Status lines (STO-ST3)
change at the beginning of T4, anticipating the following bus
cycle (if any).
The ADS signal has the dual purpose of informing the external circuitry that a Bus cycle is starting and of providing
control to an external latch for demultiplexing address bits
0-31 from ADO-AD31 pins. (See Figure 3-8.)
During this time, the control signal iJDijij, which indicates
the direction of the transfer, and BEO-BE3 which indicate
which of the four bus bytes to be referenced, become valid.
Note that during Instruction Fetch cycles BEO-BE3 are all
active, but in operand Read or Write cycles they indicate the
byte(s) to be referenced.
3,4.1 Cycle Extension
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32332 provides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-7 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are flat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the ROY (Ready) pin.
In the middle of T3 on the falling edge of PHI1, the RDY line
is sampled by the CPU. If RDY is high, the next T-state will
be T4, ending the bus cycle. If ROY is low, then another T3
state will be inserted and the ROY line will again be sampled
on the falling edge of PHI1. Each additional T3 state after
the first is referred to as a "WAIT STATE". See Figure 3-9.
Note: II a burst cycle occurs during an operand read. all the memory banks
should be enabled, during the burst cycle, regardless of BEn. The
CPU BEn lines, In this case, are valid in the middle of T3 of the burst
cycle-thus, there may not be enough time to selectively enable the
different memory banks, unless a WAIT state is added. See Figure
4·6.
During T2 the CPU floats ADO-AD31 lines unless
DT/SDONE is sampled Iowan the rising edge of reset and
the bus cycle is a write cycle. T2 is a time window to be
used for virtual to physical address translation by the Memory Management Unit, if virtual memory is used in the system.
The T3 state provides for access time requirements and it
occurs at least once in a bus cycle. In the middle of T3 on
the falling edge of PHI1, the ROY line is sampled to determine whether the bus cycle will be extended (Sec. 3.4.1).
ODIN
Figure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the ROY pin.
r-----------~~
TL/EE/B673-17
FIGURE 3-8. Bus Connections
2-112
3.0 Functional Description
(Continued)
n
T2
T3
(WAIT)
T3
T4
PHil
PHI2
ROY
TLlEE18673-18
FIGURE 3-9. ROY Pin Timing
NS32332 CPU BUS SIGNALS
PREV.CYCLE
\T40R Ti \
Tl
T2
I (W~IT) I (vlllT) I
NEXT CYCLE
13
T4
InoRTi
I
PHil [
PHI2 [
AOO-A023 [
STS [
ADs
[
STo-ST3
[
DoiN
[
m-iiEi
[
ROY [
TLIEE18673-19
FIGURE 3-10. Extended Cycle Example
2-113
....
~ r-----------------------------------------------------------------------------~
~
a
....~o
....
~
I
3.0 Functional Description (Continued)
3.4.2 Burst Cycles
The NS32332 is capable of performing Burst cycles in order
to increase the bus throughput. Burst is available in instruction Fetch cycles and operand Read cycles only. Burst is
not supported in operand Write cycles or Slave cycles.
The sequence of events for Burst cycles is shown in Figuf9
3-". The cases shown assume that the selected memory is
capable of communicating with the CPU at full speed. If it is
T4
not, then cycle extension may be requested through the
RDY line (Sec. 3.4.1).
A Burst cycle is composed of two parts. The first part is a
regular cycle (i.e. Tl through T4), in which the CPU outputs
the new status and asserts all the other relevant control
signals discussed in Sec. 3.4. In addition, the Burst Out Signal (BOUT) is activated by the CPU indicating that the CPU
can perform Burst cycles. If the selected memory allows
Tl
T3
T4
T4
T3
T4
PIli 1 [
PIli 2 [
m[
ADS [
mIT [
liN [
--cp- --¢----¢--
ADO-AD31 [
TUEE/8673-2()
(a) Normal Termination of Burst
Ta
T4
T3
T4
PIli 1 [
PHI 2 [
IIIR[
ADO-ADal
[-+---I''--+'
--cp-- -¢-TL/EE/8673-21
(b) External Termination of Burst
FIGURE 3·11_ Burst Cycles (For Read Only)
2-114
3.0 Functional Description (Continued)
Burst cycles, it will notify the CPU by activating the burst in
signal (BIN). BIN is sampled by the CPU in the middle of T3
on the falling edge of PHil. If the memory does not allow
burst (BIN high), the cycle will terminate through T4 and
BOUT will go inactive immediately. If the memory allows
burst (BIN low), and the CPU has not deasserted BOUT, the
second part of the Burst cycle will be performed (see Figure
3-11) and BOUT will remain active until termination of the
Burst.
3. The data operand has been completely read. This applies
to burst read cycles for non-aligned operands or when
the bus width is either 8 or 16 bits.
4. BIN, sampled in the current nibble's last T3, is not active
any more. (See Figure 3. 11b).
5. Bus Error or Bus Retry occurs (see Sec. 3.4.8).
6. A HOLD Request occurs.
Any nibble's T3 may be extended with WAIT states using
the ROY line as described in Sec. 3.4.2.
The second part consists of up to 3 nibbles. In each nibble,
a data item is read by the CPU. The duration of each nibble
is 2 clock cycles labeled T3 and T4.
The control signals BOUT, STO-ST3, and ODIN remain stable during the Burst chain.
The Burst chain will be terminated in the following cases:
BEO-BE3 are adjusted for every nibble in operand cycles.
1. The CPU has reached a 16 byte boundary i.e. the byte
address of the current nibble is x... xll11 (binary).
BOUT is initially set by the CPU according to the known bus
width. Its state may change in a subsequent T3 as a result
of a change in the bus width. Figure 3-12 shows the resulting BOUT timing.
2. The CPU detects that the instructions being prefetched
(in Burst Mode) are no longer needed due to an alteration
of the flow of control. This happens, for example, when a
branch instruction is executed or an exception occurs.
Note: If the selected memory is capable of handling burst transfers, it
should activate BiJiI regardless of the state of lIDll'i'.
The reason is that BOUT may be activated by the CPU after the BIN
sampling time. The liOiJf signal Indicates when the CPU Is going to
burst, and should not be Interpreted as a 'Burst Request' signal.
Note: In 16-blt bus systems (see Sec. 3.4.7) the Burst chain will be terminated by the CPU on an a.byte boundary i.e. address x•.x111 (binary) and
in a·blt bus system on a 4.byte boundary i.e. address x...x11 (binary).
PHil
~
PHI2 [
ADS [
11
T2
T3
T3
T3
l--rL ~ r-- r1 r-- r1 -'---I
n
--rL r---
/
\.
RDY [
T4
X
BWO-l [
BIN [
/
(1) Biilii' [
\.
(2) BOUT [
TL/EE/8673-88
Note 1: CPU deasserts BOUT.
Note 2: CPU asserts liOiJf.
FIGURE 3·12_ BOUT Timing Resulting from a Bus Width Change
2-115
.... ,--------------------------------------------------------------------------,
~
~
CO)
CO)
IN
CO)
fJ)
z
~
....
~
CO)
CO)
IN
~
Z
3.0 Functional Description
(Continued)
3.4.3 Bus Status
1000 - Sequential Instruction Fetch.
The CPU is reading the next sequential word
from the instruction stream into the Instruction
Queue. It will do so whenever the bus would otherwise be idle and the queue is not already full.
1001 - Non-Sequential Instruction Fetch.
The NS32332 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on these
pins indicate why the CPU is performing a bus cycle, or, if it
is idle on the bus, then why is it idle.
Referring to Figures 3-6 and 3-7, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1, and changing to the next state at T4. This allows
the system designer to fully decode the Bus Status and, if
desired, latch the decoded Signals before ADS initiates the
Bus Cycle.
The Bus Status pins are interpreted as a four-bit value, with
STO the least significant bit. Their values decode as follows:
The CPU is performing the first fetch of instruction code after the Instruction Queue is purged.
This will occur as a result of any jump or branch,
or any interrupt or trap, or execution of certain
instructions.
1010 - Data Transfer.
The CPU is reading or writing an operand of an
instruction.
0000 - The bus is idle because the CPU does not yet
need to perform a bus access.
1011 - Read RMW Operand.
0001 - The bus is idle because the CPU is executing the
WAIT instruction.
0010 - (Reserved for future use.)
0011 - The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100 - Interrupt Acknowledge, Master.
The CPU is reading an operand which will subsequently be modified and rewritten. If memory protection circuitry would not allow the following
Write cycle, it must abort this cycle.
1100 - Read for Effective Address Calculation.
The CPU is reading information from memory in
order to determine the Effective Address of an
operand. This will occur whenever an instruction
uses the Memory Relative or External addressing
mode.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt
(on NMI) it will read from address FFFFFF0016,
but will ignore any data provided.
To acknowledge receipt of a Maskable Interrupt
(on INT) it will read from address FFFFFE0016,
expecting a vector number to be provided from
the Master Interrupt Control Unit. If the vectoring
mode selected by the last SETCFG instruction
was Non-Vectored, then the CPU will ignore the
value it has read and will use a default vector
instead. See Sec. 3.4.5.
1101 - Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing the Operation Word of a Slave Processor instruction. See Sec. 3.9.1.
1110 - Read Slave Processor Status.
The CPU is reading a Status Word from a Slave
Processor. This occurs after the Slave Processor
has signalled completion of an instruction. The
transferred word tells the CPU whether a trap
should be taken, and in some instructions it presents new values for the CPU Processor Status
Register bits N, Z, Lor F. See Sec. 3.9.1.
0101 - Interrupt Acknowledge, Cascaded.
The CPU is reading a vector number from a Cascaded Interrupt Control Unit. The address provided is the address of ICU's Hardware Vector register. See Sec. 3.4.6.
0110 - End of Interrupt, Master.
1111 - Broadcast Slave 10.
The CPU is initiating the execution of a Slave
Processor instruction. The 10 Byte (first byte of
the instruction) is sent to all Slave Processors,
one of which will recognize it. From this point the
CPU is communicating with only one Slave Processor. See Sec. 3.9.1.
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt (RETI)
instruction. See Sec. 3.4.6.
0111 - End of Interrupt, Cascaded.
The CPU is reading from a Cascaded Interrupt
Control Unit to indicate that it is returning
(through RETI) from an interrupt service routine
requested by that unit. See Sec. 3.4.6.
2-116
3.0 Functional Description
(Continued)
3.4.4 Data Access Sequences
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-States separating
them. The number of bus cycles required to transfer an operand depends on its size and its alignment. Table 3-2 lists
the bus cycles performed for each situation.
The 32-bit address provided by the NS32332 is a byte address; that is, it uniquely identifies one of up to 4 billion
eight-bit memory locations. An important feature of the
NS32332 is that the presence of a 32-bit data bus imposes
no restrictions on data alignment; any data item, regardless
of size, may be placed starting at any memory address. The
NS32332 provides special control signals. Byte Enable
(BEO-BE3) which facilitate individual byte accessing on a
32-bit bus.
3.4.4.1 Bit Accesses
The Bit Instructions perform byte accesses to the byte containing the designated bit. The Test and Set Bit instruction
(SBIT), for example, reads a byte, alters it, and rewrites it,
having changed the contents of one bit.
Memory is organized as four eight-bit banks, each bank receiving the double-word address (A2-A31) in parallel. One
bank, connected to Data Bus pins ADO-AD? is enabled
when BEO is low. The second bank, connected to data bus
pins AD8-AD15 is enabled when BE1 is low. The third and
fourth banks are enabled by BE2 and BE3, respectively.
See Figure 3-13.
3.4.4.2 Bit Field Accesses
An access to a Bit Field in memory always generates a Double-Word transfer at the address containing the least significant bit of the field. The Double Word is read by an Extract
instruction; an Insert instruction reads a Double Word, modifies it, and rewrites it.
3.4.4.3 Extending Multiple Accesses
The Extending Multiply Instruction (MEl) will return a result
which is twice the size in bytes of the operand it reads. If the
multiplicand is in memory, the most-significant half of the
result is written first (at the higher address), then the leastsignificant half. This is done in order to support retry if this
instru'ction is aborted.
3.4.5 Instruction Fetches
Instructions for the NS32332 CPU are "prefetched"; that is,
they are input before being needed into the next available
entry of the twenty-byte Instruction Queue. The CPU performs two types of Instruction Fetch cycles: Sequential and
Non-Sequential. These can be distinguished from each other by their differing status combinations on pins STO-ST3
(Sec. 3.4.3).
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full. Sequential Fetches are always
type 10 Read cycles (Table 3-1).
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the instruction queue, causing the
next instruction fetch to display Non-Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status, and that cycle depends on the destination address.
If a non-sequential fetch is followed by additional sequential
fetches which are burst continuation of the non-sequential
fetch, then the Status Bus (STO-ST3) remains the same.
TLlEE/B673-22
FIGURE 3-13. Memory Interface
Since operands do not need to be aligned with respect to
the double-word bus access performed by the CPU, a given
double-word access can contain one, two, three, or four
bytes of the operand being addressed, and these bytes can
begin at various positions, as determined by A1, AO. Table
3-1 lists the 10 resulting access types.
Nole 1: During instruction fetch cycles, SEO-SE3 are all active regardless
of the alignment.
TABLE 3-1
Bus Access Types
Type Bytes Accessed A 1,AD BE3 BE2 BE1 BED
1
1
00
1
0
2
01
0
1
3
10
1
0
4
11
0
1
5
2
00
0
0
6
2
01
1
0
0
?
2
10
1
0
0
8
3
00
1
0
0
0
9
3
01
0
0
0
10
4
00
0
0
0
0
Note 2: During Operand Access cycles BEQ-BE3 are activated as if the bus
is 32 bits wide, regardless of the real width.
3.4.6 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is interrupt control rather
than the transfer of instructions or data. Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status presented on pins STO-ST3. All
Interrupt Control cycles are single-byte Read cycles.
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine.
2-117
.... r---------------------------------------------------------------------------------,
U)
c:..
CO)
CO)
3.0 Functional Description (Continued)
:a.....z
TABLE 3·2
Access Sequences
Data Bus
....
o
c:..
CO)
CO)
eN
~
Z
I
Cycle
Type
Address
'\
Byte 3
B~e2
A. Word at address ending with 11
1.
2.
4
A
o
Byte 0
o
A+1
9
A
X
o
o
o
A+3
7
5
A
o
4
8
o
Byte 1
Byte 0
X
X
X
X
Byte 3
1
Byte 1
Byte 0
X
X
o
X
X
Byte 3
Byte 2
IBYTE31BYTE21BYTE11BYTEoi -
o
E. Quad word at address endIng with 00
0
10
A
o
o
o
Other bus cycles (instruction prefetch or slave) can occur here.
2.
10
A+ 4
0
0
0
1.
2.
7
A
o
X
X
X
Byte 3
Byte 2
Byte 1
o
Byte 3
Byte 2
Byte 1
Byte 0
0
Byte 7
Byte 6
Byte 5
Byte 4
Byte 2
Byte 1
Byte 0
o
X
X
X
X
Byte 3
0
Byte 6
X
Byte 5
X
Byte 4
X
X
Byte 7
I BYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 0
o
5
A+2
o
Other bus cycles (instruction prefetch or slave) can occur here.
3.
7
A + 4
0
0
1
4.
5
A+ 6
1
1
0
H. Quad word at address ending with 11
X
IBYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 0 I -
1.
9
A
o
o
o
2.
A+3
Other bus cycles (instruction prefetch or slave) can occur here.
3.
9
A+ 4
0
0
0
4.
A+ 7
1
1
G. Quad word at address ending with 10
0
Byte 0
I BYTE7IBYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 01 -
1.
F. Quad word at address endIng with 01
X
Byte 2
o
I-
Byte 1
Byte 0
X
X
o
X
X
Byte 3
Byte 2
1
0
Byte 5
X
Byte 4
X
X
Byte 7
X
Byte 6
I BYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 0 I -
1.
4
A
0
1
2.
8
A+1
0
0
Other bus cycles (instruction prefetch or slave) can occur here.
1.
4
A+4
0
1
1
2.
8
A+5
0
0
X = Don't Care
2-118
A
Byte 1
I BYTE 31 BYTE 21 BYTE 11BYTEoi -
o
A+2
A
A+1
X
X
o
D. Double word at address ending with 11
1.
2.
X
X
IBYTE31BYTE21BYTE11BYTEoi -
C. Double word at address ending with 10
1.
2.
B~eO
I BYTE 1 I BYTE 01 -
B. Double word at address ending with 01
1.
2.
B~e1
Byte 0
X
X
X
0
X
Byte 3
Byte 2
Byte 1
1
0
Byte 4
X
X
X
X
Byte 7
Byte 6
Byte 5
A
A
A
A
A
A
A
3.0 Functional Description
z
en
Co)
I\)
Co)
Co)
I\)
(Continued)
TABLE 3-3
Interrupt Sequences
,
.....
0
Data Bus
(~
__________A-__________
~
\
Cycle
Status
Address
Interrupt Acknowledge
1
0100
FFFFFF0016
ODIN
BE3
BE2
BE1
BEO
Byte 3
A. Non-Maskable Interrupt Control Sequences
Byte 2
Byte 1
Byte 0
......
Z
en
Co)
I\)
Co)
Co)
I\)
,
.....
(J'J
o
o
X
X
X
X
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
B. Non- Vectored Interrupt Control Sequences
Interrupt Acknowledge
1
0100
FFFFFE0016
o
o
X
X
X
X
Interrupt Return
0110
1
o
o
X
X
X
X
FFFFFE0016
C. Vectored Interrupt Sequences: Non-Cascaded.
Interrupt Acknowledge
1
0100
FFFFFE0016
o
o
X
X
X
Vector:
Range: 0-127
Interrupt Return
0110
1
o
o
X
X
X
Vector: Same as
in Previous In!.
Ack. Cycle
X
X
Cascade Index:
range -16 to -1
FFFFFE0016
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
1
0100
FFFFFE0016
o
o
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
0
See Note
Address
Interrupt Return
0110
1
FFFFFE0016
(The CPU here uses the Cascade Index to find the Cascade Address)
2
0111
Cascade
0
See Note
Address
X
=
Vector, range 9-255; on appropriate byte of
data bus.
o
o
X
X
X
X
X
X
X
Cascade Index:
Same as in
previous In!.
Ack. Cycle
X
Don't Care
Note: BEO-BE3 signals will be activated according to the cascaded
leu address. The cycle type can be 1,2,3 or 4, when reading the interrupt vector. The vector
value can be in the range 0-255.
2-119
EI
....
U) r-------------------------------------------------------------------------------~
~
C")
C")
C'I
C")
en
z
.....
o
....
~
C")
C")
C'I
~
Z
3.0 Functional Description (Continued)
3.4.7 Dynamic Bus Configuration
The NS32332 interfaces to external data buses with 3 different widths: a-bit, 16-bit and 32-bit. The NS32332 can switch
from one bus width to another dynamically i.e. on a cycle by
cycle basis.
This feature allows the user to include in his system different bus sizes for different purposes, like a-bit bus for bootstrap ROM and 32-bit bus for cache memory, etc.
In each memory cycle, the bus width is determined by the
inputs BWO and BW1.
If the bus width didn't change from the previous memory
cycle, the CPU terminates the cycle normally.
If the bus width of the current cycle is different from the bus
width of the previous cycle, then two WAIT states (see Sec.
3.4.1) must be inserted in order to let the CPU switch to the
new width.
The additional 2 WAIT states count from the moment BWO
BW1 change. This can be overlapped with the wait states
due to slow memories.
Nole: 8WO-8WI can only be changed during the first T3 state of a memory
access cycle. They should be externally latched and should not be
changed at any other time.
Four combinations exist:
BW1
BWO
0
0
1
1
0
1
0
1
In write cycles, the appropriate data will be present on the
appropriate data lines. The CPU presents the data during T3
in a way that would fit any bus width.
reserved
a-bit bus
16-bit bus
32-bit bus
If the operand being written is a byte, it will be duplicated on
the 4 bytes ADO-AD31 depending on the operand address:
Address AO-1 =
The dynamic bus configuration is not applicable for slave
cycles (see Sec. 3.4.1).
The BWO-BW1 lines are sampled by the CPU in T3 with the
falling edge of PHI1 (see Figure 3-14).
T4
TI
I
T2lTmmu
I
T3
T3
T3
T4
00
01
10
11
T1
XX
XX
XX
OP
I
XX
XX
OP
XX
T2/Tmmu
XX
OP
XX
OP
OP
OP
OP
OP
I
T3
PHil [
PHI 2 [
ROY [
8WO-8WI [
-+---+--fo--oIf
TL/EE/8673-23
FIGURE 3-14. Bus width changes. Two wait states are required after the signals BWO-BW1 change.
2-120
z
3.0 Functional Description
(J)
Co)
(Continued)
N
If the operand being written is a word, 4 cases exist. The
operand address can be X ••• xOO (binary) or x... x01 (binary) or
x...x10 or x ... x11 (binary).
CPU writes a double word operand to a 16-bit bus and the
operand address is x... x11 (binary) it needs three memory
cycles.
The description above applies to the first cycle. In the other
2 memory cycles belonging to the same operand, the data
will be presented on the data bus lines to fit 16-bit bus width
and take into account the operand length.
See the duplications for each case:
OPERANO STARTS HERE
11
"T -
A1AO
-
01
10
t
Example:
The CPU has to write a double word DDCCBBAA to address
HEX 987653 which is in a 16-bit bus area. In the first cycle,
the CPU does not know the width until T3 so it generates a
cycle to address 987653 which activates the BE3 line and
puts on the data bus AA XX AA AA (X = don't care). After
this cycle, the CPU knows it has a 16-bit bus and it generates a cycle to address 987654 which activates the BEO,
BE1 and BE2 lines and puts on the data bus XX XX CC BB.
The last cycle will address 987656, activate BE2, and put on
the data bus XX XX XX DD. The BEO-BE3 lines are always
activated as if the bus is 32-bit wide, regardless of BWOBW1 state.
The CPU does not support a change of the bus width during
a sequence of several memory references belonging to the
same operand e.g. nonaligned double word. In other words,
any operand should not be split between two memory
spaces having different bus widths .
Instruction Fetches do not fall in this category and an Instruction Fetch can have its own bus width regardless of the
bus width in the previous cycle.
00
-r---t--r--r---,
I OP
: HIGH
..1. ___ L-_....L._...L.._.....L_----I
11
01
00
10
TLlEE/8673-25
OPERAND STARTS HERE ---.
Co)
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....~
o
.....
Z
(J)
Co)
N
Co)
Co)
N
....
I
U1
3.4.8 Bus Exceptions
Any bus cycle may have a bus error during its execution.
The error may be corrected during the current cycle or may
be incorrectable. The NS32332 can handle both types of
errors by means of BUS RETRY and BUS ERROR.
T---r---~--~---+---'
I OP
I HIGH 2
3.4.8.1 Bus Retry
If a bus error can be corrected, the CPU may be requested
to repeat the erroneous bus cycle. The request is done by
asserting the BRT (Bus Retry) signal.
.L ___ '--__.....L..__--I____- ' -__.....J
T- - i - -
The CPU response to Bus Retry depends on the cycle type:
-...----.,......--+---...,---....,
Instruction Fetch Cycle-If the RETRY occurs during an
instruction fetch, the fetch cycle will be retried as soon as
possible. If the RETRY is requested during a burst chain,
the burst is stopped and the fetch is retried. The only delay
in retrying the instruction fetch may result from pending operand requests (and, of course, from hold or wait requests).
I OP I OP
I HIGH 2 I HIGH 1
..L _ _ .1 ___,....._-'-_ _......_ ......_---'
T- - i - - T- - - r--r-...,----.--....,
The fetch cycle will be retried only if there are no more than
four bytes in the queue .
Operand Read Cycle-If the RETRY occurs on an operand
read, the bus cycle is immediately repeated. If the data read
is "multiple" e.g. non-aligned, only the problematic part will
be repeated. For instance, if the cycle is a non-aligned double word and the second half failed, only the second part
will be repeated. The same applies for a RETRY occurring
during a burst chain. The repeated cycle will begin where
the read operand failed (rather than the first address of the
burst) and will finish the original burst.
10PIOPIOP
HIGH 2 I HIGH 1 I LOW2
.LI __
..I. __ ..1 ___ '--__-'-__'---__-'-__.....
A1 AD
11
10
01
00
TL/EE/8673-26
If the operand being written is a double word 4 cases exist:
The operand address can be x... xOO (binary) or x ... x01 (binary) or x ... x10 (binary) or x ... x11 (binary).
See the duplications for each case:
Note that the organization of the operand described applies
to the initial part of the operand cycle. For instance, if the
2-121
fII
.... ,-----------------------------------------------------------------------------,
~
a
ic;
....
~
CW)
~
3.0 Functional Description (Continued)
Operand Write Cycle-If the RETRY occurs on a write, the
bus cycle is immediately repeated. If the operand write is
"multiple" e.g. non-aligned, only the problematic part will be
repeated. For instance, if the cycle is a non-aligned double
word and the second half failed, only the second part will be
repeated.
cycle will be repeated, i.e. a new T4 for setting the Status
Bus and issuing STS and then T1 through T4 will be performed.
Although the decision about Retry is taken by the CPU on
T4, BRT must have an early activation in T3 as described
above in order to prevent the internal pipeline to advance.
Holding the pipeline allows the repeated cycle to override
the original one. If BRT is activated only in T3 and not in T4,
there might be one cycle penalty in the performance of the
execution unit in operand read cycles.
Retry is applicable for regular memory cycles and burst cycles, but not for Slave cycles.
A Bus Retry is requested by activating the BRT line (see
Figure 3-15). EiR'i' is sampled by the CPU during T3 on the
falling edge of PHI1. If BRT is inactive, the cycle will be
terminated in a regular way. In this case BRT must also be
kept Inactive during T4. If BRT is active, EiR'i' will be sampled again during T4 on the falling edge of PHI1. If BRT is
inactive, the cycle will be terminated In a regular way. If BRT
is active, T4 will be followed by an idle state and the
T4
T1
I T2/Tmmu I
T3
T4
I
TI DR T1
I
TL/EE/8673-27
(a) Bus Cycle Not Retried
T4
Tl
I
T2/Tmmu
I
T3
T4
TI
T4
Tl
I
T2/Tmmu
I
PIli 1 [
PIli 2 [
TL/EE/8673-28
(b) Bus Cycle Retried
FIGURE 3-15. Bus Cycle Retry
2-122
z
3.0 Functional Description
en
Co)
(Continued)
N
3.4.8.2 Bus Error
Operand Write Cycles-If the bus error occurs on an operand write, the exception is immediately accepted.
If a Bus Error is incorrectable the CPU may be requested to
abort the current process and branch to an appropriate routine to handle the error. The request is performed by activating the BER signal.
BER is sampled by the CPU during T4 on the falling edge of
PHI1. If BER is active the bus will go to Tidle after T4 and
the CPU will jump to the Bus Error handler (see Sec. 3.8).
Note 1: When a bus error occurs, the Instruction that caused the error is
generally not re·executable.
The process that was being executed should either be aborted or
should be restarted from the last checkpoint.
Note 2: Bus error has top priority and is accepted even during the acknowl·
edge sequence of another CPU exception (i.e. Abort, Interrupt, etc.).
It is the responsibility of the user software to detect such an occurence and to take the appropriate corrective actions.
The CPU response to Bus Error depends on the cycle type:
Operand Read Cycles-If the bus error occurs on an operand read, the bus error is immediately accepted, and the
CPU enters the BUS ERROR exception.
T1
I
T2ITmmu
....~
....Z
Q
~
N
Co)
Co)
....~
UI
3.4.8.3 Fatal Bus Error
As previously mentioned, the CPU response to a bus error is
to interrupt the current activity and enter the error routine.
An exception to this rule occurs when a bus error is signalled to the CPU during the acknowledge of a previous bus
error. In this case the second error is interpreted by the CPU
as a fatal bus error.
The CPU will respond to this event by halting execution and
floating ADS, BEO-BE3, DDIN, STS and ADO-AD31.
The Halt condition is indicated by the setting of STO-ST3 to
zero and by the assertion of MC/EXS for more than one
clock cycle (see Sec. 4.1.3).
The CPU can exit this condition only through a hardware
reset.
Instruction Fetch Cycles-If the bus error occurs on an
instruction fetch, additional fetches are inhibited including
the one which failed. If, after inhibiting instruction fetches,
some operand cycles are still pending within the CPU, they
are executed normally, delaying the access to the bus error
exception. If and when the internal instruction queue becomes empty, the CPU will enter the BUS ERROR exception. This arrangement enables the CPU to ignore bus errors
which belong to fetch ahead cycles if these fetches are not
to be used as a result of a jump.
T4
.
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I
T3
T4
TI
TI
PHil [
PHI2 [
m[
•
AtiS[
m[
TUEE/B673-30
FIGURE 3·16. Bus Error During Read or Write Cycle
2-123
U)
..-
N
CW)
CW)
C'I
CW)
U)
Z
.....
o
..-
N
CW)
CW)
C'I
CW)
en
z
r-------------------------------------------~------------------------------------,
3.0 Functional Description
(Continued)
A
AIJO.AD31
3.4.9 Slave Processor Communication
The SPC pin is used as the data strobe for Slave Processor
transfers. In this role, it is referred to as Slave Processor
Control (SPC). In a Slave Processor bus cycle, data is transferred on the Data Bus and the status lines (STO-ST3) are
monitored by each Slave Processor in order to determine
the type of transfer being performed. SPC is bidirectional,
but is driven by the CPU during all Slave Processor bus
cycles. See Sec. 3.9 for full protocol sequences.
SPC
...
'"
IJO.D31
SPC
cpu
SLAVE
PROCESSOR
STO-ST3
STO-ST3
iii'/SDDNE
SiiONE
NS32332
TL/EE/8673-31
FIGURE 3-17. Slave Processor Connections
PREVo CYCLE
I
PHil
[
PHIZ
[
T40rTi
NEXT CYCLE
Tl
T4
Tl0RTi
I
spc[
ACO·AC31 [
STO-ST3
[
ADS
[
.Lf""""".L.I.""4-'1
5DiN[
Notes:
TUEE/8673-32
(1) CPU samples Data Bus here.
(2) Slave Processor samples CPU Status here.
FIGURE 3·18. CPU Read from Slave Processor
2·124
z
(J)
3.0 Functional Description (Continued)
Co)
N
3.4.9.1 Slave Processor Bus Cycles
A Slave Processor bus cycle always takes exactly two clock
cycles,labeled T1 and T4 (see Figures 3·18 and 3·1El). Dur·
ing a Read cycle, SPC is active from the beginning of T1 to
the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock peri·
od, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
The CPU does not pulse the address (ADS) and status
(STS) strobes during a slave protocol. The direction of a
transfer is determined by the sequence ("protocol") estab·
lished by the instruction under execution; but the CPU indio
cates the direction on the DDIN pin for hardware debugging
purposes.
1. The regular Slave protocol is fully compatible with
NS32032, NS32016 and NS3200B slave protocols.
In this protocol the NS32332 uses only the two least sig·
nificant bytes of the data bus for slave cycles. This allows
the NS32332 CPU to work with the current slaves (like
NS320B2, NS320B1 etc.)
A byte operand is transferred on the least significant byte
of the data bus (ADO-AD15).
A double word is transferred in a consecutive pair of bus
cycles least significant word first. A quadword is transferred in two pairs of slave cycles.
2. The fast slave protocol is unique to the NS32332 CPU. In
this protocol the NS32332 uses the full width of the data
bus (ADO-AD31) for slave cycles.
A byte operand is transferred on the least significant byte
of the data bus (ADO-AD?), a word operand is transferred on bits ADO-AD15 and a double word operand is
transferred on bits ADO-AD31. A quad word is transferred in two pairs of slave cycles with other bus cycles
possibly occurring between them.
3.4.9.2 Slave Operand Transfer Sequences
A Slave Processor operand is transferred in one or more
slave operand cycles. The NS32332 supports two slave
protocols which can be selected by the configuration register (CFG).
PREV.CYCLE
I
PHil
[
SPC
[
T40RTi
NEXT CYCLE
T1
T4
T1 OR Ti
I
ADO·AD3l [
STO·ST3 [
STS
[
ADS
[
CoiN
[
TLlEE18673-33
Note:
(1) Arrows indicate points at which the Slave Processor samples.
FIGURE 3-19. CPU Write to Slave Processor
2-125
Co)
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Q
.......
Z
(J)
Co)
N
Co)
Co)
N
....•
U1
.....
II)
N
CO)
CO)
N
CO)
tn
Z
......
o
.
....
N
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N
CO)
U)
Z
3.0 Functional Description (Continued)
3.5 MEMORY MANAGEMENT OPTION
The NS32332 CPU, in conjunction with the Memory Management Unit (MMU), provides full support for address
translation, memory protection, and memory allocation
techniques up to and including Virtual Memory.
When an MMU is used, the states T2 and TMMU are overlapped. During this time the CPU places ADO-AD31 into the
TRI-STATE mode, allowing the MMU to assert the translated address and issue the physical address strobe PAV. Figure 3-20 shows the Bus Cycle timing with address translation.
When a bus cycle is aborted by the MMU, the instruction
that caused it to occur is also aborted in such a manner that
it is guaranteed re-executable later.
Note: To guarantee correct instruction reexecution, Bit M in the CFG Register must be set.
11
T2/Tmmu
T3
T4
T1 OR TI
PHI 1 (
PHI2 [
Note 1: If an NS32382 MMU is used. the CPU can be selected to output
data during write cycles in state T2, by forcing lYi'/SDONE low duro
ing reset. This can be done because the NS32382 uses a separate
physical address bus.
ADO-A031 [
However, if a write cycle causes an MMU page table lookup, the
CPU data will be valid in state T3. After FLT is deasserted, regard·
less of the data timing selected.
DT ISDONE must always be forced high during reset if an NS32082
MMU is used since, in this case, no separate physical address bus
is provided.
Note 2: If an NS32082 MMU is used, in order for it to operate properly, it
must be set to the 32·Bit mode by forcing a A24/HBF low during
reset. In this mode the bus lines ADI6-AD24 are floated after the
MMU address has been latched, since they are used by the CPU to
transfer data.
3.5.1 The FLT (Float) Pin
BED-BE3 [
The FLT signal is used by the CPU for address translation
support. Activating FLT during Tmmu causes the CPU to
wait longer than Tmmu for address translation and validation. This feature is used occasionally by the MMU in order
to update its Translation Lookaside Buffer (TLB) from page
tables in memory, or to update certain status bits within
them.
Figure 3-21 shows the effect of FLT. Upon sampling FLT
low, late in Tmmu, the CPU enters idle T-States (Tf) during
which it:
1) Sets ADO-AD31, and DDIN to the TRI-STATE condition
("floating").
2) Suspends further internal processing of the current instruction. This ensures that the current instruction remains abortable with retry. (See RSTI ABT description.)
The above conditions remain in effect until FLT again goes
high. See Sec. 4.
-+---+--++--+--1
TLlEE/8673-87
FIGURE 3-20. Read (Write) Cycle with
Address Translation
3.5.2.1 Instruction Abort
Upon aborting an instruction, the CPU immediately interrupts the instruction and performs an abort acknowledge
using the ABT vector in the Interrupt Table (see Sec. 3.B).
The Return Address pushed on the Interrupt Stack is the
address of the aborted instruction, so that a Return from
Trap (RETT) instruction will automatically retry it.
The one exception to this sequence occurs if the aborted
bus cycle was an instruction prefetch. If so, it is not yet
certain that the aborted prefetched code is to be executed.
Instead of causing an interrupt, the CPU only aborts the bus
cycle, and stops prefetching. If the information in the Instruction Queue runs out, meaning that the instruction will
actually be executed, the Abort will occur, in effect aborting
the instruction that was being fetched.
3.5.2 Aborting Bus Cycles
The RST/ABT pin, apart from its Reset function (Sec. 3.3),
also serves as the means to "abort", or cancel, a bus cycle
and the instruction, if any, which initiated it. An Abort request is distinguished from a Reset in that the RST I ABT pin
is held active for only one clock cycle.
If RST/ABT is pulled low during Tmmu or n, this signals
that the cycle must be aborted. Since it is the MMU PAV
signal which triggers a physical cycle, the rest of the system
remains unaware that a cycle was started.
The MMU will abort a bus cycle for either of two reasons:
3.5.2.2 Hardware Considerations
In order to guarantee instruction retry, certain rules must be
followed in applying an Abort to the CPU. These rules are
followed by the Memory Management Unit.
1) The CPU is attempting to access a virtual address which
is not currently resident in physical memory. The referenced page must be brought into physical memory from
mass storage to make it accessible to the CPU.
2) The CPU is attempting to perform an access which is not
allowed by the protection level assigned to that page.
1) If FLT has not been applied to the CPU, the Abort pulse
must occur during Tmmu.
2-126
3.0 Functional Description
(Continued)
If RSTI ABT is pulsed at any time other than as indicated
above, it will abort either the instruction currently under execution or the next instruction and will act as a very high-priority interrupt. However, the program that was running at the
time is not guaranteed recoverable.
2) If FLT has been applied to the CPU, the Abort pulse must
be applied before the T -State in which FLT goes inactive.
The CPU will not actually respond to the Abort command
until FLT is removed.
3) The Write half of a Read-Modify-Write operand access
may not be aborted. The CPU guarantees that this will
never be necessary for Memory Management functions
by applying a special RMW status (Status Code 1011)
during the Read half of the access. When the CPU presents RMW status, that cycle must be aborted if it would
be illegal to write to any of the accessed addresses.
T1
PHI1
[
PHI2
[
ADD-AD31·
[
ADS
FLT
STD-STJ
I
T2ITmmu
I
3.6 BUS ACCESS CONTROL
The NS32332 CPU has the capability of relinquishing its
access to the bus upon request from a DMA device or another CPU. This capability is implemented on the HOLD
(Hold Request) and HLDA (Hold Acknowledge) pins. Byasserting HOLD low, an external device requests access to
the bus. On receipt of HLDA from the CPU, the device may
perform bus cycles, as the CPU at this point has set the
TI
TI
··· I
TI
I
T3
I
~
•
[
[
[
ODIN
[
BED-BEl
[
VALID
VALID
VALID
---- ---- ---fI-
VALID
VALID
·See MMU data sheet lor details on physical address timing and MMU initiated Bus cycles.
FIGURE 3-21. FLT Timing
2-127
TUEE/8673-34
.,... r------------------------------------------------------------------------------------------,
U)
N
C")
3.0 Functional Description
C")
ADO-AD31, ADS, STS, DDIN and SEO-SE3 pins to the
TRI-STATE condition. To return control of the bus to the
CPU, the device sets HOLD inactive, and the CPU acknowledges return of the bus by setting HLDA inactive.
N
C")
(/)
Z
......
o
.,...
N
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C")
N
C")
(/)
Z
(Continued)
quest is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-22 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-23 shows the sequence
if the CPU is using the bus at the time that the HOLD re-
I
Ti
I
Ti
In a Memory-Managed system, the HLDA signal is connected in a daisy-chain through the MMU, so that the MMU can
release the bus if it is using it.
I··· I
Ti
Ti
PHll[JLsu1
PHI2 [
HOL5[
HLDi[
AFFECTED SIGNALS
-i~
----
ADs [
DDiN[
-.~r--------
BEo-m [
-+----t----+-'
TL/EE/8673-35
FIGURE 3-22. HOLD Timing, Bus Initially Idle
2-128
3.0 Functional Description
(Continued)
3.7 INSTRUCTION STATUS
mapping, protection, and debugging purposes. U/S line is
updated every T4.
In addition to the four bits of Bus Cycle status (STO-ST3),
the NS32332 CPU also presents Instruction Status information on four separate pins. These pins differ from STO-ST3
in that they are synchronous to the CPU's internal instruction execution section rather than to its bus interface section.
ILO (Interlocked Operation) is activated during an SBITI (Set
Bit, Interlocked) or CBITI (Clear Bit, Interlocked) instruction.
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the semaphore primitive operations for multi-processor communication and resource sharing.
PFS (Program Flow Status) is pulsed low as each instruction
begins execution. It is intended for debugging purposes.
While ILO is active, the CPU inhibits instruction fetches. In
order to prevent MMU cycles during ILO, the CPU executes
a dummy Read cycle with status code 1011 (RMW) prior to
activating ILO. Thereafter, ILO is activated and the Read is
performed again but with status code 1010 (operand transfer). Refer to Figure 3-24.
U/S originates from the U bit of the Processor Status Register, and indicates whether the CPU is currently running in
User or Supervisor mode. It is sampled by the MMU for
T4
T3
T,
PHI2 [
HOLD [
HLDA[
AFFECTED SIGNALS
--- H--------
•
ADS [
DDIN [
BEO-BE3 [
STO-ST3[
-+___--4__V_A_LI_D_I-_ _ _+' ---+___--4__VA_L_ID_+_ _ _-+J
~~---
---- - - - -
1~--
---- -----
-+---__f----t-'
TL/EE/8873-36
FIGURE 3-23. HOLD Timing, Bus Initially Not Idle
2-129
.... r---------------------------------------------------------------------------------,
U)
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C')
C')
C'II
C')
zrn
C)
....
c:..
C')
C')
3.0 Functional Description
(Continued)
MC/EXS (Multiple Cycle/Exception Status) is activated during the access of the first part of an operand that crosses a
double-word address boundary. The activation of this signal
is independent of the selected bus width. Its timing is shown
in Figure 3-25. The MMU or other external circuitry can use
it as an early indication of a CPU access to an operand that
crosses a page boundary.
MC/EXS is also activated during the first non-sequential instruction fetch (status code 1001) following an abort, and
when the CPU enters the idle state (Status Code 0000) following a fatal bus error.
C'II
~
T1
Z
I
T2/Tmmu
I
TI
T4
T3
TLlEE/8673-37
FIGURE 3-24. ILO Timing
T4
Tl
T2
T3
T4
T1
T2
13
T4
11
PHil [
PHI2 [
TL/EE/8673-38
FIGURE 3-25. Non-aligned Write Cycle-MC/EXS Timing
2-130
3.0 Functional Description
(Continued)
3.8 NS32332 INTERRUPT STRUCTURE
Counter (PC), the Processor Status Register (PSR) and
the currently-selected Stack Pointer (SP). A copy of the
PSR is made, and the PSR is then set to reflect Supervisor Mode and selection of the Interrupt Stack.
2) Vector Acquisition.
INT, on which maskable interrupts may be requested,
NMI, on which non·maskable interrupts may be requested,and
RST/ABT, which may be used to abort a bus cycle and
any associated instruction. See Sec. 3.5.2.
In addition there is a set of internally-generated "traps"
which cause interrupt service to be performed as a result
either of exceptional conditions (e.g., attempted division by
zero) or of specific instructions whose purpose is to cause a
trap to occur (e.g., the Supervisor Call instruction).
A Vector is either obtained from the Data Bus or is supplied by default.
3) Service Call.
The Vector is used as an index into the Interrupt Dispatch
Table, whose base address is taken from the CPU Interrupt Base (INTBASE) Register. See Figure 3-26. A 32-bit
External Procedure Descriptor is read from the table entry, and an External Procedure Call is performed using it.
The MOD Register (16 bits) and Program Counter (32
bits) are pushed on the Interrupt Stack.
3.8.1 General Interrupt/Trap Sequence
Upon receipt of an interrupt or trap request, the CPU goes
through three major steps:
1) Adjustment of Registers.
Depending on the source of the interrupt or trap, the CPU
may restore and/or adjust the contents of the Program
,.
....
MEMORY
/
CASCADE TABLE
,.,..
:: :::
I
i
••
•
~~
CASCADE ADDR 14
CASCADE ADDR 15
FIXED INTERRUPTS
AND TRAPS
VECTORED
INTERRUPTS
0"
"'31
CASCADE ADDR 0
II'"-'''~
REGISTER
~
i
DISPATCH TABLE
1:
0
NVI
NON·VECTORED INTERRUPT
1
NMI
NON·MASKABLE INTERRUPT
2
ABT
ABORT
3
SLAVE
SLAVE PROCESSOR TRAP
4
ILL
ILLEGAL OPERATION TRAP
5
SVC
SUPERVISOR CALL TRAP
6
DVZ
DIVIDE BY ZERO TRAP
7
FLG
F LAG TRAP
8
BPT
BREAKPOINT TRAP
9
TRC
TRACE TRAP
UNDEFINED INSTRUCTION TRAP
10
UNO
11
RESERVED
12
BER
13-15 ::
16
,..,
RESERVED
Bus ERROR
~
VECTORED
INTERRUPTS
rL
TL/EE/8673-39
FIGURE 3-26. Interrupt Dispatch Table
2-131
....
II)
~
('I)
('I)
3.0 Functional Description
(Continued)
N
-.
('I)
CJ)
This process is illustrated in Figure 3-27, from the viewpoint of the programmer.
Z
....
o
N
('I)
('I)
N
('I)
CJ)
Z
I
I
I (PUSH)
RETURN ADDRESS
32BITS
I
STATUS
I
PSR
1
I
MODULE
32 BITS
I (PUSH)
MOD
INTERRUPT
STACK
TLlEE/B673-40
r-------- -----..,
I
i
CASCADE TABLE
i
I
INTBASE REGISTER
I
I
I
I
:
I
INTERRUPT BASE
VECTOR
DISPATCH
TABLE
t
<4
Y
DESCRIPTOR (32 BITS)
)
i""1----16---··-t-1..
DESCRIPTOR
----16-----<·~11
OFFSET
MODULE
0
MOD REGISTER ~
I
MODULE TABLE
NEW MODULE
l
MODULE TABLE ENTRY
j
MODULE TiBlE ENTRY
32
- t------
STATIC BASE POINTER
LINK BASE POINTER
+
PROGRAM BASE POINTER
(RESERVED)
SBREGISTER
PROGRAM COUNTER
I
I Y-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3-27_lnterrupt/Trap Service Routine Calling Sequence
2-132
j
TL/EE/B673-41
z
3.0 Functional Description
en
(0)
(Continued)
N
3.8.2 Interrupt/Trap Return
To return control to an interrupted program, one of two instructions is used. The RETT (Return from Trap) instruction
(Figure 3-28) restores the PSR, MOD, PC and S8 registers
to their previous contents and, since traps are often used
deliberately as a call mechanism for Supervisor Mode procedures, it also discards a specified number of bytes from
the original stack as surplus parameter space. RETT is used
to return from any trap or interrupt except the Maskable
Interrupt. For this, the RETI (Return from Interrupt) instruction is used, which also informs any external Interrupt Control Units that interrupt service has completed. Since interrupts are generally asynchronous external events, RETI
does not pop parameters. See Figure 3-29.
put is maskable, and is therefore enabled to generate interrupt requests only while the Processor Status Register I bit
is set. The I bit is automatically cleared during service of an
INT, NMI or Abort request, and is restored to its original
setting upon return from the interrupt service routine via the
RETT or RETI instruction.
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I = 0) or Vectored (bit I = 1).
3.8.3.1 Non-Vectored Mode
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
3.8.3 Maskable Interrupts (The INT Pin)
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests. The inPROGRAM COUNTER
I
I
RETURN ADDRESS
STATUS
PSR
I
MODULE
MOD
(POP)
-j
+-
}
_ _(P_O_P_)_ _ _
-1~~~---------t} :::
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
MODULE
T~BLE
ENTRY
STATIC BASE POINTER
-
--.,
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
PARAMETERS
/
SB REGISTER
STATIC BASE
B~ES
STACK SELECTED
IN NEWLY·
POPPEDPSR.
POP AND
DISCARD
FIGURE 3-28. Return from Trap (RETT n) Instruction Flow
2-133
TL/EE/8673-42
(0)
(0)
N
......
o
......
I
z
en
(0)
N
(0)
(0)
N
......
I
U1
3.0 Functional Description
(Continued)
"END OF INTERRUPT"
BUS CYCLE
INTERRUPT
CONTROL
UNIT
PROGRAM COUNTER
(POP)
RETURN ADDRESS
STATUS
I
(POP)
MODULE
PSR
-1----------4-
MOD
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
MODULETAJLEENTRY
STATIC BASE POINTER
-
h
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STATIC BASE
SBREGISTER
TL/EE/8673-43
FIGURE 3-29. Return from Interrupt (RETI) Instruction Flow
2·134
z
3.0 Functional Description
en
Co)
(Continued)
N
3.8.3.2 Vectored Mode: Non-Cascaded Case
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize many interrupt requests. Upon receipt
of an interrupt request on the INT pin, the CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Sec. 3.4.3)
reading a vector value from the low-order byte of the Data
Bus. This vector is then used as an index into the Dispatch
Table in order to find the External Procedure Descriptor for
the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI)
instruction, which performs an End of Interrupt bus cycle,
informing the ICU that it may re-prioritize any interrupt requests still pending. The ICU provides the vector number
again, which the CPU uses to determine whether it needs
also to inform a Cascaded ICU (see below).
Table index. The CPU, seeing a negative value, uses it to
find the corresponding Cascade Address from the Cascade
Table. Applying this address, it performs an "End of Interrupt, Cascaded" bus cycle (Sec. 3.4.3), informing the Cascaded ICU of the completion of the service routine. The byte
read from the Cascaded ICU is discarded.
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Sec. 3.4.3)
when processing of this interrupt actually begins. The Interrupt Acknowledge cycle differs from that provided for Maskable Interrupts in that the address presented is
FFFFFF0016. The vector value used for the Non-Maskable
Interrupt is taken as 1, regardless of the value read from the
bus.
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
For the full sequence of events in processing the NonMaskable Interrupt, see Sec. 3.B.7.1.
In order to allow more levels of interrupt, provision is made
in the CPU to transparently support cascading. Note that
the Interrupt output from a Cascaded ICU goes to an Interrupt Request input of the Master ICU, which is the only ICU
which drives the CPU INT pin. Refer to the ICU data sheet
for details.
In a system which uses cascading, two tasks must be performed upon initialization:
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number on which it receives
the cascaded requests.
N
However, if an interrupt is set pending during the CPU instruction that
masks off that interrupt. the CPU may still perform an interrupt acknowledge cycle following that instruction since it might have sampled
the INT line before the leu deasserted it. This could cause the leu to
provide an invalid vector. To avoid this problem the above operation
should be performed with the CPU interrupt disabled.
U1
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Sec. 3.9.1).
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
Trap (SVC): The Supervisor Call (SVG) instruction was executed.
Trap (DVZ): An attempt was made to divide an integer by
zero. (The Slave trap is used for Floating Point division by
zero.)
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
Trap (BPT): The Breakpoint (BPT) instruction was executed.
Trap (TRC): The instruction just completed is being traced.
See below.
Trap (UNO): An undefined opcode was encountered by the
CPU.
2-135
......
z
en
Co)
Co)
Co)
3.8.5Traps
A trap is an internally-generated interrupt request caused as
a direct and immediate result of the execution of an instruction. The Return Address pushed by any trap except Trap
(TRG) is the address of the first byte of the instruction during
which the trap occurred. Traps do not disable interrupts, as
they are not associated with external events. Traps recognized by the NS32332 CPU are:
2) A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (INTBASE) Register. Its entries are 32-bit addresses, pointing
to the Vector Registers of each of up to 16 Cascaded
ICUs.
Figure 3-26 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32-bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle
(Sec. 3.4.3), reading the final vector value. This vector is
interpreted by the CPU as an unsigned byte, and can therefore be in the range of 0 through 255.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle (Sec. 3.4.3), whereupon the Master ICU again provides the negative Cascade
~
.....
o
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit in the interrupt mask register of the interrupt controller.
3.8.4 Non-Maskable Interrupt (The NMI Pin)
3.8.3.3 Vectored Mode: Cascaded Case
Co)
Co)
N
.....
I
Il)
.....
•
N
CO)
CO)
N
~
Z
.....
o
.....
•
N
CO)
CO)
~
tn
Z
3.0 Functional Description
(Continued)
A special case is the Trace Trap (TRC), which is enabled by
setting the T bit in the Processor Status Register (PSR). At
the beginning of each instruction, the T bit is copied into the
PSR P (Trace "Pending") bit. If the P bit is set at the end of
an instruction, then the Trace Trap is activated. If any other
trap or interrupt request is made during a traced instruction,
its entire service procedure is allowed to complete before
the Trace Trap occurs. Each interrupt and trap sequence
handles the P bit for proper tracing, guaranteeing one and
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
3. If the interrupt is Non-Maskable:
a. Read a byte from address FFFFFF0016, applying
Status Code 0100 (Interrupt Acknowledge, Master,
Sec. 3.4.3). Discard the byte read .
b. Set "Vector" to 1.
c. Go to Step 8.
4. If the interrupt is Non-Vectored:
a. Read a byte from address FFFFFE0016, applying
Status Code 0100 (Interrupt Acknowledge, Master:
Sec. 3.4.3). Discard the byte read.
b. Set "Vector" to O.
c. Go to Step 8.
5. Here the interrupt is Vectored. Read "Byte" from address
FFFFFE0016, applying Status Code 0100 (Interrupt Acknowledge, Master: Sec. 3.4.3).
6. If "Byte" :2: 0, then set "Vector" to "Byte" and go to Step
8.
7.lf "Byte" is in the range -16 through -1, then the interrupt source is Cascaded. (More negative values are reserved for future use.) Perform the following:
Note: A slight difference exists between the NS32332 and previous Series
32000 CPU. when traCing is enabled.
The NS32332 always clears the P bit in the PSR before pushing the
PSR on the stack. Previous CPUs do not clear it when a trap (ILL)
occurs.
The result is that an instruction that causes a trap (ILL) exception is
traced by previous Series 32000 CPU •• but is never traced by the
NS32332.
3.8.6 Prioritization
The NS32332 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
2) Abort
a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE +4· Byte.
(Highest priority)
b. Read "Vector," applying the Cascade Address just
read and Status Code 0101 (Interrupt Acknowledge,
Cascaded: Sec. 3.4.3).
8. Perform Service (Vector, Return Address), Figure 3-30.
3) Bus Error
4) Non-Maskable Interrupt
5) Maskable Interrupts
6) Trace Trap
(Lowest priority)
Service (Vector, Return Address):
1) Read the 32-blt External Procedure Descriptor from the Interrupt
Dispatch Table: address Is Vector· 4 + INTBASE Register contents.
3.8.7Interrupt/Trap Sequences: Detailed Flow
For purposes of the following detailed discussion of interrupt and trap service sequences, a single sequence called
"Service" is defined in Figure 3-30. Upon detecting any interrupt request or trap condition, the CPU first performs a
sequence dependent upon the type of interrupt or trap. This
sequence will include pushing the Processor Status Regis·
ter and establishing a Vector and a Return Address. The
CPU then performs the Service sequence.
2) Move the Module field of the Descriptor Into the MOD Register.
3) Read the Program Base pointer from memory address MOD + 8,
and add to It the Ollset field from the Descriptor, placing the result
In the Program Counter.
4) Read the new StatiC Base pOinter from the memory address contained In MOD, placing It into the SB Register.
S) Flush queue: Non-sequentially fetch first Instruction of Interrupt
routine.
6) Push the PSR copy onto the Interrupt Stack as a 16-blt value.
For the sequence followed in processing either Maskable or
Non-Maskable interrupts (on the INT or NMI pins, respectively), see Sec. 3.8.7.1 For Abort Interrupts, see Sec.
3.8.7.4. For the Trace Trap, see Sec. 3.8.7.3, and for all
other traps see Sec. 3.8.7.2.
7) Push MOD Register Into the Interrupt Stack as a 16·blt value.
8) Push the Return Address onto the Interrupt Stack as a 32-blt quant~
!y.
FIGURE 3·30. Service Sequence
Invoked during all interrupt/trap sequences.
3.8.7.1 Maskable/Non-Maskable Interrupt Sequence
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, at the next interruptible point during its execution.
1. If a String instruction was interrupted and not yet completed:
3.8.7.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector" to the value corresponding to the trap type.
SLAVE:
ILL:
Vector = 3.
Vector = 4.
a. Clear the Processor Status Register P bit.
SVC:
Vector = 5.
b. Set "Return Address" to the address of the first byte of
the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
DVZ:
FLG:
BPT:
Vector = 6.
Vector = 7.
Vector = 8.
UND:
Vector = 10.
3) Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, P and T.
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I.
2-136
3.0 Functional Description
(Continued)
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3·31. While applying
Status Code 1111 (Broadcast ID, Sec. 3.4.3), the CPU
transfers the ID Byte on bits ADO-AD7 and a non-used byte
xxxxxxx1 (x = don't care) on bits AD24-AD31. All Slave
Processors input this byte and decode it. The Slave Processor selected by the ID Byte is activated, and from this point
the CPU is communicating only with it. If any other slave
protocol was in progress (e.g., an aborted Slave instruction),
this transfer cancels it.
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Sec. 3.4.3).
Upon receiving it, the Slave Processor decodes it, and at
this point both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The operation Word is swapped on the Data Bus, that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD?
Using the Address Mode fields within the Operation Word,
the CPU starts fetching operand and issuing them to the
Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
for memory accesses, these extensions are not sent to the
Slave processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Sec. 3.4.3).
4) Set "Return Address" to the address of the first byte of
the trapped instruction.
5) Perform Service (Vector, Return Address), Figure 3-30.
3.8.7.3 Trace Trap Sequence
1)ln the Processor Status Register (PSR), clear the P bit.
2) Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
3) Set "Vector" to 9.
4) Set "Return Address" to the address of the next instruction.
5) Perform Service (Vector, Return Address), Figure 3-30.
3.8.7.4 Abort Sequence
1) Restore the currently selected Stack Pointer to its original
contents at the beginning of the aborted instruction.
2) Clear the PSR P bit.
3) Copy the PSR into a temporary register, then clear PSR
bits S, U, T and I.
4) Set "Vector" to 2.
5) Set "Return Address" to the address of the first byte of
the aborted instruction.
S) Perform Service (Vector, Return Address), Figure 3-30.
3.8.7.5 Bus Error Sequence
After the CPU has issued the last operand, the Slave Processor starts the actual execution of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low. To
allow for this SPC is normally held high only by an internal
pull-up device of approximately 5 kfi.
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave, Sec.
3.4.3).
1) The same as Abort sequence above, but set vector to 12.
3.9 SLAVE PROCESSOR INSTRUCTIONS
The NS32332 CPU recognizes three groups of instructions
being executable by external Slave Processor:
Floating Point Instruction Set
Memory Management Instruction Set
Custom Instruction Set
Each Slave Instruction Set is validated by a bit in the Configuration Register (Sec. 2.1.3). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
In addition, each slave instruction will be performed either
through the regular (32032 compatible) slave protocol or
through a fast slave protocol according to the relevent bit in
the configuration register (Sec. 2.1.3).
A combination of one slave communicating with an old protocol and another with a new protocol is allowed, e.g. 1S-bit
FPU (32081) and 32·bit MMU (32382) or vice versa.
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status, Sec. 3.4.3). This
word has the format shown in Figure 3-34. If the Q bit
("Quit", Bit 0) is set, this indicates that an error was detected by the Slave Processor. The CPU will not continue the
protocol, but will immediately trap through the SLAVE vector
in the Interrupt Table. Certain Slave Processor instructions
cause CPU PSR bits to be loaded from the Status Word.
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand, Sec.
3.4.3).
An exception to the protocol above is the LMR (Load Memory Management Register) instruction, and a corresponding
Custom Slave instruction (LCR: Load Custom Register). In
executing these instructions, the protocol ends after the
CPU has issued the last operand. The CPU does not wait for
an acknowledgement from the Slave Processor, and it does
not read status.
3.9.116-Blt Slave Processor Protocol
(32032 Compatible)
Slave Processor instructions have a three·byte Basic Instruction field, consisting of an ID Byte followed by an Oper·
ation Word. The ID Byte has three functions:
1)lt identifies the instruction as being a Slave Processor
instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word
of the instruction.
2-137
•
3.0 Functional Description
(Continued)
Slatus Combinations:
Status Combinations:
Send ID (ID): Code 1111
Send ID (ID): Code 1111
Xfer Operand (OP): Code 1101
Xfer Operand (OP~ Code 1101
Read Slatus (ST): Code 1110
Reed Statu8 (Sn: Code 1110
Step
Slatus
I
10
CPU Send 10 Byte.
2
OP
CPU Sends Operaton Word.
2
3
OP
CPU Sends Required Operands
3
4
Slave Starts execution. CPU Pre·letches.
4
S
Slave Pulses SPC Low.
S
ST
CPU Reads Status wcrd (only II l!OONE or SPa
6
OP
CPU Reads Results gl any).
6
Action
ST
CPU Reads Status Word. (Trap? Alter Flags?)
OP
CPU Reads Results (II Any).
Step Status
Actton
ID
CPU .ends ID and Operation Word.
OP
CPU sends required operands (~ any).
Slave starts execution (CPU preletches).·
Slave pulses Si5ONE: or SPa low.
pulse Is two clock cycles wide).
FIGURE 3·31. 16·Blt Slave Processor Protocol
FIGURE 3·32. 32·Blt Fast Slave Protocol
3.9.2 32·Blt Fast Slave Protocol
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-32. While applying
Status code 1111 (Broadcast ID Sec. 3.4.2), the CPU transfers the ID Byte on bits AD24-AD31, the operation word on
bits AD8-AD23 in a swapped order of bytes and a non-used
byte XXXXXXX1 (X = don't care) on bits ADO-AD? (Figure
3-33).
Certain Slave Processor instructions affect CPU PSR. For
these instructions only the CPU will perform a Read Slave
status cycle as described in 3.9.1.1 before reading the result. The relevent PSR bits will be loaded from the status
word.
byte 3
Using the addressing mode fields within the Operation word,
the CPU fetches operands and sends them to the Slave
Processor. Since the CPU is solely responsible for memory
accesses, addressing mode extensions are not sent to the
Slave Processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand Sec. 3.4.2). After the CPU has
issued the last operand, the Slave Processor starts the actual execution of the instruction. Upon completion, it will signal the CPU by pulsing SDONE or SPC low for one clock
cycle.
10
byte 2
byte 1
byte 0
OPCODE low
OPCODE high
Don't Care
FIGURE 3·33. 10 and Opcode Format
for Fast Slave Protocol
3.9.3 FloatIng Point Instructions
Table 3-4 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodlngs of each Instruction, see
Appendix A.
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Instruction Set Reference Manual).
Unlike the old protocol, the SLAVE may request the CPU to
read the status by activating the SDONE or SPC line for two
clock cycles instead of one. The CPU will then read the
slave status word and update the PSR Register, unless a
trap is signalled. If this happens, the CPU will immediately
abort the protocol and start a trap sequence using either the
SLAVE or the UNO vector in the interrupt table as specified
in the Status Word.
The Operand Issued columns show the sizes of the operands Issued to the Floating Point Unit by the CPU. "0" indicates a 32-bit Double Word. "I" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, 0 = Double Word). "f'~ Indicates that the instruction
specifies a Floating Point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places It. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-34).
Note: The PSR update Is presenUy restricted to three Instructions: CMPI,
ROVAL. WRVAL and their custom slave equivalents.
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills its
queue before the Slave Processor finishes, the CPU will
wait applying status code 0011 (waiting for Slave, Sec.
3.4.2).
Upon receiving the pulse on either SDONE or SPC, the CPU
uses SPC to read the result from the Slave Processor and
transfer it to the destination. The Read cycles from the
Slave Processor are performed by the CPU while applying
Status Code 1101 (Transfer Slave Operand, Sec. 3.4.2).
2-138
3.0 Functional Description
Mnemonic
Operand 1
Class
ztJ)
W
N
W
W
N
(Continued)
TABLE 3·4
Floating Point Instruction Protocols,
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
Returned Value
Type and Dest.
PSR Bits
Affected
ftoOp.2
ftoOp.2
ftoOp.2
ftoOp.2
none
none
none
none
ftoOp.2
ftoOp.2
ftoOp.2
none
none
none
ADDf
SUSf
MULl
DIVf
read.f
read.f
read.f
read.f
rmw.!
rmw.!
rmw.!
rmw.!
MOVf
ASSf
NEGf
read.f
read.!
read.f
write.!
write.f
write.f
CMPf
read.!
read.!
f
N/A
N,Z,L
FLOORfi
TRUNCfi
ROUNDfi
read.!
read.f
read.!
write.i
write.i
write.i
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
none
none
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
N/A
N/A
LtoOp.2
FtoOp.2
none
none
N/A
ftoOp.2
none
f
N/A
ftoFO
ftoFO
ftoOp.2
ftoOp.2
none
none
none
none
N/A
N/A
N/A
DtoOp.2
none
none
N/A
N/A
N/A
F
L
MOVif
read.i
write.f
POLYf
DOTf
SCALSf
LOGSf
read.f
read.!
read.!
read.!
read.f
read.f
rmw.!
write.!
LFSR
SFSR
read.D
N/A
N/A
write.D
D
N/A
Note 1:
D = Double Word
I
=
Integer size (B,W,D) specified in mnemonic.
= Floating Point type (F,L) specilied in mnemonic.
NI A = Not Applicable to this instruction.
I
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
t5
8 7
3.9.4 Memory Management Instructions
Table 3-5 gives the protocols for Memory Management instructions. Encodings for these instructions may be found in
Appendix A.
In executing the RDVAL and WRVAL instructions, the CPU
calculates and issues the 32-bit Effective Address of the
single operand. The CPU then performs a single-byte Read
cycle from that address, allowing the MMU to safely abort
the instruction if the necessary information is not currently in
physical memory. Upon seeing the memory cycle complete,
the MMU continues the protocol, and returns the validation
result in the F bit of the Slave Status Word.
o
1 TS 0 0 0 0 0 0 0 1N Z F 0 0 L MIl' 01
NewPsRBltYaIUe(.)~ ..A
TL/EE/8673-44
FIGURE 3·34. Slave Processor Status Word Format
Note 1: 0 is the Trap Bit. It is set to 1 by the Slave whenever a trap is
requested.
The size of a Memory Management operand is always a 32bit Double Word. For further details of the Memory Management Instruction set, see the Instruction Set Reference
Manual and the MMU Data Sheet.
Note 2: TS is the Trap Select Bit. When a trap is requested (0 = I), TS telis
the CPU whether a SLAVE or an UND trap is to be generated. TS is
o lor a slave trap and t lor an UND trap.
Note 3: MIl' should be set for a RDYAL, WRVAL, or Custom Slave Equivalent instruction. It should be cleared for CM?I and CCMPOc and
CCMPc. When MIl' is cleared, the F bit should also be cleared.
2-139
•
.....
Q
....
Z
tJ)
w
w
w
N
N
•
.....
en
.... r------------------------------------------------------------------------------------------,
U)
N
Cf)
3.0 Functional Description
(Continued)
Cf)
C'i
~
Z
.....
CI
....
Mnemonic
N
Cf)
RDVAL'
WRVAL"
Cf)
C'i
Cf)
tn
LMR'
SMR'
Z
Operand 1
Class
TABLE 3-5
Memory Management Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
Returned Value
Type and Dest.
PSR Bits
Affected
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
DtoOp.1
none
none
Nole:
In the ROYAL and WRVAL instructions, the CPU issues the address as a Double Word, and performs a single-byte Read cycle from that memory address. For
details, see the Instruction Set Reference Manual and the Memory Management Unit Data Sheet.
D
= Double Word
•=
Privileged Instruction: will trap if CPU is in User Mode.
NI A = Not Applicable to this instruction.
3.9.5 Custom Slave Instructions
Provided in the NS32332 is the capability of communicating
with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
operand which can be a 32-bit ("D") or 64-bit ("0") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type "c" will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
Table 3-6 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
For the instruction encodings, see Appendix A.
2-140
z
3.0 Functional Description
en
w
(Continued)
I\)
w
w
I\)
....
TABLE 3-6
Mnemonic
Operand 1
Class
rmw.c
rmw.c
rmw.c
rmw.c
c
c
c
c
c
c
c
c
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
none
CMOVOc
CMOV1c
CMOV2c
read.c
read.c
read.c
write.c
write.c
write.c
c
c
c
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
CMOV3c
read.c
write.c
c
N/A
N/A
N/A
N/A
cto Op.2
none
CCMPOc
read.c
read.c
c
c
N/A
N,Z,L
CCMP1c
read.c
read.c
c
c
N/A
N,Z,L
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
read.c
read.c
read.c
read.i
read.D
read.Q
write.i
write.i
write.i
write.c
write.Q
write.D
c
c
c
i
D
Q
N/A
N/A
none
none
none
none
none
none
LCSR
SCSR
read.D
N/A
N/A
write.D
D
N/A
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
cto Op. 2
QtoOp.2
DtoOp.2
N/A
N/A
N/A
DtoOP.2
none
none
addr
addr
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
D
N/A
N/A
N/A
D to Op.1
N/A
N/A
Note:
= Double Word
=
PSR Bits
Affected
read.c
read.c
read.c
read.c
LCR'
SCR'
o
Returned Value
Type and Dest.
CCALOc
CCAL1c
CCAL2c
CCAL3c
CATSTO'
CATST1'
i
I
Custom Slave Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
Integer size (B,W,D) specified in mnemonic.
c = Custom size (0:32 bits or Q:64 bits) specified in mnemonic.
• = Privileged instruction: will trap if CPU is in User Mode.
NI A = Not Applicable to this instruction.
2-141
N/A
none
none
c
......
Z
en
w
I\)
w
w
I\)
....U1
I
.... r---------------------------------------------------------------------------------,
U)
c.:a
C')
C')
~
tn
....Zo
....
c.:a
C')
C')
4.0 Device Specifications
4.1 NS32332 PIN DESCRIPTIONS
Unless otherwise indicated, reserved pins should be left
open.
N
4.1.1 Supplies
U)
Logic Power (VCCL1, 2): +5V positive supply.
C')
Z
4.1.3 Output Signals
Address Strobe (ADS): Active low. Controls address latches, indicates the start of a bus cycle.
Data Direction in (ODIN): Active low. Indicates the directions of data transfers.
Byte Enables (BEO-BE3): Active low. Enable the access of
bytes 0-3 in a 32 bit system.
Status (STO-ST3): Bus cycle status code, STO least significant. Encodings are:
The following is a brief description of all NS32332 pins. The
descriptions reference portions of the Functional Descrip·
tion, Section 3.
Buffers Power (VCCB1, 2, 3, 4, 5): +5V positive supply.
Logic Ground (GNDL 1, GNDL2): Ground reference for on·
chip logic.
Buffer Grounds (GNDB1, GNDB2, GNDB3, GNDB4,
GNDB5, GNDB6): Ground references for on·chip drivers.
0000 - Idle: CPU Inactive on Bus.
0001 - Idle: WAIT Instruction.
0010 - (Reserved).
0011 - Idle: Waiting for Slave.
0100 -Interrupt Acknowledge, Master.
0101 - Interrupt Acknowledge, Cascaded.
0110- End of Interrupt, Master.
0111 - End of Interrupt, Cascaded.
1000 - Sequential Instruction Fetch.
1001 - Non-Sequential Instruction Fetch.
1010 - Data Transfer.
1011 - Read Read-Modify-Write Operand.
1100 - Read for Effective Address.
1101 - Transfer Slave Operand.
1110 - Read Slave Status Word.
1111 - Broadcast Slave 10.
Back Bias Generator (BBG): Output of on-chip substrate
voltage generator.
4.1.2 Input Signals
Clocks (PHI1, PHI2): Two-phase clocking signals.
Ready (ROY): Active high. While ROY is not active, the CPU
adds wait cycles to the current bus cycle. Not applicable for
slave cycles.
Hold Request (HOLD): Active low. Causes the CPU to release the bus for DMA or multiprocessing purposes.
Nole: If the FiO[l) signal is generated asynchronously. it's set up and hold
times may be violated. In this case it is recommended to synchronize
it with CTIL to minimize the possibility of metastable states.
Status Strobe (STS): Active low. Indicates that a new
status (STO-ST3) is valid. Not applicable for slave cycles.
The CPU provides only one synchronization stage to minimize the
AIDA latency. This is to avoid speed degradations In cases of heavy
fID[lj activity (i.e. DMA controller cycles interleaved with CPU
cycles.)
Multiple Cycle/Exception Status (MC/EXS): Active low.
This signal is activated during the access of the first part of
an operand that crosses a double word address boundary.
Interrupt (INT): Active low. Maskable Interrupt request.
Non-Maskable Interrupt (NMI): Active low. Non-Maskable
Interrupt request.
It is also activated in conjunction with status codes 1001
and 0000 during Abort Acknowledge and when a fatal bus
error occurs.
Resetl Abort (RST/ ABT): Active low. If held active for one
clock cycle and released, this pin causes an ABORT. If held
longer, it is interpreted as RESET.
Bus Error (BER): Active low. When active, indicates that an
error occurred during a bus cycle. It is treated by the CPU as
the highest priority exception after RESET. Not applicable
for slave cycles.
Bus Retry (BRT): Active low. When active, the CPU will reexecute the last bus cycle. Not applicable for slave cycles.
Bus Width (BW1, BWO): Define the bus width (8,16,32) in
every bus cycle. 01-8 bits, 10-16 bits, 11 -32 bits. 00 is a
reserved combination. Not applicable for slave cycles.
Burst In (BIN): Active low. When active, the CPU may perform burst cycles.
Note: MC/Ei
'tJ
'tJ
CD
~
CJ
Q.
;C"
NSJ2C201
reu
~
-
ilO
~
CD
~
D)
n
S"
CQ
en
c
CQ
CQ
CD
UI
0"
~
UI
~
en
en
o
WR
,CK
ODIN
8W,
8W'
BOUT
8lN
TLlEE/8673-86
FIGURE 8-1. System Connection Diagram (32332, 32081 & 32082)
z
Appendix B: Interfacing Suggestions
en
c,.)
(Continued)
N
c,.)
c,.)
N
.,..
....
I
WAITI
RD
WR
o
.......
WAIT2
TSO
en
c,.)
CWAIT
....
8US
CONTROL
8RSTI
LOGIC
-8RSTO
z
D8E
N
ADS
-+m
RDY
RST
+E'A
2A
CLK DDIN
3A
4A
18
28
38
48
+81N
>- ....... BiN
>-- 8WO
>-- 8WI
+--
>---+
,>---+
PFS
iNT
mil
1
ILO
FLT
DDIN
RST/A8T
RSTI
DDiN
RSI/A8T
M
HLDAI
-
PAY
-
ADS
8ER
8RT
Dr/SDONE
SPC
HOLD
STO-3
PHil
PHI2
ADO-31
NS32332
CPU
ADS
8ER
8RT
SDONE
SPC
HOLD
--'" STO-3
";
PHil
PHI2
T
I
5V
NS32382
MMU
CINH
CINH
.
~
PAO-31
MADS
~
ADO-31
PAO-31
5V
•
RST
~
• I"
+5
I
I
DO-31
SDN332
NOE
PSO
SPC
PSI
STO-3
NS32381
FPU
PHil
I--'
....
NS32C201
TCU
RST
CLK
DDIN
J
PHI2
RSTO
-
-
DO-31
10 kll
• j,
,....
4Y~ 8E3
HLDAO
l!LL
HLDA
....
~
ill
3Y~ 8E2
MILO
m
:::
iL
2Y~
L- ~
RDY
-
Lw-.,....5V
+5
N
IY~ 8EO
'-J~
RD~~
8EO 8EI8E2 8E3
80UT
c,.)
c,.)
~
r
cm
XIN
XOUT
16
~
RSTI
TL/EE/8673-93
FIGURE 8-2. System Connection Diagram (32332,32381 & 32382)
2-167
....
I
U1
.... r----------------------------------------------------------------------------,
U)
N
CO)
Q
~National
~
CO)
~ Semiconductor
Z
NS32C032-10/NS32C032-15
High-Performance Microprocessors
tn
C;
....
N
CO)
Q
U
C\I
~
Z
General Description
Features
The NS32C032 is a 32-bit, virtual memory microprocessor
with a 16-MByte linear address space and a 32-bit external
data bus. It has a 32-bit ALU, eight 32-bit general purpose
registers, an eight-byte prefetch queue, and a slave processor interface. The NS32C032 is fabricated with National
Semiconductor's advanced CMOS process, and is fully object code compatible with other Series 32000® processors.
The Series 32000 instruction set is optimized for modular,
high-level languages (HLL). The set is very symmetric, it has
a two address format, and it incorporates HLL oriented addressing modes. The capabilities of the NS32C032 can be
expanded with the use of the NS32081 floating point unit
(FPU), and the NS32082 demand-paged virtual memory
management unit (MMU). Both devices interface to the
NS32C032 as slave processors. The NS32C032 is a general purpose microprocessor that is ideal for a wide range of
computational intensive applications.
•
•
•
•
•
32-bit architecture and implementation
Virtual memory support
16-MByte linear address space
32-bit data bus
Powerful instruction set
- General 2-address capability
- Very high degree of symmetry
- Addressing modes optimized for high-level
languages
• Series 32000 slave processor support
• High-speed CMOS technology
• 68-pin leadless chip carrier
Block Diagram
ADD/DATA
CONTROLS. STAlUS
MICROCODE ROM
AND
CONTROL LOGIC
IIIIJ
CFG REGISTER
0
0
0
0
WORKING
REGISTERS
FP
SPI
SPO
PC
RD
Rl
R2
R3
R4
RS
I
I
I
R6
I
R7
I
I
MOD
PSR
:
L_________________
J
TL/EE/9160-1
FIGURE 1
2-168
ztJ)
Table of Contents
1.0 PRODUCT INTRODUCTION
N
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.8 NS32C032 Interrupt Structure
2.0 ARCHITECTURAL DESCRIPTION
3.8.1 General Interrupt/Trap Sequence
3.8.2 Interrupt/Trap Return
3.8.3 Maskable Interrupts (The INT Pin)
3.8.3.1 Non-Vectored Mode
3.8.3.2 Vectored Mode: Non-Cascaded Case
3.8.3.3 Vectored Mode: Cascaded Case
3.8.4 Non-Maskable Interrupt (The NMI Pin)
3.8.S Traps
3.8.6 Prioritization
3.8.7 Interrupt/Trap Sequences Detailed Flow
3.8.7.1 Maskable/Non-Maskable Interrupt
Sequence
3.8.7.2 Trap Sequence: Traps Other Than Trace
3.8.7.3 Trace Trap Sequence
3.8.7.4 Abort Sequence
2.1 Programming Model
2.1.1 General Purpose Registers
2.1.2 Dedicated Registers
2.1.3 The Configuration Register (CFG)
2.1.4 Memory Organization
2.1.S Dedicated Tables
2.2 Instruction Set
2.2.1 General Instruction Format
2.2.2 Addressing Modes
2.2.3 Instruction Set Summary
3.0 FUNCTIONAL DESCRIPTION
3.1
3.2
3.3
3.4
Co:)
Power and Grounding
Clocking
Resetting
Bus Cycles
oC
Co:)
N
I
......
C
.....
Z
tJ)
Co:)
N
oC
Co:)
N
I
......
U1
3.9 Slave Processor Instructions
3.9.1
3.9.2
3.9.3
3.9.4
3.4.1 Cycle Extension
3.4.2 Bus Status
3.4.3 Data Access Sequences
3.4.3.1 Bit Accesses
3.4.3.2 Bit Field Accesses
3.4.3.3 Extending Multiply Accesses
3.4.4 Instruction Fetches
3.4.S Interrupt Control Cycles
3.4.6 Slave Processor Communication
3.4.6.1 Slave Processor Bus Cycles
3.4.6.2 Slave Operand Transfer Sequences
Slave Processor Protocol
Floating Point Instructions
Memory Management Instructions
Custom Slave Instructions
4.0 DEVICE SPECIFICATIONS
4.1 Pin Descriptions
4.1.1
4.1.2
4.1.3
4.1.4
Supplies
Input Signals
Output Signals
Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
3.S Memory Management Option
3.S.1 Address Translation Strap
3.S.2 Translated Bus Timing
3.S.3 The FLT (Float) Pin
3.S.4 Aborting Bus Cycles
3.S.4.1 The Abort Interrupt
3.S.4.2 Hardware Considerations
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
4.4.2.2 Input Signals Requirements
4.4.2.3 Clocking Requirements
4.4.3 Timing Diagrams
Appendix A: Instruction Formats
Appendix B: Interfacing Suggestions
3.6 Bus Access Control
3.7 Instruction Status
List of Illustrations
.
. ...................................... 2-1
1-1
CPU Block Diagram.....................................................
The General and Dedicated Registers ............................................................................ 2-2
~~~i~s~j
Recommended Supply Connections ..............................................................................3-2
Clock Timing Relationships ...................................................................................... 3 3
~:~:~~~~~:~~i~~n~Ui~~~.~~t~. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :~~~:
Recommended Reset Connections, Non-Memory-Managed System ................................................ .
Recommended Reset Connections, Memory- Managed System ................................... . ................. 3-Sb
2-169
EI
U)
..-
N
('f)
~
~
Z
C;
..N
a
~
en
('f)
z
r---------------------------------------------------------------------------------,
List of Illustrations (Continued)
Bus Connections ......•....••••.•••••...•.•.....••.••....•................••...............•.•...........•••... 3·6
Read Cycle Timing .....•..•.....•••..........••.•....•.•.............•••••.....•.•..•...•.•..•••..•...••••..••• 3·7
Write Cycle Timing ....................•......••.•..•••••...••.••••.•.•••..•••••••••.•••••..•••••.•.•••.•.•...•. 3·8
ROY Pin Timing .....••.....•....••......•........................•................•........••.....•.•......•... 3·9
Extended Cycle Example .......................•........•......••.....•.••.....•••......•••....•.••.....••.•..3·1 0
Memory Interiace ....... , .•.............•..........•.•...•.•..•.••......•••.•.....................•........•..3·11
Slave Processor Connections ........•..•....•.•....••••.. , •••••.•.••••.•..•••.•••..•••••.••••••.••.•.•••••.••• 3·12
CPU Read from Slave Processor ...••.•...•••........•.....•.....•..........•........•••.....••....•..••......•. 3·13
CPU Write to Slave Processor ...................••......•......••••..•.•.•.....•••••.....•••.••.••••....•••.•.. 3·14
Read Cycle with Address Translation (CPU Action) ...••.•....•••..•...••••....••.......••.•....••••.....••••..•••. 3·15
Write Cycle with Address Translation (CPU Action) ..........•.....••••......••........••......•................•.. 3·16
Memory·Managed Read Cycle .......•.....•...........•..........•.........••...•....•••....•.......•.•........ 3·17
Memory·Managed Write Cycle .........•........•.•......••....••••....•••••.....••••.....•••...••••......•..•.. 3·18
FLT Timing ...........•.....••.....•......•......•••.....••.......•••.....•••.•....••••....•••.•••.•••••.•..••3·19
HOLD Timing, Bus Initially Idle ...................................•.......•••........•.•............••.•......•..3·20
HOLD Timing, Bus Initially Not Idle .....•.•....•.•....••••.......•....•••....••..••••...•.•.•....•••.....•••••..• 3·21
Interrupt Dispatch and Cascade Tables ..............•......•....•...........••.......••..•...••......•••......•. 3·22
Interrupt/Trap Service Routine Calling Sequence •.•..•.•••.. , ..•.••...••••••. , .•.••••. , .•••••...••••••.••••.•••.• 3·23
Return from Trap (RETT n) Instruction Flow •..........•......................•.........•..............••.......•. 3·24
Return from Interrupt (RET) Instruction Flow ......•.•..•...••.....••••.....•••......•.••.....••......••........•.. 3·25
Interrupt Control Connections (16 levels) ......•.•...••......•••.......••.....•..•.....•.......••..•...••••.....•• 3·26
Cascaded Interrupt Control Unit Connections ...........•.........•..........•................•..........•.....•.. 3·27
Service Sequence ............•..............••....•••.....•.••....••.•......••••.•...•.•...•...•.•...•.•.•..•3·28
Slave Processor Protocol .......................•..•...•••....••••..••••••.....•••••...•.•••....••••.....••••.. 3·29
Slave Processor Status Word Format •.....•.•.......•......•.........•......•....•..••..•...••.•.....•••......•• 3·30
NS32C032 Connection Diagram ..........................•.............•..•................•.•....••........•...4·1
Timing Specification Standard (Signal Valid After Clock Edge) ..•.•..•....••.•...••.••...•••.•.•..••.•.•...•••••.•.••• 4·2
Timing Specification Standard (Signal Valid Before Clock Edge) .•...............•.......••......••.....•............ .4·3
Write Cycle ...........................•......•••....••.•......•••......•••.•..••••......•••.•..••••...••••.•..• 4-4
Read Cycle •...........••..................................................•.......•........•...••...•..•......4·5
Floating by HOLD Timing (CPU Not Initially Idle) ...•........••.•..•••••....•.••....••........•••.....•....••••.••..• 4·6
Floating by HOLD Timing (CPU Initially Idle) ....•....•.......•........•........................•.....•............ .4·7
Release from Hold .................•............................•.......•.......••.......••.•..••••...•.••.••..4·8
FLT Initiated Float Cycle Timing .............•••.....••.•... , ..•.••.•..••..•....••••....••....•••.•.•..•••.•..•••. 4-9
Release from FLT Timing .....................................•....................................•........•..4·10
Ready Sampling (CPU Initially READy) .............•••.....••.......••......••..•..........•..•......••......... 4·11
Ready Sampling (CPU Initially NOT READY) ...............................•••......•.•.....•••....•••.......•••..4·12
Slave Processor Write Timing ................•......•••......•••....••••..•.••.•....••••.••..•••••...••••.....•. 4·13
Slave Processor Read Timing ............................................•..................................•.. 4·14
SPCTiming ..........•..............•.•....•••.....••.....•••........•.•...••••..•..••.••...•.•.••.••.•....•. 4·15
Reset Configuration Timing ........................••......•..•.......•..............•...............•......•...4·16
Clock Waveforms .................................••.•...•..•••...••••..•...•.••...•.•.•...•.•.....••••....... 4·17
Relationship of PFS to Clock Cycles .................................................................•........•..4·18
Guaranteed Delay, PFS to Non·Sequential Fetch ........••.....•.•......•••••...••.•.•..••••...••••••....••••... 4·19a
Guaranteed Delay, Non·Sequential Fetch to PFS .............................•.......••...•..................... 4·19b
Relationship of ILO to First Operand of an Interlocked Instruction •...•••......••.......••......••...•.•••...•••••.. 4·20a
Relationship of ILO to Last Operand of an Interlocked Instruction ...............•.....•..•....•..••................ 4·20b
Relationship of ILO to Any Clock Cycle .....................••.•....••••...•..•••....••••..•...•..•...•........•. 4·21
U/S Relationship to any Bus Cycle - Guaranteed Valid Interval. ....................•..•.......................•.•.. 4·22
Abort Timing, FLT Not Applied ............•........••......•.•••...••••.•.....•••...••.••••.•..•.•...•••.....•• .4·23
Abort Timing, FLT Applied ....................................•............•........•........................•.. 4·24
Power·On Reset ..................•.....•••......••.......•••..•...••••••.••.•••..•••.•.•...•••....•••.•...••• 4·25
Non·Power·On Reset. ...................................•...•......•.......................................... 4·26
INT Interrupt Signal Detection .............................•.......•........••.••....••..............•..........4·27
MNllnterrupt Signal Timing ............•.......•.......•.••...•..•......••••....••.•......•••...••.•.•...•.•••.. 4·28
Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction •.........................• 4·29
Processor System Connection Diagram ...........••..............•.......•••......•...............•••...•••••.... B·1
2·170
z
List of Tables
NS32C032 Addressing Modes ...................................................................................2-1
NS32C032 Instruction Set Summary ..............................................................................2-2
Bus Access Type ..............................................................................................3-1
Access Sequence ..............................................................................................3-2
Interrupt Sequences ............................................................................................3-3
Floating Point Instruction Protocols ...............................................................................3-4
Memory Management Instruction Protocols ..........................................................•...••........3-5
Custom Slave Instruction Protocols ...............................•................................•.........•.... 3-6
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1.0 Product Introduction
The Series 32000 microprocessor family is a new generation of devices using National's XMaS and CMOS technologies. By combining state-of-the-art MaS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. The family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
• High-Level Language Support
• Easy Future Growth Path
• Application Flexibility
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes 16 registers on the
NS32C032 CPU.
2.1.1 General Purpose Registers
There are eight registers for meeting high speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are thirty-two bits in
length. If a general register is specified for an operand that
is eight or sixteen bits long, only the low part of the register
is used; the high part is not referenced or modified.
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
2.1.2 Dedicated Registers
The eight dedicated registers of the NS32C032 are asSigned specific functions.
PC: The PROGRAM COUNTER register is a pointer to
the first byte of the instruction currently being executed.
The PC is used to reference memory in the program
section. (In the NS32C032 the upper eight bits of this
register are always zero.)
SPO, SP1: The SPO register points to the lowest address
of the last item stored on the INTERRUPT STACK. This
stack is normally used only by the operating system. It is
used primarily for storing temporary data, and holding
return information for operating system subroutines and
interrupt and trap service routines. The SP1 register
points to the lowest address of the last item stored on
the USER STACK. This stack is used by normal user
programs to hold temporary data and subroutine return
information.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
Symmetric Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each op·
erand can be referenced by anyone of the addressing
modes provided. This powerful memory·to·memory archi·
tecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
Memory Management. Either the NS32382 or the
NS32082 Memory Management Unit may be added to the
system to provide advanced operating system support func·
tions, including dynamic address translation, virtual memory
management, and memory protection.
Large, Uniform Addressing. The NS32C032 has 24-bit address pOinters that can address up to 16 megabytes without
requiring any segmentation; this addressing scheme provides flexible memory management without added-on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to ac·
cess, which allows a significant reduction in hardware and
software cost.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by speCial slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
In this document, reference is made to the SP register.
The terms "SP register" or "SP" refer to either SPO or
SP1, depending on the setting of the S bit in the PSR
register. If the S bit in the PSR is 0 the SP refers to SPO.
If the S bit in the PSR is 1 then SP refers to SP1. (In the
NS32C032 the upper eight bits of these registers are
always zero).
Stacks in the Series 32000 family grow downward in
memory. A Push operation pre-decrements the Stack
Pointer by the operand length. A Pop operation post-increments the Stack Pointer by the operand length.
FP: The FRAME POINTER register is used by a procedure to access parameters and local variables on the
stack. The FP register is set up on procedure entry with
the ENTER instruction and restored on procedure termination with the EXIT instruction.
The frame pOinter holds the address in memory occupied by the old contents of the frame pointer. (In the
NS32C032 the upper eight bits of this register are always zero.)
58: The STATIC BASE register points to the global vari·
abies of a software module. This register is used to support relocatable global variables for software modules.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
2-172
z
2.0 Architectural Description
en
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(Continued)
DEDICATED
GENERAL
N
(')
0
32
N
.
c.:I
.....
~--------32----------~
PROGRAM COUNTER
I
PC
STATIC BASE
I
SB
0
RO
"Z
en
Rl
c.:I
N
(')
0
R2
FRAME POINTER \ FP
.
R3
c.:I
N
USER STACK PTR. \ SP1 }
INTERRUPT STACK PTR.
I
SP
.....
R4
SPO
U1
R5
·0
INTERRUPT BASE \INTBASE
PSR
MOD
STATUS
MODULE
R6
R7
TLlEE/9160·3
FIGURE 2·1. The General and Dedicated Registers
The SB register holds the lowest address in memory
occupied by the global variables of a module. (In the
NS32C032 the upper eight bits of this register are al·
ways zero.)
Z: The Z bit is altered by comparison instructions. In a
comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is
set to "0".
INTBASE: The INTERRUPT BASE register holds the
address of the dispatch table for interrupts and traps
(Sec. 3.8). The INTBASE register holds the lowest address in memory occupied by the dispatch table. (In the
NS32C032 the upper eight bits of this register are always zero.)
N: The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to "1" if the sec·
ond operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to "0".
U: If the U bit is "1" no privileged instructions may be
executed. If the U bit is "0" then all instructions may be
executed. When U = 0 the NS32C032 is said to be in
Supervisor Mode; when U = 1 the NS32C032 is said to
be in User Mode. A User Mode program is restricted
from executing certain instructions and accessing cer·
tain registers which could interfere with the operating
system. For example, a User Mode program is prevented from changing the setting of the flag used to indicate
its own privilege mode. A Supervisor Mode program is
assumed to be a trusted part of the operating system,
hence it has no such restrictions.
S: The S bit specifies whether the SPO register or SP1
register is used as the stack pointer. The bit is automatically cleared on interrupts and traps. It may have a setting of 0 (use the SPO register) or 1 (use the SP1 register).
P: The P bit prevents a TRC trap from occurring more
than once for an instruction (Sec. 3.8.5.). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
I: If I = 1, then all interrupts will be accepted (Sec. 3.8.).
If I = 0, only the NMI interrupt is accepted. Trap enables are not affected by this bit.
MOD: The MODULE register holds the address of the
module descriptor of the currently executing software
module. The MOD register is sixteen bits long, therefore
the module table must be contained within the first 64K
by1es of memory.
PSR: The PROCESSOR STATUS REGISTER (PSR)
holds the status codes for the NS32C032 microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all
programs, but the high order eight bits are accessible
only to programs executing in Supervisor Mode.
TL/EE/9160-4
FIGURE 2·2. Processor Status Register
C: The C bit indicates that a carry or borrow occurred
after an addition or subtraction instruction. It can be
used with the AD DC and SUBC instructions to perform
multiple-precision integer arithmetic calculations. It may
have a setting of 0 (no carry or borrow) or 1 (carry or
borrow).
T: The T bit causes program tracing. If this bit is a 1, a
TRC trap is executed after every instruction (Sec. 3.8.5).
L: The L bit is altered by comparison instructions. In a
comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as unsigned integers. Otherwise, it is set to "0". In Floating Point comparisons, this
bit is always cleared.
F: The F bit is a general condition flag, which is altered
by many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
2.1.3 The Configuration Register (CFG)
Within the Control section of the NS32C032 CPU is the fourbit CFG Register, which declares the presence of certain
external devices. It is referenced by only one instruction,
SETCFG, which is intended to be executed only as part of
system initialization after reset. The format of the CFG Register is shown in Figure 2-3.
FIGURE 2-3. CFG Register
2-173
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2.0 Architectural Description
U)
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(Continued)
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the NS32202 Interrupt Control Unit). It the CFG I bit is set, interrupts requested through
the INT pin are "Vectored." If it is clear, these interrupts are
"Non-Vectored." See Sec. 3.S.
The F, M and C bits declare the presence of the FPU, MMU
and Custom Slave Processors. If these bits are not set, the
corresponding instructions are trapped as being undefined.
The MOD register contains a pOinter into the Module Table,
whose entries are called Module Descriptors. A Module Descriptor contains four pOinters, three of which are used by
NS32C032. The MOD register contains the address of the
Module Descriptor for the currently running module. It is automatically up-dated by the Call External Procedure instructions (CXP and CXPD).
The format of a Module Descriptor is shown in Figure 2-4.
The Static Base entry contains the address of static data
assigned to the running module. It is loaded into the CPU
Static Base register by the CXP and CXPD instructions. The
Program Base entry contains the address of the first byte of
instruction code in the module. Since a module may have
multiple entry pOints, the Program Base pointer serves only
as a reference to find them.
2.1.4 Memory Organization
The main memory of the NS32C032 is a uniform linear address space. Memory locations are numbered sequentially
starting at zero and ending at 224 - 1. The number specifying a memory location is called an address. The contents of
each memory location is a byte consisting of eight bits. Unless otherwise noted, diagrams in this document show data
stored in memory with the lowest address on the right and
the highest address on the left. Also, when data is shown
vertically, the lowest address is at the top of a diagram and
the highest address at the bottom of the diagram. When bits
are numbered in a diagram, the least significant bit is given
the number zero, and is shown at the right of the diagram.
Bits are numbered in increasing significance and toward the
left.
o
15
I
MOD
I
1
or
°U
31
STATIC BASE
LINK TABLE ADDRESS
PROGRAM BASE
Byte at Address A
115 MSB's
sI7
LSB's
FIGURE 2-4. Module Descriptor Format
The Link Table Address points to the Link Table for the
currently running module. The Link Table provides the information needed for:
1) Sharing variables between modules. Such variables are
accessed through the Link Table via the External addressing mode.
2) Transferring control from one module to another. This is
done via the Call External Procedure (CXP) instruction.
01
Two contiguous words are called a double word. Except
where noted (Sec. 2.2.1), the least significant word of a double word is stored at the lowest address and the most significant word of the double word is stored at the address two
greater. In memory, the address of a double word is the
address of its least significant byte, and a double word may
start at any address.
sI7
A+3
A+2
A+1
Double Word at Address A
LSB's
°
TL/EE/9160-5
A
A+l
Word at Address A
RESERVED
...
Two contiguous bytes are called a word. Except where noted (Sec. 2.2.1), the least significant byte of a word is stored
at the lower address, and the most significant byte of the
word is stored at the next higher address. In memory, the
address of a word is the address of its least significant byte,
and a word may start at any address.
The format of a Link Table is given in Figure 2-5. A Link
Table Entry for an external variable contains the 32-bit address of that variable. An entry for an external procedure
contains two 16-bit fields: Module and Offset. The Module
field contains the new MOD register contents for the module being entered. The Offset field is an unsigned number
giving the position of the entry point relative to the new
module's Program Base pOinter.
For further details of the functions of these tables, see the
Series 32000 Instruction Set Reference Manual.
01
A
Although memory is addressed as bytes, it is actually organized as double-words. Note that access time to a word or a
double-word depends upon its address, e.g. double-words
that are aligned to start at addresses that are multiples of
four will be accessed more quickly than those not so
aligned. This also applies to words that cross a double-word
boundary.
ENTRY
o-r
31
o
ABSOLUTE ADDRESS
(VARIABLE)
ABSOLUTE ADDRESS
(VARIABLE)
OFFSET
2.1_5 Dedicated Tables
Two of the NS32C032 dedicated registers (MOD and INTBASE) serve as pOinters to dedicated tables in memory.
The INTBASE register points to the Interrupt Dispatch and
Cascade tables. These are described in Sec. 3.S.
'-
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MODULE
( PROCEDURE)
-'TL/EE/9160-6
FIGURE 2·5. A Sample Link Table
2-174
z
2.0 Architectural Description
en
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(Continued)
2.2 INSTRUCTION SET
17 0
2.2.1 General Instruction Format
Figure 2·6 shows the general format of a Series 32000 in·
struction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5·bit General Ad·
dressing Mode ("Gen") fields. Following the Basic Instruction field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes selected.
GEN. ADDR. MODE
l
REG. NO.
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SIGNED DISPLACEMENT
I
N
(")
Word Displacement: Range -8192 to +8191
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Double Word Displacement:
Range (Entire Addressing Space)
'I
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7
1
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1
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FIGURE 2-8. Displacement Encodlngs
2.2.2 Addressing Modes
The NS32C032 CPU generally accesses an operand by calculating its Effective Address based on information available when the operand is to be accessed. The method to be
used in performing this calculation is specified by the programmer as an "addressing mode."
OPTIONAL
ExrENSIONS
BASIC
INSTRUCTION
r~--------------~A~--------------~\~~
I
DISP2 DISPI OlSP21DISPl
IMM
•
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Some instructions require additional, "implied" immediates
and I or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Sec. 2.2.3).
DISP
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DISP
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FIGURE 2-7. Index Byte Format
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected address modes. Each Disp/lmm field may contain one or
two displacements, or one immediate value. The size of a
Displacement field is encoded with the top bits of that field,
as shown in Figure 2-8, with the remaining bits interpreted
as a signed (two's complement) value. The size of an immediate value is determined from the Opcode field. Both Displacement and Immediate fields are stored most significant
byte first. Note that this is different from the memory representation of data (Sec. 2.1.4).
IMPUED
IMMEDIATE
OPERAND(S)
Q
Q
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-7.
I'
N
Byte Displacement: Range -64 to +63
I
I
INDEX
BYTE
INDEX
BYTE
GEN
ADDR
MODE
A
IMM
...
t
)J
I
I
I
I
GEN
ADDR
MODE
I
B
I
I
:
OPCODE
TL/EE/9160-7
FIGURE 2-6. General Instruction Format
2-175
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~
2.0 Architectural Description
8
Addressing modes in the NS32C032 are designed to optimally support high-level language accesses to variables. In
nearly all cases, a variable access requires only one addressing mode, within the instruction that acts upon that
variable. Extraneous data movement is therefore minimized.
NS32C032 Addressing Modes fall into nine basic types:
C')
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(Continued)
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
2.2.3 Instruction Set Summary
Table 2-2 presents a brief description of the NS32C032 instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Notations:
i = Integer length suffix: B = Byte
W = Word
Memory Space. Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers pOint to data areas generally needed by high-level languages.
Memory Relative: A pointer variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pOinter to generate the Effective Address of the operand.
D = Double Word
f = Floating Point length suffix:
F = Standard Floating
L = Long Floating
gen = General operand. Any addressing mode can be
specified.
short = A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
imm = Implied immediate operand. An 8-bit value appended after any addressing extensions.
disp = Displacement (addressing constant): 8, 16 or 32
bits. All three lengths legal.
reg = Any General Purpose Register: RO-R7.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
External: A pOinter value is read from a specified entry of
the current Link Table. To this pOinter value is added a displacement, yielding the Effective Address of the operand.
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode.
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
areg = Any Dedicated/Address Register: SP, SB, FP,
MOD, INTBASE, PSR, US (bottom 8 PSR bits).
mreg = Any Memory Management Status/Control Register.
creg = A Custom Slave Processor Register (Implementation Dependent).
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
2-176
z
2.0 Architectural Description
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(Continued)
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TABLE 2-1
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NS32C032 Addressing Modes
ENCODING
Register
00000
00001
00010
00011
00100
00101
00110
00111
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Memory Relative
10000
10001
10010
Reserved
10011
Immediate
10100
Absolute
10101
External
10110
Top of Stack
10111
Memory Space
11000
11001
11010
11011
Scaled Index
11100
11101
11110
11111
•
0
.....
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-0.
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
ROor FO
Rl or Fl
R20r F2
R30rF3
R40r F4
R50rF5
R60rF6
R70rF7
None: Operand is in the specified
register
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(Rl)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Frame memory relative
Stack memory relative
Static memory relative
disp2(displ (FP»
disp2(displ (SP»
disp2(displ (SB»
Disp2 + Pointer; Pointer found at
address Displ + Register. "SP"
is either SPO or SP1, as selected
in PSR.
Immediate
value
None: Operand is input from
instruction queue.
Absolute
@disp
Disp.
External
EXT (displ) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Displ.
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
*+disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2 x Rn.
EA (mode) + 4X Rn.
EA (mode) + B x Rn.
'Mode' and 'n' are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
N
0
Co)
•
-0.
(II
(Reserved for Future Use)
2-177
0
N
.... r-----------------------------------------------------------------------------,
~
~
C")
~
en
z
......
Q
....
§
C'II
~
2.0 Architectural Description (Continued)
TABLE 2-2
NS32C032 Instruction Set Summary
MOVES
Format
4
2
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4-bit constant.
Move Multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move Effective Address.
INTEGER ARITHMETIC
Format
4
2
4
4
4
6
6
7
7
7
7
7
7
7
Operation
Operands
Description
ADDI
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEIi
DEli
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to Extended Integer.
Divide Extended Integer.
PACKED DECIMAL (BCD) ARITHMETIC
Format
6
6
Operation
Operands
Description
ADDPi
SUBPi
gen,gen
gen,gen
Add Packed.
Subtract Packed.
INTEGER COMPARISON
Format
4
2
7
Operation
Operands
Description
CMPi
CMPQi
CMPMi
gen,gen
short,gen
gen,gen,disp
Compare.
Compare to signed 4-bit constant.
Compare Multiple: disp bytes (1 to 16).
Operation
Operands
Description
ANDi
ORi
BICi
XORi
COMi
NOTi
Scondi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Logical AND.
Logical OR.
Clear selected bits.
Logical Exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
LOGICAL AND BOOLEAN
Format
4
4
4
4
6
6
2
2-178
z
2.0 Architectural Description
tn
Co)
(Continued)
N
TABLE 2·2 (Continued)
NS32C032 Instruction Set Summary (Continued)
Operation
Operands
Description
LSHi
ASHi
ROTi
gen,gen
gen,gen
gen,gen
Logical Shift, left or right.
Arithmetic Shift, left or right.
Rotate, left or right.
4
6
6
6
6
6
8
Co)
Z
tn
Co)
N
0
0
Co)
BITS
Format
0
N
....•
0
......
SHIFTS
Format
6
6
6
0
N
....•
Operation
Operands
Description
TBITi
SBITi
SBITli
CBITi
CBITli
IBITi
FFSi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Test bit.
Test and set bit.
Test and set bit, interlocked
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit
UI
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records
used in Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned
source.
Format
8
8
7
7
8
Operation
Operands
Description
EXTi
INSi
EXTSi
INSSi
CVTP
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm,imm
reg,gen,gen
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to Bit Field Pointer.
Operation
Operands
Description
CHECKi
INDEXi
reg,gen,gen
reg,gen,gen
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
ARRAYS
Format
8
8
STRINGS
Options on all string instructions are:
String instructions assign specific functions to the Gen·
eral Purpose Registers:
B (Backward):
Decrement string pointers after each step
rather than incrementing.
U (Until match):
End instruction if String 1 entry matches
R4.
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
W(While
match):
R 1 - String 1 Pointer
RO - Limit Count
End instruction if String 1 entry does not
match R4.
All string instructions end when RO decrements to zero.
Format
5
Operation
Operands
Descriptions
MOVSi
MOVST
options
options
Move String 1 to String 2.
Move string, translating bytes.
5
CMPSi
CMPST
options
options
Compare String 1 to String 2.
Compare translating, String 1 bytes.
5
SKPSi
SKPST
options
options
Skip over String 1 entries
Skip, translating bytes for Until/While.
2-179
fII
~
.....
~
8
r---------------------------------------------------------------------------------,
2.0 Architectural Description (Continued)
TABLE 2-2 (Continued)
NS32C032 Instruction Set Summary (Continued)
N
~
Z
.....
CI
.....
~
8
N
CO)
tn
Z
JUMPS AND LINKAGE
Format
Operation
3
JUMP
BR
0
0
Bcond
3
CASEi
2
ACBi
3
JSR
BSR
1
1
CXP
CXPD
3
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
[reg listl,disp
[reg list]
disp
disp
disp
CPU REGISTER MANIPULATION
Format
Operation
Operands
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor Call.
Flag Trap.
Breakpoint Trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
Description
SAVE
RESTORE
LPRi
SPRi
ADJSPi
BISPSRi
BICPSRi
SETCFG
[reg listl
[reg listl
areg,gen
areg,gen
gen
gen
gen
[option list]
Save General Purpose Registers.
Restore General Purpose Registers.
Load Dedicated Register. (Privileged if PSR or INTBASE)
Store Dedicated Register. (Privileged if PSR or INTBASE)
Adjust Stack Pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set Configuration Register. (Privileged)
FLOATING POINT
Format
Operation
Operands
Description
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Move a Floating Point value.
Move and shorten a Long value to Standard.
Move and lengthen a Standard value to Long.
Convert any integer to Standard or Long Floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Load FSR.
Store FSR.
1
2
2
3
3
3
5
11
9
9
9
9
9
9
11
11
11
11
11
11
11
9
9
MOVf
MOVLF
MOVFL
MOVif
ROUNDfi
TRUNCli
FLOORfi
ADDf
SUBf
MULf
DIVf
CMPf
NEGf
ABSf
LFSR
SFSR
MEMORY MANAGEMENT
Format
Operation
Operands
Description
14
14
14
14
8
LMR
SMR
RDVAL
WRVAL
MOVSUi
mreg,gen
mreg,gen
gen
gen
gen,gen
8
MOVUSi
gen,gen
Load Memory Management Register. (Privileged)
Store Memory Management Register. (Privileged)
Validate address for reading. (Privileged)
Validate address for writing. (Privileged)
Move a value from Supervisor
Space to User Space. (Privileged)
Move a value from User Space
to Supervisor Space. (Privileged)
2-180
z
2.0 Architectural Description
(/)
Co)
(Continued)
N
TABLE 2-2 (Continued)
NS32C032 Instruction Set Summary (Continued)
MISCELLANEOUS
Format
Operation
1
NOP
WAIT
DIA
0
Co)
...•
N
Operands
Description
No Operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
0
.......
Z
(/)
Co)
N
0
0
Co)
...•
N
CUSTOM SLAVE
Format
0
Operation
Operands
Description
15.5
15.5
15.5
15.5
CCALOc
CCAL1c
CCAL2c
CCAL3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom Calculate.
15.5
15.5
15.5
15.5
CMOVOc
CMOV1c
CMOV2c
CMOV3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom Move.
15.5
15.5
CCMPOc
CCMP1c
gen,gen
gen,gen
Custom Compare.
15.1
15.1
15.1
15.1
15.1
15.1
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Custom Convert.
15.1
15.1
LCSR
SCSR
gen
gen
Load Custom Status Register.
Store Custom Status Register.
15.0
15.0
CATSTO
CATST1
gen
gen
Custom Address/Test. (Privileged)
(Privileged)
15.0
15.0
LCR
SCR
creg,gen
creg,gen
Load Custom Register. (Privileged)
Store Custom Register. (Privileged)
2-181
U1
....
~.-------------------------------------------------------------~
N
Cf)
8
C"I
:az
c;
....
N
Cf)
8
C"I
:az
3.0 Functional Description
Each rising edge of PHI1 defines a transition in the timing
state ("T-State") of the CPU. One T-State represents the
execution of one microinstruction within the CPU, and/or
one step of an external bus transfer. See Section 4 for complete specifications of PHI1 and PHI2.
3.1 POWER AND GROUNDING
The NS32C032 requires a single 5-volt power supply, applied on 4 pins. The Logic Voltage pins (VccL1 and VccL2)
supply the power to the on-chip logic. The Buffer Voltage
pins (VCCBl and VCCB2) supply the power to the output drivers of the chip. The Logic Voltage pins and the Buffer Voltage pins should be connected together by a power (Vccl
plane on the printed circuit board.
The NS32C032 grounding connections are made on 5 pins.
The Logic Ground pins (GNDL 1 and GNDL2) are the ground
pins for the on-chip logic. The Buffer Ground pins (GNDB1
to GNDB3) are the ground pins for the output drivers of the
chip. The Logic Ground pins and the Buffer Ground pins
should be connected together by a ground plane on the
printed circuit board.
PHil
PHI2
Both power and ground connections are shown below (Figure 3-1).
NON-OVERLAPPING
+5V
TLlEE/91S0-13
FIGURE 3-2. Clock Timing Relationships
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHI1 and PHI2
be kept as short as possible, and that they not be connected anywhere except from the TCU to the CPU and, if present, the MMU. A TTL Clock signal (CTTL) is provided by the
TCU for all other clocking.
OTHER Vee
CONNECTIONS
(Vee PLANE)
NS32C032
CPU
...,~...
~
_ _ _....
3.3 RESETTING
The RST / ABT pin serves both as a Reset for on-Chip logic
and as the Abort input for Memory-Managed systems. For
its use as the Abort Command, see Sec. 3.5.4.
The CPU may be reset at any time by pulling the RST/ ABT
pin low for at least 64 clock cycles. Upon detecting a reset,
the CPU terminates instruction proceSSing, resets its internal logic, and clears the Program Counter (PC) and Processor Status Register (PSR) to all zeroes.
On application of power, RST/ ABT must be held low for at
least 50 ].Lsec after Vee is stable. This is to ensure that all
on-chip voltages are completely stable before operation.
Whenever a Reset is applied, it must also remain
OTHER GROUND
CONNECT10NS
(GNO PLANE)
TL/EE/91S0-12
FIGURE 3-1. Recommended Supply Connections
3.2 CLOCKING
The NS32C032 inputs clocking signals from the Timing
Control Unit (TCU), which presents two non-overlapping
phases of a single clock frequency. These phases are
called PHI1 (pin 26) and PHI2 (pin 27). Their relationship to
each other is shown in Figure 3-2.
vcc
PHil
---t---~I
r--
AST/Aii'i'
i!: 64 CLOCK
JJJL
CYCLES
---j----------U---'
1-----i!:50,,1II!C - - - - - - 1
TLlEE/91S0-14
FIGURE 3-3. Power-on Reset Requirements
2-182
z
3.0 Functional Description
en
w
(Continued)
PHll~JUL
active for not less than 64 clock cycles. The rising edge
must occur while PHil is high. See Figures 3-3 and 3-4.
L
The NS32C201 Timing Control Unit (TCU) provides circuitry
to meet the Reset requirements of the NS32C032 CPU. Figure 3-5a shows the recommended connections for a nonMemory-Managed system. Figure 3-5b shows the connections for a Memory-Managed system.
.-2:64CLOCK---i
CYCLES
____---.I<""'<".........;r--
~
RST/Aai'
~""~
,-
r~
I
TL/EE/9160-15
FIGURE 3-4. General Reset Timing
Vcc
NS32C201
lCU
NS32C032
CPU
r------------,
I
I
II ~
]~~Ir_~_4r_~--~~~~------~
I
!I... _____________ .JI
EXTERNAL RESET
(OPTIONAL)
RSTI
RsTc51------.....,>--------~
iiSr/AiT
" 50"....
RESET SWITCH
(OPTIONAL)
SYSTEM RESET
TL/EE/9160-16
FIGURE 3-5a. Recommended Reset Connections, Non-Memory-Managed System
vcc
NS32C201
TCU
N83Zoaz
MMU
NS32C032
CPU
r------------,
I
I
II RESET
I
J>--tl---t-....,.--T---+~...--------l
!I... _____________ .JI
i'iSTi
RsTo
EXTERNAL RESET
(OPTIONAL)
RESET SWITCH
(OPTIONAL)
TL/EE/9160-17
FIGURE 3-5b. Recommended Reset Connections, Memory-Managed System
3) To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
4) To transfer information to or from a Slave Processor.
3.4 BUS CYCLES
The NS32C032 CPU has a strap option which defines the
Bus Timing Mode as either With or Without Address Translation. This section describes only bus cycles under the No
Address Translation option. For details of the use of the
strap and of bus cycles with address translation, see Sec.
3.5.
The CPU will perform a bus cycle for one of the following
reasons:
In terms of bus timing, cases 1 through 3 above are identical. For timing specifications, see Sec. 4. The only external
difference between them is the four-bit code placed on the
Bus Status pins (STO-ST3). Slave Processor cycles differ in
that separate control signals are applied (Sec. 3.4.6).
The sequence of events in a non-Slave bus cycle is shown
below in Figure 3-7 for a Read cycle and Figure 3-8 for a
Write cycle. The cases shown assume that the selected
memory or interface device is capable of communicating
with the CPU at full speed. If it is not, then cycle extension
may be requested through the RDY line (Sec. 3.4.1).
1) To write or read data, to or from memory or a peripheral
interface device. Peripheral input and output are memorymapped in the Series 32000 family.
2) To fetch instructions into the eight-byte instruction queue.
This happens whenever the bus would otherwise be idle
and the queue is not already full.
2-183
N
o
C)
w
....~
C)
......
z
en
w
N
oC)
w
....~
U1
...
II)
I
N
C")
o
oN
C")
en
z
......
...o
I
N
C")
o
oN
C")
en
z
3.0 Functional Description (Continued)
A full-speed bus cycle is performed in four cycles of the
PHI1 clock signal, labeled T1 through T4. Clock cycles not
associated with a bus cycle are designated Ti (for "Idle").
The T3 state provides for access time requirements, and it
occurs at least once in a bus cycle. At the end of T2 or T3,
on the falling edge of the PHI2 clock, the RDY (Ready) line
is sampled to determine whether the bus cycle will be extended (Sec. 3.4.1).
If the CPU is performing a Read cycle, the Data Bus (ADOAD31) is sampled at the falling edge of PHI2 of the last T3
state. See Section 4. Data must, however, be held at least
until the beginning of T4. DS and RD are guaranteed not to
go inactive before this point, so the rising edge of either of
them may safely be used to disable the device providing the
input data.
The T4 state finishes the bus cycle. At the beginning of T4,
the DS, RD or WR, and TSO signals go inactive, and at the
rising edge of PHI2, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles remains valid from the CPU throughout T4. Note that the Bus
Status lines (STO-ST3) change at the beginning of T4, anticipating the following bus cycle (if any).
During T1, the CPU applies an address on pins ADO-AD23 .
It also provides a low-going pulse on the ADS pin, which
serves the dual purpose of informing external circuitry that a
bus cycle is starting and of providing control to an external
latch for demultiplexing Address bits 0-23 from the ADOAD23 pins. See Figure 3-6. During this time also the status
signals DDIN, indicating the direction of the transfer, and
BEO-BE3, indicating which of the four bus bytes are to be
referenced, become valid.
During T2 the CPU switches the Data Bus, ADO-AD31 to
either accept or present data. It also starts the data strobe
(DS), signalling the beginning of the data transfer. Associated signals from the NS32C201 Timing Control Unit are also
activated at this time: RD (Read Strobe) or WR (Write
Strobe), TSO (Timing State Output, indicating that T2 has
been reached) and DBE (Data Buffer Enable).
ODIN
I--:-""f'-----l
024-031
AOO-A023
NS32C032
PHil
PHI2
OS/FLT
os
PHil
PHI2
A05
ODIN
OBE
RO
ROr-----------~-
NS32C201
WR
WR t-----------~-
T50
T50 / - - - - - - - - - - - - TLlEE/9160-1B
FIGURE 3-6. Bus Connections
2-184
z
3.0 Functional Description
I
PHI 1
en
w
(Continued)
T40RTi
I
I\)
oo
NS32C032 CPU BUS SIGNALS
n
T2
TJ
T4
I
nORTi
w
I\)
......
o
......
I
I
[
z
en
w
I\)
PHI 2
oo
[
w
I\)
......
I
U1
ADO-A023
[
02 ....031
[
AOS
[
ST()'ST3
[
0iiiN
[
BED-In
[
OS
[
ROY
[
TSO
[
TL/EE/9160-20
FIGURE 3-7. Read Cycle Timing
2·185
It)
.....
c.:..
CO)
3.0 Functional Description
(Continued)
o
NS32C032 CPU BUS SIGNALS
~
CO)
en
T40RTi
z
......
.
o.....
PHil
[
PHI2
[
N
I
T1
T2
T3
T4
I
TIORTi
I
ao
N
CO)
en
z
ADO-AD23 [
DATA OUT
02....031 [
DATA OUT
m[
STO-ST3 [
i5iiiN
[
iiEo-iii3
[
i5S
[
RDv
[
Ro
[
WR
[
OBE
[
TSO
[
STATUS VA~IO
VA~ID
NEXT
TL/EE/9160-19
FIGURE 3-8. Write Cycle Timing
2·186
z
3.0 Functional Description
U)
Co)
I\)
(Continued)
3.4.1 Cycle Extension
The RDY pin is driven by the NS32C201 Timing Control
Unit, which applies WAIT States to the CPU as requested
on three sets of pin:
1) CWAIT (Continuous WAIT), which holds the CPU in WAIT
states until removed.
2) WAIT1, WAIT2, WAIT4, WAIT8 (Collectively WAITn),
which may be given a four-bit binary value requesting a
specific number of WAIT States from 0 to 15.
3) PER (Peripheral), which inserts five additional WAIT
states and causes the TCU to reshape the RD and WR
strobes. This provides the setup and hold times required
by most MOS peripheral interface devices.
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32C032 provides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-7 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are flat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the RDY (Ready) pin.
At the end of T2 on the falling edge of PHI2, the RDY line is
sampled by the CPU. If RDY is high, the next T -states will be
T3 and then T4, ending the bus cycle. If RDY is low, then
another T3 state will be inserted after the next T -state and
the RDY line will again be sampled on the falling edge of
PHI2. Each additional T3 state after the first is referred to as
a "WAIT STATE". See Figure 3-9.
T1
T2
oc
Co)
~
.....
c
......
Z
U)
Co)
I\)
o
c
.
Co)
I\)
.....
CI1
Combinations of these various WAIT requests are both legal
and useful. For details of their use, see the NS32C201 Data
Sheet.
Figure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the TCU WAITn pins.
T3
I
(w~m
I
T4
PHil
PHI 2
RDY
TL/EE/9160-21
FIGURE 3-9. ROY Pin Timing
To acknowledge receipt of a Maskable Interrupt
(on INn it will read from address FFFE0016, expecting a vector number to be provided from the
Master NS32202 Interrupt Control Unit. If the vectoring mode selected by the last SETCFG instruction was Non-Vectored, then the CPU will ignore
the value it has read and will use a default vector
instead, having assumed that no NS32202 is
present. See Sec. 3.4.5.
0101 - Interrupt Acknowledge, Cascaded.
The CPU is reading a vector number from a Cascaded NS32202 Interrupt Control Unit. The address provided is the address of the NS32202
Hardware Vector register. See Sec. 3.4.5.
0110 - End of Interrupt, Master.
3.4.2 Bus Status
The NS32C032 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on
these pins indicate why the CPU is performing a bus cycle,
or, if it is idle on the bus, then why is it idle.
Referring to Figures 3-7 and 3-8, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1, and changing to the next state at T4. This allows
the system designer to fully decode the Bus Status and, if
desired, latch the decoded signals before ADS initiates the
Bus Cycle.
The Bus Status pins are interpreted as a four-bit value, with
STO the least significant bit. Their values decode as follows:
0000 - The bus is idle because the CPU does not need to
perform a bus access.
0001 - The bus is idle because the CPU is executing the
WAIT instruction.
0010 - (Reserved for future use.)
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt (RETI)
instruction. See Sec. 3.4.5.
0111 - End of Interrupt, Cascaded.
The CPU is reading from a Cascaded Interrupt
Control Unit to indicate that it is returning (through
RETI) from an interrupt service routine requested
by that unit. See Sec. 3.4.5.
0011 - The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100 - Interrupt Acknowledge, Master.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt (on
NMI) it will read from address FFFF0016, but will
ignore any data provided.
1000 - Sequential Instruction Fetch.
The CPU is reading the next sequential word from
the instruction stream into the Instruction
2-187
fII
~
~
,--------------------------------------------------------------------,
I
N
CO)
3.0 Functional Description
(Continued)
o
o
N
-
PHil [
CO)
PHI2 [
IT40RTiI
CO)
en
z
~
I
N
oN
en
z
-
024-031 [
L-!Ln-n-n-U- J
~ VALID
AOOR
~--~ ~
'W
~ W0 ~ ~--y; ~
'W
~~
NEXT CYCLE
InoRTl1
Jl Jl J
CO)
AOO-A023 [
Tl
- ILLIL
o
o
NS32C032 CPU BUS SIGNALS
PREY. CYCLE
U1LnUl-
~--OATAIN
""'--
IV
STD-ST3 [
~~
X
STATUS VALlO
.~~
NEXT STATU S
I~
~~
VALlO
-V
t-
M
DoiN[ ~ ~ ~
BeO-BE3 [
---
t-
NEXT ADO R
t-
NEXT
1\
NS32C201 TCU CYCLE EXTENSION SIGNALS
~
CWAIT [
~
%: tI//'~ Wd
~
~ ~~~~
~ ~ WI I~ ~W
IWh
~
~~~~
WAiTn[ ~ ~ ~ ~ ~~ ~ ~ ~~ ~ ~
/
ROY [
(TCUTOCPU )
NS32C201 TCU BUS SIGNALS
-
V
1I
-V
-J
rso[ -
/
V
1\
TL/EE/9160-22
FIGURE 3·10. Extended Cycle Example
Note: Arrows on CWAIT, PER, WAITn indicate points at which the TCU samples. Arrows on AOO-A015 and ROY indicate paints at which the CPU samples.
2-188
,--------------------------------------------------------------------------, z
3.0 Functional Description
en
Co)
(Continued)
Queue. It will do so whenever the bus would otherwise be idle and the queue is not already full.
1001 - Non-Sequential Instruction Fetch.
when BEO is low. The second bank, connected to data bus
pins AD8-AD15 is enabled when BE1 is low. The third and
fourth banks are enabled by BE2 and BE3, respectively.
See Figure 3-11.
The CPU is performing the first fetch of instruction
code after the Instruction Queue is purged. This
will occur as a result of any jump or branch, or any
interrupt or trap, or execution of certain instructions.
N
(')
oCo)
...o•
.....
N
z
en
Co)
N
(')
oCo)
...•
1010 - Data Transfer.
N
The CPU is reading or writing an operand of an
instruction.
1011 - Read RMW Operand.
The CPU is reading an operand which will subsequently be modified and rewritten. If memory protection circuitry would not allow the following
Write cycle, it must abort this cycle.
C11
1100 - Read for Effective Address Calculation.
The CPU is reading information from memory in
order to determine the Effective Address of an
operand. This will occur whenever an instruction
uses the Memory Relative or External addreSSing
mode.
1101 - Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing
the Operation Word of a Slave Processor instruction. See Sec. 3.9.1.
TL/EE/9160-23
1110 - Read Slave Processor Status.
FIGURE 3-11. Memory Interface
The CPU is reading a Status Word from a Slave
Processor. This occurs after the Slave Processor
has signalled completion of an instruction. The
transferred word tells the CPU whether a trap
should be taken, and in some instructions it presents new values for the CPU Processor Status
Register bits N, Z, L or F. See Sec. 3.9.1.
1111 - Broadcast Slave ID.
Since operands do not need to be aligned with respect to
the double-word bus access performed by the CPU, a given
double-word access can contain one, two, three, or four
bytes of the operand being addressed, and these by1es can
begin at various positions, as determined by A1, AO. Table
3-1 lists the 10 resulting access types.
TABLE 3-1
Bus Access Types
Type Bytes Accessed A 1,AO BE3 BE2 BE1 BEO
00
1
0
1
1
01
1
0
2
1
10
1
0
3
1
1
4
11
0
0
0
00
5
2
01
1
0
0
2
6
1
1
0
7
2
10
0
00
1
0
0
0
3
8
9
3
01
0
0
0
00
0
0
0
0
4
10
The CPU is initiating the execution of a Slave
Processor instruction. The ID By1e (first by1e of
the instruction) is sent to all Slave Processors,
one of which will recognize it. From this pOint the
CPU is communicating with only one Slave Processor. See Sec. 3.9.1.
3.4.3 Data Access Sequences
The 24-bit address provided by the NS32C032 is a by1e
address; that is, it uniquely identifies one of up to
16,777,216 eight-bit memory locations. An important feature
of the NS32C032 is that the presence of a 32-bit data bus
imposes no restrictions on data alignment; any data item,
regardless of size, may be placed starting at any memory
address. The NS32C032 provides special control signals.
Byte Enable (BEO-BE3) which facilitate individual byte accessing on a 32-bit bus.
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-States separating
them. The number of bus cycles required to transfer an operand depends on its size and its alignment. Table 3-2 lists
the bus cycles performed for each situation.
Memory is organized as four eight-bit banks, each bank receiving the double-word address (A2-A23) in parallel. One
bank, connected to Data Bus pins ADO-AD7 is enabled
2-189
•
U)
.,...
I
N
C')
,---------------------------------------------------------------------------------,
3.0 Functional Description
(Continued)
o
oN
TABLE 3·2
Access Sequences
C')
tf)
Data Bus
Z
.....
o
.,...
I
N
r~------------~A~----------~\
Cycle
Type
Address
Byte 3
Byte 2
Byte 1
Byte 0
C')
o
oN
C')
tf)
Z
A. Word at address ending with 11
1.
2.
4
1BYTE 1 1BYTE 01 +- A
o
A
Byte 0
A+ 1
0
X
B. Double word at address ending with 01
1.
2.
o
A
9
o
o
A+3
7
5
A
A
+
0
2
4
8
Byte 2
Byte 1
By1eO
X
X
X
X
By1e3
1
0
Byte 1
Byte 0
X
X
X
X
Byte 3
By1e2
IBYTE31 BYTE 21 BYTE 11 BYTE 01 +- A
o
1
A
o
o
E. Quad word at address ending with 00
1.
10
A
1BYTE 31 BYTE 21BYTE 11 BYTE 01 +- A
o
A+1
o
0
o
o
1.
2.
7
5
A
o
X
X
Byte 3
Byte 2
Byte 1
o
Byte 3
Byte 2
Byte 1
Byte 0
0
By1e 7
By1e 6
Byte 5
Byte 4
0
0
Byte 2
Byte 1
Byte 0
X
X
X
X
Byte 3
Byte 6
Byte 5
Byte 4
X
X
X
X
Byte 7
I
o
o
H. Quad word at address ending with 11
X
X
1BYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31BYTE 21 BYTE 1 BYTE 01 +- A
A+2
Other bus cycles (instruction prefetch or slave) can occur here.
7
3.
A+4
1
1
4.
5
0
A+6
o
Byte 0
1BYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 01 +- A
9
0
0
0
1.
A
2.
A+3
Other bus cycles (instruction prefetch or slave) can occur here.
A+4
0
0
3.
9
0
4.
A+7
G. Quad word at address ending with 10
0
1BYTE 71 BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 01 +- A
Other bus cycles (instruction prefetch or slave) can occur here.
2.
10
A + 4
0
0
0
F. Quad word at address ending with 01
X
Byte 1
0
D. Double word at address ending with 11
1.
2.
X
X
1BYTE 31 BYTE 21 BYTE 11 BYTE 01 +- A
C. Double word at address ending with 10
1.
2.
X
X
Byte 1
Byte 0
X
X
o
X
X
Byte 3
Byte 2
0
Byte 5
X
Byte 4
X
X
Byte 7
X
Byte 6
o
I
1BYTE 71BYTE 61 BYTE 51 BYTE 41 BYTE 31 BYTE 21BYTE 1 BYTE 01 +- A
1.
4
0
A
2.
B
A+1
0
0
Other bus cycles (instruction prefetch or slave) can occur here.
1.
4
0
1
A+4
1
2.
B
A+5
0
0
X = Don't Care
2-190
0
0
By1eO
X
X
X
X
Byte 3
Byte 2
By1e1
Byte 4
X
X
X
X
Byte 7
By1e6
Byte 5
z
3.0 Functional Description
(J)
Co)
(Continued)
3.4.3.1 Bit Accesses
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full. Sequential Fetches are always
type 10 Read cycles (Table 3-1).
The Bit Instructions perform byte accesses to the byte containing the designated bit. The Test and Set Bit instruction
(SBIT), for example, reads a byte, alters it, and rewrites it,
having changed the contents of one bit.
An access to a Bit Field in memory always generates a Double-Word transfer at the address containing the least significant bit of the field. The Double Word is read by an Extract
instruction; an Insert instruction reads a Double Word, modifies it, and rewrites it.
A Non·Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the instruction queue, causing the
next instruction fetch to display Non·Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status, and that cycle depends on the destination address.
3.4.3.3 Extending Multiply Accesses
Note: During non·sequential fetches, BEO-BE3 are all active regardless of
3.4.3.2 Bit Field Accesses
the alignment.
The Extending Multiply Instruction (MEl) will return a result
which is twice the size in bytes of the operand it reads. If the
multiplicand is in memory, the most-significant half of the
result is written first (at the higher address), then the leastsignificant half. This is done in order to support retry if this
instruction is aborted.
3.4.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is interrupt control rather
than the transfer of instructions or data. Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status pesented on pins STO-ST3. All
Interrupt Control cycles are single-byte Read cycles.
3.4.4 Instruction Fetches
Instructions for the NS32C032 CPU are "prefetched"; that
is, they are input before being needed into the next available
entry of the eight-byte Instruction Queue. The CPU performs
two types of Instruction Fetch cycles: Sequential and NonSequential. These can be distinguished from each other by
their differing status combinations on pins STO-ST3 (Sec.
3.4.2).
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine. For full details of the NS32C032 interrupt
structure, see Sec. 3.S.
2-191
~
o
Co)
N
....o•
......
Z
(J)
Co)
N
oo
.....
Co)
N
C11
.
.,...
II)
N
M
C
3.0 Functional Description
(Continued)
TABLE 3-3
Interrupt Sequences
~
M
(f)
Data Bus
Z
r
Ci
.,...
~
M
C
o
N
M
(f)
Z
Cycle
Status
Address
Interrupt Acknowledge
1
0100
FFFF0016
ODIN
\
BE3
BE2
BE1
BEO
Byte 3
Byte 2
A. Non-Maskable Interrupt Control Sequences
o
o
X
Byte 1
Byte 0
x
X
X
Interrupt Return
None: Performed through Return from Trap (RETI) instruction.
B. Non- Vectored Interrupt Control Sequences
Interrupt Acknowledge
1
0100
FFFE0016
0
Interrupt Return
1
0110
0
FFFE0016
0
X
X
X
X
0
X
X
X
X
C. Vectored Interrupt Sequences: Non-Cascaded.
Interrupt Acknowledge
1
0100
FFFE0016
0
0
X
X
X
Vector:
Range: 0-127
Interrupt Return
1
0110
0
0
X
X
X
Vector: Same as
in Previous Int.
Ack.Cycle
X
X
Cascade Index:
range -16to-1
FFFE0016
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
0100
FFFE0016
1
o
o
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
0
See Note
Address
Interrupt Return
0110
1
FFFE0016
o
X
Vector, range 9 - 255; on appropriate byte of
data bus.
o
(The CPU here uses the Cascade Index to find the Cascade Address)
2
0111
Cascade
0
See Note
Address
X
X
X
X
X
X
X
Cascade Index:
Sameasin
previous Int.
Ack.Cycle
X
= Don't Care
Note: BEO·BE3 signals will be activated according to the cascaded leu address. The cycle type can be 1, 2, 3 or 4, when reading the interrupt vector. The vector
value can be in the range 0-255.
2-192
,--------------------------------------------------------------------------, Z
3.0 Functional Description
~
I\)
(Continued)
oo
3.4.6 Slave Processor Communication
In addition to its use as the Address Translation strap (Sec.
3.5.1), the AT/SPC pin is used as the data strobe for Slave
Processor transfers. In this role, it is referred to as Slave
Processor Control (SPC). In a Slave Processor bus cycle,
data is transferred on the Data Bus (ADO-AD15), and the
status lines (STO-ST3) are monitored by each Slave Processor in order to determine the type of transfer being performed. SPC is bidirectional, but is driven by the CPU during
all Slave Processor bus cycles. See Sec. 3.9 for full protocol
sequences.
A
AD(0·15)
AT/SPC
"
"v
....o.
Co)
I\)
D«(J.15)
......
SPC
cpu
SLAVE
PROCESSOR
STO-ST3
STO-ST3
NS32CD32
Z
(/)
Co)
I\)
oo
Co)
I\)
....•
U1
TL/EE/9160-24
FIGURE 3-12. Slave Processor Connections
NEXT CYCLE
PREY. CYCLE
I
PHil
[
PHIZ
[
T40rTI
Tl
T4
TIORTI
I
m[
ITO-In [
•
_(3)[
DBE
TLlEE/9160-25
Note:
(I) CPU samples Data Bus here.
(2) DBE and all other NS32C201 TCU bus signals remain inactive because no ADS pulse is received from the CPU.
FIGURE 3-13. CPU Read from Slave Processor
2-193
....
In
c:..
3.0 Functional Description
8
3.4.6.1 Slave Processor Bus Cycles
C')
C'I
C')
C/)
z
.......
....
o
c:..
C')
o
o
C'I
C')
C/)
z
(Continued)
3.4.6.2 Slave Operand Transfer Sequences
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (ADO-AD7), and a
Word operand is transferred on bits ADO-AD15. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-significant word to most-significant.
Note that the NS32C032 uses only the two least significant
bytes of the data bus for slave cycles. This is to maintain
compatibility with existing slave processors.
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3-13 and 3-14). During a Read cycle SPC is active from the beginning of T1 to
the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock period, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1 ,
removing SPC at T4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
Since the CPU does not pulse the Address Strobe (ADS),
no bus signals are generated by the NS32C201 Timing Control Unit. The direction of a transfer is determined by the
sequence ("protocol") established by the instruction under
execution; but the CPU indicates the direction on the DDIN
pin for hardware debugging purposes.
PREV.CYCLE
I
PHil
T40RTi
NEXTCVCLE
TI
T4
TIORTi
I
[
ADO-ADI5 [
4~~.:.L'f' ' - - - t - - - - r '----t-
STO-ST3 [
ADs [
_(2)[
DBE
TL/EE/9160-26
Note:
(1) Slave Processor samples Data Bus here.
(2) DBE, being provided by the NS32C201 TCU, remains inactive due to the fact that no pulse is presented on ADS. TCU Signals RD, WR and TSO also remain
inactive.
FIGURE 3-14. CPU Write to Slave Processor
2-194
3.0 Functional Description
z
en
w
(Continued)
N
If AT /SPC is sampled as high, the bus timing is as previously described in Sec. 3.4. If it is sampled as low, two changes
occur:
3.5 MEMORY MANAGEMENT OPTION
The NS32C032 CPU. in conjunction with the NS32082
Memory Management Unit (MMU), provides full support for
address translation, memory protection, and memory allocation techniques up to and including Virtual Memory.
1) An extra clock cycle, Tmmu, is inserted into all bus cycles
except Slave Processor transfers.
2) The OS/FLT pin changes in function from a Data Strobe
output (OS) to a Float Command input (FLT).
3.5.1 Address Translation Strap
The Bus Interface Control section of the NS32C032 CPU
has two bus timing modes: With or Without Address Translation. The mode of operation is selected by the CPU by
sampling the AT/SPC (Address Translation/Slave Processor Control) pin on the rising edge of the RST (Reset) pulse.
I
PHI!
[
PHI2
[
ADO-AD23 [
T40RTI
I
T1
I
The NS32082 MMU will itself pull the CPU AT/SPC pin low
when it is reset. In non-Memory-Managed systems this pin
should be pulled up to Vee through a 10 k!1 resistor.
Note that the Address Translation strap does not specifical-
Tmmu
I
12
TJ
T4
"'I-"-L~"-L"f4 '--_...-.J.J
ADs [
STD-STJ [
DDIN
BEo-iiEi
[~~~~~£L____+-____-+____~+-____~______~~____+-
[£4<'-.£..o~ 4------+------1------4+------+---..J '-+-__4_
TLlEE/9160-27
FIGURE 3-15. Read Cycle with Address Translation (CPU Action)
2-195
oo
W
N
....
I
o
.......
z
en
w
N
oo
W
N
....
I
c..n
.
.,...
Il')
C"II
C')
C
oC"II
C')
(/)
z
......
c
.,...
N
C')
c
oC"II
C')
(/)
Z
3.0 Functional Description (Continued)
Iy declare the presence of an NS32082 MMU, but only the
presence of external address translation circuitry. MMU instructions will still trap as being undefined unless the
SETCFG (Set Configuration) instruction is executed to declare the MMU instruction set valid. See Sec. 2.1.3.
without Address Translation. Note that in order for the
NS32082 MMU to operate correctly it must be set to the
32032 mode by forcing A24/HBF low during reset. In this
mode the bus lines AD16-AD23 are floated after the MMU
address has been latched, since they are used by the CPU
to transfer data.
Figures 3-17 and 3-18 show a Read cycle and a Write cycle
as generated by the 32C032/32082/32C20t group. Note
that with the CPU ADS signal going only to the MMU, and
with the MMU PAV signal substituting for ADS everywhere
else, Tmmu through T4 look exactly like T1 through T4 in a
non-Memory-Managed system. For the connection diagram,
see Appendix B.
3.5.2 Translated Bus Timing
Figures 3-15 and 3-16 illustrate the CPU activity during a
Read cycle and a Write cycle in Address Translation mode.
The additional T-State, Tmmu, is inserted between T1 and
T2. During this time the CPU places ADO-AD23 into the
TRI-STATE® mode, allowing the MMU to assert the translated address and issue the physical address strobe PAV.
T2 through T4 of the cycle are identical to their counterparts
I
PHil
T40RTI
I
Tl
Tmmu
I
T2
T3
T4
[
PHI2
ADO-AD23
[
D24-D31
[
ADS
[
STD·5T3
[
DDIN
BEO-BE3
ROY
STATUS VALID
[
[
[
TL/EE/9160-28
FIGURE 3-16. Write Cycle with Address Translation (CPU Action)
2-196
z
3.0 Functional Description
I
PHil [
-
D24-D31
[
I
Tl
I
N
Tmmu
I
T2
I
I
T3
I
T4
nORTI
n
o
Ir-
Co)
...o
.....
N
I
~!LfLIL!LfL!L
PHI2 [
ADG-AD23 [
T40RTi
en
Co)
(Continued)
z
en
Co)
Sl JlSlJ1L-flJl Jlr-
n
o
-~EXTADDR
c.n
~ ~~ ~
VIRTUA
N
Co)
...
PHYSICAL
ADDRESS
VALID
ADDRESS_~
~ DATA/IN
VAUD
---
~ ~ @ ~~ ~
~
)
1
DATAIIN
J
--
N
I
~~~
IV
.iDs [
U
STO·ST3 [
,~ ~
?
X
STATU VALID
%~ ~ ~
BEO-BE3 [
RDY [
~
~
NEX STATUS
/
~~
VALID
~ ~ ~ ~ WI
NEXT
X
~ W%0 ~ ~
NEXT
fII
NS32C201 leU BUS SIGNALS
.- j
-j
.TSO [
-
LI
I
II
TLlEE/9160-29
FIGURE 3-17. Memory-Managed Read Cycle
2-197
LI)
.,...
•
C'I
Cf)
3.0 Functional Description
CI
I
0
C'I
Cf)
tn
Z
......
CI
.
T40RTi
(Continued)
I
T1
I
Tmmu
I
12
T3
T4
I
Tl0RTi
I
PHil [
.,...
C'I
Cf)
CI
PHI 2 [
0
C'I
Cf)
tn
Z
ADO-ADZ! [
024-031 [
Aiii[
PAV[
STOoST3 [
STATUS VALID
NEXT STATUS
iii5iN[
Ho-1Ei [
VALID
RDY [
NS32C201 TCU BUS SIGNALS
Wii[
iiBE[
Tl/EE/9160-30
FIGURE 3-18. Memory-Managed WrIte Cycle
2·198
,--------------------------------------------------------------------------, z
3.0 Functional Description
~
(Continued)
N
3.5.3 The FLT (Float) Pin
1) Sets AOO-A023. 024-031 and ODIN to the TRI-STATE
condition ("floating").
The FLT pin is used by the CPU for address translation
support. Activating FLT during Tmmu causes the CPU to
wait longer than Tmmu for address translation and valida·
tion. This feature is used occasionally by the NS320B2 MMU
in order to update its translation look·aside buffer (TLB)
from page tables in memory. or to update certain status bits
within them.
2) Suspends further internal processing of the current instruction. This ensures that the current instruction reo
mains abortable with retry. (See RST/ ABT description.
Sec. 3.5.4.)
Note that the AOO-A023 pins may be briefly asserted duro
ing the first idle T-State. The above conditions remain in
effect until FLT again goes high. See the Timing Specifica·
tions. Sec. 4.
Figure 3-19 shows the effect of FLT. Upon sampling FLT
low. late in Tmmu. the CPU enters idle T-States (Tt) during
which it:
Co)
...
~
o
......
z
en
Co)
N
oo
....
Co)
N
U1
Tf
Tf
T1
oo
Tf
T2
PHil [
PHI2
[
AOO-A023
[
024-031
[-t----t'
ADS
[
PAY
[
FLT
[
STO·ST3
•
[
ODIN
[
BEO-BE3
[
VALID
TLlEE/9160-31
FIGURE 3-19. FLTTiming
2·199
~
..-
~--------------------------------------------------------------.
~
3.0 Functional Description
C\I
The RSTI ABT pin, apart from its Reset function (Sec. 3.3),
also serves as the means to "abort", or cancel, a bus cycle
and the instruction, if any, which initiated it. An Abort request is distinguished from a Reset in that the RST I ABT pin
is held active for only one clock cycle.
8
~
Z
.....
o
..-
N
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o
U
C\I
CO)
en
z
(Continued)
2) If FLT has been applied to the CPU, the Abort pulse must
be applied before the T -State in which FLT goes inactive.
The CPU will not actually respond to the Abort command
until FLT is removed. See Figure 4-23.
3.5.4 Aborting Bus Cycles
3) The Write half of a Read-Modify-Write operand access
may not be aborted. The CPU guarantees that this will
never be necessary for Memory Management functions
by applying a special RMW status (Status Code 1011)
during the Read half of the access. When the CPU presents RMW status, that cycle must be aborted if it would
be illegal to write to any of the accessed addresses.
If RST/ABT is pulled low during Tmmu or Tf, this signals
that the cycle must be aborted. The CPU itself will enter T2
and then Ti, thereby terminating the cycle. Since it is the
MMU PAY signal which triggers a physical cycle, the rest of
the system remains unaware that a cycle was started.
If RSTI ABT is pulsed at any time other than as indicated
above, it will abort either the instruction currently under execution or the next instruction and will act as a very high-priority interrupt. However, the program that was running at the
time is not guaranteed recoverable.
The NS32082 MMU will abort a bus cycle for either of two
reasons:
1) The CPU is attempting to access a virtual address which
is not currently resident in physical memory. The referenced page must be brought into physical memory from
mass storage to make it accessible to the CPU.
3.6 BUS ACCESS CONTROL
The NS32C032 CPU has the capability of relinquishing its
access to the bus upon request from a DMA device or another CPU. This capability is implemented on the HOLD
(Hold Request) and HLDA (Hold Acknowledge) pins. By asserting HOLD low, an external device requests access to
the bus. On receipt of HLDA from the CPU, the device may
perform bus cycles, as the CPU at this point has set the
ADO-AD23, D24-D31, ADS, DDIN and BEO-BE3 pins to
the TRI-STATE condition. To return control of the bus to the
CPU, the device sets HOLD inactive, and the CPU acknowledges return of the bus by setting H LDA inactive.
2) The CPU is attempting to perform an access which is not
allowed by the protection level assigned to that page.
When a bus cycle is aborted by the MMU, the instruction
that caused it to occur is also aborted in such a manner that
it is guaranteed re-executable later. The information that is
changed irrecoverably by such a partly-executed instruction
does not affect its re-execution.
3.5.4.1 The Abort Interrupt
Upon aborting an instruction, the CPU immediately performs
an interrupt through the ABT vector in the Interrupt Table
(see Sec. 3.8). The Return Address pushed on the Interrupt
Stack is the address of the aborted instruction, so that a
Return from Trap (RETT) instruction will automatically retry
it.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-20 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-21 shows the sequence
if the CPU is using the bus at the time that the HOLD request is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T 4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T 4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
The one exception to this sequence occurs if the aborted
bus cycle was an instruction prefetch. If so, it is not yet
certain that the aborted prefetched code is to be executed.
Instead of causing an interrupt, the CPU only aborts the bus
cycle, and stops prefetching. If the information in the Instruction Queue runs out, meaning that the instruction will
actually be executed, the ABT interrupt will occur, in effect
aborting the instruction that was being fetched.
3.5.4.2 Hardware Considerations
In order to guarantee instruction retry, certain rules must be
fOllowed in applying an Abort to the CPU. These rules are
followed by the NS32082 Memory Management Unit.
In a Memory-Managed system, the HLDA signal is connected in a daisy-chain through the NS32082, so that the MMU
can release the bus if it is using it.
1) If FLT has not been applied to the CPU, the Abort pulse
must occur during or before Tmmu. See the Timing Specifications, Figure 4-22.
2-200
3.0 Functional Description
I
T,
I
T,
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(Continued)
T,
N
I··· I
T,
Ti
T,
Ti OR T4
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.......
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N
PHI2
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HOLD [
HL5A[
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AFFECTED SIGNALS
------- IT------ ------- -------
os[
----- -H·----- ----- ------
----
ODIN [
BEO-Be3 [
~r----------
-+----+---41
NEXT ADDR
STO·ST3 [
PREVIOUS
TL/EE/9160-32
FIGURE 3-20. HOLD Timing, Bus Initially Idle
2-201
.... r---------------------------------------------------------------------------------,
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c.:.
('I)
3.0 Functional Description
(Continued)
o
(.)
N
I
('I)
T20RT3
I
T3
T4
Ti
TI
TI
Ti
U)
Z
......
.....
o
N
('I)
~
PHI 2 [
('I)
U)
Z
HOLD[
HLDA[
AFFECTED SIGNALS
ADS[
os[
ODIN [
BEO-BE3[
ADO-AD23 [
VALID
NEXT
VALID
-- 1r-- ----
NEXTADDR
024-031 [
STO-ST3[
TL/EE/9160-33
FIGURE 3·21. HOLD Timing, Bus Initially Not Idle
2·202
z
3.0 Functional Description
(Continued)
In addition there is a set of internally-generated "traps"
which cause interrupt service to be performed as a result
either of exceptional conditions (e.g., attempted division by
zero) or of specific instructions whose purpose is to cause a
trap to occur (e.g., the Supervisor Call instruction).
3.7 INSTRUCTION STATUS
In addition to the four bits of Bus Cycle status (STO-ST3),
the NS32C032 CPU also presents Instruction Status information on three separate pins. These pins differ from STOST3 in that they are synchronous to the CPU's internal instruction execution section rather than to its bus interface
section.
3.8.1 GenerallnterruptlTrap Sequence
PFS (Program Flow Status) is pulsed low as each instruction
begins execution. It is intended for debugging purposes, and
is used that way by the NS32082 Memory Management
Unit.
U/S originates from the U bit of the Processor Status Register, and indicates whether the CPU is currently running in
User or Supervisor mode. It is sampled by the MMU for
mapping, protection, and debugging purposes. Although it is
not synchronous to bus cycles, there are guarantees on its
validity during any given bus cycle. See the Timing Specifications, Figure 4-21.
~
o
8N
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......
~
~
W
N
Upon receipt of an interrupt or trap request, the CPU goes
through three major steps:
1) Adjustment of Registers.
o
Depending on the source of the interrupt or trap, the CPU
may restore and/or adjust the contents of the Program
Counter (PC), the Processor Status Register (PSR) and
the currently-selected Stack Pointer (SP). A copy of the
PSR is made, and the PSR is then set to reflect Supervisor Mode and selection of the Interrupt Stack.
en
~
•
......
2) Vector Acquisition.
A Vector is either obtained from the Data Bus or is supplied by default.
3) Service Call.
ILO (Interlocked Operation) is activated during an SBITI (Set
Bit, Interlocked) or CBITI (Clear Bit, Interlocked) instruction.
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the semaphore primitive operations for multi-processor communication and resource sharing. As with the U/S pin, there are
guarantees on its validity during the operand accesses performed by the instructions. See the Timing SpeCification
Section, Figure 4-19.
The Vector is used as an index into the Interrupt Dispatch
Table, whose base address is taken from the CPU Interrupt Base (lNTBASE) Register. See Figure 3-22. A 32-bit
External Procedure Descriptor is read from the table entry, and an External Procedure Call is performed using it.
The MOD Register (16 bits) and Program Counter (32
bits) are pushed on the Interrupt Stack.
3.8 NS32C032 INTERRUPT STRUCTURE
INT, on which maskable interrupts may be requested,
NMI, on which non-maskable interrupts may be requested, and
RST/ ABT, which may be used to abort a bus cycle and
any associated instruction. See Sec. 3.5.4.
,~
MEMORY
/
CASCADE TABLE
I
I"r-o'
o~
31
0
NVI
N ON·VECTORED INTERRUPT
CASCADE ADDR 0
;~
I'''~~m''~
REGISTER
~
t
··
CASCADE ADDR 14
*
CASCADE ADDR 15
FIXED INTERRUPTS
AND TRAPS
VECTORED
INTERRUPTS
I
DISPATCH TABLE
X
1
NMI
NON·MASKABLE INTERRUPT
2
ABT
A BORT
3
SLAVE
SLAVE PROCESSOR TRAP
4
ILL
ILLEGAL OPERATION TRAP
5
SVC
S UPERVISOR CALL TRAP
6
DVZ
DIVIDE BY ZERO TRAP
7
FLG
FLAG TRAP
8
BPT
BREAKPOINTTRAP
9
TRC
T RACE TRAP
UNO
U NDEFINED INSTRUCTION TRAP
10
11·15 ~ ;::: RESERVED
16
,.'"
;"
VECTORED
INTERRUPTS
A.
TLlEE/9160-34
FIGURE 3-22. Interrupt Dispatch and Cascade Tables
2-203
II
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~
r---------------------------------------------------------------------------------,
3.0 Functional Description (Continued)
This process is illustrated in Figure 3-23, from the viewpoint of the programmer.
l
I
I (PUSH)
RETURN ADDRESS
j
32BITS
I
STATUS
I
I
I (PUSH)
MODULE
PSR
32 BITS
MOD
INTERRUPT
STACK
en
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TL/EE/9160-35
r-------------...,
I
I
I
I
CASCADE TABLE
I
I
I
INTBASE REGISTER
I
DISPATCH
TABLE
DESCRIPTOR (32 Brrs)
OESCRIPTOR
0-----16--- ._--16--0
Ii"""
0 1
1
"1""1
OFFSET
MODULE
MOD REGISTER
I
-:::r-J
0
MODULE TABLE
NEW MOOULE
I
MODULE TABLE ENTRY
J
MODULE TABLE ENTRY
32
-r-----,
STATIC BASE POINTER
UNK BASE POINTER
+
PROGRAM BASE POINTER
(RESERVED)
SBREGISTER
PROGRAM COUNTER
+-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3-23. Interrupt/Trap Service Routine Calling Sequence
2-204
I
TL/EE/9160-36
z
en
CAl
3.0 Functional Description (Continued)
N
3.8.2 Interrupt/Trap Return
The input is maskable, and is therefore enabled to generate
interrupt requests only while the Processor Status Register I
bit is set. The I bit is automatically cleared during service of
an INT, NMI or Abort request, and is restored to its original
setting upon return from the interrupt service routine via the
RETT or RETI instruction.
To return control to an interrupted program, one of two instructions is used. The RETI (Return from Trap) instruction
(Figure 3-24) restores the PSR, MOD, PC and S8 registers
to their previous contents and, since traps are often used
deliberately as a call mechanism for Supervisor Mode procedures, it also discards a specified number of bytes from
the original stack as surplus parameter space. RETI is used
to return from any trap or interrupt except the Maskable
Interrupt. For this, the RETI (Return from Interrupt) instruction is used, which also informs any external Interrupt Control Units that interrupt service has completed. Since interrupts are generally asynchronous external events, RETI
does not pop parameters. See Figure 3-25.
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I = C) or Vectored (bit I = 1).
3.8.3.1 Non-Vectored Mode
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests.
PROGRAM COUNTER
RETURN ADDRESS
STATUS
PSR
I
I
-.o1l----------~1-------------l
(POP)
j
32 BITS
(POP)
MODULE
32 BITS
MOD
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
MODULET~BLEENTRY
STATIC BASE POINTER
-
h
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
PARAMETERS
n
BYTES
SBREGISTER
STATIC BASE
+'
STACK SELECTED
IN NEWLYPOPPEDPSR.
POP AND
DISCARD
FIGURE 3-24. Return from Trap (RETT n) Instruction Flow
2-205
CAl
....~
o
......
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N
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....~
U1
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
3.8.3 Maskable Interrupts (The INT Pin)
oo
Tl/EE/9160-37
... r---------------------------------------------------------------------------------,
3.0 Functional Description
U)
~
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c;;
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(Continued)
C\I
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"END OF INTERRUPT"
BUS CYCLE
8
C\I
INTERRUPT
CONmOL
UNIT
C')
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z
PROGRAM COUNTER
(POP)
RETURN ADDRESS
STATUS
J
(POP)
MODULE
PSR
-1r---------+_
MOO
INTERRUPT
STACK
o
MODULE
TABLE
MODULE TABLE ENmy
J
MODULE TAJLE ENTRY
STATIC BASE POINTER
- ---...,
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STATlCBASE
SBREGISTER
-+-'
TL/EE/9160-39
FIGURE 3·25. Return from Interrupt (RETI) Instruction Flow
2·206
z
3.0 Functional Description (Continued)
en
N
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Figure 3-22 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32·bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
3.8.3.2 Vectored Mode: Non-Cascaded Case
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize up to 16 interrupt requests. Upon receipt of an interrupt request on the INT pin, the CPU performs an "Interrupt Acknowledge, Master" bus cycle (Sec.
3.4.2) reading a vector value from the low·order byte of the
Data Bus. This vector is then used as an index into the
Dispatch Table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI) instruction, which performs an End of Interrupt
bus cycle, informing the ICU that it may re·prioritize any interrupt requests still pending. The ICU provides the vector
number again, which the CPU uses to determine whether it
needs also to inform a Cascaded ICU (see below).
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle
(Sec. 3.4.2), reading the final vector value. This vector is
interpreted by the CPU as an unsigned byte, and can therefore be in the range of 0 through 255.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle (Sec. 3.4.2), whereupon the Master ICU again provides the negative Cascade
Table index. The CPU, seeing a negative value, uses it to
find the corresponding Cascade Address from the Cascade
Table. Applying this address, it performs an "End of Interrupt, Cascaded" bus cycle (Sec. 3.4.2), informing the Cas·
caded ICU of the completion of the service routine. The byte
read from the Cascaded ICU is discarded.
3.8.3.3 Vectored Mode: Cascaded Case
In order to allow up to 256 levels of interrupt, provision is
made both in the CPU and in the NS32202 Interrupt Control
Unit (ICU) to transparently support cascading. Figure 3-21,
shows a typical cascaded configuration. Note that the Interrupt output from a Cascaded ICU goes to an Interrupt Request input of the Master ICU, which is the only ICU which
drives the CPU INT pin.
In a system which uses cascading, two tasks must be performed upon initialization:
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number (0 to 15) on which it
receives the cascaded requests.
Note: If an interrupt must be masked off, the CPU can do so by selting the
corresponding bit in the Interrupt Mask Register of the Interrupt Con·
troller.
However, if an interrupt is set pending during the CPU instruction that
masks off that interrupt, the CPU may still perform an interrupt ac·
knowledge cycle following that instruction Since it might have sampled
the INT line before the leu deasserted it. This could cause the ICU to
provide an invalid vector. To avoid this problem the above operation
should be performed with the CPU interrupt disabled.
2) A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (lNTBASE) Register. Its entries are 32-bit addresses, pOinting
to the Vector Registers of each of up to 16 Cascaded
ICUs.
HARDWARE
INTERRUPTS
OR
CASCADED
CONTROLLERS
NS32C1l32
CPU
GROUP
INf 1------1
INTERRUPTS,
CASCADED,
OR
BrrllO
TUEE19160-40
FIGURE 3-26. Interrupt Control Unit Connections (16 Levels)
2·207
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...
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~
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....
~ .-----------------------------------------------------------------------------~
N
CO)
3.0 Functional Description
(Continued)
o
o
C'I
DATA
CO)
rn
z
~
CONTROL
N
CO)
ADDR 5 BITS
....
~rn
z
CASCADED
NS32202
ICU
HARDWARE
INTERRUPTS
STATUS
FROM
ADDRESS
DECODER
INTERRUPTS
OR
BIT 1/0
CONTROL
NS32C032
CPU
GROUP
MASTER
N&32202
ICU
ADDR
STATUS 1
TLlEE/9160-41
FIGURE 3-27. Cascaded Interrupt Control Unit Connections
3.8.4 Non-Maskable Interrupt (The NMI Pin)
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Sec. 3.4.2)
when processing of this interrupt actually begins. The Interrupt Acknowledge cycle differs from that provided for Maskable Interrupts in that the address presented is FFFF0016.
The vector value used for the Non-Maskable Interrupt is
taken as 1, regardless of the value read from the bus.
3.B.5Traps
A trap is an internally-generated interrupt request caused as
a direct and immediate result of the execution of an instruction. The Return Address pushed by any trap except Trap
(TRC) is the address of the first byte of the instruction during
which the trap occurred. Traps do not disable interrupts, as
they are not associated with external events. Traps recognized by the NS32C032 CPU are:
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Sec. 3.9.1).
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
For the full sequence of events in processing the NonMaskable Interrupt, see Sec. 3.8.7.1.
2·208
z
en
3.0 Functional Description
(Continued)
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
Trap (SVC): The Supervisor Call (SVC) instruction was executed.
1. If a String instruction was interrupted and not yet completed:
a. Clear the Processor Status Register P bit.
b. Set "Return Address" to the address of the first byte of
the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
Trap (DVZ): An attempt was made to divide an integer by
zero. (The FPU trap is used for Floating Point division by
zero.)
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
Trap (BPT): The Breakpoint (BPT) instruction was executed.
Trap (TRC): The instruction just completed is being traced.
See below.
Trap (UNO): An undefined opcode was encountered by the
CPU.
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I.
3. If the interrupt is Non-Maskable:
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a. Read a byte from address FFFF0016, applying Status
Code 0100 (Interrupt Acknowledge, Master, Sec.
3.4.2). Discard the byte read.
b. Set "Vector" to 1.
c. Go to Step B.
4. If the interrupt is Non-Vectored:
A special case is the Trace Trap (TRC), which is enabled by
setting the T bit in the Processor Status Register (PSR). At
the beginning of each instruction, the T bit is copied into the
PSR P (Trace "Pending") bit. If the P bit is set at the end of
an instruction, then the Trace Trap is activated. If any other
trap or interrupt request is made during a traced instruction,
its entire service procedure is allowed to complete before
the Trace Trap occurs. Each interrupt and trap sequence
handles the P bit for proper traCing, guaranteeing one and
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
a. Read a byte from address FFFF0016, applying Status
Code 0100 (Interrupt Acknowledge, Master: Sec.
3.4.2). Discard the byte read.
b. Set "Vector" to O.
c. Go to Step B.
5. Here the interrupt is Vectored. Read "Byte" from address
FFFE0016, applying Status Code 0100 (Interrupt Acknowledge, Master: Sec. 3.4.2).
6. If "Byte" :2: 0, then set "Vector" to "Byte" and go to Step
B.
3.8.6 Prioritization
The NS32016 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
(Highest.priority)
2) Abort
7. If "Byte" is in the range -16 through -1, then the interrupt source is Cascaded. (More negative values are reserved for future use.) Perform the following:
a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE +4' Byte.
b. Read "Vector," applying the Cascade Address just
read and Status Code 0101 (Interrupt Acknowledge,
Cascaded: Sec. 3.4.2).
8. Push the PSR copy (from Step 2) onto the Interrupt Stack
as a 16-bit value.
3) Non-Maskable Interrupt
4) Maskable Interrupts
5) Trace Trap
~
g
(Lowest priority)
3.8.7InterruptlTrap Sequences: Detailed Flow
For purposes of the following detailed discussion of interrupt and trap service sequences, a single sequence called
"Service" is defined in Figure 3-28. Upon detecting any interrupt request or trap condition, the CPU first performs a
sequence dependent upon the type of interrupt or trap. This
sequence will include pushing the Processor Status Register and establishing a Vector and a Return Address. The
CPU then performs the Service sequence.
9. Perform Service (Vector, Return Address), Figure 3-28.
Service (Vector, Return Address):
1) Read the 32-blt Externat Procedure Descriptor from the tnterrupt
Dispatch Table: address Is Vector' 4 + INTBASE Register contents.
2) Move the Module field of the Descriptor into the MOD Register.
3) Read the new Static Base pOinter from the memory address contained in MOD, placing it Into the SB Register.
4) Read the Program Base pOinter from memory address MOD + 8,
and add to it the Offset field from the Descriptor, placing the result
In the Program Counter.
For the sequence followed in processing either Maskable or
Non-Maskable interrupts (on the INT or NMI pins, respectively), see Sec. 3.B. 7.1 For Abort Interrupts, see Sec.
3.B.7.4. For the Trace Trap, see Sec. 3.8.7.3, and for all
other traps see Sec. 3.B. 7.2.
5) Flush queue: Non-sequentially fetch first Instruction of Interrupt
routine.
6) Push MOD Register Into the Interrupt Stack as a 16-blt value. (The
PSR has already been pushed as a 16-blt value.)
3.8.7.1 Maskable/Non·Maskable Interrupt Sequence
7) Push the Return Address onto the Interrupt Stack as a 32-blt quantity.
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, at the next interruptible point during its execution.
FIGURE 3·28. Service Sequence
Invoked during all interrupt/trap sequences.
2-209
PI
3.0 Functional Description
(Continued)
Each Slave Instruction Set is validated by a bit in the Configuration Register (Sec. 2.1.3). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
3.8.7.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector" to the value corresponding to the trap type.
SLAVE:
Vector = 3.
ILL:
Vector = 4.
SVC:
DVZ:
Vector = 5.
Vector = 6.
FLG:
BPT:
UNO:
Vector = 7.
Vector = 8.
Vector = 10.
3.9.1 Slave Processor Protocol
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an 10 Byte followed by an Operation Word. The 10 Byte has three functions:
1) It identifies the instruction as being a Slave Processor instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word of the instruction.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-29. While applying
Status Code 1111 (Broadcast 10, Sec. 3.4.2), the CPU
transfers the 10 Byte on the least-significant byte of the
Data Bus (ADO-AD7). All Slave Processors input this byte
and decode it. The Slave Processor selected by the 10 Byte
is activated, and from this point the CPU is communicating
only with it. If any other slave protocol was in progress (e.g.,
an aborted Slave instruction), this transfer cancels it.
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Sec. 3.4.2).
Upon receiving it, the Slave Processor decodes it, and at
this point both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The operation Word is swapped on the Data Bus, that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD7.
3) Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, P and T.
4) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
5) Set "Retum Address" to the address of the first byte of
the trapped instruction.
6) Perform Service (Vector, Return Address), Figure 3-28.
3.8.7.3 Trace Trap Sequence
1) In the Processor Status Register (PSR), clear the P bit.
2) Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
3) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
4) Set "Vector" to 9~
5) Set "Return Address" to the address of the next instruc-
tion.
6) Perform Service (Vector, Return Address), Agure 3-28.
Using the Address Mode fields within the Operation Word,
the CPU starts fetching operand and issuing them to the
Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
3.8.7.4 Abort Sequence
1) Restore the currently selected Stack Pointer to its original
contents at the beginning of the aborted instruction.
2) Clear the PSR P bit.
3) Copy the PSR into a temporary register, then clear PSR
bits S, U, T and I.
Slatus Combinations:
4) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
Send 10 (10): Code 1111
5) Set "Vector" to 2.
6) Set "Return Address" to the address of the first byte of
the aborted Instruction.
7) Perform Service (Vector, Return Address), Figure 3-28.
Read Status (ST): Code 1110
Xler Operand (OP): Code 1101
3.9 SLAVE PROCESSOR INSTRUCTIONS
The NS32C032 CPU recognizes three groups of instructions
being executable by external Slave Processor:
Floating Point Instruction Set
Memory ManagemEmt Instruction Set
Custom Instruction Set
Step
Status
1
10
CPU Send 10 Byte.
Action
2
OP
CPU Sends Operaten Word.
3
OP
CPY Sends Required Operands
Slave Starts Execution. CPU Pre·fetches.
4
Slave Pulses SPe Low.
6
7
ST
CPU Reads Status Word. (Trap? Alter Flags?)
OP
CPU Reads Results (If Any).
FIGURE 3-29. Slave Processor Protocol
2-210
z
3.0 Functional Description
en
Co)
(Continued)
I\)
for memory accesses, these extensions are not sent to the
Slave processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Sec. 3.4.2).
An exception to the protocol above is the LMR (Load Memory Management Register) instruction, and a corresponding
Custom Slave instruction (LCR: Load Custom Register). In
executing these instructions. the protocol ends after the
CPU has issued the last operand. The CPU does not wait for
an acknowledgement from the Slave Processor, and it does
not read status.
After the CPU has issued the last operand, the Slave Processor starts the actual execution of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low. To
allow for this, and for the Address Translation strap function, AT ISPC is normally held high only by an internal pullup device of approximately 5 kfl..
3.9.2 Floating Point Instructions
Table 3-4 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction. see
Appendix A.
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave, Sec.
3.4.2).
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Instruction Set Reference Manual).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status, Sec. 3.4.2). This
word has the format shown in Figure 3-30. If the Q bit
("Quit", Bit 0) is set, this indicates that an error was detected by the Slave Processor. The CPU will not continue the
protocol, but will immediately trap through the Slave vector
in the Interrupt Table. Certain Slave Processor instructions
cause CPU PSR bits to be loaded from the Status Word.
The Operand Issued columns show the sizes of the operands issued to the Floating Point Unit by the CPU. "0" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word. 0 = Double Word). "f" indicates that the instruction
specifies a Floating Point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-30).
The last step in the protocol is for the CPU to read a result,
if any. and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand. Sec.
3.4.2).
TABLE 3-4
Mnemonic
Operand 1
Class
Floating Point Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
PSR Bits
Affected
none
none
none
none
ADDf
SUB!
MUU
DIV!
read.!
read.!
read.f
read.f
rmw.!
rmw.f
rmw.f
rmw.f
!
Ito Op. 2
ftoOp.2
ftoOp.2
!toOp.2
MOVf
ABS!
NEGf
read.!
read.f
read.!
write.!
write.!
write.!
N/A
N/A
N/A
ftoOp.2
ftoOp.2
ftoOp.2
none
none
none
CMP!
read.!
read.!
N/A
N,Z,L
FLOOR!i
TRUNC!i
ROUND!i
read.!
read.f
read.f
write.i
write.i
write.i
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
none
none
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
N/A
N/A
LtoOp.2
FtoOp.2
none
none
MOVif
read.i
write.!
N/A
Ito Op. 2
none
LFSR
SFSR
read.D
N/A
N/A
write.D
0
N/A
N/A
N/A
N/A
Dto Op. 2
none
none
Note:
o = Double Word
I = Integer size (B,W,D) specified in mnemonic.
f = Floating Point type (F,L) specified in mnemonic.
NtA
Returned Value
Type and Dest.
= Not Applicable to this instruction.
2-211
o
o
.
Co)
I\)
.....
o
......
z
en
oo
Co)
I\)
Co)
I\)
.....•
c.n
.... r-----------------------------------------------------------------------------,
~
N
CO)
3.0 Functional Description
i
15
l
z
......
CI
....
N
~
~
~
(Continued)
3.9.3 Memory Management Instructions
Table 3-5 gives the protocols for Memory Management instructions. Encodings for these instructions may be found in
Appendix A.
In executing the RDVAL and WRVAL instructions, the CPU
calculates and issues the 32-bit Effective Address of the
single operand. The CPU then performs a single-byte Read
cycle from that address, allowing the MMU to safely abort
the instruction if the necessary information is not currently in
physical memory. Upon seeing the memory cycle complete,
the MMU continues the protocol, and returns the validation
result in the F bit of the Slave Status Word.
The size of a Memory Management operand is always a 32bit Double Word. For further details of the Memory Management Instruction set, see the Instruction Set Reference
Manual and the NS32082 MMU Data Sheet.
87
00000000
IN Z F 0 0 L 0 01
New PSR BII V.lue«.)~
-"Oull": Termlnlle Protocol. Trap(FPU). /
I
TL/EE/9160-42
FIGURE 3·30. Slave Processor Status Word Format
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
Mnemonic
RDVAL'
WRVAL'
LMR'
SMR'
Operand 1
Class
addr
addr
read.D
write.D
TABLE 3·5
Memory Management Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
N/A
N/A
N/A
N/A
0
0
0
N/A
N/A
N/A
N/A
N/A
Returned Value
Type and Dest.
PSR Bits
Affected
N/A
N/A
N/A
F
F
DtoOp.1
none
none
Note:
In the RDVAL and WRVAL instructions, the CPU issues the address as a Double Word, and perfonns a single.byte Read cycle from that memory address. For
details, see the Instruction Set Reference Manual and the NS32082 Memory Management Unit Data Sheel
o-
Double Word
• - Privileged Instruction: will trap if CPU is in User Mode.
NIA - Not Applicable to this instruction.
2-212
z
3.0 Functional Description
en
Co)
(Continued)
N
3.9.4 Custom Slave Instructions
Table 3-5 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
operand which can be a 32-bit ("0") or 54-bit ("Q") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type "c" will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
For the instruction encodings, see Appendix A.
Provided in the NS32C032 is the capability of communicating with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats. the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
o
C
Co)
N
•
....
c
.......
z
en
Co)
N
o
C
Co)
....~
U'I
TABLE 3-6
Mnemonic
Operand 1
Class
Custom Slave Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
read.c
read.c
read.c
read.c
rmw.c
rmw.c
rmw.c
rmw.c
c
c
c
c
c
c
c
c
ctoOp.2
ctoOp.2
cto Op. 2
ctoOp.2
none
none
none
none
CMOVOc
CMOV1c
CMOV2c
CMOV3c
read.c
read.c
read.c
read.c
write.c
write.c
write.c
write.c
c
c
c
c
N/A
N/A
N/A
N/A
cto Op. 2
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
none
CCMPOc
CCMP1c
read.c
read.c
read.c
read.c
c
c
c
c
N/A
N/A
N,Z,L
N,Z,L
CCVOci
CCV1ci
CCV2ci
CCV3ic
read.c
read.c
read.c
read.i
write.i
write.i
write.i
write.c
c
c
c
itoOp.2
ito Op. 2
itoOp.2
ctoOp.2
none
none
none
none
CCV40Q
CCV5QO
read. 0
read.Q
write.Q
write.O
0
Q
QtoOp.2
OtoOp.2
none
none
LCSR
SCSR
read.O
N/A
0
N/A
N/A
write.D
N/A
none
none
addr
addr
N/A
N/A
N/A
N/A
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LCR*
SCR*
read.O
write.O
0
N/A
Note:
Double Word
i = Integer size (B,W,D) specified in mnemonic.
c
~
PSRBlts
Affected
CCALOc
CCAL1c
CCAL2c
CCAL3c
CATSTO*
CATST1*
o~
Returned Value
Type and Dest.
Custom siza (0:32 bits or Q:64 bits) spacified in mnamonic.
• = Privileged instruction: will trap if CPU is in User Mode.
NI A ~ Not Applicable to this instruction.
2-213
OtoOP.2
N/A
N/A
N/A
OtoOp.1
F
F
none
none
fII
.... r---------------------------------------------------------------------------------,
U)
N
C')
o
~en
z
.....
o
....
N
C')
o
~
C')
U)
Z
4.0 Device Specifications
Byte Enable (BEO-BE3): Active low. Four control signals
enabling data transfers on individual bus bytes. Sec. 3.4.3.
Status (STO-ST3): Bus cycle status code, STO least significant. Sec. 3.4.2. Encodings are:
4.1 NS32C032 PIN DESCRIPTIONS
The following is a brief description of all NS32C032 pins.
The descriptions reference portions of the Functional DesCription. Sec. 3 .
Unless otherwise indicated reserved pins should be left
open.
0000 - Idle: CPU Inactive on Bus.
0001 - Idle: WAIT Instruction.
0010 - (Reserved).
0011 - Idle: Waiting for Slave.
0100 -Interrupt Acknowledge, Master.
0101 -Interrupt Acknowledge, Cascaded.
0110 - End of Interrupt, Master.
0111 - End of Interrupt, Cascaded.
1000 - Sequential Instruction Fetch.
1001 - Non-Sequential Instruction Fetch.
1010 - Data Transfer.
1011 - Read Read-Modify-Write Operand.
1100 - Read for Effective Address.
1101 - Transfer Slave Operand.
1110 - Read Slave Status Word.
1111 - Broadcast Slave 10.
4.1.1 Supplies
Logic Power (VCCL1, 2): +5V positive supply.
Buffers Power (VCCB1, 2): + 5V positive supply.
Logic Ground (GNDL 1, GNDL2): Ground reference for onchip logic.
Buffer Grounds (GNDB1, GNOB2, GNOB3): Ground references for on-chip drivers.
4.1.2 Input Signals
Clocks (PHI1, PHI2): Two-phase clocking signals. Sec. 3.2.
Ready (ROY): Active high. While ROY is inactive, the CPU
extends the current bus cycle to provide for a slower memory or peripheral reference. Upon detecting ROY active, the
CPU terminates the bus cycle. Sec. 3.4.1.
Hold Request (HOLD): Active low. Causes the CPU to release the bus for DMA or multiprocessing purposes. Sec.
3.6.
Hold Acknowledge (HLOA): Active low. Applied by the
CPU in response to HOLD input, indicating that the bus has
been released for DMA or multiprocessing purposes. Sec.
3.6.
User/Supervisor (U/S): User or Supervisor Mode status.
Sec. 3.7. High state indicates User Mode, low indicates Supervisor Mode. Sec. 3.7.
Nole 1: FiQi]j must not be asserted until HLDA from a previous
FfOi])IHLDA sequence is deasserted.
Nole 2: If the FfOi]) signal is generated asynchronously, it's set up and hold
times may be violated.
In this case it is recommended to synchronize it with CTTL to minimize the possibility of metastable states.
Interlocked Operation (ILO): Active low. Indicates that an
interlocked instruction is being executed. Sec. 3.7.
Program Flow Status (PFS): Active low. Pulse indicates
beginning of an instruction execution. Sec. 3.7.
The CPU provides only one synchronization stage to minimize the
R05A latency. This is to avoid speed degradations in cases of
heavy FfOi]) activity (i.e., DMA controller cycles interleaved with
CPU cycles.)
Interrupt (I NT): Active low. Maskable Interrupt request.
Sec. 3.8.
4.1.4 Input-Output Signals
Address/Data 0-23 (AOO-A023): Multiplexed Addressl
Data information. Bit 0 is the least significant bit of each.
Sec. 3.4.
Data Bits 24-31 (024-031): The high order 8 bits of the
data bus.
Address Translation/Slave Processor Control (AT/
SPC): Active low. Used by the CPU as the data strobe output for Slave Processor transfers; used by Slave Processors to acknowledge completion of a slave instruction.
Sec. 3.4.6; Sec. 3.9. Sampled on the riSing edge of Reset
pulse as Address Translation Strap. Sec. 3.5.1.
In non-memory-managed systems, this pin should be
pulled-up to Vee through a 10 kO resistor.
Data Strobe/Float (OS/FLT): Active low. Data Strobe output, Sec. 3.4, or Float Command input, Sec. 3.5.3. Pin function is selected on AT/SPC pin, Sec. 3.5.1.
Non-Maskable Interrupt (NMI): Active low. Non-Maskable
Interrupt request. Sec. 3.8.
Reset/Abort (RST/ABT): Active low. If held active for one
clock cycle and released, this pin causes an Abort Command, Sec. 3.5.4. If held longer, it initiates a Reset. Sec. 3.3.
4.1.3 Output Signals
Address Strobe (ADS): Active low. Controls address latches: indicates start of a bus cycle. Sec. 3.4.
Data Direction In (ODIN): Active low. Status signal indicating direction of data transfer during a bus cycle. Sec. 3.4.
2-214
Z
tn
w
4.0 Device Specifications (Continued)
N
All Input or Output Voltages with
Respect to GND
Power Dissipation
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O'C to + 70'C
Storage Temperature
-65'C to + 150'C
n
-0.5Vto +7V
1.5 Watt
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
VIH
Parameter
Conditions
Max
Units
Vee +0.5
V
V
Vil
Low Level Input Voltage
-0.5
0.8
VeH
High Level Clock Voltage
PHI1, PHI2 pins only
0.85 Vee
Vee +0.5
V
Vel
Low Level Clock Voltage
PHI1, PHI2 pins only
-0.5
0.10 Vee
V
VeRT
Clock Input
Ringing Tolerance
PHI1, PHI2 pins only
-0.5
0.6
V
VOH
High Level Output Voltage
IOH = -400/LA
VOL
Low Level Output Voltage
IOl = 2mA
IllS
AT ISPC Input Current (low)
VIN = O.4V, AT ISPC in input mode
II
Input Load Current
o ,,; VIN ,,; Vee, All inputs except
Il
Leakage Current
Output and I/O Pins in
TRI-STATElinput Mode
0.4 ,,; VOUT ,,; Vee
Active Supply Current
lOUT = 0, TA = 25'C
Icc
VCC82
0.10 Vee
V
0.05
1.0
mA
-20
20
/LA
-20
20
/LA
100
mA
70
gsUUUUUUUUUUUUUUUl!l~
:5
GNDL2
:::J
PHil
::J
::J
PHI2
V
0.85 Vee
~
C
iiiiiii::J
VCCl2 ::J
NS32C032
iDs :::II
CPU
C
C
C
C
C
AD22
AD21
ADZU
AD19
AD18
AD17
AU16
AD15
ADI.
U/i :II
RESERVED ::.
C
AD13
C
AD12
RE~IIV!!! ::.
C ADll
~E::
=5p
RST/AIl
RESERVED
THR::U::E: !~~~c:s~~~
I:J
C
~1I1 n n n n n n n n n n n n n n n 1iI~
AD10
AD9
ADa
AD7
AD6
TL/EE/9160-2
Bottom View
FIGURE 4-1. NS32C032 Connection Diagram
Order Number NS32C032-10E, NS32C032-15E,
NS32C032-10Vor NS32C032-15V
See NS Package Number E6SB or V6SA
2-215
N
n
o
.....
2.0
PHI1, PHI2, AT/SPC
Z
tn
w
~
Typ
Min
High Level Input Voltage
.....
o
.....
w
4.3 ELECTRICAL CHARACTERISTICS TA = 0' to + 70'C, Vee = 5V ± 5%, GND = OV
Symbol
e~
en
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
ABBREVIATIONS:
4.4.1 Definitions
L.E. -
leading edge
R.E. -
rising edge
All the timing specifications given in this section refer to
2.OV on the rising or falling edges of the clock phases PHI1
and PHI2; to 15% or 85% of Vee on all the CMOS output
signals, and to 0.8V or 2.OV on all the TTL input signals as
illustrated in Figures 4-2 and 4-3 unless specifically stated
otherwise.
T.E. -
trailing edge
F.E. -
falling edge
PHln
SIG1
[-
-
[
SIG1
[
2.0V
O.BV "
-------_.
t SlG1I
I
2.0V
2.0V
SIG2 [
[
SIG2 [
PHln
lslGll
-
tSIG2h
/i
lslG2h
------------.-
TLlEEI9160-44
• "--0715V;c·
FIGURE 4-3. Timing Specification Standard
(TTL Input Signals)
-±~~5!£c________ •
TLlEE19160-43
FIGURE 4-2. Timing Specification Standard
(CMOS Output Signals)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C032-10, NS32C032-15
Maximum times assume capacitive loading of 100 pF.
Name
Figure
Description
Reference/Conditions
NS32C032-10
NS32C032-15
Min
Min
Max
tALY
4-4
Address bits 0-23 valid
after R.E., PHI1 T1
tALh
4-4
Address bits 0-23 hold
after R.E., PHI1 Tmmu or T2
toy
4-4
Data valid (write cycle)
after R.E., PHI1 T2
tDh
4-4
Data hold (write cycle)
afterR.E., PHI1 nextT1 orTi
0
0
ns
tALADSs
4-5
Address bits 0-23 setup
before ADS T.E.
25
20
ns
tALADSh
4-10
Address bits 0-23 hold
after ADS T.E.
15
tALI
4-5
Address bits 0-23
floating (no MMU)
after R.E., PHI1 T2
25
20
ns
tADf
4-5
Data bits 024-031
floating (no MMU)
after R.E., PHI1 T2
25
20
ns
tALMf
4·9
Address bits 0-23
floating (with MMU)
after R.E., PHI1 Tmmu
25
20
ns
tADMf
4·9
Data bits 21-31
floating (with MMU)
after R.E., PHI1 Tmmu
25
20
ns
tBEY
4-4
BEn signals valid
after R.E., PHI2 T4
60
45
ns
tSEh
4-4
BEn signals hold
after R.E., PHI2 T4 orTi
tSTy
4-4
Status (STO-ST3) valid
after R.E., PHI1 T4
(before T1, see note)
35
ns
tSTh
4-4
Status (STO-ST3) hold
after R.E., PHI1 T4 (after T1)
2-216
40
Units
Max
5
35
5
50
35
10
0
0
0
ns
ns
0
45
ns
ns
ns
ns
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C032-8, NS32C032-10 (Continued)
Name
Figure
Reference!
Conditions
Description
NS32C032-10
Min
Max
NS32C032-15
Min
50
Units
Max
tOOINv
4-5
ODIN signal valid
after R.E., PHI1 T1
tOOINh
4-5
ODIN signal hold
after R.E., PHI1 next T1 or Ti
tAOSa
4-4
ADS signal active (low)
after RE., PHI1 T1
35
26
tAOSia
4-4
ADS signal inactive
after R.E., PHI2 T1
40
30
tAOSw
4-4
ADS pulse width
at 15% Vcc (both edges)
tOSa
4-4
OS signal active (low)
after RE., PHI1 T2
40
30
ns
35
0
0
30
ns
ns
25
ns
ns
ns
tOSia
4-4
OS signal inactive
after RE., PHI1 T4
40
30
ns
tALI
4-6
ADO-AD23 floating
(caused by HOLD)
after RE., PHI1 T1
25
20
ns
tAO!
4-6
024-031 floating
(caused by HOLD)
after R.E., PHI1 T1
25
20
ns
toS!
4-6
OS floating
(caused by HOLD)
after R.E., PHI1 Ti
50
40
ns
tAOS!
4-6
ADS floating
(caused by HOLD)
after RE., PHI1 Ti
50
40
ns
tBE!
4-6
BEn floating
(caused by HOLD)
after RE., PHI1 Ti
50
40
ns
tOOIN!
4-6
ODIN floating
(caused by HOLD)
after RE., PHI1 Ti
50
40
ns
tHLOAa
4-6
HLDA signal active (low)
after R.E., PHI1 Ti
30
25
ns
ns
tHLOAia
4-8
HLDA signal inactive
after RE., PHI1 Ti
40
30
tOSr
4-8
OS signal returns from
floating (caused by HOLD)
after RE., PHI1 Ti
55
40
ns
tAOSr
4-8
ADS signal returns from
floating (caused by HOLD)
after R.E., PHI1 Ti
55
40
ns
tBEr
4-8
BEn signals return from
floating (caused by HOLD)
after R.E., PHI1 Ti
55
40
ns
tOOINr
4-8
ODIN signal returns from
floating (caused by HOLD)
after RE., PHI1 Ti
55
40
ns
tOOIN!
4-9
ODIN signal floating
(caused by FL
after FLT F.E.
55
50
ns
tOOINr
4-10
ODIN signal returns from
floating (caused by FL
after FLT RE.
40
30
ns
tspca
4-13
SPC output active (low)
after R.E., PHI1 T1
35
26
ns
tSPCia
4-13
SPC output inactive
after R.E., PHI1 T4
35
26
ns
n
n
tSPCn!
4-15
SPC output nonforcing
after R.E., PHI2 T4
30
25
ns
tov
4-13
Data valid (slave processor
write)
after R.E., PHI1 T1
50
35
ns
tOh
4-13
Data hold (slave processor
write)
after RE., PHI1
nextT10rTi
0
0
ns
tPFSw
4-18
PFS pulse width
at 15% VCC (both edges)
50
40
ns
2-217
fII
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C032-10, NS32C032-15 (Continued)
Name
Figure
Reference/
Conditions
Description
NS32C032-10
Max
Min
NS32C032-15
Min
Units
Max
tPFSa
4-18
PFS pulse active (low)
after R.E., PHI2
40
35
ns
tPFSia
4-18
PFS pulse inactive
after R.E., PHI2
40
35
ns
tlLOs
4-20a
ILO signal setup
before R.E., PHI1 T1
of first interlocked
read cycle
50
35
ns
tlLOh
4-20b
ILO Signal hold
after R.E., PHI1 T3
of last interlocked
write cycle
10
7
ns
tlLOa
4-21
j[(j Signal active (low)
after R.E., PHI1
35
30
ns
tlLOia
4-21
ILO Signal inactive
after R.E., PHI1
35
30
ns
tusv
4-22
U/S Signal valid
after R.E., PHI1 T4
35
30
tUSh
4-22
U/S signal hold
after R.E., PHI1 T4
8
6
ns
tNSPF
4-19b
Nonsequential fetch to
next PFS clock cycle
after R.E., PHI1 T1
4
4
tcp
tpFNS
4-19a
PFS clock cycle to next
non-sequential fetch
before R.E., PHI1 T1
4
4
tcp
ns
Last operand transfer
0
0
before R.E., PHI1 T1 of first
tcp
of an instruction to next
of first bus
PFS clock cycle
cycle of transfer
Note: Every memory cycle starts with T4, during which Cycle Status is applied. If the CPU was idling, the sequence will be: ..... Ti, T4, T1 ... ". If the CPU wes not
Idling, the sequence will be:" ... T4, T1 ... ".
tLXPF
4-29
4.4.2.2 Input Signal Requirements: NS32C032-10, NS32C032-15
Name
Figure
Description
Reference/Conditions
NS32C032-10
NS32C032-15
Min
Min
Max
Units
Max
tPWR
4-25
Power stable to
RSTR.E.
after Vcc reaches 4.5V
50
50
}Jos
tOls
4-5
Data in setup
(read cycle)
before F.E., PHI2 T3
15
10
ns
tOlh
4-5
Data in hold
(read cycle)
after R.E., PHI1 T4
3
3
ns
tHLDa
4-6
HOLD active (low) setup
time (see note)
before F.E., PHI2 TX1
25
17
ns
tHLDia
4-8
HOLD inactive setup
time
before F.E., PHI2 Ti
25
17
ns
tHLDh
4-6
HOLD hold time
after R.E., PHI1 TX2
0
0
ns
tFLTa
4-9
FLT active (low)
setup time
before F.E., PHI2 Tmmu
25
17
ns
tFLTia
4-10
FLT inactive setup
time
before F.E., PHI2 T2
25
17
ns
tRDYs
4-11,4-12
ROY setup time
before F.E., PHI2 T2 or T3
15
10
ns
tRDYh
4-11,4-12
ROY hold time
after F.E., PHI1 T3
5
5
ns
tABTs
4-23
ABT setup time
(FLT inactive)
before F.E., PHI2 Tmmu
20
13
ns
tABTs
4-24
ABT setup time
(FLTaclive)
before F.E., PHI2 T,
20
13
ns
tABTh
4-23
ABT hold time
after R.E., PHI1
0
0
ns
2-218
z
(J)
4.0 Device Specifications (Continued)
Co)
I\)
oo
4.4.2.2 Input Signal Requirements NS32C032·10, NS32C032·15 (Continued)
Co)
Name
Figure
Referencel
Conditions
Description
NS32C032·10
NS32C032·15
Min
Min
Max
Units
Max
tRSTs
4-25,4-26
tRSTw
4-26
RST pulse width
at 0.8V (both edges)
64
64
tcp
tiNTs
4-27
INT setup time
before F.E., PHil
20
15
ns
tNMlw
4-28
NMI pulse width
at O.8V (both edges)
70
70
ns
tOls
4-14
Data setup (slave
read cycle)
before F.E., PHI2 T1
15
10
ns
tOlh
4-14
Data hold (slave
read cycle)
after R.E., PHI1 T4
3
3
ns
tSPcd
4-15
SPC pulse delay from
slave
after R.E., PHI2 T4
30
25
ns
RST setup time
before F.E., PHil
10
8
ns
tspcs
4-15
SPC setup time
before F.E., PHI1
30
25
ns
tspCw
4-15
SPC pulse width from
slave processor
(async input)
at 0.8V (both edges)
25
20
ns
tATs
4-16
AT ISPC setup for address translation strap
before R.E., PHI1 of cycle
during which RST
pulse is removed
1
1
tcp
tATh
4-16
AT ISPC hold for address translation strap
after F.E., PHI1 of cycle
during which RST
pulse is removed
2
2
tcp
~
.....
o
.......
Z
(J)
Co)
I\)
oo
Co)
I\)
.....
U1
I
Note: This setup time is necessary to ensure prompt acknowledgement via HLDA and the ensuing floating of CPU off the buses. Note that the time from the receipt
of the HOLD signal unlilthe CPU floats is a funcUon of the time HOLD signal goes low, the state of the ROY input (in MMU systems), and the length of the current
MMU cycle.
4.4.2.3 Clocking Requirements: NS32C032·10, and NS32C032·15
Name
Figure
Description
Referencel
Conditions
NS32C032·10
NS32C032·15
Min
Max
Min
Max
100
250
66
250
Units
tcp
4-17
Clock Period
R.E., PHI1, PHI2
to next
R.E., PHI1, PHI2
tCLw(1,2)
4-17
PHI1, PHI2
Pulse Width
At 2.0V on PHI1,
PHI2 (Both Edges)
0.5tcp
-10ns
0.5 tcp
-6ns
tCLh(l,2)
4-17
PHI1, PHI2 High Time
At 90% Vccon
PHI1, PHI2
O.5tCp
-15ns
0.5 tcp
-10 ns
tcLl(1,2)
4-17
PHI1. PHI2 Low Time
At15% Vccon
PHI1. PHI2
0.5 tcp
-6ns
0. 5tcp
-5ns
tnOVL(l,2)
4-17
Non-Overlap Time
At15% Vcc
on PHI1. PHI2
-2
2
-2
2
ns
Non-Overlap Asymmetry
At15% Vcc
on PHI1. PHI2
-3
3
-3
3
ns
At2.0V
on PHI1. PHI2
-5
5'
-3
3
ns
tnOVLas
(tnOVlJl) -tnOVL(2»
tCLwas
PHI1. PHI2 Asymmetry
(tCLw(l) - tCLw(2»
2-219
ns
ns
fI
....
U) r-------------------------------------------------------------------------------------~
~
4.0 Device Specifications
~
4.4.3 Timing Diagrams
a
&J
z
Ci
....
T4 OR TI
~
CO)
o
~en
z
T1
I
PHil [
PHI2 [
ADO-AD23 [
n
1lb1Jl:
K'
ADDRESS
I
-,
T2
I
I
-
T3
IL -
IlX
)
DATA OUT
-IDy
tDli
)
DATA OUT
II~AD~W
tADS.
~
IIEh
W
r---< ~
tSTv
VALID
I
-1 IIEV
iiiiiN[
-
T4
~!P
X J
X
t-: IADSls
D24-D31 [
B'EO-m[
I
(HIGH)
VALID
STO-3 [
tSTh
N
IDSS
k-D Cl
NEXT
/
~
'f-IDSls
(HIGH)
I
I
TLlEE/9160-45
FIGURE 4-4. Write Cycle
T4 OR TI
PHil [
I
I
-,
T2
T1
roo-
I
T3
X
ADDRESS
D24-D31 [
X
ADDRESS
Ao§[
,I
)ro'
------
~, ------
T4
i--
PHIZ [
ADo-AD23 [
I
~
~
JL -
__ -( OATAIN
---(
t::l:
t-!Dlh
DAT~IN
--lAD!
ALADSa
BEo-iiEi [
DiiiN[
VALID
/
~
loolNv
---lIDOINh
VALID
ST0-3 [
iiS[
NE:IA~~~LE
'\.
ROY [
(HIGH)
TLlEE/9160-46
FIGURE 4-5. Read Cycle
2-220
r--------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
TXl
TX2
Z
(J)
W
N
Ti
T4
Ti
n
«:)
.
w
Ti
N
....
PHil [
~
Z
-+_---'
PHI2 [
(J)
W
N
n
«:)
HOLO[
H_LOA
[-t____+ ____+ ____
'DSF
'ADSI
OS
w
!-_~IHLOAa
N
•
....
en
'--1-----+----
tDDINf
TL/EE/9160-47
FIGURE 4·6. Floating by HOLD Timing (CPU Not Idle Initially).
Note that whenever the CPU is not idling (not in Ti). the HOLD request (HOLD low) must be active tHLDa before the falling edge
of PHI2 of the clock cycle that appears two clock cycles before T4 (TX1) and stay low until tHLDh after the rising edge of PHI1 of
the clock cycle that precedes T4 (TX2) for the request to be acknowledged.
PHil [
PHil [
PHI2 [
PHI2
[_+-.......
HLDA
[-+---+----1-'
HOLD [
HLDA [
os.
tDSf
tADsf
_ +_ _ _+-_ _-+""'ltDDINf
ADS. [
DDIN - + - - - + - - - - + . . J · tSEf
OS.
-----.---
BrO-an [ • - -
BEo-an [ - + - - - t - - - - + . . J
ADO-AD23 [ . - -
D24-D31 [ . - -
( FLOATING)
-- - - - -
-- - - --
(HIGH)
ADS. [ . - DDIN
(FLOATING)
(FLOATING)
ADO-AD23
D24-D31
[.--~ - - - - --
I
t------ ~(FLOATiNG
i
I
TL/EE/9160-49
'( FLOATiNGi
FIGURE 4·8. Release from HOLD
TLlEE/9160-48
FIGURE 4·7. Floating by HOLD Timing (CPU Initially idle)
Note that during Ti1 the CPU is already idling.
2-221
•
.... r---------------------------------------------------------------------------------,
~
c.:.
8
N
~
Z
.....
....o
c.:.
C')
o
o
N
C')
(/)
z
4.0 Device Specifications (Continued)
CPU STATES
T1
MMUSTATES [
11
TMMU
Tt
Tt
PHil
PHI2 [
m[
ADO-AD23 [
(CPU)
D24-D31 [
(CPU)
ADS [
(CPU)
PAV [
(MMU)
iiiiiN[
BEO-iiii [
TUEE/9160-50
FIGURE 4-9. FLT Initiated Float Cycle Timing
T2
Tf
CPU STATES
T3
T4
Tmmu
MMU STATES
PHil [
PHI2
[-1-----1
,---~~--------_+--------4---------
FLY [
(MMU)
1
AI6-23 [
(CPU)
-
(FLOAfiN:I;VENBYMMu)
toDINr
6iiiN[
(CPU)
AoS[
(CPU)
m-_[~
____-4______~____~_____
TL/EE/9160-51
FIGURE 4-10. Release from FLT Timing
Note that when FLTis deasserted the CPU restarts driving DDIN before the MMU releases it. This, however, does not cause any
conflict, since both CPU and MMU force DDIN to the same logic level.
TLlEE/9160-52
FIGURE 4-11. Ready Sampling (CPU Initially READY)
2-222
z
en
Co)
4.0 Device Specifications (Continued)
I\)
o
o
Co)
I I
I
~
.....
o
I
.......
:~~
z
en
Co)
I\)
oo
.
Co)
I\)
~
RDV[
.....
(II
TL/EE/9160-53
FIGURE 4·12. Ready Sampling (CPU Initially NOT READY)
I
I
T1
T4
I
I
PHI1[~
T1
I
T4
I
PHI1[~
tOth
PHI2 [
PHI2 [
ADO-15 [
ADIl-15 [
SPe[
s.c[
(CPU)
DffiN[-+~............+-............-+-S~3 [-+................+-J,__....-+_
DDiN[
STG-3 [
AoS[
AoS[
(HIGH)
I
TL/EE/9160-55
TUEE/9160-54
FIGURE 4·14. Slave Processor Read Timing
FIGURE 4·13. Slave Processor Write Timing
T1
T4
PHil [
•
PHI2 [
SPC [
(rROM CPU)
(rROM SLA~E1 [ .
--------
-------
------
TL/EE/9160-56
FIGURE 4·15. SPC Timing
After transferring last operand to a Slave Processor, CPU
turns OFF driver and holds SPC high with internal 5 kO pull up.
TL/EE/9160-57
FIGURE 4·16. Reset Configuration Timing
2·223
....•
'"
II)
C")
«:)
4.0 Device Specifications
(Continued)
o
'"
~
z
......
«:)
....
PHil [
~
C")
«:)
~
C")
(J)
z
PHI2 [
TL/EE/9160-5B
FIGURE 4-17. Clock Waveforms
PHI2[~ruu
~[~~
TL/EE/9160-59
FIGURE 4-18. Relationship of PFS to Clock Cycles
T1
PHil [
~[b'----J/
s~ [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
...J
CODE 1001
TL/EE/9160-60
FIGURE 4-19a. Guaranteed Delay, PFS to Non-Sequential Fetch
I
Tl
I
T2
I ••• I
I
I
I
PHllL[LfLJl-1{LflJL
AoS[
s~ [
CODE 1001
+-----~}--~----
INSPF
TL/EE/9160-61
FIGURE 4-19b. Guaranteed Delay, Non-Sequential Fetch to PFS
2-224
z
en
Co)
4.0 Device Specifications (Continued)
N
o
C)
Co)
I
13 OR TI
I
T40RTI
I
Tl
12
13
~
......
T4
C)
......
z
en
Co)
N
o
C)
Co)
~
......
ADS [
U1
ILO[
TLlEE/9160-62
FIGURE 4-20a. Relationship of ILO to First Operand Cycle of an Interlocked Instruction
I
T3 OR T;
I
T40RTI
I
T1
12
T3
T4
iD[ ________________t-____________-+'
TL/EE/9160-63
FIGURE 4-20b. Relationship of ILO to Last Operand Cycle of an Interlocked Instruction
til
TL/EE/9160-64
FIGURE 4-21. Relationship of ILO to Any Clock Cycle
I T30RT; I T40RTI
I
T1
T2
T3
T4
PHil [
AiiS[
U/S[ """''''''-LI.,",",,¥, 1\-__+-____________________+'1
TLlEE/9160-65
FIGURE 4-22. U/S Relationship to Any Bus Cycle - Guaranteed Valid Interval
2-225
.,...
U) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
N
CO)
4.0 Device Specifications (Continued)
(;)
o
N
CO)
T1
tn
I
Tmmu
n
T2
Z
~
.,...
PHil [
N
CO)
(;)
o
N
CO)
tn
Z
Tl/EE/9160-66
FIGURE 4-23. Abort Timing, FLT Not Applied
PHil [
PHIZ [
OS/FtT [
-r----+---+---++-.....J
TlIEE/9160-67
FIGURE 4-24. Abort Timing, FLT Applied
vee
PHil [
I.o----------I\--
--1------
RST/ffi[ _ _ _ _ _ _ _ _ _ _ _ _ _\\--1
Tl/EE/9160-66
FIGURE 4-25. Power-On Reset
PHll[~JLfl-
"',~[
~
1RSTSrII
.....
Tl/EE/9160-69
FIGURE 4-26. Non-Power-On Reset
2-226
z
(f)
4.0 DevIce Specifications (Continued)
c.,)
I\)
n
o
....o.
c.,)
I\)
PHI1[JULrL
.....
~tINT.
iNr[
Z
~
(f)
NM{
c.,)
I\)
TL/EE/9160-71
TL/EE/9160-70
FIGURE 4-28. NMllnterrupt Signal Timing
FIGURE 4-27. INT Interrupt Signal Detection
ARST BUS CYCLE
T1
12
T3
NEXT
T4
TlorTI
I
TL/EE/9160-72
FIGURE 4-29. Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction
Note: In a transfer of a Read-Modify-Write type operand, this is the Read transfer, displaying RMW Status (Code 1011).
2-227
n
o
.
c.,)
I\)
....
en
~
,...
,--------------------------------------------------------------------------,
N
Appendix A: Instruction Formats
o
NOTATIONS
C")
~
C")
tn
Z
C;
,...
N
C")
8
C'I
C")
tn
Z
Configuration bits, in SETCFG:
I I I Fill
i = Integer Type Field
C
B = 00 (Byte)
W = 01 (Word)
D = 11 (Double Word)
f= Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L = 0 (Long Floating: 64 bits)
c= Custom Type Field
D = 1 (Double Word)
Q = 0 (Quad Word)
op = Operation Code
Valid encodings shown with each format.
gen, gen 1, gen 2 = General Addressing Mode Field
See Sec. 2.2 for encodings.
reg= General Purpose Register Number
cond = Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110 = Greater Than: N = 1
0111 = Less or Equal: N = 0
1000 = Flag Set: F = 1
1001 = Flag Clear: F = 0
1010 = LOwer: L = 0 and Z = 0
1011 = Higher or Same: L = 1 orZ = 1
1100 = Less Than: N = 0 and Z = 0
1101 = Greater or Equal: N = 1 or Z = 1
1110 = (Unconditionally True)
1111 = (Unconditionally False)
7
11' 0' l' 01
FormatO
(BR)
Bcond
7
0
;p'
10' 0' l' 01
Format 1
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPR.
0000 = US
0001 - 0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = (Reserved)
1100 = (Reserved)
1101 = PSR
1110 = INTBASE
1111 = MOD
ADDQ
CMPQ
SPR
Scond
Options: in String Instructions
U/W
0
1 co'nd'
short= Short Immediate value. May contain
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ,ACB.
I
M
mreg: NS32082 Register number, in LMR, SMR.
0000 = BPRO
0001 = BPR1
0010 = (Reserved)
0011 = (Reserved)
0100 = (Reserved)
0101 = (Reserved)
0110 = (Reserved)
0111 = (Reserved)
1000 = (Reserved)
1001 = (Reserved)
1010 = MSR
1011 = BCNT
1100 = PTBO
1101 = PTB1
1110 = (Reserved)
1111 = EIA
I BIT I
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
2-228
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
15
,,
1
gen
ENTER
EXIT
NOP
WAIT
DIA
FLAG
SVC
BPT
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
al7 , ,
'sh~rt
1
Format 2
-000
ACB
-001
MOVQ
-010
LPR
-011
op
0
11 ' 1 '
1
-100
-101
-110
z
en
Co)
Appendix A: Instruction Formats (Continued)
15
I
,,,,
gen
SI7
N
S7
,0
1 1 1 1 1I i
I "op I""
I
Format 3
CXPD
-0000
ADJSP
BICPSR
-0010
JSR
JUMP
-0100
CASE
BISPSR
-0110
Trap (UND) on XXX1, 1000
-1010
-1100
-1110
, , , , , ,SI7, , , ,
I gen 1 I gen2 I op
15
0
0
I
0
0
Co)
N
....
0
I
1 0 0 1 1 1 0
7
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
Format
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
FormatS
-000
INDEX
-001
FFS
-010
-011
-110,reg = 001
-110, reg = 011
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
DIV
.......
Z
en
Co)
N
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
0
0
Co)
N
....
I
UI
Format 4
ADD
CMP
BIC
AD DC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
SUB
AD DR
AND
SUBC
TBIT
XOR
-1000
-1001
-1010
-1100
-1101
-1110
TLlEE/9160-73
0
i
o0
0 0 1 1 1 0
0
Format 5
MOVS
-0000
SETCFG
CMPS
-0001
SKPS
Trap (UND) on 1XXX, 01XX
-0010
-0011
1 1 1 1 1 0
0
o0
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
Format 6
-0000
NEG
-0001
NOT
Trap (UND)
-0010
-0011
SUBP
-0100
ABS
-0101
COM
IBIT
-0110
-0111
ADDP
-100
-1 01
1 1 1 0
MOVif
LFSR
MOVLF
MOVFL
Format 9
ROUND
-000
-001
TRUNC
SFSR
-010
-011
FLOOR
-100
-101
-110
-111
0
---I I I I I I I I 1
___ 0 1 0 1 1 1 1 0
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
TLlEE/9160-77
Format 10
Trap (UND) Always
2-229
•
.... r---------------------------------------------------------------------------------,
~
~
Appendix A: Instruction Formats (Continued)
8
o
~
U)
16115
1 1 1 1 0
z
......
....
o
C")
8
N
C")
U)
z
10 Byte
Operation Word
Format 11
N
ADD!
MOV!
CMP!
Trap (SLAVE)
SUB!
NEG!
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
DIV!
Trap (SLAVE)
Trap (UNO)
Trap (UNO)
MUll
ABS!
Trap (UNO)
Trap (UNO)
Format 15
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
7
(Custom Slave)
Operation Word Format
nnn
000
Format 15.0
0
---I
I I I I I I I 1
___.1 1 1 1 1 1 1 O.
CATSTO
CATST1
TLIEE19160-75
-0000
-0001
LCR
SCR
-0010
-0011
Format 12
Trap (UNO) on all others
Trap (UNO) Always
o
7
-'-1
I I I I I I I
___ 1 0 0 1 1 1 1 0
1
001
TLIEE19160-76
Format 13
Format 15.1
Trap (UNO) Always
o
i
000 1 1 1
0
CCV3
LCSR
CCV5
CCV4
Format 14
RDVAL
-0000
WRVAL
-0001
Trap (UNO) on 01 XX, 1XXX
LMR
SMR
-000
-001
-010
-011
CCV2
CCV1
SCSR
CCVO
-100
-101
-110
-111
23
-0010
-0011
101
gen 1
Format 15.5
CCALO
CMOVO
CCMPO
CCMP1
CCAL1
CMOV2
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
If nnn ~ 010,011,100,110,111
then Trap (UNO) Always
2-230
CCAL3
CMOV3
Trap (UNO)
Trap (UNO)
CCAL2
CMOV1
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
z
en
w
Appendix A: Instruction Formats (Continued)
7
---I
N
7
0
I I I I I I I
___ 0 1 0 1 1 1 1 0
1
Format 16
Format 19
0 "1 1 I ~
w
N
oo
Trap (UNO) Always
7
Implied Immediate Encodings:
0
---I " " "
I
___ 1 1 0 1 1 1 1 0
1
a
7
r1
TL/EE/9160-78
o
o
N
1 W.....
•
o
TLlEE/91S0-80
.......
z
en
---I xIIx x"0
___
TLlEE/9160-77
Trap (UNO) Always
0
ra
W
N
.....•
U1
Register Mark, appended to SAVE, ENTER
Format 17
a
7
Trap (UNO) Always
---I
n. "
I I "
I
1 0 0 0 1 1 1 0
1
Register Mark, appended to RESTORE, EXIT
a
7
TLlEE/9160-79
; offset;
Format 18
Offset/Length Modifier appended to INSS, EXTS
Trap (UNO) Always
•
2-231
NS32C032·10/NS32C032-15
P[AIPH CYCLE
PER
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Wiifi
RESET
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NS32C201
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12.1 . . . . .
1321
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AOO-A023
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ADO-AD1S
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STROBE
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ADDRESS
AOO-A023 LATCHI
BUffER
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SI0-ST3
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024-031
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TLlEE/9160-81
FIGURE B-1. System Connection Diagram
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NS32C032
CPU
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~National
~ Semiconductor
NS32032-10 High-Performance Microprocessor
General Description
Features
The NS32032 is a 32-bit, virtual memory microprocessor
with a 16-MByte linear address space and a 32-bit external
data bus. It has a 32-bit ALU, eight 32-bit general purpose
registers, an eight-byte prefetch queue, and a slave processor interface. The NS32032 is fabricated with National
Semiconductor's advanced XMOSTM process, and is fully
object code compatible with other Series 32000® processors. The Series 32000 instruction set is optimized for modular, high-level languages (HLL). The set is very symmetric,
it has a two address format, and it incorporates HLL oriented addressing modes. The capabilities of the NS32032 can
be expanded with the use of the NS32081 floating point unit
(FPU), and the NS32082 demand-paged virtual memory
management unit (MMU). Both devices interface to the
NS32032 as slave processors. The NS32032 is a general
purpose microprocessor that is ideal for a wide range of
computational intensive applications.
•
•
•
•
•
32-bit architecture and implementation
Virtual memory support
16-MByte linear address space
32-bit data bus
Powerful instruction set
- General 2-address capability
- Very high degree of symmetry
- Addressing modes optimized for high-level
languages
• Series 32000 slave processor support
• High-speed XMOS technology
• 68-pin lead less chip carrier
Block Diagram
ADD/DATA
CONTROLS. STATUS
MICROCODE ROM
AND
CONTROL LOGIC
mIl
CFG REGISTER
REGISTER SET
o
o
o
o
INTBASE
SB
FP
SPI
WORKING
REGISTERS
SPO
PC
RD
Rl
R2
R3
R4
R5
I
I
I
R6
R7
I
I
MOD
I
PSR
:
L_________________
J
TL/EE/5491-1
FIGURE 1
2-233
Table of Contents
1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.B NS32032 Interrupt Structure
2.0 ARCHITECTURAL DESCRIPTION
3.B.1 General Interrupt/Trap Sequence
3.B.2 Interrupt/Trap Return
3.B.3 Maskable Interrupts (The INT Pin)
3.B.3.1 Non-Vectored Mode
3.B.3.2 Vectored Mode: Non-Cascaded Case
3.B.3.3 Vectored Mode: Cascaded Case
3.B.4 Non-Maskable Interrupt (The NMI Pin)
3.B.5 Traps
3.B.6 Prioritization
3.B.7 Interrupt/Trap Sequences Detailed Flow
3.B.7.1 Maskable/Non-Maskable Interrupt
Sequence
3.B.7.2 Trap Sequence: Traps Other Than Trace
3.B.7.3 Trace Trap Sequence
3.B.7.4 Abort Sequence
2.1 Programming Model
2.1.1 General Purpose Registers
2.1.2 Dedicated Registers
2.1.3 The Configuration Register (CFG)
2.1.4 Memory Organization
2.1.5 Dedicated Tables
2.2 Instruction Set
2.2.1 General Instruction Format
2.2.2 Addressing Modes
2.2.3 Instruction Set Summary
3.0 FUNCTIONAL DESCRIPTION
3.1
3.2
3.3
3.4
Power and Grounding
Clocking
Resetting
Bus Cycles
3.9 Slave Processor Instructions
3.9.1
3.9.2
3.9.3
3.9.4
3.4.1 Cycle Extension
3.4.2 Bus Status
3.4.3 Data Access Sequences
3.4.3.1 Bit Accesses
3.4.3.2 Bit Field Accesses
3.4.3.3 Extending Multiply Accesses
3.4.4 Instruction Fetches
3.4.5 Interrupt Control Cycles
3.4.6 Slave Processor Communication
3.4.6.1 Slave Processor Bus Cycles
3.4.6.2 Slave Operand Transfer Sequences
Slave Processor Protocol
Floating Point Instructions
Memory Management Instructions
Custom Slave Instructions
4.0 DEVICE SPECIFICATIONS
4.1 Pin Descriptions
4.1.1 Supplies
4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
3.5 Memory Management Option
3.5.1 Address Translation Strap
3.5.2 Translated Bus Timing
3.5.3 The FLT (Float) Pin
3.5.4 Aborting Bus Cycles
3.5.4.1 The Abort Interrupt
3.5.4.2 Hardware Considerations
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
4.4.2.2 Input Signals Requirements
4.4.2.3 Clocking Requirements
4.4.3 Timing Diagrams
Appendix A: Instruction Formats
Appendix B: Interfacing Suggestions
3.6 Bus Access Control
3.7 Instruction Status
List of Illustrations
CPU Block Diagram ............................................................................................~:~
The General and Dedicated Registers ............................................................................ -2
~~~1~1~:/~1
. •.• •.• •. • .• .• • .• .• •. • .• .• •. .•. • • •. .•. • •. .• •. • • •.• . ··,E
Recommended Supply Connections .............................................................................. 3-2
~=;~~~:~;~:::~~
Recommended Reset Connections, Non-Memory-Managed System ................................................ .
Recommended Reset Connections, Memory-Managed System ..................................................... 3-5b
2-234
List of Illustrations (Continued)
Bus Connections ...............................................................................................3-6
Read Cycle Timing .............................................................................................3-7
Write Cycle Timing .............................................................................................3-8
RDY Pin Timing ................................................................................................ 3-9
Extended Cycle Example ......................................................................................3-1 0
Memory Interface .............................................................................................3-11
Slave Processor Connections .................................................................................. 3-12
CPU Read from Slave Processor ................................................................................ 3-13
CPU Write to Slave Processor .................................................................................. 3-14
Read Cycle with Address Translation (CPU Action) ................................................................ 3-15
Write Cycle with Address Translation (CPU Action) ................................................................ 3-16
Memory-Managed Read Cycle .................................................................................. 3-17
Memory-Managed Write Cycle .................................................................................. 3-18
FLTTiming ...................................................................................................3-19
HOLD Timing, Bus Initially Idle .................................................................................. 3-20
HOLD Timing, Bus Initially Not Idle .............................................................................. 3-21
Interrupt Dispatch and Cascade Tables .......................................................................... 3-22
Interrupt/Trap Service Routine Calling Sequence ................................................................. 3-23
Return from Trap (RETT n) Instruction Flow ...................................................................... 3-24
Return from Interrupt(RET) Instruction Flow ...................................................................... 3-25
Interrupt Control Connections (16 levels) ......................................................................... 3-26
Cascaded Interrupt Control Unit Connections ..................................................................... 3-27
Service Sequence ............................................................................................3-28
Slave Processor Protocol ......................................................................................3-29
Slave Processor Status Word Format. ........................................................................... 3-30
NS32032 Connection Diagram ...................................................................................4-1
Timing Specification Standard (Signal Valid After Clock Edge) ........................................................ 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
Write Cycle ....................................................................................................4-4
Read Cycle ................................................................................................... .4-5
Floating by HOLD Timing (CPU Not Initially Idle) .................................................................... 4-6
Floating by HOLD Timing (CPU Initially Idle) ...................................................................... .4-7
Release from Hold .............................................................................................4-8
FLT Initiated Float Cycle Timing .................................................................................. 4-9
Release from FLT Timing ..................................................................................... .4-10
Ready Sampling (CPU Initially READY) .......................................................................... 4-11
Ready Sampling (CPU Initially NOT READy) ......................................................................4-12
Slave Processor Write Timing ...................................................................................4-13
Slave Processor Read Timing ................................................................................. .4-14
SPC Timing ................................................................................................. .4-15
Reset Configuration Timing .................................................................................... .4-16
Clock Waveforms .............................................................................................4-17
Relationship of PFS to Clock Cycles ............................................................................ .4-18
Guaranteed Delay, PFSto Non-Sequential Fetch ................................................................ 4-19a
Guaranteed Delay, Non-Sequential Fetch to PFS ................................................................ 4-19b
Relationship of ILO to First Operand of an Interlocked Instruction .................................................. 4-20a
Relationship of ILO to Last Operand of an Interlocked Instruction .................................................. 4-20b
Relationship of ILO to Any Clock Cycle .......................................................................... 4-21
U/S Relationship to any Bus Cycle - Guaranteed Valid Interval. .................................................... 4-22
Abort Timing, FLT Not Applied ................................................................................. .4-23
Abort Timing, FLT Applied ...................................................................................... 4-24
Power-On Reset ............................................................................................. .4-25
Non-Power-On Reset. ........................................................................................ .4-26
INT Interrupt Signal Detection .................................................................................. 4-27
MNI Interrupt Signal Timing ..................................................................................... 4-28
Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction ........................... 4-29
Processor System Connection Diagram ........................................................................... B-1
2-235
z
w
Co)
N
oCo)
.
N
.....
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.... r---------------------------------------------------------------------------------,
C)
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en
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z
List of Tables
NS32032 Addressing Modes .................................................................................... 2-1
NS32032 Instruction Set Summary ...............................................................................2-2
Bus Access Type ..............................................................................................3-1
Access Sequence ..............................................................................................3-2
Interrupt Sequences ............................................................................................3-3
Floating Point Instruction Protocols ...............................................................................3-4
Memory Managementlnstruction Protocols ........................................................................3-5
Custom Slave Instruction Protocols ...............................................................................3-6
2-236
z
en
1.0 Product Introduction
The Series 32000 microprocessor family is a new generation of devices using National's XMaS and CMOS technologies. By combining state-of-the-art MaS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
• High-Level Language Support
~
oCo)
• Easy Future Growth Path
• Application Flexibility
....o•
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes 16 registers on the
NS32032 CPU.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. Th!! family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
2.1.1 General Purpose Registers
There are eight registers for meeting high speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are thirty-two bits in
length. If a general register is specified for an operand that
is eight or sixteen bits long, only the low part of the register
is used; the high part is not referenced or modified.
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
2.1.2 Dedicated Registers
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
The eight dedicated registers of the NS32032 are assigned
specific functions.
PC: The PROGRAM COUNTER register is a pointer to
the first byte of the instruction currently being executed.
The PC is used to reference memory in the program
section. (In the NS32032 the upper eight bits of this
register are always zero.)
Symmetric Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided. This powerful memory·to-memory architecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
SPO, SP1: The SPO register points to the lowest address
of the last item stored on the INTERRUPT STACK. This
stack is normally used only by the operating system. It is
used primarily for storing temporary data, and holding
return information for operating system subroutines and
interrupt and trap service routines. The SP1 register
pOints to the lowest address of the last item stored on
the USER STACK. This stack is used by normal user
programs to hold temporary data and subroutine return
information.
In this document, reference is made to the SP register.
The terms "SP register" or "SP" refer to either SPO or
SP1, depending on the setting of the S bit in the PSR
register. If the S bit in the PSR is 0 the SP refers to SPO.
If the S bit in the PSR is 1 then SP refers to SP1. (In the
NS32032 the upper eight bits of these registers are always zero).
Memory Management. Either the NS32382 or the
NS32082 Memory Management Unit may be added to the
system to provide advanced operating system support func·
tions, including dynamic address translation, virtual memory
management, and memory protection.
Large, Uniform Addressing. The NS32032 has 24-bit address pointers that can address up to 16 megabytes without
requiring any segmentation; this addressing scheme provides flexible memory management without added·on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a significant reduction in hardware and
software cost.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
Stacks in the Series 32000 family grow downward in
memory. A Push operation pre-decrements the Stack
Pointer by the operand length. A Pop operation post-increments the Stack Pointer by the operand length.
FP: The FRAME POINTER register is used by a procedure to access parameters and local variables on the
stack. The FP register is set up on procedure entry with
the ENTER instruction and restored on procedure termination with the EXIT instruction.
The frame pointer holds the address in memory occupied by the old contents of the frame pointer. (In the
NS32032 the upper eight bits of this register are always
zero.)
S8: The STATIC BASE register points to the global variables of a software module. This register is used to support relocatable global variables for software modules.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
2-237
N
0
..•
C"\I
CO)
2.0 Architectural Description
(Continued)
0
C"\I
GENERAL
CO)
en
DEDICATED
Z
32
32
RO
0
PROGRAM COUNTER
PC
0
STAT1CBASE
SB
0
FRAME POINTER
FP
0
USER STACK PTR.
0
INTERRUPT STACK PTR.
R1
R2
R3
SP1 }
SP
R4
SPO
RS
·0
INTERRUPT BASE
PSR
MOD
STATUS
MODULE
INTBASE
RS
R7
TLlEE/5491-3
FIGURE 2·1. The General and Dedicated Registers
The SB register holds the lowest address in memory
occupied by the global variables of a module. (In the
NS32032 the upper eight bits of this register are always
zero.)
Z: The Z bit is altered by comparison instructions. In a
comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is
set to "0".
INTBASE: The INTERRUPT BASE register holds the
address of the dispatch table for interrupts and traps
(Sec. 3.8). The INTBASE register holds the lowest address in memory occupied by the dispatch table. (In the
NS32032 the upper eight bits of this register are always
zero.)
N: The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to "0".
U: If the U bit is "1" no privileged instructions may be
executed. If the U bit is "0" then all instructions may be
executed. When U = 0 the NS32032 is said to be in
Supervisor Mode; when U = 1 the NS32032 is said to
be in User Mode. A User Mode program is restricted
from executing certain instructions and accessing certain registers which could interfere with the operating
system. For example, a User Mode program is prevented from changing the setting of the flag used to indicate
its own privilege mode. A Supervisor Mode program is
assumed to be a trusted part of the operating system,
hence it has no such restrictions.
MOD: The MODULE register holds the address of the
module descriptor of the currently executing software
module. The MOD register is sixteen bits long, therefore
the module table must be contained within the first 64K
bytes of memory.
PSR: The PROCESSOR STATUS REGISTER (PSR)
holds the status codes for the NS32032 microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all
programs, but the high order eight bits are accessible
only to programs executing in Supervisor Mode.
S: The S bit specifies whether the SPO register or SP1
register is used as the stack pOinter. The bit is automatically cleared on interrupts and traps. It may have a setting of 0 (use the SPO register) or 1 (use the SP1 register).
P: The P bit prevents a TRC trap from occurring more
than once for an instruction (Sec. 3.8.5.). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
I: If I = 1, then all interrupts will be accepted (Sec. 3.B.).
If I = 0, only the NMI interrupt is accepted. Trap enables are not affected by this bit.
15
817
0
IXlXIXIXII I lsi HI zI IXIXI LI Icl
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TLlEE/5491-4
FIGURE 2·2. Processor Status Register
C: The C bit indicates that a carry or borrow occurred
after an addition or subtraction instruction. It can be
used with the ADDC and SUBC instructions to perform
multiple-precision integer arithmetic calculations. It may
have a setting of 0 (no carry or borrow) or 1 (carry or
borrow).
2.1.3 The Configuration Register (CFG)
T: The T bit causes program traCing. If this bit is a 1, a
TRC trap is executed after every instruction (Sec. 3.8.5).
Within the Control section of the NS32032 CPU is the fourbit CFG Register, which declares the presence of certain
external devices. It is referenced by only one instruction,
SETCFG, which is intended to be executed only as part of
system initialization after reset. The format of the CFG Register is shown in Figure 2-3.
L: The L bit is altered by comparison instructions. In a
comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as unsigned integers. Otherwise, it is set to "0". In Floating Point comparisons, this
bit is always cleared.
F: The F bit is a general condition flag, which is altered
by many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
FIGURE 2·3. CFG Register
2-238
z
2.0 Architectural Description
en
w
(Continued)
N
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the NS32202 Interrupt Control Unit). If the CFG I bit is set, interrupts requested through
the INT pin are "Vectored." If it is clear, these interrupts are
"Non-Vectored." See Sec. 3.8.
The MOD register contains a pOinter into the Module Table,
whose entries are called Module Descriptors. A Module Descriptor contains four pointers, three of which are used by
NS32032. The MOD register contains the address of the
Module Descriptor for the currently running module. It is automatically up-dated by the Call External Procedure instructions (CXP and CXPD).
The F, M and C bits declare the presence of the FPU, MMU
and Custom Slave Processors. If these bits are not set, the
corresponding instructions are trapped as being undefined.
The format of a Module Descriptor is shown in Figure 2-4.
The Static Base entry contains the address of static data
assigned to the running module. It is loaded into the CPU
Static Base register by the CXP and CXPD instructions. The
Program Base entry contains the address of the first byte of
instruction code in the module. Since a module may have
multiple entry pOints, the Program Base pointer serves only
as a reference to find them.
2.1.4 Memory Organization
The main memory of the NS32032 is a uniform linear address space. Memory locations are numbered sequentially
starting at zero and ending at 224 - 1. The number specifying a memory location is called an address. The contents of
each memory location is a byte consisting of eight bits. Unless otherwise noted, diagrams in this document show data
stored in memory with the lowest address on the right and
the highest address on the left. Also, when data is shown
vertically, the lowest address is at the top of a diagram and
the highest address at the bottom of the diagram. When bits
are numbered in a diagram, the least significant bit is given
the number zero, and is shown at the right of the diagram.
Bits are numbered in increasing significance and toward the
left.
I
r-
LINK TABLE ADDRESS
PROGRAM BASE
RESERVED
..
Two contiguous bytes are called a word. Except where noted (Sec. 2.2.1), the least significant byte of a word is stored
at the lower address, and the most significant byte of the
word is stored at the next higher address. In memory, the
address of a word is the address of its least significant byte,
and a word may start at any address.
817
LSB's
TL/EE/5491-5
FIGURE 2-4. Module Descriptor Format
The Link Table Address points to the Link Table for the
currently running module. The Link Table provides the information needed for:
01
1) Sharing variables between modules. Such variables are
accessed through the Link Table via the External addressing mode.
A
A+1
Word at Address A
Two contiguous words are called a double word. Except
where noted (Sec. 2.2.1), the least significant word of a double word is stored at the lowest address and the most significant word of the double word is stored at the address two
greater. In memory, the address of a double word is the
address of its least significant byte, and a double word may
start at any address.
A+3
oj
STATIC BASE
A
16115
I
31
Byte at Address A
131 MSB's 24123
MOD
I
01
115 MSB's
o
15
817
A+2
A+1
Double Word at Address A
LSB's
2) Transferring control from one module to another. This is
done via the Call External Procedure (CXP) instruction.
The format of a Link Table is given in Figure 2-5. A Link
Table Entry for an external variable contains the 32-bit address of that variable. An entry for an external procedure
contains two 16·bit fields: Module and Offset. The Module
field contains the new MOD register contents for the module being entered. The Offset field is an unsigned number
giving the position of the entry point relative to the new
module's Program Base pOinter.
01
A
For further details of the functions of these tables, see the
Series 32000 Instruction Set Reference Manual.
Although memory is addressed as bytes, it is actually organized as double-words. Note that access time to a word or a
double-word depends upon its address, e.g. double-words
that are aligned to start at addresses that are multiples of
four will be accessed more quickly than those not so
aligned. This also applies to words that cross a double-word
boundary.
ENTRY
o
...
Two of the NS32032 dedicated registers (MOD and INTBASE) serve as pOinters to dedicated tables in memory.
ABSOLUTE AODRESS
(VARIABLE)
ABSOLUTE AODRESS
(VARIABLE)
OFFSET
2
2.1_5 Dedicated Tables
o-r
31
I
MODULE
( PROCEDURE)
-
...
FIGURE 2-5. A Sample Link Table
The INTBASE register points to the Interrupt Dispatch and
Cascade tables. These are described in Sec. 3.8.
2-239
TL/EE/5491-6
C)
W
~
......
C)
....
C) r-------------------------------------------------------------------------------------~
W
C")
C)
N
~
Z
2.0 Architectural Description
(Continued)
Byte Displacement: Range -64 to +63
2.2 INSTRUCTION SET
2.2.1 General Instruction Format
SIGNED DISPLACEMENT
Figure 2-6 shows the general format of a Series 32000 in·
struction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Addressing Mode ("Gen") fields. Following the Basic Instruction field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes se·
lected.
Word Displacement: Range -8192 to + 8191
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Rgure 2-7.
1'
GEN. ADDR. MODE
REG. NO.
Double Word DiBplacement:
Range (Entire AddreBslng Space)
'I
0
7
1
TL/EE/5491-B
:
1
I
FIGURE 2-7. Index Byte Format
,,/-
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected address modes. Each Disp/lmm field may contain one or
two displacements, or one immediate value. The size of a
Displacement field is encoded with the top bits of that field,
as shown in Figure 2-8, with the remaining bits interpreted
as a Signed (two's complement) value. The size of an immediate value is determined from the Opcode field. Both Displacement and Immediate fields are stored most significant
byte first. Note that this is different from the memory representation of data (Sec. 2.1.4).
TLlEE/5491-11
FIGURE 2-8. Displacement Encodings
2.2.2 Addressing Modes
The NS32032 CPU generally accesses an operand by calculating its Effective Address based on information available when the operand is to be accessed. The method to be
used in performing this calculation is specified by the programmer as an "addressing mode."
Some instructions require additional, "implied" immediates
and/or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Sec. 2.2.3).
OPTIONAL
EXTENSIONS
BASIC
INSTRUCTION
r~----------------~A~----------------~\(~-------~~
DISP2 DISPI DISP21DISPI
IMPUED
IMMEDIATE
OPERAND(S)
DISP
DISP
IMM
IMM
INDEX
BYTE
INDEX
BYTE
t
t
GEN
ADDR
MODE
A
GEN
ADDR
MODE
B
OPCODE
j
TL/EE/5491-7
FIGURE 2-6. General Instruction Format
2-240
2.0 Architectural Description (Continued)
Addressing modes in the NS32032 are designed to optimally support high-level language accesses to variables. In
nearly all cases, a variable access requires only one addressing mode, within the instruction that acts upon that
variable. Extraneous data movement is therefore minimized.
NS32032 Addressing Modes fall into nine basic types:
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
2.2.3 Instruction Set Summary
Table 2-2 presents a brief description of the NS32032 instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Notations:
i = Integer length suffix:
Memory Space. Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Memory Relative: A pointer variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pointer to generate the Effective Address of the operand.
B = Byte
W = Word
D = Double Word
F = Standard Floating
L = Long Floating
gen = General operand. Any addressing mode can be
specified.
short = A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
f
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
External: A pointer value is read from a specified entry of
the current Link Table. To this pOinter value is added a displacement, yielding the Effective Address of the operand.
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode.
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by I, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
= Floating Point length suffix:
imm = Implied immediate operand. An 8-bit value appended after any addressing extensions.
disp = Displacement (addressing constant): 8, 16 or 32
bits. All three lengths legal.
reg = Any General Purpose Register: RO-R7.
areg = Any Dedicated/Address Register: SP, SB, FP,
MOD, INTBASE, PSR, US (bottom 8 PSR bits).
mreg = Any Memory Management Status/Control Register.
crag = A Custom Slave Processor Register (Implementation Dependent).
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
2-241
II
C)
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(I)
2.0 Architectural Description
(Continued)
C)
C'I
(I)
TABLE 2-1
(/)
Z
NS32032 Addressing Modes
ENCODING
Register
00000
00001
00010
00011
00100
00101
00110
00111
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Memory Relative
10000
10001
10010
Reserved
10011
Immediate
10100
Absolute
10101
External
10110
Top of Stack
10111
Memory Space
11000
11001
11010
11011
Scaled Index
11100
11101
11110
11111
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
RegisterB
Register 7
ROorFO
R1 or F1
R20rF2
R3 or F3
R40rF4
R50rF5
RBorFB
R7orF7
None: Operand is in the specified
register
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register B relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(RB)
disp(R7)
Disp + Register.
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP»
disp2(disp1 (SP»
disp2(disp 1(SB»
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP"
is either SPO or SP1 , as selected
in PSR.
Immediate
value
None: Operand is input from
instruction queue.
Absolute
@disp
Disp.
External
EXT (disp1) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
*+disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2x Rn.
EA (mode) + 4x Rn.
EA (mode) + B X Rn.
'Mode' and 'n' are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
(Reserved for Future Use)
2-242
ztJ)
2.0 Architectural Description
w
I\)
o
w
I\)
(Continued)
TABLE 2-2
NS32032 Instruction Set Summary
MOVES
Format
4
2
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4-bit constant.
Move Multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move Effective Address.
INTEGER ARITHMETIC
Format
4
2
4
4
4
6
6
7
7
7
7
7
7
7
Operation
Operands
Description
ADDI
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEIi
DEli
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to Extended Integer.
Divide Extended Integer.
PACKED DECIMAL (BCD) ARITHMETIC
Format
6
6
Operation
Operands
Description
ADDPi
SUBPi
gen,gen
gen,gen
Add Packed.
Subtract Packed.
INTEGER COMPARISON
Format
4
2
7
Operation
Operands
Description
CMPi
CMPQi
CMPMi
gen,gen
short,gen
gen,gen,disp
Compare.
Compare to signed 4-bit constant.
Compare Multiple: disp bytes (1 to 16).
Operation
Operands
Description
ANDi
ORi
BICi
XORi
COMi
NOTi
Scondi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Logical AND.
Logical OR.
Clear selected bits.
Logical Exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
LOGICAL AND BOOLEAN
Format
4
4
4
4
6
6
2
2-243
.
.....
o
C)
....
~
Cf)
r-------------------------------------------------------------------------------------~
2.0 Architectural Description
~
~
z
(Continued)
TABLE 2·2 (Continued)
NS32032 Instruction Set Summary (Continued)
SHIFTS
Format
6
6
6
Operation
Operands
Description
LSHi
ASHi
ROTi
gen,gen
gen,gen
gen,gen
Logical Shift, left or right.
Arithmetic Shift, left or right.
Rotate, left or right.
Operation
Operands
Description
TBITi
SBITi
SBITII
CBITi
CBITli
IBITi
FFSi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Test bit.
Test and set bit.
Test and set bit, interlocked
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit
BITS
Format
4
6
6
6
e
6
8
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records
used in Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned
source.
Format
8
8
7
7
8
Operation
Operands
Description
EXTi
INSi
EXTSi
INSSi
CVTP
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm,imm
reg,gen,gen
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to Bit Field Pointer.
Operation
Operands
Description
CHECKi
INDEXi
reg,gen,gen
reg,gen,gen
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
ARRAYS
Format
8
8
STRINGS
String instructions assign specific functions to the General Purpose Registers:
Options on all string instructions are:
B (Backward):
Decrement string pointers after each step
rather than incrementing.
U (Until match):
End instruction if String 1 entry matches
R4.
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
W (While match): End instruction if String 1 entry does not
match R4.
R 1 - String 1 Pointer
RO - Limit Count
All string instructions end when RO decrements to zero.
Format
5
Operation
Operands
Descriptions
MOVSi
MOVST
options
options
Move String 1 to String 2.
Move string, translating bytes.
5
CMPSi
CMPST
options
options
Compare String 1 to String 2.
Compare translating, String 1 bytes.
5
SKPSi
SKPST
options
options
Skip over String 1 entries
Skip, translating bytes for Until/While.
2-244
z
2.0 Architectural Description
en
Co)
(Continued)
N
TABLE 2-2 (Continued)
NS32032 Instruction Set Summary (Continued)
JUMPS AND LINKAGE
Format
3
0
0
3
2
3
1
3
1
Operation
JUMP
BR
Bcond
CASEi
ACBi
JSR
BSR
CXP
CXPD
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
[reg Iistl,disp
[reg list]
disp
disp
disp
CPU REGISTER MANIPULATION
Format
Operation
Operands
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor Call.
Flag Trap.
Breakpoint Trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
Description
SAVE
RESTORE
LPRi
SPRi
ADJSPi
BISPSRi
BICPSRi
SETCFG
[reg list]
[reg list]
areg,gen
areg,gen
gen
gen
gen
[option list]
Save General Purpose Registers.
Restore General Purpose Registers.
Load Dedicated Register. (Privileged if PSR or INTBASE)
Store Dedicated Register. (Privileged if PSR or INTBASE)
Adjust Stack Pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set Configuration Register. (Privileged)
FLOATING POINT
Format
Operation
Operands
Description
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Move a Floating Point value.
Move and shorten a Long value to Standard.
Move and lengthen a Standard value to Long.
Convert any integer to Standard or Long Floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Load FSR.
Store FSR.
1
2
2
3
3
3
5
11
9
9
9
9
9
9
11
11
11
11
11
11
11
9
9
MOVf
MOVLF
MOVFL
MOVif
ROUNDfi
TRUNCfi
FLOORfi
ADDf
SUBf
MULl
DIVf
CMPf
NEGf
ABSf
LFSR
SFSR
MEMORY MANAGEMENT
Format
Operation
Operands
Description
8
LMR
SMR
RDVAL
WRVAL
MOVSUi
mreg.gen
mreg,gen
gen
gen
gen,gen
8
MOVUSi
gen,gen
Load Memory Management Register. (Privileged)
Store Memory Management Register. (Privileged)
Validate address for reading. (Privileged)
Validate address for writing. (Privileged)
Move a value from Supervisor
Space to User Space. (Privileged)
Move a value from User Space
to Supervisor Space. (Privileged)
14
14
14
14
2-245
oCo)
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0
.....
N•
('I)
2.0 Architectural Description
0
TABLE 2·2 (Continued)
NS32032 Instruction Set Summary (Continued)
N
('I)
(I)
Z
(Continued)
MISCELLANEOUS
Format
Operation
1
NOP
WAIT
DIA
Operands
Description
No Operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
CUSTOM SLAVE
Format
Operation
Operands
Description
15.5
15.5
15.5
15.5
CCALOc
CCAL1c
CCAL2c
CCAL3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom Calculate.
15.5
15.5
15.5
15.5
CMOVOc
CMOV1c
CMOV2c
CMOV3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom Move.
15.5
15.5
CCMPOc
CCMP1c
gen,gen
gen,gen
Custom Compare.
15.1
15.1
15.1
15.1
15.1
15.1
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DO
CCV50D
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Custom Convert.
15.1
15.1
LCSR
SCSR
gen
gen
Load Custom Status Register.
Store Custom Status Register.
15.0
15.0
CATSTO
CATST1
gen
gen
Custom Address/Test. (Privileged)
(Privileged)
15.0
15.0
LCR
SCR
creg,gen
creg,gen
Load Custom Register. (Privileged)
Store Custom Register. (Privileged)
2-246
3.0 Functional Description
3.1 POWER AND GROUNDING
PHil (pin 26) and PHI2 (pin 27). Their relationship to each
other is shown in Figure 3-2.
The NS32032 requires a single 5-volt power supply, applied
on pin 1B (Vee!.
Each rising edge of PHil defines a transition in the timing
state ("T-State") of the CPU. One T-State represents the
execution of one microinstruction within the CPU, and/or
one step of an external bus transfer. See Section 4 for complete specifications of PHil and PHI2.
Grounding connections are made on four pins. Logic
Ground (GNDL, pin 54) is the common pin for on-chip logic,
and Buffer Grounds (GNDB1, pin 52 and GNDB2, pin 16
and GNDB3, pin 60) (16) are the common pins for the output drivers. For optimal noise immunity it is recommended
that GNDBI and GNDB2 be connected together through a
single conductor, and GNDL be directly connected to the
middle point of this conductor. All other ground connections
should be made to the common line as shown in Figure 3-1.
PHIl
In addition to Vee and Ground, the NS32032 CPU uses an
internally-generated negative voltage. It is necessary to filter
this voltage externally by attaching a pair of capacitors (Fig.
3-1) from the BBG pin to ground. Recommended values for
these are:
C1: 1 fLF, Tantalum.
C2: 1000 pF, low inductance. This should be either a disc or
monolithic ceramic capacitor.
PHI2
TLlEE/5491-13
FIGURE 3-2. Clock Timing Relationships
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHil and PHI2
be kept as short as possible, and that they not be connected anywhere except from the TCU to the CPU and, if present, the MMU. A TIL Clock signal (CTIL) is provided by the
TCU for all other clocking.
NS32032
CPU
3.3 RESETTING
The RST/ ABT pin serves both as a Reset for on-chip logic
and as the Abort input for Memory-Managed systems. For
its use as the Abort Command, see Sec. 3.5.4.
The CPU may be reset at any time by pulling the RST / ABT
pin low for at least 64 clock cycles. Upon detecting a reset,
the CPU terminates instruction processing, resets its internal logic, and clears the Program Counter (PC) and Processor Status Register (PSR) to all zeroes.
TUEE/5491-12
FIGURE 3-1. Recommended Supply Connections
On application of power, RST / ABT must be held low for at
least 50 fLsec after Vee is stable. This is to ensure that all
on-chip voltages are completely stable before operation.
Whenever a Reset is applied, it must also remain
3.2 CLOCKING
The NS32032 inputs clocking signals from the Timing Control Unit (TCU), which presents two non-overlapping phases
of a single clock frequency. These phases are called
Vcc
PHIl
---f---.. .
RSr/Aiii ---+----------I~...J
1-----1::501'_ - - - - - l
TL/EE/5491-14
FIGURE 3-3_ Power-on Reset Requirements
2-247
o'P'"
r---------------------------------------------------------------------~
~
3.0 Functional Description
o
active for not less than 64 clock cycles. The rising edge
must occur while PHI1 is high. See Figures 3-3 and 3-4.
The NS32201 Timing Control Unit (TCU) provides circuitry
to meet the Reset requirements of the NS32032 CPU. Figure 3-5a shows the recommended connections for nonMemory-Managed system. Figure 3-5b shows the connections for a Memory-Managed system.
Cf)
N
Cf)
tJ)
Z
(Continued)
a
TL/EE/5491-15
FIGURE 3-4. General Reset Timing
vcc
N632201
TCU
NS32032
CPU
r------------.,
I
I
I RESET
1>--l-1--l--_-1--.......
+ ....----'
I
RSTI
R-STO
/----"""1r----l
RST/ABT
,L. _____________ .JI
EXTERNAL RESET
(OPTIONAL)
~50J.L.ec
RESET SWITCH
(OPTIONAL)
SYSTEM
REiEr
TL/EE/5491-16
FIGURE 3-5a. Recommended Reset Connections, Non-Memory-Managed System
vcc
N832201
TCU
N832082
MMU
NS32032
CPU
r------------.,
I
II
I
RESET
1>---1Ii-+"""1r+-~~......~----I
iiSii
RsTci
!L. _____________ .JI
EXTERNAL RESET
(OPTIONAL)
~ 50~sec
RESET SWITCH
(OPTIONAL)
TL/EE/5491-17
FIGURE 3-5b. Recommended Reset Connections, Memory-Managed System
3) To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
3.4 BUS CYCLES
The NS32032 CPU has a strap option which defines the Bus
Timing Mode as either With or Without Address Translation.
This section describes only bus cycles under the No Address Translation option. For details of the use of the strap
and of bus cycles with address translation, see Sec. 3.5.
4) To transfer information to or from a Slave Processor.
In terms of bus timing, cases 1 through 3 above are identical. For timing specifications, see Sec. 4. The only external
difference between them is the four-bit code placed on the
Bus Status pins (STO-ST3). Slave Processor cycles differ in
that separate control signals are applied (Sec. 3.4.6).
The CPU will perform a bus cycle for one of the following
reasons:
1) To write or read data, to or from memory or a peripheral
interface device. Peripheral input and output are memorymapped in the Series 32000 family.
2) To fetch instructions into the eight-byte instruction queue.
This happens whenever the bus would otherwise be idle
and the queue is not already full.
The sequence of events in a non-Slave bus cycle is shown
below in Figure 3-7 for a Read cycle and Figure 3-8 for a
Write cycle. The cases shown assume that the selected
memory or interface device is capable of communicating
with the CPU at full speed. If it is not, then cycle extension
may be requested through the RDY line (Sec. 3.4.1).
2-248
3.0 Functional Description (Continued)
A full-speed bus cycle is performed in four cycles of the
PHI1 clock signal, labeled T1 through T4. Clock cycles not
associated with a bus cycle are designated Ti (for "Idle").
During T1, the CPU applies an address on pins ADO-AD23.
It also provides a low-going pulse on the ADS pin, which
serves the dual purpose of informing external circuitry that a
bus cycle is starting and of providing control to an external
latch for demultiplexing Address bits 0-23 from the ADOAD23 pins. See Figure 3-6. During this time also the status
signals DDIN, indicating the direction of the transfer, and
BEO-BE3, indicating which of the four bus bytes are to be
referenced, become valid.
The T3 state provides for access time reqUirements, and it
occurs at least once in a bus cycle. At the end of T2 or T3,
on the falling edge of the PHI2 clock, the ROY (Ready) line
is sampled to determine whether the bus cycle will be extended (Sec. 3.4.1).
If the CPU is performing a Read cycle, the Data Bus (ADOAD31) is sampled at the falling edge of PHI2 of the last T3
state. See Section 4. Data must, however, be held at least
until the beginning of T4. OS and RD are guaranteed not to
go inactive before this paint, so the rising edge of either of
them may safely be used to disable the device providing the
input data.
The T4 state finishes the bus cycle. At the beginning of T4,
the DS, RD or WR, and TSO signals go inactive, and at the
rising edge of PHI2, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles remains valid from the CPU throughout T4. Note that the Bus
Status lines (STO-ST3) change at the beginning of T4, anticipating the following bus cycle (if any).
During T2 the CPU switches the Data Bus, ADO-AD31 to
either accept or present data. It also starts the data strobe
(DS), signalling the beginning of the data transfer. Associated signals from the NS32201 Timing Control Unit are also
activated at this time: RD (Read Strobe) or WR (Write
Strobe), TSO (Timing State Output, indicating that T2 has
been reached) and DBE (Data Buffer Enable).
fiCiN I--~------I
024-031
ADO-AD23
NS32032
II
PHil
PHI2
iiSliiU:
os
PHil
PHI2
ADS
ODIN
DBE
AD
RDI-----------~
NS32201
WR
WRI-----------~
TSo
TsO~-----------.
TLlEE/5491-18
FIGURE 3·6. Bus Connections
2-249
....o r-----------------------------------------------------------------------------,
~
3.0 Functional Description (Continued)
o
~
rn
I
z
PHil
[
PHI 2
[
ADO-AD23
[
D24-D31
[
Aii§
[
STOoBT3
[
i5iiiN
[
iEO-lli
[
Os
[
RDY
[
T40RTi
I
NS32032 cpu BUS SIGNALS
T1
T2
T3
T4
I
Tl0RTI
I
AD [
DBE
[
rso[
TL/EE/5491-20
FIGURE 3-7. Read Cycle Timing
2·250
z
3.0 Functional Description
en
Co)
(Continued)
N
oCo)
NS32032 CPU BUS SIGNALS
T3
T4
I
Tl0RTi
'))
.....
I
o
Tl/EE/5491-19
FIGURE 3-8. Write Cycle Timing
2-251
3.0 Functional Description
(Continued)
3.4.1 Cycle Extension
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32032 provides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-7 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are fiat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the RDY (Ready) pin.
At the end of T2 on the falling edge of PHI2, the RDY line is
sampled by the CPU. If RDY is high, the nextT-states will be
T3 and then T4, ending the bus cycle. If RDY is low, then
another T3 state will be inserted after the next T -state and
the RDY line will again be sampled on the falling edge of
PHI2. Each additional T3 state after the first is referred to as
a "WAIT STATE". See Figure 3-9.
Tl
T2
The RDY pin is driven by the NS32201 Timing Control Unit,
which applies WAIT States to the CPU as requested on
three sets of pin:
1) CWAIT (Continuous WAIT), which holds the CPU in
WAIT states until removed.
2) WAIT1, WAIT2, WAIT4, WAITS (Collectively WAITn),
which may be given a four-bit binary value requesting a
specific number of WAIT States from 0 to 15.
3) PER (Peripheral), which inserts five additional WAIT
states and causes the TCU to reshape the RD and WR
strobes. This provides the setup and hold times required
by most MOS peripheral interface devices.
Combinations of these various WAIT requests are both legal
and useful. For details of their use, see the NS32201 Data
Sheet.
Figure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the TCU WAITn pins.
T3
I
(W~T)
I
T4
PHil
PHI2
RDY
TL/EE/5491-21
FIGURE 3·9. ROY Pin Timing
3.4.2 Bus Status
The NS32032 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on these
pins indicate why the CPU is performing a bus cycle, or, if it
is idle on the bus, then why is it idle.
To acknowledge receipt of a Maskable Interrupt
(on INT) it will read from address FFFE0016, expecting a vector number to be provided from the
Master NS32202 Interrupt Control Unit. If the
vectoring mode selected by the last SETCFG instruction was Non-Vectored, then the CPU will
ignore the value it has read and will use a default
vector instead, having assumed that no NS32202
is present. See Sec. 3.4.5.
0101 - Interrupt Acknowledge, Cascaded.
Referring to Figures 3-7 and 3-8, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1, and changing to the next state at T4. This allows
the system designer to fully decode the Bus Status and, if
desired, latch the decoded signals before ADS initiates the
Bus Cycle.
The Bus Status pins are interpreted as a four-bit value, with
STO the least significant bit. Their values decode as follows:
The CPU is reading a vector number from a Cascaded NS32202 Interrupt Control Unit. The address provided is the address of the NS32202
Hardware Vector register. See Sec. 3.4.5.
0110 - End of Interrupt, Master.
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt (RETI)
instruction. See Sec. 3.4.5.
0000 - The bus is idle because the CPU does not need
to perform a bus access.
0001 - The bus is idle because the CPU is executing the
WAIT instruction.
0010 - (Reserved for future use.)
0111 - End of Interrupt, Cascaded.
The CPU is reading from a Cascaded Interrupt
Control Unit to indicate that it is returning
(through RETI) from an interrupt service routine
requested by that unit. See Sec. 3.4.5.
0011 - The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100 - Interrupt Acknowledge, Master.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt
(on NMI) it will read from address FFFF0016, but
will ignore any data provided.
1000 - Sequential Instruction Fetch.
The CPU is reading the next sequential word
from the instruction stream into the Instruction
2-252
z
3.0 Functional Description
PREVo CYCLE
PHI2 [
N
N532032 CPU BUS SIGNALS
oCo)
NEXT CYCLE
~
....o
I (vl~n I (vlilT) I
I
iL~
- iLLiLiLIL~IL
IT40RTi I
PHil [
en
Co)
(Continued)
T1
I
T2
I
T3
T4
IT10RTi
Jl Jl J J Lf J}U1U1~
~ ~ ~ )--~ w ~
~---
~
ADO-AD23 [
024-031 [
I-
~ ~ ~ ~--~
W
~
DATAIN
---
V
ADS [
5T0-5T3 [
NEXT ADDR
VALID
.~~
V
~~
X
STATUS VALID
NEXT STATU 5
I~
~~ ~
~~
-
NEXT
VALID
1\
-j
NS32201 Teu CYCLE EXTENSION SIGNALS
t
CWAiT[ %: ~ rIM
t
t
~ V~ ~ ~ ~
~ ~ 'W I~ V.W
W
~~ ~ W& ~
t
~[ ~ t;::f@ ~ ~I~W:~V~ W% ~ %
1ft
ROY [
(TCUTOCPU)
INS32201 TL BUS SIGJLS
-V
Ii
-V
DBE [
T50 [
-~
_V
V
\
TL/EE/5491-22
FIGURE 3-10. Extended Cycle Example
Note: Arrows on CWAIT, PER, WAITn indicate pOints at which the TCU samples. Arrows on AOO-A015 and ROY indicate points at which the CPU samples.
2-253
C)
..-
N
C')
C)
N
~
Z
r-------------------------------------------------------------------------------------,
3.0 Functional Description
(Continued)
when BEO is low. The second bank, connected to data bus
pins AD8-AD15 is enabled when BE1 is low. The third and
fourth banks are enabled by BE2 and BE3, respectively.
See Figure 3-11.
Queue. It will do so whenever the bus would otherwise be idle and the queue is not already full.
1001 - Non-Sequential Instruction Fetch.
The CPU is performing the first fetch of instruction code after the Instruction Queue is purged.
This will occur as a result of any jump or branch,
or any interrupt or trap, or execution of certain
instructions.
1010 - Data Transfer.
The CPU is reading or writing an operand of an
instruction.
1011 - Read RMW Operand.
The CPU is reading an operand which will subsequently be modified and rewritten. If memory protection circuitry would not allow the following
Write cycle, it must abort this cycle.
1100 - Read for Effective Address Calculation.
The CPU is reading information from memory in
order to determine the Effective Address of an
operand. This will occur whenever an instruction
uses the Memory Relative or External addressing
mode.
1101 - Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing the Operation Word of a Slave Processor instruction. See Sec. 3.9.1.
TL/EE/5491-23
1110 - Read Slave Processor Status.
FIGURE 3·11. Memory Interface
Since operands do not need to be aligned with respect to
the double-word bus access performed by the CPU, a given
double-word access can contain one, two, three, or four
bytes of the operand being addressed, and these bytes can
begin at various positions, as determined by A1, AO. Table
3-1 lists the 10 resulting access types.
The CPU is reading a Status Word from a Slave
Processor. This occurs after the Slave Processor
has signalled completion of an instruction. The
transferred word tells the CPU whether a trap
should be taken, and in some instructions it presents new values for the CPU Processor Status
Register bits N, Z, L or F. See Sec. 3.9.1.
TABLE 3·1
Bus Access Types
Type BytesAccessed A1,AO BE3 BE2 BE1 BEO
00
1
1
1
0
01
1
0
2
10
1
3
0
11
0
1
4
00
0
0
5
2
2
01
1
0
0
6
10
1
1
0
0
?
2
8
3
00
0
0
0
3
01
0
0
1
9
0
10
4
00
0
0
0
0
1111 - Broadcast Slave ID.
The CPU is initiating the execution of a Slave
Processor instruction. The ID Byte (first byte of
the instruction) is sent to all Slave Processors,
one of which will recognize it. From this point the
CPU is communicating with only one Slave Processor. See Sec. 3.9.1.
3.4.3 Data Access Sequences
The 24-bit address provided by the NS32032 is a byte address; that is, it uniquely identifies one of up to 16,777,216
eight-bit memory locations. An important feature of the
NS32032 is that the presence of a 32-bit data bus imposes
no restrictions on data alignment; any data item, regardless
01 size, may be placed starting at any memory address. The
NS32032 provides special control Signals. Byte Enable
(BEO-BE3) which facilitate individual byte accessing on a
32-bit bus.
Memory is organized as four eight-bit banks, each bank receiving the double-word address (A2-A23) in parallel. One
bank, connected to Data Bus pins ADO-AD? is enabled
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-States separating
them. The number of bus cycles required to transfer an operand depends on its size and its alignment. Table 3-2 lists
the bus cycles performed for each situation.
2-254
,----------------------------------------------------------------------, zU)
3.0 Functional Description (Continued)
(0)
I\)
o
....
(0)
I\)
TABLE 3·2
Access Sequences
o
Data Bus
I
Cycle
Type
Address
'\
Byte 3
Byte 2
Byte 0
X
X
X
A. Word at address ending with 11
1.
2.
4
A
A+1
9
A
A+3
0
o
7
A
2.
S
A+2
0
0
1
0
1
0
Byte 2
X
0
Byte 1
X
4
8
A
A+1
0
0
Byte 0
X
o
0
Byte 0
X
X
Byte 3
X
Byte 2
X
Byte 3
X
Byte 2
X
Byte 1
Byte 3
Byte 2
Byte 1
Byte 0
0
Byte 7
Byte 6
ByteS
Byte 4
2-2SS
BYTE 41 BYTE 31 BYTE 2/ BYTE 11 BYTE 0 I +- A
1
Byte 2
Byte 1
Byte 0
X
X
X
X
Byte 3
1
0
Byte 6
X
Byte S
X
Byte 4
X
X
Byte 7
sl
BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 0
I +-
1
Byte 1
Byte 0
X
X
o
X
X
Byte 3
Byte 2
0
Byte S
X
Byte 4
X
X
Byte 7
X
Byte 6
I BYTE 71 BYTE 61 BYTE
1.
4
A
0
1
1
2.
8
A+1
0
0
Other bus cycles (instruction prefetch or slave) can occur here.
1.
4
A+4
0
1
1
2.
0
8
A+S
0
X = Don't Care
sl
o
I BYTE 71 BYTE 61 BYTE
1.
A
o
o
1
7
2.
A+2
1
o
S
Other bus cycles (instruction prefetch or slave) can occur here.
3.
7
A+ 4
0
0
1
4.
S
A+ 6
0
H. Quad word at address endIng wIth 11
X
Byte 3
o
I BYTE 71 BYTE 61 BYTE
1.
9
A
o
o
o
2.
A+3
Other bus cycles (instruction prefetch or slave) can occur here.
3.
9
A+ 4
0
0
0
4.
1
A+ 7
1
1
G. Quad word at address endIng wIth 10
Byte 0
X
I BYTE 71 BYTE 61 BYTE SIBYTE 41 BYTE 3/BYTE 21 BYTE 11 BYTE 01 +- A
10
A
o
o
o
Other bus cycles (instruction prefetch or slave) can occur here.
2.
10
A+ 4
0
0
0
1.
F. Quad word at address ending with 01
Byte 1
X
IBYTE31BYTE21BYTE11BYTEOI +- A
o
E. Quad word at address ending with 00
X
Byte 1
I BYTE 31 BYTE 21 BYTE 1 1BYTE 01 +- A
0
D. Double word at address ending with 11
1.
2.
X
X
IBYTE31BYTE21BYTE11BYTEOI +- A
C. Double word at address ending with 10
1.
Byte 0
IBYTE11BYTEOI +- A
o
B. Double word at address ending with 01
1.
2.
Byte 1
sl
A
BYTE 41 BYTE 31 BYTE 21 BYTE 11 BYTE 0 I +- A
0
Byte 0
X
X
Byte 3
X
Byte 2
X
Byte 1
0
Byte 4
X
X
Byte 7
X
Byte 6
X
ByteS
•
3.0 Functional Description
(Continued)
3.4.3.1 Bit Accesses
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full. Sequential Fetches are always
type 10 Read cycles (Table 3-1).
The Bit Instructions perform byte accesses to the byte con·
taining the designated bit. The Test and Set Bit instruction
(SBIT), for example, reads a byte, alters it, and rewrites it,
having changed the contents of one bit.
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the instruction queue, causing the
next instruction fetch to display Non-Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status, and that cycle depends on the destination address.
3.4.3.2 Bit Field Accesses
An access to a Bit Field in memory always generates a Dou·
ble-Word transfer at the address containing the least significant bit of the field. The Double Word is read by an Extract
instruction; an Insert instruction reads a Double Word, modifies it, and rewrites it.
Note: During non·sequential fetches, BEO-BE3 are all active regardless of
the alignment.
3.4.3.3 Extending Multiply Accesses
The Extending Multiply Instruction (MEl) will return a result
which is twice the size in bytes of the operand it reads. If the
multiplicand is in memory, the most-significant half of the
result is written first (at the higher address), then the leastsignificant half. This is done in order to support retry if this
instruction is aborted.
3.4.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is interrupt control rather
than the transfer of instructions or data. Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status pesented on pins STO-ST3. All
Interrupt Control cycles are single-byte Read cycles.
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine. For full details of the NS32032 interrupt
structure, see Sec. 3.B.
3.4.4 Instruction Fetches
Instructions for the NS32032 CPU are "prefetched"; that is,
they are input before being needed into the next available
entry of the eight-byte Instruction Queue. The CPU performs
two types of Instruction Fetch cycles: Sequential and NonSequential. These can be distinguished from each other by
their differing status combinations on pins STO-ST3 (Sec.
3.4.2).
2-256
z
3.0 Functional Description
(f)
Co)
(Continued)
N
oCo)
TABLE 3·3
Interrupt Sequences
N
....
I
o
Data Bus
r
Cycle
Status
Address
ODIN
BE3
BE2
BE1
BED
\
Byte 3
Byte 2
Byte 1
Byte 0
X
X
X
A. Non-Maskable Interrupt Control Sequences
Interrupt Acknowledge
1
0100
FFFF0016
o
o
x
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
B. Non- Vectored Interrupt Control Sequences
Interrupt Acknowledge
1
0100
FFFE00 16
0
0
X
X
X
X
Interrupt Return
0110
1
0
0
X
X
X
X
FFFE0016
C. Vectored Interrupt Sequences: Non-Cascaded.
Interrupt Acknowledge
1
0100
FFFE0016
0
0
X
X
X
Vector:
Range: 0-127
Interrupt Return
1
0110
0
0
X
X
X
Vector: Same as
in Previous In!.
Ack. Cycle
X
X
Cascade Index:
range -16to-1
FFFE0016
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
1
0100
FFFE0016
o
o
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
0
See Note
Address
Interrupt Return
1
0110
FFFE0016
o
Vector, range 9-255; on appropriate byte of
data bus.
o
(The CPU here uses the Cascade Index to find the Cascade Address)
0111
Cascade
0
See Note
2
Address
X
X
X
X
X
X
X
Cascade Index:
Same as in
previous In!.
Ack. Cycle
X
X = Don't Care
Note: BEO-BE3 signals will be activated according to the cascaded
leu address. The cycle type can be 1, 2, 3 or 4, when reading the interrupt vector. The vector
value can be in the range 0-255.
2·257
C)
..N
~
(J)
Z
r---------------------------------------------------------------------------------,
3.0 Functional Description (Continued)
3.4.6 Slave Processor Communication
In addition to its use as the Address Translation strap (Sec.
3.5.1), the AT/SPC pin is used as the data strobe for Slave
Processor transfers. In this role, it is referred to as Slave
Processor Control (SPC). In a Slave Processor bus cycle,
data is transferred on the Data Bus (ADO-AD15), and the
status lines (STO-ST3) are monitored by each Slave Processor in order to determine the type of transfer being performed. SPC is bidirectional, but is driven by the CPU during
all Slave Processor bus cycles. See Sec. 3.9 for full protocol
sequences.
A
AD«()'15)
"
AT/SPC
...
v
D(M5)
SPC
SLAVE
PROCESSOR
NS32D32
CPU
STO-ST3
5TO-ST3
TL/EE/5491-24
FIGURE 3-12. Slave Processor Connections
NEXT CYCLE
PREY.CVCLE
I
PHil
[
PHil
[
T40rTi
TI
T4
TIORTI
I
8TII-8T3 [
_<31[
OBE
TLlEE/5491 -25
Nota:
(1) ('oU samples Data Bus here.
(2) DBE and ali other NS32201 TCU bus signals remain Inactive because no ADS pulse is received from the CPU.
FIGURE 3-13. CPU Read from Slave Processor
2-258
z
3.0 Functional Description
en
Co:!
(Continued)
I\)
3.4.6.1 Slave Processor Bus Cycles
3.4.6.2 Slave Operand Transfer Sequences
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3·13 and 3·14). Dur·
ing a Read cycle SPC is active from the beginning of T1 to
the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock peri·
od, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
Since the CPU does not pulse the Address Strobe (ADS),
no bus signals are generated by the NS32201 Timing Control Unit. The direction of a transfer is determined by the
sequence ("protocol") established by the instruction under
execution; but the CPU indicates the direction on the DDIN
pin for hardware debugging purposes.
A Slave Processor operand is transferred in one or more
Slave bus cycles. A By1e operand is transferred on the
least-significant byte of the Data Bus (ADO-AD7), and a
Word operand is transferred on bits ADO-AD15. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-significant word to most·significant.
Note that the NS32032 uses only the two least significant
by1es of the data bus for slave cycles. This is to maintain
compatibility with existing slave processors.
PREV.CYCLE
I
PHil
[
§PC
[
ADO-AD15 [
T40RTI
.-'f'""'".......'"'-'fJ
o
Co:!
~
......
o
NEXT CYCLE
T1
T4
TIORTi
I
~--+----r ~_-+_
STG-ST3 [
•
ADs [
_(2)[
DBE
- '_ _J
TL/EE/5491-26
Note:
(I) Slave Processor samples Data Bus here.
(2) DBE. being provided by the NS32201 TCU. remains inactive due to the lact that no pulse is presented on ADS. TCU signals RD. WR and TSO also remain
inactive.
FIGURE 3·14. CPU Write to Slave Processor
2-259
C)
..-
i
en
z
r---------------------------------------------------------------------------------~
3.0 Functional Description (Continued)
3.5 MEMORY MANAGEMENT OPTION
is sampled as high, the bus timing is as previously described
in Sec. 3.4. If it is sampled as low, two changes occur:
The NS32032 CPU, in conjunction with the NS32082 Memory Management Unit (MMU), provides full support for address translation, memory protection, and memory allocation techniques up to and including Virtual Memory.
1) An extra clock cycle, Tmmu, is inserted into all bus cycles except Slave Processor transfers.
2) The DS/FLT pin changes in function from a Data Strobe
output (OS) to a Float Command input (FL
n.
3.5.1 Address Translation Strap
The NS32082 MMU will itself pull the CPU AT/SPC pin low
when it is reset. In non-Memory-Managed systems this pin
should be pulled up to Vee through a 10 k.!l resistor.
The Bus Interface Control section of the NS32032 CPU has
two bus timing modes: With or Without Address Translation.
The mode of operation is selected by the CPU by sampling
the AT /SPC (Address Translation/Slave Processor Control)
pin on the rising edge of the RST (Reset) pulse. If AT/SPC
I
PHI 1
[
PHil
[
T40Rn
I
Note that the Address Translation strap does not specifically declare the presence of an NS32082 MMU, but only the
T1
ADD-ADla [
014-031 [
ADS
[
STO-ST3
[
ODiN
[
iiEo"-iiii
[
ROY
[
TL/EE/5491-27
FIGURE 3-15. Read Cycle with Address Translation (CPU Action)
2-260
r--------------------------------------------------------------------------,
3.0 Functional Description
N
NS320B2 MMU to operate correctly it must be set to the
32032 mode by forcing A24/HBF low during reset. In this
mode the bus lines ADI6-AD23 are floated after the MMU
address has been latched, since they are used by the CPU
to transfer data.
Figures 3·17and 3·18 show a Read cycle and a Write cycle
as generated by the 32032/320B2/32201 group. Note that
with the CPU ADS signal gOing only to the MMU, and with
the MMU PAY signal substituting for ADS everywhere else,
Tmmu through T4 look exactly like Tl through T4 in a non·
Memory·Managed system. For the connection diagram, see
Appendix B.
3.5.2 Translated Bus Timing
Figures 3·15 and 3·16 illustrate the CPU activity during a
Read cycle and a Write cycle in Address Translation mode.
The additional T·State, Tmmu, is inserted between Tl and
T2. During this time the CPU places ADO-AD23 into the
TRI·STATE® mode, allowing the MMU to assert the trans·
lated address and issue the physical address strobe PAY.
T2 through T 4 of the cycle are identical to their counterparts
without Address Translation. Note that in order for the
I
PHil
T4 OR TI
I
Tl
Z
U)
Co)
(Continued)
presence of external address translation circuitry. MMU in·
structions will still trap as being undefined unless the
SETCFG (Set Configuration) instruction is executed to de·
clare the MMU instruction set valid. See Sec. 2.1.3.
Tmmu
I
fa
T3
T4
I
Tl0RTI
oCo)
~
.....
o
I
[
PHI 2
ADO-AD23
[
D24-D31
[
ADS
[
DoiN
[
BEo-iiEi
[
RDY
•
STATUS VALID
STD-ST3 [
[
TLlEE/5491-28
FIGURE 3·16. Write Cycle with Address Translation (CPU Action)
2·261
....o r-----------------------------------------------------------------------------,
~
COl)
3.0 Functional Description (Continued)
o
I
C'oI
~
T40RTi
I
T1
I
Trnmu
I
T2
T3
T4
I
TlORTi
I
Z
PHIl [
PHIZ
ADO-AD23
D24-D3l
[
[
[
Aoi[
PiV[
STO-8T3 [
OliN
[~~~~~~--+-----~----~------r_~--~----_t_
BEo-iia [
iSO[
TL/EE/5491-29
FIGURE 3-17. Memory-Managed Read Cycle
2-262
3.0 Functional Description
I
PHil
[
T40RTi
I
(Continued)
Tl
I
T2
Tmmu
T3
T4
I
TlORTi
I
PHI 2 [
ADO-A023 [
024-031 [
AiiS[
PiV[
STO·ST3 [
NEXT STATUS
STATUS VALlO
00iN[
BEo-iiEi [
VALID
ROY [
NS32201 Teu BUS SIGNALS
iiii[
DBE [
TL/EE/5491-30
FIGURE 3-18. Memory-Managed Write Cycle
2·263
o
.....
2
z
en
3.0 Functional Description
(Continued)
3.5.3 The FLT (Float) Pin
1) Sets AOO-A023, 024-031 and ODIN to the TRI-STATE
condition ("floating").
2) Suspends further internal processing of the current instruction. This ensures that the current instruction remains abortable with retry. (See RST/ABT description,
Sec. 3.5.4.)
The FLT pin is used by the CPU for address translation
support. Activating FLT during Tmmu causes the CPU to
wait longer than Tmmu for address translation and validation. This feature is used occasionally by the NS32082 MMU
in order to update its translation look-aside buffer (TLB)
from page tables in memory, or to update certain status bits
within them.
Note that the AOO-A023 pins may be briefly asserted during the first idle T-State. The above conditions remain in
effect until FLT again goes high. See the Timing Specifications, Sec. 4.
Figure 3-19 shows the effect of FLT. Upon sampling FLT
low, late in Tmmu, the CPU enters idle T-States (Tf) during
which it:
Tl
TI
TI
TI
T2
PHil [
PHI2 [
AOO-A023
024-031
[
[-t----t'
ADs
[
PAV
[
FLT
[
STO·ST3 [
ODIN
[
BEO-BE3
[
TL/EE/5491-31
FIGURE 3-19. FLT Timing
2-264
3.0 Functional Description
(Continued)
2) If FLT has been applied to the CPU, the Abort pulse must
be applied before the T-State in which FLT goes inactive.
The CPU will not actually respond to the Abort command
until FLT is removed. See Figure 4-23.
3.5.4 Aborting Bus Cycles
The RSTI ABT pin, apart from its Reset function (Sec. 3.3),
also serves as the means to "abort", or cancel, a bus cycle
and the instruction, if any, which initiated it. An Abort request is distinguished from a Reset in that the RSTI ABT pin
is held active for only one clock cycle.
3) The Write half of a Read-Modify·Write operand access
may not be aborted. The CPU guarantees that this will
never be necessary for Memory Management functions
by applying a special RMW status (Status Code 1011)
during the Read half of the access. When the CPU presents RMW status, that cycle must be aborted if it would
be illegal to write to any of the accessed addresses.
If RSTI ABT is pulsed at any time other than as indicated
above, it will abort either the instruction currently under execution or the next instruction and will act as a very high-priority interrupt. However, the program that was running at the
time is not guaranteed recoverable.
If RSTI ABT is pulled low during Tmmu or Tf, this signals
that the cycle must be aborted. The CPU itself will enter T2
and then Ti, thereby terminating the cycle. Since it is the
MMU PAY signal which triggers a physical cycle, the rest of
the system remains unaware that a cycle was started.
The NS32082 MMU will abort a bus cycle for either of two
reasons:
1) The CPU is attempting to access a virtual address which
is not currently resident in physical memory. The referenced page must be brought into physical memory from
mass storage to make it accessible to the CPU.
2) The CPU is attempting to perform an access which is not
allowed by the protection level assigned to that page.
3.6 BUS ACCESS CONTROL
The NS32032 CPU has the capability of relinquishing its
access to the bus upon request from a DMA device or another CPU. This capability is implemented on the HOLD
(Hold Request) and HLDA (Hold Acknowledge) pins. By asserting HOLD low, an external device requests access to
the bus. On receipt of HLDA from the CPU, the device may
perform bus cycles, as the CPU at this point has set the
ADO-AD23, D24-D31, ADS, DDIN and BEO-BE3 pins to
the TRI-STATE condition. To return control of the bus to the
CPU, the device sets HOLD inactive, and the CPU acknowledges return of the bus by setting HLDA inactive.
When a bus cycle is aborted by the MMU, the instruction
that caused it to occur is also aborted in such a manner that
it is guaranteed re-executable later. The information that is
changed irrecoverably by such a partly-executed instruction
does not affect its re-execution.
3.5.4.1 The Abort Interrupt
Upon aborting an instruction, the CPU immediately performs
an interrupt through the ABT vector in the Interrupt Table
(see Sec. 3.8). The Return Address pushed on the Interrupt
Stack is the address of the aborted instruction, so that a
Return from Trap (RETI) instruction will automatically retry
it.
The one exception to this sequence occurs if the aborted
bus cycle was an instruction prefetch. If so, it is not yet
certain that the aborted prefetched code is to be executed.
Instead of causing an interrupt, the CPU only aborts the bus
cycle, and stops prefetching. If the information in the Instruction Queue runs out, meaning that the instruction will
actually be executed, the ABT interrupt will occur, in effect
aborting the instruction that was being fetched.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-20 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-21 shows the sequence
if the CPU is using the bus at the time that the HOLD request is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T 4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
3.5.4.2 Hardware Considerations
In order to guarantee instruction retry, certain rules must be
followed in applying an Abort to the CPU. These rules are
followed by the NS32082 Memory Management Unit.
In a Memory-Managed system, the HLDA signal is connected in a daisy-chain through the NS32082, so that the MMU
can release the bus if it is using it.
1) If FLT has not been applied to the CPU, the Abort pulse
must occur during or before Tmmu. See the Timing Specifications, Figure 4-22.
2·265
...Nor---------------------------------------------------------------______
3.0 Functional Description
(Continued)
CO)
o
iz
Ti
PHI2
Ti
Ti
TI 011 T4
I
TiOIlTl
I
[
H6L6[
HLDi[
I
AFFECTEO SIGNALS
~~------
iDs [
---- ~r---- -----
DDIN[
BEO-BE3
------- -------
[-+___+-__-+'
STO-ST3 [
NEXT
NEXT
PIIEVIOUS
TLlEE/5491-32
FIGURE 3-20. HOLD Timing, Bus Initially Idle
2-266
~
3.0 Functional Description
(Continued)
PHll[
PHI 2 [
HOLD [
HLDA[
AFFECTED SIGNALS
ADS[
Di[
ODIN [
BEO-BE3[
ADO-AD23[
024-031 [
---
1~---
---- ---NEXT
VALID
VALID
-- 1r--- ---- ---
---
~---
NEXTADDR
---- ---- ---- ----
STo-ST3[
TL/EE/5491-33
FIGURE 3·21. HOLD Timing, Bus Initially Not Idle
2-267
fII
o
....
.-----------------------------------------------------------------------------~
N
CO)
3.0 Functional Description
IN
3.7 INSTRUCTION STATUS
&J
z
In addition to the four bits of Bus Cycle status (STO-ST3),
the NS32032 CPU also presents Instruction Status informa·
tion on three separate pins. These pins differ from STOST3 in that they are synchronous to the CPU's internal in·
struction execution section rather than to its bus interface
section.
o
(Continued)
In addition there is a set of internally-generated "traps"
which cause interrupt service to be performed as a result
either of exceptional conditions (e.g., attempted division by
zero) or of specific instructions whose purpose is to cause a
trap to occur (e.g., the Supervisor Call instruction).
3.8.1 Generallnterrupt/Trap Sequence
Upon receipt of an interrupt or trap request, the CPU goes
through three major steps:
PFS (Program Flow Status) is pulsed low as each instruction
begins execution. It is intended for debugging purposes, and
is used that way by the NS32082 Memory Management
Unit.
U/S originates from the U bit of the Processor Status Regis·
ter, and indicates whether the CPU is currently running in
User or Supervisor mode. It is sampled by the MMU for
mapping, protection, and debugging purposes. Although it is
not synchronous to bus cycles, there are guarantees on its
validity during any given bus cycle. See the Timing Specifications, Figure 4-21.
ILO (Interlocked Operation) is activated during an SBIT! (Set
Bit, Interlocked) or CBITI (Clear Bit, Interlocked) instruction.
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the semaphore primitive operations for multi-processor communication and resource sharing. As with the U/S pin, there are
guarantees on its validity during the operand accesses performed by the instructions. See the Timing Specification
Section, Figure 4-19.
1) Adjustment of Registers.
Depending on the source of the interrupt or trap, the CPU
may restore and/or adjust the contents of the Program
Counter (PC), the Processor Status Register (PSR) and
the currently-selected Stack Pointer (SP). A copy of the
PSR is made, and the PSR is then set to reflect Supervisor Mode and selection of the Interrupt Stack.
2) Vector Acquisition.
A Vector is either obtained from the Data Bus or is supplied by default.
3) Service Call.
The Vector is used as an index into the Interrupt Dispatch
Table, whose base address is taken from the CPU Interrupt Base (INTBASE) Register. See Figure 3-22. A 32-bit
External Procedure Descriptor is read from the table entry, and an External Procedure Call is performed using it.
The MOD Register (16 bits) and Program Counter (32
bits) are pushed on the Interrupt Stack.
This process is illustrated in Figure 3-23, from the viewpoint
of the programmer.
3.8 NS32032 INTERRUPT STRUCTURE
INT, on which maskable interrupts may be requested,
NMI, on which non-maskable interrupts may be requested,and
RST/ ABT, which may be used to abort a bus cycle and
any associated instruction. See Sec. 3.5.4.
, ...
MEMORY
/
CASCADE TABLE
, ...
~'"'
~~1
NVI
0
NON·VECTDRED INTERRUPT
CASCADE ADDR 0
;:::::
I""_m..~1
REGISTER
~
I
·
•
CASCADE ADDR 14
CASCADE ADDR 15
FIXED INTERRUPTS
AND TRAPS
VECTORED
1
~~
INTERRUPTS
i
:r
DISPATCH TABLE
1
NMI
N DN·MASKABLE INTERRUPT
2
ABT
A BORT
3
SLAVE
SLAVE PROCESSOR TRAP
4
ILL
I LLEGAL OPERATION TRAP
5
SVC
S UPERVISOR CALL TRAP
6
DVZ
DIVIDE BY ZERO TRAP
7
FLG
FLAG TRAP
8
BPT
B REAKPOINT TRAP
9
TRC
T RACE TRAP
10
UNO
U NDEFINED INSTRUCTION TRAP
'1-15 :: ~ RESERVED
,6
,. ....
~
VECTORED
INTERRUPTS
A.
TLlEE/549, -34
FIGURE 3-22. Interrupt Dispatch and Cascade Tables
2-268
3.0 Functional Description (Continued)
I
I
I (PUSH)
RETURN ADORESS
32 BITS
I
STATUS
PSR
I
MOOUlE
\
I
J (PUSH)
32 BITS
MOD
INTERRUPT
STACK
TlfEEf5491-35
r-------------,
I
I
I
I
I
I
INTBASE REGISTER
CASCADE TABLE
I
I
DISPATCH
TABLE
DESCRIPTOR (32 BITS)
I ."
DESCRIPTOR
o----16--_·'I"I~---16---·1
OFFSET
MODULE
0
MOD REGISTER ~
I
MODULE TABLE
NEW MODULE
I
MODULE TABLE ENTRY
PI
j
MODULE TLlE ENTRY
32
- ----..,
STATIC BASE POINTER
UNK BASE POINTER
(+
PROGRAM BASE POINTER
(RESERVED)
PROGRAM COUNTER
SBREGISTER
4-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3·23. Interrupt/Trap Service Routine Calling Sequence
2·269
I
TlfEEf5491-36
o r--------------------------------------------------------------------------....
N
('I)
o
3.0 Functional Description (Continued)
C\I
3.8.2 Interrupt/Trap Return
o
To return control to an interrupted program, one of two in·
structions is used. The RETT (Return from Trap) instruction
(Figure 3-24) restores the PSR, MOD, PC and S8 registers
to their previous contents and, since traps are often used
deliberately as a call mechanism for Supervisor Mode procedures, it also discards a specified number of bytes from
the original stack as surplus parameter space. RETT is used
to return from any trap or interrupt except the Maskable
Interrupt. For this, the RETI (Return from Interrupt) instruction is used, which also informs any external Interrupt Control Units that interrupt service has completed. Since interrupts are generally asynchronous external events, RETI
does not pop parameters. See Figure 3-25.
('I)
z
The input is maskable, and is therefore enabled to generate
interrupt requests only while the Processor Status Register I
bit is set. The I bit is automatically cleared during service of
an INT, NMI or Abort request, and is restored to its original
setting upon return from the interrupt service routine via the
RETT or RETI instruction.
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I = C) or Vectored (bit I = 1).
3.8.3.1 Non-Vectored Mode
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
3.8.3 Maskable Interrupts (The INT Pin)
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests.
PROGRAM COUNTER
RETURN ADDRESS
STATUS
PSR
I
•
I
~ 32 BITS
(POP)
1----------1
(POP)
MODULE
-\-----..:..---+-
MOD
32 BITS
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
MODULET~BLEENTRY
STATIC BASE POINTER
-
,..,
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
PARAMETERS
/
n
BYTES
SBREGISTER
STATIC BASE
+
STACK SELECTED
IN NEWLY·
POPPEDPSR.
POP AND
DISCARD
FIGURE 3-24. Return from Trap (RETT n) Instruction Flow
2-270
TL/EE/5491-37
z
3.0 Functional Description
en
w
(Continued)
~
w
~
....
"END OF INTERRUPT'
Q
BUS CYCLE
INTERRUPT
CONTROL
UNIT
PROGRAM COUNTER
(POP)
RETURN ADDRESS
STATUS
J
(POP)
MODULE
PSR
MOD
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
J
MODULE TAllE ENTRY
STATIC BASE POINTER
-
r----
liNK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STATIC BASE
SBREGISTER
TLlEE/5491-39
FIGURE 3-25. Return from Interrupt (RETI) Instruction Flow
2-271
...N
Q
~
CO)
en
z
r---------------------------------------------------------------------------------~
3.0 Functional Description
(Continued)
Figure 3-22 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32·bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle
(Sec. 3.4.2), reading the final vector value. This vector is
interpreted by the CPU as an unsigned byte, and can therefore be in the range of 0 through 255.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle (Sec. 3.4.2), where·
upon the Master ICU again provides the negative Cascade
Table index. The CPU, seeing a negative value, uses it to
find the corresponding Cascade Address from the Cascade
Table. Applying this address, it performs an "End of Interrupt, Cascaded" bus cycle (Sec. 3.4.2), informing the Cascaded ICU of the completion of the service routine. The byte
read from the Cascaded ICU is discarded.
3.8.3.2 Vectored Mode: Non-Cascaded Case
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize up to 16 interrupt requests. Upon receipt of an interrupt request on the INT pin, the CPU performs an "Interrupt Acknowledge, Master" bus cycle (Sec.
3.4.2) reading a vector value from the low-order byte of the
Data Bus. This vector is then used as an index into the
Dispatch Table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI) instruction, which performs an End of Interrupt
bus cycle, informing the ICU that it may re-prioritize any interrupt requests still pending. The ICU provides the vector
number again, which the CPU uses to determine whether it
needs also to inform a Cascaded ICU (see below).
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
3.8.3.3 Vectored Mode: Cascaded Case
In order to allow up to 256 levels of interrupt, provision is
made both in the CPU and in the NS32202 Interrupt Control
Unit (lCU) to transparently support cascading. Figure 3-27,
shows a typical cascaded configuration. Note that the Interrupt output from a Cascaded ICU goes to an Interrupt Re·
quest input of the Master ICU, which is the only ICU which
drives the CPU INT pin.
In a system which uses cascading, two tasks must be performed upon initialization:
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number (0 to 15) on which it
receives the cascaded requests.
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit in the Interrupt Mask Register of the Interrupt Con·
troller.
However, if an interrupt is set pending during the CPU instruction that
masks off that interrupt, the CPU may still perform an interrupt ac·
knowledge cycle following that instruction since it might have sampled
the INT line before the ICU deasserted it. This could cause the ICU to
2) A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (INTBASE) Register. Its entries are 32-bit addresses, pOinting
to the Vector Registers of each of up to 16 Cascaded
ICUs.
provide an invalid vector. To avoid this problem the above operation
should be performed with the CPU interrupt disabled.
HARDWARE
INTERRUPTS
OR
CASCADED
CONTROLLERS
NS32032
CPU
GROUP
INf \-------1
INTERRUPTS,
CASCADED,
OR
BIT 110
TLIEE/5491-40
FIGURE 3-26. Interrupt Control Unit Connections (16 Levels)
2-272
z
3.0 Functional Description
en
w
(Continued)
N
Q
W
...
DATA
~
Q
CONTROL
ADDR5BITS
CASCADED
N532202
ICU
HARDWARE
INTERRUPTS
STATUS
FROM
ADDRESS
DECODER
INTERRUPTS
OR
BIT 1/0
DATA
CONTROL
NS32032
CPU
GROUP
--
MASTER
N532202
ICU
ADDR
STATUS 1
INT
~----------------------------------1~
II
FROM
ADDRESS
DECODER
TL/EE/5491-41
FIGURE 3-27. Cascaded Interrupt Control Unit Connections
3.8.4 Non-Maskable Interrupt (The NMI Pin)
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Sec. 3.4.2)
when processing of this interrupt actually begins. The Interrupt Acknowledge cycle differs from that provided for Maskable Interrupts in that the address presented is FFFF0016.
The vector value used for the Non-Maskable Interrupt is
taken as 1, regardless of the value read from the bus.
3.8.STraps
A trap is an internally-generated interrupt request caused as
a direct and immediate result of the execution of an instruction. The Return Address pushed by any trap except Trap
(TRC) is the address of the first byte of the instruction during
which the trap occurred. Traps do not disable interrupts. as
they are not associated with external events. Traps recognized by the NS32032 CPU are:
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Sec. 3.9.1).
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
For the full sequence of events in processing the NonMaskable Interrupt, see Sec. 3.8.7.1.
2-273
3.0
Functional Description (Continued)
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
1. If a String instruction was interrupted and not yet completed:
Trap (SYC): The Supervisor Call (SVC) instruction was executed.
Trap (DYZ): An attempt was made to divide an integer by
zero. (The slave trap is used for Floating Point division by
zero.)
a. Clear the Processor Status Register P bit.
b. Set "Return Address" to the address of the first byte of
the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and J.
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
Trap (BPn: The Breakpoint (BPT) instruction was executed.
Trap (TRC): The instruction just completed is being traced.
See below.
3. If the interrupt is Non-Maskable:
a. Read a byte from address FFFF0016, applying Status
Code 0100 (Interrupt Acknowledge, Master, Sec.
3.4.2). Discard the byte read.
Trap (UNO): An undefined opcode was encountered by the
CPU.
A special case is the Trace Trap (TRC), which is enabled by
setting the T bit in the Processor Status Register (PSR). At
the beginning of each instruction, the T bit is copied into the
PSR P (Trace "Pending") bit. If the P bit is set at the end of
an instruction, then the Trace Trap is activated. If any other
trap or interrupt request is made during a traced instruction,
its entire service procedure is allowed to complete before
the Trace Trap occurs. Each interrupt and trap sequence
handles the P bit for proper tracing, guaranteeing one and
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
b. Set "Yector" to 1.
c. Go to Step B.
4. If the interrupt is Non-Vectored:
a. Read a byte from address FFFF0016, applying Status
Code 0100 (Interrupt Acknowledge, Master: Sec.
3.4.2). Discard the byte read.
b. Set "Vector" to
c. Go to Step 8.
5. Here the interrupt is Vectored. Read "Byte" from address
FFFE0016, applying Status Code 0100 (Interrupt Acknowledge, Master: Sec. 3.4.2).
6. If "Byte" ~ 0, then set "Vector" to "Byte" and go to Step
B.
3.8.6 Prioritization
The NS32016 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
(Highest priority)
7. If "Byte" is in the range -16 through -1, then the interrupt source is Cascaded. (More negative values are reserved for future use.) Perform the following:
a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE +4' Byte.
b. Read "Vector," applying the Cascade Address just
read and Status Code 0101 (Interrupt Acknowledge,
Cascaded: Sec. 3.4.2).
B. Push the PSR copy (from Step 2) onto the Interrupt Stack
as a 16-bit value.
9. Perform Service (Vector, Return Address), Figure 3-28.
2) Abort
3) Non-Maskable Interrupt
4) Maskable Interrupts
5) Trace Trap
o.
(Lowest priority)
3.8.7 Interrupt/Trap Sequences: Detailed Flow
For purposes of the following detailed discussion of interrupt and trap service sequences, a Single sequence called
"Service" is defined in Figure 3-28. Upon detecting any interrupt request or trap condition, the CPU first performs a
sequence dependent upon the type of interrupt or trap. This
sequence will include pushing the Processor Status Register and establishing a Vector and a Return Address. The
CPU then performs the Service sequence.
For the sequence followed in processing either Maskable or
Non-Maskable interrupts (on the INT or NMI pins, respectively), see Sec. 3.B. 7.1 For Abort Interrupts, see Sec.
3.B.7.4. For the Trace Trap, see Sec. 3.B.7.3, and for all
other traps see Sec. 3.B.7.2.
Service (Vector, Return Address):
1) Read the 3l1-blt External Procedure Descriptor from the Interrupt
Dispatch Table: address Is Vector' 4 + INTBASE Register contents.
2) Move the Module field of the Descriptor Into the MOD Register.
3) Read the new StaUc Base pointer from the memory address contained In MOD, placing It Into the SB Register.
4) Read the Program Base pointer from memory address MOD + 8,
and add to It the Offset field from the Descriptor, placing the result
In the Program Counter.
5) Flush queue: Non-sequentlally fetch first InstrucUon of Interrupt
routine.
6) Push MOD Register Into the Interrupt Stack as a 16·blt value. (The
PSR has already been pushed as a 16·blt value.)
3.8.7.1 Maskable/Non-Maskable Interrupt Sequence
7) Push the Return Address onto the Interrupl Stack as a 32·bll quanti·
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, at the next interruptible pOint during its execution.
ty.
FIGURE 3·28. Service Sequence
Invoked during all interrupt/trap sequences.
2-274
3.0 Functional Description
z
en
CAl
(Continued)
N
Each Slave Instruction Set is validated by a bit in the Configuration Register (Sec. 2.1.3). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
3.8.7.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector" to the value corresponding to the trap type.
SLAVE:
Vector = 3.
ILL:
Vector = 4.
SVC:
3.9.1 Slave Processor Protocol
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an 10 Byte followed by an Operation Word. The 10 Byte has three functions:
Vector = 5.
Vector = 6.
DVZ:
FLG:
BPT:
Vector = 7.
Vector = 8.
UNO:
Vector = 10.
1) It identifies the instruction as being a Slave Processor instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word of the instruction.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-29. While applying
Status Code 1111 (Broadcast 10, Sec. 3.4.2), the CPU
transfers the 10 Byte on the least-significant byte of the
Data Bus (ADO-AD7). All Slave Processors input this byte
and decode it. The Slave Processor selected by the 10 Byte
is activated, and from this point the CPU is communicating
only with it. If any other slave protocol was in progress (e.g.,
an aborted Slave instruction), this transfer cancels it.
3) Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, P and T.
4) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
5) Set "Return Address" to the address of the first byte of
the trapped instruction.
6) Perform Service (Vector, Return Address), Figure 3-28.
3.8.7.3 Trace Trap Sequence
1) In the Processor Status Register (PSR), clear the P bit.
2) Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Sec. 3.4.2).
Upon receiving it, the Slave Processor decodes it, and at
this point both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The operation Word is swapped on the Data Bus, that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD7.
3) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
4) Set "Vector" to 9.
5) Set "Return Address" to the address of the next instruction.
6) Perform Service (Vector, Return Address), Figure 3-28.
Using the Address Mode fields within the Operation Word,
the CPU starts fetching operand and issuing them to the
Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
3.8.7.4 Abort Sequence
1) Restore the currently selected Stack Pointer to its original
contents at the beginning of the aborted instruction.
2) Clear the PSR P bit.
3) Copy the PSR into a temporary register, then clear PSR
bits S, U, T and 1.
4) Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
5) Set "Vector" to 2.
6) Set "Return Address" to the address of the first byte of
the aborted instruction.
Status Combinations:
Send 10(10): Code 1111
Xler Operand (OP): Code 1101
Read Status (ST): Code 1110
Step
Status
1
ID
Action
7) Perform Service (Vector, Return Address), Figure 3-28.
2
OP
CPU Sends Operaton Word.
3.9 SLAVE PROCESSOR INSTRUCTIONS
3
OP
CPY Sends Required Operands
The NS32032 CPU recognizes three groups of instructions
being executable by external Slave Processor:
4
CPU Send 10 Byte.
Slave Starts Execution. CPU Pre·letches.
Slave Pulses SPC Low.
Floating Point Instruction Set
Memory Management Instruction Set
Custom Instruction Set
6
ST
CPU Reads Status Word. (Trap? Alter Flags?)
OP
CPU Reads Results (If Any).
FIGURE 3-29. Slave Processor Protocol
2-275
o
CAl
~
.....
o
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
.....
~
w
CO)
(/)
z
3.0 Functional Description
(Continued)
for memory accesses, these extensions are not sent to the
Slave processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Sec. 3.4.2).
An exception to the protocol above is the LMR (Load Memory Management Register) instruction, and a corresponding
Custom Slave instruction (LCR: Load Custom Register). In
executing these instructions, the protocol ends after the
CPU has issued the last operand. The CPU does not wait for
an acknowledgement from the Slave Processor, and it does
not read status.
After the CPU has issued the last operand, the Slave Processor starts the actual executidn of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low. To
allow for this, and for the Address Translation strap function, AT/SPC is normally held high only by an internal pullup device of approximately 5 kO.
3.9.2 Floating Point Instructions
Table 3-4 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave, Sec.
3.4.2).
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Instruction Set Reference Manual).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status, Sec. 3.4.2). This
word has the format shown in Figure 3-30. If the Q bit
("Quit", Bit 0) is set, this indicates that an error was detected by the Slave Processor. The CPU will not continue the
protocol, but will immediately trap through the Slave vector
in the Interrupt Table. Certain Slave Processor instructions
cause CPU PSR bits to be loaded from the Status Word.
The Operand Issued columns show the sizes of the operands issued to the Floating Point Unit by the CPU. "0" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, 0 = Double Word). "f" indicates that the instruction
specifies a Floating Point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-3{}).
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand, Sec.
3.4.2).
TABLE 3-4
Mnemonic
Operand 1
Class
Floating Point Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
PSR Bits
Affected
none
none
none
none
AOOf
SUBf
MUll
OIVf
read.f
read.f
read.f
read.f
rmw.f
rmw.f
rmw.f
rmw.f
f
ftoOp.2
ftoOp.2
ftoOp.2
ftoOp.2
MOVf
ABSf
NEGf
read.f
read.f
read.f
write.f
write.f
write.f
N/A
N/A
N/A
ftoOp.2
ftoOp.2
ftoOp.2
none
none
none
CMPf
read.f
read.f
N/A
N,Z,L
FLOORfi
TRUNCfi
ROUNOfi
read.f
read.f
read.f
write.i
write.i
write.i
f
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
none
none
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
N/A
N/A
LtoOp.2
FtoOp.2
none
none
MOVif
read.i
write.f
N/A
ftoOp.2
none
LFSR
SFSR
read. 0
N/A
N/A
write.O
N/A
N/A
N/A
OtoOp.2
none
none
0
N/A
Nate:
o=
Returned Value
Type and Dest.
Double Word
I = Integer size (B,W,D) specified in mnemonic.
f = Floating Paint type (F,L) specijied in mnemonic.
NtA = Not Applicable to this instruction.
2-276
z
3.0 Functional Description
15
I
(J)
IN
N
3.9.3 Memory Management Instructions
Table 3·5 gives the protocols for Memory Management instructions. Encodings for these instructions may be found in
Appendix A.
In executing the RDVAL and WRVAL instructions, the CPU
calculates and issues the 32-bit Effective Address of the
single operand. The CPU then performs a single· byte Read
cycle from that address, allowing the MMU to safely abort
the instruction if the necessary information is not currently in
physical memory. Upon seeing the memory cycle complete,
the MMU continues the protocol, and returns the validation
result in the F bit of the Slave Status Word.
The size of a Memory Management operand is always a 32bit Double Word. For further details of the Memory Management Instruction set, see the Instruction Set Reference
Manual and the NS32082 MMU Data Sheet.
o
8 7
0 0 0 0 0 0 0 0
Co)
(Continued)
Z F 0 0 L 0
NewPsRBltV.IUe(.)~
01
.-A)
"Quit": Terminate Prolocol.1l'ap(FPU).
TL/EE/5491-42
FIGURE 3·30. Slave Processor Status Word Format
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
oCo)
.
N
.....
o
TABLE 3-5
Mnemonic
RDVAL*
WRVAL'
LMR'
SMR*
Operand 1
Class
Memory Management Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
Returned Value
Type and Dest.
PSR Bits
Affected
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
DtoOp.1
none
none
Note:
In the RDVAL and WRVAL instructions, the CPU issues the address as a Double Word, and performs a single·byte Read cycle from that memory address. For
details, see the Instruction Set Reference Manual and the NS32082 Memory Management Unit Data Sheet.
o
•
~
~
NI A
Double Word
Privileged Instruction: will trap if CPU is in User Mode.
~
Not Applicable to this instruction.
II
2-277
C)
..-
~
C")
C)
r---------------------------------------------------------------------------------,
3.0 Functional Description (Continued)
N
3.9.4 Custom Slave Instructions
U)
Provided in the NS32032 is the capability of communicating
with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
C")
Z
Table 3-6 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
operand which can be a 32-bit ("D") or 64-bit ("0") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type "c" will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
For the instruction encodings, see Appendix A.
TABLE 3-6
Mnemonic
Operand 1
Class
Custom Slave Instruction Protocols.
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
read.c
read.c
read.c
read.c
rmw.c
rmw.c
rmw.c
rmw.c
c
c
c
c
c
c
c
c
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
none
CMOVOc
CMOVlc
CMOV2c
CMOV3c
read.c
read.c
read.c
read.c
write.c
write.c
write.c
write.c
c
c
c
c
N/A
N/A
N/A
N/A
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
none
CCMPOc
CCMPlc
read.c
read.c
read.c
read.c
c
c
c
c
N/A
N/A
N,Z,L
N,Z,L
CCVOci
CCVlci
CCV2ci
CCV3ic
read.c
read.c
read.c
read.i
write.i
write.i
write.i
write.c
c
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
ctoOp.2
none
none
none
none
CCV4DO
CCV50D
read.D
read.O
write.O
write.D
D
0
N/A
N/A
OtoOp.2
DtoOp.2
none
none
LCSR
SCSR
read.D
N/A
N/A
write.D
D
N/A
N/A
N/A
N/A
DtoOP.2
none
none
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
DtoOp.l
none
none
LCR"
SCR"
c
c
Note:
o = Double Word
c
PSR Bits
Affected
CCALOc
CCAL1c
CCAL2c
CCAL3c
CATSTO·
CATST1*
i
Returned Value
Type and Dest.
= Integer size (B,W,D) specified in mnemonic.
= Custom size (0:32 bits or Q:64 bits) specified in mnemonic.
• = Privileged instruction: will trap H CPU is in User Mode.
N/ A = Not Applicable to this instruction.
2-278
zCJ)
4.0 Device Specifications
Co)
N
Byte Enable (BEO-BE3): Active low. Four control signals
enabling data transfers on individual bus bytes. Sec. 3.4.3.
Status (STO-ST3): Bus cycle status code, STO least significant. Sec. 3.4.2. Encodings are:
4.1 NS32032 PIN DESCRIPTIONS
The following is a brief description of all NS32032 pins. The
descriptions reference portions of the Functional Description. Sec. 3.
Unless otherwise indicated reserved pins should be left
open.
oCo)
N
I
......
o
0000 - Idle: CPU Inactive on Bus.
0001 - Idle: WAIT Instruction.
0010 - (Reserved).
0011 - Idle: Waiting for Slave.
0100 - Interrupt Acknowledge, Master.
0101 -Interrupt Acknowledge, Cascaded.
0110 - End of Interrupt, Master.
0111 - End of Interrupt, Cascaded.
1000 - Sequential Instruction Fetch.
1001 - Non-Sequential Instruction Fetch.
1010 - Data Transfer.
1011 - Read Read-Modify-Write Operand.
1100 - Read for Effective Address.
1101 - Transfer Slave Operand.
1110 - Read Slave Status Word.
1111 - Broadcast Slave ID.
4.1.1 Supplies
Power (VcC>: +5V Positive Supply. Sec. 3.1.
Logic Ground (GNDL): Ground reference for on-chip logic.
Sec. 3.1.
Buffer Grounds # 1 (GNDB1, GNDB2, GNDB3): Ground
references for the on-chip output drivers connected to output pins. Sec. 3.1.
Back-Bias Generator (BBG): Output of on-Chip substrate
voltage generator. Sec. 3.1.
4.1.2 Input Signals
Clocks (PHI1, PHI2): Two-phase clocking signals. Sec. 3.2.
Ready (ROY): Active high. While RDY is inactive, the CPU
extends the current bus cycle to provide for a slower memory or peripheral reference. Upon detecting RDY active, the
CPU terminates the bus cycle. Sec. 3.4.1.
Hold Acknowledge (HLDA): Active low. Applied by the
CPU in response to HOLD input, indicating that the bus has
been released for DMA or multiprocessing purposes. Sec.
3.6.
User/Supervisor (U/S): User or Supervisor Mode status.
Sec. 3.7. High state indicates User Mode, low indicates Supervisor Mode. Sec. 3.7.
Interlocked Operation (ILO): Active low. Indicates that an
interlocked instruction is being executed. Sec. 3.7.
Program Flow Status (PFS): Active low. Pulse indicates
beginning of an instruction execution. Sec. 3.7.
Hold Request (HOLD): Active low. Causes the CPU to release the bus for DMA or multiprocessing purposes. Sec.
3.6.
Note1: HOLD must not be asserted until HLDA from a previous
HOLD/HLDA sequence is deasserted.
Note 2: If the FiQTIj signal is generated asynchronously, it's set up and hold
times may be violated.
In this case it is recommended to synchronize it with CTTL to minimize the possibility of metastable states.
The CPU provides only one synchronization stage to minimize the
HLOA latency. This is to avoid speed degradations in cases of
heavy HOLD activity (i.e., DMA controlier cycles inte~eaved with
CPU cycles.)
4.1.4 Input-Output Signals
Address/Data 0-23 (ADO-AD23): Multiplexed Address/
Data information. Bit 0 is the least significant bit of each.
Sec. 3.4.
Data Bits 24-31 (024-031): The high order 8 bits of the
data bus.
Address Translation/Slave Processor Control (AT/
SPC): Active low. Used by the CPU as the data strobe output for Slave Processor transfers; used by Slave Processors to acknowledge completion of a slave instruction.
Sec. 3.4.6; Sec. 3.9. Sampled on the rising edge of Reset
pulse as Address Translation Strap. Sec. 3.5.1.
In non-memory-managed systems, this pin should be
pulled-up to Vee through a 10 kn. resistor.
Data Strobe/Float (DS/FLn: Active low. Data Strobe output, Sec. 3.4, or Float Command input, Sec. 3.5.3. Pin function is selected on AT /SPC pin, Sec. 3.5.1.
Interrupt (INn: Active low. Maskable Interrupt request.
Sec. 3.8.
Non-Maskable Interrupt (NMI): Active low. Non-Maskable
Interrupt request. Sec. 3.8.
Reset/Abort (RST/ABn: Active low. If held active for one
clock cycle and released, this pin causes an Abort Command, Sec. 3.5.4. If held longer, it initiates a Reset. Sec. 3.3.
4.1.3 Output Signals
Address Strobe (ADS): Active low. Controls address latches: indicates start of a bus cycle. Sec. 3.4.
Data Direction in (ODIN): Active low. Status signal indicating direction of data transfer during a bus cycle. Sec. 3.4.
2-279
EI
C)
r---------------------------------------------------------------------------------,
e:.
4.0 Device Specifications (Continued)
N
4.2 ABSOLUTE MAXIMUM RATINGS
tn
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
CO)
C)
CO)
Z
Temperature Under Bias
Storage Temperature
All Input or Output Voltages With
-0.5Vto +7V
Respect to GND
Power Dissipation
1.5 Watt
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
O'C to + 70'C
-65'Cto + 150'C
4.3 ELECTRICAL CHARACTERISTICS TA = 0' to + 70'C, Vcc = 5V ± 5%, GND = OV
Symbol
Parameter
2.0
Units
V
-0.5
0.8
V
PHI1, PHI2 pins only
Vcc - 0.35
Vee +0.5
V
Low Level Clock Voltage
PHI1, PHI2 pins only
-0.5
0.3
V
Low Level Clock Voltage.
Transient (ringing tolerance)
PHI1, PHI2 pins only
-0.5
0.6
V
High Level Output Voltage
IOH = -400/LA
Low Level Output Voltage
IOL = 2mA
0.45
V
AT/SPC Input Current (low)
VIN = 0.4V, AT/SPC in input mode
0.05
1.0
mA
Input Load Current
o ~ VIN ~ Vee, All inputs except
PHI1, PHI2, AT/SPC
-20
20
-20
30
Active Supply Current
V
2.4
Leakage Current
Output and I/O Pins in
TRI-STATE/lnput Mode
ICC
Max
Vee +0.5
High Level Clock Voltage
Low Level Input Voltage
VCLl
Typ
Min
Conditions
High Level Input Voltage
180
lOUT = 0, TA = 25'C
300
~~E~I~15~~~~~~~~g
RESERVED
~UUUUUUUUUUUUUUUElI!
:~5
~:=!
c::
iiiiiri :::J
RESERVED :::J
RESERVED ::J
PHI1 :::J
PHI2
;:::J
I:
I:
I:
I:
t:
I:
I:
I:
I:
NS32032
AiiS b:I
UtS 3D
cpu
;:J
t:J
Af/S~ :J
RESERVED
RESERVED
II1IFLJ
m,m
c::
;::J
:J
RESERVED :::J
RESERVED ICDNNECT ro Vee lL
THROUGH A4.7 kll RESISTORI ~
AD22
AD19
AD18
AD17
AD1&
AD15
AD14
AD13
AD12
ADn
AD10
AD9
I: AD8
I: AD7
m:
nnn non n n n nn n n nn JiIj
~I;I~I~I~I~I~
£5
z:
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Bottom View
FIGURE 4·1. NS32032 Connection Diagram
Order Number NS32032E·10 or NS32032V·10
See NS Package E6SB or V6SA
2-280
AM
TLlEE/5491-2
mA
4.0 Device Specifications (Continued)
and PHI2 and O.BV or 2.0V on all other signals as illustrated
in Figures 4-2 and 4-3, unless specifically stated otherwise.
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
ABBREVIATIONS:
All the timing speCifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
L.E. -
leading edge
R.E. -
rising edge
T.E. -
trailing edge
F.E. -
falling edge
-[::¥-[
SIGI
~2'4V
ISIGII
1---'="------
[ __k
PHln
[
SIGl
a.BV
O.45V
[
I
ISIG2h
[
1~2'4V
2.0V
SlG2
SlG2
-------,-.---- -
- - 2.4V
a.BV ..l\~_~ ISIGlI
'----I--O.45V
/I"""---I---2.4V
2.0V
-1-----.-1
ISIG2h
_ _ _ _ _....J:.....______._._ -
O.45V
- - - - J .__.--------O.45V
TL/EE/5491-44
TL/EE/5491-43
FIGURE 4·3. Timing Specification Standard
(Signal Valid Before Clock Edge)
FIGURE 4·2. Timing Specification Standard
(Signal Valid After Clock Edge)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32032·10
Maximum times assume capacitive loading of 100 pF.
Name
Figure
Description
Reference/Conditions
NS32032·10
Min
tALv
4-4
Address bits 0-23 valid
after R.E., PHI1 T1
Units
Max
40
tALh
4-4
Address bits 0-23 hold
after R.E., PHI1 Tmmu or T2
tov
4-4
Data valid (write cycle)
after R.E., PHI1 T2
tOh
4-4
Data hold (write cycle)
after R.E., PHI1 next T1 or Ti
0
ns
tALAOSs
4-5
Address bits 0-23 setup
before ADS T.E.
25
ns
tALAOSh
4-10
Address bits 0-23 hold
after ADS T.E.
15
tAL!
4-5
Address bits 0-23
floating (no MMU)
after R. E., PH 11 T2
25
ns
tAD!
4-5
Data bits 024-031
floating (no MMU)
after R.E., PHI1 T2
25
ns
tALM!
4-9
Address bits 0-23
floating (with MMU)
after R.E., PHI1 Tmmu
25
ns
tAOM!
4-9
Data bits 21-31
floating (with MMU)
after R.E., PHI1 Tmmu
25
ns
tBEv
4-4
BEn Signals valid
after R.E., PHI2 T4
60
ns
tBEh
4-4
BEn Signals hold
after R.E., PHI2 T4 orTi
tSTv
4-4
Status (STO-ST3) valid
after R.E., PHI1 T4
(before T1, see note)
tSTh
4-4
Status (STO-ST3) hold
after R.E., PHI1 T4 (afterT1)
2-2B1
5
ns
ns
50
ns
0
ns
60
0
ns
ns
ns
fII
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32032-10 (Continued)
Name
Figure
Referencel
Conditions
Description
NS32032-10
Min
Units
Max
tOOINv
4-5
ODIN signal valid
after RE., PHI1 T1
tOOINh
4-5
ODIN signal hold
after RE., PHI1 next T1 or Ti
tAOSa
4-4
ADS signal active (low)
after RE., PHI1 T1
35
ns
tAOSia
4-4
ADS signal inactive
after RE., PHI2 T1
40
ns
tAOSw
4-4
ADS pulse width
at 0.8V (both edges)
tOSa
4-4
OS signal active (low)
after RE., PHI1 T2
40
ns
tOSia
4-4
OS signal inactive
after RE., PHI1 T4
40
ns
tALI
4-6
ADO-AD23 floating
(caused by HOLD)
after R.E., PHI1 T1
25
ns
tAD!
4-6
024-031 floating
(caused by HOLD)
after RE., PHI1 T1
25
ns
tOS!
4-6
OS floating
(caused by HOLD)
after RE., PHI1 Ti
50
ns
tAOS!
4-6
ADS floating
(caused by HOLD)
after RE., PHI1 Ti
50
ns
tBE!
4-6
BEn floating
(caused by HOLD)
after RE., PHI1 Ti
50
ns
tOOIN!
4-6
ODIN floating
(caused by HOLD)
after RE., PHI1 Ti
50
ns
tHLOAa
4-6
HLDA signal active (low)
after RE., PHI1 Ti
30
ns
tHLOAia
4-8
HLDA signal inactive
after RE., PHI1 Ti
40
ns
IOSr
4-8
OS signal returns from
floating (caused by HOLD)
after R.E., PHI1 Ti
50
ns
tAOSr
4·8
ADS signal returns from
floating (caused by HOLD)
after R.E., PHI1 Ti
55
ns
tBEr
4·8
BEn signals return from
floating (caused by HOLD)
after RE., PHI1 Ti
55
ns
tOOINr
4-8
. ODIN signal returns from
floating (caused by HOLD)
after RE., PHI1 Ti
55
ns
too IN!
4-9
ODIN signal floating
(caused by FL
after FLT F.E.
55
ns
tOOINr
4-10
ODIN signal returns from
floating (caused by FL
after FLT R E.
40
ns
tSPCa
4-13
SPC output active (low)
after RE., PHI1 T1
35
ns
tsPCia
4-13
SPC output inactive
after RE., PHI1 T4
35
ns
tsPCn!
4-15
SPC output nonforcing
after R.E., PHI2 T4
30
ns
tov
4-13
Data valid (slave processor
write)
after RE., PHI1 T1
55
ns
tOh
4-13
Data hold (slave processor
write)
after R.E., PHI1
nextT10rTi
0
ns
tpFSw
4-18
PFS pulse width
at 0.8V (both edges)
50
ns
n
n
2-282
50
0
ns
ns
30
ns
z
en
w
4.0 Device Specifications (Continued)
N
~
4.4.2.1 Output Signals: Internal Propagation Delays, NS32032-10 (Continued)
Name
Figure
Reference/
Conditions
Description
NS32032-10
Min
Units
•
......
o
Max
tPFSa
4-18
PFS pulse active (low)
after R.E., PHI2
40
ns
tPFSia
4-18
PFS pulse inactive
after R.E., PHI2
40
ns
tllOs
4-20a
ILO signal setup
before R.E., PHI1 T1
of first interlocked read cycle
50
ns
tllOh
4-20b
ILO signal hold
after R.E., PHI1 T3
of last interlocked write cycle
10
ns
tllOa
4-21
ILO signal active (low)
after R.E., PHI1
35
ns
tllOia
4·21
ILO signal inactive
after R.E., PHI1
35
ns
tUSv
4·22
U/S signal valid
after R.E., PHI1 T4
35
ns
tUSh
4·22
U/S signal hold
after R.E., PHI1 T4
8
ns
tNSPF
4·19b
Nonsequential fetch to
next PFS clock cycle
after R.E., PHI1 T1
4
tep
tpFNS
4·19a
PFS clock cycle to next
non·sequential fetch
before R.E., PHI1 T1
4
tep
Last operand transfer
before R.E., PHI1 T1 of first
0
tep
of an instruction to next
of first bus
PFS clock cycle
cycle of transfer
Nate: Every memory cycle starts with T4, during which Cycle Status is applied. If the CPU was idling, the sequence will be: "... Ti, T4, T1 ...". If the CPU was
not idling, the sequence will be: ". . . T4, T1 . . .".
tLXPF
4·29
4.4.2.2 Input Signal Requirements: NS32032-10
Name
Figure
Description
NS32032-10
Reference/Conditions
Min
Units
Max
tPWR
4·25
Power stable to
RST R.E.
after Vee reaches 4.5V
50
!,-S
tDls
4·5
Data in setup
(read cycle)
before F.E., PHI2 T3
15
ns
tDlh
4·5
Data in hold
(read cycle)
after R.E., PHI1 T4
3
ns
tHlDa
4·6
HOLD active (low) setup
time (see note)
before F.E., PHI2 TX1
25
ns
tHlDia
4·8
HOLD inactive setup
time
before F.E., PHI2 Ti
25
ns
tHlDh
4·6
HOLD hold time
after R.E., PHI1 TX2
0
ns
tFlTa
4·9
FLT active (low)
setup time
before F.E., PHI2 Tmmu
25
ns
tFlTia
4·10
FLT inactive setup
time
before F.E., PHI2 T2
25
ns
tRDYs
4·11,4·12
ROY setup time
before F.E., PHI2 T2 or T3
15
ns
tRDYh
4·11,4·12
ROY hold time
after F.E., PHI1 T3
5
ns
tASTs
4·23
ABT setup time
(FLT inactive)
before F.E., PHI2 Tmmu
20
ns
tASTs
4·24
ABT setup time
(FLT active)
before F.E., PHI2 Tf
20
ns
tASTh
4·23
ABT hold time
after R.E., PHI1
0
ns
2·283
0
fII
.
o
....
C'I
C')
4.0 Device Specifications (Continued)
o
C'I
4.4.2.2 Input Signal Requirements: NS32032-10 (Continued)
C')
(/)
z
Name
Figure
Referencel
Conditions
Description
NS32032-10
Min
Units
Max
tRSTs
4-25,4-26
RST setup time
before F.E., PHI1
15
ns
tRSTw
4-26
RST pulse width
at O.BV (both edges)
64
tcp
tiNTs
4-27
INT setup time
before F.E., PHI1
25
ns
tNMlw
4-2B
NMI pulse width
at O.BV (both edges)
70
ns
tOls
4-14
Data setup (slave
read cycle)
before F.E., PHI2 T1
15
ns
tOlh
4-14
Data hold (slave
read cycle)
after R.E., PHI1 T4
3
ns
tSPCd
4-15
SPC pulse delay from
slave
after R.E., PHI2 T4
25
ns
tspcs
4-15
SPC setup time
before F.E., PHI1
25
ns
tgPCw
4-15
SPC pulse width from
slave processor
(async input)
at O.BV (both edges)
20
ns
tATs
4-16
AT /SPC setup for address translation strap
before R.E., PHI1 of cycle
during which RST
pulse is removed
1
tcp
4-16
AT /SPC hold for address translation strap
after F.E., PHI1 of cycle
2
tcp
during which RST
pulse is removed
Note: This setup time is necessary to ensure prompt acknowledgement via HLOA and the ensuing floating of CPU off the buses. Note that Ihetime from the receipt
of the HOLO Signal until the CPU floats is a function of the lime HOLD signal goes low, the state of the ROY input (in MMU systems), and the length of the current
MMU cycle.
tATh
4.4.2.3 Clocking Requirements: NS32032-10
Name
Figure
Referencel
Conditions
Description
NS32032-10
Units
Min
Max
100
250
ns
tcp
4-17
Clock period
R.E., PHI1, PHI2 to next
R.E., PHI1, PHI2
tCLw
4-17
PHI1, PHI2
pulse width
At 2.0V on PHI1,
PHI2 (both edges)
0.5tcp
-10ns
tCLh
4-17
PHI1, PHI2 high time
At Vcc - 0.9Von
PHI1, PHI2 (both edges)
0.5tcp
-15ns
tCLI
4-17
PHI1, PHI2, Low Time
at O.BV on PHI1, PHI2
0.5 tcp
-5ns
tnOVL(1,2)
4-17
Non-overlap time
O.BVon F.E., PHI1, PHI2 to
O.BV on R.E., PHI2, PHI1
-2
5
ns
tnOVLas
Non·overlap asymmetry
(tnOVL(1) - tnOVL(2»
at O.BV on PHI1, PHI2
-4
4
ns
tCLwas
PHI1, PHI2 asymmetry
(tcLw(1) - tCLw(2»
at 2.0Von PHI1, PHI2
-5
5
ns
2-2B4
,--------------------------------------------------------------------------, z
en
w
4.0 Device Specifications
I\)
<:)
w
4.4.3 Timing Diagrams
T4 OR Ti
,
I
11
PHI, [
PHI2 [
ADO-A023 [
-~tJl:
KJ
ADDRESS
I
X
024-031 [
I
,
T2
n
I
T3
n
T4
L
IL -
.~~
IX
I)
DATA OUT
X
tDv
tOh
)
DATA OUT
I-: 'AOSI.
l~AD~W
iDS [
~
.....
<:)
taEh
W
I-- ~
tSTY
'tAOS.
BED-BE [
VALID
-l taEv
DDiN[
(HIGH)
tSTh ~~
VALID
5TO·3 [
N
-
\I
NEXT
1/
tDSS
'f- tOSI.
(HIGH)
I
I
TL/EE/5491-45
FIGURE 4·4. Write Cycle
T4 OR TI
PHil [
Tl
n
T2
T3
n
,...-
PHI2 [
ADO-AD23 [
X
ADDRESS
A-' ------
~
X
ADDRESS
~. ------
r---
JLr---
•
__ -( DATAIN
ALI
024-031 [
T4
r--
---(
E
-!Dlh
DA~~IN
-'AOt
AliS[
'ALAOSs
BEO-BE3" [
DDiN[
VALID
L
~
tDOINv
--l tooINh
VALID
5T0-3 [
os[
ROY [
X
'"
NE:iA~0~LE
(HIGH)
TL/EE/5491-46
FIGURE 4·5. Read Cycle
2·285
C)
.....
N
C")
.-------------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
C)
N
TX1
C")
TX2
Ti
TI
T4
TI
(f)
Z
PH11[
PHI2[-+_........I
HOLO[
HLi5l[
IDSF
IADSI
IOOINI
os
AoS[ -t----+----+----:-__t--J
IiiiiN
BEo_m[-t----+----+--.,.=.::.:....j-~
--- ----(fLOATlNGj----
----,-----tFL01ii'NG)---I~~-- ___
AOO-A023 [
~~~_-'-
024-031 [
I
----1--___ _
____
~~Oj~:~
___ _
(FLOfTING)
TL/EE/5491 -47
FIGURE 4-6. Floating by HOLD Timing (CPU Not Idle Initially).
Note that whenever the CPU is not idling (not in Ti), the HOLD request (HOLD low) must be active tHLDa before the falling edge
of PHI2 of the clock cycle that appears two clock cycles before T4 (TX1) and stay low until tHLDh after the rising edge of PHI1 of
the clock cycle that precedes T4 (TX2) for the request to be acknowledged.
PHil [
PHil [
PHI2 [
PHI2
[_+-........1
HOLD [
HLDA [
lOS!
lADS!
_+___+-__-+. . . .,IODINf
AOS.[_-r____~----~
ODIN
Os,
BEci-iiE3
OS.
--------(FLOATING)
ADS. [ • - ODIN
[-+---I----+..J
AOO-AD23 [ - - -
024-031 [ - - -
BEo-iiE3 [ • - -
(FLOATING)
------
------
(HIGH)
(FLOATING)
ADO-AD23 [ . 024-031
-------------(FLOATING)
-~ - - - - - -
I
t------~iI
FLOATiNG
i
TL/EE/5491 -49
FIGURE 4·8. Release from HOLD
TL/EE/5491 -48
FIGURE 4-7. Floating by HOLD Timing (CPU initially idle)
Note that during Ti1 the CPU is already idling.
2-286
z
~
N
4.0 Device Specifications (Continued)
Q
Co)
CPU STATES
Tl
MMUSTATES [
T1
TMMU
TI
N
TI
.....•
Q
PHI 1
PHI2 [
m[
ADO-AD23 [
(CPU)
D24-D31 [
(CPU)
ADS [
(CPU)
PAV[
(MMU)
DDiN[
BEO-BE3 [
TL/EE/S491-50
FIGURE 4·9. FLT Initiated Float Cycle Timing
CPU STATES
TI
T2
T3
T4
Tmmu
MMU STATES
PHI1 [
PHI2[~_ _.J
m[
(MMU)
ADG-23 [
& D24-31
•
(CPU)
Di5iN[
(CPU)
--
ADS[
(CPU)
m-m[~____-+____-4______~____
TL/EE/S491-51
FIGURE 4·10. Release from FLT Timing
Note that when FLTis deasserted the CPU restarts driving ODIN before the MMU releases it. This, however, does not cause any
conflict, since both CPU and MMU force ODIN to the same logic level.
TL/EE/5491-52
FIGURE 4·11. Ready Sampling (CPU Initially READy)
2-287
4.0 Device Specifications (Continued)
I I
I
I
:~~
~
RDV[
TLlEE/5491-53
FIGURE 4-12. Ready Sampling (CPU Initially NOT READY)
I
I
T1
T4
I
L__
I
I
PHI1[JLJLJ
T1
PHI1[~
T4
tDlh
PHI2 [
PHI2 [
ADO-IS [
ADO-IS [
SPC[
SPc[
(CPU)
DDtN[-+~______~______+-
DoiN[
STD·3
STO-3 [
ADii[
[-+---f-J ~---1"'"
AiiS[
(HIGH)
I
TL/EE/5491-55
TL/EE/5491-54
FIGURE 4-14. Slave Processor Read Timing
FIGURE 4-13. Slave Processor Write Timing
T4
T1
PHil [
PHI2 [
SPC [
(FROM CPU)
SPC [ •
(FRON SLAVE)
TLlEE/5491-82
FIGURE 4-15. SPC Timing
After transferring last operand to a Slave Processor, CPU
turns OFF driver and holds SPC high with internal 5 kO pullup.
TL/EE/5491-57
FIGURE 4-16. Reset Configuration Timing
2-288
z
en
w
4.0 Device Specifications (Continued)
N
o
W
N
.....
I
o
PHI1 [
PHI2[
-----..,..r
TLlEE/S491-S8
FIGURE 4-17. Clock Waveforms
PHI2[~fUl-J
mr~r--e-
TL/EE/S491-S9
FIGURE 4-18. Relationship of PFS to Clock Cycles
T1
PHI1 [
~[b--....JI
.1
-JX'-__
ST(J.3 [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
C_O_OE_1_00_1_ _
TL/EE/S491-60
FIGURE 4-19a. Guaranteed Delay, PFS to Non-Sequential Fetch
I
PHil
Tl
I
T2
I ••• I
I
I
I
LfLJLJ~fLfl-Jl-
A5S[
ST~3[-+_ _ _ _CO_D_E_l_00_l_ _ _-i.r-___-r_______
TL/EE/S491-6l
FIGURE 4-19b. Guaranteed Delay, Non-Sequential Fetch to PFS
2-289
....Q r-----------------------------------------------------------------------------,
N
C")
4.0 Device Specifications (Continued)
Q
N
~
I
Z
T30RTI
I
T40RTI
I
T1
12
T3
T4
PHil [
AiiS[
iLO[
TL/EE/5491-62
FIGURE 4·20a. Relationship of ILO to First Operand Cycle of an Interlocked Instruction
I
T30RTI
I
T40RTI
I
T1
12
T3
T4
ILO[ ................................~........................_+'
TL/EE/5491-63
FIGURE 4·20b. Relationship of ILO to Last Operand Cycle of an Interlocked Instruction
TL/EE/5491-64
FIGURE 4·21. Relationship of ILO to Any Clock Cycle
I T3 OR Ti I
T4 OR TI
I
T1
T2
T3
T4
PHil [
U/i['-L.c..L.","","~ 1'-_+-_ _ _ _ _ _ _ _ _-+...11
TL/EE/5491-65
FIGURE 4·22. U/S Relationship to Any Bus Cycle - Guaranteed Valid Interval
2·290
z
en
Co)
4.0 Device Specifications (Continued)
T1
~
I
Co)
~
Tmmu
T2
.....•
TI
o
PHI! [
PHI2 [
FiST/m [
TL/EE/5491-66
FIGURE 4-23. Abort Timing, FLT Not Applied
PHI! [
PHI2 [
iiS/ffi [
-+-----+-----r----+r-J
RsT/ABT [
TL/EE/5491-67
FIGURE 4-24. Abort Timing, FLT Applied
vee
~----------~~
PHI{ _ _--1___....1
R!rrMBT[ ____________~\--J
TL/EE/5491-68
FIGURE 4-25. Power-On Reset
TL/EE/5491-69
FIGURE 4-26. Non-Power-On Reset
2-291
,...
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4.0 Device Specifications (Continued)
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NMi[
TL/EE/5491-71
TLlEE/5491-70
FIGURE 4·28. NMI Interrupt Signal Timing
FIGURE 4·27. INT Interrupt Signal Detection
FIRST BUS CYCLE
Tl
NEXT
12
'--+-~/
TLlEE/5491-72
FIGURE 4·29. Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction
Note: In a transfer of a Read·Modify·Write type operand, this is the Read transfer, displaying RMW Status (Code 1011).
2·292
.--------------------------------------------------------------------------. z
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Appendix A: Instruction Formats
I\)
o
w
Configuration bits, in SETCFG:
NOTATIONS
....o~
I C I M I F II I
i= Integer Type Field
B = 00 (Byte)
mreg NS32082: MMU
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
W = 01 (Word)
D = 11 (Double Word)
f= Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L = 0 (Long Floating: 64 bits)
c= Custom Type Field
D = 1 (Double Word)
Q = 0 (Quad Word)
op= Operation Code
Valid encodings shown with each format.
gen, gen 1, gen 2 = General Addressing Mode Field
See Sec. 2.2 for encodings.
reg = General Purpose Register Number
cond = Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110 = Greater Than: N = 1
0111 = Less or Equal: N = 0
1000 = Flag Set: F = 1
1001 = Flag Clear: F = 0
1010 = LOwer: L = 0 and Z = 0
1011 = Higher or Same: L = 1 or Z = 1
1100 = Less Than: N = 0 and Z = 0
1101 = Greater or Equal: N = 1 or Z = 1
1110 = (Unconditionally True)
1111 = (Unconditionally False)
Register number, in LMR, SMR.
= BPRO
= BPR1
= (Reserved)
= (Reserved)
= (Reserved)
= (Reserved)
= (Reserved)
= (Reserved)
= (Reserved)
= (Reserved)
= MSR
= BCNT
= PTBO
= PTB1
= (Reserved)
= EIA
7
0
FormatO
(BR)
Bcond
7
0
,,
op
1
10 ' 0 ' l' 01
Format 1
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
short= Short Immediate value. May contain
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ, ACB.
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPR.
0000 = US
0001 - 0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = (Reserved)
1100 = (Reserved)
1101 = PSR
1110 = INTBASE
1111 = MOD
15
1
ADDQ
CMPQ
SPR
Scond
Options: in String Instructions
IU/W I BIT I
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
2-293
, ,
gen
ENTER
EXIT
Nap
WAIT
DIA
FLAG
SVC
BPT
,,
8 17
'sh~rt
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
1
Format 2
-000
ACB
MOVQ
-001
-010
LPR
-011
op
0
11 ' 1 '
-100
-101
-110
fII
,..
C) ~--------------------------------------------------------------------------------,
~
Appendix A: Instruction Formats (Continued)
C)
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15
I' ~e~ I' ~p
~
,
I
11'1'1'1'11 :
Format 3
CXPD
-0000
ADJSP
BICPSR
-0010
JSR
-0100
CASE
JUMP
-0110
BISPSR
Trap (UND) on XXX1, 1000
-1010
-1100
-1110
al7
15
0
0
o
I
I
I
op
00111 0
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
Format 7
-0000
MUL
-0001
MEl
-0010
Trap (UND)
-0011
DEI
QUO
-0100
-0101
REM
-0110
MOD
DIV
-0111
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
Format a
-000
INDEX
FFS
-001
-010
-011
-110, reg = 001
-110,reg=011
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Format 4
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
-1000
-1001
-1010
-1100
-1101
-1110
SUB
ADDR
AND
SUBC
TBIT
XOR
TLlEE/5491-73
o
i
000 0 1 1 1 0
Format 5
MOVS
-0000
SETCFG
-0001
SKPS
CMPS
Trap (UND) on 1XXX, 01 XX
a7
-0010
-0011
i
o
001110
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
Format 6
-0000
NEG
-0001
NOT
-0010
Trap (UND)
-0011
SUBP
-0100
ABS
-0101
COM
-0110
IBIT
ADDP
-0111
-100
-1 01
MOVif
LFSR
MOVLF
MOVFL
Format 9
-000
ROUND
TRUNC
-001
-010
SFSR
-011
FLOOR
--- 7
---10
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Format 10
Trap (UND) Always
2-294
0
001 1 1 1 1 0
-100
-101
-110
-111
0
1 1 1 1 1 1
TL/EE/5491-38
01
,--------------------------------------------------------------------------, z
(f)
Appendix A: Instruction Formats (Continued)
Co)
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<:)
Co)
o
I\l
.....
<:)
I
1 1 1 1 1 0
10 Byte
Operation Word
Format 11
AOO!
MOVI
CMP!
Trap (SLAVE)
SUB!
NEG!
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
OIV!
Trap (SLAVE)
Trap (UNO)
Trap (UNO)
MULl
ABS!
Trap (UNO)
Trap (UNO)
Format 15
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
(Custom Slave)
nnn
Operation Word Format
000
Format 15.0
·--1 1 I 1 I 1 I 1 I 1 I 1 I 1 I 0 1
CATSTO
CATST1
no
TL/EE/5491-75
-0000
-0001
LCR
SCR
-0010
-0011
Format 12
Trap (UNO) on all others
Trap (UNO) Always
---I
I I I I I I I
___ 1 0 0 1 1 1 1 0
1
001
TL/EE/5491-76
Format 13
Format 15.1
Trap (UNO) Always
o
7
o0
0 1 1 1 1 0
CCV3
LCSR
CCV5
CCV4
-000
-001
-010
-011
CCV2
CCV1
SCSR
CCVO
-100
-101
-110
-111
Format 14
ROVAL
WRVAL
-0000
-0001
LMR
SMR
-0010
-0011
101
Trap (UNO) on 01XX, 1XXX
Format 15.5
CCALO
CMOVO
CCMPO
CCMP1
CCAL1
CMOV2
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
If nnn ~ 010,011,100,110,111
then Trap (UND) Always
2-295
CCAL3
CMOV3
Trap (UNO)
Trap (UNO)
CCAL2
CMOV1
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
C)
....
~
CO)
r-------------------------------------------------------------------------------~
Appendix A: Instruction Formats (Continued)
~
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0
I I I I I II ~
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7
I
---I I
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0
X
I I I I I I
x
0 0 1 1 0
TL/EE/5491-80
TUEE/5491-77
Format 19
Format 16
Trap (UNO) Always
Trap (UNO) Always
0
7
---111111111
---
Implied Immediate Encodlngs:
7
0
I 1 0 1 1 1 1 0
TUEE/5491-78
r7
;
r6
;
r5
;
r4
;
r3
;
r2
r1
rO
Register Mark, appended to SAVE, ENTER
Format 17
7
0
Trap (UNO) Always
rO
7
0
---111111111
---
I
I 0 0 0 1 1 1 0
;
r1
;
r2
; r3 ;
r4
;
r5
; r6 ;
7
0
TL/EE/5491-79
; offset;
Format 18
r7
Register Mark, appended to RESTORE, EXIT
;
lengfh -1
;
Offset/Length Modifier appended to INSS, EXTS
Trap (UNO) Always
2-296
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TLlEE/5491-74
FIGURE 8-1. System Connection Diagram
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NS32CG 16-1 O/NS32CG 16-15
..... High-Performance PrinterIDisplay Processor
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General Description
Features
The NS32CG16 is a 32-bit microprocessor in the Series
32000@ family that provides special features for graphics
applications. It is specifically designed to support page oriented printing technologies such as Laser, LCS, LED, lonDeposition and InkJet.
•
•
•
•
The NS32CG16 provides a 16 Mbyte linear address space
and a 16-bit external data bus. It also has a 32-bit ALU, an
eight-byte prefetch queue, and a slave processor interface.
The capabilities of the NS32CG16 can be expanded by using an external floating point unit which interfaces to the
NS32CG16 as a slave processor. This combination provides optimal support for outline character fonts.
•
The NS32CG16 highly efficient architecture, in addition to
the built-in capabilities for supporting BITBLT (BIT-aligned
BLock Transfer) operations and other special graphics functions, make the device the ideal choice to handle a variety
of page description languages such as Postscript™, CCSPage™ and PCLTM.
Block Diagram
ADlJjOATA
•
•
•
•
•
Software compatible with the Series 32000 family
32-bit architecture and implementation
16 Mbyte linear address space
Special support for graphics applications
- 18 graphics instructions
- Binary compression/expansion capability for font
storage using RLL encoding
- Pattern magnification for Epson and HP LaserJetTM
emulations
- 6 BITBLT instructions on chip
-Interface to an external BITBLT processing unit for
very fast BITBLT operations (optional)
Floating point support via the NS32081 or the NS32381
for outline font, scaling and rotation
On-Chip clock generator
Optimal interface to large memory arrays via the
DP84xx family of DRAM controllers
Power save mode
High-speed CMOS technology
68-pin plastic PCC package
COIflROLS4:STAtuS
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2-298
TL/EE/9424-1
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~National
PRELIMINARY
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NS32CO 16-1 O/NS32CO 16-15
High-Performance Microprocessors
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General Description
Features
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The NS32C016 is a 32-bit, CMOS microprocessor with TIL
compatible inputs. The NS32C016 has a 16M byte linear
address space and a 16-bit external data bus. It is fabricated with National Semiconductor's advanced CMOS process
and is fully object code compatible with other Series
32000® CPU's. The NS32C016 has a 32-bit ALU, eight 32bit general purpose registers, an eight-byte prefetch queue
and a highly symmetric architecture. It also incorporates a
slave processor interface and provides for full virtual memory capability in conjunction with the NS32082 memory management unit (MMU). High performance floating-point instructions are provided with the NS32081 floating-point unit
(FPU). The NS32C016 is intended for a wide range of high
performance computer applications.
III
III
III
III
III
III
III
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32-bit architecture and implementation
16M byte uniform addressing space
Powerful instruction set
- General 2-address capability
- Very high degree of symmetry
- Addressing modes optimized for high-level
Language references
High-speed CMOS technology
TTL compatible inputs
Single 5V supply
48-pin dual-in-line package
Block Diagram
ADD/DATA
CONTROLS & STATUS
it
it
BUS INTERFACE CONTROL F A IN STRUCTIX
II
r---I
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MICROCODE ROM
AND
CONTROL LOGIC
r
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QUEUE
INSTRUCTION}DECODER
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DISPLACEMENT AND
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CFG REGISTER
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REGISTER SET
0
0
0
0
0
0
INTBASE
SB
FP
SPl
SPO
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PC
RO
Rl
R2
R3
R4
RS
R6
R7
I
WORKING
REGISTERS
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32·BIT
ALU
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TLlEE/8525-1
2-299
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Table of Contents
1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.8 NS32C016 Interrupt Structure
2.0 ARCHITECTURAL DESCRIPTION
3.8.1 General InterruptiTrap Sequence
2.1 Programming Model
3.8.2 Interrupti Trap Return
2.1.1 General Purpose Registers
3.8.3 Maskable Interrupts (The INT Pin)
2.1.2 Dedicated Registers
3.8.3.1 Non-Vectored Mode
2.1.3 The Configuration Register (CFG)
3.8.3.2 Vectored Mode: Non-Cascaded Case
2.1.4 Memory Organization
3.8.3.3 Vectored Mode: Cascaded Case
2.1.5 Dedicated Tables
3.8.4 Non-Maskable Interrupt (The NMI Pin)
2.2 Instruction Set
3.8.5 Traps
2.2.1 General Instruction Format
3.8.6 Prioritization
2.2.2 Addressing Modes
3.8.7InterruptiTrap Sequences: Detail Flow
2.2.3 Instruction Set Summary
3.8.7.1 Maskable/Non-Maskable Interrupt Sequence
3.0 FUNCTIONAL DESCRIPTION
3.8.7.2 Trap Sequence: Traps Other Than Trace
3.1 Power and Grounding
3.B.7.3 Trace Trap Sequence
3.2 Clocking
3.B.7.4 Abort Sequence
3.3 Resetting
3.9 Slave Processor Instructions
3.4 Bus Cycles
3.9.1 Slave Processor Protocol
3.4.1 Cycle Extension
3.9.2 Floating Point Instructions
3.4.2 Bus Status
3.9.3 Memory Management Instructions
3.4.3 Data Access Sequences
3.9.4 Custom Slave Instructions
3.4.3.1 Bit Accesses
4.0 DEVICE SPECIFICATIONS
3.4.3.2 Bit Field Accesses
4.1 NS32C016 Pin Descriptions
3.4.3.3 Extending Multiply Accesses
3.4.4 Instruction Fetches
4.1.1 Supplies
3.4.5 Interrupt Control Cycles
4.1.2 Input Signals
3.4.6 Slave Processor Communication
4.1.3 Output Signals
4.1.4 Input-Output Signals
3.4.6.1 Slave Processor Bus Cycles
3.4.6.2 Slave Operand Transfer Sequences
4.2 Absolute Maximum Ratings
3.5 Memory Management Option
4.3 Electrical Characteristics
3.5.1 Address Translation Strap
4.4 Switching Characteristics
3.5.2 Translated Bus Timing
4.4.1 Definitions
3.5.3 The FLT (Float) Pin
4.4.2 Timing Tables
3.5.4 Aborting Bus Cycles
3.5.4.1 The Abort Interrupt
4.4.2.1 Output Signals: Internal Propagation Delays
3.5.4.2 Hardware Considerations
4.4.2.2 Input Signal Requirements
4.4.2.3 Clocking Requirements
3.6 Bus Access Control
APPENDIX A: INSTRUCTION FORMATS
3.7 Instruction Status
APPENDIX B: INTERFACING SUGGESTIONS
List of Illustrations
The General and Dedicated Registers ...........................................................................• 2-1
Processor Status Register ......•.•.....•...........................•.•........•.......•.........................2-2
CFG Register .................................................•..•.................••......•.•....•.•.....•....2-3
Module Descriptor Format. ....•........•...............•.••..........•.......•..................................2-4
A Sample Link Table .............................................•.................•............••.............2-5
General Instruction Format .........•....................•....................................................... 2-6
Index Byte Format .......................................................................................••....2-7
Displacement Encodings ....•..•••......••.••......•......•..........•........•................................. 2-B
Recommended Supply Connections ......................................................................•..•...• 3-1
Clock Timing Relationships ......•...................•.......•...........•......•.......•........................ 3-2
2-300
z
List of Illustrations (Continued)
Power-On Reset Requirements .................................................................................. 3-3
General Reset Timing ..........................................................................................3-4
Recommended Reset Connections, Non-Memory-Managed System ................................................. 3-5a
Recommended Reset Connections, Memory-Managed System ..................................................... 3-5b
Bus Connections ...............................................................................................3-6
Read Cycle Timing .............................................................................................3-7
Write Cycle Timing .............................................................................................3-8
ROY Pin Timing ................................................................................................3-9
Extended Cycle Example ......................................................................................3-1 0
Memory Interface .............................................................................................3-11
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Slave Processor Connections ..•...............................................................................3-12
CPU Read from Slave Processor ................................................................................3-13
CPU Write to Slave Processor .................................................................................. 3-14
Read Cycle with Address Translation (CPU Action) ................................................................ 3-15
Write Cycle with Address Translation (CPU Action) ................................................................ 3-16
Memory-Managed Read Cycle .................................................................................. 3-17
Memory-Managed Write Cycle ..................................................................................3-18
FLTTiming ...................................................................................................3-19
HOLD Timing, Bus Initially Idle ..................................................................................3-20
HOLD Timing, Bus Initially Not Idle .............................................................................. 3-21
Interrupt Dispatch and Cascade Tables ..........................................................................3-22
Interrupt/Trap Service Routine Calling Sequence .................................................................3-23
Return from Trap (RETT n) Instruction Flow ...................................................................... 3-24
Return from Interrupt (RET I) Instruction Flow ..................................................................... 3-25
Interrupt Control Unit Connections (16 Levels) .................................................................... 3-26
Cascaded Interrupt Control Unit Connections ..................................................................... 3-27
Slave Processor Status Word Format. ........................................................................... 3-30
Connection Diagram ............................................................................................4-1
Timing Specification Standard (CMOS Output Signals) ............................................................. .4-2
Timing Specification Standard (TTL Input Signals) .................................................................. 4-3
Write Cycle ................................................................................................... .4-4
Read Cycle ....................................................................................................4-5
Floating by HOLD Timing (CPU Not Idle Initially) .................................................................... 4-6
Floating by HOLD Timing (CPU Initially Idle) .......................................................................4-7
Release from HOLD ............................................................................................4-8
FLT Initiated Cycle Timing ....................................................................................... 4-9
Release from FLT Timing ......................................................................................4-1 0
Ready Sampling (CPU Initially READY) ..........................................................................4-11
Ready Sampling (CPU Initially NOT READY) ......................................................................4-12
Slave Processor Write Timing .................................................................................. .4-13
Slave Processor Read Timing .................................................................................. 4-14
SPC Non-Forcing Delay ........................................................................................4-15
Reset Configuration Timing ..................................................................................... 4-16
Clock Waveforms .............................................................................................4-17
Relationship of PFS to Clock Cycles ........•.................................................................... 4-18
Guaranteed Delay, PFS to Non-Sequential Fetch ................................................................ 4-19a
Guaranteed Delay, Non-Sequential Fetch to PFS ................................................................ 4-19b
Relationship of ILO to First Operand Cycle of an Interlocked Instruction ............................................. 4-20a
Relationship of ILO to Last Operand Cycle of an Interlocked Instruction ............................................. 4-20b
Relationship of ILO to Any Clock Cycle ..........................................................................4-21
U/S Relationship to any Bus Cycle-Guaranteed Valid Interval ...................................................... 4-22
Abort Timing, FLT Not Applied ................................................................................. .4-23
Abort Timing, FLT Applied ...................................................................................... 4-24
2-301
fI
.... r---------------------------------------------------------------------------------,
ch
List of Illustrations (Continued)
.... Power·On Reset ..............................................................................................
4·25
U)
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Z
......
Q
....
ch
....
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Non·Power·On Reset .•....••..•............•..........................•.............•...................•.....4·26
INT Interrupt Signal Detection ..................................................................................4·27
NMllnterrupt Signal Timing ••...••....•......................................................•.....•.....•...... 4·28
Relationship Between Last Data Transfer of an Instruction and PFS
Pulse of Next Instruction .....................................................................................4·29
List of Tables
NS32C016 Addressing Modes ................................................................................... 2·1
NS32C016 Instruction Set Summary ..............................................................................2·2
Bus Cycle Categories ...........................................................................................3·1
Access Sequences .............................................................................................3·2
Interrupt Sequences ............................................................................................3·3
Floating Point Instruction Protocols ............................................................................... 3·4
Memory Management Instruction Protocols ........................................................................ 3·5
Custom Slave Instruction Protocols ............................................................................... 3·6
2·302
.--------------------------------------------------------------------------, z
(J)
1.0 Product Introduction
(0)
N
The Series 32000 Microprocessor family is a new generation of devices using National's XMaS and CMOS technologies. By combining state-of-the-art MaS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
cess, which allows a significant reduction in hardware and
software cost.
Software Processor Concept The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. The family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
• High-Level Language Support
• Easy Future Growth Path
Powerful Addressing Modes_ Nine addressing modes
available to all instructions are included to access data
structures efficiently.
• Application Flexibility
2.0 Architectural Description
Data Types_ The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes 16 registers on the
NS32C016 CPU.
SymmetriC Instruction Set While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
2.1.1 General Purpose Registers
There are eight registers for meeting high speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are thirty-two bits in
length. If a general register is specified for an operand that
is eight or sixteen bits long, only the low part of the register
is used; the high part is not referenced or modified.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided. This powerful memory-to-memory architecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
Memory Management Either the NS32382 or the
NS32082 Memory Management Unit may be added to the
system to provide advanced operating system support functions, including dynamic address translation, virtual memory
management, and memory protection.
2.1.2 Dedicated Registers
The eight dedicated registers of the NS32C016 are assigned specific functions.
PC: The PROGRAM COUNTER register is a pointer to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section. (In the
NS32C016 the upper eight bits of this register are always
zero.)
sPa, SP1: The SPO register points to the lowest address of
the last item stored on the INTERRUPT STACK. This stack
is normally used only by the operating system. It is used
primarily for storing temporary data, and holding return information for operating system subroutines and interrupt and
Large, Uniform Addressing. The NS32C016 has 24-bit address pointers that can address up to 16 megabytes without
any segmentation; this addressing scheme provides flexible
memory management without added-on expense.
Modular Software Support_ Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to ac-
GENERAL
DEDICATED
32
32
RD
PROGRAM COUNTER
PC
STATIC BASE
SB
FRAME POINTER
FP
Rl
R2
R3
USER STACK PTR.
INTERRUPT STACK PTR.
SPl }
SP
R4
SPO
RS
INTERRUPT BASE
PSR
MOD
STATUS
MODULE
:========:=======:
INTBASE
R6
R7 '--_ _ _ _ _-'-_ _--'-_ _--' TL/EE/8S2S-3
FIGURE 2-1. The General and Dedicated Registers
2-303
oo
.....
0)
.....
o
......
I
Z
(J)
(0)
N
oo
.....
.....
0)
I
U1
U)
.cD
.-
8
C'I
Cf)
U)
z
.....
o
.cD
.o
~
Cf)
U)
z
r---------------------------------------------------------------------------------,
2.0 Architectural Description
(Continued)
trap service routines. The SP1 register pOints to the lowest
address of the last item stored on the USER STACK. This
stack is used by normal user programs to hold temporary
data and subroutine return information.
F: The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions use it
to indicate overflow).
Z: The Z bit is altered by comparison instructions. In a comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is set to "0".
In this document, reference is made to the SP register. The
terms "SP register" or "SP" refer to either SPO or SP1,
depending on the setting of the S bit in the PSR register. If
the S bit in the PSR is 0 then SP refers to SPO. If the S bit in
the PSR is 1 then SP refers to SP1. (In the NS32C016 the
upper eight bits of these registers are always zero.)
N: The N bit is altered by comparison instructions. In a comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both operands are
interpreted as signed integers. Otherwise, it is set to "0".
Stacks in the Series 32000 family grow downward in memory. A Push operation pre-decrements the Stack Pointer by
the operand length. A Pop operation post-increments the
Stack Pointer by the operand length.
U: If the U bit is "1" no privileged instructions may be executed. If the U bit is "0" then all instructions may be executed. When U = 0 the NS32C016 is said to be in Supervisor
Mode; when U = 1 the NS32C016 is said to be in User
Mode. A User Mode program is restricted from executing
certain instructions and accessing certain registers which
could interfere with the operating system. For example, a
User Mode program is prevented from changing the setting
of the flag used to indicate its own privilege mode. A Supervisor Mode program is assumed to be a trusted part of the
operating system, hence it has no such restrictions.
FP: The FRAME POINTER register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
The frame pointer holds the address in memory occupied by
the old contents of the frame pOinter. (In the NS32C016 the
upper eight bits of this register are always zero.)
S: The S bit specifies whether the SPO register or SP1 register is used as the stack pointer. The bit is automatically
cleared on interrupts and traps. It may have a setting of 0
(use the SPO register) or 1 (use the SP1 register).
SB: The STATIC BASE register pOints to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module. (In the NS32C016 the upper eight bits of this register are always zero.)
P: The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3.8.5). It may have a setting
of 0 (no trace pending) or 1 (trace pending).
I: If 1= 1, then all interrupts will be accepted (Section 3.8). If
1=0, only the NMI interrupt is accepted. Trap enables are
not affected by this bit.
INTBASE: The INTERRUPT BASE register holds the address of the dispatch table for interrupts and traps (Section
3.8). The INTBASE register holds the lowest address in
memory occupied by the dispatch table. (in the NS32C016
the upper eight bits of this register are always zero.)
2.1.3 The Configuration Register (CFG)
Within the Control section of the NS32C016 CPU is the fourbit CFG Register, which declares the presence of certain
external devices. It is referenced by only one instruction,
SETCFG, which is intended to be executed only as part of
system initialization after reset. The format of the CFG Register is shown in Figure 2-3.
MOD: The MODULE register holds the address of the module descriptor of the currently executing software module.
The MOD register is sixteen bits long, therefore the module
table must be contained within the first 64k bytes of memory.
PSR: The PROCESSOR STATUS REGISTER (PSR) holds
the status codes for the NS32C016 microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all programs, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
15
817
FIGURE 2-3. CFG Register
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the NS32202 Interrupt Control Unit). If the CFG I bit is set, interrupts requested through
the INT pin are "Vectored." If it is clear, these interrupts are
"Non-Vectored." See Section 3.8.
0
IXIXIXD--fI-+-""'-+--+~-----1 RsTi
RSTO
1----....,.------1 iiSr/m
!L _____________ ..1I
EXTERNAL RESET
(OPTIONAL)
O!:50p.sec
RESET SWITCH
(OPTIONAL)
SYSTEM RESET
TUEE/B525-13
FIGURE 3-5a. Recommended Reset Connections, Non-Memory-Managed System
Vee
NS32C201
TCU
NS32082
MMU
NS32C016
CPU
1"'------------,
I
I
II RESET
1>-l-I-+-....,..-f--+~+-------I
I
RsTi
iiSTci
!L _____________ ..1:
EXTERNAL RESET
(OPTIONAL)
2:
SOj..lsec
RESET SWITCH
(OPTIONAL)
TUEE/B525-14
FIGURE 3-5b. Recommended Reset Connections, Memory-Managed System
3) To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
3.4 BUS CYCLES
The NS32C016 CPU has a strap option which defines the
Bus Timing Mode as either With or Without Address Translation. This section describes only bus cycles under the No
Address Translation option. For details of the use of the
strap and of bus cycles with address translation, see Section 3.5.
4) To transfer information to or from a Slave Processor.
In terms of bus timing, cases 1 through 3 above are identical. For timing specifications, see Section 4. The only external difference between them is the four-bit code placed on
the Bus Status pins (STO-ST3). Slave Processor cycles differ in that separate control signals are applied (Section
3.4.6).
The CPU will perform a bus cycle for one of the following
reasons:
1) To write or read data, to or from memory or a peripheral
interface device. Peripheral input and output are memory-mapped in the Series 32000 family.
The sequence of events in a non-Slave bus cycle is shown
in Figure 3-7 for a Read cycle and Figure 3-8 for a Write
cycle. The cases shown assume that the selected memory
or interface device is capable of communicating with the
CPU at full speed. If it is not, then cycle extension may be
requested through the ROY line (Section 3.4.1).
2) To fetch instructions into the eight-byte instruction
queue. This happens whenever the bus would otherwise
be idle and the queue is not already full.
2-313
Q
......
Z
UJ
c.:I
N
o
Q
....
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.... r---------------------------------------------------------------------------------,
U)
ch
....
8C'oI
~
Z
c;
....
....ch
~
CO)
en
z
3.0 Functional Description (Continued)
A full-speed bus cycle is performed in four cycles of the
PHI1 clock signal, labeled T1 through T4. Clock cycles not
associated with a bus cycle are designated Ti (for "Idle").
During T1, the C~U applies an address on pins ADO-AD15
and A16-A23. It also provides a low-going pulse on the
ADS pin, which serves the dual purpose of informing external circuitry that a bus cycle is starting and of providing control to an external latch for demultiplexing Address bits 015 from the ADO-AD15 pins. See Figure 3-6. During this
time also the status signals DDIN, indicating the direction of
the transfer, and HBE, indicating whether the high byte
(AD8-AD15) is to be referenced, become valid.
During T2 the CPU switches the Data Bus, ADO-AD15, to
either accept or present data. Note that the signals A 16A23 remain valid, and need not be latched. It also starts the
data strobe (DS), signaling the beginning of the data transfer. Associated signals from the NS32C201 Timing Control
Unit are also activated at this time: RD (Read Strobe) or WR
(Write Strobe), TSO (Timing State Output, indicating that T2
has been reached) and DBE (Data Buffer Enable).
PHil
The T3 state provides for access time reqUirements, and it
occurs at least once in a bus cycle. At the end of T2, on the
falling edge of the PHI2 clock, the RDY (Ready) line is sampled to determine whether the bus cycle will be extended
(Section 3.4.1).
If the CPU is performing a Read cycle, the Data Bus (ADOAD15) is sampled at the falling edge of PHI2 of the last T3
state, see Section 4. Data must, however, be held at least
until the beginning of T4. DS and RD are guaranteed not to
go inactive before this point, so the rising edge of either of
them may safely be used to disable the device providing the
input data.
The T4 state finishes the bus cycle. At the beginning of T4,
the DS, RD, or WR, and TSO signals go inactive, and at the
rising edge of PHI2, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles remains valid from the CPU throughout T4. Note that the Bus
Status lines (STO-ST3) change at the beginning of T4, anticipating the following bus cycle (if any).
PHI2
AD
AD~--------------------~
NS32C201
WR
Wii~--------------------'fSo
1iO~--------------------TL/EE/8525-15
FIGURE 3·6. Bus Connections
2-314
3.0 Functional Description
z
en
w
I\)
n
Q
(Continued)
NS32COI & CPU BUS SIGNALS
I
PHil
T40RTi
I
n
T2
T3
T4
nORTi
....
....•
I
G)
[
Q
......
Z
en
w
I\)
PHI 2
n
Q
[
A16·A23
[
AOO·ADI5
[
ADS
[
ST()'ST3
[
ODIN
[
Hii
[
Os
[
RDV
[
....
•
....
CI1
G)
TL/EE/8525-16
FIGURE 3-7. Read Cycle Timing
2·315
lot)
.,...
•
CD
.,...
Q
oN
3.0 Functional Description
(Continued)
NS32C016 CPU BUS SIGNALS
M
U)
T1
Z
.
C;)
.,...
CD
.,...
PHI.1
[
PHI2
[
T2
T3
T4
I
T1 ORTi
I
Q
o
N
M
U)
Z
A16·A23 [
ADO-AD1S [
ADS
[
STO·ST3
[
Di5iN
[
HBE
[
OS
[
ROY
[
DBE
TL/EE/B525-17
FIGURE 3·8. Write Cycle Timing
2·316
z
3.0 Functional Description
(J)
Co)
I\)
(Continued)
3.4.1 Cycle Extension
The ROY pin is driven by the NS32C201 Timing Control
Unit, which applies WAIT States to the CPU as requested
on three sets of pins:
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32C016 provides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-1 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are flat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the ROY (Ready) pin.
At the end of T2 on the falling edge of PHI2, the ROY line is
sampled by the CPU. If ROY is high, the next T -states will be
T3 and then T4, ending the bus cycle. If it is sampled low,
then another T3 state will be inserted after the next T·state
and the ROY line will again be sampled on the falling edge
of PHI2. Each additional T3 state after the first is referred to
as a "wait state." See Figure 3-9.
T1
T2
1) CWAIT (Continues WAIT), which holds the CPU in WAIT
states until removed.
2) WAIT1, WAIT2, WAIT4, WAIT8 (Collectively WAITn),
which may be given a four-bit binary value requesting a
specific number of WAIT States from 0 to 15.
3) PER (Peripheral), which inserts five additional WAIT
states and causes the TCU to reshape the RO and WR
strobes. This provides the setup and hold times required
by most MOS peripheral interface devices.
o
o
....
cp
....
o
.......
Z
(J)
Co)
I\)
oo
....
.....
c.n
CJ)
Combinations of these various WAIT requests are both legal
and useful. For details of their use, see the NS32C201 TCU
Oata Sheet.
Figure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the TCU WAITn pins.
T3
I
T3
(WAin
T4
PHil
PHI 2
ROY
TLlEE/8525-l8
FIGURE 3-9. ROY Pin Timing
3.4.2 Bus Status
expecting a vector number to be provided from
the Master NS32202 Interrupt Control Unit. If
the vectoring mode selected by the last
SETCFG instruction was Non-Vectored, then
the CPU will ignore the value it has read and will
use a default vector instead, having assumed
that no NS32202 is present. See Section 3.4.5.
The NS32C016 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on
these pins indicate why the CPU is performing a bus cycle,
or, if it is idle on the bus, then why it is idle.
Referring to Figures 3-1 and 3-8, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1, and changing to the next state at T4. This allows
the system designer to fully decode the Bus Status and, if
desired, latch the decoded signals before ADS initiates the
Bus Cycle.
0101 -
Interrupt Acknowledge, Cascaded.
The CPU is reading a vector number from a
Cascaded NS32202 Interrupt Control Unit. The
address provided is the address of the
NS32202 Hardware Vector register. See Section 3.4.5.
The Bus Status pins are interpreted as a four-bit value, with
STO the least significant bit. Their values decode as follows:
The bus is idle because the CPU does not need
to perform a bus access.
The bus is idle because the CPU is executing
the WAIT instruction.
0110- End of Interrupt, Master.
0010 -
(Reserved for future use.)
0111 -
End of Interrupt, Cascaded.
0011 -
The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100 -
Interrupt Acknowledge, Master.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt
(on NMI) it will read from address FFFF0016,
but will ignore any data provided.
1000 -
The CPU is reading from a Cascaded Interrupt
Control Unit to indicate that it is returning
(through RETI) from an interrupt service routine
requested by that unit. See Section 3.4.5.
Sequential Instruction Fetch.
0000 0001 -
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt
(RETI) instruction. See Section 3.4.5.
The CPU is reading the next sequential word
from the instruction stream into the Instruction
Queue. It will do so whenever the bus would
otherwise be idle and the queue is not already
full.
To acknowledge receipt of a Maskable Interrupt
(on INT) it will read from address FFFE0016,
2-317
•
....
....oc.b
~
~r-----------------------------------------------------------------.
3.0 Functional Description
NS32C018 CPU BUS SIGNALS
PREV.CYCLE
(/)
z
.....
CD
....
8
C;
IT40RTII
PHil [
PHI2 [
N
~
Z
(Continued)
AI6-A23 [
AIlG-ADI5 [
T2
I
T3
I (W~T) I (vlllT) I
NEXT CYCLE
T4
InORTl1
_IL ILrL IL!LIL!L!L
- Ul J1LJ1 LJ1 U1 U- J1 J1 ~ ~ OC
~
NEXT ADDR
IV
---
NEXTA~R
V
~~
X
STATUS VALID
NEXT STATUS
;;;;;;'"""
DoiN[ ~ rw0 ~
iiiF.[ ~ ~ ~
-
r-
ADDRESS VALID
~
~
ADDR
~IN
VALID
~--~ ~ ~
~~
AiiS[
STO-ST3 [
I
TI
E
VALID
V
II-
1\
NS32C201 TCU EXTENSION SIGNALS
~
~
CWAiT[ %: ~ ~
PER [ ~ ~
WI
WAiTn[ ~ ~ ~
i
~~~~~
~ ~ ~ ~~~ %
t
~
S t~
. t
~
~ ~ ~~
I
ROY [
(TCUTOCP U)
NS32C201 TCU BUS SIGNALS
II
-V
-/
iiBe[ - -1
- /
V
r"\
TL/EE/B525-19
FIGURE 3·10. Extended Cycle Example
Note: Arrows on CWAi'f, PEi'i. WAITn indicate points at which the TCU samples. Arrows on AOO-A015 and
ROY indicate points at which the CPU samples.
2·318
z
en
Co)
3.0 Functional Description (Continued)
N
1001 -
Non-Sequential Instruction Fetch.
The CPU is performing the first fetch of instruction code after the Instruction Queue is purged.
This will occur as a result of any jump or branch,
or any interrupt or trap, or execution of certain
instructions.
1010- Data Transfer.
The CPU is reading or writing an operand of an
instruction.
1011 -
1100 -
Memory is organized as two eight-bit banks, each bank receiving the word address (A 1-A23) in parallel. One bank,
connected to Data Bus pins ADO-AD7, is enabled to respond to even byte addresses; i.e., when the least significant address bit (AO) is low. The other bank, connected to
Data Bus pins AD8-AD15, is enabled when HBE is low. See
Figure 3-11.
HBE
Read RMW Operand.
The CPU is reading an operand which will subsequently be modified and rewritten. If memory
protection circuitry would not allow the following
Write cycle, it must abort this cycle.
Read for Effective Address Calculation.
The CPU is reading information from memory in
order to determine the Effective Address of an
operand. This will occur whenever an instruction uses the Memory Relative or External addressing mode.
AO(LBE)
n
Q
....
....•
en
Q
.......
Z
en
Co)
N
n
Q
....
•
....
C7I
en
Al·A23
1101 -
Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing the Operation Word of a Slave Processor
instruction. See Section 3.9.1.
1110- Read Slave Processor Status.
The CPU is reading a Status Word from a Slave
Processor. This occurs after the Slave Processor has signalled completion of an instruction.
The transferred word tells the CPU whether a
trap should be taken, and in some instructions it
presents new values for the CPU Processor
Status Register bits N, Z, L or F. See Section
3.9.1.
1111 Broadcast Slave 10.
The CPU is initiating the execution of a Slave
Processor instruction. The 10 Byte (first byte of
the instruction) is sent to all Slave Processors,
one of which will recognize it. From this point
the CPU is communicating with only one Slave
Processor. See Section 3.9.1.
TL/EE/B525-20
FIGURE 3·11. Memory Interface
Any bus cycle falls into one of three categories: Even Byte
Access, Odd Byte Access, and Even Word Access. All accesses to any data type are made up of sequences of these
cycles. Table 3-1 gives the state of AO and HBE for each
category.
TABLE 3·1. Bus Cycle Categories
HBE
AO
Category
o
Even Byte
Odd Byte
o
o
o
Even Word
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-States separating
them. The number of bus cycles required to transfer an operand depends on its size and its alignment (i.e., whether it
starts on an even byte address or an odd byte address).
Table 3-2 lists the bus cycle performed for each situation.
For the timing of AO and HBE, see Section 3.4.
3.4.3 Data Access Sequences
The 24-bit address provided by the NS32C016 is a byte
address; that is, it uniquely identifies one of up to
16,777,216 eight-bit memory locations. An'important feature
of the NS32C016 is that the presence of a 16-bit data bus
imposes no restrictions on data alignment; any data item,
regardless of size, may be placed starting at any memory
address. The NS32C016 provides a special control Signal,
High Byte Enable (HBE), which facilitates individual byte addressing on a 16-bit bus.
2-319
•
....•
CD
....
0
It)
3.0 Functional Description
(Continued)
0
TABLE 3-2. Access Sequences
N
C")
en
Z
.....
0
Cycle
Type
Address
....
tb
....
0
HBE
AO
Low Bus
A. Odd Word Access Sequence
0
BYTE 1
N
C")
en
Z
High Bus
2
Odd Byte
Even Byte
A
A+1
0
1
1
0
Byte 0
Don't Care
BYTE 0
-A
Don't Care
Byte 1
B. Even Double-Word Access Sequence
1
2
Even Word
Even Word
A
A+2
BYTE 3
BYTE 2
0
0
0
0
BYTE 1
Byte 1
Byte 3
BYTE 0
-A
Byte 0
Byte 2
C. Odd Double-Word Access Sequence
2
3
Odd Byte
Even Word
Even Byte
A
A+1
A+3
BYTE 3
BYTE 2
0
0
1
0
0
BYTE 1
Byte 0
Byte 2
Don't Care
BYTE 0
-A
Don't Care
Byte 1
Byte 3
D. Even Quad-Word Access Sequence
BYTE 7
2
BYTE 6
BYTES
Even Word
Even Word
BYTE 3
BYTE 4
A
A+2
BYTE 2
BYTE 1
0
0
0
0
Byte 1
Byte 3
0
0
0
0
Byte 5
Byte 7
BYTE 0
Byte 0
Byte 2
Byte 4
ByteS
-A
Other bus cycles (instruction prefetch or slave) can occur here.
3
4
Even Word
Even Word
A+4
A+S
E Odd Quad-Word Access Sequence
BYTE 7
1
2
3
BYTE 6
Odd Byte
Even Word
Even Byte
BYTES
BYTE 4
BYTE 3
A
A+1
A+3
0
0
BYTE 2
BYTE 1
BYTE 0
0
0
Byte 0
Byte 2
Don't Care
Don't Care
Byte 1
Byte 3
0
0
Byte 4
ByteS
Don't Care
Don't Care
Byte 5
Byte 7
Other bus cycles (instruction prefetch or slave) can occur here.
4
5
S
Odd Byte
Even Word
Even Byte
A+4
A+5
A+7
0
0
2-320
-A
3.0 Functional Description
(Continued)
3.4.3.1 Bit Accesses
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full. Sequential Fetches are always
Even Word Read cycles (Table 3-1).
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the instruction queue, causing the
next instruction fetch to display Non-Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status, and that cycle is either an Even Word Read or an
Odd Byte Read, depending on whether the destination address is even or odd.
The Bit Instructions perform byte accesses to the byte containing the designated bit. The Test and Set Bit instruction
(SBIT), for example, reads a byte, alters it, and rewrites it,
having changed the contents of one bit.
3.4.3.2 Bit Field Accesses
An access to a Bit Field in memory always generates a Double·Word transfer at the address containing the least significant bit of the field. The Double Word is read by an Extract
instruction; an Insert instruction reads a Double Word, modi·
fies it, and rewrites it.
3.4.3.3 Extending Multiply Accesses
The Extending Multiply Instruction (MEl) will return a result
which is twice the size in bytes of the operand it reads. I! the
multiplicand is in memory, the most·significant hal! of the
result is written first (at the higher address), then the leastsignificant half. This is done in order to support retry if this
instruction is aborted.
3.4.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is interrupt control rather
than the transfer of instructions or data. Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status presented on pins STO-ST3. All
Interrupt Control cycles are single-byte Read cycles.
3.4.4 Instruction Fetches
Instructions for the NS32C016 CPU are "prefetched"; that
is, they are input before being needed into the next available
entry of the eight·byte Instruction Queue. The CPU performs
two types of Instruction Fetch cycles: Sequential and Non·
Sequential. These can be distinguished from each other by
their differing status combinations on pins STO-ST3 (Section 3.4.2).
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine. For full details of the NS32C016 interrupt
structure, see Section 3.8.
2-321
z
en
C.:I
N
oo
....
....o
0)
I
.......
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en
C.:I
N
oo
....
....
0)
I
U1
an
....
"'....
3.0 Functional Description (Continued)
CI
~
(/)
Z
TABLE 3-3. Interrupt Sequences
Cycle
Status
AO
Address
High Bus
Low Bus
C;;
....•
CD
....
8
A. Non·Maskable Interrupt Control Sequences.
C'I
Interrupt Acknowledge
1
0100
Z
Interrupt Return
~
FFFF0016
o
o
Don't Care
Don't Care
None: Performed through Return from Trap (RETT) instruction.
B. Non· Vectored Interrupt Control Sequences.
Interrupt Acknowledge
1
0100
FFFE0016
o
o
Don't Care
Don't Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
C. Vectored Interrupt Sequences: Non·Cascaded
Interrupt Acknowledge
1
0100
FFFE0016
o
o
Don't Care
Vector:
Range: 0-127
Interrupt Return
1
0110
FFFE0016
o
o
Don't Care
Vector: Same as
in Previous Int.
Ack.Cycle
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
1
0100
FFFE0016
o
o
Don't Care
Cascade Index:
range -16to-l
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0101
Cascade
0
lOr
0 or
O'
Address
l'
Vector, range 0-255; on appropriate
half of Data Bus for even/odd address
Interrupt Return
0110
1
Don't Care
Cascade Index:
same as in
previous Int.
Ack.Cycle
Don't Care
Don't Care
FFFE0016
o
o
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0111
Cascade
0
1 or
0 or
O'
l'
Address
• If the Cascaded ICU Address is Even (AO is low), then the CPU applies RBE high and reads the vector number from bits 0-7 of the Data Bus.
If the address is Odd (AO is high). then the CPU applies RBE low and reads the vector number from bits 8-15 of the Data Bus. The vector number may be In the
range 0-255.
2-322
z
3.0 Functional Description
en
Co)
(Continued)
N
C')
3.4.6 Slave Processor Communication
AO(D-15)
In addition to its use as the Address Translation strap (Section 3.5.1), the AT/SPC pin is used as the data strobe for
Slave Processor transfers. In this role, it is referred to as
Slave Processor Control (SPC). In a Slave Processor bus
cycle, data is transferred on the Data Bus (ADO-AD15), and
the status lines STO-ST3 are monitored by each Slave
Processor in order to determine the type of transfer being
performed. SPC is bidirectional, but is driven by the CPU
during all Slave Processor bus cycles. See Section 3.9 for
full protocol sequences.
A'f/SPC
A
"
NS32C016
CPU
J\.
....ocp
....
0(11-15)
SPC
SLAVE
PROCESSOR
~
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STO-ST3
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C')
STO-ST3
....
....
CJI
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,
TL/EE/6525-21
FIGURE 3-12. Slave Processor Connections
PREV.CYCLE
I
PHil
[
PHI 2
[
SPC
[
T40rTi
Tl
T4
I
NEXT CYCLE
Tl0RTi
I
STO-ST3 [
fII
ADS
HBE
[
[~~~~~~L-----r-------+L------+-
-OB-E (3)[
-1-----1
TL/EE/6525-22
Notes:
(1) CPU samples Data Bus here.
(2) DBE and all other NS32C201 TCU bus signals remain inactive because no ADS pulse is received from the CPU.
FIGURE 3·13. CPU Read from Slave Processor
2-323
....
ch
....
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o
~
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C;
....•
....CD
8
~
~
z
3.0 Functional Description (Continued)
3.4.6.1 Slave Processor Bus Cycles
sequence ("protocol") established by the instruction under
execution; but the CPU indicates the direction on the DDIN
pin for hardware debugging purposes.
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3-13 and 3-14).
During a Read cycle SPC is active from the beginning of T1
to the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock period, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1 ,
removing SPC at T 4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
3.4.6.2 Slave Operand Transfer Sequences
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (ADO-AD7), and a
Word operand is transferred on the entire bus. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-significant word to most-significant.
Since the CPU does not pulse the Address Strobe (ADS),
no bus signals are generated by the NS32C201 Timing Control Unit. The direction of a transfer is determined by the
PREV.CYCLE
I
PHil
[
sPC
[
T4 OR Ti
NEXT CYCLE
T1
T4
T1 ORTi
I
ADO-AD15 [
STO-ST3 [
ADS
[
ODIN
[
HBE
[£4~~~~~----~------~~----1-
DBE (21 [
-+_....J
TLlEE/B525-23
Notes:
(11 Slave Processor samples Data Bus here.
(21 DBE, being provided by the NS32C201 TCU, remains inactive due to the fact that no pulse is presented on ADS.
TCU signals RD, WR and TSO also remain inactive.
FIGURE 3-14. CPU Write to Slave Processor
2-324
z
3.0 Functional Description
en
Co)
(Continued)
N
3.5 MEMORY MANAGEMENT OPTION
The NS32C016 CPU, in conjunction with the NS32082
Memory Management Unit (MMU), provides full support for
address translation, memory protection, and memory allocation techniques up to and including Virtual Memory.
Iy described in Section 3.4. If it is sampled as low, two
changes occur:
1) An extra clock cycle, Tmmu, is inserted into all bus
cycles except Slave Processor transfers.
2) The DS/FLT pin changes in function from a Data
Strobe output (DS) to a Float Command input (FLT).
The NS32082 MMU will itself pull the CPU AT/SPC pin low
when it is reset. In non-Memory·Managed systems this pin
should be pulled up to Vee through a 10 kfl resistor.
Note that the Address Translation strap does not specifically declare the presence of an NS32082 MMU, but only the
3.5.1 Address Translation Strap
The Bus Interface Control section of the NS32C016 CPU
has two bus timing modes: With or Without Address Translation. The mode of operation is selected by the CPU by
sampling the ATISPC (Address TranslationlSlave Processor Control) pin on the rising edge of the RST (Reset) pulse.
If ATISPC is sampled as high, the bus timing is as previous-
I
PHil
[
PHI2
[
T40RTi
I
T3
T1
o
o
.....
0)
.....
.
o
......
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N
oo
.....
.....•
0)
U1
T4
A16-A23 [
ADO-AD1S [
ADS
[
STO-ST3
[
ODIN
[
HBE
[
ROY
[
•
TL/EE/6S2S-24
FIGURE 3-15. Read Cycle with Address Translation (CPU Action)
2-325
.
U) r-------------------------------------------------------------------------------~
.....
CD
.....
o
oN
en
CO)
z
......
o
.....
CD
.....
.
o
oN
en
CO)
z
3.0 Functional Description
(Continued)
their counter-parts without Address Translation, with the exception that the CPU Address lines A16-A23 remain in the
TRI-STATE condition. This allows the MMU to continue asserting the translated address on those pins.
Note that in order for the NS32082 MMU to operate correctly, it must be set to the 32C016 mode by forcing A24 high
during reset.
Figures 3-17and 3-18 show a Read cycle and a Write cycle
as generated by the 32C016/32082/32C201 group. Note
that with the CPU ADS signal going only to the MMU, and
with the MMU PAV signal substituting for ADS everywhere
else, Tmmu through T4100k exactly like Tl through T4 in a
non-Memory-Managed system. For the connection diagram,
see Appendix B.
presence of external address translation circuitry. MMU instructions will still trap as being undefined unless the
SETCFG (Set Configuration) instruction is executed to declare the MMU instruction set valid. See Section 2.1.3.
3.5.2 Translated Bus Timing
Figures 3-15 and 3-16 illustrate the CPU activity during a
Read cycle and a Write cycle in Address Translation mode.
The additional T-State, Tmmu, is inserted between Tl and
T2. During this time the CPU places ADO-ADI5 and A16A23 into the TRI-STATE® mode, allowing the MMU to assert the translated address and issue the physical address
strobe PAV. T2 through T4 of the cycle are identical to
I
PHI1
T40RT;
I
T1
Tmmu
I
T2
T3
T4
[
PHI2
A16-A23
ADO-AD1S
[
[
ADS
[
STO·ST3
[
ODIN
[
HBE
[
ROY
[
TL/EE/8525-25
FIGURE 3-16. Write Cycle with Address Translation (CPU Action)
2-326
z
3.0 Functional Description
en
c.:I
(Continued)
N
n
o
....
....
o
cp
NS32C016 CPU BUS SIGNALS
I
T40RTi
I
T1
I
Tmmu
I
T2
T3
T4
I
T. ORT,
......
z
I
en
c.:I
N
n
o
PHil [
PHI2
....cp
....
[
A16·A23
[
ADO·AD15
[
U'I
AiiS[
PiW[
5TO·5T3 [
ODIN
HBE
[~~~"~~----+------+----~~------r------+L-----+-
[~~L£'"I~ L--+---+----+I----+-.J '-+----i-
iiD[
DBE [
TSO [
TLlEE/8525-26
FIGURE 3·17. Memory-Managed Read Cycle
2·327
.....
....o
It)
CD
3.0 Functional Description
(Continued)
o
C\I
(I)
en
NS32C016 CPU BUS SIGNALS
z
......
I
.
....
CD
....
o
o
T40RTi
I
TI
Tmmu
I
T2
13
T4
I
TlORTi
I
PHil [
oC\I
(I)
en
z
PHI 2 [
I
PHYSICAL
A16-A23 [
ADDRESS VALID
DATA OUT
ADO-AD 15 [
ADS [
PAV[
STO-ST3 [
STATUS VALID
NEXT STATUS
ODIN [
HBE [
VALID
ROY [
NS32C201 TCU BUS SIGNALS
TL/EE/B525-27
FIGURE 3-18. Memory-Managed Write Cycle
2-328
3.0 Functional Description
z
en
to)
(Continued)
I\)
3.5.3 The FLT (Float) Pin
1)
The FLT pin is used by the CPU for address translation
support. Activating FLT during Tmmu causes the CPU to
wait longer than Tmmu for address translation and validation. This feature is used occasionally by the NS32082 MMU
in order to update its internal translation Look-Aside Buffer
(TLB) from page tables in memory, or to update certain
status bits within them.
Sets ADO-AD15, A16-A23 and ODIN to the TRI·
STATE condition ("floating").
2)
3)
Sets HBE low.
Suspends further internal processing of the current instruction. This ensures that the current instruction remains abortable with retry. (See RST / ABT description,
Section 3.5.4.)
Note that the ADO-AD15 pins may be briefly asserted duro
ing the first idle T·State. The above conditions remain in
effect until FLT again goes high. See the Timing Specifica·
tions, Section 4.
Figure 3-19 shows the effects of FLT. Upon sampling FLT
low, late in Tmmu, the CPU enters idle T·States (Tf) during
which it:
TL/EE/8525-28
FIGURE 3-19. FLT Timing
2·329
oo
....
....
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Q)
I
........
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oo
....
....
Q)
I
U1
....
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....
8
&I)
C\I
~
Z
.....
Q
....
....•
CD
Q
U
C\I
CO)
tn
Z
3.0 Functional Description (Continued)
3.5_4 Aborting Bus Cycles
2)
The RSTI ABT pin, apart from its Reset function (Section
3.3), also serves as the means to "abort," or cancel, a bus
cycle and the instruction, if any, which initiated it. An Abort
request is distinguished from a Reset in that the RSiI ABT
pin is held active for only one clock cycle.
3)
The Write half of a Read-Modify-Write operand access
may not be aborted. The CPU guarantees that this will
never be necessary for Memory Management funtions
by applying a special RMW status (Status Code 1011)
during the Read half of the access. When the CPU
presents RMW status, that cycle must be aborted if it
would be illegal to write to any of the accessed addresses.
If RSiIABi is pulsed at any time other than as indicated
above, it will abort either the instruction currently under execution or the next instruction and will act as a very high-priority interrupt. However, the program that was running at the
time is not guaranteed recoverable.
If RSTI ABT is pulled low during Tmmu or Tf, this signals
that the cycle must be aborted. The CPU itself will enter T2
and then Ti, thereby terminating the cycle. Since it is the
MMU PAY Signal which triggers a physical cycle, the rest of
the system remains unaware that a cycle was started.
The NS32082 MMU will abort a bus cycle for either of two
reasons:
1)
The CPU is attempting to access a virtual address
which is not currently resident in physical memory. The
reference page must be brought into physical memory
from mass storage to make it accessible to the CPU.
2)
The CPU is attempting to perform an access which is
not allowed by the protection level assigned to that
page.
3.6 BUS ACCESS CONTROL
The NS32C016 CPU has the capability of relinquishing its
access to the bus upon request from a DMA device or another CPU. This capability is implemented on the HOLD
(Hold Request) and HLDA (Hold Acknowledge) pins. By asserting HOLD low, an external device requests access to
the bus. On receipt of HLDA from the CPU, the device may
perform bus cycles, as the CPU at this point has set the
ADO-AD15, A16-A23, ADS, ODIN and HBE pins to the
TRI-STATE condition. To return control of the bus to the
CPU, the device sets HOLD inactive, and the CPU acknowledges return of the bus by setting HLDA inactive.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made,
as the CPU must always complete the current bus cycle.
Figure 3-20 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-21 shows the sequence
if the CPU is using the bus at the time that the HOLD request is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
In a Memory-Managed system, the HLDA Signal is connected in a daisy-chain through the NS32082, so that the MMU
can release the bus if it is using it.
When a bus cycle is aborted by the MMU, the instruction
that caused it to occur is also aborted in such a manner that
it is guaranteed re-executable later. The information that is
changed irrecoverably by such a partly-executed instruction
does not affect its re-execution.
3.5.4.1 The Abort Interrupt
Upon aborting an instruction. the CPU immediately performs
an interrupt through the ABT vector in the Interrupt Table
(see Section 3.8). The Return Address pushed on the Interrupt Stack is the address of the aborted instruction, so that
a Return from Trap (RETT) instruction will automatically retry it.
The one exception to this sequence occurs if the aborted
bus cycle was an instruction prefetch. If so, it is not yet
certain that the aborted prefetched code is to be executed.
Instead of causing an interrupt, the CPU only aborts the bus
cycle, and stops prefetching. If the information in the Instruction Queue runs out, meaning that the instruction will
actually be executed, the ABT interrupt will occur, in effect
aborting the instruction that was being fetched.
3.5.4.2 Hardware Considerations
In order to guarantee instruction retry, certain rules must be
followed in applying an Abort to the CPU. These rules are
followed by the NS32082 Memory Management Unit.
1)
If FLT has been applied to the CPU, the Abort pulse
must be applied before the T-State in which FLT goes
inactive. The CPU will not actually respond to the Abort
command until FLT is removed. See Figure 4-24.
If FLT has not been applied to the CPU, the Abort
pulse must occur during or before Tmmu. See the Timing Specifications, Figure 4-23.
2-330
3.0 Functional Description
z
en
~
(Continued)
o
CI
....
....•
G)
I
TI
I
TI
I··· I
TI
TI
I
TIOAT4
I
TIORTI
I
~
z
en
PHI1[hJLj
c.:I
I\)
oCI
....
....
en
.
G)
PHI2 [
H&D[
HLDi[
AFFECTED SIGNALS
i6S[
0&[
-----
~[
~~------
-------
1~-----
-----
---- 1r----------
HiE [
ADO-AD15 [
:.q:~.L.L.L.Lf'
TL/EE/8525-29
FIGURE 3-20. HOLD Timing, Bus Initially Idle
2·331
.... r---------------------------------------------------------------------------------,
U)
cb
8
3.0 Functional Description (Continued)
N
~
Z
;:;
....
•
PHll[
z
PHlz[
~
CO)
en
T4
T3
....
o
CD
n
Ti
Ti
Ti
HOlD [
u[
AFFECTED SIGNALS
iDS [
1---- ----
DDiN[ -+__-ir-_VA_L_ID-;_ _ _-t' ---
iiii[ -+___-If-~_A_LID_+
_ __IJ
--
~~---
----
NEXT
~~--
----
NEXT
NEXTADDR
A16-A23 [
+ __-iI-_VA_Li_D-I_ _ _-t'
TLlEE/8525-30
FIGURE 3·21. HOLD Timing, Bus Initially Not Idle
2-332
z
3.0 Functional Description
en
Co)
(Continued)
N
3.7 INSTRUCTION STATUS
In addition, there is a set of internally-generated "traps"
which cause interrupt service to be performed as a result
either of exceptional conditions (e.g., attempted division by
zero) or of specific instructions whose purpose is to cause a
trap to occur (e.g., the SupervisDr Call instruction).
In addition to the four bits of Bus Cycle status (STO-ST3),
the NS32C016 CPU also presents Instruction Status information on three separate pins. These pins differ from STOST3 in that they are synchronous to the CPU's internal instruction execution section rather than to its bus interface
section.
3.8.1 Generallnterrupt/Trap Sequence
Upon receipt of an interrupt or trap request, the CPU goes
through three major steps:
PFS (Program Flow Status) is pulsed low as each instruction
begins execution. It is intended for debugging purposes, and
is used that way by the NS32082 Memory Management
Unit.
1)
UIS originates from the U bit of the Processor Status Register, and indicates whether the CPU is currently running in
User or Supervisor mode. It is sampled by the MMU for
mapping, protection and debugging purposes. Although it is
not synchronous to bus cycles, there are guarantees on its
validity during any given bus cycle. See the Timing Specifications, Figure 4-22.
ILO (Interlocked Operation) is activated during an SBITI (Set
Bit, Interlocked) or CBITI (Clear Bit, Interlocked) instruction.
It is made available to external bus arbitration circuitry in
order to allow these instructions to implement the semaphore primitive operations for multi-processor communication and resource sharing. As with the UIS pin, there are
guarantees on its validity during the operand accesses performed by the instructions. See the Timing Specification
Section, Figure 4-20.
2)
3)
Adjustment Df Registers.
Depending on the source of the interrupt or trap, the
CPU may restore and/or adjust the contents of the
Program Counter (PC), the Processor Status Register
(PSR) and the currently-selected Stack Pointer (SP). A
copy of the PSR is made, and the PSR is then set to
reflect Supervisor Mode and selection of the Interrupt
Stack.
Vector Acquisition.
A Vector is either obtained from the Data Bus or is
supplied by default.
Service Call.
The Vector is used as an index into the Interrupt Dispatch Table, whose base address is taken from the
CPU Interrupt Base (INTBASE) Register. See Figure
3-22. A 32-bit External Procedure Descriptor is read
from the table entry, and an External Procedure Call is
performed using it. The MOD Register (16 bits) and
Program Counter (32 bits) are pushed on the Interrupt
Stack.
This process is illustrated in Figure 3-23, from the viewpoint
of the programmer.
3.8 NS32C016 INTERRUPT STRUCTURE
INT, on which maskable interrupts may be requested,
NMI, on which non-maskable interrupts may be requested,and
RST/ABT, which may be used to abort a bus cycle and
any associated instruction. See Section 3.5.4.
,~
MEMORY
/
CASCADE TAB~E
I
"1'"
;
···
~~
CASCADE ADDR 14
CASCADE ADDR 15
FIXED INTERRUPTS
AND TRAPS
VECTORED
INTERRUPTS
01'"'
'31
CASCAOE ADDR 0
I~,"~"M"~1
r
REGISTER
~
1
DISPATCH
TAB~E
:t
0
NVI
NON·VECTORED INTERRUPT
1
NMI
NON-MASKAB~E
INTERRUPT
2
ABT
ABORT
3
S~VE
S~VE
4
I~~
ILLEGAL OPERATION TRAP
PROCESSDR TRAP
5
svc
SUPERVISOR CALL TRAP
6
DVZ
DIVIDE BY ZERO TRAP
7
F~G
F ~AG TRAP
B
BPT
BREAKPOINT TRAP
9
TRC
TRACE TRAP
III
UND
UNDEFINED INSTRUCTION TRAP
11-15 ~ ~ RESERVED
16
,. ....
VECTORED
INTERRUPTS
~
A..
TLlEE/B525-31
FIGURE 3-22. Interrupt Dispatch and Cascade Tables
2-333
o
o
....
cp
....
o
.......
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en
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N
oo
....en
....
I
CTI
....
....rD
8
~ .-----------------------------------------------------------------------------~
3.0 Functional Description
(Continued)
C'I
C")
en
z
Ci
....
rD
....
CI
~
I
I
I (PUSH)
RETURN ADDRESS
32 BITS
J
I
STATUS
PSR
1
I
I (PUSH)
MODULE
32 BITS
MOD
INTERRUPT
STACK
en
z
TL/EE/8525-32
r-------------l
I
I
I
I
I
INTBASE REGISTER
I
CASCADE TABLE
I
I
DISPATCH
TABLE
DESCRIPTOR (32 BITS)
1. ....----16----."1'"1:---16----.1
DESCRIPTOR
OFFSET
MODULE
MOD REGISTER
l
-=t-J
0
MODULE TABLE
NEW MODULE
I
MODULE TABLE ENTRY
J
MODULET~LEENTRY
32
-
STATIC BASE POINTER
------
LINK BASE PDlNTER
PROGRAM BASE POINTER
+
(RESERVED)
SBREGISTER
PROGRAM COUNTER
I
+-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3·23. Interrupt/Trap Service Routine Calling Sequence
2·334
J
TL/EE/8525-33
z
3.0 Functional Description
en
w
(Continued)
N
3.8.2 Interrupt/Trap Return
input is maskable, and is therefore enabled to generate interrupt requests only while the Processor Status Register I
bit is set. The I bit is automatically cleared during service of
an INT, NMI or Abort request, and is restored to its original
setting upon return from the interrupt service routine via the
RETT or RETI instruction.
To return control to an interrupted program, one of two instructions is used. The RETT (Return from Trap) instruction
(Figure 3-24) restores the PSR, MOD, PC and S8 registers
to their previous contents and, since traps are often used
deliberately as a call mechanism for Supervisor Mode procedures, it also discards a specified number of bytes from
the original stack as surplus parameter space. RETT is used
to return from any trap or interrupt except the Maskable
Interrupt. For this, the RETI (Return from Interrupt) instruction is used, which also informs any external Interrupt Control Units that interrupt service has completed. Since interrupts are generally asynchronous external events, RETI
does not pop parameters. See Figure 3-25.
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit 1=0) or Vectored
(bit 1=1).
3.8.3.1 Non-Vectored Mode
g....
.....
G)
~
z
en
w
N
oCI
....
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G)
UI
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
3.8.3 Maskable Interrupts (The INT Pin)
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests. The
PROGRAM COUNTER
RETURN ADDRESS
STATUS
I
PSR
I
(POP)
}
t---------l}
-1---------+-
32 BITS
(POP)
MODULE
MOO
32 BITS
INTERRUPT
STACK
MODULE
TABLE
MODULE TABLE ENTRY
MODULE
T~BLE
PI
ENTRY
STATIC BASE POINTER
-
n
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
/
SBREGISTER
STATIC BASE
+
PARAMETERS
n
BYTES
STACK SELECTED
IN NEWLYPOPPEDPSR.
POP AND
DISCARD
FIGURE 3-24_ Return from Trap (RETT n) Instruction Flow
2-335
TLlEE/8525-34
.... r---------------------------------------------------------------------------------,
....cb 3.0 Functional Description (Continued)
8
Lr)
~
tn
Z
......
C)
....
"END OF INTERRUPT"
....
BUS CYCLE
cb
8
C'I
~
Z
INTERRUPT
CONTROL
UNIT
PROGRAM COUNTER
(POP)
RETURN ADDRESS
STATUS
I
(POP)
MODULE
PSR
-t------------i-
MOD
INTERRUPT
STACK
o
MODULE
TABLE
MODULE TABLE ENTRY
t
MODULE TABLE ENTRY
STATIC BASE POINTER
-
r------
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STAnCBASE
SBREGISTER
TLlEE/8525-35
FIGURE 3·25. Return from Interrupt (RET I) Instruction Flow
2·336
r-----------------------------------------------------------------------.z
3.0 Functional Description
fa
(Continued)
3.B.3.2 Vectored Mode: Non-Cascaded Case
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize up to 16 interrupt requests. Upon receipt of an interrupt request on the INT pin, the CPU performs an "Interrupt Acknowledge, Master" bus cycle (Section 3.4.2) reading a vector value from the low-order byte of
the Data Bus. This vector is then used as an index into the
Dispatch Table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI) instruction, which performs an End of Interrupt
bus cycle, informing the ICU that it may re-prioritize any interrupt requests still pending. The ICU provides the vector
number again, which the CPU uses to determine whether it
needs also to inform a Cascaded ICU (see below).
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
pointing to the Vector Registers of each of up to 16
Cascaded ICUs.
Figure 3-22 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32-bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle
(Section 3.4.2), reading the final vector value. This vector is
interpreted by the CPU as an unsigned byte, and can therefore be in the range of 0 through 255.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle (Section 3.4.2),
whereupon the Master ICU again provides the negative
Cascaded Table index. The CPU, seeing a negative value,
uses it to find the corresponding Cascade Address from the
Cascade Table. Applying this address, it performs an "End
of Interrupt, Cascaded" bus cycle (Section 3.4.2), informing
the Cascaded ICU of the completion of the service routine.
The byte read from the Cascaded ICU is discarded.
3.B.3.3 Vectored Mode: Cascaded Case
In order to allow up to 256 levels of interrupt, provision is
made both in the CPU and in the NS32202 Interrupt Control
Unit (ICU) to transparently support cascading. Figure 3-27
shows a typical cascaded configuration. Note that the Interrupt output from a Cascaded ICU goes to an Interrupt Request input of the Master ICU, which is the only ICU which
drives the CPU INT pin.
In a system which uses cascading, two tasks must be performed upon initialization:
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number (0 to 15) on which
it receives the cascaded requests.
2)
Note: If an interrupt must be masked off, the CPU can do so by selling the
corresponding bit in the Interrupt Mask Register of the Interrupt Controller. However, if an interrupt is set pending during the CPU instruc·
tion that masks off that Interrupt, the CPU may still perform an inter·
rupt acknowledge cycle following that instruction since it might have
sampled the INT line before the ICU deasserted it. This could cause
the ICU to provide an invalid vector. To avoid this problem the above
operation should be performed with the CPU interrupt disabled .
A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction
from the location indicated by the CPU Interrupt Base
(INTBASE) Register. Its entries are 32-bit addresses,
NS32202
NS32COI6
cpu
HARDWARE
INTERRUPTS
OR
CASCADED
CONTROLLERS
GROUP
STATUS 1
INT \ - - - - - - l I N T
INTERRUPTS.
CASCADED,
OR
BIT 1/0
~~~~ESS
DECODER
Cs
TL/EE/8525-36
FIGURE 3-26. Interrupt Control Unit Connections (16 Levels)
2-337
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CI
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m
.... 3.0 Functional Description (Continued)
o
~
DATA
U)
z
C;
....
CONTROL
m
....
CASCADED
ADDR 5 BITS
8
NS32202
HARDWARE
INTERRUPTS
ICU
C'I
~
STATUS
Z
FROM
ADDRESS
DECODER
INTERRUPTS
OR
BIT 110
CS
NS32C016
MASTER
GROUP
ICU
NS32202
cpu
iiiT 1 - - - - - - - - - - - - - - - - - - - - - 1 iiiT
FROM
ADDRESS
DECODER
TL/EE/8525-37
FIGURE 3-27. Cascaded Interrupt Control Unit Connections
3.8.4 Non-Maskable Interrupt (The NMI Pin)
3.8.STraps
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Section 3.4.2)
when processing of this interrupt actually begins. The Interrupt Acknowledge cycle differs from that provided for Maskable Interrupts in that the address presented is FFFF0016.
The vector value used for the Non-Maskable Interrupt is
taken as 1, regardless of the value read from the bus.
A trap is an internally-generated interrupt request caused as
a direct and immediate result of the execution of an instruction. The Return Address pushed by any trap except Trap
(TRC) below is the address of the first byte of the instruction
during which the trap occurred. Traps do not disable inter·
rupts, as they are not associated with external events. Traps
recognized by NS32C016 CPU are:
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Section 3.9.1).
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETI) instruction. No
special bus cycles occur on return.
For the full sequence of events in processing the NonMaskable Interrupt, see Section 3.8.7.1.
2-338
,--------------------------------------------------------------------------, z
t/)
3.0 Functional Description
Co)
(Continued)
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
N
1.
Trap (SVC): The Supervisor Call (SVC) instruction was executed.
Trap (OVZ): An attempt was made to divide an integer by
zero. (The Slave trap is used for Floating Point division by
zero.)
If a String instruction was interrupted and not yet completed:
a.
b.
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
2.
Trap (BPT): The Breakpoint (BPn instruction was executed.
Trap (TRC): The instruction just completed is being traced.
See below.
3.
Trap (UNO): An undefined opcode was encountered by the
CPU.
Clear the Processor Status Register P bit.
Set "Return Address" to the address of the first
byte of the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I.
If the interrupt is Non-Maskable:
a. Read a byte from address FFFF0016, applying
Status Code 0100 (Interrupt Acknowledge, Master: Section 3.4.2). Discard the byte read.
b.
c.
5.
Here the interrupt is Vectored. Read "Byte" from address FFFE0016, applying Status Code 0100 (Interrupt
Acknowledge, Master: Section 3.4.2).
6.
3.8.6 Prioritization
7.
If "Byte" ~ 0, then set "Vector" to "Byte" and go to
Step B.
If "Byte" is in the range -16 through -1, then the
interrupt source is Cascaded. (More negative values
are reserved for future use.) Perform the following:
a. Read the 32-bit Cascade Address from memory.
The address is calculated as INTBASE + 4· Byte.
2) Abort
3) Non-Maskable Interrupt
4) Maskable Interrupts
5) Trace Trap
I
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Co)
N
n
....
....
I:)
G)
I
(It
If the interrupt is Non-Vectored:
a. Read a byte from address FFFF0016, applying
Status Code 0100 (Interrupt Acknowledge, Master: Section 3.4.2). Discard the byte read.
b.
c.
The NS32C016 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
(Highest priority)
G)
Set "Vector" to 1.
Go to Step B.
A special case is the Trace Trap (TRC), which is enabled by
setting the T bit in the Processor Status Register (PSR). At
the beginning of each instruction, the T bit is copied into the
PSR P (Trace "Pending") bit. If the P bit is set at the end of
an instruction, then the Trace Trap is activated. If any other
trap or interrupt request is made during a traced instruction,
its entire service procedure is allowed to complete before
the Trace Trap occurs. Each interrupt and trap sequence
handles the P bit for proper tracing, guaranteeing one and
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
4.
n
....
....
I:)
Set "Vector" to O.
Go to Step B.
b.
(Lowest priority)
8.
3.8.7Interrupt/Trap Sequences: Detail Flow
For purposes of the following detailed discussion of interrupt and trap service sequences, a single sequence called
"Service" is defined in Figure 3-28. Upon detecting any interrupt request or trap condition, the CPU first performs a
sequence dependent upon the type of interrupt or trap. This
sequence will include pushing the Processor Status Register and establishing a Vector and a Return Address. The
CPU then performs the Service sequence.
For the sequenced followed in processing either Maskable
or Non-Maskable Interrupts (on the INT or NMI pins, respectively), see Section 3.B.7.1. For Abort interrupts, see Section
3.B.7.4. For the Trace Trap, see Section 3.B.7.3, and for all
other traps see Section 3.B.7.2.
9.
Read "Vector," applying the Cascade Address
just read and Status Code 0101 (Interrupt Acknowledge, Cascaded: Section 3.4.2).
Push the PSR copy (from Step 2) onto the Interrupt
Stack as a 16-bit value.
Perform Service (Vector, Return Address), Figure 3-28.
Service (Vector, Return Address):
1)
3.8.7.1 Maskable/Non·Maskable Interrupt Sequence
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, at the next interruptible point during its execution.
Read the 32-bit External Procedure Descriptor from the Interrupt Dispatch Table: address is Vector'4 + INTBASE Register contents.
2)
Move the Module field of the Descriptor into the MOD Register.
3)
Read the new Static Base pOinter from the memory address contained
in MOD, placing it into the SB Register.
4)
Read the Program Base pointer from memory address MOD+8, and
add to it the Offset field from the Descriptor, placing the result In the
Program Counter.
S)
Flush Queue: Non·sequentially fetch first instruction of Interrupt Rou·
tine.
6)
Push MOD Register onto the Interrupt Slack as a 16·bit value. (The
PSR has already been pushed as a 16-bit value.)
7)
Push the Return Address onto the Interrupt Slack as a 32·bit quantity.
FIGURE 3·28. Service Sequence
Invoked during all interrupt/trap sequences
2-339
•
3.0 Functional Description (Continued)
3.8.7.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector" to the value corresponding to the trap
type.
SLAVE:
ILL:
SVC:
DVZ:
FLG:
BPT:
UND:
3)
4)
5)
6)
Each Slave Instruction Set is validated by a bit in the Configuration Register (Section 2.1.3). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
3.9.1 Slave Processor Protocol
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an ID Byte followed by an Operation Word. The ID Byte has three functions:
1) It identifies the instruction as being a Slave Processor
instruction.
2) It specifies which Slave Processor will execute it.
Vector = 3.
Vector = 4.
Vector=5.
Vector=6.
Vector = 7.
Vector = 8.
Vector = 10.
3)
Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, P and T.
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-29. While applying
Status Code 1111 (Broadcast ID, Section 3.4.2), the CPU
transfers the ID Byte on the least-significant half of the Data
Bus (ADO-AD7). All Slave Processors input this byte and
decode it. The Slave Processor selected by the ID Byte is
activated, and from this point the CPU is communicating
only with it. If any other slave protocol was in progress (e.g.,
an aborted Slave instruction), this transfer cancels it.
Set "Return Address" to the address of the first byte of
the trapped instruction.
Perform Service (Vector, Return Address), Figure 3-28.
3.8.7.3 Trace Trap Sequence
1) In the Processor Status Register (PSR), clear the P bit.
2)
Copy the PSR into a temporary register, then clear
PSR bits S, U and T.
3)
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
Set "Vector" to 9.
Set "Return Address" to the address of the next instruction.
Perform Service (Vector, Return Address), Figure 3-28.
4)
5)
6)
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Section 3.4.2).
Upon receiving it, the Slave Processor decodes it, and at
this point both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The Operation Word is swapped on the Data Bus; that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD7.
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
for memory accesses, these extensions are not sent to the
Slave Processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Section 3.4.2).
Status Combinations:
Send 10 (10): Code 1111
Xfer Operand (OP): Code 1101
Read Status (ST): Code 1110
Action
Step Status
1
ID CPU Send ID Byte.
2
OP CPU Sends Operation Word.
3
OP CPU Sends Required Operands.
4
Slave Starts Execution. CPU Pre-Fetches.
5
Slave Pulses SPC Low.
ST CPU Reads Status Word. (Trap? Alter Flags?)
6
7
OP CPU Reads Results (If Any).
3.8.7.4 Abort Sequence
1) Restore the currently selected Stack Pointer to its original contents at the beginning of the aborted instruction.
2) Clear the PSR P bit.
3)
4)
5)
Copy the PSR into a temporary register, then clear
PSR bits S, U, T and I.
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
Set "Vector" to 2.
6)
Set "Return Address" to the address of the first byte of
the aborted instruction.
7)
Perform Service (Vector, Return Address), Figure 3-28.
It determines the format of the following Operation
Word of the instruction.
3.9 SLAVE PROCESSOR INSTRUCTIONS
The NS32C016 CPU recognizes three groups of instructions
as being executable by external Slave Processors:
Floating Point Instruction Set
Memory Management Instruction Set
Custom Instruction Set
FIGURE 3-29. Slave Processor Protocol
2-340
3.0 Functional Description
(Continued)
Custom Slave instruction (LCR: Load Custom Register). In
executing these instructions, the protocol ends after the
CPU has issued the last operand. The CPU does not wait for
an acknowledgement from the Slave Processor, and it does
not read status.
After the CPU has issued the last operand, the Slave Processor starts the actual execution of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low. To
allow for this, and for the Address Translation strap function, AT/SPC is normally held high only by an internal pull·
up device of approximately 5 kn.
3.9.2 Floating Point Instructions
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave, Section
3.4.2).
Table 3-4 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Series 32000 Instruction Set Reference
Manual).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status, Section 3.4.2). This
word has the format shown in Figure 3-30. If the Q bit
("Quit", Bit 0) is set, this indicates that an error was detect·
ed by the Slave Processor. The CPU will not continue the
protocol, but will immediately trap through the Slave vector
in the Interrupt Table. Certain Slave Processor instructions
cause CPU PSR bits to be loaded from the Status Word.
......
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en
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U1
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-30).
An exception to the protocol above is the LMR (Load Mem·
ory Management Register) instruction, and a corresponding
Mnemonic
....
....c•
0)
The Operand Issued columns show the sizes of the oper·
ands issued to the Floating Point Unit by the CPU. "0" indio
cates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte,
W=Word, 0= Double Word). "f" indicates that the instruc·
tion specifies a Floating Point size for the operand (F = 32bit Standard Floating, L=64-bit Long Floating).
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand, Sec·
tion 3.4.2).
Operand 1
Class
z
~
~
o
c
TABLE 3-4. Floating Point Instruction Protocols
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
Returned Value
Type and Oest.
PSR Bits
Affected
fto Op. 2
ftoOp.2
ftoOp.2
ftoOp.2
none
none
none
none
ADDf
SUBf
MULf
DIVf
read.f
read.f
read.f
read.f
rmw.f
rmw.f
rmw.f
rmw.f
MOVf
ABSf
NEGf
read.f
read.f
read.f
write.f
write.f
write.f
N/A
N/A
N/A
fto Op. 2
ftoOp.2
ftoOp.2
none
none
none
CMPf
read.f
read.f
f
N/A
N,Z,L
FLOORfi
TRUNCfi
ROUNDfi
read.f
read.f
read.f
write.i
write.i
write.i
f
f
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
none
none
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
N/A
N/A
LtoOp.2
FtoOp.2
none
none
MOVif
read.i
write.f
N/A
fto Op. 2
none
LFSR
SFSR
read.D
N/A
N/A
write.D
N/A
N/A
N/A
DtoOp.2
none
none
0
N/A
Noles:
o = Double Word
= integer size (B,W,D) specified in mnemonic.
= Floating Point type (F,L) specified In mnemonic.
NI A = Not Applicable to this instruction.
I
f
2-341
PI
."
.....
cb
.....
3.0 Functional Description
(Continued)
3.9.3 Memory Management Instructions
Table 3·5 gives the protocols for Memory Management in·
structions. Encodings for these instructions may be found in
Appendix A.
C)
~
Cf)
15
lo
tn
Z
C;
8 7
0 0 0 0 000
IN. Z
F 0 0 L 0
New PSR Bit VsIUe(I)&- ..,A
"Ouit": Te,mlnlll Protocol, lI'ap(FPU).
.....
•
.....
oj
J
CD
8
In executing the RDVAL and WRVAL instructions, the CPU
calculates and issues the 32·bit Effective Address of the
single operand. The CPU then performs a single·byte Read
cycle from that address, allowing the MMU to safely abort
the instruction if the necessary information is not currently in
physical memory. Upon seeing the memory cycle complete,
the MMU continues the protocol, and returns the validation
result in the F bit of the Slave Status Word.
The size of a Memory Management operand is always a 32·
bit Double Word. For further details of the Memory Manage·
ment Instruction set, see the Series 32000 Instruction Set
Reference Manual and the NS32082 MMU Data Sheet.
TL/EE/8525-38
FIGURE 3·30. Slave Processor Status Word Format
N
~
Z
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
Mnemonic
RDVAL·
WRVAL·
LMR·
SMR·
Operand 1
Class
TABLE 3-5. Memory Management Instruction Protocols
Operand 2
Operand 1
Operand 2
Returned Value
Type and Dest.
Issued
Class
Issued
PSRBlts
Affected
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
DtoOp.1
none
none
Note:
In the RDVAL and WRVAL instructions, the CPU issues the address as a Double Word, and performs a single-byte Read cycle lrom that memory address. For
details, see the Series 32000 Instruction Set Reference Manual and the NS320B2 Memory Management Unit Data Sheel
o=
Double Word
• = Privileged Instruction: will trap II CPU is In User Mode.
NIA = Not Applicable to this instruction.
2-342
z
en
c.:I
3.0 Functional Description (Continued)
N
3.9.4 Custom Slave Instructions
Provided in the NS32C016 is the capability of communicating with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
Table 3-6 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
Mnemonic
Operand 1
Class
operand which can be a 32-bit ("D") or 64-bit ("Q") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type 'c' will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
For the instruction encodings, see Appendix A.
TABLE 3·6. Custom Slave Instruction Protocols
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
PSRBlts
Affected
rmw.c
rmw.c
rmw.c
rmw.c
c
c
c
c
c
c
c
c
ctoOp.2
ctoOp.2
cto Op. 2
cto Op. 2
none
none
none
none
CMOVOc
CMOV1c
CMOV2c
CMOV3c
read.c
read.c
read.c
read.c
write.c
write.c
write.c
write.c
c
c
c
c
N/A
N/A
N/A
N/A
ctoOp.2
cto Op. 2
ctoOp.2
ctoOp.2
none
none
none
none
CCMPOc
CCMP1c
read.c
read.c
read.c
read.c
c
c
c
c
N/A
N/A
N,Z,L
N,Z,L
CCVOci
CCV1ci
CCV2ci
CCV3ic
read.c
read.c
read.c
readi
write.i
write.i
write.i
write.c
c
c
c
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
ito Op. 2
cto Op. 2
none
none
none
none
CCV4DQ
CCV5QD
read.D
read.Q
write.Q
write.D
D
Q
N/A
N/A
QtoOp.2
DtoOp.2
none
none
LCSR
SCSR
read.D
N/A
N/A
write.D
D
N/A
N/A
N/A
N/A
DtoOp.2
none
none
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
DtoOp.1
none
none
Notes:
D - Double Word
i
Returned Value
Type and Dest.
read.c
read.c
read.c
read.c
LCR·
SCR'
Q)
•
.....
C)
......
z
en
c.:I
N
o
C)
.....
.....•
Q)
Ut
CCALOc
CCAL1c
CCAL2c
CCAL3c
CATSTO'
CATST1'
o
C)
.....
= integer size (B,W,D) specified in mnemonic.
c - Custom size (D:32 bits or Q:64 bits) specified in mnemonic.
.. = Privileged instruction: will trap if CPU is in User Mode.
N/A - Not Applicable to this instruction.
2-343
II
.,..
~
.,..
U) r-------------------------------------------------------------------------------~
8
~
en
....zo.,..
I
CD
.,..
o
(.)
N
C")
(/)
z
4.0 Device Specifications
Status (STO-ST3): Active high. Bus cycle status code, STO
least significant. Section 3.4.2. Encodings are:
OOOO-idle: CPU Inactive on Bus.
4.1 NS32C016 PIN DESCRIPTIONS
The following is a brief description of all NS32C016 pins.
The descriptions reference portions of the Functional De·
scription, Section 3.
0001-ldle: WAIT Instruction.
001O-(Reserved)
0011-ldle: Waiting for Slave.
4.1.1 Supplies
Logic Power (VeeLl:
Section 3.1.
+ SV positive supply for on·chip logic.
010o-Interrupt Acknowledge, Master.
0101-lnterrupt Acknowledge, Cascaded.
Buffer Power (VeeB): + SV positive supply for on·chip out·
put buffers. Section 3.1.
0110-End of Interrupt, Master.
0111-End of Interrupt, Cascaded.
1000-5equential Instruction Fetch.
Logic Ground (GNDL): Ground reference for on-chip logic.
Section 3.1.
Buffer Ground (GNDB): Ground reference for on-chip drivers connected to output pins. Section 3.1.
1001-Non-Sequentiallnstruction Fetch.
101O-Data Transfer.
4.1.2 Input Signals
1011-Read Read-Modify-Write Operand.
110o-Read for Effective Address.
1101-Transfer Slave Operand.
Clocks (PHI1, PHI2): Two-phase clocking signals. Section
3.2.
Ready (ROY): Active high. While ROY is inactive, the CPU
extends the current bus cycle to provide for a slower memory or peripheral reference. Upon detecting ROY active, the
CPU terminates the bus cycle. Section 3.4.1.
111o-Read Slave Status Word.
1111-Broadcast Slave 10.
Hold Acknowledge (HLDA): Active low. Applied by the
CPU in response to HOLD input, indicating that the bus has
been released for DMA or multiprocessing purposes. Section 3.B.
Hold Request (HOLD): Active low. Causes the CPU to release the bus for DMA or multiprocessing purposes. Section
3.6.
User/Supervisor (U/S): User or Supervisor Mode status.
Section 3.7. High state indicates User Mode, low indicates
Supervisor Mode. Section 3.7.
Interlocked Operation (ILO): Active low. Indicates that an
interlocked instruction is being executed. Section 3.7.
Program Flow Status (PFS): Active Low. Pulse indicates
beginning of an instruction execution. Section 3.7.
Nole: If Ihe HOLD signal is generated asynchronously, its set up and hold
times may be violated. In this case it is recommended to synchronize
it with CTTL to minimize the possibility of metastable states.
The CPU provides only one synchronization stage to minimize the
HLDA latency. This is to avoid speed degradalions in cases of heavy
HOLD activity (Le. DMA controller cycles inte~eaved with CPU cycles).
Interrupt (I NT): Active low. Maskable Interrupt request.
Section 3.B.
4.1.4 Input-Output Signals
Address/Data 0-15 (ADO-AD15): Multiplexed Addressl
Data information. Bit 0 is the least significant bit of each.
Section 3.4.
Address
Translation/Slave
Processor
Control
(AT/SPC): Active low. Used by the CPU as the data strobe
output for Slave Processor transfers; used by Slave Processors to acknowledge completion of a slave instruction. Section 3.4.6; Section 3.9. Sampled on the rising edge of Reset
as Address Translation Strap. Section 3.S.1.
In non-memory-managed systems this pin should be pulled
up to Vee through a 10 kO resistor.
Data Strobe/Float (DS/FLT): Active low. Data Strobe output, Section 3.4, or Float Command input, Section 3.S.3. Pin
function is selected on AT/SPC pin, Section 3.S.1.
Non-Maskable Interrupt (NMI): Active low. Non-Maskable
Interrupt request. Section 3.B.
Reset/Abort (RST/ABT): Active low. If held active for one
clock cycle and released, this pin causes an Abort Command, Section 3.S.4. If held longer, it initiates a Reset, Section 3.3.
4.1.3 Output Signals
Address Bits 16-23 (A16-A23): These are the most significant 8 bits of the memory address bus. Section 3.4.
Address Strobe (ADS): Active low. Controls address latches; indicates start of a bus cycle. Section 3.4.
Data Direction In (ODIN): Active low. Status signal indicating direction of data transfer during a bus cycle. Section 3.4.
High Byte Enable (HBE): Active low. Status signal enabling
transfer on the most significant byte of the Data Bus. Section 3.4; Section 3.4.3.
Nole: In Ihe current NS32C016, the HBE Signal is forced low by the CPU
when FLT is asserted by the MMU. However, in future revisions of the
CPU, HBE will no longer be affected by FLT. Therefore, in a memory
managed system, an external 'AND' gate is required. This is shown in
Figure 8-1 in Appendix B.
2-344
z
en
c.:I
4.0 Device Specifications (Continued)
N
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O'C to + 70'C
Storage Temperature
-65'Cto +150'C
All Input or Output Voltages with
Respect to GND
Power Dissipation
Z
...oocp
...
-0.5Vto +7V
1.5 Watt
VIH
Conditions
Parameter
UI
Min
High Level Input Voltage
Typ
2.0
Max
Units
Vee + 0.5
V
Vil
Low Level Input Voltage
-0.5
0.8
V
VeH
High Level Clock Voltage
PHI1, PHI2 pins only
0.90 Vee
Vee + 0.5
V
Vel
Low Level Clock Voltage
PHI1, PHI2 pins only
-0.5
0.10 Vee
V
VeRT
Clock Input
Ringing Tolerance
PHI1, PHI2 pins only
-0.5
0.6
V
VOH
High Level Output Voltage
IOH = -400".A
VOL
Low Level Output Voltage
IOl = 2mA
0.10 Vee
v
IllS
ATISPC Input Current (low)
VIN = O.4V, AT/SPC in input mode
0.05
1.0
mA
II
Input Load Current
o s: VIN s: Vee, All inputs except
-20
20
".A
-20
20
".A
100
mA
Icc
Leakage Current Output
and 10 Pins in TRI·STATEI
Input Mode
0.4
Active Supply Current
lOUT = 0, TA = 25'C
s:
s:
VIN
Vee
70
Connection Diagram
Dual·ln·Line Package
A22c::~b
veeL
A21~2
A2:§ 3
47gA23
A19
4
46 E5
45 g~
A18
5
44
~'LO
AI:§ 6
43
5TO
A16
A015
ADI.
E
1=
1
8
42
41
:::::I
iNT
ST1
5T2
9
AD13 ~ 10
.0
STl
39 ~ 'PFS
ADI.
38
11
:~~~ ~ ~~
AD9
~
==
E
N~::~'6
"
35
34
16
33
AD6~ 17
ADS ~ I.
32
AD7
F
: F=
15
ADS
31
DDIN
~~:
~ Ar/SPC
RST/ABT
EJ OS/FLT
t::::=
g HBE
:::::I HLDA
~~ 19
AD3
30
A~~ 21
28 ~ ROY
c:: ••
ADI~
ADO
GNDL
§
29
22
"Z7
24
25
23
26
~ HOLD
veeB
:=::J
~PHI2
PHI1
GNDB
TL/EE/8525-2
Top View
FIGURE 4-1
Order Number NS32C016D-10, NS32C016D-15,
NS32C016N-10 or NS32C016N-15
See NS Package Number D48A or N48A
2-345
V
0.90 Vee
PHI1, PHI2, ATISPC
Il
...
...~cp
~
N
4.3 ELECTRICAL CHARACTERISTICS: TA = -40'Cto + 85'C, Vee = 5V ±10%, GND = OV
Symbol
oo
.... r-------------------------------------------------------------------------------------,
ch
4.0 Device Specifications (Continued)
....
U)
CI
~
~
Z
(:)
....
ch
....
8
i3z
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHil
and PHI2; to 15% or 85% of Vee on all the CMOS output
signals, and to 0.8V or 2.0V on all the TTL input signals as
illustrated in Figures 4·2 and 4-3 unless specifically stated
otherwise.
PHln [
ABBREVIATIONS:
L.E. - leading edge
R.E. - rising edge
T.E. -
F.E. - falling edge
trailing edge
_ _ _ _ _ _ _ _}~
PHI" [
SIGI [
-
") 2.0V
2.0V
-F-====i':::::-
_ _ _ _.If'.. _______ts.!G~h
SIG2 [
SIGI [
TL/EE/8525-40
FIGURE 4-3. Timing Specification Standard
(TTL Input Signals)
SIG2 [
TL/EE/8525-39
FIGURE 4·2. Timing Specification Standard
(CMOS Output Signals)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C016·10 and NS32C016·15
Maximum times assume capacitive loading of 75 pF, on the address/data bus signals and 50 pF on all other signals.
Name
toy
Figure
Description
Reference/Conditions I-_N_S_3_2C.,.0_1_6_.1_0_t-_N_S_3_2C.,.0_1_6_.1_5--j
Min
Max
Min
Max
Units
4·4
Address bits 0-15 valid
after R.E., PHil Tl
4-4
Address bits 0-15 hold
after R.E., PHil
TmmuorT2
4·4
Data valid (write cycle)
after R.E., PHil T2
4·4
Data hold (write cycle)
after R.E., PHil
nexiTlorTi
4·4
Address bits 16-23 valid
after R.E., PHil Tl
4·4
Address bits 16-23 hold
after R.E., PHil
nexiTlorTi
o
o
ns
40
35
5
5
50
ns
35
o
o
40
ns
ns
ns
35
ns
tALADSs
4·5
Address bits 0-15 set up
before ADS T.E.
25
20
ns
tAHADSs
4·5
Address bits 16-23 set up
before ADS T.E.
25
20
ns
tALADSh
4·9
Address bits 0-15 hold
after ADS T.E.
15
10
ns
tAHADSh
4·9
Address bits 16-23 hold
after ADS T.E.
15
10
ns
4·5
Address bits 0-15 floating
(no MMU)
after R.E., PHil T2
4·9
Address bits 0-15 floating
(withMMU)
after R.E., PHil TMMU
4·9
Address bits 16-23 floating
(withMMU)
after R.E., PHil TMMU
tHBEv
4·4
HBE Signal valid
after R.E., PHil
tHBEh
4·4
HBE signal hold
after R.E., PHil
nexiTlorTi
tSTv
4·4
Status (STO-ST3) valid
after R.E., PHil T4
(before n, see note)
IsTh
4·4
Status (STO-ST3) hold
after R.E., PHil T4
(after Tl)
tDDINv
4-5
DDIN signal valid
after R.E., PHil Tl
tALMf
2·346
n
25
20
ns
25
20
ns
25
20
ns
45
35
ns
o
o
45
o
ns
35
o
50
ns
ns
35
ns
z
4.0 Device Specifications (Continued)
en
Ct.)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C016·10 and NS32C016·15 (Continued)
o
C
Description
N
NS32C016·10
NS32C016·15
Min
Min
Figure
tOOINh
4·5
ODIN Signal hold
after R.E., PHil
next Tl orTi
tAOSa
4·4
ADS signal active (low)
after R.E., PHil Tl
35
26
ns
tAOSia
4·4
ADS signal inactive
after R.E., PHI2 Tl
40
30
ns
tAOSw
4·4
ADS pulse width
at 15% Vcc (both edges)
tOSa
4·4
OS signal active (low)
after R.E., PHil T2
40
30
ns
tOSla
4·4
OS signal inactive
after R.E., PHil T4
40
30
ns
tALI
4·6
ADO-AD15 floating
after R.E., PHil Tl
(caused by HOLD)
25
20
ns
tAH!
4·6
A16-A23 floating
after R.E., PHil Tl
(caused by HOLD)
25
20
ns
Reference/Conditions
Max
Units
Max
0
0
.......
z
ns
en
Ct.)
N
30
ns
25
toS!
4·6
OS floating (caused by HOLD)
after R.E., PHil Ti
50
40
ns
tAOS!
4·6
~ floating (caused by HOLD)
after R.E., PHil Ti
50
40
ns
tHBE!
4·6
HBE floating (caused by HOLD)
after R.E., PHil Ti
50
40
ns
toolN!
4·6
ODIN floating (caused by HOLD)
after R.E., PHil Ti
50
40
ns
tHLOAa
4·6
HLDA signal active (low)
after R.E., PHil Ti
30
25
ns
tHLOAia
4·8
HLDA signal inactive
after R.E., PHil Ti
40
30
ns
tOSr
4·8
OS signal returns from floating
(caused by HOLD)
after R.E., PHil Ti
55
40
ns
tAOSr
4·8
~ signal returns from floating
after R.E., PHil Ti
55
40
ns
55
40
ns
55
40
ns
(caused by HOLD)
tHBEr
4·8
HBE Signal returns from floating
(caused by HOLD)
after R.E., PHil Ti
tOOINr
4·8
ODIN signal returns from floating
(caused by HOLD)
after R.E., PHil Ti
tOOIN!
4·9
ODIN Signal floating (caused by FLT) after FLT F.E.
55
50
ns
tHBEI
4·9
HBE signal low (caused by FLT)
after FLT F.E.
40
30
ns
tOOINr
4·10
ODIN signal returns from floating
(caused by FLT)
after FLT R. E.
40
30
ns
tHBEr
4·10
HBE signal returns from low
(caused by FLT)
after FLT R. E.
35
25
ns
tspca
4·13
SPC output active (low)
after R.E., PHil Tl
35
26
ns
26
ns
ns
tsPCia
4·13
SPC output inactive
after R.E., PHil T4
35
tSPCn!
4·15
SPC output nonforcing
after R.E., PHI2 T4
30
25
tov
4-13
Data valid (slave processor write)
after R.E., PHil Tl
50
35
tOh
4·13
Data hold (slave processor write)
after R.E., PHil next Tl or Ti
0
tpFSw
4-18
PFS pulse width
at 15% VCC (both edges)
50
tPFSa
4-18
PFS pulse active (low)
after R.E., PHI2
40
35
ns
tPFSia
4-18
PFS pulse inactive
after R.E., PHI2
40
35
ns
tlLOs
4-20a
ILO signal setup
before R.E., PHil Tl of first
interlocked write cycle
50
35
ns
tlLOh
4-20b
ILO signal hold
after R.E., PHil T3 of last
interlocked read cycle
10
7
ns
tlLOa
4-21
iIO Signal active (low)
after R.E., PHil
2-347
....
....c.
(7)
Name
0
ns
40
35
ns
ns
30
ns
o
....C
....•
(7)
(11
....
....d.
8
II)
~
en
z
......
.
....
CD
....
8N
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32C016-10 and NS32C016-15 (Continued)
Name
Figure
Description
Reference/Conditions
NS32C016-10
NS32C016-15
Min
Min
Max
Units
Max
C)
~
Z
tlLOia
4-21
ILO signal inactive
after R.E., PHI1
tusv
4-22
U/S signal valid
after R.E., PHI1 T4
tUSh
4-22
U/S signal hold
after R.E., PHI1 T4
tNSPF
4·19b
Nonsequential fetch to
next PFS clock cycle
after R.E., PHI1 T1
tpFNS
4·19a
PFS clock cycle to next
nonsequential fetch
before R.E., PHI1 T1
35
35
30
ns
30
ns
8
6
ns
4
4
tcp
4
4
Icp
Last operand transfer of
before R.E., PHI1 T1 of first
0
an instruc1ion to next
bus cycle of transfer
0
Icp
PFS clock cycle
Note: Every memory cycle starts with T4. during which Cycle Status is applied. If the CPU was idling. the sequence will be:" ... TI, T4. Tl .. :'.11 the CPU was
not idling. the sequence will be: ". . . T4. T1 . . .".
tLXPF
4·29
4.4.2.2 Input Signal Requirements: NS32C016-10 and NS32C016-15
Name
Figure
Description
Reference/Conditions
NS32C016-10
NS32C016-15
Min
Min
Max
Units
Max
tPWR
4·25
Power stable to RST R.E.
after Vcc reaches 4.5V
50
33
I's
tOls
4·5
Data in setup (read cycle)
before F.E., PHI2 T3
15
10
ns
tOlh
4·5
Data in hold (read cycle)
after F.E., PHI1 T4
3
3
ns
tHLOa
4·6
HOLD active (low) setup
time (see note)
before F.E., PHI2 TX1
25
17
ns
tHLOia
4·8
HOLD inactive setup time
before F.E., PHI2 Ti
25
17
ns
tHLDh
4·6
HOLD hold time
after R.E., PHI1 TX2
0
0
ns
tFLTa
4·9
FLT active (low) setup time
before F.E., PHI2 Tmmu
25
17
ns
tFLTia
4·10
FLT inactive setup time
before F.E., PHI2 T2
25
17
ns
tROYs
4·11,4·12
ROY setup time
before F.E., PHI2 T2 or T3
15
10
ns
tROYh
4·11,4·12
ROY hold time
after F.E., PHI1 T3
5
5
ns
tASTs
4·23
ABT setup time
(FLT inactive)
before F.E., PHI2 Tmmu
20
13
ns
tASTs
4-24
ABT setup time
(FLT active)
before F.E., PHI2 Tf
20
13
ns
tASTh
4·23
ABT hold time
after R.E., PHI1
0
0
ns
tRSTs
4·25,4·26
RST setup time
before F.E., PHI1
10
8
ns
tRSTw
4·26
RST pulse width
at 0.8V (both edges)
64
64
tcp
tiNTs
4·27
INT setup time
before R.E., PHI1
20
15
ns
tNMlw
4·28
NMI pulse width
at 0.8V (both edges)
70
70
ns
tOls
4·14
Data setup
(slave read cycle)
before F.E., PHI2 T1
15
10
ns
tOlh
4·14
Data hold
(slave read cycle)
after R.E., PHI1 T4
3
3
ns
2·348
z
en
Co)
4.0 Device Specifications (Continued)
N
oo
4.4.2.2 Input Signal Requirements: NS32C016-10 and NS32C016-15 (Continued)
Name
Figure
Description
SPC pulse delay
Reference/Conditions
Max
30
25
ns
oo
20
20
ns
U1
before R.E., PHI1 of cycle
during which RST pulse
is removed
1
1
tcp
after F.E., PHI1 of cycle
during which RST pulse
is removed
2
2
tcp
SPC setup time
before F.E., PHI1
tspCw
4-15
SPC pulse width from
slave processor
(async. input)
at O.BV (both edges)
ATISPC setup for
address translation
strap
AT/SPC hold for
address translation
strap
after R.E., PHI2 T4
from slave
N
Note: This setup time is necessary to ensure prompt acknowledgement via HLDA and the ensuing floating of CPU off the buses. Note that the time from the receipt
of the HOLD signal until the CPU floats is a function of the time HOLD signal goes low, the state of the ROY input (in MMU systems), and the length of the current
MMU cycle.
4.4.2.3 Clocking Requirements: NS32C016-10 and NS32C016-15
Name
Figure
Description
Reference/Conditions
NS32C016-10
NS32C016-15
Min
Max
Min
Max
100
250
66
250
ns
Units
tep
4-17
Clock period
R.E., PHI1, PHI2 to
next R.E., PHI1, PHI2
teLw
4-17
PHI1, PHI2
pulse width
At2.0V
on PHI1, PHI2
(both edges)
O.5tcp
-10 ns
0.5tcp
-6ns
teLh
4-17
PHI1, PHI2
High Time
At 90% VCC
on PHI1, PHI2
0.5tep
-15ns
0.5tcp
-10ns
tCLI
4-17
PHI1, PHI2
Low Time
At 15% Vcc
on PHI1, PHI2
0.5tep
-5ns
0.5tcp
-5 ns
tnOVL(1,2)
4-17
Non-overlap time
At 15% Vcc
on PHI1, PHI2
-2
2
-2
2
ns
Non-overlap asymmetry
At15% Vcc
on PHI1, PHI2
-3
3
-3
3
ns
At2.0V
on PHI1, PHI2
-5
5
-3
3
ns
tnOVLas
(tnOVL(1) - tnOVL(2»)
tCLwas
PHI1, PHI2 asymmetry
(teLw(1) - tCLw(2»)
.
o
.......
z
en
Co)
4-15
4-16
Min
Max
......
Q)
......
ns
tsPCs
tATh
Min
Units
25
4-15
4-16
NS32C016-15
30
tSPCd
tATs
NS32C016-10
2-349
.
......
Q)
......
~
.,...
*'
B
r------------------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
~
(/)
Z
.....
Q
.,...
CD
.,...
.
12
T1
8
PHil [
~
PHI2 [
T3
T4
N
Z
AJlO.15 [
AI6-23 [
ST(1.3
[-1________+~-Il-A-LI-O--+------'........1_"_/' ~N-E-XT---
os [
-1----~IDS.
~___+_---~
(HIGH)
ROY [
I
TLlEE/8525-41
FIGURE 4·4. Write Cycle
PHil [
PHI2 [
_n
Tl
12
n
r0-
-Ul
AJlO.15 [
-K
AI6-23 [
-~
-
T3
T4
r--
-C
A5S[ -t"\~
'ALAOSI
=tx
-~
>C
VALID
/
'DDINv
I---t IDDlNh
·N~{A~~L~
VALID
'\.
ROY [
/
(HIGH)
TLlEE/8525-42
FIGURE 4·5. Read Cycle
2·350
z
CJ)
4.0 Device Specifications (Continued)
W
I\)
o
o
....
....o
0'1
I
TXI
TX2
Ti
Ti
TI
T4
.....
Z
PHil [
CJ)
w
I\)
PHI2 [
oo
....0'1
....
---4--....
iiiiUi[
I
U\
HLOA[
loSt
IHBE!
1m
HBE [
ODIN
'ADS!
IOOINt
---,_----+------+------il--~
~I_----+------+------il-__J'AU
- - - - iFLOATiNGi - - --
I
AOO·IS [
~[
(FLO"XTING)
I
~~---~~---~I----~I-__ I'AH!
~~
I
TLlEE/8525-43
FIGURE 4·6. Floating by HOLD Timing (CPU Not Idle Initially)
Note that whenever the CPU is not idling (not in Ti), Ihe HOLD requesl (HOLD low) must be active IHLDa before the falling edge of PHI2 of Ihe clock cycle Ihat
appears two clock cycles before T4 (TXt) and stay low unlil IHLDh after Ihe rising edge of PHil of Ihe clock cycle Ihal precedes T4 (TX2) for Ihe requesl 10 be
acknowledged.
11
PHil [
Tl
TI
T4
PHil [
PHI2 [
•
HOLD [
HLDA [
-t-----t--'
Os
ADS
HBE [
ODIN
A16-23 [
ADO-15
(HIGH)
•
_
(FLOATING)
TLlEE/8525-44
TLlEE/8525-80
FIGURE 4·7. Floating by HOLD Timing (CPU Initially Idle)
FIGURE 4·8. Release from HOLD
Nole Ihat during Tit the CPU is already idling.
2·351
r.n
,...
•
CD
,...
4.0 Device Specifications (Continued)
C)
~
C')
en
z
......
C)
,...
cD
,...
C)
oN
C')
en
z
CPU STATES
TI
TMMU
TI
TI
MMUSTATES[
PHil
PHI2 [
m[
ADO·IS [
(CPU)
AI6-23 [
(CPU)
ADS [
(CPU)
ODIN [
(CPU)
"HBE [
TLlEE/BS25-46
'Note: In future higher speed versions of the NS32COl6, HBE will no longer be affected by FLT. See Figure 8·1 in Appendix B for the required mod~ication to the
interface logiC.
FIGURE 4-9. FLT Initiated Cycle Timing
CPU STATES
TI
MMUSTATES
Tmmu
T2
T3
T4
PHil [
PHI2[
FLT [
(MMU)
AI6-23 [
(CPU) ODIN
(CPU) [
ADs [
(CPU)
HiE [
TL/EE/8525-47
Note that when FLT is deasserted the CPU restarts driving ODIN before the MMU releases it. This, however, does not cause any conllict, since both CPU and MMU
force ODIN to the same logic level.
FIGURE 4-10. Release from FLT Timing
PHil [
PHI2 [
RDV [
TL/EE/8525-48
FIGURE 4-11. Ready Sampling (CPU Initially READY)
2-352
4.0 Device Specifications (Continued)
I u
z
en
Co)
u
I
N
(')
....en
....•
U
D ________n!-_-!nl.....-_
PHI1 [
Q
Q
.....
PHI2[
Z
en
Co)
-t--......
N
(')
....
....•
C7I
Q
RDY[+__
en
TL/EE/8525-49
FIGURE 4·12. Ready Sampling (CPU Initially NOT READY)
I
I
T1
I
T4
I
PHI1[~
PHI2 [
T1
I
I
T4
PHI1[~
I
PHI2 [
A[)().15 [
A[)()'15 [
--+_
DATA (FROM SLAVE),.-__
sPC [
SPC [
(CPU)
DDIN[-+~______~________+-
= ..
S11).3 [-+_S_TII:_:T_U_S_VA_L_ID-i-J '\.........
5111-3 [-+_S_t_ATU
__
S_VA_L_ID+-J '-____....,.._
(HIGH)
I
iDs [
iDs [
TL/EE/8525-50
TLlEE/8525-51
FIGURE 4·13. Slave Processor Write Timing
FIGURE 4·14. Slave Processor Read Timing
T4
Tl
PHI1 [
PHI2
[-+-_......
SPC [
(FROM CPU)
(FROM
sJJE1 [- ---------------- -----'spew
TLlEE/8525-81
FIGURE 4-15. SPC Timing
After transferring last operand to a Slave Processor, CPU turns
OFF driver and holds SPC high with internal 5 kO pull up.
TLlEE/8525-53
FIGURE 4-16. Reset Configuration Timing
2-353
.... r---------------------------------------------------------------------------------,
ch
4.0 Device Specifications (Continued)
....
8
~
:az
c;
....
ch
....
~
PHI1 [
Q
(I)
z
-----~r
PHI2 [
TL/EE/8525-54
FIGURE 4-17. Clock Waveforms
PHI2[~ruu
~;~uTL/EE/8525-55
FIGURE 4-18. Relationship of PFS to Clock Cycles
T1
TL/EE/8525-58
FIGURE 4-19a. Guaranteed Delay, PFS to Non-Sequential Fetch
I
I
I
I
PHI1[~rfl-n-JlT1
I
T2
I ••• I
A6S[
STO-3 [
CODE 1001
~--------------~~----~~-----------
TUEE/8525-57
FIGURE 4019b. Guaranteed Delay, Non-Sequential Fetch to PFS
2-354
z
~
I\)
o
Q
4.0 Device Specifications (Continued)
I
T30RTI
I
T40RTI
I
T1
T3
12
....
....•
en
T4
Q
......
Z
en
Co)
I\)
o
Q
AiiS[
....
en
•
....
U'I
n:o[
TL/EE/8525-58
FIGURE 4·20a. Relationship of ILO to First Operand Cycle
of an Interlocked Instruction
I
T3 OR TI
I
T40RTi
I
Tl
T3
12
T4
A5S[
~
ILO[ ................................
~~
........................
TL/EE/8525-59
FIGURE 4·20b. Relationship of ILO to Last Operand Cycle
of an Interlocked Instruction
TL/EE/8525-60
FIGURE 4·21. Relationship of ILO to Any Clock Cycle
I T3 OR TI I T40RTI I
Tl
12
T3
T4
TUEE/8525-61
FIGURE 4·22. U/S Relationship to Any Bus CycleGuaranteed Valid Interval
2·355
.
II)
.....
.....
o
o
N
('I)
en
CD
z.......
.
o
.....
4.0 Device Specifications (Continued)
T1
I
Tinmu
TI
T2
PHI1 [
CD
.....
o
oN
PHI2 [
('I)
en
z
ADS [
TL/EE/B525-62
FIGURE 4·23. Abort Timing, FLT Not Applied
PHI1 [
PHI2 [
Ds/FLT [
-+---~f----f----H-...J
TLlEE/8525-63
FIGURE 4·24. Abort Timing, FLT Applied
vee
~----------~~
+-__~
PHI1[ _ _ _
RST/AiiT[ _____________-\\--J
TL/EE/B525-64
FIGURE 4·25. Power·On Reset
PHI{~JUl-
''''~ [
~
tRS~r-
I'
,~~
TL/EE/B525-65
FIGURE 4·26. Non-Power-On Reset
2-356
z
en
CJ,)
4.0 Device Specifications (Continued)
N
n
o
.
.....
Q)
.....
o
.......
z
en
CJ,)
N
PHI1[~
iNT[
.
~_tNMIW_-r
NM{
~tINT.
n
o.....
Q)
.....
}..-
U1
TL/EE/B525-67
FIGURE 4-28. NMllnterrupt Signal Timing
TLlEE/B525-66
FIGURE 4-27. INT Interrupt Signal Detection
NEXT
FIRST BUS CYCLE
Tl
T2
T3
T4
T10rTi
I
TL/EE/B525-66
FIGURE 4-29. Relationship Between Last Data Transfer of
an Instruction and PFS Pulse of Next Instruction
NOTE:
In a transfer of a Read-Modify-Write type operand, this is the Read transfer,
displaying RMW Status (Code 1011).
2-357
•
.
~r-------------------------------------------------------------~
.....
co
Appendix A: Instruction Formats
~
~
z
C;
.....
NOTATIONS:
i = Integer Type Field
B = 00 (Byte)
W = 01 (Word)
o = 11 (Double Word)
f = Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L= 0 (Long Floating: 64 bits)
c = Custom Type Field
o = 1 (Double Word)
Q = 0 (Quad Word)
op = Operation Code
Valid encodings shown with each format.
gen, gen 1, gen 2 = General Addressing Mode Field
See Sec. 2.2 for encodings.
reg = General Purpose Register Number
cond = Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110 = Greater Than: N = 1
0111 = Less or Equal: N = 0
1000 = Flag Set: F = 1
1001 = Flag Clear: F = 0
1010 = LOwer: L = 0 and Z = 0
1011 = Higher or Same: L = 1 or Z = 1
1100 = Less Than: N = 0 and Z = 0
1101 = Greater or Equal: N = 1 or Z = 1
1110 = (Unconditionally True)
1111 = (Unconditionally False)
short = Short Immediate Value. May contain:
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ,ACB.
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPA.
0000 = US
0001 - 0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = (Reserved)
1100 = (Reserved)
1101 = PSR
1110 = INTBASE
1111 = MOD
.....
o
cb
.....
o
o
en
z
('II
CO)
Options: in String Instruct,--io_nS_-r-_.----,
I U/W
B
T
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
Configuration bits, in SETCFG:
IC I M I F
mreg:
NS32082 Register number, in LMR, SMA.
0000 = BPRO
0001 = BPR1
0010 = (Reserved)
0011 = (Reserved)
0100 = (Reserved)
0101 = (Reserved)
0110 = (Reserved)
0111 = (Reserved)
1000 = (Reserved)
1001 = (Reserved)
1010 = MSR
1011 = BCNT
1100 = PTBO
1101 = PTB1
1110 = (Reserved)
1111 = EIA
o
7
FormatO
(BR)
Bcond
7
I
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
0
I
op
10 ' 0 ' 1 101
Format 1
-0000
ENTER
-0001
EXIT
-0010
NOP
-0011
WAIT
-0100
DIA
-0101
FLAG
-0110
SVC
-0111
BPT
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
81 7
15
gen
sh~rt
0
1
op
11
I
11
1
Format 2
ADDQ
CMPQ
SPR
Scond
2-358
-000
-001
-010
-011
ACB
MOVQ
LPR
-100
-101
-110
z
en
w
Appendix A: Instruction Formats (Continued)
15
al7
0
~e~
,
I' ~p
I\)
0
o0
\1'1'1'1'11
Format 3
CXPD
BICPSR
JUMP
BISPSR
-0000
-0010
-0100
-0110
1 1 1 0
-1010
-1100
-1110
Trap (UND) on XXX1, 1000
I' gen, ,1 , I" gen 2 'I
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
....
....0.
en
......
Z
en
w
Format 7
ADJSP
JSR
CASE
n
0
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
DIV
I\)
0
0
....
en
....•
(II
o
I
I
I
op
Format 4
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
-1000
-1001
-1010
-1100
-1101
-1110
SUB
ADDR
AND
SUBC
TBIT
XOR
a7
i
0
000 0 1 1 1 0
TL/EE/8525-69
Format a
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
-000
INDEX
-001
FFS
-010
-011
-110, reg=001
-110, reg=011
-100
-101
a7
0
FormatS
-0000
MOVS
CMPS
-0001
Trap (UND) on 1XXX, 01XX
SETCFG
SKPS
i
-0010
-0011
MOVif
LFSR
MOVLF
MOVFL
001 1 1 1 1 0
Format 9
-000
ROUND
-001
TRUNC
-010
SFSR
-011
FLOOR
-100
-101
-110
-111
0
00111 0
]0
Format 6
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
NEG
NOT
Trap (UND)
SUBP
ABS
COM
IBIT
ADDP
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
2-359
111
1 1 1
0
01
TLlEE/8525-70
Format 10
Trap (UND) Always
•
.
.,...
CD
.,...
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Appendix A: Instruction Formats
(Continued)
o
U
N
16 115
C')
U)
Z
......
.
.,...
o.,...
o
U
N
C')
U)
Z
10 Byte
Operation Word
CD
Format 11
ADD!
MOV!
CMP!
Trap (SLAVE)
SUB!
NEG!
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
OIV!
Trap (SLAVE)
Trap (UNO)
Trap (UNO)
MUll
ABS!
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
---
nnn
Operation Word Format
000
Format 15.0
-0000
LCR
CATSTO
-0001
SCR
CATSTI
Trap (UNO) on ali others
--- 1111111110
_1
Format 15
(Custom Slave)
1 1 1 1 1 1 0,
TL/EE/8525-71
-0010
-0011
Format 12
Trap (UNO) Always
001
7
---I
I I I I I I I
___ 1 0 0 1 1 1 1 0
I
Format 15.1
TLlEE/8525-72
CCV3
LCSR
CCV5
CCV4
Format 13
Trap (UNO) Always
-000
-001
-010
-011
CCV2
CCV1
SCSR
CCVO
-100
-101
-110
-111
o
000 1 1 1 1 0
101
Format 14
ROVAL
WRVAL
-0000
-0001
LMR
SMR
Format 15.5
-0010
-0011
CCALO
CMOVO
CCMPO
CCMPI
CCALI
CMOV2
Trap (UNO)
Trap (UNO)
Trap (UNO) on 0IXX. lXXX
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
If nnn ~ 010, all, 100, 110, 111
then Trap (UND) Always
2-360
CCAL3
CMOV3
Trap (UNO)
Trap (UNO)
CCAL2
CMOVI
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
z
(J)
Appendix A: Instruction Formats (Continued)
W
N
o
C
....
•
....
C
en
---I
_no
I I I I I I I
1 0 1 1 1 1 ~
......
Z
1
U)
7
0
Co)
TL/EE/8525-74
....
en
•
....
---I X I XI X I 0 I 0 I 1 I 1 I 0 1 No
C
TL/EE/8525-73
U.
Format 16
C11
Trap (UND) Always
Format 19
Trap (UND) Always
Implied Immediate Encodings:
7
---I
I I I I I I I
___ 1 1 0 1 1·1 1
~
a
7
0
1
r1
ra
Register Mask, appended to SAVE, ENTER
TL/EE/8525-75
Format 17
Trap (UND) Always
a
7
r1
7
r2
r3
r4
rS
r6
Register Mask, appended to RESTORE, EXIT
0
---I
I I I I I I I 1
___ 1 0 0 0 1 1 1 0
TUEE/8525-76
a
7
Format 18
: offset:
Trap (UND) Always
le~gth-1 :
Offset/Length Modifier appended to INSS, EXTS
2-361
NS32C016-10/NS32C016-15
J>
E
-To
.--L.n • .-- ...............
PER
XCTAL2
READY
CWAIT
XCTAL1
WAIT8
NS32C201
TCU
WAIT2
REID
~}
1:=
WAif4 ~
AD
PHI2
WR
~
>C.
iffi
Wii
ADS
RSTO CTTL
ODIN ROY
ffiiE
ILO
HBE
~
--;r
~
ROY PHI1 PHI2
I
ILD HBE HOLD
HLDAI
HLDA
00
~
INTS{~
DS/FlT
FLT
PFS
PFs
iNT
NS32C016
CPU
Niii
(24)1
Uti
ADS
DoiN
ODIN
STO-ST3
I - I - - RST/Aiif
1SPC ADDR/DATA
S·
en
c
CO
CO
CD
~
STROBE
ADDRESS
LATCHI
BUFFER
ADDRESS
BUS
tn
(24)
I---t
10kO
+5
(24)
I-
L..-
ODIN
(24)
(24)
ADDR/DATA
MULTIPLEXED
BUS
::l
DJ
n
O·
N532082
MMU
RST/ABT
~
CD
-
VALID
(24)
U/S
tn
PHYSICAL
AD DR.
HlDAO
STO-ST3
t>
HOLD
r
PAV
ADS
AT/SPC
ADDRIDATA
10 kl!
~
CO
+5
HLDAD
PHI2
i')
J,..
!
HOLD ROY RSTI
PHI1
CD
Q.
WAIT REQUESTS
(ADDR. DECODED OR STRAPPED)
WAIT1
RSTI
PHil
-g
-a
t
(16),
(16
DATA
SPC
STo-sn
N532081
FPU
RST
ClK
j.-
II
I
I
EN
DATA
--
l---t RST
CLK
MULTIPLEXED
BUS
MEMORYI
PERIPHERALS
(16)
DIR
~.
DATA BUS
(16)
DATA BUfFERS
STATUS
TUEE/8525-n
FIGURE 8-1. System Connection Diagram
~National
PRELIMINARY
~ Semiconductor
NS32016-10 High-Performance Microprocessor
General Description
Features
The NS32016 is a 32-bit, virtual memory microprocessor
with a 16-MByte linear address space and a 16-bit external
data bus. It has a 32-bit ALU, eight 32-bit general purpose
registers, an eight-byte prefetch queue, and a slave processor interface. The NS32016 is fabricated with National
Semiconductor's advanced XMOS process, and is fully object code compatible with other Series 32000 processors.
The Series 32000 instructions set is optimized for modular
high-level languages (HLL). The set is very symmetric, it has
a two address format, and it incorporates HLL oriented addressing modes. The capabilities of the NS32016 can be
expanded with the use of the NS32081 floating point unit
(FPU), and the NS32082 demand-paged virtual memory
management unit (MMU). Both devices interface to the
NS32016 as slave processors. The NS32016 is a general
purpose microprocessor that is ideal for a wide range of
computational intensive applications.
•
•
•
•
•
32-bit architecture and implementation
Virtual memory support
16-MByte linear address space
16-bit external data bus
Powerful instruction set
- General 2-address capability
- High degree of symmetry
- Addressing modes optimized for high-level languages
• Series 32000 slave processor support
• High-speed XMOSTM technology
• 48-pin dual-in-line (DIP) package
Block Diagram
ADD/DATA
CONTROLS & STATUS
MICROCODE ROM
AND
CONTROL LOGIC
o::rn
CFG REGISTER
REGISTER SET
o
o
INTBASE
SB
FP
SPI
WORKING
REGISTERS
SPO
PC
RO
Rl
R2
R3
R4
R5
I
I
I
R6
R7
I
I
MOD
I
:
PSR
L_________________
2-363
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TL/EE/5054-1
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Table of Contents
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1.0 PRODUCT INTRODUCTION
2.0 ARCHITECTURAL DESCRIPTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.8 Instruction Status
2.1 Programming Model
3.8.1 General Interrupt/Trap Sequence
2.1.1 General Purpose Registers
3.8.2 Interrupt/Trap Return
2.1.2 Dedicated Register
3.8.3 Maskable Interrupts (The INT Plan)
2.1.3 The Configuration Register (CFG)
3.8.3.1 Non-Vectored Mode
2.1.4 Memory Organization
3.8.3.2 Vectored Mode: Non-Cascaded Case
2.1.5 Dedicated Tables
3.8.3.3 Vectored Mode: Cascaded Case
2.2 Instruction Set
3.8.4 Non-Maskable Interrupt (The NMI Pin)
2.2.1 General Instruction Format
3.8.5 Traps
2.2.2 Addressing Modes
3.8.6 Prioritization
2.2.3 Instruction Set Summary
3.8.7 Interrupt/Trap Sequence: Detail Flow
3.8.7.1 MaskablelNon-Maskable Interrupt Sequence
3.0 FUNCTIONAL DESCRIPTION
3.8.7.2 Trap Sequence: Traps Other Than Trace
3.1 Power and Grounding
3.9 Slave Processor Instructions
3.2 Clocking
3.9.1 Slave Processor Protocol
3.3 Resetting
3.9.2 Floating Point Instructions
3.4 Bus Cycles
3.9.3 Memory Management Instructions
3.4.1 Cycle Extension
3.9.4 Custom Slave Instructions
3.4.2 Bus Status
4.0 DEVICE SPECIFICATIONS
3.4.3 Data Access Sequences
3.4.3.1 Bit Access
4.1 Pin Descriptions
3.4.3.2 Bit Field Accesses
4.1.1 Supplies
3.4.3.3 Extending Multiply Accesses
4.1.2 Input Signals
3.4.4 Instruction Fetches
4.1.3 Output Signals
3.4.5 Interrupt Control Cycles
4.1.4 Input/Output Signals
4.2 Absolute Maximum Ratings
3.4.6 Slave Processor Communication
3.4.6.1 Slave Processor Bus Cycles
4.3 Electrical Characteristics
3.4.6.2 Slave Operand Transfer Sequences
4.4 Switching Characteristics
3.5 Memory Management Option
4.4.1 Definitions
3.5.1 Address Translation Strap
4.4.2 Timing Tables
3.5.2 Translated Bus Timing
4.4.2.1 Output Signals: Internal Propagation Delays
3.5.3 The FLT (Float) Pin
4.4.2.2 Input Signals Requirements
3.5.4 Aborting Bus Cycles
4.4.2.3 Clocking Requirements
3.5.4.1 The Abort Interrupt
4.4.3 Timing Requirements
3.5.4.2 Hardware Considerations
Appendix A: Instruction Formats
3.6 Bus Access Control
B: Interfacing Suggestions
3.7 Dual Processing
3.7.1 Bus Arbitration
3.7.2 Processor Assignment
2-364
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List of Illustrations
The General and Dedicated Registers ............................................................................2-1
Processor Status Register .......................................................................................2-2
CFG Register .................................................................................................. 2-3
Module Descriptor Format. ......................................................................................2-4
A Sample Link Table ...........................................................................................2-5
General Instruction Format ......................................................................................2-6
Index Byte Format .............................................................................................2-7
Displacement Encodings ........................................................................................2-8
Recommended Supply Connections .............................................................................. 3-1
Clock Timing Relationships ......................................................................................3-2
Power-On Reset Requirements ..................................................................................3-3
General Reset Timing ..........................................................................................3-4
Recommended Reset Connections, Non-Memory-Managed System ................................................. 3-5a
Recommended Reset Connections, Memory-Managed System ..................................................... 3-5b
Bus Connections ...............................................................................................3-6
Read Cycle Timing .............................................................................................3-7
Write Cycle Timing .............................................................................................3-8
ROY Pin Timing ................................................................................................3-9
Extended Cycle Example ......................................................................................3-1 0
Memory Interface .............................................................................................3-11
Slave Processor Connections ..................................................................................3-12
CPU Read from Slave Processor ................................................................................3-13
CPU Write to Slave Processor ..................................................................................3-14
Read Cycle with Address Translation (CPU Action) ................................................................3-15
Write Cycle with Address Translation (CPU Action) ................................................................ 3-16
Memory-Managed Read Cycle ..................................................................................3-17
Memory-Managed Write Cycle ..................................................................................3-18
FLTTiming ........................ : .......................................................................... 3-19
HOLD Timing, Bus Initially Idle ..................................................................................3-20
HOLD Timing, Bus Initially Not Idle .............................................................................. 3-21
Interrupt Dispatch and Cascade Tables .......................................................................... 3-22
Interrupt/Trap Service Routine Calling Sequence ................................................................. 3-23
Return from Trap (RETT n) Instruction Flow ...................................................................... 3-24
Return from Interrupt (REn Instruction Flow ......................................................................3-25
Interrupt Control Connections (16 levels) .........................................................................3-26
Cascaded Interrupt Control Unit Connections ..................................................................... 3-27
Service Sequence ............................................................................................3-28
Slave Processor Protocol ......................................................................................3-29
Slave Processor Status Word Format ............................................................................ 3-30
NS32016 Connection Diagram .................................................................................. .4-1
Timing Specification Standard (Signal Valid after Clock Edge) ........................................................ 4-2
Timing Specification Standard (Signal Valid before Clock Edge) ..................................................... .4-3
Write Cycle ................................................................................................... .4-4
Read Cycle ....................................................................................................4-5
Floating by HOLD Timing (CPU Not Idle Initially) .................................................................... 4-6
Floating by HOLD Timing (CPU Initially Idle) ....................................................................... 4-7
2-365
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List of Illustrations (Continued)
Release from HOLD ...............................•................•...........................................4-8
FLT Initiated Float Cycle Timing ...........•...•......................................•.....•...................•. 4-9
Release from FLTTiming ••....................................................................................4-10
Ready Sampling (CPU Initially READy) •..•••.•...•...•...•.........•...•....•....•..•.••.••.•......•....•....... 4-11
Ready Sampling (CPU Initially NOT READY) .....................•...••...••.................•••.•....•..•........ 4-12
Slave Processor Write Timing ..•.......•........................................................................4-13
Slave Processor Read Timing .................•.......•.......................•...•....•...•.........•...•....•4-14
SPCTiming ••..••.•.•..•...•..................................................................................4-15
Reset Configuration Timing ...•.•..•........................................•........•........•....•...........•4-16
Clock Waveforms .......................................................•.................................... .4-17
Relationship of PFS to Clock Cycles ..................•.................•....•...•.....................•.........4-18
Guaranteed Delay, PFS to Non-Sequential Fetch ................................................................4-19a
Guaranteed Delay, Non-Sequential Fetch to PFS ..•....•..•....•....•...•.•..•....•..•.•...•...•....•....•..•.•. 4-19b
Relationship of ILO to First Operand otan Interlocked Instruction ..•.............•....••...•..................•... .4-20a
Relationship of ILO to Last Operand of an Interlocked Instruction .....................................•............ 4-20b
Relationship of ILO to Any Clock Cycle •..........•................•...............•...•.............••.......... 4-21
U/S Relationship to Any Bus Cycle - Guaranteed Valid Interval .................................................... 4-22
Abort Timing, FLT Not Applied .•.•..............•.........•.............•..............•...•..................••4-23
Abort Timing, FLT Applied ..........................................................•.......................... .4-24
Power-On Reset ..•....•......•....•...•.......••......................•....•........•........•....•....•...•.4-25
Non-Power-On Reset ..................................•.......................................................4-26
INT Interrupt Signal Detection .................................................................................. 4-27
NMllnterrupt Signal Timing .•........•.......•....•....•........•..................•...••.....................• .4-28
Relationship between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction ........................... 4-29
System Connection Diagram .•......................................................•.•..............•......•...B-1
List of Tables
NS32016 Addressing Modes •....•.......•.............•....•..........................•...............•........ 2-1
NS32016 Instruction Set Summary ............................................................................... 2-2
Bus Cycle Categories .......................................•...................................................3-1
Access Sequences ................................................................•.............•.........•...•3-2
Interrupt Sequences •...•....................................................................................... 3-3
Floating Point Instruction Protocols .............................................•................................. 3-4
Memory Management Instruction Protocols ...........................................•..................•.......•.3-5
Custom Slave Instruction Protocols ..................•...................................................•....•...3-6
2-366
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1.0 Product Introduction
Co)
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The Series 32000 Microprocessor family is a new generation of devices using National's XMOS and CMOS technologies. By combining state-of-the-art MOS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. The family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
Memory Management: Either the NS32382 or the
NS32082 Memory Management Unit may be added to the
system to provide advanced operating system support functions, including dynamic address translation, virtual memory
management, and memory protection.
Large, Uniform Addressing: The NS32016 has 24-bit address pOinters that can address up to 16 megabytes without
requiring any segmentation; this addressing scheme provides flexible memory management without added-on expense.
Modular Software Support: Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a significant reduction in hardware and
software cost.
Software Processor Concept: The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
• High-Level Language Support
Powerful Addressing Modes: Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types: The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
Symmetric Instruction Set: While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Memory-to-Memory Operations: The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided. This powerful memory-to-memory architecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
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• Easy Future Growth Path
• Application Flexibility
2.0 Architectural Description
2.1 PROGRAMMING MODEL
fI
The Series 32000 architecture includes 16 registers on the
NS32016 CPU.
GENERAL
DEDICATED
32
32
PROGRAM COUNTER
PC
STAnCBASE
sa
FRAME POINTER
FP
RO
RI
R2
R3
USER STACK PTR.
INTERRUPT STACK PTR.
INTERRUPT BASE
SPI} SP
SPO
R4
R5
INTBASE
PSR
MOD
R6
STATUS
MDDULE
R7
TUEE/5054-3
FIGURE 2-1. The General and Dedicated Registers
2.1.1 General Purpose Registers
There are eight registers for meeting high speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are thirty-two bits in
length. If a general register is specified for an operand that
is eight or sixteen bits long, only the low part of the register
is used; the high part is not referenced or modified.
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2.0 Architectural Description
(Continued)
N
2.1.2 Dedicated Registers
Z
The eight dedicated registers of the NS32016 are assigned
specific functions.
~
C: The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used with the
ADDC and SUBC instructions to perform multiple-precision
integer arithmetic calculations. It may have a setting of 0 (no
carry or borrow) or 1 (carry or borrow).
PC: The PROGRAM COUNTER register is a pointer to the
first byte of the instruction currently being executed. The PC
Is used to reference memory in the program section. (In the
NS32016 the upper eight bits of this register are always
zero.)
T: The T bit causes program traCing. If this bit is a 1, a TRC
trap is executed after every instruction (Section 3.B.5).
L: The L bit is altered by comparison instructions. In a comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both operands are
interpreted as unsigned integers. Otherwise, it is set to "0".
In Floating Point comparisons, this bit is always cleared.
SPO, SP1: The SPO register points to the lowest address of
the last item stored on the INTERRUPT STACK. This stack
is normally used only by the operating system. It is used
primarily for storing temporary data, and holding return information for operating system subroutines and interrupt and
trap service routines. The SP1 register points to the lowest
address of the last item stored on the USER STACK. This
stack is used by normal user programs to hold temporary
data and subroutine return information.
F: The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions use it
to indicate overflow).
Z: The Z bit is altered by comparison instructions. In a comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is set to "0".
In this document, reference is made to the SP register. The
terms "SP register" or "SP" refer to either SPO or SP1,
depending on the setting of the S bit in the PSR register. If
the S bit in the PSR is 0 then SP refers to SPO. If the S bit in
the PSR is 1 then SP refers to SP1. (In the NS32016 the
upper eight bits of these registers are always zero.)
N: The N bit is altered by comparison instructions. In a comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both operands are
interpreted as signed integers. Otherwise, it is set to "0".
U: If the U bit is "1" no privileged instructions may be executed. If the U bit is "0" then all instructions may be executed. When U = 0 the NS32016 is said to be in Supervisor
Mode; when U= 1 the NS32016 is said to be in User Mode.
A User Mode program is restricted from executing certain
instructions and accessing certain registers which could interfere with the operating system. For example, a User
Mode program is prevented from changing the setting of the
flag used to indicate its own privilege mode. A Supervisor
Mode program is assumed to be a trusted part of the operating system, hence it has no such restrictions.
Stacks in the Series 32000 family grow downward in memory. A Push operation pre-decrements the Stack Pointer by
the operand length. A Pop operation post-increments the
Stack Pointer by the operand length.
FP: The FRAME POINTER register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
The frame pointer holds the address in memory occupied by
the old contents of the frame pOinter. (In the NS32016 the
upper eight bits of this register are always zero.)
S: The S bit specifies whether the SPO register or SP1 register is used as the stack pointer. The bit is automatically
cleared on interrupts and traps. It may have a setting of 0
(use the SPO register) or 1 (use the SP1 register).
SB: The STATIC BASE register points to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module. (In the NS32016 the upper
eight bits of this register are always zero.)
P: The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3.B.5). It may have a setting
of 0 (no trace pending) or 1 (trace pending).
I: If 1= 1, then all interrupts will be accepted (Section 3.B). If
1=0, only the NMI interrupt is accepted. Trap enables are
not affected by this bit.
INTBASE: The INTERRUPT BASE register holds the address of the dispatch table for interrupts and traps (Section
3.B). The INTBASE register holds the lowest address in
memory occupied by the dispatch table. (In the NS32016
the upper eight bits of this register are always zero.)
2.1.3 The Configuration Register (CFG)
Within the Control section of the NS32016 CPU is the fourbit CFG Register, which declares the presence of certain
external devices. It is referenced by only one instruction,
SETCFG, which is intended to be executed only as part of
system initialization after reset. The format of the CFG Register is shown in Figure 2-3.
MOD: The MODULE register holds the address of the module descriptor of the currently executing software module.
The MOD register is sixteen bits long, therefore the module
table must be contained within the first 64K bytes of memory.
PSR: The PROCESSOR STATUS REGISTER (PSR) holds
the status codes for the NS32016 microprocessor.
The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all programs, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
15
B
17
FIGURE 2-3. CFG Register
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the NS32202 Interrupt Control Unit). If the CFG I bit is set, interrupts requested through
the INT pin are "Vectored." If it is clear, these interrupts are
"Non-Vectored." See Section 3.8.
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The F, M and C bits declare the presence of the FPU, MMU
and Custom Slave Processors. If these bits are not set, the
corresponding instructions are trapped as being undefined.
TUEE/5054-Bl
FIGURE 2·2. Processor Status Register
2-36B
2.0 Architectural Description (Continued)
16115
2.1.4 Memory Organization
The main memory of the NS32016 is a uniform linear address space. Memory locations are numbered sequentially
starting at zero and ending at 224 - 1. The number specifying a memory location is called an address. The contents of
each memory location is a byte consisting of eight bits. Unless otherwise noted, diagrams in this document show data
stored in memory with the lowest address on the right and
the highest address on the left. Also, when data is shown
vertically, the lowest address is at the top of a diagram and
the highest address at the bottom of the diagram. When bits
are numbered in a diagram, the least significant bit is given
the number zero, and is shown at the right of the diagram.
Bits are numbered in increasing significance and toward the
left.
MSB's
817
LSB's
LSB's
01
2.1.5 Dedicated Tables
Two of the NS32016 dedicated registers (MOD and INTBASE) serve as pointers to dedicated tables in memory.
The INTBASE register pOints to the Interrupt Dispatch and
Cascade tables. These are described in Section 3.8.
The MOD register contains a pOinter into the Module Table,
whose entries are called Module Descriptors. A Module Descriptor contains four pointers, three of which are used by
the NS32016. The MOD register contains the address of the
Module Descriptor for the currently running module. It is automatically updated by the Call External Procedure instructions (CXP and CXPD).
The format of a Module Descriptor is shown in Figure 2-4.
The Static Base entry contains the address of static data
assigned to the running module. It is loaded into the CPU
Static Base register by the CXP and CXPD instructions. The
Program Base entry contains the address of the first byte of
instruction code in the module. Since a module may have
multiple entry pOints, the Program Base pOinter serves only
as a reference to find them.
Byte at Address A
Two contiguous bytes are called a word. Except where noted (Section 2.2.1), the least significant byte of a word is
stored at the lower address, and the most significant byte of
the word is stored at the next higher address. In memory,
the address of a word is the address of its least significant
byte, and a word may start at any address.
115
817
A
A+2
A+1
Double Word at Address A
Although memory is addressed as bytes, it is actually organized as words. Therefore, words and double words that are
aligned to start at even addresses (multiples of two) are
accessed more quickly than words and double words that
are not so aligned.
A+3
0I
A+1
A
Word at Address A
Two contiguous words are called a double word. Except
where noted (Section 2.2.1), the least significant word of a
double word is stored at the lowest address and the most
significant word of the double word is stored at the address
two greater. In memory, the address of a double word is the
address of its least significant byte, and a double word may
start at any address.
The Link Table Address points to the Link Table for the
currently running module. The Link Table provides the information needed for:
1) Sharing variables between modules. Such variables
are accessed through the Link Table via the External
addressing mode.
'5
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MOD
I
31
STATIC SASE
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ENTRY
LINK TABLE ADDRESS
PROGRAM BASE
ABSOLUTE ADDRESS
(VARIABLE)
ABSOLUTE ADDRESS
(VARIABLE)
OFFSET
RESERVED
I
MODULE
(P ROCEDURE)
....
TL/EE/5054-5
FIGURE 2·5. A Sample Link Table
TL/EE/5054-4
FIGURE 2·4. Module Descriptor Format
OPTIONAL
EXTENSIONS
BASIC
INSTRUcnON
r~------------~A~---------------~~-----,
DISP2DISP1
IMPUED
_EDIATE
OPE"AND(S)
DISP
IMII
.
DISP~~ISP1
DISP
I
INDEX
BYTE
INDEX
BYTE
GEN
ADCR
MODE
A
IMII
II
I
I
GEN
ADDR
MODE
B
OPCODe
t I Y
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TL/EE/5054-6
FIGURE 2·6. General Instruction Format
2-369
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2.0 Architectural Description
2)
(Continued)
NS32016 Addressing Modes fall into nine basic types:
Register: The operand Is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
.
instead.
Transferring control from one module to another. This
is done via the Call External Procedure (CXP) instruction.
The format of a Link Table is given in Figure 2-5. A Link
Table Entry for an external variable contains the 32-bit address of that variable. An entry for an external procedure
contains two 16-bit fields: Module and Offset. The Module
field contains the new MOD register contents for the module being entered. The Offset field is an unsigned number
giving the position of the entry point relative to the new
module's Program Base pOinter.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Byte Displacement: Range - 64 to + 63
For further details of the functions of these tables, see the
Series 32000 Instruction Set Reference Manual.
2.2 INSTRUCTION SET
1'0
2.2.1 General Instruction Format
_~~_
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01
Figure 2-6 shows the general format of a Series 32000 instruction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to 5-bit General Addressing Mode ("Gen") fields. Following the Basic Instruction
field is a set of optional extensions, which may appear depending on the instruction and the addressing modes selected.
Word Displacement: Range -8192 to +8191
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-7.
Double Word Displacement:
Range (Entire Addressing Space)
7
1
GEN. ADDR. MODE
:
1
0
I
//-
REG. NO.
TL/EE/5054-7
FIGURE 2-7. Index Byte Format
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Displlmm field may contain
one of two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-8, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most-significant byte first. Note that this is different from the memory
representation of data (Section 2.1.4).
TL/EE/5054-10
FIGURE 2-8. Displacement Encodlngs
Memory Relative: A pOinter variable is found within the
memory space pOinted to by the SP, SB or FP register. A
displacement is added to that pointer to generate the Effective Address of the operand.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
Some instructions require additional "implied" immediates
andlor displacements, apart from those associated with addreSSing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Section 2.2.3).
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
2.2.2 Addressing Modes
The NS32016 CPU generally accesses an operand by calculating its Effective Address based on information available when the operand is to be accessed. The method to be
used in performing this calculation is specified by the pro·
grammer as an "addressing mode."
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding into the
total, yielding the final Effective Address of the operand.
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Series 32000
Instruction Set Reference Manual.
Addressing modes in the NS32016 are designed to optimally support high-level language accesses to variables. In
nearly all cases, a variable access requires only one addressing mode, within the instruction that acts upon that
variable. Extraneous data movement is therefore minimized.
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2.0 Architectural Description
(0)
I\)
(Continued)
....
....o•
o
TABLE 2·1
G)
NS32016 Addressing Modes
ENCODING
Register
00000
00001
00010
00011
00100
00101
00110
00111
MODE
EFFECTIVE ADDRESS
ASSEMBLER SYNTAX
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO orFO
R1 or F1
R20rF2
R30rF3
R4 or F4
R50rF5
R60rF6
R60rF7
None: Operand is in the specified
register.
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (SB))
Disp2 + Pointer; Pointer found at
address Disp 1 + Register. "SP"
is either SPO or SP1, as selected
inPSR.
Immediate
value
None: Operand is input from
instruction queue.
Absolute
@disp
Disp.
10110
External
EXT (disp1)
Top Of Stack
10111
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
"+ disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2 x Rn.
EA (mode) + 4 x Rn.
EA(mode) + 8xRn.
"Mode" and "n" are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
+ Register.
Memory Relative
10000
10001
10010
Reserved
10011
(Reserved for Future Use)
Immediate
10100
Absolute
10101
External
+ disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Memory Space
11000
11001
11010
11011
Scaled Index
11100
11101
11110
11111
2·371
o
..ch
..o
r-----------------------------------------------------------------------------,
a
z
2.0 Architectural Description (Continued)
2.2.3InstructJon Set Summary
short=A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
Table 2·2 presents a brief description of the NS32016 in·
struction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Series 32000 Instruction Set Reference Manual.
imm = Implied immediate operand. An 8-bit value appended
after any addressing extensions.
disp = Displacement (addressing constant): 8, 16 or 32 bits.
All three lengths legal.
reg=Any General Purpose Register: RO-R7.
areg=Any Dedicated/Address Register: SP, SB, FP, MOD,
INTBASE, PSR, US (bottom 8 PSR bits).
Notations:
i = Integer length suffix: B = Byte
W= Word
D = Double Word
mreg = Any Memory Management Status/Control Register.
creg = A Custom Slave Processor Register (Implementation
Dependent).
f = Floating Point length suffix: F = Standard Floating
L = Long Floating
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
gen = General operand. Any addressing mode can be specified.
TABLE 2-2
NS32016 Instruction Set Summary
MOVES
Format
4
2
7
7
7
7
7
4
Operation
Operands
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Move a value.
Extend and move a signed 4-bit constant.
Move multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move effective address.
Operands
Description
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add Signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to extended integer.
Divide extended integer.
INTEGER ARITHMETIC
Format
Operation
4
2
4
4
4
6
6
7
7
7
7
7
7
7
ADDi
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEIi
DEli
PACKED DECIMAL (BCD) ARITHMETIC
Format
Operation
Operands
6
6
ADDPi
SUBPi
gen,gen
gen,gen
Description
Description
Add packed.
Subtract packed.
2-372
z
2.0 Architectural Description
en
w
(Continued)
N
TABLE 2-2
NS32016 Instruction Set Summary (Continued)
INTEGER COMPARISON
Format
Operation
4
CMPi
2
CMPQi
7
CMPMi
Operands
gen,gen
short,gen
gen,gen,disp
Description
Compare.
Compare to signed 4-bit constant.
Compare multiple: disp bytes (1 to 16).
LOGICAL AND BOOLEAN
Format
Operation
Operands
Description
ANDi
ORi
BICi
XORi
COMi
NOTi
Scondi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Logical AND.
Logical OR.
Clear selected bits.
Logical exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
Operation
Operands
Description
LSHi
ASHi
ROTi
gen,gen
gen,gen
gen,gen
Logical shift, left or right.
Arithmetic shift, left or right.
Rotate, left or right.
Operation
Operands
Description
TBITi
SBITi
SBlTIi
CBITi
CBITli
IBITi
FFSi
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Test bit.
Test and set bit.
Test and set bit, interlocked.
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit.
4
4
4
4
6
6
2
SHIFTS
Format
6
6
6
BITS
Format
4
6
6
6
6
6
8
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records used in
Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned source.
Format
Operation
Operands
Description
8
8
7
7
8
ARRAYS
Format
8
8
....a>
•
....
o
o
EXTi
INSi
EXTSi
INSSi
CVTP
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm.imm
reg,gen,gen
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to bit field pOinter.
Operation
CHECKi
INDEXi
Operands
reg.gen,gen
reg.gen,gen
Description
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
2-373
*'....
C)
r------------------------------------------------------------------------------------------,
2.0 Architectural Description
~
(Continued)
TABLE 2-2
NS32016 Instruction Set Summary (Continued)
C")
~
STRINGS
String instructions assign specific functions to the General
Purpose Registers:
Options on all string instructions are:
B (Backward):
Decrement strong pointers after each
step rather than incrementing.
R4 -
Comparison Value
U (Until match):
R3 -
Translation Table Pointer
R2 -
String 2 Pointer
Rl -
String 1 Pointer
RO -
Limit Count
Format
5
5
5
Operation
MOVSi
MOVST
CMPSi
CMPST
SKPSi
SKPST
End instruction if String 1 entry matches
R4.
W (While match): End instruction if String 1 entry does not
match R4.
All string instructions end when RO decrements to zero.
Operands
options
options
options
options
options
options
Description
Move string 1 to string 2.
Move string, translating bytes.
Compare string 1 to string 2.
Compare, translating string 1 bytes.
Skip over string 1 entries.
Skip, translating bytes for until/while.
JUMPS AND LINKAGE
Format
3
0
0
3
2
3
3
Operation
Operands
Description
JUMP
BR
Bcond
CASEi
ACBi
JSR
BSR
CXP
CXPD
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure
Call external procedure using descriptor.
Supervisor call.
Flag trap.
Breakpoint trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
[reg list), disp
[reg list]
disp
disp
disp
CPU REGISTER MANIPULATION
Format
1
2
2
3
3
3
5
Operation
Operands
Description
SAVE
RESTORE
LPRi
SPRi
ADJSPi
BISPSRi
BICPSRi
SETCFG
[reg list]
[reg list]
areg,gen
areg,gen
gen
gen
gen
[option list]
Save general purpose registers.
Restore general purpose registers.
Load dedicated register. (Privileged if PSR or INTBASE)
Store dedicated register. (Privileged if PSR or INTBASE)
Adjust stack pOinter.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set configuration register. (Privileged)
2-374
z
2.0 Architectural Description
en
Co:!
(Continued)
TABLE 2·2
NS32016 Instruction Set Summary (Continued)
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Description
Move a floating point value.
Move and shorten a long value to standard.
Move and lengthen a standard value to long.
Convert any integer to standard or long floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Load FSR.
Store FSR.
MEMORY MANAGEMENT
Format
Operation
Operands
Description
8
LMR
SMR
RDVAL
WRVAL
MOVSUi
mreg,gen
mreg,gen
gen
gen
gen,gen
8
MOVUSi
gen,gen
Load memory management register. (Privileged)
Store memory management register. (Privileged)
Validate address for reading. (Privileged)
Validate address for writing. (Privileged)
Move a value from supervisor
space to user space. (Privileged)
Move a value from user space
to supervisor space. (Privileged)
MISCELLANEOUS
Format
Operation
1
1
1
CUSTOM SLAVE
Format
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.1
15.1
15.1
15.1
15.1
15.1
15.1
15.1
15.0
15.0
15.0
15.0
Q)
.....
I
FLOATING POINT
Format
Operation
11
MOVf
9
MOVLF
9
MOVFL
9
MOVif
9
ROUNDfi
9
TRUNCfi
9
FLOORfi
11
ADDf
11
SUBf
11
MUll
11
DIVf
11
CMPf
11
NEGf
11
ABSf
9
LFSR
9
SFSR
14
14
14
14
N
Q
.....
Operands
NOP
WAIT
DIA
Description
No operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
Operation
Operands
Description
CCALOc
CCAL1c
CCAL2c
CCAL3c
CMOVOc
CMOV1c
CMOV2c
CMOV3c
CCMPOc
CCMP1c
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
LCSR
SCSR
CATSTO
CATST1
LCR
SCR
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
gen
gen
creg,gen
creg,gen
Custom calculate.
Custom move.
Custom compare.
Custom convert.
Load custom status register.
Store custom status register.
Custom address/test. (Privileged)
(Privileged)
Load custom register. (Privileged)
Store custom register. (Privileged)
2-375
Q
,..
u,
,..
«:)
«:)
('II
Cf)
U)
z
3.0 Functional Description
Each rising edge of PHI1 defines a transition in the timing
state ("T-State") of the CPU. One T-State represents the
execution of one microinstruction within the CPU, and/or
one step of an external bus transfer. See Section 4 for complete specifications of PHI1 and PHI2.
3.1 POWER AND GROUNDING
The NS32016 requires a single 5-volt power supply, applied
on pin 48 {Vecl.
Grounding connections are made on two pins. Logic Ground
(GNDL, pin 24) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 25) is the common pin for the
output drivers. For optimal noise immunity, it is recommended that GNDL be attached through a single conductor directly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 3-1).
PHI1
In addition to Vee and Ground, the NS32016 CPU uses an
internally-generated negative voltage. It is necessary to filter
this voltage externally by attaching a pair of capacitors (Figure 3-1) from the BBG pin to ground. Recommended values
of these are:
PHI2
C1: 1 JLF, Tantalum.
C2: 1000 pF, low inductance. This should be either a disc or
monolithic ceramic capacitor.
TL/EE/SOS4-12
~
1
y+5V
FIGURE 3-2_ Clock Timing Relationships
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHI1 and PHI2
be kept as short as possible, and that they not be connected anywhere except from the TCU to the CPU and, if present, the MMU. A TTL Clock signal (CTTL) is provided by the
TCU for all other clocking.
vcc~
NS32018
cpu
3.3 RESETTING
The RST/ ABT pin serves both as a Reset for on-chip logic
and as the Abort input for Memory-Managed systems. For
its use as the Abort Command, see Section 3.5.4.
The CPU may be reset at any time by pulling the RST / ABT
pin low for at least 64 clock cycles. Upon detecting a reset,
the CPU terminates instruction processing, resets its internal logic, and clears the Program Counter (PC) and Processor Status Register (PSR) to all zeroes.
TL/EE/SOS4-11
FIGURE 3-1_ Recommended Supply Connections
3.2 CLOCKING
The NS32016 inputs clocking signals from the NS32201
Timing Control Unit (TCU), which presents two non-overlapping phases of a single clock frequency. These phases are
called PHI1 (pin 26) and PHI2 (pin 27). Their relationship to
each other is shown in Figure 3-2.
On application of power, RST/ABT must be held low for at
least 50 JLs after Vee is stable. This is to ensure that all onchip voltages are completely stable before operation.
Whenever a Reset is applied, it must also remain active
vcc
PHI1
---+---~I
r-
RSf/m
264 CLOCK
CYCLES
JJ-JL
---+----------1
f-00-----250~aec---·-
.TL/EE/SOS4-13
FIGURE 3-3_ Power-On Reset Requirements
2-376
3.0 Functional Description (Continued)
for not less than 64 clock cycles. The rising edge must occur while PHI1 is high. See Figures 3-3 and 3-4.
The NS32201 Timing Control Unit (TCU) provides circuitry
to meet the Reset requirements of the NS32016 CPU. Figure 3-58 shows the recommended connections for a nonMemory-Managed system. Figure 3-5b shows the connections for a Memory-Managed system.
PHil
'""1·~--"64CLOCK-1
Rsi'IABT---.....,~~~~
CYCLES
,--
-
rl
.
TLIEEISOS4-14
FIGURE 3-4. General Reset Timing
VCC
NS32018
NS32201
TCU
cpu
. ------------,
I
I
I
I RESET
I
l>......:-+-_-l---+-~....- - - - I iiSTi
RSTO
I - - - - - t - - - - - - I iiSrlm
!L. _____________ JI
,,50,,_
EXTERNAL RESET
(OPTIONAL)
RESET SWITCH
(OPTIONAL)
SYSTEM RESET
TLlEEISOS4-1S
FIGURE 3-5a. Recommended Reset Connections, Non-Memory-Managed System
vcc
NS32201
TCU
NS32082
MMU
NS32018
CPU
.. ------------,
I
I
I
I RESET
I
J>-rl-+-....,.-+--+~------t
iiSTi
RsTo
!L. _____________ JI
EXTERNAL RESET
(OPTIONAL)
RESET SWITCH
(OPTIONAL)
TLIEEIS054-16
FIGURE 3-5b. Recommended Reset Connections, Memory-Managed System
3) To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
4) To transfer information to or from a Slave Processor.
3.4 BUS CYCLES
The NS32016 CPU has a strap option which defines the Bus
TIming Mode as either With or Without Address Translation.
This section describes only bus cycles under the No Address Translation option. For details of the use of the strap
and of bus cycles with address translation, see Section 3.5.
The CPU will perform a bus cycle for one of the following
reasons:
1) To write or read data, to or from memory or a peripheral
interface device. Peripheral input and output are memory-mapped in the Series 32000 family.
In terms of bus timing, cases 1 through 3 above are identical. For timing speCifications, see Section 4. The only external difference between them is the four-bit code placed on
the Bus Status pins (STO-ST3). Slave Processor cycles differ in that separate control signals are applied (Section
3.4.6).
The sequence of events in a non-Slave bus cycle is shown
in Figure 3-7 for a Read cycle and Figure 3-8 for a Write
cycle. The cases shown assume that the selected memory
or interface device is capable of communicating with the
CPU at full speed. If it is not, then cycle extension may be
requested through the RDY line (Section 3.4.1).
2) To fetch instructions into the eight-byte instruction
queue. This happens whenever the bus would otherwise
be idle and the queue is not already full.
2-377
....o r-----------------------------------------------------------------------------,
ch
....
o
~
Z
3.0 Functional Description (Continued)
A full-speed bus cycle is performed in four cycles of the
PHI1 clock signal, labeled T1 through T4. Clock cycles not
associated with a bus cycle are designated Ti (for "Idle").
During T1, the CPU applies an address on pins ADO-AD15
and A16-A23. It also provides a low-going pulse on the
ADS pin, which serves the dual purpose of informing external Circuitry that a bus cycle is starting and of providing control to an external latch for demultiplexing Address bits 015 from the ADO-AD15 pins. See Figure 3-6. During this
time also the status signals DDIN, indicating the direction of
the transfer, and HBE, indicating whether the high byte
(AD8-AD15) is to be referenced, become valid.
During T2 the CPU switches the Data Bus, ADO-AD15, to
either accept or present data. Note that the signals A16A23 remain valid, and need not be latched. It also starts the
data strobe (DS), signaling the beginning of the data transfer. Associated signals from the NS32201 Timing Control
Unit are also activated at this time: RD (Read Strobe) or WR
(Write Strobe), TSO (Timing State Output, indicating that T2
has been reached) and DBE (Data Buffer Enable).
ODIN
The T3 state provides for access time requirements, and it
occurs at least once in a bus cycle. At the end of T2 or T3,
on the falling edge of the PHI2 clock, the RDY (Ready) line
is sampled to determine whether the bus cycle will be extended (Section 3.4.1).
If the CPU is performing a Read cycle, the Data Bus (ADOAD15) is sampled at the falling edge of PHI2 of the last T3
state. See Section 4. Data must, however, be held at least
until the beginning of T4. DS and RD are guaranteed not to
go inactive before this pOint, so the rising edge of either of
them may safely be used to disable the device providing the
input data.
The T4 state finishes the bus cycle. At the beginning of T4,
the DS, RD, or WR, and TSO signals go inactive, and at the
rising edge of PHI2, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles remains valid from the CPU throughout T4. Note that the Bus
Status lines (STO-ST3) change at the beginning of T4, anticipating the following bus cycle (if any).
1--_---....
NS320'8 .
AO(LBE)
PHI'
DiiE
PHI2
NS3ZZO'
Ro
iiDl-----------
1----------no
;:so 1-----------WR
TL/EE/5054-17
FIGURE 3-6. Bus Connections
2-378
Z
tn
Co)
3.0 Functional Description (Continued)
I\)
....
m
....•
Q
I
PHI1
[
PHIZ
[
A16·A23
[
AOO·AD15
[
ADS
[
STD-ST3
[
iiDiN
[
HiE
[
iii
[
T40RTI
I
NS32018CPU BUS SIGNALS
T1
T2
T3
T4
I
T10RTI
I
Q
RDY [
DiE [
iSci[
TL/EE/5054-1B
FIGURE 3-7. Read Cycle Timing
2-379
.... r---------------------------------------------------------------------------------,
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.... 3.0 Functional Description (Continued)
C)
C)
C"I
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NS32D18 CPU BUS SIGNALS
en
z
TUEE/5Q54-19
FIGURE 3·8. Write Cycle Timing
2-380
3.0 Functional Description
z
en
c.:I
(Continued)
N
3.4.1 Cycle Extension
The RDY pin is driven by the NS32201 Timing Control Unit,
which applies WAIT States to the CPU as requested on
three sets of pins:
1) CWAIT (Continues WAIT), which holds the CPU in WAIT
states until removed.
2) WAIT1, WAIT2, WAIT4, WAIT8 (Collectively WAITn),
which may be given a four-bit binary value requesting a
specific number of WAIT States from 0 to 15.
3) PER (Peripheral), which inserts five additional WAIT
states and causes the TCU to reshape the RO and WR
strobes. This provides the setup and hold times required
by most MOS peripheral interface devices.
Combinations of these various WAIT requests are both legal
and useful. For details of their use, see the NS32201 TCU
Data Sheet.
Figure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the TCU WAITn pins.
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32016 provides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-7 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are flat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the ROY (Ready) pin.
At the end of T2 on the falling edge of PHI2, the ROY line is
sampled by the CPU. If ROY is high, the next T-states will be
T3 and then T4, ending the bus cycle. If it is sampled low,
then another T3 state will be inserted after the next T-state
and the ROY line will again be sampled on the falling edge
of PHI2. Each additional T3 state after the first is referred to
as a "wait state." See Figure 3-9.
11
T2
T3
I
T3
(WAIT)
T4
PHI1
PHI 2
ROY
TL/EE/S054-20
FIGURE 3·9. ROY Pin Timing
3.4.2 Bus Status
The NS32016 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on these
pins indicate why the CPU is performing a bus cycle, or, if it
is idle on the bus, then why it is idle.
the Master NS32202 Interrupt Control Unit. If
the vectoring mode selected by the last
SETCFG instruction was Non-Vectored, then
the CPU will ignore the value it has read and will
use a default vector instead, having assumed
that no NS32202 is present. See Section 3.4.5.
0101 Interrupt Acknowledge, Cascaded.
The CPU is reading a vector number from a
Cascaded NS32202 Interrupt Control Unit. The
address provided is the address of the
NS32202 Hardware Vector register. See Section 3.4.5.
0110- End of Interrupt, Master.
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt
(RETI) instruction. See Section 3.4.5.
Referring to Figures 3-7 and 3-8, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1, and changing to the next state at T 4. This allows
the system designer to fully decode the Bus Status and, if
desired, latch the decoded signals before ADS initiates the
Bus Cycle.
The Bus Status pins are interpreted as a four-bit value, with
STO the least significant bit. Their values decode as follows:
0000 -
The bus is idle because the CPU does not need
to perform a bus access.
0001 The bus is idle because the CPU is executing
the WAIT instruction.
0010- (Reserved for future use.)
0011 0100 -
0111 -
The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
Interrupt Acknowledge, Master.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt
(on NMI) it will read from address FFFF0016,
but will ignore any data provided.
To acknowledge receipt of a Maskable Interrupt
(on INT) it will read from address FFFE0016,
expecting a vector number to be provided from
1000 -
2-381
End of Interrupt, Cascaded.
The CPU is reading from a Cascaded Interrupt
Control Unit to indicate that it is returning
(through RETI) from an interrupt service routine
requested by that unit. See Section 3.4.5.
Sequential Instruction Fetch.
The CPU is reading the next sequential word
from the instruction stream into the Instruction
Queue. It will do so whenever the bus would
otherwise be idle and the queue is not already
full.
o......
.
en
......
o
Q .--------------------------------------------------------------------,
....
cD
3.0 Functional Description (Continued)
....
Q
C\I
('I)
en
N8320IB CPU BUS SIGNALS
PREV.CYCLE
z
I (¥l11T) I (¥l11T) I
_~Il-IL~IL
IT40RTii
PHil [
PHI2 [
AI6-A23 [
AIl().ADI5 [
TI
I
T2
I
TJ
NEXT CYCLE
T4
I
r
Il-Il- rL
- Ln -I1Lrl W1 W1 J Ln 01 r~~ ~
,
ADDRESS VALID
~ ~ ~ ADDR
VALID ~--~ ~~ ~~---~
IV
ADS [
STo-STJ [
InORT;
NEXTADDR
I-
IV
~~
IX
STATUS VALID
NEXT STATUS
I~r-
ffiiiN[ ~ W& ~
t-
tiBF.[ ~ ~ I?\
-V
~
R
~NEXT t-
VALID
1\
N832201 TCU CYCLE EXTENSION SIGNALS
CWAiT[ %; ~
~
rw
~~ W
~
~
~~ ~~ ~
I'W~ ~ tW2 ~ ~ f%
~
WAiTn[ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1%
'~
~
~
\
ROY [
(TCUTOCPU)
NS32201 TCU BUS SIGNALS
Rii[ - V
1\
Wii[ - V
iiiiE[ - ~
rso[ - V
V
\
TL/EE/5054-21
FIGURE 3·10. Extended Cycle Example
Note: Arrows on CWAIT, PER, WAiTn indicate points at which the TCU samples.
ROY indicate points at which the CPU samples.
2-382
Arrows on AOO-AOI5 and
z
3.0 Functional Description
en
Co)
(Continued)
I\)
C)
1001 -
Non-Sequential Instruction Fetch.
The CPU is performing the first fetch of instruction code after the Instruction Queue is purged.
This will occur as a result of any jump or branch,
or any interrupt or trap, or execution of certain
instructions.
1010 Data Transfer.
The CPU is reading or writing an operand of an
instruction.
1011- Read RMW Operand.
The CPU is reading an operand which will subsequently be modified and rewritten. If memory
protection circuitry would not allow the following
Write cycle, it must abort this cycle.
Read for Effective Address Calculation.
1100 The CPU is reading information from memory in
order to determine the Effective Address of an
operand. This will occur whenever an instruction uses the Memory Relative or External addressing mode.
Memory is organized as two eight-bit banks, each bank reo
ceiving the word address (A1-A23) in parallel. One bank,
connected to Data Bus pins ADO-AD7, is enabled to respond to even byte addresses; i.e., when the least significant address bit (AO) is low. The other bank, connected to
Data Bus pins AD8-AD15, is enabled when HBE is low. See
Figure 3- 11.
HBE
AO(LBE)
Al·AZ3
1101 -
Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing the Operation Word of a Slave Processor
instruction. See Section 3.9.1.
1110- Read Slave Processor Status.
The CPU is reading a Status Word from a Slave
Processor. This occurs after the Slave Processor has signalled completion of an instruction.
The transferred word tells the CPU whether a
trap should be taken, and in some instructions it
presents new values for the CPU Processor
Status Register bits N, Z, Lor F. See Section
3.9.1.
1111 -
BYTE
TL/EE/5054-22
FIGURE 3-11. Memory Interface
Any bus cycle falls into one of three categories: Even Byte
Access, Odd Byte Access, and Even Word Access. All ac·
cesses to any data type are made up of sequences of these
cycles. Table 3·1 gives the state of AO and HBE for each
category.
TABLE 3-1
Bus Cycle Categories
Category
HBE
AD
Even Byte
1
0
0
Odd Byte
0
0
Even Word
Accesses of operands requiring more than one bus cycle
are performed sequentially, with no idle T-States separating
them. The number of bus cycles required to transfer an op·
erand depends on its size and its alignment (i.e., whether it
starts on an even byte address or an odd byte address).
Table 3-2 lists the bus cycle performed for each situation.
For the timing of AO and HBE, see Section 3.4.
Broadcast Slave ID.
The CPU is initiating the execution of a Slave
Processor instruction. The ID Byte (first byte of
the instruction) is sent to all Slave Processors,
one of which will recognize it. From this point
the CPU is communicating with only one Slave
Processor. See Section 3.9.1.
3.4.3 Data Access Sequences
The 24-bit address provided by the NS32016 is a byte address; that is, it uniquely identifies one of up to 16,777,216
eight-bit memory locations. An important feature of the
NS32016 is that the presence of a 16-bit data bus imposes
no restrictions on data alignment; any data item, regardless
of size, may be placed starting at any memory address. The
NS32016 provides a special control signal, High Byte Enable (HBE), which facilitates individual byte addressing on a
16-bit bus.
2-383
......
en
•
......
C)
....
....CD
Q
I
3.0 Functional Description
(Continued)
Q
'"
CW)
(/)
Z
Cycle
Type
Address
TABLE 3.2
Access Sequences
HBE
AO
High Bus
Low Bus
A. Odd Word Access Sequence
BYTE 1
2
Odd Byte
Even Byte
A
A+1
0
1
0
Byte 0
Don't Care
BYTE 0
-A
Don't Care
Byte 1
B. Even Double-Word Access Sequence
2
Even Word
Even Word
A
A+2
BYTE 3
BYTE 2
0
0
0
0
BYTE 1
Byte 1
Byte 3
BYTE 0
-A
Byte 0
Byte 2
C. Odd Double-Word Access Sequence
BYTE 3
2
3
Odd Byte
Even Word
Even Byte
A
A+1
A+3
0
0
BYTE 2
0
0
BYTE 1
Byte 0
Byte 2
Don't Care
BYTE 0
-A
Don't Care
Byte 1
Byte 3
D. Even Quad-Word Access Sequence
BYTE 7
1
2
BYTE 6
BYTES
Even Word
Even Word
BYTE 4
BYTE 3
A
A+2
BYTE 2
BYTE 1
BYTE 0
0
0
0
0
Byte 1
Byte 3
Byte 0
Byte 2
0
0
0
0
Byte S
Byte 7
Byte 4
Byte 6
-A
Other bus cycles (instruction prefetch or slave) can occur here.
3
4
Even Word
Even Word
A+4
A+6
E. Odd Quad-Word Access Sequence
BYTE 7
2
3
BYTE 6
Odd Byte
Even Word
Even Byte
BYTES
BYTE 4
BYTE 3
A
A+1
A+3
BYTE 2
BYTE 1
BYTE 0
0
0
1
0
0
Byte 0
Byte 2
Don'teare
Don'teare
Byte 1
Byte 3
0
0
1
0
0
Byte 4
Byte 6
Don'teare
Don't Care
ByteS
Byte 7
Other bus cycles (instruction prefetch or slave) can occur here.
4
S
6
Odd Byte
Even Word
Even Byte
A+4
A+S
A+7
2-384
-A
3.0 Functional Description
z
en
Co)
(Continued)
I\)
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full. Sequential Fetches are always
Even Word Read cycles (Table 3-1).
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the instruction queue, causing the
next instruction fetch to display Non-Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status, and that cycle is either an Even Word Read or an
Odd Byte Read, depending on whether the destination address is even or odd.
3.4.3.1 Bit Accesses
The Bit Instructions perform byte accesses to the byte can·
taining the designated bit. The Test and Set Bit instruction
(SBIT), for example, reads a byte, alters it, and rewrites it,
having changed the contents of one bit.
3.4.3.2 Bit Field Accesses
An access to a Bit Field in memory always generates a Dou·
ble·Word transfer at the address containing the least signifi·
cant bit of the field. The Double Word is read by an Extract
instruction; an Insert instruction reads a Double Word, modifies it, and rewrites it.
3.4.3.3 Extending Multiply Accesses
The Extending Multiply Instruction (MEl) will return a result
which is twice the size in bytes of the operand it reads. If the
multiplicand is in memory, the most-significant half of the
result is written first (at the higher address), then the leastsignificant half. This is done in order to support retry if this
instruction is aborted.
o
......
en
•
......
o
3.4.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is inerrupt control rather
than the transfer of instructions or data, Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status presented on pins STO-ST3. All
Interrupt Control cycles are single-byte Read cycles.
3.4.4 Instruction Fetches
Instructions for the NS32016 CPU are "prefetched"; that is,
they are input before being needed into the next available
entry of the eight-byte Instruction Queue. The CPU performs
two types of Instruction Fetch cycles: Sequential and NonSequential. These can be distinguished from each other by
their differing status combinations on pins STO-ST3 (Section 3.4.2).
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine. For full details of the NS32016 interrupt
structure, see Section 3.8.
•
2-385
....o r-----------------------------------------------------------------------------,
....och 3.0 Functional Description (Continued)
TABLE 3·3
Interrupt Sequences
iza
Cycle
Status
AD
Address
High Bus
Low Bus
A. Non-Maskable Interrupt Control Sequences.
Interrupt Acknowledge
0100
1
FFFF0016
o
o
Don'teare
Don't Care
Interrupt Return
None: Performed through Return from Trap (RETT) Instruction.
8. Non- Vectored Interrupt Control Sequences.
Interrupt Acknowledge
0100
1
FFFE0016
o
o
Don't Care
Don't Care
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
C. Vectored Interrupt Sequences: Non-Csscaded.
Interrupt Acknowledge
0100
1
FFFE0016
o
o
Don't Care
Vector:
Range: 0-127
Interrupt Return
0110
1
FFFE0016
o
o
Don't Care
Vector: Same as
in Previous In!.
Ack.Cycle
D. Vectored Interrupt Sequences: Csscaded.
Interrupt Acknowledge
0100
1
FFFE0016
o
o
Don't Care
Cascade Index:
range -16to-1
(The CPU here uses the Cascade Indx to find the Cascade Address.)
2
0101
Cascade
0
1 or
0 or
1·
O·
Address
Vector, range 0-255; on appropriate
half of Data Bus for even/odd address
Interrupt Return
1
0110
Don't Care
Cascade Index:
same as in
previous In!.
Ack.Cycle
Don't Care
Don't Care
FFFE0016
o
o
(The CPU here uses the Cascade Index to find the Cascade Address.)
2
0111
Cascade
0
10r
Oor
Address
O·
1·
• If the Cascaded ICU Address Is Even (AO is low), then the CPU applies HSE high and reads the vector number from bits 0-7 of the Data Bus.
If the address is Odd (AO Is high), then the CPU applies RBE low and reads the vector number from bits 8-15 of the Data Bus. The vector number may be In the
range 0-255.
2-386
r--------------------------------------------------------------------,z
~
N
3.0 Functional Description (Continued)
...
3.4.6 Slave Processor Communication
AD(1I-15)
In addition to its use as the Address Translation strap (Sec·
tion 3.5.1), the AT /SPC pin is used as the data strobe for
Slave Processor transfers. In this role, it is referred to as
Slave Processor Control (SPC). In a slave processor bus
cycle, data is transferred on the Data Bus (ADO-AD15), and
the Status Lines STO-ST3 are monitored by each Slave
Processor in order to determine the type of transfer being
performed. SPC is bidirectional, but is driven by the CPU
during all Slave Processor bus cycles. See Section 3.9 for
full protocol sequences.
AT/SPC
~
"
o
.....
'P
.....
0111-15)
o
SPe
SLAVE
PROCESSOR
N83Z018
CPU
STG-ST3
STo-ST3
TL/EE/5054-23
FIGURE 3-12. Slave Processor Connections
PREV.CYCLE
I
PHil
[
PHI 2
[
sPc
[
ADO-AD15 [
T1
T40rTI
T4
I
NEXT CYCLE
Tl0RTI
I
"+,
.4f;.L./.;.L./.. .
STO-ST3 [
ADs
[
DDIN
[
HiE
[
__ (3)[
DBE
TL/EE/5054-24
Note:
(1) CPU samples Data Bus here.
(2) DBE and all other NS32201 TCU bus signals remain inactive because no
AD!! pulse is received from the CPU.
FIGURE 3-13. CPU Read from Slave Processor
2-387
Q
....
cD
....
Q
C"I
('I)
(/)
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~----------------------------------------------------------------------------,
3.0 Functional Description (Continued)
3.4.6.1 Slave Processor Bus Cycles
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3-13 and 3·14).
During a Read cycle SPC is active from the beginning of T1
to the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock period, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
sequence ("protocol") established by the instruction under
execution; but the CPU indicates the direction on the DDIN
pin for hardware debugging purposes.
3.4.6.2 Slave Operand Transfer Sequences
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (ADO-AD7), and a
Word operand is transferred on the entire bus. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-significant word to most-significant.
Since the CPU does not pulse the Address Strobe (ADS),
no bus signals are generated by the NS32201 Timing Con- .
trol Unit. The direction of a transfer is determined by the
PREVo CYCLE
I
PHil
[
sPC
[
ADO-AD15 [
T40RTi
I
Tl
T4
I
NEXT CYCLE
flORTi
I
.~'-"'-"'-"~ ~_-+___ ~_-+_
--:-I
810-813 [
ADS
[
[~""~~~__;-___~___+__(2)[
HiE
DBE
TL/EE/5054-25
Note:
(1) Slave Processor samples data bus here.
(2)
DBE. being provided by the NS32201 TeU. remains inactive due to the fact that no pulse is presented on ADS.
TCU signals RD. WR and 'FSO also remain inactive.
FIGURE 3·14. CPU Write to Slave Processor
2-388
z
~
N
3.0 Functional Description (Continued)
3.5 MEMORY MANAGEMENT OPTION
The NS32016 CPU, in conjunction with the NS32082 Memory Management Unit (MMU), provides full support for address translation, memory protection, and memory allocation techniques up to and including Virtual Memory.
described in Section 3.4. If it is sampled as low, two changes occur:
1)
2)
3.5.1 Address Translation Strap
PHil
[
PHI2
[
T40RTi
I
Tl
I
C)
C)
The NS32082 MMU will itself pull the CPU ATISPC pin low
when it is reset. In non-Memory-Managed systems this pin
should be pulled up to Vee through a 10 kO resistor.
Note that the Address Translation strap does not specifically declare the presence of an NS32082 MMU, but only the
The Bus Interface Control section of the NS32016 CPU has
two bus timing modes: With or Without Address Translation.
The mode of operation is selected by the CPU by sampling
the AT ISPC (Address TranslationlSlave Processor Control)
pin on the rising edge of the RST (Reset) pulse. If ATISPC
is sampled as high, the bus timing is as previously
I
An extra clock cycle, Tmmu, is inserted into all bus
cycles except Slave Processor transfers.
The OS/FLT pin changes in function from a Data
Strobe output (OS) to a Float Command input (FLT).
....en
•
....
llnmu
I
T4
T2
I
nORTi
I
AI6-A23 [
ADO-AD15 [
ADS
[
STO-ST3
[
ODIN
[
HBE
[
ROY
[
•
STATUS VALID
VALID
TL/EE/5054-26
FIGURE 3-15. Read Cycle with Address Translation (CPU Action)
2-389
.
o
.,...
CD
.,...
o
N
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(J)
Z
r-------------------------------------------------------------------------~
3.0 Functional Description (Continued)
presence of external address translation circuitry. MMU instructions will still trap as being undefined unless the
SETCFG (Set Configuration) instruction is executed to declare the MMU instruction set valid. See Section 2.1.3.
tion that the CPU Address lines A16-A23 remain in the
TRI-STATE condition. This allows the MMU to continue asserting the translated address on those pins.
Note that in order for the NS32082 MMU to operate correctly it must be set to the 32016 mode by forcing A24/HBF
high during reset.
Figures 3-17and 3-18 show a Read cycle and a Write cycle
as generated by the 32016/32082/32201 group. Note that
with the CPU ADS signal going only to the MMU, and with
the MMU PAV signal substituting for ADS everywhere else,
Tmmu through T4 look exactly like T1 through T4 in a nonMemory-Managed system. For the connection diagram, see
Appendix B.
3.5.2 Translated Bus Timing
Figures 3-15 and 3-16 illustrate the CPU activity during a
Read cycle and a Write cycle in Address Translation mode.
The additional T-State, Tmmu, is inserted between T1 and
T2. During this time the CPU places ADO-AD15 and A16A23 into the TRI-STATE® mode, allowing the MMU to assert the translated address and issue the physical address
strobe PAV. T2 through T4 of the cycle are identical to their
counter-parts without Address Translation, with the excep-
I
PHil
T40RTi
I
T1
T2
T3
T4
[
PHI2
A16-A23
[
ADO-ADIS
[
ADS
[
STO·STJ
[
ODIN
[
HBE
[
ROY
[
TL/EE/SOS4-27
FIGURE 3-16. Write Cycle with Address Translation (CPU Action)
2-390
z
3.0 Functional Description
en
Co)
(Continued)
I\)
....
....
Q
Q)
I
Q
NS32018 CPU BUS SIGNALS
I
T40RTi
I
T1
I
Tmmu
I
T2
T3
T4
I
Tl OR Ti
I
PHil [
PHI 2
[
A16·A23
[
ADIl-AD15
[
iiAV[
5TO·5T3 [
DIOiN
[~~~LL~~----+------+----~~------r------+~----+-
iiBE
[",,+~c.L.~~ \._-+__--+__-++-__+_J \.+__-+_
iffi[
DBE [
TLlEE/5054-2B
FIGURE 3-17. Memory-Managed Read Cycle
2-391
.....
....
Q
CD
3.0 Functional Description
(Continued)
Q
N
('I)
U)
I
Z
T4 OR Ti
I
NS320l8CPU BUS SIGNALS
Tl
I
Tmmu
I
T2
T3
T4
I
TlORTi
I
PHil [
PHI 2 [
A16·A23 [
ADO·AD15 [
AiiS[
PAV [
STO·ST3 [
NEXT STATUS
STATUS VALID
ODIN [
iiiiE[
VALID
ROY [
NS32201 TCU BUS SIGNALS
DBE [
TLIEEISOS4-29
FIGURE 3-18. Memory-Managed Write Cycle
2-392
~------------------------------------------------------------~Z
3.0 Functional Description
en
Co)
(Continued)
N
3.5.3 The FLT (Float) Pin
The FLT pin is used by the CPU for address translation
1)
Sets ADO-AD15, A16-A23 and DDIN to the TRISTATE condition ("floating").
support. Activating FLT during Tmmu causes the CPU to
wait longer than Tmmu for address translation and validation. This feature is used occasionally by the NS32082 MMU
in order to update its internal translation look.aside buffer
(TLB) from page tables in memory, or to update certain
status bits within them.
2)
3)
Sets HBE low.
Suspends further internal processing of the current instruction. This ensures that the current instruction remains abortable with retry. (See RST I ABT description,
Section 3.5.4.)
Note that the ADO-AD15 pins may be briefly asserted during the first idle T-State. The above conditions remain in
effect until FLT again goes high. See the Timing Specifications, Section 4.
Figure 3-19 shows the effects of FLT. Upon sampling FLT
low, late in Tmmu, the CPU enters idle T-States (Tt) during
which it:
TLlEE/5054-30
FIGURE 3-19. FLT Timing
2-393
o.....
.
en
.....
o
....o
rh
....
o('II
C")
en
z
r-----------------------------------------------------------------------------~
3.0 Functional Description
(Continued)
3.5.4 Aborting Bus Cycles
The RSTI ABT pin, apart from its Reset function (Section
3.3), also serves as the means to "abort," or cancel, a bus
cycle and the instruction, if any, which initiated it. An Abort
request is distinguished from a Reset in that the RSTI ABT
pin is held active for only one clock cycle.
2)
If FLT has been applied to the CPU, the Abort pulse
must be applied before the T-State in which FLT goes
ina,ctive. The CPU will not actually respond to the Abort
command until FLT is removed. See Figure 4-23.
3) The Write half of a Read-Modify-Write operand access
may not be aborted. The CPU guarantees that this will
never be necessary for Memory Management funtions
by applying a special RMW status (Status Code 1011)
during the Read half of the access. When the CPU
presents RMW status, that cycle must be aborted if it
would be illegal to write to any of the accessed addresses.
If ~I ABT is pulsed at any time other than as indicated
above, it will abort either the instruction currently under execution or the next instruction and will act as a very high-priority interrupt. However. the program that was running at the
time is not guaranteed recoverable.
If RST/ABT is pulled low during Tmmu or Tf, this signals
that the cycle must be aborted. The CPU itself will enter T2
and then Ti, thereby terminating the cycle. Since it is the
MMU PAY signal which triggers a physical cycle, the rest of
the system remains unaware that a cycle was started.
The NS32082 MMU will abort a bus cycle for either of two
reasons:
1)
The CPU is attempting to access a virtual address
which is not currently resident in physical memory. The
reference page must be brought into physical memory
from mass storage to make it accessible to the CPU.
2)
The CPU is attempting to perform an access which is
not allowed by the protection level aSSigned to that
page.
3.6 BUS ACCESS CONTROL
The NS32016 CPU has the capability of relinquishing its
access to the bus upon request from a DMA device or another CPU. This capability is implemented on the HOLD
(Hold Request) and HLDA (Hold Acknowledge) pins. By asserting HOLD low, an external device requests access to
the bus. On receipt of HLDA from the CPU, the device may
perform bus cycles, as the CPU at this point has set the
ADO-AD15, A16-A23, ADS, DDIN and HBE pins to the
TRI-STATE condition. To return control of the bus to the
CPU, the device sets HOLD inactive, and the CPU acknowledges return of the bus by setting HLDA inactive.
When a bus cycle is aborted by the MMU, the instruction
that caused it to occur is also aborted in such a manner that
it is guaranteed re-executable later. The information that is
changed irrecoverably by such a partly-executed instruction
does not affect its re-execution.
3.5.4.1 The Abort Interrupt
Upon aborting an instruction, the CPU immediately performs
an interrupt through the ABT vector in the Interrupt Table
(see Section 3.8). The Return Address pushed on the Interrupt Stack is the address of the aborted instruction, so that
a Return from Trap (RETT) instruction will automatically retry it.
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOI]) request is made,
as the CPU must always complete the current bus cycle.
Figure 3-20 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-21 shows the sequence
if the CPU is using the bus at the time that the HOLD request is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may already have
decided to initiate another bus cycle. In that case it will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally.
In a Memory-Managed system, the HLDA Signal is connected in a daisy-chain through the NS32082, so that the MMU
can release the bus if it is using it.
The one exception to this sequence occurs if the aborted
bus cycle was an instruction prefetch. If so, it is not yet
certain that the aborted prefetched code is to be executed.
Instead of causing an interrupt, the CPU only aborts the bus
cycle, and stops prefetching. If the information in the Instruction Queue runs out, meaning that the instruction will
actually be executed, the ABT interrupt will occur, in effect
aborting the instruction that was being fetched.
3.5.4.2 Hardware Considerations
In order to guarantee instruction retry, certain rules must be
followed in applying an Abort to the CPU. These rules are
followed by the NS32082 Memory Management Unit.
1)
If FLT has not been applied to the CPU, the Abort
pulse must occur during or before Tmmu. See the Timing Specifications, Figure 4-22.
2-394
r-----------------------------------------------------------------------,z
3.0 Functional Description
en
w
(Continued)
...~
...
Q)
I
C
I
Ti
I
Ti
I··· I
Ti
Ti
I
Ti OR T4
I
Ti OR T1
I
PHll[iLrLJ
PHI2 [
HoLD [
HLDA[
AFFECTED SIGNALS
-------
ADS [
os[
~}------
-------
----- 1r----- -----
oom[
----
i~----------
fII
HBE [
ADO-AD15 [
A 16-A23
-Li''-L..<'-L..<'-L..o''f'
['-'
•
....
Trap (SVC): The Supervisor Call (SVC) instruction was exea. Clear the Processor Status Register P bit.
o
cuted.
b.
Trap (DVZ): An attempt was made to divide an integer by
zero. (The SLAVE trap is used for Floating Point division by
zero.)
Otherwise, set "Return Address" to the address of the
next instruction.
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
2.
Trap (BPn: The Breakpoint (BPT) instruction was executed.
3.
Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I.
If the interrupt is Non-Maskable:
a.
Trap (TRC): The instruction just completed is being traced.
See below.
Trap (UNO): An undefined opcode was encountered by the
CPU.
Set "Return Address" to the address of the first
byte of the interrupted instruction.
Read a byte from address FFFF0016, applying
Status Code 0100 (Interrupt Acknowledge, Master: Section 3.4.2). Discard the byte read.
b.
Set "Vector" to 1.
c.
Go to Step B.
A special case is the Trace Trap (TRC), which is enabled by
setting the T bit in the Processor Status Register (PSR). At
the beginning of each instruction, the T bit is copied into the
PSR P (Trace "Pending") bit. If the P bit is set at the end of
an instruction, then the Trace Trap is activated. If any other
trap or interrupt request is made during a traced instruction,
its entire service procedure is allowed to complete before
the Trace Trap occurs. Each interrupt and trap sequence
handles the P bit for proper tracing, guaranteeing one and
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
5.
Here the interrupt is Vectored. Read "Byte" from address FFFE0016, applying Status Code 0100 (Interrupt
Acknowledge, Master: Section 3.4.2).
6.
If "Byte"
Step B.
3.8.6 Prioritization
7.
If "Byte" is in the range -16 through -1, then the
interrupt source is Cascaded. (More negative values
are reserved for future use.) Perform the following:
4.
The NS32016 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
If the interrupt is Non-Vectored:
a.
(Highest priority)
b.
Set "Vector" to O.
c.
Go to Step B.
4) Maskable Interrupts
5) Trace Trap
(Lowest priority)
0, then set "Vector" to "Byte" and go to
Read the 32-bit Cascade Address from memory.
The address is calculated as INTBASE + 4' Byte.
b.
Read "Vector," applying the Cascade Address
just read and Status Code 0101 (Interrupt Acknowledge, Cascaded: Section 3.4.2).
B.
Push the PSR copy (from Step 2) onto the Interrupt
Stack as a 16-bit value.
9.
Perform Service (Vector, Return Address), Figure 3-28.
3.8.7InterruptlTrap Sequences: Detail Flow
For purposes of the following detailed discussion of interrupt and trap service sequences, a single sequence called
"Service" is defined in Figure 3-28. Upon detecting any interrupt request or trap condition, the CPU first performs a
sequence dependent upon the type of interrupt or trap. This
sequence will include pushing the Processor Status Register and establishing a Vector and a Return Address. The
CPU then performs the Service sequence.
~
a.
2) Abort
3) Non-Maskable Interrupt
Read a byte from address FFFF0016, applying
Status Code 0100 (Interrupt Acknowledge, Master: Section 3.4.2). Discard the byte read.
Service (Vector, Return Address):
1)
Read the 32·bit External Procedure Descriptor from the Interrupt Dis·
patch Table: address is Vector'4+INTBASE Register contents.
2)
Move the Module field of the Descriptor into the MOD Register.
3)
Read the new Static Base pointer from the memory address contained
in MOD, placing it into the SB Register.
4)
Read the Program Base painter from memory address MOD + 8. and
add to it the Offset field from the Descriptor, placing the result in the
Program Counter.
For the sequenced followed in processing either Maskable
or Non-Maskable Interrupts (on the INT or NMI pins, respectively), see Section 3.B.7.1. For Abort interrupts, see Section
3.B.7.4. For the Trace Trap, see Section 3.B.7.3, and for all
other traps see Section 3.B.7.2.
5)
Flush Queue: Non·sequentially fetch first instruction of Interrupt Rou·
tine.
6)
Push MOD Register onto the Interrupt Stack as a 16·bit value. (The
PSR has already been pushed as a 16·blt value.)
3.8.7.1 Maskable/Non-Maskable Interrupt Sequence
7)
Push the Return Address onto the Interrupt Stack as a 32·bit quantity.
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, at the next interruptible point during its execution.
FIGURE 3·28. Service Sequence
Invoked during all interruptltrap sequences
2-403
fII
Q
....
....~
tia
C")
U)
z
r-----------------------------------------------------------------------------~
3.0 Functional Description (Continued)
3.8.7.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector" to the value corresponding to the trap
type.
Each Slave Instruction Set is validated by a bit in the Configuration Register (Section 2.1.3). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
SLAVE:
Vector = 3.
3.9.1 Slave Processor Protocol
ILL:
SVC:
Vector = 4.
Vector = 5.
DVZ:
FLG:
BPT:
Vector = 6.
Vector = 7.
Vector = 8.
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an 10 Byte followed by an Operation Word. The 10 Byte has three functions:
1)
2)
3)
It specifies which Slave Processor will execute it.
It determines the format of the following Operation
Word of the instruction.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Figure 3-29. While applying
Status Code 1111 (Broadcast 10, Section 3.4.2), the CPU
transfers the 10 Byte on the least-significant half of the Data
Bus (ADO-AD7). All Slave Processors input this byte and
decode it. The Slave Processor selected by the 10 Byte is
activated, and from this point the CPU is communicating
only with it. If any other slave protocol was in progress (e.g.,
an aborted Slave instruction), this transfer cancels it.
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Section 3.4.2).
Upon receilling it, the Slave Processor decodes it, and at
this pOint both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The Operation Word is swapped on the Data Bus; that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD7.
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
for memory accesses, these extensions are not sent to the
Slave Processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Section 3.4.2).
Status Combinations:
Send 10 (10): Code 1111
Xfer Operand (OP): Code 1101
Read Status (Sn: Code 1110
Step Status
Action
1
10 CPU Send 10 Byte.
2
OP CPU Sends Operation Word.
3
OP CPU Sends Required Operands.
Slave Starts Execution. CPU Pre-Fetches.
4
Slave Pulses SPC Low.
5
ST CPU Reads Status Word. (Trap? Alter Flags?)
6
7
OP CPU Reads Results (If Any).
Vector = 10.
Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, P and T.
UNO:
3)
4)
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
5)
Set "Return Address" to the address of the first byte of
the trapped instruction.
6)
Perform Service (Vector, Return Address), Figure 3-28.
3.8.7.3 Trace Trap Sequence
1) In the Processor Status Register (PSR), clear the P bit.
2) Copy the PSR into a temporary register, then clear
PSR bits S, U and T.
3)
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
4)
5)
Set "Vector" to 9.
Set "Return Address" to the address of the next instruction.
6)
Perform Service (Vector, Return Address), Figure 3-28.
3.8.7.4 Abort Sequence
1)
2)
Restore the currently selected Stack Pointer to its original contents at the beginning of the aborted instruction.
Clear the PSR P bit.
3)
Copy the PSR into a temporary register, then clear
PSR bits S, U, T and I.
4)
Push the PSR copy onto the Interrupt Stack as a 16-bit
value.
Set "Vector" to 2.
5)
6)
Set "Return Address" to the address of the first byte of
the aborted instruction.
7)
Perform Service (Vector, Return Address), Figure 3-28.
It identifies the instruction as being a Slave Processor
instruction.
3.9 SLAVE PROCESSOR INSTRUCTIONS
The NS32016 CPU recognizes three groups of instructions
as being executable by external Slave Processors:
Floating Point Instruction Set
Memory Management Instruction Set
Custom Instruction Set
FIGURE 3-29. Slave Processor Protocol
2-404
z
3.0 Functional Description
en
w
(Continued)
~
After the CPU has issued the last operand, the Slave Processor starts the actual execution 01 the instruction. Upon
completion, it will signal the CPU by pulsing SPC low. To
allow lor this, and lor the Address Translation strap function, AT/SPC is normally held high only by an internal pullup device 01 approximately 5 kn.
Custom Slave instruction (LCR: Load Custom Register). In
executing these instructions, the protocol ends after the
CPU has issued the last operand. The CPU does not wait lor
an acknowledgement Irom the Slave Processor, and it does
not read status.
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word lrom the Slave Processor, applying
Status Code 1110 (Read Slave Status, Section 3.4.2). This
word has the lormat shown in Figure 3-30. If the Q bit
("Quit", Bit 0) is set, this indicates that an error was detected by the Slave Processor. The CPU will not continue the
protocol, but will immediately trap through the Slave vector
in the Interrupt Table. Certain Slave Processor instructions
cause CPU PSR bits to be loaded Irom the Status Word.
The last step in the protocol is lor the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transler Slave Operand, Section 3.4.2).
An exception to the protocol above is the LMR (Load Memory Management Register) instruction, and a corresponding
Operand 1
Class
TABLE 3-4
Floating Point Instruction Protocols
Operand 1
Operand 2
Operand 2
Issued
Class
Issued
Returned Value
Type and Dest.
PSRBits
Affected
ftoOp.2
ftoOp.2
ItoOp.2
ItoOp.2
none
none
none
none
ItoOp.2
ItoOp.2
ItoOp.2
none
none
none
ADDI
SUBf
MUll
DIVf
read.1
read.!
read.!
read.f
rmw.I
rmw.1
rmw.I
rmw.!
MOVf
ABSf
NEGf
read.1
read.!
read.!
write.!
write.f
write.f
CMPI
read.!
read.!
f
N/A
N,Z,L
FLOORfi
TRUNCIi
ROUNDfi
read.1
read.1
read.!
write.i
write.i
write.i
I
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
none
nOl1e
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
N/A
N/A
Lto Op. 2
Fto Op. 2
none
none
MOVif
read.i
write.f
N/A
fto Op. 2
none
LFSR
SFSR
read.D
N/A
N/A
write.D
N/A
N/A
N/A
DtoOp.2
none
none
N/A
N/A
N/A
D
N/A
Note:
o = Double Word
i = integer size (B.W,D) specified in mnemonic.
f = Floating Point type (F,L) specified in mnemonic.
NtA
Q
Q
3.9.2 Floating Point Instructions
Table 3-4 gives the protocols loll owed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings 01 each instruction, see
Appendix A.
The Operand class columns give the Access Class lor each
general operand, delining how the addressing modes are
interpreted (see Series 32000 Instruction Set Relerence
Manual).
The Operand Issued columns show the sizes of the operands issued to the Floating Point Unit by the CPU. "D" indicates a 32-bit Double Word. "i" indicates that the instruction
specilies an integer size lor the operand (B = Byte,
W = Word, D = Double Word). "I" indicates that the instruction specilies a Floating Point size for the operand (F = 32bit Standard Floating, L=64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Allected column indicates which PSR bits, if any,
are updated Irom the Slave Processor Status Word (Figure
3-30).
While the Slave Processor is executing the instruction, the
CPU is Iree to preletch instructions into its queue. If it lills
the queue belore the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave, Section
3.4.2).
Mnemonic
....
en
....•
= Not Applicable 10 Ihis instruction.
2-405
PI
o r-----------------------------------------------------------------------------,
....
ch
3.0 Functional Description (Continued)
....
3.9.3 Memory Management Instructions
o
i3z
15
o
8 7
I 00000000 IN
Z F 0 0 L 0
New PSR Bll V.lue{,)~ . /
ooOuil": Terminal. Prolocol. 1I"ap(FPU~
Table 3-5 gives the protocols for Memory Management instructions. Encodings for these instructions may be found in
Appendix A.
In executing the RDVAL and WRVAL instructions, the CPU
calculates and issues the 32-bit Effective Address of the
single operand. The CPU then performs a single-byte Read
cycle from that address, allowing the MMU to safely abort
the instruction if the necessary information is not currently in
physical memory. Upon seeing the memory cycle complete,
the MMU continues the protocol, and returns the validation
result in the F bit of the Slave Status Word.
The size of a Memory Management operand is always a 32bit Double Word. For further details of the Memory Management Instruction set, see the Series 32000 Instruction Set
Reference Manual and the NS32082 MMU Data Sheet.
01
J
TLlEE/5054·41
FIGURE 3·30. Slave Processor Status Word Format
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
Mnemonic
RDVAL'
WRVAL'
LMR'
SMR'
Operand 1
Class
TABLE 3-5.
Memory Management Instruction Protocols
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
addr
addr
N/A
N/A
read.D
write. 0
N/A
N/A
0
0
0
N/A
Returned Value
Type and Oest.
PSRBlts
Affected
N/A
N/A
N/A
N/A
F
F
N/A
N/A
N/A
DtoOp.1
none
none
Note:
In the ROVAL and WRVAL instructions, the CPU Issues the address as a Double Word, and performs a single·byte Read cycle from that memory address. For
detailS, see the Series 32000 Instruction Set Reference Manual and the NS32082 Memory Management Un~ Data Sheet.
o = Double Word
• = Privileged Instruction: will trap if CPU Is in User Mode.
N/A = Not Applicable to this Instruction.
2-406
z
3.0 Functional Description
en
c.:I
(Continued)
3.9.4 Custom Slave Instructions
operand which can be a 32-bit ("D") or 64-bit ("a") quantity
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Any operand indicated as being of type 'c' will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
Provided in the NS32016 is the capability of communicating
with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
Table 3-6 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
Mnemonic
Operand 1
Class
For the instruction encodings, see Appendix A.
TABLE 3-6.
Custom Slave Instruction Protocols
Operand 2
Operand 2
Operand 1
Class
Issued
Issued
read.c
read.c
read.c
read.c
rmw.c
rmw.c
rmw.c
rmw.c
c
c
c
c
c
c
c
c
cto Op. 2
ctoOp.2
ctoOp.2
ctoOp.2
none
none
none
none
CMOVOc
CMOV1c
CMOV2c
CMOV3c
CCMPOc
CCMP1c
read.c
read.c
read.c
read.c
read.c
read.c
write.c
write.c
write.c
write.c
read.c
read.c
c
c
c
c
c
c
N/A
N/A
N/A
N/A
c
c
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
N/A
N/A
none
none
none
none
N,Z,L
N,Z,L
CCVOci
CCV1ci
CCV2ci
CCV3ic
read.c
read.c
read.c
readi
write.i
write.i
write.i
write.c
c
c
c
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
ctoOp.2
none
none
none
none
CCV4Da
CCV5aD
read.D
read.a
write.a
write.D
D
a
N/A
N/A
atoOp.2
DtoOp.2
none
none
LCSR
SCSR
read.D
N/A
N/A
write.D
D
N/A
N/A
N/A
N/A
DtoOp.2
none
none
LCR*
SCR*
addr
addr
N/A
N/A
D
D
N/A
N/A
N/A
N/A
F
F
read.D
write.D
N/A
N/A
D
N/A
N/A
N/A
N/A
D to Op.1
none
none
Note:
D
~
Double Word
= integer size (B,W,D) specified in mnemonic.
c
~
Custom size (D:32 bits or Q:64 bits) specified in mnemonic.
•
~
Privileged Instruction: will trap if CPU is in User Mode.
N/A
PSR Bits
Affected
CCALOc
CCAL1c
CCAL2c
CCAL3c
CATSTO'
CATST1*
i
Returned Value
Type and Dest.
~
Not Applicable to this instruction.
2-407
N
CI
....
....
~
CI
.,...
ch
.,...
Q
Q
r---------------------------------------------------------------------~
4.0 Device Specifications
C\I
4.1 PIN DESCRIPTIONS
Z
The following is a brief description of all NS32016 pins. The
descriptions reference portions of the Functional Description, Section 3.
~
Status (STO-ST3): Active high. Bus cycle status code, STO
least significant. Section 3.4.2. Encodings are:
0000 - Idle: CPU Inactive on Bus.
0001 0010 0011 -
4.1.1 Supplies
Power (Vee): + SV positive supply. Section 3.1
Logic Ground (GNDL): Ground reference for on-chip logic.
Section 3-1.
Idle: WAIT Instruction.
(Reserved)
Idle: Waiting for Slave.
0100 -Interrupt Acknowledge, Master.
0101 -Interrupt Acknowledge, Cascaded.
Buffer Ground (GNDB): Ground reference for on-chip drivers connected to output pins. Section 3.1.
Back-Bias Generator (BBG): Output of on-chip substrate
voltage generator. Section 3.1.
0110 -
End of Interrupt, Master.
0111 1000 -
End of Interrupt, Cascaded.
Sequential Instruction Fetch.
1001 -
Non-Sequential Instruction Fetch.
4.1.2 Input Signals
1010 1011 -
Data Transfer.
Read Read-Modify-Write Operand.
1100 1101 -
Read for Effective Address.
Transfer Slave Operand.
1110 -
Read Slave Status Word.
Clocks (PHI1, PHI2): Two-phase clocking signals. Section
3.2.
Ready (ROY): Active high. While ROY is inactive, the CPU
extends the current bus cycle to provide for a slower memory or peripheral reference. Upon detecting ROY active, the
CPU terminates the bus cycle. Section 3.4.1.
1111 - Broadcast Slave 10.
Hold Acknowledge (HLDA): Active low. Applied by the
CPU in response to HOLD input, indicating that the bus has
been released for DMA or multiprocessing purposes. Section 3.7.
User/Superior (U/S): User or Supervisor Mode status.
Section 3.7. High state indicates User Mode, low indicates
Supervisor Mode. Section 3.7.
Hold Request (HOLD): Active low. Causes the CPU to release the bus for DMA or multiprocessing purposes. Section
3.6.
Note: If the Fi()[ij signal is generated asynchronously, it's set up and hold
times may be violated.
In this case it is recommended to synchronize it with CTIL to mini·
mize the possibility of metastable states.
The CPU provides only one synchronization stage to minimize the
HLDA latency. This is to avoid speed degradations in cases of heavy
fiOITj activity (i.e. DMA controller cycles interleaved with CPU
cycles.)
Interlocked Operation (ILO): Active low. Indicates that an
interlocked instruction is being executed. Section 3.7.
Program Flow Status (PFS): Active low. Pulse indicates
beginning of an instruction execution. Section 3.7.
Interrupt (lNT): Active low, Maskable interrupt request.
Section 3.B.
4.1.4InputiOutput Signals
Non-Maskable Interrupt (NMI): Active low, Non-Maskable
interrupt request. Section 3.B.
Address/Data 0-15 (ADO-AD15): Multiplexed Address/
Data information. Bit 0 is the least significant bit of each.
Section 3.4.
Address
Translation/Slave
Processor
Control
(AT/SPC): Active low. Used by the CPU as the data strobe
output for Slave Processor transfers; used by Slave Processors to acknowledge completion of a slave instruction. Section 3.4.6. Section 3.9. Sampled on the rising edge of Reset
as Address Translation Strap. Section 3.S.1.
In Non-Memory-Managed systems this pin should be pulledup to Vee through a 10 kO resistor.
Reset/Abort (RST/ABT): Active low. If held active for one
clock cycle and released, this pin causes an Abort Command, Section 3.S.4. If held longer, it initiates a Reset, Section 3.3.
4.1.3 Output Signals
Address Bits 16-23 (A16-A23): These are the most significant B bits of the memory address bus. Section 3.4.
Address Strobe (ADS): Address low. Controls address
latches; indicates start of a bus cycle. Section 3.4.
Data Direction In (ODIN): Active low. Status Signal indicating direction of data transfer during a bus cycle. Section 3.4.
High Byte Enable (HBE): Active low. Status Signal enabling
transfer on the most significant byte of the Data Bus. Section 3.4; Section 3.4.3.
Note: The HBJ: Signal is normally floated when the CPU grants the bus in
Data Strobe/Float (DS/FLT): Active low. Data Strobe output, Section 3.4, or Float Command input, Section 3.S.3. Pin
function is selected on ATISPC pin, Section 3.5.1.
response to a DMA request on the ROil) pin.
However, when an MMU Is used and the bus Is granted during an
MMU page table look·up, HBE is not floated since the CPU does not
have sufficient information to synchronize the release of HBE to the
MMU's bus cycles.
Therefore, in a memory managed system, an exiernal TRI-STATE
buffer is required. This is shown in Figure B·l in Appendix B.
2-40B
z
en
4.0 Device Specifications (Continued)
Co)
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O°C to + 70"C
Storage Temperature
-65°C to + 150°C
All Input or Output Voltages With
-0.5Vto +7V
Respect to GND
1.5 Watt
Power Dissipation
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
....~
'P
....
o
4.3 ELECTRICAL CHARACTERISTICS TA = 0 to + 70°C, Vee = 5V ± 5%, GND = OV
Symbol
Max
Units
VIH
High Level Input Voltage
Parameter
2.0
Vee + 0.5
V
VIL
Low Level Input Voltage
-0.5
0.8
V
Conditions
Min
Typ
VeH
High Level Clock Voltage
PHI1, PHI2 pins only
Vee- 0.35
Vee+ 0.5
V
Vel
Low Level Clock Voltage
PHI1, PHI2 pins only
-0.5
0.3
V
VeLT
Low Level Clock Voltage,
Transient (ringing tolerance)
PHI1, PHI2 pins only
-0.5
0.6
V
VOH
High Level Output Voltage
VOL
Low Level 0 Output Voltage
IllS
AT/SPC Input Current (low)
VIN=O.4V, AT/SPC in input mode
II
Input Load Current
O:>:VIN:>:Vee, All inputs except
PHI1, PHI2, AT/SPC
Il
Leakage Current
Output and 110 Pins in
in TRI-STATElinput Mode
Icc
V
2.4
Active Supply Current
0.45
V
0.05
1.0
mA
-20
20
",A
-20
30
",A
300
mA
200
Connection Diagram
Dual·ln·Llne Package
A22!;;~::::::J
~
A20~
A19~
A21
2
3
4
47
46
45
:
::~~:
A16~
AD15 ~
ADI4!;;
AD13 ~
AD12 ~
ADll!;;
AD10
AD9!;;
AD8 ~
AD7 ~
E
AD6~
~
AD4 ~
ADS
AD3
E
AD2~
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NS32018
CPU
ADI C
22
ADO!;; 23
GNDL C
24
~
~
vcc
fII
A23
INT
NMI
::::::l
~~~
~ STI
::::::l ST2
42
41
40 ~ ST3
39 ~ PFS
38 ~ ODIN
37
AD~
36 ~ U/S
35
Ar/SPC
34
RST/ABT
33
Ds/FLT
32
HBE
31
HLDA
30
HOLD
29
BBG
28
RDV
27
PHIZ
26
PHil
25
GNDB
b;:;:!
g
g
g
g
g
g
g
g
g
g
P
Order Number NS32016D or NS32016N
See NS Package Number D48A or N48A
TL/EE/5054-2
Top View
FIGURE 4·1
2-409
....•
C)
....
~
en
CD
z
r-------------------------------------------------------------------------------------~
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
and PHI2 and O.SV or 2.0V on all other signals as iIIustrat-
ed in Figures 4-2 and 4-3, unless specifically stated otherwise.
ABBREVIATIONS:
L.E. - leading edge
T.E. - trailing edge
-[~'------
[ _ _k
[
PHI.
-IS-IG-1-1------.~~:
[ - - ........
SlG1
R.E. - rising edge
F.E. - falling edge
-------..--.-- -
SlG1
._~
[ ____I___I_SI_G_2h_lj
___
SlGZ
______
- - 2.4V
O.8V -',\Ir---..-j ISIG11
'---I--O.45V
~:
[
SIG2
TL/EE/5D54-42
FIGURE 4-2. Timing Specification Standard
(Signal Valid After Clock Edge)
~---t--2.4V
2.0V
L
ISIG2h
- - - - - - - ' - - - . - - - - - - -O.45V
TL/EE/5D54-43
FIGURE 4-3. Timing Specification Standard
(Signal Valid Before Clock Edge)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32016-10
Maximum times assume capacitive loading of 100 pF.
Name
Figure
Description
Reference/Conditions
NS32016-10
Min
Units
Max
tALv
4-4
Address bits 0-15 valid
after R.E., PHI1 T1
tALh
4-4
Address bits 0-15 hold
after R.E., PHI1 Tmmu or T2
tov
4-4
Data valid (write cycle)
after R.E., PHI1 T2
tOh
4-4
Data hold (write cycle)
after R.E., PHI1 next T1 or Ti
tAHv
4-4
Address bits 16-23 valid
after R.E., PHI1 T1
tAHh
4-4
Address bits 16-23 hold
after R.E., PHI1 next T1 or Ti
0
ns
tALAOSs
4-5
Address bits 0-15 setup
before ADS T.E.
25
ns
tAHAOSs
4-5
Address bits 16-23 set up
before ADS T.E.
25
ns
tALAOSh
4-9
Address bits 0-15 hold
after ADS T.E.
15
ns
tAHAOSh
4-9
Address bits 16-23 hold
after ADS T.E.
15
tALI
4-5
Address bits 0-15 floating
(noMMU)
after R.E., PHI1 T2
25
ns
tALMf
4-9
Address bits 0-15 floating
(withMMU)
after R.E., PHI1 Tmmu
25
ns
tAHMf
4-9
Address bits 16-23 floating
(withMMU)
after R.E., PHI1 Tmmu
25
ns
tHBEv
4-4
HBE Signal valid
after R.E., PHI1 T1
50
ns
tHBEh
4-4
HBE signal hold
after R.E., PHI1 next T1 or Ti
tsTv
4-4
Status (STO-ST3) valid
after R.E., PHI1 T4
(before T1, see note)
tSTh
4-4
Status (STO-ST3) hold
after R.E., PHI1 T4 (after T1)
tOOINv
4-5
DDIN signal valid
after R.E., PHI1 T1
2-410
40
5
ns
ns
50
0
ns
ns
40
ns
ns
0
ns
45
0
ns
ns
50
ns
z
U)
4.0 Device Specifications (Continued)
Co)
~
4.4.2.1 Output Signals: Internal Propagation Delays, NS32016-10 (Continued)
Name
Figure
Description
Reference/Conditions
NS32016-10
Min
Units
Max
tOOINh
4-5
ODIN signal hold
after R.E., PHil nextTl orTi
tAOSa
4-4
ADS signal active (low)
after R.E., PHil Tl
35
ns
tAOSia
4-4
ADS signal inactive
after R.E., PHI2 Tl
40
ns
tAOSw
4-4
ADS pulse width
at 0.8V (both edges)
tOSa
4-4
DS signal active (low)
after R.E., PHil T2
40
ns
tOSla
4-4
DS signal inactive
after R.E., PHil T4
40
ns
tALI
4-6
ADO-AD15 floating (caused by
HOLD)
after R.E., PHil T1
25
ns
tAH!
4-6
A16-A23 floating (caused by
HOLD)
after R.E., PHil T1
25
ns
tOS!
4-6
DS floating (caused by HOLD)
after R.E., PHil Ti
50
ns
tADS!
4-6
ADS floating (caused by HOLD)
after R.E., PHI1 Ti
50
ns
tHBE!
4-6
HBE floating (caused by HOLD)
after R.E., PHil Ti
50
ns
tODlN!
4-6
ODIN floating (caused by HOLD)
after R.E., PHI1 Ti
50
ns
tHLOAa
4-6
HLDA signal active (low)
after R.E., PHI1 Ti
30
ns
tHLOAia
4-8
HLDA signal inactive
after R.E., PHI1 Ti
40
ns
tOSr
4-8
OS signal returns from floating
(caused by HOLD)
after R.E., PHil Ti
55
ns
tAOSr
4-8
ADS signal returns from floating
(caused by HOLD)
after R.E., PHil Ti
55
ns
tHBEr
4-8
HBE signal returns from floating
(caused by HOLD)
after R.E., PHI1 Ti
55
ns
tOOINr
4-8
ODIN signal returns from floating
(caused by HOLD)
after R.E., PHI1 Ti
55
ns
tOOIN!
4-9
ODIN signal floating (caused by
FLn
after FLT FE
55
ns
tHBEI
4-9
HBE signal low (caused by FLn
after FLT F.E.
35
ns
tOOINr
4-10
ODIN signal returns from floating
(caused by FLn
after FLT F.E.
40
ns
tHBEr
4-10
HBE signal returns from LOW
(caused by FLn
after FLT F.E.
35
ns
tgPCa
4-13
SPC output active (low)
after R.E., PHil T1
35
ns
tgPCla
4-13
SPC output inactive
after R.E., PHil T4
35
ns
tgPCn!
4-15
SPC output nonforcing
after R.E., PHI2 T4
30
ns
tov
4-13
Data valid (slave processor write)
after R.E., PHI1 T1
50
ns
tOh
4-13
Data hold (slave processor write)
after R.E., PHI1 next T1 or Ti
0
ns
50
ns
tpFSw
4-18
PFS pulse width
at 0.8V (both edges)
ns
0
30
ns
tPFSa
4-18
PFS pulse active (low)
after R.E., PHI2
40
tPFSla
4-18
PFS pulse inactive
after R.E., PHI2
40
tlLOs
4-20a
ILO signal setup
before R.E., PHI1 T1 of first
interlocked write cycle
50
ns
tlLOh
4-20b
ILO signal hold
after R.E., PHI1 T3 of last
interlocked read cycle
10
ns
tlLOa
4-21
ILO signal active (low)
after R.E., PHI1
2-411
....
cp
....
o
o
35
ns
ns
ns
4.0 Device Specifications (Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32D16·1D (Continued)
Name
Figure
Description
NS32D16·1D
Reference/Conditions
Min
Units
Max
tllOia
4-21
ILO signal inactive
after R.E., PHI1
35
ns
tUSv
4-22
U/S signal valid
after R.E., PHI1 T4
35
ns
tUSh
4-22
U/S signal hold
after R.E., PHI1 T4
8
ns
tNSPF
4-19b
Nonsequential fetch to next PFS
clock cycle
after R.E .• PHI1 T1
4
tcp
tpFNS
4-19a
PFS clock cycle to next nonsequential fetch
before R.E., PHI1 T1
4
tcp
Last operand transfer of an instrucbefore R.E., PHI1 T1 of first
0
tcp
tion to next PFS clock cycle
bus cycle of transfer
Note: Every memory cycle starts w~h T4. during which Cycle Status is applied. If the CPU was Idling, the sequence will be: ". . . Ti, T4, Tl . . .". II the CPU was
not idling, the sequence will be: "... T4, T1 ...".
tLXPF
4-29
4.4.2.2 Input Signal Requirements: NS32016·10
Name
Figure
Description
Reference/Conditions
NS32D16·1D
Min
Units
Max
tPWR
4-25
Power stable to RST R.E.
after Vce reaches 4.5V
50
tDis
4-5
Data in setup (read cycle)
before F.E., PHI2 T3
15
ns
tDlh
4-5
Data in hold (read cycle)
after R.E., PHI1 T4
3
ns
tHlDa
4-6
HOLD active (low) setup time
(see note)
before F.E., PHI2 TX1
25
ns
tHlDia
4-8
HOLD inactive setup time
before F.E., PHI2 Ti
25
ns
tHlOh
4-6
HOLD hold time
after R.E., PHI1 TX2
0
ns
tFLTa
4-9
FLT active (low) setup time
before FE, PHI2 Tmmu
25
ns
tFLTia
4-11
FLT inactive setup time
before F.E., PHI2 T2
25
ns
ROY setup time
before FE, PHI2 T2 or T3
15
ns
ROY hold time
after FE, PHI1 T3
5
ns
/Ls
tROYs
4~11,
tROYh
4-11,4-12
tASTs
4-23
ABT setup time (FLT inactive)
before FE, PHI2 Tmmu
20
ns
tASTs
4-24
ABT setup time (FLT active)
before FE, PHI2 Tf
20
ns
tASTh
4-23
ABT hold time
after R.E., PHI1
0
ns
tRSTs
4-25,4-26
RST setup time
before F.E., PHI1
15
ns
tRSTw
4-26
RST pulse width
at 0.8V (both edges)
64
tcP
tiNTs
4-27
INTsetup time
before F.E., PHI1
25
ns
tNMlw
4-28
NMI pulse width
at 0.8V (both edges)
70
ns
tOls
4-14
Data setup (slave read cycle)
before FE, PHI2 T1
15
ns
tOlh
4-14
Data hold (slave read cycle)
after R.E., PHI1 T4
3
ns
tsped
4-15
SPC pulse delay from slave
after R.E., PHI2 T4
25
ns
tgpes
4-15
SPC setup time
before FE, PHI1
25
ns
tspew
4-15
SPC pulse width from slave
processor (async.input)
at 0.8V (both edges)
20
ns
4-12
2-412
z
en
w
4.0 Device Specifications (Continued)
Name
Figure
Description
!'.)
0)
Reference/Conditions
NS32016·10
Min
tATh
4·16
AT ISPC hold for address
translation strap
after F.E., PHI1 of cycle during
which RST pulse is removed
Units
Max
2
tcp
AT ISPC setup for address
before R.E., PHI1 of cycle during
1
tcp
translation strap
which RST pulse is removed
Note: This setup time is necessary to ensure prompt acknowledgement via HLOA and the ensuing floating of CPU off the buses. Note that the time from the receipt
of the HOLD Signal until the CPU floats is a function of the lime HOLD signal goes low, the state of the ROY input (in MMU systems), and the length of the current
MMU cycle.
tATs
4·16
4.2.3 Clocking Requirements: NS32016·10
Name
Figure
Description
....
...
Q
4.4.2.2 Input Signal Requirements: NS32016·10 (Continued)
Reference/
Conditions
NS32016·10
Units
Min
Max
100
250
ns
-2
5
ns
-4
4
ns
-5
5
ns
tcp
4·17
Clock period
R.E., PHI1, PHI2 to next
R.E., PHI1, PHI2
tCLw
4·17
PHI1, PHI2
pulse width
at 2.0V on PHI1, PHI2
(both edges)
0.5 tcp - 10 ns
tCLh
4·17
PHI1, PHI2 high time
at Vcc - 0.9Von
PHI1, PHI2 (both edges)
0.5 tcp - 15 ns
tCLI
4·17
PHI1, PHI210w time
atO.8Von
PHI1, PHI2
0.5tcp - 5 ns
tnOVL(1,2)
4·17
Non·overlap time
0.8Von F.E., PHI1, PHI2 to
0.8V on R.E., PHI2, PHI1
InOVLas
Non·overlap asymmetry
(tnOVL(1) - tnOVL(2»
At 0.8V on PHI1, PHI2
tcLwas
PHI1, PHI2 asymmetry
At 2.0V on PHI1, PHI2
(tCLw(1) - tcLw(2»
2·413
Q
-C)
r---------------------------------------------------------------------------------,
~
4.0 Device Specifications (Continued)
~
4.4.3 Timing Diagrams
CO)
U)
Z
TI
12
T3
T4
PHil [
PHI2 [
ADO-IS [
AI6-Z3 [
iiDiN[
S~[~_________r---~-A-L-IO--~----~~~~N-E-XT-----
os
[
-+--------{-jIOSI
~------t_--------n
(HIGH)
ROY [
I
TUEE/5054-44
FIGURE 4-4. Write Cycle
TI
12
T3
T4
PHil [
PHIZ [
ADO-IS [
"AI6-23 [
AiiS[
iiiE[
i5iiiN[
S~[
iii [
ROY [
TUEE/5054-45
FIGURE 4-5. Read Cycle
2-414
z
en
Co)
4.0 Device Specifications (Continued)
N
o
.....
en
.....
I
T4
TX2
TXI
Ti
Ti
TI
o
PHil [
PHI2 [ - 1 - -.....
HOLD [
HLDA [
_4-________-+________~r---_,~~t_--~~I'HLDA.
'DS,
IHBe!
os
lADS!
ADS
'ODIN!
: [ -+____-+____-+____-'__~
ADO·IS [
AI6-23
I
I
I
.
.
.
- -- -iFLOATINGj- - - -
~~'~~-l------L----_ _~~H~_lI
[-I-------l------I--__+__'
____
~]~:~
__ - -
(FLO~TING)
TL/EE/5lJS4-46
FIGURE 4·6. Floating by HOLD Timing (CPU Not Idle Initially)
Nole Ihal whenever Ihe CPU is nol idling (nol in Ti), Ihe HOLD request (HOLD low) must be active tHLOa before the falling edge of PHI2 of the clock cycle that
appears two clock cycles before T4 (TXl) and stay low until tHLOh after the rising edge of PHil of Ihe clock cycle that precedes T4 (TX2) for the request to be
acknowledged.
Ti
PHil [
T4
TI
Ti
PHil [
PHI2 [
PHI2 [
HOLD [
Hi:iiA[ -+---4~~
OS
ADS [
HBE
D IN
AD OD" S
ii6Cii[
HLiiA [ + ________+~
I
[-1------
os
-I----------I-.J1
(FL.OAilNCii -,R.OATING)- -------
A16.23 [ -
- - - - - -
tHBEr
tDDINr
ADS [
HBE
DDIN
AI6-23
to",
lADSr
-
(HIGH)
(FLOATING)
[_1_______1____________ _
ADD·15
(FLOATING)
(FLOATING)
TLlEE/SOS4-46
TLlEE/SOS4-47
FIGURE 4·8. Release from HOLD
FIGURE 4·7. Floating by HOLD Timing (CPU Initially Idle)
Nole thai during Til the CPU is already idling.
2-415
•
....
Q
cb
....
4.0 Device Specifications (Continued)
Q
N
('I)
(/)
Z
CPU STATES
T1
TIIMU
TI
TI
MMUSTATES
T1
TIIMU
T4
Tl
PHil [
PHI2 [
m[
ADO-IS [
(CPU)
AI8-23 [
(CPU)
ADS [
(CPU)
iiiiiN[
(CPU)
HBE [
TLlEE/5054-49
FIGURE 4·9. FLT Initiated Cycle Timing
CPU STATES
Tt
MMU STATES
Tmmu
T2
T3
T4
PHil [
PHI2[
FiT [
(MMU)
ADO-15 [
AI6-23
-
ffi5iN
(CPU) [ __
ADS [
(CPU)
-+----+----+-----
HBE [ ____- -.....
Tl/EE/5054-50
Note that when FIT is dea..erted the CPU restarts driving ODIN betore the MMU releases it. This, however, does not cause any conflict, since both CPU and MMU
torce ODIN to the same logic level.
FIGURE 4·10. Release from FLT Timing
TL/EE/5054-51
FIGURE 4·11. Ready Sampling (CPU Initially READY)
2-416
z
en
Co)
4.0 Device Specifications (Continued)
....
...
o
N
o
Q)
\
13\\13\
T4
:~~
~
RDV[
TL/EE/SOS4-S2
FIGURE 4-12. Ready Sampling (CPU Initially NOT READY)
I
I
T1
TO
I
I
PHI'[~
PHI2 [
T1
I
T4
I
PHI'[JLJLJ
I
ADO-.5 [
spc[
SPC [
(CPU)
DaN[-+~____~r-______+-
iiiiiN[
STQ.3[
STIH
AiiS[
[-4----1-""---....-
AiiS[
(HIGH)
I
TLlEE/SOS4-S4
TLlEE/S054-53
FIGURE 4-14. Slave Processor Read Timing
FIGURE 4-13. Slave Processor Write Timing
11
T4
PH)I [
PHI2 [
SPC [
(FROM CPU)
(FROM
Sl.A~1
[. --- ------ ------- -----TL/EE/SOS4-82
FIGURE 4·15. SPC Timing
After transferring last operand to a Slave Processor. CPU turns
OFF driver and holds SPC high with internal 5 kO pullup.
TLlEE/SOS4-S6
FIGURE 4·16. Reset Configuration Timing
2-417
....o
*'o
4.0 Device Specifications (Continued)
C\I
C")
(/)
z
PHil [
PHI2 [
-----~I
TL/EE/5054-57
FIGURE 4-17. Clock Waveforms
PHI2
[~f1---JLJ
m[~~
TL/EE/5054-58
FIGURE 4-18. Relationship of PFS to Clock Cycles
11
IpFNS
.1
STQ.3 [ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....JX'--_C_O_DE_l_00_'_ _
TUEE/5054-59
FIGURE 4-19a. Guaranteed Delay, PFS to Non-Sequential Fetch
I
PHil
11
I
12
I ••• I
I
I
I
LfU"LJl-1fl--fl--JL
ADS [
S1Q.3[-+_ _ _ _
CO_D_E_l_00_l_ _ _
~.r-----r-------
INSPF
TLlEE/5054-60
FIGURE 4-19b. Guaranteed Delay, Non-Sequential Fetch to PFS
2·418
z
en
Co)
4.0 Device Specifications (Continued)
I
T30RTI
I
T40RTI
I
N
CI
T1
T2
T3
.....
'l»
.....
CI
T4
iiiS[
TLlEE/5054-61
FIGURE 4-20a. Relationship of ILO to First Operand Cycle
of an Interlocked Instruction
I
TJORTI
I
T4 OR TI
I
Tl
T2
T3
T4
-+____________-+,
ILO[ ______________
TLlEE/5054-62
FIGURE 4-20b. Relationship of ILO to Last Operand Cycle
of an Interlocked Instruction
PHI1[JLJLt
fII
~[~Ir----~u.
TLlEE/5054-63
FIGURE 4-21. Relationship of ILO to Any Clock Cycle
I
TJORTI
I
T40RTI
I
T1
T2
T3
T4
TL/EE/5054-64
FIGURE 4-22. U/S Relationship to Any Bus CycleGuaranteed Valid Interval
2-419
....
J,
....
C) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
re
4.0 Device Specifications (Continued)
C")
I
rn
z
T1
I
Trnmu
12
TI
PHIZ [
TLlEE/S054-6S
FIGURE 4-23. Abort Timing, FLT Not Applied
Tf
Tf
TI
TI
12
TI
PHil [
PHI2 [
~Ri[ __r_----_+------~----~+_-J
TL/EE/SOS4-66
FIGURE 4-24. Abort Timing, FLT Applied
~---------------~~
vee
PHil
[----1----.. .
~/AErr[
______________ilr_J
TL/EE/5054-67
FIGURE 4-25. Power-On Reset
TLlEE/5054-68
FIGURE 4-26. Non-Power-On Reset
2-420
zen
4.0 Device Specifications (Continued)
Co)
~
o
......
cp
......
o
NM{
PHI1[..nJLIL
(.J
iNT[
liNTs
~_INMIw_'r
~
TL/EE/SOS4-70
FIGURE 4-28. NMllnterrupt Signal Timing
TL/EE/SOS4-69
FIGURE 4-27.INT Interrupt Signal Detection
FIRST BUS CYCLE
NEXT
TL/EE/SOS4-71
FIGURE 4-29. Relationship Between Last Data Transfer of
an Instruction and PFS Pulse of Next Instruction
NOTE:
In a Iransfer of a Read.Modify.Write type operand. this is the Read transfer,
displaying RMW Slatus (Code 1011).
2-421
fII
....
Q
ch
....
~
Cf)
tn
Z
.--------------------------------------------------------------------,
Options: in String Instrucrt_io_n_s_,-_,--,
Appendix A: Instruction Formats
I U/W
NOTATIONS:
i = Integer Type Field
B = 00 (Byte)
W = 01 (Word)
o = 11 (Double Word)
f = Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L= 0 (Long Floating: 64 bits)
c = Custom Type Field
o = 1 (Double Word)
Q = 0 (Quad Word)
op = Operation Code
Valid encodings shown with each format.
gen, gen 1, gen 2 = General Addressing Mode Field
See Sec. 2.2 for encodings.
reg = General Purpose Register Number
cond = Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110 = Greater Than: N = 1
0111 = Less or Equal: N = 0
1000 = Flag Set: F = 1
1001 = Flag Clear: F = 0
1010 = LOwer: L = 0 and Z = 0
1011 = Higher or Same: L = 1 orZ = 1
1100 = Less Than: N = 0 and Z = 0
1101 = Greater or Equal: N = 1 or Z = 1
1110 = (Unconditionally True)
1111 = (Unconditionally False)
short = Short Immediate Value. May contain:
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ, ACB.
cond: Condition Code (above), in Scond.
areg: CPU Dedicated Register, in LPR, SPR.
0000 = US
0001 - 0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = (Reserved)
1100 = (Reserved)
1101 = PSR
1110 = INTBASE
1111 = MOD
B
T
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
Configuration bits, in SETCFG:
IC IM IF
mreg:
NS32082 Register number, in LMR, SMR.
0000 = BPRO
0001 = BPR1
0010 = (Reserved)
0011 = (Reserved)
0100 = (Reserved)
0101 = (Reserved)
0110 = (Reserved)
0111 = (Reserved)
1000 = (Reserved)
1001 = (Reserved)
1010 = MSR
1011 = BCNT
1100 = PTBO
1101 = PTB1
1110 = (Reserved)
1111 = EIA
7
I
I
I
0
I
1
cond
11 10 1 101
op
1 1
10 0 1 101
FormatO
(BR)
Bcond
7
I
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
Format 1
-0000
ENTER
-0001
EXIT
Nap
-0010
-0011
WAIT
-0100
DIA
-0101
FLAG
-0110
SVC
-0111
BPT
81 7
15
I
gen
0
I
sh~rt
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
0
I
op
11
I
1
I I
Format 2
ADDQ
CMPQ
SPR
Scond
2-422
-000
-001
-010
-011
ACB
MOVQ
LPR
-100
-101
-110
,--------------------------------------------------------------------------, z
en
Co)
Appendix A: Instruction Formats (Continued)
1S
~e~
,
I'
017
o'p
~
o7
0
I
11'1'1'1'11
-0000
-0010
-0100
-0110
o
.....
.....
Q)
I
i
Format 3
CXPD
BICPSR
JUMP
BISPSR
0
1 1 00111 0
o
Format 7
-1010
-1100
-1110
ADJSP
JSR
CASE
Trap (UND) on XXX1, 1000
I' , , , I"
gen 1
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
DIV
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
o
gen 2
'I
iii
op
Format 4
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
SUB
ADDR
AND
SUBC
TBIT
XOR
-1000
-1001
-1010
-1100
-1101
-1110
0
i
00001 1 1 0
TLlEE/5054-72
FormatO
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
-000
INDEX
-001
FFS
-010
-011
-110,reg=001
-110, reg=011
-100
-101
o
FormatS
-0000
MOVS
CMPS
-0001
Trap (UND) on 1XXX, 01XX
SETCFG
SKPS
1 1 1 1 0
-0010
-0011
o
MOVif
LFSR
MOVLF
MOVFL
Format 9
-000
ROUND
-001
TRUNC
-010
SFSR
-011
FLOOR
-100
-101
-110
-111
001110
7
Format 6
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
NEG
NOT
Trap (UND)
SUBP
ABS
COM
IBIT
ADDP
0
] 0 1 1 1 1 1101
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
2-423
TLlEE/5054-37
Format 10
Trap (UND) Always
fII
o .----------------------------------------------------------------------,
,...
ch
,...
Appendix A: Instruction Formats (Continued)
o
N
(W)
o
tn
Z
1 1 1 1 0
ID Byte
Operation Word
Format 11
ADDf
MOVf
CMPf
Trap (SLAVE)
SUBt
NEGf
Trap (UND)
Trap (UND)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
DIVf
Trap (SLAVE)
Trap (UND)
Trap (UND)
MULf
ABSf
Trap (UND)
Trap (UND)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
7
I I I I I I I
nnn
Operation Word Format
000
Format 15.0
-0000
LCR
CATSTO
-0001
SeR
CATST1
Trap (UND) on all others
0
1
l 1 1 1 1 1 1 O.
___.1
on
Format 15
(Custom Slave)
TL/EE/5054-75
-0010
-0011
Format 12
Trap (UND) Always
001
on
l
0
I I I I I I I
I
___ . 1 0 0 1 1 1 1 O.
Format 15.1
TLlEE/5054-76
CCV3
LCSR
CCV5
CCV4
Format 13
Trap (UND) Always
-000
-001
-010
-011
CCV2
CCV1
SCSR
CCVO
-100
-101
-110
-111
0
1 1 1 1 0
101
Format 14
RDVAL
WRVAL
-0000
-0001
LMR
SMR
Format 15.5
-0010
-0011
Trap (UND) on 01 XX, 1XXX
CCALO
CMOVO
CCMPO
CCMP1
CCAl1
CMOV2
Trap (UND)
Trap (UND)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
If nnn ~ 010,011,100,110,111
then Trap (UNO) Always
2-424
CCAL3
CMOV3
Trap (UND)
Trap (UND)
CCAL2
CMOV1
Trap (UND)
Trap (UND)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
z
(J)
W
Appendix A: Instruction Formats (Continued)
N
o......
.
01
......
o
---I
I I I I I I I
___ 0 1 0 1 1 1 1 0
1
7
0
---I xI xI x "0
___
TL/EE/5054-77
0 I 1 "1
0
1
TL/EE/5054-BO
Format 16
Trap (UNO) Always
Format 19
Trap (UNO) Always
7
Implied Immediate Encodings:
7
0
o
---I
I I I I I I I 1
___ 1 1 0 1 1 ·1 1 0
r1
TL/EE/5054-7B
Register Mask, appended to SAVE, ENTER
Format 17
Trap (UNO) Always
o
7
ro
---I
7
__ . 1 0 0 0 1 1 1 0
r2
r3
r4
r5
rS
Register Mask, appended to RESTORE, EXIT
0
I I I I I I I
r1
1
TL/EE/5054-79
o
7
Format 18
: offset:
Trap (UNO) Always
Offset/Length Modifier appended to INSS, EXTS
2-425
NS32016-10
-ff
T
XCTAL2
PER
PERIPH. CYCLE
READY
XCTAL1
EWAi'f
WAffii
NS32201
WAiT4
TCU
RESET
WAffi
WAffi
RSTI
PHil
iiii
PHI2
WR
-}
;=
-
::::I
a.
WAIT REOUESTS
(ADDR. DECODED OR STRAPPED)
>C"
Rii
CTTL
~
::::I
CD
WR
ADS
RS'fO
l>
"CI
"CI
CD
illiiN ROY ffiiE
;.
iLO
()
HBE
""
I
~
ROY PHil PHI2
HLDAO
CD
INTS{=:
iN'f
NMi
HLDAI
DS/FLT
PFS
FIT
UlS
UlS
ADS
ADS
ODIN
ODIN
NS32018
CPU
AT/SPC
10 kD
(24)
NS32082
MMU
I- t--
iiSf/ABT
I-
SPC
f----
(24)
A24
fD
II
to
ADDRESS
BUS
(24)
'ODIN
(24)
(24)
ADDR/DATA
MULTIPLEXED
BUS
ADDRESS
LATCH!
BUFFER
+5
ADDR!DATA
+5
(24)i
0"
::::I
STROBE
PAY
STO-ST3
STO-ST3
RST/ABT
ADDR/DATA
HLDAO
PFs
!1.
I
PHI2
~
Sl
C
eQ
eQ
HOLD ROY RSTI
PHil
HLDA
(/)
HOLD
l
1
ILO HBE HOLD
S"
eQ
(16,
DATA
(16t
SPC ~
STO-STl
NS32081
FPU
RST
CLK
II
I
EN
DATA
-----
iiS'f
CLK
MULTIPLEXED
BUS
MEMORY!
PERIPHERALS
(16)
DIR
~
DATA BUS
(16)
DATA BUFFERS
STATUS
TUEE/5054-73
FIGURE B-1. System Connection Diagram
~National
~ Semiconductor
NS32008-10 High-Performance 8-Bit Microprocessor
General Description
Features
The NS3200B is a 32-bit microprocessor with a 16-MByte
linear address space and a B-bit external data bus. It has a
32-bit ALU, eight 32-bit general purpose registers, a fourbyte prefetch queue, and a slave processor interface. The
NS3200B is fabricated with National Semiconductor's advanced XMOSTM process, and is fully object code compatible with other Series 32000@ processors. The Series 32000
instructions set is optimized for modular high-level languages (HLL). The set is very symmetric, it has a two address format, and it incorporates HLL oriented addressing
modes. The capabilities of the NS3200B can be expanded
with the use of the NS320B1 floating point unit (FPU), which
interfaces to the NS3200B as a slave processor. The
NS3200B is a general purpose microprocessor that is ideal
for a wide range of computational intensive applications.
•
•
•
•
32-bit architecture and implementation
16-MByte linear address space
B-bit external data bus
Powerful instruction set
- General 2-address capability
- High degree of symmetry
- Addressing modes optimized for high-level
languages
• Series 32000 slave processor support
• High-speed XMOS technology
• 4B-pin dual-in-line (DIP) package
Block Diagram
ADD/DATA
CONTROLS. STATUS
MICROCODE ROM
AND
CONTROL LOGIC
•
a:o
CFG REGISTER
INTBASE
S8
FP
WORKING
REGISTERS
SP1
o
SPO
PC
RO
R1
R2
R3
R4
R5
I
I
I
R6
I
R7
I
MOD
I
PSR
:
L_________________
2-427
J
TL/EE/6156-1
Table of Contents
1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
1.1 NS32008 Design Goals
3.7.3 Maskable Interrupts (The INT Plan)
3.7.3.1 Non-Vectored Mode
2.0 ARCHITECTURAL DESCRIPTION
3.7.3.2 Vectored Mode: Non-Cascaded Case
2.1 Programming Model
3.7.3.3 Vectored Mode: Cascaded Case
2.1.1 General Purpose Registers
3.7.4 Non-Maskable Interrupt (The NMI Pin)
2.1.2 Dedicated Registers
3.7.5 Traps
2.1.3 The Configuration Register (CFG)
3.7.6 Prioritization
2.1.4 Memory Organization
3.7.7InterruptlTrap Sequences: Detail Flow
2.1.5 Dedicated Tables
3.7.7.1 Maskable/Non-Maskable Interrupt
Sequence
2.2 Instruction Set
2.2.1 General Instruction Format
3.7.7.2 Trap Sequences: Traps Other Than
Trace
2.2.2 Addressing Modes
2.2.3 Instruction Set Summary
3.8 Slave Processor Instructions
3.0 FUNCTIONAL DESCRIPTION
3.8.1 Slave Processor Protocol
3.1 Power and Grounding
3.8.2 Floating Point Instructions
3.8.3 Custom Slave Instructions
3.2 Clocking
3.3 Resetting
4.0 DEVICE SPECIFICATIONS
3.4 Bus Cycles
4.1 Pin Descriptions
3.4.1 Cycle Extension
4.1.1 Supplies
3.4.2 Bus Status
4.1.2 Input Signals
3.4.3 Data Access Sequences
4.1.3 Output Signals
3.4.3.1 Bit Accesses
4.1.4 InputlOutput Signals
3.4.3.2 Bit Field Accesses
4.2 Absolute Maximum Ratings
3.4.3.3 Extending Multiply Accesses
4.3 Electrical Characteristics
3.4.4 Instruction Fetches
4.4 Switching Characteristics
3.4.5 Interrupt Control Cycles
4.4.1 Definitions
3.4.6 Slave Processor Communication
4.4.2 Timing Tables
3.4.6.1 Slave Processor Bus Cycles
4.4.2.1 Output Signals: Internal Propagation
Delays
3.4.6.2 Slave Operand Transfer Sequences
3.5 Bus Access Control
4.4.2.2 Input Signals Requirements
3.6 Instruction Status
4.4.2.3 Clocking Requirements
3.7 NS32008 Interrupt Structure
4.4.3 Timing Requirements
3.7.1 General InterruptlTrap Sequence
Appendix A: Instruction Formats
3.7.2 InterruptlTrap Return
List of Illustrations
The General and Dedicated Registers ..•....•............••.............•............•............•.............. 2-1
Processor Status Register .................•......•............................................•......••.....•...2-2
CFG Register ..•••....•...................•............•......•............•...................................2-3
Data Formats for NS32008 Memory .••...•.......••..•..•......•....••.........................•....•............2-4
Module Descriptor Format. ......................................................................................2-5
A Sample Link Table ...........................................................................................2-6
General Instruction Format .....................•.........................................•...................... 2-7
Index Byte Format .............................................................................................2-8
Displacement Encodings .........................•........................•.......•......•...................•.. 2-9
Recommended Supply Connections ..............................................................................3-1
Clock Timing Relationships ....•.................................................................................3-2
Power-on Reset Requirements ................••.........................•................•......................3-3
General Reset Timing ..........................................................................................3-4
Recommended Reset Connections .......................•....................................................... 3-5
2-428
z
List of Illustrations (Continued)
en
w
Bus Connections ...........••..............................................................................•...3-6
c
c
Read Cycle Timing .............................................................................................3-7
Write Cycle Timing .............................................................................................3-8
I\)
CD
•
......
c
ROY Pin Timing ..•......•......................................................................................3-9
Extended Cycle Example ......................................................................................3-1 0
Slave Processor Connections ....................•..................................•.......................... 3-11
CPU Read from Slave Processor ................................................................................ 3-12
CPU Write to Slave Processor ...........•...................................................................... 3-13
HOLD Timing, Bus Initially Idle .................................................................................. 3-14
HOLD Timing, Bus Initially Not Idle .............................................................................. 3-15
Interrupt Dispatch and Cascade Tables .......................................................................... 3-16
Interrupt/Trap Service Routine Calling Sequence ..................................................•.............. 3-17
Return from Trap (RETT n) Instruction Flow ...................................................................... 3-18
Return from Interrupt(RET) Instruction Flow ...................................................................... 3-19
Interrupt Control Connections (16 levels) .........................................................................3-20
Cascaded Interrupt Control Unit Connections .....................................................................3-21
Service Sequence ............................................................................................3-22
Slave Processor Protocol ......................................................................................3-23
Slave Processor Status Word Format. ...........................................................................3-24
Connection Diagram ............................................................................................4-1
Timing Specification Standard (Signal Valid After Clock Edge) ....................................................... .4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
Write Cycle ....................................................................................................4-4
Read Cycle ....................................................................................................4-5
Floating by HOLD Timing (CPU Notldle Initially) ................................................................... .4-6
Floating by HOLD Timing (CPU Initially Idle) ....................................................................... 4-7
Release from HOLD ............................................................................................4-8
Ready Sampling (CPU Initially READY) ........................................................................... .4-9
Ready Sampling (CPU Initially NOT READY) ......................................................................4-10
Slave Processor Write Timing ...................................................................................4-11
Slave Processor Read Timing ................................................................................. .4-12
SPCTiming ..................................................................................................4-13
Clock Waveforms .............................................................................................4-14
Relationship of PFS to Clock Cycles .............................................................................4-14
Guaranteed Delay, PFS to Non-Sequential Fetch ................................................................ 4-15a
Guaranteed Delay, Non-Sequential Fetch to PFS ................................................................ 4-15b
Relationship of ILO to First Operand of an Interlocked Instruction ................................................... .4-17
Relationship of ILO to Last Operand of an Interlocked Instruction .................................................... 4-18
Relationship of ILO to Any Clock Cycle .......................................................................... 4-19
TIls Relationship to any Bus Cycle - Guaranteed Valid Interval ...................................................... 4-20
Power-On Reset ..............................................................................................4-21
Non-Power-On Reset ..........................................................................................4-22
INT Interrupt Signal Detection ................................................................................. .4-23
NMllnterrupt Signal Timing ..................................................................................... 4-24
Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction ........................... 4-25
List of Tables
NS32008 Addressing Modes .................................................................................... 2-1
NS32008 Instruction Set Summary ............................................................................... 2-2
Interrupt Sequences ............................................................................................3-1
Floating-Point Instruction Protocols ............................................................................... 3-2
Custom Slave Instruction Protocols ............................................................................... 3-3
2-429
fII
....• r---------------------------------------------------------------------------------,
C)
CIO
C)
C)
C'II
C")
en
z
1.0 Product Introduction
The Series 32000 Microprocessor family is a new generation of devices using National's XMaS and CMOS technologies. By combining state-of-the-art MaS technology with a
very advanced architectural design philosophy, this family
brings mainframe computer processing power to VLSI processors.
cess, which allows a significant reduction in hardware and
software cost.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by speCial slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
phYSically integrated on the CPU chip itself.
The Series 32000 family supports a variety of system configurations, extending from a minimum low-cost system to a
powerful 4 gigabyte system. The architecture provides complete upward compatibility from one family member to another. The family consists of a selection of CPUs supported
by a set of peripherals and slave processors that provide
sophisticated interrupt and memory management facilities
as well as high-speed floating-point operations. The architectural features of the Series 32000 family are described
briefly below:
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
• High-Level Language Support
• Easy Future Growth Path
• Application Flexibility
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword, and BCD, which may
be arranged into a wide variety of data structures.
SymmetriC Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
1.1 NS32008 DESIGN GOALS
The NS3200B is aimed at small to medium size systems,
and is designed to bridge the gap between B-bit CPUs and
the higher-end members of the Series 32000 family. The
NS3200B provides an B-bit data bus and is the only CPU in
the Series 32000 family that does not support virtual memory.
The NS3200B is most suitable for systems designed with
B-bit memory and peripherals.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided. This powerful memory-to-memory architecture permits memory locations to be treated as registers
for all useful operations. This is important for temporary operands as well as for context switching.
Memory Management. Either the NS323B2 or the
NS320B2 Memory Management Unit may be added to the
system to provide advanced operating system support functions, including dynamic address translation, virtual memory
management, and memory protection.
Large, Uniform Addressing. The NS3200B has 24-bit address pOinters that can address up to 16 megabytes without
requiring any segmentation; this addreSSing scheme provides flexible memory management without added-on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addreSSing. In
addition, ROM code is totally relocatable and easy to ac-
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes 16 registers on the
NS3200B CPU.
2.1.1 General Purpose Registers
There are eight registers for meeting high-speed general
storage requirements, such as holding temporary variables
and addresses. The general purpose registers are free for
any use by the programmer. They are 32 bits in length. If a
general register is specified for an operand that is B or 16
bits long, only the low part of the register is used; the high
part is not referenced or modified.
2.1.2 Dedicated Registers
The eight dedicated registers of the NS3200B are assigned
specific functions:
PC: The PROGRAM COUNTER register is a pointer to the
first byte of the instruction currently being executed. The PC
GENERAL
DEDICATED
•
•
~
3'
3'
~
RO
PROGRAM COUNTER
PC
STATIC BASE
sa
FRAME POINTER
FP
USER STACK PTA.
SP1
INTERRUPT STACK PTR.
INTERRUPT BASE
SPO
R1
R'
R3
I
SP
INTBASE
R'
RS
PSR
MOD
R6
STATUS
MODULE
R7
TL/EE/6156-3
FIGURE 2-1. he General and Dedicated Registers
2-430
.--------------------------------------------------------------------------, z
2.0 Architectural Description
en
w
(Continued)
N
is used to reference memory in the program section. (In the
NS32008, the upper eight bits of this register are always
zero.)
SPO, SP1: The SPO register pOints to the lowest address of
the last item stored on the INTERRUPT STACK. This stack
is normally used only by the operating system. It is used
primarily for storing temporary data, and holding return information for operating system subroutines and interrupt and
trap service routines. The SP1 register pOints to the lowest
address of the last item stored on the USER STACK. This
stack is used by normal user programs to hold temporary
data and subroutine return information.
In this document, reference is made to the SP register. The
terms "SP register" or "SP" refer to either SPO or SP1,
depending on the setting of the S bit in the PSR register. If
the S bit in the PSR is 0, then SP refers to SPO. If the S bit in
the PSR is 1, the SP refers to SP1. (In the NS32008, the
upper eight bits of these registers are always zero.)
Stacks in the Series 32000 family grow downward in memory. A push operation pre-decrements the stack pOinter by
the operand length. A pop operation post-increments the
stack pOinter by the operand length.
T: The T bit causes program traCing. If this bit is a 1, a TRC
trap is executed after every instruction (Section 3.7.5).
o
oCC)
L: The L bit is altered by comparison instructions. In a comparison instruction, the L bit is set to "1" if the second operand is less than the first operand, when both operands are
interpreted as unsigned integers. Otherwise, it is set to "0".
In Floating-Point comparisons, this bit is always cleared.
F: The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions use it
to indicate overflow).
o
Z: The Z bit is altered by comparison instructions. In a comparison instruction, the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is set to "0".
N: The N bit is altered by comparison instructions. In a comparison instruction, the N bit is set to "1" if the second
operand is less than the first operand, when both operands
are interpreted as signed integers. Otherwise, it is set to
"0".
U: If the U bit is "1", no privileged instructions may be executed. if the U bit is "0", then all instructions may be executed. When U = 0, the NS32008 is said to be in Supervisor
Mode; when U = 1, the NS32008 is said to be in User Mode.
A User Mode program is restricted from executing certain
instructions and accessing certain registers which could interfere with the operating system. For example, a User
Mode program is prevented from changing the setting of the
flag used to indicate its own privilege mode. A Supervisor
Mode program is assumed to be a trusted part of the operating system, hence it has no such restrictions.
S: The S bit specifies whether the SPO register on SP1 register is used as the stack pointer. The bit is automatically
cleared on interrupts and traps it. It may have a setting of 0
(use the SPO register) or 1 (use the SP1 register).
FP: The FRAME POINTER register is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
The frame pointer holds the address in memory occupied by
the old contents of the frame pOinter. (In the NS32008, the
upper eight bits of this register are always zero.)
SB: The STATIC BASE register points to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The SB
register holds the lowest address in memory occupied by
the global variables of a module. (In the NS32008, the upper
eight bits of this register are always zero.)
P: The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3.7.5). It may have a setting
of 0 (no trace pending) or 1 (trace pending).
INTBASE: The INTERRUPT BASE register holds the address of the dispatch table for interrupts and traps (Section
3.7). The INTBASE register holds the lowest address in
memory occupied by the dispatch table. (In the NS32008,
the upper eight bits of this register are always zero.)
I: If I = 1, then all interrupts will be accepted (Section 3.7). If
I = 0, only the NMI interrupt is accepted. Trap enables are
not affected by this bit.
2.1.3 The Configuration Register (CFG)
Within the Control section of the NS32008 CPU is the 4-bit
CFG Register, which declares the presence of certain external devices. It is referenced by only one instruction,
SETCFG, which is intended to be executed only as part of
system initialization after reset. The format of the CFG Register is shown in Figure 2-3.
MOD: The MODULE register holds the address of the module descriptor of the currently executing software module.
The MOD register is 16 bits long, therefore the module table
must be contained within the first 64K bytes of memory.
PSR: The PROCESSOR STATUS REGISTER holds the
status codes for the NS32008 microprocessor.
The PSR is 16 bits long, divided into two 8-bit halves (Figure
2-2). The low order eight bits are accessible to all programs, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
\cWF\'1
TLlEE/6156-5
FIGURE 2-3. CFG Register
The CFG I bit declares the presence of external interrupt
vectoring circuitry (specifically, the NS32202 Interrupt Control Unit). If the CFG I bit is set, interrupts requested through
the INT pin are "Vectored." If it is clear, these interrupts are
"Non-Vectored." See Section 3.7.
The F and C bits declare the presence of the FPU and Custom Slave Processors. If these bits are not set, the corresponding instructions are trapped as being undefined.
TLlEE/6156-4
FIGURE 2-2. The Processor Status Register
C: The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used with the
ADDC and SUBC instructions to perform multiple-precision
integer arithmetic calculations. It may have a setting of 0 (no
carry or borrow) or 1 (carry or borrow).
2.1.4 Memory Organization
The main memory of the NS32008 is a uniform linear address space. Memory locations are numbered sequentially
2-431
....
2.0 Architectural Description
(Continued)
starting at zero and ending at 224 -1. The number specifying a memory location is called an address. The contents of
each memory location is a byte consisting of eight bits (Figure 2-4A). Unless otherwise noted, diagrams in this document show data stored in memory with the lowest address
on the right and the highest address on the left. Also, when
data is shown vertically, the lowest address is at the top of a
diagram and the highest address at the bottom of the diagram. When bits are numbered in a diagram, the least significant bit is given the number zero, and is shown at the right
of the diagram. Bits are numbered in increasing significance
and toward the left.
The format of a Module Descriptor is shown in Figure 2-5.
The Static Base entry contains the address of static data
assigned to the running module. It is loaded into the CPU
Static Base register by the CXP and CXPD instructions. The
Program Base entry contains the address of the first byte of
instruction code in the module. Since a module may have
multiple entry pOints, the Program Base pOinter serves only
as a reference to find them.
15
I
MOO
I
I
oj
31
STATlCBASE
A
LINK TABLE ADDRESS
A. Byte at Address A
PROGRAM BASE
1'5
Mse's
A+l
T
LSB's
RESERVED
01
A
TL/EE/6156-7
FIGURE 2-5. Module DeSCriptor Format
B. Word at Address A
r
MSB's
A+3
A+2
A+ 1
T
The Link Table Address points to the Link Table for the
currently running module. The Link Table provides the information needed for:
LSB's
1. Sharing variables between modules. Such variables are
accessed through the Link Table via the External addressing mode.
A
TL/EE/6156-6
C. Double Word at Address A
FIGURE 2-4. Data Formats for NS32008 Memory
2. Transferring control from one module to another. This is
done via the Call External Procedure (CXP) instruction.
Two contiguous bytes are called a word (Figure 2-48). Except where noted (Section 2.2.1), the least significant byte
of a word is stored at the lower address, and the most significant byte of the word is stored at the next higher address.
In memory, the address of a word is the address of its least
significant byte, and a word may start at any address.
The format of a Link Table is given in Figure 2-6. A Link
Table Entry for an external variable contains the 32-bit address of that variable. An entry for an external procedure
contains two 16-bit fields: Module and Offset. The Module
field contains the new MOD register contents for the module being entered. The Offset field is an unsigned number
giving the position of the entry point relative to the new
module's Program Base pOinter.
Two contiguous words are called a double word (Figure 24C). Except where noted (Section 2.2.1), the least significant word of a double word is stored at the lowest address
and the most significant word of the double word is stored at
the address two greater. In memory, the address of a double word is the address of its least significant byte, and a
double word may start at any address.
For further details of the functions of these tables, see the
Series 32000 Instruction Set Reference Manual.
ENTRY
0
31
2.1.5 Dedicated Tables
ABSOLUTE ADDRESS
(VARIABLE)
Two of the NS32008 dedicated registers (MOD and INTBASE) serve as pOinters to dedicated tables in memory.
ABSOLUTE ADDRESS
(VARIABLE)
The INTBASE register pOints to the Interrupt Dispatch and
Cascade tables. These are described in Section 3.7.
OFFSET
The MOD register contains a pointer into the Module Table,
whose entries are called Module Descriptors. A Module Descriptor contains four pOinters, three of which are used by
the NS32008. The MOD register contains the address of the
Module Descriptor for the currently running module. It is automatically updated by the Call External Procedure instructions (CXP and CXPD).
I
MODULE
(PROCEDURE)
TLlEE/6156-B
FIGURE 2-6. A Sample Link Table
2-432
z
2.0 Architectural Description
U)
Co)
(Continued)
N
C)
C)
C»
OPTIONAL
EXTENSIONS
__________________ ....__________________
~A
r
-
-
~
DISP
DISP
IMM
IMM
INDEX
BYTE
INDEX
BYTE
t
t
C)
~--------~A~------~
DISPZ DISPI DISPZIDISPI
IMPLIED
IMMEDIATE
OPERAND(S)
....•
BASIC
INSTRUCTION
GEN
ADDR
MODE
A
GEN
ADDR
MODE
B
,
:,
,
,,
,,
,,
,,
OPCODE
)J
TLlEE/6156-10
FIGURE 2-7. General Instruction Format
2.2 INSTRUCTION SET
2.2.2 Addressing Modes
2.2.1 General Instruction Format
The NS3200a CPU generally accesses an operand by calculating its Effective Address based on information available when the operand is to be accessed. The method to be
used in performing this calculation is specified by the programmer as an "addressing mode."
Addressing modes in the NS3200a are designed to optimally support high-level language accesses to variables. In
nearly all cases, a variable access requires only one addressing mode, within the instruction that acts upon that
variable. Extraneous data movement is therefore minimized.
Figure 2-7 shows the general format of a Series 32000 instruction. The Basic Instruction is one to three bytes long
and contains the opcode and up to two 5-bit General Addressing Mode ("Gen") fields. Following the Basic Instruction field is a set of optional extensions which may appear,
depending on the instruction and the addressing modes selected.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or a), and the Index Byte specifies
which General Purpose register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-8.
GEN. ADDR. MODE
NS3200a Addressing Modes fall into nine basic types:
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions. an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the effective address of the operand in
memory.
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Memory Relative: A pOinter variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pOinter to generate the Effective Address of the operand.
REG. NO.
TLlEE/6156-9
FIGURE 2-8. Index Byte Format
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Displacement/Immediate field
may contain one or two displacements, or one immediate
value. The size of a Displacement field is encoded within the
top bits of that field, as shown in Figure 2-9, with the remaining bits interpreted as a signed (two's complement) value.
The size of an Immediate value is determined from the Opcode field. Both Displacement and Immediate fields are
stored most-significant byte first. Note that this is different
from the memory representation of data (Section 2.1.4.).
Some instructions require additional, "implied" immediates
and/or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Section 2.2.3).
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
2-433
tI
o
.-
i
r-----------------------------------------------------------------------------,
2.0 Architectural Description
Byte Displacement: Range -64 to
~
z
(Continued)
+ 63
eral Purpose Register by 1, 2, 4 or a and adding it into the
total, yielding the final Effective Addrsss of the operand.
Table 2-1 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
SIGNED DISPLACEMENT
Word Displacement: Range -8192 to
+ 8191
Double Word Displacement:
Range (Entire Addressing Space)
7
I
1
I
1
2.2.3 Instruction Set Summary
Table 2-2 presents a brief description of the NS3200a instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further detailS of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
o
Notations:
i = Integer length suffix: B = Byte
W = Word
D = Double Word
o
I
f = Floating-Point length suffix: F = Standard Floating
L = Long Floating
f.tI~
c,~\f.
s~\,."
gen = General operand. Any addressing mode can be
specified.
short = A 4-bit value encoded within the Basic Instruction.
(See Appendix A for encodings.)
oO~
'!>\Utl'"
imm = Immediate operand. An a-bit value appended after
any addressing extensions.
disp = Displacement (addressing constant): a, 16,32 bits.
All three lengths legal.
reg = Any General Purpose Register: RO-R7.
areg = Any Dedicated/Address Register: SP, SB, FP,
MOD.. INTBASE, PSR, UPSR, (bottom eight PSR bits).
creg = A Custom Slave Processor Register (implementation dependent).
TL/EE/6156-13
FIGURE 2-9. Displacement Encodings
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any Gen-
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction. (See Appendix A for encodings.)
2-434
r--------------------------------------------------------------------------,
2.0 Architectural Description
(Continued)
MODE
ASSEMBLER SYNTAX
cp
....
EFFECTIVE ADDRESS
Register
00000
00001
00010
00011
00100
00101
00110
00111
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO orFO
R1 or F1
R20rF2
R30rF3
R4 or F4
R50rF5
R60rF6
R70rF7
None: Operand is in the specified
register.
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (SB))
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP"
is either SPO or SP1, as selected
in PSR.
Memory Relative
Frame memory relative
10000
10001
Stack memory relative
10010
Static memory relative
Reserved
10011
(Reserved for Future Use)
Immediate
10100
Immediate
value
None: Operand is input from
instruction queue.
Absolute
10101
Absolute
@disp
Disp.
External
10110
External
EXT (disp1) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Top of Stack
10111
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Memory Space
11000
11001
11010
11011
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Scaled Index
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
• +disp
2-435
~
~
C)
C)
TABLE 2·1
NS32008 Addressing Modes
ENCODING
Z
EA (mode) + Rn.
EA (mode) + 2 x Rn.
EA (mode) + 4 x Rn.
EA (mode) + 8 x Rn.
'Mode' and 'n' are contained
within the Index Byte.
EA (mode) denotes the effective
address generated using mode.
C)
Q r--------------------------------------------------------------------------,
.,..
~
2.0 Architectural Description (Continued)
Q
C'I
:3
TABLE 2·2
NS32008 Instruction Set Summary
Z
MOVES
Format
4
2
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4·bit constant.
Move multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move effective address.
Operation
Operands
Description
ADDi
ADDQi
ADDCi
SUBi
SUBCi
NEGi
ABSi
MULi
QUOi
REMi
DIVi
MODi
MEli
DEli
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Add.
Add signed 4·bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to extended integer.
Divide extended integer.
INTEGER ARITHMETIC
Format
4
2
4
4
4
6
6
7
7
7
7
7
7
7
PACKED DECIMAL (BCD) ARITHMETIC
Format
6
6
Operation
Operands
Description
ADDPi
SUBPi
gen,gen
gen,gen
Add packed.
Subtract packed.
Operands
gen,gen
short,gen
gen,gen,disp
Description
Compare.
Compare to signed 4·bit constant.
Compare multiple: disp bytes (1 to 16).
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Description
Logical AND.
Logical OR.
Clear selected bits.
Logical exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
INTEGER COMPARISON
Format
Operation
4
CMPi
CMPQi
2
7
CMPMi
LOGICAL AND BOOLEAN
Format
4
4
4
4
6
6
2
Operation
ANDi
ORi
BICi
XORi
COMi
NOTi
Scondi
2-436
2.0 Architectural Description
z
en
w
(Continued)
N
TABLE 2-2
Instruction Set Summary (Continued)
SHIFTS
Format
6
6
6
BITS
Format
4
6
6
6
6
6
8
Operation
LSHi
ASHi
ROTi
Operands
gen,gen
gen,gen
gen,gen
Description
Logical shift, left or right.
Arithmetic shift, left or right.
Rotate, left or right.
Operation
TSITi
SSITi
SBITli
CSITi
CSITIi
ISITi
FFSi
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Test bit.
Test and set bit.
Test and set bit, interlocked.
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit.
o
oQ)
......
I
o
BIT FIELDS
Sit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records used
in Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned source.
Format
8
8
7
7
8
ARRAYS
Format
8
8
Operation
EXTi
INSi
EXTSi
INSSi
CVTP
Operands
reg,gen,gen,disp
reg,gen,gen,disp
gen,gen,imm,imm
gen,gen,imm,imm
reg,gen,gen
Description
Extract bit field (array oriented).
Insert bit field (array oriented).
Extract bit field (short form).
Insert bit field (short form).
Convert to bit field pointer.
Operation
CHECKi
INDEXi
Operands
reg,gen,gen
reg,gen,gen
Description
Index bound check.
Recursive indexing step for multiple-dimensional arrays.
STRINGS
String instructions assign specific functions to the
General Purpose Registers:
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
R1 - String 1 Pointer
RO - Limit Count
Format
Options on all string instructions are:
B (Backward):
Decrement string pointers after each
step rather than incrementing.
U (Until match):
End instruction if String 1 entry
matches R4.
End instruction if String 1 entry does
W (While match):
not match R4.
All string instructions end when RO decrements to zero.
Operation
MOVSi
MOVST
Operands
options
options
Description
Move String 1 to String 2.
Move string, translating bytes.
5
CMPSi
CMPST
options
options
Compare String 1 to String 2.
Compare, translating String 1 bytes.
5
SKPSi
SKPST
options
options
Skip over String 1 entries.
Skip, translating bytes for Until/While.
5
2-437
PI
C)
.....
~
r------------------------------------------------------------------------------------------,
2.0 Architectural Description
(Continued)
C)
TABLE 2·2
Instruction Set Summary (Continued)
N
~
Z
JUMPS AND LINKAGE
Format
Operation
3
JUMP
0
BR
0
Bcond
CASEi
3
2
ACBi
JSR
3
BSR
CXP
3
CXPD
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
disp
gen
[reg list] ,disp
[reg list]
disp
disp
disp
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4-bit constant and branch if non-zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor call.
Flag trap.
Breakpoint trap.
Save registers and allocate stack frame. (Enter Procedure)
Restore registers and reclaim stack frame. (Exit Procedure)
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from interrupt. (Privileged)
CPU REGISTER MANIPULATION
Format
Operation
1
SAVE
RESTORE
2
LPRi
2
SPRi
3
ADJSPi
BISPSRi
3
3
BICPSRi
5
SETCFG
Operands
[reg list!
[reg list!
areg,gen
areg,gen
gen
gen
gen
[option list]
Description
Save general purpose registers.
Restore general purpose registers.
Load dedicated register. (Privileged if PSR or INTBASE)
Store dedicated register. (Privileged if PSR or INTBASE)
Adjust stack pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set configuration register. (Privileged)
FLOATING POINT
Format
Operation
11
MOVf
9
MOVLF
9
MOVFL
9
MOVif
9
ROUNDfi
9
TRUNCfi
9
FLOORfi
11
ADDf
11
SUBf
MULf
11
11
DIVf
11
CMPf
11
NEGf
11
ABSf
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a floating point value.
Move and shorten a long value to standard.
Move and lengthen a standard value to long.
Convert any integer to standard or long floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
gen
gen
Load FSR.
Store FSR.
Operands
Description
No operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
9
9
LFSR
SFSR
MISCELLANEOUS
Format
Operation
1
NOP
WAIT
DIA
2-438
z
2.0 Architectural Description
(J)
w
I\)
o
oCC)
(Continued)
TABLE 2-2
Instruction Set Summary (Continued)
CUSTOM SLAVE
Format
•
......
o
Operation
Operands
Description
15.5
15.5
15.5
15.5
CCALOc
CCAL1c
CCAL2c
CCAL3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom calculate.
15.5
15.5
15.5
15.5
CMOVOc
CMOV1c
CMOV2c
CMOV3c
gen,gen
gen,gen
gen,gen
gen,gen
Custom move.
15.5
15.5
CCMPOc
CCMP1c
gen,gen
gen,gen
Custom compare.
15.1
15.1
15.1
15.1
CCVOci
CCV1ci
CCV2ci
CCV3ic
gen,gen
gen,gen
gen,gen
gen,gen
Custom convert.
15.1
15.1
CCV4DQ
CCV5QD
gen,gen
gen,gen
15.1
15.1
LCSR
SCSR
gen
gen
Load custom status register.
Store custom status register.
15.0
15.0
CATSTO
CATST1
gen
gen
Custom address/test. (Privileged)
(Privileged)
15.0
15.0
LCR
SCR
creg,gen
creg,gen
Load custom register. (Privileged)
Store custom register. (Privileged)
3.0 Functional Description
3.1 POWER AND GROUNDING
3.2 CLOCKING
The NS32008 requires a single 5V power supply, applied on
pin 48 (Vee).
The NS32008 inputs clocking Signals from the NS32201
Timing Control Unit (TCU), which presents two non-overlapping phases of a single clock frequency. These phases are
called PHI1 (pin 26) and PHI2 (pin 27). Their relationship to
each other is shown in Figure 3-2.
Grounding connections are made on two pins. Logic Ground
(GNDL, pin 24) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 25) is the common pin for the
output drivers. For optimal noise immunity, it is recommended that GNDL be attached through a single conductor directly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 3-1).
Each rising edge of PHil defines a transition in the timing
state ("T-State") of the CPU. One T-State represents the
execution of one microinstruction within the CPU and/or
one step of an external bus transfer. See Section 4 for complete specifications of PHI1 and PHI2.
In addition to Vee and Ground, the NS32008 CPU uses an
internally-generated negative voltage. It is necessary to filter
this voltage externally by attaching a pair of capacitors (Figure 3-1) from the BBG pin to ground. Recommended values
for these are:
PHil
Cl: 1 ".F, Tantalum.
C2: 1000 pF, low inductance. This should be either a
disc or monolithic ceramic capacitor.
~
1
i+
PHI2
5V
vcc~
NS32008
CPU
TL/EE/6156-15
FIGURE 3-2. Clock Timing Relationships
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHI1 and PHI2
be kept as short as possible, and that they not be
TL/EE/6156-14
FIGURE 3-1. Recommended Supply Connections
2-439
C) r---------------------------------------------------------------------------------~
.....
Ut
C)
C)
C\I
CO)
U)
z
3.0 Functional Description (Continued)
connected anywhere except from the TCU to the CPU. A
TTL clock signal (CTTL) is provided by the TCU for all other
clocking.
PHll~JLJJ-
I·
RST-------.::~
............,
3.3 RESETTING
The RST pin serves as a reset for on·chip logic. The CPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the CPU terminates instruction processing, resets its internal logic, and
clears the Program Counter (PC) and Processor Status
Register (PSR) to all zeroes.
TL/EE/6156-17
3.4 BUS CYCLES
The NS32008 will perform a bus cycle for one of the following reasons:
1. To write or read data to or from memory or a peripheral
interface device. Peripheral input and output are memorymapped in the Series 32000 family.
2. To fetch instructions into the 4-byte instruction queue.
This happens whenever the bus would otherwise be idle
and the queue is not already full.
3. To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
4. To transfer information to or from a Slave Processor.
4.SV
Vcc
J)Jl
-+-__-'
C;CLES
FIGURE 3-4. General Reset Timing
On application of power, RST must be held low for at least
50 ",s after Vee is stable. This is to ensure that all on-chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 clock cycles. The rising edge must occur while PHI1
is high. See Figures 3-3 and 8-4.
PHI , _ _
I
64cLOCK-1
In terms of bus timing, cases 1 through 3 above are identical. For timing specifications, see Section 4. The only external difference between them is the 4-bit code placed on the
Bus Status pins (STO-ST3). Slave Processor cycles differ in
that separate control signals are applied and transfers are
performed 16 bits at a time (Section 3.4.6).
I---~~:~
Figure 8-6 shows typical bus connections for the NS32008.
The address, data, and control signals referenced in the
following discussion are shown in this figure.
The sequence of events in a non-Slave Processor bus cycle
is shown in Figure 8-lIor a Read cycle and Figure 8-8 for a
Write cycle. The cases shown assume that the selected
memory or interface device is capable of communicating
with the CPU at full speed. If it is not, then cycle extension
may be requested through the RDY line (Section 3.4.1).
TL/EE/6156-16
FIGURE 3-3. Power-On Reset Requirements
The NS32201 Timing Contol Unit (TCU) provides circuitry to
meet the Reset requirements of the NS32008 CPU. Rgure
8·5 shows the recommended connections.
vcc
HU220'
NS32008
CPU
TCU
r------------,
I
I
I
,,--+1~;---,-__+--+_'~'----_l
RESET' "
I
RSTI
RSTO
1 - - - - _ - - - - - 1 iiSi
!'---- __________ .JI
EXTERNAL RESET
(OPTIONAL)
RESET SWITCH
(OPTIONAL)
SYSTEM RESET
TL/EE/6156-16
FIGURE 3-5. Recommended Reset Connections
2-440
z
en
Co)
3.0 Functional Description
(Continued)
A full-speed bus cycle is performed in four cycles of the
PHI1 clock signal, labeled T1 through T4. Clock cycles not
associated with a bus cycle are designated Ti (for "Idle").
During T1, the CPU applies an address on pins ADO-AD15
and A16-A2S. It also provides a low-going pulse on the
ADS pin, which serves the dual purpose of informing external circuitry that a bus cycle is starting and of providing control to an external latch for demultiplexing address bits 0-7
from the ADO-AD7 pins. See Figure 3-6. Also during this
time the status signal DDIN, indicating the direction of the
transfer, becomes valid.
During T2, the CPU switches the Data Bus, ADO-AD7, to
either accept or present data. Note that the signals AD8AD15 and AD16-AD2S remain valid, and need not be
latched. It also starts the Data Strobe (DS), signaling the
beginning of the data transfer. Associated signals from the
NSS2201 Timing Control Unit are also activated at this time:
RD (Read Strobe) or WR (Write Strobe), TSO (Timing State
Output, indicating that T2 has been reached) and DBE (Data
Buffer Enable).
N
The TS state provides for access time requirements, and it
occurs at least once in a bus cycle. At the end of T2 or TS,
on the falling edge of the PHI2 clock, the RDY (Ready) line
is sampled to determine whether the bus cycle will be extended (Section S.4.1).
If the CPU is performing a Read cycle, the Data Bus (ADOAD7) is sampled at the falling edge of PHI2 of the last TS
state. See Timing Specification, Section 4. Data must, however, be held at least until the beginning of T4. DS and RD
are guaranteed not to go inactive before this point, so the
rising edge of either of them may safely be used to disable
the device providing the input data.
The T4 state finishes the bus cycle. At the beginning of T4,
the DS, RD or WR, and TSO signals go inactive, and at the
rising edge of PHI2, DBE goes inactive, having provided for
necessary data hold times. Data during Write cycles remains valid from the CPU throughout T4. Note that the Bus
Status lines (STO-STS) change at the beginning of T4, anticipating the following bus cycle (if any).
ODIN
DATA
BUFFER
ADO-AD7 I'
,---
NS32008
ADs
I
OCTAL
LATCH
AO-A23
ADB-ADI5
A1B-A23
PHil
r
PHil
PHI2
1
PHI2
os
I
os
ADS
ODIN
DBE
AD
RD
NS32201
WR
WR
TSO
TSO
TL/EE/6156-19
FIGURE 3-6. Bus Connections
2-441
C
C
~
....c
o
....
~~
r-----------------------------------------------------------------------------~
3.0 Functional Description (Continued)
I
z
PHI 1
PHI 2
ADI-AD16
A16-A23
ADo-AD7
ADs
I
N83ZOO8 CPU 8USSIGNALS
T1
12
T3
T4
I
T10RTI
I
[
[
[
[
[
5T0-5T3
[
iiiiiii
[
Os
[
ROY
T40RTi
[
AD [
5BE[
TLlEE/6156-20
FIGURE 3·7_ Read Cycle Timing
2-442
z
~
N
3.0 Functional Description (Continued)
o
.
o
NS32008 CPU BUS SIGNALS
co
......
o
NU220' TCU BUS SIGNALS
Dai[
TL/EE/6156-21
FIGURE 3·8. Write Cycle Timing
2-443
C)
..-
r------------------------------------------------------------------------------------------,
~
3.0 Functional Description
C"oI
3.4.1 Cycle Extension
en
To allow sufficient strobe widths and access times for any
speed of memory or peripheral device, the NS32008 pro·
vides for extension of a bus cycle. Any type of bus cycle
except a Slave Processor cycle can be extended.
In Figures 3-7 and 3-8, note that during T3 all bus control
signals from the CPU and TCU are flat. Therefore, a bus
cycle can be cleanly extended by causing the T3 state to be
repeated. This is the purpose of the RDY (Ready) pin.
C)
C)
CO)
z
(Continued)
The RDY pin is driven by the NS32201 Timing Control Unit,
which applies WAIT States to the CPU as requested on
three sets of pins:
1. CWAIT (Continuous WAIT), which holds the CPU in WAIT
States until removed.
2. WAIT1, WAIT2, WAIT4, WAIT8 (collectively, WAITn),
which may be given a 4-bit binary value requesting a specific number of WAIT States from 0 to 15.
3. PER (Peripheral), which inserts five additional WAIT
states and causes the TCU to reshape the RD and WR
strobes. This provides the setup and hold times required
by most MOS peripheral interface devices.
Combinations of these various WAIT requests are both legal
and useful. For details of their use, see the NS32201 Data
Sheet.
Rgure 3-10 illustrates a typical Read cycle, with two WAIT
states requested through the TCU WAITn pins.
At the end of T2 on the falling edge of PHI2, the RDY line is
sampled by the CPU. If RDY is high, the next T-states will be
T3 and T4, ending the bus cycle. If RDY is low, then another
T3 state will be inserted after the next T-state and the RDY
line will again be sampled on the falling edge of PHI2. Each
additional T3 state after the first is referred to as a "WAIT
STATE". See Figure 3-9.
Tl
T2
T3
I
(W~T)
I
T4
PHil
PHI 2
RDY
TLlEE/6156-22
FIGURE 3-9. ROY Pin Timing
3.4.2 Bus Status
The NS32008 CPU presents four bits of Bus Status information on pins STO-ST3. The various combinations on these
pins indicate why the CPU is performing a bus cycle, or, if it
is idle on the bus, why it is idle.
Referring to Figures 3-7 and 3-8, note that Bus Status leads
the corresponding Bus Cycle, going valid one clock cycle
before T1 , and changing to the next state at T4. This allows
the system designer to fully decode the bus status and, if
desired, latch the decoded signals before ADS initiates the
Bus Cycle.
address FFFE0016, expecting a vector number to be provided from the Master NS32202 Interrupt Control Unit. If the
vectoring mode selected by the last SETCFG instruction
was Non-Vectored, then the CPU will ignore the value it has
read and will use a default vector instead, having assumed
that no NS32202 is present. See Section 3.4.5.
0101
The Bus Status pins are interpreted as a 4-bit value, with
STO the least significant bit. Their values decode as follows:
0000
The bus is idle because the CPU does not need to
perform a bus access.
0001
The bus is idle because the CPU is executing the
WAIT instruction.
(Reserved for future use.)
0010
0011
The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100
Interrupt Acknowledge, Master.
The CPU is performing a Read cycle. To acknowledge receipt of a Non-Maskable Interrupt (on NMI),
it will read from address FFFF0016, but will ignore
any data provided. To acknowledge receipt of a
Maskable Interrupt (on IND, it will read from
0110
0111
1000
2-444
Interrupt Acknowledge, Cascaded.
The CPU is reading a vector number from a Cascaded NS32202 Interrupt Control Unit. The address
provided is the address of the NS32202 Hardware
Vector register. See Section 3.4.5.
End of Interrupt, Master.
The CPU is performing a Read cycle to indicate that
it is executing a Return from Interrupt (RETI) instruction. See Section 3.4.5.
End of Interrupt, Cascaded.
The CPU is reading from a Cascaded Interrupt Control Unit to indicate that it is returning (through RETI)
from an interrupt service routine requested by that
unit. See Section 3.4.5.
Sequential Instruction Fetch.
The CPU is reading the next sequential word from
the instruction stream into the Instruction Queue. It
will do so whenever the bus would otherwise be idle
and the queue is not already full.
3.0 Functional Description
z
en
w
(Continued)
N
Q
Q
Q)
•
.....
Q
PREV.CYCLE
IT40RTi
PHil [
PHI2 [
NS32DD8 CPU BUS SIGNALS
I
T1
I
T2
13
I (W~n I (W~T) I
NEXT CYCLE
T4
1T10RTi
-
J1Ul Ul
J1JlLf1~UlADDRESS VALID
VALID )--0 ~8Im ~A~--~~ ~
V
ADS [
NEXT ADD R
,...
'iJ
~~
IX
STAlUSVALID
NEXTSlATU S
I~
~~ ~
-
~
R
~r--
STO-S13 [
I
nJLJL Lfl--fL ""L!l-'
~ ~ff~ ~
ADo-AD7 [
I
f-
1\
/
NS32201 TCU CYCLE EXTENSION SIGNALS
~
~
CWAiT[ %; ~ ~
PER [
~~
~
'0
~ o/a 0/& ~
Wi I'W ::'@ ~
~ ~ 0/& t%
I
WAITn [
~ 0/& ~
Gw
~ ~~~~
I
ROY [
(TCU TO CPU )
NS32201 lCU BUS SIGNALS
-
V
-
V
II
- ~
-
II
V
1\
TL/EE/6156-23
Note: Arrows on CWAIT, PER, WAITn indicale pOinls al which the TCU samples.
Arrows on ADO-AD7 and ROY indicate points at which the CPU samples.
FIGURE 3-10. Extended Cycle Example
2-445
3.0 Functional Description
(Continued)
1001
Non-Sequential Instruction Fetch.
1010
The CPU is performing the first fetch of instruction
code after the Instruction Queue is purged. This will
occur as a result of any jump or branch, or any interrupt or trap, or execution of certain instructions.
Data Transfer.
3.4.3.2 Bit Field Accesses
An access to a Bit Field in memory always generates a Double Word transfer starting at the address containing the
least-significant bit of the field. The Double Word is read by
an Exact instruction; an Insert instruction reads a Double
Word, modifies it, and rewrites it.
The CPU is reading or writing an operand of an instruction.
1011
1100
1101
1110
1111
3.4.3.3 Extending Multiply Accesses
The extending multiply instruction (MEl) will return a result
which is twice the size in bytes of the operand that it reads.
If the multiplicand is in memory, the most-significant half of
the result is written first (at the higher address), then the
least-significant half.
Read RMW Operand.
The CPU is reading an operand which will subsequently be modified and rewritten.
Read for Effective Address Calculation.
The CPU is reading information from memory in order to determine the Effective Address of an operand. This will occur whenever an instruction uses
the Memory Relative or External addressing mode.
3.4.4 Instruction Fetches
Instructions for the NS3200B CPU are "prefetched"; that is,
they are input before being needed into the next available
entry of the 4-byte Instruction Queue. The CPU performs
two types of Instruction Fetch cycles: Sequential and NonSequential. These can be distinguished from each other by
their differing status combinations on pins STO-ST3 (Section 3.4.2).
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full.
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program. Any jump or
branch instruction, a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential. In addition,
certain instructions flush the Instruction Queue, causing the
next instruction fetch to display Non-Sequential status. Only
the first bus cycle after a break displays Non-Sequential
status.
Transfer Slave Processor Operand.
The CPU is either transferring an instruction operand to or from a Slave Processor, or it is issuing the
Operation Word of a Slave Processor instruction.
See Section 3.B.1.
Read Slave Processor Status.
The CPU is reading a status word from a Slave
Processor. This occurs after the Slave Processor
has signaled completion of an instruction. The
transferred word tells the CPU whether a trap
should be taken, and in some instructions, it presents new values for the CPU Processor Status Register bits N, Z, L or F. See Section 3.B.1.
Broadcast Slave 10.
The CPU is initiating the execution of a Slave Processor instruction. The 10 Byte (first byte of the instruction) is sent to all Slave Processors, one of
which will recognize it. From this point, the CPU is
communicating with only one Slave Processor. See
Section 3.B.1.
3.4.5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose is interrupt control rather
than the transfer of instructions or data. Execution of the
Return from Interrupt instruction (RETI) will also cause Interrupt Control bus cycles. These differ from instruction or data
transfers only in the status presented on pins STO-ST3. All
Interrupt Control cycles are Read cycles. Table 3-1 summarizes NS3200B interrupt sequences.
3.4.3 Data Access Sequences
The NS3200B accesses all memory and peripheral devices
in sequences of single-byte transfers. Transfer of values
larger than bytes is performed from least-significant byte
(lowest address) to most-significant byte.
This section describes only the Interrupt Control sequences
associated with each interrupt and with the return from its
service routine. For full details of the NS3200B interrupt
structure, see Section 3.7.
3.4.3.1 Bit Accesses
The bit instructions access the byte containing the designated bit. The Test and Set Bit instruction (SBID, for example,
reads a byte, alters it, and rewrites it, having changed the
contents of one bit.
2-446
r--------------------------------------------------------------------------,
3.0 Functional Description
~
(Continued)
~
o
o
CO
TABLE 3·1
Interrupt Sequences
Cycle
Status
.....
I
o
Bus
Address
A. Nonmaskable Interrupt Control Sequences.
Interrupt Acknowledge
1
0100
FFFF0016
Interrupt Return
None: Performed through Return from Trap (RETT) instruction.
o
Don't Care
B. Nonvectored Interrupt Control Sequences.
Interrupt Acknowledge
1
0100
FFFE0016
Interrupt Return
None. Performed through return from Trap (RETT) instruction.
o
Don't Care
C. Vectored Interrupt Sequences: Noncascaded.
Interrupt Acknowledge
1
0100
Interrupt Return
0110
1
FFFE0016
o
Vector: Range 0-127
FFFE0016
o
Vector: Same as in
Previous Interrupt
Acknowledge Cycle
FFFE0016
o
Cascade Index:
Range -16to-1
o
Vector: Range 0-255
o
Cascade Index: Same
as in Previous Interrupt
Acknowledge Cycle
o
Don't Care
D. Vectored Interrupt Sequences: Cascaded.
Interrupt Acknowledge
1
0100
Z
(The CPU here uses the Cascade Index to find the Cascade Address.)
0101
Cascade
2
Address
Interrupt Return
0110
FFFE0016
1
(The CPU here uses the Cascade Index to find the Cascade Address.)
0111
Cascade
2
Address
2·447
o
..-
~
3.0 Functional Description
~
3.4.6 Slave Processor Communication
~
Z
(Continued)
AD(O·IS)
The SPC pin is used as the data strobe for Slave Processor
transfers. In a Slave Processor bus cycle, data is transferred
16 bits at a time on the Data Bus (ADO-AD15) and the
status lines STO-ST3 are monitored by each Slave Processor in order to determine the type of transfer being performed. Figure 3-11 shows typical Slave Processor connections. SPC is bidirectional, but is driven by the CPU during all
Slave Processor bus cycles. See Section 3.8 for full protocol sequences.
AT/SPC
"
v
O(o-IS)
SPC
SLAVE
PROCESSOR
N532032
CPU
STO-5T3
5TO-5T3
TL/EE/6156-24
FIGURE 3-11. Slave Processor Connections
PREVo CYCLE
PHI1
[
PHI2
[
5PC
[
I
T40rTi
NEXT CYCLE
T1
T4
T10RTi
I
ADO-AD7 [
5TO-5T3
[
ADS
[
TLlEE/6156-25
Nole 1. CPU samples Data Bus here.
Nole 2. DBE and all o1her NS32201 TCU bus signals remain inactive be·
cause no ADS pulse is received from the CPU.
FIGURE 3-12. CPU Read from Slave Processor
2-448
.--------------------------------------------------------------------,z
tn
3.0 Functional Description (Continued)
c.,)
I\)
sequence ("protocol") established by the instruction under
execution; but the CPU indicates the direction on the DDIN
pin for hardware debugging purposes.
3.4.6.1 Slave Processor Bus Cycles
A Slave Processor bus cycle always takes exactly two clock
cycles, labeled T1 and T4 (see Figures 3-12 and 3-13). During a Read cycle SPC is active from the beginning of T1 to
the beginning of T4, and the data is sampled at the end of
T1. The Cycle Status pins lead the cycle by one clock period, and are sampled at the leading edge of SPC. During a
Write cycle, the CPU applies data and activates SPC at T1 ,
removing SPC at T 4. The Slave Processor latches status on
the leading edge of SPC and latches data on the trailing
edge.
3.4.6.2 Slave Operand Transfer Sequences
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (ADO-AD7), and a
Word operand is transferred on the entire 16-bit bus (ADOAD15). A Double Word is transferred in a consecutive pair
of bus cycles, least-significant word first. A Quad Word is
transferred in two pairs of Slave cycles, with other bus cycles possibly occurring between them. The word order is
from least-significant to most-significant word.
Since the CPU does not pulse the Address Strobe (ADS),
no bus signals are generated by the NS32201 Timing Control Unit. The direction of a transfer is determined by the
PREV.CYCLE
I
PHil
[
sPc
[
ADO-AD7
[
T40RTi
NEXTCVCLE
T1
T4
T1 OR Ti
I
STD.STI [
ADS
[
_(2)[
DBE
TL/EE/6156-26
Note 1. Slave Processor samples Data Bus here.
Note 2. DBE, being provided by the NS322Dl TCU, remains Inactive due to
the fact that no pulse is presented on ADS, TCU signals RD, WR and TSO
also remain inactive.
FIGURE 3-13. CPU Write to Slave Processor
2-449
o
oOC)
.
.....
o
o
.....
I
CCI
3.0 Functional Description
C'I
3.5 BUS ACCESS CONTROL
The NS3200B CPU has the capability of relinquishing its
access to the bus request from a DMA device or another
CPU. This capability is implemented on the HOLD (Hold Request) and HLDA (Hold Acknowledge) pins. By asserting
HOLD low, an external device requests access to the bus.
On receipt of HLDA from the CPU, the device may perform
bus cycles, as the CPU at this point has set the ADO-AD15,
A16-A23, ADS and DDIN pins to the TRI-STATEI!> condition. To return control of the bus to the CPU, the device sets
HOLD inactive, and the CPU acknowledges return of the
bus by setting HLDA inactive.
o
o
C')
U)
Z
I
Ti
I
(Continued)
Ti
How quickly the CPU releases the bus depends on.whether
it is idle on the bus at the time the HOLD request IS made,
as the CPU must always complete the current bus cycle.
Figure 3-14 shows the timing sequence when the CPU is
idle. In this case, the CPU grants the bus during the immediately following clock cycle. Figure 3-15 shows the sequence
if the CPU is using the bus at the time that the HOLD request is made. If the request is made during or before the
clock cycle shown (two clock cycles before T4), the CPU
will release the bus during the clock cycle following T4. If
the request occurs closer to T4, the CPU may alre~dy.have
decided to initiate another bus cycle. In that case, It will not
grant the bus until after the next T4 state. Note that this
situation will also occur if the CPU is idle on the bus, but has
initiated a bus cycle internally.
I··· I
TI
TI
TI
TIORT1
I
PHll[JULf
PHI2
[
HOLD [
HCDA[
AFFECTED SIGNALS
------- It------ -------
ADS [
~-----
-----
---- ~r---- -----
DFN[
ADI-AD15 [
A16·A23
:...: VIN:>: Vee
-20
30
p.A
Active Supply Current
IOUT=O, TA=25'C
300
mA
Icc
V
204
180
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
and PHI2 and 0.8V or 2.0V on all other signals as illustrated
in Figures 4·2 and 4·3, unless specifically stated otherwise.
PHln
SIG!
SIG2
[3(
[[
I
Abbreviations:
L.E.-Ieading edge
T.E.-trailing edge
R.E.--fising edge
F.E.-falling edge
PHln
~
tSIGlI
ISIG2h
SIG!
O.BV
O.4SV
2.4V
t.'~
SIG2
[
[
[
£
2.4V
O.BV
\
tSIG!1
O.4SV
2.4V
2.0V
/
tSlG2h
O.4SV
TLlEEI6!56-39
TLlEEI6!56-3B
FIGURE 4-3. Timing Specification Standard
(Signal Valid Before Edge)
FIGURE 4·2. Timing Specification Standard
(Signal Valid After Edge)
2·463
o
o
C»
.....•
o
4.0 Device Specifications (Continued)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32008·10
Maximum times assume capacitive loading of 100 pF
Name
Figure
Description
Reference/Conditions
NS32008·10
Min
tAlv
4·4
Address Bits 0-7 Valid
after R.E., PHI1 T1
tAlh
4·4
Address Bits 0-7 Hold
after R.E., PHI1 T2
tov
4·4
Data Valid (Write Cycle)
after R.E., PHI1 T2
Units
Max
50
ns
50
ns
5
ns
tOh
4·4
Data Hold (Write Cycle)
after R.E., PHI1 next T1 or Ti
tAHv
4·4
Address Bits 8-23 Valid
after R.E., PHI1 T1
tAHh
4·4
Address Bits 8-23 Hold
after R.E., PHI1 next T1 or Ti
0
ns
tALADSs
4·5
Address Bits 0-7 Set Up
before ADS T.E.
25
ns
tAHADSs
4·5
Address Bits 8-23 Set Up
before ADS T.E.
25
ns
tALAOSh
4·10
Address Bits 0-7 Hold
after ADS T.E.
15
tAli
4·5
Address Bits 0-7 Floating
after R.E., PHI1 T2
25
ns
IsTv
4·4
Status (STO-ST3) Valid
after R.E., PHI1 T4
(before T1, see note)
45
ns
IsTh
4·4
Status (STO-ST3) Hold
after R.E., PHI1 T4 (after T1)
tODINv
4·5
ODIN Signal Valid
after R.E., PHI1 T1
tDDINh
4·5
ODIN Signal Hold
after R.E., PHI1 next T1 or Ti
tADSa
4·4
ADS Signal Active (Low)
after R.E., PHI1 T1
35
ns
tADSia
4·4
ADS Signal Inactive
after R.E., PHI2 T1
40
ns
tADSw
4·4
ADS Pulse Width
at 0.8V (both edges)
tOSa
4·4
OS Signal Active (Low)
after R.E., PHI1 T2
40
tOSia
4·4
OS Signal Inactive
after R.E., PHI1 T4
40
ns
tAU
4·6
ADO-AD7 Floating (Caused by HOLD)
after R.E., PHI1 T1
25
ns
tAH!
4·6
A8-A23 Floating (Caused by HOLD)
after R.E., PHI1 T1
25
ns
tAOS!
4·6
ADS Floating (Caused by HOLD)
after R.E., PHI1 Ti
50
ns
tODIN!
4·6
ODIN Floating (Caused by HOLD)
after R.E., PHI1 Ti
50
ns
tHlOAa
4·6
HLDA Signal Active (Low)
after R.E., PHI1 Ti
50
ns
tHLDAia
4·8
HLDA Signal Inactive
after R.E., PHI1 Ti
50
ns
tADSr
4·8
ADS Signal Returns from Floating
(Caused by HOLD)
after R.E., PHI1 Ti
55
ns
tDOINr
4·8
ODIN Signal Returns from Floating
(Caused by HOLD)
after R.E., PHI1 Ti
55
ns
tSPCa
4·13
SPC Output Active (Low)
after R.E., PHI1 T1
35
ns
tSPCia
4·13
SPC Output Inactive
after R.E., PHI1 T4
35
ns
tSPCn!
4·15
SPC Output Nonforcing
after R.E., PHI2 T4
30
ns
tDv
4·11
Data Valid (Slave Processor Write)
after R.E., PHI1 T1
50
tOh
4·11
Data Hold (Slave Processor Write)
after R.E., PHI1 next T1 or Ti
0
tpFSw
4·15
PFS Pulse Width
at 0.8V (both edges)
50
tPFSa
4·15
PFS Pulse Active (Low)
after R.E., PHI2
40
ns
tPFSia
4·15
PFS Pulse Inactive
after R.E., PHI2
40
ns
2·464
0
ns
50
ns
ns
0
ns
50
0
ns
ns
30
ns
ns
ns
ns
ns
z
4.0 Device Specifications
en
c.:I
(Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS3200B-l0 (Continued)
Name
Figure
Referencel
Conditions
Description
NS3200B-l0
Min
Units
Max
tllOs
4-17
ILO Signal Setup
before RE., PHil Tl
of first interlocked
read cycle
50
ns
tllOh
4-18
ILO Signal Hold
after RE., PHil T3
of last interlocked
write cycle
10
ns
tllOa
4-19
ILO Signal Active (Low)
after R.E., PHil
40
ns
tllOia
4-19
ILO Signal Inactive
after R.E., PHil
40
ns
tusv
4-20
U/S Signal Valid
after RE., PHil T4
45
tUSh
4-20
U/S Signal Hold
after R.E., PHil Tl
8
ns
tNSPF
4-16b
Nonsequential Fetch to Next PFS
Clock Cycle
after R.E., PHil Tl
4
tcp
tPFNS
4-16a
PFS Clock Cycle to Next NonSequential Fetch
before RE., PHil Tl
4
tcp
~
~
•
.....
o
ns
Last Operand Transfer of an
before RE., PHil Tl
0
tcp
Instruction to Next PFS clock
of first bus
Cycle
cycle of transfer
Note: Every memory cycle starts with T4, during which Cycle Status is applied. lithe CPU was idling, the sequence will be:"...Ti, T4, n ...".11 the CPU was not
idling, the sequence will be:"...T4, Tl ...".
tLXPF
4-25
4.4.2.2 Input Signal Requirements: NS3200B-l0
Name
Figure
Description
Referencel
Conditions
Min
NS3200B-l0
Units
Max
tpWR
4-21
Power Stable to RST R.E.
after Vcc reaches 4.5V
50
IJ-s
tOls
4-5
Data in Setup (Read Cycle)
before F.E., PHI2 T3
15
ns
tOlh
4-5
Data in Hold (Read Cycle)
after RE., PHil T4
3
ns
tHlOa
4-6
HOLD Active (Low) Setup Time
(See Note)
before F.E., PHI2 TXl
25
ns
tHlOia
4-8
HOLD Inactive Setup Time
before F.E., PHI2 Ti
25
ns
tHlOh
4-6
HOLD Hold Time
after RE., PHil TX2
0
ns
tROYs
4-9,4-10
ROY Setup Time
before F.E., PHI2
T20rT3
25
ns
tROYh
4-9,4-10
ROY Hold Time
after F.E., PHil T3
5
ns
tRSTs
4-21,4-22
RST Setup Time
before F.E., PHil
15
ns
tRSTw
4-22
RST Pulse Width
at 0.8V (both edges)
64
tep
tiNTs
4-23
INT Setup Time
before T.E., PHil
20
ns
tNMlw
4·28
NMI Pulse Width
at 0.8V (both edges)
70
ns
tOls
4-12
Data Setup (Slave Read Cycle)
before F.E., PHI2 Tl
15
ns
tOlh
4·12
Data Hold (Slave Read Cycle)
after RE., PHil T4
3
ns
tSPCd
4-13
SPC Pulse Delay from Slave
after RE., PHI2 T4
25
ns
tspcs
4-13
SPC Setup Time
Before F.E., PHil
30
ns
4-13
SPC Pulse Width from Slave
at 0.8V (both edges)
20
ns
tspCw
Processor (Async. Input)
NOTE: This setup time is necessary to ensure prompt acknowledgement via HLDA and the ensuing floating of CPU off the buses. Note that the time Irom the
receipt 01 the HOLD signal until the CPU Iloats is a function of the time ROTIi signal goes low, and the state of the ROY input.
2-465
fII
4.0 Device Specifications (Continued)
4.4.2.3 Clocking Requirements: NS32008-10
Name
Figure
Referencel
Conditions
Description
NS32008-10
Unit
Min
Max
100
250
ns
tcp
4·14
Clock Period
R.E., PHI1, PHI2 to next
R.E., PHI1, PHI2
teLw
4-14
PHI1, PHI2
Pulse Width
at 2.0V on PHI1,
PHI2 (both edges)
0.5 tep
-10n8
tCLh
4-14
PHI1, PHI2 High Time
at Vec - 0.9Von
PHI1, PHI2 (both edges)
0.5tep
-15 ns
tCLI
4-14
PHI1, PHI2 Low Time
at O.BV on
PHI1, PHI2
0.5tep
-5n8
tnOVL(1,2)
4-14
Non-Overlap Time
O.BV on F.E., PHI1, PHI2 to
O.BV on R.E., PHI1, PHI2
-2
5
ns
Non-OVerlap Asymmetry
at O.BVon PHI1, PHI2
-4
4
ns
at 2.0Von PHI1, PHI2
-5
5
ns
tnOVLas
(tnOVL(1) - tnOVL(2»)
tCLwas
PHI1, PHI2 Asymmetry
(tCLw(1) - teLw(2»)
2-466
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
T2
TI
T3
T4
PHil [
PHI2 [
ADO-AD7 [
AD8-ADI5 [
A16-23
(HIGH)
[....,I-___
os[
STD-3
--i-,-_V_A_L_ID_+_ _ _
='+'~ ~-N-E-X-T_-
-!-----l:~IDSa
ROY [
TL/EE/6156-40
FIGURE 4·4. Write Cycle
Tl
T2
T3
T4
PHil [
PHI2 [
ADO-AD7 [
ADB-AD15 [
AI6-23
•
VALID
ADS [
ODIN [
STo-3 [
VALID
--lIDDINh
NEXTCY LE
STATUS
os[
ROY [
(HI H)
TL/EE/615B-41
FIGURE 4·5. Read Cycle
2·467
...
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
!:
4.0 Device Specifications (Continued)
~
en
TXI
z
TX2
TI
Ti
T4
Ti
PHil [
PHI2 [
HOLD [
HLiiA[
'ADS!
IODIN!
~[
ADO-AD7 [
ADB-ADIS [
AI6-23
--
----(FLOATINGj----
L____ _
-t-----t-----t-----+-""\l'~~ _________
(FLOATING)
I
-t-----t-----+-----+-,I ~~H~ __ ' ____
I
---1------(FLO~TING)
TLlEE/6156-42
Note: Whenever the CPU is not Idling (not in Ti). the HOLD request (HOLD low) must be active tHLDa before the failing edge of PHI2 of the clock cycle thai appears
two clock cycles before T4(TXI) and stay low unUI tHLDh after the rising edge of PHil of the clock cycle that precedes T4(TX2) for the request to be acknowledged.
FIGURE 4-6. Floating by HOLD Timing (CPU Not Idle Initially)
TI
TI
T4
PHil [
PHil [
PHI2 [
PHI2[
HOLD [
HLDA [
-L~~r$Aa"-
~ [-+---4-JI
iiiiLD[
HLiiA [
--------(FLOATING)
~
(FLOATING)
ADD-AD7 [ -
-+____-+....J
[_ ________
AI6-23 [ __
ADB-AD1S [ AI6-23
------
(HIGH)
:~~:~ ________I______ _
ADO-IS
(FLOATING)
TLlEE/6156-43
TL/EE/6156-44
FIGURE 4-8. Release from HOLD
FIGURE 4-7. Floating by HOLD Timing
(CPU Initially Idle)
2-468
Z
tn
w
N
o
o
4.0 Device Specifications (Continued)
CD
•
....
o
PHil [
PHI2 [
ROV [
TLlEE/6156-45
TL/EE/6156-46
FIGURE 4·9. Ready Sampling
(CPU Initially READY)
I
PHil [
11
I
T4
FIGURE 4·10. Ready Sampling
(CPU Initially NOT READY)
I
I
JLSLj"
11
I
T4
I
PHI1[~
PHI2 [
PHI2 [
A~O-IS [
ADO-15 [
DATA (FROM SLAVE)~_-I_
SPe[
SPC [
(CPU)
DiiiN[
STO-3
[+____+../ ,....2.=~
STO-15 [
-+_S_~_A_JU_S_'l_A_LI_O+-J
AiiS[
AiiS[
NEXT STATUS
(HIGH)
TLlEE/6156-48
TL/EE/6156-47
FIGURE 4·12. Slave Processor Read Timing
FIGURE 4·11. Slave Processor Write Timing
T4
Tl
PHI1 [
PH12 [
-+_......
SPC [
(FROM CPU)
(FROM
SLASJE1 [ - - - - - - - - - - - - - - - - -
------
TL/EE/6156-82
Note: After transferring last operand to a Slave Processor, CPU
turns OFF driver and holds SPC high with internal 5 kO pullup_
FIGURE 4·13. SPC Timing
2-469
o ,-----------------------------------------------------------------------------,
....
~
4.0 Device Specifications (Continued)
o
iza
PHil [
-----..pr
PHI2 [
TLlEE/S156-50
FIGURE 4-14. Clock Waveforms
PHI2 [~fl----Il--J
m~r-e-
TLlEE/S15S-51
FIGURE 4-15. Relationship of PFS to Clock Cycles
Tl
IpFNS
~~3[
____________________________
_J
~ C_O_DE_'_OO_'____
__
TLlEE/S15S-52
FIGURE 4-16a. Guaranteed Delay, PFS to Non-Sequential Fetch
I
Tl
I
T2
I ••• I
I
I
I
PHI1[~fl--rl-JL
iDS [
S~3[_+------C-O-D-E-'00-'------~r------_+-------------INSPF
TLlEE/e15S-53
FIGURE 4-16b. Guaranteed, Delay, Non-Sequential Fetch to PFS
2-470
r--------------------------------------------------------------------------.z
4.0 Device Specifications
I
T30RTi
(J)
(Continued)
I
T40RTi
Co)
N
I
o
o
T1
T2
T3
tp
.....
o
T4
AoS[
iLO[
TL/EE/6156-54
FIGURE 4·17. Relationship of ILO to First Operand Cycle
of an Interlocked Instruction
T30RT,
T4 OR Ti
ILO[ ________________
I
T1
T2
T3
T4
~--------------fJ
TL/EE/6156-55
FIGURE 4·18. Relationship of ILO to Last Operand Cycle
of an Interlocked Instruction
fII
TL/EE/6156-56
FIGURE 4·19. Relationship of ILO to Any Clock Cycle
I T30RTi I T4 OR Ti
I
T1
T2
T3
T4
PHI1[
UlS [<..L.L.LL.LLJ.LfU 1\----1r--------.-------------+-'1
TL/EE/6156-57
FIGURE 4·20. U/S Relationship to Any Bus CycleGuarantee Valid Interval
2-471
C)
..,...
I
co
C)
,---------------------------------------------------------------------------------,
4.0 Device Specifications
(Continued)
C)
N
~-----------4~
C"')
(/)
VCC
Z
PHil [ _ _ _! -_ _--'
RST
[
lPWR
TLlEE/6156-59
_ _ _ _ _ _ _ _ _ _ _ _ _~~-J
FIGURE 4-22. Non-Power-On Reset
TLlEE/6156-58
FIGURE 4-21. Power-On Reset
PHll[~
NM{
~tINTS
iNT[
~,-----tNMlw_r
~
TL/EE/6156-61
FIGURE 4-24. NMllnterrupt Signal Timing
TL/EE/6156-60
FIGURE 4-23. INT Interrupt Signal Detection
NEXT
FIRST BUS CYCLE
T1
T2
T3
T4
T10rTi
I
TL/EE/6156-62
Note: In a transfer of a Read-Modify-Write type operand, this is the Read transfer,
displaying RMW Status (Code 1011).
FIGURE 4-25. Relationship Between Last Data Transfer of an
Instruction and PFS Pulse of Next Instruction
2-472
z
~
N
Appendix A: Instruction Formats
Options:
NOTATIONS
Q
Q
in String Instructions
I U/W I BIT I
i .............. Integer Type Field
B=OO (Byte)
00
•
......
Q
T = Translated
B=Backward
W=01 (Word)
D = 11 (Double Word)
U/W=OO: None
01: While Match
f .............. Floating-Point Type Field
F=1 (Standard Floating: 32 bits)
11: Until Match
L=O (Long Floating: 64 bits)
c ............. Custom Type Field
D = 1 (Double Word)
Configuration bits, in SETCFG:
Q=O (Quad Word)
op ............ Operation Code
Valid encodings shown with each format.
TL/EE/6156-63
gen, gen1,
gen2 .......... General Addressing Mode Field.
See Section 2.2 for encodings.
reg ........... General Purpose Register Number
7
0
cond
cond .......... Condition Code Field
0000= EQual: Z=1
FormatO
(BR)
Bcond
0001 = Not Equal: Z=O
0010=Carry Set: C= 1
0011 = Carry Clear: C = 0
7
1 ,
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110=Greater Than: N= 1
0111 = Less or Equal: N=O
1000= Flag Set: F= 1
1011 = Higher or Same: L=1 orZ=1
1100= Less Than: N=O and Z=O
1101 = Greater or Equal: N = 1 or Z= 1
~p
, 10' 0 '1,:1
Format 1
-0000
ENTER
-0001
EXIT
-0010
NOP
-0011
WAIT
-0100
DIA
-0101
FLAG
-0110
SVC
-0111
BPT
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
1001 = Flag Clear: F=O
1010= LOwer: L=O and Z=O
11 0 1 0
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
1110= (Unconditionally True)
1111 = (Unconditionally False)
short .......... Short Immediate Value. May contain:
quick:
cond:
15
1 ,
Signed 4-bit value, in MOVQ,
ADDQ,CMPQ,ACB
Condition Code (above), in
Scond.
areg:
ADDQ
CMPQ
SPR
Scond
CPU Dedicated Register, in
LPR, SPR.
OOOO=US
0001-0111 = (Reserved)
1000=FP
1001 =SP
1010=SB
1011 = (Reserved)
1100 = (Reserved)
1101 =PSR
1110= INTBASE
1111 =MOD
2-473
, ,
gen
al7
,
Sh~rt
Format 2
-000
ACB
-001
MOVQ
-010
LPR
-011
,,
1 op
11 I 1 1
; 01
-100
-101
-110
....
C) .-------------------------------------------------------------------------------~
~
Appendix A: Instruction Formats (Continued)
z
11001110
gen 1
Format 3
CXPD
BICPSR
JUMP
BISPSR
-0000
-0010
-0100
-0110
o
8 7
23
(/)
Format 7
-1010
-1100
-1110
ADJSP
JSR
CASE
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
Trap (UND) on XXX1, 1000
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
DIV
iii
op
123
16 115
Format 4
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
FormatS
o
23
o0
TUEE/6156-64
-1000
-1001
-1010
-1100
-1101
-1110
SUB
ADDR
AND
SUBC
TBIT
XOR
0 0 0
i
-000
-001
-010
-011
EXT
CVTP
INS
CHECK
0 000 1 1 1 0
23
SETCFG
SKPS
8 7
1sb5
gen 1
Format 5
- 0000
MOVS
-0001
CMPS
Trap (UND) on 1XXX, 01XX
-100
-101
INDEX
FFS
I
gen2
-0010
-0011
I II
op
f
i
0
o0
1 1 1 1 1 0
Format 9
MOVif
LFSR
MOVLF
MOVFL
0
-000
-001
-010
-011
ROUND
TRUNC
SFSR
FLOOR
-100
-101
-110
-111
00111 0
~~:I:
Format 6
1 1 1 1 1 1
:1
TUEE/6156-65
ROT
ASH
CBIT
CBITI
Trap (UND)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
NEG
Trap (UND)
SUBP
ABS
COM
IBIT
ADDP
-1000
-1010
-1011
-1100
-1101
-1110
-1111
Format 10
Trap (UND) Always
Trap (UND) on all others
2-474
z
en
w
Appendix A: Instruction Formats (Continued)
23
gen1
I
gen2
I
op
o
o
o
8 7
16115
N
817, , , , , , ,01
cp
....
o
nnn10110
10lf10111110
Operation Word
10 Byte
Format 11
AOOf
MOVf
CMPf
Trap (Slave)
SUBf
NEGf
Trap (UNO)
Trap (UNO)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
-1000
-1001
-1010
-1011
-1100
-1110
-1110
-1111
OIVf
Trap (Slave)
Trap (UNO)
Trap (UNO)
MULf
ABSf
Trap (UNO)
Trap (UNO)
Format 15
(Custom Slave)
Operation Word Format
nnn
23
1 ,
000
i
i
gen 1
Format 15.0
-0000
-0001
CATSTO
CATST1
12~ , , ,
gen 1
001
-0010
-0011
LCR
SCR
,
I
,16115,
gen2
, ,
I
op
Ic I : 81
Format 12
Format 15.1
Trap (UNO) Always
--- 7 I I
___ 1 0
1
I I I I I
a
1 1 1 1
01
a
12~
TL/EE/6156-77
101
Format 13
8 7
16115
gen 1
I short
, ,
gen 1
,
,
1
-100
-101
-110
-111
CCV2
CCV1
SCSR
CCVO
,16115,
gen2
I
,,
op
,
1 x 1 :1
Format 15.5
Trap (UNO) Always
23
-000
-001
-010
-011
CCVS
LCSR
CCV5
CCV4
01
op
Ii
o
00011110
Format 14
Trap (UNO) Always
2-475
-0000
CCALS
-1000
CCALO
-0001
-1001
CMOVO
CMOVS
-0010
-1010
Trap (UNO)
CCMPO
-1011
-0011
Trap (UNO)
CCMP1
-0100
-1100
CCAL1
CCAL2
-0101
-1101
CMOV1
CMOV2
Trap (UNO)
-1110
Trap (UNO)
-0110
-1111
Trap (UNO)
-0111
Trap (UNO)
If nnn=010, 011, 100, 110,111, then Trap (UNO) Always
fill
.... r---------------------------------------------------------------------------------,
C)
-
Appendix A: Instruction Formats (Continued)
~
z
Implied Immediate Encodings:
---
r
I I I I I I I
___ 0 1 0 1 1
0
1 1 0
1
r6
TLlEE/6156-78
Format 16
r5
r4
r3
r2
rl
Register Mask, appended to SAVE, ENTER
Trap (UNO) Always
r1
---
r
r2
rS
r4
r6
r5
Register Mask, appended to RESTORE, EXIT
I I I I I I I0
___ 1 1 0 1 1 1 1 0 1
I'
TL/EE/6156-79
Format 17
: offset :
+
len9
-1
Offset/Length Modifier, appended to INSS, EXTS
Trap (UNO) Always
0
171 I 0 I 0 I 0 I 1 I 1 I 1 I 0 1
TL/EE/6156-80
Format 18
Trap (UNO) Always
0
0 0 1 1 ~
I I I I I I I
___ 17x x x
1
TL/EE/6156-81
Format 19
Trap (UNO) Always
2-476
°1
Section 3
Slave Processors
•
Section 3 Contents
NS32382-10, NS32382-15 Memory Management Units (MMU) ...........................
NS32082-10 Memory Management Unit (MMU) ........................................
NS32381-15, NS32381-20 Floating-Point Units.........................................
NS32081-10, NS32081-15 Floating-Point Units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..
NS32580-20, NS32580-25, NS32580-30 Floating-Point Controllers .......................
3·2
3-3
3-42
3-81
3-111
3-128
,---------------------------------------------------------------------, z
~National
PRELIMINARY
~ Semiconductor
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NS32382-10/NS32382-15
Memory Management Units
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General Description
Features
The NS32382 Memory Management Unit (MMU) provides
hardware support for demand-paged virtual memory implementations. The NS32382 functions as a slave processor in
Series 32000 microprocessor-based systems. Its specific
capabilities include fast dynamic translation, protection, and
detailed status to assist an operating system in efficiently
managing up to 4 Gbytes of physical memory. Support for
multiple address spaces, virtual machines, and program debugging is provided.
II Compatible with the NS32332 CPU
• Totally automatic mapping of 4 Gbyte virtual address
space using memory based tables
II On-chip translation look-aside buffer allows 97% of
translations to occur in one clock for most applications
II Full hardware support for virtual memory and virtual
machines
II Implements "referenced" bits for simple, efficient working set management
III Protection mechanisms implemented via access level
checking and dual space mapping
• Program debugging support
III Dedicated 32-bit physical address bus
II Non-cacheable page support
III 125-pin PGA (Pin grid array) package
High-speed address translation is performed on-chip
through a 32-entry fully associative translation look-aside
buffer (TLB), which maintains itself from tables in memory
with no software intervention. Protection violations and
page faults (references to non-resident pages) are automatically detected by the MMU, which invokes the instruction
abort feature of the CPU.
Additional features for program debugging include three
breakpoint registers which provide the programmer with
powerful stand-alone debugging capability.
U1
Conceptual Address Translation Model
r----.,
VIRTUAL ADDRESS--.. . - - - - - . PHYSICAL ADDRESS ... . - - - - - ,
...
...
NS32332
CPU
ADDRESS STROBE
NS32382
FLOAT
MMU
ADDRESS STROBE
PHYSICAL
MEMORY
ABORT
TL/EE/9142-1
3-3
•
. r---------------------------------------------------------------------------------,
Table Of Contents
,...
U)
N
CIO
Cf)
N
Cf)
(f)
Z
......
.
o
,...
1.0 PRODUCT INTRODUCTION
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.5 Translation Exception Address Register (TEAR)
1.1 Programming Considerations
2.0 FUNCTIONAL DESCRIPTION
3.6 Bus Error Address Register (BEAR)
N
2.1 Power and Grounding
3.7 Breakpoint Address Register (BAR)
Cf)
2.2 Clocking
3.B Breakpoint Mask Register (BMR)
CIO
N
Cf)
(f)
Z
2.3 Resetting
3.9 Breakpoint Data Register (BDR)
2.4 Bus Operation
3.10 Memory Management Control Register (MCR)
3.11 Memory Management Status Register (MSR)
2.4.1 Interconnections
2.4.2 CPU-Initiating Cycles
3.12 Translation Lookaside Buffer (TLB)
2.4.3 MMU-Initiated Cycles
3.13 Address Translation Algorithm
2.4.4 Cycle Extension
3.14 Instruction Set
2.4.5 Bus Retry
4.0 DEVICE SPECIFICATIONS
2.4.6 Bus Error
4.1 Pin Descriptions
2.4.7 Interlocked Bus Transfers
4.1.1 Supplies
2.5 Slave Processor Interface
4.1.2 Input Signals
2.5.1 Slave Processor Bus Cycles
4.1.3 Output Signals
2.5.2 Instruction Protocols
4.1.4 Input-Output Signals
2.6 Bus Access Control
4.2 Absolute Maximum Ratings
2.7 Breakpointing
4.3 Electrical Characteristics
3.0 ARCHITECTURAL DESCRIPTION
4.4 Switching Characteristics
3.1 Programming Model
4.4.1 Definitions
3.2 Memory Management Functions
4.4.2 Timing Tables
3.2.1 Page Table Structure
4.4.2.1 Output Signals; Internal
3.2.2 Virtual Address Spaces
Propagation Delays
4.4.2.2 Input Signal Requirements
3.2.3 Page Table Entry Formats
3.2.4 Physical Address Generation
4.4.2.3 Clocking Requirements
3.3 Page Table Base Registers (PTBO, PTBI)
Appendix A: Interfacing Suggestions
3.4 Invalidate Virtual Address Registers (IVARn)
List of Illustrations
The Virtual Memory Model.. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ...
1-1
NS323B2 Address Translation Model ........................................................................... 1-2
Recommended Supply Connections. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. .. . . . . . . . .. . . . . .. . . . . . . . . . .. . . . . . . . . . . ... 2-1
Clock Timing Relationships . . . .. .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .... 2-2
Power-On Reset Requirements ................................................................................ 2-3
General Reset Timing. .. .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . .. .. . .. .. . . . . .. . . .. . . . . . . . . . . . . . . . . . .. . ... 2-4
Recommended Reset Connections. Memory Managed System. . . • . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .. .. . .... 2-5
CPU Read Cycle; Translation in TLB .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
Abort Resulting from Protection Violation or a Breakpoint; Translation in TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-7
Page Table Lookup. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-B
Abort Resulting After a Page Table Lookup .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
Slave Access Timing; CPU Reading from MMU.................................................................. 2-10
Slave Access Timing; CPU Writing to MMU ..................................................................... 2-11
FLT Deassertation During RDVALlWRVAL Execution. . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . .. . . . . . . . ... 2-12
Two-Level Page Tables. . . . . . .. .. . . . . . . . .. . . . . . . • . . . . . .. . . . . . . . . . .. . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. .. ... 3-1
Page Table Entries ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Virtual to Physical Address Translation . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Page Table Base Registers (PTBO, PTB1) ....................................................................... 3-4
Invalidate Virtual Address Registers (IVARO, IVAR1) .............................................................. 3-5
Breakpoint Registers (BAR, BMR, BDR) . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-4
z
(J)
List of Illustrations (Continued)
c;,)
N
Memory Management Control Register (MCR) ................................................................... 3-7
Memory Managment Status Register (MSR) ..................................................................... 3-8
TLB Model .................................................................................................. 3-9
Slave Instruction Format..................................................................................... 3-10
Pin Grid Array Package. . . . . .. . .. . . . . . . .. . . . . . . . . . .. . . . . .. . . .. .. . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. .. . .. . . . . . . ..
Timing Specification Standard (Signal Valid After Clock Edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Timing Specification Standard (Signal Valid Before Clock Edge) ........................... . . . . . . . . . . . . . . . . . . . . . . . ..
CPU Write Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MMU Read Cycle Timing After a TLB Miss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MMU Write Cycle Timing After a TLB Miss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FLT Deassertation Timing ........... . . . . . . .. . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . • .. . . . . . . . . . . . . . . . . . . . . . ...
Abort Timing (FLT = 1) .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ...
Abort Timing (FLT = 0) ... . . . . . . .. . . . . . . . . . . . . . . . .. . . .. . . . . .. . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . .. . . .. . . . . . . . . ...
Bus Retry Timing. . . .. . . . . . .. . . . . . . . . .. .. . . . . . . . .. . . . . . . . . .. . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . ..
Bus Error Timing .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Access Timing; CPU Reading from MMU. . . .. . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
Slave Access Timing; CPU Writing to MMU .....................................................................
SDONETiming .............................................................................................
HOLD Timing (FLT = 0) .....................................................................................
HOLD Timing (FLT = 1) .....................................................................................
Clock Waveforms ...........................................................................................
NON Power-On Reset Timing. . . . . . . . . . .. . . . . .. . . . . . . . .. . . . . .. .. . .. . . . . .. .. . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . ...
Power-On Reset ................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
c;,)
CO
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.......
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(J)
c;,)
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c;,)
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......
U1
System Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-1
Tables
STO-ST3 Encodings..........................................................................................
LMR Instruction Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
SMR Instruction Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RDVAL/WRVAL Instruction ProtocoL...........................................................................
2-1
2-2
2-3
2-4
Access Protection Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
"Short" Field Encodings ...................................................................................... 3-2
•
3-5
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1.0 Product Introduction
Figure 1-2. The offset is not changed. The translated page
The NS32382 MMU provides hardware support for three
basic features of the Series 32000; dynamic address translation, access level checking and software debugging. Dynamic Address Translation is required to implement demand-paged virtual memory. Access level checking is performed during address translation, ensuring that unauthorized accesses do not occur. Because the MMU resides on
the local bus and is in an ideal location to monitor CPU
activity, debugging functions are also included.
The MMU is intended for use in implementing demandpaged virtual memory. The concept of demand-paged virtual memory is illustrated in Figure 1-1. At any point in time, a
program sees a uniform addressing space of up to 4 gigabytes (the "virtual" space), regardless of the actual size of
the memory physically present in the system (the "physical"
space). The full virtual space is recorded as an image on a
mass storage device. Portions of the virtual space needed
by a running program are copied into physical memory when
needed.
To make the virtual information directly available to a running program, a mapping must be established between the
virtual addresses asserted by the CPU and the physical addresses of the data being referenced.
To perform this mapping, the MMU divides the virtual memory space into 4 Kbyte blocks called "pages". It interprets
the 32-bit address from the CPU as a 20-bit "page number"
followed by a 12-bit offset, which indicates the position of a
byte within the selected page. Similarly, the MMU divides
the physical memory into 4 Kbyte frames, each of which can
hold a virtual page.
The translation process is therefore modeled as accepting a
virtual page number from the CPU and substituting the corresponding physical page frame number for it, as shown in
frame number is 20 bits long. Physical addresses issued by
the MMU are 32 bits wide.
TL/EE/9142-3
FIGURE 1-2. NS32382 Address Translation Model
Generally, in virtual memory systems the available physical
memory space is smaller than the maximum virtual memory
space. Therefore, not all virtual pages are simultaneously
resident. Nonresident pages are not directly addressable by
the CPU. Whenever the CPU issues a virtual address for a
nonresident or nonexistent page, a "page fault" will result.
The MMU Signals this condition by invoking the Abort feature of the CPU. The CPU then halts the memory cycle,
restores its internal state to the point prior to the instruction
being executed, and enters the operating system through
the abort trap vector.
PHYSICAL
MEMORY
VIRTUAL
MEMORY
HIGH
a..._ _ _ _ _..... MEMORY
ADDRESS
HIGH
MEMORYa...-----.....
ADDRESS
MASS STORAGE
TL/EE/9142-2
FIGURE 1-1_ The Virtual Memory Model
3-6
1.0 Product Introduction (Continued)
The operating system reads from the MMU the virtual address which caused the abort. It selects a page frame which
is either vacant or not recently used and, if necessary,
writes this frame back to mass storage. The required virtual
page is then copied into the selected page frame.
The MMU is informed of this change by updating the page
tables (Section 3.2), and the operating system returns control to the aborted program using the RETT instruction.
Since the return address supplied by the abort trap is the
address of the aborted instruction, execution resumes by
retrying the instruction.
This sequence is called paging. Since a page fault encountered in normal execution serves as a demand for a given
page, the whole scheme is called demand-paged virtual
memory.
The MMU also provides debugging support. It may be programmed to monitor the CPU bus for a single or a range of
virtual addresses in real time.
rewrite the result into the source operand exactly, if page
faults are being generated only by invalid pages and not
by write protection violations (for example, the instruction
"ABSW X, X", which replaces X with its absolute value).
Also, never write to any memory location which is necessary for calculating the effective address of either operand (i.e. the pointer in "Memory Relative" addressing
mode; the Link Table pointer or Link Table Entry in "External" addressing mode).
b) No instruction should perform a conversion in place from
one data type to another larger data type (Example:
MOVWF X, X which replaces the IS-bit integer value in
memory location X with its 32-bit floating-point value).
The addressing mode combination "TOS, TOS" is an exception, and is allowed. This is because the least-significant part of the result is written to the possibly invalid
page before the source operand is affected. Also, integer
conversions to larger integers always work correctly in
place, because the low-order portion of the result always
matches the source value.
c) When performing the MOVM instruction, the entire
source and destination blocks must be considered "operands" as above, and they must not overlap.
1.1 PROGRAMMING CONSIDERATIONS
When a CPU instruction is aborted as a result of a page
fault, some memory resident data might have been already
modified by the instruction before the occurrence of the
abort.
This could compromise the restartability of the instruction
when the CPU returns from the abort routine.
To guarantee correct results following the re-execution of
the aborted instruction, the following actions should not be
attempted:
a) No instruction should try to overlay part of a source operand with part of the result. It is, however, permissible to
2.0 Functional Description
2.1 POWER AND GROUNDING
The NS323B2 requires a single 5V power supply, applied on
eight (Veel pins. These pins should be connected together
by a power (Vee) plane on the printed circuit board. See
Figure 2-1.
The grounding connections are made on eighteen (GND)
pins.
+5V
84 GND
83
C4
C8
Vee C7
• C9
M7
85
Cl0
•
L3
NS32382
L12
Vee M13
Cll
C13
K12
t.t2
N2
.......___.....+-......-+.....-4I---o4~.....+-___......_ .....-+OTHER GROUND
CONNECTION
TLlEE/9142-4
Cl
C2
=
=
1 I'F, Tantalum.
1000 pF,low inductance. This should be either a disc or monolithic ceramic capaCitor.
FIGURE 2·1. Recommended Supply Connections
3-7
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2.0 Functional Description (Continued)
These pins should be connected together by a ground
(GND) plane on the printed circuit board.
Each rising edge of PHil defines a transition in the timing
state (UT-State") of the MMU. One T-State represents one
hardware cycle within the MMU, and/or one step of an external bus transfer. See Section 4 for complete specifications of PHil and PHI2.
As the TCU presents signals with very fast transitions, it is
recommended that the conductors carrying PHil and PHI2
be kept as short as possible, and that they not be connected to any devices other than the CPU and MMU. A TTL
Clock signal (CTTL) is provided by the TCU for all other
clocking.
In addition to Vee and Ground, the NS32382 MMU uses an
internally-generated negative voltage (BBG), output of the
on-chip substrate voltage generator. It is necessary to filter
this voltage externally by attaching a pair of capacitors (Figure 2-1) from the BBG pin to ground.
2.2 CLOCKING
The NS32382 inputs clocking signals from the NS32301
Timing Control Unit (TCU), which presents two non-overlapping phases of a single clock frequency. These phases are
called PHil (pin B8) and PHI2 (pin B9). Their relationship to
each other is shown in Figure 2-2.
2.3 RESETTING
The RSTI input pin is used to reset the NS32382. The MMU
responds to RSTI by terminating processing, resetting its
internal logic and clearing the MCR and MSR registers.
Only the MCR and MSR registers are changed on reset. No
other program accessible registers are affected.
The RST/ ABT signal is activated by the MMU on reset. This
Signal should be used to reset the CPU.
PHil
On application of power, RSTI must be held low for at least
50 '""S after Vee is stable. This is to ensure that all on-Chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 clock cycles. See Figures 2·3 and 2-4.
The NS32C201 Timing Control Unit (TCU) provides circuitry
to meet the Reset requirements of the NS32382 MMU. Figure 2-5 shows the recommended connections.
PHI2
TLlEE/9142-5
FIGURE 2-2. Clock Timing Relationships
PHI'
I---
vec
iiiii ---,~
.........m
-+__
PHI' _ _
I
264CLOCK-i
C~CLES
~
TL/EE/9142-7
FIGURE 2·4. General Reset Timing
iiSii
---+---------U·--'I
~------e~~MC------~
TL/EE/9142-6
FIGURE 2·3. Power·On Reset Requirements
Vee
NS32C201
TCU
NS32382
MMU
NS32332
CPU
r---------,I
I
iiffif
.J>--t-f-......; -.....~-....--+I
IL _________ .JI
I
RSTI
RSTO
EXTERNAL RESET
(OPTIONAL)
2:50pSlC
RESET SWITCH
(OPTIONAL)
TL/EE/9142-6
FIGURE 2·5. Recommended Reset Connections, Memory·Managed System
3-8
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2.0 Functional Description
(J)
(0)
(Continued)
N
The DDIN line indicates the direction of the transfer: 0 =
Read, 1 = Write.
2.4 BUS OPERATION
2.4.1 Interconnections
DDIN is monitored by the MMU during CPU cycles to detect
write operations, and is driven by the MMU during MMU-initiated bus cycles.
The U/S pin indicates the privilege level at which the CPU is
making the access: 0 = Supervisor Mode, 1 = User Mode.
It is used by the MMU to select the address space for translation and to perform protection level checking. Normally,
the U/S pin is a direct reflection of the U bit in the CPU's
Processor Status Register (PSR). The MOVUS and MOVSU
CPU instructions, however, toggle this pin on successive
operand accesses in order to move data between virtual
spaces.
The MMU uses the FLT line to take control of the bus from
the CPU. It does so as necessary for updating its internal
TLB from the Page Tables in memory, and for maintaining
the contents of the status bits (R and M) in the Page Table
Entries.
The MMU also aborts invalid accesses attempted by the
CPU. This is done by pulsing the RST / ABT pin low for one
clock period. (A pulse longer than one clock period is interpreted by the CPU as a Reset command.)
The MMU runs synchronously with the CPU, sharing with it a
single multiplexed address/data bus. The interconnections
used by the MMU for bus control, when used in conjunction
with the NS32332, are shown in Figure A-1 (Appendix A).
The CPU issues 32-bit virtual addresses on the bus, and
status information on other pins, pulsing the signal ADS low.
These are monitored by the MMU. The MMU issues 32-bit
physical addresses on the Physical Address bus, pulsing the
PAV line low. The PAV pulse triggers the address latches
and signals the NS32C201 TCU to begin a bus cycle. The
TCU in turn generates the necessary bus control signals
and synchronizes the insertion of WAIT states, by providing
the signal RDY to the MMU and CPU. Note that it is the
MMU rather than the CPU that actually triggers bus activity
in the system.
The functions of other interface signals used by the MMU to
control bus activity are described below.
The STO-ST3 pins indicate the type of cycle being initiated
by the CPU. STO is the least-significant bit of the code. Table 2-1 shows the interpretations of the status codes presented on these lines.
2.4.2 CPU-Initiated Bus Cycles
A CPU-initiated bus cycle is performed in a minimum of four
clock cycles: Tl, T2, T3 and T4, as shown in Figure 2-6.
Status codes that are relevant to the MMU's function during
a memory reference are:
1000, 1001 Instruction Fetch status, used by the debugging features to distinguish between data and
instruction references.
1010
Data Transfer. A data value is to be transferred.
1011
Read RMW Operand. Although this is always
a Read cycle, the MMU treats it as a Write
cycle for purposes of protection and breakpointing.
1100
Read for Effective Address. Data used for address calculation is being transferred.
During period Tl, the CPU places the virtual address to be
translated on the bus, and the MMU latches it internally and
begins translation. The MMU also sa~ples the DDIN pin,
the status lines STO-ST3, and the U/S pin in the previous
T4 cycle to determine how the CPU intends to use the bus.
During period T2 the CPU removes the virtual address from
the bus and the MMU takes one of three actions:
1) If the translation for the virtual address is resident in the
MMU's TLB, and the access being attempted by the CPU
does not violate the protection level of the page being
referenced, the MMU presents the translated address on
PAO-PA31 and generates a PAV pulse to trigger a bus
cycle in the rest of the system. See Agure 2-6.
2) If the translation for the virtual address is resident in the
MMU's TLB, but the access being attempted by the CPU
is not allowed due to the protection level of the page
being referenced, the MMU generates a pul~n the
RST/ABT pin to abort the CPU's access. No PAV pulse
is generated. See Figure 2-7.
3) If the translation for the virtual address is not resident in
the TLB, or if the CPU is writing to a page whose M bit is
not yet set, the MMU takes control of the bus asserting
the FLT signal as shown in Figure 2-8. This causes the
CPU to float its bus and wait. The MMU then initiates a
sequence of bus cycles as described in Section 2.4.3.
The MMU ignores all other status codes. The status
codes 1101, 1110 and 1111 are also recognized by the
MMU in conjunction with pulses on the SPC line while it is
executing Slave Processor instructions, but these do not
occur in a context relevant to address translation.
TABLE 2-1. STO-ST3 Encodings
(STO is the Least Significant)
0000 -Idle: CPU Inactive on Bus
0001 -Idle: WAIT Instruction
0010- (Reserved)
0011 - Idle: Waiting for Slave
0100 -Interrupt Acknowledge, Master
0101 -Interrupt Acknowledge, Cascaded
0110- End of Interrupt, Master
0111 - End of Interrupt, Cascaded
1000 - Sequential Instruction Fetch
1001 - Non-Sequential Instruction Fetch
1010- Data Transfer
1011 - Read Read-Modify-Write Operand
1100 - Read for Effective Address
1101 - Transfer Slave Operand
1110 - Read Slave Status Word
1111 - Broadcast Slave ID and Operation Word
From state T2 through T4 data is transferred on the bus
between the CPU and memory, and the TCU provides the
strobes for the transfer.
Whenever the MMU generates an Abort pulse on the
RST/ABT pin, the CPU enters state T3 and then Ti (idle),
ending the bus cycle. Since no PAV pulse is issued by the
MMU, the rest of the system remains unaware that an access has been attempted.
3-9
.
(0)
CI)
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(J)
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(0)
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2.0 Functional Description
(Continued)
Figure 2-8 shows the sequence of events in a Page Table
lookup. After asserting FLT, the MMU waits for one additional clock cycle, then reads the Level-1 Page Table Entry and
the Level-2 Page Table Entry in two consecutive memory
Read cycles. There are no idle clock cycles between MMUinitiated bus cycles unless a bus request is made on the
HOLD line (Section 2.6).
2.4.3 MMU-Inltlated Cycles
Bus cycles initiated by the MMU are always nested within
CPU-initiated bus cycles; that is, they appear after the MMU
has accepted a virtual address from the CPU and has set
the FLT line active. The MMU will initiate memory cycles in
the following cases:
1) There is no translation in the MMU's TLB for the virtual
address issued by the CPU, meaning that the MMU must
reference the Page Tables in memory to obtain the translation.
During the Page Table lookup the MMU driv~s the DDIN
Signal. The status lines STO-ST3 and the U/S pin are not
released by the CPU, and retain their original settings while
the MMU uses the bus. The Byte Enable signals from the
CPU, BEO-BE3, should be handled externally for correct
memory referencing.
2) There is a translation for that virtual address in the TLB,
but the page is being written for the first time (the M bit in
its Level-2 Page Table Entry is 0). The MMU treats this
case as if there were no translation in the TLB, and performs a Page Table lookup in order to set the M bit in the
Level-2 Page Table Entry as well as in the TLB.
In the clock cycle immediately after T4 of the last lookup
cycle, the MMU issues the translated address and pulses
MADS. In the subsequent cycle it removes FLT and pulses
PAY to continue the CPU's access.
Having made the necessary memory references, the MMU
either aborts the CPU access or it provides the translated
address and allows the CPU's access to continue to T3.
T4 OR Ti
T1
T2
T3
T4
Tl OR TI
PHI1 [
PHI2 [
AOO-31 [
PAO-ll [
PA12-31 [
ADS [
PAY [
ODIN [
FLT [
(HIGHI
Uts [
STO-3 [
TlIEE/9142-9
FIGURE 2-6. CPU Read Cycle; Translation In TLB (TLB Hit)
3-10
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2.0 Functional Description
I
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(Continued)
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T2
PHil [
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TLlEE/9142-10
Note
t: The CPU drives the bus if a write cycle is aborted.
FIGURE 2-7. Abort Resulting from Protection Violation or a Breakpoint; Translation in TLB
CPU ACCESS
PTE.1
CPU ACCESS
PTE.2
CPU STATES
MMUSTATES
T2
T3
"
T4
r,
13
T4
T2
13
T4
PHI1
PH12
lOBUS
MBUS
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121
Note
t: If the R bit on the Level-1 PTE must be set, a write cycle is inserted here.
Note 2: If either the R or the M bit on the Level-2 PTE must be set, a write cycle is inserted here.
FIGURE 2-8. Page Table Lookup
3-11
TL/EE/9142-11
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2.0 Functional Description
(Continued)
If the V bit (Bit 0) in any of the Page Table Entries is zero, or
the protection level field PL (bits 1 and 2) indicates that the
CPU's attempted access is illegal, the MMU does not generate any further memory cycles, but instead issues an Abort
pulse during the clock cycle after T 4 and removes the FLT
signal.
bus cycle, CPU-initiated or MMU-initiated, can be extended,
except Slave Processor cycles, which are not memory or
peripheral references.
In Figures 2-6 and 2-8, note that during T3 all bus control
signals are flat. Therefore, a bus cycle can be cleanly extended by causing the T3 state to be repeated. This is the
purpose of the ROY (Ready) pin.
If the Rand/or M bit (bit 7 or 8) must be updated, the MMU
does this immediately in a single Write cycle. All bits except
those updated are rewritten with their original values.
In the middle of T3, on the falling edge of clock phase PHil,
the ROY line is sampled by the CPU and/or the MMU. If
ROY is high, the next state after T3 will be T4, ending the
bus cycle. If it is low, the next state after T3 will be another
T3 and the ROY line will be sampled again. ROY is sampled
in each following clock period, with insertion of additional T3
states, until it is sampled high. Each additional T3 state inserted is called a "WAIT state".
At most, the MMU writes two double words to memory during a translation: the first to the Level-1 table to update the
R bit, and the second to the Level-2 table to update the R
and/ or M bits.
2.4.4 Cycle Extension
To allow sufficient strobe widths and access time requirements for any speed of memory or peripheral device, the
NS32382 provides for extension of a bus cycle. Any type of
The ROY pin is driven by the NS32C201 Timing Control
Unit, which applies WAIT states to the CPU and MMU as
requested on its own WAIT request input pins.
READ PTE
MMU STATES
Tl
T2
T3
T4
T1
TI
PHil [
PHI2 [
PAD-31 [
ADD-31 [
MADS [
PAV
FLT
iiii
RSTIABT [
ROY
MILO [
TLIEE19142-12
FIGURE 2·9. Abort Resulting after a Page Table Lookup
3-12
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2.0 Functional Description
U)
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(Continued)
N
from the CPU. MILO is asserted in the clock cycle immediately before the Read·Modify-Write access and de·activated
in the clock cycle following T4 of the write cycle.
The write portion of the Read·Modify-Write access will not
be executed if anyone of the following conditions occurs:
(1) A bus error has occurred in the read portion of the interlocked access.
(2) The Rand/or M bit(s) in the PTE(s) do not require updating.
(3) A protection violation has occurred.
(4) An invalid PTE is detected.
If a bus retry is encountered in an interlocked access, MILO
will continue to be asserted, and the access will be retried.
2.4.5 Bus Retry
The Bus Retry input signal (BRT) provides a system with the
capability of repeating a bus cycle upon the occurrence of a
"soft" or correctable error. The system first determines that
a correctable error has occurred and then activates the BRT
input. The MMU then samples this input on the falling edge
of PHI1 in both T3 and T4 of a bus cycle. A valid bus retry
will be issued as a result of a low being sampled in both T3
and T4.
If the MMU gets a Bus Retry when it is contrOlling the bus, it
will re-run the bus cycle until BRT is deactivated.
Any Pending Hold request will not be acknowledged by the
MMU if a bus retry is detected and during Hold Acknowledge, the MMU will not recognize the Bus Retry signal.
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2.5 SLAVE PROCESSOR INTERFACE
The CPU and MMU execute four instructions cooperatively.
These are LMR, SMR, RDVAL and WRVAL, as described in
Section 2.5.2. The MMU takes the role of a Slave Processor
in executing these instructions, accepting them as they are
issued to it by the CPU. The CPU calculates all effective
addresses and performs all operand transfers to and from
memory and the MMU. The MMU does not take control of
the bus except as necessary in normal operation; i.e., to
translate and validate memory addresses as they are presented by the CPU.
The sequence of transfers ("protocol") followed by the CPU
and MMU involves a special type of bus cycle performed by
the CPU. This "Slave Processor" bus cycle does not involve
the issuing of an address, but rather performs a fast data
transfer whose purpose is pre-determined by the form of the
instruction under execution and by status codes asserted by
the CPU.
2.4.6 Bus Error
The Bus Error input signal BER will be activated (low) when
a "hard" or uncorrectable error occurs within the system
(e.g. bus timeout, double ECC error). BER will be sampled
on the falling edge of PHI1 in T4. If the MMU detects Bus
Error while it is controlling the bus, it will store the virtual
address which caused the error in the BEAR (Bus Error Ad·
dress Register), and set the ME bit in the MSR to indicate
MMU ERROR. An abort signal ABT will be generated and
further memory accesses by the MMU will be inhibited. The
32382 then returns bus control to the CPU by releasing the
FLT signal, (FLT = 1). Any pending Hold request will not be
acknowledged by the MMU if a bus error is detected.
If the Bus Error signal is received when the CPU is controlling the bus, the MMU will store the virtual address in BEAR,
and set the CE bit in the MSR to indicate CPU ERROR.
During the Hold Acknowledge, the MMU will ignore the BER
signal.
2.5.1 Slave Processor Bus Cycles
2.4.7 Interlocked Bus Transfers
Both the 32332 CPU and the 32382 MMU are capable of
executing interlocked cycles to access a stream of data
from memory without intervention from other devices.
The interconnections between the CPU and MMU for Slave
Processor communication are shown in Figure A-1 (Appendix A). The SPC signal is pulsed by the CPU as a low-active
data strobe for Slave Processor transfers. Since SPC is normally in a high-impedance state, it must be pulled high with
a 10 kfl. resistor, as shown. The MMU also monitors the
status lines STO-ST3 to follow the protocol for the instruction being executed.
Data is transferred between the CPU and the MMU with
Slave Processor bus cycles, illustrated in Figures 2-10 and
2-11. Each bus cycle transfers one double-word (32 bits) to
or from the MMU.
Before executing an interlocked access, the 32332 CPU
performs a dummy read with Read·Modify-Write status
(1011). The MMU handles the dummy read as if it were a
real RMW access. The TLB entries will be searched and
page table look-up will be performed if a miss occurs. The
access level is checked and the CPU will be aborted if write
privilege is not currently assigned. The Reference (R) and
the Modify (M) bits in the first and second level PTEs, as
well as those in the Translation look·aside Buffer, will be
updated. By executing the dummy read, the CPU is assured
of no MMU intervention when the actual interlocked access
is performed.
The 32382 MMU executes interlocked Read-Modify-Write
memory cycles to access Page Table Entries (PTEs) and
update the Reference (R) and Modify (M) bit in the PTEs
when necessary. If the Rand/or M bit(s) do not require
updating, the write portion of the RMW cycle will not be
executed. The memory cycles to access PTEs during execution of RDVAL and WRVAL instructions are not interlocked since Rand M bits are not updated.
Slave Processor bus cycles are performed by the CPU in
two clock periods, which are labeled T1 and T4. During T1,
the CPU activates SPC and, if it is writing to the MMU, it
presents data on the bus. During T4, the CPU deactivates
SPC and, if it is reading from the MMU, it latches data from
the bus. The CPU guarantees that data written to the MMU
is held through T4 to provide for the MMU's hold time requirements. The CPU also guarantees that the status code
on STO-ST3 becomes valid, at the latest, during the clock
period preceding T1. The status code changes during T4 to
antiCipate the next bus cycle, if any.
Note that Slave Processor bus cycles are never extended
with WAIT states. The RDY line is not sampled.
During interlocked access cycles, the MILO signal from the
MMU will be asserted. MILO has the same timing as ILO
3-13
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2.0 Functional Description
(Continued)
N
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NEXT CYCLE
PREY. CYCLE
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PHI2
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T40RTI
Tl
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T10RTi
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AOO-AD31
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[LfL&.L&.L&."fL- The PTE does not represent a valid translation. Any attempt to use this PTE will cause
the MMU to generate an Abort trap.
Level-2 Page Tables contain 1024 32-bit Page Table entries, and so occupy 4 Kbytes (1 page). Each Level·2 Page
Table Entry points to a final 4 Kbyte physical page frame. In
other words, its PFN provides the Page Frame Number portion (bits 12-31) of the translated address (Figure 3-3). The
OFFSET field of the translated address is taken directly
from the corresponding field of the virtual address.
PL
Protection Level. This two-bit field establishes the
types of accesses permitted for the page in both User
Mode and Supervisor Mode, as shown in Table 3-1.
The PL field is modified only by software. In a Level-1
PTE, it limits the maximum access level allowed for all
pages mapped through that PTE.
TABLE 3-1. Access Protection Levels
3.2.2 Virtual Address Spaces
When the Dual Space option is selected for address transla·
tion in the MCR (Sec. 3.10) the MMU uses two maps: one
for translating addresses presented to it in Supervisor Mode
and another for User Mode addresses. Each map is referenced by the MMU using one of the two Page Table Base
registers: PTBO or PTB1. The MMU determines the CPU's
current mode by monitoring the state of the U/S pin and
applying the following rules.
Mode
1) While the CPU is in Supervisor Mode (U/S pin = 0), the
CPU is said to be presenting addresses belonging to Address Space 0, and the MMU uses the PTBO register as
its reference for looking up translations from memory.
2) While the CPU is in User Mode (U/S pin = 1), and the
MCR DS bit is set to enable Dual Space translation, the
CPU is said to be presenting addresses belonging to Address Space 1, and the MMU uses the PTB1 register to
look up translations.
01
10
11
1
no
access
no
access
read
only
full
access
Supervisor
0
read
only
full
access
full
access
full
access
NU
CI
R
Referenced. This is a status bit, set by the MMU and
cleared by the operating system, that indicates whether the page mapped by this PTE has been referenced
within a period of time determined by the operating
system. It is intended to assist in implementing memory allocation strategies. In a Level·1 PTE, the R bit
indicates only that the Level·2 Page Table has been
referenced for a translation, without necessarily implying that the translation was successful. In a Level-2
PTE, it indicates that the page mapped by the PTE
has been successfully referenced.
R = 1 => The page has been referenced since the R
bit was last cleared.
R = 0 => The page has not been referenced since the
R bit was last cleared.
3.2.3 Page Table Entry Formats
Figure 3-2 shows the formats of Level-1 and Level-2 Page
Table Entries (PTE's).
M
Modified. This is a status bit, set by the MMU whenever a write cycle is successfully performed to the page
mapped by this PTE. It is initialized to zero by the
operating system when the page is brought into physical memory.
The bits are defined as follows:
V
Valid. The V bit is set and cleared only by software.
V = 1 => The PTE is valid and may be used for trans·
lation by the MMU.
I"
1"+1
:
9 8
First Level PTE
PFN
I"
:USR:
00
Not Used. These bits are reserved by National for future enhancements. Their values should be set to
zero.
Cache Inhibit. This bit appears only in Level-2 PTE's.
It is used to specify non-cacheable pages.
Note: When the CPU executes a Dual·Space Move instruction (MOVUSi or
MOVSUi), it temporarily enters User Mode by switching the state of
the U/S pin. Accesses made by the CPU during this time are treated
by the MMU as User·Mode accesses for both mapping and access
level checking. It is possible, however, to force the MMU to assume
Supervisor-Mode privilege on such accesses by setting the Access
Override (AO) bit in the MCR (Sec. 3.10).
,J,
Protection Level Bits (PL)
User
3) If Dual Space translation is not selected in the MCR,
there is no Address Space 1, and all addresses present·
ed in both Supervisor and User modes are considered by
the MMU to be in Address Space O. The privilege level of
the CPU is used then only for access level checking.
PFN
U/S
I
12 11
:USR:
IMIRH
9 8
Second Level PTE
FIGURE 3-2. Page Table Entries (PTE's)
3-18
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3.0 Architectural Description
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(Continued)
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M = 1 => The page has been modified since it was
last brought into physical memory_
Bits 12-31 of the virtual address hold the 20-bit Page Number, which in the course of the translation is replaced with
the 20-bit Page Frame Number of the physical address. The
virtual Page Number field is further divided into two fields,
INDEX 1 and INDEX 2.
Bits 0-11 constitute the OFFSET field, which identifies a
byte's position within the accessed page_ Since the byte
position within a page does not change with translation, this
value is not used, and is simply echoed by the MMU as bits
0-11 of the final physical address.
M=O=> The page has not been modified since it
was last brought into physical memory.
In Level-1 Page Table Entries, this bit position is undefined, and is unaltered_
USR User bits_ These bits are ignored by the MMU and their
values are not changed.
They can be used by the user software.
PFN Page Frame Number. This 20-bit field provides bits
12-31 of the physical address. See Figure 3-3.
W
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The 10-bit INDEX 1 field of the virtual address is used as an
index into the Level-1 Page Table, selecting one of its 1024
entries. The address of the entry is computed by adding
INDEX 1 (scaled by 4) to the contents of the current Page
Table Base register. The PFN field of that entry gives the
base address of the selected Level-2 Page Table.
The INDEX 2 field of the virtual address (10 bits) is used as
the index into the Level-2 Page Table, by adding it (scaled
by 4) to the base address taken from the Level-1 Page Table Entry_ The PFN field of the selected entry provides the
entire Page Frame Number of the translated address.
3_2.4 Physical Address Generation
When a virtual address is presented to the MMU by the CPU
and the translation information is not in the TLB, the MMU
performs a page table lookup in order to generate the physical address.
The Page Table structure is traversed by the MMU using
fields taken from the virtual address. This sequence is diagrammed in Figure 3-3.
The offset field of the virtual address is then appended to
this frame number to generate the final physical address_
VIRTUAL ADDRESS
22 21
1211
31
L
I
31
INDEX 1
\
INDEX 2
OFFSET
I
... aPTB. \
L
INDEX 1
1211
\ DO
21
LEVEL-l PAGE TABLE
LEVEL-l PTE
t--
0
PFN
I USR I NU I
;r+~V
31
0
II) SELECT 1ST PTE
IF DS=O THEN
A=O
ELSE
• = 1 FOR USER MODE
• = 0 FOR SUPV MODE
t
1---,
I
I
I
I
1024
PTE.
I
4 BYTES-
... ",
PFN
31
I
1211
""
INDEX 2
~
PFN
I
000000000000
~
LEVEL-2 PAGE TABLE
LEVEL-2 PTE
r
00-:
21
0
PFN
IUSRI M I R I CIINUlpL\ V
31
0
1024
PTE.
12) SELECT 2ND PTE
PHYSICAL ADDRESS
I
31
......
PFN
I
12 11
""
OFFSET
13) GENERATE PHYSICAL
ADDRESS
TLlEE/9142-20
FIGURE 3-3. Virtual to Physical Address Translation
3-19
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3.0 Architectural Description
(Continued)
3.3 PAGE TABLE BASE REGISTERS (PTBD, PTB1)
3.8 BREAKPOINT MASK REGISTER (BMR)
The PTBn registers hold the physical addresses of the Level-1 Page Tables.
The Breakpoint Mask Register provides corresponding bit
positions for each of the virtual address bits that are to be
compared when the Breakpoint Address Compare Function
is enabled. Bits which are set in this register are used for
matching virtual address bits while bits which are cleared
are treated as "don't cares". This allows a breakpoint to be
generated upon an access to any location within a block of
addresses. The BMR Register format is shown in Figure 3-6.
The format of these registers is shown in Figure 3-4. The
least-significant 12 bits are permanently zero, so that each
register always points to a 4 Kbyte boundary in memory.
The PTBn registers may be loaded or stored using the MMU
Slave Processor instructions LMR and SMR (Section 3.14).
3.4 INVALIDATE VIRTUAL ADDRESS REGISTERS
(IVARD,IVAR1)
3.9 BREAKPOINT DATA REGISTER (BDR)
The Breakpoint Data Register holds the virtual address that
triggered the breakpoint.
The Invalidate Virtual Address registers are write-only registers. When a virtual address is written to IVARO or IVAR1
using the LMR instruction, the translation for that virtual address is purged, if present, from the TLB. This must be done
whenever a Page Table Entry has been changed in memory, since the TLB might otherwise contain an incorrect translation value.
It is a read-only register and its format is shown in Figure 3-6.
3.1D MEMORY MANAGEMENT CONTROL REGISTER
(MCR)
The MCR Register controls the various features provided by
the MMU. It is 32 bits in length and has the format shown in
Figure 3-7. All bits will be cleared on reset. The bits 8 to 31
are RESERVED for future use and must be loaded with zeros.
Another technique for purging TLB entries is to load a PTBn
register. This automatically purges all entries associated
with the addressing space mapped by that register. Turning
off translation (clearing the MCR TU and/or TS bits) does
not purge any entries from the TLB.
When MCR is read as a 32-bit word, bits 8 to 31 will be
returned as zeros. Details on the MCR bits are given below.
The format of the IVAR n registers is shown in Figure 3-5.
TU
3.5 TRANSLATION EXCEPTION ADDRESS REGISTER
(TEAR)
The TEAR Register is loaded when a translation exception
occurs. It contains the 32-bit virtual address which caused
the translation exception and is a read-only register. TEAR
has the same format as the IVARn registers of Figure 3-5.
Translate User·Mode Addresses. While this bit is "1",
the MMU translates all addresses presented while
the CPU is in User Mode. While it is "0", the MMU
echoes all User-Mode virtual addresses without performing translation or access level checking.
Note: Altering the TU bit has no effect on the contents of the TLB.
TS
For more details on the updating of TEAR, refer to the note
at the end of Section 3.11.
3.6 BUS ERROR ADDRESS REGISTER (BEAR)
The BEAR Register is loaded when a CPU or MMU bus
error occurs. It contains the 32-bit virtual address which triggered the bus error and is a read-only register. BEAR has
the same format as the IVARn registers of Figure 3-5.
Translate Supervisor-Mode Addresses. While this bit
is "1", the MMU translates all addresses presented
while the CPU is in Supervisor Mode. While it is "0",
the MMU echoes all Supervisor-Mode virtual addresses without translation or access level checking.
Note: Altering the TS bit has no effect on the contents of the TLB.
OS
3.7 BREAKPOINT ADDRESS REGISTER (BAR)
The Breakpoint Address Register is used to hold a virtual
address for breakpoint address comparison during instruction and operand accesses. It is 32 bits in length and its
format is shown in Figure 3-6.
Dual-Space Translation. While this bit is "1", Supervisor Mode addresses and User Mode addresses are
translated independently of each other, using separate mappings. While it is "0", both Supervisor Mode
addresses and User Mode addresses are translated
using the same mapping. See Section 3.2.2.
1: : : : :~O~+~+:2~+: ::::101+101+1+1+1+1
31
1211
FIGURE 3-4. Page Table Base Registers (PTBD, PTB1)
131: : : : : : : : : : :
0
~1~+HoH+: :::::::::::,1
FIGURE 3-5. Address Registers (IVARD, IVAR1, TEAR, BEAR)
FIGURE 3-6. Breakpoint Registers (BAR, BMR, BDR)
3-20
r--------------------------------------------------------------------------,
3.0 Architectural Description
AO
BR
BW
BE
(Continued)
Access Level Override. This bit may be set to temporarily cause User Mode accesses to be given Supervisor Mode privilege. See Section 3.13.
DDT Data Direction. This bit indicates the direction of the
transfer that the CPU was attempting when the translation exception occurred.
Break on Read. If BR is 1, a break is generated when
data is read from the breakpoint address. Instruction
fetches do not trigger a Read breakpoint. If BR is 0,
this condition is disabled.
DDT = 0 = > Read Cycle
DDT = 1 = > Write Cycle
UST User/Supervisor. This is the state of the U/S pin from
the CPU during the access cycle that triggered the
translation exception.
Break on Write. If BW is 1, a break is generated when
data is written to the breakpoint address or when
data is read from the breakpoint address as the first
part of a read-modify-write access. If BW is 0, this
condition is disabled.
STT
BP
Break on Execution. If BE is 1, a break is generated
when the instruction at the breakpoint address is
fetched. If BE is 0, this condition is disabled.
CPU Status. This 4-bit field is set on an address
translation exception to the value of the CPU Status
Bus (STO-ST3).
Break. This bit is set to indicate that a breakpoint
condition has been detected by the MMU.
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CPU Error. This bit is set when a bus error occurs
while the CPU is in control of the bus.
ME MMU Error. This bit is set when a bus error occurs
while the MMU is in control of the bus.
DDE Data Direction. This bit indicates the direction of the
transfer that the CPU was attempting when the bus
error occurred.
DDE = 0 = > Read Cycle
BAS Breakpoint Address Space. This bit selects the address space for breakpointing.
BAS = 0 Selects Address Space 0 (PTBO).
BAS = 1 Selects Address Space 1 (PTB1).
3.11 MEMORY MANAGEMENT STATUS REGISTER
(MSR)
The Memory Management Status Register provides status
information for translation exceptions as well as bus errors.
When either a translation exception or a bus error occurs,
the corresponding bits in the MSR are updated.
The MSR register can be loaded with an LMR instruction. Its
format is shown in Figure 3-8. Bits 19 through 31 are reserved for future use and are returned as zeros when read.
Bits 8 and 18 are also reserved.
Upon reset, all MSR bits are cleared to zero. Details on the
function of each bit are given below.
DDE
= 1 = > Write Cycle
USE User/Supervisor. This is the state of the U/S pin from
the CPU during the access cycle that triggered the
bus error.
STE CPU Status. This 4-bit field is set to the value of the
CPU status bus (STO-ST3) when a bus error is detected.
Note: The MBR and TEAR registers are updated whenever a translation
exception occurs, regardless of whether a CPU abort will result As a
consequence, after an abort is recognized, MSR and TEAR may be
overwritten with new data and thus the original contents may be lost.
This happens if the CPU, while executing the abort routine, performs
instruction prefetch cycles from an invalid page. To ensure correct
operation the reading of MBR and TEAR should be performed before
any instruction prefetch crosses a page boundary, unless the next
page is valid. This may place soma restrictions in the relocation of the
TEX Translation Exception. This 2-bit field specifies the
cause of the current address translation exception.
Combinations appearing in this field are summarized
below.
00 No Translation Exception
abort routine.
01 First Level PTE Invalid
10 Second Level PTE Invalid
11
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Protection Violation
Note: During address translation, if a protection violation and an invalid PTE
are detected at the same time, the TEX field is set to indicate a pro·
tection violation.
_ B A S i BEIBWIBRIAOloslTS ITU I
BI7
131
01
TLlEE/9142-24
FIGURE 3·7. Memory Management Control Register (MCR)
IU5EIooEI ME ICE IBP @l : sf : lUST lOOT I
TL/EE/9142-25
FIGURE 3·8. Memory Management Status Register (MSR)
3-21
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3.0 Architectural Description
(Continued)
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3.12 TRANSLATION LOOKASIDE BUFFER (TLB)
tI)
The Translation Lookaside Buffer is an on-chip fully associative memory. It provides direct virtual to physical mapping
for the 32 most recently used pages, requiring only one
clock period to perform the address translation.
The efficiency of the MMU is greatly increased by the TLB,
which bypasses the much longer Page Table lookup in over
97% of the accesses made by the CPU.
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Z
sponding fields in all entries of the TLB. When the Tag portion of a TLB entry completely matches the input values, the
Value portion is produced as output. If the protection level is
not violated, and the M bit does not need to be changed,
then the physical address Page Frame number is output in
the next clock cycle. If the protection level is violated, the
MMU instead activates the Abort output. If no TLB entry
matches, or if the matching entry's M bit needs to be
changed, the MMU performs a page-table lookup from
memory.
Entries in the TLB are allocated and replaced by the MMU
itself; the operating system is not involved. The TLB entries
cannot be read or written by software; however, they can be
purged from it under program control.
Figure 3-9 models the TLB. Information is placed into the
TLB whenever the MMU performs a lookup from the Page
Tables in memory. If the retrieved mapping is valid (V= 1 in
both levels of the Page Tables), and the access attempted
is permitted by the protection level, an entry of the TLB is
loaded from the information retrieved from memory. The recipient entry is selected by an on-chip circuit that implements a Least-Recently-Used (LRU) algorithm. The MMU
places the virtual page number (20 bits) and the Address
Space qualifier bit into the Tag field of the TLB entry.
Note that for a translation to be loaded into the TLB it is
necessary that the Level-1 and Level-2 Page Table Entries
be valid (V bit = 1). Also, it is guaranteed that in the process of loading a TLB entry (during a Page Table lookup)
the Level-1 and Level-2 R bits will be set in memory if they
were not already set. For these reasons, there is no need to
replicate either the V bit or the R bit in the TLB entries.
Whenever a Page Table Entry in memory is altered by software, it is necessary to purge any matching entry from the
TLB, otherwise the MMU would be translating the corresponding addresses according to obsolete information. TLB
entries may be selectively purged by writing a virtual address to one of the IVARn registers using the LMR instruction. The TLB entry (if any) that matches that virtual address
is then purged, and its space is made available for another
translation. Purging is also performed by the MMU whenever an address space is remapped by altering the contents of
the PTBO or PTB1 register. When this is done, the MMU
purges all the TLB entries corresponding to the address
space mapped by that register. Turning translation on or off
(via the MCR TU and TS bits) does not affect the contents
of the TLB.
The Value portion of the entry is loaded from the Page Tables as follows:
The Translation field (20 bits) is loaded from the PFN field
of the Level-2 Page Table Entry.
The CI and M bits are loaded from the Level-2 Page Table
Entry.
The PL field (2 bits) is loaded to reflect the net protection
level imposed by the PL fields of the Level-1 and Level-2
Page Table Entries.
3.13 ADDRESS TRANSLATION ALGORITHM
The MMU either translates the 32-bit virtual address to a
32-bit physical address or reports a translation error. This
process is described algorithmically in the following pages.
See also Figure 3-3.
(Not shown in the figure are additional bits associated with
each TLB entry which flag it as full or empty, and which
select it as the recipient when a Page Table lookup is performed.)
When a virtual address is presented to the MMU for translation, the high-order 20 bits (page number) and the Address
Space qualifier are compared associatively to the corre-
VALUE
TAG
PAGE NUMBER
AS·
(20 BITS)
VIRTUAL
ADDRESS
M
CI
TRANSLATION
(20 BITS)
0
mmm
xxx
11
0
1
YYY
11
a a
nnn
0
zzz
11
1
1
PPP
1
www
00
1
a
qqq
0
(U/s, ZZZ)
PL
COMPARISON
TRANSLATED
ADDRESS
(PPP)
TL/EE/9142-26
FIGURE 3-9. TLB Model
•AS represents the virtual address space qualifier.
3-22
MMU Page Table Lookup and Access Validation Algorithm
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Legend:
x = y
x == y
x AND y
x OR y
x is assigned the value y
Comparison expression, true if x is equal to y
Boolean AND expression, true only if assertions x and yare both true
Boolean inclusive OR expression, true if either of assertions x and y is true
Delimiter marking end of statement
( ... J
Delimiters enclosing a statement block
item(i)
Bit number i of structure "item"
item(i:j)
The field from bit number i through bit number
of structure "item"
item.x
The bit or field named "x" in structure "item"
DONE
Successful end of translation; MMU provides translated address
ABORT
Unsuccessful end of translation; MMU aborts CPU access
This algorithm represents for all cases a valid definition of address translation.
Bus activity implied here occurs only if the TLB does not contain the mapping,
or if the reference requires that the MMU alter the M bit of the Page Table Entry.
Otherwise, the MMU provides the translated address in one clock period.
Input (from CPU) :
U (1 if U/S is high)
W (1 if DDIN input is high)
VA Virtual address consisting of:
INDEX_l (from pins A31-A22)
INDEX_2 (from pins A21-A12)
OFFSET (from pins AII-AO)
ACCESS_LEVEL
The access level of a reference is a 2-bit value synthesized by the MMU from CPU status:
bit 1
U AND NOT MCR.AO (U from U/S input pin)
bit 0 = 1 for Write cycle, or Read cycle of an "rmw" class operand access
o otherwise.
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Output:
PA Physical Address on pins PAO-PA31;
CI Cache Inhibit Signal
Abort pulse on RST/ABT pin.
Uses:
MCR
Control Register:
fields TU, TS and DS
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NS32382-10/NS32382·15
MMU Page Table Lookup and Access Validation Algorithm
Page Table Base Register 0
Page Table Base Register 1
Level-l Page Table Entry:
fields PFN, PL, V and R
PTEP_l
Pointer, holding address of PTE_l
PTE_2
Level-2 Page Table Entry:
fields PFN, PL, V, M, Rand CI
PTEP_2
Pointer, holding address of PTE_2
IF ( (MCR.TU = = 0) AND (U = = 1)
OR «MCR.TS
0) AND
THEN { PA(0:31) = VA(0:31) ; CINH PIN = 0 ; DONE
(Continued)
(0)
o
PTBO
PTBI
PTE_l
l>
a
J
::;:
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==0) )
If translation not enabled then echo
virtual address as physical address.
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IF (MCR.DS = = 1) AND (U = = 1)
THEN { PTEP_l(31:12) = PTBl(31:12)
PTEP_l(1l:2) = VA.INDEX_l ; PTEP_l(l:O) =0
ELSE
PTEP_l(31:12) = PTBO(31:12) ;
PTEP_l(11:2) = VA.INDEX_l; PTEP_l(l:O) = 0
If Dual Space mode and
then form Level-l
from PTBI
else form Level-l
from PTBO
CPU in User Mode
PTE address
register,
PTE address
register.
U)
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- - - LEVEL 1 PAGE TABLE LOOKUP - - IF ( ACCESS_LEVEL > PTE_I. PL ) OR (PTE_I. V
THEN ABORT ;
IF PTE_l.R
PTEP_2(31:11)
PTEP_2(1l:2)
0 THEN PTE_l.R
=
=
PTE_LPFN
VA.INDEL2
If protection violation or invalid Level-2 page
table then abort the access.
0)
Otherwise. set Reference bit if not already set,
1
and form Level-2 PTE address.
PTEP_2(1:0)
0
LEVEL 2 PAGE TABLE LOOKUP -
IF ( ACCESS_LEVEL > PTE_2. PL ) OR ( PTE_2. V = = 0 )
THEN ABORT ;
IF PTE_2.R = = 0 THEN PTE_2.R = = 1
IF ( W = = 1) AND ( PTE_2.M = = 0
THEN PTE_2.M
PA(31:11)
DONE ;
PTE_2.PFN
PA(ll:O)
VA.OFFSET
CINH
If protection violation or invalid page
then abort the access.
1
PTE_2.CI
Otherwise, set Referenced bit if not already set,
if Write cycle set Modified bit if not
already set,
and generate physical address.
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3.0 Architectural Description
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(Continued)
For reasons of system security, all MMU instructions are
privileged, and the CPU does not issue them to the MMU in
User Mode. Any such attempt made by a User-Mode pro·
gram generates the Illegal Operation trap, Trap (ILL). In addition, the CPU will not issue MMU instructions unless its
CFG register's M bit has been set to validate the MMU in·
struction set. If this has not been done, MMU instructions
are not recognized by the CPU, and an Undefined Instruction trap, Trap (UND), results.
3.14 INSTRUCTION SET
Four instructions of the Series 32000 instruction set are ex·
ecuted cooperatively by the CPU and MMU. These are:
LMR
SMR
Load Memory Management Register
Store Memory Management Register
RDVAL
Validate Address for Reading
WRVAL Validate Address for Writing
The format of the MMU slave instructions is shown in Figure
3-10. Table 3-2 shows the encodings of the "short" field for
selecting the various MMU internal registers.
The LMR and SMR instructions load and store MMU registers as 32-bit quantities to and from any general operand
(including CPU General-Purpose Registers).
The RDVAL and WRVAL instructions probe a memory address and determine whether its current protection level
would allow reading or writing, respectively, if the CPU were
in User Mode. Instead of triggering an Abort trap, these instructions have the effect of setting the CPU PSR F bit if the
type of access being tested for would be illegal. The PSR F
bit can then be tested as a condition code.
TABLE 3-2. "Short" Field Encodlngs
"Short" Field
Register
0000
0001
0010
0011
0110
1001
1010
1011
1100
1101
1110
1111
BAR
RESERVED
BMR
BDR
BEAR
MCR
MSR
TEAR
PTBO
PTBI
IVARO
IVARI
Nole: The Series 32000 Dual-Space Move instructions (MOVSUi and
MOVUSi), although they involve memory management action. are not
Slave Processor instructions. The CPU implements them by switching
the state of its U/S pin at appropriate times to select the desired
mapping and protection from the MMU.
For full architectural details of these instructions, see the
Series 32000 Instruction Set Reference Manual.
4.0 Device Specifications
4.1 NS32382 PIN DESCRIPTIONS
The following is a brief description of all NS32382 pins. The
descriptions reference portions of the Functional Description, Section 2.0.
Note: All other codes are illegal. They will cause unpredictable registers to
be selected if used in an instruction.
817
OPERATION WORD
to CODE
01
TLlEE/9142-27
FIGURE 3-10. MMU Slave Instruction Format
3-25
.....
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4.0 Device Specifications
(Continued)
c
,...
Power (Vee): Eight pins, connected to the + 5V supply.
Back Bias Generator (BBG): Output of on-chip substrate
voltage generator.
N
Ground (GND): Eighteen pins, connected to ground.
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Z
Hold Acknowledge in (HLDAI): Active low. Applied by the
CPU in response to HOLD input, indicating that the CPU has
released the bus for DMA or multiprocessing purposes.
Section 2.6 .
4.1.1 Supplies
Reset Input (RSTI): Active low. System reset. Section 2.3.
Status Lines (STO-ST3): Status code input from the CPU.
Active from T4 of previous bus cycle through T3 of current
bus cycle. Section 2.4.
4.1.2 Input Signals
Clocks (PHI1, PHI2): Two-phase clocking signals. Section
2.2.
User/Supervisor Mode (U/S): This signal is provided by
the CPU. It is used by the MMU for protection and for selecting the address space (in dual address space mode only).
Section 2.4.
Ready (ROY): Active high. Used by slow memories to extend MMU originated memory cycles. Section 2.4.4.
Hold Request (HOLD): Active low. Causes a release of the
bus for DMA or multiprocessing purposes. Section 2.6.
Address Strobe Input (ADS): Active low. Pulse indicating
that a virtual address is present on the bus.
Bus Error (BER): Active low. When active, indicates that an
error occurred during a bus cycle. Not applicable for slave
cycles.
Connection Diagram
NS32382 Pinout Descriptions
125 Pin Grid Array
®®®®®®®®®®®®
B®@®®®®®®®®®®@®
c®® ®®®®®®®®®®®
o®®®
®®®
E®®®
®®®
F®®®
®®®
G®®®
®®®
NS32382
H®®®
®®®
J ®®®
®®®
K®®®
®®®
L®®®
®®®
M®® ®®®®®®®® ®®
N®@®®®®®®®®®®@®
®®®®®®®®®®®®
14
13
12
11
10
9
TL/EE/9142-28
Bottom View
FIGURE 4-1. Pin Grid Array Package
Order Number NS32382U-10 or NS32382U-15
See NS Package Number U125A
3-26
Desc
Pin
Desc
NC
SPC
NC
SDONE
MILO
HLDAI
RSTI
BER
8RT
RST/A8T
STO
STI
NC
NC
GND
GND
Vee
HOLD
RDY
PHI2
PHil
PAV
FLT
ST2
ST3
RESERVED
NC
MADS
GND
GND
DDIN
HLDAO
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
81
82
83
B4
85
86
87
B8
B9
Bl0
Bll
B12
B13
B14
Cl
C2
C3
C4
C5
C6
Vee
GND
Vee
Vee
GND
GND
CINH
AD29
AD31
GND
ADS
RESERVED
PA31
AD27
AD30
U/S
PA30
PA29
PA28
AD25
AD26
AD28
PA27
PA26
PA25
AD23
AD24
GND
GND
PA24
PA23
Pin Desc Pin Desc Pin
C7
C8
C9
Cl0
Cl1
C13
C14
Dl
D2
D3
D12
D13
D14
El
E2
E3
E12
E13
E14
Fl
F2
F3
F12
F13
F14
Gl
G2
G3
G12
G13
G14
AD22
AD21
AD20
GND
PA22
PA21
AD19
AD18
AD17
PA20
PA19
PA18
AD14
AD15
AD16
GND
PA17
PA16
AD13
AD12
Vee
Vee
PA14
PA15
NC
GND
GND
AD7
AD3
Vee
BBG
HI
H2
H3
H12
H13
H14
Jl
J2
J3
J12
J13
J14
Kl
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
MI
M2
M4
M5
M6
M7
M8
PA4 M9
PA7 Ml0
GND MIl
Vee M13
PA13 M14
NC
Nl
GND N2
GND N3
AD9 N4
AD5 N5
AD2 N6
ADO N7
PAO N8
PA3
N9
PA6 Nl0
PA9 NIl
GND N12
NC
N13
PA12 N14
ADll P2
AD10 P3
AD8 P4
AD6 P5
AD4 P6
ADI
P7
PAl
P8
PA2
P9
PA5 Pl0
PA8 Pll
PAlO P12
PAIl P13
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4.0 Device Specifications (Continued)
Bus Retry (BRT): Active low. When active, the MMU will reexecute the last bus cycle. Not applicable for slave cycles.
Slave Done (SDONE): Active low. Used by the MMU to
inform the CPU of the completion of a slave instruction. It
floats when it is not active.
MMU Address Strobe (MADS): Active low. This signal is
asserted in T1 of an MMU initiated cycle. It indicates that
the physical address is available on the physical address
bus. MADS is floated during hold acknowledge.
MMU Interlock (MILO): Active low. This signal is asserted
by the MMU when it performs a read-modify-write operation
to up-date the R and/or the M bit in the Page Table Entry
(PTE). It is inactive during Hold Acknowledge.
Physical Address Bus (PAO-PA31): These 32 signal lines
carry the physical address. They float during Hold Acknowledge.
Slave Processor Control (SPC): Active low. Used as a
data strobe for slave processor transfers.
4.1.3 Output Signals
Reset Output/Abort (RST/ABT): Active Low. Held active
longer than one clock cycle to reset the CPU. Pulsed low
during T2 to abort the current CPU instruction.
Float Output (FLT): Active low. Floats the CPU from the
bus when the MMU accesses page table entries. Section
2.4.3.
Physical Address Valid (PAV): Active low. Pulse generated during T2 indicating that a physical address is present on
the bus.
Hold Acknowledge Output (HLDAO): Active low. When
active, indicates that the bus has been released.
Cache Inhibit (CINH): This output signal reflects the state
of the CI bit in the second level Page Table Entry (PTE). It is
used to specify non-cacheable pages. During MMU generated bus cycles and when the MMU is in No-Translation
mode, CINH will be held low.
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.
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.......
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~
......
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4.1.4 Input-Output Signals
Data Direction In (DDIN): Active low. Status signal indicating direction of data transfer during a bus cycle. Driven by
the MMU during a page-table lookup.
Address/Data 0-31 (ADO-AD31): Multiplexed Addressl
Data Information. Bit 0 is the least significant bit.
4.2 ABSOLUTE MAXIMUM RATINGS
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
Storage Temperature
All Input or Output Voltages with
Respect to GND
Power Dissipation
O"Cto +70"C
- 65"C to + 150"C
-0.5Vto +7V
2.5W
4.3 ELECTRICAL CHARACTERISTICS TA = 0 to + 70"C, Vcc
Symbol
VIH
Parameter
= 5V ± 5%, GND = OV
Conditions
High Level Input Voltage
Min
Typ
2.0
Max
Units
Vcc + 0.5
V
Vil
Low Level Input Voltage
-0.5
0.8
V
VCH
High Level Clock Voltage
PHI1, PHI2 Pins Only
Vcc - 0.5
Vcc + 0.5
V
VCl
Low Level Clock Voltage
PHI1, PHI2 Pins Only
-0.5
0.3
V
VCRT
Clock Input
Ringing Tolerance
PHI1, PHI2 Pins Only
-0.5
0.5
V
VOH
High Level Output Voltage
IOH
VOL
Low Level Output Voltage
IllS
SPC Input Current (Low)
= 2mA
VIN = O.4V, SPC in Input Mode
II
Input Load Current
o ,;; VIN ,;; Vcc, All Inputs Except
= -400 p.A
2.4
PHI1, PHI2, AT/SPC
Il
Icc
V
0.45
V
0.05
1.0
mA
-20
20
p.A
-20
20
p.A
500
mA
IOl
Leakage Current
(Output and I/O Pins
in TRI-STATElinput Mode)
0.4 ,;; VOUT ,;; Vcc
Active Supply Current
lOUT
= 0, TA = 25"C
3-27
350
&I
,..
It)
N
CD
4.0 Device Specifications
N
4.4 SWITCHING CHARACTERISTICS
C")
~
Z
.....
o
.
,..
(Continued)
and PHI2, and 0.8V or 2.0V on all other signals as illustrated
in Figures 4-2 and 4-3, unless specifically stated otherwise.
4.4.1 Definitions
ABBREVIATIONS:
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
N
CD
C")
N
C")
tJ)
Z
PHln
SIGI
SIG2
[:x
[[
L.E. -
leading edge
R.E. -
rising edge
T.E. -
trailing edge
F.E. -
falling edge
[
[
PH In
----2.4V
~~.45V
lSIGll
I
lSIG2h
SIGI
2.4V
j'~
._---O.BV
[
SIG2
---O.45V
x::
2.0V
'\
--2.4V
lSIGll
O.45V
2.4V
/
'SIG2h
-----O.45V
TL/EE/9142-30
TL/EE/9142-29
FIGURE 4·3. Timing Specification Standard
(Signal Valid before Clock Edge)
FIGURE 4·2. Timing Specification Standard
(Signal Valid after Clock Edge)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32382·10, NS32382·15.
Maximum times assume capacitive loading of 50 pF.
Name
Description
Figure
Reference/Conditions
= 1)
Valid (FLT = 1)
NS32382·10
NS32382·15
Min
Min
Max
Units
Max
tpALv
4-4
PAO-11 Valid (FLT
After R.E., PHI1 T1
75
50
ns
tpAHv
4-4
PA12-31
After R.E., PHI1 T2
30
20
ns
tPAVa
4-4
PAY Signal Active
After R.E., PHI1 T2
25
17
ns
tPAVia
4-4
PAY Signal Inactive
After R.E., PHI2 T2
40
27
tpAVw
4-4
PAY Pulse Width
At 0.8V (Both Edges)
35
22
ns
tpALh
4-4
After R.E., PHI1 (Next) T1
0
0
ns
tpAHh
4-4
= 1)
PA12-31 Hold (FLT = 1)
CINH Signal Valid (FLT = 1)
(FLT = 0)
CINH Signal Hold (FLT = 1)
ODIN Signal Valid (FLT = 0)
After R.E., PHI1 (Next) T2
0
0
ns
tClv
4-4,
4-15,
tClh
4-4
tOOINv
4-5,
4-7,
4-15
PAO-11 Hold (FLT
After R.E., PHI1 T2
After R.E., PHI1 T1
After R.E., PHI1 (Next) T2
40
0
tOOINh
4-5
ODIN Signal Hold (FLT
tov
4-6
ADO-AD31 Valid (Memory Write)
After R.E., PHI1 T2
tOh
4-6
ADO-AD31 Hold (Memory Write)
After R.E., PHI1 (Next) T1
tMAv
4-6
PAO-31 Valid (FLT
tMAh
4-6
PAO-31 Hold (FLT
= 0)
= 0)
27
ns
25
ns
0
After R.E., PHI1 T1
35
= 0)
ns
After R.E., PHI1 (Next) T1
0
0
After R.E., PHI1 T1
After R.E., PHI1 (Next) T1
3-28
0
50
0
30
0
ns
38
ns
20
0
ns
ns
ns
z
en
w
4.0 Device Specifications (Continued)
I\)
w
.
4.4.2.1 Output Signals: Internal Propagation Delays, NS32382-10, NS32382-15.
Maximum times assume capacitive loading of 50 pF. (Continued)
Name
Figure
Description
MADS Signal Active (FLT
Reference/Conditions
=
0)
CXI
I\)
......
NS32382-10
NS32382-15
Min
Min
tMAOSa
4-6,15
After R.E., PHil Tl
tMAOSia
4-6
MADS Signal Inactive
After R.E., PHI2 Tl
5
tMAOSw
4-6
MADS Pulse Width
At 0.8V (Both Edges)
35
DDIN Floating
After R.E., PHil T3
After R.E., PHil Tl
Max
17
25
Units
Max
ns
o
.......
z
en
w
I\)
w
CXI
tOOIN!
4-7,
4-9,11
tMILOa
4-5,
4-15
MILO Signal Active
After R.E., PHil T4
tMILOia
4-7,
4-15
MILO Signal Inactive
After R.E., PHil Tl or Ti
tABTa
4-8
RST/ ABT Signal Active (Abort)
After R.E., PHil Tl or T2
tABTia
4-8
RST/ ABT Signal Inactive (Abort)
After R.E., PHil T2 or T3
tABTw
4-8
RST/ ABT Pulse Width (Abort)
At 0.8V (Both Edges)
35
5
22
ns
ns
25
25
50
38
50
38
ns
40
ns
40
ns
50
2
25
50
60
2
ns
tFLTa
4-5
FLT Signal Active
After R.E., PHil T2
tFLTia
4-7,
4-9
FLT Signal Inactive
After R.E., PHil T2
tOf
4-12
Data Bits Floating
(Slave Processor Read)
After R.E., PHil T4
tov
4-12
ADO-AD31 Valid
(CPU Slave Read)
After R.E., PHil Tl
tOh
4-12
ADO-AD31 Hold
(CPU Slave Read)
After R.E., PHil T4
tSONa
4-14
SDONE Signal Active
After R.E., PHI2
50
35
ns
tSONia
4-14
SDONE Signal Inactive
Ater R.E., PHil
50
35
ns
tSONw
4-14
SIJONE Pulse Width
At 0.8V (Both Edges)
25
90
17
60
ns
tSONdw
4-14
SDONE Double Pulse Width
At 0.8V (Both Edges)
225
275
140
180
ns
tSON!
4-14
SDONE Signal Floating
After R.E., PHI2
40
25
ns
tHLOAOa
4-15
After R.E., PHil Ti
60
40
ns
tHLOAOia
4-15
= 0)
HLDAO Signal Inactive (FLT = 0)
After R.E., PHil T4
60
40
ns
HLDAO Signal Active (FLT
50
40
ns
40
30
ns
25
18
50
38
3
ns
ns
tMAOSz
4-15
MADS Signal Floated by HOLD
After R.E., PHil Ti
40
25
ns
tpAVz
4-15
PAV Signal Floated by HOLD
After R.E., PHil Ti
40
25
ns
tPAVr
4-15
PAV Return from Floating
(Caused by HOLD)
After R.E., PHil Tl
40
25
ns
toz
4-15
ADO-AD31 Floating
(Caused by HOLD)
After R.E., PHil Ti
25
18
ns
tMAz
4-15
PAO-31 Floated by HOLD
After R.E., PHil Ti
25
18
ns
tOOINz
4-15
DDIN Signal Floated by HOLD
After R.E., PHil Ti
40
25
ns
telz
4-15
CINH Signal Floated by HOLD
After R.E., PHil Ti
25
18
ns
tMILOia
4-15
MILO Signal Inactive
by HOLD (FLT = 0)
After R.E., PHil Ti
50
38
ns
3-29
U1
ns
40
4
~
......
&I
....
II)
co:.
4.0 Device Specifications (Continued)
C\I
4.4.2.1 Output Signals: Internal Propagation Delays, NS32382·10, NS32382·15.
Maximum times assume capacitive loading of 50 pF. (Continued)
co
C")
C")
(1)
z
C:>
....
.
Name
Figure
Description
Reference/Conditions
C\I
co
C")
(1)
z
NS32382·15
Min
Min
Max
Units
Max
tMILOa
4-15
MILO Signal Active (FLT = 0)
After R.E., PHI1 T4
50
38
ns
tHLDAOa
4-16
HLDAO Signal Active (FLT = 1)
After R.E., PHI1 Ti
45
30
ns
tHLDAOia
4-16
HLDAO Signal Inactive (FLT = 1)
After R.E., PHI1 Ti or T4
45
30
ns
tMAOSz
4-16
MADS Signal Floated
byHLDAI(FLT= 1)
After R.E., PHI1 Ti
25
18
ns
tMAOSr
4-16
MADS Return from
Floating (FLT = 1)
After R.E., PHI1 Ti orT4
30
20
ns
tpAVz
4-16
PAY Signal Floated
HLDAI (FLT = 1)
After R.E., PHI1 Ti
25
18
ns
tpAVr
4-16
PAY Return from Floating
(FLT = 1)
After R.E., PHI1 Ti or T4
30
20
ns
toz
4-16
ADO-AD31 Signals
Floating (FLT = 1)
After R.E., PHI1 Ti
25
18
ns
tOr
4-16
ADO-AD31 Return
from Floating (FLT = 1)
After R.E., PHI1 Ti orT4
30
20
ns
tMAz
4-16
PAO-31 Signals Floated
by HLDAI (FLT = 1)
After R.E., PHI1 T1
25
18
ns
tMAr
4-16
PAO-31 Return from
Floating (FLT = 1)
After R.E., PHI1 Ti or T4
30
20
ns
tClz
4-16
CINH Signal Floated by HLDAI (FLT = 1)
After R.E., PHI1 Ti
25
18
ns
tClr
4-16
CINH Return from Floating (FLT = 1)
After R.E., PHI1 Ti or T4
30
20
ns
tRSTOa
4-18
RST/ ABT Signal Active (Reset)
After R.E., PHI2 Ti
50
40
ns
tRSTOia
4-18
RST/ ABT Signal Inactive (Reset)
After R.E. PHI2 Ti
tRSTOw
4-18
RST/ ABT Pulse Width (Reset)
At 0.8V (Both Edges)
C\I
C")
NS32382·10
50
40
64
ns
Icp
64
4.4.2.2 Input Signal Requirements: NS32382·10, NS32382·15
Name
Figure
Description
Reference/Conditions
NS32382·10
NS32382·15
Min
Min
Max
Units
Max
tOls
4-5
Input Data Setup (FLT = 0)
Before F.E., PHI2 T3
12
10
ns
tOlh
4-5
Input Data Hold (FLT = 0)
After R.E., PHI1 T4
3
3
ns
tRDYs
4-5
RDY Setup
Before F.E., PHI1 T3
20
12
ns
tRDYh
4-5
RDY Hold
After R.E., PHI2 T3
4
3
ns
tsPCs
4-12
SPC Input Setup
Before F.E., PHI2 T1
45
35
ns
tSPCh
4-12
SPC Input Hold
After R.E., PHI1 T4
0
0
ns
tUSs
4-4,4-12
U/S Setup
Before F.E., PHI2T4
25
20
ns
tUSh
4-4,4-12
U/S Hold
After R.E., PHI1 (Next) T4
0
0
ns
tSTs
4-4,4-12
STO-3 Setup
Before F.E., PHI2 T4
40
25
ns
tSTh
4-4,4-12
STO-3 Hold
After R.E., PHI1 (Next) T4
0
0
ns
tOls
4-13
Data In Setup
(Slave Processor Write)
Before F.E., PHI2 T1
40
22
ns
3-30
z
en
Co)
4.0 Device Specifications (Continued)
N
Co)
co
4.4.2.2 Input Signal Requirements: NS32382-10, NS32382-15 (Continued)
Name
Figure
Description
Reference/Conditions
NS32382-10
Min
tDlh
tHOLDs
4-13
4-15
Data In Hold
(Slave Processor Write)
= 0)
= 0)
HOLD Setup (FLT
tHOLDh
4-15
HOLD Hold (FLT
tHLDAis
4-16
HLDAI Signal Setup (FLT
tHLDAih
4-16
tBRTs
4-10
tBRTh
4-10
tBERs
4-11
tBERh
4-11
= 1)
HLDAI Signal Hold (FLT = 1)
BRT Signal Setup (FLT = 0)
BRT Signal Hold (FLT = 0)
BER Signal Setup (FLT = 0)
BER Signal Hold (FLT = 0)
After R.E., PHil (Next) Ti
Max
NS32382-15
Min
......
z
ns
N
Max
3
3
~
....
o
Units
en
Co)
Co)
co
Before F.E., PHI2 T3
15
15
ns
After R.E.. PHil T4
0
0
ns
Before F.E., PHI2 Ti
25
15
ns
After R.E., PHil Ti or T4
0
0
ns
Before F.E., PHil T3 or T4
25
14
ns
After R.E., PHI2 T3 or T4
0
0
ns
Before F.E., PHil T4
25
14
ns
0
0
ns
After R.E., PHI2 T4
tRSTls
4-1B
Reset Input Setup
Before F.E., PHil Ti
20
10
ns
tRSTlw
4-1B
Reset Input Width
At O.BV (Both Edges)
64
64
tep
N
....
I
CJ1
4.4.2.3 Clocking Requirements: NS32382-10, NS32382-15
Name
Figure
Description
Reference/
Conditions
NS32382-10
NS32382-15
Min
Max
Min
Max
100
250
66
250
ns
tcp
4-17
Clock Period
R.E., PHil, PHI2 to Next
R.E., PHil, PHI2
tCLw(1,2)
4-17
PHil, PHI2 Pulse Width
At 2.0V on PHil, PHI2
(Both Edges)
0.5 tep
-10 ns
0.5tep
-6 ns
teLh(1,2)
4-17
PHil, PHI2 High Time
At Vcc - 0.9Von
PHil, PHI2 (Both Edges)
0.5 tep
-15 ns
0.5tep
-10 ns
tell
4-17
PHil, PHI2 Low Time
AtO.BVon
PHil, PHI2 (Both Edges)
0.5 tcp
-5ns
0.5tcp
-5ns
tnOVL (1, 2)
4-17
Non-Overlap Time
O.BVon F.E., PHil, PHI2 to
O.BV on R.E., PHI2, PHil
Non·Overlap Asymmetry
At O.BV on PHil, PHI2
tnOVLas
(tnOVL(l) - tnOVL(2)
tCLhas
PHil, PHI2 Asymmetry
At Vcc - 0.9V on PHil, PHI2
teLh(l) - teLh(2)
3-31
Units
-2
5
-2
5
ns
-4
4
-3
3
ns
-5
5
-3
3
ns
•
. r--------------------------------------------------------------------------,
4.0 Device Specifications
~
.....
C'I
co
C')
C'I
(Continued)
4.4.3 Timing Diagrams
C')
(f)
z
.....
o
.....
N
CO
P1111 [
C')
C'I
C')
en
z
PHIZ [
__n
T4
T1
TZ
n n
1U- UL n
VADDR
ADD-31 [
IL-rL
n
ADDRESS VALID
_~fPAlh
IX
tPAHr
----0
)
PA12-31 [
PAi[
I-
_r-=tPAHh
ADDRESS VALID
\......../
ADS [
IPAVa
T2 or Ti
DATA OUT
"-
X
PAD-II [
T1 or TI
T4
T3
n UL
J
"
I
C
'PAlv-
.-
~tPAVia
'~l
\......../
----0
IClh
CINH [
-'CI~
\
/
ODIN [
(HIGH)
-
tUS~i:=::
X
ts~s
-
-t::=:=:
STD-3 [
ROY [
~
tUSh
X
1m
\
TL/EE/9142-31
FIGURE 4-4. CPU Write Cycle Timing; Translation In TLB
3-32
zCJ)
4.0 Device Specifications
Co)
(Continued)
N
Co)
CPU STATES
T1
PHil [
PHI2 [
ADD-31 [
T,
T2
T2
MMU STATES
T,
T,
T2
T4
T,
T3
T3
T,
T4
T,
T1
CD
~
....
o
~IL~
.....
1Ln Ln LnLnLn
- tx ,
-
N
~
In
'\
VA
~~
U-
Z
CJ)
Co)
Co)
CD
....~
U1
~~_IDlh
PAD-" [
PH ADDR
PA12-31 [
-
V
MADS [
1\..../ -
PAV[
ROY [
DmN[
- l.I -
--
-to- FLOATiNG" -
CINH [
~-tRDY'l V
!
-tUDINv
...
I\.
tllOlHh-
v:
-tFlTa
MILO [
--tRDYh
~-I.'lDa
-
I--IMA'
\
TL/EE/9142-32
FIGURE 4-5. MMU Read Cycle Timing (1-Wait State); After a TLB Miss
Note: After FLT is daasserted, DDIN may ba drivan temporarily by both CPU and MMU. This, however, does not cause any conflict. Since CPU and MMU force
DDIN to the same logic lavel.
3-33
•
.
Ln , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
.....
C'I
co
('I)
C'I
('I)
en
4.0 Device Specifications (Continued)
I T1 I
z
......
o.....
•
C'I
T4
T3
12
PHI1 [
PHI2 [
CO
('I)
C'I
"'-31 [-+--+--+"\---I----+-----!-"!'
('I)
en
z
PAG-31
[_+'~+":""-!-----+----+_----II_"
MADS [
... [
RDY [_+--:--:-_ _1----'
ODIN [
fLJ[_+-_____I----_r----+_---__Ir_---
.I~[-+_---__Ir_---_r----+_-----r_--TUEE/9142-33
FIGURE 4-6. MMU Write Cycle Timing; after a TLB Miss
CPU STATES
T,
MMU STATES
T1
T,
12
T3
T4
T,
T,
T3
T1
12
T3
T4
T.
PHI1 [
PflI2 [
ADD-31 [
PAD-31 [
MADI[
... [
(MU: [
DDIN [
ICPUI
(FlOAnNG)
-
fLJ[_+__-+---+--+-:--_r"""':--+.J
.I~ [-+---+---+--+---+.1
ClN" [-+---+_--+--_r---+~r-_I--""""r_--+_--+_TL/EE/9142-34
FIGURE 4-7. FLT Deassertlon Timing
Note: After FLT is deasserted. ODIN may be driven temporarily by both CPU and MMU. This. however. does not cause any conflict. Since CPU and MMU force
ODIN to the same logic level.
3-34
z
en
Co)
4.0 Device Specifications (Continued)
N
Co)
T4 OR 11
T1
T2
CD
....~
11
T3
o
.......
PHil [
Z
~
PHIZ [
N
.....
Co)
ADS [
CD
N
PA'i[
U1
m[
RsT/ AiiT [
TL/EE/9142-35
FIGURE 4·8. Abort Timing (FLT = 1)
CPU STATES
MMU STATES
r;
T1
T4
T3
T4
TI
li
PIII1 [
PIII2 [
~[
...
[
m[
iiS'i/ABT [
----
tDDINI
DoiN[
IFLOAlING)
IMMU}
TL/EE/9142-36
FIGURE 4·9. Abort Timing (FLT = 0)
3·35
•
....
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
~
co
CO)
4.0 Device Specifications (Continued)
C'I
CO)
T1
(f)
z
(:)
....
T2
T3
T2
T1
T4
T4
T3
PHil [
~
co
CO)
PHI2 [
C'I
CO)
(f)
z
PAO-3l [
DATA IN
ADD-3l [
MADS [
PAV[
m[
RDY [
FLT [
(LOW)
MliO[
(LOW)
TL/EE/9l42-37
FIGURE 4-10. MMU Bus Retry Timing
T3
T4
T1
n
PHil [
PHI2 [
BER[
MILO [
RDY [
m[
m[
RST/ABT [
TLlEE/9l42-53
FIGURE 4·11. Bus Error Timing
3-36
z
en
c;,.)
4.0 Device Specifications (Continued)
N
c;,.)
T4 OR TI
T1
T4
co
N
......
o
.......
I
T1 OR TI
z
PHI1 [
PHI2
en
c;,.)
[L+-_..I
N
c;,.)
co
......
N
I
ADO-31[.-
U1
5PC [
U/S[ __~_~_ _++_____-r_~___~_______
5TO- 3 [
DDIN[~~__________~__~~____+-__________+-__~~____
TL/EE/9142-38
FIGURE 4-12. Slave Access Timing; CPU Reading from MMU
T4 OR Ti
T1
T4
T1 OR TI
PHil [
PHI2 [
+-____________+-__
AOO-31 [ __
.J
,..-----+--------I-..JI
SPC [
STO-3
1iiiili[
(CPU)
•
[_+-_01 ,,___-+___________-+______+-_______
+-__________+-_.1
__
TLlEE/9142-39
FIGURE 4-13. Slave Access Timing; CPU Writing to MMU
3-37
U)
..-
N
co
r---------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
C')
C'I
C')
U)
Z
......
Q
..-
PHil [
N
co
C')
C'I
PHI2 [
C')
U)
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TLlEE/9142-40
FIGURE 4-14. SDONE Timing
T3
T4
TI
TI
TI
---~~
----FLOATING
T4
T1
T2
PHil [
PHI2 [
HOLD [
HLDAD [
MADS [
-
PiV[
FLOATING
m[
AOO·31 [
PAO·31 [
AOOR VALID
ODIN [
IMMU)
IMMU READ)
ILOW)
CINH [
MILD [
TL/EE/9142-50
FIGURE 4·15. Hold Timing (FLT = 0)
3·38
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4.0 Device Specifications
en
c.:I
(Continued)
N
c.:I
.
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CPU STATE
T4
Ti
TI
Ti
TI
N
....
Ti or T4
Q
......
PHil [
Z
en
c.:I
N
c.:I
PHI2 [
0)
N
....•
U1
HLDAI [
HLDAD [
IMADS,
--~~
MADS [
----FLOATING
--lpAVz
--~~
PAV [
FLOATING
(HIGH)
FLT [
-tor
---0- ----
ADD-3l [
FLOATING
--~
-tMAr
--
PAD-3l [
---'i~
FLOATING
-~
--tClr
----i~
CINH [
---FLOATING
-~
(HIGH)
MILO [
TlIEE/9142-51
FIGURE 4-16. Hold Timing (FLT = 1)
PHil [
PHIZ [
------I-"r
TlIEE/9l42-49
FIGURE 4-17. Clock Waveforms
3-39
•
n
TI
TI
TI
TI
PHil [
PHI2 [
nT/ABT [
m[
TLIEE19142-45
FIGURE 4-18. Non Power-On Reset Timing
vee
...It-"----~\__
PHI{ __-t___-'
RSfI[ ____________~~-J
TUEE19142-46
FIGURE 4-19. Power-On Reset
3·40
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Appendix A: Interfacing Suggestions
N
Co)
co
N
IT,
CWAIT
1T1
WAIT1
T2
WAIT2
8RSn
8US
CONTROL
lOGIC
......
I
Rii
WR
o
.......
TSO
en
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z
08E
8RSTO
N
+E
ADS
~m
ROY
RST
ClK ODIN
'--
1
ut+-
BEO BE1BE2 BE3
BOUT
IN>-H
BiN
FlT
OOiN
RST/AB!
8WO>-Bw l > - -
8WO
HlOA
rS+--
BWI
PFS
iN'i>----t iN'i
Mi>----t
BER
BRT
HO
lO
Ni.ii
,...
+5 +-~
ROY
iLci
~
lA
2A
3A
4A
18
28
38
48
N
U
ROY
Rsn
FlT
OOiN
RST./A8T
I
2Yr---+
3Yr---+
4Yr---+
f~
ADS
BER
BRT
SOONE
SPC
HOLD
_iii.
STO-3
r,:
PHil
PHI2
r-+
HlOAO
HlOAI
ADS
BER
8RT
iiT/SOONE
SPC
HOLD
STO-3
PHil
PHI2
AOO-31
U1
MilO
iUL
NS32332
CPU
....
lY r---+
L-
M
PAY
5V
NS32382
MMU
CINH
CINH
---..
.
PAO-31
MADS
AOO-31
.,
.,
,
Co)
co
~
L...."..",...5V
5V
..
~
r
~
PAO-31
RST
00-31
10k.1l
+5
1 k.1l
1 k.1l
'
...
00-31
"- NOE
I
SON332
' - - PSO
SPC
PSI
STO-3
f"
NS32381
FPU
PHil
f--
...
I'
NS32C201
TCU
RST
ClK
OOiN
I
PHI2
RSTO
r
em
XIN
XOUT
1;5
I-J
RST1
SET
Tl/EE/9142-52
FIGURE A-1. System Connection Diagram
3-41
r----------------------------------------------------------------------------,
~ ~National
&i ~ Semiconductor
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NS32082-10 Memory Management Unit
General Description
Features
The NS32082 Memory Management Unit (MMU) provides
hardware support for demand-paged virtual memory implementations. The NS32082 functions as a slave processor in
Series 32000 microprocessor-based systems. Its specific
capabilities include fast dynamic translation, protection, and
detailed status to assist an operating system in efficiently
managing up to 32 Mbytes of physical memory. Support for
multiple address spaces, virtual machines, and program debugging is provided.
• Totally automatic mapping of 16 Mbyte virtual address
space using memory based tables
• On-Chip translation look-aside buffer allows 97% of
translations to occur in one clock for most applications
• Full hardware support for virtual memory and virtual
machines
• Implements "referenced" bits for simple, efficient working set management
• Protection mechanisms implemented via access level
checking and dual space mapping
• Program debugging support
• Compatible with NS32016, NS32032 and NS32332
CPUs
• 48-pin dual-in-line package
High-speed address translation is performed on-chip
through a 32-entry fully associative translation look-aside
buffer (TLB), which maintains itself from tables in memory
with no software intervention. Protection violations and
page faults (references to non-resident pages) are automatically detected by the MMU, which invokes the instruction
abort feature of the CPU.
Additional features for program debugging include two
breakpoint registers and a breakpoint counter, which provide the programmer with powerful stand-alone debugging
capability.
Conceptual Address Translation Model
r----.,
SERIES
32000
CPU
VIRTUAL ADDRESS ...
ADDRESS STROBE
FLOAT
r----., PHYSICAL ADDRESS ... r----"I
..
NS320B2
MMU
ADDRESS STROBE
PHYSICAL
MEMORY
ABORT
TL/EE/8692-1
3-42
Z
tn
Co)
Table Of Contents
1.0 PRODUCT INTRODUCTION
I\)
o01)
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.5 Breakpoint Registers (BPRO, BPR1)
1.1 Programming Considerations
2.0 FUNCTIONAL DESCRIPTION
.
I\)
.....
3.6 Breakpoint Count Register (BCNT)
2.1 Power and Grounding
o
3.7 Memory Management Status Register (MSR)
3.7.1 MSR Fields for Address Translation
2.2 Clocking
2.3 Resetting
2.4 Bus Operation
2.4.1 Interconnections
3.7.2 MSR Fields for Debugging
3.8 Translation Lookaside Buffer (TLB)
3.9 Entry/Re-entry into Programs Under Debugging
2.4.2 CPU-Initiating Cycles
3.10 Address Translation Algorithm
2.4.3 MMU-Initiated Cycles
2.4.4 Cycle Extension
3.11 Instruction Set
4.0 DEVICE SPECIFICATIONS
4.1 Pin Descriptions
2.5 Slave Processor Interface
2.5.1 Slave Processor Bus Cycles
2.5.2 Instruction Protocols
4.1.1 Supplies
4.1.2 Input Signals
2.6 Bus Access Control
2.7 Breakpointing
2.7.1 Breakpoints on Execution
4.1.3 Output Signals
4.1.4 Input-Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
3.0 ARCHITECTURAL DESCRIPTION
3.1 Programming Model
3.2 Memory Management Functions
4.4 Switching Characteristics
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals; Internal Propagation
Delays
4.4.2.2 Input Signal Requirements
3.2.1 Page Table Structure
3.2.2 Virtual Address Spaces
3.2.3 Page Table Entry Formats
3.2.4 Physical Address Generation
3.3 Page Table Base Registers (PTBO, PTBI)
4.4.2.3 Clocking Requirements
Appendix A: Interfacing Suggestions
3.4 Error/Invalidate Address Register (EIA)
List of Illustrations
The Virtual Memory Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1-1
NS32082 Address Translation Model ........................................................................... 1-2
Recommended Supply Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-1
2-2
Power-On Reset Requirements ................................................................................ 2-3
General Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
Recommended Reset Connections, Memory Managed System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
CPU Read Cycle; Translation in TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
Abort Resulting from Protection Violation; Translation in TLB . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 2-7
Page Table Lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
Abort Resulting After a Page Table Lookup .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-9
Slave Access Timing; CPU Reading from MMU.................................................................. 2-10
Slave Access Timing; CPU Writing to MMU ..................................................................... 2-11
FLT Deassertation During RDVAL/WRVAL Execution............................................................ 2-12
Bus Timing with Breakpoint on Physical Address Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-13
Execution BreakpointTiming; Insertion of DIA Instruction......................................................... 2-14
Two-Level Page Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
A Page Table Entry. . . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . .. .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Virtual to Physical Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Page Table Base Registers (PTBO, PTB1) ....................................................................... 3-4
EIA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
Breakpoint Registers (BPRO, BPR1) ............................................................................ 3-6
Breakpoint Counter Register (BCNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-7
Memory Managment Status Register (MSR) ..................................................................... 3-8
3-43
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
.....
I
N
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(/)
Z
List of Illustrations (Continued)
TLB Model
3-9
Slave Instruction Format..................................................................................... 3-10
Dual-In-Line Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Timing Specification Standard (Signal Valid After Clock Edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) .................................................... 4-3
CPU Read (Write) Cycle Timing (32-Bit Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
MMU Read Cycle Timing (32-Bit Mode) after a TLB Miss........................................................... 4-5
MMU Write Cycle Timing After a TLB Miss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6
FLT Deassertation Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
Abort Timing (FLT = 1) ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8
AbortTiming (FLT = 0) ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9
CPU Operand Access Cycle with Breakpoint On Physical Address Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10
Slave Access Timing; CPU Reading from MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11
Slave Access Timing; CPU Writing to MMU ..................................................................... 4-12
SPC Pulse From the MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
HOLD Timing (FLT = 1); SMR Instruction Not Being Executed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14
HOLD Timing (FLT = 1); SMR Instruction Being Executed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-15
HOLD Timing (FLT = 0) ..................................................................................... 4-16
Clock Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-17
ResetTiming ............................................................................................... 4-18
Power-On Reset ............................................................................................ 4-19
System Connection Diagram......... ............................ .............................................. A-1
System Connection Diagram..................................... .............................................. A-2
Tables
STO-ST3 Encodings.......................................................................................... 2-1
LMR Instruction Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
SMR Instruction Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
RDVAL/WRVAL Instruction Protocol............................................................................ 2-4
Access Protection Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Instructions Causing Non-Sequential Fetches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
"Short" Field Encodings ...................................................................................... 3-3
3-44
z
rn
1.0 Product Introduction
Co)
N
The NS320B2 MMU provides hardware support for three
basic features of the Series 32000; dynamic address translation, access level checking and software debugging. Dynamic Address Translation is required to implement demand-paged virtual memory. Access level checking is performed during address translation, ensuring that unauthorized accesses do not occur. Because the MMU resides on
the local bus and is in an ideal location to monitor CPU
activity, debugging functions are also included.
The translation process is therefore modeled as accepting a
virtual page number from the CPU and substituting the corresponding physical page frame number for it, as shown in
Figure 1-2. The offset is not changed. The translated page
frame number is 16 bits long, including an additional address bit (A24) intended for physical bank selection. Physical addresses issued by the MMU are 25 bits wide.
o
CD
....o~
The MMU is intended for use in implementing demandpaged virtual memory. The concept of demand-paged virtual memory is illustrated in Figure 1-1. At any point in time, a
program sees a uniform addressing space of up to 16 megabytes (the "virtual" space), regardless of the actual size of
the memory physically present in the system (the "physical"
space). The full virtual space is recorded as an image on a
mass storage device. Portions of the virtual space needed
by a running program are copied into physical memory when
needed.
To make the virtual information directly available to a running program, a mapping must be established between the
virtual addresses asserted by the CPU and the physical addresses of the data being referenced.
TLlEE/B692-3
FIGURE 1-2. NS32082 Address Translation Model
Generally, in virtual memory systems the available physical
memory space is smaller than the maximum virtual memory
space. Therefore, not all virtual pages are simultaneously
resident. Nonresident pages are not directly addressable by
the CPU. Whenever the CPU issues a virtual address for a
nonresident or nonexistent page, a "page fault" will result.
The MMU signals this condition by invoking the Abort feature of the CPU. The CPU then halts the memory cycle,
To perform this mapping, the MMU divides the virtual memory space into 512-byte blocks called "pages." It interprets
the 24-bit address from the CPU as a 15-bit "page number"
followed by a 9-bit offset, which indicates the position of a
byte within the selected page. Similarly, the MMU divides
the physical memory into 512-byte frames, each of which
can hold a virtual page.
PHYSICAL
MEMORY
VIRTUAL
MEMORY
•
HIGH
...._ _ _ _ _ _.. MEMORY
ADDRESS
HIGH
MEMORY ....- - - - - -..
ADDRESS
MASS STORAGE
TL/EE/B692-2
FIGURE 1-1. The Virtual Memory Model
3-45
0.------------------------------------------------1
.....
~
co
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C'I
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Z
1.0 Product Introduction
2.0 Functional Description
(Continued)
restores its internal state to the point prior to the instruction
being executed, and enters the operating system through
the abort trap vector.
2.1 POWER AND GROUNDING
The NS32082 requires a single 5V power supply, applied on
pin 48 (Vee).
Grounding connections are made on two pins. Logic Ground
(GNDL, pin 24) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 25) is the common pin for the
output drivers. For optimal noise immunity, it is recommended that GNDL be attached through a single conductor directly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 2-1).
The operating system reads from the MMU the virtual address which caused the abort. It selects a page frame which
is either vacant or not recently used and, if necessary,
writes this frame back to mass storage. The required virtual
page is then copied into the selected page frame.
The MMU is informed of this change by updating the page
tables (Section 3.2), and the operating system returns control to the aborted program using the RETT instruction.
Since the return address supplied by the abort trap is the
address of the aborted instruction, execution resumes by
retrying the instruction.
~
1
This sequence is called paging. Since a page fault encountered in normal execution serves as a demand for a given
page, the whole scheme is called demand-paged virtual
memory.
The MMU also provides debugging support. It may be programmed to monitor the bus for two virtual or physical addresses in real time. A counter register is associated with
one of these, providing a "break-on-N-occurrences" capability.
y+sv
vccp-
TLlEE/8692-4
FIGURE 2·1. Recommended Supply Connections
1.1 PROGRAMMING CONSIDERATIONS
When a CPU instruction is aborted as a result of a page
fault, some memory resident data might have been already
modified by the instruction before the occurrence of the
abort.
2.2 CLOCKING
The NS32082 inputs clocking signals from the NS32201
Timing Control Unit (TCU), which presents two non-overlapping phases of a single clock frequency. These phases are
called PHI1 (pin 26) and PHI2 (pin 27). Their relationship to
each other is shown in Figure 2·2.
Each rising edge of PHI1 defines a transition in the timing
state ("T-State") of.the MMU. One T-State represents one
hardware cycle within the MMU, and/or one step of an external bus transfer. See Section 4 for complete specifications of PHI1 and PHI2.
This could compromise the restartability of the instruction
when the CPU returns from the abort routine.
To guarantee correct results following the re-execution of
the aborted instruction, the following actions should not be
attempted:
a) No instruction should try to overlay part of a source operand with part of the result. It is, however, permiSSible to
rewrite the result into the source operand exactly if page
faults are being generated only by invalid pages and not
by write protection violations (for example, the instruction
"ABSW X, X", which replaces X with its absolute value).
Also, never write to any memory location which is necessary for calculating the effective address of either operand (i.e. the pOinter in "Memory Relative" addressing
mode; the Link Table pointer or Link Table Entry in "External" addressing mode).
b) No instruction should perform a conversion in place from
one data type to another larger data type (Example:
MOVWF X, X which replaces the 16-bit integer value in
memory location X with its 32-bit floating-point value).
The addressing mode combination "TOS, TOS" is an exception, and is allowed. This is because the least-significant part of the result is written to the possibly invalid
page before the source operand is affected. Also, integer
conversions to larger integers always work correctly in
place, because the low-order portion of the result always
matches the source value.
c) When performing the MOVM instruction, the entire
source and destination blocks must be considered "operands" as above, and they must not overlap.
PHil
PHI2
TLlEE/8692-5
FIGURE 2·2. Clock Timing Relationships
As the TCU presents signals with very fast tranSitions, it is
recommended that the conductors carrying PHI1 and PHI2
be kept as short as possible, and that they not be connected to any devices other than the CPU and MMU. A TTL
Clock signal (CTTL) is provided by the TCU for all other
clocking.
3-46
z
2.0 Functional Description
rn
Co)
I\,)
(Continued)
2.3 RESETTING
2.4 BUS OPERATION
The ASTI input pin is used to reset the NS32082. The MMU
responds to ASTI by terminating processing, resetting its
internal logic and clearing the appropriate bits in the MSR
register.
Only the MSR register is changed on reset. No other program accessible registers, including the TLB are affected.
The RSTI ABT signal is activated by the MMU on reset. This
signal should be used to reset the CPU. AT/SPC is held low
for five clock cycles after the rising edge of RSTI to indicate
to the CPU that the address translation mode must be selected.
2.4.1 Interconnections
c
00
The MMU runs synchronously with the CPU, sharing with it a
single multiplexed addressl data bus. The interconnections
used by the MMU for bus control, when used in conjunction
with the NS32016, are shown in Figure A-l (Appendix A).
The CPU issues 24-bit virtual addresses on the bus, and
status information on other pins, pulsing the signal ADS low.
These are monitored by the MMU. The MMU issues 25-bit
physical addresses on the bus, pulsing the PAV line low.
The PAV pulse triggers the address latches and signals the
NS32201 TCU to begin a bus cycle. The TCU in turn generates the necessary bus control Signals and synchronizes
the insertion of WAIT states, by providing the signal RDY to
the MMU and CPU. Note that it is the MMU rather than the
CPU that actually triggers bus activity in the system.
The A24/HBF signal is sampled by the MMU on the rising
edge of ASTI. It indicates the bus size of the attached CPU.
A24/HBF must be sampled high for a 16-bit bus and low for
a 32-bit bus.
On application of power, RSTI must be held low for at least
50 }Jos after Vee is stable. This is to ensure that all on-chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 clock cycles. The rising edge must occur while PHI1
is high. See Figures 2-3 and 2-4.
The functions of other interface signals used by the MMU to
control bus activity are described below.
The STO-ST3 pins indicate the type of cycle being initiated
by the CPU. STO is the least-significant bit of the code. Table 2-1 shows the interpretations of the status codes presented on these lines.
The NS32201 Timing Control Unit (TCU) provides circuitry
to meet the Reset requirements of the NS32082 MMU. Figure 2-5 shows the recommended connections.
VCC
PHil
----1-----'
I
~64CLOCK
I-" CYCLES
Jl-JL
PHI1~JUl
t--- ~64CLOCK-1
Rsn----4---------------1~
RSn---""'~"""'~
C~CLES
1-"---1!:50jAsec --~.,
I
TLIEE18692-7
FIGURE 2·4. General Reset Timing
TLIEE18692-6
FIGURE 2·3. Power·On Reset Requirements
Vee
NS32201
NS32082
SERIES 32000
TCU
MMU
CPU
r---------,
I
I
RESET
1>--1-+-.......;.-+-"""""-....--+1 nSTI
1L _________ .JI
I
RSTO
EXTERNAL RESET
(OPTIONAL)
~5Ql'sec
RESET SWITCH
(OPTIONAL)
TLIEEIB692-B
FIGURE 2·5. Recommended Reset Connections, Memory·Managed System
3-47
~
......
c
2.0 Functional Description
(Continued)
contents of the status bits (R and M) in the Page Table
Entries, and for implementing bus timing adjustments needed by the debugging features.
The MMU also aborts invalid accesses attempted by the
CPU. This is done by pulsing the RSTI ABT pin low for one
clock period. (A pulse longer than one clock period is interpreted by the CPU as a Reset command).
Status codes that are relevant to the MMU's function during
a memory reference are:
1000,1001 Instruction Fetch status, used by the debugging features to distinguish between data and
instruction references.
1010
Data Transfer. A data value is to be transferred.
Because the MMU performs only 16-bit transfers, some additional circuitry is needed to interface it to the 32-bit data
bus of an NS32032-based system. However, since the
MMU never writes to the most-significant word of a Page
Table Entry, the only special requirement is that it must be
able to read from the top half of the bus. This can be accomplished as shown in Figure A-2 (Appendix A) by using a
16-bit unidirectional buffer and some gating circuitry that enables it whenever an MMU-initiated bus cycle accesses an
address ending in binary "1 0".
The bus connections required in conjunction with the
NS32332 CPU are somewhat more complex (see the
NS32332 data sheet), but the sequences of events documented here still hold.
1011
Read RMW Operand. Although this is always
a Read cycle, the MMU treats it as a Write
cycle for purposes of protection and breakpointing.
1100
Read for effective address. Data used for address calculation is being transferred.
All other status codes are treated as data accesses if they
occur in conjunction with a pulse on the ADS pin. Note that
these include Interrupt Acknowledge and End of Interrupt
cycles performed by the CPU. The status codes 1101, 1110
and 1111 are also recognized by the MMU in conjunction
with pulses on the SPC line while it is executing Slave Processor instructions, but these do not occur in a context relevant to address translation.
2.4.2 CPU-Initiated Bus Cycles
A CPU-initiated bus cycle is performed in a minimum of five
clock cycles (four in the case of the NS32332): T1, TMMU,
T2, T3 and T4, as shown in Figure 2-6.
TABLE 2-1. STO-ST3 Encodings
(STO Is the Least Significant)
0000 -Idle: CPU Inactive on Bus
0001 -Idle: WAIT Instruction
0010- (Reserved)
0011 -Idle: Waiting for Slave
0100 - Interrupt Acknowledge, Master
0101 -Interrupt Acknowledge, Cascaded
0110- End of Interrupt, Master
0111 - End of Interrupt, Cascaded
1000 - Sequential Instruction Fetch
1001 - Non-Sequential Instruction Fetch
1010- Data Transfer
1011 - Read Read-Modify-Write Operand
1100 - Read for Effective Address
1101 - Transfer Slave Operand
1110- Read Slave Status Word
1111 - Broadcast Slave 10
During period T1, the CPU places the virtual address to be
translated on the bus, and the MMU latches it internally and
begins translation. The MMU also samples the ODIN pin,
the status lines STO-ST3, and the U/S pin to determine
how the CPU intends to use the bus.
During period TMMU the CPU floats its bus drivers and the
MMU takes one of three actions:
1) If the translation for the virtual address is resident in the
MMU's TLB, and the access being attempted by the CPU
does not violate the protection level of the page being
referenced, the MMU presents the translated address
and generates a PAY pulse to trigger a bus cycle in the
rest of the system. See Figure 2-6.
2) If the translation for the virtual address is resident in the
MMU's TLB, but the access being attempted by the CPU
is not allowed due to the protection level of the page
being referenced, the MMU generates a pulse on the
RST/ABT pin to abort the CPU's access. No PAY pulse
is generated. See Figure 2-7.
The ODIN line indicates the direction of the transfer: 0 =
Read, 1 = Write.
ODIN is monitored by the MMU during CPU cycles to detect
write operations, and is driven by the MMU during MMU-initiated bus cycles.
The U/S pin indicates the privilege level at which the CPU is
making the access: 0 = Supervisor Mode, 1 = User Mode.
It is used by the MMU to select the address space for translation and to perform protection level checking. Normally,
the U/S pin is a direct reflection of the U bit in the CPU's
Processor Status Register (PSR). The MOVUS and MOVSU
CPU instructions, however, toggle this pin on successive
operand accesses in order to move data between virtual
spaces.
3) If the translation for the virtual address is not resident in
the TLB, or if the CPU is writing to a page whose M bit is
not yet set, the MMU takes control of the bus asserting
the FLT signal as shown in Figure 2-8. This causes the
CPU to float its bus and wait. The MMU then initiates a
sequence of bus cycles as described in Section 2.4.3.
From state T2 through T4 data is transferred on the bus
between the CPU and memory, and the TCU provides the
strobes for the transfer. During this time the MMU floats
The MII.;U uses the FLT line to take control of the bus from
the CPU. It does so as necessary for updating its internal
TLB from the Page Tables in memory, for maintaining the
3-48
z
2.0 Functional Description
(J)
W
N
(Continued)
pins ADO-AD15, and handles pins A16-A24 according to
the mode of operation (16-bit or 32-bit) selected during reset (Section 2.3).
2) There is a translation for that virtual address in the TLB,
but the page is being written for the first time (the M bit in
its Level-2 Page Table Entry is 0). The MMU treats this
case as if there were no translation in the TLB, and performs a Page Table lookup in order to set the M bit in the
Level-2 Page Table Entry as well as in the TLB.
In 16-bit bus mode, the MMU drives address lines A 16-A24
from TMMU through T4 and they need not be latched externally. This is appropriate for the NS32016 CPU, which uses
only ADO-AD15 for data transfers. In 32-bit bus mode, the
MMU asserts the physical address on pins A16-A24 only
during TMMU, and floats them from T2 through T4 because
the CPU uses them for data transfer. In this case the physical address presented on these lines must be latched externally using PAY.
During the Page Table lookup the MMU drives the DDIN
signal. The status lines STO-ST3 and the U/S pin are not
released by the CPU, and retain their original settings while
the MMU uses the bus. The Byte Enable signals from the
CPU (HBE in 16-bit systems, BEO-BE3 in 32-bit systems)
should in general be handled externally for correct memory
referencing. (The current NS32016 CPU does, however,
handle HBE in a manner that is acceptable in many systems
at clock rates of 12.5 MHz or less.)
Bus cycles initiated by the MMU are always nested within
CPU-initiated bus cycles; that is, they appear after the MMU
has accepted a virtual address from the CPU and has set
the FLT line active. The MMU will initiate memory cycles in
the following cases:
In the clock cycle immediately after T4 of the last lookup
cycle, the MMU removes the FLT signal, issues the translated address, and pulses PAY to continue the CPU's access.
1) There is no translation in the MMU's TLB for the virtual
address issued by the CPU, meaning that the MMU must
reference the Page Tables in memory to obtain the translation.
TI
.....
Figure 2-8 shows the sequence of events in a Page Table
lookup. After asserting FLT, the MMU waits for one additional clock cycle, then reads the Level-1 Page Table Entry and
the Level-2 Page Table Entry in four consecutive memory
Read cycles. Note that the MMU performs two 16-bit transfers to read each Page Table Entry, regardless of the width
of the CPU's data bus. There are no idle clock cycles between MMU-initiated bus cycles unless a bus request is
made on the HOLD line (Section 2.6).
2.4.3 MMU·lnitiated Cycles
n
~
Q
Having made the necessary memory references, the MMU
either aborts the CPU access or it provides the translated
address and allows the CPU's access to continue to T2.
Whenever the MMU generates an Abort pulse on the
RST I ABT pin, the CPU enters state T2 and then Ti (idle),
ending the bus cycle. Since no PAY pulse is issued by the
MMU, the rest of the system remains unaware that an access has been attempted. The MMU requires that no further
memory references be attempted by the CPU for at least
two clock cycles after the T2 state, as shown in Figure 2-7.
This requirement is met by all Series 32000 CPU's. During
this time, the RDY line must remain high. This requirement
is met by the NS32201 TCU.
T4 OR
Q
ao
Note that when the MMU sets FLT active, the clock cycle
originally called TMMU is redesignated Tf. Clock cycles in
which the PAY pulse occurs are designated TMMU.
TMMU
T2
T4
T3
PHil [
lWL-1"L -1"L WL WL WL J
PHI2 [
X v. ADDR. X
I .__ h.
X V.ADDR. ~Rj-----
A16-24 [
ADO-IS [
--<
-
X
PH. ADDR.
DATA IN
--
&I
-c
ADS [
PAY [
Ir
ODIN [
m[
(HIGH)
-~
u/s [ .-,.....-
X
-~
.-,.....-
X
STO-3 [
TLlEE/B692-9
FIGURE 2-6. CPU Read Cycle; Translation in TLB (TLB Hit)
3-49
2.0 Functional Description
(Continued)
T1
TWWU
T2
T4
13
n
T1 OR
c=
-------- c=
(HIGH)
RSi'/m[
m[
\~_~/(2)
HOL6[
(BY CPU)
RDY[
TL/EE/8692-10
Note 1: The CPU drives the bus If a write cycle is aborted.
Note 2: FLT may ba pulsed if a breakpoint on physical address is enabled or an execution breakpoint is triggered.
Note 3: If this bus cycle is a write cycle to a write-protected page, FLT is asserted for two clock cycles and the abort pulse is delayed by one clock cycle.
FIGURE 2·7. Abort Resulting from Protection Violation; Translation In TLB
ITf...
I
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I
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I
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-'Ul Jl Jl Jl Jl Jl Jl Ul U1 Ul Ul.Jl Ul U1 U1 Jl Ul 11U1 Ul ~ Jl11U1
x:P£~ ~. ifl- ·~A~· f~- ·~R· 'f~- fSR· f~- ·~R 1('"1 X
CPU ACCESS
T1 Tf T1
CPU
STATES
WWU
STATES
L.S. WORD PTE. t
M.S. WORD PTE. I
L.S. WORD PTE.21 M.S. WORD PTE.21
CPU ACCESS
T3 14
Tf ntt.4U T2
TI I·Tf 1 Tf l\IM~ T2 1 T3 1 T4 TMM~ T2 1 T3 1 T4 TMM~ T2 1 T3 1T4 TMM~ 12 1 T3 1 T4 TMW~ T2 1 T3 1T4
PHI1[
PHI2[
BUS[
PH."AD.
DATA OUT
'-~
V
IV
'--
IV
V
1\
V
I
I
\
\. t--
V- r- I\- .r - \.. - r t-- rL r-~
I-
\r- I{
(3)
(I)
Note 1: If the R bit on the Level-' PTE must be set, a write cycle is inserted here.
Note 2: If enher the R or the M bit on the Level-2 PTE must be set, a write cycle is inserted here.
Note 3: If a breakpoint on physical address is enabled, an extra clock cycle is inserted here.
FIGURE 2·8. Page Table Lookup
3-50
-
TL/EE/8692-11
2.0 Functional Description
(Continued)
In Figures 2-6 and 2-8, note that during T3 all bus control
signals are flat. Therefore, a bus cycle can be cleanly extended by causing the T3 state to be repeated. This is the
purpose of the ROY (Ready) pin.
The Page Table Entries are read starting with the low-order
word. If the V bit (bit 0) of the low-order word is zero, or the
protection level field PL (bits 1 and 2) indicates that the
CPU's attempted access is illegal, the MMU does not generate any further memory cycles, but instead issues an Abort
pulse during the clock cycle after T4 and removes the FLT
signal. The CPU continues to T2 and then becomes idle on
the bus, as shown in Figure 2-9.
Immediately before T3 begins, on the falling edge of clock
phase PHI2, the ROY line is sampled by the CPU and/or the
MMU. If ROY is high, the next state after T3 will be T4,
ending the bus cycle. If it is low, the next state after T3 will
be another T3 and the ROY line will be sampled again. ROY
is sampled in each following clock period, with insertion of
additional T3 states, until it is sampled high. Each additional
T3 state inserted is called a "WAIT state."
If the Rand/or M bit (bit 3 or 4) of the low-order word must
be updated, the MMU does this immediately in a single
Write cycle, before reading the high-order word of the Page
Table Entry. All bits except those updated are rewritten with
their original values.
During CPU bus cycles, the MMU monitors the ROY pin only
if the 16-bit mode is selected. This is necessary since the
MMU drives the address lines A16-A24, and needs to detect the end of the bus cycle in order to float them.
At most, the MMU writes two 16-bit words to memory during
a translation: the first to the Level-I table to update the R
bit, and the second to the Level-2 table to update the R
and/ or M bits.
If the 32-bit mode is selected, the above address lines are
floated following the TMMU state. The MMU will be ready to
perform another translation after three clock cycles, and the
ROY line is ignored.
2.4.4 Cycle Extension
To allow sufficient strobe widths and access time requirements for any speed of memory or peripheral device, the
NS32082 provides for extension of a bus cycle. Any type of
bus cycle, CPU-initiated or MMU-initiated, can be extended,
except Slave Processor cycles, which are not memory or
peripheral references.
The ROY pin is driven by the NS32201 Timing Control Unit,
which applies WAIT states to the CPU and MMU as requested on its own WAIT request input pins.
c
c
II
(BY CPU)
TL/EE/8692-12
Note 1: If a breakpoint on physical address is enabled, an extra clock cycle is inserted here.
FIGURE 2-9. Abort Resulting after a Page Table Lookup
3-51
C)
..-
~
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~
C")
rn
z
r---------------------------------------------------------------------------------,
2.0 Functional Description (Continued)
2.5 SLAVE PROCESSOR INTERFACE
The CPU and MMU execute four instructions cooperatively.
These are LMR, SMR, RDVAL and WRVAL, as described in
Section 2.5.2. The MMU takes the role of a Slave Processor
in executing these instructions, accepting them as they are
issued to it by the CPU. The CPU calculates all effective
addresses and performs all operand transfers to and from
memory and the MMU. The MMU does not take control of
the bus except as necessary in normal operation; i.e., to
translate and validate memory addresses as they are presented by the CPU.
The sequence of transfers ("protocol") followed by the CPU
and MMU involves a special type of bus cycle performed by
the CPU. This "Slave Processor" bus cycle does not involve
the issuing of an address, but rather performs a fast data
transfer whose purpose is pre-determined by the form of the
instruction under execution and by status codes asserted by
the CPU.
transfers, and is also pulsed low by the MMU to acknowledge, when necessary, that it is ready to continue execution
of an MMU instruction. Since SPC is normally in a high-impedance state, it must be pulled high with a 10 kO resistor,
as shown. The MMU also monitors the status lines STOST3 to follow the protocol for the instruction being executed.
Data is transferred between the CPU and the MMU with
Slave Processor bus cycles, illustrated in Figures 2-10 and
2-11. Each bus cycle transfers one byte or one word (16
bits) to or from the MMU.
Slave Processor bus cycles are performed by the CPU in
two clock periods, which are labeled T1 and T4. During T1,
the CPU activates SPC and, if it is writing to the MMU, it
presents data on the bus. During T 4, the CPU deactivates
SPC and, if it is reading from the MMU, it latches data from
the bus. The CPU guarantees that data written to the MMU
is held through T4 to provide for the MMU's hold time requirements. The CPU also guarantees that the status code
on STO-ST3 becomes valid, at the latest, during the clock
period preceding T1. The status code changes during T4 to
antiCipate the next bus cycle, if any.
2.5.1 Slave Processor Bus Cycles
The interconnections between the CPU and MMU for Slave
Processor communication are shown in Figures A-1 and A-2
(Appendix A). The low-order 16 bits of the bus are used for
data transfers. The SPC signal is bidirectional. It is pulsed by
the CPU as a low-active data strobe for Slave Processor
Note that Slave Processor bus cycles are never extended
with WAIT states. The RDY line is not sampled.
PREV.CYCLE
I
PHil
[
PHI2
[
SPC
[
ADO-AD15
[
STO-ST3
[
ADS
[
iiiiiN
[
T40RTi
NEXT CYCLE
T1
T4
T1 ORTi
I
TL/EE/8692-13
Note 1: CPU samples Dala Bus here.
FIGURE 2-10. Slave Access Timing; CPU Reading from MMU
3-52
z
2.0 Functional Description (Continued)
PREVo CYCLE
I
PHil
[
PHI 2
[
SPC
[
AOO-AD15
[
STO-ST3
[
ADS
[
ODiN
[
en
w
I
~
T1
T40RTI
o
co
NEXT CYCLE
T4
T1 aRT;
~
I
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o
VALID
TL/EE/8692-14
Note 1: MMU samples Data Bus here.
FIGURE 2·11. Slave Access Timing; CPU Writing to MMU
In executing the SMR instruction (Store MMU Register, Table 2-3), the CPU also issues the ID Byte and the Operation
Word of the instruction to the MMU. It then waits for the
MMU to signal (by pulsing SPC low) that it is ready to present the specified register's contents to the CPU. Upon receiving this "Done" pulse, the CPU reads first a "Status
Word" (dictated by the protocol for Slave Processor instructions) which the MMU provides as a word of all zeroes. The
CPU then reads the contents of the selected register in two
successive Slave Processor bus cycles, and places this result value into the instruction's destination (a CPU generalpurpose register or a memory location).
In executing the RDVAL (Read-Validate) or WRVAL (WriteValidate) instruction, the CPU again issues the ID Byte and
the Operation Word to the MMU. However, its next action is
to initiate a one-byte Read cycle from the memory address
whose protection level is being tested. It does so while presenting status code 1010; this being the only place that this
status code appears during a RDVAL or WRVAL instruction.
This memory access triggers a special address translation
from the MMU. The translation is performed by the MMU
using User-Mode mapping, and any protection violation occurring during this memory cycle does not cause an Abort.
The MMU will, however, abort the CPU if the Level-1 Page
Table Entry is invalid.
2.5.2 Instruction Protocols
MMU instructions have a three-byte Basic Instruction field
conSisting of an ID byte followed by an Operation Word. See
Figure 3-10 for the MMU instruction encodings. The ID Byte
has three functions:
1) It identifies the instruction as being a Slave Processor
instruction.
2) It specifies that the MMU will execute it.
3) It determines the format of the following Operation Word
of the instruction.
The CPU initiates an MMU instruction by issuing first the ID
Byte and then the Operation Word, using Slave Processor
bus cycles. The ID Byte is sent on the least-significant byte
of the bus, in conjunction with status code 1111 (Broadcast
ID Byte). The Operation Word is sent on the entire 16-bit
data bus, with status code 1101 (Transfer Operation Word I
Operand). The Operation Word is sent with its bytes
swapped; i.e., its least-significant byte is presented to the
MMU on the most-significant half of the 16-bit bus.
Other actions are taken by the CPU and the MMU according
to the instruction under execution, as shown in Tables 2-2,
2-3 and 2-4.
In executing the LMR instruction (Load MMU Register, Table 2-2), the CPU issues the ID Byte, the Operation Word,
and then the operand value to be loaded by the MMU. The
register to be loaded is specified in a field within the Operation Word of the instruction.
Upon completion of the address translation, the MMU pulses SPC to acknowledge that the instruction may continue
execution.
3-53
•
2.0 Functional Description (Continued)
TABLE 2·2. LMR Instruction Protocol
CPU Action
Issues ID Byte of instruction, pulsing SPC.
Sends Operation Word of Instruction, pulsing SPC.
Issues low-order word of new register value to
MMU, pulsing SPC.
Issues high-order word of new register value to
MMU, pulsing SPC.
Status
MMUAction
1111
1101
1101
Accepts ID Byte.
Decodes instruction.
Accepts word from bus; places it into low-order half
of referenced MMU register.
Accepts word from bus; places it into high-order
half of referenced MMU register.
1101
TABLE 2·3. SMR Instruction Protocol
CPU Action
MMUAction
Status
Issues ID Byte of Instruction, pulsing SPC.
Sends Operation Word of instruction, pulsing SPC.
Waits for Done pulse from MMU.
Pulses SPC and reads Status Word from MMU.
Pulses SPC, reading low-order word of result from
MMU.
Pulses SPC, reading high-order word of result from
MMU.
1111
1101
xxxx
1110
1101
1101
Accepts ID Byte.
Decodes instruction.
Sends Done pulse on SPC.
Presents Status Word (all zeroes) on bus.
Presents low-order word of referenced MMU
register on bus.
Presents high-order word of referenced MMU
register on bus.
TABLE 2-4. RDVAL/WRVAL Instruction Protocol
Status
MMUAction
Issues ID Byte of instruction, pulsing SPC.
Sends Operation Word of instruction, pulsing SPC.
Performs dummy one-byte memory read from
operand's location.
CPU Action
1111
1101
1010
Waits for Done pulse from MMU
Sends SPC pulse and reads Status Word from
MMU; places bit5 of this word into the F bit of the
PSR register.
xxxx
1110
Accepts ID Byte.
Decodes instruction.
Translates CPU's address, using User-Mode
mapping, and performs requested test on the
address presented by the CPU. Aborts the CPU if
the level-1 page table entry is invalid. Starts a
Memory Cycle from the Translated Address if the
translation is successful. Aborts on protection
violations are temporarily suppressed.
Sends Done pulse on SPC.
Presents Status Word on bus, indicating in bit 5 the
result of the test.
If the translation is successful the MMU will also start a
dummy memory cycle from the translated address. See Figure 2-12. Note that, during this time the CPU will monitor the
RDY line. Therefore, for proper operation, the RDY line
must be kept high if the memory cycle is not performed.
Requests for DMA are presented in parallel to both the CPU
and MMU on the HOLD pin of each. The component that
currently controls the bus then activates its Hold Acknowledge output to grant bus access to the requesting device.
When the CPU grants the bus, the MMU passes the CPU's
HLDA signal to its own HLDAO pin. When the MMU grants
the bus, it does so by activating its HLDAO pin directly, and
the CPU is not involved. HLDAI in this case is ignored.
The CPU then reads from the MMU a Status Word. Bit 5 of
this Status Word indicates the result of the instruction:
o if the CPU
in User Mode could have made the corresponding access to the operand at the specified address (Read in RDVAL, Write in WRVAL),
Refer to Figures 4-14, 4-15 and 4-16 for details on bus
granting sequences.
1 if the CPU would have been aborted for a protection
violation.
2.7 BREAKPOINTING
The MMU provides the ability to monitor references to two
memory locations in realtime, generating a Breakpoint trap
on occurrence of any specified type of reference to either
location made by a program. In addition, a Breakpoint trap
may be inhibited until a specified number of such references
have been performed.
Bit 5 of the Status Word is placed by the CPU into the F bit
of the PSR register, where it can be tested by subsequent
instructions as a condition code.
Note: The MMU sets the R bit on ROVAL; Rand M bits on WRVAL.
2.6 BUS ACCESS CONTROL
Breakpoint monitoring is enabled and regulated by the setting of appropriate bits in the MSR and BPRO-1 registers.
See Sections 3.5 and 3.7.
The NS320B2 MMU has the capability of relinquishing its
access to the bus upon rquest from a DMA device. It does
this by using HOLD, HLDAI and HLDAO.
A Breakpoint trap is signalled to the CPU as either a NonMaskable Interrupt or an Abort trap, depending on the setting of the AI bit in the MSR register.
Details on the interconnections of these pins are provided in
Figures A-1 and A-2 (Appendix A).
3-54
Z
2.0 Functional Description
CPU STATES
MMU STATES
tn
(0)
(Continued)
N
o
I
T2
T3
T4
T2
T3
T4
CD
...
~
o
PHil [
PHI2 [
ADS [
FU[-+...............t-..........~..........~....._(I_).....+'
SPC [
RST/ ABT [
ROY [
(3)
TLlEE/8692-15
Note 1: FLT is asserted if the translation is not in the TLB or a WRVAL instruction is executed and the M Bit is not set.
Note 2: If the Level-t PTE is not valid, an abort is generated, SPC is issued in TMMU and FLT is deasserted in T 2.
Note 3: If a protection violation occurs or the Level-2 PTE is invalid, an Idle State is inserted here, PAV is not pulsed and SPC is pulsed during this Idle State.
FIGURE 2·12. FLT Deassertlon During RDVAL/WRVAL Execution
The MSR register also indicates which breakpoint register
triggered the break, and the direction (read or write) and
type of memory cycle that was detected. The breakpoint
address is not placed into the EIA register, as this register
holds the addresses of address translation errors only. The
breakpoint address is, however, available in the indicated
Breakpoint register.
On occurrence of any trap generated by the MMU, including
the Breakpoint trap, the BEN bit in the MSR register is immediately cleared, disabling any further Breakpoint traps.
Enabling breakpoints may cause variations in the bus timing
given in the previous sections. Specifically:
2.7.1 Breakpoints on Execution
The Series 32000 CPUs have an instruction prefetch which
requires synchronization with execution breakpoints. In consideration of this, the MMU only issues an execution breakpoint when an instruction is prefetched with a nonsequential
status code and the conditions specified in a breakpoint register are met. This guarantees that the instruction prefetch
queue is empty and there are not pending instructions in the
pipeline. There are three cases to consider:
Case 1:
A nonsequential instruction prefetch is made to
a breakpointed address.
Response: The queue is necessarily empty. The breakpoint
is issued.
Case 2, 3: A sequential prefetch is made to a breakpointed
address OR a prefetch is made to an even address and the breakpoint is on the next odd address.
Response: In these cases, there may be instructions pending in the queue which must finish before the
breakpoint is fired. Instead of putting the opcode byte (the one specified by the breakpointed address) in the queue, a DIA instruction is
substituted for it. DIA is a single byte instruction
which branches to itself, causing a queue flush.
When the DIA executes, the breakpoint address
is again issued, this time with nonsequential
fetch status and the problem is reduced to
case 1.
1) While either breakpoint is enabled to monitor physical addresses, the MMU inserts an additional clock period into
all bus cycles by asserting the FLT line for one clock. See
Figure 2-13.
2) If the CPU initiates an instruction prefetch from a location
at which a breakpoint is enabled on Execution, the MMU
asserts the FLT line to the CPU, performs the memory
cycle itself, and issues an edited instruction word to the
CPU. See Figure 2-14 and Section 2.7.1.
Note: Instructions which use two operands, a read-type and a write-type
(e.g., MOVO 0(rl).0(r2), with the first operand valid and protected to
allow user reads, and the second operand either invalid (page fault) or
write protected, cause a read-type break event to occur for the first
operand regardless of the outcome of the instruction. Each time the
instruction is retried, the read-event is recorded. Hence, the break·
point count register may reflect a different count than a casual assumption would lead one to. The same effect can occur on a RMW
type operand with read only protection.
Note: Execution breakpoints cannot be used when the MMU is connected
to either an NS32032 or an NS32332 CPU.
3-55
~
N
!
2.0 Functional Description
(Continued)
~
z
Tl
TMMU
T2
Tf
T4
T3
_...•
.'. - -- --_.'.
•'.. _-- ..'•
TLlEE/8692-16
Note: If a breakpoint condition is met and abort on breakpoint is enabled. the bus cycle is aborted. In this case FLT is stretched by one clock cycle.
FIGURE 2·13. Bus Timing with Breakpoint on Physical Address Enabled
CPU STATES
MMU STATES
I
Tl
Tl
TMMU
TMMU
Tf
T2
Tf
T3
T2
T4
T3
11
T4
11
Tl OR 11
I TlOR11
PHil [
PHI2[
A1S-24[
~~---
AOO-1S[
-c
AOS[
PAVe
FLT[
RD[
(BY CPU)
ROY[
(1)
TL/EE/8692-17
Note 1: If a breakpoint on physical address is enabled. an extra clock cycle is inserted here.
FIGURE 2·14. Execution Breakpoint Timing; Insertion of DIA Instruction
3-56
.--------------------------------------------------------------------------,z
(J)
3.0 Architectural Description
Co)
N
3.1 PROGRAMMING MODEL
The MMU contains a set of registers through which the CPU
controls and monitors management and debugging func·
tions. These registers are not memory· mapped. They are
examined and modified by executing the Slave Processor
instructions LMR (Load Memory Management Register) and
SMR (Store Memory Management Register). These instruc·
tions are explained in Section 3.11, along with the other
Slave Processor instructions executed by the MMU.
A brief description of the MMU registers is provided below.
Details on their formats and functions are provided in the
following sections.
3.2 MEMORY MANAGEMENT FUNCTIONS
The NS32082 uses sets of tables in physical memory (the
"Page Tables") to define the mapping from virtual to physical addresses. These tables are found by the MMU using
one of its two Page Table Base registers: PTBO or PTB1.
Which register is used depends on the currently selected
address space. See Section 3.2.2.
o(X)
....
N
o
3.2.1. Page Table Structure
The page tables are arranged in a two·level structure, as
shown in Figure3-f. Each of the MMU's PTBn registers may
point to a Level-1 page table. Each entry of the Level·1
page table may in turn point to a Level-2 page table. Each
Level-2 page table entry contains translation information for
one page of the virtual space.
The Level·1 page table must remain in physical memory
while the PTBn register contains its address and translation
is enabled. Level-2 Page Tables need not reside in physical
memory permanently. but may be swapped into physical
memory on demand as is done with the pages of the virtual
space.
The Level-1 Page Table contains 256 32-bit Page Table
Entries (PTE'S) and therefore occupies 1 Kbyte. Each entry
of the Level·1 Page Table contains fields used to construct
the physical base address of a Level-2 Page Table. These
fields are a 15·bit PFN field, providing bits 9-23 of the physical address, and an MS bit providing bit 24. The remaining
bits (0-8) are assumed zero, placing a Level·2 Page Table
always on a 512-byte (page) boundary.
PTBO, PTB1-Page Table Base Registers. They hold the
physical memory addresses of the Page Tables referenced
by the MMU for address translation. See Section 3.3.
EIA-Errorllnvalidate Register. Dual·function register.
used to display error addresses and also to purge cached
translation information from the TLB. See Section 3.4.
BPRO, BPR1-Breakpoint Registers. Specify the condi·
tions under which a breakpoint trap is generated. See Sec·
tion 3.5.
BCNT-Breakpoint Counter Register. 24·bit counter used
to count BPRO events. Allows the breakpoint trap from the
BPRO register to be inhibited until a specified number of
events have occurred. See Section 3.6.
MSR-Memory Management Status Register. Contains
basic control and status fields for all MMU functions. See
Section 3.7.
-32BITSPTBn
~_m-
512 BYTES
I
•
256
ENTRIES
1
.
LEVEL·1
PAGE TABLE
MEMORY
LEVEL·2
PAGE TABLES
TL/EE/8692-18
FIGURE 3·1. Two·Level Page Tables
3-57
.... r--------------------------------------------------------------------------,
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3.0 Architectural Description
(Continued)
Level-2 Page Tables contain 128 32-bit Page Table entries,
and so occupy 512 bytes (1 page). Each Level-2 Page Table
Entry points to a final 512-byte physical page frame. In other
words, its PFN and MS fields provide the Page Frame Number portion (bits 9-24) of the translated address (Figure 3-3).
The OFFSET field of the translated address is taken directly
from the corresponding field of the virtual address.
The PL field is modified only by software. In a Level-1
PTE, it limits the maximum access level allowed for all
pages mapped through that PTE.
TABLE 3·1 Access Protection Levels
Mode
3.2.2 Virtual Address Spaces
When the Dual Space option is selected for address transla·
tion in the MSR (Sec. 3.7) the MMU uses two maps: one for
translating addresses presented to it in Supervisor Mode
and another for User Mode addresses. Each map is referenced by the MMU using one of the two Page Table Base
registers: PTBO or PTB1. The MMU determines the CPU's
current mode by monitoring the state of the UIS pin and
applying the following rules.
1) While the CPU is in Supervisor Mode (U/S pin = 0), the
CPU is said to be presenting addresses belonging to Address Space 0, and the MMU uses the PTBO register as
its reference for looking up translations from memory.
2) While the CPU is in User Mode (U/S pin = 1), and the
MSR OS bit is set to enable Dual Space translation, the
CPU is said to be presenting addresses belonging to Address Space 1, and the MMU uses the PTB1 register to
look up translations.
3) If Dual Space translation is not selected in the MSR,
there is no Address Space 1, and all addresses presented in both Supervisor and User modes are considered by
the MMU to be in Address Space O. The privilege level of
the CPU is used then only for access level checking.
01
10
11
1
no
access
no
access
read
only
full
access
Supervisor
a
read
only
full
access
full
access
full
access
00
Referenced. This is a status bit, set by the MMU and
cleared by the operating system, that indicates whether the page mapped by this PTE has been referenced
within a period of time determined by the operating
system. It is intended to assist in implementing memory allocation strategies. In a Level-1 PTE, the R bit
indicates only that the Level-2 Page Table has been
referenced for a translation, without necessarily implying that the translation was successful. In a Level-2
PTE, it indicates that the page mapped by the PTE
has been successfully referenced.
R = 1 => The page has been referenced since the R
bit was last cleared.
R = a=> The page has not been referenced since the
R bit was last cleared.
Note: The RDVAL and WRVAL instructions set the Level-l and Level-2 bits
for the page whose protection level Is tested. See Sections 2.5.2 and
3.11.
M
Modified. This is a status bit, set by the MMU whenever a write cycle is successfully performed to the page
mapped by this PTE. It is initialized to zero by the
operating system when the page is brought into physical memory.
M = 1 => The page has been modified since it was
last brought into physical memory.
M = a=> The page has not been modified since it
was last brought into physical memory.
3.2.3 Page Table Entry Formats
Figure 3-2 shows the formats of Level-1 and Level-2 Page
Table Entries (PTE's). Their formats are identical except for
the "M" bit, which appears only in a Level-2 PTE.
In Level-1 Page Table Entries, this bit pOSition is undefined, and is altered in an undefined manner by the
MMU while the V bit is 1.
The bits are defined as follows:
PL
Protection Level Bits (PL)
User
R
Note: When the CPU executes a Dual-Space Move instruction (MOVUSi or
MOVSUi), it temporanly enters User Mode by switching the slste of
the U/S pin. Accesses made by the CPU during this time are treated
by the MMU as User-Mode accesses for both mapping and access
level checking. It is pOSSible, however, to force the MMU to assume
Supervisor-Mode privilege on such accesses by selting the Access
Overnde (AO) bit in the MSR (Sec. 3.7).
V
U/S
Note: The WRVAL instruction sets the M bit for the page whose protection
level is tested. See Sections 2.5.2 and 3.11.
Valid. The V bit is set and cleared only by software.
V= 1 => The PTE is valid and may be used for translation by the MMU.
NSC Reserved. These bits are ignored by the MMU and
their values are not changed.
V=O=> The PTE does not represent a valid translation. Any attempt to use this PTE will cause
the MMU to generate an Abort trap. While
V = 0, the operating system may use all other bits except the PL field for any desired
function.
Protection Level. This two-bit field establishes the
types of accesses permitted for the page in both User
Mode and Supervisor Mode, as shown in Table 3-1.
They are reserved by National, and therefore should
not be used by the user software.
USR User bits. These bits are ignored by the MMU and
their values are not changed.
They can be used by the user software.
TUEE/8692-19
FIGURE 3·2. A Page Table Entry
3-58
3.0 Architectural Description
(Continued)
PFN Page Frame Number. This 15-bit field provides bits
9-23 of the Page Frall]e Number of the physical address. See Figure 3-3.
virtual Page Number field is further divided into two fields,
INDEX 1 and INDEX 2.
Bits 0-8 constitute the OFFSET field, which identifies a
byte's position within the accessed page. Since the byte
position within a page does not change with translation, this
value is not used, and is simply echoed by the MMU as bits
0-8 of the final physical address.
MS Memory System. This bit represents the most significant bit of the physical address, and is presented by
the MMU on pin A24. This bit is treated by the MMU no
differently than any other physical address bit, and can
be used to implement a 32-Mbyte physical addressing
space if desired.
The 8-bit INDEX 1 field of the virtual address is used as an
index into the Level-1 Page Table, selecting one of its 256
entries. The address of the entry is computed by adding
INDEX 1 (scaled by 4) to the contents of the current Page
Table Base register. The PFN and MS fields of that entry
give the base address of the selected Level-2 Page Table.
3.2.4 Physical Address Generation
When a virtual address is presented to the MMU by the CPU
and the translation information is not in the TLB, the MMU
performs a page table lookup in order to generate the physical address.
The Page Table structure is traversed by the MMU using
fields taken from the virtual address. This sequence is diagrammed in Figure 3-3.
Bits 9-23 of the virtual address hold the 15-bit Page Number, which in the course of the translation is replaced with
the 16-bit Page Frame Number of the physical address. The
The INDEX 2 field of the virtual address (7 bits) is used as
the index into the Level-2 Page Table, by adding it (scaled
by 4) to the base address taken from the Level-1 Page Table Entry. The PFN and MS fields of the selected entry provide the entire Page Frame Number of the translated address.
The offset field of the virtual address is then appended to
this frame number to generate the final physical address.
(11 SELECT 1ST PTE
IF DS;D THEN
n;O
ELSE
n;1 FDR USER MODE
n;O FDR SUPV MDDE
24 23
(31 GENERATE PHYSICAL
ADDRESS
TUEE/B692-20
FIGURE 3-3. Virtual to Physical Address Translation
3-59
....• r------------------------------------------------------------------------------------------,
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3.0 Architectural Description
(Continued)
(Section 3.7). The ADDRESS field of the EIA register holds
the virtual address at which the error occurred, and the AS
bit indicates the address space that was in use.
In writing a virtual address to the EIA register, the virtual
address is specified in the low-order 24 bits, and the AS bit
specifies the address space. A TLB entry is purged only if it
matches both the ADDRESS and AS fields.
Another technique for purging TLB entries is to load a PTBn
register. This automatically purges all entries associated
with the addressing space mapped by that register. Turning
off translation (clearing the MSR TU and/or TS bits) does
not purge any entries from the TLB.
3.3 PAGE TABLE BASE REGISTERS (PTBO, PTB1)
The PTBn registers hold the physical addresses of the Level-1 Page Tables.
The format of these registers is shown in Figure 3-4. The
least-significant 10 bits are permanently zero, so that each
register always pOints to a 1 Kbyte boundary in memory.
The PTBn registers may be loaded or stored using the MMU
Slave Processor instructions LMR and SMR (Section 3.11).
3.4 ERRORIINVALIDATE ADDRESS REGISTER (EIA)
The Error/Invalidate Address register is a dual-purpose register.
1) When it is read using the SMR instruction, it presents the
virtual address which last generated an address translation error.
2) When a virtual address is written into it using the LMR
instruction, the translation for that virtual address is
purged, if present, from the TLB. This must be done
whenever a Page Table Entry has been changed in memory, since the TLB might otherwise contain an incorrect
translation value.
3.5 BREAKPOINT REGISTERS (BPRO, BPR1)
The Breakpoint registers BPRO and BPR1 specify the addresses and conditions on which a Breakpoint trap will be
generated. They are each 32 bits in length and have the
format shown in Figure 3-6. All implemented bits of BPRO
and BPR1 are readable and writable.
Bits 0 through 23 and bit 31 (AS) specify the breakpoint
address. This address may be either virtual or physical, as
specified in the VP bit.
Bits 24 and 25 are not implemented. Bit 26 (CE) is not implemented in register BPR1.
The format of the EIA register is shown in Figure 3-5. When
a translation error occurs, the cause of the error is reported
by the MMU in the appropriate fields of the MSR register
(RESERVED)
MS
I 31
ADDRESS BITS lD-23
24
I 23
TL/EE/8692-21
FIGURE 3-4. Page Table Base Registers (PTBO, PTB1)
I 31
24
I 23
oI
TL/EE/8692-22
FIGURE 3-5. EIA Register
I
AS I VP
I
BE I BR IBwl CE
IXIXI
:
ADD~ESS:
oI
TLlEE/8692-23
FIGURE 3-6. Breakpoint Registers (BPRO, BPR1)
3-60
z
3.0 Architectural Description
(I)
(0)
I\;)
(Continued)
Bits 26 through 30 specify the breakpoint conditions. Breakpoint conditions define how the breakpoint address is compared and which conditions permit a break to be generated.
A Breakpoint register can be selectively disabled by setting
all of these bits to zero.
AS
Address Space. This bit depends on the setting of
the VP bit. For virtual addresses, this bit contains the
AS (Address Space) qualifier of the virtual address
(Section 3.2.2). For physical addresses, this bit contains the MS (Memory System) bit of the physical
address.
VP
Virtual/Physical. If VP is 0, the breakpoint address is
compared against each referenced virtual address. If
VP is 1, the breakpoint address is compared against
each physical address that is referenced by the CPU
(i.e. after translation).
BE
Break on Execution. If BE is 1, a break is generated
immediately before the instruction at the breakpoint
address is executed. While this option is enabled, the
breakpoint address must be the address of the first
byte of an instruction. If BE is 0, this condition is
disabled.
Branch
ACBi
BR
BSR
Bcond
CASEi
Note: This option cannot be used in systems based on any CPU with a 32bit wide bus.
BW
CE
.
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......
o
Add, Compare and Branch: unless result is zero
Branch (Unconditional)
Branch to Subroutine
Branch (Conditional): only if condition is met
Case Branch
CXP
CXPD
DIA
Call External Procedure
Call External Procedure with Descriptor
Diagnose
JSR
JUMP
Jump to Subroutine
Jump
RET
RXP
BPT
Return from Subroutine
Return from External Procedure
Breakpoint Trap
FLAG
RETI
Trap on Flag
Return from Interrupt: if MSR loaded properly
by supervisor
Return from Trap: if MSR loaded properly by
supervisor
Supervisor Call
SVC
Also all traps or interrupts not generated by the MMU.
RETT
The BE bit should only be set when the CPU has a 16·bit bus (i.e.
NS32016, NS32COI6). In other systems. use instead the BPT instruction placed in memory, to signal a break.
BR
o
TABLE 3-2_lnstructlons Causing
Non-Sequential Fetches
Break on Read. If BR is 1, a break is generated when
data is read from the breakpoint address. Instruction
fetches do not trigger a Read breakpoint. If BR is 0,
this condition is disabled.
Break on Write. If BW is 1, a break is generated when
data is written to the breakpoint address or when
data is read from the breakpoint address as the first
part of a read-modify-write access. If BW is 0, this
condition is disabled.
Branch to Following Instruction
BICPSRi
Bit Clear in PSR
MOVSUi
MOVUSi
Move Value from Supervisor to User Space
Move Value from User to Supervisor Space
Counter Enable. This bit is implemented only in the
BPRO register. If CE is 1, no break is generated unless the Breakpoint Count register (BCNT, see below) is zero. The BCNT register decrements when
the condition for the breakpoint in register BPRO is
met and the BCNT register is not already zero. If CE
is 0, the BCNT register is disabled, and breaks from
BPRO occur immediately.
WAIT
Wait: fetches next instruction before waiting
BISPSRi
LMR
LPRi
Bit Set in PSR
Load Memory Management Register
Load Processor Register: unless UPSR is the
register specified
3.6 BREAKPOINT COUNT REGISTER (BCNn
The Breakpoint Count register (BCNT) permits the user to
specify the number of breakpoint conditions given by register BPRO that should be ignored before generating a Breakpoint trap. The BCNT register is 32 bits in length, containing
a counter in its low-order 24 bits, as shown in Figure 3-7.
The high-order eight bits are not used.
Note 1: The bits BR, BW and CE should not all be set. The counting performed by the MMU becomes inaccurate, and in Abort Mode (MSR
AI bit set). it can trap a program in such a way as to make it impossible to retry the breakpointed instruction correctly.
Note 2: An execution breakpoint should not be counted (BE and CE bits
both set) if it is placed at an address that is the destination of a
branch, or if it follows a queue-flushing instruction. See Table 3-2.
The counting performed by the MMU will be inaccurate if interrupts
occur during the fetch of that address.
oI
TLlEE/8692-24
FIGURE 3-7. Breakpoint Count Register (BCNn
3-61
.... r-----------------------------------------------------------------------------,
Q
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z
3.0 Architectural Description
(Continued)
AO
Access Level Override. This bit may be set to temporarily cause User Mode accesses to be given Supervisor Mode privilege. See Section 3.10.
Status Fields
The BCNT register affects the generation of Breakpoint
traps only when it is enabled by the CE bit in the BPRO
register. When the BPRO breakpoint condition is encountered, and the BPRO CE bit is 1, the contents of the BCNT
register are checked against zero. If the BCNT contents are
zero, a breakpoint trap is generated. If the contents are not
equal to zero, no breakpoint trap is generated and the
BCNT register is decremented by 1.
The MSR status fields may be read using the MSR instruction, but are not writable. Instead, all status fields (except
the BN bit) may be cleared by loading a "1" into the R bit
using the LMR instruction.
TE Translation Error. This bit is set by the MMU to indicate that an address translation error has occurred.
This bit is cleared by a hardware reset.
TET Translation Error Type. This three-bit field shows the
reason(s) for the last address translation error reported by the MMU. The format of the TET field is shown
below.
If the CE bit in the BPRO register is 0, the BCNT register is
ignored and the BPRO condition breaks the program execution regardless of the BCNT register's contents. The BCNT
register contents are unaffected.
3.7 MEMORY MANAGEMENT STATUS REGISTER (MSR)
The Memory Management Status Register (MSR) provides
overall control and status fields for both address translation
and debugging functions. The format of the MSR register is
shown in Figure 3-8.
The MSR fields relevant to either of the above functions are
described in the following sub-sections.
I IL2 I IL1 I PL I
PL
Protection Level error. The access attempted
by the CPU was not allowed by the protection
level assigned to the page it attempted to access (forbidden by either of the Page Table
Entry PL fields).
IL1
Invalid Level 1. The Level-1 Page Table Entry
was invalid (V bit = 0).
IL2
Invalid Level 2. The Level-2 Page Table Entry
was invalid (V bit = 0).
3.7.1 MSR Fields for Address Translation.
Control Functions
The address translation control bits in the MSR, ad exception of the R bit, are both readable (using the SMR instruc·
tion) and writable (using LMR).
R
TU
Reset. When read, this bit's contents are undefined.
Whenever a "1" is written into it, MSR status fields
TE, B, TET, ED, BD, EST and BST are cleared to all
zeroes. (The BN bit is not affected.)
Translate User-Mode Addresses. While this bit is "1 ",
the MMU translates all addresses presented while the
CPU is in User Mode. While it is "0", the MMU echoes all User-Mode virtual addresses without performing translation or access level checking. This bit is
cleared by a hardware Reset.
ED
ED = 1 => Read cycle.
Note: Altering the TU bit has no effect on the contents of the TLB.
TS
EST Error Status. This 3-bit field is set on an address
translation error to the low-order three bits of the CPU
status bus. Combinations appearing in this field are
summarized below.
000 Sequential instruction fetch
Translate Supervisor-Mode Addresses. While this bit
is "1 ", the MMU translates all addresses presented
while the CPU is in Supervisor Mode. While it is "0",
the MMU echoes all Supervisor-Mode virtual addresses without translation or access level checking. This
bit is cleared by a hardware Reset.
001
010
011
Note: Altering the TS bit has no effect on the contents of the TLB.
DS
These error indications are not mutually exclusive. A
protection level error and an invalid translation error
can be reported simultaneously by the MMU.
Error Direction. This bit indicates the direction of the
transfer that the CPU was attempting on the most
recent address translation error.
ED=O=>Write cycle.
Dual·Space Translation. While this bit is "1", Supervi·
sor Mode addresses and User Mode addresses are
translated independently of each other, using separate mappings. While it is "0", both Supervisor Mode
addresses and User Mode addresses are translated
using the same mapping. See Section 3.2.2.
100
Non-sequential instruction fetch
Operand transfer (read or write)
The Read action of a read-modify-write transfer (operands of access class "rmw" only: See
the Series 32000 Instruction Set Reference
Manual for further details).
A read transfer which is part of an effective
address calculation (Memory Relative or External mode)
01
TL/EE/8692-25
Note: In some Series 32000 documentation. the bits TE, Rand B are jOintly referenced with the keyword "ERC".
FIGURE 3·8. Memory Management Status Register (MSR)
3-62
r--------------------------------------------------------------------------,
3.0 Architectural Description (Continued)
N
100
3.7.2 MSR Fields for Debugging
Control Functions
Breakpoint control bits in the MSR are both readable (using
the SMR instruction) and writable (using LMR).
BEN Breakpoint Enable. Setting this bit enables both
Breakpoint Registers (BPRO, BPR1) to monitor CPU
activity. This bit is cleared by a hardware reset or
whenever a Breakpoint trap or an address translation
error occurs. If only one breakpoint register must be
enabled, the other register should be disabled by
clearing all of its control bits (bits 26-31) to zeroes.
A read transfer which is part of an effective
address calculation (Memory Relative or External mode)
Note: The BST field encodings 000 and 001 differ from those of the EST
field (Section 3.7.1) because the MMU inserts a DIA Instruction into
the instruction stream in implementing Execution breakpoints (Section
2.7.1). One side effect of this is that a breakpoint trap is never triggered directly by a sequential instruction fetch cycle.
AI
B
Figure 3-9 models the TLB. Information is placed into the
TLB whenever the MMU performs a lookup from the Page
Tables in memory. If the retrieved mapping is valid (V = 1 in
both levels of the Page Tables), and the access attempted
is permitted by the protection level, an entry of the TLB is
loaded from the information retrieved from memory. The recipient entry is selected by an on-chip circuit that implements a Least-Recently-Used (LRU) algorithm. The MMU
places the virtual page number (15 bits) and the Address
Space qualifier bit into the Tag field of the TLB entry.
User-Only Breakpointing. When this bit is set in con·
junction with the BEN bit, it limits the Breakpoint
Registers to monitor addresses only while the CPU is
in User Mode.
Abortllnterrupt. This bit selects the action taken by
the MMU on a breakpoint. While AI is "0" the MMU
generates a pulse on the INT pin (this can be used to
generate a non-maskable interrupt). While AI is "1"
the MMU generates an Abort pulse instead.
Status Fields
The MSR status fields may be read using the SMR instruction, but are not writable. Instead, all status fields (except
the BN bit) may be cleared by loading a "1" into the R bit
using the LMR instruction. See Section 3.7.1.
BD
BST
Break. This bit is set to indicate that a breakpoint trap
has been generated by the MMU.
Breakpoint Number. The BN bit contains the register
number for the most recent breakpoint trap generated by the MMU. If BN is 1, the breakpoint was triggered by the BPR1 register. If BN is 0, the breakpoint
was triggered by the BPRO register. If both registers
trigger a breakpoint simultaneously, the BN bit is set
to 1.
The Value portion of the entry is loaded from the Page Tables as follows:
The Translation field (16 bits) is loaded from the MS bit
and PFN field of the Level-2 Page Table Entry.
The M bit is loaded from the Level-2 Page Table Entry.
The PL field (2 bits) is loaded to reflect the net protection
level imposed by the PL fields of the Level-1 and Level-2
Page Table Entries.
(Not shown in the figure are additional bits associated with
each TLB entry which flag it as full or empty, and which
select it as the recipient when a Page Table lookup is performed.)
Break Direction. This bit indicates the direction of the
transfer that the CPU was attempting on the access
that triggered the most recent breakpoint trap. It is
loaded from the complement of the DDIN pin.
BD=O=>Write cycle.
BD=1 =>Read cycle.
When a virtual address is presented to the MMU for translation. the high-order 15 bits (page number) and the Address
Space qualifier are compared associatively to the corresponding fields in all entries of the TLB. When the Tag portion of a TLB entry completely matches the input values, the
Value portion is produced as output. If the protection level is
not violated, and the M bit does not need to be changed,
then the physical address Page Frame number is output in
the next clock cycle. If the protection level is Violated, the
MMU instead activates the Abort output. If no TLB entry
matches, or if the matching entry's M bit needs to be
changed, the MMU performs a page-table lookup from
memory.
Note that for a translation to be loaded into the TLB it is
necessary that the Level-1 and Level-2 Page Table Entries
be valid (V bit = 1). Also, it is guaranteed that in
Breakpoint Status. This 3-bit field is loaded on a
Breakpoint trap from the low-order three bits of the
CPU status bus. Combinations appearing in this field
are summarized below.
000 No break has occurred since the field was last
reset.
001 Instruction fetch
010
011
....o~
3.8 TRANSLATION LOOKASIDE BUFFER (TLB)
The efficiency of the MMU is greatly increased by the TLB,
which bypasses the much longer Page Table lookup in over
97% of the accesses made by the CPU.
Entries in the TLB are allocated and replaced by the MMU
itself; the operating system is not involved. The TLB entries
cannot be read or written by software; however, they can be
purged from it under program control.
BN
oQC)
The Translation Lookaside Buffer is an on-chip fully associative memory. It provides direct virtual to phYSical mapping
for the 32 most recently used pages, requiring only one
clock period to perform the address translation.
Note: When the BEN bit is set (using the LMR instruction), the MMU en·
abies breakpoints only after two non·sequential instruction fetch cycles have been completed by the CPU. See Section 3.9.
UB
Z
en
Co)
Operand transfer (read or write)
The Read action of a read-modify-write transfer (operands of access class "rmw" only:
See the Series 32000 Instruction Set Reference Manual for further details).
3-63
•
-~ r---------------------------------------------------------------------------------,
C)
~
C")
U)
z
3.0 Architectural Description (Continued)
the process of loading a TLB entry (during a Page Table
lookup) the Level-1 and Level-2 R bits will be set in memory
if they were not already sel. For these reasons, there is no
need to replicate either the V bit or the R bit in the TLB
entries.
3.9 ENTRYIRE-ENTRY INTO PROGRAMS
UNDER DEBUGGING
Whenever the MSR is written, breakpoints are disabled. After two non-sequential instruction fetch cycles have completed, they are again enabled if the new BEN bit value is
'1'. The recommended sequence for entering a program under test is:
Whenever a Page Table Entry in memory is altered by software, it is necessary to purge any matching entry from the
TLB, otherwise the MMU would be translating the corresponding addresses according to obsolete information. TLB
entries may be selectively purged by writing a virtual address to the EIA register using the LMR instruction. The TLB
entry (if any) that matches that virtual address is then
purged, and its space is made available for another translation. Purging is also performed by the MMU whenever an
address space is remapped by altering the contents of the
PTBO or PTB1 register. When this is done, the MMU purges
all the TLB entries corresponding to the address space
mapped by that register. Turning translation on or off (via
the MSR TU and TS bits) does not affect the contents of the
TLB.
LMR
RETT
executed with interrupts disabled (CPU PSR I bit off).
This feature allows a debugger or monitor program to return
control to a program being debugged without the risk of a
false breakpoint trap being triggered during the return.
The LMR instruction performs the first non-sequential fetch
cycle, in effect branching to the next sequential instruction.
The RETT (or RETI) instruction performs the second nonsequential fetch as its last memory reference, branching to
the first (next) instruction of the program under debug. The
non-sequential fetch caused by the RETT instruction, which
might not have occurred otherwise, is not monitored.
Note: If the value in the PTBO register must be changed, it is strongly recommended that the translation be disabled before loading the new value,
otherwise the purge performed may be incomplete. This is due to
instruction prefetches and/or memory read cycles occurring during
the lMR instruction which may restore TLB entries from the old map.
3_10 ADDRESS TRANSLATION ALGORITHM
The MMU either translates the 24-bit virtual address to a
25-bit physical address or reports a translation error. This
process is described algorithmically in the following pages.
See also Figure 3-3.
TAG
VIRTUAL
ADDRESS
(U/S. ZZZ)
COMPARISON
MSR, New_Value
n
; or RETI
VALUE
AS
PAGE NUMBER
(15 BITS)
PL
M
TRANSLATION
(16 BITS)
a
xxx
11
a
mmm
nnn
1
yyy
11
0
a
zzz
11
1
PPP
1
www
00
1
qqq
TRANSLATED
ADDRESS
(PPP)
TUEE/8692-26
FIGURE 3-9_ TLB Model
3-64
MMU Page Table Lookup and Access Validation Algorithm
Legend:
x = y
x == y
x AND y
x OR Y
'"m
01
x is assigned the value y
Comparison expression, true if x is equal to y
Boolean AND expression, true only if assertions x and yare both true
Boolean inclusive OR expression, true if either of assertions x and y is true
Delimiter marking end of statement
{ ... I
Delimiters enclosing a statement block
item(i)
Bit number i of structure "item"
item(i:j)
The field from bit number i through bit number
of structure "item"
item.x
The bit or field named "x" in structure "item"
DONE
Successful end of translation; MMU provides translated address
ABORT
Unsuccessful end of translation; MMU aborts CPU access
This algorithm represents for all cases a valid definition of address translation.
Bus activity implied here occurs only if the TLB does not contain the mapping,
or if the reference requires that the MMU alter the M bit of the Page Table Entry.
Otherwise, the MMU provides the translated address in one clock period.
Input (from CPU) :
U (1 if U/S is high)
W (1 if DDIN input is high)
VA Virtual address conSisting of:
INDEX_l (from pins A23-A16)
INDEX_2 (from pins AD15-AD9)
OFFSET (from pins ADS-ADO)
ACCESS_LEVEL
The access level of a reference is a 2-bit value synthesized by the MMU from CPU status:
bit 1
U AND NOT MSR.AO (U from U/S input pin)
bi t 0 = 1 for Write cycle, or Read cycle of an "rmw" class operand access
o otherwise.
Output:
PA PhYSical Address on pins A24-A16, AD15-ADO;
or
Abort pulse on RSTIABT pin.
Uses:
MSR
Status Register:
fields TU, TS and DS
O~-l80l£SN
II
NS32082-10
MMU Page Table Lookup and Access Validation Algorithm
Page Table Base Register 0
Page Table Base Register 1
Level-l Page Table Entry:
fields PFN, PL, V, Rand MS
PTEP_l
Pointer, holding address of PTE_l
PTE_2
Level-2 Page Table Entry:
fields PFN, PL, V, M, Rand MS
PTEP_2
Pointer, holding address of PTE_2
IF «MSR.TU == 0) AND (U == 1)
OR «MSR.TS
THEN ( PA(O:23) = VA(O:23) ; PA(24) = 0 ; DONE
(Continued)
PTBO
PTBl
PTE_l
0) AND (U ==0) )
I
IF (MSR.DS = = 1) AND (U = = 1)
THEN ( PTEP_l(24) = PTBloMS ; PTEP_l(23:10) = PTB1(23:1O)
PTEP_l(9:2) = VA.INDEX_l ; PTEP_l(l:O) =0 I
ELSE
PTEP_l(24) = PTBO.MS ; PTEP_l(23:10) = PTBO(23:1O)
PTEL1(9:2) = VA.INDEX_l; PTEP_l(l:O) = 0
'"a,
If translation not enabled then echo
virtual address as physical address.
If Dual Space mode and
then form Level-l
from PTBl
else form Level-l
from PTBO
CPU in User Mode
PTE address
register,
PTE address
register.
- - - LEVEL 1 PAGE TABLE LOOKUP - - -
0>
IF ( ACCESS_LEVEL> PTE_l.PL ) OR (PTE_l.V
THEN ABORT ;
IF PTE_loR = = 0 THEN PTE_loR
PTE_l(4) = (undefined value) ;
If protection violation or invalid Level-2 page
table then abort the access.
0)
Otherwise, set Reference bit if not already set,
(the M bit position may be garbaged)
1
PTEL2(24) = PTE_loMS ; PTEP_2(23:9) = PTE_loPFN
PTEP_2(8:2) = VA.INDEX_2 ; PTEP_2(l:O) = 0 ;
and form Level-2 PTE address.
LEVEL 2 PAGE TABLE LOOKUP IF ( ACCESS_LEVEL > PTE_2. PL ) OR ( PTE_2. V = = 0 )
THEN ABORT ;
IF PTE_2.R = = 0 THEN PTE_2.R = = 1
IF ( W = = 1) AND ( PTE_2.M = = 0 ) THEN PTE_2.M
PA(24)
DONE;
PTE_2.MS; PA(23:9)
PTE_2.PFN
PA(8:0)
If protection violation or invalid page
then abort the access.
1
VA. OFFSET
Otherwise, set Referenced bit if not already set,
if Write cycle set Modified bit if not
already set,
and generate physical address.
z
(f)
3.0 Architectural Description (Continued)
4.0 Device Specifications
3.11 INSTRUCTION SET
4.1 NS32082 PIN DESCRIPTIONS
Four instructions of the Series 32000 instruction set are executed cooperatively by the CPU and MMU. These are:
The following is a brief description of all NS32082 pins. The
descriptions reference portions of the Functional Description, Section 2.0.
LMR
SMR
Load Memory Management Register
Store Memory Management Register
RDVAL
Validate Address for Reading
c.:I
N
o0)
A22
WRVAL Validate Address for Writing
The format of the MMU slave instructions is shown in Figure
3-10. Table 3-3 shows the encodings of the "short" field for
selecting the various MMU internal registers.
TABLE 3-3. "Short" Field Encodings
"Short" Field
Register
0000
0001
1010
1011
1100
1101
1111
BPRO
BPRl
MSR
BCNT
PTBO
PTBl
EIA
A2t
A23
A20
A24/HBF
A19
iN'i
AIS
PAY
A17
STO
A16
STI
AD15
5T2
AD14
ST3
A013
m
A012
DDIN
ADll
ADS
U/S
AD10
AD9
Note: All other codes are illegal. They will cause unpredictable registers to
be selected if used in an instruction.
For reasons of system security, all MMU instructions are
privileged, and the CPU does not issue them to the MMU in
User Mode. Any such attempt made by a User-Mode program generates the Illegal Operation trap, Trap (ILL). In addition, the CPU will not issue MMU instructions unless its
CFG register's M bit has been set to validate the MMU instruction set. If this has not been done, MMU instructions
are not recognized by the CPU, and an Undefined Instruction trap, Trap (UND), results.
AT/SPC
ADS
iffi;AST
AD7
F[f
AD6
HLDAO
AD5
HLDAI
AD4
HOLD
AD3
RSTI
AD2
RDY
ADI
PHI2
ADO
PHil
GNDL
GNDS
TL/EE/8692-28
Top View
Order Number NS16082D
See NS Package Number D48A
The LMR and SMR instructions load and store MMU registers as 32-bit quantities to and from any general operand
(including CPU General-Purpose Registers).
FIGURE 4-1. Dual·ln·Line Package Connection Diagram
4.1.1 Supplies
The RDVAL and WRVAL instructions probe a memory address and determine whether its current protection level
would allow reading or writing, respectively, if the CPU were
in User Mode. Instead of triggering an Abort trap, these instructions have the effect of setting the CPU PSR F bit if the
type of access being tested for would be illegal. The PSR F
bit can then be tested as a condition code.
Power (Vee): +5V positive supply. Section 2.1.
Logic Ground (GNDL): Ground reference for on-chip logic.
Section 2.1.
Buffer Ground (GNDB): Ground reference for on-chip drivers connected to output pins. Section 2.1.
4.1.2 Input Signals
Note: The Series 32000 Duat-Space Move instructions (MOVSUi and
MOVUSi), although they involve memory management action, are not
Clocks (PHil, PHI2): Two-phase clocking signals. Section
2.2.
Slave Processor instructions. The CPU implements them by switching
the state of its U/S pin at appropriate times to select the desired
mapping and protection from the MMU.
Ready (RDY): Active high. Used by slow memories to extend MMU originated memory cycles. Section 2.4.4.
For full architectural details of these instructions, see the
Series 32000 Instruction Set Reference Manual.
Hold Request (HOLD): Active low. Causes a release of the
bus for DMA or multiprocessing purposes. Section 2.6.
Hold Acknowledge In (HLDAI): Active low. Applied by the
CPU in response to HOLD input, indicating that the CPU has
released the bus for DMA or multiprocessing purposes.
Section 2.6.
OPERATION WORD
sI7
ID CODE
01
TLlEE/8692-27
FIGURE 3·10. MMU Slave Instruction Format
3-67
...
~
o
o
,...
I
N
CO
o
N
('I)
en
z
4.0 Device Specifications (Continued)
Reset Input (RSTI): Active low. System reset. Section 2.3.
Status Lines (STO-ST3): Status code input from the CPU.
Active from T4 of previous bus cycle through T3 of current
bus cycle. Section 2.4.
Hold Acknowledge Output (HLDAO): Active low. When
active, indicates that the bus has been released.
4.1.4 Input-Output Signals
Data Direction In (ODIN): Active low. Status signal indicating direction of data transfer during a bus cycle. Driven by
the MMU during a page-table lookup.
Program Flow Status (PFS): Active low. Pulse issued by
the CPU at the beginning of each instruction.
User/Supervisor Mode (U/S): This signal is provided by
the CPU. It is used by the MMU for protection and for selecting the address space (in dual address space mode only).
Section 2.4.
Address Translation/Slave Processor Control (AT/
SPC): Active low. Used by the CPU as the data strobe output for Slave Processor transfers; used by the MMU to acknowledge completion of an MMU instruction. Section 2.3
and 2.5. Held low during reset to select the address translation mode on the CPU.
M.S. Bit of Physical Address/High Byte Float (A24/
HBF): Most significant bit of physical address. Sampled on
the rising edge of the reset input to select 16 or 32-bit bus
mode. This pin outputs a low level if address translation is
not enabled. It is floated during T2-T4 if 32-bit bus mode is
selected.
Address Bits 16-23 (A16-A23): High order bits of the address bus. These signals are floated by the MMU during
T2-T4 if 32-bit bus mode is selected.
Address/Data 0-15 (ADO-AD1S): Multiplexed Addressl
Data Information. Bit 0 is the least significant bit.
Address Strobe Input (ADS): Active low. Pulse indicating
that a virtual address is present on the bus.
4_1.3 Output Signals
Reset Output! Abort (RST / ABT): Active Low. Held active
longer than one clock cycle to reset the CPU. Pulsed low
during T2 or TMMU to abort the current CPU instruction.
Interrupt Output (I NT): Active low. Pulse used by the debug functions to inform the CPU that a break condition has
occurred.
Float Output (FLT): Active low. Floats the CPU from the
bus when the MMU accesses page table entries or performs a physical breakpoint check. Section 2.4.3.
Physical Address Valid (PAV): Active low. Pulse generated during TMMU indicating that a physical address is present on the bus.
Note: Absolute maximum ratings indicate limits beyond
4.2 ABSOLUTE MAXIMUM RATINGS
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
O'Cto +70'C
Temperature Under Bias
Storage Temperature
All Input or Output Voltages with
Respect to GND
-65'Cto +150'C
-0.5Vto +7V
Power Dissipation
1.5W
4.3 ELECTRICAL CHARACTERISTICS TA = 0 to + 70'C, Vee = 5V ± 5%, GND = OV
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
High Level Input Voltage
2.0
Vee + 0.5
V
Vil
Low Level Input Voltage
-0.5
0.8
V
VeH
High Level Clock Voltage
PHI1, PHI2 pins only
Vee - 0.35
Vee + 0.5
V
Vel
Low Level Clock Voltage
PHil, PHI2 pins only
-0.5
0.3
V
VelT
Low Level Clock Voltage,
Transient (ringing tolerance)
PHil, PHI2 pins only
-0.5
0.6
V
VOH
High Level Output Voltage
IOH = - 400 fLA
VOL
Low Level Output Voltage
IOl = 2 mA
IllS
AT/SPC Input Current (low)
VIN = O.4V, AT ISPC in input mode
II
Input Load Current
o :0; VIN :0; Vee, All inputs except
2.4
PHil, PHI2, AT/SPC
Il
Ice
Leakage Current
(Output and 1/0 Pins
in TRI-STATE/lnput Mode)
0.4
Active Supply Current
lOUT = O,TA = 25'C
:0;
VIN
:0;
V
0.45
V
0.05
1.0
mA
-20
20
fLA
-20
30
fLA
300
mA
Ve
3-68
200
ztJ)
4.0 Device Specifications (Continued)
c.:I
N
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHI1
N
ABBREVIATIONS:
o
L.E. -
leading edge
R.E. -
rising edge
T.E. -
trailing edge
F.E. -
falling edge
PHln
[--
SIGl
- - - - - - - - . : - - - - - - , - 2.4V
--.-SI-G-,I------~'---.:~:
~
[ _ _ _'_ _
.s_IG_2_h....JI.
___
_____
co
•
......
[ ____>E
[
SIGl
O.BV
SIG2
o
and PHI2, and O.BV or 2.0V on all other signals as illustrated
in Figures 4-2 and 4-3, unless specifically stated otherwise.
~:
SIG2
[
'\
'SIG 11
'---I--O.45V
/r---+-- 2.4V
2.0V +---~ 'SIG2h
-----~---- - - - - -
O.45V
TL/EE/B692-30
TL/EE/B692-29
FIGURE 4-3. Timing Specification Standard
(Signal Valid before Clock Edge)
FIGURE 4-2. Timing Specification Standard
(Signal Valid after Clock Edge)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32082-10.
Maximum times assume capacitive loading of 100 pF.
Name
Figure
Description
Reference/Conditions
NS32082-10
Min
Units
Max
tALv
4-4
Address Bits 0-15 Valid
tALh
4-4
Address Bits 0-15 Hold
After R.E., PHI1 T2
tAHv
4-4,4-6
Address Bits 16-24 Valid
After R.E., PHI1 TMMU or T1
tAHh
4-4
Address Bits 16-24 Hold
After R.E., PHI1 T2
tALPAVs
4-5
Address Bits 0-15 Set Up
tAHPAVs
4-5
Address Bits 16-24 Set Up
tALPAVh
4-5
Address Bits 0-15 Hold
After PAY T.E.
tAHPAVh
4-5
Address Bits 16-24 Hold
After PAY T.E.
tALI
4-10
ADO-AD15 Floating
After R.E., PHI1 T2
25
. ns
tAHI
4-7,4-10
A16-A24 Floating
After R.E., PHI1 T2 or T1
25
ns
tALz
4-15,4-16
ADO-AD15 Floating
(Caused by HOLD)
After R.E., PHI1 Ti
25
ns
tAHZ
4-15,4-16
A16-A24 Floating
(Caused by HOLD)
After R.E., PHI1 Ti
25
ns
tALr
4-15,4-16
ADO-AD15 Return from Floating
(Caused by HOLD)
After R.E., PHI1 T1
50
ns
After R.E., PHI1 TMMU or T1
3-69
40
5
ns
ns
40
ns
5
ns
Before PAY T.E.
25
ns
Before PAY T.E.
25
ns
15
ns
15
ns
&I
4.0 Device Specifications
(Continued)
4.4.2.1 Output Signals: Internal Propagation Delays, NS32082·10. (Continued)
Name
Figure
Description
Reference/Conditions
NS32082·10
Min
tAHr
4-15,4-16
tDv
A16-A24 Return from Floating
(Caused by HOLD)
After R.E., PHil Tl
4-6
Data Valid
(Memory Write)
After R.E., PHil T2
tOh
4-6
Data Hold
(Memory Write)
After R.E., PHil next Tl or Ti
tot
4-11
Data Bits Floating
(Slave Processor Read)
After R.E., PHil Tl or Ti
tov
4-11
Data Valid
(Slave Processor Read)
After R.E., PHil Tl
tOh
4-11
Data Hold
(Slave Processor Read)
After R.E., PHil next Tl or Ti
AfterR.E., PHil T1 orTMMU
Units
Max
50
ns
50
ns
ns
0
10
ns
50
ns
0
ns
tOOINv
4-5,4-7
ODIN Signal Valid
tOOINh
4-5
50
DDIN Signal Hold
After R.E., PHil T1 or Ti
tOOIN!
4-7
DDIN Signal Floating
After R.E., PHil T2
tODINz
4-16
DDIN Signal Floating
(Caused by HOLD)
After R.E., PHil Ti
tODINr
4-16
ODIN Return from Floating
(Caused by HOLD)
After R.E., PHil Tl or Ti
tODlNA!
4-9
ODIN Floating after
Abort (FLT = 0)
After R.E., PHI2 T2
tPAVa
4-4
PAY Signal Active
tPAVia
4-4
PAY Signal Inactive
tpAVw
4-4
PAY Pulse Width
At O.SV (Both Edges)
tpAVdz
4-14,4-15
PAY Floating Delay
After HLDAI F.E.
25
ns
tPAVdr
4-14,4-15
PAY Return from Floating
After HLDAI R.E.
25
ns
tpAVz
4-16
PAY Floating
(Caused by HOLD)
After R.E., PHI2 T4
30
ns
tPAVr
4-16
PAY Return from Floating
(Caused by HOLD)
After R.E., PHI2 Ti
30
ns
tFLTa
4-5,4-10
FLT Signal Active
After R.E., PHil T MMU
55
ns
tFLTia
4-7,4-10
FLT Signal Inactive
After R.E., PHil T MMU, T! or T2
35
ns
tABTa
4-S, 4-10
Abort Signal Active
After R.E., PHil T MMU or Tl
55
ns
tABTia
4-S, 4-10
Abort Signal Inactive
After R.E., PHil T2
55
ns
tABTw
4-S,4-10
Abort Pulse Width
At O.SV (Both Edges)
tlNTa
4-4,4-10
INT Signal Active
After R.E., PHil T MMU or Tf
55
ns
tlNTia
4-4,4-10
INT Signal Inactive
After R.E., PHil T2
55
ns
tlNTw
4-10
INT Pulse Width
At O.SV (Both Edges)
tSPCa
4-13
SPC Signal Active
After R.E., PHil Tl
40
ns
tSPCia
4-13
SPC Signal Inactive
After R.E., PHil T4
40
ns
0
ns
ns
25
ns
50
ns
50
ns
25
ns
After R.E., PHil TMMU orTl
35
ns
After R.E., PHI2 T MMU or Tl
40
ns
3·70
30
ns
70
ns
70
ns
z
fao
4.0 Device Specifications (Continued)
....o.
co
N
4.4.2.1 Output Signals: Internal Propagation Delays, NS32082-10. (Continued)
Name
Figure
Description
NS32082-10
Reference/Conditions
Min
Units
Max
tSPCf
4-13
SPC Signal Floating
After F.E., PHI1 T4
tspCw
4-13
SPC Pulse Width
At 0.8V (Both Edges)
25
tHLOOda
4-14
HLDAO Assertion Delay
After HLDAI F.E.
50
ns
tHLOOdia
4-14,4-15
HLDAO Deassertion Delay
After HLDAI R.E.
50
ns
tHLOOa
4-15,4-16
HLDAO Signal Active
After R.E., PHI1 Ti
30
ns
tHLDOia
4-16
HLDAO Signal Inactive
After R.E, PHI1 Ti
30
ns
tATa
4-18
AT ISPC Signal Active
After R.E., PHI1
35
ns
tATia
4-18
AT ISPC Signal Inactive
After R.E., PHI1
35
ns
tAT!
4-18
AT ISPC Signal Floating
After F.E., PHI1
25
ns
tRSTOa
4-18
RSTI ABT Asserted (Low)
After R.E. PHI1
30
ns
tRSTOia
4-18
RST I ABT Deasserted (High)
After R.E. PHI1 Ti
30
ns
70
ns
ns
4.4.2.2 Input Signal Requirements: NS32082-10
Name
Figure
Description
Reference/Conditions
NS32082-10
Min
tOls
4-5
Data In Set Up
(Memory Read)
Before F.E., PHI2 T3
tOlh
4-5
Data In Hold
(Memory Read)
After R.E., PHI1 T4
tOls
4-12
Data In Set Up
(Slave Processor Write)
Before F.E., PHI2 T1
tOlh
4-12
Data In Hold
(Slave Processor Write)
After R.E., PHI1 T4
tROYs
4-5
RDY Signal Set Up
tROYh
4-5
RDY Signal Hold
tUSs
4-4,4-11
U/S Signal Set Up
tUSh
4-4,4-11
U/S Signal Hold
Units
Max
15
ns
3
ns
20
ns
3
ns
Before F.E., PHI2 T2 or T3
15
ns
After F.E., PHI1 T3
5
ns
Before F.E., PHI2 T4 or Ti
35
ns
After R.E., PHI1 Next T4
0
ns
3·71
4.0 Device Specifications (Continued)
4.4.2.2 Input Signal Requirements: NS32082-10 (Continued)
Name
Figure
Description
Reference/Conditions
NS32082-10
Min
Units
Max
tSTs
4-4,4-11
Status Signals Set Up
Before F.E., PHI2 T4 or Ti
35
ns
tSTh
4-4,4-11
Status Signals Hold
After R.E., PHI1 Next T4
0
ns
ns
tspcs
4·11
SPC Input Set Up
Before F.E., PHI2 T1
45
tSPCh
4·11
SPC Input Hold
After R.E., PHI1 T4
0
ns
tHLDs
4·16
HOLD Signal Set Up
Before F.E., PHI2 T4 or Ti
25
ns
tHLDh
4·16
HOLD Signal Hold
After F.E., PHI2 T 4 or Ti
0
ns
tHLDls
4-15
HLDAI Signal Set Up
Before F.E., PHI2 Ti
20
ns
tHLDlh
4-15
HLDAI Signal Hold
After F.E., PHI2 Ti
0
ns
tHBFs
4-18
A24/HBF Signal Set Up
Before F.E., PHI2
10
ns
tHBFh
4-18
A24/HBF Signal Hold
After F.E., PHI2
0
ns
tRSTls
4-18
Reset Input Set Up
Before F.E., PHI1
20
ns
tPWR
4-19
Power Stable to RSTI R.E.
After Vee Reaches 4.5V
50
",s
RSTI Pulse Width
At 0.8V (Both Edges)
64
tep
tRSTlw
4.4.2.3 Clocking Requirements: NS32082-10
Name
Figure
Reference/
Conditions
Description
NS32082-10
Max
100
250
ns
-2
5
ns
-4
4
ns
-5
5
ns
tcp
4-17
Clock Period
R.E., PHI1, PHI2 to Next
R.E., PHI1, PHI2
tCLw
4-17
PHI1, PHI2
Pulse Width
At 2.0V on PHI1 ,
PHI2 (Both Edges)
0.5tep
-10 ns
tCLh
4-17
PHI1, PHI2 High Time
At VCC - 0.9Von
PHI1, PHI2 (Both Edges)
0.5tep
- 15 ns
tell
4-17
PHI1, PHI2 Low Time
AtO.BVon
PHI1, PHI2
tnOVL (1,2)
4-17
Non-overlap Time
0.8Von F.E. PHI1, PHI2 to
O.BVon R.E., PHI2, PHI1
Non-overlap Asymmetry
At O.BVon PHI1, PHI2
tnOVLas
0.5tep
- 5ns
(tnOVb(1) - tnOVY2»)
teLwas
PHI1, PHI2 Asymmetry
teLw(1) - tCLw(2»)
At 2.0V on
PHI1, PHI2
3-72
Units
Min
z
en
w
4.0 Device Specifications (Continued)
I\)
o
4.4.3 Timing Diagrams
CO
I\)
T4 OR TI
PHI1 [
T1
TMMU
T3
TZ
T4
....o
I
I T1 OR TI
~I"L- '-!l-JI"L-I"L-IL
l---1L ~ ---1L ---1L ---1L ~ U
PHIZ[
IAHv
IALv
X
ADO - 1S[
_IAHh
)
PH. ADDR.
I---
V. ADDR.
I--
)
~------------------I
(FLOATED BY MMU)
PH. ADDR.
~~--L-------l----- __ -----
':';Vla
PAVe
IPAVa
~~A~W
________
\.
DDINL
IUS,
-------- ------- ---_.
(HIGH)
1_
'-~
u/s[.--
._~'I-
~---X
STO-3[
iNT[
-----
(FLOATED BY MMU)
ADS[
m[
-
V. ADDR.
A1S-Z4[
lUSh
-
15Th
-
~IINTIa
--IIINTa
'1.----
.)
TL/EE/8692-31
FIGURE 4-4. CPU Read (Write) Cycle Timing (32-Blt Mode); Translation in TLB
•
TL/EE/8692-32
FIGURE 4-5. MMU Read Cycle Timing (32-Blt Mode); After a TLB Miss
Note: After FLT is asserted, ODIN may be driven temporarily by both CPU and MMU. This, however, does not cause any conflict, since both CPU and MMU force
ODIN to the same logic level.
3·73
C).r------------------------------------------------------------------------------------------,
.,...
•
C'I
4.0 Device Specifications (Continued)
co
C)
C'I
Tf
C')
en
T1 OR TI
z
A16-24[~--------~J,~--~~------~~~----~------_+~,~----+_---ADD-15[~-----+-, ....--_t_J,--_+----,....---+'I---I__--
(HIGH)
DDIN[~___~-J
FU[~---~---~----~(~LO~W~)--+_---+_---~--TLlEE/8692-33
FIGURE 4-6. MMU Write Cycle Timing; after a TLB Miss
TMMU
T2
T3
T4
T1
TMMU
T2
T3
T4
T1
A16-24[~----+-'·'--__1---__iF=;;...--+_---+_'l
ADO-15 [-+----I--'-~-r-'
-------------(FLOATED BY
MMU)
(HIGH)
-------------(FLOATED BY
MMU)
m[-+____I--'
TL/EE/B692-34
FIGURE 4-7. FLT Deassertion TImIng
Note: After FLT is deasserted, ODIN may be driven temporarily by both CPU and MMU. This, however, does not cause any conflict Since CPU and MMU force
lIDfiij to lhe same logic level.
3·74
r--------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
T4 OR T1
Z
~
N
o
TI
TMMU
T2
CD
T1
~
....
o
PHil [
PHI2 [
AiiS[
m[
(HIGH)
m[
RST/ AST [
TL/EE/8692-35
FIGURE 4·8. Abort Timing (FLT = 1)
CPU STATES
MMU STATES
I
Tf
T4
Tf
TI
T3
T3
T2
T2
T4
T4
PHil [
PHI2 [
AOS [
PAY [
m[
RST/ AST [
ODIN [
TL/EE/8892-36
FIGURE 4-9. Abort Timing (FLT = 0)
T1
TMWU
T2
T3
T4
•
PHil [
PHI2 [
A16-24 [
--(rLOATID Bv"WMU)---- --{
ADO-15 [
--(~MiolMM~----
--{
ADS [
m[
ODIN [
m[
RST/ABT [
--~;;;.±j
TL/EE/8692-37
FIGURE 4-10. CPU Operand Access Cycle with Breakpoint on Physical Address Enabled
Note: If a breakpoint condition is met and abort on breakpoint is enabled, the bus cycle is aborted. In this case FLT is stretched by one clock cycle.
3·75
.... r-------------------------------------------------------------------------------------,
C)
~
en
4.0 Device Specifications (Continued)
C')
z
T4 OR 11
TI
T4
11 OR 11
PHl1 [
PHI2 [
'-1-__""
ADO-IS [.SPC [
U/S[ __
~-~--~-----~-4----~---. .
[--1~-l_----1---------I-~r'----_+-----...
ODIN[~~-----__1---~--__I-----__I--~-----
STO-3
TLlEE/8692-38
FIGURE 4-11. Slave Access Timing; CPU Reading from MMU
T4 OR 11
11
T4
TI OR 11
PHil [
PHI2 [
'+__""
~O-15[__1~-----__1-~r}_----~---~,----__I---------
SPC [
STO- 3 [ __
~....J,'----__1~------__1---'---__I-------
DDIN[ __~_ _ _ _--1~
__
TLlEE/8692-39
FIGURE 4-12. Slave Access Timing; CPU Writing to MMU
T4
11
T4
11
PHil [
PHI2 [
'-1-__""
TLlEE/8692-40
FIGURE 4-13. SPC Pulse from the MMU
z
(J)
W
4.0 Device Specifications (Continued)
N
o
co
TI
~
....
o
(HIGH)
A16-24 [--.32 BIT MODE--
ADO-15 [.
i S- - - - - '(FlOATING)- - - - - - - - - - - - -.
-
i S-- - -- '(FlOATING) - - - - - - - - - - - - -.
-------
TLlEE/8692-41
FIGURE 4·14. Hold Timing (FLT = 1); SMR Instruction Not Being Executed
PHil [
I
PHI2 [
HLOAI [
HLOAO [
PAY [
m[
(HIGH)
Al~24 [_.~____~~~~____~
i S-----
AOO-15 [....: ________.:....______...:...J'
i S-----
'(FlOATING)-----~~r---E
'(FlOATING)- ---- ~~---C
TL/EE/8692-42
FIGURE 4·15. Hold Timing (FLT = 1); SMR Instruction Being Executed
~1
PHil [
PHI2 [
HOLD [
HLOAO [
PAY [
(FLOATING)
m[~------_+------_+--~--~------___~ ~----~~~~~------_+~_
Al~24 [~------_+------_+.J,
-------
AOO-15
[~------_+------_+.J,
-------
ODIN
[+ _______+------_+.J,
-------
S----- -(F~:~G)i S----i S----i
FIGURE 4·16. Hold Timing (FLT = 0)
3·77
-(FLOATING)-
-(FLOATING)-
-c
_l:::
'L
-C
TLlEE/8692-43
o.~
r--------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
~
CO)
(I)
Z
PHI1 [
PHI2 [
------1"",
TL/EE/B692-49
FIGURE 4-17. Clock Waveforms
PHil
[J-LJ--l...1uuVL.J--LfiJ-Lh.
PHI2 [
Ar/SPC
A24/HBF
\._~~~-~-___+5-~-O-C-K-~K"f.. Ilr-fj,.n..-
C
r.
[:+--t--""1'! ~-+_--t-§~,lo--...('I.....+--t§
TL/EE/8692-45
FIGURE 4-18. Reset Timing
vee
Jr--------ll---
PHI{ __-+__......
~[------------~r_~
FIGURE 4-19. Power-On Reset
3-78
TLlEE/8692-46
PER
eMIT
~
~
PERIPH CYCLE
XCTAL2
~
ICTAlt
MITI
RESET
RSTO
f.~}
Wiif.i
Wiii2 ~
N532201
TCU
_IT REQUESTS
:l
tADDA DECODED OR STRAPPED)
MIT1
PHI2
C.
;C.
AD
liD
PHil
"C
"C
CD
READY
WR
WR
~
-
ADS
RSlO eTTL
ODiN ROY oBE
:l
'"O
I
CD
HBE
10kD
--
~
+5
Q.
:l
CQ
en
C
CQ
CQ
CD
HOLD
.I.
ROY
c.>
~
CD
PHI1
'"O
PHI2
I
HOLD
HBE
en
O·
HLOAO
HOLD ROY
RSTI
:l
en
PHIt
INTS.
I......
1-<
PHI2
iNT
HLOAI
FLT
HLOA
NM.
OSlFlT
NS320161
N532C016
CPU
PFS
PFS
UtS
UIS
ADS
(24).
ADDRIDATA
MULTIPLEXED
BUS
510-513
510-513
RST/ABT
AT/SPC
SPC
+55~
(241
(16).
ADO-AD1S
SPC
NS32081
510-5T1
~
ADDRESS
(21-i
LATCH'
BUFFER
MMU
RST/ABT
A2'
ADDRIOATA
ADDRESS
STROBE
PAY
N532082
ADS
ODIN
DDIN
ADDRIDATA
HLOAD
lL
ffiiiN
(2'~
•
(24)
II
FPU
(161 . . . . .
CLK
EN
OATA
MULTIPLEXED
I==:
RST
BUS
(24)
BUS
RST
MEMORYI
PERIPERALS
ClK
(1.H
O'R
cgJ
DATA BUS
DATA BUFFERS
- --
TUEE/6692-47
Note: The "AND" gate on the HBE line is not needed when an NS32016 is used.
FIGURE A-1. System Connection Diagram
O~·~80~eSN
II
NS32082-10
PERI_
XCTAl2
-.::..
»
PERIPH CYCLE
CWlf!.lT
--'-
Cl
READY
"0
"0
CD
:;,
XCTAll
,
WAif4
v.im1i§1
M.1l2
NS32201
_jRSTI
RESET
rcu
PHI1
, I IpH17
RSTO
WAIT REOUESTS
IADOR. DECODED OR STRAPPED)
MIT1
iijj
WRI
ODIN ROY
;:C.
BEO:
~,
ern
Q.
iiD
ViR
~
~
I
+ S'
DBE
-
--
BE2
:;,
CD
Be3
H
1Y
S
2Y 3Y
74ALS257
...
~
4Y
G
D)
(')
18 28 38 48 1A 2A 3A 4A
111:
1
1
1
10
1
1111)JI~U
II II I
:;j.
~
(Q
en
c
(Q
(Q
ILO'
ROY
1
CD
HOLD
.i
PHil PHI2 BED . • • . . • BE3 j[Q
til
O·
HlOAO
HOLD ROY
PHil
PHI2
'"
Co
o
HOLD
J--+tiNT
I I
DS/Flrl'
INTS.\-+t NMI
'HCDA
NS32032
CPU
(24,,·
1
024-031
. • (8)
HLOAD
Piij
PFS
"'_I
I I
ADS
ODIN
AOO-AD23
I ' Iru
HLOAI
PFS
NS32082
~I"'--
MMU
ADS
ODIN
STO-SI3
STO-ST3
RST/ABT
RSf/m
,I
Arlspcl'
I
.~ SPC
10k1l
+5~
:;,
A1
ADO-A023
A241-t+
RSll
I
'~ (24)
~srROBE
I
~
til
g
a
ADORESS'"• • •~~.
ADO-AD23 LATCHI
::J
P
c
'"
BUFFER
,e,
+--.
(24)t_'(32)
ADO-AD1S
.,---ADDRfDATA BUS
•. 2)
AUU-AD23"
AND 024-031
DATA BU.........
~
5T0-513 ,
TLlEE/8692-48
FIGURE A-2. System Connection Diagram
z
(J)
~National
PRELIMINARY
~
Co)
Q)
~ Semiconductor
.....
•
.....
U1
.....
Z
NS32381-15/NS32381-20 Floating-Point Unit
(J)
Co)
~
.
Co)
Q)
General Description
The NS32381 is a second generation, CMOS, floating-point
slave processor that is fully software compatible with its
forerunner, the NS32081 FPU. The NS32381 FPU functions
with any Series 32000 CPU, from the NS32008 to the
NS32532, in a tightly coupled slave configuration. The performance of the NS32381 has been increased over the
NS32081 by architecture improvements, hardware enhancements, and higher clock frequencies. Key improvements include the addition of a 32-bit slave protocol, an
early done algorithm to increase CPU/FPU parallelism, an
expanded register set, an automatic power down feature,
expanded math hardware, and additional instructions.
The NS32381 FPU contains eight 64-bit data registers and
a Floating-Point Status Register (FSR). The FPU executes
20 instructions, and operates on both single and doubleprecision operands. Three separate processors in the
NS32381 manipulate the mantissa, sign, and exponent. The
NS32381 FPU conforms to IEEE standard 754-1985 for binary floating-point arithmetic.
When used with a Series 32000 CPU, the CPU and
NS32381 FPU form a tightly coupled computer cluster. This
cluster appears to the user as a single processing unit. All
addressing modes, including two address operations, are
available with the floating-point instructions. In addition,
CPU and FPU communication is handled automatically, and
is user transparent.
The FPU is fabricated with National's advanced double-metal CMOS process. It is available in a 68-pin Pin Grid Array
(PGA) package.
Features
with
NS32008,
NS32016,
• Directly
compatible
NS32C016, NS32032, NS32C032, NS32332 and
NS32532 microprocessors
• Selectable 16-bit or 32-bit Slave Protocol
• Conforms to IEEE standard 754-1985 for binary floating-point arithmetic
• Early done algorithm
• Single (32-bit) and double (64-bit) precision operations
• Eight on-chip (64-bit) data registers
• (Automatic) power down mode
• Full upward compatibility with existing 32000 software
• High speed double-metal CMOS design
• 68-pin PGA package
FPU Block Diagram
Control
Unit
Execution
Unit
Interface
and
Storage Unit
5
TL/EE/9157 -1
FIGURE 1·1
3-81
.....
~
Q
Q
~
r-----------------------------------------------------------------------------~
..-
~
Table of Contents
N
1.0 PRODUCT INTRODUCTION
(/)
1.1 IEEE Features Supported
C")
Z
U;
....CD
I
C")
N
~
Z
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.6 Instruction Protocols
1.2 Operand Formats
3.6.1 General Protocol Sequence
1.2.1 Normalized Numbers
3.6.2 Early Done Algorithm
1.2.2 Zero
3.6.3 Floating·Point Protocols
1.2.3 Reserved Operands
4.0 DEVICE SPECIFICATIONS
1.2.4 Integers
4.1 Pin Descriptions
1.2.5 Memory Representations
4.1.1 Supplies
2.0 ARCHITECTURAL DESCRIPTION
4.1.2 Input Signals
2.1 Programming Model
4.1.3 Output Signals
2.1.1 Floating-Point Registers
4.1.4 Input/Output Signals
2.1.2 Floating-Point Status Register (FSR)
4.2 Absolute Maximum Ratings
2.1.2.1 FSR Mode Control Fields
4.3 Electrical Characteristics
2.1.2.2 FSR Status Fields
4.4 Switching Characteristics
2.1.2.3 FSR Software Fields (SWF)
4.4.1 Definitions
2.2 Instruction Set
4.4.2 Timing Tables
2.2.1 General Instruction Format
4.4.2.1 Output Signal Propagation Delays for all
CPUs
2.2.2 Addressing Modes
4.4.2.2 Output Signal Propagation Delays for the
NS32008, NS32016, NS32032 CPUs
2.2.3 Floating-Point Instruction Set
2.3 ExceptionslTRAPS
4.4.2.3 Output Signal Propagation Delays for the
32·Bit Slave Protocol NS32332 CPU
3.0 FUNCTIONAL DESCRIPTION
4.4.2.4 Output Signal Propagation Delays for the
32-Bit Slave Protocol NS32532 CPU
3.1 Power and Grounding
3.2 Automatic Power Down Mode
4.4.2.5 Input Signal Requirements for all CPUs
3.3 Clocking
4.4.2.6 Input Signal Requirements for the
NS32008, NS32016, NS32032 CPUs
3.4 Resetting
3.5 Bus Operation
4.4.2.7 Input Signal Requirements for the 32-Bit
Slave Protocol NS32332 CPU
3.5.1 Bus Cycles
3.5.2 Operand Transfer Sequences
4.4.2.8 Input Signal Requirements for the 32-Bit
Slave Protocol NS32532 CPU
4.4.2.9 Clocking Requirements for all CPUs
APPENDIX A: NS32381 PERFORMANCE ANALYSIS
3-82
,-----------------------------------------------------------------------, z
List of Illustrations
FPU Block Diagram ......................•..................................................................... 1-1
Floating-Point Operand Formats ................................................................................. 1-2
Integer Format. .................................................................................•..............1-3
Register Set .........................................•..............•..........................................2-1
The Floating-Point Status Register ...............................................................................2-2
General Instruction Format ......................................................................................2-3
Index Byte Format .............................................................................................2-4
Displacement Encodings ........................................................................................2-5
Floating-Point Instruction Formats ................................................................................ 2-6
Recommended Supply Connections ............' .................................................................. 3-1
Power-On Reset Requirements .................................................................................. 3-2
General Reset Timing ..........................................................................................3-3
System Connection Diagram with the NS32532 CPU ...............•...............................................3-4a
System Connection Diagram with the NS32332 CPU ...............................................................3-4b
System Connection Diagram with the NS32008, NS32016 or NS32032 CPU .......................................... 3-4c
Slave Processor Read Cycle (NS32008, NS32016, NS32032 and NS32332 CPUs) ..................................... 3-5
Slave Processor Read Cycle (NS32532 CPU) ............•..............•.......................................... 3-6
Slave Processor Write Cycle (NS32008, NS32016, NS32032 and NS32332 CPUs) ..................................... 3-7
Slave Processor Write Cycle (NS32532 CPU) ......................................................................3-8
ID and Opcode Format 16-Bit Slave Protocol ...................................................................... 3-9
ID and Opcode Format 32-Bit Slave Protocol ..................................................................... 3-10
FPU Status Word Format ......................................................................................3-11
16-Bit General Slave Instruction Protocol: FPU Actions ............................................................ 3-12
32-Bit General Slave Instruction Protocol: FPU Actions ............................................................ 3-13
68-Pin PGA Package .......................................................................................... .4-1
Timing Specification Standard (Signal Valid After Clock Edge) .............•.......................................... 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
Clock Timing ..................................................................................................4-4
Power-On Reset ...............................................................................................4-5
Non-Power-On Reset ...........................................................................................4-6
RST Release Timing ............................................................................................4-7
Read Cycle from FPU (NS32008, NS32016, NS32032 CPUs) ....................................................... .4-8
Write Cycle to FPU (NS32008, NS32016, NS32032 CPUs) ........................................................... 4-9
Read Cycle from FPU (NS32332 CPU) .......................................................................... .4-10
Write Cycle to FPU (NS32332 CPU) .............................................................................4-11
SDN332 Timing (NS32332 CPU) ......................................•.........................................4-12
SDN332 (TRAP) Timing (NS32332 CPU) .........................................................................4-13
Read Cycle from FPU (NS32532 CPU) .......................................................................... .4-14
Write Cycle from FPU (NS32532 CPU) ........................................................................... 4-15
SDN532 Timing (NS32532 CPU) ................................................................................ 4-16
FSSR Timing (NS32532 CPU) ..................................................................................4-17
SPC Pulse from FPU ......................................................................................... .4-18
3-83
en
Co)
I\)
Co)
00
.....
•
.....
U1
......
z
en
Co)
I\)
Co)
.
00
.....
I\)
CI
~
..-•
CD
C")
C'i
~
Z
.....
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List of Tables
Sample F Fields ...............................................................................................1·1
Sample E Fields ...............................................................................................1·2
Normalized Number Ranges ..................................................................................... 1·3
Series 32000 Family Addressing Modes ...........................................................................2·1
16·Bit General Slave Instruction Protocol .......................................................................... 3·1
32·Bit General Slave Instruction Protocol .......................................................................... 3·2
Floating·Point Instruction Protocols ...............................................................................3·3
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The E field contains an unsigned number that gives the binary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be subtracted from the E field value in order to obtain the true
exponent. The bias value is 011 ... 112, which is either 127
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
1.0 Product Introduction
The NS32381 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed CMOS technology. It operates as a slave processor for transparent expansion of the Series 32000 CPU's basic instruction set. The
FPU can also be used with other microprocessors as a peripheral device by using additional TTL and CMOS interface
logic. The NS32381 is compatible with the IEEE FloatingPoint Formats by means of its hardware and software features.
Represented Value
EFleld
FField
1.5x2- 1 = 0.75
011 ... 110
100 ... 0
1.5x20 = 1.50
011 ... 111
100 ... 0
1.5x21 = 3.00
100 ... 000
100 ... 0
Two values of the E field are not exponents. 11 ... 11 signals a reserved operand (Section 1.2.3). 00 ... 00 represents the number zero if the F field is also all zeroes, otherwise it signals a reserved operand.
b) Add, subtract, multiply, divide and compare operations
c) Conversions between different floating-point formats
d) Conversions between floating-point and integer formats
e) Round floating-point number to integer (round to nearest, round toward negative infinity and round toward
zero, in double or single-precision)
1) Exception signaling and handling (invalid operation, divide by zero, overflow, underflow and inexact)
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The S bit indicates the sign of the operand. It is 0 for positive and 1 for negative. Floating-point numbers are in signmagnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
1.2.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.
The value of a Normalized number can be derived by the
formula:
(-1)5 X 2(E-Bias) X (1 + F)
The remaining IEEE features are supported in software.
These items include:
a) Extended floating-point number formats
b) Positive and negative infinity, Not-a-Number (NaN), Denormalized numbers
c) Square root and conversions between basic formats,
floating-point numbers and decimal strings
The range of Normalized numbers is given in Table 1-3.
1.2 OPERAND FORMATS
The N32381 FPU operates on two floating-point data
typeS-Single precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single precision data type, and the
suffix L (Long Floating) to select the double preCision data
type.
A floating-point number is divided into three fields, as shown
in Figure 1-2.
1.2.2 Zero
There are two representations for zero-positive and negative. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.
1.2.3 Reserved Operands
The proposed IEEE Standard for Binary Floating-Point Arithmetic (Task P754) provides for certain exceptional forms of
floating-point operands. The NS32381 FPU treats these
forms as reserved operands. The reserved operands are:
• Positive and negative infinity
• Not-a-Number (NaN) values
• Denormalized numbers
80th Infinity and NaN values have all ones in their E fields.
Denormalized numbers have all zeroes in their E fields and
non-zero values in their F fields.
The NS32381 FPU causes an Invalid Operation trap (Section 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.
The F field is the fractional portion of the represented number. In Normalized numbers (Section 1.2.1), the binary pOint
is assumed to be immediately to the left of the most significant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
1.0 s:; x s:; 2.0.
TABLE 1-1. Sample F Fields
Binary Value
1.000 ... 0
1.010 ... 0
1.100 ... 0
1.110 ... 0
(0)
(0)
TABLE 1-2. Sample E Fields
1.1 IEEE FEATURES SUPPORTED
a) Basic floating-point number formats
FFleld
000 ... 0
010 ... 0
100 ... 0
110 ... 0
(I)
Decimal Value
1.000 ... 0
1.250 ... 0
1.500 ... 0
1.750 ... 0
t
Implied Bit
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1.0 Product Introduction
(Continued)
Single Precision
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11
52
FIGURE 1·2. Floating·Polnt Operand Formats
TABLE 1·3. Normalized Number Ranges
Most Positive
Least Positive
Least Negative
Single Precision
2127 x (2 - 2- 23)
= 3.40282346 x 1038
Double Precision
2 1023 X (2 - 2- 52)
= 1.7976931348623157 X 10308
2- 126
= 1.17549436 X 10- 38
2- 1022
= 2.2250738585072014 X 10-308
-(2- 126)
= -1.17549436
Most Negative
-(2- 1022)
x 10- 38
-2127 X (2 - 2- 23)
= -2.2250738585072014 X 10- 308
-21023 X (2 - 2- 52)
= -1.7976931348623157 X 10308
= - 3.40282346 x 1038
Note: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
1.2.4 Integers
In addition to performing floating-point arithmetic, the
NS32381 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generated by the FPU as two's complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.
1.2.5 Memory Representations
The NS32381 FPU does not directly access memory. However, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.
In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the instruction format) with the most significant byte at the lowest
address.
See Figure 1-3 for the Integer Format and Table 1-4 for the
Integer Fields.
n-l
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FIGURE 1·3. Integer Format
2.0 Architectural Description
TABLE 1·4. Integer Fields
S
Value
2.1 PROGRAMMING MODEL
Name
0
I
Positive Integer
1
1- 2n
Negative Integer
The Series 32000 architecture includes nine registers that
are implemented on the NS32381 Floating-Point Unit (FPU).
Note: n represents n number of bits in the word. 8 for byte. 18 for word and
32 for double-word.
3-86
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2.0 Architectural Description (Continued)
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DEDICATED
I+- 32--.j
I FSR
I
1--32
·32Fl
MSDW
LSDW
F3 L2 MSDW
L2 LSDW
F5 L4 MSDW L4 LSDW
F7 ~~~~~s---l
LO
L2
L4
L6
Ll
r.;~~t-7;,f_~SIN;-I L3
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LSDW ---. least significant double word
MSDW ---. most significant double word
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TL/EE/9157-36
FIGURE 2-1. Register Set
Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in absolute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.
Inexact Result Trap Enable (lEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.
2.1.1 Floating-Point Registers
There are eight registers (lO-l7) on the NS32381 FPU for
providing high-speed access to floating-point operands.
Each is 64 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register addressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (i.e., integer operands) refer
to the General Purpose Registers (RO-R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
Nole: These registers are all upward compatible with the 32-bit NS32081
registers, (FO-F7I. such that when the Register addressing mode is
specified for a double precision (84-bitl operand, a pair of 32-bit reg-
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions encountered during floating-point data processing. The meanings of the FSR status bits are given below:
Trap Type (TT): bits 0-2. This 3-bit field records any exceptional condition detected by a floating-point instruction. The
n field is loaded with zero whenever any floating-point instruction except lFSR or SFSR completes without encountering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the load FSR
(lFSR) instruction. Underflow and Inexact Result are always
reported in the n field, regardless of the settings of the
UEN and lEN bits.
isters holds the operand. The programmer specifies the even register
of the pair which contains the least significant half of the operand and
the next consecutive register contains the most significant half.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating-point operation. Figure 2-2
shows the format of the FSR.
9876543210
TL/EE/9157-37
FIGURE 2-2. The Floating-Point Status Register
000 No exceptional condition occurred.
001 Underflow. A non-zero floating-point result is too small
in magnitude to be represented as a normalized floating-point number in the format of the destination operand. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set.
If the UEN bit is not set, a result of Positive Zero is
produced, and no trap occurs.
2.1.2.1 FSR Mode Control Fields
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given below.
Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded whenever they cannot be exactly represented. The rounding
modes are:
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly halfway between the two nearest values the even value
(lSB = 0) is returned.
01 Round toward zero. The nearest value which is closer
to zero or equal to the exact result is returned.
10 Round toward positive infinity. The nearest value which
is greater than or equal to the exact result is returned.
11
010 Overflow. A result (either floating-point or integer) of a
floating-point instruction is too great in magnitude to
be held in the format of the destination operand. Note
that rounding, as well as calculations, can cause this
condition.
011 Divide by zero. An attempt has been made to divide a
non-zero floating-point number by zero. Dividing zero
by zero is considered an Invalid Operation instead
(below).
100 Illegal Instruction. Any instruction forms not included
in the NS32381 Instruction Set are detected by the
FPU as being illegal.
Round toward negative infinity. The nearest value
which is less than or equal to the exact result is returned.
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2.0 Architectural Description
101
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(Continued)
Invalid Operation. One of the floating-point operands
of a floating-point instruction is a Reserved operand,
or an attempt has been made to divide zero by zero
using the DIVf instruction .
not otherwise used by FPU hardware. They are reserved for
use with NSC floating-point extension software.
2.2 INSTRUCTION SET
2.2.1 General Instruction Format
110 Inexact Result. The result (either floating-point or integer) of a floating-point instruction cannot be represented exactly in the format of the destination operand, and a rounding step must alter it to fit. This condition is always reported in the TT field and IF bit unless
any other exceptional condition has occurred in the
same instruction. In this case, the TT field always contains the code for the other exception and the IF bit is
not altered. A trap is caused by this condition only if
the lEN bit is set; otherwise the result is rounded and
delivered, and no trap occurs.
111
Figure 2·3 shows the general format of an Series 32000
instruction. The Basic Instruction is one to three bytes long
and contains the opcode and up to two 5·bit General Addressing Mode (Gen) fields. Following the Basic Instruction
field is a set of optional extensions, which may appear depending on the instruction and the addressing modes se·
lected.
The only form of extension issued to the NS32381 FPU is
an Immediate operand. Other extensions are used only by
the CPU to reference memory operands needed by the
FPU.
(Reserved for future use.)
Underflow Flag (UF): Bit 4. This bit is set by the FPU whenever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before index·
ing. See Figure 2-4.
Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-5, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most signifi·
cant byte first.
Register Modify Bit (RMB): Bit 16. This bit is set by the
FPU whenever writing to a floating point data register. The
RMB bit is cleared only by writing a zero with the LFSR
instruction or by a hardware reset. This bit can be used in
context switching to determine whether the FPU registers
should be saved.
Some non·FPU instructions require additional, "implied" immediates and/or displacements, apart from those associat·
ed with addressing modes. Any such extensions appear at
the end of the instruction, in the order that they appear within the list of operands in the instruction definition.
2.1.2.3 FSR Software Field (SWF)
Bits 9·15 of the FSR hold and display any information writ·
ten to them (using the LFSR and SFSR instructions), but are
OPTIONAL
EXTENSIONS
BASIC
INSTRUCTION
rr-------------------~~--------------------\lr---------~~---------\
,,,
DISP2 DISP1 DISP21DISP1
IMPUED
IMMEDIATE
OPERAND(S)
DISP
DISP
IMM
IMM
t
INDEX
BYTE
INDEX
BYTE
GEN
ADDR
MODE
A
I
:,
,I,
GEN
ADDR
MODE
B
OPCODE
I
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TLlEE/9157-2
FIGURE 2-3. General Instruction Format
3-88
2.0 Architectural Description
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2.2.2 Addressing Modes
Absolute: The address of the operand is specified by a
Displacement field in the instruction.
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
Top of Stack: The currently-selected CPU Stack Pointer
(SPO or SP1) specifies the location of the operand. The operand is pushed or popped, depending on whether it is written or read.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
The following table, Table 2-1, is a brief summary of the
addreSSing modes. For a complete description of their actions, see the Series 32000 Instruction Set Reference Manual.
The Series 32000 Family CPUs generally access an operand by calculating its Effective Address based on information available when the operand is to be accessed. The
method to be used in performing this calculation is specified
by the programmer as an "addressing mode."
Addressing modes in the Series 32000 family are designed
to optimally support high-level language accesses to variables. In nearly all cases, a variable access requires only
one addressing mode within the instruction which acts upon
that variable. Extraneous data movement is therefore minimized.
Series 32000 Addressing Modes fall into nine basic types:
Register: In floating-point instructions, these addressing
modes refer to a Floating-Point Register (FO-F7) or (LOL7) if the operand is of a floating-point type. Otherwise. a
CPU General Purpose Register (RO-R7) is referenced. See
Section 2.1.1Register Relative: A CPU General Purpose Register contains an address to which is added a displacement value
from the instruction, yielding the Effective Address of the
operand in memory.
N
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SIGNED DISPLACEMENT
GEN. ADDR. MODE
TL/EE/9157-3
FIGURE 2-4. Index Byte Format
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated CPU
registers PC, SP, S8 or FP. These registers point to data
areas generally needed by high-level languages.
7
1 11
Memory Relative: A pointer variable is found within the
memory space pointed to by the CPU SP, S8 or FP register.
A displacement is added to that pointer to generate the Effective Address of the operand.
Immediate: The operand is encoded within the instruction.
This addreSSing mode is not allowed if the operand is to be
written. Floating-point operands as well as integer operands
may be specified using Immediate mode.
0
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TL/EE/9157 -4
FIGURE 2-5. Displacement Encodings
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2.0 Architectural Description
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00000
00001
00010
00011
00100
00101
00110
00111
(Continued)
TABLE 2·1. Series 32000 Family Addressing Modes
Mode
Assembler Syntax
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
FO or LO
F1 or L1
F20r L2
F30r L3
F4 or L4
F50r L5
F60r L6
F7 or L7
Effective Address
None: Operand is in the specified register.
REGISTER RELATIVE
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
"+disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (SB))
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP" is
either SPO or SP1, as selected in PSR.
Immediate
value
None: Operand is issued from
CPU instruction queue.
Absolute
@disp
Disp.
External
EXT (disp1)+ disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp 1.
Top of Stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
Mode + Rn.
Mode + 2 x Rn.
Mode + 4 X Rn.
Mode + 8 x Rn.
"Mode" and "n" are contained
within the Index Byte.
10011
(Reserved for Future Use)
MEMORY SPACE
11000
11001
11010
11011
MEMORY RELATIVE
10000
10001
10010
IMMEDIATE
10100
ABSOLUTE
10101
EXTERNAL
10110
TOP OF STACK
10111
SCALED INDEX
3·90
2.0 Architectural Description
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2.2.3 Floating-Point Instruction Set
The NS32381 FPU instructions occupy formats 9, 11 and 12
of the Series 32000 Family instruction set (Figure 2-6). A
list of all Series 32000 family instruction formats is found in
the applicable CPU data sheet.
Certain notations in the following instruction description tables serve to relate the assembly language form of each
instruction to its binary format in Figure 2-6.
23
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g8n1
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I
I i
gen2
up
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0 1 1 1 1 1 0
OPERATION WORO
Movement and Conversion
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Instruction
11
0001 MOVf
gen1,gen2
I
,
10 BYTE
TL/EE/9157-5
9
010 MOVLF
gen1, gen2
9
011
gen1, gen2
9
000 MOVif
gen1,gen2
9
100 ROUNDfi
gen1, gen2
9
101 TRUNCfi
gen1, gen2
9
111
gen1, gen2
Format 11
23
l
~'n:
I
~en2
I
I I ~p
I
I
I I I I I
\ 0 \1 1 0 1 1 1 1 1 0
n
OPERATION WORD
I
MOVFL
,
10 BYTE
TL/EE/9157-6
Format 12
TUEE/9157 -7
FIGURE 2-6. Floating-Point Instruction Formats
The Format column indicates which of the three formats in
Figure 2-6 represents each instruction.
The Op column indicates the binary pattern for the field
called "op" in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case, with one or more suffixes (i or f) indicating data types, followed by a list of operands (gen1, gen2).
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This choice affects the binary pattern in
the i field of the corresponding instruction format (Figure 2-6)
as follows:
FLOORfi
Description
Move without
conversion
Move, converting
from double
precision to
single precision.
Move, converting
from single
precision to
double
precision.
Move, converting
from any integer
type to any
floating-point
type.
Move, converting
from floatingpoint to the
nearest integer.
Move, converting
from floatingpoint to the
nearest integer
closer to zero.
Move, converting
from floatingpoint to the
largest integer
less than or
equal to its
value.
Note: The MOVLF instruction f bit must be 1 and the i field must be 10.
The MOVFL instruction f bit must be 0 and the i field must be 11.
Suffix i
B
W
D
Data Type
Byte
Word
Double Word
iField
00
01
11
Arithmetic Operations
The following instructions perform floating-point arithmetic
operations on the gen1 and gen2 operands, leaving the result in the gen2 operand.
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format (Figure 2-6)
as follows:
Suffix f
F
L
Data Type
Single Precision
Double Precision (Long)
f Bit
1
o
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the bin-
3-91
.
U1
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The following instructions move the gen1 operand to the
gen2 operand, leaving the gen1 operand intact.
Format 9
I\)
Co)
ary pattern in the corresponding gen1 or gen2 field of the
instruction format (Figure 2-6). Refer to Table 2-1 for the
options available and their patterns.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
Format
11
Op
0000
11
0100
Instruction
ADDf gen1,gen2
SUBf gen1,gen2
11
1100
MULf
gen1,gen2
Description
Add gen1 to gen2.
Subtract gen 1
from gen2.
Multiply gen2 by
gen1.
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2.0 Architectural Description (Continued)
Format Op
Instruction
Description
11
1000 DIVf
gen1, gen2 Divide gen2 by gen1.
11
0101 NEGf gen1, gen2 Move negative of
gen1 to gen2.
11
1101 ASSf
gen1, gen2 Move absolute value
of gen1 to gen2.
(N)
12 0100 SCALSf gen1, gen2 Move gen2'2g en1 to
gen2, for integral
values of gen1
without computing
2g en1 •
(N)
12
(N)
12
(N)
12
Rounding
The FPU supports all IEEE rounding options: Round toward
nearest value or even significant if a tie. Round toward zero,
Round toward positive infinity and Round toward negative
infinity.
2.3 EXCEPTIONS/TRAPS
The FPU supports five types of traps: Invalid operation, Divi·
sion by zero, Overflow, Underflow and Inexact (one trap can
be signaled at a time). The user can disable the Inexact and
the Underflow traps. If an undefined Floating·Point instruc·
tion is passed to the FPU an Illegal Instruction trap will oc·
cur. The user can't disable trap on Illegal Instruction.
Upon detecting an exceptional condition in executing a
floating·point instruction, the FPU requests a TRAP by puis·
ing the SPC line for one clock cycle, pulsing the SDN332
line for two and a half clock cycles and pulsing the FSSR
line for one clock cycle. (The user will connect the correct
lines according to the CPU being used).
0101 LOGSf gen1,gen2 Move the unbiased
exponent of gen1 to
gen2.
0011 DOTI gen1, gen2 Move (gen1'gen2)
+ LOto LO.
0010 POLYf gen1, gen2 Move (LO'gen1) +
gen2 to LO.
In addition, the FPU sets the Q bit in the status word regis·
ter. The CPU responds by reading the status word register
while applying status h'E (transferring status word) on the
status lines. A trapped instruction returns no result (also if
the destination is FPU register) and does not affect the CPU
PSR. The FPU displays the reason for the TRAP in the
TRAP TYPE (TT) field of the FSR. If the CPU sends FPU ID
with illegal opcode, the FPU generates TRAP(UND) by sig·
naling TRAP and setting the T bit in the status word register.
(N): Indicates NEW instruction.
Comparison
The Compare instruction compares two floating-point values, sending the result to the CPU PSR Z and N bits for use
as condition codes. See Figure 3-11. The Z bit is set if the
gen1 and gen2 operands are equal; it is cleared otherwise.
The N bit is set if the gen1 operand is greater than the gen2
operand; it is cleared otherwise. The CPU PSR L bit is unconditionally cleared. Positive and negative zero are considered equal.
Format
11
Op
0010
Instruction
CMPf gen1, gen2
3.0 Functional Description
Description
Compare gen1
to gen2.
3.1 POWER AND GROUNDING
The NS323B1 requires a single 5V power supply, applied on
seven (VeC> pins. These pins should be connected together
by a power {VeC> plane on the printed circuit board. See
Figure 3-1.
Floating·Point Status Register Access
The following instructions load and store the FSR as a 32·
bit integer.
Format
9
9
Op
001
110
The grounding connections are made on eight (GND) pins.
These pins should be connected together by a ground
(GND) plane on the printed circuit board. See Figure 3-1.
Description
Load FSR
StoreFSR
Instruction
LFSR
gen1
SFSR
gen2
Note: All instructions support all of the NS32000 family data formats (for
extemal operands) and all addressing modes are supported.
+5V
NS32381
K5
•
Kll GND
TLIEEI9157 -8
FIGURE 3·1. Recommended Supply Connections
3-92
z
en
w
3.0 Functional Description (Continued)
N
W
V 4.5VII"'"---------------I~S----CC...J
ClK
-~----------------~
l-:? 64C~~~~~
+-_____________
R5T __
co
.....
.....•
r
U'I
.....
z
en
w
~
N
W
co
.....
•
~"
1-------~30
N
o
1'5--------- •
TLlEE/9157-9
FIGURE 3-2. Power-On Reset Requirements
3.2 AUTOMATIC POWER DOWN MODE
The NS32381 supports a power down mode in which the
device consumes only 10% of its original power at 30 MHz.
The NS32381 enters the power down mode (internal clocks
are stopped with phase two high) if it does not receive an
SPC pulse from the CPU within 256 clocks.
either one byte (8 bits), one word (16 bits) or one double
word (32 bits) to or from the FPU. During all bus cycles, the
SPC line is driven by the CPU as an aciive low data strobe,
and the FPU monitors pins STO-ST3 to keep track of the
sequence (protocol) established for the instruction being executed. This is necessary in a virtual memory environment,
allowing the FPU to retry an aborted instruction.
The FPU exits the power down mode and returns to normal
operation after it receives an SPC from the CPU. There is no
extra delay caused by the FPU being in the power down
mode.
3.5.1 Bus Cycles
A bus cycle is initiated by the CPU, which asserts the proper
status on (STO-ST3) and pulses SPC low. The status lines
are sampled by the FPU on the leading (falling) edge of the
SPC pulse except for the 32532 CPU. When used with the
32532 CPU, the status lines are sampled on the rising edge
of CLK in the T2 state. If the transfer is from the FPU (a
slave processor read cycle), the FPU asserts data on the
data bus for the duration of the SPC pulse. If the transfer is
to the FPU (a slave processor write cycle), the FPU latches
data from the data bus on the trailing (rising) edge of the
SPC pulse. Figures 3-5, 3-6, 3-7 and 3-8 illustrate these
sequences.
3.3 CLOCKING
The NS32381 FPU requires a single-phase TIL clock input
on its CLK pin (pin A8). When the FPU is connected to a
Series 32000 CPU, the CLK signal is provided from the
CTIL pin of the NS32201 Timing Control Unit.
3.4 RESETTING
The RST pin serves as a reset for on-chip logic. The FPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPU terminates instruction processing, resets its internal logic, and
clears the FSR to all zeroes.
On application of power, RST must be held low for at least
30 /Ls after Vee is stable. This ensures that all on-chip voltages are completely stable before operation. See Figures
3-2 and 3-3.
ClK
The direction of the transfer and the role of the bidirectional
SPC line are determined by the instruction protocol being
performed. SPC is always driven by the CPU during slave
processor bus cycles. Protocol sequences for each instruction are given in Section 3.6.
3.5.2 Operand Transfer Sequences
lLfLfLSLJl
_
_ _ _ _.._...............
An operand is transferred in one or more bus cycles. For the
16-8it Slave Protocol a 1-byte operand is transferred on the
least significant byte of the data bus (00-07). A 2-byte operand is transferred on the entire bus. A 4-byte or 8-byte
operand is transferred in consecutive bus cycles, least significant word first.
For the 32-8it Slave Protocol a 4-byte operand is transferred on the entire data bus in a single bus cycle and an
8-byte operand is transferred in two consecutive bus cycles
with the most significant byte transferred on data bits (0007). The complete operand transfer of bytes 80-87 where
80 is the least significant byte would appear on the data bus
as 84, 85, 86, 87 followed by 80, 81, 82, 83 in the second
bus cycle.
,,64ClDCK--I
CYCLES
I
I
iiSf
/I
Tl/EE/9157-10
FIGURE 3-3. General Reset Timing
3.5 BUS OPERATION
Instructions and operands are passed to the NS32381 FPU
with slave processor bus cycles. Each bus cycle transfers
3-93
~
..-
co
C')
3.0 Functional Description
(Continued)
-
+5V
z~
....
LI)
....-•
+5V
10k
10k
lk
lk
lk
co
C')
N
C')
NOE
tJ)
Z
SPC
ODIN
00-D31
1
PSO
PSI
SPC
..
32-BIT
DATA BUS
ODIN
-II.
DO-031
(NS32532)
510
STO
(NS32381)
CPU
STI
STI
FPU
ST2
ST2
ST4
ST3
SDN
SDN532
FSSR
FSSR
BClK
ClK
R51
RESERVED
M!L
RESERVED
!!..-
RESERVED
..!!.!-
=-
R51
I
TL/EE/9157-38
FIGURE 3-4a. System Connection Diagram with the NS32532 CPU
+5V
)
+5V
10k
+5V
Ik
Ik
NOE
SPC
DDIN
ADO-AD31
PSO
SPC
..
DDIN
32-BIT
DATA BUS
I\.
00-031
~
~
(NS32332)
STO
510
(NS32381)
CPU
STI
STI
FPU
512
512
ST3
513
SDN332
iiT/SDONE
R51/ABT
RESERVED
~
RESERVED
!!..-
RESERVED
..!!.!-
R51
I
I
ClK
cm
R510
SYSTEM ..
RESET
PSI
'17
R51I
NS32201
TCU
TL/EE/9157 -39
FIGURE 3-4b. System Connection Diagram with the NS32332 CPU
3-94
z
3.0 Functional Description
(J)
Co)
(Continued)
N
Co)
co
.....
+5V
c
.
.....
I
U1
......
10k
Z
Ar/SPC
DDIN
A
(NS32016)
STI
"
PSI
l-
N
Co)
co
.....
I
N
o
DO-DIS
I'
(NS32008)
CPU
STO
(NS32381)
STI
FPU
--.
ST2
r--+
ST3
-:.=
-
RESERVED
1
RSTO
.ill......
RESERVED ~
RST/ABi'
SYSTEM
~
PSO
Co)
DDIN
16-BIT
DATA BUS
'I
STO
~
NOE
SPC
ADO-ADI5
(NS32032)
J
(J)
RESERVED
11-
CLK
I
-==-
em
RSTI
RESET
NS32201
TCU
TLlEE/9157-40
FIGURE 3-4c. System Connection Diagram with the NS32008, NS32016 or NS32032 CPU
STO,STI
&Pi:
~",,_ _ _ _VA.,.LIO_ _ _-,~
-----------~-"
DO-D15 - - - - - - - - - -
~
~,,_ _ _VA_Ll_O_FR_O_M_FP_U_ _.I}- -TL/EE/9157 -12
Note 1: FPU samples CPU status here.
FIGURE 3-5. Slave Processor Read Cycle (NS32008, NS32016, NS32032 and NS32332 CPUs)
3-95
•
C) r---------------------------------------------------------------------------------~
....co~
3.0 Functional Description (Continued)
r-
~
o
z
......
II)
....•
....
CO
CO)
C'II
TI --+--
ClK
+
(NOTEI)
STO-5T4
CO)
(J)
Z
ODIN
ZZZZOVZX'--_ _---Jxzzzmz
I/Z7l//llA
m7ll11
1
\ ' - -_ _ _.....J
Do-rel----------------------------«~________________________J)~-------------TL/EE/9157-13
Nole 1: FPU samples CPU status here.
FIGURE 3-6. Slave Processor Read Cycle (NS32532 CPU)
STO, STI
VALID
__________________1(NOTE 1)
(NOTE 2)
VALID FROM CPU
DO-015 - - - - -
TLlEE/9157 -14
Nole 1: FPU samples CPU status here.
Nole 2: FPU samples data bus here.
FIGURE 3-7. Slave Processor Write Cycle (NS3200S, NS32016, NS32032 and NS32332 CPU)
ClK
+
(NOTE I)
5TO-5T3
ODIN
71171//17X~~X!,....,..Z"T""'T71....,....,7/,.......,...Z.,......,..I/"T""'TI/.....,........,7
ZII0ZOIY
VZ71Z1///
\'----x-
i (NOTE 2)
,,J)>-------
D O - D 3 1 - - - - - - - - - - « \ "_ _ _ _ _
TL/EE/9157 -15
Nole 1: FPU samples CPU status here.
Nole 2: FPU samples data bus here.
FIGURE 3-S. Slave Processor Write Cycle (NS32532 CPU)
3-96
z
en
Co)
3.0 Functional Description (Continued)
N
3.6 INSTRUCTION PROTOCOLS
2) It specilies which Slave Processor will execute it.
3.6.1 General Protocol Sequences
3) It determines the lormat 01 the following Operation Word
01 the instruction.
The NS32381 supports both the 16·bi\ and 32-bit General
Slave protocol sequences. See Tables 3-1,3-2 and Figures
3-12, 3-13 respectively.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Table 3-3. Then depending on
the state 01 the Protocol Select Signals PSO and PS1, either
the 16·bit or a 32·bi\ Slave protocol is used. The NS32008,
NS32016, NS32C016, NS32032 and the NS32C032 all
communicate with the NS32381 using the 16-bit Slave Protocol. The NS32332 and NS32532 CPUs communicate with
the NS32381 using a 32-bit Slave Protocol; a different version is provided lor each CPU.
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an ID byte followed by an Operation Word. See Figure 3-9 for the ID and Opcode lormat
16-bit Slave Protocol and Figure 3-10 lor the ID and Opcode
Format 32-bit Slave Protocol. The ID Byte has three lunctions:
1) It identilies the instruction to the CPU as being a Slave
Processor instruction.
TABLE 3-1. 16-Bit General Slave Instruction Protocol
Step
Status
1
ID (1111)
OP(1101)
OP(1101)
2
3
4
5
6
7
ST(1110)
OP(1101)
Action
CPU sends ID Syte
CPU sends Operation Word
CPU sends required operands (il any)
Slaves starts execution (CPU preletches)
Slave pulses SPC low
CPU Reads Status Word
CPU Reads Result (il destination is
memory and il no TRAP occurred)
TABLE 3-2. 32-Bit General Slave Instruction Protocol
Step
Status
Action
1
ID (1111)
OP (1101)
CPU sends ID and Operation Word
CPU sends required operands (il any)
Slaves starts execution (CPU prefetches)
Slave signals DONE or TRAP or CMPI
CPU Reads Status Word (II TRAP was signaled
or a CMPf instruction was executed)
CPU Reads Result (if destination is memory and
if no TRAP occurred)
2
3
4
5
6
ST(1110)
OP(1101)
TABLE 3-3. Floating-Point Instruction Protocols
Mnemonic
ADDI
SUSI
MUll
DIVf
MOVI
ASSI
NEGf
CMPI
FLOORli
TRUNCfi
ROUNDli
MOVFL
MOVLF
MOVif
LFSR
SFSR
SCALSI
LOGSI
DOTI
POLY!
D
~
Operand 1
Class
Operand 2
Class
Operand 1
Issued
Operand 2
Issued
read.1
read.f
read.f
read.1
read.f
read.f
read.1
read.f
read.f
read.1
read.!
read.F
read.L
read.i
read.D
rmw.f
rmw.f
rmw.f
rmw.f
write.f
write.f
write.f
read.1
write.i
write.i
write.i
write.L
write.F
write.f
I
f
I
I
I
I
I
I
I
I
I
F
L
i
D
I
I
I
I
N/A
write.D
rmw.f
write.!
read.f
read.!
read.1
read.!
read.!
read.f
N/A
N/A
f
f
f
!
Double Word
i = Integer size (B, W. D) specified in mnemonic.
f
~
NI A
Floating·Point type (F. L) specified in mnemonic.
~
Not Applicable to this instruction.
3-97
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I
N/A
!
I
Returned Value
ftoOp.2
ItoOp.2
ItoOp.2
ItoOp.2
ItoOp.2
ItoOp.2
ItoOp.2
N/A
itoOp.2
itoOp.2
itoOp.2
LtoOp.2
Fto Op. 2
Ito Op. 2
N/A
DtoOp.2
ftoOp.2
!toOp.2
!toFO
!toFO
PSRBits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
none
none
none
none
Co)
Q)
......
•
......
(II
......
z
en
Co)
N
Co)
Q)
......
•
N
CI
~
•
co
C")
....
C'\I
3.0 Functional Description (Continued)
7
o
tion and for the CPU to continue with the 16-Bit Slave Protocol by reading the FPU's status word.
For the 32-bit Slave Protocol, upon completion of the instruction, the FPU will signal the CPU by pulsing either
SDNXXX or FSSR (Force Slave Status Read) .
A half clock cycle SDN332 pulse with a NS32332 CPU indicates a valid completion of the instruction and that there is
no need for the CPU to read its Status Word.
C")
en
z
.....
ID Byte
....•
....
co
II)
15
I OPCODE low
~
o
I
7
0
OPCODE high
I
Byte 1
Byte 0
Operation Word
FIGURE 3-9. 10 and OPCODE Format
16-Bit Slave Protocol
z
0
A two and a half clock cycle SDN332 pulse indicates that
there is a need for the CPU to read its Status Word. In the
case of the NS32532 CPU, a one clock cycle SDN532 pulse
indicates a valid completion of the instruction and that there
is no need to read the Status Word.
For the 16-bit Slave Protocol the CPU applies Status Code
1111 (Broadcast ID. Tables 3-1, 3-2), and sends the ID Byte
on the least significant half of the Data Bus (DO-D7). The
CPU next sends the Operation Word while applying Status
Code 1101 (Transfer Slave Operand, Tables 3-1, 3-2). The
Operation Word is swapped on the Data Bus; that is, bits 07 appear on pins D8-D15, and bits 8-15 appear on pins
DO-D7.
A one clock cycle FSSR pulse is used to indicate the need
for the CPU to read the Status Word.
In all cases and for both the 16-Bit and 32-Bit Slave Protocols the CPU will use SPC to read the Status Word from the
FPU, while applying status code (1110). This word has the
format shown in Figure 3-11. If the Q bit ("Quit", Bit 0) is set,
this indicates that an error (TRAP) has been detected by the
FPU. The CPU will not continue the protocol, but will immediately trap through the Slave vector in the Interrupt Table. If
the instruction being performed is CMPf (Section 2.2.3) and
the Q bit is not set, the CPU loads Processor Status Register (PSR) bits N, Z and L from the corresponding bits in the
FPU Status Word. The FPU always sets the L bit to zero.
For the 32-bit Slave Protocol the CPU applies Status Code
1111 and sends the ID Byte (different ID for each format) in
byte 3 (D24-D31) and the Operation Word in bytes 1 and 2
in a Single double word transfer. The Operation Word is
swapped such that OPCODE low appears on byte 2 (D16D23) and OPCODE high appears on byte 1 (D8-D15). Byte
o (DO-D7) is not used.
The last step in the Slave Protocol if no errors have occurred and the result's destination is memory will be for the
CPU to read the result. Here again the CPU uses SPC to
read the result from the FPU and transfer it to its destination. These Read cycles from the FPU are performed by the
CPU while applying Status Code 1101 (Transfer Slave Operand).
31
I
23
ID
15
IOPCODE low IOPCODE highl
7
XXXXXXX1
Byte 3
Byte 2
Byte 1
Byte 0
FIGURE 3-10. 10 and OPCODE Format
32-Blt Slave Protocol
All Slave Processors input and decode the data from these
transfers. The Slave Processor selected by the ID Byte is
activated and from this point the CPU is communicating only
with it. If any other slave protocol is in progress (e.g., an
aborted Slave instruction), this transfer cancels it. At this
point also, both the CPU and FPU are aware of the number
of operands to be transferred and their sizes.
Bit
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the FPU. To do so, it references any Addressing Mode extensions appended to the FPU instruction. Since the CPU is
solely responsible for memory accesses, these extensions
are not sent to the Slave Processor. The Status Code applied is 1101 (Transfer Slave Processor Operand, Tables
3-1,3-2).
Description
(0)
Q:
Set to "1" if an FPU TRAP (error) occurred.
Cleared to '0" by a valid CMPf.
(2)
(6)
L:
Z:
Cleared to "0" by the FPU.
Set to "1" if the second operand is equal to
the first operand. Otherwise it is cleared to
(7)
N:
(15)
T:
Set to "1" if the second operand is less than
the first operand. Otherwise it is cleared to
"0".
After the CPU has issued the last operand, the FPU starts
the actual execution of the instruction. A one clock cycle
SPC pulse is used to indicate the completion of the instruc-
3-98
Setto "1" iftheTRAP is (UND) and cleared to
"0" if the TRAP is (FPU).
FIGURE 3-11. FPU Status Word Format
z
3.0 Functional Description
en
Co)
(Continued)
N
.........
CJ1
Co)
QI)
.......
z
en
Co)
N
Co)
QI)
....•
N
o
READ OPERAND
(BUS STATUS = I 101)
GO
TL/EE/9157-16
FIGURE 3-12. 16-Blt General Slave Instruction Protocol: FPU Actions
READ OPERAND
(BUS STATUS=IIOI)
y
Pulse Active
--
1
SDN332 for:1 clock
or
SiiN532 for I clock (DONE)
TL/EE/9157-17
FIGURE 3-13. 32-Bit General Slave Instruction Protocol: FPU Actions
3-99
.....
o
N
CO
C")
N
C")
(/)
Z
.....
an
........•
co
C")
N
C")
(/)
Z
3.0 Functional Description (Continued)
3.6.2 Early Done Algorithm
The NS32381 has the ability to modify the General Slave
protocol sequences and to boost the performance of the
FPU by 20% to 40%. This is called the Early Done Algorithm .
Early Done is defined by the fact that the destination of an
instruction is an FPU register and that the instruction and
range of operands cannot generate a TRAP (error). When
these conditions are met the FPU will send a SDNXXX or
SPC pulse after receiving all of the operands from the CPU
and before executing the instruction, hence an early done
as compared to the General Slave Protocols.
4.1.2 Input Signals
CLK
DDIN
STO-ST3
1100- Reserved
1101- Transferring Operation Word or Oper·
and
1110- Reading Status Word
1111- Broadcasting Slave ID
In the case of the 16-bit Slave Protocol in which the CPU
always reads the slave status word, the FPU will force all
zeroes to be read. The CPU can then send the next instruction to the FPU saving the general protocol overhead. The
FPU will start the new instruction immediately after finishing
the previous instruction.
SFSR, CMPF and CMPL do not generate an Early Done.
Note: The NS32332 generates four status lines and the
NS32532 generates five. The user should connect the
status lines as shown below:
3.6.3 Floating-Point Protocols
Table 3-3 gives the protocols followed for each floatingpoint instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
section 2.2.3.
RST
NOE
The Operand Class columns give the Access Classes for
each general operand, defining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Reference Manual).
PSO. PS1
The Operand Issued columns show the sizes of the operands issued to the Floating-Point Unit by the CPU. "D" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, D = Double Word). "f" indicates that the instruction
specifies a floating-point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
NS32381
NS32332
NS32532
STO
STO
STO
ST1
ST1
ST1
ST2
ST2
ST2
ST3
ST3
ST4
Reset: Active low. Resets the last operation
and clears the FSR register.
New Opcode Enable: Active high. This signal
enables the new opcodes available in the
NS32381.
Protocol Select: Selects the slave protocol to
be used. PSO is the least significant and rightmost bit.
OO-Selects 16-bit protocol.
01-5elects 32-bit protocol for NS32332.
10-Reserved.
11-Selects 32-bit protocol for NS32532.
4.1.3 Output Signals
SDN332
Slave Done 332: Active low. This signal is for
use with the NS32332 CPU only. If held active
for a half clock cycle and released this pin indicates the successful completion by the FPU of
a floating-point instruction. Holding this pin active for two and a half clock cycles indicates
TRAP or that the CMPf instruction has been executed.
SDN532
Slave Done 532: Active low. This signal is for
use with the NS32532 CPU only. When active it
indicates successful completion by the FPU of
a floating-point instruction.
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the FPU Status Word (Figure 3-11 ).
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified, because the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance.
4.0 Device Specifications
FSSR
4.1 PIN DESCRIPTIONS
4.1.1 Supplies
The following is a brief description of all NS32381 pins.
Vee
Power: + 5V positive supply.
GND
Clock: TTL-level clock signal.
Data Direction In: Active low. Status signal indicating the direction of data transfers during a
bus cycle .
Status: Bus cycle status code from CPU. STO is
the least significant and rightmost bit.
Force Slave Status Read: Active low. This signal is for use with the NS32532 CPU only.
When active it indicates TRAP or that the CMPf
instruction has been executed.
4.1.4 Input/Output Signals
Ground: Ground reference for both on-chip logic and drivers connected to output pins.
*DO-D31
Data Bus: These are the 32 Signal lines which
carry data between the NS32381 and the CPU.
SPC
Slave Processor Control: Active low. This is the
data strobe Signal for slave transfers. For the
32-bit protocol, SPC is only an input signal.
'For the 16·bH Slave Protocol the upper sixteen data Input signals (016031) should be left floating.
3-100
z
tJ)
4.0 Device Specifications (Continued)
Co)
N
........co.
Co)
Connection Diagram
@@@@@@@@@
K@@@@@@@@@@@
J @ @
@@
H@ @
@@
G @@
@@
NS32381
F @@
@@
E@@
@@
D@@
@@
C @ @d
@@
B@@@@@@@@@@@
A @@@@@@@@@
1 2
3
4
5
6
7
8
CI1
......
Z
tJ)
Co)
N
Co)
....•
co
N
o
9 10 11
TL/EE/9157-1B
Bottom View
Order Number NS32381
See NS Package Number U68D
FIGURE 4-1. 68-Pin PGA Package
NS32381 Pinout Descriptions
Desc
Vee
01
00
PSl (Note 1)
GNO
GNO
CLK
RST
Reserved (Note 2)
Reserved (Note 2)
02
017
016
PSO (Note 1)
GNO
NOE(Note 1)
Reserved (Note 3)
Reserved (Note 2)
Vee
015
018
03
031
014
019
Vee
030
Vee
04
020
013
029
Reserved (Note 3)
05
Pin
Desc
A2
A3
028
GNO
GNO
021
012
027
06
022
011
SON332
07
023
SPC
SON532
A4
A5
A6
A7
A8
A9
Al0
81
82
83
84
85
86
87
88
89
810
811
Cl
C2
Cl0
Cll
01
02
010
011
El
E2
El0
Ell
Fl
F2
Vee
08
GNO
026
GNO
Vee
Reserved (Note 3)
STO
STl
Reserved (Note 3)
GNO
024
025
09
010
OOIN
Vee
ST2
ST3
FSSR
Note 1: eMOS input; never float.
Note 2: Pin should be grounded.
Note 3: Pin should be left floating.
3-101
Pin
FlO
Fll
Gl
G2
Gl0
Gll
Hl
H2
Hl0
Hll
Jl
J2
Jl0
Jll
Kl
K2
K3
K4
K5
K6
K7
K8
K9
Kl0
Kll
L2
L3
L4
L5
L6
L7
L8
L9
L10
~
co
C")
.....•
C'I
C")
(/)
z
....
In
.
.....
.....
co
C")
C'I
C")
(/)
z
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
Power Dissipation
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Down Mode
ESD Rating is to be determined .
Temperature Under Bias
Storage Temperature
All Input or Output Voltages
with Respect to GND
1.5W
0.15W
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
O'C to + 70'C
-65'Cto +150'C
-0.5Vto +7.0V
4.3 ELECTRICAL CHARACTERISTICS TA = O'C to 70'C, Vee = 5V ± 5%, GND = OV
Max
Units
High Level Input Voltage'
2.0
Vee +0.5
V
VIL
Low Level Input Voltage'
-0.5
0.8
V
Symbol
Parameter
VIH
Conditions
VOH
High Level Output Voltage
IOH = -400 p.A
Val
Low Level Output Voltage
IOl = 2mA
II
Input Load Current'
VIH
Min
Typ
2.4
V
0.4
V
-10.0
10.0
p.A
High Level Input Voltage
for PSO, PS1, NOE
3.5
Vee +0.5
V
Vil
Low Level Input Voltage
for PSO, PS 1, NOE
-0.5
1.5
V
II
Input Load Current
for PSO, PS 1, NOE
-100
100
p.A
Il
Leakage Current
(Output and I/O Pins
in TRI-STATE®/Input Mode)
0.4 ,,; VOUT ,,; 2.4V
-20.0
20.0
p.A
Icc
Active Supply Current
lOUT
25'C
300
mA
Icc
Power Down Current
lOUT
25'C
30
mA
pF
pF
=
=
0, TA
0, TA
=
=
CIN
Input Capacitance
6
10
COUT
Output Capacitance
8
12
'"Except PSO, PS1, NOE and Reserved pins.
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the Timing Specifications given in this section refer to
0.8V and 2.0V on all the input and output signals as illustrated in Figures 4.2 and 4.3, unless specifically stated otherwise.
ClK
[=:J
ABBREVIATIONS
L.E. - Leading Edge
R.E. -
Rising Edge
T.E. -
F.E. -
Falling Edge
ClK
2.0V
O.SV
SlG1
1'----
SlG1
SlG2
[
2.4V
tSIG11
O.SV
O.45V
SlG2
~
[ ___I__tS_IG_2_h.....J1,
___
Trailing Edge
[ ----:---'=1C
[
[
o.s\--
- - - - - - " ' - - - - - --2.4V
tSlG11
'----If---O.45V
L- - - f - - - 2 . 4 V
2.0V
tSIG2h
_ _ _ _ _...J.__ - - - - - -O.45V
TLlEE/9157-20
FIGURE 4-3. Timing Specification Standard
(Signal Valid before Clock Edge)
______ .::
TLlEE/9157-19
FIGURE 4-2. Timing Specification Standard
(Signal Valid after Clock Edge)
3-102
z
(J)
4.0 Device Specifications (Continued)
Co)
~
....co•
....
4.4.2 Timing Tables (Maximum times assume temperature range D'C to 7D'C)
4.4.2.1 Output Signal Propagation Delays for all CPUs
(Maximum times assume capacitive loading of 100 pF)
Symbol Figure
U\
.......
z
NS32381-15
Reference!
Description
Conditions
Min
en
NS32381-20
Max
Min
Units
Co)
Max
co
....
tSPCFw
4-18 SPC Pulse Width from FPU At 0.8V (Both Edges) %tcLKp - 10 % tCLKp + 10 % tcLKp - 10 %tCLKp + 10
ns
tSPCFa
4·18 SPC Output Active
After CLK R.E.
ns
tsPCFj
4-18 SPC Output Inactive
After CLK R.E.
tSPCFnl
4-18 SPC Output Nonforcing
After CLK F.E.
38
18
33
38
18
35
Co)
N
33
ns
30
ns
~
Q
4.4.2.2 Output Signal Propagation Delays for the NS32008, NS32016 and NS32032 CPUs
Maximum times assumes capacitive loading of 100 pF
Symbol
Figure
NS32381-15
Reference!
Description
Conditions
Max
Min
NS32381-2D
Min
Units
Max
tOy
4-8
Data Valid (00-015)
After SPC L.E.
30
ns
tOj
4-8
00-015 Floating
After SPC T.E.
30
ns
4.4.2.3 Output Signal Propagation Delays for the 32-811 Slave Protocol NS32332 CPU
Maximum times assume capacitive loading of 100 pF unless otherwise specified
Symbol Figure
Description
Conditions
tOy
4-10
D.:ItaValid
After SPC L.E.;
75 pF Cap. Loading
tOlv
4-10
Data Invalid
After SPC T.E.
tOni
4-10
Data Nonforcing
After SPC T.E.
tsONa
4-12,13 Slave Done Active
tsONh
Slave Done Hold
After CLK R.E.
tSON w
4-12
Slave Done
Pulse Width
AtO.8V
(Both Edges)
tSTRPw
Min
lB
3
Slave Done (TRAP)
Pulse Width
AtO.BV
(Both Edges)
Min
%tCLKp -l0
Units
Max
25
18
ns
30
ns
33
33
ns
33
ns
%tcLKp+l0
ns
30
ns
% tCLKp + 10
30
3
%tcLKp -l0
2%tcLKp -l0 2%tcLKp+l0 2112 tCLKp -10 2% tCLKp+ 10
3-103
ns
30
33
4-12,13 Slave Done Nonforcing After eLK R. E.
4-13
NS32381-2D
Max
30
After CLK F.E.
4-13
tSONn!
NS32381-15
Reference!
ns
&I
4.0 Device Specifications (Continued)
4.4.2.4 Output Signal Propagation Delays for the 32-Blt Slave Protocol NS32532 CPU
Maximum times assume capacitive loading of 75 pF
Symbol
Figure
Description
NS32381-
Reference!
Conditions
15
Min
tOy
4-14
Data Valid
to ly
4-14
Data Invalid
After ClK R.E.
tOn!
4-14
Data Nonforcing
After SPC T.E.
tsoa
4-16
Slave Done Active
After ClK R.E.
tSOh
4-16
Slave Done Hold
After ClK R.E.
tSOn!
4-16
Slave Done Nonforcing
After ClK R. E.
tFSSRa
4-17
Forced Slave Status
Read Active
After ClK R.E.
tFSSRh
4-17
Forced Slave Status
Read Hold
After ClK R.E.
tFSSR n!
4-17
Forced Slave Status
Read Nonforcing
After ClK R.E.
20
Max
After SPC L.E.
Min
25
Max
30
Min
40
25
30
25
2
33
25
ns
ns
30
35
2
Max
3
3
30
38
Min
Units
25
3
30
2
Max
25
3
30
2
ns
25
ns
25
ns
35
30
30
30
ns
40
35
25
25
ns
25
ns
30
ns
2
38
2
33
35
2
25
2
30
30
4.4.2.5 Input Signal Requirements with all CPUs
Symbol
Figure
NS32381-
Reference!
Conditions
Description
15
Min
20
Max
Min
30
25
Max
Min
Max
Min
Units
Max
tpWR
4-5
Power-On Reset Duration
After ClK R.E.
30
30
30
30
,...s
tRSTw
4-6
Reset Pulse Width
At 0.8V (Both Edges)
64
64
64
64
tCLKp
tRSTs
4-7
Reset Release
Before ClK F.E.
10
10
10
10
ns
tRSTh
4-7
Reset Hold
After ClK R.E.
0
0
0
0
ns
4.4.2.6 Input Signal Requirements with the NS32008, NS32016, NS32032 CPUs
Symbol
Figure
Description
Reference!
NS32381-15
Conditions
Min
Max
NS32381-20
Min
Units
Max
tss
4-8
Status (STO-ST1) Setup
Before SPC L.E.
25
20
ns
tSh
4-8
Status (STO-ST1) Hold
After SPC L.E.
20
20
ns
tos
4-9
Data Setup (DO-D15)
Before SPC T.E.
25
20
ns
tOh
4-9
Data Hold (DO-D15)
After SPC T.E.
20
20
ns
tspCw
4-8
SPC Pulse Width
from CPU
AtO.8V
(Both Edges)
35
35
ns
3-104
Z
tn
w
4.0 Device Specifications (Continued)
N
W
4.4.2.7 Input Signal Requirements with the 32·Bit Slave Protocol NS32332 CPU
Symbol
Figure
NS32381·15
Reference!
Description
Conditions
Min
NS32381·20
Max
Min
Units
co
.....
•
.....
U1
.......
Z
Max
tSTs
4-11
Status Setup
Before SPC L.E.
25
20
ns
tSTh
4-11
Status Hold
After SPC L.E.
20
20
ns
tos
4-11
Data Setup
Before SPC T.E.
25
20
ns
tOh
4-11
Data Hold
After SPC T.E.
20
20
ns
tspcw
4-11
SPC Pulse Width
At O.BV (Both Edges)
35
35
ns
(J)
W
N
W
co
.....
•
N
C
4.4.2.8 Input Signal Requirements with the 32·Bit Slave Protocol NS32532 CPU
NS32381
Symbol
Figure
Reference!
Conditions
Description
15
Min
Max
20
Min
25
Max
Min
30
Max
Units
Max
Min
tSTs
4-15
Status Setup
Before ClK (T2) R.E.
25
25
20
15
ns
tSTh
4-15
Status Hold
After ClK (T2) R.E.
25
20
10
10
ns
tOOINs
4-15
Data Direction in Setup
Before SPC L.E.
0
0
0
0
ns
tOOINh
4-15
Data Direction In Hold
After SPC T.E.
10
10
10
10
ns
tDs
4-15
Data Setup
Before SPC T.E.
10
6
6
6
ns
tDh
4-15
Data Hold
After SPC T.E.
20
20
10
10
ns
tspcs
4-15
SPCSetup
Before ClK (T2) R.E.
20
20
20
20
ns
tSPCh
4-15
SPCHold
After ClK (T2) R.E.
0
0
0
0
ns
tSPCia
4-14
SPC Inactive
After ClK (Tl) R.E.
0
0
ns
tSPca
4-14
SPCActive
After ClK (Tl) R.E.
3
3
ns
4.4.2.9 Clocking Requirements with all CPUs
NS32381
Symbol
Figure
Description
Reference!
Conditions
15
20
25
30
Units
Min
Max
Min
Max
Min
Max
Min
Max
tCLKh
4-4
Clock High Time
At 2.0 V (Both Edges)
25
1000
20
1000
lB
1000
16
1000
ns
tCLKI
4-4
Clock low Time
At O.BV (Both Edges)
25
DC
20
DC
18
DC
16
DC
ns
tCTr
4-4
Clock Rise Time
Between O.BV and 2.0V
3
ns
tCTd
4-4
Clock Fall Time
Between 2.0V and O.BV
3
ns
tCLKp
4-4
Clock Period
ClK R.E. to Next ClK R.E.
DC
ns
5
7
7
3-105
66
DC
4
5
50
DC
4
40
DC
33.3
•
CI
~
....
~
C'i
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
('I)
(J)
Z
;:n
....
....•
CIO
eLK
('I)
C'i
('I)
(/)
Tl/EE/9157 -21
Z
FIGURE 4-4. Clock Timing
vee
-I
Tl/EE/9157-22
FIGURE 4-5. Power-On Reset
Tl/EE/9157 -23
FIGURE 4-6. Non-Power-On Reset
CLK--.J
ill
I
r
--.Y--t
tRSTh
RST•
,----..
TLlEE/9157-24
FIGURE 4-7. RST Release Timing
Note: The rising edge of RST must occur while elK is high, as shown.
CLK
STO, STI
SPC
-_
.....
?ll1.
VALID
xzmmv
rts'1~tSh4
_
tsPCw--j,('"""
tev4 -l-tOf:j
00-015
-----------<
VALID FROM FPU )-TLlEE/9157-25
FIGURE 4-8. Read Cycle from FPU (NS32008, NS32016, NS32032 CPUs)
3-106
z
4.0 Device Specifications (Continued)
en
Co)
ClK _ _ _....
co
......
N
.
Co)
......
(II
STO, 5T1
?llX
......
z
XllIlllW
VALID
en
Co)
j-tss-j j-tsh-l
5PC ----ctspcw--lIiL
r---- to. --I
DO-D1S--ZI""lZ"""V""Z""ZX""
VALID FROM CPU
N
Co)
co
......
•
N
o
tOh::j
~
TL/EE/9157 -26
FIGURE 4-9. Write Cycle to FPU (NS3200B, NS32016, NS32032 CPUS)
r--
11
------"'·+1'- T4 - - - j
ClK [
5TO-513
[ZZZZ77ZZZX"'-----JXZVZ7IZ/I/ll
~[
Hf~, pmm_m_m
DO_D3{ _ _ _ _ _ _ _ _ _tDv
__
TLlEE/9157 -27
FIGURE 4·10. Read Cycle from FPU (NS32332 CPU)
r--
11
D O - D 3 { - - - - - - - - - - - < 1 DATA VALID
T4---j
~--------TLlEE/9157-28
FIGURE 4-11. Write Cycle to FPU (NS32332 CPU)
3-107
.
....~co
4.0 Device Specifications (Continued)
C')
N
C')
ClK [
t/)
Z
......
II)
....
....•
_[-----~~!~~-lt:t~.o~~ _____ _
SDN332
co
C')
N
~
IsONw
Z
TUEE/9157 -29
FIGURE 4-12. SDN332 Timing (NS32332 CPU)
ClK [
tSONa-li:
SON332 [----------
~________
,...-
t STRpw
TLlEE/9157-30
FIGURE 4-13. SDN332 (TRAP) Timing (NS32332 CPU)
00- 031
[----------~l'----O-A-TA-V-A-Ll-D
_ _"""'I _ _ _.1.0
TL/EE/9157-31
FIGURE 4-14. Read Cycle from FPU (NS32532 CPU)
3-108
z
en
CAl
4.0 Device Specifications (Continued)
N
CAl
CD
r-- T1 ------<·+I·-T2 -----j
ClK[
f
STO-ST3[·-,-0'7"""'7""//~!I~O"""""!
.....
.....•
C7I
......
z
en
CAl
tSTS-j .J..!h
X/,....,....O,.....,....O.,.....,...77~O~O..,.....-y7
N
CAl
CD
.....
N•
o
I
SPC [
DO-D31[--------------------~~---DA-~--VA-L1-D--~~--------------TL/EE/9157-32
FIGURE 4·15. Write Cycle to FPU (NS32532 CPU)
TL/EE/9157 -33
FIGURE 4·16. SDN532 Timing (NS32532 CPU)
ClK [
tFSSRa--i {
[
rSSR
1:"'''
----1'
--;
--I ~_~':!mm
TL/EE/9157-34
FIGURE 4·17. FSSR Timing (NS32532 CPU)
\sPCra I
,
"1
,\sPCFla
ClK
TL/EE/9157 -35
FIGURE 4·18. SPC Pulse from FPU
3-109
C) r---------------------------------------------------------------------------------~
~
i
N
CO)
(I)
z
iii
....
....•
CD
CO)
N
~
Z
Appendix A
NS32381 PERFORMANCE ANALYSIS
NS32381 PERFORMANCE ANALYSIS
The following performance numbers were taken from simulations using the 381 SIMPLE model. The timing terms have
been designed to provide performance numbers which are
CPU independent. Numbers were obtained from SIMPLE
simulations, taking the average execution times using 'typical' operands.
The following instructions do not generate an early done. In
this case, EXT is the time from the last data sent to the FPU,
until the normal DONE is issued. (FPU Pipe is empty)
Instruction
SFSR
Listed below are definitions of the timing terms:
EXT -
EDD -
Provided that the CPU can transfer the ID/OPCODE and
any operands to the FPU during the EDD time, the average
system execution time for an instruction (keeping the FPU
pipe filled) is: EXT + EDD.
The system execution time for a single FPU instruction with
FPU register destination and early done is: EXT plus the
protocol time. (FPU pipe is initially empty)
Instruction
EXT
EDD
Total
any, reg
5
8
13
MOVF any, reg
MOVL any, reg
5
5
6
8
11
13
50
LFSR
MOVif any, reg
5
45
MOVFL any, reg
9
6
15
ADDF
ADDL
any, reg
any, reg
11
11
31
31
42
42
SUBF
SUBL
any, reg
any, reg
11
11
31
31
42
42
MULF any, reg
MULL any, reg
11
11
20
27
31
38
DIVF
DIVL
any, reg
any, reg
11
11
45
59
56
70
POLYF any, any
POLYL any, any
15
15
46
53
61
68
DOTF any,any
DOTL any, any
15
15
46
53
61
68
7
any,any
18
ROUNDfi any, mem
FLOORfi any, mem
TRUNCfi any, mem
46
46
46
CMPF
CMPL
any,any
anY,any
17
ABSf
NEGf
anY,any
any,any
9
9
SCALBf
any,any
49
LOGBf
any,any
36
MOVLF
(EXecution Time) This is the time from the last data
sent to the FPU, until the early DONE is issued.
(FPU Pipe is empty)
(Early Done Delta) This is the time from when the
early DONE is issued until the execution of the next
instruction may start.
3-110
EXT
reg,mem
17
z
en
w
~National
I\)
Q
~ Semiconductor
Q)
.....
.....•
Q
Z
'"en
NS32081-10/NS32081-15 Floating-Point Units
General Description
Features
The NS320B1 Floating-Point Unit functions as a slave processor in National Semiconductor's Series 32000® microprocessor family. It provides a high-speed floating-point instruction set for any Series 32000 family CPU, while remaining architecturally consistent with the full two-address architecture and powerful addressing modes of the Series 32000
micro-processor family.
III Eight on-chip data registers
III
III
III
III
III
III
w
I\)
Q
Q)
.
.....
.....
32-bit and 64-bit operations
Supports proposed IEEE standard for binary floatingpoint arithmetic, Task P754
Directly compatible with NS32016, NS3200B and
NS32032 CPUs
High-speed XMOSTM technology
Single 5V supply
24-pin dual in-line package
U1
Block Diagram
r
I
I
I
~
-
ExEcUTION UNjj"I
I
I
I
~
•
INTERFACE ANoi
STORAGE UNIT
I
16
I
L ___________ _
C.ntrot Bus
TL/EE/5234-1
3-111
~r-------------------------------------------------------------------~
.....
•
.....
Table of Contents
co
Q
N
~
Z
;:;
.....
•
.....
co
Q
N
~
Z
1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.4 Bus Operation
1.1 Operand Formats
1.1.1 Normalized Numbers
3.4.1 Bus Cycles
1.1.2 Zero
3.4.2 Operand Transfer Sequences
1.1.3 Reserved Operands
3.5 Instruction Protocols
1.1.4 Integers
3.5.1 General Protocol Sequence
1.1.5 Memory Representations
3.5.2 Floating-Point Protocols
2.0 ARCHITECTURAL DESCRIPTION
4.0 DEVICE SPECIFICATIONS
2.1 Programming Model
4.1 Pin Descriptions
2.1.1 Floating-Point Registers
4.1.1 Supplies
2.1.2 Floating-Point Status Register (FSR)
4.1.2 Input Signals
2.1.2.1 FSR Mode Control Fields
4.1.3 Input/Output Signals
2.1.2.2 FSR Status Fields
4.2 Absolute Maximum Ratings
2.1.2.3 FSR Software Field (SWF)
4.3 Electrical Characteristics
2.2 Instruction Set
4.4 Switching Characteristics
2.2.1 General Instruction Format
4.4.1 Definitions
2.2.2 Addressing Modes
4.4.2 Timing Tables
2.2.3 Floating-Point Instruction Set
4.4.2.1 Output Signals: Internal Propagation Delays
2.3 Traps
4.4.2.2 Input Signals Requirements
3.0 FUNCTIONAL DESCRIPTION
4.4.2.3 Clocking Requirements
3.1 Power and Grounding
4.4.3 Timing Diagrams
3.2 Clocking
3.3 Resetting
3-112
z
en
Co)
List of Illustrations
Floating-Point Operand Formats
Register Set ..
The Floating-Point Status Register
General Instruction Format
Index Byte Format
Displacement Encodings
Floating-Point Instruction Formats
Recommended Supply Connections
Power-On Reset Requirements
General Reset Timing
System Connection Diagram
Slave Processor Read Cycle
Slave Processor Write Cycle
FPU Protocol Status Word Format.
Dual-In-Line Package
Timing Specification Standard (Signal Valid After Clock Edge)
Timing Specification Standard (Signal Valid Before Clock Edge)
Clock Timing
Power-an-Reset
Non-Power-On-Reset.
Read Cycle From FPU
Write Cycle To FPU
SPC Pulse from FPU
RST Release Timing
0
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04-7
.4-8
04-9
. . 4-1 0
List of Tables
Sample F Fields
Sample E Fields
Normalized Number Ranges
Series
Family Addressing Modes
General Instruction Protocol
Floating-Point Instruction Protocols
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1.0 Product Introduction
TABLE 1·2. Sample E Fields
The NS32081 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed XMOS technology. It operates as a slave processor for transparent expansion of the Series 32000 CPU's basic instruction set. The
FPU can also be used with other microprocessors as a peripheral device by using additional TTL interface logiC. The
NS32081 is compatible with the IEEE Floating-Point Formats by means of its hardware and software features.
E Field
F Field
Represented Value
011 ... 110
100 ... 0
1.5x2- 1 =0.75
011 ... 111
100 ... 0
1.5 x 20 = 1.50
100 ... 000
100 ... 0
1.5X21 =3.00
Two values of the E field are not exponents. 11 ... 11 signals a reserved operand (Section 2.1.3). 00 ... 00 represents the number zero if the F field is also ali zeroes, otherwise it signals a reserved operand.
1.1 OPERAND FORMATS
The S bit indicates the sign of the operand. It is 0 for positive and 1 for negative. Floating-point numbers are in signmagnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
The NS32081 FPU operates on two floating-point data
types-single precision (32 bits) and double preCision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single preCision data type, and the
suffix L (Long Floating) to select the double preCision data
type.
1.1.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither ali zeroes nor ali ones.
The value of a Normalized number can be derived by the
formula:
(-1)8 X 2(E-Bias) X (1 + F)
A floating-point number is divided into three fields, as shown
in Figure 1-1.
The F field is the fractional portion of the represented number. In Normalized numbers (Section 1.1.1), the binary point
is assumed to be immediately to the left of the most significant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
1.0 ,;:; x ,;:; 2.0.
The range of Normalized numbers is given in Table 1-3.
1.1.2 Zero
There are two representations for zero-positive and negative. Positive zero has ali-zero F and E fields, and the S bit is
zero. Negative zero also has ali-zero F and E fields, but its S
bit is one.
TABLE 1·1. Sample F Fields
FField
000 ... 0
010 ... 0
100 ... 0
110 ... 0
Binary Value
1.000 ... 0
1.010 ... 0
1.100 ... 0
1.110 ... 0
DeCimal Value
1.000 ... 0
1.250 ... 0
1.500 ... 0
1.750 ... 0
1.1.3 Reserved Operands
The proposed IEEE Standard for Binary Floating-Point Arithmetic (Task P754) provides for certain exceptional forms of
floating-point operands. The NS32081 FPU treats these
forms as reserved operands. The reserved operands are:
t
Implied Bit
• Positive and negative infinity
• Not-a-Number (NaN) values
The E field contains an unsigned number that gives the binary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be subtracted from the E field value in order to obtain the true
exponent. The bias value is 011 .•. 112, which is either 127
(Single preCision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
• Denormalized numbers
Both Infinity and NaN values have ali ones in their E fields.
Denormalized numbers have ali zeroes in their E fields and
non-zero values in their F fields.
The NS32081 FPU causes an Invalid Operation trap (Section 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.
Single Precision
31 30
Is I
o
2322
E
F
8
23
Double Precision
6362
lsi
o
52 51
E
F
11
52
FIGURE 1·1. Floating·Point Operand Formats
3-114
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1.0 Product Introduction (Continued)
N
o
TABLE 1-3. Normalized Number Ranges
Single Precision
2127 X(2-2-23)
= 3.40282346 x 1038
Double Precision
21023X(2-2-52)
= 1.7976931348623157X 10308
Least Positive
2- 126
= 1.17549436X 10- 38
2- 1022
= 2.2250738585072014 x 10- 308
Least Negative
-(2- 126)
= -1.17549436X 10-38
-(2- 1022)
= -2.2250738585072014X 10- 308
Most Negative
-2127X(2-2-23)
= -3.40282346 X 1038
-21023X(2-2-52)
= -1.7976931348623157X10 308
Most Positive
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Note: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
1.1.4 Integers
In addition to performing floating-point arithmetic, the
NS32081 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generated by the FPU as two's complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.
2.1.1 Floating-Point Registers
There are eight registers (FO-F7) on the NS32081 FPU for
providing high-speed access to floating-point operands.
Each is 32 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register addressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (i.e., integer operands) refer
to the General Purpose Registers (RO-R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
When the Register addressing mode is specified for a double precision (64-bit) operand, a pair of registers holds the
operand. The programmer must specify the even register of
the pair. The even register contains the least significant half
of the operand and the next consecutive register contains
the most significant half.
1.1.5 Memory Representations
The NS32081 FPU does not directly access memory. However, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.
In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the instruction format) with the most significant byte at the lowest
address.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating·point operation. Figure 2-2
shows the format of the FSR.
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes nine registers that
are implemented on the NS32081 Floating-Point Unit (FPU).
TL/EE/5234-5
FIGURE 2-2. The Floating-Point Status Register
DEDICATED
FSR
DATA
4-----32-
2.1.2.1 FSR Mode Control Fields
FD::!===~
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given below.
Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded whenever they cannot be exactly represented. The rounding
modes are:
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly halfway between the two nearest values the even value
(LSB = 0) is returned.
F1~!===~
F2!:====~
F3~!====!
F4~!====!
F5:=!===~
F6~!====!
F7 ...
! ___---'
01 Round toward zero. The nearest value which is closer to
zero or equal to the exact result is returned.
TL/EE/5234-4
FIGURE 2-1. Register Set
3-115
•
2.0 Architectural Description (Continued)
100 Illegal Instruction. Two undefined floating-point instruction forms are detected by the FPU as being illegal. The
binary formats causing this trap are:
10 Round toward positive infinity. The nearest value which
is greater than or equal to the exact result is returned.
11 Round toward negative infinity. The nearest value which
is less than or equal to the exact result is returned.
~001lxxl0lllll0
xxxxxxxxxxl00lxxl0lllll0
Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in absolute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.
101 Invalid Operation. One of the floating-point operands of
a floating-point instruction is a Reserved operand, or an
attempt has been made to divide zero by zero using the
DIVf instruction.
Inexact Result Trap Enable (lEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.
110 Inexact Result. The result (either lIoating-point or integer) of a floating-point instruction cannot be represented exactly in the format of the destination operand, and
a rounding step must alter it to fit. This condition is always reported in the TT field and IF bit unless any other
exceptional condition has occurred in the same instruction. In this case, the TT field always contains the code
for the other exception and the IF bit is not altered. A
trap is caused by this condition only if the lEN bit is set;
otherwise the result is rounded and delivered, and no
trap occurs.
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions encountered during floating-point data processing. The meanings of the FSR status bits are given below:
Trap Type (TT): bits 0-2. This 3-bit field records any exceptional condition detected by a floating-point instruction. The
TT field is loaded with zero whenever any floating-point instruction except LFSR or SFSR completes without encountering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the Load FSR
(LFSR) instruction. Underflow and Inexact Result are always
reported in the TT field, regardless of the settings of the
UEN and lEN bits.
111 (Reserved for future use.)
Underflow Flag (UF): Bit 4. This bit is set by the FPU whenever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.
000 No exceptional condition occurred.
001 Underflow. A non-zero floating-point result is too small
in magnitude to be represented as a normalized lIoating-point number in the format of the destination operand. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set. If
the UEN bit is not set, a result of Positive Zero is produced, and no trap occurs.
2.1.2.3 FSR Software Field (SWF)
Bits 9-15 of the FSR hold and display any information written to them (using the LFSR and SFSR instructions), but are
not otherwise used by FPU hardware. They are reserved for
use with NSC lIoating-point extension software.
010 Overflow. A result (either floating-point or integer) of a
floating-point instruction is too great in magnitude to be
held in the format of the destination operand. Note that
rounding, as well as calculations, can cause this condition.
2.2 INSTRUCTION SET
2.2.1 General Instruction Format
011 Divide by zero. An attempt has been made to divide a
non-zero floating-point number by zero. Dividing zero by
zero is considered an Invalid Operation instead (below).
Figure 2-3 shows the general format of an Series 32000
instruction. The Basic Instruction is one to three bytes long
OPllONAL
EXTENSIONS
BASIC
INSTRUCTION
r~-------------------~'--------------------\(~--------_J'----------\
DISP2 DISPI DISP21DISPI
IMPUED
IMMEDlIm:
OPERAND(S)
DISP
DISP
IMM
IMM
INDEX
BYrE
INDEX
BYrE
~
t
GEN
ADDR
MODE
A
GEN
AODR
MODE
B
oPCODE
j
TLlEE/5234-6
FIGURE 2-3. General Instruction Format
3-116
r--------------------------------------------------------------------------, Z
2.0 Architectural Description
en
Co)
(Continued)
and contains the opcode and up to two 5-bit General Addressing Mode (Gen) fields. Following the Basic Instruction
field is a set of optional extensions, which may appear depending on the instruction and the addressing modes selected.
The only form of extension issued to the NS320B1 FPU is
an Immediate operand. Other extensions are used only by
the CPU to reference memory operands needed by the
FPU.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-4.
N
C
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated CPU
registers PC, SP, SB or FP. These registers point to data
areas generally needed by high-level languages.
....•
....
C
Memory Relative: A pOinter variable is found within the
memory space pointed to by the CPU SP, SB or FP register.
A displacement is added to that pointer to generate the Effective Address of the operand.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written. Floating-point operands as well as integer operands
may be specified using Immediate mode.
en
Q)
......
z
Co)
N
C
....•
....
en
Q)
Absolute: The address of the operand is specified by a
Displacement field in the instruction.
External: A pOinter value is read from a specified entry of
the current Link Table. To this pOinter value is added a displacement, yielding the Effective Address of the operand.
Top of Stack: The currently-selected CPU Stack Pointer
(SPO or SP1) specifies the location of the operand. The operand is p~shed or popped, depending on whether it is written or read.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-5, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most significant byte first.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode ex·
cept Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or B and adding it into the
total, yielding the final Effective Address of the operand.
Some non-FPU instructions require additional, "implied" immediates and I or displacements, apart from those associated with addressing modes. Any such extensions appear at
the end of the instruction, in the order that they appear within the list of operands in the instruction definition.
The following table, Table 2-1, is a brief summary of the
addressing modes. For a complete description of their actions, see the Series 32000 Instruction Set Reference Manual.
2.2.2 Addressing Modes
The Series 32000 Family CPUs generally access an operand by calculating its Effective Address based on information available when the operand is to be accessed. The
method to be used in performing this calculation is specified
by the programmer as an "addressing mode."
Addressing modes in the Series 32000 family are designed
to optimally support high-level language accesses to variables. In nearly all cases, a variable access requires only
one addressing mode within the instruction which acts upon
that variable. Extraneous data movement is therefore minimized.
o
SIGNED DISPLACEMENT
&I
Series 32000 Addressing Modes fall into nine basic types:
Register: In floating-point instructions, these addressing
modes refer to a Floating-Point Register (FO-F7) if the operand is of a floating-point type. Otherwise, a CPU General
Purpose Register (RO-R7) is referenced. See Section 2.1.1.
7
1
0
~
1
I
..\'U,,~t.
Register Relative: A CPU General Purpose Register contains an address to which is added a displacement value
from the instruction, yielding the Effective Address of the
operand in memory.
t.\"Y\J.t~IA~"'"
TL/EE/5234-10
FIGURE 2·5. Displacement Encodlngs
7
GEN. ADDR. MODE
TL/EE/5234-7
FIGURE 2·4. Index Byte Format
3-117
.... r-----------------------------------------------------------------------------,
~
;
2.0 Architectural Description
CI
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(Continued)
TABLE 2·1. Series 32000 Family Addressing Modes
C'i
Encoding
Mode
Assembler Syntax
Effective Address
REGISTER
00000
00001
00010
00011
00100
00101
00110
00111
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO orFO
R1 or F1
R20rF2
R30rF3
R4 or F4
R5 or F5
R60rF6
R7 or F7
None: Operand is in the specified register.
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
·+disp
Disp + Register; "SP" is either
SPO or SP1 , as selected in PSR.
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP»
disp2(disp1 (SP»
disp2(disp1 (SB»
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP" is
either SPO or SP1, as selected in PSR.
Immediate
value
None: Operand is issued from
CPU instruction queue.
Absolute
@disp
Disp.
External
EXT (disp1) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Top of Stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
Mode + Rn.
Mode + 2 X Rn.
Mode + 4 X Rn.
Mode + 8 X Rn.
"Mode" and "n" are contained
within the Index Byte.
10011
(Reserved for Future Use)
REGISTER RELATIVE
01000
01001
01010
01011
01100
01101
01110
01111
MEMORY SPACE
11000
11001
11010
11011
MEMORY RELATIVE
10000
10001
10010
IMMEDIATE
10100
ABSOLUTE
10101
EXTERNAL
10110
TOP OF STACK
10111
SCALED INDEX
3-118
~
2.0 Architectural Description (Continued)
Co)
N
o
2.2.3 Floating-Point Instruction Set
Movement and Conversion
The NS32081 FPU instructions occupy formats 9 and 11 of
the Series 32000 Family instruction set (Figure 2-6). A list
of all Series 32000 family instruction formats is found in the
applicable CPU data sheet.
The following instructions move the gen1 operand to the
gen2 operand, leaving the gen1 operand intact.
Format Op
Instruction
11
0001 MOVf
gen1, gen2
Certain notations in the following instruction description tables serve to relate the assembly language form of each
instruction to its binary format in Figure 2-6.
9
010 MOVLF
gen1, gen2
Format 9
23
I,
ii I
.
gen1
I I
I
I I
gen2
op
II I II
i
I I I i I I
0 0 1 1 1 1 1 0
OPERATION WORD
I
9
011
9
Move, converting
from single
precision to
double
precision.
000 MOVif
gen1,gen2
Move, converting
from any integer
type to any
floating-point
type.
9
100 ROUNDfi
gen1, gen2
Move, converting
from floatingpaint to the
nearest integer.
9
101 TRUNCfi
gen1, gen2
Move, converting
from floatingpoint to the
nearest integer
closer to zero.
9
111 FLOORfi
gen1, gen2
Move, converting
from floatingpoint to the
largest integer
less than or
equal to its
value.
TL/EE/5234-11
23
I
I I
I
op
ganl
OPERATION WORD
10 BYTE
TL/EE/5234-12
FIGURE 2-6. Floating-Point Instruction Formats
The Format column indicates which of the two formats in
Figure 2-6 represents each instruction.
The Op column indicates the binary pattern for the field
called "op" in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case. with one or more suffixes (i or f) indicating data types, followed by a list of operands (gen1, gen2).
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This chOice affects the binary pattern in
the i field of the corresponding instruction format (Figure2-6)
as follows:
Suffix i
B
W
D
Data Type
Byte
Word
Double Word
iField
00
01
11
Move, converting
from double
precision to
single precision.
gen1,gen2
MOVFL
10 BYTE
Format 11
I. I
Description
Move without
conversion
Note: The MOVLF instruction' bit must be 1 and the i field must be 10.
The MOVFL instruction' bit must be 0 and the i field must be 11.
Arithmetic Operations
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format (Figure 2-6)
as follows:
Suffix f
F
L
Data Type
Single Precision
Double Precision (Long)
The following instructions perform floating-point arithmetic
operations on the gen1 and gen2 operands, leaving the result in the gen2 operand.
f Bit
1
o
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the binary pattern in the corresponding gen1 or gen2 field of the
instruction format (Figure 2-6). Refer to Table 2-1 for the
options available and their patterns.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
3-119
Format
11
11
Op
0000
0100
Instruction
ADDf gen1,gen2
SUBf gen1. gen2
11
1100
MUll
gen1. gen2
11
1000
DIVf
gen1, gen2
11
0101
NEGf
gen1,gen2
11
1101
ASSf
gen1.gen2
Description
Add gen1 to gen2.
Subtract gen1
fromgen2.
Multiply gen2 by
gen1.
Divide gen2 by
gen1.
Move negative of
gen1 to gen2.
Move absolute
value of gen1 to
gen2.
co
.....
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Z
~
N
o
co
.....
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CI1
•
....• r---------------------------------------------------------------------------------,
.... 2.0 Architectural Description (Continued)
U)
~
('II
CO)
en
z
Ci
....
•
....
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~
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en
z
Comparison
3.2 CLOCKING
The NS32081 FPU requires a single-phase TTL clock input
on its CLK pin (pin 14). When the FPU is connected to a
Series 32000 CPU, the CLK signal is provided from the
CTTL pin of the NS32201 Timing Control Unit.
The Compare instruction compares two floating-point values, sending the result to the CPU PSR Z and N bits for use
as condition codes. See Figure 3-7. The Z bit is set if the
genl and gen2 operands are equal; it is cleared otherwise.
The N bit is set if the gen 1 operand is greater than the gen2
operand; it is cleared otherwise. The CPU PSR L bit is unconditionally cleared. Positive and negative zero are considered equal.
Format
11
Op
0010
Instruction
CMPf genl, gen2
3.3 RESETTING
The RST pin serves as a reset for on-chip logic. The FPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPU terminates instruction processing, resets its internal logic, and
clears the FSR to all zeroes.
On application of power, RST must be held low for at least
50 p.s aiter Vee is stable. This ensures that all on-chip voltages are completely stable before operation. See Figures 3-2
and 3-3.
Description
Compare genl
to gen2.
Floating-Point Status Register Access
The following instructions load and store the FSR as a 32bit integer.
Vee 4.5V
Format
9
9
Op
001
110
Instruction
LFSR
genl
SFSR
gen2
Description
LoadFSR
StoreFSR
J1JL
ClK
2.3 TRAPS
r---
I.
Upon detecting an exceptional condition in executing a
floating-point instruction, the NS32081 FPU requests a trap
by setting the Q bit of the status word transferred during the
slave protocol (Section 3.5). The CPU responds by performing a trap using a default vector value of 3. See the Series
32000 Instruction Set Reference Manual and the applicable
CPU data sheet for trap service details.
1m'
....---->:50~s-----t
TLIEEI5234-14
FIGURE 3-2. Power-On Reset Requirements
A trapped floating-point instruction returns no result, and
does not affect the CPU Processor Status Register (PSR).
The FPU displays the reason for the trap in the Trap Type
(TTl field of the FSR (Section 2.1.2.2).
CLK
JlJLfLSLfl
>:64 ClOCK----...I
_
- - -..-:ft'I'I'~'!i
I
CYCLES
I
RST
3.0 Functional Description
II
TUEEI5234-15
3.1 POWER AND GROUNDING
The NS32081 requires a Single 5V power supply, applied on
pin 24 (Vecl. See DC Electrical Characteristics table.
Grounding connections are made on two pins. Logic Ground
(GNDL, pin 12) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 13) is the common pin for the
output drivers. For optimal noise immunity, it is recommended that GNDL be attached through a single conductor directly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 3-1).
FIGURE 3-3. General Reset Timing
3.4 BUS OPERATION
Instructions and operands are passed to the NS32081 FPU
with slave processor bus cycles. Each bus cycle transfers
either one byte (8 bits) or one word (16 bits) to or from the
FPU. During all bus cycles, the SPC line is driven by the
CPU as an active low data strobe, and the FPU monitors
10kD.~
SPC
SPC
.... 1S-BIT ...
D 0-15
AID 0-15
..... DATA BUS'"
SERIES
STO
STO NS32081
32000 STO
ST1
STI
rpu
CPU
STI
RST
RST
+5V
SPC
Vee 24
Jr
NS32D81
FPU
12
>:64
CLOCK={
CYCLES
_
13
OTHER
GNDl
GNDB ...-....-1P'--+GROUND
_______
'::'
CONNECTIONS
RST
ClK
CTTL
NS32201
TCU
TLIEEI5234-13
TLIEEI5234-2
FIGURE 3-4. System Connection Diagram
FIGURE 3-1. Recommended Supply Connections
3-120
ztJ)
3.0 Functional Description
Co)
~
(Continued)
pins STO and ST1 to keep track of the sequence (protocol)
established for the instruction being executed. This is necessary in a virtual memory environment, allowing the FPU to
retry an aborted instruction.
A bus cycle is initiated by the CPU, which asserts the proper
status on STO and ST1 and pulses SPC low. STO and ST1
are sampled by the FPU on the leading (falling) edge of the
SPC pulse. If the transfer is from the FPU (a slave processor
read cycle), the FPU asserts data on the data bus for the
duration of the SPC pulse. If the transfer is to the FPU (a
slave processor write cycle), the FPU latches data from the
data bus on the trailing (rising) edge of the SPC pulse. Figures 3-5 and 3-6 illustrate these sequences.
The direction of the transfer and the role of the bidirectional
SPC line are determined by the instruction protocol being
performed. SPC is always driven by the CPU during slave
processor bus cycles. Protocol sequences for each instruction are given in Section 3.5.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word
of the instruction.
Upon receiving a Slave Processor instruction, the CPU initiates the sequence outlined in Table 3-2. While applying
Status Code 11 (Broadcast 10. Table 3-1), the CPU transfers the 10 Byte on the least significant half of the Oata Bus
(00-07). All Slave Processors input this byte and decode it.
The Slave Processor selected by the 10 Byte is activated,
and from this point the CPU is communicating only with it. If
any other slave protocol was in progress (e.g., an aborted
Slave instruction), this transfer cancels it.
The CPU next sends the Operation Word while applying
Status Code 01 (Transfer Slave Operand, Table 3-1). Upon
receiving it, the FPU decodes it, and at this point both the
CPU and the FPU are aware of the number of operands to
be transferred and their sizes. The Operation Word is
swapped on the Oata Bus; that is, bits 0-7 appear on pins
08-015, and bits 8-15 appear on pins 00-07.
3.4.2 Operand Transfer Sequences
An operand is transferred in one or more bus cycles. A 1byte operand is transferred on the least significant byte of
the data bus (00- 07). A 2-byte operand is transferred on
the entire bus. A 4-byte or 8-byte operand is transferred in
consecutive bus cycles, least significant word first.
SPC
CD
3.5.1 General Protocol Sequence
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an 10 byte followed by an Operation Word. See Section 2.2.3 for FPU instruction encodings. The 10 Byte has three functions:
1) It identifies the instruction to the CPU as being a Slave
Processor instruction.
3.4.1 Bus Cycles
STO, sn
o
3.5 INSTRUCTION PROTOCOLS
1I/IIIIIIIIIII!'-___
vA""I'L1o_ _
--'~~
-----------y.•",
-\
-
~\,_ _ _V_AL_IO_F_R_OM_FP_U_ _J}- --
DO-015 - - - - - - - - - -
TL/EE/5234-16
Note 1: FPU samples CPU status here.
FIGURE 3-5. Slave Processor Read Cycle
STO, STI
VALID
----------""\1
(NOTE 11
(NOTE 21
VALID FROM CPU
DD-015 - - - - - -
TLIEE/5234-17
Note 1: FPU samples CPU status here.
Nole 2: FPU samples data bus here.
FIGURE 3-6. Slave Processor Write Cycle
3-121
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r-------------------------------------------------------------------------------~
3.0 Functional Description (Continued)
Using the Addressing Mode lields within the Operation
Word, the CPU starts letching operands and issuing them to
the FPU. To do so, it relerences any Addressing Mode extensions appended to the FPU instruction. Since the CPU is
solely responsible lor memory accesses, these extensions
are not sent to the Slave Processor. The Status Code applied is 01 (Transler Slave Processor Operand, Table 3-1).
TABLE 3-1. General Instruction Protocol
Step
1
2
3
4
5
6
7
After the CPU has issued the last operand, the FPU starts
the actual execution 01 the instruction. Upon completion, it
will signal the CPU by pulsing SPC low. To allow lor this, the
CPU releases the SPC Signal, causing it to Iloat. SPC must
be held high by an external pull-up resistor.
8 7
0
100000000lNZOOOLOQI
VALUEIS)~
Action
CPU sends ID Byte.
CPU sends Operation Word.
CPU sends required operands.
FPU starts execution.
FPU pulses SPC low.
CPU reads Status Word.
CPU reads result (il any).
3.5.2 Floating-Point Protocols
Table 3-2 gives the protocols lollowed lor each floatingpoint instruction. The instructions are relerenced by their
mnemonics. For the bit encodings 01 each instruction, see
Section 2.2.3.
The Operand Class columns give the Access Classes lor
each general operand, delining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Relerence Manual).
The Operand Issued columns show the sizes 01 the operands issued to the Floating-Point Unit by the CPU. "D" indicates a 32-bit Double Word. "i" indicates that the instruction
specilies an integer size lor the operand (B = Byte, W ",;
Word, D = Double Word). "I" indicates that the instruction
specilies a Iloating-point size lor the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word Irom the FPU, applying Status Code 10.
This word has the lormat shown in Figure 3-7. II the a bit
("auit", Bit 0) is set, this indicates that an error has been
detected by the FPU. The CPU will not continue the protocol, but will immediately trap through the Slave vector in the
Interrupt Table. II the instruction being performed is CMPI
(Section 2.2.3) and the a bit is not set, the CPU loads Processor Status Register (PSR) bits N, Z and L Irom the corresponding bits in the Status Word. The NS32081 FPU always
sets the L bit to zero.
15
Status
11
01
01
XX
XX
10
01
..1
NEW PSR BIT
"QUIT": TERMINATE PROTOCOL, TRAP IFPU).
The Returned Value Type and Destination column gives the
size 01 any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, il any,
are updated Irom the Slave Processor Status Word (Figure
3-7).
TL/EE/5234-18
FIGURE 3-7. FPU Protocol Status Word Format
The last step in the protocol is lor the CPU to read a result,
il any, and transler it to the destination. The Read cycles
Irom the FPU are performed by the CPU while applying
Status Code 01 (Section 4.1.2).
Any operand indicated as being 01 type "I" will not cause a
transler il the Register addressing mode is specilied, because the Floating-Point Registers are physically on the
Floating-Point Unit and are therelore available without CPU
assistance.
TABLE 3-2. Floating Point Instruction Protocols
Mnemonic
ADDI
SUBI
MULl
DIV!
MOVI
ABSI
NEGI
CMPI
FLOORli
TRUNCIi
ROUNDli
MOVFL
MOVLF
MOVif
LFSR
SFSR
o~
i
Operand 1
Class
read.1
read.!
read.1
read.!
read.!
read.1
read.1
read.!
read.1
read.1
read.!
read.F
read.L
read.i
read.D
N/A
Operand 2
Class
rmw.!
rmw.!
rmw.!
rmw.1
write.!
write.!
write.!
read.!
writej
write.i
writej
write.L
write.F
write.!
N/A
write.D
Operand 1
Issued
I
f
N/A
N/A
N/A
F
L
i
D
N/A
Double Word
= Integer size (B, W, D) specified in mnemonic.
f ~ Floating-Point type (F. L) specified in mnemonic.
NtA
~
Operand 2
Issued
I
Not Applicable to this instruction.
3-122
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Returned Value
Type and Dest.
ItoOp.2
ftoOp.2
ftoOp.2
ItoOp.2
ItoOp.2
ItoOp.2
ftoOp.2
N/A
itoOp.2
itoOp.2
itoOp.2
LtoOp.2
FtoOp.2
fto Op. 2
N/A
DtoOp.2
PSRBlts
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
z
Logic Ground (GNDL): Ground reference for on-chip logic.
Section 3.1.
Buffer Ground (GNDB): Ground reference for on·chip drivers connected to output pins. Section 3.1.
The following are brief descriptions of all NS32081 FPU
pins. The descriptions reference the relevant portions of the
Functional Description, Section 3.
Dual-In-Line Package
4.1.2 Input Signals
Clock (CLK): TTL-level clock Signal.
010-~f-Vcc
09- 2
23 f- STO
OB- 3
22 f- ST1
07- 4
21 f-SPC
05- 6
I
01-Transferring Operation Word or Operand
10-Reading Status Word
II-Broadcasting Slave 10
18 -013
03- 8
17 -014
4.1.3 Input/Output Signals
02- 9
16 -015
Ol- IO
15 -im'
00- 11
14 -ClK
Slave Processor Control (SPC): Active low. Driven by the
CPU as the data strobe for bus transfers to and from the
NS32081 FPU, Section 3.4. Driven by the FPU to signal
completion of an operation, Section 3.5.1. Must be held high
with an external pull-up resistor while floating.
Data Bus (DO-D15): 16-bit bus for data transfer. DO is the
least significant bit. Section 3.4.
13 -GNDB
TLlEE/5234-3
Top View
FIGURE 4-1. Connection Diagram
Order Number NS32081D-l0 or NS32081D-15
See NS Package Number D24C
Order Number NS32081N-l0 or NS32081N-15
See NS Package Number N24A
4.2 ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
Storage Temperature
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
O'Cto +70'C
-65'Cto +150'C
All Input or Output Voltages
-0.5Vto +7.0V
with Respect to GND
Power Dissipation
1.5W
4.3 ELECTRICAL CHARACTERISTICS TA
Symbol
= O'C to 70'C, Vee = 5V ± 5%, GND = OV
Conditions
Parameter
Min
Typ
Max
Units
VIH
HIGH Level Input Voltage
2.0
Vee +0.5
V
VIL
LOW Level Input Voltage
-0.5
0.8
V
VOH
HIGH Level Output Voltage
IOH
= -400/LA
VOL
LOW Level Output Voltage
IOL
= 4mA
II
Input Load Current
o S; VIN S; Vee
IL
Leakage Current
Output and I/O Pins in
TRI-STATElinput Mode
0.45
Active Supply Current
lOUT
Icc
S;
VIN
S;
2.4
V
0.45
V
-10.0
10.0
/LA
-20.0
20.0
/LA
300
mA
2.4V
= 0, TA = 25'C
3-123
......
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04- 7
GNOl- 12
I
N
Status (STO, ST1): Input from CPU. STO is the least significant bit. Section 3.4 encodings are:
OO-(Reserved)
19 r012
oQC)
....
....o
....
....c.n
Reset (RST): Active low. Initiates a Reset, Section 3.3.
20 rOll
NS32081
FPU
N
Power (Vee): +5V positive supply. Section 3.1.
4.1 PIN DESCRIPTIONS
06- 5
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4.1.1 Supplies
4.0 Device Specifications
.
....
....
4.0 Device Specifications (Continued)
C')
4.4 SWITCHING CHARACTERISTICS
U) .-------------------------------------------------------------------------------~
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4.4.1 Definitions
All the Timing Specifications given in this section refer to O.BV
and 2.0V on all the input and output signals as illustrated in
Figures 4.2 and 4.3, unless specifically stated otherwise.
ABBREVIATIONS
L.E. -
Leading Edge
R.E. -
Rising Edge
T.E. -
Trailing Edge
F.E. -
Falling Edge
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2.0V
D.IV
SIGI
SIG2
[
[
SIOI
'SIOII
'Sl02h
jow
2.4V
Sl02
---------O.45V
[
[
2.4V
'SlG2h
TUEE/5234-27
TL/EE/5234-26
FIGURE 4·3. Timing Specification Standard
(Signal Valid Before Clock Edge)
FIGURE 4-2. Timing Specification Standard
(Signal Valid After Clock Edge)
3·124
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4.0 Device Specifications (Continued)
o
00
....
•
....
o
4.4.2 Timing Tables
4.4.2.1 Output Signal Propagation Delays
......
Maximum times assume capacitive loading of 100 pF.
Name
tev
Figure
4-7
Description
OataValid
Z
NS32081-10
Reference!
Conditions
Min
Max
Min
45
After SPC L.E.
(/)
NS32081-15
Units
Max
30
50
tOi
4-7
00-015 Floating
After SPC T.E.
tSPCFw
4-9
SPC Pulse Width
fromFPU
AtO.8V
(Both Edges)
tSPCFI
4-9
SPC Output Active
After ClK R.E.
55
38
ns
tSPCFh
4-9
SPC Output Inactive
After ClK R.E.
55
38
ns
tSPCFnf
4-9
SPCOutput
Nonforcing
After ClK F.E.
45
35
ns
Max
Units
tCLKp - 50
tCLKp
+
35
ns
50
\eLKp - 40
\eLKp
+ 40
ns
ns
4.4.2.2 Input Signal Requirements
Name
Figure
Description
Reference!
Conditions
Min
Max
Min
tpWA
4-5
Power Stable to
RSTR.E.
AfterVcc
Reaches 4.5V
50
50
/Ls
tASTw
4-6
RST Pulse Width
AtO.8V
(Both Edges)
64
64
tCLKp
tss
4-7
Status (STO-ST1)
Setup
Before SPC L.E.
50
33
ns
Ish
4-7
Status (STO-ST1)
Hold
After SPC L.E.
40
35
ns
tos
4-8
00-015 Setup Time
Before SPC T.E.
40
30
ns
tOh
4-8
00-015 Hold Time
After SPC T.E.
50
35
ns
tspcw
4-7
SPC Pulse Width
from CPU
AtO.8V
(Both Edges)
70
50
ns
tsPCs
4-7
SPC Input Active
Before ClK R.E.
40
35
ns
tSPCh
4-7
SPC Input Inactive
After ClK R.E.
0
0
ns
tASTs
4-10
RSTSetup
Before ClK F.E.
10
10
ns
tASTh
4-10
RST R.E. Delay
After ClK R.E.
0
0
ns
4.4.2.3 Clocking Requirements
Name
Figure
Description
Reference!
Conditions
Min
Max
Min
Max
Units
\eLKh
4-4
Clock High Time
At2.0V
(Both Edges)
42
1000
27
1000
ns
\eLKI
4-4
Clock low Time
AtO.8V
(Both Edges)
42
1000
27
1000
ns
tCLKp
4-4
Clock Period
ClK R.E. to Next
CLKR.E.
100
2000
66
3-125
ns
W
N
o
.
00
....
....
U1
......• r----------------------------------------------------------------------------,
4.0 Device Specifications
U)
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(Continued)
4.4.3 Timing Diagrams
~
....z
......•
«:)
Vcc
i------ICLICp------t
~----------------~~
n
,F
CD
«:)
C\I
CLK
C'I)
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m _____
TLfEEf5234-19
TLfEEf5234-20
FIGURE 4-4. Clock Timing
CLK
lIST
FIGURE 4-5. Power-On Reset
JULfLSLfL
----'""'i
IRST.
1-TLfEEf5234-21
FIGURE 4-6. Non-Power-On Reset
CLK _ _--!
STO.STI
DO-DIS
·-··----··-··----,.-··:~,{:J~~~~t)
TLiEEf5234-22
FIGURE 4-7. Read Cycle from FPU
Note: SI'e pulse must be (nominally) 1 clock wide when wTiting into FPU.
STO.STI
I'
DO-DI5
~'__ _ _V_A_U_D_F_R_O_M_CP_U_ _ _.......
TLfEEf5234-23
FIGURE 4-8. Write Cycle to FPU
Note:
SPC pulse may also be 2 clocks wide, but its edges must meet the !gpcs and tSPCh requirements with respect to elK.
3-126
z
4.0 Device Specifications
en
(0)
(Continued)
N
......o•
QI)
-\ t-tSPCFh
-\tSPCFlt-
o
.......
\ I
1~~SPCFnl
SPC---------~~______JI'
!.-tsPCF.-1
RsT
t
I
r
~
RST'
tRSlh
Tl/EE/5234-25
FIGURE 4-10. RST Release Timing
Note: The rising edge of RST must occur while elK is high, as shown.
3-127
N
......o.
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Tl/EE/5234-24
FIGURE 4-9. SPC Pulse from FPU
CLK-.J
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PRELIMINARY
~ Semiconductor
NS32580-20/NS32580-25/NS32580-30
Floating Point Controller
General Description
The NS32580 Floating-Paint Controller (FPC) is an interface
controller designed to couple the NS32532 Microprocessor
with the Weitek WTL 3164 Floating-Point Data Path (FPDP).
It is a new member of the Series 32000® family and it is fully
upward compatible with the existing NS32081 floating-point
software. The performance of the NS32580 (FPC) and the
WTL 3164 (FPDP) with the NS32532 has been significantly
enhanced for high-performance floating-paint applications.
It reaches the peak performance of 15 Mflops when executing single and double preCision ADD, SUB, MUL, and MAC
instructions in a pipelined mode while maintaining precise
exception handling.
The FPC/FPDP supports the IEEE 754-1985 standard for
Binary Floating-Point Arithmetic. An improved exception
handling scheme allows enabling or disabling of each of the
IEEE defined traps. It supports Infinity and Not a Number
(NaN) and can flush the result to zero or trap on underflowed instructions.
The NS32580 contains three FIFOs and a Floating-Paint
Status Register (FSR). It executes 18 instructions in conjunction with the WTL 3164 and with the NS32532 forms a
tightly coupled computer cluster. The FPC/FPDP appears
to the user as a Single slave processing unit. All addressing
modes, including two address operations, are available with
the floating-point instructions. In addition, the CPU and
FPC/FPDP communication is handled automatically, and is
user transparent.
The FPC is fabricated with National's advanced double-metal CMOS process and can operate at a frequency of
30 MHz.
Features
• Provides the NS32532 CPU with a complete interface
controller for high-speed floating-point arithmetic
• 15 Mflops peak performance for single and double precision ADD, SUB, MUL and MAC instructions with the
Weitek WTL 3164 FPDP
• Conforms to IEEE 754-1985 standard for Binary Floating-POint Arithmetic
• Pipelined Slave Protocol with Data and Instruction
FIFOs
• Improved exception handling including support of Infinities and Not a Number (NaN)
• Single (32-bit) and double (64-bit) precision operations
• Upward compatible with existing NS32081 software
base
• 20 MHz, 25 MHz and 30 MHz operating frequencies
• 1 ,...m double-metal CMOS technology
• 172-pin PGA package
Block Diagram
OONE
TA
I:::::::::==::::::::~~==::::~"IIP
'lIS
..'"
STATUS
....
"lIP
COH1ROL
TL/EE/9421-1
FIGURE 1-1
3-128
z
(J)
Table of Contents
1.0 PRODUCT INTRODUCTION
Co)
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3.0 FUNCTIONAL DESCRIPTION (Continued)
1.1 IEEE Features Supported
3.5 Instruction Protocols
1.2 Operand Formats
3.5.1 General Slave Protocol Sequence
3.5.2 Pipelined Slave Protocol Sequence
1.2.1 Normalized Numbers
CD
o
o
........
I
N
Z
(J)
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1.2.2 Zero
3.5.3 Status Word Register
1.2.3 Reserved Operands
3.5.4 Termination of Instruction (Not Including CMPf)
CD
1.2.4 Integer Formats
3.5.5 Byte Sex
N
U1
3.5.6 Floating-Point Protocols
1.2.5 Memory Representations
3.6 FPDP Interface
2.0 ARCHITECTURAL DESCRIPTION
2.1 Programming Model
2.1.1 Floating-Point Data Registers
Z
(J)
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3.6.1 Controlling the FPDP
N
U1
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o
3.6.4 FPDP Mode Control Registers SRO, SR1
2.1.2.1 FSR Mode Control Fields
I
........
3.6.2 Instruction Control
3.6.3 "2 Cycle Mode" and "3 Cycle Mode"
2.1.2 Floating-Point Status Register (FSR)
o
CD
I
3.6.5 IEEE Enables Register SR2
2.1.2.2 FSR Status Fields
3.6.5.1 FPDP Status Lines (SO-S3)
2.1.2.3 FSR Software Field (SWF)
3.6.6 FPC-FPDP Clocks
2.1.2.4 FSR New Fields
3.6.6.1 FPC Clock
2.1.2.5 FSR Default Values
3.6.6.2 FPDP Main Clock (WCLK)
2.2 Instruction Set
3.6.6.3 Divide/Sqrt Unit Clock (DIVCLK)
2.2.1 General Instruction Format
4.0 DEVICE SPECIFICATIONS
2.2.2 Addressing Modes
2.2.3 Floating-Point Instruction Set
4.1 NS32580 Pin Descriptions
2.3 Exceptions/TRAPs
4.1.1 Supplies
4.1.2 Input Signals
3.0 FUNCTIONAL DESCRIPTION
4.1.3 Output Signals
3.1 Power and Grounding
4.1.4 Input/Output Signals
3.2 Clocking
4.2 Absolute Maximum Ratings
3.3 Resetting
4.3 Electrical Characteristics
3.4 Bus Operation
4.4 Switching Characteristics
3.4.1 Operand Transfers
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signal Propagation Delays
4.4.2.2 Input Signal Requirements
APPENDIX A: Compatibility of FPC-FPDP with
NS32081INS32381
APPENDIX B: Performance Analysis
3·129
•
.
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List of Illustrations
FPC Block Diagram .......................•.................................................................... 1-1
Floating-Point Operand Formats ................................................................................. 1-2
Single-Precision Operand E and F Fields .......................................................................... 1-3
Double-Precision Operand E and F Fields ......................................................................... 1-4
Integer Format .........•.............••....•...•...............................................................1-5
Data Registers .................................................................................................2-1
FSR (Compatible Fields) ........................................................................................2-2
New FSR Mode Control Fields ...................•...........................................•.•................. 2-3
General Instruction Format ......................................................................................2-4
Index Byte Format ........•.................................................................................•..2-5
Displacement Encodings ........................................................................................2-6
Floating-Point Instruction Formats ................................................................................ 2-7
Recommended Supply Connections .......•.................•...............•....................................3-1
Power-On Reset Requirements ...........................•...•..................................................3-2
General Reset Timing ..........................................................................................3-3
Slave Processor Read Cycle from FPC ............................................................................3-4
Slave Processor Write Cycle to FPC .............................................................................. 3-5
System Connection Diagram ....................................................................................3-6
ID and Opcode Format ..........................................................................................3-7
32-Bit General Slave Instruction Protocol .•.... " ..•..............•................• , ...........................•.. 3-8
FPC Status Word Format ........................................................................................3-9
Byte Sex Connection Diagrams ..................•.............................................................. 3-10
FPDP Control Word ...........................................................................................3-11
FPDP Multiplier and ALU Bus Control ............................................................................ 3-12
IEEE Enables Register {FPDP) ..................................................................................3-13
FPDP Status Timing ...........•........•.......•..........•............................•.........•............3-14
Divide/Sqrt Clock DCLK2/DCLK3 ............................................................................... 3-15
NS32580 Interface Signals ......................................................................................4-1
172-Pin PGA Package ..........................................................................................4-2
Timing Specification Standard (Signal Valid after Clock Edge) ........................................................ 4-3
Timing Specification Standard (Signal Valid before Clock Edge) ...................................................... 4-4
Clock Waveforms ...........•...•.............•........•...................................................... .4-5
Power-On Reset ...........................................................•......................•.....•......4-6
Non-Power-On Reset. ..........................................................................................4-7
Read Cycle from FPC .......................................................................................... .4-8
Write Cycle to FPC .............................................................................................4-9
Slave Processor Done Timing ..................................................................................4-1 0
FSSR Signal Timing ...........................................................................................4-11
FPDP Status Signal Timing .....................................................................................4-12
FPDP Clock Signals Timing .....................................................................................4-13
FPDP Output Signals Timing ....................................................................................4-14
List of Tables
Sample F Fields ...........................•.....................••....................•.......•............... 1-1
Sample E Fields ...............................................................................................1-2
Normalized Number Ranges ................................................•.................................... 1-3
Integer Fields .•..................•........•.............•......................•...............................1-4
FSR Default State Summary .....................................................................................2-1
Series 32000 Family Addressing Modes ...........................................................................2-2
Exception Enabled/Disabled Summary ................................................................... , ....... 2-3
32-Bit General Slave Instruction Protocol ...................•.............•........................................3-1
Floating-Point Instruction Protocols ...............................................................................3-2
3-130
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1.0 Product Introduction
The E field contains an unsigned number that gives the binary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be subtracted from the E field value in order to obtain the true
exponent. The bias value is 011 ... 112, which is either 127
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
The NS32580 Floating-Point Controller (FPC) provides complete control for high speed floating-point operations between the NS32532 CPU and the Weitek WTL 3164 Floating-Point Data Path (FPDP). The FPC is fabricated using
National high-speed CMOS technology and operates as a
slave processor for transparent expansion of the Series
32000 CPU's basic instruction set. The NS32580 is compatible with the IEEE Floating-Point Formats by means of its
hardware and software features.
TABLE 1·2. Sample
F Field
EField
100 ... 0
011 ... 110
100 ... 0
011 ... 111
100 ... 0
100 ... 000
1.1 IEEE FEATURES SUPPORTED
a. Basic floating-point number formats
b. Add, subtract, multiply, divide, sqrt, and compare operations
c. Conversions between different floating-point formats
d. Conversions between floating-point and integer formats
e. Round floating-point number to integer (round to nearest, round toward negative infinity and round toward
zero, in double- or single-precision)
f. Exception signaling and handling (invalid operation, divide by zero, overflow, underflow and inexact)
Two values of the E field are not exponents. 11 ... 11 signals Not-a-Number (NaN) or Infinity (Section 1.2.3). 00 ...
00 represents the number zero (Section 1.2.2), if the F field
is also all zeroes, otherwise it signals a reserved operand
(Section 1.2.4).
The S bit indicates the sign of the operand. It is 0 for positive and 1 for negative. Floating-point numbers are in signmagnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
g. Positive and negative infinity (Section 1.2.3)
Note: In addition to supporting the IEEE floating-point overflow. the
NS32580 supports integer conversion overflow.
.
0)
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N
o
......
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N
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1.2.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.
Also, the FPC-FPDP can accept Not-a-Number (NaN) as an
operand and generate NaN as a result, but it does not conform to the IEEE 754-1985 Standard since it does not differentiate between signaling and quiet Not-a-Number.
The value of a Normalized number can be derived by the
formula:
(-1)8 X 2(E-Bias) X (1 + F)
The remaining IEEE features are supported in the software
library. These items include:
a. Extended floating-point number formats
b. Mixed floating-point data formats
The range of Normalized numbers is given in Table 1-3.
1.2.2 Zero
There are two representatives for zero-positive and negative. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.
c. Conversions between basic formats, floating-point numbers and decimal strings
d. Remainder
e. Denormalized numbers
1.2 OPERAND FORMATS
The NS32580 FPC operates on two floating-point data
types-single precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single preciSion data type, and the
suffix L (Long Floating) to select the double precision data
type.
1.2.3 Reserved Operands
Infinity arithmetic is the limiting case of real arithmetic with
operands of arbitrarily large magnitudes. The NS32580
does not treat infinity as a reserved operand and in
ROUND/i, TRUNCfi and FLOORfi instructions, when the operand is infinity, the FPC will return the TRAP "overflow"
instead of TRAP "INVALID OPERATION" with the Integer
Conversion Overflow Flag, IOF, set to "1".
Another special case regarding infinity occurs when dividing
infinity by zero. In this case NO TRAP "DIVIDE BY ZERO"
will be signaled and infinity will be returned as the result.
See Figures 1-3 and 1-4.
A floating-point number is divided into three fields, as shown
in Figure 1-2.
The F field is the fractional portion of the represented number. In Normalized numbers (Section 1.2.1), the binary point
is assumed to be immediately to the left of the most significant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
1.0:;;; x:;;; 2.0, as shown in Table 1-1.
FField
000 ... 0
010 ... 0
100 ... 0
110 ... 0
E Fields
Represented Value
1.5x2- 1 =0.75
1.5x2o=1.50
1.5 x 21 = 3.00
N
U1
The NS32580 FPC treats only Denormalized numbers as
reserved operands if the Floating-Point Status Register
ROE bit is set (Section 2.1.2). Denormalized numbers have
all zeroes in their E fields and non-zero values in their F
fields.
The NS32580 FPC causes an Invalid Operation Trap (Section 2.1.2.2) if it receives a reserved operand, unless the
operation is Simply a move (without conversion).
TABLE 1·1. Sample F Fields
Binary Value
Decimal Value
1.000 ... 0
1.000 ... 0
1.010 ... 0
1.250 ... 0
1.100 ... 0
1.500 ... 0
1.110 ... 0
1.750 ... 0
t
Implied Bit
3-131
•
1.0 Product Introduction
(Continued)
Single Precision
31 30
23 22
Is I
E
1
8
0
I
I
F
23
Double Precision
63 62
52 51
151
E
1
11
0
I
I
F
52
FIGURE 1-2. Floating-Point Operand Formats
TABLE 1-3. Normalized Number Ranges
Single Precision
Double Precision
2127 x (2 - 2- 23)
21023 x (2 - 2- 52)
= 3.40282346 x 1038
= 1.7976931348623157 X 10308
2- 126
2- 1022
= 1.17549436 X 10- 38
= 2.2250738585072014 X 10- 308
Most Positive
Least Positive
-(2- 126)
-(2- 1022)
= -1.17549436 x 10- 38
= -2.2250738585072014 X 10- 308
-2127 X (2 - 2- 23)
-21023 X (2 - 2- 52)
Most Negative
= -1.7976931348623157 X 10308
= -3.40282346 X 1038
Nole: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
Least Negative
E
F
Value
255
NatO
None
255
1-254
0
0
0
Any
NatO
0
(-1)S •
(-1)s'
(-1)"'
(-1)"'
Name
NaN
Infinity
2e - 127 ' (1.1)
2- 126 ' (O.f)
0
Infinity
Normalized Number
Denormalized Number
Zero
Comments
ROE = 0 -+ Reserved Operand
ROE = 1 -+ NaN Returned as Result
Not a Reserved Operand
Reserved Operand
FIGURE 1-3. Single-Precision Operand E and F Fields
E
F
2047
NatO
None
Value
NaN
Name
2047
1-2046
0
0
0
Any
NatO
0
( -1)" • Infinity
(-1)" • 2e-1023 • (1.t)
(-1)" • 2- 1022 • (O.t)
(-1)"'0
Infinity
Normalized Number
Denormalized Number
Zero
Comments
ROE = 0 -+ Reserved Operand
ROE = 1 -+ NaN Returned as Result
Not a Reserved Operand
Reserved Operand
FIGURE 1-4. Double-Precision Operand E and F Fields
3-132
1.0 Product Introduction (Continued)
+-
1.2.4 Integer Formats
The FPC-FPDP performs conversions between integer and
floating point operands. Integers are accepted and generated by the FPC-FPDP as two's complement values of byte
(8 bits), word (16 bits) or double-word (32 bits).
o
n-1
S
TABLE 1-4. Integer Fields
S
Value
Name
0
I
Positive Integer
1
1- 2n
Negative Integer
+-32LOLSDW
F1
LOMSDW
L1 MSDW
L1 LSDW
I
F3
L2MSDW
L2LSDW
L3MSDW
L3 LSDW
L4MSDW
L4LSDW
L5MSDW
L5LSDW
LSMSDW
L6LSDW
L7MSDW
L7LSDW
I
F5
F7
Z
-
+-32-
I
I
FIGURE 1-5. Integer Format
DATA
64
tn
(0)
I\)
en
co
o
FO
I
Z
F2
I
F4
I
F6
I
tn
(0)
I\)
en
co
o
•
I\)
en
......
Z
LSDW ..... Least Significant Double Word
MSDW ..... Most Significant Double Word
n represents number of bits in the word, 8 for byte, 16 for
word and 32 for double-word.
The FPDP supports only 32-bit integers, therefore, the FPC
has to sign extend 8- and 16-bit integers prior to integer to
floating-point number conversion.
In floating to integer conversion, FPC has to check possible
integer overflow, in case of 8- and 1S-bit integer formats.
•
I\)
o
......
tn
(0)
I\)
en
co
o
·
(0)
o
FIGURE 2-1. Data Registers
2.1.2.1 FSR Mode Control Fields
The FSR mode control fields select FPC operation modes.
The meanings of the FSR mode control bits are given below:
ROUNDING MODE (RM bit 8-7). This field selects the
rounding method. Floating-point results are rounded whenever they cannot be represented exactly. The rounding
modes are:
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly halfway between the two nearest values the even value
(Isb = 0) is returned.
01 Round toward zero. The nearest value which is closer
to zero or equal to the exact result is returned.
10 Round toward positive infinity. The nearest value which
is greater than or equal to the result is returned.
1.2.5 Memory Representations
The NS32580 FPC does not directly access memory. However, it is cooperatively involved in the execution of a set of
two-address instructions with the NS32532 CPU. The CPU
determines the representation of operands in memory.
In the Series 32000 family of CPUs, operands are stored in
memory with the least Significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the instruction format) with the most significant byte at the lowest
address.
11
Round toward negative infinity. The nearest value
which is less than or equal to the exact result is returned.
UNDERFLOW TRAP ENABLE (UEN bit 3). If this bit is set,
the FPC requests a trap whenever a result is too small in
absolute value to be presented as a Normalized number. If it
is not set, FPC returns a result of exactly zero.
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes nine registers; eight
data registers and one floating-point status register.
2.1.1 Floating-Point Data Registers (LO-L7)
INEXACT RESULT TRAP ENABLE (lEN bit 5). If this bit is
set, the FPC requests a trap whenever the result of an operation cannot be represented exactly in the operand format
of the destination (and no other exception occurred in the
same operation) or if the result of an operation overflows
and the overflow trap is disabled. If lEN is not set, the result
is rounded according to the selected rounding mode.
There are eight registers (LO-L7) in the FPDP for providing
high-speed access to floating-point operands. Each is 64
bits long. A floating-point register is referenced whenever a
floating-point instruction uses the Register addressing mode
(Section 2.2.2) for a floating-point operand. All other Register mode usages (i.e., integer operands) refer to the General
Purpose Registers (RO-R7) of the CPU, and the FPU transfers the operand as if it were in memory.
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions encountered during floating-point data processing. The meaning of the FSR status bits are given below:
Note: These registers are all upward compatible with the 32·bil NS32081
registers, (FO-F7), such that when the Register addressing mode is
specified for a double precision (64·bit) operand. a pair of 32·bit regis·
ters holds the operand. The programmer specifies the even register of
TRAP TYPE (TT bits 2-0). This 3-bit field indicates the reason for TRAP (FPU) requested by the FPC. The TT field is
loaded with zero whenever any floating-point instruction except LFSR or SFSR completes without exception. It is also
set to zero by a reset or by writing zero into it with the LFSR
instruction. The TT field is updated regardless of the setting
of the exception enable bits.
the pair which contains the least significant half of the operand and
the next consecutive register contains the most significant half.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register selects operating modes
and records any exceptional condition encountered during
execution of a floating-point operation. The FPC FSR contains all the NS32081INS32381 FSR bits and additional
fields for better exception handling. The FSR is cleared to
all zeros during reset.
3-133
•
.
Qr---------------------------------------------------------~
C")
Q
co
II)
N
C")
rn
2.0 Architectural Description
31
NewFields
z
6co
II)
N
C")
rn
z
~
6co
II)
N
C")
rn
z
98
7 6
5
4
3
2
0
SWF
FIGURE 2-2. FSR (Compatible Fields)
U=i
N
(Continued)
17 16 15
000 No exceptional condition occurred.
001 Underflow. This condition occurs whenever a result is
too close to zero to be represented as a Normalized
number.
2.1.2.4 FSR New Fields
New fields were added to the FSR for better exception handling. In the FPC, the user can enable or disable each exception or combination of exceptions by using new "enable
bits" implemented in the FSR. After reset the new fields are
loaded to the default values (compatible with NS32081). illegal Instruction always causes TRAP and can't be disabled.
CONTROL BITS
010 Overflow. This condition occurs whenever a result is
too large in absolute value to be represented (float or
integer).
011 Divide by Zero. This condition occurs whenever an
attempt was made to divide a non-zero value by zero.
100 Illegal Instruction. An illegal or undefined FloatingPoint instruction was passed to the FPC. If the T bit in
the Status Word Register (SWR) is a "0", then it indicates that an illegal instruction was passed to the
FPC. If the T bit in the SWR is a "1 ", then it indicates
that an undefined instruction was passed to the FPC.
101 Invalid Operation. This condition occurs if:
1. NaN is used as a floating-point operand by any instruction except MOVf and the Reserved Operand
Enable (ROE) bit in the FSR is disabled.
2. DNRM is used as a floating-point operand by any
instruction except MOVf.
3. Both operands of the DIVf instruction are zero.
4. Sqrt when the floating-point number is negative.
5. Infinity plus negative infinity, infinity minus infinity.
110 Inexact Result. This condition occurs whenever the
result of an operation cannot be exactly represented
in the precision of the destination (and no other exception occurred in the same operation) or if the result
of an operation overflows (floating-point or integer
conversion overflow) and the overflow trap is disabled.
RESERVED OPERANDS ENABLE (ROE bit 17). If this bit is
cleared, the FPC requests an Invalid Operation trap whenever a NaN has been detected by the FPC. Infinities are not
reserved operands in the FPC. When ROE is disabled, the
FPC does not generate reserved operands as results. Denormalized Numbers (DNRM) are always treated as reserved operands, except for the case of the SQRTf instruction. When calculating the square root of the negative denormalized number, the TRAP "INVALID OPERATION" will
occur and the Reserved Operand Flag ROF will be "0"
while Invalid Operation Flag IOF will be "1". If Invalid Operation exception is disabled, the ROE bit is overwritten internally (the FPC does not change the ROE bit in the FSR) and
the FPC can generate NaN as a result. ROE bit does not
affect MOVf instruction.
INVALID OPERATION ENABLE (IVE bit 18). If this bit is
cleared, the FPC requests a trap whenever the operation is
invalid. If this bit is set to "1", the trap is disabled and if
invalid operation occurred, NaN will be delivered as result.
DIVIDE BY ZERO ENABLE (DZE bit 19). If this bit is cleared
the FPC requests a trap whenever an attempt is made to
divide by zero. If this bit is set the trap is disabled and if
divide by zero occurred, infinity will be delivered as result.
OVERFLOW ENABLE (OVE bit 20). If this bit is cleared, the
FPC requests a trap whenever a floating-point result is too
big in absolute value to be represented. If this bit is set, the
overflow trap is disabled and if overflow occurred, Infinity or
Maximum Number will be delivered as result.
INTEGER CONVERSION OVERFLOW ENABLE (IOE bit
21). If this bit is cleared, the FPC requests a trap whenever
an Integer result is too big to be represented. If this bit is
set, the integer conversion overflow is disabled and if integer conversion overflow occurred, Max/Min integer will be
delivered as result.
111 Reserved.
UNDERFLOW FLAG (UF bit 4). This bit is set by the FPC
whenever a result is too small in absolute value to be represented as a Normalized number. Its function is not affected
by the state of the UEN bit. The UF bit is "sticky" therefore
it can be cleared only by writing a zero into it with the Load
FSR instruction or by a hardware reset.
INEXACT RESULT FLAG (IF bit 6). This bit is set by the
FPC whenever the result of an operation must be rounded
to fit within the destination format (and no other exception
occurred in the same operation) or if the result of an operation overflows and the overflow trap is disabled. This situation applies both to floating-point and integer destinations.
The IF bit is "sticky" therefore it is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
REGISTER MODIFY BIT (RMB BIT 16). This bit is set by the
FPC whenever writing to a floating-point data register. The
RMB bit is cleared only by writing a zero with the LFSR
instruction or by a hardware reset. This bit can be used in
context switching to determine whether the FPC registers
should be saved.
STATUS BITS
RESERVED OPERAND FLAG (ROF bit 22). This bit is set
by the FPC whenever reserved operand DNRM or NaN
(when ROE is cleared) is selected by the FPC. The ROF bit
is "sticky" and can be cleared only by writing a zero with the
Load FSR instruction or by a hardware reset.
INVALID FLAG (IVF bit 23). This bit is set by the FPC whenever the operation is invalid. The IVF bit is "sticky" and can
be cleared only by writing a zero with the Load FSR instruction or by a hardware reset.
DIVIDE BY ZERO FLAG (DZF bit 24). This bit is set by the
FPC whenever an attempt is made to divide a non-zero value by zero. The DZF bit is "sticky" and can be cleared only
by writing a zero with the Load FSR instruction or by a hardware reset.
2.1.2.3 FSR Software Field (SWF)
Bits 15-9 of the FSR hold and display any information written to them using the LFSR and SFSR instructions, but are
not otherwise used by FPC hardware. They are reserved for
use with NSC floating-point extension software.
3-134
z
2.0 Architectural Description
31
27
Reserved
en
c.:I
(Continued)
I\)
26
25
24
23
22
21
20
19
18
17
IOF
OVF
DZF
IVF
ROF
IOE
OVE
DZE
IVE
ROE
16
I RMB I
FIGURE 2-3. New FSR Mode Control Fields
OVERFLOW FLAG (OVF bit 25). This bit is set by the FPC
whenever a floating-paint result is too large in absolute val·
ue to be represented. The OVF bit is "sticky" and can be
cleared only by writing a zero with the Load FSR instruction
or by a hardware reset.
INTEGER CONVERSION OVERFLOW FLAG (IOF bit 2S).
This bit is set by the FPC whenever an integer result is too
large in absolute value to be represented. The IOF bit is
"sticky" and can be cleared only by writing a zero with the
Load FSR instruction or by a hardware reset.
RESERVED FIELD
TABLE 2-1. FSR Default State Summary (Continued)
Bit Name
No exceptional condition
occurred.
UEN(bit3)
0
Underflow trap disabled.
UF (bit 4)
0
Underflow flag is cleared.
lEN (bit 5)
0
Inexact result trap disabled.
IF (bitS)
0
Inexact flag is cleared.
RM (bits 8-7)
0
Round to nearest.
SWF (bits 15-9)
0
Undefined
RMB (bit 1S)
0
RMB flag is cleared.
ROE(bitI7)
0
FPC requests a trap whenever
an attempt is made to use
reserved operand except for
MOVf instruction.
IVE (bit 18)
0
FPC requests a trap whenever
the operation is invalid.
DZE (bit 19)
0
FPC requests a trap whenever
an attempt is made to divide by
zero.
OVE(bit20)
0
FPC requests a trap whenever a
floating-point result is too big to
be represented.
IDE (bit 21)
0
FPC requests a trap whenever
an integer conversion result is
too big to be represented.
ROF(bit22)
0
ROF flag is cleared.
o
I
IVF(bit23)
0
IVF flag is cleared.
......
DZF (bit 24)
0
DZF flag is cleared.
OVF (bit 25)
0
OVF flag is cleared.
en
c.:I
IOF(bit2S)
0
IOF flag is cleared.
co
RESERVED
(bits 31-27 )
0
Reserved field is c'2ared.
C11
z
I\)
C11
o
c.:I
o
I
Figure 2-4 shows the general format of a Series 32000 instruction. The Basic Instruction is one to three bytes long
and contains the opcode and up to two 5-bit General Addressing Mode (Gen) fields. Following the Basic Instruction
field is a set of optional extensions, which may appear depending on the instruction and the addressing modes selected.
The only form of extension issued to the NS32580 FPC is
an Immediate operand. Other extensions are used only by
the CPU to reference memory operands needed by the
FPC.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-5.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Displlmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-6, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most significant byte first.
Default State
0
Default State
co
2.2 INSTRUCTION SET
TABLE 2-1. FSR Default State Summary
TI(bits2-0)
I\)
C11
Default
Value
2.2.1 Generaiinstruction Format
2.1.2.5 FSR Default Values
During Reset the FSR is loaded to a default value (see Table 2-1). The default values for the FSR represent upward
compatibility of the FPC-FPDP with the NS32081. The user
can change the default values by loading the FSR register
with new values.
Default
Value
I\)
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......
z
en
c.:I
I\)
Bits 31-27 in the FSR are reserved by NSC for future use.
User should not use this field.
Bit Name
C11
co
oI
Some non-FPC instructions require additional, "implied" immediates and/or displacements, apart from those associated with addressing modes. Any such extensions appear at
the end of the instruction, in the order that they appear within the list of operands in the instruction definition.
2.2.2 Addressing Modes
The Series 32000 Family CPUs generally access an operand by calculating its Effective Address based on information available when the operand is to be accessed. The
method to be used in performing this calculation is specified
by the programmer as an "addressing mode."
Addressing modes in the Series 32000 family are designed
to optimally support high-level language accesses to variables. In nearly all cases, a variable access requires only
3-135
•
2.0 Architectural Description
(Continued)
OPTIONAL
BASIC
EXTENSIONS
INSTRUcnON
rr----------------~A~------------------~\r~--------~A~--------,
I
I
I
I
I
I
I
I
I
I
DISP2 DISPI DISPZIDISPI
IMPUED
IMMEDIATE
OPERAND(SI
DISP
DISP
INDEX
BYTE
INDEX
BYTE
GEN
ADDR
MODE
A
:
IMM
IMM
~
~
l
GEN
ADDR
MODE
B
I
I
I
I
I
I
I
I
I
I
I
I
OPCODE
TLlEE/9421-2
FIGURE 2·4. General Instruction Format
Top of Stack: The currently-selected CPU Stack Pointer
(SPO or SP1) specifies the location of the operand. The operand is pushed or popped, depending on whether it is written or read.
one addressing mode within the instruction which acts upon
that variable. Extraneous data movement is therefore minimized.
Series 32000 Addressing Modes fall into nine basic types:
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any General Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
The following table, Table 2-2, is a brief summary of the
addressing modes. For a complete description of their actions, see the Series 32000 Instruction Set Reference Manual.
Register: In floating-point instructions, these addressing
modes refer to a Floating-Point Register (FO-F7) or (LOL7) if the operand is of a floating-point type. Otherwise, a
CPU General Purpose Register (RO-R7) is referenced. See
Section 2.1.1.
Register Relative: A CPU General Purpose Register contains an address to which is added a displacement value
from the instruction, yielding the Effective Address of the
operand in memory.
7
GEN. ADDR. MDDE
SIGNED DISPLACEMENT
TLlEE/9421-3
FIGURE 2·5. Index Byte Format
7
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated CPU
registers PC, SP, S8 or FP. These registers point to data
areas generally needed by high-level languages.
Memory Relative: A pointer variable is found within the
memory space pOinted to by the CPU SP, S8 or FP register.
A displacement is added to that pOinter to generate the Effective Address of the operand.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written. Floating-point operands as well as integer operands
may be specified using Immediate mode.
0
7
1
1
I
r:c.",f..'t\'\
~f..\\\\'''~
..,'iJ
Absolute: The address of the operand is specified by a
Displacement field in the instruction.
External: A pOinter value is read from a specified entry of
the current Link Table. To this pOinter value is added a displacement, yielding the Effective Address of the operand.
TLIEE/9421-4
FIGURE 2·6. Displacement Encodlngs
3-136
2.0 Architectural Description
z
en
w
(Continued)
to.)
TABLE 2-2. Series 32000 Family Addressing Modes
Mode
Assembler Syntax
Encoding
U1
00
Effective Address
oI
to.)
o
......
None: Operand is in the specified register.
en
w
REGISTER
00000
00001
00010
00011
00100
00101
00110
00111
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
RO,
R1,
R2,
R3,
R4,
R5,
R6,
R7,
FO or LO
F1 orL1
F2 or L2
F3 or L3
F40rL4
F5 or L5
F6 or L6
F7 or L7
to.)
U1
00
o
N
U1
......
z
en
w
to.)
U1
00
REGISTER RELATIVE
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp + Register.
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
* +disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP))
disp2(disp1 (SP))
disp2(disp1 (SB))
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP" is
either SPO or SP1, as selected in PSR.
Immediate
value
None: Operand is issued from
CPU instruction queue.
Absolute
@disp
Disp.
External
EXT (disp1) + disp2
Disp2 + Pointer; Pointer is found
at Link Table Entry number Disp1.
Top of Stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:B]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
Mode + Rn.
Mode + 2 x Rn.
Mode + 4 X Rn.
Mode + 8 x Rn.
"Mode" and "n" are contained
within the Index Byte.
10011
(Reserved for Future Use)
MEMORY SPACE
11000
11001
11010
11011
MEMORY RELATIVE
10000
10001
10010
IMMEDIATE
10100
ABSOLUTE
10101
EXTERNAL
10110
TOP OF STACK
10111
z
SCALED INDEX
3-137
oI
W
o
2.0 Architectural Description (Continued)
2.2.3 Floating-Point Instruction Set
instruction format (Rgurs 2-7). Refer to Table 2·2 for the
options available and their patterns.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
The NS32580 FPC-FPDP instructions occupy formats 9, 11
and 12 of the Series 32000 Family instruction set (Figure
2-7). A list of all Series 32000 family instruction formats is
found in the applicable CPU data sheet.
Certain notations in the following instruction description tables serve to relate the assembly language form of each
instruction to its binary format in Figure 2-7.
Movement and Conversion
The following instructions move the gen1 operand to the
gen2 operan~, leaving the gen1 operand intact.
Format 9
Format Op
Instruction
11
0001 MOVf
gen1, gen2
iii
I
gen2
I
I I iii I I
0
0 1 1 1 1 1 0
OPERATION WORD
I
,
'\
9
010 MOVLF
gen1, gen2
9
011
gen1, gen2
Move, converting
from single
preCision to
double
precision.
9
000 MOVif
gen1, gen2
9
100 ROUNDfi
gen1, gen2
9
101 TRUNCfi
gen1, gen2
9
111
gen1, gen2
Move, converting
from any integer
type to any
floating-point
type.
Move, converting
from floatingpoint to the
nearest integer.
Move, converting
from floatingpoint to the
nearest integer
closer to zero.
Move, converting
from floatingpoint to the
largest integer
less than or
equal to its
value.
10 BYTE
TUEE/9421-5
Format 11
23
I. I
I
I
aenl
I
I
16 115
gan2
I
I•
I
I
op
MOVFL
10 I,17,. 0 i 1 i 1 i ,.,.,. 00 I
B
H
OPERATION WORD
,
10 B'YTE
TLlEE/9421-6
Format 12
TL/EE/9421-7
FIGURE 2-7. Floating-Point Instruction Formats
The Format column indicates which of the three formats in
Figure 2-7 represents each instruction.
The Op column indicates the binary pattern for the field
called "op" in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case, with one or more suffixes (i or f) indicating data types, followed by a list of operands (gen1, gen2).
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This choice affects the binary pattern in
the i field of the corresponding instruction format (Figure 2-7)
as follows:
Suffix I
B
W
D
Data Type
Byte
Word
Double Word
Data Type
Single Precision
Double Precision (Long)
FLOORfi
Note: The MOVLF instruction f bit must be 1 and the i field must be 10.
The MOVFL instruction f bit must be 0 and the i field must be 11.
Arithmetic Operations
The following instructions perform floating-point arithmetic
operations on the gen 1 and gen2 operands, leaving the result in the gen2 operand.
I Field
00
01
11
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format (Figure 2-7)
as follows:
Suffix f
F
L
Description
Move without
conversion.
Move, converting
from double
precision to
single precision.
f Bit
o
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the binary pattern in the corresponding gen1 or gen2 field of the
3-138
Format
11
11
Op
0000
0100
Instruction
ADDf gen1,gen2
SUBf gen1,gen2
11
1100
MULf
11
1000
DIVf
11
0101
NEGf
11
1101
ABSf
Description
Add gen1 to gen2.
Subtract gen 1
fromgen2.
gen1,gen2 Multiply gen2 by
gen1.
gen1,gen2 Dividegen2
bygen1.
gen1,gen2 Move negative
of gen1 to gen2.
gen1,gen2 Move absolute
value of gen1 to
gen2.
,--------------------------------------------------------------------------, z
2.0 Architectural Description
tJ)
Co)
(Continued)
N
Format Op
Inl3truction
Description
(N)
12
1010 MACf genl, gen2 Move (genl"gen2)
+ L1 or Fl to L1
or F1 with two
rounding errors.
(N)
12
0001 SQRTI genl, gen2 Move the square
root of gen 1 to
gen2.
2.3 EXCEPTIONS/TRAPS
An exception for the FPC is a special floating-paint condition with a default handling scheme. Seven types of exceptions are supported:
1) Underflows
2) Overflows
3) Divisions by zero
4) Illegal Instructions
(N): Indicates NEW instruction.
Format
11
Opcode
0010
Instruction
CMPf genl, gen2
The FPC has improved exception handling. Except for illegal and Undefined Instructions, the user can control all of
the exception types. In addition, there are some specific
exceptions that the user can control:
-Floating-Point overflow
Overflows
Integer conversion overflow
Description
Compare genl
to gen2.
There are four possible results to the CMPf instruction (with
normal operands):
Operands are equal
Z bit is set N, L bits are cleared
Operand1 is less than
Operand2
Invalid Operations
Operand2 is less than
Operand1
N bit is set
L, Z bits are cleared
Unordered (when
at least one
operand is NaN
and ROE is set)
L bit is set
N, Z bits are cleared
Enabling an exception will cause a TRAP whenever the exception occurs and disabling an exception will return a result
without a TRAP.
When the FPC TRAPS it sets the Q bit in the status word
register. The CPU responds by reading the status word register while applying status (11110) on the status lines. If the
CPU sent the FPC ID with an undefined opcode, the T bit in
the status word register would also be set by the FPC indicating a TRAP (UND). If the T bit is clear aiter the TRAP it
indicates a TRAP(FPU) and the reason for the TRAP resides in the FSR TRAP TYPE field. A trapped instruction
returns no result (also if the destination is an FPDP register)
and does not affect the CPU PSR.
In addition there is a flag bit, for each exception under user
control, which will mark the occurrence of the exceptional
condition whether or not the exception is enabled or disabled. These bits in the FSR can be used for polling the
exception status while TRAPS are disabled.
Floating-Point Status Register Access
The following instructions load and store the FSR as a 32bit integer. If the user specifies a register (genl in LFSR or
gen2 in SFSR) it will be a general purpose register in the
CPU.
Format
9
Opcode
001
9
110
Instruction
LFSR genl
SFSR
gen2
-Reserved Operands
Each exception or type that is controlled by the user can be
set-up to cause an interrupt or to return a result without an
interrupt on the occurrence of the exception. The interrupt is
called a TRAP and is signaled by the FPC pulsing the FSSR
line for one clock cycle. Illegal and Undefined instructions
are not under control of the user and will always cause a
TRAP if they are passed to the FPC.
N, L,Zbits
are cleared
Description
Load FSR with the
content of gen1.
(gen2 field = 0)
Store FSR in gen2.
(gen1 field = 0)
Note: All instructions support all of the NS32000 family data formats (for
external operands) and all addressing modes are supported.
Floating-point instructions that end with an enabled exception will trap, activating the FSSR signal, but will not update
the destination register. In this case, the FPC will ABORT
the instruction that ended with the exception to prevent destruction of the data in the destination register. Instructions
that ended with a disabled exception update the destination
register with the default result.
3-139
Q)
C)
·
N
C)
......
Z
tJ)
~
U1
Q)
C)
·
N
5) Invalid Operations
6) Inexact results
7) Undefined Instructions
Comparison
The compare instruction compares two floating-point operands, sending the result to the CPU PSR Z, Nand L bits for
use as condition codes.
U1
U1
......
Z
tJ)
Co)
N
U1
Q)
C)
·
Co)
C)
«:)
C')
:i
2.0 Architectural Description
It)
(Continued)
TABLE 2·3. Exception Enabled/Disabled Summary
N
C')
(I)
Z
.....
.
Exception Occurred
It)
Enabled By
N
«:)
CQ
It)
N
C')
Q = 1;
Trap Type
Q= 0;
Default
Result Returned
Flag Bits
Underflow
UEN = 1
001
UEN = 0
Zero
UF = 1
Floating·Point Overflow
OVE= 0
010
OVE = 1
lEN = 0
Infinity or
Max NRM Number
OVF = 1
OVE = 1
lEN = 1
110
IOE = 0
010
IOE = 1
lEN = 1
110
(I)
Z
.....
.
«:)
N
«:)
CQ
It)
Disabled By
Integer Conversion Ov.
N
C')
en
z
OVF = 1
IF = 1
IOE= 1
·IEN = 0
Max or Min
Integer
IOF= 1
IOF:. 1
IF = 1
Divide by Zero
DZE = 0
011
DZE = 1
Infinity
DZF = 1
Illegal Instruction
Always
Enabled
Tbit = o and
100
Cannot be
Disabled
No Result
No Flags
Affected
Invalid Operation
IVE = 0
101
IVE = 1
NaN
IVF = 1
ROE = 0
IVE = 0
101
ROE = 0
IVE= 1
NaN
ROF = 1
IVF = 1
000
ROE = 1
IVE = X
NaN
No Flags
ROE = X
IVE = 0
101
ROE = X
IVE = 1
Undefined
ROF = 1
IVF = 1
Inexact Result
lEN = 1
110
lEN = 0
Correctly
Rounded Result
IF = 1
Undefined Instruction
Always
Enabled
Tbit = 1 and
100
Cannot be
Disabled
No Result
No Flags
Affected
Reserved Op. (NaN)
Reserved Op. (NaN)
Reserved Op. (DNRM)
Status Word
Register
CMPf(NaN)
ROE = 0
IVE = 0
CMPf(NaN)
CMPf(DNRM)
x
~
ROE =X
IVE = 0
101
ROE = 0
IVE = 1
L=1,N=Z=0
ROF = 1
IVF = 1
000
ROE = 1
IVE = X
L=1,N=Z=0
No Flags
Affected
101
ROE = X
IVE = 1
N, L,Z
Undefined
ROF = 1
IVF = 1
Don't Care
3·140
r--------------------------------------------------------------------------,
3.0 Functional Description
Z
tn
w
I\)
U1
(VCC PLANE)
+5V
co
9I\)
o
......
Z
tn
w
I\)
VCCLl
VCCL2
U1
co
o
VCCL3
•
I\)
U1
......
VCCL4
VCCL5
Z
VCCL6
tn
w
I\)
VCCL7
.
U1
VCCBl
co
o
w
o
VCCB2
VCCB3
VCCB4
VCCB5
VCCB6
VCCB7
VCCBB
NS32580
(GND PLANE)
TL/EE/9421-8
FIGURE 3-1. Recommended Supply Connections
3.1 POWER AND GROUNDING
3.2 CLOCKING
The NS325BO FPC requires a single-phase TTL clock input
on its BCLK pin (pin C10) and an inverted TTL clock input
on its BCLK pin (pin BB). When the FPC is connected to a
NS32532 CPU these signals are provided directly from the
CPU's BCLK and BCLK output signals.
The NS325BO requires a single 5V power supply, applied on
15 pins. The logic voltage pins (VCCL1 to VCCL7) supply
the power to the on-chip logic. The buffer voltage pins
(VCCB1 to VCCBB) supply the power to the output drivers of
the chip. All the voltage pins should be connected together
by a power (Vee) plane on the printed circuit board.
The NS325BO grounding connections are made on 26 pins.
The logic ground pins (GNDL1 to GNDL13) are the ground
pins for the on-chip logic. The buffer ground pins (GNDB1GNDB13) are the ground pins for the output drivers of the
chip. All the ground pins should be connected together by a
ground plane on the printed circuit board.
3.3 RESETTING
The RST pin serves as a reset for on-chip logic. The FPC
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPC terminates instruction processing, resets its internal logic,
clears the FSR to all zeroes, and clears the FIFOs.
On application of power, RST must be held low for at least
50 fJos after Vee is stable. This ensures that all on-chip voltages are completely stable before operation. See Figures
3-2 and 3-3.
Both power and ground connections are shown in Figure
3-1.
3-141
•
3.0 Functional Description
(Continued)
BCLK
BCLK[._-+-~
I--
s-IL..JL
2:
RST [
~~4 ----~---4-----n-+---4----
64 Clo;aCK_
CYCLES
(NOTE 3)
1 - - - - 2: 50}'1
oo-~, --------~c:::::~::~)
Tl/EE/9421-9
FIGURE 3-2. Power-On Reset Requirements
Tl/EE/9421-12
Note 1: FPC samples CPU status here.
Note 2: FPC samples l!J5O here.
Note 3: FPC samples data here.
FIGURE 3-5. Slave Processor Write Cycle to FPC
From the slave processor point of view there are four possi·
ble combinations of locations for operands: (For special
cases see next paragraph.)
Register to Register Instructions--Both operands reside in
the register file inside the FPDP. No operand fetch or trans·
fer from memory is needed.
Memory to Register-The source operand is in memory,
therefore the CPU will transfer the operand (one 32-bit
transfer for single·precision and two 32·bit transfers for double·precision). The result is going to the floating,point regis·
ter in the register file located inside the FPDP.
Register to Memory-The source operand resides inside
the FPDP. If the instruction is monadic (one operand) the
CPU will not transfer the operand to the FPC before the
beginning of the instruction (all the information needed to
start the operation resides inside the FPDP). For dyadic in·
structions, the CPU will fetch and transfer one operand from
memory.
TLlEE/9421-10
FIGURE 3-3. General Reset Timing
3.4 BUS OPERATION
Instructions and operands are passed to the NS325BO FPC
with slave processor bus cycles. Each bus cycle transfers
one double·word (32 bits) to or from the FPC. During all bus
cycles, the SPC line is driven by the CPU as an active low
data strobe, and the FPC monitors pins STO-ST4 to keep
track of the sequence (protocol) established for the instruc·
tion being executed. This is necessary in a virtual memory
environment, allowing the FPC to retry an aborted instruc·
tion.
A bus cycle is initiated by the CPU, which asserts the proper
status on STO-ST4 and pulses SPC low. The status lines
are sampled by the FPC on the rising edge of BCLK in the
T2 state. Figures 3·4 and 3-5 illustrate these sequences.
Memory to Memory-In monadic instructions the source op·
erand is in memory and the CPU will transfer it to the FPC·
FPDP. If the instruction is dyadic, two operands will be
transferred from memory to the FPC·FPDP by the CPU
(gen 1 before gen2). The result in both cases is sent back to
memory.
When the CPU transfers an operand from memory to the
FPC-FPDP it is loaded into one of the registers that create
the operand FIFO inside the FPDP. The FPC translates the
incoming instruction (mem, reg or mem, mem) to a registerto-register instruction with the same register number. From
the incoming instruction addressing mode it should know if
the operands are coming from memory or already located in
the register file.
3.4.1 Operand Transfers
The CPU fetches operands from memory, aligns them (if
needed) and sends them to the slave (with status h'1 D) as a
32·bit transfer. If the operand is double·precision the Less
significant half is transferred first (in 32000 mode). The FPC
can not access the memory directly.
BClK
STO-ST.
The Data FIFO inside the FPC is 10 entries deep, single- or
double-precision. If the destination of instruction is memory,
the FPC will wait for completion of the instruction. Then, the
result will be transferred to the FPC and SON will be signaled. If the FPC receives a new 10 and Opcode before the
CPU finishes reading the result, (can happen if page fault
has been detected on a write) the FPC will abort the last
instruction and will start the execution of the new instruction. The NS32532 CPU can "reset" the FPC by issuing
SPC and status h' 1E when there was no FSSR from FPC. In
this case FPC flushes the instructions currently being executed and the contents of the floating-point registers are
undefined.
(NOTE 2)
DO-D3t - - - - - - - - - - - - - -
Note 1: FPC samples CPU status here.
Note 2: CPU samples FPC data here.
t>---
~V~AU~D~FR~OM~FPSC
TLlEE/9421-11
FIGURE 3·4. Slave Processor Read Cycle from FPC
3-142
w
b
"n
C
::l
NS32532-30
NS32580-30
BQ.K
BCLK
BQ.K
BCLK
..
DATA BUS
32-BIT
A
00-D31
..
XO-X31
STD-ST4
SO-S3
0'
FO-F4
g
ABIN
AAIN
ABIN
c:
m
MAIN
MAIN
!'1
::l
4-BIT
5/
AAIN
FPC
~
5/
AADDO-AADD4
CADDO-CADD4
10K.D.
SPC
SPC
SDN
SDN
FSSR
FSSR
RST
RST
5
'1
CADDO-CADD4
5
EFDoo-EFDD4
5
4
DADDO-DADD4
/
EFDDO-EFDD4
XCNTO-XCNT3
ABORT
WABORT
+5V
BS
I+l+~
,"
BADDO-BADD4
5
XCNTO-XCNT3
LMODE
RST
S.
FPDP
AADDO-AADD4
5/
BADDO-BADD4
10K.D.
a.
:::l
MBIN
MBIN
+5V
t';
~
..,
XO-X31
SO-S3
FO-F4
CPU
CD
DIVCLK
"§:
"
"
! A
I'
5-BIT
..
DATA BUS
32-BIT
A
DO-D31
c
CLK
WCLK
DIVCLK
I'
STO-ST4
c::li"
et
WTL-3164-15
l10kA
e...;
r
STALL
NEUT
OEX
TL/EE/9421-13
FIGURE 3-6. System Connection Diagram
oe-08sc:eSN/sC:-08sc:eSN/OC:-08sc:eSN
II
3.0 Functional Description
(Continued)
3.5 INSTRUCTION PROTOCOLS
(023-016) and puts the Opcode high on byte 1 (015-08).
Byte 0 (07-00) is not used.
3.5.1 General Slave Protocol Sequence
The FPC interfaces with the CPU using the Slave-Protocol.
The slave protocol is a well defined protocol for instruction
and operand transfers between the CPU and the slave coprocessors (FPC and Custom Slave). Only the CPU can initiate slave cycle or access memory to fetch operands. The
communication between the CPU and the FPC occurs at the
beginning of the floating-point instruction, when the CPU
transfers the Opcode and possible operands. At the end of
the instruction, the FPC signals successful or unsuccessful
conclusion of floating-point instruction and the CPU transfers operands from the FPC, if applicable.
The CPU broadcasts the 10 and Opcode to all slave processors, one of which will recognize it and from this point the
CPU is communicating only with one slave processor.
The CPU puts the slave 10 (different 10 for each format) on
byte 3 (031-024), puts the Opcode low on byte 2
31
23
10
15
7
0
1 OPCOOE low 1 OPCOOE high 1 XXXXXXXX 1
Byte 3
Byte 2
Byte 1
Byte 0
FIGURE 3·7. 10 and Opcode Format
CPU Status Combinations
11101 (h'1 0) Transfer Slave Processor Operands-The
CPU is transferring an operand to or from a
slave processor.
11110 (h'1 E) Read Slave Processor Status-The CPU is
reading the Status Word Register aiter the
FPC signaled TRAP or is resetting the FPC
when there was no FSSR.
11111 (h'1 F) Broadc~:st Slave 10-The CPU is initiating
the execution of a slave processor instruction.
The floating-point unit has three different instruction formats:
Format
91 23
"
MOVif -000
LFSR -001
8 7
16115
Gen 2
Gen 1
MOVLF -010
MOVFL -011
Op
1
ROUNO -100
TRUNC -101
23
1
Gen 1
AOOf
MOVf
CMPf
Trap(FPU)
Format 12 23
1
-0000
-0001
-0010
-0011
Gen2
SUBf
NEGf
Trap(UNO)
Trap(UNO)
Op
-0100
-0101
-0110
-0111
81 7
0 1 f
OIVf
Trap(FPU)
Trap(UNO)
Trap(UNO)
-1000
-1001
-1010
-1011
Op
0
16115
Gen2
Gen 1
SCAlBf"
-0100
SREMf" -0000
-0001
lOGBf"
-0101
SaRTI
Trap(UND) -0110
POlYf"
-0010
DOTf"
-0011
Trap(UND) -0111
"All the marked instructions are not supported
0
SFSR
-110
FLOOR -111
16115
Format 11
0
1
0
MUll
ABSf
Trap(UNO)
Trap(UNO)
8
f 1
-1100
-1101
-1110
-1111
~
Trap(UNO) -1000
Trap(UNO) -1100
Trap(UNO) -1001
Trap(UNO) -1101
Trap(UND) -1110
MACf
-1010
Trap(UND) -1011
Trap(UNO) -1111
by the NS32580 and will cause Trap(UND).
TABLE 3·1. 32·Bit General Slave Instruction Protocol
Step
Status
Action
1
2
3
4
5
10 (11111)
OP (11101)
6
OP (11101)
CPU sends 10 and Operation Word
CPU sends required operands (if any)
Slaves starts execution (CPU prefetches)
Slave signals DONE, TRAP or CMPf
CPU Reads Status Word (If TRAP was signaled
or if a"CMPf instruction was executed)
CPU Reads Result (if destination is
memory and if no TRAP occurred)
-
ST (11110)
3-144
:1
:1
z
3.0 Functional Description
en
w
(Continued)
N
U1
CD
0
TABLE 3-2. Floating-Point Instruction Protocols
Mnemonic
ADDI
SUSI
MUll
DIVI
MOVI
ASSI
NEGI
CMPI
FLOORli
TRUNCIi
ROUNDfi
MOVFL
MOVLF
MOVil
LFSR
SFSR
SORTI
MACI
Operand 1
Class
Operand 2
Class
Operand 1
Issued
Operand 2
Issued
read.!
read.!
read.1
read.1
read.1
read.!
read.!
read.!
read.!
read.1
read.!
read.F
read.L
read.i
read.D
rmw.1
rmw.1
rmw.1
rmw.!
write. I
write.1
write.!
read.1
write.i
write.i
write.i
write.L
write.F
write.!
I
I
I
I
I
I
I
I
I
I
I
F
L
i
D
I
I
I
I
N/A
write.D
write.1
read.!
N/A
read.!
read.!
N/A
I
I
N/A
N/A
N/A
Returned Value
flo Op. 2
Ito Op. 2
Ito Op. 2
ItoOp.2
ItoOp.2
Ito Op. 2
Ito Op. 2
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
LtoOp.2
FtoOp.2
flo Op. 2
I
N/A
DtoOp.2
ItoOp.2
ItoLl/Fl
PSRBits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
none
none
·
N
0
......
Z
en
w
N
U1
CD
0
N•
U1
......
Z
en
w
N
U1
CD
0
·
w
0
D = Double Word
i = Integer size (B, W, D) specified in mnemonic.
f = Floating,Point type (F, l) specified in mnemonic.
NtA = Not Applicable to this instruction.
READ AND DECODE
ID AND OPERATION WORD
(BUS STATUS=IIIII)
READ OPERAND
(BUS STATUS = 11101)
•
Pulse Active
FSSR for 1 clock
(TRAP or CmPf)
y
Pulse Active
SDN for
1 clock (DONE)
TLfEEf9421-14
FIGURE 3-8. 32-Bit General Slave Instruction Protocol
3-145
o
'?
o
CO
II)
C'I
C")
tn
Z
.....
~
~
C'I
&J
z
~
CO
~
C")
tn
Z
r-------------------------------------------------------------------------~
3.0 Functional Description
(Continued)
3.5.2 Pipellned Slave Protocol Sequence
The NS32532 can communicate with the FPC using the
pipelined Slave Protocol. In the pipelined slave protocol, the
CPU proceeds to the next floating-point instruction if the
destination of the current floating-point instruction is a register, without waiting for SDN signal. The FPC from the other
end can receive new instructions before the end of the previous instruction. The FPC can internally store up to five
new instructions, with up to 10 single- or double-precision
operands. The CPU saves the PC of the floating-point instructions in the Floating-Point Instruction FIFO (FIF).
If exception occurs, the floating·point instruction can be
reexecuted using the PC saved in the FIF (if exception occurs the CPU will flush the FIF and the FPC will flush the
instruction and the operand's FIFOs).
31
2
4
5
6
CPU sends ID and Opcode of MULF
instruction.
Slave starts execution of MULF
instruction.
B
Slave pulses SDN or FSSR for the DIVF
instruction. if TRAP occurred, the rest of
the instructions will be aborted.
9
10
11
12
13
L BIT:
The L bit is set to "1" if the operands in CMPf
operation are "Unordered" (i.e., one of them is
NaN). If ROE bit is cleared, the L bit is always
cleared by the FPC.
Q BIT:
The Q bit is set to "1" if TRAP occurred. The T bit
will distinguish between TRAP(UND) and
TRAP(FPU).
The T bit is set to "1" if the TRAP is TRAP(UND)
and "0" if the TRAP is TRAP(FPU). The CPU examines this bit whenever TRAP occurs.
Floating-Point Instructions that ended without exception will
signal done by pulsing the SDN line for one clock cycle. The
CPU will read the result from the FPC if the destination is
memory. The CPU can try to read the result immediately
after detecting the SDN signal. Therefore, the DONE must
be signaled after loading the result to the FPC. To read the
result the CPU uses the Read from FPC cycle as shown in
Figure 3-4. Upon detecting an exceptional condition in executing a floating point instruction, the FPC requests a TRAP
by pulsing the FSSR line for one clock cycle. In addition, it
sets the Q bit in the status word register. The CPU responds
by reading the status word register while applying status
h'1 E (transferring status word) on the status lines. A
trapped instruction returns no result (also if the destination
is FPC register) and does not affect the CPU PSR.
The FPC displays the reason for the TRAP(FPU) in the
TRAP TYPE (TT) field of the FSR. If the CPU sends FPC ID
with illegal opcode, the FPC generates TRAP(UND) by signaling TRAP and setting the T bit in the status word register.
The n field in the FSR will be set to Illegal Instruction
(h'100). POLYf, DOTl, SREMf, SCALBf, LOGBf and all the
unused opcodes in formats 11 and 12 will cause a
TRAP(UND).
CPU sends ID and Opcode of ADDF
instruction.
7
The Z bit is set to "1" if the second operand is
equal to the first operand. Otherwise, it is set to
3.5.4 Termination of Instruction (Not Including CMPf)
Action
CPU sends ID and Opcode of DIVF
instruction.
Slave starts execution of ADDF
instruction.
ID(h'1F)
Z BIT:
T BIT:
Slave starts execution of DIVF instruction.
ID(h'1F)
0
"0".
OP(h'1D) CPU sends operand (RO).
3
7
FIGURE 3-9. FPC Status Word Format (SWR)
O(RO), F1
F2, F3
F4, F5
Step Status
1 ID(h'1F)
15
Status Bits
N BIT: The N bit is set to "1" if the second operand is less
than the first operand. Otherwise, it is set to "0".
The FPC-FPDP can start execution of a new floating-point
instruction every two CPU clock cycles.
In the following example three floating-point instructions are
being pipelined:
DIVF
ADDF
MULF
23
1000000001 000000001 Toooooool NZOOOLOQI
ST(h'1E) CPU Reads Status Word (if TRAP was
signaled).
Slave pulses SDN or FSSR for the ADDF
instruction. If TRAP occurred, the rest of
the instructions will be aborted.
3.5.5 Byte Sex
The FPC supports the VME or 32000 bus, depending on the
state of the BS pin. In 32000 mode (BS = "0"), the FPC is
ready to receive the less significant half of a double-precision operand first and the more significant half afterward. In
VME mode (BS = "1 "), the FPC is ready to receive the
more significant half of a double-precision operand first and
the less significant half afterward. The FPC will send the
received operands to the correct destination registers inside
the FPDP. In VME mode, the user must swap the data bus
between the CPU and FPC. Byte 0 in the CPU should be
connected to Byte 3 in the FPC, Byte 1 in the CPU should
be connected to Byte 2 in the FPC, byte 2 in the CPU should
be connected to Byte 1 in the FPC and Byte 3 in the CPU
should be connected to Byte 0 in the FPC. The BS line is
sampled by the FPC during Reset only.
ST(h'1E) CPU Reads Status Word (if TRAP was
signaled).
Slave pulses SDN or FSSR for the MULF
instruction.
ST (h'1E) CPU Reads Status Word (if TRAP was
signaled).
3.5.3 Status Word Register
There is a Status Word Register (SWR) that holds the com·
pare results and an exception flag, which indicates TRAP.
This register can be read by the CPU by applying status
code h'1 E (read slave status) on the status line and SPC as
a timing signal. The FPC updates the status word register
after a compare float instruction or if TRAP has occurred.
The content of SWR is valid only after the FPC signals
FSSR.
3-146
Z
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3.0 Functional Description (Continued)
The FPDP is capable of supporting 32-bit and 64-bit IEEE
floating-point operations. The FPDP consists of a Multiplier,
ALU, Divide/Sqrt unit, 32 x 64-bit, Six-Port Register file, I/O
port and control unit. There are six major internal 64-bit wide
data buses used for data transfers between the different
blocks inside the FPDP.
Using six data buses allows an input of two double-precision
operands to a selected unit and to output one double-precision result in one WCLK cycle, supporting pipelining of a
new double-precision instruction every WCLK cycle. (WCLK
is half the frequency of BCLK.)
Data Bus
D7-DO
D7-DO
D15-D8
CPU
D15-D8
FPC
D23-D16
D23-D16
D31-D24
D31-D24
32000 Mode
3.6.1 ContrOlling the FPDP
The FPC controls the FPDP on an instruction by instruction
basis and not clock by clock. The instruction's control signals are delayed in the FPDP to match the pipeline stages
inside the FPDP.
Data Bus
D7-DO
D31-D24
D15-D8
CPU
D23-D16
FPC
D23-D16
This allows the specifying of all the controls for a Reg to
Reg instruction in a single control word. There are two types
of operations that can be executed concurrently on the
FPDP. The first operation is a floating-paint arithmetic operation done on operands from the register file. The second
operation is a Load/Store operation using the X port of the
FPDP.
D15-D8
D31-D24
D7-DO
VMEMode
FIGURE 3-10. Byte Sex Connection Diagrams
3.5.6 Floating-Point Protocols
Table 3-2 gives the protocols followed for each floatingpoint instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Section 2.2.3.
3.6.2 Instruction Control
The FPC controls the FPDP using a 33-bit control word. The
control word contains all the information needed for the execution of an instruction including the function to be executed, source operands and destination of the result. The controls are pipelined along with the instruction and affect the
operation at the appropriate times. The control word is sampled with the riSing edge of the WCLK (system clock divided
by two).
There are three functional fields in the control word:
The Operand Class columns give the Access Classes for
each general operand, defining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Reference Manual).
The Operand Issued columns show the sizes of the operands issued to the Floating·Point Controller by the CPU.
"D" indicates a 32-bit Double Word. "i" indicates that the
instruction specifies an integer size for the operand (B =
Byte, W = Word, D = Double Word). "f" indicates that the
instruction specifies a floating-point size for the operand
(F = 32-bit Standard Floating, L = 64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the FPC Status Word (Figure 3-9).
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified, because the Floating-Point Registers are physically in the
Floating-Point Data Path and are therefore available without
CPU assistance.
1. The FUNC bits define the arithmetic operation to be executed.
2. The MIN, ABIN, MAIN, MBIN, A ADD, B ADD, C ADD,
D ADD bits specify the source and destination for arithmetic operation. Both C ADD and D ADD fields of the
FPDP are connected to the D ADD field in the FPC control (C) word.
3. The E/F ADD and XCNT control the Load and Store
operations.
FUNC, AAIN, ABIN, MAIN, MBIN Fields
The five-bit FUNC field specifies the arithmetic operation to
be executed. The MAIN and AAIN control the muxes on the
A inputs to the MULT and ALU respectively. MBIN and ABIN
control the muxes on the B inputs to the MULT and ALU.
Aain, Main: A = "1", X = "0"
Abin, Mbin: B = "1", Y = "0"
3.6 FPDP INTERFACE
The FPC uses the Weitek WTL 3164 Floating-Point Data
Path (FPDP) as the computational unit.
5
FUNC
MIN
ABIN
MAIN
MBIN
5
5
5
5
5
4
AADD
BADD
CADD
DADD
E/FADD
XCNT
C41
C4
FIGURE 3-11. FPDP Control Word
3-147
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U1
CD
.
o
N
~
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U1
CD
o
~
o
3.0 Functional Description (Continued)
A BUS
A BUS
lMIJ:
fA""YXl
r-r-xl
~
~
1
1
64
64
A
B
A
MULTIPLIER
ALU
TL/EE/9421-15
FIGURE 3·12. FPDP Multiplier and ALU Bus Control
XCNTField
The XCNT field specifies the I/O operation to be executed.
Code
Operation
Description
H'O
NOP
No Operation
H'1
EREG LS -
XPAD
Transfer the Less Significant half of the register
specified by EREG to the X-port (Store LS).
H'2
EREG MS -
XPAD
Transfer the More Significant half of the register
specified by EREG to the X-port (Store MS).
H'3
EREG INT -
XPAD
Transfer Integer operand in the register
specified by EREG to the X-port (Store Int).
H'5
XPAD -
XREG/FREG LS
Load the Less Significant half of the data in the
X-port into the XREG LS and into the register
specified by FREG.
H'6
XPAD -
XREG/FREG MS
Load the More Significant half of the data in the
X-port into the XREG MS and into the register
specified by FREG.
H'?
XPAD -
XREG/FREGINT
Load the Integer operand in X-port into the
XREG and into the register specified by FREG.
Data from FPC is transferred to the FPDP through the XPAD
(32-bit 1/0 Port). The data is loaded into the XREG and into
a register in the register file specified by the ElF ADD.
When using the "Three cycle latency" the Divide/Sqrt block
uses the same clock as the FPDP (can not use the 2X
clock). Although the "Three cycle latency" is not optimized
for double-precision multiply it may be very useful if the system speed divided by two (WCLK output from FPC) is faster
than the FPDP speed rating.
Loading the data to both locations allows the immediate use
of the data by the ALU and MULT, bypassing the register
file. Loading the data to register in the register file prevents
data from being lost if the data from memory is needed a
few cycles later.
The FPC has a pin to specify the desired mode. In "Three
cycle latency" the LMODE pin should be connected to Vee
and in "Two cycle latency" it should be connected to GND.
The LMODE line is sampled during reset. After reset, as part
of the initialization cycle, the FPC updates the Multiply Latency bit in the FPDP control register SRO bit-? (0 = "Two
cycle latency", 1 = "Three cycle latency").
The FPDP 1/0 Mode is determined by the control bits in the
control register SR1 bits 4-0. The FPDP is being used in
Undelayed Single-Pump mode (code 00000).
3.6.3 "2 Cycle Mode" and "3 Cycle Mode"
The FPDP has two timing modes, "Two cycle latency" and
"Three cycle latency". In "Two cycle latency" single- and
double-precision operations have latency of two cycles. In
"Three cycle latency", double-precision multiply has a three
cycle latency, single-precision multiplies and single- or double-precision ALU operations have latency of two cycles.
In "Three cycle latency" Divide/Sqrt block uses the DCLK3
(same as WCLK), in "Two cycle latency" it uses the DCLK2
(2 X WCLK). FPC uses the latency pin to determine the
length of some instructions (number of cycles before FPC
can Signal DONE or TRAP).
This feature allows the CPU to run at more than twice the
maximum FPDP speed.
3-148
3.0 Functional Description (Continued)
Multiply Latency SRO Bit-7
WCLK
WCLK
FPDPSpeed
Max System
"Two Cycle "Three Cycle
Grade
Speed
Latency"
Latency"
120 ns
100 ns
80ns
60ns
120 ns
100 ns
80 ns
60ns
90ns
75ns
60ns
50ns
The FPDP has two multiply latency modes: Two cycle latency mode and Three cycle latency mode. (See separate paragraph on Latency Modes.)
SRO Blt-7
Latency Mode
Two Cycle Latency Mode
o
Three Cycle Latency Mode
45ns
38ns
30ns
25ns
I/O Mode SRl Bits 4-0
3.6.4 FPDP Mode Control Registers SRO, SRl
00000
There are few options in the FPDP like Rounding, I/O, IEEE
handling, Latency and other options that can be controlled
by writing into the control registers SRO and SR1.
The FPDP is being used in the undelayed single-pump
mode for load and store operations.
After reset and whenever the user changes the relevant
fields in the FSR, the FPC updates the FPDP control registers.
"1"
FpexDelay SRl Bit-5
"1"
"1" Set to Fast mode. An underflowed instruction with disabled underflow exception delivers zero to the destination
register.
3.6.5 IEEE Enables Register SR2
SRO
Blt-2
SRO
Bit-1
0
0
Round toward nearest value, if tie round
toward even significant
0
1
Round toward zero
1
0
Round toward positive infinity
The SR2 register has enable bits for each of the exception
conditions. The FPC updates the enable bits after Reset
and whenever the user changes the relevant bits in the
FSR. (See LFSR Instruction.)
Rounding Mode
7
EN~:~ES
Round toward negative infinity
The NaN bit is affected by the ROE bit in the FSR. If the
ROE is cleared then NaN should be enabled (signal exception upon detection of NaN). If ROE is set NaN will be disabled.
Internal abort off.
"0"
The Dnrm bit is always enabled and detection of Dnrm as
operand for operation will cause source exception.
lIokOn SRO Blt-5
Disables Interlocks.
Whenever the user changes the enable bit in the FSR, the
same bit will be updated in the exception enable register in
the FPDP.
FpexStlcky SRO Blt-6
"0"
I NaN Iinv I Dvz I Dnrm I Ovl I Unf Iinx IIOVf I
FPC updates the Inv, Dvz, Ovl and lovl, Unf, Inx enable bits
to reflect those enable bits in the FSR.
SROBlt-4
"0"
0
FIGURE 3-13. IEEE Enables Register (FPDP)
IntAbortOn SRO Blt-3
"0"
Enables bypaSSing of operands between
instructions.
SRl Bit-7
"Oil
Rounding
1
Delayed FPEX- Mode.
BypassOn SRl Bit-6
Fast/IEEE Mode SRO bit 0
1
Single-Pump Undelayed
FPEX is "Pulsed". In this mode, FPEX is asserted
for one clock cycle.
Registers SR3-SRll are not used by the FPC.
3.6.5.1 FPDP Status Lines (S3-S0)
The status of operation in the FPDP can be obtained by
using the FPDP status lines (S3-S1). The status is not
"sticky", therefore, the FPC has to sample the status lines
in the correct timing. If ALU and MULT instructions end in
the same cycle, the ALU status is valid at the end of the
cycle and the MULT status is valid at the beginning of the
following cycle.
CODE
[EJ
m
ALU
MUL
ALU
NUL
1][11][1 ~ ~
S 3-0
FIGURE 3-14. FPDP Status Timing
3-149
TUEE19421-16
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3.0 Functional Description (Continued)
3.6.6 FPC-FPDP Clocks
FPC runs off BCLK and BCLK, which is generated by the
CPU. FPDP uses two clock signals, one clock signal for
most of the chip and a special clock for the Divide unit. Both
FPDP clock signals are supplied by the FPC.
3.6.6.2 FPDP Main Clock (WCLK)
The FPDP uses a TTL level clock supplied by the FPC. The
FPC generates the WCLK by dividing the BCLK by two. All
the FPDP control Signal times are specified relative to the
rising edge of the WCLK.
3.6.6.1 FPC Clock
The FPC uses the system clocks (BCLK and BCLK) generated by the NS32532. All the timing for Signals between the
CPU and the FPC are referenced to the BCLK. BCLK is a
30 MHz, TTL level clock (for timing characteristics refer to
the timing chapter).
3.6.6.3 Divide/Sqrt Unit Clock (DIVCLK)
The Divide/Sqrt unit in "Two cycle latency" mode uses a
clock signal that is twice the WCLK (DCLK2). If the FPDP is
in "three cycle latency", the Divide/Sqrt unit uses a clock
signal that has the same frequency as WCLK (DCLK3). The
FPC generates the correct DCLK automatically using the
LMODE pin.
co
Lt)
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C')
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z
WCLK
TL/EE/9421-17
FIGURE 3-15. Dlvide/Sqrt Clock DCLK2/DCLK3
4.0 Device Specifications
A
CPU RESET
DATA
SO-S3
RST
~
00-031
5-BIT
5/
MIN
...1\
STO-ST4
-y
ABIN
MAIN
MBIN
5
BADDO-BADD4
CONTROL
CADDO-CADD4
SPC
+--
SON
EFDDO-EFDD4
FSSR
XCNTO-XCNT3
WABORT
CLOCKING {
I/o
CONTROL
MULTIPLY CONTROL
BCLK
5
/
5
,1..4
5
4
1
WCLK
BCLK
FPDP
CONTROL
C BUS
5
MDDO-MOD4
{
FPDP
)
v DATA BUS
'I
NS32580
~~~~
AND
I\.
XO-X31
FO-F4
CPU STATUS
FPDP STATUS
;
DIVCLK
}
FPDP
CLOCKING
BS
LMODE
TLlEE/9421-1 B
FIGURE 4-1. NS32580 Interface Signals
3-150
z
en
w
4.0 Device Specifications (Continued)
4.1 NS32580 PIN DESCRIPTIONS
Descriptions of the NS325BO pins are given in the following
sections. Figure 4-1 shows the NS325BO interface signals
grouped according to related functions.
4.1.1 Supplies
VCCL 1-7
VCCBl-8
GNDLl-13
GNDBl-13
AADDO-AADD4 A Read Port Register AddressChooses the inputs to the A bus of the
FPDP.
ALU A Input Select-Controls the A inAAIN
put multiplexers of the FPDP ALU.
ALU B Input Select-Controls the BinABIN
put multiplexers of the FPDP ALU.
BADDO-BADD4 B Read Port Register AddressChooses the inputs to the B bus of the
FPDP.
CADDO-CADD4 C Write Port Register Address-C/O
Bus Control. Chooses the destinations of
C and D buses. These signals should be
connected to both the (CADDO-CADD4)
and the (DADDO-DADD4) lines of the
FPDP.
Logic Power- + 5V positive supplies for
on-chip logic.
Buffers Power-+5V positive supplies
for on·chip buffers.
Logic Ground-Ground references for
on·chip logic.
Buffers Ground-Ground references for
on-chip buffers.
4.1.2 Input Signals
BCLK
Bus Clock-Input clock for CPU bus timing; NS32532 system clock.
Bus Clock Inverse-Inverted input clock
from NS32532.
BS
Byte Sex-Specifies the 110 byte ordering of the FPC. If connected to GND the
FPC is in 32000 mode. If connected to
Vee the FPC is in VME mode. The BS line
must be valid during and after Reset. See
Section 3.6.5.
LMODE
Latency Mode-Specifies the latency
mode of the FPC-FPDP. If connected to
GND the FPC-FPDP is in the "Two cycle
latency", if connected to Vee the FPCFPDP is in the "Three cycle latency".
LMODE line must be valid during and af·
ter Reset.
Reset-Active low. Resets the last operation, clears the FIFOs and the FSR register to its default state.
SO-S3
FPDP Status-Indicates any exceptions
or conditions that resulted from opera·
tions performed by the WTL 3164 floating-point data path.
Slave Processor Control-Active low.
Data strobe for slave transfers between
the CPU and the FPC.
STO-ST4
CPU Status-Bus cycle status code from
CPU. STO is the least significant and
rightmost bit.
1 1 1 0 0 -Reserved
1 1 1 01 -Transferring Operand
1 1 1 1 0 -Reading Status Word
1 1 1 1 1 -Broadcasting Slave ID
4.1.3 Output Signals
DIVCLK
Divide/Square Root Clock-Clock signal for the Divide/Sqrt unit in the FPDP.
EFDDO-EFDD4 E and/or F Port Register AddressChooses the source and destination for
the Load/Store operations of the FPDP.
FO-F4
Function Code-Specifies the operation
to be performed by the FPDP.
Forced Slave Status Read-Active low.
When active, indicates that the slave
status word should be read by the CPU. It
is floating before and after being active.
MAIN
Multiplier A Input Select-Controls the
A input multiplexers of the multiplier of
the FPDP.
Multiplier B Input Select-Controls the
MBIN
B input multiplexers of the multiplier of
the FPDP.
Slave Done-Active low. When active,
indicates successful completion by the
FPC-FPDP of a floating-point instruction.
It is floating before and after being active.
FPDP Abort-Aborts the current and
WABORT
previous instructions in the FPDP.
FPDP Clock-Clock signal for the FPDP.
WCLK
It is BCLK divided by two. i.e., if BCLK is
30 MHz, WCLK will be 15 MHz.
XCNTO-XCNT3 X Port Control-They are the Load/
Store controls for the FPDP.
4.1.4 Input/Output Signals
00-031
CPU Data Bus-Data bus between FPC
and the CPU.
XO-X31
FPDP Data Bus-Data bus between FPC
and the FPDP X port.
3-151
N
UI
co
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N
o
Z
(f)
W
N
UI
co
oI
N
UI
Z
en
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N
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co
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W
o
•
or-----------------------------------------------------------~
~
CD
4.0 Device Specifications (Continued)
~
Z
.....
In
~
Connection Diagram
R
p
CD
N
~
M
~
z
~
L
K
CD
J
~
~
H
z
G
r
E
D
C
B
A
@@@@@@@@@@@@@
@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
NS32580
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@
@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@
D@@@@@@@@@@@@@
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15
Tl/EE/9421-31
Bottom View
FIGURE 4-2. 172-Pln PGA Package
Order Number NS32580-20. NS32580-25 or NS3258D-30
See NS Package Number U172B
3-152
z
en
w
4.0 Device Specifications (Continued)
Dese
VCCL1
GND91
GNDL1
XCNTO
XCNT3
EFADD1
EFADD2
GNDL2
GND92
CADDO
CADD2
CADD3
9ADDO
GND93
GNDL3
XO
XCNT1
XCNT2
EFADDO
EFADD3
9CLK
WCLK
DIVCLK
EFADD4
CADD1
CADD4
9ADD1
9ADD2
VCC91
X2
X1
VCCL2
D1
DO
NC
GNDL4
GND94
9CLK
RST
NC
9ADD3
AADDO
9ADD4
Note: NC
~
Pin
A2
A3
A4
A5
A6
A7
AB
A9
A10
A11
A12
A13
A14
91
92
93
94
95
96
97
9B
99
910
911
912
913
914
915
C1
C2
C3
C4
C5
C6
C7
CB
C9
C10
C11
C12
C13
C14
C15
Dese
X3
X4
NC
D2
D17
D16
NC
GNDL5
NC
NC
NC
VCC92
D15
AADD1
AADD2
X5
X7
D1B
D3
D31
D14
AADD3
AADD4
X6
X9
D19
VCCL3
D30
VCC93
MAIN
M91N
XB
X10
D4
D20
D13
D29
AAIN
A91N
X11
X12
NC
D5
I\)
NS32580 Pinout Descriptions
Pin
Dese
D1
D2B
D2
GND95
D3
FO
D4
F1
D5
X13
D6
X15
D7
GND96
DB
D21
D9
D12
D10
D27
D11
F2
D12
F3
D13
X14
D14
X17
D15
D6
E1
D22
E2
D11
E3
NC
E4
SO
E12
F4
E13
X16
E14
X1B
E15
D7
F1
D23
F2
SPC
F3
SDN
F4
S2
F12
S1
F13
X19
F14
Reserved
F15
VCCL4
G1
DB
G2
GNDB7
G3
D26
G4
GNDL6
G12
VCCB4
G13
NC
G14
STO
G15
ST1
H1
NC
H2
GNDL7
H3
WABORT
H4
S3
No Connection
3-153
U1
co
Pin
H12
H13
H14
H15
J1
J2
J3
J4
J12
J13
J14
J15
K1
K2
K3
K4
K12
K13
K14
K15
L1
L2
L3
L4
L12
L13
L14
L15
M1
M2
M3
M4
M5
M6
M7
MB
M9
M10
M11
M12
M13
M14
M15
Dese
VCCL5
GNDBB
Reserved
D24
D25
D9
D10
NC
VCCB5
ST2
ST4
FSSR
GNDB9
VCCB6
GNDLB
GNDL9
VCCL6
X21
X23
X25
X26
X28
X31
X30
BS
ST3
VCCB7
GNDB10
GNDL10
GNDB11
GNDB12
GNDL11
VCCL7
X20
X22
X24
X27
X29
LMODE
GND913
GNDL12
VCC9B
GNDL13
Pin
N1
N2
N3
N4
N5
N6
N7
NB
N9
N10
N11
N12
N13
N14
N15
P1
P2
P3
P4
P5
P6
P7
PB
P9
P10
P11
P12
P13
P14
P15
R2
R3
R4
R5
R6
R7
RB
R9
R10
R11
R12
R13
R14
o
I
I\)
o
.....
z
en
w
I\)
U1
co
oI
I\)
U1
.....
z
en
w
I\)
U1
co
o
W
o
I
oCO)
oCO
4.0 Device Specifications (Continued)
N
4.2 ABSOLUTE MAXIMUM RATINGS
Power Dissipation
(J)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O·Cto +70·C
-65·C to + 150·C
Storage Temperature
ESD Rating is to be determined.
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
II)
CO)
Z
......
II)
.
N
o
CO
II)
N
CO)
(J)
Z
......
o
~
o
CO
II)
N
CO)
(J)
Z
All Input or Output Voltages
with Respect to GND
1.5W
-0.5Vto +7V
4.3 ELECTRICAL CHARACTERISTICS TA = O·Cto 70·C, Vee = 5V ±10%, GND = OV
Max
Units
VIH
Symbol
High Level Input Voltage
2.0
Vee + 0.5
V
VIL
Low Level Input Voltage
-0.5
0.8
V
VOH
High Level Output Voltage
Parameter
Conditions
Min
IOH = -400 p.A
Typ
V
2.4
0.4
V
300
mA
VOL
Low Level Output Voltage
IOL = 2mA
II
Input Load Current
0:0: VIN:O: Vee
IL
Leakage Current
(Output and I/O Pins in
TRI-STATE®/Input Mode)
0.4 :0: VOUT :0: 2.4V
Icc
Active Supply Current
lOUT = 0, TA = 25·C
CIN
Input Capacitance
pF
COUT
Output Capacitance
pF
4.4 SWITCHING CHARACTERISTICS
ABBREVIATIONS
L.E. - Leading Edge
T.E. - Trailing Edge
4.4.1 Definitions
All the Timing Specifications given in this section refer to
0.8V and 2.0V on all the input and output signals as illustrated in Figures 4.2 and 4.3, unless specifically stated otherwise.
ClK
[)
ClK
SlG2
O.SV
[
[
~K=
[
o.sv
2.0V
SlG1
----2.4V
SIG1
R.E. - Rising Edge
F.E. - Falling Edge
1SIG11
I
tSIG2h
\
O.SV
O.45V
SIG2
2.4V
j~
[
[
.w~
2.0V
I
--2.4V
1SIG11
O.45V
2.4V
tSlG2h
-------O.45V
TLlEE/9421-20
FIGURE 4-4. Timing Specification Standard
(Signal Valid before Clock Edge)
---------O.45V
Tl/EE/9421-19
FIGURE 4-3. Timing Specification Standard
(Signal Valid after Clock Edge)
3-154
z
en
Co)
4.0 Device Specifications (Continued)
~
.
UI
4.4.2 Timing Tables Maximum times assume temperature range O'C to 70'C
OC)
o
~
o
.....
4.4.2.1 Output Signal Propagation Delays Maximum times assume capacitive loading of 100 pF
Symbol Figure
Description
Reference!
Conditions
NS32580·20
NS32580·25
NS32580·30
Min
Min
Min
35
tDv
4·8
CPU Data Valid
After R.E., BCLK T2
tDoh
4·8
CPU Data Hold
After R.E., BCLK Next T1 ITi
Max
Max
23
27
2
2
2
Units
z
en
Co)
ns
UI
Max
~
ns
tDnf
4·8
CPU Data Not Floating
After R.E., BCLK Next T1 ITi
28
23
19
ns
tSDa
4·10
SDN Signal Active
After R.E., BCLK
35
28
22
ns
tSDia
4·10
SDN Signal Inactive
After R.E., Next BCLK
tSDnf
4·10
SDN Signal Not Floating
After R.E., BCLK
25
20
17
ns
tFSSRa
4·11
FSSR Signal Active
After R.E., BCLK
35
28
22
ns
tFSSRia
4·11
FSSR Signal Inactive
After R.E., Next BCLK
tFSSRnf
4·11
FSSR Signal Not Floating After R.E., BCLK
25
20
17
ns
tCv
4·14
C Bus and
WABORTValid
After R.E., WCLK
83
63
50
ns
tCh
4·14
CBUSand
WABORT Hold Time
After R.E., WCLK
tXLv
4·14
FPDP Data Valid
After R.E., WCLK
tXLh
4·14
FPDP Data Hold Time
After R.E., WCLK
2
2
2
ns
tD2p
4·13
DCLK2 Period
From 1.5V R.E., to 1.5V R.E.
50
40
33.3
ns
tD2h
4·13
DCLK2 High Time
From 1.5V R.E., to 1.5V F.E.
22
17
14.5
ns
tD21
4·13
DCLK2 Low Time
From 1.5V F.E. to 1.5V R.E.
22
17
14.5
ns
tD3p
4·13
DCLK3 Period
From 1.5V R.E., to 1.5V R.E.
100
80
66.6
ns
tD3h
4·13
DCLK3 High Time
From 1.5V R.E., to 1.5V F.E.
45
36
30
ns
2
2
2
2
2
ns
2
2
83
63
50
4·13
DCLK3 Low Time
From 1.5V F.E., to 1.5V R.E.
45
36
30
ns
4·13
WCLKPeriod
From 1.5V R.E., to 1.5V R.E.
100
80
66.6
ns
tWCLKh
4·13
WCLK High Time
From 1.5V R.E., to 1.5V F.E.
45
36
30
ns
tWCLKI
4·13
WCLK Low Time
From 1.5V F.E. to 1.5V R.E.
45
36
30
ns
tDWd
4·13
DCLK2/DCLK3 to
WCLKDelay
From 1.5V R.E., to 1.5V R.E.
tWr
4·13
FPDP Clock Rise Time
From O.4V R.E., to 2.4V R.E.
2
tWf
4·13
FPDP Clock Fall Time
From 2.4V F.E. to O.4V F.E.
2
2.5
8
ns
2
2
ns
2
2
ns
8
2.5
4.4.2.2 Input Signal Requirements NS32580-20, NS32580-25, NS32580-30
Symbol Figure
Description
Reference/
Conditions
NS32580·20
NS32580·25
NS32580·30
Units
Min
Max
Min
Max
Min
Max
50
100
40
100
33.3
100
ns
ns
tBCp
4·5
BCLKPeriod
tBCh
4·5
BCLK High Time At 2.0V on BCLK (Both Edges)
0.5tBCp
-5
0.5tBCp
-4
0.5tBCp
-3
tBCI
4·5
BCLK Low Time
At 0.8V on BCLK (Both Edges)
0.5 tBCp
-5
0.5 tBCp
-4
0.5tBCp
-3
tBCr
4·5
BCLK Rise Time 0.8V to 2.0V on R.E., BCLK
5
4
3
tBCI
4·5
BCLK Fall Time
2.0V to 0.8V on F.E., BCLK
5
4
3
ns
tNBCp
4·5
BCLKPeriod
R.E., BCLK to Next R.E., BCLK
33.3
100
ns
tNBCh
4·5
BCLK High Time At 2.0V on BCLK (Both Edges)
0.5tNBCp
-3
120
ns
R.E., BCLK to Next R.E., BLCK
3·155
50
0.5tNBCp
-5
100
40
0.5 tNBCp
-4
100
z
en
Co)
~
UI
OC)
o
W
o
ns
tD31
8
~
.....
ns
tWCLKp
2.5
o
UI
ns
2
2
.
OC)
•
4.0 Device Specifications (Continued)
4.4.2 Timing Tables Maximum times assume temperature range O°C to 70'C (Continued)
4.4.2.2 Input Signal Requirements NS32580-20, NS32580-25, NS32580-30 (Continued)
Symbol Figure
Referencel
Conditions
Description
NS32580-25
NS32580-20
Min
Max
Min
Max
NS32580-30
Units
Min
Max
0.5tNBCp
-3
120
ns
tNBCI
4-5
BCLK Low Time
At 0.8V on BCLK (Both Edges) 0.5tNBCp
-5
tNBCr
4·5
BCLK Rise Time
0.8V to 2.0V on R.E., BCLK
5
4
3
ns
tNBCI
4·5
BCLK Fall Time
2.0V to 0.8V on F.E., BCLK
5
4
3
ns
tBCNBCrf
4·5
Bus Clock Skew
2.0Von R.E., BCLK to
0.8Von F.E., BCLK
-2
+2
-2
+2
-1
+1
ns
tBCNBCfr
4·5
Bus Clock Skew
0.8Von F.E., BCLK to
2.0V on R.E., BCLK
-2
+2
-2
+2
-1
+1
ns
tpWR
4·6
Power Stable to
R.E. ofRST
After Vcc Reaches 4.5V
tRSTs
4·6,4·7 RST Setup Time
4·7
50
40
30
/Ls
Before R.E., BCLK
14
12
11
ns
At 0.8V (Both Edges)
64
64
64
tBCp
tSTs
4·8,4·9 CPU Status Setup Time Before R.E., BCLK T2
36
30
24
24
ns
tSTh
4·8,4·9 CPU Status Hold Time After R.E., BCLK T2
15
12
10
10
ns
tsPCs
4·8,4·9 SPC Setup Time
Before R.E., BCLK T2
30
23
20
20
ns
tSPCh
4·8,4·9 SPC Hold Time
After R.E., BCLK T2
0
tecp
+15
0
tRSTw
RST Pulse Width
0.5tNBCp
-4
tecp
+19
0
tos
4·9
Data Setup Time
Before R.E., BCLK T2
tOh
4·9
Data Hold Time
After R.E., BCLK Next T1 or Ti
tSAs
4·12
FPDP ALU Status
Setup Time
Before R.E., WCLK
tSAh
4·12
FPDP ALU Status
Hold Time
After R.E., WCLK
tSMs
4·12
FPDP Multiplier Status
Setup Time
Before F.E., WCLK
tSMh
4·12
FPDP Multiplier Status
Hold Time
After F.E., WCLK
txSs
4·14
FPDP Data Setup Time Before R.E., WCLK
tXSh
4·14
FPDP Data Hold Time
After R.E., WCLK
BCLK[~
7
5
3
ns
-4
-4
ns
9
9
8
ns
2
2
2
ns
9
9
8
ns
2
2
2
ns
9
9
9
ns
2
2
2
ns
I BCI BCI
-I -
~
fi
IBCp
--I _IBCNBCI,
I~Cr
~INBCI
_IBCr
~
_IBCNBCr!
_INBC!
INBCh~
BCLK[--1
L
I NBCp
TL/EE/9421-21
FIGURE 4-5. Clock Waveforms
3·156
ns
-4
'--==\ ~~
I " " - IBC'
tecp
+12
ztJ)
4.0 Device Specifications (Continued)
c.:I
N
UI
co
o
N
o
......
Z
+ ......
tJ)
BCLK[,_ _
c.:I
N
.
UI
co
o
N
UI
TL/EE/9421-22
FIGURE 4-6_ Power-On Reset
......
Z
tJ)
c.:I
N
UI
BCLK[~JLJUL
J'
RST[..-~\~S~S~~
tRSlW
•
11
t
tRSTS
.
co
o
.1
c.:I
o
r~---TL/EE/9421-23
FIGURE 4-7_ Non-Power-On Reset
ANY
T-STATE
BCLK
[
STO-ST4
[
SPC
[
Tl
T2
T1 OR
n
00-031 [
TLlEE/9421-24
FIGURE 4-8. Read Cycle from FPC
BCLK [
STO-ST4 [
SPC [
00-031 [
TLlEE/9421-25
FIGURE 4-9. Write Cycle to FPC
3-157
•
C)
~
iQ
r---------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
Cf)
en
z
BCLK [
BCLK [
~
SON [
rsSR [
~f8
en
z....
C)
i
TLlEE/9421-26
TL/EE/9421-27
FIGURE 4-10. Slave Processor Done Timing
FIGURE 4·11. FSSR Signal Timing
C'I
~
Z
WCLK [
SO-53 [
TL/EE/9421-26
FIGURE 4-12. FPDP Status Signal Timing
DCLK2 [
DCLK3 [
WCLK [
I.SV
TLlEE/9421-29
FIGURE 4·13. FPDP Clock Signal Timing
WCLK [
C, WABORT [
-.4.--.J{-il----J-----
X(LOAO) [
X(STORE) [
TL/EE/9421-30
FIGURE 4·14. FPDP Output Signal Timing
3-158
z
en
c,)
Appendix A
I\)
en
COMPATIBILITY OF FPC·FPDP WITH NS32081/NS32381
NS32081
NS32381
NS32580
CQ
o
NS32081
INSTRUCTIONS
NS32381
NS32580
NS32081 FSA +
NS32081 FSA +
RMB
AMB
AOE
IVE
DZE
OVE
IOE
ROF
IVF
DZF
OVF
IOF
z
FSR
NS32081 +
NS32081+
DOTf
POLYf
SCALBf
LOGBf
MACf
SOATf
8x64Bit
8x64 Bit
~
o
.......
en
c,)
I\)
en
REGISTERS
8x32Bit
RESERVED OPERANDS
DNRM
DNRM
DNAM
NaN
NaN
NaN can be
enabled or
Disable.
Infinity
Infinity
Infinity is NOT a
reserved
operand.
.
CQ
o
I\)
en
.......
z
en
c,)
I\)
en
CQ
o
~
o
AppendixB
PERFORMANCE ANALYSIS
The execution time is calculated from SPC (T1, T2 included) to SDN (including the SDN pulse)
Latency
reg, reg
2 cycles mode
Latency
reg, reg
3 cycles mode
Throughput
reg, reg
2 cycles mode
ADDfll
13
13
SUBfll
13
13
MULf
MUll
13
13
DIVf
DIV1
Instruction
Throughput
reg, reg
3 cycles mode
Pipe
Break
2
2
No
2
2
No
13
15
2
2
2
4
No
No
29
43
43
71
Upt029
Up to 43
Up to 43
Upto 71
No
No
No
MOVflI
13
13
2
2
ABSfll
13
13
2
2
No
NEGf/1
13
13
2
2
No
CMPfll
13 + CPU
13 + CPU
-
Yes
-
LFSA
13
13
-
-
SFSA
13 + CPU
13 + CPU
-
-
Yes
MACf
MACI
15
15
15
17
6
6
6
8
No
No
SORTf
SORTI
41
69
65
123
Up to 41
Up to 69
Upt065
Up to 123
No
No
FLOOAfi
13 + CPU
13 + CPU
TRUNCfi
13 + CPU
13 + CPU
AOUNDfi
13 + CPU
13 + CPU
MOVFL
13 + CPU
13 + CPU
MOVLF
13 + CPU
13 + CPU
MOVif
MOVil
17 + CPU
13 + CPU
17 + CPU
13 + CPU
-
3·159
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
•
Appendix B (Continued)
Add the following CPU cycles to the base (reg, reg) number of cycles for the different cases:
Instruction
Latency
2 Cycles Mode
Latency
3 Cycles Mode
Throughput
2 Cycles Mode
0
0+ CPU
0+ CPU
-
Throughput
3 Cycles Mode
Pipe Break
MONADIC FLOAT (One Operand)
mem, reg
reg, mem
mem,mem
0
0+ CPU
0+ CPU
2
-
2
see reg, reg
Yes
Yes
2
see reg, reg
Yes
Yes
-
DYADIC FLOAT (Two Operands)
mem, reg
reg, mem
mem,mem
0
0+ CPU
2 + CPU
0
0+ CPU
2 + CPU
2
-
-
MONADIC LONG (One Operand)
mem, reg
reg, mem
mem,mem
2
2 + CPU
2 + CPU
4
4
2
2 + CPU
2 + CPU
-
2
6 + CPU
6 + CPU
4
4
-
-
-
see reg, reg
Yes
Yes
DYADIC LONG (Two Operands)
mem,reg
reg,mem
mem,mem
2
6 + CPU
6 + CPU
Note: CPU stands for the time it takes the CPU to take the result from the FPC and resume operation.
3-160
-
see reg, reg
Yes
Yes
Section 4
Peripherals
Section 4 Contents
NS32C201-10, NS32C201-15 Timing Control Units.....................................
NS32202-10 Interrupt Control Unit.. ... ..... ..... .... .. .... ....... ...... ...... ........
NS32203-10 Direct Memory Access Controller (DMAC) .................................
4-2
4-3
4-25
4-50
~National
PRELIMINARY
~ Semiconductor
C
.......
z
en
Co)
• 4-bit input (WAITn) allowing precise specification of 0 to
15 wait states
• Cycle Hold for system arbitration and/or memory
refresh
• System timing (FCLK, CTTL) and control (RD, WR, and
DBE) outputs
• General purpose Timing State Output (TSO) that
identifies internal states
• Peripheral cycle to accommodate slower MOS
peripherals
• Provides "ready" (ROY) output for the Series 32000
CPUs
• Synchronous system reset generation from Schmitt
trigger input
• Phase synchronization to a reference signal
• High-speed CMOS technology
• TTL compatible inputs
• Single 5V power supply
• 24-pin dual-in-line package
General Description
The NS32C201 Timing Control Unit (TCU) is a 24-pin device
fabricated using National's microCMOS technology. It provides a two-phase clock, system control logic and cycle extension logic for the Series 32000@ microprocessor family.
The TCU input clock can be provided by either a crystal or
an external clock signal whose frequency is twice the system clock frequency.
In addition to the two-phase clock for the CPU and MMU
(PHI1 and PHI2), it also provides two system clocks for general use within the system (FCLK and CTTL). FCLK is a fast
clock whose frequency is the same as the input clock, while
CTTL is a replica of PHI1 clock.
The system control logic and cycle extension logic make the
TCU very attractive by providing extremely accurate bus
control signals, and allowing extensive control over the bus
cycle timing.
Features
• Oscillator at twice the CPU clock frequency
• 2 phase full Vee swing clock drivers (PHI1 and PHI2)
Block Diagram
XIN
XOUT
FCLK
PHI2
PHil
Wt:::=------.......;;;.;.;===~D---
CTTL
liSTe
T·STATE
COUNTER
& LOGIC
ADS
----~-4_~
RDY
--------1
--------1
WAIU --------1
WAIT2 --------1
twAIT
WAlTa
WAIT1
-------1
o
N
........•
c
NS32C201-10/NS32C201-15 Timing Control Units
DOIN
PER
z
en
Co)
N
WAIT
WAIT
STATE
COUNTER
& LOGIC
TLlEE/8524-1
4-3
N
o
N
C
....
....•
(II
II)
..-•
Table of Contents
C)
N
U
N
1.0 FUNCTIONAL DESCRIPTION
2.0 DEVICE SPECIFICATIONS
C')
1.1 Power and Grounding
Z
.....
1.2 Crystal Oscillator Characteristics
C)
1.3 Clocks
2.1.2 Input Signals
.C)
1.4 Resetting
2.1.3 Output Signals
tn
.
.N
1.5 Synchronizing Two or More TCUs
N
1.6 Bus Cycles
tn
1.7 Bus Cycle Extension
U
C')
Z
2.1 Pin Descriptions
2.1.1 Supplies
2.2 Absolute Maximum Ratings
2.3 Electrical Characteristics
2.4 Switching Characteristics
1.7.1 Normal Wait States
2.4.1 Definitions
1.7.2 Peripheral Cycle
2.4.2 Output Loading
1.7.3 Cycle Hold
2.4.3 Timing Tables
1.8 Bus Cycle Extension Combinations
2.4.4 Timing Diagrams
1.9 Overriding WAIT Wait States
List of Illustrations
Crystal Connection .............................................................................................1·1
PHil and PHI2 Clock Signals .................................................................................... 1·2
Recommended Reset Connections (Non Memory·Managed System) ................................................ 1·3a
Recommended Reset Connections (Memory· Managed System) .................................................... 1·3b
Slave TCU does not use RWEN during Normal Operation .......................................................... 1·4a
Slave TCU Uses Both SYNC and RWEN ......................................................................... 1·4b
Synchronizing Two TCUs ....................................................................................... 1·5
Synchronizing One TCU to an External Pulse ...................................................................... 1·6
Basic TCU Cycle (Fast Cycle) .................................................................................... 1·7
Wait State Insertion Using CWAIT (Fast Cycle) ..................................................................... 1·8
Wait State Insertion Using WAITn (Fast Cycle) ..................................................................... 1·9
Peripheral Cycle ..............................................................................................1·10
Cycle Hold Timing Diagram ..................................................................................... 1·11
Fast Cycle with 12 Wait States .................................................................................. 1·12
Peripheral Cycle with Six Wait States ............................................................................ 1·13
Cycle Hold with Three Wait States ............................................................................... 1·14
Cycle Hold of a Peripheral Cycle ................................................................................ 1·15
Overriding WAITn Wait States .................................................................................. 1·16
Connection Diagram ............................................................................................2·1
Clock Signals (a) ...............................................................................................2·2
Clock Signals (b) ...............................................................................................2·3
Control Inputs .................................................................................................2·4
Control Outputs (Fast Cycle) ..................................................................................... 2·5
Control Outputs (Peripheral Cycle) ............................................................................... 2·6
Control Outputs (TRI·STATE Timing) ............................................................................. 2·7
Cycle Hold .........................................................•..........................................2·8
Wait States (Fast Cycle) ........................................................................................2·9
Wait States (Peripheral Cycle) .................................................................................. 2·10
Synchronization Timing ........................................................................................2·11
4·4
z
(J)
1.0 Functional Description
(0)
~
1.1 POWER AND GROUNDING
The NS32C201 requires a single +5V power supply, applied to pin 24 (Vecl. See Electrical Characteristics. The
Logic Ground on pin 12 (GND), is the common pin for the
TCU.
1.3 CLOCKS
The NS32C201 TCU has four clock output pins. The PHI1
and PHI2 clocks are required by the Series 32000 CPUs.
These clocks are non-overlapping as shown in Figure 1-2.
Z
o
~
PHI1
.
o....
....
en
The NS32C201 has an internal oscillator that requires connections of the crystal and bias components to XIN and
XOUT as shown in Figure 1-1. It is important that the crystal
and the RC components be mounted in close proximity to
the XIN, XOUT and Vee pins to keep printed circuit trace
lengths to an absolute minimum.
Typical Crystal Specifications:
PHI2
TLfEEf8524-4
Type ........................................... At-Cut
Tolerance .............................. 0.005% at 25·C
FIGURE 1.2. PHI1 and PHI2 Clock Signals
Each rising edge of PHI1 defines a transition in the timing
state of the CPU.
As the TCU generates the various clock signals with very
short transition timings, it is recommended that the conductors carrying PHI1 and PHI2 be kept as short as possible. It
is also recommended that only the Series 32000 CPU and, if
used, the MMU (Memory Management Unit) be connected
to the PHI1 and PHI2 clocks.
Stability .......................... 0.01 % from o· to 70·C
Resonance ...................... Fundamental (parallel)
Capacitance .................................... 20 pF
Maximum Series Resistance ........................ 50n
30pF
XOUT
(141
l00kOc::J
XIN
(13)
TLfEEf8524-3
CRYSTAL
FREQUENCY
(MHz)
R
(OHM)
6-12
12-18
18-24
24-30
470
220
100
47
.....
(0)
~
1.2 CRYSTAL OSCILLATOR CHARACTERISTICS
1800
o
....
....o•
(J)
A 0.1 ,..F, ceramic decoupling capacitor must be connected
across Vee and GND, as close to the TCU as possible.
l~c
o
~
CTTL is a clock signal which runs at the same frequency as
PHI1 and is closely balanced with it.
FCLK is a clock, running at the frequency of XIN input. This
clock has a frequency that is twice the CTTL clock frequency. The exact phase relationship between PHI1, PHI2, CTTL
and FLCK can be found in Section 2.
FIGURE 1-1. Crystal Connection Diagram
Vee
NS32C201
NS32C018
CPU
TCU
r-------------,
I
I
I
I
i RESET
l>--l:-+-~_+-_+~+----I RsTi
RsTii I-----.,r------l RSr/ABT
!L _____________ .J:
EXTERNAL ReSET
(OPTIONAL)
2:
III
SOp5eC
RESET SWITCH
SYSTEM RESET
(OPTIONAL)
TLfEEf8524-5
FIGURE 1-3a. Recommended Reset Connections (Non Memory-Managed System)
Vee
NS32C201
TCU
r-------------,
I
: RESET
1>-+1---!:-~_+-_+..",......- - - _ l
I
NS32082
MMU
NS32CoI6
epu
I
RsTi
RsTo
!L _____________ .JI
EXTERNAL RESET
~
(OPTIONAL)
SO,...sec
RESET SWITeH
(OPTIONAL)
TLfEEf8S24-6
FIGURE 1-3b. Recommended Reset Connections (Memory-Managed System)
4-5
....
•
....
o
II)
C'\I
~
en
z
;:;
....
....•
~
C'\I
~
Z
1.0 Functional Description (Continued)
1.4 RESETTING
RWEN/SYNC input to the slave TCU(s) is used for synchronization. The Slave TCU samples the RWEN/SYNC input
on the rising edge of XIN. When RSTO is low and CTTL is
high (see Figure 1-5), if RWEN/SYNC is sampled high, the
phase of CTTL of the Slave TCU is shifted by one XIN clock
cycle .
The NS32C201 TCU provides circuitry to meet the reset
requirements of the Series 32000 CPUs. If the Reset Input
line, RSTI is pulled low, the TCU asserts RSTO which resets
the Series 32000 CPU. This Reset Output may also be used
as a system reset signal. Figure 1-3a illustrates the reset
connections for a non Memory-Managed system. Figure
1-3b illustrates the reset connections for a Memory-Managed system.
Two possible circuits for TCU synchronization are illustrated
in Figures 1-48 and 1-4b. It should be noted that when
RWEN/SYNC is high, the RD and WR signals will be TRISTATE on the slave TCU.
1.5 SYNCHRONIZING TWO OR MORE TCUs
Note: RWEN/SYNC should not be kept constantly high during reset, other-
During reset, (when RSTO is low), one or more TCUs can
be synchronized with a reference (Master) TCU. The
wise the clock will be stopped and the device will not exit reset when RSTI is
deasserted.
RWERISYNC
(Mull Be Low
DuringROMII
TUEE/8524-7
FIGURE 1·4a. Slave TCU Does Not Use RWEN During Normal Operation
R"WENISYNC
(MuotBeLow
DurlngROMII
+-....................+--.r-~
RWEN>-....
TL/EE/8524-8
FIGURE 1·4b. Slave TCU Uses Both SYNC and RWEN
Note: When two or more Teus are to be synchronized, the XIN of all the reus should be connected to an external clock source. For details on the external clock,
see Switching Specifications In Section 2.
XIN
CITL(s) \
RWEN/SYNC
I
I
I
I
I
I
PHASE CHANGE.
t
+
I
\
I
\
\
RSTl~
\
I
I
'--
\~-----------------------FIGURE 1·5. Synchronizing Two TCUs
4-6
TL/EE/8524-9
z
(J)
W
1.0 Functional Description (Continued)
N
o
N
RSTO~LO~W~------------------------------------------------------------------------
.
C
.....
.....
.....
C
XIN
Z
(J)
W
N
\~------------------CTTL(S)~
\'--_--11
RWEN/SYNC _ _ _...J/
TUEE/8524-10
FIGURE 1-6. Synchronizing One TCU to An External Pulse
In addition to synchronizing two or more TCUs, the RWENI
SYNC input can be used to "fix" the phase of one TCU to
an external pulse. The pulse to be used must be high for
only one rising edge of XIN. Independent of CTTL's state at
the XIN rising edge, the CTTL state following the XIN rising
edge will be high. Figure 1-6 shows the timing of this sequence.
ated. In addition to RD and WR, other signals are provided:
DBE and TSO. DBE is used to enable data buffers. The
leading edge of DBE is delayed a half clock period during
Read cycles to avoid bus conflicts between data buffers and
either the CPU or the MMU. This is shown in Figure 1-7.
The Timing State Output (TSO) is a general purpose signal
that may be used by external logic for synchronizing to a
System cycle. TSO is activated at the beginning of state T2
and returns to the high level at the beginning of state T4 of
the CPU cycle. TSO can be used to gate the CWAIT signal
when continuous waits are required. Another application of
TSO is the control of interface circuitry for dynamic RAMs.
1.6 BUS CYCLES
In addition to providing all the necessary clock signals, the
NS32C201 TCU provides bus control signals to the system.
The TCU senses the ADS signal from the CPU or MMU to
start a bus cycle. The DDIN input signal is also sampled to
determine whether a Read or Write cycle is to be generCPU STATES
TeU STATES
11
11
T2
T2
T3
T3
T4
T4
Notes:
PHil
1. The CPU and TCU view some tim·
ing states (T·states) differently.
For clarity, references to T-states
will sometimes be followed by
(TCU) or (CPU). (CPU) also implies (MMU).
ADS
2. Arrows indicate when the TCU
samples the input.
3. RWEN is assumed low (RD and
WR enabled) unless specified differently.
TSO
4. For clarily, T-states for both the
TeU and CPU are shown above
the diagrams. (See Note 1.)
ODIN
Viii
iiii
OBE
ROY
HIGH
TL/EE/8524-11
FIGURE 1-7. Basic TCU Cycle (Fast Cycle)
4-7
o
N
C
.....
.....•
U1
........•
~.-----------------------------------------------------~
~
CO)
en
z
C;
....•
....
o
('II
~
CO)
1.0 Functional Description
(Continued)
1.7 BUS CYCLE EXTENSION
There are three basic cycle extension modes provided by
the TCU, as described below.
The NS32C201 TCU uses the Wait input signals to extend
normal bus cycles. A normal bus cycle consists of four PHI1
clock cycles. Whenever one or more Wait inputs to the TCU
are activated, a bus cycle is extended by at least one PHI1
clock cycle. The purpose is to allow the CPU to access slow
memories or peripherals. The TCU responds to the Wait
signals by pulling the ROY signal low as long as Wait States
are to be inserted in the Bus cycle.
1.7.1 Normal Wait States
This is a normal Wait State insertion mode. It is initiated by
pulling CWAIT or any of the WAITn lines low in the middle of
T2. Figure 1-8 shows the timing diagram of a bus cycle
when CWAIT is sampled high at the end of T1 and low in the
middle of T2.
en
z
CPU STATES
T1
T2
T3.. ....... T3
T3
T4
TCU STATES
T1
T2
TCW ..... TCW
T3
T4
PHI1
TL/EE/8524-12
FIGURE 1·8. Wait State Insertion Using CWAIT (Fast Cycle)
4-8
1.0 Functional Description
z
en
Co)
(Continued)
N
CWAIT is high during the entire bus cycle, then the ROY line
goes low for 1 to 15 clock cycles, depending on the binary
weighted value of WAITn. If, for example, WAIT1 and
WAIT4 are sampled low, then five wait states will be inserted. This is shown in Figure 1-9.
The ROY signal goes low during T2 and remains low until
CWAIT is sampled high by the TCU. ROY is pulled high by
the TCU during the same PHI1 cycle in which the CWAIT
line is sampled high.
If any of the WAITn signals are sampled low during T2 and
CPU STATES
T1
T2
T3
TCU STATES
T1
T2
TW1
T3 .......... T3
TW2.
••• TWn
T3
T4
T3
T4
o
N
........•
c
C
......
z
en
Co)
N
o
N
....C•
....
(II
PHI1
•
TL/EE/8524-13
FIGURE 1-9. Wait State Insertion Using WAITn (Fast Cycle)
4-9
....•
~r-----------------------------------------------------------------------'
~
~
~
z
C;
.
....
....
~
C)
1.0 Functional Description (Continued)
WR signals are also re-shaped so the setup and hold times
for address and data will be increased.
1.7.2 Peripheral Cycle
This cycle is entered when the PER signal line is sampled
low at the beginning of T2. The TCU adds five wait states
identified as TDO-TD4 into a normal bus cycle. The RD and
CPU STATES
TCU STATES
This may be necessary when slower peripherals must be
accessed.
Figure 1-10 shows the timing diagram of a peripheral cycle•
T1
T2
T3
T3
T3
T3
T3
T3
T4
T1
T2
TOO
T01
T02
T03
T04
T3
T4
Cf)
U)
z
PHI1
AOS
TSii
iiiiiN
-....
WR
iiii
OlE
PER
ROY
TL/EE/8524-14
FIGURE 1-10. Peripheral Cycle
4-10
z
1.0 Functional Description
en
w
(Continued)
I\)
1.7.3 Cycle Hold
pulled low, thus causing wait states to be inserted into the
bus cycle. The cycle hold feature can be used in applications involving dynamic RAMs. A timing diagram showing
the cycle hold feature is shown in Figure 1-11.
If the CWAIT input is sampled low at the end of state T1, the
TCU will go into cycle hold mode and stay in this mode for
as long as CWAIT is kept low. During this mode the control
signals RD, WR, T50 and DBE are kept inactive; ROY is
CPU STATES
T1
T2
o
Q
.....
.....,
I\)
Q
.......
Z
T3
f3
T3
en
w
I\)
T4
o
I\)
Q
.....
,
.....
U1
TLlEE/8524-15
FIGURE 1·11. Cycle Hold Timing Diagram
input signal PER is sampled to determine whether a peripheral cycle is requested.
1.8 BUS CYCLE EXTENSION COMBINATIONS
Any combination of the TCU input signals used for extending a bus cycle can be activated at one time. The TCU will
honor all of the requests according to a certain priority
scheme. A cycle hold request is assigned top priority. It follows a peripheral cycle request, and then CWAIT and
WAITn respectively.
If, for example, all the input signals CWAIT, PER and WAITn
are asserted at the beginning of the cycle, the TCU will enter the cycle hold mode. As soon as CWAIT goes high, the
Next, the TCU samples CWAIT again and WAITn to check
whether additional wait states have to be inserted into the
bus cycle. This sampling point depends on whether PER
was sampled high or low. If PER was sarapled high, then the
sampling point will be in the middle of the TCU state T2,
(Figure 1-14), otherwise it will occur three clock cycles later
(Figure 1-15). Figures 1-12 to 1-15 show the timing diagrams for different combinations of cycle extensions.
4-11
........•
0
II)
1.0 Functional Description
(Continued)
IN
0
IN
CPU STATES
(I)
TeU STATES
T1
T2
T3
11112
15,0
10102
10,0
CO)
Z
.....
0
........•
T3
T3 ......... T3
T3
T4
PHil
0
IN
0
IN
CO)
(I)
ADS
Z
TSO
WR
iW
DBE
PER
eWAIT
WAIT1
WAIT2
WAIT4
WAIT8
WAITn
value
sampled
ROY
TLlEE/8524-16
FIGURE 1-12. Fast Cycle With 12 Walt States
(2 CWAIT and WAIT10) (Read Cycle)
4-12
r-----------------------------------------------------------------------,z
1.0 Functional Description
(Continued)
en
Co)
o
~
o
.....
~
CPU STATES
T1
T2
T3
T3
T3
T3
T3 ........ T3
T3
T3
T3
TCU STATES
T1
T2
TOO
T01
T02
TCW
TW1 .... TW5
T03
T04
T3
.....
I
o
.......
Z
en
Co)
PHI1
~
o
o
.....
.....
~
I
CTI
HIGH
lOW
HIGH
lOW
HIGH
WAIfR
value
sampled
ROY
TL/EE/8524-17
FIGURE 1·13. Peripheral Cycle with Six Walt States
(1 CWAIT and WAIT5) (Write Cycle)
4-13
.
.,...
.,...
It)
<:)
1.0 Functional Description
(Continued)
C'II
0
C'II
CPU STATES
Tt
T2
T3
T3
T3
T3
T3
T3
T4
(/)
TCU STATES
11
TH
TH
T2
TCW
TW1
TW2
T3
T4
CO)
Z
.......
.
<:)
.,...
.,...
PHil
<:)
C'II
0
C'II
CO)
ADS
(/)
Z
TSO
WR
iiii
DBE
PER
CWAIT
WAiTt
HIGH
WAIT2
LOW
WAIT4
HIGH
WAIT8
HIGH
WAlTn
ROY
TL/EE/8524-18
FIGURE 1-14. Cycle Hold with Three Wait States
(1 CWAIT and WAIT2) (Read Cycle)
4-14
1.0 Functional Description
CPU STATES
T1
T2
lCU STATES
T1
TH ••
(Continued)
T3
T3
T3
T3
13
T3
T3
13
T4
• TH
T2
TOO
T01
T02
T03
104
T3
T4
z
~
N
o
N
.....
.....•
<:)
<:)
.......
z
en
(,,)
N
oN
<:)
.....
.....•
U1
TL/EE/8524-19
FIGURE 1-15. Cycle Hold of a Peripheral Cycle
1.9 OVERRIDING WAITn WAIT STATES
minate a bus cycle, for example, CWAIT must be asserted
for at least one clock cycle, and the WAITn inputs must be
forced to their inactive state.
The TCU handles the WAITn Wait States by means of an
internal counter that is reloaded with the binary value corresponding to the state of the WAITn inputs each time CWAIT
is sampled low, and is decremented when CWAIT is high.
At least one wait state is always inserted when using this
procedure as a result of CWAIT being sampled low. Figure
1-16 shows the timing diagram of a prematurely terminated
bus cycle where eleven wait states were being inserted.
This allows to either extend a bus cycle of a predefined
number of clock cycles, or prematurely terminate it. To ter-
4-15
....• r-----------------------------------------------------------------------------,
.... 1.0 Functional Description (Continued)
~
~
o
~
tn
Z
......
Q
....•
....
CPU STATES
T1
T2
T3
T3
T3
T3
T3
T4
lCU STATES
T1
T2
TW1
TW2
Twa
TCW
T3
T4
PHI1
Q
3
C'II
C")
tn
Z
iiii
WAITn
value
sampled
00002
ROY
TL/EE/8524-20
FIGURE 1-16. Overriding WAITn Wait States
(Write Cycle)
4-16
z
en
Co)
2.0 Device Specifications
I\)
2.1.3 Output' Signals
2.1 PIN DESCRIPTIONS
The following is a description of all NS32C201 pins. The
descriptions reference portions of the Functional Description. Section 1.
Reset Output (RSTO): Active low. This signal becomes active when RSTI is low, initiating a system reset. RSTO goes
high on the first rising edge of PHI1 after RSTI goes high.
Section 1.4.
Read Strobe (RD): (TRI-STATE) Active low. Identifies a
Read cycle. It is decoded from DDIN and TRI-STATE by
RWEN/SYNC. Section 1.6.
Write Strobe (WR): (TRI-STATE) Active low. Identifies a
Write cycle. It is decoded from DDIN and TRI-STATE by
RWEN/SYNC. Section 1.6.
2.1.1 Supplies
Power (VCc>: +5V positive supply. Section 1.1.
Ground (GND): Power supply return. Section 1.1.
2.1.2 Input Signals
Reset Input (RSTI): Active low. Schmitt triggered, asynchronous signal used to generate a system reset. Section
1.4.
Note: RD and WR are mutually exclusive in any cycle. Hence they are never
low at the same time.
Address Strobe (ADS): Active low. Identifies the first timing
state (Tl) of a bus cycle.
Data Direction Input (ODIN): Active low. Indicates the direction of the data transfer during a bus cycle. Implies a
Read when low and a Write when high.
Data Buffer Enable (DBE): Active low. This signal is used
to control the data bus buffers. It is low when the data buffers are to be enabled. Section 1.6.
Timing State Output (TSO): Active low. The falling edge of
TSO signals the beginning of state T2 of a bus cycle. The
rising edge of TSO signals the beginning of state T4. Section 1.6.
Ready (ROY): Active high. This signal will go low and remain low as long as wait states are to be inserted in a bus
cycle. It is normally connected to the RDY input of the CPU.
Section 1.7.
Fast Clock (FCLK): This is a clock running at the same
frequency as the crystal or the external source. Its frequency is twice that of the CPU clocks. Section 1.3.
CPU Clocks (PHI1 and PHI2): These outputs provide the
Series 32000 CPU with two phase, non-overlapping clock
signals. Their frequency is half that of the crystal or external
source. Section 1.3.
System Clock (CTIL): This is a system version of the PHil
clock. Hence, it operates at the CPU clock frequency. Section 1.3.
Crystal Output (XOUn: This line is used as the return path
for the crystal (if used). It must be left open when an external clock source is used to drive XIN. Section 1.2.
Note: In Rev. A of the NS32C201 this signal is CMOS compatible. In later
revisions it is TTL compatible.
Read/Write Enable and Synchronization (RWEN/
SYNC): TRI-STATE® the RD and the WR outputs when high
and enables them when low. Also used to synchronize the
phase of the TCU clock signals, when two or more TCUs
are used. Section 1.5.
Crystal or External Clock Source (XIN): Input from a crystal or an external clock source. Section 1.3.
Continuous Walt (CWAIT): Active low. Initiates a continuous wait if sampled low in the middle of T2 during a Fast
cycle, or in the middle of TD2, during a peripheral cycle. If
CWAIT is low at the end of Tl, it initiates a Cycle Hold.
Section 1.7.1.
Four-Bit Walt State Inputs (WAIT1, WAIT2, WAIT4 and
WAITS): Active low. These inputs, (collectively called
WAITn), allow from zero to fifteen wait states to be specified. They are binary weighted. Section 1.7.1.
Peripheral Cycle (PER): Active low. If active, causes the
TCU to insert five wait states into a normal bus cycle. It also
causes the Read and Write signals to be re-shaped to meet
the setup and hold timing requirement of slower MOS peripherals. Section 1.7.2.
4-17
o
I\)
o
.....
.....
I
o
......
z
en
Co)
I\)
o
o
.....
.....
en
I\)
I
.
....Ln
....
(:)
C'I
Co)
C'I
~
Z
.....
2.0 Device Specifications (Continued)
2.2 ABSOLUTE MAXIMUM RATINGS (Note 1)
....
....•
Supply Voltage
7V
Input Voltages
-0.5V to Vee + 0.5V
C'I
Output Voltages
-0.5VtoVee + 0.5V
(:)
(:)
~
C')
o
z
Note: Absolute maximum ratings indicate limits beyond
which permament damage may occur. Continuous operation at these limits is not intended; operation should be limited to those conditions specified under Electrical Characteristics.
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications•
Storage Temperature
-65'C to + 150'C
Lead Temperature (Soldering, 10 sec.)
300'C
Continous Power Dissipation
1W
2.3 ELECTRICAL CHARACTERISTICS T A = -40'C to + 85'C, Vee = 5V ± 5%, GND = OV
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
VIL
Input Low Voltage
All Inputs Except RSTI & XIN
VIH
Input High Voltage
All Inputs Except RSTI & XIN
2.0
VT+
RSTI Rising Threshold Voltage
Vee = 5.0V
2.5
3.5
V
VHYS
RSTI Hysteresis Voltage
Vee = 5.0V
0.8
1.9
V
VXL
XIN Input Low Voltage
0.20 Vee
V
VXH
XIN Input High Voltage
IlL
Input Low Current
VIN = OV
-10
p.A
10
p.A
0.10 Vee
V
IIH
VOL
VOH
IL
Input High Current
VIN = Vee
PHI1 & PHI2, I = 1 mA
All Other Oujputs Except XOUT, I = 2 mA
Output High Voltage
All Outputs Except
XOUT, 1= -1 mA
Leakage Current on RD/WR
0.4V
=
5V and TA
V
0.80 Vee
Output Low Voltage
Supply Current
Icc
Note 1: All typical values are for Vce
V
=
V
0.90 Vee
s: VIN s: Vee
-20
100
fxin = 20 MHz
25'C.
Connection Diagram
Dual-In-Llne Package
~ I-Vcc
Iii£RWEN/SYNC - 2
1ID-3
Wii-4
DDIN- 5
23I-PEii
22 i-CWAiT
211-WAITI
2D I-WAlT2
ADS-I NS32C201 19 I-WAIT4
ICU
RITi- 7
18i-WAm
RITD- 8
17 I-TSO
ROY- 9
161--Cm
PHI2- 10
151-FCLK
PHll- 11
141-XOUT
13 i-XIN
0"0- 12
TL/EE/8524-2
Top View
Order Number NS32C201li or NS32C201N
See NS Package Number D24C or N24A
FIGURE 2.1
4-18
+20
p.A
120
mA
z
en
Co)
2.0 Device Specifications (Continued)
N
oN
2.4 SWITCHING CHARACTERISTICS
2.4.2 Output Loading
2.4.1 Definitions
Capacitive loading on output pins for the NS32C201.
All the timing specifications given in this section refer to
2.0V on the rising or falling edges of the clock phases PHil
and PHI2; to 15% or B5% of Vcc on all the CMOS output
signals, and to O.BV or 2.0V on all the TTL input signals,
unless specifically stated otherwise.
ROY, DBE, TSO ................................. 50 pF
C)
RD,WR ........................................ 75pF
CTTL ..................................... 50+100pF
FCLK ......................................... 100pF
PHil, PHI2 ..................................... 170 pF
R.E.-Rising Edge
F.E.-Falling Edge
2.4.3 Timing Tables
Reference/Conditions
NS32C20 1-15
NS32C201-10
Min
Max
Min
Units
Max
CLOCK-SIGNALS (XIN, FCLK, PHil & PHI2) TIMING
tcp
2.2
Clock Period
PHil R.E. to Next
PHil R.E.
tClh
2.2
Clock High Time
At 90% Vcc on PHil
(Both Edges)
0.5 tep
-15ns
0.5tcp
-7ns
0.5tcp
-IOns
0.5 tep
-3ns
tell
2.2
Clock Low Time
At 15% Vcc on PHil
0.5tep
-5ns
0.5tep
+10ns
0.5tCp
-5ns
0.5tep
+6ns
tClw(1,2)
2.2
Clock Pulse Width
At 2.0V on PHil, PHI2
(Both Edges)
0.5tcp
-IOns
0.5tcp
-4ns
0.5tcp
-6ns
0.5tcp
-4ns
PHil, PHI2 Asymmetry
(telw (1) - telw (2»
At 2.0V on PHil,
PHI2
-5
5
-3
3
ns
tClwas
100
66
ns
tClR
2.2
Clock Rise Time
15% to 90% Vcc
on PHil R.E.
8
6
ns
tClF
2.2
Clock Fall Time
90% to 15% VCC
on PHil F.E.
B
6
ns
tnOVl(1,2)
2.2
Clock Non·Overlap Time
At 15% Vcc on PHil,
PHI2
-2
+2
-2
+2
ns
Non·Overlap Asymmetry
(tnOVl (1) - InOVl (2»
At 15% Vcc on PHil,
PHI2
-4
4
-3
3
ns
tnOVLas
tXh
2.2
XIN High Time
(External Input)
At BO% Vee on XIN
(Both Edges)
16
10
ns
tXI
2.2
XIN Low Time
(External Input)
At 15% Vccon XIN
(Both Edges)
16
10
ns
tXFr
2.2
XIN to FCLK R.E. Delay
BO% Vcc on XIN R.E.
to FCLK R.E.
6
29
6
25
ns
tXFf
2.2
XIN to FCLK F.E. Delay
15% Vee on XIN F.E.
to FCLKF.E.
6
29
6
25
ns
txcr
2.2
XIN to CTTL R.E. Delay
BO% Vcc on XIN R.E.
to CTTLR.E.
6
34
6
25
ns
tXPr
2.2
XIN to PHil R.E. Delay
BO% Vee on XIN R.E.
to PHil R.E.
6
32
6
25
ns
tFCr
2.2
FCLK to CTTL R.E. Delay
FCLK R.E. to CTTL R.E.
0
6
0
6
ns
tFCf
2.2
FCLK to CTTL F.E. Delay
FCLK R.E. to CTTL F.E.
-3
4
-3
4
ns
tFPr
2.3
FCLK to PHil R.E. Delay
FCLK R.E. to PHil R.E.
-3
4
-3
4
ns
tFPf
2.3
FCLK to PHil F.E. Delay
FCLK R.E. to PHil F.E.
-5
2
-5
2
ns
tFw
2.3
FCLK Pulse Width
with Crystal
At 50% Vcc on FCLK
(Both Edges)
0.25tCp
-5ns
0.25 tep
+5ns
0.25tCp
-5ns
0.25 tcp
+5ns
tpCf
2.3
PHI2 R.E.to CTTL
F.E. Delay
PHI2 R.E. to CTTL F.E.
-3
4
-3
3
tcrw
2.3
CTTL Pulse Width
At 50% Vcc on CTTL
(Both Edges)
0.5tep
-7ns
0.5tcp
+1 ns
0.5 tep
-5ns
0.5tCp
+1 ns
Note 1: Ixc., IFCr, IFCf. IpCf. IcTh are measured wHh 100 pF load on CTTL
Note 2: PHI1 and PHI2 are interchangeable for the following parameters: tcp. tcLh. tcu. tCLw. telR, tcLF. tnOVL. tXPr. tFPr. tFPf.
4-19
en
Co)
N
o
N
CJ1
T.E.-Trailing Edge
Description
C)
C)
L.E.-Leading Edge
Figure
.....
z
....
....•
ABBREVIATIONS
Symbol
.
....
....
ns
........•
~
."
Q
~
z
......
Q
.,..
....•
2.0 Device Specifications (Continued)
2.4.3 Timing Tables (Continued)
Symbol
C')
f/)
z
Description
Reference/Conditions
NS32C201-10
NS32C201-15
Min
Max
Min
Max
-2
5
-2
3
ns
Units
CTTL TIMING (CL = 50 pF)
tpcr
2.3
PHI1 to CTTL R.E. Delay
PHI1 R.E. to CTTL R.E.
tcrR
2.3
CTTL Rise Time
10% to 90% Vcc
on CTTLR.E.
7
6
ns
tCTF
2.3
CTTL Fall Time
90% to 10% Vee
on CTTLF.E.
7
6
ns
4
ns
Q
~
Figure
CTTL TIMING (CL
=
100 pF)
-2
-2
tpcr
2.3
PHI1 to CTTL R.E. Delay
PHI1 R.E. to CTTL R.E.
tCTR
2.3
CTTL Rise Time
10% to 90% Vcc
on CTTLR.E.
8
7
ns
tcrF
2.3
CTTL Fall Time
90% to 10% Vee
on CTTLF.E.
8
7
ns
6
CONTROL INPUTS (RST1, ADS, ODIN) TIMING
tRSTs
2.4
RSTI Setup Time
Before PHI1 R.E.
20
15
tAOs
2.4
ADS Setup Time
Before PHI1 R.E.
25
20
ns
tADw
2.4
ADS Pulse Width
ADS L.E. to ADS T.E.
25
20
ns
toos
2.4
DDIN Setup Time
Before PHI1 R.E.
15
13
ns
CONTROL OUTPUTS (RSTO, TSO, RD, WR, DBE 8& RWEN/SYNC) TIMING
tRSTr
2.4
RSTO R.E. Delay
After PHI1 R.E.
21
10
ns
tTl
2.5
TSO L.E. Delay
After PHI1 R.E.
12
8
ns
tTr
2.5
TSO T.E. Delay
After PHI1 R.E.
10
ns
tRWI(F)
2.5
RD/WR L.E. Delay (Fast Cycle)
After PHI1 R.E.
30
21
ns
tRWI(S)
2.6
RD/WR L.E. Delay
(Peripheral Cycle)
After PHil R.E.
25
15
ns
tRWr
2.5/6
RD/WR T.E. Delay
After PHI1 R.E.
tOBI(W)
2.5/6
DBE L.E. Delay (Write Cycle)
After PHI1 R.E.
25
tOBI(R)
2.5/6
DBE L.E. Delay (Read Cycle)
After PHI2 R.E.
tOBr
2.5/6
DBE T.E. Delay
After PHI2 R.E.
IpLZ
2.7
RD,WR Low Level to TRI-STATE
tpHZ
2.7
IpZL
tpZH
3
3
18
20
3
3
15
ns
15
ns
20
11
ns
20
15
ns
After RWEN/SYNC R.E.
25
20
ns
RD,WR High Level to TRI·STATE
After RWEN/SYNC R.E.
20
15
ns
2.7
RD,WR TRI-STATE to Low Level
After RWEN/SYNC F.E.
25
18
ns
2.7
RD,WR TRI-STATE to High Level
After RWEN/SYNC F.E.
25
18
ns
WAIT STATES 8& CYCLE HOLD (CWAIT, WAITn, PER 8& ROY) TIMING
tCWs(H)
2.8
CWAIT Setup Time (Cycle Hold)
Before PHil R.E.
30
20
ns
leWh(H)
2.8
CWAIT Hold Time (Cycle Hold)
After PHil R.E.
0
0
ns
tCWs(W)
2.8/9
CWAIT Setup Time (Wait States)
Before PHI2 R.E.
10
6
ns
tCWh(W)
2.9
CWAIT Hold Time (Wait States)
After PHI2 R.E.
20
10
ns
tws
2.9
WAITn Setup Time
Before PHI2 R.E.
7
6
ns
tWh
2.9
WAITn Hold Time
After PHI2 R.E.
15
10
ns
tps
2.10
PER Setup Time
Before PHil R.E.
7
5
ns
tPh
2.10
PER Hold Time
After PHI1 R.E.
30
20
tRd
2.8/9/10
RDYDelay
After PHI2 R.E.
25
ns
12
ns
SYNCHRONIZATION (SYNC) TIMING
tSys
2.11
SYNC Setup Time
Before XIN R.E.
6
6
ns
tSyh
2.11
SYNC Hold Time
After XIN R.E.
5
5
ns
les
2.11
CTTLISYNC Inversion Delay
CTTL (master) to
RWEN/SYNC (slave)
4-20
10
7
ns
2.0 Device Specifications (Continued)
2.4.4 Timing Diagrams
FCLK
CTIL
PHil
PHI2
TL/EE/8524-21
FIGURE 2·2. Clock Signals (a)
XIN
FCLK
PHil
PHI2
cm
TL/EE/8524-22
FIGURE 2·3. Clock Signals (b)
TI
III
T2
PHil
RSTI
RSTO
ADS
ODIN
TLlEE/8524-23
FIGURE 2·4. Control Inputs
4·21
~
..-•
~
r-----------------------------------------------------------------------------,
2.0 Device Specifications (Continued)
oN
('I)
Tl
U)
Z
T2
T4
T3
PHI1
C;
..-•
oN
PHI2
o
N
~
Z
R5-+---";';'-n.
WR
TL/EE/8524-24
FIGURE 2·5. Control Outputs (Fast Cycle)
T1
TOO
T2
TDI
TD2
TD3
TD4
T3
T4
PH11
PH12
IDBIIR)
----1Ir.-..,
IDBIIW)
I
I
TLlEE/8524-25
FIGURE 2·6. Control Outputs (Peripheral Cycle)
RWENISYNC
.. 1.5V
whiiii
iiiii&iiii
r-+
- - - - -.. 1.5V _...;.........
TLlEE/8524-26
FIGURE 2·7. Control Outputs (TRI·STATE Timing)
4-22
.--------------------------------------------------------------------,z
U)
2.0 Device Specifications (Continued)
Co)
I\)
o
o
.....
.....•
I\)
TI
THI (FIRST)
THn (LAST)
T2
~
z
PHil
U)
Co)
I\)
o
I\)
o.....
PHI2
.....•
Ut
ROY
ROY REMAINS LOW
FOR SUBSEQUENT WAIT
TUEE/B524-27
FIGURE 2-8. Cycle Hold
TL/EE/B524-2B
FIGURE 2-9. Walt State (Fast Cycle)
T1
T2
TOO
TOI
T03
T02
TD4
T3
•
T4
PHil
PHI2
~AIT
+-____
____~~~~____
~
OR
WAIT"
PER
ROY
TL/EE/B524-29
FIGURE 2-10. Wait State (Peripheral Cycle)
4-23
....• r--------------------------------------------------------------------------,
.... 2.0 Device Specifications (Continued)
~
CI
B
z
c;
....
....•
RWEN/SYNC
~
~
o
z
t"jo-
CTlL
XIN
I -{
------1-.,.~b·.. -1----
-'
~
\
FIGURE 2·11. Synchronization Timing
4-24
\'---
TLlEE/8524-30
.----------------------------------------------------------------,z
tJ)
~National
(0)
I\)
I\)
~ Semiconductor
o
....o~
NS32202-10 Interrupt Control Unit
General Description
Features
The NS32202 Interrupt Control Unit (ICU) is the interrupt
controller for the Series 32000® microprocessor family. It is
a support circuit that minimizes the software and real·time
overhead required to handle multi·level, prioritized inter·
rupts. A single NS32202 manages up to 16 interrupt sources,
resolvesinterruptpriorities,andsuppliesasingle·byteinterrupt
vector to the CPU.
• 16 maskable interrupt sources, cascadable to 256
• Programmable 8- or 16-bit data bus mode
• Edge or level triggering for each hardware interrupt with
individually selectable polarities
• 8 software interrupts
• Fixed or rotating priority modes
• Two 16-bit, DC to 10 MHz counters, that may be con·
catenated into a single 32-bit counter
• Optional 8-bit 1/0 port available in 8-bit data bus mode
• High·speed XMOSTM technology
• Single, + 5V supply
• 40·pin, dual in·line package
The NS32202 can operate in either of two data bus modes:
16-bit or 8-bit. In the 16-bit mode, eight hardware and eight
software interrupt positions are available. In the 8-bit mode,
16 hardware interrupt positions are available, 8 of which can
be used as software interrupts. In this mode, up to 16 addi·
tional ICUs may be cascaded to handle a maximum of 256
interrupts.
Two 16-bit counters, which may be concatenated under pro·
gram control into a single 32-bit counter, are also available
for real·time applications.
Basic System Configuration
~ iiif
N832018
CPU
GROUP
MASTER
N832202
ICU
..L.
+-1
_
NON·CASCADED
INTERRUPT SOURCES
I~ iNi'
I·
CASCADED
N832202
ICU
-···
·
-·
+;-
·
..:-
'--- iNi'
CASCADED
INTERRUPT
SDURCES
+ ;-
CASCADED
N832202
ICU
·
·
..:-
TLlEE/5117-1
4-25
C)
.....
r---------------------------------------------------------------------------------,
I
Table of Contents
C'I
C)
C'I
C'I
CO)
en
z
1.0 PRODUCT INTRODUCTION
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.9 FPRT - First Priority Registers (R14, R15)
1.1110 Buffers
1.2 Read/Write Logic and Decoders
1.3 Timing and Control
1.4 Priority Control
1.5 Counters
3.10 MCTL - Mode Control Register (R16)
3.11 OSCASN - Output Clock Assignment (R17)
3.12 CIPTR - Counter Interrupt Pointer Register (R18)
3.13 PDAT - Port Dada Register (R19)
3.14 IPS - Interrupt/Port Select Register (R20)
2.0 FUNCTIONAL DESCRIPTION
3.15 PDIR - Port Direction Register (R21)
2.1 Reset
3.16 CCTL - Counter Control Register (R22)
2.2 Initialization
3.17 CICTL - Counter Interrupt Control Register (R23)
2.3 Vectored Interrupt Handling
3.18 LCSV/HCSV - L-Counter Starting Value/H-Counter
Starting Value Registers (R24, R25, R26, and R27)
2.3.1 Non-Cascaded Operation
3.19 LCCV/HCCV - L-Counter Current Value/H-Counter
Current Value Registers (R28, R29, R30, and R31)
2.3.2 Cascade Operation
2.4 Internal ICU Operating Sequence
3.20 Register Initialization
2.5 Interrupt Priority Modes
4.0 DEVICE SPECIFICATIONS
2.5.1 Fixed Priority Mode
4.1 NS32202 Pin Descriptions
2.5.2 Auto-Rotate Mode
2.5.3 Special Mask Mode
4.1.1 Power Supply
2.5.4 Polling Mode
4.1.2 Input Signals
4.1 .3 Output Signals
3.0 ARCHITECTURAL DESCRIPTION
4.1.4 Input/Output Signals
3.1 HVCT - Hardware Vector Register (RO)
4.2 Absolute Maximum Ratings
3.2 SVCT - Software Vector Register (Rl)
4.3 Electrical Characteristics
3.3 ELTG - Edge/Level Triggering Registers (R2, R3)
4.4 Switching Characteristics
3.4 TPL - Triggering Polarity Registers (R4, R5)
4.4.1 Definitions
3.5 IPND - Interrupt Pending Registers (R6, R7)
4.4.1.1 Timing Tables
3.6 ISRV - Interrupt In-Service Registers (R8, R9)
4.4.1.2 Timing Diagrams
3.7IMSK - Interrupt Mask Registers (Rl0, Rll)
3.8 CSRC - Cascaded Source Registers (R12, R13)
List of Illustrations
NS32202 ICU Block Diagram .................................................................................... 1-1
Counter Output Signals in Pulsed Form and Square Waveform for Three Differentlnitial Values ........................... 1-2
Counter Configuration and Basic Operations ....................................................................... 1-3
Interrupt Control Unit Connections in 16-Bit Bus Mode .............................................................. 2-1
Interrupt Control Unit Connections in 8-Bit Bus Mode ............................................................... 2-2
Cascaded Interrupt Control Unit Connections in 8-Bit Bus Mode ...................................................... 2-3
CPU Interrupt Acknowledge Sequence ............................................................................ 2-4
Interrupt Dispatch and Cascade Tables ........................................................................... 2-5
CPU Return from Interrupt Sequence ............................................................................. 2-6
ICU Interrupt Acknowledge Sequence ............................................................................ 2-7
ICU Return from Interrupt Sequence .............................................................................. 2-8
ICU Internal Registers ..........................................................................................3-1
HVCT Register Data Coding .....................................................................................3-2
Recommended ICU's Initialization Sequence ...................................................................... 3-3
NS32202 ICU Connection Diagram ............................................................................... 4-1
Timing Specification Standard ................................................................................... 4-2
READ/INTA Cycle .............................................................................................4-3
Write Cycle ....................................................................................................4-4
Interrupt Timing in Edge Triggering Mode .......................................................................... 4-5
InterruptTiming in Level Triggering Mode ......................................................................... 4-6
Externallnterrupt-Sampling-Clock to be Provided at Pin COUT/SCIN When in Test Mode ............................... .4-7
Internallnterrupt-Sampling-Clock to be Provided at Pin COUT ISCIN .................................................. 4-8
Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT/SCIN or GO/RO-G3/R6,
in Both Pulsed Form and Square Waveform ....................................................................... 4-9
4-26
.-------------------------------------------------------------~z
tJ)
1.0 Product Introduction
Co)
The NS32202 ICU functions as an overall manager in an
interrupt-oriented system environment. Its many features
and options permit the design of sophisticated interrupt systems.
1.4 PRIORITY CONTROL
1.11/0 BUFFERS AND LATCHES
The I/O Buffers and Latches block is the interface with the
system data bus. It contains bidirectional buffers for the
data I/O pins. It also contains registers and logic circuits
that control the operation of pins GO/IRO, ... ,G7/IR14
when the ICU is in the a-bit bus mode.
1.2 READ/WRITE LOGIC AND DECODERS
The Read/Write Logic and Decoders manage all internal
and external data transfers for the ICU. These include Data,
Control, and Status Transfers. This circuit accepts inputs
from the CPU address and control buses. In turn, it issues
commands to access the internal registers of the ICU.
1.3 TIMING AND CONTROL
sn
vee
G7IIRI4 +-1>
66/IRI2+-+
65/IR1D +-+
64/IRB +-1>
G3/IR6+-+
G2IIR4 .....
Gl/IR2+-+
GO/IRO+-+
07+-+
06+-+
05+-1>
04+-1>
03+-+
02+-+
01 .....
DO .....
Ifjf
IRI
Q
IR3
IR5
IR7
IR9
IRl1
IR13
IR15
!!!!!!J.
LV
PftIORITY
CONTROL
B~'~
i
I/O BUFFERS
AND
LATCHES
...•
N
1.5 COUNTERS
This block contains two 16-bit counters, called the H-counter and the L-counter. These are down counters that count
from an initial value to zero. Both counters have a 16-bit
register (deSignated HCSV and LCSV) for loading their restarting values. They also have registers containing the current count values (HCCV and LCCV). Both sets of registers
are fully described in Section 3.
The Timing and Control Block contains status elements that
select the ICU operating mode. It also contains state machines that generate all the necessary sequencing and control signals.
GND
Q
The Priority Control Block contains 16 units, one for each
interrupt position. These units provide the following functions.
• Sensing the various forms of hardware interrupt signals e.g. level (highllow) or edge (rising/falling)
o Resolving priorities and generating an interrupt request to the CPU
o Handling cascaded arrangements
o Enabling software interrupts
• Providing for an automatic return from interrupt
• Enabling the assignment of any interrupt position to
the internal counters
• Providing for rearrangement of priorities by assigning
the first priority to any interrupt position
• Enabling automatic rotation of priorities
Figure 1-1 shows the internal organization of the NS32202.
As shown, the NS32202 is divided into five functional
blocks. These are described in the following paragraphs:
1- 1-
N
N
TIMING
AND
CONTROL
COUNTERS
ClK
t
READ/WRITE lOGIC
AND DECODERS
4-1
11 t csi
RST
RD
Wii
lE
AD
AI
A2
FIGURE 1-1. NS322021CU Block Diagram
4-27
II
i i i i i
A3
A4
TL/EE/5117-2
Q
.-
~
N
CO)
U)
Z
1.0 Product Introduction (Continued)
2.0 Functional Description
The counters are under program control and can be used to
generate interrupts. When the count reaches zero, either
counter can generate an interrupt request to any of the 16
interrupt positions. The counter then reloads the start value
from the appropriate registers and resumes counting. Figure
1-2 shows typical counter output signals available from the
NS32202.
2.1 RESET
The ICU is reset when a logic low signal is present on the
RST pin. At reset, most internal ICU registers are affected,
and the ICU becomes inactive.
2.2 INITIALIZATION
After reset, the CPU must initialize the NS32202 to establish
its configuration. Proper initialization requires knowledge of
the ICU register's formats. Therefore, a flowchart of a recommended initialization sequence is shown in (Figure 3-3)
after the discussion of the ICU registers.
The maximum input clock frequency is 2.5 MHz.
A divide-by-four prescaler is also provided. When the prescaler is used, the input clock frequency can be up to 10
MHz.
The operation sequence shown in Figure 3-3 ensures that
all counter output pins remain inactive until the counters are
completely initialized.
When intervals longer than provided by a 16-bit counter are
needed, the L- and H-counters can be concatenated to form
a 32-bit counter. In this case, both counters are controlled
by the H-counter control bits. Refer to the discussion of the
Counter Control Register in Section 3 for additional information. Figure 1-3 summarizes counter read/write operations.
2.3 VECTORED INTERRUPT HANDLING
For details on the operation of the vectored interrupt mode
for a particular Series 32000 CPU, refer to the data sheet for
INPUT CLOCK
Ur--------....,IUr
COUNTER
CONlENTS
(INIT. VALUE=2) _ _ _ _ _ _ _ _ _ _ _-,
OUTPUT IN
PULSED FORM
'--__~I
OUTPUT IN
SQUARE WAVEFORM
COUNTER
CONlENTS
Ur------,UI"-----..,U-
(INIT. VALUE =1) - - - - - - - - . ,
OUTPUT IN
PULSED FORM
L
OUTPUT IN
SQUARE WAVEFORM
COUNTER
CONTENTS
(INIT. VALUE=O) _ _ _ _....,
OUTPUT IN
PULSED FORM
OUTPUT IN
SQUARE WAVEFORM
TLlEE/5117-4
FIGURE 1-2. Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values
4-28
z
en
Co)
2.0 Functional Description (Continued)
that CPU. In this discussion, it is assumed that the NS32202
is working with a CPU in the vectored interrupt mode. Several ICU applications are discussed, including non-cascaded
and cascaded operation. Figures 2-1, 2-2, and 2-3 show
typical configurations of the ICU used with the NS32016
CPU.
rupt Output (INT) pin and generates an interrupt vector byte.
The interrupt vector byte identifies the interrupt source in its
four least significant bits. When the CPU detects a low level
on its Interrupt Input pin, it performs one or two interrupt
acknowledge cycles depending on whether the interrupt request is from the master ICU or a cascaded ICU. Figure 2-4
shows a flowchart of a typical CPU Interrupt Acknowledge
sequence.
A peripheral device issues an interrupt request by sending
the proper signal to one of the NS32202 interrupt inputs. If
the interrupt input is not masked, the ICU activates its Inter-
I
.......... :..,
STARTING VALUE
LCSV/HCSV
~
COUNTER
FREEZE COUNTER READINGS
I
0.
..
c
='"
::>
'"~
0.
c
....
""
:z
""~
I
CURRENT VALUE
LCCVlHCCV
~
0:
""'I
~
TLiEE/5117-5
BASIC OPERATIONS:
~ ~-
(lOB)
WRITING TO LCCVlHCCV
®-
(lOB)
(only possible when counters are halted)
@l- (lOB)
@l- (lOB)
WRITING TO LCSVIHCSV
READING LCSVIHCSV
READING LCCV/HCCV
(lOB)
(only possible when counter
readings are frozen)
COUNTER COUNTS AND READINGS ARE
NOT FROZEN
COUNTER RELOADS STARTING VALUE
(occurs on the clock cycle following
the one in which it reaches zero)
FIGURE 1-3. Counter Configuration and Basic Operations
4-29
N
N
Q
~
....
Q
...
N
o
~
r-----------------------------------------------------------------------------~
2.0 Functional Description (Continued)
i3z
All-AU
AO-A23
iiif
~
N83201.
CPU
LATCH
T
I
AII-M
I
l
AII-M
HBE
+--
I::: J---. cs
lTi
IRU
lIlT
iii
+--
IRS
+-
IR7
+--
IRS
I+-
1R3
~
IRI
+-
NS3UG2
ICU
BUFFER
00-01S
AOO-AilIS
PIIIl
PHI2
00-071
GOIlRO-G7I1Rl.
t
PII"
+--
an
iiiiiN
~
IR15
IR13
iDS
PIII2
ADS
NS32201
TeU
ODIN
iiiL
-.1
Wli
iii
WI.
00-015
TL/EE/5117 -6
FIGURE 2-1. Interrupt Control Unit Connections In 16-Blt Bus Mode
A11-A23
AO-A23
-.I
NS3201.
CPU
AO-M
GND--+ HBE
T
Ail
AI-AS
LATCH
I=: J---. cs
m
an
iii'
INT
iiiiii
BUFFfR
PII"
t
PII"
DD-D7
ADD-AD11
PIII2
DD-D7
t
l'1li2
AG5
NS32301
TCU
ODIN -.1
iili
~L
~
WI
G7I1Rl.
IIII11R1Z
G5/IRlG
8411R1
G3/1R1
0211114
all1RZ
NI3220Z GOIIRG
leU
IR15
..,3
"U
IRS
IRT
IHI
IR3
IRI
DD-D15
NOTE: In !he 8-Bn Bus Mode !he Master ICU Registers appear at even
addresses (AO = 0) since the ICU communicates wi!h the least 8ignRlcant byte of the CPU data bus.
FIGURE 2-2. Interrupt Control Unit Connections In 8·Blt Bus Mode
4-30
:::
~
.....
.....
t::
+-
+++++-
++-
TL/EE/5117 -7
r--------------------------------------------------------------------------, en
Z
2.0 Functional Description (Continued)
Co)
I\)
I\)
Q
~
....
Q
AI-AS
GND--+
All-M
HIE
Ci
STI
1171111'
11111112
05/111D
114/111
113/111
6Z/1R4
CASCADED 61/1H2
NS32202 GO/IRQ
ICU
1115
DO-D7
ID
WI
liNT
All-AD
~
N83201.
CPU
LATCH
f
iii
AI-AS
8ND~
I=:r-
Pltn
ADl-AD11
PHIZ
f
f
'""
PHIZ
....
NS32201
TCU
I11III
IUffD
:::
All-M
:::
07/111'
111/1112
05/111D
114/111
113/111
Ci
G2/1R4
Bn
MASTER 01 11HZ
iii NS32202 GG/IRD
ICU
11115
1R13
1111
DO-D7
IHI ~
IR7 4 IRS 4 iii
IR3
1111
iii
HIE
:::
c-
lIT
::
:::
:::
....
m
iii
~
All-AD
I
I
I
1113
1111
IHI
IR7
1115
113
111
~
~
~
~
~
I
DO-D7
:::
:::
iii
~I
Wli
DO-D15
TL/EE/Sl17-B
FIGURE 2-3. Cascaded Interrupt Control Unit Connections In 8-Blt Bus Mode
4-31
o
.,...
S
2.0 Functional Description (Continued)
C"I
C"I
CO)
en
z
• Condo A is true if current instruction Is terminated
or an interruptible point in a string Instruction is
reached.
TL/EE/S117-Q
FIGURE 2-4. CPU Interrupt Acknowledge Sequence
4-32
z
(f)
2.0 Functional Description (Continued)
Co)
In general, vectored interrupts are serviced by interrupt routines stored in system memory. The Dispatch Table stores
up to 256 external procedure descriptors for the various
service procedures. The CPU INTBASE register points to
the top of the Dispatch Table. Figure 2-5 shows the layout
of the Dispatch Table. This figure also shows the layout of
the Cascade Table, which is discussed with ICU cascaded
operation.
2.3.2 Cascaded Operation. In cascaded operation, one or
more of the interrupt inputs of the master leu are connected to the Interrupt Output pin of one or more cascaded
ICUs. Up to 16 cascaded ICUs may be used, giving a system total of 256 interrupts.
Nate: The number of cascaded ICUs is practically limited to 15 because the
Dispatch Table for the NS32016 CPU is constructed with entries 1
through 15 either used for NMI and Trap descriptors, or reserved for
future use. Interrupt position a of the master leu should not be cascaded, so it can be vectored through Dispatch Table entry 0, reserved
for non-vectored interrupts. In this case, the non-vectored interrupt
entry (entry 0) is also available for vectored interrupt operation, since
the CPU is operating in the vectored interrupt mode.
2.3.1 Non-Cascaded Operation. Whenever an interrupt request from a peripheral device is issued directly to the master ICU, a non-cascaded interrupt request to the CPU results. In a system using a single NS32202, up to 16 interrupt
requests can be prioritized. Upon receipt of an interrupt request on the INT pin, the CPU performs a Master InterruptAcknowledge bus cycle, reading a vector byte from address
FFFE0016. This vector is then used as an index into the
dispatch table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return-from-Interrupt (RET) instruction, which performs a Return-from-Interrupt bus cycle, informing the ICU that it may re-prioritize any
interrupt requests still pending. Figure 2-6 shows a typical
CPU RETI sequence. In a system with only one ICU, the
vectors provided must be in the range of 0 through 127; this
can be ensured by writing OXXXXXXX into the SVCT register. By providing a negative vector value, the master ICU
flags the interrupt source as a cascaded ICU (see below).
The address of the master ICU should be FFFEOOI6. (0)
Cascaded ICUs can be located at any system address. A list
of cascaded ICU addresses is maintained in the Cascade
Table as a series of sixteen 32-bit entries.
(")Note: The CPU status corresponding to both, master interrupt acknowledge and return from interrupt bus cycles, as well as address bit
AS, could be used to generate the chip select (CS) Signal for ac·
cessing the master leu during one of the above cycles. In this case
the master ICU can reside at any system address. The only limitation is that the least significant 5 or 6 address bits (6 in the S·bit bus
mode) must be zero. The address bit AS must be decoded to pre·
vent an NMI bus cycle from reading the hardware vector register of
the ICU. This could happen, since the NS32016 CPU performs a
dummy read cycle from address FFFF0016. with the same status
as a master INTA cycle, when a non-maskable-interrupt is acknowl-
edged.
MEMORY
l
TH~E ADDR~S~ ARE
USED BYTHE CPU DURING
THE SECDND CYCLE OF
AN INTA DR REII
SEOUENCE TO GEr THE
INTERRUPT VECTOR FROM
A CMCADED ICU.
CASCADED ICU ADDR~S D
(INTBME-64)-
CASCADE TABLE
CASCADED ICU ADDRESS 14
~~ ______~_C_M_C_AD_ED
__IC_U_A_DD_R_~_S_15~rNVI D~CRIPTOR
NMIANDTRAP
DESCRIPTDRS·
R~ERVED·
I
(INTBASE +4- VECTOR)
INT. DESCRIPTOR 16
INTERRUPT
DlSPIirCH TA8lE
I-_IN_T._D_ES_CR_IPT_O_R_N_~~ - - - - - - - - - - - - - - - -
INT. DESCRIPTDR 255
(ADDR~S
FFF£IJOt.)-
MASTER ICU'S
HVCT REGISTER
- C P U READS THIS LOCATIDN DURING
FIRST CYCLE OF INTA OR REII
SEOUENCE TO GEr BTHER
THE INTERRUPT VECTOR OR
A CASCADE TABLE INDEX FROM
THE MASTER ICU.
- Table entries 1 to 15 should not be used by the leu since they contain NMI and Trap DeSCriptors
or are reserved for future use. (For more details refer to NS32016 data sheet.)
FIGURE 2-5. Interrupt Dispatch and Cascade Tables
4-33
TL/EE/5117 -10
N
N
o
•
......
o
N
Q
....
N
~
N
(II)
tn
Z
,-------------------------------------------------------------------~
2.0 Functional Description
or
(Continued)
cascaded ICU, of course, has its own set of 16 unique interrupt vectors, one vector for each of its 16 interrupt positions.
The CPU interprets the vector value read during a Cascaded Interrupt Acknowledge cycle as an unsigned number.
Thus, this vector can be in the range 0 through 255.
When a cascaded interrupt service routine completes its
task, it must return control to the interrupted program with
the same RETI instruction used in non-cascaded interrupt
service routines. However, when the CPU performs a Master Return From Interrupt cycle, the CPU accesses the master ICU and reads the negative Cascade Table index identifying the cascaded ICU that originally received the interrupt
request. Using the cascaded ICU address, the CPU now
performs a Cascaded Return From Interrupt cycle, informing
the cascaded ICU that the service routine is over. The byte
provided by the cascaded ICU during this cycle is ignored.
2.4 INTERNAL ICU OPERATING SEQUENCE
The NS32202 ICU accepts two interrupt types, software and
hardware.
Software interrupts are initiated when the CPU sets the
proper bit in the Interrupt Pending (IPND) registers (R6, R7),
located in the ICU. Bits are set and reset by writing the
proper byte to either R6 or R7. Software interrupts can be
masked, by setting the proper bit in the mask registers (R10,
R11).
EXECUTE CASCADED
ICU CYCLE AND READ
VECTOR FROM
CASCADED ICU
Hardware interrupts can be either internal or external to the
ICU. InternallCU hardware interrupts are initiated by the onchip counter outputs. External hardware interrupts are initiated by devices external to the ICU, that are connected to
any of the ICU interrupt input pins.
Hardware interrupts can be masked by setting the proper bit
in the mask registers (R10, R11). If the Freeze bit (FRZ),
located in the Mode Control Register (MCTL), is set, all incoming hardware interrupts are inhibited from setting their
corresponding bits in the IPND registers. This prevents the
ICU from recognizing any hardware interrupts.
Once the ICU is initialized, it is enabled to accept interrupts.
If an active interrupt is not masked, and has a higher priority
than any interrupt currently being serviced, the ICU activates its Interrupt Output (INT). Figure 2-7 is a flowchart
showing the ICU interrupt acknowledge sequence.
The CPU responds to the active INT line by performing an
Interrupt Acknowledge bus cycle. During this cycle, the ICU
clears the IPND bit corresponding to the active interrupt position and sets the corresponding bit in the Interrupt In-Service Registers (ISRV). The 4-bit in-service counter in the
master ICU is also incremented by one if the fixed priority
mode is selected and the interrupt is from a cascaded ICU.
The ISRV bit remains set until the CPU performs a RETI bus
cycle and the 4-bit in-service counter is decremented to
zero. Figure 2-8 is a flowchart showing ICU operation during a RETI bus cycle.
TL/EE/5117-11
FIGURE 2-6. CPU Return from Interrupt Sequence
The master ICU maintains a list (in the CSRC register pair)
of its interrupt positions that are cascaded. It also provides a
4-bit (hidden) counter (in-service counter) for each interrupt
position to keep track of the number of interrupts being
serviced in the cascade ICUs. When a cascaded interrupt
input is active, the master ICU activates its interrupt output
and the CPU responds with a Master Interrupt Acknowledge
Cycle. However, instead of generating a positive interrupt
vector, the master ICU generates a negative Cascade Table
index.
The CPU interprets the negative number returned from the
master ICU as an index into the Cascade Table. The Cascade Table is located in a negative direction from the Dispatch Table, and it contains the virtual addresses of the
hardware vector registers for any cascaded NS32202s in
the system. Thus, the Cascade Table index supplied by the
master ICU identifies the cascaded ICU that requested the
interrupt.
When the ISRV bit is set, the INT output is disabled. This
output remains inactive until a higher priOrity interrupt position becomes active, or the ISRV bit is cleared.
An exception to the above occurs in the master ICU when
the fixed priority mode is selected, and the interrupt input is
connected to the INT output of a cascaded ICU. In this case
the ISRV bit does not inhibit an interrupt of the same priority.
Once the cascaded ICU is identified, the CPU performs a
Cascaded Interrupt Acknowledge cycle. During this cycle,
the CPU reads the final vector value directly from the cascaded ICU, and uses it to access the Dispatch Table. Each
This is to allow nesting of interrupts in a cascaded ICU.
4-34
z
(J)
2.0 Functional Description (Continued)
Co)
N
N
C
N
.
.....
C
• Condo B is true if anyone of the following condi·
tions is satisfied.
1) No interrupt is being serviced
2) There is a pending unmasked interrupt with
priority higher than thai of the interrupt being
serviced.
3) There is a pending unmasked interrupt from a
cascaded leu with priority higher or same as that
of the highest priority interrupt position in the
master leu with the ISRV bit sel
...--..:...-...,
TL/EE/5117-12
FIGURE 2-7. leu Interrupt Acknowledge Sequence
4-35
C)
.,...
N
C)
r---------------------------------------------------------------------------------,
2.0 Functional Description (Continued)
'"
'"
en
C")
z
YES
RESET
INTERRUPT ISRV BIT
AND ASSIGN FIRST
PftIDRITY TO NEXT
INTERRUPT POSITION
RESET
INTERRUPT
ISRV BIT
TL/EE/5117-13
FIGURE 2-8.
leu Return from Interrupt Sequence
4-36
z
en
Co)
2.0 Functional Description (Continued)
The bits of the ISRV registers are changed with either the
Set Bit Interlocked or Clear Bit Interlocked instructions (SBITIW or CBITIW). The in-service bit is cleared to enable lower priority interrupts and set to disable them.
2.5 INTERRUPT PRIORITY MODES
The NS32202 ICU can operate in one of four interrupt priority modes: Fixed Priority; Auto-Rotate; Special Mask; and
Polling. Each mode is described below.
I\)
I\)
o
~
.....
o
Note: For proper operation of the ICU, an interrupt service routine must set
its ISRV bit before executing the RETI instruction. This prevents the
RETI cycle from clearing the wrong ISRV bit.
2.5.1 Fixed Priority Mode
In the Fixed Priority Mode (also called Fully Nested Mode),
each interrupt position is ranked in priority from 0 to 15, with
being the highest priority. In this mode, the processing of
lower priority interrupts is nested with higher priority interrupts. Thus, while an interrupt is being serviced, any other
interrupts of the same or lower priority are inhibited. The ICU
does, however, recognize higher priority interrupt requests.
2.5.4 Polling Mode
o
The Polling Mode gives complete control of interrupt priority
to the system software. Either some or all of the interrupt
positions can be assigned to the polling mode. To assign all
interrupt positions to the polling mode, the CPU interrupt
enable flag is reset. To assign only some of the interrupt
positions to the polling mode, the desired interrupt positions
are masked in the Interrupt Mask registers (IMSK). In either
case, the polling operation consists of reading the Interrupt
Pending (lPND) registers.
When the interrupt service routine executes its RETI instruction, the corresponding ISRV bit is cleared. This allows any
lower priority interrupt request to be serviced by the CPU.
At reset, the default priority assignment gives interrupt IRO
priority 0 (highest priority), interrupt IR 1 priority 1, and so
forth. Interrupt IR15 is, of course, assigned priority 15, the
lowest priority. The default priority assignment can be altered by writing an appropriate value into register FPRT (L)
as explained in Section 3.9.
If necessary, the IPND read can be synchronized by setting
the Freeze (FRZ) bit in the Mode Control register (MCTL).
This prevents any change in the IPND registers during the
read. The FRZ bit must be reset after the polling operation
so the IPND contents can be updated. If an edge-triggered
interrupt occurs while the IPND registers are frozen, the interrupt request is latched, and transferred to the IPND registers as soon as FRZ is reset.
Nale: When the ICU generates an interrupt request to the CPU for a higher
priority interrupt while a lower priority interrupt is still being serviced by
the CPU, the CPU responds to the interrupt request only if its internal
interrupt enable flag is set. Normally. this flag is reset at the beginning
of an interrupt acknowledge cycle and set during the RETI cycle. If the
CPU is to respond to higher priority interrupts during any interrupt
The polling mode is useful when a single routine is used to
service several interrupt levels.
service routine, the service routine must set the internal CPU interrupt
enable flag, as soon during the service routine as desired.
3.0 Architectural Description
2.5.2 Auto-Rotate Mode
The NS32202 has thirty-two a-bit registers that can be accessed either individually or in pairs. In 16-bit data bus
mode, register pairs can be accessed with the CPU word or
double-word reference instructions. Figure 3-1 shows the
ICU internal registers. This figure summarizes the name,
function, and offset address for each register.
The Auto Rotate Mode is selected when the NTAR bit is set
to 0, and is automatically entered after Reset. In this mode
an interrupt source position is automatically assigned lowest
priority after a request at that position has been serviced.
Highest priority then passes to the next lower priority position. For example, when servicing of the interrupt request at
position 3 is completed (ISRV bit 3 is cleared), interrupt position 3 is assigned lowest priority and position 4 assumes
highest priority. The nesting of interrupts is inhibited, since
the interrupt being serviced always has the highest priority.
Because some registers hold similar data, they are grouped
into functional pairs and assigned a single name. However,
if a single register in a pair is referenced, either an L or an H
is appended to the register name. The letters are placed in
parentheses and stand for the low order a bits (L) and the
high order a bits (H). For example, register R6, part of the
Interrupt Pending (lPND) register pair, is referred to individually as IPND(L).
This mode is used when the interrupting devices have to be
assigned equal priority. A device requesting an interrupt, will
have to wait, in the worst case, until each of the 15 other
devices has been serviced at most once.
The following paragraphs give detailed descriptions of the
registers shown in Figure 3-1.
2.5.3 Special Mask Mode
The Special Mask Mode is used when it is necessary to
dynamically alter the ICU priority structure while an interrupt
is being serviced. For example, it may be desired in a particular interrupt service routine to enable lower priority interrupts during a part of the routine. To do so, the ICU must be
programmed in fixed priority mode and the interrupt service
routine must control its own in-service bit in the ISRV registers.
3.1 HVCT -
HARDWARE VECTOR REGISTER (RO)
The HVCT register is a single register that contains the interrupt vector byte supplied to the CPU during an Interrupt
Acknowledge (INTA) or Return From Interrupt (RETI) cycle.
The HVCT bit map is shown below:
7
6
543
2
0
B
4-37
B
B
B
V
V
V
V
•
0
.•
C'\I
0
3.0 Architectural Description
(Continued)
C'\I
C'\I
CO)
en
z
REG. NUMBER AND
ADDRESS IN HEX.
REG.
NAME
REG. FUNCTION
RO(0016)
HVCT-
HARDWARE VECTOR
R1 (0116)
SVCT-
SOFTWARE VECTOR
R3(0316)
R2(0216)
ELTG-
EDGE/LEVEL TRIGGERING
R5 (0516)
R4(0416)
TPL-
TRIGGERING POLARITY
R7 (0716)
R6 (0616)
IPND-
INTERRUPTS PENDING
R9 (0916)
R8 (0816)
ISRV-
INTERRUPTS IN-SERVICE
R11 (0816)
R10 (OA16)
IMSK-
INTERRUPT MASK
R13 (0016)
R12 (OC16)
CSRC-
CASCADED SOURCE
R15 (OF16)
R14 (OE16)
FPRT-
FIRST PRIORITY
R16(1016)
MCTL-
MODE CONTROL
R17 (1116)
OCASN-
OUTPUT CLOCK ASSIGNMENT
R18 (1216)
CIPTR-
COUNTER INTERRUPT POINTER
R19 (1316)
PDAT-
PORT DATA
R20 (1416)
IPS-
INTERRUPT/PORT SELECT
R21 (1516)
PDIR-
PORT DIRECTION
R22 (1616)
CCTL-
COUNTER CONTROL
R23 (1716)
CICTL-
COUNTER INTERRUPT CONTROL
R25 (1916)
R24(1816)
LCSV-
L-COUNTER STARTING VALUE
R27 (1816)
R26(1A16)
HCSV-
H-COUNTER STARTING VALUE
R29 (1016)
R28 (1C16)
LCCV-
L-COUNTER CURRENT VALUE
R31 (1F16)
R30 (1E16)
HCCV-
H-COUNTER CURRENT VALUE
FIGURE 3-1.ICU Internal Registers
4-38
3.0 Architectural Description (Continued)
The BBBB field is the bias which is programmed by writing
BBBB00002 to the SVCT register (R1). The VVVV field identifies one of the 16 interrupt positions. The contents of the
HVCT register provide various information to the CPU, as
shown in Figure 3-2:
sn
_
CPU LAS OR A6
]
TL/EE/5117-14
The ELTG registers determine the input trigger mode for
each of the 16 interrupt inputs. Each input is aSSigned a bit
in this register pair. An interrupt input is level-triggered if its
bit in ELTG is set to 1. The input is edge-triggered if its bit is
cleared. At reset, all bits in ELTG are set to 1.
Nole 2: If the HVCT registar is raad with STt ~ a (INTA cycla) and no
unmasked intarrupt is panding, tha binary valua BBBBllll is ra·
turnad and any panding adga-triggered interrupt in position 15 is
cleared.
If the auto-rotate priority mode is selected, the FPRT register is also
cleared, thus preventing any interrupt from being acknowledged. In
this case a re-intialization of the FPRT register is required for the
ICU to acknowledge interrupts again.
If odd·numbered interrupt positions must be used for software interrupts, the edge triggering mode must be selected
and the corresponding interrupt inputs should be prevented
from changing state.
If a read of the HVCT register is performed with STI ~ 1 (RETI
CYcle), tha binary value BBBBll11 is returned.
3.4 TPL - TRIGGERING POLARITY
REGISTERS (R4, R5)
The TPL registers determine the polarity of either the active
level or the active edge for each of the 16 interrupt inputs.
As with the ELTG registers, each input is assigned a bit.
Possible triggering modes for the various combinations of
ELTG and TPL bits are shown below.
ELTG BIT
TPL BIT
TRIGGERING MODE
o
o
Falling Edge
o
1
Rising Edge
1
o
Low Level
High Level
1
1
Software interrupt pOSitions are not affected by their TPL
bits. At reset, all TPL bits are set to O.
If the auto·rotate mode is selected, a priority rotation is also performed.
3.2 SVCT - SOFTWARE VECTOR REGISTER (R1)
The SVCT register is a copy of the HVCT register. It allows
the programmer to read the contents of the HVCT register
without initiating a INTA or RETI cycle in the ICU. It also
allows a programmer to change the BBBB field of the HVCT
register. The bit map of the SVCT register is the same as for
the HVCT register.
During a write to SVCT, the four least significant bits are
unaffected while the four most significant bits are written
into both SVCT and HVCT (R1 and RO).
The SVCT register is updated dynamically by the ICU. The
four least significant bits always contain the vector value
that would be returned to the CPU if a INTA or RETI cycle
were executed. Therefore, when reading the SVCT register,
the state of the CPU ST1 pin is used to select either pending interrupt data or in-service interrupt data. For example, if
the SVCT register is read with ST1 = 0 (as for an INTA
cycle), the VVVV field contains the encoded value of the
highest priority pending interrupt. On the other hand, if the
SVCT register is read with ST1 = 1, the VVVV field contains
the encoded value of the highest priority in-service interrupt.
Note 1: If edged-triggered interrupts ara to ba handlad, the TPL registar
should ba programmed bafore tha ELTG ragistar.
This prevents spurious interrupt requests from being generated dur·
Ing tha ICU initialization from adga·triggarad intarrupt positions.
Note 2: Hardwara interrupt inputs connected to cascaded ICUs must hava
1heir TPL bits sat to O.
3.5 IPND -INTERRUPT PENDING REGISTERS (R6, R7)
The IPND registers track interrupt requests that are pending
but not yet serviced. Each interrupt position is assigned a bit
in IPND. When an interrupt is pending, the corresponding bit
in IPND is set. The IPND data are used by the ICU to generate interrupts to the CPU. These data are also used in polling operations.
Nole: If the CPU ST1 output is connected directly to the ICU STI input, the
vector read from SVCT is always the RETI vector. If both the INTA
and RETI vectors ara dasirad, additional logic must ba added to driva
tha ICU STI input. A typical circuit is shown below. In this circuit, tha
state of tha ICU ST1 input is controlled by both the CPU STI output
and the selected address bit.
INTA CYCLE (ST1 = 0)
RETI CYCLE (ST1= 1)
Highest priority pending interrupt is from:
Highest priority in-service interrupt was from:
cascaded ICU
any other source
cascaded ICU
programmed bias'
1111
1111
VVVV
ICU
3.3 ELTG - EDGE/LEVEL TRIGGERING
REGISTERS (R2, R3)
Note 1: The leu always interprets a fead of the HVCT register as either an
INTA or RETI cycle. Since these cycles causa intarnal changas to
the ICU, normal programs must never read the leu HVCT register.
BBBB
sn
I
I
encoded value of the highest
priority pending interrupt
I
I
any other source
programmed bias·
encoded value of the highest
priority in-service interrupt
'Tha Programmed bias for tha master leu must ranga from 0000 to 01112 becausa tha CPU intarprets a one in the most significant bit position as a Cascada Table
Index indicator for a cascaded ICU.
FIGURE 3-2. HVCT Register Data Coding
4-39
.... r---------------------------------------------------------------------------------,
C)
N
~
C'I
CO)
tn
Z
3.0 Architectural Description (Continued)
The IPND registers are also used for requesting software
interrupts. This is done by writing specially formatted data
bytes to either IPND(L) or IPND(H). The formats differ for
registers R6 and R7. These formats are shown below:
IPND(L) (R6) IPND(H) (R7) Where:
S
=
3.7 IMSK -INTERRUPT MASK REGISTERS (R10, R11)
Each NS32202 interrupt position can be individually
masked. A masked interrupt source is not acknowledged by
the ICU. The IMSK registers store a mask bit for each of the
ICU internupt positions. If an interrupt position's IMSK bit is
set to 1, the position is masked.
SOOOOPPP
S0001PPP
Set (S
=
1) or Clear (S = 0)
The IMSK registers are controlled by the system software.
At reset, all IMSK bits are set to 1, disabling all interrupts.
PPP = is a binary number identifying one of
eight bits
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit in the IMSK register. However, if an interrupt is set
pending during the CPU instruction that masks off that interrupt, the
CPU may still perform an interrupt acknowledge cycle following that
Note: The data read from either R6 or R7 are different from that written to
the register because the leu returns the register contents, rather than
the formatted byte used to set the register bits.
instruction since it might have sampled the INT line before the
The ICU automatically clears a setlPND bit when the pending interrupt request is serviced. All pending interrupts in a
register can be cleared by writing the pattern 'X1 XXXXXX'
to it (X = don't care). To avoid conflicts with asynchronous
hardware interrupt requests, the IPND registers should be
frozen before pending interrupts are cleared. Refer to the
Mode Control Register description for details on freezing
the IPND registers.
leu
deasserted it. This could cause the leu to provide an invalid vector.
To avoid this problem, the above operation should be performed with
the CPU interrupt disabled.
3.8 CSRC - CASCADED SOURCE
REGISTERS (R12, R13)
The CSRC registers track any cascaded interrupt positions.
Each interrupt position is assigned a bit in the CSRC registers. If an interrupt position's CSRC bit is set, that position is
connected to the INT output of another NS32202 ICU, i.e., it
is a cascaded interrupt.
At reset, all IPND bits are set to O.
Note: The edge sensing mechanism used for hardware interrupts in the
NS32202 ICU is a latching device that can be cleared only by acknowiedging the interrupt or by changing the trigger mode to level
sensing. Therefore, before clearing pending interrupts in the IPND
At reset, the CSRC registers are set to O.
Note I: If any cascaded ICU is used, the CSRC register should be cleared
registers, any edge·triggered interrupt inputs must first be switched to
during initialization (if the initialization does not follow a hardware
the level·triggered mode. This clears the edge·triggered interrupts;
the remaining interrupts can then be cleared in the manner described
above. This applies to clearing the interrupts only. Edge·triggered in·
terrupts can be set without changing the trigger mode.
reset) by writing zeroes Into it. This should be done before setting
the bits corresponding to the cascaded interrupt positions. This operation ensures that the 4-bit in-service counters (aSSOCiated with
each interrupt pOSition to keep track of cascaded interrupts) always
get cleared when the leu is re-initialized.
3.6 ISRV -INTERRUPT IN-SERVICE
REGISTERS (R8, R9)
NOle 2: Only the Master ICU should have any CSRC bits set. If CSRC bits
are set in a cascaded ICU, incorrect operation results.
The ISRV registers track interrupt requests that are currently being serviced. Each interrupt position is assigned a bit in
ISRV. When an interrupt request is serviced by the ICU, its
corresponding bit is set in the ISRV registers. Before generating an interrupt to the CPU, the ICU checks the ISRV registers to ensure that no higher priority interrupt is currently
being serviced.
3.9 FPRT - FIRST PRIORITY REGISTERS (R14, R15)
The FPRT registers track the ICU interrupt position that currently holds first priority. Only one bit of the FPRT registers
is set at one time. The set bit indicates the interrupt position
with first (highest) priority.
The FPRT registers are automatically updated when the ICU
is in the auto-rotate mode. The first priority interrupt can be
determined by reading the FPRT registers. This operation
returns a 16-bit word with only one bit set. An interrupt position can be aSSigned first priority by writing a formatted data
byte to the FPRT(L) register. The format is shown below:
Each time the CPU executes an RETI instruction, the ICU
clears the ISRV bit corresponding to the highest priority interrupt in service. The ISRV registers can also be written
into by the CPU. This is done to implement the special mask
priority mode.
At reset, the ISRV registers are set to O.
Note: If the ICU initialization does not follOW a hardware reset, the ISRV
register should be cleared during initialization by writing zeroes into it.
7
6
5
4
3
2
1
0
X
X
X
X
F
F
F
F
Where: XXXX =
FFFF =
Don't Care
A binary number from 0 to 15 indicating the interrupt position assigned first priority.
Note: The byte above Is written only to the FPRT(L) register. Any date writ·
ten to FPRT(H) is ignored.
At reset the FFFF field is set to 0, thus giving internupt position 0 first priority.
3.10 MCTL - MODE CONTROL REGISTER (R16)
The contents of the MCTL set the operating mode of the
NS32202 ICU. The MCTL bit map is shown below.
76543210
4-40
3.0 Architectural Description (Continued)
CFRZ
COUTD
Determines whether or not the NS32202 counter readings are frozen. When frozen, the
counters continue counting but the LCCV and
HCCV registers are not updated. Reading of
the true value of LCCV and HCCV is possible
only while they are frozen.
Note: The interrupt senSing mechanism on pins GOffRO •...• G3ffR6 is not
CFRZ = 0 = > LCCV and HCCV Not Frozen
CFRZ = 1 = > LCCV and HCCV Frozen
The CIPTR register tracks the assignment of counter outputs to interrupt positions. A bit map of this register is shown
below.
7
S
5
43210
disabled when any of these pins is programmed as clock output.
Thus, to avoid spurious interrupts, the corresponding bits in register
IPS should also be set to zero.
3.12 CIPTR - COUNTER INTERRUPT
POINTER REGISTER (R1B)
Determines whether the COUTISCIN pin is an
input or an output. COUT/SCIN should be
used as an input only for testing purposes. In
this case an external sampling clock must be
provided otherwise hardware interrupts will not
be recognized.
H
H
H
Where: HHHH =
COUTD = 0 = > COUTISCIN is Output
COUTM
COUTD = 1 = > COUT/SCIN is Input
When the COUTISCIN pin is programmed as
an output (COUTD = 0), this bit determines
whether the output signal is in pulsed form or in
square wave form.
COUTM
CLKM
NTAR
= 0 = > Square Wave Form
L
L
A 4-bit binary number identifying the
interrupt position assigned to the HCounter (or the H + L-counter if the
counters are concatenated).
A 4-bit binary number identifying the
interrupt position assigned to the Lcounter.
3.13 PDAT -
PORT DATA REGISTER (R19)
Used only in the 8-bit Bus Mode. This register is used to
input or output data through any of the pins GOI
IRO •... ,G711R14 programmed as I/O ports by the IPS register. Any pin programmed as an output delivers the data
written into PDAT. The input pins ignore it. Reading PDAT
provides the logical value of all I/O pins, INPUT and OUTPUT.
> Square Wave Form
CLKM = 1 = > Pulsed Form
Freeze Bit. In order to allow a synchronous
reading of the interrupt pending registers
(lPND), their status may be frozen, causing the
ICU to ignore incoming requests. This is of special importance if a polling method is used.
FRZ = 0 = > IPND Not Frozen
3.14 IPS -
INTERRUPTIPORT SELECT REGISTER (R20)
Used only in the 8-bit Bus Mode. This register controls the
function of the pins GOIIRO, ... ,G711R14. Each of these
pins is individually programmed as an I/O port, if the corresponding bit of IPS is 0; as an interrupt source, if the corresponding bit is 1. The assignment of the H-Counter output
to GOIIRO, ... ,G311RS by means of reg. OCASN overrides
the assignment to these pins as I/O ports or interrupt inputs.
At Reset, all the IPS bits are set to 1.
FRZ = 1 = > IPND Frozen
Determines whether the ICU is in the AUTOROTATE or FIXED Priority Mode. In AUTOROTATE mode, the interrupt source at the
highest priority position, after being serviced, is
assigned automatically lowest priority. In this
mode, the interrupt in service always has highest priority and nesting of interrupts is therefore
inhibited.
Note: Whenever a bit in the IPS register is set to zero, to program the
corresponding pin as an 110 port, any pending interrupt on the corresponding interrupt position will be cleared.
3.15 PDIR -
Controls the data bus mode of operation.
PORT DIRECTION REGISTER (R21)
Used only in the 8-bit Bus Mode. This register determines
the direction of any of the pins GOIIRO, ... ,G711R14 programmed as I/O ports by the IPS register. A logic 1 indicates an input, while a logic 0 indicates an output.
T1SN8 = 0 = > 8-Bit Bus Mode
T1SN8 = 1 = > lS-Bit Bus Mode
At reset, all MCTL bits except COUTD, are reset to O.
COUTD is set to 1.
At Reset, all the PDIR bits are set to 1.
3.16 CCTL -
3.11 OCASN - OUTPUT CLOCK
ASSIGNMENT REGISTER (R17)
Used only in the 8-bit Bus Mode. The four least significant
bits of this register control the output clock assignments on
pins GOIIRO, ... ,G3I1RS. If any of these bits is set to 1, the
clock generated by either the H-Counter or the H + L-Counter will be output to the corresponding pin. The four most
significant bits of OCASN are not used. At Reset the four
least significant bits are set to O.
L
At reset, all bits in the CIPTR are set to 1. (This means both
counters are assigned to interrupt position 15.)
NTAR = 0 = > Auto-Rotate Mode
NTAR = 1 = > Fixed Mode
T1SN8
L
Note: Assignment of a counter output to an interrupt position also requires
control bits to be set in the CICTL register. If a counter output is
assigned to an interrupt position, external hardware interrupts at that
position are ignored.
COUTM = 1 = > Pulsed Form
Used only in the 8-bit Bus Mode. This bit controls the clock wave form on any of the pins
GOIIRO, ... ,G3I1RS programmed as counter
output.
CLKM = 0 =
FRZ
LLLL =
H
COUNTER CONTROL REGISTER (R22)
The CCTL register controls the operating modes of the
counters. A bit map of CCTL is shown below.
7
S
5
43210
lCCONlcFNPslcOUTllcOUTolcRUNHlcRUNLlcDCRHlcDCRLl
CCON
4-41
Determines whether the counters are independent or concatenated to form a single 32-bit
counter (H + L-Counter). If a 32-bit counter is
selected, the bits corresponding to the H-
•
.
o
....
C'I
o
3.0 Architectural Description (Continued)
Counter will control the H + L-Counter, while
the bits corresponding to the L-Counter are not
used.
C'I
C'I
C")
(/)
z
CFNPS
CCON = 0 = > Two 16-bit Counters
CCON = 1 = > One 32-bit Counter
Determines whether the external clock is
prescaled or not.
CFNPS = 0 =
CFNPS = 1 =
COUT1&
COUTO
control bits. In this case the CIEL bit should be set to zero to
avoid spurious interrupts from the L-Counter. A bit map of
the CICTL register is shown following.
76543210
ICERH ICIRH ICIEH IWENH ICERL ICIRL ICIEL IWENL I
H-Counter Error Flag. This bit is set (1) when a
second interrupt request from the H-Counter
(or H + L-Counter) occurs before the first request is acknowledged.
CIRH
H-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the H-Counter (or
H + L-Counter). It is automatically reset when
the interrupt is acknowledged.
H-Counter Interrupt Enable. When it is set, the
H-Counter (or H + L-Counter) interrupt is enabled.
H-Counter Control Write Enable. When WEHN
is set (1), bits CERH, CIRH, and CIEH can be
written.
L-Counter Error Flag. This bit is set (1) when a
second interrupt request from the L-Counter
occurs before the first request is acknowledged.
L-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the L-Counter. It is
automatically reset when the interrupt is acknowledged.
L-Counter Interrupt Enable. When it is set (1),
the L-Counter interrupt is enabled.
L-Counter Control Write Enable. When WENL
is set (1), bits CERL, CIRL, and CIEL can be
written.
> Clock Prescaled (divided by 4)
> Clock Not Prescaled.
These bits are effective only when the COUTI
SCIN pin is programmed as an OUTPUT
(COUTO bit in reg. MCTL is 0). Their logic levels are decoded to provide different outputs for
COUT/SCIN, as detailed in the table below:
CIEH
FOUT1 COUTO COUTISCIN Output Signal
0
0
1
1
CERH
0
1
0
1
WENH
Internal Sampling Oscillator
Zero Detect Of L-Counter
Zero Detect Of H-Counter
Zero Detect Of H + L-Counter*
CERL
'If the H· and L·Counters are not concatenated and
COUT1/COUTO are both I, the COUTISCIN pin Is active
when either counter reaches zero.
CRUNH
CRUNL
CDCRH
CDCRL
CIRL
Determines the state of either the H-Counter or
the H + L-Counter, depending upon the status
ofCCON.
CRUNH = 0 = > H-Counter or H + L-Counter
Halted
CRUNH = 1 = > H-Counter or H + L-Counter
Running
Effective only when CCON = O. This bit determines whether the L-Counter is running or halted.
CRUNL = 0 = > L-Counter Halted
CRUNL = 1 = > L-counter Running
Effective only when CRUNH =0 (Counter Halted). This bit is the single cycle decrement signal for either the H-Counter or the H + L-Counter.
CIEL
WENL
Nole: Selling Ihe write enable bits (WENH or WENL) and writing any of the
other CICTL bits are concurrent operations. That is, the ICU willig·
nore any attempt to alter CICTL bits if the proper write enable bit is
not set in the data byte.
At reset, all CICTL bits are set to O. However, if the counters
are running, the bits CIRL, CERL, CIRH and CERH may be
set again after the reset Signal is removed.
3.18 LCSV/HCSV - L·COUNTER STARTING VALUEI
H·COUNTER STARTING VALUE REGISTERS
(R24, R25, R26, AND R27)
The LCSV and HCSV registers store the start values for the
L-Counter and H-Counter, respectively. Each time a counter
reaches zero, the start value is automatically reloaded from
either LCSV or HCSV, one clock cycle after zero count is
reached. Loading LCSV or HCSV from the CPU must be
synchronized to avoid writing the registers while the reloading of the counters is occurring. One method Is to halt the
counters while the registers are loaded.
CDCRH = 0 = > No Effect
CDCRH = 1 = > Decrement H·Counter or
H + L-Counter
Effective only when CRUNL = 0 and CCON =
O. This bit is the single cycle decrement signal
for the L-Counter.
CDCRL = 0 =
CDCRL = 1 =
>
>
No Effect
Decrement L-Counter
Note: The bits CDCRL and CDCRH are set when a logic 1 is written into
them, but, they are automatically cleared after the end of the write
operation. This is needed to accomplish the decrement operation.
Therefore, these bits always contain 0 when read.
When the 16-bit counters are concatenated, the LCSV and
HCSV registers hold the 32-bit start count, with the least
significant byte in R24 and the most significant byte in R27.
Reset does not affect the CCTL bits.
3.19 LCCVlHCCV - L·COUNTER CURRENT VALUEI
H·COUNTER CURRENT VALUE REGISTERS
(R28, R29, R30, AND R31)
3.17 CICTL - COUNTER INTERRUPT
CONTROL REGISTER (R23)
The CICTL register controls the counter interrupts and records counter interrupt status. Interrupts can be generated
from either of the 16-bit counters. When the counters are
concatenated, the interrupt control is through the H-Counter
The LCCV and HCCV registers hold the current value of the
counters. If the CFRZ bit in the MCTL register is reset (0),
these registers are updated on each clock cycle with the
current value of the counters. LCCV and HCCV can be read
only when the counter readings are frozen (CFRZ bit in the
4-42
z
3.0 Architectural Description
CJ)
Co)
(Continued)
N
N
o
~
.....
o
HALJ COUNTERS
BY CLEARING
BITS CRUNL AND
CRUNH IN
REG. CCTL
WRITE COUNTER'S
STARTING VALUES
INTO LCCV AND
HCCV TO AVOID
LONG INITIAL
COUNTS
RESET COUTO BIT
IN MCTL TO
PROGRAM CaUT ISCtN
PIN AS AN OUTPUT
AND ENABLE THE
INTERNAL INTERRUPT
SAMPLING CLOCK
START COUNTERS
BY SETTING BITS
CRUNL AND/OR
CRUNH IN REG. CCTL
o
TL/EE/5117-15
FIGURE 3-3. Recommended leU's Initialization Sequence
4-43
Status (ST1): Status signal from the CPU. When the Hardware Vector Register is read, this signal differentiates an
INTA cycle from an RETI cycle. If ST1 =0 the ICU initiates
an INTA cycle. If ST1 =1 an RETI cycle will result.
Interrupt Requests (lR1, IR3 ••• , IR15): These eight inputs are used for hardware interrupts. Each may be individually triggered in one of four modes: Rising Edge, Falling
Edge, low level, or High level.
Counter Clock (ClK): External clock signal to drive the ICU
internal counters.
3.0 Architectural
Description (Continued)
MCTl register is 1). They can be written only when the
counters are halted (CRUNl and/or CRUNH bits in the
CCTl register are 0). This last feature allows new initial
count values to be loaded immediately into the counters,
and can be used during initialization to avoid long initial
counts.
When the 16-bit counters are concatenated, the lCCV and
HCCV registers hold the 32-bit current value, with the least
significant byte in R28 and the most significant byte in R31.
4.1.3 Output Signals
Interrupt Output (INn: Active low. This signal indicates
that an interrupt is pending.
3.20 REGISTER INITIALIZATION
Figure 3-3 shows a recommended initialization procedure
for the ICU that sets up all the ICU registers for proper operation.
4.1.4 Input/Output Signals
Data Bus 0-7 (DO through 07): Eight low-order data bus
lines used in both 8-bit and 16-bit bus modes.
General Purpose I/O lines (GO/IRO, GlIIR2, ••• ,G7/
IR14): These pins are the high-order data bits when the ICU
is in the 16-bit bus mode. When the ICU is in the 8-bit bus
mode, each of these can be individually assigned one of the
following functions:
• Additional Hardware Interrupt Input (IRO through
IR14)
• General Purpose Data Input
• General Purpose Data Output
• Clock Output from H-Counter (Pins GO/IRO through
G3/IR6 only)
4.0 Device Specifications
4.1 NS32202 PIN DESCRIPTIONS
4.1.1 Power Supply
Power (Vee): + 5V DC Supply
Ground (GND): Power Supply Return
4.1.2 Input Signals
Reset (RST): Active low. This signal initializes the ICU. (The
ICU initializes to the 8-bit bus mode.)
Chip Select (CS): Active low. This signal enables the ICU to
respond to address, data, and control signals from the CPU.
Addresses (AO through A4): Address lines used to select
the ICU internal registers for read/write operations.
High Byte Enable (HBE): Active low. Enables data transfers on the most-significant byte of the Data Bus. If the ICU
is in the 8-bit Bus Mode, this signal is not used and should
be connected to either GND or Vee.
Read (RD): Active low. Enables data to be read from the
ICU's internal registers.
Write (WR): Active low. Enables data to be written into the
ICU's internal registers.
It should be noted that, for maximum flexibility in assigning
interrupt priorities, the interrupt positions corresponding to
pins GO/IRO, ... ,G7/IR14 and IR1, ... ,IR15 are interleaved.
Counter or Oscillator Output/Sampling Clock Input
(COUT/SCIN): As an output, this pin provides either a clock
signal generated by the ICU internal oscillator, or a zero
detect Signal from one or both of the ICU counters. As an
input, it is used for an external clock, to override the internal
oscillator used for interrupt sampling. This is done only for
testing purposes.
4-44
z
en
w
4.0 Device Specifications (Continued)
N
N
o
4.2 ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
Storage Temperature
O·Cto +70·C
-65·C to + 150·C
All Input or Output Voltages with
Respect to GND
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
-0.5Vto +7.0V
Power Dissipation
1.5 Watt
4.3 ELECTRICAL CHARACTERISTICS
TA = o· to 70·C, Vee = +5V ± 5%, GND = OV
Symbol
Parameter
Conditions
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2mA
VOH
Output High Voltage
IOH = -400 p.A
IL
Leakage Current
(Output and 1/0 Pins in TRI-STATE/lnput mode)
0.4 ,;; VIN ,;; Vee
II
Input Load Current
Vin=OtoVcc
Icc
Power Supply Current
lout = 0, T = O·C
Min
Typ
Max
Units
0.8
V
2.0
Connection Diagram
IRI5- 1
00-2
STI- 3
G7/IR1C- 4
G&/IRI2- 5
G511Rl0- 6
GC/IRB- 7
G3/IR6- 8
G2/IRC- 9
Bl/IR2- 10
GO/IRO- 11
07- 12
06- 13
05- 14
04- 15
03- 16
02- 17
01-18
00- 19
GHO- 20
NS32202
ICU
0.45
2.4
-20
-20
40 I--- Vee
391---IR13
38 I---IRl1
37 I---IR9
36 1---1R7
35 I---IR5
34 I---IR3
33 I---IRI
32>-- cue
31 -Viii
3O-iiii'
29
28
27
26
25
24
23
22
21
-toUT/SC,.
-HBE
-RST
-A4
-A3
-A2
-AI
-AD
-C!
Top View
Order Number NS32202D-6, NS32202D·10
See NS Package Number D40C
FIGURE 4-1
4-45
V
TL/EE/5117-3
V
V
20
p.A
20
p.A
300
mA
....o~
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
Abbreviations:
All the timing specifications given in this section refer to
O.BV or 2.0V on the input and output signals as illustrated in
Figure 1, unless specifically stated otherwise.
L.E.-Ieading edge
R.E.-rising edge
T.E.-trailing edge
F.E.-falling edge
::>(2.0
: 0.1 TElT POINTS
!::
TEST POINTS
x::
TUEE/5117 -16
FIGURE 4-2. Timing Specification Standard
4.4.1.1 Timing Tables
Symbol
Figure
Description
Reference/Conditions
NS32202-10
Min
Units
Max
READ CYCLE
tAhRDia
4-3
Address Hold Time
After RD T.E.
10
ns
tAsRDa
4-3
Address Setup Time
Before AD L.E.
35
ns
tCShRDia
4-3
CSHoldTime
After RD T.E.
15
ns
tCSsRDa
4-3
CS Setup Time
Before RD L.E.
30
tDhRDla
4-3
Data Hold Time
After RD T.E.
tRDaDv
4-3
Data Valid
After RD L.E.
tROw
4-3
RD Pulse Width
At O.BV (Both Edges)
160
ns
tSsRDa
4-3
ST1 Setup Time
Before RD L.E.
35
ns
tShRDia
WRITE CYCLE
4-3
ST1 Hold Time
After RD T.E.
-30
ns
tAhWRla
4-4
Address Hold Time
After WR T.E.
10
ns
tAsWRa
4-4
Address Setup Time
Before WR L.E.
35
ns
!cShWRia
4-4
CSHoldTime
After WR T.E.
15
ns
tCSsWRa
4-4
CS Setup Time
Before WR L.E.
30
ns
tDhWRia
4-4
Data Hold Time
After WR T.E.
10
ns
tDsWRia
4-4
Data Setup Time
Before WR T.E.
70
tWRiaPf
4-4
Port Output Floating
After WR T.E. (To PDIR)
200
ns
tWRiaPv
4-4
Port Output Valid
After WR T.E.
200
ns
tWRw
4-4
WR Pulse Width
At O.BV (Both Edges)
4-46
5
160
ns
50
ns
150
ns
ns
ns
z
(J)
4.0 Device Specifications (Continued)
Co)
N
N
o
4.4.1.1 Timing Tables (Continued)
Symbol
Figure
Description
Reference/Conditions
NS32202-10
Min
Units
Max
....o~
OTHER TIMINGS
tCOUTI
4-S
Internal Sampling Clock
low Time
At O.SV (Both Edges)
tCOUTo
4-S
Internal Sampling Clock Period
tSCINh
4-7
External Sampling Clock High Time
At 2.0V (Both Edges)
tSCINI
4-7
External Sampling Clock low Time
At O.SV (Both Edges)
tSCINp
4-7
External Sampling Clock Period
Ich
4-9
External Clock High Time
(Without Prescaler)
At 2.0V (Both Edges)
tChp
4-9
External Clock High Time
(With Prescaler)
At 2.0V (Both Edges)
tCI
4-9
External Clock low Time
(Without Prescaler)
At O.SV (Both Edges)
tClp
4-9
External Clock low Time
(With Prescaler)
At O.SV (Both Edges)
tCy
4-9
External Clock Period
(Without Prescaler)
tCyp
4-9
External Clock Period
(With Prescaler)
tGCOUTI
4-9
Counter Output Transition Delay
After ClK F.E.
IcOUTw
4-9
Counter Output Pulse
Width in Pulsed Form
At O.SV (Both Edges)
tACKIR
4-5
Interrupt Request Delay
After Previous Interrupt
Acknowledge
tlRld
4-5
INT Output Delay
After Interrupt
Request Active
tlRw
4-5
Interrupt Request Pulse
Width in Edge Trigger
At O.SV (Both Edges)
RST Pulse Width
At O.SV (Both Edges)
tRSTw
50
ns
400
ns
100
ns
100
ns
SOO
ns
100
ns
40
ns
100
ns
40
ns
400
ns
100
ns
300
ns
50
ns
500
ns
SOO
ns
50
ns
400
ns
4.4.1.2 Timing Diagrams
)
ADDRESS
sn:=)
IS.RD4
!---IAsROI-
CS
•
l(
~ICS""'-IS.ROI-
IROw
0
K
-- ......-
-'
~tCS"RDII--+1
iiD
0
DATABUS------ -
-
IROIIlv
---- -
-------------
J
0
FIGURE 4-3. READIINTA Cycle
4-47
Io.ROoo-1
DATA YAUD
-------
TL/EE/5117-17
...
o
N
o
a
4.0 Device Specifications (Continued)
C\I
z
ADDRESS
-"'--
DATA BUS
DATAVAUD
OUTPUT PORT
MU __________________________________________________J
TLlEE/5117-1S
FIGURE 4-4. Write Cycle
iitiIINTA)
TLlEE/5117-19
FIGURE 4-5. Interrupt Timing in Edge Triggering Mode
IR
\~
____________
~t:
r=,-1.____,r
\_---/
iiiiIINTA)
FIGURE 4-6. Interrupt TIming in Level Triggering Mode
4-48
TLlEE/5117-20
z
en
4.0 Device Specifications (Continued)
Co)
N
N
o
~
.....
o
cue
TL/EE/5117-21
Note: Interrupts are sampled on the rising edge of elK.
FIGURE 4-7. External Interrupt-Sam pIIng-Clock to be Provided at Pin COUT/SCIN When in Test Mode
seue
TL/EE/5117-22
FIGURE 4-8. Internal Interrupt-Sampling-Clock Provided at Pin COUT/SCIN
CLK
COUNTER OUTPUT
IN SQUARE ---~
WAVEFORM
TL/EE/5117-23
FIGURE 4-9. Relationship Between Clock Input at Pin ClK and Counter Output Signals at Pins COUT/SCIN or
GO/RO, ••• ,G3/R6, in Both Pulsed Form and Square Waveform
II
4-49
o .-------------------------------------------------------------------------,
....
~
C'II
~
~National
PRELIMINARY
~ Semiconductor
Z
NS32203-10 Direct Memory Access Controller
General Description
Features
The NS32203 Direct Memory Access Controller (DMAC) is
a support chip for the Series 32000® microprocessor family
designed to relieve the CPU of data transfers between
memory and 1/0 devices. The device is capable of packing
data received from 8-bit peripherals into 16-bit words to reduce system bus loading. It can operate in local and remote
configurations. In the local configuration it is connected to
the multiplexed Series 32000 bus and shares with the CPU,
the bus control signals from the NS32201 Timing Control
Unit (TCU). In the remote configuration, the DMAC, in conjunction with its own TCU, communicates with 1/0 devices
and lor memory through a dedicated bus, enabling rapid
transfers between memory and 1/0 devices. The DMAC
provides 4 16-bit 1/0 channels which may be configured as
two complementary pairs to support chaining.
• Direct or Indirect data transfers
• Memory to Memory, 1/0 to 1/0 or Memory to 1/0
transfers
• Remote or Local configurations
• 8-Bit or 16-Bit transfers
• Transfer rates up to 5 Megabytes per second
• Command Chaining on complementary channels
• Wide range of channel commands
• Search capability
• Interrupt Vector generation
• Simple interface with the Series 32000 Family of
Microprocessors
• High Speed XMOSTM Technology
• Single + 5V Supply
• 48-Pin Dual-In-Line Package
Block Diagram
A16-A23
REaO
ADO-ADI5
ACKO
HBE
ODIN
ADS
Cs
ROY
ClK
BREa
BGRT
HOLD
HlDA
lORD
IOWR
REal
u
6
g
...
ACKI
u
i::!:
""~
;;!;
REa2
III
:::J
m
ACK2
REa3
iNi
RST/HlT
ACK3
TUEE/8701-1
4-50
.--------------------------------------------------------------------------, zCJ)
Table of Contents
1.0 PRODUCT INTRODUCTION
2.0 FUNCTIONAL DESCRIPTION
2.2 Data Transfer Operations
2.2.1 Indirect Data Transfers
2.2.2 Direct (FLYBY) Data Transfers
2.3 Local Configuration
2.4 Remote Configuration
2.5 Data Source (Destination) Attributes
2.6 Word Assembly/Disassembly
2.7 Auto Transfer
2.8 Search
2.9 Interrupts
2.10 Transfer Modes
2.11 Chaining
2.12 Channel Priorities
3.0 ARCHITECTURAL DESCRIPTION
3.1 Global Registers
3.1.1 CONF· Configuration Register
3.1.2 HVCT • Hardware Vector Register
3.1.3 SVCT - Software Vector Register
3.1.4 STAT - Status Register
3.2 Control Registers
3.2.1 COM - Command Register
3.2.2 SRCH - Search Register
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.3 Parameter Registers
3.3.1 SRC - Source Address Register
3.3.2 DST - Destination Address Register
3.3.3 LNGT - Block Length Register
4.0 DEVICE SPECIFICATIONS
4.1 NS32203 Pin Descriptions
4.1.1 Supplies
4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
4.4.2.2 Input Signal Requirements
4.4.2.3 Clocking Requirements
4.4.3 Timing Diagrams
Appendix A: Interfacing Suggestions
List of Illustrations
Power-on Reset Requirements ...............................................................•................... 2-1
General Reset Timing ..........................................................................................2-2
Recommended Reset Connections ............................................................................... 2-3
Indirect Read Cycle ............................................................................................2-4
Indirect Write Cycle (Single Transfer Mode) ........................................................................ 2-5
Direct Memory·To-IlO Data Transfer (Single Transfer Mode) ......................................................... 2-6
Direct IIO-To-Memory Data Transfer (Single Transfer Mode) ......................................................... 2-7
NS322031nterconnections ....................................................................................•.2-8
Write to NS32203 Internal Registers .............................................................................. 2-9
Read from NS32203 Internal Registers .......................................................................... 2-10
NS 32203 Internal Registers .....................................................................................3-1
NS32203 Connection Diagram ..........................................................................•....•...4-1
Timing Specification Standard (Signal Valid After Clock Edge) ........................................................ 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
Write to DMAC Registers ....................................................................................... .4-4
Read From DMAC Registers .....................................................................................4-5
Clock Timing ................................................................................................. .4-6
Indirect Write Cycle ............................................................................................ .4-7
Indirect Read Cycle ........................................................................................... .4-8
Direct 1I0-To-MemoryTransfer .............................................................................•.... 4·9
Direct Memory-To-I/O Transfer ................................................................................. 4-10
HOLD/HOLDA Sequence Start .................................................................................4-11
HOLD/HOLDA Sequence End .................................................................................. 4-12
Bus Request/Grant Sequence Start .............................................................................4-13
Bus Request/Grant Sequence End ..............................................................................4-14
Ready Sampling ..............................................................................................4-15
REOn/ ACKn Sequence (DMAC Initially Not Idle) ..................................................................4-16
REOn/ ACKn Sequence (DMAC Initially Idle) ...................................................................... 4-17
HaltedCycle .................................................................................................4-18
Interrupt On Match/No Match ..................................................................................4-20
Interrupt On Halt ..............................................................................................4-21
Power-on Reset ..............................................................................................4-22
Non-Power-on Reset ..........................................................................................4-23
NS322031nterconnections in Remote Configuration ................................................................ A-1
4·51
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tf
....
o
1.0 Product Introduction
The NS32203 Direct Memory Access Controller (DMAC) is
specifically designed to minimize the time required for high
speed data transfers in a Series 32000-based computer
system. It includes a wide variety of options and operating
modes to enhance data throughput and system optimization, and to allow dynamic reconfiguration under program
control.
begin. A set of registers is provided for each channel to
control the type of operation for that channel.
Bus Interface Unit. The bus interface unit controls all data
transfers between peripheral I/O devices and memory
whenever the DMAC is in control of the bus. This unit also
controls the transfer of data between the CPU and the
DMAC internal registers.
The NS32203 can operate in two basic system configurations: local and remote. In the local configuration, the DMAC
and the CPU share the same bus (address, data and control) and only one of them can perform data transfers on the
bus at anyone time. In this configuration, the DMAC and the
CPU also share a Timing Control Unit (TCU) and a single set
of address latches. Since this configuration yields a minimum part-count system, it offers a good cost/performance
trade-off in many situations.
The remote configuration is intended to minimize the CPU
bus use. In this configuration, the NS32203 I/O devices and
optional buffer memory have their own dedicated bus (remote bus) so that an I/O transfer may be performed without
loading the CPU bus (local bus).
Timing and Control Logic. This block generates all the
sequencing and control signals necessary for the operation
of the DMAC.
Priority Resolver. This block resolves contentions among
channels requesting service simultaneously.
2.0 Functional Description
2.1 RESETTING
The RST/HLT line serves both as a reset input for the onchip logic and as a DMAC HALT input. Resetting is accomplished by pulling RST/HlT low for at least 64 clock cycles.
Upon detecting a Reset, the DMAC terminates any Data
transfer in progress, resets its internal logic and enters an
inactive state. On application of power, RST /HlT must be
held low for at least 50 ,...S after Vee is stable. This is to
ensure that all on-Chip voltages are stable before operation.
Whenever reset is applied, the rising edge must occur while
the clock signal on the ClK pin is high (see Figure 2-1 and
2-2). The NS32201 TCU provides circuitry to meet the reset
requirements. Figure 2-3 shows the recommended connections. The HALT function is accomplished when RST/HlT
is activated for 1 or 2 clock cycles and then released. It can
be used to stop any data transfer in progress in case of a
bus error. As soon as HALT is acknowledged by the
NS32203, the current transfer operation is terminated. See
Figure 4-18.
Communication between the dedicated bus and the CPU
bus may be initiated at any time by either the CPU or the
NS32203. The DMAC accesses the CPU bus whenever a
data transfer to/from memory or any I/O device residing on
this bus is to be performed. The CPU, in turn, accesses the
dedicated bus for reading status data or for programming
either the DMAC or its I/O devices.
The NS32203 internal organization consists of seven functional blocks as illustrated in the block diagram. Descriptions of these blocks are given below.
DMA Channels. The NS32203 provides four channels.
Each channel accepts a request from a peripheral I/O device and informs it when data transfer cycles are about to
4.5V·'eo_ _ _ _ _ _ _ _
cc---"
V
eLK
..,....----
5~
_oJ
~
"-U
14------~50~.,---~-+I
omB}
-~I----..I!
FIGURE 2-1. Power-On Reset Requirements
4-52
TLlEE/8701-2
2.0 Functional Description
(Continued)
CLK~Jl-Il1---64 CLOCK CYCLES--....j
RST/HLT--~'n'&",,~~m~
55
r
TL/EE/B701-3
FIGURE 2·2. General Reset Timing
Vee
NS32201
TCU
NS32203
DMAC
p----------.
I
I_I RESET
I
._---------"
I
EXTERNAL RESET
(OPTIONAL)
SYSTEM RESET
RESET SWITCH
(OPTIONAL)
HALT
(OPTIONAL)
TLlEE/B701-4
FIGURE 2·3. Recommended Reset Connections
2.2 DATA TRANSFER OPERATIONS
After the NS32203 has been initialized by software, it is
ready to transfer blocks of data, containing up to 64 kbytes,
between memory and I/O devices, without further intervention required of the CPU. Upon receiving a transfer request
from an I/O device, the DMAC performs the following operations:
Each channel can be programmed for indirect or direct data
transfers. Detailed descriptions of these transfer types are
provided in the fOllowing sub-sections.
2.2.1 Indirect Data Transfers
In this mode of operation, each byte or word transfer between source and destination requires at least two bus cycles. The data is first read into the DMAC and subsequently
it is written into the destination. The bus cycles in this case
are similar to the CPU bus cycles when the MMU is not
used. This mode is slower than the direct mode, but is the
only one that allows some data manipulation like Byte
Search or Word Assembly/Disassembly. Figure 2-4 and 2-5
show the read and write cycle timing diagrams related to
indirect data transfers. If a search operation is specified,
extra clock cycles may be added fOllowing each read cycle.
1) Acquires control of the bus
2) Acknowledge the requesting I/O device which is connected to the highest priority channel.
3) Starts executing data transfer cycles according to the values stored into the control registers of the channel being
serviced.
4) Terminates data transfers and relinquishes control of the
bus as soon as one of the programmed conditions is met.
4-53
o,... ,-----------------------------------------------------------------------.
~
o
2.0 Functional Description (Continued)
N
N
n
('I)
en
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elK
A16-23
n
12
T1
T3
T4
r--
--rL-rL-rL-!Lf1--
L~r.tUUHli{III1IUJJ/J...
I
L'
I
I
ROY
l
L'
ADO-15
~
rL...
InORnl
y:- r-
~
- '(!I..'-_100
,~ }-I(fffL
.c:t-
IV
u
ADDRESS VALID
-
DATA IN}- I--
i""'-
~
II
II
VALID
1\
II
1
['
II
\
{.
e- n
{
NS*2201 SIGN AlS
1\
II
TL/EE/8701-5
FIGURE 2-4. Indirect Read Cycle
4·54
2.0 Functional Description
Ti
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(Continued)
I\)
I\)
Ti
T2
T1
T4
13
I Tl
OR Ti
.
o
I
~
......
o
CLK [
A16-23 [
'hVlIIIII!J /IIIIII!J !If..
ADO-15 [
h
1
-
'II. ~1I.
r,---
ADDRESS VALID
'- X
ADDR.
-
~ r-
DATA OUT
ADS [
U
oorn[~ 1fI111111/, rI///////!J u
\
'II,
HBE [
ROY [
'IX
li'flllllll,
ACKn [
+
'II, ~j,
VI,
I
1\
J
\
I
HOLD [
HLDA [
iVR[
~
I-
VlIIIII
IOWR [
r'-
VALID
NSi~OI
SIGT
r-
S
I
TLlEE/8701-6
FIGURE 2-5. Indirect Write Cycle (Single Transfer Mode)
Note: If bUrst mode is selected, HOLD is released at the end of the transfer operation.
4-55
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....
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~
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en
z
r-------------------------------------------------------------------------------------~
2.0 Functional Description
(Continued)
direct data transfers. Figures 2-6 and 2-7 show the timing
diagrams of direct memory-to· I/O and I/O-to-memory transfers respectively.
2.2.2 Direct (Flyby) Data Transfers
This mode of operation allows a very high data transfer rate
between source and destination. Each data byte or word to
be transferred requires only a single bus cycle instead of
two separate read and write cycles, which are typical of the
indirect mode. The DMAC accomplishes direct data transfers by activating lORD, during memory write cycles, and
10WR, during memory read cycles.
Note 1: In the direct mode each channel can control only one 1/0 device
because the 1/0 device Is hardwired to the ACKn output of the
corresponding channel. In the Indirect mode. a channel can control
multiple devices as long as each device is selected through its own
address rather than the liCKn output. However. the possiblity of
selecting a single 1/0 device by the liCKn output is maintained in
the Indirect mode as well.
An I/O device, in the direct mode, is usually enabled by the
proper acknowledge signal (ACKn) from the DMAC. No
search or word assembly/disassembly are possible during
n
elK
A16-23
ADD-15
n
Note 2: Whenever the DMAC is either idle or is performing indirect transfers.
it generates the lORD and IOWR signals as a replica oi RD and WR.
This simplifies the logiC required to access 1/0 devices wired for
direct data transfers.
T1
T2
IZ'IIIIIIIINIIIIII/) fJI..
IOWR
I Tl
OR
nI
I
L'
I
-
_ . . ..l-...
.~
'"'"flI\-~)-I--
\
L'
X
VALID
1\
II
II
\
I.
[- ~
_-
'"L_
U
I
L'
[.
L'
.-L-_
ADDRESS VALID
I
ROY
T4
T3
[_rurLrLiLfl--!L L-~
I
rOOT
r
~
I
TLfEEf8701-7
FIGURE 2-6. Direct Memory-To-1/0 Data Transfer (Single Transfer Mode)
4-56
z
2.0 Functional Description
en
Co)
(Continued)
even though it is directed to an 110 device and is related to
an indirect data transfer. This causes the system to be quite
sensitive to the volume of data handled by the DMAC. Thus,
the overall system performance decreases as the volume of
data increases. A possible solution to this problem is to use
the remote configuration, described in the following section.
A significant advantage of the local configuration is its sim·
plicity.
2.3 LOCAL CONFIGURATION
As previously mentioned, in the local configuration the
DMAC shares with CPU and MMU the multiplexed addressl
data bus as well as the control signals from the NS32201
TCU. A typical local configuration is shown in Figure 2·8.
The DMAC, in the local configuration, must gain control of
the bus whenever a data transfer cycle is to be performed,
CL{_HJ--U--LrL.r-L~~
I
7.WllllllplIlIlI!.V>/.
A16-
ADO- I
-II Vlllli
Y,
ADDRESS VALID
,-
•""AOOR. I}.Qlh I?lJc
-
}.
DATA
~
I-
IV
ADSl'
01 i
rC
~
-17J
i\
HBE [ 7.
Y,
VALID
,,,
Dvl
~
~
r\
o l'
II
-
WRl
10
\
Kn
II
u{
I
'-
{
DAI.
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NS: ~2201 SIGN ~LS
iYR[
r\
II
TL/EE/8701-8
FIGURE 2·7. Direct I/O·To·Memory Data Transfer (Single Transfer Mode)
4·57
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....o
NS32203-10
A
...
a,
<
ADS
STO-3
ROY
HLDA
ODIN
PHil
PHI2
HOLD
ADS
STO-3
~ ROY
HLDAI
ODIN
PHil
PHI2
HOLD
RSTI
HLDAO
.::
PHil
PHI2
NS32201
TCU
ADS
RST
ODIN
RDY
CTIL
ViR
Ro
NS32082
MMU
--+ Rii
...
PAY
f--
D.iJ
I
v
I
11
HLDA
HBE
' - - - HOLD
CS
ADS
ACKO
RST
DDiN NS32203
RDY
DMAC REOO
U~I
BREO
ACKI
REal
ACK2
RE02
ACK3
RE03
lORD
10WR
~DR
>.
n°
e!.
cCD
00-15
.<
(I)
n
~.
"tl
o::::I·
DO-1St-.
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g.
ADDRESS
LATCHES
c:
CD
II
fr-,J).
L~6-23
DO-I~ j
cm
r--
~
::::I
MEMORY
'" 7
,K
A
DATA
BUFFERS 'I
L ~1f-i}5
tlJ
o·
HBE
CS
r---+
.---
IIII III
'I
::::I
n
PFS
u/s
U~~
(X)
c:::
RSTI ABT
u/s
D.
."
FLT
HBE
A16-23 DO-IS
<-
b
Ar/SPC
FLT
RSTj ABT
PFS
NS32016
CPU
N
INT
NMI
Ar/SPC
.e,
AO - 23~1\.
'~~~
--DECODER
L
D.
ADDR 00-15
ADDR 00-7
16-BIT I/O
DEVICE
8-BIT I/O
DEVICE
CS
r+CS
REO
---+
RiiViR
REO
Rii ViR
~
~
TL/EE/8701-9
FIGURE 2-8. NS322031nterconnections In Local Configuration
Note 1: The 16 Bit 110 device is wired for direct transfers.
Note 2: The data buffers should not be enabled during direct data transfers or CPU accesses to the DMAC registers.
z
2.0 Functional Description
(f)
Co)
(Continued)
The CPU can either be interrupted by BGRT or it can poll
BGRT to determine when the dedicated bus can be ac·
cessed. The DMAC, in turn, before accessing the CPU bus,
has to gain control of it. This is accomplished through the
usual request·acknowledge mechanism performed by
means of the HOLD and HLDA signals.
2.4 REMOTE CONFIGURATION
The remote configuration is intended to minimize CPU Bus
usage. In this configuration, the DMAC, buffer memory and
110 devices reside on a dedicated bus. Communication be·
tween the dedicated bus and the CPU bus is achieved by
means of TRI·STATE buffers. Whenever the CPU needs to
access the dedicated bus, it issues a bus request to the
NS32203 by activating the BREQ signal. As the dedicated
bus becomes idle, the DMAC pulls off the bus and acknowl·
edges the CPU request by activating BGRT. This output is
also used as a control signal for the interconnection logic of
the two buses.
T1
Figure A-1 in Appendix A shows an interconnection diagram
of a basic remote configuration. Both TCUs are clocked by
the same clock signal. They are synchronized during reset
by the RWEN/SYNC signal so that their output clocks are in
phase. Figures 2-9 and 2-10 show the timing diagrams for
read and write accesses to the NS32203 internal registers.
T2
eLK [
ADS [
ADO-15 [
DDIN [
HBE [
es[
NS32201 SIGNALS
Wil[
TL/EE/B701-10
FIGURE 2-9. Write to NS32203 Internal Registers
T1
T2
T3
ADO-15 [
DDIN[-r~__~____r-__~____~~__4HBE
[~r'-__~__~~____+-____~~__~
es[
Rii[
NS32201 SIGNALS
TLiEE/B701-11
FIGURE 2-10. Read from NS32203 Internal Registers
4-59
N
N
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ch
C)
N
N
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Z
2.0 Functional Description (Continued)
2.5 DATA SOURCE (DESTINATION) ATTRIBUTES
2.7 AUTO TRANSFER
Two types of data source (destination) are recognized: I/O
device and memory. If the source (destination) is an I/O
device, its address register is not changed after a data
transfer; if it is memory, its address register is either incremented or decremented after any data transfer, according
to the value of the corresponding direction bit. In the remote
configuration, any data source (destination) may reside either on the CPU bus or on the dedicated bus. If it resides on
the dedicated bus, the NS32203 does not activate the
HOLD request line when an access to the source (destination) is performed, unless a direct transfer with a data destination (source) residing on the CPU bus is required.
The NS32203 initiates a data transfer as a result of a request from an I/O device. In some cases a data transfer
may be necessary without the corresponding request signal
being asserted. This can happen, for example, when a block
of data is to be moved from one memory region to another.
In such cases, the auto transfer mode can be selected by
setting an appropriate bit in the command register. The
DMAC will initiate a data transfer regardless of the REOn
signal for that channel.
Nole: For proper operation, when auto transfer is required, the low order
byte of the command register (containing the auto·transfer enable bit)
should be written Into aiter the other registers conirolling the channel
operation have been initialized.
Data can be transferred in either B bit or 16 bit units. The
DMAC always considers the memory to be 16 bits wide.
Thus, if an a bit transfer is specified, address bit AO will
determine the byte of the data-bus where the transfer takes
place. If AO = 0, the transfer occurs on the low order byte.
If AO = 1, it occurs on the high order byte. Different transfer
widths can be specified for source and destination. However, some limitations exist in specifying these transfer widths
when certain operations must be performed. These limitations are explained below.
2.8 SEARCH
The NS32203 provides a search capability that can be used
to detect the occurrence of a certain data pattern. The
search is performed by comparing each data byte with the
search register, in conjunction with the mask register. An
appropriate bit in the command register indicates whether
the search continues 'UNTIL' a match occurs, or 'WHILE' a
match exists. The search operation does not necessarily
involve a data transfer. The DMAC allows a block of data to
be searched without requiring any data transfer between
source and destination. When performing a search, the user
can specify whether or not the matched byte will be transferred. If 'INCLUSIVE SEARCH' is specified (INC = 1), the
matched byte will be transferred, and the channel parameters will be updated accordingly. In this case, if a 16 bit word
has been read from the data source and the search condition is satisfied by the low order byte, then the high order
byte is transferred as well. If 'EXCLUSIVE SEARCH' is
specified (INC = 0), the transfer will terminate with the last
byte before the search condition was satisfied, and the parameters will pOint to the last transferred byte.
1) If a transfer block has an odd number of bytes or is not
word aligned, an a bit width for source and destination
should be selected.
2) 16-bit I/O transfers can not be specified with a bit
memory transfers.
3) Memory to memory transfers should have the same
width.
Note 1: If source and destination are both memory. DMAC transfers can
only be performed in indirect mode.
Note 2: If source and destination are both 1/0 devices and direct mode is
being used, the source device is accessed by lORD and ACKn; the
destination device is accessed by WR (from the NS32201) and CS
(from the address decoder). This allows a one direction data trans·
fer only from one 1/0 device (source) to another. If data is to be
transferred in both directions in direct mode between two 110 devioBS, two channels must be used (one for each direction of transfer).
and extra hardware is required to control the read and write signals
to the two 1/0 devices.
Search is not possible during direct transfers.
2.9 INTERRUPTS
The NS32203 provides interrupt circuitry that can be used to
generate an interrupt whenever a data transfer is completed
or a search condition is met. If an NS32202 ICU is used, the
INT signal from the DMAC should be connected to an interrupt input of the ICU. When an interrupt occurs and the
corresponding interrupt acknowledge (INTA) or return from
interrupt (RETI) cycle is executed by the CPU, the NS32203
supplies its own vector as if it were a cascaded ICU. For
such operation the virtual address of the interrupt vector
register should be placed in the ICU cascade table, described in the NS32016 and NS32202 data sheets. See
section 3.1.2.
Note 3: When an 8·bn transfer is related to an 1/0 device, the other half of
the 16·bit data bus is considered as DON'T CARE, and the HBEI
signal may be activated.
2.6 WORD ASSEMBLY/DISASSEMBLY
This feature is automatically enabled when indirect transfers
are selected, with data transferred between an a-bit wide
I/O device and a 16-bit I/O device or memory. For every 16bit I/O device or memory access, the DMAC accesses the
a-bit I/O device twice, assembling two data bytes into a 16bit word or breaking a 16-bit word into two data bytes, depending on the direction of transfer. The word assembly/disassembly feature allows a Significant increase in the
transfer speed and minimizes the CPU bus usage when the
transfer occurs between an a-bit I/O device residing on the
dedicated bus, and a 16-bit I/O device or memory residing
on the CPU bus. Word assembly/disassembly is not possible during direct data transfers.
2.10 TRANSFER MODES
When the NS32203 is in the inactive state and a channel
requests service, the DMAC gains control of the bus and
enters the active state. It is in this state that the data transfer takes place in one of the following modes:
SINGLE TRANSFER MODE
In single transfer mode, the NS32203 makes a single byte
or word transfer for each HOLD/HLDA handshake sequence.
Nole: Requests from other channels are not acknowledged in the middle of
a word assembly/disassembly. If this is unacceptable, 8 bit transfers
should be speCified for both source and destination.
In this case the request signal from the I/O device is edge
sensitive, that is, a single transfer is performed each time a
4-60
z
~
2.0 Functional Description
(Continued)
falling edge on REOn occurs. To perform multiple transfers,
it is therefore necessary to temporarily deassert REOn after
each transfer is initiated. If auto transfer mode is selected,
the bus is released between two transfers for at least one
clock cycle.
The priority resolver checks the priorities on every cycle. If a
channel is being serviced and a higher priority request is
received, the channel operation is suspended and control
passes to the higher priority channel, unless the lock bit for
the lower priority channel is set. If the lock bit is set, that
channel operation is continued until completion before control passes to the higher priority channel. The bus is always
released for at least two clock cycles when control passes
from one channel to another.
BURST (DEMAND) TRANSFER MODE
In burst transfer mode the DMAC will continue making data
transfers until REOn goes inactive. Thus, the I/O device
requesting service may suspend data transfer by bringing
REOn inactive. Service may be resumed by asserting REOn
again. If the auto transfer mode is selected, the DMAC will
perform a single burst of data transfers until the end-transfer
condition is reached.
.
o
Co:!
.....
o
Two types of priority encodings are available as software
selectable options.
The first is fixed priority which fixes the channels in priority
order based on the decreasing values of their numbers.
Channel 3 has the lowest priority, while channel 0 has the
highest.
The second option is variable priority. The last channel that
receives service becomes the lowest priority channel
among all other channels with variable priority, while the
channels which previously had lower priority will get their
priorities increased. If variable priority is selected for all four
channels, any I/O device requesting service is guaranteed
to be acknowledged after no more than three higher priority
services have occurred. This prevents any channel from
monopolizing the system. Priority types can be intermixed
for different channels.
As an example, let channels 0, 2 and 3 have variable priority
and channel 1 fixed priority. Channel 2 receives service first,
followed by channel O. The priority levels among all channels will change as follows.
Nole 1: In either of the transfer modes described above, data transfers can
only occur as long as the byte count is not zero or a search condi·
tion is not mel Whenever any of these conditions occur, the
NS32203 terminates the current operation and releases the bus for
at least one clock cycle.
Note 2: Whenever the OMAC releases
N
N
FiOD5, it waits for HLOA to go inae·
tive for at least one clock cycle before reasserting HOLD again to
continue the transfer operation.
2.11 CHAINING
The NS32203 provides a chaining feature that allows the
four DMAC channels to be regarded as two complementary
pairs. Channels 0 and 1 form the first pair, while channels 2
and 3 form the second pair. Each pair is programmed independently by setting the corresponding bit in the configuration register. When two channels are complementary, only
the even channel can perform transfer operations, while the
odd one serves as temporary storage for the new control
values and parameters loaded for the chaining operation. If
an operation is being performed by the even channel of a
pair and an end-condition is reached, the channel is not
returned to the inactive state; rather, a new set of control
values with or without parameters is loaded from the complementary channel and a new operation is started. During
the reload operation the bus is released for at least two
clock cycles. At the end of the second operation the channel returns to the inactive state, unless a new set of values
has been loaded into the complementary channel by the
CPU.
Priority Initial Order Next Order
Final Order
High 3
ch.O ACK -+ ch.O
ch.3
ch.1 ch.1 -+ fixed priority
ch.1
2
ch.3
ch.2
1 ACK-+ ch.2
Low 0
ch.3
ch.2
ch.O
Whenever the PT bit (priority type) in the command register
is changed, the priority levels of all the channels are reset to
the initial order. If only one channel has variable priority,
then no change in priority will occur from the initial order.
Note: If the lock bit is not set, three idle states are inserted between the
write cycle of a previous burst indirect transfer and the next read
cycle.
The chaining feature can be used to transfer blocks of data
to/from non-contiguous memory segments. For example,
the CPU can load channel 0 and 1 with control values and
parameters for the first two blocks. After the operation for
the first block is completed by channel 0, the control values
and parameters stored in channel 1 are transferred to channel 0, during an update cycle, and a second operation is
started. The CPU, being notified by an interrupt, can load
channel 1 registers with control values and parameters for
the third data block.
3.0 Architectural Description
The NS32203 has 128 8-bit registers that can be addressed
either individually or in pairs, using the 7 least significant bits
of the address bus and the high byte enable signal HBE.
Seventy-one of these registers are reserved, while the rest
are accessible by the CPU for read/write operations. Figure
3-1 shows the NS32203 internal registers together with their
address offsets. Detailed descriptions of these registers are
given in the following sections.
Note 1: Whenever a reload operation occurs, the register values of the com·
plementary channel are affected. Thus. the CPU must always load a
new set of values into the complementary channel if another chain·
ing operation Is required.
3.1 GLOBAL REGISTERS
The global registers consist of one configuration, one status
and two interrupt vector registers. They are shared by all
channels, and they control the overall operation of the
NS32203.
Note 2: When the chain option is selected. the CPU must be given the opportunity to acquire the bus for enough time between DMAC opera·
tions, in order for the complementary channel to be updated.
2.12 CHANNEL PRIORITIES
The NS32203 has four I/O channels, each of which can be
connected to an I/O device. Since no dependency exists
between the different I/O devices, a priority level is asSigned to each I/O channel, and a priority resolver is provided to resolve multiple requests activated simultaneously.
3.1.1 CONF-Configuration Register
This register controls the hardware configuration of the
NS32203 as well as the chaining feature.
4-61
•
....
Q
cJ:.
3.0 Architectural Description
(Continued)
C")
The CONF register format is shown below:
7
4
6
5
3
2
1
0
Q
C\I
C\I
tn
I I I
xxxxx
Z
CNF -
Cl
CO
CO = 1 =
CNF = 1 =
>
>
> Channels not complementary
> Channel 1 complementary to channelO
CNF
Configuration Bit. Determines whether
NS32203 is in local or remote configuration.
CNF = 0 =
CO-
CO = 0 =
Cl-
the
local Configuration
Chaining bit for channels 2 and 3. Determines
whether or not channels 2 and 3 are complementary.
Cl = 0 =
Remote Configuration
Cl = 1 =
Chaining bit for channels 0 and 1. Determines
whether or not channel 0 and 1 are complementary.
> Channels not complementary
> Channel 3 complementary to channel2
XXXXX -
Reserved. These bits should be set to O.
At reset, all CONF bits are reset to zero.
Note: The CNF bit should never be set by the software H the DMAC is wired
for local configuration, otherwise bus conflicts will result
23
Channel 0
Control
Registers
Channel 0
Parameter
Registers
Channell
Control
Registers
Channell
Parameter
Registers
Channel 2
Control
Registers
Channel 2
Parameters
Registers
Channel 3
Control
Registers
Channel 3
Parameter
Registers
Global
Registers
16
8
15
0
{
MSK
(0816)
Search Mask
{
{
{
{
SRC(H)
(OE16)
SRC(M)
(0016)
SRC(l)
(OC16)
Source Address
DST(H)
(1216)
DST(M)
(1116)
DST(l)
(1016)
Destination Address
lNGT(H)
(1516)
lNGT(l)
(1416)
Block length
COM(M)
(21 16)
COM(l)
(2016)
Command
SRCH
(2416)
Search Pattern
MSK
(2816)
Search Mask
{
{
{
{
COM(H)
(0216)
(2216)
COM(M)
7
COM(H)
(01 16)
COM(l)
(0016)
Command
SRCH
(0416)
Search Pattern
SRC(H)
(2E16)
SRC(M)
(2016)
SRC(l)
(2C16)
Source Address
DST(H)
(3216)
DST(M)
(31 16)
DST(l)
(3016)
Destination Address
lNGT(H)
(3516)
lNGT(l)
(3416)
Block length
COM(M)
(41 16)
COM(l)
(4016)
Command
SRCH
(4416)
Search Pattern
MSK
(4816)
Search Mask
COM (H)
(4216)
SRC(H)
(4E16)
SRC(M)
(4016)
SRC(l)
(4C16)
Source Address
DST(H)
(5216)
DSC(M)
51 16)
DST(l)
(5016)
Destination Address
lNGT(H)
(5516)
lNGT(l)
(5416)
Block length
COM(M)
(61 16)
COM(l)
(6016)
Command
SRCH
(6416)
Search Pattern
COM (H)
(6216)
MSK
(6816)
Search Mask
SRC(H)
(6E16)
SRC(M)
(6016)
SRC(l)
(6C16)
Source Address
DST(H)
(7216)
DST(M)
(71 16)
DST(l)
(7016)
Destination Address
lNGT(H)
(7516)
lNGT(l)
(7416)
Block length
CONF
(7816)
Configuration
SVCT
(5C16)
Software Vector
HVCT
(7C16)
Hardware Vector
STAT(l)
(7E16)
Status
STAT(H)
(7F16)
FIGURE 3-1. NS32203 Internal Registers
4-62
z
(J)
3.0 Architectural Description (Continued)
15 14 13 12 11 10
3.1.2 HVCT - Hardware Vector Register
E
channel #3
Channel number. Represents the number of the interrupting channel
E-
Error code. Determines whether a normal operation
completion or an error condition has occurred on
the interrupting channel.
7
6
5
4
3
2
1
0
channel #2
channel #1
channel #0
The status of each channel is defined in a four-bit field as
described below:
TC- Transfer Complete.
Indicates the completion of a channel operation, regardless of the state of the length register or whether
a match/no match condition occurred.
MN - Match/No Match Bit.
This bit is set when a match/no match condition occurs.
CH - Channel Halted.
Set when a channel operation is halted by pulling the
RST/HLT pin.
CN
CN -
8
IMElcHIMNITCIMElcHIMNITCIMElcHIMNITCIMElcHIMNITCI
This register contains the interrupt vector byte that is supplied to the CPU during an interrupt acknowledge (lNTA) or
return from interrupt (RETI) cycle. The HVCT register format
is shown below.
765432
0
BIAS
9
E = 0 = > Normal Operation Completion
E = 1 = > A second interrupt was generated by
the same channel before the first interrupt was serviced.
BIAS - Programmable bias. This field is programmed by
writing the pattern BBBBBOOO into the HVCT register.
ME -
Multiple events. This bit is set when more than one of
the above conditions have occurred.
Note: If an interrupt is enabled, the corresponding bit in the status register is
not cleared upon read, unless the interrupt is acknowledged.
3.2 CONTROL REGISTERS
Each of the four channels has three control registers, consisting of a 24-bit command register, an S-bit search register
and an S-bit mask register.
The NS32203 always interprets a read of the HVCT register
as either an interrupt acknowledge (INTA) cycle or a return
from interrupt (RETI) cycle. Since these cycles cause internal changes to the DMAC, normal programs should never
read the HVCT register (see next section). The DMAC distinguishes an INTA cycle from a RETI cycle by the state of
an internal flip-flop, called Interrupt Service Flip-Flop, that
toggles every time the HVCT register is read. This flip-flop is
cleared on reset or when the HVCT register is written into.
When an interrupt is acknowledged by the CPU, the INT
signal is deasserted unless another interrupt from a lower
priority channel is pending. In this case the INT signal is
deasserted when the acknowledge cycle for the second interrupt is performed.
3.2.1 COM - Command Register
The command register controls the operation of the associated channel. It is divided into three separately addressable
parts: COM(L), COM(M) and COM(H). The format of each
part and bit functions are shown below.
COM(L) - Command Register (Low-Byte)
7
6
5
4
3
2
1 0
I AT I LK I PT I UW I INC I 01
For this reason, if the INT signal is connected to an interrupt
input of the NS32202 ICU, the triggering mode of that interrupt position should be 'low level'.
CC -
Command Code
CC =00 = >Channel Disabled.
CC =01 = > Search
Furthermore, if that ICU interrupt input is programmed for
cascaded operation and nesting of interrupts from other devices connected to the ICU is to be allowed, then the ICU
interrupt input connected to the DMAC should be masked
off during the interrupt service routine, before the CPU interrupt is reenabled. This is because the DMAC does not provide interrupt nesting capability.
CC = 10 = > Data Transfer
CC = 11 = > Data Transfer and Search
01- Direct/Indirect Transfers
01 = 0 = > Indirect Transfers
01 = 1 = > Direct Transfers
An interrupt from a certain channel can be acknowledged
only after the return from interrupt from a previously acknowledged interrupt is performed.
INC -Inclusive/Exclusive Search
3.1.3 SVCT - Software Vector Register
The SVCT register is an image of the HVCT register. It is a
read-only register used for diagnostics. It allows the programmer to read the interrupt vector without affecting the
interrupt logic of the NS32203. The format of the SVCT register is the same as that of the HVCT register.
UW -
INC = 0 = > Exclusive Search
INC = 1 = > Inclusive Search
Search type
UW =0 = >Search UNTIL
UW = 1 = > Search WHILE
3.1.4 STAT - Status Register
The status register contains status information of the
NS32203, and can be used when the interrupts are not enabled. Each set bit is automatically cleared when a read
operation is performed. The format of this register is shown
in the following figure.
PT -
Priority type
PT =0 = > Fixed
PT = 1 = > Variable
LK -
Priority lock
LK = 0 = > Priority Unlocked
LK = 1 = > Priority Locked
4-63
cc
I
~
~
o
(0)
.....
I
o
C)
....
~
N
~
Z
r-------------------------------------------------------------------------------------~
3.0 Architectural Description (Continued)
AT -
Auto transfer
AT =0 = > Auto Transfer Disabled
AT = 1 = > Auto Transfer Enabled
At Reset, the CC bits in COM(L) are cleared, disabling the
channel.
AMN -
Action after Match/No Match
AMN = 00 = > Disable Channel
AMN = 01 = > Continue
AMN = 10 = > Load Control Values from Comple·
mentary Channel and Continue
AMN = 11 = > Load Control Values and Parame·
ters from Complementary Channel
and Continue
TCI-
Interrupt Mask on "Transfer Complete"
TCI = 0 = > No Interrupt
TCI = 1 = > Interrupt
Nole: The CC bits can be cleared by software during an Indirect data tran ..
fer to stop the transfer. This, however, should not be done during
direct data transfers. See section 3.3.3.
COM(M) • Command Register (Middle·Byte)
76543210
lool~I~lwlwl_I&I~1
ST -
Source Type
ST = 0 = > 1/0 Device
ST =1 =>Memory
SL -
Source Location
(Effective only in the remote configuration)
SL =0 = > Local
SL =1 = > Remote
SW -
MNI- Interrupt Mask on "MatchlNo Match"
MNI =0 = > No Interrupt
MNI = 1 = > Interrupt
HU-
3.2.2 SRCH - Search Register
This a·bit register holds the value to be compared with the
data transferred during the channel operation.
Source Width
SW =0 => a Bits
SW =1 =>16 Bits
3.2.3 MSK - Mask Register
The a·bit mask register determines which bits of the trans·
ferred data are compared with corresponding search regis·
ter bits. If a mask register bit is set to 0, the corresponding
search register bit is ignored in the compare operation. At
reset, all the MSK bits are set to O.
SD -
Source Direction
SD =0 =>Up
SD =1 =>Down
DT -
Destination Type
DT =0 = > 1/0 Device
SD =1 = > Memory
DL -
Destination Location
(Effective only in the remote configuration)
DL =0 = > Local
DL =1 =>Remote
DW -
Destination Width
DW =0 => a Bits
DW =1 => 16 Bits
DD -
Destination Direction.
DD =0 => Up
DD =1 =>Down
3.3 PARAMETER REGISTERS
Each channel has three parameter registers, conSisting of a
24·bit source address register, a 24·bit destination address
register and a 16·bit block length register.
3.3.1 SRC - Source Address Register
The source address register points to the physical address
of the data source. When the data source is an I/O device,
the register does not change during the transfer operation.
When the data source is memory, the register is increment·
ed or decremented by either one or two after each transfer.
3.3.2 DST - Destination Address Register
The destination address register points to the physical ad·
dress of the data destination. When the data destination is
an I/O device, the register does not change during the
transfer operation. When the data destination is memory,
the register is incremented or decremented by either one or
two after each transfer.
COM (H) • Command Register (High·Byte)
7
6
5
I HU' MNd TCI'
XTM -
ATC -
4
AMN
Interrupt Mask on "Channel Halted"
HU = 0 = > No Interrupt
HU = 1 = > Interrupt
3
2
1
0
3.3.3 LNGT - Block Length Register
The block length register holds the number of bytes in the
block to be transferred. It is decremented by either one or
two after each transfer.
IATC' DM' X
Reserved. (Should be set to 0)
Transfer Mode
DM = 0 = > Single Transfer
DM = 1 = > Burst Transfer
Note: A direct data transfer can be stopped by writing zeroes into the LNGT
register. The number of bytes transferred can be determined in this
case, from the value of either the SRC or the DST register.
Action after Transfer Complete
ATC = 0 = > Disable Channel
ATC = 1 = > Load Control Values and Parame·
ters from Complementary Channel
and Continue
4·64
zCJ)
4.0 Device Specifications
Chip Select (CS): When low, the device is selected, enabling CPU access to the DMAC internal registers.
4.1. NS32203 PIN DESCRIPTIONS
The following is a brief description of all NS32203 pins. The
descriptions reference portions of the Functional Description, Section 2.0.
Ready (ROY): Active high. When inactive, the DMA Controller extends the current bus cycle for synchronization with
slow memory or peripherals. Upon detecting RDY active,
the DMAC terminates the bus cycle.
Connection Diagram
Channel Request 0-3 (REQO - REQ3): Active low. These
lines are used by peripheral devices to request DMAC service.
Bus Request (BREQ): Used only in the remote configuration. This signal, when asserted, forces the DMAC to stop
lransferring data and to release the bus. It must be activated
by the CPU before any CPU access to the remote bus is
performed. In the local configuration this Signal should be
connected to Vee via a 4.7k resistor. Section 2.4.
Hold Acknowledge (HlDA): Active low. When asserted,
indicates that control of the system bus has been relinquished by the current bus master and the DMAC can take
control of the bus.
Clock (ClK): Clock signal supplied by the CTTL output of
the NS32201 TCU.
A22
A21
A20
A19
BREQ
A18
A17
RST/HlT
A16
iNi'
AD15
HOLD
AD14
HlDA
AD13
REQ3
AD12
ACK3
AD11
REQ2
AD10
ACK2
AD9
REQ1
AD8
ACKI
AD7
REQD
AD6
ACKD
ADS
HBE
AD4
ODIN
AD3
lORD
AD2
IOWR
ADI
ADS
ADO
ROY
GND
ClK
4.1.3 OUTPUT SIGNALS
Address Bits 16-23 (AI6-A23): Most significant 8 bits of
the address bus.
Hold Request (HOLD): Active low. Used by the DMAC to
request control of the system bus.
Channel Acknowledge 0-3 (ACKO - ACK3): These lines
indicate that a channel is active. When a channel's request
is honored, the corresponding acknowledge line is activated
to notify the peripheral device that it has been selected for a
transfer cycle. Section 2.2.2.
Bus Grant (BGRT): Used only in the remote configuration.
This signal is used by the DMAC to inform the CPU that the
remote bus has been relinquished by the DMAC and can be
accessed by the CPU. Section 2.4.
I/O Read (lORD): Active low. Enables data to be read from
a peripheral device. Section 2.2.2.
I/O Write (IOWR): Active low. Enables data to be written to
a peripheral device. Section 2.2.2.
Interrupt (I NT): Active low. Used to generate an interrupt
request when a programmed condition has occurred. Section 2.9.
TL/EE/B701-12
Top View
FIGURE 4-1. NS32203 Dual-In-Line Package
Order Number NS32203D or NS32203N
See NS Package Number D48A or N48A
4.1.4 INPUT/OUTPUT SIGNALS
Address/Data 0-15 (ADO-AD 15): Multiplexed Address/
Data bus lines. Also used by the CPU to access the DMAC
internal registers.
4.1.1 SUPPLIES
Power (Vee>: +5V positive supply.
Ground (GND): Ground reference for on-chip logic.
4.1.2 INPUT SIGNALS
Reset/Halt (RST/HlT): Active low. If held active for 1 or 2
clock cycles and released, this signal halts the DMAC operation on the active channel. If held longer, it resets the
DMAC. Section 2.1.
High Byte Enable (HBE): Active low. Enables data transfers on the most significant byte of the data bus.
Address Strobe (ADS): Active low. Controls address latches and indicates the start of a bus cycle.
Data Direction in (ODIN): Active low. Status signal indicating the direction of data flow in the current bus cycle.
4-65
Co)
I\)
I\)
oCo)
....o•
o
.....
""o
N
N
C')
en
z
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
O°Cto + 70°C
Storage Temperature
-65°C to + 150°C
All Input or Output Voltages with
Respect to GND
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
-0.5Vto +7V
Power Dissipation
1.1 Watt
4.3 ELECTRICAL CHARACTERISTICS T A = 0 to + 700C, Vee = 5V ± 5%, GND = OV
Symbol
V,H
Parameter
Conditions
V,L
Low Level Input Voltage
VOH
High Level Output Voltage
IOH = -400/LA
VOL
Low Level Output Voltage
IOL = 2mA
I,
Input Load Current
0< V,N';; Vee
IL
Leakage Current
Output and I/O Pins in TRI-STATElinput Mode
0.4 ,;; Y,N ,;; Vee
ICC
Active Supply Current
lOUT = 0, TA = 25°C
4.4 SWITCHING CHARACTERISTICS
ABBREVIATIONS:
L.E. T.E. -
-
1 O.BV
2.0V
Typ
Units
Vee + 0.5
V
-0.5
O.B
V
0.45
V
-20
20
/LA
-20
20
/LA
300
mA
2.4
4.4.1 Definitions
All the timing specifications given in this section refer to
O.BV and 2.0V on all the input and output signals as illustrated in Figures 4-2 and 4-3, unless specifically stated otherwise.
ClK _
Max
2.0
Min
High Level Input Voltage
leading edge
trailing edge
ClK
V
1BO
R.E. - rising edge
F.E. - falling edge
2.0V
O.BV
~tSIGI~
SIGI
SIG2
~.
SIGI
O.BV
--
,"O.BV
ls'GIIi---
2.0V
lslG2ht==:
SIG2
TL/EE/B701-13
FIGURE 4·2. Timing Specification Standard
(Signal Valid after Clock Edge)
2.0V
TLlEE/B701-14
FIGURE 4·3. Timing Specification Standard
(Signal Valid before Clock Edge)
4-66
z
CJ)
4.0 Device Specifications (Continued)
Co)
N
N
oCo)
4.4.2 Timing Tables
•
.....
o
4.4.2.1 Output Signals: Internal Propagation Delays, NS32203-10
Maximum Times Assume Capacitive Loading of 100 pF.
Name
Figure
Reference!
Conditions
Description
NS32203-10
Min
Units
Max
tALv
4-7
Address Bits 0-15 Valid
After R.E., CLK T1
tALh
4-9
Address Bits 0 -15
Hold Time
After R.E., CLK T2
50
tAHv
4-7
Address Bits 16-23 Valid
After R.E., CLK T1
tAHh
4-7
Address Bits 16-23 Hold
After R.E., CLK T1
orTi
5
ns
tALAOSs
4-8
Address Bits 0-15 Set Up
Before ADS T.E.
25
ns
tAHAOSs
4-8
Address Bits 16-23 Set Up
Before ADS T.E.
25
ns
tALAOSh
4-9
Address Bits 0-15
Hold Time
After ADS T.E.
15
,","S
tAU
4-8
Address Bits 0-15 Floating
After R. E., CLK T2
25
ns
toy
4-7
Data Valid (Write Cycle)
After R.E., CLK T2
50
ns
tOh
4-7
Data Hold (Write Cycle)
After R.E., CLK T1
orTi
toOv
4-5
Data Valid (Reading
DMAC Registers)
After R.E., CLK T3
tOOh
4-5
Data Hold (Reading
DMAC Registers)
After R.E., CLK T 4
5
ns
ns
50
0
ns
ns·
50
10
tHBEv
4-7
HBE Signal Valid
After R.E., CLK T1
tHBEh
4-7
HBE Signal Hold
After R.E., CLK T1
orTi
tOOINv
4-8
DDIN Signal Valid
After R.E., CLK T1
tOOINh
4-8
DDIN Signal Hold
After R.E., CLK T1
orTi
tAOSa
4-7
ADS Signal Active
After R.E., CLK T1
35
ns
tAOSia
4-7
ADS Signal Inactive
After R.E., CLK T1
40
ns
tAOSw
4-7
ADS Pulse Width
atO.8V
(Both Edges)
50
0
ns
ns
65
0
ns
ns
30
ns
tALz
4-12.4-13
ADO-AD15 Floating
After R.E., CLK Ti
55
tAHz
4-12,4-13
A16-A23 Floating
After R.E., CLK Ti
55
ns
tAOSz
4-12,4-13
ADS Floating
After R.E., CLK Ti
55
ns
tHBEz
4-12,4-13
HBE Floating
After R.E., CLK Ti
55
ns
tOOINz
4-12,4-13
DDiN Floating
After R.E., CLK Ti
55
ns
tHLOa
4-11
HOLD Signal Active
After R.E., CLK Ti
50
ns
tHLOia
4-12
HOLD Signal Inactive
After R.E., CLK Ti
orT4
50
ns
ns
tlNTa
4-19,4-21
INT Signal Active
After R.E., CLK Ti
40
ns
tACKa
4-16,4-17,4-7
ACKn Signal Active
After R.E., CLK T1
50
ns
tACKia
4-16,4-17,4-7
ACKn Signal Inactive
After F.E., CLK T4
35
ns
4-67
4.0 Device Specifications
Name
Figure
(Continued)
Referencel
Conditions
Description
NS32203-10
Min
Units
Max
tSGRTa
4-13
BGRT Signal Active
After R.E., ClK
65
tSGRTIa
4-14
BGRT Signal Inactive
After R.E., ClK
65
ns
ns
tlORDa
4-B,4-9
lORD Active
After R.E., ClK T2
40
ns
tlORDia
4-B
lORD Inactive (During
Indirect Transfers)
After R.E., ClK T4
40
ns
tlORDia
4-9
lORD Inactive (During
Direct Transfers)
After F.E., ClK T4
40
ns
tlOWRa
4-7,4-10
IOWRActive
After R.E., ClK T2
40
ns
tlOWRia
4-7
IOWR Inactive (During
Indirect Transfers)
After R.E., ClK T4
40
ns
tlOWRdia
4-10
IOWR Inactive (During
Direct Transfers)
After F.E., ClK T3
40
ns
4.4.2.2 Input Signal Requirements: NS32203-10
tpWR
4-22
Power Stable to
RSTIHlT R.E.
After Vee Reaches
4.75V
tRSTw
4-23
RSTIHlT Pulse Width
(Resetting the DMAC)
at O.BV (Both Edges)
tRSTs
4-24
RSTIHlT Set Up Time
(Resetting the DMAC)
Before F.E., ClK
tHLTs
4-1B
RSTIHlT Setup Time
(Halting a DMAC Transfer)
Before R.E., ClK T3
tHLTh
4-19
RSTIHlT Hold Time
After R.E., ClK T4
(Halting a DMAC Transfer)
50
I1s
64
tCp
15
ns
25
ns
10
ns
tDls
4-6
Data in Setup Time
Before R.E., ClK T3
15
ns
tDlh
4-6
Data in Hold
After R.E., ClK T4
3
ns
tDls
4-6
Data in Setup Time
(Writing to DMAC Registers)
After R.E., ClK T3
15
ns
tDih
4-6
Data in Hold
(Writing to DMAC Registers)
After R.E., ClK T4
3
ns
tHLDAs
4-11,4-12
HOLDA Setup Time
Before R.E., ClK
25
ns
tHLDAh
4-11
HlDA Hold Time
After R.E., ClK
10
ns
tRDYs
4-15
RDY Setup Time
Before R.E.,
ClKT20rT3
20
ns
tRDYh
4-15
RDY Hold Time
After R.E., ClK T3
5
ns
tREQs
4-16,4-17
REOn Setup Time
Before R.E., ClK
50
ns
tREQh
4-16,4-17
REOn Hold Time
After R.E., ClK
10
tSREQs
4-13
BREO Setup Time
Before R.E., ClK
25
4-6B
ns
z
4.0 Device Specifications
Name
Figure
en
Co)
(Continued)
N
N
Referencel
Conditions
Description
tBREQh
4·13
BREQ Hold Time
tALADSis
4·6
tALADSih
NS32203-10
Min
C)
Units
Max
Cf
.....
C)
After R.E., ClK
10
ns
Address Bits 0-5 Setup
Before ADS T.E.
20
ns
4·6
Address Bits 0-5 Hold
After ADS T.E.
20
ns
tHBEs
4·6
HBE Setup Time
Before R.E., ClK T1
10
ns
tHBEih
4·6
HBE Hold Time
After R.E., ClK T4
40
ns
tADSs
4·6
ADS L.E. Setup Time
Before R.E., ClK T1
40
ns
tADSiw
4·6
ADS Pulse Width
ADS L.E. to ADS T.E.
35
ns
tCSs
4·6
CS Setup Time
Before R.E., ClK T1
15
ns
tCSh
4·6
CSHoldTime
After R.E., ClK T4
40
ns
tDDINs
4·6
DDIN Setup Time
Before R.E., ClK T2
30
ns
tDDINh
4·6
DDIN Hold Time
After R.E., ClK T 4
40
ns
4.4.2.3 Clocking Requirements: NS32203-10
Name
Figure
Referencel
Conditions
Description
NS32203-10
Min
Units
Max
tClKh
4·4
Clock High Time
At 2.0V (Both Edges)
42
ns
tclKl
4·4
Clock low Time
At 0.8V (Both Edges)
42
ns
tClKp
4·4
Clock Period
R.E., ClK to Next
R.E. ClK
100
ns
4.4.3 Timing Diagrams
r.--tCLJ(Pi
~
2.0V
elK...J
r
C.BV
tCLJ(1
TLlEE/B701-17
FIGURE 4-4. Clock Timing
•
4·69
o ,-----------------------------------------------------------------------------,
....
•
C")
~
4.0 Device Specifications (Continued)
C'I
~
Z
11
12
13
14
elK [
ADS [
ADO-IS [
ODIN [
~[~,'---~----------+_------rl~
es[
TL/EE/B701-16
FIGURE 4-5. Read from DMAC Registers
11
13
12
14
I 11
OR
n
ODIN [
HBE[~~--~----------+_+_--+J
es[
TL/EE/6701-15
FIGURE 4-6. Write to DMAC Registers
4·70
z
en
(,)
...,...,
4.0 Device Specifications (Continued)
o
(,)
....o
I
TL/EE/8701-18
FIGURE 4-7. Indirect Write Cycle
ROY [
(HIGH)
IOWR [
(HIGH)
I
IIORDlo
lORD [
ACKn [
TLlEE/8701-19
FIGURE 4-8. Indirect Read Cycle
4·71
C)
,...
I
CO)
C)
,---------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
N
N
I
CO)
en
z
T1
T2
T3
T4
ClK[
ADO- 15
[~, _ _ _~
A 16- 23
[~r'-++_.......~--+--+-fJ'
ADS [
HBE
[-+','-_-+-_____+--+_+-''-
DDIN [
RDY [
lORD [
IOWR [
ACKn [
TUEE/8701-20
FIGURE 4·9. Direct 1/0 to Memory Transfer
T1
T2
T3
T4
ClK [
ADO-15 [
A16-23 [
ADS [
HBE [
DDIN [
(HIGH)
RDY [
I
lORD [
tlOWRdla
IOWR [
ACKn [
TL/EE/8701-21
FIGURE 4·10. Direct Memory to 110 Transfer
4·72
z
en
to)
4.0 Device Specifications (Continued)
I
n
N
N
Q
I n
ClK[~
n
n
Tl
to)
T2
•
......
Q
I
_MtHlDO
HOLD [
--I-
I- tHlDAh
tHLDAi,
"
HlDA [
- ---A 16-23 [
ADS [
HBE [
ODIN [
---_. ----- ----- -~
I
---- ---- ----- -
LOCAL DATA BUS
ADO-15
~
ADO-IS
>
"C
"C
CD
::s
D.
;C'
r--
CPU
A16-23
t H8E
_i
A16:.,ll
a:. HBE
LOCAL ADDRESS BUS
tf~:~~===:::l
CD
I
I I)
~,
I
::s
:~i:~~~~~~~~~~~~~~~~~n~X!IN~crR~::~li!11f~;i~~:;~~::::::~;l~~~~~~~~~~:::j~;;::j '--~L,r=
HOLD Hffii. RST/ ABT
~O
--...
::s
DBE
CO
en
c
RESET
ClOCK
CO
CO
CD
UI
0'
::s
UI
.".
ixl
iGRf
RST/;;a~m§W
ODiN
ADS
ClJ(
RDY
~C ~f~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~::::::::::::~~::~
~
n
NS32203
ru:oo
:
•
AOO-15
U
REWOTEDATABUS
ADO-'S
"CKO
REQ!
ACKl
"16-23
.-
RElIOTE ADDRESS BUS
.tHBE
....... BUFFERS
A16-23
4:iiBE
:>
TLlEE/8701-35
FIGURE A-1. NS322031nterconnections in Remote Configuration.
Note: This logic does not support direct (flyby) DMAC transfers.
Section 5
lBoard leve~ i?roducts
Section 5 Contents
VME532 High Performance 32-Bit CPU VME Board with Cache, Memory Management and
Floating Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB332-PLUS Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB32000 Development Board .......................................................
DB32016 Development Board.......................................................
5-2
5-3
5-6
5-1 0
5-15
<
m
==
~National
U1
Co)
~ Semiconductor
N
VME532
High Performance 32-Bit CPU VME Board with Cache,
Memory Management and Floating Point
Features
Product Overview
• NS32532 Central Processing Unit (CPU) with internal
cache and on-chip Memory Management Unit (MMU)
• NS32381 Floating Point Unit (FPU)
• Optional 32580 FPC+ Weitek WTL3164
• NS32202 Interrupt Control Unit (ICU)
• 20, 25 or 30 MHz operating frequency
• Cache-64 kbytes of direct-mapped zero wait-state
cache
• Conforms to all VME Revision C.1 specifications
• Supports multiprocessing system applications
• 4-16 Mbytes of on-board Dual Port DRAM with parity,
expandable to 256 Mbytes of cacheable address space
over the VME bus
• 64 kbytes of EPROM in one socket
• Two RS-232C serial ports (2681 DUART) with adjustable baud rate
• MON532 monitor firmware with power on diagnostics
The VME532 is National Semiconductor's VME based
board featuring the high-end Series 32000® family cluster.
The cluster consists of the NS32532 CPU with on-chip
Memory Management Unit, and the NS32381 Floating Point
Unit (FPU).
Available in 20, 25 and 30 MHz operating speeds, the
2-board set includes a 64 kbyte external cache with an average hit rate of over 90%. Expandable to % gigabyte of
memory, and with up to 16 Mbytes of DRAM on-board, the
VME532 provides cacheable memory address range of up
to 256 Mbytes.
The VME532 is a powerful CPU designed for systems demanding high performance in any environment, including
UNIX®, real time operating systems, e.g., VRTX32®, and
multiprocessing.
The VME532 may also be used to evaluate the NS32532
and NS32381 architecture, instruction set, timing, and performance. In addition, the board provides a native debug
and execution environment for programs developed on a
host computer and is compatible with National's GNXTM
software package.
II
TL/EE/93BO-l
FIGURE 1
5-3
~
C')
II)
r---------------------------------------------------------------------------------~
w
Hardware Description
>
CENTRAL PROCESSING UNIT
::is
Global Memory
The fourth level of the memory hierarchy is the global memory accessible to each processor through the system bus.
Each processor's local memory can serve as global memory to other processors in the system. In addition, memory
modules not local to any processor, can be used as global
memory by all microprocessors in the system. The cacheable address space is 256 Mbytes, of which 4 or 16 Mbytes
is local on-board memory.
The NS32532 microprocessor is National Semiconductor's
most powerful Central Processing Unit (CPU) that is compatible with other members of the Series 32000 family. The
NS32532 CPU contains an on-chip Memory Management
Unit (MMU) with a 64-entry translation buffer and is software
compatible with the NS32382 MMU.
Features of the NS32532 include 4 gigabytes of addressing
capability, a 512-byte instruction cache, a 1024-byte data
cache, 4-stage instruction pipeline, and dynamic bus sizing.
THE GATEWAY
In a typical CPU, more operations involve read cycles than
write cycles to local memory. The efficiency of the internal
cache of the NS32532 CPU together with the performance
of the external cache creates an effective hit rate in excess
of 90%, causing more write cycles than read cycles to
memory to occur. Since RAM access may cause a bottleneck in CPU performance, due to frequent write cycies, the
VME532 incorporates two custom gate array chips that
make up the Gateway circuitry. The Gateway is a 72-bit by 8
location deep write FIFO and read buffer allowing the CPU
to write to main memory without wait-states. Analysis indicates an 8-entry deep FI FO is sufficient to buffer, without
filling up, 99% of all memory write operations, improving the
performance of the VME532.
FLOATING POINT UNIT
The NS32381 Floating Point Unit (FPU) is a second generation CMOS, floating point slave processor, conforming to
IEEE standard 754-1985 for binary floating point arithmetic.
Functioning in a tightly coupled slave configuration with the
NS32532 CPU, the NS32381 FPU operates significantly
faster than the NS32081 FPU. Additionally, the NS32381
and has an expanded floating point instruction repertoire,
while preserving upward compatability. The NS323Bl FPU
operates on 2 floating point data types: single-precision
(32-bit) and double-precision (64-bit).
OPTIONAL FLOATING POINT ACCELERATOR
The VME532 is also available with a higher-performance
(15 MFLOPS peak) floating point alternative. This floating
point accelerator comprises the NS32580 Floating Point
Controller (FPC) and Weitek WTL3164 Floating Point Data
Path to create a compatible replacement for the standard
NS32381 FPU.
MULTIPROCESSING
Designed with multiprocessor applications in mind, the
VME532 will couple to a total of 16 processors in a separate-memory, shared-bus architecture. The VME532 provides the following multiprocessing features:
FOUR-LEVEL MEMORY HIERARCHY
CPU Cache
• CPU number switch. This thumbwheel switch on the
VME532 enables users to assign unique CPU identification numbers, ranging from 0 to 15 for each CPU in the
system.
The VME532 employs a 4-level memory hierarchy design.
The first level includes the 512-byte instruction cache and
the l-kbyte data cache, integrated within the NS32532 CPU.
This provides the CPU with an 80% internal cache hit rate
minimizing external rnemory accesses.
External Cache
• Local memory can be accessed by other VME masters,
including other CPUs. The memory of each CPU is
mapped into a unique space of the VME address.
• VME memory is shared among all bus masters, allowing
"mailbox" communication.
The second level memory hierarchy structure is composed
of a 64-kbyte direct-mapped, zero wait-state external cache,
allowing up to 256 Mbytes of cacheable address space.
With the addition of the external cache, the overall cache hit
rate increases to over 90%, allowing the NS32532 CPU to
nearly operate at full performance. In case a cache rniss
occurs, no time is wasted accessing local or external memory because memory accesses occur simultaneously with
each cache access and is aborted upon a cache hit.
The external cache is composed of very high speed
SRAMs. The data portion of the cache is arranged as an
array of 16k x 32 bits and is used to store 64 kbytes of data.
The tag portion of memory is a 4k x 16-bit array. Each entry
contains 12 bits of addressing information, 1 VALID bit, and
3 spare bits. The tag is integrated with high speed compare
logic to determine cache hit and miss.
• Bus Watcher. The bus watcher circuitry is responsible for
coherency between VME and cache-memory entries.
The bus watcher traces the activity on the VME bus.
Whenever cacheable memory is written by one of the
other VME masters, the bus watcher latches the address
of the memory, and a bus watch request signal is sent to
the cache memory controller. When an address match
occurs, the cache invalidates the entry. The bus watcher's FIFO of 8 entries prevents the loss of invalidation
requests during heavy VME bus traffic.
• Inter-processor interrupts. In addition to the normal VME
interrupt system, the VME532 allows other processors to
communicate with the VME532 using the inter-processor
interrupts. Sixteen address ranges are allocated for this
special purpose on the VME532.
Local Memory
INTERRUPTS
Included with the VME532 is National Semiconductor's
NS32202 Interrupt Control Unit (ICU). The 16 channel ICU
handles all on-board interrupts, all seven levels of VME interrupts, and inter-processor interrupts. The interrupts are
individually maskable, and the priority assignment may be
customized to suit the needs of the user.
Level three is the local dual-port parity-checking memory
consisting of 4 Mbytes, expandable to 16 Mbytes, of DRAM.
Accessing the third level through an independent local bus
reduces traffic along the common system bus. The local
dual-port memory allows access through the system bus, as
well as the local bus. The path through the system bus
serves to simplify the incorporation of peripheral devices by
transferring 1/0 directly to local memory.
5-4
r-----------------------------------------------------------------,<
SERIAL 110
ORDERING INFORMATION
A 2681 Dual-UART provides the user with two serial communication ports to enable communication with a terminal
and host processor, with RS-232C compatibility. The internal timer/counter of the DUART can be used as a watchdog
timer or real-time clock. The serial ports are provided with
Telco connectors, and DB-25 adapters for use as DTE or
DCE.
NSV-V532A-KF20
32381 FPU
VME532 Development Kit, 20 mHz,
NSV-V532A-KF25
32381 FPU
VME532 Development Kit, 25 mHz,
NSV-V532A-KF30
32381 FPU
VME532 Development Kit, 30 mHz,
NSV-V532A-KW20 VME532 Development Kit, 20 mHz,
32580/WTL3164 FPU
SOFTWARE OPTIONS
MON532 (monitor) with diagnostics is included with the
VME532. The VME532 supports National's GENIX® V.3°,
and optimizing compilers for Ada, C, Pascal, Modula-2, and
FORTRAN. The board also supports VRTX32 for real time
applications.
NSV-V532A-KW25 VME532 Development Kit, 25 mHz,
32580/WTL3164 FPU
NSV-V532A-KW30 VME532 Development Kit, 30 mHz,
32580/WTL3164 FPU
NSV-VXM532A-12M 12 Mbyte Local Memory Expansion
(20, 25, or 30 mHz)
'Derived from UNIX System V.a
VME SPECIFICATIONS
Master: A32:D32, UAT, RMW, IH7, ROR, RWD
Slave: A32:D32, UAT, BLT, RMW, ADO, BERR
Syscon: BR(0-3), (PRI, RRS, dyn.), BTC 1.6-12.8 dyn.),
IACK,SYSRST,SYSCLK
VME532 Block Diagram
.III
Local Interrupts
I
I
7 Level ViolE Interrupts
FPU
32381
J
PROM
DUART
~
1
CPU
32532
l I I
_t
""J
ICU
32201
"'-
"
11--.
Cache
"'
....
...
!li-
Interprocessor
Interrupt
Decoder
v
CPU
10 No.
Switch
DRAM
T
~
...
"'
Gateway
"'-~
...
M
~
E
r-.a.
"'
ViolE
Bus
Interlace
,....
.
r-
8
U
s
Bus
Watcher
~
I
ViolE
System
Controllerj
""I
,.
TL/EE/93BO-2
FIGURE 2
5-5
:!:
rn
en
Co)
....,
~.-----------------------------------------------------------------------,
....
CL
:;)
fa National Semiconductor
ADVANCED INFORMATION
~
C")
C")
DB332-PLUS Development Board
In
C
TL/C/9249-1
• Up to 256K bytes for JEDEC type ROM/
PROM/EPROM
• Two RS232 Serial Communication Ports
• Programmable Serial Port Baud Rates
• 16 interrupt sources that can be
arranged via Wire-Wrap Matrix
• Centronics parallel printer interface
• MON332B monitor firmware with poweron diagnostic
• Includes the Series 32000®
Microprocessor Family
-
•
•
NS32332 CPU
NS32382 MMU
NS32C201 TCU
NS32081 FPU
NS32202 ICU
MULTIBUS® I compatible
1M or 2M bytes of dual ported DRAM
Product Overview
The DB332-Plus Development Board is a high performance, 15 MHz, NS32332 based board that enables evaluation of National Semiconductor's
NS32332 computer cluster and Series 32000 family. It
has a Multibus I interface, with either 1 or 2 MBytes of
high-speed, dual-port dynamic RAM, serial and parallel 1/0, interrupt controller, ROM socket, and
NS32332 computer cluster. The cluster consists of
the NS32332 Central Processing Unit, NS32382
Memory Management Unit, NS32081 Floating Point
Unit, NS32C201 Timing Control Unit, and NS32202
Interrupt Control Unit.
The instruction sets, cycle timing, bus interfacing, and
internal architecture of the Series 32000 family can be
examined using the DB332-Plus board. In addition, the
DB332-Plus can provide a native debug and execution
environment for programs developed on a host computer. The DB332-Plus is compatible with National's
GNX software package.
The DB332-Plus board is shipped with the MON332B
monitor and diagnostic firmware, serial and parallel
printer cables, and user documentation. The board
can be used in a Multibus I system, or as stand-alone
board. In the stand-alone mode, the board needs a
power supply, and terminal.
CENTRAL PROCESSING UNIT
The DB332-Plus incorporates a 15 MHz NS32332,
which is a 32-bit, virtual memory microprocessor with
5-6
r--------------------------------------------------------------------------,
Interrupts
a 4 GByte addressing capability. The NS32332 is fully
object code compatible with other Series 32000 microprocessors, and has the added features of 32-bit
addressing, higher instruction execution throughput,
and expanded bus handling capabilities. The bus features include bus error and retry support, dynamic bus
sizing, burst mode memory accessing, and enhanced
slave processor communication protocol.
The NS32332, being a member of the Series 32000
family, has powerful addressing modes, symmetric instruction set, modular software support, and linear addressing. The NS32332 is designed to work with both
16- and 32-bit slave processors of the Series 32000
family. They allow the processor to implement demand-paged virtual memory system through the use
of the memory management unit (MMU), and support
for high-speed floating point processing through the
floating point unit (FPU).
The DB332-PLUS development board incorporates
the NS32202 Interrupt Control Unit (ICU). The ICU
manages up to 16 maskable interrupt sources, resolves interrupt priorities, and supplies a single-byte
vector to the CPU. In addition, two 16-bit counters are
provided by the NS32202.
Memory
The DB332-PLUS comes with either 1M or 2M bytes
of 85 ns static column, dual ported DRAM. At 15 MHz
it can be accessed with 1 wait state. Memory supports
Burst access via either the CPU or external MULTIBUS masters. Due to the MULTlBUS I form factor, the
memory module and its controller is mounted on a
separate P.C. board which is plugged into the DB332PLUS.
Up to 256K bytes are available for JEDEC type ROMI
EPROMs via a 28 pin socket. This socket is normally
occupied by the MON332B firmware PROM.
SLAVE PROCESSORS
The DB332-Plus contains both the NS32382 MMU,
and the NS32081 FPU. In addition, the board incorporates a connector that allows the next generation
FPU, the NS32381, to be added. The NS32381 FPU
will need to be mounted on a module that will be
plugged into the DB332-Plus's expansion connector.
Multibus Interface
The DB332-PLUS incorporates a MULTIBUS I interface, allowing the user to configure larger systems.
Most often, the DB332-PLUS would be used in conjunction with MULTIBUS compatible expansion RAM,
disk controller, or serial controller boards. However
there is no restriction, beyond MULTIBUS compliance.
The DB332-PLUS's MULTIBUS compliance levels
are:
Master D16 M24 VO E1; indicating 16-bit data path,
24-bit memory address path, 16-bit 1/0 address path, and level or edge triggered nonbus vectored interrupts.
Slave
D16 M24; indicating 16-bit data path and
24-bit memory address path.
NS32382:
The NS32382 MMU provides hardware support for demand paged virtual memory management for the
NS32332 CPU. The MMU has a 32-bit data path and
translates 32-bit virtual addresses from the CPU into
32-bit physical addresses. High-speed address translation is performed on-chip through a Translation Buffer which holds the address mappings for 32 pages. If
the virtual address generated by the CPU has no corresponding entry in the translation buffer, the MMU
will perform address translation using a two level page
table algorithm. The memory page size of the
NS32332 is 4 Kbytes.
Parallel 1/0
A 40-pin connector (J3) and the necessary cable are
provided to interface with a Centronix compatible printer.
NS32081:
The NS32081 FPU provides high-speed floating-point
processing support, and is compatible with the IEEE
754 standard for binary floating-point arithmetic. The
NS32081 operates on two floating-point data typessingle preciSion (32-bits) and double precision (64bits). In addition, the FPU performs conversion between integer and floating-point data types. The
NS32081 has eight, 32-bit floating point registers, a
floating-point status register, and operates as a slave
processor for transparent expansion of the NS32332
CPU's basic instruction set.
Serial 1/0
The two serial interfaces (J1 and J2) are designed to
provide a wide variety of asynchronous, RS232C-compatible communications. Jumper options are provided
for altering the configuration of each interface. Appropriate cables are included with the package.
Switches
The DB332-PLUS board has a non-maskable interrupt
push-button (NMI) designated S1, a RESET pushswitch designated S2 and a four- position DIP switch.
5-7
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These three switches are located on the front edge of
the CPU board. The status of the DIP switch can be
read by the DB332-PLUS software.
The DB332-PLUS can operate stand-alone, with no
assistance from the host computer system. Optionally,
the board can be operated in conjunction with a host,
taking advantage of more powerful software development tools and 1/0 capabilities. Figure 1-2 represents
the most common variations in user modes.
Consult the Development Board Monitor Reference
Manual for a complete description of capabilities.
Two different configurations are available in host assisted mode, transparent and stand-aside. Both are
illustrated in Figure 1, and explained below.
In transparent configuration, the user's communication with the host is conducted through the
DB332-PLUS, which is transparent to the user. One
advantage is that a single RS232 port on the host
computer will support both the user's terminal and the
DB332-PLUS.
In stand-aside configuration, the user communicates
directly with the host while the DB332-PLUS "stands
aside". This mode is useful when the DB332-PLUS is
connected to single-user hosts, notably those where
the terminal and keyboard are integral to the host. Optionally, stand-aside operation is possible with multiuser hosts where two RS232 ports are available.
Stand-Alone Mode
Specifications
Indicators
The DB332-PLUS board has four LEDs designated
DS1 through DS4. Led DS1 is controlled by the physical address valid signal (NPAV) from the CPU cluster
and indicates that the CPU cluster is active. DS2
through DS4 are software controlled and may be used
as status or diagnostic indicators.
User Modes
From Figure 1-2, it is clear that the stand-alone user
mode is the most simplistic and requires the least additional equipment. In this case, only an RS232 compatible terminal and power supplies for the DB332PLUS are required to achieve effective operation. Using the monitor commands given in the Development
Board Reference Manual, limited amounts of debugging can be accomplished.
Environment
The DB332-PLUS is designed for operation in an office or laboratory environment. Sufficient air flow
should be present to ensure all components are within
their specified temperature ranges.
Environment
Host Assisted Mode
The DB332-PLUS can be connected to another computer system or host. In this case, the user first develops Series 32000 software on the host system, then
uses the RS232 communication link to download the
software to the DB332-PLUS, which executes and debugs the software in a native environment. Several
development software packages are available for use
in generating Series 32000 user programs. Among
them is National's GENIX Native and Cross Support
Tools (GNX) which includes assemblers, linkers, and
debuggers.
The DB332-PLUS is supplied with MON332B for interfacing between the host and terminal in this mode.
The monitor software will provide:
• Terminal Handler (for use in transparent mode)
• Run-Time Environment (to permit execution of
downloaded programs)
Description
Temperature
Operative 5·C to 50·C
Inoperative -40·C to 60·C
Humidity
10% to 90% relative, non-condensing
Altitude
Operative 15,000 feet
Inoperative 25,000 feet
Power Requirements
The DB332-PLUS requires three regulated DC voltages for operation.
1. + 5V DC, ± 5%, 10 Amps (when utilizing 2 Mbytes
of memory)
2. +12V DC, ±10%, 100 mA
3. -12V DC, ±10%, 100 mA
Ordering Information
• Debugger Execute Module (to permit operation
with host's debugger)
5-8
Part Number
Description
NSV-32332B 1M-15
15 MHz, 1MB memory version.
NSV-32332B2M-15
15 MHz, 2MB memory version.
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1. STAND-ALONE MODE
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2. HOST-ASSISTED MODES
a) STAND-ASIDE, SINGLE-USER HOST
(eg. SPX II)
b) STAND-ASIDE MULTIUSER HOST
c) TRANSPARENT, LOCAL HOST
d) TRANSPARENT, REMOTE HOST
'REQUIRES RECONFIGURATION
TLlC/9249-2
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DB32000 Development Board
TL/EE/8523-1
•
•
•
•
Two RS-232 Serial Communication Ports
24 Programmable Parallel 1/0 Lines
Two BLXTM Connectors
Wire-wrap area for user expansion
- Bus interface
- Dual port RAM
- ROM expansion
-1/0 expansion
- RAM expansion
• TDSTM firmware provides edit, assembly,
and debug capabilities
•
Series 32000® Microprocessor Family
- NS32032 Central Processing Unit
(CPU) (can be replaced by NS32016
CPU, or NS32008 CPU, for evaluation)
- NS32082 Memory Management Unit
(MMU)
- NS32081 Floating Point Unit (FPU)
- NS32202 Interrupt Controller Unit
(ICU)
- NS32201 Timing Control Unit (TCU)
• 256K bytes DRAM expandable to 1 Mbyte
• Up to 256K bytes of EPROM in two
banks
Product Overview
National Semiconductor's D832000 Development
Board is a complete microcomputer system. It is specifically designed to assist the user in evaluating and
developing hardware and software for the NS32032
CPU, related slave processors (NS32081 FPU and
NS32082 MMU) and support devices. With the
D832000, the user may evaluate other CPUs such as
the NS32016 and NS32008. The D832000 enables
5-10
~----------------------------------------------------------------'C
m
Product Overview (Continued)
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the user to examine the architecture, instruction set,
cycle timing, and the bus interfaces for the Series
32000® family of microprocessors. Small programs
can be written, debugged, assembled, and executed
with EPROM-based T08 (Tiny Oevelopment 8ystem)
software.
Optionally, the 0832000 can provide a native debug
and execution environment for programs developed
on a larger host computer system. In this case, the
board complements capabilities provided by National's Pascal, Fortran and C cross-software packages.
The 0832000 includes the N832032 CPU, NS32082
MMU, N832081 FPU, NS32202 ICU, support circuitry,
dynamic RAM, extensive ROMIEPROM capacity, and
serial and parallel 110. 110 capability can also be expanded via 8LX interfaces.
Serial 1/0
Two serial 110 ports are provided via 2651 Universal
Synchronousl Asynchronous Receiver/Transmitters.
These ports permit the 0832000 to communicate with
R8232C compatible terminals or other computers.
The baud rate for each port is software programmable.
o
o
o
BLX 1/0 Expansion
Two connectors are provided for attachment of 8- or
16-bit 8LX expansion modules. 8LX modules may be
used to expand the 0832000's 110 capability; e.g.,
additional serial on parallel ports.
Switches
Two button switches (S3 and 84), and one 10-position
DIP switch (81) are provided. 83, labeled NMI 0, will
introduce a non-maskable interrupt to the 0832000's
CPU when pressed. S4, labeled RESET, will reset the
board when pressed. Switch 81 is a software readable
dip switch that may be used to indicate defined options, e.g., baud rate, MMU present, etc. Each switch
position function is defined by the on-board PROMbased software.
Central and Slave Processors
The 0832000 is equipped with an N832032 CPU, featuring 32-bit internal structure and 32-bit data bus. Optionally, an N832016 or NS32008 CPU can be installed, with 32-bit internal structure and 16-bit or 8-bit
data path. Each CPU provides a very powerful instruction set designed for high level language support.
The 0832000 also includes the N832082 MMU and
the NS32081 FPU. The N832082 Memory Management Unit provides hardware support for demandpaged virtual memory management. The NS32081
provides high-speed floating-point instruction execution.
Indicators
Four LEO indicators (02-05) are mounted near the
lower left corner of the 0832000. 02-04 are controlled by the contents of a program-addressed register. They are used by the T08 power-on confidence
test program to indicate test status. They may also be
used to indicate any other information the user desires. 05 is driven directly by a 15-millisecond 1-shot
timer. 05 will be extinguished whenever there is no
CPU memory or 110 access within this time. 05 is illuminated when the CPU is executing instructions. This
LEO indicates whether or not the CPU is active.
Interrupts
As part of factory configuration, the 0832000 comes
with the NS32202 ICU installed. The NS32202 Interrupt Control Unit manages up to 16 maskable interrupt
sources, resolves interrupt priorities, and supplies a
single-byte vector to the CPU. In addition, the ICU provides two, 16-bit counters.
Wire-Wrap Expansion Area
The wire-wrap expansion area provides the user with
space that is drilled to accept integrated circuits. Signal pad terminators (stubs) are located at different locations on the board enabling the user to construct
the following functions in the wire-wrap area:
- External 8us Interface
- Dual Port Memory Interface
- ROM Expansion
- 110 Expansion
- DRAM Capacity Expansion Using the On-board
DRAM Controller
Memory
Expandable to 1 Mbyte, 256K bytes of on-board dynamic RAM are provided. The wire-wrap area may be
used in conjunction with the 0832000 circuitry to develop dual port capability.
Up to 256K bytes of ROMIEPROM space is provided
in eight 28-pin sockets. The sockets are divided into
two banks, each bank permitting installation of 24- or
28-pin devices. All factory configurations include TOS
firmware installed in the lower bank, with the upper
bank vacant.
Parallel 1/0
Twenty-four parallel 110 lines are provided via an
8255A Programmable Peripheral Interface. These
may be divided into two 8-bit ports and two 4-bit ports.
5-11
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Tiny Development Systems (TDS)
Functional Description
Stand-Alone Mode (Factory Configuration)
The stand-alone user mode (see Figure 1) requires
only an RS232C-compatible terminal and power supplies for the 0832000.
TOS (Tiny Oevelopment System) software is supplied
in on-board PROMs to support this user mode. TOS is
used to edit, assemble, and execute small Assembly
language programs. In addition, TOS can control the
0832000's on-board I/O to provide cassette and printer interfaces, making the 0832000 a light duty development vehicle.
The TOS firmware allows the user to create programs
by entering source via the editor. This source is then
assembled to produce executable code suitable for
debugging. These functions have the following features:
Assembler:
- Subset of existing Series 32000 assembler
- Supports FPU by providing long and short format
real number data initialization
- Generates listings to either a printer at the parallel
port, or any RS232 device connected via serial
port
- Symbolic definition of static base or PC segment
Host-Assisted Modes
The 0832000 can be connected to another computer
system or host (refer to Figure 1). In this case, the
user first develops Series 32000 software on the host
system, then uses the RS232 communication link to
download the software to the 0832000, which executes and debugs the software in a native environment.
Several development software packages are available
for use in generating Series 32000 user programs.
Among them are:
- Pascal, Fortran and C, operating under VAXIVMS
- Pascal, Fortran and C, operating under VAX/
UNIX®
In each case, the 0832000's factory-supplied, onboard TOS software must be replaced. A suitable
PROM-based monitor software package is supplied
with the host development software.
The basic modes of host-assisted 0832000 operation
are "stand-aside" and "transparent". The terms
"stand-aside" and "transparent" may be visualized by
observing the communication configuration for each
mode. Refer to Figure 1.
The monitor software will provide:
- Terminal Handler (for use in transparent mode)
- Run-Time Environment (to permit execution of
downloaded programs)
- Oebugger Execute Module (to permit operation
with the host's debugger)
Consult the Oevelopment 80ard Monitor Reference
Manual for a complete description of capabilities.
In transparent mode, the user's communication with
the host is conducted through the 0832000, which is
transparent to the user. One advantage is that a single
RS232 port on the host computer will support both the
user's terminal and the 0832000.
In stand-aside mode, the user communicates directly
with the host while the 0832000 "stands aside". This
mode is useful when the 0832000 is connected to
single-user hosts, notably those where the terminal
and keyboard are integral to the host. Optionally,
stand-aside operation is possible with multi-user hosts
where two RS232 ports are available.
Debugger:
- Numerical arguments to commands can be in four
bases: decimal, hex, long real and short real
- Program flow visually traced by displaying source
line at all breakpoints or step stops
- Memory/register print or change commands
- Step-through program commands: step "n" instructions, step while variable in range, step until
variable reached
Editor:
- Commands to insert, replace, delete, type lines
- Automatic line number maintenance
- Save and retrieve source from audio cassette recorder
- Upload/download to/from any RS232-equipped
PC
- Oebug data displayed by type command after assembly
User Program Run Time Support:
- Accessed via a supervisor call instruction
- Routines to do terminal I/O
- Printer driver access to parallel port
- Routine to convert binary value to ASCII string
- Routine to convert ASCII string to binary value
- Conversion in four bases: decimal, hex, long real
and short real
As shipped with the 0832000, TOS provides on-board
hardware confidence test routines. These are invoked
by power-on or manual reset.
User Modes
The 0832000 can operate stand-alone, with no assistance from a host computer system. Optionally, the
board can be operated in conjunction with a host, taking advantage of more powerful software development tools and I/O capabilities.
5-12
c
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User Modes (Continued)
(0)
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STANDALONE MODE
o
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POWER
SUPPLY
I
J6
OB32000
J2
L..J
Jl
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OTE
HOST-ASSISTED MODES
POWER
SUPPLY
TERMINAL
I
J6
OB32000
STANOASIOE
J2
~
Jl
""OTE"
TERMINAL
OCE
OTE
HOST
OCE
POWER
SUPPLY
I
J6
OB32000
TRANSPARENT, LOCAL
J2
OTE
HOST
I
Jl
10CE
OCE
OTE
POWER
SUPPLY
TERMINAL
I
J6
OB32000
TRANSPARENT, REMOTE
J2
OTE
HOST
I--
MODEM
~
MODEM
I
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10CE
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OTE
'Requires Reconfiguration
FIGURE 1.0832000 Configurations
5·13
TERMINAL
TUEE/8523-2
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Specifications
Ordering Information:
Environment
NSV-32032S6T-10 DB32000 Development Board
All models are shipped with:
Two RS232 cable sets
Model DB32000-11 0 Includes NS32032-10 CPU
NS32201-10 TCU
NS32202-10 ICU
NS320B1-10 FPU
NS32082-10 MMU
NSP-TDS-M Series 32000 TDS: Tiny Development
System User's
Manual
NSP-DB32000-M Series 32000 DB32000 Development Board User's Manual
NSP-INST-REF-M Series 32000 Instruction
Set Reference Manual
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The DB32000 is designed for operation in an office or
laboratory environment. Avoid confining the DB32000
in a closed space, unless sufficient air flow is provided
to ensure all components are operated within their
specified temperature range.
Temperature:
Operating
O°Cto + 55°C
-40°C to + 75°C
Nonoperating
Humidity:
5% to 95% relative,
non condensing
Altitude:
Operating
up to 15,000 ft.
Nonoperating
up to 25,000 ft.
Power Requirements
The DB32000 requires three regulated DC voltages
for operation:
+ 12 volts DC, ± 10%, 40 mA typical (50 mA max)
-12 volts DC, ± 10%, 40 mA typical (50 mA max)
+5 volts DC, ±5%, 5A typical (10A max)
5-14
,-----------------------------------------------------------------------, c
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08320116 Development Board
TUR17083-1
•
Series 32000® Microprocessor Family
• NS32016 CPU (can be replaced by
NS32008 CPU, for evaluation)
NS32082 MMU
NS32081 FPU
NS322021CU
NS32201 TCU
MULTIBUS® mUlti-master bus interface
128 Kbytes dual ported RAM
Up to 96 Kbytes PROM capacity
Two RS232 serial communication ports
24-programmable parallel 110 lines
Three 16-bit programmable timerI
counters
0 One BLXTM expansion module connector
for additional 110 capability
0 TDSTM firmware provides edit, assembly,
and debug capabilities
0
0
0
0
••
•
•
••
Product Overview
The DB32016 Development Board is a complete microcomputer using the National Semiconductor Series
32000 family of advanced microprocessors. It is specifically designed to assist evaluation and development of Series 32000 applications in a variety of environments.
By itself, the DB32016 can be used to examine the
Series 32000 architecture and instruction set. Small
programs can be written, debugged, and executed
with EPROM-based TDS (Tiny Development System)
software.
Optionally, the DB32016 can provide a native debug
and execution environment for programs developed
on a larger host computer. In this case, the board
complements capabilities provided by National's C
and Pascal cross software packages.
Flexibility is further enhanced by the board's MULTIBUS interface. This permits expansion of the
DB32016 microcomputer system to include functions
provided by other MULTIBUS compatible boards; e.g.
diskltape controllers, bulk RAM, etc.
All models of the DB32016 include, as a minimum, the
NS32016 CPU, support circuitry, serial and parallel
lID, dynamic RAM, and extensive ROMIEPROM capacity. Optionally, the board can be populated with
NS32082 Memory Management Unit, NS32081 Floating-Point Unit, and NS32202 Interrupt Control Unit. In
all cases, lID capability can be expanded via BLX and
MULTIBUS interfaces.
5-15
....
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Hardware Function Description
(Refer to Figure 1-1)
C
TLfR17083-2
FIGURE 1-1. OB32016 Topography
Central and Slave Processors
Memory
The OB32016 is equipped with a NS32016 CPU, featuring 32-bit internal structure and 16-bit data bus. Optionally, a NS32008 CPU can be installed, with 32-bit
internal structure and 8-bit data path. Each CPU provides a very powerful instruction set designed for high
level-language support.
Included with each OB32016 is the NS32082 MMU
and the NS32081 FPU slave processors. The
NS32082 Memory Management Unit provides hardware support for demand-paged virtual memory management. The NS32081 provides high-speed floatingpoint instruction execution.
If the OB32016 is purchased without slave processors, they may be installed by the customer, as required.
128 Kbytes of on-board, dual-ported dynamic RAM
are provided. The MULTIBUS starting address of
RAM is mappable in 32K byte increments, across the
entire 16M byte address space.
Up to 96 Kbytes of ROMIEPROM space is provided in
four 28-pin sockets. The sockets are divided into two
banks, each bank permitting installation of 24 or 28pin devices. All factory configurations include TOS
firmware installed in the lower bank, with the upper
bank vacant.
MULTIBUS Interface
The OB32016 incorporates a MULTIBUS interface, allowing the user to configure larger systems. Most often, the OB32016 would be used in conjunction with
MULTIBUS compatible expansion RAM, disk controller, or serial controller boards. However there is no
restriction, beyond MULTIBUS compliance.
The OB32016's MULTIBUS compliance levels are:
Master
016 M24 116 VOEL; indicating 8/16-bit
data path, 24-bit memory address path, 8or 16-bit 1/0 address path, and level or
edge triggered non-bus vectored interrupts (if NS32202 is installed).
Slave
016 M24; indicating 8/16-bit data path,
and 24-bit memory address path.
Interrupts
Also included with the OB32016 is the NS32202 ICU.
The NS32202 Interrupt Control Unit manages up to 16
maskable interrupt sources, resolves interrupt priorities, and supplies a single-byte vector to the CPU. In
addition, the ICU provides two, 16-bit counters, one of
which can provide programmable baud rate capability
for the OB32016's serial 1/0 ports.
If the OB32016 is purchased without the ICU, it may
be installed by the customer, as required.
5-16
Parallel I/O
completed by the CPU within this period. This is useful
to indicate a MULTIBUS timeout.
24 parallel I/O lines are provided via an 8255A Programmable Peripheral Interface. These may be divided into two 8-bit ports and two 4-bit ports.
Tiny Development Systems (TDS)
Functional Description
Serial I/O
The TOS firmware allows the user to create programs
by entering source via the editor. This source is then
assembled to produce executable code suitable for
debugging. These functions have the following features:
Two serial I/O ports are provided via 8251A Universal
Synchronous/ Asynchronous Receiver/Transmitters.
These ports permit the OB32016 to communicate with
RS232 compatible terminals or other computers.
Port baud rates may be derived from a variety of
sources:
• a fixed, 9600 baud operation of both ports, if the
NS32202 ICU is not installed.
• single programmable baud rate for both ports, if
the NS32202 ICU is installed.
• Individually programmable baud rates for each
port, via the OB32016's 8253-5 PIT.
Assembler:
-
-
Timer/Counters
As mentioned above, the NS32202 ICU provides two
16-bit timer/counters, when installed. In addition,
three 16-bit counters are provided by the OB32016's
8253-5 Programmable Interval Timer. Each counter
output is available for connection as an interrupt
source for the ICU, or baud rate generation for the
serial ports.
Subset of Series 32000 assembler
Supports FPU by providing long and short format real number data initialization
Generates listings to either a printer at the parallel port, or any RS232 device connected via
serial port
Symbolic definition of static base or PC segment
Debugger:
-
-
BLX I/O Expansion
A connector is provided for attachment of 8- or 16-bit
BLX expansion modules. BLX modules may be used
to expand the OB32016's I/O capability; e.g. additional serial or parallel ports.
Numerical arguments to commands can be in
four bases: decimal, hex, long real and short
real
Program flow visually traced by displaying
source line at all breakpoints or step stops
Memory/register print or change commands
Step-thru program commands: step un" instructions, step while variable in range, step until variable reached
Editor:
-
Switches
Two push button switches (S1 and S2), and one eightposition OIP switch (S3) are provided.
S1, labeled NMI, will introduce a non-maskable interrupt to the 0832016's CPU when pressed. S2, labeled
INIT, will reset the board when pressed. Both switches
are located on the front edge of the board assembly.
OIP switch S3 is used to set the Baud rate of the serial
ports and other board configurations.
-
Command to insert, replace, delete, type lines
Automatic line number maintenance
Save and retrieve source from audio cassette
recorder
Upload/download
to/from
any
RS232
equipped PC
Oebug data displayed by type command after
assembly
User Program Run Time Support:
Indicators
-
Accessed via a supervisor call instruction
Routines to do terminal I/O
Printer driver access to parallel port
Routine to convert binary value to ASCII string
Routine to convert ASCII string to binary value
Conversion in four bases: decimal, hex, long
real and short real
As shipped with the 0832016, TOS provides on-board
hardware confidence test routines. These are invoked
following power on.
Four LEO indicators (OS1-0S4) are mounted near the
front edge of the board assembly.
OS1-3 are controlled by the contents of a program
addressed register. They are used by the TOS poweron confidence test program to indicate test status.
They may also be used to indicate any other information the user desires.
OS4 is driven directly by a one-shot timer, whose period is approximately 15 milliseconds. OS4 will be illuminated whenever there is no memory or I/O access
5-17
User Modes
The 0832016 can operate stand-alone, with no assistance from a host computer system. Optionally, the
board can be operated in conjunction with a host,
taking advantage of more powerful software development tools and lID capabilities.
Figure 1-2 represents the most common variations in
user modes.
1. Standalone Mode
2. Host-assisted Modes
a) Standaside, single-user host
b) Standaside, multiuser host
P2
c) Transparent, Local host
d) Transparent, Remote host
TLlR/7083-3
·requires reconfiguration
FIGURE 1-2.0832016 User Modes
5-18
c
Stand-Along Mode (Factory Configuration)
is that a single RS232 port on the host computer will
support both the user's terminal, and the 0832016.
In standaside mode, the user communicates directly
with the host; the 0832016 "stands aside". This
mode is useful when the 0832016 is connected to
single-user hosts. Optionally, standaside operation is
possible with multi-user hosts, where two RS232 ports
are available.
From Figure 1-2 it is clear that the stand-alone user
mode is the most simplistic; requiring the least additional equipment. In this case, only an RS232C compatible terminal and power supplies for the 0832016
are required to achieve effective operation.
TOS (Tiny Oevelopment System) software is supplied
in on-board PROM to support this user mode. TOS is
used to edit, assemble, and execute small assembly
language programs. In addition, TOS can control the
0832016's on-board I/O to provide cassette and printer interfaces; making the 0832016 a light duty development vehicle.
m
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......
Q)
Specifications
Environment
The 0832016 is designed for operation in an office or
laboratory environment. Avoid confining the 0832016
in a closed space, unless sufficient air flow is provided
to ensure all components are operated within their
specified temperature range.
o Temperature
Operating O°C to 55°C
Non Operating -40°C to 75°C
o Humidity
5% to 95% relative, non-condensing
o Altitude
Operating 15,000 ft.
Non Operating 25,000 ft.
Host Assisted Modes
Referring to Figure 1-2, the 0832016 can be connected to another computer system, or host. In this case,
the user will first develop Series 32000 software on
the host system, then utilize RS232 communication to
download the software to the 0832016. The 0832016
functions as a means of executing and debugging the
software in a native environment.
Several development software packages are available
for use in generating Series 32000 user programs.
Among them are:
• Pascal and C for VAXIVMS environments
o Pascal and C for VAX/UNIX environments
Host assisted modes require the TOS PROMs to be
replaced by a PROM-based monitor program, compatible to the host development software. Monitor software is bundled with National's Series 32000 software
packages. The monitor provides:
• a terminal handler, to control RS232 communications
• run-time environment, to permit execution of
downloaded programs
• debugger execute module, to facilitate operation with the host's debugger software
The basic host assisted modes are:
• transparent
Power Requirements
The 0832016 requires three, regulated OC voltages
for operation:
+ 12 VOC, ±10%, 50 ma max
-12 VOC, ±10%, 50 ma max
+5 VOC, ±5%, 7.5A max
All power connections are made via P1. These connections are normally provided by a MULTI8US compatible backplane. Optionally the user may elect to
provide power, using one of the recommended connectors listed for P1.
Connectors
Local bus
expansion (P2)-
• standaside
The terms, transparent and standaside, may be visualized by observing the communication configuration in
each mode. (Refer to Figure 1-2)
In transparent mode, the user's communication with
the host is conducted through the 0832016; the
0832016 is transparent to the user. An advantage
Parallel I/O (J1)Serial I/O (J2)8us interface (P1)and Power
5-19
COC VP801 830AOOA2
AMP PES-14559
TI H311130
3M 3415-001
AMP 2-86792-3
3M 3462-0001 flat
AMP 1-583715-1 round
SAE FUPH7212-86MTNE
Viking 2KH43/9AMK12
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Ordering Information
Model 0832016-110 (Order #NSV-32016P8T-10)
Includes NS32016-10 CPU, NS32082-10 MMU,
NS32081-10 FPU, NS32202-10 ICU, and
NS32201-10 TCU for 10 MHz operation.
All Models are shipped with:
• Two RS232 cable sets
• TDS: Tiny Development System User's Manual
(Publication No. 420306440-001)
• 0832016 Development 80ard User's Manual
(Publication No. 420310111-001)
Related Reference Material
Series 32000 Instruction Set Reference Manual (Customer Order No. NSP-INST-REF-M)
5-20
Section 6
Development Tools
Section 6 Contents
SYS32/30 PC-Add-In Development Package ..........................................
SYS32/20 PC Add-In Development Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISE32 NS32032 In-System Emulator..................................................
SPLICE Development Tool ..........................................................
6-2
6-3
6-9
6-12
6-21
~
National Semiconductor
SYS32/30 PC-Add-In
Development Package
TLfEEf9420-1
•
•
•
•
•
•
II Support for other Series 32000®
15 MHz NS32332INS32382 Add-In board
for an IBM® PC/AT® or compatible
system
2-3 MIP system performance
No wait-state, on-board memory in 4-, 8or 16-Mbyte configurations
Operating system derived from AT&T's
UNIX® System V Release 3
Multi-user support
GENIXTM Native and Cross-Support
(GNXTM) language tools. Includesassembler, linker, libraries, debuggers
development products:
-SPLICE
- National's Series 32000 Development
Board family
- Compilers: C, FORTRAN77, Pascal,
Ada®
• Easy to use DOS/UNIX interface
Product Overview
The SYS32TM/30 is a complete, high-performance
development package that converts an IBM PCI AT or
compatible computer into a powerful multi-user system for developing applications that use National
Semiconductor Series 32000 microprocessor family
components. The SYS32/30 add-in processor board
containing the Series 32000 chip cluster with the
NS32332 microprocessor allows programs to run on a
personal computer at speeds greater than those of a
VAXTM 780. The chip cluster on the processor board
includes the NS32332 Central Processing Unit,
NS32382 Memory Management Unit, NS32C201 Timing Control Unit and the NS32081 Floating-Point Unit.
Along with the processor board, the SYS32/30 package contains the OpUS5™ operating system. This operating system is a port of AT&T's UNIX System V
Release 3, and is derived from GENIX V.3, National
6-3
•
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.---------------------------------------------------------------------------------~
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Product Overview (Continued)
Semiconductor's port of UNIX System V Release 3.
Specially developed software is included to efficiently
integrate the NS32332 processor board and the host
PCI AT processor, allowing them to function as a complete UNIX computer system. National's Series 32000
GENIX Native and Cross-Support (GNX) language
tools are included in the SYS32/30 package to provide stable and effective tools for software development. Optional compilers are available for
FORTRAN77, C, Pascal, and Ada.
The SYS32/30 processor board plugs into the PCI AT
bus, uses the standard control and data signals, and
appears to the PCI AT as 16 bytes in the PCI AT Input/Output (lID) space. Communication between the
PCI AT and the board is accomplished via this address space. This architecture allows the board to interface to the PCI AT in the same manner as any other
AT peripheral. The PCIAT processes lID commands
while the SYS32/30 processor board continues with
regular operation. lID is requested via interrupt to the
PCI AT, which then performs the data transfer using
Direct Memory Access (DMA). (See Figure 1).
The processor board requires two slots in the PCI AT
motherboard and plugs into a single long 16-bit bus
slot. The space of the second slot is needed to accommodate ihe piggybacked memory board attached
to the processor board. No additional connections are
required.
Functional Description
15 MHz ADD-IN PROCESSOR BOARD FOR AN IBM PCI AT
OR COMPATIBLE SYSTEM
The SYS32/30 development package contains a
processor board designed around the Series 32000
chip set. This chip set includes the NS32332 Central
Processing Unit, NS32382 Memory Management Unit,
NS32C201 Timing Control Unit, and the NS32081
Floating-Point Unit.
This processor board forms the high-performance
center of the computer system with the host PCI AT
processor. Peripherals are under the control of the
PCI AT's microprocessor and are located either on the
PCI AT motherboard or on other boards in the AT
chassis. The PCI AT handles all direct access to devices and serves as an integral dedicated lID processor.
2-3 MIPS SYSTEM PERFORMANCE
The NS32332 CPU and associated devices operating
at 15 MHz provide computing power greater than that
of a VAX 780. Sustained performance for the
NS32332 device cluster is 2-3 VAX MIPS (Million Instructions Per Second). An example of relative performance using the widely recognized Dhrystone
benchmark is shown in Figure 2.
DOS
UTILITIES
SYS32/30
A
"OW
11_
"
OPMON PROGRAM
,~.
SYS32/30 DRIVERS
DATA v
AND
CONTROL
'I
1~7
PC
HARDWARE
UNIX ENVIRONMENT
11
Ift.-..J\
f'r;I
PC
PERIPHERALS
DOS ENVIRONMENT
TL/EE/9420-2
FIGURE 1
6-4
r---------------------------------------------------------~0
Cii
Functional Description (Continued)
(,)
able time in regenerating complex software systems
after changes are made. The uucp software allows
users on different UNIX systems to communicate using electronic mail and to transfer files over dial-up or
serial communications links. Menu-driven system administration is available for system setup, adding users, controlling communication lines, installing software packages, changing passwords, and other administrative functions.
DHRYSTONE 1.1
SYS32/30
ADDITIONAL SUPPORT UTILITIES
Many of the popular utilities from the Berkeley 4.2
UNIX operating system, not contained in AT&T's UNIX
System V Release 3, are supplied as part of the package. These utilities are listed in Table I.
VAX 780
TABLE I. Bsd 4.2 Utilities
CShell
bsu
ctags
from
leave
scrpt
unexpand
TL/EE/9420-3
FIGURE 2. SYS32/30 Dhrystone Program
Compiled with GNXr2 C Compiler
VAX 780 Dhrystone Data Obtained from USENET
apply
chsh
expand
head
more
strings
whereis
banner
clear
factor
last
primes
test
which
The Tools for Documenters package, derived from the
AT&T Documenter's WorkbenchTM Utility, provides
the Series 32000 programmer with the tools to prepare documentation. The major components of this
package are shown in Table II.
ON-BOARD MEMORY CONFIGURATIONS
OF 4, 8 OR 16 MBYTES
The processor board is configured with either 4, 8, or
16 Mbytes of zero wait-state physical memory. It is
possible to upgrade the 4- or 8-Mbyte configuration to
16 Mbytes through the purchase of an optional 16Mbyte memory card.
TABLE II. Tools for Documenters Utilities
Name
OPERATING SYSTEM
The SYS32/30 operating system is a port of AT&T's
UNIX System V Release 3, and is derived from GENIX
V.3, National Semiconductor's port of UNIX System V
Release 3.
The UNIX operating system is a powerful, multi-user,
multitasking operating system that includes the following key features:
Demand Paged Virtual Memory
Hierarchical file system
Source Code Control System (SCCS)
UNIX to UNIX copy (uucp)
"make" utility
Menu-driven system administration
The UNIX operating system has a proven reputation
as an effective and productive environment for efficient software development. UNIX allows multiple users to work simultaneously on the same computer and
project. The Source Code Control System (SCCS) automatically tracks program revisions as development
work progresses. The "make" software saves valu-
Description
nroft
A text formatter for line printers
troft
A text formatter for typesetters
otroft
A text formatter for typesetters
mm
A macro package
mmt
A macro package
eqn
A troft preprocessor for typesetting
mathematics on a phototypesetter
neqn
A troft preprocessor for typesetting
mathematics on a terminal
tbl
A preprocessor for formatting tables
pic
A preprocessor for graphic illustrations
col
A filter to nroft for processing multicolumn
text output, as from tbl
NETWORKING CAPABILITY
The SYS32/30 based development system configured to support networking using the TCP/IP protocol
allows project development using multiple systems, including SYS32/30 based systems, VAXIVMSTM (using TCP/IP), and VAX/4.2bsd. The compatibility de-
6-5
~
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Functional Description
~
sign of the GNX language tools allows software modules developed on these networked systems to be
linked together on a single system for execution as
one program. Networking requires that additional
hardware and software be installed in the system.
Third party products that enable networking are listed
in the SYS32/30 configuration guide.
(Continued)
files via a common network. Information for configuring the SYS32/30 for integration into a network is
contained in the configuration guide.
Compilers are available as separate optional software
to allow individual selection of the application language. The C and FORTRAN compilers are the result
of National's optimizing compiler project and reflect
state-of-the-art compiler technology for optimizing execution speed. Pascal and Ada compilers are also
available. For additional details about the GNX tools
consult the GNX tools data sheet, Literature Number
114299.
Real-time kernels such as National's EXEC or
VRTX®/Series 32000 are supported by the GNX
tools. With the appropriate command-line arguments,
and when linked with appropriate libraries, the GNX
tools are used to develop code for execution with
these real-time kernels. More information on EXEC is
contained in its data sheet in the Series 32000 Databook. The VRTX data sheet (Literature Number
114269) provides more information about VRTX.
MANUALS
A complete manual set for the operating system and
related software is included in the SYS32/30 package. This includes:
Installation instructions for the PC Add-in board
Installation instructions for software
UNIX System V.3 reference manuals and user guides
GNX Language Tools Manuals
Tools for Documenters Reference Manual
Berkeley Utilities Manual
MULTI-USER SUPPORT
The SYS32/30 operating system is an interactive,
multi-user, multitasking operating system. Many activities or jobs can be performed simultaneously when
serial ports are added to the host system. These additional serial ports are used for terminals, printers, modems, 1I0-to-development boards, I/O-to-target hardware, or for communication with National's SPLICE
debugging tool. Information about third party products
that provide additional serial ports is contained in the
SYS32/30 configuration guide.
ADA COMPILER
The Series 32000 Ada cross-development system
completely supports Ada language program development on National's SYS32/30 host and is part of National's Validated Ada Development Environment
(NVADE). NVADE provides a high performance Ada
compiler that supports all required features of the Ada
language and is fully compliant with ANSI/MIL-STD1815A. Consult the data sheet (Literature Number
114262) on the Ada cross-development system for
additional details.
GNX LANGUAGE TOOLS
The GENIX Native and Cross-Support (GNX) language tools allow the user to compile, assemble, and
link user programs to create executable files. These
files can then be executed and debugged on a Series
32000 development board, target system application
hardware, or a 32000/UNIX-based system such as
the SYS32/30.
The GNX language tools include the assembler, linker, de buggers, libraries, and the monitor software for
all Series 32000 development boards in both PROM
and source code form.
The Series 32000 GNX language tools are based on
AT&T's Common Object File Format (COFF). Under
COFF, object modules created by any of the GNX
compilers or the GNX assembler may be linked to object modules of any other translator in the GNX tools.
Compilers available are FORTRAN77, C, and Pascal.
The COFF file format also allows object modules that
have been created by the GNX tools on other development hosts (VAXIVMS or VAX/4.2bsd, for example) to be linked with modules created on the
SYS32/30 system. This flexibility is most valuable
where non-centralized software development is desired and the systems are able to transfer or share
SUPPORT FOR AN INTEGRATED DEVELOPMENT
ENVIRONMENT
The SYS32/30 contains the functionality and compatibility needed to utilize other tools available from National Semiconductor for developing and debugging
Series 32000-based applications. These tools include
the SPLICE software debugger and National's Series
32000 Development Board set.
The SPLICE development tool provides a communication link between a Series 32000 target and a development system host. This connection allows users to
download and map their software onto target memory
and then debug this software using National Semiconductor's GNX debugger. Consult the SPLICE data
sheet for more information.
The Series 32000 development boards used with the
SYS32/30 are complete microcomputer systems specifically designed to assist the user in evaluating and
developing hardware and software for the Series
32000 family of CPUs. More information on the Series
32000 development boards is contained in the Series
32000 Databook, Literature Number 400094.
6-6
Functional Description
(Continued)
DOS/UNIX INTEGRATION
linked to other object files and/or libraries, resulting in
an executable file. The Ada compiler generates executable code without creating assembly language as
an intermediate step.
Since the SYS32/30 provides a Series 32000 native
environment, the executable file may be run on the
host SYS32/30 system or loaded into RAM on either
a target system, SPLICE, or one of the Series 32000
development boards. The source-level software debuggers in the GNX tools provide powerful facilities for
debugging software on the target system.
The GNX debugger, working in conjunction with
SPLICE or with the monitor program on the target
board, is capable of downloading and controlling the
execution of software on the target system. Executable monitor software is provided in PROMs in the
SYS32/30 package for the Series 32000 development boards. Monitor software is also provided in
source form in the GNX language tools so application
designers can modify and port the monitor to suit the
needs of their target system.
After debugging, the executable file created by linking
can also be converted to PROM format using the GNX
nburn utility.
The SYS32/30 PC add-in development package allows easy transfer of data between DOS and the
UNIX operating system. A system console user can
switch between either operating system using only a
few keystrokes. A shell interface allows DOS commands to be executed from the UNIX shell, UNIX
commands to be executed from DOS, and files to be
transferred between the UNIX and DOS partitions on
the system disk. In addition, the user can suspend the
SYS32/30 operation, enter DOS, run an application,
and then return to the SYS32/30 environment.
Series 32000 Application Development
The SYS32/30 with the PC/AT operates as a local
host computer system for integrating application software into target prototype boards containing Series
32000 components. Programs can be written in assembly language or in a higher level language. Optional compilers are available for C, FORTRAN, Pascal,
and Ada.
During compilation, the C, FORTRAN, and Pascal
compilers generate assembly code which is assembled by the GNX assembler. (See Figure 3.) The output of the assembler is an object file which can be
TO
TARGET
SYSTEM,
SPLICE, OR
DB BOARD
TL/EE/9420-4
FIGURE 3
6-7
C)
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......
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r---------------------------------------------------------------------------------,
Configuring a System
Basic Kits
The SYS32/30 PC Add-In package supports a variety
of configurations. Based on developer needs, the final
configuration may need extra serial 1/0 ports, and/or
networking capability. A hard disk of sufficient size is
also an important part of the configuration. A configuration guide that outlines available options and recommended products for configuring the SYS32/30 development system is available.
Host system elements required for SYS32/30 operation are:
- IBM PC/AT or compatible system
- Two full length slots in the motherboard
- 512 Kbytes of RAM
- PC-DOS 3.1 or later
- 1.2-Mbyte floppy disk drive
- Adequate hard disk storage (see the next section
on disk size)
The SYS32/30 Add-In Development package is available in three basic kits:
NSS-SYS30-KIT1
For IBM-AT and compatible
systems
PC Add-In coprocessor board
with 4 Mbytes on-board memory
UNIX System V.3 based operating system
GNX Language Tools
Tools for Documenters
Berkeley Utilities
Installation instructions for the
PC Add-In board
Installation instructions for software
UNIX System V.3 reference
manuals and user guides
GNX Language Tools Manuals
Tools For Documenters Reference Manuals
Berkeley Utilities Manual
Same as KIT1 except with
NSS-SYS30-KIT2
8 Mbytes of on-board memory
NSS-SYS30-KIT3
Same as KIT1 except with
16 Mbytes of on-board memory
Note: The SYS32/30 processor board actually plugs into a single slot.
The second slot is required to accommodate the space taken by
the piggybacked memory board attached to the NS32332 proces·
sor board.
The SYS32/30 PC/AT Add-In Development Package
runs on an IBM PC/AT or compatible computer. If an
IBM PCI AT is not used for the host system, it is important to remember that compatibility can vary between
IBM PCI AT compatible systems. The SYS32/30 processor board may not be adequately supported by systems that lack full IBM PC/AT compatibility. The configuration guide available contains a list of IBM PC/AT
compatible systems that have the required compatibility.
MEMORY UPGRADE
To upgrade the memory size to 16 Mbytes after the
purchase of KIT1 or KIT2, the following 16-Mbyte
memory board must be purchased to replace the existing memory board:
NSS-SYS30-MEM16 16-Mbyte memory board.
HARD DISK CAPACITY
Several factors influence the size selected for a hard
disk. Consideration should include the number of users for the system, space for user files, the size of the
application to be developed, and extra software packages and compilers that must reside on the system.
For example, a 40-Mbyte hard disk is the minimum
size recommended for a SYS32/30-based development environment. This provides sufficient space for a
single-user account, the UNIX operating system and
utilities, the GNX tools, compiler software, basic DOS
software, and a moderate size application. If the system is used for developing an Ada-based application,
a minimum of 60 Mbytes of disk storage is recommended. Disk drives with even greater capacity than
the minimum sizes indicated here should be considered for additional users or software and to provide for
growth of the system.
When selecting hard disk drives or other peripheral
devices, it is important that the device conform to the
industry-standard for peripheral devices deSigned for
use on the PCI AT bus.
Optional Software Packages
(A prerequisite for use is the purchase of one of the
above basic kits).
Optimizing C Compiler
NSW-C-BHBF3
NSW-F77-BHBF3
Optimizing FORTRAN77 compiler
NSW-PAS-BHBF3
Pascal compiler
NSW-ADA-BHBF
Ada compiler
NSW-NET-BHBF3
Networking software
NSP-SYS321V3-MS Additional operating system
manual set
6-8
,--------------------------------------------------------------------------, w
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w
• National Semiconductor
Co)
N
......
N
SYS32/20 PC Add-In Development Package
TL/C/9250-1
•
•
•
High Performance, 10 MHz, no-wait state,
32-bit expansion board for an
IBM-PC/AT or compatible system
• An Operating System derived from
AT&T's UNIX® System V.3
• The Series 32000 GNX (GENIX Native
and Cross-Support) Language tools
including the Series 32000 assembler,
linker, monitors and debuggers
• Hardware that supports the NS32032
CPU, NS32082 MMU, NS32201 TCU and
the NS32081 FPU
• Two available on-board memory
configurations:
- 2-Mbyte RAM
-4-MByte RAM
Software available on 1.2-MByte floppies
Complete support for the following
application tools:
-SPLICE
- National's Series 32000 Development
Board Family
- Compilers for C, FORTRAN??, Pascal
and Ada
- Complete System V Documentation
- 4.2 "bsd" Utilities
- Tools for Documentors (TFD), a
derivative of AT&T's DWBTM utilities
- Multiuser environment
Description
VAX 780. The SYS32/20 consists of a 32-bit PC AddIn board based on the Series 32000 chip set, a complete port of AT&T's UNIX® System V.3 specially developed software that integrates the UNIX and DOS
operating systems, and National's Series 32000 development tools (GNX).
National Semiconductor's SYS32/20 is a complete,
high performance development package that converts
an IBM-PC/AT or compatible system into an ideal environment for the support of Series 32000®-based applications. The SYS32/20 PC Add-In Development
Package allows mainframe-size programs to run on a
personal computer at speeds similar to those of a
6-9
o
~r-------------------------------------------------------------~
C\i
CO)
Hardware
~
The SYS32/20 hardware consists of a Series 32000
chip set on a single-slot co-processor board. The chip
set includes an NS32032 CPU with either 2 or 4
MBytes of on-board memory.· The hardware is an
IBM PC Add-In board that plugs into the no-wait-state
motherboard. No additional connections are required.
Up to 8 serial ports can be used on all supported PCs.
Parallel ports are also supported. The SYS32/20 AddIn board supports a variety of Series 32000 family
components including the high-performance, 10 MHz
NS32032 Central Processing Unit, the NS32082
Mem0r:Y Management Unit, the NS32201 Timing Control Unit and the NS32081 Floating-Point Unit.
adding the desired software subsets. User-friendly
software guides you easily through each stage of installation.
Integrated Environment
The SYS32/20 PC Add-In Development Package allows data to be easily shared between DOS and the
UNIX System V Operating system. A user can switch
between either operating system using only a few keystrokes. A shell interface allows DOS commands to
be executed from the System V shell, System V commands to be executed from DOS, and files to be
transferred between the System V and DOS partitions
on the system disk. In addition, the user can suspend
the SYS32/20 operation, enter DOS, run an application and then return to the SYS32/20 environment.
Software
The SYS32/20 contains the OpUS5™ operating system. Opus5 is a complete port of AT&T's UNIX
System V Release 3 (V.3), and is derived from GENIXIV.3, National Semiconductor's port of UNIX System V.3.
System V is an advanced, proven programming environment that fully supports the Series 32000 microprocessor family, including Demand-Paged Virtual
Memory (DPVM). System V's general-purpose, multitasking, interactive system makes the programmer's
computing environment simple, efficient and productive.
The SYS32/20 Add-In board can also be used to execute object code under a native environment. Object
files conform to a superset of the AT&T Common Object File Format (COFF), and take full advantage of
the advanced features of the Series 32000 architecture. The GNX (GENIX Native and Cross-Support)
software consists of an assembler, a linker, debuggers, monitors, basic I/O routines and other tools that
support a group of optional compilers such as C, Pascal and FORTRAN77. Other software features supported by the SYS32/20 include Tools for Documenters.
Support for Hardware/Software Integration
Two solutions are available for integrating application
software, created under the PC-SYS32/20 development environment with target prototype. The PC with
SYS32/20 operates as a local host computer system
for the environments of both solutions. Under the environment of both solutions, the high language software debuggers provide powerful emulation facilities
to test and shakeout the integrated hardware/software target system until a proven product is achieved.
Such facilities include setting of breakpoints and registers and memory data display and modifications.
The first solution requires the use of an In-System Emulator (ISE). The SYS32/20 Add-In Development
Package supports National's ISE32 (In-System Emulator for the NS32032). The ISE software consists of
the ISE monitor firmware, which resides in PROMs in
the emulator pod, and the ISE Debugger (IDBG),
which is included with, and runs on the SYS32/20.
The monitor firmware controls the ISE hardware. The
IDBG is a high-level, user-friendly debugger program.
It translates commands entered by the user, into lowlevel instructions the ISE monitor uses to drive the
hardware. IDBG also translates and sends ISE responses to the user.
The second solution requires the use of monitor firmware programs running in the user's target hardware
and Debugger (DBG). DBG is a superset of the IDBG
described in the first solution above, and, like IDBG, is
included with, and runs on, the SYS32/20. DBG performs the same functions as IDBG. The monitor
downloads and controls the execution of the user's
software. Monitor firmware programs include MON16
(monitor firmware program for NS32016-based target
hardware) and MON32 (monitor firmware program for
Installation
Installation of the SYS32/20 PC Add-In Package is
straight-forward and well-documented.
The SYS32/20 software occupies a PC fixed disk in
one of two ways: it either uses a separate partition for
the logical disk or it uses a large DOS file. The first
method is necessary for file systems larger than 28
Mbytes; the second method is recommended for fixed
disks that don't use the ROM BIOS interface.
Installation is divided into three general stages: partitioning the fixed disk, installing the core system, and
'Note: The hardware configuration does not allow the 2·Mbyte version
to be upgraded to the 4-Mbyte version.
6-10
BasiC Kits (Note: No Compiler Included.)
NS32032-based target hardware). These monitor firmware programs are provided in PROMs and included
with SYS32/20. The monitors are also provided in
source form so Series 32000 designers can modify
the monitor to suit their target system requirements.
NSS-SYS203-KIT1 For IBM-AT and compatible systems; 2MB on-board memory;
UNIX System V.3 Operating System; GNX Assembler tools; "bsd"
and Tools For Documenters utilities; software on 1.2 MB high density floppy diskettes; a complete
set of manuals, including AT&T
UNIX System V.3 manuals.
NSS-SYS203-KIT2 For IBM-AT and compatible systems; same as KIT1 except with
4MB on-board memory.
Configuring a System
The SYS32/20 PC Add-In package supports a variety
of configurations. Based on developer needs, the final
configuration may need extra serial I/O ports, and/or
networking capability. A hard disk of sufficient size is
also an important part of the configuration. A configuration guide that outlines available options and recommended products for configuring the SYS32/20 development system is available.
Optional Software Packages
.
(Prerequisite for use is purchase of the above basIc
kits.)
The following software should be ordered for execution on the System V.3-derived operating system.
Available on high density diskettes only.
NSW-C-BHAF3
Optimizing C compiler.
NSW-F??-BHAF3
Optimizing FORTRAN?? compiler.
NSW-PAS-BHAF3
Pascal compiler.
NSW-ADA-BHBF
Ada compiler.
Networking software.
NSW-NET-BHAF3
NSP-SYS321V3-MS Additional V.3 operating system manual sets.
Minimum System Configuration
The following list specifies the minimum configuration
required to install a SYS32/20 PC Add-In Board:
• 30-Mbyte hard disk. (40-Mbyte or larger is strongly
recommended.)
• 512 Kbytes of RAM.
• PC/AT or compatible personal computer system.
• PC-DOS 3.1 or later operating system.
• Slots:
-The 2-Mbyte board consists of 1 full board +
1/2 piggyback board and may require 2 slots depending on the arrangement of other expansion
boards in the PC.
-The 4-Mbyte board consists of 1 full board + 1
full piggyback board and may require 2 slots depending on the arrangement of other expansion
boards in the PC.
Note: For purchase of any and all software packages (NSW· ... ) user
must show or demonstrate proof of prior purchase of one of the NSS·
SYS203·KITx packages above.
6-11
N
~
r-------------------------------------------------------------------~
~ National Semiconductor
ISE32™ NS32032 In-System Emulator
TL/R/8522-1
bus activity trace
•• Complete
Qualified tracing
Pre-, post-, or center-triggering on trace
•• Two
32-bit execution counters
Supports Memory Management Unit
• functions
under various host systems
• Supported
and operating systems
on-line help facility
•• Hierarchical
Self-diagnostic
up to 10 MHz*
• Operation
Emulation of NS32032 Central
• Processing Unit, NS32082 Memory
•
•
•
•
•
Management Unit, NS32201 Timing
Control Unit
Host resident debuggers
Generalized event driven system
Memory mapping, up to 128 kbytes
Read/write protection of 4 kbyte
memory blocks
Program flow traCing, up to 1023 nonsequential fetches
'Refer to ISE speed consideration section.
Description
The NS32032 In-System Emulator (ISE32) is a powerful tool for both hardware and software development
of NS32032 microprocessor-based products.
The ISE32 emulates the NS32032 Central Processing
Unit (CPU), the NS32201 Timing Control Unit (TCU)
and NS32082 Memory Management Unit (MMU).
NS32082 MMU emulation can be disabled by a switch
setting. The ISE32 allows users to test and debug
both hardware and software in their own hardware environment.
The ISE32 is a complete unit, including an internal
clock oscillator that generates a choice of three clock
signals: 10 MHz, 5 MHz, and 2.5 MHz; and 128 kbytes
of dedicated user's ISETM memory. With the ISE32,
users can easily stop emulation and examine the contents of CPU registers, slave processor registers, and
memory.
The ISE32 consists of the ISE hardware, the ISE firmware monitor, and RS232 cables. A host-dependent
debugger software program is available as part of the
appropriate Series 32000® software support package.
Each of the Series 32000 software support packages
include software tools to produce code compatible
with the debugger software. Refer to the section "Required User-Supplied Equipment".
Hardware Description
The ISE32 hardware is housed in three enclosures:
the ISE Support Box; the Emulator Pod; and the TIL
Status Pod. Figure 1 is a block diagram of ISE32 hardware.
The ISE Support Box is the largest enclosure. It contains the emulation support circuits for trace, breakpoints, and mapped memory; as well as the hardware
for the RS232 serial ports, which are used to communicate with the host and the user's terminal. It also
houses the power supplies and the ISE32 control
switches and indicators. Figure 2 shows the location
of the ISE32 control switches and indicators. Table I
lists the functions of each switch and LED.
The Emulator Pod contains the NS32032 CPU,
NS32082 MMU, and NS32201 TCU required for target
system emulation. It also contains the ISE Monitor
firmware.
6-12
.---------------------------------------------------------~0
The Emulator Pod connects to the ISE Support Box
via a four-foot flat cable assembly. Connections to the
target system are made via three one-foot target cables. One target cable is provided for each member of
the Series 32000 chip set (CPU, MMU, and TCU).
The Status Pod is the smallest enclosure. It provides
TTL-compatible input and output signals for use during ISE operation. The Status Pod has ten leads and
three binder posts that can be connected to either the
target system or test equipment such as logic analyzers or oscilloscopes. Table II lists the function of each
lead and post of the Status Pod. The Status Pod connects to the ISE Support Box via a six-foot cable.
When the ISE32 unit is not running an emulation program, it is running a program called the ISE monitor.
The monitor communicates with the ISE Debugger
and provides a command protocol that allows the host
complete control of the ISE32 hardware.
The ISE Debugger translates commands entered on
the host system from a terminal, into low-level instructions that the ISE monitor uses to drive the hardware.
The ISE Debugger also translates and sends ISE responses to the user via the terminal. All ISE monitor
operation is transparent to the user.
The ISE32 Debugger
The ISE32 Debugger is user compatible with the standard non-ISE Series 32000 Debugger. Compatibility
ISE32 Software Overview
The ISE32 software consists of the ISE firmware monitor, which resides in PROMs in the Emulator Pod, and
the ISE Debugger, which runs on the host system.
HOST
SYSTEM
TLL
STATUS POD
TERMINAL
.--=--,
POD
AC
INPUT
TLlR/B522-4
FIGURE 1. ISE32 Block Diagram
IDLE
ISE NO.
111I'e21'1
ON~OFF
MMU
EMUL
FAIL RUN
• • ~C,~
• .J
~
STOP
TAR 'SE
[~w:J
RESET
FRONT PANEL
TL/R/B522-3
FIGURE 2. ISE32 Controls and Indicators
6-13
m
~
N
~
CO)
LLI
~
,---------------------------------------------------------------------------------,
minimizes the user's learning time of the various development tools. The ISE32 Debugger fully supports
all the powerful debugging and emulation facilities
provided by the ISE32 hardware, and supplements
these features with a very powerful software-based
program debugging environment.
The basic debugging features of the ISE32 are as follows:
(1) Supports both high-level and assembly languages·.
(2) Breakpoints can be set at the source code level,
even when using high-level languages.·
(3) Supports symbolic debugging; variables can be
referenced by their source code names.·
(4) Certain procedure parameters and variables are
easily displayed.
(5) Structured data types and pointers are easily displayed.
(6) Supports both command and history files.
(7) Memory can be displayed in many different ways,
including a disassembly mode displaying memory
as NS32032 instructions.
(8) Supports all the emulation and debug facilities provided by the ISE32 hardware.
• Depends on host environment and language.
Modes of Operation
ISE32 can be set-up to operate in either stand-aside
mode or transparent mode.
In stand-aside mode, one serial RS232 link from the
host system is connected to the ISE32 while another
serial RS232 from the host system is connected to the
user's terminal. In this configuration, any of the host's
users can access the ISE32.
In transparent mode, one serial RS232 link from the
host system is connected to one serial port on the
ISE32 while the user terminal is connected to a second serial port on the ISE32. In this configuration, only
one serial port is required from the host system. In
non-emulation mode, the ISE32 is transparent to the
user, allowing normal communication between the
user and the host system.
ISE32 Operation
Human Interface
ISE32 is easy to learn and easy to use. The software
includes a complete on-line help facility. Invoking the
TABLE I. ISE32 Control and Indicator Functions
Control/Indicator
ISE NO. Switch
MMU Switch
STOP Switch
RESET Switch
IDLE
EMUL
FAIL
RUN
TAR
ISE
Function
Set to 0; other positions reserved.
When ON, ISE32 enables MMU operation.
Interrupts emulations, restores control to the ISE32 monitor.
Resets the ISE32 hardware.
Warning that POD CPU is in a wait state. (Time out)
Indicates that ISE32 is executing the user's program.
Warning that diagnostics have failed.
Indicates that ISE32 diagnostics are running.
Indicates that target power is on.
Indicates that ISE32 is on.
TABLE II Status Pod Signal Description
ISE Function
Status Pod Label
Leads
1-WHT-USRCLK-U
2-BLK-GND
3-BRN-EXTO-U
4-RED-EXT1
5-0RN-EXT2
6-YEL-EXT3
7-GRN-EXT4
8-BLU-EXT5
9-VIO-EXT6
10-GRY-EXT7
11-WHT-USEBRK/U
Not Used
Common Ground
EXTO (external input 0)
EXT1 (external input 1)
EXT2 (external input 2)
EXT3 (external input 3)
EXT4 (external input 4)
EXT5 (external input 5)
EXT6 (external input 6)
EXT7 (external input 7)
IS (input sync)
Posts
TBRUN
BKSYNCH/-U
TRSYNCH/-U
GND
TSYNC31/
TSYNC21
GND
Not Used
Output Sync
Not Used
Common Ground
Not Used
Not Used
Common Ground
6-14
"HELP" command gives a summary of alllSE32 commands, an individual command, or an individual commands parameters. This feature helps the user get his
work done quickly with less frustration.
- Byte Enable Pins
- Data Direction Pin
- Status Bits
- Interlock Bit
- Masked combinations of any of the above options.
Either virtual or physical addresses can be sampled.
ISE32 also provides a range breakpoint event, R. The
range breakpoint can be qualified by any of the above
options within a specified address range.
Any breakpoint can cause emulation to stop immediately. Also, if used with the No Stop option, breakpoints can be combined with other events to cause a
variety of action.
Emulation
The ISE32 unit has its own CPU, MMU, and TCU components. These components are connected to the target system via cables. These components perform the
same functions, with close to the same timing characteristics as they would if mounted in the target
system.' The ISE32 does not require wait states for
operation.
Emulation memory, resident in the ISE32, can be used
instead of target system memory. This feature is implemented by the mapping capabilities. With this feature, the ISE32 can run and debug programs without a
working target system. User target memory from the
entire address space of the CPU or MMU (whether it
exists or not) can be mapped onto the ISE32 emulation memory in 4 kbyte blocks. The total amount of
mapped memory cannot exceed 32 4 kbyte blocks
(128 kbytes).
Associated with the emulation memory mapping
scheme is a capability for read/write protection. Any 4
kbyte block within the address space of the CPU or
MMU can be protected.
Event-Expressions
An event-expression is a Boolean expression made
up of simple events, Le., a logical combination of simple events. This allows the user to generate many different event combinations, tailored to system activity
of particular interest to the user. These generalized
events are used by many ISE32 commands such as
stop, trace, event counting, etc. Event-expressions
provide creative and flexible debugging procedures.
Event-expressions can be evaluated as either logically
true or logically false. Valid logic operations for event
expressions are: Negation (NOT), AND, and OR.
Generalized Events
Stopping Execution on Events
To provide a versatile way of observing and controlling the significant state changes on the microprocessor, ISE32 allows the use and definition of "events".
In general, a simple event is a breakpoint, a bus
change, or a significant observation. An event can
also be a logical combination of simple events (an
Event-Expression).
A common debugging activity is to stop emulation on
the occurrence of an event of interest. Stopping emulation puts ISE32 in the monitor mode so the user can
examine and alter the state of the CPU, memory, and
ISE32 functions. Emulation can be stopped on either
simple events or event-expressions.
Simple Event Definition
ISE32 maintains a 1023-entry trace memory. Trace
memory captures bus activity in one of two trace
modes:
- Program Flow Trace
- Memory Bus Trace
Any combination of events can be used to qualify tracing. When enabled, tracing in either mode continues
until a specified terminating event occurs. The actual
end of tracing can be delayed after the terminating
event by a count of 1 to 1023. This allows trace data
to be captured before, after, or around the terminating
event.
Flexible Tracing
The simple events are:
- Breakpoints
- Latched Events
- Counter Done
- Status Pod Inputs
- Trace Done
Breakpoint Events
ISE32 provides four common breakpoint events,
named A, B, C, and D. The breakpoint event can be
used in two ways:
(1) Execution Breakpoint-occurs just prior to execution of an instruction at a specified address.
(2) Reference Breakpoint-occurs on a match when
sampling:
- Address Bits
- Data Bits
- External Status Bits
- User/Supervisor Pin
Program Flow Trace
The Program Flow Trace mode captures the CPU Program Counter address of 1023 non-sequential instructions. This mode also maintains a count of sequential
instructions executed between each non-sequential
instruction stored in the trace memory.
Memory Bus Trace
The Memory Bus Trace mode captures a summary of
the following system parameters:
- Address bus contents
• Refer to ISE speed consideration section.
6-15
enm
w
N
~
C")
LLI
!l
r---------------------------------------------------------------------------------,
-
Data bus contents
CPU status (data transfer, non-sequential fetch, interrupt acknowledge, etc.)
Time base counter contents
PFS counter contents
Status Pod external inputs
States of the following CPU pins:
UNS-UserlNot Supervisor
BEO-BE3-Byte Enable
DDIN-Data Direction In
NMI-Non-Maskable Interrupt
ILO-Interlock
duce timing margins in that hardware; i.e., combined
propagation paths are lengthened by the ISE32 target
cable and transceiver delays.
If sufficient timing margins are not restored, emulation
may not be successful. In many cases, margin can be
restored by reducing the emulation speed, lengthening the available time for signals to propagate. However, the exact speed reduction necessary to regain
margins will depend on how Series 32000 components are used in the customer hardware. Tables III,
IV and V list the combined cable and transceiver maximum propagation delay for each signal. It is the customer's responsibility to factor these delays with those
of his own circuitry. In doing so, it can be determined
whether ISE32 can reliably emulate with that circuitry.
Counters
The ISE32 contains two 32-bit counters with an overflow flag that may be used to count events, instruction
cycles, memory cycles, or clock cycles. The counters
may be programmed to start and stop counting on
specific events. This permits counters to be used as
timers to determine relative timing differences between various events. One use of this feature is to
measure software or hardware performance. The
counters may also be used to generate other ISE32
events upon completion of a count.
Supported Configurations
This product is designed to work in most target systems configurations. However, certain design restrictions may apply. Refer to the ISE32 User's Manual for
further information. (See "Documentation section")
Required User-Supplied Equipment
For use with SYS32TM/GENIXTM Systems:
- Included with the GENIX Operating System Software Package.
For use with VR32/System V /Series 32000
- Included with the System V/32000 Operating System Software Package.
For use with VAXTM/UNIXTM Systems:
- Valid DEC VAX-11TM configuration with available
RS232 port.
- Berkeley UNIX 4.2 bsd Operating System.
- NSW-C-4VXR Series 32000 Cross Software Package.
For use with VAXIVMSTM Systems:
• Valid DEC VAX/11 configuration with available
RS232 port.
• VMSTM Operating System, Version 4.2 or later.
• NSW-ASSEMB-9VMR or NSW-PASCAL-9VMR Series 32000 Cross Software Package.
Event Trigger for External Test Equipment
ISE32 events can trigger external test equipment,
such as oscilloscopes and logic analyzers. This test
equipment can be used in conjunction with the
ISE32's debugging features to solve system timing
problems. The external trigger signal is available at
the status pod output:
- BKSYNCH/-U (Output Sync)
Self-Test Diagnostics
At power-up, ISE32 runs a diagnostic program to verify ISE firmware integrity and proper hardware function.
ISE32 Timing Options
ISE32 includes the following timing options:
- Sampling time can be set to sample either virtual
or physical addresses
- Status Pod external lines can be sampled at either
data valid or address valid times
- The emulation clock frequency can be set to one
of the following frequencies:
2.5 MHz
5.0 MHz
10.0 MHz
Target Board Frequency
Specifications
Environmental
Power
ISE Speed Considerations
ISE32 utilizes standard, 10 MHz NS32032, NS32082
and NS32201 devices to perform control and emulation functions. When emulating, each device is connected to customer hardware via a target cable and
associated cable transceivers. This arrangement delays the signal propagation between the Series 32000
components in the ISE32 POD and Series 32000
sockets in the customer hardware. These delays re-
Operating Temperature
+10·Cto +40·C
Storage Temperature
- 20·C to + 65·C
2.5A @ 115 VAC, 50/60 Hz, single
phase 1.5A @ 220 VAC, 50/60 Hz,
single phase. Approximately 1170
BTU.
Physical
ISE Support Box Height:
Width:
Depth:
Emulation Pod
Height:
Width:
Depth:
6-16
5.8 in. (14.7 cm)
18.5 in. (47.1 cm)
12.3 in. (31.2 cm)
2.1 in. (5.3 cm)
9.3 in. (23.6 cm)
10.0 in. (25.4 cm)
Specifications (Continued)
TTL Status Pod
Cable Lengths
Target Interface
Electrical
Characteristics- See Tables III through V.
Height: 1.0 in. (2.5 cm)
Width: 3.125 in. (7.9 cm)
Depth: 6.125 in. (15.6 cm)
ISE Support Box to Emulation Pod:
4.0 ft. (1.22M)
ISE Support Box to TTL Status
Pod: 6.0 1t. (1.B3M)
Emulation Pod to Target Board:
1.0 ft. (0.30M)
Order Information
Complete ISE32 Units
NSS-ISE32
NSS-ISE32E
ISE32 (NS32032), 115 VAC
ISE32 (NS32032), 220 VAC
TABLE III. Electrical Characteristics for TCU Interface
Signal
Name
Interface
Device
Outgoing Signals
NTSO
CTTL
FCLK
NDBE
NRD
NWR
NRSTO
RDY
IOH
15 mA
15 mA
15mA
15mA
15 mA
15mA
15mA
15mA
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
Incoming Signals
NPER
NCWAIT
NWAIT1
NWAIT2
NWAIT4
NWAITB
XCTL1
NRWEN
NRST1
Propagation
Delay Time
Tpd*
Input And/Or
Output Current
74F244
74F244
74ALS244
74ALS244
74F244
74ALS244
74F244
74F244
74ALS244
IOL
t4BmA
t4BmA
t4BmA
t4BmA
t4BmA
t4BmA
t4BmA
t4BmA
IIH
IlL
20 IlA
20 }LA
20 IlA
20 IlA
20 IlA
20 IlA
20 IlA
20 IlA
20 IlA
1.6mA
1.6mA
0.1 mA
0.1 mA
1.6mA
0.1 mA
1.6mA
1.6mA
0.1 mA
12.4 ns
12.4 ns
12.4 ns
12.4 ns
12.4 ns
12.4 ns
12.4 ns
12.4 ns
7.9 ns
7.9 ns
12.4 ns
12.4 ns
14.5 ns
12.4 ns
7.9 ns
7.9 ns
12.4 ns
'Interface device, plus cable.
tFor Vee maintained between 4.75V and 5.25V.
TABLE IV. Electrical Characteristics for MMU Interface
Signal
Name
Input AndlOr
Output Current
IOH
IOL
IIH
IlL
Propagation
Delay Time
Tpd*
15mA
t4BmA
20 IlA
0.1 mA
11.4 ns
15 rnA
15mA
15mA
15mA
15mA
t4BmA
t4BmA
t4BmA
t4BmA
t4BmA
-
-
-
12.4 ns
12.4 ns
12.4 ns
12.4 ns
12.4 ns
20 IlA
O.4mA
19.4 ns
Interface
Device
BIDIRECTIONAL SIGNAL
NPAV
74ALS245
OUTGOING SIGNALS
A24
MMUINT
NABT
NFLT
NHLDAO
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
-
-
-
INCOMING SIGNALS
NHOLD
74LS126
-
-
'Interface device, plus cable.
tFor Vee maintained between 4.75V and 5.25V.
6·17
N
r--------------------------------------------------------------------------,
UJ
TABLE V. Electrical Characteristics for CPU Interface
C')
!a
Signal
Name
Input AndlOr
Output Current
IOH
IOL
IIH
IlL
Propagation
Delay Time
Tpd*
Interface
Device
BIDIRECTIONAL SIGNAL
NSPC
74ALS245
15 mA
t48mA
20/LA
0.1 mA
12 ns
ADOO
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
D24
D25
D26
D27
D28
D29
D30
D31
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
15mA
15 mA
15 mA
15 mA
15 mA
15 mA
15 mA
15mA
15 mA
15 mA
15 mA
15 mA
15mA
15 mA
15 mA
15 mA
15 mA
15 mA
15 mA
15 mA
15mA
15 mA
15 mA
15 mA
15mA
15 mA
15 mA
15 mA
15 mA
15mA
15 mA
15 mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
N8mA
t48mA
t48mA
t48mA
t48mA
N8mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
N8mA
t48mA
t48mA
t48mA
N8mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
20/LA
20/LA
20/LA
20/LA
20 ""A
20/LA
20 ""A
20/LA
20,...A
20/LA
20 ""A
20 ""A
20 ""A
20 ""A
20/LA
20/LA
20 ""A
20/LA
20/LA
20/LA
20 ""A
20/LA
20 ""A
20/LA
20 ""A
20 ""A
20 ""A
20/LA
20/LA
20 ""A
20 ""A
20 ""A
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
NNDIN
NADS
NBEO
NBE1
NBE2
NBE3
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
74ALS245
15 mA
15 mA
15mA
15 mA
15 mA
15 mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
20 ""A
20 ""A
20/LA
20 ""A
20 ""A
20 ""A
0.1
0.1
0.1
0.1
0.1
0.1
mA
mA
mA
mA
mA
mA
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
'Interface device, plus cable.
"tFor Vee maintained between 4.75V and 5.25V.
6·18
Signal
Name
Outgoing signals
NILO
STO
ST1
ST2
ST3
NPFS
UNS
BB
NOS
NBRO
NHLOA
Input AndlOr
Output Current
Interface
Device
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74ALS244
74F244
74ALS244
IOH
IOL
15mA
15mA
15mA
15mA
15mA
15 mA
15 mA
15 mA
15mA
15mA
15mA
t48mA
t48mA
t48mA
N8mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
t48mA
Incoming signals
TGTPC
NINTC
NMI
NBRI
NHOLOC
IIH
IlL
-
-
20mA
20mA
20mA
20mA
0.1 mA
0.1 mA
1.6mA
0.1 mA
74ALS244
74ALS244
74F244
74ALS244
Propagation
Delay Time
Tpd*
13.0 ns
13.0 ns
13.0 ns
13.0 ns
13.0 ns
13.0 ns
13.0 ns
13.0 ns
13.0 ns
8.5 ns
13.0 ns
13.0 ns
19.6 ns
8.5 ns
19.6 ns
'Including internal logic, interface device, and cable.
tFor Vee maintained between 4.75V and 5.25V.
Documentation
tion. (Included with the appropriate Series 32000 support software package.)
NSP-ISE32VMS-M ISE32 User's Manual for VAX/
VMS operation. (Included with
the appropriate Series 32000
cross-support software package.)
NSP-ISE32GNX-M ISE32 User's Manual for SYS32/
GENIX and VAX/UNIX operation.
(Included with the appropriate
Series 32000 support/cross-support software package.)
NSP-ISE32COF-M ISE32 User's Manual for VR32/
System V /Series 32000 opera-
6-19
~
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~
r---------------------------------------------------------------------------------,
ISE32 Debugger Command Summary
The following comprehensive list of ISE32 Debugger commands is in alphabetical order. Refer to the ISE32
User's Manual for a detailed description of each command.
Command
Begin
Breakpoint Create
Breakpoint Delete
Breakpoint Print
Breakpoint Revive
Indirect File
Debugger String
Define Counter
Define Latch
Define Output Sync
Define Stop
Define Trace
Disassemble
Go
Help
In
List Calls
List Definition
List Files
List Information
List Modules
List Strings
List Trace
Map Create
Map Print
Memory Fill
Function
Command
Load the program into
memory and initializes
registers.
Creates breakpoint A, B, C, D
at specified address or,
creates RANGE breakpoint
at specified address range.
Deletes specified breakpoint.
Print address and conditions
of specified breakpoints.
Revives specified breakpoint.
Executes command file or
debugger string.
Sets debugger string.
Defines set up for ISE
counter 1 or 2.
Defines the latch 0 or latch 1
event.
Defines output sync event.
Defines stop event.
Defines the end, delay, and
trace mode parameter for
trace.
Disassembles instructions.
Starts execution of the
program.
Displays general help.
Checks that the contents of
address or register are within
a specified range.
List entries in a call.
Lists current definitions.
Lists nine entries of a
selected file.
Lists current ISE status.
Lists modules in current
program.
Lists current debugger string
values.
Lists nine trace entries.
Maps and/or protects 4
kbyte blocks in a specified
address range.
Prints current mapping.
Fills specified address range
with value.
Memory Move
Memory Search
On
Print
Print Address
Protection Create
Protection Print
Quit
Repeat
Replace
Select Echo
Select Full
Select History
Select Link
Select Module
Select Options
Select Radix
Step
Step Call
Step Down
Step Instruction
Step Until
Step While
6·20
Function
Moves memory content
from address range to
address range.
Searches for value.
Sets idbg32 response on
condition.
Prints content of address
range or registers.
Prints absolute address and
module area associated
with address.
Creates protectionl
translation for pages
specified by address range.
Prints protection level
status.
Terminates session.
Repeats previous
command.
Replaces content of
address or register.
Selects echo mode.
Selects full symbolic PC.
Selects history file.
Selects communication
·channel.
Selects module.
Select current ISE operation
option.
Select global radix.
Execute specified number
of machine instructions.
Executes until a call or
return.
Executes one instruction
inside a procedure, skips
over call instructions.
Executes specified number
of instructions inside a
module.
Executes instructions until
contents of address or
register are within specified
value.
Executes instructions while
contents of address or
register are within specified
value.
.--------------------------------------------------------------------------00
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2.
TLlR/9347-1
•
•
•
•
•
III Parallel I/O port reserved for future
Download capabilities via serial
connections
256 Kbytes of mappable memory
Optional 1-Mbyte memory board,
expands memory up to 8 Mbytes
On-board monitor with power-on
diagnostics
Supports Series 32000 CPUs,
including: NS32332 NS32CG16
.
NS32032 NS32C032
NS32016 NS32C016
NS32008
highspeed download capabilities
Programmable serial port baud rates
CI CPU bus status test pOints for logic
analyzer connections
Ill! 4 LED indicators for diagnostic results
and general user applications
rJ RESET and NMI push buttons
m 15 MHz maximum operation
[l
1.0 Product Overview
The SPLICE Development Tool provides a communication link between a Series 32000 target and a development system host. This connection allows users to
download and map their software onto target memory
and then debug this software using National Semiconductor's debuggers.
SPLICE includes two RS232 serial ports for the system host/terminal. These ports are particularly useful
for target systems that have no serial ports, such as
embedded controller designs.
SPLICE is also useful for designs with ROM-based
software, or designs whose memory portion has not
yet been built. SPLICE provides 256 Kbytes of SRAM
which users can map into target memory. Using
mapped memory considerably reduces software development time.
SPLICE also uses the target system's chipset. This
cost-effective feature is achieved through the use of
CPU and MMU target cables.
6-21
'0
{!.
2.0 Description of Features
C
2.1 PHYSICAL DESCRIPTION
E
Q,
The SPLICE logic board is a 7" by 9" printed circuit
board that is the base unit for all operating configurations. Accessory parts include an expansion memory
board and target cables (see Sections 2.4 and 2.6).
Figure 2 shows the physical layout of the SPLICE logic
board. Each of these features are discussed in the
following sections.
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Regardless of the amount of memory used, SPLICE
divides the memory into 4 equal, separate banks.
Each bank may be mapped at non-overlapping starting addresses using the SPLICE, PROM-based monitor or DBG commands. See the GNX Symbolic Debuggers's Reference Manual (Publication No.
42451 0899-001 A) or SPLICE Hardware Reference
Manual for details.
The SPLICE monitor and I/O addressing occupy 256
Kbytes of memory. This block of memory will boot up
at address zero. The user may relocate these 256
Kbytes to any address; if this block of memory is relocated, SPLICE requires 2 Kbytes of the first 64 Kbytes
of RAM for a scratch pad area.
2.2 SERIAL CONNECTORS
SPLICE provides two serial ports (P5 and P6) for connection to a terminal/host. SPLICE also supplies
RS232 cables for connecting SPLICE to the hostlterminal (see Section 3 for connection diagrams). These
ports are jumper configurable for DTE (Data Terminal
Equipment) or DCE (Data Communication Equipment). DSR/DTR or CTS/RTS handshaking may also
be selected.
2.4 MEMORY EXPANSION
1-Mbyte memory expansion boards are available as
an option to the user. SPLICE supports expansion up
to 8 Mbytes, in the following configurations only:
SPLICE with 1 memory board,
with 2 memory boards,
with 4 memory boards,
or with 8 memory boards.
The memory boards connect beneath the SPLICE logic board to a 94-pin connector, P8. When using memory expansion boards, the SPLICE on-board memory
is disabled.
2.3 MEMORY
The SPLICE logic board contains 256 Kbytes of Static
RAM. Each of the 32k x 8-bit memory devices has 150
ns access times. The memory capacity of SPLICE
may be increased by adding 1 MByte memory expansion boards (see Section 2.4). When using memory
expansion boards, the SPLICE on-board RAM is disabled.
------------8.25"------------
000
00
'---'
SERIAL
1/0(2.2)
<
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D
P5
0
PARALLEL
I/o (2.7)
(2.10) [ RESET
Nt.ll
P8 - EXPANSION t.lEt.lORY
(2.4)
P9 Pl0
POWER CONNECTORS
PROt.l BASED t.lONITOR
(2.5)
DIP SWITCH #3
BAUD RATE
SELECTION (2.8)
LEOs
(2.10)
P4
256 KBYTES SRAt.l
(2.3)
TEST POINTS 1-14
(2.9)
P3 Tlt.lING CONTROL
(2.6)
7.0"
TEST POINTS 15-60
(2.9)
P2 NS32382 t.lt.lU
(2.6)
PI CPU CONNECTOR
(2.6)
TL/R/9347-2
Numbers in parenthesis indicate text sections
FIGURE 2. SPLICE Logic Board
6-22
r--------------------------------------------------------------------------,
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2.0 Description of Features (Continued)
2.5 MONITOR
Four EPROMs contain the monitor firmware. When
power is initially applied (cold boot) to SPLICE, the
monitor performs four diagnostic tests. The diagnostics test the ROM, RAM, mapping RAM and UART.
If a failure is detected, a message code will appear on
the LEDs and on the terminal. Refer to the SPLICE
Hardware Reference Manual for explanation of error
codes.
The main function of the monitor is to interpret and
handle commands from the terminal or debugger. The
SPLICE monitor communicates with National's Symbolic Debugger, DBG32. DBG32 resides on a development system host, as part of the GENIXTM Native
and Cross (GNX) Language Tools, Release 2, revision
C, or a subsequent revision of GNX functions with
SPLICE.
Some of the features of DBG32 include:
- Assembly and mixed-language program debugging,
- Symbolics
- Source-level debugging
- Single stepping, breakpoints
- Multimodule program debugging
- Variety of Radixes
- Indirect files and History files
- On-line help facility
Refer to the GNX Symbolic Debugger's Reference
Manual or the GNX datasheet for details.
CPU/MMU CABLES
Depending on the target design, SPLICE requires one
or more of the following cables:
NS32332 CPU cable
NS32032/C032 CPU cable
NS32016/C016/008 CPU cable
NS32CG16 CPU cable
NS32382 MMU cable
Figure 3 shows the basic layout of the flex cable.
60140 PIN SPLICE
CONNECTOR
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DEVICE CONNECTOR
TLlR/9347-3
Top View
FIGURE 3. Flexible Printed Circuit Cable
The "device connector" is inserted into the user's target socket, replacing the user's device. The user's device plugs into the "device socket." At the opposite
end of the flex cable is a 60 pin connector for CPUs,
or a 40 pin connector for the NS32382 MMU. These
are installed on P1 and P2, respectively, on SPLICE.
Targets using the NS32082 MMU do not require a cable.
Refer to the Hardware Reference Manual for more
details on the wiring, installation, and handling of cables.
TIMING CONTROL CABLE
The timing control cable is a twisted pair cable consisting of 26 flying leads. The following table lists the
signals, pin numbers, and functional decription of
each signal. This cable connects to P3 on SPLICE.
Section 3.2 describes how to connect this cable to the
target.
2.6 CABLE DESCRIPTION
Two different cables are supplied to connect SPLICE
with the target hardware: flexible printed circuit cable
for CPU/MMU signals and a twisted pair, flying lead
cable for timing control signals. Both types of cables
are detailed in the following text.
6-23
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2.0 Description of Features (Continued)
Signal
Pin
I/O
Functional Description
PAV
1
I
CTTL
082RDYIN
3
5
I
I
082RDOUT
7
0
RSTIN
RSTOUT
9
11
0
BDEN
13
0
BDEN
BBDEN
BBDEN
INT
15
17
19
21
0
0
0
0
DACK
23
0
TRIG1
25
0
TRIG2
26
0
Used to latch the address information from the CPU's AD bus when the NS32082
MMU is installed. NOTE: When the NS32382 MMU is used, the MMU's PAV pin is
connected to SPLICE via the 382 MMU cable, and it is not necessary to connect this
signal.
A TTL compatible version of the PHI1 clock signal.
When installing SPLICE, the signal that normally is connected to the ready input of
the 082 MMU should be disconnected and connected to the SPLICE via P3-5.
The output generated from SPLICE, after receiving the 082 ready input and ANDing it
with SPLICE's ready signal, is connected to the ready input of the 082 MMU.
A Schmitt triggered input connected to the reset circuitry of the target system.
An active low, CMOS level synchronous reset output generated by ANDing the
RSTIN signal with the SPLICE's reset circuitry output. The RSTOUT signal should be
used to reset the target's circuitry.
Active high Board Enable output. When asserted, the SPLICE ROM/IO or RAM is
accessed. This Signal is connected to the user's target to disable the buffers and
drivers of the CPU's address/data bus.
Complementary output of BDEN.
CMOS level version of BDEN.
Complementary output of BBDEN.
A CMOS level output generated by the DUART asserted whenever the DUART is
ready to transmit or receive.
An open-collector signal driven low when BDEN is asserted and SPLICE's data
buffers are enabled.
A TTL level output signal driven by the DUART's output port bit 2 on SPLICE. The
user may program the state of this output using a special supervisory call.
Like TRIG1, this is a TTL output signal driven by the DUART's output port 3 on
SPLICE. The SPLICE monitor will drive this bit low during the monitor mode and set
when running the user program.
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2.7 PARALLEL 1/0 INTERFACE
2.10 INDICATORS AND PUSH BUTTONS
P4 has been reserved for a future high speed download connection.
SPLICE uses 4 LEDs to indicate failures during poweron diagnostics. The programmer may also use these
as general purpose indicators.
Two push buttons are on the SPLICE logic board: NMI
and RESET. The reset circuit is jumper configurable to
originate from SPLICE reset or the target reset.
2.8 PROGRAMMABLE BAUD RATES
Various baud rates can be selected by setting positions 1, 2 and 3 of DIP switch 3 as follows:
Baud Rate
SW3-1
SW3-2
SW3-3
19200
9600
4800
2400
1800
1200
600
300
on
off
on
off
on
off
on
off
on
on
off
off
on
on
off
off
on
on
on
on
off
off
off
off
2.11 OPERATING SPEEDS
SPLICE operates at up to 15 MHz. When operating
from target memory, full speed operation may be
achieved. However, when accesses are made to
SPLICE memory or the UART, wait states are required. The following is a table of required wait states:
2.9 TEST POINTS
SPLICE has 60 test points which allow the user to
trace, using a logic analyzer, the CPU's bus activity.
Test Points
Signals
1-14
15-46
47-60
P3-Timing Control Signals
AD Bus Signals
Control Signals from CPU
6-24
ROM/UART
RAM
FREQ.(MHz)
1
2
3
0
1
1
6
10
15
(J)
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3.0 Required Operating Environment
3.2 SPLICE/TARGET INTERFACE
In addition to the logic board and CPU/MMU cables,
SPLICE requires the following equipment:
- A regulated + 5 VDC power supply capable of supplying a 4A minimum
- A host computer system with NSC's GENIX Native
and Cross (GNX) Development Tools, Release 2,
revision C or later
- An RS232 compatible terminal
The following sections describe how to connect
SPLICE to the user's target and host.
SPLICE connects to the user target through P1, P3,
and if the NS32382 MMU is used, P2. P1 connects to
the CPU cable which is, in turn, connected to the target CPU socket. P2 connects to the NS32382 MMU
cable. P3 connects to the timing control cable. A minimum of five timing control signals must be connected
to operate with SPLICE: CTIL, RSTIN, RSTOUT,
BDEN, and PAV. SPLICE taps onto CTIL and PAV
directly. RSTIN and RSTOUT will require the designer
to disconnect the target reset circuitry and route it
through SPLICE. BDEN is the most important signal.
An extra OR gate (see Figure 68, G1) is required to
OR the target board enable with the SPLICE board
enable. ORing these signals together prevents bus
collisions. The target board enable is taken from the
CPU data buffers; the SPLICE board enable is P3-13,
-14, -15, or -16 of the timing control cable.
IMPORTANT: The target's CPU data buffers must be
disabled to operate with SPLICE.
Other signals may be required, depending on the target design. (Refer to Section 2.6 for details on other
timing control cable signals.) When designing a board
for use with SPLICE, the designer should allow easy
access to these signals.
Figure 6 illustrates how to connect the timing control
cable to a typical NS32016 target. Figure 6A shows a
typical circuit, and Figure 68 shows the target connected to SPLICE.
3.1 SPLICE/HOST INTERFACE
SPLICE connects to the development host through
RS232 cable(s). The monitor on SPLICE will interface
with any host that has a DBG32. DBG32 is a symbolic
debugger available in the GENIX Native and Cross
Support (GNX) Development Tools software package.
The SPLICE monitor functions with GNX Tools R2 rev.
C or later.
SPLICE can be connected to the host in one of two
ways: Stand-aside mode or Transparent mode. Standaside mode is used when only one serial port is available from the host for SPLICE operation (Figure 4).
Stand-aside mode is also convenient when SPLICE
needs to be shared by different users.
4.0 Specifications/Characteristics
Environment
SPLICE is designed to operate in a laboratory environment. Sufficient air flow must be allowed to ensure all
components stay within their specified temperature
range.
Temperature: Operative O°C to 55°C
Non-operative - 40°C to + 60°C
Humidity
10% to 90% relative, non-condensing
Altitude
Operative 15,000 feet
TL/R/9347-4
FIGURE 4. Stand-Aside Mode
Transparent mode is useful for remote hosts. Transparent mode uses both serial ports (P5 and P6), as
shown in Figure 5.
Power Requirements
SPLICE requires a regulated + 5 VDC power source
capable of supplying a 4A minimum. SPLICE has a
DC-DC converter which generates the + 12 VDC and
- 12 VDC required by the RS232 interface drivers.
DC Characteristics
Table 1 lists the DC characteristics for the logic circuits on SPLICE.
AC Characteristics
TL/R/9347 -5
Table 2 lists the AC characteristics for the signals of
the SPLICE circuits. Figure 1 illustrates SPLICE access timing, RDY circuit timing, READ timing, NMI timing, and BACKOUT timing.
FIGURE 5. Transparent Mode
6-25
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4.0 Specifications/Characteristics (Continued)
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TABLE 1. DC Characteristics of I/O Signals
Signal
Max Input
Current (~A)
Min Output
Current (mA)
Max Input
Cap. (pF)
IIH
IlL
IOH
IOL
ADO-AD16
25
105
6.0
6.0
30
AD16-AD31
50
755
6.0
6.0
35
PAO-PA15
20
100
PA16-PA31
45
750
-
-
10
5
PDO-PD7
50
500
15.0
64.0
5
ADSPAV
20
500
80
20
2000
500
-
5
CTTL (1)
(2)
-
RSTIN
20
600
BWOBW1
20
600
BE1 BE2
BE3 HBE
50
700
FLT
25
250
-
DDIN
1
1
BACKIN
20
500
NMIN
25
-
-
20
5
5
5
-
5
-
-
10
-
-
5
250
5
5
MATNSATN
50
400
15.0
64.0
5
MACK SACK
50
400
15.0
64.0
5
RDYOUT
-
-
2.0
20.0
2.0
20.0
-
-
-
6.0
6.0
2.0
20.0
-
-
1.0
20.0
6.0
6.0
-
-
-
0.4
2.4
-
0.4
2.4
-
-
-
2.0
20.0
-
2.0
20.0
-
-
6.0
6.0
6.0
6.0
-
30.0
64.0
5
-
30.0
64.0
5
082RDYOUT
RSTOUT
BACKOUT
NMIOUT
INT
TRIG1
TRIG2
BDEN
BDEN
BBDEN
BBDEN
PDIR
PRESET
-
NOTE: (1) When W6 A-8 Is connected.
(2) When W6 8-C is connected.
6·26
-
,--------------------------------------------------------------------------, 0
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r(;
4.0 Specifications/Characteristics (Continued)
m
TABLE 2. AC Characteristics of SPLICE
Name
tcp
Figure Description
7A
Clock Period
C
Ref/Conditions
Min
Rising Edge CTTL to Next
Rising Edge CTTL
50.0
Typ
Max
Units
~
ns
"'CI
-
3(I)
tSDENAVa
7A
BDEN Active (High)
After Address Valid
27.0
33.5
ns
tSDENa
7A
BDEN Active (High)
After ADS or PAV Active (Low)
34.0
44.0
ns
lSDENa
7A
BDEN Active (Low)
After BDEN Active (High)
6.0
8.0
ns
tSSDENa
7A
BBDEN Active (High)
After BDEN Active (High)
15.0
25.0
ns
lSSDENa
7A
BBDEN Active (Low)
After BDEN Active (High)
21.0
33.0
ns
tRDYia
7A
RDYOUT Inactive (Low)
After BDEN Active (High)
8.0
10.5
ns
t332RDYa
7B
RDYOUT Active (High)
for 32332
After Rising Edge CTTL
9.0 11.8*
12.5 16.8*'
ns
tRDYa
7B
RDYOUT Active (High)
for 32008/016/032
After Rising Edge CTTL
7.5 10.5*'
11.0 15.5"
ns
tAADS n
7A
Address Bits 0-31 Hold From After ADS Inactive (High)
tRAMr
70
RAM Data Valid
After Address Valid
246
ns
tpROM r
70
PROM Data Valid
After Address Valid
348
ns
lDACKa
7B
DACK Active (Low)
After Rising Edge CTTL
19.0
27.0
ns
tNMi
7C
NMIOUT Active/Inactive
After Rising Edge CTTL
15.0
25.0
ns
lSACKOUTa
7E
BACKOUT Active (Low)
After BACKIN Active (Low)
2.0
5.8
ns
tSACKOUTia
7E
BACKOUT Inactive (High)
After BACKIN Inactive (High)
1.0
5.8
ns
'W8 A-8 connected
"W8 8-C connected
6-27
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4.5
ns
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4.0 Specifications/Characteristics (Continued)
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TO OE OF
DATA
BUFFERS
P
NS32016
CPU
28
ROY
NS32082
MMU
ROY
TARGET
CLOCK
RST
PAY 44
13
-
DBE 1
ABT
ABT
CLEAR
134
-[] 0 1
34
RSTI
~
1
ROY 9
ADS 6
RSTO 8
TL/R/9347-6
FIGURE 6A. Typical Circuitry for a NS32016 Target
TARGET
TO OE OF
DATA
BUFFERS
NS32D16
CPU
28
ROY
NS32082
MMU
28
ROY
CLOCK
RST
NS32201
TCU
16 CTTL
PAY 44
ABT
34
CLEAR
34
P3-3
P3-S
CTTL
082 RDYIN
P3-11
082 RDYOUT
RSTOUT
1
SPLICE
CONNECTIONS
- - - - - - ORIGINAL WIRING, CUT FOR SPLICE
TL/R/9347 -7
FIGURE 6B. Modified NS32016 Target, with SPLICE Connections
6·28
,--------------------------------------------------------------------------, W
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r4.0 Specifications/Characteristics (Continued)
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--+"I--","--..n ..- - - -
2.
BDEN
BBDEN
----+-.......
RDYOUT
"----illr------
TL/R/9347-8
FIGURE 7A. SPLICE Access Timing
.
ADS ar PAY
ri-------4
BDEN _ _ _.......
'H--+-----•
.
.......- - - i 'H--+--_..I
.... r-tRDYa
RDYOUT - - - - . . . .
_
(32008/016/032)
......--~l
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H-J
RDYOUT(32332) - - - . . . . . . ,
TUR/9347-9
FIGURE 7B. ROY Circuil Timing
6-29
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4.0 Specifications/Characteristics (Continued)
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~S
TUR/9347-10
FIGURE 7C. NMI Timing
-ADSorPAV
- ---,L.Jr--------i S
S1-S----
ADO-AD31~ So~~
I.VALID t RAM v
DATA VALID
_
tpROMv
TL/R/9347-11
FIGURE 70. READ Timing
TUR/9347-12
FIGURE 7E. Timing of BACKOUT when SPLICE is not Accessed
6-30
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5.0 Ordering Information
SPLICE Logic Boards:
Note: Memory expansion boards disable 256 Kbytes of memory on the
logic board. Users whose applications require more than 256
Kbytes of memory should order part number NSV·SPLlCE·1 MS.
This configuration ships without the 256 Kbytes of SRAM on the
logic board and with a 1·Mbyte expansion board.
NSV-SPLlCE-256
SPLICE logic board and 256
Kbytes of on-board memory.
NSV-SPLlCE-1 MB
SPLICE logic board with 1Mbyte memory expansion board
instead of 256 Kbytes of onboard memory.
SPLICE logic boards ship with the following:
SPLICE logic board
2 RS232 connectors
2 female-to-female connectors
Power supply cable
Timing control cable and clips
Stand ofts
SPLICE User's Manual
SPLICE schematics
ACCESSORIES
NSV-SPLC-MEM-BD 1-Mbyte expansion memory
board
SPLICE cable for the NS320161
NSV-SPLCBL-016
C016/008 CPU
NSV-SPLCBL-032
SPLICE cable for the NS320321
C032 CPU
NSV-SPLCBL-CG16 SPLICE
cable
for
the
NS32CG16 CPU
NSV-SPLCBL-332
SPLICE cable for the NS32332
CPU
NSV-SPLCBL-382
SPLICE cable for the NS32382
MMU
Note: The part numbers are the same for NS32016 and NS3200B CPU
cables since both parts have the same pinouts.
6-31
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Section 7
Software Support
Section 7 Contents
Series 32000 GENIX Native and Cross-Support (GNX) Language Tools (Release 2) . .. . .. .. .
Series 32000 Ada Cross-Development System for SYS32/20 Host. .. .. .. . . .. .. . .. . . .. .. .
Series 32000 Ada Cross-Development System for VAXIVMS Host. . . . . . . . . . . . . . . . . . . . . . . .
GENIX V.3 Operating System........................................................
Series 32000 Real-Time Software Components VRTX, lOX, FMX and TRACER. . . . . . . . . . . . .
Series 32000 EXEC ROMabie Real-Time Multitasking Executive. . . .. .. ... .. . .. .. . .. .. ....
7-2
7-3
7-7
7-11
7-16
7-19
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III Available in binary for the VAXTM UNIX®
Implements AT&T's standard Common
Object File Format (COFF)
Optimizing C Compiler (optional)
Optimizing FORTRAN 77 Compiler
(optional)
Pascal Compiler (optional)
Series 32000 assembler and linker
In-System Emulator Support
Interactive remote debugger with helpful
command interface
4.3 bsd operating system under
derivatives of the Berkeley operating
system
li!I Available in binary for the VAX/VMSTM
operating system
1.1 Available in binary on National
Semiconductor Series 32000 Systems
III Available in source for porting to other
operating system environments
Product Overview
propriate command-line arguments and when linked
with appropriate libraries, code generated by the GNX
language tools can be executed in any Series 32000
target environment. In addition, these tools can be
used to develop operating-system-independent code
or code designed to run in conjunction with real-time
kernels, such as National's EXEG and VRTX®/Series
32000. All of National's new language tools conform
to the GOFF file format, thereby ensuring that modules produced by anyone set of tools can be linked
with objects produced by any other set of GNX tools.
The Series 32000 GNX Language Tools are a set of
software development tools for the Series 32000 microprocessor family. Optional high-level language
compilers work in conjunction with the standard components to provide tools that can be combined to
meet a variety of development needs.
GENIX Native and Cross-Support (GNX)
Language Tools
The Series 32000 GNX Language Tools are based on
AT&T's Gommon Object File Format (GOFF). With ap-
7-3
•
Standard Components
nasm
an assembler for GNX assembly language source code (produced either
by a high-level language compiler or
by an assembly language programmer) and produces an object file;
supports NS32332 configuration
register and 32-bit addressing; also
supports NS32381, NS32382 chips;
nmeld
a linker that resolves references between object files and library routines and assigns relocated addresses to produce Series 32000
executable code;
nar
an archiver used to store frequently
referenced objects in a library for
convenient retrieval by the linker;
nlorder
finds ordering relation for an object
library;
libm.a
a library that includes math routines
that can be called from code written
in assembly or high level languages.
This library includes Bessel functions, exp, log, log10, pow, sqrt,
floor, ceil, fmod, fabs, gamma, hypot, sinh, cosh, tanh, sin, cos, tan,
asin, acos, atan, and atan2;
idbg16, idbg32 debuggers for use with National's
ISE16TM and ISE32™, respectively;
debuggers for downloading and dedbg16
bugging code on boards that use the
NS32008, NS32016, NS32032, or
NS32332 CPU and associated monitors.
mon16, mon32, monitors for use with OB32016,
mon332,
OB32000, OB32332, and OB32332
mon3328
plus Oevelopment Boards. Provided
in PROMs and in assembly language source so the user can modify and install the monitor on user-designed Series 32000 hardware.
nburn
a PROM-programming utility that
converts a COFF object file into ASCII hex, Intel hex, or Motorola S-record format output file. Suitable for
driving a OATA 1/0 Model 19
PROM-programming.
db library
development board support routines, such as string, scanf, printf,
atof, abs, regex, getc, putc, and
puts; to be used with the development board monitor;
A library of terminal 1/0 functions is also provided.
These functions can be called by user-developed
code· to allow a program running on a development
board to print data to and accept data from the console terminal. Source to these routines is provided,
should the user elect to expand or modify the functionality of these routines. In addition, functions from
the C library, "libc.a", that do not rely on the kernel for
execution, are included.
cvtasm
utility to assist in converting previous
assembler syntaxes to GNX assembler syntax;
nsize
a utility for displaying the size of the
text, uninitialized data, and initialized
data segments of an object file;
nstrip
a utility to remove symbol table information from an object file;
nnm
a utility to display the symbol table of
an object file.
The following two programs are available for configurations designed for operation on a VAX under derivatives of the Berkeley UNIX 4.3 bsd operating system.
ddt
a debugger specifically designed for
kernel debugging;
dbmon
a monitor for use with ddt provided
on PROM and in assembly language
source so the user can modify and
install the monitor on user-built Series 32000 hardware.
Optional Components
Optimizing C Compiler
The Optimizing C Compiler is derived from the UNIX C
Compiler and supports the C language as defined by
Kernighan and Ritchie. Enhancements include passing structures as arguments to functions, long variable
names, single-precision floating constants, signed and
unsigned bitfields. The compiler generates Series
32000 assembly code which is passed to the GNX
assembler.
The optimizer and code generator use state-of-the-art
optimization techniques to process C code into assembly statements that approach hand-optimized assembly code in execution speed. Optimization techniques include register allocation by coloring, constant
folding, subexpression and assignment elimination,
copy propagation, peephole optimizations, and others.
Optimizer processing can be controlled with switches
to request optimization for space instead of speed,
perform partial optimizations, specify addressing
7-4
Optional Components (Continued)
Source Products
modes and influence allocation of variables to registers.
Code can be compiled with optimization disabled in
order to generate debuggable code.
C object modules can be linked with assembly, Pascal
and FORTRAN 77 object modules for mixed-language
development.
The assembler, associated tools, and the optional C,
Pascal, and FORTRAN 77 Compilers are provided in
binary form for use on a VAX under the 4.2 bsd operating system. The source to all programs that make up
the Series 32000 GNX Language Tools is available for
porting to other UNIX operating system environments.
Pascal Compiler
National Semiconductor offers a full 90 day warranty
period. Extended warranty provisions can be arranged
by calling MCS Logistics at the toll-free numbers listed
below.
The MCS Service Technical Support Engineering Center has highly trained technical specialists available to
assist customers over the telephone with any product
related technical problems.
for more information, please call:
(800) 538-1866,
(800) 672-1811 for California,
(800) 223-3248 for Canada.
Customer Support
The Pascal compiler is an ISO-standard Pascal compiler derived from the 4.2 bsd "pc" compiler.
The Pascal compiler supports several extensions to
the standard Pascal language that are designed to
simplify program development, such as separate compilation of individual modules. In addition, I/O of enumerated types, output of octal and hexadecimal numbers, and comparison of strings of unequal length are
supported. The Pascal library, "libpc.a", includes several useful procedures and functions, for example, a
random number generator, file manipulation procedures, and clock functions.
Pascal object modules can be linked with assembly,
C, and FORTRAN 77 object modules for mixed-language development. Pascal programs can call the terminal I/O functions described for the C Compiler.
Licensing
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All binary versions of the Series 32000 GNX Language Tools require the execution of National's Binary
User Agreement. Because the language tools include
AT&T proprietary code, a System V source license is
a prerequisite for obtaining source versions of these
language tools.
Optimizing FORTRAN 77 Compiler
The Optimizing FORTRAN 77 Compiler is derived
from the UNIX System V Release 2 "f77" Compiler.
Enhancements include double-complex data types,
recursion, hex constants, one-trip do loop option,
short integers and bitwise Boolean operations.
The compiler generates Series 32000 assembly code
which is passed to the GNX assembler.
The optimizer and code generator use state-of-the-art
optimization techniques to process FORTRAN code
into assembly statements that approach hand-optimized assembly code in execution speed. Optimization techniques include register allocation by coloring,
constant folding, subexpression and assignment elimination, copy propagation, peephole optimizations and
others.
Optimizer processing can be controlled with switches
to request optimization for space instead of speed,
perform partial optimizations, specify addressing
modes and influence allocation of variables to registers.
Code can be compiled with optimization disabled in
order to generate debuggable code.
FORTRAN object modules can be linked with assembly, Pascal, and C object modules for mixed-language
development.
Part Numbers
Binaries for Cross-Support Mode hosted on VAX
under 4.2 bsd:
NSW-ASM-BRVX The assembler ("nasm"), linker
("nmeld"), math library ("libm.a"),
archiver ("nar"), ISE debugger
("idbg16/32") development-board
-support library, development board
debuggers ("ddt" and "dbg16"),
monitors in source ("dbmon" and
"mon16/32"), monitors in PROM,
the PROM-burning utility ("nburn"),
dblibrary, cvtasm, nsize, nstrip, and
nnm.
NSW-C-BRVX
Optional C compiler to be used in
conjunction with NSW-ASM-BRVX
described above.
NSW-F77-BRVX Optional FORTRAN 77 Compiler to
be used in conjunction with NSWASM-BRVX described above.
NSW-PAS-BRVX Optional Pascal Compiler to be
used in conjunction with NSWASM-BRVX described above.
All binaries for VAX/4.2 bsd are delivered on 9-track
reel tape in "tar" format.
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Binaries for Cross-Support Mode hosted on VAX
under VMS:
NSW-ASM-BRVM The assembler ("nasm"), linker
("nmeld"), math library ("libm.a"),
archiver ("nar"), ISE debugger
development("idbg16/32")
board-support library, development board debugger ("dbg16"),
monitor in source ("mon16/32"),
monitor in PROM, the PROMburning utility ("nburn"), dblibrary,
cvtasm, nsize, nstrip, and nnm.
NSW-C-BRVM
Optional C Compiler to be used in
conjunction
with
NSW-ASMBRVM described above.
NSW-F77-BRVM Optional FORTRAN 77 Compiler
to be used in conjunction with
NSW-ASM-BRVM
described
above.
NSW-PAS-BRVM Optional Pascal Compiler to be
used in conjunction with NSWASM-BRVM described above.
All binaries for VAXIVMS are delivered on 9-track reel
tape in VMS BACKUP format.
Source
NSW-ASM-SRNN
The source to NSW-ASM-BRVX,
as described above.
NSW-C-SRNN
The source to NSW-C-BRVX, as
described above.
NSW-PAS-SRNN The source to NSW-PAS-BRVX,
as described above.
NSW-F77-SRNN
The source to NSW-F77-BRVX,
as described above.
All source tapes are delivered on 9-track reel tape
written in "tar" format.
For future product releases contact your National
Semiconductor sales representative or call Series
32000 Software Marketing at (408) 721-5551.
Manuals
Each software package is delivered with one copy of
each appropriate manual.
NSP-ASM-M-MS: Manual Set included with NSWASM-BRVM
NSP-ASM-X-MS: Manual Set included with NSWASM-BRVX
NSP-C-M:
Manual included with NSW-CBRVM and NSW-C-BRVX
NSP-PASCAL-M: Manual included with NSW-PASCAL-BRVM and NSW-C-BRVX
NSP-F77-M:
Manual included with NSW-F77BRVM and NSW-F77-BRVX
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Binaries hosted on SYS32/20 under System V:
NSW-C-BLAF
Optional C Compiler to be used in
conjunction with NSW-ASM-BLAF
described above.
NSW-F77-BLAF Optional FORTRAN 77 Compiler
to be used in conjunction with
NSW-ASM-BLAF
described
above.
NSW-PAS-BLAF Optional Pascal Compiler to be
used in conjunction with NSWASM-BLAF described above.
Above binaries for SYS32/20 are delivered on lowdensity (360 kbyte) 5% inch PC-DOS floppy disks in
MS-DOS format.
7-6
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Derived from the VERDIXTM Ada
Development System (VADSTM)
Compiler support for Ada Pragmas and
Representation Attributes
Comprehensive Support Services
available from National
•
•
•
•
•
•
•
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Generates GNXTM Common Object File
Format (COFF)
Debugging Tools
Program Generation Utilities
SPLICE support
Extensive Ada Library Management
Utilities
Run-time system to support bare-board
environment
Ada VRTX® Interface Package (Optional)
Source to Ada Run-Time System
(Optional)
Product Overview
The Series 32000 Ada cross-compiler supports full
Ada language program development on National's
SYS32/20 host and is part of National's Validated
Ada Development Environment (NVADE). NVADE
provides a high performance Ada compiler that supports all required features of the Ada language and is
fully compliant with ANSI/MIL-STD-1B15A. NVADE
also provides a comprehensive set of tools specifically tailored to provide the optimum Ada Programming
Support Environment (APSE) for a host of application
development.
7-7
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The SYS32/20 Development system includes a highperformance add-in card that converts an IBM-PCI AT
or compatible system into a Series 32000-based development environment.
Once compiled, the Ada program will execute on either a Series 32000 development board or a customer
target board. This "production quality" Ada compiler
focuses on high performance, and is intended for
large-scale development of real-time, embedded control, or training simulator software applications. The
Series 32000 Ada Cross-Development System includes the Ada compiler, program library utilities, program generation utilities, library management and a
complete run-time system. This product directly inter-
c
faces with GNX language tools provided with the
SYS32/20 system, including GNX linker, DBG and
IDBG debuggers, library management tools and other
utility programs.
The Series 32000 Ada Cross-Development System
has been engineered and designed to run under
OPUS5, the SYS32/20 Operating System derived
from AT&T's UNIXTM System V. Therefore, rather
than learning a new operating system, the programmer can immediately concentrate on Ada program development. To aid the user, complete on-line manual
entries are provided. These can be configured to use
either the UNIX man utility or a separate interactive
help command, supplied with the product.
Series 32000 Ada Cross-Development System for SYS32/20 Host
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NVADE Components
Ada Compiler
In addition, the Series 32000 Ada Cross-Development
System permits Ada Program Libraries to be hierarchically organized, so that units not local to one library
can be found in other libraries. Thus, programmers
can work without interference on local versions of individual program units, while retrieving the remainder of
the program from higher-level libraries.
NVADE also uses DIANA (Descriptive Intermediate
Attributed Notation for Ada), which generates an intermediated representation for each unit. DIANA provides a tree-structured representation of an Ada program encoding the complete syntactic and semantic
information of each individual Ada unit. The presence
of DIANA as an integrated mechanism makes possible powerful editing, debugging and program query facilities, thus providing the means for simple and efficient incremental compilation.
The Ada Compiler accepts as input Ada source and
generates Series 32000 code that can be downloaded
to, and executed on, a Series 32000-based target development board.
The Series 32000 Ada Compiler supports the full Ada
language. Features include shared or unshared generics, separates, in-lines, bit representation, machinecode insertion, monitor tasks and terminal I/O. The
compiler generates GNX COFF (Common Object File
Format) object files that can be linked with object files
generated by other GNX compilers. The Ada compiler
performs several optimizations, including value-tracking global register allocation, register assignment for
commons and locals, common sub-expression removal, branch and dead code analysis, some constraint
check removal, and local peephole optimizations. The
Ada compiler operates as a re-entrant shareable process in the SYS32/20 host system, allowing the compiler to make full use of most operating system facilities.
In addition, the Ada compiler provides features to aid
in the development of real-time, embedded control
and training simulator software applications. Some of
these include Ada Pragmas as specified in Chapter 13
of the Ada Language Reference Manual (LRM), such
as: Inline, Interface, Interface_Object, Pack, Page,
Priority, Share_Body, and Suppress. Also included is
a Machine Code Package which provides an interface
for handling machine code insertion and generics (Unchecked_Dealiocation and Unchecked_Conversion)
for controlling storage and type conversions.
Debuggers
The standard GNX debugger, DBG32, is used with the
Series 32000 Ada Cross-Development System.
DBG32 can be used to debug code on the SYS32/20
host and/or to download and remotely debug or execute code on a Series 32000 development board.
DBG32 supports the use of National's SPLICE software debugging tool. Machine-level debug support is
provided by the debugger.
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Ada object files are linked by the standard GNX linker,
which is called by the Ada compiler pre-linker. The
GNX linker resolves references between object files
and library routines and assigns relocated addresses
to produce Series 32000 executable code.
Program Generation Utilities
Ada Run-Time System
An Ada make utility, similar in operation to that found
in the UNIX operating system, is provided to simplify
program compilation by maintaining program unit dependancy information. This utility determines which
files must be recompiled to produce a current executable file. This utility can also be used to ensure that
the named unit is up-to-date, recompiling dependencies as necessary. Also provided is a source code formatter, easily configurable for individual Ada coding
standards.
The Series 32000 Ada Run-time System provides
comprehensive support for tasking, debugging, exception handling and input/output.
The Run-time System is linked with the user's generated Ada program. To facilitate resource utilization efficiency, major portions of the Run-time System have
been optimized. Run-time source for customization is
also available.
Ada-VRTX Interface Package (Optional)
The Ada Run-time System includes a large, rich, and
elegant tasking system. VRTX (the Versatile RealTime Executive) provides a small, simple, compact
and fast tasking system and may be a preferred alternative to using the Ada Run-time System, particularly
for embedded microprocessor applications where
space and timing are critical. The Ada-VRTX interface
package (AVIP) offers Ada language users a convenient means of interfacing with VRTX. AVIP allows
Ada programmers the ability to call any VRTX service
from their Ada program. (The exceptions are
Program Library Utilities
The Ada language imposes stringent requirements on
an Ada Program Library. While the language provides
for separate compilation of program units, each unit is
compiled in the "context" of previously compiled
units. The compiler must have access to this context,
and the context must be carefully organized in the
form of a Program Library. This library has been designed to enhance the compiler performance. A set of
utilities is provided to manage, manipulate, and display Program Library information.
7-9
•
Program Library Utilities (Continued)
Series 32000 Ada Cross-Development System for SYS32/20 Host
NVADE Modules and Run-Time Environment
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Systems and future revisions of VMS
Derived from the VERDIXTM Ada
Development System (VADSTM)
Compiler Support for Ada Pragmas and
Representation Attributes
Comprehensive Support Services
available from National
•
•
••
•
Generates GNXTM Common Object File
Format (COFF)
Program Generation Utilities
SPLICE support
Extensive Ada Library Management
Utilities
Run-time system to support bare-board
environment
Debugging Tools
Ada VRTX® Interface Package (Optional)
Source to Ada Run-Time System
(Optional)
Product Overview
The Series 32000 Ada cross-compiler supports full
Ada language program development on Digital Equipment Corporation's VAXIVMS hosts and is part of National's Validated Ada Development Environment
(NVADE). NVADE provides a high performance Ada
compiler that supports all required features of the Ada
language and is fully compliant with ANSI/
MIL-STD-1815A. NVADE also provides a comprehensive set of tools specifically tailored to provide the optimum Ada Programming Support Environment
(APSE) for host application development.
7-11
,.
Product Overview (Continued)
Once compiled, the Ada program will execute on either a Series 32000 development board or a customer
target board. This "production quality" Ada compiler
focuses on high performance, and is intended for
large-scale development of Series 32000 real-time,
embedded control, or training simulator software applications. The VAXIVMS Ada Cross-Development
System includes the Ada compiler, program library
utilities, program generation utilities, library management utilities and a complete run-time system. This
product directly interfaces with VAXIVMS GNX language tools provided, including GNX linker, DBG and
IDBG de buggers, library management tools and other
utility programs.
The VAXIVMS Ada Cross-Development System has
been engineered and designed to run under VAX!
VMS 4.4 or later Operating Systems. Therefore, rather
than learning a new operating system, the programmer can immediately concentrate on Ada program development.
Series 32000 Ada Cross-Development System for VAX/VMS Host
VAX/VMS
Host
DEBUGGING
TOOLS
TLlGG/9364-2
7-12
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NVADE Components
Ada Compiler
Program Library Utilities
The Ada Compiler accepts as input Ada source and
generates Series 32000 code that can be downloaded
to, and executed on, a Series 32000-based target development board.
The Series 32000 Ada Compiler supports the full Ada
language. Features include shared or unshared generics, separates, in-lines, bit representation, machinecode insertion, interrupt tasks, monitor tasks and
terminal I/O. The compiler generates GNX COFF
(Common Object File Format) object files that can be
linked with object files generated by other GNX compilers. The Ada compiler performs several optimizations, including value-tracking global register allocation, register assignment for commons and locals,
common sub-expression removal, branch and dead
code analysis, some constraint check removal, and
local peephole optimizations. The Ada compiler operates as a re-entrant shareable process in the VAX/
VMS host system, allowing the compiler to make full
use of most operating system facilities.
In addition, the Ada compiler provides features to aid
in the development of real-time, embedded control,
and training simulator software applications. Some of
these include Ada Pragmas as specified in Chapter 13
of the Ada Language Reference Manual (LRM), such
as: Inline, Interface, Interface_Object, Pack, Page,
Priority, Share_Body and Suppress. Also included is
a Machine Code Package which provides an interface
for handling machine code insertion and generics (Unchecked_Dealiocation and Unchecked_Conversion)
for controlling storage and type conversions.
The Ada Language imposes stringent requirements on
an Ada Program Library. While the language provides
for separate compilation of program units, each unit is
compiled in the "context" of previously compiled
units. The compiler must have access to this context,
and the context must be carefully organized in the
form of a Program Library. This library has been designed to enhance the compiler performance. A set of
utilities is provided to manage, manipulate, and display Program Library information.
In addition, the Series 32000 Ada Cross-Development
System permits Ada Program Libraries to be hierarchically organized, so that units not local to one library
can be found in other libraries. Thus, programmers
can work without interference on local versions of individual program units, while retrieving the remainder of
the program from higher-level libraries.
NVADE also uses DIANA (Descriptive Intermediate
Attributed Notation for Ada), which generates an intermediated representation for each unit. DIANA provides a tree-structured representation of an Ada program encoding the complete syntactic and semantic
information of each individual Ada unit. The presence
of DIANA as an integrated mechanism makes possible powerful editing, debugging and program query facilities, thus providing the means for simple and efficient incremental compilation.
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The standard GNX debugger, DBG32, is used with the
Series 32000 Ada Cross-Development System.
DBG32 can be used to debug code on the VAX host
and/or to download and remotely debug or execute
code on Series 32000 development board. DBG32
supports the use of National's SPLICE software debugging tool. Full machine-level debug support is provided by the debugger.
Program Generation Utilities
An Ada make utility, similar in operation to that found
in the UNIX® operating system, is provided to simplify
program compilation by maintaining program unit dependency information. This utility determines which
files must be recompiled to produce a current executable file. This utility can also be used to ensure that
the named unit is up-to-date, recompiling dependencies as necessary. Also provided is a source code formatter, easily configurable for individual Ada coding
standards.
Linker
Ada object files are linked with the standard GNX linker, which is called by the Ada compiler pre-linker. The
GNX linker resolves references between object files
and library routines and assigns relocated addresses
to produce Series 32000 executable code .
•
7-13
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NVADE Modules and Run-Time Environment
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Ada Run-Time System
nient means of interface with VRTX. AVIP allows Ada
programmers the ability to call any VRTX service from
their Ada program. (The only exceptions are the calls
provided for user-defined interrupt handlers and for
partition create and extend.) The actual operations
performed by VRTX are identical in both assembly
language and Ada. Thus, this package gives users
both the elegant features of the Ada language and
VRTX's unique tasking system.
The Series 32000 Ada Run-Time System provides
comprehensive support for tasking, debugging, exception handling and input/output.
The Run-Time System is linked with the user's generated Ada program. To facilitate resource utilization efficiency, major portions of the Run-Time System have
been optimized. Run-Time source code for customization is also available.
Ada-VRTX Interface Package (Optional)
PRE-REQUISITES
The Ada Run-Time System consists of a large, rich
and elegant tasking system. VRTX (the Versatile RealTime Executive) provides a small, simple, compact
and fast tasking system and may be a preferred alternative to using the Ada Run-Time System, particulary
for embedded microprocessor applications where
space and timing are critical. This Ada-VRTX interface
package (AVIP) offers Ada language users a conve-
-
VAXIVMS Host Computer 750-89XX
VMS Operating System
VAXIVMS GNX Assembler Package
Supported Hardware/Software
-
7-14
All VAXIVMS computers
D832000, D8332-PLUS, VME532 target development system board with power supply
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NVADE Components (Continued)
NSW-AVIP-BRVM-2 Binary Ada VRTX Int. Pckg.
Tape, Vax-11 1785, 83XX
NSW-AVIP-BRVM-3 Binary Ada VRTX Int. Pckg.
Tape, Vax-8500, 8530, 8600
NSW-AVIP-BRVM-4 Binary Ada VRTX Int. Pckg.
Tape, Vax-8550, 8650, 8700
NSW-AVIP-BRVM-5 Binary Ada VRTX Int. Pckg.
Tape, Vax-88XX, 89XX
Shipping Package
-
Series 32000 Installation Instructions and Applications Notes
1600 bpi magnetic tape (9-track VMS copy format)
Ada Language Reference Manual
(ANSI/MIL-STD 1815A)
Ada Compiler and support tools documentation
Ordering Information
NSW-ARTS-SRVM-1 Source Ada RUNTIME SYSTEM Tape, Vax-11 1750,
11/780, 82XX
NSW-ARTS-SRVM-2 Source Ada RUNTIME SYSTEM Tape, Vax-11 1785, 83XX
NSW-ARTS-SRVM-3 Source Ada RUNTIME SYSTEM Tape, Vax-8500, 8530,
8600
NSW-ARTS-SRVM-4 Source Ada RUNTIME SYSTEM Tape, Vax-8550, 8650,
8700
NSW-ARTS-SRVM-5 Source Ada RUNTIME SYSTEM Tape, Vax-88XX, 89XX
Part Number
NSW-Ada-BRVM-1
NSW-Ada-BRVM-2
NSW-Ada-BRVM-3
NSW-Ada-BRVM-4
NSW-Ada-BRVM-5
NSW-AVIP-BRVM-1
Binary Ada Cross Dev. System
Tape, Vax-11 /750, 11/780,
82XX
Binary Ada Cross Dev. System
Tape, Vax-11 1785, 83XX
Binary Ada Cross Dev. System
Tape, Vax-8500, 8530, 8600
Binary Ada Cross Dev. System
Tape, Vax-8550, 8650, 8700
Binary Ada Cross Dev. System
Tape, Vax-88XX, 89XX
NSP-Ada-VMS
Binary Ada VRTX Int. Pckg.
Tape, Vax-11 /750, 11/780,
82XX
Additional Manual Sets for
VAXIVMS Ada Development
System
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Shared Libraries
A shared library is a library of subroutines that is accessed at run-time rather than being included in the
program when the program is linked. As a result, programs that use shared libraries occupy less space on
disk and in memory. In addition, when a library is modified, programs that use that library do not have to be
recompiled to benefit from changes to that library.
GENIXIV.3 binary is provided with a shared version of
a subset of 'libc.a' and the Networking Services Library. Tools are provided for the user to generate additional shared libraries.
Transport Level Interface (TLI) and Transport Provider
Interface (TPI)
GENIXIV.3 includes two significant libraries that help
the protocol-developer produce protocols that conform to industry standards. The TLI library is composed of user-level functions that provide access to
standard protocol services as defined by the ISO
Transport Service Interface. The TPI library specifies
capabilities that must be supplied by a transport provider and the required interface to those capabilities to
maintain consistency with the TLI library.
Together, the TLI and the TPI libraries create the
means by which network-independent applications
can be written. An application written using the TLI
library will work without modification over any network
implemented according to the TPI specification.
GENIXIV.3 includes a new version of 'uucp' (based
on the Honey-Danber 'uucp') that is implemented using the TLI library. Remote File Sharing, described below, is also implemented using the TLI library.
Assist
'Assist' is a set of programs that provide on-line assistance to users of the GENIXIV.3 operating system.
'Assist' should not be confused with on-line manual
pages; rather, 'Assist' is a menu-driven program that
helps the user form correct command line syntax on a
step-by-step basis. 'Assist' includes tools for building
custom menus in addition to the menus provided as a
part of the GENIXIV.3 operating system.
File System Switch (FSS)
FSS allows the operating system to support several
different types of file systems simultaneously. For example a file system type could be implemented to permit users to access data stored on floppy diskettes
created by other operating systems.
Remote File Sharing (RFS)
RFS is an example of the kind of network services
that can be developed using Streams. RFS allows a
group of computers to be linked together over a network so that resources belonging to one system (e.g.,
disk files, printers, and tape drives), can be made
available to users on other systems. This availability is
transparent to the user; the user does not have to
know or issue any special commands to access a remote resource.
RFS has built in security features as well. The local
machine administrator decides which file systems will
be available to the network and which remote resources the local users can access.
Mandatory File and Record Locking
Previous versions of the System V UNIX operating
system supported voluntary file and record locking.
Under voluntary file and record locking, a group of
programs must voluntarily agree to honor locks that
may have been placed on a file or a record. It was
possible for a programmer to write a 'maverick' program that refused to honor voluntary locks.
With mandatory file and record locking, a database
designer is guaranteed that any locks the program
places on a file or record will be honored by every
program in the system. Mandatory locks guarantee
the security of database applications.
Demand-Paged Virtual Memory
The GENIXIV.3 operating system supports programs
that access up to 15 Mbytes (if using the NS32082
MMU) or % gigabyte (if using the NS32382 MMU) of
virtual address space. In addition, the GENIXIV.3 operating system takes advantage of the memory protection scheme afforded by the MMU's separate user
and supervisor address space.
Optional Software
KornShell
The Korn shell is an optional command interpreter
compatible with the Bourne shell and offers many features found in the C shell, such as 'aliases'. The Korn
shell introduces new features such as 'vi editing
mode', which allows the user to modify and enter previously entered commands with fewer keystrokes.
CCompiler
The GENIXIV.3 operating system includes a C compiler based on the Berkeley 4.2 bsd 'pcc' (portable C
compiler). The C compiler and associated language
7-17
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Tools for Documenters
Customer Support
Tools for Documenters, derived from AT&T's Documenters Workbench 2.0, is an optional set of software
that contains programs that help users prepare documentation. The programs include text processors
('nroft', 'troff', and 'ditroff'), macro packages ('mm'
and 'man'), preprocessors that prepare special kinds
of text Ctbl' and 'eqn'), and postprocessors that prepare documents for handling by a particular output device, such as a printer or phototypesetter.
The GENIXIV.3 operating system, whether provided
in binary or source form, includes a 90-day warranty.
During the warranty period, customers are entitled to
toll-free telephone access to National's MCS Technical Support Engineering Center to receive assistance,
report bugs and obtain workarounds. In addition, the
customer will receive any update releases that become available from National Semiconductor at no
additional charge.
After the 90-day warranty has expired, extended support can be contracted by calling MCS Logistics at the
toll-free numbers below:
(800) 538-1866 in the USA, except California
(800) 672-1811 in California
(800) 223-3248 in Canada
Outside the USA and Canada:
(408) 749-7306
Machine Readable Documentation
The optional Machine Readable Documentation includes source to all GENIXIV.3 manuals for those
OEM's who plan to modify and print their own manual
sets.
Benefits
AVAILABLE IN SOURCE FORM TO QUALIFIED CONTRACTORS OF NSC
All source files required to produce a binary version of
the GENIXIV.3 operating system are provided. These
files include source code to the kernel (including demand-paged virtual memory code), all utilities, device
drivers, libraries, the C compiler, assembler and linker.
Kernel source code is adaptable to the NS32016,
NS32032, and NS32332 CPU and the NS32082 and
the NS32382 MMU by compilation switches. The
GENIXIV.3 operating system is designed to run on
hardware configurations that include the NS32201
Timing Control Unit, the NS32081 Floating Point Unit,
and the NS32202 Interrupt Control Unit, a minimum of
one RS232 serial port, 2 Mbytes of RAM, and a minimum 40 Mbytes of disk storage for the binary operating system.
In addition, the GENIXIV.3 operating system source
product includes a binary image of the root and lusr
file systems which was generated from the provided
source files.
Licensing
The GENIXIV.3 operating system is provided under
license from National Semiconductor Corporation.
The Source License under Contractor Provisions provides non-exclusive rights to use the GENIXIV.3 operating system source for internal purposes. A separate
Binary Distribution License provides right to distribute
binary copies and includes per copy royalty rates. To
obtain licensing information, contact your National
Semiconductor sales engineer.
Ordering Information
NSW-GV3-SRNX
NSW-GV3-SCNX
7-18
GENIXIV.3 source on reel-toreel 9-track tape
GENIXIV.3 source on 9-track
cartridge tape
,--------------------------------------------------------------------------, CD
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Can be installed in any Series 32000
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scheduler
Manages memory pool, mailboxes,
timing and terminal 1/0
Can reside in PROM and be located
anywhere in memory
•
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The VRTX® ISeries 32000 executive is the central
member of a set of silicon software building blocks
used in Series 32000-based real·time embedded systems. The executive manages the multitasking environment and responds to operating system service requests from application tasks.
The executive can be used alone or in combination
with the other silicon software components to build a
more complete operating system. The 10X® ISeries
32000 and FMX® ISeries 32000 components support
a file system that is media-compatible with PC-DOS.
The TRACERTM/Series 32000 is an interactive multi-
No requirements for particular timers,
interrupts or busses
Has hooks at key processing points for
easy customization
Comprehensive manuals with many
examples
Hot-line technical support
Integrated with interactive multitasking
debugger (optional)
Integrated with PC-DOS compatible file
system (optional)
tasking debugger that can be used in VRTX-based
systems for debug, download and test.
All the components can reside in PROM's installed in
the target system. They can be placed anywhere in
the address space and make minimal assumptions
about the hardware environment. Small user-written
routines supply information about the local implementation of interrupts, timers, 1/0 devices, etc. Application tasks interface to the components with Series
32000 SVC (Supervisor Call) interrupts, thus code for
the components does not require linking with userwritten code.
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ment or for maintaining a counter in the task control
block to monitor task execution.
The VRTX/Series 32000 R&D Package contains the
product, manuals and other documentation required
to develop a real-time application using only the VRTX
kernel. You can also purchase TRACER/Series
32000, lOX/Series 32000 and FMX/Series 32000 as
separate R&D Packages or as bundled combinations.
When the development phase is complete, contact
the National Semiconductor Series 32000 Software
Products Marketing Group to purchase a license to
incorporate VRTX into products in production volumes.
National also offers Host-Based Special Volume
Agreements which include R&D Packages and the
rights to make unlimited copies of VRTX on a designated workstation or CPU. Contact the Series 32000
Product Marketing Group for details.
Task Management
The basic logical unit controlled by VRTX is the task.
The task is a logically complete path through user
code that requires system resources. Each task has a
priority level used by VRTX to determine how access
to the CPU is allocated. Up to 256 priority levels are
available. VRTX allocates the CPU sequentially to the
highest priority task that is ready to execute. Tasks
can create, delete, suspend, and modify the priority of
themselves and other tasks. Task delays and timeslicing are also available.
Intertask Communication and Synchronization
Tasks can communicate and synchronize with other
tasks via exchange of pointer-length messages
through mailboxes. These permit mutual exclusion
and resource-locking. VRTX also has directives for dynamically building and managing message queues.
Interrupt Services
Package Contents
VRTX has directives for user-written interrupt handlers
that provide the interface between tasks and devices.
They permit the interrupt handler to influence the
scheduling of critically important tasks. Additionally,
almost all of the VRTX facilities are available to interrupt routines, so system services can be performed
immediately upon receipt of an interrupt.
The VRTX/Series 32000 R&D Package contains:
One master copy of VRTX in two 2732 PROM's
A boxtop license to make five copies of VRTX (USA
only)
Five sets of Hunter & Ready Silicon Software copyright labels
Five VRTX/Series 32000 User's Guides
A binder containing R&D documentation:
Getting Started with Silicon Software Components
How to Write a Board Support Package for VRTX
Interfacing a Language to Silicon Software Components
Application Notes
Customer Support information
VRTX Release Notes
Memory Management
VRTX provides directives for managing the free memory pool. To minimize fragmentation and overhead,
storage is allocated and released as fixed size blocks
from within memory partitions. Partitions can be built
dynamically. There are no constraints on block size.
Special Device Support
Since many applications require a real-time clock and
a character I/O device, support for them is integrated
into VRTX. Designers need only supply a small hardware-dependent interrupt service routine for each.
VRTX will then manage all the logical operations to
supply the clock management and character I/O services to application tasks and interrupt handlers.
VRTX Timing Summary
Extensions
VRTX accommodates applications with special requirements by supplying three hooks at key points in
its execution. They permit the designer to modify
VRTX processing without having to modify VRTX itself. Whenever VRTX reaches a hook it checks for the
presence of an application routine. VRTX hooks are
called at task create, delete, and context switch.
There are no constraints on hook use.They can be
used for saving/restoring the floating-point environ-
7-20
System Call
32332 Time
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System Call
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SC.-ACCEPT
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Type
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Initialization
VRT)LINIT
VRT)LGO
Initialize VRTX
Start multitasking
Task
Management
SC_TCREATE
SC_TDELETE
SC_TSUSPEND
SC_TRESUME
Create a task
Delete a task
Suspend a task
Resume execution of
suspended task
Change task priority
Get task status
Disable task
rescheduling
Enable task
rescheduling
SC_TPRIORITY
SC_TINOUIRY
SC_LOCK
SC_UNLOCK
Communications
Services
SC_POST
SC_PEND
SCJCCEPT
SC_OCREATE
SC_OPOST
SC_OPEND
SC_OACCEPT
SC_OINOUIRY
Memory
Management
SC_GBLOCK
SC_RBLOCK
SC_PCREATE
SC_PEXTEND
Timer
Services
SC_GTIME
SC_STIME
SC_TDELAY
SC_TSLICE
UI_TIMER
Character
I/O
SC_GETC
SC_PUTC
UI_RXCHR
UI_TXRDY
SC_WAITC
Interrupt
Services
customers over the telephone with product related
technical problems.
For more information, please call:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
Licensing
All R&D packages are licensed through a National
Semiconductor Binary Software Licensing Agreement.
In the United States, breaking the seal on the product
package indicates acceptance of the terms of the license; no signature is required. For international sales
a signed Binary Software License Agreement is required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Software Marketing Group before breaking the
seal on the package.
Post message to
mailbox
Pend for message at
mailbox
Accept message at
mailbox
Create message queue
Post message to
queue
Pend for message
from queue
Accept message from
queue
Get queue status
Ordering Information
NSW-VRTX-BRVM VRTX/Series 32000 in two 2732
EPROMs, and as files of S-records and define-byte records on a
1600 bpi 9-track VAXIVMS BACKUP tape, manuals and R&D documentation.
NSW-VRTX-BRVX VRTX/Series 32000 in two 2732
EPROMs, and as files of S-records and define-byte records on a
1600 bpi 9-track VAX/4.2 bsd
"tar" tape, manuals and R&D documentation.
NSW-VRTX-BLAF VRTX/Series 32000 in two 2732
EPROMs, and as files of S-records and define-byte records
stored in MS-DOS format on a 5%
inch PC-DOS floppy diskette,
manuals and R&D documentation,
NSW-VRTX-SPNN VRTX/Series 32000 source code
listing.
Get memory block
Release memory block
Create memory
partition
Extend memory
partition
Get system time
Set system time
Suspend task
temporarily
Enable round-robin
scheduling
Post time Increment
from interrupt
Get a character
Put a character
Post received
character from
interrupt
Post transmit ready
from interrupt
Wait for special
character
ULENTER
Enter interrupt handler
UI_EXIT
Exit from interrupt
handler
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National Semiconductor offers a one year complete
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Provides device-level input/output
facilities for VRTX-based software
system
Handles the translation of read and write
commands from tasks into specific
operations on particular devices
Handles the allocation of devices to
tasks
• Handles the conversion of data from
device-specific formats into user-defined
formats
• Can work with most types of 110 devices
• Has hooks and extension services for
easy customization
• Comprehensive manuals with many
examples
• Hot-line technical support
lOX/Series 32000 is the Input/Output Executive, a
companion software component for VRTX/Series
32000. lOX provides embedded microprocessor applications with a powerful set of input/output (I/O) facilities for use in a multitasking, real-time environment.
Like VRTX, lOX is a silicon software component; it
makes no assumptions about its target environment,
and can thus be used unchanged in many different
custom applications. lOX manages any number and
kind of I/O devices in a real-time, multitasking application. lOX services allow several tasks to share a single
device, with requests on that device processed according to an application-specified priority. Tasks can
transfer data to or from devices in buffered or direct
mode, using either sequential or random access. In
buffered mode, lOX maintains one or more intermedi-
ate buffers for a task using a device, minimizing the
time of task suspension by overlapping physical 1/0
with task processing. Buffering isolates application
tasks from the physical characteristics of devices, so
that serial devices such as terminals can coexist with
random access devices such as disks, both accessed
by the same buffered lOX calls.
lOX not only controls device resources, it integrates
those devices into a unified framework, providing a
consistent I/O interface with a large degree of device
independence. Application code written using lOX's
buffered I/O services can be transported with only minor modifications to other systems, even if those systems utilize completely different I/O devices. In fact,
code written in a high-level language may require no
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Device Support
lOX supports three device types-block, disk and
character devices. For each device type lOX provides
a number of salient features:
Device sharing
lOX supports shared devices through constructs
called channels. A channel is a data structure that
represents a logical conduit, or path to a device. lOX
provides separate position and error indicators for
each channel open to a device, thus facilitating device
sharing, critical in a multitasking environment.
Disk position support
lOX maintains position indicators for disks (or any random access devices), thus relieving the application
from the responsibility for calculating or maintaining
position.
Terminal support
lOX's terminal handling calls support echoing, type
ahead and holding or disabling terminal output.
For applications that require close control over device
operations, lOX's direct mode provides a set of services that can transfer data or perform device-specific
control operations and synchronization, yet still free
the application programmer from some hardware-dependent considerations such as device addresses,
command codes and interrupt handling"
lOX Features
Buffered 1/0
lOX's buffering services improve performance and
free the application from device-specific data block
sizes and formats by transferring data between the
application and lOX-maintained buffers, overlapping
physical 1/0 with application processing whenever
possible. lOX manages the intermediate buffers to
serve several purposes:
Device Independence
Application tasks can ignore the idiosyncrasies of device operation or block sizes and formats, and can
transfer fixed or variable length records according to
application needs, rather than device requirements.
Overlapping 1/0
Buffered 1/0 overlaps application processing with file
110 operations, freeing the application from synchronizing such operations.
Caching
For random-access devices such as disks, lOX's buffering services improve performance by checking lOX
buffers for the sector requested by the application,
accessing the device only if the target sector is not
buffer-resident.
Variable record length support
With lOX's buffering services, record size can be determined by the presence of a delimiter character in
the input or output stream, rather than being tied to a
fixed block size.
Extensibility
While lOX never has to be modified, it can nonetheless be extended to meet unique needs.
A user-written 1/0 handler that directly manipulates
hardware can be placed into the lOX higher-level
functions. This facility can not only service unusual
devices, but also emulate a physical device, such as a
UNIX like "pipe" between separate processes.
For less fundamental extensions lOX includes four
software "hooks" that give the system programmer
the capability to fine-tune lOX functionality so that it
matches it's computer environment.
lOX can also be extended by adding auxiliary file management software components (FMX).
The IOXISeries 32000 R&D Package contains the
product, manuals and other documentation required in
conjunction with VRTXISeries 32000 to develop a
real-time embedded application which requires advanced, multitasking, device-level 1/0 facilities for peripherals. You can also purchase TRACERISeries
32000 and FMXISeries 32000 as separate R&D
Packages or as bundled combinations.
Direct 1/0
Direct 1/0 allows the programmer to bypass lOX's
buffering services whenever an application requires
deterministic control over when and how an 1/0 operation occurs.
Synchronous 1/0
The calling task is suspended until the requested operation is completed and either data or status or both
have been returned. In this way a lock-step synchronization is enforced on an 1/0 operation.
Asynchronous 1/0
An application using direct 1/0 can initiate one or
more 1/0 operations and then continue with other processing, retrieving the results of the 1/0 later via a
VRTX mailbox or message queue. This allows 1/0 to
be overlapped with continued operation of the calling
task.
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Package Contents
The IOXISeries 32000 R&D Package contains:
One master copy of lOX in two 27128 PROMs
A boxtop license to make five copies of lOX (USA
only)
Five Hunter & Ready Silicon Software copyright labels
Five 10XISeries 32000 User's Guides and Installation
Guides
Customer Support Information
Release Notes
7-23
•
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Customer Support
NSW-IOX-SPNN lOX/Series 32000 source code listing.
National Semiconductor offers a one year complete
technical support period. Extended support provisions
can be arranged by calling MCS Logistics at the tollfree numbers which follow.
The MCS Service Technical Support Engineering Center has highly trained technical specialists to assist
customers over the telephone with product related
technical problems.
For more information, please call:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
Documentation
NSW-IOX-MS
lOX/Series
32000
Installation
Guide and User's Guide.
lOX System Calls
Type
Licensing
All R&D packages are licensed through a National
Semiconductor Binary software Licensing Agreement.
In the United States, breaking the seal on the product
package indicates acceptance of the terms of the licenses; no signature is required. For international
sales a signed Binary Software License Agreement is
required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Marketing Group prior to breaking the seal on
the package.
National also offers a Host-Based Package which includes the R&D packages ordered and the rights to
make unlimited copies of VRTX, lOX, FMX and
TRACER on a designated workstation or CPU or a
Target-Based Package which includes the rights to
make unlimited copies of the purchased R&D Packages (VRTX, lOX, FMX or TRACER) for a specific target product.
Initialization
10lNIT
Initialize lOX
100PEN
10ClOSE
10POSN
Open channel
Close channel
Set file position
Buffered 1/0
Services
10GET
10PUT
Read byles
Writebyles
Direct 1/0
Services
10READ
10WRITE
10WAIT
10RESET
10CNTRl
Read block
Write block
Wait for 1/0 completion
Reset channel
Perform device control
Device
Definition
Services
10DFBlK
Define general-block
device
Define character device
Define disk device
Remove device
definition
Device
Interface
Services
10POST
Extension
Services
7-24
Description
Channel
Control
Services
Ordering Information
NSW-IOX-BRVM lOX/Series 32000 in two 27128
EPROMs, and as files of S-records
and define-byte records on a
1600 bpi 9-track VAXIVMS BACKUP tape, manuals and R&D documentation.
NSW-IOX-BRVX lOX/Series 32000 in two 27128
EPROMs, and as files of S-records
and define-byte records on a
1600 bpi 9-track VAX/4.2 bsd "tar"
tape, manuals and R&D documentation.
NSW-IOX-BLAF lOX/Series 32000 in two 27128
EPROMs, and as files of S-records
and define-byte records stored in
MS-DOS format on 51,4 inch PCDOS floppy diskette, manuals and
R&D documentation.
Call
10DFCHR
10DFDSK
10RMDEV
10STMR
10CTMR
10TIMER
Post 1/0 request
completion
Start device timer
Cancel device timer
Announce device
timer interrupt
10RXCHR
Put character into
input buffer
10RXCHM
Put multiple characters
into input buffer
10ECHO
Put character into
echo buffer
10ECHOM
Put multiple characters
into echo buffer
10TXRDY
Get character from
output buffer
10TXRDM
Get multiple characters
from output buffer
10EXCPT
Call exception routine
10ATCHC
Attach 1/0 routine
to lOX
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , 00
...mCD'
FMX/Series 32000 R&D Package
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Table
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FMX Features
Configuration
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File Management
'0
FMX provides system calls for creating and deleting
files, renaming files, and for getting and setting certain
file characteristics. The file management calls and the
directory management calls are implementations of
the "generic file management operations" defined by
lOX. lOX provides a thin layer of code that identifies
these calls, then routes them to FMX for interpretation
and execution.
FMX is initialized via a special call, FDINIT. Initialization is the process' by which FMX sets the starting
values of all its internal data structures and variables.
FMX must be initialized before it can perform any operations.
The FMX/Series 32000 R&D Package contains the
product, manuals, and other documentation required
in conjunction with VRTX/Series 32000 and IOX/Series 32000 to develop a real-time embedded application which requires advanced, multitasking, file management services. You can also purchase TRACERI
Series 32000 as a separate R&D Package.
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Directory Management Services
FMX supports a hierarchical directory tree structure. It
provides calls for creating directories in given directories and for deleting directories.
Package Contents
The FMX/Series 32000 R&D Package contains:
One master copy of FMX in two 27128 EPROMs
A boxtop license to make five copies of FMX (USA
only)
Five Hunter & Ready Silicon Software copyright labels
Five FMX/Series 32000 User's Guides
Customer Support Information
Release Notes
Volume Management Services
A logical collection of directories on a disk is called a
volume. FMX provides a set of system calls to determine the characteristics of a new disk and to introduce the new disk to the system. These functions include evaluating volume parameters; mounting, dismounting, and synchronizing volumes; and obtaining
volume attributes.
Formatting
Customer Support
Formatting is the process of writing the data addressing scheme on the disk or sub-disk. This addressing
scheme makes it possible for the system to access
precise locations on the disk so that data can be reliably written to and read from the disk. The FMX format system call, FDFMAT, provides the necessary
tools to format disks in a variety of ways suitable for
most.
National Semiconductor offers a one year complete
technical support period. Extended support provisions
can be arranged by calling MCS Logistics at the tollfree numbers which follow.
7-26
,--------------------------------------------------------------------------,
~
CD
The MCS Service Technical Support Engineering Center has highly trained technical specialists to assist
customers over the telephone with product related
technical problems.
For more information, please call:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
NSW-FMX-BLAF
FMX/Series 32000 in two 27128
EPROMs, and as files of S-records and define-byte records
stored in MS-DOS format on a
5% inch PC-DOS floppy diskette,
manuals and R&D documentation.
FMX/Series 32000 source code
listing.
NSW-FMX-SPNN
NSW-FMX-M
All R&D packages are licensed through a National
Semiconductor Binary software Licensing Agreement.
In the United States, breaking the seal on the product
package indicates acceptance of the terms of the licenses; no signature is required. For international
sales a signed Binary Software License Agreement is
required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Marketing Group prior to breaking the seal on
the package.
National also offers a Host-Based Package which includes the R&D packages ordered and the rights to
make unlimited copies of VRTX, lOX, FMX and
TRACER on a designated workstation or CPU or a
Target-Based Package which includes the rights to
make unlimited copies of the purchased R&D Packages (VRTX, lOX, FMX or TRACER) for a specific target product.
FMX/Series 32000 User's Guide.
FMX Service Calls
Type
Initialize FMX
File
Management
Services
FMCREAT
FMDELET
FMRENAM
FMGATIR
FMSATIR
Create file
Delete file
Rename file
Get file attributes
Set file attributes
Directory
Management
Services
FMMKDIR
FMRMDIR
Make subdirectory
Remove subdirectory
File I/O
Services
FMOPEN
Open file
Formatting
7-27
Description
FDINIT
Ordering Information
NSW-FMX-BRVM FMX/Series 32000 in two 27128
EPROMs, and as files of S-records and define-byte records on a
1600 bpi 9-track VAXIVMS
BACKUP tape, manuals and R&D
documentation.
NSW-FMX-BRVX FMX/Series 32000 in two 27128
EPROMs, and as files of S-records and define-byte records on a
1600 bpi 9-track VAX/4.2 bsd
"tar" tape, manuals and R&D documentation.
Call
Initialization
Volume
Management
Services
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FDMOUNT
FDDISMT
FDSYNC
FDEVOL
FDQVOL
Mount volume
Dismount volume
Synchronize volume
Evaluate volume
parameters
Get volume attributes
FDFMAT
Format disk
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VRTX/Series 32000 Board
Support Package for National's
Series 32000-Based Boards
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Board support routines for popular
National Series 32000 boards
• Brings up a tested VRTX, lOX, FMX and
TRACER application immediately
• Includes all code to initialize and run
VRTX, lOX, FMX and TRACER
•
The routines in this package provide all the code
needed to build and run a simple VRTX application
(with or without TRACER) on several of National's Series 32000 boards. The application, which is documented in the manual "How to Write a 80ard Support
Package for VRTX", consists of two tasks, one of
which receives characters from an interrupting character 1/0 device and posts them to a VRTX mailbox.
The second task pends at the mailbox for the characters and outputs them to the 1/0 device using VRTX.
The VRTX support routines for each board include:
- Configuration table specific to the board,
- Device initialization code for National's ICU chip
(NS32202),
- Initialization code for the timer and serial 110 channel,
- Code to initialize the 32000 data structures including the Interrupt Dispatch Table, Module Table and
stack,
- Receive and transmit interrupt handler code,
- Timer interrupt handler code,
- The application configuration table.
For designers wishing to have the TRACER debugger
in the system, there are also board support routines
with the code needed to run the application with
TRACER. In addition to the code described above,
these routines include:
- TRACER configuration table,
- TRACER initialization code,
- TRACER character 1/0 handler code
- VRTX/TRACER interface code.
For lOX, an example device driver for a serial 1/0 device and a disk controller are provided, along with all
of the necessary configuration support software. A
FMX example is also provided which runs using either
a ramdisk driver or a disk driver. Example disk drivers
are provided for several disk controllers.
VRTX, lOX, FMX and TRACER support routines are
supplied for National's 0832016, 0832000 and
08332 development boards.
•
•
7-28
Includes code for sample VRTX, lOX,
and FMX application
Routines can be used as templates for
other boards
,--------------------------------------------------------------------, w
CD
Product Contents
For more information, please call:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
VRTX, lOX, FMX and TRACER board support routines
(written in Series 32000 Assembly Language) for National's Series 32000 development boards: DB32016,
DB32000 and DB332
Source code for sample tasks described in the manual
Customer Support Information
Installation Guide
Release Documentation
Licensing
All R&D packages are licensed through a National
Semiconductor Binary Software Licensing Agreement.
In the United States, breaking the seal on the product
package indicates acceptance of the terms of the license; no signature is required. For international sales
a signed Binary Software License Agreement is required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Software Marketing Group before breaking the
seal on the package.
Prerequisites
The syntax in the source code files in this product
conform to the standards and conventions used in National's GNX Language Tools Packages. Designers
wishing to assemble the files will need the GNX Language Tools or their equivalent. Users of other software development tools may have to modify the
source code in order to conform to the requirements
of their tools.
See the National Semiconductor datasheet titled "Series 32000 GENIX Native and Cross-Support (GNX)
Language Tools" for information about National's
tools.
Ordering Information
NSW-VBSP-SRVM VRTX, lOX and FMX/Series
32000 Board Support Packages
on 1600 bpi 9-track reel tape in
VAXIVMS
BACKUP
format;
manual and other documentation.
NSW-VBSP-SRVX VRTX, lOX and FMX/Series
32000 Board Support Packages
on 1600 bpi 9-track reel tape in
VAX/4.2 bsd "tar" format; manual and other documentation.
NSW-VBSP-SLAF VRTX, lOX and FMX/Series
32000 Board Support Packages
stored in MS-DOS format on a
SYS32/20 5% inch PC-DOS
floppy diskette; manual and other
documentation.
Customer Support
National Semiconductor offers a one year complete
technical support period. Extended support provisions
can be arranged by calling MCS Logistics at the tollfree numbers below.
The MCS Service Technical Support Engineering Center has highly trained technical specialists to assist
customers over the telephone with product related
technical problems.
7-29
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VRTX, lOX and FMX/Series 32000
Support Libraries
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Routines encourage writing VRTX, lOX
and FMX applications in C or Pascal
Interface routines matched to National's
GNX Language Tools
Package available on same media as
National's GNX tools
C Run-Time Library extends C for
concurrent programming
•
•
•
C Run-Time support for standard inputoutput (stdio) functions
Integrates standard 1/0 run-time library
(stdio) with real-time services of
VRTX/OS
Hook routines included to add floatingpoint support to VRTX
The VRTX/Series 32000 C Run-Time Library
This package provides libraries that simplify the writing of VRTX-based applications in C or Pascal rather
than just Series 32000 Assembly Language. The
VRTX, lOX and FMX Interface Library enables the designer to make system calls to VRTX, lOX and FMX
from C or Pascal programs. The C Run-Time Library
supports the standard function calls made from C programs and, where appropriate, invokes services from
VRTX, lOX or FMX. Some of the run-time library routines require lOX and FMX as well as VRTX.
The C Run-Time Library provides external run-time
functions not provided by the C language, It contains
character and file 1/0, string manipulation, floatingpoint routines, storage allocation and file management
functions. The library functions make calls to the
VRTX kernel and, for certain 1/0 operations, to lOX
and FMX. Library functions return an error code if a
call is made to a VRTXIOS component absent from
the system.
If VRTX is operating in a Series 32000 hardware environment
with
National's
Floating-Point
Unit
(NS32081), the designer can use hook routines supplied in the library to expand VRTX task management
to handle the floating-point environment.
All C Run-Time Library functions are re-entrant, that is,
they can be used asynchronously by several tasks.
Tasks can share a common copy of function code to
save memory space. When a task using a function is
interrupted by another task before it finishes with the
function, the interrupting task can use the same copy
of the function code without corrupting the original
task's data.
The C Run-Time Library is delivered as a library of
object modules (GNX "ar" format). As a convenience
for the VRTX system designer, the library also contains the object modules for the C Interface Library
and VRTX hook routines. Like the interface routines
the hook routines are included in the package in
source code form.
Interface Libraries
Since requests for VRTX, lOX and FMX services are
made with supervisor calls (SVCs) that can only be
performed from assembly language programs, a high
level language program must cali interface routines to
use VRTX, lOX and FMX services. The interface libraries are collections of Series 32000 assembly language routines that logically sit between a C or Pascal
program and VRTX, lOX and FMX. When a function is
called from the program, the appropriate library routine accepts the parameters from the caller and performs a Series 32000 supervisor cali (SVC) to VRTX,
lOX and FMX. When VRTX, lOX and FMX return from
processing the call, the routine transforms the results
into the form expected by the caller and returns control.
The VRTX, lOX and FMX Interface Libraries contain
routines to handle calls for task management, intertask communications, memory management, timing
services, simple character 1/0, allocating device resources, providing a consistent 1/0 interface, and disk
file management. There are no routines for VRTX interrupt handler calls because interrupt handlers are
typically written in assembly language and can issue
SVCs directly.
The interface routines are written in Series 32000 assembly language and delivered in source code form
as well as in libraries of object modules (GNX "ar"
format). The assembly language syntax and calling
sequences conform to the conventions in National's
GNX Language Tools packages.
Package Contents
VRTX, lOX, and FMX C Interface Library source code
(in GNX assembly language)
VRTX, lOX, and FMX C Interface Library as object
module library (GNX "ar" format)
VRTX Pascal Interface Library source code (in GNX
assembly language)
VRTX Pascal Interface Library as object module library (GNX "ar" format)
C Run-Time Library as object module library (GNX
"ar" format)
7-30
en
(I)
VRTX C Language User's Guide
VRTX Pascal Language User's Guide
lOX C User's Guide
FMX C User's Guide
C Run-Time Library User's Guide
Customer Support Information
Release Documentation & Installation Guide
VRTX C Interface Routines and Calling Sequences
Task Management
sc_tcreate (task, tid, pri, &err)
Create Task
sc_tdelete (tid/pri, code, &err)
Delete Task
sc_tsuspend (tid/pri, code, &err)
Suspend Task
sc_tresume (tid/pri, code, &err)
Resume Task
sc_tpriority (tid, pri, &err)
Change Task Priority
tcb = sc_tinquiry (info, tid, &err)
Task Inquiry
sc_lock()
Disable Rescheduling
sc_unlock( )
Enable Rescheduling
Communication and Synchronization
sc_post (&mbox, msg, &err)
Post Messge to Mailbox
msg = sc_pend (&mbox, timeout, &err)
Pend for Message from Mailbox
msg = sc_accept (&mbox, &err)
Accept Message from Mailbox
sc_qcreate (qid, qsize, &err)
Create Queue
sc_qpost (qid, msg, &err)
Post Message to Queue
msg=sc_qpend (qid, timeout, &err)
Pend for Message from Queue
msg=sc_qaccept (qid, &err)
Accept Message from Queue
Memory Management
block = sc_gblock (pid, &err)
Get Memory Block
sc_rblock (pid, block, &err)
Release Memory Block
sc_pcreate (pid, paddr, psize, bsize &err)
Create Memory Partition
sc_pextend (pid, paddr, psize, &err)
Extend Memory Partition
Real-Time Clock
time = sc_gtime ( )
Get Time
sc_stime (time)
Set Time
sc_delay (ticks)
Delay Task
sc_tslice (ticks)
Enable Timeslicing
Character I/O
char = sc_getc ( )
Get Character
sc_putc (char)
Put Character
sc_waitc (char, &err)
Wait for Special Character
7-31
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Direct lID Functions
iocntrl (chnl, code, &info, opts, &err)
bytes = ioread (chnl, buf, count, opts, &err)
ioreset (chnl, opts, &err)
iowrite (chnl, buf, count, opts, &err)
iowait (chnl, opts, &arr)
Perform Device Control
Read a Block
Reset lID Channel
Write a Block
Wait for Outstanding lID
Buffered lID Functions
bytes = iogat (chnl, buf, count, opts, &err)
ioput (chnl, buf, count, opts, &err)
Read Bytes
Write Bytes
Channel Control Functions
chnl = ioopan (david, davtype, opts, &err)
ioclose (chnl, opts, &arr)
posn = ioposn (chnl, offsat, opts, &arr)
Open a Channal
Close a Channel
Set Position
lOX System Services-Block Devices
iopost (&dsrb, opts, &err)
iostmr (&dsrb, ticks, opts, &err)
ioctmr (&dsrb, opts, &err)
iotimer (opts, &err)
Post lID Request Completion
Start a Request Timer
Cancel a Request Timer
Announce lID Timer Interrupt
lOX System Services-Character Devices
rcnt = iorxchr (ddtep, chr, opts, &err)
rcnt
Put a Character into Receiver
or Typehead Buffer
Put Characters into Receiver
or Typehead Buffer
Put a Character into Echo Buffer
Put Characters into Echo Buffer
Get a Character from Transmitter
or Echo Buffer
Get Characters from Transmitter
or Echo Buffer
= iorxchm (ddtep, buf, len, opts, &err)
rcnt = ioecho (ddtep, chr, opts, &err)
rcnt = ioechom (ddtep, buf, len, opts, &err)
chr = iotxrdy (ddtep, opts, &err)
rcnt
= iotxrdm (ddtep, buf, len, opts, &err)
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ddtep = iodfchr (devid, &desc, &info, opts, &err)
iodfblk (devid, &desc, &info, opts, &err)
iodfdsk (devid, &desc, &info, opts, &err)
iormdev (devid, opts, &err)
Define a Character Device
Define a Block Device
Define a Disk Device
Remove a Device Definition
lOX System Services-Initialization, Extension, and Exception
ioinit (&inipk, &err)
ioatchc (&atcpk, &err)
ioexcpt (ecode, opts, &err)
Initialize lOX
Attach an lID Handler
Raise an lID Exception
System Call Function
sc_call (fcode, &packet, &err)
Call a Component
7-32
r--------------------------------------------------------------------------.w
FMX C Interface Routines and Calling Sequences
...iii'CD
UI
File Management Functions
fmcreat (ref_chan, pathname, iniLalloc, options, &err)
fmdelet (ref_chan, pathname, options, &err)
fmgattr (ref_chan, pathname, &attr, &timpk, &file_len, options, &err)
fmrenam (ref_chan, old, new, options, &err)
fmsattr (ref_chan, path name, attr, &timpk, file_len, options, &err)
Create a File
Delete a File
Get File Attributes
Rename a File
Set File Attributes
Directory Management Functions
fmmkdir (ref_chan, pathname, options, &err)
fmrmdir (ref_chan, path name, options, &err)
Create a Directory
Remove a Directory
File liD Functions
channel = fmopen (ref_chan, path name, devtype, options, &err)
ioclose (channel, options, &err)
bytes = ioget (channel, buffer, count, options, &err)
position = ioposn (channel, offset, options, &err)
ioput (channel, buffer, count, options, &err)
bytes = ioread (channel, buffer, count, options, &err)
ioreset (channel, options, &err)
iowait (channel, options, &err)
iowrite (channel, buffer, count, options, &err)
Open a Channel to a File
Close a Channel
Read Bytes
Set Position
Write Bytes
Read a Block
Reset liD Channel
Wait for Outstanding liD
Write a Block
Volume Management Functions
fddismt (device, options, &err)
fdevol (&volpk, &err)
fdfmat (&volpk, &err)
rooLchan = fdmount (&volpk, &err)
fdqvol (&volpk, &err)
fdsync (device, options, &err)
Dismount a Volume
Evaluate Volume Parameters
Format a Volume
Mount a Volume
Query Volume Attributes
Synchronize a Volume
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fdinit (&inipk, &err)
Initialize FMX
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Extension Functions
hooLaddr = fdhook (func, hbuf)
sc_call (fcode, &packet, &err)
Build Hook Routines
Call a Component
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VRTX Pascal Interface Routines and Calling Sequences
Task Management
sctcreate (task, tid, pri, err)
Create Task
sctdelete (tid/pri, code, err)
Delete Task
sctsuspend (tid/pri, code, err)
Suspend Task
sctresume (tid/pri, code, err)
Resume Task
sctpriority (tid, pri, err)
Change Task Priority
tcb: = sctinquiry (info, tid, err)
Task Inquiry
sclock ()
Disable Rescheduling
scunlock ()
Enable Rescheduling
Communication and Synchronization
scpost (mbox, msg, err)
Post Message to Mailbox
msg: = scpend (mbox, timeout, err)
Pend for Message from Mailbox
msg: = scaccept (mbox, err)
Accept Message from Mailbox
scqcreate (qid, qsize, err)
Create Queue
scqpost (qid, msg, err)
Post Message to Queue
msg: = scqpend (qid, timeout, err)
Pend for Message from Queue
msg: = scqccept (qid, err)
Accept Message from Queue
Memory Management
block: = scgblock (pid, err)
Get Memory Block
scrblock (pid, block, err)
Release Memory Block
Create Memory Partition
scpcreate (pid, paddr, psize, bsize, err)
Extend Memory Partition
scpextend (pid, paddr, psize, err)
Real-Time Clock
time: = scgtime ( )
Get Time
scstime (time)
Set Time
scdelay (ticks)
Delay Task
sctslice (ticks)
Enable Timeslicing
Character I/O
char: = scgetc ( )
Get Character
scputc (char)
Put Character
scwaitc (char, err)
Wait for Special Character
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7-34
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C Run-Time Library Routines
Character and String Routines
bcmp
isalnum
bcopy
isalpha
bfill
is ascii
brev
isblank
bzero
iscntrl
ffs
iscsym
index
iscsymf
iswhite
lower
Integer Mathematical Routines
abs
atol
labs
rand
isdigit
islower
isodigit
isprint
ispunct
isspace
isupper
reverse
isxdigit
rindex
sprintf
sscanf
strcat
strchr
strcmp
strsave
VRTX 1/0
gets
getchar
lOX & FMX Buffered 1/0
clearerr
fflush
fclose
fgetc
fdopen
fgets
feof
fopen
ferror
fprintf
fdreopen
sprintf
strcpy
strcrspn
strlen
strncat
strncmp
strncpy
strpbrk
strspn
strrchr
toascii
toint
tolower
toupper
swab
upper
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Floating-Point Mathematical Routines
acos
atof
exp
asin
cabs
fabs
atan
ceil
floor
atan2
cos
frexp
square
idexplo
frexplo
Exception Handling
longjmp
setjmp
Miscellaneous Routines
abort
swab
VRTX Memory Management
calloc
free
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hypot
Idexp
log
log10
modf
pow
sin
sqrt
tan
sinh
cosh
tanh
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realloc
rcopy
puts
printf
putchar
scanf
fputc
fputs
fread
freopen
fscanf
fileno
fseek
ftell
fwrite
getc
getw
frewind
putc
putw
rewind
setbuf
setbuffer
setnbf
setlinebuf
ungetc
sscanf
xprintf
xscanf
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Prerequisites
NSW-VIL-SLAF
VRTX/Series 32000 Support Libraries stored in MS-DOS format on
a SYS32/20 5% inch PC-DOS floppy diskette; manuals and other documentation.
NSW-IIL-SRVM lOX/Series 32000 Support libraries on 1600 bpi 9-track reel tape in
VAXIVMS BACKUP format; manuals and other documentation.
NSW-IIL-SRVX lOX/Series 32000 Support libraries on 1600 bpi 9-track reel tape in
VAX/4.2 bsd "tar" format; manuals
and other documentation .
NSW-IIL-SLAF
lOX/Series 32000 Support libraries stored in MS-DOS format on a
SYS32/20 5% PC-DOS floppy diskette; manuals and other documentation.
NSW-FIL-SRVM FMX/Series 32000 Support libraries on 1600 bpi 9-track reel tape in
VAXIVMS BACKUP format; manuals and other documentation.
NSW-FIL-SRVX FMX/Series 32000 Support libraries on 1600 bpi 9-track reel tape in
VAX/4.2 bsd "tar" format; manuals
and other documentation.
NSW-FIL-SLAF FMX/Series 32000 Support libraries stored in MS-DOS format on a
SYS32/20 5% PC-DOS floppy diskette; manuals and other documentation .
Compiling source code files and linking members of
object module libraries requires National's GNX language tools (in native or cross support versions) on
the host system. See the National Semiconductor datasheet titled "Series 32000 GENIX Native and CrossSupport (GNX) Language Tools" for information.
Customer Support
National Semiconductor offers a one year complete
technical support period. Extended support provisions
can be arranged by calling MCS Logistics at the tollfree numbers below.
The MCS Service Technical Support Engineering Center has highly trained technical specialists to assist
customers over the telephone with product related
technical problems.
For more information, please call:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
Licensing
All R&D packages are licensed through a National
Semiconductor Binary Software Licensing Agreement.
In the United States. Breaking the seal on the product
package indicates acceptance of the terms of the license; no signature is required. For international sales
a signed Binary Software License Agreement is required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Software Marketing Group before breaking the
seal on the package.
Documentation
NSP-VC-M
NSP-RTC-M
NSP-VPAS-M
NSP-IC-M
NSP-FC-M
Ordering Information
NSW-VIL-SRVM VRTX/Series 32000 Support Libraries on 1600 bpi 9-track reel
tape in VAXIVMS BACKUP format;
manuals and other documentation.
NSW-VIL-SRVX VRTX/Series 32000 Support Libraries on 1600 bpi 9-track reel
tape in VAX/4.2 bsd "tar" format;
manuals and other documentation.
7-36
VRTX C User's Guide
C Run-Time Library User's Guide
VRTX Pascal User's Guide
lOX C User's Guide
FMX C User's Guide
.--------------------------------------------------------------------------,0
CD
TRACER/Series 32000 R&D Package
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Operates without modification in any
VRTX/Series 32000 hardware
environment
Companion product to VRTX: displays
VRTX TCB's, mailboxes, queues and
buffers
Operates independently of VRTX; does
not run as a task
Resides in PROM and can be located
anywhere in memory
Allows breakpoints by task or in userwritten system code
Displays and modifies memory or
registers by task
Provides single-stepping, downloading
and disassembly
III Can be extended to support userdefined features
Independent of software development
environment
Comprehensive manual with many
examples
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terminal. This permits changes to command syntax,
macro-like command expansion and customized displays.
TRACER supports up to 16 breakpoints, each with a
unique iteration count. Breakpoints can be set by task,
which is useful for debugging code shared between
tasks. Since TRACER operates outside the multitasking environment, it can set breakpoints in I/O routines,
interrupt service routines, and in user-written system
code.
TRACER can display VRTX system structures such as
task control blocks, mailboxes, queues and I/O buffers in tabular form with their contents interpreted in
easy-to-read format rather than as memory locations.
TRACER can examine a range of memory locations
and display them in hex, ASCII or as disassembled
code. The contents of a location can be changed, or
all locations in a range can be set to a value. Registers can be displayed and modified for any task. For
non-executing tasks, TRACER can display and modify
the register values directly in the TCB. A disassembler
within TRACER can translate binary code into assembly mnemonics. The TRACER on-line help facility also
provides the programmer with a brief summary of
TRACER command syntax and options.
TRACER/Series 32000 is an interactive multitasking
debugger designed for use with VRTX/Series 32000based systems. TRACER runs in parallel with the mUltitasking environment rather than as a task. This permits it to monitor and control program execution without competing with tasks for system resources like
task control blocks and queues. It does not distort
system behavior by affecting the competition of tasks
for access to the CPU. Since TRACER has its own
data structures, it does not depend on the correct execution of the VRTX-based system for its own execution. If bugs in an application task cause a system
crash, TRACER survives and provides a means to diagnose the problem.
There are no dependencies on the host system development environment. TRACER is not linked with user
task code. Installation in a system requires only plugging the TRACER PROMs into the target board, building a configuration table to tell TRACER about the
hardware environment, and supplying a small devicespecific interrupt handler for the TRACER communications I/O channel. TRACER can be hooked into a
VRTX-based system during development, and removed completely for production.
TRACER commands are entered interactively via a
character-oriented device, usually a terminal. When a
spare I/O channel is available, TRACER can use it;
otherwise, it can share the terminal associated with
VRTX's character I/O facility. TRACER command pro-
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For more information, please cali:
(800) 538-1866 in the USA except for California
(800) 672-1811 within California
(800) 223-3248 in Canada
(408) 749-7306 for rest of world
TRACER Command Summary
Breakpoint Commands
sb
Set Breakpoint
db
Display Current Breakpoints
rb
Remove Breakpoint
Licensing
Memory and Register Commands
sm
Set Memory
dm
Display Memory in Hex and ASCII
sr
Set Registers for a Task
dr
Display Registers for a Task or System Routine
Ali R&D packages are licensed through a National
Semiconductor Binary Software Licensing Agreement.
In the United States, breaking the seal on the product
package indicates acceptance of the terms of the license; no signature is required. For international sales
a signed Binary Software License Agreement is required. If changes are required to the license agreement, contact the National Semiconductor Series
32000 Software Marketing Group before breaking the
seal on the package.
Execution Control Commands
rx
Resume Execution
xs
Execute Single Step
tc
Switch to Command Mode
tt
Switch to Tasking Mode
System Status Commands
ds
Display System Status
dt
Display Task Status
dq
Display Queue Status
dx
Display Mailbox Pends
di
Display Input Buffer Contents & Status
Display Output Buffer Contents & Status
do
Ordering Information
The TRACER/Series 32000 R&D package contains:
One master copy of TRACER in two 27128 PROMs
A boxtop license to make five copies of TRACER
(USA only)
Five sets of Hunter & Ready Silicon Software copyright labels
Five TRACER/Series 32000 User's Guides
Customer Support information
TRACER 32000 release notes
NSW-TRAC-BRVM TRACER/Series 32000 in two
27128 EPROMs, and as files of
S-records and define-byte records on a 1600 bpi 9-track VAX/
VMS BACKUP tape, manuals
and R&D documentation.
NSW-TRAC-BRVX TRACER/Series 32000 in two
27128 EPROMs, and as files of
S-records and define-byte records on a 1600 bpi 9-track VAX/
4.2 bsd "tar" tape, manuals and
R&D documentation.
NSW-TRAC-BLAF TRACER/Series 32000 in two
27128 EPROMs, and as files of
S-records and define-byte records stored in MS-DOS format
on a SYS32/20 5% inch PCDOS floppy diskette, manuals
and R&D documentation.
NSW-TRAC-SPNN TRACERISeries 32000 source
code listing.
Customer Support
Documentation
National Semiconductor offers a one year complete
technical support period. Extended support provisions
can be arranged by calling MCS Logistics at the tollfree numbers below.
The MCS Service Technical Support Engineering Center has highly trained technical specialists to assist
customers over the telephone with product related
technical problems.
NSP-TRAC-M
Other Commands
dl
Download Code from Host System
Ii
List Disassembled Code
he
Display TRACER Commands & Arguments
Package Contents
7-38
TRACER/Series 32000 User's
Guide
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National Semiconductor
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Series 32000® EXEC
ROMabie Real-Time Multitasking
EXECUTIVE
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III Provides a multitasking executive for
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• Reconfigurable
• Real-time clock support for time-of-day
and event scheduling
• Allows up to 256 levels of task priority
which can be dynamically assigned
• Up to 256 logical channels for task
communication
• Free-memory pool control
• Available for VAXTM/VMSTM, VAX/UNIX®
and SYS32™ development environments
real-time applications
II Supports all Series 32000 CPUs
.. Complete Source Code Package
- Fully user configurable
- Hardware independent
.. Extensive user implementation support
- Unique demo, program introduction
- C and Pascal interface libraries
- Sample terminal drivers
-Integrated with Series 32000
development boards and monitor
Product Overview
time, such as intertask communications, system resource access based upon task priority, real-time
clock control, and interrupt handling. These functions
greatly simplify application development in such areas
as instrumentation and control, test and measurement, and data communications. In these applications, EXEC provides an environment in which systems programmers can immediately implement software for their particular application without regard to
the details of the system interaction.
EXEC is National Semiconductor's real-time, multitasking executive for Series 32000 based applications. Its primary purpose is to simplify the task of designing application software and provides a base 'Jpon
which users can build a wide range of applicatio(1 systems. EXEC requires only 2K bytes of RAM and only
4K bytes of ROM and is fully compatible with National
Semiconductor's Series 32000 family and the Series
32000 development board family.
EXEC allows the user to monitor and control multiple
external events that occur asynchronously in real-
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EXEC executive is fully modular and can be readily
configured to suit application needs. It is both hardware and location independent, thus providing a fundamental base on which to build a wide range of applications systems. In addition, it provides a buslike
structure that helps to integrate software with the underlying hardware through predefined data structures
and interconnect procedures. This architecture ensures maximum standardization for both compatibility
and future expansion.
is supported for the most sophisticated of multitasking
systems.
Real-Time Speed-Because EXEC was hand-coded
in assembly language, several advantages with regard
to speed are gained. Task swapping, channel and
message management, and I/O interfacing are executed more quickly than could be expected of a system written in a higher level language.
Direct Interrupt Processing-The EXEC architecture employs interrupt channels which allow devicespecific interrupt handling routines to interface directly
with the interrupt source. This accomplishes servicing
of interrupts without the overhead of task swapping,
yet allows the operating system to maintain the integrity of the system. Combining this interrupt service architecture with a device-efficient nucleus results in an
operating system that better supports demanding,
real-time applications.
User Configurability-EXEC executive-based applications may be configured from a wide range of facilities, selecting only those that meet the specific requirements of the application system. The resultant
system contains only the modules necessary for its
use, allowing the EXEC executive to fit a wide range of
applications from small, special-purpose, dedicated
applications to large, general-purpose systems.
Event Driven-In the EXEC executive, each user task
exists in its own "closed environment"-a virtual processor. Each virtual processor can synchronize with external/internal occurrences through events. EXEC
supports a wide variety of events, including synchronization with task activities, external device operations,
and the real-time clock.
Memory Pool Manager-The EXEC executive has
an integral memory pool manager. This feature not
only reduces the amount of RAM required in an application system (potentially reduces board count), but
also allows active modules more buffer area within
any given space constraint.
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Features
Structured Environment-The EXEC executive and
its associated modules support and encourage modular, structured programming, thus providing a consistent structure from application to application, which allows experience gained and software written on one
system to be easily transferred to another. Frequently,
entire programs may be used in multiple applications,
even if different CPU boards are involved.
Hardware-Oriented Interface-The EXEC executive
provides an intertask and task/executive communications architecture that is similar to hardware communications. Instead of an array of "mailboxes" (or "message centers"), EXEC uses channels. This interface is
consistent throughout the range of facilities offered,
thus reducing the number of concepts to be learned,
providing greater control at the task level, and increasing the efficiency of the system and the programming
effort.
Wide Choice of CPUs-EXEC is compatible with the
full line of 32-bit Series 32000 CPUs offered. These
include the NS32008, NS32032, and the NS32C016.
Users will be able to move a NS32016 system:
• to an NS32008 for cost-effectiveness,
• to an NS32032 for increased computing power, or
• to an NS32C016 for low-power applications.
Time-Of-Day Clock-The EXEC executive has an integral system/time-of-day clock. Included is a realtime clock configurable to a resolution of 1ms. This
eliminates the need to allocate the extra memory otherwise required for this feature.
Small Nucleus-The EXEC nucleus was hand-coded
in assembly language rather than being compiled from
intermediate or high-level languages. The resulting
product is therefore smaller and allows the incorporation of more features within an optimum size.
Priority-Oriented Scheduler-The EXEC scheduler
ensures that the highest priority task that is ready to
execute is given control, so the system is responsive
to its external world. Dynamic reprioritization of tasks
Internal Structure
EXEC may be viewed as composed of a set of functions. These functions are:
1. Nucleus- performs task and channel management
and controls executing memory.
2. Timer Manager-performs time-dependent control.
3. Dynamic Task Dispatcher-performs dynamic creation and installation of tasks at run-time.
4. Dynamic Channel Controller-performs dynamic
creation and installation of software and interrupt
channels at run-time.
5. Memory Pool Manager-performs memory allocation and deallocation.
7-40
~----------------------------------------------------------------------,~
CD
The Timer Manager, Dynamic Task Dispatcher, Dynamic Channel Controller, and the Memory Pool Manager all operate under direction of the Nucleus, which
assigns tasks to run on the hardware CPU.
:::l.
• Intertask Communication
CD
1. RECV(W) -Receive data from a channel and,
optionally, wait for an event to occur.
2. SEND(W) -Send a message to a channel and,
optionally, wait for an event to occur.
3. SIGNL
-Synchronize with another task
through event flags; signal completion.
4. BLDSC -Build software channel.
• Interrupt Handling
1. INTEX
-Interrupt exit from executive.
2. BLDIC
-Build an interrupt channel.
• Memory Pool Management
1. ALLOC -Allocate a block of pooled memory.
2. DALOC -Deallocate memory back to pool.
• Timer Management
1. MRKT(W) -Mark a time delay and, optionally, wait
for an event to occur.
2. CMRKT -Cancel previously posted mark-time
event.
3. GTIMD -Get current time of day.
4. STIMD
-Set current time of day.
System Functions
EXEC controls CPU allocation by resolving conflicting
needs of individual tasks, and monitors external
events. The Event Manager, Task Manager, Channel
Manager, Memory Manager, and Timer Manager provide system facilities that are directly accessible from
the user task level. A representative sampling of system functions are summarized below:
• Task and Event Management
1. TSKBD -Build a task and schedule it to run.
2. SUSPD -Suspend a task.
3. GTPRI
-Get task priority.
4. STPRI
-Change run-time task priority.
5. WAITE
-Wait for an event or combination of
event to occur before resuming task
processing.
6.TSTEV
-Test the current state of an event.
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Ordering Information
VAX/VMS Environment
SYS32/20, SYS32/30 Environments
Order Number: NSW-EXEC-SRVM*
Shipping Configuration: Software on 1600 bpi magnetic tape (9-track VMS copy format). EXEC reference
manual.
Prerequisite: NSW-ASM-BRVM cross software package, at current revision level.
Order Number: NSW-EXEC-SLAF
Shipping Configuration: Software on SYS32 format
streamer tape cartridge. EXEC reference manual.
Prerequisite: SYS32/20 or SYS32/30 Development
System with current revision level software.
Documentation
VAX/UNIX Environment
EXEC ROMabie Real-Time Multitasking EXECUTIVE
Reference Manual. Included with software package.
May also be ordered separately.
Order Number: NSP-EXEC-M
Order Number: NSW-EXEC-SRVX'
Shipping Configuration: Software on 1600 bpi magnetic tape (UNIX tar tape format). EXEC reference
manual.
Prerequisite: NSW-ASM-BRVX' cross software package, at current revision level.
'Software license agreement must be signed prior to order entry.
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Section 8
Application Notes
Section 8 Contents
AB-26 Instruction Execution Times of FPU NS32081 Considered for Stand-Alone
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-27 Use of the NS32332 with the NS32082 and the NS32201 . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-383 Interfacing the NS32081 as a Floating-Point Peripheral. . . . . . . . . . . . . . • . . . . . . . . . . . .
AN-404 10 MHz, No Wait States NS32016 System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-405 Using Dynamic RAM with Series 32000 CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-406 Interfacing the Series 32000 CPUs to the MULTIBUS ........ . . . . . . . . . . . . . . . . . . . .
AN-464 Effects of NS32082 Memory Management Unit on Processor Through Put. . . . . . . . . .
AN-513 Interfacing Memory to the NS32532 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-524 Introduction to Bresenham's Line Algorithm Using the SBIT Instruction; Series 32000
Note 5..........................................................................
AN-526 Block Move Optimization Techniques; Series 32000 Graphics Note 2 .. .. .... ... . ..
AN-527 Clearing Memory with the 32000; Series 32000 Graphics Note 3. . . . . . . . . . . . . . . . . . .
AN-528 Image Rotation Algorithm; Series 32000 Graphics Note 4. . . . . . . . . . . . . . . . . . . . . . . . .
AN-529 80 x 86 to Series 32000 Translation; Series 32000 Graphics Note 6 . . . . . . . . . . . . . . . .
AN-530 Bit Mirror Routine; Series 32000 Graphics Note 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2
8-3
8-4
8-6
8-14
8-25
8-32
8-37
8-41
8-67
8-77
8-80
8-84
8-93
8-99
~
National Semiconductor
Application Brief 26
Systems & Applications Group
Instruction Execution
Times of FPU NS32081
Considered for
Stand-Alone Configurations
The table below gives execution timing information for the
FPU NS32081.
Operation
The number of clock cycles nCLK is counted from the last
SPC pulse, strobing the last operation word or operand into
the FPU, and the Done-SPC pulse, which signals the CPU
that the result is available (see Figure 1). The values are
therefore independent of the operand's addressing modes
and do not include the CPU/FPU protocol time. This makes
it easy to determine the FPU execution times in stand-alone
configurations.
The values are derived from measurements, the worst case
is always assumed. The results are given in clock cycles
(CLK).
Number of
Clock·Cycles
nClK
Add, Subtract
63
Multiply Float
37
Multiply Long
51
Divide Float
78
Divide Long
108
Compare
38
SPC
CLK
TL/EE/8760-1
FIGURE 1
8-3
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r---------------------------------------------------------------------------~
Use of the NS32332 with
the NS32082 and the
NS32201
National Semiconductor
Application Brief 27
Systems Applications Group
Care should be taken when the NS32332 is designed in a
system with the NS32201 and the NS320B2. Two configurations need to be considered, one with MMU and one without.
In a configuration without an MMU, TCU and CPU both run a
four clock cycle bus (Figure 1). The ROY signal is the only
incompatible signal between the CPU and TCU and therefore the ROY output of the TCU should not be directly connected to the ROY input of the NS32332. The NS32332
samples its ROY input in the middle of T3 while the
NS32201 asserts its ROY output shortly after the middle of
T2 and removes it shortly after the middle of T3, thus the
NS32332 ROY input hold time (tROYh) is not met. To meet
tROYh, the ROY output of the NS32201 should be clocked
by the rising edge of the CTTL using a Ootype flip-flop
(74AS74) and then taken to the NS32332. It should be noted that the NS32332 outputs the data in a write cycle in T3
unless OT/SOONE pin is sampled low on the rising edge of
the reset in which case the data is output during T2. The
OT/SOONE pin is implemented as of revision B of the
NS32332.
In a configuration with MMU the NS32332 runs a four clock
cycle bus while the NS320B2 runs a five cycle bus. Two
options can be exercised.
The first option is extending the NS32332 bus cycle to five
clocks by adding a blind wait state that bypasses the
NS32201 (Figure 2). This configuration generally requires
the minimum hardware modification for a 320xx based design to run the NS32332. Here the NS32201 output Signals
can be used to interface the NS32332 and the NS320B2 to
the memory or 1/0. Additional wait states can be inserted by
clocking the ROY output of the TCU.
The second option is to have the NS32332 run a four clock
cycle bus (Figure 3). In this configuration the NS32201 output Signals cannot be used to interface the NS32332 to
memory or 1/0; they can only be used to interface the
NS320B2 to the memory. In this configuration a revision N
of the NS320B2 should be used.
TCU states
T1
T2
T3
T4
NS32332 states
T1
12
T3
T4
PHil
PHIU
74AS74
NS32332
ADS output
WAIT STATES IF NEEDED-TCU ROY output
TCU ROY a.OCKm BY em (Q)
TLlEE/8761-2
] WEETS THE NS32332 SPEC
TCU TSO
TCU
iiii. ViR
TCU
DOE
TL/EE/8761-1
FIGURE 1. NS32332, TCU Timing Diagram, No Wait State, No MMU
B-4
.
~
T1
TCUatat.s
12
NS32082 ....U statls
T1
T....u
T2
N532332statlS
T1
T.... U
T3
"
"
T3
m
"
"
"
N
.....
PHil
PHI 0
14532332 ADS output
..wu iiiV output
14532332 RDYlnput(bllnd walt)
TCURDYoutput
Teu RDY CLOCKED BY
em
TCUTSOoutput
Teu
Rii,WR outputs
TLlEE/8761-3
FIGURE 2. NS32332, MMU, TeU Timing Diagram when NS32332 is Run with 1 Wait State
Similar to Timing Diagram of NS32332 Adapter to D832000
Rii,Wi
TCUslgnals
TSO
._.:I....-+-_+-,./
ODE
TL/EE/8761-4
FIGURE 3. NS32332, MMU, TeU Timing Diagram with No Wait State
8-5
~
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r----------------------------------------------------------------------------,
~ Interfacing the NS32081 as
cc
a Floating-Point Peripheral
National Semiconductor
Application Note 383
Microprocessor Applications
Engineering
This note is a guide for users who wish to interface the
NS32081 Floating-Point Unit (FPU) as a peripheral unit to
CPUs other than those of the Series 32000 family. This is
not a particularly expensive procedure, but it requires some
in-depth information not all of which is available in the
NS32081 data sheet. Four basic topics will be covered here:
Floating-point operands need not be held in registers; they
may be supplied externally as part of the instruction sequence. Integer operands (appearing in conversion instructions) and values being transferred to or from the FSR must
be supplied externally; they cannot be held in Floating-Point
registers FO-F7.
An overview of the architecture of the NS32081 as seen
in a stand-alone environment.
The protocol used to sequence it through the execution
of an instruction.
1.2 INSTRUCTION SET AND ENCODING
The encodings used for NS32081 instructions are shown in
Figure 2. They fall within two formats, labeled from Series
32000 tradition "Format 9" and "Format 11". These formats are distinguished by their least-significant byte (the "10
Byte"). Execution of an FPU instruction starts by passing
first the 10 Byte and then the rest of the instruction (the
"Operation Word") to the FPU.
Fields within an instruction are interpreted by the FPU in the
same manner as documented in Chapter 4 of the Series
32000 Instruction Set Reference Manual, with the exception
of the 5-bit General Addressing Mode fields (gen1, gen2).
Since the FPU does not itself perform memory accesses, it
does not need to use these fields for addressing calculations. The only use it makes of these fields is to determine
for each operand whether the value is to be found internal
to the FPU (that is, within a register FO-F7, or whether it is
to be transferred to and/or from the FPU. See Figure 3. A
value of 0-7 in a gen field specifies one of the FloatingPoint registers FO-F7, respectively, as the location of the
corresponding operand. Any greater value specifies that the
operand's location is external to the FPU and that its value
will be transferred as part of the protocol. Any non-floating
operand is always handled by the FPU as external, regardless of the addressing mode specified in its gen field. It is
illegal to reference an odd-numbered register for a doubleprecision operand. If an odd register is referenced, the results are unpredictable.
Special guidelines for connecting and programming the
NS32081 as a peripheral component.
A sample application of these guidelines in the form of a
circuit interfacing the NS32081 to the Motorola 68000
microprocessor.
References are made here to the NS32081 data sheet and
the Series 32000 Instruction Set Reference Manual (Publication #420010099-001). The reader should have both
these documents on hand.
1.0 Architecture Overview
1.1 REGISTER SET
The register set internal to the NS32081 FPU is shown in
Rgure 1. It consists of nine registers, each 32 bits in length:
FSR
The Floating-Point Status Register. As given in the
data sheet, this register holds status and mode information for the FPU. It is loaded by executing the
LFSR instruction and examined using the SFSR instruction.
FO-F7 The Floating-Point Registers. Each can hold a single 32-bit single-precision floating-point value. To
hold double-precision values, a register pair is referenced using the even-numbered register of the pair.
++-
32
~
IFloating PI. Status I FSR
32
~
Fo1...._ _ _ _ _...J
F11
~======~
::I~==========~
F41
:=:::============~
Fsi
:========~
Fsi
1.3 PINOUT
The FPU is packaged in a 24-pin DIP (see Figure 4). The pin
functions can be split into two groups: those that partiCipate
in the communication protocol between the FPU and the
host system, and those that reflect the familiar requirements
of LSI components.
The protocol uses the following pins of the FPU:
00-015
The 16-bit data bus. The DO pin holds the
least-significant bit of data transferred on the
bus.
SPC
A dual-purpose pin, low active. SPC is pulsed
low from the host system as the data strobe
for bus transfers. SPC is pulsed low by the
FPU to signal that it has completed the internal execution phase of an instruction.
F7!:==============:
FIGURE 1. FPU Registers
8-6
r--------------------------------------------------------------------,~
Z
1.0 Architecture Overview (Continued)
STO, STl
cA
The status code. This 2-bit value is sampled
by the FPU on the falling edge of SPC, and
informs it of the current protocol phase. STO
is the least-significant bit of the value. The
need filled by the status code is most relevant to Series 32000-based systems, where it
serves to allow retry of aborted instructions
and to disambiguate the protocol when the
SPC signal is bussed among multiple slave
processors. In microprocessor-based peripheral applications, the status code can generally be provided from the CPU's address
lines.
RST
VCC
The clock input. This is a TIL-level square
wave which the FPU uses to sequence its internal calculations.
The reset input. This signal is used to reset
the FPU's internal logic.
The 5-volt positive supply.
GNDB, GNDl The grounding pins. GNDB serves as ground
for the FPU's output buffers, and GNDl is
used for the rest of the on-chip logic.
FPU Internal Register: Fn, n=O ... 7
long Floating = Even Register Only
001 1 1 1 1 0
~----------~--------~}\
OPERATION WORD
ClK
o
8 7
i
The pins providing for standard requirements are:
T
)
ID BYTE
10111xlxlxl
Format 9: lFSRISFSR/Conversions
111 X 1 X 1 X 1 xl
o
External to FPU
Note: All
1 1 110
'-----~-----'}
OPERATION WORD
non~floating
operands are always external.
FIGURE 3. FPU Addressing Modes
ID BYTE
Format 11: Movement/Calculation
FIGURE 2. FPU Instruction Formats
16 BIT
DATA BUS
AID
SERIES
32000
CPU
0-15
STO
S11
SPC
...
Vee
010
00-15
r,
STO NS32081
S11
FPU
SPC
rrr
RST
ClK
09
STO
08
S11
07
SPC
06
011
012
05
NS32081
FPU
04
RST CTn
013
014
03
NS32201
TCU
02
015
15
01
TL/EE/B3BB-l
DO
GNDl
ClK
13
12
Top View
FIGURE 4. NS32D81 FPU Connections
8-7
RST
GNDB
TL/EE/B3BB-2
C»
Co)
2.0 Protocol
The FPU requires a fixed sequence of transfers ("protocol")
in its communication with the outside world. Each step of
the protocol is identified by a status code (asserted to the
FPU on pins sTO and sT1) and by its position in the sequence, as shown in Figure 5.
Step 7 is, like Step 3, optional and repeatable depending on
the instruction. Any external result of an instruction is read
from the FPU in this step, least-significant word first. If the
result is a 1-byte value, it is presented by the FPU on the
least-significant half of the bus (00-07).
Note: If in Step 6 the FPU indicates that an error has occurred, it is permissible, though not necessary, to continue the protocol through Step 7. No guarantee is
made regarding the validity of the value read, but continuing through Step 7 will not cause any protocol
problems.
If at any time within the protocol another 10 byte is sent
(sT = 11), the FPU will prepare itself internally to execute
another instruction, throwing away the instruction that was
in progress. This is done to support the Abort with Retry
feature of the Series 32000 family.
Status Combinations:
11:
Write 10 Byte
01:
Transfer Operation/Operand
10:
Read Status Word
Step
1
2
3
4
5
6
7
Status
Action
11
CPU sends 10 Byte on least-significant
byte of bus.
01
CPU sends Operation Word, bytes
swapped on bus.
01
CPU sends required operands, gent
first, least-significant word first.
xx
FPU starts internal execution.
xx
FPU pulses SPC low.
10
CPU reads Status Word (Error/Comparison Result).
01
CPU reads result (if any), least-significant word first.
Because of this feature, however, there is an important consideration when using the FPU in systems that support multitasking: the operating system must not allow a task using
the FPU to be interrupted in the middle of an instruction
protocol and then transfer control to another task that is
also using the FPU. The partially-executed instruction would
be thrown away, leaving the first task with a garbage result
when it continues. This situation can be avoided easily in
software but, depending on the system, some cooperation
may be required from the user program. Other solutions involving some additional hardware are also possible.
FIGURE 5. FPU Instruction Protocol
Steps 1 and 2 transfer the instruction to the FPU. Step 1
transfers the first byte of the instruction (the 10 Byte) and
Step 2 transfers the rest of the instruction (the Operation
Word). In Step 2, the two bytes of the Operation Word must
be swapped on the bus; i.e. the most-significant byte of the
Operation Word must be presented on the least-significant
byte of the bus.
Step 3 is optional and repeatable depending on the instruction. It is used to transfer to the FPU any external operands
that are required by the instruction. The operand specified
by gen t is sent first, least-significant word first, followed by
the operand specified by gen2. If an operand is only one
byte in length, it is transferred on the least-significant half of
the bus.
The FPU initiates Step 4 of the protocol, internal computation, upon receiving the last external operand word or, if
there are no external operands, upon receiving the Operation Word of the instruction. During this time, the data bus
may be used for any purpose by the rest of the system, as
long as the SPC pin is kept pulled up by a resistor and is not
actively driven.
Step 5 occurs when the FPU completes the instruction. The
FPU pulses the SPC pin low to acknowledge that it is ready
to continue the protocol. This pulse is called the "Done
pulse". The bus is not used during this step, and remains
floating.
In Step 6, the FPU is polled by reading a Status Word. This
word indicates whether an exception has been detected by
the FPU. In the Compare instruction (CMPf), it also displays
the relationship between the operands and serves as the
result. This transfer is mandatory, regardless of whether the
information presented by the FPU is intended to be used.
See Figure 3-6 of the data sheet.
3.0 Interfacing Guidelines
There are some special interfaCing considerations that are
required (see Figure 6):
1. The edges of the SPC pulse must have a fixed relationship to the clock signal (ClK) presented to the FPU.
When writing information to the FPU, the pulse must start
shortly after a rising edge of ClK and end shortly after
the next rising edge of ClK. Failing to do so can cause
the FPU to fail, often by causing it to freeze and not generate the Done pulse. This synchronous generation of
SPC is also important when reading information from the
FPU, but the SPC pulse is allowed to be two clocks in
width. These requirements will be expressed in future
Ns320B1 data sheets as a minimum setup time requirement between each edge of the SPC pulse and the next
rising edge of ClK, currently set at 40 nanoseconds on
the basis of preliminary characterization. The propagation
delay in generating SPC through a Schottky flip-flop (e.g.
74574) and a low-power Schottky buffer (e.g. 74ls125A)
is therefore acceptable at 10 MHz. ls technology is recommended for the buffer to minimize undershoot when
driving SPC.
2. After the FPU generates the Done pulse, it is necessary
to leave the SPC pin high for an additional two cycles of
ClK before performing the Read Status Word transfer.
3. After performing the Read Status Word transfer, it is necessary to wait for an additional three cycles of ClK before reading a result from the FPU.
B-B
4.0 An Interface to the MC68000
Microprocessor
flip-flop within the Done Detector block. When the 68000
performs a Read cycle from the address that generates the
POLL select signal, the contents of the flip-flop are placed
on data bus bit D15. Since this is the sign bit of a l6-bit
value, the 68000 can perform a fast test of the bit using a
MOVE.w instruction and a conditional branch (BPL) to wait
for the FPU.
4.1 HARDWARE
A block diagram of the circuitry required to interface the
MC68000 MPU to the NS32081 is shown in Figure 7.
First the easy part. Direct connections are possible on the
data bus, which is numbered compatibly (DO-D15 on both
parts), the status pins STO-STl (connected to address
lines A4-A5 from the 68000), and the clock (CLK on both).
The system reset signal (RESET to and/or from the
MC68000) should be synchronized with the clock before
presenting it as RST to the FPU.
All that remains to be done is to generate SPC pulses that
are within specifications whenever the 68000 accesses the
FPU, and to detect the Done pulse from the FPU in a man·
ner that will allow the 68000 to poll for it.
The approach selected for generating SPC pulses uses an
address decoder that recognizes two separate address
spaces; one to transfer information to or from the FPU
(XFER), and one to poll for the Done pulse (POLL).
The schematic for the SPC generator and the Done pulse
detector is given in Figures 10a and 10b. The flip-flop labeled SPC generates the edges of the SPC pulse (on the
signal SPCT). The timing chain (TA, TB) provides the enable
control to the buffer driving SPC to the FPU, as well as the
signal to terminate the SPC pulse (either TB or TC, depending on the direction of the data transfer). Note that the timing chain assumes a full·speed memory cycle of four clocks
in accessing the FPU, and will fail otherwise. The circuit
generating the Data Acknowledge signal to the 68000
(DTACK, not shown) must guarantee this. In any system
that must use a longer access, some modification to the
timing chain will be necessary.
The 68000 signals AS (Address Strobe) and R/W (Read /
not Write) are used to generate SPC timing.
The flip-flop labeled DONE (Figure 10b) is the Done pulse
detector. It is cleared by performing a data transfer into the
FPU and is set by a Done pulse on SPC. A buffer, enabled
by the POLL select signal, connects its output to data bus
bit 15.
Figure 8 shows the timing generated when the 68000 is
writing to the FPU. The SPC pin is kept floating (held high by
a pullup resistor) until bus state S4, at which point it is pulled
low. On the next rising edge of CLK, SPC is actively pulled
high, and is set floating afterward. It is not simply allowed to
float high, as the resulting rise time can be unacceptable at
speeds above about 4 MHz. A timing chain, required due to
the 10-MHz 68000's treatment of its AS strobe, generates
the signals TA, TB and TC, from which the SPC signal's
state and enable are controlled.
4.2 SOFTWARE
Some notes on programming the FPU in a 68000 environment:
1. The byte addressing convention in the 68000 differs from
that of the Series 32000 family. In particular, a byte with
an even address is transferred on the most-significant
half of the bus by the 68000, but the FPU expects to see
it on the least-significant byte. When transferring a single
byte to or from the FPU, either do so with an odd address
specified, or transfer the byte as the least-significant half
of a 16-bit value at an even address.
2. The 68000 transfers 32-bit operands by sending the
most-significant 16 bits first. The FPU expects values to
be transferred in the opposite order. Make certain that
operands are transferred in the correct order (the 68000
SWAP instruction can be helpful for this).
Figure 9 shows the SPC timing for reading from the FPU.
The basic difference is that SPC remains active for two
clocks, so that the FPU holds data on the bus until it is
sampled by the 68000. Again, SPC is actively driven high
before being released.
Note: Although SPC must be driven high before being released, it must not be actively driven for more than
two clocks after the trailing edge of SPC. This is because the FPU can respond as quickly as three
clocks after that edge with a Done pulse.
A simpler scheme in which the SPC pulse is identical for
both reading and writing (l-clock wide always, but starting
% clock later with CLK into the FPU inverted) was considered, but was rejected because the data hold time presented by the 68000 on a Write cycle would be inadequate
at 10 MHz.
Any SPC pulse appearing while the XFER Select signal is
inactive is interpreted as a Done pulse, which is latched in a
A sample program that sequences the FPU through the execution of an ADDF instruction is listed in Figure 11. As this
example is intended for clarity rather than efficiency, improvements are possible. The XFER select is assumed to
be generated by addresses of the form 06xxxx (hex) and the
POLL select is assumed to be generated by addresses of
the form 07xxxx.
8-9
10
14\
OPERANDS
OPCOOE
'
;
(DONE)
1
, ' - - - - - - - - . , - - - . : t:;\
\lI SPC PULSE WIDTH: CRITICAL
WHEN WRITING INTO FPU. MUST BE 1 CLOCK WIDE
ClK
_
SPC
(
~=i
W
RESULT
STATUS
'-r'
=r
AT lEAST 2 CLOCKS HERE
® AT LEAST 3 CLOCKS HERE
® !!!LLONG
DELAYS BETWEEN
SPC PULSES ( > 10 MIll/SEC.'
./
BUG IN REVISION D.
TL/EE/8388-3
FIGURE 6. Interfacing to FPU: Cautions
..
,
A A
MC68000
A'-~3
IJL
ADDR. BUS
Ai
R/iii
10.0-..
+
XFER
..A
,
,
PPOll
D
SPC
TIMING
GEN.
ADDR. STROBE
....
STO. ST1
NS32081
FPU
SPC
REAO/WRITE
I
ClK
RESET
~
~
DSC
t ..........
1 -Q
--
ClK
J
RST
LD
Do - 0"
....
....
SYSTEM
RESET
Do -
4
"DONE"
DETECTOR
0,.
....
....
...
~
:s.7
0"
.
,
)
DATA BUS
TUEE/8388-4
FIGURE 7_ 68000-32081 Interface Block Diagram
8-10
ClK
ADDR
~-<",,
____
ST_n_AN_D_SE_l_EC_T_VA_Ll_D_ _- - ' } - - -
R/W
TA
I
\
I
TB
I
TC
SPC
DATA
--------,
-------------<:
FIGURE 9. 68000 Read from FPU
8·11
VALID
\...
\...
r}-
TLlEE/B3BB-6
('I)
co
('I)
z•
c(
74L5D4
+
+
TO
AS
Q
TC
745112
TC
XFER
ii
Q
RST
CLKin
'::"
74500
+
o
74574
5PC
5PC
(TO FPUj
TL/EE/B3BB-7
FIGURE lOa. Schematic: SPC Timing Generator
74LS04
SPC
>---d~----r~
74lS125A
XFER >-__________..1
DONE
015
>----+ (BUS)
R
ii
AS
roll>-------------------4-----~_'
74LS02
74lS04
RESET _~.......---. 0
S
Q
74S74
RST
R
ii
------------4..-------------. RST
1-+-...
L.-~"'"
(TO FPU)
ClK
~
________________________________________
~ClK
(TO FPU)
FIGURE lOb. Schematic: DONE Detector and RESET Synchronizer
8-12
TL/EE/B3BB-B
Register Contents:
AO
Al
A2
A3
=
=
=
=
00070000
00060010
00060020
00060030
Address
Address
Address
Address
of DONE flip-flop.
for ST=l transfer (Transfer Operand) •
for ST=2 transfer (Read Status Word).
for ST=3 transfer (Broadcast ID).
DO
Dl
D2
D3
D4
D5
D7
=
=
=
=
OOOOOOBE
00000184
3FBOOOOO
3F800000
ID byte for ADDF instruction.
Operation Word for ADDF. (Note bytes swapped.)
First operand = 1.0.
Second operand = 1.0.
Receives Status Word from FPU.
Receives result from FPU.
Scratch register (for DONE bit test).
START MOVE.W
MOVE.W
SWAP
MOVE.L
SWAP
SWAP
MOVE.L
SWAP
DO,
Dl,
D2
D2,
D2
D3
D3,
D3
POLL MOVE.W
BPL
(AO),D7
POLL
Check the DONE flip-flop,
loop until FPU is finished.
(DONE bit is sign bit, tested
by the MOVE instruction.)
MOVE.W
MOVE.L
SWAP
(A2),D4
(Al),D5
D5
Read Status Word.
Read result.
Swap halves of result.
(A3)
(Al)
(Al)
(Al)
Send ID byte.
Send Operation Word.
Send operands. The swapping
is included because the
FPU expects the leastsignificant word first.
(Can be avoided, with care.)
FIGURE 11. Slngle·Preclsion Addition (Demo Routine)
8-13
~.---------------------------------------------~~~
~ 10 MHz, No Wait States
~ NS32016 System
National Semiconductor
Application Note 404
Microprocessor Applications
Engineering
INTRODUCTION
Recent microprocessor applications such as high resolution
graphics, multiuser workstations, data communication, industrial automation, etc. have placed growing demands on
microprocessor throughputs. Higher throughputs, together
with increasing complexity of microprocessor systems, require slave support in addition to high speed, powerful microprocessors.
the memory for about 215 nanoseconds following the leading edge of the write strobe. It is assumed that the Address
lines are valid at the memory pins at the time the read or
write strobe goes active.
SRAM INTERFACE:
The Series 32000® Microprocessor family serves the needs
of high end microprocessor applications. The NS32016
Central Processing Unit (CPU) has a powerful register and
instruction set. The NS32082 Memory Management Unit
(MMU) and the NS32081 Floating-Point Unit (FPU) function
as slave processors for the CPU. All the chips in the family
run at 10 MHz. Together, the chips provide the throughput
required by high end microprocessor applications. This application note discusses the design considerations for building a 10 MHz NS32016 system with no wait states.
Series 32000 Chip Set:
The NS32016 system described here, uses the Series
32000 chip set consisting of:
1. The NS32016 Central Processing Unit (CPU)
2. The NS32082 Memory Management Unit (MMU)
3. The NS32081 Floating-Point Unit (FPU)
4. The NS32201 Timing Control Unit (TCU)
5. The NS32202 Interrupt Control Unit (ICU)
Details of the five chips are provided in the Series 32000
Data Book. Figure 1 illustrates the interconnections of a
simple NS32016 based system capable of running at
10 MHz without wait states. As shown in Figure 1, the CPU,
MMU and FPU are interconnected on a multiplexed Address/Data Bus. The TCU provides the clocks and the control signals required by the system. The multiplexed bus is
separated into Data and Address buses by using bidirectional Data bus drivers and fall-through Address latches. The
ICU, being a peripheral, is interfaced to the demultiplexed
Address and Data buses. The ICU Status input (ST1) is driven by a logical combination of ST1 from the CPU and address line A5. This allows the CPU to read both the INTA
and RETI vectors from the SVCT register of the ICU.
DESIGN CONSIDERATIONS
The deSign of a 10 MHz Microprocessor system with no wait
states requires system memory to run at comparable
speeds. Typically, system memory consists of Read Only
Memory (ROM) and Read/Write or Random Access Memory (RAM). A 10 MHz, NS32016-based system functioning
without wait states requires careful memory timing consideration.
A read cycle without wait states requires data from memory
to be valid prior to the falling edge of the PHI2 clock during
the T3 state of the CPU. This allows about 155 nanoseconds following the leading edge of the read strobe for data
to be stable. In a memory write cycle, the data is available to
With high speed, 8K x 8-bit Static RAMs (SRAMs) such as
the NMC6264s, which have a 120-nanosecond maximum
access time, an interface without wait states is feasible. Besides requiring no wait states, SRAMs do not require the
refresh circuitry that Dynamic RAMs (DRAMs) need. Neither
do they require the error checking and correcting circuitry
that DRAMs need for correcting soft errors. The timing diagrams for SRAM Read and Write cycles with the MMU are
illustrated in Figures 4 and 5 respectively. The SRAMs are
organized into even and odd banks. The Write Enable (WE)
Signals for the SRAMs are generated by logically combining
address line AO and HBE with the WR signal from the TCU.
Both even and odd SRAM banks are always enabled during
Read cycles.
EPROM INTERFACE:
With current technology, EPROMs up to 64-Kbyte densities
are available. In particular, the 27128 type EPROMs are
available with 150-nanosecond maximum access times.
These EPROMs can be used in the NS32016-based system
without wait states. The timing diagram for the EPROM
Read cycle, with the MMU is illustrated in Figure 3. The
Output Enable (OE) inputs to the EPROMs are connected to
the RD signal. This will cause both even and odd bytes of
the set of EPROMs to be enabled for a byte or word read
from the CPU. This does not affect the data as the CPU will
read the appropriate byte(s). A single DMPAL16L8A device
is used to generate all the required chip select Signals.
I/O INTERFACE:
CPU accesses to the serial communications devices require
the insertion of at least two wait states. This is accomplished by activating the TCU WAIT2 input during such accesses.
Furthermore, the leading edges of the Read and Write
strobes are delayed by one clock cycle. This is necessary
since the time delays of the Read and Write strobes from
Address Valid, required by the communications devices, are
larger than the delays provided by the 32000 chip set during
normal bus accesses. The system uses two NS16450s. This
facilitates its use in stand-alone, stand-aside or transparent
configuration. The two NS16450s have their oscillator pins
(XTAL 1 and XTAL2) connected to the crystal circuit as illustrated in Figure 1. The two NS16450s are interfaced to standard RS232C communication ports with jumpers. The jumpers allow the configuration of either port as a data-terminal
or as a data-set.
8-14
..--
+5V
~~
10 k.o.
EXT. RE
ST3
STO
U/S
HilO~F~
PFS l - I A23
30~
r°t:-p.o.
XIN
XOUT
+5(t
~
'f
Ul
~
WAIT
...
Y
r
4-:J-
HOLD
L
....... ST3
A231--
I:::
~ST1
STO
1=
L.....-
t::
L.-
~ u/S
1=
A161=
AD151--
PFS
I--
GNDl
GNDB
NS320S2
MMU
I:::
1=
1=
NS32201
TCU
FClK I PER
CWAIT
PHil
WAITS
PHI2
WAIT4
ROY
RSTO
WAITl
TSO
I-WAIT2
ODIN
iIDl--
ADS
VIR
NS320S1
FPU
~10k.o.
~_
.--.
SPC
RST
1=
~
~ lA4
RST/ABT
ADS
2Yl1=
lY41=
~]Al
... lG
rrrl= A16
2G....,
A16
~
A15 ~ SO
~
I-DO I--
~ ClK
~
HOLD
llIi1N
,--t
r-i
r--t
PHil
PHI2
ROY
RRSTI
~
A24
oo~
__
~
4 lSO
74AlS32
AD15
HlDAO
.....
"....
"
~+5V
EXT NM
.....
~_+5V
74LSOO
I~
-
J
+5V
)JlSDS
~ru~
I
°
~~h
F
ClK
Cl
ClK
Cl
ClK
Cl
~
~ .!p ~
~
~
~
~
AD
AS
BSI-~[
0-15
1=
1=
AD7
~
ADO
1=
1=
!QI=
OCh
~ ~1
~
~
~
A7
G
ADS
l..JvvIr..+ + 5V
s0l=
~
~
AS
OCh
AD7 ~ SO
~
A15
1=
1=
~ !P ~ !Q~
....
INT
~
G
115
PAY
S0l=
~
~
ADS
~M
AT/sPC
2Al
~
I-
,.-.AO -23
2Y41= A23
A23 ~ 2M
~
STO
1=
ADD I -
FlT
~FlT
1-+
~
I--
I:::
~
I-1=
I-1=
I--
0151-
1=
_AOll. I -
PHil RSTI ABT
PHI2
ADS
ROY
HlDA
Ar/SPC
HOLD
ODIN
IlO
INT
NMI
HBE I--
+5V
1=
1=
1=
RWEN/SYNC
cm I - DBE I--
r1
~
t::
ST
A16 1=
AD15
1=
BBG
1000P~ i'fl ~F
:--+ RSTI
~
NS32016
CPU
+5V
20 MHz
Fi
IBll=
DB
G
DlRI-~
AS
BS I - 07
t::: GAl
1=
1=
IBl 1= DO
DlR I - -
em
HBE
RST
Ro
ViR
6TSO
TUEE/B506-7
FIGURE 1. Circuit Diagram for the 10 MHz No Walt States NS32016 Based System
POP-NY
II
AN-404
AlSO
iii[
iii
~
iiSi
Sfl
'"
cm.>--/cu:-
:r
uu
At--.,AO
AIL--fAO
A1L--fAO
AI~AO
TL/EE/8506-8
FIGURE 1. Circuit Diagram for the 10 MHz No Wait States NS32016 Based System (Continued)
One port can be used to communicate with a host computer. The other can be used to interface the system to a terminal. If MON16 software is used, it is possible to communicate from the terminal to a host computer such as a National Semiconductor SYSI32™ or a VAXTM. Files stored in the
host can be down-loaded into the NS32016-based system
memory and executed at 10 MHz without wait states.
The Non-Maskable Interrupt signal (NMI) is used to return
from "runaway" programs to the monitor without destroying
the contents of the Program Counter and Processor Status
Register. The circuit shown in Figure 1 provides an NMI
pulse signal to the CPU.
PAL16LBA
Part #
Chip Select Generation
National Semiconductor
A23 A22 A2l A20 A19 AlB A17 A16 A15 GND
A14 SICU CSRl CSR2 CSR3 CSR4 CSIO AB CSE VCC
ICSE = IA23 • IA22 • IA2l • IA20 • IA19 • IA1B • IA17 • IA16 • IA15
ICSRl = IA23 • IA22 • IA2l • IA20 • IA19 • IA1B • IA17 • IA16 • A15
ICSR2 = IA23 • IA22 • IA2l • IA20 • IA19 • IA18 • IA17 • IA16 • A15
ICSR3 = IA23 • IA22 • IA2l • IA20 • IA19 • IA18 • IA17 • A16 • IA15
ICSR4 = IA23 • IA22 • IA2l • IA20 • IA19 • IA18 • IA17 • A16 • IA15
ICSIO = A23 • A22 • A2l • A20 • A19 • AlB • A17 • A16 • A15 • IA14
ISICU = A23 • A22 • A2l • A20 • A19 • A18 • A17 • A16 • A15 • A14 •
•
•
•
•
IA14
A14
IA14
A14
IA8
FIGURE 2. PAL Equations in PALASMTM Format
CONFIGURATION SWITCHES:
RS232C JUMPER CONNECTIONS:
Dip switches have been used in the circuit for system configuration as illustrated in Figure 1. The CPU reads them at
power-on or system reset to set the baud rate of the 1/0
ports and the CPU configuration register. Switches S1, S2,
S3 and S4 set the baud rate. Table I lists the various baud
rates possible with MON16 software. Switch S5 indicates
the presence of an FPU in the system and S6 indicates the
presence of an MMU in the system [fable II).
TABLE I
If a particular port in the system is to be connected to a
terminal, the associated jumpers need to be configured for a
Data Set. With reference to Figure 1, the jumper connections for a Data Set configuration are as follows:
S4
S3
S2
S1
Baud Rate
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134
110
75
50
a-c, b-d, e-g, f-h, i-j, k-1.
If the port is to be connected to a host computer, the associated jumpers need to be configured for a Data Terminal.
The jumper connections for a Data Terminal configuration
are as follows:
a-b, c-d, e-f, g-h, i-j, k-1.
Note: a-b
S5
Slave Processors
ON
ON
OFF
OFF
ON
OFF
ON
OFF
MMU and FPU
MMU
FPU
neither
connect node 'a' to node ·b·.
MEMORY MAP
The memory map of the system described in this note is
slightly different from the memory map of the 0832016 CPU
board. This has been done to simplify the chip-select generation logic. This requires minor changes to some 'equate'
statements in the MON16 modules in addition to the I/O
drivers changes to support the NS16450s instead of the
8251s. Figure 2 shows the PAL equations. The memory
map is shown in Table III.
TABLE III
TABLE II
S6
~>
8-17
Devices
Memory Locations
EPROMs
SRAMs
Serial Port 1
Serial Port 2
ICU-Registers
CNFG Switches
$000000-$007FFF
$00BOOO-$017FFF
$FFBOOO-$FFBOOF
$FFB01 0-$FF801 F
$FFFEOO-$FFFE3F
$FF8003
...,.
o
z
ZI
.j:o.
C
( DUMMY READ CHAR PROCEDURE )
R D C H R
RDCHR: • PROC
; PROCEDURE RDCHR (WAIT,TRM)
RD_CHR: .BLKB
; PROCEDURE VALUE
RD_WAIT :.BLKB
; WAIT/NOWAIT FLAG
RD_TRM: •BLKB
TERMINAL NUMBER
•RETURNS
.BLKW
RETURN CHR,CHR-JRDY FLAG
.VAR [Rl,R2]
.BEGIN
addr usrtl,rl
Rl: ADDRESS OF TRMINAL A
CMPQB TRMA,RD_TRM
IF TRMINJ\LNUM < > 0 THEN
BEQ
RDCHRLP:B
addr usrt2,rl
Rl: ADDRESS OF TRMINAL B
RDCHRLP:
DO WHILE IN~DY=O AND RD_WAIT=TRUE
tbitb iDL-rdy,usrtoff(rl)
INPUT IN~DY
BFS
RDCHR3:B
FOR DEBUG ONLY···
RDCHR3:B
BR
CMPQB TRUE, RD_WAIT
BEQ
RDCHRLP
END;
BR
RDCHREX:B
RDCHR3: MOVB O(Rl),RD_CHR ; RDCHR;=USART DATA
; RD_WAIT :=TRUE
MOVQB TRUE,RD_WAIT
RDCHREX:
.ENDPROC
P R C H R
FUNCTION -
( PRINT CHARACTER )
SEND ONE CHARACTER TO TERMINAL
CALLING SEQUENCE PRCHR(ENDF,WAIT,CHR,TRM)
ENDF/WAIT
BOOLEANO
CHR TRM
PRCHR: •PROC
WAIT_PR:.BLKB
CHR PR: • BLKB
IN/OUT ON INPUT FLAGE WAIT TO END OF OPERATION
OR REURN
ON OUTPUT INDICATES END OF OPERATION
CHARACTER INPUT CHARACTER TO BE PRINTED
INTEGER
INPUT TERMINAL NUMBER
; WAIT : BOOLEAN
; ASCII CHR
8·23
.j:o.
TRLCHR:.BLKB
TERMINAL NUMBER
•RETURNS
.BLKB
OUTPUT WAIT WAIT:BOOLEAN
.VAR
[Rl,R2]
.BEGIN
addr usrtl,rl
;Rl: ADDRESS OF TERMINAL A
CMPQ.B TRMA, TRLCHR
;IF TERMINALJUM<>O THEN
BEQ.
PRCHRLP:B
addr usrt2, rl
Rl: ADDRESS OF TERMINAL B
PRCHRLP:
tb1tb out __rdY,usrtoff (rl) ;IF TX-RDY = 0
BFS
PRCHR3:B
;THEN
BR
PRCHR3:B
;···DEBUG ONLY"·
CMPQ.B FALSE, WAIT__PR
IF WAIT THEN REPEAT
BNE
PRCHRLP
BR
PRCHREX:B
; ELSE WAIT:=FALSE
PRCHR3: MOVB CHR-PR,O (Rl)
MOVQ.B TRUE, WAIT__PR
;ELSE WRITE (DATA-PORT, CHR)
CONCLUSION
This application note describes a method of designing a 10MHz, no-wait-state NS32016-based system with off-theshelf memory and I/O chips. The system has a powerful
instruction set, suitable for high level language compilers.
With available cross-support software (NSX16™) and firmware (MON16), the NS32016 system can be used to com-
municate with a host computer such as a SYS/32. Programs can be written in high level languages such as C on
the SYS/32. These programs can then be compiled and
assembled to be down-loaded into the NS32016-based system memory to be executed.
8-24
l>
z
National Semiconductor
Application Note 405
Microprocessor Applications
Engineering
Using Dynamic RAM With
Series 32000® CPUs
Recent advances in semiconductor technology have led to
high-density, high-speed, low-cost dynamic random access
memories (DRAMs), making large high-performance memory systems practical. DRAMs have complex timing and refresh requirements that can be met in different ways, depending on the size, speed, and processor interface requirements of the memory being designed. For low or intermediate performance, off-the-shelf components like the DP8419
can be used with a small amount of random logic. For higher performance, specialized high-speed circuitry must be
designed
This application note presents the results of a timing analysis, and describes a DRAM interface for the NS32016 optimized for speed, simplicity and cost.
RAM
Access
Time
in nsec
250
200
150
120
100
RAM
Access
Time
in nsec
250
200
150
120
100
TIMING ANALYSIS RESULTS
Figure 1 is related to a DRAM interface using the DP8419
DRAM controller. Descriptions of the circuitry for use with
the DP8419 and related timing diagrams are omitted. See
the "DP8400 Memory Interface Family Applications" book
for details.
INTERFACE DESCRIPTION
The DRAM interface presented here has been optimized for
overall access time, while requiring moderate speed
DRAMs, given the CPU clock frequency.
This may be significant when a relatively large DRAM array
must be designed since a substantial saving can be
achieved.
The result of these considerations has been the design of a
high-speed DRAM interface capable of working with a CPU
clock frequency of up to 15-MHz and 100-nsec DRAM
chips, without wait states.
The only assumption has been that the DRAM array is directly accessible through the CPU local bus.
0
0
0
0
0
2
0
0
0
0
1
0
0
0
1
0
0
0
2
1
0
0
2
1
0
12 13 CPU Clock
Frequency in MHz
FIGURE 1. Memory Speed vs. CPU Wait States When
Using the DP8419 DRAM Controller
Figures 1 and 2 show the number of CPU wait states required during a DRAM access cycle, for different CPU clock
frequencies and DRAM access times.
The special-purpose interface requires fewer wait states
than the DP8419-based interface, especially at high frequencies.
These results assume a minimum amount of buffering between DRAM and CPU.
The results do not apply when CPU and DRAM reside on
different circuit boards communicating through the system
bus, since extra wait states may be required to provide for
synchronization operations and extra levels of buffering.
U1
CPU Wait States Required
6 7 8 9 10 11
A future application note will discuss such features as error
detection and correction, scrubbing, page mode and! or nibble mode support, in conjunction with future CPUs, such as
the NS32332.
Figure 2 shows the same data for a DRAM interface using
standard TTL components, specially designed for the
NS32016.
•
~
o
CPU Wait States Required
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0 0
0 0
0 0
0
0
0
1
0
0
1
0
0
0
0
67891011 12131415 CPU Clock
Frequency in MHz
FIGURE 2. Memory Speed vs. CPU Wait States
When Using Random Logic
This configuration presents some speed advantages; for example, the amount of buffering interposed between CPU
and DRAM array is minimal. This translates into shorter
propagation delays for address, data and other relevant signals.
Another advantage is that the interface can work in complete synchronization with the CPU. This significantly improves performance since no time is spent for synchronization. Reliability also improves since the possibility of metastable states in synchronizing flip-flops is eliminated.
A block diagram of the DRAM interface is shown in Figure 3.
Figures 4 through 7 show circuit diagrams and timing diagrams.
Interface operation details follow.
RAS AND CAS GENERATION
This is the most critical part of the entire interface circuit. To
avoid wait states during a CPU read cycle, the DRAM must
provide the data before the falling edge of clock phase
PH12 during state T3. This requires that the RAS signal be
generated early in the CPU bus cycle to meet the DRAM
access time. On the other hand, the RAS signal can be
asserted only after the row address is valid and the RAS
precharge time from a previous CPU access or refresh cycle
has elapsed.
8-25
~
o
'Ot'
Z•
cC
r------------------------------------------------------------------------------------------,
The interface circuit shown in Figures 4 and 5 relies on two
advanced clock signals obtained from CTTL through a delay
line and some standard TTL gates.
The advanced clock signals, CTTLA and CTTLB, are used
to clock the circuit that arbitrates between CPU access requests and refresh requests. The CTTLB signal is also used
to enable an advanced RAS generation circuit, which causes the RAS signal to be asserted earlier than the CPU access-grant signal from the arbitration circuit. This speeds up
the RAS signal by about 10 ns by avoiding the time required
by the arbitration circuit to change state.
mer is implemented by cascading two 4-bit counters. Both
counters are clocked by the CTTLB signal; the first is a presettable binary counter that divides the clock signal by a
specified value; the second can be either a BCD or a binary
counter depending on the CPU clock frequency.
With this arrangement, a refresh request is generated after
a fixed time interval from the previous request, regardless of
the CPU activity. A more sophisticated circuit that generates
requests when the CPU is idle could also be implemented.
However, such a circuit has not been considered here because the performance degradation due to the refresh is
relatively small (less than 3.3 percent), and the improvement attainable by using a more sophisticated circuit would
not justify the extra hardware required.
A different delay line is used to generate the CAS signal and
to switch the multiplexers for the column addresses. Note
that the CAS signal during write cycles is delayed until the
beginning of CPU state T3, to guarantee that the data being
written to the DRAM is valid at the time CAS is asserted.
The CAS signal is deasserted after the trailing edge of RAS
to guarantee the minimum pulse width requirement.
The timing diagrams in Figures 6 and 7 show the signal
sequences for both read and write cycles.
CONCLUSIONS
The DRAM interface described in this application uses two
TTL-buffered delay lines to obtain speed advantages. One
delay line is used to time the CAS signal and to enable the
column address. The other is used to generate the advanced clock signals from CTTL.
Below 10 MHz, the advanced clocks might not be required,
and the related delay line can be eliminated. When this is
done, however, higher speed DRAMs must be used. If, on
the other hand, advanced clocks must be used for frequencies lower than 10 MHz, a delay line with a larger delay (e.g.
DDU-7J-100) might be needed.
Delay lines are extremely versatile for this kind of application due to their accuracy and the fact that different delays
are easily available to accommodate different DRAM types.
The savings attainable by using slower DRAM chips, in addition to the reliability improvement and cleaner design, make
delay lines a valid alternative, even though their cost is relatively high in comparison to standard TTL gates.
ADDRESS MULTIPLEXING
The multiplexing of the various addresses for the DRAM
chips is accomplished via four 74AS153 multiplexer chips in
addition to some standard TTL gates used to multiplex the
top two address bits needed for 256k DRAMs. The resulting
nine address lines are then buffered and sent to the DRAMs
through series damping resistors. The function of these resistors is to minimize ringing.
REFRESH
The refresh circuitry includes an address counter, a timer
and a number of flip-flops used to generate the refresh cycle and to latch the refresh request until the end of the
refresh cycle.
The address counter is an 8-bit counter implemented by
cascading the two 4-bit counters of a 74LS393 chip. This
counter provides up to 256 refresh addresses and is incremented at the end of each refresh cycle.
The refresh timer is responsible for generating the refresh
request signal whenever a refresh cycle is needed. This ti-
8-26
NS32000
CPU
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FIGURE 3. DRAM Interface Block Diagram
S017-NV
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FIGURE 4. DRAM Interface Circuit Diagram (a)
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FIGURE 5. DRAM Interface Circuit Diagram (b)
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Interfacing Memory to the
NS32532
National Semiconductor
Application Note 513
Tony Radi
The overall throughput of microprocessor systems often depends on the performance of the memory subsystem. To
achieve optimum throughput with a high-performance microprocessor such as the NS32532, memory should operate with few or no wait states. The processor's clock frequency and the speed of memory components determine
the number of wait states. This Application Note discusses
design considerations for interfacing DRAM and SRAM to
the NS32532. It covers four topics:
word, and two contiguous words are a double-word. A word
or double-word can start at any address, since there are no
memory alignment requirements with the Series 32000®
processors. Although addressable as bytes, memory is organized as double-words, where the address of a doubleword is the address of its least significant byte.
While the NS32532 has no address alignment requirements, alignment affects the time to access a word or double-word. The processor more quickly accesses a doubleword whose address is a multiple of four than one whose
address is otherwise; it takes two memory cycles to fetch
non-double-word aligned data.
The NS32532 supports the memory mapping of peripheral
devices and coprocessors. Such devices can be located
anywhere in the address space except for the upper 8 MB
(addresses FF80000016 through FFFFFFFFI6), which are
reserved. The following section describes the bus signals
required for memory or 1/0 interfacing.
• An overview of NS32532 memory interface requirements
• A simple SRAM interface
• An interleaved SRAM interface
• A simple DRAM interface
BACKGROUND
The NS32532 microprocessor communicates with its environment via parallel busses and signals. These include a
32-bit data bus, a 32-bit address bus, a number of control
signals, and five bus status pins.
The processor has instruction and data caches as well as
an on-chip Memory Management Unit (MMU) to reduce bus
utilization, thereby increasing throughput. The MMU uses
page tables in external memory to perform logical-to-physical address translation. In order to minimize page table accesses, the NS32532 maintains a Translation Look-aside
Buffer (TLB) containing information about frequently-used
addresses. When the TLB does not contain needed information, the NS32532 fetches it from the external page tables. The on-chip caches duplicate a subset of external
memory. The contents of an on-chip cache are acquired in
one clock cycle, while it takes a minimum of two clocks to
fetch data from external memory. Therefore, on-chip caches
substantially reduce average memory access time when
they contain the code and data the processor needs.
On each memory access, the processor initiates a memory
access cycle while searching the internal cache. This reduces access time, since the memory cycle is already in process when the cache does not contain the needed information. During a read that fails to find the data in the cache (a
cache miss), the memory cycle continues and the processor
fetches the data from external memory. Unless declared
non-cacheable, the information is placed in the internal instruction or data cache for future reference. Conversely,
when the instruction or data cache contains the sought information (a cache hit), the processor cancels the memory
access cycle.
A memory write is always treated as a cache miss, so that
external memory is updated; this is a "write through" cache
policy. When an internal cache contains a copy of the memory location being updated, the processor also updates the
cache using a "write allocate" cache policy, thus ensuring
that both copies of the data are the same.
MEMORY ORGANIZATION
The 32-bit address bus of the NS32532 provides up to
4 Gbytes of memory in a uniform linear address space starting at zero and ending at 232 -1. Each memory location
contains an eight-bit byte. Two contiguous bytes form a
8-41
BUS INTERFACE
The NS32532 performs six types of bus operations:
1. Instruction fetch
2. Memory or I/O read
3. Memory or I/O write
4. Read or update page table entries
5. Acknowledge interrupt or completion of interrupt service routine
6. Transfer information to/from Slave Processor
Cases 1 through 5 have identical bus timing characteristics
and are discussed below. The only external difference
among these cases is a six-bit code placed on the bus
status pins (STo-ST5) during bus cycles for the purpose of
identifying which operation is occurring. Case 6 has separate control signals; Slave Processor operation is not relevant to this Application Note and is not discussed here.
The NS32532 can "burst read" up to four consecutive double-words from memory. This feature reduces the amount of
time the processor spends on the memory bus while increasing the hit rate of internal caches. Details of burst operation appear later in this document.
The I/O signals of the NS32532 support interfacing to memory, memory-mapped devices, slave processors, and external caches. The following control signals implement RAM
interfacing on any system without the external cache:
• 00-031: Bidirectional data bus. Either 8,16, or 32 bits of
data are transferred at a time. Do is the least Significant
bit.
• Ao-A31: Address bus. Ao is the least Significant bit.
• ADS: Address strobe. Indicates that a bus cycle has begun and a valid address is on the bus. This signal is the
earliest indication of a bus cycle in progress. The bus
cycle may potentially be cancelled in event of an internal
cache hit.
• BEo-BE3: Byte enable. These signals indicate which
bytes should be selected for transfer. During write cycles,
BEo-BE3 enable the memory banks for writing. During
reads, they select the appropriate banks of an I/O device
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TLlEE/9452-1
TLlEE/9452-2
FIGURE 1. Basic Read Cycle
FIGURE 2. Basic Write Cycle
8-42
.-----------------------------------------------------~~
A full-speed bus access occurs during two cycles of BClK,
T1 and T2. The processor asserts ADS during the first half
of T1 to indicate the start of a bus cycle for both reads and
writes. From the beginning of T1 until completion of the bus
cycle, the processor drives the address bus and other relevant control signals as the timing diagrams indicate. The
processor asserts CONF in the middle of T1 if the bus cycle
is not cancelled and T2 will be entered with the next clock
cycle. BMT may be asserted at the start of the cycle and
then deasserted before the time it is guaranteed valid. This
is caused by an internal cache hit, which cancels the initiated bus cycle. A confirmed bus cycle completes at the end of
T2 unless ROY is high, in which case the processor inserts
additional T2 (wait) states.
T2B
BCLK [
BMT [
[
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The second part of the burst consists of up to three nibbles
in state T2B. In each of these nibbles, the processor reads a
32-bit data item. After each data read, address bits Ao-Al
go to zero and A2-AS increment, and all byte enable out-
Following state T2 is either state T1 of the next bus cycle or
an idle T-state if the processor has no bus cycle to perform.
00-31 [ Ij
....•
A burst cycle consists of two parts. The first is a regular
(opening) cycle, in which the processor outputs its status
and asserts the relevant control signals. The processor asserts BOUT to indicate that it wants to perform burst cycles.
If the selected memory supports burst mode, it notifies the
processor via BIN low. If the memory does not allow burst
(BIN high) and the cycle extension has not been requested
via ROY, the memory cycle terminates at the end of T2 and
the processor deasserts BOUT. If the memory supports
burst and the processor has not deasserted BOUT, the second part of the burst cycle occurs and BOUT remains active
until termination of the operation.
For write bus cycles, valid data is output from the middle of
T1 until the end of the cycle (T2). Due to write-through implementation of the internal caches, write cycles are not
cancelled. When one write cycle immediately follows another, the processor continues driving the bus with data from
the previous operation until the middle of state T1 of the
second bus cycle.
AO-3{
z
BURST CYCLES
The NS32532 is capable of performing burst transfers,
which increase bus efficiency and tend to raise the internal
cache hit rate. Burst is only available in instruction fetch and
data read cycles from 32-bit memories. Figure 3 is the burst
cycle timing diagram, which assumes no wait states.
-I
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TL/EE/9452-3
FIGURE 3. Burst Read Cycle
8-43
•
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puts BEo-BE3 are activated. If the RDY pin is high at the
end of each T2B, the processor inserts additional T2B
states to allow slow memories to work with the burst cycle.
where the processor address bus lacks the necessary drive
capability. High speed 8-bit transceivers, 74PCT245, provide isolation and additional drive capability for the data bus.
The following sections discuss three simple designs. The
first two work at up to 30 MHz, and the third at 30 MHz. The
first design is a simple SRAM interface that requires no wait
states on regular memory cycles. However, it requires one
wait state in each nibble access at speeds higher than 20
MHz. The second design shows an interleaved memory implementation on burst access cycles, eliminating the single
wait state of the first design and thus operating with memory
at full speed. The third design shows a simple DRAM interface to the NS32532. This design inserts three wait states in
a regular memory cycle, but only one wait state in each
nibble transfer at 30 MHz.
SIMPLE SRAM MEMORY INTERFACE TO THE NS32532
This section presents the results of a timing analysis and
describes an SRAM interface for the NS32532 optimized for
simplicity and cost. The interface does not utilize the processor's Bus Error and Bus Retry features.
This design allows all memory writes and the opening cycle
of memory reads to proceed without wait states at any frequency up to 30 MHz. It also supports the NS32532's burst
mode without wait states at up to 20 MHz. For burst transfers at 25 MHz and 30 MHz, one wait state is inserted in
each nibble via jumper WI. Figure 4 shows the timing diagram of the interface.
All three designs use PAL ® devices for address decoding.
Standard driver, 74AS1034, are used to increase drive
T1
T2
Tl
T2
T2B
T2B
T2B
BCLK
A
D
OUT
BMT
CONF
DDIN
BREQ
TLlEE/9452-4
FIGURE 4_ Timing Diagram of the Simple SRAM Interface
8-44
The basis of the design is a state machine implemented by
PAL 16R4D (see Appendix A for state diagram PAL equations and schematics). This PAL keeps track of the processor state and drives the RDY signal high if a wait state
needs to be inserted in the nibble transfer. The processor
increments A2-A3 during burst access cycles.
Another PAL (16L8D) generates the write strobe for memory banks. The memory write strobe is generated by BMT
during write cycles (DDIN high) and terminated by the rising
edge of BCLK during T2. The memory write strobe is qualified with BEo-BE3 before being routed to the memory
banks. ~ second PAl16L8D provides address decoding,
generating the MEMRD signal when the memory is addressed in a read cycle with burst allowed.
operation. This wait state causes only a 3% performance
degradation on average.
INTERLEAVED SRAM MEMORY
INTERFACE TO THE NS32532
This section presents the results of a timing analysis and
describes an NS32532 SRAM interface optimized for speed
and Simplicity. The interface does not utilize the processor's
Bus Error and Bus Retry features. Memory banks are accessed concurrently and the data is read in an interleaved
fashion during burst transfers, thus eliminating the need for
wait states during nibble cycles.
This design provides for operation of the NS32532 at up to
30 MHz without wait states during regular and burst memory
accesses. The latched A2 bit of the processor enables
memory banks for read or write. Reads from memory banks
are interleaved during burst access cycles. This way the
address setup for one bank overlaps with the data read
from another. Figure 5 shows the interface's timing diagram.
This SRAM interface uses 25 ns static RAMs, Fast or Advanced Schottky TTL gates, and D type PALs to achieve no
wait state operation during regular memory cycles. During
burst m~mory transfers at processor speeds over 20 MHz,
one walt state is required in each nibble cycle for correct
T1
CSN
T2
Tl
T2
T2B
T2B
T2B
~~____________________________~;-
TL/EE/9452-5
FIGURE 5. Timing Diagram of the Interleaved SRAM Interface
8-45
....
~.-------------------------------------------------------------------~
II)
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cc
Four PALs implement the design: two for the processor
state machine and specific memory control signals, one for
generating write strobes, and one for address decoding
(see Appendix B for state diagram PAL equations and schematics). PAL16R4D implements the state machine. It uses
the latched A2-Aa bits to control the selection of memory
banks during a burst access, alternating the assertion of
RDL and RDU in successive cycles. The Aa value is set up
in a given cycle, for a bank that will be enabled in the subsequent cycle via RDL or RDU inputs. Aa should fall through
the D flip-flops in order to meet the address setup time for
the SRAM in the opening cycle. To do this,a pulse is generated by qualifying a skewed clock (DCLK) with ADS. This
pulse clocks Aa in the D flip-flops. For proper operation at
different processor frequencies, the jumpers should be installed as follows:
ing edge of BCLK during T2. The memory strobe is qualified
with BEo-BEa before being routed to the memory banks.
The third PAL (16L8D) is the address decoder. It generates
MEMRD when the memory is addressed in read cycles and
burst is allowed. 74AS1034 is used as the buffer driver
where the processor output pins lack the necessary drive
capability.
This SRAM interface uses 25 ns static RAMs, Fast or Advanced Schottky TTL gates, and type D PALs to achieve no
wait state operation during regular memory cycles. During
burst transfers, the interleaving of memory banks allows no
wait state operation of the processor up to 30 MHz.
SIMPLE DRAM INTERFACE TO THE NS32532
This section presents the results of a timing analysis and
describes a DRAM interface to the NS32532 optimized for
speed and simplicity. The interface, which operates at
30 MHz and does not utilize the Bus Error and Bus Retry
features of the processor, uses 80 ns DRAMs to minimize
the number of wait states. All RAS signals are activated
during a normal DRAM access and refresh cycle. During
write cycles, only the CAS signals corresponding to the enabled bytes are active, while all CAS signals are active during reads. Figure 6 shows the interface timing diagram.
• 1-2 for 30 MHz
• 3-4 for 25 MHz
• 5-6 for 20 MHz
After the opening cycle, the Set and Clear inputs of the D
flip-flops change the As value under control of the state
machine PAL.
PAL16L8D generates the memory write strobe from BMT
during write cycles (DDIN high) and terminates it on the ris-
A<2-11>
t.tA
REfRESH ADDRESS
MD
WE ~
- - - - _...../
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",-.
TLlEE/9452-6
FIGURE 6. Timing Diagram of the Simple DRAM Interface
8-46
eight /Ls. Clocked by BCLK, it must be modified if this interface operates at speeds other than 30 MHz. To make the
PAL accommodate different speeds, a load term can be
used in the PAL equations, with PAL inputs jumpered to
ground or Vee.
PAL16L8D generates the CAS strobes for the memory
banks. In read cycles, all CAS strobes are asserted on the
assumption that memory is cacheable, whereas in write cycles, the CAS strobes are qualified with BEo-BE3 before
being routed to the memory banks. The memory write
strobe is derived from DDIN. The data transceivers establish their direction from DDIN and are enabled by CONF.
The data transceivers are recommended, but not necessary
to have this interface operating.
The design uses five PALs: two for generating refresh address and refresh request, one for the state machine, one
for generating CAS strobes, and one for address decoding
(see Appendix C for state diagram PAL equations and schematics).
PAL16R8D implements the state machine. It keeps track of
the processor state and drives the RDY signals high when
wait states are inserted into bus cycles. This design uses
static column DRAM, although it could use nibble mode
DRAM with a simple modification to the state machine. Static column DRAM simplifies the design since the processor
drives and increments A2-A3 during burst access cycles
without the need to toggle CAS. With nibble mode DRAM,
the CAS lines must be toggled during nibble cycles.
Two PAL20X10s generate the refresh address and refresh
request. One PAL is the refresh address counter, which increments at the end of each refresh period. Its outputs drive
the address lines of the DRAMs (row address) during the
refresh period. The other PAL is the refresh interval counter,
generating a refresh request (RFRQ) approximately every
This DRAM interface uses 80 ns column DRAMs, Fast or
Advanced Schottky TIL gates, and type D PALs. It achieves
regular memory transfers in five cycles and burst nibbles in
two cycles. It is possible to operate the NS32532 with fewer
wait states by employing RAS prediction. A future Application Note will discuss features such as RAS prediction and
error detection and correction.
8-47
.,... r---------------------------------------------------------------------------------,
Appendix A
z•
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c(
State Diagram of the Simple SRAM Interface
AS
TL/EE/9452-7
Note 1: This condition is a subset of I AS'BREO condition.
PAl16R4D
STATE MACHINE PAL
STATE MACHINE PAL, WAIT STATE GENERATOR
NATIONAL SEMICONDUCTOR CORP, SANTA CLARA, CALIFORNIA
ClK NC NC WAIT RST BURST NC AS BREQ GND
OE NC ABC D NC NC NC VCC
A : = A' B • ID • IBREQ • IWAIT' RST
+ A • C • ID • IBREQ • IWAIT • RST
B := A' B' ID' IBREQ' WAIT' RST + A' C' ID' IBREQ' WAIT' RST
+ IA' B' C' D' RST
C : = A' B • C • ID • AS • IBURST • RST
D := A' B' C' AS' IBURST' RST + A' B' ID' AS' IBURST' RST
+ A • B • ID • IBREQ • WAIT' RST + A • C • ID • IBREQ • WAIT' RST
+ 1A • B • C • D • RST
8-48
.
l>
z
PAL16L8D
....
U1
WRITE STROBE GENERATOR
Co)
WRITE STROBE GENERATOR FOR SRAM BANKS
NATIONAL SEMICONDUCTOR. SANTA CLARA. CALIFORNIA
BED BE1 BE2 BE3 BODIN A 16 CONF BMT NC GND
BCLK WLD WL2 WL3 WUD WU1 WU2 WU3 WL 1 VCC
fWLD
fBMT • BODIN' fBED • fA 16 + BCLK • fCONF • BODIN' fBED • fA 16
fWL1
fWL2
fBMT' BODIN' fBE1 • fA16
fBMT • BODIN' fBE2 • fA 16
+ BCLK' fCONF' BODIN' fBE1 • fA16
+ BCLK • fCONF • BODIN' fBE2 • fA 16
+ BCLK' fCONF * BODIN * fBE3 * fA16
+ BCLK' fCONF * BODIN * fBED' A16
+ BCLK' fCONF' BODIN' fBE1 * A16
fWL3
fBMT' BODIN' fBE3' fA16
fWUD
fWU1
fWU2
fBMT' BODIN' fBED' A16
fBMT' BODIN * fBE1 * A16
fBMT' BODIN * fBE2' A16
fWU3
fBMT' BODIN' fBE3
+
BCLK' fCONF' BODIN' fBE2' A16
* A16 + BCLK * fCONF * BODIN * fBE3' A16
PAL16L8D
ADDRESS DECODE PAL
ADDRESS DECODER FOR THE SRAM BANKS
NATIONAL SEMICONDUCTOR. SANTA CLARA. CALIFORNIA
F1 F2 F3 A17 A16 NC NC NC NC GND
BODIN NC CSL CSU NC NC NC BURST NC VCC
fCSL
F1 • F2' F3' fA16' fA17
fCSU
F1 • F2' F3' A16' fA17
fBURST =
F1' F2' F3' fA17' fBDDIN
8-49
0(0-31>
NS32532
AI
A2
A3
A4
A5
A6
A7
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8-65
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8-66
Introduction to
Bresenham's Line
Algorithm Using the SBIT
Instruction; Series 32000®
Graphics Note 5
National Semiconductor
Application Note 524
Nancy Cossitt
1.0 INTRODUCTION
The algorithm assumes the line has positive slope less than
one, but a simple change of variables can modify the algorithm for any slope value. This will be detailed in section 2.2.
Even with today's achievements in graphics technology, the
resolution of computer graphics systems will never reach
that of the real world. A true real line can never be drawn on
a laser printer or CRT screen. There is no method of accurately printing all of the points on the continuous line
described by the equation y = mx + b. Similarly, circles,
ellipses and other geometrical shapes cannot truly be implemented by their theoretical definitions because the graphics
system itself is discrete, not real or continuous. For that
reason, there has been a tremendous amount of research
and development in the area of discrete or raster mathematics. Many algorithms have been developed which "map"
real-world images into the discrete space of a raster device.
Bresenham's line-drawing algorithm (and its derivatives) is
one of the most commonly used algorithms today for describing a line on a raster device. The algorithm was first
published in Bresenham's 1965 article entitled "Algorithm
for Computer Control of a Digital Plotter". It is now widely
used in graphics and electronic printing systems. This application note will describe the fundamental algorithm and
show an implementation on National Semiconductor's Series 32000 microprocessor using the SBIT instruction, which
is particularly well-suited for such applications. A timing diagram can be found in Figure 8 at the end of the application
note.
Bresenham's line-drawing algorithm uses an iterative
scheme. A pixel is plotted at the starting coordinate of the
line, and each iteration of the algorithm increments the pixel
one unit along the major, or x-axis. The pixel is incremented
along the minor, or y-axis, only when a decision variable
(based on the slope of the line) changes sign. A key feature
of the algorithm is that it requires only integer data and simple arithmetic. This makes the algorithm very efficient and
fast.
< slope <
1
Given (Xi, Yi) as the previously plotted pixel location for the
line segment, the next pixel to be plotted is either (Xi + 1, Yi)
or (Xi + 1, Yi + 1). Bresenham's algorithm determines
which of these two pixel locations is nearer to the actual line
by calculating the distance from each pixel to the line, and
plotting that pixel with the smaller distance. USing the familiar equation of a straight line, y = mx + b, the y value
corresponding to Xi + 1 is
+ 1) + b
Y = m(xi
The two distances are then calculated as:
dl = y - Yi
dl = m(xi
d2
d2 = (Yi
+ 1) + b -
Yi
= (Yi + 1) - Y
+ 1) -
m(xi
+ 1) -
b
and,
dl - d2 = m(xi
2.0 DESCRIPTION
Y-axis
2.1 Bresenham's Algorithm for 0
Figure 1 shows a line segment superimposed on a raster
grid with horizontal axis X and vertical axis Y. Note that Xi
and Yi are the integer abscissa and ordinate respectively of
each pixel location on the grid.
+ 1) + b -
dl - d2 = 2m(xi
Yi - (Yi
+
+ 1) + m(xi + 1) + b
1) - 2Yi
+
2b - 1
Multiplying this result by the constant dx, defined by the
slope of the line m = dy/dx, the equation becomes:
dx(dl-d2) = 2dY(Xi) - 2dx(Yi)
+c
where c is the constant 2dy + 2dxb - dx. Of course, if d2
> dl, then (dl-d2) < 0, or conversely if dl > d2, then (dld2) > O. Therefore, a parameter Pi can be defined such that
Pi = dx(dl-d2)
Pi = 2dY(Xi) - 2dx(Yi)
+c
f-t-t-t-t-t-t-t-l-l-l-l-I.. ~
Yi +l .....................~
J:...o.
Yi ................• ... ~.
~Itlt
X-axis
TLlEE/9665-2
TL/EE/9665-1
FIGURE 1
Distances d1 and d2 are compared.
The smaller distance marks next pixel to be plotted.
FIGURE 2
8-67
~ r-------------------------------------------------------------------------------~
N
LI)
:Z
c(
If Pi > 0, then d1 > d2 and Yi + 1 is chosen such that the
next plotted pixel is (Xi + 1, Yi). Otherwise, if Pi < 0, then d2
> d1 and (Xi + 1, Yi + 1) is plotted. (See Figure 2.)
Similarly, for the next iteration, Pi + 1 can be calculated and
compared with zero to determine the next pixel to plot. If
Pi + 1 < 0, then the next plotted pixel is at (Xi + 1 + 1,
Yi + 1); if Pi + 1 > 0, then the next point is (Xi + 1 + 1,
Yi + 1 + 1). Note that in the equation for Pi + 1, Xi + 1 = Xi
+ 1.
Another change of variables can be performed on the incremental values to accommodate those lines with slopes
greater than 1 or less than -1. The coordinate system containing the line is rotated 90 degrees so that the X-axis now
becomes the V-axis and vice versa. The algorithm is then
performed on the rotated line according to the sign of its
slope, as explained above. Whenever the current position is
incremented along the X-axis in the rotated space, it is actually incremented along the V-axis in the original coordinate
space. Similarly, an increment along the V-axis in the rotated space translates to an increment along the X-axis in the
original space. Figure 4a., g. and h. illustrates this translation process for both positive and negative lines with various
starting pOints.
Pi + 1 = 2dY{Xi + 1) - 2dx{Yi + 1) + c
Subtracting Pi from Pi + 1, we get the recursive equation:
Pi + 1 = Pi + 2dy - 2dx{Yi + 1 - Yi)
Note that the constant c has conveniently dropped out of
the formula. And, if Pi < 0 then Yi + 1 = Yi in the above
equation, so that:
3.0 IMPLEMENTATION IN C
Bresenham's algorithm is easily implemented in most programming languages. However, C is commonly used for
many application programs today, especially in the graphics
area. The Appendix gives an implementation of Bresenham's algorithm in C. The C program was written and executed on a SVS32/20 system running UNIX on the
NS32032 processor from National. A driver program, also
written in C, passed to the function starting and ending
points for each line to be drawn. Figure 6 shows the output
on an HP laser jet of 160 unique lines of various slopes on a
bit map of 2,000 x 2,000 pixels. Each line starts and ends
exactly 25 pixels from the previous line.
The program uses the variable bit to keep track of the current pixel position within the 2,000 x 2,000 bit map (Figure
5). When the Bresenham algorithm requires the current position to be incremented along the X-axis, the variable bit is
incremented by either + 1 or -1, depending on the sign of
the slope. When the current position is incremented along
the V-axis (I.e., when p > 0) the variable bit is incremented
by + warp or -warp, where warp is the vertical bit displacement of the bit map. The constant last bit is compared with
bit during each iteration to determine if the line is complete.
This ensures that the line starts and finishes according to
the coordinates passed to the function by the driver program.
Pi+1=Pi+ 2dy
or, if Pi> 0 then Yi + 1 = Yi + 1, and
Pi + 1 = Pi + 2{dy-dx)
To further simplify the iterative algorithm, constants c1 and
c2 can be initialized at the beginning of the program such
that c1 = 2dy and c2 = 2{dy-dx). Thus, the actual meat of
the algorithm is a loop of length dx, containing only a few
integer additions and two compares (Figure 3).
2.2 For Slope < 0 and ISlopel > 1
The algorithm fails when the slope is negative or has absolute value greater than one (Idyl> Idxl). The reason for this
is that the line will always be plotted with a positive slope if
xi and Yi are always incremented in the positive direction,
and the line will always be "shorted" if Idxl < Idyl since the
algorithm executes once for every X coordinate (i.e., dx
times). However, a closer look at the algorithm must be taken to reveal that a few simple changes of variables will take
care of these special cases.
For negative slopes, the change is simple. Instead of incrementing the pixel along the positive direction (+ 1) for each
iteration, the pixel is incremented in the negative direction.
The relationship between the starting point and the finishing
point of the line determines which axis is followed in the
negative direction, and which is in the positive. Figure 4
shows all the possible combinations for slopes and starting
points, and their respective incremental directions along the
X and V axis.
do while count < > dx
i f (p < 0) then p+ = cl
else
p+ = c2
next_y = prev_y + y_inc
next_x = prev_x + x_inc
plot (next_x,next_y)
count + = 1
/* PSEUDO CODE FOR BRESENHAM LOOP */
FIGURE 3
8-68
p2
start p1: unc = y' _inc = 0
y_inc =
start p2: >L-inc
y~nc
m=lnf
x'~nc =
=
y' _inc
=
x'~nc =
=
start p1: ><-inc
y_inc
+1
start p2: ><-inc
y_inc
a
-
1
~
~
~
~
+1
0
-1
0
p2
pI
m=O
pI
TL/EE/966S-4
TL/EE/966S-3
b.
a.
p2
pI
~
~
+1
-1
start p1: ,,--inc
y-inc
~
~
- 1
start p2: ><-inc
y-inc
~
~
start p1: ,,--inc
y_inc
start p2: ><-inc
y_inc
= +1
~
TL/EE/966S-S
TL/EE/966S-6
c.
d.
start p1: "--inc
y-inc
start P2:;-inc
~
~
~
+1
-1
-1
p2
~_inC~+1
-1<-inc
y~nc
= x'-inc = +1
~
y' -incl
~
-1
m>1
p2
TLlEE/9665-9
pI
g.
TLlEE/966S-10
h.
Note: a., g., and h. are rolated 90 degrees left and x'. y' refer to the original axis.
FIGURE 4
8-69
blt=O .....~IIIIIIIIIIIP..................piIII!IIIII.................~~bit= 1,999
I--t--t-+-+-I-HH---t-+-+-+-+-+-++++-t",,~~-+-+-+_>warp =2,000
~
bit = starting
.: . , ~
r-position ......1--+-r-.-+-+++-+.tiiiI-"",d'io""""""'-+-+-+-+-+-+--+-+-+-+-+--+--HH-I""""- bit = current
~
position
TL/EE/9665- 11
Bit Map is 500 kbytes, 2k x 2k Bits
Base Address of Bit Map is 'Bit-Map'
FiGURE 5
8-70
:I>
z
Graphics Image (2000 x 2000 Pixels), 300 DPI
•
U1
N
.a:o.
TLlEE/9665-12
FIGURE 6. Star-Burst Benchmark-This Star-Burst Image was done on a 2k x 2k pixel bit map.
Each line is 2k pixels in length and passes through the center of the image, bisecting
the square. The lines are 25 pixel units apart, and are drawn using the LINE_DRAW.S routine. There
are a total of 160 lines. The total time for drawing this Star-Burst is 2.9 sec on 10 MHz NS32C016.
8-71
~
C\oI
"9
z4(
r---------------------------------------------------------------------------------,
The SBIT instruction greatly increases the speed of the algorithm. Notice the method of setting the pixel in the C program given in the Appendix:
4.0 IMPLEMENTATION IN SERIES 32000 ASSEMBLY:
THE SBIT INSTRUCTION
National's Series 32000 family of processors is well·suited
for the Bresenham's algorithm because of the SBIT instruction. Figure 7 shows a portion of the assembly version of the
Bresenham algorithm illustrating the use of the SBIT instruction. The first part of the loop, handles the algorithm for p <
o and .CASE2 handles the algorithm for p > O. The main
loop is unrolled in this manner to minimize unnecessary
branches (compare loop structure of Figure 7 to Figure 3).
The SBIT instruction is used to plot the current pixel in the
line.
bit-fllap[bitl8] I = biLpos[(bit & 7)]
This line of code contains a costly division and several other
operations that are eliminated with the SBIT instruction. The
SBIT instruction helps optimize the performance of the program. Notice also that the algorithm can be implemented
using only 7 registers. This improves the speed performance by avoiding time·consuming memory accesses.
5.0 CONCLUSION
An optimized Bresenham line·drawing algorithm has been
presented using the SYS32/20 system. Both Series 32000
assembly and C versions have been included. Figure 8
presents the various timing results of the algorithm. Most of
the optimization efforts have been concentrated in the main
loop of the program, so the reader may spot other ways to
optimize, especially in the set-up section of the algorithm.
The SBIT instruction uses bit-fllap as a base address from
which it calculates the bit position to be set by adding the
offset bit contained in register r1. For example, if bit, or R1,
contains 2,000', then the instruction:
r1,@ biLmap
sbitd
will set the bit at position 2,000, given that biLmap is the
memory location starting at bit 0 of this grid. In actuality, if
base is a memory address, then the bit position set is:
Several variations of the Bresenham algorithm have been
developed. One particular variation from Bresenham himself
relies on "run·length" segments of the line for speed optimization. The algorithm is based on the original Bresenham
algorithm, but uses the fact that typically the decision variable p has one sign for several iterations, changing only
once in-between these "run·length" segments to make one
vertical step. Thus, most lines are composed of a series of
horizontal "run· lengths" separated by a single vertical jump.
(Consider the special cases where the slope of the line is
exactly 1, the slope is 0 or the slope is infinity.) This algorithm will be explored in the NS32CG1S Graphics Note 5,
AN-522, "Line Drawing with the NS32CG1S", where it will
be optimized using speCial instructions of the NS32CG16.
offset MOD8
within the memory byte whose address is:
base
+ (offset
DIV 8)
So, for the above example,
2,000 MOD 8 = 0
+ 2,000 DIV 8 = bit-fllap + 250
bit 0 of byte (bit-fllap + 250) is set. This bit correbit-fllap
Thus,
sponds to the first bit of the second row in Figure 5.
•All numbers are in decimal.
# Main loop of Bresenham algorithm
.LOOP: #p
.CASE2: #P
<
>
Register and Memory
0: move in x direction only
Contents
cmpqd
$0,r4
ble
.CASE2
rO
addd
rO,r4
rl
addd
r5,rl
=
=
cl constant
bit current
position
sbitd
rl,@_bit_map
r2
cmpd
r3,rl
r3
bne
.LOOP
r4
exit
[r3,r4,r5,rS,r7]
r5
ret
$0
rS
=
=
=
=
=
=
c2 constant
lasLbit
p decision var
x_inc increment
unused register
.align 4
r7
0: move in x and y direction
_bit_map
addd
r2,r4
first byte in bit map
addd
r7,rl
addd
r5,rl
sbitd
rl,@_biLmap
cmpd
rl,r3
bne
.LOOP
exit
[r3,r4,r5,rS,r7]
ret
$0
FIGURE 7
Note: Instructions followed by the letter 'd' indicate '"double word'" operations.
8-72
y_inc increment
=
address of
Set-up time per line is measured from the start of
LINE-DRAW.S only. The overhead of calling the LINEDRAW routine, starting the timer and creating the endpoints
of the vector are not included in this time. Set-up time does
include all register set·up and branching for the Bresenham
algorithm up to the entry pOint of the main loop.
Timing Performance
2k x 2k Bit Map
2k Pix/Vector 160 Lines per Star-Burst
Version
Parameter
Set-up Time Per Vector
Vectors/Sec
Pixels/Sec
Total Time
Star-Burst Benchmark
NS32000 Assembly with SBIT
NS32C016-10 NS32C016-15
45/Ls
54
82
109,776
164,771
2.9s
Vectors/Second is determined by measuring the number
of vectors per second the LINE-DRAW routine can draw,
not including the overhead of the DRIVER.C and START.C
routines, which start the timer and calculate the vector endpoints. All set-up of registers and branching for the Bresenham algorithm are included.
Pixels/Second is measured by dividing the Vectors/Second value by the number of pixels per line.
Total Time for the Star-Burst benchmark is measured from
start of benchmark to end. It does inClude all overhead of
START.C
and
DRIVER.C
and
all
set-up
for
L1NE-DRAW.S. This number can be used to approximate
the number of pages per second for printing the whole StarBurst image.
30".5
1.9s
FIGURES
8-73
National Semiconductor Corporation.
CTP version 2.4
-- line_draw.s -• file
"line draw.sM
.comm-_bit map,4997S,
.globl
lIne draw
.set
WARP ,I",
.align 4
line_draw:
enter
[r3,r4,rS,r6,r71,l2
movd
l2!~),r5
movd
B( p ,r6
movd
r5,rl
muld
$(WARP),rl
addd
r6,rl
movd
2,(fp),r4
subd
r5,r4
absd
r4,r3
l1lDvd
l6(fp) ,r2
subd
r6,r2
abad
r2,r6
cmpd
r3,r6
ble
.LLl
cmpqd
$(,),r4
.LL2
~~r
WARP,rS
br
.LL3
• align 4
.LL2:
addr
-WARP,rS
.LL3:
cmpqd
$(,),r2
bge
.LL4
movqd
$(1),r7
br
.LLS
• align 4
.LL4:
movqd
$(-l),r7
.LL5:
movd
r6,r,
addd
r"r,
subd
rl,r6
addr
,[r6:wl,r2
movd
r"r4
aubd
r3,r4
movd
2, (fp) ,r3
muld
$(WARP),r3
addd
l6(fp),r3
br
.LL6
•align 4
.LL1:
.LL7:
.LL8:
.LL9:
cmpqd
bge
addr
br
• align 4
$(,),r4
.LL7
WARP,r7
.LLB
addr
-WARP,r7
cmpqd
bge
movqd
br
• align 4
$(,),r2
.LL9
$(l),rS
.LLl,
movqd
$(-l),rS
• initialize
t r5~ys
t r6~s
t initialize starting 'bit'
t bitmwarp*ys+xs
• rl=bit
• r4-yf
• r4 a dy
: ~~:k~YI
•
•
•
•
•
•
•
r2=dx
r6-ldXl
branch if slopel
if dy<, want x_inc<,
else x inc is pos
x_inc~+/-warp because of rotate
if dx, then y_inc=+warp
TUEE/9885-13
.LL6:
.LLl1:
addr
movd
subd
addd
movd
subd
movd
muld
addd
jI[r3:wl,rjl
r3,r2
r6,r2
r2,r2
r"r4
r6,r4
2,(fp),r3
$ (WARP) ,r3
l6(fp) ,r3
cmpqd
ble
addd
addd
sbitd
cmpd
bne
exit
ret
.align 4
$('),r4
.LLll
rjl,r4
r5,rl
rl,@ bit_map
r3,rI
.LL6
addd
addd
addd
sbitd
cmpd
bne
exit
ret
r2-2*ldy-dxl=C2
~~~~r;~:-r:st_bitar3
,
•
•
•
t
main loop for algorithm
check sign of p
branch if pos
add cl to p
inc bit by x_inc only
t plot bit
t end only if bit=last_bit
[r3,r4,r5,r6,r7)
$(111)
•
•
•,
p>, then inc in y dir
add c2 to p
add y inc to bit
add x-inc to bit
plot
fiit when bit-last_bit
snd only
TUEE/8885-14
8-74
»
z
.
en
'* This program calculates points on a line using Bresenham's iterative *'
'* method. *'
'include
'define xbytes 25_
'* number of bytes along x-axis*,
'define warp
xbytes * 8
'* number of bits along x axis*,
'define maxy
1999
'* number of lines in y axis*,
unsigned char
bit_map[xbytes*maxyj;
'* array contains bit map*,
static unsigned char
bit-pos[]=ll,2,4,8,16,32,64,128);
'* look-up table for setting bit *'
line_draw(xs,ys,xf,yf)
int
'* starting Is) and finishing If) points
N
"'"
*'
xs,ys,xf,yf;
int
~t~r~~tigrt~_inc,
p,Cl,C2;-
'*
'*
*' *'
*' *'
*' *'
deltas and increments *'
'* current and last bit positions
decision variable p and constants
dxaxf-xs;
~rt~~;~:~arp)+xs;
'* initialize bit to first bit pos
'* calculate last bit on line
last_bit= (yf*warp) +xf;
if (abs(dy) > abs(dx»
I
if (dy>_)
x_inc=warp;
else
x_inelll -warp;
if (dx>_)
y_inc=l;
else
y inc= -II
cl=2*abs(iIx)I
c2=2*(abs(dx)-abs(dy»I
p=2*abs(dx)-abs(dy)I
)
else
y_inc=warp;
y_inc= -warp;
if (dx>_)
else
/* y_axis is now original x_axis */
/* calculate Bresenham's constants */
1*
p is decision variable now rotated */
'* abs(slope)<1 use original axis *'
i f (dy>_)
else
'* abs(slope»1 must rotate space
'* see Figure 5 a.,g.,and h.
'* x_axis is now original y_axis */
'* y_inc is +/-warp number of bits */
x inca l;
'* move forward one bit *'
x 1nc= -1;
/* or backward one bit */
-
Cl=2*abs(iIy)I
'* calculate constants and p *'
c2=2*(abs(dy)-abs(dx»I
p=2*abs(dy)-abs(dx)I
'* Bresenham's Algorithm *'
do
'* do once for each x increment, i.e. dx times */
I
if (p<_)
else (
p+=cl;
~t~~bnc,
'*
'*
no y movement if p<_ */
move in y dir if p>_ */
/* always increment x */
'* bit is set by calculating bit MOD 8, which is */
TL/EE/9665-15
'*
same as bit & 7, then looking up appropriate */
'* bit in table bit-pos. This bit pos is then set *'
/* in byte bit/8 *'
bit map[bit/8] 1- bit-pos[(bit&7)]I
while (bitl-last_bit);
TUEE/9665-16
8-75
1* Program driver.c feeds line vectors to LINE_DRAW.S forming Star-Burst.
"j
#include
#define xbytes
#define maxx
#define maxy
25~
unsigned char
bit_map[xbytes*maxY]i
1999
1999
main()
int i,counti
1* generate Star-Burst image *1
for
(count=l;count<=l~~~;test++)(
for
(i=~;i<=maxy;i+=25)
line draw(~,i,maxx,maxy-i)i
for (i=~ii<=maxx;i+=25)
line_draw(i,maxy,maxx-i,~};
TL/EE/9665-17
I~
start timer and call main procedure of DRIVER.C to draw lines *1
start() (
long "timer
*timer
= J';
(long")
return(*timer) ;
~x6~~;
1* write a zero to timer location *1
main(~,~);
j" Show argc as zero, argv
1* return, in
r~,
the current time
->~
*1
*j
TLlEE/9665-18
8-76
.
:J>
z
National Semiconductor
Application Note 526
Dave Rand
Block Move Optimization
Techniques Series 32000®
Graphics Note 2
U1
I\)
en
1.0 INTRODUCTION
2.0 DESCRIPTION
This application note discusses fast methods of moving
data in printer applications using the National Semiconductor Series 32000. Typically this data is moved to or from the
band of RAM representing a small portion (or slice) of the
total image. The length of data is fixed. The controller design may require moving data every few milliseconds to image the page, until a total of 1 page has been moved. This
may be (at 300 OPI, for example) (8.5 x 300) X (11 X 300),
or 1,051,875 bytes. In current controller designs the width is
often rounded to a word boundary (usually 320 bytes at 300
OPI). This technique uses 1,056,000 bytes, or 528,000
words.
The move string instructions (MOVSi) in the 32000 are very
powerful, however, when all that is needed is a string copy,
they may be overkill. The string instructions include string
translation, conditionals and byte/word/double sizes. If the
application needs only to move a block of data from one
location to another, and that data is a known size (or at least
a multiple of a known size), using unrolled MOVO instructions is a faster way of moving the data from A to 8 on the
NS32032 and NS32332.
; Version 1.0
3.0 IMPLEMENTATION
A code sample follows which makes use of a block size of
128 bytes. To move 256 bytes, for example, RO should contain 2 on entry.
Sun Mar 29 12:57:20 1987
;A subroutine to move blocks of JTeIl1Ory. Uses a granularity of
;128 bytes.
Inputs:
rO = number of 128 byte blocks to move
rl = source block address
r2
= destination
block address
;Listing continues on following page
TLIEE19696-1
8-77
CD
N
II)
Z•
OutputS:
c(
rO = 0
rl = source block address + (128 * blocks)
r2 = destination block address + (128 * blocks)
;Notes:
This algorithn corresponds closely to the MOVSD instruction,
except that rO contains the number of 128 byte blocks, not
4 byte double words. The output values are the same as if a
MOVSD instruction were used.
movmem: cmpqd O,rO
beq
mvexit
. align 4
mvlpl: movd
O(rl).O(r2)
4(rl) ,4(r2)
movd
8(rl),8(r2)
movd
movd
12(rl) ,12(r2)
movd
16(rl).16(r2)
movd
20(rl) ,20(r2)
movd
24(rl).24(r2)
movd
28(rl) ,28(r2)
movd
32(rl) ,32(r2)
movd
36(rl) ,36(r2)
movd
40(rl),40(r2)
movd
44(rl),44(r2)
movd
48(rl) ,48(r2)
movd
52(rl) ,52(r2)
movd
56(rl) ,56(r2)
movd
60(rl) ,60(r2)
movd
64(rl).64(r2)
movd
68(rl),68(r2)
movd
72(rl).72(r2)
movd
76(rl).76(r2)
movd
80(rl).80(r2)
movd
84(rl),84(r2)
movd
88(rl) ,88(r2)
movd
92(rl).92(r2)
96(rl) ,96(r2)
movd
movd
lOO(rl).100(r2)
movd
104( rl ).104( r2)
movd
108(rl).108(r2)
movd
112(rl).112(r2)
movd
U6( rl ).116( r2)
movd
120(rl),120(r2)
movd
124(rl).124(r2)
addr
128( rl). rl
addr
128(r2),r2
acbd
-l,rO,mvlpl
mvexit: ret
$0
; if no blocks to move
;exit now .
;move one block of data
;quick way of adding 128
;loop for rest of blocks
TLlEE/9696-2
8-78
.
J>
4.0 TIMING
move 256 bytes, this algorithm takes 126.8 /-'S. The loop
overhe.ad (the AD DR and ACBD instructions) is about 5%.
Doubling the block size (to 256 bytes) would reduce the
loop overhead to 2.5%, and reducing the block size (to 64
bytes) would increase the loop overhead to 10%. In comparison, the 32032 MOVSD instruction takes about 690
clocks to move a 128-byte block.
On the 32016 (1 wait state. @ 10 MHz, 16-bit bus), this code
executes in 1150 clocks per 128-byte block. Thus, to move
256 bytes, this algorithm takes 230.0 p.s. The loop overhead
on the 32016 is about 2.5%. In comparison, the 32016
MOVSD instruction would take about 1,074 clocks. Thus,
the MOVSD instruction is faster, and makes better use of
the available bus bandwidth of the NS32016.
All timing assumes word aligned data (double word aligned
for 32·bit bus). Unaligned data is permitted, but will reduce
the speed.
On the 32532 (no wait states, @ 30 MHz, 32-bit bus), this
code executes in 204 clocks, assuming burst mode access
is available. To move 256 bytes, this routine would take
13.6 p.s. The MOVSD instruction takes about 156 clocks to
move a 128-byte block. The MOVSD instruction is the best
choice, therefore, on the 32532.
On the 32332 (no wait states, @ 15 MHz, 32-bit bus), this
code executes in 458 clocks per 128-byte block. Thus, to
move 256 bytes, this algorithm takes 61.1 p.s. The loop
overhead (the ADDR and ACBD instructions) is about 10%.
Doubling the block size (to 256 bytes) would reduce the
loop overhead to 5%, and reducing the block size (to 64
bytes) would increase the loop overhead to 20%. In comparison, the 32332 MOVSD instruction takes about 721
clocks to move a 128-byte block.
On the 32032 (no wait states. @ 10 MHz, 32-bit bus), this
code executes in 634 clocks per 128-byte block. Thus, to
5.0 CONCLUSIONS
The MOVSi instructions on the NS32016 provide a very fast
memory block move capability, with variable size. On the
NS32332 and NS32032, however, unrolled MOVD instructions are faster due to the larger bus bandwidth of the
NS32332 and NS32032.
8-79
z
UI
~
en
r-.
N
It)
Z•
c(
Clearing Memory with the
32000; Series 32000®
Graphics Note 3
National Semiconductor
Application Note 527
Dave Rand
1.0 INTRODUCTION
In printer applications, large amounts of RAM may need to
be initialized to a zero value. This application note describes
a fast method.
3.0 IMPLEMENTATION
This routine is written to clear blocks of 128 bytes. This
provides an optimal tradeoff between loop size (granularity)
and loop overhead. This can be modified to use a different
size. For example, to use a block size of 64 bytes, simply
delete 16 of the MOVQD O,TOS instructions from the listing.
As well, since the value of r1 is now the number of 64 byte
groups, one of the ADDD R2,R2 instructions (prior to the
loading of the stack pointer) must be removed. Since the
32000 has two stacks, interrupts will be handled properly
using this code. If only a fixed buffer size needs to be
cleared, the code can be further unrolled to clear that area
(i.e., increase the number of MOVQD O,TOS instructions.)
2.0 DESCRIPTION
While several different methods of initializing memory to all
zeros are available, here is one that works very well on the
Series 32000. While the current version clears memory only
in blocks of 128 bytes, other block sizes are possible by
extending the algorithm.
; Version 1.1
Sun Mar 2910:22:191987
;Subroutine to clear a block of memory. The granularity of this
;algoriti"m is 128 bytes. to reduce the looping overhead.
Inputs:
rO = start of block
r1 = number of 128-byte groups to clear
Outputs:
All regi sters preserved.
;Listing continues on following page
TL/EE/9697-1
8·80
cmpqd D, rl
beq
clexit:w
[rD, rl, r2]
save
rl,r2
IOOvd
addd
r2,r2
addd
r2,r2
r2,r2
addd
r2,r2
addd
addr
4(rD)[r2:q].rD
sprd
sp,r2
lprd
sp,rD
.align 4
IOOvqd D,tos
c12:
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D, tos
IOOvqd O,tos
IOOvqd D, tos
IOOvqd D,tos
movqd D,tos
movqd 0, tos
movqd D,tos
movqd D,tos
IOOvqd D,tos
IOOvqd O,tos
IOOvqd D,tos
IOOvqd D,tes
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd 0, tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd O,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
IOOvqd D,tos
movqd D, tos
IOOvqd D,tos
IOOvqd D,tos
-l,rl,c12
acbd
lprd
sp,r2
restore [rD, rI, r2]
clexit: ret
0
cl ram:
»
z
•
c.n
N
.....
;any blocks to clear?
;no, exit now.
; save our work j ng regi sters
;here we set rD = rD + (rl * 128) + 4
;length *= 2
;*4
;*8
;*16
;get starting point + 4
; save current stack
;move to last double
;clear a double
; restore stack poi nter
; restore our saved regi sters
TLlEE/9697-2
FIGURE 1
8-81
[II
.....
C'I
II)
Z•
e
cmpqd
beq
.align
movqd
c12:
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
movqd
I1Ilvqd
movqd
movqd
I1Ilvqd
movqd
movqd
movqd
addd
acbd
clexlt: ret
clram:
O.rl
clexit:w
4
O.OO(rO)
O.04(rO)
O.08(rO)
O.12(rO)
O.16(rO)
O.20(rO)
O.24(rO)
O.28(rO)
O.32(rO)
O.36(rO)
O.40(rO)
O.44(rO)
O.48(rO)
O.52(rO)
O.56(rO)
O.60(rO)
O.64(rO)
O.68(rO)
O.72(rO)
O.76(rO)
O.80(rO)
O.84(rO)
O.sa(rO)
O.92(rO)
O.96(rO)
O.IOO(rO)
O.I04(rO)
O.I08(rO)
O.1l2(rO)
O.116(rO)
O.120(rO)
O.124(rO)
$128.rO
-1.rl.c12
0
;any blocks to clear?
;no. ex1 t now.
;clear a double
TL/EE/9697-3
FIGURE 2
8·82
r----------------------------------------------------------------.~
4.0 TIMING RESULTS
On the NS32016, NS32032 and NS32332, 4 clock cycles
per write are required. To clear one page of 300 DPI
8% x 11 (1,056,000 bytes), for example, requires 264,000
double words to be written. The optimal time for this, using
100% of the bus bandwidth on a 16 bit bus, would be
528,000' 400 ns, or 211.2 ms, @ 10 MHz. All timing data
assumes word aligned data (double word aligned for 32 bit
bus). Unaligned data is permitted, but will reduce the speed
somewhat.
On the NS32332 (no wait states. @15 MHz, 32 bit bus), this
code clears the full page image in 178 ms.
On the NS32032 (no wait states. @10 MHz, 32 bit bus), this
code clears the full page image in 324 ms.
On the NS32016 (1 wait state. @10 MHz, 16 bit bus), this
code clears the full page image in 509 ms.
Z
U,
......
I\)
Doubling the block size (to 256 bytes) would increase the
speed by 1%-2%, on the code sample.
On the NS32532, a better approach is to use the register
indirect method of referencing memory, as is shown in Figure 2. With this approach, the page memory can be cleared
in 19 ms, assuming a no wait state 30 MHz system, with a
32 bit bus. The optimal time, using 100% of the bus bandwidth of the NS32532 (2 clock bus cycle) would be 264,000
• 66.6 ns, or 17.6 ms.
•
8-83
co ,--------------------------------------------------------------------------------,
N
National Semiconductor
Application Note 528
Dave Rand
In
Image Rotation Algorithm
~ Series 32000® Graphics
Note 4
1.0 INTRODUCTION
Fast image rotation of 90 and 270 degrees is important in
printer applications, since both Portrait and Landscape orientation printing may be desired. With a fast image rotation
algorithm, only the Portrait orientation fonts need to be
stored. This minimizes ROM storage requirements.
This application note shows a fast image rotation algorithm
that may be used to rotate an 8 pixel by 8 line image. Larger
image sizes may be rotated by successive application of the
rotation primitive.
ROTIMG deals with the 8 by 8 destination character as 8
sequential bytes in two registers (R2 and R3), as follows:
Destination Font Matrix
Low Address
OxOOOOOOOO 00000000
OXOOOOOOOO 00000001
OxOOOOOOOO 00000100
OxOOOOOOOO 00000101
Entry
Definition
o
1
2
3
double 0,0
double 1,0
double 256,0
double 257,0
253
254
255
double 16842753,16843009
double Ox01010100,Ox01010101
double Ox01010101,Ox01010101
Each byte within each eight byte table entry represents one
bit of output data. By indexing into the table, and ORing the
table's contents with R2 and R3, we set the destination byte
if the corresponding source bit is set. In this manner, the
character is rotated.
2
3
5
6
Definition
0
1
2
3
Ox0101010101010001
253
254
Ox0101010101010100
255
Ox0101010101010101
The bytes in the table are standard LSB to MSB format.
Since there is no quad-byte assembler pseudo-op (other
than LONG, which is floating point), we must reverse the
'double' declaration to get the correct byte ordering, as is
shown below:
2.0 DESCRIPTION
This Rotate Image algorithm (developed by the Electronic
Imaging Group at National Semiconductor) does a very fast
8 by 8 (64 bit) rotation of font data. Note also that this algorithm does not exclusively deal with fonts, but any 64 bit
image. Larger images can be rotated by breaking the image
down into 8 x 8 segments, and using a 'source warp' constant to index into the source data.
The source data is pOinted to by RO on entry. A 'source
warp' is contained in R 1, and is added to RO after each read
of the source font. This allows the rotation of 16 by 16, 32
by 32 and larger fonts.
4
Entry
= R2
= R3
4
8
3
2
7
6
3.0 IMPLEMENTATION
What we are doing is setting the LS Bit of the destination
byte if the source bit corresponding to that byte is set. We
then shift the entire 64 bit destination left one bit, and repeat
this process until we have set all eight bits, and processed
all eight bytes of source information.
The source data for an 8 by 8 character ">" appears below:
5
7
B
High Address
ROTIMG uses an external table (a pOinter to the start of the
table is located in register R4) to speed the rotation and to
minimize the code. This table consists of 256 64 bit entries,
or a total of 2,048 bytes. The table may be located code
(PC) or data (SB) relative. The complete table is at the end
of this document (see Figure 1). A few entries of the table
are reproduced above.
8-84
Character Table for' >'
Byte
Bit Number
01234567
001000000
100100000
200010000
300001000
400001000
500010000
600100000
701000000
Hex Value
02
04
08
10
10
08
04
02
»
z
The ROTIMG algorithm, expressed in 32000 code, appears below:
I
UI
N
,
,
I
CD
IRotate image emul ation code
,
,
,
,
Inputs:
RO = Source font address
RI = Source font warp
R4 = Rotate table address
,
,
,
Outputs:
R2 = Destination font low 4 bytes (lsb->msb, 0 - 3)
R3 = Destination font high 4 bytes (lsb->msb, 4 - 7)
,
,
ROTIfotG:
rot1p:
save [rO,rS,r6,r7]
movqd
O,r2
r2,r3
movd
r2,rS
movd
8,r6
addr
O(rO). rS
movb
rl,rO
addd
r2,r2
addd
r3,r3
addd
r4[rS:q] ,r7
addrd
O(rl}, r2
ord
4(r7). r3
ord
acbd
-l.r6,rotlp
[rO,rS,r6,r7]
restore
$0
ret
'save regi sters we wi 11 use
'clear destination font
'clear high bits of dest.
'clear high bits of temp.
Ideal with 8 bytes of src.
#get a byte of source
#add source warp
'shift destination left one bit
'top 32 bi ts too
'get poi nter to table
lor in low bits
'or in high bits
land back for more
'restore regi sters
'and return
TL/EE/969B-l
Now, let's look at what happens to the data, given the example lont 01
Loop #
Source Font
R3
R2
02 hex
04
08
10
10
08
04
02
00000000
00000000
00000000
00000000
00000001
00000003
00000006
OOOOOOOC
00000018
00000000
00000100
00010200
01020400
02040800
04081000
09102000
12214000
24428100
0
2
3
4
5
6
7
8
'>'.
;0 destination
;Iirst bits in
;next bits in
;and so on
;Iast iteration
Now, arranging this in the appropriate order gives us:
Destination Character Table for' > " 90 degree
Byte
Bit Number
01234567
000000000
110000001
201000010
300100100
400011000
500000000
600000000
700000000
Destination Character Table for' >', 270 degree
Hex Value
Byte
00
81
42
24
18
00
00
00
Bit Number
01234567
000000000
100000000
200000000
300011000
400100100
501000010
610000001
700000000
Hex Value
00
00
00
18
24
42
81
00
Note that by re-ordering the output data, we may rotate 90 or 270 degrees. This may also be accomplished by using a different
table (see Figure 2).
8-85
•
4.0 TIMING
With unrolled 32000 code, the time for this algorithm is about 588 clocks on the 32016. Subtracting the font read time from this
(about 113 clocks), the actual time for rotation is 475 ciJcks. On the 32332, the time is about 388 clocks. On the 32532, the
unrolled loop time is 120-180 clocks, depending on burst mode availability. Repetition of the character data also affects the
32532, due to the data cache. See Figure 3 for an unrolled code listing.
This table is used for the ROTIMG code. It is 256 entries of 64 bits each (8 bytes' 256 = 2048 bytes). There are two entries per
line. This table is used for 90· rotation.
rottab1: .double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
0x00000000,0x00000000,0x00000001,0x00000000 ;0,1
0x000001OO,0x00000000,0x0000010t,0x00000000 ;2,3
0x0001OOOO,0x00000000,0x0001OOOl,0x00000000 ;4,5
OxOOOlOlOO,OxOOOOOOOO,OxOOOlOlOl,OxOOOOOOOO ;6,7
OxOlOOOOOO,OxOOOOOOOO,OxOlOOOOOl,OxOOOOOOOO ;•••
OxOlOOOlOO,0x00000000,0x01OOOlOl,0x00000000
OxOlOlOOOO,0x00000000,OxOl01OOO1,0x00000000
OxOlOlOlOO,0x00000000,OxOl010101,0x00000000
OxOOOOOOOO,OxOOOOOOOl,OxOOOOOOOl,OxOOOOOOOl
OxOOOOOlOO,0x00000001,OxOOOOOlOl,0x00000001
OxOOOlOOOO,OxOOOOOOOl,OxOOOlOOO1,0x00000001
0x00010100,OxOOOOOOOl,OxOOOlO101,0x00000001
OxOlOOOOOO,0x00000001,0x01OOOOO1,0x00000001
0x01OOO1OO,OxOOOOOOOl,0x01OOO10l,0x00000001
OxOlOlOOOO,OxOOOOOOOl,0x01010001,0x00000001
OxOlOlOlOO,OxOOOOOOOl,OxOlOl010l,0x00000001
0x00000000,0x000001OO,OxOOOOOOOl,OxOOOOOlOO
OxOOOOOlOO,OxOOOOOlOO,OxOOOOOlOl,OxOOOOOlOO
OxOOOlOOOO,OxOOOOOlOO,OxOOOlOOOl,OxOOOOOlOO
OxOOOlOlOO,OxOOOOOlOO,OxOOOlOlOl,OxOOOOOlOO
OxOlOOOOOO,OxOOOOOlOO,0x01OOOOOl,OxOOOOOlOO
OxOlOOOlOO,0x000001OO,OxOlOOOlOl,OxOOOOOlOO
OxOlOlOOOO,OxOOOOOlOO,OxOlOlOOOl,OxOOOOOlOO
OxOlO10100,0x000001OO,OxOlOlOlOl,OxOOOOOlOO
OxOOOOOOOO,OxOOOOOlOl,OxOOOOOOOl,OxOOOOOlOl
OxOOOOOlOO,OxOOOOOlOl,OxOOOOO101,OxOOOOOlOl
OxOOOlOOOO,OxOOOOOlOl,OxOOOlOOOl,OxOOOOOlOl
0x00010100,OxOOOOOlOl,OxOOOlO101,OxOOOOOlOl
OxOlOOOOOO,OxOOOOOlOl,OxOlOOOOOl,OxOOOOOlOl
OxOlOOOlOO,OxOOOOOlOl,OxOlOOOlOl,OxOOOOOlOl
0x01010000,OxOOOOOlOl,OxOlOlOOOl,OxOOOOOlOl
0x0101O100,OxOOOOOlOl,OxOlOlO101,OxOOOOOlOl
OxOOOOOOOO,OxOOOlOOOO,OxOOOOOOOl,OxOOOlOOOO
OxOOOOOlOO,OxOOOlOOOO,OxOOOOOlOl,OxOOOlOOOO
OxOOOlOOOO,OxOOOl0000,OxOOOlOOOl,OxOOOlOOOO
0x00010100,OxOOOlOOOO,OxOOOlOlOl,OxOOOlOOOO
OxOlOOOOOO,OxOOOlOOOO,OxOlOOOOOl,OxOOOlOOOO
OxOlOOOlOO,OxOOOlOOOO,OxOlOOOlOl,OxOOOlOOOO
0x01010000,OxOOOlOOOO,OxOlOlOOOl,OxOOOlOOOO
0x01010100,OxOOOlOOOO,0x01010101,OxOOOlOOOO
0x00000000,OxOOOl0001,OxOOOOOOOl,OxOOOlOOOl
OxOOOOOlOO,OxOOOlOOOl,OxOOOOOlOl,OxOOOlOOOl
OxOOOlOOOO,OxOOOlOOOl,OxOOOlOOOl,OxOOOlOOOl
OxOOOlOlOO,0x0001OOO1,0x00010101,OxOOOlOOOl
0x01OOOOOO,0x0001OOO1,0x01OOOOOl,OxOOOlOOOl
0x01OOO1OO,0x0001OOO1,0x01OOO10l,OxOOOlOOOl
0x0101OOOO,0x0001OOOl,0x0101OOOl,0x0001OOOl
OxOl0101OO,0x0001OOO1,0x01010101,OxOOOlOOOl
OxOOOOOOOO,OxOOOlOlOO,OxOOOOOOOl,OxOOOlOlOO
TL/EE/969B-2
FIGURE 1
8-86
r----------------------------------------------------------------------,
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
.double
U1
N
CIO
OxOOOOOlOO,OxOOOlOlOO,OxOOOOOlOl,OxOOOlOlOO
OxOOOlOOOO,0x00010100,OxOOOlOOOl,OxOOOlOlOO
OxOOOlOlOO,OxOOOlOlOO,OxOOOlO101,OxOOOlOlOO
OxOlOOOOOO,OxOOOlOlOO,OxOlOOOOOl,OxOOOlOlOO
OxOlOOOlOO,OxOOOlOlOO,OxOlOOOlOl,OxOOOlOlOO
0x0101OOOO,0x000101OO,0x010lOOO1,0x000101OO
OxOlOlOlOO,OxOOOl01OO,OxOlOlOlOl,OxOOOl01OO
0x00000000,OxOOOl010l,0x00000001,OxOOOlO101
OxOOOOOlOO,OxOOOlOlOl,OxOOOOOlOl,OxOOOlO101
OxOOOlOOOO,OxOOOlOlOl,OxOOOlOOOl,OxOOOlOlOl
OxOOOlOlOO,OxOOOlOlOl,OxOOOlOlOl,OxOOOlO101
OxOlOOOOOO,OxOOOlOlOl,OxOlOOOOOl,OxOOOlOlOl
OxOlOOOlOO,OxOOOlOlO1,OxOlOOO101,OxOOOlO101
0x01010000,OxOOOlOlOl,OxOlOlOOOl,OxOOOlO101
OxOlO10100,OxOOOlOlOl,OxOlOlOlOl,OxOOOlOlOl
OxOOOOOOOO,OxOlOOOOOO,OxOOOOOOOl,OxOlOOOOOO
OxOOOOOlOO,OxOlOOOOOO,OxOOOOOlOl,OxOlOOOOOO
OxOOOlOOOO,OxOlOOOOOO,OxOOOlOOOl,OxOlOOOOOO
0x00010lOO,OxOlOOOOOO,0x00010101,OxOlOOOOOO
OxOlOOOOOO,OxOlOOOOOO,OxOlOOOOOl,OxOlOOOOOO
OxOlOOO1OO,OxOlOOOOOO,OxOlOOO101,OxOlOOOOOO
OxOlOlOOOO,OxOlOOOOOO,OxOlOlOOOl,OxOlOOOOOO
OxOlO10100,OxOlOOOOOO,OxOlO10101,OxOlOOOOOO
OxOOOOOOOO,OxOlOOOOOl,OxOOOOOOOl,OxOlOOOOOl
OxOOOOOlOO,OxOlOOOOOl,OxOOOOOlOl,OxOlOOOOOl
OxOOOlOOOO,OxOlOOOOOl,OxOOOlOOOl,OxOlOOOOOl
0x00010100,OxOlOOOOOl,OxOOOlO101,OxOlOOOOOl
OxOlOOOOOO,OxOlOOOOOl,OxOlOOOOOl,OxOlOOOOOl
OxOlOOOlOO,OxOlOOOOOl,OxOlOOO101,OxOlOOOOOl
0x01010000,OxOlOOOOOl,OxOlOlOOOl,OxOlOOOOOl
0x01010100,OxOlOOOOOl,OxOl010101,OxOlOOOOOl
0x00000000,0x01OOO1OO,OxOOOOOOOl,0x01OOO1OO
OxOOOOOlOO,OxOlOOOlOO,OxOOOOOlOl,OxOlOOOlOO
OxOOOlOOOO,OxOlOOOlOO,OxOOOlOOOl,OxOlOOOlOO
OxOOOlOlOO,OxOlOOOlOO,OxOOOl010l,OxOlOOOlOO
OxOlOOOOOO,OxOlOOOlOO,OxOlOOOOOl,OxOlOOOlOO
OxOlOOOlOO,OxOlOOOlOO,OxOlOOO101,OxOlOOOlOO
OxOlOlOOOO,OxOlOOOlOO,OxOlOlOOOl,OxOlOOOlOO
OxOlOlO100,OxOlOOOlOO,OxOlOlOlOl,OxOlOOOlOO
0x00000000,OxOlOOOlOl,OxOOOOOOOl,OxOlOOO101
OxOOOOOlOO,OxOlOOO10l,OxOOOOOlOl,OxOlOOOlOl
OxOOOlOOOO,OxOlOOOlOl,OxOOOlOOOl,OxOlOOOlOl
OxOOOlOlOO,OxOlOOOlOl,OxOOOlO101,OxOlOOO101
OxOlOOOOOO,OxOlOOOlOl,OxOlOOOOOl,OxOlOOOlOl
OxOlOOO1OO,OxOlOOOlOl,OxOlOOO101,OxOlOOO101
OxOlOlOOOO,OxOlOOOlOl,OxOlOlOOOl,OxOlOOO101
0x01010100,OxOlOOO101,OxOlOlO101,OxOlOOOlOl
0x00000000,OxOl01OOOO,OxOOOOOOOl,0x010lOOOO
OxOOOOOlOO,OxOlOlOOOO,0x0000010l,OxOlOlOOOO
OxOOOlOOOO,OxOlOlOOOO,OxOOOlOOOl,OxOlOlOOOO
OxOOOlO100,OxOlOlOOOO,0x00010101,OxOlOlOOOO
OxOlOOOOOO,OxOlOlOOOO,OxOlOOOOOl,OxOlO10000
OxOlOOOlOO,0x01010000,OxOlOOOlOl,OxOlOlOOOO
OxOlOlOOOO,OxOl01OOOO,OxOlOlOOOl,OxOlOlOOOO
OxOlOlOlOO,OxOlOlOOOO,OxOlOlO101,OxOlOlOOOO
TL/EE/9698-3
FIGURE 1 (Continued)
8-87
~
z,
•
co
N
r---------------------------------------------------------------------------------,
1.1)
z•
msb, 0 - 3)
R3 = Destination font high 4 bytes (lsb->msb, 4 - 7}
ROTlMG:
movqd
movd
movd
movb
addd
addd
addd
addr
ord
ord
movb
addd
addd
addd
addr
ord
ord
movb
addd
addd
addd
addr
ord
ord
movb
addd
addd
addd
addr
ord
ord
movb
addd
D,r2
r2,r3
r2,rS
O(rD), rS
rl,rO
r2,r2
r3,r3
r4[r5:q] ,r6
O(r6),r2
4(r6),r3
O(rO),rS
rl,rO
r2,r2
r3,r3
r4 [rS: q] ,r6
O(r6),r2
4(r6), r3
O(rD),r5
rl,rO
r2,r2
r3,r3
r4 [r5:q]. rS
O(rS),r2
4(rS),r3
O(rO),r5
rl,rO
r2,r2
r3,r3
r4[r5:q] ,rS
O(rS),r2
4(r6),r3
O(rO), r5
rl,rO
'clear destination font
'clear high bits of dest.
'clear high bits of temp.
Iget a byte of source
#add source warp
Ishift destination left one
#top 32 bi ts too
'get poi nter to table
lor in low bits
lor in high bits
'get a byte of source
'add source warp
'shift destination left one
#top 32 bits too
'get poi nter to table
'or in low bits
lor in high bits
Iget a byte of source
ladd source warp
Ishift destination left one
#top 32 bi ts too
'get poi nter to table
'or in low bits
'or in high bits
'get a byte of source
ladd source warp
Ishi ft destination left one
Itop 32 bi ts too
Iget poi nter to table
lor in low bits
lor in high bits
Iget a byte of source
ladd source warp
bit
bit
bit
bit
TL/EE/969B-B
FIGURE 3
8-91
co
.
C'I
In
Z
z
U1
N
CD
Comments
Suggest changing algorithm to use ADDPi
Suggest changing algorithm to use ADDPi/SUBPi
Suggest changing algorithm to use SUBPi
ADDCi
ADDi
ANDi
CHECKi
BSR/JSR
MOVXBW
BICPSRB$1
BICPSRW $Ox800
CMPi
CMPSi
MOVXWD
ADDQi-1*
DIVi
ENTER[reglistl,d
WAIT
DIVi/QUOi
You may directly sign-extend data while moving
Usually not required
Direction encoded within string instructions
Supervisor mode instruction
Usually not required
Many options available
You may directly sign-extend data while moving
Suggest changing algorithm to use ADDPi
Suggest changing algorithm to use SUBPi
Watch for flag usage
Note: Series 32000 uses signed division
Builds stack frame, saves regs, allocates stack space
Usually used for Floating Point-see Series 32000 FP instructions
DIVi rounds towards -infinity, QUOi to zero
MUll
ADDQi 1*
SVC
FLAG
RETI $0
BHI
BHS
BLT
BLS
BEQ
BGT
BGE
BLT
BLE
BR/JUMP
BNE
Series 32000 uses memory-mapped I/O
Watch for flag usage
Series 32000 uses memory mapped I/O
Not exact conversion, but usually used to call O/S
Trap on overflow
Causes Interrupt Acknowledge cycle
Unsigned comparison
Unsigned comparison
Unsigned comparison
Unsigned comparison
Use CMPQi 0, followed by BEQ
Equal comparison
Signed comparison
Signed comparison
Signed comparison
Signed comparison
Not Equal comparison
Subroutines should be used for these instructions
as most Series 32000 code will not need these
operations.
SPRB UPSR,xxx may be useful
Segment registers not required on Series 32000
AD DR
EXlT[reglistl
MOVilADDQD
ACBi-1
Restores regs, unallocates frame and stack
Segment registers not required
SBITli, CBITIi interlocked instructions
MOV instruction followed by address increment
ACBi may use memory or register
8-97
•
G)
'"
II)
Z•
CC
80x86
LOOPE
LOOPNE
LOOPNZ
LOOPZ
MOV
MOVS
MUL
NEG
NOP
NOT
OR
OUT
OUTS
POP
POPA
POPF
PUSH
PUSHA
PUSHF
RCL
RCR
REP
RET
ROL
ROR
SAHF
SAL
SAR
SBB
SCAS
SHL
SHR
STC
STD
STI
STOS
SUB
TEST
WAIT
XCHG
XLAT
XOR
Series 32000
TABLE I (Continued)
Comments
BEQ followed by ACBi may be used
BNE followed by ACBi may be used
BNE followed by ACBi may be used
BEQ followed by ACBi may be used
MOVi
MOVSi
MULi
NEGi
NOP
COMi
ORi
MOViTOS,
RESTORE [rO,r1 .• r7]
LPRB UPSR,TOS
MOVixx,TOS
SAVE [rO,r1 .. r7]
SPRB UPSR,TOS
ROTio
ROTi"
RET
ROTi
ROTi
ASHi
ASHi
SUBCi
SKPSi
LSHi
LSHi
BISPSRB$1
BISPSRW $Ox800
MOVilADDQD
SUBi
Many options available
Series 32000 uses signed multiplication
Two's complement
One's complement
Series 32000 uses memory mapped 1/0
Series 32000 uses memory mapped 1/0
TOS addressing mode auto increments/decrements SP
Restores list of registers
User mode loads 8 bits, supervisor 16 bits of PSR
Any data may be moved to TOS
Saves list of registers
User mode stores 8 bits, supervisor 16 bits of PSR
Does not rotate through carry
Does not rotate through carry
Series 32000 string instructions use 32-bit counts
Rotates work in both directions
LPRB UPSR,xx may be useful
Arithmetic shift
Arithmetic shift works both directions
Many options available
Logical shift
Logical shift works both directions
Direction is encoded in string instructions
Supervisor mode instruction
MOV instruction followed by address increment
TBITi may be used as a substitute
MOVi x[RO:b],
XORi
MOVi x,temp; MOVi y,x; MOVi temp,y
Scaled index addressing mode
8-98
r------------------------------------------------------------------o~
~~
National Semiconductor
Application Note 530
Dave Rand
Bit Mirror !RolUlitoll1le;
Series 32000® Gli"a~hDcs
Note 7
1.0 INTRODUCTION
The bit mirror routine is designed to reorder the bits in an image. The bits are swapped around a fixed point, that being one
half of the size of the data, as is shown for the byte mirror below. These routines can be used for conversion of 68000 based
data.
2.0 DESCRIPTION
Source
Result of Mirror
7
6
Bit Number
5 4 3 2
I
0
0
I
I
0
0
1
0
0
1
The "mirror", in this case, is between bits 3 and 4.
1
0
0
I
Hex
Value
1
0
B2
4D
Several different algorithms are available for the mirror operation. The best algorithm to mirror a byte takes 20 clocks on a
NS32016 (about 2.5 clocks per bit), and uses a 256 byte table to do the mirror operation. The table is reproduced at the end
of this document. To perform a byte mirror, the following code may be used. The byte to be mirrored is in RO, and the
destination is to be Rl.
MOVB mirtab[rO:b] ,rl
or·ti rror a byte
TLlEE/9700-1
An extension of this algorithm is used to mirror larger amounts of data. To mirror a 32·bit block of data from one location to
another, the following code may be used. Register RO points to the source block, register R I points to the destination. R2 is
used as a temporary value.
MOYlBO
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
O(rO).r2
mirtab[r2:b] ,3(rt)
l(rO). r2
mi rtab [r2: b] ,2 (rl)
2(rO).r2
mirtab[r2:b] ,l(rl)
3(rO),r2
mirtab[r2:b] .O(rl)
#get fi rst byte
iJstore in last place
#get next byte
tlstore in next place
#get the thi rd byte
Ustore in next place
Uget the 1ast byte
Ilfirst place
TL/EE/9700-2
This code uses 33 bytes of memory, and just 169 clocks to execute. Larger blocks of data can be mirrored with this method
as well, with each additional byte taking about 40 clocks.
Registers can also be mirrored with this method, with just a few more instructions. To mirror RO to RI, for example, the
following code could be used. R2 is used as a temporary variable.
MOVlBO
MOVa
LSHD
LSHD
MOVa
MOVB
LSHD
LSHD
MOVB
MOVB
LSHD
LSHD
MOVB
MOYB
rO. r2
mi rtab [r2: bJ, rl
$8.rl
$-B. rO
rO. r2
mi rtab [r2: b] ,rl
$8. rl
$-8. rO
rO. r2
mi rtab [r2: b] •rl
SB.rl
$-8. rO
rO. r2
mi rtab [r2: b] •rl
;1get 1sbyte
Urni rror the byte
(!move into higher byte of destination
(land of source
#get 1sbyte
I,'mi rror the byte
(!move into higher byte of destination
Hand of source
Hget 1sbyte
Urni rror the byte
#move into higher byte of destination
#and of source
#get 1sbyte
~'mi rror the byte
TL/EE/9700-3
8·99
C)
C")
II)
z•
cc
r---------------------------------------------------------------------------------~
This code occupies 49 bytes, and executes in 286 clocks on an NS32016.
If space is at a premium, a shorter table may be used, at the expense of time. Each nibble (4 bits) instead of each byte is
processed. This means that the table only requires 16 entries. To mirror a byte in RO to R1, the following code can be used. R2
is used as a temporary variable.
MOVB
ANOO
MOVB
LSHD
LSHO
MOVB
ANDD
ORB
rO,r2
$15, r2
ml rtb16[r2:b], rl
$4,rl
$-4, rO
rO,r2
$15, r2
mi rtb16[r2:b], rl
'get 1sbyte
#mask to get 1s nibble
#ml rror the nl bb1e
'high nibble of destination
land of souree
'get 1sbyte
#mask to get 1s nibble
#mIrror the ni bb1e
TL/EE/9700-4
This code requires 32 bytes of memory, and executes in 125 clock cycles on an NS32016. A slightly faster time (100 clocks)
may be obtained by adding a second table for the high nibble, and eliminating the LSHD 4,r1 instruction.
TABLES
MIRTAB is a table of all possible mirror values of 8 bits, or 256 bytes. MIRTB16 is a table of all possible mirror values of 4 bits, or
16 bytes. These tables should be aligned for best performance. They may reside in code (PC relative), or data (S8 relative)
space.
mirtab:
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
•byte
. byte
•byte
•byte
•byte
•byte
. byte
. byte
•byte
•byte
•byte
•byte
. byte
. byte
. byte
OxOO,Ox80, Ox40,OxeO, Ox20, OxaO, Ox60,OxeO, OxlO, 0x90, OxSO
OxdO,Ox30,OxbO,Ox70,OxfO
OxOO , Ox88 , Ox48 ,OxeB, Ox2B, Oxa8, Ox6B ,0xeB, OxlB, Ox9B, OxSB
Oxd8 ,Ox38, OxbB,Ox7B,Oxf8
Ox04, Ox84, Ox44 , Oxe4, Ox24 , Oxa4 , Ox64 , Oxe4, Ox14, Ox94, Ox54
Oxd4, Ox34, Oxb4, Ox74, Oxf4
OXOC, Ox8e, Ox4c, Oxee, Ox2e, Oxae, Ox6c, Oxee, Oxle, Oxge, Ox5c
Oxdc, Ox3e, Oxbc, Ox7e, Oxfe
Ox02 ,OxB2, Ox42 , Oxe2, Ox22 ,Oxa2, Ox62 ,Oxe2, Ox12, Ox92 , OxS2
Oxd2 ,Ox32, Oxb2, Ox72, Oxf2
OxOa ,OxBa, Ox4a, Oxea, Ox2a, Oxaa, Ox6a ,Oxea, Oxla, Ox9a, OxSa
Oxda,Ox3a, Oxba, Ox7a, Ox fa
Ox06 ,OxB6, Ox46 , Oxe6, Ox26, Oxa6, Ox66 , Oxe6, Ox16, Ox96, OxS6
Oxd6,Ox36,Oxb6,Ox76,Oxf6
OxOe, OxBe, Ox4e, Oxee, Ox2e ,Oxae, Ox6e ,Oxee, Oxle, Oxge, OxSe
Oxde, Ox3e, Oxbe, Ox7e, Oxfe
OxOl,OxBl, Ox4l ,Oxel ,Ox2l ,Oxal,Ox6l,Oxel,Oxll ,0x9l, Ox5l
Oxdl,Ox3l, Oxbl, Ox71, Oxfl
Ox09 ,OxB9, Ox49 , Oxe9, Ox29 ,Oxa9, Ox69 ,Oxe9, Oxl9, Ox99 , OxS9
Oxd9, Ox39 , Oxb9, Ox79, Oxf9
OxOS, OxBS, Ox45, OxeS, Ox2S ,Oxa5, Ox65, Oxe5, OxlS, Ox9S, OxSS
OxdS,Ox35,OxbS,Ox75,Oxf5
OxOd,OxBd, Ox4d, Oxed, Ox2d, Oxad, OxSd, Oxed, Oxld, Ox9d, OxSd
Oxdd,Ox3d,Oxbd,Ox7d,Oxfd
Ox03 ,Ox83, Ox43 , Oxe3, Ox23 , Oxa3, Ox63 , Oxe3, Ox13, Ox93, OxS3
Oxd3, Ox33, Oxb3, Ox73, Oxf3
OxOb,Ox8b, Ox4b, Oxeb, Ox2b, Oxab, Ox6b,Oxeb, Oxlb, Ox9b, OxSb
Oxdb,Ox3b,Oxbb,Ox7b,Oxfb
Ox07 ,OxB7, Ox47 ,Oxe7 ,Ox27 ,Oxa7 ,Ox67 ,Oxe7, Oxl7 ,Ox97, Ox57
Oxd7 ,Ox37 ,Oxb7 ,Ox77 ,Oxf7
OxOf, Ox8f, Ox4f ,Oxef, Ox2f, Oxaf, Ox6f ,Oxef, Oxl f, Ox9f, OxSf
Oxdf,Ox3f,Oxbf,Ox7f,Oxff
•byte
. byte
OxO, Ox8, Ox4, Oxe, Ox2, Oxa, Ox6, Oxe, Oxl, Ox9, Ox5
Oxd,Ox3,Oxb,Ox7, Oxf
mlrtb16:
8-100
TL/EE/9700-5
Section 9
NSC800 Family
Section 9 Contents
NSC800 High-Performance Low-Power CMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . .
NSC810A RAM-I/O-Timer...........................................................
NSC831 Parallel 1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSC888 NSC800 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Comparison Study NSC800 vs. 8085/80C85/Z80/Z80 CMOS............................
Software Comparison NSC800 vs. 8085, Z80 ..........................................
9·2
9-3
9-76
9-97
9-111
9-115
9-118
z
~
~National
CD
Q
Q
~ Semiconductor
microCMOS
NSC800™ High-Performance
Low-Power CMOS Microprocessor
General Description
Features
The NSC800 is an 8-bit CMOS microprocessor that functions as the central processing unit (CPU) in National Semiconductor's NSC800 microcomputer family. National's
microCMOS technology used to fabricate this device provides system designers with performance equivalent to
comparable NMOS products, but with the low power advantage of CMOS. Some of the many system functions incorporated on the device, are vectored priority interrupts, refresh
control, power-save feature and interrupt acknowledge. The
NSC800 is available in dual-in-line and surface mounted
chip carrier packages.
• Fully compatible with Z801i> instruction set:
Powerful set of 158 instructions
10 addressing modes
22 internal registers
• Low power: 50 mW at 5V Vee
• Unique power-save feature
• Multiplexed bus structure
• Schmitt trigger input on reset
• On-chip bus controller and clock generator
• Variable power supply 2.4V-6.0V
• On-Chip 8-bit dynamic RAM refresh circuitry
• Speed: 1.0
instruction cycle at 4.0 MHz
NSC800-4
4.0 MHz
NSC800-3
2.5 MHz
NSC800-1
1.0 MHz
• Capable of addressing 64k bytes of memory and 256
1/0 devices
• Five interrupt request lines on-chip
The system designer can choose not only from the dedicated CMOS peripherals that allow direct interfacing to the
NSC800 but from the full line of National's CMOS products
to allow a low-power system solution. The dedicated peripherals include NSC810A RAM I/O Timer, NSC858 UART,
and NSC831 1/0.
'"'S
All devices are available in commercial, industrial and military temperature ranges along with two added reliability
flows. The first is an extended burn in test and the second is
the military class C screening in accordance with Method
5004 of MIL-STD-883.
Block Diagram
D'I81
B'IBI
F'
l'
E'
C'
181
181
181
IBI
A
H
D
B
F
l
E
C
181
181
181
181
H" 181
IBI
181
181
181
REGISTER
ARRAY
1161
IX
IY
1161
R 181
1181
STACK POINTER 1161
PROGRAM COUNTER 1161
ClK
OUT
INCREMENTER
oECREMENTER (16)
ADDRESS LATCH
iiii
RFSH
XIN_
TIMING AND CONTROL
XoUT_
WR
ALE
Pi
SO
BACK RESET RESET
iN OUT
ADDRESS 8US
ADDRESS/DATA BUS
TL/C/5171-73
9-3
Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS
9.0 TIMING AND CONTROL
2.0 OPERATING CONDITIONS
9.5 Bus Access Control
3.0 DC ELECTRICAL CHARACTERISTICS
9.6 Interrupt Control
4.0 AC ELECTRICAL CHARACTERISTICS
NSC800 SOFTWARE
5.0 TIMING WAVEFORMS
10.0 INTRODUCTION
NSC800 HARDWARE
11.0 ADDRESSING MODES
6.0 PIN DESCRIPTIONS
11.1 Register
6.1 Input Signals
11.2 Implied
6.2 Output Signals
11.3 Immediate
6.3 Input/Output Signals
11.4 Immediate Extended
11.5 Direct Addressing
7.0 CONNECTION DIAGRAMS
11.6 Register Indirect
8.0 FUNCTIONAL DESCRIPTION
11.7 Indexed
8.1 Register Array
11.8 Relative
8.2 Dedicated Registers
11.9 Modified Page Zero
8.2.1 Program Counter
11.10 Bit
8.2.2 Stack Pointer
12.0 INSTRUCTION SET
8.2.3 Index Register
8.2.4 Interrupt Register
12.1 Instruction Set Index/Alphabetical
8.2.5 Refresh Register
12.2 Instruction Set Mnemonic Notation
12.3 Assembled Object Code Notation
8.3 CPU Working and Alternate Register Sets
8.3.1 CPU Working Registers
12.4 8-Bit Loads
8.3.2 Alternate Registers
12.5 16-Bit Loads
12.6 8-Bit Arithmetic
12.7 16-Bit Arithmetic
8.4 Register Functions
8.4.1 Accumulator
12.8 Bit Set, Reset, and Test
8.4.2 F Register-Flags
12.9 Rotate and Shift
8.4.3 Carry (C)
12.1 0 Exchanges
8.4.4 Adds/Subtract (N)
12.11 Memory Block Moves and Searches
8.4.5 Parity/Overflow (PIV)
12.12 Input/Output
8.4.6 Half Carry (H)
12.13 CPU Control
8.4.7 Zero Flag (Z)
12.14 Program Control
8.4.8 Sign Flag (S)
12.15 Instruction Set: Alphabetical Order
8.4.9 Additional General Purpose Registers
12.16 Instruction Set: Numerical Order
8.4.10 Alternate Configurations
8.5 Arithmetic Logic Unit (ALU)
13.0 DATA ACQUISITION SYSTEM
8.6 Instruction Register and Decoder
14.0 NSC800M/883B MIL STD 883/CLASS C
SCREENING
9.0 TIMING AND CONTROL
15.0 BURN-IN CIRCUITS
9.1 Internal Clock Generator
16.0 ORDERING INFORMATION
9.2 CPU Timing
17.0 RELIABILITY INFORMATION
9.3 Initialization
9.4 Power Save Feature
9-4
z
1.0 Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Voltage on Any Pin
with Respect to Ground
~
NSC800-3
~
TA
NSC800-4
7V
~
TA
TA
TA
300'C
Parameter
TA
TA
1W
3.0 DC Electrical Characteristics Vee =
TA
TA
-0.3V to Vee +0.3V
lead Temp. (Soldering, 10 seconds)
Symbol
NSC800-1
-65'Cto + 150'C
Maximum Vee
Power Dissipation
(J)
2.0 Operating Conditions
(Note 1)
5V ± 10%, GND
=
=
=
=
=
=
=
=
=
(")
«XI
o
O'C to +70'C
o
-40'C to +85'C
O'C to +70'C
-40'C to +85'C
-55'C to + 125'C
O'C to +70'C
- 40'C to + 85'C
-55'Cto +125'C
OV, unless otherwise specified.
Max
Units
VIH
logical 1 Input Voltage
0.8 Vee
Vee
V
VIL
logical 0 Input Voltage
0
0.2 Vee
VHY
Hysteresis at RESET IN input
VOHl
logical 1 Output Voltage
VOH2
logical 1 Output Voltage
VaLl
logical 0 Output Voltage
VOL2
logical 0 Output Voltage
= 5V
lOUT = -1.0 mA
lOUT = -10/LA
lOUT = 2mA
lOUT = 10 /LA
IlL
Input leakage Current
IOL
lee
lee
Active Supply Current
lee
Active Supply Current
IQ
Quiescent Current
Ips
Conditions
Min
0.25
Vee
Typ
0.5
V
V
2.4
V
Vee -0.5
V
0
0.4
0
0.1
V
0:;;; VIN:;;; Vee
-10.0
10.0
/LA
Output leakage Current
0:;;; VIN:;;; Vee
-10.0
Active Supply Current
= 0, f(XIN) = 2 MHz, TA = 25'C
lOUT = 0, f(XIN) = 5 MHz, T A = 25'C
lOUT = 0, f(XIN) = 8 MHz, T A = 25'C
lOUT = 0, PS = 0, VIN = OorVIN = Vee
f(XIN) = 0 MHz, T A = 25'C, XIN = 0, ClK =
lOUT = 0, PS = 0, VIN = 0 orVIN = Vee
f(XIN) = 5.0 MHz, T A = 25'
Power-Save Current
8
lOUT
1
V
10.0
/LA
11
rnA
10
15
rnA
15
21
rnA
2
5
rnA
5
7
mA
CIN
Input Capacitance
6
10
pF
COUT
Output Capacitance
8
12
pF
Vee
Power Supply Voltage
5
6
V
(Note 2)
2.4
Note 1: Absolute Maximum Ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified under DC Electrical Characteristics.
Note 2: CPU operation at lower voltages will reduce the maximum operating speed. Operation at voltages other than 5V ± 10% is guaranteed by design, not
tested.
9-5
o
o
~
Z
4.0 AC Electrical Characteristics Vcc =
Symbol
Parameter
NSC800·1
5V ± 10%, GND = OV, unless otherwise specified
NSC800
NSC800·4
Min
Max
Min
Max
Min
Max
Units
Notes
Ix
Period at XIN and XOUT
Pins
500
3333
200
3333
125
3333
ns
T
Period at Clock Output
(= 2tx)
1000
6667
400
6667
250
6667
ns
tR
Clock Rise Time
110
110
80
ns
Measured from 10%-90% of
signal
IF
Clock Fall Time
70
60
50
ns
Measured from 10%-90% of
signal
tL
Clock Low Time
435
150
85
ns
50% duty cycle, square wave
input on XIN
tH
Clock High Time
450
145
75
ns
50% duty cycle, square wave
inputonXIN
tACC(OP)
ALE to Valid Data
1340
490
300
ns
Add t for each WAIT STATE
tACC(MR)
ALE to Valid Data
1875
620
375
ns
tAFR
AD(0-7) Float after
RD Falling
0
0
0
ns
tBABE
BACK Rising to Bus
Enable
1000
400
250
ns
tBABF
BACK Falling to Bus Float
50
ns
tBACL
BACK Fall to CLK
Falling
50
50
125
425
55
ns
ns
tSRH
BREQ Hold Time
tSRS
BREQ Set-Up Time
tCAF
Clock Falling ALE
Falling
0
70
0
65
0
55
ns
leAR
Clock Rising to ALE
Rising
0
100
0
100
0
80
ns
leRO
Clock Rising to
Read Rising
100
90
80
ns
leRF
Clock Rising to
Refresh Falling
80
70
60
ns
tOAI
ALE Failing to INTA
Falling
445
tOAR
ALE Falling to RD Falling
400
575
160
250
90
160
ns
tOAW
ALE Falling to WR Falling
900
1010
350
420
200
255
ns
to(BACK)1
ALE Falling to BACK
Falling
to(BACK)2
BREQ Rising to BACK
Rising
to(l)
ALE Falling to INTR, NMI,
RSTA-C, PS, BREQ, Inputs
Valid
tOPA
Rising PS to Falling ALE
to(WAIn
ALE Falling to WAIT Input
Valid
0
0
0
100
50
45
160
2460
500
1610
200
1360
500
1685
200
700
760
250
9-6
ns
600
125
475
550
ns
85
975
125
Add t for each WAIT STATE
ns
Add t for each WAIT state
Add t for opcode fetch cycles
475
ns
250
ns
Add t for each WAIT state
Add t for opcode fetch cycles
500
ns
See Figure 14 also
125
ns
z
4.0 AC Electrical Characteristics Vcc =
NSC800-1
5V
± 10%, GND
NSC800
= OV, unless otherwise specified (Continued)
NSC800-4
Symbol
Parameter
TH(ADH)1
A(8-15) Hold Time During
Opcode Fetch
0
0
0
ns
TH(ADH)2
A(8-15) Hold Time During
Memory or 10, RD and WR
400
100
60
ns
Min
Max
Min
Max
Min
Units
Max
TH(ADL)
AD(0-7) Hold Time
100
60
30
ns
THfWD)
Write Data Hold Time
400
100
75
ns
tlNH
Interrupt Hold Time
0
0
0
ns
tiNS
Interrupt Set-Up Time
100
50
45
ns
tNMI
Width of NMllnput
50
30
20
ns
tRDH
Data Hold after Read
0
0
0
ns
tRFLF
RFSH Rising to ALE
Falling
60
50
40
ns
tRL(MR)
RD Rising to ALE Rising
(Memory Read)
390
100
45
ns
\s(AD)
AD(0-7) Set-Up Time
300
45
40
ns
\s(ALE)
A(8-15), SO, 51, 101M
Set-UpTime
350
70
50
ns
\sfWD)
Write Data Set-Up Time
385
75
30
ns
tW(ALE)
ALE Width
430
130
100
ns
tWH
WAIT Hold Time
0
0
0
ns
tw(l)
Width of INTR, RSTA-C,
PS,BREQ
500
200
125
ns
tW(INTA)
INTA Strobe Width
1000
400
200
ns
tWL
WR Rising to ALE Rising
450
130
70
ns
tw(RD)
Read Strobe Width During
Opcode Fetch
960
360
185
ns
ns
tw(RFSH)
Refresh Strobe Width
1925
725
395
tws
WAIT Set-Up Time
100
70
55
ns
tW(WAIT)
WAIT Input Width
550
250
175
ns
tW(WR)
Write Strobe Width
985
390
220
ns
tXCF
XIN to Clock Falling
25
100
20
95
5
XIN to Clock Rising
25
85
20
85
5
tXCR
Note 1: Test conditions: t = 1000 ns for NSC800·1, 400 ns for NSC800, 250 ns for NSC800·4.
Note 2: Oulputtlmings are measured with a purely capacitive load of 100 pF.
9-7
Notes
80
ns
80
ns
Add two t states for first INTA of
each interrupt response string
Add t for each WAIT state
Add t for each WAIT State
Add t/2 for Memory Read Cycles
Add t for each WAIT state
~
CD
o
o
C) .-------------------------------------------------------------------------------~
C)
~
5.0 Timing Waveforms
(J)
z
Opcode Fetch Cycle
~-------------------------Ml------------------------~
------I~----T2
-----I-----T3 ------t------·T4 _ _
X1N
ClK
ALE
A(8-15)
101M. 50.51
WAIT
---"1'---+--....:.-~+_--+_"f'--~-------------+__
..............
.......
--~
.....................
~
.......
-+~~~~
.............................................................................--
~
·~-~w~-----------------------------------------
-----!-:---',..
TLlC/5171-3
Memory Read and Write Cycle
ClK
ALE
A(8-15)
---'1'---+---+--+-.;........;..-:.-------!-"["'\,---
Rii
L-l::~~!G;::l=~~===~~~~~,l---
AD(0-7) - - -.......
(WRITE) ----'l''--''''"'''":'-.;..-..:....If1'o-+_---------''fI'+---
WAIT
__............................+--.......
-J.~
---.!!R~il0
INTA. RST AC
PS-
101M. SO. 51
IO/ij=O.SO=~=.SI=~=
____-J~..............- -.......- -.......- -..............~~~.....................~
Tl/C/5171-4
9·8
5.0 Timing Waveforms
z
en
o
(Continued)
CI)
o
o
Interrupt-Power-Save Cycle
eLK
ALE
INTEl, HSTA,
RSTB.RSTC~~::::~~::~~::~::~=+~:::::::::::E~~r==;,;rr.~=rj::::::::::
iNTA
INDTE 21
TLlC/5171-5
Note 1: This t state is the last t state of the last M cycle of any instruction.
Note 2: Response to INTR inpul.
Note 3: Response to PS inpul.
Bus Acknowledge Cycle
ANY t.1 CYClE--<+---- BUS AVAILABLE STATES - - -..
ClK
AD (0 - 7)
A(B-15) _ _ _ _I -_ _ _ _ _-+_~
I:::r_t_BA_BE_ __
-- -- - -- - -------- ~L.
_ _ _ __
1-
101M. RD. ViR
ALE'
TL/C/5171-6
"Waveform not drawn to proportion. Use only for specifying test pOints.
AC Testing Input/Output Waveform
AC Testing Load Circuit
TL/C/5171-7
TL/C/5171-8
9-9
o
o
CO
o(J)
z
r--------------------------------------------------------------------------,
NSC800 HARDWARE
6.0 Pin Descriptions
6.1 INPUT SIGNALS
CPU stops executing at the end of current instruction and
keeps itself in the low-power mode. Normal operation resumes when PS returns high (see Power Save Feature description).
Reset Input (RESET IN): Active low. Sets A (8-15) and AD
(0-7) to TRI-STATE® (high impedance). Clears the contents of PC, I and R registers, disables interrupts, and activates reset out.
CRYSTAL (XIN, XOUT): XIN can be used as an external
clock input. A crystal can be connected across XIN and
XOUT to provide a source for the system clock.
Bus Request (BREQ): Active low. Used when another device requests the system bus. The NSC800 recognizes
BREQ at the end of the current machine cycle, and sets
A(8-15), AD(0-7), 10/M, RD, and WR to the high impedance state. RFSH is high during a bus request cycle. The
CPU acknowledges the bus request via the BACK output
signal.
6_2 OUTPUT SIGNALS
Bus Acknowledge (BACK): Active low. BACK indicates to
the bus requesting device that the CPU bus and its control
signals are in the TRI-STATE mode. The requesting device
then commands the bus and its control signals.
Non-Maskable Interrupt (NMI): Active low. The non-maskable interrupt, generated by the peripheral device(s), is the
highest priority interrupt. The edge sensitive interrupt requires only a pulse to set an internal flip-flop which generates the internal interrupt request. The NMI flip-flop is monitored on the same clock edge as the other interrupts. It
must also meet the minimum set-up time spec for the interrupt to be accepted in the current machine instruction.
When the processor accepts the interrupt the flip-flop resets
automatically. Interrupt execution is independent of the interrupt enable flip-flop. NMI execution results in saving the
PC on the stack and automatic branching to restart address
X'0066 in memory.
Address Bits 8-15 [A(8-15)1: Active high. These are the
most significant 8 bits of the memory address during a
memory instruction. During an I/O instruction, the port address on the lower 8 address bits gets duplicated onto A(815). During a BREQ/BACK cycle, the A(8-15) bus is in the
TRI-STATE mode.
Reset Out (RESET OUT): Active high. When RESET OUT
is high, it indicates the CPU is being reset. This signal is
normally used to reset the peripheral devices.
Input/Output/Memory (101M): An active high on the 101M
output signifies that the current machine cycle is an input!
output cycle. An active low on the 10/M output signifies that
the current machine cycle is a memory cycle. It is TRISTATE during BREQ/BACK cycles.
Restart Interrupts, A, B, C (RSTA, RSTB, RSTC): Active
low level sensitive. The CPU recognizes restarts generated
by the peripherals at the end of the current instruction, if
their respective interrupt enable and master enable bits are
set. Execution is identical to NMI except the interrupts vector to the following restart addresses:
Restart
Name
Address (X')
0066
RSTA
003C
0034
RSTB
RSTC
002C
INTR (Mode 1)
0038
Refresh (RFSH): Active low. The refresh output indicates
that the dynamic RAM refresh cycle is in progress. RFSH
goes low during T3 and T4 states of all M1 cycles. During
the refresh cycle, AD(0-7) has the refresh address and
A(B-15) indicates the interrupt vector register data. RFSH is
high during BREQ/BACK cycles.
Address latch Enable (ALE): Active high. ALE is active
only during the T1 state of any M cycle and also T3 state of
the M1 cycle. The high to low transition of ALE indicates
that a valid memory, 1/0 or refresh address is available on
the AD(0-7) lines.
Read Strobe (RD): Active low. The CPU receives data via
the AD(0-7) lines on the trailing edge of the RD strobe. The
RD line is in the TRI-STATE mode during BREQ/BACK cycles.
The order of priority is fixed. The list above starts with the
highest priority.
Interrupt Request (INTR): Active low, level sensitive. The
CPU recognizes an interrupt request at the end of the current instruction provided that the interrupt enable and master interrupt enable bits are set. INTR is the lowest priority
interrupt. Program control selects one of three response
modes which determines the method of servicing INTR in
conjunction with INTA. See Interrupt Control.
Write Strobe (WR): Active low. The CPU sends data via the
AD(0-7) lines while the WR strobe is low. The WR line is in
the TRI-STATE mode during BREQ/BACK cycles.
Clock (elK): ClK is the output provided for use as a system clock. The ClK output is a square wave at one half the
input frequency.
Wait (WAIT): Active low. When set low during RD, WR or
INTA machine cycles (during the WR machine cycle, wait
must be valid prior to write gOing active) the CPU extends its
machine cycle in increments of t (wait) states. The wait machine cycle continues until the WAIT input returns high.
Interrupt Acknowledge (INTA): Active low. This signal
strobes the interrupt response vector from the interrupting
peripheral devices onto the AD(0-7) lines. INTA is active
during the M1 cycle immediately following the t state where
the CPU recognized the INTR interrupt request.
The wait strobe input will be accepted only during machine
cycles that have RD, WR or INTA strobes and during the
machine cycle immediately after an interrupt has been accepted by the CPU. The later cycle has its RD strobe suppressed but it will still accept the wait.
Two of the three interrupt request modes use INTA. In
mode 0 one to four INTA signals strobe a one to four byte
instruction onto the AD(0-7) lines. In mode 2 one INTA signal strobes the lower byte of an interrupt response vector
onto the bus. In mode 1, INTA is inactive and the CPU response to INTR is the same as for an NMI or restart interrupt.
Power-Save (PS): Active low. PS is sampled during the last
t state of the current instruction cycle. When PS is low, the
9-10
z
o
co
en
6.0 Pin Descriptions (Continued)
Status (SO, S1): Bus status outputs provide encoded information regarding the current M cycle as follows'
Status
Machine Cycle
Opcode Fetch
Memory Read
Memory Write
1/0 Read
1/0 Write
Halt'
Internal Operation'
Acknowledge of Int"
Control
SO
S1
101M
RD
WR
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
1
6.3INPUT/OUTPUT SIGNALS
Multiplexed Address/Data [AD(O-7)]: Active high
Input data to CPU.
At RD Time:
At WR Time:
Output data from CPU.
At Falling Edge Least significant byte of address
of ALE Time:
during memory reference cycle. a-bit
port address during I/O reference
cycle.
During BREQ/ High impedance.
BACK Cycle:
0
1
0
1
1
• ALE is not suppressed in this cycle .
• ·This is the cycle that occurs immediately after the CPU accepts an interrupt (RSTA. RSTB. RS'fC. INTR. NMI).
Note 1: During halt, CPU continues to do dummy opcode fetch from location
following the halt instruction with a halt status. This is so CPU can continue
to do its dynamic RAM refresh.
Note 2: No early status is provided for interrupt or hardware restarts.
7.0 Connection Diagrams
Chip Carrier Package
Dual·ln·Line Package
AB
A9
AID
All
A12
A13
A14
A15
eLK
XDUT
XIN
ADO
ADI
AD2
AD3
AD4
AD5
AD6
AD7
GND
vee
AI2 All AID A9 A8
PS
\
WAif
N5CBDD
Top View
31
30
29
2B
27
26
25
24
23
22
21
NC
RESET
OUT BRED
J
AI3 7 6 5 4 3 2 I 4443 42 414~9 BACK
RESET OUT
BREO
BACK
101M
RESET IN
10
11
12
13
14
15
16
17
lB
19
20
Vee PS WAIT
AI4
AI5
ClK
XDUT
NC
XIN
ADO
ADI
AD2
AD3
iiii
Viii
ALE
50
iiFSi1
B
3B
9
37
10
36
II
35
12
NSCBOO
34
13
33
14
32
15
31
16
3D
17
29
1819202122232425262728
NC
51
INTA
INTR
R5TC
R5TB
R5TA
101M
RESET IN
iiii
Viii
NC
ALE
SO
RFSH
SI
INTA
t\
AD4 A05 AD6 AD7 GND NMI iiS'fl\' RSTB HSTC INTH
Top View
TLlC/5171-11
Order Number NSC800E or V
See NS Package E44B or V44A
Jm1
TLlC/5171-10
Order Number NSC800D or N
See NS Package D40C or N40A
9-11
Q
Q
C)
C)
r------------------------------------------------------------------------------------------,
co
8.0 Functional Description
(1)
This section reviews the CPU architecture shown below, focusing on the functional aspects from a hardware perspective, including timing details.
(.)
z
(25)
(26)
INTR
INTA
(23)
(24)
Am liSfC
As illustrated in Figure 1, the NSC800 is an 8-bit parallel
device, The major functional blocks are: the ALU, register
array, interrupt control, timing and control logic, These areas
are connected via the 8-bit internal data bus, Detailed descriptions of these blocks ae provided in the following sections.
(21)
NMI
F'
l'
E'
C'
H' (8)
0' (8)
8' (8)
A (8)
(8)
(8)
8 (8)
POWER
SUPPLY
{
l
IX
IY
~VCC
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
REGISTER
ARRAY
(16)
(16)
(8)
R (8)
STACK POINTER (16)
(20)
_GND
PROGRAM COUNTER (16)
elK
OUT
RFSH
iiii
(9)
(28)
(32)
INCREMENTER
DECREMENTER (16)
ADDRESS LATCH
~~~)~
TIMING AND CONTROL
XOUT
(10)
Wii
~)
ALE
~
PS
•
SO
~
Sl
~
10/M BRED 8ACK
~
•
•
iiESE'i
RESET
A(8-15)
M
ADDRESS BUS
(33)
(37)
m
AD(0-7)
ADDRESS/DATA BUS
TLiC/5171-9
Note: Applicable pinout for 40·pin
dual-in-line package within parentheses
FIGURE 1. NSC800 CPU Functional Block Diagram
9-12
8.0 Functional Description
z
en
o
(Continued)
Q)
8.1 REGISTER ARRA V
8.2.2 Stack Pointer (SP)
The NSC800 register array is divided into two parts: the
dedicated registers and the working registers, as shown in
Figure 2.
The 16·bit stack painter contains the address of the current
top of stack that is located in external system RAM. The
stack is organized in a last-in, first-out (UFO) structure. The
pointer decrements before data is pushed onto the stack,
and increments after data is popped from the stack.
Various operations store or retrieve, data on the stack. This,
along with the usage of subroutine calls and interrupts, allows simple implementation of subroutine and interrupt
nesting as well as alleviating many problems of data manipulation.
8.2.3 Index Register (IX and IV)
.
Alternate Reg. Set
Main 'teg. Set
\(
(
\
Accumulator Flags Accumulator Flags
A
F
A'
F'
B
C
B'
C'
D
E
D'
E'
H
L
H'
L'
Interrupt
Vector I
I
Working
} Registers
The NSC800 contains two index registers to hold independent, 16-bit base addresses used in the indexed addressing
mode. In this mode, an index register, either IX or IY, contains a base address of an area in memory making it a pointer for data tables.
In all instructions employing indexed modes of operation,
another byte acts as a signed two's complement displacement. This addressing mode enables easy data table manipulations.
Memory
Refresh R
Index Register IX
Index Register IV
Dedicated
Registers
Stack Pointer SP
8.2.4 Interrupt Register (I)
Program Counter PC
When the NSC800 provides a Mode 2 response to INTR,
the action taken is an indirect call to the memory location
containing the service routine address. The pointer to the
address of the service routine is formed by two bytes, the
high-byte is from the I Register and the low·byte is from the
interrupting peripheral. The peripheral always provides an
even address for the lower byte (LSB=O). When the processor receives the lower byte from the peripheral it concatenates it in the following manner:
FIGURE 2. NSC800 Register Array
8.2 DEDICATED REGISTERS
There are 6 dedicated registers in the NSC800: two 8·bit
and four 16·bit registers (see Figure 3).
Although their contents are under program control, the pro·
gram has no control over their operational functions, unlike
the CPU working registers. The function of each dedicated
register is described as follows:
CPU Dedicated Registers
Program Counter PC
Stack Pointer SP
Index Register IX
Index Register IY
Interrupt Vector Register I
Memory Refresh Register R
I
(16)
(16)
(16)
(16)
(8)
(8)
I Register
8 bits
I
External byte
i
The LSB of the external byte must be zero.
FIGURE 4a. Interrupt Register
The even memory location contains the low·order byte, the
next consecutive location contains the high-order byte of
the painter to the beginning address of the interrupt service
routine.
8.2.5 Refresh Register (R)
FIGURE 3. Dedicated Registers
8.2.1 Program Counter (PC)
For systems that use dynamic memories rather than static
RAM's, the NSC800 provides an integral 8-bit memory refresh counter. The contents of the register are incremented
after each opcode fetch and are sent out on the lower portion of the address bus, along with a refresh control signal.
This provides a totally transparent refresh cycle and does
not slow down CPU operation.
The program can read and write to the R register, although
this is usually done only for test purposes.
The program counter contains the 16·bit address of the cur·
rent instruction being fetched from memory. The PC incre·
ments after its contents have been transferred to the ad·
dress lines. When a program jump occurs, the PC receives
the new address which overrides the incrementer.
There are many conditional and unconditional jumps, calls,
and return instructions in the NSC800's instruction reper·
toire that allow easy manipulation of this register in control·
ling the program execution (i.e. JP NZ nn, JR Zd2, CALL
NC, nn).
9-13
o
o
8.0 Functional Description
(Continued)
B.3 CPU WORKING AND ALTERNATE REGISTER SETS
8.4 REGISTER FUNCTIONS
B.3.1 CPU Working Registers
8.4.1 Accumulator (A Register)
The portion of the register array shown in Figure 4b represents the CPU working registers. These sixteen 8-bit registers are general-purpose registers because they perform a
multitude of functions, depending on the instruction being
executed. They are grouped together also due to the types
of instructions that use them, particularly alternate set operations.
The A register serves as a source or destination register for
data manipulation instructions. In addition, it serves as the
accumulator for the results of 8-bit arithmetic and logic operations.
The A register also has a special status in some types of
operations; that is, certain addressing modes are reserved
for the A register only, although the function is available for
all the other registers. For example, any register can be
loaded by immediate, register indirect, or indexed addressing modes. The A register, however, can also be loaded via
an additional register indirect addressing.
The F (flag) register is a special-purpose register because
its contents are more a result of machine status rather than
program data. The F register is included because of its interaction with the A register, and its manipulations in the alternate register set operations.
Another special feature of the A register is that it produces
more efficient memory coding than equivalent instruction
functions directed to other registers. Any register can be
rotated; however, while it requires a two-byte instruction to
normally rotate any register, a single-byte instruction is
available for rotating the contents of the accumulator (A register).
B.3.2 Alternate Registers
The NSC800 registers designated as CPU working registers
have one common feature: the existence of a duplicate register in an alternate register set. This architectural concept
simplifies programming during operations such as interrupt
response, when the machine status represented by the contents of the registers must be saved.
B.4.2 F Register - Flags
The NSC800 flag register consists of six status bits that
contain information regarding the results of previous CPU
operations. The register can be read by pushing the contents onto the stack and then reading it, however, it cannot
be written to. It is classified as a register because of its
affiliation with the accumulator and the existence of a duplicate register for use in exchange instructions with the accumulator.
The alternate register concept makes one set of registers
available to the programmer at any given time. Two instructions (EX AF, A'F' and EXX), exchange the current working
set of registers with their alternate set. One exchange between the A and F registers and their respective duplicates
(A' and F') saves the primary status information contained in
the accumulator and the flag register. The second exchange
instruction performs the exchange between the remaining
registers, B, C, D, E, H, and L, and their respective alternates B', C', D', E', H', and L'. This essentially saves the
contents of the original complement of registers while providing the programmer with a usable alternate set.
CPU Main Working Register Set
Accumulator A
(8)
(8)
Register B
Register D
(8)
(8)
Register H
CPU Alternate Working
Accumulator A'
Register B'
Register D'
Register H'
Flags F
Register C
Register E
Register L
(8)
(8)
(8)
(8)
Register Set
(8)
Flags F'
(8)
Register C'
(8)
Register E'
(8)
Register L'
(8)
(8)
(8)
(8)
Of the six flags shown in Figure 5, only four can be directly
tested by the programmer via conditional jump, call, and
return instructions. They are the Sign (S), Zero (Z), Parity/
Overflow (PlY), and Carry (C) flags. The Half Carry (H) and
Add/Subtract (N) flags are used for internal operations related to BCD arithmetic.
BIT7
BIT 0
1 I z I" I" 1 1
S
H
P/V
I
N
C
1
I
LCARRY
L - - ADO/SUBTRACT
"-----PARITY OVERFLOW
L . . - - - - - - - H A L F CARRY
L..----------ZERO
"-------------SIGN
TLIC/5171-23
FIGURE 5. Flag Register
FIGURE 4b. CPU Working and Alternate Registers
9-14
8.0 Functional Description
z
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o
(Continued)
Q)
8.4.3 Carry (C)
The following operations affect the PIV flag according to
the parity of the result of the operation:
A carry from the highest order bit of the accumulator during
an add instruction. or a borrow generated during a subtraction instruction sets the carry flag. Specific shift and rotate
instructions also affect this bit.
Logic Operations
•
Two specific instructions in the NSC800 instruction repertoire set (SCF) or complement (CCF) the carry flag.
Input Register Indirect
Other operations that affect the C flag are as follows:
•
•
•
Adds
Subtracts
Logic Operations (always resets C flag)
•
Rotate Accumulator
Rotate and Shift
Rotate Digits
Decimal Adjust
The following operations affect the PIV flag according to
the overflow result of the operation.
o
Adds (16 bit with carry, 8-bit with/without carry)
•
•
Subtracts (16 bit with carry, 8-bit with/without carry)
Increments and Decrements
• Rotate and Shifts
• Decimal Adjust
• Negation of Accumulator
Other operations do not affect the C flag.
8.4.4 Adds/Subtract (N)
• Negation of Accumulator
The PIV flag has no significance immediately after the following operations.
Block I/O
o
Bit Tests
This flag is used in conjunction with the H flag to ensure that
the proper BCD correction algorithm is used during the decimal adjust instruction (DAA). The correction algorithm depends on whether an add or subtract was previously done
with BCD operands.
In block transfers and compares, the PIV flag indicates the
status of the BC register, always ending in the reset state
after an auto repeat of a block move. Other operations do
not affect the PIV flag.
8.4.6 Half Carry (H)
The operations that set the N flag are:
•
•
•
This flag indicates a BCD carry, or borrow, result from the
low-order four bits of operation. It can be used to correct the
results of a previously packed decimal add, or subtract, operation by use of the Decimal Adjust Instruction (DAA).
Subtractions
Decrements (8-bit)
Complementing of the Accumulator
The following operations affect the H flag:
• Adds (8-bit)
• Block I/O
• Block Searches
• Negation of the Accumulator
The operations that reset the N flag are:
•
•
•
•
•
•
o
Adds
Increments
Logic Operations
o
o
Subtracts (8-bit)
Increments and Decrements
Decimal Adjust
Negation of Accumulator
Always Set by: Logic AND
Complement Accumulator
Bit Testing
Rotates
Set and Complement Carry
o
Input Register Indirect
Always Reset By:
Logic OR's and XOR's
Rotates and Shifts
Set Carry
Input Register Indirect
Block Transfers
Load of the I or R Registers
Bit Tests
Other operations do not affect the N flag.
0
•
•
Block Transfers
Loads of I and R Registers
8.4.5 Parity/Overflow (P/V)
The H flag has no significance immediately after the following operations.
o
16-bit Adds with/without carry
o
16-Bit Subtracts with carry
The Parity/Overflow flag is a dual-purpose flag that indicates results of logic and arithmetic operations. In logic operations, the PIV flag indicates the parity of the result; the
flag is set (high) if the result is even, reset (low) if the result
is odd. In arithmetic operations, it represents an overflow
condition when the result, interpreted as signed two's complement arithmetic, is out of range for the eight-bit accumulator (Le. -128 to + 127).
o
Complement of the carry
Block I/O
o
Block Searches
o
Other operations do not affect the H flag.
9-15
o
o
C) r-------------------------------------------------------------------------------~
C)
co
8.0 Functional Description
z
8.4.7 Zero Flag (Z)
o
en
(Continued)
8.4.9 Additional General-Purpose Registers
The other general-purpose registers are the B, C, D, E, H
and L registers and their alternate register set, B', C', D', E',
H' and L'. The general-purpose registers can be used interchangeably.
In addition, the Band C registers perform special functions
in the NSC800 expanded I/O capabilities, particularly block
I/O operations. In these functions, the C register can address I/O ports; the B register provides a counter function
when used in the register indirect address mode.
Loading a zero in the accumulator or when a zero results
from an operation sets the zero flag.
The following operations affect the zero flag.
• Adds (16·bit with carry, 8·bit with/without carry)
•
Subtracts (16·bit with carry, 8-bit with/without carry)
•
•
Logic Operations
Increments and Decrements
•
Rotate and Shifts
•
•
•
•
Rotate Digits
Decimal Adjust
Input Register Indirect
Block I/O (always set after auto repeat block I/O)
•
•
Block Searches
Load of I and R Registers
When used with the special condition jump instruction
(DJNZ) the B register again provides the counter function.
8.4.10 Alternate Configurations
The six 8-bit general purpose registers (B,C,D,E,H,L) will
combine to form three l6-bit registers. This occurs by concatenating the Band C registers to form the BC register, the
D and E registers form the DE register, and the Hand L
registers form the HL register.
• Bit Tests
• Negation of Accumulator
The Z flag has no signficance immediately after the following operations:
Having these l6-bit registers allows 16·bit data handling,
thereby expanding the number of l6-bit registers available
for memory addressing modes. The HL register typically
provides the pointer address for use in register indirect addressing of the memory.
The DE register provides a second memory pointer register
for the NSC800's powerful block transfer operations. The
BC register also provides an assist to the block transfer
operations by acting as a byte-counter for these operations.
• Block Transfers
Other operations do not affect the zero flag.
8.4.8 Sign Flag (S)
The sign flag stores the state of bit 7 (the most-significant bit and sign bit) of the accumulator following an arithmetic operation. This flag is of use when dealing with signed
numbers.
The sign flag is affected by the following operation according to the result:
•
•
Adds (16-bit with carry, 8-bit with/without carry)
Subtracts (16-bit with carry, 8-bit with/without carry)
•
•
Logic Operations
Increments and Decrements
•
Rotate and Shifts
•
Rotate Digits
•
•
Decimal Adjust
Input Register Indirect
8.5 ARITHMETIC-LOGIC UNIT (ALU)
The arithmetic, logic and rotate instructions are performed
by the ALU. The ALU internally communicates with the registers and data buffer on the 8-bit internal data bus.
8.6 INSTRUCTION REGISTER AND DECODER
During an opcode fetch, the first byte of an instruction is
transferred from the data buffer (i.e. its on the internal data
bus) to the instruction register. The instruction register feeds
the instruction decoder, which gated by timing signals, gen·
erates the control signals that read or write data from or to
the registers, control the ALU and provide all required external control signals.
• Block Search
• Load of I and R Registers
• Negation of Accumulator
The S flag has no significance immediately after the following operations:
•
•
Block I/O
Block Transfers
• Bit Tests
Other operations do not affect the sign bit.
9-16
z
en
oCCI
9.0 Timing and Control
o
9.1 INTERNAL CLOCK GENERATOR
o
An inverter oscillator contained on the NSC800 chip pro·
vides all necessary timing signals. The chip operation frequency is equal to one half of the frequency of this oscillator.
ClK
XIN
The oscillator frequency can be controlled by one of the
following methods:
f(XTAl)
2
XOUT
.-J\N'Ir-"
RS
NOTE 1
1. leaving the XOUT pin unterminated and driving the XIN
pin with an externally generated clock as shown in Figure
6. When driving XIN with a square wave, the minimum
duty cycle is 30% high.
2 MHz
< f(XTAL)
2
R~IM!l
Cl
~20
C2~34
pF
pF
(Recommended)
f,.
EXTERNAL
Tl/C/5171-14
FIGURE 7. Use Of Crystal
fIX'N)
ClK
2
CLOCK
The CPU has a minimum clock frequency input (@ XIN) of
300 kHz, which results in 150 kHz system clock speed. All
registers internal to the chip are static, however there is
dynamic logic which limits the minimum clock speed. The
input clock can be stopped without fear of losing any data or
damaging the part. You stop it in the phase of the clock that
has XIN low and ClK OUT high. When restarting the CPU,
precautions must be taken so that the input clock meets
these minimum specification. Once started, the CPU will
continue operation from the same location at which it was
stopped. During DC operation of the CPU, typical current
drain will be 2 mA. This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock. For clock stop circuit, see Figure 8.
TLlG/5171-13
FIGURE 6. Use of External Clock
2. Connecting a crystal with the proper biasing network between XIN and XOUT as shown in Figure 7. Recommended crystal is a parallel resonance AT cut crystal.
Note 1: If the crystal frequency is 2 MHz or less a series resistor, Rs.
(470n to 1500n) should be connected between XOUT and R.
XTAL and Cz. Additionally. the capacitance of Cl and C2 should
be increased by 2 to 3 times the recommended value.
+5V
NSC800 (PIN 9)
CLOCK OUT
5K
TO NSC800
X'N
1" Z1pF l ' Z1pF
1"
TLlC/5171-36
FIGURE 8. Clock Stop Circuit
9·17
•
g
o
en
z
9.0 Timing and Control
(Continued)
During an input or output instruction, the CPU duplicates the
lower half of the address [AD(0-7)] onto the upper address
bus [A(8-15)1. The eight bits of address will stay on A(815) for the entire machine cycle and can be used for chip
selection directly.
Figure 9 illustrates the timing relationship for opcode fetch
cycles with and without a wait state.
9.2 CPU TIMING
The NSC800 uses a multiplexed bus for data and address·
es. The 16·bit address bus is divided into a high·order 8·bit
address bus that handles bits 8-15 of the address, and a
low·order 8·bit multiplexed address/data bus that handles
bits 0-7 of the address and bits 0-7 of the data. Strobe
outputs from the NSC800 (ALE, RD and WR) indicate when
a valid address or data is present on the bus. 10/M indio
cates whether the ensuing cycle accesses memory or I/O.
TLlC/5171-15
FIGURE 9a. Opcode Fetch Cycles without WAIT States
TL/C/5171-16
FIGURE 9b. Opcode Fetch Cycles with WAIT States
9·18
9.0 Timing and Control
ztJ)
o
(Continued)
CI)
During the opcode fetch, the CPU places the contents of
the PC on the address bus. The falling edge of ALE indicates a valid address on the AD(O-7) lines. The WAIT input
is sampled during t2 and if active causes the NSC800 to
insert a wait state (tw). WAIT is sampled again during tw so
that when it goes inactive, the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(O-7) lines. During t3, RFSH goes active and AD(O7) has the dynamic RAM refresh address from register R
and A(8-15) the interrupt vector from register I.
o
o
eLK
ALE
AD(O-7)
iiii
ADI0-7)
A(B-15)
101M. so. S1
Tl/C/S171-17
FIGURE 10a. Memory Read/Write Cycles without WAIT States
TL/C/S171-18
FIGURE 10b. Memory Read and Write with WAIT States
9-19
•
g
u
U)
z
9.0 Timing and Control
(Continued)
Figure t 1 shows the timing for input and output cycles with
and without wait states. The CPU automatically inserts one
wait state into each I/O instruction to allow sufficient time
for an 110 port to decode the address.
Figure 10 shows the timing for memory read (other than
opcode fetchs) and write cycles with and without a wait
_
t
state. The RD stobe is widened by "2 (half the machine
state) for memory reads so that the actual latching of the
input data occurs later.
TLlC/5171-19
FIGURE 11a.lnput and Output Cycles without WAIT States
TL/C/5171-20
'WAIT state automatically inserted during 10 operation.
FIGURE 11b.lnput and Output Cycles with WAIT States
9-20
.-----------------------------------------------------~z
9.0 Timing and Control
(I)
(Continued)
o
Vee
01)
o
o
9.3 INITIALIZATION
RESET IN initializes the NSC800; RESET OUT initializes the
peripheral components. The Schmitt trigger at the RESET
jjiJ input facilitates using an R-C network reset scheme during power up (see Figure 12).
R
10k
To ensure proper power-up conditions for the NSC800, the
following power-up and initialization procedure is recommended:
Vee
NSCBOO
RESET IN
RESET OUT
INDICATES WHEN CPU
IS BEING RESET
GND
1. Apply power (Vee and GND) and set RESET IN active
(low). Allow sufficient time (approximately 30 ms if a crystal is used) for the oscillator and internal clocks to stabilize. RESET IN must remain low for at least 3t state (ClK)
times. RESET OUT goes high as soon as the active
RESET IN signal is clocked into the first flip-flop after the
on-chip Schmitt trigger. RESET OUT signal is available to
reset the peripherals.
TLIC15171-21
FIGURE 12. Power-On Reset
9.4 POWER-SAVE FEATURE
The NSC800 provides a unique power-save mode by the
means of the PS pin. PS input is sampled at the last t state
of the last M cycle of an instruction. After recognizing an
active (low) level on PS, The NSC800 stops its internal
clocks, thereby reducing its power dissipation to one hal'. of
operating power, yet maintaining all register values and internal control status. The NSC800 keeps its oscillator running, and makes the ClK signal available to the syst~m.
When in power-save the ALE strobe will be stopped high
and the address lines [AD(0-7), A(8-15)) will indicate the
next machine address. When PS returns high, the opcode
fetch (or M1 cycle) of the CPU begins in a normal manner.
Note this M1 cycle could also be an interrupt acknowledge
cycle if the NSC800 was interrupted simultaneously with PS
(i.e. PS has priority over a simultaneously occurring interrupt). However, interrupts are not accepted during power
save. Figure 14 illustrates the power save timing.
2. Set RESET IN high. RESET OUT then goes low as the
inactive RESET IN signal is clocked into the first flip-flop
after the on-chip Schmitt trigger. Following this the CPU
initiates the first opcode fetch cycle.
Note: The NSC800 initialization includes: Clear PC to
X'OOOO (the first opcode fetch, therefore, is from memory
location X'OOOO). Clear registers I (Interrupt Vector Base)
and R (Refresh Counter) to X'OO. Clear interrupt control register bits lEA, IEB and IEC. The interrupt control bit lEI is set
to 1 to maintain INS8080AlZ80A compatibility (see INTERRUPTS for more details). The CPU disables maskable interrupts and enters INTR Mode O. While RESET IN is active
(low), the A(8-15) and AD(0-7) lines go to high impedance
(TRI-STATE) and all CPU strobes go to the inactive state
(see Figure 13).
POWER-ON RESET ACTIVE
MANUAL RESET ACTIVE
FiRST ADDRESS
RESET OUT
+..1
RESET (INTERNAL) _ _
CPU SIGNALS
OUTPUT
ALE
"'ZW2~t7ll~m~---+---.:~;::==~:~====i--i---tJr===
I
Z
I
ADRR~ij~ l/ffmununnJ:/H1
I' I
1----t----k~~[:~!~;:===~--r_--_tI(OP!C~-~OO~OOE::
RISIN~R~lo~R~I;~ -I
TLlC15171-74
FIGURE 13. NSC800 Signals During Power-On and Manual Reset
9-21
c
c
co
~
9.0 Timing and Control (Continued)
Z
AO(O-7)----+-----+'"\ ~--,-+----_+---+_+----_1:__----I_---
so. sf(~o)~ ____-;-____-T... ,---+----_+----f:-+===~....I_----I_--ALE
TL/C/5171-2S
FIGURE 14. NSC800 Power-Save
elK
AD(O-7)--+----....r-----,..."
WR_-+_____r-____,...J
~-.rn
RD,
.. -----
ALE
50,51
TL/C/5171-22
'SO, SI during BREO will indicate same machine cycle as during the cycle when Bi'fEQ was accepted.
tz = time states during which bus and control signals are in high impedance mode.
FIGURE 15. Bus Acknowledge Cycle
9.6 INTERRUPT CONTROL
In the event BREa is asserted (low) at the end of an instruction cycle and PS is active simultaneously, the following occurs:
The NSC800 has five interrupt/restart inputs, four are maskable (RSTA, RSTB, RSTC, and INTR) and one is non-maskable (NMI). NMI has the highest priority of all interrupts; the
user cannot disable NMI. After recognizing an active input
on NMI, the CPU stops before the next instruction, pushes
the PC onto the stack, and jumps to address X'0066, where
the user's interrupt service routine is located (I.e., restart to
memory location X'0066). NMI is intended for interrupts requiring immediate attention, such as power-down, control
panel, etc.
1. The NSC800 will go into BACK cycle.
2. Upon completion of BACK cycle if PS is still active the
CPU will go into power-save mode.
9.5 BUS ACCESS CONTROL
Figure 15 illustrates bus access control in the NSC800. The
external device controller produces an active BREa signal
that requests the bus. When the CPU responds with BACK
then the bus and related control strobes go to high impedance (TRI-STATE) and the RFSH signal remains high. It
should be noted that (1) BREa is sampled at the last t state
of any M machine cycle only. (2) The NSC800 will not acknowledge any interrupt/restart requests, and will not peform any dynamic RAM refresh functions until after BREa
input signal is inactive high. (3) BREa Signal has priority
over all interrupt request signals, should BREa and interrupt
request become active simultaneously. Therefore, interrupts
latched at the end of the instruction cycle will be serviced
after a simultaneously occurring BREa. NMI is latched during an active BREa.
RSTA, RSTB and RSTC are restart inputs, which, if enabled,
execute a restart to memory location X'003C, X'0034, and
X'002C, respectively. Note that the CPU response to the
NMI and RST (7\, S, C) request input is basically identical,
except for the restored memory location. Unlike NMI, however, restart request inputs must be enabled.
Figure 16 illustrates NMI and RST interrupt machine cycles.
Ml cycle will be a dummy opcode fetch cycle followed by
M2 and M3 which are stack push operations. The following
instruction then starts from the interrupts restart location.
Nole: Ali does not go low during this dummy opcode fetch. A unique indication of INTA can be decoded using 2 ALEs and RD.
9-22
9.0 Timing and Control
z
en
oco
(Continued)
LAST M CYCLE OF INSTRUCTION
12
~'tr~~i-I--Il
CLK
--ururururururu-r--- ------ ------ ------ ------ ------
NMiDR - - - ,
RSTA,ii,c
ALE
o
o
M1------------.j
13
14
16-
--~~
OF THE
I
-----'-1-'------------- -------. -------. -------. --------1---
PROGRAM
COUNTER
ONTO
'-+----+----4-- ~~~I~~ACK
---4---.j...t
+-___+-.tX\,;,A;;..D(:;.O_-7;.:.)-r~------I-(
AD(O-7) _ _ _
AD(D-7)
)------- - - - - - - -
A(8-1S) _____I -_ _+X"-_~I_--_+"IX---!_---I----_r,-1-.
------ ------ ------
WAIT - - - - - - - - - - - . ------r-~-· ____________________ _
____________
~OOE1)-----
~
~
/
-+___-!II'IX.._ _ _r-__..;,IO;,:./,;;;M_=.:,O,:.:S.:.O_=.;,;I,:,:S;.,1=;-:..1---+-----4)(,'--
IOIM,SO,SI _ _ _
I
I
TLiC/5171-24
Note ,: This is the only machine cycle that does not have an RD, WR, or INTA strobe but will accept a wait strobe.
FIGURE 16. Non-Maskable and Restart Interrupt Machine Cycle
dress. The first byte of each entry in the table is the least
significant (low-order) portion of the address. The programmer must obviously fill this table with the desired addresses
before any interrupts are to be accepted.
The NSC800 also provides one more general purpose interrupt request input, INTR. When enabled, the CPU responds
to INTR in one of the three modes defined by instruction
IMO, IMI, and 1M2 for modes 0, I, and 2, respectively. Following reset, the CPU automatically enables mode O.
Note that the programmer can change this table at any time
to allow peripherals to be serviced by different service routines. Once the interrupting device supplies the lower portion of the pointer, the CPU automatically pushes the program counter onto the stack, obtains the starting address
from the table and does a jump to this address.
The interrupts have fixed priorities built into the NSC800 as:
NMI
0066
(Highest Priority)
RSTA
003C
RSTB
0034
RSTC
002C
(Lowest Priority)
0038
Interrupt Enable, Interrupt Disable. The NSC800 has two
types of interrupt inputs, a non-maskable interrupt and four
software maskable interrupts. The non-maskable interrupt
(NMI) cannot be disabled by the programmer and will be
accepted whenever a peripheral device requests an interrupt. The NMI is usually reserved for important functions
that must be serviced when they occur, such as imminent
power failure. The programmer can selectively enable or
disable maskable interrupts (INT, RSTA, RSTB and RSTC).
This selectivity allows the programmer to disable the maskable interrupts during periods when timing constraints don't
allow program interruption.
There are two interrupt enable flip-flops (IFF, and IFF2) on
the NSC800. Two instructions control these flip-flops. Enable Interrupt (EI) and Disable Interrupt (01). The state of
IFF, determines the enabling or disabling of the maskable
interrupts, while IFF2 is used as a temporary storage location for the state of IFF,.
Interrupt (INTR) Mode 0: The CPU responds to an interrupt
request by providing an INTA (interrupt acknowledge)
strobe, which can be used to gate an instruction from a
peripheral onto the data bus. The CPU inserts two wait
states during the first INTA cycle to allow the interrupting
device (or its controller) ample time to gate the instruction
and determine external priorities (Figure 18). This can be
any instruction from one to four bytes. The most popular
instruction is one-byte call (restart instruction) or a threebyte call (CALL NN instruction). If it is a three-byte call, the
CPU issues a total of three INTA strobes. The last two
(which do not include wait states) read NN.
Nole: If the instruction stored in the ICU doesn't require the PC to be
pushed onto the stack (eq. JP nn), then the PC will not be pushed.
Interrupt (INTR) Mode 1: Similar to restart interrupts except the restart location is X'0038 (Figure 18).
Interrupt (INTR) Mode 2: With this mode, the programmer
maintains a table that contains the 16-bit starting address of
every interrupt service routine. This table can be located
anywhere in memory. When the CPU accepts a Mode 2
interrupt (Figure 17), it forms a 16-bit pOinter to obtain the
desired interrupt service routine starting address from the
table. The upper 8 bits of this pointer are from the contents
of the I register. The lower 8 bits of the pointer are supplied
by the interrupting device with the LSB forced to zero. The
programmer must load the interrupt vector prior to the interrupt occurring. The CPU uses the pOinter to get the two
adjacent bytes from the interrupt service routine starting address table to complete 16-bit service routine starting ad9-23
o
o
CO
(.)
tn
Z
9.0 Timing and Control
(Continued)
A reset to the CPU will force both IFF, and IFF2 to the reset
state disabling maskable interrupts. They can be enabled by
an EI instruction at any time by the programmer. When an EI
instruction is executed, any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed. This single instruction delay is necessary in
situations where the following instruction is a return instruction and interrupts must not be allowed until the return has
been completed. The EI instruction sets both IFF, and IFF2
to the enable state. When the CPU accepts an interrupt,
both IFF, and IFF2 are automatically reset, inhibiting further
interrupts until the programmer wishes to issue a new EI
instruction. Note that for all the previous cases, IFF, and
IFF2 are always equal.
The function of IFF2 is to retain the status of IFF, when a
non-maskable interrupt occurs. When a non-maskable interrupt is accepted, IFF, is reset to prevent further interrupts
until reenabled by the programmer. Thus, after a non-maskable interrupt has been accepted, maskable interrupts are
disabled but the previous state of IFF, is saved by IFF2
SUPPLIED BY I REGISTER
15
8 7
TL/C/5171-27
FIGURE 17. Interrupt Mode 2
9-24
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::!
3
::J
CC
$I)
::J
Q.
elK
C')
o
::J
TIlT
~
o
ALE
"0
o
:aS'
c
ADIO-7}
CD
.e
AIB-1S)
<0
NOTE 2
INTA
'"
U1
RFSH
WAIT
101M. SO. 51
Rli
TL/C/5171-25
'tw is the CPU generated WAIT state in response to an interrupt request.
Note 1: t5 wilt only occur in mode 1 and mode 2. During t5 the stack pointer is decremented.
Note 2: A jump to the appropriate address occurs here in mode 1 and mode 2. The CPU continues gathering data from the interrupting peripheral in mode 0 for a total of 2-4
machine cycles. In mode 0 cycles M2-M4 have only 1 wait state.
FIGURE 18. Interrupt Acknowledge Machine Cycle
OOSOSN
I
0
0
CO
0
(J)
Z
9.0 Timing and Control
(Continued)
so that the complete state of the CPU just prior to the nonmaskable interrupt may be restored. The method of restoring the status of IFF1 is through the execution of a Return
Non-Maskable Interrupt (RETN) instruction. Since this instruction indicates that the non-maskable interrupt service
routine is completed, the contents of IFF2 are now copied
back into IFF1, so that the status of IFF1 just prior to the
acceptance of the non-maskable interrupt will be automatically restored.
Operation
Initialize
EI
INTR
2
3
Name
lEI
IEC
IEB
lEA
0
EI
Interrupt Disable and INTR
Being Serviced
Interrupt Enabled after
next instruction
Interrupt Enabled
RET
•
•
•
NMI
0
Interrupt Disabled
•
•
•
lEI
Interrupt Enabled
RETN
•
TLlC/5171-26
Bit
0
0
•
•
•
The ICR is internal to the NSCBOO CPU, but is addressed
through the I/O space at I/O address port X'BB. Each bit in
the register controls a mask bit dedicated to each maskable
interrupt, RSTA, RSTB, RSTC and INTR. For an interrupt
request to be accepted on any of these inputs, the corresponding mask bit in the ICR must be set (= 1) and IFF1
and IFF2 must be set. This provides the programmer with
control over individual interrupt inputs rather than just a systern wide enable or disable.
lEG
Comment
Interrupt Disabled
Interrupt Enabled after
next instruction
•
•
•
Interrupt Control Register. The interrupt control register
(JCR) is a 4-bit, write only register that provides the programmer with a second level of maskable control over the four
maskable interrupt inputs.
lED
IFF2
0
•
•
•
Figure 19 depicts the status of the flip flops during a sample
series of interrupt instructions.
lEA
IFF1
0
INTR
0
0
Interrupt Disabled
0
0
Interrupt Disabled and NMI
Being Serviced
0
0
Interrupt Disabled and INTR
Being Serviced
•
•
•
Function
Interrupt Enable for INTR
Interrupt Enable for RSTC
Interrupt Enable for RSTB
Interrupt Enable for RSTA
NMI
•
•
For example: In order to enable RSTB, CPU interrupts must
be enabled and IEB must be set.
•
RETN
At reset, lEI bit is set and other mask bits lEA, IEB, IEC are
cleared. This maintains the software compatibility between
NSCBOO and ZBOA.
•
•
•
Execution of an I/O block move instruction will not affect
the state of the interrupt control bits. The only two instructions that will modify this write only register are OUT (C), r
and OUT (N), A.
EI
RET
Interrupt Enabled after
next instruction
Interrupt Enabled
•
•
•
FIGURE 19.IFF1 and IFF2 States Immediately after the
Operation has been Completed
9-26
.--------------------------------------------------------------------------,z
en
oCD
NSC800 SOFTWARE
Q
Q
10.0 Introduction
11.3 IMMEDIATE
The most straightforward way of introducing data to the
CPU registers is via immediate addressing, where the data
is contained in an additional byte of multi-byte instructions.
Example:
Instruction: Load the E register with the constant value
X'7C.
Mnemonic: LD
E,X'7C
Opcode:
This chapter provides the reader with a detailed description
of the NSC800 software. Each NSC800 instruction is described in terms of opcode, function, flags affected, timing,
and addressing mode.
11.0 Addressing Modes
The following sections describe the addressing modes supported by the NSC800. Note that particular addressing
modes are often restricted to certain types of instructions.
Examples of instructions used in the particular addressing
modes follow each mode description.
The 10 addressing modes and 158 instructions provide a
flexible and powerful instruction set.
11.1 REGISTER
The most basic addressing mode is that which addresses
data in the various CPU registers. In these cases, bits in the
opcode select specific registers that are to be addressed by
the instruction.
Example:
Instruction: Load register B from register C
Mnemonic: LD
B,C
Opcode:
t
10111 0,0,0 10,0,1
I
0 , 1, 1, 1, t , t , 0 ,0
+L.--------Selects register E
l- Second Byte
TL/C/5171-52
In this instruction, the E register is addressed with register
addressing, while the constant X'7C is immediate data in the
second byte of the instruction.
11.4 IMMEDIATE EXTENDED
As immediate addressing allows 8 bits of data to be supplied by the operand, immediate extended addressing allows 16 bits of data to be supplied by the operand. These
are in two additional bytes of the instruction.
Example:
Instruction: Load the 16-bit IX register with the constant
value X' ABCD.
Mnemonic: LD
IX,X'ABCD
Opcode:
I
TL/C/5171-50
In this instruction, both the Band C registers are addressed
by opcode bits.
I I
11 I t 0 t I t I t , 0 I 1
f
11.2 IMPLIED
The implied addressing mode is an extension to the register
addressing mode. In this mode, a specific register, the accumulator, is used in the execution of the instruction. In particular, arithmetic operations employ implied addressing, since
the A register is assumed to be the destination register for
the result without being specifically referenced in the opcode.
Example:
Instruction: Subtract the contents of register D from the
Accumulator (A register)
l- Defines opcode
(First Byte)
L . - - - - - - - - S e l e c t s I X register
I 0 I 0 I t , 0 I 0 I 0, 0, 1
l- Defines opcode
(Second Byte)
I t I 1 I 0 I 0 I tIt I 0 I t
l- Constant CD
(Third Byte)
It, 0 I
1I0 , 1I0 I 1I t
l- Constant AB
(Fourth Byte)
D
TL/C/5171-53
In this instruction, register addressing selects the IX register, while the 16-bit quanity X'ABCD is immediate data supplied as immediate extended format.
111°1°111°1°111°1
t
0 ,0 0 ,
.....- - - - - - - X ' 7 C
·a..----Selects register C
L---------Selects register B
L.------------Deflnesopcode
Mnemonic: SUB
Opcode:
I 1, t i t , t , 0 l- First Byte
I
t...
----Selects register D
L.---------Oefines opcode
TUC/5171-51
•
In this instruction, the D register is addressed with register
addressing, while the use of the A register is implied by the
opcode.
9-27
o
o
CIO
11.0 Addressing Modes
z
11.5 DIRECT ADDRESSING
oCJ)
(Continued)
Indexed addressing is particularly useful in dealing with lists
of data.
Example:
Direct addressing is the most straightforward way of ad·
dressing supplies a location in the memory space. Direct
addressing, 16·bits of memory address information in two
bytes of data as part of the instruction. The memory address
could be either data, source of destination, or a location for
program execution, as in program control instructions.
Instruction: Increment the data in memory location X'1020.
The IY register contains X'1000.
Mnemonic: JP
(IY + X'20)
Mnemonic: INC
Opcode:
Example:
Instruction: Jump to location X'0377
r - - - - - - - - S e l e c t s I Y register
X'0377
Opcode:
11 , 1 , 0 , 0 , 0 , 0 , 1 , 1
Defines increment
opcode
-Defines jump opcode
I0I0I 1
:=10=,1=,=1:!::'=1='=0=,=1=,=1=,=1::;1 ] -Constant X'0377
10,0,0,0,0,0,1,11
I
0I 0I 0I 0I 0
I- Displacement to I Y
index register
(Th Ird Byte)
This instruction loads the Program Counter (PC) is loaded
with the constant in the second and third bytes of the in·
struction. The program counter contents are transferred via
direct addressing.
TLlC/5171-54
The indexed addressing mode uses the contents of index
registers IX or IY along with the displacement to form a
pointer to memory.
11.6 REGISTER INDIRECT
Next to direct addressing, register indirect addressing pro·
vides the second most straightforward means of addressing
memory. In register indirect addressing, a specified register
pair contains the address of the desired memory location.
The instruction references the register pair and the register
contents define the memory location of the operand.
Example:
Instruction: Add the contents of memory location X'0254 to
the A register. The HL register contains X'0254.
Mnemonic: ADD
A,(HL)
11.8 RELATIVE
Certain instructions allow memory locations to be ad·
dressed as a position relative to the PC register. These in·
structions allow jumps to memory locations which are off·
sets around the program counter. The offset, together with
the current program location, is determined through a dis·
placement byte included in the instruction. The formation of
this displacement byte is explained more fully in the "In·
structions Set" section.
Opcode
Instruction: Jump to a memory location 7 bytes beyond the
current location.
11,0,0,0,0,1,1,01
Mnemonic: JR
Opcode:
Example:
This instruction uses implied addressing of the A and HL
registers and register indirect addressing to access the data
pointed to by the HL register.
I0
0
0
1
$+7
1
0
0
0 I-Defines relative jump
opcode
L~'__~'~'~~'__~'__'~~'~.
11.7 INDEXED
The most flexible mode of memory addressing is the in·
dexed mode. This is similar to the register indirect mode of
addressing because one of the two index registers (IX or IY)
contains the base memory address. In addition, a byte of
data included in the instruction acts as a displacement to
the address in the index register.
I 0 , 0 , 0 , 0 , 0 , 1 , 0 , 1 I-DiSPlacement to be
applied to the PC
The program will continue at a location seven locations past
the current PC.
9·28
z
en
oCD
11.0 Addressing Modes (Continued)
11.9 MODIFIED PAGE ZERO
Program execution continues at location X'002S after execution of a single-byte call employing modified page zero
addressing.
A subset of NSCSOO instructions (the Restart instructions)
provides a code·efficient single-byte instruction that allows
CALLs to be performed to anyone of eight dedicated locations in page zero (locations X'OOOO to X'OOFF). Normally, a
CALL is a 3-byte instruction employing direct memory addressing.
11.10 BIT
The NSCSOO allows setting, resetting, and testing of individual bits in registers and memory data bytes.
Example:
Example:
Operation: Set bit 2 in the L register
Instruction: Perform a restart call to location X'002S.
Mnemonic: RST
Mnemonic: SET
X'2S
2,L
Opcode:
Opcode:
I
I
11 I 1 I 0 J 0 I 1 J 0 I 1 I 1
Defines restart operation
opcode
11,111,0,111,1,11
I
I- Defines set bit
I
11,110,1,011,0,11
t
I
tL..------Selects one of eight
resta rt locations
t
Selects L register
Selects bit 2 of selected byte
TLlC/5171-56
TLlC/5171-55
Bit addressing allows the selection of bit 2 in the L register
selected by register addressing.
Ip I OOH I OSH I 10H I 1SH I 20H I 2SH I 30H I 3SH I
I t I 000 I 001 I 010 I 011 I 100 I 101 I 110 I 111 I
9-29
o
o
o
o
CO
(.)
12.0 Instruction Set
z
This section details the entire NSC800 instruction set in
terms of
en
The instructions are grouped in order under the following
functional headings:
• Opcode
• 8-Bit Loads
• Instruction
• 16-Bit Loads
• Function
• 8-Bit Arithmetic
• Timing
• 16-Bit Arithmetic
• Addressing Mode
• Bit Set, Reset, and Test
• Rotate and Shift
• Exchanges
• Memory Block Moves and Searches
• Input/Output
• CPU Control
• Program Control
12.1 Instruction Set Index
Alphabetical
Assembly
Mnemonic
Operation
Page
ADCA,ml
ADCA,n
ADCA,r
ADC HL,pp
ADDA,m1
ADDA,n
ADDA,r
ADDHL,pp
ADD IX,pp
ADD IY,pp
ADDss,pp
ANDml
ANDn
ANDr
Add, with carry, memory location contents to Accumulator
Add, with carry, immediate data n to Accumulator
Add, with carry, register r contents to Accumulator
Add, with carry, register pair pp to HL
Add memory location contents to Accumulator
Add immediate data n to Accumulator
Add register r contents to Accumulator
Add register pair pp to HL
Add register pair pp to IX
Add register pair pp to IY
Add register pair pp to contents of register pair ss
Logical 'AND' memory contents to Accumulator
Logical 'AND' immediate data to Accumulator
Logical 'AND' register r contents to Accumulator
9-42
9-40
9-38
9-45
9-42
9-40
9-38
9-45
9-45
9-45
9-45
9-43
9-41
9-38
BITb,ml
BITb,r
Test bit b of location ml
Test bit b of register r
9-47
9-46
CALLcc,nn
CALLnn
CCF
CPm1
CPn
CPr
CPD
CPDR
9-58
9-58
9-40
9-44
9-42
9-39
9-52
9-53
CPL
Call subroutine at location nn if condition cc is true
Unconditional call to subroutine at location nn
Complement carry flag
Compare memory contents with Accumulator
Compare immediate data n with Accumulator
Compare register r to contents with Accumulator
Compare location (HL) and Accumulator, decrement HL and BC
Compare location (HL) and Accumulator, decrement HL and BC;
repeat until BC = 0
Compare location (HL) and Accumulator, increment HL, decrement BC
Compare location (HL) and Accumulator, increment HL, decrement BC;
repeat until BC = 0
Complement Accumulator (1 's complement)
DAA
DECm1
DECr
DECrr
Decimal adjust Accumulator
Decrement data in memory location ml
Decrement register r contents
Decrement register pair rr contents
9-40
9-44
9-39
9-46
CPI
CPIR
9-30
9-52
9-53
9-39
z
(I)
12.1 Instruction Set Index (Continued)
0
CD
0
0
Alphabetical
Assembly
Mnemonic
Operation
Page
DI
DJNZ,d
Disable interrupts
Decrement B and jump relative B oF 0
9-56
9-58
EI
EX (SP),ss
EXAF,A'F'
EXDE,HL
EXX
Enable interrupts
Exchange the location (SP) with register ss
Exchange the contents of AF and A'F'
Exchange the contents of DE and HL
Exchange the contents of BC, DE and HL with the contents
of B'C, D'E' and H'L', respectively
9-56
9-52
9-51
9-51
9-52
HALT
Halt (wait for interrupt or reset)
9-56
IMO
IM1
1M2
INA,(n)
INr,(C)
INCm1
INCr
INCrr
IND
INDR
INI
INIR
Set interrupt mode 0
Set interrupt mode 1
Set interrupt mode 2
Load Accumulator with input from device (n)
Load register r with input from device (C)
Increment data in memory location m1
Increment register r
Increment contents of register pair rr
Load location (HL) with input from port (C), decrement HL and B
Load location (HL) with input from port (C), decrement HL and B; repeat until B = 0
Load location (HL) with input from port (C), increment HL, decrement B
Load location (HL) with input from port (C), increment HL, decrement B;
repeat until B = 0
9-56
9-57
9-57
9-54
9-54
9-44
9-39
9-45
9-54
9-56
9-54
9-55
JPcc,nn
JPnn
JP(ss)
JRd
JR kk,d
Jump to location nn, if condition cc is true
Unconditional jump to location nn
Unconditional jump to location (ss)
Unconditional jump relative to PC + d
Jump relative to PC + d, if kk true
9-57
9-57
9-57
9-57
9-57
LDA,I
LDA,m2
LDA,R
LDI,A
LDm1,n
LDm1.r
LDm2.A
LD (nn),rr
Load Accumulator with register I contents
Load Accumulator from location m2
Load Accumulator with register R contents
Load register I with Accumulator contents
Load memory with immediate data n
Load memory from register r
Load memory from Accumulator
Load memory location nn with register pair rr
Load register r from memory
Load register with immediate data n
Load register R from Accumulator
Load destination register rd from source register rs
Load register pair rr from memory location nn
Load register pair rr with immediate data nn
Load SP from register pair ss
Load location (DE) with location (HL), decrement DE, Hl. and BC
Load location (DE) with location (HL), decrement DE, HL and BC; repeat until BC = 0
Load location (DE) with location (HL), increment DE and HL, decrement BC
Load location (DE) with location (HL), increment DE and HL, decrement BC;
repeat until BC = 0
9-34
9-35
9-34
9-34
9-35
9-34
9-35
9-36
9-35
9-34
9-34
9-34
9-37
9-36
9-36
9-52
9-53
9-52
9-53
Negate Accumulator (2's complement)
No operation
9-40
9-56
LDr,m1
LDr,n
LDR,A
LD rd,rs
LD rr,(nn)
LD rr,nn
LDSP,ss
LDD
LDDR
LDI
LDIR
NEG
NOP
9-31
II
g
U
tn
Z
12.1 Instruction Set Index (Continued)
Alphabetical
Assembly
Mnemonic
Operation
Page
9-42
9-41
9-39
9-56
9-55
OUT (C),r
OUT (n),A
OUTO
OUTI
Logical 'OR' of memory location contents and accumulator
Logical 'OR' of immediate data n and Accumulator
Logical 'OR' of register r and Accumulator
Load output port (C) with location (HL), decrement HL and B; repeat until B = 0
Load output port (C) with location (HL), increment HL, decrement B;
repeat until B = 0
Load output port (C) with register r
Load output port (n) with Accumulator
Load output port (C) with location (HL), decrement HL and B
Load output port (C) with location (HL), increment HL, decrement B
POPqq
PUSHqq
Load register pair qq with top of stack
Load top of stack with register pair qq
9-37
9-37
RESb,ml
RESb,r
RET
RETcc
RETI
RETN
RLml
RLr
RLA
RLCml
RLCr
RLCA
RLD
RRml
RRr
RRA
RRCml
RRCr
RRCA
RRD
RSTP
Reset bit b of memory location ml
Reset bit b of register r
Unconditional return from subroutine
Return from subroutine, if cc true
Unconditional return from interrupt
Unconditional return from non-maskable interrupt
Rotate memory contents left through carry
Rotate register r left through carry
Rotate Accumulator left through carry
Rotate memory contents left circular
Rotate register r left circular
Rotate Accumulator left circular
Rotate digit left and right between Accumulator and memory (HL)
Rotate memory contents right through carry
Rotate register r right through carry
Rotate Accumulator right through carry
Rotate memory contents right circular
Rotate register r right circular
Rotate Accumulator right circular
Rotate digit right and left between Accumulator and memory (HL)
Restart to location P
9-46
9-46
9-58
9-58
9-58
9-59
9-49
9-47
9-47
9-49
9-47
9-47
9-51
9-50
9-48
9-50
9-49
9-47
9-48
9-51
9-59
SBCA,ml
SBCA,n
SBCA,r
SBCHL,pp
SCF
SETb,ml
SETb,r
SLAml
SLAr
SRAml
SRAr
SRLml
SRLr
SUBml
SUBn
SUBr
Subtract, with carry, memory contents from Accumulator
Subtract, with carry, immediate data n from Accumulator
Subtract, with carry, register r from Accumulator
Subtract, with carry, register pair pp from HL
Set carry flag
Set bit b in memory location ml contents
Set bit b in register r
Shift memory contents left, arithmetic
Shift register r left, arithmetic
Shift memory contents right, arithmetic
Shift register r right, arithmetic
Shift memory contents right, logical
Shift register r right, logical
Subtract memory contents from Accumulator
Subtract immediate data n from Accumulator
Subtract register r from Accumulator
9-42
9-41
9-38
9-45
9-40
9-46
9-46
9-50
9-48
9-50
9-48
9-50
9-48
9-42
9-41
9-38
XORml
XORn
XORr
Exclusive 'OR' memory contents and Accumulator
Exclusive 'OR' immediate data n and Accumulator
Exclusive 'OR' register r and Accumulator
9-44
9-41
9-39
ORml
ORn
ORr
OTOR
OTIR
9-32
9-54
9-55
9-55
9-54
z
en
12.0 Instruction Set (Continued)
0
0)
12.2 INSTRUCTION SET MNEMONIC NOTATION
12.3 ASSEMBLED OBJECT CODE NOTATION
Register Codes:
Register
rp
Register
Register
rs
BC
B
000
00
00
BC
001
C
01
DE
DE
01
0
010
10
HL
10
HL
011
E
11
SP
11
AF
In the following instruction set listing, the notations used are
shown below.
b:
Designates one bit in a register or memory location.
Bit address mode uses this indicator.
cc:
Designates condition codes used in conditional
Jumps, Calls, and Return instruction; may be:
NZ = Non-Zero (Z flag = 0)
100
101
111
Z = Zero (Z flag=1)
NC = Non-Carry (C flag = 0)
C = Carry (C flag = 1)
PO = Parity Odd or No Overflow (PIV=O)
PE = Parity Even or Overflow (P IV = 1)
P = Positive (S = 0)
d:
kk:
m1:
m2:
n:
nn:
p:
pp:
qq:
r:
rr:
ss:
XL:
XH:
( ):
H
L
A
pp
00
01
10
11
Conditions Codes:
cc
Mnemonic
000
NZ
001
Z
010
NC
011
C
100
PO
101
PE
110
P
111
M
Mnemonic
kk
00
NZ
01
Z
10
NC
11
C
M = Negative (S = 1)
Designates an 8-bit signed complement displacement. Relative or indexed address modes use this
indicator.
Subset of cc condition codes used in conjunction with
conditional relative jumps; may be NZ, Z, NC or C.
Designates (HL), (IX+d) or (IY+d). Register indirect
or indexed address modes use this indicator.
Designates (BC), (DE) or (nn). Register indirect or direct address modes use this indicator.
Any 8-bit binary number.
Any 16-bit binary number.
Designates restart vectors and may be the hex values
0, 8, 10, 18, 20, 28, 30 or 38. Restart instructions
employing the modified page zero addressing mode
use this indicator.
Designates the BC, DE, SP or any 16-bit register used
as a destination operand in 16-bit arithmetic operations employing the register address mode.
Designates BC, DE, HL, A, F, IX, or IY during operations employing register address mode.
Designates A, B, C, 0, E, H or L. Register addreSSing
modes use this indicator.
Designates BC, DE, HL, SP, IX or IY. Register addreSSing modes use this indicator.
Designates HL, IX or IY. Register addressing modes
use this indicator.
Subscript L indicates the lower-order byte of a 16-bit
register.
Subscript H indicates the high-order byte of a 16-bit
register.
parentheses indicate the contents are considered a
pointer address to a memory or 1/0 location.
Restart Addresses:
t
T
X'OO
000
001
X'08
010
X'10
X'18
011
X'20
100
X'28
101
X'30
110
111
X'38
9-33
Register
BC
DE
IX
SP
qq
00
01
10
11
Register
BC
DE
HL
AF
True Flag Condition
Z=O
Z=1
C=O
C=1
PIV=O
PIV=1
S=O
S=1
True Flag Condition
Z=O
Z=1
C=O
C=1
0
0
gr-------------------------------------------------------------~
CD
12.4 8-Bit Loads
z
REGISTER TO REGISTER
otI)
765
LD
rd, ra
Load register rd with rs:
,rd,
Timing:
Addressing Mode:
I
fs
o
Addressing Mode:
M cycles-1
Tstates-4
Register
LD
R,A
Load Refresh register (R) with contents of the Accumulator.
R - A
No flags affected
765 4 3 2 1 0
11,1,1,0,1,1,0,11
10,1,0,0,1,1,1,11
Timing:
M cycles - 2
T states - 9 (4, 5)
Register
Addressing Mode:
LD
r,n
Load register r with immediate data n.
r n
No flags affected
7 6 5 4 3 2 1 0
10,01
10,1,0,1,0,1,1,11
M cycles - 2
T states - 9 (4, 5)
Register
r,
11, 1 ,01
n
1
1
Timing:
M cycles-2
T states - 7 (4, 3)
Source - Immediate
Destination - Register
LD
I,A
Load Interrupt vector register (I) with the contents of A.
Addressing Mode:
I - A
7 6 5
REGISTER TO MEMORY
432
No flags affected
1 0
LD
11,1,1,0,1,1,0,11
Addressing Mode:
M cycles - 2
T states - 9 (4, 5)
Register
10 , 1 , 1 , 1 , 0 1
R
r,
1 LD (HL), r
M cycles- 2
T states - 7 (4,3)
Source - Register
Addressing Mode:
Destination - Register Indirect
76543210
LD (IX + d), r(for Nx = 0)
1 1 Nx 1 1 1 0 1
"
'"
, 'LD(IY+d),r(forNx=1)
Timing:
LD
A,R
Load Accumulator with contents of R register.
A -
m" r
Load memory from reigster r.
m1 - r
No flags affected
7 6 5 4 3 2 1 0
10,1,0,0,0,1,1,11
Timing:
I
M cycles - 2
T states - 9 (4, 5)
Register
!
11,1,1,0,1,1,0,11
Addressing Mode:
0
Timing:
LD
A,I
Load Accumulator with the contents of the I register.
A I
S: Set if negative result
Z: Set if zero result
H: Reset
PIV: Set according to IFF2 (zero if
interrupt occurs during operation)
N: Reset
C: Not affected
7 6 5 4 3 2 1 0
Timing:
321
10, 1 ,0, 1 , 1 , 1 , 1 , 1
No flags affected
rd rs
7654321
10 , 1 1
4
11,1,1,0,1,1,0,11
S: Set if negative result
Z: Set if zero result
H: Reset
PIV: Set according to IFF2 (zero if
interrupt occurs during operation)
N: Reset
C: Not affected
I
10,1,
I
,1,01
r,
d
Timing:
Addressing Mode:
9-34
M cycles- 2
T states - 19 (4, 4, 3, 5, 3)
Source - Register
Destination - Indexed
z
~
CD
12.4 8-Bit Loads (Continued)
m2 +- A
7
6
5
4
3
2
0
1
0
1
LD (BC), A
7 6 5 4 3 2 1 0
LD (DE), A
I°,1 I
Timing:
M cycles-2
Addressing Mode:
T states - 7 (4, 3)
Source - Register (Implied)
Destination -
7
6
LD
r,ml
Load register r from memory location ml.
r +- m1
No flags affected
No flags affected
I° ° ° ° ° °I
10,0,0,1,0,0,1 ,°I
543
2
I:)
I:)
MEMORY TO REGISTER
LD
m2,A
'Load memory from the Accumulator.
11, 1 ,
°
1
LD R, (HL)
M cycles-2
T states-7 (4, 3)
Addressing Mode:
Source-Register Indirect
Destination-Register
Register Indirect
7 6
1 0
I°,°,2 , 2 , °,°,1 , °ILD (nn), A
r,
Timing:
5
4 3 2 1 0 LDr, (IX
11 , 1 , Nx , 1 , 1 , 1 ,
°,
1 1 LD r, (IV
+ d)(forNx=O)
+ d)(for Nx= 1)
n (low-order byte)
d
n (high-order byte)
Timing:
M cycles-4
Addressing Mode:
T states - 3 (4, 3, 3, 3)
Source - Register (Implied)
Destination - Direct
4
3
2
1
Source-Indexed
Destination-Register
A +- m2
7
I
LD(HL), n
M cycles-3
T states-10 (4, 3, 3)
Addressing Mode:
Source-Immediate
Destination-Register Indirect
11,l,NX,l,l,l,O,l
5
No flags affected
4
3
2
1
0
°,°,°,°, °, °
1 ,
1 ,
Timing:
Timing:
43210
6
1
LDA, (BC)
LD A, (DE)
10,0,0,1,1,0,1,01
n
5
Addressing Mode:
No flags affected
0
I°,°,1 , 1 , °,1 , 1 , °I
7 6
M cycles-5
T states-19 (4, 4, 3, 5, 3)
A,m2
LD
Load the Accumulator from memory location m2.
LD
ml,n
Load memory with immediate data.
ml +- n
7 6 5
Timing:
M cycles-2
T states-7 (4, 3)
Source-Register Indirect
Destination-Register (Implied)
Addressing Mode:
LD (IX
+ d), n(for Nx =
0)
LD (IV
+ d), n(for Nx =
1)
7
6
5
4
3
2
1 0
I°,°,1 , 1 , 1 , °,1 , °1
n (low-order byte)
LD A, (nn)
1
10,0,
n (high-order byte)
d
M cycles-4
T states-13 (4, 3, 3, 3)
Addressing Mode:
Source-Immediate Extended
Destination-Register (Implied)
n
Timing:
M cycles-5
Addressing Mode:
Source-Immediate
T states-19 (4,4,3,5,3)
Destination-Indexed
9-35
1
Timing:
12.5 16-Bit Loads
REGISTER TO REGISTER
REGISTER TO MEMORY
LD
rr, nn
Load 16-bit register pair with immediate data.
rr, +- nn
No flags affected
76543210
LDBC,nn
LD
(nn), rr
Load memory location nn with contents of 16-bit register, rr.
(nn) +- rrL
No flags affected
(nn + 1) +- rrH
765 432 1 0
LD (nn), HL
10,0,1,0,0,0,1,01 (note an alternate
opcode below)
I°,°I
1
rp
I°,°,°,1 I
n (low-order byte)
LD DE, nn
LD HL, nn
1 LD SP, nn
n (low-order byte)
n (high-order byte)
n (high-order byte)
Timing:
M cycles-3
T states-10 (4, 3, 3)
Source-Immediate Extended
Addressing Mode:
Destination-Register
7 6 5 43210
LD IX, nn (for NX = 0)
Timing:
Addressing Mode:
7
6
5
4
3
2
1
M cycles-5
T states-16 (4, 3, 3, 3, 3)
Source-Register
Destination-Direct
0
LD (nn), BC
°, °,
°, I I°,°,
LD IV, nn (for NX = 1)
1,1,1,
0,0,1,0,0,0,0,1
1
1,1,
rp
1
LD (nn), DE
LD (nn), HL
1 ,1
LD (nn), SP
n (low-order byte)
n (low-order byte)
n (high-order byte)
n (high-order byte)
M cycles-4
T states-14 (4, 4, 3, 3)
Source-Immediate Extended
Destination-Register
Timing:
Addressing Mode:
M cycles-6
T states-20 (4, 4, 3, 3, 3, 3)
Addressing Mode:
Source-Register
Destination-Direct
7 6 5 43210
LD (nn), IX (for Nx = 0)
1 , 1 , NX , 1 , 1 , 1 ,
1
LD (nn) IV (for Nx = 1)
Timing:
LD
SP,55
Load the SP from 16-bit register ss.
SP +- ss
No flags affected
765 4 3 2 1 0
11 , 1 , 1 , 1 , 1 ,
°,°,
11
°,
LD SP, HL
Timing:
M cycles-1
Tstates-6
Addressing Mode:
Source-Register
Destination-Register (Implied)
7 6 5 43210
LD SP, IX (for NX = 0)
n (low-order byte)
n (high-order byte)
Timing:
LD SP,IV (for Nx = 1)
Timing:
Addressing Mode:
Addressing Mode:
M cycles-2
T states-10 (4, 6)
Source-Register
Destination-Register (Implied)
9-36
M cycles-6
T states-20 (4, 4, 3, 3, 3, 3)
Source-Register
Destination-Direct
12.5 16-Bit Loads (Continued)
7
PUSH
qq
Push the contents of register pair qq onto the memory
stack.
(SP - 1) ~ qqH
No flags affected
(SP - 2) ~ qqL
SP ~ SP - 2
7 6 5 4 3 2 1 0 PUSH BC
1 1 1 rs
1
. , . ,
10
.
,
1
,
°
,
1 1 PUSH DE
. PUSH HL
7 6
5
4
3
2
11 , 1 , Nx , 1 , 1 , 1 ,
°
°,
1
Timing:
Addressing Mode:
11
2
1 0
LD
LD
LD
LD
BC, (nn)
DE, (nn)
HL, (nn)
SP, (nn)
n (high-order byte)
M cycles-6
T states-20 (4, 4, 3, 3, 3, 3)
Source-Direct
Addressing Mode:
Destination-Register
7 6 5 43210
LD IX, (nn)(for Nx = 0)
Timing:
M cycles-3
T states-11 (5, 3, 3)
Source-Register
Destination-Register Indirect
(Stack)
Addressing Mode:
3
n (low-order byte)
PUSHAF
Timing:
654
LD IV, (nn) (for Nx = 1)
PUSH IX (for Nx=O)
PUSH IV (for Nx= 1)
n (low-order byte)
n (high-order byte)
M cycles-3
T states-15 (4, 5, 3, 3)
Source-Register
Destination-Register Indirect
(Stack)
Timing:
M cycles-6
T states-20 (4, 4, 3, 3, 3, 3)
Source-Direct
Destination-Register
Addressing Mode:
POP
qq
Pop the contents of the memory stack to register qq.
No flags affected
qqL ~ (SP)
qqH ~ (SP + 1)
SP ~ SP + 2
7 6 5 4 3 2 1 0 POP BC
MEMORY TO REGISTER
LD
rr, (nn)
Load 16-bit register from memory location nn.
rrL ~ (nn)
No flags affected
rrH ~ (nn + 1)
7 6 5 4 3 2 1 0
LD HL, (nn)
10,0,1,0,0,0,1,01 (note an alternate
opcode below)
n (low-order byte)
1
. 111
, .
r,s
10
. ,
°°
,
DE
, 11
. POP
POP HL
POPAF
M cycles-3
T states-10 (4, 3, 3)
Source-Register Indirect
Addressing Mode:
(Stack)
Destination-Register
7 6 5 43210
POP IX (for Nx=O)
11 , 1 , Nx , 1 , 1 , 1 ,
11
POP IV (for Nx= 1)
Timing:
n (high-order byte)
Timing:
Addressing Mode:
M cycles-5
T states-16 (4, 3, 3, 3, 3)
Source-Direct
Destination-Register
°,
Timing:
Addressing Mode:
9-37
M cycles-4
T states-14 (4,4,3,3)
Source-Register Indirect
(Stack)
Destination-Register
z
en
n
co
o
o
CI
CI
CD
(,)
12.6 a-Bit Arithmetic
Z
REGISTER ADDRESSING ARITHMETIC
rn
Op
ADD
ADC
INC
SUB
SBC
DEC
NEG
7
Hex
Hex
Value
Value Number
C
H
C
In
In
Added After
Before
Before
Upper
Lower
To
DAA
DAA
DAA
Digit
Digit
Byte
(Bits 7-4)
(Bits 3.0)
0
0
0
0
0
0
0
0
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0
0
1
0
0
0-9
0-8
7-F
6-F
0
0
0
0
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
00
06
06
60
66
66
60
66
66
0
0
0
0-9
6-F
0-9
6-F
00
FA
AO
9A
0
0
6
5
4
3
2
Addressing Mode:
Destination-Implied
SUB
r
Subtract the contents of register r from the Accumulator.
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
PIV: Set if result exceeds 8-bit 2's
complement range
N: Set
C: Set according to borrow
7 6 543 2 1 0
I
M cycles-1
Addressing Mode:
T states-4
Source-Register
Destination-Implied
I
r!
Timing:
M cycles-1
Addressing Mode:
Tstates-4
Source-Register
Destination-Implied
SBC
A,r
Subtract contents of register r and the carry bit C from the
Accumulator.
A +- A - r - CY
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
PIV: Set if result exceeds 8-bit 2's
complement range
N:Set
c: Set according to borrow
1
Timing:
I
M cycles-1
Tstates-4
Source-Register
7 6 5 432 1 0
,r,
0
Timing:
ADD
A,r
Add contents of register r to the
Accumulator.
A +- A + r
S: Set if negative result
Z: Set if zero result
H: Set if carry from bit 3
PIV: Set according to overflow
condition
N: Reset
C: Set if carry from bit 7
11,0,0,0,01
1
11,o,o,o,l1,r,
765
ADC
A,r
Add contents of register r, plus the carry flag, to the Accumulator.
S: Set if negative result
A +- A + r + CY
Z: Set if zero result
H: Set if carry from bit 3
PIV: Set if result exceeds 2's complement range
N: Reset
C: Set if carry from bit 7
4
3
2
1 0
Timing:
M cycles-1
Addressing Mode:
T states-4
Source-Register
Destination-Implied
AND
r
Logically AND the contents of the r register and the Accumulator.
S: Set if result is negative
A +- A 1\ r
Z: Set if result is zero
H:Set
PIV: Set if result parity is even
N: Reset
C: Reset
9-38
12.6 8-Bit Arithmetic
z
CJ)
o
(Continued)
7 6 5 4 3 2 1 0
11,0,1,0,01
7 6 5 4
r,
10,01
Timing:
M cycles-1
Addressing Mode:
T states-4
Source-Register
Destination-Implied
M cycles-1
Addressing Mode:
T states-4
Source-Register
Destination-Implied
11 , 0,
,0,
o
Timing:
M cycles-1
Addressing Mode:
T states-4
Source-Register
r ,
Addressing Mode:
Destination-Implied
Decrement the contents of register r.
S: Set if result is negative
Z: Set if result is zero
H: Set according to a borrow from
bit 4
P/V: Set only if r was X'80 prior to
operation
N: Set
C:N/A
7
Addressing Mode:
T states-4
Source-Register
Destination-Implied
r
DEC
r ,
M cycles-1
M cyc1es-1
T states-4
Source-Register
Timing:
1 0
Timing:
6
10, 0 1
INC
Increment register r.
r +- r + 1
o
,0,01
Destination-Register
XOR
r
Logically exclusively OR the contents of the r register with
the Accumulator.
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
5 432
Q)
0
1
Timing:
7 6
r,
1
CP
r
Compare the contents of register r with the Accumulator
and set the flags accordingly.
S: Set if result is negative
A - r
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2's
complement range
N: Set
C: Set according to borrow
7 6 5 4 3 2 1 0
OR
Logically OR the contents of the r register and the Accumulator.
A +- A V r
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 543 2 1 0
r,
3 2
5
4
3
r ,
2
1
0
,0 , 1 1
Timing:
M cycles-1
Addressing Mode:
T states-4
Source-Register
Destination-Register
CPL
Complement the Accumulator (1 's complement).
A +- A
S:N/A
S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
Z: N/A
P/V: Set only if r was X'7F before
H: Set
operation
P/V: N/A
N: Reset
N: Set
C:N/A
C: N/A
9-39
•
C)
C)
co
o
(/)
z
r---------------------------------------------------------------------------------12.6 8-Bit Arithmetic
7 6 5 4 3 2
1
(Continued)
0
DAA
Adjust the Accumulator for BCD addition and subtraction
operations. To be executed after BCD data has been operated upon the standard binary ADD, ADC, INC, SUB, SBC,
DEC or NEG instructions (see "Register Addressing Arithmetic" table).
10,0,1,0,1,1,1,11
Timing:
M cycles-1
Addressing Mode:
Tstates-4
Implied
S: Set according to bit 7 of result
NEG
Negate the Accumulator (2's complement).
Z: Set if result is zero
A -
H: Set according to instructions
0 - A
S: Set if result is negative
PIV: Set according to parity of result
Z: Set if result is zero
N:N/A
H: Set according to borrow from
bit 4
C: Set according to instructions
7
PIV: Set only if Accumulator was
X'80 prior to operation
5
4
3
2
1
0
10,0,1,0,0,1,1,11
N:Set
7 6 5 4 3 2
6
M cycles-1
Timing:
C: Set only if Accumulator was not
X'OO prior to operation
1 0
Tstates-4
Addressing Mode:
Implied
IMMEDIATELY ADDRESSED ARITHMETIC
11,1,1,0,1,1,0,11
ADD
A,n
10,1,0,0,0,1,0,01
Add the immediate data n to the Accumulator.
Timing:
A -
M cycles-2
Addressing Mode:
A
+
S: Set if result is negative
n
T states-8 (4, 4)
Z: Set if result is zero
Implied
H: Set if carry from bit 3
PIV: Set if result exceeds 8-bit 2's
complement range
CCF
Complement the carry flag.
CY-CY
S:N/A
Z:N/A
7 6 5 4 3 2
N: Reset
C: Set if carry from bit 7
1 0
H: Previous carry
11,1,0,0,0,1,1,01
PIV:N/A
7 6 5 4 3 2
N: Reset
C: Complement of previous carry
1 0
n
1
M cycles-2
Timing:
T states-7 (4, 3)
10,0,1,1,1,1,1,11
Addressing Mode:
M cycles-1
Timing:
Source-Immediate
Destination-Implied
T states-4
ADC
A,n
Add, with carry, the immediate data n and the Accumulator.
Implied
Addressing Mode:
SCF
A -
Set the carry flag.
CY -
Z:N/A
4
3
2
7
M cycles-1
T states-4
Addressing Mode:
S: Set if result is negative
C: Set according to carry from bit
C: Set
1 0
10,0, 1 , 1 , 0 , 1 , 1 , 1 1
Timing:
CY
N: Reset
N: Reset
5
+
PIV: Set if result exceeds 8-bit 2's
complement range
PIV:N/A
6
n
H: Set if carry from bit 3
H: Reset
7
+
Z: Set if result is zero
S:N/A
1
A
Implied
9-40
12.6 8-Bit Arithmetic
7
6
5
4
3
2
1
z
(J)
oCD
(Continued)
0
o
o
n
AND
11,1,0,0,1,1,1,01
The immediate data n is logically AND'ed to the Accumulator.
A +- A 1\ n
n
Timing:
S: Set if result is negative
Z: Set if result is zero
M cycles-2
H: Set
T states-7 (4, 3)
Addressing Mode:
PIV: Set if result parity is even
Source-Immediate
N: Reset
Destination-Implied
C: Reset
n
SUB
7
Subtract the immediate data n from the Accumulator.
A +- A - n
6
5
4
3
Z: Set if result is zero
n
M cycles-2
Timing:
P IV: Set if result exceeds 8-bit 2's
complement range
T states-7 (4, 3)
N: Set
Addressing Mode:
C: Set according to borrow
condition
6
5
432
1
OR
0
n
The immediate data n is logically OR'ed to the contents of
the Accumulator.
A +- A V s
S: Set if result is negative
n
Z: Set if result is zero
Timing:
M cycles-2
Addressing Mode:
Source-Immediate
H: Reset
PIV: Set if result parity is even
T states-7 (4, 3)
N: Reset
C: Reset
Destination-Implied
7 6 5 4 3 2 1 0
A,n
11,1,1,1,0,1,1,01
Subtract, with carry, the immediate data n from the Accumulator.
A +- A - n - CY
n
S: Set if result is negative
Z: Set if result is zero
M cycles-2
Addressing Mode:
Source-Immediate
T states-7 (4, 3)
Destination-Implied
N: Set
XOR
C: Set according to borrow
condition
6
5
4
3
2
1
A +- A
(!l
n
S: Set if result is negative
Z: Set if result is zero
H: Reset
n
Addressing Mode:
n
The immediate data n is exclusively OR'ed with the Accumulator.
0
11,1,0,1,1,1,1,01
Timing:
1
Timing:
H: Set if borrow from bit 4
PIV: Set if result exceeds 8-bit 2's
complement range
7
Source-Immediate
Destination-Implied
11,1,0,1,0,1,1,01
SBC
1 0
11,1,1,0,0,1,1,01
S: Set if result is negative
H: Set if borrow from bit 4
7
2
PIV: Set if result parity is even
M cycles-2
N: Reset
T states-7 (4, 3)
C: Reset
Source-Immediate
Destination-Implied
9-41
C)
C)
co
o
z
U)
12.6 8-Bit Arithmetic
7
6
5
4
3
2
11,1,1,0,1,1
1
(Continued)
0
7
,01
6
n
11,0,
Timing:
5
4
3
2
°
ADD A, (IX
+ d)(for Nx = 0)
1 I ADD A, (lY
+ d) (for Nx = 1)
1 0
11 , 1 , Nx , 1 , 1 , 1 ,
°,
,0,0,1,1,01
M cycles-2
d
T states-7 (4, 3)
Addressing Mode:
M cycles-5
Timing:
Source-Immediate
T states-19 (4, 4, 3, 5, 3)
Destination-Implied
CP
Source-Indexed
Addressing Mode:
n
Destination-Implied
Compare the immediate data n with the contents of the Accumulator via subtraction and return the appropriate flags.
The contents of the Accumulator are not affected.
A - n
ADC
A,m1
Add the contents of the memory location m1 plus the carry
to the Accumulator.
A A + m1 + CY S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
PIV: Set if result exceeds 8-bit 2's
complement range
N: Reset
C: Set according to carry from bit
7
7 6 543 2 1 0
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
7 6 5 4 3
PIV: Set if result exceeds 8-bit 2's
complement range
N: Set
C: Set according to borrow condition
2 1 0
11,0,0,0,1,1,1
n
I
T states-7 (4, 3)
T states-7 (4, 3)
Addressing Mode:
Addressing Mode:
Destination-Implied
76543210
11 , 1 , Nx , 1 , 1 , 1 ,
ADD
A,m1
Add the contents of the memory location m1 to the Accumulator.
+
m1
11,0,
S: Set if result is negative
Z: Set if result is zero
°
Addressing Mode:
+ d) (for Nx=l)
Source-Indexed
Destination-Implied
SUB
m1
Subtract the contents of memory location m1 from the Accumulator.
ADD A, (HL)
A -
M cycles-2
T states-7 (4, 3)
Addressing Mode:
+ d) (for Nx= 0)
ADCA, (lY
T states-19 (4, 4, 3, 5, 3)
1 0
_0..J,~1--,-,_l..J'L...0--,1
Timing:
ADC A, (IX
M cycles-5
Timing:
7
LI_1...1'_0-,-,_0...1,_0-,-,
11
,0,1,1,1,01
C: Set according to carry from bit
432
°,
d
H: Set if carry from bit 3
PIV: Set if result exceeds 8-bit 2's
complement range
N: Reset
765
Source-Register Indirect
Immediate
MEMORY ADDRESSED ARITHMETIC
A
ADC A, (HL)
M cycles-2
M cycles-2
Timing:
A -
,°
Timing:
A - m1
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
PIV: Set if result exceeds 8-bit 2's
complement range
N:Set
C: Set according to borrow condition
Source-Register Indirect
Destination-Implied
9-42
z
12.6 8-Bit Arithmetic
7
6
5
4
3
2
1
en
(")
CO
(Continued)
0
11 , 0 , 0 , 1 , 0 , 1 , 1 , 0
I
AND
m1
The data in memory location m1 is logically AND'ed to the
Accumulator.
SUB (HL)
Timing:
M cycles-2
Addressing Mode:
T states-7 (4, 3)
Source-Register Indirect
A
~
A 1\ m1
S: Set if result is negative
Z: Set if result is zero
H: Set
Destination-I mplied
PIV: Set if result parity is even
76543210
11 , 1 , Nx , 1 , 1 , 1 , 0 , 1
+ d) (for Nx=O)
SUB (IY + d) (for Nx = 1)
SUB (IX
I
N: Reset
7
6
5
4
3
2
1
C: Reset
0
11 ,0, 0 ,1 ,0,1 ,1 ,01
11 , 0 , 1 , 0 , 0 , 1 , 1 , 0
d
Source-Register Indirect
Addressing Mode:
Destination-Implied
Source-Indexed
7
Destination-Implied
6
5
43210
11,1, Nx, 1 ,1 ,1 ,0,1
SBC
A,m1
Subtract, with carry, the contents of memory location m1
from the Accumulator.
A ~ A - m1 - CY
S: Set if result is negative
H: Set if carry from bit 3
Destination-Implied
OR
m1
The data in memory location m1 is logically OR'ed with the
Accumulator.
SBC A, (HL)
A ~ A V m1
S: Set if result is negative
Z: Set if result is zero
M cycles-2
T states-7 (4, 3)
Addressing Mode:
H: Reset
PIV: Set if result parity is even
Source-Register Indirect
N: Reset
Destination-Implied
76543210
11,1, NX, 1,1,1,0,11
+ d) (for Nx = 0)
+ d) (for Nx= 1)
Source-Indexed
Addressing Mode:
C: Set according to borrow
condition
1 0
Timing:
AND (IY
T states-19 (4, 4, 3, 5, 3)
N: Set
I
AND (IX
M cycles-5
Timing:
PIV: Set if result exceeds 8-bit 2's
complement range
11 , 0 , 0 , 1 , 1 , 1 , 1 , 0
I
d
Z: Set if result is zero
7 6 5 4 3 2
AND (HL)
T states-7 (4, 3)
T states-19 (4, 4, 3, 5, 3)
Addressing Mode:
I
M cycles-2
Timing:
M cycles-5
Timing:
o
o
SBC A, (IX
+ d) (for Nx = 0)
SBCA, (IV
+ d) (forNx=1)
7
6
5
4
3
2
1
C: Reset
0
11 , 0 , 1 , 1 , 0 , 1 , 1 , 0
11,0,0,1,1,1,1,01
I
OR (HL)
M cycles-2
Timing:
T states-7 (4, 3)
d
Timing:
Addressing Mode:
Addressing Mode:
M cycles-5
T states-19 (4, 4, 3, 5, 3)
Source-Register Indexed
Destination-Implied
7
6
5
43210
Source-Indexed
Destination-Implied
,1 ,0 ,1 , 1 ,0
OR (IX
+ d) (for Nx=O)
OR (IY
+ d) (for Nx= 1)
I
d
Timing:
M cycles-5
T states-19 (4, 4, 3, 5, 3)
Addressing Mode:
Source-Indexed
Destination-Implied
9-43
•
12.6 8-Bit Arithmetic
(Continued)
XOR
m1
The data in memory location m1 is exclusively OR'ed with
the data in the Accumulator.
A -
A ED m1
5: Set if result is negative
Z: Set if result is zero
N: Reset
2
1
Addressing Mode:
5
Source-Indexed
Destination-Implied
H: Set according to carry from bit
3
PIV: Set if data was X'7F before operation
XOR (HL)
M cycles-2
T states-7 (4, 3)
Source-Register Indexed
N: Reset
C:N/A
7 6 5 4 3 2 1 0
I0 , 0 , 1 , 1 , 0 , 1 , 0 , 0 1
Destination-Implied
7 6
Addressing Mode:
C: Reset
0
11 , 0 , 1 , 0 , 1 , 1 , 1 , 0 1
Timing:
M cycles-5
T states-19 (4, 4, 3, 5, 3)
INC
m1
Increment data in memory location m1.
5: Set if result is negative
Z: Set if result is zero
H: Reset
PIV: Set if result parity is even
76543
Timing:
43210
11 , 1 , Nx , 1 , 1 , 1 , 0 , 1 1
XOR (IX
+ d) (for Nx = 0)
XOR (IV
+ d)(for Nx= 1)
INC (HL)
Timing:
M cycles-3
T states-11 (4, 4, 3)
Addressing Mode:
Source-Register Indexed
Destination-Register Indexed
7 6
d
Timing:
5
43210
M cycles-5
INC (IX
INC (IV
+ d)(for Nx = 0)
+ d) (for Nx= 1)
T states-19 (4, 4, 3, 5, 3)
Addressing Mode:
10,0,
Source-Indexed
Destination-Implied
d
CP
m1
Compare the data in memory location m1 with the data in
the Accumulator via subtraction.
A - m1
5: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
PIV: Set if result exceeds S-bit 2's
complement range
N: Set
C: Set according to borrow
condition
7 6 5 4 3 2 1 0
11 , 0 , 1 , 1 , 1 , 1 , 1 , 0 1
M cycles-2
T states-7 (4, 3)
Addressing Mode:
Source-Register Indirect
Destination-Implied
7 6
5
43210
CP (IX
CP (IV
M cycles-6
T states-23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Source-Indexed
Destination-Indexed
DEC
m1
Decrement data in memory location m1.
5: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 4
PIV: Set only if m1 was X'SO before
operation
CP (HL)
Timing:
11 , 1 , Nx , 1 , 1 , 1 , 0 , 1 1
Timing:
N:Set
C:N/A
+ d)(for Nx = 0)
+ d) (for Nx= 1)
,1,1,1,1,01
d
9-44
r---------------------------------------------------------------------------------,
12.6 8-Bit Arithmetic
7
6
5
4
3
2
1
PIV: Set if result exceeds 16·bit 2's
complement range
(Continued)
0
Ia , a , 1 , 1 , a , 1 , a , 1 I
N: Reset
C: Set if carry out of bit 15
DEC (HL)
765
Timing:
M cycles- 3
Addressing Mode:
T states - 11 (4, 4, 3)
Source - Register Indexed
Destination dexed
7 6
43210
5
11 , 1 , Nx , 1 , 1 , 1 ,
Register
4
3
2
1
o00
o
o
0
11,1,1,0,1,1,0,11
Ia , 1 I pp
In·
11, 0,
,0
DEC (lY + d) (for Nx = 1)
I
Timing:
M cycles- 4
T states - 15 (4, 4, 4, 3)
Addressing Mode:
Source - Register
Destination - Register
DEC (IX + d) (for Nx = 0)
a,1 I
~
U)
10 , 0 ,
SBC
HL,pp
Subtract, with carry, the contents of the 16·bit pp register
from the 16·bit H L register.
HL +- HL - pp - CY
S: Set if result is negative
d
Timing:
M cycles- 6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Source - Indexed
Destination - Indexed
Z: Set if result is zero
H: Set according to borrow from
bit 12
PIV: Set if result exceeds 16·bit 2's
complement range
N:Set
12.7 16-Bit Arithmetic
ADD
sS,pp
Add the contents of the 16·bit register pp to the contents of
the 16·bit register ss.
ss+-ss+pp
C: Set according to borrow condi·
tion
S:N/A
Z:N/A
H: Set if carry from bit 11
PIV:N/A
N: Reset
C: Set if carry from bit 15
7
6
5
432
I0 , a I pp
11, 0 ,
1
pp
10 ,
a , , aI
M cycles-4
Timing:
0
T states -
a , 1 I ADD HL, pp
Addressing Mode:
T states Addressing Mode:
11 (4, 4, 3)
76543210
ADD IX, pp (for NX = 0)
11 , 1 , Nx , 1 , 1 , 1 , 0 , 1
ADD IY, pp (for Nx = 1)
pp
INC
rr
Increment the contents of the 16·bit register rr.
Source - Register
Destination - Register
,-------------------,
I
15 (4, 4, 4, 3)
Source - Register
Destination - Register
M cycles- 3
Timing:
10,01
o
765432
rr +- rr + 1
7 6 5 4
10 , 0 I
rp
,
3
2
1
No flags affected
0 INC BC
I. 0, a , 1 , 1 I.INCHL
INC DE
INCSP
11,0,0,11
Timing:
M cycles-4
T states -15 (4, 4, 4, 3)
Timing:
Addressing Mode:
Source - Register
Destination - Register
Addressing Mode:
M cycles-1
T states- 6
Register
76543210
HL,pp
ADC
The contents of the 16·bit register pp are added, with the
carry bit, to the HL register.
HL +- HL + pp + CY
S: Set if result is negative
Z: Set if result is zero
11 , 1 , NX , 1 , 1 , 1 ,
10 ,
a, 1 I
INC IX (for Nx = 0)
INC IY (for Nx= 1)
a,
Timing:
M cycles- 2
T states -
Addressing Mode:
H: Set according to carry out of bit
11
9·45
Register
10 (4, 6)
•
s
z
12.7 16-Bit Arithmetic (Continued)
DEC
7
6
5
432
1
0
11 , 1 , 0 , 0 , 1 , 0 , 1 , 1 1
rr
Decrement the contents of the HI-bit register rr.
rr -
7
rr - 1
6
5
001
1
. , .
;p_
4
3
2
10, 1
No flags affected
DEC BC
0
1
,b,
1
r ,
Timing:
1 1 0 1 11DECDE
. , , , . DEC HL
M cycles-2
T states - 8 (4, 4)
Bit/Register
Addressing Mode:
DECSP
MEMORY
Timing:
M cycles-1
Addressing Mode:
Tstates Register
76543210
SET
b,m1
Bit b in memory location m1 is set.
6
m1b -
7
DEC IX (for Nx=O)
6
11 , 1 ,
DEC IV (for Nx= 1)
1
5
No flags affected
432
°,°, °,
1 ,
1
0
1 , 1 1
SET b, (HL)
10 ,0 ,
Timing:
M cycles-2
T states -10 (4, 6)
Timing:
M cycles-4
T states -15 (4, 4, 4, 3)
Addressing Mode:
Register
Addressing Mode:
Bit/Register Indirect
76543210
SET b, (lX+d) (for Nx=O)
12.8 Bit Set, Reset, and Test
SET b, (lV+d) (for Nx= 1)
REGISTER
1,1,
b,r
SET
Bit b in register r is set.
Rb -
1
°
,0,1,0,1,1
d
No flags affected
76543210
11,1,0,0,1,0,1,11
, r
M cycles-6
Addressing Mode:
T states - 23 (4, 4, 3, 5, 4, 3)
Bitllndexed
I
Timing:
M cycles-2
T states - 8 (4, 4)
Addressing Mode:
Bit/Register
RES
b,m1
Bit b in memory location m1 is reset.
m1b 7 6
RES
b,r
Bit b in register r is reset.
°
rb -
Timing:
11 , 1 ,
No flags affected
°
°,
5
4
3
0,
2
1
,0,
,1 1
76543210
°
1
,b,
,r
1
M cycles-4
T states - 15 (4, 4, 4, 3)
Addressing Mode:
Bit/Register Indirect
,
T states -
Addressing Mode:
,°
b,
M cycles-2
Timing:
76543210
8 (4, 4)
1 , 1 , Nx , 1 , 1 , 1 ,
Bit/Register
RES b, (HL)
Timing:
11,1,0,0,1,0,1,11
11 ,
No flags affected
0
RES b, (IX+d) (for Nx=O)
°,
1
RES b, (IV+d) (for Nx= 1)
BIT
b,r
Bit b in register r is tested with the result put in the Z flag.
Z -
ib
S: Undefined
Z: Inverse of tested bit
d
H:Set
P/V: Undefined
1 ,0 ,
, b,
Timing:
N: Reset
, 1 ,1 ,
°
M cycles-6
T states -
C:N/A
Addressing Mode:
9-46
Bitllndexed
23 (4, 4, 3, 5, 4, 3)
z
7
12.8 Bit Set, Reset, and Test (Continued)
BIT
1
B,m1
Bit b in memory location m1 is tested via the Z flag.
Z -
m1b
6
5
4
3
2
°,°,°,°,°,
1
I
1 , 1 , 1
Timing:
S: Undefined
Z: Inverse of tested bit
H:Set
U)
oCD
0
o
RLCA
o
M cycles - 1
T states- 4
Addressing Mode:
Implied
(Note RLCA does not affect S, Z, or PIV flags.)
PIV: Undefined
r
RL
N: Reset
Rotate register r left through carry.
C:N/A
7
6
5
4
3
2
1
~~7-.------0""~
0
11 , 1 , 0 , 0 , 1 , 0 , 1 , 1
I
BIT b, (HL)
r
TLlC/5171-56
Timing:
M cycles- 3
T states -12 (4, 4, 4)
Addressing Mode:
Bit/Register Indirect
76543210
BIT b, (IX + d) (for Nx = 0)
1 , 1 , Nx , 1 , 1 , 1 ,
1
BIT b, (IY+d) (for Nx= 1)
S: Set if result is negative
Z: Set if result is zero
H: Reset
PIV: Set if result parity is even
°,
1,1,
°
7
,0,1,0,1,1
d
°,
10 ,
1
6
5
4
3
2
°,°, °,
°,°,1 , °
11 , 1 ,
1 ,
1
N: Reset
C: Set according to bit 7 of r
1 0
1 , 1
I RL r
r,
I (Note alternate for
L--'--'--'---'-_'--'--'-....J A register below)
1
Timing:
M cycles-5
T states - 20 (4, 4, 3, 5, 4)
Timing:
Addressing Mode:
Bit/Indexed
Addressing Mode:
7
12.9 Rotate and Shift
1
REGISTER
6
M cycles-2
T states - 8 (4, 4)
5
4
3
°,°,°, °,
1 ,
Register
2
1
1 , 1 , 1
Rotate register r left circular.
I
RLA
M cycles-1
Tstates- 4
Timing:
RLC
0
Addressing Mode:
Implied
(Note RLA does not affect S, Z, or PIV flags.)
RRC
r
Rotate register r right circular.
r
TL/C/5171-57
S: Set if result is negative
Z: Set if result is zero
r
H: Reset
TL/C/5171-59
P IV: Set if result parity is even
7
6
4
3
2
S: Set if result is negative
C: Set according to bit 7 of r
Z: Set if result is zero
H: Reset
1
0
°,°, °, I
°,°,°,°,
I
11 , 1 ,
10 ,
5
N: Reset
1 ,
1 , 1
P IV: Set if result parity is even
RLC r
N: Reset
C: Set according to bit
(Note alternate for
L--'--'---'---J'--'--'--'---J A register below)
Timing:
M cycles- 2
T states - 8 (4, 4)
Addressing Mode:
Register
9-47
°
of r
C)
C)
co
o(/)
z
r---------------------------------------------------------------------------------,
12.9 Rotate and Shift (Continued)
765432
11 , 1 , 0 , 0,
0
,0,
PIV: Set if result parity is even
1
N: Reset
RRC r
C: Set according to bit 7 of r
7
(Note alternate for
A register below)
10 , 0 , 0 , 0 , 1
Timing:
M cycles T states -
Addressing Mode:
6
5
4
3
2
1
0
11,1,0,0,1,0,1,1
2
10 , 0,
8 (4, 4)
Register
r ,
,0 , 0 I
M cycles -
Timing:
76543210
T states -
LI_0~,_0_L,_0~,_0~,_1_L_J__~,_1~1
Addressing Mode:
RRCA
M cycles -
Timing:
Register
SRA
1
Shift register r right arithmetic.
T states- 4
Addressing Mode:
2
8 (4, 4)
Implied
(Note RRCA does not affect S, Z, or PIV flags.)
RR
TLiC/5171-62
Rotate register r right through carry.
S: Set if result is negative
t=:i~7------------~--O~
Z: Set if result is zero
H: Reset
PIV: Set if result parity is even
r
N: Reset
TL/C/5171-60
S: Set if result is negative
7
Z: Set if result is zero
6
5
4
3
2
11 , 1 , 0 , 0 , 1 , 0 , 1 ,
H: Reset
PIV: Set if result parity is even
r ,
N: Reset
7
6
5
4
o
0
3
C: Set according to bit 0 of r
2
1
0
Timing:
o
Addressing Mode:
0
C: Set according to bit 0 of r
1 0
M cycles T states -
RRr
2
8 (4, 4)
Register
SRL
o
0
0
Timing:
Shift register r right logical.
(Note alternate for
A register below)
M cycles- 2
T states -
Addressing Mode:
765432
r
TL/C/5171-63
0
S: Reset
LI0~,_0_L,_0~,_1~__L_~_L,_1~1
Z: Set if result is zero
RRA
M cycles -
Timing:
8 (4, 4)
Register
H: Reset
1
PIV: Set if result parity is even
T states-4
N: Reset
Addressing Mode:
Implied
(Note RRA does not affect S, Z, or PIV flags.)
SLA
7
r
6
5
4
3
2
C: Set according to bit 0 of r
1 0
11 , 1 , 0 , 0 , 1 , 0 , 1 , 1 1
Shift register r left arithmetric.
10 , 0 , 1 , 1 , 1
~77.4======~O~r--O
Timing:
r
r,
1
M cycles- 2
T states -
TLiC/5171-61
Addressing Mode:
S: Set if result is negative
Z: Set if result is zero
H: Reset
9-48
Register
8 (4, 4)
z
en
oco
12.9 Rotate and Shift (Continued)
7
MEMORY
RLC
6
11 , 1 ,
ml
Rotate date in memory location ml left circular.
5
4
0
321
C)
C)
°,°, °,
,°, °
1 ,
10,0,0,
1 , 1 1 RL (HL)
1 ,1 ,
1
Timing:
M cycles - 4
T states -15 (4, 4, 4, 3)
Addressing Mode:
Register Indirect
76543210
TLlC/5171-64
1 , 1 , Nx , 1 , 1 , 1 ,
S: Set if result is negative
Z: Set if result is zero
1,1,
H: Reset
PIV: Set if result parity is even
°
°,
RL (IX + d) (for Nx = 0)
1
RL (IY+d) (for NX= 1)
,0,1,0,1,1
d
N: Reset
7
6
5
11 , 1 ,
432
°,°, °,
1 ,
10,0,0,0,0,
C: Set according to bit 7 of ml
1 0
1 , 1
, 1 ,
°
I
Register indirect
76543210
°
M cycles - 6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
1
Addressing Mode:
1,1,
,1,0,1,1,0
Timing:
M cycles- 4
T states - 15 (4, 4, 4, 3)
°,
°
RLC (HL)
Timing:
1 , 1 , Nx , 1 , 1 , 1 ,
0,0,
11
RRC
Indexed
ml
Rotate the data in memory location ml right circular.
RLC (IX+d) (for Nx=O)
RLC (IY+d) (for Nx= 1)
,0,1,0,1,11
TL/C/5171-66
d
S: Set if result is negative
Z: Set if result is zero
Timing:
M cycles-6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Indexed
RL
H: Reset
PIV: Set if result parity is even
N: Reset
C: Set according to bit
7 6 5 4 3 2 1 0
ml
11 , 1 ,
Rotate the data in memory location ml left though carry.
°,°, °,
1,
1, 11
°
of ml
RRC (HL)
10 ,0,0,0,1,1,1,01
Timing:
M cycles - 4
T states - 15 (4, 4, 4, 3)
Addressing Mode:
Register Indirect
76543210
TL/C/5171-65
S: Set if result is negative
Z: Set if result is zero
1 , 1 , Nx , 1 , 1 , 1 ,
H: Reset
1,1,
°
PIV: Set if result parity is even
°,
1
RRC (IX + d) (for Nx = 0)
RRC (IY + d) (for Nx = 1)
,0, 1 , 0,1 , 1
d
N: Reset
C: Set according to bit 7 of ml
0,0,
9-49
°
,0,1,1,1,0
Timing:
M cycles - 6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Indexed
C)
C)
~z
r---------------------------------------------------------------------------------,
12.9 Rotate and Shift (Continued)
76543210
RR
ml
Rotate the data in memory location ml right through the
carry.
11 , 1 , Nx , 1 , 1 , 1 ,
°, I
1
+ d) (for Nx =
+ d) (for Nx =
SLA (IX
SLA (IV
0)
1)
11,1,0,0,1,0,1,11
I
d
10,0,
,0,0,1,1,01
Timing:
S: Set if result is negative
Z: Set if result is zero
M cycles- 6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Indexed
H: Reset
SRA
TL/C/5171-67
ml
Shift the data in memory location ml right arithmetic.
P IV: Set if result parity is even
N: Reset
C: Set according to bit
76543210
11,1,0,0,1,0,1,11
°
of ml
RR(HL)
TL/C/5171-69
S: Set if result is negative
Z: Set if result is zero
10,0,0,1,1,1,1,01
Timing:
M cycles-4
Addressing Mode:
T states - 15 (4, 4, 4, 3)
Register Indirect
76543210
1 , 1 , Nx , 1 , 1 , 1 ,
1,1,
°
H: Reset
+ d) (for Nx =
RR (IV + d) (for Nx =
RR (IX
°,
1
PIV: Set if result parity is even
N: Reset
0)
7
°
5
4
C: Set according to bit
3 2 1 0
1)
11,1,0,0,1,0,1,11
,0,1,0,1,1
°
of ml
SRA(HL)
10,0,1,0,1,1,1,01
d
0,0,
6
M cycles-4
Timing:
,1,1,1,1,0
T states -
Timing:
M cycles-6
T states - 23 (4, 4, 3, 5, 4, 3)
Addressing Mode:
Indexed
Addressing Mode:
76543210
SRA (IX
1 , 1 , Nx , 1 , 1 , 1 , 0 , 1
SLA
ml
Shift the data in memory location ml left arithmetic.
15 (4, 4, 4, 3)
Register Indirect
SRA (IV
+ d) (for Nx =
+ d)(for Nx =
0)
1)
1,1,0,0,1,0,1,1
d
0,0,
,0,1,1,1,0
Timing:
M cycles-6
TL/C/5171-68
T states -
S: Set if result is negative
Z: Set if result is zero
H: Reset
Addressing Mode:
23 (4, 4, 3, 5, 4, 3)
Indexed
SRL
ml
Shift right logical the data in memory location mI.
PIV: Set if result parity is even
N: Reset
C: Set according to bit 7 of ml
7 6
5 432
1 0
ml
11,1,0,0,1,0,1,11
SLA(HL)
TL/C/5171-70
10,0,1,0,0,1,1,01
S: Reset
Timing:
M cycles-4
T states -15 (4, 4, 4, 3)
Z: Set if result is zero
H: Reset
Addressing Mode:
Register Indirect
PIV: Set if result parity is even
N: Reset
C: Set according to bit 0 of ml
9·50
r--------------------------------------------------------------------------,z
~
CD
12.9 Rotate and Shift (Continued)
7 6
5
4
3
2
1 0
RRD
SRL(HL)
11,1,0,0,1,0,1,11
1o,
°,
1,1,1,1,1,
°
Addressing Mode:
76543210
1 , 1 , Nx , 1 , 1 , 1 ,
1,1,
°
+ i:.§]o
1
Timing:
17-4 I
M cycles-4
T states - 15 (4, 4, 4, 3)
Register Indirect
+ d) (for Nx =
SRL (IY + d) (for Nx =
SRL (IX
°,
1
1ACC 1
1)
d
0,0,
,1,1,1,1,
°
M cycles-6
T states - 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
PIV: Set if result parity is even
N: Reset
C:N/A
2
0
11,1,1,0,1,1,0,1
REGISTER/MEMORY
10,1,1,0,0,1,1,1
RLD
Timing:
+ Tii3
Rotate digit left and right between the Accumulator and
memory (HL).
1 -41
7
1ACC 1
0
Addressing Mode:
12.10 Exchanges
1(HL)
EX
DE,HL
Exchange the contents of the 16-bit register pairs DE and
HL.
No flags affected
DE HL
765432
o
S: Set if result is negative
Z: Set if result is zero
H: Reset
PIV: Set if result parity is even
N: Reset
C:N/A
765432
0
1o , 1
,
°,
Timing:
Addressing Mode:
,1
1
,1 , 1
1
M cycles- 5
T states - 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
REGISTER/REGISTER
TL/C/5171-71
,°
1(HL)
TL/C/5171-72
0)
,0,1,0,1,1
Timing:
o
o
Rotate digit right and left between the Accumulator and
memory (HL).
Timing:
Addressing Mode:
M cycles-1
T states-4
Register
EX
AF,A'F'
The contents of the Accumulator and flag register are exchanged with their corresponding alternate registers, that is
A and F are exchanged with A' and F'.
M cycles- 5
T states - 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
A -
A'
No flags affected
F F'
76543210
10,0,0,0,1,0,0,01
Timing:
Addressing Mode:
M cycles-1
T states - 4
Register
•
9-51
C) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C)
~z
LOO
Move data from memory location (HL) to memory location
(DE), and decrement memory pointer and byte counter BC.
12.10 Exchanges (Continued)
EXX
Exchange the contents of the BC, DE, and HL registers with
their corresponding alternate register.
BC -
B'C'
DE -
D'E'
HL -
H'L'
765
4
(DE) -
No flags affected
HL -
(HL)
S: NtA
Z: N/A
HL - 1
P/V: Set if BC -1 *0, otherwise reset
3
2
1
0
N: Reset
C:N/A
11,1,0,1,1,0,0,11
Timing:
7 6 5 4 3 2
M cycles-1
Addressing Mode:
1 0
11,1,1,0,1,1,0,11
T states- 4
Implied
11,0,1,0,1,0,0,01
REGISTER/MEMORY
EX
H: Reset
M cycles-4
Timing:
(SP),55
T states -16 (4, 4, 3, 5)
Exchange the two bytes at the top of the external memory
stack with the 16-bit register ss.
Addressing Mode:
(SP) -
CPI
Compare data in memory location (HL) to the Accumulator,
increment the memory pointer, and decrement the byte
counter. The Z flag is set if the comparison is equal.
(SP
SSL
+ 1)
7 6
-
5
No flags affected
SSH
4 320
11 , 1 , 1 , 0 , 0 , 0 , 1 , 1 1
EX (SP), HL
M cycles -
Timing:
T states Addressing Mode:
A - (HL)
HL _ HL
5
BC -
19 (4, 3, 4, 3, 5)
76543210
1
S: Set if result of comparison subtract is negative
BC - 1
Z: Set if result of comparison is
+
Z-1
Register/Register Indirect
if A = (HL)
EX (SP), IX (for NX = 0)
11 , 1 , NX , 1 , 1 , 1 , 0 , 1 1
T states -
76543210
23 (4, 4, 3, 4, 3, 5)
Register/Register Indirect
11,1,1,0,1,1,0,11
12.11 Memory Block Moves and
Searches
11,0,1,0,0,0,0,11
Timing:
Addressing Mode:
LOI
(HL)
DE
+
1
HL HL + 1
BC-BC-1
S: N/ A
Z: N/A
A - (HL)
S: Set if result is negative
H: Reset
HL - 1
HL BC-BC-1
Z: Set if result of comparison is
Z-1
H: Set according to borrow from
P/V: Set if BC -1 *0, otherwise reset
if A = (HL)
N: Reset
C:N/A
11,0,1,0,0,0,0,01
Addressing Mode:
bit 4
N:Set
11,1,1,0,1,1,0,11
M cycles-4
T states -
zero
P/V: Set if BC reset
C: N/A
76543210
Timing:
16 (4, 4, 3, 5)
Register Indirect
CPO
Compare data in memory location (HL) to the Accumulator,
and decrement the memory pointer and byte counter. The Z
flag is set if the comparison is equal.
Move data from memory location (HL) to memory location
(DE), increment memory pointers, and decrement byte
counter BC.
(DE) -
M cycles-4
T states -
SINGLE OPERATIONS
DE -
1* 0, otherwise
N: Set
C:N/A
M cycles- 6
Addressing Mode:
zero
H: Set according to borrow from
bit 4
P/V: Set if BC reset
EX (SP),IY (for Nx = 1)
,0 , 0 ,0,1 , 1 1
Timing:
Register Indirect
16 (4, 4, 3, 5)
Register Indirect
9-52
1*
0, otherwise
z
en
o
12.11 Memory Block Moves and Searches (Continued)
765432
0
11,1,1,0,1,1,0,
11
,0, 1 ,0, 1 ,0,0,
Timing:
M cycles - 4
T states - 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
REPEAT OPERATIONS
LOIR
Move data from memory location (HL) to memory location
(DE), increment memory painters, decrement byte counter
BC, and repeat until BC = o.
(DE) -
DE -
5: NI A
(HL)
DE
Z:N/A
+
1
HL HL + 1
BC BC - 1
Repeat until
BC = 0
765 4 3
H: Reset
P/V: Reset
N: Reset
C:N/A
2
11,1,1,0,1,1,0,1
11,0,1,1,0,0,0,1
Timing:
ForBC"",, 0
0
11,1,
,0,1,1,0,11
11,0,
,1,0,0,0,01
Timing:
For BC"",,O M cycles -
ForBC = 0
CPOR
Compare data in memory location (HL) to the contents of
the Accumulator, decrement the memory pointer and byte
counter BC, and repeat until BC = 0, or until (HL) equals
the Accumulator.
A - (HL)
5: Set if sign of subtraction performed for comparison is negaHL HL - 1
tive
BC BC - 1
Z: Set according to equality of A
Repeat until BC = 0
and (HL), set if true
or A = (HL)
H: Set according to borrow from
bit 4
Register Indirect
LOOR
Move data from memory location (HL) to memory location
(DE), decrement memory pointers and byte counter BC, and
repeat until BC = o.
(DE) (HL)
5: NI A
Z:N/A
DE-DE-1
H: Reset
HL HL - 1
P/V: Reset
BC-BC-1
Repeat until
N: Reset
BC = 0
C:N/A
7 6 5 4 3 2
0
,0,1,1,0,11
11,0,
,1,1,0,0,01
Timing:
For BC"",,O M cycles T states For BC=O M cycles -
21 (4, 4, 3, 5, 5)
M cycles-4
T states - 16 (4, 4, 3, 5)
Register Indirect
Addressing Mode:
(Note that each repeat is accomplished by a decrement of
the PC, so that refresh, etc. continues for each cycle.)
5
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
11,1,
M cycles- 5
T states -
T states - 21 (4, 4, 3, 5, 5)
For BC=O M cycles - 4
T states - 16 (4, 4, 3, 5)
Addressing Mode:
01)
CPIR
Compare data in memory location (HL) to the Accumulator,
increment the memory, decrement the byte counter BC, and
repeat until BC = 0 or (HL) equals A.
A - (HL)
5: Set if sign of subtraction perHL _ HL + 1
formed for comparison is negative
BC-BC+1
Z: Set if A = (HL), otherwise reset
Repeat until BC = 0
H: Set according to borrow from
or A = (HL)
bit 4
P/V: Set if BC - 1 """ 0, otherwise
reset
N:Set
C:N/A
765432
0
P/V: Set if BC reset
N: Set
C:N/A
765432
1 """ 0, otherwise
0
11,1,1,0,1,1,0,1
11,0,1,1,1,0,0,1
Timing:
5
ForBC"",, 0
M cycles- 5
T states - 21 (4, 4, 3, 5, 5)
ForBC = 0
M cycles- 4
21 (4, 4, 3, 5, 5)
4
T states - 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
T states - 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
9-53
o
o
or---------------------------------------------------------~
o
~Z
12.12 Input/Output
IN
PIV: Undefined
A,(n)
N:Set
Input data to the Accumulator from the I/O device at address N.
G:N/A
7
No flags affected
A - (n)
765 43210
6
5
4
3
2
1 0
11,1,1,0,1,1,0,11
11 , 1 ,0, 1 , 1 ,0, 1
11,0,1,0,0,0,1,01
n
Timing:
Timing:
T states Addressing Mode:
Source -
Destination -
Register
r,(C)
(G)
S: Set if result is negative
Z: Set if result is zero
(C) -
H: Reset
PIV: Set if result parity is even
(HL)
8 -
8-1
HL -
HL
+
H: Undefined
1
PIV: Undefined
N: Set
G:N/A
5
4
3
2
G:N/A
1 0
7
11,1,1,0,1,1,0,11
10,11
M cycles -
Addressing Mode:
Source -
T states -
5
432
1 0
11,0,1,0,0,0,1,11
3
Timing:
12 (4, 4, 4)
M cycles T states -
Register Indirect
Destination -
Addressing Mode:
Register
(C) -
6
Destination -
4
3
o
2
(HL) HL -
10,0,
8 -
Timing:
M cycles-3
Addressing Mode:
Source -
T states -
HL -
S: Undefined
Z: Set if 8 -1 = 0, otherwise reset
H: Undefined
8 - 1
N:Set
12 (4, 4, 4)
G:N/A
7
Register Indirect
6
5
4
321
0
11,1,1,0,1,1,0,11
INI
8 -
Register Indirect
PIV: Undefined
Input data from the I/O device addressed by the contents of
register G to the memory location pointed to by the contents
of the HL register. The HL pOinter is incremented and the
byte counter 8 is decremented.
(HL) -
(G)
HL - 1
Register
Destination -
Register In-
INO
Input data from I/O device at port address (G) to memory
location (HL), and decrement HL memory pointer and byte
counter 8.
No flags affected
r
5
4
16 (4, 5, 3, 4)
Implied/Source direct
(C), r
OUT
Output register r to the I/O device addressed by the contents of register G.
7
6
11,1,1,0,1,1,0,11
10,0,01
Timing:
Register Indirect
S: Undefined
Z: Set if 8-1 =0, otherwise reset
N: Reset
7 6
Register In-
OUTI
Output data from memory location (HL) to the I/O device at
port address (G), increment the memory pointer, and decrement the byte counter 8.
Input data to register r from the I/O device addressed by the
contents of register G. If r = 110 only flags are affected.
r -
4
Implied/Source direct
Addressing Mode:
11 (4, 3, 4)
Direct
Destination -
IN
M cycles -
T states -16 (4, 5, 3, 4)
M cycles- 3
(G)
8-1
HL
+1
11,0,1,0,1,0,1,01
Timing:
S: Undefined
Z: Set if 8 -1 = 0, otherwise reset
Addressing Mode:
H: Undefined
M cycles -
4
T states -
16 (4, 5, 3, 4)
Implied/Source direct
Destination -
9-54
Register In-
Register Indirect
z
o
UJ
12.12 Input/Output (Continued)
OUT
7
(n),A
Output the Accumulator to the I/O device at address n.
(n)
~
A
7 6
11
11
1
1
5
1
4
3
o
1
1 , 0 , 0 , 1 ,01
1
0
QI)
o
0
0
1
1
1
1
1
1
2
1
11
No flags affected
5 4 3 2
1 0
11 , 0 , 1
1 , 0 , 1 ,0,0, 1
1
6
Timing:
For B oF 0
M cycles- 5
T states -
n
ForB = 0
M cycles- 3
Timing:
T states Addressing Mode:
Source -
Addressing Mode:
11 (4, 3, 4)
Data is output to the I/O device at port address (C) from
memory location (HL), the HL memory pointer is incremented, and the byte counter B is decremented. The cycles are
repeated until B = O.
0, otherwise reset
H: Undefined
P/V: Undefined
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
N: Set
C:N/A
7 6
11
11
1
1
0
1
5 4 3 2
1
1
1 ,0 , 1
1 ,0 , 1
1
1
Timing:
1
1
16 (4, 5, 3, 4)
Implied/Source direct
Destination -
7
Register In-
HL
+
1
B-1
Repeat until B = 0
5
1
1
11
1
0 , 1
1
4
3
1 ,0 , 1
11
Timing:
2
1
C:N/A
0
1
1 , 0 , 11
1
1
1
0
1
0
For B oF 0
1
1
1
1
I
M cycles T states -
For B
=
0
Addressing Mode:
5
21 (4, 5, 3, 4, 5)
4
M cycles T states -
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL) ~ (C)
S: Undefined
~
6
Register Indirect
Data is input from the I/O device at port address (C) to
memory location (HL), the HL memory pointer is incremented, and the byte counter B is decremented. The cycle is
repeated until B = O.
~
Z: Set
P/V: Undefined
0
4
INIR
HL
=
N: Set
T states -
B
S: Undefined
H: Undefined
Repeat until B
M cycles -
Addressing Mode:
~ (HL)
HL ~ HL + 1
B ~ B-1
(C)
1 0
1 ,0, 1
0
Register Indirect
OTIR
S: Undefined
=
Register In-
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be performed.)
Data is output from memory location (HL) to the I/O device
at port address (C), and the HL memory pointer and byte
counter B are decremented.
Z: Set if B-1
16 (4, 5, 3, 4)
Destination -
Direct
aUTO
(C) ~ (HL)
B ~ B-1
HL ~ HL - 1
4
T states -
Implied/Source direct
Register
Destination -
21 (4, 5, 3, 4, 5)
M cycles -
16 (4, 5, 3, 4)
Implied/Source direct
Destination -
Register In-
Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be performed.)
Z: Set
H: Undefined
P/V: Undefined
N: Set
C: N/A
9-55
o
o
ClCI
12.12 Input/Output (Continued)
12.13 CPU Control
z
INOR
NOP
Data is input from the I/O device at address (C) to memory
location (HL), then the HL memory pointer is byte counter B
are decremented. The cycle is repeated until B = O.
The CPU performs no operation.
oen
7 6 5 4 3 2
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL) +- (C)
S: Undefined
HL +- HL - 1
Z: Set
B +- B-1
Timing:
6
5
4
3
2
1
Addressing Mode:
HALT
C: N/A
0
7
*0
M cycles T states -
ForB = 0
T states -
5
4
3
2
1
Timing:
5
No flags affected
0
M cycles-1
T states -
21 (4, 5, 3, 4, 5)
Addressing Mode:
M cycles-4
Addressing Mode:
6
10, 1 , 1 , 1 ,0, 1 , 1 ,01
11 ,0, 1 , 1 ,0,0, 1 ,01
For B
16 (4, 5, 3, 4)
Implied/Source direct
4
N/A
01
Register In-
Disable system level interrupts.
IFF1 +- 0
Register Indirect
Destination -
No flags affected
IFF2 +- 0
(Note that after each data transfer cycle, interrupts may be
recognized and two refresh cycles are performed.)
7 6 5 4 3 2
1
0
11 , 1 , 1 , 1 , 0 , 0 , 1 , 1 1
OTOR
Timing:
Data is output from memory location (HL) to the I/O device
at port address (C), then the HL memory pointer and byte
counter B are decremented. The cycle is repeated until B =
O.
(C) +- (HL)
S: Undefined
HL +- HL - 1
Z: Set
B +- B-1
7 6 5 4 3 2
EI
The system level interrupts are enabled. During execution of
this instruction, and the next one, the maskable interrupts
will be disabled.
IFF1 +- 1
No flags affected
IFF2 +- 1
7 6 543
PIV: Undefined
1
2
1
0
N: Set
11 , 1 , 1 , 1 , 1 , 0 , 1 , 1 1
C:N/A
Timing:
M cycles-1
0
T states -
11 , 1 , 1 , 0 , 1 , 1 , 0 , 1
Addressing Mode:
11 ,0, 1 , 1 , 1 ,0, 1 , 1
1M
0
The CPU is placed in interrupt mode O.
ForB
*0
M cycles T states -
For B = 0
M cycles T states -
Addressing Mode:
1
4
N/A
Addressing Mode:
H: Undefined
Repeat until B = 0
M cycles T states -
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
Timing:
4
N/A
The CPU halts execution of the program. Dummy op-code
fetches are performed from the next memory location to
keep the refresh circuits active until the CPU is interrupted
or reset from the halted state.
11 , 1 , 1 , 0 , 1 , 1 , 0 , 1 1
Timing:
M cycles-1
T states -
N: Set
7
No flags affected
0
10,0,0,0,0,0,0,01
H: Undefined
PIV: Undefined
Repeat until B = 0
1
5
7 6 543
21 (4, 5, 3, 4, 5)
4
4
N/A
2
1
No flags affected
0
11 , 1 , 1 , 0 , 1 , 1 , 0 , 1 1
16 (4, 5, 3, 4)
Implied/Source direct
Destination -
Register InTiming:
Register Indirect
M cycles T states -
(Note that after each data transfer cycle the NSC800 will
accept interrupts and perform two refresh cycles.)
Addressing Mode:
9-56
N/A
2
8 (4, 4)
z
12.13 CPU Control
76543210
(Continued)
1M
11 , 1 , Nx , 1 , 1 , 1 ,
The CPU is placed in interrupt mode 1.
No flags affected
7 6 5 4 3 2 1 0
Timing:
°,
11
Addressing Mode:
Timing:
PC nn,
otherwise continue
7 6 5 4 3 2
1M
2
The CPU is placed in interrupt mode 2.
No flags affected
7 6 5 4 3 2 1 0
1 0
1o , 1 ,
11,1,1,0,1,1,0,11
n (low-order byte)
10,1,0,1,1,1,1,01
n (high-order byte)
Timing:
M cycles-2
T states - B (4, 4)
N/A
Addressing Mode:
Timing:
1
M cycles-3
T states - 10 (4, 3, 3)
Direct
Addressing Mode:
12.14 Program Control
°
JR
d
Unconditional jump to program location calculated with respect to the program counter and the displacement d.
JUMPS
nn
Unconditional jump to program location nn.
PC PC + d
7 654 3
PC 7 6
10,0,0,1,1,0,0,01
JP
No flags affected
nn
5
4
3
2
1
o
JP
cC,nn
Conditionally jump to program location nn based on testable
flag states.
If cc true,
No flags affected
M cycles- 2
T states - B (4, 4)
N/A
Addressing Mode:
JP (IY) (for Nx = 1)
M cycles- 2
T states - B (4, 4)
Register Indirect
11,1,1,0,1,1,0,11
10,1,0,1,0,1,1,01
JP (IX) (for Nx = 0)
~
CD
°
11,1,0,0,0,0,1,11
2
1
No flags affected
0
d-2
Timing:
n (low-order byte)
M cycles- 3
T states -12 (4, 3, 5)
PC Relative
Addressing Mode:
n (high-order byte)
JP
JR
kk,d
Conditionally jump to program location calculated with respect to the program counter and the displacement d,
based on limited testable flag states.
If kk true,
No flags affected
PC -
PC PC + d,
otherwise continue
7 6 5 4 3 2
M cycles- 3
T states - 10 (4, 3, 3)
Direct
Timing:
Addressing Mode:
(ss)
Unconditional jump to program location pOinted to by register ss.
ss
7 6 5 4 321
11 , 1 , 1 ,
No flags affected
0
°, °,°,
1,
Timing:
Addressing Mode:
11
10,0,11
~k
1
0
10,0,01
JP (HL)
d-2
M cycles-1
Tstates-4
Register Indirect
ifkk met
(true)
if kk not met
(not true)
Addressing Mode:
Timing:
9-57
M cycles- 3
T states - 12 (4, 3, 5)
M cycles - 2
T states - 7 (4, 3)
PC Relative
o
12.14 Program Control
(Continued)
RETURNS
RET
DJNZ
d
Decrement the B register and conditionally jump to program
location calculated with respect to the program counter and
the displacement d, based on the contents of the B register.
B-1
No flags affected
B If B = 0 continue,
else PC PC + d
7 6 5 432 1 0
Unconditional return from subroutine or other return to program location pointed to by the top of the stack.
PCl -
10,0,0,1,0,0,0,01
M cycles-3
T states -13 (5, 3, 5)
M cycles-2
T states - 8 (5, 3)
PC Relative
IfB = 0
Addressing Mode:
7
call to subroutine at location nn.
No flags affected
765 4 321
11,11
2
nn
6
5
M cycles-3
T states - 10 (4, 3, 3)
Register Indirect
PCl (SP)
PCH (SP + 1)
SP - SP + 2,
else continue
CALL
PCH
PCl
,cc,
Timing:
4 321
If cc true
11,1,0,0,1,1,0,11
If cc not true
1
Addressing Mode:
Unconditional return from interrupt handling subroutine.
Functionally identical to RET instruction. Unique opcode allows monitoring by external hardware.
M Cycles-5
T states - 17 (4, 3, 4, 3, 3)
Direct
Timing:
Addressing Mode:
PCl -
7
No flags affected
6
5
4
3
1 0
10,1,0,0,1,1 , 0 , 1 1
Timing:
Addressing Mode:
1 0
n (low-order byte)
n (high-order byte)
If cc true
If cc not true
Addressing Mode:
2
11,1,1,0,1,1,0,11
(SP -1) PCH
(SP - 2) PCl
SP-SP-2
Timing:
(SP)
PCH (SP + 1)
SP SP + 2
cc,nn
Conditional call to subroutine at location nn based on testable flag stages.
No flags affected
If cctrlJe,
CALL
3 2
M cycles-3
T states - 11 (5, 3, 3)
M cycles-l
Tstates- 5
Register Indirect
RETI
n (high-order byte)
PC nn,
else continue
7 6 5 4
0
10,0,01
0
n (low-order byte)
0
Addressing Mode:
RET
cc
Conditional return from subroutine or other return to program location pointed to by the top of the stack.
If cc true,
No flags affected
CALLS
PC -
1
Timing:
IfB #0 0
nn
Unconditional
(SP - 1) (SP - 2) SP SP -
No flags affected
11 , 1 ,0,0, 1 ,0,0, 1 1
d-2
Timing:
(SP)
PCH (SP + 1)
SP SP + 2
7 6 5 4 3 2
M cycles-5
T states 17 (4, 3, 4, 3, 3)
M cycles - 3
T states - 10 (4, 3, 3)
Direct
9-58
M cycles - 4
T states - 14 (4, 4, 3, 3)
Register Indirect
~------------------------------------------------~z
12.14 Program Control
~
(Continued)
CD
RETN
Unconditional return from non-maskable interrupt handling
subroutine. Functionally similar to RET instruction, except
interrupt enable state is restored to that prior to non-maskable interrupt.
PCl +- (SP)
PCH +- (SP
SP +- SP
Q
Q
RESTARTS
RST
No flags affected
+
(SP - 1) +- PCH
1)
+2
SP +- SP - 2
PCH +- 0
0
PCl +- P
11,1,1,0,1,1,0,11
7 6 5 432
11
10,1,0,0,0,1,0,11
Timing:
Addressing Mode:
No flags affected
(SP - 2) +- PCl
IFF1 +- IFF2
7 6 5 4 321
P
The present contents of the PC are pushed onto the memory stack and the PC is loaded with dedicated program locations as determined by the specific restart executed.
M cycles -
4
T states -
14 (4, 4, 3, 3)
Timing:
Register Indirect
0
M cycles- 3
T states -
Addressing Mode:
1
11 , 1 , 11
11 (5, 3, 3)
Modified Page Zero
•
9-59
0
0
CO
0
Z
rn
12.15 Instruction Set: Alphabetical Order
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
BIT
BIT
BIT
BIT
A,(HL)
A,(lX+d)
A,(IY+d)
A,A
A,B
A,C
A,D
A,E
A,H
A, L
A,n
HL,BC
HL, DE
HL,HL
HL,SP
A,(HL)
A,(IX+d)
A,(IY+d)
A,A
A,B
A,C
A,D
A,E
A,H
A, L
A,n
HL, BC
HL,DE
HL, HL
HL,SP
IX,BC
IX,DE
IX,IX
IX,SP
IY,BC
IY,DE
IY,IY
IY,SP
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
n
O,(HL)
O,(IX+d)
0, (IY+d)
O,A
BE
DDBEd
FDBEd
BF
BB
B9
BA
BB
BC
BD
CEn
ED4A
ED5A
ED6A
ED7A
B6
DDB6d
FDB6d
B7
BO
B1
B2
B3
B4
B5
C6n
09
19
29
39
DD09
DD19
DO 29
0039
FD09
FD19
FD29
FD39
A6
DDA6d
FDA6d
A7
AO
A1
A2
A3
A4
A5
E6n
CB46
DDCBd46
FDCBd46
CB47
(nn) ~ address of memory location
d ~ signed displacemenl
nn~Data
d2~d-2
(16 bil)
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
n ~ Dala (8 bit)
9-60
O,B
o,C
0,0
O,E
O,H
O,L
1, (HL)
1,(lX+d)
1,(IY+d)
1,A
1, B
1,C
1,0
1, E
1,H
1, L
2, (HL)
2,(lX+d)
2,(IY+d)
2,A
2,B
2,C
2,0
2,E
2,H
2,L
3,(HL)
3, (lX+d)
3,{IY+d)
3,A
3,B
3,C
3,0
3,E
3,H
3,L
4,(HL)
4,(IX+d)
4,(IY+d)
4,A
4,B
4,C
4,0
4,E
4,H
4,L
5,(HL)
5,(lX+d)
5,(IY+d)
5,A
5,B
5,C
5,0
CB40
CB41
CB42
CB43
CB44
CB45
CB4E
DDCBd4E
FDCBd4E
CB4F
CB4B
CB49
CB4A
CB4B
CB4C
CB4D
CB56
DDCBd56
FDCBd56
CB57
CB50
CB51
CB52
CB53
CB54
CB55
CB5E
DDCBd5E
FDCBd5E
CB5F
CB5B
CB59
CB5A
CB5B
CB5C
CB5D
CB66
DDCBd66
FDCBd66
CB67
CB60
CB61
CB62
CB63
CB64
CB65
CB6E
DDCBd6E
FDCBd6E
CB6F
CB6B
CB69
CB6A
z
en
12.15 Instruction Set: Alphabetical Order (Continued)
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CCF
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CPD
CPDR
CPI
CPIR
CPL
DAA
DEC
DEC
DEC
5,E
5,H
5,L
6, (HL)
6,(IX+d)
6, (IY+d)
6,A
6,B
6,C
6,D
6,E
6, H
6,L
7, (HL)
7,(1X+d)
7,(IY+d)
7,A
7,B
7,C
7,D
7,E
7,H
7,L
C,nn
M,nn
NC,nn
nn
NZ, nn
P,nn
PE,nn
PO, nn
Z,nn
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
n
(HL)
(IX+d)
(IY+d)
CB6B
CB6C
CB6D
CB76
DDCBd76
FDCBd76
CB77
CB70
CB71
CB72
CB73
CB74
CB75
CB7E
DDCBd7E
FDCBd7E
CB7F
CB7B
CB79
CB7A
CB7B
CB7C
CB7D
DCnn
FCnn
D4nn
CDnn
C4nn
F4nn
ECnn
E4nn
CCnn
3F
BE
DDBEd
FDBEd
BF
BB
B9
BA
BB
BC
BD
FEn
EDA9
EDB9
EDAl
EDBl
2F
27
35
DD35d
FD35d
(nn) = Address of memory location
d = signed displacement
nn = Data (16 bit)
d2=d-2
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DI
DJNZ
EI
EX
EX
EX
EX
EX
EXX
HALT
1M
1M
1M
IN
IN
IN
IN
IN
IN
IN
IN
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
IND
INDR
INI
n = Data (8 bit)
9-61
0CII)
A
B
BC
C
D
DE
E
H
HL
IX
IY
L
SP
d2
(SP),HL
(SP), IX
(SP),IY
AF,A'F'
DE,HL
0
1
2
A, (C)
A, (n)
B,(C)
C,(C)
D,(C)
E,(C)
H,(C)
L, (C)
(HL)
(IX+d)
(IY+d)
A
B
BC
C
D
DE
E
H
HL
IX
IY
L
SP
3D
05
OB
OD
15
lB
10
25
2B
DD2B
FD2B
2D
3B
F3
10d2
FB
E3
DDE3
FDE3
OB
EB
D9
76
ED 46
ED56
ED5E
ED7B
DBn
ED40
ED4B
ED50
ED5B
ED60
ED6B
34
DD34d
FD34d
3C
04
03
OC
14
13
lC
24
23
DD23
FD23
2C
33
EDAA
EDBA
EDA2
0
0
•
0
0
CO
(J
(/)
z
12.15 Instruction Set: Alphabetical Order (Continued)
INIR
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JR
JR
JR
JR
JR
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
(HL)
(IX)
(IV)
C,nn
M,nn
NC,nn
nn
NZ,nn
P,nn
PE,nn
PO, nn
Z,nn
C,d2
d2
NC,d2
NZ,d2
Z,d2
(BC),A
(DE), A
(HL),A
(HL), B
(HL),C
(HL), D
(HL), E
(HL), H
(HL), L
(HL),n
(IX+d),A
(IX+d),B
(IX+d),C
(lX+d),D
(IX+d),E
(lX+d),H
(IX+d), L
(IX + d), n
(IV+d), A
(IV+d),B
(IV+d),C
(IV+d),D
(IV+d), E
(IV+d),H
(IV+d), L
(IV+d), n
(nn),A
(nn),BC
(nn),DE
(nn),HL
(nn),IX
(nn),IV
(nn),SP
A,(BC)
A,(DE)
EDB2
E9
DDE9
FDE9
DAnn
FAnn
D2nn
C3nn
C2nn
F2nn
EAnn
E2nn
CAnn
38d2
18d2
30d2
20d2
28d2
02
12
77
70
71
72
73
74
75
36n
DD77d
DD70d
DD71d
DD72d
DD73d
DD74d
DD75d
DO 36dn
FD77d
FD70d
FD71d
FD72d
FD73d
FD74d
FD75d
FD36dn
32nn
ED 43nn
ED 53nn
22nn
DO 22nn
FD22nn
ED 73nn
OA
1A
(nn) ~ Address of memory location
d ~ signed displacement
nn ~ Data (16 bit)
d2~d-2
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
n ~ Data (8 bit)
9-62
A,(HL)
A,(IX+d)
A,(IV+d)
A, (nn)
A,A
A,B
A,C
A,D
A,E
A,H
A,I
A, L
A,n
B,(HL)
B,(IX+d)
B,(IV+d)
B,A
B,B
B,C
B,D
B,E
B,H
B,L
B,n
BC,(nn)
BC,nn
C,(HL)
C,(IX+d)
C,(IV+d)
C,A
C,B
C,C
C,D
C,E
C,H
C,L
C,n
D,(HL)
D,(lX+d)
D,(IV+d)
D,A
D,B
D,C
D,D
D,E
D,H
0, L
D,n
DE,(nn)
DE,nn
E,(HL)
E,(IX+d)
E,(IV+d)
7E
DD7Ed
FD7Ed
3Ann
7F
78
79
7A
7B
7C
ED 57
7D
3En
46
DD46d
FD46d
47
40
41
42
43
44
45
06n
ED4B
01nn
4E
DD4Ed
FD4Ed
4F
48
49
4A
4B
4C
40
OEn
56
DD56d
FD56d
57
50
51
52
53
54
55
16 n
ED5Bnn
11nn
5E
DD5Ed
FD5Ed
z
en
12.15 Instruction Set: Alphabetical Order (Continued)
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDD
LDDR
LDI
LDIR
NEG
NOP
OR
OR
OR
OR
OR
E,A
E,B
E,C
E,D
E,E
E, H
E,L
E,n
H, (HL)
H,(IX+d)
H,(IY+d)
H,A
H,B
H,C
H,D
H,E
H,H
H,L
H,n
HL, (nn)
HL, nn
I,A
IX, (nn)
IX, nn
IY, (nn)
IY, nn
L,(HL)
L,(lX+d)
L,(lY+d)
L,A
L, B
L,C
L,D
L,E
L, H
L,L
L,n
SP, (nn)
SP,HL
SP,IX
SP,IY
SP,nn
5F
58
59
5A
5B
5C
5D
1E n
66
DD66d
FD66d
67
60
61
62
63
64
65
26 n
2Ann
21nn
ED47
DD2Ann
DD 21nn
FD2Ann
FD21nn
6E
DD6Ed
FD6Ed
6F
68
69
6A
6B
6C
6D
2En
ED7Bnn
F9
DDF9
FDF9
31nn
EDA8
EDB8
EDAO
EDBO
EDn
00
B6
DDB6d
FDB6d
B7
BO
(HL)
(lX+d)
' (IY+d)
A
B
(nn) = Address of memory location
d = signed displacement
nn=Data (16 bit)
d2=d-2
OR
OR
OR
OR
OR
OR
OTDR
OTIR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTO
OUTI
POP
POP
POP
POP
POP
POP
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
n = Data (8 bit)
9-63
0
01)
C
D
E
H
L
n
(C),A
(C), B
(C),C
(C), D
(C),E
(C),H
(C),L
n,A
AF
BC
DE
HL
IX
IY
AF
BC
DE
HL
IX
IY
O,(HL)
O,(IX+d)
O,(IY+d)
O,A
O,B
O,C
O,D
O,E
O,H
O,L
1, (HL)
1, (IX+d)
1,(lY+d)
1,A
1, B
1,C
1,D
1, E
1, H
1, L
2,(HL)
2,(IX+d)
2, (IY+d)
B1
B2
B3
B4
B5
F6 n
EDBB
EDB3
ED79
ED41
ED49
ED51
ED59
ED61
ED69
D3n
EDAB
EDA3
F1
C1
D1
E1
DDE1
FD E1
F5
C5
D5
E5
DDE5
FDE5
CB86
DDCBd86
FDCBd86
CB87
CB80
CB81
CB82
CB83
CB84
CB85
CB8E
DDCBd8E
FDCBd8E
CB8F
CB88
CB89
CB8A
CB8B
CB8C
CB8D
CB96
DDCBd96
FDCBd96
0
0
•
«:)
«:)
CD
(.)
tn
Z
12.15 Instruction Set: Alphabetical Order (Continued)
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
2,A
2,B
2,C
2,D
2,E
2,H
2,L
3,(HL)
3,(IX+d)
3,(lY+d)
3,A
3,B
3,C
3,D
3,E
3,H
3,L
4,(HL)
4,(IX+d)
4,(IY+d)
4,A
4,B
4,C
4,D
4,E
4, H
4,L
5, (HL)
5, (IX+d)
5,(lY+d)
5,A
5,B
5,C
5, D
5,E
5,H
5,L
6,(HL)
6,(IX+d)
6,(IY+d)
6,A
6,B
6,C
6,D
6,E
6,H
6,L
7, (HL)
7, (IX+d)
7, (lY+d)
7,A
7,B
7,C
CB97
CB90
CB91
CB92
CB93
CB94
CB95
CB9E
DDCBd9E
FDCBd9E
CB9F
CB98
CB99
CB9A
CB9B
CB9C
CB9D
CBA6
DDCBdA6
FDCBdA6
CBA7
CBAO
CBA1
CBA2
CBA3
CBA4
CBA5
CBAE
DDCBdAE
FDCBdAE
CBAF
CBA8
CBA9
CBAA
CBAB
CBAC
CBAD
CBB6
DDCBdB6
FDCBdB6
CBB7
CBBO
CBB1
CBB2
CBB3
CBB4
CBB5
CBBE
DDCBdBE
FDCBdBE
CBBF
CBB8
CBB9
(nn) = Address of memory location
d = signed displacement
nn = Data (t6 bit)
d2=d-2
RES
RES
RES
RES
RET
RET
RET
RET
RET
RET
RET
RET
RET
RETI
RETN
RL
RL
RL
RL
RL
RL
RL
RL
RL
RL
RLA
RLC
RLC
RLC
Rl,.C
RLC
RLC
RLC
RLC
RLC
RLC
RLCA
RLD
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RRA
RRC
RRC
RRC
RRC
n = Data (8 bit)
9-64
7,D
7,E
7,H
7,L
C
M
NC
NZ
P
PE
PO
Z
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
(HL)
(IX+d)
(IY+d)
A
CBBA
CBBB
CBBC
CBBD
C9
D8
F8
DO
CO
FO
E8
EO
C8
ED4D
ED45
CB16
DDCBd16
FDCBd16
CB17
CB10
CB 11
CB12
CB13
CB14
CB15
17
CB06
DDCBd06
FDCBd06
CB07
CBOO
CB01
CB02
CB03
CB04
CB05
07
ED6F
CB1E
DDCBd1E
FDCBd1E
CB1F
CB18
CB19
CB1A
CB1B
CB1C
CB1D
1F
CBOE
DDCBdOE
FDCBdOE
CBOF
zen
n
01:1
12.15 Instruction Set: Alphabetical Order (Continued)
RRC
RRC
RRC
RRC
RRC
RRC
RRCA
RRD
RST
RST
RST
RST
RST
RST
RST
RST
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SCF
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
(nn)~Address
nn~
B
C
D
E
H
L
0
08H
10H
18H
20H
28H
30H
38H
A,(HL)
A,(IX+d)
A,(IY+d)
A,A
A,B
A,C
A,D
A,E
A,H
A, L
A, n
HL, BC
HL,DE
HL,HL
HL,SP
O,(HL)
O,(IX+d)
O,(IY+d)
O,A
O,B
O,C
O,D
O,E
O,H
O,L
1, (HL)
1, (IX+d)
1, (IY+d)
1,A
1, B
1, C
1, D
1, E
1,H
1, L
2, (HL)
of memory location
Data (16 bit)
CB08
CB09
CBOA
CBOB
CBOC
CBOD
OF
ED67
C7
CF
D7
DF
E7
EF
F7
FF
9E
DD9Ed
FD9Ed
9F
98
99
9A
9B
9C
9D
DEn
ED42
ED52
ED62
ED72
37
CBC6
DDCBdC6
FDCBdC6
CBC7
CBCO
CBC1
CBC2
CBC3
CBC4
CBC5
CBCE
DDCBdCE
FDCBdCE
CBCF
CBC8
CBC9
CBCA
CBCB
CBCC
CBCD
CBD6
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
d ~ displacement
d2~d-2
n ~ Data (8 bit)
9-65
2, (IX+d)
2, (IY+d)
2,A
2,B
2,C
2, D
2,E
2,H
2,L
3,(HL)
3, (IX+d)
3, (IY+d)
3,A
3,B
3,C
3,D
3,E
3,H
3,L
4, (HL)
4, (IX+d)
4, (IY+d)
4,A
4,B
4,C
4, D
4,E
4, H
4,L
5, (HL)
5,(IX+d)
5,(IY+d)
5,A
5,B
5,C
5,D
5,E
5,H
5,L
6, (HL)
6, (IX+d)
6, (IY+d)
6,A
6,B
6,C
6, D
6,E
6,H
6,L
7, (HL)
7, (IX+d)
7, (IY+d)
7,A
DDCBdD6
FDCBdD6
CBD7
CBDO
CBD1
CBD2
CB D3
CBD4
CB D5
CBDE
DDCBdDE
FDCBdDE
CBDF
CBD8
CBD9
CBDA
CBDB
CBDC
CBDD
CBE6
DDCBdE6
FDCBdE6
CBE7
CB EO
CBE1
CBE2
CBE3
CBE4
CBE5
CBEE
DDCBdEE
FDCBdEE
CBEF
CB E8
CBE9
CBEA
CBEB
CBEC
CBED
CBF6
DDCBdF6
FDCBdF6
CBF7
CBFO
CB F1
CBF2
CBF3
CBF4
CBF5
CBFE
DDCBdFE
FDCBdFE
CBFF
0
0
•
Q
Q
CD
CJ
Z
U)
12.15 Instruction Set: Alphabetical Order (Continued)
SET
SET
SET
SET
SET
SET
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRL
SRL
SRL
7,B
7,C
7,D
7,E
7,H
7,L
(HL)
(lX+d)
(IY+d)
A
B
C
D
E
H
L
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
(HL)
(IX + d)
(IY+d)
CBF8
CBF9
CBFA
CBFB
CBFC
CBFD
CB26
DDCBd26
FDCBd26
CB27
CB20
CB21
CB22
CB23
CB24
CB25
CB2E
DDCBd2E
FDCBd2E
CB2F
CB28
CB29
CB2A
CB2B
CB2C
CB2D
CB3E
DDCBd3E
FDCBd3E
SRL
SRL
SRL
SRL
SRL
SRL
SRL
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
A
B
C
D
E
H
L
(HL)
(IX+d)
(IY+d)
A
B
C
D
E
H
L
n
(HL)
(IX+d)
(lY+d)
A
B
C
D
E
H
L
n
CB3F
CB38
CB39
CB3A
CB3B
CB3C
CB3D
96
DD96d
FD96d
97
90
91
92
93
94
95
D6n
AE
DDAEd
FDAEd
AF
A8
A9
M
AB
AC
AD
EEn
12.16 Instruction Set: Numerical Order
OpCode
Mnemonic
OpCode
Mnemonic
OpCode
Mnemonic
00
01nn
02
03
04
05
06n
07
08
09
OA
OB
OC
OD
OEn
OF
10d2
11nn
12
13
14
NOP
LDBC,nn
LD(BC),A
INCBC
INCB
DECB
LDB,n
RLCA
EXAF,A'F'
ADDHL,BC
LDA,(BC)
DECBC
INCC
DECC
LDC,n
RRCA
DJNZd2
LD DE,nn
LD(DE),A
INC DE
INCD
15
16n
DECD
LDD,n
RLA
JRd2
ADDHL,DE
LDA,(DE)
DEC DE
INCE
DECE
LDE,n
RRA
JR NZ,d2
LDHL,nn
LD(nn),HL
INCHL
INCH
DECH
LDH,n
DAA
JRZ,d2
ADDHL,HL
2Ann
2B
2C
2D
2En
2F
30d2
31nn
32nn
33
34
35
36n
37
38
39
3Ann
3B
3C
3D
3En
LD HL,(nn)
DECHL
INCL
DECL
LDL,n
CPL
JRNC,d2
LDSP,nn
LD(nn),A
INCSP
INC (HL)
DEC (HL)
LD(HL),n
SCF
JRC,d2
ADDHL,SP
LDA,(nn)
DECSP
INCA
DECA
LDA,n
17
18d2
19
1A
1B
1C
10
1En
1F
20d2
21nn
22nn
23
24
25
26n
27
28d2
29
(nn) = Address of memory location
d = displacement
nn=Data (16 bit)
d2=d-2
n=Data (8 bit)
9-66
z
en
12.16 Instruction Set: Numerical Order (Continued)
OpCode
Mnemonic
OpCode
Mnemonic
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
CCF
LDB,B
LDB,C
LDB,D
LDB,E
LDB,H
LDB,L
LD B,(HL)
LDB,A
LDC,B
LDC,C
LDC,D
LDC,E
LDC,H
LDC,L
LDC,(HL)
LDC,A
LDD,B
LDD,C
LDD,D
LDD,E
LDD,H
LDD,L
LDD,(HL)
LDD,A
LDE,B
LDE,C
LDE,D
LDE,E
LDE,H
LDE,L
LDE,(HL)
LDE,A
LDH,B
LDH,C
LDH,D
LDH,E
LDH,H
LDH,L
LD H,(HL)
LDH,A
LDL,B
LDL,C
LDL,D
LDL,E
LDL,H
LDL,L
LD L,(HL)
LDL,A
LD(HL),B
LD(HL),C
LD(HL),D
LD(HL),E
74
75
76
LD(HL),H
LD(HL),L
HALT
LD (HL),A
LDA,B
LDA,C
LDA,D
LDA,E
LDA,H
LDA,L
LDA,(HL)
LDA,A
ADDA,B
ADDA,C
ADDA,D
ADDA,E
ADDA,H
ADDA,L
ADDA,(HL)
ADDA,A
ADCA,B
ADCA,C
ADCA,D
ADCA,E
ADCA,H
ADCA,L
ADCA,(HL)
ADCA,A
SUBB
SUBC
SUBD
SUBE
SUBH
SUBL
SUB (HL)
SUBA
SBCA,B
SBCA,C
SBCA,D
SBCA,E
SBCA,H
SBCA,L
SBCA,(HL)
SBCA,A
ANDB
ANDC
ANDD
ANDE
ANDH
ANDL
AND (HL)
ANDA
XORB
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
(nn) = Address of memory location
d = displacement
nn~Data
d2~d-2
(16 bit)
n ~ Data (B-bit)
9-67
0
Q)
OpCode
Mnemonic
A9
XORC
XORD
XORE
XORH
XORL
XOR(HL)
XORA
ORB
ORC
ORD
ORE
ORH
ORL
OR (HL)
ORA
CPB
CPC
CPD
CPE
CPH
CPL
CP(HL)
CPA
RETNZ
POPBC
JPNZ,nn
JPnn
CALL NZ,nn
PUSHBC
ADDA,n
RSTO
RETZ
RET
JP Z,nn
RLCB
RLCC
RLCD
RLCE
RLCH
RLCL
RLC(HL)
RLCA
RRCB
RRCC
RRCD
RRCE
RRCH
RRCL
RRC(HL)
RRCA
RLB
RLC
RLD
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2nn
C3nn
C4nn
C5
C6n
C7
C8
C9
CAnn
CBOO
CB01
CB02
CB03
CB04
CB05
CB06
CB07
CB08
CB09
CBOA
CBOB
CBOC
CBOD
CBOE
CBOF
CB10
CB11
CB12
Q
Q
•
Q
Q
co
(,)
en
Z
12.16 Instruction Set: Numerical Order (Continued)
OpCode
Mnemonic
OpCode
Mnemonic
OpCode
Mnemonic
CB13
CB14
CB15
CB16
CB17
CB1S
CB19
CB1A
CB1B
CB1C
CB1D
CB1E
CB1F
CB20
CB21
CB22
CB23
CB24
CB25
CB26
CB27
CB2S
CB29
CB2A
CB2B
CB2C
CB2D
CB2E
CB2F
CB38
CB39
CB3A
CB3B
CB3C
CB3D
CB3E
CB3F
CB40
CB41
CB42
CB43
CB44
CB45
CB46
CB47
CB48
CB49
CB4A
CB4B
CB4C
CB4D
CB4E
RLE
RLH
RLL
RL(HL)
RLA
RRB
RRC
RRD
RRE
RRH
RR L
RR(HL)
RRA
SLAB
SLAC
SLAD
SLAE
SLAH
SLAL
SLA(HL)
SLAA
SRAB
SRAC
SRAD
SRAE
SRAH
SRAL
SRA(HL)
SRAA
SRLB
SRLC
SRLD
SRLE
SRLH
SRLL
SRL(HL)
SRLA
BITO,B
BITO,C
BITO,D
BITO,E
BITO,H
BITO,L
BITO,(HL)
BITO,A
BIT1,B
BIT1,C
BIT1,D
BIT 1,E
BIT1,H
BIT1,L
BIT 1,(HL)
CB4F
CB50
CB51
CB52
CB53
CB54
CB55
CB56
CB57
CB5S
CB59
CB5A
CB5B
CB5C
CB5D
CB5E
CB5F
CB60
CB61
CB62
CB63
CB64
CB65
CB66
CB67
CB6S
CB69
CB6A
CB6B
CB6C
CB6D
CB6E
CB6F
CB70
CB71
CB72
CB73
CB74
CB75
CB76
CB77
CB78
CB79
CB7A
CB7B
CB7C
CB7D
CB7E
CB7F
CB80
CBS1
CB82
BIT1,A
BIT2,B
BIT2,C
BIT 2,0
BIT2,E
BIT2,H
BIT2,L
BIT2,(HL)
BIT2,A
BIT3,B
BIT3,C
BIT3,D
BIT3,E
BIT3,H
BIT3,L
BIT3,(HL)
BIT3,A
BIT4,B
BIT4,C
BIT4,D
BIT4,E
BIT4,H
BIT4,L
BIT4,(HL)
BIT4,A
BIT5,B
BIT5,C
BIT5,D
BIT5,E
BIT5,H
BIT5,L
BIT5,(HL)
BIT5,A
BIT6,B
BIT6,C
BIT6,D
BIT6,E
BIT6,H
BIT6,L
BIT6,(HL)
BIT6,A
BIT7,B
BIT7,C
BIT7,D
BIT7,E
BIT7,H
BIT7,L
BIT7,(HL)
BIT7,A
RESO,B
RESO,C
RES 0,0
CBS3
CBS4
CBS5
CBS6
CBS7
CBSS
CBS9
CBSA
CBSB
CBSC
CBSD
CBSE
CBSF
CB90
CB91
CB92
CB93
CB94
CB95
CB96
CB97
CB98
CB99
CB9A
CB9B
CB9C
CB9D
CB9E
CB9F
CBAO
CBA1
CBA2
CBA3
CBA4
CBA5
CBA6
CBA7
CBA8
CBA9
CBAA
CBAB
CBAC
CBAD
CBAE
CBAF
CBBO
CBB1
CBB2
CBB3
CBB4
CBB5
CBB6
RESO,E
RESO,H
RESO,L
RESO,(HL)
RESO,A
RES 1,B
RES1,C
RES 1,0
RES 1,E
RES 1,H
RES 1,L
RES 1,(HL)
RES 1,A
RES2,B
RES2,C
RES2,D
RES2,E
RES2,H
RES2,L
RES2,(HL)
RES2,A
RES3,B
RES3,C
RES3,D
RES3,E
RES3,H
RES3,L
RES3,(HL)
RES3,A
RES4,B
RES4,C
RES4,D
RES4,E
RES4,H
RES4,L
RES4,(HL)
RES4,A
RES5,B
RES5,C
RES5,D
RES5,E
RES5,H
RES5,L
RES5,(HL)
RES5,A
RES6,B
RES6,C
RES6,D
RES6,E
RES6,H
RES6,L
RES6,(HL)
(nn) ~ Address of memory location
d ~ displacement
nn ~ Data (16 bit)
d2~d-2
n ~ Data (8-bit)
9-68
z
en
12.16 Instruction Set: Numerical Order (Continued)
(")
OpCode
Mnemonic
OpCode
Mnemonic
OpCode
Mnemonic
CBB7
CBB8
CBB9
CBBA
CBBB
CBBC
CBBD
CBBE
CBBF
CBCO
CBC1
CBC2
CBC3
CBC4
CBC5
CBC6
CBC7
CBC8
CBC9
CBCA
CBCB
CBCC
CBCD
CBCE
CBCF
CBDO
CBDl
CBD2
CBD3
CBD4
CBD5
CBD6
CBD7
CBD8
CBD9
CBDA
CBDB
CBDC
CBDD
CBDE
CBDF
CBEO
CBE1
CBE2
CBE3
CBE4
CBE5
CBE6
CBE7
CBE8
CBE9
CBEA
CBEB
RES6,A
RES7,B
RES 7,C
RES 7,D
RES 7,E
RES7,H
RES7,L
RES 7,(HL)
RES 7,A
SETO,B
SETO,C
SETO,D
SETO,E
SETO,H
SETO,L
SETO,(HL)
SETO,A
SET1,B
SET1,C
SET1,D
SET1,E
SET1,H
SET1,L
SET 1,(HL)
SET1,A
SET2,B
SET2,C
SET2,D
SET2,E
SET2,H
SET2,L
SET2,(HL)
SET2,A
SET3,B
SET3,C
SET3,D
SET3,E
SET3,H
SET3,L
SET3,(HL)
SET3,A
SET 4,B
SET4,C
SET 4,D
SET 4,E
SET 4,H
SET 4,L
SET 4,(HL)
SET 4,A
SET5,B
SET5,C
SET5,D
SET5,E
CBEC
CBED
CBEE
CBEF
CBFO
CBF1
CBF2
CBF3
CBF4
CBF5
CBF6
CBF7
CBF8
CBF9
CBFA
CBFB
CBFC
CBFD
CBFE
CBFF
CCnn
CDnn
CEn
CF
DO
D1
D2nn
D3n
D4nn
D5
D6n
D7
D8
D9
DAnn
DBn
DCnn
DD09
DD19
DD21nn
DD22
DD23
DD29
DD2Ann
DD2B
DD34d
DD35d
DD36dn
DD39
DD46d
DD4Ed
DD56d
DD5Ed
SET5,H
SET5,L
SET5,(HL)
SET5,A
SET6,B
SET6,C
SET6,D
SET6,E
SET6,H
SET6,L
SET6,(HL)
SET6,A
SET 7,B
SET7,C
SET7,D
SET7,E
SET7,H
SET7,L
SET7,(HL)
SET7,A
CALLZ,nn
CALLnn
ADCA,n
RST8
RETNC
POP DE
JP NC,nn
OUT (n),A
CALL NC,nn
PUSH DE
SUBn
RST10H
RETC
EXX
JP,C,nn
INA,(n)
CALLC,nn
ADDIX,BC
ADDIX,DE
LD IX,nn
LD(nn),IX
INCIX
ADDIX,IX
LD IX,(nn)
DEC IX
INC (IX+d)
DEC (IX+d)
LD (IX+d),n
ADDIX,SP
LDB,(IX+d)
LDC,(IX+d)
LDD,(IX+d)
LD E,(IX+d)
DD66d
DD6Ed
DD70d
DD71d
DD72d
DD73d
DD74d
DD75d
DD77d
DD7Ed
DD86d
DDSEd
DD96d
DD9Ed
DDA6d
DDAEd
DDB6d
DDBEd
DDCBd06
DDCBdOE
DDCBd16
DDCBd1E
DDCBd26
DDCBd2E
DDCBd3E
DDCBd46
DDCBd4E
DDCBd56
DDCBd5E
DDCBd66
DDCBd6E
DDCBd76
DDCBd7E
DDCBd86
DDCBd8E
DDCBd96
DDCBd9E
DDCBdA6
DDCBdAE
DDCBdB6
DDCBdBE
DDCBdC6
DDCBdCE
DDCBdD6
DDCBdDE
DDCBdE6
DDCBdEE
DDCBdF6
DDCBdFE
DDE1
DDE3
DDE5
DDE9
LDH,(IX+d)
LDL,(IX+d)
LD(IX+d),B
LD(IX+d),C
LD(IX+d),D
LD (IX+d),E
LD(IX+d),H
LD(IX+d),L
LD(IX+d),A
LD A,(IX+ d)
ADD A,(IX + d)
ADCA,(lX+d)
SUB (IX+d)
SBC A,(IX + d)
AND (IX+d)
XOR(IX+d)
OR (lX+d)
CP(IX+d)
RLC(lX+d)
RRC(IX+d)
RL(IX+d)
RR(IX+d)
SLA(IX+d)
SRA(IX+d)
SRL(IX+d)
BIT O,(IX + d)
BIT 1,(IX + d)
BIT 2,(IX + d)
BIT 3,(IX + d)
BIT 4,(IX + d)
BIT 5,(IX + d)
BIT6,(IX+d)
BIT7,(IX+d)
RES O,(IX + d)
RES 1,(IX+d)
RES 2,(IX + d)
RES 3,(IX + d)
RES 4,(IX + d)
RES 5,(IX + d)
RES 6,(IX + d)
RES 7 ,(IX + d)
SET O,(IX + d)
SET 1,(IX+d)
SET2,(IX+d)
SET3,(lX+d)
SET 4,(IX + d)
SET 5,(IX + d)
SET6,(lX+d)
SET 7 ,(IX + d)
POP IX
EX (SP),IX
PUSH IX
JP(IX)
(nn) ~ Address of memory location
nn~Data
(16 bit)
d = displacement
d2~d-2
n ~ Data (a-bit)
9-69
CD
0
0
II
0
0
CO
(.)
tJ)
Z
12.16 Instruction Set: Numerical Order (Continued)
OpCode
Mnemonic
DDF9
DEn
DF
EO
E1
E2nn
E3
E4nn
E5
E6n
E7
E8
E9
EAnn
EB
ECnn
ED40
ED41
ED42
ED43nn
ED44
ED45
ED46
ED47
ED48
ED49
ED4A
ED4Bnn
ED4D
ED50
ED51
ED52
ED53nn
ED56
ED57
ED58
ED59
ED5A
ED5Bnn
ED5E
ED60
ED61
ED62
ED67
ED68
ED69
ED6A
ED6F
ED72
ED73nn
ED78
ED79
ED7A
LDSP,IX
SCBA,n
RST18H
RET PO
POPHL
JP PO,nn
EX (SP),HL
CALLPO,nn
PUSH HL
ANDn
RST20H
RETPE
JP(HL)
JP PE,nn
EXDE,HL
CALLPE,nn
IN B,(C)
OUT (C),B
SBC HL,BC
LD (nn),BC
NEG
RETN
IMO
LDI,A
INC,(C)
OUT (C),C
ADCHL,BC
LDBC,(nn)
RETI
IND,(C)
OUT (C),D
SBCHL,DE
LD (nn),DE
1M 1
LDA,I
INE,(C)
OUT (C), E
ADCHL,DE
LDDE,(nn)
1M2
INH,(C)
OUT (C),H
SBCHL,HL
RRD
INL,(C)
OUT (C),L
ADCHL,HL
RLD
SBC HL,SP
LD(nn),SP
INA,(C)
OUT (C),A
ADCHL,SP
(nn) = Address of memory localion
d = displacemenl
nn=Dala (16 bil)
d2=d-2
OpCode
Mnemonic
OpCode
Mnemonic
ED7Bnn
EDAO
EDA1
EDA2
EDA3
EDA8
EDA9
EDAA
EDAB
EDBO
EDB1
EDB2
EDB3
EDB8
EDB9
EDBA
EDBB
EEn
EF
FO
F1
F2nn
F3
F4nn
F5
F6n
F7
Fa
F9
FAnn
FB
FCnn
FD09
FD19
FD21nn
FD22nn
FD23
FD29
FD2Ann
FD2B
FD34d
FD35d
FD36dn
F039
FD46d
FD4Ed
FD56d
FD5Ed
FD66d
FD6Ed
FD70d
FD71d
FD72d
LDSP,(nn)
LDI
CPI
INI
OUTI
LDD
CPD
IND
OUTO
LDIR
CPIR
INIR
OTIR
LDDR
CPDR
INDR
OTDR
XORn
RST28H
RETP
POPAF
JP P,nn
DI
CALLP,nn
PUSHAF
ORn
RST30H
RETM
LDSP,HL
JPM,nn
EI
CALLM,nn
ADDIY,BC
ADDIY,DE
LD IY,nn
LD (nn),IY
INCIY
ADDIY,IY
LD IY,(nn)
DECIY
INC (lY+d)
DEC (IY+d)
LD(IY+d),n
ADDIY,SP
LDB,(IY+d)
LDC,(IY+d)
LDD,(lY+d)
LD E,(IY+d)
LDH,(IY+d)
LD L,(IY+d)
LD(IY+d),B
LD(IY+d),C
LD(IY+d),D
FD73d
FD74d
FD75d
FD77d
FD7Ed
FD86d
FD8Ed
FD96d
FD9Ed
FDA6d
FDAEd
FDB6d
FDBEd
FDE1
FDE3
FDE5
FDE9
FDF9
FDCBd06
FDCBdOE
FDCBd16
FDCBd1E
FDCBd26
FDCBd2E
FDCBd3E
FDCBd46
FDCBd4E
FDCBd56
FDCBd5E
FDCBd66
FDCBd6E
FDCBd76
FDCBd7E
FDCBd86
FDCBd8E
FDCBd96
FDCBd9E
FDCBdA6
FDCBdAE
FDCBdB6
FDCBdBE
FDCBdC6
FDCBdCE
FDCBdD6
FDCBdDE
FDCBdE6
FDCBdEE
FDCBdF6
FDCBdFE
FEn
FF
LD(IY+d),E
LD(IY+d),H
LD(IY+d),L
LD(IY+d),A
LDA,(IY+d)
ADD A,(IY + d)
ADC A,(IY + d)
SUB (IY+d)
SBC A,(IY + d)
AND (IY+d)
XOR(IY+d)
OR (IY+d)
CP(IY+d)
POPIY
EX (SP), IY
PUSHIY
JP(IY)
LDSP,IY
RLC(IY+d)
RRC(IY+d)
RL(IY+d)
RR (IY+d)
SLA (IY+d)
SRA(IY+d)
SRL(IY+d)
BIT O,(IY + d)
BIT 1,(lY+d)
BIT 2,(IY + d)
BIT 3,(IY + d)
BIT4,(IY+d)
BIT 5,(IY + d)
BIT6,(IY+d)
BIT7,(lY+d)
RESO,(IY+d)
RES 1,(IY + d)
RES 2,(IY + d)
RES3,(lY+d)
RES4,(lY+d)
RES 5,(lY+d)
RES 6,(IY + d)
RES7,(IY+d)
SET O,(IY + d)
SET 1,(IY + d)
SET 2,(IY + d)
SET3,(lY+d)
SET 4,(IY + d)
SET 5,(IY + d)
SET 6,(IY + d)
SET7,(IY+d)
CPn
RST38H
n = Data (a-bil)
9-70
13.0 Data Acquisition System
the need for battery operation or at least battery backup. At
some fixed times or at some particular time durations, the
system takes readings by selecting one of the analog input
channels, commands the AID to perform a conversion,
reads the data, and then formats it for transmission; or, the
system checks the readings against set points and transmits a warning if the set paints are exceeded. With the addition of the RTC, the host need not command the remote
system to take these readings each time it is necessary.
The NSC800 could simply set up the RTC to interrupt it at a
previously defined time and when the interrupt occurs, make
the readings. The resultant values could be stored in the
NSC810A for later correlation. In the example of temperature monitoring in a building, it might be desired to know the
high and low temperatures for a 12-hour period. After compiling the information, the system could dump the data to
the host over the communications link. Note from the schematic that the current for the communication link is supplied
by the host to remove the constant current drain from the
battery supply.
The required clocks for the two peripheral devices are generated by the two timers in the NSC810A. Through the use
of various divisors, the master clock generated by the
NSC800 is divided down to produce the clocks. Four examples are shown in the table following Figure 20.
A natural application for the NSC800 is one that requires
remote operation. Since power consumption is low if the
system consists of only CMOS components, the entire
package can conceivably operate from only a battery power
source. In the application described herein, the only source
of power will be from a battery pack composed of a stacked
array of NiCad batteries (see Figure 20).
The application is that of a remote data acquisition system.
Extensive use is made of some of the other LSI CMOS components manufactured by National: notably the ADC0816
and MM58167. The ADC0816 is a 16-channel analog-todigital converter which operates from a 5V source. The
MM58167 is a microprocessor-compatible real-time clock
(RTC). The schematic for this system is shown in Figure 20.
All the necessary features of the system are contained in six
integrated circuits: NSC800, NSC810A, NSC831, HN6136P,
ADC0816, and MM58167. Some other small scale integration CMOS components are used for normal interface requirements. To reduce component count, linear selection
techniques are used to generate chip selects for the
NSC810A and NSC831.lncluded also is a current loop communication link to enable the remote system to transfer data
collected to a host system.
In order to keep component count low and maximize effectiveness, many of the features of the NSC800 family have
been utilized. The RAM section of the NSC810A is used as
a data buffer to store intermediate measurements and as
scratch pad memory for calculations. Both timers contained
in the NSC810A are used to produce the clocks required by
the AID converter and the RTC. The Power-Save feature of
the NSC800 makes it possible to reduce system power consumption when it is not necessary to collect any data. One
of the analog input channels of the AID is connected to the
battery pack to enable the CPU to monitor its own voltage
supply and notify the host that a battery change is needed.
All the crystal frequencies are standard frequencies. The
various divisors listed are selected to produce, from the
master clock frequency of the NSC800, an exact 32,768 Hz
clock for the MM58167 and a clock within the operating
range of the AID converter.
The MM58167 is a programmable real-time clock that is
microprocessor compatible. Its data format is BCD. It allows
the system to program its interrupt register to produce an
interrupt output either on a time of day match (which includes the day of the week, the date and month) and/or
every month, week, day, hour, minute, second, or tenth of a
second. With this capability added to the system, precise
time of day measurements are possible without having the
CPU do timekeeping. The interrupt output can be connected, through the use of one port bit of the NSC810A, to put
the CPU in the power-save mode and reenable it at a preset
time. The interrupt output is also connected to one of the
hardware restart inputs (RSTB) to enable time duration
measurements. This power-down mode of operation would
not be possible if the NSC800 had the duties of timekeep-
In operation, the NSC800 makes readings on various input
conditions through the ADC0816. The type of devices connected to the AID input depends on the nature of the remote environment. For example, the duties of the remote
system might be to monitor temperature variations in a large
building. In this case, the analog inputs would be connected
to temperature transducers. If the system is situated in a
process control environment, it might be monitoring fluid
flow, temperatures, fluid levels, etc. In either case, operation
would be necessary even if a power failure occurred, thus
9-71
z
en
oco
o
o
NSC800
....w
Vee
Ir
4-
*
T
-:!:
1"
co
.!..J
'"
60pf
E
~EE
TEXT FOR
FREQUENCIES
roc
EXPAND
A12
ADC
CSO
A13
P8
ADD
CSl
START
ALE
;
.---- IO/iA
c:
PA(o-7)
,---
Ii
PS
RD
TOOUT
WR
WR
TIIN
.....
S.lK
2N2222
CIK I-
AO(O-7)
PB
CS
PCl
3
'§
3-
XMIT
TO
REMOTE
5'
t:
J!
+--l
-=
5.~ ~---201
RECV
PA(0-7)
NSC810A
A13
~
V-=
~
2N2222
IOTjiA
I.lIoI74HC32
MM74HC04
CD
.---20 mA
l10UT I - - CSC IN
ALE
lojil
I~
-
~
(SEE ADC0816
DATA SHEET)
MM74HC04
RO
RESET OUT
RSTB
~
REFERENCE
GENERATOR
-=
rvee
ALE
0-
::;
0"
VSAT1
P03I--
XOUT
Vee
0"
PCO
iffi
AD(0-7)
1.SK
c:::
15
ANALOG
CHANNElS
V~_)
NScaOO
T
()
.Q
ClK
...-ViR
I-
»
I:
1N1J ICOMMON
COMPARATOR
IN
0(0-7)
V,,~+)
.--- ALE
XIN
A(8-15)
AO(o-~~ca31
c
am
II:
III:
III:
II:
II:
AD8
AS
b
TC
INl
I
I
ADA
A9
A8
RSTA
E
Al0
A9
M"74HC041
20pF
Vee
ADC0816
Al0
Vee
INO
PCO
I
TOIN
~
I--- ViR
INT OUT
.,f-----2-
-=
MM58167
i--- AD
I - - Al
I - - A2
i--- A3
i--- A4
i--- cs
i--- iffi
V
AO(o-7)
74H0373
~
H
7)
ft-;;;
'.
0(1-8)
Q(1-8)
Vee
GND
I--
h
lf~ ~~
RO
0(1
A(~12)H
-= _
...... _
A15
0(0-7)
HN6136P
POWER DOWN
MM74HC04
R~~~
2500
0(0-7)
oro
A15 _
CS
~~
OE2
GND
-=
FIGURE 20. Remote Data Acquisition
TL/C/5171-34
Z
13.0 Data Acquisition System
tn
oCD
(Continued)
ing. When in the power-save mode, the system power requirements are decreased by about 50%, thus extending
battery life.
signal which is connected to the RSTA interrupt input of the
NSC800.
When operating, the system shown consumes about 125
mw. When in the power-save mode, power consumption is
decreased to about 70 mw. If, as is likely, the system is in
the power-save mode most of the time, battery life can be
quite long depending on the amp-hour rating of the batteries
incorporated into the system. For example, if the battery
pack is rated at 5 amp-hours, the system should be able to
operate for about 400-500 hours before a battery charge or
change is required.
As shown in the schematic (refer to Figure 20), analog input
INO is connected to the battery source. In this way, the CPU
can monitor its own power source and notify the host that it
needs a battery replacement or charge. Since the battery
source shown is a stacked array of 7 NiCads producing
8.4V, the converter input is connected in the middle so that
it can take a reading on two or three of the cells. Since
NiCad batteries have a relatively constant voltage output
until very nearly discharged, the CPU can sense that the
"knee" of the discharge curve has been reached and notify
the host.
Communication with the peripheral devices (MM58167 and
ADC0816) is accomplished through the 1/0 ports of the
NSC810A and NSC831. The peripheral devices are not connected to the bus of the NSC800 as they are not directly
compatible with a multiplexed bus structure. Therefore, additional components would be required to place them on the
microprocessor bus. Writing data into the MM58167 is performed by first putting the desired data on Port A, followed
by selecting the address of the internal register and applying
the chip select through the use of Port B. A bit set and clear
operation is performed to emulate a pulse on the bit of Port
B connected to the WR input of the MM58167. For a read
operation, the same sequence of operations is performed
except that Port A is set for the input mode of operation and
the RD line is pulsed. Similar techniques are used to read
converted data from the AID converter. When a conversion
is desired, the CPU selects a channel and commands the
ADC0816 to start a conversion. When the conversion is
complete, the converter will produce an End-of-Conversion
Typical Timer Output Frequencies
Crystal Frequency
CPU Clock Output
Timer 0 Output
Timer 1 Output
2.097152 MHz
1.048576 MHz
262.144 kHz
divisor = 4
32.768 kHz
divisor = 8
3.276800 MHz
1.638400 MHz
327.680 kHz
divisor = 5
32.768 kHz
divisor = 10
4.194304 MHz
2.097152 MHz
262.144 kHz
divisor = 8
32.768 kHz
divisor = 8
4.915200 MHz
2.457600 MHz
491.520 kHz
divisor = 5
32.768 kHz
divisor = 15
9-73
o
o
g
B
en
z
14.0 NSC800M/883B MIL-STD-833
Class C Screening
National Semiconductor offers the NSC800D and NSC800E
with full class 8 screening per MIL-STD-883 for Military!
Aerospace programs requiring high reliability. In addition,
this screening is available for all of the key NSC800 peripheral devices.
Electrical testing is performed in accordance with
RESTS800X, which tests or guarantees all of the electrical
performance characteristics of the NSC800 data sheet. A
copy of the current revision of RETS800X is available upon
request.
100% Screening Flow
Test
Requirement
MIL-STD-883 Method/Condition
Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Fine Leak
Gross Leak
Burn-In
100%
100%
100%
100%
100%
100%
100%
20108
1008 C 24 Hrs. @ + 150'C
1010 C 10 Cycles - 65'C! + 150'C
2001 E 30,000 G's, Yl Axis
1014AorB
1014C
1015160 Hrs. @ + 125'C (using
burn-in circuits shown below)
+ 25'C DC per RETS800X
10% Max
+ 125'C AC and DC per RETS800X
- 55'C AC and DC per RETS800X
+ 25'C AC per RETS800X
5005
Final Electrical
PDA
QA Acceptance
Quality Conformance
External Visual
100%
100%
100%
100%
Sample Per
Method 5005
100%
2009
15.0 Burn-In Circuits
5240HR
NSC800D/883B (Dual-in-Line)
.
,
,
••
"
.
IS
7
100kHz
5.5V
31
•
,•
51
55.
1D
tiH
I
5241HR
NSC800E/883B (Lead less Chip Carrier)
33
51
I
1.5kHz
(NOTfZI
"31
30
10
"
"
""
"
""
"
""
NC-;;
11
""
"
11
1B
r
,"i,, 44143142 411.0
4 I
,•
NC-T,
1'07£'1
.,
1D
3B
3751
51
44-PINLfADLESS
PACKAGE
"
"
-li-'c
"
31
30
"
11
23
1.5 kHz
(NOTE 2)
3B
NC-¥.
100kHz
(NOTEZ)
..
..
1819
20 21
21:3 24rSre 21ra
"
'c
TL/C/5171-32
Top View
....
TUC/5171-33
All resistors 2.7 kll unless marl: Vee is the 5V supply pin.
Ground (GND): Ground reference pin.
PC3/TG: TG is the timer gating signal.
PC4/T1IN: T11N is the clock input for timer 1.
PCS/T10UT: T10UT is the programmable output of timer 1.
8.0 Connection Diagrams
Chip Carrier
Dual-In-Llne Package
PC5/T1DUT
PC3ITG
PC4/T1IN
TOIN
RESET
PC5/Tl0UT
TOOUT
lOT/iii
CE
1.
liii
WR
ALE
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
GND
10
11
12
13
14
15
16
17
18
19
20
NSC810A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
TOIN
PC3/
TG vee
~~\IN
Vee
PC2I5fii
PCl/8F
PCo/lIlTli
PB7
PB6
PB5
P84
PB3
PB2
P81
P80
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
TDDUT
IDT/M
CE
liii
Wii
NC
ALE
ADO
ADl
AD2
AD3
PC1/BF
11 ~ PCI~B7
C
6 5 4 3 2 1 44 43 42 41 40
7
•
8
9
10
11
12
NSC810A
13
14
15
16
17
18 1920 21 22 23242526 27 28
///// f
39
3B
37
36
35
34
33
32
31
30
29
PB6
PB5
PB4
PB3
PB2
NC
PBl
PBO
PA7
PA6
PA5
t \ \\"'"
AD4 AD5 AD6 AD7 GND NC PAO PAl PA2 PA3 PA4
TL/C/5517-11
Top View
NC= no connect
TLiC/5517-10
Order Number NSC810AE or NSC810AV
See NS Package Number E44B or V44A
Top View
Order Number NSC810AD or NSC810AN
See NS Package Number D40C or N40A
9-82
9.0 Functional Description
Figure 1 is a detailed block diagram of the NSC810A. The
functional description that follows describes the RAM, 1/0
and TIMER sections.
input must be low (RAM select) and the CE input must be
high at the falling edge of ALE to address the RAM. Address
bit AD7 is a "don't care" for RAM addressing. Timing for
RAM read and write operations is shown in the timing dia·
grams. The RAM is 128 x 8.
9.1 RANDOM ACCESS MEMORY (RAM)
The memory portion of the RAM·I/O·timer is accessed by a
7·bit address input to pins ADO through ADS. The 10T/fiij
9.2 DETAILED BLOCK DIAGRAM
INTERNAL
DATA
BUS
...
,
,..,
8
CE---+
MOR
Wii~
l
iiil...!....
HANDSHAKE
LOGIC
CONTROL
LOGIC
~
10T/M..!.....
,..
"
11
ALE---+
PORT A
,.. PAD-PAT
"'II
J-+
DOR
A
1',
--"0..'
RESET~
.... 21-28 ...
--"0..
..oil
,.....
....
"I
.... 29-36 ...
RAM
102481TS
(128 x81
PGRT B
..oL
--"0..
"I
I'
... ,
~
ODR
B
"'.
...
....
ADO·ADT
.... 12-19 II.
"
'"
ADDRESS I
DATA
BUFFERS AND
LATCHES
"'- --...
1"'11
,..
"
3T-39. 1.2. 5
-,..
,..,
I
T1 COMMAND
TO COMMAND
L
3
TOIN_
•
TO PRESCALE
PRESCALE
Vee.!!..
....
,.....
~ Ito..,..
....
....
PORT C
........
TIMER MOD~
REGISTERS
....
.
....
Jo..
"
I'
...
'"
"'- --...
"
..oL
....
,.. P8D-PST
....
~
11
HIGH
ORDER
11
LOW
OROER
_i
--...
,..
-
+-i
!
TO
HIGH
ORDER
TO
LOW
ORDER
I'
.... PCO-Pcs"
HANDSHAKE
AND TIMER
FUNCTIONS
~
ODR
C
II.
r..:...
6
T1
PRESCALE
I
TODUT
GND..!!..
TLlC/5517-12
FIGURE 1
9·83
9.0 Functional Description (Continued)
TABLE I. 110 and Timer Address Designations
9.3 1/0 PORTS
The three 1/0 ports, labeled A, B, and C, can be pro·
grammed to be almost any combination of Input and Output
bits. Ports A and B are configured as 8 bits wide, while port
C is 6 bits. There are four different modes of operation for
the ports. Three of the modes are for timed transfer of data
between the peripheral and the NSC810A, this is called
strobed 1/0. The fourth mode is for direct transfer without
handshaking with the peripheral.
8-Bit Address Field
Designation
R(Read)
Bits
1/0 Port, Timer, etc. W(Wrlte)
7 6 5 4 3 2 1 0
The NSC810A can be programmed to operate in four differ·
ent modes. One of these modes (Basic 1/0) allows direct
transfer of 1/0 data without any handshaking between the
NSC810A and the peripheral. The other three modes
(Strobed 1/0) provide for timed transfers of 1/0 data with
handshaking between the NSC810A and the peripheral.
The determination of the mode, data direction and data is
done by five registers which are, handily, under program
control. The Mode Definition Register (MDR), oddly enough,
determines which mode the device will operate in, while the
Data Direction Register (DDR) establishes the direction of
the data transfer. The Data register contains the data that is
being sent or has been received. The other two registers
(bit-set, bit-clear) allow the individual bits in the data register
to be set or cleared without affecting the other bits. Each
port has its own set of these registers, except the MDR
which affects ports A and Conly.
In the strobed 1/0 modes, port C bits 0, 1 and 2 function as
INTR (for the processor), BF, and STB respectively.
9.3.1 Registers
As can be seen in Table I, all the registers affecting 1/0
transfer are grouped at the lower address locations, this
allows quicker handling and more maneuverability in tight
data transfers. Also note in Table I that the NSC810A uses
23 1/0 addresses out of a block of 26. The upper three bits
of the address are determined by the chip enable address.
• Mode Definition Register (MDR)
As noted above this register defines the operating mode for
ports A and C (port B is always in the basic 1/0 mode). The
upper 3 bits of port C will also be in the basic 1/0 mode
even when the lower 3 bits are being used for handshaking.
0 0 0 0 Port A (Data)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Port B (Data)
Port C (Data)
Not Used
DDR- PortA
DDR - PortB
DDR- PortC
Mode Definition Reg.
Port A - Bit-Clear
Port B - Bit-Clear
Port C - Bit-Clear
Not Used
Port A - Bit-Set
Port B - Bit-Set
Port C - Bit-Set
Not Used
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Timer 0 (LB)
Timer 0 (HB)
Timer 1 (LB)
Timer 1 (HB)
STOP Timer 0
START Timer 0
STOP Timer 1
START Timer 1
Timer 0 Mode
Timer 1 Mode
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
R/W
R/W
R/W
..
W
W
W
W
W
W
W
..
..
···•
W
W
W
W
W
W
W
R/W
R/W
....
....
....
x = don't care
LB ~ low-order byte
HB ~ high-order byte
• A write accesses the modulus register, a read the read buffer.
•• A read from an unused location reads invalid data. a write does not affect
any operation of NSCB10A.
The four modes are as follows:
Mode O-Basic 1/0 (Input or Output)
Mode 1-Strobed Mode Input
Mode 2-Strobed Mode Output (Active Peripheral Bus)
TABLE II. Mode Definition Register Bit Assignments
Mode 3-Strobed Mode Output (TRI-STATE Peripheral
Bus)
Mode
The address assignment of the MDR is xxx00111 as shown
in Table I. Table II specifies the data that must be loaded
into the MDR to select the mode.
0
1
2
3
• Data Direction Registers (DDR)
Each port has a DDR that determines whether an individual
port bit will be an input or an output. This can be considered
the traffic light for the transfer of data between the CPU and
the peripheral. Each port bit has a corresponding bit in this
register. If the DDR bit is set (1) the port bit is an output; if it
is cleared (0) the port bit is an input. The DDR bits cannot
be written to individually. The register as a whole must be
set to be consistent with all desired port bit directions.
9-84
Bit
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
1
0
1
0
1
1
9.0 Functional Description
z
en
(Continued)
QC)
TABLE III. Bit-Set and Clear Examples
Any write or read to the port bits contradicting the direction
established by the DDR will not affect the port bits output or
input. However, a write to a port bit, defined as an input, will
modify the output latch and a read to a port bit, defined as
an output, will read this output latch. See Figure 2.
• Data Registers
Operation
PortB
These registers contain the actual data being transferred
between the CPU and the peripheral. In Basic 1/0, data
presented by the peripheral (read cycle) will be latched on
the falling edge of RD. Data presented by the CPU (write
cycle) will be valid after the rising edge of WR (see AC characteristics for exact timing).
SetB7
CiearB2
andBO
SetB4, B3
and B1
Address
xxx01101
xxx01001
xxx01101
Data
10000000
00000101
00011010
Port Pins
Prior State
Next State
00001111
10001111
10001111
10001010
10001010
10011010
9.3.2 Modes
Two data transfer modes are implemented: Basic 1/0 and
Strobed 1/0. Strobed 1/0 can be further subdivided into
three categories: Strobed Input, Strobed Output (active peripheral bus) and Strobed Output (TRI-STATE peripheral
bus). The following descriptions detail the functions of these
categories.
• Basic 1/0
Basic I/O mode uses the RD and WR CPU bus signals to
latch data at the peripheral bus. This mode is the permanent
mode of operation for ports Band C. Port A is in this mode if
the MDR is set to mode o. Read and write byte operations
and bit operations can be done in Basic 1/0. Timing for
these modes is shown in the AC Characteristics Table and
described with the data register definitions.
When the NSC810A is reset, all registers are cleared to
zero. This results in the basic mode of operation being selected, all port bits are made inputs and the output latch for
each port bit is cleared to zero. The NSC810A, at this pOint,
can read data from any peripheral port without further setup. If outputs are desired, the CPU merely has to program
the appropriate DDR and then send data to the data ports.
During Strobed 1/0, data presented by the peripheral must
be valid on the rising edge of STB. Data received by the
peripheral will be valid on the rising edge of STB. Data
latched by the port on the rising edge of STB will be preserved until the next CPU read or STB signal.
• Bit Set-Clear Registers
The 1/0 features of the RAM-I/O-timer allow modification of
a single bit or several bits of a port with the Bit-Set and BitClear commands. The address selected indicates whether a
Bit-Set or Clear will take place. The incoming data on the
addressl data bus is latched at the trailing edge of the WR
strobe and is treated as a mask. All bits containing 1s will
cause the indicated operation to be performed on the corresponding port bit. All bits of the mask with Os cause the
corresponding port bits to remain unchanged. Three sample
operations are shown in Table III using port B as an example.
INTERNAL
DATA BUS
o
.....
WRISET)
MODE
TLIC15517-13
FIGURE 2
9-85
o
»
9.0 Functional Description
(Continued)
PAO-7 input latches on the leading (negative) edge of STB,
causing BF to go high (true). On the trailing (positive) edge
of STB the data is latched and the interrupt signal, INTR,
becomes valid indicating to the CPU that new data is available. INTR becomes valid only if the interrupt is enabled,
that is the output data latch for PC2 is set to 1.
• Strobed 1/0
Strobed 1/0 Mode uses the STB, BF and INTR signals to
latch the data and indicate that new data is available for
transfer. Port A is used for the transfer of data when in any
of the Strobed modes. Port B can still be used for Basic 1/0
and the lower 3-bits of port C are now the three handshake
signals for Strobed 1/0. Timing for this mode is shown in the
AC Characteristic Tables.
When the CPU reads port A, address x'OO, the trailing edge
of the RD strobe causes BF and INTR to become inactive,
indicating that the strobed input cycle has been completed.
Initializing the NSC810A for Strobed 1/0 Mode is done by
loading the data shown in Table IV Into the specified register. The registers should be loaded in the order (left to right)
that they appear in Table IV.
• Strobed Output-Active (Mode 2)
During strobed output operations, an external device can
read data from port A using the STB signal. Data is initially
loaded into port A by the CPU writing to I/O address x'OO.
On the trailing edge of WR, INTR is set inactive and BF
becomes valid indicating new data is available for the external device. When the external device is ready to accept the
data in port A it pulses the STB signal. The rising edge of
STB resets BF and activates the INTR signal. INTR becomes valid only if the interrupt is enabled, that is the output
latch for PC2 is set to 1. INTR in this mode indicates a
condition that requires CPU intervention (the output of the
next byte of data).
• Strobed Output-TRI-STATE (Mode 3)
TABLE IV. Mode Definition Register Configurations
Mode
DDR
PortA
MDR
Basic I/O
xxxxxxxO
Strobed Input
DDR
PortC
PortC
Output
Latch
Port bit directions are
determined by the bits of
each port's DDR
xxxxxx01
00000000
xxx011
xxx1xx
Strobed Output xxxxx011
(Active)
11111111
xxx011
xxx1xx
Strobed Output xxxxx111
(TRI-STATE)
11111111
xxx011
xxx1xx
The Strobed Output TRI-STATE Mode and the Strobed Output active (peripheral) bus mode function in a similar manner with one exception. The exception is that the data signals on PAO-7 assume the high impedance state at all
times except when accessed by the STB signal. Strobed
Mode 3 is identical to Strobed Mode 2, except as indicated
above.
• Strobed Input (Mode 1)
During strobed input operations, an external device can load
data into port A with the STB signal. Data is input to the
Example Mode 1 (Strobed Input):
INTR
BF
Results of Action
Reset NSC810A
Load 01 'H into
MDR
H
H
L
L
Load OO'H into
DDRA
H
L
Load 03'H into
DDRC
H
L
Load 04'H into
Port C Bit-Set
Register
H
L
Basic input mode all ports.
Strobed input mode entered; no byte loads to port C
after this step; bit-set and clear commands to INTR
and BF no longer work.
Sets data direction register for port A to input;
data from port A peripheral bus is available
to the CPU if the STB signal is used, other
handshake signals aren't initialized, yet.
Sets data direction register of port C; buffer full
signal works after this step and it is unaffected
by the bit-set and clear registers.
Sets output latch (PC2) to enable INTR; INTR will
latch active whenever STB goes low; INTR can be
disabled by a bit-clear to PC2.·
STB pulses low
L
H
CPU reads Port A
H
L
Action Taken
INITIALIZATION
OPERATION
Data on peripheral bus is latched into port A;
INTR is cleared by a CPU read of port A or a
bit-clear of STB.
CPU gets data from port A; INTR is cleared;
peripheral is signalled to send next byte via
an inactive BF signal. Repeat last two steps until
EaT at which time CPU sends bit-clear to the
output latch (PC2) .
• Port C can be read by the CPU at anytime, allowing polled operation instead of interrupt driven operation.
9-86
9.0 Functional Description (Continued)
Example Mode 2 (Strobed Output-active peripheral bus):
Action Taken
INTR
BF
Reset NSC810A
Load 03'H into
MDR
H
H
L
L
Load FF'H into
DDRA
H
L
Load 03'H into
DDRC
H
L
Load 04'H into
Port C Bit-Set
Register
L
L
H
H
L
L
Results of Action
INITIALIZE
basic input mode all ports.
strobed output mode entered; no byte loads to
port C after this step; bit-set and clear
commands to INTR and BF no longer work.
Sets data direction register for port A to output;
data from port A is available to the peripheral
if the STB signal is used other handshake
signals aren't initialized, yet.
Sets data direction register of port C; buffer
full signal works after this step and it is
unaffected by the bit-set and clear registers
Sets output latch (PC2) to enable INTR;
active INTR indicates that CPU
should send data; INTR becomes inactive
whenever the CPU loads port A; INTR can
be disabled by a bit-clear to STB. *
OPERATION
CPU writes to
PortA
STB pulses low
Data on CPU bus is latched into port A;
INTR is set by the CPU write to port A; active
BF indicates to peripheral that
data is valid; Peripheral gets data from port A;
INTR is reset active; The active INTR signals the
CPU to send the next by1e. Repeat last two
steps until EOT at which time CPU sends
bit-clear to the output latch (PC2).
'Port C can be read by the CPU at any time, allowing polled operation instead of interrupt driven operation.
In addition to its timing function, STB enables port A outputs
to active logic levels. This Mode 3 operation allows other
data sources, in addition to the NSC810A, to access the
peripheral bus.
• Handshaking Signals
STB (Strobe) is an active low input from the peripheral device, signalling a data transfer. The NSC810A latches
data on the rising edge of STB if the port bit is an input
and the peripheral should latch data on the rising
edge of STB if the port bit is an output.
BF (Buffer Full) is a high active output from the NSC810A.
For input port bits, it indicates that new data has been
received from the peripheral. For output port bits, it
indicates that new data is available for the peripheral.
In the Strobed mode of operation, the lower 3-bits of port C
transmit/receive the handshake signals (PCO = INTR,
PC1 = BF, PC2 = STB).
INTR (Strobe Mode Interrupt) is an active-low interrupt from
the NSC810A to the CPU. In strobed input mode, the
CPU reads the valid data at port A to clear the interrupt. In strobed output mode, the CPU clears the interrupt by writing data to port A.
The INTR output can be enabled or disabled, thus
giving it the ability to control strobed data transfer. It is
enabled or disabled, respectively, by setting or clearing bit 2 of the port C output data latch (STB).
PC2 is always an input during strobed mode of operation, its output data latch is not needed. Therefore,
during strobed mode of operation it is internally gated
with the interrupt signal to generate the INTR output.
Reset clears this bit to zero, so it must be set to one to
enable the INTR pin for strobed operation.
Once the strobed mode of operation is programmed,
the only way to change the output data latch of PC2 is
by using the Bit-Set and Clear registers. The port C
by1e write command will not alter the output data latch
of PC2 during the strobed mode of operation.
Note: In either input or output mode the BF may be
cleared by rewriting the MDR.
9.4 TIMERS
The NSC810A has two timers. These are independently
programmable, 16-bit binary down-counters. Full count is
reached at n + 1, where n is the count loaded into the modulus registers. Timer outputs provide six distinct modes of
operation and allow the CPU to check the present count at
any1ime. Each timer has an independent clock input and
output. Start and stop words from the CPU can individually
start and stop the timers in any of the modes. A common
gate signal can start and stop both timers in three of the six
modes. Timer 0 has three possible input clock prescalers
-;- 1, -;- 2 and -;- 64. Timer 1 has two possible input clock
prescalers -;- 1 and -;- 2.
Primary components of one timer are shown in Figure 3 .
The timer mode register is a read/write register providing
9-87
•
<
o
.....
CO
o(J)
z
,-------------------------------------------------------------~
9.0 Functional Description
(Continued)
INTCLK and can be read without stopping the timers (see
single/ double precision).
the primary characterization of the timer output. The start!
stop logic and prescaler block divides the clock input by the
prescale factor, passing the output (INTCLK) to the binary
down-counter. This block also gates the clock input signal
(TIN) with the timer gate signal (TG). The timer block loads
the modulus from the modulus register and uses (INTCLK)
to count to zero. It loads the current count into the read
buffer block where the CPU can access it at anytime. This
timer block also indicates to the output control logic when
the modulus is loaded (or reloaded) and when the count
reaches O. The output control logic block drives the output
pins according to the timer mode register and the timer
block. The output of the timer block (Figure 3) (terminal
count) is related to the input TIN by:
.
terminal count
=
[
• Timer Mode Register
The timer mode register determines the operating configuration and the active input and output signal levels. Each
timer has its own timer mode register, allowing independent
operation.
The timer mode register (TMR) may be written or read at
any time; however, to assure accurate timing it is important
to modify the mode only when the timer is stopped (see
Timer Programming). The timer mode is selected from one
of six modes by TMR bits 0, 1, and 2 (see Table V). Bits 3
and 4 select the prescale value if the prescaler is to be
used. Bits 5, 6 and 7 select the modulus width (8- or 16bits), gate input polarity, and timer output polarity (activehigh or low), respectively. The bit functions of the TMR are
illustrated in Figure 4.
TIN
p 2(m
+
1)1
where:
TIN = the input frequency
p
=
TMR
the programmed prescale
7 6 5 4 3 2 ,
0
~TlMINGMOOE
~
ll§~
m = the modulus
PRESCALE VALUE
This relationship can be seen directly (TOUT) in Mode 5
(square wave) as it is not masked by the subsequent output
logic.
SINGLE/DOUBLE PRECISION
GATE INPUT POLARITY
TIMER OUTPUT POLARITY
9.4.1 Registers
TLIC/5517-15
FIGURE 4. Timer Mode Register
There are five control registers for each timer. These are
shown in the second group of Table I. They determine all
timer functions and outputs.
TABLE V. Mode Selection
Bit
• Modulus Registers and Read Buffer
There are two modulus registers per timer (low byte, high
byte). These are write only registers, and the two 8-bit values loaded by the CPU are combined into a 16-bit modulus
for the timer's down counter.
When the CPU reads from the modulus register addresses,
it actually accesses the read buffers. These contain the low
and high byte of the decremented modulus. This count is
constantly updated by the timer block on the falling edge of
2
1
0
-
Timer Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
Timer Stopped and Reset
Event Counter
Event Timer (Stopwatch)
Event Timer (Resetting)
One Shot
Square Wave
Pulse Generator
Timer Stopped and Reset
-
READ BUFFER
CONTROL
TIN(CLKI
TG(GATEI
INTClK
'6
TIMER
WR-+
('61
TERMINAL
COUNT
OUTPUT
CONTROL
LOGIC
TOUT
CONTROL
FIGURE 3. Timer Internal Block Diagram (One of Two Timers)
9-88
TLiC/5517-,4
9.0 Functional Description (Continued)
-
Timer Prescaler
-
There is a prescale function associated with each timer. It
serves as an additional divisor to lengthen the counts for
each timer circuit. The value of the divisor is fixed and selectable in each TMR, as shown below.
TMRO
Bits
4
3
a
a
a
The output for T1 is multiplexed with port C, bit 5. (Similarly
T11N is multiplexed with port C, bit 4.) When any timer mode
other than a or 7 is specified for T1, or when mode 2, mode
3, or mode 4 is specified for TO, the three port C pins, bit 3,
bit 4, and bit 5, become TG, T11N and T10UT, respectively.
Prescale
+1
+2
+64
• Start and Stop Registers
This is the software start and stop for the timers. There is
one start and one stop register for each timer. Writing any
data to the start register of a timer starts that timer or transfers start and stop control to TG (in the gated modes 2, 3
and 4). Writing any data to the stop register stops the timer
and removes start and stop control from TG (in the gated
modes 2, 3 and 4). Restarting the timers causes the modulus to be reloaded for all gated timer modes (2, 3 and 4).
The +64 is not available on timer 1; TMR1 bit 4 is a "don't
care,"
Bits
TMR1
4
3
Prescale
x
x
a
+1
+2
The timer prescale divides the input clock (TIN) and provides the output (INTCLK) to the drive the timer block (Figure 3).
-
During software restarts of the timers (write to the STOP
register and then to the START register) the modulus will be
reloaded only if the internal clock signal (INTCLK) is in the
high level or makes at least one transition to the high level
between the time that the STOP and START registers are
written. If INTCLK doesn't meet one of these criteria then
the modulus will not be reloaded and the timer will continue
to count down from where it was stopped.·
Single/Double Precision
Bit 5 of the TMR determines whether a single or double byte
can be accurately read from the read buffer. This option
does not affect the use of the modulus registers by the timer
block (i.e., the modulus used is always a double byte regardless of the precision mode selected).
Since it is difficult, if not impossible, to know the level of
INTCLK in non-gated modes the recommended practice for
restart operation is to reload the modulus after stopping the
timer using the 4 step programming procedure in the Timer
Programming section of this datasheet. In gated modes
INTCLK always stops high.
The read buffer keeps track of the count and is constantly
being updated by the timer block. In order to allow the CPU
to read the read buffer, the NSC810A must discontinue updates to this buffer during the read. The precision bit determines whether one or two bytes in the read buffer will be
frozen during the read process. In double precision mode,
the NSC810A freezes high and low bytes in the read buffer
for two consecutive read cycles. In the single precision
mode, the NSC810A freezes the read buffer for only one
read cycle. Read accesses should be done as follows.
'NOTE: INTCLK is coupled via the prescaler to TIN and reacts to the TIN
clock input regardless of whether the timer is started or stopped.
-
Start/Stop Timing
Figure 5 shows the relationships between the WR signal
(start register), TIN and INTCLK for both the non-gated and
gated modes. The TG signal is only sampled during the positive half of the TIN cycle. This means that when the gated
modes are used the internal clock (INTCLK) is never
stopped in the low state. Hence, when TG goes active high
INTCLK is restarted on the next high-to-Iow transition of
TIN. When TG goes inactive low INTCLK will stop as soon
as TIN is high.
When the TMR bit 5 is:
0- (double byte) read or write the low byte first, then
the high byte to maintain proper read/write communications.
1- (single byte) In this mode either the high or low byte
of the count can be read at any given instant but
not both bytes consecutively. Always write the low
byte first, then the high byte to load the modulus.
9.4.2 Timer Pins
The following example illustrates this point. If the read buffer
had a value of 0200 when the low byte was read and the
down-counter decremented to 01FF before the high byte
was read, then in the double precision mode the CPU would
have read 00 and 02, respectively. In the single precision
mode the CPU would have read 00 and 01.
TIN, TOUT, and TG
a
Timer has dedicated pins for its clock, TOIN, and its output, TOOUT. Timer 1 must borrow its input and output pins
from port C. This is accomplished by writing to the TMR for
timer 1. If mode 1, 2, 3, 4, 5 or 6 is specified in TMR1, the
pins from port C (PC3, PC4 and PC5) are automatically
made available to the timer(s) for gating (TG), T11N and
T10UT, respectively. These pins are also taken from port C
any time timer a is in mode 2, 3, 4, so that it has a TG pin. In
order to change pins PC3, PC4 and PC5 back to their original configuration as Basic I/O, the timer mode registers
must be reset by selecting mode a or 7.
NOTE: In the double precision mode, the high byte should be read immediately after the low byte. Do not access any other registers or unused
address locations between the reads.
-
Timer Output Polarity
Like the gating function, the polarity of the output signal is
programmable via bit 7 of the TMR. A zero will cause an
active-low output; a one will generate an active-high output.
Gate Input Polarity
In modes 2, 3 and 4, the TG input is the common hardware
control for starting and stopping the timers.
The polarity of the gate input may be selected by the contents of bit 6 of the TMR. If bit 6 equals 0, the gate signal will
be active-high or positive edge for mode 4; if bit 6 equals 1,
the gate polarity will be active-low or negative edge for
mode 4. Modes 2 and 3 are level sensitive. Mode 4 is edge
sensitive.
TG (PC3), the timer gate, is used for hardware control to
start/stop (or trigger) the timers. The timer gate may be
used individually by either timer or simultaneously by both
timers.
For modes 2 and 3, the timer starts on the gate-active transition assuming the start address was previously written. If
9-89
z
tJ)
oco
....
~
NSC810A
CD
o
."
C
~
n
o·
~
!.
TIN
cCD
en
...n
is·
-
Wii
o·
~
1;>
ADDRESS
~
'"
c:
CD
.e.
INTCLKFOR
NON-GATED
MODES (1, 5, 6)
CD
cO
o
TO
(TMAS.O)
,
INTCLKFOR
GMED MODES 12, 3, 4)
TLlC/5517-16
FIGURE 5. Start/Stop Timing
Note: Diagonal lines indicate interval of invalid data.
twsp-WR set-up for stopping timer 150 ns.
For mode 4 (one shot), only start-timing applies.
tGs-r-TG (gate) set-up for starting timer 100 ns.
tws-r-WR set-up for starting timer 150 ns.
tGSp-TG (gate) set-up for stopping timer 100 ns.
CD
ONE CYCLE
(:)
INltLK
."
C
:::l
-
Wi! - - - - - - - . . . . ,
()
START REGISTER
O·
~----------------------------------------+------------,
READ BUFFER
:::l
~
C
(ACTI~~~~~ --------------------------"'1:=1
TLlC/5517-17
CD
til
()
~.
FIGURE 6a. Event Counter Mode (Mode 1)
"C
O·
:::l
INltLK
oo
;a.
Viii - - - -...
:r
c:
START REGISTER
<
OUTPUT
(ACTIVE-LOW)
TLiC/5517-20
FIGURE Sd. One Shot (Mode 4)
::l
oo
3-
:it:
CD
S
INTCLK
'"cO
V)
Wii
START REGISTER
OUTPUT
(ACTIVE LOW)
TLiC/5517-21
FIGURE Se. Square Wave (Mode 5)
!----r-
ONE CYCLE
INTClK
Wii
START REGISTER
OUTPUT
{ACTIVE LOW}
TLiC/5517-22
FIGURE Sf. Pulse Generator (Mode S)
"O~8~SN
iii
~
.,...
co
U
t/)
Z
9.0 Functional Description
(Continued)
• One Shot Mode (mode 4, TMR bits = 100)
2. Write timer mode register again, this time loading it for
your requirements.
In this gated mode, the timer holds the modulus count until
the active gate edge (see Figure 6d). The output immediately becomes valid and remains valid as the counter decrements. The gating signal may go inactive without affecting
the count. If TG (the gate) becomes inactive and returns
active prior to the terminal count, the modulus will be reloaded, retriggering the one shot period. When the timer reaches the terminal count, the output becomes inactive (see
NOTE). The gate, in this mode, is edge sensitive; the active
edge is defined by the TMR.
3. Write the modulus values, low byte first, high byte
second.
4. Start the timers.
The timer read buffer is only updated when the internal timer clock (INTCLK) makes a negative-going transition. Therefore, enough input clock cycles (TIN) must occur to cause a
transition of INTCLK given the programmed pre-scaler. After the first transition, the new modulus will be loaded into
the read buffer and it can then be read by the CPU.
NOTE: The one shot cannot be retriggered during its last internal count
(INTCLK) regardless of prescaler selected. Therefore, using the divide by 1 prescaler, it cannot be retriggered during the last clock
(TIN), using the divide by 2 prescaler during the last two clocks (TIN)
and using the divide by 64 prescaler during the last 64 clocks (TIN).
• Square Wave Mode (mode 5, TMR bits
To guarantee the integrity of the data during a read operation, updates to the timer read buffer are blocked out. If an
update is blocked out due to a read, the read buffer will not
be updated until the next active transition of INTCLK. Thus,
it would appear as if a count was skipped between reads.
For example, if the output latches were FF when a block out
(read) occurred, the next update could occur at FD, thereby
giving an appearance that the count FE was skipped. In
actuality the correct number of clocks has occurred for the
read buffer to hold FD.
= 101)
In this non-gated mode, the output will go active as soon as
the timer is started. The counter decrements for each clock
period (INTCLK) and complements its output when zero is
reached (see Figure 6e). The modulus is then reloaded and
counting continues. Assuming a regular clock input, the output will then be a square wave with a period equal to twice
the prescale value times the value loaded into the modulus
+ 1 (see equation Timer section intro.). Therefore, varying
the modulus will vary the period of the square wave.
Writing the modulus value when the timer is running does
not update the timer immediately. The new value written will
get into the timer when the timer reaches its terminal count
and reloads its value. If the timer is stopped and a modulus
is written the new modulus value will get into the timer when
the internal clock is high during the modulus write or on the
next low to high internal clock transition. The next time the
timer reaches its terminal count it will load the new modulus
into the timer. One way to guarantee the new modulus will
get into the timer is to follow steps 1 through 4. Although
this procedure guarantees that the data will get into the timer you will not be able to read it back until you get a negative-going transition on the internal clock.
• Pulse Generator (mode 6, TMR bits = 110)
In this non-gated mode, the counter decrements for each
period of INTCLK (see Figure 61). When the terminal count
is reached the output becomes valid for % of the TIN clock
width for a prescale of + 1, for one full TIN clock width for a
prescale of + 2 and for 32 TIN clock widths for a pre scale of
+ 64. The modulus is then reloaded and the sequence is
repeated. Varying the prescale and modulus varies the frequency of the pulse.
Rewriting modulus does not reset the prescaler. The only
way to reset the prescaler is to write the mode register and
have the internal clock signal be high for some period between the write of the mode register and the start of the
timer. Once again, steps 1 through 4 will reset the prescaler.
9.4.4 Timer Programming
The following is the proper sequence to program the timer
and should always be used:
1. Write timer mode register selecting mode 0 or 7. This
stops the timer, resets the prescaler, and sets internal
clock high.
9-94
z
en
10.0 NSC810A/883 MIL-STD-883 Class B Screening
National Semiconductor offers the NSCS10AD and
NSCS10AE with full class B screening per MIL-STD-SS3 for
Military/ Aerospace programs requiring high reliability. In addition, this screening is available for all of the key NSCSOO
peripheral devices.
(')
Q)
......
Electrical testing is performed in accordance with
RETSS10AX, which tests or guarantees all of the electrical
performance characteristics of the NSCS10A data sheet. A
copy of the current revision of RETSS10AX is available
upon request. The following table is the MIL-STD-S83 flow
as of the date of publication.
Test
MIL-STD-883 Method/Condition
Requirement
Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Fine Leak
Gross Leak
Burn-In
2010 B
100S C 24 Hrs. @ + 150·C
1010Cl0Cycies -65·C/ +150·C
2001 E 30,000 G's, Yl Axis
1014AorB
1014C
1015160Hrs.@ +125·C(using
burn-in circuits shown below)
+ 25·C DC per RETS81 OAX
5% Max
+ 125·C AC and DC per RETS81 OAX
-55·CACand DC per RETS810AX
+25·C AC per RETSS10AX
5005
5056
2009
100%
100%
100%
100%
100%
100%
100%
Final Electrical
PDA
QA Acceptance
Quality Conformance
External Visual
11.0 Burn-In Circuit
51
CLDCK3
51
CLDCK 2
Input Clocks
5.5 Vac
10
40 I-"VVI......
39
38
37
36
35
34 1-".,..,........
33L...JOCAA_
-r-r5...1 INri
10
11
12
13
14
15
16
17
18
19
20
100%
100%
100%
Sample per
Method 5005
100%
12.0 Timing Diagram
5242HR
NSC810AD/883B (Dual-In-Line)
CLOCK 1
100%
av
4.5V
CLOCK 3
3".
-+-.....
_..,
DV-
32
31
30 1-".,..,........
29
28
27
261-"VVI......
251-"VVI......
241-"VVI......
23 1-".,..,.........
22 .......,..,.........
21 1-".,..,....-41
TL/C/5517-24
Note 1: All resistors ±5%,
erating life circuit.
V. watt unless otherwise deSignated, 12S'C op·
Note 2: E package burn·in circuit 5244HR is functionally identical to the 0
package.
Note 3: All resistors 2.7 kO unless marked otherwise.
Note 4: All clocks OV to 4.5V.
Note 5: Device to be cooled down under power after burn-in.
":"
TL/C/5517-23
9-95
~
13.0 Ordering Information
NSC810A X
X
11
X
X
r
"";obm"s,_,,,
A + =A+
1883= MIL·STD·883 Screening (Note 1)
I = Industrial Temperature (- 40'C to + 85'C)
M Military Temperature (- 55'C to + 125'C)
No Designation = Commercial Temperature (O'C to 70'C)
=
=
1-1 1 MHz Clock Output
' - - - - - - - - - ; -3=2.5 MHz Clock Output
4 = 4 MHz Clock Output
1-
L...._ _ _ _ _ _ _ _-/
0= Ceramic Package
N = Plastic Package
E = Ceramic Leadless Chip Carrier (LCC)
V = Plastic Leaded Chip Carrier (PCC)
TUC/5517-25
Note 1: Do not specify a temperature option; all parts are screened to military temperature.
14.0 Reliability Information
Gate Count
Transistor Count
4000
14,000
9·96
z
en
oQC)
~National
.....
Co)
~ Semiconductor
microCMOS
NSC831 Parallel 1/0
General Description
Features
The NSC831 is an I/O device which is fabricated using
microCMOS silicon gate technology, functioning as an input/output peripheral interface device. It consists of 20 programmable input/output bits arranged as three separate
ports, with each bit individually definable as an input or output. The port bits can be set or cleared individually and can
be written to or read from in bytes. Several types of strobed
mode operations are available through Port A.
II Three programmable I/O ports
III Single 5V Power Supply
Very low power consumption
Fully static operation
III Single-instruction I/O bit operations
• Directly compatible with NSC800 family
• Strobed modes available on Port A
1:11
EI
For military applications the NSC831 is available with class
B screening in accordance with methods 5004 of MIL-STD883.
Microcomputer Family Block Diagram
~
ADD·AD7
INTR
RSTA, B. C
NMI
AB·A15
INTA
so
51
RFSH
BRED
ftij
NSCBDD
CPU
WR
ALE
BACK
101M
WAIT
PS
RESET OUT
Vee
RESET IN
PORT A
B BITS
"*
A13
A12
CSii
CSf
NSCB31
1/0
PORT B
B BITS
ftij
WR
ALE
PORT C
4 BITS
RESET
TL/C/5594-1
9-97
~
Cf)
r-----------------------------------------------------------------------------,
co
~
Z
Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS
8.0 FUNCTIONAL DESCRIPTION
2.0 OPERATING RANGE
8.1 Block Diagram
8.2 1/0 Ports
3.0 DC ELECTRICAL CHARACTERISTICS
8.3 Registers
4.0 AC ELECTRICAL CHARACTERISTICS
8.4 Modes
9.0 NSC8311NSC883B MIL·STD-883/CLASS B
SCREENING
5.0 TIMING WAVEFORMS
6.0 PIN DESCRIPTIONS
10.0 BURN·IN CIRCUIT
6.1 Input Signals
11.0 TIMING DIAGRAM
6.2 Input/Output Signals
12.0 ORDERING INFORMATION
7.0 CONNECTION DIAGRAMS
13.0 RELIABILITY INFORMATION
9·98
1.0 Absolute Maximum Ratings
2.0 Operating Range Vee =
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
-65'Cto + 150'C
Voltage at Any Pin With
Respect to Ground
-0.3V to Vee + 0.3V
7V
Vee
Lead Temp. (Soldering, 10 seconds)
300'C
Power Dissipation
1W
NSC831-1:
O'C
-40'C
NSC831·3: -40'C
- 55'C
NSC831·4:
O'C
-40'C
-55'C
to
to
to
to
to
to
to
z
en
oCO
5V ±10%
....Co:I
+70'C
+85'C
+ 85'C
+ 125'C
+70'C
+85'C
+ 125'G
Note: Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed Continuous operation at these limits is not intended; operation
should be limited to those conditions specified under DC
Electrical Characteristics.
3.0 DC Electrical Characteristics Vee =
Symbol
Parameter
5V ± 10%, GND = OV, unless otherwise specified
Max
Units
Logical 1 Input Voltage
0.8 Vee
Vee
V
VIL
Logical 0 Input Voltage
0
0.2 Vee
V
Logical 1 Output Voltage
VOL
Logical 0 Output Voltage
Min
Typ
VIH
VOH
Test Conditions
IOH = -1.0mA
2.4
V
lOUT = -10 JJ-A
4.0V
V
IOL = 2mA
0
0.4
V
lOUT = 10 JJ-A
0
0.1
V
JJ-A
IlL
Input Leakage Current
0,;; VIN';; Vee
-10.0
10.0
IOL
Output Leakage Current
0,;; VIN';; Vee
-10.0
10.0
JJ-A
lee
Active Supply Current
lOUT = 0, twey = 750 ns
15
20
mA
10
Quiescent Current
RESET =0, RD = 1, WR = 1,
ALE = X, VIN = 0, or VIN = Vee
No Input Switching, TA = 25'C
10
100
JJ-A
GIN
Input Capacitance
4
7
pF
COUT
Output Capacitance
6
10
pF
5
Power Supply Voltage
(Note 1)
V
2.4
6
Vee
Note 1: Operation at lower power supply voltages will reduce the maximum operating speed. Operation at voltages other than 5V ± 10% Is guaranteed by design,
not tested.
ICC vs. SPEED
10
..1.~
....
/~
.s
15
a::
a::
8
~
=>
'"
~
5
'/
V
.V
4500
3000
1500
1000
750
3
4
twev (ns)
0
1
2
NSC 800 CLOCK SPEED' (MHz)
TL/C/5594-2
'When NSe831 is used with NScaOO
9-99
4.0 AC Electrical Characteristics Vcc =
Symbol
5V ± 10%, GND = OV
Test
Conditions
Parameter
NSC831-1
NSC831-3
NSC831-4
Units
Min
Max
Min
Max
Min
400
Max
250
tACC
Access Time from ALE
tAH
ADO-AD7, CE, 101M Hold Time
100
60
30
ns
tALE
ALE Strobe Width (High)
200
130
75
ns
tARW
ALE to RD or WR Strobe
150
120
75
ns
tAS
ADO-AD7, CE, 101M Setup Time
100
45
40
ns
tOH
Data Hold Time
150
90
40
ns
too
Port Data Output Valid
tos
Data Setup Time
tpE
Peripheral Bus Enable
tpH
Peripheral Data Hold Time
150
tps
Peripheral Data Setup Time
100
tpz
Peripheral Bus Disable (TRI-STATE®)
150
150
150
ns
tR8
RD to BF Output
300
300
300
ns
tRO
Read Strobe Width
tROD
Data Bus Disable
tRI
RD to INTR Output
CL = 150 pF
1000
350
100
320
80
320
0
200
125
220
0
0
100
320
75
300
ns
ns
50
320
ns
ns
200
100
75
400
300
50
ns
ns
ns
75
ns
300
ns
300
ns
tRWA
RD or WR to Next ALE
Isa
STB to BF Valid
tSH
Peripheral Data Hold With Respect to STB
lSI
STB to INTR Output
tss
Peripheral Data Setup With Respect to STB
100
75
50
Isw
STBWidth
400
320
220
twa
WR to BF Output
tWI
WR to INTR Output
tWR
WR Strobe Width
400
320
220
ns
twCY
Width of Machine Cycle
3000
1200
750
ns
Nole: Test conditions: twCY
~
125
150
300
125
300
ns
300
300
300
320
ns
100
300
340
ns
ns
ns
300
ns
300
ns
3000 ns for NSC831-1, 1200 ns for NSC831-3, 750 ns for NSC831-4
AC TESTING INPUT/OUTPUT WAVEFORM
===x:
45
100
300
0.8 Vee
0.2 Vee
0.8 Vee
0.2 Vee
AC TESTING LOAD CIRCUIT
x=
I
TLlC/5594-3
DEVICE
UNDER
TEST
1'100 PF
TL/C/5594-4
9-100
z
en
oCXI
5.0 Timing Waveforms
...
Co)
Read Cycle (Read from Port)
101M
CE
AD (0-71
ALE
no
PERIPHERAL
(PDRT) BUS
TLlC/5594-5
Note: Diagonal lines indicate interval of invalid data.
Write Cycle (Write to Port)
TLlC/5594-6
Note: Diagonal lines indicate interval of invalid data.
9-101
~
CO)
B
,-----------------------------------------------------------------------------------------------,
5.0 Timing Waveforms
(Continued)
U)
Z
Strobed Mode Input
PERIPHERAL
(PORT A) BUS
BF
INTR
101M
CE
ALE
PORT A
-
AD (D-7)
TL/C/5594-7
Note: Diagonal lines indicate interval of invalid data.
Strobed Mode Output
IOJM~
'I11I//////II/
CE
B<
AD (0-7)
PDRTAADDR
ALE
~OATAIN
_
I':~:---------------------
\
BF
m
ACTIVE (MDDE 2)
PORTA BUS
-ID0:to-+----+---_
X
DlD DATA
{
_
!!!-~T~M~E:!L
_____ _
-
-
NEW DATA
lPEt
------'--{
TLlC/5594-B
Note: Diagonal lines indicate interval of invalid data.
9-102
r--------------------------------------------------------------------------, Z
en
6.0 Pin Descriptions
o
7.0 Connection Diagrams
(1)
The following describes the function of all NSC831 input/
output pins. Some of these descriptions reference internal
circuits.
c.)
......
Dual-In-Line Package
40
39
38
37
36
PAD
6.1 INPUT SIGNALS
Master Reset (RESET): An active-high input on the RESET
pin initializes the chip causing the three 1/0 ports (A, Band
C) to revert to the input mode. The three ports, the three
data direction registers and the mode definition register are
reset to low (0).
RESET
Chip Enable (CEo, CE1): The CE inputs must be active at
the falling edge of ALE. At ALE time, the CE inputs are
latched to provide access to the NSC831.
CSO
Vee
3S PA5
34 PA6
CS1
jjjj
33 PA7
WR
10
NSC831
ALE 11
12
ADO
ADl 13
Read (RD): when the RD input is an active low, data is read
from the ADO-AD? bus.
:~: ::
Write (WR): When the CE inputs are active an active low
WR input causes the selected output port to be written with
the data from the ADO-AD? bus.
Address Latch Enable (ALE): The trailing edge (high to
low transition) of the ALE input signal latches the addressl
data present on the ADO-AD? bus, plus the input control
signals on CEo and CE1.
Power (Vecl: 5V power supply.
Ground (Vss): Ground reference.
Vee
PAl
PA2
PA3
PA4
AD4
ADS
AD6
AD7
V
ss
17
18
19
20
32
31
30
29
28
27
26
25
24
23
PCoIINTR
PC1/BF
PC2/STB
PC3
PBo
PBl
PB2
PB3
PB4
PBS
22 PB6
21 PB7
TL/C/5594-9
Top View
*Tie pins 2, 3, and 4 to either Vee or Vss.
6.2 INPUT/OUTPUT SIGNALS
Order Number NSC831D or N
See NS Package Number D40C or N40A
Bidirectional Address/Data Bus ADO-AD7: The lower 8
bits of the 1/0 address are applied to these pins, and
latched by the trailing edge of ALE. During read operations,
8 bits are present on these pins, and are read when RD is
low. During an 1/0 write cycle, Port A, B, or C is written with
the data present on this bus at the trailing edge of the WR
strobe.
Leadless Chip Carrier
RESET
PAD NC Vee PAl PA2 PA3 PA4
/
Ports A, B, C (PAO-PA7, PBO-PB7, PCO-PC3): These are
general purpose 1/0 pins. Their input/output direction is determined by the contents of the Data Direction Register
(DDRs).
PAS
PA6
CSO
Vee
CS1
PA7
PCOJlNTR
PClI8F
NC
Ali
WR
NC
ALE
ADO
ADl
AD2
AD3
PC2/STB
PC3
PBO
PBl
PB2
AD4 AD5 AD6 AD7 Vss NC PB7 PB6 PBS PB4 PB3
NC = NO CONNECT
TL/C/5594-10
Top View
Order Number NSC831E
See NS Package Number E44A
9-103
,..
CO)
r-------------------------------------------------------------------------------------~
co
8.0 Functional Description
U)
Refer to Figure 1 for a detailed block diagram of the
NSC831, while reading the following paragraphs.
Input/Output (1/0): The 110 of the NSC831 contains three
sets called Ports. There are two ports (A and B) which contain 8 bits each and one port (Port C) which has 4 bits. Any
bit or combination of bits in a port may be addressed with
Set or Clear commands. A port can also be addressed as an
U
Z
8-bit word (4 bits for Port C). When reading Port C, bits 4-7
will be read as ones. All ports share common functions of
Read, Write, Bit-Set and Bit-Clear. Additionally, Port A is
programmable for strobed (handshake mode input or output. Port C has a programmable second function for each
bit associated with strobed modes. Table I defines the ad·
dress location of the ports and control registers.
8.1 BLOCK DIAGRAM
CONTROL
LOGIC
(1.33·391
PORT A
PAO-PA7
(Z-41
iiiI.~
A8-AID • •
(Zl-Z8)
ADDRESS
8UFFERS
PORT 8
PBD-PB7
(lZ-191
ADD-AD7
4111i1iliil~
(40)
Vcc~
ADDRESSI
DATA
BUFFERS
AND
LATCHES
(29-32)
PORT C
PCO-PC3
HANDSHAKE
INTERNAL
DATA
BUS
GND~
TL/C/5594-11
Note: Applicable pinout for 40 pin dual-in·line package within parentheses.
FIGURE 1
9-104
8.0 Functional Description
z
o
(f)
(Continued)
IX)
The address assignment of the MDR is xxx00111 as shown
in Table I. The upper 3 "don't care" bits are determined by
the users decode logic (chip enable address). Table II specifies the data that must be loaded into the MDR to select the
mode.
• Data Direction Registers (DDR)
8.2 1/0 PORTS
There are three 1/0 ports (labeled A, Band C) on the
NSC831. Ports A and Bare 8-bits wide; port C is 4-bits wide.
These ports transfer data between the CPU bus and the
peripheral bus and vice versa. The way in which these transfers are handled depends upon the currently programmed
operating mode.
Each port has a DDR that determines whether an individual
port bit will be an input or an output. If DDR for the port bit is
set to a 1, then that port bit is an output. If its DDR is reset to
a 0, then it is an input. The DDR bits cannot be individually
written to; the entire DDR register is affected by a write to
the DDR. Thus, all data bits written must be consistent for
all desired port bit directions.
The NSC831 can be programmed to operate in four different modes. One of these modes (Basic 1/0) allows direct
transfer of 1/0 data without any handshaking between the
NSC831 and the peripheral. The other three modes
(Strobed 1/0) provide for timed transfers of 1/0 data with
handshaking between the NSC831 and the peripheral.
Determination of the NSCB31 port's mode, data direction
and data is done by five registers which are under program
control. The Mode Definition Register determines in which
of the four 1/0 modes the chip will operate. Another register
(Data Direction Register) establishes the data direction for
each bit in that port. The Data Register holds data to be
transferred or that which was received. The final two registers per port allow individual data register bits to be cleared
(Bit-Clear Register) or data register bits to be set (Bit-Set
Register).
TABLE I. 1/0 and Timer Address Designations
8-Bit Address Field
Designation
R (Read)
Bits
1/0 Port, Timer, etc. W(Write)
7 6 5 4 3 2 1 0
x
x
x
x
x
x
x
x
x
Operation during Strobed 1/0 utilizes two of the port C pins
for handshaking and one port C pin to interrupt the CPU.
x
x
x
x
x
x
x
x
x
x x
8.3 REGISTERS
As indicated in the overview, programmable registers control the flow of data through the ports. Table I shows the
registers of the NSC831. All registers affecting 1/0 transfers
are in the first grouping of this table.
x x
x x
x x
x x
x x
• Mode Definition Register (MDR)
The MDR determines the operating mode for port A and
whether or not the lower 3-bits of port C will be used for
handshaking (Strobed 1/0). Port B always transfers data via
the Basic 1/0 mode, regardless of how the MDR is programmed.
x
x
x
x
x
x
x
x
x
x
x
x
x x
x x
x x
x x
x x
x x
x x
x x
x x
x x x x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
= don't care
LB
~
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PortA (Data)
Port B (Data)
Port C (Data)
Not Used
DDR - PortA
DDR- Port B
DDR- PortC
Mode Definition Reg.
Port A - Bit-Clear
Port B - Bit-Clear
Port C - Bit-Clear
Not Used
Port A - Bit-Set
Port B - Bit-Set
Port C - Bit-Set
Not Used
R/W
R/W
R/W
**
W
W
W
W
W
W
W
"
W
W
W
'*
low-order byte
HB ~ high-order byte
The four modes are as follows:
" A write accesses the modulus register, a read the read buffer.
"'" A read from an unused location reads invalid data, a write does not affect
any operation of NSC831.
Mode O-Basic 1/0 (Input or Output)
Mode 1-Strobed Mode Input
Mode 2-Strobed Mode Output (Active Peripheral Bus)
TABLE II. Mode Definition Register Bit Assignments
Mode 3-Strobed Mode Output (TRI-STATE Peripheral
Bus)
Mode
0
1
2
3
9-105
Bit
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
0
1
1
0
1
1
1
x
x
x
C.:I
.....
-r-----------------------------------------~
CO)
ClCI
~
Z
8.0 Functional Description (Continued)
Any write or read to the port bits contradicting the direction
established by the DDR will not affect the port bits output or
input. However, a write to a port bit, defined as an input, will
modify the output latch and a read to a port bit, defined as
an output, will read this output latch. See Figure 2.
TABLE III. Bit-Set and Clear Examples
Operation
Port B
• Data Registers
These registers contain the actual data being transferred
between the CPU and the peripheral. In Basic I/O, data
presented by the peripheral (read cycle) will be latched on
the falling edge of RD. Data presented by the CPU (write
cycle) will be valid after the rising edge of WR (see AC characteristics for exact timing).
During Strobed I/O, data presented by the peripheral must
be valid on the rising edge of STB. Data received by the
peripheral will be valid on the rising edge of STB. Data
latched by the port on the rising edge of STB will be preserved until the next CPU read or STB signal.
• Bit Set-Clear Registers
The I/O features of the RAM-I/O-timer allow modification of
a single bit or several bits of a port with the Bit-Set and BitClear commands. The address selected indicates whether a
Bit-Set or Clear will take place. The incoming data on the
address/data bus is latched at the trailing edge of the WR
strobe and is treated as a mask. All bits containing 1s will
cause the indicated operation to be performed on the corresponding port bit. All bits of the mask with Os cause the
corresponding port bits to remain unchanged. Three sample
operations are shown in Table III using port B as an example.
INTERNAL
DATA BUS
SetB7
CiearB2
andBO
SetB4,B3
and B1
Address
xxx01101
xxx01001
xxx01101
Data
10000000
00000101
00011010
Port Pins
Prior State
Next State
00001111
10001111
10001111
10001010
10001010
10011010
8.4 MODES
Two data transfer modes are implemented: Basic I/O and
Strobed I/O. Strobed I/O can be further subdivided into
three categories: Strobed Input, Strobed Output (active peripheral bus) and Strobed Output (TRI-STATE peripheral
bus). The following descriptions detail the functions of these
categories.
• Basic 1/0
Basic I/O mode uses the RD and WR CPU bus signals to
latch data at the peripheral bus. This mode is the permanent
mode of operation for ports Band C. Port A is in this mode if
the MDR is set to mode O. Read and write byte operations
and bit operations can be done in Basic I/O. Timing for
these modes is shown in the AC Characteristics Table and
described with the data register definitions.
I
When the NSCB31 is reset, all registers are cleared to zero.
This results in the basic mode of operation being selected,
all port bits are made inputs and the output latch for each
port bit is cleared to zero. The NSCB31, at this pOint, can
read data from any peripheral port without further set-up. If
outputs are desired, the CPU merely has to program the
appropriate DDR and then send data to the data ports.
WR(SET)
MODE
TL/C/5594-12
FIGURE 2
9-106
z
8.0 Functional Description (Continued)
• Strobed 1/0
Strobed lID Mode uses the STB, BF and INTR signals to
latch the data and indicate that new data is available for
transfer. Port A is used for the transfer of data when in any
of the Strobed modes. Port B can still be used for Basic lID
and the lower 3-bits of port C are now the three handshake
signals for Strobed lID. Timing for this mode is shown in the
AC Characteristic Tables.
causing BF to go high (true). On the trailing (positive) edge
of STB the data is latched and the interrupt signal, INTR,
becomes valid indicating to the CPU that new data is available. INTR becomes valid only if the interrupt is enabled,
that is the output data latch for PC2 is set to 1.
When the CPU reads port A, address x'OO, the trailing edge
of the RD strobe causes BF and INTR to become inactive,
indicating that the strobed input cycle has been completed.
Initializing the NSC831 for Strobed lID Mode is done by
loading the data shown in Table IV into the specified register. The registers should be loaded in the order (left to right)
that they appear in Table IV.
• Strobed Output-Active (Mode 2)
During strobed output operations, an external device can
read data from port A using the STB signal. Data is initially
loaded into port A by the CPU writing to lID address x'OO.
On the trailing edge of WR, INTR is set inactive and BF
becomes valid indicating new data is available for the external device. When the external device is ready to accept the
data in port A it pulses the STB signal. The rising edge of
STB resets BF and activates the INTR signal. INTR becomes valid only if the interrupt is enabled, that is the output
latch for PC2 is set to 1. INTR in this mode indicates a
condition that requires CPU intervention (the output of the
next byte of data).
TABLE IV. Mode Definition Register Configurations
Mode
DDR
PortA
MDR
Basic 110
xxxxxxxO
DDR
PortC
PortC
Output
Latch
Port bit directions are
determined by the bits of
each port's DDR
Strobed Input
xxxxxxOl
00000000
xxxOll
xxxI xx
Strobed Output
(Active)
xxxxxOll
11111111
xxxOll
xxxI xx
Strobed Output xxxxxlll
(TRI-STATE)
11111111
xxxOll
xxxI xx
• Strobed Output-TRI-STATE (Mode 3)
The Strobed Output TRI-STATE Mode and the Strobed Output active (peripheral) bus mode function in a similar manner with one exception. The exception is that the data signals on PAO-7 assume the high impedance state at all
times except when accessed by the STB signal. Thus, in
addition to its timing function, STB enables port A outputs to
active logic levels. This Mode 3 operation allows other data
sources, in addition to the NSC831, to access the peripheral
bus. Strobed Mode 3 is identical to Strobed Mode 2, except
as indicated above.
• Strobed Input (Mode 1)
During strobed input operations, an external device can load
data into port A with the STB signal. Data is input to the
PAO-7 input latches on the leading (negative) edge of STB,
Example Mode 1 (Strobed Input):
INTR
SF
Results of Action
Reset NSC831
Load 01'H into
MDR
H
H
L
L
Load OO'H into
DORA
H
L
Load 03'H into
DDRC
H
L
Load 04'H into
Port C Bit-Set
Register
H
L
Basic input mode all ports.
Strobed input mode entered; no byte loads to port C
after this step; bit-set and clear commands to INTR
and BF no longer work.
Sets data direction register for port A to input;
data from port A peripheral bus is available
to the CPU if the STB signal is used, other
handshake signals aren't initialized, yet.
Sets data direction register of port C; buffer full
signal works after this step and it is unaffected
by the bit-set and clear registers.
Sets output latch (PC2) to enable INTR; INTR will
latch active whenever STB goes low; INTR can be
disabled by a bit-clear to PC2.·
STB pulses low
L
H
CPU reads Port A
H
L
Action Taken
INITIALIZATION
OPERATION
Data on peripheral bus is latched into port A;
INTR is cleared by a CPU read of port A or a
bit-clear of STB.
CPU gets data from port A; INTR is cleared;
peripheral is signalled to send next byte via
an inactive BF signal. Repeat last two steps until
EDT at which time CPU sends bit-clear to the
output latch (PC2).
*Port C can be read by the CPU at anytime, allowing polled operation instead of interrupt driven operation.
9-107
~
CO
....
Co)
-
CW)
~
Z
r-----------------------------------------------------------------------------~
8.0 Functional Description
(Continued)
Example Mode 2 (Strobed Output-active peripheral bus):
INTR
BF
Results of Action
Reset NSC831
Load 03'H into
MDR
H
H
L
L
Load FF'H into
DDRA
H
L
Load 03'H into
DDRC
H
L
Load 04'H into
Port C Bit-Set
Register
L
L
Basic input mode all ports.
Strobed output mode entered; no byte loads to
port C after this step; bit-set and clear
commands to INTR and BF no longer work.
Sets data direction register for port A to output;
data from port A is available to the peripheral if
the STB signal is used other handshake signals
aren't initialized, yet.
Sets data direction register of port C; buffer full
Signal works after this step and it is unaffected
by the bit-set and clear registers
Sets output latch (PC2) to enable INTR; active
INTR indicates that CPU should send data;
INTR becomes inactive whenever the CPU
loads port A; INTR can be disabled by a bit-clear
to STB.·
H
H
L
L
Action Taken
INITIALIZE
OPERATION
CPU writes to
PortA
STB pulses low
Data on CPU bus is latched into port A; INTR is
set by the CPU write to port A; active BF
indicates to peripheral that data is valid;
Peripheral gets data from port A; INTR is reset
active; The active INTR Signals the CPU to send
the next byte. Repeat last two steps until EOT at
which time CPU sends bit-clear to the output
latch (PC2).
·Port C can be read by the CPU at any time, allowing polled operation instead of interrupt driven operation.
Once the strobed mode of operation is programmed,
the only way to change the output data latch of PC2 is
by using the Bit-Set and Clear registers. The port C
byte write command will not alter the output data latch
of PC2 during the strobed mode of operation.
• Handshaking Signals
In the Strobed mode of operation, the lower 3-bits of port C
transmit/receive the handshake signals (PCO= INTR,
PC1 =BF, PC2=STB).
INTR (Strobe Mode Interrupt) is an active-low interrupt from
the NSC831 to the CPU. In strobed input mode, the
CPU reads the valid data at port A to clear the interrupt. In strobed output mode, the CPU clears the interrupt by writing data to port A.
STB (Strobe) is an active low input from the peripheral device, signalling a data transfer. The NSC831 latches
data on the rising edge of STB if the port bit is an input
and the peripheral should latch data on the rising
edge of STB if the port bit is an output.
The INTR output can be enabled or disabled, thus
giving it the ability to control strobed data transfer. It is
enabled or disabled, respectively, by setting or clearing bit 2 of the port C output data latch (STB).
BF
PC2 is always an input during strobed mode of operation, its output data latch is not needed. Therefore,
during strobed mode of operation it is internally gated
with the interrupt Signal to generate the INTR output.
Reset clears this bit to zero, so it must be set to one to
enable the INTR pin for strobed operation.
(Buffer Full) is a high active output from the NSC831.
For input port bits, it indicates that new data has been
received from the peripheral. For output port bits, it
indicates that new data is available for the peripheral.
Note: In either input or output mode the SF may be cleared by rewriting the
MOR.
9-108
9.0 NSC831/883B MIL-STD-883 Class B Screening
Electrical testing is performed in accordance with
RETS831X, which tests or guarantees all of the electrical
performance characteristics of the NSC831 data sheet. A
copy of the current revision of RETS831X is available upon
request. The following table is the MIL-STD-883 flow as of
the date of publication.
National Semiconductor offers the NSC831 D and NSC831 E
with full class B screening per MIL-STD-883 for Military/
Aerospace programs requiring high reliability. In addition,
this screening is available for all of the key NSC800 peripheral devices.
100% Screening Flow
Test
MIL-STD-883 Method/Condition
Requirement
Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Fine Leak
Gross Leak
Burn-In
2010 B
1008C 24 Hrs. @ + 150'C
1010C 10 Cycles -65'C/ + 150'C
2001 E 30,000 Gs, Y1 Axis
1014AorB
1014C
1015160 Hrs. @ + 125'C (using
burn-in circuits shown below)
+ 25'C DC per RETS831X
5% Max
+ 125'C AC and DC per RETS831X
-55'C AC and DC per RETS831X
+ 25'C AC per RETS831X
5005
100%
100%
100%
100%
100%
100%
100%
Final Electrical
PDA
QA Acceptance
Quality Conformance
External Visual
11.0 Timing Diagram
5242HR
NSC831AD/883B (Dual-In-Llne)
Input Clocks
2"s
5.5 Voc
4. 5V
CWCKl OV
10
51
CLOCK 1
'A,
51
CWCK2
51
CLOCK 3
-",
-"
';:-
100%
100%
100%
Sample per
Method 5005
100%
2009
10.0 Burn-In Circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
100%
40
39
38
37
36
35
34
CLOCK 2
·1·
n
ps+I·>-·+1.--8 PSt1=t2 pS
r2--n
rL
·1·
8"s
-~---!
4.5V - -
OV-+-~
3PS+--!
·12 ps
~....,...-
1-3 PS++7 ps---j
,-. ': __ ~~y .~"
33
32
31
30
29
28
27
26
25
24
23
22
21
I·
Tl-
L
!---10pS
TLIC15594-14
Note 1: All reSistors ±5%, % watt unless otherwise deSignated, 125°C op·
erating life circuit.
Note 2: E package burn-in circuit 5244HR is functionally identical to the 0
package.
'.
Note 3: All resistors 2.7 kfi unless marked otherwise.
Note 4: All clocks OV to 4.5V.
TLIC15594-13
Note 5: Device to be cooled down under power after
9-109
burnain.
...co ,---------------------------------------------------------------------------------,
(I)
~
Z
12.0 Ordering Information
NSC831 X X X
x
11
ifA1883+ ==AMIL-8TO·883
+ R,II••IIIIyScreening
. ' ' " " ' "(Note 1)
I = Industrial Temperature (_40DC to + 85 DC)
M = Military Temperature (-55 DC to = + 125DC)
No Designation = Commercial Temperature (ODC to + 70 DC)
'------l,-
1-1 = 1 MHz Clock Output
3 = 2.5 MHz Clock Output
-4 = 4 MHz Clock Output
I
0 = Ceramic Package
'---------1 N = Plastic Package
E = Ceramic Leadless Chip Carrier (LCC)
I
TL/C/5594-15
Note 1: Do not specify a temperallJre option: all parts are screened to military temperature.
13.0 Reliability Information (NSC831)
Gate Count
1900
Transistor Count
7400
9-110
,--------------------------------------------------------------------------, z
(J)
R National Semiconductor
o
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NSC888
NSC800™ Evaluation Board
microCMOS
.~.'
TL/C/8533-1
•
•
•
•
•
•
•
II 1k x 8 microCMOS RAM with sockets for
up to 4k x 8 RAM
[J Socket for additional 2k x 8, 2716
compatible memory component
~ Wire wrap area
II Edge connectors for system expansion
eI Single-step operation mode
II!iI Fully assembled and tested
NSC800 8-Bit microCMOS CPU
Executes Z80® Instruction Set
20 programmable parallel I/O lines
Two 16-Bit programmable
counters/timers
Powerful 2k x 8 monitor program
Five levels of vectored prioritized
interrupts
RS232 Interface
Product Overview
The board includes an NSC800 CPU plus RAM,
EPROM, 110, Timers and interface components yet
draws only 30 mA from the + 5V supply and 3 mA
from the - 5V supply.
Although designed primarily as an assessment vehicle, the NSC888 can be readily programmed and
adapted to a variety of uses. Wire wrap area is provided on-board for the user to build up additional circuitry
or interfaces, thus tailoring this high-performance, lowpower microprocessor board to meet individual needs.
The NSC888 is a self-contained microprocessor
board which enables the user to quickly evaluate the
performance and features of the NSC800 product
family. This fully assembled, tested board requires
only the addition of a ± 5V supply and an RS232 interface cable to the user's terminal to begin NSC800
evaluation.
A powerful system monitor is provided on the board
which controls serial communications via the RS232
port. The monitor also includes command functions to
load, execute and debug NSC800 programs.
9-111
m
m
.-----------------------------------------------------------------------------~
m
Functional Description
Z
Figure 1 and Figure 2 provide information on the organization of the NSC888 board. Please refer to these
figures for the following discussion.
• An additional EPROM socket is also on-board which
accepts a 2k byte 2716 compatible memory component.
Central Processor
Input/Output
The powerful NSC800 is the central processor for the
NSC888. It provides bus control, clock generation and
extensive interrupt capability. Featuring a multiplicity
of programmable registers and sophisticated addressing modes, the NSC800 executes the Z80 instruction
set.
• Parallel I/O
~
The NSC888 provides 20 programmable parallel 1/0
lines implemented using the 1/0 ports of the
NSC810A RAM-I/O-Timer. The port bits may be individually defined as input or output, and can also be
written to or read from in bytes. The 1/0 lines are
conveniently brought to a 50 contact edge connector for user interface.
Memory
-128 bytes of RAM are provided by the NC810A
RAM-I/O-Timer and are used by the monitor program for the system stack.
- 1024 bytes of RAM are provided by two 1k x 4
NMC6514's. Sockets are provided for six additional
NMC6514's, for a total of 4k bytes of RAM.
- A 2k byte EPROM system monitor is provided onboard which includes facilities to load, execute and
debug a users program.
• Serial I/O
An RS232 connector and accompanying support circuitry are provided on-board. Two 1/0 lines from the
NSC810A RAM-I/O-Timer are used for the serial
communications function, which is controlled exclusively by software. The baud rate is determined
upon system initialization by the character bit rate
from the users terminal. The maximum baud rate is
2400 baud.
Block Diagram
EXTERIIAL
COIITROL
BUS
Ala·151
R/W
MEMORY
IIscaoo
CPU
4Kx 8
iii
4K
SINGLE
STEP
MODE
A 10·71
READ
DNLY
MEMORY
DEMUl·
TlPLEXER
82PCI2
ADDRESS
DATA
COMMUIII·
CATION
INTERFACE
DATA
XMIT
}.I/O
TLICIBS33-2
FIGURE 1
9-112
Functional Description
The commands supported by the NSC888 system
monitor are as follows:
a B - Select a new baud rate
a D - Display memory
o F - Fill memory between ranges
a G - Execute program with break points
a H - Hexadecimal math routine
a J - Non-destructive memory test
o K - Store 16-bit value in memory
o M - Move a block of data
a P - Put ASCII characters in memory
a Q - Query I/O ports
aS - Substitute and/or examine memory
a T - Type memory contents in ASCII
a V - Verify two blocks of data
a X - Examine or modify CPU registers
o Y - Memory search for string
These commands are fully explained in the NSC888
Hardware/Software Users Manual.
(Continued)
Timers
The NSC888 provides two fully programmable binary
16-bit counters/timers utilizing the NSC810A RAM-II
O-Timer. These signals are also brought to the parallel I/O connector. Each timer may operate in any of
six different modes:
• Event Counter
o Accumulative Timer
o Restartable Timer
• One Shot
• Square Wave
• Pulse Generator
Connectors
• Parallel I/O
The parallel I/O lines and timer lines from the
NSC810A RAM-I/O-Timer, plus interrupt lines from
the CPU are brought to this 50 contact edge connector.
• System Bus
All NSC800 CPU lines except XIN are brought to this
86 contact edge connector. In addition, the -5V line
is also brought to the system bus connector.
Single Step/Power Save
The NSC888 provides a unique single-step mode, utilizing the Power Save input of the NSC800 CPU. This
input, when activated, reduces CPU power consumption from 50 mW to only 25 mW. It also allows the user
to single-step through a program, checking and modifying code. This function is controlled via a switch on
the board.
• RS232
This connector is provided for system interface to
the users terminal.
Interrupts
The NSC888 utilizes the powerful interrupt processing
capability of the NSC800 CPU. Interrupts are routed
via a jumper matrix to the five interrupt inputs of the
NSC800. Each input, which may be from the
NSC810A I/O ports, NSC810A timers or off board via
the system bus connector, generates a unique memory address (see Table I). All interrupts with the exception of NMI can be masked via software. Interrupt
lines are also brought to the parallel I/O connector.
Specifications
Microprocessor
CPUData WordInstruction WordCycle Time-
TABLE I.
Interrupt
Input
Memory
Address
NMI
RSTA
RSTB
RSTC
INTR
0066H
003CH
0034H
002CH
0038H*
Type
Priority
Non-maskable
Maskable
Maskable
Maskable
Maskable
Highest
System ClockRegisters-
Number of
InstructionsAddress
Capability-
Lowest
'mode 1
NSC888 Firmware
The NSC888 system monitor is provided by a preprogrammed EPROM. This comprehensive monitor includes facilities to load, execute and debug programs.
The monitor allows the user to examine and modify
any RAM memory location or CPU register. It permits
the insertion of break points to facilitate debugging.
Programs can be executed starting at any location.
9-113
NSC800
8 bits
8, 16, 24, 32 bits
2.00 JLs (minimum instruction
time)
2.00 MHz
14 general purpose (8-bit)
2 index registers (16-bit)
1 stack pointer (16-bit)
1 program counter (16-bit)
158
64k bytes
Memory
RAM-
ROM/EPROMAccess Time-
1152 bytes on-board plus
sockets for an additional 3k
bytes
Sockets for 4k bytes
on-board
625 ns for opcode fetch
875 ns for memory read
z
en
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~
~
~
o
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,---------------------------------------------------------------------------------,
Specifications
Order Information
(Continued)
Connectors
System Bus
Parallel I/O
Serial I/O
Power
NSC888
86-pin double-sided card
cage edge connector on
0.156 inch centers
50-pin double-sided edge
connector on 0.1 inch centers
Recommended mating
connector:
3M 3415-0001
AMP 2-86792-3
Standard RS232 connector
Includes CPU, 1152 bytes of
RAM, sockets for additional
3k bytes of RAM, 2k byte
monitor with additional socket
for 2k byte ROM/EPROM, 20
I/O lines, RS232 interface,
wire wrap area.
Documentation
The NSC888 Hardware/
Software Users Manual and
NSC800 Microprocessor
Family Handbook are shipped
with the NSC888 Evaluation
Board
+ 5V 30 mA (27C16 EPROM
monitor) or 90 mA (2716
EPROM monitor)
-5V3 mA
Physical
Height
Width
6.75 (17.15 cm)
7.85 (19.94 cm)
TL/C/B533-3
FIGURE 2. NSC888 Evaluation Board
9-114
(')
o
3
Comparison Study NSC800 vs.
808S/80C8S Z80® /Z80 CMOS
"C
...(ii'
QI
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~
TABLE I.
Machine Cycle Status - N5C800 and 8085
Introduction
The NSC800 is an 8-bit parallel processor with a Z80 compatible instruction set manufactured using National's microCMOS process. This process combines the speed of silicon
gate NMOS with the low power inherent to CMOS.
The NSC800 has a 16-bit address bus which consists of the
upper eight address bits (A8-A15) and the lower eight address bits (ADO-AD?). Address bits AO-A? are time multiplexed on the 8-bit bidirectional address/data bus (ADOAD?).
There are several advantages to using a multiplexed address/data bus. Multiplexing frees pins on the CPU and peripheral packages for other purposes, such as status outputs, DMA control lines, and multiple interrupts. This can
reduce system component count. Fewer bus signal lines are
required for device interconnections in most applications
(16 lines for multiplexed bus systems vs. 24 lines for nonmultiplexed systems). This reduces PC board complexity.
Peripherals of the NSC800 Family include:
50
S1
101M
Status
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0
Memory Write
Memory Read
I/O Write
I/O Read
Opcode Fetch
Bus Idle'
Halt
I:
C.
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'ALE not suppressed during Bus Idle
Direct Memory Access (DMA) control Signals BREQ and
BACK of the NSC800 perform the same functions as HOLD
and HLDA on the 80B5. The NSCBOO allows simple wire
ORing by using active low states for the DMA control signals. An active low on the BREQ (Bus Request) line, tested
during the last T state of the current M cycle, initiates a
DMA condition. The N8C800 will then respond with an active low BACK (Bus Acknowledge) Signal causing the address, data and control buses (TRI-STATE® circuits) to go
to the high impedance state, and notifies the interrupting
device that the system bus is available for use. There is a
difference in the timing relationship between these functions
for the two processors. The BOB5 responds with HLDA, onehalf T state after it recognizes HOLD. The N8C800 responds with BACK, one T state after it recognizes BREQ.
NSC810A RAM I/O Timer
NSC831 I/O
NSC858 UART
In addition to the above parts, a complete family of low power speed compatible logic and interface parts is also available.
NSC800 VS. 8085
During Input/Output cycles for peripherals, the N8C800 automatically inserts one wait state. This reduces the external
hardware required for slow peripherals. The BOB5 does not
insert its own wait state during these I/O cycles. When they
are needed, the 60B5 user must design his system to contain the additional hardware required to do the wait state
insertion. When more than one wait state is required, additional wait states can be added to the 1/0 cycles in a similar
way on both the N8CBOO and the 8085. On the N8CBOO,
this is accomplished by bringing the WAIT control signal
active low during T2 of an I/O or memory cycle. The 80B5 is
controlled in the same way through the use of the READY
line.
The N8CBOO instruction set is Z80 compatible and more
powerful than the 80B5's. The N8CBOO does not support
the RIM and 81M instructions of the 8085 (RIM and 81M can
be emulated with I/O instructions), but has an improved instruction set for enhanced system performance. The
NSCBOO has two functions, RFSH and PS, instead of the
two serial I/O lines SOD and SID. RFSH (Refresh) is a
status signal which indicates that an eight bit refresh address is present on the address/data bus (ADO-AD?). The
refresh address occurs during T3 of each M1 (opcode fetch)
cycle. The internal refresh counter is incremented after
In terms of bus structure, the N8CBOO is similar to the 8085.
Both processors utilize a multiplexed bus and timing relationships are approximately the same. The 80B5 does not
guarantee that output data on ADO-AD? are valid on both
the leading and trailing edges of WR. For the N8C800, data
are valid on both the leading and trailing edges of WR.
Both the NSC800 and the BOB5 use ALE, SO, 81, and 10/M
to indicate status. The lower eight address bits are guaranteed to be valid on the data bus at the trailing edge (high to
low transition) of ALE (Address Latch Enable). This signal is
used by the external system components to separate the
address and data buses. When the only components utilized in the system are members of the NSCBOO family
(which contain on-chip demultiplexers), ALE needs only to
be connected to the enable inputs. If non-N8C800 family
components are used, ALE can be used to enable an B-bit
latch to perform the function of bus separation.
Decoding status bits 80 and 81, in conjunction with 10/M,
notifies the external system of the type of the ensuing M
cycle. TABLE I shows a truth table of the encoded information. During a halt status the N8CBOO will continue to refresh
dynamic RAM.
Z80® is a registered trademark of Zllog Corporation.
9-115
Q:)
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Q:)
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o
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r--------------------------------------------------------------------------,
each instruction cycle. This counter output can be employed
by the user's dynamic RAM refresh circuits. The PS (Power
Save) control input, when active, causes the CPU to stop all
intemal clocks at the end of the current instruction, which
reduces power consumption. The on-chip oscillator and
ClK remain active for any required extemal timing. The
NSCaOO leaves all buses unchanged during this time, which
has the effect of reducing power consumption on other
CO
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8
TABLE II indicates the major differences between the
NSCaOO and the aoa5 presented in tabular form for quick
reference.
TABLE II.
NSC800 vs. 8085/80C85 Comparison
CO
I:)
CO
CMOS parts in the system since the buses are not changing
states. All intemal registers and status conditions are maintained, and when PS subsequently goes high, the opcode
fetch cycle begins in a normal fashion.
Ite'm
Power Consumption
Bus Drive Capacity
Dynamic RAM Refresh Counter
Automatic WAIT State on 110
Number of instruction types
Number of Programmer
Accessible Registers
Block 110 and Search
NSC800
8085
80C85
50mW@5V
1 std. TIL
(100 pF)
Yes, a-bit
Yes
15B
a50mW@5V
1 std. TIL
(100 pF)
No
No
ao
50mW@5V
1 std. TIL
(150 pF)
No
No
ao
22
Yes
10
No
10
No
Nscaoo VS. zao/zao CMOS
The NSCaOO contains the same complement of intemal registers as the zao and maintains instruction set and opcode
compatibility.
S. The NSCBOO provides three interrupts that are not available on the zao: RSTA, RSTB, RSTC. This gives the
NSCBOO five levels of vectored, prioritized interrupts with
no external logic. The general purpose interrupt (INTR)
and Non-maskable Interrupt (iiIMi) are identical to the
za~. INTR has the same three modes of operation in
both processors: Modes 0, 1, and 2. Upon initialization,
the NSCaOO is in mode 0 to maintain BOBO code compatibility. NMI, when active, causes a restart to location X'66
as is the case with the zao. Being a non-maskable interrupt, NMI cannot be disabled. The additional interrupts
RSTA, RSTB, and RSTC cause restarts to locations
X'SC, X'S4, and X'2C respectively. The priority levels of
the five interrupts are: NMI (highest), RSTA, RSTB,
RSTC, and INTR (lowest). For the NSCaOO, Interrupt acknowledge (lNTA) is provided on a dedicated output pin
and need not be decoded extemally.asis the case with
the ZBO. With the status outputs (SO, Sl, 10/M), early
read/write information is obtainable. This is impossible to
derive from the zao.
Machine cycle timing for the standard speed version of the
NSCaOO compares directly with the zao. Although the software execution speeds are comparable, the NSCBOO offers
architectural advantages.
The bus structures of the NSCaOO and the ZBO are quite
different. The NSCBOO uses a multiplexed address/data
bus. The zao has separate address and data buses. As
stated earlier, the separate bus structure requires additional
signal lines for interconnection and gives up some package
pins which could be used for other purposes.
The main differences between the NSCBOO and the zao, in
addition to the bus structures, are the refresh counter, onchip clock generation, and the interrupt capability.
1. The NSCaOO contains an a-bit refresh counter as opposed to a 7-bit refresh counter in the zao. (This enables
refresh of a 64K dynamic RAM system memory). The refresh timing of the NSCaOO is functionally identical to that
of the zao.
Refer to TABLE III for comparison of the major differences between the NSCBOO and the zao.
2. The on-chip clock generation reduces the system component count. In place of an extemal clock generator chip,
the NSCaOO needs only a crystal or RC circuit to produce
the system clock.
TABLE III.
NSC800 vs. Z80/Z80 CMOS Comparison
Item
NSC800
Z80
Z80CMOS
Power Consumption
Instruction Execution
(Minimum)
On-Chip Clock Generator
Number of On-Chip Vectored
Interrupts
Early Read/Write Status
Dynamic RAM Refresh Counter
50mW@5V
750mW@5V
75mW@5V
1 /-Ls
1 /-Ls
l/-Ls
Yes
No
No
5
2
2
Yes
Yes, a-bit
No
Yes,7-bit
No
Yes,7-bit
9-116
SUMMARY
NSC800 Family Devices
(microCMOS)
National's NSCBOO has a ZBO compatible instruction set,
which is more powerful than the BOB5. NSCBOO external
hardware requirements are less because of on-chip automatic wait state insertion, clock generation and five levels of
vectored prioritized interrupts.
MMB2PCOB B-Bit Bidirectional Transceiver
MMB2PC121nputiOutput Port
Not.: The above devices are pin for pin and function compatible with the
standard TIL, CMOS or NMOS versions currently available.
The BOB5 and the NSCaOO have similar bus structures, and
timing. The key advantages of the NSCBOO over the BOB5
are the larger instruction set, more registers accessible to
programmers, low power consumption, and a dynamic RAM
refresh counter.
The main advantages of the NSCBOO compared to the zao
are the multiplexed address/data bus, an B·bit refresh counter for dynamic RAMs, on-chip clock generation, and five
interrupts. The speed of the NSCBOO and ZBO is the same
but, the NSCBOO has very low power consumption.
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Software Comparison NSC800 vs. 8085, Z80®
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Introduction
register and any 110 location. There are also block 1/0 instructions which allow moving data blocks of up to 256
bytes directly from memory to any peripheral location or
from any peripheral location to a block of memory.
Bit manipulation instructions can set, test or reset any bit in
the accumulator, any general purpose register or any memory location.
The NSCBOO is an B-bit parallel microprocessor fabricated
using National's microCMOS process. This process allows
fabrication of a microprocessor family that has the performance of silicon gate NMOS along with the low power inherentto CMOS. The NSCBOO instruction set is a superset of
the BOBO's instruction set. It comprises over 900 operation
codes falling into 15B instruction types. The instruction categories are:
• Load and Exchange
• Arithmetic and Logie
• Rotate and Shift
• Jump and Call
• Input/Output
• Bit manipulation (set, test, reset)
• Block Transfer and Search
• CPU control
The load instructions allow the movement of data into and
out of the CPU, between internal registers, plus the capability to load immediate data into internal registers. The exchange instructions allow swapping of data between two
registers.
The block transfer instructions allow a single instruction to
move any size block of memory to any other location in
memory. Through the use of the block search instructions,
any size block of memory can be searched for a particular
byte of data.
Finally, the CPU control group allows user control over the
various modes of CPU operation, such as enabling and disabling interrupts or selling modes of interrupt response.
The following sections will compare the instruction set of
the NSCBOO with those of the 8085 and the Z80.
NSC800 vs. 8085
The 8085 instruction set consists of 246 op codes falling
into 80 instruction types. With the exception of RIM and
SIM, the NSC800 is instruction and op code compatible with
the 80B5. The RIM and SIM instructions are not supported
because the NSC800 does not have the SID and SOD serial
1/0 lines. The interrupt mask on the NSC800 is accessible
by writing the mask word to 1/0 location X'BB. The bit positions for the interrupt enables are shown below:
The arithmetic and logic instructions operate on the data in
the accumulator (primary working register) and in the other
registers. Status flags are set or reset depending on the
result of the particular operation executed. This group includes B·bit and 16·bit operations.
The rotate and shift instructions allow any register or memory location to be rotated or shifted, left or right, with or without carry. These can be either an arithmetic or logic type.
The jump and call group includes several different types:
one byte calls, two byte relative jumps, conditional branching, and three byte calls and jumps, which can reach any
location in memory. Calls push the current contents of the
Program Counter onto the stack before branching to the
new program address to facilitate subroutine execution.
Input/Output instructions allow communications between
the NSCBOO and external peripheral devices. There are 255
(location X'BB is used for an interrupt mask) unique peripheralllO locations available to the NSCBOO. 1/0 instructions
can move data between any memory location or internal
Bit
7
6
5
4
3
2
o
9-11B
Location X'BB Bit Assignments
Interrupt Enable for
N/A
N/A
N/A
N/A
RSTA
RSTB
RSTC
INTR
NI A = not used: a don't care bit.
r---------------------------------------------------------------------------------,
As an example. to enable interrupts on the RSTA input, a
logic '1' is written into bit 3 of 110 location X'SS. If the master interrupt enable has been set by executing the Enable
Interrupt (El) instruction, interrupts will now be accepted on
RSTA only.
The differences between the flag registers on the NSCBOO
and the 80B5 are identified below:
Other than the method of enabling and disabling individual
interrupts and the RIM and SIM instructions themselves, the
NSC800 instruction set is a superset of the 8085's instruction set.
2. In the NSC800, the PIV flag will not match the B085's P
flag after an B-bit arithmetic operation, since it acts as an
overflow bit for the NSC800, but acts as a parity bit for these
operations in the BOBS.
The following benchmark demonstrates the code reduction
and throughtput improvement obtained by using one of the
special NSC800 instructions over the same function implemented with the limited 8085 instruction set. The function is
to move a 512-byte block of data from one section of memory to another.
8085
3. Sit position D2 (changed for the NSC800) is a dual purpose flag; it indicates the parity of the result in the accumulator when logical operations are performed and also represents overflow when Signed two's complement arithmetic
operations are performed. An overflow occurs when the result of a two's complement operation within the accumulator
is out of range.
Bytes
3
3
3
1
LOOP:
1
3
Mnemonics
LXI
H,SOURCE
LXI
D,DEST
LXI
B,COUNT
MOV
A,M
STAX
D
INX
H
INX
D
DCX
B
MOV
A,C
ORA
B
JNZ
LOOP
Total: 19
1. Sit position D1 (additional on the NSCBOO) contains an
add/subtract flag that is used internally for proper operation
of SCD instructions.
Cycles
4. For general Compare operations, the NSC800 uses the
PIV flag as an overflow bit, while the 8085 uses the P flag
for parity.
5. The H flag (bit position D4) on the NSCBOO is functionally
the same as the auxiliary carry on the 8085.
10
10
10
7
7
6. For Double Precision Addition, the NSCBOO leaves the H
flag undefined, while the BOBS does not affect the AC flag
for this operation (DAD).
6
6
6
4
4
7. For Rotate operations, the NSCBOO resets the H flag,
while the 80B5 leaves the AC flag unaffected for these operations.
B. When Complementing the Accumulator, the NSCBOO sets
the H flag (H = 1), while the 80B51eaves the AC flag unaffected.
10
Total: 80
9. When Complementing Carry, the NSC800 leaves the H
flag undefined, while the 80B5 leaves the AC flag unaffected.
NSC800
Bytes
3
3
3
2
Mnemonics
LD
HL,SOURCE
DE,DEST
LD
BC,COUNT
LD
LDIR
Total: 11
Cycles
10. When Setting the Carry, the NSCBOO clears the H flag
(H = 0), while the 80B5 leaves the AC flag unaffected.
10
10
10
21
Nscaoo Vs. zao
The instruction set and op codes of the NSCBOO are identical to those of the ZBO. Software written for the ZBO will run
on the NSCBOO without change, unless 110 location X'SS is
used. Another location should be assigned since location
X'SS is an on-chip write-only register used for the interrupt
mask. Since the NSCBOO executes code at the same cycle
time as the Z80, any software timing loops will also remain
the same, and no change is necessary. The NSC800 expanded interrupt capability is transparent to the user unless
specifically evoked by the user software.
Total: 51
The use of the LDIR instruction of the NSC800 results in a
47.5% increase in throughput and a 42% decrease in the
number of bytes required to implement the function when
compared with the 8085 implementation. The time required
to make the move is approximately 2.69 ms for the NSCBOO
and approximately 5.12 ms for the 80B5. Note that even
though the BOBS runs at a faster cycle time (200 ns vs. 250
ns), the improved instruction set of the NSCBOO produces
an increase in system performance.
The NSCBOO has B-bit refresh rather than the 7-bit refresh
scheme of the Z80. Therefore, the state of the 8th bit will be
indeterminate since it is part of the R Register and so included in refresh operations.
The NSC800 includes all 8085 flags plus some additional
flags. The flag formats for the NSCBOO and 80B5 are:
NSC800 Flags (Z80 Flags)
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8085 Flags
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9-119
The status flags on the NSCBOO are identical to those on
the ZBO. There is no difference between the positions of the
individual bits in the flag register, nor in the manner in which
the flags are set or reset due to an arithmetic or logical
operation. Testing of the flags is also the same.
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Section 10
Physical Dimensionsl
Appendices
Section 10 Contents
Glossary of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
10·2
10-3
10-10
Glossary
In our efforts to be concise and precise, we often invent new words or acronyms to use as shorthand representations of "things"
that require much longer names if the jargon is not used. Being humans, we then become very impressed with our ability to
exclude those not in "the know" and another "in" group is formed. This glossary has been developed to help bridge this
language gap. We know it will help. We hope you will use it.
Abort-The first step of recovery when an instruction or its operand(s) is not available in main memory. An Abort is initiated by
the Memory Management Unit (MMU) and handled by the CPU.
Absolute Address-An address that is permanently aSSigned to a fixed location in main memory. In assembly code, a pattern
of characters that identifies a fixed storage location.
Access Time-The time interval between when a request for information is made and the instant this information is available.
Access Class-The five Series 32000 access classes are memory read, memory write, memory read-modify-write, memory
address, and register address. The access class informs the Series 32000 CPU how to interpret a reference to a general
operand. Each instruction assigns an access class to each of it two operands, which in turn fully defines the action of any
addressing mode in referencing that operand.
Accumulator-A register which stores the result of an ALU operation.
Ada-A high level language deSigned for the Department of Defense. It gives preference to full English words. It is meant to be
the standard military language.
Address-An expression, usually numerical, which designates a specific location in a storage or memory device.
Address-Data Reglster-A register which may contain either address or data, sometimes referred to as a general-purpose
register.
Address Strobe-Control signal used to tell external devices when the address is valid on the external address bus.
Address Translation-The process by which a logical address emanating from the CPU is transformed into a physical address
to main memory. This is performed by the Memory Management Unit (MMU) in Series 32000 systems. Logical address to
Physical address mapping is established by the operating system when it brings pages into main memory.
Addressing Mode-The manner in which an operand is accessed. Series 32000 CPUs have nine addressing modes: Register,
Register Relative, Memory Relative, Immediate, Absolute, External, Top-of Stack, Memory Space, and Scaled Indexing.
Algorithm-A set of procedures to which a given result is obtained.
Alignment-The issue of whether an instruction must begin on a byte, double byte, or quad byte address boundary.
ALU-Arithmetic Logic Unit. A computational subsystem which performs the arithmetic and logical operations of a digital
system.
Array-A structured data type conSisting of a number of elements, all of the same data type, such that each data element can
be individually identified by an integer index. Arrays represent a basic storage data type used in all high-level languages.
ASCII-(American National Standard Code for Information Interchange, 1968). This standard code uses a character set generally coded as 7-bit characters (8-bits when using parity check). Originally defined to allow human readable information to be
passed to a terminal, it is used for information interchange among data processing systems, communication systems, and
associated equipment. The ASCII set consists of alphabetic, numeric, and control characters. Synonymous with USASCII.
Assemble-To prepare a machine language program (also called machine code or object code) from a symbolic language
program by substituting absolute operation codes for symbolic operation codes and absolute or relocatable addresses for
symbolic addresses. Machine code is a series of ones and zeros which a computer "understands".
Assembler-This program changes the programmer's source program (written in English assembly language and understandable to the programmer) to the 1's and O's that the machine "understands". In particular, the Assembler converts assembly
language to machine code. This machine code output is called the OBJECT file.
Assembly Language-A step up in the language chain. This is a set of instructions which is made up of alpha numeric
characters which, with study, are understandable to the programmer. Different type of machines have different assembly
languages, so the assembly language programmer must learn a different set of instructions each time s/he changes machine.
Associative Cache-A dual storage area where each data entry has an associated "tag" entry. The tags are simultaneously
compared to the input value (a logical address) in the case of the MMU, and if a matching tag is found, the associated data entry
is output. An associative cache is present within the MMU in Series 32000 systems to provide logical-to-physical address
translation.
Asynchronous Device-A device in which the speed of operation is not related to any frequency in the system to which it is
connected.
BASIC-This acronym stands for Beginner's All-purpose Symbolic Instruction Code. BASIC is one of the most "English like" of
the high level languages and is usually the first programming language learned.
Baud Rate-Data transfer rate. For most serial transmission protocols, this is synonymous with bits-per-second (bps).
BCD-Binary Coded Decimal. A binary numbering system for coding decimal numbers. A 4-bit grouping provides a binary value
range from 0000 to 1001, and codes the decimal digits "0" through "9". To count to 9 requires a single 4-bit grouping; to count
to 99 takes two groupings of 4 bits; to count to 999 takes three groupings of 4 bits, etc.
Benchmark-In terms of computers, this refers to a software program designed to perform some task which will demonstrate
the relative processing speed of one computer versus another.
10-3
Glossary (Continued)
Bit-An abbreviation of "binary digit". It is a unit of information represented by either a one or a zero.
Bit Field-A group of bits addressable as a single entity. A bit field is fully specified by the location of its least significant bit and
its length in bits. In Series 32000 systems, bit fields may be from one to 32 bits in length.
Branch-A nonsequential flow in a software instruction stream.
Breakpoint-A place in a routine specified by an instruction, instruction digit, or other condition, where the software program
flow will be interrupted by external intervention or by a monitor routine.
Buffer-An isolating circuit used to avoid reaction of a driven circuit on the corresponding driver circuit. Buffers also supply
increased current drive capacity.
Bus-A group of conductors used for transmitting signals or power.
Bus Cycle-The time necessary to complete one transfer of information requiring the use of external address, data and control
buses.
Byte-Eight bits.
Byte Enable-BEO to BE3. CPU control signals which activate memory banks, each bank providing one byte of data per
address.
C-A highly structured high level language developed by Bell Laboratories to optimize the size and efficiency of the program.
This language has gained much popularity because it allows the prograrnmer to get close to the hardware (low level) as well as
being a high level language. Before C, the programmer who had to address the hardware had to use assembly language or
machine code.
Cache-See Associative Cache.
Cache Hit-In the MMU, logical-to-physical address translation takes place via the associative cache. For this to happen, the
addressed page must be resident in physical memory such that a logical address tag is present in the MMU's translation cache.
Cache Miss-When a logical address is presented to the MMU, and no physical address translation entry is found in the MMU's
associative cache.
Cascaded-Stringing together of units to expand the operation of the unit. Interrupt Control Units present in a Series 32000
system which are in addition the Master ICU are referred to as "cascaded" ICUs; i.e., interrupts cascade from a second-level
ICU through the master ICU to the CPU.
Clock-A device that generates a periodic signal used for synchronization.
Clock Cycle-After making a low-to-high transition, the clock will have completed one cycle when it is about to make another
low-to-high transition. This time is equal to Iff where f = the clock frequency.
COBOL-This acronym stands for "Common Business Oriented Language". It is a language especially good for bookkeeping
and accounting.
COFF-COMMON OBJECT FILE FORMAT is a standard way of constructing files developed by AT&T for the express purpose of
making all files similar. This will help reduce the situation where large files developed by one organization won't run on another
organization's equipment simply because the software interfaces are different. It provides a great potential for savings in both
time and money.
Compile-To take a program written in a High-Level Language such as C, Pascal, or FORTRAN and convert it into an objectcode format which can be loaded into a computer's main memory. During compilation, symbolic HLL statements, called source
code, are converted into one or more machine instructions which the CPU "understands". A compiler also calls the assemble
function.
Compiler-The program that converts from Source to Machine Code. The conversion is from a particular high level language to
machine code. For example, the C compiler will convert a C source program written by a programmer to machine code. This
machine code output is in the same format as that of the assembler and is also called an OBJECT file.
CPU-Central Processing Unit. The portion of a computer system that contains the arithmetic logic unit, register file, and other
control oriented subsystems. It performs arithmetic operations, controls instruction processing, and provides timing signals and
other housekeeping operations.
Cross Support-The alternative to using a "Native" development like SYS32 to develop your programs is to use Cross Support
software. "Native" means that the CPU in the development system is the same as the CPU in the system being developed.
Cross support software is all of the necessary programs for development that operate on one CPU, but generate code for
another CPU. Use of the VAX to generate Series 32000 code is a good example of cross support.
Demand-Paged Virtual Memory-A virtual memory method in which memory is divided into blocks of equal size which are
referred to as pages. These pages are then moved back and forth between main memory and secondary storage as required by
the CPU. Demand paging reduces the problem of memory fragmentation which results in unused memory space.
Dispatch Table-In Series 32000 systems, this is an area of memory which contains interrupt descriptors for all possible
hardware interrupts and software traps. The interrupt descriptor directs the CPU to the module descriptor for the procedure
which is designed to handle that particular interrupt.
Dlsplacement-A numerical offset from a known point of reference. Displacements are used in programming to facilitate
position independent code, such that a given program can be loaded anywhere in memory. In Series 32000 processors, a
displacement is contained in the instruction itself.
10-4
.--------------------------------------------------------------------.Q
Glossary (Continued)
0'
DMA-Direct Memory Access. A method that uses a small processor (DMA Controller) whose sole task is that of controlling
input-output or data movement. With DMA, data is moved into or out of the system without CPU intervention once the DMA
controller has been initialized by the CPU and activated.
.:c!
Double-Precislon-With reference to 32000 floating-point arithmetic, a double-precision number has a 52-bit fraction field, 11bit exponent field and a sign bit (64-bits total).
Double Word-Two words, i.e., 32 bits.
Editor-A program which allows a person to write and modify text. This program can be as complicated as the situation
requires, from the very simple line editor to the most complicated word processor. Letters, numbers and unprintable control
characters are stored in memory so that they can be recalled for modification or printing. The programmer uses this device to
enter the program into the computer. At this stage, the program is recognizable to both the programmer and the computer as
lines of English text. This English version of the program is known as the SOURCE.
Emulate-To imitate one system with another, such that the imitating system accepts the same data, executes the same
programs, and achieves the same results as the imitated system.
Exception-An occurrence which must be resolved through CPU intervention. An exception results in the suspension of normal
program flow. In Series 32000 systems, exceptions occur as a result of a hardware reset, interrupt or software traps. Execution
of floating-point instructions may also result in occurrences which must be resolved through CPU intervention.
Exponent-In scientific notation, a numeral that indicates the power to which the base is raised.
EXEC2-NSC's Real Time Executive for Series 32000.
FIFO-First-in first-out. A FIFO device is one from which data can be read out only in the same order as it was entered, but not
necessarily at the same rate.
Floating-Point-A method by which computers deal with numbers having a fractional component. In general, it pertains to a
system in which the location of the decimal/binary point does not remain fixed with respect to one end of numerical expressions,
but is regularly recalculated. The location of the point is usually given by expressing a power of the base.
FORTRAN-A high level language written for the scientific community. It makes heavy use of algebraic expressions and
arithmetic statements.
FP-Frame Pointer. CPU register which pOints to a dynamically allocated data area created at the beginning of a procedure by
the ENTER instruction.
FPU-Floating-Point Unit is a slave processor in Series 32000 systems which implements in hardware all calculations needed to
support floating-point arithmetic, which otherwise would have to be implemented in software. The NS32081 FPU provides highspeed floating point instructions for single (32-bit) and double (64-bit) precision. Supports IEEE standard for binary floating point
arithmetic. Compatible with NS32032, NS32C032, NS32016, NS32C016 and NS32008 CPUs.
Fragmented-The term used to describe the presence of small, unused blocks of memory. The problem is especially common
in segmented memory systems, and results in inefficient use of memory storage.
Frame-A block of memory on the stack that provides local storage for parameters in the current procedure.
GENIX-The NSC version of the UNIX operating system, ported to work with the Series 32000. It also has all of the necessary
utilities added so that program development can be accomplished.
Hardware-Physical equipment, e.g., mechanical, magnetic, electrical, or electronic devices, as opposed to the software
programs or method in which the hardware is used.
High Level Languages-These are languages which are not dependent on the type of computer on which they run. A program
written in a high level language will generally run on any computer for which there is a compiler for that language. This feature
makes high level languages "Portable", i.e., the same program will run on many different types of computers. A HLL requires a
compiler or interpreter that translates each HLL statement into a series of machine language instructions for a particular
machine.
ICU-Interrupt Control Unit. A memory-mapped microprocessor support chip in Series 32000 systems which handles external
interrupts as well as additional software traps. The ICU provides a vector to the CPU to identify the servicing software procedure.
Indexing-In computers, a method of address modification that is by means of index registers.
Index Register-A register whose contents may be added to or subtracted from the operand address.
Indirect Addressing-Programming method where the initial address is the storage location of a word which is the actual
address. This indirect address is the location of the data to be operated upon.
Instruction-A statement that specifies an operation and the values or locations of its operands, i.e., it tells the CPU what to do
and to what.
Instruction Cycle-The period of time during which a programmed system executes a particular instruction.
Instruction Fetch-The action of accessing the next instruction from memory, often overlapped by its partial execution.
Instruction Queue-With Series 32000 CPUs, this is a small area of RAM organized as a FIFO buffer which stores prefetched
instructions until the CPU is ready to execute them.
Interpreter-A program which translates HLL statements into machine instructions at run time, i.e., while the program is
executing, and is co-resident with the user program.
10-5
m
Glossary (Continued)
Interrupt-To signal the CPU to stop a software program in such a way that it can be resumed and branch to another section of
code. Interrupts can be caused by events external or internal to the CPU, and by either software or hardware.
INTBASE-Interrupt Base Register. In the Series 32000, a 32-bit CPU register which holds the address of the dispatch table
containing addresses for interrupts and traps.
ISE-In-System Emulator. A computer system which imitates the operation of another in terms of software execution. In
microprocessor system development, the ISE takes the place of the microprocessor by means of a connector at the end of an
umbilical cable. Not only does the ISE perform all the functions of the microprocessor, but it also allows the engineer to debug
his system by setting breakpoints on various conditions, permits tracing of program flow, and provides substitution memory
which may be used in place of actual target system memory.
ISV-Independent Software Vendor. A vendor, independent from National Semiconductor, who ports or develops software for
Series 32000 components. They in turn sell this software to our customers who are designing Series 32000 based products.
Kernel-This is the name given to the core of the operating system. Other programs are added to the kernel to provide the
features of the operating system. The kernel provides control and synchronization.
Language-A set of characters and symbols and the rules for using them. In our context, it is the "English like" format of the
instructions which are understood by both the programmer and the computer.
Library-High level languages as well as assembly language contain many routines which are used over and over again. To
prevent the programmer from having to write the routine every time it is needed, these routines are stored in libraries to be
referenced each time they are needed. These libraries are also OBJECT files.
Linear Address Space-An address space where addresses start at location zero and proceed in a linear fashion (i.e., with no
holes or breaks) to the upper limit imposed by the total number of bits in a logical address.
Link Base-In the Series 32000, Module Descriptor entry which pOints to a table in memory containing entries which reference
variables or entry points in Modules external to the one presently executing.
Linker-Large programs are generally broken down to component parts and farmed out to several programmers. Each one of
these parts is called a MODULE. Each programmer will develop the module using either high level or assembly language, then
"assemble" assembly language modules or "compile" high level language modules. A programmer tells the linker how to
connect these modules to make the program run. The linker makes these connections, resolves all questions about data
needed by one module, but contained in another, finds all library routines, and cleans up any other loose ends. The output from
the linker is called BINARY file and is the file that will run on the computer.
Logical Address Space-The range of addresses which a programmer can assign in a software program. This range is
determined by the length of the computer's address registers.
LSB-Least Significant Bit. The bit in a string of bits representing the lowest value.
Machine Code-The code that a computer recognizes. Specifies internal register files and operations that directly control the
computer's internal hardware.
Machine Language-The ones and zeros which are "understood" by the machine. This is often called "Binary Code." The
programmer must be able to understand the bit patterns to be able to decipher the language. Each machine has a unique
machine language.
Main Memory-The program and data storage area in a computer system which is physically addressed by the microprocessor
or MMU address lines.
Mantissa-In a floating-point number, this is the fractional component.
Mapping-The process whereby the operating system assigns physical addresses in main memory to the logical addresses
assigned by the software.
Memory-Mapped-Referring to peripheral hardware devices which are addressed as if they were part of the computer's
memory space. They are accessed in the same manner as main memory, i.e., through memory read/write operations.
Microcode-A sequence of primitive instructions that control the internal hardware of a computer. Their execution is initiated by
the decoding of-a software instruction. Microcode is maintained in special storage and often used in place of hardwired logic.
Microcomputer-A computer system whose Central Processing Unit is a Microprocessor. Generally refers to a board-level
product.
Minicomputer-A "box-level" computer with system capabilities generally between that of a microcomputer and a mainframe.
MMU-Memory Management Unit. This is a slave processor in Series 32000 which aids in the implementation of demand-paged
virtual memory. It provides logical to physical address translation and initiates an instruction abort to the CPU when a desired
memory location is not in main memory.
MOD-Mod Register. In the Series 32000, a 16-bit CPU register which holds the address of the Module Descriptor of the
currently executing software module.
Module-An independent subprogram that performs a specific function and is usually part of a task, i.e., part of a larger
program.
Module Descriptor-In the Series 32000, a set of four 32-bit entries found in main memory. Three are currently defined and
point to the static data area, link table, and first instruction of the module it describes. The fourth is reserved.
10-6
Glossary (Continued)
Modularlty-A software concept which provides a means of overcoming natural human limitations for dealing with programming
complexity by specifying the subdivision of large and complex programming tasks into smaller and simpler subprograms, or
modules, each of which performs some well-defined portion of the complete processing task.
MSB-Most Significant Bit. The bit in a string of bits representing the highest value.
NET-Short for NETWORK and describes a number of computers connected to each other via phone or high speed links. A net
is convenient for exchanging common information in the form of "mail" as well as for data exchange.
NMI-Nonmaskable Interrupt. A hardware interrupt which cannot be disabled by software. It is generally the highest priority
interrupt.
Object Code-Output from a compiler or assembler which is itself executable machine code (or is suitable for processing to
produce executable machine code).
Operand-In a computer, a datum which is processed by the CPU. It is referenced by the address part of an instruction.
Operating System-A collection of integrated service routines used by the computer to control the sequence of programs. The
operating system consists of software which controls the execution of computer programs and which may provide storage
assignment, input/output control, scheduling, data management, accounting, debugging, editing, and related services. Their
sophistication varies from small monitor systems, like those used on boards, to the large, complex systems used on main
frames.
Operating System Mode-In this mode, the CPU can execute all instructions in the instruction set, access all bits in the
Processor Status Register, and access any memory location available to the processor.
Operator-In the description of an instruction, it is the action to be performed on operands.
Page Fault-A hardware generated trap used to tell the operating system to bring the missing page in from secondary storage.
Page Swap-The exchange of a page of software in secondary storage with another page located in main memory. The
operating system supervises this operation, which is executed by the CPU and involves external devices such as disk and DMA
controllers.
Page Table-A 1K-byte area in main memory containing 256 entries which describe the location and attributes of all pointer
tables, i.e., a list of pointer table addresses.
Perlpheral-A device which is part of the computer system and operates under the supervision of the CPU. Peripheral devices
are oiten physically separated from the CPU.
Pascal-A high level language designed originally to teach structured programming. It has become popular in the software
community and has been expanded to be a versatile language in industry.
Physical Address-The address presented to main memory, either by the CPU or MMU.
Pointer Table-A 512-byte page located either in main memory or secondary storage containing 128 entries. Each entry
describes an individual page of the software program. Each page of the software program may reside in main memory or in
secondary storage.
Pop-To read a datum from the top of a stack.
PORT-To port an operating system is to cause that particular operating system to operate with a defined hardware package.
GENIX is the NSC version of UNIX which has been ported to SYS32. The operating system for other Series 32000 based
systems will differ in some degree from SYS32 and the NSC GENIX binary will not operate. It is now necessary to modify GENIX
to fit the situation caused by the new hardware. The GENIX SOURCE is used because this is the program that is most readily
understood by the programmer. The source is changed, compiled, and linked to get a new binary for that particular machine.
Primitive Data Type-A data type which can be directly manipulated by the hardware. With Series 32000, these are integers,
floating-point numbers, Booleans, BCD digits, and bit fields.
Procedure-A subprogram which performs a particular function required by a module, i.e., by a larger program; an ordered set
of instructions that have a general or frequent use.
Process-A task.
Program Base-Module Descriptor entry which pOints to the first instruction in the module being described.
Program Counter-CPU register which specifies the logical address of the currently executing instruction.
Protection-The process of restricting a software program's access to certain portions of memory using hardware mechanisms. Typically done at the operating system and page level.
PSR-Processor Status Register. A 16-bit register on Series 32000 CPU's which contains bits used by the software to make
decisions and determine program flow.
Push-to write a datum to the top of a stack.
Quad word-Four words, i.e., 64 bits.
Queue-A First-In-First-Out data storage area, in which the data may be removed at a rate different from that at which it was
stored.
Real Time-The actual time in human terms, related to a process. In a UNIX system, real time is total elapsed time, CPU time is
the percent of time a process is actually in the CPU. Sys time is the time spent in system mode, and user time is the time spent in
user mode.
10-7
Glossary (Continued)
Real Time Operating Systems-An operating system which operates with a known and predictable response time limit; so that
it can control a physical event.
Record-A structured data type with multiple elements, each of which may be of a different data type, e.g., strings, arrays,
bytes, etc.
Register-A temporary storage location, usually in the CPU, which holds digital data.
Relative Address-The number that specifies the difference between the base address and the absolute address.
Relocatable-In reference to software programs, this is code which can be loaded into any location in main memory without
affecting the operation of the program.
Return Address-The address to which a subroutine call, interrupt or trap subroutine will return after it is finished executing.
Routine-A procedure.
Royalty-Royalty is money paid to the inventor for each item of product sold. A good analogy to use is the music business. Any
time a song is used, the songwriter is paid a royalty. Think of UNIX as a song and GENIX or SYSTEM V as special arrangements.
For each shipment of GENIX or SYSTEM V, the customer pays a royalty to NSC who, in turn, pays a royalty to AT&T.
S8-ln the Series 32000 Static Base Register. Points to the start of the static data area for the currently executing module.
Secondary Storage-This is generally slow-access, nonvolatile memory such as a hard-disk which is used to store the pages
of software programs not currently needed by the CPU.
Segmented Address Space-Term used to describe the division of allocatable memory space into blocks of segments of
variable size.
Setup Time-The minimum amount of time that data must be present at an input to ensure data acceptance when the device is
clocked.
Slave Processor-A processor which cooperates with the main microprocessor in executing certain instructions from the
instruction stream. A slave processor generally accelerates certain functions which increases overall system throughput. Examples of slave processors are the FPU and MMU of Series 32000.
Software-Programs or data structures that execute instructions or cause instructions to be executed and that will cause the
computer to do work.
Software License-NSC does not sell software. Rather, we license the right to use our software. A software license is required
for all Series 32000 software. We use the license to protect NSC's interests and to assist in honoring our commitment to AT&T.
The license is also the vehicle which we use to track customers so that updates can be issued in a timely manner.
Software Q/ A-It is the charter of the Quality Assurance people to ensure that when a software product reaches the customer
that it is "bug" free. In the real world, it is impossible to test every combination of functions, so some bugs do get through. The
Q/ A engineer develops test programs which rigorously test the product prior to its introduction to the market place.
SP1-ln the Series 32000, User Stack Pointer. Points to the top of the User Stack and is selected for all stack operations while
in User Mode.
SPO-In the Series 32000, Interrupt Stack Pointer. Points to the top of the interrupt stack. It is used by the operating system
whenever an interrupt or trap occurs.
Stack-A one-dimensional data structure in which values are entered and removed one datum at a time from a location called
the Top-of-Stack. To the programmer, it appears as a block of memory and a variable called the Stack Pointer (which points to
the top of the stack).
Stack Pointer-CPU register which pOints to the top of a stack.
Static Base Register-A 32-bit CPU register which pOints to the beginning of the static data area for the currently executing
module.
String-An array of integers, all of the same length. The integers may be bytes, words, or double words. The integers may be
interpreted in various ways (see ASCII).
Subroutine-A self-contained program which is part of a procedure.
Symmetry-A computer architecture is said to be symmetrical when any instruction can specify any operand length (byte, word
or double word) and make use of any address-data register or memory location while using any addressing mode.
Synchronous-Refers to two or more things made to happen in a system at the same time, by means of a common clock
signal.
Tag-A label appended to some data entry used in a look-up process whereby the desired datum can be identified by its tag.
Task-The highest-level subdivision of a user software program. The largest program entity that a computer's hardware directly
deals with.
TCU-Timing Control Unit. A device used to provide system clocks, bus control signals and bus cycle extension capability for
Series 32000.
Trap-An internally generated interrupt request caused as a direct and immediate result of the encounter of an event.
T·State---One clock period. If the system clock frequency is 10 MHz, one T-State will take 100 ns to complete. Operations
internal and external to the CPU are synchronized to the beginning and middle of the T-States. There are four T-States in a
normal Series 32000 CPU bus cycle.
10-8
Glossary (Continued)
UNIXTM-An operating system developed at Bell Laboratories in the early 1970s. Software programs that run under UNIX are
written in the high-level language C, making them highly portable. UNIX systems do not distinguish user programs from operating system programs in either capability or usage, and they allow users to route the output of one program directly into the input
of another. This operating is unique and is becoming very popular in the microcomputer world.
USENET-A net to which UNIX systems in the United States connect. Some systems in Europe and Australia also use this net
for the purpose of passing information.
User-A software program. The total set of tasks (instructions) that accomplish a desired result. Tasks are managed by the
operating system.
User Mode-Machine state in which the executing procedure has limited use of the instruction set and limited access to
memory and the PSR.
uucp--Software which allows UNIX computers to pass information to other UNIX systems.
Varlable-A parameter that can assume any of a given set of values.
Vector-Byte provided by the ICU (Interrupt Control Unit) which tells the CPU where within the DeSCriptor table the descriptor is
located for the interrupt it has just requested.
Virtual Address-Address generated by the user to the available address space which is translated by the computer and
operating system to a physical address of available memory.
Virtual Memory-The storage space that may be regarded as addressable main storage by the system. The operating system
maps Virtual addresses into physical (main memory) addresses. The size of virtual memory is limited by the method of memory
management employed and by the amount of secondary storage available, not by the actual number of main storage locations,
so that the user does not have to worry about real memory size or allocation.
VMS-This is the operating system designed by Digital Equipment Corporation for their VAX series of computers. The original
Series 32000 software was developed on a VAX which was being controlled by the VMS Operating System.
Wait-State-An additional clock period added to a CPU memory cycle which gives an external memory device additional time to
provide the CPU with data. Also used by bus arbitration circuitry to hold the CPU in an idle state until access to a shared
resource is gained.
Wlnchester-Small, hard-disk media commonly found in personal computers.
Word-A character string or bit string considered as the primary data entity. For historical reasons, a word is a group of 16 bits
in Series 32000 systems.
10-9
!o
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NOTES
NOTES
~National
D Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
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please call (408) 749-7378.
ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar logic • Advanced low Power Schottky. Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions. Peripheral Functions. lSllVlSI Functions. DeSign Guidelines. Packaging
CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides. Active Filters. Amplifiers. Analog Switches. Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital-to-Analog Converters • Sample and Hold • Sensors/Transducers
Successive Approximation Registers/Comparators. Voltage References
DATA COMMUNICATION/LAN/UART DATABOOK-Rev. 1
lAN IEEE 802.3 • High Speed Serial/IBM Data Communications • ISDN Components. UARTs
Modems • Transmission Line Drivers/Receivers
INTERFACE DATABOOK-1988
Transmission Line Drivers/Receivers· Bus Transceivers. Peripheral Power Drivers • Display Drivers
Memory Support. Microprocessor Support. level Translators and Buffers. Frequency SynthesiS • Hi-Rei Interface
INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers
level Translators/Buffers. Display Controllers/Drivers. Memory Support. Dynamic Memory Support
Microprocessor Support. Data Communications Support. Disk Support. Frequency Synthesis
Interface Appendices. Bipolar PROMs. Bipolar and ECl RAMs. 2900 Family/Bipolar Microprocessor
Programmable logic
INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's new book targets some of the most significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evo/ution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.
INTUITIVE IC OP AMPS-1984
Thomas M. Frederiksen's new book, Intuitive Ie Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detailed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, designers, and industry observers who need to
stay abreast of the computer industry.
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LINEAR 1 DATABOOK-1988
Voltage Regulators • Operational Amplifiers. Buffers. Voltage Comparators. Instrumentation Amplifiers. Surface Mount
LINEAR 2 DATABOOK-1988
Active Filters. Analog Switches/Multiplexers. Analog-to-Digital. Digital-to-Analog. Sample and Hold
Sensors. Voltage References. Surface Mount
LINEAR 3 DATABOOK-1988
Audio Circuits. Radio Circuits. Video Circuits. Motion Control • Special Functions • Surface Mount
LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators • Voltage Regulators. Voltage References. Converters. Analog Switches
Sample and Hold. Sensors. Filters. Building Blocks. Motor Controllers. Consumer Circuits
Telecommunications Circuits. Speech. Special Analog Functions
LS/S/TTL DATABOOK-1987
Introduction to Bipolar logic. low Power Schottky. Schottky. TTL • low Power
MASS STORAGE HANDBOOK-Rev. 2
Winchester Disk Preamplifiers. Winchester Disk Servo Control. Winchester Disk Pulse Detectors
Winchester Disk Data Separators/Synchronizers and ENDECs • Winchester Disk Data Controller
SCSI Bus Interface Circuits. Floppy Disk Controllers
MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control. Error Checking and Correction • Microprocessor Interface and Applications
Memory Drivers and Support
NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs
SERIES 32000 DATABOOK-1986
Introduction. CPU-Central Processing Unit. Slave Processors. Peripherals. Data Communications and LAN's
Disk Control and Interface • DRAM Interface • Development Tools. Software Support • Application Notes
RANDOM ACCESS MEMORY DATABOOK-1987
StatiC RAMs. TTL RAMs. TTL FIFOs • ECl RAMs
RELIABILITY HANDBOOK-1986
Reliability and the Die. Internal Construction. Finished Package. MIL-STD-883 • MIL-M-3851 0
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-3851 0 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-3851 0 and DESC Drawing Cross Listing
TELECOMMUNICATIONS-1987
Line Card Components. Integrated Services Digital Network Components. Modems
Analog Telephone Components. Application Notes
THE SWITCHED-CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters. National's Switched-Capacitor Filters • Designing with Switched-Capacitor Filters
Application Circuits. Filter Design Program. Nomographs and Tables
TRANSISTOR DATABOOK-1982
NPN Transistors. PNP Transistors. Junction Field Effect Transistors. Selection Guides. Pro Electron Series
Consumer Series • NAiNB/NR Series • Process Characteristics Double-Diffused Epitaxial Transistors
Process Characteristics Power Transistors. Process Characteristics JFETs • JFET Applications Notes
VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures. Heat Flow & Thermal Resistance • Selection of Commercial Heat Sink
Custom Heat Sink Design. Applications Circuits and Descriptive Information • Power Supply Design
Data Sheets
48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48-Series Microcomputers. The 48-Serles Single-Chip System. The 48-Series Instruction Set
Expanding the 48-Series Microcomputers. Applications for the 48-Series • Development Support
Analog I/O Components. Communications Components. Digital I/O Components • Memory Components
Peripheral Control Components
~ National
D
Semiconductor
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