1988_OEM_Boards_and_Systems_Handbook 1988 OEM Boards And Systems Handbook

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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrollers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
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OEM BOARDS
AND SYSTEMS
HANDBOOK

1988

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
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Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH,
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Inboard, Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
inteligent Identifier, inteligent Programming, Intellec, Intellink, iOSP,
iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, library
Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME,
MULTIBUS, MULTICHANNEL, MULTIMODULE, MultiSERVER, ONCE,
OpenNET, OTP, PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware,
QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80, RUPI,
Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the
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numerical suffix, 4-SITE.
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*MULTIBUS is a patented Intel bus.
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Table of Contents
Alphanumeric Index ................................. . . . . . . . . . . . . . . . . . . . . ..
CHAPTER 1
Integrated Microcomputer Systems
FACT SHEETS
System 310 AP ..................................... ......................
Custom Systems Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
XENIX System 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRMX System 320 .........................................................
Financial System 320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System 31 OAP Upgrade ..................................... : . . . . . . . . . . . . . .
System 310, Model 35 .....................................................
CHAPTER 2
System Software
DATA SHEETS
iSDM System Debug Monitor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRMX 86 Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FACT SHEETS
iRMK Version 1.1 Real-Time Kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRMX 286 REL 2.0 Operating System .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iBASE-Base Application Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRMX Languages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Office Productivity Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . .
High Performance MultiSERVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
XENIX 286 Application and Development Software. . . . . . . . . . . . . . . . . . . . . .. . . . . .
APPLICATION NOTES
AP-405 Software Migration from iRMX 86 to 286 ..............................
CHAPTER 3
Single Board Computers
DATA SHEETS
iSBC 80/10B Single Board Computer........................................
iSBC 80/20-4 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 80/24A Single Board Computer........................................
iSBC 80/30 Single Board Computer .........................................
iSBC 88/05A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/14 and 86/30 Single Board Computer...............................
iSBC 86/35 Single Board Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 88/25 Single Board Computer .........................................
iSBC 88/40A Measurement and Control Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 186/03A Single Board Computer.......................................
iSBC 286/10A Single Board Computer.......................................
iSBC 286/12,286/14,286/16 Single Board Computers........................
iSBC 386/20 Single Board Computer Starter Kits. . . . . . .. . . . . . . . . . . . . . . . . . . . . ..
iSBC 386/21/22/24/28 Series and 386/31/32/34/38 Single Board Computers. ..
CHAPTER 4
MULTIBUS " Single Board Computers
DATA SHEETS
iSBC 186/100 MULTIBUS" Single Board Computer...........................
iSBC 286/100A MULTIBUS" Single Board Computer..... .....................
FACT SHEETS
MULTIBUS " 386 CPU Boards.. .. . . .. . .. .. . . .. . . .. .. .. .. .. .. .. . .. ..... .. . ..

1-1
1-3
1-5
1-7
1-9
1-11
1-13

2-1
2-5
2-24
2-30
2-42
2-44
2-49
2-51
2-53
2-55

3-1
3-8
3-16
3-26
3-35
3-45
3-54
3-63
3-72
3-81
3-92
3-102
3-114
3-125

4-1
4-10
4-19

Table of Contents (Continued)
CHAPTER 5
High Speed Math Boards
DATA SHEETS
. iSBC 337A and iSBC 337 MULTIMODULE Numeric Data Processor.. .. . . . . . .. . .

5-1

CHAPTER 6
Memory Expansion Boards
DATA SHEET
iSBC 012B RAM Memory Boards............................................
iSBC 012C ECC RAM Board. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 012CX, 010CX and 020CX iLBX RAM Boards ........ " . . . . . . . . . .. .. . . . . .
iSBC 012EX, 010EX, 020EX, 040EX High Performance HAM Boards.............
iSBC 028A1056A RAM Memory Boards ................................... , . .
iSBC 304 128K Byte RAM MULTIMODULE Board. . . . . . . . . .. . . . . .. . . . . . . . . . . . .
iSBC 300A 32K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 301 4K Byte RAM MULTIMODULE Board ........................... . . . .
iSaC 302 8K Byte RAM MULTIMODULE Board ...............................
iSBC 314 512K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 341 28-Pin MULTIMODULE EPROM.. .... .. . .. . .... .. .. .. .. . .. .. .. . .. ..

6-1
6-3
6-7
6-12
6-16
6-19
6-19
6-22
6-25
6-27
6-31

CHAPTER 7
MULTIBUS II Memory Expansion Boards
DATA SHEETS
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules..........
iSBC MEM/312, 310, 320, 340 Cache-BasedMULTIBUS II RAM Boards.........
iSBC MEM/601 MULTIBUS II Universal Site Memory Expansion Board. . . . . . . . . . .

7-1
7-5
7-9

CHAPTER8.
Peripheral Controllers
DATA SHEETS
iSBC 186/224A MULTIBUS II High Performance Multi-Peripheral Controller
Subsystem ................. " . . . . . . . . . . .. . ... . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 208 Flexible Diskette Controller . .. . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. .. . .
iSBC 214 Peripheral Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 215 Generic Winchester Controller ................. " ............ ; . . . . .
iSBC 220 SMD Disk Controller ............ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBX 217C %-inch Tape Drive Interface MULTIMODULE Board. . . . . . . . . . . . . . . . .
iSBX 218A Flexible Disk Controller ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1
8-5
8-9
8-13
8-19
8-23
8-26

CHAPTER 9
Graphics
DATA SHEETS
iSBC 186/78A Intelligent Video Graphics Subsystem ..........................
iSBX 270 Alpha-Numeric Display Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-1
. 9-9

CHAPTER 10
Digital and Analog I/O Expansion
DATA SHEETS
iSBC 517 Combination 1/0 Expansion Board..................................
iSBX 519 Programmable 1/0 Expansion Board ...................... ,.........
iSBX 5561/0 Optically Isolated 1/0 Board ..... , . .. . .. . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 569 Intelligeht Digital Control.. . . . . .. . .. . . .. .. . . . . . . . . . .. . . . . . . .. . . . . ..
iSBX 311 Analog Input MULTIMODULE Board................................
iSBX 328 Analog Output MULTIMODULE Board...............................
iSBX 350 Parallel 110 MULTIMODULE Board.. . . . . . . . . . . . . .. . . . . . . . .. . .. . . . ..
iSBX 488 GPIB MULTIMODULE Board. . . . . .. . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . ..
vi

10-1
10-5
10-9
10-12
10-18
10-22
10-26
10-30

Table of Contents (Continued)
CHAPTER 11
Local Area Network Boards and Software
DATA SHEETS
'
iRMX Networking Software REL 2.0 ........................................ .
MAP-NET Communications Software ....................................... .
IDCM 911-1 Intellink Ethernet Cluster Module ................................ .
INA 960/961 REL 2.0 Transport and Network Software ....................... .
iSBC 186/51 Communicating Computer .•....................................
iSBC 552Aand iSXM 552A IEEE 802.3 Compatible Communications Engine
Products .............................................................. .
iSBC MAP Communications Engine ......................................... .
iSBX 586 Ethernet Data Link Engine ........................................ .
iSBC 186/530 MULTIBUS " Ethernet Communication Engine, ;•..................
FACT SHEETS
,,' '
XENIX-NET Networking OpenNET Product Family .... .:: ,,(,::: ............ , ..... .
OpenNET Personal Computer Link 2 .................. ;'.' ..................... .
MAP Networking Software ......................... /,; "'~ '................•....
MAP Network Development Starter Kits ............... ; ~< ................... .
VAXIVMS Networking Software .............. ~ ....... , ..................... .

11-1
11-9 '
11-15
11-17
11-27
11-39
11-48
11-57
11-62
11-71
11-73
11-77
11-83
11-88

CHAPTER 12
Serial Communication Boards and Software
DATA SHEETS
iSBC 88/45 Advanced Data Communications Processor Board ................ .
iSBC 188/56 Advanced Data Communications Processor ................... .
iSBC 534 Four Channel Communication Expansion Board ..................... .
iSBC 544 Intelligent Communication Controller ............................... .
iSBC 561 SOEMI Controller Board .......................................... .
iSBX 351 Serial 110 Communication Board .......... ; ....................... .
iSBX 354 Dual Channel Serial 1/0 MULTIMODULE Board ..................... .
FACT SHEET
'
FAST PATH 9750B Control Unit .................•...........................
VPM 188 Async/Bisync Communication Subsystem ...................... I •
3720 SNA Communication $ubsystem ......................•.............. : .

12-1
12-10
12-19
12-24
12-33
12-38
,12-44
12-49
12-51
12-53

CHAPTER 13
MULTIBUS " Serial Communication Boards
DATA SHEET
iSBC 186/410 MULTIBUS" Serial Communications Computer ................. .

13-1

CHAPTER 14
MULTIBUS " System Development and Support Softw,are
DATA SHEETS
iSBC CSM/001 Central Services Module .................................... . 14-1
iSBC LNK/001 MULTIBUS " to MULTIBUS I Link Board ......... ; ; ............ . 14-6
FACT SHEETS
iRMX MULTIBUS " Modules Development Platform ........................... . 14-11

CHAPTER 15
System Packaging and Power Supplies
DATA SHEET
iCS 80 Industrial Chassis Kit 635, Kit 640 .................................... . 15-1
iSBC 604/614 Modular Cardcage Assemblies .......................... ~ ..... . 15-6
iSBC 608/618 Cardcages ...............................•.................. 15-9
iSBC 640 Power Supply ................................................... . 15-13
vii

Table of Contents (Continued)
iSBC 661 System Chassis .................................................. 15-16
FACT SHEETS
OEM Chassis Model 93, 94 . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . • . . .. . . . . . .. . . . . .. 15-19

CHAPTER 16
MULTIBUS II System Packaging and Power Supplies
DATA SHEETS
iSBC PKG/606, PKG/609 MU'-TIBUS II Cardcage Assemblies. . . . . . . . . . .. . . . . . .
iSBC PKG 902, PKG 903 MULTIBUS II iLBX Backplanes . ~ . . . . . . . . . . . . .. . . . .. • .
. . '
.
FACT SHEETS
iSYP/500 MULTIBUS II SystemChassis .................................•...

16-1
16-5
16-8

CHAPTER 17
Distributed Control Modules
DATA SHEETS
iSBX 344A BITBUS Intelligent MULTIMODULE Board. . . . . . . .. . . . . . . . . . . . . . . . . .
iPCX 344A BITBUS IBM PC Interface Board..................................
iRCB 44/10A BITBUS Digital 1/0 Remote Controller Board.....................
iRCB 44/20A BITBUS Analog 1/0 Controller Board. . . . . . . . . . .. . . . . .. . . . . • . . • ..
DCS 100 BITBUS Toolbox ................................................. '.
DCS 110, BITWARE DCS 120 Programmers Support Package ..................
8051 Software Packages .................................................. ,
ICE 5100/044 In-Circuit Emulator...........................................
iDCX 51 Distributed Control Executive. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. ..
8044 BITBUS Enhanced Microcontroller .....................................
8044AH/8344AH/8744AH High Performance 8-Bit Microcontrollers .. . . . . . . . . . ..
FACT SHEET
BITBUS Software Development Environment ................ , ................
iRCX 910/920 Digitall Analog Signal Conditioning Isolation
and Termination Panels ..................................................

17-1
17-9
17-15
17-24
17-32
17-39
17-44
17-52
17-60
17-68
17-89
17-115
17-120

CHAPTER 18
MULTIBUS I Architecture
DATA SHEETS
MULTIBUSSystemBus .................................................... 18-1
iLBX Execution Bus................................................ ....... 18-13
iSBX 1/0 Expansion Bus .. : ............................ :............ . . . . . .. 18-22

CHAPTER 19
MULTIBUS II Architecture
DATA SHEETS
MULTIBUS II LBX II Local Bus Extension.....................................
MULTIBUS II iPSB Parallel System Bus. .. .. . .. . .. . . .. .. .. . .. . . • .. .. .. .. .. . ..
82389 Message Passing Coprocessor-A MULTIBUS II Bus Controller. ; . . . . . . . ..
TECHNICAL BRIEFS .
.
Enhancing System Performance with the MULTIBUS II Architecture .............
Increasing System Reliability with MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . ..
Geographic Addressing in the MULTIBUS II Architecture . . . . . . . . .. . . . . . . . . . . . ..
Message Passing in the MULTIBUS II Architecture ............................
Reducing80ard and System Costs with MULTIBUS II. Architecture ..............

19-1
19-7
19-21
19-42
19-46
19-51
19-57
19-61

CHAPTER 20
Service and Support
DATA SHEETS
Insite User's Program Library. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
iRUG Description .........................................................
viii

20-1
20-5

Table of Contents (Continued)
iMBX 100/110/120/130 MULTIBUS Exchange Hardware Subscription Service ...
Customer Training .......... , ............................................. : .
Software Support Service ....................................................
Systems Engineering ....... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hardware Maintenance .......'... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Network Services .........,..................,..............................

20-6
20-8
20-1 0
20-12
20-14
20-16

Alphanumeric Index
3720 SNA Communication Subsystem. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . .. 12-53
8044 BITBUS Enhanced Microcontroller ............................................ 17-68
8044AH/8344AH/8744AH High Performance 8-Bit Microcontrollers.................... 17-89
8051 Software Packages. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 17-44
82389 Message Passing Coprocessor-A MULTIBUS II Bus Controller. . .. . . . . . . . . . . . .. 19-21
AP-405 Software Migration from iRMX 86 to 286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 2-55
BITBUS Software Development Environment: ....................................... 17-115
Custom Systems Integration ......................................................
1-3
Customer Training ............................................................... 20-8
DCS 100 BITBUS Toolbox ................................ ~........................ 17-32
DCS 110, BITWARE DCS 120 Programmers Support Package. . . . . . . . . . . . . . . . . . . . . . . .. 17-39
Enhancing System Performance with the MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . .. 19-42
Financial System 320. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
1-9
FASTPATH 9750B Control Unit.................................................... 12-49
Geographic Addressing in the MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19-51
Hardware Maintenance. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20-14
High Performance MultiSERVER .................................................. , 2-51
iBASE-Base Application Software Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
iCS 80 Industrial Chassis Kit 635, Kit 640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
iDCX 51 Distributed Control Executive ........ ~ .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .... 17-60
iLBX Execution Bus ........................................ ~....... .............. 18-13
iMBX 100/110/120/130 MULTIBUS Exchange Hardware Subscription Service. . . . . . . . . . 20-6
iPCX 344A BITBUS IBM PC Interface Board........................... ..............
17-9
iRCB 44/10A BITBUS Digital I/O Remote Controller Board.............. .............. 17-15
iRCB 44120A BITBUS Analog I/O Controller Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17-24
iRCX 910/920 Digital/Analog Signal Conditioning Isolation-and Termination Panels ..... 17-120
iRMK Version 1.1 Real-Time Kernel. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
iRMX Languages ................................................................ 2-44
iRMX MULTIBUS II Modules Development Platform.. .. .. .. . .. .. . .. .. .. .. . . .. . . .. . ... 14-11
iRMX Networking Software REL 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
iRMX System 320 . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7
iRMX 286 REL 2.0 Operating System ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
iRMX 86 Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . .
2-5
iRUG Description ..................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
iSBC CSM/001 Central Services Module............................................ 14-1
iSBC LNK/001 MULTIBUS II to MULTIBUS I Link Board..............................
14~6
iSBC MAP Communications Engine ................................................ 11-48
iSBC MEM/312, 310, 320, 340 Cache-Based MULTIBUS II RAM Boards................
7-5
iSBC MEM/601 MULTIBUS II Universal Site Memory Expansion Board .................
7-9
iSBC MM01, MM02, MM04, MM08 High Performance Memory Modules ............ , . . . .
.7-1
iSBC PKG 902, PKG 903 MULTIBUS II iLBX Backplanes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-5
iSBC PKG/606, PKG/609 MULTIBUS II Cardcage Assemblies. . . . . . . . . . . . . . . . . . . . . . . . .
16-1
iSBC 012B RAM Memory Boards ......................................... ;........
6-1
iSBC 012C ECC RAM Board......................................................
6-3
iSBC 0 12CX, 01 OCX and 020CX iLBX RAM Boards ............................... ; . . .
6-7
iSBC 012EX, 01 OEX, 020EX, 040EX High Performance RAM Boards ...................
6-12
iSBC 028A1056A RAM Memory Boards. . . . . . . . . . . . . .. . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . 6-16
iSBC 186/100 MULTIBUS II Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
iSBC 186/224A MULTIBUS II High Performance Multi-Peripheral Controller Subsystem. ..
8-1
iSBC 186/410 MULTIBUS II Serial Communications Computer. . . . . . . . . . . . . . . . . . . . . . . . .
13-1
iSBC 186/51 Communicating Computer ........ ,................................... 11-27
iSBC 186/78A Intelligent Video Graphics Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-1
iSBC 186/03A Single Board Computer ............................................. 3-81
iSBC 186/530 MULTIBUS II Ethernet Communication Engine.......................... 11-62

Alphanumeric Index (Continued)
iSBC 188/56 Advanced Data Communications Processor. . . . . . . . . . . . . . . . . . . . . . . . .. 12-10
8-5
iSBC 208 Flexible Diskette Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 214 Peripheral Controller ....................................................
8-9
iSBC 215 Generic Winchester Controller. . . . .. . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 8-13
iSBC 220 SMD Disk Controller. . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . .. . . . . . 8-19
iSBC 286/1 OOA MULTIBUS II Single Board Computer .................. , . . . . . . . . . . . . . 4-10
iSBC 286/1 OA Single Board Computer ............................................. 3-92
iSBC 286/12,286/14,286/16 Single Board Computers............. .................. 3-102
iSBC 300A 32K Byte RAM MULTIMODULE Board ................................... 6-19
iSBC 301 4K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
iSBC 302 8K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
iSBC 304 128K Byte RAM MULTIMODULE Board. . .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . 6-19
iSBC 314 512K Byte RAM MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
iSBC 337A and iSBC 337 MULTIMODULE Numeric Data Processor. . .. . . .. . . . . . .. . . . . .
5-1
iSBC 341 28-Pin MULTIMODULE EPROM .......................................... 6-31
iSBC 386/20 Single Board Computer Starter Kits .................. ... .. .. . . . . . . . . . .. 3-114
iSBC 386/21/22/24/28 Series and 386/31/32/34/38 Single Board Computers......... 3-125
iSBC 517 Combination 1/0 Expansion Board........................................ .10-1
iSBC 534 Four Channel Communication Expansion Board .................. , . . . . . . . ... 12-19
iSBC 544 Intelligent Communication Controller...................................... 12-24
iSBC 552A and iSXM 552A IEEE 802.3 Compatible Communications Engine Products. . .. 11-39
iSBC 561 SOEMI Controller Board ................................................. 12-33
iSBC 569 Intelligent Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-12
iSBC604/614 Modular Cardcage Assemblies ... ,................................... 15-6
iSBC 608/618 Cardcages . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
iSBC 640 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-13
iSBC 661 System Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-16
iSBC 80/10B Single Board Computer...............................................
3-1
iSBC 80/20-4 Single Board Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
iSBC 80/24A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . .. . . . . . 3-16
iSBC 80/30 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
iSBC 86/14 and 86/30 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45
iSBC 86/35 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
iSBC 88/45 Advanced Data Communications Processor Board........................
12-1
iSBC 88/05A Single Board Computer ........................ , . . . . . . . . . . . . . . . . . . . . . . 3~35
iSBC 88/25 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
is.BC 88/40A Measurement and Control Computer................................... 3-72
iSBX 1/0 Expansion Bus........... ............................................... 18-22
iSBX 217C 1,4-inch Tape Drive Interface MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . 8-23
iSBX 218A Flexible Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26
iSBX 270 Alpha-Numeric Display Controller .........................................
9-9
iSBX 311 Analog Input MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-18
iSBX 328 Analog Output MULTIMODULE Board ......................... , . . . . .. . . . .. 10-22
iSBX 344A BITBUS Intelligent MULTIMODULE Board................................
17-1
iSBX 350 Parallel 110 MULTIMODULE Board. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-26
iSBX 351 Serial 110 Communication Board ................ : . . . . . . . . . . . . . . . . . . . . . . . .. 12-38
iSBX 354 Dual Channel Serial 1/0 MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-44
iSBX 488 GPIB MULTIMODULE Board ..............•.............................. 10-30
iSBX 519 Programmable 110 Expansion Board.......................................
10-5
iSBX 5561/0 Optically Isolated 1/0 Board...........................................
10-9
iSBX 586 Ethernet Data Link Engine. .. .. . .. .. .. .. . .. .. .. .. .. . .. .... .. . .. .. .. .. .. .... 11-57
iSDM System Debug !VIonitor ........................................... ; . . . . . . . . . .
2-1
iSYP/500 MULTIBUS II System Chassis............................................ 16-8
Increasing System Reliability with MULTIBUS II Architecture. . . . . . . . . . .. . . . . . . .. . . . . . .. 19-46
xi

Alphanumeric Index (Continued)
Insite User's Program Library.. . .. . .. . .. .. .. . ... .. . .. . ... . .•. . .. . .•. .. . .. .. . . . .. .. . .
ICE 5100/044 In-Circuit Emulator. . .. . .•. .. . .• ..•. .•. . . .. . ... ... . .. .. . .. . ... ... ....
IDCM 911-1 Intellink Ethernet Cluster Module .......................................
INA 960/961 REL 2.0 Transport and Network Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Message Passing in the MULTI BUS II Architecture .......................... ; • . . . . . ..
MAP Network Development Starter Kits. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MAP Networking Software .........................'. • . . • . . . . . . . . . . . . . . . . . . • . . . .. .•
MAP-NET Communications Software. . . . . . . . . • • . . . . . . . . . . . . . . • . . . . . • . . .. . . . . . . . . . . .
MULTIBUS II iPSB Parallel System Bus ..•....•..............•........... ~ ........ : .
MULTIBUS II LBX II Local Bus Extension ... d • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
MULTIBUS 11386 CPU Boards. . . . . . . .. . . . . . . . •. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULTIBUSSystem Bus .......•......•....•..•........ ,.....•... '..................
Network Services ......•..........•................ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Office Productivity Tools ...... ; ....•. ;. . . . . . • • . . . . .. . . . . . • . . • . .. . . • . . . . . . . . . . . . . . .
OpenNET Personal Computer Link 2 ....................................... . . . . . . ..
OEM Chassis Model 93, 94 ............................................. ;.........
Reducing Board and System Costs with MULTI BUS II Architecture. . . . . . . . . . . • . . . . . . . ..
Software Support Service .......•..•.... '. . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . ..
System 310 AP ..................... ,............................................
System 310, Model 35 . . . . ... . .. . .. . . . .. .... . .. . . . . . . .. . . . .. . .. . .. . .. . . ... .. . . . . . .
System 31 OAP Upgrade ..........................................................
Systems Engineering. . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
VAXIVMS Networking Software ........................................ '. . . . . . . . . ..
VPM 188 Async/BiSync Communication Subsystem. . . . . . . . • . . . . . . . . . • . .. • . . . . . .. . . ..
XENIX System 320 .................................. :............................
XENIX 286 Application and Development Software •.........•............•.......... '.
XENIX-NETNetworking OpenNET Product Family ............................ '. . . . . ..

xii

20-1
17-52
11-15
11-17
19-57
11-83
11-77
11-9
19-7
19-1
4-19
18-1
20~ 16
2-49
11-73
15-19
19-61
20-10
1-1
1-13
1-11
20-12
11-88
12-51
1-5
2-53
11-71

CUSTOMER SUPPORT
CUSTOMER SUPPORT
Customer Support is Intel's complete support service that provides Intel customers with hardware support, software
support, customer training, and consulting services. For more information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major factors in
determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect,
Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices
providing hardware repair services, software support services, customer training classes, and consulting services.

HARDWARE SUPPORT SERVICES
Intel is committed to providing an international service support package through a wide variety of service offerings
available from Intel Hardware Support.

SOFTWARE SUPPORT SERVICES
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information
Phone Service), updates and SUbscription service (product-specific troubleshooting guides and COMMENTS Magazine). Basic support includes updates and the subscription service. Contracts are sold in environments which represent product groupings (i.e., iRMX environment).

CONSULTING SERVICES
Intel provides field systems engineering services for any phase of your development or support effort. You can use
our systems engineers in a variety of ways ranging from assistance in using a new product, developing an application,
personalizing training, and customizing or tailoring an Intel product to providing technical and management consulting. Systems Engineers are well versed in technical areas such as microcommunications, real-time applications,
embedded microcontrollers, and network services. You know your application needs; we know our products. Working together we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. In
just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.
For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our
workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include:
. architecture and assembly language, programming and operating systems, bitbus and LAN applications.

xiii

Integrated Microcomputer
Systems

SYSTEM 310 liP
The. System 310 AP is faster than many minicomputers. Powerful dedicated processors for
communications and mass storage inputJoutput co'ntrol allow the 8 MHz 80286 CPU to concentrate
on application software. The System 310 AP is open, which means you can upgrade performance
and/or functionality in the future without purchasing a new system. The open system design protects
your investment from becoming obsolete .. Open systems design also means easy system
customization with Intel and third-party add-in Multibus boards.

I'EIITIJRES
• 80286 Based System
• Open System MULTIBUS(!) architecture for
upgradeability and growth
• XENIX* Operating System
• iRMX(!) Operating System

• OpenNE'I"" Local Area Networking
• Total hardware and software support from
Intel's worldwide customer support
organization

Xi':NI.\ is a Iradt'mark of Microsnft.
Inll'[ Cuqltlratinn lls:mml'lI no n'Npllnsihllil~' fur tht' USI.' of an~ ('il'('ullr~ ntht'r than rjrruitr~' t'mbodied in an Intel product.
im~llIl'd. [nFormallnn ('omaml'd ht'I'l'in suPt'rSt'c1l~ pn'\itJusl~ puhhshl'd spt'rlffraUnns un tht'St' dr\irt's from Intrl.

1-1

~tl

uther cirruil patrnt Ucenses are

Septrmbrr. ]987
Ordt'r :'\umber: 270129·00-1

SI'STEM 310 AP-AN OPEN SI'STEM

IRM:P OPERATING SI'STEM

The Intel System 310 AP is based on the MULTIBUS
architecture. (IEEE 796) industry standard system bus
supported by over 200 vendors providing over 2000 ,
compatible products.
'

The iRMX operating system delivers real-time performance. Designed to manage and extend the resources of
the System 310 AP. this multitasking operating system
, provides configurable resources ranging from interrupt
management and standard device drivers'to data file
The System 310 AP is an 80286 based open system
maintenance commands for human interface and program
development. A wide range of popular industry standard
designed with expansion in mind. The system can be
high-level languages are supported for application
expanded to accommodate up to 9MB of parity-checked
RAM. all accessible with ,no wait states across MULTIBUS's development. The iRMX facilities also include powerful
Local Bus Extension (LBX",). For terminai communications. utilities for easy. interactive configuration and debugging.
the systems can be expimded to a total of 18 RS232 serial
OpeaNEr-STANDARD IN NETtfORIlING
ports.
Intel supports and drives local area networking standards
The System 310 AP supports 20MB-140MB of Winchester
and technology for microsystems and microdisk storage. Mass storage can be expanded to 560MB
communications industries. The OpenNET Product family
using the 311 Peripheral Subsystem. The 310 AP also
adheres to the International Standards Organization (ISO)
supports,a 320KB 5 ~ , noppy drive and a 60MB
and the seven layer Open Systems Interconnect (OSI)
streaming tape cartridge .drive.
'
model. Only complete products that conform to this 1I)0dei
and are based on open and public standards carry the
XENIX OPERATINGSI'STEM
OpenNET name.
Intel XENIX is the highest performance Xenix available.
XENIX. UNIX and DOS applications can be ported quickly . INTEL SERVICE AND SIJProRT
and all system elements are user configurable. Over 200
The System 310 AP Is backed by Intel's worldwide service
utilities support a rich Open System environment,
and support organization. Total hardware and software
support is available. including a hotllne number for when
, you need help fast.
'

Jiilii.ii-i.,,""
SYSTEMIMDDELS
Mlcl1IpracDlor

310 AP-17 310 ANt 310AP-41 310 AP-4Z 310 AP-88 310 AP-B2 310AP-141 310 AP-14Z 310AP-143 310 AP-I45 310AP-l.
80286
80288
80288
80286
80286
80286
80286
80286
80286
80286
80286

Nume~c

Copl1lClllor
RAM Mamory
Floppy
MlaStalllla
Tapa Backup
SerlallJO Ports
Parallal Ports
OpanNET

8 MHz
80287
1MB
3BOKB
20MB
NA
2
1

8 MHz
80287
1MB
360KB
40MB
NA
6
1

8 MHz
80287
1MB
360KS
40MB
NA
10
1

8 MHz
80287
2MB
360KB
60MB
60MB
10
1

8 MHz
80287
1MB
360KB
40MB
60MB
10
1
"

ENJ'lRONMENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

8 MHz
80287
2MB
360K8
85MB
60MB
14
1

8 MHz
80287
1MB
360KB
140MB
60MB
2
1

Yes

8 MHz
80287
2MB
360KB
140MB
60MB
10
1

8 MHz
80287
2MB

36DK8
140MB
60MB
14
1

8MHt
80287
2MB
360KS
140MB
60MB
10
1

Yes

8 MHz
80287
2MB
360KB
140MB
60MB
18
1

DIMENSIONS
10°C to 35°C
260C maximum
20% to 70% noncondensing
Sea level to 8.000 feet

Height
Width
Depth
Weight

6Y2 •

17'
22'
Approx. 55 Ibs

REGIJLA'I'lONS

ORDERING INFORMATION

Meets or exceeds the following requirements:
Safety
US
ULI14
Canada
CSA C22.2
EMIIRFI
LIS arid Canada
FCC Docket 20780-Class A

For more information or the number of your nearest sales
office call 800·548-4725 (good in the U.S. and Canada).

ELECTRICAL
DC Power Output
AC Power Input

360 watt maximum
88-132 VAC or 180-264 VAC.
47-63 Hz (user selectable)

1-2

UNITED STATES, Intel Corporation
3065 Bowers Ave .. Santa Clara. CA 95051
Tel: (408) 987-8080

Custom
Systems
Integration
Factory

~ I~1tegrnted

Custom
, Systems
Solutipns

• Integrated Systems Which Fit
Your Application Requirements
Exactly
• Manufactured from Mutually
Developed Specifications
• Complete Hardware, Firmware
and Diagnostics Development
• Volume Manufacturing Pr~cess
• Tailored Service Through Intel
Customer Support Operation

1-3

280404-001

Intel Factory Resource

DiJK:m.ery, configuration and quote.
Complete the design configurator on the
following pages. Contact your Intel sales
representative for assistance (non-disclosure
available on request).
Mail configurator to your locallntel sales
representative or send to:

Custom Systems Integration will assign an
engineering/manufacturing team to develop
and deliver your custom product.
We listen and respond to your unique
specification requirements, from special
environmentals to other MULTIBUS@
compatible peripherals
and boards.
Intel
Custom systems are
Custom
manufactured under the
Systems
same rigorous manufacturIntegration
ing process and quality
Affords
standatdsas Intel's widely
Unique
acclaimed standard
Added
MULTIBUS systems and
board products.
Value ...
Intel's volume manufacturing facilities mean
product is available when you need it.
Service support programs are tailorable to
your unique requirements through Intel's'
Customer Support Operation.

Intel Corporation
Custom Systems Integration
5200 NE Elam Young Parkway
Hillsboro. Oregon 97124
Mail Stop: HF2-61
Atm: Jackie Randall '
or call (503) 696-7664

Three
Easy
Steps
to your
Custom
Systems
Success ...

One oOntel's custom
systems marketing representatives will call to review with you the configration and delivery details.
Intel will then deliver a
quote specifying per unit price, nonrecurring engineering costs, and delivery
, estimates based on volume.

Detaned product specification and
contract. Intel will work closely with you to
develop a detailed product specification for
mutual signoff, define contractual terms
and conditions, and contract signoff.

3:'

Ordering and delivery. Intel will assign
a project team and set manufacturing ,
schedules. A prototype will be made available for approval and final signing of product specification prior to volume shipments.
Intel will meet with you periodically for
project review.

1-4

XENIX SYSTEM 320
Intel combines the power of its high performance 386·based System 320. the industry standard
XENIX multiuser multi·tasking operating system. complete network service. software. and
comprehensive customer support capabilities to deliver. install and maintain a complete system. The
result is the XENIX System 320. giving you the performance and capabilities of a minicomputer at
less than half the cost. The system is especially suited for office applications requiring multiple users
and networking of pes and terminals.

XENIX SYSTEM 320 E'EATIJRES
• 80386 Based System
• XENIX Operating System
• Open System Architecture

• OpenNE'I"" Local Area Networking
• Complete Installation. Service and Support·
• Range of Configurations

inter------·XENIX and MS DOS are trademarks of Microsoft Corporation.
Intel Corporalion assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied. Information contained herein supersedes previously published specifications on these devices from [ntel.

1-5

,\u~ust. 1987
Order :-iumtK'r; 2il()73(H}Ol

XENIX OPERATING SYSTEM
Intel XENIX is the highest performance Xenix available.
XENIX, UNIX'" and DOS applications can be ported quickly
and all system elements are user configurable. Over 200
utilities support a rich Open System environment.
Intel XENIX supports a wide range of system software and
hardware options unsurpassed by any other XEN IX
implementation. A menu-driven installation utility and
other installation utilities ensure,that the user can build
exactly what is required, interactively.

SYSTEM 3Z6-AN OPEN SYSTEM
The XENIX System 320 is based on the MULTIBUSTII
architecture, (IEEE 796) industry standard system bus
supported by over 200 vendors providing over 2000
compatible products and the XENIX Operating System.
Intel XENIX supports a broad range of application and
system software. Programs for business data processing,
scientific and engineering applications, communications,
database management, word processing, graphics and
many more are available from Intel and third-party
suppliers. A complete set of programming languages are
also available, in addition to the C compiler included with
the system~

Ope.NETTII.-THE STANDARD IN
NETWORIUNG
Intel XENIX System 320 supports OpenNET, which
adheres to the International Standards Organization (ISO)
and. the seven-layer Open Systems Interconnect (OSI)
model. Only complete products that conform to this model
and are based on open and public standards carry the
Open NET name.
OpenNET's network File Access (NFA) is compatible with
Microsoft's MS*NET and IBM's PC Networks Program.
System resources and the processing power of XENIX can
be shared among PCs and terminal users over the
network. Extensive mail facilities are supported across an
OpenNET network. Intel XENIX also several all popular
host communication protocols sold directly by Intel as well
as by third-party suppliers.

INSTAUATION SERVICE & SIJPPORT
The Intel XENIX System 320 is backed by Intel's
worldwide service and support organization. Installation is
available to quickly get the system up and running.
Complete hardware and software support is available,
including a hotline number for when the user needs help
fast. Intel also provides hands-on training workshops to
give the user a thorough understanding of the XENIX
System 320. These workshops are conducted at Intel
training centers or customer sites worldwide.

Ii" Ii i iii' i IliC'i1
ENVIRONMENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

ORDERING INFORMATION
1QOC to 40°C
26°C maximum
85% at 40°C
Sea level to 10,000 feet

For more information contact your SMS account representative:
SMS Data Products Group. Inc.
1505 Planning Research Drive
McLean. VA 22012
(703) 833-8600

REGlJl.ATIONS
Meets or exceeds the following requirements:
Safety
US
Canada
Europe

UL 478
CSZ C22.2
IEC 435

EMIIRFI
US and Canada
Europe

FCC Class B Computing Device
VDE Limit Class B

ELECTRICAl.
DC Power Output
AC Power Input .

435 watt maximum
88-132 VAC or 176-264 VAC,
47-63 Hz, single phase

DIMENSIONS
Height
Width
Depth
Weight

8'
17.5'
22.25'
Approx. 55 lbs

·UNIX is a registered trademark of AT&T.

1-6

IRMX® SY.'iTl:M :120
Intel combines the power of its high performance 386-based System 320, the widely used iRMX 286
real-time software, complete network service software and comprehensive customer support
capabilities to deliver, install and maintain a complete system. The result is the iRMX System 320
gives you the performance and capabilities of a minicomputer at less than half the cost. The system
is especially suited for applications requiring real-time response and resource control typically found
in financial transaction, industrial automation, medical and communications markets. The
iRMX System 320 is also appropriate as the development environment for module-based design.

iRIJIX"') SY.ftjl'I~M .1211 n;,11'IIRf;.ftj
• 80386 Based System
• iRMX Real-time Multitasking Operating
System
• Open System Architecture
• OpenNET Local Area Networking

• Complete Installation, Service and Support
• Worldwide User Group Support
• Range of Configurations

inter------Intel Corporation assumes no responSibility for the use of any CIrcUItry other than circuitry embodied in an Inlel produ("l. No other circuit patenllicenses are
implied. Information contained herein supersedes previously published specifications on these devices frum Intel.

1·7

June. 1987
Order Number: 280502-00 1

IRMX® 286-REAL-TIME SOFTWARE
The iRMX 286 operating system delivers real·time perfor·
mance. Designed to manage and extend the resources of
the System 320, this multitasking operating system
provides configurable resources ranging from interrupt
management and standard device drivers to data file
maintenance commands for human interface and program
development. The iRMX 286 facilities also include powerful
utilities for easy, interactive configuration and debugging.

SYSTEIU 320-AN OrEN SYSTEM
The iRMX System 320 is based on MULTI BUS architecture,
(IEEE 796) industry standard system bus supported by
over 200 vendors providing over 2000/compatible prod·
ucts, and on the iRMX 286 operating system composed of
modular layers, highly configurable for tailoring to target
applications. A wide range of popular industry standard
high·level languages are supported for application develop·
ment. Special configurations can be tailored by the user,
by Intel's Custom System Integration group or by Intel's
authorized Value Added Distribution Centers.

O,wBNETTMTHE STANDARD IN NI:TWORIlING

OIlIJf;IlING INI'ORMA'I'ItIN

Intel Corporation
5200 NE Elam Young Parkway
Hillsboro, OR 97124
(503) 681-8080

Meets or exceeds the following requirements:

UNITED STATES, Intel Corporation
3065 Bowers Ave., Santa Clara, CA 95051
Tel: (408) 987·8080

Safety
US
Canada
Europe

UL 478
CSA C22.2
IEC 435

EMIIRFI
US and Canada
Europe

FCC Class B Computing Device
VDE Limit Class B

JAPAN, Intel Japan K.K.
5-6 Tokodai Toyosato·machi, Tsukuba·gun, Ibaraki·ken 300-26
Tel: 029747-8511

I;LEt'TRIC;U

FRANCE, Intel Paris
1 Rue Edison, BP 303, 78054 Saint·Quentin·en·Yvelines Cedex
Tel: (33) 1-30-57-7000
UNITED KINGDOM, Intel Corporation (U.K.) Ltd.
Pipers Way, Swindon, Wiltshire, England SN3 1RJ
Tel: (0793) 696000

435 watt maximum
88-132 VAC or 176-264 VAC,
47-63 Hz, single phase

WEST GERMANY, Intel Semiconductor GmbH
Seidlestrasse 27, D-8000 Muenchen 2
Tel: (89) 53891

DIMENSIONS
Height
Width
Depth
Weight

Intel offers a wide range of configurations for the iRMX
System 320. Contact your local Intel representative for
further information.

For more inform~tion contact your local Intel sales
representative or

10°C to 400C
26°C maximum
85% at 40°C
Sea level to 10,000 feet

REGIJIATlON.ft;

DC Power Output
AC Power Input

WORLDWIDE VSER GROVr SVrrORT
iRUG (iRMX User Group), provides members a user's
library of iRMX software tools and utilities, access to the
group bulletin board, receipt of regularly published news·
letters and invitations to User Group Conferences. iRUG
numbers over 42 local chapters in 20 countries worldwide.

lile'"

ENt'lRONMENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

INSTALLATION SERJ'ICE & SVrPORT
The Intel iRMX System 320 is backed by Inters worldwide
service and support organization. Installation is available
to quickly get the system up and running. Total hardware
and software support is available, including a hotline
number for when the user needs help fast. Intel also
provides hands·on training workshops to give the user a
thorough understanding of the iRMX System 320. These
workshops are conducted at Intel training centers or
customer sites worldwide.

RANGE 01' CONFIGIJRATIONS

Intel supports and drives local area networking standards
and technology for microsystems and microcommunica·
tions industries. The OpenNET product family adheres to
the International Standards Organization (ISO) and the

Ii" Ii i i Iii I

seven layer Open Systems Interconnect (OSI) model. Only
complete products that conform to this model and are
based on open and public standards carry the OpenNET
name.

HONG KONG, Intel Semiconductor Ltd.
1701-3 Connaught Centre, 1 Connaught Road
Tel: (5) 844-4555

17.5'
22.25'
Approx. 55 Ibs

1-8

FINANCIAL REAL-TIME SYSTEM 320

FINA.NCIA.L SJ'Sl'EM 320
Intel combines the power of its high performance 80386 based System 320, the iRMX 286 Real·Time
Software, complete network service software and comprehensive customer support capabilities to
provide a complete FINANCIAL SERVICES NETWORK. Effective in distributing real·time financial
data from mainframes to users, the System 320 gives you the performance and capabilities of a
minicomputer at less than half the cost.
Based on MULTIBUS@ architecture, the IEEE 796 industry standard system bus, the System 320 is
supported by over 200 vendors providing over 2000 compatible products. This openness to
standards allows for a variety of configurations to meet the unique needs of financial clients. Intel's
Financial System 320 is used by prominent stock exchanges, brokerage firms and investment banks.
Special configurations can be tailored by the user, by Intel's Custom System Integration group or by
Intel's authorized Value Added Distribution Centers.

iRMX® SJ'Sl'EM 320 FEA.l'lJRES:
• Host communication to mainframes
• Complete installation, service and support
• Range of Configurations

• High performance trade data distribution
• 80386 Based System
• iRMX Real·time, Multitasking Operating
System
• OpenNET Local Area Networking Based
Entirely on Standards

imJ-------------------Intel Corporation assLlmes no responsibility for the usc of any circuitry other than circUitry emQodied in an Intel prodlJct. No other circuit patent licenses arc
• implied, Information contained herem supersedes previOusly published spcclficaLlOns on these devices from Intel.

1-9

June. 1987
Order Number:

280~04·001

lRMX@ 2B6-REIIL-'I'IME SOF'I'WIIRE

COMMIJNICII'I'IONS '1'0 HOS'l'S

The IRMX 286 operating system delivers real-time
performance_ Designed to manage and extend the
resources ()f the System 320, this mu ltitasking operating
system provides configurable resources_ These range from
interrupt management and .standard device drivers to data
file maintenance commands for human interface and
program development. The iRMX 286 facilities also include
a wide range of popular industry standard high-level
languages for application development, and powerful
utilities for easy, interactive configuration and debugging.

The System 320 has communication capabilities to host
computers.utilizing X.25 and SNA protocols. The host
communication capability allows users to have real-time
access to the host through the System 320 making more
effective use of mainframe processing.

OpeDNE'l"'III-'I'HE S'I'IINDIIRD IN
NE'I'WORllING
Intel supports and drives local area networking standards
and technology for microsystems and microcommunications industries. The Open:-iET product family adheres
to the International Standards Organization (ISO) seven
layer Open Systems Interconnect (OSI) model. Only
complete products that conform to this model and are
based on open and puhlic standards carry the OpenNET
name.

INS'I'IILM'I'ION SERJlICE liND
SIJPPOR'I'
The Intel System 320 is backed by Intel's worldwide
service and support organization. Custom support
agreements provide the exact service levels required by
customer's applications. Service can also extend to offer
support for non-Intel products. Intel's customer support
organization has offices in 100 locations worldwide.
Installation is available to quickly get your system up and
running. This total hardware and software support
includes a hotline number for when you ned help fast. Intel
also provides hands-on training workshops to give the user
a thorough understanding of the System 320. These
workshops are conducted at Intel training centers or
clIstomer sites worldwide.

RIINGE OF CONFIGIJRII'I'IONS
Intel offers a range of configurations for the iRMX System
320. Contact your local Intel representative for further
information.

SPECIFICATIONS
ENJ'IRONMEN'I'
Operdting Temperature
Wet Bulb Temperature
Relative Humidity
Altitude
.

ORDERING INFORMII'l'lON
lOOC to 40°C
26°C maximum
85% at 40°C
Sea level to 10,000 feet

REGIJM'I'IONS
Meets or exceeds the following requirements:
Safety
US
Canada
Europe

UL 478
CSA C22.2
IEC 435

EMIIRFI
US
Europe

FCC Class B Computing Device
VDE Limit Class B

ELEC'I'RICIIL
DC Power Output
AC Power Input

435 watt maximum
88-132 VAC or 176-267 VAC,
47-63 Hz, single phase

DIMENSIONS
Height
Width
Depth
Weight

8"
17.5"
22.25"
approx 55 Ibs

For more information contact your local Intel sales
representative or
Intel Corporation
5200 t\[<; IfBl·!,r,
RMKII MBI·C"

iRMK Yersion I. 1 Kernel
Starter Kit

iRMK Yrrsion I. 1 Kernel Software
iSBC 386/21
PL/M 386 or C 386
ASM 386
80386 Utilities
P·MON 386

Can be used for MLIl:flBUS I
or custom designs
RMKII MBII·p"
RMKII MBII·C"

CONSUI:J'/DAILY
CONSULT/L:r

Can be used for MULTI BUS II
or custom designs

iRMK Yersion·1.1 Kernel Software
iSBC 3861116MO 1
iSBX 351
!'LlM 386 or C 386
ASM 386
80386 Utilities
P·MON 386

Technical Information
Phone Support

Phone support, ;Comments Magazine, Troubleshooting
Guides

iRMK Yersion 1.1 Kernel
Starter Kit

On· or off·site consulting on iRMK 1.1 Kernel or other Intel products by Intel systems
engineer. Available on a daily or long term basis.
80386 Programming
Using ASM 386

Customer Training Workshop

80386 System Software

Customer Training Workshop

80386 System
Ilardware])csign

Customer Training Workshop

r, Expected availability: September 1987.
Information suhject to changr without r1I1tiCl'.

2-29

The iRMXC!) 286 Reiease 2.0 Operating System is system software designed specifically for real time
applications. The product of ten years of real time expertise by Intel. the iRMX 286 Release 2.0
Operating System provides high performance response to external events, excellent support of
special purpose hardware, and sophisticated real time programming facilities.

ADJ'ANCED FEATIJRES AJ'AIl,ABU TODAI'
• 80286 and 80386 microprocessor support
• 80287 and 80387 numeric coprocessor
support
• 16 megabyte memory addressability

•
•
•
•

Multiple tasks and multiple jobs
Multiple users
Priority based and/or round robin scheduling
Object oriented architecture

A COMPUTE REAl, TIME OPERATING SI'STEM,
NOT JIJST A KERNEl,
• Major functions of the iRMX 286 Release 2.0
Operating System include:
-Nucleus
-File System
-Basic I/O System including device drivers
for many Intel Multibus I/O boards
-Extended 110 System
-Bootstrap Loader

-Application Loader
-Human Interface supporting on target
development and end user reprogramming
-System Debugger
-Optional networking to systems running the
MS-DOS, VAXNMS, XENIX*, iNDX, iRMX 86
Release 7.0, and iRMX 286 Release 2.0
Operating Systems

SOFTWARE WITH A FIJTIJRE
• The leading real time microprocessor
software with over 6000 licenses sold
• An active iRMX Users Group (iRUG) with over
40 chapters· worldwide, a regular newsletter,
and an annual technical convention.

in1:ef

·MS·()OS

Irillll'mill'~S

©'Inlt'l

• Future 8086 family processors will be
supported by iRMX operating systems.
• Highly compatible with the iRMX 86 Release
7.0 Operating System

a Iralll'mark (If Mi('rtlSllrt CnrplIratiun . .\~:NIX is a trmJl'marl. of Mi('nlSUft Curporatlun.lINI.\. is a trademark uf Ht'li I.ahura\urll's. P.X and \ MS art'
uf I)i~ilal ~;tIUIJl"'I'nl Ctllll1lratitln

(~lI'pura'hlll

I!IK7

2-30

{lrth'r

~lIIllht'l';

Junt'.1987
280618·(101

SlJPPORT FOR THE FlJLL RANGE OF
REAL TIME APPLICATIONS
The iRI'vIX 286 Release 2.0 Operating System supports the
full range of real time applications. from embedded control
designs, to rcprogrammable systems which require
dynamic creation, deletion, and prioritization of tasks. Tilis
flexibility makes it possible to save substantial staff
retraining and software maintenance costs by using a
single operating system for many different real time
systems and subsystems. The iRMX 286 Release 2.0
Operating System is ideal for sllch applications as:
avionics
communications
communication concentrators
data acquisition and analysis
energy management
factory automation
financial trader workstations
Image processing
machine control
manufacturing test

medical instruments
military
process control
railroad control
rockets
satellite communications
simulation
SCADA systems
transaction processing

REAL TIME SOFTWARE FOR REAL
TIME APPLICATIONS
Real Time Applications are easier to develop with special
software. Operating Systems deSigned for general business
use typically lack essential real time features, so real time
application development is often expensive, difficult, or
even impossible. In contrast, the iRMX 286 Release 2.0
Operating System is real time software deSigned to make
the development of real time applications easy and
successful.

• Easily pro~ammed Into PROM.
Real time applications built on tile iRMX 286 Release
2.0 Opcrating System arc easily programmed into
PROM's or EPROM's for highly reliable embedded
systems wilicil do not require disks. A complete set of
languages Wllich support reentrant code are available
for use with tile iRMX 286 Release 2.0 Operating
System.
• Ext:ellent Support for spedal pUl'pose
b3l'dware.
Most real time applications involve some special
purpose hardware, and general purpose operating
systems are often relatively monolithic and difficult to
interface to this hardware. In contrast, the iRMX 286
Release 2.0 Operating System is a highly configurablc,
modular software system which easily supports custom
hardware. Support for special purpose hardware
includes:
-the ability to configure the operating system by layer
-hooks for user written handlers at key points .
-the ability to add operating system extensions.
-standard device driver interfaces
• Support for deslps based on Intel
systems, slnl:le board £omputel'8, aud
£omponents.
Central Processing Unit Support

Systems-. Bootable preconfigured software IS JIlcludcd for:
Intel System 310 AP family
Intel System 320 family
Single Board Computers-Preconfigured software is
included for:
iSBC 286/1OA, iSBC 286/12
iSBC 386/2X

• Hlab performan£e.
For real time applications, the iRMX 286 Release 2.0
Operating System is typically 100 times faster than
general purpose operating systems. This high
performance enables applications based on the iRMX
286 Release 2.0 operating system to keep up with the
rapid data and control flow of machine and
communication interfaces.

Component Designs-Minimum required hardware to run
the iRMX 286 Release 2.0 Operating System:
80286 or 80386 microprocessor
8259A Programmable Interrupt Controller
8254 or 8253 Programmable Interrupt Handler
Necessary memory

• "rl£b set of ~I time pl'O~ammlnl:
fadlltles.
The iRMX 286 Release 2:0 Operating System includes a
rich set of real time programming facilities that are
usually missing in whole or in part from non-real time
operating systems. These facilities include:
-interrupt management with custom exception
handlers
-support for multiple tasks
-preemptive, priority based scheduling with round
robin (time slice) scheduling within a priority level
-intertask communication through mailboxes and
semaphores

A COMPLETE REAL TIME OPERATING
SYSTEM, NOT JlJST A KERNEL
With comparable performance, the iRMX 286 Release 2.0
operating system provides many features that are cxtra
cost items, or simply unavailable, in real time kernels.
These features make the development of real time
applications much easier and faster, but do not add
unneccessary overhead. In fact, all functional layers except
the nucleus are optional in the iRMX 286 Release 2.0
operating system. This flexibility allows you to include
only those features that your application requires.
The follolVing is a brief description of the major functional
groups within the iRMX 286 Release 2.0 Operating
System.

2-31

II COMPLETE REAL TIME OPERATING
SYSTEM (continued)

[rom the iRMX 286 Release 2.0 Operating System to other
operating systems which support the UDistandard.

Nucleus
The Nucleus is the heart of the operating system and
controls all resources available to the system. The nucleus
provides key real time features including:

Application Loader
The Application Loader is used to load programs from
mass storage into memory. where they execute. Programs
may be loaded under program or operator contro\.

•
•
•
•
•

Bootstrap Loader
The Bootstrap Loader is used to load the operating system
or an application system [rom mass storage into memory,
and then to begin the system's execution.

•
•
•
•
•

support of multiple tasks
priority based and/or time slice scheduling
dynamic priority adjustment
memory management with '16 megabyte addressability
intertask communication and synchronization using
mailboxes and semaphores
interrupt management with custom exception handlers
descriptor table management
time management
object management
the addition of custom Operating System extensions.

BasIc I/O System (BIOS)
The Basic \/0 System (BIOS) provides primitives to read
from and write to peripherals. as well as the ability to
buffer I/O. The BIOS also sets up the file structures used
hy the system and provides access to all required
peripherals througlM standard device driver interface.
Many device drivers arc providrcl with the iRMX 286
Release 2.0 Operating System. and custom device drivers
and file drivers may be added by the user.
Device Drivel'S Induded with the IRItIX®
Z86 Release Z.O Operating System
Sopports Terminal Communications for
Terminal
Ct)mmunications til!' iSBC IHH/56. iSIlC 546. iSIlC 547 .•
and iSIlC ;)48 single hoard computers
Flexible Disk Controller
iSllC 208
S~lllllisk Controller
iSIlC 220
iSllC 214
~lulti·l'eripheral Controller
\\incllt'ster Disk Controller
iSIlC 215G
iSllX'· 2181\
Flexible Disk Controller
Tape Controller
iSIlX 217C
Parallel Port (Centronix·type Printer
iSIlX :1:iO
Intl'rface)
iSIlC 534
4 Channl'1 Terminal Interfacl'
iSIlC ~44A
Intl'lligent 4 Channel Tl'rminal Intl'rface
and Controller
H251A
Serial Communications Port
iSIlX :1~4
2 ClulIlnel Serial Port
Serial Comll1unil"ation~ Controller
825:10
j.n~1
~1Pll1ory Dril"t'r

System Debullller
The System Debugger is used to debug applications and
give a view into the system itself.
Human Interface
The Human Inter[ace allows multiple users to effectively
develop applications, maintain files. run programs. and
communicate' with the operating system. It consists of a
set o[ system calls. a set of commands. and a Command
Line Interpreter. Commands are availahle [or rue
management. device managemf'nt. and system status. The
Command Line Interpreter is a sophisticated tool [or
program development and system design. Its features
include dynamiC logon. [uilline eciiting. user extensions.
and support [or hackground jobs. In addition, the
Command Line Interpreter may 1)(' replaced [or special
applications. For example. a Computer .-\ided Tomography
(CAT) scanner controlled by the iRMX 286 Release 2.0
Operating System could usc a custom Command Line
Interpreter to allow the operator to direct the movement o[
the scanner.
lRM,f®-Net Networldnll software (al'allable
separately)
The iR\IX 286 Rrleasl' 2.0 Operating System is designed
to work with iR\IX·!\ET networking software to provide
transparent rile access to systems running the iRMX 86
Release 7.0. iRMX 286 Release 2.0. MS·DOS. XENIX,
iNDX. and vAXlVMS operating systems. iR'vlX·NET is ISO
standard networking software [or ether net local area
networks.
iR~IX networking allows your real time application to
communicate ef[ectively with g('neral purpose computer
systems as 111'11 as other real time systems.

Extended I/O System (EIOS)
The Extended I/O System (EIOS) provides similar services
to the BIOS. with Simplified calls that give less explicit
control o[ device behavior and performance. The EIOS also
pl'ovides a logical-to·physical device connection. and allows
a program to specify a logicill mldress [or output.
lJn/l'el'Sa1 Del'elopmenf Interface (lJDI)
The liniversal Dl'Vl'lopment Inter[ace provides an easy to
USt' interface \Iith a standard set o[ system calls to allo\1
programs and languages to ile easily transported to or

2-32

IRItIX® 286 Release 2.0 Conflllurat/on
SIze·
System Layer
Code Size Data Size
Nucleus
:J0f.:1l
2f.:ll
1l10S
86f.:B
112 bytes
,;IOS
16 byles
IHf.:1l
32 bytes
Hf.:ll
l'lll
100 byt(,s
\pplicaUon Loadel"
IOf.:1l
SY~l('m Debugger
31f.:B
If.:B
Human Intrri"a("l'
83f.:ll
224 Ilytes
*\lIlay('rs aI"(' optional ('\('('pt til(' nucleus.

ON TARGET DEJ'ELOPMENT-A
BETTER WAY TO DEJ'ELOP REAL
TIME APPUtJATlONS
Designers familiar with both cross development and on
target development agree that on target development is tht'
easier. more reliable methmt for dl'veloping applications.
Testing is greatly simplified. and you need become
comfortable with only one operating system. Furthermore.
a whole set of bugs is avoided by eliminating the transition
from one operating system to another.
Tht' iRMX 286 Rt'lrase 2.0 Operating System provides
solid on target development capability-a capability
entirt'ly missing from other real timt' software for
microprocrssors.
Developers can use the full rich feature set of the iRMX
286 Rt'lease 2.0 Operating System for development. but
then includ(' only a minimum set of iRMX functions in their
final application. As a result. your final application
.
rt'C('ives tht' bt'nefits of on target developmt'nt without the
overhead that grneral purpose operating systems incur.
Development facilities included with the iRMX 286 Release
2.0 Operating System:
• a Iluman Intl'rfact' supporting multi pit' uSt'rs
• 37 Iluman Interface commands for system status.
devict' management. and fill' management
•
• a sophisticated Command Line Interprt'ter supporting
background jobs and full line editing
• Interactive Configuration Utility (ICU)a utility for assisting an iRMX developer in the
configuration process. The InteractiVt' Configuration
Utility prompts the usel' for system paramt'tt'rs and
requirements. tht'n builds a command fill' to ('om pill'.
assembll'. bUild. and bind necessary files.
• lIardwarr traps to catch up to 90% of typical
programming errors
• System Dehugger (requires the iSDM Monitor)
• Bootstrap loader with debug option
• Parameter and Data validation
• Universal Development Interface
• Numerous dl'vice drivl'l's for Intel ~Iultibus boards
Development facilities availabll' separately for use with the
iRMX 286' Rl'lease 2.0 Operating System:
• Reentrant languages-PIAl 286. PASCAL 286.
FORTR.'\N 286. and C 28{1
• AEDIT-a menU-driven. scrl'en-oriented tl'xt l'ditor
• iSD~1 R3.0 System Debug l\IonitorAllows downloading from an iRMX 286 Release 2.0 host
to an iR\IX 286 Release 2.0 or iRMX 86 Re!t'ase 7.0
target
• Sort-Scope 286 debuggera tasking deiJugger

2-33

• ASM286-an 80286 Development Utilities Package
including the 80286 Macro Assembler. Builder. Binder.
Librarian and Mapper
• ASM86-an 8086 Development Utilities Package
including the 8086 Macro Assembler. Linker. Locator.
LiiJrarian. and line editor
• iRMX·N~;T Networking-allowsyour development effort
to be shared over several systems. Includes support for
both the i8BC 186/51 and the iSBC 552A Ethernet
Controllers
• VDI'· 720-Graphics software for the iSBC'· 186178A
graphics controller
• iPAT-a Performance Analysis Tool. hosted on an IBM
PC-AT or equivalent. to aid in the performance
optimization of an iRMX application.
• ·In Circuit ~;mulators-hosted on an IBM PC-AT or
equivalent. to aid in hardware debugging and software
tracing
• a variety of user supplied utilities and special software
are available from the iRMX Users Group (iRUG)

SOITWARE WITH A I'IJTIJRE
With over 6000 m;M and development licenses
outstanding. the iRMX operating systems are far and away
the leading real time software for microprocessors. The
iRMX community has grown so that today there is an
active iRMX Users Group (iRUG) with over 40 chapters
worldwid.e. an annual technical convention. and a regular
newsletter. In addition major universities such as the
University of North Carolina. Cornell University. and the
University of California at Berkeley use iRMX software
and/or teach real time programming courses featuring the
iRMX operating systems.
.
This year Intel celebrates the 16th anniversary of the
iRMX operating system family. Over the last de,cade. Intel
has s\eadily improved the performance and functionality of
thl' iRMX operating systems. You can count on continued
improvements in the future.
The iRMX 286 Release 2.0 Operating System runs
compatibly on 80286 arid 80386 microprocessors. and
iRMX operating systems will run on future advanced
microprocl'ssors from Intt'!. Ower the last f.ur

years tile perf.....au£e of lukl's 8086
family ml«:...processors lias I.crea~
400%. When you're using the iRMX operating systems.
you benefit from these tremendous performance
improvemrnts with a high degree of real time application
portability.

OIJTSTANDING TEtJHNltJAL SIJPPORT
With the iRMX 286 Release 2.0 Operating System you're
not alone when you're developing a real time application.
Intel has thl' best technical sales support in the real time
business. If you run into a snag: training. consulting. and
design advice are available close at hand.

lRMX 286 RELEASE 2.0 SYSTEM CAUS
Nrreleus

.10" Mallaf:e_ea,
RQ$CRK'm;$.JoB

Creates a job (whose memory pool is limited to 1 MB) with a task
Creates a jilh (whose memory pool is up to 16 MB) with a task
Deletes a job
.
Provides tokens of the child jobs of the specified jobs
Provides a list of tokens for the child jobs of the specified job in a user supplied data
structure

RQE$CR~;A'rr;$.JoB
RQ$DEL~;TE$.JOB
RQ$OF~'SPRING
RQE$OF~'SPRING

IDs" MaaalJe_ea,
RQ$CR~;An;$TASK

Creates a task
Deletes a task that is not an interrupt task
.Returns the static ·priority of a task
Changes a task's priority
Returns to the caller a token for the specified task
Increases a task's suspension depth by one; suspends the task if it is not already
suspended
Decreases a task's suspension depth by one; resumes the task if the suspension depth
becomes zero
Places the calling task in ttie asleep state for a specified amount of time

RQ$DEL~:TE$TASK

RQ$m:T$PRIORITY
RQ$SET$PRIORITY
RQ$GET$TASK$TOKENS
RQ$SUSPEND$TASK
· RQ$RESLJME$TASK
RQ$SLE~:P

Mailbox Ma,;alJe_ea,
RQ$CREATE$MAILBOX
RQ$DELETE$MAILBOX
RQ$SEND$DATA
· RQE$RECEIVE$DATA

Creates a mailbox
Deletes a mailbox
Sends a message to a mailbox
Allows the calling task to receive a message from a mailbox; the task can wait
Sends an object to a mailbox
Allows the calling task to receive an object; the task can wait if no objects are present

RQ$S~;ND$M~;SSAGE

RQ$R~;CEIVf:$MESSAGE .

Se_apltore Mallaf:e_ea,
RQ$CREATE$SEMAPHORE
RQ$DELETE$SEMAPHORE
RQ$SEND$LJNITS
RQ$RECEIVE$lINITS

Creates a semaphore
Deletes a semaphore
Adds a specific number of units to a semaphore
Asks for a specific number of units from a semaphore

SeIl18ea,aa" Me_ory
Pool MaaalJeDJea,
RQ$CREA'I'E$SEGMENT
RQ$DELETE$SEGMENT
RQ$GET$SIZE .
RQ$SET$POOL$MIN
RQ$GET$I'OOL$ATTRIB
RQE$GET$POOI.$A'I'TRIB

Creates a segment
Returns a segment to the memory pool from which it was allocated
Returns the size of a segment
. Changes the minimum size of the. memory pool of the caller's job
Returns memory pool attributes of the caller's job .
Returns information about a job with more than. 1 megabyte of memory

Desuiptor Maaa,:e_ea,
RQE$CREAn:$DESCRIPTOR
RQ~:$DELETE$DESCRII'TOR

RQE$CHANGE$DESCRIPTOR
O"'~' Maaal:e_ea,
RQ$CA'I'ALOG$()B.J~:C'I'

· RQ$LJNCA'rALOG$()B,J~:CT
RQ$LOOKUP$OB.JECT .
RQE$G~;T$OBJECT$ACCESS

RQE$CIIANGE$OBJECT$TYPE
RQE$GET$ADDRESS
.RQ$GET$TYI'K
.

Creates a descriptor in the Global Descriptor Table describing a segment
Removes a descriptor entry from the Global Descriptor Table
Changes the physical address or size of a segment by modifying its descriptor in the
GlObal Descriptor Table
Places an object in an object directory
Removes an object from an object directory
Returns a token for the catalogued name of an object
Returns the access type of an object
Changes the access type of an object
Returns the physical address of an object
Returns the type code of an object

2-34

lRMX@ 286 RELEASE 2.0 SYSTEM CALLS
Nucleus
Exceplloll BBlldlel'
MBIIBllemelll
RQ$GET$EXCEPTION$HANDLER
RQ$SET$EXCEPTION$HANDLER
IlItel'l'Dpl MBIIBllemelll
RQ$ENABLE
RQ$DISABLE
RQ$SET$INTERRUPT
RQ$RESET$INTERRUPT
RQ$GET$LEVEL

Returns the current values of the caller's exception handler
Sets exception handler and exception mode attributes

RQ$WAIT$INTERRUPT

Enables an interrupt level
Disables an interrupt level
Assigns an interrupt handler and an interrupt task to an interrupt level
Deletes the interrupt task for an interrupt level
Returns the interrupt level of highest priority which an interrupt handler has started
but not completed
Informs root task that a synchronous initialization process has completed
Sets up a data segment base address for an interrupt handler
Used by interrupt handlers to invoke interrupt tasks
Used by interrupt handlers to send an end-of-interrupt signal to hardware
Puts the calling interrupt task to sleep until it is awakened by an interrupt handler,
or a specified time period elapses
Puts the calling interrupt task to sleep until it is awakened by an interrupt handler

Composite Ob/ecl
MBIIBllemelll
RQ$CREATE$COMPOSITE
RQ$DELETE$COMPOSITE
RQ$ALTER$COMPOSITE
RQ$INSPECT$COMPOSITE

Creates a composite object
Deletes a composite object
Replaces components of composite objects
Returns a list of the component tokens contained in a composite object

Exlellsloll Ob/ecI
MBIIBllemelll
RQ$CREATE$EXTENSION
RQ$DELETE$EXTENSION

Creates a new object type
Deletes an extension object and all composites of that type

Be/elloll COlllrol
MBIIBllemelll
RQ$DISABLE$DELETION
RQ$ENABLE$DELETION
RQ$FORCE$DELETE

Makes an object immune to ordinary deletion
Makes an object susceptible to ordinary deletion
Deletes objects whose disabling depths are zero or one

RQ$END$INIT$TASK
RQ$ENTER$INTERRUPT
RQ$SIGNAL$INTERRUPT
RQ$EXIT$INTERRUPT
RQE$TIMED$INTERRUPT

Opel'BIllI1l System
Exlellsloll MBIIBllemelll
RQE$SET$OS$EXTENSION
RQ$SIGNAL$EXCEPTION

Beilloll MBIIBllemelll
RQ$CREATE$REGION
RQ$DELETE$REGION
RQ$SEND$CONTROL
RQ$ACCEPT$CONTROL
RQ$RECEIVE$CONTROL

Attaches the entry point address of a user written Operating System extension to a
call gate or deletes such an entry
Used by Operating System extensions to signal the occurrence of an exception
Creates a region
Deletes a region
Relinquishes control to the next task waiting at the region
Causes the calling task to accept control from a region if control is immediately
available
Causes the calling task to wait at the region until the task receives control

2-35

BA.SIC I/O SYSTEM
oIob£ere'
RQ$SET$DEFAULT$PREFIX
RQ$GET$DEFAULT$PREFIX
RQ$SET$DEFAULT$USER
RQ$GET$DEFAULT$USER
RQ$ENCRYPT

Set default prefix for job
Inspect default prefix
Set default user for job
Inspect default user
Encodes user password

Det'loo £et'e'
RQ$A$PHYSICAL$ATTACH$DEVICE Asynchronous attach device
RQ$A$PHYSICAL$DETACH$DEVICE Asynchronous detach device
Asynchronous perform device-level function
RQ$A$SPECIAL

Flle£et'el
RQ$A$CREATE$FILE
RQ$A$CREATE$DIRECTORY
RQ$A$DELETE$FILE
RQ$A$ATTACH$FILE
RQ$A$DELETE$CONNECTION
RQ$A$CHANGE$ACCESS
RQ$A$RENAME$FILE
RQ$A$TRUNCATE
RQ$A$OPEN
RQ$A$CLOSE
RQ$A$READ
RQ$A$WRITE
RQ$A$SEEK
RQ$A$UPDATE
RQ$WAIT$IO

Asynchronous data file creation
Asynchronous create a directory
Asynchronous delete a data file or a directory
Asynchronous attach file
Asynchronous delete file connection
Asynchronous change access rights to a file
Asynchronous rename file
Asynchronous truncate file
Asynchronous open file
Asynchronous close file
Asynchronous read file
Asynchronous write file
Asynchronous move file pOinter
Asynchronous finish writing to output device
Synchronous wait for status after Input/Output

Status/Attribute
RQ$A$GET$CONNECTION$STATUS
RQ$A$GET$DIRECTORY$ENTRY
RQ$A$GET$FILE$STATUS
RQ$A$GET$PATH$COMPONENT

Asynchronous get connection status
Asynchronous inspect directory entry
Asynchronous get file status'
Asynchronous obtain path name from connection token

(Jsel' Ob#uts
RQ$CREATE$lISER
RQ$INSPECr$USER

Create a user object
Delete a user object
Get IDs in a user object

Exteus'oD Data
RQ$A$SET$EXTENSION$DATA
RQ$A$GET$EXTENSION$DATA

Asynchronous store a file's extension data
Asynchronous receive a file's extension data

Time/Date
RQ$SET$TIME
RQ$GET$TIME
RQ$SET$GL()BAL$TIME
RQ$GET$GLOBAL$TIME

Set date/time value in internally-stored format
Get date/time value in internally-stored format
Sets the battery backed-up hardware clock to a speCified time
Obtains the time of day from the battery backed-up hardware clock

RQ$D~;IEn;$USER

LoMlaJl to Physical
Address t:oDt'el'Slon
RQ$B!()S$G~;T$ADDRESS

Returns the physical address of a selector

2-36

EXTENDED I/O SYSTEM
Input/Output Jobs
RO$CREATE$IO$.JOB
ROE$CREATE$IO$JOI3
RO$START$IO$JOI3
RO$EXIT$IO$.JOI3

wll'cal Names
RO$LOGICAL$ATTACII$DEVICE
RO$IIYBRID$DEli\CII$DEVICE

Creates an 110 job with a memory pool of up to I M bytes
Creates an 110 job witil a memory pool of up to 16M bytes
SWrts (makes ready) the initial task in an 110 job
Sends a message to a mailbox and deletes the calling task

RO$S$UNC;\TALOG$CONNECTION

Creates and catalogs a logical name for a device
Temporarily removes the correspondence between a logical name and a physical
device established via LOGICAL$ATTACH$DEVICE
Deletes a logical name created with LOGICAL$ATmCH$DEVICE
Creates a logical name for a connection
Searches through an 110 job's object directories to find the connection associated
with a logical name
Deletes a logical name from the object directory of a job

Flies
RO$S$CREATE$DIRECTORY
RO$S$CREATE$FILE
RO$S$D[-:L8TE$FILE
RO$S$AT'I/\CII$FILE
RO$S$DELETE$CONNECTION
RO$S$OPEN
RO$S$CLOSE
RO$S$READ$MOVE
RO$S$WRITE$MOVE
RO$S$SE8K
RO$S$TRUNCATE$f'ILE
RO$S$CHANGE$ACCESS
RO$S$RENAME$FILE

Creates a new directory
Creates a new physical, stream, or named data file
Deletes a stream, physical, or named file
Creates a connection to an existing file
Deletes a file connection,
Opens a connection to a file
Closes an open connection to a file
Reads a number of bytes from a file to a buffer
Writes a collection of bytes from a buffer to a file
Moves the file pointer
Removes information from the end of a named data file
Changes the access list for a named file
Cllanges ttle path of a named file

SpeclallkJ'lces
RO$S$SPECIAL

Allows a task to perform functions that are peculiar to a specific device

Status
RO$GET$LOGICAL$DEVICE$STATUS
RO$S$G8T$CONNECTION$STATUS
RO$S$GET$FILE$STATUS

Provides status information about logical devices
Provides status information about file and device connections
Allows a task to obtain information about a file

llsers
RO$GET$USER$lDS
RO$VERIFY$USER

Returns the user 10 as defined in the User Definition File
Verifies a user's name and password

RQ$LOGICAL$DEmCII$DEVICE
RQ$S$CATAlnG$CONNECTION
RO$S$LOOK$UP$CONNECTION

APPLICATION LOADER
RO$A$LOAD
RO$A$I,OAD$IO$.JOI3
ROE$A$LOAD$IO$JOI3
RO$S$LOAD$IO$JOI3
ROE$S$LOAD$IO$JOI3
RO$S$OVERLAY

Loads object code or data into memory
Creates an 110 job asynchronously with a memory pool of up to I M bytes, loads
the job's code, and causes the job's task to run
Creates an I/O job asynchronously with a memory pool of up to 16M bytes, and
loads the job's code, and causes the job's task to run
Creates an 110 job synchronously with a memory pool of up to 1M bytes, loads
the job's code, and causes the job's task to run
Creates an 110 job synchronously with a memory pool of up to 16M bytes, loads
the job's code, and causes the job's task to run
Loads an overlay into memory

2-37

lINIJ'ERSAL DEJ'ELOPMENT INTERFACE

Procram CODtl'O'
DQ$EXIT
DQ$OVERLAY
DQ$TRAP$CC

Exits from the current application job
Causes the specified overlay to be loaded
Captures control when CONTROL-C is typed

Flies
DQ$ATTACH
DQ$CHANGE$ACCESS
DQ$CHANGE$EXTENSION
DQ$CLOSE
DQ$CREATE
DQ$DELETE
DQ$DETACH
DQ$FILE$INFO
DQ$GET$CONNECTlON$STATUS
DQ$OPEN
DQ$READ
DQ$RENAME
DQ$SEEK
DQ$SPECIAL
DQ$TRUNCATE
DQ$WRITE

Creates a connection to a specified file
Changes access rights associated with a file or directory
Changes the extension of a file name in memory
Closes the specified file connection
Creates a file for use by the application
Deletes a file
.
Closes a file and deletes its connection
Returns data about a file connection
Returns status of a file connection
Opens a file for a particular type of access
Reads the next sequence of bytes from a file
Renames the specified file
Moves the current position pointer of a file
Sets terminal line-editJtransparent mode
Truncates a file to the specified length
Writes a sequence of bytes to a file

Me_ory MaDaMe_ent
DQ$ALLOCATE
DQ$FREE
DQ$GET$MSIZE
DQ$GET$SIZE
DQ$MALLOCATE
DQ$MFREE
DQ$RESERVE$IO$MEMORY

Exception HandllDM
DQ$DECODE$EXCEPTION
DQ$GET$EXCEPTION$HANDLER
DQ$TRAP$EXCEPTION

IfUllt" and Command
ParslnM
DQ$DECODE$TIME
DQ$GET$ARGUMENT
DQ$GET$SYSTEM$lD
DQ$GET$TlME
DQ$SWITCII$Bmn:R

Requests a memory segment of a specified size
.Returns a memory segment to the system
Returns the size of the specified memory block
Returns the size of the specified segment
Requests a logically contiguous memory segment of a specified size
Returns memory allocated by DQ$MALLOCATE to the Free Space Pool
R~quests memory to be set aside for overhead to be incurred by lIO operations
Converts an exception numeric code into its equivalent mnemonic
Returns a pointer to the address of the program currently being used to process
errors
Identifies a custom exception processing program for a particular type of error

Returns system time and date in both binary and ASCll-character format
Returns an argument from a STRING
Returns the identity of the environment for the UDl
Obsolete: included for compatibility
. Selects a new buffer from which to process commands

2-38

HIJMAN INTERFACE
I/O ProceSSlD';
RQ$C$GET$INPUT$CONNECTION
RQ$C$GET$OUTPUT$CON NECTION
COlDlDaDd PandD';
RQ$C$BACKUP$CIIAR
RQ$C$GET$CHAR
RQ$C$GET$INPUT$PATHNAME
RQ$C$GET$OUTPUT$PATHNAME
RQ$C$GET$PARAMETER

RQ$C$SET$PARSE$BUF'F'ER
RQ$C$GET$COMMAND$NAME

ltIes8a,;e ProceSSID';
RQ$C$F'ORMAT$EXCEPTION
RQ$C$SEND$CO$RESPONSE
RQ$C$SEND$EO$RESPONSE
COlDlDaDd ProceSSlD';
RQ$C$CREATE$COMMAND$CONNECTION
RQ$C$DELETE$COMMAND$CONNECTION
RQ$C$SEND$COMMAND

rro,:I'alD CODlrol
RQ$C$SET$CONTROL$C

Return an EIOS connection For the speciFied input File
Return an EIOS connection For the speciFied output File
Move the parsing buFFel' pointer back one byte
Get a character From the command line
Parse the command line and return an input path name
Parse the command line and return an output path name
Parse the command line For the next parameter and return it [Is a keyword
name and a value
Parse a buFFer other than the current command line
Return the command name by which the current command was invoked
Create a deFault message For an exception code
Send a message to the command output (CO) and read a response From the
command input (CI)
Send a message to the operator's terminal and return a response From that
terminal
Create a command connection
Delete a command connection
Concatenate command lines into the data structure created by
CREATE$COMMAND$CONNECTION and then invoke the command
Changes a calling task's CONTROL·C exchange to the semaphore speciFied
by the call

2.-39

IRMX® 286 RELEASE 2.0 COMMANDS
SYSTEMDEBVGGERCOMMANDS
VC
VD
VH
VJ
VK
VO
VR
VS
VT
VU

Display system call information
Display a job's object directory
Display help information
Display job hierarchy
Display ready and sleeping tasks
Display objects in a job
Display 110 RequestJResult Segment
Display stack and system call information
Display any iRMX 286 object
Display system calls in a task's stack

BIJMAN INTERFACE
COlDlDaDd LIDe IDterpreter COIDIDaDds
!
Recalls a specified command line
Alias
Assigns an abbreviation to a command
Background
Causes a command to be executed in background mode
Changeid
Changes the current user ID to any value between 0 and 65535
Dealias
Cancels the abbreviation assigned by Alias
Exit
Leaves the Super mode
History
Recalls the last 40 lines entered at the terminal
Jobs
Displays a list of bac~ground jobs by their job identification number
Kill
Cancels a background job
Logoff
Ends a user session at a dynamic logon terminal
Set
Alters the Command Line Interpreter environment by allowing on-line changes to the terminal name,
minimum and maximum background memory pool size, the memory for alias tables, or the prompt
string
Submit
Reads, loads, and executes a string of commands from a secondary storage file instead of from the
keyboard
Super
Changes the operator to the system manager by changing the user ID

BIJMAN INTERFACE
COIDIDoDly Vsed SystelD ~_s
FIle MaDa«e.eD' Co• •a.ds
Attachfile
Associates a logical name with an existing file
Copy
Copies files specified in an input list to files specified in an output list
Createdir
Creates one or more new directories
Delete
Deletes data files and empty directories from a secondary storage device
Detachfile
Removes the association of a logical name with a file
Dir
Lists a directory's filenames and file attributes
Downcopy
Copies files from an iRMX 286 volume to an Intellec Development System via the iSDM monitor
Permit
Grants or rescinds user access to a file
Rename
Changes the names of files or directories
Upcopy
Copies files, via the iSDM monitor, from an Intellec Development System to an iRMX 286 volume

J'ol••e

Ma-.e~.'

Addloc
Attachdevice
Backup
Detachdevice

Co• .a.ds

Combines the output of LOCDATA and an iRMX 286 bootloadable file_ The output of ADDLOC is
another iRMX 286 bootloadable file
Attaches a new physical device to the system and catalogs its logical name in the root job's object
directory
Copies named files to a backup volume
Removes a physical device from system use and deletes its logical name from the root job's object
di~ectory

Diskverify
Format
Locdata
Restore

Verifies the data structures of named and physical volumes
Writes format information on an iRMX 286 volume
Reads the specified data and creates a "located" file that can be processed by the ADDLOC command
Copies files from a backup volume to a named volume

2-40

S;rSlelll MaDallellleDl COlllmaDds
Accounting
Tracks activities of dynamic logon users
Initstatus
Displays the initialization status of Human Interface terminals
Jobdelete
Deletes a running interactive job
Lock
Prevents the Human Interface from automatically creating an interactive job
Logoff
Ends a user session for users with a customized Command Line Interpreter
Password
Changes passwords for dynamic logon users and creates new users when invoked by the system
manager
Super
Changes the operator's user ID into that of the system manager (user ID 0) for users who are using-a
custom Command Line Interpreter
Unlock
Permits the Human Interface to create an interactive job, after the terminal has been locked by the
LOCK command
GeDerallJllIll;r CommaDds
Date
Sets or resets the system date, or displays the current date
Debug
Transfers control to the iSDM monitor to debug an iRMX 286 application program
Logicalnames
Lists all the logical names available to the user
Memory
Displays the memory available to the user
Path
Shows the path name fo a file
Shutdown
Provides an orderly shutdown of the system
Submit
Reads, loads, and executes a string of commands from secondary storage instead of from the
keyboard for users with a custom Command Line Interpreter
Time
Sets or resets the system clock, or displays the current system time
Version
Displays the version numbers of commands
Whoami
Displays the current ID associated with the user
Zscan
Lists the ZAPs (updates) applied to an object module, library, or bootloadable file

PRODlfCT CODES-IRMX 286 RELEASE 2.0 OPERATING SYSTEM
RMX286JSC
RMX286CTSC
SYR286JSC
SYR286CTSC

iRMX 286 Release 2.0 Operating System on 514" Double Sided Double Density flexible diskettes
iRMX 286 Release 2.0 Operating System on cartridge tape
iRMX 286 Release 2.0 Operating System on 514" Double Sided Double Density Flexible diskettes plus
basic utilities and languages (PLIM 286, ASM286, ASM86, and AEDIT software)
iRMX 286 Release 2.0 Operating System on cartridge tape plus basic utilities and languages (PLIM
286, ASM286, ASM86, and AEDIT software)

Information subject to change without notice.

2-41

intel

Administration Seroices

iBASE - BASE
APPLICATION SOFIWARE
ENVIRONMENT
• Friendly, easy-to-use menus
• Menu-driven system and network
administration
• Platform for integrated and independently
provided application software
• Peripheral resource administration
and allocation
• File management
• Electronic mail and directory
• PC and host mainframe communication
options
• OpenNEP" local area network compatible

iBASE
XENlX'"

• iBASE BASE APPLICATION
SOFlWARE ENVIRONMENT

Electronic clirec:tory. The built-in electronic directory provides an on-line listing of the system and network users_ Information includes system addresses for
electronic mail as well as standard phone book information_ Directory facilities include phoneticJookup capabilities when users are not sure of exact spellings_
Electronic personal calendar. The electronic
personal calendar 'is an office automation tool which
works with electronic mail to provide an automatic
reminder of future appointments.
File management. The file management' system
provides the capability to view, edit, print and copy
files between the various system work areas. Conversion routines facilitate file format translations among
popular applications_
On-line help facility. The help facility, a comprehensive on-line documentation feature, is accessible
from the menu system so the user need not constantly
refer to manuals when using integrated applications.
With the optional iMENU facility, an experienced user
can extend or modify the help facility to specify help
information for other applications.
Remote operations access. iBASE provides menudriven access to host communications subsystems_ By
adding the optional Virtual Protocol Machine (iVPM)
facility and corresponding protocols, users can access
remote mainframe hosts. Also, local users can appear
as a terminal to a remote system using the TIYPassthrough feature provided in iBASE.

iBASE is an easy-t(}-use software platform which serves as
a menu-driven environment for system administration,
network administration and application software access_
In addition, iBASE provides electronic mail, electronic
personal .calendar and on-line help facilities as well as
data conversion tools for facilitating communication
with both mainframe hosts and PCs_
Easy-to-use menus. The menus provide quick and
user-friendly access to capabilities of the system without
the need to learn the underlying operating system.
Because it is easy to learn, the user can quickly select
desired activities such as application packages, mail,
(emote operation, system administration, or tools for
application development The menus may be customized and enhanced with the optional iMENU menu
development package_
Electronic mail. The electronic mail service, an
enhanced version of the XENIX electronic mail, is an
office automation tool that supports the timely
exchange of business messages in a multiuser and
network environment_ The mail service can be integrated with a wordprocessor to easily compose longer
messages_

INTEl. CORPORA nON. 19H(1

JUNE,1986

'XEN!X IS A REGISTERED TRADEMARK OF MICROSOFf CORPORATION

ORDER NUMBER: 270187·002

2-42

in1:el
• SYSTEM ADMINISTRATION
Dethdna

routed to individuals and groups of individuals across
the network in a timely manner. Many orthe day-to-day
administrative tasks for multiple nodes can be accomplished from a single network node. This Increa'ied convenience for the operators improves productivity and
ensures more timely execution of the administration
function.

md work _ . The System
Administration features ofiBASE allow the administrator
to quickly and easi1y add additional users to the system
URn

Each user can be customized for access to software and
various system resourc~ In addition, the administrator
can establish user work areas and default text editors.
1bis tailoring of the system enables multiple users to
operate as groups and share certain files while maintainIng security on other files.
U..-.pedfic resource allocation. The system
administrator can specifY access permissions for physical devices and software features. Thus, users can be
assigned to devices based on workloads, physical proximity, and Job-specific needs.
ArchiYifts. The system provides two levels of archivIng. The administrator can selectively backup Individual,
group and public work areas. 1bis grouping capability
simplifies the task for the administrators. While restorIng information, the administrator can read eit~~r the
whole archive or specific units. Additionally, indiVIduals
can backup and restore their own information on authorized resource devices.

• APPLICATION DEVELOPMENT TOOLS
AND 'SYSTEM FACILITIES
iMENU menu cIftelopment. The optional iMENU
facility, a version of /menus from Schmidt A'isociates.
allows users to create integrated. friendly. menu-driven
interfaces to XENIX application.'I. Programmers and
users can apply the !MENU facility in maintaining or
creating menus, forms or help screens for new and
existing applications.
Remote file transfer. The iXTRACf remote-file
tra:nsfer facility enables bidirectional tran.'Ifer of a "flat
file" to/from a mainframe host or a PC and converts the
file to/from the iDB relational databa.'ie format.
iXTRACf is Included in iBASE.
iRPC iBASE PC extelUliolUl. The optional iBPC
extensions provide the XENIX portion of PC connection
software, a menu-driven terminal emulation. file conversion and file transft"r facility. iBPC enables file sharing
between PCs and multiuser XENIX ~ystem'i. The user
can convert database and spreadsheet files from standard PC formats (Including Lotus 1-2-3. dBASE-II. and
Multiplan) to relational databa'ie formats during the
two-way file transfer. The package can be used in four
distinct modes: terminal emulation,local MS-DOS control, passthrough host sessions, and file tran.'Ifer Itransform operation.'i. The PC conne(:tion qperdtes either
over serial lines (direct or remote) or acros.'I the
OpenNET local area network The MS-DOS portion of
the PC connection software is provided by the optional
DOS-NET Virtual Terminal software.

• NE1WORK ADMINISTRATION
Network setup. The Network Administration features of iBASE provide network node setup. The network nodes can be identified as application vehicles or
public servers providing resources and other capabilities. In this way, the network administrator can optimize
network resource utilization.

Network ftII01Ifte definition md _ipmentll.
iBASE extends the concepts of a system resource by .
allowing the administrator to view the network as a
larger system. Thus, users with proper authorization can
perform' tasks such as printing or archiving on remote
nodes Independent of physical location.
Extending system tasks IICrOU the network.
Electronic office capabilities which were useful on a
single multiuser system take on a new dimension when
extended across the network Electronic mail is easily

!menus is a trademark of Schmidt Associates
Lotus Is a registered trademark of Lotus Development Corporation
dBASE II is a registered trademark of Ashton Tate
Multiplan and MS are trademarks of Microsoft Corporation

ORDERING INFORMATION
XNXIBASKERI
XNXIMENUKRI
XNXIBPCKRI
DOSNETVTSKRI

iBASE Base Application Software Environment object software and do~umentation (includes iXTRACT)
iMENU menu and forms development object software and documentation
iBPC iBASE PC ExtenSions
DOS·NET Virtual Terminal (formerly iPC)

2-43

in1:el
iRMX™
LANGUAGES

• Industry-standard languages and
utilities for developing applications on
iRMX-based systems. Includes .
FORTRAN, Pascal, C, BASIC, PL/M,
Macro ass~mbler,·AEDIT text editor .
• Complete set of utilities to create and
manage object modules

• Mix languages on single application
system with UDI standard
·hiteI8087 and 80287 math coprocessor

sUPPOI1
.• 8086 and 80286 compatibility
• Worldwide post-sales service and
support organization

(lIntel Corporation. 1985
'XENIX is a Il"ademark of Microsoft Corporation.
'tUNIX Is a trademark of Bell Laboratories.

2-44

Because the high-level languages are
actually resident on the iRMX-based
system, OEMs can pass application
software directly on to end users. End
users may then tailor the OEM's system
to better meet application needs by writing programs using the same languages.

Language-Independent
Application Development
Intel's Universal Development Interface
(UD I ) and Object Module Fc.rmat
(OMF) enable several users to write
different modules of an application, in
different languages, then link them
together.

Full Language Support
for iRMXTM -Based Systems
Intel's iRMX'M 86 and iRMX'M 286based systems are completely supported
by a wide variety of popular languages
and utilities with which to build fast,
real-time, multi-tasking applications. Included are the latest versions of
FORTRAN, Pascal, BASIC, PLiM and
Macro Assembler for Intel's 8086 and
80286 processors. Previously developed
applications using any of these
languages port easily to iRMXbased systems with minimal source
code modifications.
In addition to the wealth of languages
available, iRMX-based systems are complemented by utilities with which to
create and manage object modules. For
the iRMX 286 system, utilities which
allow system programmers to initialize
and manage the memory protection features of the 80286 transparently to the
applications programmer are pro- .
vided. This latitude in configurability
allows programmers to team their efforts
in order to achieve a shorter development
time than would otherwise be possible.

Standardized REALMATH
Support
All the iRMX languages (except BASIC
and C) support the REALMATH floating
point standard. This ensures universal
consistency in numeric computation
results and enables the user to take
advantage of the Intel 8087 and 80287
Nu"meric Data Processor or iSBX'" 337
MULTIMODULE'M boards, which boost
performance two to four times over that
possible on a mini-computer.

Complete Set of Program
Linkage and System
Building Utilities

The OMF provides users with the ability
to mix languages on a single application
system, affording the luxury of choosing
exactly the right language tools for
specific pieces of the application, rather
than compromising specialized tasks for
the sake of one, project-wide language.

Utilities for iRMX 86 operating systems include Intel's
own UNK 86, LOCATE
86 and UBRARIAN.
For iRMX 286 systems,
BIND 286 and BUILD 286
replace Link & Locate.

iRMX languages are fully compatible
with the Intel Series III/IV Development
System, should the user choose to develop
applications on a specialized development system. Applications are easily
moved to the final target system for test,
debug and minor redevelopment.

Using the UNK 86 or BIND 286
programs, users may combine individually compiled object modules to form a
single, relocatable object module. This
provides the ability to merge work from
several programmers into one cohesive
application system.

Fast, Lean Programs
for Rapid ProceSSing

The LOCATE 86 utility maps relocatable
object code into the processor memory
segments, allowing user definition of
module/memory type allocation. For
example, often-used portions of an application may be mapped to (P)ROM.

The iRMX language products enable
programmers to write the smallest",
fastest programs available in high-level
languages, due to the compiler's superior
ability to optimize code.

It is also possible to make iRMX
operating system calls directly from
FORTRAN, PASCAL, C and PLiM.
This means that application developers
can take full advantage ofthe iRMX
multi-tasking capability, whereby
multiple applications execute concurrently on the operating system. Multitasking, a requirement of most real-time
systems, is sometimes as necessary in
application software development as in
an operating system environment.

2-45

The BUILD 286 utility provides the major
capabilities of LOCATE. 86 plus allows
the system programmer to specify the
memory protection scheme for the
80286 system.
The UBRARIAN object code library
manager affords easy creation; collection
and maintenance of related object code to
reduce the overhead of separately maintained modules.

AEDIT
SCREEN
EDllOR

Finally,the MACRO Assemblers for the
8086 and 80286 processors generate

extremely efficient code and invoke
8086/8087 or 80286/287 machine
instructions.

iRMXTMPascal
iRMX Pascal meets the proposed ISO
language standard and implements
several microcomputer extensions. A
compile-time option cheeks conformance
to the standard, making it easy to Write
uniform code. Industry-standard specifications contribute to portability of application programs and provide greater
reliability.
iRMX PasCal supports eMensions,~
such as an interrupt-handler and direct

port 1/0 extension. "that allow programs
to be wriiten specifically for micro-

computers. Separate module compilation
allows linkage of Pascal modules with
modules Written in other high-level
languages.

IRMX™ FORTRAN
The iRMX FORTRAN compiler provides total compatibility with FORTRAN
66 language standards, plus most new

2-46

features provided by the FORTRAN 77
language standard including complex
numbers.iRMX FORTRAN includes
extensions specifically for microcomputer application development. Programming is simplified by relocatable""
object libraries. which provide run-time
"support for execution time activities.

iRMX FORTRAN 86 supports the 8087
math coprocessor and iRMX FORTRAN
286 supports the 80287 for the most powerful microcomputer solutions available
in number-intensive applications.

iRMXTI! PL/M
PLIM offers full access to micro-computer architecture while simultaneously
offering all the benefits of a high-level
language. Invented by Intel in 1976,
PLIM 80 was the first microcomputerspecific, block-structured, high-level
language available. Since then, thousands of users have generated
ode for millions of microcomputerbased systems using PLIM 80,
PLIM 86, and PLIM 286.
Software written for 8-bit
processors (PLIM 80)
are easily ported to the
more powerful 16-bit
(PLIM 86) environment. The
, same portability is available for the
80286 (PLIM 286).

iRMX™ BASIC
Intel's offering of Microsoft BASIC 86 is
a standardized version of the most popular
high-level language in the world. Existing BASIC programs are easily ported to
iRMX-based systems. BASIC is an excellent pass-through language by which
an OEM can offer customers the ability
to write and modify their own
applications.
.

iRMXTII C Compiler
The popular programming language C, is
fully supported on iRMX-based systems.
iRMX C offers both small and large
segmentation models, enabling applications to be written efficiently. The iRMX
C compilers combine assembly language
efficiency with high-level language convenience; it can manipulate on a machineaddress level while maintaining the
power and speed of a structured
language.
'

iRMX™ AEDIT Text Editor
The iRMX AEDIT Text Editor is screenoriented, menU-driven and easy to learn.
Guided by the menu I)f commands always before him, the user can edit text
and programs easily and efficiently.
iRMX AEDIT Text Editor allows the
simultaneous edit of two files. This allows
easy transferral of text between files and
use of existing material in the creation of
new files. Creating macros, strings of
frequently-used commands, is also very
simple. The editor' 'remembers" the
.selected commands and allows the user to
re-use them repeatedly. The
iRMX 286 version also
supports operating system
level command execution.

iRM)(TII 286 Soft-Scope· 286
High Level Language Debugger
The Soft-Scope 286 debugger allows
debugging programs running on the
iRMX 286 Operating System. Programs
written in PLiM 286, FORTRAN 286,
PASCAL 286, and C 286 can be debugged using source
code listings.

Intel Has Total Solutions
for Real-Time Systems
iRMX 86 and iRMX 286 are the fastest,
most powerful operating systems available
for multi-tasking, multi-user, real-time
applications. Complemented by a wide
range of industry-standard languages and
utilities, the iRMX-based systems are
highly flexible and configurable. '
Application development for iRMXbased systems is possible at the board or
the system level. OEMs can integrate
functionality at the most profitable level
of product design, using one system for
both development and target use. Intel's
choice of industry standard high-level
languages enables the end user to extend
OEM-provided functionality even
further, if desired.
Who is better qualified to write and supply software for Intel VLSI than Intel?
Today you have the ability to tap into
hundreds of available application software packages, languages and utilities,
peripherals and controlle~ and
MULTlBUS® boards.
Tomorrow, and ten years down the road.
you will be able to tap into the latest,
high-performance VLSI-without losing
today's software investment.

Worldwide Service
and Support
All iRMX systems are completely supported by Intel's worldwide staff of
trained hardware and software engineers.
Support available includes Hotline (telephone) Support, Software Updates, and
a Subscription Service.
Complete documentation is provided for
all operating system and application
software languages, as well as for system
hardware components. An Intel system is
not a collection of hardware and software
pieces as much as a cohesive whole that
is supported and serviced as such.

The iRMX C compiler affords easy
portability of existing C programs to
iRMX-based systems.

~§iRMXTlANGUAGE~
--•

.Sof!·Scope. is a registered trademark of Concurrent Sciences. Inc.

2-47

Specifications
Required Hardware

Required .Soflware

Data Sheets

o Any 8086/286/386 based or iSBC 86/
286/38.6 based system,including Intel's
System 86/300, 286/300 and 386/300
family. In addition, object code from the
8086 compilers will run on 8088, 80186
or 80286 based systems.
o 700KB of memory
o 1\vo iRMX compatible floppy disks or
one hard disk
o One 5.25" double-density floppy disk
drive for distribution of software
o System console device

The iRMX 86 Operating System Release
7 or later including the Nucleus, Basic I/O
System, Extended I/O System and Human
interface layers.

o 8086 Compilers:
8086/8811861188 Software Packages
(Intel order number 210689)

-orThe iRMX 286 Operating System inc1uding the Nucleus, Basic I/O System, Extended I/O System and Human Interface.

• 80286 Compilers:
80286 Software Development Tools
(Intel order number 231665)

Purchasing of any iRMX 86-resident
language requires signing of Intel's Software License Agreement (SLA). A software license is shipped with each iRMX
286·resident language.

Ordering Information
IRMX 86 LANGUAGES

IRMX 286 LANGUAGES

ASM 86, Utilities

R86ASM 86

ASM 286, Utilities

R286ASM286

FORTRAN 86

R86 FOR 86

ASM 86, Utilities

R286ASM 86

PLlM86

R86PLM86

AEDIT Text Editor

R286 EDI 286

AEDIT Text Editor

RMX864

PLlM286

R286PLM286

BASIC 86

RMX 865

FORTRAN 286

R286 FOR 286

Pascal 86

R86 PAS 86

Pascal 286

R286 PAS 286

C86

R86C 86

C286

R286 C 286

Soft-Scope' 286

R286 SSC 286

2-48

intel

Application Scrt'ices

OFFICE

PRODUCfIVI1Y
IDOLS
~ FrlendJy, easy-to-use
~ AJpIieations access Jrom

menus

Integrated office productivity tools with
.. on-line help facility
~ FuJIy relational DBMS option with report
writer and forms input .
~

worcqwocessor

~
~
~

Spreadsheet
Enhanced electronic mail
Personal calendars with group scheduling
OpenNET.M local area netuJoril
compatible

• iWORD WORDPROCESSOR

• INTEGRATED OFFICE
PRODUCTM1Y TOOLS

The iWORD package, a version oftbe Latitude" Wordprocessor from LatiCorp, Inc., is a powerful fuD-function
wordprocessor with mailmerge, spell checking and an
.integrated tabulator (spreadsheet). The wordprocessor
supports all standard text editing. storage and formatting functions: File management and editing concepts.
are very easy for beginning users yet powerful enough
for experienced users. The software allows users to
visually format documents and print them as they are
displayed on the screen

Intel offers an integrated set of office productivity tools
consisting of a databasC: management system, wordprocessor, desktop organizational utilities and spreadsheet.
Data can be interchanged among the iWORD Wordprocessor, the iPLAN Spreadsheet and the iDB Database
Syst~. These, together with the on-line help filcility,
prOVide an easy-to;use powerful set of decision support,
analysis and productivity tools.

• iDS DATABASE MANAGER
AND REPORT WRITER

• iDESK DESKTOP ORGANIZATIONAL UTILITIES
The iDESK Desktop Organizational Utilities, a version
of SYNC": The Executive Desk from LatiCorp Inc.,
provides an enhanced set of office automation capabilities. iDESK provides an enhanced electronic mail interface, additional calendar capabilities including group
. scheduling, reminders and telephone message facilities. iWORD is a prerequisite of iDESK.

The iDB database management system is a full-function,
mainframe-caliber relational DBMS that supports an
interactive querylupdate language which is a functional
superset of mM's SQL The Report Writer package
included with iDB allows users to prepare custom
reports quickly. iDB, Inters version of the Empress'
databasC: management system from Rhodnius, Inc., aJso
features a user-prompting data entry and update: subsystem, a bulk loading and unloading utility for rapid
transfer of data among files and databases, extensive
on-line help facilities, and programmatic interfaces to
the C language and XENIXt shell.

JUNE,I986
e INTEL CORPORAnON. 1986
"EMPRESS IS It. TlW>l!MAJlK Of RHODNIU5, INC.
tXENlX IS A REGISTERED TRADEMARX OF MICROSOFT CORPORATION

ORDER NUMBER: 270211-001

"l.A.1TnJDE IS It. REGISTERED TRADEMARK OF UllCORP. INC.,
nNC IS A TIlADI!MAIlK OF lAncoRP, INC.

2-49

inter
• iPLAN SPREADSHEET
The iPIAN Spreadsheet, a version of Microsoft's Multiplant, is a powerful easy-to-use "electronic worksheet"
that supports 'what-if decision modeling using simple
English commands. This two-dimensional matrix can be
tailored to a variety of applications including financial
modeling, tabulations and formula calculations. Up to

eight windows are available for both vertical and
horizontal scrolling and as many as eight interrelated
worksheets can be linked and updated. iDB SQL queries
can be embedded in iPIAN cells to ensure spreadsheet
analysis utilizes current database data.

tMulliplan L\ a n:p;iM(Orcd tralkmark or Mi<:rnsoft Cmpllralion

ORDERING INFORMATION
XNXIBASEKRI
XNXIDBKRI
XNXIWORDKRI
XNXIDESKKRI
XNXIPIANKRI

iBASE Base Application Software Environment object software and documentation
(includes iXTRACT)
iDB relational database management and report writer object software and
documentation
iWORD word processor object software and documentation
iDESK desktop organization utilities object software and documentation
iPIAN spreadsheet object software and documentation

2-50

HIGH PERFORl'tIAN£E MultiSERVERTH

HmHPERmRM~N~M~n~R~Rm

MultiSERVER is an effective way to link PC·s. terminals. minicomputers. mainframes and
applications into an organizationally productive departmental services system. Intel combines
the power of its high performance System 320. its complete network service software and its
comprehensive customer support capabilities to deliver. install and maintain a.complete
DEPARTMENT SERVICE NETWORK.

MultlSERJ'ERTH SYSTEM 320 I'E~TlJRES
• Complete Department Service Network
File Services
Print Services
Communication Services
Network Application Services
Administrative Services
Compute Services

• Complete Installation. Service and Support
• Range of Configurations

imJ-------------------Intd C:llrjlllr'.~"" ~ "'~.,.,'~

unlF!:l

sea ..

Choice of packages in most application areas

Choice of application development tools

Major software packages available directly from Intel

Worldwide support available for many software
packages

CATEGORY

PRODUcr NAME

VENDOR

Accounting

MCBA Accounting
BACS Accounting
Cone tic Accounting
Thoroughbred Accounting
Open Systems Accounting
MBSI RealWorid Accounting

MCBA
American Business Systems
Cone tic Systems
Concept Omega
Open Systems
Megascore

Application Tools

APPGEN Application Generator
ApPGEN Query Language
*iMENU

Communications
Database Management

Fusion

Network Research Company

PROGRESS
C-ISAM
File IT!
* Informix
Informix SQL
* iDB (Mistress)
MOBS III
Unify
21M
FoxBASE

Data Language
Relational Database Systems
Relational Database Systems
Relational Database Systems
Relational Database Systems
Conetic Systems
Intel
Micro Data Base Systems
Unify
2anthe
Santa Cruz Operation

* PBG200
* PBG Subroutine Libraries
* High Tech Business Graphics
GraphHopper
Grafsman

Pacific Basin Graphics
Pacific Basin Graphics
High Tech Marketing
Data Business Vision
Southwind Software

C/Tools

Graphics

Software Express
Software Express
Intel

JANUARY, 1987
ORDER NUMBER: 270128-003

2-53

inlet
CATEGORY

Languages

PRODUcr NAME

• ASM286 Assembler/RL286
* ASM386 Cross Assembler
... Mark Williams 'C'
• Fonran-286
• MicroFocus Cobol
* Microsoft Basic
·cENGUSH
* dBASE II to cENGUSH
* PL/M-286
... PL/M-386 Cross Compiler
CCSBasic
DB/C (Databus Compiler)
DBL (Dibol)
Microsoft Fortran
Pascal
RM Cobol
RM Fortran
* Softbol
Thoroughbred Basic
UX Basic
Unilisp

VENDOR

Intel
Intel
Intel
Intel
Intel
Intel
cUNE

cUNE
Intel
Intel
ControlC
Subject Wills & Company
DISC
Microsoft
Human Computing Resources
Ryan Mcfarland
Ryan Mcfarland
Omtool
Concept Omega
Human Computing Resources
R/L Group

Manufacturing

Manufacturing Control Systems

Micro Manufacturing

Medical

MDX

Clinical Data Design

Office Automation

*iWORD
... Q-Office
R Office
Lex86
Sofgram
CrystalWriter
... Lyrix

Intel
Quadrl\tron
R Systems
SofI'est
SofI'est
Syntactics
Santa Cruz Operation

Personnel

Personnel Searcher

NMI

Project Management

VUE

National Information Systems

Publishing

Circulation Management
SofI'ype

NMI
SofI'est

Spreadsheet

... iPLAN (Multiplan)
20/20
UltraCalc
SCO Professional

2·54

Intel
Access Technology
Olympus Software
Santa Cruz Operation

APPLICATION
NOTE

AP-405

May 1987

Software Migration From
iRMX® 86 to iRMX® 286

MAYNE MIHACSI
OSD Technical Marketing

INTEL CORPORATION, 1987

Order Number 280608-001

2-55

AP-405
INTRODUCTION
The iRMX® 286 operating system represents the evolution of the iRMX® 86 operating system to the protected-mode
80286 and 80386 microprocessors. Therefore, the iRMX 286 operating system has most of the same features of its 8086
counterpart.
Many Intel customers are going to migrate their software from iRMX 86 to iRMX .286. Most customers should be
pleasantly surprised at the ease of migration .between the two operating systems. This compatibility between. the two
operating systems was a key objective of the iRMX 286 project. Thus in the majority of cases, an iRMX user should
encounter no changes or only trivial changes when porting their software to iRMX 286. In the other cases, iRMX users
with a little patience, work, and the help. of this paper, should quickly have their application running on iRMX 286.
Before reading this migration note, it is strongly suggested that readers acquaint themselves with the fundamentals of the
80286 architecture.

iRMX® 286 SYSTEM ARCHITECTURE
There are inherent differences between iRMX 86 and iRMX 286 due to the differences in microprocessor architectureS.
To take advantage of some unique 80286 features additional system calls have been added in the iRMX 286 operating
system. These new calls can be identified by an RQE$ in their preface, with the E denoting "extended", to take advantage
of the 80286's 16MB addressability.
Figure 1 lists the differences for each layer of iRMX 286.

iRMX® Layer

iRMX® 286 Changes

Nucleus

BIOS

- Memory buffer protection

EIOS

- Newcalls
- Memory buffer protection

Application Loader

- Only loads 80286 OMF records
- Only loads STL modules
- Newcalls

Human Interface

- Enhanced eLi
- New commands

UDI

- Newcalls

Bootstrap Loader

- New third stage interface

leu

- Single stage leu

16MB address space
New hardware traps
Descriptor management
Privilegeh,anagement
Round robin scheduling
Interrupt management
Newcalls

Figure 1. iRMX® 286 Architectural Differences

2-56

280608-001

AP-405

iRMX® 286 NUCLEUS
16 Megabyte Address Space
Today's applications have pushed beyond the 1MB memory limitation of the 8086 architectures. Many Intel customers
have chosen iRMX 286 simply because of its ability to address 16MB of memory. While the 80286 architecture allows for
accessing 24 physical address lines, to yield 16MB physical and 16MB virtual addressability, the operating system is not
automatically allowed the same abilities. As further generations of CPUs become available and memory becomes cheaper,
operating systems will strive toward hardware independence. One method used is accessing memory logically, not physically. In the iRMX 286 operating system all memory addresses are logical addresses available via a descriptor table. A
logical address may be thought of as a pointer consisting of a selector and an offset. The selector will point to an entry in a
descriptor table containing the 24-bit physical address. Therefore, tokens are affected by containing selectors that reference an entry in the descriptor table. No longer do tokens contain the physical address of an object.

New Hardware naps
Because the 80286 processor detects several types of exceptions and interrupts from exceptions, iRMX 286 also alerts
programs generating these exception conditions. These hardware traps will be generated from the following conditions:
INTERRUPf
VECIDR

FUNCTION

8
9
10
11
12
13

Double exception
Processor extension segment overrun
Invalid task state segment *
Segment not present *
Stack segment overrun or not present
General protection
.

*Seldom seen
Users porting iRMX 86 code to iRMX 286 should be aware that the working code in iRMX 86 might still contain errors
that will be "trapped" iniRMX 286.

Descriptor Management
While the 80286 CPU is in Protected Virtual Address Mode (PVAM), all application programs deal exclusively with
logical addresses. That is, the programs do not directly access actual physical addresses generated by the processor.
Instead, a memory-resident table, called a descriptor table, records the mapping between the segment address and the
physical locations allocated to each segment. Whenever the 80286 decodes a logical address, translating a full 32-bit
pointer into a corresponding 24-bit physical address, it implicitly references one of several descriptor tables. One table is
called the Global Descriptor Table (GDT) and provides a complete description of the global address space. Another table
is provided, the Local Descriptor Table (LDT), to describe the local address space for one or more tasks. To the application programmer, much of the internal operation and management of the descriptor tables are transparent. However, the
systems programmer will need to manage the descriptors to:
A. Gain access to undefined or allocated memory areas, and
B. Add device drivers to the system.
Several new calls were added to help manage descriptor tables:
I.

RQE$CREATE$DESCRIPTOR

RQE$CHANGE$DESCRIPTOR

RQE$DELETE$DESCRIPTOR

For the applications programmer several features are available in iRMX 286.
I.

Of the maximum 8K objects available, all are indexed in the GDT with the operating system using the LDT.

While using an iRMX 86-style task switch, iRMX 286 runs as one 80286 hardware task.

2-57

280608·001

AP-405

Privilege Management
Some means of protection is required to prevent programs from improperly using code or data that belongs to the
operating system. The four privilege levels of the 80286 are numbered from 0 to 3, where 0 is the most trusted level. The
privilege level is an attribute assigned to all segments in a hierarchical fashion. Operating system code 'and data segments
are placed at the most privileged level (0) which is where iRMX 286 operates. (See Figure 2.)
The privilege levels apply to tasks and three types of descriptors:
1.

Main memory segments

2. Gates
3.

Task state segments (not used in iRMX 286)

Of particular interest to discussions concerning iRMX 286 is the gate descriptor and its usage in application programs.
Of the four types of gates in the 80286 processor, iRMX 286 uses call gates. Once invoked, control is transferred using
only the selector portion. This address becomes fixed, allowing any program to invoke another. This prohibitS tasks iliat
have not used these entry points from jumping into the middle of the operating system. The use of gates is fundamental to
the 80286 architecture and is reflected in other areas of iRMX 286.
All iRMX 286 system calls go through a call gate in order to invoke a given service procedure. In the iRMX 86 operating
system, all calls were through software interrupts, invoking an operating system extension handler, then finally the service
procedure. For iRMX code that was written for the iRMX 86 operating system, this will have little impact until it comes
time to build'the system, unless a conflict exists between the old and new nucleus calls: (See next section.) Analogous to
the iRMX 86 operating system having a software interrupt at. each level, iRMX 286 possesses call gates for each system
call at each layer of the operating system, eliminating the need for an operating system extension handler. Call gates can'
be specified through system calls and the Interactjve Configuration Utility (ICU). (See the example for RQE$SET$OS$
EXTENSION.)

TASK A

Figure 2. Example Privilege Level Assignments

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IRMX~86

System
Calls

••
•

(

Software
Interrupt

Extension
Handles

)

Service
Procedures

IRMX~286

System Call

-------i~~

Call Gate

------.~

Service Procedure

System Call

------~

~
Call Gate - - - - - -..

Service Procedure

System Call - - - - - - . . Call Gate - - - - - - . . . .

Service Procedure

Call Gates vs. Software Interrupts

Round Robin Scheduling
The iRMX 286 operating system schedules tasks based upon tasks competing for CPU resources. Th prevent the occurrence of one or more tasks waiting indefinitely, round robin scheduling is available on the iRMX 286 operating system.
One area that could benefit from this scheduling scheme is multi-user environments.
Round robin scheduling will permit equal priority tasks a finite tiq1e they may have control of the processor. Once the time
expires, the task with the same priority and ready will gain CPU control. Hardware interrupts and higher-priority tasks
can still bump any of the lower-priority tasks from running. This scheme allows all equal priority tasks an opportunity to
execute.
This scheduling is determined in the "nucleus" screen of the Interactive Configuration Utility (lCU). (See the iRMX 286
Interactive Configuration Utility Reference Manual for details.)

Interrupt Management
In the iRMX 286 operating system interrupt management has changed. In the iRMX 86 operating system an interrupt
vector table contains the address of aninteriupt handler. In the iRMX 286 operating system this table. has been called the
Interrupt Descriptor Thble (lOT) and is very similar to the GOT and LOT, except that it is referred to only when an
interrupt occurs. Interrupt addresses can be entered into the lOT when using the iRMX 286 SET$INTERRUPr nucleus
system call. Entering interrupts is still identical for both operating systems, however, with PL/M 286 not having a
SET$INTERRUPr built in, interrupts have become easier to use. (See the section on PUM 286.) The following is' a
description of the allocated interrupt entries. (Also see the section on BUILD 286 for another way to set interrupts.)

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Entry Number

o
1

2
3
4

5
6
7

8
9
10
11
12
13
14-15
16

17-55
56-63
64-127
128-255

iRMX® 286 Interrupt Allocation Description

Divide by zero
Single step (used by iSDMTM 286)
Power failure (non-maskable interrupt, used by iSDMTM 286)
One-byte interrupt instruction (used by iSDM 286)
Interrupt on overflow
Run-time array bounds error
Undefined opcode
NPX not present/NPX task switch
Double fault
NPX segment overrun
Invalid TSS
Segment not present
Stack exception
General protection

NPXerror

8259A PIC master
8259A PIC slaves
* Available to users *

New Calls
GENERAL RULES

IMPORTANT
. Here are some general rules to apply.
1.

All iRMX 286 system calls beginning with RQ$ ... are 100% compatible with iRMX 86.

All iRMX 286 system calls beginning with RQE$ ... are new to iRMX and exist only in iRMX 286.
a. All iRMX\86 system calls beginning with RQ$ ... for which there is a like iRMX 286 system call beginning
. with a RQE$ .. ; use the function procedure of the RQE$; .. call.

All iRMX 286 system calls and user extensions use call gates.

All iRMX 86 BIOS, EIOS, and loader calls are 100% compatible with iRMX 286 calls.

All objects are identified by 16-bit tokens which represent an entry in the Global Descriptor Table (GDT).

The iRMX 286 system call RQE$SET$OS$EXTENSION must be used in place of
RQ$SET$OS$EXTENSION. This call dynamically attaches an. operating system extension to a call gate.
A few specific 'system calls merit further discussion.

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RQE$SET$OS$EXTENSION
This system call as mentioned in Rule 6 above will find the following usage.
DECLARE
. Typical PUM 286 statements
MY$OS$EXT: PROCEDURE EXTERNAL;

. Typical PUM 286 statements
END MY$OS$EXT;
CALL ROE$SET$EXTENSlON (0141H, @MY$OS$EXT, @STATUS);
Where: 0141 H represents the entry number of the call gate from the GDT. This parameter is named
GATE$NUMBER.
@MY$OS$EXT represents the pOinter to first instruction of MY$OS$EXT. This parameter is
named START$ADDR.
@STATUS represents a pointer to a word containing the condition code for this call. This parameter is named EXCEPT$PTR.
A user-written operating system extension can also be attached to a call by the Interactive Configuration Utility (ICU).
Example of an ICU screen:
OS Extension
(GSN) GDT slot number
(OCN) entry point name

[0140H-01 FFEH) 0141 H
[1-45 characters) MY$OS$EXT

Enter changes [Abbreviation ?I = NEW_VALUE):
Do you need any more O.S. extensions?
This causes the GDT slot 141H to'be configured as a call gate whose entry point is MY$OS$EXT.

RQE$CREATE$JOB
This call is an example of Rule 2a where two calls perform nearly the same function. In this case the extended versions of
POOL$MIN and POOL$MAX parameters are DWORDS instead of WORDS. This is to allow a memory pool of up to
16MB for tasks and objects. While RQ$CREATE$JOB will create a memory pool of up to 1MB, it will use the same
function procedure as RQE$CREATE$JOB. This is possible because the RQ$CREATE$JOB interface procedure changes
the word pool parameters to DWORDS by padding them with zeros, then calling the RQE$CREATE$JOB function
procedure.

RQ$CREATE$SEGMENT
This call's first parameters, SIZE, yields a different value than in iRMX 86.
In iRMX 86:
Where:

In iRMX 286:
Where:

Segment = RO$CREATE$SEGMENT (SIZE, EXCEPT$PTR);
SIZE is a word containing the size, in bytes, of the requested segment in MULTIPLES OF
16 BYTES.
SEGMENT

= RO$CREATE$SEGMENT (SIZE, EXCEPT$PTR);

SIZE is a word containing the actual memory size in bytes.
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RQ$GET$POOL$ATTRIB
In this case more parameters have been added.

In iRMX 86:

RQ$GET$POOL$ATTRIB (ATTRIB$PTR, EXCEPT$PTR);

Where: ATTRIB$PTR is a pointer to the following structure.
Structure (POOLMAX WORD,
POOLMIN WORD,
INITIAL$SIZE WORD,
ALLOCATED WORD,
AVAILABLE WORD);
In iRMX 286:

RQE$GET$POOL$ATTRIB has a different structure though everything else is the same
Structure (TARGET$JOB TOKEN,
PARENT$JOB TOKEN,
POOLMAX DWORD,
POOLMIN DWORD,
INITIAL$SIZE DWORD,
ALLOCATED DWORD,
AVAILABLE DWORD,
BORROWED DWORD);

RQ$SET$INTERRUPT
Users should also be aware of the following when using this call in iRMX 286. When specifying interrupts in iRMX 286,
a special descriptor table called the Interrupt Descriptor Table (lOT) is located at a user-specified address in memory. Thistable is accessible through an entry in the Globa\ Descriptor Thble (GDT). This makes an interrupt procedure entry point
to be directly accessed via a jump to.the specific SELECTOR:OFFSET pointer in the lOT. All interrupts will have a
SELECTOR:OFFSET address just as in the iRMX 86 operating system. Therefore, the system calls syntax will remain
the same, except the parameter called INTERRUPI'$HANDLERas shown below:

Example: iRMX 286
CALL RQ$SET$INTERRUPT (LEVEL, INTERRUPT$FLAGS, 'INTERRUPT$HANDLER,
INT$HANDL.ER$DS, EXCEPT$PTR);
Where INTERRUPT$HANDLER, the entry point to the interrupt handler, should be coded directly, i.e.,
@MV$HANDLER.
By referencing a handle~ directly, all oilier intennediatesteps ~re unnecessary. (See the example in the PLlM,286 section.)

BASIC INPUT/OUTPUT SYSTEM (BIOS)
The BIOS of the iRMX 86 operating system is nearly identical to the iRMX 86 operating system BIOS. The same system
calls are available with no changes or additions. The significant differences between the two BIOS's are the. 16MB
addressability and memory protection available in the iRMX286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system BIOS protects the code and data by preventing any task
from reading or writing a segment of memory unIe.ss explicit access has been granted. It also prevents memory reads or
writes from crossing segment boundaries. Therefore any task using the A$READ or A$WRITE BIOS system calls must
have read or write access privileges.

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Device Drivers
Not all iRMX 86 operating system device drivers have been included in the iRMX 286 operating system. Consult the
following list or the iRMX 286 Interactive Configuration Utility for the specific Intel-supplied drivers.
Intel Device Drivers Supplied With iRMX® 286 R. 2.0

iSBC® 215G
iSBC 214
iSBXTM 218A
iSBX217C
iSBC 220
iSBC208
iSBX251
iSBC 264
iSBX 350 Line Printer
Line Printer for 286/10

iSBC 534
iSBC 544
Terminal Comm Cntlr
to include:
iSBC 188148
iSBC 188/56
iSBC 546
iSBC 547
iSBC 548
8274
8251A
82530
RAM disk

iSBC 286/10
iSBC 286/10A
iSBC 286/1 X
iSBC 386/2X

Not included are the following device drivers:
iSBC 204
iSBC 206

SCSI
iSBC226

EXTENDED INPUT/OUTPUT SYSTEM (EIOS)
The EIOS of the iRMX 286 operating system is nearly identical to the iRMX 86 operating system EIOS. The same system
calls are available with few changes and additions. The significant differences between the two EIOS's are the 16MB
addressability and memory protection available in the iRMX 286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system EIOS protects the code and data by preventing any task
from reading or writing a segment of memory unless explicit access has been granted. It also prevents memory reads and
writes from crossing segment boundaries. The system calls S$READ$MOVE and S$WRITE$MOVE are two calls that
will send an exception code called. E$BAD$BUFF whenever this occurs,·

Extended Memory Pool
Since the iRMX 286 operating system supports the 16MB addressability of the 80286 processor, the memory pools
created by I/O jobs can also be as large as 16MB. The new system call providing this feature is called RQE$CREATE$
1O$1OB.

New Calls
Several new system calls have been added to the iRMX 286 operating system EIOS layer. They are:
1.

RQE$CREATE$IO$1OB
POOLMIN and POOLMAX parameters changed to DWORDS for 16MB addressability.

RQS$GET$DlRECTDRY$ENTRY
Retrieve name of any file in a directory.

RQS$GET$PATH$COMPONENT
Retrieve name of any file as it is known in its parent directory.
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iRMX® 286 APPLICATION lOADER
802860MF
Two utilities are supplied with the iRMX 286 operating system to load programs and data into system memory from
secondary storage devices. They are the bootstrap loader and the application loader. Typically the bootstrap loader is used
to load the initial system and begin its execution. The application loader will typically be called, by programs running in
the system, to load additional programs. The application loader can load I/O jobs up to 16MB. These programs must be in
the 80286 Object MOdule Format (OMF). This differs from the iRMX 86 operating system, which loads only 80860MF
records. Further, the 80286 records must be in STL format. (See a later section called BND 286 for a discussion of STL
format.)

New Calls
RQE$A$LOAD$IO$JOB

This calls memory pools changed to DWORD values from word. (See RQE$CREATE$JOB call in the Nucleus section.)

RQE$S$LOAD$IO$JOB

Same as above.

HUMAN INTERFACE
Enhanced Command Line Interpreter (Cll)
The new CLI provides line-editing features, as well as its own set of commands. With CLI commands, aliases
can be created, background programs ran, output redirected or redefined for a terminal in the configuration file. The
commands are:

ALIAS
HISTORY

BACKGROUND
JOBS

KILL

CHANGEID
LOGOFF

SET

DEALIAS
SUBMIT

EXIT
SUPER

To include or customize features in the CLI, user extensions have been added to the Human Interface.

New Calls
ADDLOC

LOGOFF

SHUTDOWN

LOCK

UNLOCK

ZSCAN

Old Calls
The following Human Interface commands have been revised:

BACKUP

DISKVERIFY

FORMAT

2-64

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UDI
New System Calls
The iRMX 286 UDI contains three system calls not contained in the iRMX 86 UDI. They are:
DQ$MALLOCATE
DQ$MFREE
DQ$GET$MSIZE
All of the calls have their counterparts in the iRMX 86 UDI, however, the new system calls use full pointers instead of
selectors and DWORD instead of WORD for memory block start address and size specifications, respectively.
These three calls are only supported in programs compiled in the compact or large segmentation models. Also, earlier
versions of these calls cannot be mixed. For example:
After using DQ$MALLOCATE to allocate memory, do not use DQ$FREE to free it.
Use DQ$MFREE instead.

BOOTSTRAP LOADER
Two Stage Loader
To facilitate loading an application so that it may execute has been known as "pulling it up by its bootstraps" or simply
"booting" the application. iRMX bootstrap loaders have been divided into stages, each possessing a unique purpose
and role.
In the iRMX 86 operating system, the bootstrap loader exists as only two stages. The first stage resides in PROM located
on the CPU's board. If supplied by Intel, it will occupy less than 8Kb of memory within the PROM. Once running, it will
identify the applications name and location, then load part of the second stage, passing control to it. The second stage
finishes loading itself, loads the application into memory, then passes control to the application. While the first stage is
user-configurable, the second stage is not. The second stage is only supplied by Intel and is present on all iRMX
formatted, named volumes.

New Third Stage
In the iRMX 286 operating system, the bootstrap loader exists as three stages. The extra stage was added to be able to load
80286 OMF files. This will also permit loading 8086 OMF files with just the first and second stages. This means either
system can be booted without compromising the other. To allow for this, some files have to be renamed and some new
conventions adopted. (See below and Figure 3.)
1.

All 80286 OMF bootloader application systems must have the extension" .286".

The third stage bootstrap loader must have the same name as the application, less the extension.

The third stage bootstrap loader must reside in the same directory as the bootloadable system.

File Name Conventions

Third Stage

System to be Loaded

ISYSTEM/RMX86

ISYSTEM/RMX86.286

ISYSTEM/RMX

ISYSTEM/RMX.286

IBOOTlRMX286

IBOOT/RMX286.286

This chart indicates to those wanting to boot the iRMX 86 operating system that their file ISYSTEM/RMX86 had better
be renamed to avoid confusion.
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INPUT
OR

lSI STAGE
ON·BOARD
PROM

iRMX' FORMATTED
VOLUME WITH
IRMX· 286
BOOTSTRAP 2nd STAGE

IRMX· FORMATTED
VOLUME WITH
iRMX·286.
BOOTSTRAP 2nd STAGE

m·0803

Figure 3.
When installing the iRMX 286 operating system on a system containing the iRMX 86 operating system, the "BS" option
of the format command will install ONLY the new second stage bootstrap loader on track 0 of the hard disk. The
installation process will also add new directories as required by the iRMX 286 operating system.

Memory Locations of the Three Stages
Bootstrap Loader Locations
Description

Default

Approx. Size

1st STAGE CODE

Application
dependent

12KB

BS1.CSD

2nd STAGE CODE
1stl2nd DATA
and STACK

OB8000H

8KB

BS1.CSD

3rd STAGE
(specific) CODE
DATA and STACK

OBCOOOH

16KB

BS3.CSD

3rd STAGE
(generic) CODE

OBCOOOH

8KB

BG3.CSD

3rd STAGE
(generic)
DATA and STACK

OB8000H

BG3.csd

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CONFIGURATION SIZE CHART

iRMX® 286
Memory
Requirements

Operating
System
Layer
Nucleus
BIOS
EIOS
Application Loader
HI
UDI

34K
95K
19K
12K
36K
11K

Bootstrap Loader

leu

IRMX® 86Code
Size

iRMX® 286Code
Size

24K
78K
12.5K
10K
22K
8K
1.5K

27K
67K
16K
11K
26K
9.4K
32K

iRMX® 86Data
Size

iRMX® 286Data
Size

2K
1K
1K
2K
15K
OK
6K
308K

3.5K
19.5K
16.75K
2K
1K
O.1K
6K
384K

"These numbers reflect actual memory size required to support the different configurations of the operating systems.

FILE STRUCTURE
The file system of the iRMX 286 operating system provides for the same types of files as are on the iRMX 86 operating
system. In fact, both file systems can exist on the same volume using the same hierarchical file structure. This is made
possible through the installation of the iRMX 286 bootstrap loader's second stage onto the iRMX 86 operating system's
volume. This second stage will allow either· operating system to be booted from the same volume. One fact should be
remembered: iRMX 286 uses the 80286 OMF, while iRMX 86 uses the 8086 OMF. This stops either operating system
from loading and executing the other's files or programs. Copying, deleting or other maintenance operations can still be
accomplished across the volume. iRMX 286 operating system will also read iRMX 86 back-up format files from another
volume. The following Figure 4 shows a file system with both operating systems installed, including the changes to its
structure. Remember, iRMX 286 can reside by itself or with iRMX 86 on the same volume.

Conventions
New file conventions have been adopted to differentiate between several types of files. They are:
*.P28
*.P86
*.A28
*.A86
*. GAT

PLiM 286 source files
PLiM 86 source files
ASM 286 source files
ASM 86 source files
Gate definition files

*.BLD -

Build, file for BLD 286

*.286

Bootable iRMX 286 system file

* .86

Bootable iRMX 86 system file

After booting iRMX 286, the following assignments are assumed:
: SYSTEM:

ISYS286

: UTIL:

IUTIL286

: LANG:

ILANG286

After booting iRMX 86, the following still apply:
: SYSTEM:

ISYSTEM

: UTIL:

IUTILS

: LANG:

ILANG

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iRMX® 86.86
DIR
COPY
SUPER

~DIR

COPYDIR

~COPY

"II

f\)

m
ex>

cO'

iil
f""

"'"

(II

• Denotes file additions
Diagram reflects the installation of iRMX® 286
upon an iRMX® 86 volume.

'"o'"~
~
~

m-OaO? .

AP-405

LANGUAGES: ASM 286
Because ASM 286 supports the 80286 in protected mode, ASM 286 has more changes than other languages. Often users
converting their programs to ASM 286 from ASM 86 will assemble the programs in ASM 286 and store the error
messages generated and change the code accordingly. A few notable changes are listed below.

Group Directive
ASM 286 does not possess a group directive as in ASM 86. By giving the segments the same name, they will be grouped
together into one segment at link time.
Example: ASM 86
DATAGRP GROUP DATA 1, DATA2
DATA 1 SEGMENT
ABYTE DBO
DATA1 ENDS
DATA2 SEGMENT
AWORDDWO
DATA2 ENDS
ASSUME DS:DATAGRP
: ASM 286
DATA1 SEGMENT RW PUBLIC
ABYTE DBO
DATA1 ENDS
DATA1 SEGMENT RW PUBLIC
AWORDDWO
DATA1 ENDS
ASSUME DS:DATA1

In one module

In another module

Segment Directive
The fields of the SEGMENT directive are also different. ASM 286 does not use anything but para-aligned and
access-type.
Example: ASM 86
NAME SEGMENT [ALIGN-TYPE] [COMBINE-TYPE]
WHERE [ALIGN-TYPE] = PARA, BYTE, WORD, PAGE, INPAGE,
OR NONE
ASM 286
NAME SEGMENT [ACCESS-TYPE] [COMBINE-TYPE]
WHERE SEGMENT IS ALWAYS PARA-ALIGNED AND
[ACCESS-TYPE] = READ-ONLY (RO),
EXECUTE-ONLY (EO),
EXECUTE-READ (ER), or
READ-WRITE (RW) .

Class name is also not present in ASM 286

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Stack Segment
In ASM 286, stack segments are defined using the STACKSEG directive.
Example: ASM 286
PROG_STACK STACKSEG 10;

/' MEANS 10 BYTES ON STACK '/

The operator STACKSTART is used to define a label at the beginning of the stack to initialize the Stack Pointer (SP).
Example: ASM 286
MOV Sp, STACKSTART PROG_STACK

Selector Access
In ASM 286 the selectors used for the DS, SS, and ES in the ASSUME directive must have certain access types.
Example: ASM 286
ASSUME DS:EDATA
EDATA SEGMENT RW PUBLIC
WHEREDBO
EDATAENDS

Further, the ASSUME directive will not accept an assume for the code segment. The current code segment being assembled is automatically assumed into the CS. For more information regarding other changes in ASM 286 consult: ASM 286
Reference Manual (Appendix G), order #122671

LANGUAGES: PL/M 286
Users migrating their code to PLiM 286 should be aware of the following:

Pointer and Selector Variables·
Pointer and selector variables cannot be assigned absolute values. All values must be assigned by reference to another
variable or through based-variables.
Example: PLIM 86
Declare
A$POINTER

POINTER;

Start: DO;
A$POINTER = 0;
Example: PLIM 286
Declare
A$POINTER

POINTER;

Start: DO;
A$POINTER = NIL;

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Similarly selectors can be assigned values as follows:
Example: PLIM 86
Declare token literally 'WORD',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN = 0;
Example: PLIM 286
Declare token literally 'SELECTOR',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN

= SELECTOR$OF(NIL);

The only relational operations allowed in PUM 286 for pointers and selectors are "equals" and "not equals".

Models of Compilation
In PUM 86 the default is SMALL
In PUM 286 the default is LARGE

Interrupt Vectors
In PUM 286 all interrupt numbers on all interrupt procedures must be deleted. The required interrupt vectors will be
assigned by the 80286 system builder if not already defined by the iRMX 286 operating system call RQ$SET$
INTERRUPT.
Consequently the PUM 86 built-ins SET$INTERRUPT and INTERRUPT$PTR are unavailable in PUM 286 and should
be removed. Also, all calls to interrupt procedures are not allowed. As the conversion process takes shape, all of these
changes tum out better than initially expected as the following example shows.
Example: PLIM 86
1. DECLARE
2.

ZERO
LITERALLY
'00001000b',
INTERRUPT_HANDLER POINTER;
· TYPICAL PLIM 86 STATEMENTS

6. INTERRUPT_HANDLER: PROCEDURE INTERRUPT 56 PUBLIC REENTRANT;
· TYPICAL PLIM 86 STATEMENTS

10.
CALL RQ$SIGNAL$INTERRUPT (ZERO, @STATUS);
11. END INTERRUPT_HANDLER;
12. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
· TYPICAL PLIM 86 STATEMENTS

16.
17.

INTERRUPT_HANDLER = INTERRUPT$PTR (INTERRUPT_HANDLER);
CALL RQ$SET$INTERRUPT (ZERO, 1, INTERRUPT_HANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
TYPICAL PLIM 86 STATEMENTS

21.
22.

CALL RQ$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

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Comments
Line
Number
2.
6.
16.
17.

Description
INTERRUPT_HANDLER was defined as a pointer
Interrupt entry 56 was "hard-coded"
INTERRUPT_HANDLER was assigned the location (address) of the first instruction of the
handler via the PUM 86 built-in "INTERRUPT$PTR"
This call could have looked like: RQ$SET$INTERRUPT (ZERO, 1, INTERRUPT_PTR(INTERRUPT_HANDLER), etc eliminating lines 2 and 16.

Example: PUM 286
1. DECLARE

ZERO

LITERALLY

'00001000b';

· TYPICAL PUM 286 STATEMENTS
5. INTERRUPT_HANDLER

: PROCEDURE INTERRUPT PUBLIC REENTRANT;
· TYPICAL PUM 286 STATEMENTS

10.

CALL RQ$SIGNAL$INTERRUPT (ZERO, @STATUS);
END INTERRUPTHANDLER;

11. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
· TYPICAL PLIM 286 STATEMENTS

15.

CALL RQ$SET$INTERRUPT (ZERO, 1, @INTERRUPT_HANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
· TYPICAL PUM 286 STATEMENTS

19.
20.

CALL RQ$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

Comments
Line
Number
5.
15.

Description
Notice PUM 286 does not need to identify the interrupt in this statement
The third parameter becomes simply a pointer'to the first instruction of the handler.

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DEVELOPMENT TOOLS -

BND 286

All iRMX 86 programs linked using LINK 86 will instead have to be bound using BND 286. BND 286 is used to create all
single-task application programs that will be dynamically loaded. (See Figure 5.) The following are tasks of the binder.
1.

Creates a linkable or loadable module by combining input modules with other bindable modules.

Checks the type of variables and procedures.

Selects modules from libraries to resolve all symbolic references.

Combines logical segments by name, attribute, and privilege levels into physical segments that the processor can
manipulate efficiently.

Can create a module the application loader can load.

Linkable Modules
In a process called incremental linking, BND 286 combines linkable object modules, including library modules, output by
translators. The result is a file containing a linkable module.

Loadable Modules
A dynamically loadable module created by BND 286 is an executable module created by the combination of one or more
linkable modules. Loadable modules can be of two types:

Single-task loadable (STL)

Variable-task loadable (VTL)

r-------,
,
I
I

SOURCE
FILES

r--:

r--

TRANSLATOR

I
L
______ JI

r-------,
OBJECT
(".OBJ")

I
I

r-------~

WITH LOAD

t:~===~~l-~.-I

BND286

L________ ..! WITHNOLOAD

LOADABLE
(EXECUTABLE)
OBJECT
MODULE

I
~:

OPERATING I
SYSTEM :
LOADER
I

i
L______ J

,-----_ ... ,
I

-:
-j

SIM286

:L ________ !
~

LINKED
OBJECT
MODULE
"LINK"

LIBRARY
FILE

r--J---,

LEGEND:
-INPUT AND OUTPUT OF
SOFTWARE PRODUCTS

L---i
I

LIB286

: ...._ _ _-J
I

PRINTED
MAPS

, ______ ........I
L..

----- SOFTWARE PRODUCTS

m·OB04

Figure 5. BND 286 Application Program Development
2-73

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STLModules
These mOdules are functionally similar to tTL-format records in the 8086 OMP. STL modules ·are designed to optimize
loader execution time because each contains only one executable task. iRMX 286 and XENIX 286 operating systems .will
execute only files containing STL modules .. BND 286 outputs STL modules when the FASTLOAD, RCONFIGURE, and
XCONFIGURE controls are specified. In iRMX 286 only, the RCONFIGURE control is used.

VTLModules
VTL modules are designed, when provided by. BND 286, to also contain a single executable task, but in a format
structured for multiple tasks. BND 286 outputs VTL modules when the LOAD control is specified.

iRMX. 286 USAGE

r-_~_AS""-T'--·'

l:r-'
r-----L-j

CONSOLE
MESSAGES

.2-74

m·0805

280608-001

AP-405

BND 286 TO LINK 86 COMPARISON

LINK 86 CONTROLS

BND 286 CONTROLS
CONTROLFILE (path name)

DEBUG/NODEBUG

SYMBOLS/NOSYMBOLS

ERRORPRINT (pathname)1
NOERRORPRINT

FASTLOAD/NOFASTLOAD

"LDTSIZE ([ + l number)

LOAD/NOLOAD

NAME (modulename)·

NAME (modulename)

.OBJECT (pathname)1
NOOBJECT

PACKINOPACK

PRINT (pathname)1
NOPRINT

PRINT (pathname)1
·NOPRINT

PUBLICS/NOPUBLICS

PUBLICS/NOPUBLICS/PUBLICSONLY

RCONFIGU.RE (dm,m)

BIND and MEMPOOL

RENAMESEG (old to new)
RESERVE (number)

SEGSIZE (name(size»

"TASKPRIVILEGE ( )

TYPE/NOTYPE

"XCONFIGURE

"Not used in iRMX 286

2-75

280608-001

AP-40S

The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) used on
an iRMX 286 Release 1.0 system.
BND286

iRMX 286 Libraries-

E~AMPLE.OBJ,

EXAMPLE.LlB,

IRMX286/L1B/UPIFC.LlB,

IRMX286/L1B/UDI.GAT,

IRMX286/L1 B/HPIFC. LI B,

IRMX286/L1 B/H LGAT,

IRMX286/L1 B/LPI FC.LlB,

IRMX286/L1B/LOA.GAT,

IRMX286/L1B/EPI FC. LIB,

IRMX286/L1 B/EIO.GAT,

IRMX286/L1BIIPIFC. LI B,

IRMX286/L1 BIIOS.GAT,

IRMX286/L1B/NUCIFC.LlB,

IRMX286/L1B/NUC.GAT

iRMX 286 Library Privilege
Gates

RCONFIGURE (DM(10000H, 10000H))
(Analogous to BIND&MEMPOOL)
SEGSIZE (STACK(1024))
(Analogous to segsize)
OBJECT (EXAMPLE)
(A new control)
The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) on an
iRMX 286 Release 2.0 system. Notice all of the .GAT files and many of the.LIB files are gone. All of these "missing"
files are now contained in the files RMXIFC.LIB and UDIIFC.LIB for convenience.
BND286

EXAMPLE.OBJ;

EXAMPLE. LIB,

IRMX286/L1B/UDIIFC.LlB,

IRMX286/L1B/RMXIFC.LlB,

RCONFIGURE (DM(10000H,10000H))
(Analogous to BIND & MEMPOOL)
SEGSIZE (STACK(1 024))
(Analogous to SEGSIZE)
OBJECT (EXAMPLE)
(A new control)

2-76

280608-001

AP-405

iRMX(R) XXX.BLD File
system_bid;
segment
nucdat.code(dpl = 0),
nucdat.data(dpl = 0),
memory
(reserve = (0 .. 0001 FFFH,
003AOOOH .. OFFFFFFh));

gate
Gate_CreateJob (entry =
RqCreateJob, dpl = 0, wc = 0),

table
Idt1 (limit = 00600h,dpl = 0,
reserve = (2 .. 2, 4 . .4AH,
4CH ..4EH,51H .. 59h,
122H .. 005FFh),
entry = ( O:nucdat.escape_ss,
3:nucdat.stack,
75:nucdat.jobdat,
79:nucdat.escape_ss,
80:nucdat.entry_code) );
task
rmxtask (dpl =O,object = nucdat,
Idt = Idt1, no ie);
table
gdt (limit = 00600H, dpl = 0,
reserve = (3 .. 3BH, 3DH ..4EH,
51H .. 53H, 55H .. 59H, OC1H .. OC7H,
OE3H .. OE5H,OEAH .. OEFH,
101H .. 103H,00137h .. 00140h),
entry = (60:nucdat.data,
79:rmxtask,
80:nucdat.code,
84:ldt1,
90:Gate_AcceptControl,
91 :Gate_AlterComposite,

308:sdbcnf.code,
309:sdbcnf.data,
310:sdbcnf.newstack,
291 :bios_code,
292:bios_data,

table
idt(limit =00080h, dpl =0);
end

2-77

280608·001

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AP-405

DEVELOPMENT TOOLS - BLD 286
BLD 286 exceeds LOC 86 in capability and versatility. In many cases the use of BLD ,286 is transparent to iRMX 286
users, due to the ICU 286 automatically generating the BUILD file. All iRMX 286 users, however, should possess an
understanding of the following key 'functions:
A. Assigns physical addresses to entities, sets segment limits and access rights. (See XXX.BLD file)
B. Allows memory ranges to be reserved or allocated for specific entities. (See XXX.BLD file)
C. Creates one Global Descriptor Thble (GDT), one Interrupt Descriptor Thble (lOT), and one Local Descriptor
Thble (LDT). (See XXX.BLD file)
D. Creates gates. (See XXX.BLD file)
E. Creates task state segrtlents and (task gates). (See 'XXX.BLD file)
F.

Creates a bootloadable module. (See XXX.BLD file)

G. Creates object files containing exported system entries. (See XXX.BLD file)
H. Selects required modules from specified libraries automatically, as needed to resolve symbolic references.
I.

Performs reference-resolution and typechecking.

J.' Detects and reports errors and warnings found during processing (in the XXX.MP2 file)
See FigUre 6 for an example of BLD 286 program development.

Usage
BLD 286 is primarily used for building an application program that deals extensively with system interfaces'to a hardware
environment. This could include configuring gates and/or segments that provide this interface, then place these interfaces
in a separate file for later exportation.
The types of executable output produced by BLD 286 are bootioadable, loadable, or incremental-built. Bootioadable
modules are absolutely-located object modules that are booted via a simple loader. Loadable modules consist of single- or
multiple-task modules used for dynamic loading. Incrementally-built modules are non-executable modules used interac~
tively to build large systems.
Many users will only use BLD 286 when they produce a new configuration using the ICU. ICU 286 generates a file called
ICUBLD.CSD which invokes the builder using the file XXX.BLD as the builder definition file.
The following is a typical example of the contents of ICUBLD.CSD:
BLD286,

NUCLUS.LNK,'

SDB.LNK,

IOS.LNK,

EIOS.LNK,

,& '

LOADER.LNK,

HI.LNK,

UDI.LNK

OBJECT (/BOOT/~ * * .286)

& ( Where to put the
bootloadable file)

NODEBUG NOTYPE

(Produced by BND 286)-1

BUILDFILE (* **~BLD)

( Where to obtain the
build infOrm,ation)
2-78

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Ap·405

LIBRARIES

r---------.

TRANSLATED
I
I
I
80286
I
OBJECT
: TRANSLATORS;- MODULE(S)

t--

'---------.1
BINDER
LINKABLE
MODULE(S)

BUILD
FILE

BUILDER
EXPORT
MODULE(S)

L....-..

J r-=:

80286
SYSTEM
BUILDER

INCREMENTALLY
BUILD
SYSTEM
IMAGE

BOOTLOADABLE
MODULE

LOADABLE
MODULE

t-'NOT USED BY iRMX® 286
m-0801

Figure 6. BLD 286 Application Program Development
The build fIle contains a specific language used by BLD 286 to produce the system or system program_ BLD 286 takes all
linked input modules and assigns all of the access and protection attributes for each subsystem_ A build fIle is created to
specify the characteristics of the relationships among the subsystems: Segment attributes, gates, descriptor tables, aliases,
and memory allocation are also described in the build file and read by BLD 286_

2·79

280608-001

inter

AP-405

0--'-----1 ------lWITHNOBOOTLOAD

r--r--

r---

OBJECT
MODULE

I WITH

--_ •• 1""

LOADABLE

• (EXECUTABLE) 1-_ _ _ _---,

I
BLD286 I

Lf: -------,

BOOTLOAD

80286
EXAMPLE ;
I
LOADER ;..1-+-----<~\.-..
'- ______ .1

.
r----L-....

------'"•

r------'10-+-:-+""---'
!18OOTLOADER;

---;..I
I

~- ••

•
•

OBJECT
TRANSLATOR..- MODULE
(".OBJ")
------,. '-T""T'""

D---~
~1

L---i........

LOAOABLE

BND286

tl=W::IT::HLOA::=D:::;-+'I (EX~~~~~LE)
f_
MODULE

~·-r~·..1

r------"\
, OPERATING:
SYSTEM •
LOADER

rl,

....

1-*----'

r-------~

t..l
~ri

SIM286

LINKED
OBJECT
MODULE
"LINK"

. . _J:.._"\

i
1

I,. •••

_._J

r-------'"
LJ, MAP286 I1

'---_ __+;'

L·~T-J

:
L---il-+-~' LlB286 l I
•
.........
LEGEND:
-INPUT AND OUTPUT OF SOFTWARE PRODUCTS
--_··SOFTWARE PRODUCTS

PRINTED
MAPS

m·0806

Figure 7.

2-80

2808011-001

AP-405
MAP 286
.The 80286 mapper is a noninteractive utility that generates object module information that BND 286 and BLD 286 do not
produce. The utility is offered separately instead of having the builder and tinder performing identical functions. The user
should note that if debug information is contained in the invocation file, all of the maps will be produced.
MAP 286 will accept the following input:
A. Executable files containing a single executable module, and only one per invocation of MAP 286.
B.

Executable files containing a single bootloadable module.

C. One or more linkable or library files.
MAP 286 produces the following output maps:
For executable input files:
A. An output object file with or without debug information.
B. Table MAP, segment MAP, gate MAP, public MAP, symbol MAP, task MAP, and crossreference MAP.
For linkable input files:
A. Only a cross reference map including a module list.
In iRMX 286 the following is a typical invocation of the mapper on an executable file called
MAP

286

MYPROG

If debug information is in "MYPROG" all of the maps will be produced.

iRMX® 86 OPERATING SYSTEM PROGRAM MIGRATION
Compiling in PL/M 286
The following is an example of converting an iRMX 86 Commonly Used System Program (CUSP) called NaTE. To assist
readers, all of the conversion steps will be described.

Source Program
The program NaTE is written in PUM 86 for use on iRMX 86 operating system. When invoked, the utility will echo a
line of keyboard input to the console.
The source code file name for NaTE is NaTE.P86. To adhere to PUM 286 and iRMX 286 operating system file naming
conventions, the file should be renamed to NaTE.P28. Next, the file has to be changed to reflect changes in PUM 286
and iRMX 286 library files. Finally the file is compiled and bound with BND 286. See the following examples for further
explanation.
STEP I
Copy NaTE.P86 to NaTE.P28
STEP 2
The NaTE.P28 file has to be edited to change
A. All '0' pointers to 'NIL'
B. All '0' selectors to 'SELECIDRS$OF(NIL),

Also notice all of the include files assume an iRMX 86 operating system and have to be changed to iRMX 286 libraries.
STEP 3
The new NaTE.P28 program is compiled and any errors are corrected.

2·81

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AP-405

Stitle('iRMX 86 HI NOTE command')
$subtitle('module header')

/***********************************************************************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.

***********************************************************************/
hnote: DO;
$include(:sd:inc/hstand.lit)
$include(:sd:rmx86/inc/hgtchr.ext)
$include(:sd:rmx86/inc/hsneor.ext)
$include(:sd:inc/hutil.ext)
DECLARE
version(*) BYTE DATA ( 'program_version_number=F001',
'program_name=Note' ,0);
1
2
3
4
5

main: DO;
/* local variables */
DECLARE
excep
WORD,
BYTE, .
char
count
WORD,

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

msg

STRUCTURE (
length
BYTE,
char (STRING$MAX) BYTE) ;

count = 0;
char = rq$C$get$char( @excep);
DO WHILE( (char := rq$C$get$char( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
msg.char(count) = char;
count = count + 1;
END;
END;
msg.char(count) = cr;
count = count + 1;
THIS POINTER
msg. char ( count) = If;
NEEDS CHANGING.
count = count + 1;
msg.length = count;
CALL rq$C$send$EO$response( 0, 0, @msg, @excep);

/* exit from command */
24
25

CALL cusp$error( excep, @(O), @(O), ABORT);
END main;

END hnote;

PLM 86 Example

2-82

280608·001

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AP-405

$title('iRMX 286 HI NOTE command')
$aubtitle('module header')

/***********************************************************************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.

2
3
4

6
7
8
.9

10
11

12
13
14
15
16
17
18
19
20
21
22
23

main: DO;
/* local variables */
DECLARE
excep
WORD,
BYTE,
char
WORD,
count
mag

STRUCTURE (
length
BYTE,
char(STRING$MAX) BYTE);

count = 0;
char = rq$C$get$char( @excep);
DO. WHILE ( (char : = rq$C$get$char ( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
msg.char(count) = char;
count = count + 1;
END;
END;
msg.char(count) - cr;
THIS IS
count = count + 1;
msg.char(count) = If;
OK NOW.
count = count + 1;
msg.length = count;
CALL rq$C$send$EO$response( NIL, 0, @msg, @excep);

/* exit from command */
24
25

CALL cusp$error( excep, @(O), @(O), ABORT);
END main;

END hnote;

PLM 286 Version Example

2-83

280608-001

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AP-405

Binding an iRMX® 286 Application
STEP 1

If a program was previously linked in iRMX 86, we then examine the original
LINK file used and notice the following:
PLM86 %O.P86 COMPACT ROM OPTIMIZE(3) NOTYPE PW(132)

,
LINK86
%O.obj,
/rmx86/hi/hutil.lib,
&
/lib/plm86/plm86.1ib,
&
/rmx86/1ib/hpifc.lib,
&
/rmx86/1ib/epifc.lib, &
/rmx86/1ib/ipifc.lib, &
/rmx86/1ib/rpifc.lib &
to %.86
'
bind mempool(lOOOO,OBOOOOH)
nosb noty

1.
2.
3.

The library names will change
The pathnames to access.the libraries will change
BIND and MEMPOOL will change

STEP 2

The following is the iRMX 286 Release 1.0 version of the file in Step 4.
Remember the libraries have changed names between iRMX 286 Release 1.0 and 2.0.
PLM286 %O.p28 COMPACT ROM OPTIMIZE(3) NOTYPE PW( 132)

.bnd286

%O.obj,
&
/rmx286/1ib/hutil.lib,
&
/rmx286/1ib/plm286.1ib,
&
/rmx286/1ib/hpifc.lib, /rmx286/1ib/hi.gat,
&
/rmx286/1ib/epifc.lib, /rmx286/1ib/eio.gat, &
/rmx286/1ib/ipifc.lib, /rmx286/1ib/ios.gat,
&
/rmx286/1ib/nucifc.lib, /rmx286/1ib/nuc.gat &
renameseg(hi_code to code, hi_data to data) segsize (stack(lOOOH»
object(%O) rc(dm(12000,1000000»
node bug noty

STEP 3

This is an example of the Step 4 file modified to run on iRMX 286 Release
2.0. Notice the reduction of 1ibrary statements.
PLM286 %O.p28 COMPACT ROM OPTIMIZE(3) NOTYPE PW( 132)

bnd286

%O.obj,
/RMX286/hi/hutil.lib,
/RMX286/1ib/plm286/plm286.1ib,
/I~X286/1ib/rmxifc.lib

&
&

renameseg(hi_code to code, hi_data to data) segsize (stack(1000H»
object(%O) rc(dm(12000,lOOOOOO»
nodebug noty

Though these few migration examples reflect trivial modifications, larger
and more complex applications might require a little more attention.

2-84

280608·001

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AP-405

SUMMARY
The purpose of this application note is to provide insight and direction to those individuals contemplating using the iRMX
286 operating system. For those already familiar with the iRMX 86 operating system, this paper's focus is to provide the
pathway to a superior product.
The iRMX 286 operating system is a vast improvement over its previous counterpart. Some notable changes are round
robin scheduling, hardware-enforced protection, hardware-assisted debugging, and access to the 80386 processor. With
this operating system the capabilities of the 80286 processor can be fully utilized for multiple environments.
Since the iRMX product line was introduced, many applications, programs, and lines of code have been written to support
a tangible demand for real-time processing; in manufacturing, in medicine, and in finance, to name a few. As a result
more time is being spent on designing, writing, and testing software than ever before. The iRMX 286 operating system is
the preferred product for generating error-free programs while utilizing the highest CPU technology available in the OEM
modules market.

2-85

280608·001

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I

Single Board Computers

inter

iSBC@ 80/10B
SINGLE BOARD COMPUTER
Programmable Synchronous/
• Asynchronous
Communications

•
•
•1
•
•

8080A CPU Used as Central Processing
Unit

Interface with Selectable RS232C or
Teletypewriter Compatiblity

One iSBXTM Bus Connector for iSBXTM
MULTIMODULETM Board Expansion

•
•
•
•

K Byte of Read/Write Memory with
Sockets for Expansion up to 4K Bytes

Sockets for up to 16K Bytes of Read
Only Memory

48 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers and Terminators

Single Level Interrupt with 11 Interrupt
Sources
Auxiliary Power Bus and Power-Fail
Interrupt Control Logic for RAM
Battery Backup
1.04 Millisecond Interval Timer
Limited Master MULTIBUS® Interface

The Intel iSBC 80/10B board is a member of Intel's complete line of OEM microcomputer systems which take
full advantage of Intel's LSI technology to provide economical, self-contained computer-based solutions for
OEM applications. The iSBC 80/10B board is a complete computer system on a single 6.75 x 12.00-inch
printed circuit card. The CPU, system clock, iSBX bus interface, read/write memory, read only memory sockets, 110 ports and drivers, serial communications interface, bus control logic, and drivers all reside on the
board.

280217-1

3-1

September 1987
Order Number. 280217-002

inter

iSBC® 80/10B COMPUTER

ULE board. iSBX boards are available to provide expansion equivalent to the 1/0 available on the iSBC
.80/10B board or the user may configure entirely
new functionality such as math directly on-board.
The iSBX 350 programmable 1/0 MULTIMODULE
board provides 24 1/0 lines using an 8255A programmable peripheral interface; Therefore, the iSBX
350 module together with the iSBC 80/10B board
may offer 72 lines of programmable 110. Alternately,
a serial port may be added using the iSBX 351 serial
1/0 multimodule board or math may be configured
on-board with the iSBX 332 floating point math MULTIMODULE board.

FUNCTIONAL DESCRIPTION·
Intel's powerful 8-bit n-channel MOS 8080A CPU,
fabricated on a single LSI chip, is the central processor for the iSBC 80/1 OB board. The 8080A contains
six 8-bit general purpose registers and an accumulator. The six general purpose registers may be addressed individually or in pairs, providing both single
and double precision operators. A block diagram of
iSBC 80/10B board functional components is shown
in Figure 1.

iSBXTM Bus MULTIMODULETM Board
Expansion

The iSBX board is a logical extension of the onboard programmable 1/0 and is accessed by the
iSBC 80/1 OB single board computer as common 110
port locations. The iSBX board is coupled directly to
the 8080A CPU and therefore becomes an integral
element of the iSBC 80/108 single board computer
providing optimum performance.

The new iSBX bus interface brings an entirely new
dimension to system design offering incremental onboard expansion with small iSBX boards. One iSBX
bus connector interface is provided to accomplish
plug-in expansion with any iSBX MULTIMOD-

RS232C
COMPATIBLE
DEVICE

'RIA~O

.. PROGRAMMABL~

OS'RIAL

S
DATAICON TAOl
INTEA FACE

USER DESIGNATED
Isax MUlTIMODUlE
BOARD

USER
DESIGNATED
PERIPHERALS

TTY

DATA/CONTROL
INTERFACE

PARALLEL 110 LINES

ISBXBUs_0
- ~--

'T~~A~'I
I

BAUD RATE

TTY

R5232C
INTERFACE

INTERFACE

mr:
I

\/
ROM/EPROM

(SOCKETS)

4K • II

}

Isax BUS
MUlTIMODUlE

CONNECTOR

l---l~-~;\ -

FAIL

SELECTED

lk • 8 RAM
(SOCKETS TO

III
II

POWER

'Yi~'"

16K. 8

TERMINATOR
INTERFACE

TIMER

1 f
."

DRIYERI

1.04 MSEe
INTERVAL

SELECTOR
IJUMPER5)

,----

7,[

INTERRUPT SELECTOR
(JUMPERS)

PROGRAMMABLE
COMMUNICATIONS
INTERFACE (USART)

-0

8080A

CPU

PROGRAMMABLE
PERIPHERAL
INTERFACES

ON·BOARD SYSTEM BUS

l
MUlTIBUS
INTERFACE

...
,

MUL TIBUS~ SYSTEM BUS

...

280217-2

Figure 1. iSBC® 80/10B Single Board Computer Block Diagram
3-2

inter

ISBC® 80/10B COMPUTER

Memory Addressing

Parallel I/O Interface

The 8080A has a 16-bit program counter which allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.

The iSBC 80/10B board contains 48 programmable
parallel I/O lines implemented using two Intel 8255A
programmable peripheral interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input/output, and bidirectional ports indicated in Table 1. Therefore, the
1/0 interface may be customized to meet specific
peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable 110
line drivers and terminators. Hence, the flexibility of
the I/O interface is further enhanced by the capability of selecting the appropriate combination ofoptional line drivers and terminators to provide the required sink current, polarity, and drive/termination
characteristics for each application. The 48 programmable I/O lines and signal ground lines are
brought out to two 50-pin edge connectors that mate
with flat cable or round cable.

Memory Capacity
The iSBC 80/1 OB board contains 1K bytes of read/
write static memory. In addition,sockets for up to 4K
bytes of RAM memory are provided on board. Read/
write memory may be added in 1K byte increments
using two 1K x4 Intel 2114A-5 static RAMs. All onboard RAM read and write operations are performed
at maximum processor speed. Sockets for up to 16K
bytes of nonvolatile read-only-memory are provided
on the board. Read-only-memory may be added in
1K byte increments up to 4K bytes (using Intel 2708
or 2758); in 2K byte increments up to 8K bytes (using Intel 2716); or in 4K byte increments up to 16K
bytes (using Intel 2732). All on-board ROM or
EPROM read operations are performed at maximum
processor speed.

Serial I/O Interface
A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the board. A jumper selectable baud rate generator
provides the USART with all common communications frequencies. The USART can be programmed

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional

Lines
Port

Input

(Qty)

Output

Bidirectional

Unlatched

Latched &
Strobed

Latched

Latched &
Strobed

Control

X
X(1)

NOTE:

1. Port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched
and strobed output port or port 1 is used as a bidirectional port.

3-3

inter

ISBC® 80/10B COMPUTER

by the system software to select the 'desired synchronous or asynchronou.s serial data transmission
technique (including IBM Bi-Sync). The modeofoperation, (Le., synchronous or asynchronous), data
format, control character format and parity are all
under program control. The 8251A provides full duplex,' double-buffered transmit and receive capability. Parity, overrUl1, and framing error detection are all
incorporated inthe U~ART. The inclusion of jUfllper
selectable TIY or RS232C compatible interfaces on
the board,.in conjunction with the USART, provides
a direct interface to teletypes, CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems. The RS232C or TIY command lines,
serial data lines, .and signal ground line.s .are brought
out to a 26"pin edge connector that mates with
. RS232C compatible flat or round cable.

Power-Fail Control
A power-fail interrupt may be detected through the
AC-Iow signal generated by the power .supply. This
signal may be configured to interrupt the 8080A CPU
to initiate' an orderly power. down instruction sequence.

Interval Timer
A 1.04 millisecond timer is available for interval i~ter
rupts or as a clock output to the parallel 110 connector. The timer output is jumper selectable to the programmable parallel interface, the parallel I/O connector (J1), or directly to the 8080A CPU.

MULTIBUS® System
Expansion Capabilities
,.

Interrupt Capability
Interrupt requests may originate from 11 sources.
Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to
be transferred to the CPU (Le., input buffer is full) or
a byte. of information has been transferred to a peripheral device (Le" output buffer is empty). Three .
jumper. selectable interrupt requests can be automatically generated by the USART when a character
is ready to be transferred to the CPU (i.e., receive
channel buffer is full), a character is ready to be
transmitted (Le., the USART. is ready to. accept a
character from the CPU), or when the transmitter is
empty (i.e., the USART has no character to trimsmit). These five interrupt request lines are all maskable under program control. Two interrupt request
lines may be interfaced directly to user designated
peripheral devices; one via the MULTIBUS system
. bus and the other via the 110 edge connector. One
jumper selectable interrupt request may be interfaced to the power-fail interrupt control logic. One
jumper selectaQle interrupt request may originate
·from the interval timer. .Two general purpose interrupt requests are jumper selectable from the iSBX
interface. These two signals permit a' user installed
MULTIMODULE board to interrupt to 8080A CPU.
The eleven interrupt request lines share a single
CPU interrupt level. When an interrupt request is
recognized, a restart instruction (RESTART 7) . is
generated. The proCessor responds by suspending
program execution and executing a user defined interrupt service routine originating at location 3816.

Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUSTM
system compatible expansion boards. Memory may
be.expanded to 65,536.bytes by adding user specified combinations of RAM boards, EPROM boards,
or combination boards. Input/output capacity may
be increased by adding digital I/O and analog I/O
expansion boards. In addition, the iSBC 80/10B
board performs as a .limited bus master in that it
. must occupy the lowest priority when used with other MULTIBUS masters. The bus master may take
control of the MULTIBUS system bus by halting the
iSBC 80/10B board program execution. Mass storage capability may be. achieved by adding single
. density diskette, double density diskette,' or hard
disk controllers. Modular expandable backplanes
and cardcages are available to support multi board
systems.

SPECIFICATIONS
...
.

Word Size
Instruction: 8, 16, or 24 bits
Data: 8 bits"
.
..

Cycle Time
Basic Instruction Cycle: 1.95 p.s

NOTE:

Basic instruction cycle is defined as the· fastest instruction (Le., four clock cycles).

3-4

intJ

iSBC® 80/10B COMPUTER

Memory Addressing

I/O Addressing

On-Board ROM/EPROM
O-OFFF using 2708, 2758
0-1 FFF using 2716
0-3FFF using 2?32

On-Board Programmable I/O
I/O
Address

Device

On-Board RAM
3COO-3FFF with no RAM expansion
3000-3FFF with 2114A-5 expansion
NOTE:
All RAM configurations are automatically moved up
to a base address of 4XXX when configuring
EPROM for 2732.

Memory Capacity
On-Board ROM/EPROM
16K bytes (sockets only)
On-Board RAM
1K byte with user expansion in 1K increments to
4K byte using Intel 2114A-5 RAMs.

8255 No.1
PortA
Port B
PortC
Control

E4
E5
E6
E7

8255 No.2
PortA
PortB
PortC
Control

E8
E9
EA
EB

8251A
Data
Control

EC
ED

iSBX Multimodule
MCSO
MCS1

FO-F7
F8-FF

Off-Board Expansion
Up to 64K bytes using user specified combinations of RAM, ROM, and EPROM.

Serial Baud Rates
Frequency (kHz)
(Jumper Selectable)

307.2
153.6
76.8
38.4
19.2
9.6
6.98
4.8

Baud Rate (Hz)
Synchronous

38400
19200
9600
6980
4800

3-5

Asynchronous
(Program Selectable)

+16
19200
9600
4800
2400
1200
600

300

+64
4800
2400
1200
600
300
150
110
75

ISBC® 80/10B COMPUTER

Connectors
Double-Sided Centers
(In.)
Pins (Qty)

Interf~ce

Mating Connectors
Viking 2KH43/9AMK12 Wire':wrap

MULTIBUS System

0.156

iSBX Bus

0.1

iSBX 960·5

Parallel 1/0 (2)

0.1

3M 3415-000

Flat

Serial 1/0

0.1

AMP 87194-6

Flat

110 Capacity
Parallel:
Serial:
MULTIMODULE:

Interfaces
48 programmable lines
1 transmit, 1 receive
1 iSBX Bus MULTIMODULE
Board

Serial Communications Characteristics

MULTIBUS:
iSBX Bus:
Parallel 1/0:
Serial 1/0:

All signals TTL compatible
All signals TTL compatible
All signals TTL compatible
RS232C or a 20 mil current
loop TTY interface Gumper selectable)
.

Interrupt Requests:

All TTL compatible (active-low)

Synchronous:

5-8 bit characters; internal or external character synchronization;
automatic sync insertion
Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits;
false start bit detectors

System Clock: 2.048 MHz ± 0.1 %
Interval Timer: 1.042 ms ± 0.1 % (959.5 Hz)

Interrupts

Physical Characteristics

Single-level with on-board logic that automatically
vectors the processor to location 38H using a restart
instruction (RESTART 7). Interrupt requests may
originate from user specified 1/0 (2); the programmable peripheral interface (2); the iSBX MULTIMODULE board (2); the programmable communications
interface (3); the power fail interrupt (1); or the interval timer (1).

Width:
Height:
Depth:
Weight:

Clocks

12.00 in (30.48 cm)
6.75 in. (17.15 cm)
0.05 in. (1.27 cm)
14 oz. (397.3 gm)

Electrical Characteristics
DC Power Requirements
Voltage
Vee
VDD
Vss
VAA

=
=
=
=

+5V ±5%
+ 12V ±5%
-5V ±5%
-12V ±5%

Without
EPROM(1)
lee
IDD
Iss
IAA

=
=
=
=

2.0A(4)
150 rnA
2mA
175 rnA

With 2708
EPROM(2)

With 2758, 2716,
or 2732 EPROM(3)

Power Down Requirements
(RAM and Support Circuit)

3.1A
400 rnA
200 rnA
175 rnA

3.46A
150mA
2mA
175mA

84 rnA + 140 mAiK (2114A-5)
Not Required
Not Required
Not Required

NOTES:
1. Does not include power required for optional ROMIEPROM, 110 drivers, or 1/0 terminators.
2. With four Intel 2708 EPROMS and 2200/3300 for terminators, installed for 48 input lines. All terminator inputs low.
3. Same as #2 except with four 27585, 27165, or 27325 installed.
4. Icc shown without RAM supply current. For 2114-5 add 140.mA per K byte to a maximum of 560 mA.

3"6

inter

iSBC® 80/10B COMPUTER

Line Drivers and Terminators

MULTIBUS® Drivers

110 Drivers: The following line drivers and terminators are all compatible with the 110 driver sockets on the iSBC 80/10B Board:
Driver
7438
7437
7432
7426
7409
7408
7403
7400

CharacterIstIc

SInk Current (rnA)

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

FunctIon
Data
Address
Commands

25
25
25

Operating Temperature: O·C to 55·C

Equipment Supplied
iSBC 80/10B Single Board Computer
iSBC 80/10B Schematics

NOTE:

Port 1 has 25 nA totem pole drivers and 1 kfl terminators.
liD Terminators: 220fl/330fl divider or 1 kfl pull
up.

Reference Manual
9803119-01- iSBC 80/10B Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED).
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature '
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

22011
+5~

...----_----Go OPllON 1

33011

1kll
1kll

Tri-State
Tri-State
Tri-State

Environmental Characteristics

I-inverting, NI-non-inverting, OC--open collector.

, 22011133011

CharacteristIc Sink Current (rnA)

ORDERING INFORMATION

+5----'1N\\,-.---------GOOPTION2
280217-3

Part Number Description
iSBC80/10B Single Board Computer

3-7

intJ

iSBC® 80/20-4
SINGLE BOARD COMPUTER

•
•
•
•
•

MULTIBUS@ Control Logic Allowing
• Full
up to 16 Masters to Share System Bus
Programmable 16-blt BCD and
• Two
Binary Timers
Eight-Level Programmable .Interrupt
• Control
with Optional Memory and
• Compatible
I/O Expansion Boards
Auxiliary Power Bus, Memory Protect,
• and
Power-Fail Interrupt Control Logic

8080A CPU Used as Central Processor
4K Bytes of Static Read/Write Memory
Sockets for up to 8K Bytes of Erasable
Reprogrammable or Masked Read Only
Memory
48 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers and Terminators
Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Fully Software
Selectable Baud Rate Generation

Provided for Battery Backup RAM
Requirements

The iSBC 80/20-4 Single Board Computer is a member of Intel's complete line of OEM computer systems
which take full advantage of Intel's LSI technology to provide economical, self-contained computer-based
solutions for OEM applications. Each iSBC 80/20-4 is a complete computer system on a. single 6.75 X 12.00inch printed circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O ports
and drivers, serial communications interface, priority interrupt logiC, two programmable timers, MULTIBUS
control logiC, and bus expansion drivers all reside on each board.

280218-1

3-8

September 1987
Order Number: 280218-002

inter

iSBC® 80/20-4 SINGLE BOARD COMPUTER

vided on the board. Read only memory may be added in 1K byte increments using Intel 2708 erasable
and electrically reprogrammable ROMs (EPROMs),
or read only memory may be added in 2K byte increments using Intel 2716 EPROMs. All on-board ROM
read operations are performed at maximum processor speed.

FUNCTIONAL DESCRIPTION
Intel's powerful 8-bit n-channel MOS 8080A CPU,
fabricated on a single LSI chip, is the central processor for the iSBC 80/20-4. The 8080A contains six 8bit general purpose registers and an accumulator.
The six general purpose registers may be addressed
individually or in pairs, providing both single and double precision operators. Minimum instruction execution time is 1.86 microseconds. A block diagram of
iSBC 80/20-4 functional components is shown in
Figure 1.

Parallel 110 Interface
The iSBC 80/20-4 contains 48 programmable parallel I/O lines implemented using two Intel 8255
programmable peripheral interfaces. The system
software is used to configure the I/O lines in any
combination of the unidirectional input/output, and
bidirectional ports indicated in Table 1. Therefore,
the I/O interface may be customized to meet specified peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable
I/O line drivers and terminators. Hence, the flexibility
of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide therequired sink current, polarity, and drive/termination
characteristics for each application. The 48 programmable I/O lines and signal ground lines are
brought out to two 50-pin edge connectors that mate
with flat, woven, or round cable.

Memory Addressing
The 8080A has a 16-bit program counter which allows direct addressing of up to 65,536 bytes of
memory. An external stack, located within any portion of read/write memory, may be used as a last-in/
first-out storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.

Memory Capacity
The iSBC 80/20-4 contains 4K bytes of static read/
write memory using Intel low power static RAMs. All
on-board RAM read and write operations are
performed at maximum processor speed. Power for
on-board RAM memory is provided on an auxiliary
power bus, and memory protect logic is included for
battery backup RAM requirements. Sockets for up to
8K. bytes of nonvolatile read only memory are pro-

Serial 1/0 Interface
A programmable communications interface using Intel's 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USARD is contained on the
iSBC 80/20-4 board. A software selectable baud

RS232C

COMPATIBLE
DEVICE

a INTERRUPT
ADDRESS BUS REQUEST LINES

L-"':::::::"--Jr :~:~:~:BUS

IL___ SYSTEM DUS
58C80

280218-2

Figure 1. iSBC® 80/20 and iSBC® 80/20-4 Block Diagram Showing Functional Components
3-9

iSBC® 80/20·4 SINGLE BOARD COMPUTER

rate generator provides the USART with all common
communications frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (Le., synchronous or asynchronous), data format, control character parity, and
baud rate are all under program control. The 8251
provides full duplex, double-buffered transmit and
recieve capability. Parity, overrun, and framing error
detection are all incorporated in the USART. The
RS232C compatible interface on each board, in conjunction with the USART,. provides a direct interface
to RS232C compatible terminals, cassettes, and
asynchronous and synchronous modems. The
RS232C command lines, serial data lines, and signal
ground line are brought out to a 26-pin edge connector that mates with RS232C compatible flat or round
cable.
.

addition of an external priority network. Once bus
control is attained, a bus bandwidth .of up to 5M
bytes/sec may be achieved.
The bus controller provides its own clock which is
derived independently from the processor cloc~.
This allows different speed controllers to share resources on the same bus, and transfers via the bus
proceed asynchronously. Thus, transfer speed is dependent on transmitting and receiving devices only.
This design prevents slow master modules from being handicapped in their attempts to gain control of
the bus, but does not restrict the speed at which
faster modules can transfer data via the same bus.
Once a bus request is granted, single or multiple
read/write transfers can proceed at a maximum rate
of 5 million data words per second. The most obvious applications for the master-slave capabilities of
the bus are multiprocessor configurations, high
speed direct-memory-access (DMA) operations and
high speed peripheral control, but are by no means
limited to these three.

Multimaster Capability
The iSBC 80/20-4 is a full computer on a single
board with resources capable of supporting the majority of OEM system requirements. For those applications requiring additional processing capacity and
the benefits of multiprocessing (Le., several CPUs
and/ or controllers logically share system tasks with
communication over the system bus), the iSBC
80/20-4 provides full MULTIBUS arbitration control
logic. This control· logic allows up to three iSBC
80/20-4 or high speed controllers to share the system bus in serial (daisy chain) priority fashion, and
up to 16 masters may share the system bus with the

Programmable Timers
The iSBC 80/20-4 board provides three fully programmable and independent BCD and binary 16-bit
interval timers/event counters utilizing an Intel 8253
Programmable Interval Timer. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing of these counters is jumper selectable. Each may be independently routed to the programmable interrupt controller, the I/O line drivers

Table 1. Input/Output Port Modes of Operation

Port

1
2
3
4
5
6

Lines
(qty)

8
8
4
4
8
8
4
4

Mode of Operation
Unidirectional
Output
Input
Latched &
Latched &
Unlatched
Latched
Strobed
Strobed

X
X
X
X
X
X
X
X

X
X

X
)(

X
X
X
X
X
X
X
X

X
X

Bidirectional

Control

X
X(1)
X(1)

X
X

X
X(2)
X(2)

NOTES:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a' control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port,

3-10

inter

iSBC® 80/20-4 SINGLE BOARD COMPUTER

and terminators, or outputs from the 8255 programmable peripheral interfaces. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSSC 80/20-4 RS232C USART serial port. In utilizing the iSSC 80/20~4, the systems
designer simply configures, via software, each timer
independently to meet system requirements. Whenever a given time delay or count is needed, software
commands to the programmabletfmers/event counters select the desired function. Seven functions are
available, as shown in Table 2. The contents of each
counter may be read at any time during system operation with simple read operations for event counting
applications, and special commands are included so
that the contents of each counter can be used "on
the fly."
Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
terminal count

When terminal count is reached,
an interrupt request is generated.
This function is extremely useful
for generation of real-time clocks.

Interrupt Capability
Operation and' Priority Assignments-An Intel
8259 Programmable Interrupt Controller (PIC) provides vectoring for eight interrupt levels. As shown in
Table 3, a selection of four priority processing
modes is available to the systems designer so that
the manner in which requests are processed may be
configured to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PIC accepts interrupt requests from
the programmable parallel and serial 110 interfaces,
the programmable timers, the system bus, or directly
from peripheral equipment. The PIC then determines
which of the incoming requests is of the highest priority, determines whether this request is of higher
priority than the level currently being serviced, and if
appropriate, issues an interrupt to the CPU. Any
combination of interrupt levels may be masked
through storage via software, of a single byte to the
interrupt register of the PIC.
Table 3. Programmable Interrupt Modes

Programmable Output goes low upon receipt of
one-shot
an external trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.
Rate
generator

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low-going pulse to the next is N
times the input clock period.

Square-wave
rate generator

Output will remain high until onehalf the count has been
completed, and' go low for the
other half of the count.

Software
triggered
strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
triggered
strobe

Output goes low for one clock
period N counts after rising edge
on counter trigger input. The
counter is retriggerable.

Event counter

On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
may read the ,number of events
occurring after the counting
."window" has been enabled or
an interrupt may be generated
after N events occur in the
system.

Mode

Operation

Fully
nested

Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.

Autorotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until the next
interrupt occurs.

Specific·
priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this aSSignment.

Polled

System software examines
priority-encoded system interrupt
status via interrupt status register.

Interrupt Addressing-The PIC generates a
unique memory address for each interrupt level.
These addresses are equally spaced at intervals of
4 or 8 (software selectable) bytes. This 32- or 64byte block may be located to begin at any 32- or 64byte boundary in the 65,536-byte memory space. A
single 8080 jump instruction at each of these addressed then provides linkage to locate each interrupt service' routine independently anywhere in
memory.
Interrupt Request Generation-Interrupt requests
may originate from 26 .sources. Four jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when
a byte of information is ready to be transferred to the
CPU (i.e., input buffer is full) or a byte of information
has been transferred to a peripheral device (i.e., output buffer is empty). Two jumper selectable interrupt

3-11

iSBC® 80/20-4 SINGLE BOARD COMPUTER

requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (Le., receive channel buffer is full), or a
character is ready to be transmitted (Le., transmit
channel data buffer is empty). A jumper selectable
request can be generated by each of the programmable timers. Nine additional interrupt request lines
are available to the user for direct interface to user
designated peripheral devices via the system bus,
and eight interrupt request lines may be jumper routed directly from peripherals via the parallel 1/0 driverlterminator section.

Memory Addressing
On-Board ROM/EPROM-O-OFFF
0-1FFF (2716)

(2708)

On-Board RAM-4K bytes ending on a 16K boundary (e.g., 3FFFH, 7FFFH, BFFFH, ... FFFFH)

Memory Capacity
On-Board ROM/EPROM-8K bytes (sockets only)
On-Board RAM-4K bytes
Off-Board Expansion-Up to 65,536 bytes in user
specified RAM, ROM, and EPROM

Power-Fail Control-Gontrol logic is also included
for generation of a power-fail interrupt which works
in conjunction with the AC-Iow signal from iSBC 635
Power Supply or equivalent.

NOTE:
ROMIEPROM may be added in 1K or 2K-byte increments.

Expansion Capabilities
Memory and 1/0 capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. High speed integer and
floating-point arithmetic capabilities may be added
by using the iSBC 310AHigh Speed Mathematics
Unit. Memory may be expanded to 65,536 bytes by
adding user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/output capacity may be increased by adding digital 1/0
and analog 1/0 expansion boards. Mass storage capability may be achieved by adding single or double
density diskette controllers as subsystems. Modular
expandable backplanes and card cages are available
to support multi board systems.

1/0 Addressing
On-Board Programmable 1/0 (see Table 1)
Port

8255
No.1

8255
No.2

11 2 / 3 41 5 6
Address E41ESIE6 EsIE91EA

8255
8255
No.1
No.2 USART USART
Control Control Data Control
E7

1/0 Capacity
Parallel-48 programmable lines (see Table 1)

SPECIFICATIONS

NOTE:
Expansion to 504 input and 504 output lines can be
accomplished using optional 1/0 boards.

Word Size

Serial Communications Characteristics

Instruction: 8, 16, or 24 bits
Data: 8 bits

Synchronous-5-8 bit characters; internal or external character synchronization; automatic sync insertion.

Cycle Time

Asynchronous-5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection.

Basic Instruction Cycle: 1.86 p.s
NOTE:
Basic instruction cycle is defined as the fastest instruction (Le., four clock cycles).

3-12

iSBC® 80/20·4 SINGLE BOARD COMPUTER

Baud Rates

Timers

Frequency (kHz)
Baud Rate (Hz)
(Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

+ 16

+ 64

9600
4800
2400
1200
600
300
150
110

2400
1200
600
300
150
75

NOTE:
Timer counts loaded as two sequential output operations to same address, as given.

Input Frequencies
Reference

Event Rate

1.0752 MHz ± 10%
(0.930 fLs period, nominal)

1.1 MHz max

NOTE:

Frequency selected by I/O write of appropriate 16-bit frequency factor to baud rate register.

NOTE:

Maximum rate for external events in event counter function.

NOTE:
Baud rate factor (16 bits) is loaded as two sequential output operations to same address (DEH)'

Interfaces·
Bus: All signals TIL compatible
Parallel I/O: All signals TTL compatible
Interrupt Requests: All TIL compatible
Timer: All signals compatible
Serial I/O: RS232C compatible, data set
configuration

Interrupts
Register Addresses (hex notation, I/O address
space)
DA Interrupt request register
DA In-service register
DB Mask register
DA Command register
DB Block address register
DA Status (polling register)

System Clock (8080A CPU)
2.1504 MHz ±0.1%

Auxiliary Power

NOTE:
Several registers have the same physical address;
sequence of access and one data bit of control
word determine which register will respond.

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selections of this auxiliary
RAM power bus is made via jumpers on the board.

3-13

intJ

ISBC~

80/20-4 SINGLE BOARD COMPUTER

Memory Protect

Line Drivers and Terminators

An active-low TTL compatible memory' protect signal
is brought out on the auxiliary connector which,
when asserted, disables readlwrite access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

1/0 Drivers-The following line drivers are all compatible with the 1/0 driver sockets on the ISSC
80/20-4
Driver

Characteristic

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

Connectors
DoubleCenters
Interface Sided Pins
(In.)
(qty)
MULTIBUS
System
Bus

Auxiliary
Bus

0.156

0.100

Mating Connectors·
ELFAB BS1562043PBB
Viking 2KH43/9AMK12
Soldered PCB Mount
EDAC 33.7086540201
ELFAB BW1562D43PBB
EDAC 337086540202
ELFAB BW1562A43PBB
Wire Wrap

NOTE:
I = inverting; NI

Ports 1 and 4 have 20 mA totem-pole bidirectional
drivers and 1 kO terminators.

110 Termlnators-2200/3300 divider or 1 kO pullup

EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB
Wire Wrap

Parallel 110
(2)

0.100 3M 3415-001 Flat Crimp
GTE Sylvania
6AD01251A1DD
Soldered

Serial 110

0.100

= non-inverting; OC = open collector.

+ ••

~:---'0\0

22OCII_*....---_~""~!---~-O

t kO +SY

AMP 15837151
EDAC 345026520202
PCB Soldered
3M 3462-0001
AMP 88373-5 Flat Crimp

OPTION 1

---'V·""
..""".---"----oo OPTION 2
280218-3

Bus Drivers
Driver

NOTE:
·Connectors compatible with those listed may also be
used.

Data
Address
Commands'

Characteristic . Sink Current (rnA)
Tri-State
Tri-State
Tri-State

50
50
32

Output Frequencies/Timing Intervals
Function
Real-Time Interrupt
Programmable One-Shot

Single Timer/Counter

Dual Timer/Counter
(Two Timers Cascaded)

Min

Max

Min

Max

1.86,..s

60.948ms

3.72,..s

1.109 hr

1.86,..s

60.948 ms

3.72,..s

1.109hr

Rate Generator

16.407 Hz

537.61 kHz

0.00025 Hz

268.81 kHz

Square-Wave Rate Generator

16.407 Hz

537.61 kHz

0.00025 Hz

268.31 kHz

Software Triggered Strobe

1.86,..s

60.948ms

3.72,..s

1.109hr

Hardware Triggered Strobe

1.86,..s

eo.948ms

3.72,..s

1.109 hr

3-14

inter

iSBC® 80/20-4 SINGLE BOARD COMPUTER

Physical Characteristics
Width:

Reference Manual

12.00 in. (30.48 cm)

9800317D-iSBC 80/20-5
Manual (NOT SUPPLIED)

Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.26 cm)

Hardware Reference

Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

Weight: 14 oz. (397.6 gm)

Environmental Characteristics
Operating Temperature: O°C to 55°C

ORDERING INFORMATION
Part Number

Description

SBC 80/20-4

Single Board Computer with 4K
bytes RAM

Electrical Characteristics
DC POWER REQUIREMENTS
Voltage
(±5%)

Without
PROM(I)
(max)

Wlth4K
PROM(2)
(max)

With
ISBC530(3)
(max)

RAM
Only(4)
(max)

Wlth8K
PROM(5)
(max)

Vee = +5V
Voo = +12V
VBB = -5V
VAA = -12V

= 4.0A

4.SA
350 rnA
leOmA
20 rnA

4.SA
450 rnA
leOmA
l20mA

1.lA

100 = SOmA
IBB = 2mA

5.2A
SOmA
2mA
20 rnA

Icc

IAA

= 20 rnA

NOTES:
1. Does not include power required for optional PROM, I/O. drivers, and I/O terminators.
2. With four 2708 EPROMs and 2200/3300 input terminators installed for 32 1/0 lines, all terminator. inputs low.
3. With four 2708 EPROMs, 2200/3300 input terminators installed for 32 1/0 lines, all terminator inputs low, and iSSC 530
Teletypewriter Adapter drawing power from serial port connector.
4. RAM chips powered via auxiliary power bus.
5. With four 8716 EPROMs and eight 2200/3300 input terminators installed, all terminator inputs low.

3-15

inter

iSBC® 80/24A
SINGLE BOARD COMPUTER

• Single Board
•
•
•

Upward Compatible with iSBC SO/20-4
Computer

SOS5A-2 CPU Operating at 4.S or 2.4
MHz

Two iSBXTM Bus Connectors for iSBX
MULTIMODULETM Board Expansion
SK Bytes of Static Read/Write Memory

•
4S Programmable Parallel I/O Lines
• .with
Sockets for Interchangeable Line
Sockets for Up to 32K Bytes of Read
Only Memory

Drivers and Terminators

•

Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates

•
•
•
•

Full MULTIBUS® Control Logic for
Multimaster Configurations and System
Expansion
Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
12 Levels of Programmable Interrupt
Control
Auxiliary Power Bus, Memory Protect,
and Power-Fail Interrupt Control Logic
Provided for Battery Backup RAM
Requirements

The Intel 80/24A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's LSI technology to provide economical, self-contained computer-based
solutions for OEM applications. The iSBC 80/24A board is a complete computer system on a single 6.7 x
12.00-inch printed circuit card. The CPU, system clock, iSBX bus interface, read/write memory, read only
memory sockets, I/O ports and drivers, serial communications interface, priority interrupt logic, and programmable timers all reside on the board. Full MULTIBUS interface logic is included to offer compatibility with the
Intel OEM Microcomputer Systems family of Single Board Computers, expansion memory options, digital and
analog I/O expansion boards, and peripheral and communications controllers.

142927-1

3-16

September 1987
Order Number: 142927-004

iSBC® 80/24A SINGLE BOARD COMPUTER

The iSBX 350 Parallel 110 MULTIMODULE board
provides 24 110 lines using an 8255A Programmable
Peripheral Interface. Therefore two iSBX 350 modules together with the iSBC 80/24A board may offer
96 lines of programmable 110. Alternately, a serial
port may be added using the iSBX 351 Serial 110
MULTIMODULE board and math may be configured
on-board with the iSBX 331 FixedlFloating Point
Math MULTIMODULE board. Future iSBX products
are also planned. The iSBX MULTIMODULE board
is a logical extension of the on-board programmable
110 and is accessed by the iSBC 80/24A single
board computer as common 110 port locations. The
iSBX board is coupled directly to the 8085A-2 CPU
and therefore becomes an integral element of the
iSBC 80/24A single board computer providing optimum performance. All MULTIMODULE boards offer
incremental expansion, optimum performance, and
minimal cost.

FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's powerful 8-bit N-chanhel 8085A-2 CPU fabricated on a single LSI chip, is the central processor
for the iSBC 80/24A board operating at either 4.8 or
2.4 MHz Ourriper selectable). The 8085A-2 CPU is
directly software compatible with the Intel 8080A
CPU. The 8085A-2 contains six 8-bit general purpose registers and an accumulator. The six general
purpose registers may be addressed individually or
in pairs, providing single and double precision operators. Minimum instruction execution time is 826
nanoseconds. A block diagram of the iSBC 80/24A
functional components is shown in Figure 1.

MULTIMODULETM Board Expansion
The iSBX bus interface brings designers incremental
on-board expansion at minimal cost. Two iSBX bus
MULTIMODULE connectors are provided for plug-in
expansion of any iSBX MULTIMODULE board. The
iSBX MULTIMODULE concept provides the ability to
adapt quickly to new technology, the economy of
buying only what is needed, and the ready availability of a spectrum of functions for greater application
potential. iSBX boards are available to provide expansion equivalent to the 110 available on the iSBC
80/24A board or the user may configure entirely
new functionality, such as math, directly on board.

Memory Addressing
The 8085A-2 has a 16-bit program counter which
allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of
readlwrite memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size ..

Rsmc

USER DElKlNATED

PERIPHERALS

PROGRAM.ABU!:

COMPAnaLE

PARAUEL

DEVICE

I/OUNES

SERIAL
DATA
r-~";::"',", INTERFACE

POWEAFAIL

INTERRupr~~ ~~

142927-2

Figure 1. iSBC® 80/24A Single Board Computer Block Diagram
3-17

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

brought out to two 50-piri edge connectors that mate
with flat, woven, or round cables.

Memory Capacity
The iSBC 80/24A board contains 8K bytes of static
read/write memory using an 8K x 8 SRAMs. All
RAM read and write operations are performed at
maximum processor speed. Power for the on-board
RAM may be provided on an auxiliary power bus,
and memory protect logic is included for RAM battery backup requirements.

Serial 1/0 Interface
A programmable communications interface uSing
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/24A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The USARTcan be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (Le. synchronous, or asynchronous), data format, control character format, parity,
and baud rate are all under program control. The
8251A provides full duplex, double buffered transmit
and receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The RS232C compatible interface, in conjunction
with the USART, provides' a direct interface' to
RS232C compatible terminals, cassettes, and asynchronous and synchronous modems. The RS232C
command lines serial data lines, and signal ground
line are brought out to a 26-pin edge connector that
mates with RS232C compatible flat or round cable.

Four sockets are provided for up to 32K bytes of
nonvolatile read only memory on the iSBC80/24A
board. EPROM may be added as shown with whiteout and 2732A.

Parallel 1/0 Interface
The iSBC 80/24A board contains 48 programmable
parallel I/O lines implemented using two Intel 8255A
Programmable Peripheral Interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input/output and bidirectional ports as indicated in Table 1. Therefore,
the 1/0 interface may be customized to meet specific peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable
I/O line drivers and terminators. Hence, the flexibility
of the 1/0 interface is further enhanced by the capability of selecting the appropriate combination of optional lirie drivers and terminators to provide the required sink current, polarity, and .drive/termination
characteristics for each application. The 48 programmable I/O lines and Signal ground lines are

Port

1
2
3
4
5
6

Lines
(qty)

8
8
4
4
8
8
4
4

Multimaster Capability
The iSBC 80/24A board is a full computer on a single board with resources capable of supporting a
large variety of OEM system requirements. For

Table 1.lnput/Output Port Modes of Operation
Mode of Operation
Unidirectional
Input
Output
Bidirectional
Latched &
Latched &
Unlatched
Latched
Strobed
Strobed

X
X
X
X
X
X
X
X

X
X

X
,X
X
X
'X
X
X
X

X
X

Control

X
Xl
XI

X
X

X
X2
X2

NOTES.
1. Part of port 3 must be used as a control port when either port 1 or port,2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional p o r t . .
.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.

3-18

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

mands are included so that the contents of each
counter can be read "on the fly".

those applications reqUIring additional processing
capacity and the benefits of multiprocessing (Le.
several CPUs and/or controllers logically sharing
system tasks through communication over the system bus), the iSBC 80/24A board provides full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 80/24A boards or other bus
masters to share the system bus in serial (daisy
chain) priority fashion, and up to 16 masters to share
the MULTIBUS system bus with the addition of an
external priority network. The MULTIBUS arbitration
logic operates synchronously with a MULTIBUS
clock (provided by the iSBC 80/24A board or optionally connected directly to the MULTIBUS clock)
while data is transferred via a handshake between
the master and slave modules. This allows different
speed controllers to share resources on the same
bus since transfers via the bus proceed asynchronously. Thus, transfer speed is dependent on transmitting and receiving devices only. This design provides slow master modules from being handicapped
in their attempts to gain control of the bus, but does
not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious
applications for the master-slave capabilities of the
bus are multiprocessor configurations, high speed
direct memory access (DMA) operations, and high
speed peripheral control, but are by no means limited to these three.

Table 2. Programmable Timer Functions
Operation'

Function
Interrupt on
terminal
count

When terminal count is
reached, an interrupt request
is generated. This function is
extremely useful for
generation of real-time clocks.

Programmable
one-shot

Output goes low upon receipt
of an external trigger edge or
software command and
returns high when terminal
count is reached. This
function is retriggerable.

Rate generator

Divide by N counter. The
output will go low for one input
clock cycle, and the period
from one low-going pulse to
the next is N times the input
clock period ..

Square-wave
rate generator

Software
triggered
strobe

Programmable Timers
The iSBC 80/24A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may. be independently routed to the
8259A Programmable Interrupt Controller, to the I/O
line drivers associated with the 8255A Programmable Peripheral Interface, or may be routed as inputs
to the 8255A chip. The gate/trigger inputs may be
routed to 110 terminators associated with the 8255A
or as output connections from the 8255A. The third
interval timer in the 8254 provides the programmable baud rate generator for the RS232C USART serial port. In utilizing the iSBC 80/24A board, the systems designer simply configures, via software, each
timer independently to meet system requirements.
Whenever a given time delay or count is needed,
software commands to the programmable timers/
event counters select the desired function. Seven
functions are available, as shown in Table 2. The
contents of each counter may be read at any time
during system operation' with simple read operations
for event counting applications, and special com-

Hardware
triggered
strobe

Output goes low for one clock
period N counts after rising
edge on counter trigger input.
The counter is retriggerable.

Event counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occuring
after the counting "window'
has been enabled or an
interrupt may be generated
after N events occur in the
system.

Interrupt Capability
The iSBC 80/24A board provides vectoring for 12
interrupt levels. Four of these levels are handled directly by the interrupt processing capability of the
8085A-2 CPU and represent the four highest priority
interrupts of the iSBC 80/24A board. Requests are
routed to the 8085A-2 interrupt inputs-TRAP, RST
7.5, RST 6.5, and RST 5.5 (in decreasing order of
priority), each of which generates a call instruction to
3-19

intJ

iSBC® 80/24A SINGLE BOARD COMPUTER

a unique address (TRAP: 24H; RST 7.5: 3CH; RST
6.5: 34H; and RST 5.5: 2CH). An 8085A-2 JMP instruction at each of these addresses then provides
linkage to interrupt service routines located independently anywhere in memory. All interrupt inputs, with
the exception Of the trap interrupt maybe masked
via software. The trap interrupt should be used for
conditions such as power-down sequences which
require immediate attention by the 8085A-2 CPU.
The Intel 8259A Programmable Interrupt Controller
(PIC) ,provides vectoring for the next eight interrupt
levels. As shown in Table 3, a selection of four priority processing modes is available to the systems designer for use in designing request proceSSing con-'
figurations to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PIC accepts interrupt requests from
the programmable parallel and serial lID interfaces,
the programmable timers, the system bus, iSBX bus,
or directly from peripheral equipment. The PIC then
determines which of the, incoming requests is of the,
highest priority, deterrpines whether this request is'
of higher priority than the level currently being' serviced, and, if appropriate, issues an interrupt to the
CPU. Any combination of interrupt levels may be
masked, via software, by storing a single byte in the
interrupt mask register of the PIC. The PIC generates a unique memory address for each interrupt
level. These addresses are equally spaced at inter~
vals of 4 or 8, (software selectable) bytes. This 32 or
64-byteblock may be located to begin at any 32 or
64-byteboundary in the 65,536-byte memory space.
A single 8085A-2 JMP instruction at each of these
addresses then provides linkage to locate each interrupt service routine independently anywhere in
memory.'
,

Interrupt Request Ge,neration
Interrupt requests may originiate from 23 sources.
Two, jumper selectable interrupt requests can be
generated by each iSBX MULTIMODULE board.
Two jumper selectable interrupt requests can be automatically generated by each programmable peripheral interface when a byte of information is ready
to be transferred to the CPU (Le., input buffer is full)
or a byte of information has been transferred to a
peripheral device (i.e., output buffer is empty). Three
jumper selectable interrupt, requests can be automatically generated by the iJSART when a character
is ready to be transferred to the CPU (Le., receiver
channel buffer is full), a character is ready to be
transmitted (i.e., the USART is ready to accept a
character from the CPU), or when the transmitter is
empty (Le., the USART has no character to transmit). A jumper selectable request can be generated
by each of the programmable timers. Nine interrupt
, request lines are availabie to the user for direct inter, face to user deSignated peripheral devices via the
MULTIBUS system bus. A power-fail Signal can also
be selected as an interrupt source.

Autorotating ,

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as
"
lowest.
'Equal priority~ Each level, after
receiving service, becomes
the lowest priority level until
next interrupt occurs.

Specific
priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.

Polled,

System software examines
priority-encoded system
interrupt status via interrupt
status register.

A power-fail interrupt may be detected,through the
AC-Iow signal generated by the power supply. This
signal may be configured to interrupt the 8085A-2
CPU to initiate an orderly power down instruction sequence.

MULTIBUS® System Expansion
Capabilities
'
Memory and lID capacity may be expanded and additional functions added using Intel MULTIBUS system compatible expansion boards. Memory may be
expanded to 65,536 bytes by adding user specified
combinations' of RAM boards, EPROM boards, or
combination boards. Input/output capacity may be
increased by adding digital I/O and analog lID expanSion boards. Mass storage capability may be
achieved by adding single or double density diskette
or hard disk controllers as subsystems. Expanded
communication needs can be handled by communication' controllers. 'Modular expandable backplanes
and card cages are available to support multi board
systems.

Table 3. Programmable Interrupt Modes
Mode,
Fully nested

Power-Fail Control

3-20

iSBC® 80/24A SINGLE BOARD COMPUTER

SPECIFICATIONS

OFF-BOARD EXPANSION

Word Size

Up to 64K bytes using user specified combinations
of RAM, ROM, and EPROM.

Instruction- 8, 16 or 24 bits
Data

Up to 12BK bytes using bank select control via I/O
port and 2 jumper options.

8 bits

May be disabled using PROM ENABLE via 1/0 port
and jumper option, resulting in off-board RAM overlay capability.

Cycle Time
BASIC INSTRUCTION CYCLE

1/0 Addressing

826 ns (4.84 MHz operating frequency)
1.65 p.s (2.42 MHz operating frequency)

ON-BOARD PROGRAMMABLE 1/0

NOTE:
Basic instruction cycle is defined as the fastest instruction (i.e., four clock cycles).

Memory Addressing
ON-BOARD EPROM

O-OFFF using 2708, 2758 (1 wait state)
0-1 FFF using 2716 (1 wait state)
. 0-3FFF using 2732 (1 wait state)
using 2732A (no wait states)
0-7FFF using 2764A (no wait states)
ON-BOARD RAM

EOOO-FFFF
NOTE:
Default configuration-may be reconfigured to top
end of any 16K boundary.

Memory Capacity

8255A No.1
PortA
Port B
PortC
Control

E4
E5
E6
E7

B255A No.2
PortA
Port B
PortC
Control

E8
E9
EA
EB

B251A
Data
Control

EC, EE
ED,EF

iSBX MULTIMODULE J5
MCSO
MCSl

CO-C7
C8-CF

iSBX MULTIMODULE J6
MCSO
MCSl

FO-F7
FB-FF

1/0 Capacity

ON-BOARD EPROM

Parallel
Serial

32K bytes (sockets only)
May be added in 1K (using 2708 or 2758), 2K (using
2716), 4K (using Intel 2732A), or BK (using Intel
2764A) byte increments.

1/0 Address

Device

- 48 programmable lines
- 1 transmit, 1 receive, 1 SID,
1 SOD

. iSBX MULTlMODULE- 2 iSBX
Boards

ON-BOARD RAM

BK bytes

3-21

MUL TlMODULE

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

Serial Communications Characteristics

Interrupts

Synchronous ~ 5-8 bit characters; internal or external character synchronization;
automatic sync insertion
Asynchronous- 5-8 bit characters; break character generation; 1, 1%, or 2 stop
bits; false start bit detectors.

Addresses for 8259A Registers (hex notation, 1/0
address space)
OA or 08 Interrupt request register
OA or 08 In-service register
DB or 09 Mask register
OA or 08 Command register
DB or 09 Block address register
OA or 08 Status (polling register)

Baud Rates
Output
Frequency
in kHz
153.6
76.8
38.4 .
19.2
9.6
4.8
2.4
1.76

NOTE:
Several registers have the same physical address;
sequence of access and one data bit of. control
word determine which register will respond.

Baud Rate (Hz)
Synchronous

38400
19200
9600
4800
2400
1760

Asynchronous
+16
9600
4800
2400
1200
600
300
150
110

+64
2400
1200
600
300
150
75

Interrupt levels routed to 8085A-2 CPU automatically
vector the processor to unique memory locations:
Interrupt
Input
TRAP
RST7.5
RST6.5
RST5.5

NOTE:
Frequency selected by 1/0 write of appropriate 16-bit frequency factor to baud rate register.

Memory.
Address
24
3C
34
2c

Priority'

Type

Highest

Non-maskable
Maskable
Maskable
Maskable

,J,
Lowest

Timers
Register Addresses (hex notation, 1/0 address
space)
OF
Control register
DC
Timer 0
DO
Timer 1
DE
Timer 2

Register Address (hex notation, 1/0 address
space)
DE Baud rate register
NOTE:
Baud rate factor (16 bits) is loaded as two sequential output operations to same address (OEH)'

NOTE:
Timer counts loaded as two sequential output operations to same address as given.

Output Frequencies/Timing Intervals

Function

Single
Timer/Counter
Min

Max

Dual Timer/Counter
(Two Timers
Cascaded)
Min

Max

Real-Time Interrupt
1.86 )Ls 60.948 ms
3.72 )Ls
1.109 hrs
Programmable One-Shot
1.86 )Ls 60.948 ms
1.109 hrs
3.72 )Ls
Rate Generator
16.407 Hz 537.61 kHz 0.00025 Hz 268.81 kHz
Square-Wave Rate Generator 16.407 Hz 537.61 kHz 0.00025 Hz 268.81 kHz
Software Triggered Strobe
1.86 )Ls 60.948 ms
3.72 )Ls
1.109 hrs
Hardware Triggered Strobe
1.86 )Ls 60.948 ms
3.72 )Ls
1.109 hrs
NOTE:
Input frequency to timers is 1.0752 MHz (default configuration).

3-22

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

Input Frequencies

Memory Protect

Reference: 1.0752 MHz ± 0.1 % (0.930 IJ-s period,
nominal)

An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables readlwrite access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

Event Rate: 1.1 MHz max

Interfaces
MULTIBUS

All signals TTL compatible
All signals TTL compatible

Parallel 110

All signals TTL compatible

Serial 110

- RS232C compatible, configu-

iSBXBus

Line Drivers and Terminators
110 Driver- The following line drivers and terminators are all compatible with the 110 driver sockets on the iSBC 80/24A Board:

rable as a data set or data terminal
Timer
- All Signals TTL compatible
Interrupt Requests- All TTL compatible

System Clock (8085A-2 CPU)
4.84 or 2.42 MHz ± 0.1 % (jumper selectable)

Driver

Characteristic

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:

Auxiliary Power

I = inverting; NI = non-inverting; OC = open collector.

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of readlwrite memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Ports E4 and E8 have 32 mA totem-pole drivers and
1K terminators.
110 Terminators-220n/330n divider of 1 kn pullup.

Connectors
Double-Sided
Pins (qty)

Centers
(In.)

MULTIBUS
System Bus

0.156

ELFAB BS1562043PBB
Viking 2KH43/9AMK12 Soldered PCB Mount
EDAC 337086540201
ELFAB BW1562D43PBB
EDAC337086540202
ELFAB BW1562A43PBB Wire Wrap

Auxiliary Bus

0.100

EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB Wire Wrap

iSBX Bus (2)
Parallel 110 (2)

0.100

iSBX 960-5

0.100

3M 3415-001 Flat Crimp
GTE Sylvania 6AD01251 A 1DD Soldered

Serial 110

0.100

AMP 15837151
EDAC 345026520202 PCB Soldered
3M 3462-0001
AMP 88373-5 Flat Crimp

Interface

Mating Connectors·

·NOTE:
Connectors compatible with those listed may also be used.

3-23

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

2200/3300 OPTION 1

Bus Drivers

----,

2200

+5V~;~;

Function

Characteristic

Sink Current (mA)

Data
Address
Commands

Tri-State
Tri-State
Tri-State

32
32
32

Physical Characteristics
1 kOOPTION 2

Width:

lkO
+5V-------,~"-----,___--

12.00 in. (30.48 em)

Height: 6.75 in. (17.15 em)

142927-3

Depth:

0.50 in. (1.27 em)

Weight: 12.64 oz. (354 gm)

Electrical Characteristics
DC POWER REQUIREMENTS

Current Requirements
Configuration

Vee = +SV
± S% (max)

Voo = +12V
±S% (max)

VBB = -SV
±S% (max)

VAA = -12V
±S% (max)

Without
EPROM(1)

2.66A

40mA

20mA

RAM Only(2)

0.01A

With
iSBC530(3)

2.66A

140mA

With4K
EPROM(4)
(using 2708)

3.28A

300mA

With4K
EPROM(4)
(using 2758)

3.44A

40mA

20 mA

With8K
EPROM(4)
(using 2716)

3.44A

40mA

20 mA

With 16K
EPROM(4)
(using 2732A)

3.46A

40mA

20mA

With 32K
EPROM(4)
(using 2764A)

3.42A

40mA

20mA

180mA

120mA

20mA

NOTES:
1. Does not include power for optional EPROM, I/O drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus.
3. Does not include power for optional EPROM, I/O drivers, I/O terminators. Power for iSBC 530
Adapter is supplied via serial port connector.
4. Includes power required for four EPROM chips, and I/O terminators installed for 16 I/O lines; all
terminators inputs low.

3-24

iSBC® 80/24A SINGLE BOARD COMPUTER

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Environmental Characteristics
Operating Temperature: O°C to 55°C

Reference Manual

ORDERING INFORMATION

148437-001- iSBC 80/24A Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED)

Part Number Description
SBC 80/24A Single Board Computer

3-25

iSBC® 80/30
SINGLE BOARD COMPUTER
808SA CPU Used as Central Processing
Programmable Synchronous!
• Unit
• Asynchronous
RS232C Compatible
Serial Interface with Fully Software
16K Bytes of Dual Port Dynamic Read!
• Write Memory with On-Board Refresh
Selectable Baud Rate Generation
12 Levels of Programmable Interrupt
Sockets for up to 8K Bytes of Read
•
• Only
Control
Memory
Programmable 16-Bit BCD or
Sockets for 8041A18741A Universal
• Two
• Peripheral Interface and
Binary Counters
Interchangeable Line Drivers and Line
Auxiliary Power Bus, Memory Protect,
• and
Terminators
Power-Fail Interrupt Control Logic
for RAM Battery Backup
24 Programmable Parallel I/O Lines
• with Sockets for Interchangeable Line • Compatible with Optio,nal iSBC® 80
Drivers and Terminators
CPU, Memory, and I/O Expansion
Boards
TIBUS® Control Logic Allowing
• upFulltoMUL
16 Masters to Share the System
The iSBC 80/30 Single Board Computer is a member of Intel's complete line of OEM computer systems which
take full advantage of Intel's LSI technology to provide economical self-contained computer-based solutions
for OEM applications. The iSBC 80/30 is a complete computer system on a single 6.75 x 12.00-inch printed
circuit card. The CPU, system clock, readlwrite memory, nonvolatile read only memory, universal peripheral
interface capability, 1/0 ports and drivers, serial communications interface, priority interrupt logic, programmable timers, MULTIBUS control logic, and bus expansion drivers all reside on the board.

280219-1

3-26

September 1987
Order Number: 280219-002

intJ

iSBC® 80/30 SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's powerful 8-bit n-channel 808SA CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 80/30. The 8085A CPU is directly software
compatible with the Intel 8080A CPU. The 8085A
contains six 8-bit general purpose registers and an
accumulator. The six general purpose registers may
be addressed individually or in pairs, providing both
single and double precision operators. The minimum
instruction execution time is 1.45 microseconds. The
808SA CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 80/30
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this eternal stack. This stack proilides subroutine nesting bounded only by memory .
size.

to 64K-address space. The iSBC 80/30 provides extended addressing jumpers to allow the on-board
RAM to reside within a one megabyte address
space when accessed via the MULTIBUS. In addition, jumper options are provided which allow the
user to reserve 8K- and 16K-byte segments of onboard RAM for use by the 8085A CPU only. This
reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address
space.

EPROM/ROM Capacity ,
Sockets for up to 8K bytes of nonvolatile read only
memory and provided on the iSBC 80/30 board.
Read only memory may be added in 1 K-byte increments up to a maximum of 2 K-bytes using Intel
2708 or 2758 erasable and electrically reprogrammabie ROMs (EPROMs); in 2 K-byte increments up
to a maximum of 4 K-bytes using Intel 2716
EPROMs; or in 4 K-byte increments up to 8K-bytes
maximum using Intel 2732 EPROMs. All on-board
EPROM/ROM operations are performed at maximum processor speed.

Bus Structure

Parallel I/O Interface

The iSBC 80/30 has an internal bus for all on-board
memory and I/O operations and a system bus (Le.,
the MULTIBUS) for all external memory arid I/O operations. Hence, local (on-board) operations do not
tie up the system bus, and allow true parallel processing when several bus masters (i.e., DMA devices, other single board computers) are used in a multimaster scheme. A block diagram Of the iSBC
80/30 functional components is shown in Figure 1.

The iSBC 80/30 contains 24 programmable parallel
I/O lines implemented using the Intel 825SA Programmable Peripharal Interface. The system software is used to configure the I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. Therefore, the I/O interface may be customized to meet specific peripheral requirements. In order to take full advantage of
the large number of possible I/O configurations,
sockets are provided for interchangeable I/O line
drivers and terminators. Hence, the flexibility of the
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional
line drivers and terminators to provide the required
sink current, polarity, and drive/termination characteristics for each application. The 24 programmable
I/O lines and Signal ground lines are brought out to a
50-pin edge connector that mates with flat, woven,
or round cable.

RAM Capacity
The iSBC 80/30 contains 16K bytes of dynamic
read/write memory using Intel 2117 RAMs. All RAM
read and write operations are performed at maximum processor speed. Power for the on-board RAM
may be provided on an auxiliary power bus, and
memory protect logic is included for RAM battery
backup requirements. The iSBC 80/30 contains a
dual port controller, which provides dual port capability for the on-board RAM memory. RAM accesses
may occur from either the iSBC 80/30 or from any
other bus master interfaced via the MULTIBUS.
Since on-board RAM accesses do not require the
- MULTIBUS, the bus is available for any other concurrent operations (e.g., DMA data transfers) requiring the use of the MULTIBUS. Dynamic RAM refresh
is accomplished automatically by the iSBC 80/30 for
accesses originating from either the CPU or via the
MULTIBUS. Memory space assignment can be selected independently for on-board and MULTIBUS
RAM accesses. The on-board RAM, as seen by the
8085A CPU, may be placed anywhere within the 0-

Universal Peripheral Interface (UPI)
The iSBC 80/30 provides sockets for a user sup.plied Intel 8041A18741A Universal Peripheral Interface (UPI) chip and the associated line drivers and
terminators for the UPI's I/O ports. The
8041A/8741A is a single chip microcomputer containing a CPU, 1K bytes of ROM (8041 A) or EPROM
(8741 A), 64 bytes of RAM, 18 programmable I/O
lines, and an 8-bit timer. Special interface registers
included in the chip allow the 8041A to function as a
3-27

" SERIAL"
DATA
INTERFACE

RS232C
COMPAnILE"
DEVICE

USER DESIONATED
PERIPHERALS
42 PROGRAMMAILE

PARALLEL UO LINES

iil

:-"

en
~

POWER FAIL

. INTEARUPT

m
o@

41NTEAAUPT
REQUEST LINES

2 INTERRUPTREQUEST LINES

\!l
CD

Q
.....

....
o
w

Co)

. 8 INTERRUPT

en
Z
C)

REQUEST

(/)

s·

LINES

IQ
CA)

r
m

~
::u

i
3

PRC:~AiI.

..;C

c
o
o

MAILE
TIMERS

i:
"U

-t
m

::u

iii
3

MULTIBUS

280219-2

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

slave processor to the iSBC 80/30's 8085A CPU.
The UPI allows the user to specifiy algorithms for
controlling user peripherals directly in the chip,
thereby relieving the 8085A for other system functions. The iSBC 80/30 provides an RS232C driver
and an RS232C receiver for optional connection to
the 8041A/8?41A in applications where the UPI is
programmed to handle simple serial interfaces. For
additional information, including 8041 Al8? 41 A instructions, refer to the UPI-41A User's Manual and
application note AP-41.

of OEM system requirements. For those applications
requiring additional processing capacity and the
benefits of multiprocessing (i.e., several CPUs and/
or controilers logically sharing system tasks through
communication over the system bus), the iSBC
80/30 provides full MULTIBUS arbitration control
logic. This control logic allows up to three iSBC 80/
30's or other bus masters to share the system bus in
serial (daisy chain) priority fashion, and up to 16
masters to share the MULTIBUS with the addition of
an external priority network. The MULTIBUS arbitra~
tion logic operates synchronously with a MULTIBUS
clock (provided by the iSBC 80/30 or optionally connected directly to the MULTI BUS clock) while data is
transferred via a handshake between the master
and slave modules. This allows different speed controllers to share resources on the same bus, and
transfer via the bus proceed asynchronously. Thus,
transfer speed is dependent on transmitting and receiving devices only. This design prevents slow
master modules from being handicapped in their attempts to gain control of the bus, but does not restrict the speed at which faster moqules can transfer
data via the same bus. The most obvious applications for the master-slave capabilities of the bus are
multiprocessor configurations, high speed direct
memory access (DMA) operations, and high speed
peripheral control, but are by no means limited to
these three.

Serial 1/0
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/30. A software selectable baud rate
generator provides the USART with all common
communication frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM By-Sync).
The mode of operation (Le., synchronous or asynchronous), data format, control character format,
parity, and baud rate are all under program control.
The 8251A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a
direct interface to RS232C compatible terminals,
cassettes, and asynchronous and synchronous modems. The RS232C command lines, serial data
lines, and signal ground line are brought out to a 26pin edge connector that mates with RS232C compatible flat or round cable.

Programmable Timers
The iSBC 80/30 provides three independent, fully
programmable 16-bit interval timers/event counters
utilizing the Intel 8253 Programmable Interval Timer.
Each counter is capabile of operating in either BCD
or binary modes. Two of these timers/counters are
available to the systems designer to generate accurate time intervals under software control. Routing
for the outputs and gate/trigger inputs of two of
these counters is jumper selectable. The outputs
may be independently route~ to the 8259A Program-

Multimaster Capability
The iSBC 80/30 is a full computer on a single board
with resources capable of supporting a great variety

Mode of Operation
Port

Unidirectional

Lines
(qty)

Input
Unlatched

1
2
3

8
8
4
4

X
X
X
X

Output

Latched &
Strobed

X
X

Latched

X
X
X
X

Bidirectional

Control

Latched &
Strobed

X
X

X
Xl
Xl

NOTE:

1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

3-29

iSBC@ 80/30 SINGLE BOARD COMPUTER

contents of each counter may be read at any time
during system operation with simple read operations
for event counting applications, and special commands are included so that the contents of each
counter can be read "on the fly".

mabie Interrupt Controller, to the 110 line drivers associated with the 825SA Programmable Peripheral
Interface,· and to the 8041A/8741A Universal Programmable Interface, or may be routed as inputs to
the 825SA and 8041A/8741A chips. The gate/trigger inputs may be routed to 1/0 terminators associated with the 8255A or as output connections from
the 8255A. The third interval timer in the 8253 provides the programmable baud rate generator for the
iSBC 80/30 RS232C USART serial port. In utilizing
the iSBC 80/30, the systems designer simply configures, via software, each timer independently to meet
system requirements.

Interrupt CapabilitY
The iSBC 80/30 provides vectoring for 12 interrupt
levels. Four of these levels are handled directly by
the interrupt processing capability of the 8085A CPU
and represent the four highest priority interrupts of
the iSBC 80/30. Requests are routed to the 808SA
interrupt inputs, TRAP, RST 7.5, RST 6.5, and RST
5.5 (in decreasing order of priority) and each input
generates a unique memory address (TRAP: 24H;
RST 7.5: 3CH; RST 6.5: 34H; and RST 5.5: 2CH). An
8085A jump instruction at each of these addresses
then provides linkage to interrupt service routines
located independently anywhere in memory. All interrupt inputs with the exception of the trap interrUPt
may be masked via software. The trap interrupf
should be used for conditions such as power-down
sequences which require immediate attention by the
808SA CPU. The Intel 8259A. Programmable Interrupt Controller (PIC) provides vectoring for the next
eight,interrupt levels. As shown in Table 3, a selection of four priority processing modes is available to
the systems designer for use in designing request
processing configurations to match· system requirements. Operating mode and priority assignments
may be reconfigured dynamically via software at any
time during system operation; The PIC accepts interrupt requests from the programmable parallel and
serial 1/0 interfaces, the programmable timers, the
system bus,. or directly from peripheral equipment.
The PIC then determines which of the incoming requests is of the highest priority, determines whether
this request is of higher priority than the level currently being serviced, and, if appropriate, issues. an
interrupt to the CPU. Any combination of interrupt
levels may be masked, via software, by storing a
single byte in the interrupt mask register of the PIC.
The PIC generates a unique memory address for
each interrupt level. These addresses are equally
spaced at intervals of 4 or 8 (softWare selectable)
bytes. This 32- or 64-byte block may be located to
begin at any 32- or 64-byte boundary in the 65,536byte memory space. A single 8085A jump instruction
at each of these addresses then provides linkage to
locate each interrupt service routine independently
anywhere in memory.

Whenever a given time delay or count is needed,
software commands to the programmable timersl
event counters select the. desired function. Seven
functions are available, as shown in Table·.2. The
Table 2. Programmable Timer Functions
Operation

Function
Interrupt on
Terminal Count

Programmable
One-Shot

Output goes low upon receipt of
an external trigger edge or
.
software command and returns
high when terminal count is
reached. This function is
retriggerable.
Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low-going pulse to the next is N
times the input clock period.

Rate
Generator

Square-Wave
Rate Generator
Software
Triggered
Strobe
Hardware
Triggered
Strobe
Event Counter

When terminal count is
reached, an interrupt request is
generated. This function is
extremely useful for generation
ofreal-time clocks. .'

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.
Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.
Output ~oes low for one clock
period counts after rising
edge on counter trigger input.
The counter is retriggerable.
On a jumper selectable basis,
the clock input becomes an
input from the external system.
CPU may read the number of
events occurring after the
counting "window" has been
enabled or an interrupt may be
generated after N events occur
in the system.

Interrupt Request Generation-Interrupt requests
may originate from 18 sources. Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when

3-30

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

a byte of information is ready to be transferred to the
CPU (i.e., input buffer is full) or a byte of information
has been transferred to a peripheral device (i.e., output buffer is empty). Two jumper selectable interrupt
requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (i.e., receive channel buffer is full), or a

density diskette controllers as sub-systems. Modular
expandable backplanes 'and cardcages are available
to support multi-board systems.

SPECIFICATIONS
Word Size

Table 3. Programmable Interrupt Modes
Mode
Fully
Nested
Autorotating
Specific
Priority
Polled

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Instruction: 8, 16, or 24 bits
Data: 8 bits

Cycle Time
Basic Instruction Cycle: 1.45 f-LS
NOTE:
Basic instruction cycle is defined as the fastest instruction (i.e., four clock cycles).

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.
System software examines
priority-encoded system
interrupt status via interrupt
status register.

Memory Addressing
On-Board ROM/EPROM: 0-07FF (using 2708 or
2758 EPROMs); O-OFFF (using 2716 EPROMs); 01FFF (using 2716 EPROMs; 0-1 FFF (using 2732
EPROMs).

character is ready to be transmitted (i.e., transmit
channel data buffer is empty). A jumper selectable
request can be generated by each of the programmable timers and by the universal peripheral interface, eight additional interrupt request lines are
available to the user for direct interface to user designated peripheral devices via the system bus, and
two interrupt request lines may be jumper routed directly from peripherals via the parallel I/O driver/terminator section.

On-Board RAM: 16K bytes of dual port RAM starting
on a 16K boundary. One or two 8 K-byte segments
may be reserved for CPU use only.

Memory Capacity
On-Board Read Only Memory: 8K bytes (sockets
only)
On-Board RAM: 16K bytes
Off-Board Expansion: Up to 65,536 bytes in user
specified combinations of RAM, ROM, and EPROM

Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 Power Supply or equivalent.

NOTE:
Read only memory may be added in 1 K, 2K, or 4K
byte increments.

Expansion Capabilities
Memory and I/O capacity may be expanded and additionaJ functions added by using Intel MULTIBUS
compatible expansion boards. High speed integer
and floating point arithmetic capabilities may be added by using the iSBC 310A High Speed Mathematics
Unit. Memory may be expanded to 65,536 bytes by
adding user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/output capacity may be increased by adding digital I/O
and analog I/O expansion boards. Mass storage capability may be achieved by adding single or double

I/O Addressing
On-Board Programmable: I/O (see Table 1)
Port

8255A

8041A18741A

1 121 3 IControl
Address EsIE91EAI

3-31

USART

Data 1Control DatalControl
E4 or EsIE5 or E7 EC 1 ED

inter

ISBC® 80/30 SINGLE BOARD COMPUTER

110 Capacity
Parallel: 42 programmable lines using one 8255A
(241/0 lines) and an optional 8.o41A18741 A (18 I/O
lines)
Serial: 2 programmable lines using one 8251A and
an optional 8041A/8741 A programmed'for serial operation
NOTE:
For additional information on the 8.o41A/8741A refer to the UPI-41 User's Manual (Publication
98.0.05.04).

Serial Communications Characteristics
Synchronous: 5-8 bit characters; internal or external
chariicter synchronization; automatic sync insertion.
Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection.

NOTE:
Several registers have the same physical address;
sequence of access and one data bit of control
word determine which register will respond.
Interrupt Levels routed to 8.o85A CPU automatically
vector the processor to unique memory locations:
Interrupt
Input

Memory
Address

TRAP
RST7.5
RST6.5
RST5.5

24
3C
34
2C

Priority

Type

Highest

Non-maskable
Maskable
Maskable
Maskable

Lowest

Timers
Register Addresses (Hex notation, I/O address
space)
DF Control register
DC Timer .0
DD Timer 1
DE Timer 2

Baud Rates
Frequency (kHz)
(Software
Selectable) .

Baud Rate (Hz)
Synchronous

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

Asynchronous

+ 16

+ 64

9600
4800
2400
1200
600
300
150
110

2400
1200
600
300
150
75

NOTE:
Timer counts loaded as two sequential output operations to same address, as given.
Input Frequencies
Reference: 2.46 MHz ±.o.1% (.0 ..041 ,...S period,
nominal); 1.23 MHz ±.o.1% (.0.81 ,...S period, nominal); or 153.6.0 kHz ± .0.1 % (6.51 ,...S period nominal).

NOTE:
Above frequencies are user selectable

NOTE:
Frequency selected by 110 write of appropriate 16-bit frequency factor to baud rate register (8253 Timer 2) .

Interrupts
Addresses for 8259A Registers (Hex notation, I/O
address space)
DA Interrupt request register
DA In-service register
DB Mask register .

Event Rate: 2.46 MHz max
NOTE:
Maximum rate for external events in event counter·
function.
.

Interfaces
MULTIBUS: All signals TIL compatible
Parallel I/O: All signals· TIL compatible

DA Command register

Interrupt Requests: All TIL compatible

DB Block address register

Timer: All signals TIL compatible

DA Status (polling register)

Serial I/O: RS232C compatible, data set
configuration

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

System Clock (808SA CPU)
2.76 MHz ±0.1%

Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Driver

Characteristics

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I

Connectors
Interface
Bus
Parallel 110
Serial 110

Pins Centers
(qty) (in.)
86
50
26

0.156
0.1
0.1

= invertin9; NI = non-inverting; OC = open collector

Mating Connectors

Port 1 of the 8255A has 20 rnA totem-pole bidirectional drivers and 1 kO terminators.

Viking 2KH43/9AMK12
3M 3415-000
3M 3462-000

110 Terminators: 2200/3300 divider or 1 kO pullup
2200

OPTION 1

Memory Protect
An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

OPTION 2

2200/3::~r-_-_-_-_-_-_.3
....~N'~""~...,...---------:1--0
..
1 kO

1 kO
+5V - - -.........N'V....

-----o
280219-3

Bus Drivers

Line Drivers and Terminators
110 Drivers: The following line drivers are all compatible with the 110 driver sockets on the iSBC
80/30.

Function

Characteristic

Sink Current (rnA)

Data
Address
Commands

Tri-State
Tri-State
Tri-State

50
50
32

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 18. oz. (509.6 gm)
Output Frequencies/Timing Intervals
Function
Real-Time Interrupt
Progrt;lmmable One-Shot
Rate Generator
Square-Wave Rate Generator
Software Triggered Strobe
Hardware Triggered Strobe

Single Timer/
Counter

Dual Timer/Counter
(Two Timers Cascaded)

Min

Max

Min

Max

1.63,...s
1.63,...s
2.342 Hz
2.342 Hz
1.63,...s
1.63,...s

427.1 ms
427.1 ms
613.5 kHz
613.5 kHz
427.1 ms
427.1 ms

3.26,...s
3.26,...5.
0.000036 Hz
0.000036 Hz
3.26,...s
3.26,...s

466.50 min
466.50 min
306.8 kHz
306.8 kHz
466.50 min
466.50 min

3-33

intJ

iSBC® 80/30 SINGLE BOARD COMPUTER

Electrical Characteristics
DC POWER REQUIREMENTS
Current Requirements
Configuration
Without EPROM(l)

Vee = +SV
±S% (max) ,
Icc

= 3.5A

Voo = +12V
±S% (max)
100 =' 220mA

Vaa = -SV
±S% (max)
IBB

= -

VAA = -12V
±S% (max)

= 50mA

3.6A

220mA

350mA

20mA

2.5mA

With iSBC 530(4)

3.5A

320mA

150mA

With 2K EPROM(5)
(using 8708)

4.4A,

350mA

95mA

40mA

With 2K EPROM(5)
(using 2758) .

4.6A

220mA

50mA

With 4K EPROM(5)
(using 2716)

4.6A

220mA

50mA

With 8K EPROM(5)
(using 2332)

4.6A

220mA

50mA

With 8041/8741 (2)
RAM only(3)

50 rnA

NOTES:
1. Does not include power required for optional EPROM/ROM, 8041A18741A I/O drivers, and I/O terminators.
2. Does not include power required for optional EPROM/ROM. I/O drivers and. I/O terminators.
3. RAM chips powered via auxiliary power bus.
4.00es not include power required for optional EPROM/ROM, 8041A/8741A I/O drivers, and I/O terminators. Power for
iSBC 530 is supplied through the serial port connector.
5. Includes power reqiured for two EPROM/ROM chips, 8041A18741A and 2200/3300 input terminators installed for 34
I/O lines; all terminator inputs low.

Reference manuals are shipped with each product
only if designated SUPPLIED. Manuals may be ordered from any Intel sales representative, distributor
office or from Intel Uterature Department, 3065
Bowers Avenue, Santa Clara, California 95051.

Environmental Characteristics
Operating Temperature: O'C to 55'C

Reference Manual
ORDERING INFORMATION

98006118- iSBC 80/30 Single Board Computer
Hardware .Reference . Manual (NOT
SUPPLIED)

Part Number Description
SBC 80/30
Single Board Computer with 16K
bytes RAM

3-34

iSBC® 86/05A
SINGLE BOARD COMPUTER
(8086-2) Microprocessor with 5
Programmable Synchronous/
• Asynchronous
• or8086/10
RS232C Compatible
8 MHz CPU Clock

•
•

Serial Interface with Software
Selectable Baud Rate

Software Compatible with 8086, 8088,
80186,80286 Based 16-bit Single Board
Computers

•
•
•
•
•

Optional 8086/20 Numeric Data
Processor with iSBC® 337 A
MULTIMODULETM Processor

•
for up to 256K Bytes of JEDEC
• Sockets
24/28-Pin Standard Memory Devices;
8K bytes of Static RAM; Expandable
On-Board to 16K Bytes

Expandable On-Board to 512K Bytes

•

Two iSBXTM Bus Connectors

24 Programmable Parallel I/O Lines
Two Programmable 16-Blt BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Bus Interface for
Multimaster Configurations and System
Expansion
Supported by a Complete Family of
Single Board Computers, Memory,
Digital and Analog I/O, Peripheral
Controllers, Packaging and Software

The iSBC 86/05A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained, computer-based
solutions for OEM applications. The iSBC 86/05A board is a complete computer system on a single 6.75 x
12.00 in. printed circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O
ports and drivers, serial communications interface, priority interrupt logic and programmable timers, all reside
on the board. The large control storage capacity makes the iSBC 86/05A board ideally suited for control-oriented applications such as process control, instrumentation, industrial automation, and many others.

143325-1

3-35

September 1987 '
Order Number: 143325-003

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

Memory Configuration
The iSBC 86/05A microcomputer contains 8K bytes
of high-speed 8K x 4 bit static RAM on-board. In
addition, the above on-board RAM may be expanded to 16K bytes with the iSBC 302 MULTIMODULE
RAM option which mounts on the iSBC 86/05A
board. All on-board RAM is accessed by the 8086-2
CPU with no wait states, yielding a memory cycle
time of 500 ns.

Central Processing Unit
The central processor for the iSBC 86/05A board is
Intel's iAPX 86/10 (8086-2) CPU. a clock rate of 8
MHz is supported with a jumper selectable option of
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit memory
base pointer registers and two 16-bit index registers.
All are accessed by a total of 24 operand addressing
modes for comprehensive memory addressing and
for support of the data· structures required for today's structured, high level languages as well as assembly language.

The iSBC 86/05A board also has four 28-pin, 8-bit
wide (byte-wide) sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
256K bytes of EPROM are supported in 64K byte
increments with Intel 27512 EPROMs. The iSBC
86/05A board also supports 2K x 8, 4K x 8, 8K x 8,
16K x 8 and 32K x 8 EPROM memory devices.
These sites also support 2K x 8 and 8K x 8 bytewide static RAM (SRAM) devices and iRAM devices,
yielding up to 32K bytes of SRAM in 8K byte increments on the baseboard.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8- and .16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

When the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 512K bytes of
EPROM and 64K bytes of byte-wide SRAM capacity
on-board.

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the iAPX 86/10 architecture and data
set. Over 60 numeric instructions offer arithmetic,
trigonometric, transcendental, logarithmic and exponential instructions. Supported data types include
16-, 32-, and 64-bit integer, and 32- and 64-bit floating point, 18-digit packed BCD and 80-bit temporary.

Parallel 1/0 Interface
The iSBC 86/05A Single Board Computer contains
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table
1. In order to take advantage of the large number of
possible 110 configurations, sockets are provided for
interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable 110 lines and signal ground lines are
brought out to a 50-pin edge connector.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential inst}uctions and can reduce the 740 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programmfngconstructs needed for asynchronous realtime systems. The. memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, ex. tra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses·.
Each register maps 64K bytes at a time with activation of a specific register controlled explicity by program control and selected implicity by specific functions and instructions. All Intel languages support
the extended memory capability, relieving the programmer of managing the megabyte memory space
yet allowing explicit control when necessary.

Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86j05A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(i.e., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
3-36

infef

iSBC® 86/05A SINGLE BOARD COMPUTER

8K BYTES RAM
(ISBC· 302)
I
I ________
(4x2168)
L.
.1,

I
I

ISB· 337A

NUD'i~~IC

I
I

PROCESSOR

L. __ ..l8~~L __ .J

MULTI BUS· SYSTEM BUS·

143325-2

Figure 1. iSBC® 86/05A Block Diagram
or to count external events. The third interval timer
in the 8254 provides the programmable baud rate
generator for the iSBC 86/05A board RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

incorporated in the USART. The RS232C compatible interface in conjunction· with the USART, provides a direct interface to RS232C compatible terminals, cassettes, and asynchronous/synchronous
modems. The RS232C command lines,· serial data
lines and signal ground line are brought out to a 26pin edge connector.
.

Programmable Timers
iSBXTM MULTIMODULETM On-Board
Expansion

The iSBC 86/05A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Inter.val Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer

Two 8/16-bit iSBX MULTlMODULE connectors are
provided on the iSBC 86/05A microcomputer.
Through these connectors, additional on-board lID
and memory functions may be added. iSBX MULTIMODULE boards support functions such as additional parallel and serial I/O, analog lID, mass storage
device controllers (e.g., cassettes and floppy disks),
BITBUSTM controllers, bubble memory, and other
custom interfaces to meet specific needs. By mounting directly on the single board computer, less inter3-37

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input

Output

Control
Bidirectional

Latched

Latched
& Strobed

'Latched

Latcched
& Strobed

2
3

4
4

NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When Terminal Count is Reached, an Interrupt Request is Generated. This Function
is Extremely Useful for Generation of Real-Time Clocks.

Programmable
One-Shot

Output Goes Low upon Receipt of an External Trigger Edge or Software Command
and Returns High when Terminal Count is Reached. This Function is Retriggerable.

Rate Generator

Divide by N Counter. The Output will go Low for One Input Clock Cycle, and the
Period from One Low GOing Pulse to the Next is N Times the Input Clock Period.

Square-Wave
Rate Generator

Output will Remain High Until One-Half the Count has been Completed, and go Low
for the Other Half of the Count.

Software
Triggered Strobe

Output Remains High Until Software Loads Count (N). N Counts After Count is
Loaded, Output goes Low for One Input Clock Period.

Hardware
Triggered Strobe

Output Goes Low for One Clock Period N Counts After Rising Edge Counter Trigger
Input. The Counter is Retriggerable.

Event Counter

On a Jumper Selectable Basis, the Clock Input Becomes an Input from the External
System. CPU may Read the Number of Events Occurring After the Counter
"Window" has been Enabled or an Interrupt may be Generated After N Events Occur
in the System.

face logic, less power, simpler packaging, higher
performance, and lower cost result when compared
to other alternatives such as MULTIBUS form factor
compatible boards. The iSBX connectors on the
iSBC 86/05A board provide all signals necessary to.
interface to the local on-board bus, including 16 data
lines for maximum data transfer rates. iSBX MULTIMODULE boards designed with 8-bit data paths and

3-38

using the 8-bit iSBX connector are also supported
on the iSBC 86/05A microcomputer. A broad range
of iSBX MULTIMODULE options are available in this
family from Intel. Custom iSBX modules may also be
designed for use on the iSBC' 86/05A board. An
iSBX bus interface specification is available from Intel.

inter

iSBC® a6/0SA SINGLE BOARD COMPUTER

MULTIBUS SYSTEM BUS AND
MULTIMASTER CAPABILITIES

Interrupt Capability
The iSBC 86/05A board provides 9 vectored interrupt levels. The highest level is the NMI (Non-Maskable Interrupt) line which is directly tied to the 8086
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the. next eight interrupt levels. As shown in Table 3, a selection of four
priority processing modes is available for use in designing request processing configurations to match
system requirements for efficient interrupt servicing
with minimal latencies. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts interrupt requests from all on-board I/O
resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

Overview
The MULTIBUS system bus (IEEE 796) is Intel's industry standard microcomputer bus structure. Both
8- and 16-bit single board computers are supported
on the MULTlBUS structure with 24 address and 16
data lines. In its simplest application, the MULTIBUS
system bus allows expansion of functions already
contained on a single board computer (e.g., memory
and digital I/O). However, the MULTIBUS structure
also allows very powerful distributed processing
configurations with multiple processors and intelligent slave I/O, and peripheral boards capable of
solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with
a broad array of board level products, LSI interface
components, detailed published specifications and
application notes.

Expansion Capabilities.
Memory and I/O capacity maybe expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expanded by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. Input/output capacity may be added with digital I/O
and analog I/O expansion boards. Mass storage capability may be achieved by adding single or double
density diskette controllers, or hard disk controllers.

Interrupt Request Generation
Interrupt requests to be serviced by the iSBC
86/05A board may originate from 24 sources. Table
4 includes a list of devices and functions supported
by interrupts. All interrupt signals are brought to the
interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 86/05A board provides full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 86/05A boards or other bus
masters to share the system bus using a serial (daisy chain) priority scheme and allows up to 16 masters to share the MULTIBUS system bus with an external parallel priority decoder. In addition to the multiprocessing configurations made possible with multimaster capability, it also provides a very efficient
mechanism for all forms of DMA (Direct Memory Access) transfers.

Power-Fail Control and Auxiliary
Power
Control logic is also included, to accept a power-fail
interrupt in conjunction with a power-supply having
AC-Iow signal generation capabilities, to initiate an
orderly shut down of the system in the event of a
power failure. Additionally, an active-low TIL compatible memory protect signal is brought out on the
auxiliary connector which, when asserted, disables
read/write access to RAM for systems requiring bat. tery backup of read/write memory. Selection of this
auxiliary RAM power bus is made via jumpers on the
board.

3-39

intJ

ISBC~

86/05A SINGLE BOARD COMPUTER

Table 3. Programmable Interrupt Modes
Mode
Fully Nested
Auto-Rotating
Specific
Priority
Polled

Operation
Interrupt Request Line Priorities Fixed at 0 as Highest, 7 as Lowest.
Equal Priority. Each Level, After Receiving Service, Becomes the Lowest Priority
Level until next Interrupt Occurs.
System Software Assigns Lowest Priority Level. Priority of all Other Levels Based in
Sequence Numerically on this Assignment.
System Software Examines Priority-Encoded System InterrLipt Status via Interrupt
Status Register.
Table 4. Interrupt Request Sources

Device
MULTIBUS Bus Interface

8255A Programmable
Peripheral Interface
8251AUSART
8254 Timers
iSBX Connectors
Bus Fail Safe Timer

Power Fail Interrupt
Power Line Clock
External Interrupt
iSBC 337A MULTIMODULE
Numeric Data Processor

Number of
Interrupts
8; may be Expanded to 64
Requests from MULTIBUS Resident
Peripherals or Other CPU Boards
with Slave 8259A PICs on
MULTIBUS Boards
Signals Input Buffer Full or Output Buffer Empty;
3
also BUS INTR OUT General Purpose Interrupt
from Driver/Terminator Sockets
2
Transmit Buffer Empty and Receive Buffer Full
Timer 0, 1 Outputs; Function Determined by
2
Timer Mode
Function Determined by iSBX MULTIMODULE
4
(2 per iSBX Connector)
Board
Indicates Addressed MULTIBUS Resident
1
Device has not Responded to Command within
6-10ms
1
Indicates AC Power is not within Tolerance
Source of 120 Hz Signal from Power Supply
1
General Purpose Interrupt from Auxiliary (P2)
1
Connector on Backplane
1
Indicates Error or Exception Condition
Function

3-40

iSBC® 86/05A SINGLE BOARD COMPUTER

System Development Environment
Development support for the iSBC 86/05A Board is
offered on the System 310 and Series IV Microcomputer Development System from Intel as well as the
IBM Personal Computer.
In the Series IV, System 310 and IBM PC development environments, languages offered are Assembler, PLM-86, C, Fortran and Pascal. A powerful software debugger, PSCOPE, is also offered on all
development systems. PSCOPE provides Software
Trace Execution, defineable breakpoints and user
defined/executable debugging procedures.

ing many different real-time applications. Key iRMX
86 operating system features include multitasking,
multiprogramming, interrupt management, device indepflndence, file protection and control, interactive
debugging, plus interfaces to many Intel and non-Intel developed hardware and software products.
The iRMX 86 operating system is highly modular and
configurable, and includes a sophisticated file management, I/O system, and powerful human interface. The iRMX 86 operating system is also easily
customized and extended by the user to match
unique requirements.

SPECIFICATIONS
In-Circuit Emulator

Word Size

The 12 1CETM In-Circuit Emulator provides the necessary link between the software development environment and the "target" iSBC 86/05A board, the
12 1CE In-Circuit Emulator provides a sophisticated
command set to assist in debugging software and
final integration of the user hardware and software.

Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits
System Clock

5.00 MHz or 8.00 MHz ± 0.1 % (jumper selectable)

iSDMTM System Debug Monitor

Basic Instruction Cycle

The Intel iSDM System Debug Monitor package contains the necessary hardware, software, cables,
EPROMs and documentation required to interface,
through a serial or parallel connection, an iSBC
86/05A target system to System 310 or Series IV
Intellec® Microcomputer Development System for
execution and interactive debugging of applications
software on the target system. The Monitor can:
load programs into the target system; execute the
programs instruction by instruction or at full speed;
set breakpoints; and examine/modify CPU registers,
memory content, and other crucial environmental
details. Additional custom commands can be built
using the Command Extension Interface (CEI).

At 8 MHz: 750 ns
250 ns (assumes instruction in the
queue)
At 5 MHz: 1.2 sec.
400 ns (assumes instruction in the queue)
NOTE:

Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles).

Memory Cycle Time
500 ns cycle time (no wait states requires a memory
component access time of 250 ns or less)
RAM: 500 ns
EPROM: Jumper selectable from 500 ns to 875 ns

Software Support
The iRMX 86 operating system is offered for development with a System 310 and provides users with a
powerful set of system building blocks for develop-

3-41

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

Memory Capacity/Addressing

Baud Rates

JEDEC 24/28 Pin Sites
Device

Total Capacity

Baud Rate (Hz)
Frequency (KHz)
(Software
Synchronous Asynchronous
Selectable)

Address Range

2K x 8
4K X 8
8K X 8
16K X 8
32K X 8
64K x 8

8K bytes
16K bytes
32K bytes
64K bytes
128K bytes
256K bytes

Device

Total Capacity

Address Range

2K x 8
4K x 8
8K x 8
16K x 8
32K X 8
64K x 8

16K bytes
32K bytes
64K bytes
128K bytes
256K bytes
512K bytes

FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH
80000-FFFFFH

FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH
With iSBC® 341 MULTIMODULETM
EPROM/SRAM

+16
9600
4800
2400
1200
600
300
150
110

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

+64
2400
1200
600
300
150
75

NOTE:
1. Frequency selected by 1/0 write of appropriate 16-bit
frequency factor to baud rate register (8254 Timer 2).

TIMERS

NOTE:
iSBC 86/05A EPROM sockets support JEDEC 24/28-pin
standard EPROMs and RAMS.

Input Frequencies

ON-BOARD STATIC RAM

Reference: 2.46 MHz ±0.1 % (0.041 sec. period,
nominal); or 153.60 KHz ± 0.1 %
(6.51 sec. period, nominal)

8K bytes -

0-1 FFFH

NOTE:
Above frequencies are user selectable

16K bytes- 0-3FFFH (with iSBC 302 MULTIMODULE Board)

Event Rate: 2.46 MHz max

1/0 CAPACITY
PARALLEL
SERIAL

Output Frequencies/Timing Intervals

24 programmable lines using one 8255A.

Function

1 programmable line using
one 8251A.

iSBX MULTIMODULE- 2
iSBX
single
wide
MULTIMODULE board or 1
iSBX double-width MULTIMODULE board.

SERIAL COMMUNICATIONS
CHARACTERISTICS
SYNCHRONOUS -

5-8 bit characters; internal or
external character synchronization; automatic sync insertion.

3-42

Dual
Timer/Counter
(Two Timers
Cascaded)

Min

Max

Min

Max

Real-Time
Intempt

1.63,.8

427.1 m8

3.268

466.50
min

Programmable
One-Shot

1.63,.8

427.1 m8

3.268

466.50
min

Rate Generator

2.342 Hz

613.5 kHz

306.8 kHz

Square-Wave
Rate Generator

2.342 Hz

613.5 kHz

0.000036
Hz
0.000036
Hz

Software
Triggered Strobe

1.63,.8

427.1 m8

3.26s

466.50
min

Hardware
Triggered Strobe

1.63,.8

427.1 ms

3.26s

466.50
min

Event·
Counter

ASYNCHRONOUS- 5-8 bit characters; break
character generation; 1, 1%,
or 2 stop bits; false start bit direction.

Single
Timer/Counter

2.46 MHz

306.8 kHz

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

INTERFACES

I/O Terminators

MULTIBUS Bus:

All signals TIL compatible

iSBX BUS Bus:

All signals TIL compatible

220/330 divider or 1K pullup
2200/3300

__ i _________________ _

PARALLEL 1/0:

All signals TIL compatible
SERIAL 1/0:
RS232C
compatible,
configurable as a data
set or data terminal
TIMER:
All signals TIL compatible
INTERRUPT REQUESTS: All TIL compatible

Centers
(In.)

Mating
Connectors

0.156

Viking
Wire Wrap

iSBX Bus
8-Bit Data
16-Bit Data
Parallel 1/0
(2)

36
44
50

0.1
0.1

iSBX 960-5
iSBX 961-5
3M Flat
or
T1 PINS

Serial 1/0

0.1

Interface
MULTIBUS
System

1kO

143325-3

MULTIBUS® DRIVERS
Characteristic

Sink Current (mA)

Tri-State
Tri-State
Tri-State
Open Collector

50
50
32
20

Physical Characteristics
Width:

0.1

1kO
+5V~

Function
Data
Address
Commands
Bus Control

Connectors
DoubleSided
Pins
(qty)

2200

+5V----'\~

12.00 in. (30.48 cm)

Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 14 oz (388 gm)

ELECTRICAL CHARACTERISTICS

3M Flat
or
AMP Flat

DC Power Requirements
LINE DRIVERS AND TERMINATORS

Configuration

I/O Drivers

Without EPROM(l)
RAM only(2)

The following line drivers are all compatible with the
1/0 driver sockets on the iSBC 86/05A board.

With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

Driver
7438
7437
7432
7426
7409
7408
7403
7400-

Characteristic
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Sink Current (rnA)
48
48
16
16
.16
16
16
16

Current Requirements
(All Voltages ±5%)
-,12V
+5V
+12V
4.7A
120 rnA
5.0A

25 rnA

23 rnA

25 rnA

23 rnA

4.9A

25 rnA

23 rnA

4.9A

25 rnA

23 rnA

NOTES:
1. Does not include power for optional ROM/EPROM, I/O,
drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

NOTES:
I = inverting; NI = non-inverting; OC = open collector.

Port 1 of the 8255A has 20 rnA totem-pole bidirectional drivers and 1K terminators
3-43

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

Manuals may be ordered from any Intel sales repre·
sentative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ENVIRONMENTAL
CHARACTERISTICS
Operating Temperature: O°C to 55°C
Relative Humidity: to 90% (without condensation)

ORDER INFORMATION
REFERENCE MANUAL

,Part Number

Description

SBC 86/05A

16-bit Single Board Computer with
8K bytes RAM

Order no. 147162-002-iSBC 86/05A Hardware
Reference Manual (NOT SUPPLIED)

3·44

iSBC® 86/14 AND iSBC® 86/30
SINGLE BOARD COMPUTERS
8086 Microprocessor with 5 or 8 MHz
• CPU
Clock
Fully Software Compatible with iSBC®
• 86/12A
Single Board Computer
Optional 8086 Numeric Data Processor
• with
iSBC® 337A MULTIMODULETM
Processor
bytes of Dual-Port Read/
• 32K/128K
Write Memory Expandable On-Board to

Programmable Synchronous/
• Asynchronous
RS232C Compatible
Serial Interface. with Software
Selectable Baud Rates
Programmable 16-Bit BCD or
• Two
Binary Timers/Event Counters
Levels of Vectored Interrupt Control,
• 9Expandable
to 65 Levels
MULTIBUS® Interface for Multimaster
• Configurations
and System Expansion
by a Complete Family of
• Supported
Single Board Computers, Memory,

256K bytes wjth On-Board Refresh
for up to 64K bytes of JEDEC
• Sockets
24/28-pin Standard Memory Devices
iSBXTM Bus Connectors
• Two
• 24 Programmable Parallel I/O Lines

Digital and Analog I/O, Peripheral
Controllers, Packaging and Software

The iSBC 86/14 and iSBC 86/30 Single Board Computers are members of Intel's complete line of OEM
microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained,
computer-based solutions for OEM applications. Each board is a complete computer systemon a single 6.75 x
12.00-in. printed circuit card distinguished by RAM memory content with 32K bytes and 12BK bytes provided
on the iSBC 86/14 and iSBC B6/30 board, respectively. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O ports and drivers, serial communications interface, priority interrupt logic and
programmable timers, all reside on the boards.

280007-1

3-45

September 1987
Order Number: 280007-004

intJ

iSBC® 86114 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the 8086/10 architecture and data set.
Over 60 numeric instructions offer arithmetic, trigonometric, transcendental, logarithmic and exponential instructions. Supported data types include 16-,
32, and 64-bit integer, and 32- and 64-bit floating
point, 18-digit packed BCD and 80-bit temporary.

FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processor for the iSBC 86/XX' boards is
Intel's iAPX 86/10 (8086-2) CPU. A clock rate of 8
MHz is supported with a jumper selectable option of
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit memory
base pointer registers and two 16-bit index registers,
all accessed by a total of 24 operand addressing
modes for comprehensive memory addressing and
for support of the data structures required for today's structured, high level languages as well as assembly language.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce. the 750 nsec
minimum instruction cycle to 250 nsec for queued
instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used. to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time .and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

NOTE:
iSBC 86/XX designates both the iSBC 86/14 and
iSBC 86/30 CPU boards.

280007-2

Figure 1. iSBC® 86/XX Block Diagram
3-46

inter

iSBC® 86/14 AND iSBC@ 86/30 SINGLE BOARD COMPUTERS

RAM Capabilities

Parallel 110 Interface

The iSBC 86/14 and iSBC 86/30 microcomputers
contain 32K bytes and 128K bytes of dual-port dynamic RAM, respectively. In addition, on-board RAM
may be doubled on each microcomputer by optionally adding RAM MULTIMODULE boards. The onboard RAM may be expanded to 256K bytes with
the iSBC 304 MULTIMODULE Board mounted onto
the iSBC 86/30 board. Likewise, the iSBC 86/14 microcomputer may be expanded to 64K bytes with
the iSBC 300A MULTIMODULE option. The dualport controller allows access to the on-board RAM
(including RAM MULTIMODULE options) from the
iSBC 86/XX boards and from any other MULTIBUS
master via the system bus. Segments of on-board
RAM may be configured as a private resourc'e, protected from MULTIBUS system access. The amount
" of memory allocated as a private resource may be
configured in increments of 25% of the total onboard memory ranging from 0% to 100% (optional
RAM MULTIMODULE boards double the increment
size). These features allow the multiprocessor systems to establish local memory for each processor
and shared system memory configurations where
the total system memory size (including local onboard memory) can exceed one megabyte without
addreSSing conflicts.

The iSBC B6/XX Single Board Computers contain
24 programmable parallel 110 lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
1/0 lines in any combination of unidirectional input!
output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible 1/0 configurations, sockets are provided for interchangeable 1/0 line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drivel termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Serial 110
A programmable communications interface using
the Intel 8251A Universal Synchronousl Asynchronous Receiver/Transmitter (USART) is contained on
the iSSC 86/XX boards. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

EPROM Capabilities
Four 28-pin sockets are provided for the use of Intel
2716s, 2732As, 2764s, 27128s, and their respective
ROMs. When using 27128s, the on-board EPROM
capacity is 64K bytes. Other JEDEC standard pinout
devices are also supported, including byte-wide static RAMs.

Programmable Timers
The iSBC B6/XX boards provide three independent,
fully programmable 16-bit interval .timersl event
counters utilizing the Intel 8253 Programmable In-

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(Qty)

Input
Latched

2
3

8
8
4
4

X
X
X
X

Output

Latched &
Strobed
X
X

Latched
X
X
X
X

Latched &
Strobed
X
X

Bidirectional

Control

X
X(1)
X(1)

3-47

inter

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

terval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 86/XX boards' RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

iSBXTM MULTIMODULETM On-Board
Expansion
Two 8/16-bit iSBX MULTIMODULE connectors are
provided on the iSBC 86/XX microcomputers.
Through these connectors, additional on-board I/O
functions may be added. iSBX MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial I/O, analog I/O, small mass storage device controllers (e.g., cassettes and floppy disks),
and other custom interfaces to meet specific needs.
By mounting directly on the single board computer,
less interface logic, less power, simpler packaging,
higher performance, and lower cost result when
compared to other alternatives such as MULTIBUS
form factor compatible boards. The iSBX connectors
on the iSBC 86/XX boards provide all signals necessary to interface to the local on-board bus, including
16 data lines for maximum data transfer rates. iSBX
MULTIMODULE boards designed with 8-bit data
paths and using the 8-bit iSBX connector are also
supported on the iSBC 86/XX microcomputers. A
broad range of iSBX MULTIMODULE options are
available in this family from Intel. Custom iSBX modules may also be designed for use on the iSBC 86/
XX boards. An iSBX bus interface specification and
iSBX connectors are available from Intel.

Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
When terminal count is reached,
Terminal Count an interrupt request is generated.
This function is extremely useful
for generation or real-time clocks.
Programmable
One-Shot

Rate
Generator

Output goes low upon receipt of
an internal trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.

MULTIBUS® SYSTEM BUS AND
MULTIMASTER CAPABILITIES

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low going pulse to the next is N
times the input clock period.

Overview
The MULTIBUS system bus is Intel's industry standard microcomputer bus structure. Both 8 and 16-bit
single board computers are supported on the MULTIBUS structure with 24 address and 16 data lines.
In its simplest application, the MULTIBUS system
bus allows expansion of functions already contained
on a single board computer (e.g., memory and digital
I/O). However, the MULTIBUS structure also allows
very powerful distributed processing configurations
with multiple processors and intelligent slave I/O,
and peripheral boards capable of solving the most
demanding microcomputer applications. TheMULTIBUS system bus is supported with a broad array of
board level products, LSI interface components, detailed published specifications and application notes.

Square-Wave
Output will remain high until oneRate Generator half the count has been
completed, and go low for the
other half of the count.
Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.

Event Counter

On a jumper selectable basis,the
clock input becomes an input
from the external system. CPU
may read the number of events
occurring after the counter
"window" has been enabled or
an interrupt may be generated
after N events occ\lr in the
system.

intJ

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

request processing configurations to match system
requirements for efficient interrupt servicing with
minimal. latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC
accepts interrupt requests from all on-board I/O resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

board EPROM capacity may be expanded to 128K
by user reprogramming of a PAL device to support
27256 EPROM devices. Input/output capacity may
be added with digital I/O and analog I/O expansion
boards. Mass storage capability may be achieved by
adding single or double density diskette controllers,
or hard disk controllers. Modular expandable backplanes and card cages are available to support multiboard systems.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 86/XX boards provide full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 86/XX boards or other bus masters,
including iSBC 80 family MUL TIBUS compatible 8-bit
single board computers to share the system bus using a serial (daisy chain) priority scheme and allows
up to 16 masters to share the MUL TIBUS system
bus with an external parallel priority decoder. In addition to the multiprocessing configurations made
possible with multi master capability, it also provides
a very efficient mechanism for all forms of DMA (Direct Memory Access) transfers.

Interrupt Request Generation
Interrupt rp.quests to be serviced by the iSBC 86/XX
boards may originate from 28 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Power-Fail Control and Auxiliary
Power

Interrupt Capability

Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 and iSBC 640 Power Supply or equivalent, to initiate an orderly shut down of the system in
the event of a power failure. Additionally, an activelow TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protectionof RAM contents during system power-down
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery back-up of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

The iSBC 86/XX boards provide 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8086 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides
control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four priority
processing modes is available for use in designing
Table 3. Programmable Interrupt Modes
Mode

Operation
Fully Nested Interrupt request line priorities fixed
at 0 as highest, 7 as lowest.

Auto-Rotating Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
Specific
Priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.

Polled

System software examines priorityencoded system interrupt status via
interrupt status register.

System Development Capabilities
The development cycle of iSBC 86/XX products can
be significantly reduced and simplified by using either the System 86/310 or the Intellec Series IV Microcomputer Development System or the IBM PC.

3-49

infef

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

SPECIFICATIONS

IN-CIRCUIT EMULATOR
The 121CE In-Circuit Emulator provides the .necessary link between the software development environment and the "target" iSBC 86/XX execution
system. In addition to providing the mechanism for
loading executable code and data into the iSBC 86/
XX boards, the 12 1CE In-Ci~cuit Emulator provides a
sophisticated command set to assist in debugging
software and final integration of the user hardware
and software.

Word Size
Instruction: 8,16, 24, or 32 bits
Data: 8, 16 bits

System Clock
5.00 MHz or 8.00 MHz ± 0.1 % Oumper selectable)

PL/M·86
Cycle Time

Intel's system's implementation language, PVM-86,
is standard in the System 86/310 and is also available for the Series IV and the IBM PC. PL/M-86 provides the capability to program in algorithmic language and eliminates the need to manage register
usage or allocate memory while still allowing explicit
control of the system's resources when needed.
FORTRAN 86, PASCAL 86 and C86 are also available the Inte"ec Series IV, 86/310 systems and the
IBM PC.·

Table 4.
Device

BASIC INSTRUCTION CYCLE
8 MHz: 750 ns
250 ns(assumes instruction in the queue) .
5 MHz: 1.2 JLs
400 ns (assumes instruction in the queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

~nterrupt

Request Sources

Function

Number of
Interrupts

MULTIBUS Interface

Requests from MULTIBUS resident peripherals or other 8; may be Expanded to
CPU boards.
64 with Slave 8259A
PICs on MULTIBUS
Boards

8255A· Programmable
Peripheral Interface

Signals input buffer full or output buffer empty; also BUS
tNTR OUT general purpose interrupt from driver/
terminator sockets.

8251A USART .

Transmit buffer empty and receive buffer full.

8253 Timers

Timer 0, 1 outputs; function determined by timer mode.

iSBX Connectors

Function determined by iSBX MULTIMODULE board.

Bus Fail Safe Timer

Indicates addressed MULTIBUS resident device has not
responded to command within 6 ms.

4
(2 per iSBX Connector)
1

Power Fail Interrupt

Indicates AC power is not within tolerance.

Power Line ClOCk

Source of 120 Hz signal from power supply..

External Interrupt

General purpose interrupt from auxiliary (P2) connector
on backplane.

iSBC 337 A MULTIMODULE Indicates error or exception condition.
Numeric Data Processor

Parity Error

Indicates on-board RAM parity error from iSBC 303
parity MULTIMODULE board (iSBC 86/14 option).

Edge-Level Conversion

Converts edge triggered interrupt request to level
interrupt.

OR-Gate Matrix

Outputs of OR-gates on-board for multiple interrupts.

3-50

inter

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

Memory Cycle Time
RAM:

Serial Communications
Characteristics

750 ns

EPROM: Jumper selectable from 500 ns to 875 ns

Synchronous: 5-8 bits characters; internal or external character synchronization; automatic sync insertion

Memory CapacityI Addressing

Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit direction

ON-BOARD EPROM
Device
2716
2732A
2764
27128

Total Capacity
81< bytes
16K bytes
32K bytes
64K bytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

BAUD RATES
Frequency (kHz)
Baud Rate (Hz)
(Software
Selectable
Synchronous Asynchronous
.;.-16
.;.-64
9600
2400
153.6
1200
76.8
4800
38400
2400
600
38.4
19200
1200
300
19.2
9.6
9600
600
150
4800
300
75
4.8
2.4
2400
150
1.76
1760
110
-

NOTE:
iSSC 86/XX EPROM sockets support JEDEC 24/
28-pin standard EPROMs and RAMs. Total EPROM
capacity may be increased to 128 bytes by the user
reprogramming an on-board PAL.

ON-BOARD RAM
Board
iSSC 86/14
iSSC 86/30

Total Capacity
32K bytes
128K bytes

Address Range
0-07FFFH
0-1 FFFFH

NOTE:
Frequency selected by I/O write of appropriate 16·bit fre·
quency factor to baud rate register (8253 Timer 2).

WITH MULTIMODULETM RAM
Total Capacity Address Range
Board
64K bytes
iSSC300A
O-OFFFFH
(with iSSC 86/14)
256K bytes
iSSC304
0-3FFFFH
(with iSSC 86/30)

Timers
INPUT FREQUENCIES
Reference: 2.46 MHz ± 0.1 % (0.041 J.tsec period,
nominal); or 153.60 kHz ± 0.1 % (6.51 J.tsec period,
nominal)

I/O Capacity
Parallel: 24 programmable lines using one 8255A

NOTE:
Above frequencies are user selectable.

Serial: 1 programmable line using one 8251A
iSSX MULTIMODULE: 2 iSSX boards

Event Rate: 2.46 MHz max

OUTPUT FREQUENCIES/TIMING INTERVALS

Function

Single
Timer/Counter
Min

Dual
Timer/counter
(Cascaded)

Max

Min

Max
466.50 min
466.50 min

Real·Time Interrupt

1.63J.ts

427.1 ms

3.26s

Programmable One·Shot

1.63 J.ts

427.1 ms

3.26s

Rate Generator

2.342 Hz 613.5 kHz 0.000036 Hz

306.8 kHz

Square·Wave Rate Generator 2.342 Hz 613.5 kHz 0.000036 Hz

306.8 kHz

Software Triggered Strobe

1.63J.ts

Hardware Triggered Strobe

1.63 J.ts

Event Counter

3-51

427.1 ms

3.26s

466.50 min

427.1 ms

3.26s

466.50 min

2.46 MHz

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

Port 1 of the 8255A has 20 mA totem·pole bidirectional drivers and 1 KO terminators

Interfaces
MULTIBUS: All Signals TTL compatible
iSBX Bus: All signals TTL compatible

I/O TERMINATORS

Parallel I/O: All signals TTL compatible

2200/3300 divider or 1 kO pullup

Serial I/O: RS232C compatible, configurable as a
data set or data terminal
Timer: All signals TTL compatible
Interrupt Requests: All TTL compatible

220DJ330n
2200

+5V

Connectors
Interface

DoubleCenters
Sided
(in.)
Pins

----~'II3!""DO----,

__ fr_-_-_-_~__________~ __ _
Mating
Connectors

MUILTIBUS
System

0.156

iSBXBus
8·Bit Data

0.1

iSBX 960·5

Parallel 110
(2)

0.1

3M 3415·000 Flat
or
TI H312125 Pins

Serial I/O

0.1

3M 3462-0001
Flat or
AMP 88106-1 Flat

1 kG

lK{l

+5V - - - " ' ' ' ' ' ' " ' ' ' - - - - - - 0

280007-3

Viking
3KH43/9AMK12
Wire Wrap

MULTIBUS® Drivers
Function
Data
Address
Commands
Bus Control

Characteristic
Tri·State
Tri·State
Tri-State
Open Collector

Sink Current (mA)
32
32
32
20

Physical Characteristics
Line Drivers and Terminators

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 14 oz (388 gm)

I/O DRIVERS
The following line drivers are all compatible with the
I/O driver sockets on the iSBC 86/05 board
Driver
Characteristics
Sink Current (rnA)
7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Environmental Chara~teristics

48
48
16
16
16
16
16
16

Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

NOTE:
I = inverting; N I = non·inverting; OC = open collector.

3-52

iSBC@ 86/14 AND ISBC@ 86/30 SINGLE BOARD COMPUTERS

Electrical Characteristics

Environmental Characteristics
Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

DC POWER REQUIREMENTS
Current Requirements
(All Voltages ±50/0)
Configuration
Without EPROM1
RAM only2
With 8K EPROM3
(using 2716)
With 16K EPROM3
(using 2732A)
With 32K EPROM3
(using 2764)

+5V

+12V

-12V

Reference Manual

5.1A
600mA
5.4A

25mA

23mA

25mA

23mA

144044-002: iSBC 86/14 and iSBC 86/30 Hardware
Reference Manual (NOT SUPPLIED)

5.5A

25mA

23mA

5.6A

25mA

23mA

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

NOTES:
1. Does not include power for optional ROM/EPROM, 1/0
drivers, and 1/0 terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 1/0 lines; all terminator inputs l o w . ·
.

ORDERING INFORMATION
Part Number Description
SBC 86/14
Single Board Computer
SBC 86/30
Single Board Computer

3-53

iSBC® 86/35
SINGLE BOARD COMPUTER

•
•

Optional 8086 Numeric. Data Processor
with iSBC® 337A MULTIMODULETM
Processor

Upward Compatible with iSBC 86/30
• Single
Board Computer

•
•
•
•

Programmable Synchronous/
• Asynchronous
RS232C Compatible

8086 (8086-2) Microprocessor with 5 or
8 MHz CPU Clock

512K Bytes of Dual-Port Read/Write
Memory Expandable On-Board to 640K
or 1M Bytes
Sockets for up to 128K Bytes of JEDEC
24/28-Pin Standard Memory Devices

Serial Interface with Software
Selectable Baud Rates

•
•
•
•

Two iSBXTM Bus Connectors

Three Programmable 16-Bit BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable Off Board to 65 Levels
MULTIBUS® Interface for Multimaster
Configurations and System Expansion
Supported by a Complete Family of
Single BOard Computers, Memory,
Digital and Analog 1/0, Peripheral
Controllers, Packaging and Software

24 Programmable Parallel I/O Lines

The iSBC 86/35 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
that take full advantage of Intel's technology to provide economical, self~contained, computer-based solutions
for OEM applications. The board is a complete computer system containing the CPU, system clock, dual port
read/write memory, nonvolatile read only memory, I/O ports and drivers, serial communications interface,
priority interrupt logic and programmable timers, all on a single 6.75 x 12.00 in. printed circuit card. The iSBC
86/35 board is distinguished by its large RAM content of 512K bytes which is expandable on-board to 1
megabyte; the direct addressing capability of the 8086-2 CPU. The large, on-board memory resource combined with the 8086 microprocessor provides high-level system performance ideal for applications, such as
robotics, process control, medical instrumentation, office systems, and business data processing.

210219-1

3-54

September 1987
Order Number: 210219-004

inter

iSBC® 86/35 SINGLE BOARD COMPUTER

registers, all accessed by a total of 24 operand addressing modes for comprehensive memory addressing and for support of the data structures required for today's structured, high level languages
as well as assembly language.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 86/35 board combines the power of the
industry standard 8086 CPU with up to a megabyte
page of board resident, dual ported system memory
to improve the system's overall performance. By
placing the direct memory addressing capability of
the iAPX 86/10 CPU on board, MULTIBUS® access
to system memory can be eliminated, significantly
improving system throughput. Intel's incorporation of
256K bit DRAM technology, parallel and serial 110,
iSBXTM connectors, and interrupt control capabilities
make this high performance single board computer
system a reality.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.
For enhanced 5 or 8 MHz numerics processingcapability, the iSBC 337A MULTIMODULE NUmeric
Data Processor extends the iAPX 86/10 architecture
and data set. Over 60 numeric instructions offer
arithmetic, trigonometric, transcendental, logarithmic
and exponential instructions. Supported data types
include 16-, 32-, and 64-bit integer, and 32- and 64bit floating pOint, 18-digit packed BCD and 80-bit
temporary.

Central Processing Unit
The central processor for the iSBC 86/35 board is
Intel's iAPX 86/10 (8086-2) CPU. A clock rate of 8
MHz is supported with a jumper selectable option for
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit index

,...-------~

I 1Z8KaiUSICl!) 304)

I S12KaS'ISBeS 3141

51ZK.80Slcl!laG/3SJ

NUL TIBUS@SYSTEM BUS

210219-2

Figure 1. iSBC® 86/35 Block Diagram

3-55

iSBC® 86/35 SINGLE BOARD COMPUTER

The dual-port controller allows access to the onboard RAM (including RAM MULTIMODULE board
options) from the iSBC 86/35 board and from any
other MULTIBUS master via the system bus. Segments of on-board RAM may be configured as a private resource; protected from MULTIBUS system
access.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture rea,dily
supports modular programming by facilitating fast,
simple, inter-modular communication, and other pro~
gramming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time and activation of a specific' register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

RAM Capabilities
The iSBC 8,6/35 microcomputer contains 512K
bytes of dual-port dynamic RAM which may be expanded on-board by adding a RAM Multimodule
board as an option. The on-board RAM may be expanded to 640K bytes with the iSBC 304 MULTIMODULE Doard mounted onto the iSBC 85/35
board. Likewise, the iSBC 86/35 microcomputer
may be expanded to 1 Megabyte with theiSBC 314
MULTIMODULE board option.

EPROM Capabilities
Four 28-pin JEDEC sockets are provided for the use
of Intel 2764, 27128, 27256, 27512, EPROMs and
their respective ROMs. When using 27512, the onboard EPROM capacity is 256K bytes. Other JEDEC
standard pinout devices are also supported, including byte-wide static RAMs.

Parallel 110 Interface
The iSBC 86/35 Single Board Computer contains 24
programmable parallel I/O lines implemented using
the Intel 8255A Programmable Peripheral Interface.
The system software is used' to configure the I/O
, lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible I/O configurations, sockets are provided for interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the re.
quired drive/termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Port

Unidirectional

Lines
(qty)

Input

Control

Output

Latched

Latched &
Strobed

Latched

Bidirectional

Latched &
Strobed
-

3-56

iSBC® 86/35 SINGLE BOARD COMPUTER

Table 2. Programmable Timer Functions

Serial 1/0

Function

A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSSC 86/35 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

Operation

Interrupt on
When terminal count is reached,
terminal count an interrupt request is generated.
This function is extremely useful
for generation of real-time clocks.
Programmable Output goes low upon receipt of an
external trigger edge or software
one-shot
command and returns high when
terminal count is reached. This
function is retriggerable.
Rate
generator

Programmable Timers

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one low
going pulse to the next is N times
the input clock period.

Square-wave Output will remain high until onerate generator half the count has been
completed, and go low for the
other half of the count.

The iSSC 86/35 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either SCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate timer intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSSC 86/35 board's RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

iSBXTM MULTIMODULETM On-Board
Expansion
Two 8/16-bit iSSX MULTIMODULE connectors are
provided on the iSSC 86/35 microcomputer.
Through these connectors, additional on-board I/O
functions may be added. iSSX MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial I/O, analog I/O, small mass storage device controllers (e.g., cassettes and floppy disks),

3-57

Software
triggered
strobe

Output remains high until software
loads count (N). N counts after
count is loaded, output goes low
for one input clock period.

Hardware.
triggered
strobe

Output goes low for one clock
period N counts after riSing edge
counter trigger input. The counter
is retriggerable.

Event counter

On a jumper selectable basis, the
clock input becomes an input from
the external system. CPU may
read the number of events
occurring after the counter
"window" has been enabled or an
interrupt may be generated after N
events occur in the system.

iSBC® 86/35 SINGLE BOARD COMPUTER

and other custom interfaces to meet specific needs.
By mounting directly on the single board computer,
less interface logic, less power, simpler packaging,
higher performance, and lower cost result when
compared to other alternatives such as MULTIBUS
form factor compatible boards. The iSBX connectors
on the iSBC 86/35 board provides all signals necessary to interface to the local on-board bus, including
16 data lines for maximum data transfer rates. iSBX
MULTIMODULE boards designed .with 8-bit data
paths and using the 8-bit iSBX connector are also
supported on the iSBC 86/35 microcomputer. A
broad range of iSBX MULTIMODULE options are
available in this family from Intel. Custom iSBX modules may also be designed for use on the .iSBC 86/
35 board. An iSBX bus interface specification and
iSBK connectors are available from Intel.

both serial (daisy chain) and parallel priority
schemes. The serial scheme allows up to three iSBC
. 86/35 boards/bus masters to share the MULTIBUS
system bus; while up to 16 masters may be connected using the parallel scheme and external decode
logic.

Interrupt Capability
The iSBC 86/35 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8086-2
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four
priority processing modes is available for use in designing request processing configurations to match
system requirements for efficient interrupt servicing
with minimal latencies. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts interrupt requests from aU on-board I/O
resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

MULTIBUS® SYSTEM BUS
CAPABILITIES
Overview
The MULTIBUS system bus is Intel's industry standard (IEEE 796) microcomputer bus structure. Both
8- and 16-bit single board computers are supported
on the MULTIBUS structure with 24 address and 16
data lines. In its simplest application, the MULTIBUS
system bus allows. expansion of functions already
contained on a single board computer (e.g., memory
and digital I/O). However, the MULTIBUS structure
also allows very powerful distributed processing
configurations with multiple processors and intelligent slave I/O, and peripheral boards capable of
solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with
a broad array of board level products, LSI interface
components, detailed published specifications and
application notes. Please refer to the MULTIBUS
Handbook (order number 210883) for more detailed
information.

Table 3. Programmable Interrupt Masks
Mode

Fully nested

Operation

Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.
Auto-rotating Equal priority. Each level, after
receiving service, becomes the
. lowest priority level until next
interrupt occurs.
System software assigns lowest
Specific
priority level. Priority of all other
priority
levels based in sequence
numerically on this assignment.
Polled
System software examines priorityencoded system interrupt status
via interrupt status register.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.
several CPUs and/or controllers logically sharing
system tasks through communication on the system
bus), the iSBC 86/35 board provides full MULTIBUS
arbitration control logic. This control logic allows

3-58

infef

ISBC® 86/35 SINGLE BOARD COMPUTER

Interrupt Request Generation

Power-Fall Control and
Auxiliary Power

Interrupt requests to be serviced by the iSBC 86/35
board may originate from 28 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Control logic is included to accept a power-fail interrupt in conjunction with the AC-Iow signal from the
Power Supply to initiate an orderly shut down of the
system in the event of a power failure. Additionally,
an active-low TIL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system power-

Table 4. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS® interface

Requests from MULTIBUS® resident
peripherals or other CPU boards

8255A Programmable
Peripheral Interface

Signals input buffer full or output
buffer empty; also BUS INTR OUT
gener~1 purpose interrupt from
driver/terminator sockets

8251A USART

Transmit buffer empty and receive
buffer full

8253 Timers

Timer 0, 1 outputs; function determined by timer mode

iSBXTM connectors

Function determined by iSBXTM
MULTIMODULETM board

Bus fail safe timer

Indicates addressed MULTIBUS®
resident device has not responded
to command within 6 ms

Power fail interrupt

Indicates AC power is not within
tolerance

Power line clock

Source of 120 Hz signal from power
supply

External interrupt

General purpose interrupt from auxiliary (P2) connector on backplane

iSBC 337A MULTIMODULE
Numeric Data Processor

Indicates error or exception condition

Edge-level conversion

Converts edge triggered interrupt request to level interrupt

OR-gate matrix

Outputs of OR-gates on-board for
multiple interrupts

3-59

8; may be expanded to
64 with slave 8259A
PICs on MULTIBUS®
boards

4
(2 per iSBXTM connector)

intJ

iSBC® 86/35 SI.N(;LE BOARD COMPUTER

down sequences. An auxiliary power bus is also provided to allow separate· power to RAM for systems
requiring battery backup of read/write memory. Selection of this auxiliary RA~ powl'lr bus is made via
jumpers on the board.

SPECIFICATIONS
Word Size
INSTRUCTION :- 8, 16, 24, or 32 bits

System Development Capabilities·

DATA --.:. 8, 16 bits

The development cyc,le of iSBC 86/35 products can
be significantly reduced and simplified by using either the System 86/330' or the Intellec Series IV
Microcomputer Development System. '

System Clock

IN-CIRCUIT EMULATOR

Cycle Time

The 121CE In-Circuit Emulator provides the necessary link between the software development environment and the "target" iSBC 86/35 execution system. In addition ~o providing the mechanism for loading executable code and data into the iSBC 86/35
board the 121CE In-Circuit Emulator provides a sophisti~ated command set to assist in debugging soft~
ware and final integration of the user h~~dware and
software.

5 MHz or 8 MHz ±0.1 % Oumper selectable)

BASIC iNSTRUCTION CYCLE
·8 MHz ~ 250 ns (assumes instruction in the queue)
5 MHz -

400 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined. as the fastest instruction time (i.e., two clock cycles). Jumper. selectable for 1 wait-state on-board memory access.

Software Support·

Memory CapacityI Addressing

Real time support for the iSBC 86/35 board is provided by the iRMX 86 operating system. The iRMX
86 Operating System is a highly functional operating
system with a rich set of features and options based
on an object-oriented architecture. In addition to being modular and configurable, functions beyond the
nucleus include a sophisticated file management
and 110 system, and powerful human interface. Both
packages are easily customized and· extended by
the user to match unique requirements.

ON-BOARD EPROM

Device

Total Capacity

Address Range

2764
27128
27256
27512

32K bytes
64K bytes
128K bytes
256K bytes

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
,DOOOO-FFFFFH

ON-BOARD RAM

. Board

Interactive multi-user support is provided by the Xenix· operating system. Xenix is a compatible derivative of UNIX··, System III.

Total Capacity

iSBC 86/35512K bytes .

Address Range
0-7FFFFH

WITH MULTIMODULETM RAM

Language support for the iSBC 86/35 board in'cludes Intel's ASM 86, PL/M 86, and PASCAL, and
FORTRAN, as well as many third party 8086 languages. The iSDM monitor provides on-target, inter~
active system debug capability including breakpoint
and memory examination features. The monitor supports iSBC/iAPX 86,88, 186, and 188 based applications.
·Xenix is a trademark of Microsoft Corp.
··UNIX is a trademark of Bell Labs.

3-60

~oard

Total Capacity

Address Range

iSBC 304
iSBC 314

640K bytes
1M bytes

8-9 FFFFH
8""FFFFFH

iSBC® 86/35 SINGLE BOARD COMPUTER

I/O Capacity

OUTPUT FREQUENCIES/TIMING INTERVALS

PARALLEL-24 programmable lines using one
8255A.

Single
Timer/Counter

Function

Min

Max

1.63 J.ts 427.1 ms

3.26s

466.50 min

Programmable 1.63 J.ts 427.1 ms
one-shot

3.26s

466.50 min

SERIAL-1 programmable line using one 8251A.
Real-time
Interrupt

iSBXTM MULTIMODULETM-2 iSBX boards

Serial Communications Characteristics

Rate
generator

SYNCHRONOUS-5-8 bit characters; internal or
external character synchronization; automatic sync
insertion

2.342 Hz 613.5 kHz 0.000036 Hz 306.8 kHz

Square-wave 2.342 Hz 613.5 kHz 0.000036 Hz 306.8 kHz
rate generator

ASYNCHRONOUS-5-8 bit characters; break character generation; 1, 1%, or 2 stop bits; false start bit
detection
BAUD RATES

Frequency (kHz)
(Software
Selectable)

Max

Dual
Timer/Counter
(Cascaded)

Software
riggered
strobe

1.63 J.ts 427.1 ms

3.26s

466.50 min

Hardware
riggered
strobe

1.63 J.ts 427.1 ms

3.26s

466.50 min

Event
counter

Baud Rate (Hz)

2.46 MHz

Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9606
4800
2400
1760

Interfaces

""16 ""64
9600 2400
4800 1200
2400
600
1200
300
600
150
300
75
150
110

MULTIBUS®-AII signals TTL compatible
iSBXTM BUS-All signals TTL compatible
PARALLEL I/O-All signals TTL compatible
SERIAL I/O-RS232C compatible, configurable as
a data set or data terminal

NOTE:
Frequency selected by I/O write of appropriate 16-bit frequency factor to baud rate register (8253 Timer 2).

TIMER-All signals TTL compatible

Timers

Connectors

INTERRUPT REQUESTS-All TTL compatible

INPUT FREQUENCIES

DoubleSided
Pins

(In.)

0.156

36
44

0.1 .
0.1

Parallel I/O
(2)

0;1

3M 3415-000 Flat
or
TI H312125 Pins

Serial I/O

0.1

3M 3462-0001
Flat or
AMP 88106-1 Flat

Interface

Reference: 2.46 MHz ± 0.1 % (0.041 J.Ls period,
nominal); or 153.60 kHz ± 0.1 % (6.51 J.Ls period,
nominal)

MULTIBUS®
System

NOTE:
Above frequencies are user selectable.

iSBXTM Bus
8-Bit Data
16-BitData

Event Rate: 2.46 MHz max

3-61

Connec~ors

Viking
3KH43/9AMK12
Wire Wrap
Viking
000292-0001
000293-0001

iSBC® 86/35 SINGLE BOARD COMPUTER

Line Drivers and Terminators

Electrical Characteristics

I/O DRIVERS-The following line drivers are all
compatible with the I/O driver sockets on the iSBC
86/05 board

DC POWER REQUIREMENTS

Driver

Characteristic

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC·
I

48
48
16
16
16
16
16
16

Current Requirements
(All Voltages ±5%)

Configuration
Without EPROM(1)

Port 1 of the 8255A has 20 mA totem-pole bi-directional drives and 1 kO temrinators

+12V

-12V

5.1A

25mA

23mA

660mA

With 32K EPROM(3)
(using 2764)

5.6A

25mA

23mA

With 64K EPROM
(using 27128)

5.7A

25mA

23mA

With 128K EPROM
(using 27256)

5.8A

25mA

23mA

RAM only(2)

NOTE:
I = inverting; NI = non-inverting; DC = open collector.

+5V

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers. and I/O terminators.
.
2. RAM chips powered via auxiliary power bus in power..
down mode.
3. Includes power required for 4 ROM/EPROM chips. and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

I/O TERMINATORS-2200/3300 divider or1 kO
pullup
(OPTION 1)
2200/3300

Environmental Characteristics
OPERATING TEMPERATURE - O°C to 55°C
200 linear feet per minute (LFM) air velocity

210219-3

RELATIVE HUMIDITY sation)

(OPTION 2)

to 90% (without conden-

1 kO

Reference Manual

1kll

+5V-----"VV\.,--------o.

146245-002 - iSBC 86/35 Hardware Reference
Manual (NOT SUPPLIED)

210219-4

Manuals may be ordered from any Intel sales representative. distributor office or from Intel LiteraWre
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

MULTIBUS® Drivers
Function

Characteristic Sink Current (rnA)
·32
32
32
20

Data
Tri-State
Address
Tri-State
Commands Tri-State
Bus Control Open Collector

ORDERING INFORMATION
Part Number
SBC86/35

Physical Characteristics·
Width:
Height:
Depth:

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.70 in. (1.78 cm)

Weight: 14 oz. (388 gm)
3-62

Description
Single Board Computer

iSBC® 88/25
SINGLE BOARD COMPUTER

•
•
•
•
•
•

Programmable Synchronous!
• Asynchronous
RS232C Compatible

8-Bit 8088 Microprocessor Operating at
5 MHz

Serial Interface with Software
Selectable Baud Rates

One Megabyte Addressing Range
Two iSBXTM Bus Connectors

24 Programmable Parallel I!O Lines
• Two
16-Bit BCD or
• BinaryProgrammable
Timers!Event Counters

Optional Numeric Data Processor with
iSBC® 337 MULTIMODULETM Processor
4K Bytes of Static RAM; Expandable
On-Board to 16K Bytes

•

Sockets for up to 64K Bytes of JEDEC
24!28-Pin Standard Memory Devices;
Expandable On-Board to 128K Bytes

MULTIBUS® Interface for Multimaster
• Configurations
and System Expansion

•

9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels

Development Support with Intel's iPDS,
Low Cost Personal Development
System, and EMV-88 Emulator

The iSBC 88/25 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's technology to provide economical, self-contained, computer-based solutions for OEM applications. The iSBC 88/25 board is complete computer system on a single 6.75 X 12.00-in.
printed circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O ports and
drivers, serial communications interface, priority interrupt logic and programmable timers, all reside on the
board. The large control storage capacity makes the iSBC 88125 board ideally suited for control-oriented
applications such as process control, instrumentation, industrial automation and many others.

143847-1

3-63

September 1987
Order Number: 143847-003

inter

iSBC® 88/25

FUNCTIONAL DESCRIPTION

ASCII data, and iterative word and byte string manipulation functions.

Central Processing Unit

For enhanced numerics processing capability, the
iSBC 337 MULTIMODULE Numeric Data Processor
extends the architecture and data set. Over 60 numeric instructions offer arithmetic, trigonometric,
transcendental, logarithmic and exponential instructions. Supported data types include 16, 32, and 64bit integer, and 32 and 64-bit floating point, 18-digit
packed BCD and 80-bit temporary.

The central processor for the iSBC 88/25 board is
Intel's 8088 CPU operating at 5 MHz. The CPU architecture includes four 16-bit byte addressable data
registers, two 16-bit memory base pointer registers
and two 16-bit index registers, all accessed by a total of 24 operand addressing modes for comprehensive memory addressing and for support of the data
structures required for today's structured, high level
languages, as well as assembly language.

Architectural Features
A 4-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities

Instruction Set
The 8088 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpac.ked

MULTIIUS' SYSTEM IUS

143847-2

Figure 1. ISBC® 88/25 Block Diagram

3-64

inter

iSBC® 88/25

offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64 Kbytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions. All Intel languages support the extended memory capability, relieving the programmer of managing the megabyte
memory space, yet allowing explicit control when
necessary.

The iSSC 88/25 Single Soard Computer contains 24
programmable parallel 110 lines implemented using
the Intel 8255A Programmable Peripheral interface.
The system software is used to configure the 1/0
lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible 1/0 configurations, sockets are provided for interchangeable 1/0 line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required driveltermination characteristics.

Memory Configuration

The 24 programmable 1/0 lines and signal ground
lines are brought out to a 50-pin edge connector.

Parallel 1/0 Interface

The iSSC 88/25 microcomputer contains 4 Kbytes
of high-speed static RAM on-board. In addition, the
on-board RAM may be expanded to 12 Kbytes· via
the iSSC 302 8 Kbyte RAM module which mounts on
the iSSC 88/25 board and then to 16 Kbytes by adding two 4K x 4 RAM devices in sockets on the iSSC
302 module. All on-board RAM is accessed by the
8088 CPU with no wait states, yielding a memory
cycle time of 800 ns.

Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronousl Asynchronous ReceiverlTransmitter (USART) is contained on
the iSSC 88/25 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun and framing error detection are all
incorporated in the USART. The RS232C compatible interface on each board, in conjunction with the
USART, provides a direct interface to RS232C compatible terminals, cassettes and asynchronous and
synchronous modems. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

In addition to the on-board RAM,the iSSC 88/25
board has four 28-pin sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
64 Kbytes of EPROM are supported in 16 Kbyte increments with Intel 27128 EPROMs. The iSSC
88/25 board is also compatible with the 2716, 2732
and 27.64 EPROMs allowing a capacity of 8K, 16K
and 32 Kbytes, respectively. Other JEDEC standard
pinout devices are also supported, including bytewide static and integrated RAMs.
With the addition of the iSSC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 128 Kbytes of
EPROM capacity on-board.

Table1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input
Latched &
Strobed
X
X

Latched
1
2
3

8
8
4
4

X
X
X
X

Output
Latched

X
X
X
X

Latched &
Strobed
X
X

Bidirectional

Control

X(1)
X(1)

3-65

iSBC® 88/25

The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators .associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 88/25 board RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

Programmable Timers
The iSBC 88/25 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of. operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is
reached, an interrupt request
is generated. This function is
extremely useful for
generation of real-time
clocks.

Programmable
One-Shot

Output goes low upon receipt
of an .external trigger edge or
software command and
returns high when terminal
count is reached. This
function is retriggerable.

Rate
Generator

Divide by N counter. The
output will go low for one
input clock cycle, and the
period from one low going
pulse to the next is N times
the input clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising
edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occurring
after the counter "window"
has been enabled or an
interrupt may be generated
after N events occur in the
system.

ISBXTM MULTIMODULETM On-Board
Expansion
Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 88/25 microcomputer. Through
these connectors, additional on-board I/O functions
may be added. iSBX MULTIMODULES optimally
support functions provided by VLSI peripheral components such as additional parallel and serial I/O,
analog I/O, small mass storage device controllers
(e.g., cassettes and floppy disks), and other custom
interfaces to meet specific needs. By· mounting directly on the single board computer, less interface
logic, less power, simpler packaging, higher performance, and lower cost result when compared to other
alternatives such as MULTIBUS form factor compatible boards. The iSBX connectors on the iSBC
88/25 provide all signals necessary to interface to
the local on-board bus. A broad range of iSBX MULTIMODULE options are available in this family from
Intel. Custom iSBX modules may also be designed
for use on the iSBC 88/25 board. An iSBX bus interface specification and iSBX connectors are available
from Intel.

MULTIBUS® SYSTEM BUS AND
MULTIMASTER CAPABILITIES
Overview
The MULTIBUS system bus is Intel's industry standard microcomputer bus structure. Both 8 and 16-bit
single board computers are supported on the MULTIBUS structure with 24 address and 16 data lines.
In its simplest application, the MULTI BUS system
bus allows expansion of functions already contained
ona single board computer (e.g., memory and digital
I/O). However, the MULTIBUS structure also allows
very powerful distributed processing configurations
with multiple processor and intelligent slave I/O, and
peripheral boards capable of solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with a broad array of
board level products, LSI interface components, detailed published specifications and application notes.
3-66

inter

iSBC® 88/25

Table 3. Programmable Interrupt Mode

Expansion Capabilities
Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expanded by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. Input/output capacity may be added with digital I/O
and analog I/O expansion boards. Mass storage capability may be achieved by adding single or double
density diskette controllers, or hard disk controllers.
Modular expandable backplanes and cardcages are
available to support multiboard systems.

Mode
Fully Nested

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

Auto-Rotating

Equal priority. Each level,
after receiving service,
becomes the lowest priority
level until next interrupt
occurs.

Specific
Priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.

Polled

System software examines
priority-encoded system
interrupt status via interrupt
status register.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 88/25 board provides full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 88/25 boards or other bus masters,
including iSBC 80 and iSBC 86 family MULTIBUS
compatible single board computers to share the system bus using a serial (daisy chain) priority scheme
and allows up to 16 masters to share the MULTIBUS
system bus with an external parallel priority decoder.
In addition to the multiprocessing configurations
made possible with multimaster capability, it also
provides a very efficient mechanism for all forms of
DMA (Direct Memory Access) transfers.

interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

Interrupt Request Generation
Interrupt requests to be serviced by the iSBC 88/25
board may originate from 24 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are .brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259.A: PIC or the NMI input
to the CPU directly.

Interrupt Capability
The iSBC 88/25 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8088 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides
control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four priority
processing modes is available for use in designing
request processing configurations to match system
requirements for efficient interrupt servicing with
minimal latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC
accepts interrupt requests from all on-board I/O resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the

Power-Fail Control and Auxiliary
Power
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 and iSBC 640 Power Supply or equivalent, to initiate an orderly shut down of the system in
the event of a power failure. Additionally, an activelow TTL compatible memory protect signal is
brought out of the auxiliary connector which, when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system power-down
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery backup of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

3-67

inter

iSBC® 88/25

System Development Capabilities

Run-Time Support

The development cycle of iSBC 88/25 products can
be significantly reduced and simplified by using the
Intellec Series IV Microcomputer Development System.

Intel also offers two run-time support packages;
iRMX 88 Realtime Multitasking Executive and the
iRMX 86 Operating System. iRMX 88 is a simple,
highly configurable and efficient foundation for
small, high performance applications. Its multitasking structure establishes a solid foundation for modular system design and provides task scheduling
and management, intertask qommunication and synchronization, and interrupt servicing for a variety of
peripheral devices. Other configurable options include terminal handlers, disk file system, debuggers
and other utilities. iRMX 86 is a high functional operating system with a very rich set of features and options based on an object-oriented architecture. In
addition to being modular and configurable, functions beyond the nucleus include a sophisticated file
management and 1/0 system, and powerful human
interface. Both packages are easily customized and
extended by the user to match unique requirements.

PL/M-86
Intel's system's implementation language, PL/M-86,
is available as an Intellec Microcomputer Development System option. PL/M-86 provides the capability to program in algorithmic language and eliminates
the need to manage register usage or allocate memory while still allowing explicit control of the system's
resources when needed.

Table 4. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS Interface

Requests from MULTIBUS resident peripherals or other
CPU boards

8; may be expanded to
64 with slave 8259A
PIC's on MULTIBUS
boards

8255A Programmable
Peripheral Interface

Signals into buffer full or output buffer empty; also BUS
INTR OUT general purpose interrupt from driverl
terminator sockets

8251A USART

Transmit buffer empty and receive buffer full

8253 Timers

Timer 0, 1 outputs; function determined by timer mode

iSBX Connectors

Function determined by iSBX MULTIMODULE board

Bus Fail Safe Timer

Indicates addressed MULTIBUS resident device has not
responded to command within 6 ms

2
4
(2 per iSBX connector)

Power Fail Interrupt

Indicates AC ower is not within tolerance

Power Line Clock

Source of 120 Hz signal from power supply

External Interrupt

General purpose interrupt from parallel port J1 connector

iSBC 337 MULTIMODULE Indicates error or exception condition
Numeric Data Processor

3-68

ISBC@88/25

SPECIFICATIONS

ON-BOARD RAM

4 Kbytes-O-OFFFH

Word Size
WITH ISBC 302 MULTIMODULE RAM

Instruction-8, 16, 24, or 32 bits
Data-8 bits

12 Kbytes-O-2FFFH

System Clock
5.00 MHz or 4.17 MHz

± 0.1 %

WITH ISBC 302 MULTIMODULE BOARD AND
TWO 4K x 4 RAM CHIPS

Qumper selectable)

16 Kbytes-O-3FFFH
NOTE:
4.17 MHz required with the optional iSBC 337 module.

1/0 Capacity
Paraliel-24 programmable lines using one 8255A
Serial-1 programmable line using one 8251A
iSBX Multimodule-2 iSBX MULTIMODULE boards

Cycle Time
BASIC INSTRUCTION CYCLE

Serial Communications Characteristics

At 5 MHz-1.2 /Ls
-400 ns (assumes instruction in the
queue)

Synchronous-5 8-bit characters; internal or external character synchronization; automatic sync insertion
Asynchronous-5 8-bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection

NOTES:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

Memory Cycle Time

Baud Rates

RAM-800 ns (no wait states)
EPROM-Jumper selectable from 800 ns to 1400 ns

Frequency (KHz)
Baud Rate (Hz)
(Software
Selectable)
Synchronous Asynchronous

Memory CapacityI Addressing
ON-BOARD EPROM
Device
Total Capacity
2716
8 Kbytes
16 Kbytes
2732
2764
32 Kbytes
27128
64 Kbytes

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

38400
19200
9600
4800
2400
1760

+16
9600
4800
2400
1200
600
300
150
110

+64
2400
1200
600
300
150
75

NOTES:

WITH iSBC 341 MULTIMODULE EPROM
Device
2716
2732
2764
27128

Total Capacity
16 Kbytes
32 Kbytes
64 Kbytes
128 Kbytes

Frequency selected by I/O write of appropriate 16·bit fre·
quency factor to baud rate register (8253 Timer 2).

Address Range
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH

NOTES:

iSBC 88/25 EPROM sockets support JEDEC 24/28-pin
standard EPROMs and RAMs (2 sockets); iSBC 341 sockets also support E2PROMs.

3-69

iSBC® 88125

Timers

CONNECTORS
DoubleSided Centers
Interface
(in.)
Pins
(qty)

INPUT FREQUENCIES
Reference: 2.458 MHz ± 0.1 % (406.9 ns period,
nominal); or 1.229 MHz ±0.1% (813.8 ns period,
nominal); or 153.6 KHz ± 0.1 % (6.510 fJ-s period,
nominal)

MULTIBUS
System

Mating
Connectors.

0.156

Viking
3KH43/9AMK12
Wire Wrap

0.1

iSBX 960-5

NOTE:
Above frequencies are user selectable.

iSBX Bus
8-Bit Data
Parallel 1/0
(2)

0.1

Event Rate: 2.46 MHz max

3M 3415-000 Flat
or
TI H312125 Pins

OUTPUT FREQUENCIES/TIMING INTERVALS

Serial 1/0

0.1

3M 3462-0001
Flat or
AMP 88106-1 Flat

Dual
Timer/Counter
(Two Timers
Cascaded)

Single
Timer/Counter

Function

Min

Max

Min

Max

Real·Time
Interrupt

1.63",s

427.1 ms

3.26s

466.50 min

Programmable
One-Shot

1.63

"'S

427.1 ms

3.26s

466.50 min

Rate
Generator

2.342 Hz

613.5 KHz

0.000036 Hz

306.8 KHz

Square-Wave
Rate
Generator

2.342 Hz

613.5 KHz

0.000036 Hz

306.8 KHz

Software
Triggered
Strobe

1.63

"'S

427.1 ms

3.26s

466.50 min

Hardware
Triggered
Strobe

1.63",s

427.1 ms

3.26s

466.50 min

2.46 MHz

Event
Counter

Line Drivers and Terminators
1/0 Drivers: The following line drivers are all compatible with the 1/0 driver sockets on the iSBC 881
25 board.

Driver
7438
7437
7432
7426
7409
7408
7403
7400

Characteristics

Sink Current (rnA)

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTES:
I

inverting; NI

non-inverting; OC

open collector.

Interfaces

Port 1 of the 8255A has 32 mA totem-pole bidjrectional drivers and 100 terminators.

Multibus: All signals TIL compatible

1/0 Terminators: 2200/3300 divider or 1 KO pullup.

iSBX Bus: All signals TIL compatible

2200/3300 Option 1

Parallel I/O: All signals TIL compatible
22O!l

Serial 1/0: RS232C compatible, configurable as a
data set or data terminal

+5V.--_ _ _

~~_ _ _ _. . ._ _O

-b

---------------------

Timer: All signals TIL compatible

143847-3

Interrupt Requests: All TIL compatible
1 KO Option 2

I ... ----~,.,~..,~-------14~38~7-4
3-70

inter

iSBC® 88/25

MULTIBUS Drivers

Environmental Characteristics

Function Characteristic Sink Current (rnA)
Data
Tri-State
32
Address
Tri-State
24
Commands Tri-State
32
Bus Control Open Collector
20

Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

Reference Manual
143825-001-iSBC 88/25
Manual (NOT SUPPLIED)

Physical Characteristics
Width: 12.00 in. (30.48 cm)

Depth: 0.70 in. (1.78 cm)
Weight: 14 oz. (388 gm)

ORDERING INFORMATION

Electrical Characteristics
DC POWER REQUIREMENTS

Without EPROM(1)"
RAM only(2)
With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

Reference

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Height: 6.75 in. (17.15 cm)

Configuration

Hardware

Current Requirements
(All Voltages ±5%)
+12V -12V
+5V
3.8A
25mA 23mA
104mA
4.3A
25mA 23mA
4.4A

25mA

23mA

4.4A

25mA

23mA

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode: Does not include power for optional RAM.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator inputs low.
"

3-71

Part Number

Description

SBC 88/25

8-bit Single Board Computer
with 4 Kbytes RAM

..
•
•
•

iSBC® 88/40A
MEASUREMENT AND CONTROL COMPUTER
4K Bytes Static RAM, Expandable via
• iSBC®
301 MULTIMODULETM RAM to

High Performance 4.8/6.67 MHz 8088
8-Bit HMOS Processor

8K Bytes (1K Byte Dual-Ported)

12-Bit KHz Analog-to-Digital Converter
with Programmable Gain Control
16-Bit Differential/32 Single-Ended
Analog Input Channels
Three iSBXTM MULTIMODULETM
Connectors for Analog, Digital, and
other I/O Expansion

•

Four EPROM/E2PROM Sockets for up
to 64K Bytes, Expandable to
128K Bytes with iSBC® 341 Expansion
MULTIMODULETM

•

MULTIBUS® Intelligent Slave or
Multimaster

The Intel iSBC 88/40A Measurement and Control Computer is a member of Intel's large family of Single Board
Computers that takes full advantage of Intel's VLSI technology to provide an economical self-contained
computer based solution for applications in the areas of process control and data acquisition. The on-board
8088 processor with its powerful instruction set allows users of the iSBC 88/40A board to update process
loops as much as 5-10 times faster than previously possible with other 8-bit microprocessors. For example,
the high performance iSBC 88/40A can concurrently process and update 16 control loops in less than 200
milliseconds using a traditional PID(Proportional-lntegral-Derivative) control algorithm. The iSBC 88/40A
board consists of a 16 differential/32 single ended channel analog multiplexer with input protected circuits,
AID converter, programmable central processing unit, dual port and private RAM, read only memory sockets,
interrupt logic, 24 channels of parallel 110, three programmable timers and MULTIBUS control logic on a single
6.75 by 12.00-inch printed circuit card. The iSBC 88/40A board is capable of functioning by itself in a standalone system or as a multi master or intelligent slave in a large MULTIBUS system.

280220-1

3-72

October 1986
Order Number: 280220-001

inter

iSBC® 88/40A COMPUTER

iSBC 88/40 boards or other single board computer
masters or intelligent slaves.

FUNCTIONAL DESCRIPTION
Three Modes of Operation

Intelligent Slave

The iSBC 88/40A Measurement and Control Computer (MACC) is capable of operating in one of three
modes: stand-alone controller, bus multimaster or
intelligent slave. A block diagram of the iSBC
88/40A Measurement and Control Computer is
shown in Figure 1.

The iSBC 88/40A board can perform as an intelligent slave to any Intel 8- or 16-bit MULTIBUS master CPU by not only offloading the master of the analog data collection, but it can also do a significant
amount of pre-processing and decision-making on
its own. The distribution of processing tasks to intelligent slaves frees the system master to do other
system functions. The Dual port RAM with flag bytes
for signaling allows the iSBC 88/40A board to process and store data without MULTIBUS memory or
bus contention.

Stand-Alone Controller
The iSBC 88/40A Measurement and Control Computer may function as a stand-alone single board
controller with CPU, memory and 1/0 elements on a
single board. The on-board 4K bytes of RAM and up
to 64K bytes of rea~ only memory, as well as the
analog-to-digital converter and programmable parallel 1/0 lines allow Significant control and monitoring
capabilities from a single board.

Central Processing Unit
The central processor unit for the iSBC 88/40A
board is a powerful 8-bit HMOS 8088 microprocessor. By moving on-board jumpers, the user can select either a 4.8 or· 6.67 MHz CPU clock rate. The
iSBC 88/40A board can also run at 8 MHz by changing the CPU clock oscillator to a 24 MHz unit. For 8
MHz operation, the iSBC 88/40A board should either be the only MULTIBUS master in the system or
be an intelligent slave that never directly accesses
the MULTIBUS interface.

Bus Multimaster
In this mode of operation the iSBC 88/40A board
may interface and control a wide variety of iSBC
memory and lID boards or even with additional

UULTlaus'" SYSTEM BUS

LOCAL BUS

USER
BATTERY

~_-"---'''''

1018 CPU
(8 MHz OPT.J

' - ; - - - _.......

II DATA PROCESSOR
8087 NUMERIC

EXPANSION

3KCllISA)

..,._ _ _..... 1

'
I

I
4KRAM
I
II _________
EXPANSION
.'
.JI

I
I

r--7.f:---, L________J

ISIe3Dl

lS8C337

ANALOG INPUTS

BACKUP

STATIC RAIl

4.111.17 MHz

..,

PARALLEL DIGITAL 110

~...,.----"'"
10 ma PULSE I
ADDITIONAL FOUR

TO !CS".lOt TO IC8 hO,'3O
SIGNAL CONDITIONINQlSCREW
TERMINATION PANELS

21-PIN SOCKETS

~ _ _ _ _ _ _ _ _ _ _ ...J

ISBC341

Figure 1. iSBC® 88/40A Measurement and Control Computer Block Diagram

3-73

280220-2

inter

iSBC® 88/40A COMPUTER

INSTRUCTION SET-The 8088 instruction repertoire includes variable length instruction format (including double operand instructions), 8-bit and 16-bit
signed and unsigned arithmetic operators for binary,
BCD and unpacked ASCII data, and iterative word
and byte string manipulation functipns. The instruction .set of the 8088 is. a superset' of the 8080A1
8085A family and with available software tools, programs written for the 8080Al8085A can be easily
converted and run on the 8088 processor. Programs
can also be run that are implemented on the 8088
with little or no modification.
ARCHITECTURAL FEATURES-A 4-byte instruction queue provides pre-fetching' of sequential instructions and can reduce the 1.04 ms minimum instruction cycle to 417 ns (at 4.8 MHz clock rate) for
queued instructions. The stack oriented architecture
facilitates nested subroutines and co-routines, reentrant code and powerful interrupt handling. The
memory expansion capabilities offer a 1 megabyte
addressing range. The dynamic relocation scheme
allows ease in segmentation of pure procedure and,
data for efficient memory utilization. Four segment
registers (code, stack, data, extra) contain program
loaded offset values which are used to map 16·bit
addresses to 20-bit addresses. Each register maps
64K bytes at a time and activation of a specific register is controlled explicitly by program control and is
also selected implicitly by specific functions and instructions.
.

Bus Structure
The iSBC 88/40A single board computer has three
buses: 1) an internal bus for communicating with onboard memory, analog-to-digital converter, ISBX
MULTIMODULES and 1/0 options; 2) the MULTIBUS system bus for referencing additional memory
and 1/0 options, and 3) the dual-port bus which allows access to RAM from theon-board CPU and the
MULTIBUS system bus. Local (on-board) accesses
do not require MULTIBUS communication, making
the system bus available for use by other MULTIBUS masters (i.e., DMA devices and other :single
board computers transferring to additional system
memory). This feature allows true parallel processing in a multiprocessor environment. In addition, the
MULTIBUS interface can be used for system expansion through the use of other 8- and 16-bit iSBC
computers, memory and 1/0 expansion boards.

TIMODULE RAM is added to the protected RAM.
The MULTIBUS port base address of the dual-port
RAM can be jumpered to any 1K byte boundary in
the 1M byte address space. The dual-port RAM can
be accessed in a byte-wide fashion from the MULTIBUS system bus. When accessed from the MULTIBUS system bus, the dual-port RAM decode logic
will generate INH11 (Inhibit RAM) to allow dual-port
RAM to overlay other system RAM. The dual-port
control logic is designed to favor an on-board RAM
access. If the dual-port is not currently performing a
memory cycle. for the MULTIBUS system port, only
one wait state will be required. The on-board port
any require more than one wait state if the dual-port
RAM was busy when the on-board cycle was requested. The LOCK prefix facility of the iAPX 88/10
assembly language will disallow system bus accesses to the dual-port RAM. In addition, the on-board
port to the dual-port RAM can be locked by other
compatible MULTIBUS masters, which allows true
symmetric semaphore operation. When the board is
functioning in the master mode, the LOCK prefix will
additionally disable other masters from obtaining the
system bus.
PRIVATE RAM-In addition to the 1 K byte dual-port
RAM, there is a 3K byte section of private static
RAM not accessible from the system bus. This RAM
has a .base address of 00000, and consists of three
Intel 8185 RAM chips which are interfaced to the
multiplexed addressldata bus of the 8088 microprocessor. Expansion of this private RAM from 3K to
7K byte scan be accomplished by the addition 6f an
iSBC 301 MULTIMODULE RAM (4K bytes). When
the 301 is added, protected RAM extends from 0 to
7K, and the base address of the dual-port RAM is
relocated from 3K (OOCOO) to 7K (01 COO). All protected RAM accesses require one wait state. The
private RAM resides on the local on-board bus,
which eliminates contention problems between on. . board accesses to private RAM and system bus accesses to dual-port AM. The private RAM can be
battery backed (up to 16K bytes).
Additional RAM can be added by utilizing JEDEC. compatible static RAMs in the available EPROM
sockets.

RAM Capabilities
DUAL-PORT RAM-The dual-port RAM of the iSBC

88/40A board consists of 1K bytes of static RAM,
implemented with Intel 2114A chips. The on-board
base address 01 this RAM is OOCOO (3K) normally; it
is relocated to 01 COO (7K) when the iSBC 301 MUL.3-74

Parallel 1/0 Interface
The iSBC 88/40A single board computer contains
24 programmable parallel 1/0 lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
1/0 lines in .any combination of unidirectional input!
output and bidirectional ports indicated in Table 1.
There the 1/0 interface may be customized to meet
specific peripheral requirements. In order to take full
advantage of the large number of possible 1/0

inter

iSBC® 88/40A COMPUTER

configurations, sockets are provided for interchangeable I/O line drivers and terminators. Port 2
can also accept TTL compatible peripheral drives,
such as 75461/462, 75471/472, etc. These are
open collector, high voltage drivers (up to 55 volts)
. which can sink 300 mA. Hence, the flexibility of the
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional
line drivers and terminators to provide the required
sink current, polarity, and drive/termination characteristics for each application. The 24 programmable
I/O lines and signal ground lines are brought out to a
50-pin edge connector that mates with flat, woven,
or round cable. This edge connector is also compatible with the Intel ICSTM 920 Digital I/O and iCS 930
AC Signal Conditioning/Termination Panels, for field
wiring, optical isolation and high power (up to 3 amp)
power drive.

Timing Logic
The iSBC 88/40A board provides an 8254-2 Programmable Interval Timer, which contains three
independent, programmable 16-bit timers/event
counters. All three of these counters are available to
generate time intervals or event counts under software control. The outputs of the three counters may
be independently routed to the interrupt matrix. The
inputs and outputs of timers 0 and 1 can be connected to parallel I/O lines on the J1 connector, where
they replace 8255A port C lines. The third counter is
also used for timing E2PROM write operations.

Interrupt Capability
The iSBC 88/40A board provides 9 vectored interrupt levels. The highest level is NMI (Nonmaskable
Interrupt) line which is directly tied to the 8088 CPU.
This interrupt cannot be inhibited by software and is
typically used for Signalling catastrophic events (Le.,
power failure). On servicing this interrupt, program
control will be implicitly transferred through location
00008H. The Intel 8259A Programmable Interrupt
Controller (PIC) provides vectoring for the next eight
interrupt levels. As shown in Table 2, a selection of
four priority processing modes is available to the designer to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PCI accepts interrupt requests from
the programmable parallel and/or iSBX interfaces,
the programmable timers, the system bus, or directly
from peripheral equipment. The PIC then determines
which of the incoming requests is of the highest priority than the level currently being serviced, and, if
appropriate, issues an interrupt to the CPU. Any
combination of interrupt levels may be masked, via
software, by storing a single byte in the interrupt
make register of the PIC. The PIC generates a

EPROM Capabilities
Four 28-pin sockets are provided for the use of Intel
2716s, 2732s, 2764s, 27128s, future JEDEC-compatible 128K and 256K bit EPROMs and their respective ROMs. When using 27128s the on-board
EPROM capacity is 64K bytes. Read only memory
expansion is available through the use of the
iSBC 341 EPROM/ROM memory expansion MULTIMODULE. When the iSBC 341 is used an additional
four EPROM sockets are made available, for a total
iSBC 88/40A board capacity of 128K bytes EPROM
with Intel 27128s.
.

E2PROM Capabilities
The four 28-pin sockets can also accommodate Intel
2817A or 2816A E2PROMs, for dynamic storage of
control loop setpoints, conversion parameters, or
other data (or programs) that change periodically but
must be kept in nonvolatile storage.

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

lines
(qty)

Input
Latched

Output

Latched &
Strobed

Latched

Bidirectional

Control

Latched &
Strobed

X(1)

3-75

inter

iSBC® 88/40A COMPUTER

unique memory address for each interrupt level.
These addresses are equally spaced at 4-byte intervals. This 32-byte lock may begin at any 32-byte
boundary in the lowest 1K bytes of memory, and
contains unique instruction pointers and code segment offset values (for expanded memory operation)
for each interrupt level. After acknowledging an interrupt and obtaining advice identifier byte from the
8259A PIC, the CPU will store its status flags on the
stack and execute an indirect CALL instruction
through the vector location (derived from the device
identifier) to the interrupt service routine.
NOTE:
The first 32 vector locations are reserved by Intel
for. dedicated vectors. Users who wish to maintain
compatibility with present and future Intel products
should not use these locations for user-defined
vector addresses.

Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635, iSBC 640, and iCS 645 Power Supply.
or equivalent.

iSBXTM MULTIMODULETM Expansion
Capabilities
Three iSBX MULTIMODULE connectors are provided on the iSBC 88/40A board. Up to three single
wide MULTIMODULE or one double wide and one
single wide iSBX MULTIMODULE can be added to
the iSBC 88/40A board. A wide variety of peripheral
controllers, analog and digital expansion options are
available. For more information on specific iSBX
MULTIMODULES consult the Intel OEM Microcomputer System Configuration Guide.

Table 2. Programmable Interrupt Modes
Mode
Fully Nested
Auto-rotating

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Specific
Priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.

Polled

System software examines priorityencoded system interrupt status
via interrupt status register.

Processing Expansion Capabilities
The addition of a iSBC 337 Multimodule Numeric
Data Processor offers high performance integer and
floating point math functions to users of the iSBC
88/40A board. The iSBC 337 incorporates the Intel
8087 and because of the MULTIMODULE implementation, it allows on-board expansion directly on
the iSBC 88/40A board, eliminating the need for additional boards or floating point requirements.

MULTIBUS® Expansion
Memory and I/O capacity may be expanded further
and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be
expanded by adding user specified combination of
RAM boards, EPROM boards, or memory combination boards. Input/output capacity may be increased
by adding digital I/O and analog I/O MULTIBUS expansion boards. Mass storage capability may be
achieved by adding single or double density diskette
controllers, or hard disk controllers either through
the use of expansion boards and iSBX MULTIMODULES. Modular expandable backplanes and cardcages are available to support multi board systems.

INTERRUPT REQUEST GENERATION-Interrupt
requests may originate from 26 sources. Two jumper
selectable interrupt requests can be automatically
generated by the programmable peripheral interface
when a byte of information is ready to be transferred
to the CPU (Le., input buffer is full) or a byte of information has been transferred to a peripheral device
(Le., output buffer is empty). A jumper selectable request can be generated by each of the programmable timers. An additional interrupt request line may
be jumpered directly from the parallel I/O driver terminator section. Eight prioritized interrupt request
lines allow the iSBC 88/40A board to recognize and
service interrupts originating from peripheral boards
interfaced via the MULTIBUS system bus. The fail
safe timer can be selected as an interrupt source.
Also, interrupts are provided from the iSBX connectors (6), end-of-conversion, PFIN and from the power line clock.

NOTE:
Certain system restrictions may be incurred by the
inclusion of some of the iSBC 80 family options in
an iSBC 88/40 system. Consult the ,Intel OEM Microcomputer System Configuration Guide for specific data.

Analog Input Section
The analog section of the iSBC 88/40A board receives all control signals through the local bus to
3-76

intJ

iSBC® 88/40A COMPUTER

initiate channel selection, gain selection, sample and
hold operation, and analog-to-digital conversion.
See Figure 2.
INPUT CAPACITY-32 separate analog signals
may be randomly or sequentially sampled in singleended mode with the 32 input multiplexers and a
common ground. For noisier environments, differential input mode can be configured to achieve 16 separate differential signal inputs, or 32 pseudo differential inputs.
RESOLUTION-The analog section provides 12-bit
resolution with a successive approximation analogto-digital converter. For bipolar operation (- 5 to + 5
or -10 to + 10 volts) it provides 11 bits plus sign.
SPEED-The A-to-O converter conversion speed is
50 p.s (20 kHz samples per second). Combined with
the programming interface, maximum throughput via
the local bus and into memory will be 55 microseconds per sample, or 18 kHz samples per second, for
a single channel, a random channel, or a sequential
channel scan at a gain of 1, 5 ms at a gain of 5,250
ms at again of 50, and 20 ms at a gain of 250. A-toO conversion is initiated via a programmed command from the 8088 central processor. Interrupt on
end-of-conversion is a standard feature to ease programining and timing constraints.

made configurable via user program commands up
to 250 x (20 millivolts full scale input range). User
can select gain ranges of 1 (5V), 5 (1V), 50
(100 mY), 250 (20 mY) to match his application.
OPERATIONAL DESCRIPTION-The iSBC 88/40A
single board computer addresses the analog-to-digital converter by executing IN or OUT instructions to
the port address. Analog-to-digital conversions can
be programmed in either of two modes: 1) start conversion and poll for end-of-conversion (EOC), or 2)
start conversion and wait for interrupt at end of con-/
version. When the conversion is complete as signaled by one of the above techniques, INput instructions read two bytes (low and high bytes) containing
the 12-bit data word.
Output Command-Select input channel and start
conversion.
GAIN

CONNECTOR

~
BIT POSITION
INPUT CHANNEL

'\
3

Input Data-Read converted data (low byte) or
. Read converted data (high byte).
DATA
BIT POSITION

'\
7

LOW/STATUS BYTE 'I-03--'1'0-2'1-0-1'1-0-0'1-'--'--'1E-O-'C1
DATA

(
HIGH BYTE

1011 10101 09 1 08 1 07 1 06 1 05 1 04 1

GAIN-To allow sampling of millivolt level signals
such as strain gauges and thermocouples, gain is
LOCAL
BUS

HIGH
IMP.EDANCE
BUFFER
AMP
16 Ct1ANNEL
INPUT

MULTIPLEXER
PROGRAMMABLE
GAIN SELECT
& OFFSET
ADJUST

ANALOG

INPUT
SIGNALS

SIGNAL ..... "
GROUND

r-I-Gl-Ir-G-2""'1r----.-·-J 'I-C-3'I-c-2'I-c-1'I-c"""01

(

ACCURACY-High quality components are used to
achieve 12 bits resolution and accuracy of 0.035%
full scale range ± % LSB at gain = 1. Offset is adjustable under program control to obtain a nominal
±0.024% FSR ± % LSB accuracy at any fixed temperature between O°C and 60°C (gain = 1). See
specifications for other gain accuracies.

CHANNEL SELECT

(

PSEUDO DIFFERENTIAL GROUND

280220-3

Figure 2. iSBC® 88/40 Analog Input Section
,
3-77

iSBC® 88/40A COMPUTER

Offset Correction-At higher gains (X 50, x 250)
the. voltage offset tempco in the A/D circuitry can
sometimes cause unacceptable inaccuraGies. To
correcHor this offset, one channel can be dedicated
to be used as a reference standard. This channel
can be read from the program to determine the
amount of offset. The reading from this channel will
then be subtracted from all other channel readings,
in effect eliminating the offset tempco.

MEMORY ADDRESSING
On-Board ROM/EPROM
FEOOO-FFFFF (using 2716 EPROMs)
FCOOO-FFFFF (using 2732 EPROMs)
F8000-FFFFF (using 2764 EPROMs)
FOOOO-FFFFF (using 27128 EPROMs)

SYSTEM SOFTWARE DEVELOPMENT

On-Board ROM/EPROM (With iSBC 341
MULTIMODULE EPROM option installed)

The development cycle of the iSBC 88/40 board
may be significantly reduced using an Intel Intellec
Microcomputer Development System 'and Intel's
FORTRAN, PASCAL, or PUM 86/88 Software
packages.

FCOOO-FFFFF (using 2716 EPROMs)
FBOOO-FFFFF (using 2732 EPROMs)
FOOOO-FFFFF (using 2764 EPROMs)
EOOOO-FFFFF (using 27128 EPROMs)
On-Board RAM (CPU Access)

SPECIFICATIONS

OOOOO-OOFFF
00000-01 FFF (if iSBC 301 MULTIMODULE RAM option installed)

Word Size
Instruction-8, 16, or 32 bits
Data-8 bits

On-Board RAM
Jumpers allow 1K bytes of RAM to act as slave RAM
for access by another bus master. .Addressing may
be set within any 1 K boundary in the 1-megabyte
system address space.

Instruction Cycle Time (minimum)
8088 Clock Rate

Instruction

4.8 MHz 6.67 MHz 8.0 MHz
In Queue
417 ns
Nolin Queue 1.04 ns

300 ns
750 ns

250 ns
625 ns

Number of
Clock Cycles
2
5

Slave RAM Access
Average: 350 ns

MEMORY CAPACITY

INTERVAL TIMER

On-Board ROM/EPROM/E2PROM

Output Frequencies

Up to 64K bytes; user installed in 2K, 4K, 8K or 16K
byte increments or up to 128K if iSBC 341 MULTIMODULE EPROM option installed. Up to 8K bytes of
E2PROM using Intel 2816As or 2817As may be
user-installed in increments of 2, 4, or 8 bytes.

Single Timer

Function
Real-Time
Interrupt
Interval

On-Board RAM

Min

Max

0.977 JLs

64ms

Dual Timers
(Two Timers
Cascaded)
69.9 minutes
maximum

15.625 Hz 1024 KHz 0.00024 Hz
Rate
Generator
minimum
(Frequency

4K bytes or 8K bytes if the iSBC 301 MULTIMODULE RAM is installed. Integrity maintained during
power failure with user-furnished batteries. 1K bytes
are dual-ported.
Off-Board Expansion

CPU CLOCK

Up to 1 megabyte of user-specified combination of
RAM, ROM, and EPROM.

4.8 MHz ± 0.1 % or 6.67 MHz
able via jumpers);

± 0.1 %.

(User select-

8.0 MHz (with user installed 24 MHz oscillator)
3-78

iSBC® 88/40A COMPUTER

1/0 Addressing

Gain TC (at gain = 1)-30 PPM (typical), 56 PPM
(max) per degree centigrade, 40 PPM at other gains.

All communications to parallel I/O ports, iSBX bus,
A/D port, timers, and interrupt controller are via read
and write commands from the on-board 8088 CPU.

OffsetTC(in % of FSRI'C)

Gain
1
5
50
250

Interface Compatability
Parallel 1/0-24 programmable lines (8 lines per
port); one port includes a bidirectional bus driver. IC
sockets are included for user installation of line drivers and/or I/O terminators and/or peripheral drivers
as required for interface ports.

Interrupts

Offset TC (typical)
0.0018%
0.0036%
0.024%
0.12%

Sample and Hold-Sample Time: 15 p.s
Aperature-Hold Aperature Time: 120 ns
Input Overvoltage Protection: 30 volts
Input Impedance: 20 megohms (min.)
Conversion Speed: 50 p.s (max.) at gain = 1
Common Mode Rejection Ratio: 60 dB (min.)

Physical Characteristics

8088 CPU includes a non-maskable interrupt (NMI).
NMI interrupt is provided for catastrophic events
such as power failure. The on-board 8259A PIC provides 8-bit identifier of interrupting device to CPU.
CPU multiplies identifier by four to derive vector address. Jumpers select interrupts from 26 sources
without necessity of external hardware. PIC may be
programmed to accommodate edge-sensitive or level-sensitive inputs.

Width: 30.48 cm (12.00 in.)
Length: 17.15 cm (6.75 in.)
Height: 1.78 cm (0.7 in.)
2.82 cm (1.13 in.) with iSBC Memory Expansion, MULTIMODULES, iSBX Numeric Data
Processor or iSBX MULTIMODULES.

Electrical Requirements

Analog Input

Power Requirements

16 differential (bipolar operation) or 32 single-ended
(unipolar operation).

Current

Voltage

Full Scale Voltage Range--5 to +5 volts (bipolar), 0 to + 5 volts (unipolar).

+5V
+5V Aux
+12V
-12V

NOTE:
Ranges of 0 to 10V and ± 10V achievable with externally supplied ± 15V power.

Maximum

Typical

5.5A
150mA
120 mA
40mA

4A
100 mA
80mA
30mA

NOTES:
1. The current requirement Includes one worst case (active-standby) EPROM current.
2. If +5V Aux is supplied by the iSBG 88/40A board, the
total + 5V current is the sum of the + 5V and the + 5V
Aux.

Gain-Program selectable for gain of 1, 5, 50, or
250.
Resolution-12 bits (11 bits plus sign for ± 5, ± 10
volts).
Accuracy-Including noise and dynamic errors.
Gain

25°C

1
5
50
250

±0.035% FSR*
±0.06% FSR*
±0.07% FSR*
±0.12% FSR*

Environmental Requirements
Operating Temperature: 0° to + 60°C with 6 CFM
min. air flow across board
Relative Humidity:
to 90% without condensation

NOTE:
FSR = Full Scale Range ± y, LSB. Figures are in percent
of full scale reading. At any fixed temperature between O'G
and 60'G, the accuracy is adjustable to ± 0.05% of full
scale.

Equipment Supplied
iSBC 88/40A Measurement and Control Computer
Schematic diagram
3-79

inter

iSBC® 88/40A COMPUTER

REFERENCE MANUALS

ORDERING INFORMATION

147049·001- SBC 88/40A Measurement and Con·
trol Computer Hardware Reference
Manual (Order Separately).

Part Number Description
SBC 88/40A Measurement and Control Computer

Manuals may be ordered from an Intel sales repre·
sentative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

3·80

iSBC® 186/03A
SINGLE BOARD COMPUTER

•
•
•
•

8.0 MHz 80186 Microprocessor with
Optional 8087 Numeric Data Processor
Eight (Expandable to 12) JEDEC 28-Pin
Sites
Six Programmable Timers and 27
Levels of Vectored Interrupt Control
MULTIBUS® Interface for System
Expansion and Multimaster
Configuration

•

24 Programmable 1/0 Lines
Configurable as a SCSI Interface,
Centronics Interface or General
Purpose 1/0

•
•
•

Two iSBXTM Bus Interface Connectors
for Low Cost 1/0 Expansion
iLBXTM (Local Bus Extension) Interface
for High-Speed Memory Expansion
Two Programmable Serial Interfaces;
One RS 232C, the Other RS 232C or
RS 422 Compatible

The iSBC 186/03A Single Board Computer is a member of Intel's complete line of microcomputer modules
and systems that take advantage of Intel's VLSI technology to provide economical, off-the-shelf, computerbased solutions for OEM applications. The board is a complete microcomputer system on a 7.05 x 12.0 inch
printed circuit card. The CPU, system clock, memory, sockets, 1/0 ports and drivers, serial communications
interface, priority interrupt logic and programmable timers, all reside on the board.
The iSBC 186/03A board incorporates the 80186 CPU and SCSI interface on one board. The extensive use of
high integration VLSI has produced a high-performance single-board system. For large memory applications,
the iLBX local bus expansion maintains this high performance.
.

230988-1

3-81

September 1987
Order Number: 230988-005

inter

iSBC® 186/03A COMPUTER

OVERVIEW

BITBUSTM MASTER CONTROLLER
The BITBUS interconnect environment is a high performance low-cost microcontroller interconnect
technology for distributed control of intelligent industrial machines such as robots and process controllers. The BITBUS interconnect is a special purpose
serial bus which is ideally suited for the fast trilnsmission of short messages between the .microcontroller nodes in a modularly distributed system.

Operating Environment
The iSBC 18S/03A single board computer features
have been designed to meet the needs of numerous
microcomputer applications. Typical applications include:
.'
• Multiprocessing single board computer
• BITBUS master controller

The iSBC 18S/03A board can be implemented as
the MULTIBUS-based master controller CPU which
monitors, processes and updates the control status
of the distributed system. The iSBX 344 board is
used to interface the iSBC 18S/03A board to the
BITBUS interconnect. Actual message transfer over
the iSBX bus can be accomplished by either software polling by the CPU or by using the on-chip
8018S DMA hardware instead of the CPU. Using
DMA, the CPU is only required to start the DMA process and then poll for the .completion of the message transfer, thus dramatically improving the data
transmission rate and master control processor efficiency. The maximum transfer rates over the iSBX
bus for the iSBC 18S/03A board are about 900 messages/second in polled mode and 2S00 messages/
second in DMA mode. An 8 MHz iSBC 18S/03A
board in DMA mode is 3 times as fast as a typical
S MHz iSBC 8S/30 board running in polled mode.
The iSBC 18S/03A board in DMA mode provides the
highest performance/price solution for BITBUS
message transmission out of all of Intel's complete
line of 1S-bit CPU modules.
.

• Stand-alone singel board system
MULTIPROCESSING SINGLE BOARD
COMPUTER
High-performance systems often need to divide system functions among multiple. processors. A multipr.oc~ssing single ~(jard computer distributes an applications processing load over multiple processors
that communicate over a system bus. Since these
applications use the system bus for inter-processor
communication, it is required that each processor
has local execution memory.
The iSBC 18S/03A board supports loosely coupled
multiprocessing (where each' processor performs a
spe~ific function) through its MULTIBUS compatible
arc,hltecture. The IEEE 79S system bus facilitates
processor to processor communication, while the
iLBX .bus makes high-speed data and execution
memory available to each CPU as shown in Figure 1.
This architecture allows multiple processors to run in
~arallel enabling very high-performance applications.

ISBC" 544
BOARD

c::::J c::::J
ISac"' 186/03A
.BOARD

ISac"' 012CX RAM
BOARD

MULTI BUS· SYSTEM BUS

230988-2

Figure 1. A Multiprocessing Single Board Computer Application
.3-82

iSBC® 186/03A COMPUTER

INTERNAL MACHINE CONTROL

,-------------------,
I

MASTER CONTROLLER

¢><)
ISBX'· 344
BITBUS'·
INTERFACE
BOARD

I
I
iSBX'· BUS
BITBUS'·
INTERCONNECT

MOTOR
CONTROL

¢><)
IRCB 44/10
/'--...AISBX'·
VYBUS

ISBX'· BUS

'-:::-:-:::=:"'1 OPERATOR
CUSTOM INTERFACE
PUSH
L...:=::':'::"-i BUTTONS

TEMPERATURE
MONITORING
AND CONTROL

OPERATOR
DISPLAY

L ___________________

I
I
I
I
I
I
I
I
I

I
I
I
I
I

I
~

ICHANDLER

230988-3

Figure 2. Sample iSBC® 186/03A BITBUSTM Master Application
iSBC 186/03A board. The KEPROM memory device
employs a data protection mechanism which makes
the memory array unreadable until unlocked by an
authorized 64-bit "key". KEPROMs protect system
software from unauthorized use. If more memory is
needed, an optional iSBC 341 memory site expansion board can be added to provide an additional
four JEDEC sites. Two iSBX MULTIMODULETM
boards can be added to the iSBC 186/03A board to
customize the board's 1/0 capabilities. As shown in
Figure 3, the iSBX connectors can support a singleboard system with the analog input and output modules needed by machine or process control systems.

STAND-ALONE SINGLE BOARD SYSTEM
A stand-alone single board system is a complete
computer system on one board. By reducing the system's board count, the single board system saves
space, power, and ultimately, costs. The on-board
resources need to be capable of performing all of
the basic system functions. These applications typically require terminal support, peripheral control, local RAM and program execution. In previous generations of single board computers, these functions
could only be obtained with multiple board solutions.
The iSBC 186/03A board integrates all the functions
of a general purpose system (CPU, memory, I/O and
peripheral control) onto one board. The iSBC
186/03A board can also becustomized as a single
board system by the selection of memory and iSBX
I/~options. The board's 8 JEDEC 28-pin sockets
can accommodate a wide variety of byte-wide memory devices. For example, four 27256 EPROMS and
four 2186 IRAMs can be installed for a total of 128
KB of EPROM program storage and 32 KB of RAM
data storage. In addition, Intel's JEDEC site compatible 27916 KEPROMTM (Keyed Access EPROM)
memory device may. be configured for use on the

FUNCTIONAL DESCRIPTION

Architecture
The iSBC 186/03A board is functionally partitioned
into six major sections: .central processor, memory,
SCSI compatible parallel interface, serial 1/0, interrupt control and MULTIBUS bus expansion. These
areas are illustrated in Figure 4.

3-83

inter

ISBC® 186/03A COMPUTER

230988-4

.Figure 3. A Stand-Alone Single .Board System Application

80188
cpuaDMA

FOUR SITE
EXPANSION

L ____________ _

!:
MULTISUS· SYSTEM BUS

230988-5

Figure 4. ISBC®. 186/03A Board Block Diagram

3-84

inter

iSBC® 186/03A COMPUTER

generator, square-wave generator, software triggered strobe, hardware triggered strobe and event
counter. The contents of each counter may be read
at any time during system operation.

CENTRAL PROCESSOR

The 80186 component is a high-integration 16-bit
microprocessor. It combines several of the most
common system components onto a single chip (Le.
Direct Memory Access, Interval Timers, Clock Generator and Programmable Interrupt Controller). The
80186 instruction set is a superset of the 8086. It
maintains object code compatability while adding
ten new instructions. Added instructions include:
Block I/O, Enter and Leave subroutines, Push Immediate, Multiply Quick, Array Bounds Checking,
Shift and Rotate by Immediate, and Pop and Push
All.
-

MEMORY

There are eight JEDEC 28-pin memory sites on the
iSBC 186/03A board providing flexible memory expansion. Four of these sites (EPROM sites) may be
used for EPROM or E2PROM program storage,
while the other four (RAM sites) may be used for
static RAM or iRAM data storage or used as additional program storage. The eight sites can be extended to twelve by the addition of an iSBC 341
MULTIMODULE board. These additional sites will
provide up to 64K by1es of RAM using 8K x 8 SRAM
or iRAM devices. The EPROM sites (Bank B) are
compatible with 8K x 8 (2764), 16K x 8 (27128A),
32K x 8 (27256), 64K x 8 (27512) as well as 2K x 8
(2817A) and 8K x 8 (2864) E2PROMs. The RAM
sites (Bank A) are compatible with all by1ewide
SRAM, iRAM or NVRAM devices. NVRAM usage requires additional circuitry in order to guarantee data
retention. (Refer to AP-173 for further information.)
Bank A can be reassigned to upper memory just below the assigned memory space for Bank B to support additional EPROM or E2PROMs.

Use of the 80130 component is limited to the 3 timers and 8 levels of interrupts available. Direct processor execution of the 16K by1es of iRMX 86 Operating System nucleus primitives is not supported.
An optional 8087 Numeric Data Processor may be
installed by the user to dramatically improve the
186/03A board's numerical processing power. The
interface between the 8087 and 80186 is provided
by the factory-installed 82188 Integrated Bus Controller which completes the 80186 numeric data processing system. The 8087 Numeric Data Processor
option adds 68 floating-point instructions and eight
80-bit floating point registers to the basic iSBC 186/
O~A board's programming capabilities. Depending
on the application, the 8087 will increase the performance of floating point calculations by 50 to 100
times.
TIMERS

The 80186 provides three internal 16-bit programmable timers. Two of these are highly flexible and
are connected to four external pins (two per timer).
They can be used to count external events, time external events, generate nonrepetitive waveforms,
etc. As shipped on the iSBC 186/03A board, these
two timers are connected to the serial interface, and
provide baud rate generation. The third timer is not
connected to any external pins, and is useful for
real-time coding and time-delay applications. In addition, this third timer can be used as a prescaler to
the other two, or as a DMA request source. The
80130 provides three more programmable timers.
One is a factory default baud rate generator and outputs an 8254 compatible square wave that can be
used as an alternate baud rate source to either serial
channel. The 80130's second timer is used as a system timer. The third timer is reserved for use by the
iRMX Operating System. The system software configures each timer independently to select the deSired function. Available functions include: interrupt
on terminal count, programmable one-shot, rate

Memory addressing for the JEDEC sites depends on
. the device type selected. The four EPROM sites are
top justified in the 1 MB address space and must
contain the power-on instructions. The device size
determines the starting address of these devices.
The four RAM sites are, by default, located starting
at address O. The addressing of these sites may be
relocated to upper memory (immediately below the
EPROM site addresses) in applications where these
sites will contain additional program storage. Th.e
optional iSBC 341 MULTIMODULE sites are addressable immediately above the RAM site addresses.
Power-fail control and auxiliary power are provided
for protection of the RAM sites when used with static
RAM devices. A memory protect Signal is provided
through an auxiliary connector (J4) which, when asserted, disables read/write access to RAM memory
on the board. This input is provided for the protection of RAM contents during system power-down sequences. An auxiliary power bus is also provided to
allow separate power to RAM for systems requiring
battery back-up of read/write memory. Selection of
this auxiliary RAM power bus is made via jumpers on
the board. .
.

3-85

inter

iSBC® 186/03A COMPUTER

The Centronics interface requires very little software
overhead since a PAL device is used to provide necessary handshake timing. Interrupts are generated
for printer fault conditions and a DMA request is issued for every character. The interface supports
Centronics type printers compatible with mOdels 702
and 737.

SCSI PERIPHERAL INTERFACE
The iSBC 186/03A board includes a parallel peripheral interface that consists of three 8-bit parallel
ports. As shipped, these ports are configured for
general purpose 1/0. The parallel interface may be
reconfigured to be compatible with the SCSI disk interface by adding two user-supplied. and programmed Programmable Array Logic (PAL) devic~s,
moving jumpers and' installing a user-su~phed
74LS640-1 device. Alternatively, the parallel Interface may be reconfigured as aOMA controlled Centronics compatible line printer interface by adding
one PAL and changing jumpers. Refer to the iSBC
186/03A Hardware Reference Manual for PAL
equations and a detailed implementation procedure.

SERIAL 1/0
The iSBC 186/03A Single Board Computer contains
two programmable communications interfaces using
the Intel 8274 Multi-Protocol Serial Controller
(MPSC).
Two 80186 timer outputs are used as software selectable baud rate generators capable of supplying
the serial channels with common.' communications
frequencies. An 80130 baud rate timer may be jumpered to either serial port to provide higher frequency
baud rates. The mode of operation (i.e., asynchronous, byte synchronous or bisynchronous pro~o
cols), data format,' control character format, panty,
and baud rate are all under program control. The
8274 provides full duplex, double buffered trans~it
and receive capability. Parity~ overrun, and framing
error detection are all incorporated in the MPSC.
The iSBC 186/03A board supports operation in the
polled, interrupt and DMA driven in.terfa~es t~rou~h
jumper options. The default configuration IS with
channel A as RS422A1RS449, channel B as
RS232C. Channel A can optionally be configured to
support RS232C. Both channels are default configured as data set (DCE). Channel A can be reconfigured as data terminal (DTE).for connection to a modem-type device.

The SCSI (Small Computer Systems Interface) interface allows up to 8 mass storage peripherals such
as Winchester disk drives, floppy disk drives and
tape drives to be connected directly to the iSBC
186/03A board. Intel's iSBC 186/03A board utilizes
. a single initiator, Single target implementation of the
SCSI bus specification. Bus arbitration and deselectlreselect SCSI features are not supported. Single host, multiple target configurations can be used.
However, the iSBC 186/03A board will stay connected to one target until the transaction is completed before switching to the second target. The iSBC
186/03A board's SCSI interface implements a 5 megabit/second transfer rate. A sample SCSI application is shown in Figure 5. Intel tested iSBC 186103A
board compatible SCSI controllers include Adaptek
4500, DTC 1410, Iomega Alpha 10, Shugart 1601
and 1610, Vermont Research 8103 and Xebec
1410.

SCSI BUS

ISac" 188/03A

BOARD

MULTIBUS· SYSTEM BUS

230988-6

Figure 5. Sample SCSI Application
3-86

inter

iSBC® 186/03A COMPUTER

iLBX local bus expansion and the iSBX MULTIMODULE expansion bus as shown in Figure 6. Each bus
structure is optimized to satisfy particular system requirements. The system bus provides a basis for
general system design including memory and 1/0
expansion as well as multiprocessing support. The
iLBX bus allows large amounts of high performance
memory to be accessed by the iSBC 186/03A board
over a private bus. The iSBX MULTIMODULE expansion board bus is a means of adding inexpensive
1/0 functions to the iSBC 186/03A board. Each of
these bus structures are implemented on the iSBC
186/03A board providing a flexible system architecture solution.

INTERRUPT CONTROL
The iSBC 186/03A board provides 27 on-board vectored interrupt levels to service interrupts generated
from 33 possible sources.
The interrupts are serviced by four programmable
interrupt controllers (PICs): one in the 80186 component, one in the 80130 component, one in the 8259A
component and one in the 8274 compQnent. The
80186, 8259A and 8274 PICs act as slaves to the
80130 master PIC. The highest priority interrupt is
the Non-Maskable Interrupt (NMI)'line which is tied
directly to the 80186 CPU. This interrupt is typically
used to signal catastrophic events (e.g. power failure). The PICs provide prioritization and vectoring for
the other 26 interrupt requests from on-board 1/0
resources and from the MULTIBUS system bus. The
PICs then resolve the requests according to the programmable priority resolution mode, and if appropriate, issue an interrupt to the CPU.
.

MULTIBUS® SYSTEM BUS-IEEE 796
The MULTIBUS system bus is an industry standard
(IEEE 796) microcomputer bus structure. Both 8and 16-bit single board computers are supported on
the IEEE 796 structure with 20 or 24 address and 16
data lines. In its simplest application, th!=, system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and I/O).
However, the IEEE 796.bus also allows very powerful distributed processing configurations with mUltiple processors and intelligent slave, 1/0 and peripheral boards capable of solving the most demanding
microcomputer applications. The MULTIBUS system
bus is supported with a broad array of board-level
products, LSI interface components, detailed published specifications and application notes.

Table 1 contains a list of devices and functions capable of generating interrupts. These interrupt
sources are jumper configurable to the desired interrupt request level.

Expansion
OVERVIEW
The iSBC 186/03A board architecture includes
three bus structures: the MULTIBUS system bus, the

Table 1. Interrupt Request Sources
Number of
Interrupts

Function

Device
MULTIBUS Bus
Interface
INTO-INT7

Requests from MULTIBUS Bus Resident Peripherals or
Other CPU

8274 Serial Controller

Transmit Buffer Empty, Receive Buffer Full and Channel
Errors

Internal 801 86Timer
andDMA

Timer 0, 1, 2, Outputs (Function Determined by Timer
Mode) and 2 DMA Channel Interrupts

80130 Timer Output

iRMX System Timer (SYSTICK)

iSBX Bus Connectors

Function Determined by iSBX MULTIMODULE Board

6
(3 per
iSBX Connector)

Bus Fail-Safe Timer

Indicates Addressed MULTlBUS Bus Resident Device
Has Not Responded to Command within 10 ms

8255A Parallel 1/0
Controller

Parallel Port Control

J4 Connector

External/Power-Faillnterrupts

3-87

iSBC® 186/03A COMPUTER

ISBX'·

MULTIMODULE'·
BOARD

230988-7

Figure 6. ISBC® 186/03A Board System Architecture
lines for maximum data transfer rates. MULTIMODULE boards designed with 8-bit data paths and using
the 8-bit iSBX connector are also supported on th$iSBC 186/03A board. A broad range of iSBX MULTIMODULE options are available from Intel. Custom
iSBX bus modules may also be. designed. An iSBX
bus interface specification is available from Intel.

ILBXTM BUS-LOCAL BUS EXTENSION

The iSBC 186/03A board provides a local bus extension (iLBX) interface. This standard extension allows on-board memory performance with physically
off-board memory. The combination of a CPU board
and iLBX memory boards is architecturally equivalent to a single board computer and thus can be
called a "virtual single board computer". The iLBX
bus is implemented over the P2 connector and requires independent cabling or backplane connection.

OPERATING SYSTEM SUPPORT
Intel's iRMX 86 Operating System is a highly functional operation system with a very rich set of features and options based on an object-oriented architecture. In addition to being modular and configurable, functions include a sophisticated file management and 1/0 system, and a powerful human interface. The iRMX 86 Release 6 Operating System can
be used with the iSBC 186/03A board to generate
application code for iRMX 86 based systems.

ISBXTM BUS MULTIMODULETM
ON-BOARD EXPANSION

Two iSBX MULTIMODULE board connectors are
provided on the iSBC 186/03A microcomputer
board. Through these connectors, additional onboard 1/0 functions may be added.· iSBX MULTIMODULE boards optimally support functions provided by VLSI peripheral components such as additional parallel and serial 1/0, analog I/O, and graphics
control. The iSBX bus connectors on the iSBC
186/03A board provide all signals necessary to interface to the local on-board bus, including 16 data

NOTE:

Intel does not support the direct processor execution of the 16K bytes of the iRMX 86 Operating
System nucleus primitives from the 80130 component.

3-88

iSBC® 186/03A COMPUTER

allowing explicit control of the system's resources
when needed. C 86 is especially appropriate in applications requiring portability and code density. FORTRAN 86, PASCAL 86, and BASIC 86 are also available on the iRMX 86 operating system, on the System 86/3XX and on the Intellec development system.

DEVELOPMENT ENVIRONMENT
Intel offers numerous tools to aid in the development
of iSBC 186/03A board applications. These include
on-target development, full development systems,
in-circuit emulators and programming languages.
Some of the features of each are described below.
Using the iRMX 86 Operating System, software development can be performed directly on the iSBC
186/03A board. This on-target development is the
, most economical way to develop iSBC 186/03A
board based projects.

SPECIFICATIONS
Word Size
Instruction-8, 16,24 or 32 bits
Data-8 or 16 bits

The development cycle of iSBC 186/03A board
products can be significantly reduced and simplified
by using either the System 86/3XX (iRMX 86-based)
or the Intellec® Series Microcomputer Development
Systems.

System Clock
8.0 MHz

The Integrated Instrumentation In-Circuit Emulator
(1 2 ICETM) provides the necessary link between an
Intellec development system and the "target" iSBC
186/03A execution system. In addition to providing
the mechanism for loading executable code and
data into the iSBC 186/03A boards, the 121CE 186
emulator provides a sophisticated command set to
assist in debugging software and final integration of
the user hardware and software.

Numeric Data Processor (Optional)
8087-1

Basic Instruction Cycle Time
750 ns
250 ns (assumes instruction in the queue)

Intel has two systems implementation languages,
PL/M 86 and C 86. Both are available for use on the
iRMX 86 Operating System, on the System 86/3XX
and on the Intellec Microcomputer Development
System. PL/M 86 provides the capability to program
in algorithmic language and eliminates the need to
manage register usage or allocate memory while still

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le. two clock cycles plus instruction
fetch). Zero wait-state memory is assumed.

MEMORY RESPONSE TIMES
Device Type
EPROM Memory Sites
oWait States
1 Wait State
RAM Memory Sites
with SRAMs or EPROMs
o Wait States
1 Wait States
with 2186 IRAMs
1 Wait State
2 Wait States

Max Access Time
(from Chip Enable)

Min Cycle Time

245 ns
370 ns

318 ns
443 ns

197 ns
322ns

318 ns '
443 ns

261 ns
386ns

443 ns
568 ns

NOTE:
The number of wait states inserted is jumper selected depending on memory device, specifications.

3-89

inter

iSBC® 186/03A COMPUTER

MEMORY CAPACITY/ADDRESSING

Common Baud Rates
Using 80130 Timer:
Using 80186 Timers:
500K
750K
125K
500K

Four EPROM Sites
Device
2764 EPROM
27128 EPROM
27256 EPROM
27512 EPROM

Capacity
32 KB
64KB
128 KB
256 KB

Address Range
F8000wFFFFFH
FOOOOH-FFFFFH
EOOOOwFFFFFH
COOOOH-FFFFFH

Four RAM Sites
Device

Capacity

Address Range

2KSRAM
8KSRAM
32KSRAM
2186HAM
2817A E2PROM
2764 EPROM

8KB
32KB
128 KB
32 KB
8KB
32 KB

27128 EPROM

64 KB

27256 EPROM

128 KB

0-01FFFH
0-07FFFH
0-1FFFFH
0-07FFFH
FOOOOH-F7FFFH*
FOOOOw F7FFFH
(below EPROM Sites)
EOOOOH-EFFFFH
(below EPROM Sites)
COOOOH - OFFFF H
(below EPROM Sites)

Capacity

2KSRAM
8KSRAM
32KSRAM
2186 RAM
2817A E2PROM

8 KB
32 KB
128 KB
32 KB
8KB

1~K

64K
48K
19.2K
9600
4800
2400
1200
600
300
150
110*
75*

, 'Asynchronous use only
NOTE:
Frequency selected by 1/0 write of appropriate 16-bit frequency factor to baud rate register of 80186 or 80130 timers.

Four iSBC® 341 Expansion Sites
Device

48K
19.2K
9600
4800
2400
1200
600
300
150
110'
75*

Timer Input Frequency

Address Range

80186 Reference: 2.0 MHz ± 0.1 %
80130 Reference: 8.0 MHz ± 0.1 %

02000H-03FFFH
08000wOFFFFH
10000H-1 FFFFH
08000wOFFFFH
02000w03FFFH ..

Interface Compliance
MULTIBUS- IEEE 796 compliance: Master 016
M24 116 VO EL
iSBX Bus- Two 8/16 bit iSBX bus connectors allow use of up to 2 single-wide modules or 1 single-wide and 1 doublewide module. Intel, iSBX bus compliance: 016/16 OMA
iLBXIntel iLBX bus compliance: PM 016
SerialChannel A: Configurable as RS 422A
or RS 232C compatible,
configurable as a data
set or data terminal
Channel B: RS 232C compatible,
configured as data set
Parallel 1/0- SCSI (ANSI-X3T9, 2/82-s) compatible or Centronics 702 or 737 compatible (requires user supplied PALs and
74LS640-1)

NOTE:
All on board memory is local to the CPU (i.e. not dual-ported).
'Must use 8k x 8 decode option. there are four copies of
the E2PROM in the 8K x 8 address area.
"(May be mixed with 2K x 8 SRAM)

Serial Communications Characteristics
Synchronous-

5-8 bit characters, internal or external character synchronization;
automatic sync insertion; break
character generation
Asynchronous- 5-8 bit characters; 1, %, or 2
stop bit; false start bit detection.

3-90

iSBC® 186/03A COMPUTER

PHYSICAL CHARACTERISTICS

CONNECTORS
Interface
MULTIBUS
System

iSBX Bus
8·Bit Data
16-Bit Data

Double·
sided
Pins

Width: 12.00 in. (30.48 cm)
Length: 7.05 in (17.90 cm)
Height: 0.50 in. (1.78 cm)
Weight: 13 ounces

Mating
Connectors

86 (P1)

Viking
3KH43/9AMK12
Wire Wrap

60 (P2)

Viking
3KH30/9JNK

Viking 000292·0001

Viking 000293-0001

Serial 1/0

iLBX Bus

Kelam
RF30-2853-542

Parallel
Interface

3M 3425-6000
3M 3425-6050
w/strain
Ansley 609-5001 M

ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: O·C to 60·C at 6 CFM airflow over the board.
Relative Humidity: to 90% (without condensation)

ELECTRICAL CHARACTERISTICS

3M 3452-0001 Flat
AMP88106-1 Flat

The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
battery back-up or expansion modules.
Voltage
(volts)
+5
+ 12
-12

ORDERING INFORMATION
Part Number
SBC 186/03A

Description
186-based single board computer

REFERENCE MANUAL
iSBC® 186/03A Single Board Computer Hardware
Reference Manual-Order Number 148060

3-91

Max. Current
(amps)
5.4
0.04
0.04

Max Power
(watts)
27
0.48
0.48

iSBC® 286/10A
SINGLE BOARD COMPUTER
8 MHz 80286 Microprocessor
• Supports
User Installed 80287.Numeric
• Data Processor
iLBXTM Interface for iLBX Memory
• Board
Expansion
o
Wait-State Synchronous Interface to
• EX Memory Expansion Boards
Eight JEDEC 28-Pin Sites for Optional
• SRAMliRAM/EPROM/E2PROM

•

On-Board Memory Capacity
• Maximum
384 KB
iSBXTM Bus Interface Connectors
• Two
for 1/0 Expansion
16 Levels of Vectored Interrupt Control
• Centronics-Compatible
• Printer Interlace Parallel 1/0
Programmable Multlprotocol
• Two
Synchronousl Asynchronous Serial
Interfaces; One RS232C, the Other
RS232C or RS4221449 Compatible

Components
Optional Expansion to Sixteen JEDEC .
28-Pin Sites with Two iSBE® 341
. Boards

The iSBC@ 286/10A Single Board Computer is a member of Intel's complete line of microcomputer modules
and systems which take advantage of Intel's VLSI technology to provide economical, off-the-shelf, computerbased solutions for OEM applications. The board is a complete microcomputer system on a 6.75 x 12.0 inch
printed circuit card. The CPU, system clock, memory sockets, lID ports and drivers, serial communications
interface, priority interrupt logic and programmable timers all reside on the board. The iSBC 286/10A board
offers both a standard iLBX interface for high-speed memory access to Intel's series of iLBX memory boards
and a new,O wait-state, synchronous interface for use with lritels EX series of memory boards. The iSBC
286/10A Single Board Computer is fully compatiblEi with its predecessor, the iSBC 286/10A board, and can be
. .
used in applications originally designed for the earlier model.

280079-1

• XENIXTM is a trademark of MICROSOFT Inc.
• UNIXIH> is a registered trademark of BELL Labs.

3-92

September 1987
Order Number: 280079-005

infef

iSBC® 286/10A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

Architectural Features
The 8086, 8088, 80186 and the 80286 microprocessor family contains the same basic set of registers,
instructions, and addressing modes. The 80286
processor is upward compatible with the 8086,
8088, and 80186 CPUs.

Overview
The iSBC 286/10A board utilizes the powerful
80286 CPU within the MULTIBUS® system architecture, enhanced by the industry standard iLBX bus
and a new, 0 wait-state, synchronous memory interface, to provide a high performance 16-bit solution.
This board also includes on-board interrupt, memory
and 1/0 features facilitating a complete signal board
computer system. The iSBC 286/10A board is designed to be fully compatible with the iSBC 286/10
board, and only minor changes to software timing
loops may be required.

The 80286 operates in two modes: 8086 real address mode, and protected virtual address mode. In
8086 real address mode, programs use real address
with up to one megabyte of address space. Programs use virtual addresses in protected virtual address mode, also called protected mode. In protected mode, the 80286 CPU automatically maps 1 gigabyte of virtual addresses per task into a 16 megabyte real address space. This mode also provides
memory protection to isolate the operating system
and ensure privacy of each task's programs and
data. Both modes provide the same base instruction
set, registers, and addressing modes.

Central Processing Unit
The central processor for the iSBC 286/10A board
is the 80286 CPU operating at a 8.0 MHz clock rate.
The 80286 CPU is upwardly compatible with Intel's
8088 and iAPX 86 CPUs. The 80286 CPU runs 8088
and 86 code at substantially higher speeds due to
it's parallel chip architecture. In some cases, software timing loops may have to be adjusted to accommodate the faster CPU clock. In addition, the
80286 CPU provides on chip memory management
and protection and virtual memory addressing of up
to 1 gigabyte per task. Numeric processing power
may be enhanced with the user installed 80287 numerics processor. The clock rates for the 80286 and
the 80287 are independent with the 80287 rate
jumper selectable at either 5.3 or 8.0 MHz.

VECTORED INTERRUPT CONTROL

Incoming interrupts are handled by two on-board
8259A programmable interrupt controllers and by
the 80286's NMI line. Interrupts originating from up
to 16 sources are prioritized and then sent to the
CPU as a vector address. Further interrupt capability
is available through bus vectored interrupts where
slave 8259 interrupt controllers are resident on separate iSBC boards and are then cascaded into the
on-board interrupt control.
INTERRUPT SOURCES

Instruction Set

Twenty-three potential interrupt sources are routed
to the interrupt jumper matrix where the user can
connect the desired interrupt sources to specific interrupt levels. Table 1 includes a list of devices and
functions supported by interrupts.

The 80286 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.
For enhanced numerics processing capability, the
80287 Numeric Data Processor extends the 80286
architecture and data set. Over 60 numeric instructions offer arithmetic, trigonometric, transcendental,
logarithmic and exponential instructions. Supported
data types include 16-, 32-, and 64-bit integer, 32and 64-bit floating point, 18-digit packed BCD and
80-bit temporary. The 80287 meets the proposed
IEEE P754 standard for numeric data processing
and maintains compatibility with 8087-based systems.

MEMORY CAPABILITIES

There are a total of eight 28-pin JEDEC sites on
board. Four sites are for local memory and can contain up to 256K bytes of EPROM devices. The four
other sites are known as the dual-port memory and
. may be addressed by the MULTIBUS interface and
the on-board CPU bus. Up to 128K bytes of either
iRAM, SRAM, EPROM, or E2PROM can reside in
these sites. Both the local and dual-port memory
can be expanded to eight sites each by using two
iSBC 341 JEDEC expansion modules. In this way,
smaller size memory devices can be used up to the
256KB (local) and 128KB (dual-port) memory capacities.

3-93

l
~'.'-'

.. --RS232C/RS4221
RS449 INTERFACE

DRIVERITER..INATOR
INTERFACE

'11

POWERFAIL_

lEi

...CD

en03

€I

...

cO ......
.j>.
0

:r:03

INTERRUPT
MATRIX

:-"

80287 NU"ERIC
DATA PROCESSOR
(USER SUPPLIED)

PROGRA.... ABLE
PERIPHERAL
INTERFACE
(1255A)

ONE
PROGRA.... ABLE
TI ..ER
(1I31254A)

I
I
I
I

(JU .. PERSI

~
PROGRA ....ABLE
INTERRUPT
CONTROLLERS
(TWOI259A)

iS8X"BUS
..ULTI"ODULE ..
CONNECTOR

~------

I
I
I
I

r--- J

--"2

iD
(')

SiTes

;FOUR28PjN
iSBC· 341

SERIAL
INTERFACE
(USART)
(1274)

1--

FOUR 21 PIN SITES
(LOCAL ..E.. ORYI

l>
:Jl
C

i,z

iLBX'-BUS
INTERFACE

8MHz
80288
CPU

SYNCHRONOUS
INTERFACE

MULTIBUS' 1
MULTIMASTER
INTERFACE
L

;.-

DUAL·PORT
CONTROLLER

(')

r------·

I FOUR 21 PIN SITES
ISac' 341

I"-rVI

FOUR 21 PIN SITES

s:::

"tI

c:
-I
m

:Jl

<;iLBX'. BUS/sYNCHRONDUS INTERFACE)

}

iii

(f)

:0;'

...
DI

.....

ON·BOARD LOCAL BUS

en
.......
l>

PROGRA ....ABLE
BAUD RATE
GENERATOR
(2138254)

0'
()

iSaX"
MULTI"ODULE '.
CONNECTOR

Lr -<

386
CPU

MONITOR EPROMS

--"ON.TARGET
,
DEVELOPMENT
ENVIRONMENT

- OR·

iRMXTM 286 R.2
OPERATING SYSTEM

Perform I/O to a specified port
Disassemble and execute instructions
Single-step execution of instructions
Define and examine symbols in a program

Ib~;?II---, ~ HOST (INTELLEC")-

TARGET (isec" 386/2X)
DEVELOPMENT
ENVIRONMENT

IXlCUMENTATKlN
AND SERIAL CABLES

INTELLECI!!> SERIES III. IV

L - STARTER KIT -----1

USER SUPPLIED

---.J
280602-4

Figure 3. iRMX® Starter Kit Development Environments

3-132

iSBC® 386/21/22/24/28 AND 386/31/32/34/38

guages and tools including ASM 86, ASM 286, PLIM
286, BINO 286, BUILO 286, and AEOIT text editor.
Thirty-two-bit languages are not supported.

On-Target Debug with the DMON
386020-Based iSBC 386/2x and 3x
Starter Kits

The starter kit also allows deSigners to download all
or part of an existing iRMX 286-based application to
the iSBC 386/2x and 3x boards for execution. In
some cases, software timing loops may need to be
readjusted to compensate for the increased clock
rate of the 80386 microprocessor. Furthermore, I/O
address references may also need changing to
match the I/O map of the iSBC 386/2x and 3x
boards.

The OMaN 386-Based starter kits use the un hosted
OMaN 386020 Oebug Monitor, which is intended for
debugging embedded, 32-bit code. Once the user
has either downloaded their code (using their own
bootstrap loader) to the iSBC 386/2x and 3x board's
ORAM memory, or programmed their code in
EPROMs and plugged them in the iSBC 386/2x's
and 3x's sockets, OMaN may be used to fully debug
the code, including any code using the 80386's 32bit OMF (object module format).
.

iRMX 86-based 8086 applications will also run on
the iSBC 386/2x and 3x boards under the iRMX 86
operating system or under the iRMX 286 operating
system included in the starter kit. To run them under
the iRMX 286 operating system, the code is first recompiled using 286 compilers. The code is then
downloaded to the iSBC 386/2x and 3x boards using the monitor software. As with other code, the
iRMX 86 application code may have to be modified
to adjust software timing loops and I/O address references.

The OMaN 386020 portion of the OMaN-based
starter kits provides OMaN in two 27512 EPROMs,
ready for use immediately in an iSBC 386/2x and 3x
board, and in a 51;4" diskette, for integration with
other, user-supplied code. Complete documentation
is also included.
The OMaN 386020 monitor provides the following
.
debug capabilities:
• Examine/modify memory, I/O ports, processor
registers, descriptor tables, and the task state
segment

Configuring the On-Target
Development Environment

• Evaluate expression
• Control execution both in real and protected
mode
• Set software breakpoints on execution addresses
• Set hardware breakpoints on execution and data
addresses

If the deSigner chooses to configure an on-target
development environment using an Intel 286/310
system, either a standard SYS 31 0-40(A), -41 (A), or
-17(A) system may be used.
In addition to the iSBC 386/2x and 3x boards and
memory, other boards that theiRMX 286 software
supports may be installed in the system. These
boards include the iSBC 214/215G/217/218A series of disk controller boards, the iSBC 188/48 and
iSBC 544A 8- and 4-channel communications
boards, the iSBC 350 line printer board, the iSBX
351 2-channel communications MULTIMOOULETM
and a RAM (disk) driver, and many more.

HOST

• Oisassemble instructions
The OMaN 386020 based starter kit does not provide operating system (O.S.) support. If the applica. tion software uses an O.S. interface, the O.S. must
be ported to run with the 80386 microprocessor, the
8251A Serial Controller, and the 80387 math coprocessor (if used).

DOWNLOAD

_ _ _ _-::-:;:::::;-;==;:;;-_ _ _ _••

DEVELOPSfW

(USER SUPPLIED)

I TARGET
EXECUTE CODE

AND DEBUG
DOCUMENTATION

ISBCoI'J aQS/2X and 3X

CPU

INTELLECill> SERIES III. IV

L-.,...-_ _ _ USER SUPPLIED - - - - - '

L _____

STARTER KIT - - - - - - ' 280602-5

Figure 4. D-MON386ES Target Development Environment

3-133

inter
Syst~m

iSBC® 386/21/22/24/28 AND 386/31/32/34/38

Compatibility

The iSBC 386/2x and 3x Single Board Computers
are complemented by a wide range of MULTIBUS
hardware and software products from over 200 manufacturers worldwide. This product support enables
the designer to easily· and quickly incorporate the
iSBC 386/2x boards into his system design to satisfy
a wide range of high performance applications.
.
Applications that use other 8- and 16-bit MULTIBUS
single board computers (such as Intel's iSBC
286/10A and iSBC 286/12 8 MHz, 80286 based single board computers) can be upgrad~d to use the
iSBC 386/2x and 3x boards. Changes'to hardware
and systems software (fo~ speed and 1/0 configuration dependent code) may be required.

EPROM Memory
Number of sockets-Two 32-pin JEDEC Sites (compatible with 28-pin and 32-pin devices)
Sizes accommodate~4 kb (8k x 8), 128 kb (1'6k x
8), 256 kb (32k x 8), 512 kb (64k x 8), 1 Mb (128k x
8), 2 Mb (256k x 8)
Device access speeds-130 ns to 320 ns
Maximum memory-512k bytes with 27020 (2M bit)
EPROMs

1/0 Capability

BOARD SPECIFICATIONS

Serial Channel

Word Size

Type-One RS232C DTE asynchronous channel using an 8251A device

Instruction--8, 16, 24, 32 or 40 bits
Data--8, 16, 32 bits
System Clock
80386 CPU-16 MHz or 20 MHz
Numeric Processor--80387 module-16 MHz or
20 MHz

Data Characteristics-5-8 bit characters; break
character generation; 1, 1%, or 2 stop bits; false
start bit detection; automatic break detect and handling; evenlodd parity error generation and detection
Speed-110, 150, 300, 600, 1.2 kb, -2.4 kb, 4.8 kb,
9.6 kb, 19.2 kb

Cycle Time
Basic
Instruction:
iSBC
386/21/22/24/28,
16 MHz-125 ns
iSBC 386/31/32/34/38, 20 MHz-100 ns (assumes
instruction in queue)
NOTE:
Basic instruction cycle is. defined as the fastest instruction time (i.e. two clock cycles)

Leads supported-TO, RD, RTS, CTS DSR, RI, CD,

SG
Connector Type-10 pin ribbon

Expansion-One 8/16-bit iSBX interface connector
for single or double wide iSBX MULTIMODULE
board.
Interrupt Capacity

DRAM Memory
On-board parity memory
iSBC 386/21/31 board-1M
iSBC 386/22/32 board-:-2M
iSBC 386/24/34 board-4M
iSBC 386/28/38 board--8M

Maximum Addressable Physical Memory-16 Megabytes (protected virtual address mode) 1 Megabyte
(real address mode)

byte
bytes
bytes
bytes

Memory expansion-One additonal plug-in module:
iSBC MM01-1M byte
iSBC MM02-2M bytes
iSBC MM04-4M bytes
iSBC MM08--8M bytes

Potential Interrupt Sources-21 (2 fixed, 19 jumper
selectable)
Interrupt Levels-16 using two 8259A devices and
the 80386 NMIline
Timers
Quality-Two programmable timers using one 8274
device
Input Frequency-1.23 MHz ± 0.1 %

3-134

ISBC® 386/21/22/24/28 AND 386/31/32/34/38

Output Frequencies/Timing Intervals ,
Single Counter

Function
Real-time interrupt
Rate Generator
Square-wave rate generator
Software triggered strobe

Min

Max

1.63 JLs
18.8 Hz
18.8 Hz
1.63 JLs

53.3 ms
615 kHz
615 kHz
53.3 ms

Interfaces
MULTIBUS Bus-All signals TTL compatible
iSBX Bus-All signals TTL compatible
Serial 1I0-:RS 232C, DTE
MULTIBUS® DRIVERS

Recommended Minimum Cardcage Slot Spacing
1.2 in. (3.0 cm), with or without iSBX
MULTIMODULE
1.8 in. (4.6 cm), with addded iSBC MMOx memory
module
Approximate Weight
26 oz. (738 gm)
29 oz. (823 gm), with added iSBC MMOx memory
module

Reference Manual
149094-iSBC 386/21/22/24/28 Hardware Reference Manual (order separately)

Ordering Information

Function

Type

Sink Current (mA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
Open Collector

64
24
32
16/32

Part Number Description
CPU Boards
SBC38621
SBC38622
SBC38624

Power Requirements
iSBC 386/2x and 3x boards
Maximum: +5V, 12.5A
±12V, 35 rnA
Typical:
+ 5V, 9A
±12V, 20 rnA
NOTE:
Does not include power for iSBX module, EPROM
memory, or added iSBCMMOx memory modules.
Add the following power when adding iSBC MMOX
memory modules:
iSBC MM01
MM02
MM04
MM08

+5V,O.71A
+ 5V, 0.96A
+5V,O.71A
+ 5V, 0.96A

Environmental Requirements
Operating Temperature-O·C to 60·C at 300 LFM
Relative Humidity-O% to 85% noncondensing
Storage Temperature--40·C to + 70·C

SBC38628
SBC38631
SBC38632
SBC38634
SBC38638

16 MHz 80386
Board with 1 MB
16 MHz 80386
Board with 2 MB
16 MHz 80386
Board with 4 MB
16 MHz 80386
BOard with 8 MB
20 MHz 80386
Board with 1 MB
20 MHz 80386
Board with 2 MB
20 MHz 80386
Board with 4 MB
20 MHz 80386
Board with 8 MB

MULTIBUS I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory
MULTIBUS"I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory
MULTIBUS I CPU
DRAM Memory

Memory Modules
SBCMM01
1 MB Parity DRAM Memory Expansion Module
SBCMM022 MB Parity DRAM Memory Expansion Module
SBCMM04
4 MB Parity DRAM Memory Expansion Module
SBCMM08
8 MB Parity DRAM Memory Expansion Module

Physical Characteristics
Dimensions
Width-12.00 in. (30.48 cm)
Height-7.05 in. (17.91 cm)
Depth-0.86 in. (2.18 cm), 1.62 in. (4.11 cm) with
'added memory module
3-135

iSBC® 386/21/22/24/28 AND 386/31/32/34/38

Starter Kits
SBC38621 SPKG

SBC38621 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
.

Starter Kits
SBC38631SPKG

SBC38631 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38631SPKGR2 SBC38631 plus iRMX 286 R.2.
O.S;, Monitor, Training, Documentation, and Discount on
tools.
SBC38632SPKG
SBC38632 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38632SPKGR2 SBC38632 plus iRMX 286 R.2.
O.S., Monitor, Training, Docu~
mentation, and Discount on
tools.
SBC38634SPKG
SBC38634 plusDMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38634SPKGR2 SBC38634 plus iRMX 286 R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38638SPKG
SBC38638 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38638SPKR2 SBC38638 plus iRMX 286 R.2.
O.S. Monitor, Training, Documentation and Discount on
tools.

SBC38621SPKGR2 SBC38621 plus iRMX 286 R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38622SPKG
SBC38622 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38622SPKGR2 SBC38622 plus iRMX 286 R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38624SPKG
SBC38624 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38624SPKGR2 SBC38624 plus iRMX 286 R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38628SPKG
SBC38628 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
DMON386020
Debug Monitor provided in two
media, both in EPROMs for immediate use in the iSBC
386/2x board, and in a 5%"
diskette. Also includes documentation.
SBC38628SPKR2 SBC38628 plus iRMX 286 R.2.
O.S. Monitor, Training, Documentation and Discount on
tools.
Mating Connectors
Vendor Part
No. of Centers Connector
Vendor
Function
Pins
(in)
Type
Number
iSBX Bus
44
0.1
Soldered
Viking
000293-0001
Connector
Flat Crimp
3M
3399-6010
Serial RS232C
10
0.1
Connector
P2 Interface
60
0.1
RF30-2803-5
Kel-AM
Flat Crimp
Edge Connector
T&B Ansley
A3020

3-136

MULTIBUS® II Single
Board Computers

iSBC® 186/100 MULTIBUS® II
SINGLE BOARD COMPUTER
•

8.0 MHz 80186 Microprocessor with
Optional High Speed 8087-1 Numeric
Data Coprocessor

•

Optional 82258 Advanced DMA
'Controller Providing Four Additional
High Peformance DMA Channels

•

On-Board 512K Bytes DRAM
Conflgurable as Dual Port Memory

•

MPC (Message Passing Coprocessor)
Single Chip Interface to the Parallel
System Bus with Full Message Passing
Capability

•

Four (Expandable to Eight) 28-Pin
JEDEC Sites for PROM, EPROM, or
EEPROM

•

24 Programmable 1/0 Lines
Conflgurable as SCSI Interface,
Centronics Interface, or General
Purpose 1/0

•

Two Programmable Serial Interfaces,
One RS 232C and the Other RS 422A
with Multidrop Capabilities

•

Resident Firmware Supporting a Reset
Operating Ssytem, a Program Table,
_and Build-In-Self-Test (BIST)
Diagnostics Including Initialization and
Power-Up Tests

•

8- or 16-bit iSBXTM IEEE P959 Interface
Connector with DMA Support for 1/0
Expansion

The iSBC 186/100 Single Board Computer is a member of Intel's family of microcomputer modules that
utilizes the advanced features of the MULTIBUS® II system architecture. The 80186-based CPU board takes
advantage of VLSI technology to provide economical, off-the-shelf, computer based solutions for OEM applications. All features of the iSBC 186/100 board, including the single chip bus interface (message passing
coprocessor), reside on a 220mm x 233mm (8.7 inches x 9.2 inches) Eurocard printed circuit board and
provide a complete microcomputer system. The iSBC 186/100 board takes full advantage of the MULTIBUS II
bus architecture and can provide a high performance single CPU system or a powerful element for a highly
integrated multi-processing application.

280263-1

'IBM is a registered trademark of International Business Machines

4-1

September 1986
Order Number: 280263·001

intJ

iSBC® 186/100 MULTIBUS BOARD

memory and the bus interface (see Table 1). With
the addition of an Advanced DMA (ADMA) 82258
controller, ADMA requests may be generated by either the iSBX interface, the SCSI interface, the bus
interface controller, or the serial interface (see Table
2). The addition of the ADMA controller also allows
the serial ports to be used in a full-or half-duplex
.
multidrop application.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 186/100 MULTIBUS II Single Board Computer utilizes the 8 MHz 80186 microprocessor to
provide a range of solutions for various low cost
OEM and end-user applications. Intel's commitment
to offering high performance at a cost effective level
are evident in the design of the iSBC 186/100 Single
Board Computer. The integration of the functions of
a general purpose system (CPU, memory, 1/0 and
peripheral control) into a single board computer imply that the total system's board count, power and
space requirements, and costs are reduced. Combining these cost advantages with the advanced features of the MULTIBUS II system architecture, the
iSBC 1286/100 board is ideal for price sensitive
MULTIBUS II multi-processing or single CPU applications. Some of the advanced featues of the MULTIBUS II architecture embodied in the iSBC 186/100
board are distributed arbitration, virtual interrupt capabilities, message passing, iPSB bus parity, and
softwareconfigurability and diagnostics using interconnect address space.

An additional high performance 8087-1 Numeric
Data Coprocessor may be installed by the user to
significantly improve the iSBC 186/100 board's numerical processing power. Depending on the application, the high speed 8087-1 will increase the performance of floating point calculations by 50 t01 00
times.
Table 1. Basic DMA Configuration

80186

Local Bus

DMA Channel 0

Output DMA iPSB Bus
Interface
Input DMA iPSB Bus
Interface

DMA Channel 1

Memory Subsystem
Architecture
The iSBC 186/100 CPU board supports the iPSB
bus features of interconnect address space, Built-InSelf-Test (BIST) diagnostics, solicited and unsolicited message passing, and memory and 1/0 references. In addition to supporting the iPSB bus architecture, other functions traditionally found on Intel
single board computers are included in the iSBC
186/100 board. These traditional capabilities include
iSBX bus expansion, high speed 8087-1 numeric coprocessor, advanced DMA control, JEDEC memory
site expansion, SCSI, Centronics, or general purpose configurable parallel 1/0 interface, serial 1/0,
and programmable timers on the 808186 microprocessor. Figure 1 shows the iSBC 186/100 board
block diagram.

Central Processing Unit and DMA
The 80186 is an 8.0 MHz 16-bit microprocessor
combining several common system components
onto a single chip (Le., two Direct Memory Access
lines, three Interval Timers, Clock Generator, and
Programmable Interrupt Controller). The 80186 instruction set is a superset of the 8086 and maintains
object code compatiblity while adding additional instructions.

The 1M byte memory space of the 80186 is divided
into three main sections. The first section is the
512K bytes of installed DRAM, the second section is
the window into the global 4G bytes memory space
of the iPSB bus (iPSV memory window address
space) which starts at 512K bytes and goes up to
either 640K bytes or 768K bytes, and the third section is designated for local ROM going from the endingaddress of the iPSB memory window address
space up to, if desired, 1M byte (see Figure 2).
The iSBC 186/100 board comes with 512K bytes of
DRAM installed on the board. This memory can be
used as either on-board RAM or Dual Port RAM by
, loading the start and end addresses into the appropriate interconnect registers. The lower boundary
address to the iPSB memory window may begin at
any 64K byte boundary and the upper boundary address may end at any 64K byte boundary. Refer to
the iSBC 186/100 Single Board Computer User's
Guide for specific information on programming address spaces into interconnect registers.
The memory subsystem supports 128K bytes or
256K bytes access to the iPSB memory address
space. The iPSB memory window base address is
fixed at address 512K. The position of the window in
the iPSB memory address space is programmable
and thus allows the CPU to access the complete 4G
byte memory address space of the MULTIBUS II
iPSB bus.

In the basic configuration, Direct Memory Access
(DMA) requests are available between the local
4-2

iSBC® 186/100 MULTIBUS BOARD

CHANNELB

CHANNEL A

RS232
INTERFACE

ISBX'·
. INTERFACE

PROGRAMMABLE
PERIPHERAL
CONTROLLER
(8255AI

SERIAL
COMMUNICATION
CONTROLLER
(825301

INTERRUPT
CONTROL
(21 8259AI

8087·1
NUMERIC DATA
COPROCESSOR
(OPTIONALI

MULTI BUS· "PARALLEL SYSTEM BUS
280263-2

Figure 1. iSBC® 186/100 CPU Board Block Diagram
The ROM space consists of four 28-pin JEDEC
sockets which take EPROMs, EEPROMs or ROMs
with 28-pin packages. An iSBC 341 28-pin MULTIMODULETM EPROM board can be plugged into 2 of
the JEDEC sockets and provide up to 512K bytes of
ROM memory. Device capacities, which are jumper
selectable, are supported from 8K x 8 up to 64K x 8.
Once the device capacity is selected, the capacity is
uniform for all sockets.

On-Board Local Functions
PROGRAMMABLE TIMERS AND INTERRUPT
CONTROL
The 80186 microprocessor on the iSBC 186/100
board provides three independent, fully programmable 16-bit interval timers/event counters. In conjunction, two 8259A Programmable Interrupt Controllers
(PIC) on the iSBC 186/100 board are used in a master/slave configuration for processing on-board interrupts. At shipment, the 80186 interrupt controller
and one PIC are connected as slaves to the master
PIC. The first timer on the 80186 microprocessor is
routed to the master Programmable Interrupt Controller and the second CPU timer is routed to the
slave PIC. This architecture thus supports software

I/O access from the iSBC 186/100 CPU board
across the iPSB bus is accomplished by mapping
64K bytes of local I/O access one to. one to the
iPSB I/O address space. However, only the upper
32K bytes are available to access the iPSB I/O address space because the lower 32K bytes on the
iSBC 186/100 board are reserved for local on-board
I/O.

4-3

intJ

iSBC® 186/100 MULTIBUS BOARD

Table 2 DMA Configuration with ADMA Option
Local Bus
Serial Channel B DMA
Serial Channel B DMA or Parallel Port

80186
DMA Channel 0
DMA Channel 1
ADMA82258
DMA Channel 0
DMA Channel 1
DMA Channel 2

Input DMA Bus Interface
Output DMA Bus Interface
Half-duplex Fast Serial Interconnect 1
Channel A or Interrupt 1 from iSBX Bus if Used with an iSBC 341
EPROM MULTIMODULE Board
Full-duplex Fast Serial Interconnect 1
Channel A or iSBX Bus DMA Channel if Used with an iSBC 341 .
EPROM MULTIMODULE board.

DMA Channel 3

NOTE:
When a MULTIMODULETM expansion board is installed and DMA support is required, then an ADMA controller must also be
installed. For additional optional configurations see the iSBC 1861100 Single Board Computer User's Guide.

IPSB
MEMORY
MAP

D~~
MB II .
MEMORY

1024K

ISBC'"
186/100
MEMORY
MAP
ON·
BOARD
EPROM

768K

BASE ADDRESS IS ANY
MULTIPLE OF 128K OR 256K
(SIZE OF MULTIPLE = WINDOW SIZE)

---+----1

IPSB
MAYBE
WINDOW
640K ~
512K

......
ON- ..
BOARD
DRAM

MBII
WINDOW

BASE ADDRESS IS ANY
MULTIPLE OF 64K
512KB

./
280263-3

Figure 2. Memory Mapping Diagram

4-4

inter

iSBC® 186/100 MULTIBUS BOARD

The Centronics interface requires very little software
overhead since a user supplied PAL device is used
to provide necessary handshake timing. Interrupts
are generated for printer fault conditions and a DMA
request is issued for every character.

programmable timer interrupts. In addition, directvectored interrupt capability of the serial communication controller (SCC) may be used. Figure 3 depicts the interrupts in terms of their priorities.
Interrupt Services
80186 Timer 0
8087-1 Error Interrupt
Message Interrupt
iPSB Bus Error Interrupt
82530 SCC Interrupt
82258 ADMA Interrupt
80186 Slave PIC Interrupt
8259 Slave PIC Interrupt
PPI 0 Interrupt
iSBX Bus Interrupt 0
iSBX Bus Interrupt 1
Interconnect Space Interrupt
80186 Timer 1 Interrupt
PPI 1 Interrupt
Ground

Interrupt Priority
Master Level 0
1
2
3
4
5
6
7

SERIAL I/O LINES
The iSBC 186/100 board has one 82530 Serial
Communciations Controller (SCC) to provide 2 channels of serial 1/0. The SCC generates all baud rate
clocks and provides loopback capability on both
channels. Channel A is configured for RS 422A multidrop DTE application. Channel B is RS 232C only
and is configured as DTE.

Slave 0
1
2
3
4
5
6&7

The multidrop configuration may either full-or halfduplex. A full-duplex multidrop configuration with a
single master driving the output lines allow a slave to
monitor the data line and to perform tasks in parallel
with tasks performed on another slave. However,
only the selected slave may transmit to the master.
A half-duplex multidrop configuration is more strict in
its protocol. Two data lines and a ground line are
required between a master and all slaves in the system and although all units may listen to whomever is
using the data line, the system software protocol
must be designed to allow only one unit to transmit
at any given instant.

Figure 3. ISBC® 186/10 Interrupt Priority Scheme

PARALLEL/SCSI PERIPHERAL
INTERFACE
The iSBC 186/100 board includes an 8255A parallel
peripheral interface that consists of three 8-bit parallel ports. As shipped, these ports are configured for
general purpose 1/0. Programmed PAL devices
(Programmable Array Logic) and the bi-directional
octal transceiver 74LS245 are provided to make it
easy to reconfigure the parallel interface to be compatible with the SCSI (Small Computer System Interconnect) peripheral interface. Alternatively, the iSBC
186/100 board provides the jumper configuration facilities for operating the parallel interface as an interrupt driven interface for a Centronics compatible line
printer by adding one PAL and reconfiguring jumpers. Both interfaces may use the 82258 DMA controller for data transfers if desired.

BUILT-IN-SELF-TEST DIAGNOSTICS
On-board built-in-self-test (BIST) diagnostics are implemented using the 8751 microcontroller and the
80186 microprocessor. On-board tests include ini~
tialization tests on DRAM, EPROM, the 80186 microcontroller, and power-up tests. Additional activities performed include a Reset Operating System
initialization at power-up and a program table check,
a feature allowing users to add custom code in
EPROM while still maintaining full uSe of the factory
supplied BISTs.
Immediately after power-up and the 8751 microcontroller is intialized, the 80186 microprocessor begins
its own initialization and on-board diagnostics. Upon
successful completion of these activities, the Reset
Operation System invokes the user-defined program
table. A check is made of the program table and the
custom programs that the user has defined for his
application will then execute sequentially.

The SCSI interface allows multiple mass storage peripherals such as Winchester disk drives, floppy disk
drives, and tape drives to be connected directly to
the iSBC 186/100 board. A sample SCSI application
is shown in Figure 4. The SCSI interface is compatible with SCSI controllers such as Adaptek 4500,
DTC 1410, Iomega Alpha 10, Shugart 1601 and
1610, Vermont Research 8403, and Xebec 1410.

4-5

intJ

ISBC® 186/100 MULTIBUS BOARD

SCSI BUS

ISBC" 1861100
BOARD

MULTIBUS" II PARALLEL SYSTEM BUS
280263-4

Figure 4. SCSI Application
BISTs improve the reliability, error reporting, and re, covery capability of MULTIBUS II boards. In addition,
these test and diagnostics reduce ma.,ufacturing
and maintenance' costs for the user. A yellow LED
(labeled 'BIST') on the front panel indicates the
status of the initialization checks and the power-up
tests. It is illuminated if any of the initialization
checks fail and remains off if the board successfully
completes its tests. The LED also illuminates when
the BIST tests start and stays on until the test complete successfully. The results of the BIST diagnostics are stored in the last 6 registers of the Header
Record in Interconnect space.

and independent hardware vendors. Custom iSBX
bus MULTIMODULE boards designed for MULTIBUS or proprietary bus systems are also supported
as long as the IEEE P959 iSBX bus specification is
followed.
IPSB BUS INTERFACE SILICON
The MPC (message passing coprocessor) provides
all necessary iPSB bus interface logic on a single
chip. Services provided by the MPC include memory
and 1/0 access to the iPSB by the 80186 processor,
bus arbitration, exception cycle protocols, and transfers as well as full message passing support. Dual
port architecture may be implemented using the
message passing coprocessor.

ISBXTM BUS MULTIMODULETM
EXPANSION
One 8-or 16-bit iSBX bus MULTIMODULEconnector
is provided for 1/0 expansion. The iSBC 186/100
board supports both 8-bit and 16-bit iSBX modules
through this connector. DMA is also supported to .
the iSBX connector and can be configured by programming the DMA multiplexor attached to the
82258 DMA component. The iSBX connector on the
iSBC 186/100 board supports a wide variety of standard MULTIMODULE boards available from Intel

Interconnect Subsystem
The interconnect subsystem is one of the four MUL. TIBUS II address spaces, the other three b~ing
memory space, 1/0 space, and message space. The
purpose of interconnect space is to allow software
to initialize, identify, configure, and diagnose the
boards in a MULTIBUS II system. All Intel MULTIBUS II boards support interconnect space.

4-6

inter

ISBCIIl> 186/100 MULTIBUS BOARD

The interconnect space is organized into a group of
8-bit registers called a template. The interconnect
registers are organized into functional groups called
records. Each register belongs to only one record,
and there are three basic types of interconnect records: a header record, a function record, and an End
of Template (EOT) record. The 80186 on the iSBC
186/100 board accesses its own template via the
interconnect address space on the iPSB bus.

Cycle Time
BASIC INSTRUCTION: 8.0 MHz - 500 ns for minimum code read

Memory Capacity
LOCAL MEMORY

The header record provides board and vendor ID
information, general status and control information,
and diagnostic status and control information. The
function record contains parameters needed to perform specific functions for the board. For example,
an iPSB memory record contains registers that define the start and end address of memory for access
across the iPSB bus. The number of function records in a template is determined by the manufacturer. The EOT record simply indicates the end of the
interconnect template.

NUMBER OF SOCKETS: four 28-pin JEDEC sites
Memory
Capacity
8K
16K
32K
64K

EPROM
EPROM
EPROM
EPROM

Chip Example

x8
x8
x8
x8

2764
27128
27256
27512

ON·BOARD flAM
There are two types of registers in the MULTIBUS II
interconnect space, read-only and software configurable registers. Read-only registers are used to hold
information such as board type, vendor, firmware
level, etc. Software configurable registers allow read
and write operations under software control and are
used for auto-software configurability and remote/
local diagnostics and testing. A software monitor
can be used to dynamically change bus memory
sizes, disable or enable on-board resources such as
PROM or JEDEC sites, read if the iSBX bus or
PROM are installed as well as access the results of
Built-In-Self-Tests or user installed diagnostics.
Many of the interconnect registers on the iSBC
186/100 board perform functions traditionally done
by jumper stakes. Interconnect space support is implemented with the 8751 microcontroller and iPSB
bus interface logic.

512K bytes 64K

x 4 bit Dynamic RAM

110 Capability
Serial:
-

Channel A: RS 422A with DTE multidrop capability

Channel B: RS 232C compatible, configured as
DTE
Parallel:· SCSI, Centronics, or general purpose
I/O

SPECIFICATIONS

Two programmable channels using one 82530
Serial Communications Controller
19.2K baud rate maximum in full duplex in asynchronous mode or 1 megabit per second in full
duplex in synchronous mode

Expansion: One 8-or 16-bit IEEE P959 iSBX
MULTIMODULE board connector supporting
DMA

Word Size

Serial Communications Characteristics

INSTRUCTION: 8-, 16-, 24-, 32-, or 40-bits
DATA: 8-or 16-bits

ASYNCHRONOUS MODES:
,. 19.2K baud rate maximum in full duplex

System Clock

• 5-8-bit character; odd, even, or parity; 1, 1.5, or 2
stops bits

CPU: 8.0 MHz

• Independent transmit and receive clocks, 1X,
16X, 32X, or 64X programmable sampling rate

NUMERIC COPROCESSOR: 8.0 MHz (part number

• Error detection: Framing, Overrun, and Parity

8087-1)

• Break detection and generation

4-7

inter

iSBC® 186/100 MULTIBUS BOARD

BIT SYNCHRONOUS MODES:
• 1 megabit per second maximum in full duplex

ISBX BUS:

As per IEEE P959 specification

• SOLC/HOLC flag generation and recognition
• Automatic zero bit insertion and detection

CONNECTORS

• Automatic CRC generation and detection (CRC
16 or CCID)

Location

• Abort generation and detection
• I-field residue handling

Function
iPSB Bus

Part #
603-2-1 EC-C096-F

Physical Dimensions

• SOLC loop mode operation
• CCID X.25 compatible

The iSBC 186/100 board meets all MULTIBUS II
mechanical specifications as presented in theMULTIBUS II specification (# 146077)

BYTE SYNCHRONOUS MODES:
• Internal or external character. synchronization (1
or 2 characters)

DOUBLE-HIGH EUROCARD FORM FACTOR:

• Automatic CRC generation and checking (CRC
16 or CCID)

Depth:

220 mm (8.7 in.)

233 mm (9.2 in.)
Height:
Front Panel Width: 20 mm (0.784 in.)
Weight:
743 g (26 oz.)

• IBM Bisync compatible

Timers
Three programmable timers on the 80186 microprocessor

Environmental Requirements
Temperature: Inlet air at 200 LFM ~irflow over all
boards
Non-operating: ~ 40· to + 70·C
Operating: o· to + 55·C .

INPUT FREQUENCIES:

Frequencies supplied by the internal 80186 16 MHz
crystal
Serial chips:
crystal driver at 9.8304 MHz divide
by two
iSBX connector: 9.8304 crystal driven an 9.8304
MHz

Humidity:

Non-operating: 95% RH @55·C, noncondensing
Operating: 90% RH @ 55·C, non-condensing

Electrical Characteristics

Interrupt Capacity

The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
or expansion modules.

POTENTIAL INTERRUPT SOURCES:

255 individual and 1 broadcast
INTERRUPT LEVELS:

12 vectored requests using two 8259As, 3 grounded
inputs, and 1 input to the master PIC from the slave
PIC
INTERRUPT REQUESTS:

All signals DL compatible INTERFACES
IPSB BUS:

As per MULTIBUS II bus architecture specification
4-8

Voltage
(Volts)

Max Current
(Amps)

Max Power
(Watts)

+5
+12
-12

6.5 rnA
50 rnA
50 rnA

34.13W
0.06W
0.06W

iSBC® 186/100 MULTIBUS BOARD

Reference Manuals

ORDERING INFORMATION

iSBC 186/100 Single Board Computer User's Guide
(#148732-001)

SBC186100

Part Number Description
MULTIBUS II 80186-based Single
Board Computer

Intel MULTIBUS II Bus Architecture Specification
(#146077)
Manuals may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature
Department, 3065 Bowers Avenue, Santa Clara, CA,
95051.

4-9

iSBC® 286/100A MULTIBUS®II
SINGLE BOARD COMPUTER

•

8 MHz 80286 Microprocessor with·
Optional 80287 Numeric Data
Co-Processor

•

MULTIBUS® II iPSB (Parallel System
Bus) Interface with Full Message
Passing Capabilities and up to 4
Gigabytes of Memory Addressability on
the Bus

•
•
•

•
•

MULTIBUS® II Interconnect Space for
Software Configurability and Self-Test
Diagnostics

•
•
•

Two Programmable Serial Interfaces,
one RS232C (DCE or DTE), the other
RS232C or RE422A/RS449 Compatible

High-Speed Memory Expansion with
MULTIBUS II iLBX II (Local Bus
Extension) .Interface Addresses up to
16 MBytes of Local and/or Dual Port
Memory
Two iSBX Bus Interface Connectors for
I/O Expansion Bus
Four DMA Channels Supplied by the
82258 Advanced DMA Controller with 8
MBytes/sec Transfer Rate

Resident Firmware Supports Self-Test
Power-Up Diagnostics and OnCommand Extended Self-Test
Diagnostics

Two 28-pin JEDEC Sites for up to 128
KBytes of Local Memory Using SRAM,
NVRAM, EEPROM, and EPROM
24 Programmable I/O Lines
Configurable as SCSI Interface,
Centronics Interface, or General
Purpose I/O

The iSBC 286/100A Single Board Computer is part of Intel's family of MULTIBUS II CPU boards that utilizes
the advanced features of the MULTIBUS II System Architecture. It is ideally suited for a wide range of OEM
applications. The combination of the 80286 CPU, the Message Passing Coprocessor (MPC), the MULTIBUS II
Parallel System Bus (iPSB bus), and the Local Bus Extension (iLBX II bus) makes the iSBC 286/100A board
suited for high performance, multiprocessing system applications in a multimaster environment. The board is a
complete microcomputer system on a 220mm x 233rnm (8.7 x 9.2 inch) Eurocard form factor with pin and
socket DIN connectors.

280076-1

4-10

March 1987
Order Number: 280076-004

inter

iSBC® 286/100A MULTIBUS® II

Overview

Architecture

The iSBC 286/100A Single Board Computer combines the 80286 microprocessor with the Message
Passing Component (MPC) on a single board within
the MULTIBUS II system architecture. This offers a
message passing based high performance multiprocessing solution for system integrators and designers. Figure 1 shows a typical MULTIBUS II multiprocessing system configuration. Overall system performance is enhanced by the Local Bus Extension
(iLBX II) which allows 0 wait state high speed memory execution.

All features of the MULTIBUS II architecture are fully
supported by the iSBC 286/100A board including
the Parallel System Bus (iPSB), interconnect space,
Built-In-Self-Tests (BIST) diagnostics, and full message passing. These features are described in the
following sections. In addition to taking advantage of
the MULTlBUS II system architecture, the iSBC
286/100A board has complete single board computer capability including two iSBX bus expansion connectors, 80287 numeric data coprocessor option,
advanced DMA control, JEDEC' memory ,sites,
SCSI configurable parallel interface, serial I/O, ,and
programmable timers. Figure 2 shows the iSBC
286/100A board block diagram.

280076-2

F,lgure 1. Typical MULTIBUS®U Multiprocessing System Configuration

MUI.TIIIUS" • PARALLEL SYSTEII BUS

280076-3

Figure 2.ISBC® 286/100A Board Block Diagram

4-11

inter

iSBC® 286/100A MULTIBUS® II

tween agents on the iPSB bus. The arrival of a solicited message is negotiated between the sending
and receiving agents. Data is sent in "packets" with
each packet containing four bytes of control information and up to 28 bytes of data. There is no specific limit to the· number of packets that may be sent
in a single message, but the total.message may not
transfer more than 16 Mbytes.

Central Processing Unit
The central processing unit for the iSBC 286/100A
board is the 80286 microprocessor operating at
8.0 MHz clock rate. The 80286 runs 8086 and 80186
code at substantially higher speeds (due to a parallel
chip architecture) while maintaining software compatibility with Intel's 8086 and 80186 microprocessors. Numeric processing power may be enhanced
with the 80287 numeric data coprocessor. The
80286 CPU operates in two modes: real address
mode and protected virtual address mode. In real
address mode, programs use real addressing with
up to one megabyte of address space. In protected
virtual address mode, the 80286 CPU automatically
maps 1 gigabyte of virtual address per task into a 16
megabyte real address space. This mode also provides the hardware memory protection for the operating system. The operating mode is selected via
CPU instructions.

The iSBC 286/100A also includes a feature called
the iPSB window register that allows the user to selectively access under software control any 256K
byte block of memory within the 4 Gigabytes of
memory space on the iPSB bus interface.

INTERCONNECT SPACE SUPPORT
Intercont:lect space is one of four MULTIBUS II address spaces, the other three being memory space,
I/O space, and message space. Interconnect space
allows software to initialize, identify, configure, and
diagnose the boards in a MULTIBUS II system. The
Interconnect template consists of 8-bit registers, organized into functional groups called records. There
are three types of records, the header record, the
function record, and the End of Template record.

iPSB Bus Interface
The iSBC 286/100A board has a Message Passing
Coprocessor (MPC) component on the base board
that contains most of the logic required to operate
the Parallel System Bus (iPSB bus) interface. Some
of the key functions provided by the MPC include
bus arbitration, transfer control, parity generation
and checking, and error detection and reporting.

The header record provides board and vendor ID
information, general status and control information,
and diagnostic control. The function record allows
the user to configure and/or read the
iSBC 286/100A board's hardware configuration via
software. The End of Template record identifies the
end of the interconnect template.

Data transfers between processors via the iPSB bus
is defined in the MULTIBUS II architecture through a
transfer protocol, a reserved address space, and an
information/data block. This interprocessor communication convention is known as message passing.
Operations occurring within the reserved address
space are called message space operations.

BUILT IN SELF TEST (BIST)
DIAGNOSTICS·
MULTIBUS II's Built in Self Test (BIST) diagnostics
improve the reliability and error reporting and recovery capability of MULTIBUS II boards. These confidence tests and diagnostics not only improve reliability but also reduce manufacturing and maintenance costs for the OEM user. A yellow LED (LED 1)
on the front panel provides a visual indication of the
power-up diagnostics status.

Message passing allows iPSB bus agents to transfer
variable amounts of data at rates approaching the
maximum bandwidth of the bus. Message passing
permits a sustained transfer rate of 2.2 Mbytes
per second, and a single message may transfer up
to 16 Mbytes from one agent to another. The MPC
fully supports message space operations, executes
iPSB bus arbitration and executes the message
paSSing protocol independent of the host CPU, leaving the host free to process other tasks.

Error Reporting and Recovery
The MPC supports both solicited and unsolicited
message passing capability across the iPSB. An unsolicited message can be thought of as an intelligent
interrupt from the perspective of the receiving agent
because the arrival of an unsolicited message is unpredictable. Attached to an unsolicited message is
one of 255 possible source addresses along with 28
bytes of data attached to the message data field. A
solicited message moves large blocks of data be-

The MULTI BUS II Parallel System Bus and the
iLBX \I bus provides bus transmission and bus parity
error detection signals. Error information is logged in
the MPC and a bus error interrupt is generated. Information on the error source for reporting or recovery purposes is available to software through· the
iSBC 286/100A board interconnect space registers.

4-12

inter

ISBC® 286/100A MULTIBUS® II

cal on-board bus including 16 data lines and DMA
for maximum data transfer rates. MULTIMODULE
boards designed with 8-bit data paths and using the
8-bit iSBX bus connectors are also supported. A
broad range of iSBX bus MULTIMODULE options
are available from Intel. Custom iSBX bus MULTIMODULE boards designed for MULTIBUS or proprietary bus systems are also supported provided the
IEEE P959 iSBX bus specification is followed.

INTERRUPT CONTROL
In a MULTIBUS II system, external interrupts (interrupts originating off the CPU board) are messages
over the bus rather than signals on individual lines.
Message based interrupts are handled by the MPC.
Two on-board 8259A Programmable Interrupt Controllers (PICs) are used for processing on-board interrupts. One is used as the master and the other as
the slave. Table 1 includes a list of devices and functions supported by. interrupts.

NUMERIC DATA CO-PROCESSOR
The 80287 Numeric Data Co-Processor can be installed on the iSBC 286/100A board by the user.
The 80287 Numeric Data Co-Processor is connected 'to dedicated processor· signal lines which are
pulled to their inactive state when the 80287 Numeric Data Co-Processor is not installed. This enables
the user to detect via software that the 80287 socket
is occupied. The 80287 Numeric Data Co-Processor
runs asynchronously to the 80286 clock. The 80287
Numeric Data Co-Processor operates at 8 MHz and
is driven by the 8284A clock generator.

iSBX® BUS MULTIMODULETM
ON-BOARD EXPANSION
Two iSBX bus MULTIMODULE connectors are provided, one 16- or 8-bit and the other 8-bit. Through
thesE3 connectors additional on-board 1/0 functions
may be added. The iSBX bus MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as. additional parallel
and serial 110, analog 1/0, and graphics control. The
iSBX bus connectors on the iSBC 286/100A board
provides all signals necessary to interface to the 10-

Table 1. Interrupt Devices and Functions
Device
MULTIBUS® II Interface

Function
Message-based Interrupt Request from the
iPSB Bus via 84120 Message Interrupt
Controller

8751 Interconnect Controller

BIST Control Functions

82530 Serial Controller

Transmit Buffer Empty, Receive Buffer
Full and Channel Errors

8254 Timers

Timers 0, 1, 2 Outputs; Function Determined
by Timer Mode

Number of Interrupts

1 Interrupt from up to
256 sources
1
1 Interrupt from
10 Sources
3

8255A Parallel 110

Parallel Port Control

iLBX II Bus Interface

Indicates iLBXTM II Bus Error Condition

iPSB Bus Interface

Indicates Transmission Error on iPSB Bus

iSBX Bus Connector

Function Determined by iSBX Bus
MULTIMODULE Board

Edge Sense Out

Converts Edge Triggered Interrupt to a Level

Bus Error

Indicates Last iPSB Bus Operation
Encountered an Error

Power-Fail

ExternallPower-Faillnterrupts

4-13

intJ

iSBC® 286/100A MULTIBUS® II

ports. As shipped, these ports are configured for
general purpose 110. Programmed PAL (Programmable Array Logic) devices and the octal transceiver
74LS640-1 are provided to make it easy to reconfigure the parallel interface to be compatible with the
SCSI (Small Computer System Interconnect) peripheral interface. Alternatively, the parallel interface
may be reconfigured as a Centronics compatible line
printer by adding one PAL and reconfiguring jumpers. Both interfaces may use the 82258 DMA controllers for data transfers.

DMA CONTROL
Four DMA (Direct Memory Access) channels are
supplied on the iSBC 286/1 OOA board by the 82258.
The 82258 is an advanced DMA controller designed
especially for the 16-bit 80286 microprocessor. It
has four DMA channels which can transfer data at
rates up to 8 Megabytes per second (8 MHz clock) in
an 80286 system. The large bandwidth allows the
user to handle very fast data transfer or a large number of concurrent peripherals.

The SCSI interface allows multiple mass storage peripherals such as Winchester disk drives, floppy disk
drives, and tape drives to be connected directly to
the iSBC 286/100A board. A sample SCSI application is shown in Figure 3. The SCSI interface is compatible with SCSI controllers such as the Adaptek
4500, DTC 1410, lomga Alpha 10, Shugart 1601 and
1610, Vermont Research 8403, and Xebec 1410.

MEMORY CAPABILITIES
The local memory of the iSBC 286/100A board consists of two groups of byte-Wide sites. The first group
of two sites are reserved for EPROM or ROM and
are used for the BIST power-up diagnostic firmware.
The second group of two sites support JEDEC standard 28-pin devices.

The Centronics interface requires very little software
overhead since a user-supplied PAL device is used
to provide necessary handshake· timing. Interrupts
are generated for printer fault conditions and a DMA
request is issued for every character.

PARALLEL PERIPHERAL INTERFACE
The iSBC 286/100A board includes a parallel peripheral interface that consists of three 8-bit parallel

SCSI BUS

sac- 211/100A
IIQAAD

MULTIBUS·' II PARALLEL SYSTEM BUS

280076-4

Figure 3. Sample SCSI Applications

4-14

iSBC® 286/100A MULTIBUS® "

SERIAL 1/0

SOFTWARE SUPPORT

The 82530 Serial Communications Controller (SCC)
is used to provide two channels of serial I/O. The
SCC generates all baud rate clocks and provides
loopback capability on both channels. Channel B is
RS232C only and is configured as a DCE. Channel A
is factory-default configured for DCE RS232C operation. Channel A may be reconfigured by the user for
DTE or RS422 operation.

The iRMX 86 Release 7 Operating System software
provides the ability to execute all configurable layers
of the iRMX 86 software in the MULTIBUS II environment. Applications in Real Address Mode are
supported for the iSBC 286/100A board, including
support for the SCSI peripheral interface and all
iSBX bus boards. The iRMX 86 Release 7 Operating
System also supports all 80286 component applications.

The 82258 ADMA can be programmed to support
both channels A and B to perform movement of
large bit streams or blocks of data.

PROGRAMMABLE TIMERS

For on-target MUL TIBUS II development, use the
iSBX 218A or a SCSI controller and a floppy or Winchester drive, or port iRMX application software developed on the System 310, Series II/III, IV to MULTlBUS II hardware.

The iSBC 286/100A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Three of these timers/
counters are available to the system designer to
generate accurate time intervals under software
control. The outputs may be independently routed to
the 8259A Programmable Interrupt Controller to
count external events. The system software configures each timer independently to select the desired
function. Seven functions are available as shown in
Table 2. The contents of each counter may be read
at any time during system operation.

Language support for the iSBC 286/100A boards
real address mode includes Intel's ASM 86,
PLiM 86, PASCAL and FORTRAN as well as many
third party 8086 languages. Language support for
virtual address mode operation includes ASM 286,
PL/M 286, PASCAL and C. Programs developed in
these languages can be down-loaded from the Intel
Series III or Series IV Development System to the
iSBC 286/100A board via the iSDM 286 System Debug Monitor Release 2. The iSBX 218A can be used
to load iRMX software developed on a System 310.
The iSDM 286 monitor also provides on-target program debugging support including breakpoint and
memory examination features.

Table 2. Programmable Time Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is reached, an interrupt request is generated. This function is
extremely useful for generation of real-time clocks.

Programmable
One-Shot

Output goes low upon request of an external trigger edge or software command and
returns high when terminal count is reached. This function is retriggerable.

Rate Generator

Divide by N counter. The output will go low for one input clock cycle, and the period
from one low going pulse to the next is N times the input clock period.

Square-Wave
Rate Generator

Output will remain high until one-half the count has been completed, and go low for
the other half of the count.

Software Triggered
Strobe

Output remains high until software loads count (N). N counts after count is loaded,
output goes low for one input clock period.

Hardware
Triggered Strobe

Output goes low for one clock period N counts after rising edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis, the clock input becomes an input from the external
system. CPU may read the number of events occurring after the counter "window"
has been enabled or an interrupt may be generated after N events occur in the
system.

4-15

intJ

iSBC® 286/100A MULTIBUS® II

The MULTIBUS II Interconnect Space Registers allow the software to configure boards eliminating
much of the need for jumpers and wire wraps. The
is OM 286. Monitor can initialize these registers at
configuration time using user-defined variables. The
monitor can also automatically configure memory
boards, defining the addresses for each board sequentially in relation to the board's physical placement in the card cage. This feature allows for swapping, adding, and deleting of memory boards on a
dynamic basis.

1/0 CAPABILITY
Parallel:

SCSI, Centronics, or general purpose
1/0

Serial:

Two programmable channels using one
82530 Serial Communications Controller
Timers:
Three programmable timers using one
8254 Programmable Interrupt Controller
Expansion: One 8/16-bitiSBX MULTIMODULE
connector and one 8-bit iSBX MULTIMODULE connector

SPECIFICATIONS
INTERRUPT CAPABILITY
WORD SIZE

Potential Interrupt Sources-255 individual and 1
broadcast
Interrupt Levels
- 16 vectored requests
using two 8259As and
the 80286 NMI line

Instruction- 8-, 16-, 24-, 32-, or 40-bits
Data
- 8- or 16-bits
SYSTEM CLOCK

CPU
-8.0 MHz
Numeric Co-Processor~ 8.0 MHz

Serial Communications Characteristics

CYCLE TIME

Basic Instruction: 8.0 MHz-375 ns; 250 ns (assumes
instruction in queue)

Asynchronous Modes:

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles)

Bit
-

Memory Capacity (Maximum)
EPROM:

2732, 8K bytes; 2764, 16K bytes;
27128, 32K bytes; 27256, 64K bytes;
27512, 128K bytes
EEPROM: 2817A, 4K bytes
iRAM:
2186, 16K bytes

NOTE:
Two local sites must contain BIST or user-supplied
boot-up EPROM.

5-8-bit character; odd, even, or parity; 1, 1.5, or
2 stop bits
Independent transmit and receive clocks, 1X,
16X, 32X, or 64X programmable sampling rate
Error Detection: Framing, Overrun and Parity
Break detection and generation
Synchronous Modes:
SDLC/HDLC flag generation and recognition
Automatic zero bit insertion bit and detection
Automatic CRC generation and detection (CRC
16 or CCITT)
Abort generation and detection
I-field residue handling
SDLC loop mode operation
CCITI X.25 compatible

Byte Synchronous Modes:
- Internal or external character synchronization (1
or 2 characters)
- Automatic CRC generation and checking (CRC
160r CCITI)
- IBM Bisync compatible

4-16

inter
Baud
Rate

iSBC® 286/100A MULTIBUS® "

Common Baud Rates '

Timers

Synchronous
(x1 Clock)

Asynchronous
(x16 Clock)

Input Frequencies: 1.23 MHz ±0.1% or 4 MHz
± 0.1 % (Jumper Selectable)

Time Constant

64K
48K
19.2 K
9600
4800
2400
1800
1200
300
110

36
49
126
254
510
1022
1363
2046
8190

6
14

SO
62
83
126
510
1394
Output Frequencies/Timing Intervals
Dual Timer/Counter
(two timers cascaded)
Min
Max

Single Timer/Counter

Real-Time Interrupt
Programmable One-Shot
Rate Generator
Square-Wave Rate Generator
Software Triggered Strob.e
Hardware Triggered Strobe
Event Counter

Min

Max

500 ns
500ns
18.8 Hz
18.8 Hz
500ns
500 ns

53.1 ms
53.1 ms
. 2 MHz
2 MHz
53.1 ms
53.1 ms
5.0 MHz

INTERFACES
,iPSB Bus:
iLBX II Bus:
iSBX Bus:
SERIAL 110
Channel A:

1.00 ms
1.00 ms
0.000290 Hz
0.000290 Hz
1.00 ms
1.00 ms

57.9 min
57.9 min
1 MHz
1 MHz
57.9 min
57.9 min

CONNECTORS
All signals TIL compatible
All signals TIL compatible
All signals TIL compatible

RS232C/RS422
compatible,
configurable as a data set or
'
data terminal
Channel B:
RS232C compatible, configured
as a data set
All signals TIl compatible
Timer:
Interrupt Requests: All signals TIL compatible

Location

Function

Part #

P1
P2

iPSB Bus
iLBXTM II Bus

603-2,-IEC-C096-F
603-2-IEC-C096-F

inter

iSBC® 286/100A MULTIBUS® II

PHYSICAL DIMENSIONS

ENVIRONMENTAL REQUIREMENTS

The iSBC 286/100A board meets all MULTIBUS II
mechanical specifications as represented in the
MULTIBUS II specification (part number 146077).

Temperature: (Inlet air) at 200 LFM airflow over
boards
Non-operating- - 40°C to + 70°C
Operating-O to + 55°C
Non-operating-95% RH @ 55°C
Humidity:
Operating-90% RH @ 55°C

Double-High Eurocard Form Factor:
Depth:
Height:
Front Panel Width:
Weight:

220 mm (8.7 in.)
233 mm (9.2 in.)
20 mm (0.784 in.)
653 g (1 lb. 7 oz.)

ELECTRICAL CHARACTERISTICS
The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
or expansion modules.
Voltage
(volts)

Max/Typical Current
(amps)

Max Power
(watts)

BTU

GramCaiorie

+5
+12
-12

10.31/8.25A
50/40mA
46/37 mA

54.39W
630mW
580mW

3.13
0.04
0.03

774.2
9.0
8.3

REFERENCE MANUALS

ORDERING INFORMATION·

ISBC 286/100A Single Board Manual Computer User's Guide (#149093-001)

Part Number
SBG286/100A

Intel MULTIBUS II Bus Architecture. Specification
(#146077)
Manual may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature·
Department, . 3065 Bowers Ave., Santa Clara, CA
95051

4-18

Description
MULTIBUS II 80286 based Single
Board Computer

32-BIT PERFORMANCE WITH MIJLTlBIJS® " CAPABILITY
These 32-bit MULTIBUSrder to provide a
reliable connection to the peripheral devices, additional ground lines are included at the connector.

Built-In-Self-Test Diagnostics

SPECIFICATIONS

On-board built-in-self-test (BIST) diagnostics provides confidence testing of the various functional areas of the iSBC 186/224A controller board. The initialization checks are performed by the 8751 microcontroller, while the BIST package is executed by
the 80186 microprocessor.

CPU:

5 MHz 80186 synchronized to 5 MHz
8237 A-5 DMA controller

Memory: 128K bytes DRAM on-board for buffers
and track cache
2 PROM sites contain Built-in-Self-Test
(BIST) and PCI firmware

BIST provides valuable testing and error reporting
and recovery. capability on MULTIBUS II boards, enabling the OEM to reduce manufacturing and maintenance costs. An LED on the board's front panel
indicates the status of power-up diagnostics.

Mass Storage Device Compatibility
Winchester-Any ST506/412 compatible 51,4"
drive.
.
.
Manufacturers include: Quantum, CMI, CDC,
Maxtor, Memorex, Atasi.
Densities range from 10 MB to 140 MB.

PCI Peripheral Communications
Interface,

Floppy-Any SA450/460 compatible 51,4" drive.
Manufacturers include: Teac, Shugart.
Sizes include half height, full height, 48TPI, 96TPI.

PCI is a logical message-based peripheral controller
interface to provide a standard software interface on
peripheral I/O boards. This protocol provides a vehicle to issue multiple commands or statuses concurrently. This allows the 186/224A board to accept
multiple commands and queue them in on-board
memory.

Tape-Any QIC-02 compatible, %" streaming tape
.
drive.
Manufacturers include: Archive, Cipher, Tandberg.

Physical Dimensions

BACKPLANE BUS INTERFACES

The iSBC 186/224A board meets all the mechanical
specifications as presented in the MULTIBUS II specification (order #146077 rev. C).

P1 Connector: This is used as the standard MULTIBUS II 32-bit parallel system bus. It contains all signals required to implement the full standard interface.

DOUBLE-EUROCARD FORM FACTOR

P2 Connector: The P2 connector is not electrically
connected internally on the board.

Depth: 220 mm (8.6 in)
Height: 233 mm (9.2 in)

. Winchester Connections: One 50-pin D-type, right
angle female, high density connector which provides

Front Panel Width: 20 mm (0. 784 in~)

8-3

iSBC® 186/224A

CONNECTORS
InteHace

Connector

iPSB bus (P1)

96 Pin DIN, Right Angle Female

96 Pin DIN, Right Angle Female,
Not Connected Internally

ST506/412 (Winchester)

50 Pin 0 Type, Right Angle Female,
High Density (See Note)

SA450/460 (Floppy)

25 Pin 0- Type, Right Angle Female,
(See Note)

QIC-02 (Tape)

25 Pin D-Type, Right Angle Female,
(See Note)

Part No.
603-2-1 EC-C096-F
603-2-IEC-C096-F

NOTE:

The manufacturers below provide connectors which will plug into the connectors supplied on the iSBC 186/224A board
front-panel.

Connector Type Manufacturer Pins
Flat Ribbon
Crimped
Bulk Cable
Solder Cup

Pin Crimp

Reference Manuals

Part No.

T&B Ansley
T&BAnsley

50
25

609-50P
609-25P

Amlan
Amlan
ITT Cannon
ITT Cannon

50
25
50
25

CDS50L
CDS25L
DD-50P
DB-25P

AMP
AMP
ITT Cannon
ITT Cannon

50
25
50
25

206438-1
205436-1
DDC-50P
DBC-25P

iSBC 186/224A Board Hardware Reference Manual
(order number 138272-001)
Intel MULTIBUS " Bus Architecture Specification
(order number 146077)
Manual may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA
95051.

ORDERING INFORMATION
Part Number .

. Description

iSBC 186/224A

Multiperipheral
system

Controller Sub-

8-4

iSBC® 208
FLEXIBLE DISKETTE CONTROLLER

•
•
•
•

Phase Lock Loop Data Separator
• Assures
Maximum Data Integrity
Read and Write on Single or Multiple
• Sectors
Single + 5V Supply
• Capable
of Addressing 16M Bytes of
• System Memory

Compatible with All iSBC® 80, iSBC 86,
and iSBC 88 Single Board Computers
Controls Most Single and Double
Density Diskette Drives
On-Board iSBXTM Bus for Additional
Functions
User-Programmable Drive Parameters
allow Wide Choice of Drives

The Intel iSBC 208 Flexible Disk Controller is a diskette controller capable of supporting virtually any soft-sectored, double density or single density diskette drive. The standard controller can control up to four drives with
up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats, the controller
supports sector lengths of up to 8192 bytes. The iSBC 208 board's wide range of drive compatiblity is
achieved without compromising performance. The operating characteristics are specified under user program
control. The controller can read, write, verify, and search either single or multiple sectors. Additional capability
such as parallel or serial 110 or special math functions can be placed on the iSBC 208 board by utilizing the
iSBX bus connection.

280228-1

8-5

September 1986
Order Number: 280228-001

iSBC® 208

Universal Drives and the iSBC® 208
Controller

FUNCTIONAL DESCRIPTION
Intel's 8272 Floppy Disk Controller (FDG) circuit is
the heart of the iSBC 208 Controllier. On-board data
separation logic performs standard MFM (double
density) and FM (single density) encoding and decoding, eliminating the need for external separation
circuitry at the drive. Data transfers between the
controller and memory are managed by a DMA device which completely controls transfers over the
MULTIBUS® system bus. A block diagram of the
iSBC 208 Controller is shown in Figure 1.

Because the iSBC 208 Controller has universal drive
compatibility, it can be used to control virtually any
standard- or mini-sized diskette drive. Moreover, the
iSBC 208 Controller fully supports the iSBX bus and
can be used with any iSBX module compatible with
this bus. Because the iSBC 208 Controller is programmable, its performance is not compromised by
its universal drive compatibility. The track-to-track
access, head-load, and head-unload characteristics
of the selected drive model are program specified.
Data may be organized in sectors up to 8192 bytes
in length.

MINI·DRIVES

STANDARD DRIVES
(0·,

(5"·'

iJ.
1i

11JZ

)

CONNECTOR

U
~

ISBX
CONNECTOR

f4-- '

f--f4--

8237
DMAC

DATA BUS(B,

L..-.-

I
BUS

I
.
.

AUX
PORT

ADDER

(20'1..,.

CONTROLLER

TIMING
Pll

SEGMENT
REGISTER

'---

'218

I+-

('0,

8272
FDC

(18'

ADDRESS
BUFFER

(Z4'[

DECODE

DATA

BUFFER

ADDRESS
BUS

MULTIBUS SYSTEM BUS P1

(8,

DATA
BUS

.
280228-2

Figure 1.ISBC® 208 Flexible Disk Controller Block Diagram

8-6

iSBC® 208

Interface Characteristics

SPECIFICATIONS

The standard iSBC 20B Controller includes an Intel
B272 Floppy Disk Controller chip which supports up
to four drives, single or double sided.

Compatibility
CPU

SIMPLIFIED INTERFACE-The cables between the
iSBC 20B Controller and the drive(s) may be low
cost, flat ribbon cable with mass termination connectors. The mechanical interface to the board is a
right-angle header with locking tabs for security of
connection.

Any iSBC MULTIBUS computer or system main frame

Devices- Double or single density standard (B")
and mini (5%") flexible disk drives. The
drives may be single or double sided.
Drives known to be compatible are:
Standard (8")
Caldisk
Remex
Memorex
MFE
Siemens
Shugart
Pertec
CDC

PROGRAMMING-The powerful B272 FDC circuit is
capable of executing high-level commands that simplify system software development. The device can
read and write both single and multiple sectors. CRC
characters are generated and checked automatically. Recording density is selected at each Read and
Write to support the industry standard technique of
recording basic media information on Track 0 of
Side 0 in single density, and then switching to double density (if, necessary) for operations on other
tracks.

Mini (5%")

143M
RFD4000
550
700
FDD200-B
SAB50/BOO
FD650
9406-3

Shugart
Micropolis
Pertec
Siemens
Tandon
CDC
MPI

450 SA 400
1015-IV
250
200-5
TM-100
9409

51/52/91/92

Diskette- Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted
IBM Diskette 20 (or equivalent doublesided)

Program Initiation-Ali diskette operations are initiated by standard input/output (110) port operations
through an iSBC single board computer.

Equipment Supplied

System software first initializes the controller with
the operating characteristics of the selected drive.
The diskette is then formatted under progr~m control. For subsequent transfers, the starting memory
address and transfer mode are specified for the
DMA controller. Data transfers occur in response to
commands output by the CPU.

iSBC 20B Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 20B Hardware Reference Manual

Data Transfer-Once a diskette transfer operation
has been initiated, the controller acts as a bus master and transfers data over the MULTIBUS at high
speed. No CPU intervention is required until the
transfer is complete as indicated either by the generation of an interrupt on the bus or by examination of
a "done" bit by the CPU.

Physical Characteristics
Width: 6.75 inches (17.15cm)
Height: 0.5 inches (1.27 cm)
Length: 12.0 inches (30.4B cm)
Shipping Weight: 1.75 pounds (O.BO Kg)
Mounting: Occupies one slot of iSBC system chassis or iSBC 604/614 Cardcage/Backplane. With an iSBX MULTIMODULE
board mounted, vertical height increases
to 1.13 inches (2.B7 cm).

ISBX BUS SUPPORT-One connector is available
on the iSBC 20B board which supports the iSBX system bus. This connector supports single-byte tran~
fer as well as higher-speed transfers supervised by
the DMA controller. Transfers may take place in
polled or interrupt modes, user-selected. The presence of the iSBX bus allows many different functions
to be added to the board. Serial 110, parallel 110 and
various special-purpose math functions are only a
few of the capabilities available on iSBX MULTIMODULE boards.

Electrical Characteristics
Power Requirements:

B-7

+ 5 VDC

3.0A

inter

iSBC@208

Data Organization and Capacity
,

Standard Size Drives
Single Density

Double Density
Bytes per Sector
Sectors per Track
Tracks per Diskette
Bytes per Diskette
(Formatted, per
diskette surface)

IBM System 34

Non-IBM

IBM System 3740

Non-IBM

256 1 512 1 1024
26 1 15 1 8

20481409618192
4 1 2 1 1

128 1 256 1 512
26
8
15

10241 204814096
4 I 2 I 1

256

630,784

• 256,256
(128 byte/ sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/ sector)

315,392

512,512
(256 bytes/sector)
591,360
(512 bytes/ sector)
630,784
(1024 bytes/sector)

.Drive Characteristics

Standard Size
Double/Single Density

Transfer Rate (K bYtes/s)
Disk Speed (RPM)
Step Rate Time
(Programmable)
Head Load Time
(Programmable)

Head Unload Time
. (Programmable)

Mini Size

62.5/31.25

Double/Single Density
. 31.25/15.63

360
1 to 16 ms/track in
1 ms increments

300
2.to 32 ms/track in'
2 ms increments

2to 254 msin
2 ms increments

4to 508 ms in
4 ms increments

16 to 240 ms in
16 ms increments

32 to 480 ms in
32 ms increments

Environmental Characteristics

Reference Manual
143078-001- iSBC 208 Flexible. Disk Controller
Hardware Reference Manual (NOT
SUPPLIED). .
,

Temperature: O·C to 55·C (operating); -55·C to
+ 85·C (non-operating)
Humidity:
.Up to 90% Relative Humidity without
condensation (operating); all conditions without condensation or .frost
(non-operating) .

Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa,
Clara, CA 95051.

ORDER.ING INFORMATION
Part Number Description
SBC 208

8-8

Flexible Disk Controller

inter
•
•
•
•

iSBC® 214
PERIPHERAL CONTROLLER SUBSYSTEM
Supports 20 or 24-Bit Addressing
• On-Board
• ECC Diagnostics and Winchester

Based on the 80186 Microprocessor
Controls up to Two ST506/412 5%"
Winchester Disk Drives

•
•

Controls up to Four Single/Double
Sided and Single/Double Density 5%"
Flexible Disk Drives
Controls up to Four QIC-02 Streaming
Tape Drives

Incorporates Track Caching to Reduce
Winchester Disk Access Times
iRMXTM and XENIX· Operating System
Support

The iSBC 214 Subsystem is a single-board, multiple device controller that interfaces standard MULTIBUS®
systems of three types of magnetic storage media. The iSBC 214 Peripheral Controller Subsystem supports
the following interface standards: ST506/412 (Winchester Disk), SA 450/460 (Flexible Disk), and QIC-02 (%"
Streaming Tape).
The board combines the functionality of the iSBC 215 Generic Winchester Controller and the iSBC 213 Data
Separator, the iSBXTM 218A Flexible Disk Controller, and the iSBX 217C %" Tape Drive Interface Module.
The iSBC 214 Subsystem emulates the iSBC 215G command set, allowing users to avoid rewriting their
software.
The iSBC 214 Peripheral Controller Subsystem offers a single slot solution to the interface of multiple storage
devices, thereby reducing overall power requirements, increasing system reliability, and freeing up backplane
slots for addtional functionality. In addition, the new iSBC 214 Subsystem can be placed in a 16 Megabyte
memory space.

280089-1

·XENIX is a trademark

of MICROSOFT Corp.
8-9

September 1986
Order Number: 280089-001

intJ

iSBC@ 214

ware decode the command request, allocate RAM
buffer space, and dispatch the tasks.

The iSBC 214 represents a new Peripheral Controller Subsystem architecture which is designed
around a dual bus structure and supported by realtime, multitasking firmware. The 80186 controls the
local bus and manages the interface between the
MULTIBUS and the controller. It is responsible for
high speed data transfers of up to 1.6 megabytes
per second between the iSBC 214 Subsystem and
host memory. The 80186 and the multitasking firm-

A second bus, the I/O Transfer Bus; supports data
transfers between the controller and the various peripheral devices. It is this dual bus system that allows the iSBC 214 Subsystem to provide simultaneous data transfers between the controller and the
storage devices, and between the controlier and the
MULTIBUS. (See Figure 1).

~
801"
110 PROCESSOR

OMA
CONTROLLER

LOCAL
BUS
INTERFACE,

MULTIBUS·
INTERFACE

WINCHESTER
DISK
INTERFACE

' 110 TRANSFER
BUS
INTERFACE

ROM

,...

FLEKIBLE
DISK
INTERFACE

RAM

QlCo02
TAPE
INTERFACE

ISBC" 214 PERIPHERAL CONTROLLER SUBSYSTEM

280089-2

Figure 1. Block Diagram iSBC@ 214 Peripheral Controller Subsystem

MULTIBUS"

ISBC" 214 PERIPHERAL CONTROLLER SUBSYSTEM

I/O INTERFACE
ST506I412
WINCHESTER

I/O INTERFACE
QIC-02TAPE

110 INTERFACE

&A"50 FLOPPY

Il" TAPE DRIVE

280089-3

Figure 2. Fully Configured Peripheral Subsystem

8-10

iSBC® 214

The iSBC 214 Subsystem implements an intelligent
track caching scheme through dynamic allocation of
buffer space. This provides reduced access times to
the Winchester disk and improved system performance. Operating systems with file management designed to handle sequential data can be supplied
directly from the cache without incremental access
to the disk.

Tape Controller Interface
The tape controller section of the iSBC 214 Subsystem is based on the 8742 Universal Peripheral Interface (UPI). It is capable of supporting up to four
QIC-02 compatible streaming tape drives over a
standard 50-pin daisy-chained cable.

FUNCTIONAL DESCRIPTION

All standard QIC-02 commands are supported. All
drives must be capable of streaming at 30 or 90
inches per second.

Winchester Disk Interface

MULTIBUS® Host Interface

The iSBC 214 Subsystem provides control of one or
two ST506/412 compatible Winchester devices and
supports up to 16 Read/Write heads per drive. The
Intel 82062 acts as the main controller taking care of
FM/MFM encoding and decoding, bit stream serialization and deserialization, address mark detection
and generation, sector identification comparisons,
CRC error checking and format generation. The
board uses a standard daisy-chained control cable
and a separate data transfer cable for each device
supported.

The MULTIBUS connection consists of two standard
printed circuit board edges that plug into MULTIBUS
edge connectors on a backplane in the system bus.
An active P1 connector is required and serves as the
Host systems's communciation channel to the controller. An active P2 connector is optional and only
required for supporting full 24-bit addressing and
power fail signals.

ECC

Compatibility

High data integrity is provided by on-board Error
Checking Code logic. For burst error correction, a
32-bit code is appended to the sector data fields by
the controller. During a· read operation, the same
logic regenerates the ECC polynomial and compares this second code to the appended ECC. The
ECC logic can detect an erroneous data burst up to
32 bits in length with correction up to 11 bits.

CPU-any iSBC MULTIBUS computer or system
mainframe.

If an ECC .error is detected the controller automatically initiates a retry operation on the data transfer. If
the maximum retry count is exceeded, the location
of the bad data within the transfer buffer is identified
and the 80186 then performs error correction on the
data bytes.

Tape drive-Any QIC-02 compatible, .25" streaming
tape drive.

SPECIFICATIONS

Winchester disk-Any
5.25" disk drive.

ST506/412

compatible,

Flexible disk-Any SA450/460 compatible, 5.25"
.
disk drive.·

Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 214 Hardware Reference Manual.

Flexible Disk Interface
The Flexible Disk Controller performs all data separation, FM (single density) and MFM (double density)
encoding, and CRC support. The 34-pin connector is
designed to support the SA450/460 interface directly and up to four flexible disk devices may be connected to the controller.

Physical Characteristics
Width: 6.75 in. (17.15 cm)
Height: 0.5 in. (1.27 cm)
Length: 12.0 in. (30.48 cm)
Shipping Weight: 19 oz. (540 g)

8-11

inter

iSBC® 214

Humidity:

Ordering Information
iSBC 214 Peripheral Controller Subsystem.
Mou~ting: Occupies one slot or SBC system chassis or cardcage/backplane.

Up to 90% relative humidity without
condensation (operating); all conditions without condensation or frost
(non-operating).

Reference Manual
134910-001: iSBC 214 Peripheral Controller Subsystem Hardware Reference Manual
(not supplied). Reference Manual
may be ordered from any Intel sales
representative, distributor office or
from Intel Literature Department,
3065 Bowers Avenue, Santa Clara,
CA 95051.
.

Electrical Characteristics
Power Requirements:

+ 5 VDC

4.5A max.

Environmental Characteristics
Temperature: 1O·C to 55·C with airflow of 200 linear
feet per minute (operating); -55·C to
+ 85·C (non-operating).

8-12

iSBC® 215
GENERIC WINCHESTER CONTROLLER
• On-Board Diagnostics and ECC
• Full Sector Buffering On-Board
• Capable of Directly Addressing 16 MB
of System Memory

• Controls up to Four 5%",8" or 14"
Winchester Disk Drives from Over Ten
Different Vendors
• Compatible with Industry Standard
MULTIBUS® (IEEE 796) Interface

• Removable Back-up Storage Available
Through the iSBXTM 218A Flexible Disk
Controller and the iSBX 217C %" Tape
Interface Module

• Supports ANSI X3T9/1226 Standard
Interface
• Software Drivers Available for
iRMXTM 86, iRMX 88 and Xenix*
Operating Systems
•

Intel 8089 I/O Processor Provides
Intelligent DMA Capability

Using VLSI technology, the iSBC 215 Generic Winchester Controller (GWC) combines three popular Winchester controllers onto one MULTIBUS board: the iSBC 215A open loop controller, the iSBC 215B closed loop
controller, and an ANSI X3T9/1226 standard interface controller. The combined functionality of the iSBC 215
Generic Controller supports up to four 51,4", 8" or 14" Winchester drives from over 10 different drive vendors.
Integrated back-up is available via two iSBX MULTIMODULE boards; the iSBX 218A module for floppy disk
drives and the iSBX 217C module for 1,4" tape units.
From the MULTIBUS side, the iSBC 215 GWC appears as one standard software interface, regardless of the
drive type used. In short, the iSBC 215 GWC allows its user to change drive types without rewriting software.
The iSBC 215 Generic Controller is totally downward compatible with its predecessors, the iSBC 215A and
215B controller; allowing existing iSBC 215A and 215B users to move quickly to the more powerful iSBC 215
Generic Winchester Controller. In addition, the iSBC 215 GWC directly addresses up to 16 megabytes of
system memory.

210618-1

Xenix. is a trademark of Microsoft Corp.

8-13

October 1986
Order Number: 210618.002

iSBC® 215

ECC polynomial to the appended ECC. The ECC
logic can detect an erroneous data burst up to 32
bits in length and using an 8089 algorithm can correct an errone,ous burst up to 11 bits in length.

FUNCTIONAL DESCRIPTION
Disk Interface
The iSBC 215 Generic Winchester Controller can interface to over 10 different disk drives. To change
drive types the user need only reconfigure a minimal
number of board jumpers and, if required, insert the
proper formatting information into the command parameter blocks.

iSBXTM Interface
Two iSBX bus connectors provide I/O expansion capability for the iSBC 215 GWC. With the optional addition of the iSBX 218A Flexible Disk Controller
MULTIMODULETM and or the iSBC 217C %" Tape
Interface Module, the iSBC 215 GWC can be configured into one of four types of peripheral subsystems, see Table 1.

The ANSI X3T9/1226 standard interface is a simple
one-for-one flat cable connection from drive to controller.

Table 1. Peripheral Subsystem Configurations
iSBC® iSBXTM iSBXTM
215
218A
217C

Full On-Board Buffer
The iSBC 215 Generic controller contains enough
on-board RAM for buffering one full data sector. The
controller is designed to make use of this buffer in all
transfers. The on-board sector buffer prevents data
overrun errors and allows the iSBC 215 Generic
Winchester Controller to occupy any priority slot on
the MULTIBUS.

Winchester Only
Winchester
Winchester

+ Floppy
+ %" Tape
+ Floppy

Winchester
+ %" Tape

'"
'"
'"
'"

'"
'"

ECC

Expanded I/O Capability

High data integrity is provided by on-board Error
Checking Code (ECG) logic. When writing sector 10
or data fields, a 32-bit ECC, for burst error correction, is appended to the field by the controller. During a read operation, the same logic regenerates the

The iSBC 215 GWC controller allows the execution
of user-written 8089 programs located in on-board
or MULTIBUS system RAM. Thus the full capability
of the 8089 I/O processor can be utilized for custom
I/O requirements.

i-------------------------l
I
I
I

I
I
I

IOI'

I
I

lOP

I
I

lOP

MULTIBUS'
INTERFACE

MULTIBUS·
BUS

LOCAL

r.. r - - - - - - ,

IUS

INTERFACE

SYSTEM

MEMORY

ROM

1/0 COMMUNICA·
TlONS BLOCKS

RAM

ISBC" 215 GENERIC WINCHESTER CONTROLLER

-------------------------------210618-2

Figure 1. Block Diagram of iSBC® 215 Generic Winchester Disk Controller
8-14

inter

ISBC@215

Interface with Shugart/Quantum/RMS Drives

210618-3

NOTE:
1. Shugart SA1000 or RMS Data Express.·

·Data Express is a trademark of Rotating Memory Systems.

Interface with Memorex/Shugart Drives

210618-4

Interface with ANSI Drive
' - - " " " ' - - - ' CONTROL AND
READlWRITE

'---7[1',
'u

O/A ,R
'G

X
B

.
SHIFT
REGISTERS

COLOR
lOOK-UP
TABLE

231035-2

Figure 1. Block Diagram
9-2

infef

iSBC® 186/78A CONTROLLER

Table 1.82720 Command Library

Video Output

Video Control Commands

RESET:
SYNCH:

The iSBC 1.86/78A VGC controls both monochrome
and color monitors, providing TTL (OV-5V) or analog (OV-0.7V) signal outputs. The iSBC 186/78A
VGC operates with a broad range of CRT horizontal
scan-rates. (The scan-rate is related to the pixel
clock rate and the desired display resolution.) The
pixel clock rate is selected by a jumper on the board,
and may be either 20 MHz or 25 MHz. The pixel
clock oscillator may be changed by the user to support monitors with lower bandwidths.

Resets the GDC to its idle state.
Specifies the video display
format.
Display Control Commands

START:
BCTRl:
ZOOM:
CURS:
PRAM:

PITCH:

Ends idle mode and unblanks the
display.
Controls the blanking and
unblanking of the display.
Specifies the zoom factors for
graphics character writing.
Sets the position of the cursor in
display memory.
Defines the starting address and
lengths qf display areas, and
specifies the eight bytes for the
graphics character.
Specifies the width of the X
dimension in display memory.

MONOCHROME MONITORS

The iSBC 186/78A VGC video outputs and sync signals may be either TTL or analog level signals. The
sync signals are available as separate vertical and
horizontal sync signals (Vsync. and Hsync) or as a
composite sync signal (Csync). When the iSBC
186/78A VGC operates in the monochrome mode,
the analog video signal can provide a 16-level grey
scale.

Drawing Control Commands

WDAT:
MASK:
FIGS:
FIGD:
GCHRD:

Writes data words or bytes into
display memory.
Sets the mask register contents.
Specifies the parameters for the
drawing processor.
Draws the figure as specified.
Draws the graphics character into
display memory.

COLOR MONITORS

When operating in the color mode,the iSBC
186/78A VGC video outputs are Red, Green, and
Blue video signals, with a maximum of 16 individual
colors displayed at one time. The Red and Blue output signals are always analog. The Green output signal may be analog or TTL. The analog signals are
generated in a 12-bit look-up table that provides a
possible 4096 colors. When the Green output is analog, it may be combined with the composite sync
signal, producing a Sync-on-Green signal. The vertical and hqrizontal sync signals (Vsync and Hsync)
are available on separate outputs or they may be
combined to generate a composite sync signal
(Csync).

Data Read Commands

RDAT:
CURD:
lPRD:

Reads data words or bytes from
display memory.
Reads the cursor position.
Reads the light pen address.

?r four 512 x 512 x 4 frame buffers. Display memory
read or written 16 bits at a time by the 82720
GDC. Both display cycles and read-modify-write
(~MW) cycles may be controlled by the user. During
display cycles, data is read from the display memory
and sent to the CRT for display, starting at the upper
left hand of the screen and moving down toward the
bottom right corner. During RMW cycles, data is
transferred between the GDC and the display memory.
IS

GRAPHICS CONTROL CENTER
Central Processing Unit
The 80186 component is a high--performance, highintegration 16-bit microprocessor. It combines several of the most common components onto a single
~hip including DMA (Direct Memory Access), interval
timers, clock generator, and a PIC (Programmable
Interrupt Controller). The 80186 CPU provides up to
a 100% performance improvement over the 8086
CPU at an equivalent clock rate.

In monochrome mode, all 256K 16-bit words are
treated as a contiguous block of memory,. where a
logical "1" in memory is displayed as an illuminated
pixel. In color mode, four color planes exist in memory and are written into (multi-write) and displayed
simultaneously. Each plane consists of 64K 16-bit
words.

Three internal 16-bit programmable timers are
vided. On the iSBC 186/78A VGC, two of these
ible timers are connected to four external pins
pins per timer). They can be used to count or
9-3

proflex(two
time

inter

iSBC® 186178A CONTROLLER

external events, generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time delay applications. User software can configure. each
timer independently to select the desired function.
Available functions include: Interrupt on terminal
count, programmable one-shot, rate generator,
square-wave generator, software triggered strobe,
hardware triggered strobe, and event counter. In addition, the third timer can be used as a prescaler for
the other two timers, or as a DMA request source.
The contents of each counter may be read at any
time during system operation.

Universal Memory Sites for
Local Memory
Eight 28-pin JEDEC-compatible sockets are provided for using 2732, 2764, 27128, 27256 and 27512
EPROMs and their respective ROMs. Other JEDECstandard pinout devices are also supported, including byte-wide static RAMs and iRAMs. Expansion to
a total of 12 sockets is available by adding the iSBC
341 memory module. With the iSBC 341 memory
module installed, the board supports up to 768K
bytes of local storage (using 27512 EPROMs).
The eight sockets are divided into four blocks of two
each (for high ahd low byte), or six blocks when using the iSBC 341 memory module. These independent blocks allow the user to mix many different
kinds of 28-pin devices for increased application
flexibility. Two different kinds of components may be
used at anyone time and all devices on the optional
iSBC 341 memory module must be the same. The
memory decode PAL is socketed so that the user
may replace it with a custom PAL configured to suit
their particular application.

A 6·byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 500 ns
minimum instruction cycle to 333 ns for queued instructions. The stack oriented architecture readily
supports modular programming by facilitating fast,
simple intermodule communication along with other
programming constructs needed for asynchronous
real-time systems.
The 80186 CPU uses a dynamic relocation scheme
that allows separation of command procedures from
data for efficient memory utilization. Four segment
registers (code, stack, data, extra) contain program
loaded offset. values which are used to map 16-bit
addresses to 20-bit addresses. Each register maps
64K bytes at a time. Activation of a specific register
is controlled, both explicitly by program control, and
implicitly by specific functions and instructions. In
addition, the iSBC 186/78A VGC has external logic
to provide access to the full 16M byte range of the
MULTIBUS address space.

Interrupt Control
The iSBC 186/78A VGC board uses the programmable interrupt controller (PIC) within the· 80186
component, and allows 5 on-board vectored interrupt levels. The highest priority interrupt is the NonMaskable Interrupt (NMI) line which is tied directly to
the 80186 CPU. This interrupt is typically used to
signal catastrophic events (e.g. power failure). The
PIC provides prioritization and vectoring for the other
4 interrupt requests from on-board 1/0 resources
and from the MULTIBUS system bus. The PIC then
resolves the requests according to the programmable priority resolution mode, and if appropriate, issues an interrupt to the CPU.

Both DMA channels provided by the 80186 CPU are
supported on theiSBC 186/78A VGC. These channels allow a direct path from the MULTIBUS or iSBX
bus to local memory. Indirect access to the display
memory is also possible under 82720 GDC control.
A flag byte signaling mechanism aids in creating an
interprocessor communication scheme. This includes: (1) the ability to set/reset interrupts and (2)
board reset.
'
.

Interrupt service requests to the iSBC 186/78A VGC
may originate from 22 sources. Table 2 contains a
list of devices and functions capable of generating
interrupts. Most of these interrupts may be jumpered
(user configurable) to the desired interrupt request
level.

Instruction Set
The 80186 instruction library is a superset of that for
the 8086. Therefore, object code compatibility was
maintained while 10 instructions were added. The
new instructions include: Block 1/0, Enter and Leave
subroutines, Push Immediate, Multiply Quick, Array
Bounds Checking, Shift and Rotate by Immediate,
and Pop and Push All.

iSBXTM MULTIMODULETM Expansion
The iSBC 186/78A VGC has two iSBX MULTIMODULE connectors, both support the 8-bit and 16-bit
iSBX data buses. The addition of iSBX MULTIMODULE boards provides 1/0 functions to suit most application requirements. These 1/0 functions can in-

9-4

iSBC® 186/78A CONTROLLER

Table 2. Interrupt Request Sources
Device

Function

Number
Interrupts

MULTIBUS interface
INTO-INT7

Requests from resident MULTIBUS CPU or
peripheral controller boards

Internal 80186 timer
and DMA

Timer 0, 1, 2, outputs (function determined by timer
mode) and 2 DMA channel interrupts

iSBX interfaces

Function determined by iSBX MULTIMODULE
boards

Bus fail-safe timer

Indicates addressed resident MULTIBUS device has
not responded to command within 6 msec

GDC vertical retrace

Synchronization of screen blanking

Flag Byte

Board identification

clude parallel and serial I/O, analog I/O, and mass
storage device control. Mounting iSBX MULTIMODULEs directly on the single board computer often
results in less interface logic, lower power, simpler
packaging, higher performance, and lower costs
than an alternative full-size iSBC board solution. See
Figure 2 for an example of a minimal system where
iSBX MULTIMODULE boards are added to an iSBC
186/78A VGC acting as the host CPU.

Each of the iSBX connectors on the iSBC 186/78A
VGC provides all of the signals necessary to interface to the local on-board bus, including 16 data
lines for maximum data transfer rates. All iSBX MULTIMODULE boards, designed with 8-bit data paths
and using the 8-bit iSBX connector, are also supported on the iSBC 186/78A VGC. A broad range of
iSBX MULTIMODULE options are available from
Intel.

231035-3

Figure 2. iSBC® 186/78A as a Host-CPU

9-5

intJ

ISBC® 186178A CONTROLLER

MULTIBUS® .SVSTEM ARCHITECTURE
System Bus-Overview
The MULTIBUS system bus is Intel's industry standard (IEEE 796) microcomputer bus structure. Both
8-bit and 16-bit single board computers are supported with 24 address and 16 data lines. A MULTIBUS
system can be expanded by using a variety of MULTIBUS board products, such as the iSBC 186/78A
VGC. The bus structure also allows very powerful
distributed processing configurations with multiple
processors, including multiple i~BC 186/78A VGC
boards, for the most demanding microcomputer applications.

er bus masters, to share the system bus using a
. serial (daisy chain) priority scheme. Up to 16 busmasters may share the MULTIBUS system bus with
an external parallel priority decoder. In addition to
the multiprocessing configurations made possible
with multimaster capability, the MULTIBUS system
bus· also provides an efficient mechanism for all
forms of. DMA (Direct Memory Access) transfers.
Figure 3 shows a multiuser, multimaster configuration.

MULTIBUS® Expansion
Memory and liD capacity may be increased and additional functions added by using Intel MULTIBUS
compatible expansion boards. System memory for
the 80186 microprocessor may be expanded by
adding RAM boards, EPROM boards, or memory
combination boards. Digital liD and analog liD expansion boards· are available. Floppy disk and harddisk controllers are available on MULTIBUS expansion boards or iSBX MULTIMODULE boards. Modular, expandable backplanes and cardcages are
available to support multi-board systems.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.
several CPUs and/or controllers logically sharing
system tasks), the iSBC 186/78A VGC provides full
MULTIBUS bus arbitration control logic. This control
logic allows up to three iSBC 186/78A VGCs, or oth-

231035-4

Figure 3_
9-6

inter

ISBC® 186178A CONTROLLER

GRAPHICS SOFTWARE (OPTIONAL)

System Clock
8.00 MHz

± 0.1 %

iVDI 720 Command Interpreter
The iVDI 720 Virtual Device Interpreter provides the
iSBC 186178A VGC with a Virtual Device Interface
(VOl) that is consistent with the graphics software
standard defined by the ANSI X3 organization. The
iVDI 720 software decodes high-level commands to
streamline the development of application code. It
also supports a variety of input device drivers including digitizing tablets and mice. The standard software interface provides a smooth upgrade path, simplifying the transition to future hardware devices.

Instruction Cycle Time
8 MHz

-500 ns
-333 ns (assumes instruction in queue)
NOTE:

Basic instruction is defined as the fastest instruction time (Le., two clock cycles).

Memory Response Time
The proposed ANSI standard defines the encoding
of high-level text and graphics commands. The iVDI
720 software decodes a binary representation of
these proposed commands, and allows consistent
formatting and storage of VOl encoded images.

286 ns for zero wait-states (address to data-valid)

Memory Capacity (Max)

The iVDI 720 Graphics Virtual Device Interpreter is
designed· for EPROM installation on the iSBC
186178A VGC. Graphics functions can then be offloaded to the iSBC 186/78A VGC, permitting the
host CPU board to concentrate on system level operations such as database management or network
communications.

EPROM

512K bytes (768K with iSBC 341 MULTIMODULE) using 27512s
E2PROM 16K bytes (24K with iSBC 341 MULTIMODULE) using 2817As
iRAM
64K bytes (96K with iSBC 341 MULTIMODULE) using 51C86s
Static RAM same as iRAM

iRMXTM 86/iRMX 286 Software Device
Driver

PHYSICAL CHARACTERISTICS
Length:
Height:
Depth:

The iRMX 86 and iRMX 286 software are Intel's realtime, multi-tasking operating systems. The iVDI 720
software package furnishes the software device
driver required to operate the board in an iRMX software environment. It creates a predictable environment for the input and output of high-level commands between the user and system, or among the
graphics peripherals attached to the system, such
as a mouse, tablet, printer or plotter. The iRMX driver includes PL/M and C language bindings.

Weight:

SPECIFICATIONS

Word Size
Instruction-8, 16, 24, or 32 bits
Data
-8 or 16 bits

9-7

12.00 in. (30.48 cm)
7.05 in (17.90 cm)
0.50 in. (1.78 cm)
1.13 in. (2.82 cm) with iSBC Memory Expansion and MULTIMODULEs, or iSBX
MULTIMODULE boards
18.3 ounces (519 gm) excluding any
MULTIMODULE boards

inter

iSBC® 186/78A CONTROLLER

Connectors
Interface

Double-sided

Centers

Supplier

MULTIBUS System

86 pin (P1)

0.156 in.

Viking 3KH43/9AMK12
Wire Wrap

iSBXBus
(8- and 16-bit)

36/44 (J2; J3)

0.100

Viking 000294-0001

Video Interface
- or-

26 (J1)
5 pes. (J7-11)

0.1
SMC-type

3M 3399-6026 flat cable
Sealectro 50-007-0000"
with Belden 174/U coax

ELECTRICAL CHARACTERISTICS

RELATED LITERATURE

Power Requirements: 8.4A @ + 5 ± 5% Vdc (Maximum);4.9A @ +5 ±5% Vdc
(typical)

210883-001- MULTIBUS Handbook
280002-001- iVDI 720. Data Sheet (Virtual Device
Interface) ,
146717-002- iVDI 720 Graphics Software· Reference Manual
142686-001- iSBX Specification

ENVIRONMENTAL REQUIREMENTS,
Operating Temperature: O· to 5S·Cwith 200 Ifm air
flow
Relative Humidity:

210451-001- 80186 Data Sheet.
210655-001-lntel 82720 Data Sheet,

. to 90% without condensa,tion

Literature and Hardware Reference Manual may be
ordered from an Intel Sales Representative, distributor office or from Intel Literature Department, 3065
Bowers Avenue, Santa Clara, California 95051.

REFERENCE MANUAL
147393-001- iSBC 186178A Video Graphics Subsystem Hardware Reference Manual

ORDERING INFORMATION
Part Number Description
iSBC 186178A Intelligent Video Graphics. Subsystem
.

9-8

iSBXTM 270
ALPHA-NUMERIC DISPLAY CONTROLLER

•
•
•
•
•

•
•
•
•

Complete Video Display Controller on a
Double-Wide iSBXTM MULTIMODULETM
Board
Interfaces to either Black and White or
Color Display Monitors
Displays 7 x 9, 5
Fonts

x 7, or 6 x 8 Character

High Level Software Interface via
Pre-Programmed 8041A UPI

Keyboard and Light Pen Interface
Provided On-Board
50 Hz or 60 Hz Frame Rate Operation
Provides Cursor Control, Reverse
Video, Blinking, Underline, Highlight
and Page or Scroll Mode
Compatible with All 8/16 Bit iSBC®
Boards which Support the Intel iSBX
Bus

Capability via Pre-Defined
• Graphics
Graphic Character Fonts

Interchangeable Character Fonts
Available in EPROM

The iSBX 270 Video Display Controller (VDC) is a complete video controller on a standard double wide Intel
iSBX MULTIMODULE board. Providing either black and white (B&W) or eight-color displays, the iSBX 270 VDC
brings alphanumeric video control to the iSBX bus. Any computer board or system supporting the Intel iSBX
MULTIMODULE bus is compatible with the iSBX 270 VDC, including most board and system products from
Intel. Additionally, the iSBX 270 VDC supports keyboard and light pen 110 on-board; this simplifies the deSign
of intelligent terminals.
The iSBX 270 module allows the user to add high level video display capability to hislher computer system
with a minimal cost and effort. Typical applications for the iSBX 270 VDC include video displays for industrial
operator stations, word processing systems, data base management products and many other uses.

210220-1

9-9

October 1986
Order Number: 210220-001

inter

iSBXTM 270 CONTROLLER

FUNCTIONAL DESCRIPTION

Red, Green, and Blue Video and sync allowing 8
different colors to be displayed.

iSBXTM Interface

Composite video is not provided on the iSBX 270
MULTIMODULE board; however', with minimal external circuitry, composite video can be added (circuit
design available; contact the local Intel Sales Office
for details).

The iSBX 270 VDC interfaces to the Intel iSBX bus
via the 8041A Universal Peripheral Interface (UPI)
Microcomputer. The 8041 A, under firmware control,
provides communication between the baseboard
and the iSBX 270 controller circuitry via the iSBX
data and control lines. Data may be displayed immediately following power up, using default initialization
provided by the 8041A UP\. In addition, eight highlevel commands are provided by the iSBX 270 firmware; these eight commands are used to alter the
default initialization of the controller and determine
status. Following initialization, characters are displayed on the CRT by simply writing to the proper
1/0 port.

Table 1 lists several CRT vendors compatible with
the iSBX 270 VDC.
Table 1. CRT's (B&W and Color)(1)
Type

B&W

Color

CRT Interface
The iSBX 270 VDC will interface to many B&W and
RGB color display monitors. For B&W monitors, the
iSBX 270 board provides TTL level signals for video,
vertical sync, and horizontal sync. Additionally, in
B&W, two levels of intensity (normal and highlight)
are supported under program control.

TTL 120, TV 120, TV 50
M3570
MDC-15
DM30-12BO-51-A04

Ball Brothers
lOT
CONRAC
NEC
MITSUBISHI

7-015-0131
19AC
5711C13
1202DH
C-3419

NOTE:
1. This in no way constitutes an endorsement by Intel Cor·
poration of these companies' products. The companies listed are known to provide products compatible with the iSBX
270 board.

When operating in the color mode, the iSBX 270
module provides TTL level 75 ohm line drivers for

CRT
CONNECTION

Model #

Vendor
Ball Brothers
Motorola
TSD
ELSTON

LIGHT PEN
INPUT

KEYBOARD
CONNECTION

CONNECTOR

ON·BOARD
DATA
BUS
CONTROL
ADDRESS
BUS

==========>

<==========;;;iSBX'.~BUS

Figure 1. iSBXTM 270 VDC Block Diagram

9-10

210220-2

iSBXTM 270 CONTROLLER

210220-3

Figure 2. The iSBXTM 270 VDC Interfaces to a User-Supplied Video CRT, Keyboard and Light Pen

CRT Controller

Keyboard Interface

The CRT Controller performs all timing and data
buffering functions for the CRT. The iSBX 270 VDC
uses the Intel 8275 CRT Controller (for additional
details refer to the 8275 data sheet available from
Intel.)

The iSBX 270 VDC also interfaces to a keyboard I/O
device via the J1 edge connector. The keyboard interface of the iSBX 270 VDC accepts up to eight TTL
parallel data lines and one TTL strobe, either positive or negative. Keyboard input is indicated by a
status bit in the.8041A and/or an interrupt. In addition, control lines are provided for visual and/or audible indicators. .

Screen Refresh
The iSBX 270 VDC contains 4K bytes of high speed
static RAM, as well as a high speed DMA controller
(8237A). The 8237A, under the control of the 8041 A
UPI, takes care of both writing data to the screen
and refreshing the screen.

Table 2 lists several keyboards that interface to the
iSBX 270 VDC.
Table 2. Keyboards(1)

Character Generation
The character fonts (128 characters, including alphabetic, numeric, and special characters) that are
displayed on the CRT are stored in EPROM. The
need may arise to display different character fonts,
i.e., those used in international systems or custom
symbols which are. application specific. With the
iSBX 270 VDC the user may modify any or all of the
character ,fonts by simply reprogramming the
EPROM. In addition, the user may utilize a larger
EPROM to obtain up to 256 characters.

Vendor

Model #

Advanced Input Devices
Cherry
Cherry
Chomerics
Cortron
Keytronic
Keytronic
Keytronic
Keytronic
Microswitch
Microswitch

SK-067
B70-05AB
CBBO-07AA
AN261 09/ AE26203
35-500014
L1648
L1660
L1674-03
L1752
66SD6-7
87SD30-8

NOTE:
1. This in no way constitutes an endorsement by Intel Corporation of these companies' products. The companies listed are known to provide products compatible with the iSBX
270 board.

9-11

iSBXTM 270 CONTROLLER

Light Pen Interface

TV MONITOR

Light pen I/O devices may be directly interfaced to
the iSBX 270 VDC. A light pen hit is triggered on the
rising edge of the light pen signal and is indicated by
a status bit in the UPI 8041A and/or an interrupt.

Most video display monitors with a 10 MHz bandwidth or better.

Table 3 lists a light pen vendor whose product interfaces to the iSBX 270 VDC.

TTL level pulse, maximum 50 ns rise time, minimum
100 ns hold time.

LIGHT PEN INPUT

Table 3. Light Pens(1)
Vendor

Information Control Co.

Compatibility

Model #

LP-700

CPU

NOTE:
1. This in no way constitutes an endorsement by Intel Cor·
poration of this companies' products .. The company listed
is known to provide products compatible with the iSBX 270
board.

Any iSBC single board computer or I/O board compatible with the MULTIBUS system bus and implementing the iSBX bus and connector.

Physical Characteristics
SPECIFICATIONS

3.08 inches (7.82 cm)
0.8 inches (2.05 cm)
7.5 inches (19.05 cm)
0.5 pounds (0.175 Kg)
Weight:
Mounting: Occupies one double-wide iSBX MULTIMODULE position on boards; increases
board height (host plus iSBX board) to
1.14 inches (2.90 cm).
Width:
Height:
Length:

Controller Characteristics
DISPLAY

Programmable to a maximum of 35 rows
umns of characters.

80 col-

CRT OUTPUTS

Electrical Characteristics

B&W: TTL level HSYNC, VSYNC, Video.
Color: TTL level, 750 line drivers for RGB and combined sync provide 8 different display colors.

Power Requirements:

+ 5 VDC

1.3A

Environmental Characteristics

FRAME RATE

Temperature: O°C to 55°C (operating); -55°C to
+ 85°C (non-operating)
Humidity:
Up to 90% relative humidity without
condensation (operating); all conditions without condensation or frost
(non-operating).

50 Hz or 60 Hz via jumper settings (non-interlaced)
CHARACTER FONTS

5 x 7, 7 x 9, or 6 x 8 jumperable with appropriate
crystal. Character generator uses 2716 EPROM.
Also compatible with 2732A EPROM's. For generation of special fonts, please refer to iSBX 270 VDC
Hardware Reference Manual.

Equipment Supplied
iSBX 270 VDC Controller
Reference Schematic

VIDEO CONTROL

Cabling and connectors from the VDC controller
to the CRT, keyboard and light pen are not supplied with the controller. Cables can be fabricated
with commercially available cable and connectors
as described in the iSBX 270 Hardware Reference
Manual.

Reverse video, blinking, underline, highlight, cursor
control and page or scroll mode.

9-12

iSBXTM 270 CONTROLLER

Reference Manual

ORDERING INFORMATION
Part Number Description
SBX 270
Video Display Controller
MODULE Board

143444-001- iSBX 270 Video Display Controller
Hardware Reference Manual (NOT
SUPPLIED).
Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

9-13

MULTI-

Digital and Analog
I/O Expansion

iSBC® 517
COMBINATION 1/0 EXPANSION BOARD
•

48 Programmable I!O Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Synchronous! Asynchronous
Communications Interface with RS232C
Drivers and Receivers

•

Eight Maskable Interrupt Request Lines
with a Pending Interrupt Register

•

1 ms Interval Timer

The iSBC 517 Combination 1/0 Expansion Board is a member of Intel's complete line of iSBC memory and 1/0
expansion boards. The board interfaces directly with any iSBC single board computer via the system bus to
expand serial and parallel 1/0 capacity. The combination 1/0 board contains 48 programmable parallel I/O
lines. The system software is used to configure the I/O lines to meet a wide variety of system peripheral
requirements. The flexibility of the I/O interface is significantly enhanced by the capability of selecting the
appropriate combination of optional line drivers and terminators to provide the required sink current,polarity,
and drive/termination characteristics for each application. A programmable RS232C communications interface is provided on the iSBC 517. This interface may be programmed by the system software to provide
virtually any asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). A
comprehensive RS232C interface to CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems is thus on the board. An on-board register contains the status of eight interrupt request lines
which may be interrogated from the system bus, and each interrupt request line is maskable under program
control. The iSBC 517 also contains a jumper selectable 1 ms interval timer and interface logic for eight
interrupt request lines.

280229-1

10-1

October 1986
Order Number: 280229-001

inter

iSBC® 517 EXPANSION BOARD

FUNCTIONAL DESCRIPTION
Programming Flexibility
The 48 programmable liD lines on the iSBC 517 are
implemented utilizing two Intel 8255 programmable
peripheral interfaces. The system software is used
to configure these programmable I/O lines in any of
the combinations of unidirectional inputloutput, and
bidirectional ports indicated in Table 1. In order to
take full advantage' of the large number of possible
liD configurations, sockets are provided for interchangeable liD line drivers and terminators to provide the required sink current, polarity, and drive/termination characteristics for each application. The 48
programmable liD lines and signal ground lines are
brought out to two 50-pin edge connectors that mate
with flat, round, or, woven cable. Typical liD read
access time is 280 nanoseconds. Typical liD read
cycle time is 600 nanoseconds.

Communications Interface
The programmable communications interface on the
iSBC 517, is provided by an Intel 8251 Universal
Synchronousl Asynchronous Receiver ITransmitter
(USART). The USART can be programmed by the
system software to select the desired asynchronous
or synchronous serial data transmission technique
(including IBM Bi-Sync). The mode of operation (Le.,
synchronous or asynchronous), data format, control
character format, parity, and asynchronous serial

transmission rate are all under program control. The
8251 provides full duplex, double-buffered transmit
and receive capability, and parity, overrun, and framing error detection are all incorporated in the
USART. The comprehensive RS232C interface on
the board provides a direct interface to RS232C
compatible equipment. The RS232C serial data lines
and signal ground lines are brought out to a 26-pin
edge connector that mates with RS232C compatible
flat or round cables.

Interrupt Request Lines
Interrupt requests may originate from eight sources.
Four jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to
be transferred to the CPU (Le., input buffer is full) or
a character has been transmitted (Le., output data
buffer is empty). Two jumper selectable interrupt requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (Le., receive buffer is full) or a character
has been transmitted (transmit buffer is empty).
These six interrupt request lines are all maskable
under program control. Two interrupt request lines
may be interfaced directly from user designated peripheral devices via the liD edge connector. An onboard register contains the status of all eight interrupt request lines, and may be interrogated by the
CPU. Each interrupt request line is maskable under
program control. Routing for the eight interrupt request lines is jumper selectable., They may be ORed

RS232C

COMPATIBLE
DEVICES

USER DESIGNATED PERIPHERALS

O~NTERRUPT
REQUEST
LINES

r--~-..,

ADDRESS BUS
DATA BUS
CONTROL BUS

}

~MULTIBUS
V

INTERFACE

280229-2

NOTE:

Interrupts originating from the programmable communications interface and programmable peripheral interface are jumper selectable.

Figure 1. iSBC® 517 Combination 1/0 Expansion Board Block Diagram
,
10-2

inter

iSBC® 517 EXPANSION BOARD

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Input

Lines
(qty)

Ports

Unlatched

1
2
3

8
8
4
4
8
8
4
4

4
5
6

Output
Latched &
Strobed

Latched

X
X

Bidirectional

Control

Latched &
Strobed
X
X(1)
X(1)

X
X

X
X(2)
X(2)

X
X

NOTES:
1. Part of port 3 must be used as control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.

to provide a single interrupt request line for the iSBC
80/10B,or they may be individually provided to the
system bus for use by other iSBC single board computers.

Serial Communications Characteristics
Synchronous-5-8 bit characters; internal or external character synchronization; automatic sync insertion.

Interval Timer
Each board contains a jumper selectable 1 ms interval timer. The timer is enabled by jumpering one of
the interrupt request lines from the 1/0 edge connector to a 1 ms interval interrupt request signal
originating from the baud rate generator.

Asynchronous-5-8 bit characters; peak characters
generation; 1, 1%, or 2 stop bits; false start bit detectors.

Interrupts
SPECIFICATIONS
1/0 Addressing
Port

Address X4 X5 X6

Eight interrupt request lines may originate from the
programmable peripheral interface (4 lines), the
USART (2 lines), or user specified devices via the
1/0 edge connector (2 lines) or interval timer.

8255
8255
USART USART
No.1
No.2
Data Control
Control Control

X9 XA

Interrupt Register Address

NOTE:
X is any hex digit assigned by jumper selection.

X1
XO

1/0 Transfer Rate

NOTE:
X is any hex digit assigned by jumper selection.

Parallel-Read or write cycle time 760 ns max
Serial-(USART)
Baud Rate (Hz)
Frequency (kHz)
(Jumper
Asynchronous
(Program
Selectable)
Synchronous
Selectable)

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

+16
9600
4800
2400
1200
600
300

Interrupt mask register .
Interrupt status register

Timer Interval
1.003 ms ± 0.1 % when 110 baud rate is selected
1.042 ms ± 0.1 % for all other baud rates

+64
2400
1200
600
300
150
75
110

10-3

iSBC® 517 EXPANSION BOARD

Bus Drivers

Interfaces
Bus-All signals TIL compatible
Parallel I/O-All signals TIL compatible
Serial I/O-RS232C
Interrupt Requests-All TIL compatible

CDC VPB01 E43AOOA 1

0.156

Parallel 1/0

0.1

3M 3415'000 or
TIH312125

Serial 1/0

0.1

3M 3462·000 or
TIH312113

!Auxiliary(1 )

0.1

AMP PE5-14559 or
TIH311130

50
25

Electrical Characteristics
Average DC Current
Vec = +5V ±5%
VDD = +12V ±5%
VAA = -12 ±5%
Ice = 2.4 mA max
IDD = 40 mA max
IAA = 60 mA max

NOTE:
1. Connector heights and wire-wrap pin lengths are not
guaranteed to conform to Intel OEM or system packaging.
Auxiliary connector is used for test purposes only.

Line Drivers and Terminators

NOTE:
Does not include power required for optional 1/0
drivers and 1/0 terminators. With eight 2200/3300
input terminators installed, all terminator inputs low.

1/0 Drivers-The following line drivers and terminators are compatible with all the 1/0 driver sockets on
the iSBC 517:

Environmental Characteristics

Sink Current (mA)
48
48
16
16
16
16
16
16

Characteristics
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Sink Current (mA)

Tri-state
Tri-state

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 14 oz, (397.3 gm)

Interface Pins (qty) Centers (In.) Mating Connectors
Bus

NOTE:
I = Inverting; NI

Characteristics

Physical Characteristics

Connectors

Driver
7438
7437
7432
7426
7409
7408
7403
7400

Function
Data
Commands

non-inverting;OC

Operating Temperature-O°C to + 55°C

Reference Manual
9800388B-iSBC 517 Hardware Reference manual
(NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa' Clara,
California 95051.'

open-collector.

Ports 1 and 4 have 25 mA totem-pole drivers and
1" kO terminators.

ORDERING INFORMATION
Part Number
SBC 517

1/0 Terminators-2200/3300 divider or 1 kO pullup

+5V_---':

Description
Combinatiori 1/0 Expansion Board

22Og/330gr~~-- - -____---<0 I.Be 90'

OPTION

\kg
1 kQ

+ 5V ---------'\'VV\~------o

10-4

ISBC 902 OPTION

280229-3

iSBC® 519
PROGRAMMABLE I/O EXPANSION BOARD
• Jumper Selectable 0.5, 1.0, 2.0, or
4.0 ms Interval Timer
• Eight Maskable Interrupt Request Lines
with Priority Encoded and
Programmable Interrupt Algorithms

• iSBC® I/O Expansion via Direct
MULTIBl:JS® Interface
• 72 Programmable I/O Lines with
Sockets for Interchangeable Line
Drivers and Terminators
• Jumper Selectable I/O Port Addresses

The iSBC 519 Programmable I/O Expansion Board is a member of Intel's complete line of iSBC memory and
I/O expansion boards. The iSBC 519 interfaces directly to any iSBC single board computer via the system bus
to expand input and output port capacity. The iSBC 519 provides 72 programmable I/O lines. The system
software is used to configure the I/O lines to meet a wide variety of peripheral requirements. The flexibility of
the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line
drivers and terminators to provide the required sink current, polarity, and drive/termination characteristics for
each application. Address selection is accomplished by using wire-wrap jumpers to select one of 16 unique
base addresses for the input and output ports. The board operates with a single + 5V power supply.

280230-1

10-5

October 1986
Order Number: 280230-001

inter

iSBC® 519 BOARD

Typical I/O read/write cycle time is 450 nanoseconds. The interval timer provided on the iSBC 519
may be used to generate real time clocking in systems requiring the periodic monitoring of I/O functions. The time interval is derived from the constant
clock (BUS CCLK) and the timing interval is jumper
selectable. Intervals of 0.5, 1.0, 2.0, and 4.0 milliseconds may· be selected when an iSBC single board
computer is used to generate the clock. Other timing
intervals may be generated if the user provides a
separate constant clock reference in the system.

FUNCTIONAL DESCRIPTION
The 72 programmable I/O lines on the iSBC 519 are
implemented utilizing three Intel 8255A programmable peripheral interfaces. The system software is
used to configure the I/O lines in any combination of
undirectional input/output and bidirectional ports in~
dicated in Table 1. In order to take full advantage of
the large number of possible I/O configurations,
sockets are provided for interchangeable I/O line
drivers and terminators. The 72 programmable I/O
lines and signal ground lines are brought out to three
50-pin edge connectors that mate with flat, round, or
woven cable.

Eight-Level Vectored Interrupt
An Intel 8259A programmable interrupt controller
(PIC) provides vectoring for eight interrupt levels, As
shown in Table 2, a selection of three priority processing algorithms is available to the system designer so that the manner in which requests are serviced

Interval Timer
Typical I/O read access time is 350 nanoseconds.

Table 1. Input/Output Port Modes of Operation

Ports

1,4,7
2,5,8
3,6,9

Lines
(qty)

8
8
4
4

Mode of Operation
Unidirectional
Input
Output
Latched &
Latched &
Latched
Unlatched
Strobed
Strobed
X

Bidirectional

Control

X(1,2,3)

NOTES:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input ora
latched and strobed output port.or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.
3. Part of port 9 must be used as a control port when either port 7 or port 8 are used as a'latched and strobed input or a
latched and strobed output port or port 7 is used as a bidirectional port.
USER DESIGNATED
PERIPHERALS

•

INTERRUPT
REQUEST
LINES

•

IN1'f:RAUPT

INTERRUPT

REQU!ST

REQUEST
LINe

LINES

ADDFlEssaU8
DAlASUS
CONTFlOlBUS

CONSTANT CLOCK (CCLK)

ISICeo
BUS

280230-2

Figure 1. iSBC® 519 Programmable I/O Expansion Board Block Diagram
10-6

ISBC® 519 BOARD

Table 2. Interrupt Priority Options
Algorithm

Interrupts

Operation

Fully nested

Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.

Auto-rotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Specific priority

System software assigns lowest
priority level. Priority of all other
levels are based in sequence
numerically on this assignment.

Register Addresses (hex notation, I/O address
space)
XD Interrupt request register
XC In-service register
XD Mask register
XC Command register
XD Block address register
XC Status (polling register)
NOTE:
Several registers have the same physical address;
sequence of access and one data bit of control
word determines which register will respond.

may be configured to match system requirements_
Priority assignments may be reconfigured dynamically via software at any time during system operation_ The PIC accepts interrupt requests from the
programmable parallel I/O interfaces, the interval
timer, or direct from peripheral equipment. The PIC
then determines which of the incoming requests is of
the highest priority, determines whether this request
is of higher priority than the level currently being
serviced, and if appropriate, issues an interrupt to
the system master; Any combination of interrupt levels may be masked through storage, via software, of
a single byte to the interrupt mask register of the
PIC.

Ten interrupt request lines may originate from the
programmable peripheral interface (6 lines), or user
specified devices via the I/O edge connector (3
lines), or int,erval timer (1 line).

Interval Timer
Output Register-Timer interrupt register output is
cleared by an output instruction to I/O address XE
or XF(t).
Timing Intervals-500, 1,000, 2,000 and 4,000 ms
± 1 %; jumper selectable(2).

Interrupt Request Generation-Interrupt requests
may originate from 10 sources. Six jumper selectable interrupt requests can be automatically generated by the programmable peripheral interfaces
when a byte of information is ready to be transferred
to the system master (Le., input buffer is full) or a
character has been transmitted' (Le., output data
buffer is empty). Three interrupt request lines may
be interfaced to the PIC directly from user designated peripheral devices via the I/O edge connectors.
One interrupt request may be generated by the interval timer.

NOTES:
1. X is any hex digit aSSigned by jumper selection.
2. Assumes constant clock (CCLK) frequency of
9.216 MHz ±1%.

Interfaces
Bus-All signals TTL compatible
Parallel I/O-All signals TIL compatible
Interrupt Requests-All TIL compatible

Bus Line Drivers-The PIC interrupt request output
line may be jumper selected to drive any of the nine
interrupt lines on the MULTI BUS. Any of the onboard request lines may also drive any interface interrupt line directly via jumpers and buffers on the
board.

Connectors

SPECIFICATIONS
Addressing
Port

8255
No.1

Control
Address XO Xl

X4 X5 X6

8255
No.2
Control

8255
No.3

Centers
(In.)

Bus

0.156

Viking 3KH43/9AMK12

Parallel 110

0.1

3M 3415-000 or
TIH312125

Serial 110

0.1

3M 3462-000 or
TIH312113

Auxiliary(1)

0.1

AMP PE5-14559 or
TIH311130

Mating Connectors

NOTE:
1. Connector heights and wirewrap pin lengths are not
guaranteed to conform to Intel OEM or System packaging.

Control
XB X9 XA

Pins
(qty)

Interface

10-7

inter

iSBC® 519 BOARD

Bus Drivers

Line Drivers and Terminators

Driver

Characteristics

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I = inverting; NI

Characteristics

Sink Current (rnA)

Data

Tri-state

Commands

Tri-state

Function

1/0 Drivers-The following line drivers and terminators are compatible with all the 1/0 driver sockets on
the iSBC 519:

Physical Characteristics
Width: '
Height:
Depth:
Weight:

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
14 oz. (397.3 gm)

Electrical Characteristics
= non-inverting; DC = open-collector.

Average DC Current

1/0 Terminators-220n/330n divider or 1 knpull~
up.

22Oru3::~r---,~~~~~:~:~"""~~~~~~=,--_o
....

Without Termlnatlon(1) With Termlnatlon(2)

Icc = 1.SA max

3.SA max

NOTES:
1. Does not include power required for operational 110 drivers and 110 terminators.
2. With 18 2200/3300 input terminators installed, all terminator inputs low.

Isac 901 OPTION

1kD

1 kO+5V

----I\JYV,I.-.- - - - - 0

Isac 902 OPTION

Environmental Characteristics

280230-3

Operating Temperature: O°C to
Ports 1, 4 and 7 may use any of the drivers or terminators shown above for unidirectional (input or output) port configurations: Either terminator and the
following bidirectional drivers and terminators may
be used for ports 1, 4 and 7 when these ports are
used as bidirectional ports.

Reference Manual
9800385B-iSBC 519 Hardware Reference manual
(NOT SUPPLIED) .
Manuals .may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Bidirectional Drivers
Driver

Characteristics

II"1tel8216

NI,TS

Intel 8226

I, TS

NOTE:
I = inverting, NI

Sink Current (rnA)

ORDERING INFORMATION

= non-inverting; TS = three-state

Part Number Description
SBC 519
Programmable 1/0 Expansion Board

Terminators (for ports 1, 4 and 7 when used as
bidirectional ports)
Supplier

Product Series

CTS

760-

Dale

LDP14k-02

Beckman

899-1

+ 55°C

10-8

iSBC® 556
OPTICALLY ISOLATED 1/0 BOARD
•

Up to 48 Digital Optically Isolated
Input/Output Data Lines for
MULTIBUS® Systems

•

Choice of
- 24 Fixed Input Lines
-16 Fixed Output Lines
- 8 Programmable Lines

II Voltage/Current Levels
- Input up to 48V
- Output up to 30V, 60 rnA
•

Provisions for Plug-In, Optically
Isolated Receivers, Drivers, and
Terminators

Common Interrupt for up to 8 Sources

• + 5V Supply Only
The iSBC 556 Optically Isolated 1/0 Board provides 48 digital input/output lines with isolation between
process application or peripheral device and the system CPU board(s). The iSBC 556 contains two 8255A
programmable interface devices, and sockets for user supplied optically isolated drivers, receivers, and input
resistor terminators, together with common interrupt logic and interface circuitry for the system bus. Input
signals can be single-ended or differential types with user defined input range (resistor terminator and optoisolated receiver selection), allowing flexibility in design of voltage and threshold levels. The output allows user
selection of Opto-Isolated Darlington Pair which can be used as an output driver either as an open collector or
current switch.

280231-1

10-9

November 1986
Order Number: 280231-001

intJ

iSBC® 556 BOARD

Table 1. 1/0 Ports Opto-Isolator Receivers, Drivers, and Terminators
Port No.
X =1/0
Base
Address

Type
of
1/0

X+O
X+ 1
X+2

Lines
(qty)

Input
Output
Input!
Control
Input
Output
Input! }
Output
Control

X+4
X+5
X+6
X+7

Resistor
Terminator
Pac-Rp 16-Pin DIP
Bourns 4116R-00
or Equivalent

Dual
Opto-Isolator
8-Pin DIP
Monsanto
MCT66
or Equivalent

8
8
8

Driver
7438
or
Equivalent

Pull-Up
iSBC® 902

8
8

1 if input

SPECIFICATIONS

2 if input

1/0 Addressing
8255 #1
8255 #2
Con
ConPort
A l B i c trol A l B i c trol
Address x+0Ix+1Ix+2 X+3 x+4Ix+5Ix+6 X+7

Number of Lines
24 input lines
16 output lines
8 programmable lines: 4 input - 4 output

Where: base address is from OOH to 1FH Gumper
selectable)

1/0 Interface Characteristics

Connectors

Line-to-Line Isolation: 235V DC or peak AC
Input!Output Isolation: 500V DC or peak AC

Mating
Pins Centers
Connectors
qty. in. cm
P1 iSSC bus
86 0.156
Viking
3KH43/9AMK12
J 1 16 fixed input 50 0.1
3M 3415-000 or
& 8 fixed
TI M312125
output lines
J2 8 fixed input, 50 0.1
3M 3415-000 or
8 fixed
TI M312125
output, &8
programmableinputl
output lines
Interface

Terminator PAC
USER·SUPPLIED

DUAL OPT()"ISOlATOR

r - - -

-r-.,-9-~---,

r --I

USER.sUPPL1ED
RESISTOR

~ '-.-,()--~~_-+I_RP-+:

'_6.'_'N_O'-<)P (+)

isac

I-I

D---*=:l =~-330_'=' i!--.. .:.
=*=.

L _____ - ' .

+-:
L~...J
_R'---!.

28023t-2

Rp determines voltage and current range.

Physical Characteristics

Bus Interface Characteristics
All data address and control commands are iSSC 80
bus compatible.

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 12 oz. (397.3 gm)

10-10

iSBC® 556 BOARD

Electrical Characteristics

Reference Manual
502170- iSBC 556 Hardware Reference Manual
(Order Separately)

Average DC Current
Vee = +5V ±5%, 1.0A without user supplied isolated receiver I driver
lee = 1.6A max with user supplied isolator receiverl
driver

Environmental Characteristics

ORDERING INFORMATION
Part Number Description
SBC 556
Optically Isolated 1/0 Board

Temperature: O°C to 55°C
Relative Humidity: 0% to 90%, non-condensing

10-11

inter
•
•
•
•
•

iSBC® 569
INTELLIGENT DIGITAL CONTROLLER

Single Board Digital 1/0 Controller with
up to Four Microprocessors to Share
the Digital Input/Output Signal
Processing
3 MHz 8085A Central Control Processor
Three Sockets for 8041/8741A
Universal Peripheral Interface (UPI-41A)
for Distributed Digital 1/0 Processing
Three Operational Modes
- Stand-Alone Digital Controller
- MULTIBUS® Master
-Intelligent Slave (Slave to MULTIBUS
Master)

for up to 8K Bytes of Intel
• Sockets
2758,2716,2732 Erasable
Programmable Read Only Memory

•
•
•
•
•

2K Bytes of Dual Port Static
ReadlWrite Memory

48 Programmable Parallel 1/0 Lines
with Sockets for Interchangeable Line
Drivers or Terminators
Three Programmable Counters
12 Levels of Programmable Interrupt
Control
Single

+ 5V Supply

MULTIBUS Standard Control Logic
Compatible with Optional iSBC 80 and
iSBC® 86 CPU, Memory, and 1/0
Expansion Boards

The Intel iSBC® 569 Intelligent Digital Controller is a single board computer (8085A based) with sockets for
three 8041A/8741A Universal Peripherals Interface chips (UPI-41 A). These devices, which are programmed
by the user, may be used to offload the 8085A processor from time consuming tasks such as pulse counting,
event sensing and parallel or serial digital I/O data formatting with error checking and handshaking. The iSBC
569 board is a complete digital controller with up to four processors on a single 6.75 inches x 12.00 inches
(17.15 cm x 30.48 cm) printed circuit board. The 8085A CPU, system clock, read/write memory, non-volatile
memory, priority interrupt logic, programmed timers, MULTIBUS control and interface logic, optional UPI processors and optional line driver and terminators all reside on one board.

280232-1

10-12

October 1986
Order Number: 280232-001

inter

iSBC® 569 CONTROLLER

FUNCTIONAL DESCRIPTION
Intelligent Digital Controller
Three Modes of Operation-The iSBC 569 Intelligent Digital Controller is capable of operating in one
of three modes; stand alone controller, bus master,
or intelligent slave.
Stand Alone Controller-The iSBC 569 board may
function as a stand alone, single board controller
with CPU, memory, and I/O elements on a single
board. Five volt ( + 5VDC) only operation allows configuration of low cost controllers with only a single
power supply voltage. The on-board 2K bytes RAM
and up to 16K bytes ROM/EPROM, as well as the
assistance of three UPI-41A processors, allow significant digital I/O control from a single board.
Bus Master-In this mode of operation, the iSBC
569 controller may interface with and control iSBC
expansion memory and I/O boards, or even other
iSBC 569 Intelligent Digital Controllers configured as
intelligent slaves (but no additional bus masters).

Intelligent Slave-The iSBC569 controller can perform as an intelligent slave to any 8- or 16-bit MULTIBUS master CPU by offloading the master of digital control related tasks. Preprocessing of data for
the master is controlled by the on-board 8085A CPU
which coordinates up to three UPI-41A processors.
Using the iSBC 569 board as an intelligent slave,
multi-channel digital control can be managed entirelyon-board, freeing a system master to perform other system functions. The dual port RAM memory allows the iSBC 569 controller to process and store
data without MULTIBUS memory contention.

Simplified Programming
By using Intel UPI-41 A processors for common
tasks such as counting, sensing change of state,
printer control and keyboard scanning/debouncing,
the user frees up time to work on the more important
application programming of machine or process optimization. Controlling the Intel UPI-41 A processors
becomes a simple task of reading or writing com. mand and data bytes to or from the data bus buffer
register on the UPI device.

.......

DUAL

2M RAM

PORT

DUAL

CPU

CONTROL

PORT
BUS

MULTIIUS

280232-2

Figure 1. iSBC® 569 Intelligent Digital Controller Block Diagram

10-13

inter

ISBC® 569 CONTROLLER

Central Processing Unit
A powerful Intel 8085A 8-bit CPU, fabricated on a
single LSI chip, is the central processor for the iSBC
569 controller. The six general purpose 8-bit registers may be addressed individually or in pairs, providing both Single and double precision operations.
The program counter can address up to 64K bytes
of memory using iSBC expansion boards. The 16-bit
stack pOInter controls the addressing of an external
stack. This stack provides sub-routine nesting
bounded only by memory size. The minimum instruction execution time is 1.30 microseconds. The
808SA CPU is software compatible with the Intel
8080A CPU.
..

(EPROMs); in 2K byte increments up to a maximum
of 4K bytes using Intel 2316 ROMs or 2716
EPROMs; in 4K byte increments up to 8K bytes
maximum using Intel 2732 EPROMs; or in 8K byte
increments up to 16K bytes maximum using Intel
2364 ROMs (both sockets must contain same type
ROM/EPROM). All on-board ROM/EPROM operations are performed at maximum processor speed.

Universal Peripheral Interfaces
(UPI-41A)

The iSBC 569 Intelligent Digital Controller utilizes a
triple buS architecture concept. An internal bus is
used for on-board memory and I/O operations. A
MULTIBUS interface is available to provide access
for all external memory and I/O operations. A dual
port bus with controller enables access via the third
bus to 2K bytes of static RAM from either the onboard CPU or a system master. Hence, common
data may be stored in on-board memory and may be
accessed either by the on-board CPU or by system
masters. A block diagram of the iSBC 569 functional
components is shown in Figure 1.

The iSBC 569 Intelligent Digital Controller board provides three sockets for user supplied Intel 8041 AI
8741 A Universal Peripheral Interface (UPI-41 A)
chips. Sockets are also provided for the associated
line drivers and terminators for the UPI I/O ports.
The UPI-41A processor is a single chip microcomputer containing a CPU, 1K byte of ROM (8041 A) or
EPROM (8741 A), 64K bytes of RAM, 16 programmabie I/O lines, and an 8-bit timer/event counter.
Special interface registers included in the chip allow
the UPI-41A processor to function as a slave processor to the iSBC 569 controller board's 8085A
CPU. The UPI processor allows the user to specify
algorithms for controlling peripherals directly thereby
freeing the 808SA for other system functions. For
additional information, including UPI-41 A instructions, refer to the UPI-41 User's Manual (Manual No.
9800504).

RAM Capacity

Programmable Timers

The iSBC 569 board contains 2K bytes of read/write
memory using Intel 2114 static RAMs. RAM accesses may occur from either the iSBC 569 controller or
from any other bus master interfaced via the MULTIBUS system bus. The iSBC 569 board provides addressing jumpers to allow the on-board RAM
to reside within a one megabyte address space
when accessed via the system bus. In addition, a
switch is provided which allows the user to reserve a
1K byte segment of on-board RAM for use by the
8085A CPU. This reserved RAM space is not accessible via the system bus and does not occupy any
system address space.

The iSBC 569 Intelligent Digital Controller board provides three independently programmable interval
timer/counters utilizing one Intel 8253 Programmable Interval Timer (PIT). The Intel 8253 PIT provides
three 16-bit BCD or binary interval timer/counters.
Each timer may be used to provide a time reference
for each UPITM processor or for a group of UPI processors. The output of each timer also connects to
the 8259A Programmable Interrupt Controller (PIC)
providing the capability of timed interrupts. All gate
inputs, clock inputs, and timer outputs of the 8253
PIT are available at the I/O ports for external access.

Bus Structure

Timer Functions-In utilizing the iSBC 569 control-

EPROM/ROM Capacity
Two sockets for up to 16K bytes of nonvolatile read
only memory are provided on the iSBC 569 board.
Nonvolatile memory may be added in 1K byte increments up to a maximum of 2K bytes using Intel 2758
erasable and electrically reprogrammable ROMs

ler, the systems designer simply configures, via software, each timer to meet systems requirements. The
8253. PIT modes are listed in Table 1. The contents
of each counter may be read at any time during system operation with simple read operations for event
counting applications. The contents of each counter
can be read "on-the-fly" for time stamping events or
time clock referenced program initiations.

10-14

inter

ISBC® 569 CONTROLLER

8259A Interrupts-The eight interrupt sources originate from both on-board controller functions and
the system bus:

Table 1. 8253 Programmable Timer Functions
Function
Operation
Interrupt on
When terminal count is reached,
Terminal Count an interrupt request is generated.
Programmable
One-Shot

UPI-41A Processors-One interrupt from each of
three UPI processor sockets.

Output goes low upon receipt of
an external trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.

8253 PIT-One interrupt from each of three outputs.
MULTIBUS System Bus-one of eight MULTIBUS
interrupt lines may be jumpered to either of two
8259A PIC interrupt inputs.

Rate
Generator

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low-going pulse to the next is N
times the input clock period.
Output will remain high until oneSquare-Wave
Rate Generator half the count has been
completed, and go low for the
other half of the count.

Software
Triggered
Strobe·

Programmable Reset-The iSBC 569 Intelligent
Digital Controller board has a programmable output
latch used to control on-board functions. Three of
the outputs are connected to separate UPI-41A RESET inputs. Thus, the user can reset any or all of the
UPI-41A processors under software control. A fourth
latch output may be used to generate an interrupt
request onto the MULTIBUS interrupt lines.· A fifth
latch output is connected to a light-emitting diode
which may be used for diagnostic purposes.

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Expansion Capabilities

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising edge
on counter trigger input. The
counter is retriggerable.
Event Counter On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
. may read the number of events
occurring after the counting
"window" has been enabled or
an interrupt may be generated
after N counts occur in the
system.

When the iSBC 569 controller is used as a single
board digital controller, memory and 1/0 capacity
may be expanded using Intel MULTIBUS compatible
expansion boards. In this mode, no other bus masters may be in the system. Memory may be expanded to a 64K byte capacity by adding user specified
combinations of RAM boards, EPROM boards, or
combination boards. Input/output capacity may be
increased by adding 1/0 expansion boards. Multiple
iSBC 569 boards may be included in an expanded
system using one iSBC 569 Intelligent Digital Controller as the system master and additional controllers as intelligent slaves.

Interrupt Capability

Intelligent Slave Programming

The iSBC 569 Intelligent Digital Controller provides
interrupt service for up to 12 interrupt sources. Any
of the 12 sources may interrupt the on-board processor. Four interrupt levels are handled directly by
the 8085A CPU and eight levels are serviced from
an Intel 8259A Programmable Interrupt Controller
(PIC) routing an interrupt request output to the INTR
input of the 8085A.

When used as an intelligent slave, the iSBC controller appears as an additional RAM memory module.
System bus masters communicate with the iSBC
569 boards as if it were just an extension of system
memory. To simplify this communication, the user
has been given some specific tools:

8085A Interrupt-Each of four direct 8085A interrupt inputs has a unique vector memory address. An
8085A jump instruction at each of these addresses
then provides software linkage to interrupt service
routines located independently anywhere in the
memory.

Flag Interrupt-The Flag Interrupt is generated any
time a write command is performed by an off-board
CPU to the first location of iSBC 569 RAM. This interrupt provides a means for the master CPU to notify the iSBC 569 controller that it wished to establish
a communications sequence. The flag interrupt is
cleared when the on-board processor reads the first
location of its RAM. In systems with more than one
intelligent slave, the flag interrupt provides a unique

10-15

inter

iSBC@ 569 CONTROLLER

interrupt to each slave outside the normal MULTIBUS interrupt lines (INTO/-INT7/).
RAM-The on-board 2K byte RAM area that is accessible to both an off-board CPU and the on-board
8085A may be configured fo~ system access on any
2K boundary.

1/0 Capacity
Parallel-Timers-Three timers, with independent
gate input, clock input, and timer output user-accessible. Clock inputs can be strapped to an external
source or to an on-board 1.3824 MHz reference.
Each timer is connected to a 8259A Programmable
Interrupt Controller and may also be optionally connected to UPI processors.
'

MULTIBUS@ Interrupts-The third tool to improve
system operation as an intelligent slave. is access to
the MULTIBUS interrupt lines. The iSBC 569 controller can both respond to interrupt signals from an offboard CPU, and generate an interrupt to the offboard .cPU via the system bus.

UPI-I/O--Three UPI-41A interfaces, each with tWo
8-bit I/O ports plus the two UPI Test Inputs. The 8bit ports are user-configurable (as inputs or outputs)
in groups of four.

System Development Capability

Serial-1 TTL compatible serial channel utilizing SID
and SOD lines of on-board 8085A CPU.

Software development for the iSBC 569 Intelligent
Digital Controller board is supported by the Intell~c@
Microcomputer Development System including a
resident macroassembler, text editor; system monitor, a linker, object code locator, and Library Manager. In addition, both PL/M AND FORTRAN language
programs can be compiled to run on the iSBC 569
board. A unique incircuit emulator (ICE-851M ) option
provides the capability of developing and debugging
software directly on the iSBC 569 board., This greatly
simplifies the design, development, ,and debug of
iSBC 569 system software..

SPECIFICATIONS

All communications to the UPI-41A processors, to
the programmable reset latch, to the timers, and .to
the interrupt controller are via read and write commands from the on-board 808SA CPU.

Memory Addressing
On-board' ROM/EPROM-O-07FF (using 2758
EPROMs); O-OFFF (using 2716 EPROMs or 2316
ROMs); 0-1 FFF (using 2732 EPROMs); 0-3FFF (using the 2364 ROMs)

On-board RAM--8000-87FF System' accesrany.
2K increment 00000-FF800 (switch selection); 1K
bytes may be disabled from bus access by switch
selection.

8085ACPU
Word Size:

On-Board Addressing

8, 16 or 24 bits

Cycle Time: 1.30 ,""s ± 0.1 % for fastest executable
instruction; i.e., four clock cycles.
Clock Rate: 3.07 MHz ±0.1%

1/0 Addressing

System Access Time
Dual port memory-725 ns

Memory Capacity

Source

Addresses

8253
UPIO
UPI1
UPI2
PROGRAMMABLE RESET
8259A

OEOH-OE3H
OE4H-OE5H
OE6H-OE7H
OE8H-OE9H
OEAH-OEBH
OECH-OEDH

On-board ROM/EPROM-2K, 4K, 8K, or 16K bytes
of user installed ROM or EPROM.
On-board RAM-2K bytes of static RAM. Fully accessiblefrom on-board 8085A. Separately addressable from system bus.
'

Timer Specifications
Input Frequencies-jumper selectable reference

Off-board expansion-up to 64K bytes of EPROM/
ROM or RAM capacity.

10-16

Internal: 1.3824 MHz ±0.1% (0.723 ,""S,
nominal)
External: User supplied (2 MHz maximum)

infef

iSBC® 569 CONTROLLER

Line Drivers and Terminators

Output Frequencies (at 1.3824 MHz)
Function
Mln 1

Max 1

Real-time
interrupt interval

1.45/Lsec 47.4 msec

Rate Generator
(frequency)

21.09 Hz 691.2 KHz

I/O /Drivers-The following line drivers are all compatible with the 1/0 driver sockets on the iSBC 569
Intelligent Digital Controller.
Driver

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

1. Single 16-bit binary count.

Interfaces
MULTIBUSTM Interface-All signals compatible with
iSBC and MULTIBUS architecture
Parallel I/O-All signals TTL compatible
Interrupt Requests-All TTL compatible
Timer-All signals TTL compatible
Serial I/O-AII signals TTL compatible

NOTE:
I = inverting; NI = non-inverting; OC = open collector.

1/0 Terminators-220n/330n divider or 1 kn pullup (DIP) - user supplied
220U

Connectors
Pins Centers
(qty) (in.)

Interface
Bus

0.156

Parallel 1/0

0.1

Mating Connectors

5V=======:;~,~=====~.!__
1
1

Viking 3KH43/9AMK12

k~J

-o

k~.'

+SV---~W'Ir-.--~--~

280232-3

3M 3415-000 or
TIH312125

Environmental Characteristics
Physical Characteristics
Width:
Depth:
Thickness:
Weight:

Operating Temperature : 0° Cto 55° C (32° Fto 131°F)
Relative Humidity: To 90% without condensation

30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
3.97 gm (14 ounces)

Reference Manual
502180- iSBC 569 Intelligent Digital Controller
Board Hardware Reference Manual (NOT
SUPPLIED)

Electrical Characteristics
DC Power Requirements-+5V @ 2.58A with no
optional devices installed. For each 8741A add 135
rnA. For each 220/330 resistor network, add 60 rnA.
Add the following for each EPROM/ROM installed.
Type
2758
2716
2316E
2732
2364

Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be .ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

+ S.OV Current Requirement
1ROM

2ROM

100mA
100mA
120mA
40 rnA
40 rnA

125mA
125 rnA
240 rnA
55 rnA
55 rnA

ORDERING INFORMATION
Part Number
SBC 569

10-17

Description
Intelligent Digital Controller

inter
•
•
•

iSBXTM 311
ANALOG INPUT MULTIMODULETM BOARD

Low Cost Analog Input Via iSBXTM
MULTIMODULETM Connector
8 Differential/16 Single-Ended, Fault
Protected Inputs
20 mV t05V Full Scale Input Range,
Resistor Gain Selectable

+
•+
•
• Throughput to

Unipolar (0 to 5V) or Bipolar ( - 5V to
5V) Input, Jumper Selectable

12-Bit Resolution Analog-To-Digital
Converter
18 KHz Samples Per Second
Memory

The Intel iSBX 311· Analog Input MULTIMODULE board provides simple interfacing of non-isolated analog
signals to any iSBC board which has an iSBX compatible bus and connectors. The single-wide iSBX 311 plugs
directly onto the iSBC board, providing data acquisition of analog signals from eight differential or sixteen
single-ended voltage inputs, jumper selectable. Resistor gain selection is provided for both low level (20 mV
full scale range) and high level (5 volt FSR) signals. Incorporating the latest high quality IC components, the
iSBX 311 MULTIMODULE board provides 12 bit resolution, 11 bit accuracy, and a simple programming interface, all on a low cost iSBX MULTIMODULE board.
.
.

280233-1

10-18

October 1986
Order Number: 280233-002

intJ

iSBXTM 311 BOARD

FUNCTIONAL DESCRIPTION
The iSBX 311 Analog Input MULTIMODULE board is
a member of Intel's growing family of MULTIMODULE expansion boards, designed to allow
quick, easy, and inexpensive expansion for the Intel
single board computer product line. The iSBX 311
Analog Input MULTIMODULE Board shown in Figure
1, is designed to operate with a variety of microcomputer modules that contains an iSBX bus connector
(P1). The board provides 8 differential or 16 singleended analog input channels that may be jumper-selected as the application requires. The MULTIMODULE board includes a user-configurable gain, and a
user-selectable voltage input range (0 to + 5 volts,
or - 5 to + 5 volts). The MULTIMODULE board receives all power and control Signals through the
iSBX bus connector to initiate channel selection,
sample and hold operation, and analog~to-digital
conversion.

Input Capacity
Sixteen separate analog signals may be randomly or
sequentially sampled in single-ended mode with the
sixteen input multiplexers and a common ground.

For noisier environments, differential input mode can
be configured to achieve 8 separate differential signal inputs, or 16 pseudo-differential inputs.

Resolution
The iSBX 311 MULTIMODULES provide 12-bit resolution with a successive approximation analog-todigital converter. For bipolar operation (- 5 to + 5
volts) it provides 11 bits plus sign.

Speed
To A-to-D converter conversion, speed is 35 microseconds (28 KHz samples per second). Combined
with the sample and hold, settling times and the programming interface, maximum throughput via the
iSBX bus and into memory will be 54 microseconds
per sample, or 18 KHz samples per second, for a
single channel, a random channel, or a sequential
channel scan. A-to-D conversion is initiated via the
iSBX connector and programmed command from
the iSBC base board. Interrupt on end-of-conversion
is a standard feature to ease programming and timing constraints.

HIGH

IMPEDANCE
BUFFER

AMP
•

8 CHANNEl

<~;

INPUT

MULTIPLEXER

INTR

GAIN
RESISTOR

DIFFERENTIAL
TO
SINGLE
ENDeD

AMP
ANALOG
INPUT
SIGNALS

SIGNAL

GAIN

GROUND

SELECT

•

OFFSET
ADJUST

SAMPLE

•

DATA

HOLD

LINES

AMP

START
CONVERSION

ANO
CHANNEl
SElECTOR
lOGIC

280233-2

Figure 1. iSBXTM 311 Analog Input MULTIMODULETM Board

10-19

inter

iSBXTM 311 BOARD

Accuracy
High quality components are used to achieve 12 bits
resolution and accuracy of 0.035% full scale range
± % LSB. Offset and gain are adjustable to
± 0.024 % FSR ± % LSB accuracy at any fixed temperature between O·C (gain = 1). See specifications
for other gain accuracies.

Gain

SPECIFICATIONS

To allow sampling of millivolt level signals such as
strain gauges and thermocouples, gain is made configurable via user inserted gain resistors up to 250 x
(20 millivolts, full scale input range). User can select
any other gain range from 1 to 250 to match his
application.

The host iSBC microcomputer addresses the iSBX
311 MULTIMOOULE board by executing IN or OUT
instructions to the iSBX 311 MULTIMOOULE as one
of the legal port addresses. Analog-to-digital conversions can be programmed in either of two modes: 1.
start conversion and poll for end-of-conversion
(EOC), or 2. start conversion and wait for interrupt
(INTRO/) at end of conversion. When conversion is
complete as signaled by one of the above techniques, INput instruction read two bytes (low and
high bytes) cOr:ltaining the 12 bit data word plus
status information as shown below.
OUTput Command-Select input channel and start
conversion.
Bit Position
Input Channel

Inputs-S differential. 16 single-ended. Jumper selectable.
Full Scale Input
Voltage Range--5 to +5 volts (bipolar). 0 to +5
volts (unipolar). Jumper selectable.
Gain-User-configurable through installation of two
resistors. Factory-configured for gain of X1.

OPERATIONAL DESCRIPTION

Resolution-12 bits over full scale range (1.22 mV
at 0-5V, 5 p.V at 0-20 mV).
AccuracyGain
1
5
50
250

NOTE:
Figures are in percent of full scale reading. At any fixed
temperature between O· and BO·C, the accuracy is adjustable to ±0.035% of full scale.

I I I I Ic31 c21 C1 I col

7 6 5 43

Dynamic Error-±0.015% FSR for transitions.
Gain TC (at Gain = 1): 30 PPM per degree centigrade (typical); 56 PPM per degree centigrade
(max).

Low/Status Byte 1031021011001Istart/lbusy/IEOc/1
High Byte

Accuracy at 25·C
± 0.035% ± % LSB
± 0.035% ± % LSB
±0.035% ± % LSB
±0.035% ± % LSB

76543210

INput Data-Read converted data and status (low
byte) or Read converted data (high byte). Reads can
be with or without reset of interrupt request line
(INTRO/).
Bit Position

Fastest data conversion and transfer to memory can
be obtained by dedicating the microcomputer to setting the channel address/starting conversion, polling·
the status byte for EOC/, and when it comes true,
read the two bytes of the conversion and send the
start conversion/next channel address command.
For multitasking situations it may be more convenient to use the interrupt mode, reading in data only
after an interrupt signals end of conversion.

I011 I010 I 091 osl 071 061 051 041

10-20

inter

iSBXTM 311 BOARD

Offset TC (In percent of FSRrC):
Gain

Electrical Characteristics (from iSBX
connector)

Offset
0.0018
0.0036
0.024
0.116

5
50
250

vcc = ± 5 volts (± 0.25V), Icc = 250 mAmax
Vdd = + 12 volts (±0.6V), Idd = 50 mAmax
Vss

Offset is measured with user·supplied 10 PPMI'C gain resistors Instal/ed.

-12 volts (±0.6V), Iss

55 mAmax

Environmental Characteristics
Operating Temperature: 0° to 60°C (32° to 140°C)
. to 90% (without condensaRelative Humidity:
tion)

Input Protection- ± 30 volts.
Input Impedance-20 MO (minimum).
Conversion Speed-50 ms (nominal).

Reference Manuals

Common Mode Rejection Rati0-60 db (minimum).

142913- iSBX 311 Analog Input MULTIMODULE
Board Hardware Reference Manual (or.
der separately)

Sample and hold-sample time 15 ms.
Aperture-hold aperture time: 120 ns.

Related Literature

ConnectorsInterface

Pins
(Qty)

Centers
in
cm

P1 iSBX Bus

0.1

J1 8/16
Channels
Analog

0.1

230973-Distributed Control Data Book

Mating
Connectors

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

iSBCiSBX
connector
3m 3415-000 or
0.254 T1 H312125 or
iCS 910 cable
0.254

ORDERING INFORMATION
Part Number Description
SXB 311
Analog Input MULTIMODULE Board

Physical Characteristics
Width: 9.40 cm (3.7 inches)
Length: 6.35 cm (2.5 inches)
Height: 2.03 cm (0.80 inch) MULTIMODULE board
only
2.82 cm (1.13 inches) MULTIMODULE and
iSBC board
Weight: 68.05 gm (2.4 ounces)

10-21

inter
•

iSBXTM 328
ANALOG OUTPUT MULTIMODULETM
BOARD

Low Cost Analog Output Via iS8XTM
MULTIMODULETM Connector

•

8 Channel Output, Current Loop or
Voltage in any Mix

•

4-20 mA Current Loop; 5V Unipolar or
Bipolar Voltage Output

•

12-8it Resolution

•

0.035% Full Scale Voltage Accuracy
@ 25°C

•

Programmable Offset Adjust in Current
Loop Mode

The Intel iSBX 328 MULTIMODULE board provides analog signal output for any intelligent board having an
iSBX compatible bus and connector. The single-wide iSBX 328 plugs directly onto the host board, providing
eight independent output channels of analog voltage for meters, programmable power supplies, etc. Voltage
output can be mixed with current loop output for control of popular 4-20 mA industrial control elements. By
using an Intel single chip computer (8041) for refreshing separate sample-hold amplifiers through a single 12
bit DAC, eight channels are contained on a single MULTIMODULE board for high density and low cost per
channel. High quality analog components provide 12 bit resolution, and slew rates per channel of 0.1V per
microsecond. Maximum channel update rates are 5 KHz on a single channel to 1 KHz on all eight channels.

280234-1

10-22

October 1986
Order Number: 280234-001

infef

iSBXTM 328 BOARD

FUNCTIONAL DESCRIPTION

OPERATIONAL DESCRIPTION

The iSBX 328 MULTlMODULE board, shown in Figure 1 is designed to plug onto any host iSBC microcomputer that contains an iSBX bus connector. The
board uses an Intel 8041 microcontroller to manage
eight analog output channels that may be user-configured through jumpers to operate in either bipolar
voltage output mode (- 5V to + 5V), unipolar voltage output mode (0 to + 5V), or current loop output
mode (4 to 20 mAl applications. Channels may be
individually wired for simultaneous operation in both
current loop output and voltage output applications.
The outputs feed to a 50-pin edge connector (J1) on
the iSBX 328 MULTIMODULE board.

The host iSBC microcomputer addresses the MULTIMODULE board by executing IN or OUT instructions specifying the iSBX 328 MULTIMODULE as a
port address. The iSBX 328 is initialized to select
whether software or hardware offset is to be used
and how many channels will be active. Then a 2 byte
transfer to each active channel sets the 12 bit output
value, the channel selected and the current or voltage mode.

Commands
OUTput Command-Initialization of UPI/iSBX 328

Interfacing through the
Intel iSBX Bus

All data to be output through the MULTIMODULE
board is transferred from the host microcomputer to
the MULTIMODULE board via the iSBX bus connector. The iSBX 328 board accepts the binary digital
data and generates a 12-bit data word for the Digitalto-Analog Converter (DAC) and a four bit channel
decode/enable for selecting the output channel.
The DAC transforms the data into analog signal outputs for either voltage output mode or current loop
output mode. Offsetting of the DAC voltage in current output mode may be performed by the UPI software offset routine or by the hardware offset adjustments included on the board. The MULTIMODULE
board status is available via the iSBX bus connector,
to determine if the UPI is ready to receive updates to
analog output channels.

0 Bit

1N 1N 1,02101100,1
NN: 0,0

0,1
1,0

= unipolar configuration
software currant ollset
= no mixing
= bipolar configuration

last channel
to be output

software current ollset

OUTput Command 7
High Byte
Low Byte

Data Bytes

I--+-If-+-+-+--+-I---l

~~:::S-~:;::::::::::7----J
DAC Data
DAC channel
to receive data
o UPI generates ollset
1 = SBC generates ollset I - - - - - - - - . J
In current loop mode

280234-3

CURRENT·TO·VOL TAGE
,-----,

AMP

DIGITAL·TO
ANALOG

INTEL"
8041A
UPI'

CONVERTER
12·81T
RESOLUTION

SAMPLE/HOLD
CAPACITOR

MUL TtPLEXER CONTROL

DEMULTI,
PLEXER

280234-2

Figure

iSBC® 328 Analog Output MULTIMODULETM Board Block Diagram
10-23

inter

iSBXTM 328 BOARD

INput Command-Status Buffer Read

Compliance
Voltage

Resolution

Slew Rate

0.1V per microsecond minimum

5 KHz

1 KHz

Single Channel
Update Rate
Eight Channel
Update Rate

280234-4

Output Impedance- 0.1 n. Drives capacitive loads
up to 0.05 microfarads. (approx. 1000 foot cable)

Interrupts
No interrupts are issued from the iSBX 328 to the
host iSBC microcomputer. Data coordination is handled via iSBC software polls of the status buffer.

Temperature
Coefficient

SPECIFICATIONS
Outputs

8 non-isolated channels,
each independently jumpered for voltage output or
current loop output mode.

Voltage Ranges

0 to + 5V (unipolar operation)
- 5 to + 5V (bipolar operation)

Current Loop
Range

4 to 20 mA (unipolar operation only)

Output Current

± 5 mA maximum (voltage
mode-bipolar operation)
0 to 250.0. with on~board
iSBX power. 1000.0. minimum
with 30 VDC max. external
.
supply

Load Resistance -

12V using on-board iSBX
power. If supplied by user, up
to 30 VDC max
12 bits bipolar or unipolar

-0.005%I"C

Refresh and Throughput Rates··
Refresh 1 channel (no new data):
80 f..ts
Refresh all 8 channels (no new data):
650 f..ts
Update and refresh 1 channel with new
data: firmware program 2
150 f..ts
for each additional channel
130 f..ts
Update and refresh 1 channel with new .
data: firmware program 1 or 3
200 f..ts
for each additional channel
155 f..ts
Update and refresh all 8 channels
(all new data): firmware program 2
1,050 ms
per channel of new data
50 f..ts
Update and refresh all 8 channels
(all new data): firmware program 1or 3
1,280 ms
per channel of new data
80 f..ts
•• All times nominal

AccuracyAmbient
Temp

Mode

Accuracy

Voltage-Unipolar, typical
Voltage-Unipolar, maximum
Voltage-Unipolar, typical
Voltage-Unipolar, maximum

± 0.025% FSR
± 0.035% FSR
± 0.08% FSR
± 0.19% FSR

@25·C
@25·C
@O· to 60·C
@O· to 60·C

Voltage-Bipolar, typical
Voltage-Bipolar, maximum
Voltage-Bipolar, typical
Voltage-Bipolar, maximum

±
±
±
±

@25·C
@25·C
@O· to 60·C
@O· to 60·C

Current Loop, typical
Current Loop, maximum
Current Loop, typical
Current Loop, maximum

± 0.07%
± 0.08%
± 0.17%
±·0,37%

0.025% FSR
0.035% FSR
0.09% FSR
0.17% FSR

10-24

FSR
FSR
FSR
FSR

@25·C
@25·C
@O· t060·C
@O· t060·C

inter

iSBXTM 328 BOARD

Connectors-

Environmental Characteristics

Interface

Pins
(Qty)

Centers
In
em

P1 iSBX Bus

0.1

0.254

iSBCiSBX
connector

J1 8/16
channels
analog

0.1

0.254

3m 3415-000 or
T1 H312125 or
iCS 910 cable

Mating
Connectors

Operating Temperature: O· to 60·C (32· to 140·C)
Relative Humidity:

Reference Manuals" ..
142914- iSBX 328 Analog Output MULTI-MODULE
Board Hardware Reference Manual (Order Separately)
230973-- Distributed Control Modules Databook

Physical Characteristics
Width: 9.40 cm (3.7 inches)
Length: 6.35 cm (2.5 inches)
Height: 1.4 cm (0.56 inch) MULTIMODULE board
only
2.82 cm (1.13 inches) MULTIMODULE and
iSBC board.
Weight: 85.06 gm (3.0 ounces)

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ORDERING INFORMATION
Part Number

Description

SBX328

Analog
Board

Electrical Characteristics
vee

= ±5V (0.25V),

Voo

= ±12V(±0.6V), 100
(voltage mode)

lee

= 140 mA max
= 45 mA max
= 200 mA max

'(current loop
mode
Vss

-12V (±0.6V), Iss

to 90% (without condensation)

= 55 mA max

10-25

Output

MULTIMODULE

.
iSBX™ 350
PARALLEL 1/0 MULTIMODULE™ BOARD
•
•

•

iSBXTM Bus Compatible I/O Expansion

•

Accessed as I/O Port Locations

24 Programmable I/O Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Single

•

iSBX Bus On-Board Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

Three Jumper Selectable Interrupt
Request Source~

+ 5V Low Power Requirement

The Intel iSBX 350 Parallel I/O MULTIMODULE Board is a member of Intel's line of iSBX bus compatible
MULTIMODULE products. The iSBXMULTIMODULE board plugs directly into any iSBX bus compatible host
board offering incremental on-board expansion. The iSBX 350 module provides 24 programmable I/O lines
with sockets for interchangeable line drivers and terminators. The iSBX board is closely coupled to the host
board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS
system traffic for· other system resources. In addition, incremental power dissipation is minimal requiring only
1.6 watts (not including optional driver/terminators).

280235-1

September 1986
Order Number: 280235-001

intJ

iSBXTM 350 BOARD

are brought to a 50-pin edge connector that mates
with flat, woven, or r?und cable.

FUNCTIONAL DESCRIPTION
Programmable Interface

Interrupt Request Generation

The iSBX 350 module uses an Intel 8255A-5 Programmable Peripheral Interface (PPI) providing 24
parallel 1/0 lines. The base-board system software
is used to configure the 1/0 lines in any combination
of unidirectional input! output and bidirectional ports
indicated in Table 1. Therefore, the 1/0 interface
may be customized to meet specific peripheral requirements. In order to take full advantage of the
large number of possible 1/0 configurations, sockets
are provided for interchangeable 1/0 line drivers and
terminators. Hence, the flexibility of the 1/0 interface
is further enhanced by the capability of selecting the
appropriate combination of optional line drivers and
terminators to provide the required sink current, polarity, and driverItermination characteristics for each
application. In addition, inverting bidirectional bus
drivers (8226) are provided on sockets to allow convenient optional replacement to non-inverting drivers (8216). The 24 programmable 1/0 lines, signal
ground, and + 5 volt power Uumper configurable)

Interrupt requests may originate from three jumper
selectable sources. Two interrupt requests can be
automatically generated by the PPI when a byte of
information is ready to be transferred to the base
board CPU (Le., input buffer is full) or a byte of information has been transferred to a peripheral device
(Le., output buffer is empty). A third interrupt source
may originate directly from the user I/O interface (J1
connector).

Installation
The iSBX 350 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nylon hardware to insure the mechanical security of the assembly (see Figure 1 and Figure 2).

USER 110
CONNECTOR _____
INTEL ISBXTII 350
MULTIMODULE TIl
BOARD.

HOST BOARD

~
::;

'.-::<: _
, .' :'
. -::
.... ;:';::

ISBX"
MULTIMODULE
CONNECTOR

280235-2

Figure 1. Installation of iSBXTM 350 Module on a Host Board

10-27

iSBXTM 350 BOARD

1.13 (mIX.)

ISBXN
CONNECTOR
(MALE)

C.;.O_~ _BE_~_~O.;.R. .a

_ _ _......
. (FEMALE)

_ _ _......_S_O_C_K_ET_......_ _--.

o.SOl(mln.)

280235-3

Figure 2. Mounting Clearances (inches)
Table 1. Input/Output Port Modes of Operation
Mode of Operation

Port

Unidirectional

Lines
(qty) .

Input

Output

Bidirectional

Unlatched

Latched &
Strobed

Latched

Latched &
Strobed

Control

X(1)

NOTE:
1. Part of Port C must be used as a control port when either Port A or Port B are used as a latched and strobed input or a
latched and strobed output port or Port A is used as a bidirectional port.

SPECIFICATIONS

1/0 Addressing
8255A-5 Ports

Word Size

PortA
Port B
PortC
Control

Data: 8 Bits

Reserved

iSBX 350 Address
XO orX4
X1orX5
~2orX6

X30rX7
X8 to XF

NOTE:
The first digit of each port lID address is listed as "X"
since it will change dependent on the type of host iSBC
microcomputer used. Refer to the Hardware Reference
Manual for your host iSBC microcomputer to determine the
first digit of the port address.

10-28

iSBXTM 350 BOARD

1/0 Capacity

2201l/3301l USBe 901 OPTION)

2201l

24 programmable lines (see Table 1)
+5V

----~"..---.,l
o

Access Time

1 kll(lSBCii(i20PTKiN)--~~;;---------------

Read: 250 ns max.
Write: 300 ns max.

'\IV\

+5V

28023S-4

NOTE:
Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

Interrupts
Interrupt requests may originate from the programmable peripheral interface (2) or the user specified
liD (1).

Physical Characteristics
Width:
Length:
Height":

Weight:

Interfaces

7.24 cm (2.85 in.)
9.40 cm (3.70 in.)
2.04 cm (0.80 in.) iSBX 350 Board
2.86 cm (1.13 in.)iSBX 350 Board
Host Board
51 gm (1.79 oz)

"See Figure 2

iSBXTM Bus-All signals TTL compatible
Parallel liD-Ali signals TTL compatible

Electrical Characteristics

Parallel Interface Connectors

DC Power Requirements

No. of
Centers Connector
Interface Palrsl
Vendor
(In.)
Type
Pins
Parallel I/O
25/50
Connector

0.1

Female

Parallel I/O
25/50
Connector

0.1

Female
Soldered

Vendor
Part No.
3415·0001
with Ears

GTE 6AD01251A1DD
Sylvania

Power
Requirements

Configuration

+5@320mA

Sockets XU3, XU4, XU5, and XU6 empty (as
shipped).

+5V@500mA

Sockets XU3, XU4, XU5, and XU6 contain
7438 buffers.

+SV@620mA

Sockets XU3, XU4, XUS, and XU6 contain
iSBC 901 termination devices.

NOTE:
Connector compatible with those listed may also be used.

Environmental
Line Drivers and Teminators

Operating Temperature: O°C to

I/O Drivers-The following line drivers and terminators are all compatible with the liD driver sockets on
the iSBX 350.

Reference Manual

Driver
7438
7437
7432
7426
7409
7408
7403
7400

Characteristic

Sink
Current (rnA)

9803191-01-iSBX 350 Parallel liD MULTIMODULE Manual (NOT SUPPLIED)

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

Reference Mam!als may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers. Ave., Santa
Clara, California 95051.

ORDERING INFORMATION

NOTE:
I = Inverting, NI = Non-Inverting, OC = Open Collector

Port 1 has 25 mA totem pole drivers and 1 k!l terminators.

Part Number Description
SBX 350
Parallel liD MULTIMODULE Board

I/O Terminators-220!l/330!l divider or 1 k!l pull
up.

+ 55°C

10-29

iSBX™ 488
GPIBMULTIMODULETM BOARD
•

•

Complete IEEE 488-1978 Talker/
Listener Functions Including:
- Addressing, Handshake Protocol,
Service Request, Serial and Parallel
Polling Schemes

•

Software Functions Built into VLSI
Hardware for High Performance, Low
Cost and Small Size

•

Standard iSBX Bus Interface for Easy
Connection to Intel ISBCTM Boards

Complete IEEE 488-1978 Controller
Functions Including:
- Transfer Control, Service Requests
and Remote Enable

•

IEEE 488-1978 Standard Electrical
Interface Transceivers

•

Five Volt Only Operation

Simple Read/Write Programming

The Intel iSBX 488 GPIB Talker/Listener/Controller MULTIMODULE board provides a standard interface from
any Intel iSBC board equipped with aniSBX connector to over 600 instruments and computer peripherals that
use the IEEE 488-1978 General Purpose Interface Bus. By taking full advantage of Intel's VLSI technology the
single-wide iSBX 488 MULTIMODULE board implements the complete IEEE 488-1978 Standard Digital Interface for Programmable Instrumentation on a single low cost board. The iSBX 488 MULTIMODULE board
includes the 8291A GPIB Talker/Listener, 8292 GPIB Controller and two 8293 GPIB Transceiver devices. This
board represents a significant step forward in joining microcomputers and instrumentation using industry
standards such as the MULTIBUS® system, bus, iSBX bus and IEEE 488-1978. The high performance
iSBX 488 MULTIMODULE board mounts easily on Intel iSBX bus compatible single board computers.
A simple user programming interface for easy reading, writing and monitoring of all GPIB functions is provided.
This intelligent interface minimizes the impact on host processor bandwidth.

143560-1

10-30

October 1986
Order Number: 143580-001

intJ

ISBXTM 488 BOARD

FUNCTIONAL DESCRIPTION

GPIB Talker/Listener Capabilities

The iSBX 488 MULTIMODULE board is a singlewide iSBX bus compatible I/O expansion board that
provides a complete implementation of the IEEE
488-1978 Standard Digital Interface for Programmable Instrumentation. The iSBX 488 MULTIMODULE
board may be configured to be a GPIB controller,
talker, listener or talker/listener. The hardware implementation of the iSBX 488 board takes full advantage of Intel's VLSI capability by using the Intel
8292 GPIB controller, 8291A talker/listener and two
(2) 8293 bus transceivers. All communication between the host iSBC board and the iSBX 488
MULTlMODULE board is executed via the Intel standard iSBX connector. Many of the functions that previously were performed by user software have been
incorporated into VLSI hardware for high performance and simple programming. Both the Intel 8291A
GPIB Talker/Listener device and the 8292 device
can each communicate independently with the host
processor on the iSBC board depending on configuration. Communication from the host iSBC board to
either device on the iSBX 488 board is flexible and
may be either interrupt or poll driven depending on
user requirements. Data transfers to or from the
GPIB may be executed by the host processor's I/O
Read and I/O Write commands or with DMA handshaking techniques for very high speed transfers.

The Intel 8291 A device on the iSBX 488
MULTIMODULE board handles all talker/listener
communications between the host iSBC processor
board and the GPIB. Its capabilities include data
transfer, bus handshake protocol, talker/listener addressing procedures, device clearing and triggering,
service requests, and both serial and parallel polling
schemes. In executing most procedures the iSBX
488 board does not interrupt the microprocessor on
the iSBC processor board unless a byte of data is
waiting on input or a byte is sent to an empty output
buffer, thus offloading the host CPU of GPIB overhead chores.

DEVICE
FUNCTION

ISBX
CONNE CTOR

The GPIB talker/listener functions can be easily programmed using the high level commands made
available by the Intel 8291A on the iSBX 488
MULTI MODULE board. The 8291A device architecture includes eight registers for input and eight registers for output. One each of these read and write
registers is used for direct data transfers. The remaining write registers are used by the programmer
to control the various interface features of the Intel
8291A device. The remaining read registers provide
the user with a monitor of GPIB states, bus conditions and device status.

GPIB INTERFACE
FUNCTIONS

I
I

r--I

BLK

jv--

I "-

8291 A
TALKER
LISTENER

Vt-

DECODE

8282
BUFFER

I
I
~
v

8292
CONTROLLER

ADDRESS, SELECT,
IORlW

8 MHz
CLOCK

bdI

DMA

~INTR

GPIB

TRANSCEIVER
• SUPPORT
LOGIC

l/t

SIMPLE PROGRAMMING INTERFACE

VL
8293
XCVR

'---

TRANSFER

-V

"l
8293
XCVR

SYSTEM
CONTROL

" Ir-

"
A

"
I

DATA

MGMT.

"'-'

JUMPER
LOGIC

-rALKeRLISTENER
ADDRESS

143580-2

Figure 1. iSBXTM 488 MULTIMODULETM Board Block Diagram

10-31

inter

iSBXTM 488 BOARD

SOFTWARE FUNCTIONS BUILT INTO VLSI
HARDWARE

Additional features that. have migrated from discrete
logic and software into Intel VLSI include programmable data transfer rate and three addressing
modes that allow the iSBX board to be addressed as
either a major or a minor talker/listener with primary
or secondary addressing. The iSBX 488
MULTIMODULE board can be programmatically
configured into almost any bus. talker, listener, or
talker/listener configuration. Writing software to
control these and other iSBX 488 board functions is
simply a matter of reading or writing the control registers.
IEEE 488-1978 Functions(1)
Function

ISBXTM 488
Supported
IEEE Subsets

Source Handshake (SH)
Acceptor Handshake (AH)
Talker (T)
Extended Talker (TE)
Listener (L)
Extended Listener (LE)
Service Request (SR)
Remote Local (RL)
Parallel Poll (PP)
. Device Clear (DC)
Device Trigger (DT)
Controller (C)

SHO, SH1
AHO,AH1
TO through T8
TEO throu'gh TE8
LO through L4
LEO through LE9
SRO, SR1
RLO, RL1
PPO, PP1, PP2
DCO through DC2
DTO, DT1
CO through C28

simultaneous responses. In applications reqUiring
multiple bus controllers, several iSBX 488 boards
may each be configured as a controller and pass the
active control amongst each other. An iSBX 488
board configured for a System Controller has the capability to send Remote Enable (REN) and Interface
Clear (IFC) for initializing the bus to a known state.

GPIB Physical Interface
The iSBX 488 MULTIMODULE board interfaces to
the GPIB using two Intel 8293 bidirectional transceivers. The iSBX 488 board meets or exceeds
all of the electrical specifications defined in
IEEE 488-1978 including bus termination specifications. In addition, for direct connection to the GPIB,
the iSBC 988 cable, a 26 conductor 0.5 meter GPIB
interface cable is also available from Intel. The cable
is terminated with a 26-pin edge connector at the
iSBX end and a 24-pin GPIB connector at the other.
The cable is also supplied with shield lines for simple
grounding in electrically noisy environments.

Installation
The iSBX 488 MULTIMODULE board plugs directly
onto the female iSBX connector available on many
Intel iSBC boards. The MULTIMODULE board is
then secured at one additional point with nylon hardware (supplied) to insure the mechanical security of
the assembly.
.

SPECIFICATIONS
NOTE:
1. For detailed information refer to IEEE Standard Digital
Interface for Programmable Instrumentation published by
The Institute of Electrical and Electronics Engineers, Inc.
1978.

iSBXTM Bus-All signals TTL compatible

Controller Capabilities

26-pin Edge Connector-Electrical levels compatible with IEEE 488-1978.

The GPIB controller functions supplied by the
iSBX 488 board are provided by the Intel 8292 GPIB
controller device. The 8292 is actually an Intel
8041 A eight bit microcomputer that has been preprogrammed to implement all IEEE 488-1978 controller functions. The internal RAM .in the 8041A is
used as a special purpose register bank for the 8292
GPIB Controller. Just as with the 8291A GPIB Talker/Listener device, these registers are used by the
programmer to implement controller monitor, read
and write commands on the GPIB.
When configured as a bus controller the iSBX 488
board will respond to Service Requests (SRQ) and
will issue Serial Polls. Parallel Polls are also issued
to multiple GPIB instrunient devices for receiving

Interface Information

Physical Characteristics
Width: 3.70 in (0.94 cm)
Length: 2.85 in (7.24 cm)
Height: 0.8 in (2.04 cm)
Weight: 3.1 oz (87.8 gm)

GPIB Data Rate*
300K bytes/sec transfer rate with DMA host iSBC
board

10-32

inter

iSBXTM 488 BOARD

SOK bytes Is transfer rate using programmed 1/0
730 ns Data Accept Time
'Data rates are iSBX board maximum. Data rates
will vary and can be slower depending on host
iSBC board and user software driver.

Environmental Characteristics
Operating Temperature: O· to 60·C (32" to 140·F)
Relative Humidity:
Up to 90% R.H. without
condensation.

Reference Manual

Electrical Characteristics

143154-001- iSBX 488 GPIB MULTIMODULE
Board Hardware Reference Manual
(not supplied).

DC Power Requirements: Vee = +S VDC ±S%
lee = 600 milliamps maximum

ORDERING INFORMATION

GPIB Electrical and Mechanical
Specifications
Conforms to IEEE 488-1978 standard electrical levels and mechanical connector standard when purchased with the iSBC 988 GPIB cable.

Part Number Description
SBX488
GPIB MULTIMODULE
SBC988
0.5 meter GPIB cable for iSBX 488
MULTIMODULE Board

10-33

Local Area Network
Boards and Software

iRMX® NETWORKING SOFTWARE RELEASE 2.0
MEMBER OF THE OpenNf;TTM PRODUCT FAMILY
•

Provides Transparent Network File
Access
- Remote Files can be Accessed Just
Like Local Files
- Network Communications are
Transparent to the User

•

Provides Network File Protection and
User Access Control Mechanisms

•

Connects iRMX, DOS, XENIX*,
VAX/VMSt, and OpenNETTM NRM
Systems on the LAN
- Runs Under the iRMX® 86 R7 and
iRMX® 286 R2 Operating Systems
- Interoperates with XENIX
Networking Software (XENIX-NET),
Intel OpenNET PC Link with
Microsoft Networks (MS-NET),
VAX/VMS OpenNET, and iN OX
OpenNET Software

•

Supports OpenNET IEEE 802.3
Compatible Hardware and ISO 8073
Software
- iSXMTM 552/552A COMMengine
Boards
- iSBC® 186/51 COMMputer™ Board
- iNA 960/961 Transport Software

• Supports File Server and/or File
Consumer Applications
•

Implements a Distributed Name Server
to Minimize Administrative Effort

The Intel iRMX® Networking Software (iRMX-NET) implements the Network File Access (NFA) protocols to
provide transparent access to files on other systems that are attached to the same Local Area Network (LAN)
and that are running the appropriate Network File Access software. Transparent file access means that
remote files can be accessed as if they were local because the OpenNETTM software does the necessary
network communications for the user.
A seven layer OSI communication system solution is established on an iRMX system when the iRMX Networking Software is used in conjunction with the Intel iNA 960/961 Transport Software plus hardware such as the
iSXMTM 552A or the iSBC® 186/51 communication processor boards. Networked iRMX systems can serve in
a wide range of applications including real time transaction processing, automated testing, data collection,
communications switching, and process control.
.
'XENIX and MS-DOS are trademarks of Microsoft Corp.
tVAX and VMS are trademarks of Digital Equipment Corp.

"",,,

,."

-~:::-------------------,"

,
,,

NETWORK

I
I
I

---+

,
\

DIRECTION OF RESOURCE REQUESTS

\
231372-1

11-1

April 1987
Order Number: 231372-003

IRMX-NET SOFTWARE

present or as an I/O job if the EIOS is present.
iRMX-NET contains a number of user-defined parameters which must be set up when configuring the
system. These parameters include the number of file
consumers served concurrently, the identification of
which directories are pUblic, and the specification of
various time-out values.

IRMX®-NET FUNCTIONAL OVERVIEW
iRMX-NET provides transparent network file access
by implementing the Network File Access protocols.
The Network File Access protocols provide the ability for local application programs to access remote
files by attaching the remote system as a local file
system device. Then remote files can be 'accessed
by simply using the remote system's name as part of
the file path name.

051
MODEL

The Network File Access protocols were developed
jointly by IBM, Microsoft, and Intel to provide a powerful set of network file access capabilities among a
variety of heterogeneous operating systems. The
Network File Access protocols have been implemented on iRMX with iRMX-NET, on PC/M5-00S*
with MS-NET, on XENIX· with XENIX-NET, on
VAXIVMSt with VAXIVMS OpenNET, and on the
NRM (Network Resource Manager for Intel microprocessor development systems) with iNOX OpenNET software.

SOFlWARE

HARDWARE

7]IRMX Q11 86 OR IRMX 286]
IRMX- NET

]IN.A961

TO LAN
231372-8

Figure 1. Example Configuration using an
ISXMTM 552A COMMenglne as an Intelligent
Front-End Processor

iRMX-NET provides the transparent network file access capability through file consumer and file server
software functions. The file consumer software intercepts file commands from the local application program and transmits them across the LAN to the file
server node where the target file resides. The file
server software receives, interprets, and executes
commands received over the LAN from remote file
consumers. When iRMX-NET is initially installed, the
user has the option of configuring the system to include either or both of the ,file consumer and file
server functions. '

051
MODEL

The iRMX-NET Network File Access service provides functionality for layers 5 through 7 of the OSI
7-layer communications model. The layer 1 through
4 services are provided by iNA 960/961 Transport
Software and IEEE 802.3 compatible controller
boards such as the iSXM 552A or the iSBC 186/51.

SOFlWARE

] IRMXQII86

]

HARDWARE

IRMX- NET

,
INA 960

TO LAN
231372-9

iRMX-NET capabilities can be installed in a variety of
hardware configurations to meet differing system requirements. For example, a "COMMengine" configuration consists of a host processor board executing
iRMX-NET R2.0 under either iRMX 86 or iRMX 286
and an intelligent network controller board executing
iNA 961 Transport Software. Figure ,1 shows an example of a COMMengine configuration with an iSBC
286/12 host board and an iSXM 552A COMMengine
controller board. Also, a single board COMMputer™
system can be implemented with an iSBC 186/51,
board executing both iRMX-NET software and iNA
960 Transport Software under iRMX 86. See
Figure 2.
iRMX-NET is included at iRMX configuration time as
a user job if the Extended I/O System (EIOS) is not
11-2

, Figure 2. Example Configuration using an
ISBCIBl 186/51 COMMputer™

iRMX® FILE SYSTEM OVERVIEW
The iRMX Operating System provides a flexible
structure for managing directories of files on several
different devices. To illustrate some of the capabilities, refer to the example system configuration
shown in Figure 3.
In this example, disk A is the system device. The
system device is the storage device from which the

IRMX-NET SOFTWARE

To access a remote file, the user first attaches the
remote network node as a file system device. Then
remote files can be accessed by designating the remote node logical device name as part of the file
path name.
For example, Figure 4 illustrates two systems on a
local area network, both equipped with iRMX-NET
software. System S1 would access its local files on
disk A with the following iRMX naming convention:

I directorylfilename

231372-10

Directories and Files

The user on S1 can access files on the remote network node, System S2, by first attaching S2 to the
file system with the augmented iRMX command:

Figure 3. IRMX® File System
system is bootstrapped and it is also the default device to which file references are directed. When the
system is initialized, application programs can access directories and files on device A with a hierarchical directory structure. Files on the system device
are accessed with the following iRMX naming convention:

ATIACHDEVICE S2 AS nodename REMOTE
This allows user on system S1 to access the remote
files on System S2 with the simple naming convention:
:nodename:directory/filename

I directoryIfilename
The system device "A" is the default device and
therefore it doesn't have to be specifically identified
in the path name. If the user wishes to access files
on another device, for example "8", that device can
be attached to the file system with the iRMX command:

REt.lOTE LOCAL
riLES
riLES
DISK C

ATIACHDEVICE 8 AS logical name

231372-11

Then files can be directly accessed on the 8 device
with this naming convention:

Figure 4. iRMX®-NET Network File Access

:Iogicalriame:directory/filename

iRMX-NET provides transparent network file access
at the BIOS, EIOS and Human Interface levels of the
iRMX Operating System. This means that all iRMX
user applications that use the 810S, EIOS, or Human Interface file access commands can be used in
a networked environment where the referenced files
may reside at other network nodes on the local area
network.

TRANSPARENT NETWORK FILE
ACCESS
Transparent network file access enables the user
application to manipulate and use remote files as if
they were local. In contrast, a less-sophisticated file
transfer capability typically requires a multi-step process with the application program having to find the
address of the remote system, to move the file to
the local system, to process it, and then to restore it
to the remote system when processing is completed.

NETWORK FILE PROTECTION AND
USER ACCESS CONTROL
The iRMX-NET Network File Access software also
adds the benefits of extensive file security mechanisms across the network.

The benefit transparent network file access provides
is user access to remote files without the need to
transfer the file back and forth from the remote to
the local system. The network communications required to access theremote file are managed by the
iRMX-NET software in a way that is transparent to
the user application.

The file accessing capabilities implemented by the
iRMX-NET OpenNET Network File Access software
extends the file systems of the individual network
nodes into a network hierarchical file system. Within

11-3

inter

iRMX-NET SOFTWARE

the network, any user with appropriate access permissions can access each of the public files on other network nodes through a unique path of the network directory. iRMX-NET allows directories to be
designated as public (accessible from other network
nodes) or private (accessible only locally) when configuring the file server.
In addition, the iRMX Operating System itself offers
the ability to define protection rights for individual
directories and files. The iRMX-NET software provides the ability to extend these file protection privileges to accesses over the local area network. Local
iRMX files and directories can be specified to be
"read only" or "writable." Within the network file
system, these access rights apply to remote files as
well.
iRMX-NET also defines two types of user access
control that allows the network administrator a
trade-off between performance and level Of security.
The first type of protection is called "consumerbased" protection and offers the highest performance for accessing remote files. The second type is
called "server-based" protection and offers the
highest level of security. The two types of user protection rely on an iRMX-NET concept called the
"Administrative Unit." The Administrative Unit (AU)
is a collection of network nodes that have the same
set of users defined. The Administration Unit can
contain only one network node if desired.
The consumer-based mechanism applies to network
nodes within one Administrative Unit. In this case, ,a
user is checked for valid username and password by
the local system, and once this access is gained,
public files on other nodes within the Administrative
Unit can be accessed without further user verification by the destination node. Because of the minimum of administrative overhead, consumer-based

protection is the best performer. However, this
mechanism offers the least protection against malicious users and therefore is best suited for collections of users that are trustworthy and where performance is of particular value.
Server-based protection comes into play for accesses that cross Administrative Unit boundaries. For
these accesses, the remote system whose file is being accessed checks the user identification to confirm authorization before granting access to the public files in its file system. This mechanism offers the
highest level of security.
An example of the Administrative Unit concept and
its use in setting up consumer-based protection and
server-based protection network nodes is shown in
Figure 5. In this example, the networked systems
51, 52, and 53 are all within Administrative Unit # 1
and can access each others files with the consumerbased mechanism. However, if system 52 wishes to
access files on a system in another Administrative
Unit (such as system 54), the server-based mechanism takes effect and the destination system (54)
checks user authorization before granting access to
its public files.

FILE SERVER AND, FILE CONSUMER
IMPLEMENTATION
iRMX-NET implements file access across the network through introducing a new file type, the "remote file." The iRMX Operating System normally
supports physical, stream, and named files through
the respective file drivers contained within the Basic
1/0 System (BIOS). The iRMX-NET file consumer
software adds a new file driver called the Remote
File Driver (RFD). All local commands that reference
remote files are intercepted at the BIOS level and

ADMIN. UNIT 1
ADMIN. UNIT 2

(§
NODES4

-----

~ SERVER
,

, , BASED
ACCESS
PROTECTION

231372-13

Figure 5. Example of iRMX®-NET File Protection Administration
11-4

inter

iRMX·NET SOFTWARE

are redirected through the RFD to the appropriate
remote node on the network. At the remote node,
the iRMX-NET file server software receives commands from the network and forwards them to the
local operating system which then executes the
commands on the remote node's local file system.

accesses the file system through an iRMX Operating
System dependent software module called the Apex
File Access (AFA) Software. The AFA Software receives requests from the File Server Software and,
acting as the remote user, executes the necessary
file operations corresponding to the requests.

Figure 6 shows the implementation of both the file
consumer and file server software in a COMMengine
environment. In a COMMengine environment, the
Multibus Interprocessor Protocol (MIP) Software
provides the interface between, the iRMX-NET Software executing on the host processor board and the
iNA 961 Transport Software executing on the intelligent network controller board.

The User Administration (UA) module maintains the
files used when making additions and deletions of
authorized users and consumer systems within an
Administrative Unit on the network.

DISTRIBUTED NAME SERVER
The Name Server Software provides name-to-network-address mapping for the network' node on
which it is installed. iRMX-NET implements a distributed or "protocol based" name server scheme in
which every node "knows" its own name and address. The named network node responds with identification of its address to any name server request
for its name (See Figure 7). The file consumer uses
this mechanism to translate a remote network node
name to a network address when a remote file is.
accessed. As a result, network management is simplified since there is no need to maintain a master
directory file within the network.

When a request for a remote file is made, the Remote File Driver routes the request to the iRMX-NET
File Consumer Software. The File Consumer Software translates the remote rietwork node name into
a network address and then formats network communication messages that are sent by the MIP Software to the iNA 961 Transport Software and then to
the remote network node.
When a file access request is received from the network, the iNA 961 Transport Software routes the request via the MIP Software to the iRMX-NET File
Server Software. The File Server Software in turn

INTELLIGENT NETWORK
CONTROLLER BOARD
HOST PROCESSOR
BOARD

NUCLEUS

OTHER IRMX SUBSYSTEMS
231372-14

Figure 6. IRMX®·NET Software Modules In a COMMengine Environment

11-5

iRMX·NET SOFTWARE

X BROADCASTS: WI:lERE IS B1
STEP 2: B REPLIES:
231372-7

Figure 7. Distributed Name Server Scheme

INTEROPERABILITIES
An iRMX-NET system can transparently access files
resident at remote systems that are configured with
OpenNET NetWork File Access file server software.
iRMX·NET, XENIX·NET, VAXIVMS OpenNET, and
iNDX OpenNET equipped network nodes can act as
file servers.. Likewise, an iRMX-NET equipped network node can act as a file server to other network
nodes that are equipped with OpenNET Network
File Access' file consumer software. iRMX·NET,

VAX/VIolSt

INDX

XENIX NETWORKING
SOFTWARE
SERVER-

VAX/ViolS
OpenNETTM
~ SERVER-

INDX Open NET

IRIolX$

XENIX·

IRIolX- NET
-

XENIX-NET, and Microsoft Networks (MS·NEn
equipped nodes can act as file consumers. See Fig·
ure. ~ for an illustration of these interoperation capa·
bilities. The arrows in the diagram indicate the direc·
tion of resource requests. Table 1. lists the operating
systems and the required networking software that
interoperate with ,iRMX-NET R2.0 when installed
with either the iRMX 86 R7 or iRMX 286 R20perat·
ing Systems.

SERVER-

SERVER -

·f

CONSUMER

)
IRIolX

SERVER

I
-CONSUIolER IRIolX
IRIolX- NET

~CONSUIolER XENIX
XENIX NETWORKING
SOFTWARE

I
~CONSUIolER

IolS-DOS·fPC-DOS
IolS-NET
231372-12

'XENIX and MS·DOS are trademarks of Microsoft Corp.
tvAX and VMS are trademarks of Digital Equipment Corp.

Figure 8. IRMX@·NET R2.0 Interoperablllty with other OpenNETTM Systems

11-6

infef

iRMX-NET SOFTWARE

Table 1. Interoperable Software
Operating System

Table 2. Valid IRMX®-NET R2.0 Compatible
COMMengine Host Boards and Software

Networking Software

XENIX' R3.4

XENIX Networking
Software R2.0

MS·DOS· V3.1-3.2

MS-NET V1.0-1.01

iNDXR3.2

NDS II R3.2
'OpenNETTM File Servers

VAXIVMSt V4.2-4.4

VAXIVMS OpenNET R1.0

iRMX® 86R7
iRMX286R2

iRMX-NET R2.0

iRMX86R6

iRMX-NET R1.0A

COMMenglne
Host
ISBC® Boards:

Host Operating System
IRMX®,86
IRMX® 286
R7
Yes
Yes
Yes
Yes
Yes
No

86/30
86/35
286/10 (A)
286/12
286/20
386/20 '

No
No
No
No
No
No

No
No
Yes
Yes
Yes
Yes

No
No
No
No
No
No

Table 3. iRMX®~NET R2.0 Compatible
COMMengine LAN Controller
Boards and Software

'XENIX and MS-DOS are trademarks of Microsoft Corp.
tvAX and VMS are trademarks of Digital Equipment Corp.

COMMenglne
COMMenglne Hardware
Transport
iSXMTM 552A iSXM 552 ISBC® 186/530
Software:
iNA 961 R1.3
Yes
Yes
No
No
No
No
iNA 961 R2.0

SYSTEM COMPATIBILITIES
iRMX·NET R2.0 is supported by the iRMX 86 R7 and
the iRMX 286 R2 Operating Systems.
iRMX·NET R2.0 operates with the iNA 960 R1.1 or
iNA 961 R1.3 Transport Software and runs in either
COMMputer mode or COMMengine mode.

Table 4. iRMX®-NET R2.0 Compatible
COMMputer™ Boards and Software
COMMputer Hardware
ISBCII!> 186/51
ISBC286/12
with ISBXTM 586

COMMputer™
Software:

iRMX-NET R2.0 operates in a COMMengine environment with a variety of host iSBC boards along
with the iSXM 552 and iSXM 552A LAN controllers.
iRMX-NET R2.0 operates in a COMMputer environment with the iSBC 186/51.

iRMX® 86

R7
R6

Yes
No

No
No

iRMX286

No
No

R1.1
R2.0

Yes
No

No
No

iNA 960

SYSTEM INCOMPATIBILITIES
iRMX-NET R2.0 is NOT supported by the iRMX 86
R6 or iRMX 286 R1 Operating Systems.

MEMORY REQUIREMENTS'

iRMX-NET R2.0 does NOT operate with iNA 961
R1.1 or iNA 960/961 R2.0 Transport Software.

iRMX-NET R2.0 typically requires from90K to 145K
bytes of memory depending on the particular hardware and software configuration.

iRMX-NET R2.0 does NOT operate with the iSBC
186/530 LAN Controller board or with the iSBXTM
586 MULTIMODULETM.
The compatible combinations of COMMengine and
COMMputer hardware and software are shown in
Tables 2,3, and 4.

11-7

intJ

iRMX~NET

ORDERING INFORMATION·

Title

Order Code

Description

RMXNETJSU

Development . license.
pass-through allowed.

RMXNETJRO

OEM license allowing passthrough of iRMX-NET Software with payment of appropriate incorporation fee.

RMXNETRF

Incorporation fee for iRMXNET.

RMXNT961 KITJSU

Development license kit bundling iRMX-NET Software with
the iNA 961 Transport Software. No pass-through allowed..

RMXNETKITJRI

SOFTWARE

iRMX-NET Software bundled
with the iNA 961 Transport
Software and the iSXM 55::!A
LAN controller to provide a
complete IEEE 802.3 LAN
connection for an iRMX Multibus system.

Order
No.

iNA 961 Programmer's.Reference Manual
[for iNA 961 R1.3]

122274

iNA 960 Release 2.0 Programmer's
Reference Manual

149231

iNA 960 Release 2.0 Configuration Guide

149230

iSBC/iSXM 552A IEEE 802.3
Communication Controller User's Guide
[Hardware Reference Manual]

149228

iSBC 552 Ethernet Communications
Controller Hardware Reference Manual

122141

iSBC 186/51 COMMputer Board
Hardware Reference Manual

122330

iSBX 586 MULTI MODULE Ethernet
Communication Controller Hardware
Reference Manual

122290

iSBC 186/530 Ethernet COMMengine
User's Guide

149226

OpenNET PC Link User's Guide

f66664

VAXIVMS OpenNET Hardware and
Transport Software Installation Guide

480070

VAXIVMS OpenNET Networking
Software User's Guide

480071

XENIX Networking Software User's Guide
[forXENIX-NET R2]

135147

XENIX Networking Software Installation
and Configuration Guide
[for XENIX-NET R2]

135146

iNDX OpenNET User's Guide

135848

OpenNET NRM Installation Manual

136883

OpenNET NRM User's Guide

136882

·460255

OpenNET Planning and Design Guide

138444

iRMX Networking Software Users' Guide
[for iRMX-NET R1.0A]

122323

To order Intel Literature, contact your
local Intel sales office or write or cali:

iNA 960 Programmer's Reference Manual
[for iNA 960 R1.1]

122193

iNA 960 Architecture Reference Manual
[for iNA 960 R1.1]

122194

An Intel Software License Agreement (SLA) is required to order-iRMX-NET Software products.
Please consult the current Intel Product Catalog for
complete order code descriptions and licensing information.

RELATED LITERATURE
Title
iRMX Networking Software Release
2.0 User's Guide

Order
No.

Intel Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130
(800) 548-4725

11-8

inletAP.NETTM COMMUNICATIONS SOFTWARE
(MAPNET2.1 AND MAP2.1SXMSW)
MEMBER OF THE OpenNETTM PRODUCT FAMILY
•

Supported by OpenNETTM-Map
Hardware and Software:
- iSBC®554 Token Bus Board
- iNA 960 Communication Software

•

MAPNET2.1 Implements ISOIOSI
Layers 5-7, as Specified by Map
Version 2.1
Designed to Interface with iNA 960 Rei
2.Q-lntel's Transport and Network
Software for Layers 3-4.

•

Provides MAP 2.1 ISO FTAM, Session,
CASE, Network Management/Directory
Services

•

Pre-Configured to Run on Intel's iSBC
554 MAP Board

•

Preconfigured Software Provides
Layers 3-7 of the MAP 2.1
Specifications.

•

Preconfigured Map Software with the
iSBC 554 Board Provides a Seven
Layer Turnkey Solution.

MAPNET2.1, iNA 960 Rei 2.0 and the
iSBC®554 Map Board Provide a Seven
Layer, Modular and Configurable MAP
Solution Based on Intel's OpenNET
Architecture.

MAPNET2.1, iNA 960 Rei 2.0 and the iSBC 554 Map Board are ready-to-use building blocks for OEM suppliers
of networked systems to implement ISO/OSllayers 1-7, as specified by MAP version 2.1. The Intel iSBC 554
board provides the data link and the IEEE 802.4 based physical layer for MULTIBUS® based systems.
MAP-NET is designed to use the services and interface provided by Intel's iNA 960 Rei 2.0 Software package.
iNA 960 Rei 2.0 provides the ISO 8473 network and ISO 8073 transport layers 3 and 4 of MAP 2.1.
MAPNET2.1 provides layers 5-7 of the MAP 2.1 specifications and is designed to run on top of iNA 960 Rei
2.0 on the iSBC 554 board. Together the board and software modules provide a complete, seven layer
configurable MAP solution for OEM's. The MAP-NET software is also available preconfigured with iNA 960 Rei
2.0 to run on the Intel iSBC 554 board. This preconfigured software with the board provides a complete 7 layer
turnkey solution for MAP 2.1.
Figure 1. below indicates how Intel's OpenNET IMAP software and hardware products fit in the ISO/OSI
reference model for MAP.

APPLICATION

PRESENTATION

SESSION

TRANSPORT

NETWORK

DATA LINK
PHYSICAL

191 [i/"".''''
1 I © I'u'""

t.tAP2.1 sxt.tsw
(PRECONfIGURED
t.tAP LAYERS 3 - 7
SOfTWARE)

TURNKEY SOLUTION

SOfTWARE
(LAYERS 5 - 7)

SOfTWARE
(LAYERS 3- 4)

(LAYERS 1- 2)

CONFIGURABLE SOLUTION

231666-1

Figure 1. ISOIOSI Reference Model

11-9

September 1986
Order Number: 231666-002

inter

MAP·NETTM COMMUNICATIONS SOFTWARE

FUNCTIONAL OVERVIEW
The Intel MAPNET2.1 software provides the following services specified by MAP 2.1; the session service, directory services, network management, FTAM
and CASE. These services fit into the upper 3 layers
of the ISOIOSI 7 layer model.
Using the Services of MAP-NET, users can initiate
communications with other users on a MAP LAN,
access information regarding resources available on
a LAN, transfer files across a LAN and address other users on the LAN by logical names rather than
numbered addresses.
MAP-NET is designed to interface with iNA 960 Rei
2.0. iNA 960 Rei 2.0 provides the network and transport protocol that is required by the map specification. Please refer to the iNA 960 data sheet for more
information. The configurable software packages
MAP-NET and iNA 960 Rei 2.0 are designed to run
on the iSBC 554 for a complete, on-board, seven
layer map COMMengine.
MAP2.1 SXMSW is a preconfigured software package that incorporates the functions of MAP-NET and
iNA 960 Rei 2.0. This package provides layers 3-7
and is designed to run on the iSBC 554 for a complete, on-board, seven layer, turnkey MAP
COMMengine.

MAP-NETTM SESSION SERVICES
The MAPNET2.1 software implementation provides
the Session services specified in the MAP version
2.1 specification. The session service is built on top
of the iNA 960 Rei 2.0 transport service. iNA 960 Rei
2.0 provides the class 4 services of the ISO 8073
transport specification and the ISO 8473 network
specification. The Session service supports all of the
services provided by the underlying transport layer.
Besides, the session layer also provides a 'graceful
close' service. This service enables a user to release a session connection without the loss of any
outstanding requests. The 'graceful close' feature is
in addition to the 'abort' method of close provided by
transport.

MAP-NETTM DIRECTORY SERVICES
The MAPNET2.1 Directory Services software maintains a database of network objects such as node
names, user names, etc.... and related properties.
For example, the directory services cim be used to
store the name of a network user and his network

addresses as the properties associated with his
name. A network user or application can query the
directory service to retrieve information from this database. Users can also add or delete objects and
properties from this database.
The Directory Services provided in MAPNET2.1
does the following:
-

Runs on top of CASE
Performs name to address conversion
Maintains a local cache of resolved names

Provides two forms of Directory Service-Client
Service Agent for Local Data Base and Directory
Service Agent for Remote/Master Data Base.
(Can be configured to utilize the host memory
pool)

MAP-NETTM CASE
The MAPNET2.1 Common Application Service Elements (CASE) is built on top of the MAPNET2.1 Session Service.
CASE is designed to support all the services provided by the lower .ISO layers. In addition, MAP 2.1
CASE provides name-to-address translation for the
user. By the use of the CASE service, a process can
make a connection request to a remote process by
using only the names of the processes. CASE takes
these process names supplied by the user and re. solves these names into network addresses and
identification utilizing the services provided by the
MAPNET2.1 Directory Service.
This greatly increases the ease-of-use of network
Services provided by the underlying layers.

MAp·NETTM FILE TRANSFER,
ACCESS AND MANAGEMENT (FTAM)
The FTAM Software in MAPNET2.1 provides remote
file transfer capability. This capability is provided by
the implementation of file request 'Initiator' module
and a file request 'Responder' module. The Initiator
intercepts file commands from the local user and
transmits them across the LAN to the Responder at
the node where the target file resides. The Responder receives. interprets, and executes the command acting as a user on its local node. File transfer
between nodes is made possible by the implementation of a common set of file transfer protocols defined by the ISO FTAMSpecification.

11-10

inter

MAp·NETTM COMMUNICATIONS SOFTWARE

MAP-NETTM NETWORK
MANAGEMENT FUNCTIONS (NMF)

MAP2.1SXMSW-PROCONFIGURED
LAYERS 3-7 MAP 2.1 SOFTWARE

The NMF meets or exceeds the MAP2.1 functionality for net management of each layer. The NMF interfaces to CASE, Session, Transport, Network, and
Data Link layers. It provides three basic services:

MAP2.1 SXMSW preconfigured 7 layer solution supports all seven layers on the iSBC 554 MULTIBUS@
based commengine board. The services that are
supplied by this preconfigured software package are
FTAM, Directory Services, CASE, Session, Transport and Network layers. In order to provide maximum flexibility in interfacing user applications, the
network management facility has been added. The
preconfigured MAP software product is supplied with
iRMX@86 device drivers, user interface utilities and
the 7 laye·r conformance tested software.

Read Net Management Object

Set Net Management Object
Event Notification

The NMF can be configured as a Net Manager for
managing local or remote Net Agents or Net Agent
for use by a remote Network Manager.
MAPNET2.1 FTAM allows a user to:

OPERATING SYSTEM ENVIRONMENT

1)
2)
3)
4)
5)

Figure 2 is a layout of the complete seven layer
commengine. The preconfigured MAP software is
downloaded on the iSBC 554 board. The user utilities can communicate with the seven layer commengine via the MULTIBUS Interface Protocol (MIP).

Create files on a remote node.
Write into files on a remote node.
Read files on a remote ·node.
Delete files on a remote node.
Get file attibutes on a remote node.

To perform the above functions the Initiator module
should be configured in the user's node and the Responder should be configured in the remote target
node. MAP-NET FTAM implementation allows a
node to be 1) a file Initiator only, 2) a file R.esponder
only and 3) both an Initiator and Responder.

MAP-NETTM and iNA 960 Software
MAPNET2.1 is designed to interface with iNA 960
Rei 2.0. iNA 960 Rei 2.0 provides the transport and
network layers as required by the MAP specifications. Table 1 shows some examples of functions
provided by MAPNET2.1 and iNA 960 Rei 2.0.

11-11

MIP is an Intel reliable process to process message
delivery protocol between MULTIBUS processors.
An implementation of the MIP protocol is provided
on the iSBC 554 for communication with the host.
The corresponding MIP/File Access Interface will
have to be provided on the host side for communication with the iSBC 554. The user utilities include Directory Services, File Transfer and Net Management. The MIP/Fite Access Interface is available
from Intel for the iRMX 86 Operating System and
can be easily ported to other operating system environments.

intJ

MAP-NETTM COMMUNICATIONS SOFTWARE

Table 1. MAP2.1SXMSW and MAP-NETTM/iNA 960 Rei 2.0 Services
Application

Presentation
Session

Transport

File Trarisfer, Access and Management (FTAM)
provides remote operations on files (create, read, write, delete, get file attributes)
Common Application Service Elements (CASE)
supports all the services provided by the lower ISO layers
provides name to address translation support
Directory Services
performs name to address conversion
maintains local cache of resolved names
two forms of Directory Service-client Service Agent for local data base and
directory Service Agent for remote (master) data base
Null
Implements subset of ISO session 8327 specified by the MAP 2.1 specifications.
Provides 'Graceful Close'
'graceful Close' allows the closing of a connection without any loss of queued
requests
it enhances the transport provided 'Close' which aborts a connection
\Virtual circuit
open: establish a virtual Circuit database
send connect: actively try to establish a virtual connection
await connect: passively awaits the arrival of a connection request
. send: send a message
receive: post a buffer to receive a message
close: close a virtual circuit
Datagram
send: send a datagram message
receive: post a buffer to receive a datagram message

Network

Internetworking
routing between multiple lans
segmentation/ reassembly
user defined routing tables
Multiple subnets supported
user supplied
802.3, 802.4

Data Link

Transmit: transmit a data link packet
Receive: post a buffer to receive a data link packet
Connect: make a data link logical connection (link
service access point. IEEE802.4)
Disconnect: disconnect a data link logical connection
Change token bus address
Add multicast address
Delete multicast address
Configure TBH

Network
Management

Read/Clear/Set network objects (local/remote):
read/clear/set local or remote MAP-NET/iNA 960 network parameters
Read/Set network memory (local/remote):
read/set memory of the local or a remote station
useful in network debug process
Bootconsumer: requests a network boot server to
load a boot file into this station
Echo: Echo a packet between this station and
another remote station on the network

11-12

inter

MAP-NETTM COMMUNICATIONS SOFTWARE

p----------.
USER
OPERATING
SYSTEM
FILE
ACCESS
INTERFACE

USER UTILITIES

MIP

----------------1------------------i~B~~S

554

BOA RD

MIP

DIRECTORY
SERVICES A
CASE

I-

FlAM
CONSUMER

FlAM
SERVER

PRESENTATION
(NVLL)

«
Z
«

+l
J,m,

SXMSW

SESSION

-TRANSPORT

NElWORK

-DATA LINK

PHYSICAL
231666-2

Figure 2. MAP-NETTM/MAP2.1SXMSW User Interface

Available Literature

iSBC/iSXM 552A Hardware Reference Manual

iNA 960 Release 2.0 Programmers Reference
Manual.

iSBC 554 Hardware Reference Manual

MAP-NET Programmers Reference Manual

iNA 960 Release 2.0 Configuration Guide

RMX-NET Programmers Reference Manual

iNA 960/MAP-NET Installation Guide

iNA 960/961 Rei 2.0 Data Sheet

iSBC 186/51 Hardware Reference Manual

iSBC 554 Data Sheet

iSBC/iSXM 552 Hardware Reference Manual

iSBC 552A Data Sheet

11-13

intJ

MAP-NETTMCOMMUNICATIONS SOFTWARE

ORDERING INFORMATION

Software

Hardware
Part Number Modem Frequencies/Channel Pairs
iSBC 554-1
Transmit: 59.75 to 71.75 MHz/Ch. 3
and 4
Receive: 252 to 264 MHz/Ch. P and Q
iSBC554-2
Transmit: 71.75 to 83.75 MHz/Ch. 4A
and 5
Receive: 264 to 276 MHz/Ch. Rand S
iSBC 554-3
Transmit: 83.75 to 95.75 MHz/Ch. 6
and FM1
Receive: 276 to 288 MHz/Ch. T and U

Code
Description
MAP21SXMSWRO License for preconfigured MAP
2.1 layers 3-7 software ..
MAP32SXMSWRF Incorporation fee for preconfigured MAP 2.1 layers 3-7 software (License required).
MAPNET21 RO
License for configurable MAP
2.1 layers 5-7 software.
MAPNET21 RF
Incorporation fee for configurable MAP 2.1 layers 5-7 software (License required).
iNA 961 R2
Preconfigured transport and internet software for a IEEE
802.3 to IEEE 802.4 router.
Configurable MAP 2.1 layers
iNA 960 R2
3-4 software.

Hardware/Software Packages
Code
Description
MAP554NODEKIT-X Package consists of:
(X = 1, 2 or 3) One iSBC 554-X (X = 1, 2 or
3) and
One MAP21 SXMSWRF.
This kit requires the prior
purchase of
MAP2.1 SXMSWROthe software license.

11-14

iDCM 911-1 INTELLlNKTM
ETHERNET* CLUSTER MODULE
• Eliminates Need for Transceivers and
Ethernet Coaxial Cable for a Local
Cluster of Workstations
.

• Permits Clustering of up to Nine
Workstations in a Smaller Area

• Enables Local Cluster of Nine
Workstations to Connect to Main
Ethernet Cable with Only One
Transceiver

•

• Enables Workstations to be up to 100M
from Main Ethernet Cable
IEEE 802.3/Ethernet Compatible

The IntellinkTM Ethernet Cluster Module is a device used as a means of interconnecting up to nine Ethernet
devices without the need for Ethernet coaxial cable and transceivers. The Intellink module forms a standalone
Ethernet local area network with "interconnection" communication capability. The Intellink module (and attached devices) can optionally be connected to the Ethernet coaxial cable through a single transceiver.

210508-1

/ /

_ _.,...-_,-:EnfE=R;;.::NET=CCMX::;;;..-_ _ _ _ _

TRANSCEMII

UP TO

L ..

RS
_ _.L-_ _ _ _- - ,

INTE~~

210508-2

Figure 1.lntellinkTM Configuration
·Ethernet is a trademark of Xerox Corporation.

11-15

September 1987
Order Number: 210508·003

inter

iDeM 911-1

FUNCTIONAL DESCRIPTION .

Physical Characteristics

Intellink module performs the same functions as a
standard Ethernet transceiver. It buffers receive and
transmit data, detects attempts by two or more stations to gain access to the line simultaneously, sig.nals the presence of a collision to the transmitting
stations, and transmits the jam signal prior to initiation of the random back-off algorithm.

Width:
Height:
Depth:
Weight:

14 in. (35.56 cm)
7.8 in. (19.81' cm)
5.5 in. (13.97 cm)
10 lb. (4~52 kg)

ELECTRICAL CHARACTERISTICS
Ethernet Work Station to IntellinkTM
Interface (WI) Connectors

Input Voltage Range

There are nine WI interface connectors into which
Ethernet-based systems can be connected. Each
connector has the same Signal pairs as does the
equivalent connector on a standard Ethernet transceiver.

(Voltages AC RMS)

r---~---------.

Voltage (1S%)

100V ±15%
120V ±15%
220V ±15%

IntellinkTM Module to Transceiver
. Interface (IT) Connector

240V ±15%

The IT interface connector on the Intellink module is
used to connect the local cluster to the "main"
Ethernet cable through ·a standard transceiver, or
can be left unconnected for standalone operation.
The characteristics of this connector are identical to
an Ethernet system to transceiver cable connector.

NOTE:
The frequency range is 47 to
64 Hz, single phase.

ENVIRONMENTAL
CHARACTERISTICS

Topology

Temperature:

The Intellink module can function in standalone operation in which case it appears as a "zero length
Ethernet segment" for up to nine Ethernet-based
systems, or optionally can be connected to the
"main" Ethernet coaxial cable through a single
transceiver. When connected to the "main" Ethernet coaxial cable, it extends the Ethernet system in- .
terface to the transceiver from 50 meters to 100 meters. (Figure 1).

Humidity:

10·C to 40·C Operating
- 40·C to 70·C Non-Operating
10% to 85% Operating
5% to 9,5% Non-Operating

ORDERING INFORMATION
Part Number Description
iDCM 911-1
Intellink, .IEEE 802.3/Ethernet compatible

11-16

iNA 960/961 RELEASE 2.0
TRANSPORT AND NETWORK SOFTWARE
MEMBER OF THE OpenNETTM PRODUCT FAMILY
• Certified ISO Standard Transport and
Network Layer Software

•

Connection less Transport (Datagram)
Services

•

ISO 8073 Transport Class 4 Services
- Multiple Virtual Circuit Connection
Capability
- Guaranteed Message Integrity
- Data Rate Matching (Flow Control)
- Variable Length Messages
-Expedited Delivery

•

ISO 8473 Network Class 3 Services
- Connectionless Internetworking
Capability
- Supports End·Node Systems
- Supports Internetwork Routers

Data Link Drivers Support Many
Hardware Environments
- IEEE 802.3 Hardware Such as the
iSBC® 186/51, iSXMTM 552(A), and
iSBXTM 586 Boards and Various
Designs Based on the 8086, 8088, or
80186 Processors and the 82586 LAN
Coprocessor
-IEEE 802.4 Hardware such as the
iSBC® 554 Board
- Others Definable by the User

•

Highly Configurable for Multiple System
Environments
- As an iRMX® 86 Job
- As a Stand·Alone Communications
Processor System
- Supports Other Host Operating
System Independent Designs

• Comprehensive Network Management
Services
..,... Collection of Network Usage
Statistics
- Setting and Inspecting of Transport
and Data Link Parameters
- Fault Isolation and Detection
- Boot Server

iNA 960 is a complete transport and network software system plus a comprehensive set of network management functions, data link drivers, and system environment features. It is highly configurable to allow optimized
selection of features, parameters, data link drivers, and memory buffers for a variety of system environments.
iNA 961 is derived from iNA 960. It consists of preconfigured subsets of iNA 960 that are designed to operate
with several specific COMMengine hardware environments. iNA 961 contains preconfigured load files ready
for download to the hardware. Load files are included to support the iSXM 552 and iSXM 552A IEEE 802.3
COMMengines, and the iSBC 554 IEEE 802.4 (MAP) COMMengine.
iNA 960/961 is a mature, flexible, and ready-to-use software building block for OEM suppliers of networked
systems for both technical and commercial applications. Using the iNA 960 software the OEM can minimize
development cost and time while achieving compatibility with a growing number of equipment suppliers adopting the ISO and IEEE standards.

APPLICATION

PRESENTATION

SESSION

TRANSPORT

NETWORK
OATA {

UNK
LAYER

_~~T_A_~I~~ ~~~~R_F~:~__
PHYSICAL DATA LINK

PHYSICAL

NETWORK
MANAGEMENT

~
j-'"'"

TYPICAL INA 960
HARDWARE ENVIRONMENTS

82586

MENTEO

BY INA 96

}

IMPLEMENTED
BY HARDWARE

ISBC"or
ISXMTN 552A
IEEE 802.3
CONTROLLER

80186

~IIIIIIIIIIIIIIII~ {Jiff}
230777-1

11-17

September 1987
Order Number: 230777-004

inter

iNA 960/961

FUNCTIONAL OVERVIEW
Using the ISO seven layer model for network communications, iNA 960 provides the services of layers
four and three, the transport and network layers.
The iNA 960 design is an implementation of the
Class 4 services of the ISO standard 8073 connection oriented transport protocol. The iNA 960 transport layer provides a reliable full-duplex message
delivery service on top of the internetworking capability offered by the network layer. The iNA 960 network layer is an implementation of the Class 3 services of the ISO standard 8473 connectionless network protocol. The network layer allows routing of
information packets between different networks
(each network is called a subnetwork). The network
layer directs information packets to the packet delivery services of the IEEE 802.3 or IEEE 802.4 data
link and physical layer functions.
Consisting of linkable object modules, the iNA 960
software can be configured to implement a range of
capabilities and interface protocols. In addition to re-

liable process-to-process message delivery services, iNA 960 includes a datagram service, internetworking end-node capabilities, internetworking router node capabilities, boot server capabilities, a direct
user access to the data link layer, and a comprehensive network management facility.
iNA 960 also contains a variety of client program
interfaces, data link drivers, and a stand-alone operating system executive. As a result, iNA 960 is highly
configurable to run under the iRMX 86 operating
system, to run under its own operating system executive on an Intel iSXM IEEE 802.3 or IEEE 802.4
network board, or to run on a custom designed controller with an 8086, 8088, or 80186 processor coupled with an 82586 data link coprocessor.
The iNA 960 software also includes a comprehensive network management service. This facility enables the user to monitor and adjust the network's
operation in order to optimize its performance.
For a conceptual block diagram of iNA 960, refer to
Figure 2.

SELECTABLE
INTERFACE
MODULES L..._......I .......-......1

STAND-ALONE
OS
EXECUTIVE

...'I;.,......:===:::;------"l

TRANSPORT . - - -_ _
LAYER
ISO 8073 L..._ _ ___r..L..----...J

NETWORK ....._ _ _.....J:....._ _ _ _...
LAYER
1+----1
ISO 8473 L..._ _ _........L.._ _ _ _......

NETWORK
MANAGEMENT
FUNCTIONS
BOOT
SERVER

SELECTABLE
HARDWARE
DRIVERS

230777-2

Figure 2. iNA 960 Conceptual Block Diagram

11-18

infef

iNA 960/961

TRANSPORT LAYER
The Transport Layer provides message delivery
services between client processes running on computers (network "nodes") anywhere in the network.
Communicating client processes within the network
are identified by a transport address that is a combination of a network address defining the network
node and a transport service access point defining
the interface point through which the client accesses
the transport services. The transport address is supplied by the iNA 960 user for both the local and the
remote client processes that are to be connected.
The iNA 960 transport layer implements two kinds of
message delivery services: virtual circuit and datagram. The virtual circuit services provide a reliable
point-to-point message delivery capability that ensures maximum data integrity and is fully compatible
with the ISO 8073 Class 4 protocol standard. The
datagram service provides a best-effort message
delivery between client processes requiring less
overhead and therefore allows higher throughput
than virtual circuits.
Both the datagram and the virtual circuit services are
optional and can be included when configuring iNA
960.

Virtual Circuit Services
Reliable Delivery: Data is delivered to the destination in the exact order it was sent by the source with
no errors, duplications or losses, regardless of the
quality of service available from the underlying network service.

Expedited Delivery (optional): With this service the
client can transmit up to 16 bytes of urgent data
bypassing the normal flow control. The expedited
data is guaranteed to arrive before any normal data
submitted afterward.

Connection less Transport (Datagram)
Service
The datagram service transfers data between client
processes without establishing a virtual circuit connection. The service is a "best effort" capability and
data may be lost or misordered. Data can be transferred at one time to a single destination or to several destinations (multicast). The iNA 960 datagram
service conforms to the ISO draft standard DIS

8602.

NETWORK LAYER
The network layer of iNA 960 provides the Class 3
connectionless network services specified by the
ISO standard 8473 protocols.
The iNA 960 network layer provides the capability of
connecting multiple different networks (called subnetworks) together and having information packets
from one subnetwork routed to a destination on any
other subnetwork. The network layer thus provides
for two major capabilities:
• Internetworking
• Multiple subnets attached to one node
The iNA 960 network layer allows the user a variety
of configurations. A node can be configured as:

Data Rate Matching (flow control): The Transport
Layer attempts to maximize throughput while conserving communication subsystem resources by
controlling the rate at which messages are sent.
That rate is based on the availability of receive buffers at the destination and its own resources.
Multiple Connection Capability (Process Multiplexing): Several Processes can be simultaneously using
the Transport Layer with no risk that progress or lack
of progress by one process will interfere with others.
Variable Length Messages: The client software can
submit arbitrarily short or long messages for transmittal without regard for the minimum or maximum
network service data unit (NSDU) lengths supported
by the underlying network services.

11-19

• An internet end node belonging to a single subnetwork which is in turn connected to other subnetworks. In this configuration, the end node has
the capability to address other nodes anywhere
on the entire system of subnetworks.
• An internetwork router belonging to two or more
subnetworks. In this case, only the 1$0 ,8473
standard connection less internetworking layer is
configured on the node. The user can select the
addressing and routing algorithms to be used.
The iNA 960 network layer provides a routing algorithm with user changeable routing tables. The
network layer also permits the future addition of
address passing and routing algorithms as standards emerge. A router node can be configured
with a variety of subnet data link and physical layers of mixed media types. The transport layer and
above are not needed by this node.

inter

iNA 960/961

• A mUlti-homed end system which is connected to
two or more subnets. The network layer can provide routing between these subnets. In this case
the transport layer is included and applications
can run on this system and communicate on all
subnetworks connected to it.

NETWORK MANAGEMENT FACILITY
The Network Management Facility provides the user
of iNA 960 with planning, operation, maintenance,
and initialization services described belo'!":
• Planning: This service captures network usage
statistics on the various layers to observe network traffic and to help plan network expansion.
Statistics are maintained by the layers themselves and are made available to users via a program interface with the NMF.

• A single network end node which can address
nodes on one subnetwork only. This gives iNA
960 the transport layer functionality and a null
network layer. The program interface to iNA 960
can be set up to accept the network address for. mat of the ISO 8473 standard or of the previous
draft ISO standard.

• Operation: This service allows the user to monitor
network functions and to inspect and adjust network parameters. The goal is to provide the tools
for performance optimization on the network.

Data Link Drivers
The iNA 960 network layer has a variety of data link
drivers for both IEEE 802.3 and IEEE 802.4 data link
and physical layers. Specifically, IEEE 802.3 hardware drivers are included for the iSBC 186/51
COM Mputer, the iSBC/iSXM .552 and 552A
COMMengines, the iSBX 586 module, and 82586based custom designed systems. An IEEE 802.4
data link driver is also included for the iSBC 554
token-bus MAP board. In addition, a user can add up
to two user written subnetworks (when operating under the iRMX 86 operating system). Communication
between the subnetwork drivers and the network .
layer is via request blocks and is based on the programmatic interface specified by iNA 960.

Router Capabilities
Since iNA 960 includes a wide variety of data link
drivers and a flexibleinternetworking capability,. a
wide variety of internetworking configurations are
supportable.
• With the iSBC 554 board and the iSBX 586 module, an IEEE 802.4 MAP token-bus to IEEE 802.3
Ethernet CSMAlCD router is supported. iNA 961
includes a preconfigured load file for this hardware configuration.
• With the iSBC 186/51 board and theiSBX 586
module, an IEEE 802.3 to IEEE 802.3 router is
supported.
• With the iSBC 186/51 board (which has both an
IEEE 802.3 port and a serial port), the user can
link a separate serial data link driver (such as for
X.25) to the iNA 960 network layer and produce
an IEEE 802.3 to serial link router.
For full internetworking configurations, the user can
set up the routing tables which are used for routing
information packets between subnetworks; The
routing tables can be changed during operation via a
routing management facility. Information packets follow the routing path fixed by the routing table information.

• Maintenance: This service deals with detecting;
isolating, and correcting network faults. It also
provides the capability to determine the presence
of other nodes on the network and the viability of
their connection to the network.
• Initialization: NMF provides initialization and remote loading facilities for remote nodes on the
network.
'
Network management provides distributed management of the network. The user can request any of
the services to be performed on a remote as well as
a local node. The NMF interfaces to every other network layer both to utilize their services and to access
their internal data bases.
In support of the above services, the NMF capabilities include layer management, echo testing, limite~
debugging facilities, and the a~ility to down line load
and dump a remote system.
The NMF software provides a routing management
facility which can be used to change the internetworking routing ,tables. The routing tables are used
by the network layer to route information packets
between subnetworks.
The NMF provides the hooks for MAP-NET software
(which provides layers 5 through 7 support for MAP
networks) to support the network management functions In the MAP 2.1 specification. Thu$, the MAPNET user has a choice of selecting the Intel NMF
network management functions or the MAP network
management functions.
Layer management deals with manipulating the internal database of a layer. The elements of these
data bases are termed objects. Some examples for
objects are the number of collisions, the retransmission timeout limit, the number of packets sent, and
the list of nodes to boot. NMF can examine and
modify objects in a layer's data base.

11-20

inter

iNA 960/961

An echo facility is provided. Using this facility, one
node can determine if another node is present on
the network or not, test the communication path to
that node, and determine whether the remote node
is functional.
NMF enables the user to read or write memory in
any node present on the network. This feature is
provided as an aid to debugging.

for most operations. The only exception is the boot
serVer option which also needs the iRMX 86 Basic
10 System. The iSBX 586 IEEE 802.3 module is supported when iNA 960 runs under the iRMX 86 operating system. Also, the two user defined data link
drivers are supported when iNA 960 runs under the
iRMX 86 operating system. Figures 3 and 4 show
two example hardware configurations supported by
iNA 960 running under the iRMX 86 operating system.

NMF can down line load any system present on the
network. A simple Data Link protocol is used to ensure reliability. This facility can be used to load databases, to boot systems without local mass storage,
or to boot a set of nodes remotely, thus ensuring
that they have the same version of software, etc.
Dumping is an operation equivalent to memory read
from the user's standpoint. However, dumping uses
the Data Link facilities while memory read uses the
transport facilities.

lSac'" 186/51
WITH IRMX" 8&
AND INA 960 R2

EXTERNAL DATA LINK (EDL)
The External Data Link option allows the user to access the Data Link Layer directly instead of having
to go through the network and transport layers. This
flexibility is useful when the user needs custom higher layer software or does not need the Network Layer and Transport Layer services (e.g. when sending
"best effort" messages or running customer'diagnostics).
Through the EDL, the capabilities supporting the
lower layers in iNA 960 are made directly available
to the user. EDL enables the user to establish and
delete data link connections, trarismit packets to individual and multiple receivers, and configure the
data link software to meet the requirements of the
given network environment.
.

230777-6

Figure 3. Configuration using
ISBC® 186/51, iRMX® 86 and iNA 960

IEEE 802.3 NETWORK

ISBCIl Board such a.
the ISBC1l 286/12 Board with
IRMX86 and INA960 Software

SYSTEM ENVIRONMENT
iNA 960 is designed to run on hardware based on
the 8086, 8088, or 80186 microprocessors and the
82586 LAN Coprocessor. The software can be configured to run under the iRMX 86 operating system
or on a dedicated 8086, 8088, or 80186 processor
separately from the host. The following section describes these two operating environments.

iRMX® 86 Operating System
Environment
In this configuration, both the user program and iNA

960 are running under the iRMX 86 operating system. The communications software is implemented
as an iRMX 86 job requiring only the iRMX nucleus

11-21

MULTIBUSIII SYSTEM BUS

230777-7

Figure 4. Configuration using an iSBC® Board
and ISBXTM 586 Controller Module

Operating System Processor
Independent Implementation
iNA 960 is also' capable of operating in a standalone system environment under its own operating
system executive. This mode of operation is appropriate in those systems where the iRMX operating
system is not the primary operating system, where
off-loading the host of the communications tasks is
necessary for performance reasons, or where a cus-

iNA 960/961

tom designed communications front end processor
configuration is being used. iNA 960 can be configured to support such implementations by providing
network services on an 8086, 8088, or 80186 processor that in turn controls an 82586 LAN coprocessor. Figure 5 depicts the conceptual block diagram
of this configuration. The iSBC/iSXM 552, the iSBC/
iSXM 552A, and the iSBC 554 boards are MULTIBUS@ I implementations of this architecture. Figures
6 and 7 depict examples of these implementations.

IEEE 802.4 TOKEN BUS NElWORK

t
ISBC'"

ISBC'"554
running
INA 961

Host Processor'
Board

This approach provides the component and system
designer with an ISO standard cOl')1munications software building block that can be adapted to their system needs with a minimum development effort. For
added flexibility, iNA 960 provides the user with the
alternative of using the iNA 960 interface module or
of writing their own module if necessary.

<
"

I
'"

MULTIBUS I SYSTEM BUS

)

•

230777-4

Figure 7. Configuration using the
iSBC@ 554 and iNA 961

USER INTERFACE
iNA 960 is designed to run both under the iRMX 86
operating system or on a dedicated communications
front end processor separate from the host. In both
environmemts, the user interface is based on exchanging memory segments called request blocks
between iNA 960 and the client. The format and
contents of the request blocks remain the same in
both configurations with only the request block delivery mechanism changing.
.

Request blocks are memory segments containing
the data to be passed from the user to iNA 960
(commands) or from iNA 960 to the user (responses). The iNA 960 request blocks consist of fixed format fields identical across all. user commands and
argument fields unique to the individual commands.
Refer to Figure 8 for the standard request block for.,
mat.
230777-5

Figure 5. In the operating system/processor
independent implementation iNA 960 is running
on a dedicated 8086, 8088 or 80186 processor.

IEEE 802 3 NETWORK

!
ISXM'"552A

ISBC'"
Host Processor

running

Board

INA,961

Issuing an iNA 960 command consists of filling in the
request block fields and transferring the block to iNA '
960 for execution. After processing the command,
iNA 960 returns the request block with one of the
pre-defined response codes placed in the response
code field of the request block. The response code
indicates whether the command was executed successfully or whether an error occurred. By examining
the response code, the user can take appropriate
action for that command.

MULTIBUS I SYSTEM BUS

)

•

230777-3

i=igure 6. Configuration using the
iSXMTM 552A and INA 961

The request block delivery mechanism is the means
by which the host processor and' the communications processor running iNA 960 software exchange
the request blocks. iNA 960 provides three such
mechanisms: the MIP (Multibus Inter-process Protocol), the BCB (Base Control Block), and a user-defined mechanism. The MIP interface is included for
use in systems already supporting this protocol, the
BCB is a simple interface for single host environments, and the user-defined interface accommodates unique application requirements.
11-22

infef

iNA 960/961

FIELDS

WORD/BYTE

Reserved (2)
Length
Userl.D.
Response Port
Return Mailbox Token
Segment Token
Subsystem
Opcode
Response Code

WORD
BYTE
WORD
BYTE
WORD
WORD
BYTE
BYTE
WORD

Arguments

BYTE

•
•
•

FIXED FORMAT
FIELDS
(same for all
commands)

ARGUMENTS
(changes by
command)

Figure 8. iNA 960 Request Block Format

Transport Layer User Interface
The following table summarizes the user commands and the corresponding transport layer responses:
Command

Function

OPEN

Allocates memory for the connection database of a virtual circuit for
connection to be established. The connection database contains data
concerning the connection.

SEND CONNECT
REQUEST

Requests connection to a fully specified remote transport address using
specified ISO connection negotiation options.

AWAIT CONNECT
REQUEST TRAN

Indicates that the transport client is willing to consider incoming connection
requests based on pre-established acceptance criteria.

AWAIT CONNECT
REQUEST USER

Indicates that the transport client is willing to consider incoming connection
requests if the request meets the address and negotiation option criteria it
passed to the client for further consideration.

ACCEPT CONNECT
REQUEST

Indicates that the connection requested by a remote transport service is
accepted by the client.

SEND DATA or
SEND EOM DATA

With this command the client requests the transmission of the data in the
buffers using the normal delivery service of the specified connection.

RECEIVE DATA

Posts normal receive data buffers for a specific connection or for a buffer
pool used by a class of connections.

WITHDRAW RECEIVE
BUFFER

Returns a previously posted receive buffer for use.

SEND EXPEDITED
DATA

Transmits up to 16 bytes of data using the expedited delivery service. The
expedited data is guaranteed to arrive at the destination before any normal
data submitted afterward.

RECEIVE EXPEDITED
DATA

Posts receive data buffers for expedited delivery for a specific connection or
for a pool of buffers used by a class of connections.

11-23

iNA 960/961
Transport Layer User Interface (Continued)
Function

Command
WITHDRAW EXPEDITED
BUFFER

Returns a previously posted expedited delivery receive buffer for use.

Terminates an existing connection or rejects an incoming connection
request. Any normal or expedited data queued up to be sent will not be sent.

AWAIT CLOSE

Requests notification from the client of the termination of a specified
connection.

STATUS

Returns status of the transport service connections.

SEND DATAGRAM

Requests transmission of the data in the buffers using the transport
datagram service.

RECEIVE DATAGRAM

Posts a receive buffer for a specific receiver or a class of receivers to
receive data from a transport datagram.

WITHDRAW
DATAGRAM BUFFER

Returns a previously posted datagram buffer for use.

ADD DATAGRAM
MULTICAST ID

Allows a client to belong to a group and receive datagrams sent to this group
in addition to receiving datagrams specifically addressed to the client.

DELETE DATAGRAM

Allows a client to remove themselves from a multicast group.

Network Management Layer User Interface
Function

Command
READ OBJECT

Returns the value of the specified object to the client.

SET OBJECT

Sets the value of an object as specified by the client.

READ AND CLEAR
OBJECT

Returns the value of the specified object to the client then clears the object.

ECHO

This function is used to determine the presence of a node to test the communication
path to that node and to ascertain the viability and functionality of the remote host
addressed.

UP LINE DUMP

Requests a remote node to dump a specified memory area.

READ MEMORY

Reads memory of the specified network node.

SET MEMORY

Sets memory of the specified network node.

FORCE LOAD

Causes a node to attempt a remote load from another node.

External Data Link Interface
Command
CONNECT

Function
With this command the client establishes a data link connection.

DISCONNECT

Eliminates a previously established connection.

TRANSMIT

Transmits data contained in buffers specified by the client.

POST RECEIVE
PACKET DESCRIPTOR

Allocates memory for maintaining records on receive data buffers; Also may
be used to allocate memory for buffering receive data.

ADD MULTICAST

Adds an address to the list of data link multicast addresses.

REMOVE MULTICAST
ADDRESS

Removes an address from the list of data link multicast addresses.

SET DATA LINK ID

Sets up a unique data link ID for the node.

11-24

iNA 960/961

CONFIGURING iNA 960
iNA 961 contains preconfigured subsets of iNA 960
that are designed to execute on specific hardware
configurations such as the iSXM 552A and the iSBC
554 boards. The preconfigured load files in iNA 961
are ready for downloading to the hardware and
therefore require no software configuration effort by
the customer.
iNA 960 is highly configurable for a variety of system
environments, and it therefore allows configuration
and optimization by the customer. iNA 960 is configurable at the object code level.
In order to adapt iNA 960 to a specific system environment, the user must configure the software to
define the desired functions, to select the appropriate user interface, to set the layer parameters, and
to set up for the specific hardware configuration.
There are a number of capability combinations the
user may elect to implement in their application. At
the transport layer level, the options are virtual circuit service with or without expedited delivery, or datagram service, or both. At the network layer level,
the options are to use the ISO 8473 internet layer or

-MDS SEAlES III
OR

to use a null network layer. At the data link level, the
user may include or exclude the External Data Link
interface.
The Network Management Facility is also optional.
When it is configured in, the user may also include
the boot server module. These capabilities can be
rl)ade available simply by linking in the corresponding software modules. The interface options are also
implemented in a modular fashion. The user links in
the desired module to set up for the iRMX 86 operating system or the operating system independent
configurations.
Layer parameters and configuration options are first
edited into layer configuration files, then assembled
and linked into iNA 960. Layer parameters adjust the
network's operation to match the usage pattern and
the available. resources. For example, within the
Transport Layer, the flow control parameters, the retransmission timer parameters, the transport data
base parameters, etc. can be set via this process.
During the configuration process, the user also sets
up for the required hardware configuration, such as
port addresses, interrupt levels, number of memory
buffers, etc. For the flow diagram of configuring iNA
960,refer to Figure 9.

'----.-----'

OPTIONAL FUNCTIONS
• USER ENVIRONMENT
• LAVER PARAMETERS
CONFIGURATION

• H/W

-86300 AND
iRMX·S6

-UNIVERSAL PROM
PROGRAMMER
IF USER SYSTEM
IS IN FIRMWARE

SOFTWARE
UTILITIES
REQUIRED:
- TEXT EDITOR

-ASM 86
-LINK 86

-LOC.86

230777-9

Figure 9. The Configuration Process for iNA 960
11-25

intJ

iNA 960/961

SPECIFICATIONS

MAP-NET Programmers Reference Manual
(149227 -001)

Hardware Supported
- iSBC 186/51 Communication Computer
- iSBC/iSXM 552 and 552A Ethernet COMMengines

RMX-NET Programmers Reference Manual
(122323-002)

iSBC 554 Token Bus (MAP) COMMengine
iSBX 586 Ethernet Data Link Engine when configured with a supporting iSBC or iSXM board.

Typical Throughput at Transport

Environments:
186/51 and iRMX 86
Operations System
Dedicated 80186/82586
COMMengine

ORDERING INFORMATION
iNA 960 is the order code for the fully configurable
version of iNA 960 with the full ISO standard transport and network services. Licenses are available for
both the object and the source code.
iNA 961 is the order code for a preconfigured version of iNA 960 for the following hardware configurations:

50k to 200k bytes/sec
100k to 300k bytes I
sec

Memory Requirements (in bytes):
Base System
12k plus configurable
buffer memory
Normal Virtual Circuit
18k plus configurable
Option
buffer memory
Expedited Delivery Option 2k
Datagram Option
3k plus data base
memory
ISO 8473 Internet Layer
20k
Null Network Layer
2k
NMFOption
1k to 5k
External Data Link Option
5k
Boot Server Option
5k
Available Literature:
- iNA 960 Release 2.0 Programmers Reference
Manual (149231-001)
-

iNA 960 Release 2.0 Configuration Guide
(149230-001 )

iSBC 186/51
(122136-002)

iSBC/iSXM. 552 Hardware Reference Manual
(122141-002)

iSBC/iSXM 552A Hardware Reference Manual
(149228-001 )

iSBC 554 Hardware Reference Manual (149229001)

Hardware Reference

Manual

Hardware

Network Layer

- iSXM 552 Board
- iSXM 552A Board
- iSXM 552A Board
- iSBC 554 Board
- iSBC 554/iSBX
586 Boards

null
null
internet
internet
internet (router)

# of Virtual

Circuits

30
100
100
100
(no transport)

iNA 960 release 1 is the former version (available
since 1984) of fully configurable iNA 960 software
that conformed with the draft ISO transport standard
(DIS 8073). The network layer is null. Release 1 will
be supported by Intel until all operating system products such as iXNX and iRMX convert to iNA 960
Release 2 transport services.
iNA 961 Release 1 includes preconfigured subsets
of iNA 960 Release 1 for the following hardware
configurations:
Hardware

# of Virtual Circuits

- iSXM 552 Board
- iSXM 552A Board

30
100

Order Code Product

iNA960ESR
iNA960LST
iNA960YRO
iNA961 ZRO
iNA960RF

11-26

Machine Readable Source Code
Human Readable Source Code
Object Code License-Configurable
Object Code License-Preconfigured
Incorporation fee per unit.

inter

iSBC® 186/51
COMMUNICATING COMPUTER
MEMBER OF THE OpenNETTM PRODUCT FAMILY

•
•
•
•

6 MHz 80186 Microprocessor
128K Bytes of Dual-Ported RAM
Expandable On-Board to 256K Bytes
82586 Local Area Network Coprocessor
for EthernetllEEE 802.3 Specifications
Two Serial Interfaces, RS-232C and
RS-422A1RS-449 Compatible

Supports Transport Layer Software
• (iNA
960) and Higher Layer

•
•
•
•
•

Communications Software (such as
iRMX®-NET)

Sockets for up to 192K Bytes of JEDEC
28 Pin Standard Memory Devices
Two iSBXTM Bus Connectors
16M Bytes Address Range of
MULTIBUS® Memory
MULTIBUS Interface for Multimaster
Configurations and System Expansion
Supported by a Complete Family of
Single Board Computers, Peripheral
. Controllers, Digital and Analog I/O,
Memory, Packaging and Software

The iSBC® 186/51 COMMUNICATING COMPUTER, THE COMMputer™, isa member of Intel's OpenNETTM
family of products, and supports Intel's network software. The COMMputer utilizes Intel's VLSI technology to
provide an economical self-contained computer for applications in processing and local area network control.
The combination of the 80186 Central Processing Unit and the 82586 Local Area Network Coprocessor makes
it ideal for applications which require both communication and processing capabilities such as networked
workstations, factory automation, office automation, communications servers, and many others. The CPU,
Ethernet interface, serial communications interface, 128K Bytes of RAM, up to 192K Bytes of ROM, I/O ports
and drivers and the MULTIBUS interface all reside on a single 6.75" x 12.00" printed circuit board.

280207-1

11-27

January 1987
Order Number: 280207-002

intJ

iSBC® 186/51

S~C

MULTIBUS"SYSTEM BUS

280207-2

Figure 1. iSBC® 186/51 Block Diagram

FUNCTIONAL DESCRIPTION

"OPEN SYSTEMS"
ISO MODEL

Communicating Computer
Intel's OpenNET strategy provides the user with
building blocks to implement all seven layers of the
International Standards Organization's .(ISO) Open
Systems Interconnect (OSI) model (see Figure 2.)
The iSBC 186/51 is a part of the OpenNET product
family. The iSBC 186/51 can host iNA 960 transport
layer softWare to provide ISO 8073 class 4 standard
protocol on IEEE 802.3 LAN. In conjunction with the
transparent file access software, iRMX-NET, the
iSBC 186/51 and iNA 960 provide a complete seven
layer communications solution.
The iSBC 18.6/51 board integrates a programmable
processor and communications capability onto one
board, serving both computational and networking
capacities as dictated by the application. The com\TIunications coprocessor (82586) aids in this task by
accomplishing as much of the communications task
as possible before the processor intervenes (thus
reducing the overhead load of the 80186 processor).

11-28

NETWORK
MANAGEMENT

COMMUNICATION
APPLICATION
PRESENTATION
SESSION
TRANSPORT
NETWORK

:}...

DATA LINK

--i ETHERNET I-PHYSICAL

2 } ISSC-186/51
1

280207-3

Figure 2. iSBC® 186/51 Implementation of ISO
Standard Model

intJ

iSBC® 186/51 SBC

The dual capabilities of the iSBC 186/51 board are
useful in three types of applications: (1) as a single
board communicating computer running both user
applications and communications tasks; (2) as one
bus master of a multiple processor board solution
running a portion of the overall user application and
the communications tasks; and (3) as an "intelligent
bus slave" that performs communications related
tasks as a peripheral processor to one or more bus
masters in a communications intensive environment.

Architecture
The iSBC 186/51 board is functionally partitioned
into three major sections: central computer, I/O including LAN interconnect and memory including
shared dual port RAM (Figure 1).
The central computer, an 80186 CPU, provides powerful processing capability. The microprocessor,
together with the on-board PROM/EPROM sites,
programmable timers/counters, and programmable
interrupt control provide the intelligence to manage
sophisticated communications operations on-board
the iSBC 186/51. The timers/counters and interrupt
control are also common to the I/O area providing
programmable baud rates to USARTs and prioritizing interrupts generated from the USARTs. The central computer functions are protected for access by
the on-board 80186 only.
The I/O is centered around the Ethernet access provided by the 82586. All 10 Mbps CSMAlCD protocols can be supported. Included here as well are two
serial interfaces, both of which are fully programmable. In support of the single board computer, two
iSBX connectors are provided for further customer
expansion of I/O capabilities. The I/O is under full
control of the on-board CPU and is protected from
access by other system bus masters.
The third major segment, dual-port RAM memory, is
the key link between the 80186, the Ethernet controller, and bus masters (if any) managing the system functions. The dual-port concept allows a common block of dynamic memory to be accessed by
the on-board 80186 CPU, the on-board Ethernet
controller and off-board bus masters. The system
program can, therefore, utilize the shared dual-port
RAM to pass command and status information between the bus masters and on-board CPU and
Ethernet controllers. In addition, the dual-port concept permits blocks of data transmitted or received
to accummulate in the on-board shared RAM, minimizing the need for a dedicated memory board.

CENTRAL COMPUTER
FUNCTIONALITY
Central Processing Unit
The central processor for the iSBC 186/51 is Intel's
80186 CPU. The 80186 is a high integration 16-bit
microprocessor. It combines several of the most
common system components onto the chip (Le., Direct Memory Access, Interval Timers, Clock generator, and Programmable Interrupt Controller). The
CPU architecture includes four l6-bit Byte addressable data registers, two 16-bit index registers and
two 16-bit memory base pointer registers. These are
accessible by a total of 24 operand addressing
modes for (1) comprehensive memory addressing,
and (2) support of the data structures required for
today's structured, high level languages-as well as
assembly language.

Instruction Set
The 80186 instruction set is a supersetiof the 8086.
It maintains object code compatibility while adding
10 new instructions to the existing 8086 instruction
set. The 80186 retains the variable length instruction
format (including double operand instructions), 8-bit
and 16-bit signed and unsigned arithmetic operators
for binary, BCD and unpacked ASCII data, and iterative word and byte string manipulations. Added instructions include: Block I/O, Enter and Leave subroutines, Push Immediate, Multiply Quick, Array
Bounds Checking, Shift and Rotate by Immediate,
and Pop and Push All.

Architectural Features
A six-byte instruction queue provides prefetching of
sequential instructions and can reduce the 1000 ns
minimum instruction cycle to 333 ns for queued instructions. The stack oriented architecture readily
supports modular programming by facilitating fast,
simple intermodule communication, and other programming constructs needed for asynchronous realtime systems. Using a windowing technique and external logic, the full 16M Bytes addressing range of
the IEEE-796 MULTIBUS Standard is available to
the user. The dynamic relocation scheme allows
ease in segmentation of pure procedure and data for
efficient memory utilization. Four segment registers
(code, stack, data, extra) contain program loaded
offset values which are used to map 16-bit addresses to 20-bit addresses. Each register maps 64K

11-29

inter

iSBC® 186/51 SBC

Bytes at a time and activation of a specific register is
controlled both explicitly by program control, and implicitly by specific functions and instructions. A flag
byte signaling mechanism aids in creating an interprocessor communication scheme. This includes (1)
the ability to set/reset interrupts with MULTIBUS
commands and (2) board reset.

The system software configures each timer independently to select the desired function. Examples of
available functions are shown in Table 1. The contents of each counter may be read at any time during
system operation.

Interrupt Capability
Programmable Timers
The 80186 provides three internal 16-bit programmable timers. Two of these are highly flexible and
are connected to four external pins (two per timer).
They can be used to count external events, time external events,' generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time delay applications. In addition, this third timer can be
used as a prescaler to the other two, or as a DMA
request source. The factory default configuration for
timer 0 is baud rate generator.
The 80130-6 provides three more programmable
timers. One is a factory default baud rate generator
and outputs an 8254 compatible square wave to the
RS232 Channel B. The other two timers are assigned to the use of the Operating System and
should not be altered by the user.

The iSBC 186/51 has two programmable interrupt
controllers (PICs): one in the 80186 component and
one in the 80130-6 component. In the iRMX mode,
the 80186 interrupt controller acts as a slave to the
80130-6. The 80186 interrupt controller in this mode
uses all of its external interrupt pins. It therefore
services only internally generated interrupts (Le.,
three timers, two DMA channels). The 80130-6 interrupt controller operates in the master mode and has
eight prioritized inputs that can be programmed either edge or level sensitive.
The iSBC 186/51 board provides 9 vectored interrupt levels. The highest level is the NMI (Non-Maskable Interrupt) line which is directly tied to the 80186
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Programmable Interrupt Controllers (PIC) provide control and
vectoring for the next eight interrupt levels. As
shown in Table 2, a selection of four priority proc-

Table 1.80186 Programmable Timer Functions
Function

' Operation

Interrupt on
Terminal Count

When terminal count is reached, an interrupt request is generated. This function is
extremely useful for generation of real-time clocks.

Programmable
One-Shot

Output goes low upon receipt of an external trigger edge or software command and
returns high when terminal count is reached. This function is retriggerable.

Rate Generator

Divide by N counter. The output will go low for one input clock cycle, and the period
from one low going pulse to the next is N times the input clock period.

Square-Wave Rate
Generator

Output will remain high until
other half of the count.

Software
Triggered Strobe

Output remains high until software loads count (N). N periods after count is loaded,
output goes low for one input clock period.

Hardware
Triggered Strobe

Output goes low for one clock period N counts after rising edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis, the clock input becomes an input from the external
system. CPU may read the number of events occurring after the counter "window"
has been enabled or an interrupt may be generated after N events occur in the
system.

% the count has been completed, and go low for the

11-30

intJ

iSBC®186/51 SBC

essing modes is available for use in designing request processing configurations to match system
requirements for efficient interrupt servicing with
minimal latencies. Operating modes and priority assignments may be reconfigured dynamically via soft:
ware at any time during system operation. The PIC
accepts interrupt requests from all on-board I/O resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU.

1/0 FUNCTIONALITY
Local Area Network Coprocessor
The 82586 is a local communications controller designed to relieve the 80186 of many of the tasks
associated with controlling a local network. The
82586 provides most of the functions normally associated with the data link and physical link layers of a
local network architecture. In particular, it performs
framing (frame boundary delineation, addressing,
and bit error detection), link management, and data
modulation. It also supports a network management
interface.

Interrupt Request Generation
iSBC 186/51 Interrupt Service requests may originate from 25 sources. Table 3 contains a list of devices and functions supported by interrupts. All interrupts are jumper configurable with either suitcase or
wire wrap to the desired interrupt request level.

The 80186 and the 82586 communicate entirely
through a shared memory space. To the user, the
82586 appears as two independent but communicat-

Table 2. iSBC® 186/51 Programmable Interrupt Modes
Operation

Mode
Fully Nested

Interrupt request line priorities fixed at 0 as highest, 7 as lowest

Special Fully
Nested

Allows multiple interrupts from slave PICs to the master PIC. Used in the case of
cascading where the priority has to be conserved within each slave

Specific Priority

System software assigns lowest priority level. Priority of all other levels based in
sequence numerically on this assignment

Polled

System software examines priority-encoded system interrupt status via interrupt
status register
Table 3. Interrupt Request Sources

Device

Function

Number of
Interrupts

MULTIBUS® Interface

Requests from MULTIBUS resident peripherals or other CPU

8274

Transmit buffer empty, receive buffer full and channel errors

Internal 80186 PIC

Timer 0, 1, 2 outputs (function determined by timer mode) and 2
DMA channel interrupts

82586

Communications processor needs attention

Flag Byte Interrupt

Flag byte interrupt set by MULTIBUS master

Systick

80130-6, iRMX® system timer

Edge to Level Trigger

Converts EDGE interrupts to level interrupts

iSBX® Connectors
MULTIMODULE®

Function detem;ined by iSBX

Bus Fail Safe Timer

Indicates addressed MULTIBUS resident device has not
responded to command within 6 ms

OR-Gate Matrix

Outputs of OR-gates on-board for multiple interrupts

11-31

4
(2 periSBX
connector)

inter

iSBC® .186/51 SBC

reception .resources. In addition, the user can output
the status of all internal registers to facilitate system
design.

ing units: the Command Unit (CU) and the Receive
Unit (RU). The CU executes the commands given by
the 80186 to the 82586. The RU handles all activities related to packet reception, address recognition,
CRC checking, etc. The two are controlled and monitored by the CPU via a shared memory structure
called the System Control Block (SCB). Commands
for the CU and RU are placed into the SCB by the
host processor. Status information is placed into the
SCB by the CU and RU (via the CU). The Channel
Attention and Interrupt lines are used by the CPU
and the 82586 to get the other to look into the SCB.
See Figure 3. The 82586 features a high level diagnostic or maintenance capability. It automatically
gathers statistics on CRC errors, frame alignment
errors, overrun errors, and frames lost due to lack of

Upon initialization, the 82586 obtains the address of
its System Control Block through the Initialization
Root which begins at location OFFFFF6H. See Figure 4. The SCB contains control commands, status
register, pointers to the Command Block List (CBL)
and Receive Frame Area (RFA), and tallies for CRC,
Alignment, DMA Overrun and No Resource errors.
Through the SCB, the 82586 is able to provide
status and error counts for the 8086, execute "programs" contained in the CBL and receive incoming
frames in the Receive Frame Area (RFA).

82586
RECEIVE
UNIT

CHANNEL
ATTENTION

cpu

SERIAL DATA IN

COMMAND
UNIT

I
I

INTERRUPT

,
I

XMIT

SERIAL DATA OUT

l>-

ON-BOARD LOCAL BUS

j>.

MEMORY

SYSTEM
CONTROL
BLOCK

COMMAND
BLOCK
LIST

,
I

RECEIVE
FRAME AREA

280207-4

Figure 3. System Overview

11-32

inter

iSSC® 186/51 SSC

SYSTEM CONTROL BLOCK (SCB)

COMMAND BLOCK LIST (CBL)

82586 CONTROL
COMMANDS

STATUS
POINTERS

ERROR TALLIES
-CRC
-ALIGNMENT
-NO RESOURCE
-DMA OVERRUN

~ECEIVE

FRAME AREA (RFA)

I
I
I
I
I
I

DESCRIPT~

RECEIVE
LIST (RDL)

FREE BUFFER LIST

I
L_~

(F~

___________ -.J

280207-5

Figure 4. 82586 Memory Structures

Serial 1/0

iSBXTM MULTIMODULETM
On-Board Expansion

Two programmable communications interfaces using the Intel 8274 Multi-Protocol Serial Controller
Two 8/16-bit iSBX MULTIMODULE connectors are
(MPSC) are contained on the iSBC 186/51. Two inprovided in the iSBC 186/51 microcomputer.
dependent software selectable BAUD rate genera- '
Through these connectors, additional on-board I/O
tors provide the channels with all the common com. functions may be added. iSBX MULTIMODULE
munications frequencies. The mode of operation (for
boards optimally support functions provided by VLSI
example, Asynchronous, Byte Synchronous or Biperipheral components such as additional parallel
synchronous protocols), data format, control characand serial I/O, analog I/O, small mass storage deter format, parity, and baud rate are all under provice controllers (e.g., cassettes and floppy disks),
gram control. The 8274 provides full duplex, double
and other custom interfaces to meet specific needs.
buffered transmit and receive capability. Parity, overBy mounting direct/yon the single board computer,
run, and framing error detection are all incorporated
less interface logic, less power, simpler packaging,
in the MSPC. The iSBC 186/51 supports operation
higher performance, and lower cost results when
in the polled, interrupt and DMA driven interfaces
compared to other alternatives such as MULTIBUS
through jumper options. The board is delivered preform factor compatible boards. The iSBX connectors
viously configured with channel A in RS-422/RSon the iSBC 186/51 boards provide all signals nec449. Channel B in RS-232C. Channel A may be conessary to interface to the local on-board bus, includfigured to support RS-232C.
ing 16 data lines for maximum data transfer rates.

11-33

intJ

ISBC® 186/51 SBC

iSBC MULTIMODULE boards designed with 8-bit
data paths and using the 8-bit iSBX connector are
also supported on the iSBC 186/51 microcomputers. A broad range of iSBX MULTIMODULE options
are available in this family from Intel. Custom iSBX
modules may also be designed for use on the iSBC
186/51 boards. An iSBX bus interface specification
and iSBX connectors are available from Intel.

MEMORY FUNCTIONALITY

lines. In its simplest application, the MULTIBUS system bus allows expansion of functions already contained on a single board computer (e.g., memory
and digital I/O). However, the MULTIBUS structure
also allows very powerful distributed processing
configurations with multiple processors and intelligent slave I/O, and peripheral boards capable of
solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with
a broad array of board level products, LSI interface
components, detailed published specifications and
application notes.

RAM Capabilities
The iSBC 186/51 COMMputer board contains 128K
Bytes of dual-port dynamic RAM. The on-board
RAM may be expanded to 256K Bytes with the iSBC
304 MULTIMODULE board mounted onto the iSBC
186/51 board. The dual-port controller allows access to the on-board RAM (including RAM MULTIMODULE options) from the iSBC 186/51 board and
from any other MULTIBUS master via the system
bus. Segments of on-board RAM may be configured
as a private resource, protected from MULTIBUS
system access. The amount of memory allocated as
a private resource may be configured in increments
of 25% of the total on-board memory ranging from
0% to 100% (optional RAM MULTIMODULE board
doubles the increment size). These features allow
the multiprocessor systems to establish local memory for each processor and shared system memory
configurations where the total system memory size
(including local on-board memory) can exceed one
megabyte without addressing conflicts.

Universal Memory Sites for Local
Memory
Six 28-pin sockets are provided for the use of Intel's
2732, 2764, 27128, 27256 EPROMs and their respective ROMs. When usJng the 272568, the onboard EPROM capacity is 192K Bytes. Other JEDEC .
standard pinout devices are also supported, includ~
ing byte-wide static RAMs and iRAMs.

Multimaster Capabilities

For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPU's and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 186/51 boards provide full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 186/51 boards or other bus
master, including iSBC 80XX family MULTIBUS compatible 8-bit single board computers, to share the
system bus using a serial (daisy chain) priority
scheme. This allows up to 16 masters to share the
MULTIBUS system bus with an external parallel priority decoder. In addition to the multiprocessing configurations made possible with multimaster capability, it also provides a very efficient mechanism for all
forms of DMA (Direct Memory Access) transfers.

MULTIBUS® SYSTEM BUS AND
MULTIMASTER CAPABILITIES

MISCELLANEOUS FUNCTIONALITY

Overview

Power-Fail Control and Auxiliary
Power

The MULTIBUS system bus is Intel's industry standard microcomputer bus structure. Both 8- and 16bit single board computers are supported on the
MULTIBUS structure with 24 address and 16 data

An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the

11-34

iSSC® 186/51 SSC

protection of RAM contents during system powerdown sequences. An auxiliary power bus is also provided to allow separate power to RAM for systems
requiring battery back-up of read/write memory. Selection of this auxiliary RAM power bus is made via
jumpers on the board.

System Development Capabilities
The development cycle of iSBC186/51 products
can be significantly reduced and simplified by using
either the System 3XX or the Intellec Series Microcomputer Development Systems. The Assembler,
Locating Linker, Library Manager, Text Editor and
System Monitor are all supported by the ISIS-II diskbased operating system. To facilitate conversion of
the 8080Al8085A assembly language programs to
run on the iSBC 186/51 boards, CONV-86 is-available under the ISIS-II operating system.

Run-Time Support
The iRMX 86 Operating System is a highly functional
operating system with a very rich set of features and
options based on an object-oriented architecture. In
addition to being modular and configurable, functions beyond the nucleus include a sophisticated file
management and 110 system, and a powerful human interface.

SPECIFICATIONS
Word Size
Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits

System Clock
6.00 MHz ± 0.1%

In-Circuit Emulator
The Integrated Instrumentation In-Circuit Emulator
(1 2ICE) provides the necessary link between the
software development environment provided by the
Intellec system and the "target" iSBC 186/51 execution system. In addition to providing the mechanism for loading excutable code and data into the
iSBC 186/51 boards, the 121CE-186 provides a sophisticated command set to assist in debugging software and final integration of the user hardware and
software.

Cycle Time

Basic Instruction Cycle
6 MHz-1000 ns
333 n's (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest instruction time (I.e., two clock cycles.)

Memory CapacltylAddressing

PL/M-86 and C-86
PL/M-86 provides the capability to program in algorithmic language and eliminates the need to manage
register usage or allocate memory while still allowing
explicit control of the system's resources when
needed. C-86 is especially appropriate in applications requiring portability and code density. FORTRAN 86 and PASCAL 86 are also available on Intellec or 3XX systems.

Six Universal MemorY Sites support JEDEC 24/28
pin EPROM, PROM, iRAM and static RAM.

Example for EPROM:
Total Capacity
Device

11-35

2732
2764
27128
27256

24K Bytes
48K Bytes
96K Bytes
192K Bytes

Address Range
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

inter

iSBC® 186/51 SBC

On-Board RAM
Board
Total Capacity
iSBC 186/51
128K Bytes

Baud Rates
Address Range
0-1FFFFH

Frequency
(KHz) (S/W
Selectable)

With MULTIMODULETM RAM
Board
iSBC304

Total Capacity
256K Bytes

Address Range
0-3FFFFH

I/O Capacity
Serial-two programmable channels usilig one
8274. iSBX MULTIMODULE-two 8/16-bit iSBX
connectors allow use of up to 2 single-wide modules
or 1 single-wide module and 1 double-wide iSBX
module.
Serial Communications Characteristics
Synchronous -

5-8 bit characters; internal or extemal character synchronization;
automatic sync insertion

Asynchronous -

5-8 bit characters; break character after generation; 1, %, or 2
stop bits; false start bit detection

Baud Rate (Hz)
Synchronous

Asynchronous

+16

+64

153.6

9600

2400

76.8

4800

1200

38.4

38,400

2400

600

19.2

19,200

1200

300

9.6

9,600

600

150

4.8

4,800

300

2.4

2,400

150

1.76

1,760

110

2400

NOTE:
Frequency selected by 1/0 write of appropriate 16-biI frequency factor to baud rate register (80186 timer 0 and
80130 baud timer).

Timers
Input Frequencies
Reference 1.5 MHz ± 0.1 % (0.5 ,..,s period nominal)
Event Rate: 1.5 MHz max.

80186 Output Frequencies/Timing Intervals
Single
Timer/Counter

Function

Dual (Cascaded)
Timer/Counter

Min

Max

Min

Max

Real-Time
Interrupt

667 ns

43.69 ms

667 ns

47.72 minutes

Programmable
One-Shot

1000 ns

43.69 ms

1000 ns

47.72 minutes

Rate Generator

22.889 Hz

1.5 MHz

0:0003492 Hz

1.5 MHz

Square-Wave
Rate Generator

22.889 Hz

1.5 MHz

0.0003492 Hz

1.5 MHz

Software
Triggered Strobe

1000 ns

43.69 ms

1000 ns

47.72 minutes

1.5 MHz

Event Counter

11~36

intJ

iSSC® 186/51 SSC

Interfaces

Compliance

Ethernet- IEEE 802.3 compatible

iSBXTM Bus-IEEE P959 compatible

MULTIBUS®- IEEE 796 compatible

Serial 1/0- RS-232C compatible, configurable as a
data set or data terminal, RS-422A1
RS-449

MULTIBUS®- Master 016 M24 116 VO EL

Connectors
Interface

Double-Sided
Pins

Centers
(In.)

0.1

86 (P1)

0.156

60 (P2)

0.1

Viking
3KH30/9JNK

Ethernet
MULTIBUS SYSTEM

iSBX Bus
8-Bit Data
16-Bit Data
. Serial I/O

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)

Mating
Connectors

AMP87531-5
Viking
3KH43/9AMK12
Wire Wrap

0.1

iSBX960·5

0.1

iSBX960-5

0.1

3M 3452-0001
Flat or
AMP88106-1 Flat

Environmental Characteristics
Operating Temperature: O·C to 55·C
Relative Humidity: 10% to 90% (without condensation)

Depth: 0.70 in. (1.78 cm)
Weight: 18.7 ounces (531 g.)

Electrical Characteristics
DC Power Supply Requirements
Maximum Current
(All Voltages ± 5%)

Configuration

+12

-12

SBC 186/51 as shipped:
Board Total
With separate battery back-up
Battery back-up

7.45A
6.30A
1.15A

40mA
40mA

With SBC-304 Memory Module
Installed:
Board Total
With separate battery back-up
Battery back-up

7.55A
6.30A
1.25A

40mA
40mA

NOTES:
1. Add 150 rnA to 5V current for each device installed in the 6 available Universal Memory Sites.
2. Add 500 rnA to 12V current if Ethernet transceiver is connected.
3. Add additional currents for any SBX modules installed.

11-37

infef

iSBC® 186/51 SBC

Reference Manual

Ordering Information

122330·001-iSBC 186/51 Hardware Reference
Manual (NOT SUPPLIED)

Part Number

Description

SBC 186/51

Communicating Computer

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

11·38

iSBC® 552A AND iSXMTM 552A
IEEE 802.3 COMPATIBLE
COMMUNICATIONS ENGINE PRODUCTS
MEMBER OF THE OpenNETTM PRODUCT FAMILY
•

Provides High-Performance Network
Front-End Processing for All
MULTIBUS® I Systems Regardless of
the Operating System of the Host
-Intelligent Controller with an 8 MHz
80186 Processor and 256K of DRAM
Memory
-IEEE 802.3 Network Port Driven by
the 82586 LAN Coprocessor

•

Can Execute On-Board the Intel iNA
960/961 Software, an Implementation
of Industry Standard ISO 8073
Transport and ISO 8473 Network
Protocols

•

Resident Network Software Can be
Down-Loaded Over the Bus or the LAN

•

On-Board Diagnostic and Boot
Firmware

•

Supported by XNX-NET and RMX-NET
Network File Service Software
Products

•

Available in Two Versions
- iSBC 552A is a Flexible, Intelligent
Communications Controller for IEEE
802.3 LANs
- iSXMTM 552A is a Preconfigured
Controller for Executing iNA 961
Transport and Network Software as
a Fully Qualified System Extension
Module for the System 310 Family
.
Products

The iSBC 552A and iSXM 552A COMMengine products are designed for communications front end processor
applications cOnnecting MULTIBUS I systems onto IEEE 802.3 compatible LANs. COMMengines are dedicated to the communications tasks within' a system allowing the host to spend more time processing user
applications. A I"(lajor advantage of COMMengines is that they can be used to network existing systems and
established designs without forcing the redesign of the entire system architecture.
The iSBC and iSXM 552A boards can be used with any operating system because they require only a high
level interface to communicate with the host (eg. transport commands in the case of the iSxM 552A board).
The result is a powerlul system building block which enables the OEM to network MULTIBUS I based systems
with different operating systems. Applications for the 552A products include networked multiuser XENIX 286
based systems for the office and laboratory, iRMX-based systems for real-time applications, or many other
system applications.

280385-1
September 1986
Order Number: 280385-001

inter

iSBC® 552A AND iSXMTM 552A Boards

THE iSBC® BOARD vs
. THE iSXMTM BOARD
The i5BC 552A version is a board that offers the
hardware necessary for the user to construct an
IEEE 802.3 front-end processor for custom requirements. The Intel iNA 960 ISO standard transport and
network software can be configured and optimized
to run on the iSBC 552A board.

runs the iNA 960/961 transport software and delivers data between user buffers in MULTIBUS I memory arid iNA 960/961 buffers on the i5BC and iSXM
552A boards. iNA 960/961 software is responsible
for the reliable transfer of information across the
IEEE 802.3 compatible network.
The 80186 and 82586 use both synchronous and
asynchronous ready logic. The 80186 chip select
lines are used to select memory mapped 110 locations.

The iSXM 552A version is a product that is preconfigured for Intel's family of System 310 products, includes the necessary internal system cabling, and is
fully qualified to run in System 310 products. The
iSXM 552A board supports the iNA 961 ISO standard transport and network software with no configuration activities required of the customer. iSXM
552A board customers receive the iNA 961 software
through Ii separate purchase of a softwa.re license.

The 80186 supplies the timers and the interrupt controller on the iSBC 552A board. The interrupt controller is used in the fully nested mode. The inputs
and the outputs of the 80186 timers are not connected to external sources and destinations. Timer
clocking and timer interrupts are generated internally
in the 80186.

ARCHITECTURE DESCRIPTION

Memory
The iSBC/iSXM 552A board is equipped with
256K Bytes of zero wait state dynamic RAM and
16K Bytes of EPROM. The EPROM parts (Type
2764) are in two 28-pin sockets (JEDEC 27256 or
27572). The user can substitute parts (Type 27512)
to provide 128K Bytes of EPROM. .

280385,2

Figure 1.ISBCCIil/lSXMTM 552A Architecture
The iSBC and iSXM 552A boards consist of the following major architectural blocks (see Figure 1): an
80186 processor running at 8 MHz, the IEEE 802.3
110 channel based on the 82586 LAN coprocessor,
the on-board memory consisting of ROMs and 256K
of zero wait state dynamic RAM, and the
MULTIBUS I interface.

Processor
The iSBC 552A board contains an 80186 processor
operating at 8 MHz. It is responsible for implement
ing the intelligent interface between the i5BC 552A
board and a host processor. The 80186 processor

The one megabyte address space of the 80186 is
divided intQ four quadrants (see Figure 2). The first
quadrant (0-256K Byte) is reserved for local
EPROM
memory and the
last quadrant
(768-1000K Byte) is reserved for local DRAM memory. The second quadrant (256-512K Byte) is used
for memory mapped 110. The iSBC/iSXM' 552A
board is totally memory mapped. The third quadrant
(512-768K Byte) maps into a 256K Byte MULTIBUS
I window. This window allows the iSBC/iSXM 552A
board to access a total of 16M Byte of MULTIBUS I
memory in 256K Byte segments. The iSBC/iSXM
552A board does not contain any memory which is
accessible by other boards over the MULTIBUS I
system bus;
.
The 256K Byte MULTIBUS I window starts on
64K Byte boundaries anywhere in the 16M Byte
MULTI BUS I memory. The starting location of this
window is determined by a memory mapped 110
latch described in the "iSBC 552A User Interface"
section.
Memory mapped 110 locations are selected by the
PCS and the MCS cootrollines of the 80186 processor.Functions controlled by memory mapped 110
are discussed in the "iSBC 552A User Interface"
section.

11-40

inter

iSBC® 552A AND iSXMTM 552A Boards

MULTIBUS@ I
SYSTEM BUS

80186
ADDRESS SPACE

FFFFFF(H)
FFFFF(H)
EPROM-MEMORY
SPACE
SUPPLIED WITH
TWO 8Kx8
EPROMS (2764)
MAXIMUM IS
TWO 64Kx8
[PROMS (27512)
COOOO(H)

256K

+- ANY 256 K BLOCK

256 K BYTE
MULTlBUS@
WINDOW

80000(H)

ON-BOARD
MEMORY
MAPPED I/O
16M-BYTE
SPACE
40000(H)

DRAM-MEMORY
ADDRESS SPACE
256K BYTES
OF ZERO WAIT
STATE DRAM

00000 ( H)

OOOOOO(H)

280385-3

Figure 2. iSBC® iSXMTM 552A Memory Configuration

IEEE 802.3 Interface
The IEEE 802.3 Interface on the iSBC/iSXM 552A
board is based on the 82586 LAN controller. Data is
transferred between the on-board memory of the
iSBC/iSXM 552A board and the 82586 controller by
82586 initiated DMA. The 82586 initiates the DMA
cycles by activating the HOLD signal to the 80186
processor. The DMA cycle begins when the 80186
processor activates the HOLD ACKNOWLEDGE signal.

Each iSBC/iSXM 552A board is manufactured with a
unique default 48-bit IEEE 802.3/Ethernet network
address stored in an address PROM. This address
PROM is protected by checksum and can be read by
utilizing the on-board memory mapped 1/0. The
82586 can be programmed to have this or any other
Ethernet address.

11-41

intJ

ISBC® 552A AND iSXMTM 552A Boards

MULTIBUS® I Interface
The iSBC/iSXM 552A board can access the MULTIBUS I with an 8- or 16- bit data path and can support
up to 24-address bits. An I/O operation by the
80186 on the iSBC/iSXM 552A board normally accesses the I/O ports on the 80186 that controls the
processor's interrupt controller and timers. MULTIBUS I/O is disabled in this normal operation.
iSBC/iSXM 552A MULTIBUS I/O operations can be
enabled or disabled by writing to memory mapped 1/
control locations (Table 2). When the MULTIBUS
I/O is enabled, the iSBC/iSXM 552A board can write
or read the complete 64K Bytes of I/O space locations.

™

ISBC® AND ISXM
552A
BOARDS
BASE I/O PORT - - .
ADDRESS +3
'.

SCP2

": :

SCPl

SCPO

I/O WRITE

BASE I/O PORT
ADDRESS

•

FLAG BYTE

Figure 3. iSBC@ 552A MULTIBUS@ I
Communication Interface
Table 1

1
2
4

The flag byte port is used by the host processor to
reset the iSBC/iSXM 552A board, to interrupt the
80186 processor, and to reset a MULTIBUS I interrupt generated by the iSBC/iSXM 552A board (Table 1). SCPO-SCP2 are general purpose registers
that the host processor can I/O write to and the
.iSBC/iSXM 552A board can read from. SCPO can
also be preset by hardware jumpers.

iSBC® 552A FUNCTIONAL
DESCR'IPTION

280385-4
Base I/O port address = configurable. If 8-bit 110 is used. base
port address is configurable from O-OFCH. If 16-bit 1/0 Is used.
base port address is configurable from O-OFFFCH.
Flag byte: see Table 1.
SCPO-SCP2: 110 written by host processor and read by 80186
on iSBC and iSXM 552A SCPO can be jumper preset.

Value Written
to Flag Byte Port

A host processor in a system communicates with the
iSBC/iSXM 552A board via a flag byte port and
three other byte registers in the MULTIBUS interface. These registers are called the "System Configuration Pointer" registers (SCPO-SCP2). The flag
byte port and the SCP registers are presented as 4
consecutive MULTIBUS I/O ports to the host proci
essor; The locations of these I/O ports on the MULTIBUS are configurable on the iSBC 552A (Figure 3).
To the 80186 processor on the iSBC/iSXM 552A
board, the three SCP registers are memory mapped
locations.

Action
Resets iSBC 552A Board
Interrupts 80186 on Interrupt
Level 1
Clears a MULTIBUS Interrupt
Previously Generated by the
iSBC 552A Board

The iSBC 552A board is a high performance general
purpose IEEE 802.3 compatible COMMengine designed to offload a host processor in a system from
transport layer and network layer communication
processing. The board, supports user written communications software for unique applications or it
can run Intel's iNA 960/961 transport and network
software in standard applications. When running
iNA 960 software, the iSBC 552A board provides the
host processor with reliable process to process
message delivery. User messages to be sent are
copied by iNA 960 software into iSBC 552A board
local memory for transmission. Packets received
from the network are first buffered and reassembled
into messages on the iSBC 552A board. These received messages are then delivered to the user.
The iSBC 552A board makes use of the functions on
the 82586 controller to implement a number of network functions_ These functions include reprogram- .
ming the iSBC 552A station address, Multicast packet reception filtering, and loopback diagnostics. The
82586 also records a set of network statistics information. Information stored' includes the number of
CRC and alignment errors, the number of occur~
rences of no receive buffer resources and the number of DMA overruns/underruns.
The iSBC 552A can be configured to have a range
of EPROM memory configurations up to 128K Bytes
using 27512's.
The iSBC 552A board and iNA 960 software combination offers a flexible and configurable transport
11-42

inter

ISBCCi!> 552A AND ISXMTM 552A Boards

COMMengine, and allows a user to optimally configure the system for highest performance. The iSXM
552A and iNA 961 combination offers a preconfigured turn-key solution. In both cases, iNA 960/961
software and the 552A significantly reduce the design cycle involved in designing and implementing a
transport COMMengine.
For additional information about iNA 960/961,
please refer to the iNA 960/961 data sheet.

OPERATING ENVIRONMENTS
The iSBC/iSXM 552A is designed to function in any
MULTIBUS I system as a communications processor. It can function as both a MULTIBUS I bus master or a slave. As a MULTIBUS I master, it can access up to 16M Byte of host memory and 64K Byte
of 1/0 address. As a MULTIBUS I slave, it occupies
four consecutive 110 locations on the MULTIBUS I
system memory. These locations are reserved for
the flag byte and the three SCP registers.

iSBC® 552A User Interface
The iSBC 552A board communicates with a host
processor through a handshake of interrupts. The
host processor can generate flag byte interrupts to
the 80186 on the iSBC 552A and the iSBC 552A can
generate MULTIBUS I interrupts to the host processor. The host processor and the iSBC 552A board
can also communicate through shared MULTIBUS I
system memory. None of the on-board buffer on the
iSBC 552A board is accessible to the host processor
but the iSBC 552A can read and write all of the 16M
Byte of MULTIBUS I system memory.
The host processor and the iSBC 552A board further
communicate through the SCP registers. These byte
registers can be I/O written by the host and can be
read through memory mapped 110 by the iSBC 552A
processor.
The 80186 processor controls the iSBC 552A
through memory mapped 110, Functions that are
. controlled are listed in Table 2.

iSXMTM 552A FUNCTIONAL
DESCRIPTION
The iSXM 552A board is offered to operate specifically with the iNA 961 transport and network layer
software. The iSXM 552A firmware provides the capabilities to load iNA 961 onto the 552A from either
a buffer in the local host or remotely from another
IEEE 802.3 network station. It also performs a variety of IEEE 802.3 and on-board diagnostics (see
sections on iNA 961 User Interfaces and Operating
Systems Environment).
iNA 961 software and the iSXM 552A board together
provide the functionality of a preconfigured operating system independent transport engine. In addition
to transport services, iNA 961 software also includes
extensive data link, internetworking, and network
management services, Figure 4 shows the distribution of network seven layer functions between iNA
961/iSxM 552A and the host processor. Table 3
shows some examples of functions provided by iNA
961. Refer to the iNA 960/961 data sheet for more
iNA 961 information.
.

Table 2. ISBC® 552A Memory Mapped Functions
80186 Chip
Select Lines

Read/Write
by 80186

MCS

MULTIBUS I Interface registers
(System Configuration Pointer Registers, see "MULTIBUS Interface" Section)

PCS

W
R
W
W
W

Channel Attention to 82586
Reading iSBC 552A Ethernet Address PROMS
Controlling Loopback of the Serial Interface
Disabling and Enabling MULTIBUS I/O
Generating and Clearing iSBC 552A
Interrupts to the MULTIBUS System Bus
Controlling the On-Board LED
Latches the MULTIBUS Window Segment
(8 most Significant Bits of 24-Bit Address)

W
W

Functions

11-43

ISBC® 552A AND iSXMTM 552A Boards

"OPEN SYSTEMS"
ISO MODEL
END USER
APPLICATION
PROCESS

HOST PROCESSOR
6
5

-4.

3
2

INA 961/ISXM™ 552A
SYSTEMS

280385-5

Figure 4. INA 961 Configuration on iSXMTM 552A Board
Table 3. INA 961 Services

Transport

Virtual Circuit
Open: Establish ,a Virtual Circuit Database
Send Connect: Actively Try to Establish a Virtual Connection
Await Connect: Passively Awaits the Arrival of a Connection Request
Send: Send a Message
Receive: Post a Buffer to Receive a Message
Close: Close a Virtual Circuit
Datagram
Send: Send a Datagram Message
Receive: Post a Buffer to Receive a Datagram Message

Data Link

Transmit: Transmit a Data Link Packet
Receive: Post a Buffer to Receive a Data Link Packet
Conn~ct: Make a Data Link Logical Connection (Link
Service Access Point, IEEE802.3/802.2)
Disconnect: I;)isconnect a Data Link Logical Connection
Change Ethernet Address: Change the Ethernet Address
Add Multicast Address: Add aMulticast Address
Delete Multicast Address: Remove a Multicast Address
Configure 82586: Configure the 82586 Controller

Network
Management

Read/Clear/Set Network Objects (Local/Remote):
Read/Clear/Set Local or Remote iNA 960 Network Parameters
Read/Set Network Memory (Local/Remote)
Read/Set Memory of the Local or a Remote Station
Useful in Network Debug Process.
Boot Consumer: Requests a Network Boot Server to
Load a Boot File into this Station
Echo: Echo a Packet between this Station and
Another Remote Station on the Network
11·44

inter

iSBC® 552A AND iSXMTM 552A Boards

iSBC® liSXMTM 552A Boot Firmware
User Interface
The iSBC/iSXM 552A boot firmware is used to load
iNA 961 or other software onto the 552A board from
either local MULTIBUS I memory or a remote network station. The firmware performs a number of local and network diagnostics. Table 4 describes the
functions of the boot firmware.
The iSBC/iSXM 552A boot firmware interfaces with
the host processor through a configurable command
buffer location in MULTIBUS I memory. This location
can be either jumper or program configured. The
host processor updates the command byte in the
command buffer and expects the firmware to update
the response byte when the command is done. The
host processor signals to the firmware to examine
this command buffer by writing a 2 to the flag byte
port. The firmware will update the response byte
when the command is completed.
The iSBC/iSXM 552A boot firmware commands fully
support the initialization of the MIP interface.

The MIP interface is used by the host processor to
communicate with the iNA 961 once it is loaded and
started. See section "iNA 961 User Interfaces" for
details.

iNA 961 User Interfaces
User programs give iNA 960 commands to the iNA
961 software on the iSBC/iSXM 552A board via the
MULTIBUS I Interface Protocol (MIP). MIP is an Intel
reliable message delivery protocol between MULTIBUS I processors. Figure 5 illustrates how this message delivery functions. Commands are passed between the iSBC/iSXM 552A board and the host
processor in the form of request blocks. A request
block is a buffer that contains a command specification and the command parameters. Each request
block (or equivalently, each command) is reliably delivered from the host processor to iNA 961 via the
MIP facility. iNA 961 will extract the command information and carry out the command. After the command is done, iNA 961 will use the MIP facility to
return the command result to the user program.

Table 4. iSXMTM 552A Boot Firmware Commands
Command

Function

Presence

This command will indicate that the boot firmware is
functional by returning the version number of the
firmware, the power on diagnostic result, and the default
Ethernet address of the iSXM 552A board.

Load

Load a program from MULTIBUS memory into a
designated location in the iSBC 552A memory.

Load and Go

Load a program from MULTIBUS bus memory into a
deSignated location in the iSXM 552A memory. Proceed
to start this program once it is loaded. This command
also initializes the MIP interface on the iSXM 552A
board.

Echo

Echo a packet between this iSXM 552A board and
another station on the network.

Remote Boot

This command requests a remote boot server station to
download software onto the iSXM 552A board.

MIP Initialize
and Start

Used after a remote boot. This command initializes the
MIP interface on the iSXM552A board and then start the
software loaded by the remote boot command.

11-45

inter

iSBC® 552A AND iSXMTM 552A Boards

USER
PROGRAM

1+----1

INA
961 MIP
DRIVER

USER
MIP
DRIVER

INA 961
SOFTWARE

. TRANSFER OF
REQUEST BLOCKS
(COMMANDS)

S
Y
S
T
E
M

B
U
S

HOST PROCESSOR

ISXM™ 522A/INA 961
BOARD SOFTWARE

280385-6

Figure 5. INA 961 MIP Interface

iNA 961 request blocks are in the same formats as
iNA 960 commands. Refer to the iNA 960/961 data
sheet and reference manuals for more details on
iNA 960/961 software.

Operating Systems Environment

Diagnostics
The iSBC/iSXM 552A board offers a range of power
up diagnostics designed to ensure that the 80186
processor, the memory, and the IEEE 802.3 interface are functioning properly. Table 5 describes
these diagnostics.

The iSBC/iSXM 552A board and iNA 9601961 software can function in any MULTIBUS I environment.
The communication between the iSBC/iSXM 552A
and the host processor is entirely independent of
any host operating systems. iNA 9601961 uses the
MIP protocol to interface with the. host processor.
The MIP is a reliable, host operating system independent, process to process communication
scheme between any processors on the
MULTIBUS I System Bus. iNA 960/961 can service
multiple processes utilizing its services at the same
time.
A host processor passes iNA 960/961 commands
and buffers in the MULTIBUS I system memory to
the iNA 960/961 software. This software is responsible for updating the response fields of these commands. It is. responsible for copying the user send
buffer in MULTIBUS I system memory into its onboard buffers for transmission and for. copying re-.
ceived messages to user buffers in MULTIBUS I system memory.

1.1-46

Table 5. Functions Checked by
iSXMTM 552A Diagnostics

1. Insufficient RAM
2. RAM March Pattern Test
3. Ram Ripple Data Test
4. Boot Firmware PROM Checksum
5. Address PROM Checksum
6. 80186 Interrupt Controller
7.80186 Timer Controller
8. 82586 Initialization
9. 82586 CRC Check
10. 82586 Broadcast Packet Recognition
11. 82586 External Loopback
12. 82586 Individual Address Recognition
13. 82586 Multicast Address Recognition
14. 82586 Reset
15. 82586 Diagnose Check

inter

iSBC® 552A AND iSXMTM 552A Boards

DEVELOPMENT ENVIRONMENT
The iSXM 552A board is a complete system product
that allows a user to emphasize the development of
high level software, such as a network file server.
The iSXM 552A board and the iNA 961 software to- .
gether form a transport COMMengine that integrates
into any MUlTIBUS I system. iNA 961 is supplied in
a boot loadable file format. This file can be loaded
into the iSXM 552A by a host processor or through a
remote boot server network node. The boot firmware on the iSXM 552A supports both functions. In
order to remote boot the host system, appropriate
host processor firmware and software is required.
The iSBC 552A allows a user to fine tune iNA 960
and to put the software on the board. Both iNA 960
and the iSBC 552A can be flexibly configured to best
meet the users' requirements. An Intel development
system, together with the Intel 121CETM system or
equivalent product can be used if the user desires to
do extensive development work on the iSBC 552A.
Intel also supplies a wide range of host processor
boards and systems (such as the iSBC 286/12 and
system 310) that will function well both with the iSBC
552A or the iSXM 552A board.

MUlTIBUS Interface: The iSBC/iSXM 552A board
conforms to all AC and DC requirements outlined in Intel
MUlTIBUS I Specification.
Order Number 142686-022m
except for the following signals:
SignaIDATO-DAT7
Signal Specification:
III = 180 JIoA IIH = 125 JIoA
DC Power Required: All voltages supplied by the
MUlTIBUS I interface
+ 5.0V ± 5%, 6.2A maximum
+12.0V ±5%, 0.5A maximum

Environmental
Temperature: O°C to + 55°C Operating
-40°C to -65°C Non-Operating
Humidity:
5% to 90% Operating
5% to 95% Non-Operating

ORDERING INFORMATION
Part Number Description
SBC552A
IEEE 802.3 COMMengine

SPECIFICATIONS
Data Transfer: 8 or 16 bits
Average Raw MUlTIBUS I Transfer Rate:
8.7M bits/second (450 ns., 16-bit
system memory and no MUlTIBUS I
contention)

SXM552A

IEEE 802.3 Transport Engine for
iNA961 and SYP31 0 systems

iNA960

Configurable transport software usable with the SBC552A
Preconfigured transport software for
the SXM552A

iNA961

Transceiver Interface
Transmit Data Rate: 10M bits/second
Signal levels:
Host Interrupts:

Series 10,000 ECl-compatible
One MULTIBUS I non-vector
interrupt for use in system/
host handshaking

11-47

intJ

iSBC® 554
MAP COMMUNICATIONS ENGINE

•

Provides IEEE 802.4 Networking
Capability for MULTIBUS® Based
Systems Running Under any Operating
System

•

Serves as a Complete Front End
Communication Engine With the
Capacity to Provide MAP Layers 1
Through 7 Capability for MULTIBUS®
Based Hosts

•
•
•

Runs on Board Intel's Proven iNA 960
Rei 2:0 Providing the ISO 8073
Transport Software and ISO 8473
Network Software as Required by the
Map Specifications
Runs on Board Intel's MAp·NETTM
Software for Layers 5-7 of the Map
Protocol
Preconfigured Software Available for
Seven Layer Map Engine, Four Layer
Transport Engine or IEEE 802.4 to IEEE
802.3 Router

•
••
•
•
•
•
•
•

8 MHz 80186 Processor
256K Bytes of RAM of Which
128K Bytes Provide Dual Port Window
Support
10 Mbps IEEE 802.4/Token Bus Modem
Interface
Sockets for up to 4 JEDEC 28 Pin
Memory Devices, up to Maximum of
160K Bytes EPROM Storage
One iSBXTM Bus Connector for I/O
Expansion Capability
Can Be Configured as Either a Master
or a Slave. in MULTIBUS
On Board Diagnostic and Boot
Firmware
Available in Three Different Modem
Frequencies/Channel Pairs

The iSBC 554 COMMengine product is designed to fit into front end LAN Communication processor applications. It allows the connection of MULTIBUS I based systems onto a MAPIIEEE802.4 (Token Bus) LAN.
COMMengines are dedicated communication processor boards. They allow the host processor board to offload LAN communication related tasks onto the front end COMMengine. Therefore the host has more processing capability for user applications or other tasks. COMMengines also allow the networking of existing
systems without forcing a redesign of the entire system architecture.
The iSBC 554 board canbe used as a front end COMMengine for a MULTI BUS-based host running any
operating system. This is because the on board software provides a high level interface to the host (e.g.,
application or transport level commands). This results in a powerful system building block which enables an
OEM to connect MULTIBUS-based systems onto IEEE 802.4 10 Mbps. LANs. Applications for the iSBC 554
include networked iRMXTM-based systems for real time applications and networked XENIX' systems for
laboratory and data base application. The iSBC 554 is preconfigured to run iNA 961 R2.0 transport and
network software. iNA 961 R2.0 is a preconfigured version for the iSBC 554 of Intel's iNA 960 LAN software
which implements the ISO 8073 Class 4 transport protocol and the ISO 8473 network layer protocol.
The iSBC 554 COMMengine supports multiple datalinks via the iSBX connector located on the iSBC 554
baseboard. The user has the option to interface any of Intels iSBX communication interfaces to support a two
way router. For example iNA 960 supports the MAP/TOP router using the iSBX 586 interface. The preconfigured router software is supplied in iNA 961.
The iSBC 554 is also capable of running on a board MAP2.1 SXMSW preconfigured implementation of the
MAP software for layers 3 through 7 of the ISO/OSI model. This is an ideal turnkey solution for OEMs requiring
a 7 layer MAP COMMengine. MAP-NETTM provides layers 5 through 7 of the MAP specifications and can be
configured with iNA 960 R2.0 to run on the iSBC 554, providing a complete on-board seven layer COM Mengine.

'XENIX is a trademark of Microsoft Corporation.

11-48

September 1988
Order Number: 231594-002

iSBC® 554 COMMUNICATIONS ENGINE

services. Figure 1 shows the configuration of.
MAP-NET and iNA 960 R2.0. Table 1 shows some
examples of functions provided by MAP-NET and
iNA 960 R2.0. iNA 961 R2.0 is a preconfigured version of iNA 960 for the iSBC 554. Refer to the
iNA 960 R2.0 data sheet for more information. .

iSBC® 554 FUNCTIONAL
DESCRIPTION
The iSBC 554 board is a preconfigured MAP Communication Engine with boot firmware and 256K
bytes of RAM. The iSBC 554 board is offered for use
with Intel's MAP-NETtiNA 960 based MAP software.
The iSBC 554 firmware provides the capabilities to
load Intel's MAP software on the iSBC 554 from either a buffer in the local host or remotely from another Token Bus station. It also performs a variety of
on-board diagnostics.

MAP-NET is Intel's implementation of the MAP software for layers 5 through 7. Refer to the MAP-NET
data sheet for more information. This implementation of layers 5 through 7 will run on the iSBC 554
along with iNA 960 R2.0. The iSBC 554 coupled with
the software packages provides a high performance,
7-layer' communication engine (see Figure 1).
MAP 2.1 SXMSW is also available as a preconfigured
software package providing layers 3 through 7 of the
MAP software. This package and the iSBC 554 provides a 7 layer turnkey MAP solution.

The MAP-NET with iNA 960 R2.0 software and the
iSBC 554 board together provide the functionality of
a preconfigured
independent 7 layer engine. In
addition to transport services, iNA 960 R2.0 software also includes ISO 8473 Internet network layer,
extensive data link and network management facility

"OPEN SYSTEMS"
ISO MODEL

INA 960 R2.0

2
ISBCQ!) 554 ENGINE

~--+f/~~~~ ___ ~
All software runs on board

Figure 1. MAP~NETTM and iNA 960 Configuration on ISBC® 554 Board

11-49

231594-1

inter

iSBC® 554 COMMUNICATIONS ENGINE

Table 1. MAP-NETTM and iNA 960 R2.0 Services
Application

File Transfer, Access and Management (FTAM)
Provides remote operations on files (Create, Read, Write, Delete,
Get File Attributes)
Common Application Service Elements (CASE)
Supports all the services provided by the lower ISO layers
Provides name to address translation support
Directory Services
Performs name to address conversion
Maintains local cache of resolved names
Two forms of directory service-client service agent for local data
base and directory-service agent for remote (master) data base

Session

Implements subset of ISO Session 8327 specified by the MAP 2.1
Specifications
Provides "Graceful Close"
"Graceful Close" allows the closing of a connection without any
loss of queued requests
It enhances the transport provided "close" which aborts a
connection

Transport

Virtual circuit
open: establish a virtual circuit data base
send connect: actively try to establish a virtual connection
await connect: passively awaits the arrival of a connection request
send: send a message
receive: post a buffer to receive a message
close: close a virtual circuit
Datagram
send: send a datagram message
receive: post a buffer to receive a datagram message

Network

Internetworking
routing between multiple lans
segmentation/reassembly·
user defined routing tables
Multiple sub nets supported
user supplied
802.3, 802.4

Data Link

Transmit: transmit a data link packet
Receive: post a buffer to receive a data link packet
Connect: make a data link logical connection (link
.service access point. IEEE802.4)
Disconnect: disconnect a data link logical connection
Change token buS address
Add multicast address
Delete multicast address
Configure TBH

11-50

inter

iSBC® 554 COMMUNICATIONS ENGINE

Table 1. MAP-NETTM and INA 960 R2.0 Services (Continued)
Network
Management

Read/Clear/Set network objects (local/remote):
read/clear/set local or remote MAPNET /iNA 960 network parameters
Read/Set network memory (local/remote):
read/set memory of the local or a remote station
Useful in network debug process
Boot consumer: requests a network boot server to
load a boot file into this station
Echo: Echo a packet between this station and
another remote station on the network
Options on the iSBC 554 board allow up to 128K
Byte of RAM to be accessible by the host. This dual
port RAM is jumper selectable to appear anywhere
in the MULTIBUS 16M Byte memory space on 128K
Byte boundaries. The dual port RAM memory is a
data link between the on board 80186, the token bus
controller, and the bus master (if any) managing the
systems functions. This shared dual port RAM can
be used to transfer command, status and data between the on board 80186 processor and the host.
This feature minimizes the necessity for the 80186
to access MULTIBUS while acquiring shared information. This has a direct positive effect on performance, serving to eliminate bus contention.

ARCHITECTURE DESCRIPTION
The iSBC 554 board consists of the following major
architectural blocks (see Figure 2): an 80186 processor running at 8 MHz, the Token Bus channel
based on the Token Bus Handler chip set and the
Token Bus Modem, the on-board memory consisting
of ROM and RAM, the iSBX interface, and the
MULTIBUS interface.
PROCESSOR
The iSBC 554 board contains an 80186 processor
operating at 8 MHz. It is responsible for implementing the intelligent interface between the iSBC 554
board and a host processor. The 80186 processor
runs the MAP-NET/iNA 960 R2.0 transport software
and the data link software needed by the Token Bus
Handler chip set. It is responsible for the delivery of
data between user buffers in MULTIBUS memory
and iNA buffers on the iSBC 554 board. The iNA
software is responsible for the reliable transfer of
information across the Token Bus LAN.
MEMORY
The one megabyte address space of the 80186 is
divided into four quadrants (see Figure 3). The first
quadrant (0-256K Byte) is local RAM memory. The
second quadrant is memory mapped Token Bus
Handler address. The third quadrant (512-768K
Byte) maps into two MULTIBUS windows (128K
Byte each). These windows allow the iSBC 554
board to access the total 16M Byte of MULTIBUS
memory in 128K Byte segments. The fourth quadrant (768-1 M Byte) is local ROM which contains the
80186 firmware, the Token Bus station address, and
relocated 80186 internal registers.
The two 128K Byte MULTIBUS windows each start
on 64K Byte boundaries anywhere in the 16M Byte
MULTIBUS memory. The starting location of either
window is determined by writing to a local I/O
. mapped latch.

TOKEN BUS INTERFACE
The Token Bus interface on the iSBC 554 is implemented by the Token Bus Handler (TBH) chip set
and the Token Bus Modem (TBM). Data is transferred between the on-board memory and the TBH
by the TBH initiated DMA. The TBH will then pass
data, operating according to the IEEE 802.4 Token
Bus Specification, to the TBM which handles the
physical interface to the Token Bus.
Each iSBC 554 board is manufactured with a unique
default Token Bus network address stored in an address PROM. This address PROM is protected by
checksum and can be read by utilizing the on board
I/O.
MULTIBUS® INTERFACE
The iSBC 554 board can access the MULTIBUS with
an 8- or 16-bit data path and can support up to 24
address bits. The internal 80186 registers are relocated into the local memory map to avoid conflicts
with MULTIBUS I/O during 80186 internal register
accesses, The iSBC 554 board is capable of accessing the MULTIBUS I/O from 384-64K (180HFFFFH) Byte of I/O space locations.

11-51

A host processor in a system communicates with the
iSBC 554 board via a flag byte port in the MULTIBUS interface. The flag byte port is presented as a

inter

iSBC® 554 COMMUNICATIONS ENGINE

ISBX™
INTERFACE

80186

INTERNAL BUS

TOKEN
BUS
MODEM

TOKEN BUS
HANDLER

TOKEN BUS
CONNECTION

MULTIBUSII!)SYSTEM BUS

231594-2

Figure 2. iSBC® 554 Architectural Blocks

MULTIBUS-

XMIT

SERIAL DATA OUT

ON·BOARD LOCAL BUS

MEMORY

SYSTEM
CONTROL
B;OCK

COMMAND
BLOCK
LIST

,
RECEIVE
FRAME AREA

280269-4

Figure 3. System Overview
11-65

intJ

iSBC® 186/530 MULTIBUS® II

INITIALIZATION

ROOT

COMMAND BLOCK LIST (CBL)

r----~------------------------,
825111 CONTROL
COMMANDS

...

STATUS

ci --

I
I
.1
I
I
IL _____________________________ I

POINTERS

ERROR TALLIES
-CRC
-ALIGNMENT
-NO RESOURCE
-DMA OVERRUN

RECEIVE FRAME AREA (RFAI

'I--- -----------

I
I
I

DESCRIPT~
~

RECEIVE
LlST(RDL)

I
I

!L _____________
~U-"~71
I

I
~

280269-5

Figure 4. 82586 Memo,ry Structures

Memory Subsystem
The iSBC 186/530 board's on-board memory subsystem consists of a large DRAM array and a set
of ROM/EPROM memory sites. Access to the
on-board memory subsystem resources, as well as
off-board iPSB bus access, is accomplished by observing the iSBC 186/530 board memory map (See
Figure 5). The mapping occurs within the 1 megabyte memory space of the 80186 microprocessor,
and is split into three main areas: DRAM reserved,
iPSB window, and EPROM reserved. The first 0 to
512K bytes is always reserved for local DRAM, the
next 128K or 256K bytes (or up to 768K) is the iPSB
window, and the remaining 384K or 256K byte area
is reserved for 'local EPROM. The iPSB window,
maps a 128K or 256K byte memory area into the 4
gigabyte global physical address range of the
MULTIBUS II iPSB bus. This window is programmable and allows the ,80186 processor to access the
complete 4 gigabyte memory space of the iPSB bus.
The board's memory map also supports a 64K byte
access window for 110 space between local and

iPSB bus access. The 64K bytes of local 110 space
is mapped 1-to-1 to the iPSB bus' 64K byte 110
space. The upper 32K bytes access the iPSB bus
110 space, and the lower 32K bytes are reserved for
local on-board 110.
DRAM CAPABILITIES
The iSBC 186/530 board comes standard with a
256K byte DRAM memory array on-board. Eight additional 18~pin sockets are provided to the OEM for,
expanding the DRAM array to 512K bytes.
EPROM MEMORY
A total of four 28-pinJEDC universal sites reside on
the iSBC 186/530 board. These sockets support additon of byte-wide ROM and EPROM devices in densites from 8K bytes (2764) to 64K bytes (27512) per
device. Two of the four sockets contain a pair of
27128 EPROM devices installed at the factory.,
These devices contain 32K bytes of firmware provi-

11-66

ISBC® 186/530 MULTIBUS® II

IPSB
MEMORY MAP
D4GBYTES
~

MBII
MEMORY

ISBC 188/530
MEMORY MAP
1024K
ONBOARO
EPROM
7e8K

:..

W~~~~W-

--"i---~

MBII
WINDOW
BASE ADDRESS IS ANY MULTIPLE OF 128K
........ ~=~+-OR 256K (SIZE OF MULTIPLE WINDOW SIZE)

512K

ON·
BOARO
DRAM

1-.._--,0

280269-6

Figure 5.ISBC® 186/530 Board Memory Map Diagram
ded to execute the Built-In-Self-Test (BIST) powerup diagnostics routine, EPROM devices installed at
the factory. These devices contain 32K bytes of firmware provided to execute the Built-In-Self-Test
(BIST) power-up diagnostics routine. The remaining
two sockets allow the user to add either two
ROM/EPROM devices or an iSBC 341 256K byte
EPROM MULTIMODULETM board for a maximum of
512K bytes of ROM/EPROM on-board.

General 110 Subsystem

PROGRAMMABLE TIMERS AND INTERRUPT
.
CONTROL
The board's 80186 microprocessor provides three
independent, fully programmable 16-bit interval timers/event counters and an interrupt controller.
The 80186 interrupt controller is configure~ in the
"fully nested mode," and supports five external interrupt sources via five dedicated pins provided on
the 80186. All five pins are used as interrupt requests from other hardware on-board (See Table 3).

.The I/O subsystem provides timers, interrupt control
and an RS232C serial port for debug and test.
Table 3. External Interrupt Sources
Interrupt

Vector Type

Vector Location

NMI
INTO
INT1
INT2
INT3

2
12
13
14
15

00008 H
00030 H
00034 H
00048 H
0004C H

Default
Priority
1
6
7
8

11-67

Function
Reset stake pin
Interrupt from the Ethernet Controller
Message Interrupt from the MPC (MINT)
Error Interrupt from the MPC (EINT)
Interrupt from the 8031 Interconnect
Controller

inter

iSBC® 186/530 MULTIBUS® II

RS232C SERIAL PORT

nect access to the iPSB bus by the 80186 and
82586 processors.

There is a simple RS232C serial port provided on
the iSBC 186/530 board for use in debug and test.
The serial interface is derived from the 8031 serial
interface port. Only the Receive Data (RD) and
Transmit Data (TO) lines are supported, connected
to a 25-pin connector on the front panel. The pin
assignments for the 25-pin connector are shown in
Table 4.

The single-chip Message Passing Coprocessor is a
highly integrated CMOS device implementing the full
message passing protocol and performing all the arbitration, transfer, and exception cycle protocols
specified in the MULTIBUS II Architecture Specifica~
tion Handbook, Rev. C., Order Number 146077.

Table 4. Serial Interface Connector,
Pin Assignments
Pin

RS232CFunction

1
2
3
4
5
6
7
8
9
10
11
12
13

Shield
Transmit Data (TXD)
Receive Data (R x D)
Not Used
Not Used
Not Used
Signal Ground (OV)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used

Interconnect Subsystem
MULTIBUS II interconnect space is a standardized
set of read-only and software configurable registers
designed to hold and control board configuration information, and communicate system and board level
diagnostics and testing information. Interconnect
space is implemented with an 8031 microcontroller
and the MPC silicon resident on the iSBC 186/530
board.

Pin RS232C Function
14
15
16
17
18
19
20
21
22
23
24
25

Not used
Not used
Not used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used

The read-only registers store information such as,
board type, vendor 1.0., firmware rev. level, etc. The
softwareconfigurable registers are used for autosoftware configurability and remote/local diagnostics and testing .. For example, a software monitor
can be used to dynamically change bus memory
sizes, enable on-board resources such as memory,
read if the PROM devices are installed, or access
results of Built-In-Self-Tests and other diagnostics.

iPSB Bus Interface Subsystem
This subsystem's main component is the MPC Message Passing Coprocessor chip. Subsystem services provided by the MPC bus interface component
includes full message, memory, I/O, and intercon~

Most options on the iSBC 186/530 board are controlled by. interconnect space. In addition, many of
the interconnect registers on the board perform
functions traditionally done by jumper stakes. Other
interconnect registers provide. status information allowing system software to determine configuration
status.

ISBC 186/530

LAN
CONTROLLER

ROM BASED
DOWNLOAD
ROUTINE

IPSB BUS

Figure 6. Download Routine
11-68

280269-7

inter

iSBC® 186/530 MULTIBUS® "

Firmware Capability
HOST/CONTROLLER SOFTWARE DOWNLOAD
ROUTINE
.
Resident in ROM on this controller is a host-to-controller software download routine to support the
downloading of communication firmware into the
iSBC 186/530 board. This loader adheres to the
MULTlBUS II Download Protocol and responds to
commands issued by software running on a host
CPU board. The host CPU passes these commands
to the loader via registers defined in the board's interconnect space. A download function, a commence execution function, and an examine local
memory function are all provided in the routine. Data
transfers are supported by both shared memory systems and message based systems. The top 1K of
DRAM on the board is reserved for the exclusive use
of the download program. Host CPUs must not overwrite this area with download commands.
Software on the host is responsible for accessing
the iSBC 186/530 board's firmware on disk or from
ROM visible to the host and translating it into linear
sequences of bytes suitable for downloading (See
Figure 6). After downloading the firmware, the host
issues a command for the loader routine on the controller to begin execution of the download software.

The BIST package provides a valuable testing, error
reporting and recovery capability of MULTIBUS II
boards enabling OEMs to reduce overall system
manufacturing and maintenance costs. An LED on
the board's front panel indicates the status of power-up diagnostics. It is on when BIST diagnostics
start running and is turned off upon successful completion of the BISTs.

SPECIFICATIONS
Word Size
Instructlon-8-, 16-, 24-, or 32-bits
Data-B-, or 16-bits

System Clock
CPU-B.O MHz

Cycle Time
Basic Instructlon-B.O MHz-375 ns; 250 ns (assumes instruction in queue)
NOTE:
Basic instruction cycle .is defined as the fastest instruction time (i.e., two clock cycles).

Built-In-.$elf-Test Diagnostics
On-board initialization checks and built-in-self-test
(BIST) diagnostics are implemented using the 8031
microcontroller and the 80186 microprocessor. Onboard tests included in the BIST package are:
DRAM, EPROM, 80186, 82586, 8031, and MPC.
These tests are performed by the 80186 microprocessor.
Additional activities performed include a Reset Operating System initialization at power-up and a program table check, a feature allowing users to add
custom code in EPROM while still maintaining full
use of the facory supplied BISTs. Immediately after
power-up and the 8031 microprocessor is initialized,
the 80186 microprocessor begins its own initialization and on-board diagnostics. Upon successful
completion of these activities, the Reset Operation
System invokes the user-defined program table. A
check is made of the program table and the custom
programs that the user has defined for his application will then execute sequentially.

Memory Capacity
Local Memory
DRAM-256K bytes on-board (64K x 4-bit devices).
8 sockets provided to support additional 256K bytes
EPROM-Number of sockets-four 28-pin JEDEC
sites
EPROM

Device Size
(Bytes)

Maximum
Memory Capacity

2764
27128
27256
27512

8K
16K
32K
64K

32K bytes
64K bytes
128K bytes
256K bytes

"EPROM expansion to up to a maximum 01 512K bytes IS achieved
via attachment 01 the iSBC 341 EPROM (256K byte) MULTIMODULE
board.

11-69

inter

iSBC® 186/530 MULTIBUS® II

I/O Capability

Electrical Characteristics

ETHERNET (IEEE 802.3)- One ETHERNET channel. Uses 15-pin connector, 82586 LAN Coprocessor and an Ethernet Serial Interface component

The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices or expansion
modules.

RS232C-only Serial Port- Simple serial port,
RS232C, driven off 8031 microcontroller. serial port
interface; used for debug and test
Timers- Three programmable timers on the 80186
microprocessor

Voltage
(volts)

Max. Current
(amps)

Max. Power
(watts)

+5V
+12V
-12V

6.5A
50mA
50mA

34.13W
0.06W
O.06W

Input Frequencies- Frequencies supplied by the
internal 80186 16 MHz crystal

Reference Manuals
Interrupt Capability
Potential Interrupt Sources from iPSB Bus- 255
individual and 1 Broadcast
Interrupt Levels - 5 interrupt sources using 80186
Interrupt Controller
Interrupt Requests -

All levels TTL compatible

iSBC 186/530 ETHERNET (IEEE 802.3) Communications Engine ,User's Guide 149226-001
Intel MULTIBUS II Architecture Specification Handbook 146007
Reference manuals may be ordered from any Intel
Sales Representative, Distribution Office, or from
the Intel Literature Department, .3065 Bowers Avenue, Santa Clara, CA 95051.

Eurocard Form Factor
Depth Height -

220mm (8.7 inches)

ORDERING INFORMATION

233mm (9.2 inches)

Part Number
iSBC 186/530

Front Panel Width Weight -

20mm (0.784 inches)

743 g (26 ounces)

Environmental Characteristics
Temperature:
(non-operating)
(operating)
Humidity
(non-operating)
(operating)

Inlet air at 200 LFM airflow
over all boards
-40°C to + 70°C
Oco to +55°C
95% Relative Humidity @
+ 55°C, non-condensing
95% Relative Humidity @
+ 55°C, non-condensing

11-70

Description
MULTIBUS II ETHERNET (IEEE
802.3) Communication Engine

intel'

Network Services

XENIX*-NET NE1WORKING
OpenNETTM

PRODUCT FAMILY
~
~
~

Complete IAN Solution based entirely
on standards
Multiple operating system interoperation:
XENIX, MS"-DOS, iRM)(TM, iNDX
.
Existing applications distributed
without change
Comprehensive net~rk sero;ces:
- Ne~rk File Access
- Remote Job Execution
- Network XENIX Mail
- Network Administration
- Virtual Terminal
- MS-DOS Virtual Terminal
- Print spooling

• XENIX:NET COMPLETE NElWORK SERVICES

• 1UfAL IAN SOLUflON FOR
MICROSYSTEM APPUCATIONS

In addition to transparent network file access, XENIXNET makes available critical services to all nodes in a
LAN providing for increased group productivity and
system utilization.
Remote Job Execution. With Remote Job Execution, a user can execute a XENIX command stream at
single or multiple remote nodes. Additionally, these
command streams can be queued for execution at
specific times throughout the day. This facility allows
users to distribute and balance the workload logically
throughout a network, completely utilizing the combined power of the network resources.
Network XENIX Mail. The XENIX Mail facility has
been extended· to transparently reach beyond a single
XENIX system to remote nodes within a LAN. XENIX
Mail users don't have to concern themselves with
where a particular user resides on the network. Network XENIX Mail service provides the necessary routing and delivery throughout the network and through a
UUCP link.
Virtual Terminal. Packaged as a separate network
service, Virtual Terminal allows local XENIX users to
"logon" to a remote Intel XENIX node within the
network. This capability allows users to access all available resources and functions such as host communications and peripherals.

OpenNET is Intel's Open System strategy and product
family for local area networks (LANs). XENIX·NET
represents the first truly integrated department service
network to provide all the necessary hardware and
software to link Intel microsystems, terminals, PCs,
mainframes, minis, peripherals and software in one
consistent, integrated system.

• XENIX-NET NElWORK FILE ACCESS
IUR TRANSPARENT INTEROPERATION
XENIX-NET provides transparent network file access
(NFA) and additional network services to interoperate
among various nodes on the LAN. XENIX-NET NFA run~
under the XENIX 3.0 operating system from Intel. There
are no special operating system calls to access remote
files.·
.
Applications and users make standard XENIX file access
requests such as OPEN, CLOSE, READ and WRITE.
XENIX-NET NFA transparently accesses files across the
network. XENIX-NET NFA determines from the filename if the file is on a local storage device or remote
across the network. Application~ access remote files a~ if
they were local; no modification~ to application~ software are required to run across the network.
XENIX-NET NFA makes networked microsystems look
like one large integrated computer system with a single
network-wide hierarchical file system.
'!lINTEL CORPDRATIDN.1987
·XENIX AND MS,ARE REGISTERED TRADEMARKS OF MICROSOFT CORPORATION

JANUARY. 1987
ORDER NUMBER 2700SS..()()4

11-71

• COMPLETE NE1WORK SUPPORT AND
SERVICE FROM A SINGLE SOURCE

DOS-NET Virtual Tenninal. Packaged as a separate network service, DOS-NET Virtual Terminal is an
MS-DOS service which allows IBM pes and compatibles connected through the OpenNET LAN to "logon"
to any remote Intel XENiX system and access the
multiuser applications and services (such as mail)
available in that environment.
Easy Network Administration. XENIX-NET provides a complete set of interactive network configuration and maintenance utilities. With the addition of
iBASE, Intel's menu driven business shell, network
administration is further simplified by giving the network administrator a "window" to all nodes residing
on a sub-network. A series of screens and menus
prompts the administrator through network configuration and maintenance.
Print Spooling. XENIX-NET Print Spooling provides shared access to single or multiple printers distributed throughout a network. Expensive laser and
letter-quality printers, for example, can be shared
among numerous users from one site and need not be
duplicated at each node in the network.

Intel takes ownership of the complete network system
by offering a broad range of service and support packages.
Network consulting, planning, design and analysis is
aVailable for customers to ensure proper, cost-effective
network selection and configuration.
Network installation and check-out serVice consolidates the complex coordination of a network installation to one vendor. Intel reduces the time to network
availability by ensuring the proper functioning of all
nodes on the network, including the cabling.
Intel extended hardware/software service and support
agreements are designed to support both Intel and
non-Intel components of a network - making Intel
the single point of contact for problems or questions
relating to the network.
Finally, Intel offers complete training on XENIX-NET
software, as well as for the entire OpenNET product
line to make network users as productive as possible .

• OpenNET LAN STANDARDS
Intel supports and drives LAN standards and technol- .
ogy for the microsystems and microcommunications
industries. The OpenNET product family adheres to
the International Standards Organization's (ISO)
seven layer Open Systems Interconnect (OSI) model.
Only complete products that conform to this model
and are based on open and public standards carry the
OpenNET name.

• Open NET XENIX-NET LAN SOLUTION

THE TOfAL

No other hardware and software LAN combination
integrates such a breadth of services or offers a faster or
more economical path to getting networked application systems that transform personal productivity into
organizational efficiency.

ORDERING INFORMATION
Complete Network-Ready Systems
Complete XENIX-NET ready systems are available from Intel. SYS3 10- I 41 comes complete with an integrated LAN controller.SYS310145 comes with an integrated IAN controller as well as an integrated mainframe Host Communication Controller for ASYNC and BYSNC
communication protocols_
Any Series 300 microsystcm from Intel may be upgraded to a network-ready system by adding an XNXNFAEKRIKIT option, or at initial
order appending "XN" option designator for System 300 hardware configuration orders .
. XENIX Networking Software and Kits
XNXNFAEKRl
XENIX Networking and iNA 961 Object Software plus rights for 8 copies
XNXNFAEKRlKIT
XENIX Networking and iNA 961 Object Software plus an iSXM 552S Ethernet controller for pass-through product
DOSNE1VTSKRI
PC terminal emulator that enables a PC user to "login" directly to a XENIX system running XENIX virtual terminal
XNXNE1VTSKRI
Provides XENIX-to-XENIX virtual terminal capabilities

IAN Hardware
iSXM552
iMDX457
iMDX3015
iMDX3016-1
iDCM91 1-1
PCUNK

Ethernet COMMengine plus one iNA 961 Software Incorporation Fee
Ethernet Transceiver Cable
Ethernet Transceiver
Ethernet Cable
Intellink
Includes the Network Interface Unit (NJU) add-in IEEE 802_3 "Ethernet" controller for IBM PC and compatibles,
preconfigured iNA 961 ISO transport software for NJU and MS NET network file access software for PC DOS/MSDOS PC or compatible.

11-72

O~DNETTH,

MS-NET Access for the IBMTM PC

Now users of IBMT. PC AT, PC XT and other compatible computers can access Intel's OpenNET'""
networking system, using Microsoft's MS·NET, through the OpenNET Personal Computer Link2 (PC
Link2). An 80186/82586 microprocessor·based expansion board, PC Link2 is easily installed in a PC
expansion card slot and uses only 44 K of PC memory. The software package incorporates the MS·
NET and iNA 960 (ISO 8073 compatible) transport software. '
O~DNETTHPERSONALCOMPVTERLIN«2FEATVRES

• Runs on IBM PC AT. PC XT, and PC· DOS
compatibles
• Uses standard DOS commands
• Interconnects to iRMX 554

BOARD

•

MIP

DIRECTO':j
SERVICES

I-

zw
:IE

CASE

FTAM ~II
CONSUMER

PRESENTATION
(NVLL)
SESSION

:IE
I-

FTAM
SERVER

MAPNET2_1

TRANSPORT

MAP2.1SXMSW

NETWORK

DATA LINK
PHYSICAL

Figure 2: MAP-NET 2.1 liseI' Interface

11-79

THREE WAYS TO GET STARTED

WITH MAP
INT«;L offers three methods for getting started with MAP;
complete hroadhand MAP. ~IAP on EtherNET. and MAP
broadband/EtherNET compatibility.

MAP Development Stal'tel' Kit. Intel's ~IAP
Starter Kit allows you to begin learning and developing
MAP broadband applications. This kit provides a low-cost,
turnkey MAP development network with on-sitl' installation
and extended (12 months) software support to assist you
during the application development cycle. The two node
Starter Kit has been engineered to allow you to easily .
expand the network to eight nodes. Each node provides a
complete seven-layer MAP solution, including network
management, FTAM, Directory Services, CASE and
application-level interfaces for all functions. The MAP
Development Starter Kit documentation includes
programming examples, a user's manual for layers five
through seven, and a programmer'sreference manual for
layers three and four,

MAP appllmUon development on IEEE
80Z.:I. "MAP on EtherNET" is intended for those users
wanting to dEYAX II. DECnet ... _

01. Digital equIpment COrp.

@INTEL CORPORIITION 1988

OllDER NUMBER 280321HlO1

11-88

Power-up, self-test diagnostics are resident on both the
Unibus and Qbus controller. Extended host resident
diagnostics are also provided which can be loaded onto the
boards to aid in problem resolution. In addition, appropriate
internal cables, and chassis mounting hardware are included.

Physical Description
The VAXNMS Networking Software package consists of
the appropriate network controller board and the software
necessary for the (Micro)VAX to communicate over the
OpenNET network. The following sections describe the
hardware and software components of VMS NET.

VMSNET Software

VMSNET Hardware
VMSNET comes with one of two types of Ethernet
controller boards: a Unibus* board for the high-end VAX or
a Qbus board for the MicroVAXII system.' Both boards
implement the industry standard ISO 8073 transport protocol
and Ethernet/IEEE 802.3 physical data link technology.
Both boards are high performance, intelligent communications controllers featoring onboard, deqicated Intel
80186/82586 processors which support layers I through 4 of
the ISO OSI Reference Model. Thus, the Unibus and Qbus*
boards perform the CPU tasks associated with lower layer
LAN communications protocols, thereby freeing the
(Micro)VAX host CPU to concentrate on applications
requirements.
.

NETWORK FILE

!-'

L--=...:AC::;C::.:E==S=S..J.:(N~F...:..:A:L..)- - - I

I
_

- A specially configured version of iNA 960 transport layer
softww;e which operates on the network controller boards

- A VMS interface driver which enables VMS

L.E_T. . :H;.;.E.,=R;.;:N;.;.;ET. . ;. ; ;1IE. .;.:E-'"E~80"-2_.3-'_.

programs to

access the network controller board
- An implementation of the Network File Access (NFAj
protocols Gointly developed by Intel, mM, and Microsoft)
which enables (Micro)VAX users to interoperate with
.
other nodes on the OpenNET network

APPLICATION

(7)

PRESENTATION

(6)

SESSION

(5)

TRANSPORT

(4)

NETWORK

(3)

DATA LINK

(2)

PHYSICAL

(1)

_~~iN~A~96=O~---II
(ISO 8073)
.___ {

SPECIFICATIONS

The software is supplied on either a 9 track magnetic tape
(for high-end VAXs) or on both a TKSO cartridge tape and
RXSO 5 'A-inch disk (for MicroVAXlIs). The following software components are included as part of the VAXNMS
networking software:

ISo-OSI VAXNMS OpenNET Implementation

OpenNET, iRMX are trademarks of Intel Corporation .
• Unibus and abus are trademarks of Digital Equipment Corporallon.

11-89

VMSNET NETWORKING
SOFTWARE

Functional De-'-=-sc:.::n-"'·p"'t::cio_n_ _ _ _ _ _ _ _ _ _~----

Physical Characteristics

Transparent File Access

Software

VMSNET provides transparent remote file access capability
to the (Micro)VAX through a file server module. The server
receives,interprets and executes the command acting as a
user to its local file system. Consequently, a PC, iRMX, or
XENIX user can work with data files and resources
residing at the VAX as if they were resident on his/her
system.

1. 9 track 1600 bpi magnetic tape
or
2. TKSO cartridge tape and RXSO 514-inch disk

File Transfer
VMSNET also provides a set of file transfer utilities that
allow (Micro)VAX users with the ability to transfer files
that reside on other OpenNET server nodes to the
(Micro)VAX or vice-versa. These utilities include copying
files, deleting files, listing directories, and a belp facility.

DECnet Access
VMSNET will allow consumer access to a file residing on
DECnet nodes. The only protocol restriction is that the
server will not allow file locking or compatibility mode
opens on DECnet file access. The consumer may use
logical names to define DECnet pathnames. For example, if
"dev" is defined in login.com with an equivalence string of
"isodev" user mypasswork"::dra I[user]", the consumer can
use "dev" as the first patbname component; the server will
automatically use DECnet for the· file access:

Unibus controller: +5vdc (±5 %) at 4.5 amps typical,
6 amps maximum
-15 vdc (±10%) at .5 amps, 3 amp
surge
Qbus controller:

Network Management
A set of network management utilities provide (Micro)VAX
users with information and statistics of VMS NET along
with the capability to control the execution of the VMSNET
server and file transfer utility. Th invoke the network utility,
tbe user simply needs to type "NET" in response to the
DCL (Digital Command Language) prompt.

Host Requirements
VAX 750, 780, 782, 785
VAX 8xxx family
MicroVAXII
(Micro)VMS operating system, version 4.2 or later

11-90

+5 vdc (±5%) at·6 amps typical
+12 vdc (±10%) at .5 amps, 3 amp
surge

Environmental Characteristics
Operating Temperature: 0° to 50°C (32 ° to 122 OP)
Operating Humidity:

Maximum of 90% relative humidity,
non-condensing
Forced air cooling

Ordering Information
VMSNET

- net use vms IIvms/user mypasswork
- Ic IIvms/dev
- cp IIvms/dev/test.obj/usr/bin

Power Requirements

VAX/VMS Networking Software for installation on a high end VAX: consists of a Unibus
network controller board with 256KB RAM, a
5 ft. and 10 ft. flat transceiver cables, software
on a 9 track 1600 bpi magnetic tape, and an
installation and user's guide.

MVMSNET VAXIVMS Networking Software for installation on a MicroVAXII: consists of a Qbus network controller board with 256KB RAM, an
18 inch flat transceiver cable, software on botb
TKSO cartridge tape and RXSO 5 14 inch disk,
and an installation and user's guide.

Serial Communication
Boards and Software

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inter
•
•
•
•

iSBC® 88/45
ADVANCED DATA COMMUNICATIONS
PROCESSOR BOARD
(SOSS-2) Microprocessor Operates
• SOSS
at S MHz
iSBC® 337 Numeric Data Processor
• Option
Supported
16K Bytes Static RAM (12K Bytes Dual• Ported)
2S-Pin JEDEC Sites for EPROM/
• Four
RAM Expansion; Four Additional 2S-Pin

Three HDLC/SDLC Half/Full-Duplex
Communication Channels-Optional
ASVNC/SVNC on Two Channels
Supports RS232C (Including Modem
Support), CCITT V.24, or RS422A1449
Interfaces
On-Board DMA Supports SOOK Baud
Operation
Self-Clocking NRZI SDLC Loop Data
Link Interface
- Polnt-to-Point
-Multidrop

JEDEC Sites Added with iSBC® 341
Board
Two iSBXTM Bus Connectors

• MULTIBUS® Interface Supports
• Multimaster Configuration

Software Programmable Baud Rate
• Generation

The iSBC 88/45 Advanced Data Communications Processor (ADCP) Board adds 8 MHz, 8088 (8088-2) 8-bit
microprocessor-based communications flexibility to the Intel line of OEM microcomputer systems. The
iSBC 88/45 ADCP board offers asynchronous, synchronous, SDLC, and HDLC serial interfaces for gateway
networking or general purpose solutions. The iSBC 88/45 ADCP board provides the CPU, system clock,
EPROM/RAM, serial I/O ports, priority interrupt logic, and programmable timers to facilitate higher-level application solutions.

210372-1

12-1

September 1987
Order Number: 210372-002

inter

iSBC® 88/45 BOARD

plemented by the user include SNA terminal interfaces to IBM systems.

FUNCTIONAL DESCRIPTION
Three Communication Channels

On-Board DMA

Three programmable HOLC/SOLC serial interfaces
are provided on the iSBC 88/45 AOCP board. The
SOLC interface is familiar to IBM system and terminal equipment users. The HOLC interface is known
by users of CCITT's X.25 packet switching interface.

For high-speed. communications, one MPSC channel has a OMA capacity to support an 800K baud
rate. The second channel attached to the MPSC is
capable of simultaneous 800K baud operation When
configured with OMA capability, but is connected to
an RS232C interface which is defined as 20K baud
maximum. Figure 2 shows an RS422A1449 multidrop application which supports high-speed operation.

One channel utilizes an Intel 8273 controller to manage the serial data transfers. Accepting the 8-bit
data bytes from the local bus, the 8273 controller
translates the data into the HOLC/SOLC format. The
channel operates in half/full-duplex mode.

Interfaces Supported

In addition to the synchronous mode, the 8273 controller operates asynchronously with NRZI encoded
data which is found in systems such as the IBM
3650 Retail Store System. An SOLC loop configuration using iSBX 352 and iSBC 88/45 products is
shown in Figure 1.
The two additional channels utilize the Intel 8274
Multi-Protocol Serial Controller (MPSC). The MPSC·
provides two independent half/full-duplex serial
channels which provide asynchronous, synchronous, HOLC or SOLC protocol operations. The sync
and async protocol operations are commonly used
to communicate with inexpensive terminals and systems.

The iSBC 88/45 AOCP board provides an excellent
foundation to support these electrical and diverse
software drivers protocol interfaces. The control
lines, serial data lines, and signal ground lines are
brought out to the three double-edge connectors.
Figure 3 shows the cable to connector construction.
Two connectors are pre-configured for RS422A1
449. All three channels are configurable for
RS232C/CCITT V.24 interfaces as shown in Table
1.
Table 1. iSBC® 88/45 Supported Configurations

The three serial channels of theiSBC 88/45 AOCP
board offer communications capability to manage a
gateway application. The gateway application, as
shown in Figure 1, manages diverse protocol requirements for data movement between channels.
Typical protocol management software layers im-

Connection

Synchronous

Asynchronous

Modem Direct Modem' Direct
Point-to-Point
Multidrop
Loop

N.A.

C
(Only)

N.A.

• Modem should not respond to break .
• 'Channels A, S, and C denoted by X.

iSBC· 18145

HOST
CPU

tl.2K lAUD
SYNC

L.-_~

210372-2

Figure 1. iSBC® 88/45 Gateway Processor Example
12-2

infef

iSBC® 88/45 BOARD

MASTER

CONNECTOR
Jl

TT
SO
RT
ISOC' 88'''5
BOARD

RO
TR
OM

CONNECTOR
Jl

I
I !

CONNECTOR

Jl
SO

I
TR

Isac' 88145
BOARD.

Isac' 88145

SLAVE A

SLAVE B

BOARD

210372-3

NOTE:
The last slave device in the system must contain termination resistors on all signal lines received by· the slave board.
The master device contains bias resistors on all signal lines.

Figure 2. Synchronous Multidrop Network Configuration Example-RS422A

CONNECTOA PIN 1

210372-4

Figure 3. Cable Construction and Installation for RS232C and RS422A/449 Interface

12-3

ISBC@88/45 BOARD

ture is designed to effectively execute the application and networking software written in higher-level
languages.

Self Clocking Point-to-Polnt Interface
The iSBC 88/45 ADCP board is used in an asynchronous mode interface when configured as shown
in Figure 4. The point-to-point AS232C example
uses the self-clocking mode interface for NAZI encoding/decoding of data. The digital phase-lock
loop allows operation of the interface in either halfduplex or full/duplex implementation with or without
modems.

CONNECTOR

J1. J2 OR J3
TaC
TaD
RTS

iSBe' 88145 eTS
BOARD Axe

This architectural support includes four 16-bit byte
addressable data registers, two 16-bit memory base
pointer registers and two 16-bit index registers.
These registers are addressable through 24 different
operand addressing modes for comprehensive
memory addressing and for high-Ievellanguag~ data
structure manipulation.
The stack-oriented architecture readily supports
Intel's iAMX executives and iMMX multiprocessing
software. Both software packages are designed for
modular application programming. Facilitating the
fast inter-module communications, the 4-byte instruction queue supports program constructs needed for real-time systems.

CONNECTOR
J1. J2 OR J3
RaC
RaO
RTS

eTS iSBe' 88/45
TxC BOARD

RaO

TIlD

OTR

OSR

OTA

Since programs are segmented between pure procedure and data, four segment registers (code,
stack, data, extra) are available for addressing 1
megabyte of memory space. These registers contain
the offset values used to address a 64K byte segment. The registers are controlled explicitly through
program control or implicitly by 'high-level language
functions and instructions.

210372-5

Figure 4. Self-Clocking or Asynchronous Pointto-Point Modem Interface Configuration
Example-RS232C

Synchronous Polnt-to-Polnt Interface
The real-time system software can also utilize the
programmable timers as shown in Table 2 and various interrupt control modes available on the ADCP
board to have responsive and effective application
solutions.

Figure 5 shows a synchronous pOint-to-point mode
of operation for the iSBC 88/45 ADCP board. This
AS232C example. uses a modem to generate the
receive clock for coordination of the data transfer.
The iSBC 88/45 ADCP board generates the transmit
synchronizing clock for synchronous transmission.

Table 2. Programmable Timer Functions
Function

CONNECTOR
J1, J2 OR J3

CONNECTOR
J1. J2 OR J3

RTS
CTS

ISBC' .,,45 TID
BOARD

CTS

R.D iSle' 81145

AID

TaD

OTR
OSR

OSR

Operation

Interrupt on Terminal An interrupt is generated on
Count
terminal count being reached.
This function is useful for
generation of real-time
clocks.

BOARD

OTA

Aate Generator

Divide by N counter. Based
on the input clock period, the
output pulse remains low until
the count is expired.

Square Wave
Generator

Output remains high for onehalf the count, goes low for
the remainder of the count.

Software Triggered
Strobe

Output remains high until
count expires, then goes low
for one clock period.

210372-6

Figure 5. SynchronousPolnt-to-Polnt Modem
Interface Configuration Example-RS232C

Central Processing Unit
The central processor for the iSBC 88/45 Advanced
Data Communications Processor board is Intel's
iAPX 8088 microprocessor operating at 8 MHz. The
microprocessor interface to other functions is illustrated in Figure 6. The microprocessor architec-

12-4

inter

iSBC® 88/45 BOARD

Numeric Data Processor Extension

Interrupt Capability

The 8088 instruction set includes 8-bit and 16-bit
signed and unsigned arithmetic operators for binary,
BCD, and unpacked ASCII data. For enhanced numerics processing capability, the iSBC 337 MULTIMODULE Numeric Data Processor extends the
8088 architecture and data set.

The iSBC 88/45 ADCP board provides nine vectored interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line. The additional eight
interrupt levels are vectored via the Intel 8259A Programmable Interrupt Controller (PIC). As shown in
Table 3, four priority processing modes are available
to match interrupt servicing. requirements. These
modes and priority assignments are dynamically
configurable by the system software.

The extended numerics capability includes over 60
numeric instructions offering arithmetic, trigonometric, tran!)cendental, logarithmic, and exponential instructions. Many math-oriented applications utilize
the 16-, 32-, and 64-bit integer, 32- and 64-bit floating point, 18-digit packed BCD, and 80-bit temporary
data types..

Table 3. Programmable Interrupt Modes
Mode

16K Bytes Static Ram
The iSBC 88/45 ADCP board contains 16K bytes of
high-speed static RAM, with 12K bytes dual-ported
which is addressable from other MULTIBUS devices. When coupled with the high-speed DMA capability of the iSBC 88/45 ADCP board, the dual-ported
memory provides effective data communication buffers. The dual-ported memory is useful for interprocessor· message transfers.

Operation

Nested

Interrupt request line priorities
fixed; interrupt 0 is the highest
and 7 is the lowest.

Auto-Rotating

The interrupt priority rotates;
once an interrupt is serviced it .
becomes the lowest priority.

Specific Priority

System software assigns
lowest level priority. The other
levels are sequenced based on
the level assigned.

Polled

System software examines
priority interrupt via interrupt
status register .

...810

AI1:I

~=:;::~AO~o!iA.!!SS~A~"~.AA~f==~
I'

MUL'IIUS'
INTERFACE

ADO-RD7 DATA

STATIC

EPROM
14K IYTES

1237. 5

OMA

DUAL

AAM

PORT

12K DUAL·PORT
41HOCAL

ACCESS
CONTROL

24·11'
SLAV(
ADDRESS
DECODE

1/"'-""'1

IIULTIBUS
ADORESSalTS
ADR,./·ADAI7

CHANNEL C

ICONNECTOR .11)

210372-7

Figure 6. Block Diagram of the ISBC® 88/45 ADCP Board
12-5

intJ

ISBC~

88/45 BOARD

In addition to specialized or custom designed iSBX
boards, the customer has a broad range of Intel
iSBC MULTIMOOULEs available, including parallel
1/0, analog 1/0, iEEE 488 GPIB, floppy disk, magnetic bubbles, video, and serial 1/0 boards.

Interrupt Request Generation
Listed in Table 4 are the devices and functions supported by interrupts on the iSBC 88/45 AOCP board.
All interrupt signals are brought to the interrupt jumper matrix.·· Any of the 23 interrupt sources are
strapped to the appropriate 8259A PIC request level.
The PIC resolves requests according to the software
selected mode and, if. the interrupt is unmasked, issues an interrupt to the CPU.

The serial 1/0 MULTIMOOULE boards include the
iSBX 351 (one ASYNC/SYNC serial channel) the
iSBX 352 (one HOLC/SOLC serial channel) and the
iSBX 354 (two SYNCIASYNC, HOLC/SOLC serial
channels) boards. Adding two iSBX 352· MULTIMODULE boards to the iSBC 88/45 AOCPprovides
a total of five HOLC/SOLC channels.

EPROM/RAM Expansion
In addition to the on-board RAM, the iSBC 88/45
AOCP boafd provides four 28-pin JEOEC sockets for
EPROM expansion. By using 2764 EPROMs, the
. board has 32K bytes of program storage. Three of
the JEOEC standard sockets also support byte-wide
static RAMs or iRAMs; using 8K x 8 static RAMs
provides an additional 24K bytes of RAM.

MULTIBUS® Multlmaster Capabilities
OVERVIEW
The MULTIBUS system is Intel's industry standard
microcomputer bus structure. Both 8- and 16-bit single board computers are supported on the MULTIBUS structure with 24 address and 16 data lines. In
addition to expanding functions contained on a single board computer (e.g., memory and digital 1/0),
the MULTIBUS structure alloWs very powerful distributed processing configurations with inultiple
processors, intelligent slaves, and . peripheral
boards.

Inserting the optional iSBC 341 MULTIMOOULE
EPROM expansion board onto the iSBC 88/45
AOCP board provides four additional 28-pin JEOEC
sites. This expansion doubles the available program
storage or extends the RAM capability by 32K bytes.

.iSBXTM MULTIMODULETM Expansion.
Two 8-bit iSBX MULTIMOOULE connectors are provided on the iSBC 88/45 microcomputer. Through
these connectors, additional iSBX functions extend
the 1/0 capability of the microcomputer. The iSBX
connectors provide the necessary signals to interface to the local bus.

Multimaster Capability
The iSBC 88/45 AOCP board provides full MULTIBUS arbitration control logic. This control

Table 4. Interrupt Request Sources
Device

Function

No. of
Interrupts

MULTIBUS Interface

Select 1 interrupt from MULTIBUS resident peripherals
or other CPU boards.

8273 HOLC/SOLC
Controller

Transmit buffer empty and receive buffer full

8274 HOLC/SOLC
SYNCI ASYNC Controller

Software examines register for status of communication
operation

8254-Timer

Counter 2 of both PIT devices

iSBX Connectors·

Function determined by iSBX MULTIMOOULE Board
(2 interrupts per socket)

Bus Fail Safe Timer

Indicates MULTIBUS addressed device has not
responded to command within 4 msec

Power Line Clock

Source of 60 MHz signal from power supply

Bus Flag Interrupt

Flag interrupt in byte location 1000H signals board reset
or data handling request

iSBC 337A Board

Numeric Data Processor generated status information

8237A-5

Signals end of 8237 OMA operation

12-6

inter

ISBC® 88/45 BOARD

logic allows up to three iSBC 88/45 ADCP boards or
other bus masters, including iSBC 286, iSBC 86 and
iSBC 86 family boards to share the system bus using
a serial (daisy chain) priority scheme. By using an
external parallel priority decoder, the MULTIBUS
system bus could be shared among sixteen masters.

to support assembler, PLlM, PASCAL, and FORTRAN software development environments. The
modular building block software lends itself well to
customized application solutions.

, SPECIFICATIONS

The Intel standard MULTIBUS Interprocessor Protocol (MIP) software, implemented as the Intel iMMX
800 package for iRMX 86 and iRMX 88 Real-Time
Executives, fully supports multiple 8- and 16-bit distributed processor functions. The software manages
the message passing protocol between microprocessors.'

Word Size
Instruction: 8, 16, 24, or 32 bits
Data: 8 or 16 bits

System Clock

System Development Capabilities

8 MHz: ±0.1%

The application development cycle for an iSBC
88/45 ADCP, board is reduced arid simplified
through the usage of several Intel tools. The tools
include the Intellec Series Microcomputer Development System, the ICE-88 In-Circuit Emulator, the
iSDM 86 debug monitor software, and the iRMX 86
and iRMX 88 run-time support packages.

NOTE:
Jumper selectable for 4 MHz operation with iSBC
337 Numeric Data Processor module or ICE-88
product.

Cycle Time

The Intellec, Series Microcomputer Development
System ,offers a complete development environment
for the iSBC 88/45 software. In addition to the operating system, assembler, utilities and application de-'
bugger features provided with the system, the user
optionally can utilize higher-level languages like
PLlM, PASCAL, and FORTRAN.

Basic Instruction Cycle at 8.00 MHz: 1.25 p.s, 250 ns
(assumes instruction in the queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles).

Memory Cycle Time
The ICE-88 In-Circuit Emulator provides a link between the Intellec system and the target iSBC
88/45-based system for code loading and execution. The ICE-88 package assists the developer with
the debugging and system integrating processes.

RAM: 500 ns (no wait states)
EPROM: jumper selectable from 500 ns to 625 ns.
On-Board RAM·
KBytes

Run-Time Building Blocks

16 (total)
12 (dual-ported)

Intel offers run-time foundation software to support
applications which range from general purpose to
high-performance solutions. The iRMX 88 Real-time
Multitasking Executive provides a multitasking struc~
ture which includes task scheduling, task manage~
ment, intertask communications, and interrupt servicing for high-performance applications. The highly
configurable modules make the system tailoring job
easier whether one uses the compact executive or
the complete executive with its variety of peripheral
devices supported.

Hex Address
Range
0000-3FFF
1000-3FFF

°Four ,sec 88/45 EPROM sockets support JEDEC 24/28pin standard EPROMs and RAMs (3 sockets); iSeC 341 (4
sockets)

Environmental Characteristics
Temperature:O'C to + 55'C, free moving air across
the base board and MULTIMODULE board
Humidity: 90%, non-condensing ,

The iRMX 86 Operating System provides a very rich
set of features and options to support sophisticated
applications solutions. In addition to supporting realtime requirements, the iRMX 86 Operating System
has a powerful, but easy-to-use human interface.
. When added to the sophisticated 110 system, the
iRMX 86 Operating System is readily extended

Physical Characteristics
Width: 30.48 cm (12.00 in)
Length: 17.15 cm (6.75 in)
Height: 1.50 cm (0.59 in)
Weight: 6.20 gm (22 oz)
12-7

inter

ISBC® 88/45 BOARD

Memory CapacityI Addressing

Electrical Characteristics

On-Board EPROM·

DC Power Dissipation-28.3 Watts

Device

Total
K Bytes

Hex Address
Range

2716
2732A
2764
27128

8
16
32
64

FEOOO-FFFFF
FCOOO-FFFFF
F8000-FFFFF
FOOOO-FFFFF

DC Power Requirements

Without EPROM(1)

'WIth optional
ISBC®341 MULTIMODULETM EPROM
Total
KBytes

Device
2716
2732A
2764
27128

Hex Address
Range

5.1A

20mA

With 8K EPROM
(Using 2716)

+0.14A

With 16K EPROM
(Using 2732A)

+0.20A

With 32K EPROM
(Using 2764)

+0.24A

With 64K EPROM
+0.24A
(Using 27128)
NOTE:
1. AS SHIPPED-no EPROMs in sockets,· no iSBC 341
module. Configuration includes terminators for two
RS422A1449 and one RS232C channels.

FCOOO-FFFFF
F8000-FFFFF
FOOOO-FFFFF
EOOOO-FFFFF
"Four ISBC 88/45 EPROM sockets support JEOEC 24/28pin standard EPROMs and RAMs (static andiRAM, 3 sockets); iSBC 341 sockets also support EPROMs and RAMs.
16
32
64
128

Timer Input Frequency-8.00 MHz

Interfaces
iSBXTM Bus-All signals TTL compatible

B
Serial RS232C Signals- .
CLEAR TO SEND
DATA SET. READY
TRANSMIT CLOCK
DATA TERMINAL READY
FRAME GROUND
REQUEST TO SEND
RECEIVE CLOCK
RECEIVE DATA
SIGNAL GROUND
TRANSMIT DATA

Supported
Interface

Max. Baud
Rate

8274(1) RS442A1449 800K SOLC/HOLC
RS232C
125K Synchronous
CCITIV.24 50K Asynchronous
125K Synchrom)us(2)
8274 RS232C
CCITIV.24 50K Asynchronous
8273(S) RS442A/449 64K SDLC/HDLC(S) .
RS232C
9.6K SELF CLOCKING
CCITIV.24

NOTES:
1. 8274 supports HOLC/SOLC/SYNC/ASYNC multiproto-

col
2. Exceed RS232C/CCITT V.24 rating of 20K baud
3. 8273 supports HOLC/SOLC
BAUD RATE EXAMPLES (Hz)
8254
Synchronous
Timer Divide
KBaud
CountN

Serial RS422A1449 SignalsCS
DM
RC
RD
RS
RT
SC
SO
SG
TR
TT

Serial Communication Characteristics

± 0.1 %

Channel Device

CTS
DSR
DTE TXC
DTR
FG
RTS
RXC
RXD
SG
TXD

.Current Requirements
(All Voltages ±5%)
-12V
+12V
+5V

Configuration

CLEAR TO SEND
DATA MODE
RECEIVE COMMON
RECEIVE DATA
REQUEST TO SEND
RECEIVE TIMING
SEND COMMON
SEND DATA
SIGNAL GROUND
TERMINAL READY
TERMINAL TIMING

10
26
31
52
104
125
143
167
417
833
EQUATION

12-8

800
300
256
154
76.8
64
56
48
19.2
9.6
8,000,000
N

Asynchronous
+16 +32 +64
KBaud
50.0
19.2
16.1
9.6
4.8
4.0
3.5
3.0

25;0
9.6
8.06
4.8
2.4
2.0
1.7
1.5

12.5
4.8
4.03
2.4
1.2
1.0
0.87
0.75

- -_. 500K 250K 125K

-N

intJ

ISBC@ 88/45 BOARD

SERIAL INTERFACE CONNECTORS
Interface
RS232C
RS232C
RS449
RS449

Mode(1)
DTE
DCE
DTE
DCE

MULTIMODULETM
Edge Connector
26-pin(4),
26-pin(4),
40-pin(5),
40-pin(5),

3M-3462-0001
3M-3462-0001
3M-3464-0001
3M-3464-0001

Cable

Connector

3M(2)-3349/25
3M(2)-3349/25
3M(3)-3349/37
3M(3)-3349/37

25-pin(6),3M-3482-1000
25-pin(6),3M-3483-1000
37-pin(7),3M-3502-1000
37-pin(7),3M-3503-1000

NOTES:
1. DTE-Data Terminal Equipment Mode (male connector); DCE-Data Circuit Equipment mode (female connector) requires
line swaps.
2. Cable is tapered at one end to fit the 3M-3462 connector.
3. Cable is tapered to fit 3M-3464 connector.
4. Pin 26 of the edge connector is not connected to the flat cable.
5. Pins 38, 39, and 40 of the edge connector are not connected to the flat cable.
6. May be used with the cable housing 3M-3485-1000.
7. Cable housing 3M-3485-4000 may be used wih the connector.

Line Drivers (Supplied)

Reference Manual

Device

Characteristic

Qty

Installed

1488
1489
3486
3487

RS232C
RS232C
RS422A
RS422A

3
3
2
2

1
1
2
2

143824-iSBC 88/45 Advanced Data Communications Processor Board Hardware Reference Manual
(not supplied).
Reference manuals maybe ordered from any Intel,
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

ORDERING INFORMATION
Part Number Description
SBC 88/45

12-9

8-bit 8088-based Single Board Computer with 3 HDLC/SDLC serial
channels

intJ

iSBC® 188/56
ADVANCED COMMUNICATING COMPUTER

• iSBC® Single Board Computer or
Intelligent Slave Communication Board
• 8 Serial· Communications Channels,
Expandable to 12 Channels on a Single
MULTIBUS® Board
'

• 7 On-Board DMA Channels for Serial
I/O, 2 80188 DMA Channels for the
iSBXTM'MULTIMODULETM Board
• MULTIBUS Interface for System
Expansion and Multimaster
Configuration

• 8 MHz 80188 Microprocessor
• Supports RS232C Interface on .6
Channels, RS422A/449 or RS232C
Interface Configurable on 2 C~annels

• 256K Bytes. Dual-Ported RAM On-Board

• Supports Async, Bisync HDLC/SDLC,
On-Chip Baud Rate Generation, Half! '
Full~Duplex, NRZ, NRZI or Frill
Encoding/Decoding

• Two 28-pin JEDEC PROM Sites
Expandable to 6 Sites with the iSBC
341 MULTIMODULE Board for a
Max.imum of 192K Bytes EPROM

• Two iSBX Connectors for Low Cost I/O
Expansion

• Resident Firmware to Handle up to 12
RS232C A~ync Lines

The iSBC 188/56 Advanced Communicating Computer (COMMputerTM) is an intelligent 8-channel single
board computer. This iSBC board adds ttie 8 MHz 80188 microprocessor-based communications flexibility to
the Intel line of OEM microcomputer systems. Acting as a stand-alone CPU or intelligent slave for communication expansion, this board provides a high performance, low-cost solution for multi-user systems. The features
of the iSBG 188/56 board are uniquely suited to manage higher-layer protocol requirements needed in today's
data communications applications. This single board computer takes full advantage of Intel's VLSI technology
to provide state-of-the-art, economic, computer based solutions for OEM communications-oriented applications.

280715-1

·IBM is a registered trademark of International Business Machines
·UNIX is a trademark of Bell Laboratories
·XENIX is a trademark of Microsoft Corporation

12-10

November 1986
Order Number: 280715-002

inter

iSBC® 188/56 ADVANCED COMM COMPUTER

OPERATING ENVIRONMENT
The iSBC 188/56 COMMputer™ features have
been designed to meet the needs of numerous communications applications. Typical applications include:
1. Terminal/cluster controller
2. Front-end processor
3. Stand-alone communicating computer

Terminal/Cluster Controller
A terminal/cluster controller concentrates communications in a central area of a system. Efficient
handling of messages coming in or going out of the
system requires sufficient buffer space to store
messages and high speed I/O channels to transmit
messages. More sophisticated applications, such as
cluster control/ers, also require character and format
conversion capabilities to aI/ow different types of terminals to be attached.
The iSBC 188/56 Advanced Communicating Computer is well suited for multi-terminal systems (see
Figure 1). Up to 12 serial channels can be serviced
in multi-user or cluster applications by adding two
iSBX 354 MULTIMODULE boards. The dual-port
RAM provides a large oncboard buffer to handle

incoming and outgoing messages at data rates up to
19.2K baud. Two channels are supported for continuous data rates greater than 19.2K baud. Each serial
channel can be individually programmed for different
baud rates to allow system configurations with differing terminal types. The firmware supplied on the
iSBC 188/56 board supports up to 12 asynchronous
RS232C serial channels, provides modem control
and performs power-up diagnostics. The high performance of the on-board CPU provideS intelligence
to handle protocols and character handling typically
assigned to the system CPU. The distribution of intelligence results in optimizing system performance
by releasing the system CPU of routine tasks.

Front-End Processor
A front-end processor off-loads a system's central
processor of tasks· such as data manipulation and
text editing of characters collected from the attached terminals. A variety of terminals require flexible terminal interfaces. Program code is often dynamically downloaded to the front-end processor
from the system CPU. Downloading code requires
sufficient memory space for protocol handling and
program code. Flow control and efficient handling of
interrupts require an efficient operating system to
manage the hardware and software resources.

I.?J ' ••.
~
.

&
ISBX" 354
BOARD

c:==:J

ISBX'" 354
BOARD

r:::::::=::::::

ISBC" 188/56
BOARD

ISBC" 86/30 BOARD

r---,-,----,

FIRMWARE

SYSTEM
PROCESSOR
MULTIBUS" SYSTEM BUS

280715-2

Figure 1. Terminal/Cluster Controller Application
12-11

intJ

ISBC® 188/56 ADVANCED COMM COMPUTER

The iSBC 188/56 board features are designed to
provide a high performance solution for front-end
processor applications -(see Figure 2). A large
amount of random access memory is provided for
dynamic storage of program code. In addition, local
memory sites are available for storing routine programs -such as X.25, SNA or bisync protocol software. The serial channels can be configured for links
to mainframe systems, point-to-point terminals, modems or multidrop configurations.

The MULTIBUS interface can be used to access additional system functions. Floppy disk control and
graphics capability can be added to the iSBC standalone computer through'the iSBX connectors.

ARCHITECTURE
The four major functional areas are Serial I/O, CPU,
Memory and OMA. These areas are illustrated in Fig"
ure 4. -

Stand-Alone COMMputer™
Application

Serial 110

A stand-alone communication computer is a complete computer system. The CPU is capable of managing the resources required to meet the needs of
multi-terminal, multi-protocol applications. These applications typically require multi-terminal. support,
floppy disk control, local memory allocation, and
program execution and storage.

Eight HOLC/SOLC serial interfaces are provided on
the iSBC 188/56 board. The serial interface can be
expanded to 12 channels by adding 2 iSBX 354
MULTIMOOULE boards. The HOLC/SOLC interface
is compatible with IBM· system and terminal equipment and with CCITI's X.25 packet switching interface.

To support stand-alone applications, the iSBC
188/56 COMMputer board uses the computational
capabilities of an on-board CPU to provide a highspeed system solution controlling 8 to 12 channels
of serial I/O (see Figure 3). The local memory available is large enough to handle special purpose
code, execution code and routine protocol software.

Four 82530 Serial - Communications Controllers
(SCC) provide eight channels of half/full duplex ser-ial 1/0. Six channels support RS232C interfaces. Two channels are RS232C/ 422/ 449 configurable and can be tri-stated to allow multidrop !letworks.
The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,

•

o
o

ISBX" 354
BOARD

c::=:::J

r---rr--,

188156
BOARD

ISBC~

80188

FIRMWARE

MULTII~US· SYSTEM BUS

280715-3

Figure 2. Front-End Processor Application
12-12

iSBC® 188/56 ADVANCED COMM COMPUTER

byte-oriented synchronous (HOLC/SOLC) modes.
The increased capability at the serial controller point
results in off-loading the CPU of tasks formerly assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to configure
it to handle all asynchronous data formats regardless of data size, number of start or stop bits, or
parity requirements .. An on-chip baud rate generator
allows independent baud rates on each channel.

Central CPU

The clock can be generated either internally with the
SCC chip, with an external clock or via the NRZ1
clock encoding mechanism.

The 80188/82530 combination with on-board
PROM/EPROM sites, and dual-port RAM provide
the intelligence and speed to manage multi-user,
multi-protocol ~ommunication operations.

All eight channels can be configured as Data Terminal Equipment (OTE) or Data Communications
Equipment (OCE). Table 1 lists the interfaces supported.
Table 1.ISBC® 188/56 Interface Support
Connection

Synchronous

Asynchronous

Modem to Direct Modem to Direct
Point-to-Point
Multidrop
Loop

X··

Channels
o and 1

N/A

The 80188 central processor component provides
high performance, flexibility and powerful processing. The 80188 component is a highly integrated microprocessor with an 8-bit data bus interface and a
16-bit internal architecture to give high performance.
The 80188 is upward compatible with 86 and 186
software.

Memory
There are two areas of memory on-board: dual-port
RAM and universal site memory. The iSBC 188/56
board contains 256K bytes of dual-port RAM that is
addressable by the 80188 on-board. The dual-port
memory is configurable anywhere in a 16M byte address space on 64K byte boundaries as addressed
from the MULTIBUS port. Not all of the 256K bytes
are visible from the MULTIBUS bus side. The
amount of dual-port memory visible to the

•• All 8 channels are denoted by X.

rFlWll

ROUTINE
PROGRAMS

80188

D
STAND-ALONE
PROCESSOR

MULTIBUS~ SYSTEM BUS

280715-4

Figure 3. Stand-Alone COMMputer™ Application
12-13

ISBC® 188/56 ADVANCED COMM COMPUTER

MULTIBUS side can be set (with jumpers) to none,
16K bytes, or 48K bytes. In a multiprocessor system
these features provide local memory for each processor and shared system memory configurations
where the total system memory size can exceed one
megabyte without addressing conflicts.
The second area of memory is universal site memory providing flexible memory expansion. Two 28-pin
JEDEC sockets are provided. One of these sockets
is used for the resident firmware as described in the
FIRMWARE section.
The default configuration of the boards supports
16K byte EPROM devices such as the Intel 27128
component However, these sockets can contain
ROM, EPROM, Static RAM, or EEPROM. Both sockets must contain the same type of component (Le.
as. the first socket contains an EPROM for the resident firmware, the second must also contain an
EPROM with the same pinout). Up to 32K bytes can
be addressed per socket giving a maximum universal site memory size of 64K bytes. By using the iSBC
341 MULTI MODULE board, a maximum of 192K
bytes of universal site memory is available. This provides sufficient memory space for on-board network
or resource management software.

On-Board DMA
Seven channels of Direct Memory. Access (DMA)
are provided between serial I/O and on-board dual
port RAM by two 8237-5 components. Each of channels 0, 1,2, 3, 5, 6, and 7 is supported by their own
DMA line. Serial channels 0 and 1 are configurable
for full duplex DMA. Configuring the full duplex DMA
option for Channels 0 and 1 would require Channels
2 and 3 to be interrupt driven or polled. Channel 4 is
interrupt driven or polled only.
Two DMA channels are integrated in the 80188
processor. These additional channels can be connected to the iSBX interfaces to provide DMA capability to iSBX MULTIMODULE boards .such as the
iSBX 218A Floppy Disk Controller MULTIMODULE
board.

OPERATING SYSTEM SUPPORT
Intel offers run-time foundation software to support
applications that range from general purpose to
high-performance solutions.

SERIAL
COMMUNICATIONS
CONTROLLERS
SCC(4)

CHANNELS

CHANNEL

7·2

1.0

RS232C

RS232CI
422/449

256K RAM

MULTIBUS· SYSTEM BUS

280715-5

Figure 4. Block Diagram of iSBC® 188/56 Board

12-14

ISBC® 188/56 ADVANCED COMM COMPUTER

Release 6 of the iRMX 86 Operating System provides a rich set of features and options to support
sophisticated stand-alone communications applications on the iSBC 188/56 Advanced Communicating
Computer. In addition to supporting real-time requirements, the iRMX 86 Operating System Release
6 has a powerful, yet easy to use human interface.
Services provided by the iRMX 86 Operating System
include facilities for executing programs concurrently, sharing resources and information, servicing
asynchronous events and interactively controlling
system resources and utilities. The iRMX 86 Operating System is readily extended to support assembler, PL/M, PASCAL, and FORTRAN software development environments. The modular building
block software lends itself well to customized application solutions. If the iSBC 188/56 board is acting
as an intelligent slave in a system environment, an
iRMX 86 driver resident in the host CPU can be written by following the examples in the manual "Guide
to Writing Device Driven for iRMX 86 and iRMX 88
I/O Systems".
The iSDMTM 86 System Debug Monitor supports target system debugging for the iSBC 188/56 Ad-

vanced Communicating COMMputer board. The
monitor contains the necessary hardware, software
and documentation required to interface the iSBC
188/56 target system to an Intel microcomputer development system for debugging application software.
The XENIX' 286 Operating System, Release 3, is a
fully licensed adaptation of the Bell Laboratories
System III UNIX' Operating System. The XENIX system is an interactive, protected, multi-user, multitasking operating system with a powerful, flexible
human interface. Release 3 of XENIX 286 includes a
software driver for the iSBC 188/56 board (and up to
two iSBX 354 MULTIMODULE Boards) acting as an
intelligent slave for multi-user applications· requiring
multiple persons running independent, terminal-oriented jobs. Example applications include distributed
data processing, business data processing, software
development and engineering or scientific data analysis. XENIX 286 Release 3 Operating System services include device independent I/O,tree-structured
file directory and task hierarchies, re-entrantlshared
code and system accounting and security access
protection.

Table 2. Features of the ISBC® 188/56 Firmware
Feature

Description

Asynchronous Serial
Channel Support

Supports the serial channels in asynchronous ASCII mode.
Parameters such as baud rate, parity generation, parity
checking and character length can be programmed
independently for each channel.

Block Data Transfer
(On Output)

Relieves the host CPU of character-at-a-time interrupt
processing. The iSBC 188/56 board accepts blocks of data for
transmission and interrupts the processor only when the entire
block is transmitted.

Limited Modem Control

Provides software control of the Data Terminal Ready (DTR)
line on all channels. Transitions on the Carrier Detect (CD) line
are sensed and reported to the host CPU.

Tandem Modem Support

Transmits an XOFF character when the number of characters
in its receive buffer exceeds a threshold value and transmits an
XON character when the buffer drains below some other
threshold.

Download and
Execute Capability

Provides a capability for the host CPU to load code anywhere in
the address space of the iSBC 188/56 board and to start
executing at any address in its address space.

Power Up
Confidence Tests

On board reset, the firmware executes a series of simple tests
to establish that crucial components on the board are
functional.

12-15

inter

iSBC® 188/56 ADVANCED COMM COMPUTER

FIRMWARE
The iSBC 188/56 Communicating· COMMputer
bo~rd is supplied with resident firmware that supports up to 12 RS232C asynchronous serial channels. In addition, the firmware provides a facility for a
host CPU to download and· execute code on the
iSBC 188/56 board. Simple power-up confidence
tests are also included to provide a quick diagnostic
service. The firmware converts the iSBC 188/56
COMMpt.iter board to a slave communications controller. As a slave communications controller, It requires a separate MULTIBUS host CPU board and
requires the use of MULTIBUS interrupt line to signal
the host processor. Table 2 summarizes the features of the firmware.

INTERRUPT CAPABILITY

80188 processor and the other in the 80130 component. The two· controllers are configured with the
80130 controller as the master and the 80188 controller as the slave. Two of the 80130 interrupt inputs
are connected to the 82530 serial controller components to provide vector interrupt capabilities by the
serial controllers. The iSBC 188/56 board provides
22 interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line which is directly tied to
the 80188 CPU. This interrupt is typically used for
signaling catastrophic events (e.g. power failure).
There are 5 levels of interrupts internal to the 80188
processor. Another 8 levels of interrupts are available from th~ 80130 component. Of these 8, one is
tied to the programmable interrupt controller (PIC) of
the 80188 CPU. An additional 8 levels of interrupts
are available at the MULTIBUS interface. The iSBC
188/56 board does not support bus vectored interrupts. Table 3 lists the possible interrupt sources.

The iSBC 188/56 board has two programmable interrupt controllers (PICs). One is integrated into the
Table 3. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS Interface
INTO-INT7

. Requests from MULTIBUS resident peripherals or other
CPU boards.

82530 Serial Controllers

Transmit buffer empty, receive buffer full and channel
errors 1 and external status.

Internal 80188
Timer and DMA

Timer 0, 1,2 outputs and 2 DMA channel interrupts.

80130 Timer Outputs

Timer 0, 1, 2 outputs of 80130.

Interrupt from Flag
Byte Logic

Flag byte interrupt set by MULTIBUS master (through
MULTIBUS® I/O Write).

Bus Flag Interrupt

Interrupt to MULTIBUS® (Selectable for INTO to INT7)
generated from on-board 80188 I/O Write.

iSBX Connectors

Function determined by iSBX MULTIMODULE board.

8
8 per 82530
Total = 32
5

4 (Two per
Connector)
2

iSBXDMA

DMA interrupt from iSBX (TDMA).

Bus Fail-Safe Timeout
Interrupt.

Indicates iSBC 188/48 board timed out either waiting for
MULTIBUS access or timed out from no acknowledge
while on MULTIBUS System Bus.

Latched Interrupt

Converts pulsed event to a level interrupt. Example:
8237A-5 EOP.

OR-Gate Matrix

Concentrates up to 4 interrupts to 1 interrupt (selectable
by stake pins).

Ring Indicator
Interrupt

Latches a ring indicator event from serial channels 4, 5,
6,or7.

NOR-Gate
Matrix

Inverts up to 2 interrupts into 1 (selectable by stake
pins).

12-16

intJ

iSBC® 188/56 ADVANCED COMM COMPUTER

SUPPORT FOR THE 80130
COMPONENT
Intel does not support the direct processor execu. tion of the iRMX nucleus primitives from the 80130
component. The 80130 component provides timers
and interrupt controllers.

The Multimaster capabilities of the iSBC 188/56
board offers easy expansion of processing capacity
and the benefits of mUltiprocessing. Memory and
I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expanSion boards.

SPECIFICATIONS
EXPANSION
Word Size
EPROM Expansion
Memory may be expanded by adding Intel compatible memory expansion boards. The universal site
memory can be expanded to six sockets by adding
the iSBC 341 MULTIMODULE board for a maximum
total of 192K bytes of universal site memory.

Instruction-8, 16, 24 or 32 bits
Data Path-8 bits
Processor Clock
82530 Clock
8MHz
4.9152 MHz

DMAClock
4MHz

Dual Port RAM
iSBC 188/56 Board-256 bytes

iSBXTM MULTIMODULETM Expansion
Module

As viewed from the 80188-64K bytes

Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 188/56 board. Using iSBX modules additional functions can be added to extend the
I/O capability of the board. In addition to specialized
or custom designed iSBX boards, there is a broad
range of iSBX MULTIMODULE boards from the Intel
including parallel 110, analog I/O, IEEE 488 GPIB,
floppy disk, magnetic bubbles, video and serial I/O
boards.
The serial I/O MULTIMODULE boards available include the iSBX 354 Dual Channel Expansion MULTIMODULE board. Each iSBX 354 MULTIMODULE
board adds two channels of serial I/O to the iSBC
188/56 board for a maximum of twelve serial channels. The 82530 serial communications controller on
the MULTIMODULE board handles a large variety of
serial communications protocols. This is the same
serial controller as is used on the iSBC 188/56
board to offer directly compatible expansion capability for the iSBC 188/56 COMMputer board.

As viewed from the MULTIBUS System BusChoice: 0, 16K or 48K

EPROM
iSBC® 188/56
On Board
Size
Address Range
Board Using:
Capacity
2732
2764
27128
27256
27512

Memory Expansion

MULTIBUS® INTERFACE
The iSBC 188/56 Advanced COMMputer board can
be a MULTIBUS master or intelligent slave in a multimaster system. The iSBC 188/56 board incorporates a flag byte signalling mechanism for use in
multiprocessor environments where the iSBC
188/56 board is acting as an intelligent slave. The
mechanism provides an interrupt handshake from
the MULTIBUS System Bus to the on-board-processor and vice-versa.

8K bytes FEOOO-FFFFFH
4K
8K 16K bytes FCOOO-FFFFFH
16K 32K bytes F8000-FFFFFH
32K 64K bytes FOOOO-FFFFFH
64K 128K bytes EOOOO-FFFFFH

EPROM with
iSBC® 341
Board Using:

Capacity

Address Range

2732
2764
27128
27256

24K bytes
48K bytes
96K bytes
192K bytes

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

I/O Capacity
Serial-8 programmable lines using four 82530 components
iSBX MULTIMODULE-2 iSBX single-wide boards

12-17

intJ

iSBC®188/56 ADVANCED COMM COMPUTER

Serial Communications Characteristics

SERIAL RS232C SIGNALS

Synchronous-Internal or external character synchronization on one or two synchronous characters

CD
CTS
DSR
DTE TXC
DTR
RTS
RXC
RXD
SG
TXD
RI

Asynchronous-5-8 bits and 1. 1%. or 2 stop bits
per character; programmable clock factor; break detection and generation; parity. overrun. and framing
error detection.

Baud Rates
Synchronous
X1 Clock

Carrier
Clear to Send
Data Set Ready
Transmit Clock
Data Terminal Ready
Request to Send
Receive Clock
Receive Data
Signal Ground
Transmit Data
Ring Indicator

RS422A/449 SIGNALS

Baud Rate

82530 Count Value
(DeCimal)

64000
48000
19200
9600
4800
2400
1800 .
1200
300

36
49
126
254
510
1022
1363
2046
8190

RC
RD
RT
SO
TT

Receive Common
Receive Data
Receive Timing
Send Data
Terminal Timing

Environmental Characteristics
Temperature: Oto 55·C at 200 Linear Feet/Min.
(LFM) Air Velocity
Humidity:

Asynchronous
X16Clock

to 90%. non-condensing (25·C to
70·C)

Physical Characteristics

Baud Rate

82530 Count Value
(Decimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Width:
Length:
Height:
Weight:

30.48 cm(12.00 in)
17.15 cm (6.75 in)
1.04 cm (0.41 in)
595 gm (21 oz)

Electrical Characteristics
The power required per voltage for the iSBC 188/56
board is shown below. These numbers do not include the current requ,ired by universal memory sites
or expansion modules.

Interfaces
iSBXTM BUS

The iSBC 188/56 board meets iSBX compliance level 08/8 DMA

Voltage
(Volts)

Current
(Amps) typo

Power
(Watts) typo

+5
+12
-12

4.56A
0.12A
0.11A

22.8W
1.5W
1.3W

Reference Manual
iSBC 188/56 Advanced Data Communications Computer Reference Manual Order Number 148209-001.

MULTIBUS® SYSTEM BUS

The iSBC 188/56 board meets MULTIBUS compliance level Master/Slave 08 M24 116 VO EL.

ORDERING INFORMATION
Part Number

Description

iSBC 188/56

8-Serial Channel Advanced Communicating Computer

12-18

iSBC® 534
FOUR CHANNEL COMMUNICATION EXPANSION BOARD

•

•
•
•

Serial 1/0 Expansion Through Four
Programmable Synchronous and
Asynchronous Communications
Channels
Individual Software Programmable
Baud Rate Generation for Each Serial
1/0 Channel
Two Independent Progammable 16·Bit
Interval Timers
Sixteen Maskable Interrupt Request
Lines with Priority Encoded and
Programmable Interrupt Algorithms

•
•
•
•
•

Jumper Selectable Interface Register
Addresses
16·Bit Parallel 1/0 Interface Compatible
with Bell 801 Automatic Calling Unit
RS232C/CCITT V.24 Interfaces Plus 20
mA Optically Isolated Current Loop
Interfaces (Sockets)
Programmable Digital Loopback for
Diagnostics
Interface Control for Auto Answer and
Auto Originate Modems

The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of memory
and I/O expansion boards. The iSBC 534 interfaces directly to any single board computer via the MULTIBUS
to provide expansion of system serial communications capability. Four fully programmable synchronous and
asynchronous serial channels with RS232C buffering and provision for 20 mA optically isolated current loop
buffering are provided. Baud rates, data formats, and interrupt priorities for each channel are individually
software selectable. In addition to the extensive complement of EIA Standard RS232C signals provided, the
iSBC 534 provides 16 lines of RS232C buffered programmable parallel I/O. This interface is configured to be
directly compatible with the Bell Model 801 automatic calling unit. These capabilities provide a flexible and
easy means for interfacing Intel iSBC based systems to RS232C and optically isolated current loop compatible
terminals, cassettes, asynchronous and synchronous modems, and distributed processing networks.

280238-1

12·19

November 1986
Order Number: 280238-001

ISBC® 534 COMMUNICATION BOARD

FUNCTIONAL DESCRIPTION

Table 1. Programmable Timer Functions

Communications Interface
Four .programmable communications interfaces using Intel's 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) are contained
on the board.' Each USART can be programmed by
the system software to individually select the desired
asynchronous or synchronous serial data transmission technique (including IBM Bisync). The mode of
operation (Le., synchronous or asynchronous), data
format, control character format, parity, and baud
rate are ail under program control. Each 8251A provides full duplex, double buffered transmit and receive capability. Parity, overrun, and framing error
detection are all incorporated in each USART. Each
set of RS232C command lines, serial data lines, and
signal ground lines are brought out to 26-pin edge
connectors that mate with RS232C flat or round cables.

16-Bit Interval Timers
The iSBC 534 provides six fully programmable and
independent BCD and binary 16-bit interval timers
utilizing two Intel 8253 programmable interval
timers.' Four timers are available to the systems designer to generate baud rates for the USARTs under
software control. Routing for the outputs from the
other two counters is jumper selectable. Each may
be independently routed to the programmable interrupt controller to provide real time clocking or to the
USARTs (for applications requiring different transmit
and receive baud rates). In utilizing the iSBC 534,
the systems designer simply configures, via software, each timer independently to meet system requirements. Whenever a given baud rate or time delay is needed, software commands to the programmable timers select the desired function. Three
functions of these timers are supported on the iSBC
534, as shown in Table 1. The contents of each
counter may be read at any time during system operation.

Function

Operation

Interrupt on
terminal count

When terminal count is
reached an interrupt request is
generated. This function is
used for the generation of realtime clocks.

Rate generator

Divide by N counter. The output
will go low for one input clock
cycle and high forN-1 input
clock periods.

Square wave
rate generator

Output will remain high for onehalf the count and low for the
other half of the count.

Interrupt Request Lines
Two independent Intel 8259A programmable interrupt controllers (PIC's) provide vectoring for 16 interrupt levels.' As shown in Table 2, a selection of
three priority processing algorithms is available to
the system designer. The manner in which requests
are serviced may thus be configured to match system requirements. Priority assignments may be reconfigured dynamically via software at any time during system operation. Any combination of interrupt
levels may be masked through storage, via software,
of a single byte to the interrupt mask register of each
PIC. Each PIC's interrupt request output line may be
jumper selected to drive any of the nine interrupt
lines on the MULTIBUS.

12-20

Table 2. Interrupt Priority Options
Algorithm

Operation

Fully
nested

Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

Autorotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Specific
priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
aSSignment.

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RS232C
COMPATIBLE
DEVICE

CURRENT

RS232C

CURRENT

RS232C

LOOP
DEVICE

COMPATIBLE

LOOP

COMPATIBLE

LOOP

COMPATIBLE

LOOP

DEVICE

OM""

DEVICE

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INTERFACE

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:s::

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~

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N
~

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3

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III

=
0
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III

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n

iii'
co
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2
PROGRAMMABLE

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aUNES

IUNES

280238-2

intJ

ISBC® 534 COMMUNICATION BOARD

Interrupt Request Generation-As shown in Table
3, interrupt requests may originate from 16 sources.
Two jumper selectable interrupt requests (8 total)
can be automatically generated by each USART
when a character is ready to be transferred to the
MULTIBUS system bus (Le., receive buffer is full) or
a character has been transmitted (transmit buffer is
empty). Jumper selectable requests can be generated by two of the programmable timers (PITs), and six
lines are routed directly from peripherals to accept
carrier detect (4 lines), ring indicator, and the Bell
801 present next digit request lines.

Asynchronous- 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits;
false start bit detection.

Sample Baud Rates(1)
Frequency(2)
Baud Rate (Hz)
(kHz, Software
Selectable)
Synchronous Asynchronous

Systems Compatibility
The iSBC 534 provides 16 RS232C buffered parallel
1/0 lines implemented utilizing an Intel 8255A programmable peripheral interface (PPI) configured to
operate in mode 0." These lines are configured to
be directly compatible with the Bell 801 automatic
calling unit. (ACU). This capability allows the
iSBC 534 to interface to Bell 801 type ACUs and up
to four modems or other serial communications devices. For systems not requiring interface to an ACU,
the parallel 1/0 lines may also be used as general
purpose RS232C compatible control lines in system
implementation.
"NOTE:
Complete operational details on the Intel 8251A
USART, the Intel 8253 Programmable Interval Timer, the Intel 8255A Programmable Peripheral· Interface, and the Intel 8259A Programmable Interrupt
Controller are contained in the Intel Component
Data Catalog.

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

·0
1
2
3
4
5
6
7

PIC 1

PORTO Rx RDY
PORTOTx RDY
PORT 1 RxRDY
PORT 1 TxRDY
PORT 2 Rx RDY
PORT2TxRDY
PORT 3 RxRDY
PORT3TxRDY

PIT 1 counter 1
PIT 2 counter 2
Ring Indicator (all ports)
Present next digit
Carrier detect port 0
Carrier detect port 1
Carrier detect port 2
Carrier detect port 3

2400
1200
600
300
150
75
110

Interval Timer and Baud Rate
Generator Frequencies
Input Frequency (On-Board Crystal Oscillator)1.2288 MHz ± 0.1% (0.813,.,.s period, nominal)

PICO

+ 64

9600
4800
2400
1200
600
300

NOTES:
1. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 kHz may be generated utilizing
on-board crystal oscillator and 16-bit programmable interval timer (used here as frequency divider).
2. Frequency selected by I/O writes of appropriate 16-bit
frequency factor to Baud Rate Register.

Table 3. Interrupt Assignments
Interrupt
Request
Line

+ 16

Function

Real-Time
Interrupt
Interval

Single Timer

Dual/Timer
Counter
(Two Timers
Cascaded)

Min

Max

Min

Max

1.63,...s

53.3 ms

3.26,...s

58.25
minutes

Rate
Generator
18.75 Hz 614.4 kHz 0.0029 Hz 307.2 kHz
(Frequency)

SPECIFICATIONS
Serial Communications Characteristics
Synchronous- 5·8 bit characters; internal or external character synchronization; automatic sync insertion.
12-22

inter

ISBC® 534 COMMUNICATION BOARD

Interfaces-RS232C Interfaces

Physical Characteristics

EIA Standard RS232C Signals provided and supported:
Carrier detect
Receive data
Ring indicator
Clear to send
Secondary receive data
Data set ready
Data terminal ready Secondary transmit data
Transmit clock
Request to send
Receive clock
Transmit data

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 14 oz. (398 gm)

Parallel 1/0-8 input lines, 8 output lines, all signals
RS232C compatible

Average DC Current

Electrical Characteristics
Without
With
Opto-Isolators Opto-lsolators(1)
1.9A, max
1.9A,max
Vee = +5V
420 mA, max
Voo = +12V 275mA, max
400mA, max
VAA = -12V 250mA, max
Voltage

Bus-All Signals MULTIBUS system bus compatible

I/O Addressing
The USART, interval timer, interrupt controller, and
parallel interface registers of the iSBC 534 are configured as a block of 16 110 address locations. The
location of this block is jumper selectable to begin at
any 16-byte 110 address boundary (i.e., OOH, 10H,
20H, etc.).

NOTE:
1. Wilh four 4N33 and four 4N37 apia-isolator packages
installed in sockets provided to implement four 20 rnA current loop interfaces.

Environmental CharacteristiCS
Operating Temperature: O·C to +55·C

I/O Access Time
400 ns
400 ns
400 ns
400 ns

USART registers
Parallel I/O registers
Interval timer registers
Interrupt controller registers

Reference Manual
502140-002-iSBC 534 Hardware Reference Manual (NOT SUPPLIED)

Compatible Connectors
Interface

Pins Centers
(qty.) (in.)

Bus
86
Serial and
26
parallel 110

0.156
0.1

Mating Connectors
Viking2KH43/9 AMK12
3m 3462-0001 or
TIH312113

Compatible Opto-Isolators
Function
Driver

Receiver

Supplier
Fairchild
General Electric
Monsanto
Fairchild
General Electric
Monsanto

Part Number
4N33

ORDERING INFORMATION
Part Number Description
SBC 534
Four Channel Communication Expansion Board

4N37

12-23

inter

iSBC® 544
INTELLIGENT COMMUNICATIONS CONTROLLER

Communications Controller
• iSBC®
Acting as a Single Board

•
•
•
•

Communications Computer or an
Intelligent Slave for Communications
Expansion
On-Board Dedicated BOB5A
Microprocessor Providing
Communications Control and Buffer
Management for Four Programmable
SynchronC)us/ Asynchronous Channels
Sockets for Up To BK Bytes of EPROM
16K Bytes of Dual Port Dynamic Read/
Write Memory with On-Board Refresh
Extended MULTIBUS® Addressing
Permits iSBC 544 Board Partitioning
Into 16K-Byte Segments in a
1-Megabyte Address Space

Programmable Parallel I/O Lines
• Ten
Compatible with Bell B01 Automatic
Calling Unit
Levels of Programmable
• Twelve
Interrupt Control
Individual Software Programmable
• Baud
Rate Generation for Each Serial
I/O Channel

•
•

Three Independent Programmable
Interval Timer/Counters
Interface Control for Auto Answer and
Auto Originate Modem

The iSBC 544 Intelligent Communications Controller is a member of Intel's family of single-board computers,
memory, I/O, and peripheral controller boards. The iSBC 544 board is a complete communications controller
on a single 6.75 x 12.00 inch printed circuit card. The on-board SOS5A CPU may perform local communications
processing by directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous serial I/O ports, RS232/RS366 compatible parallel I/O, programmable timers, and
programmable interrupts.
.

280239-1

12-24

November 1986
Order Number: 280239-001

inter

iSBC® 5.4.4 COMMUNICATIONS CONTROLLER

SOS5A CPU to coordinate up to four serial channels.
Using the iSSC 544 as an intelligent slave, multichannel serial transfers can be managed entirely onboard, freeing the bus master to perform other system functions.

FUNCTIONAL DESCRIPTION

Intelligent Communications Controller
Two Mode Operation - The iSSC 544 board is
capable of operating in one of two modes: 1) as a
single board communications computer with all computer and communications interface hardware on a
single board; 2) as an "intelligent bus slave" that
can perform communications related tasks as a peripheral processor to one or more bus masters. The
iSSC 544 may be configured to operate as a standalone single board communications computer with
all MPU, memory and I/O elements on a single
board. In this mode of operation, the iSSC 544 may
also interface with expansion memory and I/O
boards (but no additional bus masters). The iSSC
544 performs as an intelligent slave to the bus master by performing all communications related tasks.
Complete synchronous and asynchronous I/O and
data management are controlled by the on-board

r -

SERiAL

To -

SEAiiLliO -

Architecture - The iSSC 544 board is functionally
partitioned into three major sections: I/O, central
computer, and shared dual port RAM memory (Figure 1). The I/O hardware is centered around the four
Intel S251A USART devices providing fully programmable serial interfacing. Included here as well is a
10-bit parallel interface compatible with the Sell S01
automatic calling unit, or equivalent. The I/O is under full control of the on-board CPU and is protected
from access by system bus masters. The second
major segment of the intelligent communications
controller is a central computer, with an SOS5A CPU
providing powerful processing capability. The SOS5A
together with on-board EPROM/ROM, static RAM,
programmable timers/counters, and programmable

sERiALiiO -

SERiAL

"'0 - -

- -

PARAillLii'o -

--,

I
I

I
I
I
I
I

I
I
I
rI

I
I
I

PROGRAMMABLE 1/0

-r-------~

R~hNE~~::%~~Y

TRANSMlnER READY

R~~~T,~'l>~g:l~~

I
I
I

CARRIER DETECT

..K ••

I
I
I

DYNAMIC
RAM

I
I

r----~--J

I CENTRAL COMPUTER
L
___________________

r------,

;--_ _ _ _....J

L..-""7'<,.-....J

-L _ _

_ _ _ y~L~~T..!!A~ M.!M~~

MULTI.US

280239-2

Figure 1. iSBC® 544 Intelligent Communications Controller Block Diagram
12-25

intJ

iSBC® 544 COMMUNICATIONS CONTROLLER

Bell Model S01, or equivalent, and can also be used
for auxiliary functions. All signals are RS232C compatible, and the interface cable signed assignments
meet RS366 specifications. For systems not requiring an ACU interface, the parallel I/O port can be
used for any general purpose interface requiring
RS232C compatibility.

interrupt control provide the intelligence to manage
sophisticated communications operations on-board
the iSBC 544 board. The timer/counters and interrupt control are also common to the I/O area providing programmable baud rates to the USARTs and
prioritizing interrupts generated from the USARTs.
The central computer functions are protected for access only by the on-board SOS5A. Likewise, the onboard SOS5A may not gain access to the system bus
when being used as an intelligent slave. When the
iSBC 544 is used as a bus master, the on-board
SOS5A CPU controls complete system operation accessing on-board functions as well as memory and
I/O expansion. The third major segment, dual port
RAM memory, is the key link between the iSBC 544
intelligent slave and bus masters managing the system functions. The dual port concept allows a common block of dynamic. memory to be accessed by
the on-board S085A CPU and off-board bus masters. The system program can, therefore, utilize the
shared dual port RAM to pass command and status
information between the bus masters and on-board
CPU. In addition, the dual port concept permits
blocks of data transmitted or received to accumulate
in the on-board shared RAM, minimizing the need
for a dedicated memory board.

Central Processing Unit
Intel's powerfulS-bit n-channelSOS5A CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 544. The SOS5A CPU is directly software
compatible with the Intel SOSOA CPU. The SOS5A
contains six S-bit general purpose registers and an
accumulator; The six general purpose registers may
be addressed individually or in pairs, providing both
single and double precision operators. The minimum
instruction execution time is 1.45 microseconds. The
SOS5A CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 544
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.

Serial 1/0
Four programmable communications interfaces using Intel's S251A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) are contained
on the board and controlled by the on-board CPU in
combination with the on-board interval timer / coun,ter to provide all common communication frequencies. Each USART can be programmed by the system software to individually select the desired asynchronous or synchronous serial data transmission
technique (including IBM Bisync). The mode of operation (Le., synchronous or asynchronous), data format, control character format, parity, and baud rate
are all under program control. Each S251A provides
full duplex, double-buffered, transmit and receive capability. Pa(ity, overrun, and framing error detection
are all incorporated in each USART. Each channel is
fully buffered to provide a direct interface to RS232C
compatible terminals, peripherals, or synchronous/
asynchronous modems. Each channel of RS232C
command lines, serial data lines, and signal ground
lines are brought out to 26-pin edge connectors that
mate with RS232C flat or round cable.

Parallel 1/0 Port
The iSBC 544 provides a 10-bit parallel 110 interface
controlled by an Intel S155 Programmable Interface
(PPI) chip. The parallel I/O port is directly compatible with an Automatic Calling Unit (AGU) such as the

·EPROM/ROM Capacity
Sockets for up to SK bytes of nonvolatile read only
memory are provided on the iSBC 544 board. Read
only memory may be added in 2K byte increments
up to a maximum of 4K bytes using Intel 2716
EPROMs or masked ROMs; or in 4K byte increments up to SK bytes maximum using Intel 2732
EPROMs. All on-board EPROM/ROM operations
are performed at maximum processor speed.

RAM Capacity
The iSBC 544 contains 16K bytes of dynamic read/
write memory using Intel 2117 RAMs. Power for the
on-board RAM may be provided on an auxiliary power bus, and memory protect logic is included for
RAM battery backup requirements./The iSBC 544
contains a dual port .controller, which provides dual
port capability for the on-board RAM memory. RAM
accesses may occur from either the on-board SOS5A
CPU or from another bus master, when used as an
intelligent slave. Since on-board RAM accesses do
not require the MULTIBUS, the bus is available for
concurrent bus master use. Dynamic RAM refresh is
accomplished automatically by the iSBC 544 for accesses originating from either the CPU or from the
MULTIBUS.

12-26

iSBC® 544 COMMUNICATIONS CONTROLLER

Addressing - On board RAM, as seen by the onboard 8085A CPU, resides at address 8000HBFFFH. On-board RAM, as seen by an off-board
CPU, may be placed on any 4K byte address boundary. The iSBC 544 provides extended addressing
jumpers to allow the on-board RAM to reside within
a one megabyte address space when accessed via
the MULTIBUS. In addition, jumper options are provided which allow the user to protect 8K or 12K
bytes on-board RAM for use by the on-board 8085
CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address space.
Static RAM - The iSBC 544 board also has 256
bytes of static RAM located on the Intel 8155 PPI.
This memory is only accessible to the on-board
8085A CPU and is located at address 7FOOH7FFFH·

Programmable Timers
The iSBC 544 board provides seven fully programmable and independent interval timer/counters utilizing two Intel 8253 Programmable Interval Timers
(PIT), and the Intel 8155. The two Intel 8253 PITs
provide six independent BCD or binary 16-bit interval
timer/counters and the 8155 provides one 14-bit binary timer/counter. Four of the PIT timers (BDGO-3)
are dedicated to the USARTs providing fully independent programmable baud rates.
Three General Use Timers - The fifth timer
(BDG4) may be used as an auxiliary baud rate to any
of the four USARTs or may alternatively be cascaded with timer six to provide extended interrupt inter-

vals. The sixth PIT timer/counter (TINT1) can be
used to generate interrupt intervals to the on-board
8085A. In addition to the timer/counters on the 8253
PITs, the iSBC 544 has a 14-bit timer available on
the 8155 PPI providing a third general use timer/
counter (TINTO). This timer output is jumper selectable to the interrupt structure of the on-board 80B5A
CPU to provide additional timer/counter capability.
Timer Functions - In utilizing the iSBC 544 board,
the systems designer simply configures, via software, each timer independently to meet systems requirements. Whenever a given baud rate or interrupt
interval is needed, software commands to the programmable timers select the desired function. The
on-board PITs together with the 8155 provide a total
of seven timer/counters and six operating modes.
Mode 3 of the 8253 is the primary operating mode of
the four dedicated USART baud rate generators.
The timer/counters and useful modes of operation
for the general use timer/counters are shown in Table 1.

Interrupt Capability
The iSBC 544 board provides interrupt service for up
to 21 interrupt sources. Any of the 21 sources may
interrupt the intelligent controller, and all are brought
through the interrupt logic to 12 interrupt levels. Four
interrupt levels are handled directly by the interrupt
processing capability of the 8085A CPU and eight
levels are serviced from an Intel 8259A Programmable Interrupt Controller (PIC) routing an interrupt request output to the INTR input of the BOB5A (see
Table 2).

Table 1. Programmable Timer Functions
Function

Operation

Interrupt on Terminal
Count (Mode O)

When terminal count is reached, an interrupt request is
generated. This function is useful for generation of realtime clocks.

Rate Generator
(Mode 2)

Divide by N counter. The output will go low for one input
clock cycle and high for N - 1 input clock periods.

Square-Wave Rate
Generator (Mode 3)

Output will remain high until one-half the TC has been
completed, and go low for the other half of the count.
This is the primary operating mode used for generating a
Baud rate clocked to the USARTs.

Software Triggered
Strobe (Mode 4)

When the TC is loaded, the counter will begin. On TC
the output will go low for one input clock period.

Single Pulse

Single pulse when TC reached.

Counter

8253
TINT1

8253
BDG4*

8253
BDGO-4
TINT1

8253
BDG4*
TINT1

8155
TINTO

Repetitive Single Pulse

Repetitive single pulse each time TC is reached until a
new command is loaded .

8155
TINTO

• BDG4 is jumper selectable as an auxiliary baud rate generator to the USARTs or as a cascaded output to TINT1. BDG4'
may be used ,in modes 2 and 4 only when configured as a cascaded output.
.

12-27

iSBC® 544 COMMUNICATIONS CONTROLLER

to the 8085A interrupt inputs, TRAP, RST 7.5, RST
6.5 and RST 5.5 have a unique vector memory address. An8085A jump instruction at each of these
addresses then provides software linkage to interrupt service routines located independently anywhere in the Memory. All interrupt inputs with the
exception of the TRAp may be masked via software.

Table 2 Interrupt Vector Memory Locations
Interrupt
Source

Vector
Location

Power Fail
TRAP
24H
RST7.5
8253 TINT1
3CH
8155 TINTO
Ring Indicator(1) RST 6.5
34H
Carrier Detect
Flag Interrupt
RST 5.5
2CH
INTOI -INT7 I (1 of 8)
RXRDYO
INTR
Programmable
TXRDYO
RXRDY1
TXRDY1
RXRDY2
TXRDY2
RXRDY3
TXRDY3

Interrupt
Level
1
2
3

8259A Interrupts -

4
5-12

NOTE:
1. Four ring indicator interrupts and four carrier detect interrupts are summed to the RST 6.5 input. The 8155may be
interrogated to inspect anyone of the eight signals.
Interrupt Sources - The 22 interrupt sources originate from both on-board communications functions
and the MULTIBUS. Two interrupts are routed from
each of the four USARTs (8 interrupts total) to indicate that the transmitter and receiver are ready to
move a data byte to or from the on-board CPU. The
PIC is dedicated to accepting these 8 interrupts to
optimize USART service request. One of eight interrupt request lines are jumper selectable for direct
interface from a bus master via the system bus. Two
auxiliary timers (TINTO from 8155 and TINT1 from
8253) are jumper selectable to provide general purpose counterltimer interrupts. A jumper selectable
Flag Interrupt is generated to allow any bus master
to interrupt the iSBC 544 by writing into the base
address·of the shared dual port memory accessable
to thesysteni. The Flag .Interrupt is then cleared by
the iSBC 544 when the on-board processor reads
the base address. This interrupt provides an interrupt link between a bus master and intelligent slave
(see System Programming). Eight inputs from the
serial ports are monitored to detect a ring indicator
and carrier detect from each of the four channels.
These eight interrupt sources are summed to a single interrupt level of the 8085A CPU. If one of these
eight interrupts occur, the 8155 PPI can then be interrogated to determine which port caused the interrupt. Finally, a jumper selectable Power Fail Interrupt
is available from the MULTIBUS to detect a power
down condition.

8085 Interrupt - Thirteen of the twenty-two

inter~

rupt sources are available directly to four interrupt
inputs of the on-board S085A CPU. Requests routed

Eight interrupt sources signaling transmitter and receiver ready from the four
USARTs are channeled directly to the Intel 8259A
PIC. The PIC then provides vectoring for the next
eight interrupt levels. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts transmitter and receiver interrupts from
the four USARTs. It then determines which of the
incoming requests is of highest priority, determines
whether this request is of higher priority than the level currently being serviced, and , if appropriate, issues an interrupt to the CPU. The output of the PIC
is applied directly to the INTR input of the 8085A.
Any combination of interrupt levels may be masked,
via software, by storing a single byte in the interrupt
mask register of the PIC. When the 8085A responds
to a PIC interrupt, the PIC will generate a CALL instruction .for each interrupt level. These addresses
are equally spaced at intervals of 4 or 8 (software
selectable) bytes. Interrupt response to the PIC is
software programmable to a 32- or 64-byte block of
memory. Interrupt sequences may be expanded
from this block with a single 80S5A jump instruction
at each of these addresses.
Interrupt Output - In addition, the iSBC 544 board
may be jumper selected to generate an interrupt
from the on-board serial output data (SOD) of the
8085A. The SOD signal may be jumpered to anyone
of the 8 MULTIBUS interrupt lines (INTOI -INT7 I) to
provide an interrupt signal directly to a bus master.

Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 Power Supply or equivalent.

Expansion Capabilities
When the iSBC 544 board is used as a single board
communications controller, memory and 1/0 capacity may be expanded and additional functions added
using Intel MULTIBUSTM compatible expansion
boards. In this mode, no other bus masters may be
configured in the system. Memory may be expanded
to a 65K byte capacity by adding user specified combinations of RAM boards, EPROM boards, or combi. nation boards. Input/output capacity may be increased by adding digital 1/0 and analog 1/0 expan-

12-28

infef

iSBC® 544 COMMUNICATIONS CONTROLLER

sion boards. Furthermore, multiple iSBC 544 boards
may be included in an expanded system using one
iSBC 544 board as a single board communications
computer and additional controllers as intelligent
slaves.

vides a linker, object code locater, and library manager. A unique in-circuit emulator (lCE-85) option
provides the capability of developing and debugging
software directly on the iSBC 544 board.

SPECIFICATIONS

System Programming
In the system programming environment, the
iSBC 544 board appears as an additional RAM
memory module when used as an intelligent slave.
The master CPU communicates with the iSBC 544
board as if it were just an extension of system memory. Because the iSBC 544 board is treated as memory by the system, the user is able to program into it
a command structure which will allow the iSBC 544
board to control its own I/O and memory operation.
To enhance the programming .of the iSBC 544
board, the user has been given some specific tools.
The tools are: 1) the flag interrupt, 2) an on-board
RAM memory area that is accessible to both an offboard CPU and the on-board 8085A through which a
communications path can exist, and 3) access to the
bus interrupt line.
Flag Interrupt - The Flag Interrupt is generated
anytime a write command is performed by an offboard CPU to the base address of the iSBC 544
board's RAM. This interrupt provides a means for
the ma,ster CPU to notify the iSBC 544 board that it
wishes to establish a communications sequence. In
systems with more than one intelligent slave, the
flag interrupt provides a unique interrupt to each
slave outside the normal eight MULTIBUS interrupt
line~ (INTO/ -INT7 I).
On-Board RAM - The on-board 16K byte RAM
area that is accessible to both an off-board CPU and
the on-board 808SA can be located on any 4K
boundary in the system. The selected base address
of the iSBC 544 RAM will cause an interrupt when
written into by an off-board CPU.
Bus Access - The third tool to improve system
operation as an intelligent slave is access to the
MULTIBUS interrupt ,lines. The iSBC 544 board can
both respond to interrupt signals from an off-board
CPU, and generate an interrupt to the off-board CPU
via the MULTIBUS.

System Development Capability
The development cycle of iSBC 544 board based
products may be significantly reduced using the Intellec series microcomputer development systems.
The Intellec resident macroassembler, text editor,
and system monitor greatly simplify the design, development and debug of iSBC 544 system software.
An optional ISIS-II diskette operating system pro-

Serial Communications Characteristics
Synchronous -

5-8 bit characters; automatic
sync insertion; parity.

Asynchronous -

5-8 bit characters; break character generation; 1, 1%, or 2
stop bits; false start bit detection; break character detection.

Baud Rates
Frequency (KHz)(1)
Baud Rate (Hz)(2)
(Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

+16

+64

9600
4800
2400
1200
600
300

2400
1200
600
300
150
75
110

NOTES:
1. Frequency selected by I/O writes of appropriate 16.bit
frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of pos- '
sible software programmable rates available. Any frequency from 18.75 Hz to 614.4 KHz may be generated utilizing
on-board crystal oscillator and 16·bit Programmable Inter·
val Timer (used here as a frequency divider).

808SA CPU
Word Size -

8, 16 or 24 bits/instruction; 8 bits of
'data

Cycle Time -

1.45/ f-ts ± 0.01 % for fastest executable instruction; i.e., four clock cycles.

Clock Rate -

2.76 MHz ± 0.1 %

System Access Time
Dual port memory -

740 ns

NOTE:
Assumes no refresh contention.

12-29

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Memory Capacity

Interrupts

On-Board ROM/PROM installed ROM or EPROM

4K, or 8K bytes of user

On-Board Static RAM - 256 bytes on 8155
On-Board Dynamic RAM (on-board access) 16K bytes. Integrity maintained during power failure
with user-furnished batteries (optional)
On-Board Dynamic RAM (MULTIBUS access) 4K, 8K, or 16K bytes available to bus by swtich'selection

Memory Addressing

Address for 8259A Registers (Hex notation,110
, address space)
E6
E6
E7
E6
E7
E6

Interrupt request register
In-service register
Mask register
Command register
Block address register
Status (polling register)

NOTE:
Several registers have the same physical address:
Sequence of access ,and one data bit of the control
word determines which register will respond.

On-Board ROM/PROM - O-OFFF (using 2716
EPROMsor masked ROMs); 0-1FFF (using 2732A
EPROMs)

Interrupt levels routed to the 8085 CPU automatically vector the processor to unique memory locations:

On-Board Static RAM -

24 TRAP
3C RST 7.5
34 RST 6.5
2C RST 5.5

256 bytes: 7FOO-7FFF

On-Board Dynamic RAM (on-board access) 16K bytes: 8000-BFFF.
On-Board Dynamic RAM (MULTIBUS® access) any 4K inCrement OOOOO-FFOOO which is switch and
jumper selectable. 4K, 8K or 16K bytes can be made
available to the bus by switch selection.

I/O Capacity
Serial - 4 programmable channels using four
8251A USARTs
Parallel - 10 programmable lines available for Bell
801 ACU, or equivalent use. Two auxiliary jumper
selectable Signals

I/O Addressing
On-Board Programmable I/O
Port

Data

Control

USARTO
USART 1
USART2
USART3
8155 PPI

DO
02
04
06
E9 (Port A)
EA (Port B)
EB (Port C)

01
03
05
07
E8

Timers
Addresses for 8253 Registers (Hex notation, 1/0
address space)
Programmable Interrupt Timer One
08
Timer 0
BOGO
09
Timer 1
BOG1
OA
Timer 2
BOG2
DB
Control register
Programmable Interrupt Timer Two
BOG3
DC
Timer 0
BOG4
DO
Timer 1
DE
Timer 2
TINT1
OF
Control register
Address for 8155 Programmable Timer
E8
Control
Timer (LSB)
TINTO
. Timer (MSB)
EO
TINTO
Input Frequencies - Jumper selectable reference
1.2288 MHz ± 0.1 % (0.814 IJ-s period nominal) or
1.843 MHz ± 0.1 % crystal (0.542 IJ-s period, nominal)

12-30

ISBC® 544 COMMUNICATIONS CONTROLLER

Output Frequencies (at 1.2288 MHz)
Function

Single
TimerICounter

Dual Timer/Counter
(two timers cascaded)

Min

Max

Min

Max

Real-Time Interrupt Interval

1.63 p.s

53.3 p.s

3.26 p.s

58.25 min

Rate Generator (frequency)

18.75 Hz

614.4 KHz

0.00029 Hz

307.2 KHz

Interfaces

Connectors

Serial 1/0 - EIA Standard RS232C signals provided and supported:
Carrier Detect
Clear to Send
Data Set Ready
Data Terminal Ready
Request to Send
Receive Clock

Receiver Data
Ring Indicator
Secondary Receive Data'
Secondary Transmit Data •
Transmit Clock
Transmit Data
DTE Transmit clock
, Optional if parallel 110 port is not used as Automatic Calling Unit.

Centers
(In.)

Mating
Connectors

Bus

0.156

Viking
2KH43/9AMK12

Parallel I/O

0.1

3M 3415-000 or
AMP 88083-1

Serial I/O

0.1

3M 3462-000 or
AMP 88373-5

Memory protect

Parallel 1/0 - Four inputs and eight outputs (includes two jumper selectable auxiliary outputs). All
signals compatible with EIA Standard RS232C. Directly compatible with Bell Model 801 Automatic
Calling Unit, or equivalent.
MULTIBUS -

Pins
(qty)

Interface

Compatible with iSBC MULTIBUS.

On-Board Addressing

Bus Drivers

All communications to the parallel and serial I/O
ports, to the timers, and to the interrupt controller,
are via read and write commands from the on-board
808SA CPU.

Auxiliary Power

Function

Characteristic

Sink
Current (mA)

Data
Address
Commands

Tri-state
Tri-state
Tri-state

50
15
32

NOTE:

Used as a master in the Single board communications
computer mode.

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Physical Characteristics
Width:

30.48 cm (12.00 inches)

Depth:

17.15 cm (6.75 inches)

Thickness:
Weight:

1.27 cm (0.50 inch)

12-31

3.97 gm (14 ounces)

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Electrical Characteristics
DC Power Requirements
Current Requirements
Configuration
With 4K EPROM
(using 2716)

Vee

Icc

Without EPROM

+5V ±5%
(max)
3.4A max

VDD

±12V ±5%
(max)

100

350 mA max

VBB

-5V(3) ±5%
(max)

IBB

5mAmax

VAA

-12V ±5%
(max)

1M = 200 mA max

3.3Amax

350 rnA max

5mAmax

200mAmax

RAM only(1)

390mAmax

176 mA max

5mAmax

RAM(2) refresh
only

390mAmax

20 mA max

5mAmax

NOTES:
1. For opera1ional RAM only, for AUX power supply rating.
2. For RAM refresh only. Used for battery backup requirements. No RAM accessed.
3. VBB Is normally derived on-board from VAA, eliminating the need for a VBB supply. If it is desired to supply VBB from the
bus, the current requirement is as shown.

Environmental Characteristics
Operating Temperature: ODC to 55DC (32DF to 131 DF)
Relative Humidity: To 90% without condensation

Reference Manual

ORDERING INFORMATION

502160 - iSBC 544 Intelligent Communications
Controller Board Hardware Reference Manual (NOT
SUPPLIED)

Part Number

Description

iSBC 544

Intelligent Communications Controller

12-32

iSBC® 561
SOEMI (Serial OEM Interface)
CONTROLLER BOARD
Dedicated I/O Controller Provides a
• Direct
Connection of MULTIBUS®-

•
•
•

aased Systems to an IBM 9370 or .4361
Mainframe Host or to any IBM System/
370 via an IBM 3174 Subsystem Control
Unit via IBM's SOEMI (Serial OEM
Interface) Protocol
Physical Interface Is via IBM 3270 Coax
with a Maximum Distance of 1.5 km
Maximum Transmission Rate of 2.36
Megabits/Second
Dual·I/O Processors Manage Both
SOEMI and MULTIBUS® Interfaces

Includes a SMC-to-BNC Cable
• Assembly
to Attach into the IBM 3270
Information Display System
Diagnostic Capability
• On-Board
Provides Operational Status of Board'
Function and Link with the Host
Supported by a Complete Family of
• Single Board Computers, Memory,
Digital and Analog I/O, Peripheral and
Graphics Controllers' Packaging and
Software

The Intel iSBC 561 SOEMI (Serial OEM Interface) Controller Board is a. member of Intel's family of single
board computers, memory, I/O, peripheral and graphics controller boards. It is a dedicated intelligent I/O
controller on a MULTIBUS form-factor printed circuit card. The board allows OEMs of MULTIBUS-based
systems a direct, standard link to an IBM 9370 Information System, to an IBM System 4361, or to any IBM
System/370 attached to an IBM 3174 Subsystem Control Unit via the SOEMI (Serial OEM Interface). The
iSBC 561 Controller also provides IBMSystem/370 users access to the broad range of applications supported
by hundreds of MULTIBUS vendors.
The SOEMI interface is comprised of an IBM System/370 programming interface and an IBM 3270 coax
interface. It is a flexible, high speed, point-to-point serial interface offered as a feature on the IBM 9370 and
4361 processor families and on the 3174 Subsystem Control Unit. The iSBC 561S0EMI Controller Board
contains two processors and provides the necessary intelligence for conversion, control functions, and buffer
management between the IBM mainframe and the MULTIBUS system. This board allows an IBM user to
distribute control and information to MULTIBUS compatible systems fora variety of applications including
factory automation, data acquisition, measurement, control, robotics, process control, commu·nications, local
area networking, medical instrumentation, and laboratory automation.

290114-1

'IBM is a trademark of International Business Machine Corp.

12-33

October 1987
Order Number: 280114-002

inter

iSBC® 561 BOARD

SOEMI INTERFACE OVERVIEW
The Serial OEM Interface (SOEMI) is a new means
of connecting Original Equipment Manufacturer
(OEM) MULTIBUS-based systems and subsystems
to an IBM System/370 mainframe. Previously, the
only low-cost way to attach non-IBM equipment into
the IBM mainframe environment was to use 3270
emulation software and hardware adaptors. This
type of interface is low-speed (approx. 19.6K bitsl
sec.) and not very flexible as to. the type and format
of data that can be transferred. The 3270 emulators
must mimic the device formats of the displays and
printers that are typically attached on this interface;
stripping ,out command characters, carriage return
andl line feed characters, etc. The SOEMI interface
is available on; the IBM 9370, the IBM 4361, and the
3174 Subsystem Control Unit model 1L. The SOEMI
Protocol is much faster and more flexible, in that any
type of raw data or formatted data may be sent
across the connecting coax cable.
The SOEMI attachment into the MULTIBUS system
architecture, Via the iSBC 561 SOEMI Controller
Board, extends the attachment capabilities of the
IBM 9370, 4361 and 3174 to a variety of systems,
boards, and I/O devices provided by other manufacturers. Figure 1 is an example of the variety achievable on Intel's MULTIBUS (IEEE 796) system architecture.
The SOEMlinterface utilizes the System/370 Programming Interface on the .IBM 9370, 4361 and
3174 to create the protocols and formats required by
a given application for connection to and communication with virtually any type of OEM device.

The System/370 Programming Interface provides
the standard System/370 I/O instructions for exchanging data ' between the host and the
M~LTIBUS-based system. System/370 applications
see MULTIBUS system memory as one or more entities called "spaces." The System/370 host system
program writes to and reads from these spaces. The
user can define the number of spaces or the layout
of fields in the SOEMI interface at his discretion and
as required by, the application arid the MULTIBUS
system configuration.
.The 3270 coax interface provides the physical connection between the OEM MULTIBUS system and
the IBM host. The coax cable (type RG62AU) can
operate over a distance of 1.5 kilometers at a maximum transfer rate of 2.3587 MbitS/second. The distance of 1.5 kilometers can be increased toa maximum of 3 kilometers by installing an IBM 3299 Terminal Multiplexer (repeater) between the IBM 9370,
4361 or 3174 and the MULTIBUS system. The protocol at the coax interface includes a polling mechanism, a set of Write and Read ,commands, and requires a buffer with an address register at the 'OEM
controller end.
The connection to the IBM 4361 is made via the IBM
3270 Information Display System's Display/Printer
Adapter (DPA) and/or Work Station Adapter (WSA)
coax ports. The DPA can drive up to sixteen 3270/
SOEMI coax ports, and is the. standard configuration. The WSA is an optional add-on to thEllBM 4361
that incre!lses the total number coax ports supported to 40. The connection to the IBM 9370 is made
via the Workstation Subsystem Controller featur~,
and a workstation adapter which can connect up to

IBM 4381

DISPLAY PRINTER ADAPTER
OR WORK STATION ADAPT

lalll370
WORKSTATION SUBSYSTEII
CONTROLLER

8086

188.211.011:.

IRIIX· OPERATING
, SYSTEM
XENIX'

·XENIX is a trademark of MICROSOFT Corporation

290114-2

Figure '1. IBM 4361-to-MULTIBUS@ Atblchment Capability ~IOCk Diagram
12-:34

intJ

iSBC® 561 BOARD

6 SOEMI ports. This can be increased to 32 ports
using optional terminal multiplexers. The connection
to the IBM 3174 model 1L is made via IBM dual-purpose connectors (OPC) which can connect up to 4
SOEMI ports. This can be increased to 32 ports using terminal multiplexer adapters. A typical configuration can support an aggregate data rate of approximately 45K Bytes/second (approx. 360K bits/second).

bus ownership, generate bus clocks, respond to and
generate interrupts, etc. With the iSBC 561 controller connected to the mainframe, all MULTIBUS system resources are available to the IBM host program/controller. From the IBM side, the mainframe
is capable of accessing the entire 16 MBytes of
MULTIBUS system memory, 64K Bytes of 110
space, and all on-board resources of the iSBC 561
board. Other intelligent MULTIBUS boards access
iSBC 561 controller services through ,normal interrupt mechanisms.

OPERATING ENVIRONMENT·
The iSBC board functions as a slave to the host
mainframe,
reacting , and
executing
under
System/370 program control as as mainframe resource. In addition, it has a full multimaster MULTIBUS interlace that allows the board to arbitrate for

Using the SOEMI interlace in a relatively low-level
application may simply require the user to write System/370 application control programs that reside in
the IBM mainframe. A more elaborate implementation would also involve application programs that reside in the MULTIBUS system under its "native" op-

r~-----------~~--------~

I
I
I

I
I
I FRONT.END

I
I
I

1....,;_, ____ _

__ I~:-.J

I SECTION

I
I

--..L--l
I
I
I
I
I
I
I
I
_-.1
MULtIBUS~ I SYSTEM BUS

290114-3

Figure 2. iSBC® 561 SOEMI (Serial OEM Interface) Controller Board Functional Block Diagram
12-35

inter

ISBC@ 561 BOARD

erating environment (i.e., iRMX or XENIX operating
systems) and an end-to-end protocol that ties both
sets of application programs together.

ARCHITECTURE
The iSBC 561 board is functionally partitioned into
three major sections: the front-end section, the common section, and the back-end section (see Figure
2).

Front-End Processor Section:
IBM Host Interface
The front-end section of the iSBC 561 Controller
board interfaces with the.lBM mainframe via the IBM
3270 Information Display System, and consists of an
8X305 Signetics microcontroller, the 8X305 instruction memory,and the coaxial interface. The 8X305
executes the coax commands and places the structured field's instructions in shared memory buffers
for subsequent execution by the back~end processor. The front~end instruction memory consists of
three 2K x 8-bit PROMs which provide the instruction code for the 8X305 processor and the information needed to generate the various control signals
required by the 8X305 to elicit system functions. The
information contained in each PROM is not modifiable by the user. The coaxial interface is based on a
DP8340 transmitter component that converts 8-bit
parallel data received from the front~end processor
to a 12-bit serial stream, and a DP8341 receiver
component, that converts a 12-bit serial stream of
data from the mainframe to parallel data with separated command and parity bits.

Common Section:
.Shared Memory Buffer
The common section of the iSBC 561 board consists·
of two B-bit, bi-directional message registers and a
.16K x 8-bit static RAM shared buffer. This shared
memory buffer between the front-end processor and
the back-end processor is the resource for transferring information and control messages between the
.IBM host and the MULTIBUS systE!m.

ing on the direction of the transfer and type of operation or task to be performed. The information is
stored in the shared buffer as a set(s) of structured
fields. The back-end processor transfers this information by performing 8- or 16-bit data transfers to or
from the MULTIBUS system bus, the shared buffer,
and the local memory.
The control program for this high-speed, back-end
processor is resident in two 'local ROM sites. The
processor also has access to 16K bytes of static
RAM for local data storage.
The back-end section interfaces to other MULTIBUS
boards through two bus controllers, a bus arbiter,
and the address, data, and command buffers for access over the 24 address lines and 16 data lines of
the MULTIBUS system bus:

OPERATION FLOW
The commands and information passed along the
coax by the IBM host to the iSBC 561 controller represent what is known as a "structured field." The
iSBC 561 front-end processor strips out the 12-bit
protocol header deposits the remaining structured
field(s)in the shared memory buffer, and notifies the
back-end processor. The back-end processor then
processes these structured fields in order to access
the proper MULTIBUS memory space and 1/0 ports.
It then deposits the information or task in the space
and notifies the MULTIBUS subsystem master that a
transfer has occurred and is awaiting service.
When requiring service, the MULTIBUS system ap~
plication sends an interruptto the iSBC 561 board.
The board then issues an attention to the mainframe. At this pOint, the mainframe is under no obligation or time constraint to servi.ce the interrupt, and
its response is application dependent.
The mainframe issues commands to service the interrupt. The information concerned with the interrupt
is then passed through the shared memory and serialized by the iSBC 561 board before being sent to
the mainframe. The exact communications protocol
used for this end-to-end transfer is defined by the
user application programs running in both operating
environments.

Back-End Processor Section:
MULTIBUS® Interface

Interface Connector/Cable Assembly

The back-end section of the board provides an intelligent interface to the MULTIBUS system bus, and
consists of the 8086-2 microprocessor, local memory, bus interface circuitry, and memory-mapped logic. The 8086 processor is capable of either retrieving
information· the 8X305 placed in the shared buffer,
or placing information in the shared buffer, depend-

The cable assembly used to connect the iSBC 561
.SOEMI Controller Board to the IBM mainframe or
3174 control unit cable assembly consists of RG180
type cable having an SMC connector on one end
(which mates to the iSBC 561 board right angle SMC
connector) and a BNC connector on the other end
(which mates to the IBM cable assembly connector).

.. -

12-36

ISBC® 561 BOARD

S~ECIFICATIONS

Cable Characteristics
Impedance:

Operational Characteristics
Back-end processor-Intel 8086-2/5 MHz
- 20-bit address path; 8/16 bit
data path
Front-end processor- Signetics 8X305/8 MHz
- 16-bit instruction path; 8-bit
data path
Serial Transfer Rate- 2.3587 Mbits/second (max.
bit rate)
- 360K bits/second (approx.
aggregate throughput)
Serial Transfer Rate- Binary dipulse (with 12-bit
serial stream)
Memory Capacity - All iSBC 561 controller board
memory is available to onboard firmware only.
Common memory - 16K Bytes of Shared Buffer
memory (SRAM @ 0 wait
state access)
8086-2 memory
8X305 memory

- 16K Bytes of EPROM;
- 16K Bytes of SRAM
- 4K Bytes of Instruction memory (EPROM)
- 2K Bytes of Control memory
(EPROM)

Physical Characteristics
Width:
Height:
Depth:
Weight:

30.48 cm (12.00 in)
17.15 cm (6.75 in)
1.78 cm (0;70 in)
510 gm (18 oz)

coax connector-50 ohms (nominal)
external cable (user furnished).
95 ohms (nominal)
Capacitance: 35 pF1ft
Propagation: 1.6 ns/ft

Environmental Characteristics
Operating Temperature: 0° to 55°C at 200 LFM air
velocity
Operating Humidity: 10 to 85% non~condensing
(0° to 55°C)
Non-Operating Temperature: -40°C to 75°C
Shock: 30G for a duration of 11 ms with % sinewave
shape.
Vibration: 0 to 55 Hz with 0.0 to 0.010 inches peak
to peak excursion.

Reference Manuals
147048-001- iSBC 561 SOEMI (Serial OEM Interface) Controller Board Hardware Reference Manual (NOT SUPPLIED)
Reference manual may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.
GA33-1585-0 (File No. S370-03-IBM Serial OEM
Interface (SOEMI) Reference Manual
(NOT SUPPLIED)
I:\eference manual may be ordered from IBM Advanced Technical Systems; Dept. 3291, 7030-16;
Schoenaicherstr. 220; 7030 Boeblingen. Federal
Republic of Germany.

Electrical Characteristics
DC Power Requirements:
Voltage-+5V
Current (Max)-6.28A
Current (Typ)-5.46A
Power Dissipation (Max)-35.5VA

ORDERING INFORMATION
Part Number Description
iSBC 561

SOEMI (Serial OEM Interface) Controller board

12-37

inter

iSBXTM 351
SERIAL 1/0 MULTIMODULETM BOARD

Bus Compatible I/O Expansion
• ISBXTM
Programmable Synchronous/
• Asynchronous Communications

•
•

Channel with RS232C or RS449/422
Interface
Software Programm~ble Baud Rate
Generator
Two Programmable 16-Blt BCD or
Binary Timer/Event Counters

Jumper Selectable Interrupt
• Four
Request Sources

•

Accessed as I/O Port Locations
Low Power Requirements

• Single + 5V when Configured for
• RS449/422 Interface
iSBX Bus On-Board Expansion
• Eliminates
MULTIBUS@ System Bus
Latency and ,Increases System
Throughput

T~e

Intel iSBX 351 Serial 110 MULTIMODULE board is a member of Intel's new line of iSBX bus compatible
MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host
board offering incremental on-board 110 expansion. The iSBX 351 module provides one RS232C or RS449/
422 programmable synchronous/asynchronous communications channel with software selectable baud rates.
Two general purpose programrilable16-bit BCD or binary timers/ event counters are available to the host
board to generate accurate time intervals under software control. The iSBX board is closely coupled to the
host board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS
, system traff,ic for other system resources. In addition, incremental power dissipation is minimal requiring only
3.0 watts (assumes RS232C interface).

, 280236-1

12-38

September 1988
Order Number: 280238-001

intJ

ISBXTM 351

FUNCTIONAL DESCRIPTION

Installation

Communications Interface
The iSBX 351 module uses the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) providing one programmable communications channel. The USART can be programmed
by the system software to individually select the desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (i.e., synchronous or asynchronous), data format, control character format, parity,
and baud rate are all under program control. The
8251A provides full duplex, double buffered transmit
and receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The command lines, serial data lines, and Signal
ground lines are brought out to a double edge connector configurable for either an RS232C or RS449/
422 interface (see Figure 3). In addition, the iSBX
351 module is jumper configurable for either pointto-point or multidrop network connection.

The iSBX 351 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nylon hardware to insure the mechanical security of the assembly (see Figures 1 and 2).

16-Bit Interval Timers
The iSBX 351 module uses an Intel 8253 Programmable Interval Timer (PIT) providing 3 fully programmable and independent BCD and binary 16-bit interval timers. One timer is available to the system designer to generate baud rates for the USART under
software control. Routing for the outputs from the
other two counters is jumper selectable to the host
board. In utilizing the iSBX 351 module, the systems
designer simply configures, via software, each timer
independently to meet system requirements. Whenever a given baud rate or time delay is needed, software commands the programmable timers to select
the desired function. The functions of the timers are
shown in Table 1. The contents of each counter may
be read at any time during system operation.

Interrupt Re«:luest Lines.
Interrupt requests may originate from four sources.
Two interrupt requests can be automatically generated by the USART when a character is ready to be
transferred to the host board (i.e., receive buffer is
full) or a character has been transmitted (i.e., transmit buffer is empty). In addition, two jumper selectable requests can be generated by the programmable timers.

12-39

Table 1. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is
reached, an interrupt request
is generated. This function is
useful for generation of realtime clocks.

Programmable
One-Shot

Output goes low upon receipt
of an external trigger edge
and returns high when
terminal count is reached.
This function is retriggerable.

Rate Generator

Divide by N counter. The
output will go low for one
input clock cycle, and the
period from one low going
pulse to the next is N times
the input clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
Triggered Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered Strobe

Output goes low for one clock
period N counts after riSing
edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occurring
after the counting "window"
has been enabled or an
interrupt may be generated
after N events occur in the
system.

iSBXTM 351

UlliR 110
CONNECTOR -_~:".;:;;r'

INTEL IIIX 351

MULnMODULE
BOARD

BOARD

~
.Y'''' ~:=:.

.Yv·'·~V=:::

INTEL IIBJC
MULnMODULE
CONNECTOR

280236-2

Figure 1. Installation of ISBC@ 351 Module on a Host Board

.00

MAX

~r- -LL-~
__

____-L_____
SO_C_KE_T____

~~
__

iSBX 351 MUL TIMODULE BOARD

1.13
MAX
iSBX
CONNECTOR
(MALE)

____
r

CONNECTOR
__
i_s_Bx____L_____L___----s-o-C-KE-T-------L----"71MIN
(FEMALE)

280236-3

Figure 2. Mounting Clearances (Inches)

12-40

ISBXTM 351

RS232C CABLING

RS4491422 CABLING

CONNECTOR PIN 1

280236-4

Figure 3. Cable Construction and Installation for RS232C and RS449/422 Interface

SPECIFICATIONS
1/0 Addressing
1/0 Address for

1/0 Address for

an 8-81t Host

a 16-81t Host

Chip Select

Function

XO,X2,X4
orX6

YO,Y4,Y8
orYC

8251A
USART

Write: Data
Read: Data

X1,X3,X5
orX7

Y2, Y6, YA
orYE

MCSOI
Activated (True)

Write: Mode or Command
Read: Status

X80rXC

ZO or Z8

8253 PIT

Write: Counter 0
Load: Count (N)
Read: Counter 0

X90rXD

Z20rZA

MSC11Activated
(True)

Write: Counter 1
Load: Count N
Read: Counter 1

XAorXE

Z40rZC

Write: Counter 2
Load: Count (N)
Read: Counter 2

XB orXF

Z6 orZE

Write: Control
Read: None

NOTE:
X = The iSBX base address that activates MCSO & MSC1 for an 8·bit host.
Y = The iSBX base address that activates MCSO for a 16·bit host.
Z = The iSBX base address that activates MCS1 for a 16·bit host.
The first digit, X, Y or Z, is always a variable, since it will depend on the type of host microcomputer used. Refer to the
Hardware Reference Manual for your host microcomputer to determine the first digit of the 1/0 base address.
The first digit of each port 110 address is listed as "X" since it will change depending on the type of host iSBC microcomput·
er used. Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit of the 110
address.

12-41

inter

ISBXTM 351

Word Size

Serial Communications

Oata-8 bits

Synchronous-5-8-bit characters; internal character synchronization; automatic sync insertion; even.
odd or no parity generation/detection.

Access Time

Asynchronous-5-8-bit characters; break character
generation and detection; 1. 1%. or 2 stop bits; false
start bit detection; even. odd or no parity generation/detection.

Read~250 ns max
Write--300 ns max

NOTE:
Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

Interval Timer and Baud Rate
Generator
Input Frequency (selectable):
1.23 MHz
153.6 kHz

± 0.1 % (0.813 J-Ls period nominal)
±0.1 % (6.5 ,...S period nominal)

Sample Baud Rate
8253 PIT(1)
Frequency (kHZ,
Software Selectable)
307.2
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

8251 USART Baud Rate (Hz)(2)
Asynchronous
+16
19200
9600
4800
2400
1200
600
300
150
110

Synchronous
~

38400
19200
9600
4800
2400
1760

+64
4800
2400
1200
600
300
150
75
~

NOTES:
1. Frequency selected by I/O writes of appropriate 16-bit frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software-programmable rates available. Any frequency from
18.75 Hz to 614.4 kHz may be generated utilizing on-board crystal oscillator and 16-bit Programmable Interval Timer (used
here as frequency divider).

Output Frequency
Rate Generator
(Frequency)

Single Timer(1)
Single Timer(2)

Real-Time Interrupt
(Interval)

Min

Max

Min

Max

18.75 Hz

614.4 kHz

1.63 1ls

53.3 ms

2.34 Hz

76.8 kHz

13.0 Ils

426.7ms

Dual Timer(3) (Counters 0 and 1 in Series)

0.000286 Hz

307.2 kHz

3.26 1ls

58.25 min

Dual Timen4) (Counters 0 and 1 in Series)

0.0000358 Hz

38.4 kHz

. 26.0 Ils

7.77 hrs

NOTES:
1. Assuming 1.23 MHz clock input.
2. Assuming 153.6 kHz clock input.

3. Assuming Counter 0 has 1.23 MHz clock input.
4. Assuming Counter 0 has 153.6 kHz clock input.

12-42

inter

ISBXTM 351

EIA Standard Rs449/422 signals provided and supported.

Interrupts
Interrupt requests may originate from the UsART (2)
or the programmable timer (2).

Clear to Send (CS)
Data Mode (OM)
Terminal Ready (TR)
Request to Send (Rs)
Receive Timing (RT)
Receive Data (RD)
Terminal Timing (TT)
Send Data (SO)

Interfaces
isBX Bus-all signals TTTL compatible.
serial-configurable of EIA Standards Rs232C or
Rs449/422

Physical Characteristics

EIA Standard Rs232C signals provided and supported.

Width: 7.24 cm (2.85 inches)
Length: 9.40 cm (3.70 inches)

Clear to Send (CTs)
Data Set Ready (DsR)
Data Terminal Ready (DTR)
Request to Send (RTs)
Receive Clock (RXC)
Receive Data (RXD)
Transmit Clock (DTE TXC)
Transmit Data (TXD)

Height": 2.04 cm (0.80 inches)
isBX 351 Board
2.86 em (1.13 inches)
isBX 351 Board and Host Board
Weight: 51 grams (1.79 ounces)
·(see Figure 2)

Serial Interface Connectors
Configuration
Rs232C
Rs232C
Rs449
Rs449

Mode(2)

MULTIMODULETM
Edge Connector

Cable

Connector(8)

DTE
DCE
DTE
DCE

26-pin(5), 3M-3462-0001
26-pin(5), 3M-3462-0001
40-pin(6), 3M-3464-0001
40-pin(6), 3M-3464-0001

3M(3)-3349/25
3M(3)-3349/25
3M(4)-3349/37
3M(4)-3349/37

25-pin(7),3M-3482-1000
25-pin(7),3M-3483-1000
37-pin(1),3M-3502-1000
37-pin(1),3M-3503-1000

NOTES:
1.
2.
3.
4.
5.
6.
7.
8.

Cable housing 3M-3485-4000 may be used with the connector.
DTE-Data Terminal mode (male connector), DCE-Data Set mode (female connector).
Cable is tapered at one end to fit the 3M-3462 connector.
.
Cable is tapered to fit 3M-3464 connector.
Pin 26 of the edge connector is not cOnnected to the flat cable.
Pins 37, 39, and 40 of the edge connector are not connected to the flat cable.
May be used with cable housing 3M-3485-1000..
Connectors compatible with those. listed may also be used.

Electrical Characteristics

Reference Manual
9803190-01- isBX 351 Serial 1/0 MULTIMODULE

DC Power Requirements
Mode
Rs232C
Rs449/422

Manual (NOT ~UPPLlED)

Voltage

Amps
(Max)

+5V ±0.25V
+12V ±0.6V
-12V ±0.6V
+5V ±0.25V

460mA
30mA,
30mA
530mA

Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Ave., Santa
Clara, California, 95051.

ORDERING INFORMATION
Part Number Description

Environmental Characteristics
Temperature: 0·C-55·C, free moving air across the
base board and MULTIMODULE
board.
.

sBX 351

12-43

Serial 1/0 MULTIMODULE Board

inter

iSBXTM 354 DUAL CHANNEL SERIAL 1/0
MULTIMODULETM BOARD

RS232C or RS422A/449
• Two
Programmable Synchronous/

•
•

Asynchronous Communications
Channels
Programmable Baud Rate Generation
for Each Channel
Full Duplex Operation

iSBXTM Bus Compatible I/O Expansion
• Supports
HDLC/SDLC, NRZ, NRZI or
• FM Encoding/Decoding
Interrupt Options ·for Each
• Three
Channel
• Low Power Requirements

The Intel iSBX 354 Serial I/O MULTIMODULE board is a member of Intel's line of iSBX compatible MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host board
offering incremental on-board I/O expansion. Utilizing Intel's 82530 Serial Communications Controller component, the iSBX 354 module provides two RS232C or RS422A/449 programmable synchronous/asynchronous
communications channels. The 82530 component provides two independent full duplex serial channels, on
chip crystal oscillator, baud-rate generator and digital phase locked loop capability for each channel. The iSBX
board connects to the host board through the iSBX bus. This offers maximum on-board performance and frees
the MULTIBUS® System bus for use by other system resources.

280045-1

12-44

September 1887
Order Number: 280045-008

infef

iSBXTM 354 MODULE

FUNCTIONAL DESCRIPTION
Communications Interface
The iSBX 354 module uses the Intel 82530 Serial
Communications Controller (SCC) component providing two independent full duplex serial channels.
The 82530 is a multi-protocol data communications
peripheral designed to interface high speed communications lines using Asynchronous, Byte-Synchronous and Bit-Synchronous protocols to Intel's microprocessor based board and system level products.
The mode of operation (Le. asynchronous or synchronous), data format, control character format,
and baud-rate generation are all under program control. The 82530 SCC component can generate and
check CRC codes in any Synchronous mode and
can be programmed to check data integrity in various modes. The command lines, serial data lines,
and signal ground lines are brought out to a double
edge connector.

The iSBX 354 module provides a low cost means to
add two serial channels to iSBC@ boards with 8 or
16 bit MULTIMODULE interfaces. In the factory default configuration, the iSBX 354 module will support
two RS232C interfaces. With user supplied drivers
and termination resistors, the iSBX 354 module can
be reconfigured to support RS422A1449 communication interfaces with support on Channel A only for
multidrop control from the base board. Both channels can be configured as DTE or DCE with RS232C
interfaces.

Interrupt Request Line
The 82530 SCC component provides one interrupt
to the MINTRO signal of the iSBX interface. There
are six sources of interrupts in the SCC component
(Transmit, Receive and External/Status interrupts in
both channels). Each type of interrupt is enabled under program control with Channel A having higher
priority than Channel B, and with Receive, Transmit

280045-2

Figure 1. Installation of 2 ISBXTM 354 MULTIMODULETM Boards on an ISBC® Board

IMU'UUIC""

BOARD

'12" THREADED NYLON SPACER - - -

280045-3

Figure 2. Mounting Technique
12-45

inter

iSBXTM 354 MODULE

and External/Status interrupts prioritized in that order within each channel.

the iSBX 354 MULTIMODULE board on a Host
Board. Figures 3 and 4 provide cabling diagrams.

Installation

Programming Considerations

The iSBX 354 module plugs directly into the female
iSBX connector on the host board. The module is
then secured .at one additional point with nylon hardware to insure the mechanical security of the assembly. Figures 1 and 2 demonstrate the installation of

The Intel 82530 see component contains several
registers that must be programmed to initialize and
control the two channels. Intel's iSBX 354 Module
Hardware Reference Manual (Order #146531-001)
describes these registers in detail.

RS232C DB-25 CONNECTORS

PIN 1

40 CONDUCTOR FLAT
RIBBON CABLE

ISBXTU 354 MODULE
COMPONENT SIDE

,40 PIN MALE
CONNECTOR

280045-4

Figure 3. RS232C Cable Construction
RS422A/449 DB-37 CONNECTORS
FEMALE
PIN 1
(START AT 5TH
NOTCH FROM END) _
3 CONDUCTORS
'PIN 1
(START AT 1ST NOTCH FROM END)
(START AT 6TH NOTCH FROM END)
2 CONDUCTORS
15 CONDUCTORS
280045-5

Figure 4. RS422A1449 Cable Construction

12-46

inter

ISBXTM 354 MODULE

SPECIFICATIONS

Signals Provided

Word Size
Data-8 bits

Clock Frequency
4.9152 MHz

Serial Communications
Synchronous-Internal or external character synchronization on one or two synchronous characters
Asynchronous-5-8 bits and 1, 1Yz or 2 stop bits
per character; programmable clock factor; break detection and generation; parity, overrun, and framing
error detection
Sample Baud Rate:
Synchronous X1 Clock
Baud Rate

82530 Count Value
(Decimal)

64000
48000
19200
9600
4800
2400
1800
1200
300

36
49
126
254
510
1022
1363
2046
8190

RS232CDTE

RS232CDCE

-Transmit Data
-Receive Data
-Request to Send
-Clear to Send
-Data Set Ready
-Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock
-Data Terminal Ready
-Ring Indicator

-Transmit Data
-Receive Data
-Clear to Send
-Data Set Ready
-Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock .
-Ring Indicator

RS422A/449
-Send Data
-Receive Timing
-Receive Data
-Terminal Timing
-Receive Common

1/0 Port Addresses
Port Address
8·Blt

Read Status Channel B
Write Command Channel B

Read Data Channel B
Write Data Channel B

Read Status Channel A
Write Command Channel A

Read Data Channel A
Write Data Channel A

Read Disable RS422A/449 Buffer
Write Enable RS422A1449 Buffer

Asynchronous X16 Clock
Baud Rate

82530 Count Value
(Decimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Function

16·Blt

NOTES:
1. The "X" and "Y" values depend on the address of the
iSBX interface as viewed by the base board.
2. "X" corresponds with Activation of the MCSO/interface
signal; "Y" corresponds with Activation of the, MCS1/interface Signal.

Power Requirements
INTERFACES
ISBXTM Bus: Meets the iSBX Specification, Compliance Level: 08 F

+5Vat 0.5A
+12V at 50 mA
-12V at 50 mA

Physical Characteristics
Serial: Meets the EIA RS232C standard on Channels A and B. Meets the EIA RS422A1449 standard
on Channels A and B, Multi-drop capability on Channel A only.

Width: 2.85 inches
. Length: 3.70 inches
Height: 0.8 inches
Weight: 85 grams

12-47

inter

'ISBXTM 354 MODULE

ENVIRONMENTAL
CHARACTERISTICS·

REFERENCE MANUAL

Temperature: O·C to 55·C operating at 200 linear
feet per minute across baseboard and
MULTIMODULE board
Humidity: To 90%, without condensation

146531·001-iSBX 354 Channel Serial 1/0 Board
Hardware Reference Manual
Reference manuals may be ordered from any Intel
sales representative, distributor office, .or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

ORDERING INFORMATION
Part Number Description
iSBX 354

Dual Channel 1/0 MULTIMODULE .

12-48

FASTPATHTM 9750B
Conbol Unit

System/370 Channel
Connectivity Platform

FEATURES
~ Connects a System/370 or
compatible multiplexer channel to
the MULTIBUS® architecture
~ Operates as a multidevice control
unit on a block multiplexer channel
~ Supports three megabytes per
second data streaming through the
block multiplexer channel .
~ Implements dynamic speed
matching buffer for efficient
channel util ization
~ Supports up to 6 IEEE 796
Multibus compatible application
adapter boards
~ Implements a remote maintenance facility
~ Provides standard control unit
personalities .
~ Facilitates development of custom
control unit personalities
~ Designed as a completely
integrated system controller

Available in a single or dual
controller configuration
~ Available as system modules
designed to fit into a standard 19"
rack mount
~ Worldwide service, support
and training

DESCRIPTION
The 9750B control unit is an open
standardized connectivity platform
that allows connections of Multibusbased application modules with an
IBM" System/370 or compatible
mainframe. Its hardware and software
subsystems connect to the System/370
block multiplexer channel and the
IEEE-796 Multibus interface.
The hardware and software interface is a front-end processor that
performs the System/370 block multiplexer protocol management functions
and presents the 9750B to the main-

frame and its application software as
a standard control unit. A choice of
control unit personalities is provided
with the 9750B. Custom personalities.
are easily developed and incorporated
into the 9750B control unit. Multibus
compatible application adapters are
integrated into the 9750B connectivity
platform and are addressed by the
mainframe through standard subchannel addressing methods.
The 9750B maximizes throughput
with its modular design implementing
a speed matching buffering scheme
supporting offset and'data streaming
protocols at the full three megabytes
per second rate.
With this flexible connectivity platform, System/370 mainframes can
connect to local area networks, wide
area networks, hosts or specialized
peripherals. The 9750B connectivity
platform brings the open architecture

Block Multiplexer Channel

Sy.18ml37O
or
Compatible
FASTPATH 9l5OB

Hosts

~Intel

Corporation. 1987

Networks

Peripherals

. ORDER NUMBER: 270359·01

12-49

of Multibus to the System/370.

MOOULAR DESIGN
The single controller 9750B consists of a logic module made up of a
channel adapter. a control processor
and adapter board connections.
Up to two controllers can be configured into a single integrated rackmount chassis.
The Channel Adapter is the interface between the Multibus and the
System/370 compatible block multiplexer channels. Supporting up to
256 subchannel addresses which are
mapped to the integrated adapter
boards. the channel adapter is
dynamically configurable for multiple
concurrent device attachments
through a single channel connection.
The Control Processor performs
such functions as sending status.
controlling data transfer between the
channel adapter and the adapter
boards. handling resets and managing on-line/off-line transitions.
Adapter Boards are selected from

the set of board products that are
electronically compatible with the
IEEE 796 Multibus specification. Up
to six adapter boards can be integrated into a single 9750B controller.
Adapter boards are used to move data
from the channel adapter out to the
external application environment.
Adapter boards can implement local
area network protocols or perform
specialized high-speed device-todevice data transfer. Multiple similar
and multiple diverse applications
can be supported simultaneously in
a single 9750B controller chassis.

PERSONALITIES
The 9750B emulates standard
System/370 mainframe control unit
personalities. The mainframe operating environment is configured to
recognize and address the 9750B as a
standard control unit. Custom personalities can be created for the 9750B.
BSAM. When the mainframe is
configured to address the 9750B as
an "undefined device" (a valid device

typel. the Basic Sequential Access
Method (BSAMI is used for data
transfer between the host and the
adapter boards via the standard System/370 block multiplexer channel.
CETI. When the mainframe is configured to address the 9750B as a
3088 channel-to-channel device. the
Continuously Executing Transfer Interface (CETI) protocol is used to transfer
data to and from the adapter boards
acting as communication ports. This
allows communication with local
area networks or other host-based
applications. This interface provides
the maximum possible throughput
between the System/370 and the
application by minimizing the number of I/O interrupts required to
exchange data.

DIAGNOSTICS
The 9750B supports a continuously
resident host addressablediagnostic
emulation mode as well as a remotely
accessible diagnostic service port for
maintenance and problem diagnosis.

SPECIFICATIONS
Single Controller
Dual Controller
Voltage:
110/US.: 230/Europe
110/US.: 230/Europe
Frequency: 60 Hz/US.: 50-60 Hz/Europe
60 Hz/U.S.: 50-60 Hz/Europe
Operating Environment: Temperature: 15-35° Centigrade
15-35° Centigrade
Relative
Humidity:
70-80% non-condensing
70-80% non-condensing
Altitude:
10.000 feet maximum
10.000 feet maximum
Channel:
System/370 Bus and Tag
Connectors:
System/370 Bus and Tag
Dimensions:
Size:
15.75" x 22.25" x 19.00"
19.25" x 22.25" x 19.00"
Weight:
4071bs.
4561bs.
Maximum Number of
Application Adapters:
12
6
Interfaces:
Channel:
FIPS 60 and System/370 Compatible Block Multiplexer Channel
Adapter
Boards:
IEEE 796 and Multibus Compatible
Control Unit
Personalities:
Undefined Device (BSAM Accessl
3088 Device (CETI Accessl
Agencies:
UL. CSA. VDE and FCC
Power Requirements:

12-50

intel'

Communications Services

VPM 188 ASYNC/BISYNC
COMMUNICATION
SUBSYSTEM

IBMt

HOST
MAINFRAME

Virtual Protocol Machine delivers
asynchronous and bisynchronous lines and
protocols for Intel XENIX' systems and
networks
Mainframe link for bost data, application,
and report access provided by IBM protocol
emulation of HASp, 2780/3780 RJE and
3270 bisync protocols
Async communications support for terminal
multiplexing, serial printers, async modems
dnd serial system-to-system links
Single hybrid subsystem for very cost effective
and flexible mUltiple service communication
support
Full menu-driven installation, administration
and user interface for ease of use

• VPM 188 ASYNC/BISYNC
COMMUNICATION SERVICES

• FLEXIBLE MULTILINE CONTROL
AND CONFIGURATION

The VPM 188 Async/Bisync Communication Subsystem delivers a wide variety of communication services.
IBM mainframe access is provided via emulation of
IBM bisync network protocols and devices:
- 3271 Model 2 Cluster Controller, 3277/78 Displays, and 3287 Printers for interactive host access
- 2780/3780 Remote Job Entry (RJE) Workstation
for batch host access
- Multileaving HASP RJE Workstation for batch host
access
Comprehensive asynchronous communication support is provided, including:
- Async terminal multiplexing either directly attached or remotely connected via dial-up async
modems
Serial printer control
System-to-system link support through serial async
line using UUCP; either directly attached or
remotely connected via async modem

The subsystem controls 8, 10 or 12 communication
lines in a wide set of user selected configurations. It
allows dynamic selection of line types at install and
boot time; the number of bisync lines and protocols
and the number of async lines can be configured for
specific application requirements. Both interactive
and batch mainframe access is supported via emulation
of IBM's most popular network and device protocols.

• MENU-DRNEN INTERFACE FOR
INTEGRATION AND EASE OF USE
The VPM subsystem's flexibility and power is delivered
to users and administrators through a comprehensive
menu system. The menus lead users and administrators
through installation, generation, administration, and
use of the subsystem in a nonconfrontive, easy to use
manner. Rapid productivity gains results.

'INTEL CORPORATION. 1'1117
• XEN[X [S A REGISTERED TRADEMARK OF MICRoson CORPORATION
tlBM IS A REGISTERED TRADEMARK OF INHRNATlONAl H(IS/NESS MACHlNf·S

JANUARY.I'IM7
ORJ)I:R NIIMHI:R: ;!7U:!lfI·4IU[

12-51

• ADVANCED SUBSYSTEM FEATIJRES.

• A SINGLE WORKSTATION FOR ALL
PROCESSING AND COMMUNICATION NEEDS

Support for simultaneous operation of multiple mixed
line types and bisync protocol emulations is enabled
using VPM's dynamic line configuration and protocol
downloading features.
OpenNET'" compatible network operation allows
bisync emulation services and async communication
services to be accessed by remote XENIX and DOS
users across openNET for cost-effective gatewayoperation. May require OpenNET Virtual Terminal.
Screen and print data can be moved to any system or
network file for .subsequent processing by standard
XENIX and/or DOS applications. Addition of custom
applications can enable IBM compatible distributed
DP.

TECHNICAL SPECIFICATIONS

With Intel's powerful VPM communication subsystem,
users no longer require multiple workstations for their
various tasks. Local department processing, personal
computing, mainframe application processing and
reporting and inter-user communication can all be
accomplished from a single PC or terminal.

• THE VIRTIJAL PROTOCOL MACHINE STANDARD
.VPM 188 implements AT&T's specification for a Virtual Protocol Machine for UNIX' systems. Intel's version for XENIX Systems goes beyond the VPM standard
with hybrid protocol services.
"REGISTERED TRADEMARK OF AT&T

•

3270 Bisync Emulation - 3271 Model 2 Cluster Control Unit, 3277/78 Display, 3287 Printer
HASP Emulation- Multileaving HASP RJE Workstations
2780/3780 RJE Emulation - 2780/3780 RJE Workstation Emulation
9600 bps full and half-duplex line support

ORDERING INFORMATION
VPM188DK

HASP 188DK

RBTEl88DK

3270BSC 188DK

SXM18848
SXM354

The base Virtual Protocol Machine for 188/48 and 188/56 controllers in Intel XENIX systems. Controls 8, 10 or
12 RS232 lines to be async and/or bisync. All async support included. Packageincludes software and documentation. Prerequisite is XENIX system with iBASE.
Multileaving HASP RJE workstation emulator. Supports both transparent and non-transparent mode HASP
protocols. Package includes HASP emulation software, installation instructions, user guide and administrator
guide. Prereq\1isite is VPM188DK
2780/3780 RJE workstation emulator for Remote Batch Terminal Emulation (RBTE) across bisync lines/networks. Package includes RBTE emulation software, installation instructions, user guide and administrator guide.
Prerequisite is VPM 188DK
3270 bisync emulator for interactive IBM host access. Emulates a 3271 Model 2 Cluster Control Unit an!! up to
seven devices: 3277/78 Model 2 Displays and one 3287 Model 2 Printer. Compatible with OpenNET for
cross· net gateway oriented service. Package includes all emulation software, installation instructions, 3277/78
function key templates, user guide and administrator guide. Prerequisite is VPMl88DK
Eight line communication system extension module hardware. Used when no 188/48 ()r 188/56 exists in
system already. Includes all necessary hardware, cabling and documentation.
Additional two line communication system extension module hardware. Used to add 2 async lines to 188 based
subsystem via daughter board. Includes all necessary hardware, cabling and documentation. Prerequisite is SBC
or SXM 188/48.

12-52

intel

Communicatiolls Serflices

3270 SNA
COMMUNICATION
SUBSYSTEM

mMt
HOST

MAINFRAME

~
~
~

~
OpenNET

3278
DISPlAY
EMUlATOR

3270 SNA/SDLC emulator for Intel XENlX·
systems and networks'
Mainframe data and application access
SNA gateway for OpenNET'M LAN users
3274 cluster controller (PU.T2), 3278 display
(LU.T2) and 3287 printer (LU.T2) emulation
Complete menu driven interface and
administration delivers ease of use
72 nodes and 16 simultaneous
sessions supported

REMOTE INTEL SYSTEM

• 3270 SNA COMMUNICATION
SERVICES

• OpenNET-SNA CONTROLLER AND
DEVICE EMUlATION GATEWAY

The 3270 Communication Subsystem allows multiple
XENIX system users and IBM PC compatibles on an
OpenNET network to operate on IBM SNA networks.
The sUbsystem installs in· a single non-dedicated
XENIX system and runs SNA emulations for system
users and OpenNET users. It provides emulation of a
3274 Type 2 Cluster Controller, 3278 Model 2 Displays and 3287 Model 2 Printers. Up to 72 XENIX-NET
nodes are supported from a single gateway with 16
simultaneous Logical Unit sessions.

The 3270 SNA Communication Subsystem can be distributed across an OpenNET network for optimal gateway services. One network node contains the actual
SNA communication processor for 3274 Cluster Controller emulation while other nodes have copies of the
device emulators. The dispersed device emulators all
access the one gateway node for mainframe SNA communication. Up to 16 users can establish and use SNA
sessions simultaneously.

• SNA COMMUNICATION ENVIRONMENT
This subsystem communicates with the host over dialup, leased, point-to-point, and multidrop lines, coexisting with IBM equipment. Line speeds up to 9600 bps
are supported. The subsystem communicates with a
variety of IBM hosts (370, 303X, 308X, 43XX), communication front ends (3705,3725), access methods
(VI'AM, TCAM) and applications (CICS, CMS,
DSPRINT, ISPF, TSO/SPF). No change is required to
the host software for connection and operation of the
Intel 3270 SNA Subsystem .

• A SINGLE WORKSTATION FOR ALL
PROCESSING AND COMMUNICATION NEEDS
With Intel's 3270 SNA Subsystem, users will no longer
require multiple workstations for their various tasks. A
single terminal or PC can be used to access local
applications and data as well as access mainframe data,
applications and reports. Intel's SNA emulator is
optimized for very cost effective department automation.

• INnL CORPORATION, 1986

°XENIX IS A REGISTERED TRADEMARK OF MICROSOfT CORPORATION
tmM IS A REGISl"fRED TRADEMARK OF INTERNATIONAL BUSINESS MACHINES

DECEMBER,.986
ORDER NUMBER: 27Ol1~

12-53

intel
• ADVANCED SUBSYSTEM FEAnJRES

• HIGH PERFORMANCE MULTI-PROCESSOR
SUBSYSTEM ARCHITECTURE

Session hold allows a user to temporarily exit or suspend an SNA session to perform other tasks, while
maintaining the host connection, and return to the
same connection later.
Multiple gateways can exist on a single OpenNET network in those cases where greater than 16 concurrent
sessions are required.
Screen and print capture features allow users to easily
log screen data from the current session into any file on
the network, and spool printer output to any file. Users
can process the captured data files further using standard. DOS and XENIX applications.
Printer sharing enables the "local copy" device to be
specified as any network printer attached to a node
with 3287 Printer Emulation.
Complete menu-driven user and administration interface reduces installation and maintenance time and
enhances user productivity due to low confrontation.
Interactive configuration and terminal definition utilities are included for flexibility in configuring the subsystem for target environments.
For coexistence with Intel's other advanced communication subsystem, VPM 188 Async/Bisync Communication Subsystem, assures that a combination of SNA,
Bisync and Async lines can be configured and used.

The functions of the 3270 SNA Communications Subsystem are optimally distributed across the system bus.
The system's central processor oftloads the majority of
communication tasks to an advanced communication
processor which handles most of the emulation. Printer and display emulation, and configuration and operation administration are done by the central CPU while
3274 SNA Cluster Controller emulation, session control and SOLC are implemented in the communication
processor. The m:t result is higher system performance.

ICONTROLLER EMUlATION!
I

SESSION CONTROL

SDLe

I
I

TERMINALS &. PRINTERS

• A COMPLETE,. INTEGRATED SNA
COMMUNICATION SOLtmON
The 3270 SNA Communication Subsystem is a fully
integrated hardware, firmware and software solution
which is ready to install and operate in an Intel XENIX
system. Complete installation instructions, administrator's guide and user's guide for both XENIX only and
Intel's XENiX enhanced with iBASE are included.

TECHNICAL SPECIFICATIONS
3270 Base Oatastream (3270 OSC)
SNA Character String (SCS)
1920 Character Device Buffers
SNA Communication Protocols
SOLC Link Protocols
9600 bps full and half-duplex

SNA PUType 2
SNA LU Types 1, 2 and 3
Requires synchronous modem and system
to modem cabling in addition to leased or
dial-up communication line.

ORDERING INFORMATION
3274SNA88

Complete 3270 SNA Communication Subsystem including: iSBC 88/45-based communication controller (double high) with 256K memory and SOLC firmware, 3274 Cluster
Controller emulator firmware for single system or OpenNET network SNA gateway
operation, 3270 printer support software, 3278 display emulator software, 3287 printer
emulator software and complete documentation.

12-54

MULTIBUS® II Serial
Communication Boards

inter
•
•

•
•
•

iSBC® 186/410 MULTIBUS® II
SERIAL COMMUNICATIONS COMPUTER

•
•

Six Serial Communication Channels on
a Single MULTIBUS® " Board,
Expandable to 10 Channels via iSBXTM
Bus Connectors
High Integration 8 MHz 80186
Microprocessor
82258 Advanced DMA Controlle~
Provides 4 Independent High
Performance DMA Channels

MULTIBUS® " iPSB (Parallel System
Bus) Interface with Full Message
Passing Capability
Four 28-Pin JEDEC Sites, Expandable
to 8 Sites with ISBC® 341
MULTIMODULETM for a Maximum of
512K Bytes EPROM

• 110
•
•

Two iSBXTM Connectors for Low Cost
Expansion

Supports RS232C-Only on 4 Channels,
RS422A or RS232C Interface
Conflgurable on 2 Channels

MULTIBUS® " Interconnect Space for
Software Configurability and
Diagnostics

Resident Firmware to Support Host-toController Download Capability and
Built-In-Self-Test (BIST) Diagnostics

512K Bytes DRAM Provided

The iSBC 186/410 MULTIBUS II Serial Communications Computer is an intelligent 6-channel communications
processor implementing the full, high performance message passing interface of the MULTIBUS II (iPSB)
Parallel System Bus. This iSBC board combines an 8 MHz 80186 16-bit microprocessor, with six serial channels (expandable to 10 serial channels on-board via iSBX connectors), up to 512K bytes of DRAM, four 28-pin
JEOEC sites, two iSBX connectors, and an 82258 AOMA controller on a single 220 mm x 233 mm (8.7 in. x 9.2
in.) Eurocard printed circuit board. The iSBC 186/410 board supports asynchronous, byte synchronous, and
bit-synchronous (HOLC/SOLC) communications protocols on the two fuil/half duplex RS232C/RS422A channels, and asynchronous-only on the four fuil/half duplex RS232C-only channels. Acting as a terminal controller
or front-end processor, this board adds significant data communications flexibility to an OEM's MULTIBUS II
design.

280268-1

13-1

October 1987
Order Number: 280268-002

inter

ISBC® 186/410

.ter controller applications also require character and
format conversion capabilities to allow attachment
of different types of terminals.

OPERATING ENVIRONMENT
The.iSBC 186/410 MULTIBUS II Serial Communications Computer is a powerful data communications
sub-system specifically designed to operate in and
support the message-based, multi-processor system
configurations being implemented on the MULTIBUS II architecture. The board's on-board CPU, an 8
MHz 80186 microprocessor, provides significant intelligence to· off-load and distribute the serial communications functions away from one or all· of a system's processor boards.

The iSBC 186/410 MULTIBUS II.Serial Communications Computer is well suited for multi-terminal system applications (see Figure. 1). Up to 10 serial
channels can be serviced in multi-user or cluster
configurations by adding two iSBX 354 Dual Serial
Channel MULTIMODULE boards. The on-board
512K byte (expandable to 512K bytes) DRAM array
is the buffer area designed to handle incoming and
outgoing messages at data rates up to 19.2K baud
(asynch). Each serial channel can be individually
programmed for different baud rates to allow system
configurations with differing terminal types .. The onboard 80186 CPU handles the protocols and character manipulation tasks traditionally performed by a
system hosl

The iSBC 186/410 board was designed with a set of
features to address liIeveral communications appli~
cation areas: terminal/cluster controller, or front-end
processor.

Front-end Processor
A front-end processor off-loads a system's central

~ .processor of bandwidth-draining tasks such °as data
o

manipulation and text editing of characters collected
from th~ attached serial I/O devices. Since most ter-

ISBC" 186/410
BOARD

ISac" 386/100 BOARD

I
SYSTEM
PROCESSSOR

80186

FIRMWARE

. CLUSTER
CONTROLLER
MULTI BUS" IPSB BUS

280268-2

Figure 1. Terminal/Cluster Controller Application

13-2

intJ

iSBC® 186/410

o
o

•

GAN
GLOBAL AREA
NETWORK

MAINFRAME

ISBX" 354
BOARD

ISBC~

186/410
BOARD

80186

FIRMWARE

CLUSTER
CONTROLLER

280268-3

Figure 2. Front-End Processor Application

minal and serial I/O devices require flexible interfac·
es, program code is often dynamically downloaded
to the front·end processor from a system CPU.
Downloading code requires sufficient memory space
for protocol handling and program code. Flow con·
trol and interrupt handling requirements need an efficient real time operating software environment to
manage the hardware and software resources on
the board.

eas: Processor, Serial I/O, Memory, General. I/O,
iPSS bus interface, and Interconnect (see Figure 3).

Processor Subsystem
80186 PROCESSOR

The central processor unit on the iSSC 186/410
board is Intel's 16-bit 8 MHz 80186 microprocessor.
The highly integrated 80186 CPU combines several
system components onto a single chip (i.e., two Di- .
rect Memory Access lines, three Interval Timers,
Clock Generator, and Programmable Interrupt Conc
troller). The 80186 instruction set is a superset of
the 8086 and maintains object code compatibility
while adding additional instructions.

The iSSC 186/410 board features are designed to
provide a high performance solution for front·end
processor applications (see Figure 2). A large
amount of memory is provided for dynamic storage
of program code. Two serial channels (as well as
four iSSX expansion serial channels) can be config·
ured for links to mainframe systems, point·to·point
terminals, modems or multi·drop deSigns and four
serial channels are for terminal communication,
asynchronous RS232C operation only.

This high performance component manages the
board's mUlti-user, multi-protocol communications
operations. Refer to the Microsystem Components
Handbook, Order Number 230843-00X, for more detailed information on the hardware operation and requirements of the 80186 microprocessor component.

ARCHITECTURE
The iSSC 186/410 MULTISUS II Serial Communica·
tions Computer consists of six major subsystem ar·
13-3

(
~

RS422A I RS232C
SERIAL

INTERFACE

~'r

rEi
c

CD
~

AS232C1RS422A
SERIAL
INTERFACE

RS232C
SERIAL

INTERFACE

"..

.I.

"..

Cii
III
0
@)

....
C»
CJ)

.....
~

....
0
.....
cu
J,..

III

SERIAL

COMMUNICATIONS
CONTROllER
(82530)

COMMUNICATIONS

SERIAL
COMMUNICATIONS

CONTROLLER
(82530)

I»
~

CL
."

C
::J

::J

!!!.

0'
~

iii
ca

l:npL~r
OPTION

CONNECTOR

{
. .~:y

FOUR 2II-P1N SITES

82258 ADMA

DMACONTROL
(OPTION)

enID

n@)

...
......
...
o

801M
CPU
8 MHZ

512KBYTU
DRAM

I FOU~~::'N~'TES I
L

~
V

ON-BOARD 1/0 LOCAL BUS

I»

isax'·
IIULTIIIOOULE'·

CONNECTOR

C»

III

isax"
MULTIMODULE"

INTERRUPT

CONTROL
(2 - 8259...)

,'=-iJ' ...J

[II

MULTIBUS'II
iPSB

INTERFACE

8751

"CONTROLLER
(INTERCONNECTI
BlST)

r>-

ON·BOARD MEMORY LOCAL BUS

>"'
MULTIBUS' II PARALLEL SYSTEII BUS

280268-4

iSBC® 186/410

DIRECT MEMORY ACCESS (DMA) FUNCTION

SERIAL 1/0 SUBSYSTEM

The iSBC 186/410 board provides 13 channels of
DMA to support serial 110, iPSB interface, andlor
iSBX bus transfer operations. The 80186 microprocessor provides two DMA channels,. the 82258 Advanced (ADMA) controller supports three "direct"
channels of DMA, and the ADMA multiplexer circuit
uses the fourth 82258 ADMA channel providing
eight additional multiplexed DMA channels. The allocation of the board's DMA channels to on-board resources is listed in Table 1.

Six serial interfaces are provided on the iSBC
186/410 board: two interfaces support full asynchronous, byte-synchronous, and bit-synchronous
(HDLC/SDLC) communication and four interfaces
support asynchronous-only communication. The two
RS422A configurable ports can also be tri-stated to
allow multi-drop networks. The board's serial capability can be expanded to 10 channels by adding two
iSBX 354 Dual Channel Serial 1/0 MULTIMODULE
boards. Each added iSBX 354 board uses an

Table 1.ISBC® 186/410 Board DMA Channel Allocation
Channel
Count

Channel
Number

DMA Configuration
Local Bus Resource

80186
1

DMAChannel

Half-Duplex High Speed Serial Interface (SCC1 Channel A)
(-High Density 15-Pin Connector)

DMAChannel

Full-Duplex Serial Interface (SCC1 Channel A) or SBX1 DMA Request

82258ADMA
3

DMAChannel

Input DMA from MPC (Message Passing Coprocessor)

DMAChannel

Output DMA to MPC

DMAChannel

Half-Duplex High Speed Serial Interface (SCC1 Channel B)
(-High Density 15-Pin Connector) or SBX1 DMA REO

DMAChannel

Full-Duplex High Speed Serial Interface (SCC1 Channel B) or
INT2 DMA REO from DMA Multiplexer

Half-Duplex Serial Interface (SCC2 Chan. A, 9-pin conn.)

DMA Multiplexer"

DMAChannel

Full-Duplex Serial Interface (SCC2 Chan. A)

DMAChannel

Half-Duplex Serial Interface (SCC2 Chan. B, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC2 Chan. B) or SBX1 DMA Request
or Half-Duplex SCC1 Channel B.

DMAChannel

"Half-Duplex Serial Interface (SCC3 Chan. A, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC3 Chan. A) or SBX2 DMA Request

DMAChannel

Half-Duplex Serial Interface (SCC3 Chan. B, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC3 Chan. B) or INT1 SBX1 for
SBX344.

NOTE:
• ADMA Channel 3 is used to add the DMA Multiplexer.

13-5

inter

ISBC® 186/410

82530 SCC component to provide two independent
full duplex serial channels configurable. as either
RS232C or RS422A interfaces. It also supports both
asynchronous or programmable byte and bit synchronous (HDLC/SDLC) protocols. The HDLC/
SDLC interface is compatible with IBM system and
terminal equipment and with CCITT's X.25 packet
switching interface.

SDLC) modes. The increased capability at the serial
controller pOint results in off-loading a CPU of tasks
normally assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to
configure it to handle all asynchronous data formats
regardless of data size, number of start or stop bits,
or parity requirements. An on-chip baud rate generator allows independent baud rates on each channel.

Three 82530 Serial Communications Controllers
(SCCs) provide six channels of half/full serial 1/0.
Two channels are configurable as either RS232C or
RS422 on two high density 15-pin female D-shell
connectors. Four more channels are RS232C-only
using IBM standard 9-pin male D-shell cOnnectors.
All six channels directly support the Data Terminal
Equipment (DTE) configuration, with the Data Communication Equipment (DCE) pin-out supported by
changes in the cable wiring.

Memory Subsystem
The iSBC 186/410 board's on-board memory subsystem consists of a large DRAM array and a set of
universal memory sites. Access to the on-board
memory subsystem resources, as well as off-board
iPSB bus access, Is accomplished by obs.erving the
iSBC 186/410 board memory map (see Figure 4).
The mapping occurs within the 1 megabyte memory
space of the 80186 microprocessor, and is split into
three main areas: DRAM reserved, iPSB window,
and EPROM reserved. The first 0 to 512K bytes is
always reserved for local DRAM, the next 128K or

The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,
byte-synchronous, and bit-synchronous (HDLCI

IPSB
MEMORY
MAP

D··~m

MBII
MEMORY

1024K

1861410
MEMORY
MAP
ONBOARD
EPROM

768K
WINDOW MAY BE
128K OR 256K

640K

J~s..B

WINDOW
512K

MBII
WINDOW
BASE ADDRESS IS ANY MULTIPLE OF 128K
.-'- ...r....;;....~~--OR 256K (SIZE OF MULTIPLE = WINDOW SIZE)

ONBOARD
DRAM

....._ _.... 0
280268-5

Figure 4. iSBC® 186/410 Board Memory Map Diagram
13-6

ISBC® 186/410

256K bytes (or up to 76aK) is the iSPB window, and
the remaining 384K or 256K byte area is reserved
for local EPROM. The iPSB window maps a 128K or
256K byte local memory area into the 4 gigabyte
global physical address range of the MULTIBUS II
iPSB bus. This window is programmable and allows
the 80186 processor to access the complete 4 gigabyte memory space of the iPSB bus.

tervals under software control. The outputs may be
independently routed to a PIC to count external
events. The system software configures each timer
independently and can read the contents of each
counter at any time during system operation.
In a MULTIBUS II system, external interrupts (interrupts originating from off-board) are interrupt type
messages over the iPSB bus rather than signals on
individual lines. Interrupt type messages are handled
by the bus interface logic, the MPC Message Passing Coprocessor chip. The MPC component interrupts the 80186 processor via an 8259A Programmable Interrupt Controller (PIC) indicating a message has been received. This means that 1 Interrupt
line can handle interrupts from up to 255 sources.

The board's memory map also supports a 64K byte
access window for I/O space between local and
iPSB bus access. The 64K bytes of local I/O space
is mapped 1-to-1 to the iPSB bus' 64K byte I/O
space and is not programmable. The upper 32K
bytes access the iPSB bus I/O space, and the lower
32K bytes are reserved for local on-board I/O.

Two on-board 8259A PICs are used in a masterslave configuration for processing on-board interrupts. One of the interrupt lines handles the interrupt
messages received from the iPSB bus. Table 2 includes a list of devices and functions supported.

DRAM CAPABILITIES

The iSBC 186/410 board comes standard with a
512K byte DRAM memory array on-board.
EPROM MEMORY

ISBXTM BUS 1/0 EXPANSION

A total of four 28-pin JEDEC universal sites reside
on the iSBC 186/410 board. These sockets support
addition of byte-wide ROM and EPROM devices in
densities from 8K bytes (2764) to 64K bytes (27512)
per device. Two of the four sockets contain a pair of
27812 EPROM devices installed at the factory(1).
These devices contain 128K bytes of firmware providing both the Host-to-contrOller download routine
and the Built-In-Self-Test (BIST) power-up diagnostics routine. The remaining two sockets allow the
user to add either two additional devices or an iSBC
341 EPROM MULTIMODULE for a maximum of
512K bytes.
NOTE:
(1) These devices may be removed by the user for
access to the two 28-pin sites.

Two 8/16-bit iSBX bus (IEEE P959) connectors are
provided for modular, low-cost I/O expansion. The
iSBC 186/410 board supports both 8-bit and 16-bit
iSBX MULTIMODULEs through these mating, gastight pins and socket connectors. DMA is also supported to the iSBX connectors and can be configured by programming the DMA multiplexor attached
to the 82258 ADMA component. The iSBX connectors on the iSBC 186/410 board support a wide variety of standard iSBX compatible boards from Intel
and other independent vendors providing add-on
functions such as, floppy control, 1,4" tape control,
bubble memory, parallel/serial I/O, BITBUSTM interface, math, graphics, IEEE 488, and analog I/O.
Custom iSBX module designs are also supported as
per the IEEE P959 iSBX bus specification.

General I/O Subsystem

iPSB Bus Interface Subsystem

The I/O subsystem provides timers, interrupt control
and two IEEE P959 iSBX connectors for I/O expansion or customization.

This subsystem's main component is the Message
Passing Coprocessor chip. Subsystem services provided by the MPC bus interface component include
full message passing support and memory, I/O, and
interconnect access to the iPSB bus by the 80186
processor. The single~chip Message Passing Coprocessor is a highly integrated CHMOS device implementing the full message passing protocol and
performing all the arbitration, transfer, and exception
cycle protocols specified in the MULTIBUS II Architecture Specification Rev. C., Order Number
146077.

PROGRAMMABLE TIMERS AND INTERRUPT
CONTROL

The 80186 microprocessor on the iSBC 186/410
board provides three independent, fully programmable 16-bit interval timers/event counters for use by
the systems designer to generate accurate time in-

13-7

inter

iSBC® 186/410

Table 2. iSBC® 186/410 Board Interrupt Devices and Functions
Device
iPSB Bus Interface (MPC)

Function
Message-Based Interrupt Requests from the iPSB
bus via MPC Message Passing Coprocessor

Number of
Interrupts
1 interrupt for
up to 255
sources

8751 Interconnect Controller

Interconnect Space

80186 Timers & Interrupt

Timers 0 and 1 and Interrupt Acknowledge 1

82530 SCCs (3 devices)

SCC # 1 and SCC # 2 or SCC # 3 for Transmit
Buffer Empty, Receive Buffer Full, and Channel
Errors

iPSB Bus Interface (MPC)

Indicates Transmission Error on iPSB Bus

82258 ADM A

DMA Tr~nsfer Complete

IEEE P959 iSBX Bus Connectors (2)

Functions Determined by iSBX Bus
MULTIMODULE Boards

IEEE P959 iSBX Bus Connectors (2)

DMA Interrupt from iSBX (TDMA)

1
4
(2/ connector)
2

for the exclusive use of the download program. Host
CPUs must not overwrite this area with download
commands.

Interconnect Subsystem
MULTIBUS II interconnect space is a standardized
set of software configurable registers designed to
hold and control board configuration information as
well as system and board level diagnostics and testing information. Interconnect space is implemented
'with the 8751 microcontroller and the MPC silicon
resident on the iSBC 186/410 board.

Software on the host is responsible for ,accessing
the iSBC 186/410 board's firmware on disk or from
ROM visible to the host and translating ,it into linear
sequences of bytes suitable for downloading (see
Figure 5). After downloading the firmware, the host
issues a command for the loader routine on the controller to begin execution of the' downloaded software.

The read-only registers store information such as
board type, vendor I.D., firmware rev. level, etc. The
software configurable registers are used for autosoftware configurability and remote/local diagnostics and testing.

BUILT·IN SELF·TEST DIAGNOSTICS
On-board built-in self-test (BIST) diagnostics provide
a customer confidence test of the various functional
areas on the iSBC 186/410 board. The initialization
checks are performed by the 8751 microcontroller,
while the BIST package is executed by the 80186
microprocessor. On-board tests included in'the BIST
package are: DRAM, EPROM, 80186, 82530 SCCs,
and the MPC.

Firmware Capability
HOST/CONTROLLER SOFTWARE DOWNLOAD
ROUTINE
Resident in ROM on this controller is a host-to-controller software download routine to support the
downloading of communication firmware into the
iSBC 186/410 Serial Communication Computer.
This loader adheres to the MULTIBUS II Download
Protocol and responds to commahds issued by software running on a host CPU board. The host CPU
passes these commands to the loader via registers
defined in the board's interconnect space. A download function, a commence execution function, and
an examine local memory function are all provided in
the routine. Data transfers are supported by both
shared memory systems and message based systems. The top 1K of DRAM on the board is reserved

Additional activities performed include initialization
at power-up using the Initialization and Diagnostics
Executive and a program table check, a feature allowing users to add custom code in EPROM while
still maintaining full use of factory supplied BISTs.
Immediately after power-up and initialization of the
8751 microcontroller, the 80186 microprocessor begins its own initialization and on-board diagnostics.
Upon successful completion of these activities, the
Initialization and Diagnostics Executive invokes the
user-defined program table. A check is made of the
program table which then executes user-defined
custom programs.
13-8

intJ

Isec@ 186/410

HOST

FIRMWARE

CONTROLLER

ROM BASED
DOWNLOAD
ROUTINE

IPSB BUS

280268-6

Figure 5. Download Routine
The BIST package provides a valuable testing, error
reporting and recovery capability on MULTIBUS II
boards enabling the OEM to reduce manufacturing
and maintenance costs. An LED on the board's front
panel indicates the status of power-up diagnostics. It
is on when BIST diagnostics start running and is
turned off upon successful completion of the BISTs.

NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., 4 clock cycles).

Memory Capacity
Local Memory

SPECIFICATIONS
Word Size
Instruction: 8-, 16-, 24-, 32-, 40-, or 48-bits

DRAM-512K bytes on-board (64K x 4-bit devices);
8 sockets provided to support additional 256K bytes
. EPROM-Number of sockets-four 28-pin JEDEC
sites

Data: 8- or 16-bits

System Clock
CPU: 8.0 MHz

EPROM

Device Size
(Bytes)

Max. Memory
Capacity

2764
27128
27256
27512

8K
16K
32K
64K

32K bytes
64K bytes
128K bytes
256K bytes

NOTE:

Cycle Time

"EPROM Expansion to up to a maximum of 512K bytes is
achieved via attachment of the iSBC 341 EPROM (256K
byte) MULTIMODULE board.

Basic Instruction: 8.0 MHz-SOO ns

1/0 Capability
Serial-Six programmable serial ,channels using
three 82530 Serial Communications Controller components.

13-9

inter

ISBC® 186/410,

110 Expansion-Two 8/16-bit IEEE P959 iSBX connectors (DMA supported). (The board supports either two single wide or one double-wide form factor
iSBX module(s).)

Baud Rates

Timers-Three programmable timers on the 80186'
microprocessor.
Input Frequencies-Frequencies supplied by the internal 80186 16 MHz crystal; 82530 SCCs: crystal
driven at 9.8304 MHz div. by two; iSBX, Connector:
crystal driven at 9.8304 MHz.

Synchronous X1 Clock
,(Channels 0, 1)
Baud Rate

Serial Communications Characteristics
Synchronous-Internal or external character synchronization on one or two synchronous characters.
Asynchronous--5-43 data bits and 1, 1Yz or 2 stop
bits per character; programmable clock factor; break
detection and generation; parity, overrun; and framing error detection.

,
,

64000
48000
19200
9600
, 4800,
2400
1800
1200
300

82530 Count Value
(Decimal)
36
49
126
254
510
1022
1363
2046
8190

Asynchronous X16 Clock
(Channels 0-5)
82530 Count Value
(Decimal)

Baud Rate
19200
9600,
,4800
2400
1800
, 1200
300
110

6
14

62
83
126
510
1394

Serial Signals/Pin-Outs
" RS232Clnter1ace Pin Assignment for High Density 15-Pln Connectors
J2
Pin

RS-232CPln
Number

1
2
3
4
,5
6

7
8
9
10
11
12
13,
14,
15

1
2

5
6

,7
8
9
10
11
12
,13
14 '
15

' R5-232C Signal
Name
TXD
RTS
RXD
CTS
RXC
DSS
DTR
DSR
DCD
STXC
SGD
LCLPBK
RMLPBK
TSTMD
RNG

13-10

RS-232C Signal Function
Transmit Data
Request To Send
Receive Data
Clear To Send
Receive Clock
Data Signal Select
Data Terminal Ready
Data Set Ready
Carrier Detect
Transmit Clock
Signal Ground
Local Loopback
Remote Loopback
Test Mode Indicator
Not Supported

' "

iSBC® 186/410

RS422A Interface Pin Assignment for High Density 15-Pln Connectors
J1
Pin

Signal Name
On Board

RS-422A Signal
Name

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

RS42211

TR(a)
(a)
RD(a)
(a)
(a)
TR (b)
(b)
RD (b)
(b)
(b)

RS4229

RS42212
RS42290

RS-422A Signal Function
Transmit Data
Control
Receive Data
Indication
Signal Timing
Transmit Data
Control
Receive Data
Indication
Signal Timing
Signal Ground
Not Used
Not Used
Not Used
Chassis Ground

NOTE:
The iSBC" 186/40 board does not support the unused signals.

Rs232C Interface Pin Assignment for IBM® Compatible 9-Pin Connectors
Pin Number

Signal Name

Function

-In/Out

1
2
3
4
5
6
7
8
9

CD
RXD
TXD
DTR
SG
DSR
RTS
CTS
RI

Carrier Detect
Received Data
Transmit Data
Data Terminal Ready
Signal Ground
Data Set Ready
Request To Send
Clear To Send
Ring Indicator

In
In
Out
Out

Interrupt Capability

In
Out
In
Not Supported

Connectors
Interface

Potential Interrupt Sources from iPSB Bus-255 individual and 1 Broadcast

iPSB
bus (P1)

Interrupt Levels-12 vectored requests using two
8259As and 1 input to the master PIC from the slave
PIC

RS232CI 15-pin high density,
D type, right
angle female
(see note)
RS232C- 9-pin IBM compatonly
ible, D type, right
angle male (see
note)

Interfaces
iPSB Bus-Compliance Level RQAlRPA D16M32

Serial 1/Q--,2 ch. RS232C or RS422A compatible,
configured DTE only; 4 ch. RS232C IBM compatible
only, configured DTE only.

Part #
603-2-IEC-C096-F

RS422A

Interrupt Requests-All levels TIL compatible

iSBX Bus-Compliance Level D8/16 DMA

Connector
96-pin DIN, right
angle female

NOTE:
The manufacturers below provide connectors which
will mate with the connectors supplied on the iSBC
186/410 board front-panel.

13-11

inter

ISBC® 186/410

Mating Connectors, Shells and Cables
Connectors and Shells

Manufacturer

High Density D-type Plug (male)
High Density D-type Plug (male)
D-type Receptacle (female)
D-type Receptacle (female)
Connector Shells

AMP
Positronic
AMP
In-Cannon
AMP
In-Cannon
3M

Cable Description
15 Conductor-Shield,
15 Conductor-Shield,
10 Conductor-Shield,
9 Conductor-Shield,

Pins

Part No.

15
15
9
9
(For 15 or
9-pin connect.
above).

204501-1
DO-15M
205203-3
DE-9S
745171-X
DE-51218
358-2100

Manufacturer

Part No.

Alpha /
Beldon
Alpha
Beldon

Round
Round
Round
Round

5120/15
9541
5120/10
9539

NOTE:
All cable referenced is available in 100 ft. minimum lengths.

PHYSICAL DIMENSIONS

ELECTRICAL CHARACTERISTICS

The iSBC 1861410 board meets all MULTIBUS II
mechanical specifications as presented in the
MULTIBUS II Architecture Specification Handbook
(#146077, Rev. C)

The maximum power required per voltage is shown
below.

Eurocard Form Factor
Depth: 220 mm (8.7 inches)

Voltage
(volts)

Max. Current
(amps)

Max. Power
(watts)

+5V
+12V
-12V

8.22A
150mA
150mA

43.16W
1.89W
1.89W

Height: 233 mm (9.2 inches)
Front Panel Width: 20 mm (0.76 inches)

REFERENCE MANUALS

Weight: 822 gm (29 ounces)
iSBC 186/410 Serial Communications Computer User's Guide (#148941-001)

ENVIRONMENTAL
CHARACTERISTICS

Intel MULTIBUS II Architecture Specification Handbook (# 146077)
Manuals may be ordered from any Intel Sales Representative, Distribution Office, or from the Intel literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

Temperature
Inlet air at 200 LFM airflow over all boards
Non-operating: -40°C to + 75°C
Operating: 0° to + 55°C

ORDERING INFORMATION

Humidity

Part Number

Non-operating-950/0 Relative Humidity
non-condensing
Operating-900/0 Relative Humidity
condensing

+ 55°C,

Description

iSBC 186/410 MULTIBUS II Serial Communications Computer

+ 55°C, non-

13-12

MULTIBUS® II System
Development and Support
Software

inter

iSBC® CSM/001
CENTRAL SERVICES MODULE

•

ISBC@ CSM/001 Central Services
Module Integrates MULTIBUS® II
Central System Functions on a Single
Board

•
•
•
•

MULTIBUS@ II Parallel System Bus
Clock Generation for all Agents
Interfaced to the MULTIBUS II IPSB Bus
System-wide Reset Signals for Powerup, Warm Start, and Power Failurel
Recovery
System-wide Time-out Detection and
Error Generation
Slot I.D. and Arbitration I.D.
Initialization

•

MULTIBUS II Interconnect Space for
Software Configurability and
Diagnostics

•

Built-In Self Test (BIST) Power-up
Diagnostics with LED Indicator and
Error Reporting Accessible to Software
via Interconnect Space

•
•
•

General Purpose Link Interface to
Other Standard (MULTIBUS I) or
Proprietary Buses
Time-of-day Clock Support with Battery
Back-up on Board
Double-high Eurocard Standard Form
Factor, Pin and Socket DIN Connectors

The iSBC CMS/001 Central Services Module is responsible for managing the central system functions of clock
generation, power-down and reset, time-out, and assignment of I.O.s defined by the MULTIBUS II specification. The integration of these central functions in a single module improves overall board area utilization in a
multi-board system since these functions do not need to be duplicated on every board. The iSBC CMS/001
module additionally provides a time-of-day clock and the general purpose link interface to the other standard
(MULTIBUS I) or proprietary buses.

280070-1

14-1

November 1986
Order Number: 280070-002

iSBC CSM/001 MODULE

system wide time out detection and error generation.
The System Interconnect Space subsystem controls
1.0. initialization and software configurable interconnect space. The Link Board interface subsystem
provides an interface to the MULTIBUS I Link board
or links to other buses. The last two subsystems are
of the Time-of-Oay clock and the iPSB bus interface.
These areas are illustrated in Figure 2.

FUNCTIONAL DESCRIPTION

Overall
The iSBC CMS/001 Central Services Module integrates MULTIBUS II central system functions on a
single board. Each MULTIBUS II system requires
management of these central system functions as
defined in the· MULTIBUS II specification. Figure 1
illustrates a typical multiprocessing MULTIBUS II
system configuration. To perform its central system
functions, the iSBC CSM/001 Central Services Module has a fixed slot 1.0. and location in the backplane. The iSBC CSM/001 board additionally provides an interface to the MULTIBUS I Link board and
a time-of-day clock.

Architecture
The iSBC CSM/001 board is functionally partitioned
into 6 major subsystems. The Central System Wide
Control subsystem includes MULTIBUS II iPSB bus
clock generation and system wide reset signal generation. The Time-Out Control subsystem provides

CENTRALIZED SYSTEM-WIDE
CONTROL SUBSYSTEM

Parallel System Bus Clock Generation
The CSM generates the Parallel System Bus clocks.
The Bus Clock (BCLKO) 10 MHz signal and the Constant Clock (CCLKO) 20 MHz signal are supplied by
CSM to all boards interfaced to the Parallel System
Bus. These boards use the Bus Clock 10 MHz signal
for synchronization, system timing, and arbitration
functions. TheConstant Clock is an auxiliary clock.
The frequency of the Bus Clock and Constant Clock
can be halved via jumpers for diagnostic purposes.

_Taus'"

280070-2

Figure 1. Typical MULTIBUS® II System Configuration

280070-3

Figure 2; Block Diagram of iSBC® CSM/001 Board

14-2

inter

Isec CSM/001 MODULE

type, so that this information is available to the system software. The CSM software configurable interconnect space allows write operations to support
board configuration and diagnostics under software
control. The CSM also uses interconnect space for
system wide functions such as providing a time/date
record (from time-of-day clock), software access to
diagnostics and software control of the system wide
functions.

Reset Control and Power-Faill
Recovery
The CSM sends a system-level reset/initialization
signal to all boards interfaced to the Parallel System
Bus. The CSM assigns slot 1.0. and arbitration 1.0. to
these boards during this initialization process; It provides this Signal upon pressing of the reset switch,
restoration of system power or a software request
for reset received via the CSM interconnect space.
The reset switch may be jumper-configured to cause
a power-up or warm reset, with cold reset the default
configuration. The reset switch is located on the
front panel. Additionally, warm reset and cold reset
signals can be input through the P2 connector.

BUILT-IN-SELF-TEST (BIST)
DIAGNOSTICS
Self-test/diagnostics have been built into the heart
of the MULTIBUS II system. These confidence tests
and diagnostics improve reliability and reduce manufacturing and maintenance costs. LED 1 (labeled
BIST) is used to indicate the status of the Built-InSelf-Test. It is turned on when theBIST starts running and is turned off when the BIST completes successfully. In addition, all error information is recorded in interconnect space so it is accessible to soft.
ware for error reporting.

The CSM power supply interface is accomplished
via the ACLO input of the P2 connector. ACLO is an
open collector input from the power supply which
provides advance warning of imminent power fail. If
battery backup is not required, a jumper is provided
on the CSM to disable the power fail signal ACLO.

TIME-OUT SUBSYSTEM

The Built-In-Self-Tests performed by the on-board
microcontroller at power-up or at software command
are:
1. PROM Checksum Test-Verifies the contents of
the 8751 microcontroller.

The TIMOUT* (Time-Out) Signal is provided by the
CSM whenever it detects the failure of a module to
complete a handshake. This TIMOUT* Signal is received by all boards interfaced to the iPSB bus and
may be disabled via the interconnect space.

2. RAM Test-Verifies that each RAM location of·
the 8751 microcontroller m~y store O's and 1's by
complementing and verifying twice each RAM location.

INTERCONNECT SUBSYSTEM
The CSM Interconnect subsystem provides arbitration 1.0., and slot 1.0. initialization, software configurable interconnect space, and on-board diagnostics
capability.

3. Real Time Clock Chip RAM Test-Verifies that
reads and writes to the RAM locations on Real
.
Time Clock Chip are functional.
4. Real Time Clock Test-Reads and writes all RAM
locations of the RTC chip. Not run at power-up
due to destructive nature.
.

At reset, the CSM supplies each board interfaced to
iPSB bus with its slot 1.0. and its arbitration 1.0. The
slot I. D. assignment allows user or system software
to address any board by its physical position in the
backplane.

5. Arbitration/Slot 1.0. Register Test-Verifies that
arbitration and slot I.D.s can be read and written
from on-board.
6, 8751 Status Test-Verifies that input pins of the
8751 are at correct level.
..

The interconnect space has both read-only and software configurable facilities. The read-only registers
hold information such as vendor number and board

7. Clock Frequency Test-Tests accuracy of Real
Time Clock to 0.2% against bus clock.

14-3

inter

iSBC CSM/001MODULE

and provides a memory and 1/0 access window to
MULTIBUS I from the MULTIBUS II Parallel System
Bus. Only one iSBC LNK/001 board can be connected tq the iSBC CSM/001 module.

CSM LINK INTERfACE,
The CSM Link Interface and the MULTIBUS I iSBC
LNK/001 board provides a bridge ' between MULTIBUS land' MULTIBUS II systems., Hybrid systems
can be built for development or target. The CSM
Link Interface ' uses the P2 connector on the iSBC
CSNl/001 module for transferring commands' and
data from MULTIBUS II to a MULTIBUS I Link board.
The MULTIBUS I Link board (iSBC LNK/001) is purchased separately from the iSBC CSM/001 board
and includes the cable' which connects the iSBC
CSM/001 board and the MULTIBUS I Link board
(see Figure 3). ,,'

TIME-Of-DAY CLQCK SUBSYSTEM
The, Time-Of-Day Clock subsystem c:~nsists of a
clock chip, battery, and .interface ,circuitry. ,The clock
provides time keeping to 0.Q1 % accuracy of fractiOnS of seconds, seco'nds, minutes, hours,day, day
of week, month, and year. This information is accessible via the interconnect space. The battery back~
up for thecloc,k chip provides 2 years of operation.

The CSM Link Interface supports 8-ort6-bit transfers via a 16-bit addressl data path. The, iSBC
LNK/001 board resides in the MULTIBUS I system

MULTI BUS" I

SYSTEM BUS,

280070-4

,': ,

Figure 3. ISBC4!l CSM/001 Link Interface

SPECifiCATIONS

Link Cable

System Clocks

The Link cable uses a 64-conductor ribbon cable for
interconnecting the, CSM board to the Link Board.
The maXimum length for the cable is 1 inete~. '
10'MHz

BCLKO (Bus Clock)
CCLK* (Constant CI~Ck)

20 MHz.
10MHz

LCLK* (Link Clock) .

Jumper option available to divide these frequencies
in half

Interface Compliance
MULTIBUS
(#146077)

Bus

Architecture

Interface Specifications
Location
P1
P2

SpeCification

14-4

Function
iPSB Bus
Link and Remote
Services

Part #
603-2-IEC-C096F
603-2-IEC-C064-F

iSBC CSM/001 MODULE

PHYSICAL DIMENSIONS

BATTERY CHARACTERISTICS

The iSBC CSM/001 board meets all MULTIBUS II
mechanical specifications as presented in the MULTIBUS II specification (#146077).

3V nominal voltage; capacity of 160 milliamp hours
minimum.

Double-High Eurocard Form Factor:

BATTERY DIMENSIONS

Depth:
Height:
Front Panel Width:
Weight:

Outside dimension
Height

220 mm. (8.7 in.)
233 mm.(9.2 in.)
20 mm. (0.78 in.)
4820 gm. (16.5 oz.)

20 mm-23mm
1.6 mm-3.2 mm

REFERENCE MANUALS
iSBC CSM/001 Board Manual (#146706-001)

ENVIRONMENTAL REQUIREMENTS
Intel MULTIBUS II Bus Architecture Specification
(#146077)

Temperature: (inlet air) at 200 LFM airflow over
boards
Non~operating: - 40 to + 70°C
Operating:
0 to + 55°C
Humidity:
Non-operating: 95% RH @ 55°C
Operating:
90% RH @ 55°C

Manuals may be ordered from any Sales Representative, Distributor Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA
95051.

POWER REQUIREMENTS

ORDERING INFORMATION

Voltage (volts)

Current (amps)

+5
+5VBB

6A (max.)
1A (max.)

Part Number
iSBC CSM/001

14-5

Description
MULTIBUS II Central Services
Module

iSBC® LNK/001 BOARD
MULTIBUS® II TO MULTIBUS® I Link Board
•

Development Vehicle Making
MULTIBUS@ I ISBC@ Boards Accessible
to MULTIBUS@ II Board Designers

• On Board 128K Byte Dual Port DRAM
. Memory
•

16M Bytes of MULTIBUS@ I Memory
Mapped into MULTIBUS@ II Memory
Space Conflgurable from MULTIBUS@ II
Interconnect Space

•

32K Bytes of MULTIBUS@ I I/O Mapped
Into MULTIBUS@ II I/O Space
Configurable from MULTIBUS@ II
Interconnect Space

•

Conversion of MULTIBUS@ I Interrupts
to MULTIBUS@. II Interrupt Messages

•

MULTIBUS@ I Form Factor Board

•

Connects to MULTIBUS@ II Central
Services Module (lSBC CSM/001 Board)
via a 3 Foot Flat Ribbon Cable

The iSBC LNK/001 board maps MULTIBUS I memory and 1/0 space into the MULTIBUS II iPSB bus and
converts MULTIBUS I interrupts into MULTIBUS II interrupt messages. Up to 16M Bytes of MULTIBUS I
memory and up to 32K Bytes of MULTIBUS 11/0 is addressable from MULTIBUS II through the iSBC LNK/001
board. Additionally, 128K Bytes of dual port DRAM memory resides on the iSBC LNK/001 board for use by
both MULTIBUS I and MULTIBUS II systems. MULTIBUS II OEM product designers can now speed hardware
and software development efforts by using the iSBC LNK/001 board to access standard or custom MULTIBUS I products.

280135-1

14-6

October 1986
Order Number: 280135-002

inter

Isec® LNK/001

MULTIBUS I system. A MULTIBUS II agent requesting a memory transfer involving the iSBC LNK/001
board is directed through the CSM to the iSBC
LNK/001 Dual Port memory or a MULTIBUS I slave.
If the access address is within the MULTIBUS II Dual
Port window, the transaction is acknowledged by the
iSBC LNK/001 board and returned to the MULTIBUS II iPSB through the CSM. In the event the address is outside the MULTIBUS II Dual Port window,
the. transaction is directed to the MULTIBUS I system. Here the iSBC LNK/001 board enters arbitration for the MULTIBUS I system bus to complete the
requested transaction. Once the iSBC LNK/001
board is the owner of the MULTIBUS I system bus,
data is transferred to or from the iSBC LNK/001
board/Central Services Module connection. The
MULTIBUS I slave acknowledges the transfer and
the iSBC LNK/001 board passes the acknowledge
on through the Central Services Module to the MULTIBUS II iPSB.

GENERAL DESCRIPTION
The iSBC LNK/001 board makes MULTIBUS I products accessible to MULTIBUS II designers.. The
iSBC LNK/001 board resides in the MULTIBUS I
system and connects to the Central Services Module (iSBC CSM/001 board) via a 3 foot flat ribbon
cable. The ribbon cable connects the P2 connector
of the iSBC LNK/001 board to the P2 connector on
the Central Services Module. The iSBC LNK/001
board supports:
a. 128K Bytes of Dual Port DRAM,
b. 16- and 24-bit addressing into 16M Bytes of MULTIBUS I memory with 8- and 16-bit data paths,

C. 8- and 16-bit addressing into 32K Bytes of MULTIBUS 11/0 with 8- and 16-bit data paths,
d. MULTIBUS I interrupt to MULTIBUS II interrupt
message conversions of up to eight levels of non
bus-vectored interrupts via an 8259A programmable interrupt controller, and
e. initialization tests and Built-In-Self-Test (BISn using interconnected address space.

MULTIBUS II I/O operations are always directed to
the MULTIBUS I I/O slaves and consequently require arbitration for the MULTIBUS I system bus.

APPLICATIONS

INTERCONNECT MAPPING

The primary application of the iSBC LNK/001 bQard
is in the design development environment. The iSBC
LNK/001 board allows designers to start their development efforts by leveraging existing MULTIBUS I
products or to begin modular design efforts and preserve investments in custom products. In either
case, the use of leverage with existing MULTIBUS I
hardware and software allows designers to begin
their MULTIBUS II product designs.·

The function record of the iSBC LNK/001 board, a
function record within the Central Services Module
interconnect template, appears as a board within a
board (see Table 1). The actual iSBC LNK/001
board configuration is done through unique interconnect registers using the same slot ID as the Central
Services Module. The iSBC LNK/001 function rec-·
ord begins at an offset of 256 from the start of the
CSM template and the EOT (End Of Template) byte
is attached as the last function of the iSBC LNK/001
function record.
.

MEMORY AND 1/0 READIWRITE
SEQUENCE

Dual Port 128K Byte DRAM Memory

The iSBC LNK/001 board establishes a master/
slave relation between a MULTIBUS II system and a

A dynamic RAM Dual Port, resident on the iSBC
LNK/001 board, provides a 128K Byte media for

MULTIBUS' I

SYSTEM BUS

280135-2

Figure 1. Sequence Diagram
14-7

inter

ISBC@ LNK/001

MULTIBUS I and MULTIBUS II agents to pass data
efficiently. With both buses sharing the Dual Port
memory the need for the MULTIBUS II system to
continuously arbitrate for MULTIBUS I system access is eliminated. Consequently, each bus can continue operating at its respective speed when accessing the iSBCLNK/001 Dual Port memory.

dress register value. This memory block, configurable on any 64K Byte boundary within the MULTIBUS
I memory address space, is set via interconnect accesses to the iSBC LNK/001 function records from
the MULTIBUS II system (see Table 1). The first
16M Bytes of MULTIBUS II memory space can be
mapped in the 16M Bytes of MULTIBUS I memory
address space (see Figure 3).

MULTIBUS® I Memory Addressabillty

MULTIBUS@ 11/0 Addressablllty

The MULTIBUS I system views the iSBC LNK/001
Dual Port as acontiguous 128K Byte memory block
mapped into the 16M Bytes of MULTIBUS I memory
address space starting· at the Dual Port Start Ad-

Up to eight 4K Byte blocks of MULTIBUS II I/O
space can be mapped into MULTIBUS I I/O space

Table 1. Function Record Overview ISBC~ LNK/001 Board
OffSet

Description

Offset

Description

0-255

iSBC CSM/001 Header and
Function Record
Board Specific R:ecord Type
Record Length
Vendor 10, Low Byte
Vendor 10, High Byte
Link Version Number
Hardware Revision Test Number
Link General Status
Link Gerieral Control
Link BIST Support Level
Link BIST batli In
Link BIST Data Out
Link BIST Slave Status
Link BIST Master Status .
Link BIST TestiD
MBI Dual Port Start Address

271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288

MBI Dual PortEnd Address
MBII Dual Port Start Address
MBII Dual Port End Address
MBII Memory Start Address
MBII Memory End Address
I/O 4K Segment Control
MBI Interrupt Enable
. Link Interrupt 0 Destination Address
Link Interrupt 1 Destination Address
Link Interrupt 2 Destination Address
Link Interrupt 3 Destination Address
Link Interrupt 4 Destination Address
Link Interrupt 5 Destination Address
Link Interrupt 6 Destination Address
Link Interrupt 7 Destination Address
Interrupt Source Address
Link Status Register
EOT (End of Template)

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270

IIULTIBUS. II

BUS AND·

LINK

MESSAGE

DUAL
PORT

CONTROL
LOGIC

RAM

280135-3

Figure 2. Link Board Dual Port Drawing
14-8

inter

iSBC® LNK/001

which the interrupt message is being sent. Each of
the eight MULTIBUS I interrupt lines can be programmed to generate a unique MULTIBUS II destination address. These destination addresses are initialized through interconnect space by programming
the iSBC LNK/001 Interrupt Destination Address
Registers. The message source address is also configurable via interconnect space by writing to the Interrupt 0 Source Address Register with a base value.
Once the base value of source Address 0 is established, Source Address 1 through 7 are set for incrementing values by the 8751A interconnect processor. The iSBC LNK/001 board recognizes MULTIBUS II Negative Acknowledge agent errors
("NACK") and performs an automatic retry algorithm.

II
4GB

MULTIBUS~

MULTIBUS@ I
16MB!

~g~~

==::

"'1:0-7...,..-:.-1

;~;

~ ~

---_"""'~UO

MEMORY MAPPING
~,.....".-:,.,.,

64KB

,/
,/

",.-

Initialization Tests and BIST

32KB.~

",.-

Self test and diagnostics have been built into the
MULTIBUS II system. The BIST LED is used to indicate the result of the Built-In-Self-Test and turns on
when BIST starts running and turns off when it has
successfully executed. BIST test failure information
is recorded in the interconnect space and is accessible to software for error reporting.

MBII
I/O

o
I/O MAPPING

280135-4

Figure 3. MULTIBUS® I Memory
and 1/0 Mapping Diagram

PHYSICAL CHARACTERISTICS
(see Figure 3). MULTIBUS II I/O accesses must be
from 32K Byte to 64K Byte in order to be mapped
into MULTIBUS I 1/0 address space. These blocks
are specified through an interconnect access to the
"1/0 4K Segment Control" register (see Table 1).
Each bit in the register represents a 4K Byte block of
I/O addresses. When a bit (or bits) is set, the 4K
Byte block of MULTIBUS II 1/0 space represented
by that bit will be dedicated to MULTIBUS I 1/0
space.

Form Factor
The iSBC LNK/001 board is a MULTIBUS I form factor board residing in a MULTIBUS I system. Physical
dimensions are identical to all standard MULTIBUS I
boards.

Connection to MULTIBUS® II Bus
The iSBC LNK/001 board connects to the iSBC
CSM/001 board in the MULTIBUS II system via a 60
pin conductor flat ribbon cable. The physical c,onnection is made on the P2 connector of both the
iSBC LNK/001 board and the iSBC CSM/001 board.
The cable termination requirements and DC requirements for the signal drivers and receivers are detailed in the iSBC CSM/001 USERS GUIDE, Section
6.6.4. The maximum length of the cable is 3 feet.
The cable and the connectors are shipped unassembled to allow user flexibility.

Interrupt to Message Conversion
As the iSBC LNK/001 board receives non-bus vectored interrupts from the MULTIBUS I system, the
on-board 8259A programmable interrupt controller
(PIC) prioritizes the MULTIBUS I interrupts and initiates the MULTIBUS II unsolicited interrupt message
generation process. Up to 8 levels of non-bus vectoredinterrupts are supported by the iSBC LNK/001
board.
The iSBC LNK/001 board generates the MULTIBUS
II interrupt messages and is the Interrupt Source.
The iSBC LNK/001 board is assigned a Source ID
through interconnect space when the MULTIBUS II
system is powered up or when the user programs
the source ID register via interconnect space. The
Interrupt Destination is the MULTIBUS II board to

SOFTWARE SUPPORT
To take advantage of iSBC LNK/001 Dual Port architecture, existing software device drivers may require modification. Device driver changes depend on
the specific application and vary in complexity depending upon the device driver.
14-9

intJ

ISBC® LNK/001

SPECIFICATIONS

ENVIRONMENTAL REQUIREMENTS

16· and 24·bit Address Paths
8· and 16·bit Data Paths
Block transfers are not supported

Temperature: Inlet air at 200 LFM airflow over
boards
Non Operating: - 40·C to + 75·C
Operating: O·C to + 55·C
Humidity:
Non Operating: 0 to 95% RH @ 55·C
Operating: 0 to 95% RH @ 55·C

Cable Characteristics

POWER REQUIREMENTS

The cable is a 60 pin conductor flat ribbon cable with
a maximum length of 3 feet. The P2 connector to the
iSBC LNK/001 board is a 30/60 pin board edge
connector with 0.100" pin centers, KEL·AM Part
Number RF30·2853·5. The connector to the P2 DIN
connector on the iSBC CSM/001 board is 3M Part
Number 3338·000.

Voltage: + 5V
Current: 7.14 Amps

Word Size

REFERENCE MANUALS
iSBC LNK/001 Users Guide (# 148756·001)
Intel MULTIBUS II Bus Architecture Specification,
Rev C (# 146077)

Interface Specifications
Location

.Function

P1
P2

MULTIBUS IEEE 796 System Bus
Cable connection to P2 connector of
iSBC CSM/001 board

PHYSICAL DIMENSIONS
The iSBC LNK/001 board meets all MULTIBUS ·1
mechanical specifications as presented in the MULTIBUS I specification.

iSBC CSM/001 Users Manual (#146706·001)
Manuals may be ordered from any Sales Represent·
ative, Distributor Office, or from the Intel Literature
Department, 3065. Bowers Ave., Santa Clara, CA.
95051.

ORDERING INFORMATION
Part Number

Description

iSBC LKN/001

MULTIBUS II to MULTIBUS I iSBC
LNK/001 Interface Board

Depth: 17.15 cm (6.75 in.)
Height: 1,27 cm (0.50 in.)
Front Panel Width: 30.48 cm (12.00 in.)
Weight: Estimated 565 g (20 oz.)

14·10

MlJLTIBlJ~

" MODlJLES DEJlELOPMENT SlJPPORT

The MULTlBUS@ II Modules Development Platform (MOP) is a fully-integrated system for board
designers or users to develop software for and test MULTIBUS II boards_ OEM customers and
MULTIBUS II board vendors can use this system to integrate off-the-shelf or custom MULTI BUS II
boards. develop software drivers and applications and test the entire system. In addition. the
integrated system can serve as a proof-of-concept vehicle. This makes the MOP a good system for
R&D labs to evaluate unique MULTIBUS II applications. For customers using the iRMX@ 286 system
as their target operating system. applications developed on the MOP can be moved to the target
system with little or no effort.

TWO MODELS TO FIT DEJlELOPMENT TEAM SIZE
Depending on the size of the development team. two models are offered. Model I contains a single
80386-based board with 4 MB on-board RAM. an 80 MB wini: tape. floppy and an asynchronous
terminal controller with 6 ports. Model II adds another 80386 CPU board. 80 MB wini and terminal
controller for up to six more users.

FEATlJRES:
• Suitable for board developers. design labs
and systems integrators
-Intel iRMX 286 application software and
device driver development
-Board check-out
-Demo vehicle
-Proof-of-concept evaluation

• 80386-based with full message-passing
• Intel iRMX 286 Prototype Operating System
and application tools
• Compatible with Intel's iRMX 286 ReI. 2
product
• 2 models are available with one or two
80386 CPU (4 MB RAM) boards

imJ-------------------Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an inlel product No other circuit patent licenses are
implied. Information contained herein supersedes previously pub:ished specifications on these devices from Intel.
,Junt',I!lfl7
Ol'llcl' Nllmhcr: 2UUG:D·UU I

14-11

INDlfSTRY STANDARD JRMX® 286
REL. :1 PROTOTYPE AND TOOLS

OPERATING ENVIRONMENT
Temperature:
Humidity:

The MDP comes with Intel'siRMX 286 ReI. 3Prototype
operating system configured for MDP's specific set of
boards that supports a multi-user development
environment. It is based on Intel's iRMX 286 ReI. 2
product and takes advantage of the 80386 protected mode
multitasking. environment. The operating system also
implements the systems features of the MULTI BUS II
architecture: high speed message-based data transfer and
interrupts. geographic addressing and. high reliability
physical connectors.
iRMX 286 standard software development tools are
provided: ASM 286 and the' 80286 Utilities (Build. Bind).
PL/M 286 and the AEDIT editor. Intel's C. FORTRAN and
Pascal COmpilers are also available and supported under
the iRMX 286 operating system.

AC power input:
Dimensions:
Height:
Width:
Depth:
Weight:

10°C-40°C
85% non-condensing
(operating)
95 % non-condensing
(not operating)
88-132 VACor 180-264 VAC;
47-63 Hz
7.75//(19.7 em)
17.5// (445 em)
22.25" (56.5 em)
54/64Ibs.

ORDERING INFORMATION
,MBIIMDPIR
MBIlMDP2R

EXPANSION CAPABILITY FOR
ClfSTOM DESIGNS
The MDP provides both peripheral and board-level
expansion capabilities. With Model I. customers have an
additional full-height peripheral bay and up to 3
MULTIBUS II expansion slots with 16.7 A of + 5 V. Each
CPU board can also accept up to 16 MB of on-board RAM
(using two 8 MB MULTIMODULEST") without any changes
to the operating system.

SPECIFICATIONS
Hardware
8-slot MULTIBUS II chassis; 535 W power supply
iSBC 3861100 (16 MHz) with 4 MBon-board RAM and
80287 Math Coprocessor
iSBX 354 serial controller (console and auxiliary ports)
iSBC 186/224A peripheral controller
iSBC 186/410 async. terminal controller (6 users per
board)
80 NIB Winchester
320 KB floppy
60 MB streamer tape
3 terminal cables
Software
iRMX 286 ReI. 3 Prototype Operating System
Documentation
iRMX 286 Release 2.0 Operating System
ASM 286 and 80286 Utilities
PL/M 286
AEDIT
DMON and iSDM \Ionitor PROMs

-14-12

SBCMMOI
SBCMM02.
SBCMM04.
SBCMM08

iRMX MULTIBUsl1 Modules
Development Platform.
Modell.
iRMX MULTI BUS II Modules
Development Platform.
Model II.
1-.2-.4- and 8 MB memory
MULTIMODULE for the
iSBC 386/1 00 board

System Packaging and
Power Supplies

ICSTM 80
INDUSTRIAL CHASSIS KIT 635, KIT 640

•
•
•
•

•
•
•
•
•

Available with iSBC® 640 Power Supply
Accommodates from 1· to 3 ISBC®
604/614 Cardcage Assemblies for 4-12
MULTIBUS® Board Capacity
Vertical Board Orientation and Four
Fans for High Efficiency Cooling
Front Access to iSBC® Boards, Power
. Supply, and Signal Conditioning Panels

19-1nch Wide RETMA Rack Mounting or
NEMA Type Backwall Mounting
Brackets
UL and CSA Approved
Multi-Voltage Operation
Lockable Service Panel
Recessed Mounting Space for Signal
Conditioning/Wire Termination Panels

The iCS 80 Industrial Chassis provides industrially oriented mounting space for Intel single board computer
(iSBC) products, associated iSBC power supplies, and related analog and digital conditioning/termination
panels. The base unit provides a 4-slot MULTIBUS backplane (iSBC 604) with expansion space and cabling to
expand to 12 MULTIBUS backplane slots by adding additional 4-slot iSBC 614s as needed (up to two). Full
MULTIBUS compatability in the iCS 80 chassis allows configuration of multiple single board computers to
share system tasks through communication over the bus (through multi master bus arbitration built on the
multiple iSBC processors).

280240-1

15-1

October 1988
Order Number: 2802411-001

intJ

ICSTM 80 CHASSIS KIT

connectors are provided for rapid service replacement. An AC wiring barrier strip allows simple wiring
connections for integration into larger systems (see
Figure 4).

FUNCTIONAL DESCRIPTION
ICSTM 80 Kit 640
This chassis uses the higher power iSBC 640 power
supply, and is designed to power higher board count
systems. By installing one or two additional. iSBC
614 cardcages, this chassis will accommodate up to
8 or 12 MULTIBUS boards. Signal conditioning panels may attach directly in the iCS 80. .

Industrial Rack Mounting
The chaSSis mounts directly into 19-inch standard
width RETMA (Radio-Electronics-Television Manufacturers Association) customer provided rack. Alternately, mounting brackets and power cabling access
are provided for mounting directly on a backwall,
such as the. backwall panel of a NEMA-type (National Electrical Manufacturers Association), front-access-only cabinet.

Engineered for Industrial Applications
The MuLTIBUSslots are mounted vertically to improve convection cooling and the top, bottom and
sides are engineering to allow maximum air flow
over the boards. Four fans are provided to increase
air flow, allowing users to eliminate or minimize the
need for supplementary fans or air conditioning.
.
Po~er

Front Access Serviceability
To simplify serviceability, front access is provided for
all iSBC boards, the power supply, operation indicator lights, interrupt and reset buttons, and the AC
power fuse.

Supply Flexibility

The power supplies are mounted on slide in/out
mounting rails,and quick disconnect cabling and
TOP VIEW

-~I.-=- =- =- _-_-_-_- '- '-17-.4=-=- =- =- - -~- ~-.lJ
_-

;;

. . . .. ..

,~l.

-----+I.I~'
11.97

?
0

L1+--1..
~

- I...

1m •••

5.47

Ie!

FAONTVIEW

00000000 0
SIDE VIEW

280240-2

Figure 1.ICSTM 80 Chassis Dimensions
15-2

inter

ICSTM 80 CHASSIS KIT

Typical Small Configuration
• iSBC 88/40A Test and Measurement Computer
• iCS 910 Analog I/O Signal Conditioning Panel
• iCS 930 AC/OC Control Interface Panel

280240-3

280240-4

Figure 2. Small Configuration ICSTM 80 Kit

Figure 3.ICSTM 80 Kit 640 with 12 MULTIBUS®
Card Slots Mounted In NEMA Cabinet

Typical Maximum Configuration
• 16·bit 8086 processor (iSBC 86/30 w/RAM MUL·
TIMOOULE)
• 768K bytes RAM (2 • iSBC 056A)
• 128K bytes EPROM (or 16K E2PROM)
• 240 analog inputs (3 • iSBC 88/40A w/2 ea.
iSBX 311)
• 24 analog voltage outputs

OR
• 24 analog current outputs (4-20 mAl
• 72 isolated digital inputs/outputs
• 144 TTL digital inputs/outputs (2 • iSBC 519s)
(All iCS 9XX Signal Conditioning/Termination Panels
shown mounted to cabinet)

280240-5

Figure 4. Rear View ICSTM 80 Chassis Showing
Power Distribution Panel (detilched to show
terminal block), and Cabling from iCS 80 Chassis
to iCS 9XX RETMA Mounted Signal Conditioning
Panels (Top of ICS 80 Chassis)

15·3

inter

ICSTM 80 CHASSIS KIT

vertically over the area where the second or third
cardcage would mount (see Figure 2). The benefit of
this design is a completely self-contained industrial
chassis with iSBC cards, power supply, signal conditioning and field wiring terminations, all in one enclosure.

Lockable Service Panel
To assist in development, checkout and service, two
pushbuttons are provided. The RESET button pulls
low the initialize line (INIT) on the MULTIBUS backplane. The INTERRUPT button pulls low one interrupt line on the MULTIBUS backplane (lNT1). Logic
within the iCS 80 ensures that these buttons function with all versions of Intel single board computers.
From the front of the iCS 80 chassis, iNithout CRT
or other panel, an operator. or service person can
reset or interrupt on-going iCS 80 system operations
to get attention, signal an alarm, or start a self-test
operation.

SPECIFICATIONS

Capacity
Four slots for MULTIBUS compatible single comput~
ers, memory, I/O or other expansion boards

A front panel key provides three positions: OFF (AC
power off and key removable), ON. (AC power on,
pushbuttons enabled, key unremovable), and LOCK
(ACpower· on, pushbutlons disabled, key removable).
.

Expandable to 12 slots using two iSBC 614 cardcages (Order Separately)

Front Panel Controls

Three. indicator light emitting diodes record basic
chassis status. POWER ON (GREEN); RUN
(GREEN); and HALT (RED); the RESET or INTERRUPT buttons will remove the HALT state.

PUSH BUTTONS
RESET: Connected to Initialize/ on MULTIBUS
backplane

U.L. Approved

INTERRUPT: Connected to Interrupt 1/ line on
MULTIBUS backplane.

The iCS 80 chassis has received full Underwriters
Laboratory approval (F.6 # E70842) as a U.L. listed
component under the Underwriters Laboratories
Safety Standard for Process Control Equipment,
UL 1092. When installed as described in the iCS 80
Hardware Reference Manual, the iCS 80 chassis
provides adequate protection against shock, fire and
casualty hazards, and should comply with most local
and regional requirements for installation in ordinary
locations. In addition, the iCS 80 chassis was designed to comply with the UL requirements for Data
Processing Equipment, UL478. The iCS 80 has also
been approved by the Canadian Standards Association under CSA categoryC22.2 No. 142, the Canadi.an Standard for Safety for Process Control Equipment and C22.2 No. 154 for Data Processing Equipment.

PANEL INDICATOR LIGHTS (LEOs)

POWER ON (green):
MULTIBUS backplarie

+ 5V

power exits on the

RUN (green): CPU is executing an instruction. Light
goes out if CPU is in WAIT or HALT state
HALT (red): CPU has executed a HALT instruction
KEYLOCK

OFF: AC power off, key removable
ON: AC power on, push buttons enabled, key removable

Mounting Space for Signal
Conditioning/Wire Terminations

LOCK: AC power on, pushbuttons disabled, key removable

The cardcages and power supplies in the iCS 80
chassis are recessed behind the front edge of the
rack mounting ears to provide. mounting space for
the iCS 9XX series signal conditioning/termination
panels and field wiring.· For smaller systems with
only one or twoiSBC 604/614 cardcages (4 t08
slots), up.to two iCS 910, iCS 920, or iCS 930 signal
conditioning/termination panels can be mounted

Fuse: AC power (6A)

. Equipment Supplied
iCS 80 industrial chassis, three fans for cardcages,
one fan for power supply, 4-slot cardcage with MULTIBUS backplane, control panel with switches, indi-

15-4

inter

ICSTM 80 CHASSIS KIT

cators, keylock, power distribution barrier strip, AC
power fuse, line filter, 115V power cable, and logic
for interrupt and reset buttons. An installation package is also provided, including a NEMA cabinet
mounting kit, power supply extension cables, and
RETMA cabinet mounting screws, 100/120/220/
240 VAC operation.

OUTPUT POWER
Voltage

Output
Current (max)

Overvoltage
Protection

iSBC640

+12V
+5V
- -5V
-12V

Software

4.5A
30.0A
1.75A
1.75A

ISBC640

+14Vto
+ 5.SV to
-5.SV to
-14Vto

+16V
+ 6.6V
-6.6V
-16V

See the RMX/SO Real-time Multitasking Executive
specifications for industrial related applications. In
addition, system monitors for most of the Intel single
board computers are available in the INSITE (Intel's
Software Index and Technology Exchange) User's
Program Library.

Combined Line/Load Regulation: ± 1 % at ± 10%
static line change and ± 50% static load change,
measured at the output connector (± 0.2% measured at the power supply under the same conditions).

Physical Characteristics

Remote Sensing: Provided for + 5 VDC output line
regulation.

Height: 39.3cm (15.7 in.)
Width: 4S.5 cm (19.0 in.) at front panel
43.5 cm (17.4 in.) behind front panel
Depth: 30.0 cm (12.0 in.) with all protrusions
Weight: 16.S kg (37.0 Ib) without power supplies

Output Ripple and Noise: 10 mV (iSBC 640 supply)
peak-to-peak, max (DC to 500 kHz)
Output Transient Response: Less than 50 ,...sec for
± 50% load change.
Maximum Watts Dissipation (load plus losses):
500W (iSBC 640 supply)

Environmental Characteristics
(Ambient at iCS-SO air intake, bottom of chassis)
Temperature: (Ambient)

Installation
Complete instructions for installation are contained
in the iCS SO Site Planning and Installation Guide,
including RETMA and NEMA cabinet mounting, and
field signal, ground wiring and cooling suggestions.

Operating:
O°C to + 50°C (32°F to 122°F)
Non-operating: - 40°C to + S5°C
Humidity:
Up to 90% relative, noncondensing
at 40°C

warranty

Electrical Characteristics

The iCS SO Industrial Chassis is warranted to be free
from defects in. materials and workmanship under
normal use and service fora period of 90 days from
date of shipment.

The iCS SO chassis provides mounting space for the
iSBC 640 power supply. Unless otherwise stated,
electrical specifications apply to both power supplies
when installed by user in iCS SO chassis.

Reference Manuals

INPUT POWER
Frequency: 47 to 63 Hz. Voltage (Nominal)
Voltage:
(Single Phase, Jumper Selectable)
iCS SO Kit 640:100,120,220,240 VAC (±10%)

Current
(Including fans)

9800708A: iSBC 604/614 Cardcage Hardware Reference Manual (SUPPLIED)

With ISBC 640

Input Voltage

5.6Amax

103 VAX

ORDERING INFORMATION

206 VAX

Part Number

2.SA max
Power,max:

9800799A: iCS SO Industrial Chassis Hardware Reference Manual (SUPPLIED)

Description
iCS SO Kit 640 iCS SO system consisting of:
iCS SO Industrial Chassis
iSBC 640 Power Supply

5S0 watts

15-5

iSBC® 604/614
MODULAR CARDCAGE ASSEMBLIES

•
•
•

Interconnects and Houses up to Four
MULTIBUS® Boards per Cardcage
Connectors Allow Interconnection of
up to Four Cardcage Assemblies for 16
Board Systems
Strong Cardcage Structure Helps
Protect Installed Boards from Warping
and Physical Damage

•
•
•
•

Cardcage Mounting Holes· Facilitate
Interconnection of Units
Compatible with 3.S-lnch.RETMA Rack
Mount Increments
Interleaved Grounds on Backplane
Minimize Noise and Crosstalk
Up to 3 CPU Boards per System for
Multiprocessing Applications

The iSBC 604 and iSBC 614 Modular Cardcage Assemblies units provide low-cost, off-the-shelf housing for
OEM products using two or more MULTIBUS boards. Each unit inerconnectsand houses up to four boards.
The base unit, the iSBC 604 Cardcage Assembly, contains a male backplane PC edge connector and bus
signal termination circuits, plus power supply connectors. It is suitable for applications requiring a single unit, or
may be interconnected with up to three iSBC 614cardcage assemblies for a four cardcage (16 board) system.
The iSBC 614 contains both male and female backplane connectors, and may be interconnected with iSBC
604/614 units. Both units are identical, with the exception of the bus signal terminator feature. A single unit
may be packaged in a 3.5 inch RETMA rack enclosure, and two interconnected units may be packaged in a 7
inch enclosure. The units are mountable in any of three planes..
.

280205-1

15-6

September 1986
Order Number: 280205-001

inter

iSBC® 604/614 CARDCAGES

660 ....

·1

12875

I
~I

I
I

lBB OIA THAU. 3 HOLES

-t
5.500

-r
_I

'SO

-l--~I

2:0

ISBC. 614 ONLY

2750

300-'

SIDE VIEW

14.20

t
t

iSBC6140NLY

[

2500

II
35....

Isac 6040NLY
•

13 500

·1
+

3.340

GiiiiW

END VIEW

/GiiiiW

-----I..I~OIA.

X .60 DEEP

4 HOLES

280205-2

BonOMVIEW

Figure 1.ISBC® 604/614 Cardcage Assembly Dimensions

SPECIFICATIONS

Mating Power Connectors

Backplane

AMP

Bus Lines-Ali MULTIBUS system bus address,
data, and command bus lines are bussed to all four
connectors on the printed circuit backplane
Power Connectors-G for ground, + 5,
+ 12V, -12V, and -10V power supply lines

Molex
- 5,

Connector

87159-7

87023-1

Polarizing Key

87116-2

Connector

09-50-7071

08-50-0106

Polarizing Key

15-04-0219

NOTE:
1. Pins from a given vendor may only be used with connectors from the same vendor.

ISBC 604-Bus Signal terminators, backplane male
PC edge connector only, and power supply headers
iSBC 614-Backplane male and female connectors
and power supply headers

15-7

inter

ISBC® 604/614 CARDCAGES

ORDERING INFORMATION

Environmental Characteristics

Part Number Description
SSC 604
Modular Cardcage Assembly (Base
Unit)

Operating Temperature: O°C to·55°C

Reference Manual

Bus Arbitration: Serial; up to 3 CPU masters
Equipment Supplied: iSBC 604 or iSBC 614
Cardcage Schematic

9800708-iSBC 604/614 Cardcage Hardware Reference Manual (ORDER SEPARATELY)

Physical Dimensions

SBC614

Part Number Description
Modular Cardcage Assembly (Expansion Unit)

Height: 8.5 in. (21.59 cm)
Width: 14.2 in. (36.07 cm)
Depth: 3.34 in. (8.48 cm)
Weight: 35 oz. (992.23 gm)
Card Slot Spacing: 0.6 in.

15-8

intJ
•
•
•
•

iSBC® 608/618
CARDCAGES

Houses Eight MULTIBUS® ISBC®
Boards in an Aluminum Package

Enhanced Bus Noise Immunity for High
• Speed
Systems

Board-to-Board Clearance for iSBC®
MULTIMODULETM Boards on A" Slots

•
•
• ISBC®

Plug on iSBC 618 Unit for up to Sixteen
Board Systems

Board-ta-Board Clearance for ISBXTM
MULTIMODULETM Boards on Two Slots

NEMA-Type Backwa" or 19-1nch Rack
Mount Hardware Included

Para"el Priority Circuitry for up to Eight
Multlmaster ISBC® Boards

Signal Line Termination Circuitry on
608 Cardcage

Intel's iSBC 608/618 Cardcages are matched to the latest generation of iSBC/iSBX boards which mount in
the MULTIBUS system bus. These products provide several features which make them the industry's leading
price/performance cardcage product. MULTIMODULE board clearance, parallel priority circuitry, enhanced
backplane noise immunity, and precision fit card guides are a few of the distinctions which make this the
industry's better product.
The iSBC 608 Cardcage is the base unit, housing up to eight iSBC boards and their MULTIMODULE boards.
Additionally, this base unit includes mounting hardware and fan mounting bracketry. The iSBC 618 is the
expansion unit, providing eight additional iSBC board slots to the iSBC 608 Cardcage for a total of sixteen
board slots which can be NEMA-type backwall or 19-inch rack mounted. This is accomplished with the mounting hardware of the iSBC 608 Cardcage. The iSBC 618 expansion unit also includes fan mounting bracketry.

210373-1

15-9

November 1986
Order Number: 210373·001

inter

iSBC® 608/618 CARDCAGES

FUNCTIONAL DESCRIPTION

Mechanical Aspects
The iSBC 608/618 Cardcages provide housing and
a MULTIBUS system bus for up to sixteen single
board computers and their MULTIMODULE boards.
The iSBC 608 unit and iSBC 618 unit offer board-toboard clearance (0.8 inches or greater) on all eight
slots for iSBC MULTIMODULE boards. Two slots
provide clearance (1.2 inches or greater) for iSBX
MULTIMODULE boards as shown in Figure 1. Each
card cage includes precision fitted nylon cardguides
for secure board fit and accurate MULTIBUS board
pin alignment. Fan mounting bracketry is.also included with each cardcage. This bracketry allows the
mounting of several industry standard fans. The
iSBC 608 Cardcage base unit includes aluminum
mounting hardware for NEMA-type backwall mounting, or anchoring a sixteen slot iSBC 608/618 combination in a standard 19-inch rack.

connections. There are six different priority schemes
allowed, each requiring a different jumper configuration. In systems where an iSBC 618 Cardcage is attached to the base unit, the base unit will have lower
priority overall. That is, master boards in the
iSBC 608 base unit bay gain control of the
MULTIBUS lines only when no boards in the
iSBC 618 expansion unit are asserting the bus request (BREOI) signal.
Noise-minimizing ground traces are strategically interleaved between signal and address lines on these
backplanes. This provides the enhanced noise immunity and minimized signal-to-signal coupling
which is important in high speed, high board count
microcomputer systems.
The iSBC 608/618 Cardcages provide power connector lug bolts for + 5 VDC and ground. The lug
bolts, compared to other power connection methods, help transfer higher amounts of current. Other
voltages (± 12 VDC, - 5 VDC) are connected via a
mating power connector plug as shown in Figure 2.

Electrical Aspects
The iSBC 608/618 Cardcages implement a parallel
priority resolution scheme by using plug-in jumper

ISBX'· MULTIMOOULE'"
BOARD SPACING

IJl0Pc:.~~: ~
'-...(

l",,-----I-I
f

+5VDC

.0...------,

TERM::~ ;;;~~;;;;;~;;;;:;;~:~~~~~~:~~;~:~;~~~;:~~;
::

TERMINAL

;;;;;;;;;;:;.:;:::;:~ ::::;::::::;;::::::;.

........................................~~.

•••••• ,............... ••••••••••••• ••••••

••• 0 ••••••••••••••••••••••••••••••••••••

C.2_

: : : : : : : : : : : : : : : : : :i: :~ :::

I-14----7.00·-----~1
0
0

o @

......

E+:
0

ISBee MULTIMODULE'·
BOARD SPACING

210373-2

Figure 1. iSBC® 608/618 Cardcages Dimensions

15-10

inter

iSBC® 608/618 CARDCAGES

Environmental Characteristics

SPECIFICATIONS
Bus Lines
All MULTIBUS (IEEE 796) system bus address and
command lines are bussed to each of the eight
MULTIBUS connectors on the backplane. Ground
traces are interleaved among these signal lines and
bussed to the backplane edge connector for interconnection of the iSBC 608 and iSBC 618 backplane.

Operating Temperature:
Storage Temperature:
Humidity:
.
Vibration and Shock:

O°C to 55°C
-40°C to + 85°C
50% to 95% non-condensing at 25°C to 40°C.
2G max. through 50 Hz

Physical Characteristics
SLOT-TO-SLOT DIMENSIONS (See Figure 1)

Power Connectors
Ground (OV), + 5V, - 5V, + 12V, -12V power supply header stakes and power lug bolts are provided
on the iSBC 608/618 Cardcages as shown in Figure
2.

Top-J1:
J1-J2:
J8-Bottom:
All Others:

1.200
1.300
0.700
0.800

in. (to center)
in. (center to center)
in. (to center)
(center to center)

Physical Dimensions
Height:
Length:
Width:
Weight:
Shipping Weight:

8.38 in. (21.29 cm)
13.16 in. (33.43 em)
7.50 in. (19.05 cm)
3.50 Ibs (1.59 kg)
5.75 Ibs (2.61 kg)

Equipment Supplied
ISBC® 608 BASE UNIT
Two at greater than 1.2
inches; six at 0.8 inches
For expansion with iSBC
Male Backplane
618 cardeage
Connector:
Parallel Priority Circuitry: Eight slots are configurable via the use of jumper
Six
priority
stakes.
schemes allowed
Construction Materials: Aluminum card housing
Nylon card guides
Power connector header
stakes and lug bolts
Eight Slots:

210373-3

Figure 2. Power Header Stakes and Lugs

15-11

inter

iSBC® 608/618 CARDCAGES

Accessories

User-Supplied Equipment

ISBC® 618 EXPANSION UNIT
Eight-Slots:
Two at greater than 1.2
inches; six at 0.8 inches
Female Backplane
For expansion to iSBC
Connector: .
. 608 base unit
Parallel Priority Circuitry: Eight slots are configurable via the use of jumper
stakes: ' Six
priority
schemes allowed.
Construction Materials:
Aluminum card housing
Nylon card guides
Power connector header
stakes and lug bolts
Fan Mounting Hardware
Schematic

MATING POWER CONNECTORS
Vendor Part Number

3M
Ansley
Berg

3399-6026
609-2600M
65485-009

MOUNTABLE FANS
Vendor Part Number

Rotron
SU2A 1-028267
Torin
TA300-A30473-10
Pamotor 85060

15-12

intJ
•

iSBC® 640 POWER SUPPLY

± 5V and ± 12V Output Voltage

•

• Sufficient Power for 8-12 MULTIBUS®
Computer, Memory, and PerIpheral
Boards
•

Current limiting and Overvoltage
Protection on All Outputs

•

UL Listed and CSA Certified

•

"AC Low" Power Failure TTL Logic
Level Output Provided for System
Power-Down Control

DC Power Cables and Connectors Mate
Directly to iSBC 604/614 and
iSBC 608/618 Modular Cardcagel
Backplane Assemblies

•

100, 120,220, and 240V AC Operation

•

50 Hz or 60 Hz Input

The iSBC 640. Power Supply provides low cost, off-the-shelf, single chassis power generation for OEM anq
industrial system products using Intel single board computers. The iSBC 640 supply provides regulated DC
output power at + 12V, + 5V, and - 5V and -12V levels. The current capabilities of each of these output
levels has been chosen to provide power over a O°C to + 55°C temperature range for one fully loaded Intel
single board computer, plus residual capability for most combinations of up to eleven iSBC memory, liD, or
combination expansion boards. Current limiting and over-voltage protection is provided on all outputs. Access
for AC input is provided via a standard 4-pin keyed connector. DC output power levels are provided on cables
with keyed connectors directly compatible with the iSBC 604/614 and iSBC 608/618 Modular Backplanel
Cardcage assemblies. The iSBC 640 supply includes logic whose purpose is to sense system AC power failure
and generate a TTL signal for clean system power-down control.
.

280212-1

15-13

October 1986
Order Number: 280212-001

inter

ISBe@640

SPECIFICATIONS

Mating Connectors(1)

Electrical Characteristics

AC Input

Input Power
Frequency: 50 Hz ± 5%, 60 Hz ± 5%
Voltage: 100/120/220/240 VAC ±10%
Via user configured wiring options

03-09-2042 or Equivalent

Molex

02-09-2118 or Equivalent
(18 to 22 Gauge Wire) .

Housing

Current Current Limit Short Circuit

Over-

(Amps)

Range

(Amps)

voltage

(Max)

(Amps)

(Max)

Protection

+12V

4.SA

4.7-6.8

2.3

+SV

30A

31.S-4S.0

1S.0

6.2V ± O.4V

-SV

1.7SA

1.8-3.2

0.9

-6.2V ± O.4V

-12V

1.7SA

1;8-3.2

0.9

Voltage

Molex

DC Output2

Output Power
Nominal

Housing

Pins

26-03-3071

Amp

3-87025-3

Molex

08-50-0187
or
08-50-0189

Amp

87023-1

Molex

15-04-9209

Amp

87116-2

1SV ± 1V

-1SV±

Key

Combined Line/Load Regulation- ± 1% at ± 10%
static line change and ± 50% static load change,
measured at the output connector (± 0.2% measured at the· power supply under the same conditions).
Remote Sensing-Provided for
regulation.

Molex

+ 5 VDC output line

Output Ripple and Nolse-10 mV peak-to-peak·
maximum (DC to 500 KHz)
Output Transient Response-Less than· 50 /lsec
for ± 50% load change.
..
Output Transient Devlatlon-Lessthan± 10% of
initial voltage for ± 50% load change.
Power Failure Indication (AC Low}-A TIL. open
collector high signal is provided when the input voltage drops below 90% of its nominal value. DC voltages will remain within 5% of their nominal values
for 3.0 milliseconds (minimum, 7.5 ms typical) after
AC Low goes true.
The "AC Low" Signal will reset to a TIL low level
when the AC input voltage is restored and after all
output voltages are within specified regulation.

Compatible with Molex 09-66-1071 Header

NOTES
1. Pins from given vendor may only be used with connectors from the same vendor.
2. iSBG 640 DG output connectors are directly compatible
with input power connectors on iSBC 604/614 and
iSBG 608/618 Modular Gardcage/Backplane assemblies.
Four connectors are provided.

Physical Characteristics
Height: 6.66 in. max. (16.92 cm)
Width: 8.19 in. max. (20.80 cm)
Depth: 12.65 in. max. (32.12 cm)
Weight: 30 Ibs. max (13.63 kg)

Environmental Characteristics
Temperature: O·C to 55·C with 55 CFM moving air
Non-Operating: -40·C to +85·C

Equipment Supplied
iSBC 640 Power Supply with AC and DC cables with
keyed connectors.

The "AC Low" threshold is adjustable for optimum
powerdown performance at other input combinations (i.e. 100 VAC, 220 VAC, 50 Hz).

15-14

intJ

iSBC® 640

Reference Manuals
9800803- iSBC 640 Power Supply Hardware Reference Manual (order separately)
9800798- iCS 80 Systems Site Planning and Installation Manual (for installation of iSBC
640 supply into iCS 80 Industrial Chassis) (Order Separately)

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ORDERING INFORMATION
Part Number Description
SBC 640
Power Supply

15-15

iSBC® 661
SYSTEM CHASSIS
•

UL, FCC arid ,CSA Approved for Data
Processing Equipment
.

Extra-Wide Cardcage Slot Spacing for
ISBXTM MULTIMODULETM Board'
Clearance

•

230 Watt Power Supply with Power Fail
Warning

Conflgurable for Front or Rear Access
to MULTIBUS® Circuit Boards

•

Five Connector Ports for I/O Cabling

•

Operational from 47 Hz to 63 Hz,
100/120/220/240 VAC ± 10%

•

Eight-Slot MULTIBUS® Chassis with
Parallel Priority Circuitry

•
•
•

Designed for Slide Rack Mounting or
Table-Top Use

The iSBC 661 System Chassis is an advanced MULTIBUS (IEEE) 796 chassis which incorporates unique
usability and service features not found on competitive products. This chaSSis is designed or rack-mount or
table-top applications and reliably operates up to an ambient temperature of 50·C. Additionally, this sytem
chassis is certified by UL, CSA and FCC for data processing equipment.
An application requiring multiprocessing will find this eight-slot MULTIBUS chassis particularly well suited to its
needs. Parallel priority bus arbitration circuiry has been integrated into the backplane. This permits a bus
master to reside in each slot. Extra-wide inter-slot spacing on the cardcage allows the use of plug-on MULTIMODULE boards without blocking adjacent slots. For this reason, the iSBC 661 System Chassis provides the
slot-functionality of most 16-slot chassis. Standard logic recognizes a system AC power failure and generates
a TTL signal for use in powerdown control. Additionally, current limiting and over-VOltage protection are
provided at all outputs.

210866-1

15-16

October 1986
Order Number: 210866-002

inter

iSBC® 661 CHASSIS

FUNCTIONAL DESCRIPTION

under User Supplied Options. Rubber feet are included on the chassis for convenient table-top use.

Mechanical Features

The chassis is constructed of burnished aluminum
which has been coated with corrosion-resistant
chromate. It contains a system control module which
presents the front panel control switches to the user,
and holds the 1/0 cabling bulkhead to the rear. The
chassis has the unique feature of being configurable
for either front or rear access to MULTIBUS circuit
.
boards.

The iSBC 661 System Chassis houses, cools, powers, and interconnects up to eight iSBC single board
computers and their MULTIMODULE boards for the
MULTIBUS System Bus. Based on Intel's iSBC 608
Cardcage, the chassis provides 0.8 inches of board
center-to-center clearance on six slots, and 1.2
inches or more of center-to-center clearance on
two slots. This permits the users of standard MULTIMODULE boards and custom wire-wrap boards to
plug into the MULTIBUS System Bus without blocking adjacent slots. All slots provide enough clearance for iSBC MULTIMODULE boards, and two
slots can accommodate iSBX MULTIMODULE
boards.
High-technology MULTIBUS applications requiring
rack-mount, or laboratory table-top use will find the
iSBC 661 System Chassis ideal. Standard 19" slidrack mounting is possible with user-provided slides
attached to the side panels. Slide mounting holes
are provided in the chassis for the slide-rails listed

I
'0'

,------,
I
I
I

POWER SUPPLY

AREA

This is accomplished by a simple procedure involving removal of the system control module, reversing
it end-for-end, and re-securing it to the chassis. The
system chassis is shipped in a configuration such
that the MULTIBUS boards are installed from the
front.

Electrical Features
The iSBC 661 System Chassis is powered by the
iSBC 640 power supply. This is a standard Intel power supply which has been adopted by several
MULTIBUS vendors throughout the industry. It sup-

I
I
I

I
FAN

_____ -l

,------,
I
I
IL

EIGHT-SLOT

CARDCAGE

_____

I
I
-lI

FAN

I
L

To.•"

-TOP VIEW

o."~f-

T
1~r--

~~_r.ll rnD~~
~~~~3~K_OUTS

8.72~

_ _ _ _ _inIeI
__

"'1.----'.·0.' ----....,.~I To.•2.'

BACKPANEL

FRONT VIEW

r - - - - - - - -......

......

"'I·----'o'----.J-I
SIDE VIEW

210866-2

Figure 1,ISBC® 661 System Chassis Dimensions

15-17

intJ

iSBC® 661 CHASSIS

plies 230 watts of power, power fail warning, and
remote. sensing of +5 volts. Its electrical and operational parameters are listed under Specifications.
The card cage of the. iSBC 661 System Chassis implements a user-changeable parallel priority bus arbitration scheme by using plug-in jumper connections. Six different priority schemes are allowed,
each scheme fixing the priority to the eight MULTIBUS board slots. Bus contention among eight busmasters in a multiprocessing environment can be
managed using this approach.
Noise minimizing ground traces are strategically interleaved between signal and address lines on the
system bus. This provides the enhanced noise immunity and minimized signaHo-signal coupling
which is particularly important in high speed, high
board count microcomputer systems.

Electrical Parameters

Weight: 41 pounds (21 kg)
Shipping Weight (approx.): 50 pounds (25 Kg)

Equipment Supplied

(Not included: order separately)

Table 1. Output Power Levels ISBC® 661-1

+12V
+5V
-5V
-12V

Width: 16.95 inches (43.05 cm)
Height: 8.72 inches (22.2 cm)
Depth: 19.00 inches (48.3 cm)

Reference Manual

OUTPUT POWER

Voltage

Physical Characteristics

iSBC® 661-1-Eight-slot MULTIBUS system chassis
with parallel priority arbitration circuitry and 230 watt
linear power supply

SPECIFICATIONS

Output
Current
(max.)
4.5A
30.0A
1.75A
1.75A

Operational Humidity-10% to 85% relative, noncondensing
R,emote Sensing-Provided for + 5 VCD
Output Transient Response-50 fl-s or less for
±50% load change

Current
Limits'
(amps)
4.7-6.8
31.5-45.0
1.8-3.2
1.8-3.2

145340-001-iSBC 661 System Chassis Hardware
Reference Manual

Over-Voltage
Protection

User Supplied Options

15V ±1V
6.2V ±O.4V
-6.2V ±0.4V
-15V ±1V

Compatible Rack-Mount Slides-Chassis Trak, Inc.,
P. O. Box 39100, Indianapolis, IN 46239; Part No.
C300 S 122

Operational Parameters

ORDERING INFORMATION

Input AC Voltage-100/120/220/240 VAC ±10%
(User selects via external switch), 47-63 Hz
Power-Fail Indication and Hold-Up Time (triggered at
90% of VAC in)-TTL O.C. High 3 msec. (min.)
Output Ripple and Noise-1 % Peak-to-Peak output·
nominal (DC to 0.5 MHz)
Operational Temperature-O·C t050·C
Storage Temperature--40·C to 70·C

Part Number Description
SBC6611
Eight-slot MULTIBUS system chassis with parallel priority arbitration circuitry and 230 watt Linear Power
Supply

15-18

• A chassis for user installed 51A II peripherals
and MULTmUS@ single board computers .

OEM CHASSIS
MODEL 93
MODEL 94

• Model 93 - Four MULTmUS slots, three
iLJIXTM slots
• Model 94 - Five MULTIBUS slots, two
iLBX slots
• Extra wide cardcage slot spacing for iSBX
or MULTIMODULE™ clearance for two of
seven slots
• 360 watt power supply
• Designed to meet UL, CSA, FCC Class A,
IEC 435 and VDE Class A requirements for
data processing equipment

The Open Chassis

Standard Package

312 Floorstand
AUGUST 1986
ORDER NUMBER 280391>00.

15-19

Cardcage/Backplane

Package Constructi()n

Rear Panel

The cardcage accepts up to seven
MULTIBUS (IEEE 796) single board
computers and supports parallel
priority resolution for multiprocessing
applications. Two of the seven slots
have extra wide spacing to accommodate iSBX MULTIMODULE boards.
.
. . ,
The Model 93 incorporates three
iLBX bus slots on the P2 connector.
The Model 94 incorporates two iLBX
bus slots on the P2 connector.

The chassis consists of a plastic base,
a plastic top cover, a metal I/O panel
and two front filler panels. The
MULTIBUS cards are oriented
horizontally when the system is
oriented horizontally.

The rear panel of the chassis contains
a metal Input/Output panel as well as
the on/off switch, the AC power
receptacle, a fuse, a filter, and a voltage selector. The metal Input/Output
panel contains knockouts which can
support the following connector types:

There is room in the chassis for one
non-standard printed circuit board.
This space would typically house a
data separator or tap. formatter boa~d.

Peripheral Mounting
The chassis contains space for two full
height or four half height 5 1,4 "
peripheral devices. The dimensions
are:
Width: 30:0 cm (11 3/4 ")
Height: S.5 cm (3 liS ")
Depth: 22.0 cm (S 3/4 ")
This chassis provides standard mounting holes for 5 'A " devices. Filler
panels are shipped with the system to
cover any space not occupied by mass
storage devices.

User Controls

Connector Type
15 pin D sub
25 pin D sub
J7/50 pin D sub
750 BNC
36 pin D
26 GPIB

The front of the chassis contains a
reset button, an interrupt button, a
power on light, and a run light. user
installation of appropriate wiring (not
included) is required to operate these
controls.

Mounting Options

Quantity
2
21
3

Power Supply

The chassis can be mounted hrizontallyon a table top or in a 19" NEMA
rack. The chassis can be mounted
vertically in an optional floorstand.
Rack mounting holes are molded into
the chassis base and are designed for
use with rack mount slide available
from Chassis Trak.

The chassis contains a 360 watt power
supply which is user selectable for
110/220 VAC 47-63 Hertz. The wiring
harness shipped with the chassis
supplies power to the MULTIBUS
backplane, the fans, two industry
standard 5'A " or four half high
industry standard 5'A " peripherals.

Vertical mounting requires the purchase of an optional floorstand (order
code SYP3l2). Use of the floorstand
does not change the environmental
specifications.

Cooling
Two fans force air across the chassis
from left to right (looking at the front
of a horizontally oriented chassis).

CAADCAGE

SPACE FOR DATA SEPARATOR BOARD
BACKPLANE

FULL HEIGHT PERIPHERAL

BAY (DEVICE NOT INCWOEO)

514- FULL HEIGHT

PERIPHERAL BAY
(DEVICE NOT INCWDED)

POWER SUPPLY (BENEATH DRIVE BASE)

Major Chassis Components
RUN INDICATOR AND INTERRUPT SWITCH
RUN INDICATOR AND RESET SWITCH

15-20

INPUT POWER:

/'00/"01120 - 220/240 VAC
_ 50160 HZ

SAFETY: ULlCSAIVDEIlEC
RFI: FCCiVDE
OPERATES AT

SPACE FOR TWO
(CUSTOMER INSTALLED)
FULL HEIGHT
5V." PERIPHERALS

BASE

"POWER" LIGHT
AND
RESET SWITCH

"RUN" LIGHT
AND INTERRUPT
SWITCH

Chassis Front View
Desk Top or Rack Mount
or Floor Standing
.(WIOptional Stand)

PORT TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE

1
2
3
4
5
6

SIZE

TYPICAL USE

25·Pin '0' subminiature
15·Pin '0' subminiature
37·Pin '0' subminiature
35·Pin '0'
26·Pin '0'
75 Ohm BNC

RS232C
Networks
Miscellaneous
Parallel Printer
GPIB 488
Video

AC POWER

Jl
J2
J3
J4
J5
~
CD
0::=>
(~--=.3_ ) C~--",-3_____) (
3
)
J6
J7
J8
J9
Jl0
Jtl
Q
CD
C~ C ) 0::=> CD CD
J12
J13
J14
J15
J16
J17
rr-=l
®
0=) 0::=> 0::=> CD CD
J21
J18
JIg
J20
J22
J23
Il;d
®o=)
CD
CD
CDCQ
~
J27
J24
J25
J26
® o:::J
~ CD CO Ole lJ1n
J30
J31
J32
co CD CD ~w~

AC POWER
PANEL

FUSE
AND
VOLTAGE
SELECTOR

Chassis Back View

15-21

SPECIFICATIONS
Dimensions
HORIZONTAL ORIENTATION
Height: 165 mm (6.5 '1
Width: 432 mm (17.0")
Depth: 508 mm (20.0")
Approximate Weight: 18.1 Kg (42 Ib)

VERTICAL ORIENTATION
Height: 620 mm (24.4 ")
Width: 216 mm (8.5 ")
Depth: 584 mm (23.0")
Approximate Weight: 25.5 Kg (55 Ib)

Safety Requirements
EMI Limits
The chassis is designed to meet:
Safety: UL 114, CSA 22.2, IEC 435
RFIIEMI: FCC Docket 20780 Class A
VDE0871 Class A
Actual compliance will depend on the
single board computers, peripherals,
and the cable connectors which the
user installs in the chassis.

Altitude: Sea Level to 2,400 meters

Input Power

(8,000 ft)

Voltage and Maximum Current:
88 to 132 VAC, 6 amps or
176 to 264 VAC, 4 amps
Frequency: 47 to 63 Hertz
Maximum power consumption: 600 watts
The chassis is shipped configured for
120 VAC operation. The user can
easily change this setting for use with
220 VAC.
.

Output Power
Voltage and maximum current:
+5VDC
4.75 to 5.25VDC 45 amps
8 amps
+12VDC 11.40 to 12.6OVDC
-12VDC -11.4 to -12.6VDC 2.5 amps
Maximum total output power: 360 watts

Shock: 30 G Non-operating
Vibration:
5 Hz to 1 KHz Random
0.001 Ga/Hz (1 G rms) Operating
The chassis is not intended for use in
mobile or high vibration environments

ORDERING INFORMATION
Chassis:
SYS310AP93
Chassis:
SYS310AP94
Floorstand: SYP312
Chassis Trak 300S non-pivoting rack
slide or equivalent are available from
Chassis Trak, Inc., P.O. Box 39100,
Indianapolis, Indiana 46239.

Environmentals
The following numbers are the limits for
this chassis regardless of customer
configuration
Operating: 100C to 35°C
26°C maximum Wet Bulb
temperature 20% to 80% Relative
Humidity, non-condensing

15-22

Intel believes that the information in
this document is accurate as of its
publication date; such information is
subject to change without notice. Intel
is not responsible for any inadvertent
errors.

MULTIBUS® II System
Packaging
and Power Supplies

.:,

intJ

iSBC® PKG/606
iSBC PKG/609
MULTIBUS® II CARDCAGE ASSEMBLIES

•

Available in Two Sizes to Hold Up to 6
or 9 MULTIBUS® /I Boards

•

All Lines Fully Terminated per the iPSB
MULTIBUS /I Specification

•

Designed to Mount Inside a Chassis or
Other Enclosure

•

Assembly Uses Aluminum Extrusion
Construction for Strength and Rigidity·

•

Accommodates Intel iSBC® PKG/902
and iSBC® PKG/903 2 and 3 Slot
ILBXTM /I Backplanes

•

Uses a 6 Layer Parallel System Bus
(iPSB) Backplane

The iSBC PKG/SOS/S09 series of cardcages are designed to mount and interconnect up to S or 9 MULTIBUS II
boards for small to medium size advanced MULTIBUS II microcomputer systems. The cardcages are compact
in size and easily mount in standard or custom enclosures. Extra-wide support extrusions and heavy duty
endplates help make the iSBC PKG/SOS/S09 cardcage assemblies especially suited for installation in systems
located in high vibration or high shock environments. Installed in the cardcage assembly is a Slayer iPSB
backplane that utilizes separate power and ground planes and fully terminates all signal lines. This layout
minimizes system noise and ensures reliable operation even in fully loaded, multiprocessor-based system.

280075-1

1S-1

September 1986
Order Number: 280075.(102

inter

iSBC® PKG/606 ISBC PKG/609

FUNCTIONAL DESCRIPTION

Mechanical Features
The cardcages accommodate up to 6 (iSBC
PKG/606) or 9 (iSBC PKG/609) MULTIBUS II
boards spaced at O.B inch centers. The assemblies
are designed to hold "double. high" (6U) Euro formfactor boards (233.4 mm high x 220 mm deep) or a
mixture of "single high" .(3U) and "double high"
boards using additional hardware (not supplied).
Each installed board is held in place by two screws
supplied as part of the board retainer hardware.
The cardcage frame is bunt using five support extrusionsand two aluminum end plates as shown in figure 1. Both cardcages are 10.5" wide and 10.1"
deep and vary in height according to model (see
specifications section).
The cardcages are designed to mount inside chassis
or other enclosures and may be installed so that the
MULTIBUS II boards load either horizontally or vertically in the unit. All assembly hardware is countersunk allowing the cardcages to be mounted ·flush
against any internal chassis surface.
A Parallel System Bus (iPSB) backplane is mounted
to the P1 side of the assembly, and one or more
iLBXTM II backplanes (not supplied) can be mounted
to the P2 side.

capacitive loading on the bus. Mounted on the backplane are 6 or 9, 96-pin, female DIN connectors (depending on model), bus termination resistors, decoupiing capacitors, and power terminals. Press-fit technology is used throughout. The PC board is UL recognized for flammability. The card cages themselves
are UL recognized components.
Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + VCC and ground. Different size resistors are. used according to the type
of driver connected to the line in an operating
system.
The DIN type connectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The connectors are mounted on O.B"centers to match. Intel's IPSB (Parallel System Bus)
MULTIBUS II backplanes and are ~eyed to ensure
proper mating to the MULTIBUS II board. The connector can provide up to 9 amps of current at + 5V
to each MULTIBUS II board in addition to the current
avanable over the iLBX II backplane.
Screw terminals on the backplane are provided for
connection to + 5V, ± 12V power and ground. In addition, an extra + 5V terminal is provided for connection to a backup battery for memory protection during power fan conditions. These terminals, each of
which can handle up to 25 amps of current at 55·C,
provide a simple and highly reliable connection
method to the system power supply.

Electrical Features
The iPSB backplane uses a 6 layer design with separate power and ground layers and a signal routing
scheme which minimizes ringing, crosstalk, and

The first slot position is designed to accept the Central Services Module (CSM) MULTIBUS II board. All
other slots can accept any combination of
MULTIBUS II boards.

END PLATE
(1 OF 2)
IPsa BACKPLANE
(9 SLOT SHOWN)
. -P1 SIDE

SUPPORT
EXTAUSION(1 OF 5)

\
:f

...'
.'
~

ILaXNII
MOUNTING
LOCATION
-P2 SIDE

rL -

10:11 IN

~(25.88CM.)--'1

SLOT 0
(J1)

10.47 IN.
(28.19 CM.)

- I-I

/
/

v-,

SUPPORT
EXTRUSION

V- CARD GUIDE

'SEE SPECIFICATIONS

280075-2

Figure 1. Cardcage Assembly Dimensions (ISBC® PKG/609 shown)
16-2

inter

iSBC® PKG/606 iSBC PKG/609

SPECIFICATIONS

Mechanical
Specification
Board Capacity
Dimensions Height
Width
Depth
Weight

iSBC® PKG/606 Card cage

iSBC® PKG/609 Card cage

6
15.20 cm (5.98 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
4 Ibs. (1.8 kg)

9
21.20 cm (8.38 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
5 Ibs. (2.3 kg)

Board Spacing

0.8 in. (20.3 cm)

Mounting Hole Locations

See Figure 2

Construction Materials,
Cardcage Frame

Aluminum extrusions and end plates, nylon card guides

Construction Method
iPSB Backplane

Six layer backplane with separate VCC and ground layers;
all connectors, power terminals, and resistor/capacitor
sockets are press·fit into the backplane

Connector Type

96 pin "DIN" female, gold plated, meets IEC standard
603·2·IEC·C096·F
Quantity of Power Terminals and Current Rating:

Electrical
iPSB Backplane- Meets Intel MULTIBUS II specifi·
cation No. 146077 for board
dimensions, layout, signal line
termination, and transmission
characteristics
Power Connections- Type: Screw terminal block,
AMP PIN 55181·1, Winches·
ter PIN 121·25698·2, or
equivalent

.73IN~ ~
(1.85 CM)

Voltage

Quantity
3
1
1
1
4

+5
+12
-12
+5BB
GND

FRONT ~
9.01 IN
(22.89 CM)

T
(1:[

iSBC® PKG/606
Cardcage

f-o

iSBC® PKG/609
Card cage

Current
Current
Quantity
(amps)
(amps)
54
12
12
12
78

4
1
1
1
5

1.491N
(3.78CM)

I
---1..

BOTTOM
VIEW

6.28 IN
M.)

~V-17-----.,....-

.1881N (4.78 MM)
DIA. (4 PL)

BACKPLANE
MOUNTING ---'
LOCATION

REAR

280075-3

Figure 2. Mounting Hole Locations
16·3

81
18
18
18
135

iSBC® PKG/606 iSBC PKG/609

Mating Connection: No.6 locking spade or ring
tongue lug

Operating Environment:
0-55°C (at 25 amps per power terminal);
0-70°C (at $; 18 amps per power terminal);
0% to 95% relative humidity, non-condensing;
0-10,000 ft. altitude.
Reference Manual- MULTIBUS II Cardcage Assembly and iLBX II Backplane User's Guide, PIN
146709-001 (supplied).

Maximum current available per slot:
Voltage

Current

+ 5V
+12V
-12V
+5BB

9A
2A
2A
2A

ORDERING INFORMATION
Part Number

Description

iSBC PKG/606

6 slot MULTIBUS II Cardcage
Assembly

iSBC PKG/609

9 slot MULTIBUS II Cardcage
Assembly

16-4

inter

iSBC® PKG/902
iSBC® PKG/903
MULTIBUS® II iLBXTM II BACKPLANES

Provides ILBXTM II Interconnect for
• Fastest
CPU/Memory Data Transfers
Designed to Mount In MULTIBUS® II
• Cardcage
Assemblies

•

a 6 Layer, Fully Terminated
• Uses
Backplane
a 10 Pin Connector for
• Includes
BITBUSTM Applications
Available In 2 Slot (ISBC® PKG/902)
• and
3 Slot (ISBC® PKG/903) Sizes

Meets All Electrical and Mechanical
Requirements of the MULTIBUS® II
Specifications

The iSBC PKG/902 and iSBC PKG/903 series of iLBX II backplanes are designed to mount on the P2 side of
Intel's MULTIBUS II cardcage assembly or other double Euro (6U) card cage. One or more backplanes may be
installed in a system to allow high speed data transfers between the CPU and memory boards installed in the
system. The iLBX II backplane uses a 6 layer PCB with separate power and ground planes and full termination
on all signal lines. This deSign minimizes system noise and ensures reliable operation in all applications.

280074-1

16-5

October 1988
Order Number: 280074-002

iSBC® PKG/902 iSBC® PKG/903 BACKPLANES

of driver connected to the line in an operating system. The SIP style resistors help make the board
compact in size and allows the designer to mount
several backplanes directly adjacent to one another
in a system without having to skip slots.

o .110 IN. DIA. (4PL) /
(2.8MM)

Mounted on the rear of the backplane is .a 10-pin
BITBUS connector. This connector serves as the serial communication interface for any iSBX 344 BITBUS controller boards installed in the system.

:&O~
0

N"
CDN

CDO

Ntn

~------A------~·~I
280074-2

Dimensions

iSBC PKG/902

IN
CM

1.55 .80
3.94 2.03

iSBC PKG/903

IN
CM

2.35
5.97

1.60
4.06

Figure 1.ILBXTM II Board Dimensions
(iSBC® PKG/903Shown)

The DIN type connectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The connectors are mounted on 0.8" centers. to match Intel's iPSB (Parallel System Bus)
MULTIBUS II backplanes and are keyed to ensure
proper mating to the MULTIBUS II board. Thecon~
nector can provide up to 6 amps of current at + 5V
.to.each MULTIBUS II board in addition to the current
available over the Parallel System Bus backplane.
Screw terminals on the backplane are provided for
connection to + 5V power and ground. These terminals, each of which can handle up to 25 amps of
current, provide a simple and highly reliable connection method to the power supply.

SPECIFICATIONS

Mechanical and Environmental
Connector Spacing: 20.3 cm (0.8 in)
Number of Slots: iSBC PKG/902:2 slots
iSBC PKG/903: 3 slots
Board Dimensions: See Figure 1
Weight: iSBC PKG/902~.2 kg (8 oz)
. iSBC PKG/903~.3 kg (12 oz)

FEATURES

Mechanical and Electrical
The iSBC PKG/902 and iSBC PKG/903 iLBX II
backplanes use a 6 layer printed circuit board (PCB)
with separate power and ground layers and a signal
lead routing scheme which minimizes ringing, cross·
talk, and capacitive loading on the bus. Mounted on
the PCB are two (iSBC PKG/902) or three (iSBC
PKG/903) 96 pin DIN connectors, one 10-pin BITBUS, connector, terminating resistors, decoupling
capacitors, and power terminals. The resistors and
capacitors are mounted into sockets, and all parts
are press-fit into the backplane. The PCB is UL recognized for flammability.

Connectors:
DIN: 96-pin female, gold plated, meets IEC standard 603-2-IEC-C096-F
BITBUS: 10-pin male, gold plated, T&BAnsley 6091012M, or equivalent .
Constructed Method: Six layer backplane with separate VCC and Ground layers
All connectors, power terminals, and resistor/capacitor
sockets are press-fit into the
backplane
Mounting Hole Location: See Figure 1
Operating Environment: 0·C-70·C ambient temperature; 0% to 90% relative
humidity, non-condensing;
o ft. -10,000 ft. altitude

Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + VCC and ground. Different size resistors are used according to the type
16-6

infef

iSBC® PKG/902 iSBC® PKG/903 BACKPLANES

Electrical
Backplane Electrical
Characteristics and
Line Terminations:

REFERENCE MANUAL
Per Intel MULTIBUS II
specification 146077,
Sec. II, iLBX II

MULTIBUS II Cardcage Assembly and iLBX Backplane User's Guide, PIN 146709-001 (not supplied)

ORDERING INFORMATION

Power Connections
Type: Screw terminal block: AMP PIN 55181-1;
Winchester PIN 121-25698-2; or equivalent
Mating Connection: No. 6 locking spade or ring
tongue lug
Quantity: 2(VCC, bround)
Current Rating: iSBC PKG/902: 12 amps; iSBC
PKG/903: 18 amps (Power and
Ground)
Maximum Current
6 amps (over the iLBX II backAvailable Per Slot: plane)

Part Number
iSBC PKG/902
iSBC PKG/903

16-7

Description
2 slot iLBX II Backplane
3 slot iLBX II Backplane

SYP 500
MULTIBUS@n
SYSTEM CHASSIS

• Full enclosure MULTIBUS@ n design
development tool or OEM chassis
• Office and indu,strial applications
• 3 full height/6 half beigbt peripheral
. bays
, .
• 8 slot MULTIBUS@
assembly

n cardcage

• 3 slot iLBX™ n backplane .
• 535 Watt power supply
• Fully tested: low-noise, shock;~ibration
and electrostatic .resistant
.

DECEMBER 1986
ORDER NUMBER: 280153-002

16-8

The SYP 500 System Chassis is a
MULTIBUS II design tool enabling
product designers to begin work
immediately on MULTIBUS II
development projects. It is also ideal
for OEM applications. Two front
mounted LEDs indicate "Power On"
and "Status" (PSB busy) while a
keyswitch provides external "reset"
capabilities for the chassis. The voltage
selector, power-on switch and card cage
opening are located in the rear of the
chassis. Three peripheral bays, two of
which are accessible from the front of
the chassis, support up to three industry
standard 5.25" full-height or six halfheight peripherals. An eight slot
cardcage, Parallel System Bus
and iLBX II backplane assembly are
integrated with a 535 Watt
power supply.

FUNCTIONAL DESCRIPTION

Mechanical Features
Intel's SYP 500 MULTIBUS II Chassis
is a full enclosure, off-the-shelf design
development tool and OEM chassis.
Designers and systems integrators can
integrate their MULTIBUS II board set

with tape, Wini or floppy peripherals
into a complete system. The SYP 500
has three full-height 5.25" peripheral
bays. Peripheral power cables, office
and industrial environment cooling, and
peripheral mounting brackets for
industry standard full- or half-height
peripherals are provided with the
chassis. Access via the front panel
allows two of the bays to be configured
with removable media peripherals e.g.
tape and floppy drives.

auxiliary backplane, on the other
hand, provides direct high speed
interconnection between a processor
board and memory boards. It contains
three iLBX slots. One of these slots has
a lO-pin BITBUS connector that serves
as a serial interface for any iSBX 344
BITBUS controller board installed in
the system. This cardcage conforms to
the published MULTlBUS II
specification.

This chassis includes an eight-slot
MULTIBUS II cardcage assembly with
0.8" centers (slot width). The cardcage
is made with heavy duty endplates and
extra-wide support extrusions to ensure
adequate support for most applications.
For industrial applications, this chassis
is mountable into any 19" vertical rack.

The SYP 500 chassis has a 535 Watt
switching power supply with selectable
AC power input of 115 V or 220 V at
47-63Hz. The AC input power is
externally selectable with a slide switch
mounted on the rear of the chassis. A
power distribution board is installed in
the chassis to allow easy connection to
all peripheral bays through six plugs
mounted on the power distribution
board.
The chassis has been fully tested to
ensure low-audible noise emission,
resistance to electrostatic discharge and
resistance to appropriate levels of
vibration and shock in both office and
industrial environments.

Two backplanes are installed in the
cardcage assembly: the system
backplane and the auxiliary backplane.
:rhe system backplane is the Parallel
System Bus (iPSB) for communications
between up to eight MULTIBUS II
boards. This backplane utilizes separate
power and ground planes and fully
terminates all signal lines. The

SPECIFICATIONS:
Electrical Parameters
Maximum Amperage:

Physical Parameters
Voltage

Current

~-+-5~V~-+---7-5A--~

+12V
-12V
Designed to meet:

Electrical Features

lOA
2.5A.

UL478
CSA C22.2 No. 154
FCC Class B
VDE Level B
IEC 435

Height:
Width:
Depth:
Weight:

7.~5"

(19.7 cm)
17.5" (44.5 cm)
22.25" (56.5 cm)
33 Ibs. (15 kg.)

Bay Dimensions
,3.5" wide x 6" high x 8.5" deep

Acoustical Noise
Less than 50 dbA in office environment (30°C)

Electrostatic Discharge

Operational Parameters

No hard errors to 12:5 kV

AC Power Input: 90-132 VAC or
180-264 VAC at 47-63 Hz
Operating Temperature Range: 10°C to 55°C
Storage Temperature: -40°C to 60°C
Operational Humidity: 10% to 85% relative,
non-condensing

Contents
• 8-s10t MULTIBUS II Chassis
• Power cord
• User's guide
• Two keys
• Peripheral mounting brackets & power cables

Ordering Information
SYP 500

16-9

Distributed Control Modules

inter

iSBXTM 344A
BITBUS™ INTELLIGENT MULTIMODULETM BOARD

•
•
•

High Performance 12 MHz 8044
Controller
Integral Firmware Including the IDCX 51
Executive Optimized for Real-Time
Control Applications
Full BITBUSTM Support

2 28-Pin JEDEC Memory Sites for
User's Control Functions
Low Cost, Double-Wide iSBXTM BITBUS
Expansion MULTIMODULETM Board
Power Up Diagnostics

The iSBX 344A BITBUS Intelligent MULTIMODULE board is the BITBUS gateway to all Intel products that
support the iSBX 1/0 Expansion Interface. Based on the highly integrated 8044 component (an 8-bit 8051
microcontroller and an SDLC-based controller on one chip) the iSBX 344A MULTIMODULE board extends the
capability of other microprocessors via the BITBUS interconnect. With the other members of Intel's Distributed
Control Modules (iDCM) family, the iSBX 344A MULTIMODULE board expands Intel's OEM microcomputer
system capabilities to include distributed real-time control. Like all members of the iDCM family, the iSBX 344A
MULTIMODULE board includes many features that make it well suited for industrial control applications such
as: data acquisition and monitoring, process control, robotics, and machine control.

280247-1

17-1

October 1987
Order Number: 280247-002

inter

iSBXTM 344A BOARD

OPERATING ENVIRONMENT

MULTIBUS® Expansion

Intel's Distributed Control Modules (iDCM) product
family contains the· building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high speed serial communication between microcontrollers. The iDCM hardware products: including the iSBX 344A MULTIMODULE
board, iPCX 344A board and all iRCB BITBUS Remote Controller Boards communicate in an iDCM
system via the BITBUS interconnect as shown in
Figure 1.

Typically, MULTIBUS iSBC boards have a maximum
of two iSBX 110 expansion connectors. These connectors facilitate addition of one or two iSBX I/O
MULTIMODULE boards with varying numbers of 110
lines. The iSBX 344A MULTlMODULE board increases the number of I/O lines that can be accommodated by a MULTIBUS system by at least an order of magnitude.

As a member of the iDCM product line the iSBX
344A MULTIMODULE board fully supports the BITBUS microcontroller interconnect. Typically, the
iSBX 344A MULTIMODULE board would be part of a
node (master or slave) on the BITBUS interconnect
in an iDCM system. As shown in Figure 2 the iSBX
344A MULTIMODULE board plugs into any iSBC®
board with an iSBX connector.
The iSBX 344A MULTIMODULE board is the hardware interface between Intel's MULTIBUS® and the
BITBUS environment. With this interface the user
can harness the capabilities of other Intel microprocessors e.g. 80386, 80286, 80186, 8086, 80188,
8088 in a iDCM system or extend an existing MULTIBUS system with the iDCM family.

Extending BITBUSTM fiDCM System
Processing Capability
The iSBX 344A MULTIMODULE board allowsutilization of other processors in a iDeM system to accommodate particular application requirements. The
MULTIMODULE board is compatible with any iSBX
connector so that any board having a compatible
connector can potentially enhance system performance. Intel's DCS100 BITBUS Toolbox Software
provides easy to use high performance software interfaces for iSBC boards. The iSBC 86/35,286/12,
and 188/48 boards are a few examples. Custom
configurations are also possible with user customized software.

BITBUSTW
INTERCONNECT #2

280247-2

Figure 1. iDeM Operating Environment

17-2

ISBXTM 344A BOARD

face Unit (SIU). This dual processor architectureal"
lows complex control and high speed communication to be realized cost effectively.
.

ARCHITECTURE
Figure 3 illustrates the major functional blocks of the
iSBX 344A board: 8044 BITBUS Enhanced Microcontroller (BEM), memory, BITBUS microcontroller
interconnect, Byte FIFO interface, initialization and
diagnostic logic.

The 8044 BEM microcontroller also includes built-in
firmware known as DCM44. This firmware includes a
set 0.1 functions called Remote Access and Control
(RAC), a preconfigured version of the DCX51 Executive, communications software, and a power-up test
procedure·

~
I/O EXPANSION BUS

INmALIZATION
" DIAGNOSTIC
LOGIC

Memory
The iSBX 344A MULTIMODULE board memory consists of two interllal and external memory. Interflal
memory is located in the on-chip memory of the
iDCM controller. The iDCX 51 Executive and the remaining 8044 BEM firmware ration this resource ..
However, eight bytes. of bit addresslilble internal
memory are reserved for the user. Ample space is
reserved for user programs and data in· the iSBX
344A MULTIMODULE board external memory.

OFF CHIP
MEMORY

1-+--+-1_-+1

Z8PIN
CODE SITE

Two 28-pin JEDEC sites comprise the iSBX 344A
MULTIMODULE board external memory. One site
has been dedicated for data; the other for code. Table 1 lists the supported memory devices for each
site. Intel's 2764 and 27128 are examples. The user
may choose one of two. memory configurations and
spepify different memory sizes by placing the proper
jumpers at ,system ,initialization. The most flexible
configuration option provides the user with access to
the code site for program download or !-Ipload. This
feature ensures expansion of an existing' system is
easily accommodated. For example, the addition of
another conveyor to a material, handling system
would require adding another controller or controllers and changes to existing applications code and
addition of new code.

1044
BIT1IUS 111 ENHANCED

MICROCONTROU.ER

280247-4

Table 1. Supported Memory Devices

Figure 3. iSBXTM 344A Block Diagram

iDCM Controller
The heart of the iSBX 344A MULTIMODULE board's
controlling and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044
consists of the advanced 8-bit, 8051 microcontroller
and a SDLC-based controller called the Serial Inter-

17-3

Device

Data Site

Code Site

4Kx8-64Kx8
EPROM/ROM
2K)( 8-32K x 8
SRAM
2Kx8-16Kx'8
NVRAM and E2PROM

Yes

inter

ISBXTM 344A BOARD

matically accepts messages for the FIFO. No user
code is required, increasing the time available for
application system development.

BITBUSTM Microcontroller
Interconnect
The iSBX 344A MULTIMODULE board fully supports
the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial. bus optimized for
control applications. The interconnect supports both
synchronous ~\l<;l ,self-clocked modes of operation.
These modes bf operation are selectable dependent
on application requirements as are the transmission
rates. Table 2 shows different combinations of
modes of operations, transmission rates, and dis·
tances. The SDLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remain·
der of this established architecture. These features
contribute to BITBUS reliability and usefulness as a
microcontroller interconnect.

The Byte FIFO supports both byte and message
transfer protocol in hardware via three register ports:
data, command, and status. The extension side SUPports polled, interrupt, and limited DMA modes of
operation (e.g. 80186 type DMA controllers).

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iSBX 344A
MULTIMODULE board includes many features
which make it well suited for industrial control applications. Power up diagnostics is just one of these
features. Diagnostics simplify system startup consid·
erably, by immediately indicating an 8044 BEM or
external bus failure. The LEDs used for power up
diagnostics are available for user diagnostics after
power up as well as to further contribute to reliable
operation of the system.

TheBITBUS connection consists of one or two differential pair(s) of wires. The BITBUS interface of
the iSBX 344A MULTIMODULE board consists of a
half-duplexRS 485 transceiver and an optional
clock source for the synchronous mode of operation.

Initial iSBX 344A MULTIMODULE board parameters
are set by positioning jumpers. The jumpers determine the BITBUS mode of operation: synchronous,
self-clocked, transmission rate, and address of the
iSBX module in the BITBUS system. This minimizes
the number of spare boards to be stocked for multiple nodes, decreasing stocking inventory and cost.

Byte FIFO Interface·
The Byte FIFO Interface on the iSBX 344A
MULTIMODULE board implements the required
hardware buffering between the 8044 BEM and an
extension. An extension is defined as a device at·
tached to the iSBX 1/0 expansion interface on the
iSBX 344A MULTIMODULE board. In an iDCM system, an example of an extension is an iSBC 286/12
board which may be considered the host board in a
MULTIBUS system. When used with the software
handlers in the BITBUS Toolbox, implementation of
this interface is complete.

INTEGRAL FIRMWARE
Resident firmware located in the 8044 BEM includes: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Control (RAG) function that enables user communication
and control of different microcontrollers and 1/0
points; a. communications gateway to connect the
BITBUS interconnect, iSBX bus, and iDCX 51 Executive tasks; and power up diagnostics.

For particular applications, the user may wish to develop a custom software interface to the. extension
or host board. On the iSBX 344A MULTIMODULE
board side of the interface the iDCM firmware auto-

Table 2. BITBUSTM Mlcrocontroller Interconnect Modes of Operation
Maximum Distance
Between Repeaters
M/ft

Maximum # Nodes
Per Segment

Maximum # Repeaters
Between a Master
and Any Slave

500-2400

30/100

375
62.5

300/1000
1200/4000

28
28

2
10

. Speed
Kb/s
Synchronous
Self Clocked

Segment. Distance between master and repeater or a repeater and a repeater.
Synchronous mode requires user supplied crystal.
.

17-4

inter

iSBXTM 344A BOARD

The services provided by the iSBX 344A MULTIMODULE board integral firmware simplify the development and implementation of complex real-time
control application systems. All iDCM hardware
products contain integral firmware thus supplying
the user with a total system solution.

The Remote Access and Control Function is a special purpose task that allows the user to transfer
commands and program variables to remote BITBUS controllers, obtain the status of a remote 1/0
line(s), or reverse the state of a remote 1/0 line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function.

Intel provides a complete development environment
for the iSBX 344A MULTIMODULE board. Software
development support consists of: the 8051 Software
Development Package, the DCS100 BITBUS Toolbox Host Software Utilities, the DSC11 0 Bitware for
ICETM Support, and the DCS120 Programmer's Support Package. The 8051 Software Development
Package provides the RL 51 Linker and Relocator
Program, and ASM 51. PL/M 51 is also available.
Hardware tools consist of the In-Circuit Emulator
(ICE 51001044).

DEVELOPMENT ENVIRONMENT

Table 3. IDCX 51 Calls

Call Name

Description

TASK MANAGEMENT CALLS

RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS

RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS

RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS

RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS

RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

17-5

iSBXTM 344A BOARD
Table 4. RAC Services
RACService

Action Taken by Task 0

RESET_STATION

Perform a software reset.

CREATLTASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call ..

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC

PROJECT

Suspend or resume RAC services.

READ_I/O

Return values from specified 1/0 ports.

WRITE

Write to the specified 1/0 ports.

1/0

UPDATE_I/O
UPLOAD

Update the specified I/O ports.

MEMORY

Return the values in specified memory area.
~alues

DOWNLOAD_MEMORY

Write

OR_I/O

OR values into specified 1/0 ports.

AND

1/0

AND values into specified 1/0 ports.

XOR . .,..J/O

XOR values into specified 1/0 ports.

READ

INTERNAL

WRITE_INTERNAL

to specified memory area.

Read values at specified internal RAM areas.
Write values to specified internal RAM areas.

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD

Write values to specified EEPROM memory.

CODE

NOTE:
Internal memory locations are included in the 192 bytes of data RAM providecj in the microcontroller. External memory refers
to memory outside the microcontroller - the 2B-pin sockets of the iSBX 344A module and the iRGB 44/10A board. Each
RAG Access Fun"ction may refer to multiple 110 or memory locations in a single command.

Add ress Range

SPECIFICATIONS
CPU
8044 BITBUS Enhanced Microcontroller (BEM)

Word Size'
Instruction: 8 bits
Data: 8 bits

Processor Clock 12 MHz

Option A

Option B

External
Data
Memory

0000H-7FFFH

External
Code
Memory

1000H-OFFFFH

8000H-OFEFFH

Internal
Code
Memory

OOOOH-OFFFH

Option A: Supports maximum amount of external EPROM code memo
ory.
Option B: Supports downloading code into external RAM or EEPROM
memory.

Instruction Execution Times
1 JJ.s 60% instructions
2 JJ.s 40% instructions

Terminations

4 JJ.s Multiply & Divide

Sockets provided on board for % Watt 5% Carbon
type resistors. Resistor value to match characteristic
impedance of cable as closely as possible-120n or
greater.

Memory CapacityI Addressing
iDeM Controller: Up to 64 Kbytes code

Message Size
54 bytes max

17. . 6

intJ

ISBXTM 344A BOARD

8044 BITBUSTM Enhanced Mlcrocontroller

(8044
Function

+ Firmware) 1/0 Addressing as Viewed from the 8044
Address

Read

Write

Bit

Oata

FFOOH

Command

FF01H

Status
-RFNF*
-TFNE*
-TCMO*

B3H
B2H
92H

Write sets command to
extension - Read clears
command from extension

LEO #1

90H

LEO #2

91H

B4H

Node Address

FFFFH

Configuration

FFFEH

Also INT1 Input
Also INTO Input

~
.~

ROY/NE*

Comments

iSBXTM 344A MULTIMODULETM Board 110 Addressing as Viewed from the
ISBXTM 344A MULTIMODULETM Board·
Register Function

Address

Oata

Comments

Base'

Read/Write

Command

Base'

Write sets command from
extension
Read clears command to
extension

Status

Base'

Read Only

Interrupt/DMA Lines

Status Register Interface

Signal

Location

Interface
Option

RINT
TINT
RCMI
RORQ
TORQ

MORQ/MINTO
MINT1
OPTO
MORQ/MINTO
MINT1

INT
INT
INTorOMA
OMA
OMA

Status Register Interface
7 6 5 432 1 0

I I

'l'fL-______
I I I I L£J
L-___________

TFNF*
RFNE*
RCMD*

280247-5

17-7

intJ

iSBXTM 344A BOARD

The iSBX 344A MULTIMODULE board presents one
standard load to the BITBUS bus

Connector Options
10 Pin Plug

Power Requirements

Flat Cable: 3M 3473-6010, TB Ansley 609-1001M,
or equal

0.9A at + 5V ± 5% (does nof include power to the
,
memory devices)

Discrete Wire: BERG 65846-007, In Cannon 1217326-105, or equal

Physical Characteristics
Pinout
Pin

Signal

1
2
3
4
5
.6
7
8
9
10

+12V
+12V
GND
GND
DATA·
.DATA
DCLK*/RTS·
DCLK/RTS
RGND
RGND '.'

Double-wide iSBXTM MULTIMODULETM Form Factor
Dimensions
Height: 10.16 mm (0.4 in) maximum component
height
Width: 63.5 mm (2.50 in)
Length: 190.5 mm (7.50 in)
Weight: 113 gm (4 OUrlces)

Environmental Characteristics
Operating Temperature: O·C ,to 55·C at 200 Linear
Feet/Minute Air Velocity
Humidity:
90% non-condensing

Electrical Characteristics
Interfaces

Reference Manual (NOT Supplied)

iSBXTM 1/0 Expansion Bus: supports the standard
I/O Expansion Bus Specification with compliance
level IEEE 959.

148099- iSBX 344A Intelligent BITBUS Interface
Board User's Guide

Memory. Sites: Both code and data sites support the
standard 28-pin JEDEC site.

Ordering Information

BITBUSTM InterconneCt: Fully supported synchronous mode at 2.4 Mbits/sec and self clocked mode
for 375 kbitslsec and 62.5 kbits/sec

Part Number Description
iSBX 344A

17-8

BITBUS Intelligent MULTIMODULE
board

inter
•
•
•

iPCX 344A
BITBUSTM IBM* PC INTERFACE BOARD
Compatible with Intel's DOS-Based
• Development
Tools
External Memory Sites for User's
• Control
Programs
PC System Form Factor Board
• IBM
Power Up Diagnostics
•

High Performance 12 MHz 8044 SingleChip Microcontroller
Integral Firmware Optimized for RealTime Control Applications Using the
BITBUSTM Interconnect
Fully Supports Intel's Complete Remote
Control Soard Product Line (iRCS)

The iPCX 344A BITBUS IBM PC INTERFACE board provides the BITBUS gateway to IBM's family of Personal
and Industrial Computers. Based on Intel's highly integrated 8044 (an 8051 microcontroller and an SDLC
controller on one chip) the iPCX 344A IBM PC INTERFACE board extends the real-time. control capability of
the IBM PC via the BITBUS interconnect. The PC system performs the human interface functions for the
BITBUS interconnect. Like all members of Intel's Distributed Control Modules (iDCM) family, the iPCX 344A
IBM PC INTERFACE board includes features tl]at make it well suited for Industrial Control applications such
as: data acquisition and monitoring, process control, machine control, and statistical process .control (SPC).

"IBM is a trademark of International Business Machines.

17-9

October 1887
Order Number: 280414-002

intJ

IPCX344A

IRCU4/10A
DIGITAL BOARD

280414-2

Figure 1. IDeM Operating Environment

OPERATING ENVIRONMENT

ARCHITECTURE

Intel's Distributed Control Modules (iDCM) product
family provides the building blocks to il)'lplement
real-time distributed 1/0 control applications. All of
the iDCM family utilizes the BITBUS,interconnect to
provide standard high speed serial communication
between microcontrollers. The iDCM hardware products: including the iPCX 344A board, iSBXTM 344A
MULTIMODUL!:TM board and all iRCB BITBUS Remote Controller Boards communicate in an iDCM
system via the BITBUS interconnect as shown in
'
Figure '1.

Figure 2 illustrates the major functional blocks of
the iPCX 344A IBM PC INTERFACE board: B044
BITBUS ENHANCED MICROCONTROLLER, memory, BITBUS interconnect, PC System Interface, and
initializationldiagnostic logic.

As a member of the iDCMProduct line, the iPCX
344A IBM PC INTERFACE board fully supports the
.aITBUS microcontroller interconnect. Typically, the
iPCX 344A IBM PC System INTERFACE board will
be part of a node (master or slave) on the BITBUS
interconnect. The iPCX 344A board plugs into the
PC add-in slot.
The iPCX 344A IBM PC INTERFACE board is the
hard~are interface between the PC system and the
BITBUS environment. With this interface the user
can utilize the human interface and application software of the PC and extend the 1/0 range of the PC
to include real-time distribUted control.

Memory,mode ,of operation, and bus transmission
'rate options are easily selected by the user, thereby
, decreasing inventory levels and associated costs.

8044 BITBUSTM Enhanced
Mlcrocontroller (BEM)
The source of the iPCX 344A IBM PC INTERFACE
board's controlling and communication capability is
Intel's highly integrated 12 MHz B044 microcontroller. The B044 consists of the advanced B-bit, B051
microcontroller and a SDLC controller called the Serial Interface' Unit (SIU). This dual processor architecture provides complex control 'and high speed
communications in a cost-effective, single chip implementation.

1.7-10

inter

iPCX344A

Two 28-pin JEOEC sites comprise the iPCX 344A
board's external memory. One site is dedicated to
data; the other to code. Table 1 lists the supported
memory devices for each site. Intel's 2764 and
27128 are examples. The user can choose one of
two memory configurations and specify different
memory sizes by configuring the correct jumpers.
This configurability provides the user with access to
the code site for program download or upload .and
ensures that an existing system is easily expanded.

PC BUS

I
INITIALIZATION
& DIAGNOSTIC
LOGIC

BYTE FIFO
INTERFACE

Table 1 Supported Memory Devices
OF F CHIP
ME MORY
28 PIN
DAtA SITE
28 PIN
.CO DE SITE

8044
BITBUS" ENCHANCED
MICROCONTROLLER

Device

Data Site

Code Site

4K x 8-64Kx8
EPROM/ROM

Yes

2Kx 8-32K x8
SRAM

Yes

2K x 8-16K x 8
NVRAM and E2PROM

Yes

BITBUSTM Microcontroller
Interconnect

__-J

The iPCX 344A IBM PC INTERFACE board fully supports the BITBUS microcontroller interconnect The
BITBUS interconnect is a serial bus optimized for
. control applications and supports both synchronous
and self-clocked modes of operation. Each mode of
operation and the different transmission rates are
jumper selectable dependent on application requirements.

BITBUS'· INTERCONNECT

280414-3

Figure 2. iPCX 344A Block Diagram
Another essential part of the 8044 controller is the
integral firmware residing on·chip to implement the
BITBUS interface. In the operating environment of
the iPCX 344A board, the 8044's SIU acts as an
SOLC controller offloading the on·chip 8051 micro·
controller of communication tasks; freeing the 8051
to concentrate on real·time control.
The 8044 BEM (8044 microcontroller and on·chip
firmware) provides in one package a simple user in·
terface, and high performance communications and
control capabilities to efficiently and economically
build a complex control system.

Table 2 shows different combinations of mode of
operation, transmission rate, and distance. The
SOLC protocol, BITBUS message format, and compatibility with Intel's other software and hardware
products comprise the remainder of this established
architecture. These features contribute to BITBUS
reliability and usefulness as a microcontroller interconnect
The BITBUS connection consists of one or two differential user selected pair(s) of wires. The BITBUS
interface on the iPCX 344A board consists of a halfduplex RS485 trarisceiver and an optional clock
source for the synchronous mode of operation.

Memory
The iPCX 344A IBM PC System INTERFACE board
contains both internal and external memory. Internal
memory is located in the on-chip memory of the
8044 BEM. The BITBUS firmware includes Intel's
powerful iOCX 51, real-time, multitasking, executive.
Eight bytes of bit-addressable internal memory are
reserved for the user. Additional space is reserved
for user programs and data in the board's external
memory.

PC System Interface
The iPCX 344A board will operate in any IBM PC XT,
PC AT, or compatible system that meets the following requirements:
-

17-11

An IBM PC, PC XT with an oscillator running at
4.77 MHz (processor running at 4.77 MHz also)

inter
-

iPCX344A

An IBM PC AT with an oscillator running at 12 or
16 MHz (processor running at 6 or 8 MHz)
An available I/O channel with addresses that are
not used by any other boards in the system in the
range of 200H to 3FFH on even addresses
At least one available system interrupt (required
ONLY if running the iPCX 344A board in interrupt
mode; user selectable from PC Interrupts 2, 3, 4,
5,6, or 7)

All IBM guidelines have been followed to ensure
complete IBM PC system compatibility.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iPCX 344A
BITBUS IBM PC INTERFACE board includes many
features making it well suited for industrial control
applications. Power on diagnostics simplify system
startup considerably by immediately indicating an
8044 BEM or external bus failure.

The iDCX 51 Executive is an event-driven software
manager that can respond to the needs of multiple
tasks. This real-time multitasking executive provides:
task management, timing, interrupt handling, and
message passing services. Table 3 shows the
iDCX 51 operating system calls. The executive supports up to seven user tasks at each node while
making BITBUS operations transparent.
Remote Access and Control (RAG) is a special pur- .
pose task that allows the user to transfer commands
and program variables to and from BITBUS controllers to obtain the status of I/O or data line(s), or
reverse the state of an I/O line or read and write
memory, etc. No user code need be written to use
this function. See Table 4 for a complete listing of
RAC services.
The services provided by the iPCX 344A board's integral firmware simplify the development and implementation of complex real-time control systems.

DEVELOPMENT ENVIRONMENT
Intel provides a variety of development environments for BITBUS applications. Intel's Development
Systems and OEM Systems Handbooks provide details on the following development tools.
- BITBUS TOOLBOX-BITBUS Monitor and Interface Handlers
- ASM/PLM 51-Low and High level languages
for application code generation on 8044

INTEGRAL FIRMWARE

The iPCX 344A BITBUS PC-BUS INTERFACE board
contains resident firmware located in the 8044
BITBUS ENHANCED MICROCONTROLLER. This
on-chip firmware consists of: a pre-configured
iDCX 51 Executive for real-time, multitasking control;
DCM 44, a Remote Access and Control (RAG) program that enables BITBUS communication and control of I/O pOints on the BITBUS interconnect; and
power up diagnostics.
Table 2. BITBUSTM Microcontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum #.. Nodes
Per Segment"

Maximum #. Repeaters
Between a Master and
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment: Distance between master and repeater or repeater and repeater.
Synchronous mode requires user supplied crystal.

Table 3. iDCX 51 Systems Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAll

Wait for a message event.
17-12

infef

iPCX 344A

Table 3. iDCX 51 Systems Calls (Continued)
Description

Call Name
MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RE$ENABLE$INTERRUPT

Re·enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.
Table 4; RAC Services

RACService

Action Taken by Task 0

RESET_STATION

Perform a software reset.

CREATE_TASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROJECT

Suspend or resume RAC services.

READ_I/O

Return values from specified I/O ports.

WRITE_IIO

Write to the specified I/O ports.

UPDATE_I/O

Update the specified I/O ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY

Write values to specified memory area.

OR_I/O

OR values into specified I/O ports.

AND_I/O

AND values into specified I/O ports.

XOR_IIO

XOR values into specified I/O ports.

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values to specified internal RAM areas.

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD_CODE

Write values to specified EEPROM memory.

SPECIFICATIONS
CPU

Processor Clock
12.0 MHz

8044 BITBUS Enhanced Microcontroller (BEM)

Instruction Execution Time

Word Size

1 /ks 60% instructions
2 /ks 40% instructions
4 /ks. Multiply and Divide

Instruction-8 bits
Data-8 bits

17·13

inter

IPCX344A

Memory Capacity Addressing

Physical Characteristics

iDCM Controller: Up to 64 Kbytes code.
Device
EPROM/ROM
4Kx8-64Kx8
SRAM
2Kx8-32Kx8
NVRAM and E2PROM
2Kx8-16Kx8

IBM PC ADD-ON FORMAT
Height: 3.98 in.
Depth: 6 in ..

Data

Code

Yes

Interfaces

Yes

BITBUS Interconnect: Fully supports synchronous
mode at 500 Kbps to 2.4 Mbs
and self-clocked modes at
375 Kbs or 62.5 Kbs
Note: On-board ALE clock
supports 1 Mbps synchronous operation. All other synchronous mode speeds require user-supplied 2.0 MHz9.6 MHz crystal.
PC System:
Two unidirectional, one-bytedeep, nine-bit FIFO buffers
(ninth bit distinguishes between data and command)

External 1/0 Space
OFFOOH-OFFFFH
space)

(mapped

into

data

memory

Termination
Minimum 1200 each end of BITBUS interconnect
with user supplied resistors

Add ress Ranges·
Power Requirements

Option A
Option B
External Data 0000H-7FFFH
0000H-7FFFH
Memory Site
External Code 1OOOH -OFFFFH 8000H-OFEFFH
Memory Site (OOOOH -OFFFFH
If EA Active)
Internal Code OOOOH-OFFFH
OOOOH-OFFFH
Memory

0.9A at

up to 54 bytes

(memory not included)

Environmental Requirements

Option A: Supports maximum amount of external EPROM code memo
ory.
Option B: Supports downloading code Into external RAM or EEPROM
memory.

Message Size:

+ 5V ± 5%

Operating Temperature: 16'C to 32'C at no .air ·flow
O'C to 55°C at 200 Linear
Feet/Minute air velocity
Operating Humidity:
90% Noncondensing
Storage Temperature: - 40'C to + 70'C
Storage Humidity:
95% Noncondensing

REFERENCE MANUAL
149235-001- iPCX 344A BITBUS IBM PC System
Interface Board User's Guide

Connectors
Standard 9-pin-D Subminiature socket

ORDERING INFORMATION
Part Number
iPCX344A

17-14

Description
BITBUS IBM PC System
INTERFACE Board

iRCB 44/10A
BITBUSTM DIGITAL I/O REMOTE CONTROLLER BOARD

•
•
•
•
•

High Performance 12 MHz 8044
Controller

I/O Expansion with 8·Bit iSBXTM
• Connector

Integral Firmware: iDCX Executive,
Optimized for Real· Time Control

•
•
•

Full BITBUSTM Support
Standard Industrial Packaging:
Eurocard, DIN Connector

Programmable Control/Monitoring
Using 24 Digital I/O Lines
Power Up Diagnostics
Compatible with iRCX 910 Digital Signal
Isolation and Termination Module

2 28·Pin JEDEC Memory Sites for
User's Control Functions

The iRCB 44/10A BITBUSTM Digital liD Remote Controller Board is an intelligent real-time controller and a
remote liD expansion device. Based on the highly integrated 8044 component (an 8 bit 8051 microcontroller
and an intelligent SDLC-based controller on one chip) the iRCB 44/10A board provides high performance
control capability at low cost. The iRCB 44/10A board can expand Intel's OEM microcomputer system capabilities to include distributed real-time control. Like all members of the iDCM family, the iRCB 44/10A board is
well suited for industrial control applications such as data acquisition and monitoring, process control, robotics,
and machine control.

280213-1

17-15

October 1987
Order Number: 280213-003

intJ

iReB 44/10A

OPERATING ENVIRONMENT,

, ARCHITECTURE

Intel's Distributed Control Modules (iDCM) product
family contains the building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high speed serial communication between microcontrollers. The iDCM hardware products, which include the iPCX 344A board, iSBX 344A
MULTIMODULETM board and the iRCB 4411 OA BITBUS Remote Controller Board (and other iRCB
boards), communicate in an iDCM system via the
BITBUS interconnect as shown in Figure 1.
The iRCB 44/10A board, can be used as an intelligent remote controller or an 110 expansion device.
When performing as an intelligent controller the
iRCB 44/10A board not only monitors the status of
multiple process points, but it can execute varied
user supplied control algorithms. When functioning
as an 110 expansion device, the iRCB 44/1 OA board
simply collects data 'from multiple 110 ports and
transmits this information via the BITBUS or iSBX
bus interface to the sys1em controller for analysis or
updating purposes.
As a member of the iDCM product line, the iRCB
44/10A board fully supports the BITBUS microcontroller interconnect. Typically, the iRCB 44/10A
board would be a node in a BITBUS system. The
iRCB 44/10A board could be a master or slave
node. (The BITBUS system supperts a multidrop
configuration': one master, many slaves.)

Figure 2 illustrates the major functional blocks of the
iRCB 44/10A board: 8044 BITBUS Enhanced Microcontroller, memory, BrrBUS microcontroller interconnect, parallel 110, iSBX expansion, initialization
and diagnostic logic.

8044 BITBUSTM Enhanced
Microcontroller
The heart of the iRCB 44/10A board's controlling
and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044 consists
of the advanced 8-bit 8051 microcontroller and a
SDLC controller called the Serial Interface Unit
(SIU). This dual processor architecture allows complex controi and, high speed communication functions to be realized cost effectively. The 8044's SIU
acts as a SDLC-based controller which offloads the
on-chip 8051 microcontroller of communication,
tasks; freeing the 8051 to concentrate on real-time,
control.
The 8044 BEM microcontroller also includes, in firmware, a set of procedures known as Remote Access
and Control (RAC), a preconfigured version of the
DCX 51 Executive, communications software, and
power-up diagnostics.
The BEM (8044 microcontroller and on-chip firmware) provides, in one package, a simple user interface, and high performance communications and
control capabilities to efficiently and economically,
build a complex control system.

280213-2

Figure 1.IDCM Operating Environment

17-16

inter

iRCB44/10A

ensures expansion of an existing system is easily
accommodated.

Memory
The iRGB 44/10A board memory consists of two
sections: internal and external. Internal memory is
located in the on-chip memory of the BEM. The
iDGX51 Executive and the remaining BEM firmware
ration this resource. However, eight bytes of bit addressable internal memory are reserved for the user.
Ample space is reserved for user programs and data
in the iRGB 44/10A board external memory.
Two 28 pin JEDEG sites comprise the iRGB 44/10A
board external memory. One site has been dedicated for data, the other for code. Table 1 lists the supported memory devices for each site. Intel's 2764,
and 27128 are examples. The user may choose one
of two memory configurations and specify different
memory sizes by placing the proper jumpers at system initialization. The most flexible configuration option provides the user with access to the code site
for program download or upload. This feature

INmALIZATION
AND
DIAGNOSTIC
LOGIC

Table 1. Supported Memory Devices
Device

Data Site

Code Site

4K x 8-64K x 8
EPROM/ROM

YES

x 8-32K x 8

YES

SRAM.
2K x 8-16K x 8
NVRAM and E2PROM

BITBUSTM Microcontroller
Interconnect
The iRGB 44/10A board serial interface fully supports the BITBUS microcontroller interconnect. The
BITBUS interconne~t is a serial bus optimized for

28 PIN DATA SITE

24UNES

PARALLEL
I/O

BITBUS"
REPEATERS
(OPTIONAL)
...-==-=--~

BITBUS'" INTERCONNECT

.re==:=:=. c::::::>""'.
REPEATED BITBUS"
INTERCONNECT

280213-3

Figure 2.IRCBTM 44/10A Block Diagram
17-17

intJ

iReB 44/10A

control applications. The bus supports both synchronous and self-clocked modes of operation. These
modes of operation are selectable dependent on application . requirements as are the transmission
speeds. Table 2 shows. the different combinations of
modes of operation, transmission speed,S, and distances. The SDLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remainder of the BITBUS architecture. These features contribute to BITBUS system reliability and l,Isefulness
as a microcontroller interconnect.
The BITBUS connection consists of one or two differential pair(s) of wires. The serial (BITBUS) interface of the iRCB 44/10A board consists of: a halfduplex RS 485 transceiver, an optional BITBUS repeater and an optional clock source for the synchronous mode of operation.

Digital Parallel 110
In order to provide an optimal parallel 1/0 interface
for control applications, the iRCB 44/1 OA board supports 24 software programmable parallel 110 lines.
This feature supplies the flexibility and simplicity required for control and data acquisition systems. Sixteen of these lines are fully programmable as inputs
or outputs, with loop back, on a bit by bit basis so
that bit set, reset, and toggle operations are streamlined. The remaining eight lines are dedicated as inputs. Figure 3 depicts the general 110 port structure.
The parallel 1/0 lines can be manipulated by using
the Remote Access and Control (RAC) function (in
BEM firmware) from a supervisory node or locally by
a user program. The user program can also access

the RAC function or directly operate the 1/0 lines.
Input, output, mixed- input and output, and bit operations are possible simply by reading or writing a
particular port.

iSBXTM Expansion
One iSBX 1/0 expansion connector is provided on
the iRCB 44/1 OA board. This connector can be used
to extend the 1/0 capability of the board. In addition
to specialized and custom designed iSBX boards, a
fuJi line of compatible high speed, 8-bit expansion
MULTIMODULE boards, both single and double
wide, are available from Intel. The only incompatible
modules are those that require the MWAIT' Signal or
DMA operation. A few of .Intel's iRCB 44/10A board
compatible iSBX MULTIMODULE boards include:
parallel 1/0, serial 1/0, BITBUS expansion, IEEE
488 GPIB, analog input and analog output.
'
With the iSBX 344A BITBUS Controller MULTIMODULE board and user supplied software, the iRCB
44/10A board can act as an intelligent BITBUS repeater facilitating the transition between two BITBUS segments operating at different speeds.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iRCB 44/10A
board' includes many features, which make it well
suited for industrial control applications. Power up
diagnostics is just one of these features. Diagnostics
simplify system startup considerably, by immediately
indicating an iDCM ,controller or external bus failure.
The LEOs used for power up diagnostics are

Table 2. BITBUSTM Mlcrocontroller Interconnect Modes of Operation
Speed
Kb/s

Maximuin Distance
Between Repeaters
Mlft

Maximum # Nodes
Per Segment"

Maximum # Repeaters
Between A Master And
Any Slave

, Synchronous

500-2400

3Q/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment Distance between master and repeater or repeater and repeater. Synchronous mode requires user supplied crystal.

17-18

intJ

IRCB44/10A

available for user diagnostics after power up as well
to further contribute to reliable operation of the system.
Initial iRCB 44/10A board parameters are set by positioning jumpers. The jumpers determine the
BITBUS mode of operation: synchronous, self
clocked, transmission speed, and address of the
iRCB 44/10A board in the BITBUS system. This
minimizes the number of spare boards to be stocked
for multiple nodes, decreasing stocking inventory
and cost.

INTEGRAL FIRMWARE
The iRCB 44/10A board contains resident firmware
located in the 8044 BEM. The on-chip firmware consists of: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Controller (RAC) function that enables user communication and control of different microcontrollers and I/O
points; a communications gateway to connect the
BITBUS interconnect, iSBX bus, iPCX bus and iDCX
51 tasks; and power up diagnostics.

Table 3. IDCX 51 Executive Calls
Description

Call Name
TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
Obtain a message buffer from the system buffer pool.

RQ$ALLOCATE
RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

+5V

RESET'

OPEN
COLLECTOII

DATA
BUS - -......---1D
BIT

Qt-----i

X ) - -.....-

...- - I / O PORT PIN

WR'---+-----'

RD'---t-"----,

280213-4

Figure 3. I/O Port Structure

17-19

inter

iRCB44/10A

The iDCX 51 Executive is.an.event"driven software
manager that can respond to the needs of multiple
tasks. This real-time multitasking executive provides:
task management, timing, interrupt handling, and
message passing services. Table 3 shows the iDCX
51 calls. Both the Exe.cutive and the communications gateway allow for the addition of up to seven
user tasks at each node. while making BITBUS operation transparent.
The Remote Access and Control Function is a speCial purpose task that allows the user to transfer
commands and program variables to remote BIT-

BUS controllers, obtain the status of a remote 1/0
line(s),or reverse the state ofa remote 1/0 line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function.Power up tests provide a quick diagnostic serv- .
ice.
The services provided by the iRCB 44/10A board
integral firmware simplify the development and implementation' of complex real-time control' application systems. All iDCM hardware products contain
integral firmware thus supplying the user with a total
system solution.

Table 4. RAC Services
RACService
RESET_STATION
CREATE-TASK
DELETE-TASK
GET_FUNCTION_ID
RAC PROTECT
READ_IO.
.WRITE 10
UPDATE-IO
UPLOAD_MEMORY
DOWNLOAD

MEMORY

OR-I/O
AND 1/0
XOR_1I0

Action Taken by Task 0
Perform a soijwan:i reset.
Perform an RQ$CREATE$TASK system call.
Perform an RQ$DELETE$TASK system caJI.·
Perform an RQ$GET$FUNCTION$IDS call.
Suspend or resume RAC services.

Update the specified 1/0 ports.
Return the values in specified memory area.
. Write values to specified memory area.
OR values into specifi!;ld 1/0 ports.
AND values into specified 1/0 ports.

READ_INTERNAL

XOR values into specified 1/0 ports.
Read values at specified internal RAM areas. .

WRITE

Write "values at specified internal RAM areas.

INTERNAL

NODE-INFO
OFFLINE
UPLOAD_CODE
DOWNLOAD_CODE

Return values from specified 1/0 ports.
Write to the specified 1/0 ports.

Return device related information.
Set node offline.
. Readilalues from code memory space.
Write values to specified EEPRO"" memory.

17-20

inter

iReB 44/10A

mounting for one RCB 44/10A, with connectors for
power, the BITBUS interconnect signals, and 24 Industry Standard 1/0 isolation and signal conditioning
modules. These modules, available from a number
of vendors worldwide, typically provide greater than
1500V isolation and support signal conditioning in a
number of voltages including 5-60 VDC,120 and
240 VAC.

INDUSTRIAL PACKAGING
The iRCB 44/10A form factor is a single high, 220
mm deep Eurocard and supports most standard industrial packaging schemes as well as Intel's RCX
910 Digital Signal Conditioning, Isolation and Termination Module (see below). The Eurocard form factor specifies reliable DIN connectors. A standard 64
pin connector is included on the iRCB 44/10A
board.

SPECIFICATIONS

Physical Characteristics

Word Size

Single high, 220 mm deep Eurocard Form Factor

Instruction: 8 bits
Data:
8 bits

Dimensions
Width: 13.77 mm (0.542 in) maximum component
height

Processor Clock 12 MHz

Height: 100 mm (3.93 in.)
Depth: 220 mm (8.65 in.)
Weight: 169 gm (6 ounces)

Instruction Execution Times
1 p.sec 60% instructions
2 p.sec 40% instructions
4 p.sec Multiply & Divide

DIGITAL SIGNAL CONDITIONING,
ISOLATION, AND TERMINATION
The RCB 44/10A is fully compatible with the RCX
910 Digital Signal Conditioning, Isolation and Termination Panel. The RCX 910 panel provides integral

Memory CapacitylAddressing·
iDCM Controller: Up to 64 Kbytes code

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment for the iRCB 44/10A board.
BITBUSTM Development Environments
BITBUSTM TOOLS

DCS 100
TOOLBOX
Ql
C)

'0
.;::

ID
ID·

ii5

::l

ii5

,..
X

...,J:

·ID

0
0

C\I

15
::l

......
CI

11)

0
C

Series II

III
IV
iPDS
IRMX5%"

S"
XENIX5%"

S"
DOS

X
A
X
X
X
X
X

'A
X'
X
X
X
X

A
X
X

X
X
B
B
X

X
X
X
X
X

:::i

~
-I
Q.

.....

-I

X
X

en
<

Il:

X
X
X
X
X

D
D

D
D.

D
D

NOTES:
A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX. XENIX qisks not required.
C. Down-revision version.
D. Available for iRMX® 86.

17-21

EPROMPROG.

iii

ID
Q.

ICETM

NODE
CODE

en
0

"[jj

0
0..

co
0

...,

C\I

::>

;::

C\I
~

::2;

0
0

Series II

III
IV
iPDSTM
iRMX® 5%"

8"
XENIX5%"

8"
DOS

X
A
X
X
X
X
X

A
X
X
X
X
X

A
X
X

X
X

B
B
X

EPROM PROG.

CODE

X
X
X
X
X

co
::::;

::2;
....
...J

0..

u;
...J
cc

<=
._.'"

intJ

iRCB 44/20A

110 Capability

Stability

Analog-16 single-ended or 8 differential channels
and 2 outputs channels

Gain tempc0-32 ppmrc (gain = 11)
.75 ppmrc (gain = 500)
Offset tempco-100 microvoltsrC max.

Expansion-one single-or double-wide iSBX MULTIMODULE (MWAIT • or DMA not supported by iRCB
44/20)

Dynamic Performance

Two external: iSBX I/O Bus or BITBUS Interconnect
sources

Aggregate throughout-20 KHz (gain = 1, 10)
7.5 KHz (gain = 100,500)
Common mode rejection-70 dB (gain = 1)
100 dB (gain = 500)
AID conversion time-30 microseconds

Bus Termination

Analog Output Specifications

Jumper selectable resistors provide termination capability for cable with an impedance of 1200. or
greater.

Number of channels-2
Output ranges-O to 5V, 0 to 10V (unipolar) ±5V,
± 10V (bipolar)
Current-loop range-4 to 20 mA (unipolar mode
only)
Output impedance-O.2n min. (voltage)
5 Mn max. (current)
Output current- ± 5 mA (short-circuit protected)

Interrupt Sources

Analog Input Specifications
Number of channels-16 single-ended or 8 differential
Input ranges-O to 5V, 0 to 10V (unipolar) ±5V,
± 1OV (bipolar)
Gain ranges-1, 10, 100, 500, (software programmable)
Input impedance-100Mn
Input bias current-±50 nA
Overvoltage protection- ± 32V power on
± 20V power off

Accuracy
Resolution-12 bits
Linearity and Noise-±% LSB (trimmable)
System Accuracy
Gain = 1-±0.035% full-scale range (trimmable)
Gain = 500-±0.15% full-scale range (trimmable)

Accuracy
Resolution-12 bits
Linearity and Noise-±o/4 SB (trimmable)
System AccuracyGain = 1--0.35% full-scale range (trimmable)
Gain = 500-±0.15% full-scale range (trimmable)

Stability
Full-scale temperature coefficient
150 microvoltsl"C (unipolar)
300 microvolts/oC (bipolar)
0.6 microampsl"C (current-loop)
Offset temperature coefficient
30 microvolts/oC (unipolar)
180 microvoltsl"C (bipolar)
0.3 microamps/oC (current-loop)

Mating Connectors
Function
BITBUS
Connector

iSBX
Connector

# of Pins

Type

Vendor

Part Number

Flat Cable

GWElco
Robinson Nugent

00-8259-096-84-124
RNE-IDC-64C-TG30

Wire Wrap

ITICannon
GWElco

G06 M96 P3 BDBL-004
6082573017

Solder

Viking

000292-0001

17-30

IRCB44/20A

Dynamic Performance

Physical Characteristics

Aggregate throughput-20 KHz (gain = 1, 10)
7.5 KHz (gain = 100, 500)
Settling Time-15 microseconds to ±% LSB

Width:

Electrical Characteristics

Weight: 169 gm (6 ounces)

Interface Compliance

Environmental Characteristics

iSBX BUS (through level DB/BF):
Memory sites-code and data sites are JEDEC
compatible

Operating Temperature: O'C to + 60'C at O.B CFM
air volume
90% non-condensing
Relative Humidity:

3.77 mm (0.542 in) maximum component
height
Height: 100 mm (3.93 in)
Depth:

220 mm (B.65 in)

BITBUS:
-

Synchronous and self-clocked mode support for
500 Kbps to 2.4 Mbps, 375K and 62.5K bits/sec

Reference Manual (Not Supplied)
148816- iRCB 44/20A Hardware Reference

NOTE:
On-board ALE clock supports 1 Mbps synchronous
operation. All other synchronous mode speeds require user-supplied 2.0-9.6 MHz crystal.
-

Equivalent to 1.1 standard (RS 4B5) loads

Message length up to 54 bytes maximum

Manual

ORDERING INFORMATION
Part Number Description
iRCB 44/20A BITBUS Analog I/O Controller Board

Power Requirement (exclusive of optional
memory oriSBX MULTI MODULE)
Voltage

Current (amps)

+5V #5%
+12V ±5%
-12V ±5%

0.9 max. 0.7 typ
100 mA max.
100 mA max.

Max,Power
(watts)
4.5

NOTE:

+ 15V and -15V required for 0 to 10V and ± 1OV ranges;
for ±15Voperation, the iRCB 44/20A cannot be used with
ISBX MULTIMODULES that use ±12V power sources.

17-31

intJ

DCS100 BITBUSTM TOOLBOX
HOST SOFTWARE UTILITIES

•

Six Utilities Simplify Development of
Host Software for Controlling
BITBUSTM-Based Systems

•

Includes the BITBUSTM Monitor Which
Provides On-Line Monitoring and
Control of a BITBUSTM System

Universal BITBUSTM Interface and
BITBUSTM Interface Handler Libraries
Provide 32 Syste~ Managementl
Control Procedure

•

Compatible with Intel's C, PL/M and
ASM Languages

Reliable and Easy to Use

•

For DOS~ iRMX® 86/286, XENIX·, and
iPDSTM Host Systems

The BITBUS Toolbox provides a set of utilities designed to simplify developmentaf host system software for
controlling a BITBUS netWork. The Toolbox includes: two Ijbraries of procedures that can be called from the
host code; an on-line program called the BITBUS Monitor which is invaluable for troubleshooting, monitoring,
and manually controlling a system; and code conversion/communication software to support applications
software development on a PC.
.
,
The procedure libraries contain common procedures used by the host to read or write data to remote node I/O
ports, download or upload programs and data, start and stop tasks (program modules) runl1ingon the nodes,
send and receive messages, and perform a variety of system status and contro) functions: By 'using these
libraries, the programmer's task of generating BITBUS host code is substantially reduced.

280732-1

··IBM, XT and AT are trademarks of International Business Machines Corporation.
·XENIX is a trademark of Microsoft Corporation.

17-32

October 1987
Order Number: 280732-001

inter

DCS100

THE BITBUSTM TOOLBOX-PRODUCT
DESCRIPTION
The BITBUS Toolbox is used to develop host code
for controlling a BITBUS network, and is an essential
tool for both centralized and distributed control applications.
With centralized control, the host code sends commands to a node to read and update the I/O. All the
decisions are made at the host. Normally, this kind
of system would require extensive host code. However, the Toolbox includes the UBI and BIH procedure libraries that can be called to perform simple or
complex control procedures.
In addition to the Toolbox, all BITBUS boards include, in firmware, a set of procedures known as

Remote Access and Control (RAG). By sending simple messages to these procedures, basic I/O functions can be performed. The RAC procedures are
listed in Table 1.
With distributed control systems, programs run on
the remote BITBUS boards (nodes) and offload the
host system of most decision making responsibilities. Using UBI calls or the BITBUS Monitor, commands can be sent to the nodes to control tasks or
to periodically upload data for further analysis or
storage. The software tools in the BITBUS Toolbox
reduce the time and effort necessary to develop
host code for these applications.
In addition to the DCS100 BITBUS Toolbox, other
host code tools include a full set of host software
compilers, libraries, debuggers, and in-Circuit .emulators. The BITBUS Toolbox is described in detail in
the sections that follow.

Table 1. Remote Access and Control Procedures
Name

Function

RESET_STATION

Perform a software reset.

CREATE_TASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROTECT

Suspend or resume RAC services.

READ_I/O

Return values from specified I/O ports.

WRITE_I/O

Write to the specified I/O ports.

UPDATE_I/O

Update the specified I/O ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY

Write values to specified memory area.

OR_IO

OR values into specified I/O ports.

AND_IO

AND values into specified I/O ports.

XOR_IO

XOR values into specified I/O ports.

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values to specified internal RAM areas.

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD_CODE

Write values to specified EEPROM memory.

17-33

intJ

DCS100

The DCS100 BITBUS Toolbox includes six hostsoftware utilities. They include:

• OBJHEX Conversion Utility-Converts an object
file to hex format for downloading code.
• UDl2DOS-Converts Intel object code programs
to .exe format for execution on the PC.

• Universal BITBUS Interface (UBI)-a set of 28
procedures for implementing remote I/O and
controlling a BITBUS network.

Universal BITBUSTM Interface

BITBUSTM TOOLBOX UTILITIES

• BITBUS Interface Handlers (BIH)-four basic
procedures for sending/receiving messages over
a BITBUS network.
• BITBUS Monitor (BBM)-An on-line program with
36 commands that enable a user to configure,
troubleshoot, monitor, .and manually control a
BITBUS network.

UBI is a library of 28 procedures called by the host
program to manage the I/O, download or upload
code and data, manage tasks on a node, send and
receive messages, and perform an assortment of
miscellaneous functions. These procedures are listed in Table 2, below..

• PC Bridge-Communications program for the PC
to support software d,eveloptnent on a PC and
download into an iRMX or XENIX-hosted BITBUS
network.
Table 2. UBI Procedure Calls

I/O
BQ$AND$I/O
BQ$OR$I/O
BQ$XOR$I/O
BQ$WRITE$I/O
BQ$READ$I/O
BQ$UPDATE$I/O

AND I/O
OR I/O
Excl. OR I/O
Write I/O
Read I/O
Write 110 and read back

MEMORY MANAGEMENT

BQ$ABS$LOAD
BQ$WRITE$CODE$MEM
BQ$READ$CODE$MEM
BQ$WRITE$INT$MEM
BQ$READ$INT$MEM
BQ$WRITE$EXT$MEM
BQ$READ$EXT$MEM

Download program to code memory
Write to code memory
Read code memory
Write to internal data memory
Read internal data memory
.
Write to external data memory
Read external data memory

TASK MANAGEMENT

BQ$CREATE$TASK
BQ$DELETE$TASK
BQ$GET$FUNCTION$IDS

Create task
Delete task
Read task function IDs

MESSAGE MANAGEMENT

BQ$FLUSH
BQ$RECEIVE$MESSAGE
BQ$SEND$MESSAGE

Clear an iSBX/iPCX interface
Receive a message
Send a message

17-34

inter

DCS100

Table 2. UBI Procedure Calls (Continued)
MISCELLANEOUS CALLS

BO$DELAY
BO$NODE$INFO
BO$PROBE$SBX
BO$PROTECT$RAC
BO$RESET$DEVICE
BO$RESYNC$NODE
BO$SET$PORT
BO$SET$SBX
BO$SHELL

Perform a time delay
Return node information
Check for BITBUS iSBX board
Lockout (protect) a node
Initiate a software reset
Set a node offline, prep. to resync
Set port 1/0 address
Set port 1/0 address
Shell escape and then return

The UBI utility includes libraries interfacing with
PL/M and C host code running within DOS, iRMX,
and XENIX environments. Also included are declaration files for the procedures.

READ or UPLOAD procedures) together with an error code. These error codes can help the host system take corrective action.

To use these procedures, the UBI calls are incorporated into the source code modules together with
parameters needed by the procedures (e.g. node
address, port address, memory location, task number, and data). The source module and UBI declaration files are then compiled and linked with the UBI
library.
..

BITBUSTM Interface Handlers (BIH)

When the call executes, the called procedure will be
performed, data will be returned (in the case of

BIH is a library of four basic procedures for sending
and receiving messages between the host and network nodes. These procedures, listed in Table 3, are
most useful when generating custom UBI-like procedures. The BIH utility includes procedure libraries
and declaration files for DOS, iRMX 86/88/286, and
ISIS-PDS (iPDS)-based systems.

Table 3. BIH Procedure Calls

Call Name
CO$DCM$INIT
CO$DCM$RECEIVE
CO$DCM$STATUS$CHECK
CO$DCM$TRANSMIT

Description

Performs any initialization required by the
BITBUS Interface Handlers.
Receives one message from any BITBUS
node.
Determines whether a BITBUS message
is available to receive.
Transmits one message to any BITBUS
node.

17-35

inter

DCS100

To use these libraries, the appropriate decl~ration
file is included with the host source code. The modules are then compiled and the resultant object
module is linked to the BIH library.
.

BITBUSTM Monitor
The BITBUS Monitor (BBM) is an on-line program
that is invaluable for troubleshooting and testing a
BITBUS system and can also be used to manually
control a system. BBM commands are listed in
Table 4.

Table 4. BITBUSTM Monitor Commands
MESSAGE MANAGEMENT

I/O
AIO
010
RIO
UIO
WIO
XIO

And I/O
Or I/O
Read 1/0
Update I/O
Write to I/O
Exclusive OR I/O

MEMORY MANAGEMENT
LOAD
RCMEM
RIMEM
RXMEM
WCMEM·
WIMEM
WXMEM

Download to code memory
Read code memory
Read internal memory
Read data memory
Write to code memory
Write to internal memory
Write to data memory

TASK MANAGEMENT
CTASK
DTASK
SYS

Create a task
Delete a task
Display node task status

DMSG
RMSG
SMSG
TMSG

Display a message
Receive .a message
Send a message
Sends, receives, displays a message

MISCELLANEOUS COMMANDS
DELAY·
EXIT
FLUSH
HELP
INCLUDE
LIST
LOCK
NODEINFO
PAUSE
RESET
RESYNC
SETPORT/
SETSBX
SHELL
SYMBOLS
UNLOCK
VERBOSE

17-36

Suspend Activity
ExitBBM
..
Clears an iSBX/iPCX interface
Provide on-line help
Open/execute a BBM file
Creates a copy of the BBM session.
Lqckout (protect) a node
Node information
Wait until
SW reset at a node
Set a node offline
Set port I/O address
XENIX/DOS shell escape from BBM
Display/create/change the value of
a user symbol.
Unprotect
Controls echo and prompts

inter

DCS100

I/O ACCESS

Six commands are provided for writing to and reading from I/O ports on remote nodes. With these
commands, an operator can test the I/O connected
to a BITBUS node or monitor the status of an input
port. The I/O commands allow an operator to quickly isolate a problem at a remote node.
MEMORY ACCESS

each node. The task management commands are
especially useful when developing/troubleshooting
multitasking control programs.
MESSAGE OPERATIONS

These four commands are used to send and receive
messages to and from tasks on remote nodes.
MISCELLANEOUS COMMANDS

Seven memory access commands are provided.
These commands allow the operator to download
and upload both code (programs) and data (variables) between the host system and remote BITBUS
nodes. Internal RAM memory within the 8044BEM
microcontroller can also be accessed. In addition,
the BBM supports code download to both static
RAM and E2PROM devices. The memory access
commands are especially useful for on-target application development.
The BITBUS Monitor enables the user to reference
a memory location by using a symbolic reference or
label. For example, if a task running on a node includes a program variable called "rate", the operator can modify this variable simply by typing:

The BBM includes 15 comniands that are used to
control the operating status of nodes, and to support
various troubleshooting functions. These. commands
include:
The HELP command-an on-line facility that displays the complete BBM command directory or detailed information on using the commands.
The SHELL command.,-allows an operator to do a
shell escape to DOS or XENIX, perform the needed
operating system function, and return to the monitor.
The RESET, FLUSH, and RESYNC commands-'used to clear a node that is hung.

WlMEM .rate 6CH

OPERATING ENVIRONMENT

In this case, the program will execute with a value of
6C hex for "rate".

The BITBUS Monitor will run on DOS, iRMX 86/286,
XENIX and iPDS-based systems. Both 5%" and 8"
media is provided for iRMX and XENIX systems. The
iPDS version of the monitor does not include the
following BBM commands (or equivalent UBI calls):
DELAY, LIST, PAUSE, RCMEM, RESYSC, SETPORT, SYMBOLS, TMSG, VERBOSE, WCMEM.

Symbolic references can also be used for other
BBM parameters, such as node address, port ad. dress, and data. Symbolic access allows the user to
more easily test and modify programs at run time.
TASK MANAGEMENT

PC Bridge

Four commands are available to monitor and control
the running of tasks on the nodes.
The DCX 51 real time multitasking executive found
on all BITBUS boards can support up to 7 user tasks
(in addition to the RAC task). Each of these tasks
have an initial Task Descriptor (ITO) which assigns a
function 10 to the task plus other important run-time
parameters used by the executive. By chaining ITDs
together, multiple tasks can become active upon
power up.

The PC Bridge is a communications program .that
runs on a PC-DOS or MS-DOS system, and is used
to establish a communication link between the PC
and an Intel iRMX 86/286 or XENIX-based microcomputer system. The software engineer can use
the Bridge in two ways. First, he can develop host or
node programs on the PC and download the code to
the host system or remote nodes. He can also use
the PC as a virtual terminal to the host system. The
PC Bridge effectively expands the development environment for the software engineer.

The BBM commands allow tasks to selectively be
made active (CTASK) or inactive (DTASK). In addition; the SYS command can be used to display
which nodes are present and operational in a system and display the function IDs for active tasks on

The link between the PC and the host microcomputer can either be over an RS232 cable (supplied) or
via a modem link. The PC Bridge transfers data at up
to 19.2K baud (asynchronous) and supports
XON/XOFF flow control.

17-37

inter

DCS100

OBJHEX

Documentation (supplied)

OBJHEX is an object code to hex code conversion
utility similar to the OH51 hex converter supplied
with Intel "8051" languages. OBJHEX has the additional ability to retain the object module's symbol table during the conversion process. The table is
stored at the host system and enables the BITBUS
Monitor to symbolically access program memory.
OBJHEX runs on both DOS and iRMX86 (5%" , 8"
medial-based systems.

BITBUS Toolbox Overview and
Installation Guide
BITBUS Monitor User's Guide
Universal BITBUS Interface
User's Guide
BITBUS Interface Handlers User's
Guide
PC Bridge Communications Utility
User's Guide
BITBUS OBJHEX Conversion Utility
User's Guide

UDI2DOS
UDI2DOS converts Intel object code (8086 OMF) to
the .exe format so that it will run within a DOS environment.

Series II
III
IV
IPDS
IRMXS%"

8"
XENIXS%"

8"
DOS

iii
~

:z:

iii

III

DolO

X
X
B
B
X

X
X
·X
X
X

GI
til
"CI
C)'I:

:z:
...,

Q
N

X
A
X
X
X
X
X

148685-002
149236-001
460237-001

Compatible Software

Order Codes

Media Provided

::Ii

460236-001

Intel ASM, PLlM, and C languages
(8086/80286/80386 versions)

SPECIFICATIONS

10
10

460235-001
148686-002

A
X
X

X
X
X

Order Number Description
DCS100SU
BITBUS Toolbox Host Software
Utilities, single-use license for development only. Includes RS232
cables to connect an Intel microcomputer system with an IBM'
PC-XT" or PC-AT", and full documentation. See above for media
provided.
BITBUS Toolbox Host Software
DCS100BY
Utilities. Same as above, except
sold with a buyout license. Allows
incorporation of UBI and BIH procedure libraries-no additional incorporation fee is required.

NOTES:
A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX. XENIX disks not required.

17-38

inter

DCS110 BITWARE
DCS120PROGRAMMERSSUPPORTPACKAGE

•

Supports Calls to the 8044BEM
Microcontroller On-Chip, Multitasking
DCX 51 Executive

•

Fully Compatible with Intel's ASM51
and PL/M51 Languages

•

DCS110 also Includes DCM44 Code to
Support Emulation/Debug of BITBUSTM
Node Code using Intel In-Circuit
Emulators

•

For DOS, iRMX®, iPDSTM, and Series
III/IV Development Environments

The DCS110 and DCS120 packages are designed to support software development of distributed control
BITBUS applications. Both products include a DCX51 interface library so that BITBUS application programs
can make calls to the PCX51 Executive. DCS110 also includes a DCM44 downloadable file that enables an
Intel in-circuit emulator such as the ICETM 5100/044 to emulate a BITBUS environment. By using an in-circuit
emulator together with DCS11 0, the developer can easily and quickly debug BITBUS application code.

280731-1

17-39

October 1987
Order Number: 280731-001

inter

DCS110/DCS120

DCX 51 ENVIRONMENT
The 8044BEM microcontroller, used on every
BITBUS board, includes in firmware a preconfigured
version of the DCX 51 Executive. DCX 51 provides a
variety of services to the application code, including:
task management; interrupt management; inter-task
communications; memory management; and timing
'services. Up to 7 l'Jser tasks can run concurrently
under DCX 51. Each,task has a unique Initial Task
Descriptor (ITO) that describes to the executive several run-time parameters (e.g. stack space, priority
level, etc.). By also specifying an Initial Data De-

scriptor (100), the executive can be partially reconfigured. Modifiable run-time constants include the
system clock rate, clock priority, internal memory
buffer size; and user (internal) memory size. DCX 51
calls are listed in Table 1.
By running applications under DCX 51, the designer
can make optimal use of the 8044BEM microcontroller. If a task needs to waitfor a message, an interrupt, or a time period, DCX 51 will temporarily assign
acc,ess to the 8044 to another task. In this way, mUltiple tasks can access the microcontroller.

Table 1. DCX 51 Procedure Calls:
Call Name

Description

Task Management Calls
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

Intertask Communication Calls
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Re~urn

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

a message buffer to the system buffer pool.

Memory Management Calls
RQ$GET$MEM

Get available memory from the system memory pool.

RQ$RELEASE$MEM

Release memory to the system memory pool.

Interrupt Management Calls
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ!SWAIT

Wait for an interrupt event.

Timer Management Calls
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

17-40

inter

OCS110/0CS120

Interfacing to the DeX 51 Executive
To interface with the executive, DCS110 and
DCS120 both include a DCX 51 interface library plus
a set of "include" files. The interface library, which is
linked to the application modules, allow the code to
access DCX 51 procedures. The "include" files consist of DCX 51 declaration and macro definition files
that help 'simplify source code development. These
files are listed in Table 2.

Des 11 0 Bitware Software Package
In addition to the DCX 51 interface files, DCS110
also includes a DCM44 object file to support debug
of node code using an Intel in-circuit emulator.
DCM44 is the firmware found in all 8044BEM
BITBUS microcontrollers and together with an Intel

in-circuit emulator, successfully duplicates the
8044BEM environment. Emulators that are supported include the ICETM 5100/044, the ICE 44, and the
EMV 44.

Developing Applications Software
Using DCS110 or DCS120 software to develop
BITBUS applications software is a straightforward,
multi-step process as diagrammed in Figure 1. The
designer uses a text editor to write the application
code either in ASM 51 or PL/M 51. The source code
modules are then assembled/compiled along with
the DCX 51 "include" files. The final step is to link
together all of the modules, the OCX 51 interface
library, and the DCM441.LlB file. The linked/located
absolute object module can then be downloaded to
the target board or burned into EPROM.

Table 2. DCS110/120 Files
Filename

Description

DCX 51 Support Files:
OCX51 I. LIB

Interface library to the DCX 51 executive. Provides the linker with the address of data
variables and entry points for DCX51 procedures called from other object modules.

DCX51 A. EXT
DCX51A.LlT
DCX51P.LlT

External and literal declaration files. These files sLipport DCX 51 calls from ASM 51
and PL/M 51 code.

DCXBOP.EXT
OCXB1P.EXT
DCXB2P.EXT
DCXB3P.EXT

DCX 51 External procedure declarations for PL/M 51 modules using 8044 register
banks 0, 1, 2 or 3.

DCX51A.MAC

Initial Task Descriptor (ITO) and Initial Data Descriptor (100) macro definitions.

APPL1.A51
APPL2.A51

Sample application, parts 1 and 2; template for generating ITDs and 100.

DCM441.LlB

This file maps out reserved memory needed by the 8044BEMfirmware and is linked
to other user object modules using the RL51 Linker.

DCM44 Firmware Flies (DCS110 Only):
DCM44

DCM44 (BITBUS) code for InteIICETM/EMVemulators.

17-41

inter

DCS110/DCS120

WRITE
SOURCE CODE

COMPILE/
ASSEMBLE

LINK

LOAD/EXECUTE

LEGEND:

FILE

(

DCS 110/120 FILE

)

SOFTWARE TOOL

DCS 110 ONLY
280731-2

Figure 1. DCS 11 0/120 Software Development Environment

DCS120BY

Development Environments
Both DCS110 and DCS120 are shipped with media
to support software development on PC/MS·DOS,
iRMX 86, iPDS, and Intellec@ Series III/IV systems.
DCS110 is available with a single-use license for application development and debug. Designers planning to incorporte DCX 51 files in their application
should purchase the DCS120 "buyout" product.
Order Codes Description

DCS110SU

Bitware Software Package. Includes
DCM44 code to emulate a BITBUS
environment when using an Intel incircuit emulator and interface files to
support procedure calls to DCX 51.
Provided with documentation and
PC-DOS, iRMX 86 (5%" , 8"), iPDS,
and Series III/IV media. Single-use
license.

Programmers Support Package. Includes interface files to support procedure calls to DCX 51. Provided
with documentation and PC-DOS,
iRMX 86 (5%" , 8"), iPDS, and Series III/IV media. Buyout license allows incorporation of software into
product-no additional incorporation
fee is required.

COMPATIBLE SOFTWARE TOOLS

DCS100

AEDIT

'XENIX is a trademark of Microsoft Corp.

17-42

BITBUS Toolbox Host Software Utilities for PC/MS-DOS, iRMX 86/286,
XENIX·, iPDS, and Series III/IV host
systems.
Source Code and Text Editor for all
Intel host environments (consult
data sheet for order codes).

DCS110/DCS120

8051 LANGUAGES

(Note: All products also include RL51 Linker/Relocator, LlB51 Librarian, and OH51 object to hex code
converter)
D86ASM51
ASM 51 Assembler for PCDOS host system
R86ASM51
ASM 51 Assembler for iRMX
86 host system
186ASM51
ASM 51 Assembler for Series
III/IV host systems
MC151ASM
ASM 51 Assembler for iPDS
and Series II host systems
PL/M 51 Compiler for PC-DOS
D86PLM51
host system
R86PLM51
PL/M 51 Compiler for IRMX 86
host system
186PLM51
PL/M 51 Compiler for Series
III/IV host systems
PLIM 51 Compiler for iPDS and
iMDX352
Series II host systems

IN-CIRCUIT EMULATORS AND PROM
PROGRAMMERS

(Note: + indicates that the product is no longer
available)
In-Circuit Emulator for the RUICE51 00/044
PITM-44 Family (hosted on PCDOS, and Series IIIIIV-see
data sheet for order codes)
8044 In-Circuit Emulator (hostICE-44+
ed on Series II-IV systems)
iPDSEMV44CON + Kit to add 8044 support to an
EMV-51/51A emulator .(iPDS
host)
Universal PROM programmer
iUP-200A,
iUP-201A
(hosted on PC-DOS, iPDS, and
Series III/IV; see data sheet for
order codes)

17-43

inter
8051
SOFTWARE PACKAGES
• Choice of hosts:
PCDOS 3.0 based IBM* PC XT/AT*,
iRMX@86, iPDSTM System, Series II,
Series III, and Series IV
• Supports all members of the Intel
MCS@ -51 architecture

• LlB51 Librarian which lets
programmers create and maintain
libraries of software object modules
8051 Software Development Package
Contains the following:

PL/M51 Software Package Contains the
following:

• 8051 Macro Assembler which gives
symbolic access to 8051 hardware
features ..
.

• PL/M51 Compiler which is designed to
support all phases of software
implementation

• RL51 Linker and Relocator program
which links modules generated by .the
. assembler

• RL51 Linker and Relocator which
enables programmers to develop
software in a modular fashion

• .L1B51 Librarian which lets
programmers create and maintain
libraries of software object modules

LEGEND

O
10----:
l;_ .. _J

INTEL DEYELDPiIIENT

TOOLS AND OTHER
PR0DUCT8
MCS--51
SOFTWARETOOLS

USER-CODED
SOFTWARE

162771-1

Figure 1. MCS® -51 Program Development Process

'IBM and AT are registered trademarks of International Business Machine Corporation.

17-44

October 1987
Order Number: 162771·005

intJ

8051 Software Packages

PL/M 51 SOFTWARE PACKAGE
High-level programming language for
• the
Intel MCS® -51 single-chip
microcomputer family

•
•
•
•

Compatible with PL/M 80 assuring
MCS® -80/85 design portability
Enhanced to support boolean
processing
Tailored to provide an optimum
balance among on-chip RAM usage,
code size and code execution time
Produces relocatable object code
which is linkable to object modules
generated by all other 8051 translators

•
•
•

Allows programmer to have complete
control of microcomputer resources
Extends high-level language
programming advantages to
microcontroller software development
Improved reliability, lower maintenance
costs, increased programmer
productivity and software portability

•
• MCS®

Includes the linking and relocating
utility and the library manager

Supports all members of the Intel
-51 architecture

PL/M 51 is a structured, high-level programming language for the Intel MCS-51 family of microcomputers. The
PL/M 51 language and compiler have been designed to support the unique software development requirements of the single-chip microcomputer environment. The PL/M language has been enhanced to support
Boolean processing and efficient access to the microcomputer functions. New compiler controls allow the
programmer complete control over what microcomputer resources are used by PLiM programs.
PL/M 51 is largely compatible with PL/M 80 and PLiM 86. A significant proportion of existing PLiM software
can be ported to the MCS-51 with modifications to support the MCS-51 architecture. Existing PL/M programmers can start programming for the MCS-51 with a small relearning effort.
PLiM 51 is the high-level alternative to assembly language programming for the MCS-51. When code size and
code execution speed are not critical factors, PL/M 51 is the cost-effective approach to developing reliable,
maintainable software.
The PL/M 51 compiler has been designed to support efficiently all phases of software implementation with
features like a syntax checker, multiple levels of optimization, cross-reference generation and debug record
generation.
ICETM 5100, ICE 51, and EMV51 are available for on-target debugging.
Software available for PC DOS 3.0 based IBM' PC XT/AT* Systems.

LEGEND

INTEl DEVELOPMENT

TOOLS AND OTHER
PRODUCTS
MCS"'·51

SOf'lWAAE TOOLS

USER-COOED
SOFTWAfIE

162771-2

Figure 2. PL/M51 Software Package

17-45

8051 Software Packages

PL/M 51 COMPILER
FEATURES

Interrupt Handling

Major features of the Intel PL/M 51 compiler and
programming language include:

A procedure may be defined with the INTERRUPT
attribute. The compiler will generate code to save
and restore the processor status, for execution of
the user-defined interrupt handler routines.

Structured Programming
PL/M source code is developed in a series of modules, procedures, and blocks .. Encouraging program
modularity in this manner makes programs more
readable, and easier to maintain and debug. The
language becomes more flexible, by clearly defining
the scope of user variables (local to a private procedure, for example).

Compiler Controls
The PL/M 51 compiler offers controls that facilitate
such features as:
-

Language Compatibility
PLIM 51 object modules are compatible with object
modules generated by all other MCS-51 translators.
This means that PL/M programs may be linked to
programs written in any other MCS-51 language.

Including additional PL/M 51 source files from
disk
Cross-reference
Corresponding assembly language code in the
listing file

Program Addressing Control

Object modules are compatible with In-Circuit Emulators and Emulation Vehicles for MCS-51 processors: the DEBUG compiler control provides these
tools with symbolic debugging capabilities.

The PL/M 51 compiler takes full advantage of program addressing with the ROM (SMALLIMEDIUMI
LARGE) control. Programs with less than 2 KB code
space can use the SMALL or MEDIUM option to
generate optimum addressing instructions. Larger
programs can address over the full 64 KB range.

Supports Three Data Types

Code Optimization

PLIM makes use of three data types for various applications. These data types range from one to sixteen bits and facilitate various arithmetic, logic, and
address functions:

The PL/M 51 compiler offers four levels of optimization for significantly reducing overall program size.

Bit: a binary digit
Byte: a-bit unsigned number or,
Word: 16-bit unsigned number.

Another powerful facility allows the use of BASED
variables that map more than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.

Two Data Structuring Facilities
PL/M 51 supports two data structuring facilities.
These add flexibility to the referencing of data stored
in large groups.
-

Array: Indexed list of same type data elements

Structure: Named collection of same or different
type data elements

Combinations of Both: Arrays of structures or
structures of arrays.

Combination or "folding" of constant expressions; "Strength reductions" (a shift left rather
than multiply by 2)

Machine code optimizations; elimination of superfluous branches

Automatic overlaying of on-chip RAM variables

Error Checking
The PL/M 51 compiler has a very powerful feature
to speed up compilations. If a syntax or program error is detected, the compiler will skip the code generation and optimization passes. This usually yields
a 2X performance increase for compilation of programs with errors.
A fully detailed set of programming and compilation
error messages is provided by the compiler and user's guide.
'

17-46

8051 Software Packages

BENEFITS

Lower Development Cost

PLIM 51 is designed to be an efficient, cost-effective solution to the special requirements of MCS-51
Microsystem Software Development, as illustrated
by the following benefits of PL/M use:

Increases in programmer productivity translate immediately into lower software development costs
because less programming resources are required
for a given programmed function.

Low Learning Effort

Increased Reliability

PLIM 51 is easy to learn and to use, even for the
novice programmer.

PLIM 51 is designed to aid in the development of
reliable software (PL/M programs are simple statements of the program algorithm). This substantially
reduces the risk of costly correction of errors in systems that have already reached full production
status, as the more simply stated the program is, the
more likely it is to perform its intended function.

Earlier Project Completion
Critical projects are completed much earlier than
otherwise possible because PL/M 51, a structured
high-level language, increases programmer productivity.

Easier Enhancements and
Maintenance
Programs written in PL/M tend to be self-documenting, thus easier to read and understand. This means
it is easier to enhance and maintain PL/M programs
as the system capabilities expand and future products are developed.

RL51 LINKER AND RELOCATOR
•

Links modules generated by the
assembler and the PL/M compiler

•

Locates the linked object to absolute
memory locations

•

Enables modular programming of
software-efficient program
development

•

Modular programs are easy to
understand, maintainable and reliable

The MCS-51 linker and relocator (RL51) is a utility which enables MCS-51 programmers to develop software in
a modular fashion. The utility resolves all references between modules and assigns absolute memory locations to all the relocatable segments, combining relocatable partial segments with the same name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The total number of allowed symbols in user-developed software is very large because the assembler number
of symbols' limit applies only per module, not to the entire program. Therefore programs can be more readable
and better documented. RL51 can be invoked either manually or through a batch file for improved productivity.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
maintained.
RL51 produces two files. The absolute object module file can be directly executed by the MeS-51 family. The
listing file shows the results of the Iink/locate process.

17-47

8051 Software Packages

call only object modules that are required to satisfy
external references.
Consequently, the librarian enables the customer to
port and reuse software on different projects-thereby maintaining the customer's software investment.

ORDERING INFORMATION

Order Code

Operating Environment

D86PLM51

PL/M51 Software for PC DOS 3.0 Systems

R86PLM51

PLlM51 Software for iRMX 86 Systems

Documentation Package

SUPPORT:

PL/M 51 User's Guide

Hotline Telephone Support, Software Performance
Report (SPR), Software Updates, Technical Reports, and monthly Technical Newsletters are available.

MCS-51 Utilities User's Guide

17-48

intJ

8051 Software Packages

8051 SOFTWARE DEVELOPMENT PACKAGE
• Symbolic relocatable assembly
language programming for 8051
microcontrollers
• Extends Intellec® Microcomputer
Development System to support 8051
program development
• Produces Relocatable Object Code
which is linkable to other 8051 Object
Modules

• Encourage modular program design for
maintainability and reliability
• Macro Assembler features conditional
assembly and macro capabilities
• Supports all members of the Intel
MCS® 51 architecture

The 8051 software development package provides development system support for the powerful 8051 family
of single chip microcomputers. The package contains a symbolic macro assembler and relocation/linkage
utilities.
The assembler produces relocatable object modules from 8051 macro assembly language instructions. The
object code modules can be linked and located to absolute memory locations. This absolute object code may
be used to program. the 8751 EPROM version of the chip. The assembler output may also be debugged using
the new family of ICE 5100 emulators or with the ICE-51TM in-circuit emulator.
.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide software compatibility between the two families of microcontroUers.
Software available for PC DOS 3.0 based IBM' PC XT/AT Systems.

162771-3

17-49

infef

8051 Software Packages

8051 MACRO ASSEMBLER

•
•
•

Supports-8051 family program
development on Intellec®
Microcomputer Development Systems
Gives symbolic access to powerful
8051 hardware features
Produces object file, listing file and
error diagnostics

•
•
•

Object files are linkable and locatable
Provides software support for many
addressing and data allocation
capabilities
Symbolic Assembler supports symbol
table, cross-reference, macro
capabilities, and conditional assembly

The 8051 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language modules into linkable and locatable object code modules. Assembly language mnemonics are easier to program and are more
readable than binary or hexadecimal machine instructions. By allowing the programmer to give symbolic
names to memory locations rather than absolute addresses, software design and debug are performed more
quickly and reliably. Furthermore, since ,modules are linkable and relocatable, the programmer can do his
software in modular fashion. This makes programs easy to understand; maintainable and reliable.
The assembler 'supports macro definitions and calls. This is a convenient way to program -a frequently used
code sequence only once. The assembler also provides conditional assembly capabilities.
Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was
defined and referenced.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These
features include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic.
The assembler also provides symbolic access to hardware registers, 1/0 ports, control bits, and RAM addresses. ASM51 can support all members of the 8051 family.
Math routines are enhanced by the MUltiply and DIVide instructions. '
If an 8051 'program contains errors, the assembler provides a comprehensive set of error diagnostics, which
are included in the assembly listing or on another file. Program testing may be performed by using the iUP
Universal Programmer and iUP F87/51 personality module to program the 8751 EPROM version of the chip.
ICE 5100,ICE51 and EMV51 are available for program debugging.

,RL51 LINKER AND, RELOCATORPROGRAM
•

Links modules generated by theassembler

•

Locates the linked object to absolute ,_
memory locations

•

Enables modular programming of
software for efficient program
development

•

Modular programs are easy to
understand, maintainable and reliable

The 8051 linker and relocator(RL51) is a utility which enables 8051 programmers to develop software in a
modular fashion. The linker resolves all references between modules and the relocator assigns absolute
memory locations to all the relocatable segments, combining relocatable partial segments with the same
name.
With this utility, software can be developed more quickly bacause small functional modules are easier to
understand, design and test than large programs.
The number of symbols in the software is very large because the assembler symbol limit applies -only per
module not the entire program. Therefore programs can be more readable and better documented.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
maintained.
17-50

intJ

8051 Software Packages

RL51 produces two files. The absolute object module file can be directly executed by the 8051 family. The
listing file shows the results of the link/locate process.

LIB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to create and maintain libraries of software object modules.
With this utility, the customer can develop standard software modules and place them in libraries, which
programs can access through a standard interface. When using object libraries, the linker will call only object
modules that are required to satisfy external references.
Consequently, the librarian enables the customer to port and reuse software on different projects-thereby
maintaining the customer's software investment.

ORDERING INFORMATION

Order Code

Operating Environment

D86ASM51

8051 Assembler for PCDOS 3.0 Systems

R86ASM51

8051 Assembler for iRMX 86 Systems

Documentation Package:

SUPPORT:

MCS-51 Macro Assembler User's Guide
MCS-51 Utilities User's Guide for 8080/8085
Based Development System

Hotline Telephone Support, Software Performance
Reporting (SPR), Software Updates, Technical Re, ports, Monthly Newsletter available.

MCS-51 8048-to-805,1 Assembly Language Converter Operating Instructions for ISIS-II Users

17-51

inter

ICETM·5100/044In·Circuit Emulator
. for the RUPITM·44 Family

•
•
• Bits Trace

Precise, Full-Speed, Real-Time
Emulation of the RUPITM-44 Family of
Peripherals

Debugging Enables Access to
• Symbolic
Memory Locations and Program

64 KB of Mappable High-Speed
Emulation Memory

•
Equipped with the Integrated Command
• Directory
(ICDTM) That Provides

254 24-bit Frames of Trace Memory (16
Program Execution
Addresses and 8 Bits Trace Eternal
Events)

•
•
•

Serial Link to Intel Series III/IV or IBM*
PC AT or PC XT (and PC DOS
Compatibles)
ASM-51 and PL/M-51 Language
Support

Variables
Four Address Breakpoints Plus InRange, Out-of~Ral'1ge, and Page Breaks

- On-Line Help
- Syntax Guidance and Checking
- Command Recall

•
•

Built-in CRT-Oriented Text Editor

On-Line Disassembler and Single-Line
Assembler to Help with Code Patching
Provides an Ideal Environment for
Debugging BITBUSTM Applications .
Code

The ICETM-51 00/044 in-circuit emulator is a high-level, interactive debugger that is used to develop and test
the hardware and software of a target system based .on the RUPITM-44 family of peripherals. The ICE5100/044 emulator can be serially linked to an Intellec® Series III/IV or an IBM PC AT or PC XT. The emulator
can communicate with the host system at standard baud rates up to 19.2K. The design of the emulator
supports all of the RUPI-44 components at speeds up to and including 12 MHz.
.
.
"IBM is a registered trademark of International Business Machines Corporation. Intel Corporation assumes no responsibility
for the use of any circuitry other than cirCUitry embodied in an Intel product. No other patent licenses are implied. Information
contained herein supersedes previously published specifications on these devices from Intel.

280325-1

17-52

November 1986
Order Number: 280325-001

infef

ICETM·5100/044

tion of the microcontroller to debug the system as a
completed unit.

PRODUCT OVERVIEW
The ICE-5100/044 emulator provides full emulation
support for the RUPI-44 family of peripherals, including 8044-based BITBUSTM board products. The
RUPI-44 family consists of the 8044, the 8744, and
the 8344.
The ICE-51 00/044 emulator enables hardware and
software development to proceed simultaneously.
With the ICE-5100/044, prototype hardware can be
added to the system as it is designed and software
can be developed prior to the completion of the
hardware prototype. Software and hardware integration can occur while the product is being developed.

The final product verfication test can be performed
using the ROM or EPROM version of the microcontroller. Thus, the ICE-5100/044 emulator provides
the ability to debug a prototype or production system
at any stage in its development without introducing
extraneous hardware or software test tools.

PHYSICAL DESCRIPTION
. The ICE-51 00/044 emulator consists of the following components (see Figure 1):
• Power supply
• AC and DC power cables
• Controller pod
• Serial Cable (host-specific)
• User probe assembly (consisting of the processor module and the user cable)

The ICE-5100/044 emulator assists four stages of
development:
•
•
•
•

Software debugging
Hardware debugging
System integration
System test

• Crystal power accessory (CPA)
• 40-pin target adaptor

Software Debugging
The ICE-51 00/044 emulator can be operated without being connected to the target system and before
any of the user's hardware is available (provided external data RAM is not needed). In this stand-alone
mode, the ICE-5100/044 emulator can be used to
facilitate program development.

Hardware Debugging
The ICE-5100/044 emulator's AC/DC parametric
characteristics match the microcontroller's. The emulator'S full-speed operation makes it a valuable tool
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces.

System Integration
Integration of software and hardware can begin
when the emulator is plugged into the microcontroller socket of the prototype system hardware. Hardware can be added, modified, and tested immediately. As each section of the user's hardware is completed, it can be added to the prototype. Thus, the
hardware and software can be system tested in realtime operation as each section becomes available.

System Test
When the prototype is complete, it is tested with the
final version of' the system software. The ICE5100/044 emulator is then used for real-time emula-

• Clips assembly
• Software (includes the ICE-5100/044 emulator
software, diagnostic software, and a tutorial)
The controller pod contains 64 KB of emUlation
memory, 254- by 24-bit frames of trace memory, and
the control processor. In addition, the controller pod
houses a BNC connector that can be used to connect up to 10 multi-ICE compatible emulators for
synchronous starting and stopping of emulation.
The serial cable connects the host system to the
controller pod. The serial cable supports a subset of
the RS-232C signals.
The user probe assembly consists of a user cable
and a processor module. The processor module
houses the emulation processor and the interface
logic. The target adaptor connects to the processor
module and provides an electrical and mechanical
interface to the target microcontroller socket.
The crystal power accessory (CPA) is a small, detachable board that connects to the controller pod
and enables the ICE-5100/044 emulator to run in
stand-alone mode. The target adaptor plugs into the
socket on the CPA; the CPA then supplies clock and
power to the user probe.
The clips assembly enables the user to trace external events. Eight bits of data are gathered on the
rising edge of PSEN during opcode fetches. The
clips information can be displayed using the CLIPS
option with the PRINT command.

17-53

ICETM·5100/044

280325-2

Figure 1. The ICETM·5100/044 Emulator Hardware
The ICE·5100·044 emulator software supports mnetroller of the target system. Emulation is a transparmonics, object file format~, and symbolic references
ent process that happens in real-time. The execution
of the user software is facilitated with the ICEgenerated by Intel's ASM-51 and PL/M-51 programming languages. Along with the ICE-51 00/044 emu5100/044 command language.
lator software is a customer confidence test disk
with diagnostic routines that check the operation of
the hardware.
Memory Mapping

The on-line tutorial is written in the ICE-5100 command language. Thus,the user is able to interact
with and use the ICE-51 00/044 emulator while executing the tutorial.

There is a 64 KB of memory that can be mapped to
the CODE memory space in 4 KB blocks on 4 KB
boundaries. By mapping memory to the ICE51001044 emulator, software development can proceed before the user hardware is avaiiabie.

A comprehensive set of documentation is provided
with the ICE-51 00/044 emulator.

Memory Examination and Modification
ICETM·5100/044 EMULATOR
FEATURES
The ICE-51 00/044 emulator has been created to assist a product designer in developing, debugging and
testing designs incorporating the RUPI-44 family of
peripherals. The following sections detail some of
the ICE-51 00/044 emulator features.

The memory space for the 8044 microcontroller and
its target hardware is fully accessible through the
emulator. The ICE-51 00/044 emulator refers to four
physically distinct memory spaces, as follows:
• CODE"-references program memory .
• IDATA-references internal data memory
• RDATA-references special function register
memory
• XDATA-references external data memory

Emulation
Emulation is the controlled execution of the user's
software in the target hardware or in an artificial
hardware environment that duplicates the microcon-

ICE-5100/044 emulator commands that access
memory use one of the special prefixes (e.g., CODE)
to specify the memory space.

17-54

ICETM·5100'044

The microcontroller's special function registers and
register bits can be accessed mnemonically (e.g.,
DPL, TCON, CY, P1.2) with the ICE-51 00/044 emulator software.
Data can be displayed or modified in one of three
bases: hexadecimal, decimal, or binary. Data can
also be displayed or modified in one of two formats:
ASCII or unsigned integer. Program code can be disassembled and displayed as ASM-51 assembler
mnemonics. Code can be modified with standard
ASM-51 statements using the built-in single-line assembler.

Breakpoint Specifications
Breakpoints are used to halt a user program in order
to examine the effect of the program's execution on
the target system. The ICE-51 00/044 emulator supports three different types of break specifications:
• Specific address break-specifying a single address point at which emulation is to be stopped.
• 'Range break-an arbitrary range of addresses
can be specified to halt emulation. Program execution within or, optionally, outside the range
halts emulation.
• Page break-up to 256 page breaks can be specified. A page break is defined as a range of addresses that is 256-bytes long and begins on a
256-byte address boundary.

Symbolic references can be used to specify memory
locations. A symbolic reference is a procedure
name, line number, program variable, or label in the
user program that corresponds to a location.
Some typical symbolic functions include:
• Changing or inspecting the value of a program
variable by using its symbolic name to access the
memory location.
• Defining break and trace events using symbolic,
references.
• Referencing variables as primitive data types.
The primitive data types are ADDRESS, BIT,
BOOLEAN, BYTE, CHAR (character), and
WORD.
The ICE-51 00/044 emulator maintains a virtual symbol table (VST) for program symbols. A maximum of
61 KB of host memory space is available for the
VST. If the VST is larger than 61 KB, the excess is
stored on available host system disk space and is
paged in and out as needed. The size of the VST is
limited only by the disk capacity, of the host system.

Break registers are user-defined debug definitions
used to create and store breakpoint definitions.
Break registers can contain multiple breakpoint definitions and can optionally call debug procedures
when emulation halts.

Trace Specifications
Tracing can be triggered using specifications similar
to those used for breaking. Normally, ,the
ICE-5100/044 emulator traces program activity
while the user program is executing. With a trace
specification, tracing can be triggered to occur only
when specific conditions are met during, execution.
Up to 254 24-bit frames of trace information are col- ,
lected in a buffer during emulation. Sixteen of the 24
bits trace instruction execution addresses, and 8 bits
capture external events (CLIPS).

,·Print newest four instructions in the buffer .,
, ( hl t > PRINT NEWEST 4
FRAME
ADDR
CODE
INSTRUCTIONS
(28)
300A
C02A
PUSH
,2AH
(30
300C
2532
ADD
A, 32H
(32)
300E
F52A
MOV
2AH, A
(34)
3010
B53210
CJNE
A,32H, $+10H
hlt>
,. Buffer display showing clips .,
hl t > PRINT CLIPS OLDEST 2
FRAME
ADDR
CODE
INSTRUCTIONS
CLIPS
(76543210)
(00)
007AH
0508
INC INDX PTR
10101111
(01)
007CH
80E6
SJMP (#28)
00100010

280325-3

Figure 2. Selected Trace Buffer Displays

17-55

ICETM-5100/044

The trace buffer display is similar to an ASM-51 program listing as shown in Figure 2. The PRINT command enables the user to selectively display. the
contents of the trace buffer. The user has the option
of displaying the clips information as well as dissassembled instructions.

ARM

~t>GO

FOREVER

TIL

USING

Procedures
Debugging procedures (PROCs) are a user-defined
group ofJCE-51 00/044 commands that are executed as one command. PROCs enable the user to define several commands in a named block structure.
The commands are executed by entering thename
of the PROC. The PROC bodies are a simple DO ...
END construct.

TRACE

ffiO.

hI t > GO FROM I3H

ARM

FOREVER

TIL

USING

TRACE

hI t > GO FROM I3H USING
BRKREG

hIt>GO FROM I3H USING bri
TRACE

hIt>GO FROM I3H USING bri TRACE

OUTSIDE

PAGE FROM TIL

hIt>GO FROM I3H USING bri TRACE traceit

280325-4

Figure 3. The Integrated Command Directory for the GO Command
17-56

inter

ICETM·5100/044

PAOCs can simulate missing hardware or software,
set breakpoints, collect debug information, and execute high-level software patches. PAOCs can be
copied to text files on disk, then recalled for use in
later test sessions. PAOCs can also serve as program diagnostics, implementing ICE-51 00/044 emulator commands or user-defined definitions for special purposes.

On-Line Syntax Menu
A special syntax menu, called the Integrated Command directory (ICD), similar to the one used for the
121CETM system and the VLSiCE-96 emulator, aids in
creating syntactically correct command lines. Figure
3 shows an example of the ICD and how it changes
to reflect the options available for the GO command.

Help

tor's memory along with the user's code to enable
rapid debug of 8044 BITBUS applications code.

DESIGN CONSIDERATIONS
The height of the processor module and the target
adaptor need to be considered for target systems.
Allow at least 1% inches (3.8 cm) of space to fit the
processor module and target adaptor. Figure 5
shows the dimensions of the processor module.
Execution of user programs that contain interrupt
routines causes incorrect data to be stored in the
trace buffer. When an interrupt occurs, the next instruction to be executed is placed into the trace buffer before it is actually executed. Following completion of the interrupt routine, the instruction is executed and again placed into the trace buffer.

ELECTRICAL CONSIDERATIONS

The HELP command provides ICE-51 00/044 emulation command assistance via the host system terminal. On-line HELP is available for the ICE-5100/044
emulator commands shown in Figure 4.

The emulation processor's user-pin timings and
loadings are identical to the 8044 component, except as follows.

BITBUSTM Applications Support

• Up to 25 pF of additional pin capacitance is contributed .by the processor module and target
adaptor assemblies.

The ICE-51 00/044 emulator provides an. ideal environment for developing applications code for BITBUS board products such as the ACB-44/10, the
ACB-44/20, the PCX-344, and the iSBXTM-344
board.
The BITBUS firmware, available separately as BITWAAE, can be loaded into the ICE-51 00/044 e.mula-

• Pin 31, EA, has approximately 32 pF of additional
capacitance loading due to sensing circuitry.
• Pins 18 and 19, XTAL 1 and XTAL2 respectively,
have approximately 15-16 pF of additional capacitance when configured for crystal operation.

/hlt > HELP
HELP is available for:
ADDRESS
BYTE
CURHOME
DISPLAY
EXPRESSION
KEYS
MAP
OPERATOR
REFERENCE
STRING
VERIFY
~>

APPEND
CHAR
CURX
DO
GO
LABEL
MENU .
PAGING
REGS
SYMBOLIC
VERSION

ASM
CI
CURY
DYNASCOPE
HELP
LINES
MODIFY
PARTITION
REMOVE
SYNCSTART
WAIT

BASE
CNTL_C
DCI
EDIT
IF
LIST
MODULE
PRINT
REPEAT
TEMPCHECK
WORD

BIT
... BOOLEAN
COMMENTS CONSTRUCTS
DEBUG
DEFINE
ERROR
EVAL
INCLUDE
INVOCATION
LITERALLY LOAD
MSPACE
MTYPE
PROC
PSEUDO_VAR
RESET
RETURN
TRCREG
TYPES
WRI.TE
.

BRKREG·
COUNT
DIR
EXIT
ISTEP
LSTEP
NAMES COPE
PUT
SAVE
VARIABLE

-lJ

280325-5

FIgure 4. HELP Menu
17-57

inter

ICETM~5100/044

PROCESSOR MODULE

PIN 1

10PVlEW

~1;~________________~~~~·:~:~;-------------------EU~===4·====~I·
IH em)

(10.2 em)

280325-6

Figure 5•. Processor Module Dimensions

HOST REQUIREMENTS

PHYSICAL CHARACTERISTICS

• IBM PC AT.or PCXT (or PC DOS cOmpatible)
with 512 KB of available RAM and a, hafddisk
running under the DOS 3.0 '( or later) operating
system.
• Intellec Series III/IV microcomputer development
system. running the ISIS or iNDXoperating system respectively, ~ith at least 512 KB of app.lication memory resident
.
.

Controller Pod
Width: .

8~%"

HE!ight:
Depth:

1_%".
13_%"

Weight:

41bs

• Disk drives-dual floppy or one hard disk and one
floppy drive required.

(21
cm)
( 3.8 cm)
(34.3 cm)
( 1.85 kg)

User Cable'

ICETM·5100/044 EMULATOR·
SOFTWARE PACKAGE

The user cable is 3 feet.{appi"Qximately 1 m)

• ICE-5100/044 emulator software
• ICE-5100/044 confidence tests
• ICE-5100 tutorial software

Processor Module
(With the target adaptor attached)
3- ' 0/.6" (9.7 em)·
Width:
(10.2 cm)
Height: 4"
( 3.8. cm)
1-%"
Depth:

EMULATOR PERFORMANCE
Memory
Mappable
full-speed
emulation code
memory

64 KB

Mappable to user or ICE5100/044 emulator memoryin 4 KB blocks on 4 KB
boundaries.
'

Trace memory,

254 x 24 bit frames

Virtual Symbol .
Table

A .maximum of 61 KB of
host memory space is
available for the virtual
symbol table (VST). The
rest of the VST resides on
disk and is paged in and
out as .needed.

Power Supply
Width:
Height:
Depth:
. Weight

7-%"
4"
11"
151bs

(18.1 cm)
(10.06 cm)
(27.97 em)
( 6.1 kg)

Serial Cable
The serial cable is 12 feet (3.6 m):

17-58

intJ

ICETM_5100/044

Software Only

ELECTRICAL CHARACTERISTICS

Order Code
SA044D

Power Supply
100-120V or 200-240V (selectable)
50-60 Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V

SA044S

ENVIRONMENTAL
CHARACTERISTICS
Operating temperature
Operating humidity

+ 10°C to + 40°C (50°F to
104°F)
Maximum of 85% relative
humidity, non-condensing

ORDERING INFORMATION

Emulator Hardware and Software
Order Code
1044KITAD

1044KITD

1044KITAS

1044KITS

Description
This kit contains the ICE-5100/044
user probe assembly, power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation for
use with an IBM PC AT or PC XT. The
kit also includes the 8051 Software
Development Package and the
AEDIT text editor for use on DOS
systems. [Requires software license.)
This kit is the same as the 1044KITAD
excluding the. 8051 Software· Development Package and the AEDIT text
editor. [Requires software license.)
This kit contains the ICE-51 00/044
user probe assembly, power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation for
use with Intel hosts (Series IIII1V).
The kit also includes the 8051 Software Development Package and the
AEDIT text editor for use on the Series III/IV. [Requires software license.)
This kit is the same as the 1044KITAS
excluding the 8051 Software pevelopment Package and the AEDIT text
editor. [Requires software license.)

Description
This kit contains the host, probe, diagnostic, and· tutorial .software on
5%" disks for use on an IBM PC AT
or PC XT (requires DOS 3.0 or later).
.[Requires software license.)
This kit contains the host, probe, diagnostic, and tutorial software on 8"
disks (both single-density and double-density) for use on a Series III,
and on 5-%" disks for use on a Series IV. [Requires software license.)

Other Useful Intel® MCS®-51 Debug and
Development Support Products
Order Code Description
D86ASM51
8051 Software Development Package (DOS version)-Consists of the
ASM-51 macro assembler which
gives symbolic access to 8051 hardware features; the RL51 linker and
relocator program that links modules
generated by ASM-51; CONV51
which enables software written for
the MCS-48 family to be up-graded to
run on the 8051, and the L1B51 librarian which programmers can use
to create and maintain libraries of
software object modules. Use with
the DOS operating system (version
3.0 or later).
D86PLM51
PL/M-51 Software Package (DOS
version)-Consists of the PL/M-51
compiler which provides high-level
programming language support; the
L1B51 utility that creates and
maintains libraries of software object
modules, and the RL51 linker and
relocator program that links modules
generated by ASM-51 and PLlM-51
. and ·Iocates the linked object module·s· to absolute memory locations.
Use with the DOS operating system
(version 3.0 or later).
186ASM51
8051 Software Development Package (ISIS version)-Same as the
D86ASM51 package except this one
is for use with the Series III.
186PLM51
PL/M-51 Sofware Package-Same
as the D86PLM51 package except
this one is for use with the Series III
and Series IV.
D86EDINL
AEDIT text editor for use with the
DOS operating system.

17-59

intJ

iDCX 51
DISTRIBUTED CONTROL EXECUTIVE

MCS@·51 and RUPITM·44
• Supports
Familes of 8·Bit Microcontrollers
Real·Time, Multitasking
• -Supports
up t08 Tasks at Four
. Priority Levels
• Local and Remote Task Communication
Ex~cutive

•
•
•
•
•

Small-2.2K Bytes
Reliable
Simple User Interface
Dynamic Reconflguratlon Capability
Compatible with BITBUSTM/Distributed
Control Modules (iDCM) Product Line

The iDCX 51 Executive is compact, easy to use software for developmentand implementation of applications
using the high performance a·bit family of 8051 microcontrollers,including the .8051, 8044, and 8052. Like the
8051 family, the iDCX 51 Executive is tuned for real-time control applications requiring manipulation and
scheduling of more than one task, and fast response to external stimuli.
The MCS·51 microcontroller family coupled with iDCX 51 is a natural combination for applications such as data
acquisition and monitoring, process control, robotics, and machine control. The iDCX 51 Executive can significantly reduce applications development time, particularly BITBUS distributed control environments ..
The iDCX 51 Executive is available in two forms, either as configurablesoftware on diskette or as preconfigured firmware within the 8044 BEM BITBUS microcontroller.
.

280176-1

Figure 1.IDCX 51 Distributed Control Executive

'XENIXTM is a trademark of Microsoft Corporation.

17-60

October 1987
Order Number: 280176-003

inter

iDCX 51

MICROCONTROLLER SUPPORT
The iDCX 51 Executive is designed to support the
MCS-51 and RUPI-44 families of 8-bit microcontrollers. MCS-51 microcontrollers that are supported include the 8051, 80C51 , 8052, 8031, 8032, and 8751
devices. The RUPI-44 microcontrollers include the
8044, 8344, and 8744 devices. All of these microcontrollers share a common 8051 core.

ARCHITECTURE
Real-time and Multitasking

events: interrupts, timers, and messages ensuring
the application system always responds to the environment appropriately.

Task Management
A task is a program defined by the user to execute a
particular control function or functions. Multiple programs or tasks may be required to implement a particular function such as "controlling Heater 1". The
iDCX 51 Executive recognizes three different task
states as one of the mechanisms to accomplish
scheduling of up to eight tasks. Figure 2 illustrates
the different task states and their relationship to one
another.

Real-time control applications must be responsive to
the external environment and typically involve the
execution of more than one activity (task or set of
tasks) in response to different external stimuli. Control of an industrial 'drying process is an example.
This process could require monitoring of multiple
temperatures arid humidity; control of. fans, heaters,
and motors that must respond accordingly to a variety of inputs. The iDCX 51 Executive fully supports
applications requiring response to stimuli as they occur, i.e., in real-time. This real-time response is supported for multiple tasks often needed to implement
a control application.

The scheduling of tasks is priority based. The user
can prioritize tasks to reflect their relative importance within the overall control scheme. For instance, if Heater 1 must go off line prior to Heater 2
then the task associated with Heater 1 shutdown
could be assigned a higher priority ensuring the correct shutdown sequence. The RQ WAIT system call
is also a scheduling tool. In this example the task
implementing Heater 2 shutdown could include an
instruction to wait for completion of the task that implements Heater 1 shutdown.

Some of the facilities precisely tailored for development and implementation of real-time control application systems provided by the iDCX 51 Executive
are: task management, interrupt handling, message
passing, and when integrated with communications
support, message passing with different micro controllers. Also, the iDCX 51 Executive is driven by

The iDCX 51 Executive allows for PREEMPTION of
a task that is currently being executed. This means
that if some external event occurs such as a catastrophic failure of Heater 1, a higher priority task associated with the interrupt, message, or timeout resulting from the failure will preempt the running task.
Preemption ensures the emergency will be responded to immediately. This is crucial for real-time control
application systems.

Running Task Executes ROWAIT or RODELETE
READY

II-+----:::---:-::---,,...----::-:---:::---c,...-,..----fl RUNNING
Event Occurs Assoc. wi Asleep Task wi
Higher Priority Than Running Task.

Event Occurs Assoc.
wlAsleepTask wi
Lower Priority
Than Running
Task

Event Occurs Assoc. wi Asleep Task wi
Higher Priority Than Running Task
ASLEEP

l
Running Task Executes RQWAIT

Figure 2. Task State Transition Diagram

17-61

280176-2

inter

iDCX 51

Interrupt' Handling

REMOTE TASK COMMUNICATION

The iDCX 51 Executive supports five interrupt
sources as shown in Table 1. Four of these interrupt
sources, excluding timer 0, can be assigned to a
tas~. When one of the interrupts occurs the task associated with it becomes a running task (if it were
the highest priority task in a ready state); In this way,
the iDCX 51 Executive responds to a number of in"
ternal and external stimuli including time intervals
designed by the user.

The iDCX 51 Executive system calls can support
communication to tasks on remote controllers. This
feature makes the iDCX 51 Executive ideal for applications using distributed architectures. Providing
communication support saves significant application
development time and allows for more effective use
of this time. Intel's iDCM product line combines
hardware and software to provide this function ..
In an iDCM system, communication between nodes
occurs via the BITBUS microcontroller interconnect.
The BITBUS microcontroller interconnect is a high
performance serial control bus specifically intended
for use in applications built on distributed architectures. The iDCX 51 Executive provides BITBUS support.

Table 1. iDCX 51 Interrupt Sources
Interrupt Source

Interrupt Number

External Request 0

OOH

Timer 0

01H

External Request 1

02H

Timer 1

03H

Internal Serial Port 1

04H

BITBUSTM/iDCM COMPATIBLE

Message Passing
The iDCX 51 Executive allows tasks to interface with
one another via a simple message passing facility.
This message passing facility can be extended to
different processors when communications support
is integrated within a BITBUS/iDCM system, for example. This facility provides the user with the ability
to link different functions or tasks. Linkage between
tasks/functions is typically required to support development of complex control applications with multiple sensors (input variables) and drivers (output
variables). For instance, the industrial drying process
might require a dozen temperature inputs, six moisture readings, and· control of: three fans, tWo conveyor motors, a dryer motor, and a pneumatic conveyor. The data gathered from both the temperature
and humidity sensors could be processed. Two
tasks might be required to gather the data and process it. One task could perform a part of the analysis, then include a pointer to the next task to complete the next part of the analysis. The tasks could
continue to move between one another.

A pre-configured version of the iDCX 51 Executive
implements the BITBUS message format and provides all iDCX 51 facilities mentioned previously:
task management, interrupt handling, and message
passing. This version of the Executive is supplied in
firmware on the 8044 BEM with the iDCM hardware
products: the iSBXTM 344A BITBUS Controller MULTIMODULETM; theiDCX 344A BITBUS controller
board for the PC; and.the iRCB boards.
Designers wh<;> want to use the iDCX executive on
an Intel BITBUS board should purchase either
DCS110 or DSC120 BITBUS software. Both of these.
products include an interface library to iDCX 51 procedures and other development files. It is riot necessary to purchase the iDCX 51 Executive.

SIMPLE USER INTERFACE
The iDCX 51 Executive's capabilities are utlilized
through system calls. These interfaces have been
defined for ease of use and simplicity. Table 2 includes a listing of these calls and their functions.
Note that tasks may be created at system initialization or run-time using the CREATE TASK call.
Other Functions such as GET FUNCTION IDS, ALLOCATE/DEALLOCATE BUFFER, and SEND MESSAGE, support communication for distributed archi.tectures.

17-62

iDCX 51

Table 2. iDCX 51 System Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available system memory pool memory.

RQ$RELEASE$MEM

Release system memory pool memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re·enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

Another feature that eases application development
is automatic register bank allocation. The Executive
will assign tasks to register banks automatically un·
less a specific request is made. The iDCX 51 Executive keeps track of the register assignments allowing
the user to concentrate on other activities.

SYSTEM CONFIGURATION
The user configures an iDCX 51 system simply by
specifying the initial set of task descriptors and con-,
figuration values, and linking the system via the
RL 51 Linker and Locator Program with user programs.
Each task that will be running under control of the
executive has an Initial Task Description (ITO) that
describes it. The ITO specifies to the executive the
amount of stack space to reserve, the priority level
of the task (1-,.4), the internal memory register bank
to be associated with the task, the internal or external interrupt associated with the task, and a function
10 (assigned by the user) that uniquely labels the
task. The ITO can also include a pointer to the ITO
for the next task. In this wayan ITO "chain" can be
formed. For example,if four ITO's are chained to-

gether, then when the system is initialized, all four
tasks will be put into a READY state. Then, the highest priority task will run.
The DCX 51 user can control several system constants during the configuration process (Table 3).
Most of these constants are fixed, but by including
an Initial Data Descriptor (100) in an ITO chain, the
system clock priority, clock time unit, and buffer size
can be modified at run-time.
This feature is useful for products that use the same
software core, but need minor modification of the
executive to better match the end application. The
initial data descriptor also allows the designer, who
is using an 8044 BEM BITBUS Microcontroller, to
modify the preconfigured (on-chip) iDCX 51 Executive.
Programs may be written in ASM 51 or PLIM 51.
Intel's 8051 Software Development Package contains both ASM 51 and RL 51. Figure 3 shows the
software generation process.

17-63

inter

iDCX51

Table 3. DCX 51 Configuration Constants
Description

Constant Name
RQ CLOCK PRIORITY

The priority level of the system clock.

RQ CLOCK TICK

The number of time cycles in the system clock basic.time unit (a "tick").

RQ FIRST ITO

The absolute address of the first ITO in the ITO chain.

RQ MEM POOL ADR

The start address of the System Memory Pool (SMP) in Internal DataRAM.

RQ MEM POOL LEN

The length of the SMP.

RQRAM 100

The absolute RAM address of where iDCX 51 checks for an Initial Data
Descriptor (100) during initialization.

RQ SYS BUF SIZE

The size, in bytes, of each buffer in the system buffer pool.

WRITE
SOURCE CODE

ASSEMBLE/
COMPILE

LlNK/
LOCATE

LOAD/EXECUTE

AEDIT
INSTALL EMULATOR
r-~---....., PROBE IN
ICE™ 5100 SERIES, MICROCONTROLLER
ICEIM 44, ICE51,
SITE
EMV44, OR EMV51,1---""
EMULATORS

TARGET
BOARD
IUP-200A/201A
WITH
UNIVERSAL PROM I - -___- t -.. MCS® 51/
PROGRAMMER
INSTALL
RUPI'N 44
EPROM
MICROIN CODE
CONTROLLER
SITE
INSTALL SRAM
IN CODE SITE

0"",,,,,.
D

SOFTWARE TOOL
280176-3

NOTE:
*RL 51 is included with ASM51 and PLIM 51; OBJHEX and the BITBUS Monitor are part of the DCS100 BITBUS
Toolbox.

Figure 3. Software Generation Process

infef

iDCX 51

cated from any remaining memory. These buffers
form the System Buffer Pool (SBP) that can be used
to create additional stack space or to locate messages sent between tasks.

SOPHISTICATED INTERNAL MEMORY
MANAGEMENT
The amount of internal memory available ranges
from 128 to 256 bytes depending on the type of microcontroller used.

Ouring run-time, the iOCX 51 Executive dynamically
manages this space. If a task is deleted, its stack
space is returned to the System Buffer Pool for use
by other tasks or as a message buffer.

Internal memory is used for the executive, stack
spare for "running" tasks, space for message buffers, and reserved memory for variables storage.
Other memory is used for register space. Except for
register space, the allocation of internal memory is
controlled by the executive, user-specified task/data
descriptors and system configuration constants.

As new tasks are dynamicalily created, the executive reserves the needed stack space. If no space is
available, the executive deallocates a buffer from
the System Buffer Pool and then allocates the needed stack space.

To optimize use of this limited resource, iOCX 51
provides dynamic (run-time) memory management.

To send or receive a message, the executive allocates one or more buffers from the SBP for space to
locate the message. With iOCX 51, messages can
be optionally located in external (off-chip) memory.
The pre-configured executive in the 8044 BEM
BITBUS microcontroller, however, always locates
messages in internal memory.

INITIALIZATION AND DYNAMIC
MEMORY MANAGEMENT
At initialization (see Figure 4), the iOCX 51 Executive
creates the System Memory Pool (SMP) out of the
remaining initial free space (i.e. memory not used by
the iOCX 51 Executive or for register space). Next,
stack space is created for each of the initial tasks
that will be running on the system. If reserved memory is requested (using an 100), that memory is also
set aside. Finally, multiple buffers (size specified during iOCX 51 configuration or using an 100) are allo-

RELIABLE
Real-time control applications require reliability. The
nucleus requires about 2.2K bytes of code space, 40
bytes on-chip RAM, and 218 bytes external RAM.

DCX 51 Initialization
Task 0
Task 1
Task 2
Task 3
Unallocated

Initial
Free
Memory
Space

STEPS:

I
SSP

1. Create system memory pool from the initial free memory space.
2. Allocate stack space (space for 4 tasks shown).
3: Allocate user-reserved memory (per the IDD).
4. Allocate equal-size buffers to form the system buffer
pool.

I
User
Memory

Figure 4. iDCX 51 Initialization of Internal Memory

17-65

inter

iDCX51

Streamlined code increases performance and reliability, and flexibility is not sacrificed as code maybe
added to either on-chip or external memory.
The iDCX 51 architecture and simple user interface
further enhance reliability and lower cost. For example, the straightforward structure of the user interfaces, and the transparent nature of the scheduling
process contribute to reliability of the overall system
by minimizing programming effort. Also, modularity
increases reliability of the system and lowers cost by
allowing user tasks to be refined independent of the
system. In this way,errors are identified earlier and
can be easily corrected in each isolated module. '
In addition, users can assign tasks a Function ID
that allows tracking, of the tasks associated with a
particular contrcil/mol)itorig function. This feature reduces maintenance and trouble shooting time thus
increasing system run time and decreasing cost.

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment
for the MCS-51 and RUPI-44 families of microcontrollers. The iDCX 51 Executive is only one'of many
of the software development products available. The
executive is compatible with the following software
development utilities available from Intel:
• 8051 Macro Assembler (ASM 51)
• PLiM 51 Compiler
• RL 51 Linker and Relocator Program
• LIB 51
Intel hardware development tools currently available
for MCS-51 and RUPI-44 microcontroller development are:
• ICE-51 00/252 Emulator for the MCS-51 family of
microcontrollers
• ICE-51 00/044 Emulator for the RUPI-44 family of
microcontrollers (8044, 8344, 8744)
• iUP-200Al201A PROM Programmer, 21X soft- '
'
ware, and iUP programming modules

OPERATING ENVIRONMENT
The iDCX 51 Executive supports applications development based on any member of the high performance 8051 family of microcontrollers. The Executive
is available on diskette with user linkable libraries or
in the 8044 BITBUS Enhanced Microcontroller preconfigured in on-chip ROM. (The 8044 BEM is an
8044 component that consists of an 8051 microcontroller and SDLC controller on one chip with integral
firmware.)
When in the iDCM environment (Figure 5), the preconfigured iDCX 51 Executive can communicate
with other BITBUS series controller boards. The
BITBUS board at the master node can be associated with either an iRMXTM, PC-DOS or XENIX' host
system.

The DCX 51 Executive is also compatible with older
hardware development tools (no longer available),
which include:
• EMV-51 144 Emulation Vehicles
• ICE-51 144 In-Circuit Emulators
Table 4 shows the possible MCS-51 and RUPI-44
families development environments: host systems,
operating systems, available software utilities, and
hardware debug tools.

MASTER

REMOTE NODES
(SLAVES)

260176-4

Figure 5. iDeM Operating Environment

17-66

inter

IDCX 51

SPECIFICATIONS

Reference Manual (Supplied)

Supported Microcontrollers

460367-001- iDCX 51 Distributes Control Executive User's Guide for Release 2.0.

8031
8051
8032
8744
8344

80C31
,80C51
8751
8044
8052

ORDERING INFORMATION
Part Number
DCX51SU

Compatible DCM BITBUSTM Software
DCS 100 BiTBUS Toolbox Host Software Utilities'

Description
Executive for 8051 Family of Microcontrollers. Single User License, Development Only. Media Supplied for
All Host Systems (Table 3).
Royalty (Incorporation) Fee for iDCX
Executive. Set of 50 incorporations.
IDCX 51 RF does not shipwith soft~
ware (Order DCX 51SU).

DCX51RF

DCS 110 BITWARE DCM44 Code for BITBUS emulation
.

Table 4. MCS®-S1/RUPITM-44 Families Development Environments
Host Systems
Development Utilities

PC/MS-DOS. IRMX®S6

Intel/ec®

IPDSTM

Series"

Series IIIIIV

SOFTWARE
ASM 51
PLIM 51

+ Utilities(1)
+ Utilities(1)

iDCX 51 Executive

HARDWARE
ICE-51 00/044/252

iUP-200Al201 A

EMV-51 (2), EMV-44(2)

ICE-51 (2), ICE-44(2)

iPDS

+ iUP-F87 144A PROM Programmer

NOTES:
:.
.
1. Utilities include RL 51, LIB 51, and AEDIT. Software for Series II systems is down-revision version.
2. These products are no longer available.

17-67

inter

8044 BITBUSTM
ENHANCED MICROCONTROLLER

•
•
•
•

Dual Processor Mlcrocontroller
• Architecture

•
•
•

High Performance 8-Blt CPU
Embedded Parallel Communications
Firmware
Tuned for Distributed Real-Time
Control

BITBUSTM Firmware Included

On~Chlp

Power-Up Diagnostics
DCX 51 Distributed Control Executive
Included On-Chip
MCS®-51 Software Compatible

The 8044 BITBUS Enhanced Microcontroller (BEM) is a powerful 8-bitmicrocontroller with on-chip firmware.
The dual processor architecture of the 8044 combined with the inherent the processing power of an 8051 CPU
is well suited. for distributed data acquisition and control applications in both the factory and laboratory. The
firmware integral includes facilities for: diagnostics, task management, message passing, and user-transparent
parallel and serial communication services.

FREQUENCE
REFERENCE

I---_DATA

~--. SDLe-BASED
SERIAL
COMMUNICATIONS

INTERRUPfS

CONTROL

PARALLEL PORTS
ADDRESS DATA BUS
AND 110 PINS

COUNTERS

280129-1

Figure 1. BEM Block Diagram

·IBM is a trademark of Intemational Business Machines Corporation.

17-68

October 1987
Order Number: 280129.003

8044 BITBUSTM Enhanced Microcontroller

and computational power are provided by the onchip 8-bit 8051 CPU. The Serial Interface Unit (SIU)
executes a majority of the communications functions
in hardware resulting in a high performance solution
for distributed control applications where communication and processing power are equally important.
The BEM's firmware implements the BITBUS message structure and protocol, and the pre-defined liD
command set.

OPERATING ENVIRONMENT
Introduction
The BITBUS Interconnect Serial Control Bus Specification defines an integrated architecture optimized

for implementing real-time distributed control systems. The architecture includes a message structure
and protocol for multitasking environments, and a
predefined interface for liD access and control. As
with traditional bus specifications the mechanical,
electrical, and data protocols have been defined.
Over a twisted pair of wires the bus can support up
to 250 nodes at three different bit rates dependent
on application performance requirements. Figure 2
illustrates the BITBUS Interconnect architecture.

Firmware
The 8044 microcontroller requires specific hardware
to interface to BITBUS. The BEM's firmware also
requires a particular hardware environment in order
to execute correctly, just as the iOCX 86 Operating
System or other operating systems required a specific hardware environment, i.e., interrupt controller,
timers, etc. Based upon the hardware provided, Basic or Extended firmware environments result.

The 8044 BITBUS Enhanced Microcontroller (BEM)
or OCM Controller provides the user with the smallest BITBUS building block-a BITBUS component
solution. With its dual processor architecture, this
unique single chip provides both communication and
computational engines (Figure 3). Real-time control

The Basic firmware environment supports the minimum configuration for the BEM to execute as a

MASTER
TASKS
TRANSACTION
PROTOCOL
DATA LINK
PHYSICAL
LINK

PHYSICAL
LINK

/
PHYSICAL
LINK

DATA LINK

TRANSACTION
PROTOCOL

SLAVE TASKS

280129-2

Figure 2. BITBUSTM Architecture

CONTROL
LINES

8051
MICROCONTROLLER

DUAL-PORT
RAM

...-t-~

HDLCI
SOLe
PORT

280129-3

Figure 3. 8044's Dual Processor Architecture

17-69

8044 BITBUSTM Enhanced Microcontroller

BITBUS device. The Extended firmware environment requires hardware incremental to the Basic environment and allows the user to take full advantage
of all the features included in the BEM's firmware.
The designer may implement the Basic or Extended
firmware environment as desired as long as the programmatic requirements of the firmware are met
(see below).

EXTENDED FIRMWARE ENVIRONMENT
(Continued)

Figure 4 shows one example of an Extended firmware environment. This particular example represents the BITBUS Core as used on Intel's iSBXTM
344A BITBUS Controller MULTIMODULETM Board
and iRCB 44/10A BITBUS Remote Controller
Board.

Configuration

OFFFEH external data
space

System RAM

0-02FFH external data
space

Diagnostic LED # 1

Port 1.0 (Pin 1) .

Diagnostic LED # 2

Port 1.1 (Pin 2)

User Task Interface

First Task DescriptorOFFFOH to OFFFFH in
External data space
Other Task Descriptors
and User Code01 OOOH to OFFEFH
in external code space

User RAM Availability

On-Chip-02AH to 02FH
bit space
Off-Cliip-BITBUS
Master: 0400H to
OFFEFH external data
space
BITBUS Slave: 01 OOH to
OFFEFH external data
space

Remote Access and
Control Interface

Memory-Mapped I/OOFFOOH to OFFFFH
external data space

BASIC FIRMWARE ENVIRONMENT

Memory Bus
BITBUS Node Address
Configuration
System RAM
Diagnostic LED # 1
Diagnostic LED # 2

Parallel ports of 80~4
OFFFFH external data
space
OFFFEH external data
space
0-02FFH external data
space
Port 1.0 (Pin 1)
Port 1.1 (Pin 2)

EXTENDED FIRMWARE ENVIRONMENT

Memory Bus
BITBUS Node Address

Parallel ports of 8044
OFFFFH external data
space

ADD·AD7
CONFIG.

BITBUS'" INTERCONNECT.

OPTIONAL

OSC~TOR

DATA

~
DCLKI
·RTSPAIR

12M

ADD·AD7

DATA
SERIAL
NTERFAC

SCLK
110'
RTS'

TAL

,--+

t--

DATA
MEMORV

BEM

f'.--

LS§

L-

AD·AF

<---- .,

t----'\

~ M~~g~Vt-

LATCH

AB·AF

_.-

PMEM:

DECODER r -

C ONCS'

I - - FIFO

10CS'

280129-4

Figure 4. Extended Firmware Environment Example

17-70

intJ

8044 BITBUSTM Enhanced Mlcrocontroller

suits in high performance and reliability for distributed control and processing environments. The intelligent SIU offloads the CPU from communication
tasks, thus dedicating more of its compute power to
external processes.

EXTENDED FIRMWARE ENVIRONMENT
(Continued)

Parallel Interface to
Extension Device

FIFO Command Byte-:OFF01 H external data
space
FIFO Data Byte-OFFOOH
external data space
Receive Data Intr-INTO
(pin 12)
Transmit Data Intr-INT1
(pin 13)
Command/Data BitP1.2

Major features of the 8051 microcontroller are:
• 8-bit CPU
• On-chip oscillator
• 4K bytes of RAM
• 192 bytes of ROM
• 32 I/O lines
• 64K address space external data memory
• 64K address space external program memory
• Two Programmable 16-bit counters

FUNCTIONAL DESCRIPTION

• Five source interrupt structure with two priority
levels

High Performance 8044
Microcontroller

• Bit addressability for Boolean functions
• 1 JA-s instruction cycle time for 60% instructions
2 JA-s instruction cycle time for 40% instructions

TheB044 combines the powerful 8051 microcontroller with an intelligent serial communications controller to provide a single-chip solution that efficiently
implements distributed processing or distributed
control systems. The microcontroller is a self-suffi"
cient unit containing ROM, RAM, ALU, and peripherals. The 8044's architecture and instruction set are
identical to the 8051 'so The serial interface of the
8051 is replaced with an intelligent communications
processor, the Serial Interface Init (SIU), on the
8044. This unique dual processor architecture re-

• 4 JA-s cycle time for 8 by 8 unsigned multiple and
divide
As noted in the Operating Environment discussion,
the BITBUS firmware requires various CPU resources, i.e., memory, timers, .and I/O dependent upon
the firmware environment selected.

FFFF .......- - - - - ,

j!ffi'r-----,

EXTERNAL

OFFF

0fFF
INTERNAL

lEA 11

0000

EXTERNAL
IElIO)

""000,,,,0. ' -_ _---' .

'-------~¥~------~/

!!!1 L-_ _..J

~~-----IN-T:~RN-A-L----'

PROGRAM MEMORY

DATA MEMORV

.. Figure 5. BEM Memory, Map
17-71

0000

EXTERNAL
DATA

MEMORY

280129-5

inter

8044 BITBUSTM Enhanced Mlcrocontroller

Memory Architecture

SIGNAL FUNCTIONS

The 8044 microcontroller maintains. separate data
and code memoryspac:es. Internal data memory
and program memory reside on the controller; External memory resides outside the controller. The BEM
firmware uses the available internal code memory
space and most of the remaining internal data memory with the exception of bit sPlice 02AH to 02FH.
Figure 5 shows the BEM's memory map.

The 8044 BEM's pin configuration and pin description follow.·

P1.0 '
P1.1

m
1/0 ADDRESSING REQUIREMENTs

ffi

P1.4
Pl.5

P1.7

RST

The table bel,ow provides theBEM's lID. port addresses.·
Table 1 BEM 1/0 Addressing
Function

Address

Bit

Red LEDP1.0

90H

Green LED P1.1

91H

TCMD
RFNF#

92H

B3H

TFNF#

B2H

RDY/NE·

B4H

vee

39
38
37

PO.O

3.
35
34
33
32

PO.3
PO.4
PO.5
PO .•
PO.7

PO.l
PO.2

VPP
31 D
PIilIll
30 ALE
29 J5mj
28 P2.7
27 P2.6
26 P2.5
25 P2.4
24 P2.3

TXD

INTI
INTO
TO

Byte

Wli
lID

23 P2.2
22 'P2.1
21 P2.0

280129-6

Figure SA. BEM DIP Pin Configuration

Node Address

FFFFH

Configuration

FFFEH

Reserved

FFEOH-FFFDH

Digital I/O

•FFCOH-FFDFH

SBX #4

FFBOH-FFBFH

Pl.7

39
38
37

SBX #3

FFBOH-FFAFH

RST/VPD
P3.0

10,

3 • . PO.7

SBX #2

FF90H-FF9FH

Hie

SBX #1

FF80H-FF8FH
. FF40H-FF7FH

Reserved

FF02H-FF3FH

P3.1
P3.2
P3.3
P3.4
P3.5

FIFO Command

FF01H

FIFO Data

FFOOH

User Defined

6 5

Pl.5

PI.6

11
12
13
14
15

4 3

I 44 43 42 41 40

35
8044
R0112

PO.'
PO.5
PO ••

Nle

ALE

32
31

PSEN
P2.7
P2 .•
P2.5

280129-26

Figure SB. BEM PLCC Pin Configuration
Table 2 BEM Pin Description
Description

Name
VSS

Circuit ground potential.

Vee

+ 5V power supply during operation and program verification.

PORTO

Port 0 is an 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address
and data bus when using external memory. It is used for data output during program
verification. Port 0 can sink/source eight LS TTL loads.

PORT 1

Port 1. is an 8-bit quasi-bidirectional 110 port. It is used for the low-order address byte during
program verification. Port 1 can sink/source four LS TTL loads.
In non·loop mode two of the I/O lines serve alternate functions:
-RTS (P1.6) Request-to Send output. A low indicates that the 8044 is ready to transmit.
-CTS (P1. 7) Clear-to-Send input. A low indicates that a receiving station is ready to receive.
17-72

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8044 BITBUSTM Enhanced Mlcrocontroller

Table 2. BEM Pin Description (Continued)
Name

Description

PORT 2

Port 2 is an 8·bit quasi·bidirection I/O port. It also emits the high·order address byte when
accessing external memory. It is used for the high·order address and the control Signals
during program verification. Port 2 can sink/source four LS TTL loads.

PORT 3

Port 3 is an 8·bit quasi·bidirectionall/O port. It also contains the interrupt, timer, serial port
and RD and WR pins that are used by various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for that function to operate. Port 3
can sink/source four LS TTL loads.
In addition to I/O some of the pins also serve alternate functions as follows:
• I/O R x D (P3.0). In point·to·point or multipoint configurations, this pin controls the
direction of pin P3.1. Serves as Receive Data input in loop and diagnostic modes.
• DATA T x D (P3.1). In point·to·point or multipoint configurations, this pin functions as
data input/output. In loop mode, it serves as transmit pin. A '0' written to this pin
enables diagnostic mode.
• INTO (P3.2). Interrupt 0 input or gate control input for counter O.
• INT1 (P3.3). Interrupt 1 input or gate control input for counter 1.
• TO (P3.4). Input to counter O.
• SCLK T1 (P3.5). In addition to I/O, this pin provides input to counter 1 or serves as
SCLK (serial clock) input.
• WR (P3.6). The write control signal latches the data byte from Port 0 into the External
Data Memory.
• RD (P3.7). The read control signal enables External Data Memory to Port O.

RST

A high on this pin for two machine cycles while the oscillator is running resets the device. A
small external pulldown resistor (::::: 8.2 Kfl) from RST to VSS permits power·on reset
when a capacitor (::::: 10 p.f) is also connected from this pin to Vee.

ALE/PROG

Provides Address Latch Enable output used for latching the address into external memory
during normal operation. It is activated every six oscillator periods except during an
external data memory access. It also receives the program pulse input for programming
the EPROM version.

PSEN

The Program Store Enable output is a control signal that enables the external Program
Memory to the bus during external fetch operations. It is activated every six oscillator
periods, except during external data memory accesses. Remains high during internal
program execution.

EAIVPP

When held at a TTL high level, the 8044 executes instructions from the internal ROM when
the PC is less than 4096. When held at a TTL low level, the 8044 fetches all instructions
. from external Program Memory. The pin also receives the 21V EPROM programming
supply voltage on the 8744.

XTAL 1

Input to the oscillator's high gain amplifier. Required when a crystal is used. Connect to
VSS when external source is used on XTAL 2.

XTAL2

Output from the oscillator's amplifier. Input to the internal timing circuitry. A crystal or
external source can be used.

Firmware

Basic Firmware Services

The BEM's Basic firmware environment provides
two services: BITBUS Communications and PowerUp Diagnostics. The Extended firmware environment provides the Basic firmware services plus Par·
allel Communications and User Software Services
(iDCX 51 Executive, Remote Access and Control
functions). A discussion of each service follows.

POWER-UP DIAGNOSTICS
INCREASE RELIABILITY
For added reliability and simplified system start up,
the BEM firmware includes power-up diagnostics. At
chip reset the BEM diagnostic firmware checks the
integrity of the 8044's instruction set, ROM, internal

17-73

inter

8044 BITBUSTM Enhanced Microcontroller

RAM, and external RAM. LED indicator lights may
be used to show the progress of the diagnostics.
Intel's BITBUS boards use one red LED, and one
green LED as indicators for test progress. Since the
test halts if a fault is found, the last LED state indicates the trouble area.

BITBUSTM Physical Interface
Irnplementation of the electrical interface to BITBUS
requires external hardware. Specifically, an EIA
Standard RS-485 driver and transceiver and an optional clock source for the synchronous mode of operation. A self clocked mode of operation is also
available. Different modes of operation facilitate a
variety of performanceldistance options as noted in
. Table 4. Figure 7 illustrates the BEM's BITBUS interface hardware requirements.

No programmatic interface exists for the power-up
diagnostics. Only LEOs (or other indicators) connected to the outputs of Port 1 of the 8044 are required. For the test sequence shown in Table 3, the
red LED is connected to pin P1.0, and the green
LED is connected to pin P1.1.

Table 4. BITBUSTM
Interconnect Modes of Operation

Table 3 Power-Up Test Sequence

Max #
Max. Dist
Max #
Nodes
Speed Between
Kb/s Repeaters Between Repeaters
Repeaters
M/ft

State of Port'
After Test Completion
Test Sequence

Red LED
(Pin 1.0)

Green LED
(Pin 1.1)

Power-on

Prior to Start of Tests

Off

Test 1-lnstruction Set

Test2-ROM
Checksum Test

Off

Test 3-lnternal RAM

Off

Test 4-External, RAM

Off

Synchro2400
nous
SelfClocked

30/100

375 300/1000
62.5 1200/4000

28
28

2
10

BITBUSTM Data Link Service

,'Ports are Active Low.

BITBUSTM INTERFACE SIMPLIFIES DESIGN
OF DISTRIBUTED CONTROL SYSTEMS
The BITBUS Serial Control Bus is a serial bus optimized for high speed transfer of short messages in a
hierarchical system. From the perspective of systems using the BITBUS bus there are three external
protocols that must be adhered to: physical" data
link, and transaction control as shown in Figure 2.
The physical interface includes all bus hardware requirements, e.g. cable and connector definition,
transceiver specification. The data link interface refers to the device to device transfer of frames on the
bus. The transaction control interface indentifies the
rules for transmitting messages on the bus as well
as the format of the messages passed.
For maximum reliability and to facilitate standardization the following existing standards were chosen as
portions of the BITBUS Specification: International
Electrotechnical Commission (lEG) mechanical
board and connector specifications, the Electronic
Industry Association (EIA) RS-485 Electrical Specification and IBM"s Serial Data Link Control protocol
for the physical and data link levels of the BITBUS
interface.

The 8044's serial interface unit (SIU) implements a
majority of the data link interface, a subset of IBM's
Serial Data Link Protocol (SDLG), in hardware resulting in a significant performance advantage compared with, multichip solutions. Multichip solutions require both hardware and software glue that degrade
performance, decrease reliability, and increase cost.
This portion of the BITBUS interface requires no
user involvement for execution.
For a detailed discussion of the protocol executed
by the BITBUS data link service. refer to "The
BITBUS Interconnect Serial Control Bus Specification". A basic subset of SDLC with ,the REJECT option is implemented. The standard frame format
transferred across the BITBUS is shown in Figure 8.
The information field carries the BITBUS message.
BITBUSTM Transaction Control Service
For added reliability, the BITBUS interface incorporates error checking at the message level in addition
to the imbedded error checking provided by SDLC at
the data link level. The message control interface
defines the format and function of messages transmitted in frames across the BITBUS bus. (Figure 9)
The transaction protocol requires that for every order message transmitted across the bus a reply
message must be transmitted in return. Error types
and error detection mechanisms are also designated
by this interface.

17-74

inter

8044 BITBUSTM Enhanced Microcontroller

+5Y

ALE

1
;--- D

+5Y

MCLK

oJ--

CK
CLO

CLR

Y
1

0,0---

r--D

o· :>--

0,..,

0
DATA

S DATA

1/0·

------Q

RTS'

-J~

ij>"-I
.,A, , / \

+5Y

--0

0,£

DATA"

DCLK/RTS

DCLK'!

RlS'

---1

-::-

SCLK

280129-7

NOTES:
i. Connect to ground for self-clocked mode and SCLK for synchronous mode.
2. Remove for self-clocked operation with repeater(s).
3. Connect to RTS' for synchronous mode or I/O' for self-clocked mode.
4. Selects MCLK as serial clock source.
5. Selects ALE or oscillator as serial clock source.

Figure 7. BITBUSTM Interface Hardware Requirements

'FLAG' ADDRESS' CONTROL 'INFORMATION' FCS' FLAG'
N

(BYTES)

Figure 8. BITBUSTM Frame Format
MSB

LSB
LENGTH

I SE I DE I TR I RESERVED
NODE ADDRESS

'SOURCE TASK

JDESTINATION TASK

COMMAND/RESPONSE

-+-- ~~:JS~iTTED
MT - MESSAGE TYPE
SE - SOURCE EXTENSION
DE - DESTINATION EXTENSION
TR - TRACK FIELD

DATA

280129-8

Figure 9. BITBUSTM Message Format

17-75

intJ

8044 BITBUSTM Enhanced Microcontroller

BITBUSTM Interface Configuration
The BEM's firmware also simplifies designation of
the bus mode of operation (Speed/distance option)
as well as the node address, memory configuration
and parallel interface parameters by reading two external locations for this information as shown in Fig-

ure 10. The designer no longer needs to directly manipulate the 8044's serial mode register (SMD),
status/command register (STS) , and send/receive
counter register (NSNR). These two 8-bit locations
are derived by multiplexing the 8044's port 0 address lines ADO-AD7.

Node Address Register

BIT2

o
o
o

BIT3

BITO
BIT 1

BIT4
BIT5
BIT6
BIT7

o
o
o
o

ALL JUMPERS REMOVED SELECTS
NODE ADDRESS OOH.
ALL JUMPERS INSTALLED SELECTS
NODE ADDRESS FFH.

280129-9

Mode Register
ESTABLISH THE BITBUS'· MODE IN THE
BEM FIRMWARE. THEY ARE USED ONLY
DURING POWER-UP. BIl'BUS'· MODE AND
BIT RATE ARE AS FOLLOWS:
00 - SYNCHRONOUS
01 - SELF-CLOCKED 375Kb/SEC
10 - RESERVED
11 - SELF-CLOCKED 62.5Kb/SEC.
RESERVED FOR FUTURE USE.
CONNECTED TO THE EA PIN OF THE
8044, ALLOWING INTERNAL ROM TO BE
DISABLED. JUMPER REMOVED ENABLES
INTERNAL ROM.

BITO
BIT 1
BIT 2
BIT3
BIT4
BIT5

o
o~
______
o
.
o
o~
~

CONNECTED TO THE MEMORY DECODE PAL
TO PROVIDE THE TWO MEMORY
ADDRESSING OPTIONS. IN BOTH CASES,

~~~~O::t~;~~T:~I~:: I~F SEPARATE

MAINTAINED. JUMPER REMOVED ROR
OPTION A; JUMI'ER INSTALLED FOR OPTION B.

BIT6
BIT7

~N~itJf~r~~g~~E~I~:~l~~I~~J~

THIS INFORMATION ON
INITIALIZATION. JUMPER REMOVED
INDICATES NO BYTE FIFO.
SELECTS EXTENSION MODE IF
BYTE FIFO IS PRESENT:
0= INTERRUPT
1 =DMA
RESERVED FOR FUTURE USE.

280129-10

NOTE:
Jumper Installed = 1
Jumper Removed = 0

Figure 10. BITBUSTM Firmware Configuration
17-76

inter

8044 BITBUSTM Enhanced Microcontroller

Extended Firmware Services
PARALLEL COMMUNICATION INTERFACE
EXTENDS DISTRIBUTED CONTROL
CAPABILITY
The BEM's firmware also includes a parallel interface for expanding the capabilities of distributed systems. For example, this interface allows other processors to be employed in BITBUS systems if more
processing power is required as shown in Figure 11.
This interface provides the means for connection to
other buses: iSBX bus, STD bus, IBM's PC bus.
'The interface consists of a byte-FIFO queue through
which BITBUS messages can be passd via embedded communications firmware. From the BEM's perspective the user simply designates the correct routing information in the BITBUS message header and
the message is directed to the communications firmware and passed through the parallel interface. One
example of an implementation that uses this interface is the iSBX BITBUS Controller MULTIMODULE
Board via the iSBX bus.
Parallel Interface Hardware
To implement the Parallel Interface, the user must
provide hardware for two FIFOs (one byte minimum)
in external data memory, and control Signals to/from
the 8044's Pins: INTO (PS.2), INT1 (PS.S), and P1.2.
Key hardware elements required are: decoder for
the registers' external addresses, temporary storage
for bytes passing through the interface, a way to
designate bytes as command or data" and a means
to generate the control signals. FIFO's must be used
, ,to move the data through the interface although the
depth of the FIFO need not exceed one byte .

Interface hardware must also be provided for the
"extension" side of the interface. Implementation of
this hardware is left to the user with the restriction
that the operation of the BEM side remains independent.
Parallel Byte Stream and Message Protocol
The two byte registers (FIFOs) provide the path for
bytes to move through the parallel interface. Bytes
are read or written from the registers desigmited:
FIFO Data Byte (FFOOH) and FIFO Command Byte
(FF01 H). INTO,' INT1 and P1.2 provide,control signals to the firmware for moving the bytes through
the registers. These signals' are referred to as the
Parallel Interface Control Bits:
Pin
INTO
INT1
P1.2

Function
RFNF
TFNE'
TCMD

Internal Bit Address
BSH
B2H
92H

The hardware uses RFNF to control the output of
bytes from the BEM. RFNF is set when the FIFO
Data or FIFO Command Byte Registers can receive
information. RFNF remains clear when the FIFO
Data or Command Bytes are not available. Transmission of a BITBUS message' across the parallel
interface consists of successively outputing message bytes to the FIFO Data Byte Register until all
bytes are sent. The firmware then writes a value of 0
to the Command Byte register indicating all the message bytes have been sent. The first data byte in the
message indicates the number of bytes in the message.

;r----'----.:==r
~~

280129-11

Figure 11. Extending the Capability of BITBUSTM System with the Parallel Communications Interface
17-77

8044 BITBUSTM Enhanced Microcontroller

TFNE controls the input of data bytes to the BEM.
This bit is set when bytes are available for reading.
When no bytes are available this bit is clear. TCMD
indicates whether the next byte read is a Data Byte
or Command Byte. BITBUS messages are received
by inputing data bytes until a command byte is received. Data bytes are read from ttie FIFO Data Byte
Register. Command Bytes are read from the FIFO
Command Byte Register.
Figure 12 provides one example of a Byte FIFO Interface. This specific example illustrates the interface provided on the iSBX 344A BITBUS Controller
MULTIMODULE Board. Figure 13 shows transmission of bytes from the BEM across the parallel interface. Figure 14 shows transmission of.bytes to the
BEM:

SEND MESSAGE

TO BITBUS"INTERCONNECT

WRITE
NEXT'
DATA

r----------------,
I
I
IS8X"344 B O A R D . .

BYTE

I
I

8EM

I
I
I

8044 LOCAL 8US

w:g:

RFNF'

TRANSMIT
FIFO

YES

RECEIVE
FIFO

TFNF'
:~=~',
L ____________
-'- ___ -.J

EXTENSION DEVICE CPU

WRITE
END OF
MESSAGE
COMMAND

LOCAL8US

EXTENSION
DEVICE CPU

280129-12

Figure 12. Byte FIFO Interface Example

RETURN

280129-13

Figure 13. Transmitting a Message from BEM
17-78

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8044 BITBUSTM Enhanced Mlcrocontroller

RECEIVE MESSAGE

1988_OEM_Boards_and_Systems_Handbook 1988 OEM Boards And Systems Handbook

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