1988_OKI_Microcontroller_Data_Book 1988 OKI Microcontroller Data Book
User Manual: 1988_OKI_Microcontroller_Data_Book
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DATA BOOK
OKI
MICROCONTROLLER
criteriD~
manufacturers representatIVe
(408) 988-6300
3350 Scott Blvd ., Bldg. 4
4 S nte Clara, CA 95054
, a
THIRD EDITION
ISSUE DATE: MAR 1988
PREFACE
A high technology company with an aggresive approach to innovation, OKI has been
supplying single-chip microcontrollers since 1975. OKI's single-chip microcontrollers
find wide application in various types of electronic equipment in the consumer and the
industrial fields. Our products have been enjoying a good reputation for their high
quality and high performance. The most outstanding feature employed in all of OKI's
microcontrollers is CMOS technology which ensures low power operation.
OKI will continue to enhance the its microcontroller series and program development
systems to cater to cutomers' requirements.
CONTENTS
1. PROGRAM DEVELOPMENT SYSTEM . ................................................. .
2. LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
3. CODE ENTRY ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
1. USABLE MEDIA... .... .... . ... ............ . . . ....... ..... ....... . ... ............. ...
17
2. SINGLE CHIP MICROCONTROLlER DEVELOPMENT STAGES........................
18
4. PACKAGING...........................................................................
19
5. RELIABILITY INFORMATION...........................................................
33
6. DATA SHEET..........................................................................
43
•
•
OlMS-40 SERIES .................................................... , . . . . .. .. . . . . .
45
MSM5840 .........................................................................
47
MSM5842 .........................................................................
58
MSM58421 ........................................................................
66
MSM58422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
MSM5847 .........................................................................
84
OlMS-50/60 SERIES ..............................................................
89
MSM5052 .........................................................................
~
MSM5054 .........................................................................
98
MSM5055 ......................................................................... 105
MSM5056 ......................................................................... 112
MSM6051 ......................................................................... 119
MSM6351 ......................................................................... 1~
MSM6052 ......................................................................... 139
MSM6352 ......................................................................... 149
•
OlMS-64 SERIES. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
161
MSM6404 ......................................................................... 163
MSM6404VS ...................................................................... 175
MSM6408 ......................................................................... 177
MSM6411 ......................................................................... 188
MSM6422 ......................................................................... 199
MSM6442 ......................................................................... 207
MSC6458 ......................................................................... 217
MSC6458VS ........................................................................ 233
iii
•
OlMS-65 SERIES ................................................................... 235
MSM6502/6512 ............................................ , ....................... 237
•
8 BIT SERIES (OKI ORIGINAL) ....................................................... 247
MSM62580 ......................................................................... 249
MSM66301 ......................................................................... 258
•
8 BIT SERIES (INTEL COMPATIBLE) ................................................. 281
MSM80C35/48, MSM80C39/49, MSM80C40/50 .................................... 283
MSM80C31 F/MSM80C51 F ......................................................... 308
MSM80C154/MSM83C154 ......................................................... 333
MSM85C154VS .................................................................... 367
7. PROGRAM DEVELOPMENT SUPPORT SYSTEMS . ....................................... 369
EASE40 ............................................................................... 371
EASE6400 ............................................................................. 380
EASE6502 ............................................................................. 390
EASE80C49 ........................................................................... 400
EASE80C51/mkii ...................................................................... 411
MAC51 ............................................................................... 420
iv
11
PROGRAM DEVELOPMENT
SYSTEMS
PROGRAM DEVELOPMENT SYSTEMS FOR
OKI MICROCONTROLLERS
11
OLMS-40 SERIES
target chip
MSM5840
MSM5842
development tool
package name
standard software
(included in package)
adaptor module
(if necessary)
EASE 40
(SERIAL INTERFACE)
(BUS INTERFACE)
DB400 debugger
ASM40 cross assembler
-
MSM58421
MPB421
MSM58422
MPB422
MSM5847
dedicated hardware
simulator
field debugging
tool
MPB202
-
-
[Note]
1. The standard software DB400 and ASM40 are avalable on CP/M-80 for most personal computers, or ISIS-II for
INTEL MOS.
CP/M is a registered trade mark of Digital Research, and ISIS-II, MDS of Intel.
LOW POWER SERIES
target chip
development tool package name
standard software
MSM5052
EASE5052/5S
MSM505S
MSM5054
EASE5054/55
MSM5055
MSMS051
(EASES051)
EASE
host
monitor
ASM50
cross assember
MSMS351
(EASES351/S353)
MSMS353
MSMS052
EASES052, (EASES352/S052)
MSMS352
(EASES352/S052)
[Note]
1. The standard software is avilable under following operating system.
CP/M-80 for most of personal computers
MSOOS for OKI if800, NEC PC9801 etc.
PCDOS for IBM PC-XT, AT, IBM 5550
3
e PROGRAM DEVELOPMENT SYSTEMS
e - - - - - - - - - -____
OLMS-64 SERIES
target chip
development tool
package name
I/O adaptor
module
MSM6404
-
MSM6408
-
standard software
(included in package)
field debugging
tool
-
(ASM6408)*
-
MSM6402
MSM6404VS
-
EASE6400
EASE
host
monitor
ASM6400
MSM6422
PAM6422
MSM6411
PAM6411
PEM6411
MSM6442
PAM6442
PEM6442
MSC6458
[Note]
EASE6458
Piggyback
-
PEM6422
ASM6458
-
MSC6458VS
The standard software is available under following operating system.
EASE, ASM6400, ASM6458 ...... CP/M-80 for most personal computers,
MSDOS for OKI if800, NEC PC9801 etc.
PCDOS for IBM PC-XT, AT, IBM 5550
* ASM6408 ...................... CP/M-80 version.
ASM6400 Covers MSDOS and PCDOS for MSM6408.
OLMS-65 SERIES
target chip
development tool
package name
standard software
(included in package)
field debugging tool
MSM6502/6512
EASE6502
EASE65
ASM6502
MPB6502EVA
[Note]
The standard software is available under CP/M-80, MSDOS, or PCDOS.
8 BIT SERIES (INTEL· compatible)
target chip
development tool
standard software
option al software
piggyback
EASE80C49
EASE49
ASM49
-
-
EASE
See Note 1.
MSM80C48
MSM80C49
MSM80C50
MSM80C51F
MSM83C154
EASE80C5imKil
ASM51
MSM85Ci 54VS
[Note]
1. Optional Software for MSM80C51 /83C 154
PASM preprocessor, MAC51 relocatable assembler, RL51 object linker, LlB51 librarian SID51 symbolic debugger
2. The softwares are available under following operating system.
EASE49 .............................. CP/M-80,ISIS-1I
ASM49 ............................... CP/M-80,ISIS-1I
EASE&ASM51 ....................... CP/M-80forOKI if 800, NECPC8801 etc.
MSDOS for OKI if800, NEC PC9801 etc.
PCDOS for IBM PC-XT, AT, IBM 5550
PASM, MAC51 , RL51, LlB51
MSDOS forOKI if80, NEC PC9801 etc.
SID51
PCDOS for IBM PC-XT, AT, IBM 5550
4
- - - - - - - - - - - - - - - . PROGRAM DEVELOPMENT SYSTEMS.
8 BIT SERIES (OK I original)
development tool
package name
standard software
(included in package)
optional software
MSM66301
EASE66301
ASM66301
EASE
SeeNote1.
MSM62580
EASE62580
AS62580
EASE
target chip
[Note)
1. Optional Software for MSM66301
c-compiler (VMS for uVAX-1I)
relocatable assembler (VMS)
object linker and librarian (VMS)
cc66 debuger (VMS)
symbolic debugger (VMS)
• underdevelopment
5
11
LINE-UP AND TYPICAL
CHARACTERISTICS
• OLMS-40 SERIES
TYPE NO.
MSM5840
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
5V
4.2MHz
2048 x 8
128x 4
6
16
32 )(4
5
CMOS
MSM5842
CMOS
5V
4.2MHz
768x8
MSM5B421
CMOS
5V
4.2MHz
1536)(8
40x4
5
MSM58422
CMOS
5V
4.2MHz
1536)(8
40)(4
5
MSM5847
CMOS
3V
32kHz
1536x8
96x4
-
8
35LCD Seg.
SLeD Seg. or LOGIC
7)(5 FLT Seg.
5Discreate
24 x 3leC Seg.
1/0
PORT
TIMER
COUNTER
8
8 Bit R/W
INTER·
INSTRUC MACHINE
STACK
RUPT
CYCLE
TION
POWER CONSUMPTION
ACTIVE
STAND-BY
PACKAGE
2
4
98
7.6,,5
1.6mA
-
42DIP/44FlAT
1
52
7.6~S
1.SmA
-
280lP/32FLAT
8
8 Bit
-
B
12 Bit
-
1
52
7.6,...5
2.OmA
-
60FLAT
8
12 Bit
-
1
52
7.6,...5
2.OmA
-
60FLAl
7
13 Bit
-
2
43
61O"S
50""
-
44FlATICHIP
REMARKS
-----
•
• OLMS-50/60 SERIES
TYPE NO.
MSM5052
PROCESS
CMOS
POWER
SUPPLY
VOLTAGE
1.5V
CLOCK
FREQUENCY
32kHz
ROM
(BIT)
1280x14
RAM
(BIT)
62x4
INPUT
PORT
B
OUTPUT PORT
26 x 2LCD Seg.
S LOGIC
110
PORT
TIMER
COUNTER
INTER·
INSTRUC MACHINE
STACK
RUPT
TION
CYCLE
ACTIVE
PACKAGE
C
z
m
REMARKS
STAND·BY
-
-
-
-
42
122,...5
3""
-
CHIP
-
-
-
-
40
1221'S
3""
-
CHIP
Built-in temperature detector
CMOS
1.5V/3V
32kHz
1024x 14
62x4
6
MSM5055
CMOS
1.5V/3V
32kHz
1792)( 1
96)(4
B
60 x 2lCO Seg.
4 lOGIC
-
-
-
-
42
122,...5
3.A
-
CHIP
VOICE
CONTROLLER
MSM5056
CMOS
1.5V
32kHz
1792)( 14
90x4
4
38 x 2LCO Seg.
-
-
-
-
42
122,...5
3""
-
CHIP
Connection with
solar cell available
MSM6051
CMOS
1.5V/3V
32kHz
2560 x 1
120x4
9
63 x 3lCO Seg.
4 LOGIC
-
-
1
2
59
91. 511S
3""
-
CHIP
-
59 x 3lCD Seg. or
58 x 4LCD Seg.
20
-
3
7
65
61.0,.$
3.A
-
CH'IP/100FLAT
CMOS
1.5V/3V
32kHz
4096 x 15 1024x
4 LOGIC
MSM6353
CMOS
1.5V!3V
32kHz
4096 x 15 1024 x 4
-
-
20
MSM6052
CMOS
3V
3.58MHz
2048 x 14 640x4
12
12
4
MSM6352
CMOS
3V
3.58MHz
2048 x 14 640 x
12
12
4
-
3
7
4 Bit
1
5
4 Bit
2
5
-
~
'tI
o»
%
52
17.911S
1.2mA
0.2""
28DIPI40DIP /
MFLAT
Built-in DTMF
52
17.9I1S
1.SmA
0.2""
2BDIPI40DIP I
44FLAT
Built-in DTMF
on-hook dialing
...
C
»
:u
»
(')
CHIPI
42PINS-DiP
3""
.
'tI
.-(')
60.0""
..
C:::
»
Z
MSM5054
44 x 2lCD Seg.
4 LOGIC
MSM6351
Z
C
• OlMS-54 SERIES
TYPE NO.
MSM6404
PROCESS
CMOS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
5V
4.2MHz
4000)( 8
256 x 4
4
-
4
-
32
110
PORT
32
TIMER
COUNTER
INTER·
RUPT
STACK
12 Bit
12 Bit R/W
bit R/W
5
32
121
12 Bit R/W
8 Bit R/W
5
32
a
INSTRUC. MACHINE
TION
CYCLE
POWER CONSUMPTION
-I
PACKAGE
REMARKS
-<
:3!
ACTIVE
STAND·BY
952n5
6mA
1.A
42DIP/44FLAT
121
1.S
6mA
1.A
42DIP/44FLAT
o
l>
r-
o
12 Bit
MSM640B
CMOS
5V
4.0MHz
8096 x 8 256x 4
MSM6411
CMOS
5V
4.2MHz
1024x 8
32 x4
4
-
8
-
2
8
63
952n5
6mA
1.A
16DIP/24FLAT
MSM6422
CMOS
5V
4.2MHz
2048 x 8
64x 4
1
-
18
12 Bit
2
16
63
952n5
6mA
1.A
16DIP/24FLAT
MSM6442
CMOS
5V
4.2MHz
2048 x 8
4
1
46 x 2LCD Seg.
16
4
16
76
952n5
6mA
1.A
BOFlAT
MSC6458
Bi-CMOS
5V
4.3MHz
8192 x 8 512 x 4
9
12)( 12FLT Seg.
24
8
32
147
930n5
9mA
1.A
STACK
::E:
l>
:D
l>
o-I
m
128
x
8 Bit R/W
12 Bit
16 Bit A/W
8 Bit R/W
I
en
64 FLAT
Built-in FLT Controller/Driver
otJ)
PACKAGE
REMARKS
64 Shrink DIP/
• OlMS-55 SERIES
TYPE NO.
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
2000 x 8
MSM6502
CMOS
3V
32kHz
MSM6512
CMOS
3V
32k~~ __
I 2000 x 8
INSTRUC- MACHINE
TION
CYCLE
COUNTER
INTER·
RUPT
10alCD Seg.
8
12 Bit
3
32
68
91.5p.S
45p.A
108lCO Seg.
8
12 Bit
3
32
68
9 1.5p.S
30p.A
OUTPUT PORT
128x 4
4
128 x 4
4
I
TIMER
110
PORT
INPUT
PORT
I
POWER CONSUMPTION
ACTIVE
STAND·BY
I
1
:D
Built-in LCD Controller/Driver
30p.A
44FLAT/CHIP
12p.A
44FLAT/CHIP
:::!
• 8 Bit SERIES (INTEL compatible)
TYPE NO.
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
1/0
TIMER
PORT
COUNTER
INTER·
RUPT
STACK
INSTRUC- MACHINE
TION
CYCLE
POWER CONSUMPTION
ACTIVE
STAND-BY
PACKAGE
REMARKS
MSM80C35
CMOS
5V
l1MHz
-
64)( 8
-
24
8 Bit A/W
2
8
11'
1.36,,5
lOrnA
'FA
4QOIP/44FlAT
M$M80C39
CMOS
5V
l1MHz
-
128 x 8
-
24
8 Bit R/W
2
8
11'
1. 3611 5
lOrnA
'FA
40DIPf44FLAT
MSM80C40
CMOS
5V
6MHz
-
256)( 8
-[
24
8 Bit RiW
2
8
11'
2.5"S
lOrnA
'FA
40DIP/44FLAT
MSM80C31F
CMOS
5V
16MHz
-
128
MSM80C154
CMOS
5V
16MHz
-
256x 8
MSMBOC48
CMOS
5V
l1MHz
1024
x
8
MSM80C49
CMOS
5V
l1MHz
2048
l(
8
128
MSMBOC50
CMOS
5V
6MHz
4096
x
8
MSM80C51F
CMOS
5V
16MHz
4096
x
8
--CMOS
MSM83C154
5V
I
I
16MHz
16384
x
I
- I
32
16 Bit R/Wx2
5
64
11'
0.75,,5
20mA
'FA
400IP/44FlATI
44PLCC
32
16 Bit R/Wx3
6
'28
11'
O.7S/lS
20mA
'FA
400IP/44FALT I
44PlCC
24
8 Bit AIW
2
8
11'
1.36,,5
lOrnA
'FA
40DIP/44FLAT
I
24
8 Bit RtW
2
8
11'
1.36,,5
lOrnA
'FA
40DI?/44FLAT
256x 8
- I
24
8 B.t RIW
2
8
11'
2.5,,5
lOrnA
'FA
40DIP/44FLAT
128
x
8
- I
32
16 Bit AIWx2
5
64
11'
0.75,,5
20mA
'FA
400IP/44FlATi
44PLCC
8 256
x
8
-
'FA
400lPI 44FlATI
44PLCC
x
8
64x 8
x
8
-
-+--
-
I
I
32
I
16 Bit AIWx3
6
'28
11'
0.75FS
20mA
•
r
Z
m
c•
'U
:J>
Z
o
~
'U
• 8 BIT SERIES (OKI original)
POWER
TYPE NO.
PROCESS
MSM62580
CMOS
SUPPLY
VOLTAGE
5V
CLOCK
FREQUENCY
5MHz
INPUT
PORT
RAM
(BIT)
ROM
(BIT)
3072 x 8
128
x
8
OUTPUT PORT
110
,
-
TIMER
COUNTER
PORT
I
-
INTERINSTRUC- MACHINE
STACK
RUPT
TION
CYCLE
-
32
95
800n8
POWER CONSUMPTION
ACTIVE
4mA
PACKAGE
10p.A
C.O.B.
MSM6630'
I
CMOS
5V
10MHz
x
a
512>< 8
B
For ICcards
under development
16384
REMARKS
STAND-BY
I
I
40
16 Bitx4
'7
256
99
400n5
-
-
64 Shrink DIPI
68 PLCCI
64 FLAT
--------
Under development (PGB type)
• AIDC 8ch. lObit
• UART
·PWM
• Chapter' register
o:J>
r
n
::z::
:J>
:D
:J>
n
-I
m
:D
iii
-I
oen
•
~
• LINE-UP AND TYPICAL CHARACTERISTICS . - - - - - - - - - - - - -
lOW POWER
HIGH SPEED
OLM-50/60 SERIES
OLM-64 SERIES
POWER
CONSUMPTION
TYPE NO.
ROM
RAM
MACHINE
CYCLE
52 Seg. LCD Driver
MSM6404
4OOOx8
256 x 4
952nS
110;36
3pA
88 Seg. LCD Driver
MSM6408
8096x8
256x4
95208
110;36
96x4
3pA
120Seg. LCODriver
MSM6411
1024x8
32x4
952nS
110;11
1792 x 14
9Ox4
3pA
76Seg. LCD Driver
MSM6422
2048x8
64x4
95208
110; 19
MSMOO51
2560 x 14
120x4
3pA
189Seg. LCD Driver
MSM6442
2048x8
128x4
95208
92Seg. LCD Driver
MSM6052
6352
2048 x 14
640 x 4
1.anA
1.anA
DlMF Generator
MSM6458
8192x8
512x4
9:lOnS
144 Seg. FLT Driver
MSM6351
4096 x 15
1024x4
3pA
232 Sag. LCD Driver
3pA
Serial board (Synchronisedl
Non synchronised)
TYPE NO.
ROM
MSM5052
1280 x 14
62x4
3pA
MSM5054
1024 x 14
62x4
MSM5055
1792 x 14
MSM5056
MSM6353
4096 x 15
RAM
1024x4
FEATURES
FEATURES
OLM-40/65 SERIES
TYPE NO
ROM
RAM
MACHINE
CYCLE
FEATURES
MSM5840
2048x8
12Bx4
7.6"S
110;30
MSM5842
768x8
32x4
7.6~
110;21
MSM58421
1536x8
4Ox4
7.6~
35Seg.LCDDriver
MSM58422
1536xB
4Ox4
7.6~
35 Sag. FLT Driver
MSM5847
1536xS
96x4
600~
72Seg.LCDOriver
MSM6502
2OOOx8
12Bx4
91.5~
lOBSeg. LCD Driver
TYPE NO.
ROM
RAM
MACHINE
CYCLE
FEATURES
MSM6512
2OOOx8
128x4
91.5"S
l04Seg. LCD Driver
MSM625IlO
3072x8
128x8
BOOnS
Built-in EEPAOM2048xS
4BIT
IC CARD
ONE CHIP MICROCOMPUTER FOR IC CARD
BBIT
L'-------------JnL---OKI ONE CHI
12
- - - - - - - - - - - - - . LINE-UP AND TYPICAL CHARACTERISTICS.
I HIGH PERFORMANCE I
MSM80C154 SERIES
TYPE NO.
HIGH PERFORMANCE
nX SERIES
OLMS-66K SERIES
D
ROM
RAM
MACHINE
CYCLE
TYPE NO.
ROM
RAM
MACHINE
CYCLE
16384 x 8
256 x 8
75On5
MSM66301 "
16384x8
512x8
400n5
256)(8
75On5
--~-~-
MSM83C154
MSMBOC154
MSM80C51 SERIES
D
TYPE NO.
ROM
RAM
MACHINE
CYCLE
MSM80C51/51F
4096x8
128x8
O.75~S
128)(8
0.75"5
MSM80C31 /31 F
MSM80C48 SERIES
16BIT
0
TYPE NO.
ROM
RAM
MACHINE
CYCLE
MSM80C48
1024)(8
64x8
1.36,.8
MSM80C49
2048x8
128x8
).36,.8
MSM8OCSO
4095x8
256x8
2.5,.8
64x8
1.36~S
MSM80C39
128)(8
1.36"5
MSM80C40
256x8
2.5~S
MSM80C35
r--
8BIT
UCROCOMPUTER
13
CODE ENTRY
------------------------------------------eCODEENTRVe
CODE ENTRY
The program code ENTERING method is outlined below.
1. USABLE MEDIA
(1) 2 pieces of same type EPROMs containing identical DATA
D
EPROM specification
2716
2732
27C32
27C32A
2764
27C64
27128
27256
(2) 1 copy of object machirie code list
17
• CODE ENTRY. - - - - - - - - - - - - - - - - - - - - - - -
2. SINGLE CHIP MICROCONTROLLER DEVELOPMENT STAGES
USER 1
D
• Program with OKI development tool.
TOOL
if 800
USER 2
• Prepare 2 pcs of EPROM and programming list
EPROM
OKI3
Ij I1
OKI4
Printout
• Print out identical EPROM da:t:a~.'/1l"J'11-~~~~~"tf.flO'l
......
• Engineering Sample
Actual production sample of your microcontroller
chip prepared for final approval.
. -,
(PO- ······~rr\tO~~~
:;
l"~~
OKI5
18
---
• Volume production of single chip microcontrollers.
PACKAGING
PACKAGING
PACKAGE/PIN COUNT
DIP
FLAT
PLCC
MSM5840
42PIN
44PIN
-
MSM5842
28PIN
32PIN
-
MSM58421
-
60PIN
-
MSM58422
-
60PIN
-
MSM5847 '
-
44PIN
-
MSM5052 '
-
56PIN
-
MSM5054 '
-
56PIN
-
MSM5055 '
-
BOPIN
-
MSM5056,
-
-
-
MSM6051 '
-
-
-
MSM6351 '
-
100PIN
-
MSM6052
28/40 PIN
44PIN
-
MSM6352
28/40 PIN
44PIN
-
MSM6404
42PIN
44PIN
44PIN
-
-
MSM6404VS
42 PIN PIGGY BACK
MSM6408
42PIN
44PIN
44PIN
MSM6411
16PIN
24 PIN
-
MSM6422
24PIN
24PIN
-
MSM6442
-
80PIN
-
MSC6458
64 PIN SHRINK
64PIN
68PIN
MSC6458VS
64 PIN SHRINK
PIGGYBACK
-
-
NOTE: • CHIP TYPE is available.
21
• PACKAGING . - - - - - - - - - - - - - - - - - - - - - - - - -
PACKAGE/PIN COUNT
DIP
PLCC
MSM6502'
-
56PIN(S)
-
MSM6512'
-
56PIN(S)
-
MSM62580
-
COB (5PIN)
-
MSM66301
64 PIN SHRINK
64PIN
68PIN
MSM80C35
40PIN
44PIN
44PIN
MSM80C39
40PIN
44PIN
44PIN
MSM80C40
40PIN
44PIN
44PIN
MSM80C31
40PIN
44PIN
44PIN
MSM80C48
40PIN
44PIN
44PIN
MSM80C49
40PIN
44PIN
44PIN
MSM80C50
40PIN
44PIN
44PIN
MSM80C31F
40PIN
44PIN
44PIN
-
-
MSM80C51 FVS
40 PIN PIGGY BACK
MSM80C51F
40PIN
44PIN
44PIN
MSM80C154
40PIN
44PIN
44PIN
MSM83C154
40PIN
44PIN
44PIN
-
-
MSM85C154VS
40 PIN PIGGY BACK
NOTE: (S) means Small pachage
22
FLAT
------------------------------------------------•• PACKAGING •
• 16 PIN PLASTIC DIP
(Unit:mm)
7.62±O.30
0°_15°
2.54±o.25
SEATING PLANE
• 18 PIN PLASTIC DIP
Ii
24.5
(Unit:mm)
MAX
2.54±O.25
O~15°
SEATING PLANE
23
• PACKAGING . - - - - - - - - - - - - - - - - - - - - - - - • 24 PIN PLASTIC DIP
(Unit:mm)
15.24±030
2.54 ;to.2 5
"l!"l
~
NI
00-IS'
SEATING PLANE
.28 PIN PLASTIC DIP
(Unit:mm)
15.24±030
SEATING PLANE
24
• PACKAGING •
• 40 PIN PLASTIC DIP
52.8 MAX
(Unitmm)
15.24±030
SEATING PLANE
• 42PIN PLASTIC DIP
52.8
(Unit: mm)
MAX
15.24±030
2.54±025
SEATING PLANE
25
• PACKAGING . , - - - - - - - - - - - - - - - - - - - - - - - • 64 PIN SHRINK DIP
58.0 MAX
(Unit: mm)
19.05±0.30
26
------------------------------------------------ePACKAGING e
• 24 PIN PLASTIC FLAT
(Unit:mm)
o
ill
INDEX MARK
@
• 32 PIN PLASTIC FLAT
(Unit:mm)
0.1-0.3
INDEX MARK
27
• PACKAGING ...- - - - - - - - - - - - - - - - - - - - - - • 44 PIN PLASTIC FLAT
I
(Unit:mm)
14.5±o.4
10.5 ±O.3
~
O· _10·
INDEX MARK
• 56 PIN PLASTIC FLAT
(Unlt:mm)
14.5±O.4
10.5±0.3
INDEX MARK
28
- - - - - - - - - - - - - - - - - - - - - - -.... PACKAGING.
• 60 PIN PLASTIC FLAT
(Unit:mm)
24.0"'0.•
2.4"'0.2
1.0"'01
(i)
INDEX MARK
• 80 PIN PLASTIC FLAT
(Unit:mm)
25.0"'0.•
2.1 ±0.2
0-10'
0.2±015
~
INDEX MARK
\
0.15
29
• PACKAGING . - - - - - - - - - - - - - - - - - - - - - - - -
• 44 PIN PLASTIC PLCC
( u.n tmax:mm)
t=-min:mm
INDEX MARK
1.27 TYP
4.57
4.
-.,
I\.:l
.....
..'"
~
I•
16.00
14.99
•
I
• 68 PIN PLASTIC PLCC
.
max:mm)
~Untt=--min:mm
t"'"
I\.:l
......,
'"
.
~
I•
30
23.62
22.61
•
I
- - - - - - - - - - - - - - - - - - - e . PACKAGING.
• 40 PIN PIGGY BACK
(Unit:mm)
~~m~m~~~iiiliilj
0.6
MAX
II
I
I
I
!2.54±025
Hr
Til .
035
MAX
15.24±030
r
"1
• 42 PIN PIGGY BACK
(Unit:mm)
31
e PACKAGING
e----------...,---------------
• 64 PIN SHRINK PIGGY BACK
(Unit: mm)
I'
58.00
---I
lQlQl>=:1~~:l~~
I
UP'l~L' 'IV1J.S:
Shipment
Delivery
'<
~
~ ~aCkagingl
~
Transportation
Control
II
3
Failure
Report
Analysis
n
Service
~
1
-Quality Assurance
& Quality Control
Staff Activities
Reliab'lit~1
Reliability
Engineering
•
:XI
m
r-
I
~
;+
en
Customer
!!!
Inspection
g
Maintenance
Service
I
c:
w
XXRS
250 g 90· BEND
3 TIMES
Solderability
I-
MSM80C35/39/48149·
(5min) (5min)
10 cycles
~
Sake 112S·C, 24h,01
Immerse into Flux
Immerse into Solder
(215±2°C 10:tlsec)
22
0
22
0
Referred
standard
MIL·
STD883C
METHOD
2004
MIL
STD883C
METHOD
2003
- - - - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION.
4. SEMICONDUCTOR MEMORY
FAILURES
The life-span characteristics of semiconductor
elements in general (not only semiconductor Ie
devices) are described by the curve shown in the
diagram below. Although semiconductor
memory failures are similar to those of ordinary
integrated circuits, the degree of integration
(miniaturization), manufacturing complexity and
other circuit element factors influence their incidence.
al conditions) in the development stage to
reduce this type of failure. In addition to checking
endurance against surge currents, special protective circuits are incorporated in the input and
output sections.
~
AI
? ~.
~n~~ection
Aluminum
.
' __Wli'&·~!
/
f
wire
i
Poly Si
Destruction
position
Semiconductor Element Failure Rate Curve
Initial SHIPPING
failure
+
Wear-out
Random _ _ _--i....f~ailure
failure
\
m>
\
1
I
\
\
\
,,
"
m<1.
General
electronic
devices
m=1
-------
/
/
J-- .//
•
--+-Time
~
Debugging by burn-in
screening
//
Semiconductor
elements
1) Surge Destruction
This is destruction of the input/output stage circuits by external surge currents or static electricity. The accompanying photograph shows a
point of contact between aluminum and polysilicon that has been dissolved by a surge cur··
rent. A hole has formed in the substrate silicon,
leading to a short circuit. This kind of failure is
traceable in about 30% of defective devices returned to the manufacturer. Despite miniaturization of semiconductor memory component elements (which means the elements themselves
are less resistant), these failures usually occur
during assembly and other handling operations.
At Oki, all devices are subjected to static electricity intensity tests (under simulated operation-
Example of surge destruction
2) Oxide Film Insulation Destruction (Pin Holes)
Unlike surge destruction, this kind of failure is
caused by manufacturing defects. Locally weakened sections are ruptured when subjected to
external electrical stress. Although this problem
is accentuated by the miniaturization of circuit
elements, it can be resolved by maintaining an
ultra-clean manufacturing environment and
through 100% burn-in screening.
3) Surface Deterioration due to Ionic Impurities
Under some temperature and electric field conditions, charged ionic impurities moving within the
oxide film previously resulted in occasional deterioration of silicon surfaces. This problem has
been eliminated by new surface stabilization
techniques.
4) Photolithographic Defects
Integrated circuits are formed by repeated photographic etching processes. Dust and
scratches on the mask (which corresponds to a
photographic negative) can cause catastrophic
defects. At present, component elements have
been reduced in size to the order of 1 0 cm
through miniaturization. However, the size of
dust and scratches stays the same. At Oki, a
high degree of automation, minimizing human intervention in the process, and unparalleled
cleanliness, solves this problem.
Photolithographic Defect
41
• RELIABILlTVINFORMATION . - - - - - - - - - - - - - - - - - 5) Aluminum Corrosion
Aluminum corrosion is due to electrolytic reactions caused by the presence of water and
minute impurities. When aluminum dissolves,
lines break. This problem is unique to the plastic
capsules now used widely to reduce costs. Oki
has carefully studied the possible cause and
effect relationship between structure and manufacturing conditions on the one hand, and the
generation of aluminum corrosion on the other.
Refinements incorporated in Oki LSls permit superior endurance to even the most severe high
humidity conditions.
6) Alpha-Particle Soft Failure
This problem occurs when devices are highly
miniaturized, such as in 1 megabit RAMs. The inversion of memory cell data by alpha-particle
generated by radio-active elements like uranium
and thorium (present in minute quantities, measured in ppb) in the ceramic package material
causes defects. Since failure is only temporary
and normal operation restored quickly, this is
referred to as a "soft" failure. At Oki we have
eliminated the problem by coating the chip surface of 1 megabit RAMs with a resin which effectively screens out these'alpha-particles.
7) Degradation in Performance Characteristics
Due to Hot Electrons
With increased ·miniaturization of circuit elements, internal electric ·field strength in the channels increases since the applied voltage remains
the same at 5V. As a result, electrons flowing in
the channels, as shown in the accompanying diagram, tend to enter into the oxide film near the
drain, leading to degradation of performance. Although previous low-temperature operation tests
have indicated an increase of this failure, we
have confirmed by our low-temperature acceleration tests, including checks on test element
groups, that no such problem exists in Oki LSls.
Drain
VD
G~ ~Source
:
+VG
I
Drain
P
Package ceramic
-;-=-C":":""'"7-:-.,....,.f--~.,..,..",..,.,-~ Silicon oxide
-,,---'-'---'-r""-,+!-~~-+"'-'""-'--'- Ii I m
Substrate silicon
/
++---
..
a-particle
IonIZation along
the ,,-particle path
42
Hot electrons
Substrate sil icon
Characteristic deterioration caused
by hot electrons
With further progress in the miniaturization of circuit components, failures related to pin hole
oxide film destruction and photolithography have
increased. To eliminate these defects during
manufacturing, Oki has been continually improving its production processes based on reliability
tests and information gained from the field. And
we subject all devices to high-temperature burnin screening for 48 to 96 hours to ensure even
greater reliability.
DATA SHEETS
OLMS-40 SERIES
H
OKI
semiconductor
MSM5840
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM5840 microcontroller is a low-power, high-performance single chip device implemented in complementary metal oxide semiconductor technology. Integrated within this one chip are
16K bits of mask program ROM, 512 bits of data RAM, 30 Input/Output lines, a programmable
timer/counter, and oscillator. Program memory is byte wide and data-paths are organized in 4 bit nibbles. RAM and I/O lines are bit addressable. Up to 4K of external ROM interfaces to the 8 bit bidirectional bus. 98 instructions include binary, BCD, logical operations; bit set, reset, test, 8 bit I/O; relative
jumps; multifunctional instructions (increment, modify, skip); 8 bit wide table output; subroutine call
and return. 94% of instructions are single byte, single cycle operations.
FEATURES
•
•
•
•
•
•
•
•
•
Low Power Consumption - 8mW Typical
100% Static Logic - 50JLW Standby, Typical
2K x 8 Internal ROM
Up to 4K x 8 External ROM
128 x 4 Internal RAM
30 I/O Lines Incl. 8 Bit Data Bus
Programmable 8 Bit Timer/Counter
Sell-contained Oscillator
98 Instructions
• Expandable Memory and I/O
• 2 I nterrupt Levels
• 4 Stack Levels
• Operating Temperature
-40° to +85°C
• 3V to 6V Operating VDD
• Battery Powered or Battery Backup
• TTL Compatible (with pullups)
• 7.61-'s Cycle Time @4.2MHz (VDD 5V± 10%)
FUNCTIONAL BLOCK DIAGRAM
PROGRAM ROM
(2048 x 8)
DATA RAM
{16)(8 )(4)
----05V
---oGND
:1-.
\... PGJ '--PF J
PF also
open drain
'-PE....I
"'-po-"
xl098
'-PK-I
'--PA----' '--PBJ
76543210
RESET
SYNC MODE
~ADRL-../
&
Instruction
47
e MSM5840e---------------------------------------------------PIN CONFIGURATION (Top View)
44 Pin Plastic Flat Package
42 PIN PLASTIC DIP (RS)
"z~
A,
0
if
" i " ~ "z
~
~
m
~
m
~
~
~
A,
A,
A,
"
SYNC
0
"
H;
PH;"
PH,
H;;
CiN
MODe
CIN
OSC,
OSCI
PG,
G,
iVA
PG,
PG,
G,
RO
PGo
K,
PK,
K,
F,
K,
F,
PK·
PF,
PF,
F,
PK,
PF,
e,
PK,
PFo
K,
0,
D,
0,
0,
GNO
r3
L!.I
~
0
~
~ ~
~ z I"'
"
"
~ ~
w
~
w
~
PIN DESCRIPTION
Designation
Pin No.
GND
21
VDD
42
Main power source (+5V)
OSCo
10
Crystal OSC input, external clock input
OSC,
48
9
Function
Circuit GND potential
Crystal OSC input, external clock output (not TTL compatible)
PA,PB
1 t04
38 t041
Pseudo-bidirectional ports for 4-bit parallel I/O. Used as a pairfor8-bit I/O. Used
to output 8 LSBs of address in external ROM mode. Used to read external
instruction during IF.
PD,PE,
PE,PG
17t020
23t034
Output ports for 4-bit parallel output and bit set/reset. Specified by internal
port pointer, Bit position specified by set/reset instruction. PD also used for
instruction address MSBs in external ROM mode during IF.
PK
13to 16
4-bit parallel or bit test input port (unlatched)
PH
36 and 37
RESET
7
RESET has priority over every other signal. (see MSM5840 user's manual for
initialization sequence)
MODE
8
Used to enable external ROM mode during RESET and also to enable STbp mode
during execution (for stepping program)
INT
6
Negative edge sensitive external interrupt signal associated with EI and DI
instructions. Vectors to location 200H.
CIN
35
Negative edge sensitive external input for counter associated with ECT and DCT
instructions. Vectors to location 1 DOH. (same as timer)
SYNC
5
General purpose synchronizing signal output at the beginning of each machine
cycle. Used for address strobe during external ROM mode.
Read strobe pulseoccuring when port A or B is read (1 A, 1 B, 1 AB)
2-bit input port with latched memory (negative level sensitive)
RD
12
WR
11
Write strobe pulse occurring when port A or B is written (OA, OB, OAB, OBS, OTD)
IF
22
Read strobe pulse occurring during an instruction fetch from external ROM.
_ - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5840 •
FUNCTIONAL DESCRIPTION
Program ROM
The MSM5840 will address up to 4K bytes of
program ROM and can have 2K bytes of internal
masked ROM, or all ROM may be located externally. External EPROM may be used for program
development with conversion to internal ROM occurring after program debug and system checkout and verification. All instructions are byte
wide. Only three of the 98 instructions require
two bytes of program code. The instructions are
routed to a programmed logic array which generates the necessary internal control signals.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 128 nibbles, 8 nibbles of
which are dedicated registers accessible directly
under program control. These are the general
purpose registers, W, X, Y and Z, and the 4 save
(exchange) registers, CH, A, L, and AX. All other
DATA RAM must be addressed indirectly
through the DP (data po:nter) registers, a seven
bit pOinter (directly accessible by numerous instructions) consisting of 4 bit DPL register and a
3 bit DPH register. Any nibble of internal data
RAM can be accessed through the DP registers.
Some instructions automatically change the contents of the DP registers allowing efficient array
processing.
Input/Output Ports
PA, PB - These two ports are pseudobidirectional ports which can be used as simple
1/0 lines or used as either a 4-bit or 8-bit parallel
bus. An instruction fetches the external ROM
data through these ports by outputting the 8 low
order bits of address during SYNC followed by
an IF (instruction fetch) cycle. In addition,
synchronized data transfers are possible
thro~ these ports with the 1/0 pin signals RU
and WR associated with certain input/output instructions dedicated to these ports. In short, PA
and PB can be used as a multiplexed addressl
instruction/data bus.
PO, PE, PF, PG - These four output ports are
addressed indirectly through the TWO BIT port
pointer whose contents are changed through
certain instructions. These ports are bit
(set/reset) addressable. PO is also used for the
high order bits of address during an external instruction fetch. PF and PG are open drain outputs and PG is set high by a hardware RESET.
PK is an input port without memory, addressable either as a nibble or bit level input.
PH is a two-bit input port with memory, which
can be tested and reset under program control.
External Interrupt
The TNT pin can be tested under program
control or enabled to cause a vectored interrupt
to location 200H. It is negative edge sensitive.
Timerl Counter
The timer/counter is an 8-bit counter whose
input is selected under program control to be
either an external signal (CIN) or an internal
square wave of 1/1 28 the frequency of the OSCe
input (2 MHz/128 = 15.625 kHz). The
timer/counter can be enabled or disabled under
program control as can be associated internal interrupt which vectors to location 100H and has
higher priority than the external interrupt.
Stack
The stack is an LIFO queue for storing returnfrom-interrupt and return-from-subroutine address information. It is eleven bits wide and 4
levels deep.
Program Counter (PC)
The program counter is 11 bits wide and
loaded under program control.
Accumulator
The accumulator register is the data path
focal point of the CPU. Approximately one-half of
the instructions involve the accumulator. Its contents are the source and destination for many
ALU operations and port operations. CASE statements (computed GOTOs) are possible by using
the Jump with Accumulator (JA) instruction.
Flags
The MSM5840 is endowed with the following
set of flags.
Z - zero flag
Indicates that the result
of the previous operation
was zero
F- all ones
Indicates a carry from the
DPL register
0- all zeros
Indicates a borrow from
the DPL register
C - carry
Indicates a carry from the
previous operation
T - timer
Indicates that the timerl
counter is specified as a
timer
CT - counter
Indicates that the timerl
counter is specified as a
counter
TM - timer flag
Indicates an overflow of
the timer/counter register
INT - interrupt
Latching memory flag for
the external interrupt
INTE - interrupt
I ndicates that interrupts
enable
have been enabled
He - He memory
Indicates that an input
has been detected on the
He input
same as He except H 1
input
X
indicates internal ROM
1 indicates external
ROM. If all external ROM
indicates first bank of
2K.
o
o
49
eMSM5840e-------------------------------------------------INSTRUCTION SET
Mnemonic
a
Q)
Instruction Code
Descri ption
7
6
5
4
3
2
1
Byte
Cycle
0
ClA
Clear Accumulator
0
0
0
1
0
0
0
0
1
1
Cll
ClearDPl
0
0
1
0
0
0
0
0
1
1
ClH
ClearDPH
0
1
1
0
0
0
0
0
1
1
lAI
load Accumulator with Immediate
0
0
0
1
13
I,
11
10
1
1
lLi
load DPl with Immediate
0
0
1
0
i3
I,
1,
10
1
1
lHI
load DPH with Immediate
0
1
1
0
0
I,
11
10
1
1
l
load Accumulatorwith Memory
1
0
0
1
0
1
0
0
1
1
lM
load Accumulator with Memory then Modify DPH
1
0
0
1
0
1
11
10
1
1
lAl
load Accumulatorwith DPl
0
1
0
1
0
1
0
1
1
1
llA
load DPl with Accumulator
0
1
0
1
0
1
0
0
1
1
lAW
load Accumulator with W Register
1
0
0
0
0
1
0
0
1
1
-0
LAX
til
load Accumulatorwith X Register
1
0
0
0
0
1
0
1
1
1
1
t3
Q)
lAY
load Accumulator with Y Register
~
.9 lAZ
1
0
0
0
0
1
1
0
1
load Accumulator with Z Register
1
0
0
0
0
1
1
1
1
1
-0 SI
Store Accumulator to Memory then Increment DPl
1
0
0
1
0
0
0
0
.1
1
SMI
Store Accumulator to Memory then Modify DPH
and Increment DPl
1
0
0
1
0
0
11
10
1
1
1
II:
en
til
0
..J
lWA
load W Register with Accumulator
1
0
0
0
0
0
0
0
1
lXA
load X Register with Accumulator
1
0
0
0
0
0
0
1
1
1
lYA
load Y Register with Accumulator
1
0
0
0
0
0
1
0
1
1
lZA
load Z Register with Accumulator
1
0
0
0
0
0
1
1
1
1
lPA
load Port Pointer with Accumulator
0
1
0
1
1
0
0
0
1
1
lTI
load Timer with Immediate
0
1
16
1
Is
0
2
2
14
1 0 0
13 I, i1
0
17
1
10
RTH
Read TimerH
0
1
1
0
1
0
1
0
1
RTl
Readtimerl
0
1
1
0
1
0
1
1
1
1
XA
Exchange Accumulator with Save Register A
0
1
0
0
1
0
0
1
1
1
1
Xl
Exchange DPl with Save Register l
0
1
0
0
1
0
1
0
1
C>
XCH
Exchange DPH and Carry with Save Register CH
0
1
0
0
1
0
0
0
1
1
til
J::
X
Exchange Accumulatorwith Memory
1
0
0
1
1
0
0
0
1
1
XM
Exchange Accumulatorwith Memory then Modify
DPH
1
0
0
1
1
0
11
10
1
1
XAX
Exchange Accumulator with Save Register AX
0
1
0
0
1
0
1
1
1
1
INA
Increment Accumulator
0
0
0
0
0
0
0
1
1
1
1
Q)
c:
0
x
UJ
i:Q)
INl
Increment DPl
0
1
0
1
0
1
1
1
1
0
INM
Increment Memory
0
1
0
1
1
1
0
1
1
1
Cl
INW
Increment W Register
1
0
0
0
1
0
0
0
1
1
E
~
Q)
~
c:
Q)
E
~
0
.!:
50
Skip if Zero
INX
Increment X Register
1
0
0
0
1
0
0
1
1
1
INY
Increment Y Register
1
0
0
0
1
0
1
0
1
1
INZ
Increment Z Register
1
0
0
0
1
0
1
1
1
1
----------------------------------------------------. MSM5840 •
INSTRUCTION SET (CONT.)
Mnemonic
DCA
Description
Decrement Accumulator - Skip if Not All Ones
'\
Instruction Code
7
6
5
4
0
0
0
0
1
0
0
1
1
Byte
Cycle
1
1
1
0
1
1
3
2
1
0
1
1
1
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
"E
DCl
Ql
Decrement DPl
E
DCM
Decrement Memory
e"E
DCW
Decrement W Register
DCX
Decrement X Register
1
0
0
0
1
1
0
1
1
1
E
DCY
Decrement Y Register
1
0
0
0
1
1
1
0
1
1
0
DCZ
Decrement Z Register
1
0
0
0
1
1
1
1
1
1
DCH
Decrement DPH - Skip if All Ones and C = Zero
0
1
0
1
1
1
1
1
1
1
CAO
Complement Accumulator of One
0
1
0
1
0
0
0
0
1
1
AND
And Accumulatorwith Memory
0
1
0
0
0
1
0
0
1
1
OR
Or Accumulator with Memory
0
1
0
0
0
1
0
1
1
1
EOR
Exclusive or Accumulator with Memory
0
1
0
0
0
1
1
0
1
1
~
0
Ql
Skip if All Ones
Ql
~
.!:
OJ
0
"",
0
....J
RAl
Rotate Accumulator left through Carry
0
1
0
0
0
1
1
1
1
1
AC
Add MemorytoAccumulatorwith Carry
0
1
0
0
1
1
0
0
1
1
ACS
Add Memory to Accumulator with Carry, Skip
if Carry
0
1
0
0
1
1
0
1
1
1
AS
Add Memory to Accumulator, Skip if Carry
0
1
0
0
1
1
1
0
1
1
AIS
Add Immediate to Accumulator, Skip if Carry
0
0
0
0
Is
12
11
10
1
1
Decimal adjust Accumulator in Subtraction
0
1
0
1
1
0
1
0
1
1
CM
Compare Accumulatorwith Memory, Skip if Equal
0
1
0
1
1
1
1
0
1
1
AWS
Add W RegistertoAccumulator, Skip if Carry
1
0
0
1
1
1
0
0
1
1
AXS
Add X Register to Accu mulator, Skip if Carry
1
0
0
1
1
1
0
1
1
1
AYS
And Y Registerto Accumulator, Skip if Carry
1
0
0
1
1
1
1
0
1
1
AZS
Add Z Register to Accumulator, Skip if Carry
1
0
0
1
1
1
1
1
1
1
SPB
Set Port Bit
1
0
1
1
0
0
I,
10
1
1
RPB
Reset Port Bit
1
0
1
1
0
1
I,
10
1
1
5MB
Set Memory Bit
1
0
1
1
1
0
I,
10
1
1
RMB
Reset Memory Bit
1
0
1
1
1
1
I,
10
1
1
U;
TAB
Test Accumulator Bit"'
1
0
1
0
0
0
I,
10
1
1
Qi
TMB
Test Memory Bit
1
0
1
0
0
1
11
10
1
1
m TKB
e:Qi
Test K Port Bit
1
0
1
0
1
0
11
10
1
1
THB
Test H Port Bit
1
0
1
0
1
1
0
10
1
1
iii
TI
Test Interrupt flag
1
0
1
0
1
1
1
1
1
1
TTM
Test Time flag
1
0
1
0
1
1
1
0
1
1
TC
Test Carry flag
0
1
0
0
0
0
1
0
1
1
SC
Set Carry flag
0
1
0
0
0
0
0
0
1
1
RC
Reset Carry flag
0
1
0
0
0
0
0
1
1
1
0
~
E DAS
=:;
~
~
.....
-
(J)
SkipifOne
51
eMSM5840e'---------------------------------------------------INSTRUCTION SET (CO NT.)
Mnemonic
CD
J
Description
Jump
t:
:.=
:>
e
.0
:>
C/)
"0
t:
.s::
6
5
0
17
0
16
4
3
1
0
1
1
I,
I.
0 110 I.
13 12 11
10
2
a
Byte
Cycle
2
2
JC
Jump in Current Page
1
1
I,
I.
13 12
11
10
1
1
JA
Jump with Accumulator
0
1
0
0
0
1
1
1
1
CAL
Call Subroutine
0
0
16
1
1
2
2
I,
I.
1 1,0 I.
12 11
a
Ir
10
II!
In
Instruction Code
7
0
Ig
RT
Return from Subroutine
0
1
0
1
1
0
0
1
1
2
OBS
Output Byte String
0
1
1
1
0
0
0
0
1
2-17
OTD
Output Table Data
0
1
1
1
0
0
0
1
1
2
OA
Output Accumulator to Port A
0
1
1
1
0
0
1
0
1
1
OB
Output Accumulator to Port B
0
1
1
1
0
0
1
1
1
1
:;
:;:,
OP
Output Accumulator to Port P designated Port
Pointer
0
1
1
1
0
1
0
0
1
1
:>
Co
OAB
Output Memory and Accumulatorto Ports A and B
0
1
1
1
0
1
0
1
1
1
.E
OPM
Output Memory to Port P designated Port Pointer
0
1
1
1
0
1
1
0
1
1
IA
Input Port A in Accumulator
0
1
1
1
1
0
1
0
1
1
IB
Input Port B in Accumulator
0
1
1
1
1
0
1
1
1
1
IK
Input Port K in Accumulator
0
1
1
1
1
1
0
0
1
1
lAB
Input Ports A and B in Memory and Accumulator
0
1
1
1
1
1
0
1
1
1
EI
Enable Interrupt
0
1
0
1
0
0
1
1
1
1
DI
Disable Interrupt
0
1
0
1
0
0
1
0
1
1
ET
Enable Timer
0
1
1
0
1
1
1
1
1
1
DT
Disable Timer
0
1
1
0
1
1
1
0
1
1
ECT
Enable Counter
0
1
1
1
1
1
1
1
1
1
DCT
Disable Counter
0
1
1
1
1
1
1
0
1
1
HLT
Halt
0
1
1
0
1
1
0
1
1
1
EXP
Exchange Program
0
1
1
0
1
0
0
1
1
1
NOP
No Operation
0
0
0
0
0
0
0
1
1
:;
Co
0
ec:
0
()
52
0
----------------------------------------------------e MSM5840e
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
VOO
Ta=25°C
-0.3t07
V
Input Voltage
VI
Ta=25°C
-0.3toVOO
V
Operating Voltage PF PG
Vo
Ta=25°C
-0.3 to 25
V
Storage Temperature
Tsta
-55to+150
°C
Supply Voltage
Unit
Limits
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage tothe
device. This is a stress rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
VOO
Operating Temperature
FanOut
Conditions
Limits
Unit
@1 MHz
3t06
V
@4.2MHz
4.5 t05.5
V
-40to+85
°C
Top
N
MOSLoad
15
TTL Load
1
D.C. CHARACTERISTICS
(VDD = 5V±1 0%, Ta = -20° to +70°C)
Parameter
Typ.
Symbol
Conditions
Min.
High Input Voltage
VIH
-
3.6
Low Input Voltage
VIL
-
High Output Voltage (1)
VOH
IO=-40/LA
Low Output Voltage
VOL
IO=1.6mA
0.4
V
VI=VOO/OV
25
f----25
/J- A
VI =VOO/OV
1
f----50
/LA
VI =VOO/OV
1
f----1
/LA
-1
mA
OSCo Input Leak Current
RESET, MOOE Leak Current
IIH
IlL
Input Leak Current(2)
IIH
IlL
Unit
0.8
V
V
4.2
V
IIH
IlL
Max.
PA, PB High Output Current
IOH
VOH =O.4V
High Output Current(1)
IOH
VOH =2.5V
-0.25
mA
Low Output Current
IOL
VOL =0.4V
1.6
mA
BVOH
IO= 1O/L A
20
Input Capacitance
CI
f=1MHz
Ta=25°C
5
pF
Output Capacitance
Co
f=1MHz
Ta=25°C
7
pF
100
VI =VOO/OV
10
200
/J- A
100
VI =VOO/OV
f=4.2MHz
1.6
4
mA
PF, PG Output Breakdown Voltage
Current Consumption(3)
V
Notes: (1) Except PA, PB (see graphs)
(2) Except OSCo,~, MODE
(3) Typical Value of VOO is 5V
53
• MSM5840··---------------------------------------------------A.C. CHARACTERISTICS (INTERNAL ROM MODE)
(VDD = 5V±1 0%, Ta = -40° to +85°C)
Parameter
CycleTime
Sync Pulse Width
Symbol
tCY
!,S
0.95
!,S
1.9
!,S
tRW
tRO
WR Pulse Width
tww
SyncltoWRl
two
Port Input Setup Time
tOSR
Port Input Hold Time
tOHR
CL =50pF
CL =50pF
1/2 tCY +0.5
!,S
0.95
!,S
13/16 tCY +0.5
!,S
4/16tCY
!,S
0.8
!,S
0.8
!,S
13/16 tCY +0.5
!,S
0
WR 1to New Oata Valid
toow
PA,PB
CL=50pF
Sync 1to New Data Valid
toos
PO, PE, PF, PG
CL =50pF
PHD, PH, Input Pulse Width
tHW
(1)
tcw
(1)
tlNTW
500
nS
250
nS
500
nS
Note: (1) The processorlogicwill ignore the following events:
1.An INTfallingedgeoccurringduringTINHofa TI instruction.
2. A PHDorPH,low level occurringonlyduringTINH oIa THB instruction.
TIMING CHARTS
tCY
I--,swj
SYNC
---'
r-
~
'RD
'RW-
{
'WD
..
'ww
~
~
PA,PB
--!'DDW
} NEW OUTPUT
DATA
INPUT DATA
(1)
I---'DSR-
PK
DON'TCARE
r--tDHR
INPUT DATA
DON'T CARE
.1
tDDS
.1
PD,PE
NEW DATA
OLD DATA
PF,PG
'I
.rtHW-j
PHD. PH,
,
·CW
I'-------'
i-tINTW-
I,r"---\
1/2.CY
1
I
tlNH
(7/16·CY)
Note: (1) All 'ONES' must be output before reading port A or B.
54
Unit
tsw
RO Pulse Width
INT Input Pulse Width
Max.
7.6
Sync 1toRrJ 1
CIN Input Pulse Width
Typ.
Min.
Conditions
1
1/16tCY
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5840 •
A.C. CHARACTERISTICS (EXTERNAL ROM MODE)
(VDD
=
5V±1 0%, Ta
=
-40° to +85°C)
Parameter
Symbol
Conditions
Min.
Typ.
Unit
Max.
Cycle Time
tCY
7.6
,.,.S
Sync Pulse Width
tsw
0.95
,.,.S
IF Pulse Width
tlW
1.425
,.,.S
Sync I tolF j
tiD
CL =50pF
Address Low Delay
tLAD
CL =50pF
Address Low Hold
tLAH
1/16 tCY
Instruction Setup
tiS
1/16tCY
Instruction Hold
tlH
Data Recovery
tDR
CL =50pF
Address High Delay
tHAD
CL =50pF
Address High Hold
tHAH
3/16 tCY + 1
,.,.S
0.8
,.,.S
,.,.S
1/16tCY+l
,.,.S
20
0
0
nS
0.8
,.,.S
0.5
,.,.S
0.5
,.,.S
CY
tsw
SYNC
r--
--'
tID
- ,.1
tlW_
I
tLAD
PA,PB
DATA
tlS_
ADDRESS
LOW
INSTR
tHAD
PO
DATA
Cycle Dependent Timings
-
ff
ADDRESS HIGH
4MHz
DATA
tOR
I
I
'1
I
I
DATA
tHAH
2MHz
lMHz
1/16tCY
0.5,.,.S
I,.,.S
2,.,.S
1/16tCY+l
1.5,.,.S
2,.,.S
3,.,.S
5,.,.S
3/16tCY+l
2.5,.,.S
4,.,.S
7,.,.S
13,.,.S
4/16tCY-l
I,.,.S
3,.,.S
7,.,.S
15,.,.S
1/2tCY+l
5,.,.S
9,.,.S
17,.,.S
33,.,.S
500kHz
4,.,.S
7/16tCY
3.5,.,.S
7,.,.S
14,.,.S
28,.,.S
13/16tCY+l
7.5,.,.S
14,.,.S
27,.,.S
53,.,.S
55
e MSM5840e---------------------------------------------------TYPICAL PERFORMANCE CURVES
Supply Current vs Supply Voltage
Supply Current vs Oscillator Frequency
(Ta = 25°C, No Load)
(Ta = 25°C, No Load)
10m ..-,----r--r---,------,
10m , . - - - - . . - - - - r - - - - - - ,
VOO=6V
I
5V
1 m r-+---+""7'~t-::;#
1m 1----I----1-7'SoS--
~
c
c
100"
100"
1----t7"?C:;~'--t---__t
~
c
E
10" L...-.....,'--_L-_ _ _L...-_ _~
10M
1M
lOOK
10K
10"
f
0.1"
(OSC) (Hz)
L...-...1-_--'-_ _.L.-_-'-_ _----'
o
3
5
7
10
VOO(V)
Oscillator Frequency vs Supply Voltage
(Ta
Oscillator Frequency vs Temperature
= 25°C, CL = 50pF)
(CL = 5OpF)
10
10
v
8
N
J:
~
6
4
...........
J:
~
/
U
en
g
.....
8
N
6
r-...........
U
en
g
.....
-
4
I
2
o
o
2
3
5
VOo(V)
56
7
10
-50
o
50
Ta (OC)
100
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5840 •
High Current Out YS Voltage
Low Current Out YS Voltage
(Ta = 2SoC, Except PA, PB)
-10~,-----~--~-----r------~
-al--+-----+----f-----+-------j
IS
<
!
..J
a:
$
(J)
-g
.9
60
CLA
CCL
CLH
LAI
LLI
LHI
L
LAL
LLA
LAW
SI
LWA
LPA
LTI
Description
Clear Accumulator
ClearDPL
ClearDPH
Load Accumulatorwith Immediate
Load DPL with Immediate
Load DPH with Immediate
Load Accumulatorwith Memory
Load Accumulatorwith DPL
Load DPL with Accumulator
Load Accum ulator with W Register
Store Accumulator to Memory then Increment DPL
Load W Register with Accumulator
Load Port Poi nter with Accumulator
Load Timer with All Zeros
Instruction Code
7
6
5
4
3
0 0 0 1 0
0 0 1 0 0
0 1 1 0 0
0 0 0 1 I.
0 0 1 0 I.
0 1 1 0 0
1 0 0 1 0
0 1 0 1 0
0 1 0 1 0
1 0 0 0 0
1 0 0 1 0
1 0 0 0 0
0 1 0 1 1
0 1 1 0 1
2
1
0 0
0 0
0 0
12
0
0
0
0
10
I. I, 10
0 0 10
1 0 0
1 0 1
1 0 0
1 0 0
0 0 0
0 0 0
0 0 0
0 0 0
"
Byte Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5842 •
INSTRUCTION SET (CONT.)
Mnemonic
Descri ption
Instruction Code
7
6
5
4
3
2
1
0
Byte
Cycle
Q)
Cl
<=
'"
u
.r:;
c:
Q)
E
~
u
Q)
0
::::<=
Q)
E
~
u
<=
'"
u
'0>
0
...J
u
~
E
;;
~
iii
~
Q)
e:"'
Q)
Q)
(f)
iii
Q)
.!:
Exchange Accumulator with Memory
1
0
0
1
1
0
0
0
1
1
INA
INl
INM
INW
DCA
DCl
DCM
I"O~M"""m"''''''
0
0
0
0
0
0
0
Increment DPl
Skip if Zero
Increment Memory
Increment W Register
Decrement Accumulator - Skip if Not All Ones
Decrement DPl
} Skip if All Ones
Decrement Memory
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CAO
RAl
Complement Accumulator of One
Rotate Accumulator leftthrough Carry
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
AC
AS
AIS
DAS
CM
Add Memory to Accumulatorwith Carry
Add Memory to Accumulator, Skip if Carry
Add Immediate to Accumulatgr, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare AccumCilatorwith Memory, Skip if Equal
0
1
1
10
1
1
12
0
1
0
1
0
1
1
1
1
1
1
5MB
RMB
TAB
TMB
THB
TTM
TC
1
1
1
1
1
1
0
0
0
0
1
SC
RC
Set Memory Bit
Reset Memory Bit
Test Accumulator Bit
Test Memory Bit
Test H Port Bit
TestTimerfiag
Test Carry flag
Set Carry fl ag
Reset Carry flag
J
Jump
0
"5
e
.0
::J
(f)
.....
.r:;
U
I
X
)(
W
"5
S::J
~
"5
a.
-=
e
c:0
0
0
0
0
0
0
0
17
1
JC
JA
CAL
Jump in Current F',age
Jump with Accumulator
Call Subroutine
RT
Return from Subroutine
0
OTD
OA
OB
OP
Output Table Data
Output Accumulatorto Port A
Output Accumulatorto Port B
Output Accumulatorto Port P designated Port
Pointer
Output Memory to Port P deSignated Port Pointer
0
Input Port A in Accumulator
Input Port B in Accumulator
Input Port K in Accumulator
0
No Operation
0
0
17
<=
~
al
0
OPM
IA
IB
IK
NOP
1
1
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
Is
Is
1
I.
I.
0
0
0
0
0
1
1
1
0
I.
1
1 0
0 1
I. Is
1 0
0
1
I.
1
1
11
10
1
0
1
1
1
0
1
1
11
11
11
11
10
10
10
10
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
1
1
2
10
1
1
2
1
0
1
0
1
1
1
1
2
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
0
0
0
1
0
0
0
1
1
0
0
19
11
11
0 0 1
1 0 19
10 12 11
0
I.
12
12
10
10
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
10
10
1
1
1
1
0
0
0
1
1
1
1
0
0
1
•
0
1
U
61
-MSM5842 -~-------------------------------------------------ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Symbol
Conditions
VOO
Ta=25°C
-o.3t07
VI
Ta=25°C
-0.3toVOO
V
-55to+150
°C
Tstg
Limits
Unit
V
Note: Streases above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This Is a stress rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature
Symbol
VOO
Conditions
Limits
Unit
1MHz
3t06
V
4.2MHz
4.5t05.5
V
-40 to 85
°C
Top
Fan Out
MOSLoad
40
TTL Load
1
D.C. CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40° to +85°C)
Symbol
Conditions
Min.
High Input Voltage
Parameter
VIH
-
3.6
Low Input Voltage
VIL
-
High Output Voltage (1)
VOH
IO=-40/LA
Low Output Voltage
VOL
IO=1.6mA
OSCo Input Leak Current
IIH
IlL
RESET Leak Current
IIH
IlL
Input Leak Current(2)
IIH
IlL
Typ.
Max.
Unit
V
0.8
4.2
V
V
0.45
VI=VOO/OV
-
VI=VOO/OV
-
VI=VOO/OV
-
V
25
-25
/LA
1
-20
/LA
1
-1
/LA
PA, PB High Output Current
IOH
VOH=0.4V
High Output Curreni(1)
IOH
VOH=2.5V
-0.25
Low Output Current
IOL
VOL=0.45V
1.6
Input Capacitance
CI
f=1MHz
Ta=25°C
5
pF
Output Capacitance
Co
f=1MHz
Ta=25°C
7
pF
100
VI=VOO/OV
20
200
/LA
100
VI=VOO/OV
f=4.2MHz
1.5
4
mA
Current Consumption(3)
Notes: (1) Except PA, PB (see graphs)
(2) Except OSCo, RESET
(3) Typical Value of VOO is 5V
62
-1
mA
mA
mA
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5842 •
A.C. CHARACTERISTICS
(VDD = 5V± 10%, Ta = -40° to +85°C)
Symbol
Conditions
Min.
Cycle Time
Parameter
tCY
OSC=e4MHz
7.6
IL S
Sync Pulse Width
tsw
0.95
IL S
Port Input Invalid Time
tDiV
Port Input Valid Time
tov
Sync 1to New Data Valid
Typ.
Max.
Unit
1/2 tCY +0.5
IL S
13/16 tCY + 0.5
IL S
2
toos
PD. PE CL = 50pF
PHo Input Pulse Width
tHW
(1)
CIN Input Pulse Width
tcw
IL S
250
nS
250
nS
Notes: (1) The processor logic may ignore the following event:
A PHo low level occurring only during TINH of a THB instruction.
(2) All 'ONES' must be output before reading port A or B.
TIMING CHARTS
tCY
r--tSW...:j
SYNC
r-
}
--'
PA,PB
INPUT DATA
NEW OUTPUT 0 ATA
Note 2
tOlV
PK
tovINPUT DATA
DON'T CARE
DON'T CARE
tDOS
OLD DATA
PO,PE
NEW DATA
t t HW -
PH O
ttcwi I
CIN
1/2 tCY
I-I'
'1
tlNH
7/16 t Cy
I
I
1/16 tc y
63
• MSM5842 ••- - - - - - - - - - - - - - - - - - - - - - - - - -
TYPICAL PERFORMANCE CURVES
Supply Current vs Supply Voltage
Supply Current vs Oscillator Frequency
(Ta = 25°C, CL = 1 5pF)
(Ta = 25°C, No Load)
10m
10m
I
J(OSC) = 8MHz
4MHz
VOO = 5 ' l
1m ~~~~~~~2MHz
1 MHz
100KHz
100",
3
1m
3
100",
c
c
.9
.9
10",
V
./
~
10",
OHz
0.1", ~.I...........I~-+-~----,J
o 1 3 5
7
10
10K 100K
VOo(V)
Oscillator Frequency vs Supply Voltage
Oscillator Frequency vs Temperature
(Ta = 25°C, CL = 50pF)
"N
10
0en
0
,...
--,
8
6
/
f'..
J:
~
0
1/
en
0
'=:
8
6
4
2
2
I
3
........ ~=5V
"N 10
4
0
o
5
VOo(V)
. 64
12
1/
J:
~
14
I
12
10M
1M
J(OSC)(Hz)
7
10
-50
o
Ta(OC)
50
100
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5842 •
Low Current Out vs Voltage
High Current Out vs Voltage
(Ta=25°C)
(Ta = 25°C)
-4
20
15
~
E
10
5
o
V
I--
1
3
I
.9
VDD=5V
t-.... i'..
-2
15y(PA'~
o
5
7
10
o
1
3
5
Fall Time vs Load
Rise Time vs Load
(Ta = 25°C, PA, PB, PD, PE, SYNC)
(Ta = 25°C, PD, PE, SYNC)
1000
1000
800
<:
I...J
10
7
Vo(V)
Vo(V)
.,
PD,PE
SYNC
VDD=5V
VDD~
-1
il
a
-3
.,
800
-::.J:
600
/
<:
600
.t"
)
400
200
o
10 20
-
I--v
Vi
D=5V
50 100200 5001000
CL(pF)
=5V
V
.t"
400
VDD
200
o
-
10 20
V
V
50 1 00 200 500 1000
CL(pF)
65
OKI
semiconductor
MSM58421
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM58421 is a low-power, high-performance 4-bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within this one chip is a 5 digit 7 -segment LCD driver and PLA which can change the
character font for the 7 segments freely under the control of the mask programmable data.
Also integrated in this chip are mask ROM of 1536 x 8 bits for programming, data RAM of 40 x 4
bits, 13 general-purpose input/output ports, 1 2-bit timer, and clock oscillator to facilitate easy application to equipment with an LCD display.
FEATURES
•
•
•
•
•
•
•
•
Low Power Consumption CMOS 4-bit
One-Chip Microcomputer
100% Static Logic
1536 x 8 bits Mask ROM
40 x 4 bits Data RAM
1 Static Register
Built-in 12-bit Timer (with 32 Hz Common
Output)
All Input Ports Contain Schmitt Trigger
Circuits
8-bit Interface Bus
• 52 Instructions
• 94% of the 52 Instructions are 1 Byte and 1
Machine Cycle
• Integrated with 13 Input/Output Ports and 40
Static LCD Driver Circuit
• +5V Single Power Supply, 60-Pin Mold Flat
Package
• 7 -Segment Character User Programmable
Font (32 Words x 7 Segments)
• Various Functions Changeable under Mask
Program Control
FUNCTIONAL BLOCK DIAGRAM
C
'-PLCDSJ '-PLCD5...J'-PLCD4...JLPLCD3...J '-PLCD2..J\.....PLCD1.J
~
a
3
2 1
' - - PK
0
PH
.........J
M
N
• Crystal Oscillator 4.194304 MHz, SYNC
66
~
7 .63 "sec LCD common signal 32 Hz
3 2 1
0
'--PA-J
3 2 las
~PB~
0 OVoo G
y
N
S S
N
CC
0
C
1 0
- - - - - - - - - - - - - - - - - - - - - - - - - ' . MSM58421 •
LOGIC SYMBOL
PIN CONFIGURATION
J
PORT A
;!;;!;
J
PORT B
RESET
RESET
PLC03 -e
PLCD3-d
) PLeD 1
PLCD3-c
PLCD6-S
J
PLC02-e
PLCD 2
] PLeD 3
PORT K [ -
Ko
K,
K,
J
K;
PLeD 4
PLeD 1-f
Pl.C01-c
J PLeD 5
PLC01-g
PlCDG-1
JPLeD 6
GNO
COMMON
voo
SYNC
-~
COMMON
~
SYNC SIGNAL OUTPUT
COMMON SIGNAL OUTPUT
co
~
I-
0::
a:: a:
I-II:
Q..
Q.
0..
0..
III
lJl
I-
I-
00 0
0
!Ii
III:
0
Q.
PIN DESCRIPTION
Function
Designation
Pin No.
GND
33
Circuit GND potential
VDD
23
Main power source (+5V)
OSCo
17
Crystal OSC input, external clock input
OSC,
16
PA,PB
19 to 22
24t027
Pseudo-bidirectional ports for 4-bits parallel I/O. To input data from these ports, it is
necessary to write "1 "tothem beforehand. When nothing is applied totheir
terminals, the content of output ports is written in them, so they can also be used as
registers. In addition, it is possible to use them for make 8-bit parallel output
depending on instructions.
PK
28 t031
Input ports for 4-bit parallel input with no latching function.
PH
14
Input port with latching function to be set by negative logical signal.
That is, this terminal is set at the time when the negative logical signal is applied to it
from the outside.
It is reset automatically after execution of the test instruction of this port.
RESET
18
The RESET signal which input has priority over all of other signals and performs the
following functions:
(1) Resets all bits of the program counter;
(2) Resets the timer counter and timer flag;
(3) Resets the port poi nter;
(4) Resets the accumulator;
(5) Resets I/O ports PA and PB;
(6) Resets the input port PH flag;
(7) Initializes the output port PLCD for LCD;
(8) Resets the machine cycle to M 1.
Since the RESET terminal is pulled up to VDD by an internal resistor (approx. 800
kO), it is possible to make power ON/reset by connecting it with an external
capacitor.
Crystal OSC input, external clock output (not TTL compatible)
67
• MSM58421 ••- - - - - - - - - - - - - - - - - - - - - - - - -
PIN DESCRIPTION (CONT.)
Designation
PinNa.
SYNC
15
PLCD
1 -6
1 to 13
34 to 60
Function
General-purpose synchronizing signal output. The signal is output at the beginning
of each machine cycle. Output constantly, this signal is used also as clock pulse to
external units.
The cycle of SYNC becomes 32 times that of the original oscillation (8/-LS when the
clock pulse is 4 MHz).
PLCD 1 - 6 (Pins 1 - 13 and 34 - 60)
7-bit and 5-bit parallel output ports, respectively. They are used to direct drive an
LCD (static type). Specification of each port is done by the port pointer (PP) as
shown in the table below:
Content of PP
Port Specified
bs
b2
b,
bo
x
0
0
0
PLCD1
x
0
0
1
PLCD2
x
0
1
0
PLCD3
x
0
1
1
PLCD4
x
1
0
0
PLCD5
x
1
0
1
PLCD61 '--4
x
1
1
0
PLCD6 5 and BI
x
1
1
1
--
X: Don't care
BI: 7 Segment Decoder PLA Blank Input
The data of be, of the internal 4-bit bus is written to 5 of PLCD6, and that olbs to
BI.
32
COMMON
COMMON (Pin 32)
COMMON output terminal. This output signal is connected tothe common electrode
of static type LCD. The frequency of the COMMON signal output is given with the
following equation:
f(COM) =f(OSC)/217
Where the basic clock f(OSC) is 4.19304 MHz, f(COM) becomes 32 Hz (duty ratio:
50%).
MASK OPTION TABLE
Ilosc) ~4.194304MHz
PortKO
PortK2
PortK3
Commom
28pin
30pin
31 pin
32pin
a
Ko
K,
K3
32Hz
12bit
1
Ko
BUZZER
COMMON
32Hz
12bit
2
Ko
BUZZER
K3
32Hz
12bit
3
Ko
BUZZER
K3
64Hz
11 bit
4
Ko
K,
K3
64Hz
11 bit
5
"0
K,
K3
128Hz
10bit
6
Ko
BUZZER
K3
128Hz
10bit
7
Ko
K,
K3
256Hz
9bit
8
Ko
K,
K3
512Hz
8bit
9
Ko
BUZZER
K3
512Hz
Timer
No.
8bit
I IBUZZER) ~2048Hz
68
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM58421 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VDD
Ta=25°C
-0.3t07
V
Input Voltage
VI
Ta=25°C
--o.3toVDD
V
Power Dissipation
PD
Ta = 25°C per 1 package
200
mW
-55to+150
°C
Unit
Power Supply Voltage
Storage Temperature
Tsta
OPERATING RANGE
Symbol
Conditions
Limits
Power Supply Voltage
Parameter
VDD
I(OSC) =Ot04.2 MHz
4t06
V
Operating Temperature
TOp
-
-40 to +S5
°C
MOSLoad
15
TTL Load
1
Fan Out (excluding COM, SEC)
N
-
D.C. CHARACTERISTICS
(VDD
= 5V±1 0%, Ta = -40 to +85°C)
Parameter
Symbol
"H" Input Voltage
VIH
"L" Input Voltage
VIL
Conditions
Min.
Typ.
Max.
3.6
Unit
V
o.s
V
10=-SOI'A
VDD
-0.1
V
VOH
10=-2OI'A
VDD
-0.1
V
"H" Output Voltage(3)
VOH
10=-4OI'A
4.2
V
"H" Output Voltage(4)
VOH
10=-15I'A
4.2
"L" Output Voltage(1)
VOL
10=801'A
0.1
V
"L" Output Voltage(2)
VOL
10 =2OI'A
0.1
V
"L" Output Voltage(5)
VOL
10=1.6mA
0.4
V
"H" Output Voltage( 1)
VOH
"H" Output Voltage(2)
V
OSCo Input Leak Current
IIH/IIL
VI =VDDIVI =OV
101-10
I'A
Input Current(6)
IIH/IIL
VI =VDDIVI =OV
1/-20
I'A
PA
"H"
PB
Output Current
10H
VO=O.4V
"H" Output Current(3)
10H
VO=2.5V
-0.25
rnA
"L" Output Current(4)
10L
VO=O.4V
1.6
rnA
Input Capacity
Output Capacity
Current Consumption
-1
rnA
CI
1=1 MHz, Ta=25°C
5
pF
Co
1=1 MHz, Ta=25°C
7
pF
IDD
1= 4.194304 MHz,
at no load
2
5
rnA
Notes: (1) Applied to COMMON
(2) Applied to SEGMENT
(3) Applied to SYNC
(4) Applied to PA, PB
(5) Applied to SYNC, PA, and PB
(6) Appl ied to RESET, PK, and PH
69
eMSM58421
e------------------------------------------------___
SWITCHING CHARACTERISTIC
(VOD
= 5V±1 0%, Ta = -40° to +85°C)
Parameter
SYNC Delay Time from
Clock (OSCol
Clock (OSCol Pulse
Width
Symbol
!,J,d
Conditions
Min.
CL =50pF
!,J,WH
tWL
Typ.
Max.
Unit
800
ns
115
ns
Cycle Time
tCY
(1)
p's
SYNC Pulse Width
tsw
(2)
p's
PA
PB Data Valid Time
PK
tov
CL =50pF
(3)
p's
PA
PB Data Invalid Time
PK
tDiV
CL =50pF
Data Delay Time
toos
CL =50pF
Port H Set Pulse Width (7)
tHW
COMMON Delay Time
from SYNC
!sCd
CL =50pF
SEGMENT Delay Time
from COMMON
tCSd
CL =50pF
CLOCK (OSCo)
tl/Xl
SYNC
70
(4)
p's
500
ns
500
ns
2
p's
1
p's
--------------------------------------------------~. MSM58421 •
~--~------___ tCY~(l~)----------~
SYNC
(4)
(3)
I - - - - t o I V---+-tDV
(6)
PA,PB,PK
INPUTMOOE _________
IN VALID
~~-----------J
~
VALID
____
-J
~
-_-_-_~~O~Lt_:_:_:_:_:_
PA,PB
OUTPUT
MODE
_____..JX\.,I-I_-._-_-__
IN VALID
________________
-~~--I
-_-_-_-_-_-_-_-_
......_N_EW_D_A_T_A_
t1
PH
______ 0
THB INSTRUCTION CYCLE
SYNC
'~
16x1/f(OSC)
.1.
TINH
15x1/f(OSC)
.If'1x1/f(OSC)
Notes: (11 tev = 32 x 1/f(08e)
(2) t8W = 4 x 1/f(08e)
(3) tov = 8 x 1/f(08e)
(4) tOIV = 16 x 1/f(08e) + 0.5 p's
(5) t008 = 26 x 1/f(08e) + 1 p's
(6) When data is input from PA or PB, set the contents of PA or PB to "1" prior to reading instruction.
(7) At execution of the THB instruction, any input made during a period of TINH (15 x 1/f(08e)) shown in the
above figure may be neglected.
SYNC
tsed
COMMON
tcsd
SEGMENT _ _ _ _ _ _ _""""\
(WHEN THE DISPLAY ____________...1
CONTENT IS FIXED)
tcsd
r------""""\ _ - - - - -.....
~ _ _ _ _ _ _J
~-------------'
71
• MSM58421 .---------------------------------------------------
DESCRIPTION OF TERMINALS
GND (Pin 33)
Circuit grounding potential
VDD (Pin 23)
Main power supply
OSCo (Pin 17)
Input of internal oscillation circuit at one side
of crystal resonator and ceramic vibrator.
OSC 1 (Pin 16)
Output of internal oscillation circuit at the
other side of crystal resonator and ceramic vibrator (not TTL compatible)
PA, PB (Pins 19 - 22 and 24 - 27)
These are quasi-bidirectional ports for 4-bit
parallel 1/0. To input data from these ports, it is
necessary to write "1" to them beforehand.
When nothing is applied to their terminals, the
content of output ports is written in them, so they
can also be used as registers. In addition, it is
possible to use them to make an 8-bit parallel
output depending on instructions.
PK (Pins 28 - 31)
Input ports for 4-bit parallel input with no
latching function.
PH (Pin 14)
Input port with latching function to be set by
negative logical signal.
This terminal is set at the time when the negative logical signal is applied to it from the outside.
It is reset automatically after execution of the
test instruction of this port.
RESET (Pin 18)
Reset must be active for greater than 1 machine cycle.
The RESET signal, when input, has priority
over all of other signals and performs the following functions:
(1) Resets all bits of the program counter;
(2) Resets the timer counter and timer flag;
(3) Resets the port pointer;
(4) Resets the accumulator;
(5) Resets 1/0 ports PA and PB;
(6) Resets the input port PH flag;
(7) Initializes the output port PLCD for LCD; and
(8) Resets the machine cycle to M 1.
72
Since the RESET terminal is pulled up to VDD
by an internal resistor (approx. 800ka), it is
possible to activate power ONlreset by connecting it to an external capacitor.
SYNC (Pin 15)
This is a general-purpose synchronizing
signal output. The signal is output at the beginning of each machine cycle. Output constantly,
this signal is used also as clock pulse to external
units.
The cycle of SYNC becomes 32 times that of
the original oscillation (8/Ls when the clock pulse
is 4MHz).
PLCD 1 - 6 (Pins 1 - 13 and 34 - 60)
These are 7 -bit and 5-bit parallel output
ports, respectively. They are used to directly
drive an LCD (static type). Specification of each
port is done by the port pointer (PP) as shown in
the table below;
Content of PP
Port Specified
b3
b2
bl
bo
x
x
x
x
x
x
x
x
0
0
0
PLCDl
0
0
1
PLCD2
0
1
0
PLCD3
0
1
1
PLCD4
1
0
0
PLCD5
1
0
1
PLCD6-4
1
1
0
PLCD6 5 and BI
1
1
1
-
X: Don'tCare
BI: 7 Segment Decoder PLA Blank Input
The data of bo, of the internal4-bit bus is written to
5 of PLCD6, and that of b3 to 81.
COMMON (Pin 32)
This is a COMMON output terminal. This
output signal is connected to the common electrode of static type LCD. The frequency of the
COMMON signal output is given with the following equation:
f(COM)
= f(OSC)/217
Where the basic clock f(OSC) is 4.19304 MHz,
f(COM) becomes 32 Hz (duty ratio: 50%).
---------------------------------------------------. MSM58421 •
INSTRUCTIONS LIST
Mnemonic
CLA
CLL
CLH
LAI
LLI
LHI
L
LAL
LLA
LAW
SI
LWA
LPA
LTI
X
INA
INL
INM
INW
DCA
DCL
DCM
CAO
RAL
AC
AS
AIS
DAS
CM
5MB
RMB
TAB
TMB
THB
TTM
TC
SC
RC
J
JC
JA
CAL
Description
Clear Accumulator
ClearDPL
ClearDPH
Load Accumulator with Immediate
Load DPL with Immediate
Load DPH with Immediate
Load Accumulator with Memory
Load Accumulator with DPL
Load DPL with Accumulator
Load Accumulator with W Register
Store Accumulator to Memory then Increment DPL
Load W Register with Accumulator
Load Port Pointer with Accumulator
Load Timer with Immediate "0" (Clear Timer & TMF)
Exchange Accumulator with Memory
Increment Accumulator
Increment DPL
Increment Memory
IncrementW Register
Decrement Accumulator
Decrement DPL
Decrement Memory
Complement Accumulator of One
Rotate Accumulator Left through Carry
Add Memory to Accum ulator with Carry
Add Memory to Accumulator, Skip if Carry
Add Immediate to Accumulator, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare Accumulator with Memory
Set Memory Bit
Reset Memory Bit
Test Accoumulator Bit
Test Memory Bit
Test H Port Bit
TestTimeflag
Test Carry flag
Set Carry flag
Reset Carry flag
Jump
Jump in Current Page
Jump with Accumulator
Call Subroutine
7
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
17
1
0
0
Ir
RT
OTD
OA
OB
OP
OPM
IA
IB
IK
NOP
Return from Subroutine
Output Table Data
Output Accumulatorto Port A
Output Accumulator to Port B
Output Accumulatorto Port deSignated Port Pointer
Output Memory to Port P designated Port Pointer
Input Port A in Accumulator
Input Port B in Accumulator
Input Port K in Accumulator
No Operation
0
0
0
0
0
0
0
0
0
0
Instruction Code
5 4 3 2 1
0 0 1 0 0 0
0 1 0 0 0 0
1 1 0 0 0 0
0 0 1 13 12 I,
0 1 0 Is 12 I,
1 1 0 0 10 I,
0 0 1 0 1 0
1 0 1 0 1 0
1 0 1 0 1 0
0 0 0 0 1 0
0 0 1 0 0 0
0 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 0 0
0 0 1 1 0 0
0 0 0 0 0 0
1 0 1 0 1 1
1 0 1 1 1 0
0 0 0 1 0 0
0 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 0
1 0 1 0 0 0
1 0 0 0 1 1
1 0 0 1 1 0
1 0 0 1 1 1
0 0 0 Is 12 I,
1 0 1 1 0 1
1 0 1 1 1 1
0 1 1 1 0 I,
0 1 1 1 1 11
0 1 0 0 0 I,
0 1 0 0 1 I,
0 1 0 1 1 0
0 1 0 1 1 1
1 0 0 0 0 1
1 0 0 0 0 0
1 0 0 0 0 0
0 1 1 0 110 I.
16 I. I. Is 12 I,
1 I. I. 13 12 I,
1 0 0 0 0 1
0 1 1 1 110 I.
I. 15 I. Is 12 11
1 0 1 1 0 0
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 0 1
1 1 1 1 1 0
0 0 0 0 0 0
6
0
0
0
0
10
10
10
0
1
0
0
0
0
0
0
0
Byte
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
2
2
1
1
1
1
1
8
2
2
1
1
1
0
1
0
0
0
1
0
0
10
0
0
10
10
10
10
0
0
0
0
10
10
10
1
1
1
1 1-15
0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
2
73
• MSM58421 .---------------------------------------------------
TYPICAL PERFORMANCE CURVES
Output Current (lOL) TYP
Output Current (I0H) TYP
(VDD
20
~
E
= 5V, Ta = 25°C)
-
."
C"
E
E
:I:
~
6
4
10
~
U
(fJ
12>-
/
V
:J
:J
N
j
8
c:
!
.Y.
"0
c:;
12
"
8
~
. r-.....
c:
'C""
............
:J
!
.Y.
"0
c:;
E
:J
E
6
4
'x
'x
'"
'"
:2
:2
o
o
7
S
3
Power supply voltage VOO (V)
o
SO
100
100 - t(OSC) Characteristic TYP
(CL = lSpF, Ta = 2S0C)
I
10mr--------,------=--,---------,
~~
~~~~
1m
-SO
Ambient temperature Ta (OCI
100 - VOO Characteristic TYP
10m
o
10
s
\~
0
0
1m
c:
0
'aE
ac:
"
C
5
g 100"
0
100"
!!
:;
,
u
/
/
V
10"
10K
17
7
S
3
Power supply voltage Voo (V)
lOOK
1M
10M
Clock frequency f(OSCI (Hz)
10
75
OKI
semiconductor
MSM58422
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH FLT DRIVER
GENERAL DESCRIPTION
OKI's MSM58422 is a low-power, high-performance 4-bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within the one chip is a mask ROM of 1536 x 8 bits, RAM of 40 x 4 bits, 10 input/output ports 11-bit timer-counter, clock OSCillator, 4-bit parallel arithmetic circuit, 40 static FLT drivers
etc.
MSM58422 has an instruction set which consists of 4-bit arithmetic instructions, Boolean (bit)
manipulation instructions (bit-set, bit-reset, bit-test), data input/output instructions, and 8-bit code
translation (Table data out) instructions.
Also the pseudo-bilateral ports are used for connection to the buses of other 8-bit systems.
FEATURES
•
•
•
•
•
•
•
• 60-Pin Flat Package
• Built-in 11 -bit Timer
• 94% of the 52 Instructions and 1 Byte and 1
Machine Cycle
• Integrated with 10 Input/Output Ports and 40
Static FLT Driver Circuit
• PK and PH Input contain Schmidt Trigger
Circuits
Low Power Consumption CMOS 4-bit
One-Chip Microcomputer
100% Static Logic
1536 x 8 bits MASK ROM
8-bit Interface Bus
1 Stack Register
52 Instructions
+5V Single Power Supply
FUNCTIONAL BLOCK DIAGRAM
f: :
>ATA~AM40W:
FE
:
65432
9
B PK
U
PFLT6
PFTL5
PH T4
PFTl3
PFlT2
PFTL 1
Z
Z
E
R
PH
:3
2
PA
1 0
PB
SROO vG
YES SON
NSCC DO
CE 1 0
T
OSC 4.194304 MHz. SYNC = 7.63 Jlsec
76
- - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
PIN CONFIGURATION
LOGIC SYMBOL
44 Pin Flat Package
_
(0'<1" (")
~.h~
rb
~. "
.:,.:,
.:,
~ ~i i i,~ ~
(
X'tal
PFLT
PFLT
PFLT
PFLT
5-c
3-a
3-b
5-d
,
2
osc
1
PORT A
~osc
PORTS
SYNC
TEST
4
SYNC
- - - - 0 RESET
PFLT1
PFlT 2-1
a -g
PORT H - - 0 H"
PORTK
PFLT 5-e
PFLT 2-b
PFLT 1-1
PFLT1-a
DIM
DIM,
DIM (
11
9
PFLT3a-g
PFLT4a- 9
FLT DRIVE
(OUTPUTI
BUZZER
PFlT 1-b
PFLT5a-g L -_ _ /
64Hz
PFlT5-g
PFlT PH
PFLTSYNC
PFLTOSC,
PFLT2a
5V
1
16
PFLT61 --5
OV
ABSOLUTE MAXIMUM RATING
Symbol
Conditions
Limits
VDD
Ta =25°C
-0.3 -7
V
Input Voltage
VI
Ta =25°C
-0.3 -VDD
V
Output Voltage (FLT)
Va
V
Parameter
Supply Voltage
Ta =25°C
VDD -30
Ta = 25°C per 1 package
200
Ta = 25°C per 1 FLT
8
-
-55-+125
°C
Symbol
Condition
Limits
Unit
VDD
HOSC) = 0 to 4.2 MHz
4-6
V
TOp
-
-40 - +85
°C
Va
-
VDD - 26
V
MaS Load
15
TTL Load
1
Power Dissipation
Storage Temperature
Unit
PD
Tstg
mW
OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature
Output Voltage (FLT)
Fan Out (excluding FLTs)
N
-
77
• MSM58422 • - - - - - - - - - - - - - - - - - - - - - - - - -
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 - +85°C)
Parameter
Symbol
"H" Input Voltage
VIH
"L" Input Voltage
VIL
"H" Output Voltage (1)
Conditions
Min.
Typ.
Max.
3.6
Unit
V
0.8
V
VOH
10 =-15ILA
4.2
V
"H" Output Voltage (2)
VOH
10 =-4OILA
4.2
V
"L" Output Voltage (3)
VOL
10 = 1.6 mA
0.4
V
IIH/IIL
VI =VOO/OV
101-10
ILA
1/-20
ILA
-1
mA
OSCo Input Leak Current
Input Current (4)
IIH/IIL
VI =VOO/OV
"H" Output Current (1 )
10H
VO=O.4V
"H" Output Current (5)
10H
Vo = 2.5 V
-0.25
mA
mA
mA
"H" Output Current (6)
10H
VO=3V
-1
"L" Output Current (3)
10L
Vo =0.4 V
1.6
FLT Output Leak Current
ILO
VO=VOO-26V
Input Capacity
CI
f = 1 MHz, Ta = 25°C
5
pF
Output Capacity
Co
f = 1 MHz, Ta = 25°C
7
pF
Current Consumption
100
f = 4.2 MHz at no load
2
Notes: (1)
(2)
(3)
(4)
(5)
(6)
78
Applied to PA, PB
Applied to SYNC, BUZZER, 64 Hz and PFTL
Applied to PA, PB, SYNC, BUZZER and 64Hz
Applied to PH, RESET, OIM and PK
Applied to SYNC and 64Hz
Applied to BUZZER and PFLT
-10
5
ILA
mA
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
SWITCHING CHARACTERISTICS
(VDD =5V±10%, Ta =-40 - +85°C)
Parameter
SYNC Delay Time from
Clock (OSCo)
Symbol
Conditions
td
CL =50pF
Min.
Typ.
Max.
Unit
800
ns
tWH
tWL
115
ns
Cycle Time
TCY
(1 )
/Ls
SINC Pulse Width
tsw
(2)
/Ls
PA
PB Data Valid Time
PK
tDV
CL =50pF
(3)
/Ls
PA
PB Data Invalid Time
PK
tDV
CL =50pF
(4)
/Ls
Data Delay Time
tDDS
CL =50pF
(5)
ns
Port H Set Pulse Width (8)
tHW
64Hz Delay Time
from SYNC
tSFD
CL =50pF
2
/LS
BUZZER Delay Time
from SYNC
tSBD
CL =50pF
2
/Ls
SEGMENT Delay Time
from SYNC
tSSD
CL =50pF (8)
2
/Ls
Clock (OSCo) Pulse Width
500
ns
Notes: (1) tCY = 32 x 1/f(OSC)
(2) tsw = 4 x 1/f(OSC)
(3) tDV = 8 x 1/f(OSC)
(4) tDIV = 16 x 1 If(OSC) + 0.5 /Ls
(5) to OS = 26 x 1/f(OSC) + 1 /Ls
t.pWH
t.pWL
CLOCK (OSCol
SYNC
79
• MSM58422 • - - - - - - - - - - - - - - - - - - - - - - - - -
~-------------tCY~(l~)----------~
SYNC
(4)
t---tDIV·:.=.----+-(S)
PA,PB,PK
IN VALID
INPUT MODE _ _ _ _ _ _.j-_
_ _ _ _--'"
PA,PB
OUTPUT
MODE
_____
IN VALID
'--_ _..J '-_ _ _ _ _ _ _ __
~)(~:I·~~~~~~~~~O~L_~_D_:_:_~5_~_-_- -_-_-_-_-_-~~~~~~-N-E-W-D-A-T-A-___
U
PH
Notes: (6) When data input from PA or PB, set the contents of PA or PB to "1" prior to reading instruction.
(7) Alteration by the instructions relative to output ports PFLT (It is in the case that the outputs of open drain are pulled down to GND by a resistor below 20 k 0).
SYNC
______ n
'~
THB '.m"CT'O. CYCLE
lSxl/f(OSC)
.1.
TINH
15xl/f(OSC)
.1.01 xl/f(OSC)
Notes: (8) At execution of the THB instruction, any input made during a period of TINH (15
1If(OSC) shown in the above figure may be neglected.
80
x
- - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
32 pulses
1024 pulses
32 pulses
--~
tSBD
tSFD
64Hz
.::::tr::=.=...----------- ----~------------------------
DIM, DIM2
SYNillJLJlJlJL _______ _
L
L
SEG
H
L
SEG
L
H
SEG
Notes: (9) The waveform shown above is in lighting up state, in the case that that open-drain output
of FLT driver is pulled down to GND by a resistor below 20 kil.
DIM 1 and DIM 2 inputs must be in the state specified above.
81
eMSM58422e-----------------------------------------------DESCRIPTION OF TERMINALS
GND {Pin 33)
Circuit grounding potential
VDD (Pin 23)
Main power supply
OSCo (Pin 17)
Input of the internal oscillation circuit at one
side of the crystal resonator and ceramic
vibrator.
OSC 1 (Pin 16)
Output of the internal oscillation circuit at the
other side of the crystal resonator and ceramic
vibrator (not TTL compatible)
PA, PB (Pins 19 - 22 and 24 - 27)
These are quasi-bidirectional ports for a 4-bit
parallel I/O. To input data from these ports, it is
necessary to write a "1" to them beforehand.
When nothing is applied to their terminals, the
content of the output ports is written into them
so they can also be used as registers. In addi~
tion, it is possible to use them to make an 8-bit
parallel output depending on instructions.
PK (Pin 31)
1-bit input port with no latching function. Contains Schmidt a Schmidt Trigger Circuit.
PH (Pin 14)
Input port with latching function to be set by
negative logical signal.
This terminal is set at the time the negative
logical signal is applied to it from the outside. It is
reset automatically after execution of the test
instruction at this port.
RESET (Pin 18)
Reset must be active for greater than 1
machine cycle.
The RESET Signal input has priority over all
of other signals and performs the following
functions:
(1) Resets all bits of the program counter;
(2) Resets the latches of I/O ports PA, PB and
output port PFLT6;
(3) Resets the timer flag (TMF);
(4) Resets the accumulator;
(5) Resets the skip F/F Circuit;
(6) Resets the machine cycle to MI;
(?) Resets the output port PFL T5-1· to the data
of 7 Seg PLA address 0;
Since the RESET terminal is pulled up to VDD
by an internal resistor (approx. 800 kn), it is
possible to activate power ON/reset by
connecting it to an external capacitor.
SYNC (Pin 15)
This is a general-purpose synchronizing
signal output. The signal is output at the
beginning of each machine cycle. Output
constantly, this signal is used also as a clock
pulse to external units.
One SYNC cycle is 32 times that of the
original oscillation (8 f.1s when the clock pulse is
4 MHz).
82
PFL T 1 - 6 (Pins 1 - 13 and 34 - 60)
These are 7 -bit and 5-bit parallel output
ports, respectively. They are used to directly
drive an FL T (static type). Specification of each
port is accomplished by the port pOinter (PP),
which is a 4-bit register and is set to the
contents of the accumulator by the LPA
instruction.
Latching data of each port is output through
the logical AND operation with the DIMA Signal
(later described) and via buffer circuits. (When
the data in the latch is 1, DIMA is output. When it
is 0, the output is at high impedance.)
Content of PP
Port Specified
b3
b,
b,
bo
x
0
0
0
PFLT1
x
0
0
1
PFLT2
x
0
1
0
PFLT3
x
0
1
1
PFLT4
x
1
0
0
PFLT5
x
1
0
1
PFLT6-1 -4
x
1
1
0
PFLT6-5, BI and BZ
x
1
1
1
-
x : Don't care
BI: 7 Segment Decoder PLA Blank Input
BZ: Control Signal output for the buzzer output
The inputs with the latching function of ports
PFLT1-5 are connected to the outputs of the 7
segment decoder PLA and that of PFLT6 directly
to the internal buses.
DIM1, DIM2 (Pins 28, 29)
Input terminals for the dimmer control of
output ports PFLT1-6.
DIM1
DIM2
DIMA
o
o
1/4 duty
1/8 duty
1/16 duty
1
1
o
o
1
1
1
BUZZER (Pin 30)
This terminal outputs the value of the logical
AND operation between latching bit 2 of output
port PFLT6 and the timer output (05).
By externally connecting a resistor and a
transistor, this BUZZER output terminal is used
to control an alarm, buzzer etc.
64 Hz (Pin 32)
This is an output terminal, whose frequency
is 1/65536 of the OSCO. For example, when the
frequency of oscillator is 4.194304 MHz, the
frequency of the 64 Hz signal output is given 64
Hz.
This output pulse is used for adjusting the
frequency. Its duty is 50%.
- - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
INSTRUCTIONS LIST
Mnemonic
ClA
Cll
ClH
lAI
lLi
lHI
l
lAl
llA
lAW
SI
lWA
lPA
lTI
Description
INA
INl
INM
INW
DCA
DCl
DCM
CAO
RAl
AC
AS
AIS
DAS
CM
5MB
RMB
TAB
TMB
THB
TTM
TC
SC
RC
J
Clear Accumulator
ClearDPl
ClearDPH
load Accumulator with Immediate
load DPl with Immediate
load DPH with Immediate
load Accumulator with Memory
load Accumulator with DPl
load DPl with Accumulator
load Accumulator with W Register
Store Accumulator to Memory then Increment DPl
load W Register with Accumulator
load Port Pointer with Accumulator
load Timerwith Immediate "0" (Clear Timer & TMF)
Exchange Accumulator with Memory
Increment Accumulator
Increment DPl
Increment Memory
Increment W Register
Decrement Accumulator
Decrement DPl
Decrement Memory
Complement Accumulatorof One
Rotate Accumulator left through Carry
Add Memory to Accumulator with Carry
Add Memory to Accumulator, Skip if Carry
Add Immediate to Accumulator, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare Accumulator with Memory
Set Memory Bit
Reset Memory Bit
Test Accoumulator Bit
Test Memory Bit
Test H Port Bit
Test Time flag
Test Carry flag
Set Carry flag
Reset Carry flag
Jump
JC
JA
CAL
Jump in Current Page
Jump with Accumulator
Call Subroutine
RT
Return from Subroutine
Output Table Data
Output Accumulator to Port A
Output Accumulatorto Port B
Output Accumulator to Port designated Port Pointer
Output Memory to Port P designated Port Pointer
Input Port A in Accumulator
Input Port B in Accumulator
Input Port K in Accumulator
No Operation
X
OTD
OA
OB
OP
OPM
IA
IB
IK
NOP
7
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
I,
1
0
0
17
0
0
0
0
0
0
0
0
0
0
6
0
0
1
0
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
I.
1
1
0
I.
1
1
1
1
1
1
1
1
1
0
Instruction Code
5 4 3 2 1
0 1 0 0 0
1 0 0 0 0
1 0 0 0 0
0 1 13 12 I,
1 0 13 I. I,
1 0 0 10 Il
0 1 0 1 0
0 1 0 1 0
0 1 0 1 0
0 0 0 1 0
0 1 0 0 0
0 0 0 0 0
0 1 1 0 0
1 0 1 0 0
0 1 1 0 0
0 0 0 0 0
0 1 0 1 1
0 1 1 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
0 1 0 0 0
0 0 0 1 1
0 0 1 1 0
0 0 1 1 1
0 0 I. I. Il
0 1 1 0 1
0 1 1 1 1
1 1 1 0 Il
1 1 1 1 I,
1 0 0 0 I,
1 0 0 1 I,
1 0 1 1 0
1 0 1 1 1
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
1 1 0 1,0 I.
I. I. 13 I. Il
I. I. 13 I. I,
0 0 0 0 1
1 1 1 1,0 I.
I. I. 13 I. Il
0 1 1 0 0
1 1 0 0 0
1 1 0 0 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 1
1 1 1 0 1
1 1 1 1 0
0 0 0 0 0
0
0
0
0
10
10
10
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
10
0
0
10
10
10
10
0
0
0
0
1
e
Byte
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
10
1
1
1
2
e
10
1
1
1· 1-15
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
1
2
1
1
1
1
1
1
1
1
83
OKI
semiconductor
MSM5847
CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
OKI's MSM5847 microcontroller is a low-power, high performance single-chip device implemented in complementary metal oxide semiconductor technology. Integrated onto single chip are 1536 x
8 bits of mask program ROM, 96 x 4 bits of data RAM, 7 input/output lines, 1 output line, a timer, LCD
Driver and oscillator. Program memory is byte wide and data paths are organized in 4 bit nibbles. RAM
is bit addressable. 43 instructions include binary, logical operations; bit set, reset, test; multifunctional instruction (increment, skip); subroutine call and return. 95% of instructions are single byte, single
cycle operations.
FEATURES
• Low Power Consumption 50 JJ-A Typical
• 1.SK x 8 Internal ROM
• 96 x 4 Internal RAM
• 7 I/O lines, 1 output line including 8 bit data
bus
• 13 bit Timer
• Self-contained Oscillator
•
•
•
•
•
•
•
43 Instructions
2 Stack Levels
-20° to +70°C Operating Temperature
3 V Operating VDD
61 OJJ-s Cycle Time @32.768 kHz
44 pin Flat Package
Chip Form
FUNCTIONAL BLOCK DIAGRAM
DATA MEMORY (RAM)
16x6X4bit
I
DSPRAM
w
LCD DRIVER
Timing
1/3 dutyl/3 bias
222018161412109676543210
23211917151311
321
34 B
321 0
32 1 0
\......J
Hz U
Z
SROOVG
'-----1
L-....J
PA
PB
YESSDN
NSCCDD
CE01
Common
Segment
84
Z
E
R
T
• MSM5847.
PIN CONFIGURATION
LOGIC SYMBOL
44 Pin Flat Package
Ao
A.
A,
A,
Bo
B.
B,
B,
8EGMENTO
: }ortA
_ }ortB
-J
8egmenta
seg~ent23
23
34 Hz
BUZZER
SYNC
+3V
VDD
OV
GND
COMMON 1
COMMON 2
COMMON3
34 HzOutput
--- Buzzer Output
__ Synchronized
Signal
Segment 22
Segment 21
Segment 20
Segment 19
Segment18
Segment 17
Segment 16
Segment 15
Segment 14
Segment 13
Segment12
PBo
PB,
PB,
PB,
SegmentO
Segment 1
Segment 2
Segment 3
Segment 4
Segment 5
Segment 6
-- Common 1
Common 2
Common3
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
Conditions
Limits
Unit
-0.3 -7
V
-0.3 -VOO
V
-0.3 -VOO
V
-
-55 - +125
°C
Symbol
Condition
Limits
Unit
VOO
HOSC) = 32.768 kHz
2.7 - 3.3
V
TOp
-
-20 -+70
°C
VOO
Input Voltage
VI
Output Voltage
Vo
Storage Temperature
Tstg
Ta
25°C
=
OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature
85
eMSM5847e---------------------------------------------------AC CHARACTERISTICS
(Voo = 3V± 10%, Ta = -20 -
Parameter
+70°C)
Symbol
Condition
Min.
Typ.
Max.
Unit
t
CL =50 pF
-
-
5
J.LS
15
-
-
J.Ls
SYNC Oelay Time
from Clock (OSCo)
Clock (OSCo) Pulse Width
tWH
tWL
Cycle Time
tCY
-
Note (1)
-
-
J.Ls
SYNC Pulse Width
tsw
-
Note (2)
-
-
J.Ls
PA, PB Oata Valid Time
tov
-
Note (3)
-
-
J.Ls
PA, PB Oata Invalid Time
tOIV
CL=50pF
-
-
Note (4)
J.Ls
Oata Oelay Time
toos
-
-
-
Note (5)
J.Ls
Note: (1)
(2)
(3)
(4)
(5)
tCY =
tsw =
tov =
tOIV =
to OS =
20 x 11f (OSC)
2 x 11f (OSC)
4 x 1If" (OSC)
8 x 11f (OSC) + 20 J.LS
1 7 x 11f (OSC) + 40 J.LS
f(OSC)
tCY
tsw
[
tov
tOIV
toos
=32.768kHZ]
= 610J.Ls
= 61J.LS
= 122J.Ls
= 264J.Ls
= 558.5J.Ls
tq,WL
tq,WH
CLOCK(OSCo)
SYNC
_%
tCY
,,----
tsw
SYNC
K
h
tDiV
PA,PB
Input mode
INVALID
tDV
"'
VALID
INVALID
tDDS
PA,PB
Output mode
86
OLD DATA
NEW DATA
----------------------------------------------------4. MSM5847.
DC CHARACTERISTICS
(Voo = 3V± 10%, Ta = -20 - + 70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
VIH
-
VOO
-0.2
-
-
V
"L" Input Voltage
VIL
-
-
-
0.3
V
0
-
0.2
V
1/3 VOO
-0.2
-
1/3 VOO
+0.2
V
2/3 VOO
-0.2
-
2/3 VOO
+0.2
V
VOO
-0.2
-
VOO
V
Vo
V,
*1
Common, Segment
Output Voltage
V2
Applicable to
Common 1-3
Segment 0-23
Va
"H" Output Voltage
*2 *3 *4
VOH
10 = 1loLA
VOO
-0.2
-
-
V
"L" Output Voltage *2
VOL
10 = 1loLA
-
-
0.2
V
"L" Output Voltage *3 *4
VOL
10= 1 mA
-
-
1.0
V
OSCo Input Current
IIH/IIL
VI=VOOIVI=OV
-
-
5/-5
loLA
RESET Input Current
IIH/IIL
VI=VOOIVI=OV
-
-
1/-15
loLA
Current Consumption
100
VOO=3V
f = 32.768kHz,
no load
-
50
100
loLA
Note: *1 Applicable to PAo-2, PBo-a, SYNC and 34 Hz
*2 Applicable to PAa
*3 Applicable to BUZZER
Level of Output Voltage for Common, Segment
------------V3
-----V2
-------V,
'-----'- -
-
-
- Vo
87
eMSM5847e'------------------------------------------------TYP. Output Current (lOL) vs Output
Voltage (VOL) for Low-level State
TYP. Output Current (lOH) vs Output
Voltage (YOH) for High-level State
(VOO=3V, Ta=25°C)
(VOO=3V, Ta=25°C)
-2.0
10
-1.8
9
-1.6
8
-1.4
7
34 Hz terminal
OJ
.
15
a.
0
::l~
o..C
u8
OSP digit. AP
0
0
0
1 0
"3
n 2 n 1 no
+-
(PC) + n + 1. if C = 1
PC
+-
(PC) + n + 1. if Z = 1
or C = 1
+-
(Port)
P
Port
A
AP
1 P
Port
A
Port +- (AP)
0
Port
0
Port +- 0
0
P
digit
A
digit +- (AP). (ACC)
digit
A
digit +- (AP) via table
OSPF digit. AP
0
0
1
1 0
P
HALT
0
0
0
1 0
0
0
0
0
0
0
0
0
0
Halt CPU
NOP
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
0
=0
97
OKI
semiconductor
MSM5054
CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTRQLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5054 is a low-power, high-performance single-chip microcontroller employing
complementary metal· oxide semiconductor technology. Integrated onto a single chip are 4-bit of ALU,
14K bits of mask programmable ROM, 248 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port and output port.
The MSM5054 is widely used in electronic products requiring low power operation, for example,
Clocks, Timers and Games.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3 /LA Typical
1024 x 14 Internal ROM
62 x 4 Internal RAM
6 Input Port
4 Output Port
4 x 4 Key Matrix Input (SI-S., Ml-M4)
44 LCD Driver
(1/2 Duty, 112 Bias, 88 Segment)
• 40 Instructions
• 1.5 V or 3 V Operating Voltage
(Masking Option)
• 32.768 kHz Crystal Oscillator
• 122 .1/-,s Instruction Cycle
• -20 to 75°C Operating Temperature
• 74 pad die
FUNCTIONAL BLOCK DIAGRAM
80----1
LO·
L======J~~~~~~~~~~015PLA
LATCH
.nd
DRIVER
SEGMENT
OUTI
\
SEGMENT
OUT44
COM l
COM,
INSTRUCTION
DECODER
5,
I
S.
1! I I I 1
98
1111 III
------------------------------------------------------'. MSM5054 •
LOGIC SYMBOL
CHIP PAD LAYOUT
SEG44
OXlllATION[
SEGMENT
OUT 1
)
INPUT"ORT [
15,- 54)
INPU,~~~:,j
[
SEGMENT
OUT..
COM 1
OUTPUT PORT [
(M,-M4)
COM,
SO
lO
RESET
~~[
BUZZER
OUTPUT
LAMP OUTPUT
32Hz
SOURCE
T,
T,
T3
T4
T,
]TEST
SEG1
SEGMENT OUTPUT
CHIP SIZE 4.68 x 4.23 (mm)
PIN DESCRIPTION
Designation
Function
VDD
Circuit ground potential
VSS ,
Power source (-1.5 V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 JLF capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 JLF capacitor.
VCP", VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 JLF capacitor.
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T,-Ts
Terminals to test internal logic, T 1 - T3 and T s are pulled down to VSS ,.
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS ,.
After power is turned on, the MSM5054 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
99
FUNCTIONAL DESCRIPTION
A block diagram of the MSM5054 is given on
page 97. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5054 user's manual.
Program ROM
The MSM5054 addresses up to 1 K word of
internal mask programmable ROM. Each word
consists of 14 bits, and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 62 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified by the page register, but direct
addressing is available in Page O.
Column address is directly addressed by the
operand of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C) depending on the condition.
Program Counter (PC)
The program counter is 10 bits wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of the Jump or Branch instruction.
There is no boundary in the ROM, so the
Jump or Branch instruction can be put anywhere
inthe ROM.
100
Input/Output Port
Input Port (81 - 84)
The input port (S1 - S4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the SWITCH instruction.
Input Port (K1 - K4)
The input port (K1 - K2) is a 2-bit parallei
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the KSWITCH instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of the data latches
are rewritten by a matrix instruction.
Display Function
The MSM5054 is provided with a segment
output terminal which can directly drive a 1/2
bias, 112 duty LCD, and the common drive
output terminal COM1 and COM2. The segment
drive circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with a display instruction, the
LCD drive waveform is output to the segment
drive output terminal.
Time Base
The time base of the CPU is provided by
connecting a 32.768 kHz crystal to the XT and
XT pins. One machine cycle is 122.1 /Ls.
A hardware divider of up to 1 Hz is provided,
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
--------------------------------------------------__e. MSM5054.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage 1
Symbol
Conditions
Limits
Unit
VOO-VSS,
Ta = 25°C
-0.3 to +2.0
V
Supply Voltage 2
VOO-VSS2
Ta =25°C
-0.3 to +4.0
V
Supply Voltage 3
VOO-VEE
Ta =25°C
-0.3 to +4.0
V
Input Voltage
VIN,
Ta =25°C
VSS, -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
°c
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Unit
Symbol
Limits
VOO-VSS,
1.25 to 1.65
V
Topr
-20 to 75
°c
DC CHARACTERISTICS
(VOO =OV, VSS" VEE = -1.55V, VSS 2 = -3.0V, CI = 30kn, Ta = 25°C)
Limits
Parameter
Symbol
Condition
Unit
Min.
Power supply current
100
Oscillation start
voltage
-VOSC
~ithin
5 seconds
SS, terminal
Typ. Max.
-
3.0
-
/LA
1.45
-
-
V
-4
-
-
4/-4
-
IOH,
VOH, =-0.2V
10M,
VOM, =VSS,
lOLl
VOL, =-2.8V
4
-
IOH2
VOH2=-0.2V
-0.4
-
-
IOL2
VOL2=-2.8V
0.4
-
-
Output current 3
BO
IOH3
VOH3=-0.4V
-50
-
-500
IOL3
VOL3=-0.8V
VSS,= -1.25V
VEE =-1.25V
VSS 2 =-2.4V
2.5
-
7.5
Output current 4
LO
IOH4
VOH4 = -0.55V
-
-83
IOL4
VSS , =-1.25V
VEE=-2.4V
VSS 2 =-2.4V
-21
VOL4 = -1.15V
1
-
-
IOH5
VOH5=-0.5V
-100
-
-
IOL5
VOL5=-1.0V
1.5
-
7.5
Input current 1
S,-S4
IIH,
VIH, =OV
1
10
50
IlL,
VIL, = -1.55V
-
-
-0.2
Input current 2
K"K2
IIH2
VIH2=OV
IIL2
VIL2 = -1.55V
Oscillator built-in
capacitor
CO
Output current 1
COM
Output current 2
SEGMENT
Output current 5
M,-M4
± 0.2V
/LA
-
2.5
6
12
-
-
-0.2
20
-
/LA
/LA
/LA
p.A
/LA
/LA
pF
101
e MSM5054e---------------------------------------------------MEASURING CIRCUIT
VCP
VCM
Ca
XT
XT '------=r-
XTAL
O.l.uF
30pF
32.768kHz
TYPICAL APPLICATION
LCD
Lamp
SI-'S2 -'S3 ...L.
S4
-L.
COM I
SI
S2
S3
S4
SEGMENTS
COM2
LO
SO
MSM5054
VSS I
XT
(CO=20pF)
Cl
VOO
AC
V
SS2
VEE
C3
C4
5- 35pF
O.l.u F
1.5V
20mH
102
---------------------------------------------------.. MSM5054·
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
c:
0
:;
7
AOOACC,AP
0 0 0 0 0 P 0
AOO#O,AP
0
SUB ACC,AP
0 0
SUB#O,AP
0
1 1 0 0
o
0
5 4
6
3
1 0 0
P
D
1 P 0
1 0 0
2 1 0
A
AP - (AP) + (ACC)
A
AP-(AP) +0
A
AP - (AP) - (ACC)
1 1 0 1 P
0
A
AP-(AP)-D
o
N+ 1
A
AP - N adjust {(AP)j
Q;
a. AOJUSTN,AP
0
CMPACC,AP
0
0 0
E CMP#O,AP
0
1 0
INCAP
0
1 1 0 0 P 0 0 0
DECAP
0
1 1 0
XORACC,AP
0 0 0 0 0 P 0
XOR#D,AP
0
BITACC,AP
0 0 0 0 0 P 1 1 1 0
A
BIT #O,AP
0
A
I (AP)VD
A
:
i
:5
~
c:
0
1 1 0
0 0
0 P
A
AP-(AP) + 1
1
A
A-(AP) -1
1 1 1
A
AP - (AP)1i(ACC)
A
AP-(AP)1iO
1 1 1 1 P
1 0
0
1 0 P
D
iii BIC ACC, AP
0 0 0 0
1 P 0
0
1 P
BIC #0, AP
1
1 P 0 0 0
0 0 0 0 0
-
(AP) - (ACC)
(AP)-D
D
~ BISACC,AP
Q;
a. BIS#O,AP
0
0
A
A
1 P 1 1 1 0
1 1 P
P 0
1 1 0
1 0 0 0 P
1 0 0
D
1 1 0
0
(AP) V (ACC)
APV(ACC)
A
(AP)VD
A
APA (ACC)
A
APAD
;: ASRAP
0 0 0 0 0 P 0 0
1 1
A
l.(C) 0 - (AP)J
rn
ASlAP
0 0 0 0
1 1
A
(C)-(AP)-O
ClZ
0 0 0 0 0 0
1 0
ClC
0 0 0 0 0 0
1 0 0
.c
c:
0
1 P 0 0
1 0 0
0 0 0
Z-O
1 0
0 0 0
C-O
0 0 0
~
Q; ClA
a.
0 SEZ
01
ca
u:: SEC
0 0 0 0 0 0
1 0
1 1 0
0 0 0 0
1 0
1 0
1 0 0 0 0 0
o
0 0 0
1 0
1 0 0
SEA
0 0 0 0
1 0
1 0
.....
~
FORMATAP
as
Q.
tJ)
FORMATN
0
o
o
0 0
b, bo
OUTPUT PORT (M,-M4)
...... Mn (n=1 , 2, 3, 4)
Freq ...... freq, Mreg ...... sound
Buzzer start
Buzzer stop
LDON/OFF
A
Digit ...... (AP), (ACC)
1 1
A
FMT reg ....... (AP)
0 0 0 1 0 0 0 0 1 1
N
FMT reg ....... N
A
Digit ...... (AP) via table
0 0 1 0 0 P
1 1 0
digit
1 1 P 0 0
DSPF digit, AP
0 0
HALT
0 0 0 1 0 0 0 0 0 0 0 0 0 0
INTENAB
32/16
0
0
0 0 1 0 0 1 0 1 1 1 0 0 0
0 0 1 0 0 0 1 0 0 0 0 1 0
Enable timer
INTDSAB
.c 32/16
0
0
0 0 1 0 0 1 0 1 1 0 1 0 0
0 0 1 0 0 0 1 0 0 0 0 0 1
Disable timer
...CD
tJ)
0
ad
g
c:
0
0
::J
Il.
0
104
1 1 0
P
digit
Halt
INTMODEAP
1 1 0
1 0 P 0
1 0 0
A
AP ...... Interrupt mode
PAGEAO
1 1 0
1 1 0 0
1 0
1
A
Preg ...... (AO)
PAGEN
0 0
0 1 0 0 0 1 0 1
N
Preg ...... N
RATEAP
1 1 0
A
AP ...... DIVIDER (8 Hz-1 Hz)
RSTRATE
0 0 0 1 0 0 1 0 0 0 1
BACKUP
ON/OFF
0 0 0 1 0 0 0 0 0 1 b3 b2 0 0
Backup ON/OFF
NOP
0 0 0 0 0 0 0 0 0 0 000 0
No operation
1 0
P 1 0 0 1
o
0 0
DIVIDER (8 Hz-1 Hz) ...... 0
OKI
semiconductor
MSM5055
CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5055 is a low-power, high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are 4 bits of
ALU, 25K bits of mask programmable ROM, 384 bits of data RAM, crystal oscillator, voltage doubler,
timer, LCD driver, input port, output port and interface circuit for voice LSI (MSM6212).
The MSM5055 is widely used in electronic products requiring low power operation, for example,
multi-functioned watches, voice synthesizer watches and games.
FEATURES
• Low Power Consumption 3 p.A Typical
• 1792 x 14 Internal ROM
• 96 x 4 Internal RAM
• 4 x 2 Input Port
• 4 x 1 Output Port
• 4 x 4 Key Matrix Input (K1-K4, M1-M4)
• 60 LCD Driver
(112 Duty, 112 Bias, 120 Segment)
•
•
42 Instructions
1.5 V or 3 V Operating Voltage
(Masking Option)
• 32.768 kHz Crystal Oscillator
• 122.1 p.S Instruction Cycle
• -20 to 75°C Operating Temperature
• 94 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
96 word x 4 bit
LD
SEGMENT
M1
OUTl
\
M4
LO
SEGMENT
OUT60
K1
,COMl
\
COM2
K4
S.
INSTRUCTION
DECODE
I
S.
1792word x 14bit
!I!j I!
AC T1 T2 T3 T4 T5
105
• MSM5055 . - - - - - - - - - - - - - - - - - - - - - - - - - -
CHIP PAD LAYOUT
LOGIC SYMBOL
r,,::;;:;;::;n;:;n;:;r:;n;::;n.:;n;::;;:iMfTI::;nrrnTITirriflr'il SEG31
OSCILLATION (___
*
VDD
VSS2
VCP
VCM
SEGMENT
DUn
Sl
INPUT PORT [
(81-$4)
82
$3
S4
INPUT PORT [ -
K2
Kl
(Kl-K4)
~~
LCD DRIVER
M2
IM1-M4i
M3
M4
-
LOAD
LO
RESET
AC
AC,
COM2
BD
LD _
BUZZER OUTPUT
LAMP OUTPUT
AC'2
~~~1
T3
T4
T5
AC
T,
K.
T,
RESET
T2
Tl
POWER SOURCE [ - - - VEE
- - - VCP
VCM
SD
LD
K,
gD9~~tU LSE
XTOUT -
VSSl
S,
S,
VEE
K,
K,
COMl
Ml
OUTPUT PORT [ - -
XTOUT
SEGMENT
OUT60
]
--
TEST
T,
T.
La
15
COM2t.::::.=================:.;;....J SEG30
SEGl
SEGMENT OUTPUT
CHIP SIZE 5.49 x 4.71 (mm)
PIN DESCRIPTION
Designation
VDD
Circuit ground potential
VSS ,
Power source (-1.5 V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 p.F capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 p.F capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 p.F capacitor.
XT,XT
106
Function
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T1 -T5
Terminals to test internal logic, T1 - T3 and T5 are pulled down to VSS l'
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS l'
After power is turned on, the MSM5055 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
LO
Load data terminal of M 1 to M.
AC2
Reset terminal for external circuit
XTOUT
Clock output for eXternal circuit
----------------------------------------------------. MSM5055 •
FUNCTIONAL DESCRIPTION
A block diagram of the MSM5055 is given on
page 104. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5055 user's manual.
Program ROM
The MSM5055 addresses up to 1 K word of
internal mask programmable ROM. Each word
consists of 14 bits, and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 62 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified by the page register, but direct
addressing is available in Page o.
Column address is directly addressed by the
operand of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C) depending on the condition.
Program Counter (PC)
The program counter is 10 bits wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of the Jump or Branch instruction.
There is no boundary in the ROM, so the
Jump or Branch instruction can be put anywhere
in the ROM.
Input/Output Port
Input Port (51 - 54)
The input port (S1 - S4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the SWITCH instruction.
Input Port (K1 - K4)
The input port (K1 - K2) is a 2-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the KSWITCH instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of the data latches
are rewritten by a matrix instruction.
Display Function
The MSM5055 is provided with a segment
output terminal which can directly drive a 1/2
bias, 112 duty LCD, and the common drive
output terminal COM1 and COM2. The segment
drive circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with a display instruction, the
LCD drive waveform is output to the segment
drive output terminal.
Time Base
The time base of the CPU is provided by
connecting a 32.768 kHz crystal to the XT and
XT pins. One machine cycle is 122.1 JLs.
A hardware divider of up to 1 Hz is provided,
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
107
• MSM5055 .------------------------------------------~--------
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Limits
Unit
Supply Voltage 1
VOO-VSSI
Ta =25°C
-0.3 to +2.0
V
Supply Voltage 2
VOO - VSS 2
Ta = 25°C
-0.3 to +4.0
V
VOO -VEE
Ta = 25°C
-0.3 to +4.0
V
Input Voltage
VIN,
Ta = 25°C
VSS , -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
°c
Parameter
Supply Voltage 3
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VOO-VSSI
1.25 to 1.65
V
Topr
-20 to 75
°c
DC CHARACTERISTICS
(VOO =OV, VSS " VEE = -1.55V, VSS 2 = -3.0V, CI = 30k!), Ta = 25°C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Power supply current
100
Oscillation start
voltage
-VOSC Within 5 seconds
VSS , terminal
Output current 1
COM
IOHI
VOH, =-0.2V
IOMI
YOM, =VSS, ± 0.2V
Typ. Max.
-
3.0
-
/LA
1.45
-
-
V
-4
-
-
4/-4
-
-
lOLl
VOL, =-2.8V
4
-
Output current 2
SEGMENT
IOH2
VOH2 =-0.2V
-0.4
-
-
IOL2
VOL2=-2.8V
0.4
-
-
Output current 3
AC2 LOAD, XTOUT
IOH3
VOH3=-0.5V
-10
-
-
IOL3
VOL3 = -1.05V
10
-
-
Output current 4
M1-M4
IOH4
VOH4=-0.5V
-100
-
-
IOL4
VOL4 =-1.0V
1.5
-
12.7
Output current 5
LO
IOHs
VOHs = -0.55V
-21.6
-
-83
IOLs
VOLs = -1.15V
1
-
-
Output current 5
SO
IOHe
VOHe=-O.4V
-50
-
-
IOHa
VOLe =-0.8V
-
5
-
Input current 1
S,-S4
IIHI
VIH, =OV
1
10
50
IlL,
VIL, = -1.55V
-
-
-0.2
IIH2
VIH2 =OV
2.5
6
12
-
-
-0.2
-
20
Input current 2
K,-K4
Oscillator built-in
capacitor
108
IIL2
CD
VIL2 = -1.55V
VSS , =-1.25V
VEE =-2.4V
VSS 2 =-2.4V
VSSI =VEE
=-1.25V
VSS 2=-2.4V
-
/LA
/LA
/LA
/LA
/LA
/LA
/LA
/LA
pF
-----------------------------------------------------. MSM5055 •
MEASURING CIRCUIT
VCP
VCM
C3
XT
XTAL
XT
C1 . C2. C3 0.1/LF
C4
30 pF
X-tal
32.768 kHz
TYPICAL APPLICAT.ION
LCD
Lamp
COM 1
Sl--i...
S2....L
S3
....l...
S4
--l..
Sl
S2
S3
S4
SEGMENTS
COM 2
LD
SD
MSM5055
VSS 1
XT
(CD=20pF)
C1
VDD
AC
C4
5 - 35pF
O.1/L F
1.5V
20mH
109
• MSM5055 .------------------------------"----------------------
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
ADD ACC, AP
0 0 0 0
ADD#D,AP
0
SUB ACC,AP
0 0
c:
7 6
0 P 0
1 0 0
1 1 0 0 P
0 0
D
1 P 0
A
AP +-(AP) - D
A
AP +- N adjust {(AP)}
A
(AP) - (ACC)
A
(AP) -D
1
A
AP +-(AP) + 1
1
A
A+-(AP) -1
P 0 1 1 1
A
AP
A
AP +- (AP) -V- D
A
(AP) V (ACC)
A
(AP)VD
0
0 0 0 0
1 P 1 1 1 0
~ CMP#D,AP
E
0
1 0
0
0
1 1 0 0 P 0 0 0
0
1 1 0
XOR ACC, AP
0 0 0 0 0
XOR #D,AP
0 1
BITACC,AP
0 0 0 0 0
BIT #D,AP
0 1 0
1 P 0
0 0 0 0
0
ASRAP
0 0 0 0 0
en ASLAP
P 1
1 1 0
1 0 0
0 0 0 0
D
0 P 0
1 0 0 0
0
D
1 0 P
BIC#D,AP
0
o
1 1 1 P
BICACC,AP
::=
:.c
D
DECAP
0 0 0 0
...
iii
P
1 1 P
~ BISACC,AP
Q;
c. BIS#D,AP
0
AP +-(AP) +D
-AP +- (AP) - (ACC)
D
1 1 0 0
c:
A
AP +- (AP) + (ACC)
N+ 1
1 P
0
Q; ADJUSTN,AP
c.
0
CMP ACC, AP
Q
:S INCAP
~
A
A
1 0 0
.2 SUB #D,AP
a;
1 1 0
5 4 3 2 1 0
1 1 0
P
D
1 P 0
1 1 0
1 P
D
+-
A
APV (ACC)
A
(AP) VD
A
AP A (ACC)
A
AP AD
P 0 0
1 1
A
C(C)
1 P 0 0
1 1
A
(C) +- (AP) +- 0
1 0 0 0 0 0
CLZ
0 0 0 0 0 0
1 0
0
CLC
0 0 0 0 0 0
1 0 0
CD
CLA
0 0 0 0 0 0
1 0
SEZ
0 0 0 0
1 0
1 0 1 0 0 0 0 0
Z+-l
1 0 0
C+-l
c:
~
"-
C.
0
Cl
III
u::
(AP) "'V (ACC)
1 0 0 0 0
1 1 0 0 0 0
1 0 0 0 0
O-(AP):::J
Z-O
C+-O
Z-O,C+-O
SEC
0 0 0 0
1 0
SEA
0 0 0 0
1 0 1
MOV ACC, AP
1 1 1 1 0
P 0 0 0 0
A
AP+-(ACC)
'0 MOVACC,AX
1 1 1 1 0
0 0
A
AX+-(ACC)
~ MOV#D,AP
0
A
AP+-D
0 0
A
ACC+-(AP)
X
A
ACC+-(AX)
"CD
c:
~
0
1 P 0
MOVAP,ACC
1 1 1 1
MOVAX,ACC
1 1
1 1 1 0 0
JMP adrs
1 0
o a,o a
c. JMP@AP
E JMPIO@AP
...,
:::l
BEQ
BZE
110
1 1 1 0 P
+n
+n
g
0
1 1 0 0 0 0
X
D
o
Z+-l,C+-l
as a 7 as as a 4 a 3 a 2 a, a o
PC +-adrs
P 1 1 0
1
A
PC +- (PC) + (AP) + 1
0 0 0 0
1 P 1 1 0
1
A
PC +- (PC) + {(AP) A 7H } +1
0 0 0
1 0 0
0 0 0 0 0
1
1 0 n 4 n3 n 2 n, no
PC +- (PC)+n+l, if Z=l
----------------------------------------------------. MSM5055 •
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Mnemonic
Operation
131211109 8 7
6 5
4 3 2 1 0
BNE
a. BNZ
E
...,::J BCS
+n
+n
0 0 0
1 1 0
1 1 0 n. n3 n 2 n, no
PC +- (PC)+n+1, if z=o
+n
0 0
1 1 0 0 0 0 n • n3 n 2 n, no
PC +- (PC)+n+1, if C=1
BCC
+n
0
0 0 0
1 1 0
SWITCHAP
1 1 0
1 0
P 0 0 0
KSWITCHAP
1 1 0
1 0
P 0
MATRIXAP
1 1 0
MATRIXMn
.9::J
0 0 0
1 0
0 0 0
1
0
"5
1 0 0 n. n3 n 2 n, no
A
AP +-INPUT PORT (S1 - S4)
0
1 0
A
AP +-INPUT PORT (K1 - K4)
1 1 P 0 0
1 0
A
OUTPUT PORT (M 1 - M4)
+-(AP)
o M.M3M2M,
0......
"S XTCPON/OFF
a.
-=
PC +- (PC)+n+1, if c=o
1
OUTPUT PORT (M1-M4)
+- Mn (n=1, 2,3,4)
0 0 0
1 0
1 0 0 0 0 o b, bo
XTOUT ON/OFF
FREON
0 0 0
1 0 0
1 1 0
Freq +-N
BUZZER sound
0 0
1 0 0
1 1 0 0 b3 b2 1 0
Mreg +- sound, Buzzer start
BSO
0 0 0 1 0
1 1 0 0 0 o 0 0
Buzzer stop
LAMP ON/OFF
0 0 0 1 0 0 0 0 0 1 0 o b, bo
LD ON/OFF
DSP digit, AP
0 0
1 0 0
DSPH digit, AP
0 0
1 0
0
0
P
digit
1 P
digit
1
N
Digit (Low part) +- (AP), (ACC)
A
A
Digit (High part) +- (AP), (ACC)
» FORMATAP
a. FORMATN
1 1 0
1 1 P 0 0
1 1
A
FMT reg. +- (AP)
'"
0 0 0
1 0 0 0
1 1
is DSPF digit, AP
0 0
(J)
DSPFH digit, AP 0 0
N
FMT reg. +- N
P
digit
A
Digit (Low part) +- (AP)
via table
1 1 1 P
digit
A
Digit (High part) +- (AP)
via table
1 1 0
0
HALT
0 0 0
1 0
0 0
INTENAB
32/16
0 0
0
1 0
0
0 0 0
1 0
0 0 1 0 0 0 0
INTDSAB
32/16
0 0
0 1 0
0
0
0 0 0 0 0 0
1 0
1 1 1 0 0 0
1 0
1 1 0
1 0
1 0 0
Halt
Enable timer
Disable timer
0 0 0
1 0
0 0 1 0 0 0 0 0
Q; INTMODEAP
1 1 0
1 0
P 0
1 0 0
A
AP +- Interrupt mode
0
PAGEAO
1 1 0
1 1 0 0
1 0 1
A
Preg +-(AO)
PAGEN
0
1 0
1 0
N
Preg +-N
ADRSAP
1 1 0
1 1 P 0
1 1 0
A
Areg +-(AP)
0 0
1 0
0
1 1 0
N
Areg +-N
1 1 0
1 0
P 1 0 0
A
AP +- DIVIDER (8 Hz-1 Hz)
0
0 0
1 0
0
BACKUP
ON/OFF
0
0 0
1 0
0 0 0 0
1 b3 b2 0 0
Backup ON/OFF
NOP
0 0 0 0 0
0 0 0 0
0 o 0 0 0
No operation
(J)
.s::
O/!S
e"E
0
()
::::l
a. ADRSN
()
RATEAP
RSTRATE
0 0
0
0 0
0
1
1
1 0 0 0
1
1 0 0 0
DIVIDER (8 Hz-1 Hz) +-0
111
OKI
semiconductor
MSM5056
CMOS 4BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5056 is a low-power, high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,
25K bits of mask programmable ROM, 360 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port, output port and overcharge protection circuit for connection to a solar cell.
The MSM5056 is widely used in electronic products requiring low power operation, for example,
solar calculator watches and games.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3 iJ-A Typical
1792 x 14 Internal ROM
90 x 4 Internal RAM
4 Input Port
4 Output Port
4 x 4 Key Matrix Input (K,-K., M,-M.)
38 LCD Driver
(112 Duty, 112 Bias, 88 Segment)
• 42 Instructions
• 1.5 V Operating Voltage
(The solar cell can be connected.)
• 32.768 kHz Crystal Oscillator
• 122.1 iJ-s Instruction Cycle
• -20 to 75°C Operating Temperature
• 68 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
SD
A3-AO
SEGMENT
OUT t
LD
DISPLAY
LATCH
and
I
SEGMENT
OUT38
DRIVER
---+ COM l
MI
I
M,
COM 2
KI
I
K,
INSTRUCTION
OECODEA
I I I I 1I
VOD
VS$2
VSC
VCM
VSS,
VEE
vep VIN
112
---------------------------------------------------'. MSM5056 •
LOGIC SYMBOL
CHIP PAD LAYOUT
SEGMENT OUTPUT
OSCILLATION [
asc,
ase l
asc 3
SEGMENT
OUT,
SEGMENT
DUT3S
COM,
COM 2
'NPUT PORT [
(K,- K4 )
OUTPUT PORT [
(MI~ M4)
80
BUZZER OUTPUT
LD
LAMP OUTPUT
T.
T.
RESeT
VDD
T,
Vss,
POWER [
SOURCE
ADJUSTMENT for
SOLAR CELL CRAMP
VOLTAGE
T,
T,
T,
T,
VSS 2
VEE
Vsc
VCP
VCM
V'N
] TEST
CHIP SIZE 5.42 x 4.13 (mm)
PIN DESCRIPTION
Designation
VDD
Function
Circuit ground potential
VSS,
Power source (-1.5 V)
VSC
Solar cell connection terminal
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 p.F capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 p.F capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 p.F capacitor.
--
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T,-T5
Terminals to test internal logic, T, - T3 and T 5 are pulled down to VSS,.
T. is output. Test pins must be normaly open.
AC
Terminal to clear internal logic pulled down to VSS,.
After power is turned on, the MSM5056 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
VIN
Adjustment for solar cell cramp voltage
This terminal is connected to VSS, terminal through 50 - 200 k!1 resistor.
113
eMSM5056e-------------------------------------------------FUNCTIONAL DESCRIPTION
A block diagram of the MSMSOS6 is given on
page 111. Each block of logic will be briefly
discussed. For more information, please refer to
the MSMSOS6 user's manual.
Program ROM
The MSMSOS6 will address up to 1.7S K
words of internal mask programmable ROM.
Each word consists of 14 bits and all
instructions are one word. The instructions are
routed to a programmed logic array which
generates the signals necessary for control of
logic.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 90 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified with the page register, but direct
addressing is available at Page O.
Column address is directly addressed by the
operands of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and AC contents, or RAM contents and an
immediate digit. It sets or resets the flags (Z, C)
depending on the condition.
Program Counter (PC)
The program counter is an 11-bit wide
counter and specifies the address of the
program ROM.
The PC is incremented by one at every
execution of an instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of a Jump or Branch instruction.
There is no boundary in the ROM, so a Jump
or Branch instruction can be put anywhere in the
ROM.
Input/Output Port
Input Port (K1 - K2)
The input port (K1 - K4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal reSistor, and the status of
the port can be fetched by an input instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers. The contents of data latches are
rewritten by an output instruction. A key matrix
is used in combination with K1 to K4.
114
Kl
K2
-$-
K3
i
+
K4
Ml
M2
M3
M4
Display Function
The MSMSOS6 is provided with a segment
output terminal which can directly drive a 1/2
bias, 112 duty LCD and common drive output
terminals. COM1 and COM2. The segment drive
circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with the display instruction,
the LCD drive waveform is output to the segment
drive output terminal.
Time Base
Time base of the CPU is provided by
connecting a 32.768 kHz crystal to the OSC1
and OSC3 pin. One machine cycle is 122.1 /ls.
A hardware divider up to 1 Hz is provided
enabling programs to implement and a clock
function by counting signals between 16 and 1
Hz.
Solar Cell Overcharge Protection Circuit
When a solar cell is connected to prolong the
usefull life of the battery, a resistor is inserted
between the VIN pin and VSS1 to adjust the
overcharge protection voltage.
...------1 VSS,
.--'\AI.fIr---I
VIN
MSMS056
--------------------------------~--------------~- MSM5056-
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Limits
Unit
VOO -VSS,
Ta = 25°C
-0.3 to +3.0
V
Supply Voltage 2
VOO-VSC
Ta = 25°C
-0.3 to +3.5
V
Supply Voltage 3
VOO - VSS 2
Ta= 25°C
-0.3 to +6.0
V
VOO-VEE
Ta = 25°C
-0.3 to +6.0
V
Input Voltage
VIN,
Ta = 25°C
VSS, -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
°c
Parameter
Supply Voltage 1
Supply Voltage 4
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Unit
Symbol
Limits
VOO-VSS,
1.25 to 1.65
V
Topr
-20 to 75
°c
DC CHARACTERISTICS
(Voo =OV, VSS" VEE = -1.55V, VSS 2 = -3.0V, CI = 30kn, CG = 30pF, Ta = 25°C)
Limits
Parameter
Symbol
Condition
Unit
Min.
Typ. Max.
Operating voltage 1
-VSS,
VSS, terminal
2.0
V
Operating voltage 2
-VSC
VSC terminal
0
2.0
3.0
V
VSS, terminal
-
3.0
-
/LA
1.45
-
-
V
1.25 1.55
Power supply current
100
Oscillation start
voltage
Within 10 seconds
-VOSC
VSS, terminal
IOH,
VOH, =-0.2V
Output current 1
COM
10M,
YOM, =VSS,
IOL,
Output current 2
SEGMENT
IOH2
-4
-
-
4/-4
-
-
VOL, =-2.8V
4
-
-
VOH2 = -0.2V
-0.4
-
-
IOL2
VOL2=-2.8V
0.4
-
-
Output current 3
M,-M.
IOH3
VSS" VEE -1.25V
-100
-
-
IOL3
VSS 2-2.3V
3
-
8
Output current 4
SO
IOH.
VOH.=-0.4V
IOL.
VOL.=-1.15V
3
10
30
Input current
K,-K.
IIH,
VIN=-OV
5
10
15
IlL,
VIN = -1.55V
-
-
-0.2
-
20
-
pF
50
-
200
kn
Oscillator built-in
capacitor
CO
Solar battery cramp
resistor
RIN
± 0.2V
VSS, =-1.8V
VIN terminal
I VOH3 -0.4 V
I VOL3 -0.85V
-50 -100 -200
/LA
/LA
/LA
/LA
/LA
115
• MSM5056 .,----------------------------------------------------
MEASURING CIRCUIT
30pF
O.lJ1F
32.768kHz
TYPICAL APPLICATION
LCD
K1
K2
COM 2 SEGMENT COM1
K3
M2
BD
LD
K4
M4
M3
TR2
MSM5056
VDD
M1
VSG
VIN
AC
'--_---4------~----------'
116
CG : 5 ~ 35pF
Cl , C2 , C3: O.lJ1F
TR1,TR2: hfe"'200
TR2 : VCEo > 35V
Ll : 20 ~ 30mH
B
: 1.5V
R
: 50 ~ 200kn
--------------------------------------------------__e. MSM5056 •
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
c
0
~
Q)
c.
0
Operation
131211109
8
ADD ACC, AP
0
0
0
0
0
P 0
ADD #D,AP
0
1
1
0
0
P
ADCAP
0
0
0
0
0
P 0
1 0
1
SUB ACC, AP
0
0
0
0
1
P 0
1
0
0
0
1
1 0
7
5
4
1 0
0
6
3
D
SUB #D, AP
0
1
1 0
1
P
SBCAP
0
0
0
0
1
P 0
1
1
1
2
0
AP -
A
AP-(AP) - D
A
AP -
Decimal adjust
{(AP) + (ACe) + (e)l
A
AP -
(AP) - (ACC)
A
AP -(AP) - D
A
AP - Decimal adjust
{(AP) - (ACC) - (e)l
A
(AP) - (ACC)
A
(AP) - D
D
.2
Qi
E
:5
~
(AP)
+ (ACC)
A
CMP ACC, AP
0
0
0
0
1
P
CMP #D, AP
0
1 0
1
1
P
INCAP
0
1
1
0
0
P 0
0
0
1
A
AP -(AP)
DEC AP
0
1
1
0
1
P 0
0
0
1
Ii.
A-(AP) -·1
1
1
1
A
AP -
A
AP -(AP) VD
A
(AP) V (ACC)
A
(AP) VD
A
AP -
A
AP -(AP) VD
A
AP -
A
AP -(AP)AD
1
D
XOR ACC, AP
0
0
0
0
0
P 0
XOR #D,AP
0
1
1
1
1
P
BIT ACC, AP
0
0
0
0
0
P
c
BIT #D, AP
0
1 0
1
0
P
~
BISACC, AP
0
0
0
0
0
P 0
c.
BIS #D, AP
0
1 0
0
0
P
D
1
1 0
1
D
+
1
(AP)-V-(ACC)
0
~
0
co
;:
.t:
(f)
1
1 0
D
1
1 0
(AP) V (ACC)
(AP) A(ACC)
BICACC, AP
0
0
0
0
1
P 0
BIC #D, AP
0
1 0
0
1
P
ASRAP
0
0
0
0
0
P 0
0
1
1
A
L(C) 0 -
ASlAP
0
0
0
0
1
P 0
0
1
1
A
(C) -(AP)-O
D
(AP)=:J
ClZ
0
0
0
0
0
0
1
0
1 0
0
0
0
0
Z-O
c
ClC
0
0
0
0
0
0
1
0
0
1
0
0
0
0
C-O
~
ClA
0
0
0
0
0
0
1 0
1
1
0
0
0
0
Z -O,C-O
SEZ
0
0
0
0
1
0
1
1 0
0
0
0
0
Z-1
SEC
0
0
0
0
1
0
1 0
0
1
0
0
0
0
C-1
SEA
0
0
0
0
1
0
1
0
1
1
0
0
0
0
Z-1,C-1
MOVACC,AP
1
1
1
1 0
P 0
0
0
0
MOVACC,AX
1
1
1
1 0
0
Ui
MOV #D,AP
0
1
1
1 0
P
~
MOVAP,ACC
1
1
1
1
1
P 0
to
c
MOVAX,ACC
1
1
1
1
1
0
CHGAP
1
1
1
0
0
P 0
CHGAX
1
1
1
0
0
0
0
~
c.
0
Cl
ttl
u::
~
c
ttl
0
X
0
0
0
X
AX-(AeC)
A
AP-D
A
ACC -(AP)
A
ACC -(AX)
0
A
(ACe)-(AP)
A
(AeC)-(AX)
X
0
0
0
AP -(ACC)
A
0
D
0
A
117
e MSM5056e-------------------------------------------------DESCRIPTION OF INSTRUCTIONS {CO NT.)
Instruction Code
Mnemonic
Operation
131211109 8
0.
E
...,'"
7
6
5 4
3
2
1 0
JMP adrs
1
0
o
JMP @AP
0
0
0
0
0
P
1
1 0
1
JMPIO @AP
0
0
0
0
1
P
1
1 0
1
BEQ
BZE
+n
+n
0
0
0
1
1
0
0
1 0 n. n3 n 2 n, no
PC
BNE
BNZ
+n
+n
0
0
0
1
1 0
1
1
0 n. n3 n 2 n, no
PC ~ (PC) +n + 1, if Z=O
BCS
BlT
+n
+n
0
0
0
1
1
0
0
1 n. n3 n 2 n, no
PC
BCC
BGE
+n
+n
0
0
0
1
1 0
1 0
1 n. n3 n2 n, no
PC -
(PC) +n+1, if C=O
BGT
+n
0
0
0
1
1 0
1
1
1 n. n3 n 2 n, no
PC -
(PC)+n+1, if Z=O
and C=O
BlE
+n
0
0
0
1
1 0
0
1
1 n. n3 n 2 n, no
PC
~
(PC)+n+1, if Z= 1
or C=1
~
(Port)
PC
~adrs
A
PC
~
A
PC ~ (PC) + {(AP)/\ 7H } + +1
a 10 ag as a7 a6 a5 a. a3 a2 a, ao
0
~
~
(PC) + (AP) + 1
(PC)+n+1, if Z=1
(PC)+n+ 1, if C=1
,-
INP Port, AP
1
1 0
1
0
P
Port
A
AP
"'0.
0.-
OUT AP, Port
1
1 0
1
1
P
Port
A
Port
c'"
-0
OUT #D, Port
0
0
0
1 0
0
Port
D
Port - D
>
DSP digit, AP
0
0
1
0
0
P
digit
A
digit
~
(AP), (ACC)
digit
~
(AP) via table
-'"
c.
'"
"'
is
e
:::>a. c
08
118
~
(AP)
DSPF digit, AP
0 0
1
1 0
P
HALT
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Halt CPU
NOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
digit
A
OKI
semiconductor
MSM6051
CMOS 4BIT HIGH PERFORMANCE SINGLE CHIP VERY LOW POWER
MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
OKI's MSM6051 is a low-power and high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,
35K bits of mask programmable ROM, 480 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port and output port.
The MSM6051 is widely used in electronic products requiring low power operation, for example,
stopwatches with lap time memory, calculator wC!tches and handy terminals.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3ILA Typical
2560 x 14 Internal ROM
120 x 4 Internal RAM
9 Input Port
4 Output Port
4 x 4 Key Matrix Input (K1-K4, M1-M4)
66 LCD Driver (including 3 common)
(1/3 Duty, 1/3 Bias, 189 Segment)
•
•
•
•
•
•
59 Instructions
1.5 V or 3 V Operating Voltage
(Masking Option)
32.768 kHz crystal Oscillator
91.5 /1-s Instruction Cycle
-20 to 75°C Operating Temperature
101 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
120word x 4 bit
LD
M1
1
SEGMENT
Dun
M4
LO
\
SEGMENT
CUT66
K,
I
K.
s.
~.
INSTRUCTION
DECODER
PROGRAMAOM
OPTION
256 word x 1 4 bit
VSSt
VSS3
VCP
I 1 j j j j I
voo
VSS2
VEE
VCM
!I I j I Ij
AC Tt T2 T3 T4 T5 32Hz
119
• MSM6051 .-------------------------------------------------
LOGIC SYMBOL
OSCILLATION (
CHIP PAD LAYOUT
SEGMENT
oun
INPUT PORT [
(S1-84)
INPUT PORT
(K1-K4)
OPTION INPUT
OUTPUT PORT
(M1-M4)
rl
rl
SEGMENT
OUT6S
BD
LD
BUZZER OUTPUT
LAMP OUTPUT
CLOCK PULSE
OUTPUT
RESET
LOAD
] TEST
SEGMENT OUTPUT
CHIP SIZE 5.85 x 4.10(mm)
PIN DESCRIPTION
Designation
120
Function
VDD
Circuit ground potential
VSS ,
Power source (-1.5 V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 J-tF capacitor.
VSS3
Power source for LCD driver (-4.5 V)
This terminal is connected to VDD terminal through a 0.1 J-tF capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 /i-F cllpacitor.
VCp, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 J-tF capacitor.
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T,-T5
Terminals to test internal logic, T 1 - T3 and T5 are pulled down to.VSS ,.
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS ,.
After power is turned on, the MSM6051 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
LO
Load data terminal of M 1 to M4.
AC2
Reset terminal for external circuit.
XTOUT
Clock output for external circuit.
----------------------------------------------------ee MSM6051
e
FUNCTIONAL DESCRIPTION
Input/Output Port
A block diagram of the MSM6051 is given on
page 118. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM6051 user's manual.
Input Port (Sl - S4)
The input port (S1 - S4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS , by an internal resistor, and the status of
the port is fetched by a SWITCH instruction.
Program ROM
The MSM6051 addresses up to 2.5 K words
of internal mask programmable ROM. Each word
consists of 14 bits, and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 120 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified the with page register, but direct
addressing is available at Page O.
Column address is directly addressed by
operand of various instructions.
ALU
The ALU performs' 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C, G) depending on the condition.
Program Counter (PC)
The program counter is 1 2 bits wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of a Jump, Call or Branch instruction.
There is no boundary in the ROM, so a Jump
or Branch instruction can be put anywhere in the
ROM.
Stack
The MSM6051 has a 3 level stack apart from
data RAM. The contents of the PC are loaded
into the stack when a call instruction is executed
or an interrupt is generated.
Input Port (K1 - K4)
The input port (K1 - K4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS 1 by an internal resistor, and the status of
the port is fetched by a KSWITCH instruction.
Input Port (OPIN)
The input port (OPIN) is single input port.
OPIN is pulled down to VSS , by an internal
power save circuit, and the status of the port is
fetched by an input instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of data latches are
rewritten by a matrix instruction.
Display Function
The MSM6051 is provided with the segment
output terminal which can directly drive a 1/3
bias, 1/3 duty LCD, and the common drive
output terminals COM1, COM2 and COM3.
The segment drive circuit consists of the
display data latch, multiplexer and driver. If the
data is sent to the display data latch with the
display instruction, the LCD drive waveform is
output to the segment drive output terminal.
Time Base
The time base of the CPU is provided by
connecting 32.768 kHz crystal to the XT and XT
pin. One machine cycle is 91.5 !-'s.
A hardware divider up to 1 Hz is provided
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
Also, a 1/100 second digit counting function
is provided as a hardware feature to make for
easy implementation of a stopwatch function.
121
• MSM6051 .--------------------------------------------------
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Limits
Unit
Supply Voltage 1
VOO-VSSl
Ta =25°C
-2.0 to +0.3
V
Parameter
Supply Voltage 2
VOO -VSS2
Ta = 25°C
-4.0 to +0.3
V
Supply Voltage 3
VOO -VSS3
Ta =25°C
-6.0 to +0.3
V
Supply Voltage 4
VOO-VEE
Ta = 25°C
-4.0 to +0.3
V
Input Voltage
VINl
Ta =25°C
VSS l -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
°c
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VOO-VSSl
1.25 to 1.65
V
Topr
-20to 75
°c
DC CHARACTERISTICS
(VOO =OV, VSS 1, VEE = -1.55V, VSS 2 = -3.0V, VSS3 = -4.5V, CI = 30kll, Ta = 25°C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Power supply current
Oscillation start
voltage
3.0
-
/J- A
1.45
-
-
V
VOHl =-0.2V
-4
-
-
IOMHl VOMHl =VSS l ± 0.2
4/-4
-
-
IOMLl VOML 1 = VSS 2 ± 0.2
4/-4
-
-
VOLl =-4.3V
4
-
-
VOH2 =-0.2V
-
100
lOLl
-4
-
IOMH2 VOMH2 = VSS 1±0.2
4/-4
-
-
IOML2 VOML2 = VSS 2±0.2
4/-4
-
-
VOL2=-4.3V
4
-
-
IOH2
Output current 2
SEGMENT
-
VSS terminal
Within 5 seconds
-VOSC VSS l terminal
IOHl
Output current 1
COM
Typ. Max.
IOL2
Output current 3
AC2 LOAD XTOUT
IOH3
VOH3=-0.5 V
-10
-
IOL3
VOL3 = -1.15V
10
-
-
Output current 4
IOH4
VOH4 =-0.5V
-100
-
-
IOL4
VOL4=-1.0V
2
-
10
IOHs
VOHs = -0.55V
Ml-M4
Output current 5
LO
Output current 6
SO
122
IOLs
VOLs = -0.85V
IOHa
VOHa = -0.55V
lOLa
VOLe = -0.85V
VSS l =-1.25V
VEE =-2.0V
VSS 2 =-2.0V
VSS l =-1.25V
VEE =-2.0V
VSS 2 =-2.0V
-12.5 -25
/J- A
/J- A
/J- A
/J- A
-83
1
-
-
-17
-30
-62
-
5
-
/J- A
/J- A
--------------------------------------------------. MSM6051 •
Limits
Parameter
8ymbol
Conditions
Unit
Min.
Typ.
Max.
Input current 1
8,-8.
IIHI
VIH, =OV
2
20
IILI
VIL, =-1.55V
-
-
Input current 2
K,-K.
IIH2
VIH2=OV
5
13
26
IIL2
VIL2 = -1 .55V
-
-
-0.2
Input current 3
OPIN
IIH3
VIH3 =OV
45
VIL3 = -1.55V
-
30
IIL3
-
-0.2
-
20
-
Oscillator built-in
capacitance
CD
100
-0.2
p.A
p.A
p.A
pF
MEASURING CIRCUIT
VCP
VCM
C1.C2 .C3.C4 O.l/lF
C5
30 pF
X-tal
32.768 kHz
C4
XT
XT
VEE
C5
TYPICAL APPLICATION
C1
C2 toC5
LCD
B
L
5-35 pF
O.l/lF
1.5 V
20mH
Lamp
81 -'82 ........
83 -'84 -'-
COM1 to COM3
81
82
LD
83
BD
84
M8M6051
X-tal
I::J
XT
(CD=20 pF)
V88t
B
VDD
C1
123
• MSM6051 .----------------------------------------------------
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
c
ADD ACC, AP
0 0 0 0 0
ADD#D,AP
0
ADCAP
0 0 0 0 0
P 0
P
1 1 0 0
1 0 0
P
D
1 0
1
A
AP - (AP) + (ACC)
A
AP-(AP) +D
A
AP - Decimal adjust
(AP) +.(ACC) + (C)l
ADCNAP
1 1 0 0 0
A
AP - N adjust (AP) + (Cll
0 0 0 0 1 P 0 1 0 0
A
AP - (AP) - (ACC)
SUB#D,AP
0 1 1 0 1 P
A
AP-(AP) - D
A
AP - Decimal adjust
HAP) - (ACC) - (C)l
A
AP -N adjust (AP) - (C)l
A
(AP) - (ACC)
~ SBCAP
Qj
a.
0
SBCNAP
(.}
CMPACC,AP
;; CMP#D,AP
~
N
D
0 0 0 0 1 P 0 1 0
1 1 0 0
1 P
1 P 1 1 1 0
0
1 0
N
1 1 1 0 0 0 0
DECAP
1 1 1 0
1 P 0
1 0 0
DEC AX
1 1 1 0
o
0 0 0 0
XOR#D,AP
0
1 1 1 1 P
BIT ACC,AP
0 0 0
0
0
1 0 0 0
iXi BIC ACC, AP
0
o
0
1 0 0
BIC#D,AP
ROLAP
X
A
AX-(AX) + 1
0 0 0
A
AP - (AP)-1
P 0
X
A
AX-(AX)-1
1 1 1
A
AP - (AP) -V- (ACC)
D
0 0 P 1 1 1 0
BIT #D,AP
0
~ BISACC,AP
Qj
a.
0
BIS#D,AP
.::: RORAP
AP - (AP) + 1
P 0 0 0 0
XORACC,AP
1 0
0 0 0 0 0
0
(AP)-D
A
D
INCAX
1 0
A
1 1 P
1 1 1 0 0
-
1
0 0 0 0
INCAP
c
:c
en
"-
P 0
SUB ACC,AP
0
~
E
7 6 5 4 3 2 1 0
0
o
P
D
P 0
1 1 0
P
D
1 P 0
1 1 0
1 P
D
AP - (AP) -V- D
(AP) V (ACC)
A
(AP)VD
A
(AP) V (ACC)
A
(AP) V D
A
(AP) " (ACC)
A
(AP) " D
P 0 0
1 0
A
L... (C) - (AP)---.J
1 P 0 0
1 0
A
L(c) - (AP) ..-J
0 0 0 0 0 P 0 0
1 1
A
L.. (C) 0 - (AP)--.-J
0 0 0 0
1 P 0 0
1 1
A
(C) -(AP)-O
1 0
1 0
0 0 0
0 0 0 0
0
A
A
(])
«i ASRAP
'0
a: ASLAP
0
z-o
1 0 0 0 0
C-O
0 0 0 0 0 0 1 0 0 0 0 0 0 0
G-O
o
CLZ
0 0 0
c
CLC
0 0 0 0 0 0 1 0 0
~
Qj
a.
CLG
CLA
0 0 0 0 0
SEZ
0
SEC
0 0 0 0 1 0
0
0
Ol
as
u:::
124
o
0 0
0
0
o
0
o
0
1 0
1 1 0 0 0 0
Z -0, C -0, G-O
1 0
1 0
1 000 0 0
Z-1
1 0 0
1 0 0 0 0
C-1
----------------------------------------------------'. MSM6051 •
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Mnemonic
Operation
13121110 9
8
7
6
5
4
3
2
1 0
SEG
0
0
0
0
1 0
1 0
0
0
0
0
0
0
G-1
SEA
0
0
0
0
1 0
1 0
1
1 0
0
0
0
Z-1,C-1,G-1
MOVACC,AP
1
1
1
1 0
P 0
0
0
1
1
1
1 0
0
~
MOV#D,AP
0
1
1
1 0
P
'"
MOVAP,ACC
1
1
1
1
1 P 0
MOVAX,ACC
1
1
1
1
1 0
....
.S1
MOVACC,AX
u::'"
.,
c:
.0
"
~
.S
SEZ
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
(Z)-l
SEA
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
(Z), (C), (G)-l
1
" r, " r.
" " " '.
(rP) -(ACC)
1
(,Pb) - (ACC)
1
" " " '
" " " r.
(,P), (ACC), (Z) - i
1
(ACC), (Z) - (rP)
1
r,
(ACC), (Z) - (,Pb)
1
(rP) .. (ACC)
1
MOV ACC, REGl
0
0
0
0
0
0
P
1
1
1
1
MOVD ACC, REG2
1
0
1
0
b,
b.
0
P,
P,
P,
p.
MOV #i, REGl
0
0
1
1
1
0
P
i,
i,
i,
i.
MOV REG1, ACC
0
0
0
0
0
1
P
1
1
1
1
~
MOVD REG2, ACC
1
0
1
1
b,
b.
0
P,
P,
P,
p.
l!l
EXG
0
0
0
0
0
1
P
0
0
0
0
~
'"c:
't;
'"
REGl
Cl
'"c: c:
.~.S!
~
r.
(,Pb) .. (ACC)
EXGD
REG2
0
1
1
1
b,
b.
0
P,
P,
P,
p.
CALL
ad,s
1
1
1
a"
a,.
a.
a.
a,
a,
a,
a.
a,
a,
a,
a•
(STACK)
0
1
(PC), (PC) -a" - a. (SP) - (SP) + 1
1
"0 "~
"
RET
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
(PC) - (STACK) + 1
~.S
RTl
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
(PC) - (STACK) + 1
..,0
c:
JMP
1
1
0
a"
a,.
a.
a.
a,
a,
a,
a.
a,
a,
a,
a.
(PC) -a" - a.
1
"
JMP
a REGl
0
0
0
0
0
0
P
1
1
0
1
r,
" " '
(PC) - (PC) + (rP) + 1
1
JMPIO
a REGl
0
0
0
0
0
1
P
1
1
0
1
r,
r,
(PC) ... (PC) + 7 A (,P) + 1
1
~
.Q~
~
" "
" r, "
r,
" "
.
'.
'.
0."
E~
...," .-~
ad,s
r,
.
'.
~
(SP) - (SP) - 1
(SP) - (SP) - 1 (at INT routine)
1
1
•
i:
tn
i:
m
....
•
~
•
~
'"ex>
3:
en
3:
INSTRUCTION LIST (Continued)
Ma-
Instruction code
Description
Mnemonic
'£
~
"
c.
7
6
5
4
3
2
1
0
14
13
12
11
BGTn
0
0
0
0
1
1
P
0
0
1
n.
n,
n,
",
"0
BlE n
0
0
0
0
1
1
P
1
0
1
n,
n,
n,
n,
no
if (G) - 0 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
no
if (C) - 1 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
BCS n
"0
9
8
10
0
0
0
0
1
1
P
0
0
0
n,
n,
n,
n,
-.
cycle
if (G) - 1 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
1
1
1
BCC n
0
0
0
0
1
1
P
1
0
0
n.
n,
n,
n,
no
if (C) = 0 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
BEQ n (BZE n)
0
0
0
0
1
1
P
0
1
0
n,
n,
n,
n,
no
if (Z) - 1 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
no
if (Z) = 0 then (PC) ~ (PC) + N
else (PC) ~ (PC) + 1
no
if [(G) - 1 or (Z) -1] then (PC)
else (PC) - (PC) + 1
~
(PC) + N
~
(PC) + N
E
::>
chine
BNE n (BNZ n)
BGE n
BlT n
Melody
MSA adrs'
start
0
0
0
0
0
0
0
0
1
1
1
1
P
P
1
0
1
1
0
1
n,
n.
n,
n,
n,
n,
n,
n,
When P = 0
in bit 8,
N = n + 1;
when P = 1,
N =-n
0
0
0
0
1
1
P
1
1
1
n,
n,
n,
n,
no
0
0
0
0
1
0
a,
a,
a,
a,
a,
a,
a,
a,
ao
Specifies the first address of note data. (EOOH - FFFH)
1
1
2
DSP dig, REG1'
0
0
0
1
0
0
P
dig, dig, dig, dig,
r,
r,
r,
ro
digit (lower Part)
"0
DSPH dig, REG1'
0
0
0
1
0
1
P
dig, dig, dig, dig o r,
r,
r,
r,
digit (High Part)
~
(rP), (ACC)
1
~~
DSPF dig, REG1'
0
0
0
1
1
0
P
dig, dig, dig, dig o
r,
r,
r,
r0
digit (low Part)
~
(rP) via Table
2
DSPFH dig, REG1'
0
0
0
1
1
1
P
dig, dig, dig, dig,
r,
r,
r,
r0
digit (High Part)
~
(rP) via Table
2
OUT REG1, PORT
0
1
0
1
0
Y4
P
Y,
Y,
y,
Yo
r,
r,
r,
r0
(PORT y)
~
-~"
~::> ::>
OUT #i, PORT
0
1
0
1
1
y.
0
V,
y,
y,
Vo
i,
i,
i,
i,
(PaRTy)
~i
c:::> c:
INP PORT, REG1
0
1
0
0
0
V,
P
y,
V,
V,
Yo
r,
r,
r,
r,
(rP), (ACC)
Nap
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
1
HALT
0
0
0
0
0
1
0
0
1
1
1
I0
0
0
0
Halt CPU
1
~B
(5.!::
.,"
.0
5.9-~
-
0·-
(rP), (ACC)
1
1
if [(G) - 0 or (Z) 0] then (PC)
else (PC) ~ (PC) + 1
~
1
(rP)
~
1
1
1
(PORT V)
1
~
"-
u
Note: Instructions marked with an asterisk (.) are available for MSM6351 onlv.
Page
;...
•
OKI
semiconductor
MSM6052
CMOS 4BIT SINGLE CHIP LOW POWER MICROCONTROLLER FOR
TELEPHONE
GENERAL DESCRIPTION
The OKI MSM6052 is low-power, high-performance single-chip 4-bit microcontroller employing
complementary metal oxide semiconductor technology, especially designed for use in sophisticated
telephone sets. Integrated onto a single chip are 4 bits of ALU, 28K bits of mask programmable ROM,
2560 bits of data RAM, programmable timer, oscillator, 12-bits of input port, 12-bits of output port and
4-bits of input/output port. In addition to these units, a DTMF generator is provided.
With the MSM6052, sophisticated telephone sets become feasible through a single chip instead
of the conventional 3-chip configuration.
FEATURES
•
•
•
•
•
•
•
•
•
Low Power Consumption 0.3mA Typical @3V
(DTMF output off)
2048 x 14 Internal ROM
640 x 4 Internal RAM
3 x 4 Input Port
3 x 4 Output Port
1 x 4 Input/Output Port
DTMF Generator
Buzzer Sound Output
4-Bit Programmable Timer Applicable for
Output of Dial Pulse
• Interrupt by Progammable Timer
• 5 Level Stack
• Power Down Mode
• 52 Instructions
• Instructions Useful for Data Management
(Data Search and Block Data Transfer)
• 2.5 to 6.0V Operating Voltage
• 3.58 MHz Oscillator
• 17.9 P.s Instruction Cycle
• -20 to 75°C Operating Temperature
• 28 Pin DIP or 40 Pin DIP
FUNCTIONAL BLOCK DIAGRAM
DPOUT
DTMFOUT
BD
Ii==~~===~l=;>I D,N
DATA RAM
640 word x 4 bit
DOUT
11
12
PROGRAMMABLE
DTMF
TIMER
CIRCUIT
13
14
C1
C2
C3
'C4
01
02
03
04
E01
E02
E03
E04
101
102
103
104
10E
INSTRUCTION
DECODER
He ---'r-l"----'
PROGRAM ROM
2048 word x 1 4 bit
XT
XI
32kHz
TIMING
GENERATOR
!1 ! 1
AC TEST
"DO Vss
,
~-----------------
139
• MSM6052 ••----------------------------------------------------
PIN CONFIGURATION
EO'
C,
C,
C,
C,
I,
0,
R,
0,
R,
R,
HS
I,
I,
0,
0,
0,
NC
0,
OP OUT
DTMF OUT
I,
NC
I,
10,
10,
10,
R,
R,
R,
DTMF OUT
10,
10,
io
3
10,
VDD
BD
AC
DC; Don't connect.
(a) 40 Lead Plastic 01 P
(c) 44 Lead Plastic Flat Package
(NC pin must not be connected to any signal.)
(b) 28 Lead Plastic DIP
LOGIC SYMBOL
KEYBOARD [
INPUT
E01
E02
E03
E03
KEYBOARD [
INPUT
101
102
103
104
10E
INPUT PORT [
11
12
13
14
KEYBOARD [
OUTPUT
C1
C2
C3
C4
OUTPUT [
PORT
01
02
03
04
DPOUT
DTMFOUT
BD
32kHz
] OUTPUT PORT
] 10PORT
OUTPUT ENABLE
DIALPUSLE
OUTPUT
DTMFOUTPUT
BUZZER OUTPUT
32kHz OUTPUT
RESET
HOOK SWITCH
OSCILLATION (
140
TEST
) POWER
----------------------------------------------------. MSM6052 •
PIN DESCRIPTION
Designation
Function
VDD
Power source
VSS
Circuit ground potential
AC
Terminal to clear internal logic, pulled down to VSS.
After power is turned on, the MSM6052 must be reset by this terminal.
TEST
Terminal to test internal logic, pulled down to VSS.
This terminal must be open in normal operation.
XT,XT
Input and output terminals of oscillator inverter.
3.58 MHz ceramic resonator is connected to these terminals.
HS
Input terminal connected to the hook switch, pulled up tp VDD.
DPOUT
Output terminal of dial pulse.
Dial pulse rate (10 pps or 20 pps) and Make Break ratio (40% or 33 %) can
be selected by software.
DTMFOUT
Output terminal of DTMF signal
BD
Output terminal of buzzer sound
32 kHz
Output terminal of 32 kHz clock
R,-R.
Rs-Rs
Input port pulled down to VSS.
1,-1.
Input port having clocked pull-down resistor to VSS.
Only when this port is accessed, pull-down resistors are connected to this
port.
C,-C,
0,-0.
Output port
10,-10.
Tri-state bidirectional port
10E
Output terminal
When 10, -10. is accessed, input completion signal (when read) or
load signal (when written) is output from 10E terminal.
141
• MSM6052 .'--------------------------------------------------
FUNCTIONAL DESCRIPTION
A block diagram of the MSM6052 is given on
page 129. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM6052 user's manual.
Program ROM
The MSM6052 will address up to 2 K words
of internal mask programmable ROM. Each word
consists of 14-bits and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Port (11 - 14)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal resistor and
'transistor. Only when it is desired to fetch status
of the port, input current flows through these
pins. Status of the port is fetched by an input
instruction.
•
Output Port
Port (C1 - C4)
4-bit output port. These ports consist of data
latches and buffers, and the contents of the data
latches are rewritten by an output instruction.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 640 nibbles.
All locations are addressed by 10-bit
address registers (AR 1, AR,j, 2-bit bank register
(B), 4-bit page register (P) or a part of the
instruction's operand.
Port (01 - 04)
4-bit output port. This port consists of data
latches and buffers, and the contents of the data
latches are rewritten by an output instruction.
Electrical characteristics of 03 and 04 are
different from those of 01 and 02. 03 and 04 of
the ports are used as XMIT MUTE and MUTE
normally.
ALU
The ALU performs a 4-bit parallel operation
on RAM and ACC contents, or on RAM contents
and an immediate digit. It sets or resets the three
flags (Z, C, G) depending on the condition.
Port (E01 - E04)
4-bit output port. This port consists of data
latches and buffers, and the contents of data
latches are rewritten by an output instruction.
Program Counter (PC)
The program counter is an 11-bit wide
counter that specifies the address of program
ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of a Jump, Call or Branch instruction.
As there is no boundary in the ROM, and a
Jump, Call or Branch instruction can be put
anywhere in the ROM.
Stack
The MSM6052 has a 5 level stack apart from
the data RAM. The contents of the PC are loaded
into stack when a Call instruction is executed or
an interrupt is generated. Nesting of subroutines
within subroutines can continue up to 4 times,
including the interrupt.
•
Input Port
Port (R1 - R4)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal resistor, and status
of the port is fetched by an input instruction.
Port (R5 - R8)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal resistor, and the
status of the port is fetched by an input
instruction.
142
•
Input/Output Port
Port (101 - 104)
4-bit bidirectional port. This port consists of
data latches, output buffers and input buffers.
The contents of the data latches are rewritten by
an output instruction, and status of the port is
fetched by an input instruction.
Address Registers (AR1, AR2)
The address registers are used to specify the
1O-bit address of data RAM, when a data search
instruction (ROAR) or block data transfer
instruction (MVAR) is executed.
This register is an up/down counter, and is
incremented or decremented by 1 with
execution of the instruction.
Timing Generator
By connecting a 3.58 MHz ceramic resonator
to the XT and XT terminal, the timing generator
generates a basic timing signal to control the
MSM6052 .
The MSM6052 can operate in 2 modes,
normal operating mode and power down mode.
STOP instruction is used to place the MSM6052
in the ;Jower down mode. The oscillation stops
and all functions are stopped. However, the
contents of RAM and all registers are maintained.
____________________________________________________1. MSM6052 •
Programmable Timer
The programmable timer consists of a 4-bit
down counter and a 1/100 prescaler.
Any of a 7990.1 Hz clock, 1997.5 Hz clock
and 998.8 Hz clock is input to the 1/100
prescaler. Output of the 1/100 prescaler
decrements the 4-bit down counter by 1 .
When the contents of the 4-bit down counter
is decremented to 0, the programmable timer
generates an interrupt.
This programmable timer can be used as a
dial pulse generator. The dial pulse rate (10 pps,
20 pps) and Make/Break ratio (40%, 33%) of the
dial pulse which the programmable timer
generates are selectable.
DTMF Circuit
OTMF circuit is used to generate a OTMF
signal. 12 kinds of OTMF signal (0 to 9, #, *) can
be output by an output instruction.
BD Circuit
The BO circuit generates the square wave
which can be used as the confirmation sound,
warning sound and so on. 15 kinds of sound
(4.66 to 0.82 kHz) are output by an output
instruction specifying the frequency.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VOO
Ta =25°C
-0.3 to 7.0
V
Supply Voltage
VI
Ta = 25°C
-0.3 to VOO+0.3
V
Output Voltage
Vo
Ta = 25°C
-0.3 to VOO+0.3
V
Storage Temperature
Tstg
-
-55 to 125
°C
Po
Ta=25°C
200
mW
Input Voltage
Power Dissipation
OPERATING CONDITIONS
Parameter
Operating Voltage
Memory Retension
Voltage
Symbol
Limits
Unit
VOO
2.5 to 6.0
V
1.2 to 6.0
V
-20 to 75
°C
VOOM
Operating Temperature
Topr
DC CHARACTERISTICS
(VOO = 3V, Ta = -20 to 75°C)
Limits
Parameter
"H" Input Voltage
Symbol
VIH
"L" Input Voltage
VIL
"H" Output Current (1)
10H,
"L" Output Current (1)
10L,
Unit
Conditions
Min.
Typ.
Max.
VOO=3V
2.2
-
-
V
VOO=6V
4.4
-
V
VOO=3V
-
0.8
V
-
-
1.6
V
VOH=2.6V
-200
-
-
p.A
VOL=0.4V
500
p.A
-1
-
-
VOH=2.6V
-
mA
VOO=6V
03,04
OPOUT
"H" Output Current (2)
IOH2
"L" Output Current (2)
IOL2
VOL=0.4V
10
-
-
p.A
"H" Output Current (3)
IOH3
VOH=2.6V
-20
-
-
p.A
"L" Output Current (3)
IOL3
VOL=0.4V
10
-
-
p.A
C,-C4
0,,02, BO
143
• MSM6052 .----------------------------------------------------
DC CHARACTERISTICS (CONT.)
Limits
Parameter
Symbol
"H" Output Current (4)
10H.
"L" Output Current (4)
10L.
"H" Output Current (5)
IOH5
"L" Output Current (5)
IOL5
Pull-up Resistance
RUp
Conditions
10,- 10.
10E
EO , -EO.
Typ.
Max.
-150
-
-
/LA
VOL=O.4V
300
-
-
/LA
VOH=2.6V
-40
-
-
/LA
VOL=O.4V
25
-
-
/LA
17
-
150
kf!
-
300
kf!
100
kf!
VOH=2.6V
32 kHz
Unit
Min.
HS
Pull down
Resistance (1)
Rdwon 1
R,-Rs
33
Pull down
Resistance (2)
Rdwon 2
I, -I., AC, TEST
10
Input Leak Current
IlL
o ::S:VIN ::S:VOO
10,-10.
-
-
±2
/LA
0.3
0.6
mA
1.2
2.4
mA
1.2
2.4
mA
VOO= 2.5 to 6.0V
Current
Consumption (1)
lOOp
Current
Consumption (2)
lOOT
Memory retention
Current
100M
OTMF output
off
VOO=3V
VOO=6V
-
OTMFoutput
on
VOO=3V
-
VOO=6V
-
3.5
7.0
mA
ON HOOK
VOO=2.5V
Ta=25°C
-
0.01
0.2
/LA
Ta=-20to75°C
-
-
2
/LA
AC CHARACTERISTICS
(VOO = 3V, Ta = -20 to 75°C)
Limits
Parameter
Key Input Time
Tone Output Voltage
Symbol
TKIN
VOUT
Conditions
Typ.
Max.
33
-
-
VOO=2.5V
150
250
350
VOO=4.0V
200
350
570
VOO=6.0V
300
480
850
mV
rms
VOO=2.5 to 6.0V
Row only
RL =1 kf!
Unit
Min.
ms
High/Low Level Ratio
dBCR
VOO=2.5 to 6.0V
1
2
3
dB
Oistortion Ratio
%OIS
RL=l kf!
-
1
5
%
Os, 0., OP OUT
CL=50 pF
-
-
0.5
-
-
0.5
C,-C.
CL=50 pF
-
-
0.5
-
-
10
0,,02, BO, 32 kHz
CL=50 pF
-
-
5
-
-
10
10,-10.,IOE, EO, - EO.
CL=50 pF
-
-
1
-
-
1
Rise/Fall Time (1)
tTLHl
tTHLl
Rise/Fall Time (2)
tTLH2
tTHL2
Rise/Fall Time (3)
tTLHs
tTHL3
Rise/Fall Time (4)
tTLH.
tTHL.
144
/LS
/LS
/LS
/LS
----------------------------------------------------. MSM6052 •
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
7 6
5 4 3 2 11
a
a a
CLA
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
MOVACC,AP
1 1 1
ADD ACC,AP
ADD#D,AP
u
06>
ADCAP
.Q
SUB ACC, AP
"0
c::
to
SUB #D,AP
U
~ SBCAP
E
:5 CMPACC,AP
~ CMP#D,AP
XOR ACC, AP
XOR#D,AP
BITACC,AP
c::
BIT #D,AP
~
BISACC,AP
0
~
Co
0
BIS#D,AP
iii BIC ACC, AP
BIC#D,AP
RORAP
Q)
~
ROLAP
"0 ASRAP
a:
ASLAP
SEZ
CLZ
c::
SEC
~
CLC
Co
SEG
09
~
0
01
to
u:
Operation
1312 11 110 1 9 1 8
CLG
SEA
a a a
1 1 a
a a a
a a a
1 1 a
a a a
a a a
1 a 1
a a a
a
a
a
P
P
P
1 P
a
A
AP +- (AP) - ACC
A
AP +-(AP) - D
1
A
AP +-(AP) - ACC - C
a
A
(AP) -ACC
1 P
a
P
a a
1 a
a a
a a
a 1
a 1
a a
a 1
a a
a 1
a 1
a a
a 1
a a
a 1
a a
a 1
a a
1 a
1 a
1 a
1
A
(AP) -D
A
AP +- (AP) ""V ACC
A
AP +-(AP)""VD
a
A
(AP) VACC
A
(AP)VD
a
A
AP +- (AP)
A
AP+-(AP) V D
a
A
AP +- (AP) A ACC
A
AP+- (AP) AD
a
a
A
C(AP)-C:::J
A
L (AP) +- C-.J
1 1
A
O-(AP)-C
1
1
A
1
a a a a
a a a a
1 a a a
1 a a a
a a a a
a a a a
1 a a a
1 a a a
A
a
D
a
1 1 1
D
P 1 1 1
P
P
D
a
1 1
a
1 1
P
P
D
P
P
P
P
P
a
a
a
a
a
a
a
a
1
D
a
a
a
a
a
a
a
a
1 a
1 a
1 a
1 a
1 a
1 a
1 a
1 a
a a
1
1
1
a
a
a
a
1
1
a
x
a
MOVACC,AX
1 1 1
a
to
MOVAP,ACC
1 1 1 1 1 1
MOVAX,ACC
1 1
CHGAP
1 1 1
~
Cl
D
a
MOV#D,AP
1 1
1
A
A
a 1
a a
1
+ ACC
AP+-(AP) + D
AP +- (AP) + ACC + C
AP +- (AP)
A
1 P 1 1 1
1 P
~
~
a
a
1 P
c::
'iii
D
1 1 1 1 P
a a
1 a
a a
1 a
a a
1 a
a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
a a
1
a
P
1 1 1
a
a a
1
v ACC
C +-(AP) +-0
a
a
a
a
a
a
a
a
Z +-1
Z+-O
C+-1
C+-O
G +-1
G +-0
Z +- 1 , C +- 1 , G +-1
Z +-0, C +-0, G +-0
AP +-ACC
A
AX +-ACC
D
A
AP+-D
a a a a
A
ACC +-(AP)
A
ACC +-(AX)
A
(AP)-ACC
X
a a a a
145
• MSM6052 .---------------------------------------------------
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Mnemonic
Operation
1312 11 10 9 8
Qi
Ui
<::
7
6 5 4 3 2 1 0
CHGAX
1 1 1 0 0 0
ROAR
1 1 0 0 0 0 0
0 0 0 0 0 0 0
ROAR+H
1 1 0 0 0 0 0
0
X
ROAR+H,Z
1 1 0 0 0 0 0
ROAR+H,N
1 1 0 0 0 0
(AX)--ACC
A
1 Oil 0 0 0 0
ACC - (AR 1), AR 1- AR 1±1
1 00/10 0 0 0
ACC-(AR,)
if (AR 1)=0 then PC - PC + 1
else AR 1- AR 1±1, repeat
o Oil
0 0 0 0
1
o Oil
0 0 0 0
1 0
o Oil
0 0 0 0
1 0
ROAR+H,Z,L 1 1 0 0
1 0 0
ROAR+H,N,L 1 1 0 0
1 0
MVAR
1 1 0
1 0 0 0 0 0 0 0 0
MVAR + (-)
1 1 0
1 0 0 0
0
1 Oil 0 0 0 0
MVAR+H,Z
1 1 0
1 0 0 0
1
o Oil
0 0 0 0
MVAR+H,N
1 1 0
1 0 0
1 0
o Oil
0 0 0 0
MVAR + H, L
1 1 0
1 1 0 0 0
o Oil
0 0 0 0
~
0 0
ca
iii
Cl
MVAR +H,Z, L 1 1 0
MVAR +H,N,L 1 1 0
1 1 0 0
1 1 0
1
1 0
o Oil
c:
:s
e
.c
:::l
(/)
146
CALL adrs
1 0
RET
0 0 0 0 0
RTI
0 0 0 0
ACC-(AR,)
if (AR 1)fO then PC - PC + 1
else AR1 - AR1 ±1, repeat
ACC - (AR 1), L - L - 1
if (AR 1)=0 or L=O
then PC- PC+1
else AR1 -AR, ±1, repeat
ACC - (AR 1), L - L - 1
if (AR 1) fO or L=O
then PC - PC + 1
else AR 1- AR 1±1, repeat
AR2-(AR,)
AR2-(AR,),
AR,-AR, ±1, AR2-AR2 ±1
AR2-(AR,),
if (AR 1)=0 then PC - PC +1
else AR1 -AR,±1,
AR2 - AR2± 1, repeat
AR2-(AR,)
if (AR 1)'1'0 then PC - PC +1
else AR1 -AR, ± 1,
AR2 - AR2±1, repeat
AR2-(AR,),L-L-1
if L=O then PC - PC +1
else AR 1- AR 1± 1 ,
AR2-AR2±1, repeat
0 0 0 0
AR2- (AR,), L -L-1
if (AR,)=O or L=O
then PC - PC +1
else AR 1- AR 1± 1 ,
AR2 - AR2±1, repeat
0 0 0 0
AR2-(AR,), L -L-1
if (AR 1)10 or L=O
then PC - PC +1
else AR,-AR, ± 1,
AR2 - AR2 ±1, repeat
o Oil
!
Q)
ACC-(AR,)
1 a '0 a g as a 7 as as a. a 3 a 2 a , ao
STACK - (PC), PC - adrs
0
1
1 0 0 0 0 0 0
PC - (STACK) + 1
1 0
1
1 0 0 0 0 0 0
PC - (STACK) or
PC -(STACK) +1
----------------------------------------------------e. MSM6052
•
DESCRIPTION OF INSTRUCTIONS (CONT.)
I nstruction Code
Mnemonic
Operation
1312 11 10 9 8
0.
E
....,:::l
o a,o a
JMP adrs
1 0
JMP@AP
0 0 0 0 0
JMPIO @AP
0 0 0 0
9
7 6
5 4
3
2 1 0
a 8 a 7 a 6 as a. a 3 a 2 a, a o PC
P 1 1 0 1
1 P 1
1 0
A
1
A
~adrs
PC
~
(PC) + (AP) + 1
PC
~
(PC) + ((AP) A 7H} +1
BEan
(BZE n)
1 1 1 0
1 P 0
BNEn
(BNZ n)
1 1 1 0
1 P 1 1
o
n. n3 n 2 n, no
if Z=O then PC~PC - n or
PC~PC +n + 1
else PC ~ PC +1
BCSn
1 1 1 0
1 P 0
0
o
n. n3 n 2 n, no
if C=1 then PC ~ PC -n or
PC ~PC +n + 1
else PC ~ PC +1
BCCn
1 1 1 0
1 P 1
0
o
n. n3 n 2 n, no
1 0 n. n3 n 2 n, no
if Z=1 then PC~PC - n or
PC~PC + n +1
else ~ PC ~ PC + 1
if C=O then PC
.r=
else PC
0
<::
PC - n or
~
PC +1
BGTn
1 1 1 0
1 P 0
0
1 n. n3 n 2 n, no
if G=1 then PC ~ PC - nor
PC ~PC +n + 1
else PC ~ PC +1
BLEn
1 1 1 0
1 P 1 0
1 n. n3 n 2 n, no
if G=O then PC ~ PC - n or
PC ~PC +n+1
else PC ~ PC +1
BGEn
1 1 1 0
1 P 0
03
ro
~
PC~PC+n+1
1 1 n. n3 n 2 n, no
ifG=1 or Z=1
then PC ~ PC - n or
PC~PC+n+1,
else PC
BLT n
1 1 1 0
IN PORT,AP
0
0 0 1 0
OUTAP, PORT
0
0
1
-0 OUT #0, PORT
0
0
-
':::l
"So.
0.<:::::l
1 P 1 1 1 n. n3 n 2 n, no
~
PC +1
if G=O and Z=O
then PC ~ PC -n or
PC ~PC+n+1
else PC ~ PC+1
P
PL
A
AP~(PORT)
PH P
PL
A
PORT~(AP)
1 1 PH 0
PL
D
PORT~D
o
STOP
0 0
1 1
0 0
0
rn
.r=
HALT
0 0
1 1 1 0
0
0
0
1 0
ACT
0
0
1 1 1 0
0
0
1 0
"0
<::
EI
0 0
1 1 1 0
0
1 1 0
e"E
DI
0
1 1
1 0
0
0
ET
0 0
1 1 1 0
0
::::>
DT
0 0
1 1 1 0 0
1 1 010 0 0
1
Disable timer activate
()
EC
0
0
1 1 1 0
0
1 1 1 1 0
0
Enable output port (C,-C.)
DC
0 0
1 1 1 0
0
1 1 1 0
CD
"0
03
0
1 0 0
0
0
Stop system clock
0 0
0
HaltCPU
0 0
0
0 0 0
1 0
Activate CPU
0 0
Enable timer interrupt
1 1 0 0
1 0 0
Disable timer interrupt
1 1 0
0
0
1 0
Enable timer activate
0
a..
0
1 0 0
Disable output port (C ,-C.)
147
• MSM6052·'-------------------------------------------------DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Mnemonic
Operation
1312 11 10 9 8
OM
7 6 5
4
3 2 1 lJ
1 0
Set I/O port (101-104) to
output mode
1 1 1 0 0 0 1
Set 1/0 port (101-104) to
input mode
0 0
1 1 1 0
0 0
1 1 1 0 0
RST
0 0
1 1 1 0
1 0 0 0 0
Reset divider
NOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0
No operation
0
1 1 1 0 0
Om
~CD
o..c: 1M
0'0
=>"0
Doc:
0'"
148
1 0 0
OKI
semiconductor
MSM6352
CMOS 4BIT SINGLE CHIP LOW POWER MICROCONTROLLER FOR
TELEPHONE
GENERAL DESCRIPTION
The OKI MSM6352 is a low-power, high-performance single-chip 4-bit microcontroller employing
complementary metal oxide semiconductor technology, especially designed for use in sophisticated
telephone sets. Integrated onto a single chip are a 4-bit ALU, 28K bits of mask programmable ROM,
2560 bits of data RAM, programmable timer, oscillator, 12-bits of input port,12-bits of output port and
4-bits of input/output port. In addition to these units, a DTMF generator is provided.
With the MSM6352, sophisticated telephone sets become feasible through a single chip instead
FEATURES
•
Low Power Consumption 1.8mA Typical @3V
(DTMF output off)
• 2048 x 14 Internal ROM
• 640 x 4 Internal RAM
• 3 x 4 Input Port
• 3 x 4 Output Port
• 1 x 4 Input/Output Port
• DTMF Generator (Single Tone Mode or Dual
Tone Mode)
• Buzzer Sound Output
• 4 Bits Programmable Timer Applicable for
Output of Dial Pulse
• Watch Dog Timer
• On Hook Dialing and Off Hook Dialing
Function
•
Interrupt
Programmable Timer-Interrupt
Real Time Interrupt
• 5 Level Stack
• Power Down Mode
• 52 Instruction Set
• Instructions Useful for Data Management
(Data Search and Block Data Transfer)
• 2.0 to S.SV (2.2 to S.SV at TONE MODE)
Operating Voltage
• Low Voltage Detector
• 3.58 MHz Oscillator
• 17.9 fis Instruction Cycle
• -20 to 75°C Operating Temperature
• 28 Pin DIP, 40 Pin DIP or 44 Pin FLAT
• Software Compatibility with MSM6052
FUNCTIONAL BLOCK DIAGRAM
A.
A2
A3
A.
DATA RAM
640 w()(dll4 bit
A5
~,
H.
"
12·
"'1
§~
-(.;4
8~
03
U.
EO.
E02
~8~
...0. I§~
10e
INSTRUCTION
Hs ---(:=J-------,-j
DECOOER
PROGRAM ROM
2046 word x 14 bit
XT
Xi'
32kHz
TIMING
GENERATOR
II II
AC TE~T
"DO Vss
~===;=_=_=_=
__=_=_=_=__=_=_=_=__=_~_J
149
• MSM6352 • - - - - - - - - - - - - - - - - - - - - - - - - -
PIN CONFIGURATION
E01
C,
C,
C,
C,
I,
C,
0,
R,
C,
DTMF OUT
I,
0,
R.
0,
I,
I,
1
10,
0,
DPOUT
DTMF OUT
10,
10,
10,
NC
DPOUT
3
NC
R,
HS
10,
io
I,
0,
0,
0,
R,
R,
R,
C,
C,
I,
DTMF OUT
VDD
VDD
BD
AC
VSS
DC: Don't connect.
(a) 40 Lead Plastic DIP
(c) 44 Lead Plastic Flat Package
(NC pin must not be connected to any signal.)
(b) 28 Lead Plastic DIP
LOGIC SYMBOL
KEYBOARD [
INPUT
E01
E02
E03
E03
KEYBOARD [
INPUT
101
102
103
104
10E
INPUT PORT [
11
12
13
14
KEYBOARD [
OUTPUT
C1
C2
C3
C4
OUTPUT [
PORT
01
02
03
04
DPOUT
DTMFOUT
BD
32kHz
AC
HOOK SWITCH
OSCILLATION (
150
HS
XT
XT
] OUTPUT PORT
]
10PORT
OUTPUT ENABLE
DIAL PUSLE
OUTPUT
DTMFOUTPUT
BUZZER OUTPUT
32kHz OUTPUT
RESET
TEST
TEST
VDD
VSS
) POWER
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6352 •
PIN DESCRIPTION
Designation
Function
VDD
Pource source
VSS
Circuit ground potential
AC
Terminal to clear internal logic, pulled down to VSS.
After power is turned on, the MSM6052 must be reset by this terminal.
TEST
Terminal to test internal logic, pulled down to VSS.
This terminal must be open in normal operation.
XT,XT
Input and output terminals of oscillator inverter.
3.58 MHz ceramic resonator is connected to these terminals.
HS
Input terminal connected to the hook.switch, pulled up tp VDD.
DPOUT
Output terminal of dial pulse.
Dial pulse rate (10 pps.or 20 pps) and Make Break ratio (40% or 33 %) can
be selected by software.
DTMFOUT
Output terminal of DTMF signal
BD
Output terminal of buzzer sound
32 kHz
Output terminal of 32 kHz clock
R,-R4
R5-R8
Input port pulled down to VSS.
1,-14
Input port having clocked pull-down resistor to Vss.
Only when this port is accessed, pull-down resistors are connected to this
port.
C,-C4
0,-04
Output port
10,-104
Tri-state bidirectional port
10E
Output terminal
When 10, - 104 is accessed, input completion signal (when read) or
load signal (when written) is output from 10E terminal.
151
·MS~2·-------------------------------------------------------
FUNCTIONAL DESCRIPTION
A block diagram of the MSM6352 is given on
page 149. Each block of logic will be briefly discussed. For more information, please refer to the
MSM6352 user's manual.
Program ROM
The MSM6352 will address up to 1 K words
of internal mask programmable ROM. Each word
consists of 14-bits and all instructions are one
word. The instructions are routed to a programmed
logic array wh ich generales the signals necessary for
control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal data
RAM consists of 640 nibbles.
All locations are addressed by 10-bit address
registers (AR" AR.), 2-bit bank register (B),
4-bit page register (P) or a part of the instruction's
operand.
Program Countar (PC)
The PC is an 11-bit counter to specify the
ROM's address. The PC is normally incremented
by one by every execution of the instruction, and
then specifies the next instruction to be executed.
However, Jump, Conditional branch, and Subroutine instructions are exceptions.
When the JMP adrs or CALL adrs instruction
is executed, all of the PC contents are rewritten,
so jump can be done to any address of the ROM.
Bank Register (B)
The ban k register is a 2 bits register which
specifies the bank of the RAM. Read/Write operation is performed by the Input/Output instruction.
Page Register (P)
The page register is a 4 bits register which
specifies the page of the RAM. Read/Write operation is performed by the Input/Output instruction.
Address Register 1 (AR,)
The address register AR, is a 10 bits register
which specifies the RAM's address. This register is
used by the R DAR instruction or the MV AR
instruction. Read/Write operation is performed by
the Input/Output instruction.
Address Register 2 (AR. )
The address register AR. is a 10 bits register
which specifies the RAM's address. This register is
Llsed by the MVAR instruction. Read/Write operation is performed by the Input/Output instruction.
Loop Counter (L)
The loop counter is a 10 bits down counter
which specifies a number of words of the data
to be searched or to be moved by the RDAR
instruction or the MVAR instruction. Its contents
can be rewritten by the output instruction.
152
ALU, Conditional Flag, ACC
(a) ALU
The ALU performs 4-bits parallel operation of
the RAM contents and ACC contents, or the
RAM contents and an immediate data. The
arithmetic, logic, comparison and rotate operations can be done.
(b) Conditional flag
The zero flag (Z), carry flag (C) and greater
flag (G) are provided. These flags are set or
reset depending on the operation result and
referred to by the conditional branch instruction.
The flag operation instruction enables these
flags to be set or reset individually or allogether.
(c) ACC
The ACC is 4-bits register for arithmetic, and
equipped with data transfer instruction between ACC and RAM.
Steck
The stack consists of a RAM of 5 words x 11
bits. It is used to save the PC contents when the
sub-routine is called or a timer interrupt is generated, and 5-level nesting can be done including a
timer interrupt. The PC contents saved in the stack
is popped to the PC by the RETURN instruction.
Interrupt
MSM6352 has two kinds of interrupt as below.
• Realtime interrupt
• Programmabletimer interrupt
Stop Mode
Stop mode is established by the execution of
the STOP instruction. In the stop mode, oscillation
of system clock stops and all operations are suspended, but the RAM contents and all register
contents are maintained.
Halt Mode
Halt mode is established by the execution of
the HALT instruction and the execution of program of main routine is suspended. In the halt
mode, all RAM contents and register contents are
maintained.
Timer Activation and Realtime Interrupt Circuit
The timer activation and realtime interrupt
circuit are to release HALT mode (timer activiation) and to generate interrupt (Realtime interrupt) at the tailing edge of the 31.21 Hz clock
obtained by dividing the 3.579545 MHz system
clock by 114688. The timer activ/ltion and realtime interrupt circuit can be used for the generation of timer activation and realtime interrupt by
setting or resetting the mode setting flag (TMF).
- - - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6352 •
Divider Circuit
The 3 stage binary divider circuit to which
31.21 Hz clock is supplied is provided. The divider
circuit's contents can be read by the input instruction (lN2, AP), and at the same time HS input
port data is also read. The divider circuit can be
reset by the RST instruction.
Programmable Timer and Programmable Timer
Interrupt
The programmable timer is used for dial pulse
output or timer interrupt generation. This timer
consists of control resistor PTL, 1/100 divider
circuit, 4 bit presettable down counter PTC,
interrupt flag IRQF, interrupt enable flag ElF,
selection flag EOF of off and on-hook dialing
made, and dial pulse phase selection flag DPE,
1/100 divider circuit, PTC, IRQF, ElF, EOF and
DPF are reset at system reset.
DTMF Output Circuit
The DTMF output circuit is to generate DTMF
tone signal and is controlled by DTMF and TONE
register. Rewriti ng the contents of the output latch
for DTM F circuit by output instructions, 12 kinds
of dual or single tones can be output to the DTMF
output port. The tone output frequency is selected
by the DTMF register.
BD Circuit
The BD circuit generates the square wave which
can be used as the confirmation sound, warning
sound and so on. 15 kinds of sound (4.66 to 0.82
kHz) are output by an output instruction specifyi ng the frequency.
Watchdog Timer WDT
The watchdog timer is to generate the system
reset signal to recover from system ran away
trouble.
Input Port (R, - R.)
R, - R. is 4-bits input port, which status is
fetched by the input instruction. The port is pulled
down to the low level (Vss) by resistor, so it can
be used as keyboard input port.
Input (Rs - R.)
R s - R. is 4-bits input port, which status is
fetched by the input instruction. The port is pulled
down to the low level (Vss) by resistor, so it can
be used as keyboard input port.
Input Port (I, - I.)
I, - I. is 4-bits input port, which status can be
fetched by the input instruction. It is pulled down
to low level (Vss) by register via transistor only
when it is desired to fetch the port status or input
signal is low level.
As input current is restricted, it can be used
being fixed at high level (Voo).
HS Input Pin
It is one bit input pin, which status can be
fetched by the input instruction. It is pulled up to
high level (Voo) by resistor. It is used as a hook
switch input pin.
Output Port (C, - C. )
C, - C. is 4-bits output port. The contents of
the output latch can be rewritten by the output
instruction. The low level is output at each output
pin after the system is reset. When the HS input
pin is open or at high level, the low level is output
to each output pin irrespective of the contents of
the output latch.
The outputs of C, - C. are all CMOS output.
Output Port (0, - 0.)
0, - O. is 4-bit output port. The contents of
the output latch can be rewritten by the output
instruction.
Output latch of 0, and 0, are reset and 0 3
and O. are set at system reset.
Each output from 0, - O. port is C-MOS.
Output Port EO, - EO.)
EO, - EO. is 4-bits output port. The contents
of the output latch can be rewritten by the output
instruction. The level is output at each output pin
after the system is reset. Each output of EO, EO. is CMOS output.
Input/Output Port (10, - 10.)
10, - 10. is 4-bits input/output port. Fetching of the port status and rewriting of the output
latch contents can be done by the input/output
instruction.
Each Output of 10, - 10. is CMOS at output
mode.
10E Output Pin
It is one bit output pin. A load signal is output
at this pin when the output latch's (10, - 10.)
contents are rewritten.
DTMF Output Pin
It is output pin to output DTMF signals. Start
and stop of the OTMF output are done by the
output instruction.
DP Output Pin
It is an output pin for dial pulse output. Start
and top of the dial pulse output can be done by
the output instruction.
The OP OUT pin output is C-MOS output.
BD Output Pin
It is output pin for the buzzer output. The
buzzer output can be started and stopped by the
output instruction. Output of BO port is CMOS
output.
32 kHz Output Pin
It is an output pin to output 31.960 kHz clock
(duty: 50%) which is obtained by dividing the
3.579545 MHz system clock by 112. This clock
keep outputting as long as system clock oscilation
is executed. Output of 32 kHz pin is CMOS outout.
153
eMSM6352e------------------------------------------------------XT,XTPins
These are input and output pins of the oscillator inverter, and the oscillator circuit is provided
with the built in feed back resistor. By connecting to them oscillation of system clock status.
3.579545 MHz ceramic resonator and capacitors.
ELECTRIC CHARACTERISTICS
• Absolute Maximum Ratings
Parameter
Symbol
Conditions
Limits
Unit
VOO
Ta = 25'C
-30 -7
V
Input Voltage
VI
Ta = 25'C
-0.3 - VOO + 0.3
V
Output Voltage
Vo
Ta = 25'C
-0.3 - VOO + 0.3
V
Power Dissipation
Po
Ta = 25'C
200 max.
mW
Tstg
-
-55 - +125
°c
Symbol
Conditions
Limits
Unit
VOO
Pulse Mode
f OSC = 3.58 MHz
2.0 - 5.5
V
VOOM
-
1.2-5.5
V
Topr
-
-20 - +75
°c
Supply Voltage
Storage Temperature
• Operating Conditions
Parameter
Operating Voltage
Memory Retension Voltage
Operating Temperatu re
Note: Operating conditions for tone mode is VOO = 2.2 - 5.5V.
154
- - - - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6352 •
• DC Characteristics
(Ta = -20 - +75°C)
Conditions
Supply
Min.
Voltage
Parameter
Symbol
Typ.
Max.
Unit
"H" Output Current (1)
10H.
0 3, O.
VOH = 2.6V
3.0 V
-0.2
-
-
mA
"L" Output Current (1)
lOL,
OP OUT
VOL=O.4V
3.0V
0.5
-
-
mA
"H" Output Current (2)
10Hz
VOH = 2.6V
3.0V
-1.0
-
-
mA
VOL = O.4V
3.0V
10
-
-
f.J.A
C,-C.
"L" Output Current (2)
10Lz
"H" Output Current (3)
IOH3
O " Oz
VOH = 2.6V
3.0V
-2.0
-
-
J1.A
"L" Output Current (3)
IOL 3
BO
VOL = O.4V
3.0V
10
-
-
J1.A
"H" Output Current (4)
10H.
3.0V
-150
-
-
J1.A
"L" Output Current (4)
10L.
10, -10. VOH = 2.6V
10E
EO, - EO. VOL=O.4V
3.0V
300
-
-
J1.A
"H" Output Current (5)
10Hs
VOH = 2.6V
3.0V
-40
-
-
J1.A
VOL = O.4V
3.0V
25
-
-
J1.A
3.0V
2.2
-
-
5.5V
40
-
-
3.0V
-
-
0.8
5.5V
-
-
1.4
5.5V
-
-
2
3.0V
-2.0
-
-180
5.5V
-40
-
-360
VIH = 5.5V
5.5V
20
-
180
VIH = 3.01/
3.0V
10
-
90
VIL = OV
5.5V
-
-
-2
1,-1.
VIH = 5.5V
5.5V
60
-
600
AC,
VIH = 3.0V
3.0V
30
-
300
TEST
VIL = OV
5.5V
-
-
-2
J1.A
VIH = 5.5V
5.5V
-
-
2
J1.A
VIL = OV
5.5V
-
-
-2
J1.A
Tone output off
2.5V
-
0.25
0.5
With no load
5.0V
-
1.5
2.4
Tone output on
2.5V
-
1.3
2.4
With on load
5.0V
-
4.2
6.8
ON HOOK, Ta = 25°C
With no load
2.5V
-
-
0.2
"L" Output Current (5)
10Ls
"H" Input Voltage
VIH
Survey
Circuit
1
32kHz
V
-
2
"L" Input Voltage
"H" Input Current (1)
IIH,
"L" Input Current (1)
IlL,
V
-
VIL
VIH = 5.5V
HS
"H" Input Current (2)
11Hz
"L" Input Current (2)
II L z
"H" Input Current (3)
IIH3
"L" Input Current (3)
IIL3
"H" Input Current (4)
IIH.
"L" Input Current (4)
Current Consumption (1)
Current Consumption (2)
II L.
J1.A
VIL = OV
J1.A
R,- R3
J1.A
J1.A
3
10,-10.
mA
lOOp
mA
lOOT
Current Consumption (3) 100M
J1.A
4
J1.A
155
eMSM6352e----------------------------------------------------• AC Characteristics
Parameter
Cycle Time
(Ta = -20 - +75°C)
Supply
Min.
Voltage
Symbol
Conditions
tCY
f = 3.579545MHz
Typ.
Max.
Unit
f.LS
3.0V
-
17.9
-
2.2V
-
180
-
4.0V
-
260
-
5.5V
-
330
-
3.0V
1
2
3
5.5V
1
2
3
3.0V
-
-
5
5.5V
-
-
5
-
3.3
-
-
Row side only
Tone Output
VOUT
RL=1kn
High/Low Level Ratio
Distorsion Ratio
Switch Input Time
mV
rms
dB
-
dBCR
RL = 1 kn
%dlS
tKIN
%
ms
tTLH,
Q3. Q•• DP OUT
3.0V
-
-
0.5
tTHL,
CL = 50pF
3.0V
-
-
0.5
tTLH2
C,-C.
3.0V
-
-
0.5
tTHL2
CL = 50pF
3.0V
-
-
10
tTLH3
Q,. Q2. BD. 32kHz
3.0V
-
-
5
tTHL3
CL = 50pF
3.0V
-
-
10
tTLH.
10, - 10•• 10E
EO,- EO.
CL = 50pF
3.0V
-
-
1
3.0V
-
-
1
Rise/Fall Time (1)
5
f.LS
Rise/Fall Time (2)
f.LS
Rise/Fall Time (3)
Rise/Fall Time (4)
Survey
Circuit
f.LS
tTHL.
f.LS
• DTMF Tone Output Freqeuncy
Standard Frequency (Hz)
Output Freqeuncy (Hz)
Deviation (%)
R1
697
699.1
+0.30
R2
770
766.2
-0.49
R3
852
847.4
-0.54
+0.74
R4
941
948.0
C1
1209
1215.9
+0.57
C2
1336
1331.7
-0.32
C3
1477
1471.9
-0.35
f OSC = 3.579545MHz
156
-----------------------------------------------------·MSM6352·
Instruction Code
u
u
Mnemonic
13 12 11 10 9
8
7
ADD ACC. AP
0
0 0
0
0
P 0
ADD #D. AP
0
1
0
0
P
1
6 5 4
3
2
0 0
1
D
1
A
A=OH-FH. P=O or 1
A
D=OH-FH
A=OH-FH. P=O or 1
ADCAP
0 0
0 0
0
P 0
1
0
1
A
A=OH-FH. P=O or 1
c
SUB ACC. AP
0 0
0 0
1
P 0
1
0 0
A
A=OH-FH. P=O or 1
~
15.
0
SUB #D. AP
0
1
0
1
P
u
SBCAP
0 0
0 0
1
P 0
1
CMPACC. AP
0
0
0 0
1
P
1
CMP #D. AP
0
1
0
1
1
P
XOR ACC. AP
0
0 0
0
0
P 0
XOR #D. AP
0
1
1
1
P
BIT ACC. AP
0 0
0 0
0
P
BIT #D. AP
0
1
0
1
0
P
BIS ACC. AP
0
0 0
0
0
P
BIS #D. AP
0
1
0
0
P
BIC ACC,AP
0
0 0
BIC #D. AP
0
1
0
'~
1
D
D=OH-FH.
A
A=OW,,,'FH. P=O or 1
1
1
."E
~
0
0
P 0
0
1
P
IAPI- ACC
IAPI- D
A
A=OH-FH. P=O or 1
A
D=OH-FH.
A=OH-FH. p=o or 1
1
0
0
1
0
D
A=OH-FH. P=O or 1
-
-
-
IAPI V ACC
-
-
-
IAPI VO
A
A=OH-FH. P=O or 1
A
D=OH-FH,
A=O -F
P=Q or 1
A
A=OH-FH. P=O or 1
A
D=OH-FH.
A-O>.i-F><. p=o or 1
A=OH-FH. P=O or 1
0
P 0
0
1
0
A
II
I!
0 0
1
P 0
0
1
0
A
A=OH-FH. P=O or 1
cr:
ASR AP
0 0
0 0
0
P 0
0
1
1
A
A=OH-FH. P=O or 1
ASLAP
0 0
0 0
1
P 0
0
1
1
A
A=OH-FH. P=O or 1
SEZ
0 0
0
1
0
1
0
1
0 0
CLZ
0 0
0 0
0 0
1
0
1
0 0 0
0 0
SEC
0
0
1
0
0
1
0 0
0 0
CLC
0 0
0 0
1
0 0
1
0 0 0
SEG
0
0
1
0 0
0 0 0
0
0 0
-
AP ~ IAPI
-
AP~
'! ACC
IAPI V D
-
-
AP ~ IAPI A ACC
-
-
AP~ IAPI AD
-
IAPI- C ]
-
[IAPI~CJ
-
O-IAPI- C
-
C~IAPI~O
1
-
-
Z~1
-
0
-
-
Z~O
-
-
1
-
C~1
0
-
-
0 -
C~O
0 0
-
-
-
G~1
-
0 0 0
0
.~
~
IAPI V D
D=OH-FH,
A=OH-FH. p=O or 1
0 0
1
AP ~ IAPI V ACC
AP~
A
0 0
0
-
A
0 0
0 0
AP~ IAPI- ACC - C
-
ROR AP
c
AP~ IAPI- D
-
ROLAP
0
+ ACe + C
AP ~ IAPI- ACC
D-OH-FH.
A=OH-FH. P=O or 1
1
1
AP~ IAPI
A=OH-FH. P=O or 1
D
O. 1
+D
A
iii
0
+ ACe
IAPI
A
1
1
AP ~ IAPI
AP~
0
D
1
-
1
c
0
···
·· ····· · ····· · · -.
·- .
·····- ·
·
······
··
· · · c:
···
···
···
A=OH-FH. P=O or 1
1
1
Description
A
D
1
~
OJ
1
D
1
~
c3
0
E
:;
~
0
« ~
0
0
'"
~
0 0
0
1
Ii:
~
~
~
CLG
0 0
SEA
0
0 0 0
0 0
CLA
0
0 0
0
MOVACC. AP
1
1
1
1
0 0
1
0 0
0 0 0 0
0
-
- -
0
G~O
0
1
0
1
1
0
0 0 0
-
1
1
Z~1.C~1.G~1
0 0
1
0
1
1
0
0 0 0
0
0
0 0
0
1
1
-
0 0
0
Z ~ O. C ~ O. G ~ 0
A=OH-FH
-
-
-
AP~
-
-
MOV ACC. AX
1
1
1
1
0 0
X
A
X=OH-FH
A=OH-FH
MOV #D. AP
0
1
1
1
0 P
D
A
D=OH-FH
A=OH-FH. P=O or 1
MOV AP. ACC
1
1
1
1
1
1
MOV AX. ACC
1
1
1
1
1
0
CHGAP
1
1
1
0
0
1
CHGAX
1
1
1
0
0 0
0 0
0 0
X
0
0 0
X
0
1
A
A
A=OH-FH
A
X=OH-FH
A=OH-FH
I!
a
1
A
A=OH-FH
A
X=OH-FH
A=OH-FH
-
-
AX~ACC
-
-
AP~
-
ACC~
lAP I
-
-
ACC
~
IAXI
-
-
IAPI-ACC
-
-
IAXI .. ACC
··
····
··
-
ACC
D
157
eMSM6352e----------------------------------------------------Instruction Code
Mnemonic
13 12 11 10 9
1
8 7 6
5 4
3
2
0
0 0 0
RDAR
1
1 0
0
0
0
0
0
0
0
RDAR +(-)
1
1 0
0
0
0
0
0
1 D/I 0
0
0
0
0
D/I
~
Oar 1
S
S
8
··
-
-
ACC~(AR,)
··-
-
ACe
1 -
-
1
1 0
0
0
0
0
1
o D/I
0
0
0
0
D/I
~O
RDAR+(-), N
1
1
0
0
0
0
1
0
o D/I
0
0
0
0
D/I
~
0 or 1
RDAR +(-I,Z,L
1
1 0
0
1
0
0
1
o D/I
0
0
0
0
D/I
~
0 or 1
RDAR+(-),N,L 1
1 0
0
1
0
1
0
o D/I
0
0
0
0
D/I
~
0 or 1
MVAR
1
1
0
0
0
0
0
0
0
0
0
-
-
0
0
0
D/I
~
0 or 1
-
-
0
0
0
D/I
~
Oar 1
-
1 -
or 1
1
0
0
MVAR +(-)
1
1 0
1
0
0
0
0
1 D/I 0
MVAR+(-), Z
1
1
1
0
0
0
1
o D/I
0
0
Description
~
U
u 2
~
RDAR +(-), Z
0
"
0
-
-
+-
(AR I
),
ARt
+-
ARt ±1
ACC~
· ··
··· · -
-
~
t'!
r: e
-
-
-
0-
u
SELHR
0
0
1
1 1 0
EHLH
0
0
1 1
1 0
1 1 0
0 0 0
OHLH
0
0
1 1
1 0
1 1 0
0 0 0 0
SELN
0 0
1
1 0
1 0
1 0
1
1
0
SELP
0
0
1
1 1 0
1 0
1
1 0
EO
0
0
1
1 1
a
1 0
1
1 1 0
DO
0
0
1
1 1 0
1 0
1
1 0
NOP
0
0 0 0
0
0 0
a
0
0
0 0
0 0
-
-
-
Enable hook switch low to high trans*
mission
Disable hook switch low to high trans-
mission
0
- - - -
Disable on-hook dial
0 0 0 0
- - - -
No operation
1 0
159
OLMS-64 SERIES
rn
OKI
semiconductor
MSM6404
HIGH-SPEED 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6404 microcontroller is a low power, high-performance single-chip device
implemented in complementary metal oxide semiconductor technology. 32K bits of mask program
ROM, 1024 bits of data RAM, 36 Input/Output lines, a programmable timer/event-counter, and
oscillator are integrated onto one chip. Program memory is byte wide and data-paths are organized in
4 bit nibbles. RAM and I/O lines are bit addressable. 122 instructions include binary, BCD
operations; bit set, reset, test; 8 bit I/O; relative jumps; multifunctional instructional (increment,
modify, skip) 8 bit wide table output; subroutine call and return.
FEATURES
•
4000 x 8 MASK ROM
An evaluation board is available for up to 8k
x 8.
• 256 x 4 RAM (including the stack area)
• 9 x 4 Ports, 36 I/O lines
4 lines for input ports having a latch, and the
other 32 lines for bit operation are available.
• Three built-in counters
12-bit time-base counter
12-bit programmable timer
8-bit high-speed programmable timer/event
counter
• Built-in 8-bit serial I/O register (with 3-bit
counter)
• Five interrupts with five priority levels
(4 internal, 1 external)
• 32 stack levels (in RAM)
• LED direct drive available (8mA x 5 ports at the
same time)
• Power down features
• Instruction execution time
952 ns 4.2 MHz clock
• Instruction systems suitable for control
• 122 instructions
• Mask option
P60-63 for input port
• Full static operation
• Low power consumption
TYP O.4j1W at VOO=2V
TYP 5j1W at VOO=5V OHz clock
• 5V single power supply, 42-pin DIP or
44-pin FLAT
BLOCK DIAGRAM
ROM
4000 x 8
-GND
3210
3210
1 t
LL
32 10 3210_3210 3210
INTO
aN ~I -L §CK CTo
TMO Lso
TCK
eLK
51
163
• MSM6404 ••- - - - - - - - - - - - - - - - - - - - - - - - - -
PIN CONFIGURATION
(Top View) 42-pin Plastic DIP
(Top View) 44-pin Plastic Flat Package
g> 0:
'" 0:" ~ 0: >00 ""Il.,,
0
0
"
'"
Il.
0
"'
Il.
'"
if If
0
P3'
P32
P62
P6'
P33
P73
P72
P7'
P70
P20
P2'
P22
P23
poo
po,
P60
05Co
NC
osc,
P73
RESET
P72
TEST
P7'
P20
P90
P~3
P2'
P83
P82
P22
pa2
P8'
P80
P23
pa,
P'3
P02
P'2
Pll
P03
~ ~ Il."o Il.'"0
P'O
0
"
z z
'"
0
a: a: a:" a:'" "
0
Il.
PIN DESCRIPTION
Pin name
Function
Input/output
When reset
POO
P01 / SCK
P02/S0
P03/SI
Input/output
4-bil input/output port.
P01 to P03 are also used as serial interface
terminals.
"1"
P10/CIN
P11/TMO
P12/TCK
P13
Input/output
4-bil input port with latch.
Built-in pull up register for all bit input.
"1"
P20/INT
P21
P22
P23
Input
4-bit input port with a latch. P20 is shared with INT
input. (Fall trigger input) P21 - 23 are level input.
Built-in pUll up register for all bit input.
P30-33
Input/output
4-bit input/output port
P40-43
Input/output
4-bit input/output port
The latch is
reset.
"1"
"0"
: 8-bit output port
P50-53
Input/output
4-bit input/output port
P60-63
input/output
4-bit input/output port *1
"0"
P70-73
Input/output
4-bit input/output port
"0"
P80-83
Input/output
4-bit input/output port
OSCo
OSC,
Input/output
TEST
RESET
VDD
GND
"0"
X'tal connection terminal for system clock oscillation
Oscillation
wave
Output
(Test terminal for Maker)
Pulse output
Input
System reset input terminal
Power source voltage supply
Note: When each port is used for output, it is possible to drive one TTL (one input).
*1 Can be made asa port dedicated to input (mask option).
164
"0"
- - - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6404 •
INSTRUCTION LIST
Mnemonic
Oescri plion
Code
6yle
Cycle
LAI
n
A-n
9n
1
1
LLI
n
L-n
8n
1
1
LHLI
nn
HL-nn
15nn
2
2
LMI
nn
M(w)-nn
14nn
2
2
LAL
A-L
21
1
1
LLA
L-A
20
1
1
LAH
A-H
22
1
1
LHA
H-A
2E
1
1
LAM
A-M
38
1
1
LMA
M-A
2F
1
1
LAM+
A-M, L-L+1,SkipifL=0
24
1
1
0
LAM-
A -M, L -L-1, Skip if L= F
25
1
1
:::J
LMA+
M -A, L -L+1 ,SkipifL=O
26
1
1
LMA-
M -A,L -L-1,SkipifL=F
c.
a.
£tJ)
a.
-0
'"
0
27
1
1
LAMM
n,
A-M,H-HVn,
39-36
1
1
LAMO
mm
A-Md
10mm
2
2
LMAO
mm
Md-A
11mm
2
2
LMTO
mm
Md(w) - T (M(w), A), T =ROM lable
19mm
2
3
LMCT
M(w)-CT
3E59
2
2
LCTM
CT-M(w)
3E51
2
2
LMSR
M(w)-SR
3E5A
2
2
LSRM
SR -M(w)
3E52
2
2
LTMM
TM - (M(w), A)
3E50
2
2
PUSH
ST -C, A, H, L, SP -SP-4
1C
1
3
POP
C, A, H, L -, ST SP -SP+4
10
1
3
X
A-M
28
1
1
29-26
1
1
-'
Q)
n,
A-M,H-HVn,
Cl
XM
'x"
X+
A - M , L-L+1,SkipifL=0
3C
1
1
X-
A - M , L-L-1,SkipifL=F
2C
1
1
----
INA
A -A+1, Skip if A=O
30
1
1
E
Q)
INM
M -M+1,Skip ifM=O
33
1
1
INL
L-L+1,SkipifL=0
31
1
1
c
.c
()
LU
-C cQ)
Q)
~
()
E
Q)
~
()
Q)
Eo
165
• MSM6404 • - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
Description
INH
C
INMD
H-H+1,SkipifM~0
mm
Md -Md+1, Skip if Md
~O
Code
Byte
Cycle
32
1
1
12mm
2
2
CI>
E
~
DCA
A-A-1,SkipifA ~F
34
1
1
DCM
M-M-1,SkipifM
37
1
1
DCl
l -l-1, Skip ifl ~F
35
1
1
DCH
H -H-1,SkipifH
36
1
1
13mm
2
2
02
1
1
()
CI>
0
:;:,
~F
<:
Q)
E
~
()
E
DCMD
mm
~F
Md -Md-1,SkipifMd
~F
ADS
A -A+M, Skip if Cy
ADCS
A, C -A+M+C, Skip if Cy~1
01
1
1
ADC
A,C-A+M+C
03
1
1
AIS
n
A - A+n, Skip if Cy
~1
~1
3E4n
2
2
DAA
A-A+6
06
1
1
DAS
A-A+10
OA
1
1
AND
A-AVM
00
1
1
OR
A-AVM
05
1
1
EOR
A-AVM
04
1
1
CMA
A-A
OB
1
1
CIA
A-A+1
OC
1
1
RAl
Rotate left with C
OE
1
1
RAR
Rotate Right with C
OF
1
1
TC
SkipifC~1
09
1
1
SC
C-1
07
1
1
RC
C-O
08
1
1
()
:a;
E
:5
~
~
'"
Q.
E
CAl
n
SkipifA~n
3EOn
2
2
CLI
n
Skipifl~n
3E2n
2
2
CPI
p, n
SkipifPp~n
17pn
2
2
CMI
n
SkipifM~n
3E1n
2
2
SkipifA~M
16
1
1
54-57
1
1
0
()
CAM
<:
0
~CI>
Q.
~1
TAB
n,
Skip if Abit (n ,)
RAB
n,
Abit(n,)-O
64-67
1
1
SAB
n,
Abit(n,)-1
74-77
1
1
TMB
n,
Skip if Mbit (n ,)
58-5B
1
1
RMB
n,
Mbit(n,)-O
68-6B
1
1
0
iIi
166
~1
- - - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6404 •
INSTRUCTION LIST (Continued)
Mnemonic
Description
Code
Byte
Cycle
5MB
n
Mbit(n,)-1
78-7B
1
1
TFB
n,
Skip if Fbit (n,) =1
5C-5F
1
1
RFB
n,
Fbit(n,) -0
6C-6F
1
1
SFB
n,
Fbit(n,)-1
7C-7F
1
1
~
E
TPB
n,
Skip if Pbit (n,) =1
50-53
1
1
c.
0
RPB
n,
Pbit(n,) -0
60-63
1
1
iii
SPB
n
Pbit(n,)-1
70-73
1
1
TPBD
pn,
Skip if Ppbit (n,) =1
3Dpo-3
2
2
RPBD
P n,
Ppbit (n ,) = 0
3Dp.-,
2
2
SPBD
pn,
Ppbit (n ,) =1
3Dp.-B
2
2
c
Ql
Ci
2
Q;
E
MEl
MEIF-1
3E60
2
2
MDI
MEIF-O
3E61
2
2
EITB
EITBF-1
3DC9
2
2
EITM
EITMF-1
3DCA
2
2
EICT
EICTF-1
3DCB
2
2
EIEX
EIEXF-1
3DC8
2
2
DITB
EITBF-O
3DC5
2
2
DITM
EITMF-O
3DC6
2
2
DICT
EICTF-O
3DC7
2
2
DIEX
EIEXF-O
3DC4
2
2
TITB
Skip If EITBF =1
3DC1
2
2
TITM
Skip If EITMF =1
3DC2
2
2
TICT
Skip If EICTF =1
3DC3
2
2
TIEX
Skip If EIEXF =1
3DCO
2
2
TOEX
Skip If IROEX =1
3D20
2
2
TOTB
Skip If IROTB =1
3DDO
2
2
TOTM
Skip If IROTM =1
3DD1
2
2
TOCT
Skip If IROCT =1
3DD2
2
2
TOSR
Skip If IROSR =1
3DD3
2
2
ROEX
IROEX-O
3D24
2
2
ROTB
IROTB-O
3DD4
2
2
ROTM
IROTM-O
3DD5
2
2
ROCT
IROCT-O
3DD6
2
2
ROSR
IROSR-O
3DD7
2
2
167
• MSM6404 •
-----------------~-------
INSTRUCTION LIST (Continued)
Mnemonic
.9
'"
.::=
.~
(/)
Q)
~
..<:
$
"0
Description
Code
Byte
Cycle
ECT
CTF ~1 (start)
3DBB
2
2
ESR
SRF -1 (start)
3DBA
2
2
DCT
CTF ~O (stop)
3DB7
2
2
DSR
SRF ~O (stop)
3DB6
2
2
TCT
Skip If CTF =1
3DB3
2
2
TSR
Skip If SRF =1
3DB2
2
2
PC-a.
CO-FF
1
1
4a12
2
2
Ba
1
4
Aa12
2
4
18
1
3
IE
1
4
:::J
<.)
JCP
a.
JP
a'2
PC~a12
CZP
a
ST -PC+1, PC -2a,
SP-SP-4
CAL
a12
ST -PC+2, PC -a12,
SP~SP-4
.<:
()
"~
OPT
P5, P.-T (M(w), A),
T=ROMtable
RT
PC -ST, SP
RTS
PC -ST, SP -SP+4,
Skip unconditional
IF
1
4
JA
PC -(PC -A)+1
IA
1
1
JM
PC-(M(w),A)
IB
1
2
IP
A-P
20
1
1
IPD
A-Pp
3DpD
2
2
23
1
1
3DpC
2
2
lD
:;
B
:::J
0
:;::
:::J
0.
E
e
::J0.."
P
OP
OPD
~SP+4
P-A
p
Pp-A
NOP
No Operation
00
1
1
HALT
HaltCPU
3DB8
2
2
STOP
Stop Clock
3DB9
2
2
<.)8
168
- - - - - - - - - - - - - - - - - - - - - - - - - - ' . MSM6404 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Conditions
Voo
Input Voltage
VI
Output Voltage
Vo
Ta=25°C
Ta = 25°C per package
Power Dissipation
Storage Tern perature
Limits
Unit
-0.3t07
V
-0.3toVoO
V
-o.3toVoO
V
200 max.
mW
Po
Ta = 25°C per output
50 max.
mW
Tstg
-
-55 to +150
°C
Symbol
Conditions
Limits
Unit
I(OSC) ;$1 MHz
3t06
V
V
OPERATING RANGE
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
VOO
I(OSC) ;$4.2 MHz
4.5 t05.5
VOOH
I (OSC) =OHz
2t06
V
TOp
-
-40 to +85
°C
MOSLoad
15
TTL Load
1
FanOut
N
-
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 to +85°C)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
2.4
-
VOO
V
VOO
V
-
0.8
V
-
V
-
0.4
V
0.4
V
1
2
V
-
15/-15
/LA
5
"H"lnput Voltage*1,*2
VIH
"H"lnputVoltage*3,*4
VIH
-
3.6
"L"lnput Voltage
VIL
-
-0:3
"H" OutputVoltage*1,*5
VOH
10=-15/LA
4.2
"L" Output Voltage *1
VOL
10=1.6mA
"L" Output Voltage*5
VOL
10 =15/LA
"L" Output Voltage*6
VOL
la=BmA
Input Current*3
IIH/IIL
VI=VOO/OV
Input Current*2,*4
IIH/IIL
VI=VOO/OV
-
"H" OutputCurrent*l
10H
VO=2.4V
-0.1
"H" Output Current*l
1/-30
/LA
-
rnA
-1.2
rnA
7
-
pF
10H
VO= O.4V
Input Capacity
CI
Output Capacity
Co
1=1 MHz
Ta=25°C
-
VOO=2V, no load
Ta=25°C
-
0.2
5
/LA
No load
-
1
100
/LA
Quarts oscillation
1=4 MHz, no load
-
6
12
rnA
Current Dissipation
(when stop condition)
Current Dissipation
IOOS
100
*1 Applied to PO, Pl, P3, P4, P5, P6, P7 and PB
*2 Applied to P2
*3 Applied to asc.
* 4 Applied to RESET
* 5 Applied to 0SC7
*6 - In using LED, total output current should be within the limit 01 Power d.issipitation in "Absolute Maximum
Rating."
169
• MSM6404 ••- - - - - - - - - - - - - - - - - - - - - - - - - -
AC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40° to +85°C)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Clock Pulse Width
Clock (OSC)
I,f,w
-
Cycle Time
Icy
-
119
-
-
nS
952
-
120
-
-
nS
120
-
Input Data Setup Time
tDS
-
Input Data Hold Time
tDH
Input Data, Input
Clock Pulse Width
tow
-
120
-
-
nS
nS
nS
SR Data Setup Time
tss
-
120
-
tSH
-
120
Data Delay Time
tOR
CL = 15pF
tCy+300
nS
Data Delay Time at
Mode Switching
tDCR
CL=15pF
-
-
-
nS
SR Data Hold Time
-
7/StCy+300
nS
Data Delay Time at
OPT Instruction
tOIl
CL = 15pF
-
-
6/StCy+300
nS
Data Delay Time at
OPT Instruction
nS
tDI2
CL = 15pF
-
-
7/S tcy + 300
nS
CT/TM Data Delay
Time using TBC Clock
tCT/tn
CL = 15pF
-
-
2/Stcy+360
nS
SR/TM Data Delay
Time using PR Clock
tSR/ITR
CL=15pF
-
-
tCy+4S0
nS
CT Data Delay Time
using PR Clock
tCR
CL = 15pF
-
-
lOIS tCY + 4S0
nS
CT Data Delay Time
using External Clock
tcp
CL=15pF
-
-
2/StCY+360
nS
SR/TM Data Delay
Time using External
Clock
tSp/lTp
CL=50pF
-
-
360
nS
-
-
nS
SR Clock Invalid Time
tSINH
INT Invalid Time
tliNH
170
-
2/StCY
I/StCY
nS
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6404 •
TIMING CHARTS
Output Condition
OSC o
Po, p., P,
p.,p"p.
0,1,3
PA=4,5,6
P" P,
7 or
a
~C~n
b:'--b:L k-'~ L-
~I.------t-D-R--~--------~--------~------~~~------f~r----------tD-I-1----------~~-------------
r----tD-CR
~-----------t-D-12----------------~J~-----
P,
Tac clock
CT
TM
po. clock' SR
P I> clock" TM
p. 0 clock" CT
p. o , po., PI> EXT clock
~1·========tctC~R~======~~
,
J~
CT
t---tcp-
SR
TM
---0
tsp
I--
---0
tTP
f.-.. Output Data to port will be ciock for SR, TM or CT.
171
• MSM6404.,---------------------------------------------------Input Condition
1MC
OSC O
PO,Pl,P,
P" P4 , P,
P"P"P,
SR clock
TM clock
1'---.)
- - tDW
I---
1r--1
1\
POI
SR clock
PO,
SI
1\
INPUT
DATA
tss
1/
1\
tSH
1MC
OSC O
ts INH
ts INH: POI (SR clock) INH period during LMSR INST.
(Note: POI is used for clock of SR)
q INW P,o (interrupt) INH period during RPB and RPBD INST.
172
- - - - - - - - - - - - - - - - - - - - - - - - - - - ' . MSM6404 •
TYP. Current YS Voltage for High State Output
(lOH)
(VOH)
TYP. Current ys. Voltage for Low State Output
(loll
(VOL)
-1.0
-
-0.7
18
16
r---...
'"'"
-0.6
I-- r--..
-0.5
E
I
.9
r-- i--
-0.3
-0.2
I
-0.1
4V
~
0
~
""
'"
\
\
""
3
.'\4
....J
10
.9
\
\
\
5
\
7
0
2
(Ta
10
~
6
7
.......
I'--.. r--....
N
7
-
10
~
6
4
3
3
2
2
Ta (OC)
40
60
80
/
5
4
20
V
U
en
9-
0
9
/
I
5
-20
8
= 25°C, CL = 15 pF)
8
~DD=5V
-40
6
9
.......
I
o
5
(VOO)
10
7
4
TYP. Maximum Oscillator Frequency YS.
f(OSC)
Supply Voltage
11
~
3
VOL (V)
= 15 pF)
8
9-
'/
11
9
3V
2
6
TYP. Maximum Oscillator Frequency YS
f(OSC)
Temperature
(Ta)
U
en
/" ! -
4
VOH (V)
(CL
8
6
\
4V
.."....
~
12
E
r\
'\.
2
14
VDD = 6V
NV
-0.4
N
5V
6V
-0.8
~
I /' _VDD
I
II I
rl ...f/
20
-0.9
100
0
/
/
/
2345678
VDD (V)
173
eMSM6404e-------------------------------------------------TYP. Supply Current vs. Supply Voltage
ODD)
(VDD)
(Ta=25°C)
No Load
10m
1I?SC)=4MHZ ::
....
-
V
1m
2J"Hz
~
1JHZ
500kHz
.100kHz
1001'
5
c
.9
101'
~
./
11'
I.- OHz
I.....
100n
o
2
3
4
5
6
VOO(V)
174
7
8
9
10
OKI
&emiconductor
MSM6404VS
MSM6404 PIGGY BACK
GENERAL DESCRIPTION
The MSM6404VS is a device whose built-in ROM is replaced by external EPROM using the piggyback method.
FEATURES
•
Supply Voltage: 5V
± 5%
• Frequency: DC - 4.2 MHz
• Operating Temperature: 0 - 70°C
Note: There are a few differences in the electrical characteristics of this chip and the evaluation chip.
Please refer to next page for the detail.
PUTTING METHOD OF ROM
Please refer to drawing below.
M6404VS
OKI
JAPAN4X30
PIN CONFIGURATION
Pin Connection between MSM6404 VS and EPROM
Vee
I
A12
All
10
9
ToAO-A12
of MSM6404VS
¢
8
J
DO
1
2
11
'Y
DATA
-
7
6
ADDRESS
1
ToDl0-D7
ofMSM6404VS
-
3
_Vpp
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
rGND
1"'-'28
2
27
3
26
4
25
5
24
6
23
7 276422
8
21
9
20
10
19
11
18
12
17
VCCPGMN.C.A8A9
All
~~01
CE
070605-
"~
-14
15
03
4
5
6
Note: When putting 2732A.
pin 1, 2, 27, 28 are not used.
07
GND
175
e MSM6404VS
e--------------------------------------------------
DIFFERENCES BETWEEN MSM6404 AND MSM6404VS (PIGGY-BACK)
Item
6404
6404VS (Piggy-Back)
1. Port
initialization
during reset
Port PO, 1,3 are set to "1 " and port
2,4,5,6, 7,8 are reset to "0"
directly by signal put into the
RESET.
Port PO, 1,3 are set to "1" and port 2,
4, 5, 6,7,8 are reset to "0" during reset
cycle being executed.
2. Timer
Operation
After being reset, timer stops
counting until data are set in it.
It is undecidable whether the timer
starts counting or not after being reset.
Therefore, the timer should be
initialized by software.
3. Shift registor
Serial Out F/F (SOF/F) is set to "0"
after being reset.
It is undecidable whether Serial Out
F/F (SOF/F) is set to "0" or "1" after
being reset. Therefore Serial Out F/F
should be initialized by software.
Internal clock ~
Internal clock
4. Port
input/output
timing
t
1
Data are input
at this moment
Data are input
at this moment
Synchronized
with falling edge
Internal clock
Internal clock ~
J1SL
==}c=
k=
Data are output
at this moment
Data are output
at this moment
5. Port
input/output
(maracteristics)
TTL FO=1
(lOL = 1.6 mA 0.4V)
LSTTLFO=1
(lOL = 0.4 mA 0.4V)
VDD
4-
P20-3
VDDVDD
P20-3
TTL compatible input
POO-P83
e---{9o--
(Except P20-3)
176
~
~
CMOS input
POO-83
o------t>o--
(Except P20-3)
Available
ROM capacity
4K byte
Accessible up to 8K byte
IPLcall
instruction
Not available
Available
OKI
semiconductor
MSM6408
HIGH-SPEED 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6408 microcontroller is a low power, high-performance single-chip device
implemented in complementary metal oxide semiconductor technology. 64K bits of mask program
ROM, 1024 bits of data RAM, 36 Input/Output lines, a programmable timer/event-counter, and
oscillator are integrated onto one chip. Program memory is byte wide and data-paths are organized in
4-bit nibbles. RAM and 110 lines are bit addressable. 122 instructions include binary, BCD
operations; bit set, reset, test; 8-bit 110; relative jumps; multifunctional instructional (increment,
modify, skip) 8-bit wide table output; subroutine call and return.
FEATURES
• 8096 x 8 MASK ROM
An evaluation board is available for up to 8K
x 8.
• 256 x 4 RAM (including the stack area)
• 9 x 4 Ports, 36 I/O lines
4 lines for input ports having a latch, and the
other 32 lines for bit operation are available.
• Three built-in counters
1 2-bit time-base counter
1 2-bit programmable timer
8-bit high-speed programmable timer/event
counter
• Built-in 8-bit serial I/O register (with 3-bit
counter)
• Five interrupts with five priority levels
(4 internal, 1 external)
• 32 stack levels (in RAM)
• LED direct drive available (SmA x 5 ports at the
same time)
• Power down features
• Instruction execution time
1.0/Ls 4.0 MHz clock
• Instruction systems suitable for control
• 1 22 instructions
• Mask option
P60-63 for input port
• Full static operation
• Low power consumption
TYP O.4/LW at VDO=2V
TYP 5/LW at VDD=5V OHz clock
• 5V single power supply, 42-pin DIP or
44-pin FLAT
BLOCK DIAGRAM
ROM
BOOO x 8
-VOD
-GND
3210
3210
3210 3210 3210 3210
3210_3210 3210
INTO
I L;!I L~CK
LTCK LSI
eTC eLK
177
0
I
eMSM640Se------------------------------------------------PIN CONFIGURATION
(Top View) 42-pin Plastic DIP
44 Pin Plastic Flat Package
.,
~ l
P40
N
_
.,
0
:. :. :.
0., N
c., .,
> ....
if
~ If
P41
0
P31
P32
Pe2
Pel
P33
P60
OSC.
NC
esc.
P73
RE§Ei'
P72
TEST
P71
P20
P90
P2l
P22
P21
P63
P22
P82
P23
P23
P81
POO
POI
P02
.8 . ~ f '"
P03
0
00
z z
0
a: a:
N
.,
[ 0:.
.
.,
0
PIN DESCRIPTION
Pin name
Input/output
Function
When reset
POO
P01/SCK
P02/S0
P03/S1
Input/output
4-bit input/output port.
P01 to P03 are also used as serial interface
terminals.
111 "
P10/CIN
P11ITMO
P12/TCK
P13
Input/output
4-bit input port with latch.
Built·in pull up register for all bit input.
Ill"
P20/lNT
P21
P22
P23
input
4-bit input port with a latch. P20 is shared with INT
input. (Fall trigger input) P21 - 23 are level input.
Built-In pull up register for all bit input.
P30-33
Input/output
4-blt Input/output port
P40-43
Input/output
4-bit input/output port
The latch is
reset.
"l"
"0"
: a-bit output port
"0"
P50-53
Input/output
4-bit Input/output port
P60-63
Input/output
4-blt Input/output port *1
lion
P70-73
Input/output
4-blt input/output port
"0"
paO-a3
Input/output
4-bit input/output port
OSC.
OSCI
Input/output
TEST
RESET
VOO
GNO
X'tal connection terminal for system clock oscillation
Output
(Test terminal for Maker)
Pulseoutput
Input
System reset input terminal
Power source voltage supply
Note: When each port is used for output, it is possible to drive one TTL (one input).
*1 Can be made as a port dedicated to input (mask option).
178
"0"
Oscillation
wave
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
INSTRUCTION LIST
Mnemonic
c.
~
£
rtl
:::l
c..
-0
01
0
Description
Code
Byte
Cycle
LAI
n
A-n
9n
1
1
LLI
n
L-n
8n
1
1
LHLI
nn
HL-nn
15nn
2
2
LMI
nn
M(w)-nn
14nn
2
2
LAL
A-L
21
1
1
LLA
L-A
2D
1
1
LAH
A-H
22
1
1
LHA
H-A
2E
1
1
LAM
A-M
38
1
1
LMA
M-A
2F
1
1
LAM+
A -M, L -L+1, Skip ifL=O
24
1
1
LAM-
A -M, L -L-1, SkipifL=F
25
1
1
LMA+
M -A, L -L+1,SkipifL=0
26
1
1
LMA-
M -A, L-L-1,SkipifL=F
27
1
1
.J
LAMM
n.
A-M,H-HVn.
39-3B
1
1
LAMD
mm
A-Md
10mm
2
2
LMAD
mm
Md-A
11mm
2
2
LMTD
mm
Md(w) -T (M(w), A), T=ROM table
19mm
2
3
LMCT
M(w)-CT
3E59
2
2
LCTM
CT-M(w)
3E51
2
2
LMSR
M(w)-SR
3E5A
2
2
LSRM
SR-M(w)
3E52
2
2
LTMM
TM -(M(w),A)
3E50
2
2
PUSH
ST-C,A,H,L, SP-SP-4
1C
1
3
POP
C, A, H, L, -ST SP -SP+4
1D
1
3
28
1
1
29-28
1
1
A -M, L -L+1, Skip if L=O
3C
1
1
X-
A-M,L-L-1,SkipifL=F
2C
1
1
X
A-M
Q)
Cl
XM
0
X+
c:
01
.c:
)(
w
-
.....
-c:
c: Q)
n.
A-M,H-HVn.
INA
A -A+1, Skip if A=O
30
1
1
Q)e
e
Q)
INM
A -M+1, Skip IfM=O
33
1
1
gg
_0
INL
L-L+1,SkipifL =0
31
1
1
I!!~
179
• MSM6408 • - - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
Description
INH
c:
Q)
INMD
H-H+1.SkipifM=0
mm
Md -Md+1. Skip if Md =0
Code
Byte
Cycle
32
1
1
12mm
2
2
E
~
DCA
A -A-1. Skip if A = F
34
1
1
DCM
M-M-1.SkipifM =F
37
1
1
E
DCl
l -l-1.Skipifl =F
35
1
1
0
DCH
H -H-1.Skip ifH =F
36
1
1
0
Q)
Cl
:;::,
r::
Q)
~
E
13mm
2
2
ADS
A - A+M. Skip if Cy =1
02
1
1
ADCS
A. C - A+M+C. Skip if Cy=1
01
1
1
DCMD
mm
ADC
AIS
Md -Md-1.SkipifMd =F
A.C-A+M+C
n
A -A+n. Skip ifCy =1
03
1
1
3E4n
2
2
DAA
A-A+6
06
1
1
DAS
A-A+10
OA
1
1
AND
A-AVM
00
1
1
E
OR
A-AVM
05
1
1
~
EOR
A-AVM
04
1
1
0
~
:§
~
as
c.
E
-
CMA
A-A
OB
1
1
CIA
A-A+1
OC
1
1
RAl
Rotate left with C
OE
1
1
RAR
Rotate Right with C
OF
1
1
TC
SkipifC=1
09
1
1
SC
C-1
07
1
1
RC
C-O
08
1
1
CAl
n
Skip if A =n
3EOn
2
2
CLI
n
Skipifl=n
3E2n
2
2
CPI
p.n
Skip if Pp=n
17pn
2
2
CMI
n
SkipifM =n
3E1n
2
2
SkipifA=M
16
1
1
54-57
1
1
0
<..)
CAM
r::
0
~Q)
c.
TAB
n2
Skip if Abit (n2) =1
RAB
n2
Abit (n2)-0
64-67
1
1
SAB
n2
Abit(n,}-1
74-77
1
1
TMB
n2
Skip if Mbit (n,) =1
58-5B
1
1
RMB
n2
Mbit(n2)-0
68-68
1
1
0
iii
180
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
INSTRUCTION LIST (Continued)
Mnemonic
Description
Code
Byte
Cycle
5MB
n
Mbil(n.)-l
78-7B
1
1
TFB
n,
Skip if Fbi! (n.) =1
5C-5F
1
1
RFB
n,
Fbi!(n,)-O
6C-6F
1
1
c
SFB
n,
Fbil(n.)-l
7C-7F
1
1
~CD
TPB
n,
Skip if Pbil (n ,) =1
50-53
1
1
0
c.
0
RPB
n,
Pbil(n.)-O
60-63
1
1
SPB
n
Pbil(n.)-l
70-73
1
1
TPBO
pn,
Skip if Ppbil (n.) =1
30pO-3
2
2
RPBO
pn,
Ppbll (n,) =0
30p.-7
2
2
SPBO
pn,
Ppbil (n,) =1
3DpB-B
2
2
3E60
2
2
iii
MEl
MEIF-1
MOl
MEIF-O
3E61
2
2
EITB
EITBF-1
30C9
2
2
EITM
EITMF-1
30CA
2
2
EICT
EICTF-1
3DCB
2
2
EIEX
EIEXF-1
30C8
2
2
OITB
EITBF-O
3DC5
2
2
OITM
EITMF-O
30C6
2
2
OICT
EICTF-O
30C7
2
2
OIEX
EIEXF-O
30C4
2
2
TlTB
Skip If EITBF =1
3DC1
2
2
15.
E
TlTM
Skip If EITMF =1
3DC2
2
2
!!!
E
TICT
Skip If EICTF =1
30C3
2
2
TlEX
Skip If EIEXF =1
30CO
2
2
TOEX
Skip If IROEX =1
3020
2
2
TOTB
Skip If IROTB =1
3000
2
2
TOTM
Skip If IROTM =1
3001
2
2
TOCT
Skip If IROCT =1
3002
2
2
TOSR
Skip If IROSR =1
3003
2
2
ROEX
IROEX-O
3024
2
2
ROTB
IROTB-O
3004
2
2
ROTM
IROTM-O
3005
2
2
ROCT
IROCT-O
3006
2
2
ROSR
IROSR-O
3007
2
2
181
• MSM6408 • - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
.9
~.!!!
Description
Code
Byte
Cycle
ECT
CTF -1 (start)
30BB
2
2
ESR
SRF -1 (start)
30BA
2
2
OCT
CTF -0 (stop)
30B7
2
2
OSR
SRF -0 (stop)
30B6
2
2
TCT
Skip If CTF =1
30B3
2
2
TSR
Skip If SRF =1
30B2
2
2
:E~
cn~
.2lc
:::l
0
()
JCP
ae
PC-ae
CO-FF
1
1
JP
a'2
PC-a'2
4a'2
2
2
LJP
a'3
PC-a13
3F
3
4
CZP
a
ST - PC+1 ,PC -2a,
SP-SP-4
Ba
1
4
CAL
a'2
ST-PC+2,PC-a,2,
SP-SP-4
Aa12
2
4
RT
PC -ST, SP -SP+4
IE
1
4
RTS
PC -ST, SP -SP+4,
Skip unconditional
IF
1
4
JA
PC-(PC-A)+1
IA
1
1
JM
PC - (M(w), A)
IB
1
2
IP
A-P
20
1
1
A-Pp
30pO
2
2
P-A
23
1
1
30pC
2
2
00
1
1
.<:
0
c
£
:::l
.9:::l
0
.....
"5
Co
IPO
p
OP
E:
OPO
e
::::l-
f>§
182
p
Pp-A
NOP
No Operation
HALT
HaltCPU
30B8
2
2
STOP
Stop Clock
30B9
2
2
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Conditions
Limits
Unit
-0.3t07
V
Ta=25 DC
-0.3 to VOO
V
Voo
Input Voltage
VI
Output Voltage
Vo
-0.3 to VOO
V
200 max.
mW
Ta = 25 DC per output
50max.
mW
-
-55to+150
DC
Ta = 25 DC per package
Power Dissipation
Storage Temperature
Po
Tstg
OPERATING RANGE
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
Conditions
Limits
Unit
f(OSC);:;;1 MHz
3t06
V
f(OSC) ;:;; 4.0 MHz
4.5t05.5
V
VOOH
f(OSC) =0 Hz
2t06
V
TOp
-
-40 to +85
DC
MOSLoad
15
TTL Load
1
Symbol
VOO
FanOut
N
-
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 to +85 D C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
"H" InputVoltage*1,*2
VIH
V
3.6
-
VOO
VIH
-
2.4
"H" Input Voltage *3,*4
VOO
V
0.8
V
-
V
0.4
V
0.4
V
1
2
V
-
15/-15
f.!A
-
1/-30
f.!A
-
rnA
-1.2
rnA
5
pF
Parameter
"L" Input Voltage
VIL
-0.3
"H" Output Voltage *1, *5
VOH
IO=-15f.!A
4.2
"L" Output Voltage *1
VOL
IO=1.6mA
"L" Output Voltage *5
VOL
10 = 15f.!A
VOL
IO=BmA
Input Current'3
IIH/IIL
VI=VOO/OV
Input Current*2,*4
IIH/IIL
VI =VOO/OV
-
"H" Output Current*1
IOH
VO=2.4V
-0.1
"H" Output Current*1
IOH
VO=0.4V
-
"L" Output Voltage*6
Input Capacity
CI
Output Capacity
Co
Current Dissipation
(when stop condition)
Current Dissipation
-
7
-
VOO=2V, no load
Ta=25 DC
-
0.2
5
f.!A
No load
-
1
100
f.!A
-
6
12
rnA
f=1MHz
Ta=25 DC
IOOS
100
Quarts oscillation
f=4 MHz, no load
I
*1
*2
Applied to PO, P1, P3, P4, P5, P6, P7 and P8
AppliedtoP2
*3 AppliedtoOSCo
*6
In USing LED, total output current should be within the limit of Power dissipitation in "Absolute Maximum
Rating."
*4
Applied to RESET
*5
AppliedtoOSC,
183
• MSM6408 • - - - - - - - - - - - - - - - - - - - - - - - - -
AC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 to +85°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Clock Pulse Width
Clock (OSC)
tq,W
-
125
-
-
nS
Cycle Time
toy
/LS
120
-
nS
Input Data Hold Time
tOH
120
-
-
tos
-
1
Input Data Setup Time
-
nS
Input Data, Input
Clock Pulse Width
tow
-
120
-
-
nS
SR Data Setup Time
tss
-
120
tSH
-
120
-
Data Delay Time
tOR
CL =15pF
-
-
nS
SR Data Hold Time
tCy+300
nS
tDCR
CL =15pF
-
-
7/StCY +300
nS
CT/TM Data Delay
Time using TBC Clock
tCT/tTT
CL =15pF
-
-
2/StCy+360
nS
SR/TM Data Delay
Time using PR Clock
tSR/tTR
CL =15pF
-
-
tCy+4S0
nS
CT Data Delay Time
usi ng PR Clock
tCR
CL =15pF
-
-
1O/S tCY + 4S0
nS
CT Data Delay Time
using External Clock
tcp
CL =15pF
-
-
2/StCY +360
nS
SR/TM Data Delay
Time using External
Clock
tSP/tTP
CL =50pF
-
-
360
nS
SR Clock Invalid Time
tSINH
-
-
nS
tllNH
-
2/StCY
INT Invalid Time
-
nS
Parameter
Data Delay Time at
Mode Switching
184
l/StCY
nS
- - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
TIMING CHARTS
Output Condition
OSC o
po,p.,p,
p.,p"p.
P p.
"
0,1,3
PA=4,5,6
7 or 8
PA = gar A
po.
p..
po.
p ..
TBC clock
0\fVVi-n~I.------------tD-R------------------------~----~~~----~I,---------t-DC-R---------J~------
CT
TM
po. clock' SR
p .. clock' TM
~tSR~t~
l
tTR
p. o clock' CT
p.o,po.,p .. EXTciock
1\
CT
f.--tcp-
S~
TM
-- tsp
tTP
I-• Output Data to port will be clock for SR, TM or CT.
185
e MSM640Se--------------------------------------------------Input Condition
lMC
OSC O
po. PI' P,
p •• p •• p,
p •• p,. P,
SR clock
TM clock
POI
I\.......J
-
tDW
f4--
SR clock
INPUT
DATA
tss
V
tSH
lMC
OSC O
ts INH
ts INH: POI (SR clock) INH period during LMSR INST.
(Note: POI is used for clock of SR)
tt
186
INH: P,o (jnterruptllNH period during RPBand RPBD INST.
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
TYP. Current vs Voltage for High State Output
(lOH)
(VOH)
TYP. Current vs. Voltage for Low State Output
(lOL)
(VOL)
(Ta ~ 25°C)
(Ta ~ 25°C)
-1.0
20
6V /
-0.9
-0.8
18
f----
-0.7
"-., Voo ~ 6V
-0.6
~
-0.5
.E
l---
'--
~V
:c -0.4
.9
-0.3
l---
-0.2 I
-
~
-0.1
0
""
2
'"
~
4V
'"
'\.
3
14
'\
\4
\ \
\
5
2
6
7
0
VOH (V)
2
3
4
5
6
7
8
9
10
VOL (V)
TYP. Maximum Oscillator Frequency vs.
HOSC)
Supply Voltage
(VOO)
(Ta ~ 25°C, CL ~ 15 pF)
15 pF)
10
10
9
~ t-....
8
~Voo~5V
7
........
6
1'---- t---...
U
N
:c
~
r-
U
til
Q
til
Q
4V
"
4
\
f/
..", ~
. / I-- 3V
11
8
N
8
1
9
:c
~
10
6
(Ta)
~
-l
f\
TYP. Maximum Oscillator Frequency vs
HOSC)
Temperature
(CL
12
.9
\
fj
~
.E
f\
5V
I--Voo
/
1/
16
-........
/'
5
7
/
6
5
4
4
3
3
2
2
II
V
v
I
/
1
o
-40
-20
0
20
Ta (C)
40
60
80
100
0
2
3
4
5
6
7
8
Voo (V)
187
OKI
semiconductor
MSM6411
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6411 microcontroller is a low-power, high-performance single-chip device
implemented in complementary metal oxide semiconductor technology. 1024 x 8 bits of program
ROM, 32 x 4 bits of data RAM, 11 Input/Output lines and oscillator. Program memory is byte wide
and data paths are organized as 4-bit wide. 63 instructions include binary, logical operations; bit set,
reset, test; multifunctional.
FEATURES
•
•
•
•
•
•
•
1024 x 8 Internal ROM
32 x 4 Internal RAM
11 I/O Lines (8 I/O Lines, 3 Input Lines)
8-bit serial I/O Register
2 Interrupt Levels
8 Stack Levels
LED direct drive available (SmA x 5 ports at the
same time)
• 952 ns 4.2MHz (VOO 5V±1 0%)
•
•
•
•
•
63 Instructions
Self-Contained Oscillator
-40 to +85°C Operating Temperature
3 to 6V Operating VOO
Low Power Consumption 5 ",W Typical
(STOP, VOO = 5V, no load)
• Mask Option Crystal/Ceramic
Oscillator
FUNCTIONAL BLOCK DIAGRAM
INST.
ROM
1024 x 8
DEC.
INT
8180
SCi<
188
RESET OSC.
OSC,
rr
VOOGND
----------------------------------------------------e MSM6411 e
LOGIC SYMBOL
PIN CONFIGURATION
(Top View)
16 PIN PLASTIC DIP (RS)
5V
:l~
SI
VOO
['
2
OV
PO
RESET
1
: SCK
Voo
0
"-
P10
0
CLOCK
(
21
'P2
INT
:J
{
3
1 P02/S0
2
~
~
11 P01/SCK
a:
0
"-
0
~
PIN DESCRIPTION
Designation
Input/Output
Pin No.
Function
Reset
Input/Output
10
11
12
13
4 Bits 1/0 port.
P01 to P03 are used both 1/0
port and terminal of shift resister
"1 "
Input/Output
14
15
1
2
P20/lNT
P21
P22
Input
3
4
5
Latch is reset.
3 Bits input port with latch.
("0")
P20 is used as both input port and
input terminal of INT (input of
falling edge trigger).
OSCo
Input
7
Input terminal of system clock.
Oscillation circuit consists of
OSCo and OSCI.
0SC1
Output
6
Oscillation circuit consists of
OSCo and OSCI.
RESET
Input
9
Input terminal of system reset
VDD
GND
Input
16
Main power source and circuit
GND potential.
POO
P01/SCi<
P02/S0
P03/S1
P10
P11
P12
P13
8
4 Bits 1/0 port
"1 "
Clock pulse In
189
e MSM6411e------------------------------------------------FUNCTIONAL DESCRIPTION
ROM
ROM is organized in 1024 words by 8 bits. It
is used to stored developed application
programs (instructions). It is addressed by the
program counter (PC).
PC
The PC consists of a 1 O-bit binary counter
and is used to address ROM.
Stack and Stack Pointer
An interrupt or CAL instruction causes the
contents of the PC to be saved in the stack. The
PC is restored from the stack by RT instruction.
All RAM locations (up to 8 levels) are
available as the stack. Note that four words of
RAM are used for each level.
The stack pOinter is a 5-bit up-down counter
that pOints to the address of the next stack to be
used. It allows the RAM locations to be used as a
push-down stack.
RAM
RAM consists of up to 32 words 4 bits wide. It
is addressed by the H- and L-registers or by the
contents of the second byte of an instruction.
L-REGISTER
A 4-bit register which specifies RAM
locations A3-AO.
H-REGISTER
A l-bit register which specifies RAM location
A4.
190
ALU
A 4-bit logic circuit that provides arithmetic
and logical operations.
ACC
Consisting of a 4-bit register, the
accumulator holds the result of operations or the
data present on ports.
CFLAG
The flag that holds a carry generated from the
result of operations.
INPUT/OUTPUT Ports (2 x 4 bit)
Organized into 4 bits, 2 ports are provided for
effecting and controlling data transfer to and
from an external source. The ports are selected
by codes included in instructions.
Input Ports (1 x 4 bit)
Contained port 2 (P2), which is an input port
with latching function. P20 is set at falling edge
of the input signal P21 and P22 are set at "0"
level inputs. Also, P20 is used as an interrupt
request flag. When P20 is set and an interrupt
operation occurs, it is automatically reset.
TIMING CONTROL (TC)
A 0 level on the RESET pin for longer than 2
machine cycles initializes the internal circuitry.
Clock pulses are supplied to the XT pin from
an external source. Also, by mask-option, it
organizes a circuit of oscillation with P20 and
produces clock pulses (by connecting externally
to crystal, ceramic or CR).
-----------------------------------------------------. MSM6411 •
INSTRUCTION LIST
Mnemonic
0.
~
.c
UI
:::I
c..
-cas
0
Description
Code
Byte
Cycle
LAI
n
A+-n
90-9F
1
1
LLI
n
L+-n
80-8F
1
1
LHLI
nn
HL +- nn
15nn
2
2
LAL
A+-L
21
1
1
LLA
L+-A
2D
1
1
LAM
A+-M
38
1
1
LMA
M+-A
2F
1
1
LAMD
mm
A+-Md
10mm
2
2
LMAD
mm
Md+-A
11mm
2
2
LMSR
M(w) +-SR
3E5A
2
2
LSRM
SR +-M(w)
3E52
2
2
PUSH
ST +- C, A, H, L, SP +- SP-1
1C
1
3
POP
C, A, H, L +- ST, SP +- SP+1
1D
1
3
...J
:::I
-0.
:::10.:::1
.=0
IPD
P
A+-Pp
3DpD
2
2
OPD
p
Pp+-A
3DpC
2
2
ADS
A+- A+M, SKIP IF Cy = "1"
02
1
1
ADC
C,A+-C+A+M
03
1
1
3E4n
2
2
AIS
n
A+- A+n, SKIP IF Cy = "1"
DAS
A+-A+10
OA
1
1
AND
A+-A AM
OD
1
1
~
EOR
A+-AV-M
04
1
1
=:
CMA
A+-A
OB
1
1
CAM
SKIPIFA=M
16
1
1
SC
C +-"1"
07
1
1
RC
C+-HO"
08
1
1
TC
SKIP IF C = "1 "
09
1
1
OE
1
1
°
E
~
r--A ______
RAL
_'"
,.,c
[C+-3+-2+-1+-°i
Q)
X
A-M
28
1
1
...... c
c CD
CD E
CD
E
CD ...
INL
L +- L+1, SKIP IF L = "0"
31
1
1
INH
H +-H+1, SKIP IF H = "0"
32
1
1
°CD
INM
M +-M+1, SKIP IF M = "0"
33
1
1
)(J:
-
wu
... 0
'=0
191
• MSM6411 ••--------------------------------------------------
INSTRUCTION LIST (CO NT.)
Mnemonic
-
......
c
CO)
-=
Il. c
og
192
----------------------------------------------------. MSM6411 •
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
Limits
-0.3 -7
V
Ta= 25°C
-0.3 -VDD
V
-0.3 -VDD
V
Ta= 25°C
per one package
200 max.
mW
Ta= 25°C
per one output
50 max.
mW
-55-+150
°C
Limits
Unit
VDD
Input Voltage
VI
Output Voltage
Vo
Power Dissipation
PD
Storage Temperature
Conditions
Tstg
Unit
OPERATING CONDITIONS
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
Fan Out
Symbol
Condition
f(OSC) :;; 1 MHz
VDD
VDDH
TOp
N
3-6
V
f(OSC) :;; 4.2MHz
4.5 -5.5
V
HOSC) =OHz
2-6
V
-40 -+85
°C
MOSLoad
15
TTL Load
1
-
193
• MSM6411 .'----------------------------------------------------
DC CHARACTERISTICS
(Voo = SV±1 0%, Ta = -40 - +8S 0 C)
Parameter
Symbol
Condition
Min.
Typ
Max.
Unit
"H" Input Voltage *1, *2
VIH
2.4
-
VOO
V
"H" Input Voltage *3, *4
VIH
3.6
-
VOO
V
"L" Input Voltage
VIL
-0.3
-
0.8
V
"H" Output Voltage *1, *5
VOH
10 = -1S/LA
4.2
-
-
V
"L" Output Voltage *1
VOL
10 = 1.6mA
-
-
0.4
V
"L" Output Voltage *5
VOL
10 = 1S/LA
-
-
0.4
V
"L" Output Voltage*6
VOL
lo=8mA
-
1
2
V
II~IlL
VI = VOO/OV
-
-
-15
~
/LA
I~IlL
VI =VOO/OV
-
-
Ao
/LA
Input Current *3
Input Current *2, '4
"H" Output Current '1
10H
Vo = 2.4V
-0.1
-
-
rnA
"H" Output Current '1
10H
Vo =O.4V
-
-
-1.2
rnA
-
5
-
-
7
-
VOD = 2V, no load
Ta= 25°C
-
0.2
5
/LA
No load
-
1
100
/LA
Crystal oscillation,
No load, 4.2MHz
-
6
12
rnA
Input Capacitance
Output Capacitance
Power Consumption
(STOP)
Power Consumption
CI
f = 1 MHz, Ta = 25°C
Co
IOOS
100
pF
'1 Applied to PO and P1 .
'2 Applied to P2.
'3 Applied to oseo
'4 Applied to RESET
*5 Applied to OSC1
'6 In using LEO, total output current should be within the limit of Power dissipitation in "Absolute Maximum
Rating."
194
------------------------------------------------------. MSM6411 •
AC CHARACTERISTICS
(VDD = 5V± 10%, Ta = -40 - +85°C)
Symbol
Condition
Min.
Typ
Max.
Unit
Clock (OSCo) Pulse Width
t,/)w
-
119
-
-
ns
Cycle Time
tCY
-
952
-
-
ns
Input Data Setup Time
tDS
-
120
-
-
ns
Input Data Hold Time
tDH
-
120
-
-
ns
Input Data/Input Clock
Pulse Width
tDW
-
120
-
-
ns
SR Clock Pulse Width
tsw
-
trJ1.W
-
-
ns
SR Data Setup Time
tss
-
120
-
-
ns
SR Data Hold Time
tSH
-
120
-
-
ns
Data Delay Time
tDR
CL =15pF
-
-
tCY
+300
ns
SR Data Delay Time'·
tSR
CL =15pF
-
-
tCY
+480
ns
SR Data Delay Time
Using External Clock
tsp
CL=15pF
-
-
360
ns
tSINH
-
2/8
tCY
-
-
ns
Parameter
SR Clock Invalid Time
, When SR clock is oscillated by alternate output of "1 " or "0" to P01 .
195
• MSM6411 ••----------------------------------------------------
TIMING CHART
~----------1MC--------------~
tCY
OSCO
PO, P1, P2
OStOH
PO,P1
tOR
P02/S0
tSR
P01/SCK
I~ r-lU
tsw tsw
Ir-
P03/SI
I--.
INPUli
OATA
~H
P02/S0
--.
X
tsp
P2
~-----------1MC--------------
OSCO
P01 SCK inhibit period
during LMSR INST.
196
--------------------------------------------------. MSM6411 •
TYP. Maximum Oscillator Frequency
f(OSC)
YS Supply Voltage
Ta=25°C
(VDD)
CL= 15pF
10
8
S
6
en
g
-0.9
-0.8
V
7
:r:
-1.0
v
9
"N
TYP. Current YS Voltage for High State Output
(lOH)
(VOH)
/
6
1/
5
-0.6
:r:
J
4
-0.7
<.s
9
-0.5
-0.4
3
-0.3
2
-0.2
1
-0.1
0
1
2
3
4
5
6
7
8
9 10
f' ""'- VDD =6V
t\.
r--... 5V \
1\
4V "'1\
r"'"
" 1\ r\,1\
t- ~
r\
2
0
,,
\
3
4
TYP. Maximum Oscillator Frequency
f(OSC)
YS Temperature
(Ta)
CL= 15pF
10
9
8
7
"N
:r:
S
6
en
g
-I--.
r-.... .......
20
16
r--.... ....
14
VDD=5V
<.s..J
5
7
8
9 10
VDD=5V
1 17
(/
12
7
10
I
r7
3
6
17
2
4
9
l.---"" ~
6VJ
8
4
6
TYP. Current YS Voltage for Low State Output
(lOL)
(VOL)
18
6
5
VOH(V)
VDD(V)
1...- 4V
~
3V
2
o
-40
0
40
80
120
-20
20
60
100
Ta(OC)
0
2
3
4
5
6
7
8
9 10
VOL (V)
197
• MSM6411 ••------------------------------------------------TYP. Supply Current vs Supply Voltage
(tOO)
(VOO)
Ta=25°C
No Load
10m
V
1...--"
HOSe) =4MHz
I
V
"V 1...--"
V
~~
I'
/
V
V
/
1m
./
100IL
V
2MHz
I
1001 MHz
I
500kHz
~
V
~lJ
/
5D
.fl
1 OIL
~
L,..0Hz
1IL
100n
V
o
1
/
2
V
V
3
4
5
VDD(V)
198
6
7
8
9
10
OKI
semiconductor
MSM6422
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6422 is a low power, high performance single-chip device implemented in
complementary metal oxide semiconductor technology.
Integrated onto a single chip are 16K bits of mask program ROM; 256 bits of data RAM; 18
Input/Output lines and oscillator. Program memory is byte wide and data-paths are organized in 4 bit
nibbles. RAM and 1/0 lines are bit addressable. 63 instructions include Binary, BCD operations; Bit
set, Reset, Test; Subroutine call and return.
FEATURES
•
•
•
•
•
•
•
•
Low power consumption - 30 mW Typical
2048 x 8 Internal ROM
64 x 4 Internal RAM
18 1/0 Lines include 8 Bit Data Bus
Self-contained Oscillator
63 Instructions
2 Interrupt Levels
16 Stack Levels
•
•
•
•
•
LED direct drive available (8mA x 5 ports at the
same time)
-40 to +85°C Operating Temperature
4.5 to 5.5V Operating VDD at 4.2 MHz
3 to 6V Operating VDD at 1 MHz
TTL Compatible
952ns Cycle Time @ 4.2MHz
(VDD 5V ±1 0%)
FUNCTIONAL BLOCK DIAGRAM
ROM
2048x8
10
3210
wjffi
3210
3210
~
Timing
&
I
1111
3210
,.
0
I
N
T
12b;nBC
tt
GV
NO
DO
l+-
Control
i1
1
S S
C C
S
00
1 0
R
E
E
T
199
eMSM6422.e------------------------------------------------LOGIC SYMBOL
(Top View)
24 PIN PLASTIC DIP (RS)
24 PIN FLAT PACKAGE
Voo
P5'
o
P43
P33
P32
P3'
P30
PIN DESCRIPTION
Terminal symbol
Input/Output
Function
Reset
POO
P01
P02
P03
I/O
4-bit I/O ports
(pseudo bidirectional
configuration)
"1 "
P10
P11
P12
P13
I/O
4-bit I/O ports
(pseudo bidirectional
configuration)
"1 "
P30
P31
P32
P33
110
4-bit I/O ports
(pseudo bidirectional
configu ration)
"1 "
P40
P41
P42
P43
I/O
4-bit I/O ports
(pseudo bidirectional
configuration)
"0"
P50
P51
I/O
2-bit I/O ports
(pseudo bidirectional
configuration)
110"
P20/INT
Input
1-bit input port with a latch.
Combined use with an
interrupt input(falling edge
trigger input)
The latch is
reset to "0"
OSCo
Input
System clock (SYSCLK)
input terminal. This provides
an oscillation circle with
OSC, terminal.
-
Output
System clock output
terminal. This provides an
oscillation circle with
OSCoterminal.
-
RESET
Input
RESET input terminal.
-
VDD
GND
Input
Power Supply terminals.
-
OSC,
200
------------------------------------------------------. MSM6422 •
FUNCTIONAL DESCRIPTION
Program ROM
Organized into as many as 2,048 words by 8
bits, ROM is used to store developed application
programs (instructions). It is addressed by the
program counter (PC).
Data RAM
RAM consists of up to 64 words 4 bits wide. It
is addressed by the H- and L-registers or by the
contents of the second byte of an instruction.
Input/Output Ports
18 input/output port lines are provided for
effecting and controlling data transfer to and
from an external source. The ports are selected
by codes included in instructions.
P20/lNT PIN (1 line)
A low on this interrupt input pin sets the
interrupt request flag. The flag is automatically
reset when an external interrupt occurs.
The line can be used as an input port when
interrupt is not used.
12-BIT TIME BASE COUNTER (TBC)
The time base counter consists of a 12-bit
binary counter. An interrupt request is generated
each time an overflow occurs from the division of
OSCD input signals by 2'2.
PROGRAM COUNTER (PC)
The program counter (PC) consists of a
11-bit binary up counter. It is used to address
ROM.
STACK AND STACK POINTER (SP)
An interrupt or subroutine call (CAL) causes
the contents of the program counter to be saved
in the stack. The program counter is restored
from the stack by the RT instruction.
All RAM locations (up to 16 levels) are
available as the stack. Note that four words of
RAM are used for each level.
The stack pointer is a 4-bit up-down counter
that points to the address of the next stack to be
used. It allows the RAM locations to be used as a
push-down stack.
L-REGISTER
A 4-bit register which specifies RAM locations A3-AO.
H-REGISTER
A 4-bit register whose two low-order bits
specify RAM locations A5-A4.
ALU
The 4-bit logic circuit that provides arithmetic
and logical operations.
ACCUMULATOR (Ace)
Consisting of a 4-bit register, the accumulator holds the result of operations or the data
present on ports.
C-FLAG
The flag that holds a carry generated from the
result of operations.
TIMING CONTROL (TC)
A 0 level on the RESET pin for longer than a
predetermined period initializes the internal
circuitry and ports.
Clock pulses are supplied to the OSC D pin
from an external source. A crystal or ceramic
oscillator may be connected to OSCD and OSC ,
to form an oscillator circuit to produce clock
pulses.
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
Limits
-0.3 -7
V
Ta = 25°C
-0.3 -VDD
V
-0.3 -VDD
V
Ta = 25°C
per one package
200 max.
mW
Ta = 25°C
per one output
50 max.
mW
-55 - +150
°C
VDD
Input Voltage
VI
Output Voltage
Va
Power Dissipation
PD
Storage Temperature
Conditions
Tstg
--
Unit
201
• MSM6422 ••----------------------------------------------------
OPERATING CONDITIONS
Parameter
Symbol
Condition
Limits
Unit
3-6
V
4.5 -5.5
V
HOSC) ~ 1 MHz
Supply Voltage
VOO
Memory-Hold Voltage
Operating Temperature
HOSC) ~ 4.2MHz
VOOH
-
2-6
V
TOp
-
-40 - +85
°C
MOS Load
15
-
TTL Load
1
-
Fan Out
N
DC CHARACTERISTICS
(Voo = 5V± 10%, Ta = -40 - +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage *1, *2
VIH
-
2.4
-
VOO
V
"H" Input Voltage *3, *4
VIH
-
4.2
-
VOO
V
"L" Input Voltage
VIL
-
-0.3
-
0.8
V
"H" Output Voltage *1, *5
VOH
10 = -15/LA
4.2
-
-
V
"L" Output Voltage *1
VOL
10 = 1.6mA
-
-
0.4
V
"L" Output Voltage *5
VOL
10 = 15/LA
-
-
0.4
V
"L" Output Voltage'6
VOL
lo=8mA
-
1
2
V
IIH/
IlL
VI =VOO/OV
-
-
1~
-15
/LA
II~
VI =VOO/OV
-
-
Input Current *3
Input Current *2, *4
IlL
hO /LA
"H" Output Current *1
10H
Vo = 2.4V
-0.1
-
-
mA
"H" Output Current *1
10H
Vo =O.4V
-
-
-1.2
mA
-
5
-
-
7
-
VOO = 2V, no load
Ta= 25°C
-
0.2
5
/LA
No load
-
1
100
/LA
Crystal oscillation,
No load, 4.194304MHz
-
6
12
mA
Input Capacity
CI
f = 1 MHz, Ta = 25°C
Output Capacity
Current Consumption
(STOP)
Current Consumption
Co
IOOS
100
pF
*1 Applied to PO, P1, P3, P4, and P5
*2 Applied to P2
*3 Applied to OSC o
*4 Applied to RESET
*5 Applied to OSC,
'6 In using LED. total output current should be within the limit of Power dissipitation in "Absolute Maximum
Rating."
202
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6422 •
AC CHARACTERISTICS
(VDD = 5V±1 0%, Ta = -40 - +85°C)
Symbol
Condition
Min.
Typ.
Max.
Unit
Clock (OSCo) Pulse Width
tcf>W
-
119
-
-
ns
Cycle Time
tCY
-
952
-
-
ns
Input Data Setup Time
tDS
-
120
-
-
ns
Input Data Hold Time
tDH
-
120
-
-
ns
Input Data/Input Clock
Pulse Width
tDW
-
120
-
-
ns
Data Delay Time
tDR
CL =15pF
-
-
tCY +300
ns
Parameter
1 MC
tCY
PO,P"P3
P.,P.
PO,P " P3
P",P.
-I.
-J,---
-tDR
203
eMSM6422e---------------------------------------------------INSTRUCTION SET
Hex op code
Byte
Cycle
LAI
n
90-9F
1
1
Acc-n
LLI
n
SO-SF
1
1
L-n
LAL
21
1
1
Acc-L
LLA
20
1
1
L-Acc
LAH
22
1
1
Acc-H
LHA
2E
1
1
H-Acc
LAM
3S
1
1
Acc-M
LMA
2F
1
1
M-Acc
X
2S
1
1
Acc-M
14-nn
2
2
M(W)-nn
Mnemonic
"0
os
0
...J
e"E
0
()
-
.....I :
I:Q)
Q)E
EQ)
Q) ...
"'0
0Q)
-="0
LMI
nn
LHLI
nn
15-nn
2
2
HL-nn
LAMO
mm
10-mm
2
2
Acc-Md
LMAO
mm
11 -mm
2
2
Md-Acc
IPO
p
30-pO
2
2
Acc-Pp
OPO
p
30-pC
2
2
Pp-Acc
MEl
3E-60
2
2
MEIF-"1"
MOl
3E-61
2
2
MEIF-"O"
EIEX
30-CS
2
2
EIEXF-"1"
EITB
30-C9
2
2
EITBF -"1"
OIEX
30-C4
2
2
EIEXF-"O"
OITB
30-C5
2
2
EITBF-"O"
TIEX
30-CO
2
2
SKIP IF EIEXF="1 "
TITB
30-C1
2
2
SKIP IF EITBF="1 "
TQEX
30-20
2
2
SKIP IF IRQEX="1"
TQTB
30-00
2
2
SKIP IF IRQTB="1 "
RQEX
30-24
2
2
IRQEX-"O"
RQTB
30-04
2
2
IRQTB-"O"
INL
31
1
1
L - L+ 1, SKIP IF L="O"
INH
32
1
1
H - H+ 1, SKIP IF H="O"
INM
33
1
1
M - M+1, SKIP IF M="O"
OCL
35
1
1
L - L-1, SKIP LF L="F"
OCH
36
1
1
H - H-1, SKIP IF H="F"
OCM
37
1
1
M - M-1, SKIP IF M="F"
12-mm
2
2
Md-Md+1,
SKIP IF Md="O"
INMO
204
Oescription
mm
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6422 •
INSTRUCTION SET (CONT.)
Mnemonic
Hex op code
Byte
Cycle
Description
TAB
n2
54 -57
1
1
SKIP IF (Acc-Bit n2) = "1"
TMB
n2
58 -5B
1
1
SKIP IF (M-Bit n2) = "1"
RMB
n2
68 -6B
1
1
(M-Bit n2) - "0"
.s
5MB
n2
78-7B
1
1
(M-Bit n2) - "1 "
c:
TPBDp
n2
3D ·pO-3
2
2
SKIP IF (Pp-Bit n2) = "1 "
RPBDp n2
3D·p4-7
2
2
(Pp-Bit n2) - "0"
SPBDp
3D·p8-B
2
2
(Pp-Bit n2) - "1"
TC
09
1
1
SKIP IFC = "1"
RC
08
1
1
C-"O"
SC
07
1
1
C-"1"
ADS
02
1
1
Acc -Acc+M,
SKIP IF Cy="1 "
ADC
03
1
1
C, Acc - C+Acc+M
3E·4n
2
2
Acc-Acc+n,
SKIP IF Cy="1 "
DAS
OA
1
1
Acc -Acc+10
AND
00
1
1
Acc-AccAM
OR
05
1
1
Acc-AccVM
EOR
04
1
1
Acc-Acc'v'M
CMA
OB
1
1
AcC-Ace
Cl
15
lIS
.s:::
iii
AIS
()
:;
E
.s:::
==...
«
n2
n
CAM
16
1
1
SKIP IF Acc=M
3E·On
2
2
SKIP IF Acc=n
OE
1
1
a6
CO-FF
1
1
PC-a6
JP
a11
40-47
00 - FF
2
2
PC -a11
CAL
a11
AO-A7
00- FF
2
4
STACK - PC+2, PC-a11,
SP-SP-1
RT
1E
1
4
PC - STACK, SP - SP+ 1
PUSH
1C
1
3
STACK - PC+2, PC-a11,
SP-SP-1
POP
10
1
3
C, Acc, H, L - STACK,
SP-SP+1
STOP
3D·B9
2
2
CLOCK STOP
NOP
00
1
1
NO OPERATION
CAl
n
RAL
JCP
.s:::
()
c:
~
m
III
Q;
.s:::
0
,.-Acc----,.
[C-3-2-1-Q-,
205
• MSM6422 .---------------------------------------------------TYP. Current (lOH) vs Voltage (VOH)
for High state Output
-1.0
-0.9
-0.8
l- f.....
-0.7
~-0.6
'i-0 .5
.9-0.4
l-
"
i\:
o
N~
"
\
rl
r/
1\ \
\
\
./
6
4
2
1\
1 2 3 4 5 6 7 8 9 10
VOH(V)
TYP. Maximum Oscillator Frequency
f(OSC) vs Supply Voltage (VD)
o
~
N
7
~
6
5
J:
0
en
.9
I - 3V
1 2 3 4 5 6 7 8 9 10
VOL (V)
V
1m
II
5001'
I
o
o
4V
(Ta = 25°C. No Load)
II
4
./" ~
~
j
3
2
VOO=5V
10m
5m
/
8
---
TYP. Supply Current (lDD)
vs Supply Voltage (VDD)
(Ta = 25°C. CL = 15pF)
10
9
/'
1//
.9 8
\
\
I
I
6V
16
14
<12
E
-:'10
VOO=6V
I - 4V
-0.1
o
20
18
,5V
-0.3
-0.2 k
TYP. Current (lod vs Voltage (VOL)
for Low state Output
-
HOSC) 4M Hz
2MHz- f1MHz
500kHz==:
100kHz
1 2 3 4 5 6 7 8 9 10
VOo(V)
./ OHz
TYP. Maximum Oscillator Frequency
f(OSC) vs Temperature (Ta)
(Voo=5V. CL = 15pF)
10
N
J:
~
0
en
.9
100n
I"
9
"'-
8
7
6
r-....
5
4
3
2
1
o
-40 -20 0 20 40 6080 100120
Ta(OC)
206
o
1 2 3 4 5 6 7 8 9 10
VOo(V)
OKI
semiconductor
MSM6442
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM6442 is a low power, high performance single chip device implemented in
complementary metal oxide semiconductor technology with 46 segment outputs and 2 commons.
Also integrated onto this chip are 16K bits mask program ROM, 512 bits of data RAM, 28
Input/Output lines and oscillator. 71 instructions include binary, BCD, logical operations; bit set,
reset, test; subroutine call and return.
FEATURES
• Low Power Consumption 30mW (typ)
• 2048 x 8 Internal ROM
• 128 x 4 Internal RAM
• Two built-in counters
1 2-bit time-base counter
8-bit programable timer/event counter
• 16 Input/Output Ports and 46 LCD
Output Port and 2 Common Output
(1/2 Outy, 1/2 Bias)
• LEO direct drive available
• Self-contained Oscillator
• 71 Instructions
• 4 Interrupt Levels
• 1 6 Stack Levels
• -40 to +85°C Operating Temperature
• 4.5 to 5.5V Operating VOD at 4.2 MHz
3.0 to 6.0V Operating VOD at 1 MHz
• TTL Compatible
FUNCTIONAL BLOCK DIAGRAM
RAM
OSCo
OSC,
TEST1
TEST2
RESOUT
i I COM2
I
LCDGND
VM
SEG46
COM1
SEG1
- - - VDD
--GND
XT
XT
TEST3
BZ
INT
INOUT
32 1 0
CIN
207
• MSM6442·--------------------------------------------------LOGIC SYMBOL
PIN CONFIGURATION (TOP VIEW)
5V
OV
$7
sa
59
RESET INPUT
RESET OUTPUT
$W
."
$"
$>'
TEST
CLOCK
[
lCDCLOCK
C
$'4
$>5
$16
SH
$18
$19
$20
INTERRUPT INPUT
INTERRUPT OUTPUT
SUZZER OUTPUT
$21
$22
$23
SEG
PORT3
$24
$25
$26
$27
528
$29
$30
$31
$3,
$33
$3<
$35
$36
$37
$38
$39
$<0
...8<,
8<1
$42
$<3
$<5
PIN DESCRIPTION
Terminal
POO -P03
P10 -P13
Input!
Output
Input!
Output
INT
"1 "
I/O port
"0"
LCD output port (can be assigned to data
output in 4 bit wide)
LCD output port
"O'l.
Output'
Output'
LCD common output terminal 1
LCD common output terminal 2
Input
Input port of external interrupt
SEG17 -SEG46
INTOUT
(P10 and count input CIN are in
common)
Input!
Output
SEG1 -SEG16
COM1
COM2
1/0 port
1/0 port
When
reset
1/0 port
P30 -P33
P40 -P43
Function
Output
Interrupt output port
Reset input port
RESET
"0"*
"1 "
-
RESET OUT
Output
Reset output terminal
"1 "
BZ
Output
Buzzer pulse output port in 2048 KHz
"0"*
OSCo
OSC,
Input!
Output
Crystal OSC or ceramic OSC connection
Crystal OSC or ceramic OSC connection
(System clock)
-
XT
XT
Input!
Output
32.768 kHz crystal oscillator connection
(use for LCD control)
-
-
TEST terminal 1 (open) (Connected to VOO)
TEST terminal 2 (open)
TEST terminal 3 (open)
TEST 1
TEST 2
TEST 3
VOO
VLCD GND
VM
GNO
Input
Power supply (5V)
-
Input
Power supply for LCO
-
Input!
Output
Input
(VOO-VLCO)/2 supply voltage output
or supply voltage input
Power supply (OV)
'''a'' indicates the LCD GND voltage level
208
"0"*
-
-----------------------------------------------------eMSM6442e
ELECTRIC CHARACTERISTICS
• Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
VDD
Input Voltage
VI
Output Voltage
Vo
LCD Voltage
Storage Temperature
Conditions
Ta = 25°C
Limits
Unit
-0.3 - 7
V
-0.3 - VDD
V
-0.3 - VDD
V
VOD -9 - VDD
V
Tstg
-
-55 - +150
°c
Symbol
Conditions
Limits
Unit
LCDGND
• Operating Conditions
Parameter
Supply Voltage
LCD Voltage
Memory Retension Voltage
Operating Temperature
LCD Clock
Oscillation Frequency
Fan Out ( 1/0 Pord
f (OSC) ~ 1 MHz
3-6
V
f (OSC) ~ 4.2MHz
4.5 - 5.5
V
LCDGND
*1
VDD -8 - 0
V
VDOH
Oscillation off
2-6
V
Top
-
-40 - +85
°c
VDD
f(XT)
N
*2
32.768
kHz
MOS Load
15
-
TTL Load
1
-
*1 Voltage applied to LCD is (DD-VLCD).
*2 Oscillation Circuit for LCD Clock (XT, XT Port) is for Christal Oscillation only.
209
/
eMSM6442e----------------------------------------------------DC CHARACTERISTICS
(VDD = 5V ±10%, LDCGND = OV, Ta = -40 - +85°C)
Parameter
Symbol
Condition
'1. INT
"H" Input Voltage
'3.
VIL
'1. OSC1
10
'2.
10
VOH
SEG1-SEG46
10
COM1, COM2
10
'1, '2
10
OSC1
"L" Output
Voltage
10
VOL
SEG1-SEG46
10
COM1, COM2
"M" Output
Voltage
TYP
COM1, COM2
-
2.4
-
10
YOM
= -15/LA
= -4oo~
= -10/LA
= -50/LA
= 1.6mA
= 15mA
= 10/LA
= 50/LA
10 ±0.5
OSCO
"H" Input Current XT
"L" Input Current
IIH
VI= VDD
'1
'2
'3
'4
Note:
210
-
VDD
V
3.6
-
VDD
V
0
-
0.8
V
4.2
-
-
'(J
2.4
-
-
V
Voo-O.2
-
-
V
Voo-0.2
-
-
V
-
-
0.4
V
-
-
0.4
V
-
-
0.2
V
-
-
0.2
V
-
VOO/2rO.2
V
-
-
15
/LA
-
-
7
/LA
VOO/2 0.2
INT, RESET
-
-
1
/LA
-
-
-15
/LA
-
-
7
/LA
-
-
-30
/LA
VO
-0.1
-
-
mA
VO
-
-
-1.2
mA
No load
Display 011
XT Port is fixed to "L"
-
0.2
10
/LA
Display 011
XT Port is fixed to "L"
-
1
100
/LA
-
100
200
/LA
-
6
12
mA
XT
IlL
'1
10H
Current
Consumption
-at stop mode
-no oscillation
IDDS
Current
Consumption
-at stop mode
IDDL
Current
Consumption
IDD
Applied
Applied
Applied
Applied
Unit
OSCO
VI = OV
INT, RESET
"H" Output
Current
MAX
VIH
"L" Input Voltage '1. '4
"H" Output
Voltage
MIN
= 2.4V
= 0.4V
Voo = 2V, TA = 25°C
No load
Display off
At stop mode
f(XT) = 32.768 KHz
No load
Display 011
f(osc) = 4.2 MHz
f(XT) = 32.768 KHz
to PO, P1, P2, and P4.
to ifilTrnIT, RESET, and BZ.
to OSCO, XT, and RESET.
to XT, INT, and RESET.
"M" output voltage is intermediate voltage of the output from common port at dynamic display.
-----------------------------------------------------eMSM&M2e
AC CHARACTERISTICS
(VDD = 5V ±10%, Ta = -40 - +85°)
Parameter
Symbol
Condition
MIN
TYP
MAX
Unit
Clock (OSc,,) Pulse Width
tow
-
119
-
-
nS
Cycle Time
tcv
-
952
-
-
nS
Input Data Set-up Time
t08
-
120
-
-
nS
Input Data Hold Time
tDH
Note 1
120
-
-
nS
INT Input Data Pulse Width
tDWl
-
120
-
-
nS
CT Clock Pulse Width
tDW2
-
2IStcY7120
-
-
nS
Data Delay Time
tDR
C L = 15pF
-
-
300
nS
Reset Input Pulse Width
twRS
Note 2
2tcy
-
-
nS
Note 1*
Note 2*
To release powerdown by inputting "L" level into INT Port, pulse width should be longer than the
time for the oscillation stabilization at OSc".
The condition of stable oscillation. To release powerdown by reset, pulse width should be longer
than the time for oscillation stabilization at OSc".
211
0
I
/
·M~·-----------------------------------------------
TIMING CHART
OSCo
~
tcy
OSCo
PO, P1,
P3, P4
~
OSCo
PO, P1,
P3, P4
~
I
I·
~
tOR
OUTPUT DATA
If
J
tOW1
,
----,
P10/CIN
1\
tOW2
tOW2
v-----
~
tWRS
2"12
-----------------------------------------------------eMSM&W2e
OUTPUT WAVE FORM OF LCD RIVER
STATIC MODE
------ VDD
COM1, COM2
t - - - - VCDGND
------- VDD
SEGn
(n = 1~46)
t - - - - LCDGND
------ VDD-LCDGND
COM1~SEGn
~------------4------0
COM2~SEGn --~
DISPLAY
OFF
ON
OFF
------- -(VDD-LCDGND)
DISPLAY
OFF
DYNAMIC MODE
VDD
- --VM
--LCDGND
COM1
COM2
VDD
SEGn
(n =
1~46)
-- LCDGND
COM1~SEGn
----- ------------- VDD-LCDGND
------- VM-LCDGND
___+_+
o
---- -(VM-LCDGND)
----------- -(VDD-LCDGND)
OFF
DISPLAY
OFF
----- VDD-LCDGND
-- VM-LCDGND
COM2~SEGn
--+
DISPLAY
OFF
- -- 0
-(VM-LCDGND)
--- -(VDD-LCDGND)
ON
OFF
eMSM6442e------------------------------------------------FUNCTIONAL DESCRIPTION
ROM
Organized into 2048 words by 8 bits, ROM
is used to store developed application programs
(instructions). It is addressed by the program
counter (PC).
PROGRAM COUNTER (PC)
The program counter consists of a 11-bit
binary counter. It is used to address ROM.
STACK
An interrupt or CAL instruction causes the
contents of the PC to be saved in the stack. Also,
the PUSH instruction causes the contents of
accumulator, carry-flag, H- and L-register to be
saved in it. These are allowed to be restored by
the RT instruction or POP instruction.
RAM
Organized into 128 words of 4 bits, RAM is
addressed by the H- and L-register or the contents of the second byte of an instruction.
L-REGISTER
A 4-bit register which specifies the row
address of RAM and the port-address in the port
operation instructions. It is also used as a
working register.
H-REGISTER
A 4-bit register which specifies the column
address of RAM and is used as a working
register.
ALU
A 4-bit logic circuit which provides
arithmetic and logical operations.
ACCUMULATOR (ACL)
Consisting of a 4-bit register, the
accumulator holds the result of operations or the
date present on ports.
C-FLAG
The flag that holds a carry generated from
the result of operations.
INPUT/OUTPUT Ports (16 bits)
16 input/output ports are provided for
effecting and controlling data transfer to and
from an external source. The ports are selected
by codes included in the instructions.
12-bit TIME-BASE COUNTER
The time base counter consists of a 12-bit
binary counter. It is used to devide the frequency
of the OSCo input by 2'2 and. generate the
. ·~.r'lpt request at every over-flow signal.
8-bit TIMER EVENT COUNTER
The timer event counter consists of a 8-bit
counter (8-bit) register, comparing and
controlling circuits. It is used to count pulses of
an internal or external source. Coincidently, if
value between the counter and the register
causes interrupt request occur.
LCD DRIVER
The LCD driver is used to effect LCD display
by transferring data in a program to the register
assigned as port 5 and 6. It is available to_select
driving in static or dynamic operation (1/2 duty
cycle) and frame frequency (128 Hz/64 Hz) and
to drive up to 92 segments at 1/2 duty. Also, 16
outputs(SEG 1-SEG 16)of the segment terminals
can be used as normal data outputs.
A standard LCD clock is produced by the
oscillation dividing a crystal oscillator (32.768
kHz) connected to XT and XT terminals. This is
also used as standard clock of displaying, clock
interrupting and watch dog timer. (This clock can
be also produced by dividing a frequency of
4.194304 MHz. Note the selection of the frame
frequency, when the crystal oscillator is used
without a frequency of 4.194304 MHz.)
INTERRUPT
As shown below, 1 - 4 is available to interrupt;
1. External interrupt at the falling edge of INT
signal input
2. Clock interrupt at every second (32.768 kHz
crystal- oscillator)
3. Time base counter interrupt at the occurance
of an overflow of the timer base counter.
4. Timer event counter interrupt coinciding
between the signals of the 8-bit counter and
register.
Interrupts 1 and 2 are also used to release the
power down mode.
WATCH DOG TIMER (WDT)
A timer for detecting the overrunning of the
program. This timer produces the overflow signal
by dividing the 64 Hz frequency by 4 generated
from the oscillation of a frequency of 32.768
kHz. It can be also halted, when unused.
TIMING CONTROL (T.C)
A 0 level on the RESET pin for longer than
predetermined period initializes the internal
circuitry and ports.
Clock pulses are supplied to the OSCo pin
from an external source. A crystal or ceramic
oscillator may be connected to OSCo and OSC 1
to form an oscillator circuit to produce clock
pulses.
----------------------------------------------------'. MSM6442 •
INSTRUCTION SET
Mnemonic
-0
as
0
....I
Cycle
Description
n
90-9F
1
1
Acc-n
LLI
n
80-8F
1
1
L-n
LAL
21
1
1
Acc-L
LLA
2D
1
1
L-Acc
LAH
22
1
1
Acc-H
LHA
2E
1
1
H -Acc
LAM
38
1
1
Acc-M
LMA
2F
1
1
M-Acc
X
nn
28
1
1
Acc - M
14·nn
2
2
M(W) -nn
LHLI
nn
15·nn
2
2
HL-nn
LAMD
mm
10·mm
2
2
Acc -Md
LMAD
mm
11 ·mm
2
2
Md-Acc
3E·59
2
2
M(W)-CT
LMCT
3E·51
2
2
CT-M(W)
IPD
p
3D·pO
2
2
Acc -Pp
OPO
P
30·pC
2
2
Pp -Acc
3E·60
2
2
MEIF -"1"
LCTM
MEl
C
0
u
Byte
LAI
LMI
"0
...
Hexopcode
MOl
3E·61
2
2
MEIF-"O"
EIEX
30·C8
2
2
EIEXF-"1"
EICT
30·CB
2
2
EICTF-"1"
DIEX
30·C4
2
2
EIEXF-"O"
DICT
30·C7
2
2
EICTF-"O"
TIEX
30·CO
2
2
SKIP IF EIEXF="1 "
TICT
3D·C3
2
2
SKIP IF EICTF="1 "
TQEX
30·20
2
2
SKIP IF IRQEX="1 "
TQCT
30·D2
2
2
SKIP IF IRQCT ="1 "
RQEX
3D·24
2
2
IRQEX-"O"
RQCT
3D·D6
2
2
IRQCT -"0"
INL
31
1
1
L - L+ 1, SKIP IF L="O"
INH
32
1
1
H - H+1, SKIP IF H="O"
INM
33
1
1
M - M+ 1, SKIP IF M="O"
O)E
EO)
0) ...
DCL
35
1
1
L - L-1, SKIP IF L="F"
"'0
00)
DCH
36
1
1
H - H-1, SKIP IF H="F"
,-",
"'0)
':-0
DCM
INMD
mm
37
1
1
M - M-1, SKIP IF M="M"
12·mm
2
2
Md - Md+1, SKIP IF
Md="O"
• MSM6442 .----------------------------------------------------
INSTRUCTION SET (CO NT.)
Mnemonic
TAB
TPB
RPB
SPB
Hex op code
Byte
Cycle
n2
54 - 57
1
1
SKIP IF (ACC-Bit n2) = "1"
Description
n2
50-53
1
1
SKIP IF (P-Bit n2) = "1"
n2
60-63
1
1
(P-Bit n2) - "0"
n2
70 -73
1
1
(P-Bit n2) - "·i "
TMB
n2
58-5B
1
1
SKIP IF (M-Bit n2) = "1"
.s
RMB
n2
68-6B
1
1
(M-Bit n2) - "0"
as
5MB
n2
78-7B
1
1
(M-Bit n2) - "1"
Cl
=cc
.J::
iii
TPBOp
n2
30·pO-3
2
2
SKIP IF (Pp-Bit n2) = "1"
RPBOp
n2
30·p4-7
2
2
(Pp-Bit n2) - "0"
SPBOp
n2
3D ·p8-B
2
2
(Pp-Bit n2) - "1"
TC
09
1
1
SKIP IF C = "1"
RC
08
1
1
C-"O"
SC
07
1
1
C-"1"
ADS
02
1
1
Acc - Acc+M, SKIP IF
Cy="1"
AOC
03
1
1
C, Acc - C+Acc+M
3E·4n
2
2
Acc - Acc+n, SKIP IF
Cy="1"
OAS
OA
1
1
Acc -Acc+10
AND
00
1
1
Acc -AccAM
1
Acc -AccVM
AIS
u
~
n
E
OR
05
1
~
EOR
04
1
1
Acc -AccVM
CMA
08
1
1
Acc -Acc
CAM
16
1
1
SKIP IF Acc=M
3E·On
2
2
SKIP IF Acc=n
OE
1
1
a6
CO - FF
1
1
PC-a6
JP
all
40 47
00 - FF
2
2
PC - a11
CAL
a11
AO A7
00 - FF
2
4
STACK - PC+2,
PC-a11, SP-SP-1
RT
lE
1
4
PC -STACK, SP -SP+1
PUSH
1C
1
3
STACK - C, Acc, H, L,
SP-SP-1
POP
10
1
3
C, Acc, H, L - STACK,
SP-SP+1
STOP
30·B9
2
2
CLOCK STOP
NOP
00
1
1
NO OPERATION
ECT
3D·BB
2
2
CTF - "1" (Counter Start)
OCT
3D·B7
2
2
CTF - "0" (Counter Stop)
TCT
3D·B3
2
2
Skip if CTF
:5
CAl
n
,--Acc~
RAL
JCP
.J::
u
c
~
en
'"
(j;
.s::
(5
[C - 3-2-1-0,
='
"1"
OKI
semiconductor
MSC6458
OKI 4-BIT 1-CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The MSC6458 is a high-speed, 4-bit 1-chip microcontroller with built-in FLT drivers/controllers developed
to support relatively large control systems.
FEATURES
• ROM: 8000 x 8 bits
• RAM: 512 x 4 bits
• Ports: I/O 24 ports (8 having 10L = 20 mAl
Input 9 (2 also serving as interrupt inputs)
• FLT drivers (Withstand 12 (IOH = 2OmA)
voltage 4OV):
12 (IOH = 6mA)
• LED direct drive available
• Interrupts: 7 lines (2 external, 5 internal)
• Built-in counters: 12 bits, timebase counter
16 bits, programmable counter
8 bits, high-speed
programmable timer/event
counter
•
•
•
•
•
Serial I/O: Built-in 8-bit SIO register
Oscillation circuit: Crystal or ceramic oscillation
Number of instructions: 147
Cycle time: 930 ns ( 4.3MHz)
Operating ranges: 4.5 to 5.5V ( 4.3MHz)
Voltage: 3.0 to 6.0V (1 MHz)
Temperature: -40 to +85°C
• Power dissipation (typical)
(display off): 9mA ( 5V, 4.3MHz)
2mA (3V, 1MHz)
• Power down: STOP instruction
•
Package: 64-pin shrink DlP/64- pin FLAT
BLOCK DIAGRAM
Vfl.T
10
T1
,
Tl1
SEGO
SEGl
osc"
-OSCI
SEG11
-TEST
L - _ - - . J - RESEi
-voo
-GND
3m
2113210
3210 3210 3210
217
• MSC6458 • - - - - - - - - - - - - - - - - - - - - - - - - -
LOGIC SYMBOL
PIN CONFIGURATION (TOP VIEW)
64 PIN PLASTIC ru:~ 0
SHRINK DIP
RESET
TEST
5V
OV
fLTPower
PORn [
J
PORT2(
'7"''''
1110"',
I ] forFLT
g"m,otD,,,,'
---_.-
=
PIN DESCRIPTION
Terminal
Input!
Output
Function
port
_
port (also used as serial clock input SCK)
port (also used as serial data output SO)
port (also serial data input SI)
POO
P01/SCK
P02/S0
P03/S1
Input!
Output
1/0
1/0
1/0
1/0
P10/CIN
P11 ITMO
P12/TCK
P13
Input!
Output
1/0 port (also used as count input GiN)
1/0 port (also used as timer output TMO)
1/0 port (also used timer clock input TCK)
1/0 port
P20/lNTO
P22/1NT1
Input
Input Port with Latch (falling edge sensitive)
also used as interrupt input INTO
Input Port with Latch ('0' level sensitive)
also used as interrupt input INT1
When
reset
"1 "
"1 "
-
P30 -P33
Input!
Output
1/0 port
"1 "
P60 -P63
Input!
Output
1/0 port
uO"
P40 - P43
P50 -P53
Outputl
Input
1/0 port (lOL =20mA MAX)
"0"
P70 - P72
P80 -P83
Input
Input port with pull down register
Pull down register of P70 - P72 can be removed
by instruction
SEGO -SEG11
Output
FLT segment driver (dynamic)
"0"
T11/SEG12
- T8/SEG15
Output
FLT segment driver (dynamic)/Timing output
"0"
T7/0UT7
-TOIOUTO
Output
FLT segment driver (static)/Timing output
"0"
OSCO
OSC1
Input!
Output
Crystal connection terminal for system clock
oscillation
-
RESET
Input
System reset input
-
TEST
Output
Test pin (Open)
-
VFLT
Input
Power supply for FLT driving
-
VDD
GND
Input
System Power Supply
-
218
- - - - - - - - - - - - - - - - - - - - - - - . MSC6458 •
FUNCTIONAL DESCRIPTION
1. ROM
The ROM, organized in 8 bits, has a
maximum capacity of 8000 bytes.
2. RAM
The RAM is organized in 4 bits per word,
with a capacity of 512 words.
It is separated into two banks each 256
words long. Bank selection is accomplished via
internal ports. The RAM location in the banks is
addressed by the Hand L registers or by the
second byte of each instruction.
3. Ports (24 1/0,7 input)
The 24 pseudo-bidirectional I/O ports effect
or control the exchange of data with external
sources. The ports are specified by the L
register or by codes contained in instructions.
Ports 4 and 5 may draw 10L up to 20mA.
The seven input ports have built-in pulldown
resistors. Up to 84 keys can be scanned by
assembling them in key matrices with the timing
outputs of the FL T drivers (with 1 2 segments x
12 timings on display; also during automatic
display).
4. Interrupt Input Pins (2 terminals)
The il\rFO/P20 and INT1/P22 pins are
interrupt input pins. External interrupt request
flags of INTO/P20 pin and INT1/P22 pin can be
set by using interrupt input pins:
INTO/P20 pin ... positive edge or negative edge
input.
INT1 /P22 pin ... "0" level input.
These flags are automatically reset when
the appropriate external interrupts occur. These
pins are available for use as input ports when not
used as interrupt input pins.
5. FL T Drivers/Controllers (Automatic Display)
The FL T drivers have a withstand voltage of
40V in the positive direction from the GND level.
They comprise 12 ports that can draw 20m A as
10H (Timing outputs) and 12 ports that can draw
6mA as such (Segment outputs).
A choice of four display modes is supported
as listed below. A display RAM area is allocated
as part of the RAM space. Data is automatically
displayed when transferred to the display RAM.
(Two different display frequencies are
selectable.) Static output data can be displayed
by controlling the FL T drivers by programming.
Display modes (@4.194304 MHz)
(1) 12 Segments x 12 Timings
1/12 duty (85.3/341 .3 Hz)
(2) 16 Segments x 8 Timings
1/8 duty (128/512 Hz)
(3) 16 Segments 4 Timings +4 output'
1/4 duty (256/1 024Hz)
(4) 16 Segments+8 output'
Program controlled
'output: static outputs
x
6. Stack (STACK) and Stack Pointer (SP)
The PC is saved in the stack when an
interrupt occurs or a CAL instruction is
executed. It is recovered by the execution of an
RT instruction.
One fourth of the RAM space (128 words
maximum, 32 levels) is available as a stack area.
A 4-word RAM area is used for "one" level in the
stack.
The stack pOinter is an 8-bit up-down
counter (the MSB and 2 bits from LSB being
fixed at '1') indicating the next stack address to
use. It enables the RAM space to be used as a
pushdown stack. Data can also be transferred
between stack pointer and the H/L registers.
7. Interrupts
Seven interrupt lines are provided for eight
sources and eight levels of interrupts as follows
(two external inputs):
(1) Display interrupt
Update to timing signals (positive edge)
(2) External interrupt1
Negative edge on the INTO/P20 pin
(3) External interrupt2
Positive edge on the INTO/P20 pin
(4) External interrupt3
'a' input on the INT1 /P22 pin
(5) Timebase interrupt
1 2-Bit timebase counter overflow
(6) Timer interrupt
16-Bit timer and timer register matched signal
(7) Counter interrupt
8-Bit counter and counter register matched
signal
(8) Serial/O interrupt
8-Bit shift register shift end signal
8. 12-Bit Timebase Counter
The timebase counter is made up of a 12-bit
binary counter. It generates an interrupt request
every time it overflows as a result of dividing the
OSCO input 2'2.
9. 16-Bit Programmable Timer/Event Counter
Comprising a 16-bit register, a 16-bit binary
counter, a comparator circiut, and a control
circuit, the programmable timer generates an
interrupt request when the register and cou nter
values are matched.
10. 8-Bit High-Speed Programmable
Timmer/Event Counter
The high-speed programmable timer/event
counter comprises an 8-bit register, an 8-bit
binary counter, a comparator circuit, and a
control circuit. Starting and stopping the counter
can be controlled by instructions. It generates an
interrupt request when the register and counter
values are matched.
219
• MSC6458 • - - - - - - - - - - - - - - - - - - - - - - - - 11. 8-Bit Serial 1/0
Serial 1/0 consists of an 8-bit shift register,
a 3-bit shift counter, and a control circuit. It is
used for serial data input and output. Serial data
input and output takes place synchronized with
a shift clock, which is selectable between
internal and external clocks. The shift counter
automatically terminates a data transfer on
counting eight shift clock pulses and generates
an interrupt request.
1 2. Registers (Ace, H, L, F)
The accumulator (Acc) is a 4-bit register
used to perform data transfers or calculations
with the RAM, other registers, ports and so on.
The Hand L registers are each a 4-bit
register. They transfer data to and from Acc and
SP (stack pointer) and address the RAM. The L
register is also used to specify ports to use.
The F register is made up of four
independent flip-flops. It can be used as a
program "flag" or general-purpose register
because each of these flip-flops permits
set/reset testing and transferring 4-bit parallel
data to and from Acc by instructions.
13. Timing Control (TC)
A '0' input on the RESET pin for a certain
period initializes internal circuitry and ports.
As the input side of clock pulses, the OSCO
pin accepts clock pulses from an external
source. Clock pulses may also be obtained by
configuring an oscillation circuit with a crystal
oscillator or ceramic resonator connected to
OSCO and OSC 1 .
220
- - - - - - - - - - - - - - - - - - - - - - - - - . MSC6458 •
Load Instructions, etc.
Mnemonic
Code
Bytes
Cycles
Description
LAI
n
90-9F
1
1
A <-- n
LLI
n
BO-8F
1
1
L<--n
LHI
n
3E·7n
2
2
H <-- n
LHLI
nn
15· nn
2
2
HL <-- nn
LMI
nn
14· nn
2
2
M (w) <--nn
LAL
21
1
1
A<--L
LLA
2D
1
1
L<--A
LAH
22
1
1
A<--H
LHA
2E
1
1
H<--A
LAM
38
1
1
A<--M
LMA
2F
1
1
M<--A
LAM +
24
1
1
A ..... M, L ..... L+1, Skip if L
= "0"
LAM-
25
1
1
A <-- M, L <-- L-1, Skip if L
= "F"
LMA+
26
1
1
M <-- A, L <-- L+1, Skip if L
= "0"
LMA-
27
1
1
M <-- A, L <-- L-1, Skip if L
= "F"
LAMM
n2
39-3B
1
1
A <-- M, H <-- H ¥ n2
LAMD
mm
10· mm
2
2
A <--Md
LMAD
mm
11· mm
2
2
Md <--A
X
28
1
1
A<-+M
X+
3C
1
1
A <-+ M, L <-- L+l, Skip if L
= "0"
X-
2C
1
1
A <-+ M, L <-- L-1, Skip if L
= "F"
XM
n2
29-2B
1
1
A <-+ M, H <-- H ¥ n2
LMT
mm
19· mm
2
4
M (w) <-- T (Md (w), A)
LAF
3E·54
2
2
A<--F
LFA
3E·5C
2
2
F<--A
LHLS
3E·53
2
2
HL <-- SP
LSHL
3E·5B
2
2
SP <-- HL
A<--P
IP
20
1
1
OP
23
1
1
P<--A
IPD
p
3D· pD
2
2
A <-- Pp
OPD
P
3D· pC
2
2
Pp <-- A
18
1
3
P4, P5 <-- T (M (w), A)
OPT
-
221
• MSC6458 • - - - - - - - - - - - - - - - - - - - - - - - - - Interrupt Control Instructions
Mnemonic
Code
Bytes
Cycles
3E·60
2
2
MOl
3E·61
2
2
MEIF <-"0"
EIXO
3D· E8
2
2
EIXOF <- "1"
MEl
Description
MEIF <- "1"
EIXU
3D· E9
2
2
EIXUF <- "1"
EIXL
3D· EA
2
2
EIXLF <-"1"
EIOP
3D· EB
2
2
EIOPF <- "1"
EITB
30·08
2
2
EITBF <- "1"
EITM
30·09
2
2
EITMF <- "1"
EICT
30·0A
2
2
EICTF <-"1"
EISR
3D· DB
2
2
EISRF <- "1"
OIXO
3D· E4
2
2
EIXOF <- "0"
OIXU
3D· E5
2
2
EIXUF <- "0"
OIXL
3D· E6
2
2
EIXLF <- "0"
OIOP
3D· E7
2
2
EiOPF <- "0"
DITB
30·04
2
2
EITBF <- "0"
OITM
30·05
2
2
EITMF <- "0"
OICT
30·06
2
2
EICTF <-"0"
OISR
30·07
2
2
EISRF <-"0"
TIXO
3D· EO
2
2
Skip if EIXOF
TIXU
3D· E1
2
2
Skip if EIXUF
TIXL
3D· E2
2
2
TIOP
3D· E3
2
2
TITB
3D· DO
2
2
TITM
30·01
2
2
TICT
30·02
2
2
TISR
30·03
2
2
TQXO
30·20
2
2
TQXU
30·21
2
2
TQXL
30·22
2
2
TQOP
30·23
2
2
TQTB
3D· CO
2
2
TQTM
3D· C1
2
2
TQCT
3D· C2
2
2
TQSR
3D· C3
2
2
= "1"
= "1"
Skip if EIXLF = "1"
Skip if EIOPF = "1"
Skip if EITBF = "1"
Skip if EITMF = "1"
Skip if EICTF = "1"
Skip if EISRF = "1"
Skip if IRQXOF = "1"
Skip if IRQXUF = "1"
Skip if IRQXLF = "1"
Skip if IRQOPF = "1"
Skip if IRQTBF = "1"
Skip if IRQTMF = "1"
Skip if IRQCTF = "1"
Skip if IRQSRF = "1"
RQXD
30·24
2
2
IRQXOF <- "0"
RQXU
30·25
2
2
IRQXUF <- "0"
RQXL
30·26
2
2
IRQXLF <- "0"
RQDP
30·27
2
2
IRQDPF <- "0"
RQTB
3D· C4
2
2
IRQTBF <- "0"
RQTM
3D· C5
2
2
IRQTMF <- "0"
RQCT
3D· C6
2
2
IRQCTF <- "0"
RQSR
3D· C7
2
2
IRQSRF <- "0"
222
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSC6458 •
Increment/Decrement Instructions
Mnemonic
Code
Bytes
Cycles
INA
30
1
1
A <-A+1, Skip if A
INl
31
1
1
l <- l + 1, Skip if l
INH
32
1
1
H <- H+1, Skip if H
INM
33
1
1
M <- M+1, Skip if M
DCA
34
1
1
A <-A-1, Skip if A
DCl
35
1
1
l <- l-l, Skip if l
DCH
36
1
1
H <- H-1, Skip if H
DCM
37
1
1
M <- M-1, Skip if M
Description
= "0"
= "0"
= "0"
= "0"
= "F"
= "F"
= "F"
= "F"
INMD
mm
12· mm
2
2
Md <- Md+ 1, Skip if Md
= "0"
DCMD
mm
13· mm
2
2
Md <- Md-1, Skip if Md
= "F"
Code
Bytes
Cycles
Bit Handling Instructions, etc.
Mnemonic
Description
= "1"
TAB
n2
54-57
1
1
Skip if A (n2)
RAB
n2
64-67
1
1
A (n2) <-"0"
SAB
n2
74-77
1
1
A (n2) <- "1"
TPB
n2
50-53
1
1
Skip if P (n2)
RPB
n2
60-63
1
1
P (n2) <- "0"
SPB
n2
70-73
1
1
P (n2) <- "1"
TMB
n2
58-5B
1
1
Skip if M (n2)
RMB
n2
68-6B
1
1
M (n2) <- "0"
5MB
n2
78-7B
1
1
M (n2) <- "1"
TFB
n2
5C-5F
1
1
Skip if F (n2)
RFB
n2
6C-6F
1
1
F (n2) <- "0"
SFB
n2
7C-7F
1
1
F (n2) <- "1"
TPBD
p,n2
3D·
pO~3
2
2
Skip if Pp (n2)
p, n2
3D·
p4~7
2
2
Pp (n2) <- "0"
p, n2
3D·
p8~B
2
2
Pp (n2) <- "1"
1
Skip if C
RPBD
SPBD
TC
09
1
RC
08
1
1
C<-"O"
SC
07
1
1
C +- "1"
= "1"
= "1"
= "1"
= "1"
= "1"
223
Arithmetic Instructions
Mnemonic
Code
Bytes
Cycles
C, A _C+A+M, Skip if C = "1"
Description
ADCS
01
1
1
ADS
02
1
1
A+- A+M, Skip if Cy = "1"
ADC
03
1
1
C,A_C+A+M
3E·4n
2
2
A _A+n, Skip if Cy = "1"
DAA
06
1
1
A_A+6
DAS
OA
1
1
A_A+10
AND
OD
1
1
A_AAM
OR
05
1
1
A_AVM
EOR
04
1
1
A+-A¥M
CMA
OB
1
1
A_A
CIA
OC
1
1
A+- A+1
RAL
OE
1
1
CC +- 3+-2_1 +-O~
,-- A ______
RAR
OF
1
1
t C -->
CAM
16
1
1
SkipifA=M
n
AIS
,--A ______
3-->2-->1-->0)
CAl
n
3E· On
2
2
SkipifA=n
CMI
n
3E·1n
2
2
SkipifM=n
CLI
n
3E·2n
2
2
SkipifL=n
CPI
p,n
17· pn
2
2
Skip if Pp = n
Code
Bytes
Cycles
CO-FF
1
1
PC-a6
JA
1A
1
2
PC _ (PC _ A) + 1
JM
1B
1
2
PC _ (M (w), A)
Branch Instructions, etc.
Mnemonic
JCP
a6
Description
JP
a12
40 4F
oo-FF
2
2
PC_a12
CAL
a12
AO AF
OO-FF
2
4
ST _ PC+2, PC _ a12, SP _ SP-4
CZP
a
Ba
1
4
ST +- PC+1, PC +- 2a, SP _ SP-4
WP
a13
3F 3F
oo-1F
00 FF
3
4
PC_a13
LCAL
a13
3F 3F
BO-9F
00 FF
3
4
ST - PC+3, PC - a13, SP +- SP-4
RT
1E
1
4
PC +- ST, SP _ SP+4
RTS
1F
1
4
PC _ ST, SP _ SP+4, then Skip
224
- - - - - - - - - - - - - - - - - - - - - - - - - . MSC6458 •
Counter Controllnstructlona, etc.
Mnemonic
Code
Bytes
Cycles
Description
LCTM
3E·51
2
2
CTR_M(w)
LMCT
3E·59
2
2
M (w) _CT
ECT
3D· BB
2
2
CTF _"1"
(Counter Start)
DCT
3D· B7
2
2
CTF_"O"
(Counter Stop)
TCT
3D· B3
2
2
Skip if CTF
LTMM
3E·50
2
3
TMR_M(2w)
LMTM
3E·58
2
3
M(2w)_TM
LSRM
3E·52
2
2
SR _ M (w), SC _ "0"
LMSR
3E·5A
2
2
M (w) _SR
ESR
3D· BA
2
2
SRF <- "1"
(Shift Register Start)
DSR
3D· B6
2
2
SRF <-"0"
(Shift Register Stop)
TSR
3D· B2
2
2
Skip if SRF
Code
Bytes
Cycles
PUSH
1C
1
3
ST _ C, A, H, L, SP +- SP-4
POP
10
1
3
C, A, H, L +- ST, SP +- SP+4
HALT
3D· B8
2
2
Halt CPU
STOP
3D· B9
2
2
Stop CPU
NOP
00
1
1
No Operation
= "1"
SC: Shift Counter
= "1"
CPU Controllnatructlona, etc.
Mnemonic
Description
225
eMSC645Se------------------------------------------------explanations of Instruction Symbols
U
A
H
L
F
M
Md
M(w)
Md(w)
M(2w)
ST
SP
PC
P
Pp
CTR
CT
CTF
TMR
TM
SR
SRF
(X, Y)
T(X, Y)
n
nn
n2
(n2)
a
aX
mm
C
Cy
226
: Accumulator (4-bit)
: H register (4-bit)
: L register (4-bit)
: F register (4-bit)
: RAM word addressed by the Hand L registers
: RAM word addressed by second byte of an instruction code
: Two RAM words addressed by the Hand L register/H3-0 and l3-1 (S-bit)
: Two RAM words addressed by second byte of an instruction code (S-bit)
: Four RAM words addressed by the Hand L register/H3-O and l3-2 (16-bit)
: Four RAM words (16-bit) allocated as a stack area
: Stack pointer (S-bit)
: Program counter
: Port specified by the L register (4-bit)
: Port specified by 4 high-order bi°ts of second byte of an instruction code (4-bit)
: S-Bit counter/register
: S-Bit programmable counter
: Programmable counter start flag
: 16-Bit timer/register
: 16-Bit programmable timer
: S-Bit shift register
: Shift register start flag
: ROM address data specified by a11-4 as X and a3-O as Y (12-bit)
: ROM table data specified by a11-4 as X and a3-O as Y (S-bit)
: Immediate data (4-bit)
: Immediate data (S-bit)
: Two low-order bits of an instruction code
: Bit specified by the two low-order bits of an instruction code
: ROM address data
: ROM address data (X-bit)
: RAM address data (S-bit)
: Carry flag
: Flag indicating a carry in a calculation result
-----------------------------------------------------.MSM~8·
ELECTRIC CHARACTERISTICS
• Absolute Maximum Ratings
Parameter
Supply Voltage
Indicated Supply Voltage
Input Voltage
Symbol
Conditions
VOO
VFLT
VI
Ta= 25°C
Input Voltage
Vo
"H" Output Current
!Indicated Output)
10H
"L" Output Current
(P4, P5)
10L
Power Oissipation
Po
Per pin
TO - Tt1
OUTO- OUT7
Output terminal SEGO - SEG11
total
TO - Tt1
Per terminal
P4 total
P5 total
Per package
Per input/output terminal
-
Storage Temperature
Tstg
* When timing output is used as static output
40
30
72
72
20
40
40
600
50
-55 - +150
mA
mA
fuA
mA
mA
mA
mA
mW
mW
°c
Limits
4.5 - 5.5
3-6
10 -40
2-6
Unit
V
V
V
V
°c
VOO -45
Input/output
Indicated output
SEGO- SEG1
Ta= 25<>C
-0.3 - VOO
-0.3 - VOO
-0.3 -VFLT
10
Unit
V
V
V
V
V
mA
Limits
-0.3 -7
*
• Operating Conditions
Parameter
Supply Voltage
Indicated Supply Voltage
Memory Retension Voltage
Operating Temperature
(Fan Out (Input/Output Port)
Symbol
VOO
Conditions
f (ose) ;S;; 4.3MHz
f (ose) ;S;; 1 MHz
-
VFLT
VOOH
Topr
Oscillation off
N
MOS Load
TTL Load
-
• DC Characteristics
Parameter
"H" Input Voltage
"L" Input Voltage
"H" Output Voltage
"L" Output Voltage
"H" Input Current
erminal applied Symbol
*1
OSCO,RESET
VIH
P7, PS
*2
VIL
P7, PS
*3
SEGO - SEG11 VOH
TO - T11
PO, P1, P3, PS
P4,P5
OSC1
VOL
SEGO - SEG11
TO - T11
OSCO
P2, RESET
P7(P73=0), PB
P7(P73=1 )
-40 - +S5
15
1
(VOO = 5V ±10%, Ta
Typ.
Min.
2.4
3.S
3.4
0
0
4.2
10=-15"A
10= -SmA VFLT-2.5
10= -20mA VFLT·3.5
10= 1.6mA
10 = .10mA
Conditions
10 = 15"A
10 = lmA
10= 1mA
-
-
IIH
VI = VOO
-
-
-
= -40 - +S5°C)
Max.
Unit
VOO
VOO
VOO
O.B
1.S
-
0.4
O.B
0.4
1.S
1.4
15
1
SO
1
V
V
V
V
V
V
V
V
V
V
V
V
V
"A
"A
"A
"A
227
eMSM645Se----------------------------------------------------Parameter
Min.
Typ.
Max.
Unit
-
-15
p.A
-30
p.A
-
-
-1
p.A
VO'" 2.4V
-0.1
-
-
rnA
VO = O.4V
-
-
-1.2
rnA
No load
f (osc) = 4.3MHz
-
12
20
rnA
No load
-
1
100
p.A
-
0.5
10
p.A
-
2
100
p.A
erminal applied Symbol
Conditions
OSCO
"L" Input Current
P2, RESET
-
VI=OV
IlL
P7,P8
"H" Output Current
PO, Pl, P3,
P4,P5,P6
Current Consumption
IOH
100
Current Consumption
(When stop mode condition)
IOOS
No load
VOO = 2V
Ta = 25°C
Current Consumption
(F LT driver section)
IFLT
No load
All F LT driver,
"L" level
* 1. Applied to PO, Pl, P2, P3, P4, P5, P6
*2. Applied to PO, Pl, P2, P3, P4, P5, P6, OS CO, RESET
*3. Applied to PO, Pl, P3, P4, P5, P6, OSCl
• AC Characteristics
(VOO = 5V ±10%, Ta = 40 - +85°C)
Symbol
Conditions
Min.
Typ.
Max.
Clock (O.S.C 0) Pulse Width
tW
-
116
-
-
nS
Cycle Time
tCY
928
-
-
nS
Parameter
Unit
Input Data Setup Time
tos
-
120
-
-
nS
Input Data Hold Time
tOH
-
120
-
nS
tOWP2
Note 1
120
-
-
SR Clock. Pulse Width
tOW1
-
120
-
-
CT Clock. Pu Ise Width
tOW2
-
2/8tCy+120
-
-
nS
TM Clock. Pulse Width
tOW3
P2 Input Data Pulse Width
nS
nS
nS
120
-
-
tss
-
tCy+120
SR Data Setup Time
-
nS
SR Data Hold Time
tSH
-
120
-
-
nS
tSINH
-
2/8tcy
-
-
nS
Data Delay Time
tOR
CL=15pF
-
300
nS
SR Clock Delay Time
tsP
CL=15pF
-
-
360
nS
tWRS
Note 2
2tcy
nS
tTLHS
-
-
-
VFLT=40V
3
p.SS
SR Clock Invalid Time
Reset Input. Rise Time
Segment Output. Rise Time
*
Segment Output. Rise Time
tTHLS
CLD = 15pF
Timing Output. Rise Time
tTLHT
VFLT=40V
Timing Output. Rise Time
tTHLT
CLD=15pF
-
1
p.S
-
3
p.S
-
1
p.S
*1. When stop mode is to be released by "L" level input from P20/INTO, it is necessary to keep the pulse
width of more than oscillation stability time for OSC o •
*2. This indicates when OSC o oscillation is stabilized. However, when stop mode is released by reset
input, the pulse width of more than OSC o oscillation stability time as requested.
*3. tSINH: When shift register commands LMSR during shift in operation, its inner part will not change
if clock, which inputs P01/SCK during tSINH period, changes.
228
---------------------------------------------------.MSM~8·
STANDARD CHARACTERISTICS
• "H" Output Current IOH - Output Voltage
VOH Characteristics ITa = 25°C)
• "H" Output Currant IOH- Output Voltage
VOH Characteristics ITa = 25"C, VFLT = 4OV)
Segment Output
-20
PO,P1,P3,P4,P5,P6
-1.0
-18
-0.9
_ -12
~
-0.6
:I:
~4V
~
o
-Q4
1\
r.... 3Vl\.
2
o
5 6
VOH(V)
PO, P1, P3, P6.
6V
24
22
II ./
20
18
I~
16
~
IIJ
14
V
..J 12
'/
9 10
fl
8
'I ~
6
4 J
2
J.
1\
35
7
8
37
38
VOH (V)
36
9 10
• "L" Output Currant IOL- Output Voltage
VOL Charactaristlcs ITa = 25"C)
1
1
-02
\
1'-13 "4
1
1\
1\
\
-os
'" \"
-0.3 ~
-10
:I:
9 -os
5V 1\
...... "
9 -0.4
-0.1
1
f\.
.§. -0.5 "-
~
,
Voo=5V
-50
~
-40
4"-
<"
-30
.§
-20
\
1
.§.
.... 3V _ '- f-
[\
\
-10
r\
II
2
3
VOL (V)
4
0 35
5
• "L" Output Currant IOL - Output Voltage
VOL Characteristics ITa = 25°)
6V Voo = 5V
P4 50
P5
fl
jV V
40
rt
9 20
39
40
9
8
7
1
l- I - 3V
V-
..J
37
38
VOH(V)
10
hl/
.§.
\
36
• "L" Output Currant IOL - Output Current
VOL Characteristics ITa = 25°C, VFL T = 4OV)
Segment Output
L.---'l-4V
Z
~ 30
40
39
• "L" Output Currant IOH- Output Voltage
VOL Characteristics ITa = 25° C, V F LT = 4OV)
Timing Output
Voo
=5V
rl
0
,
\
-14
f-.. 10.... Voo=6V
-0.7
-0.2
1\
-16
-0.8
<"
Voo=5V
..J
9
I/
6
5
4
VOO=5V
3
2
10
I/'
/
j
o
2
3
VOL (V)
4
5
2
3
4
5
VOL (V)
229
·MSM~·-------------------------------------------------------
• "L" Output Current IOL - Output Current
VOL Characteristics ITa = 25"C, VFLT = 4OV)
• Current Consumption IDD - Supply Voltage VDD
ITa = 25°C, No load)
100m
Timing Output
10
9
8
1
.9
VoO-5V
7
6
5
r
4
I
3
2
I
I
-'
,
-,,,/
/
1m
/
J
o
o
f (ose) = 4HMz
... 2MHz
1 MHz
500kHz--= F=
. /V
10m
2
3
4
5
VOL (V)
~o
1001'
.9
• Maximum Clock Freqency flosc) - Supply
Voltage VDD Characteristics
ITa = 25°C, CL = 15pF)
101'
10
~
9
~
8
N
J:
~
V
7
6
V
J
~ 5
£. 4
/
I
3
~
lOOn
2
1
0
1
2
3
4
5
6
7
8
9 10
• Maximum Clock Frequency flosc) - Ambient
Tempereture Ta (VDD = 5V, CL = 15pF)
9
8
7
N
J:
6
.
I'
Voo= 5V
,
....
........
.......
........
r-
~ 5
~ 4
£.
3
2
0-40 - 20 -0204060 80100120
Ta (0C)
230
o
2
3
4
5
6
Voo(V)
Voo(V)
10
... Stop mode
V
7
8
9
10
---------------------------------------------------eMSMM5Se
TIMING CHART
)J:YYUY
tcv
PO,P1,P3,P4
P5, P6,P7,P8
Input Data
tDS
PO,P1,P3
P4,P5,P6
SEGO
I
SEG11
Output Data
t
-I
I i
I
T11
O.9VF-'T------ vm
ttO.1VFLT
tTLHS
TO
tDH
tTHLS
O]VFCT-----vm
- - - - -.I~4----------t-..,,_= 0.1 VFLT
tTLHT
GND
GND
tTHLT
231
·MSM~·-------------------------------------------------------
r----,
P01/SCK
~
tDW1
P03/S1
tDW1
Input IData
tSH
tss
Input
P02/S0
P10/CIN
P12/TCK
Output Data
~
IJS~
P2CiiNTO
P22/INT1
D~ta
~~---------------------------------
---'1
'om
{
'om
~1--
j-------:"'---IJ--
DW3
..---==-tD==-W-3
-=-=--I-!_-=:..:..:..:t
-j
1 - .- t W R - S
tslNH
1MC
2MC
LMSR Instruction
232
OKI
semiconductor
MSC6458VS
MSC6458 PIGGY BACK
GENERAL DESCRIPTION
The MSC6458VS is a device whose built-in ROM is replaced by external EPROM using the
piggyback method.
FEATURES
• Supply Voltage: 5V±5%
• Frequency: DC - 4.3MHz
•
Operating Temperature: 0 - 70°C
ROM INSERTION
Please refer to drawing below.
C6458
OKI
JAPAN
PIN CONFIGURATION
Pin Connection between MSC6458 VS and EPROM
Vee
A13
A12
All
10
9
8
5
Vpp
A12
A7
A6
A5
4
A4
3
2
A3
A2
Al
AD
00
01
02
GND
7
ToAD -A13
of MSC6458VS
) , ADDRESS
'Y
6
1
AD
DO
1
2
10-1
MSC6458VS
),
'Y
Note: When inserting a 2764,
pin 26 is not used.
DATA
--
"1"'-'28
2
27
3
26
4
25
5
24
6
23
72712822
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC PGM A13 A8A9All
DE
A1D
CE
070605-
g;Jl
3
4
5
6
07
GND
233
OlMS-65 SERIES
H
OKI
semiconductor
MSM6502/6512
CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM6502/6512 is a low-power, high-performance 4 bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within this one chip is a 108 (4 x 27) dot LCD Driver. Also integrated in this chip are
16K bits of mask program ROM, 512 bits of data RAM, Input/Output lines, a programmable
timer/counter, and oscillator.
The advantages of the MSM6502/6512 in comparison with the OLMS-40 Series include, among
other features, a lower drive voltage, multiplexed interrupts, a larger number of drivable liquid crystal
elements, a buzzer output, and larger memories.
FEATURES
•
•
•
•
•
•
•
•
•
ROM
RAM
Number of
Instructions
Clock Oscillation
CycleTime
Timer Interrupt
I/O Ports
Input ports
LCD Drive
•
•
Buzzer
Interrupt
2000 x 8 bit
128 x 4 bit
68
•
Stack
•
•
Powerdown
Operating power
supply voltage
Consumption
current
(VDD=3V,
OSC=
32.768 kHz)
Crystal 32.768 kHz
91.5 1Ls
Dual (16 & 128 Hz)
4 bit x 2 Port
4 bit x 1 Port
108 (4X27)
picture elements
2K/1 K/51 2 Hz/Soft
Three types
(external, two timer
types)
•
•
Package
Nesting RAM stack
pointer = 7 bits
Halt mode available
2.4V-3.6V
MSM6502
: 45ILA (Typical)
30ILA (Halt mode)
MSM6512
: 30ILA (Typical)
1 2ILA (Halt mode)
56 pin FLAT (Small type)/
CHIP FORM
FUNCTIONAL BLOCK DIAGRAM
237
• MSM6502/6512 • - - - - - - - - - - - - - - - - - - - - - - -
PIN CONFIGURATION (TOP VIEW)
LOGIC SYMBOL
COlt'l-.:t(O)N ..... O
Crystal
OSCo
resonator
asel
connection
PORT 00
01
02
03
J
wwwwwwwcw
C/JOOCIJOOC/)W(f»OO
wl{)""C?C\I ....
omco
l()U)IJ)Il)IOIl)Il)..,'"
Reset
~5;';(;
wwww
Cl)cnOOCIJ
~~~~~~~c~
porta
(input/output ports)
l
TEST3
TEST.
]
LCO
common output
LCD
segment output
8Z
13
BZ
14
25
26
+3V
Voo
BZ
OV
GNO
BZ
J
w w ~ ~ c 81
en u c i
I ~wll-z I~I~
Buzzer output
w w 0
CI)
~~~
ZOO 0 0
C:_~~~I->OO"OOQO
PIN DESCRIPTION
Designation
Pin No.
GND
24
VDD
21,49
OSCo
OSC,
PO,P1
-
Function
Circuit GND potential
Main power source
22
Crystal OSC input, internal clock input
23
Crystal OSC input, internal clock output
1 to 4
5t08
Pseudo-bidirectional ports for 4-bits parallel 1/0. To input data from these ports,
it is necessary to write "1" beforehand.
The port to be selected is specified by the L register. The register contents and
the corresponding specified ports are listed below.
Content of L register
.
0.8
1.9
2.0AH
3.0BH
4.0CH
5.0DH
6.7.0EH.OFH
Port Specified
PO
P1
P2
P3
P4
P5
No designation
Note: P3, P4, P5 are internal ports.
P2
9t012
INT
16
238
Input ports for 4-bit parallel input with no latching function.
Input pin to request an interrupt from the external circuit. The input flag is set by
the fall of the input signal.
- - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
Designation
Pin No.
RESET
15
Function
The reset mode starts after "0" is input to the RESET pin for more than 2
machine cycles.
The reset signal has priority over all of other signals and performs the following
operations automatically:
(1) Resets all bits of the PC (Program counter) to "0".
(2) Sets all bits olthe parallel 110 ports (POO to P13) to "1 ".
(3) Resets the internal resister (H, L, ACC, C, P3, P4, P5).
(4) Resets the skip flag.
(5) Resets all bits of the time base counter (TBC).
(6) Resets the Interrupt request flag (lRQF).
(7) Resets the interrupt enable flag (ElF).
(8) Resets the master interrupt enable flag (MEIF).
(9) Sets all bits of the stack pointer (SP) to "1 ".
(10) Initializes the segment and common outputs.
(11) Sets all bits of the index register (lOR) to "1".
Since the RESET pin is pulled up to VDD by an internal resister (approx. 800
kO), it is possible to achieve power ON/reset by connecting it with an
external capacitor.
LCD Drive Pins
SEGO-26
29t048
50t056
25t028
COM 1 -4
BZ/BZ
13,14
A special AC waveform designed to comply with liquid crystal properties is
required for liquid crystal drive purpose. The MSM6502B is equipped with a
1/4 duty 1/3 bias liquid crystal drive circuit with four common output ports and
27 segments to enable displays of 108 picture elements. On/off selection of
picture element displays involves writing "0" or "1" in the corresponding bits in
the RAM OOH to thru 1AH display area, and subsequent automatic hardware
controlled display. The frame frequency is 64 Hz.
BZ and BZ are used in the generation of alarms and other sounds. The
selectable frequencies include three hardware frequencies (TBC output) 51 2,
1024, and 2048 Hz, and a software type based on P50 data. These frequencies
are selected at P3.
When one of the hardware frequencies is selected by P3, output of that
frequency is continuous. But selection of the software type results in output of
P50 contents to generate a melody by program.
INSTRUCTION LIST
Grouping
Load
Byte
Cycle
LAI
n
8n
1
1
Acc-n
LLI
n
7n
1
1
L-n
LHLI
n8
6A
n8
2
2
HL-n8
LXI
n8
69
n8
Mnemonic
Code
Function
2
2
X-n8
LAM
BO
1
1
Acc-M
LAL
Bl
1
1
Acc-L
LAH
B2
1
1
Acc-H
LMA
84
1
1
M -Acc
LLA
B5
1
1
L-Acc
LHA
B6
1
1
H-Acc
2
2
M -Acc
LMAD
m7
lB
m7
239
• MSM6502/6512 • - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (CO NT.)
Grouping
LAMD
m7
LMT
Function
Byte
Cycle
2
2
Acc-M
67
1
2
M -ROM
Code
Mnemonic
1A
m7
PUSH
HL
BC
1
2
STACK -HL, SP -SP-2
PUSH
CA
BD
1
2
STACK -C, Acc, SP -SP-2
POP
HL
BE
1
2
HL -STACK, SP -SP+2
POP
CA
BF
1
2
C, Acc -STACK, SP - SP+2
B8
1
1
Acc~M
2
2
Acc~M
Load
XAM
Exchange
Increment
and
decrement
XAMD
240
1C
m7
XHS
3F
1
1
HL~SP
INA
10
1
1
Acc - Acc + 1, Skip if Acc= 0
INL
11
1
1
L-L+1,SkipifL=O
INM
12
1
1
M-M+1 ,Skip if
M=O
INX
5C
1
1
X-X+1
DCA
14
1
1
Acc - Acc-1 , Skip if Acc= F
DCL
15
1
1
L-L-1
DCM
16
1
1
M-M-1 ,Skip ifM=
F
DCX
5D
1
1
X-X-1
DSC
60
1
1
C,Acc-C+Acc+M,AdjustifC=O
DAC
61
1
1
C,Acc-C+Acc+(M < HL > +6), Adjust if
C=O
ADS
62
1
1
Acc -Acc+M, Skip ifCy=1
ADCS
63
1
1
C,Acc -C+Acc+M < HL > ,Skip if C=1
AIS
Operation
m7
n
SkipifL=F
On
1
1
Acc-Acc+n, Skip if Cy=1
CMA
65
1
1
Acc-Acc
EOR
66
1
1
Acc -Acc-lfM
AND
4C
1
1
Acc -AccI\M
OR
4D
1
1
Acc -AccvM
CAM
6B
1
1
Skip if Acc = M
CPAL
6C
1
1
Skip if Acc = L
CAXL
6D
1
1
Skip if Acc = XL
CAXH
6E
1
1
Skip if Acc = XH
SC
1F
1
1
C-"1"
RC
1E
1
1
C-"O"
TC
4E
1
1
Skip if C= "1"
- - - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
INSTRUCTION LIST (CO NT.)
Grouping
Mnemonic
Code
Byte
Cycle
RAL
18
1
1
RAR
19
1
1
r - - Acc-,
(*) - C - 3-2-1 -0-(*)
n2
30-33
1
1
M bitn2 -"1"
5MBO
m7,n2
50
m7
-
2
2
M bitn2-"1"
SPB
n2
20-23
1
1
Pbitn2-"1"
RMB
n2
34 -37
1
1
M bitn2-"0"
-
2
2
M bitn2 -"0"
Operation
5MB
Bit
Function
,.- Acc ____
(*) -C -3-2-1--0-(*)
53
m7
RMBO m7,n2
54
m7
RPB
n2
24-27
1
1
Pbitn2 -"0"
TMB
n2
38-3B
1
1
SkipifM bitn2 ="1"
TMBO
m7,n2
58 5B
m7 m7
2
2
Skip ifM bitn2 ="1"
TPB
n2
28-2B
1
1
Skip if P bit n2 ="1"
TAB
n2
2C-2F
1
1
Skip if Acc bit n2 = "1"
TIRB
n2
49-4B
1
1
if IRQF bit n2="1" Skip & IRQF bit n2 -"0"
EI
5E
1
1
MEIF-"1"
01
5F
1
1
MEIF-"O"
9000-97CF
2
2
PC,o-o- a11
Operation
57
m7
Interrupt
Branch
Input!
Output
CPU
Control
J
a11
CAL
a11
AOOO-A7CF
2
3
STACK-PC+2, SP-SP-3, PClO- o-a11
a6
CO-FF
1
1
PCs-o-a6
RT
3C
1
2
PC -STACK, SP-SP+3
RTS
30
1
1
PC -STACK, SP-SP+3, then Skip
JCP
IP
B3
1
1
Acc-P
OP
B7
1
1
P-Acc
HALT
4F
1
1
HLF-"1"
NOP
00
1
1
No Operation
241
eMSM6502/6512 e --------------------------------------------ELECTRICAL CHARACTERISTIC
ABSOLUTE MAXIMUM RATING
Parameter
Power Supply Voltage
Symbol
VOO
Input Voltage
VI
Output Voltage
Vo
Power Dissipation
StorageTemperature
Conditions
Po
Tstg
Ta=25°C
Ta=25°C
per package
-
Limits
Unit
-0.3-7
V
-0.3- VOO
V
-0.3- VOO
V
200
mV
-55-+150
°c
OPERATING RANGE
Symbol
Conditions
Limits
Unit
Power Supply Voltage
VOO
j(osc)=32.768 kHz
2.4-3.6
V
Operating Temperature
Top
-20-+70
°c
Parameter
242
-
- - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
D.C. CHARACTERISTICS
(VOO = 3V, Ta = -20 - +70 0 e)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V,H
-
2.6
-
-
V
V,L
-
-
-
0.4
V
Voltage 1)
VOH
'0=-1.OmA
2.0
-
-
V
"L"Output
Vollage(2)
VOL
10=1.OmA
-
-
1.0
V
2.8
-
3.0
V
1.8
-
2.2
V
0.8
-
1.2
V
0.0
-
0.2
V
V, = VOOIV, = OV
-
-
2/-2
/LA
I'HII'L
V, =VOOIVI =OV
-
-
1/-10
/LA
"H"'L
V, =VOOIV, =OV
-
1000/-1
/LA
I'H"'L
V, =VOOIV, =OV
-
-
1/-40
/LA
-
-
-50
/LA
-
45
70
-
30
55
30
40
-
12
25
-
15
25
-
5
15
-
-
10
"H"lnputVoltage
"L"lnputVollage
"H"Out~ut
MSM6502
'0=-5/LA
MSM6512
'0=-2/LA
MSM6502
'0 =±2/LA
MSM6512
10=±0.5/LA
V3
V2
LCD Drive
Output Voltage(3)
V,
MSM6502
10=±2/LA
MSM6512
10=±0.5/LA
MSM6502
10=5/LA
MSM6512
10=±2/LA
Vo
OSCo Input Current
Input Current(4)
Input Current(5)
Input Current(6)
PO,P1
"H" Output Current
"H"'L
Vo=OV
10H
MSM6502
100
Current
Consumption
MSM6512
MSM6502
IOOHLT
MSM6512
!(ose) =32.768 kHz
at no load
Hose) =32.768 kHz
at HLT execution
MSM6502
'OOS
Oscillation Start
Time
TOSC
Statls
MSM6512
-
/LA
/LA
/LA
SEC
243
• MSM6502/6512 . - - - - - - - - - - - - - - - - - - - - - (1) Applied to BZ, BZ
(2) Applied to BZ, BZ, PO, P1
(3) Applied to COMMON, SEGMENT
- - ----Va
-- -
- --V.
------V,
- - - - - Vo
(4) Applied to RESET, INT
(5) Applied to P2 (When input is unable)
(6) Applied to P2 (When Input is able)
SWITCHING CHARACTERISTIC
(VOO = 3V, Ta = -20 - +7O·C)
Symbol
Conditions
MIN.
TYP.
MAX.
Clock (OSCo) Pulse Width
Parameter
tq,W
-
15
-
-
ILS
Cycle Time
tCY
-
(1 )
-
-
ILS
PO
P1 Data Valid Time
P2
tov
-
(2)
-
-
ILS
PO
P1 Data Invalid Time
P2
tOIV
-
-
-
(3)
ILS
~? Data Delay Time
toos
CL=50pF
-
-
(4)
ILS
(1)
(2)
(3)
(4)
tCy=3 x 1/f(osc)
tov = 112 x 1/f(osc)
tOlV = 1 x 11f(0sc) + 1OILS
toos = 5/2 x 1/f(osc) + 1 5ILS
1MC tCY
OSCo
tcf>w
PO
P1 Input mode
P2
t¢w
INVALID
tOlV
PO
P1 Output Mode
VALID
tov
OLD DATA
toos
244
INVALID
NEW DATA
Unit
- - - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
TYPICAL PERFORMANCE CURVES for MSM6502
Low-level Output Current (lOL)
- Output Voltage (VOL)
High-level Output Current (lOH)
- Output Voltage (VOH)
(Voo =3V, Ta= 25°C)
(Voo= 3V, Ta= 25°C)
-5
10
-4
8
9
<
.s
-3
.9
-2
J:
7
-
<
.s...J
(BZ, BZ terminal)
'\
.9
~(PO,P1 terminal)
.1
o
1
2
3
4
5
6
o
7
8
9
10
f
If
o
(PO, P1 terminal)
-
II'"
2
(COMMO~, SEGMENT terminal)
o
4
3
\
-1
6
5
.1,-.1 !
f - (BZ, BZ terminal)
(COMMON SEGM,ENT,terminal~
2
3
4
5
6
7
8
9
10
VOL(V)
VOH(V)
Middle-level Output Current (11, 12)
- Output Voltage (V1 , V2)
Current Consumption (100)
- Power Supply Voltage (VOO)
(Voo= 3V, Ta= 25°C)
(Ta= 25°C, No load)
25
10m
20
5m
15
V1
10
<
-5
N
-
500IL
/ /
0
-10
1m
/ /
5
-5
V2
J /
(COMMON, SEGMENT terminal)
V II
100IL
-15
5
-20
..fl
-25
.., HOSC) = 32,768 KHz
50IL
/ V o~z
,/
0
1OIL
o
1
2
3
4
5
6
7
8
9
10
5IL
V"V2(V)
500n
100n
o
2
3
4
5
6
7
8
9
10
Voo(V)
245
-::-
~
eMSM6502/6512e--------------------------------------------TYPICAL PERFORMANCE CURVES for MSM6512
Low-level Output Current (lod
- Output Voltage (Vod
High-level Output Current (lOH)
- Output Voltage (VOH)
(Voo =3V, Ta= 25°C)
(Voo= 3V Ta= 25°C)
10
-5
9
8
-4
7
<
.§
J:
.9
-3
........
<
(BZ, BZ terminal)
.§
1'\
-2
...J
.9
4
(PO, P1 terminal)
3
1\
-1
6
5
1/
2
o
~
o
~(PO, P1 terminal)
1
2
3
4
5
6
o
7
8
9
10
-
I
(COMMON, SEGMENT terminal)
II
_1---:.1
!
t - (BZ, BZ terminal)
(COMMON SEGMENT terminal)
o
2
3
4
5
6
7
8
9
10
VOH(V)
VOL(V)
Middle-level dutput Current (11, 12)
- Output Voltage (V1 , V2)
Current Consumption (100)
- Power Supply Voltage (Voo)
(Ta= 25°C, No load)
(Voo= 3V, Ta= 25°C)
25
10m
20
5m
15
V1 V2
10
<
..5N
-
1m
JJ
5
5001-'
II II
0
J
-10 II II
j
-5
(COMMON, SEGMENT terminal)
1001-'
-15
3
-20
.9
-25
i(OSC) = 32,768 KHz
501-'
0
V
101-'
o
1
2
3
4
5
6
7
8
9
10
51-'
V
V
oJz
V
11-'
500n
100n
o
1
2
3
4
5
6
Voo(V)
246
7
8
9
10
8 BIT SERIES (OKI ORIGINAL)
n
OKI
salTllconc:luctor
MSM62580
CMOS 8-BIT SINGLE CHIP MICROCONTROLLER WITH 16K BIT E2PROM
GENERAL DESCRIPTION
The MSM62580 is a CMOS single-chip microcontroller with on-board 16K bit E2PROM for
applications such as IC-cards, etc.
The powerful instruction set consists of 95 instructions including special instructions for IC cards,
executed by the 8-bit CPU in 800 ns at 5.0 MHz clock frequency.
The MSM62580 has improved hardware and software for security. Consequently, this chip suits
application such as IC cards of low cost, high security and high reliability.
APPLICATION EXAMPLES
•
•
•
•
IC Cards
Mechanical Controls
Automobile Controls
Industrial Controls
•
•
•
•
Compact Disc Players
AudiolVideo Equipment
Household Appliances
Musicallnstruments
FEATURES
High speed instruction cycle
High number of instructions, and an efficient instruction set
(For example)
• Instructions for
• Instructions for
auto increment
: SIN, SOUT, DLY
serial interface
and auto decre• Index addressing
ment
• 1 byte call addresing : CZP
• Small Die size
• Simplified E2 PROM write/erase operation by using control ROM.
• From D.C to 5 MHz clock frequency
• 9600 baud-rate serial interface using "DLY" instruction.
: INC, DEC
SPECIFICATIONS
•
•
•
•
•
•
Single chip, low power CMOS
8-Bit Microcontroller
3K Bytes program ROM
512 Bytes control ROM
2K Bytes E2PROM
128 Bytes data RAM
•
•
•
•
•
•
•
•
:
Clock frequency
Instrucion cycle
:
Number of instructions:
Operation current
:
Ambient range
:
Number of pads
:
Supply voltage
:
Die size
:
0 - 5.0 MHz
SOOns @ 5 MHz
95
4 rnA typo
0 to 70°C
5
+ 5 V ± 10%
5.0 )( 4.5 mm
249
eMSM62580e-----------------------------------------------BLOCK DIAGRAM
0 1 - - - - - - ; 1-------,
SIO
*
EEPROM
VDD
ROM
3K x8
RES
2Kx8
CLK
GND
A
ALU
B
BA
Accumulator
Arithmetic circuit
B register (auxiliary register)
B register paired with accumulator
(B register higher rank)
C
Carry flag
CCR
Condition code register
CLK
Clock input pin
D register (data pointer)
D
EEPROM: Rewritable read-only memory
Power supply pin (OV)
GND
H
P
PC
RAM
RES
SIO
SP
TIC
VDD
Z
Half carry flag
(for decimal operations)
Parity flag
Program counter
Data memory
Reset input pin
Serial input/output pin
Stack poi nter
Timing and control circuit
Power supply pin (5V)
Zero flag
* EEPROM is not used as instruction
area.
PIN DESCRIPTION
250
Description
Input/Output
S-I/O
Input/Output
VDD
-
Main power source
GND
-
Circuit GND potential
Function
Serial data input/output port.
Quasi bidirectional I/O port.
Set "1" level after "Reset".
RES
Input
"Reset" has priority over every other signal.
RES input initialize the processor.
Active "0" level.
ClK
Input
External clock input
• MSM62580·
REGISTER DIAGRAM
17,
,0
17,
,01
1
Accumulator
B-register
GGR
17 , , ,
,0 I
D-register
17 , , ,
,01
Stack pointer (SP)
, ,
,0 I
Program Counter (PC)
111 ,
MEMORY MAP
~
:Emptyarea
C·ROM :Control ROM
ZP
127
:Zero page address called
by CZP instruction.
R1FH
7FH
FFFH
EOOH
RS
RAM
" I '''~ I """
W
1EH
4K
1000H
3K
R4
4
R3
3
R2
R1
RO
Rn
o
31 r---~
o
o
"""'A
PC
(a) RAM map
(BA)
(c) ROM map
(b) EEPROM map
251
• M$M62580 • - - - - - - - - - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VOO
Ta = 25°C
-0.5 to 7
V
Input Voltage
VI
Ta = 25°C
- 0.3 to VDD + 0.5
V
Output Voltage
Vo
Ta = 25°C
-0.3 to VDD +0.5
V
Storage Temperature
Tstg
Supply Voltage
o to
+70
°C
OPERATING CONDITIONS
Parameter
Symbol
Limits
Unit
Supply Voltage
VOO
4.5 to 5.5
V
Operating Temperature
TOp
o to
°C
+70
D.C. CHARACTERISTICS
(Voo = 5V± 10%, Ta = 0 to +70°C)
Parameter
Operating Current
Symbol
Conditions
Min
Typ
Max
Unit
100
f = 5 MHz
-
4
10
rnA
-0.3
-
0.5
-0.3
-
0.5
SIO
-0.3
-
0.8
ClK
2.4
-
Voo
4
-
Voo
2.0
-
Voo
ClK
low Input Voltage
High Input Voltage
RES
RES
Vil
VIH
-
-
SIO
V
V
low Output Voltage
VOL
10l MAX = 1.6mA
0
-
0.4
V
High Output Voltage
VOH
IOH MAX- -100;.A
2.4
-
VOO
V
-
-
20
pA
-
-
-1
rnA
-
15
-
pF
-
20
-
pF
Input Current (ClK, RES)
IIH1/11L1
VI=ONOO
Input Current (SIO)
IIH2/11l2
Input Capacitance
CI
Output Capacitance
Co
f= 1MHz
Ta=25°C
Notes: = ClK, RES has poll down resistance SIO has pull up resistance.
252
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM62580 •
A.C. CHARACTERISTICS
(Voo
= 5V± 10%, Ta = 0 to +70°C)
Symbol
Min
Typ
Max
Unit
ClK Cycle Time
TCY
200
-
-
ns
ClK Cycle low Width
TCl
0.4*TCY
-
0.6*TCY
ns
ClK Cycle High Width
TCH
O.4*TCY
-
0.6*TCY
ns
ClK Cycle Rise Time
TCR
-
5.0
p.S
ClK Cycle Fall Time
TCR
-
-
5.0
p.S
RES Pulse Width
TRW
8*TCY
-
-
p.S
SIO INPUT Rise Time
TSR
-
-
5.0
p's
SIO INPUT Fall Time
TSF
-
-
5.0
p.S
Parameter
Note: at output load capacitance Co
= 30pF
TIMING CHARTS
'--------TCy------~
TCl
ClK
'----TCHTCR
TCF
SIO
\ 114---RES
.
TRW
---,-.I /
~_O.8V
O.8V¥
253
• MSM62580 • - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST
MNEMONIC
FLAGS
opr
OPERATION
BYTE CYCLE
B
A+-B
1
1
*
0
A+-O
1
1
*
@O
A +- (D)
1
1
*
@O+
A+-(O), 0+-0+ 1
1
2
*
@O-
A+-(O), 0+-0-1
1
2
*
N
A+- (N)
2
2
*
N+@D
A+- (N+O)
2
3
*
#N
A+- #N
2
2
*
B
B+-A
1
1
0
D+-A
1
1
@O
(D) +- (A)
1
1
@D+
(O)+-A, 0+-0+ 1
1
2
@O-
(0)+-A,0+-0-1
1
2
N
(N) +- A
2
2
N+@O
(N+O) +- A
2
3
Rn
o +- Rn
1
2
#N
o +- #N
2
2
0
Rn +- 0
1
2
#N
Rn +- #N
2
3
@O
(BA) +- (D)
1
4
@BA
(D) +- (BA)
1
4
C
MOV A, opr
MOV opr, A
MOV 0, opr
MOV Rn, opr
MOV @BA, apr
MOV @O, apr
P
H
Z
MOV @O+, apr
#N
(D)+- # N,O+-O + 1
2
2
MOV @O+. apr
BA
(O)+-A, (0 + 1)+-B
1
3
MOVW BA. apr
@O
A+-(O), B+-(0+1)
1
3
*
MOVW BA, apr
#N
A+-#N1, B+-#N2
3
3
*
254
- - - - - - - - - - - - - - - - - - - - - - - - . MSM62580 •
MNEMONIC
FLAGS
cpr
OPERATION
BYTE CYCLE
C
XCH A. cpr
P
H
Z
B
A-B
1
2
*
0
A-O
1
2
*
@O
A .... (D)
1
2
*
N
A .... (N)
2
2
*
B
O .... B
1
2
SP
0 .... SP
1
2
XCH C. cpr
P
C ... p
1
1
*
ADD A. cpr
@O
A+- A+(O)
1
1
*
*
*
N
A+- A+(N)
2
2
*
*
*
#N
A+- A+ #N
2
2
*
*
*
@O
A+-A+(O)+C
1
1
*
*
*
N
A+-A+(N)+C
2
2
*
*
*
#N
A+-A+#N+C
2
2
*
*
*
Decimal adjust
1
1
*
*
@O
A-(D)
1
1
*
*
N
A-(N)
2
2
*
*
#N
A-#N
2
2
*
*
CMP @O. cpr
#BA
(D) - (BA)
1
4
*
*
EOR A. cpr
@O
A+- AV(O)
1
1
*
N
A+- A"'It(N)
2
2
*
#N
A+- A"It#N
2
2
*
@O
A+- AV(O)
1
1
*
N
A+- AV(N)
2
2
*
#N
A+- AV#N
2
2
*
1
1
*
2
2
*
2
2
*
XCH O. cpr
AOC A. cpr
OAA
CMP A. cpr
OR A. cpr
AND A. cpr
@O
N
#N
A
A
A
<-
A_I\(O)
<- A~#(N)
<-
AI\#N
-
*
255
• MSM62580
MNEMONIC
.----------------~-------
FLAGS
BYTE CYCLE
OPERATION
apr
C
INC apr
DEC apr
RRC apr
RLC apr
PUSH apr
POP apr
A
1
A-A+1
H
1
Z
*
,
0
0-0+1
1
1
@O
(D) - (0)+ 1
1
1
*
N
(N) - (N)+ 1
2
2
*
A
A+-A-1
1
1
*
0
0+-0-1
1
1
@O
(D) - (0)-1
1
1
*
N
(N) +- (N)-1
2
2
*
A
C;c
-+
A7 _O:J
1
1
*
*
@O
4C
-+
(0)7-0:J
1
1
*
*
N
I;C
-+
(N)7-0:J
2
2
,*
*
A
Cc +- A7 -0:;1
1
1
*
*
@O
[ C +- (0)7-"0+1
1
1
*
*
N
LC +- (N)7 -0;:1
2
2
*
*
1
3
0
P+-SP-2
(SP)+-O, SP+-SP-1
1
2
PSW
CCR+-(SP-1), A+-(SP-2),
SP+-SP+2
1
3
1
2
PSW
~P)+-A,(SP-1)+-CCR,
0
D - (SP + 1), SP - SP
JZ apr
addr
if Z=1, PC-PC+2+addr
2
213
JNZ apr
addr
if Z =P 1, PC+-PC+2+addr
2
2/3
JC apr
addr
if C=1, PC+-PC+2+addr
2
2/3
JNC apr
addr
if C =P 1, PC+-PC+2+addr
2
2/3
JB apr
baddr,addr
if(baddr) = 1,PC+- PC + 3 + addr
3
3/4
JNB apr
baddr,addr if(baddr) =P 1, PC- PC + 3 + addr
3
3/4
+1
2
3/4
3
3/4
3
3/4
Rn+-Rn-1, if Rn =P 0,
PC-PC+2+addr (n=4-7)
OJNZ apr
Rn,addr
JMNE apr
#N,addr
if (D) ". #N, PC+-PC+3+addr
JONE apr
#N,addr
if 0
256
P
'*
#N, PC+-PC+3+addr
*
*
*
*
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM62580 •
FLAGS
MNEMNIC
opr
OPERATION
BYTE CYCLE
C
JMP opr
addr
CAL opr
addr
CZP opr
addr
PC+-addr(O-4K)
2
2
2
4
(SP)+-PC+ 2,PC+-ZP,SP+-SP-2
1
4
PC+-(SP), SP+-SP + 2
1
3
No Operation
1
1
A+-O
1
1
RC
C+-O
1
1
0
SC
C+-1
1
1
1
RT
NOP
CLR opr
A
~SP)+-PC+2,
PC+-addr(O-4K)
P+-SP-2
baddr
(baddr) +- 0
2
2
SB
baddr
(baddr) +- 1
2
2
A
A+-A
1
1
C
C+-C
1
1
*
P
P+-C, if A=odd, C+-1 ELSE C+-O
1
1
*
SIN
C +- SIO
1
1
*
SOUT
SilO +- C
1
1
DELAY N + 3 CYCLES
2
3-258
CHK opr
DLY opr
#N
H
Z
1
RB
CPL opr
P
*
*
257
OKI
&emlconductor
MSM66301
OKI ORIGINAL HIGH PERFORMANCE
CMOS SINGLE-COMPONENT 8/16-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM66301 is a an new generation, high performance single component microcontroller
inplemented in sillicon gate complementary metal oxide semiconductor technology (CMOS).
Integrated within this chip are 16-bit ALU, 16K bytes of mask program ROM, 512 bytes of data RAM,
481/0 lines, built-in 16-bit timers, 1O-bit AID converter, serial 110 port, pulse width modulator (PWM),
and oscillator.
FEATURES
•
•
•
•
•
•
•
•
258
8-Bit External Data Bus Interface
16-Bit Internal Architecture
64K address space for program memory
(including 16K bytes onchip ROM)
512K address space for data memory
(including 512 bytes onchip RAM)
High speed execution
Minimum Cycle for Instruction: 400ns
(10MHz)
The Abundance of Powerful Instructions
8/16 data transfer operation
8/16 bit arithmetic operation
16(8) bit x 16(8) bit - 32(16) bit
32(16) bitl16 (8) bit - 32(16) bit
16(8) bit ± 16(8) bit -16(8) bit
8/16 logic operation
Bit operation
String operation
User stack operation
ROM table access operation
The same instruction allows both byte and
word width operation according to Data
Descriptor.
That is to say, the same algorithm and the
same source program lines are applicable to
byte and word width data manipulation with
only changing Data Descriptor.
Many Addressing Modes
•
•
•
•
•
•
•
•
•
8 Input lines, 40 Input/Output lines
Built-in 16 bit timer x 4
Each timer has the following 4 modes.
Auto reload timer mode
Clock out mode
Capture register mode
Real time output mode
Serial Port x 1 ch.
(variable bit length, baud rate generators for
transmitter & receiver)
Asyncronous normal mode
Asyncronous multi processor
communication mode
Syncronous normal mode
Syncronous multi processor
communication mode
16 bit Pulse Width Modulator x 2
Transition Detector x 4
10 bit AID converter (8 channel)
1 non-maskable interrupt, 16 maskable
interrupts
Stand-by Function
software Clock stop
software CPU stop
hardware CPU stop
64 pin Shrink DIP/64 pin plastic flat
package/68 pin PLCC
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
PIN CONFIGURATION
ADO/POO
VDD
1
VREF
AGND
PS7/AI7
P56/AI6
P55/AI5
AOS/I-'05
ADS/Poe
AOT/POT
AS/P10
P54/AI4
P53/AI3
9
PS1/All
A9/P'1
A10/P12
P50/AIO
All/Pt3
P47fTRANS3
A12/P14
P46!TRANS2
A13/P15
P45ITRANSl
A14/P16
P44/TRANSO
A15/P17
P43/PWMl
A16/P20
P42/PWMO
A17/P21
P41/TMl CK
A18/P22
P40fTMOCK
P37/TM310
RESOUT
P36!TM210
ALE
P35ITM1IO
P34ITMOIO
P33/1NTl
P32/1NTO
P3l/RXe
P3Q/TXD
P27/RXC
P26ITXC
P2S/HLDA
OSCl
GNO
P24/HOlD
---" _ _.r-
NMI
FUNCTIONAL BLOCK DIAGRAM
TMCK1
TMCKO
TMIOa
TMI02
1MI01
TMIOO
EA
READY
-ALE
-PSEN
RxD
RxD
RxC
TxC
-RD
-WR
TRANS3 TRANS2
TRANS1
TRANSB
ROM
isa:
f-
Z
0
()
-'
<:
AD7
ADO
Z
VREF
a:
UJ
AI7-AID
f-
X
UJ
AGND
A18
AS
PWM1
PWMD
tt
V G
ON
DO
H T T
o L N N
H
P5
P4
P3
P2
Pl
PO
LOT T
A 1 0
o
259
eMSM66301
e------------------------------------------------
PIN DESCRIPTION
Designation
Input/Output
Poo- P07/
ADo-AD7
I/O
Pl0-P17/
I/O
AB-A15
P20- P221
AlB-AlB
P2:vCLKOUT
P24/HOLD
I/O
P2s/HLDA
P2sITXC
P27/RxC
P301TxD
P3l/RxD
P321INTO
P33/fNjf
P34ITMOI0
P3s/TM110
P3BITM210
P37ITM310
260
I/O
Function
PO: a-bit I/O port. Each bit can be assigned to input or
output.
AD: Outputs the lower a bits of program counter during
external program memory fetch, and receives the
addressed instruction under the control of PSEN.
Also outputs the address, Outputs or inputs data
during an external data memory access
instruction, under control of ALE, RD, and WR.
P1 : 8-bit I/O port. Each bit can be assigned to input or
output.
A: Outputs the middle a bits of program counter
(PCa-1S) during external program memory fetch.
Also outputs the middle a bits of address during
an external data memory access instructions.
P2: 8-bit I/O port. Each bit can be assigned to input or
output.
A: Outputs the upper 3 bits of address during external
data memory access instructions.
CLKOUT: clock output pin. Output frequency range is
equal to or twice the system clock.
HOLD:
Input pin to request the CPU to enter the
hardware power-down state.
HOLD ACKNOWLEDGE: the HLDA signal
HLDA:
appears in reponse to the HOLD signal and
indicates that the CPU has entered the
power-down state.
Transmitter clock input pin.
TxC:
RxC:
Receiver clock input pin.
P3: a-bit I/O port. Each bit can be assigned to input or
output.
Transmitter data output pin.
TxD:
Receiver data input pin.
RxD:
Interrupt Request Input pin.
INT:
Falling edge trigger or level trigger is
selectable.
TMOIO - TM310: One of the following signals is output
or input,
• clock twice the frequency range of the 1 6
bit timer overflow
• load trigger signal to the capture register
input
• setting value output
The signal that is input or output depends on the mode.
- - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
PIN DESCRIPTION (Continued)
Designation
Input/Output
P4o/TMOCK
P4,ITM1CK
P421PWMO
I/O
P43/PWM1
P44- P47/
TRANSO - TRNS3
Function
P4: 8 bit I/O port. Each bit can be assigned to input or
output.
TMOCK, TM 1CK: clock input pins of timer 0, timer 1 .
TRNS: Transition Detector.
The input pins which sense the failing edge
and set the flag.
PWM: Pulse Wide Modulator output pin.
P50- P571
A10-A17
INPUT
P5:
AI:
8 bit input port.
analog sygnal input pin to AID converter.
RESOUT
OUTPUT
Output 'H' level when the CPU is in RESET cycle.
Reset to 'L' level by program.
ALE
OUTPUT
Address Latch
Enable:
The timing pulse to latch the lower
8 bit of the address output from
port 0 when the CPU accesses the
external data memory.
PSEN
OUTPUT
Program Store
Enable:
The strobe pulse to fetch to external program memory.
RD
OUTPUT
Output strobe activated during a BUS read.
Can be used to enable data on to the bus from the
external data memory.
WR
OUTPUT
Output strobe during a bus write.
Used as write strobe to external data memory.
READY
INPUT
Used when the CPU accesses low speed peripherals.
EA
INPUT
Normaly set to 'H' level.
If set to 'L' level, the CPU fetches the code to external
program memory.
FLT
INPUT
If FLT is 'H' level, ALE, WR, RD, PSEN are set 'H' level
when reset.
If FLT is set to 'L', ALE, WR, RD PSEN are set to floating
level when reset.
RESET
INPUT
RESET input pin
261
eMSM66301
e------------------------------------------------
PIN DESCRIPTION (Continued)
Designation
Input/Output
OSCO,OSC,
NMI
Function
Oscillation circuit consists of OSCo. OSC 1.
INPUT
non maskable interrupt input pin (falling edge)
VREF
reference voltage input pin for AID converter
AGND
ground for AID converter
VDD
system power supply
GND
ground
REGISTERS
0
15
•
ACCUMULATOR
•
CONTROL REGISTERS (CR)
ACC
psw
PROGRAM STATUS WORD
pc
PROGRAM COUNTER
~
•
LOCAL REGISTER BASE
LRB
SYSTEM STACK POINTER
ssp
POINTING REGISTERS (PR)
INDEX REGISTER1
Xl
INDEX REGISTER2
X2
DP
DATA POINTER
usp
USER STACK POINTER
•
•
LOCAL REGISTERS
erO
rl
ro
erl
rS
r2
er2
r5
r4
erS
r7
r6
SPECIAL FUNCTION REGISTERS (SFR)
All of the 1/0 functions are controlled by SFRs.Also. some of the internal functions (Timer. WDT.
etc ....) are controlled by SFRs. SFRs are located in the top of RAM space (OOOH - 007FH).
262
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [1]
Address
0000
Name
System Stack Pointer
0001
0002
local Register Base
Program Status Word
Source Index Register
0009
for Block Transfer
00 DC
0000
SSPl
R/W
8/16
FF
lRBl
FF
R/W
8/16
unknown
PSWl
RIW
8/16
00
ACCl
R/W
8/16
00
ACCH
0008
OOOB
When
reset
PSWH
Accumulator
0007
OOOA
8/16
Operation
lRBH
0005
0006
R/W
SSPH
0003
0004
Abbrebiation
Destination Index Register
00
00
SI
R/W
16
unknown
01
R/W
16
unknown
CX
R/W
16
unknown
BSDI
R/W
8
unknown
SBYCON
R/W
8
00
WDT
W
8
PRPHF
R/W
8
01
R/W
16
unknown
R/W
8/16
00
R/W
8/16
for Block Transfer
Counter Register
for Block Transfer
Source/Destination
OOOE
Bank Register
0010
Stand-By Control Register
0011
Watch Dog Timer
0012
Peripheral Control Register
0016
Work Area for Emulator
0017
0018
Interrupt Request Flag
IRQH
0019
001A
Interrupt Enable Flag
IEl
00
External Interrupt
Control Register
EXICON
00
00
IEH
001B
001C
IRQl
R/W
8
00
263
• MSM66301 . - - - - - - - - - - - - - - - - - - - - - - - - -
MSM66301 Special Function Registers [2]
Address
Name
Abbrebiation
R/W
8/16
Operation
When
reset
R/W
8
Unknown
0020
Port 0 Data Register
PO
0021
Port 0 Mode Register
POlO
R/W
8
00
0022
Port 1 Data Register
P1
R/W
8
unknown
0023
Port 1 Mode Register
P110
R/W
8
00
0024
Port 2 Data Register
P2
R/W
8
unknown
0025
Port 2 Mode Register
P210
R/W
8
00
0026
Port 2 Special Function
Control Register
P2SF
R/W
8
00
0028
Port 3 Data Register
P3
R/W
8
unknown
0029
Port 3 Mode Register
P310
R/W
8
00
002A
Port 3 Special Function
Control Register
P3SF
R/W
8
00
002C
Port 4 Data Register
P4
R/W
8
unknown
0020
Port 4 Mode Register
P410
R/W
8
00
002E
Port 4 Special Function
Control Register
P4SF
R/W
8
00
002F
Port 5
P5
R
8
0030
Timer 0 Counter
TMO
R/W
16
0031
0032
00
Timer 0 Register
TMRO
R/W
16
0033
0034
Timer 1 Counter
TM1
R/W
16
Timer 1 Register
TMR1
R/W
16
Timer 2 Counter
TM2
R/W
16
Timer 2 Register
TMR2
R/W
16
Timer 3 Counter
TM3
R/W
16
003F
264
00
00
0030
003E
00
00
0038
003C
00
00
0039
003A
00
00
0037
0038
00
00
0035
0036
00
00
00
Timer 3 Register
TMR3
R/W
16
00
00
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [3]
Address
Name
Abbrebiation
R/W
8/16
Operation
When
reset
0040
Timer 0 Control Register
TCONO
R/W
8
00
0041
Timer 1 Control Register
TCON1
R/W
8
00
0042
Timer 2 Control Register
TCON2
R/W
8
00
0043
Timer 3 Control Register
TCON3
R/W
8
00
0046
Transition Detector Reg.
TRNS
R/W
8
00
001"3
Stop Mode Buffer Flag
W
8
265
e MSM66301
e-----------------------MSM66301 Special Function Registers [4]
Address
Name
Abbrebiation
R/W
8/16
Operation
When
reset
TRNS
R/W
8
00
0046
Transition Detec\or
0048
Transmitter Clock Generator
STTM
R/W
8
00
0049
Transmitter Clock Generator
Control Register
STTMR
R/W
8
00
004A
Transmitter Control Register
STTMC
RIW
8
00
004C
Receiver Clock Generator
SRTM
RIW
8
00
0040
Receiver Clock Generator
Control Register
SRTMR
RIW
8
00
004E
Receiver Control Register
SRTMC
R/W
8
00
0050
Transmitter Mode Control Register
STCON
R/W
8
00
0051
Transmitter Data Buffer
STBUF
W
8
unknown
0054
Receiver Mode Control Register
SRCON
R/W
8
00
0055
Receiver Data Buffer
SRBUF
R
8
unknown
0056
Receiver'Eroor Status Register
SRSTAT
R
8
00
0058
AID Scanning Mode Register
ADSCAN
RIW
8
00
0059
AID Select Mode Register
ADSEL
R/W
8
00
0060
AID Convert Result Register 0
ADCROL
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
ADCROH
0061
0062
AID Convert Result Register 1
ADCR1H
0063
0064
AID Convert Result Register 2
AID Convert Result Register 3
AID Convert Result Register 4
AID Convert Result Register 5
AID Convert Result Register 6
006F
266
ADCR6L
ADCR6H
006D
006E
ADCR5L
ADCR5H
006B
006C
ADCR4L
ADCR4H
0069
006A
ADCR3L
ADCR3H
0067
0068
ADCR2L
ADCR2H
0065
0066
ADCR1L
AID Convert Result Register 7
ADCR7L
ADCR7H
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [5]
Address
0070
Name
PWM 0 Counter
R/W
8/16
Operation
R/W
8/16
PWM 0 Register
00
00
PWMROL
R/W
PWM 1 Counter
00
00
PWMC1L
R/W
8/16
PWMC1H
0075
0076
8/16
PWMROH
0073
0074
PWM 1 Register
00
00
PWMR1L
R/W
8/16
PWMR1H
0077
When
reset
00
PWMCOL
PWMCOH
0071
0072
Abbrebiation
00
0078
PWM 0 Control Register
PWCONO
R/W
8
00
007A
PWM 1 Control Register
PWCON1
R/W
8
00
267
-MSM66301
-~----------------------------------------------
ADDRESSING MODE
The MSM66301 supports 512KB (64KB X8BANKs) 05 data space and 64KB of program space
with verious types of addressing methods. These methods divide into the following types.
1. RAM ADDRESSING (FOR DATA SPACE)
1 .1 Register Direct Addressing
ROR
DP
t ...
n
-- •
..
V////ffiQ~W//ffil
1.2 Displacement Addressing
a) Zero Page
[~
L
A,
10H
L------n~~////1
OOOH
0010H
b) Direct Page
_
ex.
51
A,
offXX10H
xxOOH
,
,,
RAM
\0_--------
xxl0H
1.3 Pointing Register Indirect Addressing
a) Data Pointer (DP) Indirect
[~
SLL
[DP]
DP
b) User Stack Pointer (USP) Indirect
r - - ex.
SRL
10H
=;==
[U5P]
;
I
0-255
USP
J-
--.."
268
I
RAM
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
c)
Index register (X1 ,X2) Indirect
ex.
300H
INC
[
[X 1)
...~
X1
SSP, #
1~~2~7F~H~~
1.4 Immediate Addressing
MOV
2. ROM ADDRESSING (FOR PROGRAM SPACE)
2.1 Direct Addressing
[~
JMP
2.2 Pointing Register Indirect Addressing
a) Date Pointer (DP) Indirect
[~
LC
[DP]
--I
DP
b) User Stack Pointer (USP) Indirect
~.-------------------------------------------------------~
J
c)
10H
[USP]
Pointing Register (X1, X2, DP, USP) Indirect with 16bit displacement
~. -------------------------------------------------------~
CMPC
300H
[X1]
X1
0-65535
~J)
269
e--------------------------------------------------
eMSM66301
INSTRUCTIONS
Data Transfer
Instruction
L
ST
Function
A,-
A
A,.
A
_, A
-- •
-- •
-- -•
MOV
MOV
" #
MOV
er. *
er
MOV
d, •
(d)
MOV
DP, •
DP
MOV
X1, •
X1
MOV
X2, •
X2
MOV
USP,.
WSP
MOV
PSW,.
PSW
MOV
SSP,.
SSP
MOV
LRB,.
LRB
CLR
*
SWAP
*
Instruction
Function
--- •
LB
A, *
AL
STB
A,*
AL
A
MOVB
A, *
AI---
1m me.
MOVB
*,A
*
MOVB
*, #
MOVB
r, •
MOVB
d, •
MOVB
PSWO, *
MOVB
SCB,'
CLRB
•
-- -- •
-- •
-- •
-- •
-- •
---- •
--
*
-• --- •
AL
Imme.
r
-- •
(d)
PSWO
SCB
-- •
-- •
*
*
0
•
--
0
A'5-8~A7-0
SWAPB
A7-4~A3-0
XCHGB
AL~'
XCHG
A,
A~*
XNBL
A,
A3-0-*3-0
TRNS USP, LRB
USP'5-3
USP2-0
TRNS LRB, USP
LRB'2""o
LRB'5-'3
-------
LRB'2-0
0
USP'5-3
0
Push & Pop
Instruction
Function
PUSHU
*
POPU
A
PUSHS
*
POPS
*
270
---. --
Instruction
Function
•
USER STACK
PUSHUB
•
•
A
USER STACK
POPUB
A
AL
*
SYSTEM STACK
SYSTEM STACK
---
USER STACK
USER STACK
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
Rotate & Shift
Instruction
Function
ROL
*
Rotate
ROR
*
Rotate
SLL
*
Shift
SRL
*
Shift
SRA
*
Shift
-
-
Instruction
Function
ROLB
•
Rotate
RORB
*
Rotate
Logical
SLLB
*
Shift
Logical
SRLB
*
Shift
Arithmetic
SRAB
*
Shift
-
-
-
-
Logical
Logical
Arithmetic
Increment & Decrement
Instruction
Function
INC
*
*
DEC
*
*
-
Instruction
Function
*+1
INCB
*
*
*-1
DECB
*
*
-
-
*+1
*- 1
ROM Table Reference
Instruction
Function
LC
A,*
A -
CMPC
A,*
A-* (ROM)
* (ROM)
Instruction
Function
LCB
A, *
AL
CMPCB
A, *
AL -* (ROM)
-
* (ROM)
271
• MSM66301 • - - - - - - - - - - - - - - - - - - - - - - - - Arithmetic Operation
Instruction
Function
MUL
er1: A
DIV
erO: A
-
-
-
Instruction
Function
AXerO
MULB
A
erO: Aler2
DIVB
A
-
ALxrO
-
AlrO
ADD
A, -
A
A+-
ADDB
A, *
AL
ADD
-, A
- - -+A
ADDB
*,A
-
ADD
-, d
- + (d)
ADDB
*, d
ADD
*, #
--
- + Imme.
ADDB
-, #
-
ADC
A, -
A
A+- +C
ADCB
A,*
AL
ADC
*, A
*
* +A+C
ADCB
*, A
ADC
-, d
-
- + (d) +C
ADCB
-, d
ADC
*, #
*
• + Imme. +C
ADCB
*, #
SUB
A, -
A
SUBB
A, -
SUB
*,A
*
--A
SUBB
*,A
SUB
*, d
*
* - (d)
SUBB
*, d
SUB
-, #
- -Imme.
SUBB
*, #
- - - -Imme.
SBC
A, *
A
A-*-C
SBCB
A, *
AL
SBC
*,A
*
*-A-C
SBCB
*,A
SBC
*, d
*
-- (d)-C
SBCB
*, d
SBC
*, #
- -Imme.-C
SBCB
-, #
272
--
-
-
-*
-
A--
--
AL +-
- +AL
* + (d)
---
* +Imme.
AL +- +C
* +AL +C
- + (d) +C
*
- +Imme. +C
AL
.--
AL --
- -AL
- - (d)
• -
AL - * - C
* - AL-C
* - (d)-C
*
*
-
* -Imme. - C
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
Logical Operation
Instruction
Function
Instruction
Function
AND
A,-
A ...... Aand-
ANDB
A,-
AND
*, A
-
...... * and A
ANDB
-,A
AND
*, d
*
...... * and (d)
ANDB
-, d
AND
*, #
*
...... * and Imme.
ANDB
-, #
-
OR
A,-
A
......
Aor.
ORB
A,-
AL
OR
-, A
- ......
- or A
ORB
*, A
*
<-
-orAL
OR
-, d
- ......
* or (d)
ORB
*, d
*
<-
- or (d)
OR
-, #
-
...... * or Imme .
ORB
*,
#
*
<-
• or Imme.
XOR
A,-
A ...... Axor-
XORB
A,-
AL
XOR
',A
*
...... * xor A
XORB
',A
•
XOR
-, d
- ......
• xor (d)
XORB
-, d
XOR
*, #
-
...... - xor Imme.
·
XORB
*, #
*
AL
...... Aland -
• ......
• ......
- and Al
* and (d)
- and Imme.
<-
...... Alor-
...... Al xor<-
• xor Al
<-
* xor (d)
<-
• xor Imme.
Comparison
Instruction
Function
Instruction
Function
- *
CMP
A,-
A--
CMPB
A,*
Al
CMP
-,A
.-A
CMPB
',A
--Al
CMP
-, d
* - (d)
CMPB
*, d
*- (d)
CMP
*,
.-Imme.
CMPB
-, #
·-Imme.
#
273
• MSM66301 . - - - - - - - - - - - - - - - - - - - - - - - - Stack Operation
Instruction
Function
ADD A. [+USP]
USP ..-. USP +2, A ..-. A + [USP]
ADC A. [+USP]
USP ..-. USP +2, A ..-. A + [USP] +C
SUB A. [+USP]
USP ..-. USP +2,A ..-. A- [USP]
SBC A. [+USP]
USP ..-. USP +2,A ..-. A- [USP]-C
AND A. [+USP]
USP ..-. USP +2, A ..-. Aand [USP]
OR A. [+USP]
USP ..-. USP +2, A ..-. Aor [USP]
XOR A. [+USP]
USP ..-. USP +2, A ..-. Axor [USP]
CMP A. [+USP]
USP
..-.
USP + 2, A - [USP]
Decimal Adjust
Instruction
Function
DAA
Decimal Adjust for Addition
DAS
Decimal Adjust for Substruct
Bit Operation
Instruction
Function
Instruction
Function
SBR
*
bit ..-. 1
SB
*
bit ..-. 1
RBR
*
bit ..-. 0
RB
*
bit ..-. 0
MBR
C,-
C ..-. bit
MB
C,-
C
MBR
*, C
bit ..-. C
MB
*,C
bit ..-. C
TRB
*
Z ..-. bit
Execute
Instruction
EX
274
Function
*
Execute Specified Data as the Instruction
-
bit
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
Jump & Call
Instruction
adrs
SJ
...
•
I
Function
Instruction
Function
Short Jump
SCAl
Jump
CAL
adrs
•
Short Call
Call Subroutine
Jump if 'ole'
JC
EO, adrs
Jump if'='
JC
NE, adrs
JC
lE, adrs
Jumpif'< ='
JC
IT, adrs
Jump if
'<'
JC
GE, adrs
Jumpif'
> ='
JC
GT, adrs
Jump if
'<'
JBS bit, adrs
Jump if bit-on
JBR bit, adrs
Jump if bit-off
JRNZ, DP, adrs
loop Function
VCAl adrs
Vector Call
Return
Instruction
Function
RT
Return from Subroutine
RTI
Return from Interrupt
String Operation
Function
Instruction
SMOVI
String Transfer with Increasing Pointers
SMOVD
String Transfer with Decreasing Pointers
SCMP
String Compare
Others
Function
Instruction
-
Instruction
1
SC
C
SS
STACK FLAG
NOP
No Operation
-
1
Function
-
0
RC
C
BRK
Software Reset
(Note)
'#' and 'imme.'
'-'and'-+'
Addressing expression (See Addressing mode)
Immediate value
Bit-shift direction
275
eMSM66301
e-----------------------------------------------------
ABSOLUTE MAXIMUM RATING (TARGET SPECIFICATION)
Item
Power Supply Voltage
Input Voltage
Symbol
Condition
VDD
VI
Value
Unit
-0.3 - 7.0
V
-0.3 - VDD
V
Output Voltage
Va
-0.3 - VDD
V
Analog Reference Voltage
VR
-0.3 - VDD
V
Analog Input Voltage
VAl
-0.3 - VR
V
Ta = 25°C, per Package
400 Max.
mW
Power Desipation
PD
Ta = 25°C, per Output
50 Max.
mW
TSTG
-
-55 -150
°c
Symbol
Condition
Value
Unit
Power Supply Voltage
VDD
f (OSC) ~ 10 MHz
4.5 - 5.5
V
Data Retention Voltage
VOOH
f (OSC) = 0 Hz
2-6
V
4.5 - VDD
V
0-0.2
V
VAG - VR
V
Storage Temperature
Ta" 25°C
OPERATING RANGE
Item
Analog Reference Voltage
VR
Analog Ground Voltage
VAG
Analog Input Voltage
VAl
MaS Load
Fan Out
N
30
Poo - P07
2
P,0
1
TTL Load
276
-
P47
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
DC CHARACTERISTICS (TARGET SPECIFICATION)
(Voo = 5V
±10%, Ta
= -40 -
Typ.
Max.
Unit
+85"C)
Item
Symbol
Condition
Min.
"H" Input Voltage *1, *2, *3, *7
VIH
-
2.4
VOO
V
"H" Input Voltage *6, *7, *9
VIH
-
4.0
VOO
V
"L" Input Voltage * 1, *2, *3, *7
VIL
-
-3.0
0.8
V
"L" Input Voltage *6, *8, *9
VIL
-
-0.3
0.8
V
"H" Output Voltage *1,*2,*4,*5
VOH
10 = -30 fJA
4.2
V
"H" Output Voltage *10
VOH
10
= -15 fJA
4.2
V
"L" Output Voltage *1, *4
VOL
10 = 3.2 mA
0.45
V
"L" Output Voltage *2, *5
VOL
10 = 1.6 mA
0.45
V
"L" Output Voltage *10
VOL
10 = -15 fJA
0.4
V
Input Current *1,*2,*3,*7,*8
IIH/IILI
VI = Voo/OV
1/-1
fJA
I n put Cu rrent *6
IIH/IIL
VI
= Voo/OV
1/-20
fJA
Input Current *9
IIH/IIL
VI = Voo/OV
10/-10
fJA
"H" Output Current *1, *2, *4, *5
10H
VO= 2.4V
Analog Reference Voltage
Supply Resistance
RR
VAG = OV
Analog Input Leak Current
RLAI
VAG =OV
RAI
1
Mn
CAl
A/O Converter Active
and
In Sampling Condition
10
pF
C,
f = 1MHz, Ta = 25"C
5
pF
f = 1MHz, Ta = 25"C
7
pF
VOO = 2V, No Load, Ta =25"C
0.2
fJA
No Load
1
fJA
f (OSC) = 10MHz, No Load
20
mA
Analog Input Impedance
Input Capacity
Output Capacity
Co
Current Consumption (Stop)
Current Consumption
*1
*2
*3
*4
*5
Specification
Specification
Specification
Specification
Specification
applied
applied
applied
applied
applied
IOOS
100
to
to
to
to
to
PO
P1, P2, P3, P4
P5
ALE, PSEN, RD, WR
RESOUT
*6
*7
*8
*9
*10
Specification
Specification
Specification
Specification
Specification
mA
-0.2
Kn
16
±1
applied
applied
applied
applied
applied
to
to
to
to
to
fJA
RES, NMI
REAOY, EA
F LT
OSC o
OSC,
277
eMSM66301
e----------------------------------------------------
AC CHARACTERISTICS (TARGET SPECIFICATION)
External Program Memory Control
(VDD = 5V ±10%, Ta = -40 - +85°C)
Symbol
Condition
Min.
OSC Clock Pulse Width
trpW
-
50
nS
ALE Pulse Width
tAW
-
100
nS
PSEN Pulse Width
tpw
-
250
nS
Item
Typ.
Max.
Unit
PSEN Pulse Delay Time
tPAD
"L" Address Set Up Time
tAAS
"L" Address Hold Time
tAAH
"H" Address Delay Time
tAAD
"H" Address Hold Time
tAPH
trpW-10
Instruction Set Up Time
tiS
80
nS
Instruction Hold Time
tlH
50
nS
nS
tcpW-30
tcpW+30
nS
trpW-30
tcpW+30
nS
trpW+30
nS
trpW+40
nS
CL = 50pF
External Data Memory Control
Item
tcpW+20
(VDD = 5V ±10%, Ta = -40 - +85°C)
Symbol
Condition
Min.
Typ.
OSC Clock Pulse Width
trpW
-
50
nS
ALE Pulse Width
tAW
-
100
nS
RD Pulse Width
tRW
-
250
nS
WR Pulse Width
tww
-
200
nS
Max.
Unit
RD Pulse Delay Time
tRAD
tcpW+20
nS
WR Pulse Delay Time
tWAD
tcpW+20
nS
"L" Address Set Up Time
tAAS
tcpW-30
trpW+30
nS
"L" Address Hold Time
tAAH
tcpW-30
trpW+30
nS
"H" Address Delay Time
tAAD
tcpW+30
nS
tcpW-10
tcpW+40
nS
2trpW-10
2trpW+40
nS
"H" Address Hold Time (RD) tARH
"H" Address Hold Time (WR) tAWH
CL = 50pF
Memory Data Set Up Time
tMS
80
nS
Memory Data Hold Time
tMH
50
nS
Data Delay Time
tDD
Data Hold Time
tDH
278
2trpW-10
tcpW+30
nS
2trpW+40
nS
----------------------------------------------------eMSM66301 e
AID CONVERSION CHARACTERISTICS (TARGET SPECIFICATION)
(VDD = 5V ±10%,)
Item
Resolution
Symbol
Min.
n
Zero Point Error
EZS
Fu" Scale Error
EFS
Linearity Error
EL
VR = VDD
VAG = GND =OV
Analog Input
Impedance ~ 5Kn
Ta
Input Crosstalk
Channel Conversion Speed
Condition
tc
= 25°C
64
Typ.
Max.
Unit
10
Bits
±2
LSB
±2
LSB
±3
LSB
±2
LSB
320
~s/CH
279
·MSM~01
.----------------------------------------------------
TIMING CHART
ClK
ALE
tAW
PSEN
tPAD
I
/
ADO-7
PC0-7
I!tAAS tAAH
tpw
INSTo-7
)
~tlS
I
/
A8-15
I
tlH
I
-I
I
\
PC8-15
M
~
I
RD
tRAD
I
/
ADO-7
tRW
I
/
\.
\
I-- tMS
ItAAS tAAH
II
/
tMH I
l
\
'j
A8-18
tAAD
DP8-18
1\
f-----
I
I
H
WR
I
ADO-7
/
\
tWAD
D~O-7
1~Ast;:!f
I
A8-18
\
~
280
tww
D OUTO-7
I
\
/
-tDH-1
DP 8-18
f
~tAWH--l
8 BIT SERIES (INTEL COMPATIBLE)
[I
OKI
semiconductor
MSM80C35/48
MSM80C39/49
MSM80C40/50
CMOS a-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM80C48/MSM80C49/MSM80C50 microcontroller is a low-power, high-performance
8-bit single chip device implemented in silicon gate complementary metal oxide semiconductor
technology. Integrated within these chips are 8K/16K/32K bits of mask program ROM,
512/1024/2048 bits of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program
memory and data paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction set, thereby optimizing power down, port data transfer, decrement and port float
functions.
Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages (GSK).
FEATURES
• Lower power consumption enabled by CMOS
silicon gate process
• Completely static operation
• Improved power-down feature
• Minimum instruction cycle 1 .36 J,Ls (11 MHz)
@VCC=+5V±10%
11 MHz version of MSM80C40/50 (6 MHz <
XTAL 1.2 < 11 MHz) is under development.
•
•
•
•
•
•
• Every signal input terminal is provided with a
Schmitt circuit, except XTAL 1 Pin.
• Every signal output terminal is capable of
driving a standard TTL, except XTAL2 Pin.
• 111 instructions
• All instructions are usable even during
execution of external ROM instructions.
• Operation facility
Addition, logical operations, and decimal
adjust
1 K x 8 bits
• Program memory (ROM)
(MSM80C48)
2K x 8 bits
(MSM80C49)
4K x 8 bits
(MSM80C50)
64 x 8 bits
• Data memory (RAM)
(MSM80C48)
128 x 8 bits
(MSM80C49)
256 x 8 bits
(MSM80C50)
•
•
•
•
•
•
•
Two sets of working registers
External and timer interrupts
Two test inputs
Built-in 8-bit timer counter
Extendable external memory and I/O ports
Input/output ports
Input/output ports
- 8 bits x 2
Data bus input/output
-8bitsx1
Single-step execution function
Every signal input terminal is provided with a
Schmitt circuit, except XTAL 2 Pin
Every signal output terminal is capable of
driving a standard TTL, except X'tal 2 Pin.
Wide range of operating voltage, from +2.5V
to+6VofVCC·
High noise margin action
Two kinds of package; 40-pin plastiC DIP and
44-pin plastic flat package
Compatible with Intel's 8048, 8049 and 8050
283
• MSM80C3S/48, 80C39/49, 80C40/S0 . , - - - - - - - - - - - - - -
FUNCTIONAL BLOCK DIAGRAM
(PORT 2)
DATA STORE
INITIALIZE
DATA MEMORY tRAM)
64 I( MSM80C48RS
a
CPU MEMORY
SEPARATE
, 28
SINGLE
STEP
II
8 MSM8OC49RS
256" 8 MSM8OC50RS
PIN CONFIGURATION
(Top View) 40 Lead Plastic DIP
TO
XTAL1
RESET
T'
P2,
P2,
INT
P2,
P2,
XTAL2
ss
EA
AD
PSEN
ALE
08.
08,
(Top View) 44 Lead Plastic FLAT
Vee
Ne
P2,
P2.
P2,
P',
P',
P',
P',
P',
P',
P',
P',
08,
08,
Vss
P2,
Vss
X'TAL1
DB,
X'TAL2
DB.
DB,
DB,
~~~~~~~~-r--
Pin Name
P1 0 - P1,
P20 - P2,
DBo - DB,
TO, T1
INT
RD
WR
284
P2,
P2,
Vee
TO
PROG
P2,
P2,
P2,
P2,
P2,
T,
VDD
08,
08,
PROG
:
:
:
:
Input/output port (PORT1)
Input/output port (PORT2)
Data bus port (BUS PORT)
Test
: Interrupt
: Read
: Write
ALE
PSEN
RESET
Ss
EA
XTAL 1,2
: Address Latch Enable
: Program Store Enable
: Reset
: Single Step
: ROM Mode
: Crystal Controlled
Oscillator
- - - - - - - - - - - - - -..... MSM80C3S/48, 80C39/49, 80C40/S0 .'
PIN DESCRIPTION
Designation
Input/Output
Function
P1o-P1,
(PORT 1)
Input/Output
8-bit Quasi-bidirectional port
P2o-P2,
(PORT 2)
Input/Output
8-bit Quasi-bidirectional port
The high -order fou r bi ts of external program memory add resses can be
output from P20-P23, to which the I/O expander MSM82C43RS may also
be connected,
DBo-DB,
(BUS)
Input/Output
Bidirectional port
The low-order eight bits of external program memory address can be
output from this port, and the addressed instruction is fetched under the
control of PSEN signal. Also, the external data memory address is output, and
data is read and written synchronously using RD and WR signals.
The port can also serve as either a statically latched output port or a
non-latch ing input port.
TO
(Test 0)
Input/Output
The input can be tested with the conditional jump instructions JTO and
JNTO. The execution of the ENTO ClK instruction causes a clock output to
be generated.
T1
Input
The input can be tested with the conditional jump instructions JT1 and
JNT1. The execution of a STRT CNT instruction causes an internal
counter inputlo be activated.
INT
(interrupt)
Input
Interrupt input. If interrupt is enabled, INTinput initiates an interrupt.
Interrupt is disabled after a reset.
Also testable with a JNI instruction. Can be used to terminate the
power-down mode. (Active"O"level)
RD
(Read)
Output
Wff
A signal to read data from external data memory. (Active "O"level)
A signal to write data to external data memory. (Active "0" level)
(Write)
This signal is generated in each cycle. It may be used as a clock output.
External data memory or external program memory is addressed upon the
falling edge. Forthe external ROM, this signal is used to latch the bus port
data upon the ALE signal rise-up after the execution of the OUTl BUS, A
instruction.
ALE
Address &
Data latch
Clock
PSEN
Program
Store Enable
Output
A signal to fetch an instruction from external program memory
(Active "0" level)
RESET
Output
(RESET) input initialize the processor. (Active "O"level)
Used to term inate the power-down mode.
SS
(Single Step)
Output
A program is executed step by step. This pin can also be used to control
internal oscillation when the power-down mode is reset.
(Active "O"level)
EA
(External Access)
Input
PROG
(Expander Strobe)
Output
When held at high level, all instructions are fetched from external memory.
(Active "1 " level)
This output strobes the MSM82C43RS I/O expander.
285
• MSM80C35/48, 80C39/49, 80C40/50 . ' - - - - - - - - - - - - - -
PIN DESCRIPTION (CONT.)
Designation
Input/Output
XTAL 1
(Crystal 1)
Input
XTAL2
(Crystal 2)
Output
VCC
-
Power supply terminal
VDD
-
Standby control input. Normally, "1" level. When set to "0" level,
oscillation is stopped and processor goes into standby mode.
VSS
-
GND
Function
One side olthe crystal input forthe internal oscillator. An external source can
also be input.
Other side of Crystal input for internal oscillator.
Note: The required RESET pulse duration is at least two machine cycles under the condition that the power supply
and the oscillator have been stabilized.
286
--------------_e MSM80C35/48, 80C39/49, 80C40/50 e
ADDED FUNCTIONS OF MSM80C48, MSM80C49 AND MSM80C50
The MSM80C48, MSM80C49 and
MSM80C50 basically incorporate the capabilities of Intel's 8048, 8049, and 8050 plus the following new functions:
1.
Power-Down Mode Enhancements
1 ,1 Power-down by software
(1)
(2)
(3)
Clock (See item 4, "Power-down mode", for
details.)
a. Crystal-controlled oscillator halt (HLTS
instruction)
Power requirements can be minimized.
b. Clock supply halt (HALT instruction)
Restart is accomplished without oscillator wait.
1/0 ports (See Table 4-1 and 4-2 for
details.)
1/0 port floating instructions
Power consumption resulting from inputsl
outputs can be minimized with FL T and
FL TT instructions.
Port floating is cancelled QLexecuting
FRES instruction, "0" level at INT pin or "0"
level at RESrr pin.
Six types of power-down can be done by a
combination of HLTS/HAL T and FL TIFLTT
instructions.
ing up the rise time of the output signals.
When these ports are used as input ports,
the internal pullup resistance becomes approximately 9 k 0 when input data is "1 ".
The internal pullup resistance rises to ap-·
proximately 100 kO when input data is "0".
Thus, a high noise margin can be obtained by
selecting the impedance and thus the outflow of
current is minimized whenever these ports are
used as output or input ports.
3.3 Clock generation control via the SS
terminal
When the crystal-controlled oscillator is
halted in the HLTS or hardware power-down
mode, the SS terminal is pulled down by a resistor of 20 - 50 kO, while its internal pullup resistor of 200 - 500 kn is isolated from Vec. When
the power-down mode is cancelled, the internal
resistor of the SS terminal is changed from pulldown to pullup. Consequently, the CPU can be
halted for any period of time until the crystalcontrolled oscillator resumes normal oscillation
when a capacitor is connected to the SS terminal.
4.
Power-Down Mode
1.2 Power-down by hardware (See 4.3,
Power-down mode by VDD pin utilization
for details.)
Crystal-controlled oscillators can be halted
by controlling the VDD terminal, thereby floating
all 1/0 ports for minimum power consumption.
The MSM80C48, MSM80C49, and
MSM80C50 power-down mode can be enabled
in 2 different ways-through software by a combination of clock control and port floating
instructions, and through hardware by control of
the VDD pin.
2.
4.1 Software power-down mode
Power-down mode can be done by a combination of the following instructions.
Additional Instructions (11)
HLTS
HALT
FLT
FLTT
FRES
MOVA, P1
3.
MOVA, P2
MOVP1, @R3
MOVP1 P, @ R3
DEC @ Rr
DJNZ @ R, addr
Improved Uses of BUS Po - 7, P1 0 P20 - 7, and SS terminals
(1 )
Instruction
code:
3.2 P1 0 - and P20 The MSM80C48, MSM80C49 and
MSM80C50 are designed to minimize power
consumption when P1 0 - 7 and P20 - 7 are used
as input/output ports, to maximize the performance of CMOS.
When these ports are used as output ports,
the acceleration circuit is actuated only when
output data changes from "0" to "1 ", thus speed7
I0
0 0 0I0 0 0
1
I
Description:
7,
3.1 BUSPo-7
The MSM80C48, MSM80C49, and
MSM80C50 remove the limitation on the use of
OUTL BUS, A instructions during the external
ROM access mode by having an independent
data latch and external ROM mode address
latch in BUS Po - 7.
Consequently, there is no need to relocate
bus port instructions when in the external ROM
access mode.
7
HALT (clock supply halt to control circuit)
(2)
Although crystal-controlled
oscillator operation is continued, the clock supply to
the CPU control circuit is
halted and CPU operations
suspended. When cancelling
this software mode, restart is
accomplished without oscillator wait. Timing charts
are outlined in Figs. 4-1 and
4-2.
HLTS (oscillation stop)
Instruction
code:
rl-1-0-0--0-1-0-0--1-0-'1
.
.
.
Description:
The oscillator operation is
halted and CPU operations
suspended. In cancelling
this power down mode, connecting a capacitor to the SS
pin enables a reasonable
287
• MSM80C35/48, 80C39/49, 80C40/50 . , - - - - - - - - - - - - - -
(3)
wait period to be accomplished before normal operation is resumed. [Except iT
the case of using the RESE
pin]
Timing charts are outlined in
Figs. 4-3 and 4-4.
FLT (floating P1 0 - 7, P20 - 7, and BPo - 7)
Instruction
code:
Description:
~
Internal ROM
mode
PI
Floating
P2
Floating
BP
Floating
External ROM mode
Floating
P20 -
3
P2. -
7
operation
floating
Operation
Details of IC pin status as a result of executing the FLT instruction are shown in Table
(4)
4-1.
FLTT (floating of all output pins)
Instruction
code:
4.2 Cancellation of software power-down
Description:
I~
Internal ROM
mode
External ROM mode
ALE
Floating
Operation
PSEN
Floating
Operation
PROG
Floating
Floating
WR
Floating
Floating
RD
Floating
Floating
Floating
Floating
TO OUT
PI
P2
Floating
Floating
Floating
P20 P2, -
3
7
operation
floating
BP
Floating
Operation
XTAL
Operation
Operation
Details of IC pin status as a result of executing the FLTT instruction are shown in Table
4-2.
Example 1: Power-down mode accomplished by stopping oscillation.
o Setting by execution of
HLTS [82H] instruction.
Example 2: Power-down mode accomplished by stopping the clock
supply to the CPU control
circuit.
o Setting by execution of
HALT [01 H] instruction.
Example 3: Power-down mode by floating
of P1 0 - 7, P20 - 7 and BPo 7, and subsequent stopping of
CPU oscillation.
288
o Setting by first executing
the FLT[A2H] instruction
and then the HLTS[82H] instruction.
Example 4: Power-down mode by floating
P10 - 7, P20 - 7 and BPo - 7,
and then stopping the clock
supply to the CPU control circuit.
o Setting by first executing
the FLT[A2H] instruction,
and then the HALT[01 H] instruction.
Example 5: Power-down mode by floating
all output pins, followed by
stopping oscillation.
o Setting by first executing
the FLTT[C2H] instruction
followed by execution of
the HLTS[82H] instruction.
Example 6: Power-down mode by floating
all output pins, followed by
stopping of the clock supply to
the CPU control circuit.
o Setting by first executing
the FLTT[C2H] instruction,
followed by execution of
the HALT[01 H] instruction.
mode
The power-down mode status outlined
above in examples 1 to 6 can be cancelled by
using either the interrupt pin or the RESET pin.
(1) Use of the INT pin during external interrupt
enabled mode (Le. following execution of
EN I instruction).
o The clock generator is activated and the
CPU started J:!.P.. when a "0" level is applied to the INT pin. If this "0" level is
maintained until at least 2 ALE output
signals occur, an external interrupt is
generated, and execution proceeds from
address 3. If, however, the power-down
mode has been done during the interrupt
processing routine, execution is
resumed just after the power-down
instruction.
(2) Use of the INT pin during external interrupt
disabled mode (Le. following execution of
DIS I instruction or hardware reset)
o The clock generator is activated and the
CPU started J:!.P.. when a "0" level is applied to the INT pin. If this "0" level is
maintained until at least 2 ALE output
signals occur, execution is resumed just
after the power-down instruction.
(3) Use of the RESET pin
o The clock generator is activated and the
CPU started....!:!.P....Y'hen a "0" level is applied to the RESET pin. If this "0" level is
maintained until at least 2 ALE output
signals occur, the CPU is reset and execution proceeds from address O. In case
cancellation is done in oscillation stop
mode, the "0" level must be input to the
RESET PIN until oscillation is stabilized.
--------------_e MSM80C35/48, 80C39/49, 80C40/50 e
Table 4-1
Pin No.
Details of Pin Status Following Execution of FLT Instruction
Pin Name
Internal ROM
External ROM
lP
TO
Active
Active
2P
XTAL1
Acti)le
Active
3P
XTAL2
Active
Active
4P
RESET
Active
Active
5P
SS
200 - 500 kG pullup
200 - 500 kG pullup
6P
INT
Active
Active
7P
EA
Active
Active
8P
RD
Active
Active
9P
PSEN
Active
Active
lOP
WR
Active
Active
Active
llP
ALE
Active
l2P
DBO
Floating
Active
l3P
DBl
Floating
Active
l4P
DB2
Floating
Active
l5P
DB3
Floating
Active
16P
DB4
Floating
Active
17P
DB5
Floating
Active
l8P
DB6
Floating
Active
19P
DB7
Floating
Active
20P
VSS
o [V)
o [V)
21P
P20
Floating
Active
22P
P21
Floating
Active
23P
P22
Floating
Active
24P
P23
Floating
Active
25P
PROG
Active
Active
26P
VDD
"1 "level
"1 "level
27P
P10
Floating
Floating
28P
P11
Floating
Floating
29P
P12
Floating
Floating
30P
P13
Floating
Floating
31P
P14
Floating
Floating
32P
P15
Floating
Floating
33P
P16
Floating
Floating
34P
P17
Floating
Floating
35P
P24
Floating
Floating
36P
P25
Floating
Floating
37P
P26
Floating
Floating
38P
P27
Floating
Floating
39P
T1
Active
Active
40P
Vee
+2 to +6 [V)
+2 to +6 [V)
Note: The FLT mode itself is reset by executing the FRES instruction, or supplying "O"level to INT or RESET pin.
289
• MSM80C35/48, 80C39/49, 80C40/50 . - - - - - - - - - - - - - Table 4-2
Pin No.
Details of Pin Status Following Execution of FLTT Instruction
Pin Name
Internal ROM
External ROM
1P
TO
Floating if output enabled
Floating if output enabled
Active
2P
XTAL1
Active
3P
XTAL2
Active
Active
4P
RESET
Active
Active
5P
SS
200 to 500 kD pullup
200 to 500 kD pullup
6P
INT
Active
Active
7P
EA
Active
Active
8P
RD
Floating
Floating
9P
PSEN
Floating
Active
10P
WR
Floating
Floating
11P
ALE
Floating
Active
12P
DBO
Floating
Active
13P
DB1
Floating
Active
14P
DB2
Floating
Active
15P
DB3
Floating
Active
16P
DB4
Floating
Active
17P
DB5
Floating
Active
18P
DB6
Floating
Active
19P
Active
OB7
Floating
20P
VSS
o [V]
o [V]
21P
P20
Floating
Active
22P
P21
Floating
Active
23P
P22
Floating
Active
24P
P23
Floating
Active
25P
PROG
Floating
Floating
26P
VDD
"1 "level
"1 "level
27P
P10
Floating
Floating
28P
P11
Floating
Floating
29P
P12
Floating
Floating
30P
P13
Floating
Floating
31P
P14
Floating
Floating
32P
P15
Floating
Floating
33P
P16
Floating
Floating
34P
P17
Floating
Floating
35P
P24
Floating
Floating
36P
P25
Floating
Floating
37P
P26
Floating
Floating
38P
P27
Floating
Floating
39P
T1
Active
Active
40P
Vee
+2.5 to +6 [V]
+2.5 to +6 [V]
Note: The FLTT mode itself is reset by executing the FRES instruction, or supplying "0" level to INT or RESET pin.
290
-
- - - - - - - - - - - - - -...... MSM80C35/48, 80C39/49, 80C40/50 •
I Tl I T2 I T3 I
1 I
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IRUN---1I---++I-+--+---I---+I-_I~-+XTAL l ' 2 I
I
I
f1
I
I
'I I i
.
I
I II I: II
I
I
I I
I
I
I
11
is--- I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
RESET
O-r--+--r---+-------.... --r--J...-+-T-T-~I
I
I
I
I
I
I
i
I
I
I
I
I
I
I•
RESET EXECUTE I
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
,
I
I
I
I
I
I
I
I
• Cancellation Condition: Use RESET pin.
ALE
X'TAL 1
m
I
Fig,4·1
1
1,':
I.
: Tl I T2; T3 :
HALT [01 H] Instruction Execution Timing Chart
T4
(f
I
nnnnnnnnnnnnn
nnnnJL
oIIJUUpUUpUUJW.Uli~
"
I
1'1
I
I
I,
if
'
I
:
I
rr-w-J-I
,
I
ALE
I
I
:
I
o IIi III 1Ii II
I '+,-+--11--+...1
1
I I I
I
I
I
i
IHALT EXECUTEI--I
I
I I I
I
I
I
I
STOP--fl:
I
I
IRUN
I
I
I
I
CPU MODE ~RUI':I:
,
I
I
I
I i'
I
I
I
I
X'TAL 1 . 2
i
I
is
I
IRUN--+-.L--!-I+1--+I---r--i----TI--i,-""1ItI
I
I
I
I
I I
I
I
I
I
1
I
I
I
(
I
I
I
INT
I
I
I
I
I
I
I
I
I
I
I
I
.,.--I..-j-""--I--.--rI
I
I
I
,
I
,
,
I
1
I
I
I
I
INTER~UPT EXpCUTE i
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I:
m::
I
O+-..,--r -t------- -
iii
!!
I
• Cancellation Condition: Use tNT pin.
Fig,4-2
X'TAL 1
:
HALT [01 H] Instruction Execution Timing Chart
: .Tl : T2 ; 13 ;
iI-I-'-T-"'4'--_ _4-'-"'-I..,.,...'-+-~+-'_"'_i-:..:'4-.:..=..+-=--'-I-...:..:~.:..=..I-'-~,.:..::;........
1
Ol~uuruu~uu~~
nnnnnnnnnn
1 I
I
I
I
I :
IIIJll
ri-h II
I
0:
I
i
It..w,. I
I. I
I
HLTS EXECUTE...J
1
CPU MODE ~IIRUN--rSTOPff OISC ..I.. I
I
I
'--,EVOKE I
X'TAL 1 . 2 -r----!RUN
1 STOP(l--j
:,::
I
I
I
I
RESET pin must bel
held at "0" level
I
I
I
I
I
1 I
I
I
1
until the oscillation I
RESET
I
I
I.L
becomes norma!.
I
ALE
o....--r-t-- 1---- '
ss
::
1
i
oI
_1
I
I
I
I
1
I
SS 200-500Kn :
I
PULLUP
I
i
-t--r-i --r-t-~--t-
;.'- - - - I t - - + :-+--I--I--+I--ill--t-I-+I--+I--!-I-t--I
I
I
:
I
:
:
:
:
:
I _
I I
I'
I,
I
I
I
r SS 200I...._t--t--+: RE~ET ~XEqUT~
I : -:
'500Kn
I
I
SS 20-50Kn PULLDOWN
• Cancellation Condition: Use RESET pin.
Fig,4-3
I
I
I II
I RUN--r--~I---+--+--+--II II
I RUN-+--+-...;....~--+----ilI I
I I'
I
I
I
I
I
I
I
I
I
I
PULLUP
HLTS [82H] Instruction Execution Timing Chart
291
• MSM80C3S/48, 80C39/49, 80C40/S0 . - - - - - - - - - - - - - -
X'TAL 1
ALE
~~r-:JtJaJ
I
I
1 I
o
I
I
I
I
I
I
I
I
I I'
I. I
I
I
'II
I
I
'
I
I
I
I
I
.1
ill
I
I
I HLTSEXECUTE-l
I
CPU MODE f----;RUN---'-STOPf! I
I. I
SC
X'TAL 1 ·2 +---iRUI'l--l-STOPfr-1°
E"OKE
I
I
I
I
When a 0.47 /LF capacitor is-4 50- ~ I
connected to the SS pin,
60ms
I
50-60 ms wait
WAIT
I
I
,
+
1
1!
I
I
I
I
I
I
I
I
I
I
1
1
I
I
I
I
I
I
!
O~--~--~--~-----·
I
I
I
I
1
SS
1 I
o
I
_!
SS 200-500Kn
I
PULLUP
II.
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I!
I
II
I ' I .1
I
I
I rhl
I
I
I
I
I
:
I RUN
:
I
' RUN
1
:
I
I
I
1
I
I
I
I
I
I
I
I rTI i
i
I I I w....--L
I
I
I
I
I
I
I
I
I
I
I
i I
I
I
I
I:
I
I
I
1
!!
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
II
I
I
I
I
I
I
I
i
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
'~--r-~--~--~--~--~I
I
I
I
I
I
I
,
I
SS 200-'
I
I
500Kn PULLUP 1
I
I
I
I
1
,
I
I
1
I
II!
I
I
INTERRUPT EXECUTE I
"
I
I
I
I
I -:
SS 20-50Kn PULLDOWN
* Cancellation Condition: Use INT pin.
Fig.4-4
HLTS [82H] Instruction Execution Timing Chart
4.3 Hardware power-down mode
In the MSM80C48, MSM80C49 and
MSM80C50, forcing the level at the VDD pin [pin
26] to a "0" during either external ROM or internal ROM mode results in suspension of the oscillator function and subsequent floating (high
impedance) of all the I/O pins except the RESET,
SS and XTAL 1/2 pins. The CPU is thereby
stopped while maintaining internal status.
Details of the IC pin status at this time are outlined in Table 4-3.
4.4 Cancellation of hardWare power-down
mode
(1) Use of RESET pin
o The clock generator is activated and the
CPU started up when a "1" level is applied
to th~ pin while a "0" level is input to
the RESET pin. If this "0" level is kept applied to the RESET pin until oscillation
become stable, the CPU will be reset and
will start executing from address O. The
timing chart is outlined inFig. 4-5.
(2) Use of the TNT pin during external interrupt
enabled status (i.e. following execution of
EN I instruction)
o The clock generator is activated and the
CPU started up when a "1" level is applied
to the VDD pin while a "0" level is applied to
the INT pin.
292
If this "0" level is maintained until at least 2
ALE output signals occur, an external interrupt is generated, and execution starts from
address 3.
However, if the power-down mode is started
during an interrupt processing routine, execution will be continued on the next instruction after the present instruction. The timing
chart is outlined in Fig. 4-6.
(3) Use of the INT pin during external interrupt
disabled mode (i.e. following execution of
DIS I instruction or hardware reset)
o The clock generator is activated and the
CPU started up when a "1" level is applied
to the VDD pin while a "0" level is applied to
the INT pin. If this "0" level is maintained
until at least 2 ALE output signals occur, execution is continued on the next instruction
after the present instruction. The timing
chart is outlined in Fig. 4-6.
(4) Use of VDD pin only
o The clock generator is activated and the
CPU started up when a "1" level is applied
to the VDD pin while a "1" leveJ..!§. also applied to both the RESET and INT pins. In
this case, execution is resumed from the
stopped position. The timing chart is outlined in Fig. 4-7.
---------------e. MSM80C35/48, 80C39/49, 80C40/50 •
Table 4-3
Pin No.
Details of Pin Status during Hardware Power-Down Mode
Pin Name
Normal Operation
(VDD = "1 "level)
Power Down Mode
(V DO = "0" level)
1P
TO
Active
Floating if output enabled
2P
XTAL1
Active
Active
3P
XTAL2
Active
Active
4P
RESET
Aclive
Active
5P
SS
200 to 500 kO pullup
20 to 50 kO pulldown
Active
6P
INT
Active
7P
EA
Active
Active
8P
RD
Active
Floating
9P
PSEN
Active
Floating
10P
WR
Active
Floating
11 P
ALE
Active
Floating
12P
DBO
Active
Floating
13P
DB1
Active
Floating
14P
DB2
Active
Floating
15P
DB3
Active
Floating
16P
DB4
Active
Floating
17P
DB5
Active
Floating
18P
DB6
Active
Floating
19P
DB7
Active
Floating
20P
VSS
o [V)
o [V)
21P
P20
Active
Floating
22P
P21
Active
Floating
23P
P22
Active
Floating
24P
P23
Active
Floating
25P
PROG
Active
Floating
26P
VDD
"1 "level
"O"level
27P
P10
Active
Floating
28P
P11
Active
Floating
29P
P12
Active
Floating
30P
P13
Active
Floating
31P
P14
Active
Floating
32P
P15
Active
Floating
33P
P16
Active
Floating
34P
PH
Active
Floating
35P
P24
Active
Floating
36P
P25
Active
Floating
37P
P26
Active
Floating
38P
P27
Active
Floating
39P
T1
Active
Active
40P
Vee
+2 to +6 [VI
+2 to +6 [V)
293
• MSM80C3S/48, 80C39/49, 80C40/S0 . - - - - - - - - - - - - - -
.1
Ml
: Tl 1T2 : T3
or
M2
i
Ml
IS T4
X'tall . 2
~~~J1L
ALE
O I
l~:
:
:
IFLOA~TING
I
I
I
I
I
,
I
I
,I
...L-..!R U N--L-!.-STOP.(\-\~I_ _+'_.-+---i--'--'--+I
,
'I I
IOSC I
-t-tR U I':I---r--l-S TOP{1-1 EV OK'=E......-t--+---I---t---II
I
,I
1___
I
I
I
RESET pin must be held!
I
I
I I
at "0" level u nti I the
,
oscillation becomes
I
normal
'
CPU MODE
X'tal 1 . 2
r
I
I
1
I
I
"
t t l
I
I
,
I
,
,
"
iI
,
II
I
I'
I
I
I
I
I
I
i
I
I
I
1
~g>:,'r'l'~ I
I
I
I
I I I
I
I
I
I
I
!%4J Y _ I I~-----I--I-...,--I_...l-LL ___ -+--t-T-t--.L111:1~'~'
'111111111111
I
I
'Oml
I'
I
'
:
I
I
I
I
I
I
0-'--"-,I'
I
1,..-"1"-4-,.--t-T-....
o
1
H
I
o
I
I
I
I
'
I
I
SS 200-500Kn
PULLUP
I
I
SS 200-500Kn PULLUP
I,
SS 20-50Kn PULLDOWN
* Cancellation Condition: Use RESET pin.
Fig.4-5
:Tl
X'tal
ALE
CPU MODE
X'tall' 2
i ;r2 i Tli
If T4
o
'
I
I
IFLOATIN~,..-!
I
I
I'
I
.LL..ln---<~
I
~RUN-ti-STOPH~:---~I~I---t-~-.-~
..L.-.J R U r\i...l.+-STOP-! H
I
I
I! I
When a 0.47 IlF capacitor is
connected to the S"S" pin,
50-60 ms wait.
, ,
I
VDD
Hardware Power-Down Mode Timing Chart
~~~J11
l
1
o
OSC "'L..---tI--i----+-+--4-1
IEVOKE I
50I
60ms
WAIT
r-
I
I!
'M~Mulm
~%')W~
1 I
I
,
I
I
o t--r --t..lo:¥<'"4;.....~---.....;..-+---+-......~~
1 I
,
o
I
SS 200-500Kn
PULLUP
500Kn PULLUP
SS 20-50Kn PULLDOWN
* Cancellation Condition: Use the I NT pin.
Fig.4-6
294
I I
I
I
I
,
I
I
I
,
I
I
I
I
I RESET EXECUTE
Hardware Power-Down Mode Timing Chart
I
I
I
- - - - - - - - - - - - - -....... MSM80C35/48, 80C39/49, 80C40/50 •
I
T1
I·
X'tal
ALE
CPU MODE
X'tal 1 . 2
I
I
T2 I T3
I
I
I'
(f
T4
~~J.JJ!
1 I
I
I
FLOATIN9~
;i'~~
O~:
I
t-tRUN-f-i--STOP~S
I
I
1
-I--+RUN-++-STOP_PSC EVOKE
I
I
I ,
I
When a 0.47 I'F c~citor is -J 50-
I
I
connected to the S-S- pin,
50-60 ms wait.
I
RUN
I
I
I
I
I
:
I
I
I
: :
I
I-- I
60 ms
WAITf
I
1
VDD
I
I
I
I
I I
I I
~O or 1~
o i"""'f"
I
I
1 I
I
I
I
I
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(j-·.J-----T--1--L...- .... -+-~--rI
I
I
I
I
I
I
I
-_t--I-..J-II
I
I
I
I
I
I
I
I
I
I
I
I
I
...
I
o +-+--+--~--------_:--J....-t_-.l.-~- ...J.....-... -f_-..j.--1--:--1I
I
I
I
I
I
i; II i: II II I I1 II II
1 I
I
I
I
I
I
I
I
O,--~-~-~--------i-~-~--I--f--~-~-+--~-~-..J-~1 I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I!
I
I
I
i I
~I
SS200-500Kn
I
PULLUP
I SS200I.
500Kn PULLUP
I
I
RESTART----'---I
SS20-50Kn PULLDOWN
* Cancellation Condition: Use the VDD pin on condition
RESET and INT pins are in "1" level.
Fig.4-7
Hardware Power-Down Mode Timing Chart
295
~
MSMSOC4S/MSMSOC49/MSMSOC50 INSTRUCTION TABLE
'"a>
CD
L
H
0
0
o () 0 0
1
o 0 0 1
2
00 1 0
3
00 1 1
NOP
HALT
Added
OUTLBUS
A
JBOaddr
4
01 00
5
o 1 0 1
ADD A,
# data
JMP
ENI
ADDCA,
# data
CALL
MOVA,
# data
JMP
6
7
o 1 1 0
01 1 1
8
1 0 0 0
1 0 0 1
9
A
1 0 1 0
DECA
INSA,BUS
INA,P1
INA,P2
B
1 01 1
C
1 1 00
MOVDA,
Pp
0000
1
INC@,RO INC@,R1
DISI
JTFaddr
INCA
INCRr
EN TCNTI JNTO addr
CLRA
XCHA,Rr
0001
2
XCHA@,
RO
XCHA@,
R1
XCHD
A,@R1
5
ORLA,
@RO
ORLA,
@R1
MOVA, T
ANLA,
@RO
ANLA,
@R1
JB2addr
JBl addr
CALL
DIS TCNTI
ORLA,
# data
JMP
STRTCNT JNTl addr
ANLA,
# data
CALL
JTO addr
CPLA
OUTLP1,
A
SWAP A
OUTLP2,
A
STATT
JTl addr
DAA
......
ANLA,Rr'
CO
o
n
Added
JMP
STOP
TCNT
MOVA,P2
Added
CALL
ENTOClK
ADDA,
@RO
ADD A,
@R1
MOVT,A
ADDCA,
@RO
ADDCA,
@R1
J83addr
MOVXA,
@RO
MOVXA,
@R1
Added
RET
JMP
CLRFO
JNl addr
MOVX
@RO,A
MOVX
@R1,A
J84addr
RETR
CALL
CLRFO
JNZaddr
MOV
@RO,A
MOV
@R1,A
FLT
Added
MOVPA,
@A
JMP
CLRF1
JMPP@A
CALL
CPLF1
JFOaddr
R3Added
JMP
SEI.RBO
JZaddr
XRLA,
#data
CALL
SELRB1
Added
MOVP3A,
@A
JMP
SELMBO
JB7 addr
MOVP1,@
R3Added
CALL
SELMB1
MOVA,?1
RRCA
ADDA,Rr
RRA
ADDCA.Rr
t
......
CJI
o
JFl addr
•
01 1 1
8
ORLBUS,
# data
ORLP1,
# data
ORLP2,
# data
ORLDPp,
A
ANLBUS,
# data
ANLP1,
# data
ANLP2,
# data
ANLO Pp,
CLRC
CPLC
MOVRr,A
HLTS
1 000
9
1 001
A
1 0 1 0
B
MOV @ RO, MOV @R1,
J8Saddr
#data
#data
MOVR,
#data
1 0 1 1
C
DEC@RO DEC@R1
Added
Added
FLTT
Added
MOV?1 P,@
MOVA,
PSW
DECAf
1 1 00
0
XRLA,
@RO
XRLA,
@R1
JB6addr
MOVPSW
A
XRLA,Rr
JNCaddr
RLA
DJNZRr
JCaddr
RLCA
MOVA,Ar
1 1 0 1
E
DJNZ@RO DJNZ@R1
Added
Added
FRES
1 1 1 0
F
1111
o
n
Co)
~
o 1 1 0
7
~
n
Co)
CO
ORLA.Rr
1 01
6
•
31:
en
31:
~
MOVDPp,
A
o 1 00
o
F
1111
CO
XCHD
A,@RO
001 1
4
E
1 1 1 0
CJI
......
00 1 0
3
0
1 1 0 1
MOVA,
@RO
MOVA,
@R1
A
--------------_e. MSM80C35/48, 80C39/49, 80C40/50 •
EXPLANATION OF INSTRUCTION SYMBOLS
Symbols are listed below.
A
Accumulator
AC
Auxiliary carry
addr
12-bit program memory address or
its part
Bit indicator (b = 0 - 7)
Bb
BS
Bank switch
BUS PORT
BUS
Carry
C
ClK
Clock
CNT
Counter
D
4-bit data
data
8-bit numerical value
DBF
Memory data bank flip-flop
FO, F1
FO flag and F1 flag
Interrupt
I
Program counter
Port indicator (p = 4 - 7)
Program status word
Resister indicator (r = 0 - 7)
Stack pointer
Timer
Timer flag
Test pins TO and T1
External RAM
Symbol denoting immediate data
Symbol denoting indirect address
Denotes contents of X
Denotes contents addressed by X
Transference
PC
Pp
PSW
Rr
SP
T
TF
TO, T1
X
#
@
(X)
((X»
LIST OF INSTRUCTIONS
Class ification
U)
Instruction Code
Mnemonic
07 D. 0, D. 03 0, D. Do
~
.!:
c::
.2
~
"c.~
£
0
0
..:
Byte Cycle
Description
ADDA.Rr
0
1
1
0
1
r,
r.
ro
68-6F
1
1
(AC). (C), (A) - (A) + (Rr)
ADD A, @Rr
0
1
1
0
0
0
0
ro
80-61
1
1
(AC), (C), (A) - (A) + «Rr»
ADDA.#data
0
d7
0
de
0
d,
0
d.
0
d3
0
d,
1
d.
1
do
03
Byte 2
2
2
(AC). (C). (A) - (A) + data
ADDCA.Rr
0
1
1
1
1
r,
r.
ro
78-7F
1
1
(AC). (C). (A) - (A) + (Rr) + (C)
ADDCA.@Rr
0
1
1
1
0
0
0
ro
70-71
1
1
(AC), (C), (A) -(A) + «Rr» + (C)
AD DC A, #data
0
d7
0
d.
0
d,
1
d.
0
d3
1
0
d, d.
1
do
13
Byte 2
2
2
(AC), (C), (A) - (A) + data + (C)
ANLA, Rr
0
1
0
1
1
r,
r.
ro
58-SF
1
1
(A) - (A) AND (Rr)
ANLA,@Rr
0
1
0
1
0
0
0
ro
50-51
1
1
(A) - (A) AND «Rr»
ANLA, #data
0
d7
1
d.
0
d,
1
d.
0
d3
0
d,
1
d.
1
do
53
Byte 2
2
2
(A) - (A) AND data
c::
~
(J
Hexadecimal
ORLA,Rr
0
1
0
0
1
r,
r.
ro
48-4F
1
1
(A) - (A) OR (Rr)
ORLA,@Rr
0
1
0
0
0
0
0
ro
40-41
1
1
(A) - (A) OR «Rr»
ORLA, #data
0
d7
1
de
0
d,
0 0
d. d3
0
d,
1
d.
1
do
43
Byte 2
2
2
(A) - (A) OR data
XRLA, Rr
1
1
0
1
1
ro
D8-DF
1
1
(A) - (A) XOR (Rr)
XRLA,@Rr
1
1
0
1
0
"
r.
0
0
ro
00-01
1
1
(A) -(A) XOR «Rr»
XRLA,#data
1
d7
1
d.
0
1
d, d.
0
d3
0
d,
1
d.
1
do
03
Byte 2
2
2
(A) - (A) XOR data
INCA
0
0
0
1
0
1
1
1
17
1
1
(A)-(A)+1
DECA
0
0
0
0
0
1
1
1
07
1
1
(A)-(A)-1
CLRA
0
0
1
0
0
1
1
1
27
1
1
(A)-O
CPLA
0
0
1
1
0
1
1
1
37
1
1
DAA
0
1
0
1
0
1
1
1
57
1
1
(A)-(A)
Add 6 to bits 0 - 3 when contents of
accumulator bits 0 - 3 exceed 9 or
when auxiliary carry (AC) is 1. Then
add 6 to bits 4 - 7 when the result of
adding the carry from the 10werO - 3
exceeds 9, or when carry (C) is 1.
Set 1 in the carry flag if an overflow
is generated in the end resu It, orwhen
the carry prior to adjustment is 1.
297
• MSM80C35/48, 80C39/49, 80C40/50 . - - - - - - - - - - - - - -
LIST OF INSTRUCTIONS (CONT.)
Classification
--
'"
§
l=
"
.5;
'"c:
Instruction Code
Mnemonic
0, D. D. 04 0, 0, 0, Do
Hexadecimal
Byte Cycle
(A.-,) ::; (Ao-,)
SWAP A
0
1
0
0
0
1
1
1
47
1
1
RLA
1
1
1
0
0
1
1
1
E7
1
1
q
RLCA
1
1
1
1
0
1
1
1
F7
1
1
L@-1 A, A6 As A4 A3 Al AI AojJ
c:
~
"c.
Description
A7 A6 As A4 A3 Al AI AoP
Rotate accumulator contents to the
left by 1 bit.
Rotate accu mulator contents with
carry to the left by 1 bit.
0
.9
.!!!
E
"
""
~
RRA
0
1
1
1
0
1
1
1
77
1
1
RRCA
0
1
1
0
0
1
1
1
67
1
1
Ao~
qA7 A6 As A4 A, Al AI
Rotate accumulator contents to the
right by 1 bit.
l..@-j A7 A6 As A4 A, A2 AI ~
Rotate accumulator contents with
carrytotheright by 1 bit.
'c:"
~
~
.5;
INA,P1
0
0
0
0
1
0
0
1
09
1
2
(A) -(PH
INA,P2
0
0
0
0
1
0
1
0
OA
1
2
(A) -(P2)
OUTLP1, A
0
0
1
1
1
0
0
1
39
1
2
(P1) -(A)
OUTLP2,A
0
0
1
1
1
0
1
0
3A
1
2
(P2) -(A)
ANL P1, #data
1
d,
0
d.
1
0
d. d.
1
d,
0
d,
0
d,
1
do
99
Byte 2
2
2
(P1) - (P1) AND data
ANL P2, #data
1
d,
0
d.
0
d.
1 1
d4 d,
0
d,
1
d,
0
do
9A
Byte 2
2
2
(P2) - (P2) AND data
ORL P1, #data
d, d. d. d4 d, d, d, do
1
0
0
0
1
0
0
1
89
Byte 2
2
2
(P1) -(P1) OR data
ORL P2, #data
1
d,
0
d.
0
d5
0
d4
1
d,
0
d,
1
d,
0
do
8A
Byte 2
2
2
(P2) - (P2) OR data
INSA, BUS
0
0
0
0
1
0
0
0
08
1
2
(A) -(BUS)
OUTLBUS,A
0
0
0
0
0
0
1
0
02
1
2
(BUS) -(A)
ANL BUS, #data
1
d,
0
d.
0
d.
1 1
d4 d3
0
d,
0
d,
0
do
98
Byte 2
2
2
(BUS) - (BUS) AND data
ORL BUS, #data
1
d,
0
d.
0
d.
0
d.
1
d3
0
d,
0
d,
0
do
88
Byte 2
2
2
(BUS) - (BUS) OR data
MOVDA,Pp
0
0
0
0
1
1
p,
Po
OC-OF
1
2
(Ao-3) - (Pp) p=4-7
(A4-')-0
MOVDPp,A
0
0
1
1
1
1
p,
Po
3C-3F
1
2
(Pp) -(Ao-,) p=4-7
ANLDPp,A
1
0
0
1
1
1
p,
Po
9C-9F
1
2
(Pp) -(Pp) AND (Ao-3) p=4-7
ORLDPp,A
1
0
0
0
1
1
p,
Po
8C-8F
1
2
(Pp) -(Pp) OR (Ao-,) p=4-7
INCRr
0
0
0
1
1
r,
r,
ro
18-1F
1
1
(Rr) -(Rr)+1
-m:8~
INC@Rr
0
0
0
1
0
0
0
ro
10-11
1
1
«Rr))-«Rr))+1
II> i!!.l=
0:: o.5~
DECRr
1
1
0
0
1
ro
C8-CF
1
1
(Rr) -(Rr)-1
DEC@Rr
1
1
0
0
0
"0
r,
0
ro
CO-C1
1
1
«Rr))-«Rr))-1
a10 a •
a, aa
aa
a5
0
a4
0
a3
1
a,
0
a,
0
ao
4-E4
Byte 2
2
2
(PCa-,o) -addr8-10
(PCo-,) -addrO-7
(PC,,)-DBF
1
1
0
0
1
1
B3
1
2
(PCo-,) -«A))
:;
c.
:;
~
:;
c.
E
'"
~c:c:
"oeg
.~g
.c:t=
JMPaddr
~'"
JMPP@A
c:"
""
0Il=
a:a.~
298
1
0
- - - - - - - - - - - - - - . MSM80C35/48, 80C39/49, 80C40/50 •
LIST OF INSTRUCTIONS (CONT.)
Classification
Instruction Code
Mnemonic
0, D. Os D. 0, 0, 0, Do
DJNZ Rr, addr
1
a,
1
a.
1
as
0
a.
1
a,
r,
a,
r,
a,
ro
ao
Hexadecimal
E8-EF
Byte 2
Byte Cycle
2
2
Description
(Rr)
(PCo-,)
(PC)
-(Rr)-1
-((Rr))-1
-addril(Ar)~O
-(PC) + 2 if (Rr)
~O
1
a,
1
a.
1 0
as a.
0
a,
0
a,
0
a,
ro
ao
EO-E1
Byte 2
2
2
((Ar))
(PCo-,)
(PC)
JCaddr
1
a,
1
a.
1 1
as a.
0
a,
1
a,
1
a,
0
ao
F6
Byte 2
2
2
(PCo-,)
(PC)
i1C~1
-addr
-(PC) +2iIC~O
JNCaddr
1
a,
1
a.
1
a,
0
a.
0 1
a, a,
1
a,
0
ao
E6
Byte 2
2
2
(PCo-,)
(PC)
iIC~O
-addr
-(PC) +2iIC~1
JZaddr
1
a,
1 0
a. a,
0
a.
0 1
a, a,
1
a,
0
ao
C6
Byte 2
2
2
(PCo-,)
(PC)
-addr
iIA~O
-(PC) +2iIA;,O
JNZaddr
1
a,
0 0
a. as
1
a.
0
a,
1
a,
1
a,
0
ao
96
Byte 2
2
2
(PCo-,)
(PC)
iIA;,O
-addr
-(PC) +2 ilA ~O
~
JTOaddr
0
a,
0
a.
1 1
as a.
0
a,
1
a,
1
a,
0
ao
36
Byte 2
2
2
(PCo-,)
(PC)
ifTO~1
-addr
-(PC) +2 iITO~O
'"e:
"ee:
JNTOaddr
0
a,
0
a.
1 0
as a.
0
a,
1
a,
1
a,
0
ao
26
Byte 2
2
2
(PCo-,)
(PC)
ifTO~O
-addr
-(PC) + 2 ilTO ~ 1
JT1 addr
0
a,
1 0
a. 8s
1
a.
0
a,
1
a,
1
a,
0
ao
56
Byte 2
2
2
(PCo-,)
(PC)
-addr
ifT1 ~1
-(PC) + 2 ifT1 ~ 0
JNT1 addr
0
a,
1
a.
0
a,
0 0
a. a,
1
a,
1
a,
0
ao
46
Byte 2
2
2
(PCo-,)
(PC)
ifT1 ~O
-addr
-(PC) + 2 ilT1 ~ 1
JFOaddr
1
a,
0
a.
1 1
as a.
0
a,
1
a,
1
a,
0
ao
B6
Byte 2
2
2
(PCo-,)
(PC)
iIFO~1
-addr
-(PC) +2iIFO~O
JF1 addr
0
a,
1
a.
1 1
as a.
0
a,
1
a,
1
a,
0
ao
76
Byte 2
2
2
(PCo-,)
(PC)
ilF1 ~1
-addr
-(PC) +2i1F1 ~O
JTFaddr
0
a,
0
a.
0 1
a, a.
0
a,
1
a,
1
a,
0
ao
16
Byte 2
2
2
(PCo-,)
TF
(PC)
-addr}
-0
ifTF~1
-(PC) +2iITF~O
JNladdr
1
a7
0 0
a. as
0
a.
0
a,
1
a,
1
a,
0
ao
86
Byte 2
2
2
(PCo-,)
(PC)
-addr
il INT ~ 0
-(PC)+2 il INT ~1
JBbaddr
b, b, bo
a, a. a,
1
a.
0
a,
0
a,
1
a,
0
ao
12-F2
Byte 2
2
2
(PCo-,)
(PC)
ilBb~1
-addr
-(PC)+2 il Bb ~O
CALLaddr
a" a. a. 1 0
a, a. as a. a,
1
a,
0
a,
0
ao
14-F4
Byte 2
2
2
((SP))
(PC.-,o)
(PCo--)
(PC,,)
(SP)
DJNZ @Rr,addr
'"c:
.Q
ti
.5
:E
m
e:c:
"'"
:"I::::
~~
"",
:0:;0
-addril((Ar))~O
-(PC) +2 il((Rr)) ~O
-(PC) + 2, (PSW .--)
-addr8-10
-addrO-7
-DBF
-(SP)+1
AET
1
0
0
0
0
0
1
1
83
1
2
(SP)
(PC)
AETA
1
0
0
1
0
0
1
1
93
1
2
(SP)
-(SP)-1
(PC)
-liSP))
(PSW.-,) -((SP)) INT END
CLRC
1
0
0
1
0
1
1
1
97
1
1
(C)
CPLC
1
0
1
0
0
1
1
1
A7
1
1
(C)
-(e)
~~
CLAFO
1
0
0
0
0
1
0
1
85
1
1
(FO)
-0
,,,OJ
CPLFO
1
0
0
1
0
1
0
1
95
1
1
(FO)
-(FO)"
CLAF1
1
0
1
0
0
1
0
1
A5
1
1
(F1)
-0
CPLF1
1
0
1
1
0
1
0
1
B5
1
1
(F1l
-(m
MOVA,Ar
1
1
1
1
1
r,
r,
ro
F8-FF
1
1
(A)
-(Ar)
MOVA,@Ar
1
1
1
1
0
0
0
ro
FO-F1
1
1
(A)
-(Ar))
MOVA,#data
0 0 1 0 0 0
1
d, d. d, d. d, d, d,
1
do
23
Byte 2
2
2
(A)
-data
CI).E
c:
0'"
:.;:::1::
g.2
u:Ole:
.-
~~
~£
!::g
l!ll:;
.. :g
0'-
-(SP)-1
-liSP))
-0
299
• MSM80C35/48, 80C39/49, 80C40/50 . ' - - - - - - - - - - - - - -
LIST OF INSTRUCTIONS (CONT.)
Class ilication
Instruction Code
Mnemonic
07 0, 0, D. 03 0, 0, Do
Hexadecimal
Byte Cycle
Description
MOVRr,A
1
0
1
0
1
r,
r,
ro
A8-AF
1
1
(Rr)
-(A)
MOV@Rr,A
1
0
1
0
0
0
0
ro
AO-A1
1
1
«Rr))
-(A)
MOV Rr, #data
1
d7
0
d,
1
d,
1
d.
1
d3
d,
"
r,
d,
ro
do
B8-BF
Byte 2
2
2
(Rr)
-data
MOV @Rr, #data
1
d7
0
d,
1
d.
1
d.
0
d3
0
d,
0
d,
ro
do
BO-B1
Byte 2
2
2
«Rr))
-data
-(PSW)
MOVA,PSW
1
1
0
0
0
1
1
1
C7
1
1
(A)
~
MOVPSW,A
1
1
0
1
0
1
1
1
07
1
1
(PSW)
-(A)
~
.!.,
XCHA,Rr
0
0
1
0
1
r,
r,
ro
28-2F
1
1
(A)
!:;(Rr)
.S;
XCHA,@Rr
0
0
1
0
0
0
0
ro
20-21
1
1
(A)
!:;«Rr))
XCHDA,@Rr
0
0
1
1
0
0
0
ro
30-31
1
1
(Ao-,.)!:;«Rro-3))
~
MOVX,6,,@Rr
1
0
0
0
0
0
0
ro
80-81
1
2
(A)
-«Rr)) External RAM
c
MOVX@Rr,A
1
0
0
1
0
0
0
ro
90-91
1
2
«Rr))
-(A) External RAM
MOVPA,@A
1
0
1
0
0
0
1
1
A3
1
2
(A)
-«PC,-,o, A))
MOVP3A,@A
1
1
1
0
0
0
1
1
E3
1
2
(A)
-«PCol1,A))
MOVP1 P,@R3
1
1
0
0
0
0
1
1
C3
1
2
(P1)
-«(PCo-7)-«R3)) ))
MOV P1,@R3
1
1
1
1
0
0
1
1
F3
1
2
(P1)
-«R3»
MOVA,P1
0
1
1
0
0
0
1
1
63
1
1
(A)
-(P1) Latch data
MOVA,P2
0
1
1
1
0
0
1
1
73
1
1
(A)
-(P2) Latch data
EN TCNTI
0
0
1
0
0
1
0
1
25
1
1
TINT Enable FIF -1
.,e:
e:
~
DISTCNTI
0
0
1
1
0
1
0
1
35
1
1
TINT Enable FIF-o
ENI
0
0
0
0
0
1
0
1
05
1
1
EXINT Enable F/F-1
DISI
0
0
0
1
0
1
0
1
15
1
1
EXINT Enable F/F-o
.,e:
SELRBO
1
1
0
0
0
1
0
1
C5
1
1
(BS)
-0
SELRB1
1
1
0
1
0
1
0
1
05
1
1
(BS)
-1
~
SELMBO
1
1
1
0
0
1
0
1
E5
1
1
(DBF)
-0
SELMB1
1
1
1
1
0
1
0
1
F5
1
1
(DBF)
-1
ENTOCLK
0
1
1
1
0
1
0
1
75
1
1
TO
-1/3XTAL 1
FLT
1
0
1
0
0
0
1
0
A2
1
1
P1, P2, BUS Floating
.2
U
.S;
~e:
0
U
FLTT
1
1
0
0
0
0
1
0
C2
1
1
CPU Output Signal Floating
FRES
1
1
1
0
0
0
1
0
E2
1
1
FLT,FLTTRESET
HLT
0
0
0
0
0
0
0
1
01
1
1
CPU Control Clock Stop
HALTS
1
0
0
0
0
0
1
0
82
1
1
XTAL 1·2 Stop
MOVA,T
0
1
0
0
0
0
1
0
42
1
1
(A)
-(T)
MOVT,A
0
1
1
0
0
0
1
0
62
1
1
(T)
-(A)
;:::2
STRTT
0
1
0
1
0
1
0
1
55
1
1
(T)
-~-I+
E~
;::.-
STRTCNT
0
1
0
0
0
1
0
1
45
1
1
(T)
-T1 Clock
STOP TCNT
0
1
1
0
0
1
0
1
65
1
1
(T) Count Stop
0
0
0
0
0
0
0
0
00
1
1
(PC)
Sen
e:e:
g~
""
.,-
~"
"::Ie:
NOP
5~.g
300
-(PC) +1
151- XTAL
- - - - - - - - - - - - - - - ' . MSM80C3S/48, 80C39/49, 80C40/S0 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Limits
Unit
Symbol
Conditions
VCC
Ta=25°C
-0.3t07
VI
Ta=25°C
-o.3toVCC
V
-55 to+150
°c
Tstg
V
OPERATING RANGE
• MSM80C35/48, 80C39/49 ... DC to 11 MHz, VCC = 5V ±20%
• MSM80C40/50
... DC to 6 MHz, VCC = 50 ±20%
Parameter
Supply Voltage
RAM Retention Voltage
Ambient Temperature
Fan Out
Symbol
Conditions
Limits
Unit
VCC
lose = DC-11 MHz·
+2.5 to +6
V
VCC
+2 to +6
V
TA
-40 to +85
°c
N
MOSload
10
TTL load
1
11 MHz version 01 MSM80C40/50 (6 MHz < XTAL 1.2 < 11 MHz) is under development.
301
• MSM80C35/48, 80C39/49, 80C40/50 . ' - - - - - - - - - - - - - -
DC ELECTRICAL CHARACTERISTICS
(Vee
= 5V±1 0%, Ta = -40 to +85°e)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
"L" Input Voltage
VIL
-0.3
0.8
V
"H" Input Voltage (1)
VIH
2.2
VCC
V
"H" Input Voltage (2)
VIH
3.8
VCC
V
"L" Output Voltage (3)
VOL
10L =2mA
0.45
V
"L" Output Voltage (4)
VOL
10L = 1.6 rnA
0.45
V
"H" Output Voltage (3)
VOH
IOH=400/LA
"H" Output Voltage (4)
VOH
IOH=50/LA
2.4
V
"H" Output Voltage (3)
VOH
IOH=20/LA
4.2
V
"H" Output Voltage (4)
VOH
IOH=10/LA
4.2
2.4
Measuring
Circuit
1
V
V
Input Leak Current
IlL
VSS~ VIN~ VCC
±10
/LA
2
Output Leak Current (5)
10L
VSS~VO~VCC
±10
/LA
3
RESET Pull up
Resistance
RR
VIN~VIH~J
20/500
50/750
kO
SS Pull up Resistance
(6)
RSS
Oscillation
stop/oscillation
20/200
50/500
kO
5/75
15/150
kO
P1, P2 Pull up
Resistance
VIN~VIL
RP1, P2
VIN~VIH/
VIN~ VIL
2
At hardware power
down VCC=2V
(TA=+25°C) (7)
1
10
/LA
At HLTS execution *VCC=2V
(TA = +25°C) (7)
1
10
/LA
At HALT (6 MHz)
1.5
3
rnA
At HALT (11 MHz)(S)
2.5
5
rnA
Atexecution
(6 MHz)
5
10
rnA
At execution
(11 MHz)(S)
10
20
rnA
3
4
Power Supply Current
ICC
Notes: (1) This does not apply to RESET, XTAL 1, XTAL2, and VOO.
(2) RESET, XTAL 1, XTAL2, VOO
(3) BUS, RO, WR, PSEN, ALE
(4) Other outputs
(5) High-impedance state
(6) This operates as a pull-down resistor when the oscillation is stopped in the HLTS or hardware power-down
mode and as a pull-up resistor in other states.
(7) This does not contain flow out current from I/O Ports and Signal pins.
(S) MSMSOC35/4S, SOC39/49
302
- - -___________1. MSM80C35/48, 80C39/49, 80C40/50 •
AC CHARACTERISTICS
(Vee
= 5V±1 0%, TA = -40 o e
to +85°e)
Limits
Parameter
Symbol
11 MHz Clock
Min.
Max.
Variable Clock (0 - 11 MHz)
Min.
Unit
Max.
Cycle Time
tCY
1.36
1.36
/LS
ALE Pulse Width
tLL
150
7/3OtCy-1 65
ns
Address Set up ALE
tAL
70
2/15tCy-110
ns
Address Hold from ALE
tLA
50
1/15tCy-40
ns
Bus Port Latch Data Setup
toALE
tBL
110
5/30tCy-115
ns
Bus Port Latch Data Hold
from ALE
tLB
90
3/3OtCy-45
ns
Control Pulse Width
(PSEN, RD, and WR)
tcc
300
6/15tCy-245
ns
Data Setup before WR
tDW
250
6/15tCy-295
ns
Data Hold afterWR
tWD
40
2/15tCy-140
Data Hold after RD
tDR
0
PSEN, RD to Data-in
tRD
Address Setup to WR
tAW
Address Setup to Data-in
tAD
100
0
200
200
ns
100
ns
5/15tCy-250
ns
8/15tCy-325
ns
ns
6/15tCy-345
400
Address Float to RD, PSEN
tAFC
0
Port Control Setup to PROG
tcp
100
Port Control Hold from PROG
tpc
60
PROG to P21nput Valid
tpR
-
Output Data Setup
tDP
200
6/15tCy-345
ns
Output Data Hold
tpD
20
3/15tCy-250
ns
Input Data Hold from PROG
tpF
0
PROG Pulse Width
tpp
700
10/15tCy-205
ns
Port 2 1/0 Setup to ALE
tpL
150
9/30tCy-255
ns
Port 2110 Hold from ALE
tLP
20
3/30tCy-115
ns
Note: Control output:
Bus output:
ns
0
ns
2/15tCy-80
ns
4/15tCy-300
9/15tCy-165
650
150
0
150
ns
ns
CL =80 pF
CL = 150 pF [for 20 pF (tWD))
303
• MSM80C35/48, 80C39/49, 80C40/50
.~-------------
MSM80C49 OPERATION GUARANTEE RANGE
Ta = -40 to +85°e
I
I
I
I
I
I
I
I
III sec)
I
I
I
I
100
Operation Guarantee Range
->
l!
.,
-1.5MHz
10
E
\.
F.,
\
u
\
>
<.J
\
-3MHz
\.
\
\
\
MSM80C40/50'
I"..
'"
"
1
2
3
4
Supply Voltage (Vee)
• 11 MHz version of MSM80C40/50 IS under development
304
5
6
(V)
-
6MHz
-
11 MHz
- - - - - - - - - - - - - - ' . MSM80C35/48, 80C39/49, 80C40/50 •
TIMING CHART
Instruction Fetch (from external program memory)
i---------tCy--------l
ALE
tAFC
tcc
BUS
Read (from external data memory)
ALE
tcc----I
BUS
305
• MSM80C35/48, 80C39/49, 80C40/50 ••- - - - - - - - - - - - - Write (to external memory)
ALE
f---tcc----i
BUS
4 low-order bits input/output of port 2 when expanded I/O is used
(in external program memory access mode)
P20-3
(Output
model
P20-3
(Input
model
306
PCH
PCH
- - - - - - - - - - - - - - - ' . MSM80C35/48, 80C39/49, 80C40/50 •
MEASUREMENT CIRCUIT
2
~
~
(11
V,H
I--
r(3)
::>
~
~
V,L
::>
I--
~
::>
1=
0
0
::>
::>
GND
- -
=- -=-
=3
-
-=-
4
V,H
I--
I--
::>
::>
~
V,L
~
::::
z
1
GND
-=
GND
5
~
INPUT
WAVEFORM
(2)
V,H
I--
I--
::>
::>
1=
~
V,L
::::
::>
0
GND
I
CL
OUTPUT
WAVEFORM
OUTPUT
WAVEFORM
txxx
Notes: (1) This is repeated for each specified input pin.
(2) This is repeated for each specified output pin.
(3) Input logic for setting the specified state.
307
OKI
&erniconductor
MSM80C31 F/MSM80C51 F
CMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM80C31 F/MSM80CS1 F microcontroller is a low power, high performance 8-bit single
component device implemented in OKI's silicon gate complementary metal oxide semiconductor
process technology. Integrated within the device is 4K bytes of mask programmable ROM
(MSM80CS1 F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source
two-level interrupt structure, a full duplex serial port, and an on chip oscillator and clock circuitry. In
addition, the device has two software selectable modes for further power reduction - Idle and Power
Down. Idle mode freezes the CPU's instruction execution while maintaining RAM and allowing the
timers, serial port and interrupt system to continue functioning. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
• Operating temperature: -40 - +8SoC
• Operating frequency:
O.S - 16 MHz
• CMOS technology, 2j.tm Silicon gate
• Minimum instruction cycle:
1.0j.ts (@ 12MHz, Vcc = SV±20%)
0.7SJ.Ls (@ 16MHz, Vcc =SV±10%)
• Low power consumption:
Normal Operation
16 mA @ SV, 12MHz
Idle Mode
3.7 mA @ SV, 12MHz
Power Down Mode
SOIJ-A @ 2V
• Instruction set includes 111 instructions
• 8-bit CPU
• On chip oscillator and clock circuitry
•
•
•
•
•
•
•
•
•
•
•
32 Input/Output lines
4069 x 8 bits on chip ROM (MSM80CS1 F)
128 x 8 bits on chip RAM
64K address space for program memory
64K address space for external data memory
Two 16-bit timer/counters
Five source two-priority level interrupt
structure
Full duplex serial port
Boolean processor
CMOS and TTL compatible
CMOS ROM LESS development device
(MSM80C31 F)
DIFFERENCES BETWEEN MSM80C31 F/MSM80C51 F AND
MSM80C31/MSM80C51
•
•
•
Operating frequency
O.S -16 MHz ............. MSM80C31 F-1/MSM80CS1 F-1
0.5 -12 MHz ............. MSM80C31 IMSM80CS1 IMSM80C31 F/MSM80CS1 F
External clock input terminal
XTAL 1 .................... MSM80C31 F(-1)/MSM80CS1 F(-1)
XTAL2 .................... MSM80C31/MSM80CS1
Emulation mode
Output impedance of ALE and PSEN pins becomes about 20kfl while CPU is being reset in
MSM80C31 F/MSM80CS1 F.
Any other functions and electrical characteristics of MSM80C31 F/MSM80C51 F except for the above
three differences are the same as those of MSM80C31 IMSM80CS1.
308
"11
C
Z
CONTROL SIGNALS
1--------------"~
~
:>I, I
j
R/W SIGNALS
,..-L--....L..,ll
I
o-t
5z
•raJ
r-
P20 - P27
o
o
~
c
~
POO - P07
G)
•::u
!iii:
XTALI - - - - - 4 -....
XTAL2
ALE
PSEN
RESET
"
II
.•~
l;l
o
~II
II
A
x
!
,}"
"
x
II
.1,1
:0
;XC
3:
SERI~L
'E _
...J
en
3:
to
o
oCo)
....
P30 - P37
L _____________________
~
=!!
to
o
o
(II
....
."
c.>
a
«>
•
~
• MSMSOC31F/SOC51F ••----------------------------------------PIN CONFIGURATION
MSM80C51 FV-XXGSKlMSM80C31 FVGSK
(Top View) 44-Lead Plastic Flat Package
MSM80C51 F-XXRS/MSM80C31 FRS
(Top View) 40-Lead Plastic DIP
""". C":! ~
.-
0
U
0
a:1i:a:a:i~5'~~~~
vee
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.&
Pl.7
RESET
RXD/P3.0
TXD/P3.1
iNfiilP3.2
INTlIP3.3
TO/P3.4
Po.o/ADO
PO.l/AD1
PO.2/AD2
PO.3/AD3
PO.4/AD4
PO.5/AD5
PO.&/AD&
PO.7/AD7
::I
Pl.6
""
"M
PO.4
0
PO.S
Pl.7
PO.S
S::S::
RESET
CPCP
00
PO.7
~~
NC
EA
00
NC
P3.1/TXD
ALE
PSEN
P2.7/A15
P2.&/A14
P2.5/A13
P2.4/A12
P2.3/All
P2.2/Al0
P2.1/A9
P2.0/A9
WR/P3.&
RDIP3.7
XTAL2
XTAL1
VSS
~
--------<:\
0.8
0.46 ~
0.8 ~
0.8
AC inputs during testing are driven at 2.4V for a logic ..," and 0.45V for a logic "0". Timing measurements are
made at 2.0V for a logic ..," and O.SV for a logic "0". For timing purposes, the float state is defined as the point
at which a PO pin sinks 3.2 mA or sources 400p.A at the voltage test levels.
SERIAL PORT TIMING
I/O EXPANSION MODE
(TA
= -40°C to +S5°C; VCC = 4 to 6V; VSS = OV, 0.5 to 12 MHz; Load capacitance = so pF)
Symbol
Parameter
TXLXL
Serial port clock cycle time
12TCLCL
TQVXH
Output data setup to clock rising edge
10TCLCL-133
TXHQX
Output data hold after clock rising edge
2TCLCL-117
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Min.
Max.
Units
p.s
0
-
-
10TCLCL-133
ns
ns
ns
ns
SERIAL PORT (I/O EXPANSION MODE)
MACHINE CYCLE I
2
0
3
4
5
6
7
8
CLOCK
OUTPUT DATA
........
WRITE TO saUF
TXHDV
- 1 - I-TXHDX
INPUTDATA _ _ _ _ _..JIi:.WILID="--"Y::...,:::I\_N:.VALID:::I\.....Jl::.vALID~\_,.,...v'WO::l"_.JIIO.::::i"_...I\="'_...I\"::::'WO::_l\
t
CLEAR Rl
317
~
n
~
CD
!n
-4
i
i
G)
n
CYCLE
%
•
STEP
XTAL 1
21
1
-4
o
Pm\!
m>/WR
PORT-O
PORT-2
PORT-CPU
•
3l:
(I)
3l:
:::-: 011
Ic::: 8.~::D ::!!~
Co)
n
en
en .-
I:
."
ALE
CPU-f'ORT 1
6
n
~"T':
L~-DAE ~ : ~RT D~TA: :
--':""-PORT""T'"!O......
N;EW
I
I
iI'nS~Ction'execution
Instruction decordlng
I
•
ITM+l
t--j
I
jl
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TM+l
I
I
I
I
I
I
I
I
I
I
I
I
PC+l.
i
II
I
" _
PC+l1
I
[':,Mtl
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
----------------------------------------_e. MSM80C31F/80C51F
•
EXTERNAL PROGRAM MEMORY FETCH
----------~--------__ MlorM2----------~----
XTAL 1
ALE
PORTO
PORT2
READ CYCLE 1 (MOVX A, @Rr)
XTAL 1
0
ALE
0
PSEN
0
Ri5
0-
PORTO
0
PORT 2
0
319
• MSMSOC31F/SOC51F ••----------------------------------------READ CYCLE 2 (MOVX A, @DPTR)
XTAL 1
0
ALE
0
J5§rn
0
RD
0-
PORTO
0
[J
PORT 2
0
WRITE CYCLE 1 (MOVX, @Rr, A)
XTAL 1
0
ALE
0
PSEN
0
WR
0-
PORTO
0
PORT 2
0
320
-----------------------------------------eeMSM80C31F/80C51F e
WRITE CYCLE 2 (MOVX A, @DPTR, A)
-;-------Ml------I-------
XTAL 1
ALE
PORTO
PORT 2
PORT OPERATION
XTAL 1
o
ALE
0-1----1
0-1----1
1
PORT 0,1,2,3,
PIN DATA
CPU DATA
SAMPLED
321
• MSM80C31F/80C51F ••----------------------------------------INSTRUCTION SET DETAILS
Mnemonic
rn
<=
0
;
Co
0
<)
i
E
;;
~
"0
.~~
3~
0
322
Hexadecimal
1 n2 n, no
28-2F
1
1
(A) - (Al + (Rn)
25
Byte 2
2
1
(Al - (A) + (direct)
ADDA,Rn
0
ADD A, direct
0 0 1 0 0 1 0 1
a7 a. a. a. aa a2 a, ao
ADD A, @Ri
0
ADDA,#data
0 0 1 0 0 1 0 0
d7 d. d. d. da d2 d, do
ADDCA,Rn
0
ADDC A, direct
0 0 1 1 0 1 0 1
a7 a. a. a. aa a2 a, ao
ADDCA,@Ri
0
ADDC A, #data
0 0 1 1 0 1 0 0
d7 d. d. d. da d2 d, do
SUBBA,Rn
1
SUBB A, direct
1 0 0 1 0 1 0 1
a7 a. a. a. aa a2 a, ao
SUBBA,@Ri
1
SUBB A, #data
1 0 0 1 0 1 0 0
d7 d. d. d. da d2 d, do
INCA
0
0
0
0
0
INCRn
0
0
0
0
1 n2 n, no 08-0F
INC direct
0 0 0 0 0 1 0 1
a7 a. a. a. aa a2 a, ao
INC@Ri
0
0
0
0
0
1
1
INC DPTR
1
0
1
0
0
0
1
DECA
0
0
0
1
0
1
0
1
1 n2 n, no
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1 n2 n, no
0
1
1
1
1 n2 n, no
0
1
1
1
0
1
0
Byte Cycle
Explanation
26-27
1
1
(Al - (Al + «Ri»
24
Byte 2
2
1
(A) - (Al + #data
38-3F
1
1
(Al - (Al + (C) + (Rn)
35
Byte 2
2
1
(Al - (Al + (C) + (direct)
36-37
1
1
(A) - (A) + (C) + «Ri»
34
Byte 2
2
1
(Al - (A) + (C) + #data
98-9F
1
1
(A) - (A) - «C) + (Rn»
95
Byte 2
2
1
(A) - (Al - «C) + (direct»
96-97
1
1
(Al - (A) - «C) + «Ril»
94
Byte 2
2
1
(Al - (A) - «C) + #data)
04
1
1
(A)-(Al+1
1
1
(Rn) - (Rn) + 1
05
Byte 2
2
1
(direct) - (direct) + 1
1
06-07
1
1
«Ri» - «Ri» + 1
1
A3
1
2
(DPTR) - (DPTR) + 1
0
14
1
1
(Al -(A)-l
18-1F
1
1
(Rn) - (Rn) - 1
15
2
1
(direct) - (direct) - 1
DECRn
0
DEC direct
0 0 0 1 0 1 0 1
a7 a. a. a. aa a2 a, ao
DEC@Ri
0
0
0
1
0
1
1
1
16-17
1
1
«Ri) - «Ri» - 1
MULAB
1
0
1
0
0
1
0
0
A4
1
4
(B,.-el, (A7-oJ-(Al x (B)
DIVAB
1
0
0
0
0
1
0
0
84
1
4
(A,.- el, (B7 - oJ-(A)/(B)
DAA
1
1
0
1
0
1
0
0
04
1
1
Contenis of Accumulator are BCD,
IF [[(Aa-oJ > 9] or [(AC) =111
THEN (Aa - oJ - (Aa - oJ + 6
AND
IF [[(A7 - .) > 9] OR [(C) = 111
THEN (A7 -.) -(A7-.) +6
ANLA,Rn
0
1
0
1
1 n2 n, no
58-5F
1
1
(A) - (A) AND (Rn)
ANL A, direct
0 1 0 1 0 1 0 1
a7 a. a. a. a3 a2 a, ao
55
Byte 2
2
1
(A) - (A) AND (direct)
ANLA,@Ri
0
56-57
1
1
(Al - (A) AND «Ri»
ANLA,#data
0 1 0 1 0 1 0 0
d7 d. d. d. d3 d2 d, do
54
Byte 2
2
1
(A) - (A) AND #data
rn
-<=
Instruction Code
07 D. D. D. Da 02 0, Do
0
1
0
0
1
0
1
1
1
-----------------------------------------eeMSM80C31F/SOC51F e
INSTRUCTION SET DETAILS (CO NT.)
Instruction Code
D, D. D. D. Da D2 D, Do
Hexadecimal
ANL direct, A
0 1 0 1 0 0 1 0
a, a. ao a. aa a2 a, aD
52
Byte 2
2
1
(direct) - (direct) AND (A)
ANLdirect,
#data
0 1 0 1 0 0 1 1
a, a. ao a. aa a2 a, aD
d, d. do d. da d2 d, do
53
Byte 2
Byte 3
3
2
(direct) - (direct) AND #data
ORLA,Rn
0
48-4F
1
1
(A) - (A) OR (Rn)
ORL A, direct
0 1 0 0 0 1 0 1
a, a. ao a. aa a2 a, aD
45
Byte 2
2
1
(A) - (A) OR (direct)
ORLA,@Ri
0
46-47
1
1
(A) - (A) OR «Ri))
ORLA,#data
0 1 0 0 0 1 0 0
d, d. do d. d3 d2 d, do
44
Byte 2
2
1
(A) - (A) OR #data
ORL direct, A
0 1 0 0 0 0 1 0
a, a. ao a. aa a2 a, aD
42
Byte 2
2
1
(direct) - (direct) OR (A)
ORLdirect,
#data
0 1 0 0 0 0 1 1
a, a. ao a. aa a2 a, aD
d, d. do d. da d2 d, do
43
Byte 2
Byte 3
3
2
(direct) - (direct) OR #data
XRLA,Rn
0
68-6F
1
1
(A) - (A) XOR (Rn)
XRL A, direct
0 1 1 0 0 1 0 1
a, a. ao a4 aa a2 a, ao
65
Byte 2
2
1
(A) - (A) XOR (direct)
XRLA,@Ri
0
66-67
1
1
(A) - (A) XOR «Ri))
XRLA, #data
0 1 1 0 0 1 0 0
d, d. do d4 d3 d2 d, do
64
Byte 2
2
1
(A) - (A) XOR #data
'c:0"
XRL direct, A
0 1 1 0 0 0 1 0
a, a. as a. a3 a2 a, aD
62
Byte 2
2
1
(direct) - (direct) XOR (A)
c.
XRLdirect,
#data
0 1 1 0 0 0 1 1
a, a. as a. a3 a2 a, ao
d, d. do d. d3 d2 d, do
63
Byte 2
Byte 3
3
2
(direct) - (direct) XOR #data
CLRA
1
1
1
0
0
1
0
0
E4
1
1
(A)-O
CPLA
1
1
1
1
0
1
0
0
F4
1
1
(A)-(A)
Mnemonic
~CIl
0
a;
()
'6>
0
....I
1
1
1
1
0
0
1
1
0
0
0
0
1 n2 n, no
0
1
1
1
1 n2 n, no
0
1
1
1
Byte Cycle
Explanation
q ,I
A
RLA
0
0
1
0
0
0
1
1
23
1
1
A.I A,I A.I A31 A21 A, lAo
rJ
The contents of the accumulator
are rotated left by one bit.
IAo~
RLCA
0
0
1
1
0
0
1
1
33
1
1
Lm!A,IA.IA,IA.IA3IA2IA,
The contents of the accumulator
and carry are rotated left by one bit.
Lj A,I A.I Asl A.I A31 A21 A, I AD ~
RRA
0
0
0
0
0
0
1
1
03
1
1
The contents of the accumulator
are rotated right by one bit.
LmA,IA6IAsIA.IA3IA2IA,IAoP
RRCA
0
0
0
1
0
0
1
1
13
1
1
The contents of the accumulator
and carry are rotated right by one
bit.
SWAP A
1
1
0
0
0
1
0
0
C4
1
1
(A3- 0)::::; (A, -.)
323
• MSM80C31F/80C51F ••----------------------------------------INSTRUCTION SET DETAILS (CONT.)
Mnemonic
Instruction Code
07 O. D. D. Os D. 0, Do
1
MOV A, direct
1 1 1 0 0 1 0 1
a7 a. a. a. as a. a, ao
1
1
Byte Cycle
1
1
(A)-(Rn)
2
1
(A) - (direct)
E6-E7
1
1
(A) -«Ril)
74
Byte 2
2
1
(A) -#data
E5
Byte 2
MOVA,@Ri
1
0 1 1 1 0 1 0 0
d7 d. d. d. ds d. d, do
MOVRn,A
1
F8-FF
1
1
(Rn) -(A)
MOV Rn, direct
1 0 1 0 1 n. n, no A8-AF
Byte 2
a7 a. a. a. as a. a, ao
2
2
(Rn) - (direct)
MOV Rn, #data
0 1 1 1 1 n. n, no
d7 d. d. d. ds d. d, do
78-7F
Byte 2
2
1
(Rn) -#data
MOV direct, A
1 1 1 1 0 1 0 1
a7 a. a. a. as a. a, ao
F5
Byte 2
2
1
(direct) - (A)
MOV direct, Rn
1 0 0 0 1 n. n, no
a7 a. a. a. a3 a. a, ao
88-8F
Byte 2
2
2
(direct) - (Rn)
85
Byte 2
Byte 3
3
2
(direct 1) - (direct 2)
1
0
1
0
1
1
1
0
1
0
a~ a~ a~ a~ a~ a~
a~ a~ a1 a~ a! a1
0
0
1
1 n. n, no
a~
a}
0
1
a8
a/,
MOV direct, @Ri
1 0 0 0 0 1 1 1
a7 a. a. a. a3 a. a, ao
86-87
Byte 2
2
2
(direct) - «Ril)
MOVdirect,
#data
0 1 1 1 0 1 0 1
a7 a. a. a. a3 a. a, ao
d7 d. ds d. d3 d. d, do
75
Byte 2
Byte 3
3
2
(direct) -#data
MOV@Ri,A
1
F6-F7
1
1
«Ri» -A
MOV @Ri, direct
1 0 1 0 0 1 1 1 A6-A7
Byte 2
a7 a. a. a. a3 a. a, ao
2
2
«Ri)) - (direct)
MOV @Ri, #data
0 1 1 1 0 1 1 1 76-77
d7 d. d. d. d3 d. d, do Byte 2
2
1
«Ri)) - #data
MOVOPTR,
#data 16
1 0 0 1 0 0 0 0
d,s d14 d'3 d,. dll dlO do de
d7 de d. d. d3 d. d, do
90
Byte 2
Byte 3
3
2
(OPTR) - #data ,.
1ii
c:
~
c:
ANLC/bit
"8co
1 0 1 1 0 0 0 0
b7 bo b. b. b3 b2 b, bo
ORL C, bit
.
","'
_c:
03
1
1
(C)-1
02
Byte 2
2
1
(bit)-1
1
1
(C)-(C)
2
1
(bit) - (bit)
2
2
(C) - (C) AND (bit)
BO
Byte 2
2
2
(C) - (C) AND (bit)
0 1 1 1 0 0 1 0
b7 bo b. b. b3 b2 b, bo
72
Byte 2
2
2
(C) - (C) OR (bit)
ORLC/bit
1 0 1 0 0 0 0 0
b7 bo b. b. b3 b2 b, bo
AO
Byte 2
2
2
(C) - (C) OR (bit)
MOVC, bit
1 0 1 0 0 0 1 0
b7 bo b. b. b3 b2 b, bo
A2
Byte 2
2
1
(C) -(bit)
MOVbit,C
1 0 0 1 0 0 1 0
b7 bo b. b. b3 b2 b, bo
92
Byte 2
2
2
(bit)-(C)
ACALL addr 11
a,o a. ao 1 0 0 0 1
a-, 8e a. a. a3 a2 a, ao
Byte 1
Byte 2
2
2
(PC) - (PC) + 2
(SP) - (SP) + 1
«SP» - (PC7 - ol
(SP) - (SP) + 1
«SP» - (PC ,. - oJ
(PC) - page address
12
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
(SP) - (SP) + 1
«SP» - (PC7 - ol
(SP) - (SP) + 1
«SP» -(PC,.- oJ
(PC) -addr,.- 0
c:
1
0
1
0
0
1
1
0
~
"5
Q.
..
:c..
"fij
·c
E
Q)
m
LCALL addr 16
0
0
0
1
1
1
0
0
0
1
1
1
0
a.
a7 ao a. a. a3 a2 a, ao
0
0
815814813812811 810 89
OJ
c:
:cu
c:
~
RET
0
0
1
0
0
0
1
0
22
1
2
(PC,. -oJ-«SP»
(SP) - (SP) - 1
(PC7 - ol - «SP»
(SP) - (SP) - 1
RETI
0
0
1
1
0
0
1
0
32
1
2
(PC ,. - oJ- «SP»
(SP) - (SP) - 1
(PC7 - ol - «SP»
(SP) - (SP) - 1
Byte 1
Byte 2
2
2
(PC) - (PC) + 2
(PC,o - ol- page address
02
Byte 2
Byte 3
3
2
(PC) -addr,.- 0
.a
E
~
e
a.
ol:: «Ri3 - ol)
AJMPaddr11
LJMPaddr16
87 86
ao 0 0 0 0 1
a. a. a3 a2 a, ao
0
0
810 89
0
0
0
0
0
ao
a7 ao a. a. a3 a2 a, ao
a 15 a 14 a 13 a 12 a 11 a 10
1
89
325
• MSMSOC31F/SOC51F ••----------------------------------------INSTRUCTION SET DETAILS (CONT.)
Mnemonic
Cl
c:
:;:
<>
c:
Instruction Code
0, O. Do D. 03 02 0, Do
SJMPrel
1
r,
JMP@A+OPTR
Hexadecimal
Byte Cycle
0
r.
0
rs
0 0 0
r. r3 r2
0
r,
0
ro
80
Byte 2
2
2
(PC) - (PC) + 2
(PC) - (PC) + rei
1
1
1
1
73
1
2
(PC) - (A) + (OPTR)
0 0 0
r3 r2 r,
0
ro
60
Byte
2
2
(PC) - (PC) + 2
IF (A) = 0 THEN (PC) - (PC) + rei
0
1
JZ rei
0
r,
1 1 0
r. rs r.
JNZrel
0
r,
1 1
r. rs
1 0 0 0
r. r3 r2 r,
0
ro
70
Byte 2
2
2
(PC) - (PC) + 2
IF (A) "I' 0 THEN (PC) - (PC) + rei
JCrel
0
r,
1
r.
0
rs
0 0 0 0
r. r3 r2 r,
0
ro
40
Byte 2
2
2
(PC) - (PC) + 2
IF (C) "1'1 THEN (PC) - (PC) + rei
JNCrel
0
r,
1
r.
0
rs
1 0 0 0
r. r3 r2 r,
0
ro
50
Byte 2
2
2
(PC) -(PC) +2
I F (C) #- 0 THEN (PC) - (PC) + rei
JB bit, rei
0 0 1 0 0 0 0 0
b, b. bs b. b3 b2 b1 bo
r, r. rs r. r3 r2 r, ro
20
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 1 THEN (PC) - (PC) + rei
JNBbit, rei
0 0 1 1 0 0 0 0
b, b. bs b. b3 b2 b1 bo
r, r. rs r. r3 r2 r, ro
30
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 0 THEN (PC) - (PC) + rei
JBC bit, rei
0 0 0 1 0 0 0 0
b, b. bs b. b3 b2 b1 bo
r, r. rs r. r3 r2 r, ro
10
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 1 THEN (bit)-O
(PC) - (PC) + rei
CJNE A, direct,
rei
1 0 1 1 0 1 0 1
a, a. as a. a3 a2 a, ao
r, r. rs r. r3 r2 r1 ro
B5
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (direct) < (A) THEN (PC) - (PC)
+reland(C)-O
IF (direct) > (A) THEN (PC) - (PC)
+ rei and (C)-l
CJNE A, #data,
rei
1 0 1 1 0 1 0 0
d, d. ds d. d3 d2 d1 do
r, r. rs r. r3 r2 r, ro
B4
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF #data < (A)
THEN (PC) - (PC) + rei and
(C)-O
IF #data> (A) THEN (PC) - (PC) +
rei and (C) - 1
CJNE Rn, #data,
rei
1 0 1 1 1 n2 n, no B8-BF
d, d. ds d. d3 d2 d1 do Byte 2
r, r. ro r. r3 r2 r, ro
Byte 3
3
2
(PC) - (PC) + 3
IF #data < (Rn) THEN (PC) - (PC)
+reland (C)-O
IF #data> (Rn) THEN (PC) - (PC)
+ rei and (C)-l
CJNE@Ri,
#data,rel
1 0 1 1 0 1 1 1 B6-B7
d, d. ds d. d3 d2 d1 do
Byte 2
r, r. rs r. r3 r2 r1 ro
Byte 3
3
2
(PC) - (PC) + 3
IF #data < ((Ri» THEN (PC) (PC) + rei and (C) - 0
IF #data> ((Ri» THEN (PC) (PC) + rei and (C) - 1
OJNZRn, rei
1
n
0 1 1 n2 n, no 08-0F
rs r. r3 r2 r, ro
Byte 2
2
2
(PC) - (PC) + 2
(Rn) - (Rn) - 1
IF (Rn) #- 0 THEN (PC) - (PC) + rei
OJNZdirect, rei
1 1 0 1 0 1 0 1
a, a. as a. a3 a2 a1 ao
r, r. rs r. r3 r2 r, ro
05
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
(direct) -(direct)-l
IF (direct) 'f' 0 THEN (PC) - (PC)
+ rei
NOP
0
00
1
1
(PC) - (PC) + 1
~
0
0
.0
E
~
e
0..
326
Explanation
1
r.
0
0
0
0
0
0
0
------------------------------------------e.
MSM80C31F/80C51F •
NOTES ON THE INSTRUCTION SET AND THE ADDRESSING MODES
Rn
- Register R7 -RO of the currently
selected Register Bank.
direct
- 8-bit internal data location's address.
This could be an Internal Data RAM
location (0 - 127) or a SFR [i.e., 1/0
port, control register, status register,
etc. (128 - 255)].
@Ri
- 8-bit internal data RAM location (0 255) addressed indirectly through
register R1 or RO.
#data
- 8-bit constant included in instruction.
#data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & LJMP. A branch can be
anywhere within the 64K-byte
Program Memory address space.
addr 11
- 11-bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of
program memory as the first byte of
the following instruction.
rei
- Signed (two's complement) 8-bit offset
byte. Used by SJMP and all conditional
jumps. Range is -128 to +127 bytes
relative to first byte of the following
instruction.
bit
- Direct Addressed bit in Internal Data
RAM or Special Function Register.
INSTRUCTIONS THAT AFFECT FLAG SETTINGS 1
INSTRUCTION
ADD
ADDC
SUBB
MUL
DIV
DA
RRC
RLC
SETBC
1
FLAG
C OVAC
x X X
X X X
X X X
0 X
0 X
X
X
X
INSTRUCTION
CLRC
CPLC
ANL C, bit
ANL C,/bit
ORL C, bit
ORL C, fbit
MOVC, bit
CJNE
FLAG
C OVAC
0
X
X
X
X
X
X
X
I
Note that operations on SFR byte address 208 or bit
addresses 208-215 (Le., the PSW or bits in the PSW) will
also affect flag settings.
327
e MSM80C31F/80C51Fee----------------------------------------APPLICATION EXAMPLES
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
XTAL2
B.2K
~
~VE
EA
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0 (RXD)
P3.1 (TXD)
P3.2 (iiiffii)
P3.3 (lNTlI
P3.4 (TO)
P3.5 (T1)
P3.6 (WR)
P3.7 (RD) ALE
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
RESET
10jlf
31
,~{
[fI
10
11
12
13
14
15
16
17
MSM80C51F
1
2
3
4
5
6
7
B
2
3
4
5
},~
P50
P51
MSM82C43 P52
P53
I/O
11
1
9
P20 EXPANDER P60
P61
P21
P62
P22
P63
P23
PROG
Cs
39
38
37
36
35
34
33
32
P70
P71
P72
P73
110
29
The following software driver is required to interlace to the 82C43
Mixing Parallel Output, Input, and
Control Strobes on Port 2.
INPUT DATA FROM AN 82C43 1/0 EXPANDER
CONNECT TO P23-P20
P25 & P24 MIMIC CSI & PROG
P27-P26 USED AS INPUTS
PORT TO BE READ IN ACC
IN82C43
IN82C43
MOV
MOV
ClR
ORl
MOV
SETB
P21 P20
0
0
0
1
0
A,#11010000B
P2,A
;OUTPUT INSTRUCTION CODE
P2.4
;FAlLING EDGE OF PROG
P2,#OOOO1111B
;SET FOR INPUT
A,P2
;READ INPUT DATA
P2.4
;RETURN PROG HIGH
Address
Code
Port 4
Port 5
Port 6
Port 7
P23
P22
0
0
0
1
Instruction
Code
0
I/O expansion Using an 82C43
328
Read
Write
ORlO
ANlD
1
23
I/O
-----------------------------------------4.
MSMSOC31F/SOC51F •
APPLICATION EXAMPLES (CO NT.)
7
F
r
19~
XTAL1 vee
Vss
CJ
-=;opF'[
]!8~
XTAL2
8.2K
~~t
10
1
12
13
14
15
16
17
,~{
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
EA
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0(RXD)
P3.1 (TXD)
P3.2 (INTO)
P3.3 (INT1)
P3.4 (TO)
P3.5 (n)
P3.6 (WR)
P3.7 (RD) ALE
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
RESET
MSM80C51F
PSEN
110
39
38
37
36
35
34
33
32
n
29
19
7 f;r
11
XTAL 1 Vee
F
-::;-opFT"
8.2 K
8 ..
cr
31
0/0 {
10
11
12
13
14
15
16
17
XTAL2
RESET
MSM80C51F
EA
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
(RXD)
(TXD)
(iNTii)
(ifiifi)
(TO)
(n)
(WR)
(RD) ALE
PSEN
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
1
2
3
4
5
6
7
8
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
110
39
38
37
36
35
34
33
32
29
Multiple 80C51 F's Using Half-Duplex Serial Communication
329
• MSMSOC31F/SOC51F ••----------------------------------------APPLICATION EXAMPLES (CONT.)
19
1~rIJj~
lOp~
Pl.0
P1,'
Pl.2
P1.3
Pl.4
Pl.5
Pl.6
Pl.7
XTAL2
8.2 K
~
P2.0
EA
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.1
P10IRXDI
P3.1ITXDI
Pl.2I1NTOI
P3.3I1NTll
P3.4ITOI
P3.5IT1)
P3.61~1
Pl.7 IRDI ALE
PO.O
PO.l
PO.2
PO.3
PO.4
PO.6
PO.6
PO.7
RESET
MSM80C51F
10llt
31
,.{
30
PSEN
1
2
3
4
5
6
7
B
},.
21
22
23
2
25
26
27
2B
},.
+5V
GND
Vee
Vss
20
12
13
14
15
16
17
18
19
39
37
3
35
33
32
PAO
PAl
PA2
PA3
PM
PAS
PA6
PA7
ADO
ADI
AD2
AD3
AD4
A05
ADS
AD7
MSM81C55
29
101M
RD
10
Wii
11
ALE
, - - . CE
...L
-=-
r4
--
RESET T~~~R
CAN BE SUt'PLIED BY SYSTEM RESET
OR PORT LINE OF 80C61
Adding a Data Memory and I/O Expander
6
Pl.0
Pl.l
P1.2
Pl.3
Pl.4
Pl.5
P1.6
P1.1
RESET
MSM80C51F
liD [
14
16
16
17
Pl.O IRXDI
P3.1ITXDI
P3.2I1NTOI
P3.3 liNTil
Pl.4ITOI
Pl.6IIll
P3.6IWRI
P3.71RDI ALE
Multiple Interrupt Sources
330
29
3
31
32
34
35
36
TIMER
XTAL 2
EA
PBO
PBl
PB2
PB3
PB4
PB5
P86
PB7
37
38
39
1
2
5
P
,
19
1~ Ef5.
10P~
TIMER
IN
PCO
PCl
PC2
PC3
PC4
PC5
21
22
23
24
25
2
2
28
1
2
3
5
6
7
8
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
110
33
32
liD
------------------------------------------•• MSM80C31F/80C51F •
MSM80C31/MSM80C51 INSTRUCTION CODES
~
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
0
0000
NOP
AJMP
address 11
(Page 0)
LJMP
address 16
RRA
INCA
INC
direct
INC@RO
INC@Rl
1
0001
JBCbit,
rei
ACALL
address 11
(Page 0)
LCALL
address 16
RRCA
DECA
DEC
direct
DEC@RO
DEC@Rl
2
0010
JBbit,
rei
AJMP
address 11
(Page 1)
RET
RLA
ADDA,
#data
direct
ADDA,
@RO
ADDA,
@Rl
3
0011
JNBbit,
rei
ACALL
address 11
(Page 1)
RETI
RLCA
i\DDCA,
#data
ADDCA,
direct
ADDCA,
@RO
ADDCA,
@Rl
4
JCbit,
...
,.
....
AJMP
ORL
ORL
ORLA,
ORLA,
ORLA,
ORLA,
direct, A
#data
direct
@RO
@Rl
ANLA,
direct
ANLA,
@RO
ANLA,
@Rl
XRLA,
direct
XRLA,
@RO
XRLA,
@Rl
MOV
direct,
#data
MOV@RO,
#data
MOV@Rl,
#data
0100
rei
5
0101
JNCrel
ACALL
address 11
(Page 2)
ANL
direct, A
ANL
direct,
#data
ANLA,
#data
6
0110
JZrel
AJMP
address 11
'(Page 3)
XRL
direct, A
XRL
direct,
#data
XRLA,
#data
JNZrel
ACALL
address 11
(Page 3)
II"" ORLC,
AJMP
address 11
(Page 4)
II""
SJMPrel
8
1000
9
1001
...II""
II""
direct,
#data
address 11
(Page 2)
7
0111
II"" ADDA,
II""
II"" MOVA,
bit
JMP
@A+DPTR
ANLC,
bit
MOVCA,
@A+PC
DIVAB
MOV
direct 1,
direct 2
MOV
direct.
@RO
MOV
direct,
@Rl
ACALL
MOVDPTR,
address 11
#data 16
(Page 4)
MOVbit,
C
MOVCA,
@A+DPTR
SUBBA,
#data
SUBBA,
direct
SUBBA,
@RO
SUBBA,
@Rl
MOV@RO,
direct
MOV@Rl,
direct
#data
A
1010
ORLC/bit
AJMP
address 11
(Page 5)
MOVC,
bit
INC DPTR
MULAB
B
1011
ANLC/bit
ACALL
address 11
(Page 5)
CPLbit
CPLC
CJNEA,
#data,
rei
CJNEA,
direct',
rei
1100
PUSH
direct
AJMP
address 11
(Page 6)
CLR bit
CLRC
SWAP A
XCHA,
direct
D
1101
POP
direct
ACALL
address 11
(Page 6)
SETBbit
SETBC
DAA
DJNZ
direct,
rei
E
1110
MOVXA,
@DPTR
AJMP
address 11
(page 7)
F
MOVX
@DPTR,A
ACALL
address 11
(page 7)
C
1111
...
II""
MOVXA,
@RO
MOVXA,
@Rl
CLRA
MOVX
@RO,A
MOVX
@Rl,A
CPLA
...
II""
CJNE @RO~ CJNE@Rl,
#data,
#data,
rei
rei
XCHA,
@RO
XCHA,
@Rl
XCHDA,
XCHDA,
@RO
@Rl
MOVA,
direct
MOVA,
@RO
MOVA,
@Rl
MOV
direct, A
MOV
@RO,A
MOV
@Rl,A
3 BYTE
2 BYTE
MNEMONIC
2 CYCLE
4 CYCLE ....
331
• MSMSOC31F/SOC51F ••-----------------------------------------
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
INCRO
INCR1
INCR2
INCR3
INCR4
INCR5
INCR6
INCR7
DECRO
DECR1
DECR2
DECR3
DECR4
DECR5
DECR6
DECR7
ADDA,RO
ADDA,R1
ADDA,R2
ADDA,R3
ADDA,R4
ADDA,R5
ADDA,R6
ADDA,R7
ADDCA,RO
ADDCA,R1
ADDCA,R2
ADDCA,R3
ADDCA,R4
ADDCA, R5
ADDCA,R6
ADDCA,R7
ORLA,RO
ORLA,R1
ORLA,R2
ORLA,R3
ORLA,R4
ORLA,R5
ORLA,R6
ORLA,R7
ANLA,RO
ANLA,R1
ANLA,R2
ANLA,R3
ANLA,R4
ANLA,R5
ANLA, R6
ANLA,R7
XRLA,RO
XRLA,R1
XRLA,R2
XRLA,R3
XRLA,R4
XRLA,R5
XRLA,R6
XRLA,R7
MOVRO,
#data
MOVR1,
#data
MOVR2,
#data
MOVR3,
#data
MOVR4,
#data
MOVR5,
#data
MOVR6,
#data
MOVR7,
#data
MOV
direct,
RO
MOV
direct,
R1
MOV
direct,
R2
MOV
direct,
R3
MOV
direct,
R4
MOV
direct,
R5
MOV
direct,
RS
SUBBA,
RO
SUBBA,
R1
SUBBA,
R2
SUBBA,
R3
SUBBA,
R4
SUBBA,
R5
MOVRO,
direct
MOVR1,
direct
MOVR2,
direct
MOVR3,
direct
MOVR4,
direct
CJNERO,
#data,
rei
CJNER1,
#data,
rei
CJNER2,
#data,
rei
CJNER3,
#data,
rei
CJNER4,
#data,
rei
XCHA,
RO
XCHA,
R1
XCHA,
R2
XCHA,
R3
XCHA,
R4
XCHA,
R5
XCHA,
R6
XCHA,
R7
DJNZRO,
rei
DJNZR1,
rei
DJNZR2,
rei
DJNZR3,
rei
DJNZR4,
rei
DJNER5,
rei
DJNER6,
rei
DJNER7,
rei
MOVA,RO
MOVA,R1
MOVA,R2
MOVA,R3
MOVA,R4
MOVA,R5
MOVA,R6
MOVA,R7
MOVRO,A
MOVR1,A
MOVR2,A
MOVR3,A
MOVR4,A
MOVR5,A
MOVRS,A
MOVR7,A
332
I
,.
III..
,.
MOV
direct,
R7
SUBBA,
RS
SUBBA,
R7
MOVR5,
direct
MOVRS,
direct
MOVR7,
direct
CJNER5, ~
#data,
rei
CJNERS,
#data,
rei
CJNER7, ~
#data,
rei
I
OKI
semiconductor
MSM80C154/ MSM83C154
CMOS 8-bit One-Chip Microcontroller
GENERAL DESCRIPTION
The MSMS3C154/MSMSOC154 is a high performance S.lJit one-chip microcontroller implementing large
integration, high speed and low power consumption by 2 }.1m silicon gate CMOS process technology.
The MSMS3C154 features 16K byte ROM, 256 byte RAM, 32 I/O ports, three 16-bit timer/counters,
multifunctional serial port and clock generator. In addition, the MSMS3C154 has three standby modes
enabling further power reduction.
The MSMSOC154 is identical to the MSMS3C154 except the omission of 16K byte ROM.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully static circuit
On-chip program memory
On-chip data memory
External program memory address space
External data memory address space
I/O ports
(Port 1,2,3, impedance programmable)
16.IJit timer/counters
(includes watch dog timer & 32 bit timer)
Multifunctional serial port
:
:
:
:
16K x S bit ROM (MSMS3C154 only)
256 x S bit RAM
64K bytes
64K bytes
: 32
:3
I/O Expansion mode
: UART mode (featuring error detection)
6-source 2-priority level
interrupt and multi-level
interrupt available by programming IP and IE registers
Memory-mapped special function registers
Bit addressable data memory and SFRs
Minimum instruction cycle
: 1.0 p.s @ 12 MHz operation
: 0.75 p's @ 16 MHz operation (MSM80C154-1)
16 MHz version of MSMS3C154 (12 MHz < XTALl ·2
.;; 16 MHz) is now under development.
"Multiply" /"divide" instruction cycle
: 3}.1s @16 MHz operation
Standby functions
: Idle mode (CPU halt)
: Power down mode (Oscillator stop)
Activated by Software or Hardware; Providing ports with
floating or active status
The software power down mode is terminated by
interrupt signal enabling excution from the interrupted
address.
Lower power consumption achieved by 2 }.1m silicon gate CMOS process
Upward compatible with MSM80C51 /SOC31
Packages
: 40-pin DIP, 44-pin flat package and 44-pin PLCC
333
~
c.>
c.>
....
-nn
en
=t
0
:xl
P2.0 ----l
~
P2.7+-+1 -
c:
1('
K=:>l ,
'L::...:..:....J"-"" , +
'-'
"
ROM
x8bit
,-_.
,~.
.
,
""
m
r
0
R/WSIGNAL
+
o.J
1.:)1
+
n
~-I ;";""TI~a.I
I
ADDRESS
,
~
C
»
C)
.:::IJ
»
3:
Pl.0
Pl.7
P3.0
P3.7
TIMER/COUNTER 0 & 1
•
ii!I:
ii!I:
QI)
...0
U'I
~
"QI)
Co)
...
0
U'I
~
•
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
PIN CONFIGURATION
MSM83C154-XXRS/MSM80C154RS
(Top-View) 40 Lead Plastic DIP
MSM83C154V-XXGS/MSM80C154VGS
(Top-View) 44 Lead Plastic Package
'm"k
MIN 14.9
PIN FUNCTIONS
Pin Name
Description
PO.O
~
PO.7
Bidirectional I/O ports. They are also the data/address bus (input/output
of data and output of lower 8-bit address when external memory is accessed.
They are open drain output when used as I/O ports, but tri-state output when used
as data/address bus.
Pl.0
~
Pl.7
Pl .0 to Pl.7 are quasi-bidirectional I/O ports. They are pulled up internally when
used as input ports. Two of them have the following secondary functions:
• Pl.0 (T2)
: Used as external clock input pin for the timer/counter 2 .
• Pl.l (T2EX)
: Used as trigger input for the timer/counter 2 to be reloaded
or captured; causing the timer /counter 2 interrput.
335
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - - -
PIN FUNCTIONS (CONT.)
Description
Pin Name
P2.0 - P2.7
P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit
address when an external memory is accessed. They are pulled up internally when
used as input ports.
P3.0 - P3.7
P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when
used as input ports. They also have the following secondary functions:
.P3.0 (RXD)
Serial data input/output in the I/O expansion mode and serial data input in the
UART mode when the serial port is used .
• P3.1 (TXD)
Synchronous clock output in the I/O expansion mode and serial data output in
the UART mode when the serial port is used .
• P3.2 (INTO)
Used as input pin for the external interrupt 0, and as count-up control pin for the
timer /counter O.
• P3.3 (lNT1)
Used as input pin for the external interrupt 1, and as count-up control pin for the
timer /counter 1 .
• P3.4 (TO)
Used as external clock input pin for the timer/counter O.
• P3.5 (T1)
Used as external clock input pin for the timer/counter 1 and power down mode
control input pin .
• P3.6 (WR)
Output of the write strobe signal when data is written into external data memory .
• P3.7 (RD)
Output of the read strobe signal when data is read from external data memory.
ALE
Address latch enable output for latching the lower 8-bit address during external
memory access. Two ALE pulses are activated per machine cycle except during
external data memory access at which time one ALE pulse is skipped.
PSEN
Program store enable output which enable the external memory output to the bus
during external program memory access. Two PSEN pulses are activated per
machine cycle except during external data memory access at which two PSEN
pulses are skipped.
EA
When EA is held at "H"level, the MSM83C154 executes instructions from
internal program memory at address OOOOH to 3FFFH, and executes instructions
from external program memory above address 3FFFH.
When EA is held at "L" level, the MSM80C154/MSM83C154 executes instructions
from external program memory for all addresses.
RESET
If this pin remains "H" for at least 1 Jl second, the MSM80C154/MSM83C154 is
reset. Since this pin is pulled down internally, a power-on reset is achieved by
simply connecting a capacitor between Vcc and this pin.
XTAL1
Oscillator inverter input pin. External clock is input through XTAL 1 pin.
XTAL2
Oscillator inverter output pin.
VCC
Power supply pin during both normal operation and standby operations.
VSS
GND pin.
336
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
DATA MEMORY AND SPECIAL FUNCTION REGISTER
LAYOUT DIAGRAM
'oFFH
OF8H
IOCON
OFOH
B
OEOH
ACC
ODOH
PSW
OCDH
TH2
OCCH
TL2
OCBH
RCAP2H
OCAH
RCAP2L
OC8H
T2CON
OB8H
IP
OBOH
P3
OA8H
IE
OAOH
P2
99H
SBUF
98H
SCON
90H
Pl
aJ
l-
IU
u
I-
w
a:
w
a:
a:
o
0
0
Z
US
CIl
w
0
0
«
a:
w
I-
CIl
8
7
08H
07H
Bank 0
OOH
338
0
«
aJ
a:
Bank 2
w
w
a:
I-
<.!)
24
23
18H
17H
0
0
z
!::
31
Bank 3
CIl
W
<.!)
w
a:
u
w
z
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
DETAILED DIAGRAM OF SPECIAL FUNCTION REGISTERS
Direct
Byte
Address
Special
Function
Register
Symbol
Bit Address
(MSB)
(LSB)
WDT T32 SERR IZC P3HZ P2HZ P1 HZ ALF
OF8H
FF
FE
FD
FC
FB
OFOH
F7
F6
F5
F4
F3
OEOH
E7
E6
E5
E4
E3
CY
AC
FO
RS1
RSO
D7
D6
D5
D4
D3
ODOH
1
1
1
F9
F8
IOCON
F1
FO
B
E1
EO
ACC
OV
F1
P
D2
D1
DO
FA
F2
E2
1
1
1
PSW
OCDH
Not Bit Addressable
TH2
OCCH
Not Bit Addressable
TL2
OCBH
Not Bit Addressable
RCAP2H
OCAH
Not Bit Addressable
RCAP2L
TF2 EXF2 RCLK TCLKEXEN2 TR2
OC8H
I
CF
1
CE
1
PCT
OB8H
I
OBOH
1
BF
B7
1
-
OAOH
I
I
PT2
PS
BD
BC
ET2
AF
1
A7
1
1
CB
1
CA
1
PT1 PX1
BB
1
BA
C9
1
PTO
1
B9
C8
ES
ET1
EX1
I
I
I
T2CON
PXO
1
B8
ETO
I
I
IP
P3
EXO
1
AD
1
AC
1
AB
1
AA
1
A9
1
A8
IE
A6
1
A5
1
A4
1
A3
1
A2
1
A1
1
AO
P2
Not Bit Addressable
SMO
90H
CC
-
99H
98H
1
I B6 I B5 I B4 I B3 I B2 I B1 I BO
EA
OA8H
CD
SM1
REN
SM2
TB8
H
C/T2 CP/RL2
SBUF
RB8
RI
TI
9F
1
9E
1
9D
1
9C
1
9B
1
9A
1
99
1
98
SCON
97
1
96
1
95
1
94
1
93
1
92
1
91
1
90
P1
339
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
Direct
Byte
Address
Special
Function
Register
Symbol
Bit Address
(MSB)
8DH
Not Bit Addressable
TH1
8CH
Not Bit Addressable
THO
8BH
Not Bit Addressable
TL1
8AH
Not Bit Addressable
TLO
89H
Not Bit Addressable
TMOD
TF1
88H
TFO
TRO
IE1
IT1
lEO
ITO
I 8A 1 89 1 88
TCON
Not Bit Addressable
PCON
DPH
83H
Not Bit Addressable
82H
Not Bit Addressable
DPL
81H
Not Bit Addressable
SP
80H
340
TR1
8F I 8EI 8D I 8C I 8B
87H
~
(LSB)
87
I 86 I 85 I 84 I 83 I 82 I 81 I 80
PO
- - - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
SPECIAL FUNCTION REGISTERS
Timer mode register (TMOD)
NAME
MSB
LSB
76543210
ADDRESS
------------~--------+-----------
TMOD
89H
BIT LOCATION
FLAG
TMOD.O
MO
GATE
--r-----r-----r------r-----r-----r------
C/T
Ml
MO
GATE
C/T
Ml
MO
FUNCTION
I
- - - - - -.- Ml
:
j
-
- -
j'" -
: Timer/counter 0 mode setting
--
o :
- -
.: -8-bit
- - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - ti mer /counter with 5-bit prescalar.
MO
0
-
-
-
,- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- -
-
-
- -
-
--
___ ~ __ ~ __ 1___:_ ~ ~-~~t_t~m_e~/~~u~~:r.:. _______________________ _
TMOD.l
1
: 0
: 8-bit timer/counter with 8-bit auto reloading.
---1- --:- -;Ti~~;/;o-u~;e-r-O ;e~;;a;ed-i~~-TI.:O-(8~bi;) ;i;;'~;; ---
-i-
Ml
:
: counter and THO (8-bit) timer/counter. TFO is set
:
: by TLO carry, and TF 1 is set by THO carry.
TMOD.2
CIT
Timer/counter 0 count clock designation control bit.
XTAL 1 ·2 divided by 12 clocks is the input applied to timer/counter
o when C/T ~ "0".
The external clock applied to the TO pin is the input applied to
ti mer /counter 0 when C/T' ~ "1".
TMOD.3
GATE
When this bit is "0", the TRO bit of TCON (timer control register) is
used to control the start and stop of timer/counter 0 counting.
If this bit is "1", timer/counter 0 starts counting when both
the TRO bit of TCON and INTO pin input signal are "1", and stops
counting when either is changed to "0".
TMOD.4
MO
Ml
:
MO
: Timer/counter 1 mode setting.
- - - - - - - - - - - -1- -
-
-
-
- - - - - - - -
- - - - - - - - -
-
- -
-
-
-
-
-
- - -
-
- --
o ; 0 : 8-bit timer/counter with 5-bit prescalar.
~ ~ ~~ ~ I-~~~ ~ ~l~~~i~ :i_~~!~~~~u~~ir~ ~~~_-_-_-_-_-_-_-_-~ _-_ ~~~ ~ ~ -_-_~-_~
I
-------+------4
TMOD.5
M1
TMOD.6
CIT
TMOD.7
GATE
1
:
-- -1- -
0
: 8-bit timer/counter with 8-bit auto reloading.
T -:;-- -:-Ti~e~jc~u~t~r-l ~~;r;ti;n-s~o-pp;d.- --- ------- -I
Timer/counter 1 count clock designation control bit.
XTAL 1 ·2 divided by 12 clocks is the input applied to timer /counter
1 when C/T' ~ "0".
The external clock applied to the T1 pin is the input applied to
ti mer /counter 1 when clf ~ "1".
When this bit is "0", the TRl bit of TCON is used to control
the start and stop of timer/counter 1 counting.
If this bit is "1 ", timer/counter 1 starts counting when both
the TRl bit of TCON and INTl pin input signal are "1 ", and stops
counting when either is changed to "0".
341
eMSM80C154/83C154e-----------------------------------------Power control register (peON)
NAME
ADDRESS
MSB
7
6
5
4
3
2
1
LSB
0
PCON
87H
SMOD
HPD
RPD
-
GF1
GFO
PO
IDL
BIT LOCATION
FLAG
FUNCTION
PCON.O
IDL
IDLE mode set when this bit is set to "1". CPU operations are
stopped when IDLE mode is set, but XTAL 1'2, timer/counters 0,1,
and 2, the interrupt circuits, and serial port remain active.. IDLE mode
is cancelled when the CPU is reset or when an interrupt is generated.
PCON.1
PO
PO mode set when this bit is set to "1". CPU operations and XT AL 1,2
are stopped when PO mode is set. PO mode is cancelled when the CPU
is reset or when an interrupt is generated.
PCON.2
GFO
General purpose bit.
Testing this flag when IDLE mode is cancelled by an interrupt shows
whether the interrupt is a normal interrupt or an IDLE mode release
interrupt.
PCON.3
GF1
General purpose bit.
Testing this flag when PO mode is cancelled by an interrupt shows
whether the interrupt is a normal interrupt or a PO mode release
interrupt.
PCON.4
-
PCON.5
RPD
Bit used to specify cancellation of CPU power down mode (IDLE or
PO) by interrupt signal.
Power down mode cannot be cancelled by interrupt signal if interrupt
is not enabled by I E (interrupt enable register) when this bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when
this bit is "1" (even if interrupt is disabled), the program is executed
from the next address of the power down mode setting instruction.
The flag is reset to "0" by software.
PCON.6
HPD
The hard power down setting mode is enabled when this bit is set to
"1" .
If the level of the power failure detect signal applied to the HPDI pin
(pin 3.5) is changed from "1" to "0" when this bit is "1", XTAL 1 ·2
oscillation is stopped and the system is put into hard power down
mode. HPD mode is cancelled when the CPU is reset.
PCON.7
SMOD
342
Reserved bit. The output data is "1" if the bit is read.
When the timer/counter 1 carry signal is used as a clock in mode 1,
2 or 3 of the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is
"0" for delayed processing. And when the bit is "1", the serial port
operation clock is normal for faster processing.
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Timer control register (TCON)
NAME
ADDRESS
MSB
7
6
5
4
3
2
1
LSB
0
TCON
aaH
TFl
TRl
TFO
TRO
IE 1
ITl
lEO
ITO
BIT LOCATION
FLAG
FUNCTION
TCON.O
ITO
External interrupt 0 signal used in level detect mode when this bit is
"0", and in trigger detect mode when "1".
TCON.l
lEO
Interrupt request flag for external interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when ITO = "1".
TCON.2
ITl
External interrupt 1 signal used in level detect mode when this bit is
"0", and in trigger detect mode when "1".
TCON.3
IEl
Interrupt request flag for external interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when ITl = "1".
TCON.4
TRO
Counting start and stop control bit for timer/counter O.
Timer/counter 0 starts counting when this bit is "1", and stops
counting when "0".
TCON.5
TFO
Interrupt request flag for timer interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from timer/counter O.
TCON.6
TRl
Counting start and stop control bit for timer/counter 1.
Timer/counter 1 starts counting when this bit is "1 ", and stops
counting when "0".
TCON.7
TFl
Interrupt request flag for timer interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from ti mer /counter 1 .
343
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
Serial port control register (SCON)
NAME
ADDRESS
SCON
98H
BIT LOCATION
[I
LSB
MSB
7
6
5
4
3
2
SMO
SM1
SM2
REN
TB8
RB8
o
TI
RI
FUNCTION
FLAG
SCON.O
RI
"End of serial port reception" interrupt request flag.
This flag must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been received when in
mode 0, or by the STOP bit when in any other mode. In mode 2
or 3, however, R I is not set if the R B8 data is "0" with SM2 = "1".
R I is set in mode 1 if STOP bit is received when SM2 = "1".
SCON.1
TI
"End of serial port transmission" interrupt request flag. This flag
must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been sent when in
mode 0, or after the last bit of data has been sent when in any other
mode.
SCON.2
RB8
The ninth bit of data received in mode 2 or 3 is passed to RB8.
The STOP bit is applied to RB8 if SM2 = "0" when in mode 1.
RB8 can not be used in mode O.
SCON.3
TB8
The TB8 data is sent as the ninth data bit when in mode 2 or 3.
Any desired data can be set in TB8 by software.
-------------+---------+-------------Reception enable control bit
SCON.4
REN
No recePtion when REN = "0".
Reception enabled when REN = "1".
SCON.5
SM2
SCON.6
SM1
If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or
3, the "end of reception" signal is not set in the R I flag.
Nor is the "end of reception" signal set in the R I flag if the STOP
bit is not "1" when SM2 = "1" in mode 1.
SMO : SMl : MODE:
_ _ _ _ _ _ _ _ _ _ _ ...! _ _ _ _ _ .l _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
o : 0 : 0 : 8-bit shift register I/O
o
1
1
'8-bit UART variable baud rate
-------------+-----------1--- ---;- - - - -:- -- - -~ - --- -- --- -- --- - - -- --- - - - -- - --- - -------, -
-
- - - , - - - - - -1- - -
I
SCON.7
SMO
1:
I
0
:
:
2
-
- --- - ----- - - - - - - - - - - - - - --------
: 9-bitUART1/32XTALl,1/64XTALl
: baud rate
S:bi; UART-v~;i~bl~ -b~~d-r~;e------------
---1- -:- -,- -:, --:3 - -r-,
344
-
I
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Interrupt enable register (IE)
5
4
3
2
,
LSB
0
ET2
ES
ET'
EX'
ETO
EXO
NAME
ADDRESS
MSB
7
IE
OA8H
EA
BIT LOCATION
FLAG
IE.O
EXO
Interrupt control bit for external interrupt O.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is ",".
IE.'
ETO
Interrupt control bit for timer interrupt O.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.
IE.2
EX'
Interrupt control bit for external interrupt ,.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.
IE.3
ET'
Interrupt control bit for timer interrupt' .
Interrupt disabled when bit is "0".
Interrupt enabled when bit is ",".
IE.4
ES
IE.5
ET2
IE.6
-
IE.7
EA
6
-
FUNCTION
Interrupt control bit for serial port.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.
Interrupt control bit for timer interrupt 2.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is ",".
Reserved bit. The output data is "'" if the bit is read.
Overall interrupt cont~ol bit.
All interrupts are disabled when bit is "0".
All interrupts are controlled by IE.O thru IE.5 when bit is ",".
345
e MSM80C154/83C154
e--------------------
Interrupt priority register UP)
ADDRESS
NAME
OBSH
f----FLAG
BIT LOCATION
IP
6
5
4
3
2
1
LSB
0
PCT
-
PT2
PS
PTl
PXl
PTO
PXO
FUNCTION
o.
IP.O
PXO
Interrupt priority bit for external interrupt
Priority is assigned when bit is "1 ".
IP.l
PTO
Interrupt priority bit for timer interrupt
Priority is assigned when bit is "1".
PXl
Interrupt priority bit for external interrupt 1.
Priority is assigned when bit is "1".
IP.3
PTl
Interrupt priority bit for timer interrupt 1.
Priority is assigned when bit is "1".
IP.4
PS
IP.5
PT2
IP.2
I
346
MSB
7
IP.6
-
IP.7
PCT
o.
Interrupt priority bit for serial port.
Priority is assigned when bit is "1".
Interrupt priority bit for timer interrupt 2.
Priority is assigned when bit is "1".
Reserved bit. The output data is "1" if the bit is read.
Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned
interrupts can be processed when this bit is "0". When the bit is
"1 ", the priority interrupt circuit is stopped, and interrupts can only
be controlled by the interrupt enable register (IE).
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Program status word register (PSW)
NAME
ADDRESS
PSW
ODOH
BIT LOCATION
PSW.O
--
MSB
_ n;~_±ic I
5
4
3
2
1
LSB
0
FO
RS1
RSO
OV
F1
P
FUNCTION
FLAG
P
Accumulator (ACC) parity indicator.
"1" when the "1" bit number in the accumulator is an odd number,
and "0" when an even number.
PSW.1
F1
User flag which may be set to "0" or "1" as desired by the user.
PSW.2
OV
Overflow flag which is set if the carry C6 from bit 6 of the ALU or
CY is "1" as a result of an arithmetic operation. The flag is also
set to "1" if the resultant product of executing a multiplication
instruction (MUL AB) is greater than OFFH, but is reset to "0"
if the product is less than or equal to OFFH.
PSW.3
RSO
RAM register bank switch
-
PSW.4
RS1
- - -----------.-
RS1
RSO
BANK
0
0
0
OOH - 07H
0
1
1
08H -OFH
1
0
2
10H - 17H
1
1
3
RAM ADDRESS
18H-1FH
-----
PSW.5
FO
User flag which may be set to "0" or "1" as desired by the user.
PSW.6
AC
Auxiliary carry flag.
This flag is set to "1" if a carry C 3 is generated from bit 3 of the
ALU as a result of executing an arithmetic operation instruction.
In all other cases, the flag is reset to "0".
PSW.7
CY
Main carry flag.
This flag is set to "1" if a carry C 7 is generated from bit 7 of
the ALU as result of executing an arithmetic operation instruction.
If a carry C 7 is not generated, the flag is reset to "0".
347
• MSM80C154/83C154
.-----~----------------
I/O control register (lOCON)
NAME
ADDRESS
MSB
7
IOCON
OF8H
WDT
BIT LOCATION
FLAG
6~bl
T32
SERR
4
IZC
3M~
P3HZ
P2H~
,I
P' HZ
LSB
0
ALF
FUNCTION
IOCON.O
ALF
If CPU power down mode (PO, HPD) is activated with this bit set to
",", the outputs from ports 0, ',2, and 3 are switched to floating
status.
When this bit is "0", ports 0, " 2, and 3 are in output mode.
IOCON.'
P'HZ
Port' becomes a high impedance input port when this bit is "'''.
IOCON.2
P2HZ
Port 2 becomes a high impedance input port when this bit is "'''.
IOCON.3
P3HZ
Port 3 becomes a high impedance input port when this bit is ",".
IOCON.4
IZC
IOCON.5
SERR
IOCON.6
T32
IOCON.7
WDT
348
--
-
The'O kohm pull-up resistance for ports ',2, and 3 is switched off
when this bit is ",", leaving only the' 00 kohm pull-up resistance.
Serial port reception error flag.
This flag is set to "'" if an overrun or framing error is generated
when data is received at a serial port.
The flag is reset by software.
Timer/counters 0 and' are connected serially to form a 32-bit
timer/counter when this bit is set to ",".
TF' of TCON is set if a carry is generated in the 32-bit timer/counter.
Watchdog timer mode is set when this bit is set to "'''. And if TF'
is set to "'" after watchdog timer mode has been set, the CPU is
reset and the program is executed from address O.
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Timer 2 control register (T2CON)
~~
~
====T=2=C=O=N====:==~0~C~8~H~+-_~-T;_~J_E~~L~c~~ l~K
NAME
ADDRESS
BIT LOCATION
T2CON.0
MSB
o
EXEN2
CP/RL2
FLAG
FUNCTION
CP/RL2
Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1".
16-bit auto reload mode IS set when TCLK + RCLK = "0" and
CP/RL2 = "0".
/R L2 is ignored when TCL_K_+_R_C_L_K_=_"_1_"_._ _ _ _ _ _ _ __
I
_______
LSB
3
+_~ -=- __ ~ C~
T2CON.1
C/T2
Timer/counter 2 count clock designation control bit.
The internal clocks (XTALl·2 712, XTALl·2 7 2) are used when
this bit is "0", and the external clock applied to the T2 pin is passed
to timer/counter 2 when the bit is "1".
---
T2CON.2
I
TR2
T2CON.3
EXEN2
T2CON.4
TCLK
T2Ci)",,-
hCLi<
I
----
T2CON.6
----~--
EXF2
Timer/counter 2 counting start and stop control bit.
Timer /counter 2 commences counting when this bit is "1" and stops
counting when "0".
T2EX timer/counter 2 external control signal control bit.
Input of the T2EX signal is disabled when this bit is "0", and
enabled when "1".
Serial port transmit circuit drive clock control bit.
Timer /counter 2 is switched to baud rate generator mode when this
bit is "1", and the timer/counter 2 carry signal becomes the serial
port transmit clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
I - ----
-
Serial port receive circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1", and the timer /counter 2 carry signal becomes the serial
port receive clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
r--------
- -
--~----------
Timer/counter 2 external flag.
This bit is set to "1" when the T2EX timer/counter 2 external
control signal level is changed from "1" to "0" while EXEN2 = "1".
This flag serves as the timer interrupt 2 request signal. If an interrupt
is generated, EXF2 must be reset to ;'0" by software.
- -1 - - - - - - - - - -
T2CON.7
TF2
Timer/counter 2 carry flag.
This bit is set to "1" by a carry signal when timer/counter 2 is in
16-bit auto reload mode or in capture mode.
This flag serves as the timer interrupt 2 request signal. If an interrupt
is generated, TF2 must be reset to "0" by software.
349
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
LIST OF INSTRUCTIONS
LIST OF INSTRUCTION SYMBOLS
:
:
:
:
:
:
:
:
:
:
:
:
:
+
:
:
X
:
I
(X)
:
((X))
:
:
#
@
:
:
:
<:
.....
:
:
:
<
:
>
bit address
:
code address :
data
relative offset:
direct address:
A
AB
AC
B
C
DPTR
PC
Rr
SP
AND
OR
XOR
D "*
350
Accumulator
Register pair
Auxiliary carry flag
Arithmetic operation register
Carry flag
Data pointer
Program counter
Register indicator (r = 0 - 7)
Stack pointer
Logical product
Logical sum
Exclusive OR
Addition
Subtraction
Multiplication
Division
Denotes the contents of X
Denotes the contents of address determined by the contents of X
Denotes the immediate data
Denotes the indirect address
Equality
Non equality
Substitution
Substitution
Negation
Smaller than
Larger than
RAM and the special function register bit specifier address (b o - b 7 )
Absolute address (Ao - A, 5 )
Immediate data (10 - 17)
Relative jump address offset value (Ao - R 7 )
RAM and the special function register byte specifier address (a o - a 7 )
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
MSM80C154/MSM83C154 INSTRUCTION TABLE
~
0
0000
0
0000
NOP
1
0001
JBC bit,
rei
1
0001
INC A
INC
direct
INC@RO
INC@Rl
DEC A
DEC
direct
DEC@RO
DEC@Rl
ADDA,
#data
ADDA,
direct
ADD A,
@RO
ADD A,
@Rl
ADDC A,
@RO
ADDC A,
@Rl
RR A
ACALL
LCALL
address.ll
(Page 0) address 16
RRC A
"'III
...
...
AJMP
address 11
(Page 1)
RET
RLA
3
0011
JNB bit,
rei
ACALL
address 11
(Page 1)
RETI
RLCA
4
0100
JC bit,
rei
AJMP
address 11
(Page 2)
5
0101
JNC rei
ACALL
address 11
(Page 2)
6
0110
JZ rei
-7
0111
JNZ rei
8
SJMP rei
1001
7
0111
AJMP
LJMP
address 11
(Page 0) address 16
JB bit,
rei
9
6
0110
4
0100
2
0010
1000
5
0101
3
0011
2
0010
,.
ORL
direct,
... #data
ORL
direct, A
,.
ANL
direct, A
AJMP
,. XRL
address 11
direct, A
(Page 3)
ACALL ,.
address 11
(Page 3)
AJMP
address 11
(Page 4)
MOV
ACALL
address 11
DPTR
#data 16 ... (Page 4)
AJMP
A
ORALC,bit address 11
1010
(Page 5)
~~L C,
,.
,.
ADDC A, ADDCA,
#data
direct
"'II1II
,.ORL A,
#data
ORLA,
direct
ORLA,
@RO
ORLA,
@Rl
ANL ...
ANL A,
direct,
#data
#data
ANLA,
direct
ANlA,
@RO
ANLA,
@Rl
XRL ...
direct,
#data
XRLA,
direct
XRLA,
@RO
XRLA,
@Rl
,.
XRLA,
#data
MOV@Rl,
#data
JMP
@A+DPTR
MOVA,
#data
ANLC,
bit
MOVCA,
@A+PC
DIVAB
MOV
direct 1,
direct 2
MOV
direct,
@RO
MOV
direct,
@Rl
MOV bit, MOVCA, SUBB A,
@A+DPTR
#data
C
SUBB A,
direct
SUBB A,
@RO
SUBB A,
@Rl
,....
...
,......
MOVC,
bit
MOV @RO,
direct
MOV@Rl,
direct
INC
DPTR
MUL AB
CPL bit
CPL C
CJNE A,
#data,
rei
CJNE A~ CJNE @RO~ CJNE @Rl,
#data,
direct,
#data,
rei
rei
rei
XCHA,
direct
,.
iii..
ANLC,bit
C
1100
PUSH
direct
AJMP
address 11
(Page 6)
CLR bit
CLR C
SWAP A
D
1101
POP
direct
ACALL
address 11
(Page 6)
SETB bit
SETB C
DAA
E
1110
MOVX A,
@DPTR
AJMP
address 11
(Page 7)
MOVX A, MOVX A,
@RO
(ill Rl
F
MOVX
@DPTR,A
ACALL
address 11
(Page 7)
...
f-----
1111
MOV'"
MOV @RO,
direct,
#data
... #data
bit
ACALL
address 11
(Page 5)
B
1011
,.
MOVX
ColRO, A
MOVX
(a'Rl, A
....
2 BYTE
...
iii..
...
DJNZ
direct,
... rei
XCH A,
@RO
XCH A,
@Rl
XCHD A,
@RO
XCH A,
@Rl
CLR A
MOVA,
direct
MOVA,
@RO
MOVA,
@Rl
CPLA
MOV
direct, A
MOV
@RO,A
MOV
@Rl,A
3 BYTE
MNEMONIC
2 CYCLE
4 CYCLE
351
II
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
- - --------
--- ---
-
~
1000
9
1001
0
0000
INC RO
INC R1
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
1
0001
DEC RO
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
2
0010
ADD A,
RO
ADDA,
R1
ADD A,
R2
ADD A,
R3
ADDA,
R4
ADDA,
R5
ADDA,
R6
ADDA,
R7
3
0011
ADDC A,
RO
ADDCA,
R1
AD DC A,
R2
ADDCA,
R3
ADDC A,
R4
ADDCA,
R5
ADDC A,
R6
ADDC A,
R7
4
0100
ORLA,
RO
ORLA,
R1
ORLA,
R2
ORLA,
R3
ORLA,
R4
ORLA,
R5
ORLA,
R6
ORLA,
R7
5
0101
ANLA,
RO
ANLA,
R1
ANLA,
R2
ANLA,
R3
ANLA,
R4
ANLA,
R5
ANLA,
R6
ANLA,
R7
6
0110
XRLA,
RO
XRLA,
R1
XRLA,
R2
XRLA,
R3
XRLA, I XRLA,
I
R4
R5
XRLA,
R6
XRLA,
R7
7
0111
MOV RO,
#data
MOV R1,
#data
MOV R2,
#data
MOV R6,
#data
MOV R7,
#data
8
MOV
direct,
RO
MOV
direct,
R1
MOV
direct,
R2
MOV
R6
MOV
direct,
R7
9
1001
SUBB A,
RO
SUBB A,
R1
SUBB A,
R2
SUBB A,
R6
SUBB A,
R7
A
1010
MOV RO,
direct
MOV R4, MOV R5, MOV R6,
direct .... direct IiII. direct
MOV R7,
direct
1000
B
1011
8
...
II"'"
MOV R1,
direct
IiII.
A
1010
B
1011
C
1100
D
1101
E
1110
1111
MOV R2,
direct
I""
MOV R3,
#data
MOV R4,
#data
I"" MOV
MOV
direct,
R4
direct,
IiII. R3
SUBB A,
R3
SUBB A,
R4
I""
MOV R3,
direct
IiII.
I""
I""
MOV
direct,
IiII. R5
I direct,
MOV R5,
#data
i
I
SUBB A,
R5
r
F
CJNE RO, CJNE R1, CJNE R2, CJNE R3, CJNE R41 CJNE R5, CJNE R6, CJNE R7~
#data,
#data,
#data,
#data,
#data, I #data,
#data,
#data,
rei
rei
rei
rei
rei
IiII. rei
IiII. rei
IiII. rei
I
I
C
1100
XCH A,
RO
XCHA,
R1
XCH A,
R2
D
1101
DJNZ RO
rei
DJNZ R1
rei
DJNZ R2,
rei
XCHA,
R3
I
XCH A,
R4
~JNZ R3, I""DJNZ R4,
rei
rei
IiII.
XCHA,
R5
XCH A,
R6
XCH A,
R7
DJNE R5, DJNE R6, DJNE R7,
rei
rei
rei
E
1110
MOVA,
RO
MOVA,
R1
MOVA,
R2
MOVA,
R3
MOV. A,
R4
MOVA,
R5
MOVA,
R6
MOVA,
R7
F
MOV RO,
A
MOV R1,
A
MOV R2,
A
MOV R3,
A
MOV R4,
A
MOV R5,
A
MOV R6,
A
MOV R7,
A
1111
352
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
INSTRUCTION SET DETAILS
.,c.
I nstruction Code
Mnemonic
>
I-
Descriptio n
Bytes Cycles
D7 D. Os 0_ 0 3 0, 0, Do
ADD A, Rr
0
0
1
0
1
r, r,
ro
1
(AC), (OV), (C), (A) +- (A)+(Rr)
2
1
(AC), (OV), (C), (A) +- (A)+(direct
address)
1
-- - -
ADD A, direct
0
0
1
0
0
1
0
1
a7 a. as a_ a3 a, a, ao
ADD A,@Rr
0
0
1
0
0
1
1
ro
1
1
(AC), (OV), (C), (A) +- (A)+((Rr))
ADD A, #data
0
0
1
0
0
1
0
0
2
1
(AC), (OV), (C), (A) +- (A)+#data
17 I. Is I_ I, I, I,
10
ADDC A, Rr
ADDC A, direct
0
0
1
1
1
r, r, ro
1
1
(AC), (OV), (C), (A) +- (A)+(C)+(Rr)
0
0
1
1
0
1
0
2
1
(AC), (OV), (C), (A) +- (A)+(C) +(direct
address)
1
a7 a. as a_ a, a2 a, ao
'"c:
0
'B
ADDC A,@Rr
0
0
1
1
0
1
1
ro
1
1
(AC), (OV), (C), (A) +- (A)+(C)+((Rrl)
ADDC A, #data
0
0
1
1
0
1
0
0
2
1
(AC), (OV), (C), (A) +- (A)+(C)+#data
h I. Is I_ I, I, I, 10
;:
t:
c:
c:
SUBB A, Rr
.Q
.."'
SUBB A, direct
0
SUBB A,@Rr
c.
.,
0
0
1
1
r, r, ro
1
1
(AC), (OV), (C)' (A) +- (A)-((C))+((Rr))
1
0
0
1
0
1
0
2
1
(AC), (OV), (C), (A) +- (A)-((C)+(direct
address) )
1
a7 a. as a. a, a, a, ao
Iii
u
.;:;
1
E
SUBB A, #data
c:
E·:::>
u
u
Bytes Cycles
Mnemonic
I-
Description
D, D. Ds D. D_ D, D, Do
RR
A
0
0
0
0
0
0
1
1
1
Accumulator
1
@JC: 1-1-1-1-1-1-I; ~
c:
0
.;;
OJ
~ ~
8".Q
0°
... ::l
RRC A
0
SWAP A
OJ ...
0
0
1 0
0
1
1
1
1
-1;;
::l c:
E·-
::l
U
U
Accumulator
E: 1-1- I- I- 1-1-1;1
<{
1
1
0
0
0
1
0
0
1
1
(A. - ,) ... (Ao - _)
INC
A
0
0
0
0
0
1 0
0
1
1
(A)
INC
Rr
0
0
0
0
1
r, r, ro
1
1
(Rrl
INC
direct
0 0 0 0 0 1 0 1
a, a. as a • a_ a, a, a.
2
1
(direct address)
'"E
INC
@Rr
0
~
~
INC
DPTR
1 0
DEC
A
0
0
DEC
Rr
0
0
DEC
...
c:
+-
(A)+l
+-
(Rrl+l
+-
(direct address)+l
0
0
1
1
ro
1
1
((Rrl)
1 0
0
0
1
1
1
2
(DPTR)
0
1 0
1
0
0
1
1
(A)
0
1
r, r, ro
1
1
(Rrl
direct
0 0 0 1 0 1 0 1
a, a. as a. a_ a, a, a.
2
1
(direct address)
DEC
@Rr
0
0
0
1
0
1
ro
1
1
((Arl)
+-
ANL
A, Rr
0
1
0
1
1
r, r, r.
1
1
(A)
+-
(A) AND (Rrl
ANL
A, direct
0 1 0 1 0 1 0 1
a, a. as a. a_ a, a, ao
2
1
(A)
+-
(A) AND (direct address)
ANL
A,@Rr
0
1 1 ro
1
1
(A)
+-
(A) AND ((Rrl)
'"c:0
"E
ANL
A, #data
0 1 0 1 0 1 0 0
I, I. Is I. I, I, I, 10
2
1
(A)
+-
(A) AND #data
2
ANL
direct, A
0 1 0 1 0 0 1 0
a, a. as a • a_ a, a, ao
2
1
(direct address)
AND (A)
<--
(direct address)
ANL
direct,
#data
0 1 0 1 0 0 1 1
a, a. as a. a_ a, a, a.
I, I. Is I. I_ I, I, 10
3
2
(direct address)
AND #data
+-
(direct address)
iii
u
ORL
A, Rr
0
r, r, ro
1
1
(A)
<--
(A) OR (Rr)
0
..J
ORL
A, direct
0 1 0 0 0 1 0 1
a, a. as a. a_ a, a, ao
2
1
(A)
+-
(A) OR (direct address)
ORL
A,@Rr
0
1 1 ro
1
1
(A)
+-
(A) OR ((Rrl)
ORL
A, #data
0
1 0 0 0 1 0 0
I, I. I, I. I_ I, I, I.
2
1
(A)
+-
(A) OR #data
f
...c:
'E"
'"...c:u
-
1;;
.=
0
0
1 0
1
1 0
1
+-
+-
((Rr))+l
+-
(DPTR)+l
(A)-l
+-
(Rrl-l
+-
(direct address)-l
((Rrl)-l
c:
0
.;;
E
'a."
0
1
0
0
1
'0,
354
1 0
0
0
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
INSTRUCTION SET DETAILS (CONT.)
Instruction Code
(1)
a.
>
Mnemonic
t-
ORL
direct, A
0 1 0 0 0 0 1 0
a7 a. as a. a, a, a, ao
2
1
(direct address) <- (direct address) OR
(A)
ORL
direct,
#data
0 1 0 0 0 0 1 1
a7 a. as a_ a, a, a, ao
17 I. Is I_ I, I, I, 10
3
2
(direct address) <- (direct address) OR
#data
on
c
.gu
Description
Bytes Cycles
O, D. Ds D. D, D2 D, Do
XRL
A,Rr
0
r, r, ro
1
1
(A) <- (A) XOR (Rr)
1;;
XRL
A, direct
0 1 1 0 0 1 0 1
a7 a. as a_ a, a, a, ao
2
1
(A) <- (A) XOR (direct address)
~
XRL
A,@Rr
0
ro
1
1
(A) <- (A) XOR ((Rr))
XRL
A, #data
0 1 1 0 0 1 0 0
17 I. Is I_ I, I, I, 10
2
1
(A) <- (A) XOR #data
XRL
direct, A
0 1 1 0 0 0 1 0
a, a. as a_ a, a, a, ao
2
1
(direct address) <- (direct address)
XOR (A)
XRL
direct,
#data
0 1 1 0 0 0 1 1
a7 a. as a_ a, a, a, ao
I, I. 15 I_ I, I, I, 10
3
2
(direct address) <- (direct address) XOR
#data
MOV A, #data
0 1 1 1 0 1 0 0
17 I. Is I_ I, I, I, 10
2
1
(A) <- #data
MOV
0 1 1 1 1 r, r, ro
17 I. Is I_ I, I, I, 10
2
1
(Rr) <- #data
2
c
c
0
.;:;
1
1
1 0
1
0
1
0
1
1
(1)
a.
0
'iii
.~
OJ
0
....J
on
c
0
.;:;
u
2
Rr, #data
1;;
.!:
OJ
MOV direct,
#data
0 1 1 1 0 1 0 1
a7 a. as a_ a, a2 a, ao
17 I. Is I_ I, 12 I, 10
3
2
(direct address) <- #data
'£:
'tJ
MOV @Rr, #data
0 1 1 1 0 1 1 ro
17 I. Is I_ I, I, I, 10
2
1
(Rr)) <- #data
MOV
DPTR,
#data 16
1 0 0 1 0 0 0 0
I,; 1,_ 113 III I" 1'0 I. I.
17 I. Is I_ I, 12 I, 10
3
2
(DPTR) <- #data 16
CLR
C
1
1
0
0
0
0
1
1
1
1
(C) <-0
c
III
19
OJ
...
.!!!
(1)
al
E
E
-
SETS C
1
1
0
1 0
0
1
1
1
1
(C) <- 1
c
0
.;:;
CPL
C
1
0
1
1 0
0
1
1
1
1
(C) <- (C)
2
ANL
C, bit
1 0 0 0 0 0 1 0
b 7 b. b s b_ b, b 2 b, b o
2
2
(C) <- (C) AND (bit address)
ANL
C.lbit
1 0 1 1 0 0 0 0
b 7 b 6 b s b_ b, b, b, b o
2
2
(C) <- (C) AND (bit address)
ORL
C, bit
0 1 1 1 0 0 1 0
b 7 b. b s b_ b, b 2 b, b o
2
2
(C) <- (C) OR (bit address)
ORL
C.lbit
1 0 1 0 0 0 0 0
b 7 b 6 b s b_ b, b 2 b, b o
2
2
(C) <- (C) OR (bit address)
MOV
C, bit
1 0 1 0 0 0 1 0
b 7 b 6 b s b_ b, b, b, b o
2
1
(C) <- (bit address)
on
u
1;;
.!:
c
0
.;:;
...
OJ
(1)
a.
0
OJ
'"
;;::
~
u'"
-
355
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
INSTRUCTION SET DETAILS (CONT.)
..
Instruction Code
0.
Mnemonic
....>
Bytes
Fvc1es
D, D. Ds D4 D, D2 D, Do
Description
MOV bit,C
1 0 0 1 0 0 1 0
b, b. b s b 4 b 3 b 2 b, b o
2
2
(bit address)
+-
(C)
SETB bit
1 1 0 1 0 0 1 0
b, b. b s b 4 b 3 b 2 b, b o
2
1
(bit add ress)
+-
1
I: ..
.gco'-g
tt) CLA
bit
2
1
(bit address)
+-
0
.~~
1 1 0 0 0 0 1 0
b, b. b s b 4 b 3 b 2 b, b o
bit
1 0 1 1 0 0 1 0
b, b. b s b 4 b 3 b 2 b, b o
2
1
(bit address)
+-
(bit address)
MOV A,Ar
1
r2 r, ro
1
1
(A)
+-
(Ar)
MOV A, direct
1 1 1 0 0 1 0 1
a, a. as a4 a3 a2 a, ao
2
1
(A)
+-
(direct address)
MOV A,@Ar
1
1
1
0
0
1
ro
1
1
(A)
+-
((Ar))
MOV Ar,A
1
1
1
1
1
r 2 r, ro
1
1
(Ar)
+-
(A)
MOV Ar, direct
1 0 1 0 1 r2 r, ro
a, a. as a4 a3 a2 a, ao
2
2
(Ar)
+-
(direct address)
MOV direct, A
1 1 1 1 0 1 0 1
a, a. as a4 a. a2 a, ao
2
1
(direct address)
+-
(A)
MOV direct, Rr
1 0 0 0 1 r2 r, ro
a, a. a, a4 a3 a2 a, ao
2
2
(direct address)
+-
(Ar)
MOV direct,
@Rr
1 0 0 0 0 1 1 ro
a, a. as a4 a3 a2 a, ao
2
2
(direct address)
+-
((Rrl)
MOV @Rr,A
1
ro
1
1
((Ar))
+-
(A)
MOV @Ar,
direct
1 0 1 0 0 1 1 ro
a, a. a, a4 a. a2 a, ao
2
2
((Ar))
+-
(direct address))
MOVCA,
@A+DPTA
1 0
0
1 0
0
1
1
1
2
(A)
((A)+(DPTR))
1 0
0
0
0
0
1
1
1
2
(PC) +- (PC) + 1
(A) +- ((A) + (PC))
0
0
1
0.::1
11)'-
.
CPL
1
1 0
1
I:
.2
tJ
2
1
Ii:
.=...
.
't;
.......
a'"
I:
co
co
.
~
01:
u.2
~tJ
t: 2 MOVC A,@A+PC
8·~
GO
a>"
I: I:
"'0
.1:'-
u"
XU
lIlt;
a
356
1
1
0
1
1
+-
XCH
A, Rr
1
r2 r, ro
1
1
(A) ¢ (Ar)
XCH
A, direct
1 1 0 0 0 1 0 1
a, a. a, a4 a3 a2 a, ao
2
1
(A) ¢ (direct address)
XCH
A,@Ar
1
1
XCHD A,@Ar
1
1 0
.. 2
"
I:
co._
1
1
0
0
1
1 ro
1
1
(A) ¢ ((Rrl)
1 0
1
1
1
1
(A O - 3 )¢((Ar o-.))
0
ro
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
INSTRUCTION SET DETAILS (CONT.)
I nstruction Code
CD
0-
>
I-
Mnemonic
PUSH direct
1
1
0
0
0
0
0
0
2
2
(SP) +- (SP)+l
((SP)) +- (direct address)
2
2
(direct address) +- ((SP))
(SP) +- (SP)-l
2
2
(PC) +- (PC)+2
(SP) +- (SP)+l
((SP)) +- (PC o -,)
(SP) +- (SP)+l
((SP)) +- (PC. -15)
(PC O - ,O ) +- A.-,.
3
2
(PC) +- (PC)+3
(SP) +- (SP)+l
((SP)) +- (PC o -,)
(SP) +- (SP)+l
((SP)) +- (PC. -IS)
(PC. -IS) +- A.-IS
a, a. as a. a3 a. a, a o
POP
direct
1
1 0
1
0
0
0
0
a, a. as a. a3 a 2 a , ao
ACALL addr 11
A,oA. A. 1 0 0 0 1
A,A.AsA.A3A2A,Ao
UI
e::
0
.~
::>
~
.:
CD
LCALL addr 16
0
0
0
1
0
0
1
0
AISAI.A13A,.AII AIOA. A.
A, A. As A. A3 A2 A, Ao
e::
.;:
::>
e
.0
::>
U)
u
::>
1
0
1
2
(PC'- IS ) +- ((SP))
(SP) +- (SP)-l
(PC.-,) +- ((SP))
(SP) +- (SP)-l
1 0
0
1 0
1
2
(PC'- IS ) +- ((SP))
(SP) +- (SP)-l
(PC o -,) +- ((SP))
(SP) +- (SP)-l
2
2
(PC) +- (PC)+2
(PC. -,0) +- A. -,.
3
2
(PC. -IS) +- A.-IS
2
2
(PC) +- (PC)+2
(PC) +- (PC)+relative offset
1
2
(PC) +- (A)+(DPTR)
3
2
(PC) +IF
THEN
(PC) +IF
THEN
0
1 0
RETI
0
0
1
AJMP addr 11
A,oA. A. 0 0 0 0 1
A,A.A s A.A 3 A.A , Ao
LJMP addr 16
0
0
0
0
0
0
1 0
AISAI.A13AI2AIIA,.A. A.
A, A. As A. A3 A2 A, A •
~
0-
0
0
.:
E
0
RET
UI
e::
0
.;:
SJMP rei
1
0
0
0
0
0
0
0
R, R. Rs R. R3 R. R, R.
....,::>
JMP
@A+DPTR
CJNE A, direct,
rei
0
1
1
1 0
0
1
1
1 0 1 1 0 1 0 1
a, a. as a. a3 a. a, ao
R,R.R s R.R 3 R.R , R.
UI
e::
·8u
.r.
u
e::
~
!XI
(PC)+3
(A) (direct address)
*
(PC)+relative offset
(A) < (direct address)
(C) +- 1
ELSE
2
t:
.:
Description
Bytes Cycles
0, D. Os D. 0 3 O2 0 , Do
(C) +- 0
--_ .. -
CJNE A, #data,
rei
1 0
1
1 0
1
0
0
I, I. Is I. 13 12 I, 10
R, R. Rs R. R3 R. R, Ro
3
2
(PC) +IF
THEN
(PC) +IF
THEN
(PC)+3
(A) #data
*
(PC)+relative offset
(A) < #data
(C) +-1
ELSE
(C) +- 0
357
• MSM80C154/83C154 •
INSTRUCTION SET DETAILS (CaNT.)
I nstruction Code
8-
~
Description
Bytes Cycle
Mnemonic
D7 D. D, D. D, D2 D, Do
CJNE Rr, #data,
rei
1 0 1 1 1 rz rl ro
17 I. Is I. I, 12 II 10
R 7 R.R s R.R,R z R,R o
3
2
(PC) <-IF
THEN
(PC) <-IF
THEN
(PC)+3
((Rr)) #data
*
(PC)+relative offset
((Rr)) < #data
(C) <-- 1
ELSE
(C) <--0
CJNE @Rr,
#data, rei
1 0 1 1 0 1 1 ro
17 I. Is I. I, I, I, 10
R 7 R.R,R.R,R,R,R o
3
2
(PC) <-- (PC)+3
((Rr)) #data
IF
THEN
(PC) <-- (PC)+relative offset
((Rr)) < #data
IF
THEN
(C) <-- 1
ELSE
(C) <--0
DJNZ Rr, rei
1 1 0 1 1 r2 fl ro
R7 R. Rs R. R3 R, R, Ro
2
2
(PC) <-(Rr) <-IF
THEN
(PC) <--
'"c:
.g
"2
1;;
c:
DJNZ direct, rei
or:
c:
"
1 1 0 1 0 1 0 1
a7 a. as a. a3 a, a, ao
R7 R. Rs R. R3 R, R, Ro
3
2
(PC)+2
(Rr)-1
(Rr) 0
*
(PC)+relative offset
(PC) <-- (PC)+3
(direct address) <-- (direct address)-1
IF
(direct address) 0
THEN
(PC) <-- (PC)+relative offset
*
rii'"
358
*
JZ
rei
0 1 1 0 0 0 0 0
R7 R. Rs R. R3 R, R, Ro
2
2
(PC) <-- (PC)+2
(A) =0
IF
THEN
(PC) <-- (PC)+relative offset
JNZ
rei
0 1 1 1 0 0 0 0
R7 R. Rs R. R, R, R, Ro
2
2
(PC) <-- (PC)+2
IF
(A) 0
THEN
(PC) <-- (PC)+relative offset
JC
rei
0 1 0 0 0 0 0 0
R7 R. Rs R. R3 Rz R, Ro
2
2
(PC) <-- (PC)+2
(C) = 1
IF
THEN
(PC) <-- (PC)+relative offset
JNC
rei
0 1 0 1 0 0 0 0
R7 R. Rs R. R3 Rz R, Ro
2
2
(PC) <-- (PC)+2
(C) = 0
IF
THEN
(PC) <-- (PC)+relative offset
JB
bit, rei
0 0 1 0 0 0 0 0
b 7 b. b s b. b, b z b, b o
R7 R. Rs R. R3 Rz R, Ro
3
2
(PC) <-- (PC)+3
(bit address) = 1
IF
THEN
(PC) <-- (PC)+relative offset
JNB
bit, rei
0 0 1 1 0 0 0 0
b 7 b. b s b. b 3 b z b, b o
R7 R. Rs R. R3 Rz R, Ro
3
2
(PC) <-- (PC)+3
(bit address) = 0
IF
THEN
(PC) <-- (PC)+relative offset
*
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
INSTRUCTION SET DETAILS (CaNT.)
I nstruction Code
Q)
a.
'"c: JBC
bit, rei
U
'" '"
~
Description
D7 D. Ds D. D. D, D, Do
.&:0
0'';;
c:
Bytes Cycle
Mnemonic
>
f-
~
0 0 0 1 0 0 0 0
b 7 b. b s b. b. b, b, bo
R7 R. Rs R. R. R, R, Ro
3
2
(PC) <- (PC)+3
(bit address) = 1
IF
THEN
(bit address) <- 0
(PC) <- (PC)+relative offset
all;;
c:
~
0",
E
c:
Q) 0
E'i;
-'"c: ...'~"
'"
~
f·~
x
w
MOVX A,@Rr
1
1
1
0
0
0
1
ro
1
2
(A)
<-
((Rd) EXTERNAL RAM
MOVX A, @DPTR
1
1
1
0
0
0
0
0
1
2
(A)
<-
((DPTR}) EXTERNAL RAM
MOVX @Rr,A
1
1
1
1
0
0
1
ro
1
2
(Rd
MOVX @DPTR,A
1
1
1
1
0
0
0
0
1
2
((DPTP))
0
0
0
0
0
0
0
0
1
1
(PC)
'" NOP
c:
0
~
Q) '';::;
<-
<-
(A) EXTERNAL RAM
<-
(A) EXTERNAL RAM
(PC)+1
.&:u
...
",
o~
l;;
.!:
359
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - -
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Rating
Unit
Vee
= 25°C
Ta = 25°C
-0.5 -7
V
Ta
VI
Tstg
Storage temperature
-0.5 - Vee + 0.5
V
-55-+150
°c
Operational Range
... DC to 12 MHz, VCC = ±20%
• MSM8OC154/83C154
• MSM8OC154-1 /83C154-1 ... DC to 16 MHz VCC = ±10%
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
Vee
*1 fosc = DC-16 MHz
2.5 - 6
V
Memory hold voltage
Vee
2-6
V
Ambient temperature
Ta
-40-+85
°c
*1: 2.5 V';; Vee < 4 V DC characteristics will be specified elsewhere.
16 MHz version of MSM83C154 (12 MHz < XTAL 1·2.;; 16 MHz) is being developed.
DC Characteristics
(VCC = 5V±1 0%, Ta =
Parameter
-40 to +85°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
-0.5
0.2VCC-O·l
V
Input Low Voltage
VIL
Input High Voltage
VIH
Except XTALl and
RESET
0.2 VCC +0.9
VCC + 0.5
V
Input High Voltage
VIHI
XT AL 1 and RESET
0.7 VCC
VCC + 0.5
V
Output Low Voltage
(PORT 1,2,3)
VOL
IOL = 1.6 mA
0.45
V
Output Low Voltage
(PORT 0, ALE, PSEN)
Vall
IOL = 32 rnA
0.45
V
Output High Voltage
(PORT 1,2,3)
VOH
IOH =-60 IJA
VCC=5V±10%
2.4
V
IOH =-30IJA
0.75 VCC
V
Meas·
uring
circuit
1
Output High Voltage
(PORT 0, ALE, PSEN)
VOHI
IOH = -10 IJA
0.9 VCC
V
IOH = -400IJA
VCC=5V± 10%
2.4
V
IOH = -150 IJA
0.75 VCC
V
IOH = -401JA
0.9 VCC
V
-10
Logical 0 Input Current
(PORT 1,2,3)
IlL
VI=0.45V
Logical 1 to 0 Transition
Current (PORT 1,2,3)
ITL
Input Leakage Current
(PORT 0 floating, EA)
ILl
-200
IJA
VI=2.0V
-500
IJA
VSS
0-
=>
t-
Z
=>
o
3
4
~
~
Vec
VIH
M
0'"
~
VIL
t-
t-
VIH
=>
0-
=>
0Z
=>
0
VIL
Vss
-=Note
M
'"
o
t-
-=-
1
~
l-
t-
=>
=>
0-
0-
t-
Z
=>
0
Vss
1. Repeated for specified input pins.
2. Repeated for specified output pins.
3. Input logic for specified status.
361
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
External Program Memory Access AC Characteristics
(VCC = 5 V ± 20%, VSs=O V, XTAL1·2 = 12 MHz, Ta = -40 °c to 85°C
VCC = 5 V ± 10%, VSS = 0 V, 12 MHz < XTAL1·2.;; 16 MHz, Ta = -40°C to 85°C
PORT 0, ALE, and PSEN connected with 100 pF load, other connected with 80 pF load)
Ratings
Symbol
Parameter
16 MHz clock
Min.
Max.
Variable clock from
DC to 16 MHz
Min.
Unit
Max.
62.5
ns
85
2tCLCL40
ns
18.5
1tCLCL44
ns
27.5
1tCLCL-35
ns
tCLCL
62.5
ALE Pulse Width
tLHLL
Address Valid to ALE Low
tAVLL
Address Hold After ALE
Low
tLLAX
ALE Low to Valid Instr In
tLLlV
ALE Low to PSEN Low
tLLPL
32.5
1tCLCL-30
ns
PSEN Pulse Width
tPLPH
152.5
3tCLCL-35
ns
PSEN Low to Valid Instr
In
tPLIV
Input Instr Hold After
PSEN
tPXIX
Input Instr Float After
PSEN
tPXIZ
XTAL1·2 Oscillator Period
tPXAV
PSEN to Address Valid
3tCLCL-105
82.5
42.5
42.5
ns
ns
0
0
ns
1tCLCL-20
1tCLCL-20
ns
ns
- - f------
Address to Valid Instr In
tAV1V
Address Float to PSEN
Low
tAZPL
207.5
5tCLCL-105
0
0
External program memory read cycle
ALE
~tA~V:.=L~L~tL~L!:.'PL,+-_ tPLPH
tLLlV
362
4tCLCL-100
150
ns
ns
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
External Program Memory Access AC Characteristics
(VCC = 5 V ± 20%, VSS = 0 V, XTAL1·2 = 12 MHz, Ta = -40°C to 85°C
VCC = 5 V ± 10%, VSS=O V, 12 MHz < XTAL1·2';; 16 MHz, Ta = -40°Cto85°C
PORT 0, ALE, and PSEN connected with 100 pF load, other connected with 80 pF load)
Ratings
Parameter
Symbol
16 MHz clock
Min.
Max.
Variable clock from
DC to 16 MHz
Min.
Unit
Max.
XTAL 1 ·2 Oscillator Period
tCLCL
62.5
ALE Pulse Width
tLHLL
85
2tCLCL40
ns
Address Valid to ALE Low
tAVLL
18.5
ltCLCL44
ns
Address Hold After ALE
Low
tLLAX
27.5
ltCLCL-35
ns
RD Pulse Width
tRLRH
275
WR Pulse Width
tWLWH
275
RD Low to Valid Data In
tRLDV
Data Hold After RD
tRHDX
Data Float After RD
tRHDZ
55
ALE Low to Valid Data In
tLLDV
Address to Valid Data In
tAVDV
ALE Low to RD or WR
Low
tLLWL
147.5
180
ns
62.5
6tCLCL-l00
6tCLCL-l00
207.5
0
ns
5tCLCL-l05
ns
ns
0
2tCLCL-70
ns
400
8tCLCL-l00
ns
457.5
9tCLCL-l05
ns
3tCLCL+40
ns
227.5
3tCLCL40
Address to RD or WR Low
tAVWL
4tCLCL-70
ns
Data Valid to WR
Transition
tQVWX
22.5
ltCLCL40
ns
Data Valid to WR High
tQVWH
332.5
7tCLCL-l05
ns
Data Hold After WR
tWHQX
75
2tCLCL·50
ns
Address Float to RD Low
tAZRL
RD or WR High to ALE
High
tWHLH
0
32.5
102.5
ltCLCL·30
0
ns
1tCLCL+40
ns
363
• MSM80C154/83C154 • - - - - - - - - - - - - - - - - - - - -
External data memory read cycle
ALE
PORTO :~STR
PORT 2
PCH
External data memory write cycle
ALE
tLLWL:.j..~_ _ tWLWH
tLLAX
-'I
~________________
tQVWH
PORTO
:~STR
DATA (ACC)
AS - A15PCH
364
P2.0 - P2.7 DATA or AS - A16 DPH
AS - A15PCH
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Serial Port
CI/O Extension Mode) AC Characteristics
VCC = 5 V ±20%, VSS= 0 V, XTAL1·2 = 12 MHz, Ta = -40°C to 85°C
VCC = 5 V ±10%, Vss = 0 V, 12 MHz < XTAL1·2';; 16 MHz, Ta = -40 °c to 85°C
Parameter
Symbol
Min.
Max.
Unit
Serial Port Clock Cycle Time
tXLXL
12tCLCL
Output Data Setup to Clock Rising Edge
tOVXH
10tCLCL-133
ns
Output Data Hold After Clock Rising Edge
tXHOX
2tCLCL-75
ns
Input Data Hold After Clock Rising Edge
tXHDX
0
ns
Clock Rising Edge to Input Data Valid
tXHDV
ns
10tCLCL-133
ns
MACHINE CYCLE
ALE
jtXLXL--j
SHIFT CLOCK
rtOVXH~
OUTPUT OATA
rtXHOX
I
--,\::::::XX::::::XX~=-=-=-=-=-~Xx=====~Xx~=-=-=-::-=-XX::::~xC====~xC:::::7/---
~tXHDV1 ~
INPUT DATA
AL
AL
rtXHDX
AL
ALI
AL
AL
ALI
AL
365
• MSM80C154/83C154 • - - - - - - - - - - - - - - - - - - - -
,
.
,
.
---------,----=x
AC Characteristics Measuring Conditions
1. Input/output signal
VOH
VIH TEST POINT
VOL
VOH
VvllHLX
VIL
' - - - - - VOL
* The input signals in AC test mode are either VOH (logic "1")
or VOL (logic "0") input signals where logic "1" corresponds
to a CPU output signal waveform measuring point in excess of
VIH,and logic "0" to a point below VIL'
2. Floating
Floating
VOH--""",I
-I\VIH
-,~VIL
VOL--......."
* The port 0 floating interval is measured from the time the
port 0 pin voltage drops below VIH after sinking to GND at
2.4 mA when switching to floating status from a "1" output,
and from the time the port 0 pin voltage exceeds VIL after
connecting to a 400 IJA source when switching to floating
status from a "0" output.
XTAL 1 External Clock Input Waveform Conditions
Parameter
Symbol
Min.
Max.
Units
16
MHz
l/tCLCL
DC
High Time
tCHCX
20
20
Oscillator Freq.
ns
Low Time
tCLCX
Rise Time
tCLCH
20
ns
Fall Time
tCHCL
20
ns
EXTERNAL CLOCK DRIVE WAVEFORM
NC
XTAL2
EXTERNAL
OSCILLATOR------------------~XTAL1
SIGNAL
VSS
366
ns
OKI
semiconductor
MSM85C154VS
M83C154/M80C51 F PIGGY BACK
GENERAL DESCRIPTION
The MSM85C154 is a device whose built-in ROM is replaced by external EPROM using the piggyback method. External EPROM capacity is up to 16K bytes. It can be used for evaluation of programs
for MSM83C154 and MSM80C51F.
INSTALLATION METHOD FOR EXTERNAL ROM
M85C154
OKI
Pin 1 For 27128
* The MSM85C154VS pin layout of bottom side is the same as the pin
layout for MSM83C154-XXRS.
367
• MSM85C154VS . ' - - - - - - - - - - - - - - - - - - - - - - - -
*NOTE
MSMB5C154VS piggy back is originally designed for the programming of MSM~C154 and it covers the
function as the piggy back for MSMBOC51F.
Please be careful not to use additional function which dedicated to MSMB3C154 in usig the piggy back for
MSMBOC51. The function, flag, and resistor listed below are dedicated to MSMB3C154.
ICON (OFBH)
TH2 (OCDH)
TL2 (OCCH)
RCAP2H (OCBH)
RCAP2L (OCAH)
T2CON (OCBH)
IP (OBBH)
IE (OABH)
PCON (OB7H)
: I/O CONTROL RESISTOR
:TIMER 2. UPPER SIDE RESISTOR
:TIMER 2. LOWER SIDE RESISTOR
: CAPTURE RESISTOR. UPPER SIDE
: CAPTURE RESISTOR. LOWER SIDE
: TIMER CONTROL RESISTOR 2
: INTERRUPT PRIORITY RESISTOR 2
bit 5 (Bit address BDH) PT2
bit 7 (Bit address BFH) PCT
: INTERRUPT ENABLE RESISTOR
bit 5 (Bit address ADH) ET2
: POWER CONTROL RESISTOR
bit 5 (Bit address Nil) RPD
bit 6 (Bit address Nil) HPD
In using this piggy back for MSMBOC51 F, do not set the above items (Control bit should not be "1").
All bits are set to "0" at initial reset.
In high temperature atmosphere, malfunction may happen (output latches of the Port 0 are set when
interrupt occurs) in writing the instruction code of which LSB is "0" at address 0 of the EPROM.
To avoid this problem, please be sure to write AJMP instruction (operational code is X1) at address 0 instead
of LJMP instruction (operational code is 02).
Operating frequency is from DC to 12MHz.
The MSMB5C154VS has been developed assuming that it is used for evaluation of program. Please use the
MSM83C154 (mask ROM version) as the devices installed on a product.
368
PROGRAM DEVELOPMENT
SUPPORT SYSTEMS
o
EASE40 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the
OLMS40 Series 4-Bit, 1-Chip Microcontroller
EASE40 PROGRAM DEVELOPMENT SUPPORT SYSTEM
The OKI EASE40 Program Development Support System designed for use with the CMOS 4-bit,
1-chip microcontroller OLMS40 Series consists of the MPB400 (evaluation board) and the
MPB400DS (key & display board), plus a number of EASE40 microcontroller interface boards. These
components can also be connected by MULTIBUS interface or serial I/O interface to the "SO series"
of development tools or serial I/O terminal units for even more efficient program development.
• Since the MPB400 includes a MULTIBUS interface, it can be connected online to "SO series" development
systems equipped with an existing MULTIBUS interface to enable direct use of the system console and
1/0 units.
• With an MPB401 connected to the MPB400, online connections are also possible to serial.
interface systems (such as the ifSOO personal computer).
• A floppy disk based assembler/debugger is available for use in online type systems. (CP/M®,
ISIS-II base)
Note: (CP/M"' is the registered trademark of Digital Research Inc. (USA).
ISIS-II and MULTIBUS are registered trademarks of Intel Corp (USA).
II
371
• EASE40 .-----------------------------------------------------
SYSTEM CONFIGURATION
[1] SERIAL INTERFACE TYPES
FEATURES
The serial interface type employs serial interface
equipped development tools available on the
market or personal computers, together with the
MPB400 board and MPB401 .
ItaOO OKI personal
computer
eN1
HOST COMPUTER REQUIREMENTS
Note: 1. Where "80 series" development
systems other than the if800 are
used, the system must be capable
of using CP/M.
2. The MPB401 is connected
directly to the MPB400 via a
socket.
1. CP/M-80 version 2.0 or 2.2 must be operable as
the operating system.
2. The host computer memory capacity must be large
enough to operate at least 52K bytes of CP/M.
3. Interface must be RS232C, TTL, or 20 rnA current
loop.
4. The RS232C serial port must be accessible
when the CPIM system calls function No.6
(direct console 110), on condition that a
logical device CON: is assigned to a physical
device TTY.
Oki personal computers if800 model 20 and
model 30 are standard host computers which
satisfy these reqUirements.
[2] BUS INTERFACE TYPES
D
FEATURES
MP84000S
CN1
CN2
MPB400
MULTIBUS equipped "80
senes" development system
(Intel: MDS System
DSCe System)
Note: For Bus interface types, an
online/offline switch located on
MPB400DS is set to "online"
position.
372
Bus interface types employ MULTIBUS equipped
development tools available on the market, e.g.,
the MPB400, and MPB400DS. Use of an FDD
unit (floppy disk drive) which the development
system has as standard equipment, enables
disk base editing, assembling, and debugging.
When debugging especially, a disk based
"debugger" enables loading, excuting and
correcting of users' application programs from a
development system console.
HOST COMPUTER REQUIREMENTS
1. Intel 8080A microprocessor or equivalent processor is used as the CPU.
2. Intel MULTIBUS or equivalent bus system is
used.
3. ISIS-II or CP/M-80 msut be operable as the
operating system.
4. 00 is not used as the 8080A (or equivalent)
microprocessor I/O address.
- - - - - - - - - - - - - - - - - - - - - - - - - - . EASE40 •
[3] FIELD DEBUGGING TYPES
FEATURES
User's application
circuit
Field debugging types are used for final field evaluation
of application circuits and programs after program
debugging with serial interface or bus interface types
has been completed. The small and compact MPB202
board used for this purpose is equipped with a socket
for program EPROMs.
;,-
MPB202
[4] OLMS40 SERIES EVALUATION
FEATURES
User·s application
circuit
Dedicated board
The dedicated boards indicated in the diagram
are required for a program evaluation of the
OLMS421 or OLMS422 microcontroller.
MPB421 (for OLMS421)
or
MPB422 (for OLMS422)
MPB400
or
MPB202
373
D
• EASE40 .-----------------------------------------------------
ASSEMBLER
ASM40 is a floppy disk based high-performance assembler which operates under CP/M and ISIS-II.
This assembler is used to translate source files generated on disk by using an editor (available on the market),
thereby generating object files (Intel HEX format), assembly list files and symbol files in the specified
devices.
LIST OF PSEUDO-INSTRUCTIONS
FEATURES
1. Free descriptive format source files
2. Enables description of up to nine types
arithmetic expressions in the source program
operand field
3. Symbol file generation capacity
4. Six types of pseudo-instructions available
5. A type setting pseudo-instruction enables checking
the limitation of basic instruction sets for each
OLMS40 microcontroller.
D
374
Pseudoinstruction
Function
EQU
Assignment of operand value to name.
ORG
Setting of program start address
END
Indication of end of program
NSE
Setting of 0 in the 4 lower order bits of
the assembler location counter, and
addition of 16. The NOP instruction is
assigned to blank areas where no
machine language instruction has been
assigned.
TYP
Indication of the OLMS40 series type
-----------------------------------------------------. EASE40 •
DEBUGGER
The EASE40 debugger can be used for effective debugging in both serial interface and bus interface
type systems.
FEATURES
EXAMPLE OF USE OF COMMANDS
1. Simple input format for debugging commands
entered from the console of the connected
development tool (personal computer)
2. Efficient loading/saving and display/change of
object codes
3. Real-time execution and step execution
4. Display/change of microcontroller contents
5. Use of assembler symbols permitted (only in
bus interface types)
LOAD~H~a:TEsT.HEX
LI
ST~:
FJ: LI STJ. 00 J
DEFINE~.START-JAC
REMOVE~.JOBJ"END2
URAM.o.o.o.TO.o.lFF
PC=789
URAM.o.I00-48.o.049A12
GO.o.URAM.a.FROM.o.12 3.o.T I LLAPC-7 A4.o.&1 0
GO.o.TILLAPF- ..
STEP.o.FROM.o.500.o.COUNTA30
VERIFY~O~A:SAMPL2.0BJ~UROM~400~TO~7FF
SAVE.o.:Fl:JOBl.002.o.0ATO.o.1FF
Command input format
Command name
LOAD
LOAD [ L::,. H/O] L::,. Path name [L::,. EXT]
LIST
LIST L::,. Pathname/OFF
DEFINE
DEFINE L::,. Symbol
REMOVE
REMOVE L::,. Symbol [. Symbol, ..... ]/SYMBOLS
Display
Keyword [L::,. address]
Change
Keyword = data· ref
Keyword L::,. addr = data [. data,data .... ,data]
ESET
RESET
EXIT
EXIT
GO
GO [L::,. URAM/UROM] [L::,. FROM L::,. addr·exp]
[L::,. TILLL::,.PC=Iaddr·exp[L::,. &n]][L::,.ASM]
GO [L::,. URAM/UROM] [L::,. FROM 6addr·exp]
[L::,. TILLL::,. Port·exp = data·exp] [L::,.ASM]
STEP
STEP [L::,. URAM/UROM][6FROM6addr·exp]
[L::,.COUNT L::,.n][ L::,.ASM]
@
@
VERIFY
VERIFY [L::,. H/O] L::,. Pathname [L::,. EXT] [L::,. URAM/UROM] [address]
SAVE
SAVE [L::,. H/O] L::,. Path name [L::,. URAM/UROM] [address]
L::,. •.•.•
Space,
[ ... ]..... May be omitted,
= expr
III
I ..... Slash denoting "or".
375
e EASE40ee--------------------------------------------------DEBUGGER COMMAND SAMPLES
DB400
«
DB400 »
OLMS40 SERIES ON LINE DEBUGGER
VERS 1 . 3
*LOAD A: SAMPLI . HEX
*IB
« INITIAL- BUFFER »
F E D C B A 9 8 7 6 5 4 3 2 1 0
0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RW=O RX=O RY=O RZ=O XCH=O A=O
ACC=O CY=O DPH=O. DPL=O PP=O
PF=O PG=O
*GO URAM FROM 7Al TILL PC=7CF &2
Y/N/E ?
Y
MODE: IB TO FB
PA=F PB=F PD=C PE=5
PC=07CF 74
PA=F PB=F PD=O PE=5
PC=07CF 74
*GO FROM 7Al TILL PF=9
Y/N/E ?
N
MODE: I B TO FB
MODE=NON TO FB
PA=F PB=F PD=F PE=F
PC=07CF 74
*FB
« FINAL BUFFER »
F E D C B A 9 8 7 6 5 4 3 2 1 0
0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7: 0 F
* 9 E 4 F 0 0 0 0 0 0 0 0
RW=F RX=4 RY=E RZ=9 XCH=* A=*
ACC=9 CY=l DPH=2 DPL=O PP=*
PA=F PB=F PD=F PE=F PF=9 PG=O
PK=B PH=2 CIN=O INT=l
*STEP FROM 7Al COUNT 6
PA=F PB=F PD=C PE=O
PC=07Al' 3700
PA=F PB=F PD=C PE=O
PC=0700 AC
PA=F PB=F PD=C PE=O
PC=0702 AD
PA=F PB=F PD=C PE=O
PC=0704 65
PA=F PB=F PD=C PE=O
PC=0705 26
PA=F PB=F PD=C PE=O
PC=0706 37A3
*EXIT
II
PF=O PG=O PK=B PI=A
PF=O PG=O PK=B PI=A
PF=9 PG=O PK=B PI=A
*
376
PF=9
PF=9
PF=9
PF=9
PF=9
PF=9
PG=O
PG=O
PG=O
PG=O
PG=O
PG=O
PK=B
PK=B
PK=B
PK=B
PK=B
PK=B
PI=A
PI=A
PI=A
PI=A
PI=A
PI=A
-----------------------------------------------------. EASE40 •
SELECTION OF MICROCONTROLLER AND EVALUATION BOARDS/SOFTWARE
Microcontroller
Evaluation board
Dedicated board
Serial interface type
r-;M;p;;:B4;;;01~W--.J-~
OLMS40
OLMS42
~ - - - ,MS47
Dedicated hardware
simulator
EVALUATION MICROCONTROLLERS
OLMS40
MSM5840
MPB400 board accessories
OLMS42
MSM5840
MPB400 board accessories
OLMS421 MSM5840
MPB421 board accessories
OLMS422 MSM5840
MPB422 board accessories
SOFTWARE
Serial interface type
FD40S·CP/M
Assembler/(serial)debugger CP/M single side single density 8-inch
Two (serial) monitor software EPROMs
FD40B·ISIS
Assembler/(bus) debugger ISIS-II single sided single density 8-inch
Two (bus) monitor software EPROMSs
PD40B·CP/M
Assembler/(bus) debugger CP/M single sided single density 8-inch
Two (bus) monitor software EPROMS
Bus interface type
377
• EASE40 ••----------------------------------------------------MPB400 Board
The MPB400 board is used for OLMS-40 Series
microcontroller program generation and evaluation.
With the MSM8085A used for control purposes,
several system configurations can be achieved in
combination with other boards and software.
Dimensions: 220 x 305 (mm)
MPB401 Board
The MPB401 board, used together with the MPB400
board, consists of interface circuit with the development
system and transfer speed converter unit.
Dimensions: 105 x 205 (mm)
80 x 115 (mm)
MPB202 Board
The MPB202 board is equipped with an evaluation
microcontroller and 4K bytes of program EPROM
sockets. This miniature size board is used effectively
in mounting evaluations when built into application
equipment for final testing of debugged programs.
Dimensions: 95 x 120 (mm)
378
-----------------------------------------------------'. EASE40 •
MPB421
The MPB421 board has been designed for OLMS-421
microcontroller program evaluation, and is used connected to the MPB400. This board is equipped with
LCD driver circuits and PLA EPROM sockets.
Dimensions: 145 x 180 (mm)
D
379
EASE6400 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the
OlMS-64 SERIES CMOS 4-Bit, 1-Chip Microcontroller
EASE6400 PROGRAM DEVELOPMENT SUPPORT
SYSTEM
The EASE6400 Program Development Support System has been specifically designed for-rapid and
efficient program development of Oki's OLMS-64 series of CMOS 4-bit, 1-chip microcontroller.
(Target chips: MSM6404, MSM6402, MSM6422, MSM6411, MSM6431, MSM6442 and MSM6408)
FEATURES
1. In-circuit emulation when connected to an
RS232C interface equipped a host computer
or to an input/output device such as a CRT
terminal and the EASE8 (option).
3. Six types of break conditions (for interruption
of. emulation) including execution address
and machine cycle counter.
4. EPROM writer (for 2732, 2732A, 2764) to
enable programming, transfer, and
verification of user program area contents.
5. User program debugging operations directed
by debug commands entered from the keyboard of the connected input/output device.
6. Program evaluation by use of dedicated evaluation chip (MSM6400E), thereby enabling
380
the same operations to be executed as when
the MSM6404 chip is used.
7. Built-in system diagnostic program.
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M®-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS® (ver2.11 or later)
(3) PC-DOS® (ver2.11 or later)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BDOS function
call 6 on condition that console device is
assigned to TTY:.
- - - - - - - - - - - - - - - - - - - - - - - - - - . EASE6400 •
SYSTEM CONFIGURATION
The EASE6400 Program Development Support
System consists of the EASE6400 Emulator (a
high performance program emulator which
includes the EASE Host Monitor, the EASE6400
Evaluation, and the host computer) and the
ASM6404 Assembler. With the EASE6400
Evaluation connected online to the host
computer equipped with an RS232C interface,
the system covers all operations from assembly
of the source program through program
evaluation and debugging.
• 7 bits, 2 stop bits, even parity
• 7 bits, 2 stop bits, odd parity (switchable)
• EASE
• ASM6400
EASE6400
Evaluation Kit
COMMUNICATION WITH HOST
COMPUTER
ICs used
• Communication interface MSM82C51A
• Driver/receiver SN75188N, SN75189N
Transmission format
• 110 to 9600 bps (switchable)
• 8 bits, 2 stop bits, non-parity
:8
!~I
B
Note: CP/M is a registered trademark of Digital
Research Inc. (U.S.A.)
EASE and ASM6404 for PC-DOS, MS-DOS are
optional softwares.
381
• EASE6400 • - - - - - - - - - - - - - - - - - - - - - - - - -
ASM6400ASSEMBLER
The ASM6400 is a floppy disk based high-performance assembler which operates on CP/M-80,
MS-DOS, or PC-DOS.
This assembler is used to translate source files generated on disk by using an editor (available on the
market), thereby generating object files (Intel HEX format), assemble list files, and cross-reference
list files in the specified devices.
FEATURES
1. Free descriptive format source files
2. Capacity to describe up to ten types of operators
in the source program operand column
3. Ability to specify the number of characters
per line and the number of lines per page in
assembly list files
4. Cross-reference list file generation capacity
5. 13 types of powerful pseudo-instructions available
6. Object codes where internal page jump instructions and all page jump instructions are assigned
automatically can be obtained by branch pseudoinstructions
7. Control of assembly list file outputs by LIST
or NLST pseudo-instruction
LIST OF PSEUDO-INSTRUCTIONS
Pseudoinstruction
TYP
Specifies a type of target chip
EQU
Assignment of operand value to name.
SET
Same as EQU pseudo-instruction, but
with redefinition capacity
ORG
Setting of program start address
END
Indication of end of program
B
382
Function
Automatic conversion to internal page or
all page jump instruction after checking
branch destination
DB
8-bit data or ASCII character definition
DS
Reserves memory area for specified
number of bytes
NSE
Setting of 0 in the 4 lower order bits of
the assembler location counter, and
addition of 16. The NOP instruction is
assigned to blank areas where no
machine language instruction has been
assigned.
DATE
Insertion of date in assemble list title
PAGE
Execution of assemble list page feed
TITL
Insertion of assemble list title
LIST
Designation of assemble list output
NLST
Inhibition of assemble list output
---------------------------------------------------eEASE6400e
EASE6400 EMULATOR
Consisting of a host computer and the EASE6400 Program Evaluation Kit, the EASE6400 Emulator
supports a wide range of development debugging operations efficiently and effectively. OlMS-64
application programs can be debugged without user application circuits just as easily as completed
systems.
a) User program execution
FEATURES
1. Real-time tracing function does not effect
execution time
The EASE6400 Evaluation Kit incorporates a
realtime trace area for 2048 machine cycles.
When the tracing for a particular user program
area address has been set, the address,
operation code, port, and probe status are traced
each time the specified address is executed.
2. Execution time measurement
The user program execution time can be measured by using the cycle counter on the
EASE6400 Evaluation Kit. (Max. 16.777,215 cycles)
This counter can also be used as a pass counter
to indicate the number of times a specified address is executed. And em ulation can be
stopped after a specified address has been executed a specified number of times.
3. Mass storage
With an 8192-bytes of static RAM area in the
EASE6400 Evaluation Kit for use as a user
program area, there is no problem with
inadequate memory area during debugging. And,
needless to say, user programs can be
loaded/saved from the host computer.
Furthermore, with an EPROM writer included on
this board, the user program area contents can
be written into EPROMs, and the EPROM
contents can be read out.
4. Ample break functions
The emulator can suspend (break) program execution by any of the following six break conditions.
a) Breakpoint break
Break upon execution of specified address. (Any
address may be specified.)
b) External break
Break by application of external break signal.
c) Halt/stop instruction break
Break by execution of HALT or STOP instruction.
d) Trace buffer full break
Break when overflow of trace area occurs.
e) Cycle counter overflow break
Break when overflow of cycle counter occurs.
f) Probe match break
Break when probe data matches set data.
5. Extensive range of debugging commands
In addition to display/updating of all register, port, and
RAM contents, the following commands enable
all debugging operations to be executed
efficiently.
Input format:
STP number of instructions, start address
Input of this command results in the specified
number of instructions in the user program being
executed from the specified address (start
address).
Input format:
G start address, break address (n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped
when the specified address (break address) is
executed n times.
Note: Program execution is suspended temporarily each
time the specified address is executed.
Input format:
G start address, break address RAM
(address-n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped if
the contents of the specified RAM address are n
when the specified address (break address) is
executed. In this case, too, program execution is
suspended temporarily whenever the specified
address is executed.
b) Use of floppy disks
Input format:
lOD filename
Input of this command enables the specified
file contents (user program) to be loaded into
the EASE6400 Evaluation Kit code memory
which serves as the OlMS-64 masked ROM
area.
Input format:
SAV filename start address, end address
Input of this command enables the contents of the
specified range of code memory to be saved at
the specified filename.
Input format:
DIAG2
Input of this command enables execution of commands within the specified file.
This execution can be suspended temporarily by
using the PAUSE command.
383
IJ
• EASE6400 • - - - - - - - - - - - - - - - - - - - - - - - - -
c) Instruction executed bit memory
The EASE6400 Emulator includes an instruction
executed bit memory which indicates which user
program addresses have been executed. Program flow can be determined by examination of
the contents of this memory.
6. Easy to remember command format
TheEASE6400Emuiator debugging commands con·
sist of command mnemonics followed by parameters
(address or mnemonic).
Command mnemonic configuration
a) First character
Denotes the function to be executed by the
emulator.
b) Second and following characters
Name of function to be executed by the
emulator- that is, MSM6400E evaluation
chip or EASE6400 Evaluation Kit register,
memory, or port name (abbreviation).
384
Example:
*DDMO,1F.J
II
ab
\j I
VI
cdef
a: denotes wait for command input from emulator
b: denotes display of contents of specified object
c: data memory (equivalent MSM6400E RAM area)
designation
d: start address of contents to be displayed
e: end address of contents to be displayed
f: carriage return denoting end of command input
- - - - - - - - - - - - - - - - - - - - - - - - - . EASE6400 •
EASE6400 EMULATOR MEMORY CONFIGURATION
The EASE6400 emulator memory area which can be used by the user ,is outlined in the following diagram. The
sections enclosed in boxes represent the register and memory areas which can be accessed from the host
computer keyboard, and which can be displayed/updated by debugging command.
PROGRAM
COUNTER
!PC!
CM
~
CODE
MEMORY
STACK
POINTER
8192x8
DATA
MEMORY
PORT 9
U
E]
~
o
c:=J
Pl
4
PORT 5
D
r=J U
PROBE
COMPARE
REGISTER
PROBE
MASK
~
~
TR
PORT 2
PORT 1
PORT 4
IE
SO
CE
I
PORT 3
P2
.
4
I. P3
I
4
I
PORT 7
PORT 8
D
r==J
EXECUTION
MODE
REGISTER
BREAK
CONTROL
REGISTER
BREAK
STATUS
REGISTER
~
U
M
T
8192 8192 8192 8192 8192
xl
xl
xl
xl
xl
i
I
PORT 6
TRACE
L
PORTO
IRQ
FLAG
REGISTER
.
BP
PORTA
U
I
PORTC
r:=J
EJ I J
CARRY
HL
REGISTER
OM
ACCUMULATOR
MEMORY
2048x66
61
BS
FB
IB
INITIAL
BUFFER
FINAL
BUFFER
139x8
210x8
CYCLE COUNTER ENABLE BIT MEMORY
SYNC OUTPUT BIT MEMORY
INSTRUCTION EXECUTED BIT MEMORY
TRACE ENABLE BIT MEMORY
BLK
BREAKPOINT BIT MEMORY
CYCLE COUNTER
TRACE POINTER
BLOCK
MEMORY
TP
8192xl
385
• EASE6400 • - - - - - - - - - - - - - - - - - - - - - - - - -
MAJOR MEMORY OPERATIONS
1. Code memory
The code memory is an 8192 x 8-bit RAM area
which corresponds to the OlMS-64 masked
ROM area where user programs are stored.
(The MSM6404 ROM capacity is 4000 bytes)
2. Data memory
The data memory is a 256 x 4-bit RAM area corresponding to the MSM6400E RAM area.
3. Instruction executed bit memory
This memory is an 8192 x 1-bit RAM area which has
addresses identical to the code memory. When a
code memory program is executed, the bits corresponding to the excuted addresses are set to "1". The
program flow can thus be determined by checking the
contents of this memory.
4. Break point bit memory
The break point bit memory is also an 8192 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", program execution is suspended immediately after the
code memory contents corresponding to that bit are
executed.
5. Trace enable bit memory
The trace enable bit memory is another 8192 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", port/
register contents, etc., are stored in the trace
memory when the code memory contents
corresponding to that bit are executed.
386
6. Sync ouput bit memory
The sync output bit memory is another 8192 x 1-bit
RAM area which has addresses identical to the code
memory. When the code memory contents are executed, the corresponding bits in the sync output
memory are checked, and if a "1" bit is found, an output sync signal (active lOW) is passed to the probe
terminal.
7. Cycle counter enable bit
The cycle counter enable bit memory is also another
8192 x 1·bit RAM area which has addresses identical to the code memory. When the code memory
contents are executed, the corresponding bits in the
cycle counter enable bit memory are checked,
and if a "1" bit is found, the cycle counter is
counted up in step with that machine cycle.
8. Probe comparison register/probe mask
The conditions for generating a break by input data
from the probe (probe match break) can be changed
by altering these two settings.
9. Initial/final buffers
These two memories are 210 x 8-bit RAM areas
used to store the initialized settings of the MSM6400E
evaluation chip or the MSM6400E status immediately
after a break when real·time emulation is executed.
10. Trace memory
The trace memory is a 2048 x 66-bit RAM area used
to store traced data.
The trace instruction is given by the trace enable bit.
---------------------------------------------------e EASE6400 e
LIST OF DEBUGGING COMMANDS
Load, save, and Verify Commands
LOD [dr : ] filename .J
SAV [dr:] filename [address, address].J
VER [dr :] filename [address, address].J
Load programs into code memory
Save code memory program
Verify file with code memory
EPROM Commands
PPR address, address [, address].J
TPR address, address [, address].J
VPR address, address [, address].J
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
Commands Used to Display/Change Internal Status of Evachip
PC
DPC
CPC address .J
Display Program Counter
Change Program Counter
SP
DSP.J
CSP data.J
Display Stack Pointer
Change Stack Pointer
AC
DAC.J
CACdata.J
Display Aoc
ChangeAcc
CY
DCY.J
CCYdata.J
Display Carry Flag
Change Carry Flag
HL
DHL.J
CHLdata .J
Display H-L Registers
Change H-L Registers
FR
DFR.J
CFRdata.J
Display Flag Register
Change Flag Register
PO~P8
DPn .J
CPn data.J
(n
(n
= 0, 1, 2, 3, ... 8)
= 0, 1,2,3, ... 8)
Display Port n
Change Port n
P9
DCMR .J
CCMRdata.J
Display Counter Mode Register
Change Counter-Mode Register
(port 9)
PA
DSMR.J
CSMRdata.J
Display Shift Mode Register
Change Shift Mode Register
(port A)
PB
DCFR
* Change CFR command is not permitted
Display Control Flag Register
(port B)
PC
DEIF .J
CEIFdata .J
Display Enable Interrupt Flag
Change Enable Interrupt Flag
(port C)
DIRQ
Display Interrupt Request Flag
(port D)
PO
MEl
* Change IRQ command is not permitted
DMEI.J
CME I data.J
Display Master Enable Interrupt Flag
Change Master Enable Interrupt Flag
D.J
Display all internal status
Data & Code Memory Display, Change, and Fill Commands
OM
DDM address [, address] .J
COM address +"
data data... .J
FDM address, address, data .J
Display Data Memory
Change Data Memory
Fill Data Memory
CM
DCM address [, address].J
CCM address .J
data data... .J
FCF address, address, data .J
Display Code Memory
Change Code Memory
Fill Code Memory
387
• EASE6400 . - - - - - - - - - - - - - - - - - - - - - - - - -
Attribute Memory Display, Enable, and Reset Commands
BP
DBP address [, address].)
EBP address [, address].)
RBP address [, address].)
Display Break Point Bits Memory
Enable Break Point Memory
Reset Break Point Bits Memory
TR
DTR address [, address].)
ETR address [, address].)
RTR address L address].)
Display Trace Enable Bits Memory
Enable Trace Enable Bits Memory
Reset Trace Enable Bits Memory
IE
DIE address [, address].)
RIE address [, address].)
Display Instruction Executed Bits Memory
Reset Instruction Executed Bits Memory
CE
DCE address [, address].)
ECE address [, address].)
RCE address [, address].)
Display Cycle Counter Enable Bits Memory
Enable Cycle Counter Enable Bfts Memory
Reset Cycle Counter Enable Bits Memory
SO
DSO address [, address].)
ESO address [, address].)
RSO address [, address].)
Display Sync Out Enable Bits Memory
Enable Sync Out Enable Bits Memory
Reset Sync Out Enable Bits Memory
Trace Memory Display Commands
TM
DTM
DTl
Display Trace Memory
Display Trace List
Other Hardware Display and Change Commands
DCC.)
CCC number .)
Display Cycle Counter
Change Cycle Counter
DBC.)
SBC [[±] mnemonic, ... ]
Display Break Condition Register
Set Break Condition Register
mnemonic means one of following key words
here.
BB ........ Break at Break Point
XB ........ External Break
CO ........ Cycle Counter Over Flow
TF ......... Trace Memory Full
PM ........ Probe Match
HS ........ HALT/STOP Instruction Executed
BS
DBS')
Display Break Status Register
PM
DPM.)
CPM data.)
Display Probe Mask Register
Change Probe Mask Register
CR
DCR')
CCRdata.)
Display Probe Compare Register
Change Probe Compare Register
DEM
CEM mode-ref .)
Display Execution Mode Register
Change Execution Mode Register
mode-ref means one of following keywords
here.
IF .......... IB
TOFB
IN ......... IB
TO NON
NN ........ NON TO NON
NF ........ NON TO FB
FF ......... FB TOFB
DBl address [, address].)
SPB address [, address].)
SDB address L address].)
Display Block Memory
Set Block Memory into Program Block
Set Block Memory into Data Block
BANK 1 or 2
Set Attribute Memory Bank Register
CC
BC
EM
BlK
BANK
388
-------------------------------------------------eEASE6400e
Initial Buffer & Final Buffer
DIB..J
DFB..J
CI key-word data .;
IB
FB
CIOM address .; data data... ..J
CF key-word data .;
CFDM address
data data... ';
FIDM address, address, data.;
FFDM address, address, data .;
Display Initial Buffer
Display Final Buffer
Change elements of Initial Buffer
key-word ... AC, HL, FR, SMR, CMR, MEl,
ElF, CY, Pn (n=O, 1, 3, 4, ... , 8)
Change Initial Buffer Data Memory
Change elements of Final Buffer
key-word ... AC, HL, FR, SMR, CMR, MEl,
ElF, CY, Pn (n=O, 1,3,4, ... , 8)
Change Final Buffer Data Memory
Fillnitial Buffer Data Memory
Fill Final Buffer Data Memory
Assemble & Disassemble Commands
ASM address ..J mnemonic ... .;
DASM address [, address]';
Assemble to Code Memory
Disassemble to Console
Emulation Commands
G [start-address) [, break-parameter, ...... ).;
GD [start-address] [, break-parameter, ...... )..J
STP [number) [, address)';
Go (Start Real Time Emulation)
Go Direct (Start Real Time Emulation)
break-parameter format is shown below
1) address
2) asddress (n)
3) addres (n) & address (m)
4) add res RAM (address - data)
1 < n, m < 65535
Start Step Execution
Other Commands
@ [-n]';
HELP..J
EXIT .;
RES';
RESE..J
SIO H or F';
DEV';
ST mnemonic';
FDD [dr ... drl .;
DIR [dr:]';
(n = 1 , 2, ..... , 9) Command - Repeat
Display Help File (EASE 64, HLP
Exit to CP/M
Reset EASE 6400 system
Reset Eva - chip (MSM 6400E)
Set I/O Mode
CH2 port Output Control
Family Set
Flopy Disk Unit Set
Display file directory
389
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the
MSM6502 CMOS 4-Bit, 1-Chip Microcontroller
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
The EASE6502 Program Development Support System has been specifically designed for rapid and efficient
program development of Oki's MSM6502 CMOS 4-bit, 1-chip microcontroller.
o
FEATURES
SYSTEM CONFIGURATION
1. Connecting the MPB6502 Evaluation Board
to a host computer or to an I/O terminal such
as a CRT terminal includes an RS232C
interface circuit. All debugging operations
can be entered from the console keyboard.
2. Executes user programs with the trace in real
time or in single step mode.
3. Mass storage user program area (4K bytes).
4. Six types of break conditions, including
execution address and machine cycle
counter.
5. EPROM programmer (for 2716, 2732, 2732A) to
enable programming, transfer, and verifing with
user program area contents.
6. The same operation as the MSM6502,
because OKi designed the original evaluation
chip (MSM6502E).
7. Built-in system diagnostic program.
The EASE6502 Program Development Support
System consists of the EASE6502 Emulator (a
high performance program emulator which
includes the EASE65 Host Monitor, the
M PB6502 Evaluation Board, and the host
computer) and the ASM6502 Assembler. With
the MPB6502 Evaluation Board connected
online to the host computer equipped with an
RS232C interface, the system covers all
operations from assembly of the source program
through to program evaluation and debugging.
User's application
circuit
•
•
EASE65
ASM6502
FDD
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M®-80 (ver 2.0 or later)
memory capaCity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS® (ver 2.11 or later)
(3) PC-DOS® (ver 2.11 or later)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BDOS function
call 6 on condition that console device is
assigned to TTY:.
COMMUNICATION WITH HOST
COMPUTER
ICs used
• Communication interface MSM82C51A
• Driver/receiver SN75188N, SN75189N
Transmission format
• 110 to 9600 bps (selectable)
• 8 bits, 2 stop bits, non-parity
7 bits, 2 stop bits, even parity
7 bits, 2 stop bits, odd parity (selectable)
390
MPB66Q2
Evaluation Board
:8
I~I
+5V +12V -12V
B
(4.5A) (O.2A) (O.2A)
Note: CP1M is the registered trademark of Digital Research
Inc. (U.S.A.)
EASE65 and ASM6502 for MS-DOS, PC-DOS
are optional softwares.
---------------------------------------------------.. EASE6502 •
ASM6502 ASSEMBLER
The ASM6502 is a floppy disk based high-performance assembler.
This assembler is used to translate source files generated on disk by using an editor (available on the
market), thereby generating object files (intel HEX format), assembly list files, and cross-reference
list files on the specified devices.
FEATURES
LIST OF PSEUDO-INSTRUCTIONS
1. Free descriptive format source files
2. Capacity to describe up to ten types of arithmetic
in the source program operand field
3. Ability to specify the number of characters per line
and the number of lines per page in assembly
list files
4. Cross-reference list file generation capacity
5. 13 types of powerful pseudo-instructions available
6. Object codes where all page jump instructions and
inter-page jump instructions are assigned
automatically can be obtained by branch pseudoinstructions
7. Control of assemble list file outputs by LIST or
NLST pseudo-instruction
Pseudoinstruction
Function
EQU
Assign the operand value to the name.
SET
Same as EQU pseudo-instruction, but
with redefinition capacity
ORG
Define assembler location counter.
END
Terminte assembly
B
Automatic conversion to all-page or
inter-page jump instruction after checking branch destination
DB
8-bit data or ASCII character string
definition
DS
Reserve n bytes area of uninitialized
storage
NSE
Setting of 0 in the 4 lower order bits of
the assembler location counter, and
addition of 16. The NOP instruction is
assigned to blank areas where no
machine language instruction has been
assigned.
DATE
Insertion of date in assemble list title
PAGE
Execute page eject
TITL
Insert assemble list title
LIST
Turn on assemble list output
NLST
Turn off assemble list output
391
11
• EASE6502 .-------------------------------------------------
EASE6502 EMULATOR
Consisting of a host computer and the MPB6502 Program Evaluation Board, the EAS.E6502 Emulator
supports a wide range of development debugging opera~ion~ effi?ien.tly.and effectl.vely. MSM6502
application programs can be debugged without user application circuits Just as easily as completed
systems.
FEATURES
1. Real-time tracing function does not effect
execution time
The MPB6502 Evaluation Board incorporates a realtime trace area for 2048 machine cycles. When tracing for a particular user program area address has
been set, the port, HL register, and MEl flag status
are traced each time the specified address is executed.
2. Execution time measurement
The user program execution time can be measured
by using the cycle counter on the MPB6502 Evaluation Board. (Max. 16,777,215 cycles)
This counter can also be used as a pass counter
to indicate the number of times a specified
address is executed. Emulation can be stopped
after a specified address has been executed a
specified number of times.
3. Mass storage user program area
With a 4096-byte static RAM area in the
MPB6502 Evaluation Board for use as a user
program area, there is no problem with
inadequate memory area during debugging. And,
needless to say, user programs can be
loaded/saved from the host computer.
Furthermore, with an EPROM programmer
included on this board, the user program area
contents can be written into EPROMs, and the
EPROM contents can be read out.
4. Ample break functions
The emulator can suspend (break) program execution by any of the following six brteak conditions.
a) Breakpoint break
Break upon execution of specified address. (Any
address may be specified.)
b) External break
Break by application of external break signal.
c) Halt instruction break
Break by execution of HALT instruction.
d) Trace buffer full break
Break when overflow of trace area occurs.
e) Cycle counter overflow break
Break when overflow of cycle counter occurs.
t) Probe match break
Break when probe data matches set data.
392
5. Extensive range of debugging commands
In addition to display/updating of all register, port, and
RAM contents, the following commands enable all
debugging operations to be executed efficiently.
a) User program execution
Input format:
STP number of instructions, start address
Input of this command results in the specified
number of instructions in the user program being
executed from the specified address (start
address).
And if the terminal to be used to display the contents has been specified by SDF command at this
time, the display can be put into an easy to read
format.
Input format:
G start address, break address (n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped
when the specified address (break address) is
executed n times.
Note: Program execution is suspended temporarily each
time the specified address is executed.
Input format:
G start address, break address RAM
(address-n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped if
the contents of the specified RAM address are n
when the specified address (break address) is
executed. In this case, too, program execution is
suspended temporarily whenever the specified
address is executed.
_________________________________________________ • EASE6502 •
b) Use of floppy disks
Input format:
LaD filename
Input of this command enables the specified file
contents (user program) to be loaded into the
MPB6502 Evaluation Board code memory which
serves as the MSM6502 masked ROM area.
Input format:
SAV filename start address, end address
Input of this command enables the contents of the
specified range of code memory to be saved at
the specified filename.
Example:
*DDM
0,
1F';
II \J I eV If
abc d
a: denotes wait for command input from emulator
b: denotes display of contents of specified registter/
memory/board
c: data memory (equivalent MSM6502 RAM area)
designation
d: start address of contents to be displayed
e: end address of contents to be displayed
f: carriage return denoting end of command input
Input format:
DIAG filename
Input of this command enables execution of commands within the specified file automatically.
This execution can be suspended temporarily by
using the PAUSE command.
Input format:
LIST filename
NLiST
If the list command is entered, the emulator creat
the CP/M file and write into it the any characters
which are output to the console till entering the
NLST command.
D
c) Instruction executed bit memory
The
EASE6502
Emulator
includes
an
instruction executed bit memory which indicates
which user program addresses have been executed. Program flow can be known by examination of the contents of this memory.
6. Easy to remember command format
The MPB6502 Emulator debugging commands consist of command mnemonics followed by parameters
(address or mnemonic).
Command mnemonic configuration
a) First character
Stand for the emulator function (display/update)
b) Second and following characters
Represent one of the MPB6502 Evaluation Board
or the MSM6502E evaluation chip element (register, memory or port name).
393
• EASE6502 .,---------------------------------------------------
EASE6502 EMULATOR MEMORY CONFIGURATION
The EASE6502 emulator memory area which can be used by the user is outlined in the following diagram. The
sections enclosed in boxes represent the register and memory areas which can be accessed from the host
computer keyboard, and which can be displayed/updated by debugging command.
INSTRUCTION EXECUTED BIT MEMORY
SYNC OUTPUT BIT MEMORY
TRACE ENABLE BIT MEMORY
CYCLE COUNTER ENABLE BIT MEMORY
BREAKPOINT BIT MEMORY
VM
CM
VERIFY
MEMORY
CODE
MEMORY
TM
4096x8
BTl
PRE
S C
0 E
TRACE MEMORY
2048x66
4096x8
TRACE POINTER
4096 x 5
DM
SG
DATA
MEMORY
SEGMENT
DATA
MEMORY
128x4
Hl
ACCUMULATOR
REGISTER
~
E]
E]
PORTO
PORT 1
PORT 2
TP
I
STACK
POINTER
CC
INSTRUCTION
DATA
~
U
EJ
E] EJ E] EJ
CARRY
MEl FLAG
INDEX
REGISTER
EJ
~
~
U
PROBE
COMPARE
REGISTER
E]
IB
INITIAL
BUFFER
139x8
394
PORT 4
PORT 3
EMULATION
MODE
~
PROBE
MASK
EXTERNAL
PROBE
BREAK
CONTROL
REGISTER
~
E]
~
FB
FINAL
BUFFER
139x8
111
CYCLE COUNTER
208x8
PROGRAM
COUNTER
I
BREAK
STATUS
REGISTER
~
BlK
BLOCK
MEMORY
4096 x 1
PORT 5
241
- - - - - - - - - - - - - - - - - - - - - - - - - ' . EASE6502 •
MAJOR MEMORY OPERATIONS
1. Code memory
9. Probe comparl register/probe mask
The code memory is an 4096 x 8-bit RAM area
which corresponds to the MSM6502 masked ROM
area where user programs are stored.
(The MSM6502 ROM capacity is 2000 bytes)
The conditions for generating break by input data
from the probe (probe match break) can be changed
by altering these two settings.
2. Data memory
The data memory is a 128 x 4-bit RAM area corresponding to the MSM6502 masked RAM area.
3. Verify memory
The verify memory is a RAM area with addresses
identical to the code memory. When a user program
is loaded into the code memory identical contents are
also set in this memory.
Comparrison of this memory with the code memory
enables the operator to determine what sections of
the user program have been changed after loading.
4. Instruction executed bit memory
This memory is an 4096 x 1-bit RAM area which has
addresses identical to the code memory. When a
code memory program is executed, the bits corresponding to the executed addresses are set to "1".
The program flow can thus be known by checking the
contents of this memory.
10. Segment data memory
The segment data memory is a 208 x 8-bit RAM
area with coordinates 0 thru 7 on the vertical axis and
A thru Z on the horizontal axis. This memory is used
to display the status of each bit of the MSM6502 RAM
liquid crystal display area at the specified coordinate
and by the specified character.
Displaying the status of this memory provides an
image of the liquid crystal display status.
11. Initiallfinal buffers
These two memories are 139 x 8-bit RAM areas
used to store the initialized settings of the MSM6502E
evaluation chip or the MSM6502E status immediately
after a break when real-time emulation is executed.
12. Trace memory
The trace memory is a 2048 x 66-bit RAM area used
to store traced data.
The trace instruction is given by the trace enable bit.
5. Break point bit memory
The break point bit memory is also an 4096 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", program execution is suspended immediately after the
code memory contents corresponding to that bit are
executed.
D
6. Trace enable bit memory
The trace enable bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1 ", port!
register contents, etc., are stored in the trace
memory when the code memory contents corresponding to that bit are executed.
7. Sync ouput bit memory
The sync output bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the code
memory. When the code memory contents are executed, the corresponding bits in the sync output
memory are checked, and if a "1" bit is found, an output sync signal (active LOW) is passed to the probe
terminal.
8. Cycle counter enable bit
The cycle counter enable bit memory is also another
4096 x 1-bit RAM area which has addresses identical to the code memory. When the code memory
contents are executed, the corresponding bits in the
cycle counter enable bit memory are checked, and if
a "1" bit is found, the cycle counter is counted up in
step with that machine cycle.
395
• EASE6502 .---------------------------------------------------
DEBUGGING COMMAND TABLE
Load, Save, and Verify Commands
1.
2.
3.
4.
5.
6.
LOD
SAV
VER
LSG
SSG
VCM
1
[dr: filename
[dr: filename [address, address]
[dr:] filename [adress, address]
[dr:] filename [address, address]
[dr:] filename
address [, address]
Load Pr09,ram into Code Memory
Save Co e Memory Program
Venlty File with Code Memory
Load Segment data
Save Segment data
Verify Code Memory with Verify Memory
EPROM Commands
1. PPR address, address [, address]
2. TPR address, address
3. VPR address, address [, address]
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
Display Commands
o
1. 0
2.DAC
3.DHL
4.DCY
5.DSP
6. OLD
7. DEI
8. DPn
9.DPC
10. DCC
11. OCR
12. DPM
13. DBC
14. DBS
15. OEM
16.DIB
17. DFB
18. DSG
19. DBP address [, address)
20.DCE address [, address)
21. DSO address [, address)
22. DIE address [, address)
23. DTR address [, address)
24. DDM address [, address)
25. DCM address [, address)
26. DVM address [, address)
27. DTM tp-address, line-number
28. DTL -number, line-number
All Register, Flag, Port
Ace Register
HLR~ister
Carry lag
Stack Pointer
LCD Driver ON/OFF status (Port 4-0 bit)
Enable Interupt Flag (MEl, TBC EI, ext. INT EI)
Port N (n=O, 1,2,3,4)
Program Counter
Cycle Counter
Probe Compare Register
Probe Mask Register
Break Condition
Break Status
Emulation Mode
Initial buffer & Final buffer
Final buffer & Initial buffer
Segment Data Status
Break Point Bit Memory
Cycle Counter Enable Bit Memory
Sync Output Enable Bit Memory
Instruction Executed Bit Memory
Trace Enable Bit Memory
Data Memory (M6502E Intemal RAM)
Code Memory
Verify Memory
Trace Memory
Trace List
Change Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
396
CAC data
CHL data
CCY Oorl
CSP data
CLD Oorl
CEI [data)
CIR data
CPn data
CPC address
CCC (+or-) data
CCR data
CPM data
CBZ Oorl
CEM mode
CI key-word data
CF key-word data
CSG
CCM address
COm address
BANK 0 or 1
Ace Register
HL Register
Carry Flag
Stack Pointer
LCD Driver ON/OFF Status
Enable Interrupt Flag
Index Register
Port n (n=O, 1, 3, 4, 5)
Program Counter
Cycle Counter
probe CQmpare Register
Probe Mask Register
Buzzer Output Select Hard or Soft
Emulation Mode
*mode*
IF
IN
NN
NF
FN
Initial Buffer
Final Buffer
s~mentdata
IB
IB
NON
NON
FB
to FB
to
to
to
to
NON
NON
FB
NON
Co eMemory
Data Memory (M6502E Internal RAM)
Attribute Memory Bank
- - - - - - - - - - - - - - - - - - - - - - - - - - . EASE6502 •
Enable Commands
1.
2.
3.
4.
EBP
ECE
ESO
ETR
address
address
address
address
[, address]
[, address]
[, address]
[, address]
Break Point Bit Memory
Cycle Counter Enable Bit Memory
Sync Output Enable Bit Memory
Trace Enable Bit Memory
[, address]
[, address]
[, address]
[, address]
[, address]
Break Point Bit Memory
Cycle Counter Enable Bit Memory
Instruction Executed Bit Memory
Sync Output Enable Bit
Trace Enable Memory
M6502E Eva-chip
MPB6502 Board
Reset Commands
1. RBP
2.
3.
4.
5.
6.
7.
RCE
RIE
RSO
RTR
RES
RES
address
address
address
address
address
E
Fill Commands
1.
2.
3.
4.
FCM
FDM
FIDM
FFDM
address, address, data
address, address, data
address, address, data
address, address, data
Code Memory
Data Memory
Initial Data Memory
Final Data Memory
Emulation Commands
1. G
2. GD
[st-address] [, break-parameter, ----]
Begin Emulation
[st-address] [, break-parameter, ___ oj
Begin Emulation
If the optional st-address is given, emulator will begin emulation from st-address. And if optional breakparameter is given, emulation will break on the first break-parameter to be satisfied.
Break-parameter =
=
=
=
3. STP
[number] [, st-address]
break-address
break-address (pass count)
break-address (pass count) & break-address (pass count)
break-address RAM (RAM address-data)
Single Step
Other Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
ASM
DASM
LIST
NLST
DBLK
SPB
SDB
SIO
EXIT
PAUSE
DIAGI
DIAG
@ [-n]
HELP
SBC
16. SDF
address
address [, address]
[dr :] filename
Assemble to Code Memory
Disassemble to Console
List Console Output into Disk File
End listing
address [, address]
Display Block Memory
address [, address]
Set Program Block
addres [, address]
Set DB Block
ForH
Set Emulator to I/O terminal mode
Retum to CP/M
Stop Command File Execution
Start Sell Check Program
[dr :] filename
Execute Command File
Repeat Command
Display HELP File
(+ or -) mnemonic [, (+ or -) mnemonic. ---]
Set/Reset Break Condition Register
• mnemonic·
BB
Break when Break Point Reached
XB
Extemal Break
CO
Break on Cycle Counter Overflow
TF
Break when Trace Buffer Full
PM
Break on Probe Match
HT
Break on HALT Instruction
(+ or -) mnemonic [, (+ or -) mnemonic, ---]
SeVReset Dump Format
1. DEL
2.
3.
4.
5.
6.
7.
8.
Cntrl/C
Cntri/P
Cntrl/Q
Cntrl/S
Cntrl/R
ESC
@ [-n]
o
Delete the last character entered
Return to CP/M
Copy all subsequent console output to the currently assigned list device
Continue normal dispaly
Stop display
Echoe current input line
Abort any command inprogress
Repeat the command
.
Note: The MSM6502 RAM area corresponds to the EASE6502 Emulator data memory, and the mask ROM corresponds to
the code memory.
397
• EASE6502 .---------------------------------------------------
SAMPLES
A>ERSE65
«
Sep,
Pl'"eiiminary
EASE65
3,1983
Now,
OKl
start
electric
up
lI1.0
ind.co.,ltd
I1P86502
board.
HARD WARE SELF CHECK
[ NORMAL END J
«
I1PB6502 EMULATOR
PRELIMINARY lIt.5
COPYRIGHT OKI ELECTRIC IND. CO.
LTD.
1984
ACTIVE BREAK CONDITION ---> BREAK POINT BREAK
HALT
** NOW DEvICE NO.
( KEY
o
A,B **
~
IN OTHER DEVICE NO.
[PRESENTED DEVICE
* DIAG INIT1
.. ; INITIALIZATION
INSTRUCTION BREAK
]
NO.~A:B:J
START
* FCM *
* LSG PIC.DAT
SGRAM SET-UP COMPLETED
.. LOD RAMSEr
LOAD COMPLETED
*
LIST CRT.LST
..
j
NEXT ADORESS=0020
NOW INITIALIZATION END AND LIST START
DIAG COMMAND END
* GD O,1F
BANK: 1
EXECUTION MODE
(RESET TRACE POINTERI
EMULATION GO **
NON TO NON
PARAMETER=OOlF(
0)
ADDRESS BREAK
[BREAK
NEXT
PC~OIF
[NEXT TRACE
PC~O'OJ
POINTER~17J
* DDH 0,3
5 5 5 2
LOC~03-00
.. DTI1
4,3
LAI
LMA
PORT(O-2)~FFO
CY~O
MEI~O
XP~FF
TP",
LOC~013
82
B4
PORT(0-2)~FFO
HL~OO
CY~O
MEI~O
XP~FF
TP~5
LOC=014
11
INl
PORT(O-2)=FFO
HL=OO
CV=O
I1EI"'O
XP"'FF
TP=6
LOC~012
HL~OO
.. DIE 0,20
*
lOC=OOO
110000000000
LOC~020
0
DASH
1111
1111
LOC~010
6AOO
LOC=012
82
LAI
LOC~013
B4
LMA
LOC~OOI
5F
DO
LOC~002
* NLST
* EXIT
398
1111
DI
JCP
010
DB
00 00 00 00 00 00 00 00
LHLI 00
LOC~OOO
A>
0000
1101
0,13
2
00 00 00 00 00 00
-------------------------------------------------. EASE6502 •
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the MSM6502 CMOS 4-81T 1-CHIP MICROCONTROLLER
Category
Hardware
Software
Manual
Accessories
Model
MPB6502
EASE65
ASM6502
Title
4-bit 1-chip microcontroller evaluation board
Floppy disk based host monitor*
Floppy disk assembler*
TM-6502
EASE6502 Development Support System - User's Manual
TCU-6502
User application circuit connection cables
TCS-1
Host CP/M® computer connecting cables (for if800 model 10/20/30)
TCP-1
Power supply cables (+5V, 4.5A) (+12V, 0.2A) (-12V, 0.2A)
TCX-1
External probe cables
TCC-1
Board connecting cables
* Available under following operating system
• CP/M-80 (ver 2.0 or later)
• MS-DOS (ver2.11 or later)
• PC-DOS (ver2.11 or later)
OPTIONS
Option name
MPB6502 EVA
Board
Remarks
A simplified evaluation board consisting of the MSM6502E plus EPROM sockets,
and designed for the MSM6502. Programs are evaluated by inserting the EPROM
where the user program is stored into an EPROM socket.
Dimensions: 160 x 127 (mm)
o
399
EASE OOC49 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for
MSM80C48RS/MSM80C49RS/MSM80C50RS CMOS 8-Bit Microcontrollers
EASE80C49 PROGRAM DEVELOPMENT SUPPORT
SYSTEM
The EASE80C49 Program Development Support System has been specifically designed for rapid and
efficient program development of Oki's MSM80C48RS, MSM80C49RS and MSM80C50RS CMOS
8-bit, 1-chip microcontrollers.
o
FEATURES
SYSTEM CONFIGURATION
1. In-circuit emulation when connected to an RS232C
interface equipment host computer or to an
input/output device such as a CRT terminal.
2. 4K byte user program area available for code
transfer to/from floppy disk, collation/updating of
area contents, and continuous/step execution.
3. Eight types of break conditions (for interruption
of emulation) including execution address and
machine cycle counter.
4. EPROM programmer (for 2716, 2732, 2732A) to
enable writing, transfer, and comparison of user
program area contents.
5. User program debugging operations directed by
debug commands entered from the keyboard of
the connected inpuUoutput device.
6. Built-in system diagnostic program.
The EASE80C49 Program Development Support
System consists of the EASE80C49 Emulator (a high
performance program emulator which includes the
EASE49 Host Monitor, the MPB800 Evaluation
Board, and the host computer) and the ASM-49
Assembler.
With the MPB800 Evaluation Board connected
online to the host CP/M computer (such as an
if800) equippped with an RS232C interface, the
system covers all operations from assembly of
the source program through to program
evaluation and debugging.
• EASE49
• ASM49
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M@-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-OOS® (ver 2.11 or later)
(3) PC-OOS® (ver 2.11 or later)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BOOS function
call 6 on condition that console device is
assigned to TTY:.
MPB800
Evaluation Board
IC§JI
+5V +12V -12V
(4.5A) (O.2A) (O.2A)
MPB800 EVALUATION BOARD DATA
TRANSFER SYSTEM
ICs used
• Communication interface MSM82C51A
• Driver/receiver
SN75188N,
SN75189N
Transmission format
• 110 to 9600 bps (Switchable)
• 8 bits, 2 stop bits, non-parity
400
:8
Note:
o
CP/M is a registered trademark of Digital
Research Inc. (U.S.A.)
When the EASE80C49 is used on the
MSM80C50, the MSM80C39 evaluation chip
on the emulation board is to be replaced by
MSM80C40.
EASE49 and ASM-49 for PC-DOS, MS-DOS are
optional softwares.
--------------------------------------------------. EASE80C49 •
ASM-49 CROSS-ASSEMBLER
The ASM-49 is a floppy disk based high-performance assembler.
It translates source files generated on disk by using an editor, thereby generating object code files and
assembly list files.
LIST OF PSEUDO-INSTRUCTIONS
FEATURES
1. Free descriptive format source files
2. 35 types of powerful pseudo-instructions
available for assembler control purposes
3. Macro definition ability
4. 11 types of pseudo-instructions to enable
conditional assembly
5. Assembly repetition processing (loop processing)
6. Determination of variable values in the
source program by input from a console
during assembly, and linking to existing
source programs. (INPUT and LINK pseudoinstructions)
7. Capacity to describe up to 13 types of operators in
the source program operand column
Pseudo-instructions
Function
ORG Expression
Location counter value defined
as nnn. (Expression=nnn)
DS Expression
Reserves memory area for n
number of bytes. The first and
last byte values may be
changed.
Use ORG $+n to prevent
change of values.
(Expression = n)
DW Expression
16-bit data definition
DB Expression
a-bit data or ASCII character
string definition
EQU
Assignment of operand value
to name
SET
Same as EQU pseudoinstruction, but with
redefinition capacity
IF Expression
Evaluate expression value,
and skip to next ENDIF, END
or EDF (end of file) if result is
zero. Assemble the next
instruction if result is not zero.
NIF Expression
Evaluate expression value,
and skip to next ENDIF, END
or EDF (end offile) if result is
not zero.
END Expression
End of assembly
MACRO
Macro definition
GO TO Label
Branch the subsequent
assembly to the destination
indicated in the label
REPT Expression
Denotes repetition block.
Assembly is executed the
number of repetitions indicated
by the expression value.
REPND
Definition of end of repetition
block
LIST
Pass option invalidated, and
output of full assembly list
NOLST
Inhibition of assembly list
outputs apart from error
messages
TITLE
Allocation of title at head of
assembly list page
401
e EASE80C49 e------------------------EASE80C49 EMULATOR
Consisting of a host computer and the MPB800 Program Evaluation Board, the EASE80C49 Emulator
supports a wide range of development debugging operations efficiently and effectively.
MSM80C49RS and MSM80C50RS application programs can be debugged without user application
circuits just as easily as completed systems.
FEATURES
1. Real-time tracing function does not effect
execution time
The MPB800 Evaluation Board incorporates a
real-time trace area for 1024 machine cycles.
When tracing for a particular user program area
address has been set, the port, program counter,
and probe data status are traced each time the
specified address is executed.
2. Execution time measurement
The user program execution time can be measured
by using the cycle counter on the MPB800 Evaluation Board. (Max. 16,777, 215 cycles)
This counter can also be used as a pass counter
to indicate the number of times a specified address
is executed.
u
3. 4096-byte user program area
A 4096-byte static RAM area in the MPB800
Evaluation Board is used as a user program area,
and user programs can be loaded/saved from the
host computer into this area. Furthermore,
with an EPROM programmer included on this
board the user program area contents can be
written into EPROMs, and EPROM contents
can be read.
4. Ample break functions
The emulator can suspend (break) program
execution by any of the following eight break
conditions.
a) BB (Breakpoint Break)
Break upon execution of specified address.
(Any address may be specified.)
b) EB (External Break)
Break by application of external break signal.
c) CO (Cycle counter Overflow break)
Break when overflow of cycle counter occurs.
d) TF (Trace Full break)
Break when 4097 tracings executed.
e) PM (Probe Match break)
Break when probe data matches set data
f) IF (Instruction Fetch)
Break when machine code is fetched.
g) MX (MovX)
Break by MOVX instruction.
h) ER (Error code)
Break if incorrect machine code is fetched.
402
5. Extensi'!e range of debugging commands
In addition to display/updating of all register, port,
and RAM contents, the following commands
enable all debugging operations to be executed
efficiently.
a) User program execution
Input format:
STP number of instructions, start address
Input of this command results in the specified
number of instructions in the user program
being executed from the specified address
(start address).
Input format:
G [, start address]
Input of this command results in the user program being executed from the specified address
(start address). If no start address is specified,
execution is started from the address indicated
by the program counter at that time.
b) Use of floppy disks
Input format:
LOA filename
Input of this command enables the specified file
contents (user program) to be loaded into the
MPB800 Evaluation Board code memory which
serves as the MSM80C49RS/MSM80C50RS
masked ROM area.
The same contents can also be loaded into the
utility buffer by using the LDU command.
Input format:
SAY, start address, end address, filename
Input of this command enables the contents of
the specified range of code memory to be saved
at the specified filename.
c) Instruction excuted bit memory
The EASE80C49 Emulator includes an instruction executed bit memory which indicates which
user program addresses have been executed.
Program flow can be determined by examination
of the contents of this memory.
------------------------------------------------eEASE80C4ge
MAJOR MEMORY OPERATIONS
6. Easy to remember command format
The MPB800 Emulator debugging commands
consist of command mnemonics followed by
parameters (address or mnemonic).
Command mnemonic configuration
a) First character
Denotes the function to be executed by the
emulator.
b) Second and following characters
Name of function to be executed by the
emulator-that is, MSM80C39 microcomputer or
MPB800 Evaluation Board register, memory, or
port name (abbreviation).
Example:
*DDM 0, 1F ~
II \J I V I
ab cde f
a: denotes wait for command input from emulator
b: denotes display of contents of specified registerl
memory/board
c: data memory (equivalent MSM80C49RS/
MSM80C50RS RAM area) designation
d: start address of contents to be displayed
e: end address of contents to be displayed
f : carriage return denoting end of command input
1. Code memory
The code memory is an 4096 x 8-bit RAM area
which corresponds to the MSM80C49RS/
MSM80C50RS program area (masked ROM)
where user progrSlms are stored.
2. Data memory
The data memory is a 128 x 8-bit RAM area
corresponding to the data memory (RAM) on the
MSM80C49RS chip. The data memory area for
MSM80C50RS is 256 x 8-bits.
3. Utility buffer
The utility buffer is a 4096 x 8-bit RAM area used
in temporary saving from the emulator when a
load, save, or transfer command is entered.
4. Break pOint bit memory
The break point bit memory is also an 4096 x 1-bit
RAM area which has addresses identical to the
code memory. If a particular bit in this memory is
"1", program execution is suspended immediately
after the code memory contents corresponding to
that bit are executed.
5. Trace enable bit memory
The trace enable bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the
code memory. If a particular bit in this memory is
"1", port and probe data is stored in the trace
memory when the code memory contents corresponding to that bit are executed.
6. Sync output bit memory
The sync output bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the
code memory. When the code memory contents
are executed, the corresponding bits in the sync
output memory are checked, and if a "1" bit is
found, an output sync signal (active LOW) is
passed to the probe terminal.
7. Cycle counter enable bit
The cycle counter enable bit memory is also
another 4096 x 1-bit RAM area which has
addresses identical to the code memory. When
the code memory contents are executed, the
corresponding bits in the cycle counter enable bit
memory are checked, and if a "1" bit is found, the
cycle- counter is counted up in step with that
machine cycle.
8. Probe comparison register/probe mask register
The conditions for generating a break by input
data from the probe (probe match break) can be
changed by altering these two settings.
9. Trace memory
The trace memory is a 1024 x 56-bit RAM area
used to store traced data.
The trace instruction is given by the trace enable
bit.
403
D
• EASE80C49 . ' - - - - - - - - - - - - - - - - - - - - - - - -
EASE80C49 EMULATOR MEMORY CONFIGURATION
The EASE80C49 emulator which consists of a host CP/M® computer and the MPB800 Evaluation Board has
been designed for efficient debugging of MSM80C49RS and MSM80C50RS application programs.
The various sections of the EASE80C49 Emulator which can be used are outlined in the following diagram.
The sections enclosed in boxes represent the register and memory areas which can be accessed from the
host computer keyboard, and which can be displayed/update by emulator command.
INSTRUCTION EXECUTED BIT MEMORY
TRACE ENABLE BIT MEMORY
SYNC OUTPUT BIT MEMORY
CYCLE COUNTER ENABLE BIT MEMORY
BREAKPOINT BIT MEMORY
BTl
PRE
CM
S
0
C
E
UB
TM
UTILITY
BUFFER
CODE
MEMORY
TRACE
MOMORY
4096 x S
4096 x S
1024x56
""\ 1/
4096 x 1
TRACE POINTER
I
I
OM
DATA
MEMORY
TP
CYCLE COUNTER.
12SxS
CC
PROGRAM COUNTER ACCUMULATOR INSTRUCTION DATA
PC
XM
EXTERNAL
MEMORY
256xS
(Option)
PROBE
COMPARE
REGISTER
PROBE
MASK
I
I
PR
S1
PM
AC
121
sl
INTERUPT
VDD
EXTERNAL
PROBE
~
IVDll
XP
sl
I
TESTa
EJ
sl
TEST 1
I
BS
sl
PO
TIMER
EC
PORT 1
sl
Pl
sl
ERROR CODE
s1
TI
PORTO
(Bus Port)
E] I
PROGRAM STATUS WORD
PS
BREAK CONTROL BREAK STATUS
REGISTER
REGISTER
BC
24
s\
10
sl
Emulator memory configuration
404
10
sl
PORT 2
sl
P2
sl
--------------------------------------------------. EASE80C49 •
EXECUTION EXAMPLE
In this sample program, 1 byte is read from port 1, and a parity check is executed on the first 7 bits. The MSB
(most significant bit) is set to "1" if parity is odd parity, and reset to "0" if even parity. The result is then passed
to port 2. Note that errors have been intentionally included in this program for demonstration purposes. Various
emulator commands are used to correct the errors.
It is assumed that the program has already been assembled, and the object code has been stored in hexadecimal format in a file called "PARITY.HEX" in drive A.
Program list
o0
o0
0 0
0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o9
5 3 7 F
o0 0 I
o0 0 3
1 40 C
E6 0 9
o0 0 5
4 3 0 8
o0 0 7
3 A
o0 0 9
040 A
000 A
o0 0 C
000 C
o0 0 C
BA 0 8
o0 0 C
o0 0 E
9 7
I 2 I 2
000 F
A 7
o0 I I
7 7
o0 I 2
o0 I 3
EA 0 F
o0 1 5
8 3
o0 I 6
0000
ERRORS
SYMBOL TABLE
PAR 0
0 0 0 C
***************************
*
This program reads a byte from Port 1 and checks
bits 0 thru 6 for parity. If Parity is odd, then
bit 7 in the byte will be set and the result will
be output to Port 2. If the Parity is even. bit 7
will be reset before the byte is output to Port 2.
****************************
**************
*
MAIN PROGRAM
*
**************
PARITY
PAR I
WAIT
ORG
IN
ANL
CALL
JNC
ORL
OUTL
JMP
A. P I
A. # 7FH
PAR 0
PAR I
A, # 8H
P2, A
WAIT
; Input byte from PI
; Mask out bit 7
; Jump if even parity
; Set bit 7
; Output byte to P2
**************
*
SUBROUTINES
*
**************
PAR 0
PAR 2
PAR 3
PARI
MOV
CLR
JB
CPL
RR
DJNZ
RET
END
o0
0 9 PAR 2
R 2, # 8
C
0 , PAR 3
C
A
R 2 , PAR 2
0 0 0 F
;
;
;
;
Set loop count
Initialize Carry Flag
Jump if bit 0 = I
Toggle Carry Flag
; Loop 8 times and ret
PAR 3
0 0 I 2
405
• EASE80C49 .-----------------------------------------------A> EASE4 9
MPB80080C49
EMULATOR. VER 4.3
COPYRIGHT JUNE.1982.
• FCM 0
FFF FF -
OKI
SEMICONDUCTOR
Code memory is filled with FFH
• LOA PAR I TY - - Contents of the "PARITY. HEX" file are transferred to the code memory
• D CM 0
1 F - - - - Code memory location contents from address OH thru 1FH are displayed
000=09
53
7F
14
OC E6
09
010=12
A7
77
EA
OF
FF FF FF
83
43
08
3A
04
OA BA
08
97
12
FF FF FF FF FF FF FF
·EBP A -----Break point at address AH is set to "1".
• E BP
1 7 F F F - - Break point bits from address 17H thru FFFH are st to "1"
• DB P 0
2 F - - - The break point bit status from address OH thru 2FH is displayed
000=0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
010=0000000111111111
020=1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
• CP 1
0
Port 1 is set to "0" (even parityj
• CP 2
0 - - - - - Port 2 is set to "0"
•G 0
Start of emulation from address OH
EMULATION BEGUN
PC=O OA TERMI NATED
R 1 =CA
• CP 1
PO=FF P1=00 P2=00 TO=1 T1=1 XP=FF AO=OO RO=
- - . Port 2 is correct in respect to even parity
1 - - - - - Port 1 is set to "1" (odd parity)
• S DF -AL P 1 P 2 AC - - Dump format is changed
• G 0 - - - - - - Start of emulation from address OH
EMULATION BEGUN
PC=O OA T BRM I NAT ED P1=0 1 P2=09 AC=09- Port 2 is not correct in respect to odd parity
• CP 1
3
Port 1 is set to "3" (even parity)
--:---~.
Port 2 is set to "0"
• G 0 - - - - - - Start of emulation from address OH
EMULATION BEGUN
PC=OOA TERMINAT
• CP 1
4
Port 1 is set to "4" (odd parity)
.CP20
Port 2 is set to "0"
·G 0
Start of emulation from address OH
406
------------------------------------------------. EASE80C49 •
EMULATIOM BEGUN
P C= 0 OA T BRM I NA TED P 1=0 4 P 2=OC AC=OC - Port 2 is not correct in respect to odd parity
-DTM -10 1 0 - - - Trace contents of the last ten cycles are displayed
PC=015 RET
PO=FF Pl=04 P2=00 TO=1 Tl=1 IN=1 XP=FF TP=0058
PC=005 JNC
09
PO=FF Pl=04 P2=00 TO=1 Tl=1 IN=1 XP=FF TP=0060
POSSIBLE INTERRUPT ........ SEE APPENDIX3
~
PC=007 ORL A.#08 PO=FF Pl=04 P2=00 TO=1 Tl=1
PC=009 OUTL P2.A
PO=FF Pl=04 P2=OC TO=1 Tl=1
PC=OOA JMP
OOA
PO=FF Pl=04 P2=OO TO=1 Tl=1
-EBP
5
-CP2
0
-G
IN=1 XP=FF TP=0062
IN=1 XP=FF TP=0064
IN=1 XP=FF TP=0066
The break point bit at address 5H is set to "1"
Port 2 is set to "0"
0
Start of emulation from address OH
EMULATION BEGUN
PC=007 TERMINATED
Five
-STP 5
PO=007 ORL
A.#08
PO=009 OUTL P2.A
PO=O OA JMP
OOA
PO=OOA JMP
OOA
PC=OOA JMP
OOA
Pl=04
P2=00
AC=04
steps (instructions) are executed
P 1=0 4
Pl=04
Pl=04
P2=0 0 AO=OO
P2=OC AC=OC
P2=OC AO=OC
P 1=0 4
Pl=04
P2=OO AO=OO
P2=OO AO=OC
0
F - - - - - Code memory location contents from address OH thru FH are displayed
000=09
-OOM 8
-DOM 0
000=09
-RBP 5
53 7F 14 OC E6 09 43 08 3A 04 OA BA 08 97 12
80 - - - - Code memory location contents at address 8H are changed to "80H"
F - - - - Code memory location contents from address OH thru FH are displayed
-DCM
-OPI
53
7F
14
OC
E6
09
43
80
3A
04
OA
BA
08
97
12
. - - - - - rhe break point bit at address 5H is set to "0" (reset)
1 - - - - - Port 1 is set to "1" (execution of odd parity again)
0
*CP2
*G 0
EMULATION BEGUN
PO=OOA TERMINATED Pl=OI P2=81 AO=81- 0 P 1 7F
Port 1 is set to "7F" (execution of odd parity again)
-CP2 0
*G 0
EMULATION BEGUN
PO=OOA TERMINATED
Pl=7F P2=FF AC=FF-Port2iscorrectinrespecttooddparity
- SAy 0 1 F PRTY 1- Program with file name of "PRTY1.HEX" is stored
* F OM 0 F F F F F - - Code memory is filled with FFH
* V PRO F F F 0 - - EPROM is inserted into an EPROM socket and a blank check is
executed
* LOA P R T Y 1
Program with file name of "PRTY.HEX" is transferred to code memory
- P PRO 1 F 0 - - - Transferred contents are written in the EPROM
- V P R 0 1 F 0 - - - EPROM contents are compared with code memory contents
- i C ~ No error message (EPROM and code memory contents are identical)
A
Return to CP/M(R) control
>
-----
407
• EASE80C49 . - - - - - - - - - - - - - - - - - - - - - - - - -
LIST OF DEBUGGING COMMANDS
Characters which can be used
AaBbCcDdEeFfGgHh liJjKkLlMmNnOoPpOqRrSsTtUuVvWwXxVyZz 1234567890.,@+Cntl/C Cntl/P Cntl/O CntllR CntlfT Escape Space
Display Commands
1. DAC
2. DBP, 000 [,FFF]
3. DBS
4.DCC
5. DCE, 000 [,FFF)
6. DCM, 000 [,FFF]
7. DDM, 00 [,7F]
8. DIE, 000 [,FFF)
9.DPO
10. DP1
11. DP2
12. DPC
13. DPS
14. DRG
15. DSK
16. DSO,OOO[,FFF]
17. DTI
18. DTM, XXX, YVYV
19. DTP
20. DTR, 000 [,FFF]
21. DVD
22. DXM, 00 [,FF]
23. DXP
Display Accumulator
Display Breakpoint Bit(s) Status
Display Break Status
Display Cycle Counter
Display Cycle Counter Enable Bit(s) Status
Display Code Memory
Display Data Memory
Display Instruction Executed Bit(s) Status
Display Port a (Bus Port)
Display Port 1
Display Port 2
Display Program Counter
Display Program Status Word, Test 0, Test 1, Interrupt Pin
Display Registers RO thru R7
Display Stack
Display Sync Output Bit Memory
Display Timer
Move Trace Pointer (XXXX) and display Trace Memory (YVYV)
Display Trace Pointer
Display Trace Enable Bit(s) Status
Display Vdd Pin
Display Ex1ernal Memory
Display Ex1ernal Probe Byte, Probe Mask and Probe Compare Register
Change Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
CAC, FF
CCC,
CCM, FFF, FF
COM, 7F, FF
CPO, FF
CP1, FF
CP2, FF
CPC, FFF
CPM, BBBBBBBB
CPR, BBBBBBBB
CPS, FF
CTI, FF
CXM, FF, FF
zzzzzzzz
Change Accumulator
Change Cycle Counterr (ZZZZZZZZ is a positive or negative decimal number)
Change Code Memory
Change Data Memory
Change Port (Bus Port)
Change Port 1
Change Port 2
Change Program Counter
Change Probe Mask (BBBBBBBB is a binary number)
Change Probe Compare Register (BBBBBBBB is a binary number)
Change Progr.am Status Word
Change Timer
Change External Memory
a
Fill Commands
1. FCM, 000, FFF, FF
2. FDM, 00, 7F, FF
3. FXM, 00, FF, FF
Fill Code Memory
Fill Data Memory
Fill Ex1ernal Memory
Enable Commands
1.
2.
3.
4.
408
EBP, 000 [,FFF)
ECE, 000 [,FFF]
ESO, 000 [,FFF]
ETR, 000 [,FFF)
Enable Breakpoint Bit(s)
Enable Cycle Counter Bit(s)
Enable Sync Output Bit(s)
Enable Trace Bit(s)
--------------------------------------------------. EASE80C49 •
Reset Commands
1.
2.
3.
4.
5.
6.
RBP, 000 [,FFF]
RCE, 000 [,FFF]
RIE, 000 [,FFF]
RSO, 000 [,FFF]
RTR, 0000 [,FFF]
RES
Reset Breakpoint Bit(s)
Reset Cycle Counter Enable Bit(s)
Reset Instruction Executed Bit(s)
Reset Sync Output Bit(s)
Reset Trace Enable Bit(s)
Reinitialize MPB800 System
Utility & Disk Input/Output Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
CUB, FFF, FF
DUB, 000 [,FFF]
FUB, 000, FFF, FF
TCM, 000, FFF
TUB, 000, FFF
TST
LOA, filename
LOU, Filename
SAV, 000, FFF, filename
SVU, 000, FFF, filename
Change Utility Buffer
Display Utility Buffer
Fill Utility Buffer
Transfer Code Memory into Utility Buffer
Transfer Utility Buffer into Code Memory
Test
Load Program into Code Memory
Load Program into Utility Buffer
Save Code Memory Program
Save Utility Buffer Program
EPROM Writer Commands
1. PPR, 000, FFF, FF
2. VPR, 000, FFF, FF
3. TPR, 000, FFF
Pogram Code Memory onto EPROM
Verify EPROM with Code Memory
Transfer EPROM into Code Memory
Emulation Commands
1. G[,HHH]
2. STP [,EEEE] [,HHH]
3. SBC, mnemonic
[,mnemonic]
4. SDF, mnemonic
[,mnemonic]
Begin real time emulation. HHH is the start address (hex).
Step emulation, where EEEE is the decimal number of instruction to execute,
and HHH is the start address (hex).
SeVReset Break Control Bit
SeVReset Dump Format
Command Line Editing & Keyboard Operation
1. Rubout
2. Cntl/C
3. Cntl/P
4.
5.
6.
7.
8.
Cntl/Q
Cntl/R
Cntl/S
Escape
@
Delete the last character entered
Return to CP/M
Copy all subsequent console output to the currently assigned list device.
Output is sent to both the list device untill the next CnVP is typed.
Continue normal display
Echoe current input line
Stop display
Abort any command inprogress
Repeat last command
409
o
• EASE80C49 . - - - - - - - - - - - - - - - - - - - - - - - - -
EASE80C49 8-BIT 1-CHIP MICROCONTROLLER
PROGRAM DEVELOPMENT SUPPORT SYSTEM
Category
Hardware
Software
Manual
Title
Model
MPB800
8-bit 1-chip microcontroller evaluation board
EASE-49
Floppy disk based emulator'
ASM-49
Floppy disk based assembler'
TM-800
Program Development Support System-User's Manual
TCU-800
TCS-8
User application system connecting cables
Host CP/M(R) computer connecting cables (for if800 model 20/30)
Accessories
TCP-8
Power supply cables (+5V,3.5A) (+12V, 0.2A) (-12V,O.2A)
TCX-1
External probe emulation purposes
• Available under following operating system
• CP/M-80 (ver 2.0 or later)
• MS-DOS (ver2.11 or later)
• PC-DOS (ver2.11 or later)
u
410
EASE80C51 mkll PROGRAM DEVELOPMENT SYSTEM
for
MSM83C154/80C51 CMOS 8-BIT, 1-CHIP MICROCONTROLLER
EASE80C51mkil PROGRAM DEVELOPMENT SYSTEM
The EASE80C51 mkll Program Development System is a high-performance dedicated system
featuring Oki's exclusive technology, and which has been specifically designed for rapid and efficient
program development of the Oki MSM83C154/80C51 8-bit single-chip microcontroller.
SYSTEM CONFIGURATION
The EASE80C51 mkll Program Development
System consists of the EASE80C51 mkll Emulator
(a high performance program emulator which includes the EASE Host Monitor, the EASE8051 mkll Emulation Kit, and the host CP/M@ or
PC-DOS computer) and the ASM51 Assembler
(a powerful assembler operated in CP/M@ or
PC-DOS. With the EASE80C51 mkll Emulation
Kit connected online to the host CP/M computer
(such as the if800) equipped with an RS232C
interface, the system covers all operations from
assembly of the source program through to
program evaluation and debugging.
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M®-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS@ (ver2.11 or later)
(3) PC-DOS'" (ver2.11 or later)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BOOS function
call 6 on condition that console device is
assigned to TTY:.
EMULATOR DATA TRANSFER
ICs used
• Communication interiace MSM82C51A
• Driver/receiver
SN75188N,
SN75189N
Transmission format
• 300 to 19200 bps (Switch able)
• 8 bits, 2 stop bits, non-parity
• Asynchronous
411
• EASE80C51mkil .---------------------------------------------
User's
application
User's
application
circuit
circuit
• EASE
• ASM51
User cable
FDD
User cable
Host
Terminal Unit
computer
(CRT terminal etc.)
RS232C
RS232C
EASE80C51 mkll
Emulation
~
EASE80C51 mkll
Emulation
Kit
Kit
/
". AC power supply
(1) Connection to host computer
(2) Connection to terminal unit
Fig. 1 System configuration
Note 1. CP/M is a registered trademark of Digital Research Inc. (U.S.A.)
2. The AC power supply can be switched to 90-132V and 180V-264V at a terminal inside the emulation kit.
3. PC-DOS stands for IBM personal computer DOS.
412
- - - - - - - - - - - - - - - - - - - - - - - - - . EASE80C51 mkll •
ASM51 ASSEMBLER
The ASM51 is a floppy disk based high-performance assembler.
This assembler is used to translate source files generated on disk by using an editor (available on the market),
thereby generating object files (Intel HEX format), assemble list files, cross-reference list files, and symbol list
files in the specified devices.
OUTPUT FILES
PART OF PSEUDO-INSTRUCTIONS LIST
1.
2.
3.
4.
Pseudo-instructions
Object files (Intel HEX format)
Assembly list files
Cross-reference list files
Symbolic list files
ASSignment of operand value
to name
SET
Same as EQU pseudoinstruction, but with
redefinition capacity
ORG
Setting of program start
address
END
Indication of end of program
JMP
Automatic change to relative,
internal2K page, or all pages
jump instruction after checking
branch destination
CALL
Automatic chang to relative,
internal 2K page, or all pages
call instruction after checking
branch destination
RADIX
Radix changed to 2, 8, 10, or
16 depending on value of
operand
DB
8-bit data or ASCII character
definition
DW
16-bit data definition
DS
Reserves memory area for
specified number of bytes
NSE
Setting of in the 4 lower
order bits of the assembler
location counter, and addition
of 16. The NOP instruction is
assigned to blank areas
where no machine language
instruction has been assigned.
DATE
Insertion of date in assemble
list title
EJECT
Assemble list page feed
operation
TITLE
Insertion of assemble list title
LIST
Designation of assemble list
output
NOLIS
Zuhibition of assemble list
output
FEATURES
1. Free descriptive format source files
2. Capacity to describe up to ten types of operators
in the source program operand column
3. Ability to specify the number of characters per line
and the number of lines per page in assemble list
files
4. 24 powerful pseudo-instructions
5. Control of assemble list file outputs by LIST or
NOLIST pseudo-instruction
6. Output file and output device can be specified
when the assembler is started.
ASM51 ASSEMBLER FUNCTIONAL
BLOCK DIAGRAM
Source file
ASM51
Assembly list files
' - - - -__ Symbol list files
____
Function
EQU
Cross~reference
list files
°
413
e EASE80C51mkil e--------------------------------------------___
EASE80C51mkil EMULATOR
Connected to the host computer via an RSS232C interface, the EASE80C51 mkll Emulator supports a
wide range of development debugging operations efficiently and effectively.
MSM83C154/80C51 application programs can be debugged without user application circuits just as
easily as completed systems.
FEATURES
1. Real-time emulation
Real-time emulation without insertion of a wait
state is possible because of the MSM83C154E
evachip.
2. Execution time measurement
The user program execution time can be measured with the cycle counter in the Emulation Kit.
(Max. 4,294,836,225 cycles)
This cycle counter start/stop is effected according to the cycle counter start address/stop address set by the command.
3. Mass storage user program area
This emulator provides a 64K-byte RAM area,
(which is the entire address space of
MSM83C154/80C51) as the code memory
(user program area). So, the largest program for
MSM83C154/80C51 can be fully loaded in this
RAM area.
It is also possible to assign 4K-byte units of program
memory area to the RAM area on the emulation kit or
the ROM on the user's application circuit by using
the mapping command.
This emulator further provides the EPROM programmer to enable the user program area contents to be written to the EPROM or the EPROM
contents to be read.
(EPROMs supported: Intel 2732, 2732A, 2764
or 27128 or equivalent:)
4. Ample break functions
The emulator can suspend (break) program execution by any of the following break conditions.
All conditions can be set and cancelled as
desired.
a) Breakpoint break
Br~ak upon execution of the address where a
break point has been set. (Any address to be
specified.)
b) Address break
Break execution of the address specified
when the emulation command input was applied. It is also possible to specify a break
after the specified address has been executed n times.
c) Power down break
Breakoccured when evachip going to the
power down mode.
d) Break·by external forced break signal
Break by input of low level break signal from
outside via the attached probe cable.
414
e) Break by trace memory overflow
Break occurs when the trace memory is filled
up with trace data.
I) Break by cycle counter overflow
g) Break by internal RAM/SFR area contents
Break occurs when the contents of the specified RAM/SFR in the MSM83C154E matched
with the specified contents the specified
number of times upon execution of the program at the specified address.
5. Comprehensive real-time trace functions
This emulator has the following two real time
trace areas not affecting the execution time.
1. Trace memory
This is the memory to trace (store) the status of
the ports, carry flag and accumulator of the
MSM83C154E when an instruction in the program memory area is executed. (Up to 2048 machine cycles)
Tracing is instructed in three ways as shown
below.
a) To start tracing each time the specified address is executed.
b) To start tracing upon execution of a special
instruction (ACALL, AJMP, LCALL, LJMP,
RET, RETI, PUSH or POP)
c) To cause tracing by trace start/stop bit
2. Flash trace memory
The memory to trace status of the whole internal
RAM or SFR area in the MSM83C154E, when
the instruction at the address specified by the
emulator command (debug command) being
executed.
The contents of the internal RAM or SFR area
can be stored up to 16 times in this memory.
6. Easy-to-use emulator commands
The emulator command (debug command) of
this emulator consists of the command mnemonic and succeeding parameter(s) (address or
mnemonic).
Command mnemonic structure
a) First letter
Represents the function to be performed by
the emulator.
b) Second letter and on
Represent MSM83C154E evachip (or EASE80C51 mkll emulation kit) register, memory, or
port name.
- - - - - - - - - - - - - - - - - - - - - - - - . EASE80C51 mkll •
Example:
*DDM
0
1F.)
II \JcdI eV II
ab
a: Indication 01 waiting lor command input Irom
emulator
b: Instruction 01 displaying contents 01 specified
object
c: Instruction of data memory (equivalent to internal
RAM area in MSM83C154E)
d: Start address of contents to be displayed
e: End address of contents to be displayed
I: Carriage return indicating end of command input
This emulator provides various emulator commands not only for display/modification of the
contents of each register and port of the special
evaluation chip MSM83C154E but also for
efficient debugging operation.
Input format:
STP number-of-instructions start-address
Inputting the above command causes the user
program to be executed for as much as the
specified number of instructions from the
specified addresses (start address).
It is possible to modify the display format to be
easier to read by specifying the object of
contents display by the SSF command.
Input format:
G start-address, parameter
Parameter input format
(1) Break-address, ... , break-address
(2) Break-address (n)
(3) Break-address RAM ram-address (byte-n)
(4) Break-address sfr-mnemonic (byte-n)
Inputting the command as shown in (1) causes the
user program to be executed from the specified address (start address), and breaks the program execution upon execution of any of the specified break addresses.
Inputting the command as shown in (2) causes the
user program to be executed from the specified start
address, and breaks the program execution when it
has passed the specified break address in times.
Inputting the command, as shown in (3), causes the
program to be executed from the specified address
(start address). When the user program at the
specified break address is executed, the contents of
the specified address (ram address) of the internal
RAM in the MSM83C154E are compared with
the specified contents (byte) and the program execution is broken if they agree the specified
numberoftimes (n).
Inputting the command, as shown in (4), causes the
user program to be executed from the specified address (start address). When the user program at the
specified break address is executed, the contents of
the specified SFR in the MSM83C154E are
checked. If the contents agree with the specified
value (byte) the specified number of times (n),
breaking occurs.
Input format:
(1) LOD filename
(2) SAV filename start-address end-address
(3) VER filename start-address end-address
Inputting the command, as shown in (1), enables the
contents (user program) of the specified file on
the host computer to be loaded into the code
memory on the EASE80C51 mkll emulation kit
corresponding to the program memory area
(user program area) of the MSM83C 154/80C51 .
Inputting the command, as shown in (2), enables the
block of code in the specified range of the code
memory to be saved using the specified file name.
Inputting the command, as shown in (3), enables the
block of code in the specified file to be compared with
the block of code in the code memory.
Input formal:
(1) DIAG filename
(2) M
(3) @
Inputting the command, as shown in (1), enables the
command in the specified file to be executed automatically. Use of the PAUSE command in combination enables execution of the command in the file to
be suspended temporarily.
Inputting the command, as shown in (2), enables the
command line defined by the MAC command to be
executed.
Inputting the command, as shown in (3), enables the
last command to be executed again.
Input formal:
(1) LIST filename
(2) NLST
If LIST command is entered, the emulator create
the CP/M file on the host computer and writes
into it any characters which are output to the
console until entering the NLST command.
Use of the above "DIAG" command in combination
enable the debugging work to be executed and stored
in the file automatically.
Input formal:
S tm-mnemonic data number
Using the S command, you can search out the trace
information in the trace memory.
Where the "tm-mnemonic" is the element of the
trace information in the trace memory that you
wish to search, and "data" is a value of that
element. "number" is the time of an agreement.
For example, Entering "S" PO 2 3", the emulator
searches through the trare memory from the top
and finds the position where the trace PO data is
equal to 2, three times, and displays the trace
information at that position.
415
7
e EASE80C51mkil
e------------------------
DISK ACCESS COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
lOD
SAV
VER
DIAG
LIST
NlST
HELP
FDD
[dr:) filename
[dr:) filename [address adress)
[dr:) filename [address adress)
[dr:) filename
[dr:) filename
dr: ... dr:
load Program into Code Memory
Save Code Memory Program
Verify File with Code Memory
Execute command file
List console Output into Disk file
End listing
Display HELP File
Set Disk Drive
EPROM PROGRAMMER COMMANDS
1.
2.
3.
4.
PPR address address [address)
TPR address address [address)
VPR address address [address)
TYPE mnemonic
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
Set EPROM type
ASSEMBLE COMMANDS
1.
2.
3.
4.
5.
ASM
DASM
DBlK
SPB
SOB
address
address
address [address)
address [address)
address [address)
Assemble to Code Memory
Disassemble to Console
Display Block Memory
Set Program Block
Set Data Block
TRACE COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
DTM-number number
DFTM number number
DTG
DFA
S mnemonic data number
SFF mnemonic
STG mnemonic
SFA address [ ... address)
RFA address [ ... address)
RTG
Display Trace Memory
Display Flash Trace Memory
Display Trigger Mode
Display Flash Trace address
Search Trace Memory data
Set Flash Trace Display format
Set Trigger Mode
Set Flash Trace address
Reset Flash Trace address
Reset Trigger Mode
EMULATION COMMANDS
1.
2.
3.
STP number [number)
G[st-address) [,break-parameter)
If the optional st-address if given, emulator will begin emulation from st-address.
And if optional break-parameter is given.
emulation will break on the first break-parameter to be satisfied.
break-parameter = break-address, ..... , break-address (max. 10)
break-address (pass count)
break-address RAM ram-address (byte-pass count)
break-address sfr-mnemonic (byte-pass count)
SSF (+/-) mnemonic [... (+1-) mnemonic)
Set STP Command Display format
DISPLAY COMMANDS
1.
2.
3.
4.
5.
6.
416
0
Dsfr-mnemonic
DSFR mnemonic [ ... mnemonic)
DPC
DREG
DSBUF
Display Register Flag Port
Display sfr-mnemonic data
Display mnemon ic data
Display Program Counter
Display all Register Bank
Display receiver data
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ e EASE80C51 mkll e
CHANGE COMMANDS
1.
2.
3.
4.
5.
Csfr-mnemonic data
CSFR [mnemonic ... mnemonic!
CPCdata
CREGdata
CSBUFdata
Change sfr-mnemonic
ChangeSFR
Change Program Counter
Change Register ban k
Change Transmitter data
CODE MEMORY & DATA MEMORY COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
DCM address [address!
DDM address [address!
DXDM address [address!
CCMaddress
CDMaddress
CXDM address
FCM address address byte
FDM address address byte
FXDM address address byte
Display Code Memory
Display Data Memory
Display External Data Memory
Change Code Memory
Change Data Memory
Change External Data Memory
Fill Code Memory with byte
Fill Data Memory with byte
Fill External Data Memory with byte
ATTRIBUTE MEMORY COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
DBP address [address!
DTR address [address!
DSO address [addressl
DIE address [addressl
EBP address ... address
ETR address ... address
ESO address ... address
FPB address address byte
FTR address address byte
FSO address address byte
RBP,address ... address
RTR'address ... address
RSO address ... address
RIE
Display Break Point Bit Memory
Display Trace Enable Bit Memory
Display Sync Output Enable Bit Memory
Display Instruction Executed Bit Memory
Enable Brak Point Bit
Enable Trace Enable Bit
Enable Sync Output Enable Bit
Fill Break Point Bit Memory with byte
Fill Trace Enable Bit Memory with byte
Fill Sync Output Enable Bit Memory with byte
Reset Break Point Bit
Reset Trace Enable Bit
Reset Sync Output Enable Bit
Reset Instruction Executed Bit Memory
o
BUFFER MEMORY COMMANDS
1.
2.
3.
DBUF
TBUF
LBUF
Display Buffer Memory
Transfer Data Memory & SFR Data into Buffer Memory
Load Buffer Memory into Data Memory & SFR
CYCLE COUNTER COMMANDS
1.
2.
3.
DCC
CCCdata
TIME data
Display Cycle Counter
Change Cycle Counter
Set 1 cycle time
BREAK CONDITION & STATUS COMMANDS
1.
2.
3.
DBC
DBS
SBC (+/-) mnemonic .. (+1-) mnemonic
Display Break Condition
Display Break Status
Set Break
OTHER COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
RES
RES E
SIOForH
PAUSE
EXIT
DIR[dr:)
MAP [address!
MAC
M
@
M80C51
M83C154
EASE80C51 mK11 System initialization
MSM83C154E Evachip reset
Set Emulator to I/O terminal mode
Stop comm3.nd file execution and wait key-in
Return Host computer's OS
Display file directory
Mapping
Define command execution
Execute Defined command
Repeat front command
Set Em u lator to the MSM80C51 checking mode
Set Emulator tothe MSM83C154 checking mode
417
e EASE80C51mkil
e------------------------------------------_____
EASE80C51 mkll PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the MSM83C154/80C51 CMOS 8-BIT 1-CHIP MICROCONTROLLER
Clock select switch
AC power
connector
Reset SWit'\ \
Probe cable
connector
Crystal oscillator
connector
EPROM programmer
User cable
connector
300 (W) x 105 (D) x 210 (H) mm
RS232C
connector
Category
o
Model name
Component name
Hardware
EASE80C51 mkll
Emulation kit
Emulation kit for MSM83C154/80C51
Software
EASE
ASM 51
Host monitor for floppy disk based (Note 2)
Assembler for floppy disk based (Note 2)
Manuals
TM-80C51
AM-80C51
EASE80C51 mkll Emulator User's Manual
ASM51 Assembler User's Manual
Accesories
TCU-80C51
TCS-n
TCP-2
TCX-2
User application circuit connection cable
Host computer connection cable (3) (Note 3)
AC power supply cable
Emulation probe cable
Note 1. Refer to the ASM51 Assembler User's Manual for assembler details.
Note 2. PCDOS 51 /4 floppy disk, PC format, double-side double-density (8 sectors x 40 tracks x 2)
PC DOS stands for IBM personal computer DOS.
CP/M-80 8-inch floppy disk, IBM3740 soft-sectored format, single-side single-density.
CP /M-80 is the registered trademark of Digital Research Co.
Note 3. Two cables are used for connecting the if800 or equivalent computer to the EASE80C51 mkll
Emulation Kit-one to the CH1 port, and the other to the CH2 port. (Model name, TCS-2)
The third cable is for connection of an IBM PC or equivalent computer to the EASE80C51 mkll
Emulation Kit. This calbe is connected to the CH1 port. (Model name, TSC-3).
418
-------~---------------.
EASE80C51 mkll •
OPTIONAL SOFTWARE
OS
Name
Supplied software
CP/M-80
MS-DOS
PC-DOS
VMS
UNIX
PASM
0
0
0
·
MAC51
0
0
0
RL51
0
0
0
LlB51
0
0
0
0
0
0
0
·
·
·
·
·
·
SID51
OBJHEX
.
.
·
·
·
·
·
Pre-Processor
Macro-Assembler
Linker
Librarian
Symbolic Debugger
Object Converter
• ·····Being developed
OPTIONAL HARDWARE
Type
EASE8
Remarks
Handy I/O terminal
EASE8 can be used as a terminal unit for the EASE80C51 mkll Emulation Kit.
(Convenient portable model)
o
419
MAC51 SUPPORT
SO~RE
PACKAGE
for the
MSM80C51 CMOS 8-BIT MICROCONTROLLER
FEATURES
1. Symbolic relocatable assembly language programming for 80C51 /154 microcontrollers
2. Produces Relocatable Object Code which is
linkable to other 8051 Object Modules
3. Encourages modular program design for
maintainability and reliability
4. Macro Assembler features conditional assembly and macro capabilities
MAC51 SUPPORT SOFTWARE PACKAGE
The following MAC51 programs are available
to develop user programs.
PASM Pre-processor
PASM is used to expand macro calls,
conditional assembly statements, and INCLUDE
statements included in user generated source
programs, thereby generating expanded source
programs. A number of items of development
information are inserted in these developed
source programs for MAC51.
o
MAC51 Assembler
MAC51 converts source programs into
relocatable codes to form relocatable object files
(OBJ files). Print, symbol, cross reference, and
error files are generated as assembly
information.
420
LlB51 Librarian
The L1B51 program manages OBJ files for
each module. Files consisting of a number of
relocatable object modules (OBJ modules)
generated by L1B51 are called the object library.
L1B51 handles object library generation, and
OBJ module addition, deletion, and upgrading.
RL51 Linker
RL51 links and relocates one or more OBJ
modules to generate one absolute object
module. RL51 also generates a list file
consisting of symbol table and link map as link
information. OBJ modules which serve as the
RL51 input can be OBJ files generated by
MAC51, and OBJ modules located within the
object library generated by L1B51.
SID51 Symbolic debugger
SID51 is used when a symbol using
debugger is selected. Absolute object files are
converted to Intellec HEX format files.
OBJHEX Converter
OBJHEX converts Object file into Intellect HEX
file.
Outline of Program Development
The procedures involved in the processing
from source program generation through ROM
loading are described below in the sequence
indicated in Figure 1-1. For further details of
individual utilities, refer to the respective
manuals.
- - - - - - - - - - - - - - - - - - - - - - - - - - - . MAC51 •
1. Generation of MAC51 assembly language
source program by the editor.
Source programs can contain basic and
pseudo instructions, and assembler control,
macro call, conditional assembly, and
INCLUDE statements.
2. When macros are used, macro definitions are
generated in macro library files (with MAC
extension) by the editor. Macro call
statements are described within source
programs.
3. Where macro call, conditional assembly
statement, and INCLUDE statement
descriptions are included in a source
program, there are expanded by PASM to
form an expanded source program.
4. Source programs or expanded source
programs are assembled by MAC51 to form
relocatable object files.
5. A group of relocatable object files can be
managed by L1B51 together in a relocatable
object library files (LIB extension). When
required, object modules can be called from
this object library by RL51.
6. Relocatable object files are converted to
absolute object files by RL51. At this stage,
one or more relocatable object files can be
linked to relocatable object modules in the
library file.
7. ABS modules are converted by SID51 or
OBJHEX to Intellec HEX format files. With
EASE80C51 mkll, HEX file contents can be
written into EPROM devices .
o
5.
EASE80C51mkll
Fig. 1 -1 Program development flow
421
MEMO
MEMO
MEMO
OKI
Oki Semiconductor
650 North Mary Avenue, Sunnyvale, CA94086, U.S.A.
Tel: (408) 720-1900
Fax: (408) 720-1918
Telex: 2966870KI SNTA
For further information please contact:
Old Electric Industry Co., Ltd,
Head Office Annex
10-3, Shibaura, 4-<:home,
Minato-ku, Tokyo 108, Japan
Tel: 3-454-2111
Fax : 3-798-7643
Telex : J22627
Electronic Devices Group
Overseas Marketing Dept.
Printed in USA
Old Semiconductor
650 Norih Mary Avenue,
Sunnyvale, CA 94086,U.S.A.
Tel: (408) 720- t900
Fax : (408) 720-1918
Telex : 296687 OKI SNTA
Old Electric Europe GmbH
Niede"'a,seler Lohweg 8,
0 -4000 ousseldorl II ,
Fed. Rep. of Gennany
Tel : 211 -59550
Fax : 211 -591669
Telex : 853-4312 OKI·o
~
~
SINe[ 188 1
Old Electronics (Hong Kong) Ltd.
16th Roor, Fairmont House.
8 Cotton Tree ~rive , Hong Kong
Tel: 5-263111
Fax : 5-200102
Telex : 62459 OKIHK HX
.( Oki Semiconductor
REF NO.: MCU10-4A24·58
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