1988_Plessey_Frequency_Dividers_and_Synthesisers_IC_Handbook 1988 Plessey Frequency Dividers And Synthesisers IC Handbook

User Manual: 1988_Plessey_Frequency_Dividers_and_Synthesisers_IC_Handbook

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FREIUENCY
DIVIDERS

and

SYNTBESISERS
ICBandbook

PLESSEY

Semiconductors

Foreword
Plessey Semiconductors has long been recognised as a leading source of high speed
dividers ICs. The SP8000 series of dividers has led the world over the past 15 years in speed
and technical performance. One of the most comprehensive ranges of fixed and
programmable dual-modulus frequency dividers currently available, the SP8000 series has
found design slots in a wide variety of applications. In the Military market, our devices are
used in Frequency Synthesis systems in Radio Communications, Guidance systems in
Missiles, Electronic Warfare etc. In the Professional market, they are used in Instrumentation
equipment, and in Cellular/Cordless telephones and Private Mobile Radio equipment.
To satisfy the differing requirements of these markets, all products in the SP8000 series can
be supplied with a variety of packaging and screening options.
Plessey Semiconductors alsO offers a wide variety of parts to cater to the various
requirements of Frequency Synthesiser systems. From UHF Two-Modulus Synthesiser
systems to a single chip self-contained PLL Synthesiser IC, our products have truly
established themselves, with more innovative designs in the pipeline to further our reputation
as a suplier of synthesiser circuits.

FREgUENCY
DIVIDERS
and
SYNTBESISERS
ICBandbook
Contents
Page
Foreword
Product index
Product list
Semi-custom design
The Quality Concept

2
4
8
10
12

Technical data
1.
2.

SP8000 Series High Speed dividers
Frequency synthesisers

227

Application notes
Phase noise intermodulation and dynamic range
Radio synthesiser circuits loop filter design
A serially programmable VHF frequency synthesiser
Design compromises in single loop frequency synthesiser
The care and feeding of high speed dividers
Universal programmer for Plessey synthesiser ICs
Using the SP8835 in 3.5GHz synthesisers
Thermal design
Package outlines and ordering information
Plessey Semiconductors locations

291
300
313
315
322
328
331
333
335
347

SP8000 series high speed dividers
Prod uct Index
Plessey Semiconductors' SP8000 series leads the world in technical performance. One of
the most comprehensive ranges of dividers available, the SP8000 series has been developed
and extended to cater for the exacting requirements of the instrumentation and
communications markets. The range includes prescalers from divide-by-2 up to divide-by129, operating from 1Hz to 3.5GHz.
Suffix A Military
Suffix B Commercial

-55°C to +125°C
-40°C to +85°C
O°C to +70°C
-30°C to 70°C
(please check with data sheet of device type)

Fixed modulus dividers

SP8604A
SP8604B
SP8602A
SP8602B
SP8607A
SP8607B
SP8605A
SP8605B
SP8606A
SP8606B
SP8822A
SP8822B
SP8812A
SP8812B
SP8802A
SP8832B
SP8790A
SP8790B
SP8601A
SP8601B
SP8600A
SP8600B
SP8610A
SP8610B
SP8611A
SP8611B
SP8712B
SP8824A
SP8824B
SP8814A
SP8814B
SP8804A
SP8835B

•
•
•

•

•
•
•

•

•
•
•
•

•
•
•
•
•
•
•
••

•
•

•

•
•

300
300
500
500
600
600
1000
1000
1300
1300
1800
1800
2400
2400
3300
3500
60
60
150
150
250
250
1000
1000
1300
1500
2400
1800
1800
2400
2400
3300
3500

•••
••
••
•••
••
•••
•
••
••
••
•
•••
•

•
••
•

••
••
•
•

18
18
18
18
18
18
100
100
100
100
53
53
65
65
100
100

•

11
11
25
25
25
25
100
100
100
100
110
48
48
52
52

90
90

••
••

•
•
•

••
••
••

••
••
•

••
•

••
•
•
•

••
••
••

••
•
••
•
••
•

•
•
•

•
•

Fixed modulus dividers (continued)

SP8794A
SP8794B
SP8670A
SP8670B
SP8735B
SP8675B
SP8678B
SP8828A
SP8828B
SP8818A
SP8818B
SP880SA
SP8838B

SP8660A
SP8660B
SP8660
SP8637B
SP8630A
SP8630B
SP8635B
SP8634B
SP8665B
SP8668B
SP8830A
SP8830B

SP8659A
SP8659B
SP8650A
SP8650B

SP8655A
. SP8655B

I 100 I

SP8629

•

•
•

••
•

•
•
•

•
•

•

•
•••
•

•
•
•

•
•

BN = Binary outputs
Package codes: CM = Metal Can, OG

= Ceramic OIL,

120
120
600
600
600
1000
1500
1800
1800
2400
2400
3300
3500
150
150
150
400
600
600
600
700
1000
1500
1500
1500
200
200
600
600

••

••
•

••
••

••

••
••
• •
••
••
•
•
••
•
•

••

11
11
45
45
90
95
95
45
45
48
48
85
85
13
13
13
90
70
70
90
90
105
105
50
50
13
13
45
45

200
200

I: I I

13
13

150

I•

•
•
BN

••
•
BN
BN
BN

••

••
•
•••
•
•••

••

••
••
••
•
•

••
••
•••
•
••

••
•
••
•
••
•

••

: I

•
•

•

•
•
•

•

•
•

••
• I •

= Plastic OIL, MP = Miniature Plastic OIL

Two-modulus programmable dividers

8/9

SP8691A
SP8691B
SP8743A
SP8743B

10/11

SP8695A
SP8695B
SP8690A
SP8690B
SP8799A
SP8799
SP8647A
SP8647B
SP8643A
SP8885A
SP8885B
SP8880A
SP8880B

•
•
•
•
•

•
•
•
•

• • •
••
• • •

200
200
500
500
200
200
200
200
200
225
250
250
350
500
500
550
575

•• ••
••
•••
•
••
••

1. The SP8704 is programmable to divide by either 64/65 or 128/129.
C = CMOS output and control input.

21
21
60
60
21
21
21
21
7
7
65
65

65
70
70
111
111

••• •• •••

•
•
••• ••• •••
•• • ••• •
• • •
••• • •••
•• • ••
• • •

••
••

•••
•• • •
••
••
•

•• •

Two-modulus programmable dividers (continued)

1. The SP8704 is programmable to divide by either 64/65 or 128/129.
C = CMOS output and control input.

Frequency synthesisers

NJ8821

Frequency synthesiser, microprocessor interface,
resettable counters

-30 to +70

236

NJ8821B

Frequency synthesiser, microprocessor interface,
resettable counters

-40 to +85

236

NJ8821A

Frequency synthesiser, microprocessor interface,
resettable counters

-55 to +125

241

NJ8822

Frequency synthesiser, microprocessor serial interface,
resettable cou nters
Frequency synthesiser, microprocessor serial interface,
resettable counters

-30 to +70

246

-40 to +85

246

NJ8822A

Frequency synthesiser, microprocessor serial interface,
resettable cou nters

-55 to +125

251

NJ8823

Frequency synthesiser, microprocessor interface,
non-resettable counters

-30 to +70

256

NJ8823B

Frequency synthesiser, microprocessor interface,
non-resettable counters

-40 to +85

256

NJ8824

Frequency synthesiser, microprocessor serial interface,
non-resettable counters
Frequency synthesiser, microprocessor serial interface,
non-resettable counters

-30 to +70

261

-40 to +85

261

Frequency synthesiser, microprocessor serial interface,
for 3V to 5V operation

~30

266

NJ8822B

NJ8824B
NJ882C25

to +70

Product List
High speed dividers
TYPE No.

PAGE

SP8629

150MHz + 100 fixed modulus divider

SP8634B

700MHz + 10 fixed modulus divider

SP8637B

400MHz + 10 fixed modulus divider

SP8647A & B

250M Hz + 10/11 two modulus divider

SP8655A & B

200M Hz + 32 fixed modulus divider

SP8659A & B

200MHz + 16 fixed modulus divider

SP8660A & B

150MHz + 10 fixed modulus divider

SP8668B

1500MHz + 10 fixed modulus divider

SP8678B

1500MHz + 8 fixed modulus divider

SP8680B

600MHz + 10/11 two modulus divider

SP8690A & B

200MHz + 10/11 two modulus divider

101

SP8695A & B

200MHz + 10/11 two modulus divider

106

SP8716/8/9A

520MHz ultra low current two modulus dividers

125

SP8740A
SP8735B

DESCRIPTION

TYPE No.

SP8789

225MHz

SP8793

225MHz + 40/41 two modulus divider

PAGE

20/21 two modulus divider

15:111111111'...

SP8795

5:11 II_if

200MHz

40/41 two modulus divider

225MHz

32/33 two modulus divider

225M Hz

BIBII

lUI]!!' r

10/11 two modulus divider

....

3.3GHz

2 fixed modulus divider

SP8808A

3.3GHz

8 fixed modulus divider

SP8814A & B

2.4GHz + 4 fixed modulus divider

SP8822A & B

1.8GHz

2 fixed modulus divider

SP8832B

3.5GHz

2 fixed modulus divider

SP8838B

3.5GHz + 8 fixed modulus divider

[]lllill

It!

...

..........
2.16• •_

. . . . . . ., ••••.,• • •_

I!dIUIIIIi

Frequency synthesisers
interface)

NJ8822,NJ8822B

SP8850

236

Frequency synthesiser (microprocessor serial interface)
with resettable counters

246

MFNHF synthesiser

277

1.5GHz professional synthesiser

284

Semi-Custom design
For more than a decade Plessey Semiconductors has led and consistently advanced the
state of the art in semi-custom technology.
This leadership has been based on the use of comprehensive design software, Plessey
Design System (PDS). PDS is independent of both technology and function in that Gate
Arrays and cell based designs using CMOS or Bipolar can be developed.
PDS is supported on a DEC VAXNMS based system. However, Plessey supports Daisy,
Valid and Mentor workstations, which are all interfaced into PDS, thereby offering an easy
design route to meet your needs and costs.
These support routes offer the user the maximum flexibility in their design. However,
Plessey also offers a 'turnkey' design function where we will complete the design from start to
finish.
We offer a complete range of CMOS and Bipolar processes to meet all requirements of
speed, power, packing density and cost and a very comprehensive range of through-hole,
surface mount and pin grid array packages.

Gate Array Families
Plessey offers a complete range of Gate Array families, in both CMOS and ECl, for costeffective, fast turn-round projects - see tables below.
ClA 3000 SERIES (CMOS)

ClA 5000 SERIES (CMOS)

• Double layer metal
• 4 micron channel length
• 2.8ns typo gate delay
• 20M Hz system clock
• Fully auto-routed
• 3V to 6V power supply
• Static protected I/O
• Military screening
• >90 % utilization of gates
PRODUCT FAMILY:

• Double layer metal
• 2 micron channel length
• 1.2ns typo gate delay
• 40MHz system clock rate
• Fully auto-routed
• 3V to 6V power supply
• Static protected I/O
• Military screening
• >90% utilization of gates
PRODUCT FAMILY:
I/O
Gales
36
ClA51XX
640
48
CLA52XX
1232
2016
64
CLA53XX
3060
80
CLA54XX
4408
96
CLA55XX
112
CLA56XX
5984
128
CLA57XX
7104
144
ClA58XX
8064
10044
160
ClA59XX

CLA31XX
CLA33XX
CLA35XX

Gales
840
1440
2400

I/O
40
52

Power
4
4
4

ElA 60000 (ECl)
• High performance: 1GHz
• 180ps typo gate speed
• ECL 10K. ECL 100K. TTL and
• CMOS compatible
• Programmable speed/power
• Full military operation
PRODUCT FAMILY:
ELA61 000
ELA62000
ELA63000
ELA65000

Gales
660
1400
2900
4500

Pads
48
68
96
120

Power
4
8

8
8
16
16
16
16
16

Plessey MEGA CELL
PLESSEY MEGACELL
offers the ASIC designer the
opportunity to move to VHSIC
gate complexities without
losing the simplicity of gate
array design methods.
MEGACELL also offers
design freedom and product
innovation through creative
design.

Design Route

Workstation Or Low

Cost Graphics Entry

Cell Library
Four types of library
elements are available giving
functional, dynamic, and
physical design flexibility:
Microcells are modular size
cells of simple logic functions
(gates and flip-flops) similar to
those in current standard
logic families.
Macrocells comprise a
user-library of buildingblocks (e.g. 74 Series TTL)
compiled from Microcells to
speed up design entry.
Paracells are cells which
can be parameterised through
their regular composition
(e.g. ROM, RAM, PLA). The
simple netlist cell code is
auto-compiled into a physical
entity requiring very little
design effort for these types of
cells.
Supracells are large fixedfunction cells pre-designed to
replicate or improve existing
VLSI standard functions.
Many standard products can
be incorporated into the
Supracell concept.

Plessey Software
•
•

Logical Simulation
Timing Verification

•
•

Testability Analysis
Fault Analysis

Para cell Assembly
Module (PAM)
Slllcon Compiler

Megacell Layout Editor (MLE)
•
Plat'cmcnt
•
•

ROlltin,q
Imcnlt't!vc Al.ltoroutil1J.1

•
•
•

Bateh Autol'Outing
On -line ORC/IiRe
User Command Procedures

Ma.kmaklng
" ' - - - ' \ . 1 & Prototype
'--.JII.-----;11 Manufacture

The Quality Concept
Quality cannot be inspected into a product; it is only by careful design and evaluation of
materials, parts and processes (followed by strict control and ongoing assessment) that
quality products will be produced.
All designs conform to standard layout rules, all processes are thoroughly evaluated and all
new piece part designs and suppliers are investigated before authorisation for production
use.
The same basic procedures are used on all products up to and including device packing. It
is only then that extra operations are performed for certain customers in terms of lot
qualification or release procedure.
By working to common procedures all users benefit; the high reliability user gains the
advantage of scale hence improving the confidence factor in the quality achieved, whilst the
volume user gains the benefits of basic high reliability deSign concepts.
Plessey Semiconductors have the following factory approvals:
8S9300 and 8S9400 (BSI Approval No. 1053/M).
CECC50000 and CECC90000 (Reg. No. M/0020/CECC/UK-1053/M).
DEF-STAN 05-21 (DCl Reg. No. 1SB P01).
Plessey Semiconductors conforms to MIL-M-38510F and is qualified to supply to
MIL-STD-883C.

Screening
Different screening procedures are carried out by Plessey Semiconductors Limited, a
brief description of the differences involved are explained in the next few pages.

Internal Visual

Method 2010
Test Condition B 100%

Stabilisation Bake

Method 1008
24 Hrs at Condition C 100%

Temperature Cycling

Method 1010
Test Condition C 100%

Constant Acceleration

Method 2001
Test condition E Y1 only. 100%

Method 2001
Test Condition E Y1 only. 100%

Initial Electrical

Those parameters requiring
Delta calculations. 100%

Burn-In

Method 1015
160 Hrs at 125°C min. 100%

Post Burn-In
Electrical Test

Full Electrical Test to guarantee
Data Sheet. 100%

Those parameters requiring
Delta Calculations. 100%

Method 5005 Class B
Samples as necessary

Visual inspect
chips

Usually 2010
Cond B

2010
Cond B

Assemble

Screen

2010
Cond A

BS9400
1.2.10 Cond B

Includes
100 % bond
pull
None

As list
attached

Method 5004
Class B
Method 5005
Class B
Group A
Group B
Group C
Group 0

Method 5004
Class S

BS9400
1.2.9 Level B

Grou

Group
Group
Group
Group

A
B
C
0

NOTES
1. Visual inspection BS9400 1.2.10 Cond B is equivalent to MIL-STD-883 Method 2010 Cond B.
2. Screening BS9400 1.2.9 Level B is equivalent to MIL-STD-883 Method 5004 Class B EXCEPT it does not include
100% hot and cold test.
3. Conformance testing BS9400 is similar to MIL-STD-883 Class B EXCEPT:
Group A does not necessarily include hot and cold testing.
Group B does include 160 hour operating life test.
Group C does include 2000 hour operating life test and hot and cold testing.
Group 0 only usually includes 8000 hour life test and dimension checks.

MIL-STD-883C Class B Integrated Circuits
Many of the ICs contained in this
Handbook are also available from Plessey
Semiconductors screened to MIL-STD883C Class B. For technical information on
these plus other MIL grade linear and digital
circuits, ask for our MIL-STD-883C Class B
Integrated Circuit Handbook, Publication
No. P.S.2162.

Technical
Data
1. SP8000 Series
High speed
dividers

PLESSEY

Semiconductors ___________________

SP8600A & B
250MHz + 4
The SP8600 is an asynchronous ECl counter with open
collector outputs. It requires external input bias and an AC
coupled input signal of 600mV p-p.

Vee IOV)

CiOcK INPUT"

FEATURES
•

Open Collector Output

•

AC Coupled Input

eMS

Fig.1 Pin connections - bottom view

QUICK REFERENCE DATA

•••
•

Supply Voltage: -S.2V

ABSOLUTE MAXIMUM RATINGS

Power Consumption: 8SmW
Max. Input Frequency: 2S0MHz

Supply voltage
Output voltage (Pins 1 and 3)
Storage temperature range
Max. junction temperature
Max. clock liP voltage

Temperature Range:
-SsoC to +12S oC (A Grade)
-30°C to +70°C (8 Grade)

-10V
VEE +14V

-55°C to +175°C
+175°C
2.5V p-p

Vce(OV)

, - - - - - - - - • ----------,
I
I
CLOCK INPUT 8

CLOCKINPUT

I
I

1 OUTPUT

7rl---L_-,..._..J-----t__,...-_j----13 OUTPUT
I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J

SP8600A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: VEE = -5.2V ± 0.25V Vcc = OV
Temperature: A Grade Tamb = -55°C to +125°C
B Grade Tamb = -30°C to +70°C

Characteristic

Symbol

Value
Min.

Max.

250

Units

Conditions

MHz

Input = 400-800mV

Maximum frequency (sinewave input)

fmax

Minimum frequency (sinewave input)

fmin

MHz

Input = 400-800mV

Power supply current

lEE

VEE = -5.2V

Output current

loUT

1.65

NOTES
1 . Unless otherwise stated the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The dynamic test circuit is shown in Fig. 5.

2000
1800

1800

1400

"'::>a

TAMB

= _55 cC to

+125 c C

*Tested as
specified in
table of
Electrical
Characteristics

1200

.....j
.. ... HL'/ 6UAR~TEE~U11
.,/'"
... !\.,
1000

:Ii

800

~
!

400

OPERATING

WIN~OW

200

100

300

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics of SP8600A

OPERATING NOTES
1. The input is normally AC coupled to one of the inputs or,
if complementary signals are available, to both inputs. The
inputs require an external bias as shown in Fig.5.
2. If no signal is present the device will self-oscillate. If this
is undesirable this can be prevented by offsetting the two
inputs by approximately 40mV as shown in Fig. 6.
3. The outputs are in the form of complementary free
collectors with about 2mA available from them over full
temperature range. The outputs can be interfaced to ECl or
Schottky TTL as shown in Fig. 7.

4. For maximum' frequency operation the output load
resistor values must be such that the output transistors will
not saturate. If the output load resistors are connected to OV
then saturation occurs with resistor values greater than 600
ohms. If only one output is used the other output can be
connected to OV.
5. The input can be operated down to DC but input slew
rate must be better than 20v/~s.
6. The input impedance varies as a function of frequency.
See Fig. 4.

SP8600A & B

Fig.4 Typical input impedance: supply voltage -5.2V, temperature 25° C, frequencies in MHz, impedances normalised to 50 ohms.

~----~--------------~--------~--~----~
51

OUTPUT TO

, _ _ _ _ _ _ _"..._...._ _ _ _ _ _ _ _ _ _ 1111(-5,211)

Fig.5 Test circuit

SP8600A & B

r---~--------------~---------------~

- --:--l
Ok

cLoc~nrt--~-"9'-------'
51

':::'

3 OUTPUT

I
I
I

____ J

,U
'-------------I>----------5.'V
Fig.6 Biasing to prevent oscillation under no signal conditions

,------~>-----.-----~

+------------~---_5.2V

Fig.7 Interfacing to EeL and Schottky TTL

PLESSEY

Semiconductors ___________________

SP8601A & B
150MHz + 4
The SP8601 is an asynchronous ECl counter with a
current steered output which can be used to drive TTL or
CMOS. Biased externally, it may be directly driven from an
ECl II source.

Vee (OVI

ClOcK INPUT"

FEATURES
•

Current steered output can drive TTL or CMOS

•

AC or DC Coupled Input

•

Inputs ECl II Compatible

eM8
QUICK REFERENCE DATA

Fig.1 Pin connections - bottom view

•
•

Supply Voltage: -5.2V
Power Consumption: 85mW

•

Temperature Range:
-55°C to +125°C (A Grade)
-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output voltage (Pins 1 and 3)
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-10V
VEE +14V
-55°C to +150°C

+175°C
2.5V p-p

Vcc(OV)

r
I

-- -

---6·----------,

:,: :1

""'t M

""f M

1: :
I

I
L _____ - -

-~5----

_____ .J

Fig.2 Functional diagram

SP8601A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee ~ OV, VEE ~ -5.2V ± O.25V
Temperature: A Grade Tamb ~ -55°C to +125°C
B Grade Tamb ~ -30°C to +70°C

Characteristics

Symbol

Maximum frequency
(sinewave input)
Minimum frequency
(sinewave input)
Power supply current
Output current

fmax

Value
Min.

1.6

Units

Conditions

MHz

Input

400-800mV p-p

MHz

Input

400-800mV p-p

mA
mA

VEE

150

fmin

lEE
lOUT

Max.

-5.2V

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig. 5.

1,0001-+-+-++-+-+
'E

i:~~~
i~

*Tested as
specified in
table of
Electrical
Characteristics

.~~~~~~~~~~~-=~~~~~~~~

Fig.3 Typical characteristic of SP8601A

Fig.4 Typical input impedance. Test conditions: supply voltage -5.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

SP8601A & B
OPERATING NOTES
1. The signal source can be capacitively coupled to the
clock input if input bias is provided (See Fig.6) but is
normally directly coupled with ECl II levels. The inputs can
be operated either singly or with double complementary
input drive.
2. The outputs are in the form of complementary free
collectors with 1.6mA available from them over full military
temperature range (A grade). The outputs can be interfaced
to ECl or Schottky TTL as shown in Figs. 6 and 7. Interfacing
to TTL at frequencies above 20MHz requires low
capacitance interconnections and the use of Schottky TTL.
3. For maximum frequency operation the output load
resistor values must be such that the output transistors will
not saturate. If the output load resistors are connected to OV
then saturation will occur with resistor values greater than
6000. If only one output is used the other output can be
connected to OV. See Table 1 for typical variation of
maximum input frequency with output load resistor.

Minimum
Output
Voltage (mV)

load
Resistor
(ohms)

Input
Frequency
(MHz)

1100

1000

120

320

200

150

180

Table 1

4. Input impedance is a function of frequency. See FigA.
5. The input can be operated down to DC but input slew
rate must be better than 20V//1s.
6. All components should be suitable for the frequency in
use.

OUTPUTS TO
SAMPLING

OUT
0.1)1
OUTPUT TO
SAMPLING
SCOPE

",-=cr----.__

r--T

SCOPE

~-L__~Y---~~
t---------- v..

Fig.S Test circuit

,.,

750

,--- -

--.![?:.-- -- -I,

,I
I

INPUT--II---+-4-"'<>-------'
1

I
1

1.8k

TTL OUTPUT

1
I,
I

L _____________ ~
5

1O~

Fig.6 Typical application showing interfacing

SP8601A &8

0,1..,

SP8601

...
!eO

L-__~~__Jl---------+~----~ECLO~~T
t----------S.2V

:J,1O"
Fig. 7 Interfacing to EeL

SP8602A & B
SP8604A & B

500MHz -;- 2
300MHz -;- 2

The SP8602 and SP8604 are emitter coupled logic dividers
which feature ECl 10K compatible outputs when used with
external pulldown resistors. The inputs are AC coupled.
/

CLOCK ,NPUT

FEATURES
20

•
•

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

CLOCK INPUT

INTERNAL BIAS DECOUPlING

eMS

QUICK REFERENCE DATA
Fig.1 Pin connections - bottom view

•

Supply Voltage: -5.2V

•

Power Consumption: 85mW

•

Temperature Range:
-55°C to +125°C (A Grade)
-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS
-8V
10mA
-55°C to +175°C
+175°C
2.5V p-p

Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

D'V'~E
I
: __
2'1----I I____J --------r 7

CLOCK INPUT 1

6 OUTPUT

CLOcKINPUT

OUTPUT

L ______ ?_______ --.J
v"

Fig.2 Functional diagram

SP8602J4A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee ~ OV, VEE ~ -5.2V ± O.25V
Temperature: Tamb A Grade ~ -55°C to +125°C
B Grade ~ -30°C to +70°C

Characteristics

Symbol

Maximum frequency
(sinewave input)

fmax

Value
Min.
Max.

Units

Grade

500

MHz

SP8602

300

SP8604
All

} Input

Minimum frequency
(sinewave input)
Power supply current
Output low voltage
Output high voltage
Minimum output swing

fmln

MHz
MHz

lEE

All

-1.4
-0.7

V
V
mV

All
All
All

VOL

VOH
VOUT

-1.8
-0.85
400

Notes

Conditions

~ 400-8oomV

p-p,

Input ~ 400-800mV p-p

VeE ~ 5.2V
Outputs unloaded
VeE ~ -5.2V
Vee ~ -5.2V
Vee ~ -5.2V

Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH ~ +1.63mV 1°C and VOL ~ +O.34mV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at 25°C only.

0
::0

...5
.....

1000

-Tested as
specified in
table of
Electrical
Characteristics

8DO
600

::!

400

::0

200

0
0

100

200

300

400

500

INPUT FReQUENCY (MHz)

Fig.3 Typical characteristic of SP8602 and SP8604

FigA Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

SP8602/4A & B
OPERATING NOTES
3. The circuit will operate down to DC but slew rate must be
better than 100VlJ.ls.
4. The outputs are compatible with ECl II. There is an
internal load of 4k on each output. The outputs can be
interfaced to ECl 10K by addition of a pulldown resistor of
1.5k from the outputs to VEE to increase output voltage swing.
5. Input impedance is a function of frequency. See Fig. 4.
6. All components should be suitable for the frequency in
use.

1. The clock inputs (pins 1 and 2) can be driven singleended or differentially and should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling,
pin 3, to ground.
2. In the absence of a signal the device will self-oscillate.
If this is undesirable it may be prevented by connecting a
15k resistor from the unused input to VEE (ie pin 1 or2 to pin
8). This causes a drop in sensitivity of about 100mV.

TC SAMPLING

SCOPE

FROM GENERATOR

~--~--~~-r

~~--------~~~~~r
INPUT 1

10n

450

~
TO SAMPLING

OUT

FROM GENERATOR
INPUT2

SCOPE

L..~~h-i~

TO SAMPLING

SCOPE

____~10n

3.5k

........--.......---

~------

;;r;, "

...

Fig.S Test circuit

--,
INPUT

I
I

o----j"t----'-Qo----------,

I,
t----
15k

Eel OUTPUT

1.Sk

'.
'-----------1----------1--1--5
...
",rl;
Fig.6 Typical application showing interfacing

PLESSEY _____________________________________
Semiconductors
SP8605A & B 1000MHz
SP8606A & B 1300MHz
The SP86DS and SP86D6 are emitter coupled logic dividers
with ECl III compatible outputs. Specified from -SsoC to
+12SoC (A Grade), these devices feature AC coupled inputs
and 600mV p-p clock input sensitivity.

Ne [ 1

FEATURES

•
•

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

'-.../

'4~ Vee (OV)

NC[ 2

13PNC

Ne [ 3

12PNC

CLOCK INPUT [ 4

'1 ~ OUTPUT

Ne [ 5

10P OUTPUT

INTERNAL BIAS DECOUPLING [ 6

9P Ne

VEE [7

SPNC

DG14

QUICK REFERENCE DATA

•
•
•
•

Supply Voltage: -S.2V
Power Consumption: 320mW
Max. Input Frequency: 1300MHz (SP8606)
Temperature Range:
A Grade: -S5°C to +11 O°C
(125°C with suitable heat sink)
B Grade: O°C to +70°C

Fig.l Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
1SmA
-SSOC to +1SDOC
+17SOC
2.SV p-p

-------T--I
1tt,~~R~S~L~~~

I
I

CLOCK INPUT 4

I
I

J
L

DIVIDE BY

Vee (OV)

1'4

--6---1

I
I

10 OUTPUT

110LifPij"f'

L _______ ?,_______
V"

Fig.2 Functional diagram

I
I

SP8S0S/SA & B
ELECTRICAL CHARACTERISTICS

Supply voltage: Vee = OV, VEE = -5.2V ± 0.25V
Temperature: A Grade Tcase = -55°C to +125°C (Note 2)
B Grade Tamb = O°C to +70°C

Characteristics

Symbol

Value
Min. Max.
1.0
1.3
1.3

Units

Grade

Conditions

Notes

SP8605A,B
SP8606A
SP8606B
All

Input = 400-1200mV p-p
Input = 800-1200mV p-p
Input = 400-1200mV p-p
Input = 600-1200mV p-p

Note 7
Note 7
Note 7
Note 5

VEE = -5.45V
Outputs unloaded
VEE = -5.2V Outputs
loaded with 4300(25°C)
VEE= -5.2V Outputs
loaded with 4300(25°C)
VEE = -5.2V Outputs
loaded with 430 ohms

Note 6

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)
Current consumption

fmin

150

GHz
GHz
GHz
MHz

lEE

100

All

Output low voltage

VOL

-1.92

-1.62

All

Output high voltage

VOH

-0.93

-0.75

All

Minimum output swing

VOUT

500

All

Note 6

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The A grade devices must be used with a heat sink to maintain chip temperature below+175°e when operating in an ambient of+125°e.
3. The temperature coefficients of VOH = +1.2mV I ° e and VOL = + 0.24mV I ° e but these are not tested.
4. The test configuration for dynamic testing is shown in Fig.5.
5. Tested at 25°e and +125°e only (+ 70 0 e for B grade).
6. Tested at 25°e only.
7. Tested at +125°e only (+70 o e for B grade).

~ 1400~~-t--r-1--t~~3--t~--+--r~--t-~~--t-,

!'~~~~~~~~~~~~~~7-~~~t-~~--t-,
E

'Tested as
specified in
table of
Electrical
Characteristics

;; 1000
C

;:
i

400

':'~~;:EE~~~
o
soo
100

200

300

400

600

700

800

900 1000 1100 1200 1300

INPUT FREQUENCY (MHz)

Fig.3 Typical characteristic of SP8606

THERMAL CHARACTERISTICS
(he approximately 30°CIW
approximately 110 °CIW

8JA

OPERATING NOTES
1. The clock inputs (pin 4) should be capacitively
coupled to the signal source. The input signal path is
completed by connecting a capacitor from the internal
bias decoupling, pin 6, to ground.
2. If no signal is present the device will self-oscillate. If
this is undesirable it may be prevented by connecting a
10k resistor from the unused input to VEE (ie pin 4 to pin 7).
This reduces sensitivity by approximately 100mV.
3. The input can be operated at very low frequencies but
slew rate must be better than 200VIJJs.

4. The input impedance of the SP8605/6 is a function of
frequency. See Fig. 4.
5. The emitter follower outputs require external load
resistors. These should not be less than 330 ohms, and a
value of 430 ohms is recommended. Interfacing to ECl
III/10K is shown in Fig. 7.
6. These devices may be used with split supply lines and
earth referenced input using the circuit shown in Fig. 6.
7. All components should be suitable for the frequency in
use.

SP860S/SA & B

Fig.4 Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 2So C, frequencies in MHz,
impedances normalised to SO ohms.

......-

......- - Vee

BOA

SIGNAL
SOURCE

MONITOR

--...,..........- -......0.-.....

VEE

S.2V to.25V

Fig.S Toggle frequency test circuit

+ 3V
1"

I-~OUTPUT

t-c:=:J--t1::=- OUTPUT

VEE

2.2V

Fig.6 Circuit for using the input signal about ground potential

SP8S0S/SA & B

LOW POWER INTERFACING

Fig.7 Interfacing SP860S16 to ECL 10K and ECL III

-------l

r - - - - - - -14
I
I
1n
INPUT

I
I

~_ _oI~l1~--~-~E~O~~

---11---'-0--..---£

I
I

DIVIDE
BY2

.1
,---"O_......j
_ _ _ _ _--+_BIAS

;t'.

I,.
I

_________ J

430

~----------~---~~~~

;r,'.

Fig.8 Typical application showing interfacing

PLESSEY

Semiconductors ___________________

SP8607A & B
600MHz -;- 2
The SP8607 is an emitter coupled logic divider which
features ECl 10K compatible outputs when used with
external pulldown resistors. The inputs are AC coupled.
/

FEATURES
•
•

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

CLOCk INPUT

CLOCK INPUT

INTERNAL BIAS DECOUPUNG

QUICK REFERENCE DATA
•

Supply Voltage: -5.2V

•

Power Consumption: 80mW

•

Temperature Range:
-55°C to +125°C (A Grade)

eMS
Fig.1 Pin connections - bottom view

-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS

-8V

Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

10mA
-55°C to +150°C
+175°C
2.5V p-p

:-------r---6---:
I~EEJ'~~~L~~~

Vee (OV)

I DIVI~E I
21----L____

CLOCK INPUT 1

CL'5CKINPUT

: __

6 OUTPUT

J-----~1 7

L - - - - - _y._______ --.J
V"

Fig.2 Functional diagram

OUTPUT

SP8607A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vcc ~ OV, VEE ~ -5.2V ± 0.25V
Temperature: Tamb A Grade ~ -55°C to +125°C
B Grade ~ -30°C to +70°C

Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current

fmax

Output low voltage
Output high voltage
Minimum output swing

VOL
VOH
VOUT

Value
Min.
Max.
600
40
1S

fmin

lEE
-1.S
-0.S5
400

-1.4
-0.7

Units

Conditions

MHz
MHz
mA

Input ~ 4OQ-SOOmV p-p
Input ~ 4OD-SOOmV p-p
VEE ~ -5.2V

V
V
mV

Outputs unloaded
VEE ~ -5.2V
VEE ~ -5.2V
VEE ~ -5.2V

Notes

Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH ~ +1.63mV 1°C and VOL ~ +O.34mV/oC but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at 25°C only.

1000

800

...--+--+_+--+--+_+-

!~ 800~~~--~~~--~~~~~~~~~~~~~4-~~
:J

:IE

400

200

":J....
;!;

'Tested as
specified in
table of
Electrical
Characteristics

0
0

Fig.3 Typical characteristic of SP8607A

·jl

FigA Typical input impedance. Test conditions: supply voltage -5.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

SP8607A &

OPERATING fllOTES
1. The clock inputs (pins 1 and 2) can be driven singleended or differentially and should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal·bias decoupling,
pin 3, to ground.
2. In the absence of a signal the device will self-oscillate.
If this is undesirable it may be prevented by connecting a
15k resistor from the unused inputto VEE (ie pin 1 or2 to pin
8). This causes a drop in sensitivity of about lOOmV.

3. The circuit will operate down to DC butslew rate must be
better than 1OOV/~s.
4. The outputs are compatible with ECL II. There is an
internal load of 4k on each output. The outputs can be
interfaced to ECL 10K by addition of a pulldown resistor of
1.5k to the outputs to increase the output voltage swing.
5. Input impedance is a function of frequency. See Fig. 4.
6. All components should be suitable for the frequency in
use.

2.7k

+-____

GENERATOR

INNIP~~~~______~__

i~~----~--~~~

____-4~~~~lO'1---0

OUTP\lT

OUT
OUTPUT TO
SAMPLING
SCOPE

450

10n

r---'-----4.____"'"""__J"-T--i-{=::J-I1---o

OUTPUT

3.5k

f'--------o---.......---v"

;;r;,"
Fig.S Test circuit

---,
I

"
o--jt---,-O-----.,

I
I
I.

+----O!--------r-

;::

1400~4--+-~4--+-1--+--+-1--+-e7~
1200

1000

800

600

~4-r-'-'7":L-*....L",'-;;+-7~'-7~-+"'7"Ir--'o;~

*Tested as
specified in
table of
Electrical
Characteristics

4oo~+--+~~~~~~"~~~~~~~~~~

o
'00~~;:l:E~~
o
~

100

_55°C (TCASE)

200

300

400

500

600

700

800

900

1000 '100 1200 1300 1400 1500

INPUT FREOUENCY (MHz)

Fig.3 Typical input characteristics

THERMAL CHARACTERISTICS
(JJC

(jJA

approximately 30°C/W
approximately 110 °C/W

OPERATING NOTES
1. The clock input (pin 4) should be capacitively coupled to
the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
6 to ground.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 10k
resistor from the input to VEE (i.e. Pin 4 to Pin 7). This reduces
sensitivity by approximately 100mV.
3. The input can be operated at very low frequencies but

slew rate must be better than 200V/ jJs.
4. The input impedance of the SP8610/11 is a function of
frequency. See Fig. 4.
5. The emitter follower outputs require external load
resistors. These should not be less than 330 ohms, and a
value of 430 ohms is recommended. Interfacing to ECl
III/10K is shown in Fig. 7.
6. These devices may be used with split supply lines and
ground referenced input by means of the circuit of Fig. 6.

SP8610/11A & B

.j1

Fig.4 Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 2So C, frequencies in MHz, impedances
normalised to SO ohms.

- . . - - . . - - - Vee

.",

SOn.LINE

SIGNAL
SOURCE

'H" ~=
'~

MONITOR

Yu=.5.2: O.25V

Fig.S Toggle frequency test circuit

- - -......- -......-

504
SIGNAl
SOURCE

Vcc~

·3V

,~~

_~==~--~~~4r--~---,

~OUTPl1T

'nt--c:=J--<=..
OUTPUT

_~_-+-

__-4__

VEE - -2.2Y

Fig.B Circuit for using the input signal about earth potential

SP8610111A & B

LOW POWER INTERFACING

Fig.7 Interfacing SP8611 series to ECL 10K and ECL 11/

,. -------l

r------I
I
,.
INPUT--t

1
1

• 1

'--_-<>'II"',_ _ _~_ EeL OUTPUT

t-~I>--I-;~_~
1

400

DIVIDE
BY4

.--_,,<1)-1- _____......._81 ••

:J,'.

I
I
1
I"

7'--------j

430

43'

+------------__- ......_

::r,,.

Fig.8 Typical application showing interfacing

.s.2V

SP8620A & B
400MHz -;- 5
The SP8620 is an asynchronous emitter coupled logic
counter which provides an ECl compatible outpat when an
external pulldown resistor is added. It requires an AC
coupled input of 600mV p-p.

Ne ( 1

FEATURES
•
•

ECl Compatible Output
AC Coupled Inputs (Internal Bias)

'-./

14] Vee (DV)

NC [ 2

JNe

NC [ 3

PINTERNAL BIAS DECOUPLING

OUTPUT [ 4

NC [ 5

NC [ 6

VEE

PNC
PCLOCK INPUT

9P NC
•bNC

QUICK REFERENCE DATA
•
•

Supply Voltage: -5.2V
Power Consumption: 285mW

•

Temperature Range:
-55°C to +125°C (A Grade)

DG14
Fig.l Pin connections - top view

-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
15mA
-55°C to +150°C
+175°C
2.5V p-p

Vcc(OV)

r-------------!l~--------- -----,
I

4 OUTPUT

CLOCK INPUT 10

I
I
_ ________ J

I
L __
12
INTERNAL BIAS

DECOUPLING

Fig.2 Functional diagram

SP8620A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vcc = OV, VEE = -S.2V ± 0.2SV
Temperature: A Grade Tamb = -SsoC to +12SoC
B Grade Tamb = -30°C to +70°C

Characteristics
Maximum frequency
(sinewave input)
Minimum frequency
(sinewave input)
Power supply current
Output low voltage
Output high voltage
Minimum output swing

Symbol
fmax

Value
Min. Max.

Units

400

MHz

Input = 4oo-800mV p-p

MHz

Input = 400-800mV p-p

Note 4

S5
-1.5
-0.7

mA
V
V
mV

VEE = -5.2V
VEE = -S.2V
VEE = -5.2V
VEE = -S.2V

Note 4

fmin

lEE
VOL
VOH
VOUT

-1.8
-0.8S
400

Conditions

Note

(2S°C)
(2S0C)

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH= +1.63mV/oC and VOL= +O.94mV/oC but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at 25°C only.

Ii 1200

I>. 1000

800

r--t-ITAM! =-b.cL +J2S.cl

I I I I i'}
GU~ANTEED
OPERATING

/
~600 H / ' :

~400

~200
i!;

~NDO~

*Tested as
specified in
table of
Electrical
Characteristics

I I I I I I

't-J. 1 I I I
100

200

300

400

500

600

INPUT FREOUENCY (MHz)

Fig.3 Typical input characteristic of SP8620A

FigA Typical input impedance. Test conditions: supply voltage -5.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

SP8620A & B
OPERATING NOTES
1. The clock input (pin 10) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
12, to ground.
2. The circuit will operate down to De but slew rate must be
better than 1OOV /l1s.
3. The outputs are compatible with Eel II. There is an

internal load of 3k at the output. The output can be interfaced
to Eel/10K by the addition of 1.5k to the output to increase
the output voltage swing.
4. Input impedance is a function of frequency. See FigA.
5. All components should be suitable for the frequency in
use.

INPUT FROM
GENERATOR

t - - - - - - - - v..

Fig.5 Test circuit

,------- --------,
14

INPUT

o.---J 1--1r----"'<>--~
1

1
. , _.....-o::4'--.._--

'.2

I
I
I
I
I

INPUT

P~~~~VE

UNREGULATED

9---------,

TRIGGERED

1"'iiiPi:iT 69--------------+-----'

Fig.8 Use of on-chip zener diode for operation from
unregulated supply

rm
Fig.9 Input circuit diagram

OUTPUT
Vee
1

----,

200

I
I

OUTPUT

Fig. 10 Output circuit diagram

PLESSEY __________________________________

s..n~uctDrs

SP8630A & B
600MHz + 10
The SP8630 is an asynchronous emitter coupled logic
counter which provides an ECl compatible output when
used with an external pulldown resistor. It requires an AC
coupled input of 600mV p-p.

NC [ 1

"-'

14
13

Nt [ 3

FEATURES

"p NC

OUTPUT [ 4
NC [ 5

•
•

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

PVee JOY)

PNC
12 PINTERNAL BIAS DECOUPLING

Ne [ 2

PCLOCK INPUT

Ne [ 6

gP Ne

VEE [ 7

.b NC
DG14

QUICK REFERENCE DATA
•
•
•

Fig.l Pin connections - top view

Supply Voltage: -5.2V
Power Consumption: 350mW
Temperature Range:
-55°C to +125°C (A Grade)
-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS

-8V

Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

15mA
-55°C to

+1~,(i°C

+115°C
2.5V p-p

Yoc(oy)

r-------------~-------------~I

I
I

I
I
I

4 OUTPUT

CLOCK INPUT 10

I
I
L - -

INTERNAL alAS
D!COUPLINO

-?,- - I
VEE

Fig.2 Functional diagram

- -

SP8630A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee = OV, VEE = -5.2V ± 0.25V
Temperature: A Grade Tamb = -55°C to +125°C
B Grade Tamb = -30°C to +70°C

Characteristics

Symbol

Maximum frequency
(sinewave input)
Minimum frequency
(sinewave input)
Power supply current
Output low voltage
Output high voltage
Minimum output swing

fmax

Value
Min. Max.

Units

600

MHz

Input

= 4oo-800mV p-p

MHz

Input

= 4oo-800mV p-p

70
-1.5
-0.7

mA
V
V
mV

VEE
VEE
VEE
VEE

fmm

lEE
VOL
VOH
VOUT

-1.8
-0.85
400

Conditions

= -5.2V
= -5.2V
= -5.2V
= -5.2V

Note

Note 4
Note 4

(25°C)
(25°C)

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH = +1.63mV laC and VOL = +O.94mV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.S.
4. Tested at 25°C only.

.
~
.

.5.

1200

1000

*Tested as
specified in
table of
Electrical
Characteristics

BOO

:::>

:IE

600
4DO

:::>
;;!;

2DO

Fig.3 Typical input characteristic of SP8630A

FigA Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

SP8630A & B
OPERATING NOTES
1. The clock input (pin 10) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
12, to ground.
2. The circuit will operate down to DC but slew rate must be
better than 1OOV/I1s.
3. The outputs are compatible with ECl II. There is an

internal load of 3k at output. The output can be interfaced to
ECU10K by the addition of 1.5k to the output to increase the
output voltage swing.
4. Input impedance is a function of frequency. See FigA.
5. All components should be suitable for the frequency in
use.

INPUT FROM
GENERATOR

~-------v

Fig.5 Test circuit

,-------

,.------,

1
1
1

1
1
1
1

INPUTC~

.'-~~o=I4'--.........- - o Eel OUTPUT

15k

400

1.Sk

I
12

'",J;;

I
1

BIAS

1- -

- - -

,- - -

- -

'-------------:~----------L-~5.2V

Fig.6 Typical application showing interfacing

PLESSEY

Semiconductors ___________________

SP86348 SP86358 SP86378
700/600/400MHz

10 (BCD OUTPUTS)

The SP8634/5 and 7 are ECl decade counters with TTL
compatible BCD outputs. They require an AC coupled input
of 600mV p-p and have an ECl 10K compatible inhibit input
which inhibits the device when in the 11igh state. Both ECl
and TTL 'carry' outputs are provided and there is a TTL reset.

INTERNAL BIAS DECOUPlING [ 1
'A' OUTPUT [ 2

RESET [ 3

FEATURES
•

Reset Input TTL Compatible
AC Coupled Input (Internal Bias)

•

TTL and ECl Compatible Carry Outputs

•

16 ] CLOCK INPUT INHIBIT

15] Nt
14 ] CLOCK INPUT

NC [4

13] Nt

VEE [5

12] Vcc(OVl

NC [6

'8' OUTPUT [ 7

'C' OUTPUT [ 8

BCD Outputs TTL Compatible

•
•

\"J

J TIL CARRY OUTPUT

P
P

'0' OUTPUT

Eel CARRY OUTPUT

D616
Flg.l Pm connectIons - top VIew

Clock Inhibit Input ECl Compatible

QUICK REFERENCE DATA
•

Supply Voltage: 5.2V

•

Power Consumption: 400mW

•

Temperature Range: O°C to +70°C

ABSOLUTE MAXIMUM RATINGS
-8V
+11V
-55°C to +150°C
+175°C
2.5V p-p

Supply voltage
BCD outputs voltage
Storage temperature range
Max. junction temperature
Max. clock liP voltage

~~.
INHIBIT
CLOCK INPUT

VEE

'A' OUTPUT
'S' OUTPUT
Vee (OV)
_ _ 2 _ _ _ _ _ _ , _ _ _ 6'~

'C' OUTPUT

'0' OUTPUT
8 ______ " _______ ,

I
I
I
I

I
I
11 TTL CARRY OUTPUT

I
I

"---+-H-----+-----o

I
I

Eel CARRY OUTPUT

RESET 31?---~-+__----_0-------+--------'

L __ --

I
I

---------1,-- -------- _______ -.J

INTERNAL BIAS

DECOUPLING

Fig.2 Functional diagram

SP8634/5178
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vcc ~ OV VEE ~ -5.2V ± 0.25V
Temperature: Tamb ~ O°C to +70°C

Characteristics

Symbol

Maximum frequency
sinewave input

fmax

Minimum frequency
sinewave input
Power supply current
Clock inhibit high
voltage
Clock inhibit low
voltage
TTL output high voltage
(pin 2,7,8,10)
TTL output low voltage
(pin 2,7,8,10)
TTL output voltage (pin 11)

fmin

lEE
VINH

Value
Min. Max.
700
600
400
40
90
-0.96

VINL
VOH

VOH
VOL
tE

-0.9
-1.8

tON

100

VINH
VINL

2.4

Note 7
Note 6

-5.2V (250 C)

VEE

All

0.4

All

-0.7
-1.5
2.5

V
V
ns

All
All
All

10kOfrom TTL
output too +5V
10kOfrom TTL
output to +5V
5kOfrom TTL
output to +5V
5kOfrom TTL
output to +5V
VEE ~ -5.2V (25° C)
VEE ~ -5.2V (250 C)
10% to 90%

All

Note 7

V
V

All
All

Note 6
Note 6

2.4

ECl output high voltage (pin 9)
ECl output low voltage (pin 9)
Edge speed for correct operation
at maximum frequency
Reset on time for correct
operation
Reset input high voltage
Reset input low voltage

} Note 5

All

0.4

VOL

Notes

2.4

TTL output low voltage (pin 11)

Conditions

Grade

MHz SP86348 Input ~ 400-800mV
MHz SP86358 p-p
MHz SP86378
Input ~ 400-800mV
MHz
All
p-p
VEE ~ -5.2V
mA
All
VEE ~ -5.2V (25° C)
V
All

-1.65

VOL
VOH

Units

0.5

Note 6
Note 6
Note 6
Note 6

Note 7

NOTES
1. Unless otherwise stated the elecirical characteristics are guaranteed over full specified supply, frequency and temperature range.
2. The temperature coefficient of VOH (ECl) ~ +1.3mV 10C and VOL ~ +O.5mV 1°C but these are not tested.
3. The temperature coefficient of inhibit threshold voltage ~ +O.24mV 1°C but this is not tested.
4. The test configuration for dynamic testing is shown in Fig.5.
5. Tested at O°C and + 70°C only.
6. Tested at +25°C only.
7. Guaranteed but not tested.

1800,..--,-...,.-,-,.--,-.,..-,-r-.,-.,..-;-r-.,-,

!
!

16001-+-+-+-I-+-+-+--1r-+-+-+--1-t--I

140.1-+--+-+-+ TJ8 ~ lo'c ~ +7!'c +-+--i-I-+--I
12001-+-+-+-I-+-+-+~r-+-+-+--1-t--I

Ev//~////

~~~~~~+-+-+-+-+I-+-+~~~~

o~I~~~~dl~I=~I~~~~~~
o
=
m
~

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics SP8634

*Tested as
specified in
table of
Electrical
Characteristics

SP8634/5/78

Fig.4 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 25°C. Frequencies in MHz, impedances
normalised to 50 ohms.

50~~M "-:!!:::":::J--{="=H

MONITOR

CUT
7

•

O.1:;t
-uv

Fig.S SP86341517 high frequency test circuit

OPERATING NOTES
1. The clock input (pin 14) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
1, to ground.
2. In the absence of a signal the devices will self-oscillate.
This can be prevented by connecting a 6Sk resistor between
the clock input, pin 14, and the negative supply (pin 5).
3. The device will operate down to DC but the input slew
rate must be better than 100V/~s.
4. The Carry O/P is ECL II compatible but can be interfaced
ECL III/10K by the inclusion of two resistors. See Fig. 7.
5. The clock inhibit is compatible with ECL 1II/10K

throughout the temperature range.
6. The output (pins 2, 7, 8, 10 and 11) are current sources
and can be made TTL compatible by addition of 10k and 5k
(pin 11) to +5V. See Fig,6. This gives a fan-out of 1. This can
be increased by buffering the output with a PNP emitter
follower. See Flg.8.
7. The device Is clocked on the positive transition of the
clock input on pin 14, provided that the clock inhibit input
(pin 16) is In the low state. It is important to note that the
positive transition of clock Inhibit must occur while the clock
is in the high state to avoid spurious counting.

SP8634/5/78

------~------------------~----~----~--~~--~--------~r_---

.••

CARRY

RESET

CLOCK

iNHiBiT

TTL OUTPUT

2N5771
CLOCK

__.....____________.....____________.....________________....______...._____•• 2V

Fig.6 Typical application configuration
EeL CARRY OUTPUT ----~----- Eel II COMPATIBLE

}
Uk

- - - -.....------ya (-6.2'1)

Fig.7 EeL 1/1/1 OK interfacing

,------------,
I

...

I
I

I
I
I
I

I
I
I
I
I

L ________ :::v ____ .-J

OUTPUT

TTL

OUTPUT

940 OHMS FOR

'A','B' ,'C' AND 'D' OUTPUTS,

295 OHMS FOR TTL

CARRY OUTPUT

Fig.S TTL output buffering for increased fan-out

SP8634/S/7B
RESET INPUT

~-,IO:.;O-":.c'.c:I::.H_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

CLOCk

:jSEE HorE
e

_~L-__________~

D~
_~__________________~~~_ _ _ __

CARRY OUTPUT (TTL)

CARRY OUTPUT

(ECL)~
_-'-_ _ _ _ _ _ _- - '
NOTE THE BCD OUTPUTS ABC AND

0 REPRESENT THE LOAD RESISTORS

Fig.9 Timing diagram

PLESSEY

Semiconductors __________________

SP8643A
350MHz

10/11

The SP8643 is an ECl variable modulus divider, with ECl
10K compatible outputs. It divides by 10 when either of the
ECl control inputs, 1'E:1 or PE2, is in the high state and by 11
when both are low (or open circuit).
The two clock inputs are interchangeable and either will
act as a clock inhibit when connected to an ECl high level.
Normally, one input is left open circuit and the other is AC
coupled, with externally-applied bias.

CLOCK INPUT 1[ 1

CONTROL INPUT

CONTROL INPun [ 3

FEATURES
•

ECl Compatible Inputs/Outputs

•

AC Coupled Input (External Bias)

18 ] CLOCK INPUT 2

15] Ne
14

JNe

NC [ 4

13 ~ Ne

Vee IOVI [ •

12 JVEE

:J DO NOT CONNECT

NC [ •

NC [ 1

10PNC

OUTPUT [ •

9 P'OUTPUT

DG16
Fig.1 Pm connections - top view

QUICK REFERENCE DATA
•

i[ •

.......,

Supply Voltage: -5.2V

•

Power Consumption: 260mW

•

Temperature Range: -55°C to +125°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
20mA
-55°C to +150°C
+175°C
2.5V p-p

Vcc(OV)

•
------------,
1------------,I
I
!

I
I
I
a

OUTPUT

I
CONTROl. {PEl
INPUTS

;;&'2

I • OUTPUT

2I
3

CLOCK INPUT1

CLOCK INPUT 2 16

?'1---r")--------L---_L___-1
I

L _ ---------------J.--,. -------- - -" ---'
Y..

Fig.2 Functional diagram

SP8643A
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vee ~ OV VEE ~ -S.2V ± 0.2SV
Temperature: Tamb ~ -SsoC to +12SoC
Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
ECl output high voltage
ECl output low voltage
PE input high voltage
PE input low voltage
Clock to ECl output delay
Set-up time
Release time

Value
Min. Max.

3S0

fmax
fmin

lEE
VOH
VOL
V,NH
V,NL
tp
ts
tr

-O.SS
-1.S
-0.93

Conditions

Units

SO
6S
-0.7
-1.S
-1.62
6

2.S
3

MHz
MHz
mA
V
V
V
V
ns
ns
ns

Input
Input
VEE ~
VEE ~
VEE ~
VEE ~
VEE ~

Notes

400-S00mV p-p
400-S00mV p-p
-S.2V
-S.2V (2S°C)
-S.2V (2S°C)
-S.2V (2S°C)
-S.2V (2S°C)
~

Note 6
Note 6
Note 6

NOTES
I. Unless otherwise stated, the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH ~ +1.63mV JOC, VOL ~ +0.94mV jOe and of Y,N ~ +1.22mV jOe but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.6.
4. The set up time ts is defined as minimum time that can elapse between l - H transition of control input and the next l - H clock pulse
transition to ensure that + 10 is obtained.
5. The release time tr is defined as the minimum time that can elapse between H -+ l transition olthe control input and the next l - H clock pulse
transition to ensure that the + 11 mode is obtained.
6. Guaranteed but not tested.

-'"

2000
1800

i'600

TAMB "" -55"C to +125"C

>
.§. 1400
w
~

*Tested as
specified in
table of
Electrical
Characteristics

1200

~'000

BOO

600

I--- I--- /

400

/:
/

GUARANTEED/
/
OPERATING
JIND~W

o
o

/ :1 -

l-.l

100

200

300

400

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristic of SP8643A

TRUTH TABLE FOR
CONTROL INPUTS
PE1

PE2

DiviSion
Ratio

OPERATING NOTES
1. The clock and control inputs are ECl III compatible.
There is an internal pull down resistor to VEE of 4.3k on each
input and therefore any unused input can be left open circuit
when not in use but should be bypassed for RF signals with a
1nF capacitor to ensure maximum noise immunity. If it is
desirable to capacitively couple the signal source to the
clock input then an external bias is required as shown in Fig.
6. The external bias voltage should be -1.3V at 2SoC.

2. The outputs are compatible with ECl II but can be
interfaced to ECl 10K as shown in Fig. 7.
3. The circuit will operate down to DC but slew rate must be
better than 100Vllls.
4. Input impedance is a function of frequency. See Fig. S.
S. All components should be suitable for the frequency in
use.

SP8643A

CLOCK INPUT

-1"r____________________________-j"t!

RIN~T-'~~:

OUTPUT

.-J

L
Fig.4 Timing diagram

.j'

Fig.5 Typical input impedance. Test conditions: supply voltage -5.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

IN4148

r-""""'--I..!...-_""!!!!'-.,~O.'~

INPUT FROM
GENERATOR

01jJ

L____= __.Jr---C=::J---I· ~
TO SAMPLING
SCOPE

'-----"i---------S.2V

Fig.6 Test circuit

OUTPUTS TO
SAMPLING
SCOPE

SP8643A

Eel CONTROL INPUTS
0=+11
1 =+10

PE1

1N4148

PE2

5_ _ _ 2 _

CLOCK INPUT

o--t 1--+-,.-----'<>--"T--1r
47

7.'(0)----+

Eel 10k
OUTPUT

16o--+-.--{
I

7,.

1.Sk

L _______ _ ________ .J
12

~
-+___________
-.4_-<>-__ 5.2V

L - -_ _ _ _ _ _ _ _ _ _ _

Fig.7 Typical application using ECL outputs. NB Voltage at TPI should be -1.3V at 25°C

PLESSEY _____________________________________
Selniconductors
SP8647A & B
250MHz + 10/11
The SP8647 is an ECl variable modulus divider. with ECl
10K and TTL/CMOS compatible outputs. It divides by 10
iNhen either of the ECl control inputs. PE1 or PE2. is in the
high state and by 11 when both are low (or open circuit).
The two clock inputs are interchangeable and either will
act as a clock inhibit when connected to an ECl high level.
Normally, one input is left open circuit and the other is AC
coupled. with externally-applied bias.

CLOCK INPUT 1 [ 1

•

Open Collector TTL/CMOS Output

•

AC Coupled Input (External Bias)

CLOCK INPUT 2

CONTROL INPUTS \""
_1 [[ 2
PE2 3

14P NC

NC [ •

13P NC

Vee fDVI { 5

ECl Compatible Inputs/Outputs

,.
,.

FEATURES
•

\"../

12PVEE

NC [ •

Ne [ 7

10PNC

Eel OUTPUT ( 8

TTL/CMOS OUTPUT

'P Eel Qij'ijijjT
DG16

QUICK REFERENCE DATA
Fig. 1 Pin connections - top view

•

Supply Voltage Vee-VEE: 5.2V ± O.25V

•

Power Consumption: 260mW

•

Temperature Range:
-55°C to +125°C (A Grade)
-30°C to +70°C (B Grade)

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee - VEE
Output current
Storage temperature range
Max. junction temperature
Open collector voltage (Pin 11)
Max. clock liP voltage
Max. open collector current

BV
20mA
-55°C to +150°C
+175°C
+12V
2.5V p-p
15mA

Vee (OY)

•

i-r--r===-~-==-=-=====-I=-==-=-==i=-=-===~---------~" =
CONTROL {

PEl

I
I

8 OUTPUT

I • CiiIiPuT

I
I

CLOCK INPUT 1

I
I

CLOCK INPUT 2

,. I

INPUTS

_
P£2

L _____ -"- _________!______________ J
'2

V..

Fig.2 Functional diagram

SP8647A & B
ELECTRICAL CHARACTERISTICS (ECl OPERATION)
Supply Voltage: Vee ~ OV VEE ~ -5.2V ± 0.25V
Temperature: A Grade Tamb ~ -55"C to +125°C

Characteristic

B Grade Tamb ~ -30°C to +70°C

Value
Min. Max.

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
ECl output high voltage
ECl output low voltage
Clock and PE input high voltage
Clock and PE input low voltage
Clock to ECl output delay
Set-up time
Release time

250

fmax

fmm
lEE
VOH
VOL
V,NH
V,NL
tp

-0.S5
-1.8
-0.93

50
65
-0.7
-1.5
-1.62
6

2.5
3

Is
tr

Conditions

Units
MHz
MHz
mA
V
V
V
V
ns
ns
ns

Input
Input
VEE ~
VEE ~
VEE ~
VEE =
VEE =

Notes

400-S00mV p-p
400-S00mV p-p
-5.2V
-S.2V (25°C)
-5.2V (25°C)
-5.2V (25°C)
-5.2V (25°C)
~

Note 6
Note 6
Note 6

Note 7
Note 7
Note 7

NOTES
1. Unless otherwise stated, the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH = +1.63mV/oC, VOL = +0.94mV 1°C and of V'N= +1.22mV/oC.
3. The test configuration for dynamic testing is shown in Fig.6.
4. The set up time ts is defined as minimum time that can elapse between l - H transition of control input and the next l - H clock pulse
transition to ensure that + lOis obtained.
5. The release time t,js defined as the minimum time that can elapse between H - l transition olthe control ir ,put and the next L- H clock pulse
transition to ensure that the + 11 mode is obtained.
6. SP8647B tested at 25°C only.
7. Guaranteed but not tested.

ELECTRICAL CHARACTERISTICS (TTL OPERATION)
Supply Voltage: Vcc = 5V ± 0.25V VEE = OV
Temperature: A Grade Tamb = -55°C to +125°C B Grade Tamb = -30°C to +70°C

Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
TTL output low voltage

fmax

TTL output high voltage
Clock to TTL output
high delay (positive going)
Clock to TTL output
low delay (negative going)
Set-up time
Release time

VOH
tPLH

Value
Min. Max.
250
50
65
0.5

fmin

lEE
VOL
3.5

tPHL
ts
tr

15
2.5
3

Conditions

Units

Notes

MHz Input = 400-800mV p-p
MHz Input = 400-800mV p-p
mA
V
Vcc = +5.25V
Sink current = SmA
V
Vcc = +S.OV
ns

Note
Note
Note
Note

3
3
3
3, 5

Note 3, 5
Note 4

Note 4

ns
ns

Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.6.
3. SP8647B tested at 25°C only.
4. Guaranteed but not tested.
5. TIL output for use up to 15MHz output frequency. Cload E 5pF.

1200

/"
>

1000

!.
w

1) s L.lclol+l~.C I
I II I I
I

800

::>

t::
~

600

400

::>

200

I- /

~GUARANTEEDY
/
OPERATING
/

WINDOW

1 I I I I

*Tested as
specified in
table of
Electrical
Characteristics

I I I I I I I
100

200

300

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristic of SP8647A

SP8647A & B
CLOCK INPUT

~h~

~b~

-ll

Pi INPUTlL....: _ _ _ _ _ _ _ _ _ _ _ _

OUTPUT

..J

L
Fig.4 Timing diagram

TRUTH TABLE FOR
CONTROL INPUTS

-PE1

PE2

Division
Ratio

Fig.5 Typical input impedance. Test conditions: supply voltage 5V, ambient temperature 25°C, frequencies in MHz,
impedances normalised to 50 ohms.

OPERATING NOTES
1. The clock and control inputs are ECL III compatible.
There is an internal pulldown resistor to VEE of 4.3k on each
input and therefore any unused input can be left open circuit.
If it is desirable to capacitively couple the signal source to the
clock then an external bias is required as shown in Fig. 6. The
external bias voltage should be -1.3V at 25°C.
2. The outputs are compatible with ECL II but can be
interfaced to ECL 10K as shown in Fig. 8.
3. The circuit will operate down to DC but slew rate must be
better than 1OOV I~s.
4. Input impedance is a function of frequency. See Fig. 5.

The TTL/CMOS OIP is a free collector, with an output

riselfall time which is a function of load resistance and load

capacitance. The load capacitance should therefore be kept
to a minimum and the load resistance should not be too small
otherwise VOL will be too great. eg TTL output current = 8mA
VOL = 0.5V. For CMOS outputs, the value of load resistor
should be the maximum consistent with satisfactory rise
times.
6. All components should be suitable for the frequency in
use.

SP8647A & B

1N4148

r-.....L.:-.....,~----'--.!!!!....,~01~

INPUT FROM

GENERATOR

0.1)1

L_......",..._J'---{=:::Jr-il---c=-

OUTPUTS TO
SAMPLING

SCOPE

10 SAMPLING

SCOPE

'-----1----------5.2Y

Fig.6 Test circuit

TTL CONTROL INPUTS
0= ...11
1 =+10

1-----------~---~-~-------------~~-·5V
IN4148

680

------,

,-----

I
,1

10n

680

o--J I---r-~--'<----o--£
I

~-+--[

TTL
OUTPUT

1
160-

TP1

750

1
1

L _______ ~~~-------

___ J

'--------------------------~~-------------------------------~
Fig.7 Typical application showing interfacing. NB Voltage at TPl should be 3.7V at 25°

a OR

+----0

Eel OUTPUT

~15k
--_~--

__'.2V

Fig.S Interfacing to EeL 10K

PLESSEY

Semiconductors __________________

SP8650A & B
600MHz + 16
The SP8650 is an asynchronous emitter coupled logic
counter which provides ECl 10K compatible outputs when
external pulldown resistors are added. It requires an AC
coupled input of 600mV p-p.

OUTPUT [ 1

FEATURES
•
•

'-"

l3P Ne

NC [3

OUTPUT [ 4
NC [5

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

14P Vee IDYl

Ne [2

Ne [.
VEE [7

PINTERNAL BIAS DECOUPUNG

PNC
lOP CLO'CiINPUT
11

9P NC
PCLOCK INPUT

OG14

QUICK REFERENCE DATA
•
•

Supply Voltage: -5.2V
Power Consumption: 300mW

•

Temperature Range:
-55°C to +125°C (A Grade)
-30°C to +70°C (B Grade)

Flg.l Pm connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
10mA
-55°C to +150°C
+175°C
2.5V p-p

Vcc(OV)

1_ - - - - - - - - - ___ !'~ _____ I
CLOCK INPUT

I
I

1 OUTPUT

I
10

1
4 OUTPUT

I
I
I

L_-;-..:~~:.:DECOUPLING

----- - - -1'-- - ---- - - - - __ -.J
Yu

Fig.2 Functional diagram

--I
I

I
I

CLOCK INPUT

---- -

SP8650A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vcc = OV, VEE = -5.2V ± 0.25V
Temperature: A Grade Tamb = -55°C to +125°C
B Grade Tamb = -30°C to +70°C

Characteristics

Symbol

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)

fmm

Value
Min. Max.

Units

600

MHz

Input

= 400-800mV

MHz

Input

= 400-800mV p-p

-1.8

60
-1.5

mA
V

-0.85

-0.7

lEE

Power supply current
Output low voltage

VOL
VOH

Output high voltage

Notes

Conditions

p-p
Note 4
Note 4

= -5.2V
VEE = -5.2V
VEE

(25°C)
(25°C)

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH = +1.63mV 1°C and VOL = +O.94mV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at 25° only.

W
Q

1200
1000

*Tested as
specified in
table of
Electrical
Characteristicti

800

600

:IE 400

"....
"1!;

200

Fig.3 Typical input characteristic of SP8650A

Fig.4 Typical input impedance: Test conditions: supply voltage -5.2V, ambient temperature 25° C, frequencies in MHz,
normalised to 50 ohms.

SP8650A & B
OPERATING NOTES
1. The clock inputs (pins 8 and 10) can be driven singleended or differentially and should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling.
pin 12. to ground.
2. If no signal is present the device will self-oscillate. If
this is undesirable it may be prevented by connecting a
10k resistor from one of the inputs to VEE. This will reduce
the input sensitivity by approximately 100mV.

3. The circuit will operate down to DC but slew rate must be
better than 100Vll1s.
4. The outputs are compatible with ECl II. There is an
internal load of 4k at each output. The output can be
interfaced to ECl 10K by addition of two resistors.
5. Input impedance is a function of frequency. See Fig. 4.
6. All components should be suitable for the frequency in
use.

.,.

r----·'~4---,~_1::~r_~1On~OUTPUTTO

10n
INPUT FROM

GENERATOR

OUT

L_-r;-_.r--C:450=r_-i10~

SAMPLING

SCOPE

~-------vu

Fig.S Test circuit

I
in

INPUT

8 1

o---J I----"c>--------,

I
I
I,
DIVIDE BY
16

10k

o--+---o''--+4:-::-:~-o Eel OUTPUT

'00

"------------1----------.J---L-S.2V

Fig.6 Typical application showing interfacing

PIN10R4-

147

+----<>

Eel OUTPUT

~"5k
- -.......----5...
Fig.7 Interfacing to EeL 10K

SP8655A & B 200MHz + 32
SP8657A & B 200MHz + 20
SP8659A & B 200MHz + 16
The SP8655, 57 and 59 are low power emitter coupled logic
counters with open collector outputs capable of driving TTL
or CMOS. They are available in two temperature ranges: 55°C to +125°C (A grade) and -30°C to +70°C (8 grade). It
has internally biased inputs.

CLOCK INPUT

-Vee

FEATURES
•
•
•

AC Coupled Inputs
Low Power Consumption
Open Collector Output CMOS and TIL Compatible

OUTPUT

eMS

Fig.l Pin connections - bottom view

QUICK REFERENCE DATA

ABSOLUTE MAXIMUM RATINGS

•
•

Supply Voltage: 5.0V
Powel Consumption: 50mW

•

Temperature Range:
-55°C to +125°C (A Grade)

Supply voltage
Open collector output voltage
Storage temperature range
Max. junction temperature
Max. clock liP voltage
Output sink current

-30°C to +70°C (8 Grade)

8V
12V
-55°C to +150°C
+175°C
2.5V p-p
10mA

,-------------------------,
I
I
I

7' v"
I

--CKINPUT

5 V££(OVI

8L __________ _

1- - - -

SP8655A & 8 _ _ _ _ _ _ _ _ _ _ _

-I,-=-=-::::;l- - - - - - - ,...--]------------,- - -

-1'
14

OUTPUT

I
I
~5

CLOCK INPUT 1 0 - - - - - '

CLOCK INPUT 'o-~----'
1-----

SP8657A
B _ _ _ _ _ _ _ _ _.
________
_ _& _

,-------------I

Ir===~

-.J
l ?2 Vee

\-------<>4

CLOCK INPUT 1

CLOCKINPUT

I
65

'I-"':'" _ _ _ _ _ _ _ _ _ _SP8659A&B

___________

Vn(OV)

OUTPUT

VEE(OV)

Fig.2 Functional diagram

SP86ssn/9A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vcc ; S.OV ± O.2SV VeE; OV
Temperature: A grade Tamb; -55°C to +12SoC
B grade T amb ; -30°C to +70°C

Characteristic

Value

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output high voltage

lEE
VOH

Output low voltage

VOL

Min.

fmax

MHz Input =400 - 800m V
MHz Input =400 - 800m V
mA Vcc= S.2SV
Vcc= SV Note 4
V
Pin 4 = 1.SkO to 10V
mV Vcc = SV
Pin 4 = 1.SkO to 10V

200
40
13

fmin

Conditions

Units

Max.

7.S
400

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The dynamic test circuit is shown in Fig.S.
3. Above characteristics are not tested at 25°C (tested at low and high temperature only).
4. Open collector output not to be used above 15MHz. Cioad .,. 5pF.

1800

f
!.

1600

T.... '" -5S°C ... "'125°C

1400

*Tested as
specified in
table of
Electrical
Characteristics

1200

~ 1000

...

tj // ~
/

600
400

...
D

-- .

GUARANTEEDY
/
OPERATING
WINDOW

I
100

150

2IID

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics

OPERATING NOTES
1. The clock inputs (pin 1 and 8) should be capacitively
coupled to the signal source. When driven single-ended, the
input signal path is completed by connecting a capacitor
from the unused input to ground.
2. In the absence of a signal the devices will self-oscillate.
This can be prevented by connecting a 39k resistor from
either input to ground. If the device is driven single ended, it
is recommended that the pulldown resistor be connected to
the decoupled unused input. There will be a loss in sensitivity
of approximately 2OOmV.
3. The device will operate down to DC but the input slew
rate must be better than 1ooVl~s.
4. The open collector output will drive 3 TTL loads, and
thus requires a suitable resistor to Vcc to maintain noise

immunity. In order to ensure noise immunity on transitions,
this resistor should not exceed 4.7k. For interfacing to
CMOS, the open collector may be restored to a +10V line via
a 3.3k resistor. The output sink current must not exceed
10mA. and the use of too Iowa value of resistor may lead to a
loss of noise immunity. especially at low temperatures.
5. Input impedance is a function of frequency. See Fig. 4.
6. The rise time of the open collector output waveform is
directly proportional to the load capacitance and load
resistor value. Therefore the load capacitance should be
minimised and the load resistor kept to a minimum
compatible with system power requirements. In the test
configuration of Fig. 5. the output rise time is approximately
20ns and fall time is typically 10ns.

SP865517/9A & B

Fig.4 Typical input impedance. Test conditions: supply voltage 5.0V, ambient temperature 25° C, frequencies in MHz, impedances
normalised to 50 ohms.

:J--i

QlNIRATOII'
--'ROM

1k'"

r---t--C=J--i~ o.:~.::a

TOIOA

IAMIIIJNG . . - ICOPI

Flg.5 Test circuit

,_____;gl-.e ---,
,.

---I

8P8855/7/1

(DEPENDING ON
CMOS SUPPLY VOLTAGE)

...--<:>---+-_ CMOS

.1
3Ik

5110V

,I'.

L-----

BI,.

1----

I
_...J

Fig.6 Typical application showing interfacing

SP865517/9A & B

Fig.7 Interfacing to TTL. Load not to exceed 3 TTL unit loads.

PLESSEY

Semiconductors ___________________

SP8660
150MHz

The SP8660 is a low power emitter coupled logic counter
with an open collector output capable of driving TTL or
CMOS. It has internally biased inputs and an open collector.

CLOCK INPUT

FEATURES

'-'

8 ~ CLOCK INPUT

Vee

7PNC

6pNC

OUTPUT

PVEE !OVj
DPB

•

AC Coupled Inputs

•
•

Low Power Consumption
Open Collector Output CMOS and TTL Compatible

Fig. 1 Pin connections - top view

QUICK REFERENCE DATA
•

Supply Voltage: S.OV

•

Power Consumption: SOmW

•

Temperature Range: -30°C to +70°C

•

8 Lead Plastic Package

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Open collector output voltage
Storage temperature range
Max. junction temperature
Output si nk current
Max. clock liP voltage

12V
-55°C to +125°C
+175°C
10mA

2.5V p-p

v'"

~----------J-----------l
I
I
I

4 OUTPUT

I
CLOCK INPUT , , ' - - - - '

CiOCK INPUT

L ___________ , - - - - - ______ JI
VEE(OV)

"
Fig.2 Functional diagram

SP8660
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee = S.OV ± 0.2SV VEE = OV
Temperature' Tomb =-30°C to +70°C
Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output high voltage

fmax

lee
VOH

Output low voltage

VOL

Value
Min.
Max.

Units

150

fmin

40
13

MHz
MHz
mA
V

400

Conditions
Input =2oo-10oomV
Input =400-1000mV
Vee =S.2SV
Vee =SV
Pin 4
1.Skn to 10V
Vee
SV
Pin 4
1.Skn to 10V

=
=

Notes

Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristios shown above are guaranteed over speolfled supply, frequency and temperature range.
2. The dynamic test Circuit Is shown in Fig,S,
3. All characteristics above are tested at 25°C only.
4. Cload 4ii SpF.

,...

TAMI" ·.~c 1M .70QC

~~~
/7
VjOPIRATING

40CI

...
••

*Tested as
specified In
table of
Electrical
Characteristics

'10

INPUT PRIQUINCY (MHo)

Fig,3 Typical input characteristics

Fig.4 Typical input impedance. Test conditions: supply voltage 5.0V, ambient temperature 25° C, frequencies in MHz, impedances
normalised to 50 ohms

SP8660
OPERATING NOTES
1. The clock inputs (pin 1 and 8) should be capacitively
coupled to the signal source. When driven single-ended. the
input signal path is completed by connecting a capacitor
from the unused input to ground.
2. In the absence of a signal the devices will self-oscillate.
This can be prevented by connecting a 39k resistor from
either input to ground. If the device is driven single ended, it
is recommended that the pulldown resistor be connected to
the decoupled unused input. There will be a loss in sensitivity
of approximately 200mV.
3. The device will operate down to DC but the input slew
rate must be better than 1OOV/j.Js.
4. The open collector output will drive 3 TTL loads, and
thus requires a suitable resistor to Vcc to maintain noise

immunity. In order to ensure noise immunity on transitions,
this resistor should not exceed 4.7k. For interfacing to
CMOS, the open collector may be returned to a +1 OV line via
a 3.3k resistor. The output sink current must not exceed
10mA, and the use of too Iowa value of resistor may lead to a
loss of noise immunity, especially at low temperatures.
5. Input impedance is a function of frequency. See FigA.
6. The rise time of the open collector output waveform is
directly proportional to the load capacitance and load
resistor value. Therefore the load capacitance shou Id be
minimised and the load resistor kept to a minimum
compatible with system power requirements. In tile test
configuration of Fig. 5, the output rise time is approximately
20ns and fall time is 10ns typically.

FROM~,.

GENERATOR

t-'--+--r--t._--.J-t

TOSO.n.
SAMPLING _

t-- S:~~

SCOPE

Fig.S Test circuit

·5V

i -----~
~'lc- - - -~1,1 5I'·::Mci~~':."::'~~O~~AGEI
,.
----i

SP8680

•

"
I

,
L - - - - -

.,AS

-:1--- - -

CMOS

I
I
~

Fig.6 Typical application showing interfacing

----------nm

--.---5V

1"4'-__~+--_ _:_TT_L_. .

SP86601

Fig.7 Interfacing to TTL. Load not to exceed 3 TTL unit loads.

PLESSEY

Semiconductors ___________________

SP8660A & B
150MHz + 10
The SP8660A/8 is a low power emitter coupled logic
counter with an open collector output capable of driving TTL
or CMOS. The device is available in two temperature ranges:
-55°C to +125°C (A grade) or -30°C to +70°C (8 grade). It
has internally biased inputs.

CLOCK INPUT

FEATURES
•

AC Coupled Inputs

•
•

Low Power Consumption
Open Collector Output CMOS and TIL Compatible

OUTPUT

eM8

Fig. 1 Pin connections - bottom view

QUICK REFERENCE DATA
•

Supply Voltage: 5.0V

•

Power Consumption: 50mW

•

Temperature Range:
-55°C to +125°C (SP8660A)
-30°C to +70°C (SP8660B)

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Open collector output voltage
Storage temperature range
Max. junction temperature
Output sink current
Max. clock liP voltage

8V
12V
-55°C to +150°C
+175°C
10mA
2.5V p-p

r----------J----------- l

I
I

ClOCK INPUT 1

Ci:Oci( INPUT "

4 OUTPUT

I
I

L - - - - - - - - -

-1'- - - - - - - - - - Va(OV)

Fig.2 Functional diagram

I
j

SP8660A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vce = 5.0V ± 0.25V VEE = OV
Temperature: A grade Tamb = -55°C to +125°C
B grade Tamb = -30°C to +70°C

Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output high voltage

lEE
VOH

Output low voltage

VOL

Value
Min.
Max.

Units

Conditions

40
13

MHz
MHz
mA
V

400

Input =400 - 800mV
Input =400 - 800mV
Vcc= 5.25V
Vcc= 5V
Pin 4 = 1.5kO to 10V
Vcc = 5V
Pin 4 = 1.5kO to 10V

150

fmax
fmin

7.5

Notes

Note 4

NOTES
1. Unless otherwise stated the .electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The dynamic test circuit is stIown in Fig.5.
3. Above characteristics are not tested at 25°C (tested at low and high temperature only).
4. Cload ~5pF.

1800
TAM.

·30"C and +70"C

0G~Ako0

*Tested as
specified in
table of
Electrical
Characteristics

OPERATING
/WINOOW

150

100

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristic of SP8660A

OPERATING NOTES
1. The clock inputs (pin 1 and 8) should be capacitively
coupled to the signal source. When driven single-ended, the
input signal path is completed by connecting a capacitor
from the unused input to ground.
2. In the absence of a signal the devices will self-oscillate.
This can be prevented by connecting a 39k resistor from
either input to ground. If the device is driven single ended, it
is recommended that the pulldown resistor be connected to
the decoupled unused input. There will be a loss in sensitivity
of approximately 200mV.
3. The device will operate down to DC but the input slew
rate must be better than 100V/jJs.
4. The open collector output will drive 3 TIL loads, and
thus requires a suitable resistor to Vcc to maintain noise

immunity. In order to ensure noise immunity on transitions,
this resistor should not exceed 4.7k. For interfacing to
CMOS, the open collector may be restored to a +10V line via
a 3.3k resistor. The output sink current must not exceed
10mA, and the use of too Iowa value of resistor may lead to a
loss of noise immunity, especially at low temperatures.
5. Input impedance is a function of frequency. See Fig. 4.
6. The rise time of the open collector output waveform is
directly proportional to the load capacitance and load
resistor value. Therefore the load capacitance should be
minimised and the load re.3istor kept to a minimum
compatible with system po'ver requirements. In the test
configuration of Fig. 5, the o~tput rise time is approximately
20ns and fall time is 10ns typically.

SP8660A & B

.j'

Fig.4 Typical input impedance. Test conditions: supply voltage 5.0V, ambient temperature 25°C, frequencies in MHz. impedances
normalised to 50 ohms.

FROM~,.

GENERATOR

SCOPE

Fig.S Test circuit

L-_ _ _ _-I==}-~-.,AS

I
L
____ _

r--"-'T--L_J--tl---- ~';:G

TOSOn

SAMPLING _

Fig.6 Typical application showing interfacing

SP8660A & B

I
SP8660

I-

~"2k

TIL

Fig. 7 Interfacing to TTL. Load not to exceed 3 TTL unit loads.

PLESSEY

Semiconductors ___________________

SP8665B 1000MHz + 10
SP8668B 1500MHz + 10
The SP8665/8 are asynchronous ECl counters which
provide ECl compatible outputs. They feature an ECl
compatible input inhibit which simplifies the design of
frequency counters and other instrumentation.

FEATURES

•
•
•

OUTPUT

ECl Compatible Output
AC Coupled Input
Clock Inhibit Input

INTERNAL BIAS DECOUPUNG

CLOCK INPUT

CLOCK INHIBIT

'--------'

DG14
QUICK REFERENCE DATA

•
•
•

Fig.1 Pin connections - top view

Supply Voltage: -6.8V
Power Consumption: 500mW
Temperature Range: O°C to +70°C

ABSOLUTE MAXIMUM RATINGS

-8V

Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

20mA

-55°C to +150°C
+175°C
2.5V p-p

INTERNAL

Ycc(OV)

BIAS DECOUPLING

1- -

- - - - - - - - - M

I
I
I
I
I
CLOCK INPUT 1001

CLOCKINHIBIT8

----'

L ______ - - _

-1'- _____ - - ___ ...1
v"

Fig.2 Functional diagram

SP866S/8B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee = OV VEE = -S.BV ± 0.3V
Tamb (8 grade) = O°C to +70°C

Characteristic

Symbol

Maximum frequency(sine wave liP)

fmax

Minimum frequency(sine wave liP)
Current consumption
Output low voltage
Output high voltage
Minimum output swing

Value
Min. Max.
1.0
1.S

fmin

lEE

Clock inhibit high threshold voltage
Clock inhibit low threshold voltage

-1.B7
-0.B7

VOL
VOH
VOUT
V,NBH
V,NBl

1S0
105
-1.S
-0.7

500
-0.96
-1.S2

Units

Grade

GHz
GHz
MHz
mA
V
V
mV
V
V

SP86658
SPB66B8
All
All
All
All
All
All
All

Notes

Conditions
Input
Input
Input
VEE =
VEE =
VEE =

= 4OD-1200mVp-p
= 6OD-1200mVp-p
= 600-1200mVp-p
-S.BV
-S.BV (2S0 C)
-S.BV (2S0 C)

Note S
Note S
NoteS
NoteS

NoteS
VEE = -S.BV (25° C)
VEE = -S.BV (25° C)

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.S.
3. The temperature coefficient of VOH = + 1.3mV 1°C and VOL = +O.5mV 1°C but these are not tested.
4. The temperature coefficient of VINB = +O.BmV 1°C but this is not tested.
5. Tested at 25°C and 70°C only.
6. Tested at 2Soe only.
'''D~+--+-+-+-+-TAMB ==O°Cto +70~C

--1-+--+--+-+---1

f
i 1~~~~~~~~~~~~~~~~-~~~~~
1400

r:
~

600

*Tested as
specified in
table of
Electrical
Characteristics

~ 4OO~~-+-~~~~~~-r~~~-r~-+-~-4~

2DDDI:l:f:EfHfHE::J:TI
o

100·

200

300

400

500

600

700

800

900 1000 1100 1200 1300 1400 1SOD

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristic SP8668. The SP8665 operating window is similar except for the maximum operating frequency

CLOCK
INPUT

, - - - -_ _ _ _ -D.96V

;.-_ _ _ _ _ _ _ _ _ _ ".75V
OUTPUT------------I

-1.BOY

Fig.4 Timing diagram(N.B. output waveform is asymmetric)

SP8665/8B
OPERATING NOTES
1. The clock input (pin 10) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
12, to ground.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from the input to VEE (i.e. Pin 10 to Pin 7). This will
reduce the input sensitivity by approximately 100mV.
3. The clock inhibit input is compatible with standard ECL
III/10K using a common OV. A 6k pulldown resistor is
included on the chip. The input should be left open to DC

when not in use, but should be bypassed for RF s' .... nals with a
1nF capacitor to ensure maximum noise immunity.
4. Input impedance is a function of frequency. See Fig. 5.
5. The emitter follower output includes an internal 3k
pulldown resistor and is compatible with ECL II, but can be
interfaced with ECL III/10K by the inclusion of two resistors.
See Fig. 7.
.
6. Note that all components should be suitable for the
frequency in use.
7. The circuit will operate to DC but the input slew rate must
be 200VlIJs or greater.

Fig.5 Typioal input impedance. Test conditions: supply voltage -6.8V, ambient temperature 25° C, frequencies in MHz, impedances
normalised to 50 ohms.

TO 10",
SAMPLING
SCOPE

SAMPLlNQ

ICOPI!
Uk

- -....- -_ _ _ v..

Fig.6 Test circuit

---"'II-!:P~IN.!.'-{~="::J---t---O EeL

10K lIP

SP86&5/B

U,·4k
- -....- v..

...

p.-,-C=:J--i t-:-i:=.

Fig. 7 SP8665/8 to fECL 10K interface

SPS66S/SB

-1 ..........--"'<>----<.-(
'"

10 1

2.4k
15k

;;r;

L ____ _
7

L -_ _ _ _ _ _ _ _ _ _---..--+-'""-_
_ _ _ _ _ _ _+_ -6.BV
V"

Fig.B Typical application showing interfacing

PLESSEY ______________________________________
Selniconductors
SP8670A & B
600MHz + 8
The SP8670 is an asynchronous emitter coupled logic
counter which provides ECl 10K compatible outputs when
external pulldown resistors are added. It requires an AC
coupled input of 600mV p-p.

FEATURES
•
•

'-./

OUTPUT [ ,

Vee (OV)

Nt [ 2

Ne [ 3

INTERNAL BIAS DECOUPLlHG

OUTPUT [

ECl Compatible Outputs
AC Coupled Inputs (Internal Bias)

11 JNC

Nt [ 5

Ne [ 6

VEE [ 7

CLOCK INPUT
NC

1CLOCK INPUT

QUICK REFERENCE DATA

OG14

•

Supply Voltage: -5.2V

•

Power Consumption: 300mW

•

Temperature Range:
-55°C to +125°C (A Grade)
-30°C to + lO°C (B Grade)

Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
10mA
-55°C to +150°C
+175°C
2.5V p-p

Vee (OV)

,- - - - - - - - - - J'~ - - - - - - - - - -

:---1

CLOCK INPUT 8

CLOCK INPUT

DIVIDE BY

L __

DIVIDE BY

2
Q

1 OUTPUT

I
I

I
1

- - - - - - - - - - _ _ _ _ _ _1

12
INTERNAL BIAS
DECOUPUNG

Fig.2 Functional diagram

SP8670A & B
ELECTRICAL CHARACTERISTICS
Supply voltage: Vee = OV, VEE = -5.2V ± 0.25V
Temperature: A Grade Tamb = -55°C to +125°C
B Grade Tamb = -30°C to +70°C

Characteristics

Maximum frequency
(sinewave input)
Minimum frequency
(sinewave input)
Power supply current
Output low voltage
Output high voltage
Minimum output swing

Symbol
fmax

Value
Min.
Max.

Units

600

MHz

Input = 400-S00mV p-p

MHz

Input = 400-S00mV p-p

Note 4

60
-1.5
-0.7

mA
V
V
mV

VEE= -5.2V
VEE = -5.2V (25° C)
VEt'. = -5.2V (250 C)
VEE = -5.2V

Note 4

fmln

lEE
VOL
VOH
VOUT

-1.S
-0.S5
500

Notes

Conditions

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of Voo = +1.63mV 1°C and VOL = +O.94mV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at 25°C only.

*Tested as
specified in
table of
Electrical
Characteristics

Fig.3 Typical input characteristic of SP8670A

Fig.4 Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 2SoC, frequencies in MHz.
normalised to SO ohms.

SP8670A & B
OPERATING NOTES
3. The circuit will .operate dawn ta DC but slew rate must be
better than 1OOVljJs.
4. The .outputs are campatible with ECl II. There is an
internal laad .of 4k at each .output. The .output can be
interfaced ta ECl 10K by additian .of twa resistars.
5. Input impedance is shawn in Fig. 4.
6. All campanents shauld be suitable far the frequency in
use.

1. The clack inputs (pins 8 and 10) can be driven singleended .or differentially and shauld be capacitively caupled
ta the signal Saurce. The input signal path is campleted by
cannecting a capacitar fram the internal bias decaupling,
pin 12, ta graund.
2. If na signal is present the device will self-oscillate. If
this is undesirable it may be prevented by cannecting a
10k resistar fram .one .of the inputs ta VEE. This will reduce
the input sensitivity by approximately 100mV.

~~--

~~JR~~'6~ ----

______~i~__~r---~~--~__~~==J--i'O'~
L __-r;-__.r----L:=:J--;10~
~-------------

OUTPUT TO
SAMPLING

SCOPE

Fig.5 rest circuit

--,
1n

INPUT

8 1

o-----J 1----"0-----------..,

I
I
I,
~--+---<>"--+_L

__h--o Eel OUTPUT
Uk

L----------------------t-__________________-1______L

;;;;, ,.

Fig.6 Typical applicatian shawing interfacing

PIN10R4~

+----0

Eel OUTPUT

-----+------S.2V

Fig. 7 Interfacing to EeL 10K

-S.2V

PLESSEY

SMnlcanduclors ___________________________________

SP8678B
1500MHz + 8
The SP8678B is an asynchronous ECL counter which
provides ECL compatible outputs. It features an ECL
compatible input inhibit which simplifies the design of
frequency counters and other instrumentation.

Ne [ 1

'-"

Ne [ 3

FEATURES
•
•
•

11] Ne

OUTPUT [ 4

Ne [ 5

ECl Compatible Output
AC Coupled Input
Clock Inhibit Input

Vee (OV)

JNe
" PINTERNAL BIAS DECDUPLING

NC [ 2

CLDCK INPUT

NC [ •

•

VIE [ 7

CLOCk INHIBIT

DG14
QUICK REFERENCE DATA
Fig. 1 Pin connections - top view

•

Supply Voltage: -6.BV

•
•

Power Consumption: 475mW
Temperature Range: O°C to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
20mA
-55°C to +150°C
+175°C
2.5V p-p

Vcc(OV)

,----------k----------,
I
I
INTERNAL
BIAS DECOUPLING 12

I•
I

OUTPUT

I _~::rl---'

CLOCK INPUT 10

CLOCK INHIBIT 8

I
I

L----------f----------~
v..

Fig.2 Functional diagram

SP8678B
ELECTRICAL CHARACTERISTICS
Supply lIoltage: Vcc = OV Vee = -6.8V ± 0.3V
Tamb (8 grade) = O°C to +70°C

Characteristic

Value
Min.
Max.

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Current consumption
Output low voltage
Output high I(oltage
Minimum oytput swing
Clock inhibit high threshold voltage
Clock Inhibit low threshold voltage

fmax

1.5
150

fmin

lee
Val
VOH
VOUT
V,NBH
V,NBl

-1.87
-0.87
500
-0.96

-1.5
-0.7

-1.S2

Conditions

Units
GHz
MHz
mA
V
V
mV
V
V

Input =600 - 1200mV p-p
Input =600 - 1200mV p-p
VEE= -6.8V
VEE= -S.8V(25°C)
VEe= -S.8V(25°C)

Notes
Note 5
Note 6
Note 6

Note 5
VEE= -S.8V(25°C)
Vee= -S.8V(25°C)

NOTES
1. Unless otherwise stated, the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig. 6.
3. The temperature coefficient of VOH= +1.3mV/oe and VOL= +0.5mV/oe but these are not tested.
4. The temperature coefficient of V,NS = +O.8mV /oe but this is not tested.
5. Tested at 25°C and 70°C only.
6. Tested at 25°C only.

,ooor-+-+-i-+-+--:

1400

g '200r-40~~~r-~~~--7-~~~--~~~-1~

r=
~ aoo

i m~t-+-~~~~~~~~~~~~+-~

-Tested as
specified in
table of
Electrical
Characteristics

,00~t-~t'f=+=+=+=+=+=4=4=~~~~1
Q

'00

300

400

SOD

600

70CI

800

900 1000 11011 1200 1300 1400 1500

INPUT FREQUENCY (MHz)
Fig.3 Typical input characteristics

CLOCK
INPUT

r--------------------- . . .

~~;~----------------,

-1.82V

i-----------------------O~~T------------------~

-o.75Y

-1.6OV

Fig.4 Timing diagram

OPERATING NOTES
1. The clock input (pin 10) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capacitor from the internal bias decoupling, pin
12, to ground.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from the input to VeE (i.e. Pin 10 to Pin 7). This will
reduce the Input sensitivity by approximately 100mV.
3. The clock inhibit input is compatible with standard ECl
III/10K using a common OV. A 6k pulldown resistor is
included on the chip. The input should be left open to DC

when not in use, but should be bypassed for RF signals with a
1nF capacitor to ensure maximum noise immunity.
4. Input impedance is a function of frequency. See Fig. 5.
5. The emitter follower output includes an internal 3k
pulldown resistor and is compatible with ECl II, but can be
interfaced with ECl III/10K by the inclusion of two resistors.
See Fig. 7.
6. Note that all components should be suitable for the
frequency in use.
7. The circuit will operate to DC butthe inputslew rate must
be 200VlJ.ls or greater.

SP8678B

Fig.5 Typical input impedance. Test conditions: supply voltage -6.BV, ambient temperature 25°C, frequencies in MHz, impedances
normalised to 50 ohms.

20n

~---C:=J----ll----c:=:: •
T05Dn
SAMPLING

SCOPE

- -.......---~---v"

Fig.6 Test circuit

-------l!P~IN~4~{:~=~==~-~-~
~
SP8678

- -....

Eel 10K liP

2.4k

---+---v..
Fig.7 SP8678 to ECL 10K interface

SP8678B

~~
INHIBIT
(Eel)

arr-

~;----~

r---~---

-r. . . r--""~OI_.....,V._'

~--¢"-C=::J-1>-- O~;P~T

1
1

.AI<

I
1

;;;;, L ____ - - -

,- __ ..J

V'::...- - - - - - - -.... ·UV
L-_ _ _ _ _ _ _ _ _ _. . ..:.:

;;;;"n
Fig.8 Typical application showing interfacing

PLESSEY

Semiconductors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

SP8680A
600MHz +10/11
The SP8680 is an ECl counter with both ECl 1OK and TTL
compatible outputs. The circuit can operate from either ECl
or TTL supplies. The division ratio is controlled by two
control inputs (PE1 and PE2) which are ECl compatible. The
counter will divide by 10 when either control input is in the
high state and by 11 when both inputs are low. The counter
can also be set to the eleventh state by applying a high level
to the master set input.

CLOC~ INHIIIlT [ 1

CONTROl INPUT

'-./

15 ] INPUT BIAS

rEI [ 2
Z[
PE2

14 ] MASTER SET INPUT

Vee [ 4

13] Va {TTl DIP)

DIP STAG~ VecA [ 5

FEATURES
•
•

Very High Speed - 650MHz Typ.

tl ]mOUTPUT

PUllUP[ 7

]Nt

• ]iCL OUTPUT

or AC Clocking

•

Clock Enable

•
•

Divide By 10 or 11
Asynchronous master set

•

Equivalent to Fairchild 11 C90

DG16
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

QUICK REFERENCE DATA
•

12 ] VEE

PEt PULLUP [

Eel. OUTPUT [ 8

ECl and TTL Compatible Outputs

'. ] CLOCK ',.PUT

Supply voltage
ECl output source current
Storage temperature range
Mal<. junction temperature
TTL output sink current
Max. clock liP voltage

Supply Voltage: 5V +O.5V -0.25V
or -5V -O.5V +0.25V

•

Power Consumption: 420mW

•

Temperature: -55°C to +125°C

8V
50mA
-55°C to +150°C
+175°C
30mA
2.5V p-p

, __________________vL: ______ V':'];:T____ I
I
PEt PULL UP 6

TTL OUTPUT

I
I

Q.~>-----o8 ECLOUTPUT

~---ol 9 -EC1.-0U-TPU-T
I

PE2 PULL UP 7
CLOCK INHIBIT

L_________ ~.::_~ ______
16
CLOCK INPUT

14
MASTER SET

15
INPUT BIAS

Q _____ -0- ____
j12
Vu

113
TTL Vu

Fig.2 Functional diagram

SP8680A
ELECTRICAL CHARACTERISTICS
TTL OPERATION

Supply voltage: Vee = VeeA = 4.75 to 5.5V VEE
Temperature:cTamb= -55°C to +125°C
Characteristics

= OV

Symbol

Value
Min.
Max.

Units

550

MHz

Clock input AC
coupled = 350mV p-p

Note 4

MHz

Clock input AC
coupled = 600mV p-p

Note 5

Conditions

Notes

Maximum frequency
sinewave input

fmax

Minimum frequency
sinewave input

fmin

Power supply current

lEE

105

Vee = Vee max.
Pins 6,7,13 open circuit

Note 4

Power supply current
including TTL stage

lEE

111

Vee = Vee max.
Pins 6,7 open circuit

Note 4

0.5

V
V

Vee
Vee

Vee

= Vee min. IOH = -64Ot.tA
= Vee max. IOL = -20mA
= 5.0V (25°C)

Vee

= 5.0V (25°C)

TTL output high voltage
TTL output low voltage

VOH
VOL

2.3

Input high voltage
PEl and PE2 inputs

VINH

3.9

Input low voltage
PEl and PE2 inputs

VINl

Input low current
PEl and PE2 inputs

III

-4

tpHl
tplH

Propagation delay CP to Q TTL
Propagation delay MS to Q TTL
Mode control set-up time
Mode control release time
TTL output rise time (20 % - BO D/~
TTL output fall time (BO % - 20 D/~

tp
ts
t,

3.5

Vee = Vee max. (25°C)
Pins 6,7 = Vee VIN = O.4V

Vee

= 5.0V

ns
ns
ns
ns
ns

Vee
Vee
Vee
Vee
Vee

= 5.0V (25°C)
= 5.0V (25°C)
= 5.0V (25°C)
= 5.0V (25°C)
= 5.0V (25°C)

4
4

tTlH
tTHl

5
5

(25°C)

Note 4
Note 4

Note 5
Note
Note
Note
Note
Note

5
5
5
5
5

ELECTRICAL CHARACTERISTICS
ECl OPERATION
Supply Voltage: VEE = -4.75V to -5.5V Vee = OV
Temperature: Tamb = -55°C to +125°C
Characteristics

Symbol

Value
Min.
Max.

Units

550

MHz

Clock input AC
coupled = 350mV p-p

Note 4

MHz

Clock input AC
coupled = 600mV p-p

Note 5

105

Vee = Vee max.
Pins 6,7,13 open circuit

Note 4

Conditions

Maximum frequency
sinewave input

fmax

Minimum frequency
sinewave input

fmin

Power supply current

lEE

ECl output high voltage

VOH

-0.93

-0.7B

VEE = -5.2V (25°C)
load = lOon to -2V

ECl output low voltage

VOL

-1.B5

-1.62

VEE = -5.2V (25°C)
Load = lOon to -2V

Input high voltage
Input low voltage
I nput low currents

VINH
VINl
III

-1.095
-1.B5
0.5

-O.Bl
-1.475

V
V
/1 A

VEE = -5.2V (25°C)
VEE = -5.2V (25°C)
25°C

Input high current
Clock and MS
PEl and PE2

IH
IH

400
250

/1 A

VIN
VIN

/1 A

= -1.B5V (25°C)
= -O.BV (25°C)

Notes

SP8680A
ELECTRICAL CHARACTERISTICS - ECl OPERATION (CONT.)
Characteristics

Value
Min.
Max.

Symbol

Propagation delay CP to 04

tpHL
tpLH
tpLH
ts
tr
ITLH
ITHL

Propagation delay MS to 04
Mode control set-up time
Mode control release time
ECl output rise time (20 % - BO o/~
ECl output fall time (BO % - 20 %)

Conditions

Units
load

ns
ns
ns
ns
ns
ns
ns

3
6

4
4
2
2

= 1000 to -2V (25°C)

Notes
Note 5
Note
Note
Note
Note
Note

25°C
25°C
25°C
25°C
25°C

5
5
5
5
5

NOTES
1. Unless otherwise stated, the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH = +1.2mV 1°C, VOL = +0.24mV 1°C and of V,N = +O.BmV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.6.
4. Tested at 25°C and +125°C only.
5. Guaranteed but not tested.

I\,

9=1400

:§.1200
~

1000

E 800
it
~

125~ "-

600

55'C

""- "-

100

200

300

400

500

600

r-- r-~

700

~
800

INPUT FREQUENCY (MHz)

Fig.3 Typical input sensitivity SP8680

CLOCK INPUT

-,'rr-

--('r--

-'1 !

. . 'NPUTl......
: ___________

Q4 AND TTL

..J'

L
MS

CLOCK
INH.

PE1

PE2

l
l

L
L
L

L
L

x =DON'T

H
H

OUTPUT
RESPONSE
All OUTPUTS
SET HIGH
HOLD
+11
+10
+10
+10

CARE

Fig.4 Truth table and timing diagram SP8680

NOTE:
The set-up time ts is defined as minimum time that can elapse between L-H transition of control input and the next L.... H clock pulse transition to
ensure that the +10 mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H - L transition of control input and the next L.... H clock pulse
transition to ensure that the +11 mode is obtained.

SP8680A

,1
Fig.5 Typical input impedance. Test conditions: supply voltage 5V, ambient temperature 25°C, frequencies in MHz.
impedances normalised to 50 ohms.

+v~

200

'00
200

200

Eel OUTPUT
10500
SAMPLING

stOPE

TTL. OUTPUT

Fig.6 Test circuit

OPERATING NOTES
1. The clock input, which is ECl 10K compatible
throughout the temperature range, can alsO be directly
coupled to TTL as shown in Fig.9. The clock can also be
capacitively coupled to the signal source (see Fig.7).
Connecting the internally-generated bias lIoltage to the
clock input, i.e. pin 15 to pin 1El centres the clock input about
the switching threshOld (see Fig.S).
2. The two complementary outputs are I:el 10K
compatible but internal pulldown resistors are not included,
and thus an external resistor tb Vfi.E is required.
3. The TTL totem pole output operates with the same
supply and is powered up by connecting V EE (pin 12) to TTL
VEE (pin 13). Ifthe TTL output is not required then the TTL VEE
(pin 13) should be left open-circuit reducing ttie power
consumption by 20mW.

4. Both control inputs (PE1 and PE2) are ECL 10K
compatible throughout the temperature range. Each control
input is provided with a pull up resistor, the remote ends of
which are connected to pins 6 and 7. This allows the pull up
resistors to be unused if so desired, or to be used to interface
from TTL (see Fig.9). If interfacing to ECl is required then
pins 6 and 7 should be left open circuit: alternatively they can
be connected to V EE to act as pull-down resistors. When high,
the master set input sets the counter to the eleventh state, is
asynchronous, and overrides the clock input.
5. All the inputs have an internal pull-down resistor of 50k.
6. The device will operate down to DC but input slew rate
must be better than 20Vlps.
7. Input impedance Is a function of frequency. See Fig.5.

SP8680A

o-.r~"
SP8680

Fig.7 AC coupled input

."V

TTL. MODULUS
CON ROL

221 __

;;;;,""
----- • - - I
OUTPUT Vee

I
1

0.11

INPUT

o--f

....

I
I
I

I
IL ________

TTL OUTPUT

__.J

YuTTL

Fig.S TypIcal applicatIon showIng Interfacing

TV"

r---vcr

I
'OR' I
I

I
I
TTL

'OR'

~,27'
TTL

[I"

I
I
I
L. ____

(II LOW IPI!ID

r- -I

,oR.1

I
I
V..

I
'OR' I
I

I
L ____
CD) HIGH IPIID

Fig.9 TTL interface to PEl and PE2

PLESSEY

Semiconductors __________________

SP8680B
600MHz + 10/11
The SP8680 is an ECl counter with both ECl 1OK and TTL
compatible outputs. The circuit can operate from either ECl
or TTL supplies. The division ratio is controlled by two
control inputs (PE1 and PE2) which are ECl compatible. The
counter will divide by 10 when either control input is in the
high state and by 11 when both inputs are low. The counter
can also be set to the eleventh state by applying a high level
to the master set input.

CLOCK INHIBIT [ 1

'-"

tE1[ 2
CONTROL 1NPUT
2[

FEATURES

•
•
•
•
•
•
•

vcc[

VEE (TTL DIP)

12PVEE

PE1 PULlUP [ 8

11pmOUTPUT

PE2 PUUUP 7

10PNC
9)J Eel OUTPUT

DP16

ABSOLUTE MAXIMUM RATINGS
Supply voltage
ECl output source current
Storage temperature range
Max. junction temperature
TTL output sink current
Max. clock liP voltage

Supply Voltage: 5V +0.5V -0.25V
or -5V -0.5V +0.25V
Power Consumption: 420mW
Temperature: -40°C to +85°C

•
•

Flg.l Pm connections - top View

QUICK REFERENCE DATA

•

INPUT BIAS

EeL OUTPUT

Very High Speed - 650MHz Typ.
ECl and TTL Compatible Outputs
DC or AC Clocking
Clock Enable
Divide By 10 or 11
Asynchronous master set
Equivalent to Fairchild 11 C90

CLOCK INPUT

MASTER SET INPUT

PE2

DIP STAGE VetA [ 5

1SP

Vee

8V
SOmA
-SsoC to +12SoC
+17SoC
30mA
2.SV p-p

Vee OUTPUT

r-- - -- -- - -- - _______ 6' _______ 6'_____ ,
I 11
I

PEl PULL UP 6

TTL OUTPUT

I
I

Q4!-<1-----1
9 ECLOUTPUT
1I

PE2PUU UP 7
CLOCK INHIBIT

L______ ---~·::-~------Q------o-----J
16

CLOCK INPUT

MASTER SET

INPUT BIAS

VEE

Fig.2 Functional diagram

113

Tn. VEE

SP8680B
ELECTRICAL CHARACTERISTICS
TTL OPERATION
Test conditions (unless otherwise stated):
Tamb == -40"C to +85°C Supply voltage: Vee
Symbol

Characteristics

VeeA

== 4.75 to 5.5V

VEE

== OV

Value
Min.
Max.

Units

575

MHz

Clock input AC
coupled == 350mV p-p

MHz

Clock input AC
coupled == 600mV p-p

Conditions

Maximum frequency
sinewave input

fmax

Minimum frequency
sinewave input

fmln

Power supply current

lEE

105

Vee == Vee max.
Pins 6,7,13 open circuit

Power supply current
including TIL stage

lEE

111

Vee == Vee max.
Pins 6,7 open circuit

TIL output high voltage
TIL output low voltage

VOH
VOL

2.3
0.5

V
V

Vee
Vee

Input high voltage
PE1 and PE2 inputs

V,NH

3.9

Vee

== Vee min. IOH == -64OpA
== Vee max. IOl == -20mA
== 5.0V (25°C)

Input low voltage
PE1 and PE2 inputs

V,Nl

Vee

== 5.0V

Input low current
PE1 and PE2 inputs

III

-4

a TIL

tpHl
tplH

tp
t.
t.
tTlH
tTHl

Propagation delay CP to

Propagation delay MS to TTL
Mode control set-up time
Mode control release time
TIL output rise time (20 % - 80 %)
TIL output fall time (SO % - 20 %)

3.5

Vee == Vee max. (25°C)
Pins 6,7 == Vee Y,N == O.4V

Vee

== 5.0V

ns
ns
ns
ns
ns

Vee
Vee
Vee
Vee
Vee

== 5.0V
== 5.0V
== 5.0V
== 5.0V

5
5

Note 4

(25°C)

4
4

Notes

(25°C)

(25°C)
(25°C)
(25°C)
(25°C)
5.0V (25° C)

Note 4
Note
Note
Note
Note
Note

4
4
4
4
4

ELECTRICAL CHARACTERISTICS
EClOPERATION
Test conditions (unless otherwise stated):
Tamb
-40°C to +85°C Supply Voltage: VEE

Characteristics

Symbol

Maximum frequency
sinewl!ve input

fmax

Minimum frequency
sinewave input

fmln

Power supply current

lEE

ECL output high voltage

VOH

ECL output low voltage
Input high voltage
Input low voltage

= -4.75V to -5.5V

Vee

= OV

Value
Min.
Max.

Units

575

MHz

Clock input AC
coupled
350mV p-p

MHz

Clock input AC
coupled
SOOmV p-p

Conditions

Notes

Note 4

105

-0.93

-0.78

VOL

-1.85

-1.62

V,NH
V,Nl

-1.095
-1.85

-0.81
-1.475

V
V

Vee
Vee max.
Pins 6,7,13 open circuit

=
=
VEE = -5.2V (25°C)
Load = 1000 to -2V
VEE = -5.2V (25°C)
VEE = -5.2V (25°C)
VEE
-5.2V (25°C)
Load
1000 to -2V

SP8680B
ELECTRICAL CHARACTERISTICS - ECl OPERATION (CONT.)
Charactertstlc

Value
Min.
Max.

Symbol

Input low currents
Input high current
Clock and MS
PE1 and PE2
Propagation delay CP to 04
Propagation delay MS to 04
Mode control set-up time
Mode control release time
ECL output rise time (20 % - 80 %)
ECL output fall time (80 %- 20 %)

ilL

0.5

IH
IH
tpLH
tpLH
t.
tr
tTLH
tTHL

Conditione

Units

400
250
3
8
4
4
2
2

25°C

pA
pA
ns
ns
ns
ns
ns
ns

VIN= -1.85V(25"C)
VIN= -0.8V(25°C)
Load = 1000 to -2V(25°C)
25°C
25°C
25°C
25°C
25°C

Notes

Note 4
Note 4
Note 4
Note 4
Note 4
Note 4

NOTES
1. Unless otherwise stated, the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH~ +1.2mV/oC, VOL= +O.25mV/oC and of VIN= +O.8mV/oC but these are not tested.
3. The test configuration for dynamic testing Is shown in Flg.S
4. Guaranteed but not tested.

CLOCK INPUT

~~~

!___________--11 !

1I!INPUTl......

Q4 AND T1\.

..J

L
MS

CLOCK
INH.

PE1

PE2

L
L
L
L
L

H
L
L
L
L

X
L
H
L
H

X
L
L
H
H

x =DON'T

OUTPUT
RESPONSE
ALL OUTPUTS
SET HIGH
HOLD
+11
+10
+10
+10

CARE

Flg.S Truth table and timing diagram SPB6BO
NOTE:
The set-up time ts is defined as minimum time that can elapse between L- H transition of control input and the next L-H clock pulse transition to
ensure that the +10 mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H -L transition of control input and the next L-H clock pulse
transition to ensure that the +11 mode is obtained.

SP8680B

.j'

FigA Typical input impedance. Test conditions: supply voltage 5V, ambient temperature 25°C, frequencies in MHz,
impedances normalised to 50 ohms.

+V~

'60

200
200

GENE~'!TOR "--~::J---~-III--+

200

Eel OUTPUT
TO 500
SAMPLING
SCOPE

TTL OUTPUT

TO
MONITOR

Fig.5 Test circuit

OPERATING NOTES
1. The clock input, which is ECl 10K compatible
throughout the temperature range, can also be directly
coupled to TTL as shown in Fig.B. The clock can also be
capacitively coupled to the signal source (see Fig.6).
Connecting the internally-generated bias voltage to the
clock input, i.e. pin 15 to pin 16 centres the clock input about
the switching threshold (see Fig.7).
2. The two complementary outputs are ECl 10K
compatible but internal pulldown resistors are not included,
and thus an external resistor to VEE is required. The outputs
are capable of driving a 50 ohm load to -2V over the
temperature range -40°C to +85°C. The output high level
will typically be reduced by 50mV.
3. The TTL totem pole output operates with the same
supply and is powered up by connecting VEE (pin 12) to TTL
VEE (pin 13). If the TTL output is not required then the TTL VEE

(pin 13) should be left open-circuit reducing the power
consumption by 20mV.
4. Both control inputs (PE1 and PE2) are ECl 10K
compatible throughout the temperature range. Each control
input is provided with a pull up resistor, the remote ends of
which are connected to pins 6 and 7. This allows the pull up
resistors to be unused if so desired, or to be used to interface
from TTL (see Fig.B). If interfacing to ECl is required then
pins 6 and 7 should be left open circuit: alternatively they can
be connected to VEEtO act as pull-down resistors. When high,
the master set input sets the counter to the eleventh state, is
asynchronous, and overrides the clock input.
5. All the inputs have an internal pull~down resistor of 50k.
6. The device will operate down to DC but input slew rate
must be better than 20V/jls.
7. Input impedance is a function of frequency. See Fig.4.

SP8680B

0,1>,

o--f t-~-,1,6
SP8680

"
Fig.6 AC coupled input

,---~-------t--~-----+5.2V

OUTPUT Vee

r- o....r-........,
I

I
I
0.1"

INPUT

16 1

o---J t-<~'<>--,--r

t--__-C1>"10'-----. t'-...
~
50

'00

'50

200

250

INPUT FREQUENCY (MHz)

Fig.6 Typical input characteristics SP86790/1

-I'

Fig.7 Typical input impedance. Test conditions: supply voltage 5.0V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

OPERATING NOTES
1. The clock inputs can be single or differentially driven.
The clock input is biased internally and is coupled to the
signal source with a suitable capacitor. The input signal path
is completed by an input reference decoupling capacitor
which is connected to earth.
2. In the absence of a signal the device will self-oscillate. If
this is undesirable it may be prevented by connecting a 68k
resistor from the input to VEE (i.e. Pin 1 or 16 to Pin 12). This
reduces input sensitivity by approximately 100mV.
3. The circuit will operate down to DC but slew rate must be

10k internal pulldown resistor. Unused inputs can therefore
be left open circuit.
6. The input impedance of the SP8690/1 varies as a
function of frequency. See Fig. 7.
7. The TTL/CMOS output has a free collector and the high
state output voltage will depend on the supply that the
collector load is taken too. This should not exceed 12V.
8. The rise/fall time of the open collector output waveform
is directly proportional to load capacitance and load resistor
value. Therefore load capacitance should be minimised and

better than 100VlM!\,
4. The 04 and 04 output. are oompatlble with eOL. II but
can balnterlaeod t{) EeL. 10K as ilhown In Flg.9,
tl. iho PI!! Inputs are EOL. IIi/10K compatlblellnd Inlliude a

the load resistor kept to Il minimum compatible with system
power requirements, In the test configuration of Fig, 81 the
output riae time is approximately 10nl Ind fill time Is 1n8
typically,

104

SP8690/1A & B

- - -......----1~---_---vcctf_5V)

CLOCK INPUT

..:_:::::'!~

____

~-I

33
33
INPUT MONITOR ----~I--C=::J-+

. . . . , . - ' - - - -....- - - - - - Vn(OV)

Fig.B Test circuit for dynamic measurements

..v

TTL CONTROL INPUT

O-~1

1_-+<10

o------------+~c=c=}__;

1----I
10n

CLOCK INPUT

------,

ole
3

o----J I-----'o-.....-r
I

560

'Ok

I"
I
I

TTL OUTPUT

Eel OUTPUT

10,

Fig.9 Typical applications circuit showing interfacing

105

PLESSEY

Semiconductors __________________

SP8695A&B
200M Hz

10/11

The SP8695 is a low power ECL counter with both ECL
10K and TTL compatible outputs. They divide by 10 when
either control input in the 'high' state and by 11 when both are
'low' (or open circuit). The inputs are ECL II compatible but
can also be AC coupled. An open collector output is
provided for interfacing to TTL or CMOS.

CLOCK INPUT [ 1

ffi[

FEATURES

'-"

18 ] CLOCK INPUT

15] Ne

PEl [ 3

14] Ne

Ne [4

13] Ne

Vee [ 5

JVEE

•

low Frequency Operation

Ne [ 6

JOPEN COllECTOR OUTPUT

•

ECl and TTL! CMOS Outputs

NC [ 7

~ NC

•

DC or AC Coupled Input

•

Temperature Ranges:
A Grade: -55°C to +125°C

•PEClOUTPUT

Eel OUTPUT [ 8

DG16
Fig. 1 Pin connections - top view

B Grade: -30°C to +lO°C

QUICK REFERENCE DATA
•

Supply Voltage: +5.0V

•

Power Consumption: 80mW

•

Maximum Input Frequency: 200MHz

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output EeL current
Storage temperature range
Max. junction temperature
Max. input voltage
Max. open collector output voltage
Max. open collector current

-8V
10mA
-55°C to +150°C
+175°C
2.5V p-p
+12V
15mA

--,

i--

I
OPEN
011 COLLECTOR
OUTPUT

I
I

I
Q.

o
CONTROL {PE1
INPUTS

PE2

CLOCK INPUT 1

2
3

I
I

1
9 OUTPUT

~I----::=f:>----------J----......JL---......J

CLOCK INPUT2 1&

L _ ---------------J----------- ____ .J
12

v"
Fig.2 Functional diagram

106

OUTPUT

SP8695A & B
ELECTRICAL CHARACTERISTICS
ECl OPERATION
Supply Voltage: VEE = -5.2V ± 0.25V Vee = OV
Temperature: A grade Tamb = -55°C to +125°C
B grade: Tamb = -30°C to +70°C
Characteristics

Symbol

Maximum frequency sinewave input
Minimum frequency sinewave input
Power supply current
ECl output low voltage
ECl output high voltage
PE input high voltage
PE input low voltage
Clock to ECl output delay
Set-up time
Release time

fmax

Value
Min. Max.
200
2
21
-0.7
-1.5

fmin

lEE
VOH
VOL
VINH
VINL
tp
Is
tr

-0.85
-1.8
-0.93

-1.62
9
3
8

Temperature

Units

Conditions

MHz
MHz
mA
V
V
V
V
ns
ns
ns

Input = 400-800mV p-p
Input = 400-800mV
VEE = -5.0V
VEE = -5.2V (25° C)
VEE = -5.2V (25° C)
VEE = -5.2V (25°C)
VEE = -5.2V (25° C)

Note 3
Note 4
Note 3

Note 4
Note 4
Note 4

NOTES
1. Unless otherwise stated, the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH = +1.63mV(OC, VOL= +O.94mV (OC and of VIN = +1.22mV (OC but these are not tested.
3. SP8695B tested at 25°C only.
4. Guaranteed but not tested.
5. TTL output not recommended for use above 15MHz output frequency. Coad .:10: 5pF.

ELECTRICAL CHARACTERISTICS
TTL OPERATION
Supply Voltage: Vee = 5.0 ± 0.25V VEE = OV
Temperature: A grade Tamb = -55°C to +125°C
B grade Tamb = -30°C to +70°C
Characteristic

Symbol

Maximum frequency sinewave input
Minimum frequency sinewave input
Power supply current
TIL output high voltage
TIL output low voltage
Clock to TIloutputdelay (positive going)
Clock to TIL output delay (negative going)
Set-up time
Release time

fmax

Value
Max.
Min.
200

MHz
MHz
mA
V
V
ns
ns
ns
ns

2
21

fmin

lEE
VOH
VOL
tpLH
tpHL
ts
tr

Conditions

Units

3.75
0.5
32
18
3
8

Input =400 - 800mV p-p
Input =400 - 800mV p-p
Vee= 5.0V
Vee= 5V Rl= 5600
Rl =5600
Rl = 5600
Rl =5600

Notes
Note
Note
Note
Note
Note
Note
Note
Note
Note

3
4
3
3,5
3
4
4
4
4

'800
'800

f
>

T11I=_55,ltoT125lc

1400

r:i ...V/L
!

1200

*Tested as
specified in
table of
Electrical
Characteristics

400

200

o
o

GU~ANTEED/
OPERATING
/
WINDOW
I

I
"0

'50

./
200

'50

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics SP869SA

107

SP8695A & B

CONTROL INPUT TRUTH TABLE

CLOCK INPUT

~h~

PEINPUTlL ....
; _ _ _"""-_ _ _ _ _ _ _....1

OUTPUT

-l

PE1

PE2

Division
Ratio

l
H
l
H

l
l
H
H

11
10
10
10

Fig.4 Timing diagram SP8695

NOTES
The set-up time ts is defined as minimum timethat can elapse between L-H transition of control input and the next L-H clock pulse transition to
ensure that the + 10 mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H-L transition of control input and the next L-H clock pulse
transition to ensure that the +11 mode is obtained.

Fig.5 Typical input impedance. Test conditions: supply voltage 5.0V, ambient temperature 25°C, frequencies in MHz, impedances

normalised to 50 Ohms.

OPERATING NOTES
1. The clock inputs can be driven from ECl II, III and 10K.
The input reference voltage (-3.8V at 25°C) is compatible
with ECl II, III and 10K over the specified temperature range.
The inputs can also be capacitively coupled by addition of
external bias as shown in Fig. 6. Each input has an internal
pull-down resistor of 10k, and unused inputs can therefore
be left open circuit. They should by bypassed to RF where
maximum noise immunity is required.
2. The PE control inputs are similarly ECl III/10K
compatible and also have an internal 10k pull-down resistor,
allowing unused ir}fluts to be left open circuit if required.
3. The 04 and 04 ECl outputs have internal circuitry
equivalent to a 14k pull-down resistor on each output and are
ECl II compatible: they can however be interfaced to ECl
III/10K as shown in Fig. 8.

108

4. The circuit will operate down to DC but slew rate must be
better than 5V/j.Js.
5. The input impedance of SP8695 varies as a function of
frequency. See Fig. 5.
6. The TTL/CMOS output has a free collector and the high
state output voltage will depend on the supply that the
collector load is taken to. This should not exceed 12V. The
rise and fall time of the open collector output waveform is
directly proportional to load capacitance and load resistance
value. Therefore load capacitance should be kept to a
minimum and the load resistor kept to a minimum
compatible with system power requirements. In the test
configuration of Fig. 6 the output rise time is approximately
10ns and fall time is 7ns typically.

SP8695A & B
r-------~--~--------ov

t-------------TO

GENERATOR

ITl O/P

~-~~:-~----~~~~--~~~~~i::::r_l~~
~ tr-t-===

TO
SCOPE:

TO SCOPE

INPUT

L-...,.,....---r-'------'"1~

£J~~
~5

________" "________ 5.2V

Fig.6 Test circuit

SP8695

OUTPUT~----IC=J---.....----_ Eel 10K OIP

Q4 OR

t--------o

PE INPUT

3.6k

TTL/CMOS DRIVE

Fig.7 Interfacing TTL/CMOS to PE inputs

Fig.S Interfacing to SPS695 output to ECL 10K

r--------------------------------1----------------------------------~--~~v

-- ---------,

560

~--=---1

-J

MODULUS
CONTROL
INPUT

Fig.2 Functional diagram SP8704

113
I

SP8704
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -40°C to 85°C. Vcc = +2.75V to +5.5V
Characteristic

Min.

Supply current
I nput sensitivity

10
150
25
15
15
50

mVrms

300

mVrms
n
pF
V pk-pk

50
2
1

Output

Modulus control (pin 6)

Units

Max.

10MHz
80M Hz
150MHz
850M Hz
950MHz

Input overload
Input impedance

Ratio select (pin 3)

Value
Typ.

LO
HI •
LO
HI'

1
Vcc
1
2

Clock to output delay
Set up time
Release time

8
16
16

Including output emitter follower
Sinewave input into 50n

Emitter follower output
current source = 0.75mA

V
V

128/129 selected
64/65 selected

V
V

65 or 129 selected
64 or 128 selected

ns
ns
ns

'Or pin open circuit

TRUTH TABLE

114

Conditions

Pin 3

Pin 6

Division
ratio

L
L
H
H

L
H
L
H

129
128
65
64

PLESSEY

NOVEMBER 1987

Semiconductors _________.P.R..E.L..IM
.....
IN'' ' 'A' ' ' RlIIIIy...I.N.F.O.R.M.A.T.IO_N

SP8710A & B
225MHz LOW POWER TWO MODULUS DIVIDER . 100/1 01

The SP8710 is a Low Power Two Modulus Divider with a
divide by 100 ratio when the modulus control input is high
and 101 when the input is low. The device also features a
power down mode and will operate with a 3V power
supply.The 'A' Grade device is characterised over the full
military temperature range of -55 Q C to + 125 Q C, the '8'
Grade over the industrial range of -40°C to + 85 Q C.

MOD CONTROL
OUTPUT VCC

EJ
SP8710

OUTPUT

BIAS DECOUPLE

VEE

FEATURES
• Low Power High Speed
• Power Down Mode
• CMOS Compatible Ol!tput Capability
• Ideal for Decade Synthesisers
.3V Supply Operation

VCC'
POWER DOWN

CLOCK INPUT

DG8 (SP87l0A). DP8 (SP87l0B)
Fig. 1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS

QUICK REFERENCE DATA

Supply voltage
Clock input level
Junction temperature
Storage temperature range
SP8710A
SP87108

• Supply Voltage Range 3V to 10V
• Full Military Temperature Range:
-55°C to 125°C (SP8710A)

POWER
DOWN
7

r---

12V

2.5V pop
+175 Q C
-55°C to + 150 Q C
-55°C to + 125 C
Q

OUTPUT
Vee
2

Veel
8

---,

I
I

I
I
I

I
CLOCK INPUT 5

+ 1001101

3 OUTPUT

BIAS DECOUPLE 6

I
I
I
I
I1.. _ _ _ _ _ _ _ _ _ _ _ _ ..JI
4

VEE

MODULUS
CONTROL
INPUT

Fig.2 SP8710 functional diagram

115

SP8710AlB
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)
Tamb = SP8710A-55°Cto +125°C,.SP8710B-40°Cto +85°C, Vee = +3Vto +10V
Value
Characteristic

Min.
Max. sinewave input frequency
Min. sinewave input frequency
Min. slew rate for LF operation
Power supply current lEE

Output low voltage
Output high voltage
Modulus control input high voltage
Modulus control input low voltage
Modulus control input high current
Modulus control input low current
Clock to output propagation delay
Set up time
Release time
Power down input high voltage
Power down input low voltage
Power down input high current
Power down input low current

MHz
MHz

20
100

0
Vee-0.9
Vee-0.95
0

0.6Vee
0

Input
Input

= 200m V - 1200mV pop
= 400mV - 1200mV pop

V/~s

1
1
1
1
5,6,7
1
1
7
7
7
7

Max.

225

5
5
5

Conditions

Units

8.5
1
0.5
Vee
Vee
Vee
O.4Vee
20
-10
80
10
10
Vee
O.4Vee
1
-1

=
=

mA
mA
mA
V
V
V
V
V

Power up Vee
5V
10V
Power up Vee
Power down
Load
10pFlll00k
Load
1OpFIll OOk, Vee
Load
1OpFIll OOk,Vee

!lA
!lA

Input
Input

=
=
=

= 5V
= 10V

= Vee
= OV

ns
ns
ns
V
V

!lA
~

1600r-----~------~----~------~--~~------~

1200r--,--~----~~----~----~~~.--+----~

INPUT
AMPLITUDE
(mVp-p)

in Table of
Electrical
Characteristics

800

400..,..--'---1

100

200

INPUT FREQUENCV (MHz)
Fig.2 Typical input characteristics SP8710

116

* As specified

300

SP8710AlB

POWER DOWN INPUT

RATIO SELECT

Vee

7
1
8
r-----------------O-------------------O------------

--------------~

OUTPUT

Vee

CLOCK
INPUT 5

<>---II-O-.....--I____~
6

,,
,
,,,
,,
,
~

DIVIDE BY
100/101

,,,
,
,,
,

'4
_____________________________________________________ _____________ J

Fig.3 Typical application showing interfacing

-jl

Fig.4 Typical Input Impedance. Test conditions:supply voltage 5V. ambient temperature 25°C,
frequencies in MHz, impedances normalised to 50 Ohms

117

PLESSEY

Semiconductors __________________

SP8712B
2400MHz

The SPB712B is an asynchronous emitter coupled logic
counter which provides Eel 10K compatible outputs and
can drive 100 ohm lines. It operates from a -6.BV supply or
split supplies of +5V and -1.BV. Otherwise it is similar to the
SP8610 and SP8611.

NC[ 1

FEATURES

•
•
•

ECl Compatible Output
AC Coupled Input (Internal Bias)
Typical Operating Frequency 2.5GHz

'-"

NC[ 2

NC[ 3

PVcc{OV)

PIC
PIC

CLOCK INPUT [ 4

11 ~OUTPUT

NC( 5

10 J OUTPUT

INTERNAl BlAS DECOUPLING [ 6

•

VEE[7

DC14
QUICK REFERENCE DATA
Fig.1 Pin connections - top view

•
•
•

Supply VOltage: -6.BV
Power Consumption: 630mW typo
Output Vo~age Swing BOOmV typo

ABSOLUTE MAXIMUM RATINGS
Supply voltage (Vcc - VEE)
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

BV
15mA
-55°C to +150°C
+175°C
2.5V p-p

YCC (OY)

------------~----------~I

I
I
CLOCK INPUT 4

DIVIDE
BY 2

I
1

: 11

OUTPUT

: 10

0ii'i'PuT

DIVIDE

BY 2

L-----J-----r----------J
6
INTERNAL
BIAS DECOUPLING

YEE (·UY)

Fig.2 Block diagram

118

SP8712B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vee = OV, VEE = -6.8V
Temperature: Tamb = O°C to +700C
Characteristic

Symbol

Maximum frequency
sinewave input
Minimum frequency
sinewave input
Power supply current

fmax

Output low voltage

VOL

Output high voltage
Minimum output swing

± 0.35V
Value
Min. Max.
2.4

Notes

Conditions

Units
GHz

Input = 600mV pk-pk

Note 4

fmin

500

MHz

Input = 400mV pk-pk

Note 5

lEE

110

Note 5

-0.93

-0.7

VOH

-1.9

-1.6

VOUT

0.7

Outputll unloaded
VEE = -7.15V
Outputs loaded with
6200 to VEE = -6.8V (25° e)
Outputs loaded with
6200 to VEE = -6.8V (25° e)
Outputs loaded with
6200 to VEE = -6.8V

Note 5

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over specified supply. frequency and temperature range.
2. The temperature coefficients of VOH = +1.2mV 1°C and VOL= +0.24mV 1°C but these are not tested.
3. The test configuration for dynamic testing is shown in Fig.5.
4. Tested at +70°C only.
5. Tested at 25°C only.
"Tested as specified in
table of Electrical
Characteristics
2000
N

(/)

1600

1400

10.

>
§.
w
C

1800

~
~'~
v/ v/w.;,.~.~

1200
1000

:::l

!::

...
...:::l<

800

::;

600

...

400

200

..J

200

400

600

800

1000

1200

OPERATING
AREA

1400

1600

1800

2000

2200

I-- -

2400

2600

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics SPB712

OPERATING NOTES
1. The clock input (pin 4) should be capacitively coupled to
the signal source. The input signal path is completed by
connecting a capaCitor from the internal bias decoupling pin
(6) to ground.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 10k
resistor from the input to VEE (i.e. pin 4 to pin 7). This reduces
sensitivity by approximately 100mV.
3. The input can be operated at very low frequencies but
slew rate must be better than 200VIllS.
4. The input impedance of the SP8712 is a function of
frequency. See Fig.4.

5. The emitter follower outputs require external load
resistors. These should not be less than 330 ohms, and a
value of 620 ohms is recommended. InterfaCing to EeL
III/10K is shown in Fig.7.
6. These devices may be used with split supply lines by
means of the circuit of Fig.6. Some improvement in the upper
frequency of operation may be obtained under these
conditions, but suitable circuit layout must be employed to
achieve this improvement.
7. To obtain the best performance from these devices,
good RF construction techniques must be employed: the use
of lead less chip capacitors is recommended.

119

SP8712B

Fig.4 Typical input impedance. Test conditions: supply voltage -6.8V, ambient temparature 25°C. Frequencies in MHz, impedances
normalised to 50 ohms.

-"",,-"""--Vcc = ov
500
SIGNAL
SOURCE

500 LINE
TO SCOPE

1n~

~~L-_~nL_-'1

I
I

I
I
VEE'" - 8.8V ± O.35V

: +5 ATTENUATOR :
L_~E~O~__ j

Fig.5 Toggle frequency test circuit

---.,....--,--vec=

+5V

rc:=::r--c:--

VEE=-1.8V

Fig.6 Operation on split supply voltages

120

OUTPUT

SP8712B

1.Sk

.e.8v--4-------4-

·S.2V

LOW POWER INTERFACING

Fig.7 Interfacing SP8712 series to ECL 10K and ECL 11/

14
-------

-------l
I
I

L-_-01.!C11'--_ _~-_ ECL OUTPUT
DIVIDE

I
I

,-....:..:>--O__--__......_BIAS
620

620

~-----------4-~>--.6.8V

Fig.8 Typical application showing interfacing

121

PLESSEY ___________________________________
Semlconduclors
SP8716/8/9
520MHz ULTRA LOW CURRENT TWO MODULUS DIVIDERS
SP8716 740/41, SP8718 764/65, SP8719 780/81 are
50mW programmable dividers with a maximum specified
operating frequency of 520MHz over the temperature range
-40°C to +85°C.
The signal (clock) inputs are biased internally and require
to be capacitor coupled. The output stage is of an unusual
low power design featuring dynamic pull-up, and optimised
for driving CMOS. The 0 to 1 output edge should be used to
give the best loop delay performance.

MODULUS CONTROL INPUT [ '0
OUTPUT Vee [ 2

OUTPUT [

•

Vee

NO CONNEcnON

3 87161819

ov [4

PINPUT
5P
INPUT DECDUPUNG

DPB, MPB
Fig. 1 Pin connectIOns - top view

FEATURES

•
•
•

DC to 520MHz Operation
-40°C to +85°C Temperature Range
Control Inputs and Outputs are CMOS Compatible
ABSOLUTE MAXIMUM RATING

QUICK REFERENCE DATA

•
•

Supply voltage (pin 2 or 8):
Storage temperature range:
Max. junction temperature:
Max. clock input voltage:

Supply Voltage 5.2V ± O.25V
Supply Current 10.5mA typo

Vee

•

r------ ----- -I
I
I
I
I
~.ll
~:l'.'t#"-t I,I
I

I
I
I
I
I
I
3 OUTPUT
I
I
I

I
I

__~--~_,
t-1-1--+--

I
I

_______ --lI
4
OY

MODULUS

CONTROL
INPUT

Fig.2 Functional diagram

122

8V
-55°C to +150°C
+175°C
2.5V p-p

SP8716/8/9
ELECTRICAL CHARACTERISTICS
Test conditions (unl_ oth_IH stated):
Supply voltage: Vcc = +4.95 to 5.45V, Temperature: Tamb

Characteristics

Symbol

Max. frequency
Min. frequency (sinewave input)
Power supply current
Output high voltage
Output low voltage
Control input high voltage
Control input low voltage
Control input high current
Control input low current
Clock to output delay
Set-up time
Release time

= -40"C to

Value
Min.

Max.

520

fmax

30
11.9

fmin

Icc
VOH

UnHs

Conditions

Notes

MHz
MHz
mA

Input 10Q-280mV p-p
Input 4OQ-800mV p-p
CL = 3pF; pins 2, 8 linked
IL= -0.2mA
IL = 0.2mA
+N
+N + 1
VINH = 8V
VINL = OV
CL = 10pF
CL = 10pF
CL = 10pF

1
2
1
1
1
1
1
1
1
2
2
2

(Vcc -1.2)

VOL
VINH
VINL
IINH
IINL
tp
ts
Ir

+85°C

1
8
1.7
0.41

3.3
0

V
V
mA
mA
ns
ns
ns

-0.20
28
10
10

NOTES
1. Tested at 25°C only.
2. Guaranteed but not tested.

-=,=-1

---mnrr--mnrr ---JUlJlJ1J11l
I
mil ~:: _______

-+L-~-J L~-J~~:
SET-UP
TIME
10

PROPAGATION
DELAY

RELEASE
TIME
I.

NOTE
The set-up time ts is defined as the minimum time that can elapse between a L- H transition of the control input
and the next L ... H clock pulse transition to ensure that the +N mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H-L transition of the control input
and the next L..... H clock pulse transition to ensure that the +(N + 1) mode is obtained.

Fig.3 Timing diagram

'0:

~,ooo~--~~--~----+----4-----+----~

g~ ooo~~~~--~--~~~~~~-+----~

;! ...

g400

200

H,..--f"""~

,. ,,.

...

300

*Tested as
specified in
table of
Electrical
Characteristics

...

FREQUENCY IN MHz

Fig.4 Typical input characteristics

123

SP8716/8/9
OPERATING NOTES

.-____________

1. The inputs are biased internally and coupled to a signal
source with suitable capacitors.
2. If no signal is present the devices will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from one input to pin 4 (ground). This will reduce the
sensitivity.
3. The circuits will operate down to DC but slew rate must
be better than 1OOVl).ls.
4. The output stage is of an unusual design and is intended
to interface with CMOS. External pull-up resistors or circuits
must not be used.
5. This device is NOT suitable for driving TTL or its
derivatives.

~
1n

OUTPUT

..0
MONITOR
..0

........... SIQNAL
SOURCE

~--------------~--w

Fig.6 Typical input impedance

124

~-,-----------v~

CONTROL
INPIIT

Fig.5 Toggle frequency test circuit

SP8716/8/9A
520MHz ULTRA LOW CURRENT TWO MODULUS DIVIDERS

The SP8716A + 40/41, SP8718A + 64/65 and SP8719A
+80/81 are 50mW programmable dividers with a maximum
specified operating frequency of 520MHz over the
temperature range -55°C to +125°C.
The signal (clock) inputs are biased internally and require
to be capacitor coupled. The output stage is of an unusual
low power design featuring dynamic pull-up, and optimised
for driving CMOS. The 0 to 1 output edge should be used to
give the maximum loop delay.

MODULUS CONTROL INPUT [ 10

OUTPUT Vee [ 2

'-J

SP8716

OUTPUT [3

18/9A •

ov [ 4

Vee

NO CONNEcnON
INPUT
INPUT DECOUPLING

DGB
Fig.1 Pin connections - top view

FEATURES

•
•
•

DC to 520MHz Operation
-55°C to +125°C Temperature Range
Control Inputs and Outputs are CMOS Compatible
ABSOLUTE MAXIMUM RATING

QUICK REFERENCE DATA

•
•

Supply voltage (pin 2 or 8):
Storage temperature range:
Max. junction temperature:
Max. clock input voltage:

Supply Voltage 5.2V ± 0.25V
Supply Current 1O.5mA typo

8V
-55°C to +150°C
+175°C
2.5V p-p

-------,
2

,..---4

I
I

I
I
I
I

3 OUTPUT

I
I
I

I
I

,
ov

_______ .-lI

MODULUS

CONTROL
INPUT

Fig.2 Functional diagram

125

SP8716/8/9A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vcc = +4.95 to 5.45V, Temperature: Tamb = -55°C to +125°C
Characteristics

Symbol

fmax

Value
Min.
520

fmin

Icc
VOH
VOL
VINH
VINL
ItNH
IINL
tp
ts
tr

Max.

(Vcc -1.2)
3.3
0

30
11.9
1.2
1
8
1.7
0.41

-0.20
28
10
10

Units

Conditions

Notes

MHz
MHz
mA
V
V
V
V
mA
mA
ns
ns
ns

Input 125-350mV p-p
Input 40Q-800mV p-p
CL = 3pF; pins 2, 8 linked
IL = -0.2mA
IL = 0.2mA
+N
+N + 1
VINH = 8V
VINL = OV
CL= 10pF
CL = 10pF
CL = 10pF

1
2
1
1
1
1
1
1
1
2
2
2

NOTES
1. Tested at 25°C only.
2. Guaranteed but not tested.

SIGNAL (CLOCK) INPUT

o_ _

JU1Jl[ _-_-~lJlJ1IT ~ ~lJlJ1IT ~ ~ ~JUU1JlflfL

____

OUTPUTlu--~-J~ __ l-=:-i~~

JL
SET-UP
TIME
h

L JL

PROPAGATION
DELAY
Ip

EXTRA STATE

RELEASE
TIME
If

NOTE
The set-up time Is is defined as the minimum time that can elapse between a L- H transition of the control input
and the next L .... H clock pulse transition to ensure that the +N mode is obtained.
The release time tr is defined as the minimum time that can elapse between a H -L transition of the control input
and the next L-H clock pulse transition to ensure that the +(N + 1) mode is obtained.

Fig.3 Timing diagram

*Tested as specified
in table of
Electrical Characteristics

FREQUENCY IN MHz

FigA Typical input characteristics

126

SP8716/8/9A
OPERATING NOTES
1. The inputs are biased internally and coupled to a signal
source with suitable capacitors.
2. If no signal is present the devices will self-oscillate. Ifthis
is undesirable it may be prevented by connecting a 15k
resistor from one input to pin 4 (ground). This will reduce the
sensitivity.
3. The circuits will operate down to DC but slew rate must
be better than 100Vl}ls.
4. The output stage is of an unusual design and is intended
to interface with CMOS. External pull-up resistors or circuits
must not be used.
5. This device is NOT suitable for driving TTL or its
derivatives.

r---------------~------------y~
CONTROL

INPUT

~
........

OUTPUT

500

MONITOR
500

SIGNAL

SOURCE

+-______......._ov
Fig.S Toggle frequency test circuit

Fig.6 Typical input impedance

127

PLESSEY

Semiconductors ___________________

SP8720A&B
300MHz -;- 3/4
The SP8720 is an ECl counter with ECl 10K compatible
outputs. It divides by 3 when either control input is in the high
state and by 4 when both inputs are low (or open circuit). An
AC coupled input of 600mV p-p is required.

CLOCK INPUT [ 1

CONTROL INPUTS

16 ] INTERNAL BIAS DECOUPLING
15 ~ Ne

!PE1
[2
2. [
PE2

•

ECl Com I Jatible Outputs

•

AC Coupled Input (Internal Bias)

•

Control Inputs ECl 111/1 OK Compatible

PNe

13P NC
12P

NC [ 4

FEATURES

Vee

10P Ne

OUTPUT

VEE

DO NOT CONNECT

•

'OUTPUT

Fig.l Pin connections - top view

QUICK REFERENCE DATA
•

Supply Voltage: -5.2V

•

Power Consumption: 240mW

•

Temperature Range:
A Grade: -55°C to +125°C
B Grade: -30°C to +70°C

ABSOLUTE MAXIMUM RATINGS
-8V
20mA
-55°C to +150°C
+175°C
2.5V p-p

Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

Vcc(OV)

I--------~---------I

I
I
I

I
I

I
CONTROL {
INPUTS

I8
I

I __

PeT 21
_

PE2

CLOCK INPUT

9~~

I
I
I
I

I
I

L---------b--- ___ ..j___ --1
16

INf.EANAL BIAS

iJ!I!

••COU~lINIi

128

OUTPUT

OG16

SP8720A & B
ELECTRICAL CHARACTERISTICS
Eel OPERATION
Supply Voltage: VEE = -S.2 ± 0.2SV Vcc = OV
Temperature: A Grade Tamb = -SsoC to +12SoC
B Grade Tamb = -30°C to + 70°C
Characteristics

Symbol

Maximum frequency

fmax

Value
Min. Max.

Units

300

MHz Input = 400-800mV

Note 3

p-p
MHz Input

Note 3

sinewave input
Minimum frequency

fmin

sinewave input
Power supply current

lEE

Conditions

p-p
VEE

Notes

= 400-800mV

= -S.2V

Note 3

ECl output high voltage

VOH

-0.8S

-0.7

VEE

= -S.2V

(2S°C)

ECl output low voltage

VOL

-1.8

-1.S

VEE

= -S.2V

(2S°C)

PE input high voltage

V,NH

-0.93

VEE

= -S.2V

(2S°C)

PE input low voltage

V,NL

-1.62

VEE

= -S.2V

(2S0C)

Clock to ECl output delay

Note 4

Set-up time

2.5

Note 4

Release time

Note 4

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply. frequency and temperature range.
2. The temperature coefficients of VOH = +1.63mV jOe, VOL = +O.94mV jOe and of V IN = +1.22mV jOe but these are not tested.
3. SP8720B tested at 2SoC only.
4. Guaranteed but not tested.

CLOCK INPUT

___ _

--.11f4-"

~tf__

j-'.I_________

I I

i'E INPUT

TRUTH TABLE FOR CONTROL INPUTS

'l..

..L:_ _ _ _ _ _ _ _oJ

OUTPUT

PE1

PE2

Division
Ratio

l
H
l
H

l
l
H
H

4
3
3
3

Fig.3 Timing diagram
NOTE:
.
The set-up time ts is defined as minimum time that can elapse between L-- H transition of control input and the next L -- H clock pulse
transition to ensure that the +3 mode is obtained,
The release time t, is defined as the minimum time that can elapse between a H-L transition ofa control input and the next L-H clock
pulse transition to ensuro that the +4 mode is obtained,

129

SP8720A & B
2000

1000

>e
-,
...

TAMII--5S Clo-125'C

800

t--

~
/

GUA~ANTEED/
/
OPERATING

/
/

*Tested as
specified in
table of
Electrical
Characteristics
/

WINDOW

400

••

N-,

I
300

200

400

INPUT FREQUENCY (MHz)

Fig.4 Typical input characteristics SP8720A

OPERATING NOTES
1. The clock input is biased internally and is coupled to the
signal source with a suitable capacitor. The input signal path
is completed by an input reference decoupling capacitor
which is connected to earth.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from the input to VEE (i.e. Pin 1 to Pin 12). This will
reduce the input sensitivity by approximately 100mV.
3. The circuit will operate down to DC but slew rate must be
better than 100Vl/1s.

4. The Q and Q outputs are compatible with ECI- II but can
be interfaced to ECl 10K as shown in Fig. 7. There is an
internal circuit equivalent to a load of 2k pulldown resistor at
each output.
5. The PE inputs are ECl III/10K compatible and include a
4.3k internal pulldown resistor. Unused inputs can therefore
be left open circuit.
6. The input impedance of the Spa720 varies as a function
of frequency. See Fig. 5.

Fig.S Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 2So C, frequencies in MHz,
impedances normalised to SO ohms.

130

SP8720A & B

,.
OUTPUT TO
SAMPLING

SCOPE

~-------oVEE-5.2V

Fig.6 Test circuit

EeL CONTROL INPUTS

0=4
1 =3

r---~--~~Y-----,

I
I
I
,1

CLOCK INPUT

o---J h----'-<>--.,--[

4.3k

15k

,;t

47
'---V-"L_--'T"""~

I
I

400

L_________

Eel 10K

OUTPUT

r--O--_ _

'--------~~---------L-v"

Fig.7 Typical applications circuit showing interfacing

131

PLESSEY

Semiconductors ___________________

SP8740A&B
SP8741A&B
The SP8740 and SP8741 are ECl counters with ECl10K
compatible output. The SP8740/SP8741 divide by 5 and 6
respectively when either control input is in the high state and
by 6 and 7 respectively when both inputs are in the low state
(or open circuit). An AC coupled input of 600mV is required.

300MHz

5/6

300MHz + 6/7

CLOCK INPUT [ 1

'-../

INTERNAL BIAS DECOUPLING

PEl [ 2
CONTROL INPUTS """"1 [
PE2 3

1SPNC

NC[ 4

13] NC

FEATURES

Veei

•

ECl Compatible Outputs

NC [ •

•

ECl Compatible Control Inputs

•

AC Coupled Inputs (Internal Bias)

OUTPUT

14PNC
12] VEE
11 ]

DO NOT CONNECT

10] Nt
9 ] OUTPUT

DG16
QUICK REFERENCE DATA
•

Fig.l Pin connections - top view

Supply VOltage -5.2V

•

Power Consumption: 240mW

•

Temperature Range:
A Grade: -55°C to +125°C
B Grade: -30°C to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
20mA
-55°C to +150°C
+175°C
2.5V p-p

Vce(OV)

r-----------~------------~

C~~1\~L

{

I
I

I
Q1

8 OUTPUT

_ I
;:; ::1==-=--=--.. .
I

CLOCK INPUT

r_:'

I
I

10--------------4------4--------'

L ____ ~------j------------~
16
INTERNAL BIAS

12
Ve

DEeOUPLING

Fig.2 Functional diagram (SP8740)

132

SP8740/1A 8. B

,
,- - - - - - - - - - - -1- - - - - - - - ---,
VccIOY)

I
I
,

I
I
I

I
I
I
o

C IN~1~~L

{"",.'
iiE2 3 I

CLOCK INPUT

I
I•
,

OUTPUT

I _

9 OUTPUT

L ____ -L _______ L
16
INTERNAL BIAS

I
___________ J

DECOUPUNG

Fig.3 Functional diagram (SP8741)

ELECTRICAL CHARACTERISTICS
Supply Voltage: VEE = -5.2 ± 0.25V Vcc = OV
Temperature: A Grade Tamb = -55°C to +125°C
B Grade Tamb = -30°C to + 70°C

Characteristics

Symbol

Maximum frequency
sinewave input
Minimum frequency
sinewave input
Power supply current
ECl output high,voltage
ECl output low voltage
PE input high voltage
PE input low voltage
Clock to ECl output delay
Set-up time
Release time

fmax

Value
Min. Max.

Units

300

MHz

fmin

lEE
VOH
VOL
VINH
VINL
tp
ts
tr

-0.85
-1.8
-0.93

MHz

60
-0.7
-1.5

mA
V
V
V
V
ns
ns
ns

-1.62
6
2.5
3

Conditions

Notes
Note 3

Input = 400-800mV
p-p
Input = 400-800mV
p-p

Note 3
Note 3

VEE =-5.2V(2SO C)
VEE =-5.2V(25° C)
VEE =-5.2V(25° C)
VEE =-S.2V(25° C)
Note 4
Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over the full specffied supply, frequency and temperature
range of both SP8740 and SP8741.
2. The temperature coefficients of VOH= +1.63mV/oC, VOL= +O.94mV/oC and VIN= +1.22mV/oC but these are not tested.
3. SP8740/1 B tested at 25°C only.
4. Guaranteed but not tested.

TRUTH TABLE FOR CONTROL INPUTS

CLOCK INPUT

Pi INPUTS

OUTPUT

-... .. ......__________________
~

~tr~
I I

IL.L:____________...1

..J

~~-~~~---------

Division
PE1

PE2

Ratio

L
H
l
H

L
L
H
H

S
S
S

Fig.4 Timing diagram SP8740

133

SP8740/1A & B

TRUTH TABLE FOR CONTROL INPUTS

CLOCK INPUT

~ .. ~

_t't--

Pi INPUTS

IL...\:________....I
I I

PE1

PE2

L
L

H
L
OUTPUT

H
H

Division
Ratio

7
6
6
6

Fig.S Timing diagram SP8741
NOTE:

The set-up time t, is defined as minimum time that can elapse between L-H transition of control input and the next L- H clock pulse
transition to ensure that the +5 or 6 mode is obtained.
The release time t, is defined as the minimum time that can elapse between a H-L transition of a control input and the next L-H clock
pulse transition to ensure that the +6 or 7 mode is obtained.
2IlOO

18DO

TAM'~-S5°CtoA25°C

1:
>e

'Tested as
specified in
table of
Electrical
Characteristics

-'200

~
i
~

800

400

••

-r/ /
"N-

/ D::~~~G

GUA'ANTEED/
/

'DO

200

'00

4••

INPUT FREQUENCY (MHz)

Fig.6 Typical input characteristics SP8740/1A

Fig.7 Typical input impedance. Test conditions: supply voltage -S.2V, ambient temperature 2So C, frequencies in MHz,
impedances normalised to 50 ohms.

134

SP8740/1A & B
OPERATING NOTES
1. The clock input is biased internally and is coupled to the
signal source with a suitable capacitor. The input signal path
is completed by an input reference decoupling capacitor
which is connected to earth.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from the input to VEE (i.e. Pin 1 to Pin 12). This will
reduce the input sensitivity by approximately 100mV.
3. The circuit will operate down to De but slew rate must be
better than 100v/us.

4. The Q and Q outputs are compatible with Eel II but can
be interfaced to Eel 10K as shown in Fig. 9. There is an
internal circuit equivalent to a load of 2k pulldown resistor at
load output.
5. The PE inputs are Eel III/10K compatible and include a
4.3k internal pulldown resistor. Unused inputs can therefore
be left open circuit.
6. The input impedance of the SP8740/1 varies as a
function of frequency. See Fig. 7.
7. The SP8740 is not suitable for use in a fixed divide by 6
mode.
-S.2V

J~______~~~__~~--~~~~8~-[:4S~0~__-{:=~
-

INPUT FROM ~
GENERATOR

TO SAMPLING
SCOPE

L-__~____J9~-4:4:~:J~--~-~

OUTPUT TO
SAMPLING
SCOPE

_=-'-~--~-'"

Fig.8 Test circuit

Eel CONTROL INPUTS
o ""8or7
1 "" SorB

PEr

PEi

r - -""":':":":'---JL - - - ' - - ' - - - - - ,

I
I
I
,1

CLOCK INPUT

0---1

I
I

SP874D/l

I
Uk

I
I

15k

,;t

400

1.5k

~ _________ ,..---<~----~--'

L..---------------------1~

_______________________l-v"

Fig.9 Typical applications circuit showing interfacing

135

PLESSEY
SMniconductors __________________________________
SP8735B
600MHz

8 (BINARY OUTPUTS)

The SP8735 is an ECL counter with binary outputs. In
addition, carry outputs are provided in TTL and ECL. The AC
coupled input requires 600mV p-p, and the outputs are open
collectors. A TTL compatible reset is provided, making this
device ideal for instrumentation applications.

'-'

INTERNAL BIAS DECOUPUNG [ 1
'A' OUTPUT [ 2

RESET [ 3

FEATURES
•

Binary Outputs to Open Collectors

•

Reset Input TTL Compatible

•
•

AC Coupled Input
Clock Inhibit ECl Compatible

•

TTL and ECl Compatible Carry Outputs

j CLOCK INPUT INHIBIT

15] NC
14

CLOCK INPUT

NC [4

13] NC

VEE [ 5

12] Vcc(OV)

NC [6

11 ] TTL CARRY OUTPUT

'S' OUTPUT [ 7

10] NC

NC [ .

9 ] Eel CARRY OUTPUT

DG16
Flg.l Pm connectIOns - top view

QUICK REFERENCE DATA
•
•

Supply Voltage 5.2V
Power Consumption: 400mW

•

Temperature Range: 0 to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Binary ourput voltage
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
+11V
-55°C to +150°C
+175°C
2.5V p-p
VEE

'A' OUTPUT
2

1
CLOCK INPUT 18

INHIBIT

------r----

'8' OUTPUT

r---- -----

Vee (OV)

I
"'I- - - . . ,

r-'-~

TTL CARRY

OUTPUT

19 E'6~¥~~V

1
1

1 "'I- - - - '

L ___ _

___ _

0 ___

v•..

RESS1

Flg,2 Funotlonal diagram

136

I
I
1'1

Cl.OCK INPUT 14

I~~ONUA;L~~~

-1

SP87358
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vee ~ OV VEE ,. -S.2V ± 0.2SV
Temperature: Tamb O"C to .-lOuC
0

Characteristics

Symbol

Maximum frequency
(sinewave input)
Minimum frequency
(sinewave input)
Power supply current
Clock inhibit high
voltage
Clock inhibit low
voltage
TTL output high voltage
(pin 2,7)
TTL output low voltage
(pin 2,7)
TTL carry high voltage (pin 11)

fmax

Value
Min. Max.

Units

600

MHz Input

fmln

lEE
V,NH

400-BOOmV pcp

Note S

MHz Input - 400-BOOmV pcp

Note 7

mA VEE' -S.2V
V VEE - -S.2V (2S0C)

Note 6

-0.96

V,NL

-1.6S

VOH

2.4

VOL

0.4

VOH
VOL

ECl carry high voltage (pin 9)
ECl carry low voltage (pin 9)
Edge speed for correct operation
at maximum frequency
Reset on time for correct
operation
Reset input high voltage
Reset input low voltage

VOrl
VOL
tE

-0.9
-1.B

tON

100

V,NH
V,NL

2.4

-S.2V (2S0C)

VEE

10k n from TTL
output to +SV
10k from TTL
output to +SV
Skn from TTL
output to +SV
Sk n from TTL
output to +SV
VEE -S.2V (2S0 C)
VEE = -S.2V (2S0C)

Note 6

10% to 90%

Note 7

V
0.4

-0.7
-1.S
2.S

V
V
ns

O.S

2.4

TTL carry low voltage (pin 11)

Notes

Conditions

Note 6
Note 6
Note 6

Note 7

V
V

Note 6
Note 6

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficient of VOH(ECL) = +1.3mV/oC and VOL= +O.5mV/oC but these are not tested.
3. The temperature coefficient of inhibited threshold voltage = +O.24mV IcC but this is not tested.
4. The test configuration for dynamic testing is shown in Fig.B.
5. Tested at O°C and +70°C only.
6. Tested at +25°C only.
7. Guaranteed but not tested.
100naMIN
REB!T INPUT

-j

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

CLOCK INHIBIT

______________

~r--

CLOCK

'A' OUTPUT

'S'OUTPUT

TTL CARRY

Eel CARRY

.---,L_______
.---,L___________
....J

....J

--.J
Fig.3 Timing diagram

137

SP8735B
1800

I
I

1600

1 1400
g 1200

TAMI·O Cto ·70 C

g 1000

,800

600

I I
I I

~
/

400
200

o
o

I
I I
I
I I
/:
GUARAN~ED'/.
/
OPERATING
/
WINDOW

.I.

I
f"-4..
100

*Tested as
specified above.

I I

IIIIL.}--f
200

300

400

500

600

700

INPUT FREQUENCY (MHz)

Fig.4 Typical input characteristics SP8735

Fig.5 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

OPERATING NOTES
1. The clock input (pin 14) should be capacitively coupled
to the signal source. The input signal path is completed by
connecting a capaCitor from the internal biasdecoupling, pin
1 to ground.
2. In the absence of a signal the devices will self-oscillate.
This can be prevented by connecting a 68k resistor between
the clock input and the negative supply (pin 5).
3. The device will operate down to DC but the input slew
rate must be better than 100V/j.Js.
4. The Eel Carry output (pin 9) is ECl II compatible but
can be interfaced ECl III/10K by the inclusion of two
resistors. See Fig. 7.

138

5. The clock inhibit is compatible with Eel III/10K
throughout the temperature range.
6. The 'A', '8' and TTL Carry outputs are current sources
and require the addition of 10k (pins 2 and 7) and 5k (pin 11)
to +5V for TTL compatibility. See Fig. 6. This gives a fan-out =
1. The fan-out can be increased by buffering the output with
a PNP emitter follower, see Fig. 9.
7. It is important to note that a positive going transition on
either the clock or clock inhibit will clock the device provided
of course that each input is in the low state.
8. Input impedance is a function of frequency. See Fig. 5.

SP8735B

1---------1

10v=r-l5V

I
I
I
I

ECl CARRY OUTPUT - - - . - - -

I
I
OUTPUT

ECl III/10K
COMPATIBLE

~1Sk

~R
____

I
-5.'V
I
L _________ J

R·= 940 OHMS FOR
'A' AND '8' OUTPUTS,
295 OHMS FOR TTL
CARRY OUTPUT

----O-----5,2V

Fig.6 TTL output circuit

Fig. 7 ECL 1/ to ECL II//l0K interface

5:1
SO OHM
MONITOR

-S,2V

Fig.8 SP8735 high frequency test circuit

-----~----------~------~r_--~r_---_t-------1_--- V

TTL OUTPUT

Ct.OCK

iNHiiiT

__________________6-_________

_____-<'-__ 5.'V

Fig.9 Typical application showing interfacing

139

PLESSEY
Semiconductors

IIIII!I"'------------------

SP8743A 450MHz + 8/9
SP87438 500MHz + 8/9
The SP8743 is an ECl counter with ECl 10K compatible
outputs. It divides by 8 when either control input is in the high
state and by 9 when both inputs are low (or open circuit). An
AC coupled input of 600mV p-p is required.

CLOCK INPUT [ 1

CONTROL INPUTS

jm2 [[ ,
PEZ

FEATURES

Ne [ 4
Vcc(OV)[ 5

•
•

ECl Compatible Outputs
ECl Compatible Control Inputs

•

AC Coupled Input (Internal Bias)

'-'

PINTERNAL BIAS DECOUPUNG
lSP Ne
'tEl

PNe
PNe
12P VEE
14

Ncr •

10] Ne

OUTPUT

UDO NOT CONNECT

9] ii'UrPiIT

OG16

QUICK REFERENCE DATA
Fig.1 Pin connections - top view

•

Supply Voltage: -S.2V

•

Power Consumption: 240mW

•

Temperature Range:
A Grade: -SsoC to +12SoC
B Grade: -30°C to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
20mA
-55°C to +150·C
+175°C
2.5V p-p

Vcc(OV)

, - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - ---,
5

I
I
I

I
I8

PEi' , I ; ;

CONTROL INPUTS

PEl

CLOCK INPUT

L _

-------1- ______ ~ _______________ .J
16

INTERNAL BIAS

Vu.

DECOUPLING

Fig.2 Function diagram

140

OUTPUT

ou;:pjjf

SP8743A & B
ELECTRICAL CHARACTERISTICS
Supply Voltage: VEE ~ -5.2 ± 0.25V Vcc ~ OV
Temperature: A Grade Tamb ~ -55°C to +125°C
B Grade Tamb ~ -30°C to +70°C

Characteristic

Symbol

. Maximum frequency
sinewave input
Minimum frequency
sinewave input
Power supply current
ECl output high voltage
ECl output low voltage
PE input high voltage
PE input low voltage
Clock to ECl output delay
Set-up time
Release time

fmax.

Value
Max.
Min.
450
500
40

fmin

lEE
VOH
VOL
V,NH
V,NL
tp
ts
tr

60
-0.7
-1.5

-0.85
-1.8
-0.93

-1.62
6

1
2.5

Units

Grade

MHz
MHz
MHz

A
B
Both

mA
V
V
V
V
ns
ns
ns

Both
Both
Both
Both
Both
Both
Both
Both

Notes

Conditions
Input = 400 - 800mV p-p
Input = 400 - 800mV p-p
Input = 400 - 800mV p-p

Note 4
Note 4
Note 5

VEE=
VEE =
VEE=
VEE=
VEE =

Note 6

-5.2V
-5.2V(25° C)
-5.2V(25°C)
-5.2V(25°C)
-5.2V(25° C)

Note 5
Note 5
Note 5

NOTES
1. Unless otherwise stated the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The temperature coefficients of VOH ~ +1.63mV 1°C, VOL ~ +O.94mV 1°C and of V,N ~ +1.22mV 1°C.
3. The test configuration for dynamic testing is shown in Fig.6.
4. Tested at low and high temperature only (not at 25°C)
5. Guaranteed but not tested.
6. Tested at 25°C only.

TRUTH TABLE FOR CONTROL INPUTS

CLOCK INPUT

~Ir~
I

PEl

PE2

Division
Ratio

l
H
l
H

l
l
H
H

9
8
8
8

---...jIll.--

r'+'--------------------

PEINPUTSIL..i.:- - - - - - - - - - - - ' , :

Fig.3 Timing diagram
NOTE
The set-up time Ie is defined as minimum time that can elapse between L-H transition of control input and the next L- H clock pulse
transition to ensure that the +8 mode is obtained.
The release time t, is defined as the minimum time that can elapse between a H-L transition of a control input and'the next L-H clock
pulse transition to ensure that the +9 mode is obtained.

0.
>

1400

1200

* Tested as

1000

specified in
Table of
Electrical
Characteristics

.00

Z
W

600

...'::>"

400

200

0
0

INPUT FREQUENCY (MHz)

Fig.4 Typical input characteristics of SP8743

141

SP8743A & B
OPERATING NOTES
1. The clock input is biased internally and is coupled to the
signal source with a suitable capacitor. The input signal path
is completed by an input reference decoupling capacitor
which is. connected to earth.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 15k
resistor from the input to VEE (i.e. Pin 1 to Pin 12). This will
reduce the input sensitivity by approximately 100mV.
3. The circuit will operate down to De but slew rate must be
better than 100Vltls.

4. The Q and Qoutputs are compatible with Eel II but can
be interfaced to Eel 10K as shown in Fig. 7. There is an
internal circuit equivalent to a load of 2k pull down resistor at
each output.
5. The PE inputs are Eel III/10K compatible and include a
4.3k internal pulldown resistor. Unused inputs can therefore
be left open circuit.
6. The input impedance of the SP8743 varies as a function
of frequency. See Fig. 5.

Fig.5 Typical input impedance. Test conditions: supply voltage -5.2 V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms.

,.
DUT

...
...

t-------o Vn-6.2V

Fig.S Test circuit

142

OUTPUT TO
SAMPlING
SCOPE

SP8743A & B

r---~--~~Y-----I

I
I
CLOCK INPUT

,.
o---J

I
l

I
I
I

4.3k

I
I

IS'

L------------1:-___________..l._v..

Fig.7 Typical applications circuit showing interfacing

143

PLESSEY _____________________________________
Semiconductors
SP8755A&B
1200MHz + 64
The SPB755 is a divide by 64 prescaler which operates
from a standard 5V TTL supply and will drive TTL directly.
The SPB755A operates over the full military temperature
range (-55°C to +125°C).

Vee [1

FEATURES
•
•

TIL Compatible Output
AC Coupled Input (Internal Bias)

'--"

Ne [2

JBIAS

bINPUT REF

Ne [3

OUTPUT [ 4

PNC

Ne [5

PCLOCK INPUT

Ne [6

apNC

V'E(OVI [7

• PNC
DG14

QUICK REFERENCE DATA
Fig.1 Pin connections - top view

•
•

Supply Voltage: 5V
Power Consumption: 270mW

•

Temperature Range:
A Grade: -55°C to +125°C
B Grade: -30°C to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

BV
±30mA
-55°C to +150°C
+175°C
2.5V p-p

Yco
1

i--------------j---------------l
CLOCK INPUT

I
I
I
10

I
I
I4

I
I

I
INPUT REF

12C)----'

I
~~~I
DECOUPLING 13 I
I
L _________

I
I
I
I

-----1--------- _____ J
7
VEE (OV)

144

Fig.2 Functional diagram

OUTPUT

SP8755A & B
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vee; 5.0 ± 0.25V VEE; OV
Temperature: A grade Tamb ; -55°C to +125°C
B grade Tamb; -30°C to +70°C

Characteristics

Symbol

Maximum frequency sinewave input

fmax

Minimum frequency sinewave input

fmln

Power supply current

lEE

Output high voltage

VOH

Output low voltage

VOL

Value
Min.

Units

Grade

100

GHz
GHz
MHz

SP8755A
SP8755B
Both

Both

Max.

1.2
1.2

2.5
0.45

Conditions
Input; SOO-1200mV p-p
Input; 400-1200mV p-p
Input; SOO-1200mV p-p

Sink current; 5mA

NOTES
1. Unless otherwise stated,the electrical characteristics shown above are guaranteed over specified supply, frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.5.
3. Above characteristics are not tested at 25°C (tested at low and high temperature only).

1400

1200

1000

W
Q

'Tested as
specified in
table of
Electrical
Characteristics

800

:I '00
c

400

.00

1-....-+-+-+-I-+--+--f-+-+-+-~-I-+--!.;£11-1

ott:t:t~~~ttt!j
o
m
800

800

INPUT FREQUENCY (MHz)

Fig.3 Typical input characteristics SP8755AIB

OPERATING NOTES
1. The clock input is biased internally and is connected to
the signal source via a capacitor. The input signal path is
completed by an input referencedecoupling capacitorwhich
is connected to earth.
2. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting an 18k

resistor between input and VEE (i.e. Pin 10 to Pin 7). This will
reduce sensitivity by approximately 100mV.
3. The device will operate down to DC but input slew rate
must be better than 100VljJs.
4. The output stage is a standard totem pole TTL and can
therefore be interfaced directly to TTL.

145

SP8755A & B

Fig.4 Typical input impedance. Test conditions: supply voltage SV, ambient temperature 2SoC. Frequencies in MHz, impedances
normalised to SO ohms.
'sv

,.
1k

SAMPLING

f---c:::J-----c=~~ ~~~~i

Fig.S Test circuit

INPUT~

I•

...---<>'-_TTL OUTPUT

146

Fig.6 Typical applications circuit showing interfacing

PLESSEY
Semiconductors _____________________________________
SP8782A & B
1GHz

16/17, 32/33 MULTI-MODULUS DIVIDER

The SP8782 is a 1GHZ multi modulus divider which
divides by 16/17 when the Ratio select pin is low and 32/33
when this pin is high The Modulus control pin selects
either a divide by 16 or 32 when the pin is high or 17 or 33
when the pin is low. The device uses resynchronisation
techniques to reduce the effects of propagation delays in
frequency synthesis. The 'A' Grade device is characterised
over the full military temperature range of -55°C to
+ 125°C. the 'B' Grade over the industrial range of -40°C
to +85°C.

RATIO SELECT
CLOCK INPUT

EJ
SP8782

CLOCK INPUT

VEE

FEATURES

VCC
OUTPUT

MOD CONTROL

DG8 (SP8782A), DP8 (SP8782B)

• Advanced Resynchronising Techniques to Negate
Loop Delay Effects
• CMOS Compatible Output Capability
• Multi-Modulus Division

QUICK REFERENCE DATA
.Supply Voltage Range: 4V to 6V
• Full Military Temperature Range:-55°C to + 125°C

RATIO
SELECT
1

Fig. 1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Clock input level
Junction temperature
Storage temperature range
SP8782A
SP8782B

6V
2.5V pop
+ 175°C
-55°C to + 150°C
-55°C to '+ 125°C

Vee

,---- ------

---,

I
I

I
I
I

I
CLOCK INPUT 2

I
1----07 OUTPUT
I

+ 16117

+ 32133

CLOCK INPUT 3

I
I
I
_ _ _ .J

I
I
L. _ _ _ _ _ _ _ _ _
4

VEE

MODULUS
CONTROL
INPUT

Fig.2 SP8782 functional diagram

147

SP8782A1B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)
Tamb
SP8782A: -55'C to + 125'C, SP8782B -40'C to + 85'C, Vee

= + 4V to

+ 6V

Value
Characteristic

Max. sinew ave input frequency
Min. sinewave input frequency
Min. slew rate for LF operation
Power supply current lEE
Output low voltage
Output high voltage
Modulus control input high voltage
Modulus control input low voltage
Modulus control input high current
Modulus control input low current
Ratio select input high voltage
Ratio select input low voltage
Ratio select input current
Clock to output propagation delay
Set up time
Release time

2,3
2,3
2,3
8
7
7
5
5
5
5
1
1
1
2,3,7
5
5

Conditions

Units
Min.

Max.

0
3.2
0. 7Vee
0
0.6
-0.6
0.6Vee
0
-10

GHz
MHz
Vc"Il S
mA
V
V
V
V
mA
mA
V
V
[.lA
ns
ns
ns

50
100
40
1.7
Vee
Vee
0.4Vee
0.9
-0.9
Vee
0.3Vee
10
3
1
1

Input
Input

=200m V - 1200mV p-p
=400mV - 1200mV p-p

Outputs unloaded

At driver end of 3k resistor
At driver end of 3k resistor
Via 3k to Vee
Via 3k to OV

1600r-----~----~------~----~--~~----~

*
INPUT
AMPLITUDE
(mVp-p)

200

400

600

800

INPUT FREQUENCY (MHz)
Fig.2 Typical input characteristics SP8782

148

1000

1200

As specified
in Table of
Electrical
Characteristics

SP8782A1B

MODULUS
3k'
CONTROL
INPUT o--------C=:J-- 5
6

RATIO SELECT

r----------------- 6------------------- O-----------------,

PIN 6 IS GROUNDED
~ TO IMPROVE ISOLATION
~ : BETWEEN THE OUTPUT
I AND MOD CONTROL
I INPUT
I

DIVIDE BY
16117, 32133

, THE 3k RESISTOR REDUCES THE AMPLITUDE OF THE CONTROL
SIGNAL TO MINIMISE RADIATION

Fig.3 Typical applications showing mterfacing

"i1

Flg.4 Typical mput Impedance. Test conditions: supply voltage 5V, ambient temperature 25°C,
frequencies in MHz, impedancies normalised to 50 Ohms

149

PLESSEY

Semiconductors ___________________

SP8785A&B 1000MHz + 20/22
SP8786A&B 1300MHz + 20/22
The SP8785 and SP8786 are high speed 2 modulus
counters for use up to 1.0 and 1.3GHz respectively. They
feature ECl compatible control inputs and outputs and are
available in either the -30°C to +70°C (8 Grade) or -55°C to
+125°C (A Grade) temperature ranges.

Veel10VI

OUTPUT

'--'

16] Vec2 (OV)

15J m
14] PEi

OUTPUT [ 4

FEATURES

13] NC

NC [ 5

12 ] CLOCK INPUT

•

ECl Compatible Outputs

NC [6

"P VREFI

•
•

AC Coupled Input
Control Inputs ECl Compatible

NC [ 7

lOP VREF2

VfE [8

QUICK REFERENCE DATA

DG16

Flg.l Pin connections - top view

•
•

Supply Voltage: -5.2V
Power Consumption: 450mW (Typ.)

•

Temperature Range:
A Grade: -55°e to +125°e
B Grade: -30 o e to + 70 0 e

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock liP voltage

-8V
20mA
-55°C to +150°C
+175°C
2.5V p-p

Vee1

Vcc2

,---- __ -------!,---- -!,!---- -- ---- ---,
I

I
I

I
I
I

I
CONTROL {PE114
INPUTS

CLOCK INPUT

I
I

I
I
I
I

L.,---....1

____ _

I
-----------------------~

VllEF1

VRu2

Fig.2 Functional diagram

150

120- - - - - - ' C ' - \ P

OUTPUT

SP8785/6A & B
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vee = OV VEE = -5.2V ± 0.25V
Temperature: A grade Tease = -55°C to +125°C (case temperature)
B grade Tamb = -30°C to +70°C

Characteristics
Maximum toggle frequency
sinewave input

Symbol
fmax

Value
Min. Max.
1.0
1.3

Conditions

Grade

GHz

SP8785

Input

= 400-1200mV

Note 4

SP8786

p-p
Input

= 600-1200mV

Note 4

GHz

Minimum toggle frequency
sinewave input
Current consumption

fmin

150

MHz

All

lEE

115

All

Output low voltage

VOL

-1.85

-1.62

All

Output high voltage

VOH

-0.93

-0.78

All

p-p
Input = 400-1200mV
p-p
Input = 400-1200mV
p-p
VEE = -5.2V
outputs unloaded
VEE = -5.2V
output load = 4300
VEE =-5.2V (25° C)

Minimum output swing

VOUT

500

All

output load = 4300
VEE =-S.2V(2S0 C)

1.3

Clock to output delay
Set up time
Release time
PE input high voltage
PE input low voltage

GHz

Is
tr
V,NH
V,NL

Notes

Units

ns
ns
ns
V

1
1
-0.93
-1.62

SP8786

All
All
All
All
All

output load = 4300
VEE = -S.2V
VEE = -S.2V
VEE = -5.2V
VEE=-S.2V(2S0C)

Note 4
Note 5
Note 6

Note 4
Note S
Note S
Note S

VEE=-S.2V(2S°C)

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over specified supply, frequency and temperature range.
2. The A grade devices must be used with a heat sink to maintain chip temperature below+175°C when operating at an ambient of+125°C.
3. The temperature coefficient of V,NL & V,NH = +0.8mV JOC, of VOH = +1.2mV jOe but these are not tested.
4. Tested at low and high temperatures only.
5. Guaranteed but not tested.
8. Tested at 25°C only.

CLOCK INPUT

FiE

~ ;-Ir
it1-_______________
]I-:------------I

INPUTS

04 OUTPUT

---.Jr------'~---L

m
___..110L_ _J----"'----L
_____

TRUTH TABLE FOR CONTROL INPUTS

PE1

PE2

L
L

H
H
H

H
H

Division
Ratio
22
20
20
20

Fig.3 Timing diagram
NOTES
The set up time ts is defined as minimum time that can elapse between L-H transition of control Input and thelnext'L-H clock pulse transition to
ensure +20 mode is selected.
The release time t, is defined as minimum time that can elapse between H..... L transition of the control input and the next L-H clock pulse
transition to ensure the +22 mode is selected.

151

SP8785/6A & B

1400
1200

'Tested as
specified in
table of
Electrical
Characteristics

"' 1000

~
~

E
!E

BOO

...
...
...
0
0

200

400

600

BOO

1000

1200

1400

INPUT FREQUENCY (MHz)

Fig.4 Typical characteristics SP8786

Fig,5 Typical input impedance. Test conditions: supply voltage 5,2V, ambient temperature 25° C, frequencies in MHz,
impedances normalised to 50 ohms,

OPERATING NOTES
1, The clock input (pin 12) should be capacitively coupled
to the signal source, The input signal path is completed by
connecting a decoupling capacitor from VREF1 (pin 11) to
ground. VREF2 (pin 10) should also be decoupled with a
suitable capacitor, see Figs, 6 and 7,
2. If no signal is present the circuit device will self-oscillate.
If this is undesirable it may be prevented by connecting a 10k
resistor from the input to VEE (I.e. pin 12 to pin 8),
3. The input can be operated at very low frequencies but
slew rate must be better than 200VljJs,
4, The emitter follower outputs!require!ai4300 pull-down
resistor and are compatible with Eel III/10K. An equal load

152

on an unused output will reduce distortion,
5, The PE inputs are ECl III/10K compatible and include a
4,3k pull-down resistor. Unused inputs can therefore be left
open,
6. The input impedance of the SP878S/6 is a function of
frequency, see Fig. 5. These impedance variations may give
the effect of large variations in sensitivity because of the
loading of the source by the device. For best results
impedance matching should be used.
7, Note that all components should be suitable for the
frequency in use.

SP878S/SA & B

r ....--....r.'l.L.__

~1n

I"-....._+-I~

OUTPUTSTO
SAMPLING
SCOPE

'-r::~~-r:-'
TO

430

~~~~~ING ~==}---{=33::JH

~--+--+-_-,.2V

Fig.6 Toggle frequency test circuit

,---I

1 and 16

...---------------...-.....;l
1

1
1

o-Jt-'~2r l_~-{

'--Q=---"-_

EeL III/10K

':;';;

'",;t :L ________ _

430

....--'.2V

~--------+-

Fig.7 Typical application circuit showing Interfacing

153

PLESSEY

Semiconductors ___________________

SP8789
225MHz + 20/21 TWO MODULUS DIVIDER

The SP8789 is a low power programmable -;-20/21
counter.lt divides by 20, when the control input is in the high
state and by 21 when in the low state. An internal voltage
regulator allows operation from a wide range of supply
voltages.

\,J

CONTROL INPUT [ 1
OUTPUT Vcc2 [ 2

8] Vet1
7 ] REF OECOUPlING

SP8789
OUTPUT [ 3

6 ] INTERNAL BIAS DECOUPlING

V"IOV) [4

Sp INPUT

FEATURES

•
•
•
•

DP8, MP8

Very Low Power
Control Input and Output CMOS/TTL Compatible
AC Coupled Input
Operation up to 9.5V using Internal Regulator

Flg.l Pm connections - top View

ABSOLUTE MAXIMUM RATINGS
Supply voltage
6.0V pins 7 & 8 tied
Supply voltage
13.5V pin 8, pin 7 decoupled
-55°C to +125°C
Storage temperature range
Max. junction temperature
+175°C
Max. clock input voltage
2.5V p-p
Vcc2
Max. 10V

QUICK REFERENCE DATA

•
•
•

Supply voltage: +5.2V or 6.8 to 9.5V
Power consumption: 26mW Typical
Temperature range: -40°C to +85°C

VCC1
100ntrl;
VCC2

r---------

2----8

----,

o---J1n!I-_~Is~__.r---I
DIVIDE BY
20/21
16
INTERNAL
[-:-,r---L---,,....-_J
BIAS
I
DECOUPLING ~1n
rrln
I
16k
CLOCK
INPUT

L_¢ ___
n7n
VEE (OV)

1_ _ _ _ _

CONTROL
INPUT

3_ _ _ _

OUTPUT

Fig.2 Functional diagram SP8789

154

7_ _ _
_

REF

,;t DECOUPLE

I
I
I
I
I
.-J

SP8789
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vcc 1 & 2 = 5.2V ± 0.25V or 6.8V to 9.5V (see Operating Note 7);
VEE = OV; Temperature Tamb = -40°C to +85°C
Characteristic

Symbol

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)

fmin

Power supply current
Control input high voltage
Control input low voltage
Output high voltage

lEE
VINH
VINL
VOH

Output low voltage

VOL

Units

Notes

225

MHz

Note 4

Input = 200-800mV p-p

MHz

Note 4

Input = 400-800mV p-p

mA
V
V
V

Note
Note
Note
Note

4
2
2.4

ts
tr
tp

Set up time
Release time
Clock to output propagation time

Value
Min. Max.

Conditions

4
4
4
4

Pins 2, 7 and 8 linked
Vcc = 4.95V 10H = 100pA

0.5

Note 4

Pin 2 linked to 8 and 7
10L = 1.6mA

ns
ns
ns

Note 3
Note 3
Note 3

25°C
25°C
25°C

14
20

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.6.
3. Guaranteed but not tested.
4. Tested only at 25°C.

CLOCK INPUT

LIlI111.J1..I1I _-_- _1IlIUUUUl.IlJ' _-_- _'UU1JU1IU1J' _-_-_lJlfUUlIU1IUUUL
-j

CONTROL INPUT --,
OUTPUT

rlr

~ !-ts
~- - -

11-

--"L-_~_~---~

__I~

TRUTH TABLE FOR CONTROL INPUTS
Control
input

Division ratio

0
1

21
20

Fig.3 Timing diagram SP8789
NOTES
The set-up time tsis defined as minimum time that can elapse between L-H transition of control input and next L-H clock pulse transition to
ensure +20 mode is selected.
The release time tr is defined as minimum time that can elapse between H-L transition of the control input and the next L-H clock pulse
transition to ensure the +21 mode is selected.

1600
1400

I>.
> 1200

VCC = 4.95V TO 5.45V PINS 7 AND 8 CONNECTED
TOGETHER. Tamb = -40°C to +85°C

w 1000

'Tested as specified
in table of
Electrical Characteristics

:::;)

5...

800

::&

600

....:::;)

...;!!;

400
200
0

100
200
INPUT FREQUENCY (MHz)

FigA Input sensitivity SP8789

300

155

SP8789
OPERATING NOTES
1. The clock input (Pin 5) should be capacitivelycoupled to
the signal source. The input signal path is completed by
coupling a capacitor from the internal bias decoupling, Pin 6
to ground.
2. The output stage which is normally open collector (Pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V line via aSk resistor butthe output
sink current should not exceed 2mA. If interfacing to TTL is
required then Pins 2 and 7 should be connected together to
give a fan-out
1. This will increase supply current by
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
better than 20Vl/Js is required.
4. The mark space ratio of the output is approximately 1.2:1
at 200MHz.

5. Input impedance is a function of frequency. See Fig.5.
6. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 150k
between unused input and ground. This reduces the input
sensitivity by typically 50-100mV p-p.
7. The internal regulator has its input connected to Pin 8,
while the internal reference voltage appears at Pin 7 and
should be decoupled. For use from a 5.2V supply, Pins 7 and
8 should be connected together, and 5.2V applied to these
pins. For operation from supply voltages in the range +6.8V
to +9.5V, Pins 7 and 8 should be separately decoupled,·and
the supply voltage applied to Pin 8.

Fig.5 Typical input impedance. Test conditions: supply voltage S.2V, ambient temperature 25°C, frequencies in
MHz, impedances normalised to 50 ohms.

VCC OF MODULUS
CONTROL DEVICE

D----~VCC1

OUTPUT

[H-t-i

'--_ _ _-'

156

Fig.6 Toggle frequency test circuit

50n
MONITOR

50n
SIGNAL
SOURCE

SP8789A
200M Hz -7- 20/21 TWO MODULUS DIVIDER

The SP8789A is a low power programmable -;.-20/21
counter which operates over the full Military temperature
range. It divides by 20 when the control input is in the high
state and by 21 when in the low state.

CONTROL INPUT [ 1

'-../

OUTPUT [

FEATURES

SP8789A
6 ] INTERNAL BIAS OECOUPUNG

V,,(DV) [ 4

•
•

Very Low Power
Control Input and Output CMOS/TTL Compatible

•

AC Coupled Input

8J Vee I

7J Vee 2

OUTPUT Vee [ 2

5] INPUT

DGB
Fig.1 Pin connections - top view

QUICK REFERENCE DATA
•

Supply voltage: +5.2V

•

Power consumption: 26mW Typical

•

Temperature range: -55°C to +125°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage:
Storage temperature range:
Max. junction temperature:
Max. clock input voltage:

6.0V Pins 7 & 8 tied
-55°C to +150°C

+175°C
2.5V p-p

r-- - -

- -

-.!""2

....:.-,;1;

T-I- _---,
8

CLOCK
INPut

o--u-1n~ _~1!.5---f----l
DIVIDE BY

20/21
16
INTERNAL
[-:-'r---t--r--J
BIAS
I
DECOUPLING ..,..In
rrln I
16k
L_~ ___ l_ _ _ _ _

n7n
VEE COV)

CONTROL
INPUT

3_ _ _ _ _ _ _ _

--1

OUTPUT

Fig.2 Function diagram SP8789A

157

SP8789A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vcc 1 & 2

= 5.2V ± 0.25V;

Characteristic

Symbol

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)

fmin

Power supply current
Control input high voltage
Control input low voltage
Output high voltage

lEE
VINH
VINl
VOH

Output low voltage

VOL

Set up time
Release time
Clock to output propagation time

ts
tr
tp

VEE

=OV;

Temperature Tamb

= -55°C to

Value
Min. Max.

Units

Notes

200
150

MHz
MHz

Note 3

+125°C

Conditions
Input
Input

20
50

MHz
MHz

Note 3

7
5.2
2

mA
V
V
V

Note 4
Note 4
Note 4
Note 4

0.5

Note 4

Pin 2 linked to 8 and 7
10l = 1.6mA

ns
ns
ns

Note 3
Note 3
Note 3

25°C
25°C
25°C

2.4

14
20

Input
Input

= 200-400mV p-p
= 200-800mV p-p
= 400mV p-p
= 200mV p-p

Pins 2, 7 and 8 linked
Vcc = 4.95V 10H = 100pA

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.B.
3. Guaranteed but not tested.
4. Tested at 25°C only.

CLOCK INPUT

1.nn.fU1.I\.I _- _- _"UlIlfUUUl1U"_-_- _"UlI1I1.Il.rU1I _-_-_1.11.IlIU1Il.fl

-j

CONTROL INPUT ---,
OUTPUT

r'r

--j j-Is

1~-

~-----------

~_~_---.r----~_:!2

___..J---

TRUTH TABLE FOR CONTROL INPUTS
Control
inpuls

Division ratio

0
1

21
20

Fig.3 Timing diagram SP8789A

NOTES
The set·up time Isis defined as minimum time that can elapse between L-H transition of control input and next L-H clock pulse transition to
ensure +20 mode is selected.
The release time tr is defined as minimum time that can elapse between H-L transition of the control input and the next L-H clock pulse
transition to ensure the +21 mode is selected.

158

SP8789A

'Tested as specified
in table of
Electrical Characteristics

100

200

300

INPUT FREQUENCY (MHz)

FigA Input sensitivity SP8789A

OPERATING NOTES
1. The clock input (Pin 5) should be capacitively coupled to
the signal source. The input signal path is completed by
coupling a capacitor from the internal bias decoupling, Pin 6
to ground.
2. The output stage which is normally open collector (Pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V lineviaa 5k resistorbutthe output
sink current should not exceed 2mA. If interfacing to TTL is
required then Pins 2 and 7 should be connected together to
1. This will increase supply current by
give a fan-out
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
beUer than 20VlJ.ls is required.

4. The mark space ratio of the output is approximately 1.2:1
at 200MHz.
5. Input impedance is a function of frequency. See Fig.5.
6. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 150k
between unused input and ground. This reduces the input
sensitivity by typically 50-100mV p-p.
7. The supply voltage regulator which allows the SP8789 to
be used at supply voltages up t09.5V isNOTavaiiableforuse
in the A Grade device: the SP8789A is ONL Y available for
operation from 5.2V supply, and therefore Pins 7 and 8
should always be externally connected together.

Fig.5 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 25° C, frequencies in
MHz, impedances normalised to 50 ohms.

159

SP8789A

VCC OF MODULUS
CONTROL DEVICE

+5.2V

OUTPUT

11-+-1--1

______~

Fig.6 Toggle frequency test circuit

160

son

MONITOR

son

SIGNAL
SOURCE

PLESSEY

Semiconductors __________________

SP8790A&B
60MHz + 4 (2-MODULUS EXTENDER)
The SPB790 is a divide-by-four counter designed for use
with 2-modulus counters. It increases the minimum division
ratio of the 2-modulus counter while retaining the same
difference in division ratio. Suitable for low power frequency
synthesis interfacing to CMOS or TTL.

CLOCK INPUT

FEATURES
•
•
•

CiiiCKiiPiIT

CONTROL INPUT -

Very Low Power
Control Input and Counter Output will
Interface Directly to TIL or CMOS

CONTROL OUTPUT

"COUNTER OUTPUT
NC

eM8

Interfaces to SP8000 Programmable
2 Modulus Counters

Fig.l Pin connections

QUICK REFERENCE DATA
•
•

Supply Voltage: 5.0V
Power Consumption: 40mW

•

Temperature Range:
A Grade: -55°C to +125°C
B Grade: -30°C to +70°C

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Open collector output
Storage temperature range
Max. junction temperature
Max. clock liP voltage
Output sink current

BV
12V
-55°C to +150°C
+175°C
2.5V pop
10mA

CONTROL INPUT

1----' -CONTROL 2
OUTPUT

Vee

-----------t-------,

I
I
I
I
I

I
I
I

I
I
I
I

I
o.

H-O--IOUTPUT
STAGE

Q~---t

I
I

I
L
_____ _
•
CI.OCK INPUT

__________ b_____
~------~

I
I
3

g6~~;E~L~EUCTTp~

I
I
I
J

5
Vu JOY)

0i1SCK INPUt
Not~,

NEGAflVE GOtHai Q~ut .wOULD
CLOCK FOI..l.OWING STAGE

Fig.2 Functional diagram

161

SP8790A & B
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vee = 5V ± 0.25V VEE = OV
Temperature: A grade: -55°C to +125°C
B grade: -30°C to +70°C

Characteristics

Symbol

Value
Min. Max.

Maximum frequency
sinewave input
Power supply current
Control input high voltage
Control input low voltage
Output high voltage (pin 3)

fmax

lEE
VrNH
VrNL
VOH

3:5
0

Output low voltage (pin 3)

VOL

Output high voltage (pin 2)
Output low voltage (pin 2)
Clock to counter output
-ve going delay
Clock to counter output
+ve going delay
Clock to control output
-ve going delay
Clock to control output
+ve going delay
Control input to control
output -ve going delay
Control input to control
output +ve going delay

VOH
VOL
tpHL

Conditions

Units

Tested as a
controller. See Fig.4

MHz
11
10
1.5

mA
V
V
V

0.4

4.5
3.7
25

V
V
ns

tpLH

tpHL

tpLH

tpHL

4.27
3.28

Pin 3 via t.6k
to +10V
Pin 3 via 1.6k
to +10V
Vee = 5.2V (25°C)
Vee = 5.2V (25°-C)

Notes
Note 3
Note
Note
Note
Note

Note 3

Note 4
Note 4
1Okn pull-down
on control OIP
10kn pull-down
on control OIP
1Okn pull-down
on control OIP
10knpull-down on
on control OIP

Note 4
Note 4
Note 4
Note 4

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full supply, frequency and temperature range.
2. The test configuration for dynamic testing is shown in FigA.
3. Tested at low and high temperatures only.
4. Guaranteed but not tested.
CLOCK INPUT

CONTROL INPUT

COUNTER OUTPUT
(PIN 3)

CONTROL OUTPUT
(PIN 2)

'r--1

L...--..J

r--1

L...--..J

N.B. IF CONTROL INPUT ='1' THEN CONTROL OUTPUT" '1'

Fig.3 Timing diagram

162

3
3
3
3

L-

SP8790A & B
VCC

VCC

CONTROL OUTPUT

0.1/1

FIN SIGNAL SOURCE
400mV POP 300MHz

r-~---"'_---'---' f------o

0j1/1 16

u-----o

OUi~UT
MONITOR
SCOPE

CONTROL INPUT
3.5V FOR 20
1.5V FOR 21

Fig.4 Test circuit

CMOSlTTl DIP

Fig.5 Typical interfacing to suppress self oscillation with no input signal

OPERATING NOTES
1. The device will normally be driven by capacitively
coupling the inputs to outputs of a 2-modulus divider. See
Figs. 4 and 5. The maximum frequency of the device when
used as a controller is limited by the internal delays and will
not operate above 60MHz. When used as a prescaler the
device will operate in excess of 80M Hz, the maximum
frequency being limited by saturation of the counter output
stage.
2. The device is normally driven from very fast edges of a2modulus divider and therefore there is no input slew rate
problem.
3. The control input is TTUCMOS compatible.
4. The counter output (pin 3) interfaces into CMOSITTL by

the addition of a pull-up resistor. For interconnecting to
CMOS the output can be connected via a pull-up resistor to
supply which should not exceed 12V.
5. When used as a controller the circuit will self-oscillate.
This can be prevented by using one of the arrangements as
shown in Fig. 5.
6. The control output, which includes an internal 16k pulldown resistor is ECL compatible and interfaced directly into,
for example, SP8695. See Fig. 5.
7. The propagation delays stated are with a 10k pull-down
resistor which is input pull-down of the SP8695. For
Interfacing into the SP8643/47 series which have 4.3k pulldowns, the propagation delays will be reduced.

163

PLESSEY

Semiconductors ___________________

SP8792 225M Hz + 80/81
SP8793 225MHz + 40/41
WITH ON-CHIP VOLTAGE REGULATOR
The SP8792 and SP8793 are low power programmable
+80/81 and +40141 counters, temperature range: -40" C to
+85D C. They divide by 80(40) when control input is in the
high state and by 81(41) when in the low state. An internal
voltage regulator allows operation from a wide range of
supply voltages.

MODULUS CONTROL INPUT I 10

"'"

Vee1

OUTPUT Vee I 2

Vcc2

OUTPUT I 3

INPUT OECOUPUNG

INPUT

ovl

DPB
MPB
FEATURES

•
•
•
•

Fig.l Pin connections - top view

Very Low Power
Control Input and Output CMOS/TTL Compatible
AC Coupled Input
Operation up to 9.5V using Internal Regulator
ABSOLUTE MAXIMUM RATINGS
Supply voltage
6.0V pins 7 & 8 tied
Supply voltage
13.5V pin 8, pin 7 decoupled
-40 DC to +85 DC
Storage temperature range
Max. junction temperature
+175 D C
Max. clock input voltage
2.5V p-p
10V
Vcc2 max

QUICK REFERENCE DATA

•
•

Supply Vo~age: +5.2V or 6.8V to 9.5V
Power Consumption: 26mW

Vcc1

vc;2

;;;;, 100n

, - - - - - - - - - - - - --------- - - - - ,
I
I

--------1lnl--25~1---_r;;;;;;;;_;;;_;~
DIVIDE BY 80/81

=~
'~

I
•I

~~I

I
I
I

DIYI~:.:.~O/41

L-~---:O~~R:L- - - - --;;-.i.:--------- ~~ __ .J
VEE IOV)

INPUT

;;;;,

Fig.2 Functional diagram

164

01 VT,oOER

SP879213
ELECTRICAL CHARACTERISTICS

=
=

Supply Voltage: Vcc
5.2V ± 0.25V or 6.8-9.5V (See Operating Note 6)
Temperature: Tamb
-40°C to +85°C
Characteristic

Symbol

Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Control input high voltage
Control input low voltage
Output high voltage

fmax

Value
Min.
Max.

Output low voltage

4
2
2.4

VOL

Set up time
Release time
Clock to output propagation time

MHz
MHz
mA
V
V
V

20
7

lEE
VINH
VINl
VOH

ts
tr
tp

= OV

Units

225

fmin

VEE

0.5

ns
ns
ns

14
20

Notes

Conditions
Input
Input

= 20G-800mV
= 400mV p-p

p-p

Pins 2,7 and 8 linked
Vcc = 4.95V 10H = 100flA
Pin 2 open or linked
to 8 and 7 10l = 1.6mA
25°C
25°C
25°C

Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 3
Note 3
Note 3

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.S.
3. Guaranteed but not tested.
4. Tested at 25°C only.

CLOCK 'NPUT

lJlIlIlIlI1I _-_- _1..I1Il.nJlJUU1 _- _- _1JlJ1IUU1Il.I _-_-_1nnJUU1JUU1IUL
~

CONTROL INPUT

i'r

~_ ... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

- t--t.
--.t-t---------------

41(21)

40(20)

OUTPUT ~-----~_~!2~}_~---------',-_ _ _ __

TRUTH TABLE FOR CONTROL INPUTS
Division Ratio

Control
Inputs

SP8792

SP8793

Fig.3 Timing diagram SP8792(3
NOTES
The set-up time ts is defined as minimum time that can elapse between L-H transition of control input and the next L-H clock pulse transition to
ensure +80 or 40 mode is selected.
The release time t, is defined as minimum time that can elapse between H-L transition of the control input and the next L-H clock pulse
transition to ensure the +81 or 41 mode is selected.
1800

0:
0.

r-"T'"-r-r-"T'"-r-,.-"T'"-r-"-"T'"-r-,

1---+--+-+-+--+-+-+--+-+-+--+-1
1400 1---+--+_+-+--+_+-+---+_+-+--+-1
1200 1---+--+-+-+--+-+-+---+-+-+---+-1
1000 1---+--+-+-+--+-+-+---+-+-+---+-1
1600

=
C

~
~
~

BOO

!:;
~

600 I

1-.,J,.-"""7"l.-+-""7"'.I--)--"'7"-I---+--+--I

H0GlJkT~/
V
;r, /~/1-+--+---1
"",

*Tested as
specified in
table of
Electrical
Characteristics

//Ol>ERATING '';/ /

400 , . . .

100

300

INPUT FREQUENCY (MHz)

Fig.4 Input sensitivity SP8792(SP8793

165

SP879213
OPERATING NOTES
1. The clock input (pin 5) should be capacitively coupled to
the signal source. The input signal path is completed by
coupling a capacitor from the internal bias decoupling, pin 6,
to ground.
2. The output stage which is normally open collector (pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V line via a 5k resistor but the output
sink current should not exceed 2mA. If interfacing to TTL is
required then pins 2 and 7 shou,ld be connected together to
give a fan-out = 1. This will increase supply current by
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
better than 20V/~s is required.
4. The mark space ratio of output is approximately 1.2: 1 at
200M Hz.

5. Input impedance is a function of frequency. SEte Fig. 5.
6. The internal regulator has its input connected to pin 8,
while the internal reference voltage appears at pin 7 and
should he decoupled. For use from a 5.2V supply, pins 7 and
8 should be connected together, and 5.2V applied to these
pins. For operation from supply voltages in the range +6.8V
to +9.5V, pins 7 and 8 should be separately decoupled, and
the supply voltage 'applied to pin 8.
7. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 150k
between unused input and ground. This reduces the input
sensitivity by typically 50-100mV P-p.

Fig.5 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 25° C. frequencies in MHz,
impedances normalised to 50 ohms.

Vee OF

MODULUS

CONTROL DEVICE

CONTROL
INPUT

Yee1

n-----~--oy~
OUTPUT

100n

Fig.6 Toggle frequency test circuit

166

SEE OPERATING

NME6

~ MO:iOR

[}-t--H

500
SIGNAL
SOURCE

PLESSEY

Semiconductors ___________________

SP8792A 200MHz -;- 80/81
SP8793A 200MHz -;- 40/41
The SP8792A and SP8793A are low power programmable
+80/81 and +40/41 counters which operate over the full
Military temperature range. They divide by 80(40) when the
control input is In the high state and by 81(41) when in the
low state.

CONTROL INPUT [ '0

....,

OUTPUTVcc[ 2

7PVCC2

OUTPUT[ 3
VEE!OV)[ 4

FEATURES

•
•
•

ap Vee1

pINPUT DECOUPLING

'PINPUT

DGB

Very Low Power
Control Input and Output CMOS/TTL Compatible
AC Coupled Input

Fig.1 Pin connections - top view

QUICK REFERENCE DATA

•
•
•

Supply Voltage: +5.2V
Power Consumption: 26mW typical
Temperature Range: -55°C to +125°C

ABSOLUTE MAXIMUM RATINGS

6V pins 7 & 8 linked
-55°C to +150°C
+175°C
2.5V p-p

Supply voltage
Storage temperature range
Max. junction temperature
Max. clock liP voltage

VCC1
VCC2

,-------------

~~oon
8
7

n7n
---------

I
I

I
I
1n
51
~~~J: ~ 1----"01- - - - 1 DIVI~;.!~2~18.
6I
,-----"0----1

DECOUPLING I

1n,;t

DIVIDE BY 4014.
(SP8793)

I
I
L_~_----,-VEE(OV)

C?~:S.fL

- - - - - - 3 - - - - - - - - --- ____ ...J
OUTPUT

Fig.2 Functional diagram

167

SP879213A
ELECTRICAL CHARACTERISTICS
Supply Voltage: Vcc = 5.2V ± 0.25V Vff. = OV
Temperature: T8mb = -55°C to +125°C
Value
Min.
Max.

Symbol

Characteristic
Maximum frequency (sinewave input)

fmax

Minimum frequency (sinewave input)
Power supply current
Control input high voltage
Control input low voltage
Output high voltage

fmln
lEE
V,NH
V,NL
VOH

Output low voltage

VOL

Set-up time
Release time
Clock to output propagation time

200
150

MHz
MHz
MHz
mA
V
V
V

20
7
4
2
2.4

ts
tr
tp

Conditions

Units

0.5

ns
ns
ns

14
20

Input =200 - 400mV p-p
Input =200 - 800mV p-p
Input =400mV p-p

Pins 2,7 and 8 linked
Vcc= 4.95V IOH= -100pA
Pin 2 linked to 8 and 7
IOL= 1.6mA
25°C
25°C
25°C

Notes

Note 3
Note
Note
Note
Note

4
4
4
4

Note 4
Note 3
Note 3
Note 3

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply, frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.6.
3. Guaranteed but not tested.
4. Tested at 25°C only.

CLOCK 'NPUT

"UU1J1IlJl.J _- _- _l..I1J1I1fLIl.f _-_- _l.ILflf1JU1.flf _-_- _~
I

CONTROL INPUT

..... "

----...

...--11

-----------~-------------

I<-.J..:_ __
41(21)

40(20)

OUTPUT ~-----~_~.!.'!!!'_~-----___,~

____

TRUTH TABLE FOR CONTROL INPUTS
Control
Inputs

Division Ratio
SP.8792A SP8793A

Fig.4 Input sensitivity (SP8792/3A)

NOTE
The set-up time ts is defined as the minimum time that can elapse between a L + H transition of the control input and the next L- H clock pulse
transition to ensure that the +80(40) mode is selected.
The release time tris defined as the minimum time that can elapse between a H-L transition of the control input and the next L-H clock pulse
transition to ensure that the +81 (41) mode is selected.

16001--+-+-1--+--r--1--+-+-+-1--+-4

1~~~-+~~+-~~-~~-+~--+-~

g 1200~~-+~~+-~--f--~~-+~-+-~
i!:i

loool--+-+-1I--+-+--f--t-+-+-1--+--l

~ 8001--~~~~~~~.-t-+-+-1--+--l

~~.oo
600 ]~UARANT~.io'/j/')"
OPERATING
;!;
~DOW

/~-+--l-1--1

~o~d-~~~~~~--~~~-4--+-~
D I

!II
IN~lJf

'AIClUet 1400
.sw 1200
~

1:
600

*Tested as specified
in table of
Electrical Characteristics

400 f---'

/ •.w;...~
K/
OPERATING
/W,/OW/

'/'
/

200

100

300

INPUT FREQUENCY (MHz)

FigA Input sensitivity SPB795A

OPERATING NOTES
1. The clock input (Pin S) should be capacitively coupled to
the signal source. The input signal path is completed by
coupling a capaCitor from the internal bias decoupling, Pin 6
to ground.
2. The output stage which is normally open collector (Pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V IineviaaSk resistor buttheoutput
sink current should not exceed 2mA. If interfacing to TTL is
required then Pins 2 and 7 should be connected together to
give a fan-out = 1. This will increase supply current by
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
better than 20V/J.Js is required.

4. The mark space ratio of the output is approximately 1.2:1
at 200M Hz.
S. Input impedance is a function of frequency. See Fig.S.
6. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 1S0k
between unused input and ground. This reduces the input
sensitivity by typically SQ-100mV p-p.
7. The supply voltage regulator which allows the SP879S to
be used at supply voltages up to 9.SV is NO T available for use
in the A Grade device: the SP879SA is ONL Y available for
operation from S.2V supply, and therefore Pins 7 and 8
should always be externally connected together.

-11

Fig.5 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 2So C, frequencies in
MHz, impedances normalised to SO ohms.

178

SP8795A

VCC OF MODULUS
CONTROL DEVICE

+S.2V

OUTPUT

[H-H

L-______~

500
MONITOR

500
SIGNAL
SOURCE

Fig.6 Toggle frequency test circuit

179

SP8799
225MHz -;- 10/11 TWO MODULUS DIVIDER

The SP8799 is a low power programmable -;- 10/11
counter. It divides by 10. when the control input is in the high
state and by 11 when in the low state. An internal voltage
regulator allows operation from a wide range of supply
voltages.

'-.../

CONTROL INPUT [ 1
OUTPUT Vec2 [

SP8799

OUTPUT [ 3

Vee1

REF DECDUPLING

INPUT

P
6P
P

INTERNAL BIAS DECOUPLING

VujOV) [ 4

FEATURES

•
•
•
•

DPB. MPB

Very Low Power
Control Input and Output CMOS/TIL Compatible
AC Coupled Input
Operation up to 9.5V using Internal Regulator

Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage

6.0V Pins 7 & 8 tied
13.5V Pin 8, Pin 7 decoupled
Storage temperature range
-55°C to +125°C
Max. junction temperature
+175°C
Max. clock input voltage
2.5V p-p
Voo2
MB1W

QUICK REFERENCE DATA

•
•
•

Supply voltage: +5.2V or 6.8 to 9.5V
Power consumption: 26mW Typical
Temperature range: -40°C to +85°C

I-------~";'-....:.~,;;;: 1---1
I
I
I
I
I

I
CLOCK~n
INPUT~

16
I
I

DIVIDE BY
10/11

INTERNAL
I~r-----1.--.,.-_J
BIAS
DECOUPLING .,.In
rrln
16k
L_~

___

nfn
VEE (OV)

1_ _ _ _ _

CONTROL
INPUT

3_ _ _ _

OUTPUT

Fig.2 Functional diagram SP8799

180

7_ _ _

REF
;;;;, DECOUPLE

-.1

SP8799
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vcc 1 & 2
5.2V ± 0.25V or 6.BV to 9.5V (see Operating Note 7);
VEE
OV; Temperature Tamb
-40°C to +B5°C

Characteristic

Symbol

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)

fmin

Power supply current
Control input high voltage
Control input low voltage
Output high voltage

lEE
VINH
VINL
VOH

Output low voltage

VOL

Value
Min. Max.

Units

Notes

225

MHz

Note 4

Input

= 200-BOOmV p-p

MHz

Note 4

Input

= 40D-eOOmV p-p

mA
V
V
V

Note
Note
Note
Note

4
2
2.4
0.5

Conditions

4
4
4
4

Pins 2, 7 and Blinked
Vcc = 4.95V 10H = 100pA

Note 4

Pin 2 linked to e and 7
10L = 1.6mA

ts
14
ns
Note 3
Set up time
tr
Release time
20
ns
Note 3
tp
Clock to output propagation time
45
ns
Note 3
NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply.
2. The test configuration for dynamic testing is shown in Fig.5.
3. Guaranteed but not tested.
4. Tested only at 25°C.
CLOCK INPUT

frequency and temperature range.

LI1.ILn.1lJl.f _- _- _1l1.fUlJU1IUU' _- _- _LIUUUl.IUl..f _-_- _Ln..IlfUlIU1IU1

-j

CONTROL INPUT - ,
OUTPUT

25°C
25°C
25°C

; -

--j I-Is
~-

~ _~_-.r-- ---~

__ ___.r--s
~

TRUTH TABLE FOR CONTROL INPUTS
Control
input

Division ratio

0
1

11
10

Fig.3 Timing diagram SP8799
NOTES
The set-up time tsis defined as minimum time that can elapse between L-H transition of control input and next I:--H clock pulse transition to
ensure + 10 mode is selected.
The release time t, is defined as minimum time that can elapse between H-L transition of the control input and the next L-H clock pulse
transition to ensure the'" 11 mode is selected.

~ 1400~-+--+--4--+--4--~--~~--t--+--+--1

§.

_.
1200

vdc ~

4.95V TO 5.45V PINS 7 ANO 8 CONNECTED
TOGETHER. Tamb = -40'C 10 +85'C

w 1000

*Tested as specified
in table of
Electrical Characteristics

....

3!:

INPUT FREQUENCY (MHz)

Fig.4 Input sensitivity SP8799

181

SP8799
OPERATING NOTES
5. Input impedance is a function of frequency. See Fig.5.
6. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 150k
between unused input and ground. This reduces the input
sensitivity by typically 5Q-100mV p-p.
7. The internal regulator has its input connected to Pin 8,
while the internal reference voltage appears at Pin 7 and
should be decoupled. For use from a 5.2V supply, Pins 7 and
8 should be connected together, and 5.2V applied to these
pins. For operation from supply voltages in the range +6.8V
to +9.5V, Pins 7 and 8 should be separately decoupled, and
the supply voltage applied to Pin 8.

1. The clock input (Pin 5) should be capacitively coupled to
the signal source. The input signal path is completed by
coupling a capacitor from the internal bias decoupling, Pin 6'
to ground.
2. The output stage which is normally open collector (Pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V lineviaa5k resistorbullheoutput
sink current should not exceed 2mA. If interfacing to TTL is
required then Pins 2 and 7 should be connected together to
give a fan-out
1. This will increase supply current by
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
better than 20V lJ1s is required.
4. The mark space ratio of the output is approximately 1.2:1
at 200M Hz.

Fig.5 Typical input impedance. Test conditions: supply voltage 5.2V, ambient temperature 25°C, frequencies in
MHz, impedances normalised to 50 ohms.

VCC OF MODULUS
CONTROL DEVICE

o-----oVCC1

OUTPUT

MO~I~OR
k
son
D-t-H
1n

SIGNAL
SOURCE

' - -_ _ _...J

lOOn

Fig.6 Toggle frequency test circuit

182

SP8799A
200MHz 710/11 TWO MODULUS DIVIDER
The SP8799A is a low power programmable +10/11
counter which operates over the full Military temperature
range. It divides by 10 when the control input is in the high
state and by 11 when in the low state.

CONTROL INPUT [ 1
OUTPUT Vee [

FEATURES

'-"

VUCDV) [ 4

Very Low Power
Control Input and Output CMOS/TIL Compatible

•

AC Coupled Input

Vee'
Vee 2

SP8799A

OUTPUT [ 3

•
•

sp
7p
P
sp

INTERNAL BIAS DECOUPUNG

INPUT

DGS
Fig. 1 Pin connections - top view

QUICK REFERENCE DATA
•

Supply voltage: +5.2V

•

Power consumption: 26mW typical

•

Temperature range: -55°C to +125°C

ABSOLUTE MAXIMUM RATINGS
6.0V Pins 7 & 8 tied
-55°C to +150°C
+175°C
2.5V p-p

Supply voltage:
Storage temperature range:
Max. junction temperature:
Max. clock input voltage:

r--------~,~--.:.-,;;; T-L--,
2

CLOCK
INPUT

.r-----'

1n~ _~ISL__
o--fl-

INTERNAL

DECg~LlNG

.,.1n

DIVIDE BY
1DI11

I
L_¢ ___

nm I

VEE(~

16k

1_ _ _ _ _

CONTROL
INPUT

3_ _ _ _ _ _ _ _

--1

OUTPUT

Fig.2 Function diagram SP8799A

183

SP8799A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Supply voltage: Vee 1 & 2

= 5.2V ± 0.25V;

Characteristic

Symbol

VEE

= OV;

Temperature T.mb

= -55°C to

Value
Min. Max.

Units

Notes

200
150

MHz
MHz

Note 3

Maximum frequency
(sinewave input)

fmax

Minimum frequency
(sinewave input)

fmin

20
50

MHz
MHz

Note 3

Power supply current
Control input high voltage
Control input low voltage
Output high voltage

lEE
VINH
VINL
VOH

7
5.2
2

mA
V
V
V

Note
Note
Note
Note

Output low voltage

VOL
ts
tT
tp

Set up time
Release time
Clock to output propagation time

4
2.4

4
4
4
4

+125°C

Conditions
Input
Input
Input
Input

= 2OQ-400mV p-p
= 200-800mV p-p
= 400mV p-p
= 200mV p-p

Pins 2, 7 and 8 linked
Vee = 4.95V 10H = 100tlA

0.5

Note 4

Pin 2 linked to 8 and 7
10L = 1.6mA

ns
ns
ns

Note 3
Note 3
Note 3

25°C
25°C
25°C

14
20

NOTES
1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply. frequency and temperature range.
2. The test configuration for dynamic testing is shown in Fig.S.
3. Guaranteed but not tested.
4. Tested at 25°C only.

CLOCK INPUT

Lru1IUU1I _-_- _""U1.Il.J111I11_-_- _"U1JlJ1IlIUl.I"_-_-_"lJ1IUlII.IlI1.

-!
CONTROL INPUT - ,
OUTPUT

--j

1--1•

~-~---

~_!_~---~

__5_ _ _.....J---

TRUTH TABLE FOR CONTROL INPUTS
Control
Inpuls

Division ratio

0
1

11
10

Fig.3 Timing diagram SP8799A

NOTES
The set-up time Isis defined as minimum time that can elapse between L-H transition of control input and next L-H clock pulse transition to
ensure + 1a mode is selected.
The release time t, is defined as minimum time that can elapse between H-L transition of the control input and the next L-H clock pulse
transition to ensure the +11 mode is selected.

184

SP8799A
1800 r-"'T"'""'T-,r--"'-"'T"'""'T-r-,.....,......,.-r-,.....,..-,

'Tested as specified
in table of
Electrical Characteristics

100

200

300

INPUT FREQUENCY (MHz)

Fig.4 Input sensitivity SP8799A

OPERATING NOTES
1. The clock input (Pin 15) should be capacitively coupled to
the signal source. The input signal path is completed by
coupling a capacitor from the internal bias decoupling, Pin 6
to ground.
2. The output stage which is normally open collector (Pin 2
open circuit) can be interfaced to CMOS. The open collector
can be returned to a +10V line via a 15k resistor butthe output
sink current should not exceed 2mA. If interfacing to TTL is
required then Pins 2 and 7 should be connected together to
give a fan-out
1. This will increase supply current by
approximately 2mA.
3. The circuit will operate down to DC but a slew rate of
better than 20V/ps is required.

4. The mark space ratio of the output is approximately 1.2: 1
at 200M Hz.
S. Input impedance is a function of frequency. See Fig.S.
6. If no signal is present the device will self-oscillate. If this
is undesirable it may be prevented by connecting a 1S0k
between unused input and ground. This reduces the input
sensitivity by typically SO-100mV pop.
7. The supply voltage regulator which allows the SP8799 to
be used at supply voltages up to 9.SV is NO T available for use
in the A Grade device: the SP8799A is ONL Y available for
operation from S.2V supply, and therefore Pins 7 and 8
should always be externally connected together.

O~----~~--~~------~------~------~--~~

-11
Fig.fj Typical Input ImplJdlJncl. r!lst IJOhdltlo/,/s: &uPply valtagf1 5.2V, ambient tlmperature 25° O. frequMtJietl In
MH2:, impedanCes normalised to 50 ohms.

185

SP8799A

VCC OF MODULUS
CONTROL DEVICE

+S.2V

kMO~OR

OUTPUT
~

1"
[H-t--I

_ _ _.....

Fig.S Toggle frequency test circuit

186

SOO

SIGNAL
SOURCE

PLESSEY

Semiconductors ___________________

SP8802A
3.3GHz 7 2 FIXED MODULUS DIVIDER

The SP8802A is one of a range of very high speed low
power prescalers for professional and military applications.
The device features a complementary output stage with on
chip current sources for the emitter follower outputs.
Vee [1

'-./

INPUT [ 2

FEATURES

INPUT [ 3

•
•

Very High Speed Operation 3.3GHz
Silicon Technology for Low Phase Noise
(Typically better than -140d8c/ Hz at 10kHz

•

Specified over the Full Military Temperature Range

•

Low Power Dissipation 420mW (Typ.)

•

5V Single Supply Operation

NO [ 4

sp
P
P

SP8802

OUTPUT

GND

DG8
Fig. 1 Pin connections - top view

•

High Input Sensitivity

•

Very Wide Operating Frequency Range

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vcc
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p
-55°C to +150°C
+175°C

THERMAL CHARACTERISTICS
BJA

= 150°C/W

SUPPLY

r------------------ -------------l

I
I

VCC4-~~--~--~----~~

I
I

I
I
6

O-U-T-PU-T

+--__-+--__-'7-01 OUTPUT
INPUT ~---+-jl.....-__._-J'

INPUT03~-----~-~

L ___________

~15

I
I
I
I
I

_______________ J

GND
Fig.2 SP8802A block diagram

187

SP8802A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -55°C to +125°C. Vee = 4.75V to 5.25V (See Note)
Characteristic

Supply current

Value
Min.

Input sensitivity
0.5GHz to 2.8GHz
3.3GHz

2.3

Input impedance (series equivalent)

2.3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6.7
6.7

0.8

Units

Conditions

Typ.

Max.

100

Vee = 5V

175
400

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

1
0.35

V p-p
V p-p

Vee = 5V
Vee = 5V load as Fig.4

NOTE
Devices must be used with a suitable heatsink to maintain chip temperature below 175°e when operating at T,mb> 1aaoe.

* Tested as
specified in
Table of
Electrical
Characteristics

FREQUENCY (GHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

c1~~~T-1~
~470

13P

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

188

SP8802A

-jl

Fig.5 Typical input impedance

189

PLESSEY

Semiconductors ___________________

SP8804A
3.3GHz -;- 4 FIXED MODULUS DIVIDER

The SP8804A is one of a range of very high speed low
power prescalers for professional and military applications.
The device features a complementary output stage with on
chip current sources for the emitter follower outputs.
Vee [ 1
INPUT [ 2

FEATURES
•

'-'

SP8804
INPUT [ 3

Very High Speed Operation 3.3GHz

NC [ 4

•

Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Specified over the Full Military Temperature Range

•

Low Power Dissipation 370mW (Typ.)

•

5V Single Supply Operation

•
•

High Input Sensitivity
Very Wide Operating Frequency Range

P
P
P
5P

OUTPUT

OUTPUT
GNO

DGB
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------ -------------l
1

I
I

VREF (2V)

400

I
I

400

aOUTPUT
I--

t-_-t-_~7-o1 OUTPUT
I
I
I

~~T
INPUT

L ___________

~15

_______________ J

GND
Fig.2 SP8804A block diagram

190

SP8804A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -55°C to +125°C, Vcc = 4.75V to 5.25V (See Note)

Characteristic

Supply current

Value
Min.

Input sensitivity
0.5GHz to 2.8GHz
3.3GHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6,7
6,7

0.8

Units

Conditions

Typ.

Max.

Vcc = 5V

175
400

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

0
pF

1
0.25

V p-p
V p-p

Vcc = 5V
Vcc = 5V load as Fig.4

NOTE
Devices must be used with a suitable heatsink to maintain chip temperature below 175°C when operating atTamb >1 05°C.

THERMAL CHARACTERISTICS
8JA

= 150°C/W

i
eilE

500

* Tested as

specified in
Table of
Electrical
Characteristics

S.
z

>
4

2
FREQUENCY (GHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

riU~~~T~~

Ji47°13P

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

191

SP8804A

-11

Fig.5 Typical input impedance

192

PLESSEY _____________________________________
Semiconduclors
SP8808A
3.3GHz -;- 8 FIXED MODULUS DIVIDER

The SP8808A is one of a range of very high speed low
power prescalers for professional and military applications.
The device features a complementary output stage with on
chip current sources for the emitter follower outputs.
Vee [ 1

INPUT [ 2

FEATURES

•
•
•
•
•
•
•

.......,

INPuf[ 3

Very High Speed Operation 3.3GHz
Silicon Technology for Low Phase Noise
(Typically better than -140d8c/ Hz at 10kHz
Specified over the Full Military Temperature Range
Low Power Dissipation 345mW (Typ.)
5V Single Supply Operation
High Input Sensitivity
Very Wide Operating Frequency Range

NC [ 4

SPBBDB

P
P
P
sp

OUTPUT

OUTPUT
GNO

DGB
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------l-------------l
I
I

VCC

I
I

I
I
I
I

&I-OU-T-PU-T

7 1 OUTPUT

INPUT 2=--_-+;:"-----,..----'

INPUT~3----------+_--~
I

I
I

!L ____________
I ~5---- ____________ Jl
GND
Fig.2 SPBBOBA block diagram

193

SP880SA
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -SsoC to +12SoC, Vee = 4.7SV to S.2SV (See Note)

Characteristic

Supply current

Value
Min.

I nput sensitivity
O.SGHz to 2.8GHz
3.3GHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6,7
6,7

Typ.

Max.

8S
17S
400

0.8

Conditions

Units
mA

Vee = SV

mV
mV

RMS sinewave
Measured in son
system. See Figs. 3 & 4

SO
2

n
pF

1
0.4

V p-p
V p-p

Vee = SV
Vcc = SV load as Fig.4

NOTE
Devices must be used with a suitable heat sink to maintain chip temperature below 175°C when operating at Tamb >11 DOC.

THERMAL CHARACTERISTICS
(JJA

= 1SD °C/W

* Tested as
specified in
Table of
Electrical
Characteristics

FREQUENCY (GHz)

Fig.3 Typical input sensitivity

COAXIAL
SWITCH

POWER
METER

O.I

ciuR,.~~T ----I

470

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

0.1/1

Fig.4 Test circuit

194

SP8808A

-jl

Fig.5 Typical input impedance

195

PLESSEY

Semiconductors __________________

SP8812A & B
2.4GHz -;- 2 FIXED MODULUS DIVIDER

The SP8812 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

Vee [1

'-./

INPUT [ 2

INPuf[

FEATURES

•
•

High Speed Operation 2.4GHz
Silicon Technology for Low Phase Noise
(Typically better than -140d8c/ Hz at 10kHz
Very Low Power Dissipation 250mW (Typ.)
5V Single Supply Operation
High Input Sensitivity
Very Wide Operating Frequency Range
Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (8 Grade)

•
•
•
•
•

3 SP8812

NC [ 4

P
P
sp

OUTPUT

OUTPUT
GND

DG8 (SP8812A)
DP8 (SP8812B)
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------ 1-------------l
I
I
I
I

Vee

1--

OUTPUT

t-_+-_--'7-o1
INPUT

~--+;l,.....

I
I
I

___..l

INPUT~3-----+----J

L ___________

~I5
GND

_______________

Fig.2 SP8812 block diagram

196

I
I

OUTPUT

SP8812A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = A Grade -SsoC to +12SoC, B Grade -40°C to +8SoC, Vee = +4.7SV to +S.2SV
Characteristic

Value

Supply current

Min.

Max.

Vec = SV

100
12S

mV
mV

RMS sinewave
Measured in SOO
system. See Figs. 3 & 4

I nput sensitivity
SOOMHz to 2200MHz
2400MHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with f;n =SOOMHz
Output voltage with f;n = 2400MHz

6,7
6,7

4001

0.8

SO
2

0
pF

1
0.13

V p-p
V p-p

II:

* Tested as

150

specified in
Table of
Electrical
Characteristics

100

.E.
!:
>

Vee = SV
Vec = SV load as Fig.4

III

::;

See Fig.S

01)

...0
!:

Conditions

Units

Typ.

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

c!u~~~T~~

~470

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

197

SP8812A & B

-)1

Fig.S Typical input impedance

198

PLESSEY

Selniconductors _____________________________________

SP8814A & B
2.4GHz -;- 4 FIXED MODULUS DIVIDER

The SP8814 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

Vee [ 1

'-.../

INPUT [ 2

8
7

SP8814
INPUt [ 3

FEATURES
•
•

High Speed Operation 2.4GHz
Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Very Low Power Dissipation 220mW (Typ.)

•

5V Single Supply Operation

•
•

High Input Sensitivity
Very Wide Operating Frequency Range

•

Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (B Grade)

Ne [ 4

P
b
P

Ne
OUTPUT

OUTPUT

GNU

DG8 (SP8814A
DP8 (SP8814B)
Fig.l Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V pop

-55°C to +150°C
+175°C

SUPPLY

r------------------ - ----------

--l

1
VCC4-~~--~--~----~--_.

VREF (2V)

~--+---~ OUTPUT
INPUT

7 --+-{_---.>--_
2

INPUT~3----------+_--~

L ___________

~15

_______________

GND
Fig.2 SPBB14 block diagram

199

SP8814A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = A Grade -SsoC to +12SoC, B Grade -40°C to +85°C, Vee = +4.7SV to +S.2SV

Characteristic

Value

Supply current

Min.

Input sensitivity
SOOMHz to 2200MHz
2400MHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin =SOOMHz
Output voltage with fin ==2400MHz

6,7
6,7

4OO!

~
~
!

~
II:

I'
I

0.8

Conditions

Units

Typ.

Max.

Vee = SV

100
12S

mV
mV

RMS sinewave
Measured in son
system. See Figs. 3 & 4

so
2

1
0.13

V pop
V pop

Vee = SV
Vee == SV load as FigA

, ,I

* Tested as

150

specified in
Table of
Electrical
Characteristics

100

:; so

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

0"Q:f
l

o"U\~~T --I

470

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

200

SP8814A & B

Fig.S Typical input impedance

201

PLESSEY'_____________________________________
Semiconductors
SP8818A & B
2.4GHz

+- 8 FIXED MODULUS DIVIDER

The SP8818 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

Vee [ 1

'-"

INPUT [ 2

FEATURES

INPuf[ 3

•

High Speed Operation 2.4GHz

•

Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Very Low Power Dissipation 200mW (Typ)

•

5V Single Supply Operation

•

High Input Sensitivity

•

Very Wide Operating Frequency Range

•

Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (B Grade)

NC [ 4

SP8818

P
b

OUTPUT
DUTPUT
GND

OG8 (SP8818A)
OP8 (SP8818B)
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------ ----------- --l

I
I
I
I

INPUT

vee 4---+-_-.......-_---..-~

VREF (2V)

400

I
I

OUTPUT

I
I

OUTPUT

~1~2--..+-j~-_-;t
I

INPUT~3-----+_-~

L___________ ~15

_______________

GND

Fig.2 SP8818 block diagram

202

SP8818A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = A Grade -55°C to +125°C, B Grade -40°C to +85°C, Vcc = +4.75V to +5.25V
Characteristic

Value

Supply current

Min.

Max.

Vce = 5V

100
125

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

Input sensitivity
500MHz to 2200MHz
2400MHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin =500MHz
Output voltage with fon = 2400MHz

6,7
6,7

4001

0.8

I
)

;

Conditions

Units

Typ.

50
2

0
pF

1
0.13

V p-p
V p-p

;

Vce = 5V
Vce = 5V load as Fig.4

g
on

*Tested as

150

ir:

'":0

specified in
Table of
Electrical
Characteristics

100

II:

Sir:

1000

2000

FREQUENCY (MHz)

FigA Test circuit

rs
Tt
COAXIAL

0.1/1

POWER
METER

tu~~~T~~
,!t470 l3P
OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.3 Typical input sensitivity

203

SP8818A & B

Fig.S Typical input impedance

204

PLESSEY

Semiconductors ___________________

SP8822A & B
1.8GHz -;- 2 FIXED MODULUS DIVIDER

The SP8822 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.
Vee [ 1

FEATURES

SP8822 •

NC [ 4

High Speed Operation 1.8GHz

•

Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Very Low Power Dissipation 215mW (Typ.)

8 ] Ne

INPuT [

•

'-"

INPUT [ 2

J OUTPUT

OUTPUT
GND

DG8 (SP8822A)
DP8 (SP8822B)
Fig.1 Pin connections - top view

•

5V Single Supply Operation

•
•

High Input Sensitivity
Very Wide Operating Frequency Range

•

Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (B Grade)

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------ -------------l

1
1

I
I

INPUT

vcc __~~--~--~--~---,

I
1

6 1 OUTPUT

7 1 OUTPUT

iNPUT 13

L___________ ~l~ _______________ J
GND

Fig.2 SP8822 block diagram

205

SP8822A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb
A Grade -55°C to +125°C, B Grade -40°C to +85°C, Vee

Characteristic

Min.

I nput sensitivity
200MHz to 1500MHz
1800MHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin
Output voltage with fin

Value

Supply current

= +4.75V to

Typ.

Max,

6,7
6,7

4001

0.8

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

1
0.13

V p-p
V p-p

See Fig.5
Vee
Vee

= 5V
= 5V load as Fig.4

I
I

* Tested as

150

specified in
Table of
Electrical
Characteristics

III

:I 100

'"
g
~

Vee

= 5V

50
2

Conditions

Units

50
100

= 250MHz
= 1800MHz

+5.25V

500

1000

1500

2000

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR

0.1

d'U"~~T-I

470

311

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

206

SP8822A & B

-11

Fig.5 Typical input impedance

207

PLESSEY _____________________________________
Selniconductors
SP8824A & B
1.8GHz -;- 4 FIXED MODULUS DIVIDER

The SP8824 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

.co [ 1 -=
IMPUT[ 2

1fjPiif[ 3

FEATURES

NC[ 4

•
•

High Speed Operation 1 .8GHz
Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Very Low Power Dissipation 190mW (Typ.)

•

5V Single Supply Operation

•
•

High Input Sensitivity
Very Wide Operating Frequency Range

•

Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (B Grade)

SP8824

PIC

7 pOUll'UT
•

OUll'UT

GND

DG8 (SP8824A)
DP8 (SP8824B)
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------,-------------l
I

VCC

VREF(2V)
400

400

INPUT cr---O-~

~_1--_7!.Q1 OUTPUT
1
1
1

~~3~_ _ _ _~_~

I
1

,mA

L ___________

~I~---------------J
GND

Fig.2 SP8824 block diagram

208

1 OUTPUT

SP8824A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tomb = A Grade -55°C to +125°C, B Grade -40°C to +85°C, Vee = +4.75V to +5.25V
Characteristic
Supply current

Min.

I nput sensitivity
200MHz to 1500MHz
1800MHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin
Output voltage with fin

Value

Typ.

Max.

Units

50
100

= 250M Hz
= 1800MHz

4001

6,7
6,7

0.8

= 5V

Vee

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

1
0.15

V p-p
V p-p

Conditions

Vce
Vee

= 5V
= 5V load as Fig.4

/1
I

*Tested as

150

1/1

specified in
Table of
Electrical
Characteristics

lOll

~ so

500

1000

1500

2000

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR

POWER
METER

JI~~~T----11~

n~C 1

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

209

SP8824A & B

-j1

Fig.5 Typical input impedance

210

PLESSEY

Semiconductors __________________

SP8828A & B
1.8GHz -7- 8 FIXED MODULUS DIVIDER

The SP8828 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

Vee [ 1

'-./

INPUT [ 2

FEATURES

INPut [ 3

SP8828

Nee 4

•

High Speed Operation 1.8GHz

•

Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Very Low Power Dissipation 175mW (Typ.)

•

5V Single Supply Operation

•

High Input Sensitivity

•

Very Wide Operating Frequency Range

•

Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (B Grade)

P
P
P

OU1?UT

OUTPUT

GNO

DG8 (SP8828A)
DP8 (SP8828B)
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vcc
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r-----------------I

-------------l

vcc __~,_--~--~--~--_,

VREF (2V)
1k

I
I

400

INPUT

e l ffirrPlrr

I
I

I
I
7~

I
I

I
I
I

~13
I

L___________ ~l~-- _____________ J
GND

Fig.2 SP8828 block diagram

211

SP8828A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = A Grade -55°C to +125°C, B Grade -40°C to +85°C, Vee = +4.75V to +5.25V
Characteristic

Value

Supply current

Min.

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin = 250M Hz
Output voltage with fin = 1800MHz

6,7
6,7

ei!:

4001
I
I

0.8

Vee = 5V

50
100

mV
mV

RMS sinewave
Measured in 50n
system. See Figs. 3 & 4

50
2

n
pF

1
0.15

V p-p
V p-p

150

*Tested as
specified in
Table of
Electrical
Characteristics

:Ii 100
0:

g
z

Vee = 5V
Vee = 5V load as Fig.4

II)

Conditions

Max.

Input sensitivity
200M Hz to 1500MHz
1800MHz

Units

Typ.

SOD

1000

1SOD

200D

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR

o='~f~'_r:

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

212

SP8828A & B

"11

Fig.5 Typical input impedance

213

PLESSEY

Semiconductors ___________________

SP8830A & B
1.5GHz

+- 10 FIXED MODULUS DIVIDER

The SP8830 is one of a range of very high speed low power
prescalers for professional and military applications. The
device features a complementary output stage with on chip
current sources for the emitter follower outputs.

Vee [ 1

'-'

INPUT [ 2

INPut [ 3

FEATURES

•
•
•
•
•
•
•

SP8830

NC[ 4

High Speed Operation 1.5GHz
Silicon Technology for Low Phase Noise
(Typically better than -140d8c/Hz at 10kHz
Very Low Power Dissipation 200mW (Typ.)
5V Single Supply Operation
High Input Sensitivity
Very Wide Operating Frequency Range
Temperature Range:
-55°C to +125°C (A Grade)
-40°C to +85°C (8 Grade)

8] NC

J OUTPUT

POUTPUT

GID

DG8 (SP883DA)
DP8 (SP883DB)
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r---------------------------------,I
1
1
1
I

Vee
1k

I
I

1
1

1OUTPUT

IMM
1

-13
INPUT

INPUT

L--------___ ~1 _______________ J
GND

Fig.2 SPBBSO block diagram

214

SP8830A & B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = A Grade -55°C to +125°C, B Grade -40°C to +85°C, Vee = +4.75V to +5.25V

Characteristic

Pin
1

Supply current
Input sensitivity
100MHz to 1200MHz
1.5GHz

2,3

Input impedance (series equivalent)

2,3

= 100MHz
= 1500MHz

6,7
6,7

Output voltage with fin
Output voltage with fin

Value
Min.

Typ.

Max.

50
15
25

0.8

Conditions

Units

Vee

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

0
pF

1
0.4

V p-p
V p-p

Vee
Vee

ll:

tJ)

::;;

a; 15

>
.§.
Z

;;;

= 5V
= 5V load as Fig.4

*Tested as
specified in
table of
Electrical
Characteristics

= 5V

500

1000

1500

2000

FREQUENCY (MHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR

POWER
METER

COAXIAL
SWITCH

c!u~~~T~'Tr
~1k

I3P

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

215

SP8830A & B

o~----~----~=r------1-------~----~r---~~

-jl

Fig.S Typical input impeqance

216

PLESSEY _____________________________________
Semiconductors
SP8832B
3.5GHz

+- 2 FIXED MODULUS DIVIDER

The SP8832B is one of a range of very high speed low
power prescalers for professional applications. The device
features a complementary output stage with on chip current
sources for the emitter follower outputs.
Vee [1

FEATURES

•
•
•
•
•
•

'--'

INPUT [ 2

Very High Speed Operation 3.5GHz
Silicon Technology for Low Phase Noise
(Typically better than -140d8c/Hz at 10kHz
Low Power Dissipation 420mW (Typ.)
5V Single Supply Operation
High Input Sensitivity
Very Wide Operating Frequency Range

INPUt [ 3

NC [ 4

8
7

SP8832
6

OUTPUT

OUTPUT
GND

DGB
DPB
Fig.l Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vcc
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------,-------------l
I
I
I
I

vee
VREF (2V)

400

61OUTPUT
+--_+-_....:7-0' OUTPUT

I
I
I

INPUT ~--+-f._ _.,.--~""

iN'PDT o-3"---_ _ _ _-+__......J

L ___________

~I~--

_____________

I
I

GND
Fig.2 SP8832B block diagram

217

SP8832B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -40°C to +85°C, Vee
+4.75V to +5.25V

Characteristic

Supply current

Value
Min.

Input sensitivity
0.5GHz to 2.8GHz
3.5GHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6,7
6,7

0.8

Units

Conditions

Typ.

Max.

100

Vee = 5V

175
500

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

0
pF

1
0.35

V p-p
V p-p

Vee = 5V
Vee = 5V load as Fig.4

* Tested as
specified in
Table of
Electrical
Characteristics

FREQUENCY (GHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR

POWER
METER

COAXIAL
SWITCH

cruRT~~T~1~
~470

r3P

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

Fig.4 Test circuit

218

SP8832B

-11

Fig.S Typical input impedance

219

PLESSEY

Semiconductors __________________

SP8835B
3.5GHz -;- 4 FIXED MODULUS DIVIDER

The SP8835B is one of a range of very high speed low
power prescalers for professional applications. The device
features a complementary output stage with on chip current
sources for the emitter follower outputs.
Vee [ 1

FEATURES

INPUT [ 2

•
•

INPuT (

SP8835

Very High Speed Operation 3.5GHz
Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz
Low Power Dissipation 370mW (Typ.)
5V Single Supply Operation
High Input Sensitivity
Very Wide Operating Frequency Range

•
•
•
•

\.J
7

NC ( 4

P
P
P
P

OUTPUT
OUTPUT

GND

DG8
DPB
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p
-55°C to +150°C
+175°C

SUPPLY

r------------------ -------------l
I
1

VCC4-~~--~--~----~--.

I
I
I

INPUT

I
I

I
I
61~

7 1 OUTPUT

12
I

:
I
I

iNPliT 13

!L ____________I

5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J

GND
Fig.2 SP8834B block diagram

220

1
I

SP8835B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb = -40°C to +85°C, Vee = +4,75V to +5,25V
Characteristic

Supply current

Value
Min.

Input sensitivity
0,5GHz to 2,8GHz
3,5GHz

2,3

I nput impedance (series equivalent)

2,3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6,7
6,7

0,8

Units

Conditions

Typ.

Max.

Vee = 5V

175
500

mV
mV

RMS sinewave
Measured in 500
system, See Figs, 3 & 4

50
2

0
pF

1
0,25

V p-p
V p-p

Vee = 5V
Vee = 5V load as FigA

* Tested as
specified in
Table of
Electrical
Characteristics

FREQUENCY (GHz)

Fig,3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

O,l

ciu~~~T--I

470

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

FigA Test circuit

221

SP8835B

-jl

Fig.S Typical input impedance

222

PLESSEY

Semiconductors ___________________

SP8838B
3.5GHz

+- 8 FIXED MODULUS DIVIDER

The SP8838B is one of a range of very high speed low
power prescalers for professional applications. The device
features a complementary output stage with on chip current
sources for the emitter follower outputs.
Vee [1

FEATURES

INPUT [ 2

•

INPut [ 3

•

'--'

SP8838

Very High Speed Operation 3.5GHz

NC [ 4

Silicon Technology for Low Phase Noise
(Typically better than -140dBc/Hz at 10kHz

•

Low Power Dissipation 345mW (Typ.)

•

5V Single Supply Operation

•

High Input Sensitivity

•

Very Wide Operating Frequency Range

8
7

J Nt
J OUTPUT

6] iffiffiif
5] GND

DGB
DPB
Fig.1 Pin connections - top view

ABSOLUTE MAXIMUM RATINGS
Supply voltage Vee
Clock input voltage
Storage temperature range
Junction temperature

6.5V
2.5V p-p

-55°C to +150°C
+175°C

SUPPLY

r------------------ -------------l

I
I

VCC4--+~--~--~----~--_.

I
I

a 1 0uTPUT

1
I
I
INPUT

I OUTPUT

INPUT ,3

6.7SmA

L___________ ~ls

_______________

GND
Fig.2 SP88388 block diagram

223

SP8838B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb
-40°C to +85°C, Vee
+4.75V to +5.25V

Characteristic

Supply current

Value
Min.

Input sensitivity
0.5GHz to 2.8GHz
3.5GHz

2,3

Input impedance (series equivalent)

2,3

Output voltage with fin = 1000MHz
Output voltage with fin =3GHz

6,7
6,7

0.8

Units

Conditions

Typ.

Max.

Vee = 5V

175
500

mV
mV

RMS sinewave
Measured in 500
system. See Figs. 3 & 4

50
2

1
0.4

V p-p
V p-p

Vee = 5V
Vee = 5V load as Fig.4

* Tested as
specified in
Table of
Electrical
Characteristics

FREQUENCY (GHz)

Fig.3 Typical input sensitivity

SIGNAL
GENERATOR
COAXIAL
SWITCH

POWER
METER

ciu~~~T~~

Jt47°13P

OUTPUT LOAD FOR
AMPLITUDE MEASUREMENTS

0.1/1

FigA Test circuit

224

SP8838B

-j1

Fig.5 Typical input impedance

225

226

Technical
Data
2. Frequency
synthesisers

227

228

PLESSEY

Semiconductors __________________

NJ8820, NJ8820B
FREQUENCY SYNTHESISER (PROM INTERFACE)
The NJ8820/NJ8820B is a synthesiser circuit fabricated on
the Plessey 5-micron CMOS process and is capable of
achieving high sideband attenuation and low noise
performance. The circuit contains a reference oscillator, 11bit programmable reference divider, digital and sample-andhold phase comparators, 10-bit programmable 'M' counter,
7-bit programmable 'A' counter and the necessary control
and latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words read from an
external memory with the necessary timing signals
generated internally.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8820 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of -30°C to +70°C. The NJ8820B is available only in
Ceramic DIL package with operating temperature range of
-40°C to +85°C.

PDA[

'-.../

20~CH
19 ~RB

PDB [ 2
LD [ 3

~ MC

FIN [ 4

~ DS2

V_s [ 5 NJ882016 PDS1
VDD [ 6 NJ8820B15

OSC IN

PDSD

14 bPE

DSC DUT [ 8

13 JME

DO[ 9

12 JDJ

DI[ 10

11 J D2

OP20, MP20 (NJ8820)
OG20 (NJ8820B)

FEATURES

Flg.l Pm connections

•
•
•

Low Power Consumption
Direct Interface to ROM or PROM
High Performance Sample and Hold Phase Detector

•

>lOMHz Input Frequency

I
I

PDA

I
I

OSC OUT 0--------'

Do~I--------~4--+_+--r---------_,
DATAjD11
INPUT D2o-------r~r-~-~-r_---_,

D301------t-~-~~-~--,
I

PDB

I
I

t;:;--b
'1- I
OV

I
I

LOCK DETECT
(LD)

I
I
I
I

I
I

L-l-t-- _~O:'R~O:
Vss

II MODULUS
CONTROL

____________

J O~~~~T

VDD

Fig.2 Block diagram

229

NJ8820/NJ8820B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
VOD-VSS 5V ± 0.5V, Temperature range NJ8820: -30·C to +70·C, NJ8820B: -40·C to +85·C

DC Characteristics at Voo = 5V
Characteristics

Min.

Supply current

Value
Typ.

Max.

3.5
0.7

OUTPUT LEVELS
ME output
Low level
Open drain pull-up voltage
OS OUTPUTS
High level
Low level

4.6

MODULUS CONTROL OUT
High level
Low level

4.6

LOCK DETECT OUT
Low level
Open drain pull-up voltage
PDa Output
High level
Low level
3-state leakage
INPUT LEVELS
Data Inputs
High level
Low level

Units

COnditions

5.5
1.5

mA
mA

FOSC, FIN = 10MHZ} 0 to 5V
FOSC FIN = 1.0MHz square
,
wave

0.4
8

V
V

Islnk 4mA

0.4

V
V

IsourcolmA
I sink 2mA

0.4

V
V

lsource lmA
Isink 1mA

0.4
8

V
V

I sink 4mA

0.4
±0.1

V
V
pA

0.7S

V
V

4.6

4.25

Program Enable Input (PE)
Trigger level

Vbl..
±l00mV

I source SmA
I sink SmA

TTL compatible
See note 1
Vbl.. = self bias point of
PE (nominally Vo0/2)

AC Characteristics
Characteristics

Min.

FIN/OSC inputs

200

Max. operating freq. OSC/FIN inputs

10.6

Propagation delay, clock to modulus control

Value
Typ.

Max.

Units

Conditions

mVRMS 10MHz AC coupled sinewave
MHz
ns

Note 2

Program enable pulse length, tw

Pulse to Vss or Voo

Data set-up time, tSI

Data hold time, tHI

Digital phase detector propagation delay
Gain programming resistor, RB

Voo = SV, Input squarewave
VOD-VSS Note S

ns
500

See Fig.7
Note 3

Hold capacitor, CH

Output resistance PDA

Digital phase detector gain
Power supply rise time

1
100

VlRad

10 %to 90%. Note 4

NOTES
1. Data inputs have internal 'pull-up' resistors to enable them to be driven from TIL outputs. 2. All counters have outputs directly synchronous
with their respective clock rising edges. 3. Fin~e output resistance of internal voltage follower and 'on' resistance of sample switch driving this pin
will add a finite time-constant to the loop. A 1nF hold capacitor will give a maximum time-constant of 5 microseconds. 4. To ensure correct
operation of power-on programming. 5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.

230

NJ8820/NJ8820B
PIN DESIGNATION
Pin No.

Name

Description

POA

Analog output from the sample and hold phase comparator for use as a 'fine'
error signal. Output at (VorrVss)/2 when in lock. Voltage increases as FV phase
lead increases and decreases as FR phase lead increases. Output is linear over
only a narrow phase window determined by gain programmed by RB.

POB

Three-state output from the phase/frequency detector for use as a 'coarse' error
signal.
FV> FR or FV leading: positive pulses
FV < FR or FR leading: negative pulses
FV = FR and phase error within POA window: high impedance

An open drain lock detect output at low level when phaseerrorwithin POAwindow
(in lock).
High impedance at all other times.

FIN

The input to the main counters normally driven from a prescaler which may be AC
coupled or when a full logic swing is available may be DC coupled.

Vss

Negative supply (normally ground)

VOO

Positive supply

7,8

OSC.IN/
OSC.OUT

These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required
between each end of the crystal and ground to provide the necessary additional
phase shift. An external crystal-generated reference signal may alternatively be
applied to OSC.IN. This may be a low-level Signal AC coupled into OSC.IN or if a
full logic swing is available it may be DC coupled. The program range of the
reference counter is 6-4094 in steps of 2, with the division ratio being twice the
programmed number.

9,10,11,12

00-03

Information on these inputs is transferred to the internal latches during the appropriate data read time slot. 03 MSB, DO LSB.

An open-drain output for use in controlling the power supply to an external ROM
or PROM. This output is low during the data read period and high impedance at
other times.

A positive or negative pulse or edge AC coupled into this pin initiates the singleshot data read procedure. Grounding this pin repeats the data read procedure in a
cycl ic manner.

15,16,17

OSO-OS2

Internally generated three-state data select outputs which may be used to address
external memory.

Signal for controlling an external dual-modulus prescaler. The modulus control
level will be low at the beginning of a count cycle and will remain low until the 'A'
counter completes its cycle. The modulus control then goes high and remains
high until the 'M' counter completes its cycle at which point both counters are
reset. This gives a total division ratio of M.N +A where Nand N +1 represent the
dual modulus prescale values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including -:-128/129.
The program range of the 'M' counter is 3-1023 and for correct program
operation M "?A. Where every possible channel is required, the
Iminimum division ratio should be N2-N.

An external sample and hold phase comparator gain programming resistor should
be connected between this pin and Vss.

An external hold capacitor should be connected between this pin and Vss.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (VOD- Vss)
-0.5V to 7V
Input voltage
Open drain O/Ps (pins 3 and 13)
7V
All other pins
Vss -0.3V to VDD +0.3V
Storage temperature
-65°C to +150°C
(OG package, NJ8820B)
Storage temperature
-55°C to +125°C
(OP and MP packages, NJ8820)

231

NJ8820/NJ8820B
2.0

J 1 1.

J-=

VDD =5V
= LOW FREQUENCY
OV TO 5V SQUAREWAVE

I-- I_fiN

i'-.

1.5

!zOJ

ffi
a:
a:

a:
a:

:::I 1.0
U

~ 3

...:::I

'" """
~

..........

lMH;-'"

::;...

III

:::I
U 4

III

~ 10MHz

r"-- "-'-..

0.5

0.2

0.4

INPUT FREQUENCY (MHz)

r---.....

0.6
0.8 1.0
1.2
INPUT LEVEL (V rms)

1.4

1.6

Fig.4 Typical supply current versus input level, Osc In

Fig.3 Typical supply current versus input frequency

PROGRAMMING
Program information can be obtained from an external

ROM or PROM under control of the NJ8820/NJ8820B.
Twenty-eight data bits are required per channel arranged as
eight 4-bit words leaving four redundant bits, two of which
are available on the data bus driving the data-transfer time
slot and may be used for external control purposes. A
suitable PROM may be the 748287 giving up to 32 channel
capability as shown in Fig.5. Note that the choice of PNP
transistor and supply bypass capacitor on the ROM should
be such that the ROM will power up in time: for example, at
10MHz oscillator frequency, the ROM must be powered up in
less than 2511S.
Reading of this data is normally done in a single shot mode
with the data read cycle started by either a positive or
negative pulse on the program enable pin. The data read
cycle is generated from a program clock at 1/64th of the
reference oscillator frequency. A memory enable signal is
supplied to allow power-down of the memory when not in
use. Data select outputs remain in a high-impedance state
when the program cycle is completed to allow the address
bus to be used for other functions if desired. The data map,
data read cycle and timing diagram appears as Figs. 6 to 8.
Data is latched internally during the shaded portions of the

program cycle and all data is transferred to the counters and
latched during the data transfer time slot.
Alternatively, the PE pin may be grounded causing the
data read cycle to repeat in a cyclic manner to allow
continuous up-dating of the program information. In this
mode external memory will be enabled continuously, (ME
low) and the data read cycle will repeat every sixteen cycles
of the internal program clock, i.e. every 1024/fosc seconds.
This programming method is not recommended because the
higher power consumption and the possibilities of noise
injection into the loop from the digital data lines.
Power-on programming On power-up the data read cycle
is automatically initiated making it unnecessary to provide a
PE pulse on power-up. The circuit detects the power supply
rising above a threshold point, (nominally 1.5V) and after an
internally generated delay to allow the supply to rise fully the
circuit is programmed in the normal way. This delay is
generated by counting reference oscillator pulses and is
therefore dependent on the crystal used. The delay consists
of 53248 reference oscillator cycles giving a delay of about
5ms at 10MHz.
To ensure correct operation of this function the power
supply rise time should be less than 5ms, (at 10MHz) rising
smoothly through the threshold point.

+5V
A4-A7
(CHANNEL SWITCH)
1.5k

22t-

C2B

.JL

C2A

22p

tI=-+hH-.-..---.j'-

L.J

Cl ;;'C2A +C2B + ...
L . . . . . - - -_ _ _--....!D:!,;1'r110
"1..-_ _--1

Fig.5 Programming via PROM

232

NJ8820/NJ8820B

WORD

DS2

DSl

DSO

1
2
3
4
5
6
7
8

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

M1
M5
M9
A3
R3
R7
-

MO
M4
M8
A2
A6
R2
R6
R10

M3
M7
A1
A5
R1
R5
R9

M2
M6
AO
A4

RO
R4
R8

Fig.6 Data map

DATA
TRANSFER
ON -VE
CYCLE OF
PROGRAM
CLOCK

DSO----~---------------

051-----+----------------

DS2 ----~---------------

4 PROGRAM CLOCK
CYCLES FROM SETTLING

WORD WORD

WORD

WORD WORD WORD

DATA
TRANSFER

Fig.7 Data selection
PE

---~-------

~L ___ J~_

DSO - - - - - - - - - - - - - -

---'X'-________

______

tw
(PE INTERNAL)

00-03

(DATAINTERNAL
MODE)

Fig.8 Timing diagram

233

NJ8820/NJ8820B
PHASE COMPARATORS
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error signal to enable
fast switching between channels. This output is active until
the phase error is within the sample and hold phase detector
window, when its output becomes high impedance. Phaselock is indicated at this point with a low level on LD. The
sample and hold phase detector provides a 'fine' error signal
to give further phase adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
signal, PDA. When in phase lock this output would typically
be at (VDrrVss)/2 and any offset from this would be
proportional to phase error. The relationship between this
offset voltage and the phase error is the phase-comparator
gain which is programmable with an external resistor, RB. An
internal 50pF capacitor is used in the sample and hold
comparator.

This gain is typically:
GAIN = 10 [VDrrVs9-0.7-S9(RB-'h )]
2 x Tr 50x10- 12 x RBxFR
The value of RB should be chosen to give the required gain at
the reference frequency used. Fig.9 for example shows that
to achieve a gain of 3S0V per radian at 10kHz requires
approximately 39kO. A second external component is
required; this is a hold capacitor of non-critical value which
might typically be 470pF, a smaller value being sufficient if
the sideband performance required is not high. Fig.9 shows
the gain normalised to a 1Hz comparison frequency; to
obtain the value for any other frequency, divide the value of
gain frequency product by the desired frequency.
The output from these phase detectors should be
combined and filtered to generate a single control voltage to
drive the VCO as in Fig.S.

1M~--~---r--~----~--~---r----~~

RB
10k~--4----t---1~~+---4----+----~~

'FA

5kHz
10kHz

400

25kHz

200

I
I
I

t
800
400
160

I 1200 I 1600 I
I 600 I 800 I
I 240 I 320 I

GAIN

x FR PRODUCT

Fig.9 RB versus gain and reference frequency

CRYSTAL OSCILLATOR

APPLICATION EXAMPLE

When using the internal oscillator, the stability may be
enhanced at high frequencies by the use of an external
resistor between Pin S and the other components. A value of
150-2700 is advised.

An application example for a synthesiser for operation up
to 520MHz is given in Fig.10. This gives up to 32 channels
with a maximum supply current of 17mA, (typically 12mA) at
520MHz excluding the VCO. With careful construction the
circuit is capable of providing sideband attenuation in excess
of 90dB with lock-times of only a few milliseconds for a 1MHz
frequency step.

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of VDD, as otherwise 'latch up'
may occur.

234

NJ8820/NJ8820B

+5.2V

TO VCO

---......,CCI-+-<:S

;;r;,In

47k (520VlRAOIAN)
kHz COMPARISON
FREQUENCY

r++--fI

11~~======jt==~~=:==============~~==::::~~J

10
9

02
03

ME
OSO
1
OS2

Fig. 10 Application example

235

PLESSEY

Semiconductors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

NJ8821, NJ8821 B
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
The NJ8821/NJ8821 B is a synthesiser circuit fabricated on
the Plessey 5-micron CMOS process and is capable of
achieving high sideband attenuation and low noise
performance. The circuit contains a reference oscillator, 11bit programmable reference divider, digital and sample-andhold phase comparators, 10-bit programmable 'M' counter,
7-bit programmable 'A' counter and the necessary control
and latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external
control from a suitable microprocessor.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8821 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of -30°C to + 70°C. The NJ8821 B is available only in
Ceramic DIL package with operating temperature range of
-40°C to +85°C.

PDA

•1

PDS

FIN [4

DS2

NJBB21 16

OSI

V•• [

'-"

20 PCH
19 pRB

voo [ 6 NJBB21B 15 DSO
DSC IN[ 7

14 J PE

DSC OUT [ 8

DO [ 9

12PD3

Dl [ 10

11 P D2

DP20. MP20 (NJ8821)
DG20 (NJ8821B)

FEATURES
Fig.1 Pin connections

•
•
•
•

Low Power Consumption
High Performance Sample and Hold Phase Detector
Microprocessor Compatible
>10MHz Input Frequency

r--------Trr--------,
I I
:}
DATA SELECT INPUTS
DSO DS1 DS2

PROGRAM
ENABLE (PE)

LATCH SELECT
LOGIC
.

INTJ~NAL

LATCHES

OSC IN

osc OUT6----....J

DATA1~~9--------+--- FR or FV leading: positive pulses
FV < FR or FR leading: negative pulses
FV = FR and phase error within PDA window: high impedance

An open drain lock detect output at low level when phase error within PDA window
(in lock).
High impedance at all other times.

FIN

The input to the main counters normally driven from a prescaler which may beAC
coupled or when a full logic swing is available may be DC coupled.

Vss

Negative supply (normally ground)

Voo

Positive supply

7,8

OSC.IN/
OSC.OUT

These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required
between each end of the crystal and ground to provide the necessary additional
phase shift. An external crystal-generated reference signal may alternatively be
applied to OSC.IN. This may be a low-level signal AC coupled into OSC.IN or if a
full logic swing is available it may be DC coupled. The program range of the
reference counter is 6-4094 in steps of 2, with the division ratio being twice the
programmed number.

9,10,11,12

00-03

Information on these inputs is transferred to the internal latches during the appropriate data read time slot. 03 MSB, DO LSB.

15,16,17

DSO-DS2

Signal for controlling an external dual-modulus prescaler. The modulus control
level will be low at the beginning of a count cycle and will remain low until the 'A'
counter completes its cycle. The modulus control then goes high and remains
high until the 'M' counter completes its cycle at which point both counters are
reset. This gives a total division ratio of M.N +A where Nand N +1 represent the
dual modulus prescale values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including ..;-128/129.
The program range of the 'M' counter is 3-1023 and for correct program
operation M ~A. Where every possible channel is required, the
minimum division ratio should be N2-N.

An external sample and hold phase comparator gain programming resistor should
be connected between this pin and Vss.

An external hold capacitor should be conllected between this pin and Vss.

This pin is used as a strobe for the data. A logic high on this pin transfers
data from the data pins to the internal latch selected by the address, (data
select) lines, while a logic zero disables the data lines.
Data-select inputs to control the addressing of data latches.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (Voo - Vss)
Input voltage
Open drain O/P (pin 3)
All other pins
Storage temperature
Storage temperature

238

-0.5V to 7V

7V
Vss -0.3V to Voo +0.3V
-65°C to +150°C
(DG Package, NJ8821B)
-55°C to +125°C
(DP and MP packages, NJ8821)

NJ8821 INJ8821 B
2.0

J .1

J .1_

VDD =5V
FIN = LOW FREQUENCY
OV TO 5V SQUAREWAVE

1
...

.§. 6

1•5

!zw

ffi

a:
a:

::l
(.)

::l 1.0

...

(.)

II.
II.

::l

""'"
~

......... I'---.. 10MHz

1MHz"""""

i'-.

III

::l
III

0.5

0.2

0.4

INPUT FREQUENCY (MHz)

Fig.3 Typical supply current versus input frequency

'-...,
...........

'-...,

"""-

0.6
0.8
1.0
1.2
INPUT LEVEL (V .ms)

r---

1.4

1.6

FigA Typical supply current versus input level, Osc In

PROGRAMMING
Timing is generated externally, normally from a
microprocessor, and allows the user to change the data in
selected latches. The data map is Fig.5 with the PE pin used
as a strobe for the data. Taking the PE pin high will transfer
data from the data pins into the selected latch and taking this
pin low will disable the data pins, retaining that data on the
selected latch. Data transfer from all internal latches into the
counters will occur simultaneously with the transfer of data
into latch 1 and therefore this would normally be the final
latch addressed during each channel change. Timing
information for this mode of operation is given in Fig.6.
When re-programming, a reset to zero state is followed by
reloading with the new counter values. This means the
synthesiser loop lock up time will be well defined and less
than 10msec. If shorter lock up times are required, when
making only small changes in frequency, the non-resettable
version NJ8823 should be considered.

WORD

OS2

OS1

OSO

1
2
3
4
5
6
7
8

0
0
0
0
1
1
1
1

0
0

0
1
0

M1
M5
M9
A3

MO
M4
M8
A2
A6
R2
R6
R10

M3
M7
A1
A5
R1
R5
R9

M2
M6
AO
A4
RO
R4
R8

1
0
0
1
1

R3
R7

0
1

Fig.5 Data map

00-03

ISE

Fig.6 Timing diagram

239

NJ8821/NJ8821 B
PHASE COMPARATORS
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error signal to enable
fast switching between channels. This output is active until
the phase error is within the sample and hold phase detector
window, when its output becomes high impedance. Phaselock is indicated at this point with a low level on LD. The
sample and hold phase detector provides a 'fine' error signal
to give further phase adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
signal, PDA. When in phase lock this output would typically
be at (VDrrVss)/2 and any offset from this would be
proportional to phase error. The relationship between this
offset voltage and the phase error is the phase-comparator
gain which is programmable with an external resistor, RB. An
internal 50pF capacitor is used in the sample and hold
comparator.
This gain is typically:
GAIN =

10 [VDrrVss-0.7-89(RB -'h
2 x rr 50x10"'2 x RBxFR

)]

'FR

I 1600 I

5kHz

400

10kHz

200 ~ 400

600L 800

25kHz

240

800

J
I 160 I

1200

320

GAIN

x FR PRODUCT

I
I

Fig.7 RB versus gain and reference frequency

CRYSTAL OSCILLATOR
The value of RB should be chosen to give the required gain at
the reference frequency used. Fig.7 for example shows that
to achieve a gain of 380V per radian at 10kHz requires
approximately 39kQ. A second external component is
required; this is a hold capacitor of non-critical value which
might typically be 470pF, a smaller value being sufficient if
the sideband performance required is not high. Fig.7 shows
the gain normalised to a 1Hz comparison frequency; to
obtain the value for any other frequency, divide the value of
Gain Frequency product by the desired frequency.

240

When using the internal oscillator, the stability may be
enhanced at high frequencies by the use of an external
resistor between Pin 8 and the other components. A value of
150-2700 is advised.

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of VDD, as otherwise 'latch up'
may occur.

PLESSEY

Selniconductors ______________________________________

NJ8821A
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
The NJ8821A is a synthesiser circuit fabricated on the
Plessey 5-micron CMOS process and is capable of achieving
high sideband attenuation and low noise performance. The
circuit contains a reference oscillator, 11-bit programmable
reference divider, digital and sample-and-hold phase
comparators, 10-bit programmable 'M' counter, 7-bit
programmable 'A' counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external
control from a suitable microprocessor.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.

FIN

•

DS2

FIN

5 NJ8821A 16
DG 15
6

D51
DS'

VSS
VDO

ose IN

DSC OUT

•

Vss
VDO

FEATURES
•
•

PDB

PD"

MC
DS2
DSl
DS'
PE

Ne
Dse III

Dse OUT

DG20

Low Power Consumption
High Performance Sample and Hold Phase Detector

•

Microprocessor Compatible

•
•

>1OMHz Input Frequency
Military Temperature Range (-55°C to +125°C)

GG24
Fig.1 Pin connections

DATA SELECT INPUTS

'---------r-I-I---------,
I
I
i :}INTl~NAL
DSO DS1 DS2

PROGRAM
ENABLE (PE)

LATCH SELECT
LOGIC
.

LATCHES

I PDA

OSCIN
OSC OUT 6 - - - - - - - !

PDB

DATA1~~~------r-4r-~-+--r-------,

J;:;--!

'1- I

INPUT D2~-----_r~r-~-~-r_---_,
D3o-------r~r-~-._-~-~

LOCK DETECT
(LD)

I
I

Fin

I
I

-1-L ___ ~O:R~O:
VSS

MODULUS

_t-_--_--_--_--_--_-_-_-_-_-_-.-J-D1 C8yJ~~i

VDD

Fig.2 Block diagram

241

NJ8821A
ELECTRICAL CHARACTERISTICS
Test condHions (unless otherwise stated):
VDD - VSS 5V ± 0.5V
Temperature range -55°C to +125°C

DC Characteristics at V DD

= 5V

Characteristics

Min.

Supply current

MODULUS CONTROL OUT
High level
Low level

Value
Typ.

Max.

3.5
0.7

7.0
2.0

mA
mA

0.4

V
V

I.ource 1mA
Isink 1mA

V
V

Isink 4mA

V
V

l.ource4mA
ISink4mA

4.6

LOCK DETECT OUT
Low level
Open drain pull-up voltage
PDB Output
High level
Low level
3-state leakage
INPUT LEVELS
Inputs
High level
Low level

0.4

8
4.6

Conditions

Units

0.4
±0.1

JIA

0.75

V
V

0.75

V
V

0.75

V
V

FOSC, FIN = 10MHZ} 0 to 5V
FOSC FIN =1.0MHz square
,
wave

oata

4.25

Program Enable Input
High level
Low level

4.25

DSINPUTS
High level
Low level

4.25

TTL compatible
See note 1

AC Characteristics
Characteristics

Min.

FIN/OSC inputs

200

Max. operating freq. OSC/FIN inputs

10.6

Value
Typ.

Max.

Units

Conditions

mVRMS 10MHz AC coupled sinewave
MHz

VDD = 5V, Input squarewave
VDo-Vss.Note 4

Propagation delay, clock to modulus control

Strobe pulse width external mode, twiST)

JIS

Data set-up time, t.(DATA)

JIS

Data hotd time, tH(DATA)

JIS

Address set-up time, tSE

JIS

Address hold time, tHE

Digital phase detector propagation delay
Gain programming resistor, RS

JIS
500

See Fig.7
Note 3

Hold capacitor, CH

Output resistance PDA

Digital phase detector gain

Note 2

VlRad

NOTES
1. Data inputs have internal 'pull-up' resistors to enable thern to be driven frorn TIL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. Finite output resistance of internal voltage follower and 'on' resistance of sarnple switch driving this pin will add a finite tirne-constant to the loop. A 1nF
hold capacitor will give a rnaxirnurn tirne-constant of 5 rnicroseconds.
4. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.

242

NJ8821A
PIN DESIGNATION
Pin No.

Name

Description

PDA

Analogue output from the sample and hold phase comparator for use as a 'fine'
error signal. Output at (VDD-Vss)/2 when in lock. Voltage increases as FV phase
lead increases and decreases as FR phase lead increases. Output is linear over
only a narrow phase window determined by gain programmed by RB.

PDB

Three-state output from the phase/frequency detector for use as a 'coarse' error
signal.
FV > FR or FV leading: positive pulses
FV < FR or FR leading: negative pulses
FV = FR and phase error within PDA window: high impedance

An open drain lock detect output at low level when phase error within PDA window
(in lock).
High impedance at all other times.

FIN

The input to the main counters normally driven from a prescalerwhich may beAC
coupled or when a full logic swing is available may be DC coupled.

Vss

Negative supply (normally ground)

VDD

Positive supply

8,9

7,8

11,12,13,14

9,10,11,12

DO-D3

18,19,20

15,16,17

Signal for controlling an external dual-modulus prescaler. The modulus control
level will be low at the beginning of a count cycle and will remain low until the 'A'
counter completes its cycle. The modulus control then goes high and remains
high until the 'M' counter completes its cycle at which point both counters are
reset. This gives a total division ratio of M.N +A where Nand N +1 represent the
dual modulus prescale values.
The programme range of the 'A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including +128/129.
The program range of the 'M' counter is 3-1023 and for correct program
operation M -;;'A. Where every possible channel is required, the minimum
division ratio should be N2-N.

An external sample and hold phase comparator gain programming resistor should
be connected between this pin and Vss.

An external hold capacitor should be connected between this pin and Vss.

OSC.IN These pins form an on-chip reference oscillator when a parallel resonant crystal is
OSC.OUT connected across them. Capacitors of an appropriate value are also required
between each end of the crystal and ground to provide the necessary additional
phase shift. An external crystal-generated reference signal may alternatively be
applied to OSC.IN. This may be a low-level signal AC coupled into OSC.IN or if a
full logic swing is available it may be DC coupled. The programme range of the
reference counter is 6-4094 in steps of 2, with the division ratio being twice the
programmed number.
Information on these inputs is transferred to the internal latches during the appropriate data read time slot. D3 MSB, DO LSB.
This pin is used as a strobe for the data. A logic high on this pin transfers
data from the data pins to the internal latch selected by the address, (data
select) lines, while a logic zero disables the data lines

DSO-DS2 Data-select inputs to control the addressing of data latches.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (V DD - V ss)
Input voltage
Open drain O/P (pin 3)
All other pins
Storage temperature

-0.5V to 7V
7V
Vss -0.3V to VDD +0.3V
-65°C to +150°C

243

NJ8821A
2.0

.i ,L

1.5

.5.
Iz
III

.....

II:
II:

:::l

:::l 1.0
(J

~
"":::l
i1 OMHz Input Frequency

•

PDA

PD.

FIN

NIC

CAP

FIN

ENABLE

CLOCK

OSC.!N

DATA

OSC.OUT

PDA
PD.

CLOCK
DATA

NIC

NIC
OSC OUT

DP16 (NJ8822)
DG16 (NJ8822B)

MP18 (NJ8822)

Fig. I Pin connections - top view, not to scale

OUTPUT
(Me)

Fig.2 Block diagram. Pin numbers for MP package

246

are shown in brackets.

NJ8822,NJ8822B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
VOD-VSS SV ± O.SV
Temperature range: NJ8822 -30°C to +70°C, NJ88228 -40°C to +8S0C

DC Characteristics at Voo

= 5V

Characteristics

Min.

Value
Typ.

Supply current

MODULUS CONTROL OUT
High level
Low level

mA
mA

FOSC, FIN
FOSC FIN
,

0.4

V
V

I source 1mA
I sink 1mA

0.4
8

V
V

'sink4mA

0.4

V
V

I source SmA
I sink 5mA

±0.1

f.1A

4.6

3-state leakage

Conditions

Units

S.5
1.5

4.6

LOCK DETECT OUT
Low level
Open drain pull-up voltage
PDB OUTPUT
High level
Low level

Max.

= 10MHzt 0 to SV
= 1MHz square
wave

AC Characteristics
Characteristics
FIN/OSC inputs
Max. operating freq. OSC/FIN inputs

Min.

Positive going threshold, VT +
Negative gOing threshold, VT-

Units

Conditions

mV RMS

10MHz AC coupled sinewave

MHz

Voo = SV, Input squarewave
VOO-Vss, 25°C

30
0.5
0.5
0.2
0.2
0.2
0.2
0.2

tCH

3
2

Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB

Max.

200

Propagation delay, clock to modulus control
Programming inputs
Clock high time, teH
Clock low time, tel
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tos
Data hold time, tOH
Clock rise and fall times

Value
Typ.

500

ns
f.1S
f.1s
f.1s
f.1S
f.1s
f.1s
f.1s
V
V

Note 2

All timing periods
are referenced to
the negative
transition of the
clock waveform
Note 1

Hold capacitor, CH

Programming capacitor, CAP

Output resistance, PDA

Note 3

NOTES
1 Data, Clock and Enable inputs are high impedance Schmitt buffers without ull up resistors. They are therefore not TIL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and 'on' resistance of sample switch driving this pin will add a finite time-constant to
the loop. A 1nF hold capacitor will give a maximum time-constant of 5 microseconds.
4. The inputs to the device should be at logic '0' when power is applied if latch up conditions are to be avoided. This includes the signal/osc.
frequency inputs.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD-VSS)
-O.SV to 7V
Input voltage
Open drain O/P (pin 3 (DG) pin 4 (MP))
7V
All other pins
Vss -0.3V to VOO +0.3V

Storage temperature
Storage temperature

-SSOC to +12SoC
(DP and MP packages, NJ8822)
-65°C to +150°C
(DG package, NJ88228)

247

NJ8822,NJ8822B
PIN DESIGNATION
Pin No.

Name

Description

PDA

Analog output from the sample and hold phase comparator for use as a 'fine' error signal.
Voltage increases as FV (FV is the output from the 'M' counter) phase lead increases and
decreases as FR (FR is the output from the reference counter) phase lead increases.
Output is linear over only a narrow phase window determined by gain (programmed by
RB). In a type 2 loop, this pin is at (Vee - Vss)/2 when the system is in lock.
Not connected.
Three-state output from the phase/frequency detector for use as a 'coarse' error signal.
FV> FR or FV leading: positive pulses.
FV < FR or FR leading: negative pulses.
FV = FR and phase error within PDA window: high impedance.
An open drain lock detect output at low level when phase error is within PDA window
(in lock); high impedance at all other times.
The input to the main counters. It is normally driven from a prescaler which may be AC
coupled or, when a full logic swing is available, may be DC coupled.
Negative supply (ground).
Positive supply (normally 5V).
Not connected.
These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required between
each end of the crystal and ground to provide the necessary additional phase shift. The
addition of a 220 ohm resistor between Pin 8 and the crystal will improve stability.
An external reference signal may alternatively be applied to OSC.IN. This may be a
low-level signal, AC coupled, or if a full logic swing is available it may be DC coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the division ratio
being twice that programmed.
Not connected.
Information on this input is transferred to the internal latches during the appropriate data
read time slot. Data is high for a '1' and low for a '0'. There are three data words which
control the NJ8822, MSB is first in the order, 'A' - (7 bits), 'M' - (10 bits), 'R' - (11 bits).
Data is clocked in on the negative transition of the clock waveform. If less than 28 negative
clock transitions have been received when the enable line goes low (i.e. only 'M' and 'A' will
have been clocked in) then the 'R' counter latch will remain unchanged and only 'M' and
'A' will be transferred from the input shift register to the counter latches.
This will protect the 'R' counter from being corrupted by any glitches on the clock line after
only 'M' and 'A' have been loaded.
If 28 negative transitions have been counted then the 'R' counter will be loaded with the
new data.
When the enable is low the data and clock inputs are disabled internally. As soon as the
enable is high the data and clock input are enabled and data may be clocked into the
device. The data is transferred from the input shift register to the counter latches on the
negative transition of the enable input and both inputs to the phase detector are
synchronised to each other. Enable transitions only allowed when CLK is high.
This pin allows an external capacitor to be put in parallel with the ramp capacitor, and
allows further programming of the device. (This capacitor is connected from CAP to Vss).
Output for controlling an external dual modulus prescaler. The modulus control level will
be low at the beginning of a count cycle and will remain low until the 'A' counter completes
its cycle. The modulus control then goes high and remains high until the 'M' counter
completes its cycle at which point both counters are reset. This gives a total division ratio of
M.N + A where Nand N + 1 represent the dual modulus prescaler values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including ..;- 128/129.
The programming range of the 'M' counter is 3-1023 and for correct program operation
M ;;. A. Where every possible channel is required, the minimum division ratio should be
N2 - N.
An external sample and hold phase comparator gain programming resistor should be
connected between this pin and Vss.
An external hold capacitor should be connected between this pin and Vss.

DG,DP
1

MP
1

3
2

N/C
PDB

FIN

5
6

6
7
8

7,8

9,10

Vss
Vee
NIC
esc. IN/
eSC.OUT

NIC
DATA

CLK

ENABLE

CAP

248

NJ8822,NJ8822B
2.0

r----r-.....,...--r--r----r-.....,...--r--r----r-...,

loo
i

=15V
FIN = LOW FREQUENCY
OV TO 5V SQUAREWAVE

1.5

tzw

""-

II:

1.0

1----i--+-+-+-t-""7F----iI--t--+=ooi

en 0.5

1----ir--t7""q--=...r-""-t--t----II--t--+--i

"'"t---

;:)

.......

..........

.............

r--

10MHz

r--

lMHz

INPUT FREQUENCY (MHz)

Fig.3 Typical supply current v. input frequency
0.2

0.4

0.6

O.S

1.0

1.4

1.2

1.6

INPUT lEVEL (V rms)

Fig.4 Typical supply current v. input level, Osc In

PROGRAMMING
Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of the R counter,
which can be programmed in the range 3 to 2047.
fosc

2 X fcomp
ie where fcomp = comparison frequency
fosc = oscillator frequency
R = R counter ratio
For example where crystal frequency = 10MHz and a
channel spacing comparison frequency of 12.5kHz is
required,
10 7
R=
=400
2 X 12.5 X 103
Thus the R register would be programmed to 400 expressed
in binary.
NB The total divider range is from 6 to 4094 in steps of 2.

VCO Divider Chain
The synthesised frequency of the voltage control oscillator
(VeO) will depend on the division ratio of the M and A

counters, the value of the external two modulus prescaler
(NIN + 1) and the value of the comparison frequencyfcomp.
The division ratio P = NM + A
where M is the ratio of the M counter in the range 3 to 1023

CLOCK

~I·

ENABLE _ _ _....l... ____

DATA

tCH

and A is the ratio of the A counter in the range 1 to 127.
NoteM ;"'A
fveo
AlsoP + - fcomp
For example if the desired veo frequency
275M Hz, the
comparison frequency is 12.5kHz and a two modulus
prescaler of 764/65 is being used, then:
275 X 10 6
P =
=22 X10 3
12.5 X 103
Now P
NM +A
which can be rearranged to be PIN = M + AIN
In our example we have
22 X 103
A
A
= M +- therefore 343.75 = M +64
6
64
M is programmed to the integer part = 343 and A is
programmed to the fractional part times 64
ie A = 0.75 X 64 = 48
NB The minimum ratio that can be used is N2 - N
To check P = 343 X 64 + 48 = 22000 which is the required
divide ratio.
When re-programming, a reset to zero state is followed by
reloading with the new counter values. This means the
synthesiser loop lock up time will be well defined and less
than 10msec. If shorter lock up times are required, when
making only small changes in frequency, the non resettable
version NJ8824 should be considered.

-L_-j-

LF-

tCl

-I

I '"~ rL

------£--51X------

Fig.S Timing diagram showing timing periods required for correct operation

249

NJ8822,NJ8822B

CLOCK

ENABLE

(15) 26

(16) 27

(17) 26

____ JlSLfl...J

--.J

Fig.6 Timing diagram showing programming details

PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain
where K is phase detector constant (volts/rad), K v is
the VCO constant (rad-sees/volt) and P is the overall loop
division ratio. When P is large and the loop gain is low, noise
may be reduced by employing a phase comparator with a
high gain. The sample and hold phase detector within the
NJ8822 has both a high gain and uses a double sampling
technique to reduce spurious ouputs to a low level.
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error Signal to enable
fast switching between channels.
This output is active until the phase error is within the
sample and hold phase detector window, when its output
becomes high impedance. Phase-lock is indicated at this
pOint with a low level on LD. The sample and hold phase
detector provides a 'fine' error signal to give further phase
adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
Signal, PDA. When in phase lock this output would typically
be at (VorrVss)/2 and any offset from this would be
proportional to phase error.
KK viP,

The relationship between this offset voltage and the phase
error is the phase-comparator gain which is programmable
with an external resistor, RS and a capacitor, CAP.
An internal SOpF capacitor is used in the sample and hold
comparator.
This gain is typically:
GAIN = 10 [VorrVss-0.7-89(RS -'h)]
2 rr [CAP + SOX10-12] x RSxFR

The value of

RS and CAP should be chosen to give the required gain
at the reference frequency used. Fig.8 shows that to
achieve a gain of 380V per radian at 10kHz requires RS to
be approximately 391<0, CAP is zero. A hold capaCitor
(CH) of non-critical value which might be typically 470pF
is connected from CH to Vss. A smaller value is sufficient
if the sideband performance required is not high.
The output from the sample/phase detector should be
combined with that of the coarse phase/frequency detector
and filtered to generate a single control voltage to drive the

veo.

lM~---r--~----r---'----r--~;---'----'

VT+

Fig.7 Timing diagram showing voltage thresholds

CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be
enhanced at high frequencies by the use of an external
resistor between Pin 8 and the other components. A value of
1S0-27OO is advised.

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of Voo, as otherwise 'latch up'
may occur.

250

L 800 I 1200 I 1600
I 400 I 800 I 800

5kHz

400

10kHz

200

25kHz

80 .1 160.1 240.1 320
K IN VOLTS/RAD.

GAIN K FR PRODUCT mV/RAD-Sji;C
(1) CAPeKI = OpF
(2) CAPeK! = 47pF
(3) CAPeK! = o.8nF

Fig.8 RB v. gain and reference frequency

NJ8822A
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
WITH RESETTABLE COUNTERS
The NJ8822A is a synthesiser circuit fabricated on the
Plessey 5-micron CMOS process and is capable of achieving
high sideband attenuation and low noise performance. It
contains a reference oscillator, ll-bit programmable
reference divider, digital and sample-and-hold phase
comparators, 10-bit programmable 'M' counter, 7-bit
programmable 'A' counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters subsequent updating can
be abbreviated to 17 bits when only the 'A' and 'M' counters
require changing.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser for up to 950MHz operation.

•
•

'--'

16 PCH

POB [ 2

lSP RB

LO [ 3

14] Me

FIN [ 4

13 ] CAP

Vss [ 5 8822A 12 ] ENABLE
VDD [

OSC.lN [ 7
OSC.OUT [ 8

11 ] CLOCK
10] DATA

9] N/C

DG16
Fig. 1 Pin connections - top view, not to scale

FEATURES

•
•
•

PDA [ 1

Low Power Consumption
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
> 1OMHz Input Frequency
Military Temperature Range (-55°C to +125°C)

FIN

15
VSS 0 - -

I MODULUS
CONTROL

I-------------:.=.,J
L ______________________
14

VDDo!--

OUTPUT
~

Fig.2 Block diagram.

251

NJ8822A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Voo-Vss SV ± O.SV
Temperature range -SsoC to +12SOC

DC Characteristics at Voo

= 5V

Characteristics

Min.

Supply current

MODULUS CONTROL OUT
High level
Low level

Value
Typ.

Max.

6.3
0.7

7.0
2.0

mA
mA

0.4

V
V

Isource 1mA
Isink 1mA

V
V

Isink 4mA

0.4

V
V

I source 4mA
Isink 4mA

±0.1

Jl.A

4.6

LOCK DETECT OUT
Low level
Open drain pull-up voltage

0.4

Conditions

Units

FOSC, FIN = 10MHZ( 0 to SV
FOSC FIN = 1MHz square
wave
,

poe OUTPUT
4.6

High level
Low level
3-state leakage

AC Characteristics
Characteristics

Min.

Value
Typ.

Max.

Units

Conditions

FIN/OSC inputs

200

mVRMS

10MHz AC coupled sinewave

Max. operating freq. OSC/FIN inputs

MHz

Voo = SV, Input squarewave
Voo-Vss, 2SoC

Propagation delay, clock to modulus control

Programming inputs
Clock high time, teH
Clock low time, tel
Enable set-up time, tss
Enable hold time, tSH
Data set-up time, tos
Data hold time, tOH
Clock rise and fall times

30
O.S
O.S
0.2
0.2
0.2
0.2
0.2

Positive going threshold, Vr +
Negative going threshold, Vr-

tCH

3
2

Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB

ns
Jl.s
Jl.s
/lS
/lS
Jl.s
/ls
Jl.s
V
V

Note 2

All timing periods
are referenced to
the negative
transition of the
clock waveform
Note 1

SOO
S

Hold capacitor; CH

Programming capacitor, CAP

Note 3

Output resistance, PDA
kQ
S
NOTES
1. Data, Clock and Enable inputs are high impedance Schmitt buffers without pull up resistors. They are therefore not TIL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and 'on' resistance of sample switch driving this pin will add a finite time-constant to
the loop. A 1nF hold capacitor will give a maximum time-constant of S microseconds.
4. The inputs to the device should be at logic '0' when power is applied if latch up conditions are to be avoided. This includes the signal I osc.
frequency inputs.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (VOD-Vss)
Input voltage
Open drain O/P (pin 3)
All other pi ns
Storage temperature

252

-O.SV to 7V
7V
Vss -0.3V to Voo +0.3V
-6SoC to +1S0°C

NJ8822A
PIN DESIGNATION
Pin No.

Name

Description

PDA

N/C
PDB

FIN

5
6

Vss
VDD

Not connected.
Three-state output from the phase/frequency detector for use as a 'coarse' error signal.
FV > FR or FV leading: positive pulses.
FV < FR or FR leading: negative pulses.
FV = FR and phase error within PDA window: high impedance.
An open drain lock detect output at low level when phase error is within PDA window
(in lock); high impedance at all other times.
The input to the main counters. It is normally driven from a prescaler which may be AC
coupled or, when a full logic swing is available, may be DC coupled.
Negative supply (ground).
Positive supply (normally 5V).

7,8

N/C
OSC.IN/
OSC.OUT

9
10

N/C
DATA

ClK

ENABLE

CAP

Output for controlling an external dual modulus prescaler. The modulus control level will
be low at the beginning of a count cycle and will remain low until the 'A' counter completes
its cycle. The modulus control then goes high and remains high until the 'M' counter
completes its cycle at which point both counters are reset. This gives a total division ratio of
M.N + A where Nand N + 1 represent the dual modulus prescaler values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including + 128/129.
The programming range of the 'M' counter is 3-1023 and for correct program operation
M ;;. A. Where every possible channel is required, the minimum division ratio should be
N2 - N.

An external sample and hold phase comparator gain programming resistor should be
connected between this pin and Vss.
An external hold capacitor should be connected between this pin and Vss.

Not connected.
These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required between
each end of the crystal and ground to provide the necessary additional phase shift. The
addition of a 220 ohm resistor between Pin 8 and the crystal will improve stability.
An external reference signal may alternatively be applied to OSC.IN. This may be a
low-level signal, AC coupled, or if a full logic swing is available it may be DC coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the division ratio
being twice that programmed.
Not connected.
Information on this input is transferred to the internal latches during the appropriate data
read time slot. Data is high for a '1' and low for a '0'. There are three data words which
control the NJ8822, MSB is first in the order, 'A' - (7 bits), 'M' - (10 bits), 'R' - (11 bits).
Data is clocked in on the negative transition of the clock waveform. If less than 28 negative
clock transitions have been received when the enable line goes low (i.e. only 'M' and 'A' will
have been clocked in) then the 'R' counter latch will remain unchanged and only 'M' and
'A' will be transferred from the input shift register to the counter latches.
This will protect the 'R' counter from being corrupted by any glitcheson the clock line after
only 'M' and 'A' have been loaded.
If 28 negative transitions have been counted then the 'R' counter will be loaded with the
new data.
When the enable is low the data and clock inputs are disabled internally. As soon as the
enable is high the data and clock input are enabled and data may be clocked into the
device. The data is transferred from the input shift register to the counter latches on the
negative transition of the enable input and both inputs to the phase detector are
synchronised to each other. Enable transitions only allowed when ClK is high.
This pin allows an external capacitor to be put in parallel with the ramp capacitor, and
allows further programming of the device. (This capacitor is connected from CAP to Vss).

253

NJ8822A

-.,....-r---r-......--.--r---r--,.

2.0 r---r-......

loo

1
a:

1.0 1---+-+-+-t--::~--+7""I--+--+--l

1.5

=15V
FIN = LOW FREQUENCY
OV TO 5V SQUAREWAVE

0.5

" --

t--+-~7"f--+--+--+-+-+--+--l

~ ~ i"-..
........

INPUT FREQUENCY (MHz)

f'...

10MHz
lMHz

Fig.3 Typical supply current v. input frequency
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

INPUT LEVEL (V rmB)

Fig.4 Typical supply current v. input level, Osc In

PROGRAMMING
Reference Divider Chain

and A is the ratio of the A counter in the range 1 to 127.
Note M ;;'A

The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of the R counter,
which can be programmed in the range 3 to 2047.

fosc

10 3

=400

2 X 12.5 X
Thus the R register would be programmed to 400 expressed
in binary.
NB The total divider range is from 6 to 4094 in steps of 2.

VCO Divider Chain
The synthesised frequency of the voltage control oscillator
(VeO) will depend on the division ratio of the M and A
counters, the value of the external two modulus prescaler
(N/N + 1) and the value of the comparison frequency fcomp.
The division ratio P = NM + A
where M is the ratio of the M counter in the range 3 to 1023

AlsoP

fvco

+fcomp
--

For example if the desired veo frequency 275MHz, the
comparison frequency is 12.5kHz and a two modulus.
prescaler of +64/65 is being used, then:

P =

275 X 106
12.5 X 10 3

=22 X10 3

NowP =NM +A

which can be rearranged to be P/N = M
In our example we have

X1~

- - - = M +- therefore 343.75 = M +64
6
64
M is programmed to the integer part = 343 and A is
programmed to the fractional part times 64
ie A = 0.75 X 64 = 48
NB The minimum ratio that can be used is N2 - N
To check P = 343 X 64 + 48 = 22000 which is the required
divide ratio.
When re-programming, a reset to zero state is followed by
reloading with the new counter values. This means the
synthesiser loop lock up time will be well defined and less
than 10msec. If shorter lock up times are required, when
making only small changes in frequency, the non resettable
version NJ8824 should be considered.

Fig.5 Timing. diagram showing timing periods required for correct operation

254

+ A/N

NJ8822A

3
CLOCK

(15) 26

(16) 27

(17) 28

____ SULSl...J

ENABLE~

Fig.6 Timing diagram showing programming details

PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain
KK viP, where K is phase detector constant (volts/rad), K vis
the VCO constant (rad-secs/volt) and P is the overall loop
division ratio. When P is large and the loop gain is low, noise
may be reduced by employing a phase comparator with a
high gain. The sample and hold phase detector within the
NJ8822 has both a high gain and uses a double sampling
technique to reduce spurious ouputs to a low level.
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error signal to enable
fast switching between channels.
This output is active until the phase error is within the
sample and hold phase detector window, when its output
becomes high impedance. Phase-lock is indicated at this
pOint with a low level on LD. The sample and hold phase
detector provides a 'fine' error signal to give further phase
adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
signal, PDA. When in phase lock this output would typically
be at (Vor>-Vss)/2 and any offset from this would be
proportional to phase error.

The relationship between this offset voltage and the phase
error is the phase-comparator gain which is programmable
with an external resistor, RB and a capacitor, CAP.
An internal 50pF capacitor is used in the sample and hold
comparator.
This gain is typically:
GAIN = 10 [Vor>-Vss-0.7-89(RB -'1,)]
211' [CAP + 50x10-12 ] x RBxFR

The value of

RB and CAP should be chosen to give the required gain
at the reference frequency used. Fig.8 shows that to
achieve a gain of 380V per radian at 10kHz requires RB to
be approximately 39kO, CAP is zero. A hold capacitor
(CH) of non-critical value which might be typically 470pF
is connected from CH to Vss. A smaller value is sufficient
if the sideband performance required is not high.
The output from the sample/phase detector should be
combined with that of the coarse phaselfrequency detector
and filtered to generate a single control voltage to drive the
VCO.

1M~--~--~----r---'----r---'----~--~

VT·

1~~~d----+--~----+----r---+----t-~
RB

Fig.7 Timing diagram showing voltage thresholds
10k~~~---f~-4~~+----r---t----r---,

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of Voo, as otherwise 'latch up'
may occur.

FiI

5kHz

400

10kHz

200

25kHz

I
I
I

800
400
160

I 1200 I 1600
I 600 I 800
I 240 I 320

K IN VOLTS/RAD.

GAIN _ FR PRODUCT mViRAD-SEC
(1) CAPeK! = OpF
(2) CAPex! = 47pF
(3) CAPext = O.8nF

Fig.B RB v. gain and reference frequency

255

PLESSEY
Semiconductors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
NJ8823, NJ8823B
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH NON-RESETTABLE COUNTERS
The NJ8823/NJ8823B is a synthesiser circuit fabricated on
the Plessey 5-micron CMOS process and is capable of
achieving high sideband attenuation and low noise
performance. The circuit contains a reference oscillator, 11bit programmable reference divider, digital and sample-andhold phase comparators, 1D-bit programmable 'M' counter,
7-bit programmable 'A' counter and the necessary control
and latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external
control from a suitable microprocessor.
The NJ8823 is available in Plastic OIL (OP) and Miniature
Plastic OIL (MP) poackages, both with operating
temperature range of -30°C to +70°C. The NJ8823B is
available only in Ceramic OIL package with operating
temperature range of -40°C to +85°C.

POA [ ~
POB [ 2

pRe

18 P MC

FIN [ 4

POS2

Vss [ 5

NJ8823 16 POSI
VDD [ 6 NJ8823B 15 OSO

OSC IN[ 7
OSC

ouT[
oo[

14 P PE

PNC
P03
11 b02

DP20, MP20 (NJ8823)
DG20 (NJ8823B)

FEATURES

•

20 pCH
19

LO [ 3

01 [ 10

••
••

'-"

Low Power Consumption

Fig.l Pin connections

High Performance Sample and Hold Phase Detector
Microprocessor Compatible

> 10MHz Input Frequency
Fast Lock Up Time

,-------I
I

-:}

DATA SELECT INPUTS

~r~IS~lS~-

PROGRAM
ENABLE (PEl

osc

~TCH

SELECT
LOGIC
.

INTJ~NAL
LATCHES

I POA

OSC OUT ( > - - - - - . . . )

r+.':o:!dY.#~+t;:;!:rr,

OATA1~~~--------~~--~+---~---------;

INPUT 02 FR or FV leading: positive pulses
FV < FR or FR leading: negative pulses
FV = FR and phase error within PDA window: high impedance

An open drain lock detect output at low level when phase error within PDA window
(in lock).
High impedance at all other times.

FIN

The input to the main counters normally driven from a prescaler which may be AC
coupled or when a full logic swing is available may be DC coupled.

Vss

Negative supply (normally ground)

Voo

Positive supply

7,8

OSC.IN/
OSC.OUT

These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required
between each end of the crystal and ground to provide the necessary additional
phase shift. An external crystal-generated reference Signal may alternatively be
applied to OSC.IN. This may be a low-level signal AC coupled into OSC.IN or if a
full logic swing is available it may be DC coupled. The program range of the
reference counter is 6-4094 in steps of 2, with the division ratio being twice the
programmed number.

9,10,11,12

DO-D3

Information on these inputs is transferred to the internal latches during the appropriate data read time slot. D3 MSB, DO LSB.

15,16,17

DSO-DS2

Signal for controlling an external dual-modulus prescaler. The modulus control
level will be low at the beginning of a count cycle and will remain low until the 'A'
counter completes its cycle. The modulus control then goes high and remains
high until the 'M' counter completes its cycle at which point both counters are
reset. This gives a total division ratio of M.N +A where Nand N +1 represent the
dual modulus prescale values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including +128/129.
The program range of the 'M' counter is 3-1023 and for correct program
operation M ;;:'A. Where every possible channel is required, the
minimum division ratio should be N2-N.

An external sample and hold phase comparator gain programming resistor should
be connected between this pin and Vss.

An external hold capacitor should be connected between this pin and Vss.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (Voo - Vss)
Input voltage
Open drain O/P (pin 3)
All other pins
Storage temperature
Storage temperature

258

-0.5V to 7V

7V
Vss -0.3V to Voo +0.3V
-65°C to +150°C
(DG Package, NJ8823B)
-55°C to +125°C
(DP and MP Packages, NJ8823)

NJ8823,NJ88238
2.0

t I

ia
a:

JJJ

<"
.5.

1.5

...

OS~/ / '
/'

1.0

./'

III 0.5

...........

V ..-V

~ S
a:
a:

"""\

::l

.....-V V

J J-

.1 .1

Voo =SV
FIN = LOW FREQUENCY
OV TO SV SQUAREWAVE

Joo ='SV
OSC IN. FIN = OV TO SV SQUAREW,VE

-r;;;;

U 4

::;

iil

""" """
1MHz""'"

......... 10MHz

.........

TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO FIN
AND OSC IN.
I

1
0.2

1"--. I'-...
I"-- r--...... ......

0.4

INPUT FREQUENCY (MHz)

Timing is generated externally. normally from a
microprocessor. and allows the user to change the data in
selected latches. The data map is Fig.5 with the PE pin used
as a.strobe for the data. Taking the PE pin high will transfer
data from the data pins into the selected latch and taking this
pin low will disable the data pins. retaining that data on the
selected latch. Data transfer from all internal latches into the
counters will occur simultaneously with the transfer of data
into latch 1 and therefore this would normally be the final
latch addressed during each channel change. Timing
information for this mode of operation is given in Fig.6.
When re-programming. the counters are changed only
when they reach a zero state. There is no reset to zero state.
This means the synthesiser loop lock up time will be variable.
For the case when only small changes in frequency are
required. the non-resettable synthesiser should achieve the
shortest loop lock up times.

1.4

1.6

Fig.4 Typical supply current versus input level. Osc In

Fig.3 Typical supply current versus input frequency

PROGRAMMING

0.6
0.8 1.0
1.2
INPUT LEVEL (V ,ma)

WORD

DS2

DSl

DSO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Ml
M5
M9
A3

MO
M4
M8
A2
A6
R2
R6
Rl0

M3
M7
Al
A5
Rl
R5
R9

M2
M6
AO

3
4

5
6
7
8

R3
R7

RO
R4
R8

Fig.S Data map

~1~p3~ ljjIII!//1II'Ji'---_------.J'III/III!!/I!11///
PE

00-03
IH
(DATA)
ISE

TW(ST)

Fig.6 Timing diagram

259

NJ8823,NJ8823B
PHASE COMPARATORS
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error signal to enable
fast switching between channels. This output is active until
the phase error is within the sample and hold phase detector
window, when its output becomes high impedance. Phaselock is indicated at this point with a low level on LD. The
sample and hold phase detector provides a 'fine' error signal
to give further phase adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
signal, PDA. When in phase lock this output would typically
be at (VDrrVss)/2 and any offset from this would be
proportional to phase error. The relationship between this
offset voltage and the phase error is the phase-comparator
gain which is programmable with an external resistor, RB. An
internal 50pF capacitor is used in the sample and hold
comparator.
This gain is typically:
GAIN =

10 [VDrrVs9-0.7-89(RB -'II
2 x 1T 50x10- 12 x RBxFR

)]

1Mr---~--;r---.--~---,----;---;---,

1~r-~+---4---~---+---+----r---+---,

RB
10kr---~---+--~~~+---~---+----r---;

r--;;R

5kHz
10kHz
25kHz

400
200
80

I
I

t
800
400
160

I 1200 I 1600 i
I 600 -.l 800 J
I 240 I 320 I

GAIN

x FR PRODUCT

Fig. 7 RB versus gain and reference frequency

CRYSTAL OSCILLATOR
The value of RB should be chosen to give the required gain at
the reference frequency used. Fig.7 for example shows that
to achieve a gain of 380V per radian at 10kHz requires
approximately 39kO. A second external component is
required; this is a hold capacitor of non-critical value which
might typically be 470pF, a smaller value being sufficient if
the sideband performance required is not high. Fig.7 shows
the gain normalised to a 1Hz comparison frequency; to
obtain the value for any other frequency, divi.de the value of
Gain Frequency product by the desired frequency.

260

When using the internal oscillator, the stability may be
enhanced at high frequencies by the use of an external
resistor between Pin 8 and the other components. A value of
150-2700 is advised.

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of VDD, as otherwise 'latch up'
may occur.

PLESSEY_____________________________________
Senticonduclors
NJ8824, NJ8824B
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
WITH NON-RESETTABLE COUNTERS

The NJ8824 is a synthesiser circuit fabricated on the
Plessey 5-micron CMOS process and is capable of achieving
high sideband attenuation and low noise performance. It
contains a reference oscillator, 11-bit programmable
reference divider, digital and sample-and-hold phase
comparators, 10-bit programmable 'M' counter, 7-bit
programmable 'A' counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although 28 bits of data are initially
required to program all counters subsequent updating can
be abbreviated to 17 bits when only the 'A' and 'M' counters
require changing.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 or SP8704 series to produce a
universal binary coded synthesiser for up to 960MHz
operation.

FEATURES
Low Power Consumption

••
•

POA
CH
RB

POB

NIC

CAP

FIN

CAP

FIN

ENABLE

Vss

ENABLE

Vss

CLOCK

VDD

DATA

NIC

NIC
OSC OUT

OSC IN

DP16 (NJ8824)
DG16 (NJ8824B)

MP18 (NJ8824)

Fig. I Pin connections - top view, not to scale

High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature

•

> 10MHz Input Frequency

•

Fast Lock Up Time

PDA

DATA 110(12)

ENABLE¢I~12~(1~4L)--~--~~~--~~~~~----CLOCK 111 (13)

I
I
15(6)
VSS~

14(16)

VDD~

I MODULUS
C:ONTROL
I

L ______________________ J

OUTPUT
(MC)

Fig.2 Block diagram. Pin numbers for MP package are shown in brackets.

261

NJ8824,NJ8824B
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
VOD-VSS 5V ± 0.5V
Temperature range: NJ8824 -30°C to +70°C, NJ8824B -40°C to +85°C

DC Characteristics at V DD = SV
Characteristics

Min.

Value
Typ.

Supply current

Max.

Conditions

Units

5.5
1.5 .

mA
mA

FOSC, FIN
FOSC FIN
,

0.4

V
V

Isource 1mA
Isink 1mA

V
V

Isink4mA

0.4

V
V

I source 5mA
I sink 5mA

±0.1

/iA

= 10MHzt 0 to 5V
= 1MHz square
wave

MODULUS CONTROL OUT
High level
Low level

4.6

LOCK DETECT OUT
Low level
Open drain pull-up voltage

0.4

PDB OUTPUT
High level
Low level

4.6

3-state leakage

AC Characteristics
Characteristics

Min.

Value
Typ.

Max.

Units

Conditions

FIN/OSC inputs

200

mVRMS

10MHz AC coupled sinewave

Max. operating freq. OSC/FIN inputs

MHz

Voo = 5V, Input squarewave
Voo-Vss, 25°C

Propagation delay, clock to modulus control

Note 2

Programming inputs
Clock high time, teH
Clock low time, tel
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tos
Data hold time, tOH
Clock rise and fall times
Positive going threshold, VT +
Negative going threshold, VT-

0.5
0.5
0.2
0.2
0.2
0.2
0.2

tCH

/is
/is
/is
/is
/is
/is

All timing periods
are referenced to
the negative
transition of the
clock waveform

/is

3
2

V
V

Note 1

Phase Detector
Digital phase detector propagation delay
Gain programming resistor, RB

500

Hold capacitor, CH

Programming capacitor, CAP

Output resistance, PDA

Note 3

NOTES
1. Data, Clock and Enable inputs are high impedance Schmit! buffers without pull up resistors. They are therefore not TIL compatible.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and 'on' resistance of sample switch driving this pin will add a finite time-constant to
the loop. A 1nF hold capacitor will give a maximum time-constant of 5 microseconds.
4. The inputs to the device should be at logic '0' when power is applied ~ latch up conditions are to be avoided. This includes the signal/ esc.
frequency inputs.

ABSOLUTE MAXIMUM RATINGS
Supply voltage (VOD-Vss)
-0.5V to 7V
Input voltage
Open drain O/P (pin 3 (DG) pin 4 (MP»
7V
All other pins
Vss-0.3V to Voo +0.3V

262

Storage temperature
Storage temperature

-55°C to +125°C
(DP and MP packages, NJ8824)
-65°C to +150°C
(DG packages, NJ8824B)

NJ8824,NJ8824B
PIN DESIGNATION
Pin No,
Name

Description

PDA

Analog output from the sample and hold phase comparator for use as a 'fine' error signal.
Voltage increases as FV (FV is the output from the 'M' counter) phase lead increases and
decreases as FR (FR is the output from the reference counter) phase lead increases.
Output is linear over only a narrow phase window determined by gain (prograrr.med by
RB). In a type 2 loop, this pin is at (Voo - Vss)/2 when the system is in lock.
Not connected.
Three-state output from the phase/frequency detector for use as a 'coarse' error signal.
FV> FR or FV leading: positive pulses.
FV < FR or FR leading: negative pulses.
FV = FR and phase error within PDA window: high impedance.
An open drain lock detect output at low level when phase error is within PDA window
(in lock); high impedance at all other times.
The input to the main counters. It is normally driven from a prescaler which may be AC
coupled or, when a full logic swing is available, may be DC coupled.
Negative supply (ground).
Positive supply (normally 5V).
Not connected.
These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. Capacitors of an appropriate value are also required between
each end of the crystal and ground to provide the necessary additional phase shift. The
addition of a 220 ohm resistor between Pin 8 and the crystal will improve stability.
An external reference signal may alternatively be applied to OSC.IN. This may be a
low-level signal, AC coupled, or if a full logic swing is available it may be DC coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the division ratio
being twice that programmed.
Not connected.
Information on this input is transferred to the internal latches during the appropriate data
read time slot. Data is high for a '1' and low for a '0'. There are three data words which
control the NJ8824, MSB is first in the order, 'A' - (7 bits), 'M' - (10 bits), 'R' - (11 bits).
Data is clocked in on the negative transition of the clock waveform. If less than 28 negative
clock transitions have been received when the enable line goes low (i.e. only 'M' and 'A' will
have been clocked in) then the 'R' counter latch will remain unchanged and only 'M' and
'A' will be transferred from the input shift register to the counter latches.
This will protect the 'R' counterfrom being corrupted by any glitches on the clock line after
only 'M' and 'A' have been loaded.
If 28 negative transitions have been counted then the 'R' counter will be loaded with the
new data.
When the enable is low the data and clock inputs are disabled internally. As soon as the
enable is high the data and ciock input are enabled and data may be clocked into the
device. The data is transferred from the input shift register to the counter latches on the
negative transition of the enable input and both inputs to the phase detector are
synchronised to each other. Enable transitions only allowed when ClK is high.
This pin allows an external capacitor to be put in parallel with the ramp capacitor, and
allows further programming of the device. (This capacitor is connected from CAP to Vss).
Output for controlling an external dual modulus prescaler. The modulus control level will
be low at the beginning of a count cycle and will remain low until the 'A' counter completes
its cycle. The modulus control then goes high and remains high until the 'M' counter
completes its cycle at which point both counters are reset. This gives a total division ratio of
M.N + A where Nand N + 1 represent the dual modulus prescaler values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including -'- 128/129.
The programming range of the 'M' counter is 3-1023 and for correct program operation
M ;;, A. Where every possible channel is required, the minimum division ratio should be
N2 - N.
An external sample and hold phase comparator gain programming resistor should be
connected between this pin and Vss.
An external hold capacitor should be connected between this pin and Vss.

DP
1

MP
1

3
2

N/C
PDB

FIN

5
6
7,8

6
7
8
9,10

Vss
Voo
N/C
OSC.IN/
OSC.OUT

9
10

N/C
DATA

ClK

ENABLE

CAP

263

NJ8824,NJ8824B
2.0

1.I.

esc Jsv t

JDD

os6V /"

w
II:
II:

i
;l

FIN

~DD ==Isv

.I. J.

IN, FIN = OV TO SV SQUAREW~VE

O.s
---"Ill

.--

,/'

.......... V

V -F;;;

""'"

fo-""

~ ~ I".....

TOTAL SUPPLY CURRENT IS
THE SUM OF THAT DUE TO FIN
AND OSC IN.
I

.......

3
4
S
6
7
INPUT FREQUENCY (MHz)

1.0

lOW FREQUENCY
OV TO 5V SQUAREWAVE

------

10MHz
lMHz

Fig.3 Typical supply current v. input frequency
0.2

0.4

0.6
0.8
1.0
INPUT lEVEL (V ,ma)

1.2

1.4

1.6

Fig.4 Typical supply current v. input level, Dsc In

2 X fcomp
ie where fcomp = comparison frequency
fosc = oscillator frequency
R = R counter ratio
For example where crystal frequency = 10MHz and a
channel spacing comparison frequency of 12.5kHz is
required,
10 7
R= - - - - - = 4 0 0
2 X 12.5 X 103
Thus the R register would be programmed to 400 expressed
in binary.
NB The total divider range is from 6 to 4094 in steps of 2.

and A is the ratio of the A counter in the range 1 to 127.
NoteM ;;"A
AlsoP

tvco

+(comp
--

For example if the desired veo frequency = 275M Hz, the
comparison frequency is 12.5kHz and a two modulus
prescaler of +64/65 is being used, then:
275 X 106
P =
= 22 X 103
12.5 X 103
NowP = NM +A
which can be rearranged to be PIN = M + A/N
In our example we have
22 X 10 3
A
A
= M +-6 therefore 343.75 = M +64
64
M is programmed to the integer part = 343 and A is
programmed to the fractional part times 64
ie A = 0.75 X 64 = 48
NB The minimum ratio that can be used is N2 - N
To check P = 343 X 64 + 48 22000 which is the required
divide ratio.
When re-programming, the counters are changed only
when they reach a zero state. There is no reset to zero state.
This means the synthesiser loop lock up time will be variable.
For the case when only small changes in frequency are
required, the non-resettable synthesiser should achieve the
shortest loop lock up times.

VCO Divider Chain
The synthesised frequency of the voltage control oscillator
(VeO) will depend on the division ratio of the M and A
counters, the value of the external two modulus prescaler
(N//II + 1) and the value olthe comparison frequency fcomp.

The division ratio P
NM + A
where M is the ratio of the M counter in the range 3 to 1023

CLOCK

ENABLE _ _ _

~I·

_____

ICH

·L_-i- ·1 L

L*~--

DATA ___________________

tCl

,~~

~~~------------

Fig.5 Timing diagram showing timing periods required for correct operation

264

NJ8824,NJ8824B

(15) 26

ENABLE

(16) 27

(17) 28

____ JlSLJlS

CLOCK

--1

Fig.6 Timing diagram showing programming details

PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain
K"Kv/P, where K" is phase detector constant (volts/rad),
Kvis the VCO constant (rad-secs/volt) and P is the overall
loop division ratio. When P is large and the loop gain is low,
noise may be reduced by employing a phase comparator
with a high gain. The sample and hold phase detector, within
the NJ8824 has both a high gain and uses a double sampling
technique to reduce spurious outputs to a low level.
A standard digital phase/frequency detector driving a
three-state output provides a 'coarse' error signal to enable
fast switching between channels.
This output is active until the phase error is within the
sample and hold phase detector window, when its output
becomes high impedance. Phase-lock is indicated at this
point with a low level on LD. The sample and hold phase
detector provides a 'fine' error signal to give further phase
adjustment and to hold the loop in lock.
An internally generated ramp controlled by the digital
output from both the reference and main divider chains is
sampled at the reference frequency to give the fine error
signal, PDA. When in phase lock this output would typically
be at (VorrVss)/2 and any offset from this would be
proportional to phase error.

The relationship between this offset voltage and the phase
error is the phase-comparator gain which is programmable
with an external resistor, RB and a capacitor, CAP.
An internal SOpF capacitor is used in the sample and hold
comparator.
This gain is typically:
GAIN =0 10 [VorrVss-0.7-89(RB -''')]
2 1T [CAP + 50x10- 12 ] x RBxFR

The value of

RB and CAP should be chosen to give the required gain
at the reference frequency used. Fig.8 shows that to
achieve a gain of 380V per radian at 10kHz requires RB to
be approximately 39kO, CAP is zero. A hold capacitor
(CH) of non-critical value which might be typically 470pF
is connected from CH to Vss. A smaller value is sufficient
if the sideband performance required is not high.
The output from the sample/phase detector should be
combined with that of the coarse phase/frequency detector
and filtered to generate a single control voltage to drive the
VCO.

lM~---r---'----r---'----r----r---'----'

VT -

lOOk

1-\-Y-d----t----i---\--+--t--t-----1

Fig.7 Timing diagram showing voltage thresholds

PROGRAMMING/POWER UP
All data and signal input pins should have no input applied
to them prior to the application of Voo, as otherwise 'latch up'
may occur.

'"Fil

5kHz

400

10kHz

200

25kHz

I 800 I 1200 I 1600
1 400 I 600 I 800
I 160 I 240 I 320
K" IN VOL TS/RAD.

GAIN x FR PRODUCT mViRAD-SEC
(1) CAPext = OpF
(2) CAPext = 47pF
(3) CAPext = 0.8nF

Fig.S RB v. gain and reference frequency

265

PLESSEY

Semiconductors __________________

NJ88C25
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)

The NJ88C25 is a synthesiser circuit fabricated on the 2micron CMOS process and is capable of achieving high
sideband attenuation and low noise performance. The circuit
contains a reference oscillator, 11-bit programmable
reference divider, digital and sample-and-hold phase
comparators, 10-bit programmable 'M' counter, 7-bit
programmable 'A' counter, latched and buffered Band 0 and
Band 1 outputs and the necessary control and latch circuitry
for accepting and latching the input data.
Data is presented serially under external control from a
suitable microprocessor. Although thirty bits of data are
initially required to program all counters, subsequent
updating can be abbreviated to nineteen bits when only the
'A', 'M' and 'B' counters require changing.
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.

PDA [ 1

'-'

PDS [ 2

18
17

FV [ 3

PCH
PRS

16pUC

vss[ 6

PCAP
P
13 PCLOCK

voo[ 7

12p DATA

LD [4
FIN[

BANDU[8
OSC IN[ 9

NJ88C25

ENABLE

11PBANDI

10~ USC OUT

DG1B, DP1B, MPIB
Fig.1 Pin connections - top view

FEATURES

•

•••
•

3.0V to 5.0V Supply Range
Low Power Consumption
High Performance Sample and Hold Phase Detector
Serial Input with Fast Update Feature
> 20MHz Input Frequency

ABSOLUTE MAXIMUM RATINGS
Supply voltage (Voo - Vss)
-O.5V to 7V
I nput voltage
Open drain OIPs (pins 3 & 4)
7V
All other pins
Vss-O.3V to Voo +O.3V
Storage temperature
-65°C to +150°C

Eil41
I

LOCK DETECT
(LD)

'-------;94I
I

CONTROL LOGIC

VDDe_-L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

vss
Fig.2 Block Diagram

266

I
I MODULUS
CONTROL

I
J

OUTPUT
(MC)

NJ88C25
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Voo - Vss 2.7V to 5.5V, Temperature Range -30°C to

DC Characteristics at V DO

+70°C

= S.OV

Characteristic

Min.

Supply current

Value
Typ.

Max.

5.5
0.7
3.7

TBA
TBA
TBA

mA
mA
mA

FOSC, FIN
FOSC, FIN
FOSC, FIN

0.4

V
V

I source 1mA
Isink1mA

0.4
7

V
V

I sink 4mA

0.4
±0.1

V
V
pA

Conditions

Units

==
==
==

20M Hz ~ 0 to 5V
1MHz
square
10MHz wave

Modulus Control out,
BAND 0, BAND 1
High level
Low level

Voo-O.4

Lock Detect Out, FV
Low level
Open drain pull-up voltage

PDB output
High level
Low level
3-state leakage

4.6

I source 4mA
I sink 4mA

AC Characteristics
Value

Characteristic

Min.

FIN/OSC outputs
Max. operating freq. OSC/FIN inputs
Propagation delay, clock to
modulus control

Typ.

Units

Conditions

mVRMS
MHz
ns

20MHz AC coupled sinewave
Voo == 5V, 0 to 5V square wave
Note 2

tCH

ps
ps
ps

Max.

200
20
30

Programming inputs
Clock high time, tCH
Clock low time, tCl
Enable set-up time, tES
Enable hold time, tEH
Data set-up time, tos
Data hold time, tDH
Clock rise and fall times
Positive going threshold, Vr
Negative going threshold, VrDigital phase detector propagation
delay
Gain programming resistor, RB
Hold capacitor, CH
Programming capacitor, CAP
Output resistance, PDA

0.5
0.5
0.2
0.2
0.2
0.2
0.2
3

Note 5

2
500

ps
ps
ps
V
V
ns

TTL compatible

5
1
1
5

nF
nF

Note 3

NOTES
1. Data inputs have internal 'pull-up' resistors to enable them to be driven from TTL outputs.
2. All counters have outputs directly synchronous with their respective clock rising edges.
3. The finite output resistance of the internal voltage follower and 'on' resistance of sample switch driving this pin will add a finite time-constant to
the loop. A 1nF hold capacitor will give a maximum time constant of 5 microseconds.
4. The inputs to the device should be at logic '0' when power is applied if latch up conditions are to be avoided. This includes the signal/osc.
frequency inputs.
5. Clock to enable set up time is variable, dependent on frequency of OSC.IN. it needs to be specified in terms of OSC. IN frequency, clock high
time (tCH) and clock low time (tCI.). Enable set-up time, tES must meet following conditions: 4 x 1/0SC. IN"; tES «teH + tCl).

267

NJ88C25
PIN DESIGNATION
Pin No.

Name

Description

PDA

PDB

Three-state output from the phase/frequency detector for use as a 'coarse' error signal.
FV> FR or FV leading: positive pulses.
FV < FR or FR leading: negative pulses.
FV = FR and phase error within PDA window: high impedance.
This pin is an open drain output from the 'M' counter.

An open drain lock detect output at low level when phase error is within PDA window
(in lock); high impedance at all other times.

FIN

6
7

Vss
Voo

The input to the main counters. It is normally driven from a prescaler which may be AC
coupled or, when a full logic swing is available, may be DC coupled.
Negative supply (ground).

9,10

OSC.lN/
OSC.OUT

8,11

BAND 0/1

DATA

Information on this input is transferred to the internal latches during the appropriate data
read time slot. Data is high for a '1' and low for a '0'. There are four data words which control
the NJ88C25, MSB is first in the order, 'A' - (7 bits), 'M' - (10 bits), 'B' (2 bits) and 'R' (11 bits).

CLOCK

Data is clocked in on the negative transition of the clock waveform. If less than 30 negative
clock transitions have been received when the enable line goes low (ie only 'B', 'M' and 'A'
have been clocked in) then the 'R' counter latch will remain unchanged and only 'B', 'M' and
'A' will be transferred from the input shift register to the counter latches.
This will protect the 'R' counter from being corrupted by any glitches on the clock line after
only 'B', 'M' and 'A' have been loaded.
If 30 negative transitions have been counted then the 'R' counter will be loaded with the new
data.

ENABLE

CAP

When the enable is low the data and clock inputs are disabled internally. As soon as the
enable is high the data and clock inputs are enabled and data may be clocked into the device.
The data is transferred from the input shift register to the counter latches on the negative
transition of the enable input and both inputs to the phase detector are synchronised to each
other. Enable transitions are only allowed when ClK is high.
This pin allows an external capacitor to be put in parallel with the ramp capacitor, and
allows further programming of the device. (This capacitor is connected from CAP to Vss.)

Output for controlling an external dual modulus prescaler. The modulus control level will be
low at the beginning of a count cycle and will remain low until the 'A' counter completes its
cycle.The modulus control then goes high and remains high until the 'M' counter completes
its cycle at which point both counters are reset. This gives a total division ratio of M.N + A
where Nand N + 1 represent the dual modulus prescaler values.
The program range of the 'A' counter is 0-127 and therefore can control prescalers with a
division ratio up to and including ..;-128/129.
The programming range of the 'M' counter is 3-1023 and for correct program operation
M ? A. Where every possible channel isrequired, the minimum division ratio should beNLN.

An external sample and hold phase comparator gain programming resistor should be
connected between this pin and Vss.

An external hold capacitor should be connected between this pin and V ss.

268

Positive supply (normally 5V).
These pins form an on-chip reference oscillator when a parallel resonant crystal is
connected across them. CapaCitors of an appropriate value are also required between each
end of the crystal and ground to provide the necessary additional phase shift. The addition of
a 2200 resistor between Pin 8 and the crystal will improve stability.
An external reference signal may alternatively be applied to OSC.IN. This may be a low-level
signal, AC coupled, or if a full logic swing is available it may be DC coupled.
The program range of the reference counter is 3 to 2047 in steps of 1, with the division ratio
being twice that programmed.
Two latch outputs, providing an output of the data from the register 'B'.

NJ88C25
2.0

r---.--,---.--r---.-......--r--,.--..,-...,
VOO = 5V
OSCIN,FIN =OVT05VSQUAREWAVE

I I l.

"""-

I-

w
a:
a:
:::l 1.0

......

:::l

III

0.5'

to=L
FIN = LOW FREQUENCY OV 10 5VSQUAREWAVE

""'"

.......

4
INPUT FREQUENCY (MHz)

.......

~HZ

"'- ~

1MHZ","

"'......

Fig.3 Typical supply current versus input frequency
0.2

0.4

0.6
0.8
1.0
INPUT LEVEL (V nn5)

1.2

1.4

1.6

Fig.4 Typical supply current versus input level, Dsc In

PROGRAMMING

Reference Divider Chain
The comparison frequency depends upon the crystal
oscillator frequency and the division ratio of the R counter,
which can be programmed in the range 3 to 2047.
fosc
R=---2 X fcomp

ie where fcomp = comparison frequency
fosc = oscillator frequency
R = R counter ratio
For example where crystal frequency = 10MHz and a
channel spacing comparison frequency of 12.5kHz is
required,
R=

107
2 X 12.5 X 103

=400

Thus the R register would be programmed to 400 expressed
in binary.
NB The total divider range is from 6 to 4094 in steps of 2.

The division ratio P = NM + A
where M is the ratio of the M counter in the range 3 to 1023
and A is the ratio of the A counter in the range 1 to 127
Note M ;"A
fvco
AlsoP = - fcomp
For example if the desired veo frequency = 275M Hz, the
comparison frequency is 12.5kHz and a two modulus
prescaler of +64/65 is being used, then:

275 X 106

= 12.5

X 103

= 22

X 103

NowP =NM +A
which can be rearranged to be P/N = M + A/N
In our example we have

22 X 103
A
A
- - - =M +-therefore343.75 =M + 64
6
64
M is programmed to the integer part = 343 and A is
programmed to the fractional part times 64
ie A
0.75 X 64
48
NB The minimum ratio that can be used is N2 - N
To check P = 343 X 64 + 48 = 22000 which is the required
dividers ratio.

269

NJ88C25

CLOCK

tCH

ENABLE

I·

·L

tCl

tEH---j

tDH_

·1

t=L

~~=> IN VOLTS/RAD.

Fig.B RB versus gain and reference frequency

271

PLESSEY _____________________________________
Semiconductors
NJ88C30
VHF SYNTHESISER

The NJ88C30 contains all the logic needed for a VHF PLL
synthesiser and is fabricated on the Plessey high
performance small geometry CMOS. The circuit contains a
reference oscillator and divider, a two modulus prescaler and
4-bit control register, a 12-bit programmable divider, a phase
comparator and the necessary data input and control logic.

GROUND [ 1
DATA TRANSFER [ 2
CLOCK [

DATA [ 4

FEATURES

CRYSTAl MON [ 5

•

Low Power CMOS

•

Easy to Use

•
•

Low Cost
Single Chip Synthesiser to VHF

•

Lock Detect Output

'-./ 14 COMP FRED
13D.pup
12 ]it>ON
NJ88C30
11 ] LOCK DETECT
10 VCO

CRYSTAL IN [ 6

P DIV OUT

CRYSTAL OUT [ 7

Von

DP14
Fig.1 Pin connections (plastic OIL - top view)

APPLICATIONS
GROUND

•
•

Mobile Radios
Hand Held Portable Radios

•

Sonobuoys

.PUP

CLOCK

.pDN

DATA
CRYSTAL MON

ABSOLUTE MAXIMUM RATINGS

CRYSTAL IN

Voo
Voltage on any pin
Operating temperature
Storage temperature

CRci~~AL

(- -

-O.3V to +6V
-O.3V to Voo +O.3V
-30°C to +70°C
-55°C to +125°C

CRYSTAL
'--c.::--4--_-~
IN

VCO

-t

CRYSTAL OUT

VCO
P OIV OUT
Von

Fig.2 Pin connections (miniature plastic OIL - top view)

~YS~r~ MO~ ..!l;"~)~ND-~OM!f·:EQ----l

~OV

110

+1,5,10,20,2,4,8 OR 16

REF SELECT

~OV

VDD

I
I

~
I:::ii29

0~1

4> UP

iP"DN

~~~

!
~PDIVOUT
0;.11

ov'1-

I
I

:-:::::-:::-=-===----.. . . .--.
I
I
L_________________________ J

TRANSFER II L
DATA 0 4
CLOCK 13

_ _ _-.[r....J.----r

Fig.3 Functional block diagram

272

LOCK DET

MP14

DATA

COMP FREQ

DATA TRANSFER

NJ88C30
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb

= -30°C to

+70°C, Voo

Characteristic

= 5V ± 0.5V
Value

Min.

Units

Conditions

Typ.

Max.

1V rms VCO input at 200M Hz
and fXTAL = 10MHz

6,7

MHz

Vrms
V
V

Parallel resonant,
fundamental crystal
AC coupled
DC coupled
DC coupled

Supply
Supply current

Crystal oscillator
Frequency
External input level
High level
Low level

6
6
6

1
Voo-1

10
10
10

1
4

VCO input
VCO input sensitivity
Slew rate VCO input
VCO input impedance

At 200M Hz, see FigA

5pF/10kO

DATA, DATA TRANSFER,
CLOCK inputs
High level
Low level
Rise, fall time
Data set up time
Clock frequency
Transfer pulse width

V rms
V/f.1s

Voo-1
2,3,4
2,3,4
2,3
3,4
3
2

500

V
V
ns
ns
MHz
ns

0.8

VOUT = 0.5V

9,11,14

1.6

VOUT = 0.5V

12
13

0.8
0.8

mA
mA

VOUT = 0.5V
VOUT = Voo - 0.5V

1
200
200
2

See Fig.5

Crystal monitor output
Current sink

Comp freq, LOCK DET, P DIV
Current sink

¢> UP/¢> DN
Current sink
Current source

'Tested as specified
in table of
Electrical Characteristics

100

150

200

FREQUENCY (MHz)

Fig.4 Input sensitivity

273

NJ88C30

CLOCK

DATA

DR2

XI I

DRl

ORO

DF15

DATA
T R A N S F E R _ - - - + + -_ _ _

DFl

DFO

f _ 1n L -

--JL

~I_

DATA SET UP TIME

TRANSFER
PULSE WIDTH

Fig.5 Input data timing diagram

180

r-......

/".

t'....

'-....

r"'r-,

--f--

-10

lOOk

10M

lOOk

FREQUENCY (Hz)

1M
10M
FREQUENCY (Hz)

Fig.6 Gain phase characteristics of reference oscillator inverter

CIRCUIT DESCRIPTION
Crystal Oscillator and Reference Divider
The reference oscillator consists of a Pierce type oscillator
intended for use with parallel resonant fundamental crystals.
Typical gain and phase characteristics for the osci lIator
inverter are shown in Fig.6. An external reference oscillator
may be used by either capacitively coupling a 1V rms
sinewave into the CRYSTAL IN pin or if CMOS logic levels
are available by connecting directly to CRYSTAL IN pin.
The reference oscillator drives a divider to produce a range
of comparison frequencies which are selected by decoding
the first three bits (DR2, DR1, DRO) of the input data. The
possible division ratios and the comparison frequencies if a
10MHz crystal is used are shown in Fig.?
DR2 DR1 ORO Division Ratio
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1600
800
400
200
2000
1000
500
100

Comparison Frequency
for 10MHz Ref. Osc.
6.25kHz
12.5kHz
25kHz
50kHz
5kHz
10kHz
20kHz
100kHz

Fig.7 Reference divider division ratios

274

To assist in trimming the crystal, an open drain output at
one hundredth of the reference oscillator frequency is
provided on CRYSTAL MONITOR pin 1.

Programmable Divider
The programmable divider consits of a .;-15/16 two
modulus prescaler with a 4-bit control register followed by a
12-bit programmable divider. A 1V rms sinewave should be
capacitively coupled from the VCO to the divider input VCO
pin.
The overall division ratio is selected by a Single 16-bitword
(DF 15 to 0) loaded through the serial data bus. A lower limit
of 240 ensures correct prescaler operation; the upper limit is
65535. The VCO frequency in a locked system will be this
division ratio multiplied by the comparison frequency.

Phase Comparator
The phase comparator consists of ~ital type phase
comparator with open drain UP and DN outputs and an
open drain lock detect output. Open drain outputs from the
reference divider and programmable divider are provided for
monitoring purposes or for use with an external phase
comparator. Waveforms for all these outputs are shown in
Fig.8. The duty cycle of UP and DN versus phase
difference are shown in Fig.9. The phase comparator is linear
over a ±27T range and if the phase gains or slips by morethan
27T the phase comparator outputs repeat with a 27T period.

NJ88C30

(a) Phase P DIVoutput leads
phase COMP FREQ output

COMP FREQ

POlY

I I

4> UP

LOCK DET

(b) Phase P DIV output lags
phase COMP FREQ output

CDMP FREQ

POlY

4> UP

U
I

--~rlr--------~Il~------I
I
I
I

LOCK DET

U~------

Fig.B Phase comparator waveforms

DUTY CYCLE
4> UP

100"10

PHASE DIFFERENCE

DUTY CYCLE

4> ON

21T

PHASE DIFFERENCE

Fig.9 Phase comparator output characteristics

275

NJ88C30
Once the phase difference exceeds 21T the comparator will
gain or slip one cycle and then try to lock to the new zero
phase difference. Note very narrow pulses may be seen on
the inactive phase comparator output at the end of the pulse
on the active output.

values can be determined, given a required natural loop
bandwidth W n and damping factor 6, by the following
equations:
K , R2C,
26 and K
GKoVee
Wn
21TN

Data Input and Control Register

where

To control the synthesiser a simple three line serial input is
used with Data, Clock and Data Transfer signals. The data
consists of 19 bits, the first three DR2, DR1, DRO control the
reference divider, the next sixteen, DF1S to DFO, control the
prescaler and programmable divider. Until the synthesiser
receives the Data Transfer pulse it will use the previously
loaded data; on receiving the pulse it will switch rapidly to the
new data.

W
- natural loop bandwidth (rad/s)
6
- damping factor
Ko
- VCO gain factor (radNs)
Vee - charge pump supply voltage (V)
N
- division ratio = fouT/feoMP
G
- gain 01 amplifier

APPLICATIONS
A simplified circuit for a synthesiser intended for VHF
broadcast receiver applications is shown in Fig.10. When the
varicap line drive voltage necessary to tune the required
band is greater than SV, some form of level shifter such as the
operational amplifier shown in Fig.10 is required. Pulses
from the phase comparator are filtered by R1, R2ancl C 1. Their

The values in Fig. 10 were calculated for:
Wn
= 3000 rad/s
6
= 0.707
Ko
= 18 MradNs
Vee = SV
lOUT = 100MHz
feoMP = 50kHz
G
= 2

LOCK DETECT

DATA TRANSFER
CLOCK
DATA

+12V

,11 On
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

----~

+5V

Fig. 10 Typical application

Example of Programming
For a channel spacing (comparison frequency) of 5kHz
when using a crystal oscillator of 10MHz the reference
divider ratio will need to be 2000 (see Fig.7). This is
programmed as binary 100 in the mostsignificantthreeofthe
19 bits (MSB programmed first).

To obtain the maximum VCO frequency of 200M Hz the
programmable divider ratio would be:
200 x 106
5x1ii3

The complete program word would then be:

Binary
Hex

2
1 10
'1 1 0 10
4

15114113 112
1 1 0 1 0 11
9

11 110 19 18
1 1 1 10 1 0
C

Using the same crystal and 5kHz channel spacing the
minimum VCO frequency programmable would be 1.2MHz

3 12 11
0
o 10 10 1 0
0

276

7 16 15 14
o 11 1 0 1 0
4

with the division ratio of 240 (= FO Hex). The program word
would then be:

Binary
Hex

= 40 x 1Q3 w h'ICh'IS 9C40 Hex.

2 11
0
1 1 0 10
4

15114113 112
o 10 10 10
0

11 110 19 18
o 10 10 1 0
0

7 16 15 14
1 1 1 1 1 11
F

3 12 11
010 10
0

0
0

PLESSEY

Semiconductors ___________________

NJ88C31
MFNHF SYNTHESISER
The NJ88C31 contains all the logic needed for an MFNHF
PLL synthesiser and is fabricated on Plessey high
performance small geometry CMOS. The circuit contains a
reference oscillator and divider, a two modulus prescaler and
4-bit control register, a 12-bit programmable divider, a phase
comparator and the necessary data input and control logic,
and a 4.5MHz J..IP clock drive output.

\,.../

CLOCK OUT [ 1

CRYSTAL OUT [ 3
VDO [

14 ] DATA TRANSFER

NJ88C31 13] GROUND
12] MF VCD

ENABLE [ 5

FEATURES
•

Low Power CMOS

•

Easy To Use

•
•

Low Cost
Single Chip Synthesiser

•
•

Lock Detect Output
4.5MHzf.lP Clock Output

11 ] BAND

veo [

10] UP

LOCK DET [ 8

9] UP

DATA

APPLICATIONS

•

TEST [

VHF

•

16] DATA
15] DATA CLOCK

CRYSTAL IN [ 2

LOCK DEl

CLOCK OUT

AM/FM Radios

CRYSTAL IN

Car Radios

veo

VHF

CRYSTAL OUT

TEST

ENABLE

MP16
Fig.2 Pin connections (miniature plastic OIL - top view)

CRYSTAL
OUT

CLOCK OUT
VDD GROUND
1(5)---14'(8)-113(1)---------,

r---------

1
CR~~TAL~~~~~~-------------+----~ 790/180/450/500/900

COMP FREQ

'----r----'

VD~

,.---lL.----,

MODE/REF SELECT
VHF VC01 H'=="~

~ UP
~DN

o~ '1

'--"T""""'T'"-r,~ LOCK DET

~~~~~~
~----.---~

ov~

!
I

6(10)1 TEST

MF VC01 t-<>:=:;-;:,-t

11(15) BAND
DATA
TRANSFER 114(2)
DATA
116(4)

I
19 BIT SHIFT REGISTER

L _________________________

DATACLOCK?1!15~(3")-----~~---------------------J

1
~

Fig.3 Functional block diagram. Pin numbers for MP package are shown in brackets.

277

NJ88C31
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb

= -30°C to

+70°C, VDD

Characteristic

ABSOLUTE MAXIMUM RATINGS
VDD
Voltage on any pin
Operating temperature
Storage temperature

= 5V ± 0.5V

Pin
MP16

Pin
DP16

Supply
Supply current

Value
Min.

6,7

2,3

6
6
6

2
2
2

1
VDD-1

13
16
13,16

7
12
7,12

0.3
0.3

2,3.4
9,10
2,3.4,
9,10
2,3
3.4
3
2

5,6,
14,15,16
5,6,
14,15,16
14,15
15,16
15
14

VDD-1

5,15
5,15

LOCK DET
Current sink
UP/ ON, BAND
Current sink
Current source

External input level
High level
Low level

VCO inputs
VHF VCO input sensitivity
MF VCO input sensitivity
VCO input impedance
DATA, DATA TRANSFER,
DATA CLOCK, TEST and
ENABLE Inputs
High level
Low level
Rise, fall time
Data set up time
Clock frequency
Transfer pulse width

CLOCK OUT, BAND
Current sink
Current source

Units

Conditions

1V rms VHF VCO input at
120MHz and fXTAL = 4.5MHz
fXTAL = 4.5MHz,
Enable low

MHz

V rms
V
V

Parallel resonant,
fundamental crystal
AC coupled
DC coupled
DC coupled

V rms
V rms

At 50 to 125MHz, see FigA
At 0.1 to 2.5MHz

Typ.

Max.

Supply current
(Standby mode)

Crystal oscillator
Frequency

-0.3V to +6V
-0.3V to VDD +0.3V
-30°C to +70°C
-55°C to +125°C

4.5

5pF/10kn

V
1

200

500

ns
ns
MHz
ns

1,11
1,11

0.8
0.8

mA
mA

VOUT = 0.5V
VOUT = VDD-0.5V

1.6

VOUT = 0.5V

13
14

9
10

0.8
0.8

mA
mA

VOUT = 0.5V
VOUT = VDD-0.5V

200
2

See Fig.5

CIRCUIT DESCRIPTION
1.6

I
~

I!:
F!
~

i!
~

Crystal Oscillator and Reference Divider

* Tested as

1.4

specified in
Table of
Electrical
Characteristics

1.2
1.0
0.8
0.6
0.4
0.2

TYPICAL

100

150

FREQUENCY (MHz)

FigA Input sensitivity of VHF

278

200

veo

250

The reference oscillator consists of a Pierce type oscillator
intended for use with parallel resonant fundamental crystals.
Typical gain and phase characteristics for the oscillator
inverter are shown in Fig.6. An external reference oscillator
may be used by either capacitively coupling a 1V rms
sinewave into the CRYSTAL IN pin or if CMOS logic levels
are available by connecting directly to the CRYSTAL IN pin.
The reference oscillator drives a divider to produce a range
of comparison frequencies which are selected by decoding
the first three bits (DR2, DR1, ORO) of the input data. The
possible division ratios and the comparison frequencies if a
4.5MHz crystal is used are shown in Fig.7.
There is a 4.5MHz J.lP clock drive output available on the
CRYSTAL OUT pin.

NJ88C31

DATA CLOCK

DATA

DR2

XII I

DR1

DRO

X,-_DF_1_5

_-t::...._ X

DATA

_ - - - - - - - - - -I
I

T R A N s F E R - - - - - - . - +-i

DF_1____

DFO

------..,;.1 L
n

DATA SET UP TIME

TRANSFER
PULSE WIDTH

Fig.5 Input data timing diagram
180

I'-..

i'-.

ffiw

120 -

f--

t'-.....

a;
Cl

1"\

"'-

.........

~ 60

-10

100k

10M

100k

FREQUENCY (Hz)

1M
10M
FREQUENCY (Hz)

Fig.6 Gain phase characteristics of reference oscillator inverter

BAND Output
The programming bit DR2 is brought out as a BAND
output, '1' for MF band and '0' for VHF.
DR2 DR1 ORO

Division Comparison Frequency
4.5MHzXTAL
Ratio

0
0
0

0
0
1

0
1
0

90
1BO
450

50kHz
25kHz
10kHz

1
1
1

0
0
1

0
1
0

450
500
900

10kHz
9kHz
5kHz

B
A

v
H

Fig.7 Reference divider division ratios

Programmable Divider
The programmable divider consists of a 12-bit divider
preceded on FM by a divide by 15/16 two modulus divider.
The FIM input is fed through an amplifier to provide
adequate sensitivity.

Phase Comparator
The digital phase comparator has three open drain
outputs; ell UP and ell DN drive the charge pump and LOCK
DETECT may be integrated to generate a MUTE signal.
Waveforms for all these outputs are shown in Fig.B. The duty
cycle of ell UP and ell DN versus phase difference are shown in
Fig.9. The phase comparator is linear overa±217" range and if
the phase gains or slips by more than 217" the phase
comparator outputs repeat with a 217" period. Once the phase
difference exceeds 217" the comparator will gain or slip one
cycle and then try to lock to the new zero phase difference.
Note very narrow pulses may be seen on the inactive phase
comparator output at the end of the pulse on the active
output.
ENABLE Input
When ENABLE is taken to logic '0' both VCO input buffers
and the prescaler are switched off to save power. The crystal
oscillator, CLOCK OUT and control registers continue
working normally, such that when ENABLE is taken to a '1'
the device will retune the last programmed frequency.

TEST Input
When the TEST pin is taken to a logic 1, the ell UP pin is
connected to the output of the reference chain divider
(CaMP FREQ) and the ell DN pin is connected to the output
of the 12-bit programmable signal chain divider (PROG DIV);
this mode is normally only used in factory testing.

279

NJ88C31

(a) Phase P DIV output leads
phase of COMP FREQ output

L-

COMP FREO

PDIV

--U

I
I

<1> UP

<1> ON

LOCK DET

U
I

(b) Phase P DIV output lags
phase of COMP FREQ output

COMP FREO

P DlV

I
I
U

<1> ON

LOCK DET

I
I
U

Fig.8 Phase comparator waveforms

DUTY CYCLE
<1> UP

100%

PHASE DIFFERENCE

DUTY CYCLE
DN

0%
PHASE DIFFERENCE

·2"

Fig.9 Phase comparator output characteristics

280

NJ88C31
Data Input and Control Register
To control the synthesiser a simple three line serial input is
used with Data, Clock and Data Transfer signals. The data
consists of 19 bits, the first three DR2, DR1, DRO control the
reference divider, the next sixteen. DF1S to DFO, control the
prescaler and programmable divider. Until the synthesiser
receives the Data Transfer pulse it will use the previously
loaded data; on receiving the pulse it will switch rapidly to the
new data. See Fig.S.

APPLICATIONS
A simplified circuit for a synthesiser intended for VHF
broadcast receiver applications is shown in Fig.1 O. When the
varicap line drive voltage necessary to tune the required
band is greater than SV, some form of level shifter such asthe
operational amplifier shown in Fig.10 is required.Pulses from
the phase comparator are filtered by R1, R2, and C,. Their
values can be determined. given a required natural loop
bandwidth Wn and damping factor {j, by the following
equations:

~ and K =

Ko x Vee x G
27TN

where
W

natural loop bandwidth (rad/s)
damping factor

- VCO gain factor (radNs)

Vee
N
G

- charge pump supply voltage (V)
- division ratio = fouT/feoMP
- Gain of amplifier

The values in Fig.10 were calculated for:

= 3000 rad/s
= 0.707

=
=
=
=
=

Vee
fOUT
feoMP
G

18 MradNs
SV
100MHz
2SkHz
2
+12V

~5V~~---+--~~--n

22k

Fig.10 Typical application for DP16 device

Example of Programming
VHF section
For a channel spacing (comparison frequency) of 10kHz
when using a crystal oscillator of 4.SMHz, the reference
divider ratio will need to be 4S0 (see Fig.7). This is
programmed as binary 010 in the most Significant three bits
of the 19 bit data word (MSB programmed first).

To obtain a VCO frequency of 12SMHz the programmable
divider ratio would be:
12Sx 106
10 x 103 = 12S00 = 30D4 Hex.
The programming word would be:

DR
Bit No.
Binary
Hex

21110
1 I0
2

1s114113112 11 110 9 1 8
o I 0 I 1 I 1 010 101 0
0
3

MF section
The four least significant bits of DF are not used in
programming the programmable divider ratio, but
nevertheless a total of 19 bits must be supplied.
For a channel spacing of SkHz when using a crystal
oscillator of 4.SMHz, the reference divider ratio will be 900
(see Fig.7). This is programmed as 110 in the most significant

2 11 10
1 1 1 10
6

I4
I

11 1 0

o I1 I0 I0
4

bits of the 19 bit word (MSB is programmed first).
To obtain a frequency of 2.SMHz the programmable
divider ratio would need to be 500. The value programmed
into the DP register must be the desired ratio minus one, i.e.
in this case 499 which is 1F3 Hex.
The programming word would be:

DR
Bit No.
Binary
Hex

7 16 1S
1 I 1 I 0
D

OF
1s114113 112 111101918
o 1 0 1 0 1 1 1111111
F
1

7 16 l s i 4
01°1 1 L1
3

I2 11

XLXIX1X
DON'T CARE

281

PLESSEY
Semiconductors ___________________
This information is for sample evaluation only. Final specification will tak.e account of mark.et demands.

SP2001
DIRECT DIGITAL SYNTHESISER WITH 100MHz OUTPUT

The SP2001 Direct Digital Frequency Synthesiser
(DDFS) is an ECl lOOK compatible 'numerically controlled
oscillator' i.e. it directly generates the DAC code required
for an output sinewave anywhere within the output range
5kHz to 100 MHz. A block diagram of the full synthesiser
is included in Fig 2.

Ne (DO NOT USE)

Ne ( DO NOT USE)

FSI13

FSI14

FSI12

FSI15 MSB

VEEI·5.2V)

VEE

FEATURES
• Maximum Clock Frequency > 350MHz
• 16-Bit Resolution
.8-Bit Parallel Cosine Output
• ECl 100K Compatible Inputs and Outputs
.40-lead Sidebrazed Ceramic Oil Package
• Maximum Output Frequency > 100MHz
• Useable with 5, 10, 15 or 30kHz Channel Spacing
• Useable with 3.125, 6.25, 12.5 or 25kHz Channel
Spacing
• Asynchronous Data load for Fast (17ns) Hop Time
• low Power: 1.85W
.Very low Close-to-Carrier Noise,-135dBc/Hz

FSI11

ROM DiP 7 (MSS)

FSl10

FSI8

SP2001

CLOCK INPUT

ROM Q/P 3

ROM OIP 2

FSI6

ROM O/P 1

ROM OIP 0
Ne

OUTPUT GND

FSI4

FSI

ROM QIP4

FSI7

FSI3

GND(OV)

GND (OV)

·2V VDD

FSI2

FSl1

• local Oscillator Transmitter Synthesis in VHF low
Band (30 - 100MHz)
• LO Synthesis in Frequency Agile Radio/Radar
• Wide Single - Range Sinewave Generator
• ECM/ECCM - e.g Follower Jammers or Fast
Hoppers

FSI5

APPLICATIONS

ROM OlP6
ROM Q/P 5

FSI9

SET INPUT
21

FSIO

= Frequency Select Input
Fig. 1 Pin connections - top view

~-----------------------,
I
SP2001 I
I
MSB
I
I
I
ROM
I
DAC
LOOK
UP
I
ADDRESS
FREQUENCV{
TABLE
H:>--t SP9768
INVERTER
SET
180· COSINE

--------------------~

f CLOCK
(=327 MHz)

Fig.2 Direct Digital Synthesiser Block. Diagram

282

DC40

OIP

SP2001
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated)
VEE = -5.2V, Vcc = GND, Voo = -2.0V, Toase

= -10°C to

+ 85°C

Value
Characteristic

Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output lOW voltage
lEE supply current
100 supply current

Conditions

Units
Min.
-1125
-1810
-1025
-1810

Typ.

-955
-1705
310
125

Max.
-880
-1520
-880
-1620

mV
mV
mV
mV
mA
mA

loaded with 50n to -2V
loaded with 50n to -2V

ABSOLUTE MAXIMUM RATINGS
Storage temperature
Max. junction temperature
Case temperature in operation
Max. voltage between VEE & Vcc
Input voltage (DC)
Output current at Va
VOH
ECl termination supply

-65°C to + 150°C
+150°C
-55°C to + 150°C
-7.0V to + 0.5V
VEE to (Vcc +0.5)V
-20mA
-1.75V to -2.25V

CIRCUIT DESCRIPTION
The SP2001 is a digital direct frequency synthesisel
with an output frequency of 5Khz to 100 MHz, in a single
range. at 5kHz channel spacing. Alternative clock
frequencies will lead to different channel spacing. The
circuit needs no reactive components at all (except power
supply decoupling capacitors) and is under full digital
control at all times. including during the phase-coherent
frequency transitions. Frequency accuracy is set by an
external clock oscillator; close-to-carrier noise levels on
the synthesiser output are dominated by the clock
performance.
The fully digital system does not contain control loops,
so thai 'hop' lime between discrete output frequencies is
limited in principle only by the digital to analog converter
settling time of about 5ns. In practice. to simplify the logic,
a further four clock periods of delay have been added; the
resultant total of 17ns worst case is about five orders of
magnitude faster than loop synthesisers. The block diagram
(Fig.2) shows a full DDFS. including the recommended
Plessey SP9768 Digital to Analog Converter.
The function of the blocks can be seen from Fig.2. To
avoid the need for storage of a full 360 degrees in the
ROM, the MSB output of the accumulator is used as a sign
inverter. which with the lSBs, forms a digitised triangular
number sequence. The ROM contains the data for 180
degrees. stored in a cosine sequence in this instance. ROM
size is 1K bit (128 x 8 bits) and with the reflection about
zero implicit in the 180° storage, this is equivalent 10 256
words of data i.e. the storage density is equal to the word
length.
The data passes through retiming latches at each stage
including the output in order to provide accurate data at the
high clock rate; pipeline delays are unimportant in a nonlooped system.
Finally, the DAC constructs the output waveform. which
conSists of discrete points on the sinusoid. Interpolation
could be carried out by low-pass filtering; in practice. no
filters were used except the inherent low-pass action of
the DAC.

Performance of the system is to some extent limited by
the maximum update rate of the DAC used. The
recommended SP9768 will typically update to ± i lSB at
over 200M Hz. When the clock is running at 327.68MHz. the
DAC achieves 5-6 bits accuracy but is otherwise
unimpaired in operation. When the output is 100MHz. a
spurious rejection of 32dBc is obtained. The largest spurs
are at (327.68-3 x 100)MHz and (4 x tOO-327- 68)
MHz. At 10MHz output. using the same programme code.
wilh 32.768MHz clock, the largest spur is at -38dBc,
although this IS a frequency which would be removed by
low pass filtering. The true spur level is -46dBc. close to
the theoretical limit for an 8-bit system. Close-Io-carrier
noise is very good and IS dominated by the clock source;
separate measurements indicale a noise floor of better than
-135dBc·Hz at ±25kHz.
Measurement of close-to-carrier spurs involves the
use of an extremely wide dynamic range receiver. This was
achieved by using a Hewlett-Packard 3047A!11740A
Microwave Phase" Noise Measurement System, with a
signal generator type HP8662A. Measurements are of
course channel specific; the 'cleanest' channels occur
when the channel selected is a whole binary number such
as 00010000 0000 0000. Channels close to this, e.g. one
channel away. contain small close-Io-carrier components
generally at a spacing dependent on the ratio between the
output frequency and the clock. Typically, at fOUT= fCLOCK/4.
and f INCREMENT = 5kHz, the spurs are at ± 20kHz.
The 'SET' input (pin 22) provides a 'start from zero' as a
test facility. It sets all accumulator latches to zero so that
the output is the ROM zeros state.
The frequency equation is:
fOUT

f CLOCK

Input Data

2 '6
e.g. For 5kHz increments, fCLOCK = 327.68MHz.
For 3.125kHz increments, fCLOCK = 204.8Hz.

TIMING
The channel selection data is parallel asynchronously
loaded so timing is uncritical. Internal latching of the device
pipelines the data, so there is a through delay of 4 clock
periods plus 400ps from change of input data. Minimum
channel re-selection time is therefore approximately 12ns
plus DAC settling time. In a worst case, one further clock
period should be allowed.

283

PLESSEY

Semiconductors ___________________

SP8850
1.5GHz PROFESSIONAL SYNTHESISER
The SP8850 is a low power single chip synthesiser
intended for professional radio communications containing
all the elements (apart from the loop amplifier) to fabricate a
PLL frequency synthesis loop.
The device is serially programmable by a three wire data
highway and contains three independent buffers to store one
reference divider word and two local oscillator divider words.
Analog and digital phase comparators are provided and
both gain and output phase are programmable via the divider
buffers. The preset tandem operation of the phase detectors
can be overwritten or the comparison frequencies switched
to output ports under control of the divider word. The dual
modulus ratio and therefore operation range is also
programmable through the same word.
A power down mode is incorporated as a battery economy
feature.

FEATURES

••
••
••
•
•

•
•
•
•

Low Operating Power, Typically 125mW
1.5GHz Operating Frequency
Complete Phase Locked Loop
High Input Sensitivity
Programmed through Three Wire Data Bus
Wide Range of Reference Division Ratios
Wide range of Local Oscillator Division Ratios
Local Storage for Two Frequency Words giving
Rapid Frequency Toggling
Integrated Analog and Digital Phase Detectors
Programmable Phase Detector Gain
Power Down Mode
ESD Protection on all Pins

ASBOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature
Operating temperature
Prescaler input voltage

284

-O.3V to 7V
-55°C to +150°C
-55°C to +125°C
2.5V p-p

Pin out
Vcc1,
Vcc2,
Vcc3,
Vcc4,

VEE1
VEE2
VEE3
VEE4

ECL Supplies
Oscillator Supplies
Analog Detector Supplies
Preamp and 16/17

OG28
Fig.1 Pin connections - top view

SP88S0

1----------------------------,
I
111

I
I
I

DUAL Fl/F2

~]~UF:R

I
I
I

_____ l

I
3 1DIGITAL
ERROR
SIGNAL

L...,-.,..---I 24

~---r.RSH

281

CSH

11 ANALOG
ERROR
I SIGNAL

LOCK

I DETECT

51 Fref
OUTPUT
INTERFACE

I
I

L ____

LOGIC

______________________ J

CRYSTAL

Fig.2 SP8850 block diagram

DATA~

\'----_/

CLOCK~n
I. J
Is

nl.---_----1.1

'"--I,-ep

I,ep ~ 11ls
Is ~ 10ns
I, ~ 10ns

Fig.3 Clock and data timing requirements

285

SP88S0
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tomb = -55°C to +125°C, Vee = +4.75V to +5.25V

Characteristic

Value
Min.

Supply current
I nput sensitivity

80MHz
150MHz
0.9GHz
1GHz
1.5GHz

Input overload

Comparison frequency
Reference oscillator
Reference division ratio
Data clock repetition rate trep
Minimum set up time ts
Minimum release time tr

F1/F2 input

Units

17.5
10
10
17.5
50

mVrms
mVrms
mVrms
mVrms
mVrms
Ohms
pF

240
56

524303
262151

4
2

2.5
20
8192
1

With 16/17 selected
With 8/9 selected
MHz
MHz

10
10

High
Low

0.5 Vee

High
Low

0.5 Vee

High
Low

0.5Vee

Conditions

mV rms
50
2

RF input division ratio

Data enable

Max.

300

Input impedance

Data input

Typ.

/.lS

ns
ns
0.3 Vee

V
V

0.3 Vee

V
V

0.3 Vee

V
V

F1 buffer selected
F2 buffer selected

DESCRIPTION
The programmable divider chain is of AM counter
construction and therefore contains a dual modulus front
end prescaler, an A counter which controls the dual modulus
ratio and an M counter which performs the bulk multimodulus division. A programmable divider of this
construction has a division ratio of MN + A and a minimum
integer steppable division ratio of N(N - 1).
In the SP8850 the dual modulus front end prescaler is a
dual N ratio device capable of being statically switched
between 16/17 and 819 ratios. The contrOlling A counter is of
four bit design enabling a maximum count sequence of 15,
(24- 1) which begins with the start olthe M counter sequence
and stops when it has counted by the preloaded number of
cycles. Whilst the A counter is counting the dual modulus
prescaler is held in the N + 1 mode, then relaxes back to the
N mode at the completion of the A sequence. The M counter
is a 15-bit asynchronous divider which counts with a ratio set
by a control word. In both A and M counters the contrOlling
data from the F1/F2 buffer is loaded in sequence with every
M count cycle. The N ratio of the dual modulus prescaler is
selected by a one bit word in the reference divider buffer and,
when a ratio of 8/9 is selected the A counter is automatically
switched to three bits, having an impact on the frequency bit
allocation as described in the data entry section.

Reference Source
The reference source in the SP8850 is obtained from an on
board oscillator, frequency controlled by an external crystal.
The oscillator can also function as a buffer amplifier allowing
the use of an external reference source. In this mode the

286

source is simply AC coupled into the oscillator.
The oscillator output is coupled to a programmable
reference divider whose output is the reference source for
the phase detector. The reference divider is a fully
programmable 13-bit asynchronous design and can be set to
any division ratio between 2 and 8192. The actual division
ratio is controlled by a data word stored in the internal
reference data buffer.

Phase Comparator
In order to improve performance in phase locked and
unlocked conditions, the SP8850 is provided with both digital
and analog phase comparators. The digital comparator is
sensitive to both frequency and phase errors over a wide
linear range and is designed to rapidly bring the loop close to
phase lock. The analog sample and hold comparator brings
the loop into final phase lock and holds it in this condition
with minimum sideband generation. In normal operation the
digital phase comparator is automatically disabled when the
loop phase error is within the linear range of the analog
comparator.
The automatic switching from digital to analog
comparators may be overwritten by an internal two bit
control word, stored in the reference divider buffer. Using
this word, the loop can be switched to internal digital control
only or both can be disabled and the local oscillator and
reference divider signals switched to output pins allowing
use of an external phase detector.
There are three further control bits associated with the
phase detectors which are stored in the F1/F2 buffer. The

SP8850
first bit controls the sense of the phase detector, allowing for
inversions of control direction in the external loop. The other
two bits are an internal gain control for the phase detectors
allowing compensation for local oscillator control slope
changes over the band, so maintaining close to optimum
loop parameters (see Table 1).
MSB

LSB

Digital

Analog

0
0
1
1

0
1
0
1

50/lA
75/lA
125/lA
200/lA

1
1.5
2.5
4

Output for RF phase lag
Sense bit

Current source
Current sink

0
1

Data Entry and Storage
The data section of the SP8850 consists of a data input
interface, an internal data shift register and three internal
data buffers.
Data is entered to the data input interface by a three wire
data highway with data, clock and chip enable inputs. The
input interface then routes this data to a 24-bit shift register
with bus connections to three data buffers. Data entered via
the serial bus is transferred to the appropriate data buffer on
the negative transition of the chip enable input according to
the two final data bits as shown in Table 2.
The dual F1/F2 buffer can receive two 22-bit words and
controls the programmable divider A and M counters using
19-bits, the phase detector gain with two bits and the phase
detector sense with one bit. A fourth input from the
synthesiser control system selects the active buffer.

+ve
-ve

The third buffer contains only 16 bits, 13 being used to set
the reference counter division ratio, and 2 to control the
phase comparator enable logic. The remaining bit sets the
dual modulus prescaler N ratio.
2 Bit S.R. Contents

B ulfer Loaded

00
01
10
11

F1
F2
ACTIVE A *
REFERENCE

Table 1
Note: Digital is charge pump current, Analog is multiplication
factor of externally set gain.

The unit gain of the digital detector is controlled by the
integration capaCitor in the loop amplifier. The analog gain is
set by an external resistor R and the hold time constant by the
external capacitor C. In operation the two detectors will be
summed into the loop amplifier and the ratio of the two gains
set by the series resistance in the analog detector output. See
the application circuit diagram.
A lock detect circuit gives an output when the analog
phase comparator is within the linear range of operation.

Digital detector Analog detector

Table 2

* Transfer of A counter bits into buffer controlling the
programmable counter.

The data words may be entered in any individual or
multiple sequence and the shift register can be updated
whilst the data buffers retain control of the synthesiser with
the previously loaded data. This enables four unique data
words to be stored in the device, with three in the data buffers
and a fourth in the shift register, whilst the chip is enabled. F1
word may also be updated whilst F2 is controlling the
programmable divider and vice versa.
The dual F1/F2 buffer enables the device to be toggled
between two frequencies using the F1/F2 select input at a
rate determined by the comparison frequency and also
enables random frequency hopping at a rate determined by a
byte load period, since the loop can be locked to F1 whilst F2
is updated by entering new data via the shift register.
An F1 or F2 update cycle will consist of a byte containing
24 bits, whereas the reference byte will contain 18 bits. The
device requires 3 bytes, each with a chip select sequence,
totalling 66 bits to fully program.
When the dual modulus counter (A count) is set to +8/9,
the data required to set the counter is reduced by one bit,
leaving a redundant bit in the 22-bit F1/F2 buffer. Various
programming sequences are shown in Fig.5.

CONTROL MICROPROCESSOR

* See Table 1 for digital phase comparator
charge pump current.
+5V

FigA Typical application diagram

287

SP8850

CONTROL
LOGIC

I
PHASE
DETECTOR
SENSE

15 BIT PROGRAMMABLE COUNTER
(M COUNTER)

4 BIT
PROGRAMMABLE
COUNTER
(A COUNTER)

Fig.S(a) FI or F2 word. bit allocation with 16117 selected

PHASE
DETECTOR
SENSE

15 BIT PROGRAMMABLE COUNTER
(M COUNTER)

3 BIT
PROGRAMMABLE
COUNTER
(A COUNTER)

Fig.S(b) FI or F2 word, bit allocation with 819 selected
DUAL
MODULUS
NRATIO
SELECT
MSB

PHASE

DB~~~ra~:

I I

LSB

1212k1koI291~1271~125124123122121 120 1

I I

13 BIT PROGRAMMABLE COUNTER

iCONTROL
LOGIC

CONTROL

Fig.S( c) Reference word bit allocation

DATA

DATA
CLOCK

REF WORD

F2WORD

F1 WORD
22 BITS

10101

22 CLOCKS

Irul

I 22 CLOCKS I

rul

DATA LOADS ON NEGATIVE EDGE

CHIP
SELECT

---L

---I

Fig.S(d} Typical data load sequence
Fig.S Data format diagrams

288

Application
Notes

289

290

Phase Noise Intermodulation and Dynamic Range _ _
The radio receiver operates In a non-benign environment. It needs to pick out a very weak wanted signal from a background of
noise at the same time a81t rejects a large number of much stronger unwanted signals. These may be present either fortuitously,
as In the case of the overcrowded radio spectrum, or because of deliberate action, as In the case of Electronic Warfare. In either
case, the use of suitable devices may considerably Influence the Job of the equipment designer.
Dynamic range Is a 'catch all' term, applied to limitations of Intermodulatlon or phase noise: It has many definitions depending
upon the appllcetlon. Firstly, however, It Is advisable to define those terms which limit the dynamic range of a receiver.

INTERMODULATION
This is described as the 'result of a non linear transfer
characteristic'. The mathematics have been exhaustively
treated, and Ref.1 is recommended to those interested.
The effects of Intermodulation are similar to those
produced by mixing and harmonic production, insofar as the
application of two Signals of frequencies f1 and f2 produce
outputs of 212 - f1, 2f1 - 12, 2f1, 2f2 etc. The levels of these

signals are dependent upon the actual transfer function of
the device and thus vary with device type. For example, a
truly square law device, such as a perfect FET, produces no
third order products (2f2 - f1, 2f1 - 12). Intermodulation
products are additional to the harmonics 2f1, 2f2, 3f1, 3f2etc.
Fig.1 shows intermodulation products diagrammatically.

I
Frequency

.211

212

Fig.1 Intermodulation products

The effects of intermodulation are to produce unwanted
signals, and these degrade the effective Signal to noise ratio
of the wanted signal. Consider firstly the discrete case of a
weak wanted signal on 7.010MHz and two large unwanted
signals on 7.020 and 7.030MHz. A third order product (2 x
7.02 - 7.03) falls on the wanted signal, and may completely
drown it out. Fig.2 shows the total HF spectrum from 1.5 to
41.5MHz and Fig.3 shows the integrated power at the front
end of a receiver tuned to 7MHz. It may be seen that just as
white light is made up from all the colours of the spectrum, so

the total power produced by so many signals approximates
to a large wide band noise signal. Now, it has already been
shown that two signals, f1 and 12, produce third order
intermodulation products of 2f1 - f2 and 2f2- f1. The signals
will produce third order products somewhat greater in
number, viz: 2f1- f2, 2f1- Is, 212- f1, 2f2- f3, 213- f,and 2f3- f2.
An increase in the number of input signals will multiply
greatly the effects of intermodulation, and will manifest as a
rise in the noise floor of the receiver.

REF-~IBm'r--'---r--r--r--'--.--'--'---r--'

41.OMHz

Fig.2

6.5MHz

Fig.3

291

The amplitude relationships of the third order
intermodulation products and the fundamental tones may be
derived from Ref.1, where it is shown that the
intermodulation product amplitude is proportional to the
cube of the input signal level. Thus an increase of 3dB in

input level will produce an increase of 9dB in the levels of the
intermodulation products. Fig.4 shows this in graphic form,
and the point where the graphs of fundamental power and
intermodulation power cross is the Third Order Intercept
Point.

THIRD ORDER
INTERCEPT POINT

""
Input Power dBm

Fig.4 3rd order intercept

The third order intercept point is, however, a purely
theoretical concept. This is because the worst possible
intermodulation ratio is 13dB (Ref.2), so that in fact the two
graphs never cross. In addition, the finite output power
capability of the device leads to Gain Compression.
Thus, it is apparent that the intermodulation produced
noise floor in a receiver is related to the intercept pOint.
Figs.S, 6 and ? show the noise floor produced by various
intercept pOints, in a receiver fed from an antenna - a realistic
test! Fig.S shows that a large number of Signals are below the
noise floor and are thus lost; this represents aOdBm intercept
point. Fig.? shows a +20dBm intercept noise floor, and it is
obvious that many more Signals may be received.

INPUT INTERCEPT +10dBm

REF -2OdBm

1OdB/DIV

A
l

" A

11.\

rill

WJ \

DL-95dBm

VI'

'11

I'\J

]
7.1MHz

7.0MHz

Fig.6
INPUT INTERCEPT OdBm

REF -20dBm

INPUT INTERCEPT +20dBm

REF-2OdBM

1OdB/DIV

10dB/DIV

I A

DL -7SdBm

hi L

IYf

'~IJ U.~

If r

I,'

tM.

Wlr~

LlI

'ltJln

l
VI~

f.I

~L 111l! '\

"I ".It

•

,LJ Ii

lr I'll. I~U Vl
".-1 '1"1 "J
I"

DL -11SdBm
7.1MHz

7.0MHz

Fig.5

292

7.0MHz

7.1 MHz

Fig.7

Because of the rate at which intermodulation products
increase with input level (3dB on the intermodulation
products for 1dB on the fundamental), the addition of an
attenuator at the front end can improve the signal to noise
ratio, as an increase in attenuation of 3dB will reduce the
wanted signal by 3dB, but the intermodulation will decrease
by 9dB. However, it is a fair comment that aerial attenuators
are an admission of defeat, as suitable design does not
require them!
The concept of dynamic range is often used when
discussing intermodulation. Fig.8 shows total receiver
dynamic range, which is defined as the spurious Free
Dynamic Range. Obviously an intermodulation product
lying below the receiver noise floor may be ignored. Thus the
usable dynamic range is that input range between the noise
floor and the input level atwhich the intermodulation product
reaches the noise floor. In fact

DR = 3(13- NF)

... (1)

Where DR is the dynamic range in dB
/3 is the intermodulation input intercept point in dBm
NF is the noise floor in dBm.
Note that in any particular receiver, the noise floor is
related to the bandwidth; dynamic range is similarly so
related.

VHF receivers require noise figures of 1 or 2dB for most
critical applications, and where co-sited transmitters are
concerned, signals at OdBm or more are not uncommon.
However, such signals are usually separated by at least 5 % in
frequency and filters can be provided. Close-in signals at
levels of -20dBm are not uncommon, and dynamic ranges in
SSB bandwidths of about 98dB are required.
The achievement of high input intercept points and low
noise factors is not necessarily easy. The usual superhet
architecture follows the mixer with some sort of filter,
frequently a crystal filter, and the performance of this filter
may well limit the performance. Crystal filters are not the
linear reciprocal two-port networks that theory suggests,
being neither linear nor reciprocal. It has been suggested
that the IMD is produced by ferrite cored transformers, but
experiments have shown that ladder filters with no
transformers suffer similarly. Thus, although ferrite cored
transformers can contribute, other mechanisms dominate in
these components. The most probable is the failure of the
piezo-electric material to follow Hooke's Law at high input
levels, and possibly the use of crystal cuts other than AT
could help insofar as the relative· mechanical crystal
distortion is reduced. The use of SAW filters is attractive,
since they are not bulk wave devices and do not suffer to
such an extent from IMD; however, it is necessary to use a
resonant SAW filter to achieve the necessary bandwidths
and low insertion losses.
The design of active components such as amplifiers is
relatively straightforward. Amplifiers of low noise and high
dynamic range are fairly easy to produce, especially with
transformer feedback, although where high reverse isolation
is required, care must be taken. Mixers are however, another
matter.
Probably the most popular mixer is the diode ring (Fig.9).
Although popular, this mixer does have some drawbacks,
which have been well documented. These are:
Insertion loss (normally about 7dB)
High LO drive power (up to +27dBm)
Termination sensitive (needs a wideband 5(0)
Poor interport isolation (40dB)

c
LOCAL
OSCILLATOR

Fig.9 Diode ring
Fig.B

HF receivers will often require input intercept pOints of
+20dBm or more. The usable noise factor of HF receivers is
normally 10-12dB: exceptionally 7 or 8dB may be required
when small whip antennas are used. An SSB bandwidth
would have a dynamic range from (1) of 105.3dB. The same
receiver with a 100Hz CW bandwidth would have a dynamic
range of 114.6dB and thus dynamic range is quite often a
confusing and imprecise term.
Appendix A defines a quantitive method of
Intermodulation Noise Floor assessment, developed later
than the data in Figs.5 to 7.

The insertion loss is a parameter which may be classed
merely as annoying, although it does limit the overall noise
figure of the receiving system. The high LO drive power
means a large amount of DC is required, affecting power
budgets in a disastrous way, while termination sensitivity
may mean the full potential of the mixer cannot be realised.
For the diode ring to perform adequately, a good
termination 'from DC to daylight' is required - definitely at the
image frequency (LO ± sig. freq.) - and preferably at the
harmonics as well. Finally, interport isolation of 40dB with a
+27dBm LO still leaves -13dBm of LO radiation to be
filtered or otherwise suppressed before reaching the
antenna.

293

A further problem with the simple diode ring of this form is
that the 'OFF' diodes are only off by the forward voltage drop
of the ON diodes. Thus the application of an input which
exceeds this OFF voltage leads to the diodes trying to turn
ON, giving gain compression and reduced IMD
performance.

of intermodulation, but by using suitably large transistors
and emitter degeneration, very high performances
(+32dBm input intercept) can be achieved. The Plessey
SL6440 has been described (Refs.3, 4, 5) and uses these
techniques to achieve a high standard of performance (see
Fig.16).

LOCAL OSCILLATOR

Fig. 10 Resistive loaded high intercept paint mixer

Fig.12 VMOS mixer

OUTPUT

LOCAL OSCILLATOR

Fig.11 Quad MOSFE:T commutative mixer

Fig.10 shows a variation of this in which series resistors are
added. The current flow through these resistors increases
the reverse bias on the OFF diodes which gives a higher gain
compression point: such a mixer can give +36dBm intercept
points with a +30dBm of LO drive. Nevertheless, as is
common to all commutative mixers, the intermodulation
performance is related to the termination, and the LO
radiation from the input port is relatively high.
Variations of this form of mixer include the Rafuse Quad
MOSFET mixer of Fig.11, which suffers with many of the
same problems. Fig.12 shows a dual VMOS mixer capable of
good performance, but requiring a large amount of DC
power and with limited isolation of the LO injection.
Many advantages accrue to the choice of the transistor
tree type of approach (Fig.13). Here the input signal
produces a current In the collectors of the lower transistors
and this current is com mutated by the upper set of switching
transistors. Because the current is to a first order
approximation independent of collector voltage, the
transistor tree does not exhibit the sensitivity to load
impedance that the diode ring does, and indeed, by the use
of suitable load impedances, gain may be achieved. The nonlinearity of the voltage to current conversion in the base
emitter junctions of the bottom transistors Is the major cause

294

Fig.13 The transistor tree·

PHASE NOISE
The mixing process for the superhet receiver is shown in
Fig.14, where an incoming signal mixes with the local
oscillator to produce the intermediate frequency. Fig.15
shows the effect of noise modulation on the LO, where the
noise sidebands of the LO mix with a strong, off channel
signal to produce the IF. This means that the phase noise
performance ofthe LO affects the capability ofthe receiver to
reject off channel signals, and thus the receiver selectivity is
not necessarily defined by the signal path filters. This
phenomena is referred to as Reciprocal Mixing, and has
tended to become more prominent with the increased use of
frequency synthesisers in equipments.

Local
Oscillator

To put these levels in perspective, relatively few signals
generators are adequate to the task of being the La in such a
system. For example, 'Industry Standards' like the HP8640B
are not specified to be good enough: neither are the HP8642,
Marconi 2017/2018, or Raca19082, all of which are modern,
high performance signal generators.
All this suggests that it is very easy to over-specify a
receiver in terms of selectivity, and Simple synthesisers are
not necessarily ideal in all situations.
The ability of the receiver to receive weak wanted signals in
the presence of strong unwanted signals is therefore
determined not only by the intermodulation capabilities of
the receiver, but by phase noise and filter selectivity.
The usual approach to high performance synthesis has
used multiple loops for good close-in performance. Notable
exceptions are those equipments using fractional N
techniques with a single loop. Nevertheless, such
equipments not generally specified as highly as multi-loop
synthesisers. A vital part of the synthesiser is still the low
noise VCO, for which many approaches are possible. This
VCO performance should not be degraded by the addition of
the synthesiser: careful choice of technologies is therefore
essential. For example, Gallium Arsenide dividers are much
worse in phase noise production than silicon, and amongst
the silicon technologies, TTL is better than ECL.
From equation (1)

Wanted
Signal

Fig. 14 Superhet mixing

Noisy Local

Oscillator
Unwanted
Signal

Wanted
Signal

2
DR = 3(l p3- NF) dB

Translated
Noise

where I p3 = input intercept point dBm
NF = noise floor dBm
Wanted IF

The phase noise governed dynamic range is given by

IF ~I._~---+I

DR¢> = Pn

Fig.15 Reciprocal mixing

The performance level requirements of receivers is
dependent upon the application. Some European mobile
radio specifications call for 70dB of adjacent channel
rejection, equating to some -122dBcJHz, while an HF
receiver requiring 60dB rejection in the adjacent sideband
needs -94dBc/Hz at a 500Hz offset. The use of extremely
high performance filters in the receiver can be completely
negated if the phase noise is poor. For example, a receiver
using a KVG XF9B filter with a rejection in the unwanted
sideband of 80dB at 1.2kHz, would require a local oscillator
with -114dBc/Hz phase noise at 1.2kHz if the filter
performance was not to be degraded.

REF -3.3dBm

I.
U

ilL.

r1l!'J"/!.,.,. ... . . , .
CE~

mE 1.404MHz

..
ltd'

+ 10 10glOB Db

(2)

Where P n is the phase noise spectral density in dBc/Hz at any
offset and B is the IF bandwidth in Hz.
(N.B. This is not quite correct if B is large enough such that
noise floor is not effectively flat inside the IF bandwidth).
Ideally the ratio
DR 1M
DR¢>

should be 1 in a well designed receiver - I.e. the dynamic
range limited by phase noise is equal to the dynamic range
limited by intermodulation.
Certain aspects of low noise synthesiser design have been
touched upon and Ref.6 provides further information.
The performance of a receiver in terms of its capabilities to
handle input signals widely ranging in input level is
dependent upon the receiver capability in terms of
intermodulation and phase noise. Neglect of either of these
parameters leads to performance degradation, and it has
been shown that specifications are not only often difficult to
meet, but sometimes contradictory in their requirements.

This paper was first presented at the RF Technology Expo,
Anaheim, Jan 1986.
P.E. Chadwick

~
SPAN 50IcHz

Fig. 16 SL6440 intermodulation performance

295

REFERENCES
1.

Broadband Amplifiers Application Notes, Appendix 3, Plessey Semiconductors Ltd., Cheney Manor, Swindon, England.

Ideal Limiting Part 1, George S.F. and Wood, 3.w., Washington D.C.: U.S. Naval Research Laboratory AD266069,
2nd October, 1961.

The SL6440 High Performance Mixer, P.E. Chadwick, Wescon Proceedings Session 24, Mixers for High Performance
Radio Published by Electronic Conventions Inc., 999 North Sepulveda Blvd. EI Segundo, CA., 90245.

High Performance Integrated Circuit Mixers, P.E. Chadwick. Clark Maxwell Commemorative Conference on Radio
Receivers and Associated Systems, Leeds 1981. Published by I.E.R.E.,Savoy Hill House,Savoy Hill,London. Conf. Pub. 49.

The SL6440 High Performance Mixer, P.E. Chadwick. R.F. Design, June 1980.

Frequency Synthesisers. Vadim Manassewitsch, Wiley & Sons, 1980 ISBN 0-471-07917-0.

296

APPENDIX A

Intermodulation is caused by odd order curvature in the transfer characteristic of a device. If two signals f1 and f2
are applied to a device with third order term in its transfer characteristic, the products are given by:
(COSf1

+ COSf2)3

= Cos3f1

+ 3COS2f1

COSf2

+ 3Cosf 2f2 COSf1 + Cos3f2

from the trig identities Cos3A, Cos2A and CosACosB, this is

+ %Cosf1 + %Cos 2f1Cosf2 + %COSf1Cos 2f2 + %COSf2 + %Cos 3f2 + %COSf2

%Cos 3f1
(where f1
Cos(2f1
Cos(2f2

A and f2 = B). Neglecting coefficients, the terms Cos2f1 COSf2 and COSf1 Cos2f2 are equal to

+ f2) + Cos(2f1 + f1) + Cos(2f2 -

f2) and
f1)

By inspection, it may be seen that frequencies of f1, 12, 3f1,3f2, (2f1 ± f2) and (2f2± f1) are present in the output. Of
these, only 2f2 - f1, and 2f1 - f2 are close to wanted frequencies f1 and f2.
The application of three signals f1, f2 and f3, produces a similar answer, in that the resulting products are:
3f1, 3f2, 3fa, f1

+ f2 + f3, f1 + f2- f3,

f1- f2

+ f3,

f1-12- f3, f2- f1

+ f3, f2- f1- f3, -f1- f2- 13, -f1- f2 + 13

in addition to the products
2f1 ± f2, 2f2 ± f1, 2f2 ± fa, 213 ± f2, 2f1 ± fa, 213 ± f1
if a greater number of signals are applied such that the input may be represented by:
COSf1

+ COSf2 + Cosfa + COSf4 ... Cosfn

The result from third order curvature can be calculated from:
(COSf1

+ COSf2 + COSf3 + COSf4 ... COSfn)3

This expansion produces terms of
Cos(f1± f2± f3), COS(f1 ± f2± f4), COS(f1 ± f2± fn) etc from which it can be seenthatthetotal number of products is:
n!
3!(n _ 3)! =4 x Yen (n- 1)(n - 2)
(The factor of 4 appears because each term has four possible sign configuratons i.e. COS(f1
COS(f1 + f2 - f3) etc). This agrees with Ref A1.
Bya similar reasoning, n signals produce:

+ f2 + f3),

2n(n - 1) products of the form (2f1 ± f2) (2f2 ± f1) etc and n 3rd harmonics.
Thus the total number of intermodulation products produced by third order distortion is:
n

+ 2n(n -) + %n

(n - 1)(n - 2)

(1)

Reduction of the input bandwidth of the receiver modifies this. Consider, for example, a receiver with sub-octave
filters, rather than the 'wide-open' situation analysed above. In this case, the third harmonics produced by any input
signals will not fall within the tune band, as will some of the products such as f1 + f2 + fa, f1- f2- f3, etc. In this case,
the total number of intermoduation products is reduced. There are only three possible sets of products of the form f1
f1± f2± 13, i.e. f1 + f2- 13, f1- f2 + f3and f3- f1- f2which can give products within the band. Note thatfor products to
be considered, they must have an effective input frequency at the receiver mixer equivalent to an on-tune desired
signal. In addition, products of the form 2f1 + f2, 2f2 + f1 etc are again out of band. Thus half of the 2n (n - 1)
products of this class are not able to cause problems and the total number of products to be considered is now:
n (n - 1)

+ %n

(n - 1)(n - 2)

(2)

This result does not agree with Barrs (Ref A2) who uses the results in (1). The results in (2) are an absolute worst
case, insofar as a number of the intermodulation products are out of band.
(For the purposes of this analysis, IMD in a mixer is assumed to produce an 'on tune' signal. Thus not all the
possible intermodulation frequencies appearing in a half octave bandwidth will be able to interfere).
The same arguments apply to narrower front end bandwidths. However, the narrower the front end bandwidth,
the higher is the probability that the distribution of signals will produce IMD products outside the band. For
example, a receiver with ±2.5% front end bandwidth tuned to 10MHz will accept signals in a band from 9.75 to
10.25MHz. Signals capable of producing a product of the form 2f1 - f2 must have one of the signals (f1 or f2) in the
. band 9.875 - 10.25 for a product to appear on tune. Thus the two signal apparent bandwidth is less than would be
expected. Similar constraints apply to the 11 + 12 - f3 product.
Similar arguments apply to other orders of curvature. Second order curvature, for example, will not produce any
products in band for input bandwidths of less than 2:1 in frequency ratio.

297

The actual levels of intermodulation produced can be predicted from reference A1. In practice, the situation is
that the input signals to a receiver are rarely all of equal unvarying amplitude and assumptions are made from the
input intercept points and the input signal density.
If a series of amplitude cells are established for given frequency ranges, such as that in Table 1, then a prediction
of the number of intermodulation products for any given number of input signals and amplitudes may be obtained,
either from equation (1) or (2) (as applicable) or from Ref A1 (for higher orders). Where the input bandwidth of the
receiver is deliberately minimised, the maximum cell size in the frequency domain should be equal to the input
bandwidth.
The total input power in each cell is
nPav
where n is the number of signals and Pav is the average power of each signal.
A worst case situation is to assume that all signals in the cell are equal to the cell upper power limit boundary, e.g.
if the cell amplitude range is from -40 to -30dBm, then an assumption that all signals in this cell are at -30dBm is a
worst case.
If, however, it is assumed that signals will have a Gaussian distribution of input levels within a cell, then the total
input power becomes:

Pt = 0.55nP
where Pt is the total power
n is the number of signals
P is the power level at the upper boundary of the cell
Because the total IMD power is the sum of all the IMD powers, the average input power is
Pav =

0.55nP
n

The IMD power produced by third order curvature is:
10 log10 [%n(2n2

+ 1)) Antilog Y,o[Pav -

3(13 - Pav))dBm

where PIM is the total power of the intermodulation products
13 is the third order input intercept point
Because the coefficients of the amplitudes of the intermodulation products are (depending on product)
a 3, a 2 b, ab 2 , abc, b 3
where a, band c are approximately equal, the use of a3 as the general coefficient is justified.
From equations (1) or (2) and (3), the totallMD power and number of products may be calculated. As 'n' increase
in number, the number of products will mean that the resultant IMD tends more to a noise floor increase in the
receiver, thus reducing the effective sensitivity.
The amount of this degradation is such that the noise floor is:

% (O.55nP)3
13

13
x af
(fmax - fmin)

where (fmax- fmin) is the bandwidth prior to the first intermodulating stage. af is Signal bandwidth in a linear system.
The Gaussian Factor of 0.55 is somewhat arbitrary, since errors in this assumption are cubed.
The intermodulation Limited Dynamic Range is
% (13

+ 174 -

10 10glO af - NF)

where NF is the Noise Figure in dB.
The effects of Reciprocal Mixing are similar, except that signals may be taken one at a time. The performance is
affected by the frequency separation between an 'off-tune' interfering signal and an 'on-tune' wanted signal unless
the separation is such that the oscillator noise floor has been reached. Here again, reduction offrontend bandwidth
reduces the number of signals.
Generally speaking, the effects of reciprocal mixing are limited to close in effects - say within ±50kHz, unless very
poor synthesisers are used.
The response at some separation fo from the tune frequency is: (L - 10 10glO 10af)dB where L is phase noise
spectral density in dBc/Hz and af is the IF bandwidth.
This assumes that the spectral density does not change within the receiver bandwidth: Ref A 1 shows this to be
generally applicable for narrow bandwidths.
The intermodulation free dynamic range is defined as:
%[13- noise floor) = %[13

+ 174 -

10 log10 af - NF)dB

where 13 is the input 3rd order intercept point in dBm
NF is the noise figure in dB
af is the IF bandwidth in Hz

298

It has been claimed that there is 6dB rejection of phase noise in diode commutative mixers. Thus the relationship
between IMD and phase noise can be expressed as:
IMD dynamic range = phase noise dynamic range +6dB = (L - 10 log10 .t.f) + 6dB
Thus at any offset, it is important to ensure that the two dynamic ranges are approximately equal if performance is
not be be compromised.
A receiver for example with an input intercept pOint of +20dBm and input signals of -30dBm will produce an IMD
product at-130dBm which, for an HF receiver with a noise factor of8dB, will be just above the noise floor, in an SSB
bandwidth. The noise floor of the LO will need to be such that the noise is at -133dBm if degradation is not to occur,
and th is wi II be produced by a noise floor of -137 dBc/Hz in the synthesiser atthe frequency separation of the signals
in question. Thus the high intermodulation performance may well be compromised by poor phase noise.
REFERENCES

A Table of Intermodulation Products, JIEE (London) Part 111,31-39 (Jan 1948) C.AA Wass.

A Re-appraisal of H.F. Receiver Selectivity, RA Barrs. Clerk Maxwell Commemorative Conference in Radio
Receivers and Associated Systems, Leeds 1981. pp.213-226, Published by IERE, 99 Gover Street,
London WC1 E 6AZ. Conference Publication No. 50 ISBN 0 903 748 45 2.

299

Radio Synthesiser Circuits
Loop Filter Design_~_ _ _ _ _ _ _ _ _ _ __
LOOP BANDWIDTH
An important choice In the design of the Phase Locked Loop Is the Loop Bandwidth. This detennlnes parameters such as lock
up time, noise and modulation capability, and generally Is made as wide as possible in single loop synthesisers. There are
conflicting requirements however, and single loop synthesisers are not always practicable - Rets. 1, 2.
The NJ8820 series use two phase detectors, a digital
where Kv is the veo constant in radS/volts-sec.
'steering' detector and an analog high gain linear detector.
Although the loop will lock eventually without the digital
This latter detector is a sample-and-hold type in which an
steering, the time taken is much longer. The time to attain
frequency lock is given approximately by:
internal SOpF capacitor is discharged at a constant current.
This current is set by the gain programming resistor RB, and
ll. W R2
the voltage on the capacitor is sampled at the reference
... (S)
frequency. Thus the gain of the detector is fixed by the time
2.SKv (R3 + ~)
available for the capacitor to be discharged. If the discharge
current was constant, the phase detector would have a gain
This is derived from the slew rate at the output of the
directly proportional to frequency and current, but the
integration without the digital loop connected. Independent
departure from constant current gives a correcting factor,
control of lock up time and loop bandwidth is therefore
and the gain is thus:
available by correct choice of R1.
1

[VSUPPLY-

0.7 - 89 (RB) -2]
12 + CAP) x RB x ... (1)

K - 10 [27T x (SO x 10
where RB is the gain

FR]

programming resistor and FR is the phase comparison
frequency. The value of CAP is 0 for the NJ8820/1 and is
fixed externally in the NJ8822.
The analog phase comparator has a very high gain and so
can only operate over a narrow phase range. This phase
window is given by:

ll.

= 4.S/K radian

The 2nd order analog loop has a bandwidth and damping
factor given by:

R3C

0=2""

... (2)

R2
pOA--~~~--~--~

__~~I-,

... (6)

. Wn

... (7)

If the loop is slewed at too high a rate by the digital output,
then a longer lock up time may result because of overshoot;
in extreme cases, the loop will become unstable, because the
VCO frequency will sweep too quickly.

where K is the phase detector constant (volts/radian).
When the analog phase detector is outside this range, the
digital detector operates to provide steering. Inside the
analog detector phase range, the digital output is in its 'TriState' high impedance condition.
When the loop filter consists of an integrator of the form of
Fig.1 the digital output produces a voltage ramp given by:
R3 2.S
- 2.S R1 - R1 C volts/sec

~KKV
NR2C

Wn =

CR2 =
R2
R3
R1

where Wn =
K =
Kv =
o=
N =

27T KKv
wn2N

... (8)

7T KKv
ONwn

... (9)

;;: SR2 20
Wn

... (10)

loop bandwidth in rads/sec
analog phase detector gain in volts/rad
veo sensitivity in Hz/volt
loop damping factor
divide ratio

The minimum value of R1 can be determined as follows. The
noise bandwidth, Bn, of a second order loop is:
PDB--~~~---+--~

Bn =
Fig.1 Augmenting integrator for loop filter

R3
( -R1

+ R1C1
-1)
- rads/sec2

dLw
dt

1
(
= 2R3C 4Bn -

R!c) (Bn in radians) ... (12)

Thus the maximum voltage sweep is

1
(
dt = 2Kv R3C 4Bn-

R!c)

... (13)

which simplifies to
... (3)

Thus for a frequency step of ll. w, the loop will slew to the
new freql,Jency in

ll.w

gx.

... (14)

dt
The integrator gives an output (assuming R2»

... (4)

300

... (11)

and the maximum sweep rate is

The figure of 2.S is derived as follows:
A 2nd order loop has infinite De gain and thus the analog
phase detector output sits at a potential very close to the half
supply voltage point. It is thus at 2.SV, and the maximum
change in Vin is therefore 2.SV, and this input will appear
whenever the digital phase detector operates.
This ramp results in a frequency sweep of approximately
2.SKv

Fh + Ri3

K4>Kv

= 2.S

R3
( R1

1 )
R1C volts/sec

R1)

... (1S)

R3
therefore 2.5 ( R1

R3=~

1) :;;;

R1 C

K4>

2R2C

... (16)

and by substitution,

WnD

;;:. 5R2 (2D

K4>

IWn

+ 1)

... (17)

For D > 0.5 < 1.0
and Wn> 10 rads/sec
Then the approximation

... (18)

is correct.
It is advisable to use a larger value than this: it is suggested
that

R1 min = 6R2

K4>

... (19)

The mInImum usable values of K4> occur at higher
reference frequencies, where a wider loop bandwidth can be
used. Wide loop bandwidths are good for reduction of veo
noise and freedom from microphony, while narrow loops
minimise the effects of reference frequency noise.
The NJ8820 analog phase detector has an internal noise
level of about 1 microvolVVHz at a frequency of 100Hz. This
falls within increasing frequency, and decreasing phase
detector gain.

veo

Avoidance of this condition may be achieved by limiting
the phase deviation at the detector such that detector is
operating within its linear range. For devices with
programmable phase detector gain, such as NJ8820 series,
this may be achieved by using a low gain and high deviation
ratio.
Modulation index, m, is given by:

Noise

Phase noise of the veo inside the loop bandwidth will be
reduced by the loop, while outside the loop bandwidth it will
be unaltered. The phase noise of the reference oscillator will
add to the veo noise at frequencies inside the loop
bandwidth and this effect also influences the choice of loop
bandwidth. For example, a loop with a 5kHz loop bandwidth
operating at 900MHz with a reasonable 5MHz crystal
oscillator noise floor (-125dBc/Hz at 1kHz oscillator) would
have a noise power of some -80dBc/Hz at 1kHz offset at final
frequency. For a further discussion of phase noise and other
compromises see Ref. 2.
Where a high phase detector gain is used with a noisy
oscillator, or with a high value of Kv, it may well happen that
the analog phase detector is driven outside the phase
window. This will lead to the digital output becoming active,
and instability is likely to result.

Modulation Techniques
Modulation of the PLL may take place inside or outside the
loops bandwidth. Modulation outside the loop bandwidth
requires the loop bandwidth to be less than the lowest
modulating frequency, and the amount of modulation will
vary over the frequency range as K v, the veo constant varies.
Various techniques may be used to minimise the variation
in modulation sensitivity, and probably the easiest in the use
of a separate modulation diode. The variation in capacitance
is very small for normal NBFM variations and thus the
deviation may well remain sensibly constant over a wide
range, e.g. +0.75kHz for 5kHz nominal deviation over an
18MHz range at VHF.
Modulation outside the loop bandwidth leads to a signal
appearing at the phase detector output corresponding to the
phase error between reference frequency and the divided
veo. Should this phase error be such as to lead to the phase
detector being driven outside its phase window, then
problems may occur, with reference frequency sidebands
appearing and possibly even unlocking of the loop.

frequency deviation
modulating frequency

... (20)

For a modulation index of 1 at the veo, the phase variation is
1 radian. Thus an NBFM transmitter with a deviation of
2.5kHz and modulation frequency of 500Hz has a phase
deviation of 5 radians.
In a 25kHz channelled system at 30M Hz, the deviation at
the detector would be 5/1200 rads or 0.24 degrees.
Attempting to operate the NJ8820 at 800 volts/rad would give
problems because of limiting in the analog phase detector.
Modulation inside the loop bandwidth avoids this problem,
but care must be taken to ensure that the reference
frequency sidebands do not become appreciable. In
addition, the wideband noise of the phase detector and loop
filter can cause problems when Kv, the oscillator constant in
MHz/volt, is high.
Modulation of the reference oscillator is another possible
technique of modulating inside the loop bandwidth.
However, all modulation inside the loop bandwidth produces
phase rather than frequency modulation and there are, in
addition, limits on the frequency deviation and modulation
frequency that can be accepted without the loop becoming
unlocked. Generally, the modulation frequency must be
much less than the loop bandwidth. Gardner (Ref.4) has
derived the equation:
... (21)

Aw
where I:. W =
Wn =
Wm =

frequency deviation
loop natural frequency (bandWidth)
modulating frequency

This equation is only valid for Wm« Wn
In general, modulation outside the loop bandwidth is used,
because the required bandwidth is greater than the reference
frequency. The loop bandwidth is usually 1/5 and 1/10 of the
lower modulating frequency.
Note that modulation applied such that

I:.w
dt

>- K4>Kv
'"

R2C

... (22)

will cause the loop to unlock.
In addition, modulation such that the analog phase
detector limits is not advisable. This will occur when

1:.4>

;;:. 4.5N/K4> rads

1:.4> is equivalent to m, the modulation index: when m

... (23)

= 1,

A4> = 1 radian.
Thus, a synthesiser operating at 145MHz with a 25kHz
comparison frequency and a modulation index of 30 for the
lowest modulating frequencies would need K4> to be less than
870 volts/rad. Operation at lower frequencies are used.
However, large amounts of LF phase noise can have
appreciable phase deviations and thus low noise oscillators
should be used.
Noise from the amplifier used in the loop filter should be
minimised: the use of a low noise amplifier such as a Plessey
SL562 is suggested. Filtering after the amplifier, such as in
Fig.2, is advisable to minimise the noise modulation of the
veo, but care should be taken to ensure that the added
phase shift does not cause the loop to become unstable.

301

Loop Stability
Calculation of loop stability may be carried out in a number
of ways. It has been claimed (Ref.4) that a true 2nd orderPLL
does not exist because of strays. In addition, an extra section
(at least) of RC filtering is generally required to minimise the
effects of noise in the operational amplifier. Various
computer programs exist in which such analysis can be
undertaken, but it is possible to evaluate loop stability in a
relatively easy manner using a programmable calculator.
For a 2nd order loop such as Fig.2, it may be shown that the
transfer function is

A oKK v
Nw
where 0

E =
F =

wT2

i (1-W2E) - W (F- w2D)

... (24)

+ T2)
+ To + T1 + T2) + To (T1 + T2)
+ To + T1 + T2 + T3

T3To (T1
T3 (Ao T1
Ao T1

and Ao, K' Kv, N,
definitions.
Ao
To
T1

T2
T3

w, have the previously assigned

open loop amplifier gain
1/fo, amplifier open loop 3dB bandwidth

R2C1
R3C1
R4C2

The finite modulation bandwidth ofthe VCO is ignored in this
analysis.
Evaluating the equation (24) in terms of gain and angle
(rLO) at various frequencies allows the stability to be
evaluated. An example of a frequency synthesiser design is
given in the following section, where Table 1 lists a suitable
program for Hewlett Packard Calculators using Reverse
Polish Notation.

Frequency Synthesiser Design _ _ _ _ _ _ _ __
A frequency synthesiser is required for a transmitter covering 144-14BMHz. the supply Yoltage for the synthesiser is 10 Yolts,
pre-emphasised frequency modulation is required with an upper limit of 3kHz, adjacent channel noise is required to be -70dB at
12.5kHz channel spacing and a 'lock-up' time of 25ms Is required.
12.5kHz channel spacing systems use an IF bandwidth of
R1 min =6R2
... (27)
7.5kHz, which gives approximately 39dB more noise than a
K
1Hz bandwidth. Thus the VCO for this synthesiser must have
Thus, at the mid-band frequency of 146M Hz, where N =
a phase noise characteristic of -109dBc/Hz at 12.5kHz (see
11680:
Ref.1) and from Refs. 2 and 3 this may be shown to be
practical with a Single loop synthesiser using a narrow
CR2 = 27T x 320 x 0.75 x 1()6 = 1 3
... (28)
bandwidth.
(27T X 50)2 X 11680
.
The choice of prescaler should be made from a
consideration of programming - see the relevant data sheet.
~ = 7T x 320 x 0.75 x 1Q6 =293
The lowest modulation frequency is 300Hz and the
... (29)
R3
0.7 x 11680x27TX50
transmitter will attenuate components below this frequency
at 12dB/octave or more. Standard pre-emphasis rises at
6dB/octave from 300Hz to 2700Hz: thus the deviation at
1
... (30)
R1 ;",5R2 (2D )
300Hz is approximately 18dB down on that at 2.7kHz and at
K
Wn
50Hz will be about -45dB. With a deviation at 2.7kHz of
2.5kHz, the deviation at 50Hz will be about 15Hz.
The use of high values of resistance leads to greater noise
At 144MHz, the divide ratio is 145000/12.5 = 11600. Thus
generation in the loop filter because of KTB noise, while low
the 15Hz deviation it caused by the 50Hz modulation
values lead to larger current swings, which can give slew rate
becomes
limiting in the op-amp. If R3 is set to 22000, thus preventing
slew rate limiting,
15/50 x 1/11600

radians at the phase detector, which is negligible. Thus the
analog phase detetor will operate inside its window at low
frequencies. Even at 300Hz where the modulation index is
8.33, the phase deviation at the phase detector is only 0.041
degrees.
Since a 10V supply is available, a VCO control'ineswing of
8 volts may be assumed. Allowing overlap, the VCO will
cover 143-149MHz, giving Kv (the VCO constant) as
0.75MHzlvolt. This gives a residual deviation caused by the
phase detector noise of about 0.75Hz.
A loop bandwidth of 50Hz is well below the lowest
modulating frequency and values may be readily calculated.
K, the phase detector gain, is an independent vari!lble; a
reasonable mid-range value of 320 volts/rad gives a phase
window of 0.89 degrees.
From these constants, values of R1, R2, R3 and C in Fig.1
may be calculated.

CR2

= 21T KKv
wn 2 N

R2 ~ 1TKKv
R3 - DNwn

302

... (25)
... (26)

R2 = 664kO (use 680kO)
C1 = 1.91lF (use 2.~F)
From these standard values
W n

=...jN;;~

= 293.3rads/sec

== 46.7Hz

...(31)

R3C

and D =-2-' Wn =0.71

C1
R3
R2
PDA-C~-.......- t !--C=:J--,

R1
PDB-C::J-~-~

;;:;, C2

Fig.2 Augmenting integrator amplifier with filtering

R1 min

( 5x

6801<0) ( 271"2 xx0.71
)
46.7 + 1

320

= 10.7kn ... (32)

Loop Stability Program for HP Calculators
Enter

STOO
ST01
ST02
ST03
ST04
STOS
ST06
ST07

(use 12kn or 151<0).
A further section of filtering may be added as in Fig.2, and
the cut-off frequency may be arbitrarily set at 500Hz. Again, a
reasonable compromise is required on CR values for the
same reasons. The added filter section reduces noise from
the op-amp and resistors, and so is a useful addition.
Let R = 101<0 and C = O.33pF
Using the program in Table 1, the stability may be calculated.
(Assume a Plessey SL562 op-amp, where fo, the open loop
3dB frequency is 250Hz and Ao, the open loop gain = 30000).
TO

T1
T2
T3
N
K4>
Kv

1/fo = 4 x 10-3
R2C1 = 1.496
R3C1 = 4.84 x 10-3
R4C2
330 x 10-8

320

The results of the program are:
Frequency (Hz)

Loop Gain

Phase Margin (Degrees)

1
10
SO
100

2200
23
1.S9
0.69

-178
-164
-119
-128

From this analysis, it may be seen that the loop is stable.
Increasing the time constant of T3 is thus practicable from a
loop stability point of view.
The lock up time t may be calculated from

l!.w

2.SKv

(1
. R1R3

+ CR1

)

Enter
2
x
DDS (h)7I"
x
ST08
RCL1
RCL2
D1D +
RCLO

as opposed to 476ms without the digital steering (see
equation (S)).
Note that these lock up times assume that me major
factors affecting loop bandwidth are the values of the time
constant R2C. In practice, this simplification is not
completely justified, and, for example, increasing the value of
C2R4 to give T3
Sms would increase lock up time while
having little effect on loop stability.

PDA-4:::J~{:::~:::J-i

;;;;,C3

x
D85 RCL9

STO.2
D9D RCL8
RCL2
x
RCL9
x
D9S RCL.O

D6D STO.O
RCL4
RCLS

x
RCL6
065 x
RCL7

-.-

Fig.3 Loop filter with input sections
In cases where the operational amplifier 'locks up' because
of overdrive, the circuit of Fig.3 may be used, often with
success. The time constants C3R2I2 should be about 10/fn
where fn is the loop bandwidth. It should be noted that the
capacitor C1 must be of the non-polarised variety, as the
voltage across it can reverse. Similarly, the external capaCitor
provided in the phase detector of the NJ8820 should be a low
leakage type, such as polystyrene: ceramic capaCitors are
not generally good enough.
Bypassing the gain setting resistor of the NJ8820 series
with a large capacitor may reduce noise derived from this
resistor.

RCL8
(g)X2

RCL8
x
ST09
D35 RCL1
RCL2

RCL.O

RCL.1

RCL3

CHS
1

D3D RCL9

STO.1
D8D RCL8
D81 RCL2

RCL.O

RCLO

+
D55

RCL8
D7D

+
(h)1/x
RCL.1

D5D RCL3

RCL1

D75

RCL3

RCL2
R3

RCL.O
(g)x 2

D46 RCL1

D25
R2

RCLO

RCL2

ST09
RCL4
D2D RCL1

D15 RCL8
(g)X2

so for a 600kHz change,

t = 8.Sms to achieve frequency lock.

Line Function

+
RCLO
x
D4D STO.O
RCL4
RCL1

x
x

... (33)

Line Function

001 hLBLA

0.7SMHzlvolt (4.7 x 108 rads/volt)

K4>
Kv

(TO = 1/fo, the 3dB point of the op amp 'open loop'
bandwidth, T1 = R2C1, T2 = R3C, T3 = R4C2, Ao = open
loop gain, K4> = phase detector gain in volts/rad for the
analog phase detector, Kv = VCO constant in rads/volt-sec,
N = divide ratio).

Line Function

11680

TO
T1
T2
T3
Ao

STO.1
RCL9
(g)X2

CHS
RCL.1

x
100 STO.3
Enter
RCL.2
(g)P
(h)PSE
1D5 (h)PSE
(g)R
(h)RTN

Table 1 Loop stability program

To use, enter the frequency in Hz, and press R/S. The
display will show the loop gain, flash twice and display the
phase margin in degrees.
Note that HP calculators provide angular information up to
±180 degrees only. Thus a change from -179 degrees to
-181 degrees would show as -179 to +179 degrees.

303

Multimodulus Division _____________
Phase Locked Loop Frequency Syntheslsers of the form shown In Flg.4 suffer from the problems Inherent In producing fully
programmable dividers required to operate at appreciable frequencies while not consuming excessive power. Although
advances In small geometry Integrated circuit technology make any figures obsolete, guaranteed operation above about 50MHz
requires relatively high power.
The use of fixed prescaling, as in Fig.5, is widely used, but
for a division ratio of N in the prescaler and a channel spacing
of f kHz, the phase comparison frequency of Fig.4 has been
reduced by the factor fiN. This lower frequency necessitates
a lower bandwidth in the phase locked loop, and thus a
greater susceptibility to microphonics etc., and, generally
speaking, a longer lock up time.
The alternatives to fixed division are mixing, as in Fig.6 or
'multi modulus division' ('pulse swallowing') as in Fig.? The
use of mixers requires great care in the choice of frequencies
if spurious products are not to be a problem and although
widely used, is certainly more complicated than
multimodulus division in terms of its physical realisation,
requirements for 'adjust-on-test' parts, and its susceptibility
to layout problems.
The multi modulus divider system is shown in Fig.? It is
built up from a number of blocks:

1. A two-modulus divider which will divide by one of two
numbers N or N + 1 (e.g., 10/11,64/65 etc.).
2.

An A counter which is programmable and the output of
which controls the modulus of the divider.

DeSign in this region is critical: worst case tolerances
MUST be used if the reproducibility and reliability of the
design under temperature and voltage extremes is not to be
compromised.
The value of N must also be large enough that the output
frequency from the divider does not exceed the maximum
input frequency of the following circuitry. In single chip MOS
controllers, this may well be as high as 50MHz under some
conditions, but under others, such as high temperature and
low voltage, much lower. Generally, however, the limitation
on such circuits is the loop delay ratherthan inputfrequency.
The loop delay is affected by the edge of the waveform on
which the divider and the A and M counters trigger. If the
edges are opposite then the loop delay may be increased by
large amount, and if in these circumstances, the use of an
inverter at the output of the divider is justified.
The minimum value of N is therefore seltled by these
constraints, but the actual choice of N may be determined by
the ease of programming. This may be seen by conSidering a
synthesiser with a 25kHz phase comparison frequency and
25kHz channelling, using a 40/41 divider.
At 156MHz:

3. An M counter which is programmable, is clocked in
parallel with the A counter, and the output of which resets
both itself and the A counter.
The counters may count 'down' to zero from the
programmed input, or count 'up' from zero.
The principle of operation is as follows:
The A counter is programmed to a smaller number than
the M counter and assuming the counters to be empty, the
system starts with the divider (NIN + 1) dividing by N + 1.
This continues until the A counter reaches its programmed
value, whereupon the divider divides by N until the M counter
is full. As the M counter has received A pulses, this counter
overflows after (M - A) pulses, corresponding to N(M - A)
input pulses to the divider. Thus the total division ratio P is
given by:

304

> total loop delay

= 0 for the lowest channel)

fN = 1 or 10 or 100

= f, 10

f,
100

etc.

and similarly for binary divide ratios.
The choice of prescaler is therefore fixed by

1. Total allowable loop delay.
N
fin

= 6240

In general, where

=NM +A
Obviously, A must be equal to or less than M forthe system
to work, while for every possible channel to be available, the
minimum total divide ratio is N(N - 1) while the maximum
total divide ratio is M(N + 1). Amax should be equal to or
greater than N.
Although deceptively simple in theory, there are a few
pOints which require consideration in the design of such a
divider system. Of these probably the most important is Loop
Delay.
Consider the counter chain at the instantthat the (N + 1)th
pulse appears at the two modulus divider input. After some
time tp1 the output produces a pulse, which clocks theA and
M counters. Assume that the A counter is filled by the pulse,
and so after a time tp2 (determined by the propagation delay
of the A counter) an output is produced to set the dual
modulus divider ratio to N. After a set-up time ts, the dual
modulus divider will divide by N. But if tp1
tp2 + ts is
greater than N cycles of input frequency, the divider will not
be set to divide by N until after N pulses have appeared, and
the system will fail. Thus

156
0.025

therefore NM + A = 6240
therefore 40M + 0
6240 (A
therefore M = 156

= (N + 1)A + N(M - A)

N
fin

> controller delays

2. Output frequency within the controller input frequency
band,

Programming ease.

REFERENCE FREQUENCY DIVISION RATIO (R)
The value of R is set by the input frequency and the phase
comparison frequency. Higher input frequencies require
greater power and offer lower stability, while lower
frequencies (below 4MHz) generally require larger physical
crystal case sizes. Normally, a frequency between 4 and
10.?MHz is used, especially as in double conversion
equipments commonality of oscillators may be possible.
e.g. for a 2.5kHz comparison frequency and 10.245MHz 2nd
local oscillator frequency,

10.245 X 1()6
2.5 x 103

= 4098

Note that R is always an even number.

REF
FREO

Fig.4 Direct division

REF.
FREQ.

Fig.S Fixed presca/ing

'='Ii'r +tx

REF.
FREO.

Fig.6 Mixing in the loop

305

Fig.7 Dual modulus prescaling

Programming the NJ8820 and NJ8821/23
The NJ8820 and NJ8821/23 are versatile high performance CMOS frequency synthesiser controllers. The differences
between devices lies in hardware programming methods.

The basic system of a single loop frequency synthesiser is
shown in Fig.8, where a 2-modulus prescaler is used to divide
the VCO frequency down to a suitable range for use in the
CMOS device. The NJ8820/1/3 is programmed by 8 of 4 bit
words on the data inputs: the addresses for these words may
be obtained internally or externally and appear on the Data
Select inputs/outputs. To program any frequency, it is
necessary to program the A counter, the M counter and the
reference or R counter: these counters are respectively, 7, 10,
and 11 bits long.

end of the cycle, the ME (Memory Enable - NJ8820 and
NJ8820HG only) pin goes high and thus system power
consumption is minimised. 'Power-on' initiation is used, in
which the application of power to the device is sensed and a
programming cycle initiated. In order to avoid corruption of
the data, a delay of 53248 cycles of reference oscillator
frequency is provided before the programming cycle occurs.
This delay is approximately 5ms for a 10MHz reference
frequency.

External Mode

ADDRESSING
Addressing is by one of three modes: These are:

Self Programming Internal Mode

Here the reference oscillator (either an internal crystal
oscillator or from an external source) signal is divided in the
reference counter by 64 and a DATA READ cycle
commences every 1024/fosc seconds.
In this DATA READ cycle, the MEMORY ENABLE pin is
pulled low, and the DATA SELECT outputs DSO, 1 and 2
count in binary from 0 to 7. This provides addresses for the
DATA on DO, 1, 2 and 3, the data being transferred to internal
latches on the trailing edge of the DATA SELECT pulses -see
Fig.9. Note that the Program Clock is internally derived and is
at a frequency of fosc/64. The PE (Program enable) pin is
grounded, and the cycle continuously repeats. This mode is
not recommended, as noise may be picked up by the phase
locked loop.

Single Shot Internal Mode

In this mode, the PE pin is provided with a pulse input. This
pulse initiates a data read cycle as outlined above, and at the

306

The address is presented to DSO, 1 and 2, and a pulse is
applied to the PE pin to transfer data to the internal latches.
The data is transferred from the latches to the counters
simultaneously with the transfer of data into Latch 1: thus this
word should be the last one entered.

WORD VALUES
For any particular set of conditions, viz operating
frequency, prescaler ratio, comparison frequency and input
frequency from the reference oscillator, a unique set of
programming words exist.

Reference Divider
This divider produces the comparison frequency required
by the synthesiser. It is programmable from 6 to 4094 in steps
of 2. The division ratio is twice the programmed number.
Therefore, if for example a 10MHz crystal is used, and a
12.5kHz reference required, this counter would be
programmed to give a ratio of 100000/12.5 = BOO. The actual
programming would then be 400, which would be entered in
binary according to the data map, Table 3.

MEMORY
ENABLE
PROGRAM (PR)
NJ8820HG
ONLY

1--I

(NJ~~~)AND DAT~ SELEt;T OUT~UTS
NJ8820HG ONLY)

DSO DSl DS2

r===~---L~

OSCOUT
VCO

~"l'"

PDB

I
I

LOCK DETECT
(LD)

INPUT D2
D3 1

I
I
MODULUS
CONTROL
OUTPUT
(MC)

Fig.8 The phase lock loop

A and N Dividers
The A counter is a 7-bit counter and the M counter is a 10bit counter. The programming calculations are as follows:
1.

The A counter should contain

x bits such that 2·' = M.

2. If more bits are included in the A counter, these should
be programmed to zero.
e.g.M =64 = 6 bits
A = 10 bits
then the 4 MSB are programmed to zero.

= 440~106 = 145ns

Total divide ratio, P, is given by
P =NM +A
N
64, as a 64/65 divider is used
Pmin from above is 17200

Therefore 17200 = 64M + A
And M ;;;. A
17200
LetA =OThenMmin =---e4 =266.75
17600
= 266
and Mmax = ----e4" = 275.0
Thus the M counter must be programmable from 268 to 275
as required: the M counter must have at least 9 bits.
For a frequency of 433.975MHz

P = 433.97/0.025 = 17359
therefore

M =

17359
64

= 271.2343

The A counter is programmed for the remainder I.e.
0.2343 x 64 = 15
From this, the A counter is programmed to 15 and the M
counter to 271. The output frequency can bow be checked.

= NM +A
= 271 x 64 + 15 = 17359

and this is the required divider ratio.
Repeated calculations for memory programming may be
easily evaluated using a programmable calculator. The
program listed in Table 2 is suitable for most Hewlett Packard
calculators.

307

Line

Function

Display

001

hLBLA
E:NTE:R
RCLO

25 13 11
31
24 0
71
23 2
24 1
71
23 3
25 33
31
24 1
61
23 4
24 3
31
24 3
25 33
41
23 3
25 74
25 74
25 4
25 12

002
003
004

005
006
007
008
009

010
011
012
013
014

015
016
017
018
019
020
021
022
023

ST02
RCL1

ST03
hFRAC
E:NTE:R
RCL1

X
ST04
RCL3
E:NTE:R
RCL3
hFRAC

ST03
hPSE
hPSE
RCL4
hRTN

To use the program, enter the comparison frequency in
STOO, and the dual-modulus prescaler ratio in ST01 (this is
the value of N in an N/N + 1 divider).
Enter the frequency to be synthesised in Hz and press the
RlS button. The calculator will flash twice and display the
decimal value of M: pressing RIS again will display the value
for the A counter. The M counter value is in ST03: the A
counter value is in ST04.
WORD

DS2

DS1

DSO

1
2
3
4
5
6
7
8

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

M1
M5
M9
A3

MO
M4
M8
A2
A6
R2
R6
R10

M3
M7
A1
A5
R1
R5
R9

M2
M6
AO

R3
R7

Table 3 Data map

Table 2 Calculator program for values of M and A

DATA
TRANSFER
ON-VE
CYCLE OF
PROGRAM
CLOCK

DSO----+-------------DS1----+--------------

052----+-------------4 PROGRAM CLOCK
CYCLES FROM SETTLING

WORD WORD
1
2

Fig.9 Data selection

308

DATA
TRANSFER

A4
RO
R4
R8

NJ8820/1 SYNTHESISER DESIGN SUMMARY
1.

•
•
•

Choose a suitable prescaler

•

Check that input frequency range is suitable.

<10.7MHz

N 50ns
fin>

•
+ If + Ip

•

Set loop values
Choose the loop bandwidth W n rads/sec - normally less
than fx . 21T
(fx
crystal freq uency)
10R

Choose the Damping Factor 0 - normally 0.7.
Choose phase comparator gain such that at the lowest
modulation frequency the phase deviation

(If is 'set-up' or 'release' time - whichever is longer; Ip is

Modulalion index
(MN +A)

propagation delay).
•

•

Choose the crystal frequency and value of R
The phase comparison frequency should be as high as
possible - usually the channel spacing.

•

Higher crystal frequencies use more current and are
less stable, but frequencies below 4MHz need larger
case styles.

•

R must be an even number.

4.5
K4>rads

Minimum division ratio is N2 - N.

5.
2.

•

a and 127.

•

A is between

•

A is always equal to or less than M.

•

Total division ratio is NM

•

M is between 3 and 1023.

•

+ A.

21TK4>Kv
Wn 2 . (NM

CR2

+ A)

(K 4> in volts/rad
)
(K v in rads/volt-sec )
( W n in rads/sec
)

•

Set values for A and M

Calculate the values:

R2
R3

1TK 4>Kv
O(NM +A)
6R2
K4>

_1_
R4C2

>- 10wn
~

21T

Check the time to reach a new frequency

•

.6.w
2.5Kv
(.6.

is the frequency step in rads/sec).

>-..----- OIP FREQ = (NM + A) If
MODULUS CONTROL
R effeclive

= 6 TO 4094

ANALOGUE
PDA

Ix max = 10MHz

USE A LOW NOISE OP AMP

Fig.10 PLL using NJ8820/1/3

309

7. Check the loop stability using Bode or Nyquist plots
- or use the calculator program listed in Table 1. (Page 4).

8. Derive the program numbers for the A and M
counters - or use the calculator program listed in Table 2.
(page 9).
9.

M (10 bit binary)

(decimal
M9

0
0

1
1

0
0

1
1

0
0

1
1

26B
26B
26B

An example

..
A synthesiser is to operate from 430 to 440MHz in 25kHz
steps (the channel spacing is 25kHz):
•

Choose the divider The SP8718 is one choice. Since it
divides by 64/65 then N = 64.

•

Choose the reference fl'equency 25kHz is the channel
spacing and is the best choice in this case.

..
..
..
..
..
274
275

Table 5a Binary values for M

•

Choose the crystal frequency 2.5MHz is one possibility.
The value of R can now be calculated:
A

Crystal frequency = Reference frequency x R x 2
•

Calculate the division ratio (the ratio between the VCO
output frequency and reference frequency)
This is 17200 to 17600 in steps of 1.

•

48
49

0
0
0

1
1
1

0
0
0

0
0

..
..

So for the minimum frequency: 64M + A = 17200
If A = 0, M = 268.75
This is not possible (it must be an integer) so this
268.
must be decreased to make Mmin

..
..
..

63
0

Draw up a table for the required values of A and M
Division ratio (P) = NM + A
=64M+A

Calculate values for A and M The division ratio
NM + A is 17200 to 17600.

•

A (7 bit binary)

(decimal)

SoR=50

Table 5b Binary values for A

or use tne calculator program listed in Table 2.
R

268

..
..

48
49
50

17200
17201
17202

430.000
430.025
430.050

50
50
50

..
..

..
..
..

268
269

63
0

17215
17216

430.375
430.400

..
..
..

Division ratio Output frequency (MHz)

..
..
..

274
275

63
0

17599
17600

..
439.975
440.000

Table 4 Decimal values of A and M

These figures are acceptable:

;;;'A

P>M2 - M
The values of M, A and R must be fed into the NJ882O/1 for
each value of frequency required. (In this example the value
of R is constant). The values must first be converted into
BINARY format as shown in Table 5.

310

Rl0

R (11 bit binary)

(decimal)

..
..
..
50

Table 5c Binary values for R

In each case the LSB is identified by the heading MO, AO or

RO.
The NJ8820 and NJ8821/23 require 32 bits of data to be
transferred for each value of frequency. These 32 bits are
composed of the 28 bits above (10
7 + 11) plus 4
redundant bits. The method of transferring this data is
different for the two device types.
NJ8820 - data obtained from a PROM
NJ8821/23 - data obtained from a Microprocessor.

USING THE NJ8820
The NJ8820 operates with an external 4 bit wide PROM.
Information is transferred automatically from the PROM to
the NJ8820 when the PE pin is activated. A 1024 bit PROM
(256 x 4) will store 32 channels because each channel
requires the transfer of 8 words (32 bits) of data. A 256 x 4
PROM has 8 address lines (AO to A7) of which the NJ8820
can address 3 (AO to A2, connected to OSO to OS2). The
remaining 5 address lines allow the unique identification of
the channel required (32 channels in this case) as shown in
Table 6, so for each channel number there are 8 words, each
of four bits. The composition of these words is as shown in
Table 7. The '-' symbol indicates that this is not read normally the 8 bit value is O.
The value of the bits 03, M1, etc. can be either a or 1 and
can be found from the tables in the previous section. For
example, when M = 268 then M1 = 0, MO = aand WORD 1 is
0000.

USING THE NJ8821/23 IN A PARALLEL MODE

•

OSO, OSl and OS2 to select the correct word

•

00, 01, 02 and 03 are the input data for A, M and R

counters

•

PE is the strobe

To enter channel information follow the sequence listed
below:
1.
2.
3.
4.
5.
6.
7.

Ensure the PE (strobe) is O.
Select any word (except word 1) ... (OSO to OS2) and the
relevant input data (00 to 03).
Wait for 1 microsecond or more.
Pulse the strobe (to 1) for 2 microseconds or more and
return to O.
Wait for 1 microsecond or more.
Repeat (2) to (5) as required.
Repeat (2) to (5) for word 1.

The composition of the data words is identical to that for the
NJ8820.

The NJ8821/23 operates with an asynchronous stream of
data supplied from a microprocessor. When used in a 4-bit
parallel mode it requires the transfer of 8 words (32 bits) of
data. Word numbers 1 to 3 control the 'M' counter, 4and 5 the
'A' counter, 6 to 8 the 'R' counter. It is not necessary to
transfer all the words every time; WORD 1 indicates to the
NJ8821/23 that the data should be transferred from all
latches to counters and so WORD 1 must always be sent last.
There are 8 data connections between the microprocessor
and NJ8821 123:

USING THE NJ8821/23 IN A SERIAL MODE
When used in a serial mode (using a single external shift
register) the NJ8821 123 requires the transfer of 8 words, each
of 7 bits (56 bits) of data to program the A, M and R counters
but only 5 words (35 bits) subsequently to reprogram the A
and M counters. There are thus only 3 data inputs from the
microprocessor: DATA, CLOCK and STROBE, as shown in
Fig.11.
ADDRESS LINES

CHANNEL NUMBER 0

CHANNEL NUMBER 1

a
a
a
a
a
a

a
a
a

a
a

word 8

1
1
1
1
1
1

a
a
a

a
a

word 1
word 2
word 3

..
1

word 8

Table 6 Channel identification

ADDRESS LINES
A1
A2

a
a
a
a
1
1
1
1

a
a

M1
M5
M9
A3

1
1

a
a

R3
R7

1
1

a
1

DATA LINES
02
01

MO
M4
M8
A2
A6
R2
R6
R10

WORD

M3
M7
A1
A5
R1
R5
R9

M2
M6
AO

A4
RO
R4
R8

3
4
5
6
7
8

Table 7 Channel number composition

311

+5V
---{1

'--'

[ 2

3
4

4015

[ 1
[ 2

19P

14~

[ 3

[ 4

lap
17 DS2

-{6

DATA

7
ria

rr;'n

'--'

16
15f:!--

~5 NJBB21
6

[ a
DO

CLOCK

DSl

NJBB23 15 ~

[ 7

lOP--

20p

J-!L-

13 J
12

:f2L

11~2

STROBE

Fig.11 NJ8821/23 serial mode connections

The composition and entry sequence of the data words is
identical to that of the NJ8820 except that the data is
transm itted serially.

Once again, there is no need to transfer all the words every
time provided that WORD 1 is always sent last.

CLOCK

DATA

STROBE

Fig. 12 Serial data timing

REFERENCES
1.

"Design Compromise in Single Loop Frequency Synthesisers" P.E. Chadwick, RF Design Expo, Anaheim,
Ca. Jan 1985

Frequency Synthesisers, Theory and Design, V. Manassewitsch, Wiley, 1980, ISBN 0-471-07917-0

Digital PLL Frequency Synthesisers, U.L. Rohde, Prentice Hall, 1983, ISBN 0-13-214239-2

Phaselock Techniques, F.M. Gardner, Wiley 1979, ISBN 0-471-04294-3

312

A Serially Programmable
VHF Frequency Synthesiser_ _ _ _ _ _ _ _ __
This demonstration circuit uses three Plessey Devices - the NJ8822 single chip synthesiser, the SP8793 dual-modulus
prescaler and the SL562 low noise op-amp in the configuration shown in Fig.1. The NJ8822 is programmed via a serial
microprocessor interface.
The VCO is a FJET oscillator using a transmission line as
The output spectra at 12.SkHz reference frequency is
the resonator. This VCO is modulated by applying the audio
shown in Fig.2, and Fig.3 is a graph of modulating frequency
signal to the cathode of a reversed biased PIN diode as
against percentage distortion at several values of deviation.
The circuit performs normally at a supply voltage of
shown in the circuit diagram. The loop filter uses the SLS62
which with the values shown has a loop bandwidth of 60Hz
5V ± O.SV and within a temperature range of -30°C to
and a damping factor of 0.6. This fHter is followed by a low
+ 70 ° C. the only observable effect of varying the
pass pole at 3.7kHz to attenuate the 12.SkHz reference
temperature was a frequency drift of 3kHz between the
sidebands. The lock up time for a 1MHz change in frequency
temperature extremes due to the uncompensated reference
is 80ms (determined empirically). The output frequency
oscillator.
range is 144-146MHz and the level is +3dBm into SOO.

r-~----------------~------------------------~~~----~----------~~-----o+5V

4.711H

lOOn

@---I rc:::::::r-;
MODULATION

~
lOd.

BB109B

105mm

n"rl;;

~=2=.7=kJ--."'<:S
4.7/lH

~~~~~~~~rlT.---Ul

111~GND

100

;J;,lOOn

r+-t---1>-ft--1--II---t----i@VeOOUT
4.7/lH
11

4.7P

SOLID 75Q COAX

Fig.1 NJ8822 serially programmable VHF synthesiser

313

(a) Unmodulated 10kHz span

(b) Unmodulated 100kHz span

(d) Modulated 1kHz 5kHz deviation 50kHz span

Fig.2 NJ8822 frequency synthesiser spectral performance

-LOOP GOES UNSTAB~
BELOW 200Hz

I I 1111111

_LOOP GOES UNSTABLE
I BfLPr'1 ~'!'1~z
\
LOOP GOES UNSTABLE
BELOW 10OH

i'--.

-" -i-"Wi
10Hz

100Hz

1kHz

10kHz

Fig.3 Graph of distortion against modulating frequency at
various deviations for the NJ8822 VHF frequency synthesiser

314

Design Compromises in
Single Loop Frequency Synthesisers _ _ _ _ _ __
The single loop frequency syntheslser is Justly popular as an approach to frequency synthesis. It has the merit of simplicity,
and because of this, low cost, especially as a large amount of the circuitry Is easily produced In monolithic Integrated circuit form.
Certain performance parameters of the synthesiser are
defined by the equipment performance. For example, a
marine VHF radio frequency synthesiser has requirements
for phase noise and discrete spurious outputs defined by the
adjacent channel specification, and the phase noise
performance may well need to be several dB better than
would at first be expected. If the adjacent channel rejection is
70dB for example, then a single sideband phase noise level in
the receiver bandwidth must be more than 70dB, see Fig.1.ln
fact, the translated noise level should be reduced by an
amount dependent upon the performance of other areas of
the equipment and these specification levels are typically
determined by the system architect. Frequently, however,
during deSign of a project, some modifications in
architecture become apparent, but an understanding of
practical limitations is vital at an early stage if delay and
Fig.3 Use of a fixed prescaler
consequent expense is to be avoided. For further details on
the effects of phase noise on receiver performance, see
Ref.1.

~'.

L I--~
p~l

Unwanted

vco

AdJacent
Channel Signal

~~~G--~

~~ ~ ~ I
----~

rodS

Frequency

Fig.1 Phase noise and adjacent channel rejection

Fig.2 Simple PLL

DIVIDERS
Single loop synthesisers using direct division as in Fig.2
suffer frOm certain limitations. Fully programmable dividers
are not generally available for frequencies above about
50MHz without high power consumptions, and even CMOS
dividers currently available are limited in applications at low
(5V) supply voltages and extreme temperatures. Newer
devices are appearing, however, and experimental 250M Hz
operation has been observed.

Fig.4 Mixing in the loop

Early synthesisers used fixed prescalers to divide the VCO
down to a suitable frequency for the programmable counter
as in Fig.3, or used mixing techniques as in Fig.4. Indeed, a
large number of CB radios use the mixing technique, but this
system can suffer from spurious products unless carefully
designed in choice of frequencies, input levels and particular
mixers used, see Refs. 2,3,4 and 5. In addition, the large
variation in subsequent division ratio may give problems with
loop dynamiC performance.
A major area of conflict lies in the choice of reference
frequency. In synthesisers such as Fig.3, the output
frequency step size is M times, the reference frequency,
where M is the prescale ratio. In a system where every
channel is used, the problem is then that the reference
frequency has to be decreased by a factor of M, and as a
result, the bandwidth of the feedback loop must decrease.
The bandwidth and damping factor of the loop filter are
vitally important parameters in determining such loop
characteristics as lock up time as well as the phase noise
characteristics. (The effects of loop bandwidth on phase
noise will be discussed later.) In general, the widest possible
loop bandwidth is required to minimise lock up time and to
confer the greatest immunity to shock and vibration.
However, the loop bandwidth cannot be greater than the
reference frequency and so the use of a fixed prescaler is
obviously somewhat limited. The alternative is the widely
used 'Two Modulus' or 'Pulse Swallowing' prescaler system,
illustrated in Fig.5. In this method, the prescaler is able to
divide by two Integers Nand N + 1. The two counters A and

315

M are programmable and are clocked in parallel, the divider
being set initially to the N + 1 ratio. When the A counter is
full, the divider is set to divide by N until the M counter is full,
giving a total division ratio of MN + A. This system is limited
to a minimum division ratio of N 2 - N if every value of N is to
be achieved (no 'skipped' channels) and the M counter must
always be programmed to a bigger number than the A
counter. Within these limitations, however,a fully
programmable divider is achieved and so frolcan now equal
the channel spacing.

equipments are by now obsolete in design and extremely
expensive to manufacture. Nevertheless, the lessons of
tolerancing delays necessary in such designs should not be
forgotten just because the majority of circuitry is now hidden
inside a block of silicon.
The choice of prescaler ratio is governed by a number of
factors. Discussed so far have been minimum ratio and loop
delay. However, the output frequency of the divider must be
low enough for the A and M counters to function.
Summarising

fin ~ N 'max control
where N is the divider ratio
fmax control is control circuit maximum operating
frequency.

fmin:;;;

N
total loop delay

Output

Pmln

= N2 -

where Pmln is the minimum divide ratio.
N is the dual modulus divider ratio.

Fig.5 Two modulus divider

Another and more subtle limitation is in the delay times of
the various components within the loop. When the circuit
(Fig.5) has counted down so that the M counter has been
filled, the whole system is reset, and quite obviously, must
achieve this in a time equal to N + 1 cycles of the input
frequency e.g. in a +64/65 prescaler, at 1GHz, the reset of
the M and A counters must be achieved in 65 cycles or in this
case, 65ns. This means that the propagation delays plus set
up/release times plus reset delays must not exceed 65ns and
it is this area where trouble can often be expected, especially
at temperature extremes. Although a 1GHz synthesiser with
a 64/65 divider only sees an input frequency of 15MHz for
1GHz input, the set up/release time and delays may well
easily reach 85-90ns and the system will thus fail.
If the propagation through the divider =td
the set up time = ts
the release time = tf
the propagation delay through theA and M counters = tc
then
fmax

(td

+ ts + tc)

(td

+ tf + tc)

whichever is least.
One of the areas in which an increase in loop delay time
can inadvertently occur is if the A and M counters trigger
from a different edge to the dual modulus prescaler. This can
cause a major diminution in available loop delay, as can an
attempt to physically separate the divider and control
circuits. Other deleterious affects have been noted, such as
radiation of the divider output to the VCO, producing high
frequency sidebands, so practical synthesisers are best
produced with little physical spacing between divider and
control circuit.
The control circuit is a practical device in a number of
technologies, although modern devices exclusively use
CMOS to minimise power consumption. Prescalers are still
mainly exemplified by bipolar technology, advances in
which have seen major reductions in power consumptions in
recent years - for example from 65mA at 5V for a divide by
10/11 operating at 250M Hz in 1976 to 4mA at 5V for a divide
by 40/41 operating at 225MHz today. Some equipments still
build up theA and M counters from discrete ICs and then add
phase detectors, reset circuitry and so on, but such

316

Various values for N exist in proprietary devices. These
range from 3/4 to 128/129: binary values (32/33, 64/65,
128/129) are popular for ease of programming from ROMs
and microprocessors, while decimal and BCD are used for
thumbwheel switch programming.
Programming is a straightforward exercise for binary
division and the following method is recommended.
1. The A counter should contain

x bits such that

2' = N
2. If more bits are included in the A counter, these should
be programmed to zero.
e.g.
N = 64 = 6 bits
A = 10 bits
then the 4 MSB are programmed to zero.

3. The M and A counters are treated as being combined so
that the MSB of the M counteris the MSB ofthetotal and LSB
of the A counter is the LSB of the total.
e.g.
A synthesiser operating from 43O-440MHz in 25kHz steps
uses a 64/65 divider, and the control circuit uses binary
counters.
P = f/freland frel = channel spacing = 25kHz
Pmin = 430/0.025 = 17200
Pmax = 440/0.025 = 17600
Minimum possible divide ratio is N2 - N = 4032
where N is two modulus divider ratio
Maximum allowable loop delay = 440:\06 ='145ns
Total divide ratio, P, is given by
P = NM +A
N = 64, as a 64/65 divider is used
Pmin from above is 17200
Therefore 17200 = 64M + A
And M;;'A
17200
LetA =OThenMmin =Ei4""" = 268.75
= 268
17600
and M max = ~ = 275.0
Thus the M counter must be programmable from 268 to 275
as required: the M counter must have at least 9 bits.

For a frequency of 433.975MHz
P = 433.97/0.025 = 17359

therefore

17:9

= 271.2343

The A counter is programmed for the remainder i.e.
0.2343 x 64 = 15
From this, the A counter is programmed to 15 and the N
counter to 271. The output frequency can now be checked.
P = NM +A
= 271 x 64 + 15 = 17359
and this is the required divider ratio.

The two modulus prescaler is therefore able to offer the
advantages. of producing a programmable divider operating
at a very high frequency, but consuming a fraction of the
power of such a divider. This enables the reference
frequency to equal the channel spacing, thus allowing
maximisation of loop bandwidth with its concomitant faster
lock up time. It is limited by total loop delay, maximum
operating frequencies of dividers and counters, and in
minimum count values, but is nevertheless a powerful tool
for the synthesiser designer.
The limitation on the value of Pmin, the minimum ratio can
be avoided by the use of three and four modulus dividers.
The use of a four modulus counter allows a very wide
frequency range to be covered with one device, but at the
expense of a much higher power dissipation. Typical of such
devices are the Plessey SPB901 and SPB906. Power
consumptions for 2-modulus dividers typically range from
4mA at 200M Hz (Plessey SPB792/3) through 11mA at
520MHz (Plessey SPB716/B/9) to 25mA at 1GHz (Plessey
SPB703).

LOOP BANDWIDTH AND PHASE NOISE
As stated earlier, phase noise is a very important parameter
in frequency synthesisers. Too many early synthesisers
suffered from phase noise problems which manifested
themselves as poor equipment performance in such areas as
multiple signal selectivity and ultimate signal to nOise ratio.
The performance of the synthesiser may be degraded or
improved by changing the loop bandwidth, depending upon
the characteristics and parameters involved.
The general characteristics of a phase locked loop (PLL)
are that for signals injected into the loop it acts as a low pass
filter for signals inside the loop bandwidth, and as a high pass
filter for signals outside the loop bandwidth. To analyse the
performance, consider modulation of the VCO at very low
frequencies. The output of the phase detector will be a low
frequency signal of phase such as to attempt to remove the
modulation imposed on the VCO. As the modulation
frequency increases, the error component of the phase
detector output is not passed by the loop filter, and so the
modulation is not removed by the loop. Note that the
modulation is phase modulation (PM) up to the filter break
point, and frequency modulation (FM) thereafter. In the 'inbetween' range, some interesting distortion effects can
occur, especially when excessive group delay exists in the
loop filter.
The relationship of loop filter bandwidth to phase noise is
now apparent. Phase noise from the oscillator
corresponding to frequencies below the filter bandwidth will
be removed by the loop, while phase noise components
outside the loop bandwidth will be unaffected by the loop.
Under these circumstances then, the VCO output spectrum
will be cleaned up by the loop. However, for frequencies
inside the loop bandwidth, other factors enter. Variations in

the reference frequency cause variations in output frequency
from the synthesiser, and phase noise components at the
reference frequency are purely the frequency domain
transforms of time domain frequency instability (Refs. 6,7
and B). These phase noise effects are multiplied in the loop
by the divider ratio. An example (admittedly using gross
instability for demonstration) is shown.
If the 430MHz synthesiser has an instability of +1 Hz in the
25kHz reference frequency, this is multiplied by P.
i.e. for operation at 433MHz
P = 433/0.025 = 17320
Therefore IF +1Hz at 25kHz gives +17.32kHz at final
frequency.
Phase noise at the reference frequency is derived from two
sources:
(a) the system standard oscillator
(b) the reference chain divider
Oscillators for standards are available with very low phase
noise characteristics, and -130 to -170dBc/Hz at 1kHz offset
covers the usual range. This phase noise is modified by the
reference divider and multiplied by the division ratio as
explained above. Of course, phase noise at any offset is
reduced by division until the phase noise floor of the divider
is reached. Little has been published on the causes of phase
noise in dividers, although various measurements have been
made (Ref. 9). It has been suggested that TTL and CMOS
dividers are better than ECL .and CMOS is better at low (1020Hz) offsets. At a 1kHz offset, ECL levels of about -155 to
-165dBc/Hz appear usual. The explanations for the
occurence of phase noise is intuitively regarded as being
jitter in the transition point of the signal: on this basis, one
would not expect CMOS to be so good as TIL insofar as the
rise and fall times will be somewhat slower. Regrettably, the
difficulty and cost of making meaningful measurements is an
inhibiting factor: data on the phase noise performance of
Gallium Arsenide dividers would be of considerable interest
espeCially at small frequency offsets.
'
From the above discussion, a phase noise floor of some
-150dBc/Hz can be expected at the end of the reference
frequency divider chain if a good frequency standard is used
while a low cost one maywelJ beatabout-130dBc/Hz.lnou;
430MHz synthesiser, a degradation at 1kHz (if the loop is
wide enough) of some 84dB will be seen, so inside the loop
bandwidth, the noise performance will be limited to -130 +
84 = -46dBc/Hz. At lower offset frequencies, the phase
noise of dividers and frequency standards is worse, so the
phase noise performance is now being defined by the loop,
rather than the VCO. These are worst case figures, but the
ultimate signal to noise ratio of an FM receiver can clearly be
seen to be easily limited at UHF by multiplied phase noise.
Fortunately, the noise enhancement by the loop is such that
pre-emphasis of the modulation provides major
improvements in signal to noise ratio.
Nevertheless, it is obvious that the choice of loop
bandwidth is compromised by the ultimate signal to noise
level required by the system and that such factors as
reference oscillator noise level and divider noise cannot be
totally disregarded. Operation in the usual cellular radio
bands at BOO or 900MHz makes the situation some 6dB worse
than that analysed above and the use of a psophometric
audio weighting in the equipment is advisable. Sub audible
tones may well need fairly high deviation if signal to noise
performance is not to be severely limited on them, although
modern decoders will work with a negative signal to noise
ratio (Ref.10).
In the single loop synthesiser, the phase noise in adjacent
channels, which determines the adjacent channel
performance, is, to a first order, unaffected by the loop and its
parameters. Second order effects such as noise modulation

317

by such loop components as high value resistors and
operational amplifiers may be negated by the use of a passive
low pass filter prior to the veo. Phase noise in the oscillator
is discussed below.
Even where the effects of multiplied phase noise may be
ignored, such as where the reference divider chain noise is
sufficiently low, certain other problems occur in the loop
filter design. Many of these are associated with the phase
detector employed, which in many areas has been a digital
phase/frequency detector. Various types of detector have
been used over the years, from an OR gate producing a
variable mark space ratio to the well known 2 D type detector.
The first of these used integration of the variable mark-space
ratio to produce the required output, while the latter (Fig.6)
produces minimal width pulses on both CIlu andCllD when in
the zero phase error condition. Unfortunately, the zero phase
error state exists for a degree of phase error dependent upon
the propagation of the gates and a phase error/output
voltage characteristic such as Fig.7 is achieved. The
performance in the central flat portion of the characteristic
means that the loop gain falls to zero when the phase error
reaches some small but finite value, and this leads to an
increase in the low frequency phase noise of the loop. This
phenomenon is of course related to the reference frequency
of the loop, being worse at high comparison frequencies.

819""11---'1'"

81gnal2

Fig.6 Dual D type phase discriminator

wider loop bandwidth for the same comparison frequency
sideband rejection, or increased rejection, or to some extent,
both. The analog phase detector may easily be given a very
high gain and narrow range of operation - say a 2 degree
range with a gain of 600 volts/radians, but only a limited lock
range. It is however, essential to ensure that saturation of this
detector, and indeed of the loop filter/amplifier is minimised,
as under channel change conditions, the control line and
thus the filter amplifiers can be driven hard into saturation. A
long recovery time here may well make a mockery of any
lock up time calculations. It is this approach which has been
adopted in the NJ8820 series of eM OS control circuits from
Plessey with a large degree of success.
The choice of loop bandwidth is also governed by the time
to change channel, and here again, compromise is often
necessary. For example, a lock up time of 1ms and a loop
bandwidth of 100Hz are apparently mutually incompatible.
By using the two detector approach outlined above however,
the loop bandwidth for the digital detector may be made
much wider than the analogue detector, thus providing a
form of adaptive filtering. The basic loop equation for a type 2
2nd order loop is
Wn

~ KoKv
Ntl

where Wn = loop natural frequency, Kv = veo gain in
Rad/S-v, K 0 = phase detector gain in volts/rad, N = division
ratio and t1 = integrator time constant. shows the
dependence of Wn, the loop natural frequency on N. It
should be noted the 3dB bandwidth of the loop and the
natural frequency W n, are not identical - except for a
damping factor, D = 3.02.
It was stated earlier that noise caused by the phase
detector and loop filter is easily filtered to avoid noise in
adjacent channels and the use of low-noise components in
loop filters (NOT a 741!) is advisable. Where possible, time
constants should use large capacitors and small resistors to
minimise KTBR noise. 1/f noise can be a problem with
operational amplifiers, and where loop bandwidth is high,
slew rate is important if the dynamic loop bandwidth is to
beary any relationship to the small signal case.
To summarise, the choice of loop bandwidth affects close
in phase noise and lock up time. Phase noise is produced by
dividers, phase detectors and filters, and when multiplication
ratios are high, the reference frequency phase noise can be
dominant when multiplied. To minimise this effect, the loop
bandwidth can be narrowed, since noise outside the loop
bandwidth is determined soley by the veo. Typical divider
phase noises of-1500r-160dBc/Hz can be expected, solow
cost reference oscillators can dominate the noise
performance.

VOLTAGE CONTROLLED OSCILLATORS

Fig.7 Transfer characteristic. of phase discriminator with
a charge pump

Although a number of approaches have been made to
minimise this problem, including the provision of a leakage
path across the veo control line (Ref. 16), the better
approach is to use a linear phase detector of high gain to 'fill
in' the gap in the response. An additional benefit of this
method is that if the digital phase detector has a 'tri-state'
output for the area in which the dead zone occurs and the
linear phase detector operates, then the phase detector
output at comparison frequency is reduced, allowing either a

318

Many engineers consider veo design to be a black art,
and although some art is occasionally involved, veos are
amenable to analysis.
In the single loop synthesiser, the phase noise
performance outside the loop bandwidth is dominated by the
veo, with the noise generation by passive components in
the loop filter generally being of lesser importance.
Scherer, Leeson (Ref.12) and Robins (Ref.13) have
analysed oscillator phase noise performance and Scherer
(Ref.14) has demonstrated the applicability of Leeson's
equations and uses the equation

L(I)

= Va

[

FkT] (fo)2

Po] 2 Eq. 1

Po Ttl Q + V.CV227Tf.

where L (f) is the SSB phase noise at an offset F
F isthe Noise Figureoftheamplifierintheoscillator
k
is Boltzmann's Constant
T is the Temperature
Ps is the available signal power
f 0 is operating frequency
f
is the offset at which the poweristobecalculated
o is working 0 of the tuned circuit
C is tank capacity
V is tank current peak voltage
Po is rf output power
By inspection of Eq. 1, it may be seen that the phase noise
is proportional to 0- 2 and also to (frequency offseW2. This
means that for each octave decrease in the offset frequency,
the noise power will increase by 4 times or at 6dB/octave. As
the frequency offset decreases 1/f or flicker noise becomes
important: this 'break' frequency can be as high as 50MHz
with GaAs devices. From Eq. 1, it may be determined that a
low phase noise oscillator will have a large voltage swing, a
high working 0 and provide little output power to the load.
There is of course a limit as to the level of power required, as
the noise of any subsequent buffer amplifiers will degrade
the oscillator.
A major compromise in the design of equipment is the
choice of VCO frequency. If, for example, a 800M Hz cellular
radio type of receiver is considered, some fairly
straightforward calculations will serve to act as a guide.
Starting with the receiver parameters, we will assume that a
70dB rejection of a signal two channels (60kHz) away is
required. A numbr of receiver sub system parameters are
involved.
(a)
(b)
(c)
(d)

Synthesiser phase noise
IF filter performance
Co-channel rejection ratio
Gain compression of stages before the main IF
selectivity.

Of these parameters, (c) is the least obvious in its
applicability. Ref.1 showed how oscillator noise was mixed
onto a wanted signal by a strong unwanted signal. The
degradation of a wanted signal by this noise obviously
depends upon the relative levels of signal and noise, and
because the noise is on the same frequency, the Co-channel
rejection. Typically, this means that a noise level within the IF
passband of some 8dB less than the signal is required. Thus
for the 70dB rejection, oscillator noise at - 78dB is required,
and 80dB would thus be the design aim.
Conversion of this level to dBc/Hz is not straightforward
because of the non linear slope of the phase noise. However,
for narrow bandwidths at large offsets, little error is obtained
by approximating the phase noise slope to a straight line.
This may be illustrated as follows:
From Eq. 1, the power spectrum at an offset beyond the
flicker noise knee is given by:

Po = Kf-2
where P
K
f

fU(Kf-2df = fu
fLJ'
fL
K (fL-1 - fu-1)

Therefore

p,
(fL -1

fu-1)

K =

10 3

1
= 2.58 X 10-3
67.5 x 103J

Kf-?

2.58
(53.5

X
X

10-3 _
-15
103)2 - 0.901 x 10

= -120.5dBc/Hz

At 60kHz

P = -121.4dBc/Hz
and at 67.5kHz

P = -122.5dBc/Hz
If the 'break point' for 1/f noise is above 60kHz, then the
spectral density is determined by noise rising at f 3. Similar
procedures are followed:

Po = K'f- 3
fu
fu
fo'f--.J df = -K'

-K'

[

f;2

]

(fu-? - fL-2)

K'
="2
(fc 2 -

fu"'2)

Using similar figures, the performance required is:
53.5kHz
60.0kHz
67.5kHz

-120.OdBc/Hz
-121.5dBc/Hz
-123.OdBc/Hz

The error by assuming a linear relationship is given by:
IF bandwidth = 15kHz
therefore noise power is 10 log 1015 x 103dB greater than in a
1Hz bandwidth
which is 41.8dB
therefore if the noise power is 80dB down on the signal,
total carrier to noise power ratio is -121.8dSc/Hz at 60kHz.
This in fact gives a requirement some O.4dS higher than
previously calculated and in 120dS is obviously negligible.
Having decided upon the level of allowable oscillator
noise, it is now possible to calculate the best methods of
achieving this level. Using Scherer's figures from Ref.13 for a
400MHz oscillator which will be doubled, using parameters
of:

FKT

[-Kf-1]

L53.5

so at 53.5kHz

the noise

flower and f upper,

10-8

= -80dB

To find the phase noise in a 1Hz bandwidth at an offset f

is the noise power
is a constant
is the offset

For a frequency band bounded by
power is:

p, has been defined as the phase noise in the band
therefore

= 200
23pF

=
= 10V ~k
=
[6nV 2
W-

where 6nV is the noise voltage and 1V is
the input before limiting.

The noise power P at a 30kHz offset is, from Eq. 1,
-135d Bc/Hz.
So far flicker noise has been ignored. Flicker noise is a low
frequency phenomonen which causes problems by
intermodulation with the carrier frequency to produce noise
sidebands. The 'break point' at which flicker noise becomes
dominant varies but a UHF VCO of the type under
consideration would probably have a break point at about
50-150kHz offset from the carrier. Eq. 1 needs some

319

modification to include this factor and a multiplicand of
(1

+ fe)

--fmay be used, where fe is the 1/f noise corner frequency.
The previously calculated noise will now be degraded by
about 8dB under these conditions, (assuming f. = 150kHz)
and will now be -127dBc/Hz. This is about 5dB inside the
previously calculated requirement. Note that calculations
have been made on the basis of a 30kHz offset to allow for
doubling the oscillator frequency.
Considering an oscillator with a fundamental frequency of
800M Hz, a number of problems appear. Ignoring for the time
being the increased noise figure olthe device, the available Q
of components is considerably less - for example high
quality chip capacitors can offer Q's of about 200, leading to
working Q of about 100. Calculating noise levels for a 80kHz
offset with all other parameters constant except tank
capacity which is 12pF (half the 400MHz oscillator) the noise
at 80kHz is -105dBc/Hz or about 17dB outside the
requirement. Obviously, these figures are no more than a
guide, but the suggestion is that the doubled 400MHz
oscillator will meet requirements, while the 800M Hz
oscillator will not (see Fig.8).

transmission line can provide an oscillator tuneable from 130
to 190MHz with a coarse tuning trimmer, and electrically
tuneable over 6MHz at the bottom of the band to 8.75MHz at
the top, thus maintaining Wn sensibly constant. The use of
PIN diodes to switch capacitors is possible, although care
must be taken not to degrade Q e.g. a 10pF capacitor at
150MHz has Xc = 1060. A PIN diode with an ON resistance
of 0.50 will give QMAX = 212, assuming a perfect capacitor,
and as considered earlier, this can have disastrous effects on
phase noise performance.

Fig.9 Transmission line VCO using the line as an
impedance inverter
Controller

1...-

fret

Fig.S Use of a lower frequency oscillator for improved
phase noise

Flicker noise can be reduced by the inclusion of local DC
negative feedback, such as an un bypassed emitter resistor,
but a major requirement is to choose a suitable device. In
general a low phase noise oscillator will run at high power,
using a device with both low flicker noise and low high
frequency noise, and with high gain and minimum damping
on the tuned circuit. In fact, in many applications, the
thermionic tube is attractive! Q should be as high as possible,
and where VCOs are concerned, the MHzIV should be
minimised. This is because of the effects of noise - at
10MHzIV, 1 microvolt of noise will produce 10Hz of FM
deviation.
Where relatively wide frequency ranges are concerned, the
variation in loop bandwidth may cause problems.
Wn

where

K0
Kv
N
t1

= ~ KoKv
Nt1

= natural

loop frequency
= VCO constant
= phase detector constant
= divider ratio
= integrator time constant

W n varies with N, and where desirable to maintain equal lock
up times and loop bandwidth, Kv may be deSigned to vary
with N. Several methods exist, but the use of a transmission
line VCO can prove useful, as the effective inductance
increases with frequency. The use of a suitable length of

320

An initially attractive method of realising the transmission
line VCO is shown in Fig.9, where a length of line is used as a
reactance inverter, changing the capacity into an
inductance. The use of a Smith Chart will, however, show
that the resulting inductance will have a low reactance unless
the terminating capaCitor is large and the line relatively long
(greater than 1Ia wavelength). This leads to a low Q circuit as
the resistance of the line is constant, and measurements
made using a 16cm rigid coax 750 line with a loss of
4dB/100ft at 150MHz gave a Q ofless than 100. This line was
terminated with an air spaced trimmer. The same line as a
shortened capacitively loaded resonator as in Fig.10 had a Q
of over 250.

Fig.10 Transmission line VCO using a shortened Jo./4 line
capacitive/y loaded

SUMMARY
The compromises in the synthesiser design are now
apparent: a narrow bandwidth is required to minimise
multiplied reference noise, but a wide bandwidth is needed
to minimise lock up time. A high oscillator frequency may be
required to avoid spurious outputs and multiplier chains,
while a low frequency and multiplier chain give the best
performance on system phase noise and possibly power
consumption. The classical way to minimise these problems
is the two loop synthesiser, but cost is a determining factor
effecting the compromise finally reached. Power
consumption is always a problem and unfortunately is more
demanding at high frequencies while increasing channel
occupancy will lead to ever tighter performance
requirements in terms of phase noise and switching time.
Modern integrated circuits help the designer by providing
better phase detectors and faster lower power dividers.
Nevertheless, the single loop synthesiser has been shown to
involve a number of compromises in its design, and in some
cases, these compromises may limit the final equipment
performance level. The single loop synthesiser is very useful,
but is not universally applicable.

REFERENCES
1.

Dynamic Range, Intermodulation and Phase Noise,
P.E. Chadwick, Radio Communication March 1984,
pp223-228

Phase Noise in Signal Sources. W.P. Robins,
Peter Peregrinus Ltd., London 1982 ISBN 0906048761
pp173-202

The SL6440 High Performance Integrated Circuit Mixer
P.E. Chadwick, Wescon 1981, Session 24 Record,
entitled "Mixers for High Performance Radio".
Published by Electronic Conventions Inc.,
999 N. Sepulveda Blvd, EI Segundo, CA 90245

Digital PLL Frequency Synthesisers,Theoryand Design,
Ulrich L. Rohde, pub Prentice Hall, 1983.
ISBN 0 1322142392 pp86-87

High Performance Integrated Circuit Mixers,
P.E. Chadwick, RF Design, June 1980 pp20-23.

High Performance Integrated Circuit Mixers,
P.E. Chadwick, Clerk Maxwell Commemorative
Conference on Radio Receivers and Associated
Systems, Leeds 1981 (I.E.R.E. Conference Publication
No. 50, ISBN 0903748452)

Frequency Synthesisers, Theory and Design,
2nd Edition, Vadim Manassevitsch, Wiley, 1980,
ISBN 0 471 07917 O.

Characterisation of Frequency Stability: A Transfer
Function Approach and its Application to measure via
Filtering of Phase Noise, J. Rutman, Trans. IEEE on
Instrumentation and Measurement, Vol. 22 (1974)
pp40-48

Phase Noise Measurement using a High Resolution
Counter with On Line Data Processing, Peregrine,
Ricci. Proc 30th Annual Symposium on Frequency
Control, U.S. Army Electronics Command Ft.
Monmouth N.J. 1976

10. State of the Art Signalling Devices for Mobile Radio
Systems - Selective Call, Tone Squelch and Digital
Signalling, L.G. Litwin, Proceedings Communications
84, lEE Conference. Publication No. 235,
ISBN 085296292 4, 1984
11. AN1006, A VHF Synthesiser using the SP8906 and
NJ8811, Plessey Semiconductors Ltd., Swindon,
England
12. A Simple Model of a Feedback Oscillator Noise
Spectrum, D.B. Leeson, Proc IEEE Vol. 54,
February 1966
13. Phase Noise in Signal Sources, W.P. Robins pp47etseq
14. Learn About Low Noise Design, Dieter Scherer
Microwaves, April 1979 pp 116-122 May 1979 pp72-77

321

The care and feeding of High Speed Dividers _ _ __
Circuit design and layout for high speed dividers operating at fraquencles up to 2GHz owe much more to analog RF design
techniques than normal digital ones and the limitations on flexibility and component choice Inherent In UHF RF design are of
paramount Importance In successful designs.

PRACTICAL DESIGN CONSIDERATIONS
High speed divider applications require the printed circuit
boards to be mechanically designed with two considerations
in mind:
(1) Electrical performance
(2) Mechanical and thermal performance.
These two considerations are inter-related; for example,
the use of 1/16 inch thick fibreglass PC board may be
desirable mechanically, but a son stripline on this thickness
of board is about S/32 inch wide, and is thus too wide to pass
between the pins of an IC.
Most of the heat conducted from a dual-in-line IC package
is removed from the bottom of the package. less than 10% is
conducted out by the leads, and because of the cavity
between the chip and lid, relatively little through the top of
the package.
For this reason, the use of a double-layer PC board layout
is recommended, with a groLind plane top surface. Where
1/32 inch thick material is used, a top surface ground plane
will add substantially to the heat dissipation capabilities of
the board.
For use at very high frequencies, consideration must be
given to the type of component used. Carbon composition
resistors are more nearly resistive at high frequencies than
either carbon or metal film types, and are available in very
small sizes. Bypass capacitors need to be chosen carefully if
they are to act as low impedances, as series inductance leads
to an increasing impedance with frequency above the series
resonant frequency of the device. As a guide, a 1000pF disc
ceramic capacitor with 1/4 inch leads will be self resonant at
about 7SMHz, and will appear as an inductive impedance of
about 22n at 800MHz. The use of chip capacitors is
recommended above SOOMHz, although leaded monolithic
ceramic capacitors with suitably short leads are often
acceptable.
The use of a ground plane for RF decoupling purposes is
often recommended, and can be helpful. However, the
danger is that the ground current paths in the plane are not
defined very well, and because of this lack of definition, the
ground plane can cause unsatisfactory operation. Probably
the best method is to return all the bypass capacitors to a
single point (as in Fig.1) and return this pOint to the ground
plane.

Also note that in Fig.1 the output load resistors have their
grounded ends connected together and a common return
used. Because the currents in the resistors are in antiphase,
cancellation of the inductive effects taken place, and the path
followed by the relatively large output currents is controlled.
Defining the ground current path is more important in
applications like frequency synthesis, where a relatively
large part of the system may be on one PCB.
It is well known that the effect of mismatching a
transmission line is to cause variations in the voltage along
the line. Standard practice at Plessey Semiconductors has
been to use a S:1 attenuator manufactured from 'microdot'
resistors as an attenuator feeding a son sampling
oscilloscope or a power meter. Although a high vswFi will
exist on the line from the generator to the test fixture, the
theory is that the line from the power meter to the attenuator
will be a matched line, and so the power measured is 14dB
lower than the power at the device input pin. This method has
been proved very successful, even if Simple, and offers some
advantages over the use of hybrids or directional couplers.
The use of a matched son system can help, and using
microstrip techniques, a track with a defined impedance is
reasonably practical. The impedance of a microstrip line is
given by:

Zo = 377 (Llw) (1/cr)

Where L
dielectric thickness, W
width of track and cr is
the relative permeability of the board material.
Some correction factor's have to be applied, and typically,
on 1/16 inch glass fibre epoxy board, the following sizes
provide a guide to track width
100n -1mm
7Sn - 2mm
son - 4mm
These impedances rely on the ground plane on the
obverse of the board being complete, and where boards are
wave soldered, it may be necessary to make arrangements to
prevent blistering.
100Dr---~-----r----~----~--~r---~

BIAS DECOUPLING PIN

.,-/ PLATED THROUGH
HOLE TO
GROUND PLANE

200~.-~-----+----~----+---~r---~

200

400

600

800

1000

FREQUENCY (MHz)

Fig.2 Example of input sensitivity curves

EClOUTPUT
Rl

lOAD RESISTOR, lCC

lEADlESS CHIP CAPACITOR

Fig.1 Single point grounding

322

The input level of a divider should be maintained within the
guaranteed operating window shown on its data sheet
(Fig.2). Excessive input can vary in its effects, from causing
permanent damage to miscounting, especially when cold.
Running the device at too Iowa level can cause problems,
even though the level is within the 'typical' performance line
of the device. An ECl output Signal on pin 6 of the device in

Fig.3 can couple 60mV of signal to the input shown on Fig.2
at SOOMHz. Such a level of coupling can lead to divider jitter if
the input signal is low, and it becomes very necessary to keep
the inputs and outputs well separated at the higher
frequencies. This includes ECl lines to modulus control pins
on two modulus dividers.

CMOS outputs are, on the face of it, TTl-compatible.
However, investigation will show that the outputs are not
guaranteed to meet TTL levels at TTL currents and it is not
recommended that CMOS output devices be used to directly
drive TTL. Where an interface of this sort is required, an
active transistor interface should be used.
Fig.4 shows a circuit for an ECl-TTl interface, using a line
receiver. Simple circuits using one or two transistors cannot
be guaranteed to work over all the tolerances of ECl output
voltages and temperature ranges.
Interfacing to dividers is not difficult if a few simple rules
are obeyed. These are:
(1) Observe the input requirements - guaranteed input
operating area, and slew rate.
(2) Do not use open collector outputs above 10MHz.
(3) Do not use CMOS outputs to drive TTL.
(4) Use a sensible layout with good components, and
sensible values - 0.1 microfarad ceramic capacitors are NOT
bypasses at 1.SGHz.
Treating dividers as RF linear devices is probably the best
way to ensure successful applications at high frequencies.
There is no magic in HF deSign, only intelligent layout and
sensible component choice.

Fig.3 Coupling between parallel tracks

Most dividers are edge triggered, and although they are
specified over a frequency range with sine wave input, they
will operate to lower frequencies provided a suitably high
slew rate is provided on the input signal. This is generally of
the order of 100 to 200 volts/microsecond. This should be
achieved by shaping of the input signal, for example by
limiting, rather than by overdriving the device.
The outputs of devices may be of the following forms:
(1)
(2)
(3)
(4)

ECl
Open collector TTL
TTL
CMOS

Of these, the ECl output is well defined; some devices
require external load resistors and the data sheet should be
consulted. Where these external resistors are required,
suitable interconnection techniques should be used
between them and the device; the resistors should be
carefully chosen for their non-inductive properties when
output frequencies are very high. Where an ECl output
divider drives another divider it is best to AC couple, since
few dividers are strictly ECl-compatible on their inpl..!ts.
Open collector TTL outputs are relatively slow. Although
the negative edge is limited in speed by the turn-on time of
the output transistor, the rising edge is limited by the external
load resistor and capacitance to ground. In practice this
means that short narrow tracks are required to the following
device, and a minimum 'fan-in' load provided. In. addition,
open collector TTL should not be used above about 10MHz
output frequency.
True TTL outputs are not so limited, because of the active
pull-up. Nevertheless, the use of such outputs at frequencies
above about 25-30MHz is not recommended, especially into
capactive loads. loads of more than 30pF should not be
driven faster than about 1SMHz. Note that the current drawn
by true TTL outputs increases with increasing load
capacitance.

!lA710C COMPARATOR OR
!lA75107A LINE RECEIVER

Fig.4 ECL/TTL interface

Impedance Matching
The use of microstrip techniques has been mentioned
already. However, in itself this will not produce a matched
network and various possibilities exist to improve the
matching at the input of a device. These include Tchebycheff
impedance tran.sforming networks, narrow band 'l'
matching networks, and at high enough frequencies, the use
of transmission lines. Wideband matching is often difficult,
and attempts should be made to use networks that have the
lowest possible working Q. This is for two reasons: firstly a
high Q network will not only be narrow band, but will have
the capability of increasing the losses, and secondly, a low Q
network is generally more tolerant of component variations.
The greater losses in high Q circuits occur because of the
greater circulating current: the loss power is 12R, so that if the
Q is doubled with all else constant, the power loss is
increased by 4 times.
The easiest method of determining matching components
is by means of the Smith Chart.

THE SMITH CHART
The input impedance of SPSOOO-series high speed dividers
varies as a function of frequency and is therefore specified on
the datasheets by means of Smith Charts. The following
information is included in this handbook as a guide to their
interpretation and use.

323

Construction of the chart
The chart is constructed with two sets of ci rcles, one set
comprising circles of CONSTANT RESISTANCE (Fig. 5)
and the other circles of CONSTANT REACTANCE (Fig. 6).
The values on these circles are normalised to the
characteristic impedances of the system by dividing the
actual value of resistance or reactance by the characteristic
impedance e.g. in a 500 system, a resistance of 1000 is
normalised to a value of 2.0.
By combining Figs. 5 and 6 to form Fig. 7, a chart is
produced in which any normalised impedance has a unique
position on the chart, and the variation of this impedance
with frequency or other parameters may be plotted.

A further series of circles may be plotted on the chart:
these are circles of constant VSWR, and represent the degree
of mismatch in a system. The VSWR is the ratio of the device
impedance to the characteristic impedance, and is always
expressed as a ratio greater than 1: thusa250device in a 500
system gives rise to a 2:1 VSWR. These circles of constant
VSWR have been added in Fig. 7.
Any point can be represented on the Smith Chart: for
example an impedance of 150-1750 can be represented by a
normalised impedance (in a 50 0 system) of 3-j1.5 and this
point is plotted in Fig. 7 as point A.

Fig.5 Constant resistance circles

Fig.6 Constant reactance circles

Fig.7 The complete chart

324

Network calculations
The main application for Smith Charts with integrated
circuits is in the design of matching networks. Although
these can be calculated by use of the series to parallel (and
vice-versa) transforms, followed by the application of
Kirchoff's Laws, the method can be laborious. Although the
Smith Chart as a graphical method cannot necessarily
compete in terms of overall accuracy, it is nevertheless more
than adequate for the majority of problems, especially when
the errors inherent in practical components are taken into
account.
Any impedance can be represented at a fixed frequency by
a shunt conductance and susceptance (impedances as
series reactance and resistance in this context). By
transferring a pOint on the Smith Chart to a point at the same
diameter but 180" away, this transformation is automatically
made (see Fig. 8) where A and B are the series and parallel
equivalents.
It is often easier to change a series RC network to its
equivalent parallel network for calculation purposes. This is
because as a parallel network of admittances, a shunt
admittance can be directly added, rather than the tortuous
calculations necessary if the series form is used. Similar
arguments apply to parallel networks, so in general it is best
to deal with admittances for shunt components and
reactances for series components.
Admittances and impedances can be easily added on the
Smith Chart (see Fig. 9). Where a series inductance is to be
added to an admittance (i.e. parallel R and C), the admittance
should be turned into a series impedance by the method
outlined above and in Fig. 8. The series inductance can then
be added as in Fig. 9 (see also Fig. 10).
Point A is the starting admittance consisting of a shunt
capacitance and resistance. The equivalent capacitive
impedance is shown at pOint B. The addition of a series
inductor moves the impedance to point C. The value of this
inductor is defined by the length of the arc BC, and in Fig. 10
is -jO.S to j0.43 i.e. a total of jO.93. This reactance must of
course be denormalised before evaluation.
Point C
represents an inductive impedance which isequivalenttothe
admittance shown at Point D. The addition of shunt
reactance moves the input admittance to the centre of the
chart, and has a value of -j2.0. Point D should be chosen
such that it lies on unity impedance/conductance circle: thus
a locus of points for point C exists.
This procedure allows for design of the matching at any
one frequency. Wide band matching is more difficult and
other techniques are needed. Of these, one of the most
powerful is to absorb the reactance into a low pass filter form
of ladder network: if the values are suitably chosen, the
resulting input impedance is dependent upon the reflection
coefficient of the filter.
At frequencies above about 400MHz, it becomes practical
to use sections of transmission line to provide the necessary
reactances, and reference to one of the standard works on
the subject is recommended.

-J1.0

Fig.S Series reactance to parallel admittance conversion

]1.0

Fig.9 Effects of series and shunt reactance

325

Fig. 10 Matching design using the Smith Chart

326

PHASE NOISE AND DIVIDERS
Phase noise is becoming increasingly important in
systems and it is necessary to minimise its effects. First,
however, phase noise must be defined.
A spectrally pure signal of a given frequency would appear
on a perfect spectrum analyser display as a single straight
line as in Fig.11. If the signal is frequency modulated with a
discrete modulation frequency, the result will be a comb of
frequencies as in Fig.12, while modulation with noise will
produce an output spectrum as in Fig.13. Note that the noise
density decreases as the offset from the carrier increases.
This effect is the result of the effectively lower modulation
index m. In the case of a Voltage Controlled Oscillator
modulated by white noise, a similar effect will be seen,
because for a given deviation f, the modulation index m, ( =
1/fmod) is greater for lower frequencies than for higher
frequencies. Thus the number of sidebands is greater for
lower frequencies, and the noise spectral density increases
as the carrier is approached.
The causes of phase noise in dividers are not well
understood, but the effects of internal noise on the switching
point of the various flip-flops cannot be ignored. The 1/f

noise will obviously inter-relate to the phase noise ifthis is so,
and it is interesting to note that various measurements of
Gallium Arsenide dividers suggest performances 20 to 30dB
worse than for ECl dividers. Rohde (ref. 4) suggests that TTL
and CMOS are much better than ECl, although little work
has been published in this field, possibly because of the
measurement difficulties.
The non-saturating nature of ECl, the fact that the
transistors are designed and processed for high speed rather
than low noise, and the smaller signal swings than TTL or
CMOS, lead intuitively to the conclusion that ECl should be
worse than either of these other two logic families. This
appears to be the case, while the high 1/f noise knee of
Gallium Arsenide devices leads to the high relatively close in
phase noise.
Devices with slow output edges, such as open collector
TTL output stages may also be expected to be worse, which
is again born out in practice.
Minimisation of phase noise requires the use of wellfiltered supplies, correct input levels and minimisation of
noise in level changing circuitry.

5
11.

Fig.11 Spectrally pure signal

Fig. 12 Spectrally pure signal, frequency modulated
with single tone

Fig. 13 Spectrally pure signal, frequency modulated by noise

REFERENCES
1. Electronic Applications of the Smith Chart, Philip H. Smith, McGraw Hill, 1969.
2. Microwave Filters, Impedance - Matching Networks and Coupling Structures, Matthei, Young, Jones, Artech House 1980.
SBN 0890060991.
3. Tables of Chebyshev Impedance Transforming Networks of low Pass Filter Form, Matthei G.L., Proc IEEE August 1964
pp 939 - 963.
4. Digital Pll Frequency Synthesis Theory and Design V.L. Rohde, Prentice Hall 1983 ISBN 0-13-214239-2.

327

Universal Programmer for Plessey Synthesiser ICs _ _
The programmer described in this application note will provide the data required topragram any of the Plessey NJ8820 or
NJ88C30 series of Syntheslser ICs. This circuit can be made from readily available CMOS logic ICs and a single 2K byte eprom
(type 2516). and requires only a +5V supply.

BRIEF CIRCUIT DESCRIPTION
The program cycle is initiated by pressing the momentary
switch 81. This generates a pulse which clocks the 40130latch which in turn resets the 4040 counter; the same clock
pulse is passed to the output buffer as a program enable
signal for the NJ8820 or NJ8821/23.
The Q2 to Q7 outputs of the counter then sequentially
address 64 locations in the eprom, the start address of which
is determined by Hex switch 82 which is used to set bits A9to
A6 of the eprom address. The data outputs of the eprom 0604 are used to generate data select signals 082-080
(NJ8821/23) and to provide a 3-bit address to the 4051
multiplexer which in turn selects one of the eight hex
switches S3-S10.

The MSB of switch 82 selects, via the 74HC157
multiplexer, either the data bits 06-04 from the eprom or the
data select signals 082-0SO from input buffers (NJ8820).
Data output 03-DO (NJ8820/21/23) from the output buffer
is determined by setting the 8 hex switches 83-810. The
serial data output is derived from 03-00, via a 74HC153
multiplexer, which is in turn controlled by data bits 03 and
02 from the eprom.
Eprom data output 01 and DO generate the clock and
enable signals respectively.

DS>

DS1

NJ8820

DSO

jo8NSTS
*

SERiAl
ClK
ENABLE
PE

r-~==~~-----------!'C~

GND

* SERIAL DATA TO NJ8822,
NJ88C30 OR NJ88C31
00·D3 PARALLEL DATA

TO NJ8820 OR NJ8821.

Fig.l Universal programmer for NJ8820/21/22123124IC25 & NJ88C30/31

328

Switch

NJ8820/11213/4
NJ88C30/31

LSB MSB

MSB

LSB

LSB MSB

Switch

LSB MSB

MSB

LSB MSB

LSB

LSB MSB

NJ8820/11213/4

R10

NJ88C30/31

F15

F14

F13

F12

F11

F10

NOTE:
When entering the data for the NJ8820 series of devices it is necessary to multiply the M divide ratio by 4 prior to conversion to
hexadecimal. It is necessary to divide the R divide ratio by 2 prior to conversion to hexadecimal to take into account the fixed
divide by 2 in the reference chain.
Table 1 Switch settings for various synthesiser types

Synthesiser Type

0
0
0
0
0
0
1

0
0
0
0
1
1
0

0
0
1
1
0
0
0

0
1
0
1
0
1
0

NJ8821/3
NJ882214 (17 Bits)
NJ882214 (28 Bits)
NJ88C30/31
NJ88C25 (19 Bits)
NJ88C25 (30 Bits)
NJ8820

Table 2 Eprom addressing

AS to AO is determined by the 4040 counter outputs 07 -02 to
give 64 timing slots per synthesiser type. Start addresses A9
to A6 are set by switch S2.
Table 4 is an example of the eprom data for the NJ8822.
The start address 0040 is set by hex switch S2.
It can be seen how the data generates the clock and enable
signals, the control signals for the parallel to serial
conversion in the 74HC153 Mux and the selection of the
switches 53-510. In this case 56 and 57 are selected, these
contain the data for the 'A' counter which is thefirstto be sent
to the device.
A complete memory map of the eprom is given in Table 5.

0
1

Switch selected

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

55
54
53 LH5 switch
57
56
510 RH5 switch
59
58

0
0
1
1

0
1
0
1

050-052 and Oata outputs enabled
OSO-052 and Oata outputs disabled

Serial data
M5B 03
02
01
L5B 00

Clock alP

Enable alP
Table 3 Eprom data

329

Switch
Select

Parallel
to Serial

Address

Oata

O/P Enable

040
041
042
043
044
045
046
047
048
049
O4A
048
O4C
040
O4E
04F

80
02
47
45
48
49
4F
40
33
31
37
35
38
39
3F
30

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Table 4 Example of eprom data organization

NJ8821/3

NJ882214
17 Bit

NJ8822/4
28 Bit

NJ88C30/31

NJ88C25
19 Bit

NJ88C25
30 Bits

NJ8820

330

00
40
80
80
02
21
01
80
02
21
01
60
26
76
56
80
02
21
01
80
02
21
01
65
80
80
80
80
80
80
80
80 80
00 00
00 00
00 00
00 00

80
30
70
80
80
23
03
80
80
23
03
6F
80
70
50
80
80
23
03
80
80
23
03
67
80
80
80
80
80
80
80

01
41
80

80
47
27
07
80
47
27
07
53
24
74
54
80
47
27
07
80
47
27
07
68
80
80
80
80
80
80
80
80
00
00
00
00

01
41
80
80
45
25
01
80
45
25
05
51
2A
7A
5A
80
45
25
05
80
45
25
05
69
80
80
80
80
80
80
80
80
00
00
00

00
40
80
80
48
28
07
80
48
28

10
50
80
80
49
29
02
80
49
29
75
55
2E
7E
5E
80
49
29
09
80
49
29
09
60
80
80
80
80
80
80
80
80
00
00

11
51
80
80
4F
2F
80
80
4F
2F
78
77
57
58
28
2C
78
7C
5C
58
80
80
48
4F
28
2F
08
OF
80
80
48
4F
28
2F
08
OF
6F
53
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
00
00
00
00
00 00 00
00 00 00 00

11
51
80
80
40
20
80
80
40
20
79
59
32
62
50
80
40
20
00
80
40
20
00
51
80
80
80
80
80

10
50
80
80

20
60
80
80
31
11
80
80
31
11

21
61
80
80
33
37
13
17
80
80
80
80
33
37
13
17
7F 7D 63
5F 50 5F
30 36 34
60 66 64
80 80 80
80 80 80
33 31 37
13 11 17
8F 80 8F
80 80 80
33 31 37
13 11 17
77 75 78
57 55 58
80 80 80
80 80 80
80 80 80
80 80 80
80 80 80
80 80 80
80 80 80
80 80 80

80
80
80
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00

21
61
80
80
35
15
80
80
35
15
61
5E
3A
6A
80
80
35
15
8E
80
35
15
79
59
80
80
80
80
80
80
80
80
00
00

00
00

20 30 31 31
60 70 71 71
80 80 80 80
80 80 80 80
38 39 3F 30
18 19 1F 10
80 80 80 80
80 80 80 80
38 39 3F 30
18 19 1F 10
67 65 68 69
80 80 80 80
38 3E 3C 72
66 6E 6C 52
80 80 80 80
80 80 80 80
38 39 3F 30
18 19 1F 10
80 80 80 80
80 80 80 80
38 39 3F 30
18 19 1F 10
7F 7D 63 61
5F 50 5F 5E
80 80 80 80
80 80 80 80
80 80 80 80
80 80 80 80
80 80 80 80
80 80 80 80
80 80 80 80
80 80 80 80
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00

Table 5 Eprom memory map

Eprom
Start
Addr (Hex)

Switch
No.

100

140

200

Using the SP8835 in 3.5GHz Synthesisers _ _ _ __
Until recently, prescalers have only been available (at reasonable consumer prices) for frequencies up to about 1GHz. Now,
with the rapid improvement of silicon technology, Plessey Semiconductors has developed a range of dividers for frequencies for
up to 3.5GHz.
The following application note explains how one of these devices can easily be used with two standard integrated
synthesisers. The first example is of a 3.5GHz synthesiser using the SP8835 -.;- 4 (3.5GHz) together with the SP5000 (1GHz
synthesiser Chip). The second example is again a 3.5GHz synthesiser, but using the SP8835 -.;- 4 with an SP8704 -.;-128/9 (dual
modulus divider 1GHz) and the NJ8820. This second example can be programmed to give a smaller frequency step size than the
first example, but requires more components.
High speed dividers are primarily used in frequency
synthesisers, either phase locked loops or frequency locked
loops. Synthesisers incorporate a voltage controlled
oscillator which is controlled via a feedback network so that it
oscillates at a predetermined frequency. In most cases, this
synthesised frequency can be altered (by external
programming) to tune the oscillator over a range of
frequencies (band). The prescaler is used in such a system to

reduce the oscillator's frequency to one that can be
compared with a standard known reference frequency
(usually obtained from a crystal oscillator and divider). This
frequency comparison can be made in several ways, for
example a phase comparison using a phase detector (PLL)
or a frequency comparison using a frequency counter (,uPC)
in a frequency locked loop.

+5V

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