1988_Ricoh_Electronic_Devices_Data_Book 1988 Ricoh Electronic Devices Data Book
User Manual: 1988_Ricoh_Electronic_Devices_Data_Book
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· ICD©®[]{]
ELECTRONIC DEVICES
DATA BOOK
ELECTRONIC DEVICES
DATA BOOK
1. GENERAL INFORMATION
2. QUALITY ASSURANCE SYSTEM
3. ASIC
4. MEMORY
S.CPU
6. PERIPHERAL
7. THERMAL PRINT HEAD
ICD©®DO
RICOH COMPANY, LTD.
ELECTRONIC DEViCES DIVISION
NOTICE
RICOH COMPANY, LTD. reserves the right to make changes in any products described
herein at any time without notice.
Specifications in the data book are subject to change without notice.
RICOH COMPANY, LTD. does not assume any liability arising out of the application or
use of any product, circuits or software described herein, neither does it convey any license
under its patent rights nor the patent rights of others.
Copy right © 1988
RICOH COMPANY, LTD.
Table of Contents
Page
1.
GENERAL INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1·
2.
QUALITY ASSURANCE SYSTEM
2-
3.
ASiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-
CMOS EPL 208 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3- 3
EPL APPLICATION MANUAL
4.
............................ .
3 - 11
EPL 241 E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 - 61
CMOS GATE ARRAY 5GH Series . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 - 73
CMOS GATE ARRAY 5GH Series CELL LIST
................ .
3 - 75
CMOS GATE ARRAY 5GF Seteis . . . . . . . . . . . . . . . . . . . . . . . . . . .
3- 83
CMOS GATE ARRAY 5GF Series CELL LIST
3 - 89
CMOS STANDARD CELL RSC-20 Series . . . . . . . . . . . . . . . . . . . . . .
3 - 99
CMOS STANDARD CELL RSC-20 Series CELL LIST ............ .
3 - 101
CMOS STANDARD CELL RSC·15 Series . . . . . . . . . . . . . . . . . . . . . .
3 - 107
CMOS STANDARD CELL RSC-15 Series CELL LIST ............ .
3 - 109
MEGA CELL FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 - 121
MEGA CELL FAMI L Y for DSP
3 - 129
MEMORY
........................... .
........................................... .
MASK ROM
64K bit RP2364E . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-
.......................... .
4- 3
4- 7
MASK ROM 256K bit RP23256D/E, RP23257D/E .............. .
4 - 11
MASK ROM
1M bit RP231026E
......................... .
MASK ROM
4M bit RP23C4000
......................... .
4 - 15
4- 19
4- 25
MASK ROM 128K bit RP23128E
EPROM 64 bit
5.
................ .
CPU
RF5HOI/RP5HOI
..................... .
............................................... .
RP65C02 (CMOS 8 bit CPU)
............................. .
55- 3
6.
7.
PERIPHERAL
.........................................
6·
REAL TIME CLOCK
RF/RJ/RP5C15 . . . . . . . . . . . . . . . . . . . .
6· 3
REAL TIME CLOCK
RP5C01 . . . . . . . . . . . . . . . . . . . . . . . . .
6· 11
REAL TIME CLOCK
RP5C62/RF5C62
................. .
QUAD UART
RF5C59 . . . . . . . . . . . . . . . . . . . . . . . . .
CRT CONTROLLER
RF5C16 . . . . . . . . . . . . . . . . . . . . . . . . .
6· 25
6· 30
6· 37
VOLTAGE REGULATORS
RX5RA Series
VOLTAGE DETECTORS
RX5VA Series
6· 49
................... .
6· 55
THERMAL PRINT HEAD
7·
THERMAL HEAD SH Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7· 2
1. GENERAL INFORMATION
• Synaptical table describing Ie among our products.
System of R ICOH's products
J
{~;~;Iication
_
,-----IC
Hard·
ware -
,
Semi·
[custom
-L
USIC
(user "
EPL (CMOS PLD)
Gate Array
Standard Cell
(Polycell Type Standard Cell)
Specific
IC)
Full·
u t
ASSP
c s om
- - - Structured Cell
,.._
. .
(Application
Specific Standard
Product)
STANDARD----------------I
(Standard IC)
Specific
IC)
:eu~:~~g Block TYP~ Standard Cell)
L
MROM
EPROM
- - Microprocessor
- - Peripheral IC
L-._
Real-time Clock
-CRT Controller
~Voltage
Regulator
r---- Voltage
Detector
-QUAD. UART
I
I-
Auto-focus
Ie
DC Motor Controller
Lparallell/O
HIC - - - TPH (Thermal Print Head)
Software -CAD system1
Hardware-~ Personal Computer ........... .
Cell Library
I-- Engineering Work Station
Development L EPL Programer
software
RICOH supports the CAD system, an extensive
VLSI Design package that operates on IBM
personal computers or EWS (Engineering Work
Stations).
,Proposal Service ................................................................ RICOH will always provide proposals for the
design and development of any ASIC device,
EPL to gate array conversion, Gate Array, or
Standard Cell.
Service·
ware -r-Design Center Service ......................................................... R ICOH offers a turn·key design environment,
CAD system seminars and consulting service.
RICOH engineers will train customers to
develop and design I.C.'s.
~Maintenance Service ........................................................... RICOH will service or repair CAD systems
purchased from R ICOH and Maintain all
software.
1-2
RICOH ASIC
EPL
Features
This is the ASIC which allows the user to
program optional logic circuits with
many standard PAL programmers. This is
optimum replacement for small-scale
logic and CPU peripheral devices. EPL's
provide a quick evaluation and correction
of logic circuits.
-Upward compatible to AMD/MMI
PALS.
-CMOS EPROM process
• Low current consumption and
high programmability.
• Erasable by ultraviolet light
(ceramic window package).
-Maximum access time 25/35ns
-20pin, 24pin types
-Up to 900 gate equivalents
-Security fuse
-Output polarities are programmable.
•
Lineup
Model name
Power
supply
Configuration
Electrical characteristics
~c-----,M,,-a~x. Icc
Operation
Max.
~ access time
Max. opera-
Package
ting freq.
G EPL10P8
B 10 input 8 output
I
AN D-DR/XOR Array
EPL12P6 B 12 input 6 output
AN D-OR/XOR Array
EPL14P4 B 14 input 4 output
AND-OR/XOR Array
EPL16P2 B 16 input 2 output
AND-OR/XOR Array
G EPL16P8 B 10 input 6 input/output
II
AND-OR/XOR Array
EPL16RP8 B 8 input 8 feedback 8 output
5V±5%
8 register AND-ORJXOR Array
EPL 16RP6 B 8 input 6 feedback 2 inputl
Compatible
products
PAL10L8.10H8
~L6.12H6
50mA*
40mA*
PAL14L4.14H4
PAL16L2.16H2
20DIP
35n5
20MHz
(plastic, ceramic
with window)
PAL 16L8
r-::----c___- - - - i
PAL16R8
70mA
60mA
PAL16R6
output 6 output 6 register
AND-OR/XOR Array
EPL 16RP4 B 8 input 4 feedback 4 inputl
output 4 output 4 register
AND-OR/XOR Array
EPL241 ED/
6 input 16 input/output
EP/EJ
16 microcell built-in
PAL16R4
140m A **
1 20mA **
25n5
20MHz
24DIP
28PLCC
22Vl0 & others
clock select
asychronous reset
attached/6 register
GI: Group I
GIl : Group II
* Since Group has twice as many product terms as PAL products, typical currents will be reduced to a half of the above
specification values by power-down circuits in RICOH's EPL.
** It will proportional to the product term usage. (40 mA at 35% utilization)
Note) A high speed version of 20pin EPL's with access time of 15ns is under development.
Interface
Support Tool
Software
@EPLASM (RICOH)
@ABEL (Data I/O)
Hardware
@Universal Programmer
UNISITE40, 29B (Data I/O)
@Model 60A (Data I/O)
@Model PW98-20 (RICOH)
(Board Writer)
• Packer 30 (AVAL)
Hardware
• SW16 (Ricoh)
(RICOH)
Customer
RICOH or Distributors
.....- - - - 1 •
Logic equation
• Specification
• IBM-PC AT (IBM)
• PC9801 (NEC)
•
• PROMAC Model 11 (Japan Macnics)
1-3
If the customer has the programer, it can be
programed by the customer.
@mark: Products handled by RICOH's sales
RICOH ASIC
GATE ARRAY
Features
This is the ASIC which performs wiring operation in matching with user's specification upon
preparing the master arranged with the fixed number of gates beforehand by the manufacturer. For this reason, large-scale circuit can be developed at a moderate cost and in short
period of time.
Three series of Gate Arrays are available:
.5GH CMOS (1.5ns/gate propagation delay)
.5GF CMOS (l.Ons/gate propagation delay)
.3G Analog/Digital Bi-CMOS
RICOH's cell libraries can be designed on Daisy, Mentor and P.C. CAD stations (FutureNet)
5GH Series (CMOS Gate Array, 2.0Jl Design Rule)
Model
name
No. of
gate
5GH05
5GH10
5GH16
5GH23
5GH29
5GH38
5GH55
560
1000
1600
2300
2900
3800
5500
No. of
I/O
40
60
72
88
98
108
120
Gate delay
time
Power
Input output
supply
level
1.5ns/gate
Load con-
5V±10%
dition
Package (No. of PINs)
DIP
CMOS/
TTL
compatible
2 input NAND,
FAN OUT ~ 3,
14,16,18,20,22,24,28,40
24, 28, 40, 48
24,28,40,48
28,40,48
28,40,48
28,40,48
Shrink DIP
FLAT
42
28
28
-
64
64
64
-
-
PLCC
-
60,44
60,80,44
60,80,100
80,100
60,80,100
44
44
28,68,84
68,84
68,84
-
-
wire length = 3 rnm
I
Note) For the packages other than above, please inquire to RICOH.
5GF Series (CMOS Gate Array, 1.5Jl Design Rule)
name
No. of
gate
5GF21
2100
Model
5GF26
2600
5GF32
3200
5GF45
5GF58
5GF82
4500
5800
8200
Max. loading
memory capacity
RAM (ROM) (bit)
2K
(4 K)
2K
(4 K)
2K
(4K)
4K
(8 K)
8K
(16 K)
16 K
(32 K)
No. of
I/O
Power
Gate delay time
supply
Package (No. of PINs)
Input output
level
84
94
DIP
Shrink
DIP
FLAT
PLCC
40
64
44,60,64,80,100
68
40
64
44,60,64,80,100
68
40
64
44,60,64,80,100
68
40
64
60,64,80,100
68
40
64
64,80,100
68
40
64
80,100
68
1.0ns/gate
102
120
138
168
5V±10%
Load condition
2 input NAND
FANOUT~3
wire length ~ 3
CMOS/TTL
compatible
mi
Note) In case of memory integrated, the total number of usable gate wi II decrease compared to the above·mentloned numbers,
For the number of usable gate when memory is integrated,and Test PINs to check memory or logic, please consult your
RICOH design center,
3G Series (Bi-CMOS/CMOS Gate Array)
Model
name
3GOI
3G02
No. of
gate
250
400+
decorder
No. of
I/O
37 (with
NPNTr)
{ 16 (with
NPNTr)
14 (with
PNPTr)
Gate delay
Power
Analog circuit
time
supply
scale
6ns1gate
5V±5%
(CMOS)
8 op·AMP eq.
4ns/gate
-15V
(bipolar)
12 op-AMP eq.
Package (No. of PINs)
DIP
PLCC
PIP
44,54,60
-
-
24,28,40,64 44,54,60
-
-
28,40,64
FLAT
Note) Since input and output sections contain bipolar NPN transistors, it will allow the direct drive of externally mounting
elements such as LED, fluorescent indication tube, mini-motor, etc,
1-4
RICOH ASIC
o ~~:aory
Features of 5G F Series
Development Tool
Hardware
_ EWS
- Personal
computer
D
I/O Cell
5GF Series Gate Arrays allow memory (ROM, RAM) in
conjunction with Logic requirements.
RICOH's unique system of constituting the memory using
wired area, as shown on the right diagram. Since it does not
requi re the master for memory, the cost for development can
be kept down in case of memory integrated.
Logic Area,-'---'=-;:;-:-;;-ill
J
I/O Cell
~J~Jj iJ,
(for CAD Interface)
I/O Cell
I/O Cell
Example of other systems
Software
5GF Senes
@RICOH cell library and simulation data
@RICOH's development software
@DASH, CADAT (Data I/O Co. provided that development only on
personal computer)
@Mark: Products handled by RICOH sales
LOGICIAN (Daisy)
IDEA 1000 (Mentor)
IBM·PC AT (IBM)
@SW16 (RICOH)
Interface
Customer
RICOH
• Logic diagram
• Timing chart
I. Schematic
interface
• Specifications
• ROM data
(EPROM or FD)
___ l __
(e
II. CAD
interface
_ ROM data (EPROM or F D ) : = I
,.-------1
• RICOH cell library
• Software for
development
(_ ROM library)
N
Timing simulation
Confi rmation
y
N
Auto placement
Confirmation
and wiring
y
Mask creation ~
sample preparation
Evaluation
Mass production
y
}-5
RICOH ASIC
STANDARD CELL·STRUCTURED CELL
Features
This kind of ASIC allows maximum flexibility without
full custom expense. Development time and fabrication
costs are more than gate arrays but allow integration of
analog cells, CPU peripherals, memory cells (ROM and
SRAM), and D.S.P. functions (multipliers, Microprogram Sequencer, dual port SRAM).
RICOH's standard cell design rules are 2 micron or 1.5
micron which allow *2.0ns per gate delays or 1.0ns per
gate delays.
When Bi-CMOS is integrated on the 2 micron design
rules, I.C.'s provide high current options, high voltage
options and other common analog functions not possible
with standard digital processes.
The Structured Cell system is comprised of three types
of Cells.
1. Basic logic and registers
2. Compiled Cells synthesizing the basic Cells (Inc.
ROM and SRAM Blocks)
3. Mega cells that perform complex functions
(Cell Library)
.2.0/1 design rule
• Macro cell, Macrofunction cell (Basic cell) ............... 103 cells
• Mega cell (Large cell)
Logic cell for CPU peripheral ............................... 6 cells
• Compiled cell (Large cell)
MROM, SRAM
• Analog cell ........................................................... 5 cells
• Bipolar analog cell ............................................... 180 cells
.1.5/1 design rule
• Macro cell, Macrofunction cell (Basic cell) ............... 411 cells
• Mega cell (Large cell)
Logic cell for CPU peripheral ............................... 5 cells
• Compiled cell (Large cell)
DSP cell ........................................................... 9 cells
MROM, SRAM, PLA
• Analog cell ........................................................... 2 cells
Example of Development
§ O S Standard Cell
I
The 2 micron design rule Standard Cells can be further enhanced by combining high voltage
and high current capability. All cells common to the 2 micron library are compatible with the
Bi-CMOS process. Analog cells can be implemented in this process. The analog cells integrate
popular functions such as operational amplifiers, comparators, voltage references, and specialized buffer cells.
Example of development
(Ie for controller)
I
ASIC OSP (Digital Signal Processor)
I
RICOH has the cell library for DSP available as mega·cell and is, therefore, prepared to develop
DSP as ASIC. (Cell for DSP can be automatically prepared in line with user's specification,
using CAD.) Accordingly, it will materialize the function most suited for user's specification
without any excess and lack and thus, will materialize high performance 1 chip DSP that can
not be materialized with general·purpose DSP.
Example of development
(Ie for image processing)
1-6
RICOH ASIC
CMOS Standard Cell· Structured Cell (1.51l Design Rule)
CMOS
Process
"--
Gate delay
Power supply voltage
1.0n5 /gate (load condition: 2 input NAND, FAN OUT = 3, wire length
=
3mml
5V 15V±10%1
Package
Same as 2.0j..L design rule
Basic cell
Micro-cell-----180 cells
Micro-function cell-----231 cells
( Compiled cell )
( Mega-cell)
Multiplexer
TCC ITimer/Counter!
-&'
0'
@
Multiplier
ACt (Asynchronous communication interface)
Multiplier/Accumulator
PIO IParaliel input/outputl
Large-scale cell
-<
o MROM, SRAM, PLA
• Cell for DSP
• CPU peripheral cells
ALU
HS IHand shakel
Pipeline register
I NTC (I nterrupt controllerl
Addition subtraction cell
Barrel shifter
Register file
Microprogram sequencer
Analog cell
AID converter (Sbit)
0/ A converter 18bitl
CMOS, Bi-CMOS Standard Cell (2.01l Design Rule)
Process
Gate delay
Power supply voltage
DIP
Shrink DIP
-0
~
f"
FLAT
28,42,64
44,60,64, 80, 100, 128, 144, 160
18,20, 28,44,68,84
SOP
20,24,28
PGA
5V ± 10%, ±5V (Bipolar section)
5V 15V±10%1
14,16,18,20,22,24,28,40,42,48
PLCC
Basic cell
Bi-CMOS lsi gatel
CMOS
2.0ns/gate ICMOS logic section I (Load condition: 2 input NAND, FAN OUT = 3, wire length = 3mml
68,84,100,120,132,144,160,180
Macro-cell-----71 cells
Macro-function cell-----32 cells
Compiled cell
oMROM, SRAM
(Mega-cell >
Large-scale cell
< Compiled cell )
• CPU peripheral cells
oMROM,SRAM
RTC IReal-time clockl
~
Timer (8bit)*
SCI (Communication interface)
Multiplier (8 x 8)*
TCC ITimer/Counter!
CRT controtter*
* under development
0'
• Operational amplifier-----5 cells
@
-<
• Comparator----4 cells
Analog celt
o I/O cell-----3 cells
IBipolar!
• VRFE, Analog switch, Transistor, Resistor,
Capacitor-----Many kinds for each
A/D converter 18bitl
Flash type AID converter*
Analog celt
ICMOSI
D/A converter 18bitl
Operational amplifier
SCF (Switched capacitor filter)*
*
under development
1-7
RICOH ASIC
Development Tool (for CAD interface)
Hardware development tools required in the case of CAD
interface are same as gate arrays .
CAD interface supports the following systems.
• 2.011 design rule
CMOS Standard cell with basic cell
.1.511 design rule
CMOS Standard cell with basic cell
The systems in which other cells are used will be schematic
interface.
Interface
Type
I. Schematic
interface
Customer
RICOH
•
----- ---- --. -_._ .. -- --. ----- ---- _.- -- ----- ... ----. _... --- --- --- ---- --
I
--~-_.-
I
:
-.-. ------ _. "--- ._---_. _.. ----------------_ .. ---.".- --
Software development
• RICOH cell library
Hardware
development
• Simulation data
• Software for
development
n.
CAD
interface
Timing simulation
Mask creation "-'
sample preparation
Mass production
Note) The CAD interface system provides software development for any practical circuit.
1-8
RICOH STANDARD
MASK ROM
Lineup
Model name
Configuration
Memory
Type
capacity
Access
Power supply
time (ns)
voltage
RP2D32
32K
64K
8192x8
RP2D129
128K
16384x8
128K
16384x8
256K
32768x8
RP2D130
Pin
compatible
Operation
Standby
250
440
-
24
TI
250
440
-
24
INTEL
200
550
110
28
INTEL
250
550
110
28
INTEL
550
110
28
TI
200
550
110
28
INTEL
250/200
550
110
28
INTEL
250/200
550
110
28
TI
1M
131072x8
250/200
550
165
28
INTEL
4M
524288x8
262144x16
200
220
0.55
40
250
NMOS
5V±10%
RP23128E
RP232560/E
RP23257D/E
RP231026D/E
RP23C4000
No. of pin
4096x8
RP2D33
RP2364E
Max. power consumption
(mW)
CMOS
Interface
RICOH
Customer
• EPROM for code check 2 pes.
CD
Ordering
format
0
Function
terminal
4-
1-----"-NO=-<.!Confirmation1>-_ _ _ _ _ _ _ _I -_ _ _ _ _ _-'
(
3rd check
YES
(
2nd cheCk)
)
YES~-~========~---+-----i~~~~~J
I
I
L ______________________ ~--- ______ ...1
The above processes are omitted
by RICOH to deliver mass
:
production to the customers at
I
the earliest possible opportunity.
:
LJ~;::::==~------~
I
(
I
1-9
4th check)
RICOH STANDARD
EPROM
Max. power consumption
Model name
Memory
Type
capacity
Access
time (/Ls)
Configuration
(mW)
Power supply
voltage
Operation
RP/RF5HOl
CMOS
64 bits
64xl
1
5V±5%
55
No. of pin
Pin
compatible
B
-
Cycle time
Package
I Standby
I
0.55
MICROPROCESSOR
Model name
Power supply Max. power
voltage
consumption
Circuit function
RP65C02
Bbit CMOS CPU (Rockwell Compatible)
RP65C02A
Bbit CMOS CPU (NCR Compatible)
Motion
frequency
20mW/MHz
5V±5%
40·DIP
1 -4MHz
l/Ls - 250ns
20mW/MHz
40·DIP
REAL·TIME CLOCK
Max. current consumption
Model name
Power supply
voltage
Circuit function
RP/RF/RJ5C15
REAL TIME CLOCK
RP5COl
REAL TIME CLOCK with RAM
RP/RF5C62
REAL TIME CLOCK
Backup
power
Package
During
backup
voltage
2SOl'A
15/LA
2.0V
2SO/LA
151'A
2.2V
lB·DIP
SOI'A
31'A
2.0V
lBDIP/1BSOP
Operation
lBDIP/1BSOP/2BPLCC
5V±10%
5V±10%
CRT CONTROLLER
Power
Model name
RF5C16A/RP5C16
•
Circuit function
CRT OISPLAY CONTROLLER (All in One Type)
640x200 or BOx25 (chalacter x line)
Power
supply
supply
voltage
current
5V±10%
SOmA
Package
64·FLAT
64·DIP
The 5C16 can display graphics in 16 colors and multiple screens by commands from popular CPU's (65C02, 8085, Z80).
This VLSI CRT Controller only needs one or two DRAMS and CPU to function.
VOL TAGE REGULATOR
Output
Model name
RX5RA
Circuit function
IC for power (output can be set at 0.1 V step)
voltage
accuracy
Operation
voltage
range
Power
consumption
Package
±2.5%
1.5 -10V
l/LA
Mini·power mold/TO·92
Voltage
detection
accuracy
Operation
voltage
range
Current
consumption
Package
±2.5%
1.5 - 10V
11'A
Mini·power mold/TO·92
VOLTAGE DETECTOR
Model name
RX5VA
Circuit function
IC for voltage detection (detection voltage
can be set at 0.1 V step)
QUAD. UART
Model name
RF5C59
Circuit function
Asynchronous receiver transmitter with 4 channel ports.
1-10
Power supply Max. power
voltage
current
5V
20mA
Package
60·FLAT
RICOH STANDARD
AUTO FOCUS IC
Max.
Light
supply
power
emitting
current
interval
Max. measuring
path time
(After Vee ON)
Package
voltage
3V±10%
4.5mA
0.5s
32ms
44-FLAT
Power
Model name
RF3L06
RF3Lll
Circuit function
AUTO FOCUS IC FOR 35mm LENS
SHUTTER CAMERA & VTR
CAMERA
• RF3L06 and RF3L 11 are the IC for autofocus of projection and light reception system under which near infrared LED and
linear line senser are combined together.
DC MOTOR CONTROLLER
Model name
RF3POl
*
Circuit function
DC SERVO MOTOR CONTROLLER (Can be connected direct to PWM
output, Sbit CPU)
Power supply Max. power
voltage
current
5V±5%
30mA
Package
60-FLAT
R F3P01 can control the speed of DC motor in extensive ranges and at high accuracy by connecting it with 8bit CPU,
PARALLEL I/O
Model name
RF5C60
Circuit fU'1ction
6 I/O Port (Sbit I/O Port x 5, 5bit I/O Port x 11
Power supply Max. power
voltage
current
5V±10%
30mA
Package
60-FLAT
Note) EPL is the registered trademark owned by RICOH, LOGICIAN is the registered trademark owned by Daisy Systems Co,
IDEA 1000 is the registered trademark owned by Mentor Graphics Co, IBM-PC is the registered trademark owned by IBM
Co, DASH is the registered trademark owned by FutureNet Co, CADAT is the registered trademark owned by HHB
Systems Co,
1-11
I
2. QUALITY ASSURANCE SYSTEM
THE POLICY OF QUALITY ASSURANCE
RICOH, Electronic Devices Division, keeps in mind to develop devices and assure the quality putting ourselves
in customers' place. RICOH pursuits following 5 points night and day to offer the best quality timely with
the optimum cost to the customers.
REQUIRED QUALITY
REALIZATION
EARLY STAGE
TOTAL ASSURANCE
CONTROL
CONTROL
HIGH QUALITY
FAILURE RELAPSE
HIGH RELIABILITY
PREVENTION
I. Accomplish the quality aim satisfying the use condition and requirements of customers.
2. Control the first stage thoroughly to make in the quality on development and manufacturing steps.
3.
Recognize the importance of quality through quality improvements and quality educations, and then
aim at the high quality and high reliability.
4.
Inquire into the cause of failure in cooperation with other sections and take measures immediately and
completely not to meet the recurrence.
5. Complete the synthetic assurance and control system which satisfy quality, cost, and delivery.
2-3
•
QUALITY CONTROL FLOW CHART IN MANUFACTURE
Parts, Materials
Quality Level Check
Machines, Dimension
Environment, Process
Parameter, Sub
Materials, Operators
1'---_
I In-Process Q.C.
_
Quality Level Check
_____ oj
Test, Inspection
~--~--~------~
Quality Level Check
Quality Level Check
Quality Level Check
------1
Test, Inspection
~------.-------~
~
Quality Assurance
----------<"-. Inspection ?'----------
L...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Claims
Field Information
etc.
2-4
______
I
1
Sample, Lot Judge
QUALITY ASSURANCE SYSTEM
An effective quality assurance system cannot be undertaken on an individual basis. Only a cooperative effort
among all divisions can consistently achieve a solid guarantee of top quality. Put into practical use, a system
of this type must be functional, it must be based on the idea of standardization, and it must quickly accommodate the data and feedback that continually pass between departments.
We have developed a Quality Assurance System that incorporates these concepts. Our Quality Assurance
Department is set up to ensure fast, accurate relay of information between divisions and prompt execution
of quality assurance tasks at each step in the manufacturing process - from product development to mass
production.
At the product development stage, the tasks required in all succeeding stages are defined and responsibility
for their execution is assigned. The Quality Assurance Department then undertakes inspections from a comprehensive point of view, through its inquiry groups. Our quality and reliability criteria are geared to meet
reliability and qualification testing standards such as MIL, EIAJ, and 1IS to ensure that our product designs,
processes, and conformity to standards are approved.
At the mass-production stage, the Manufacturing Department undertakes strict control of processes, product
quality within processes, equipment, and the environment, in order to build in quality at each step. The
Quality Assurance Department safeguards overall quality by inspecting incoming materials, controlling product amendments, maintaining accuracy in measurement devices, inspecting wafers and making final checks,
monitoring quality, and undertaking quality assurance checks which ensure that no defective products reach
the market.
2-5
•
FAILURE ANALYSIS FLOW CHART
I
Customer
l
Sales & Marketing Dep.
I
I : Claims (Defective devices
J
J
Quality Assurance Dep.
I
J
J : Failure Analysis
--t-.------ --,
r-----I
External Visual
r __
I
~~~~~~~"~r~~~~-~~~
Research Data
Process Data
Q.A. Data
:
Electrical Analysis
& Field Information)
: Scope/X ray Video
A",o To""
: Manual Checker
-' Oscilloscope
:~~~~~~~~[~~~~~~,
Parametric
:~a~~e~ ___ ,
Jr-_-_-_-_-,-------L----~~ii~t~~~ ____ ----L~~~pe~~n~~i
Jr-i
Internal Visual
L_I~ipec.!i~n__
I
Life Test
Environmental
Test
De Encapsulation
Scope
S.E.M.
I
J
Manual Probe
X.M.A. (E.D.S., W.D.S.)
Cross Section
EB Tester
r----J-----L-----,
Classification of
I
I
IL _______
Failure Mechanism
] ________ I
~
I
~
t
Production Dep.
1[1--------------:::----,-----------1'1
Report
Design Dep.l: Action to
Prevent Failure
t
I
I
Quality Assurance Dep.
l
Sales & Marketing Dep.
I
Customer
J
t
2-6
J
: Advise and Confirmation
of the Action
Failure Analysis Report
J
I
LOT ASSURANCE INSPECTION
( +ASSEMBLY INCOMING INSPECTION)
Sampling: Every Wafer Lot
No.
LTPD
TEST METHODS
TEST ITEMS
(%)
Maximum
Accept No.
I
ELECTRICAL
(Open, Short check)
Auto Tester
QAT Specification
5
0
2'
HIGH TEMPERATURE
OPERATING LIFE
Ta = T jmax 125°C
20 Hrs.
Dynamic Operation
10
0
3
THERMAL SHOCK
(liquid)
Ta = T stgmin ~ T stgmax
(5' -10" -5')
20
0
20
0
10 Cycles
MIX PCT
TYPE A
TYPEB
FPP-IH
package
DIL
package
TYPEC
FPP-2,3
package
SOLDERING HEAT
260°C
Lead only
10 sec.
260°C
Full dip
5 sec.
260°C
Lead only
10 sec.
(2.5 x 4)
THERMAL SHOCK
T stgmin
T stgmin
T stgmin
I
I
I
T stgmax
5 Cycles
T stgmax
5 Cycles
T stgmax
5 Cycles
121°C
2 atms
20 Hrs.
121 °C
2 atms
20 Hrs.
121°C
PRESSURE COOKER
2-7
2 atms
20 Hrs.
•
OUTGOING INSPECTION
Sampling Method: MIL-STD 105D
No.
1
DIVISION
ELECTRICAL
TEST ITEMS
CRITERIA
Function
DC
AC
QAT Specification
LEVEL
AQL
0.25%
*1)
2
* I)
APPEARANCE
Heavy Defect
Light Defect
Visual Inspection
Criteria
Catastrophic Failures (short. open, or functially inoperative) AQL 0.065%
2-8
0.65%
1.0%
RELIABILITY TEST REQUIREMENTS
TABLE I RELIABILITY/ENVIRONMENTAL
PACKAGE TYPE
I
No.
TEST ITEMS
TEST CONDITION
PLASTIC
I
2
3
4
5
6
7
8
9
10
II
12
13
High Temp. Operating Life
High Temp. Reverse Bias
High Temp. Storage
Low Temp. Storage
85/85 Temp. Humidity Bias
Low Temp. Operating Life
Pressure Cooker
Thermal Shock
Temp. Cycle
ESD Sensitivity
Latch Up (CMOS Device Only)
Mechanical Shock
Vibration
125°C (I50°C) Vcc Max
125°C (I 50°C) Max
125°C (150°C)
-40°C (-65°C)
85°C/85% RH Vcc Max
-20°C (-55°C)
121°C/15PSIG/l00% RH
125°C( -65~ 150° C)
-40~ 125°C(-65~ 150°C)
M
M
0
0
M
M
0
0
M
M
0
0
M
M
M
M
M
-40~
2000V/200V
-
*
*
1500g/ZI, YI, XI
20 ~ 2 kHz
CERAMIC
QUALIFY
TEST TIME
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
200 Hrs.
200 Cycles
1000 Cycles
*
M
M
M
M
M
M
-
4 Cycles
): Option
TABLE II MECHANICAL
PACKAGE TYPE
No.
14
IS
16
17
18
19
TEST ITEMS
Physical I?imensions
Marking Permanency
Visual and Mechanical
Solderability
Lead Integrity
(Fatigue, Forming, Pull)
Hermeticity
(Fine, Gross)
TEST CONDITION
QUALIFY
TEST TIME
PLASTIC
CERAMIC
COND.B or D
M
M
-
M
M
M
M
M
M
-
0
0
-
*
M
-
-
260°C
-
F/L: 5 x 10 B ATMcc/sec
G/L: 2 Hrs. at 60 PSIG
M: Mandatory
2-9
0: Optional
-
-
*. Not Applicable
•
QUALITY & RELIABILITY ASSURANCE FUNCTION
TOKYO (JAPAN)
TOKYO VLSI
OSAKA VLSI
DESIGN
DEP.
USA
NIES
REDD RICOH ELECTRONIC DEVICE DLV.
2-10
_IC_D©_®_[}[]__~I
EPL 208 SERIES
EKE-2-8807
CMOS ELECTRICALLY
PROGRAMMABLE LOGIC
• GENERAL DESCRIPTION
• FEATURES
RICOH EPL 20B Series are Field-programmable logic
arrays by CMOS EPROM process technology.
Tow product groups make up the EPL 20B Series
family.
Group I consists of AND-FIXED OR, XOR Arrays.
(EPLI0P8, 12P6, l4P4, l6P2)
Group IT consists of AND-FIXED OR, XOR Array,
eCMOS process technology ensures the low power con:
sumption, and higher reliability
e Available in both plastic and Cerdip window packages
eData copying protection
e Flexibility oflogic structure
e Package Type
20-pin 300mil Plastic DIP (One-shot)
20-pin 300mil Ceramic DIP with a window (Repro grammable)
eProduct Term : 32 line (Group I)
: 64 line (Group IT)
e Propagation Delay Time
: 35ns (MAX)
e Each pin has Programmable Polarity
eUp-ward compatibility with MMI PAL
(EPL 16P8) and three Registered AND-FIXED OR, XOR
Arrays. (EPL 16RP8, 16RP6, 16RP4)
EPL 20B Series allows users to program easily by programming EPROM Memory Cell, available in both plastic
packages for one-shot and reprogrammable Cerdip window
packages.
Therefore, it is possible to shorten the development term
and check and correct the circuits easily.
EPL 20B Series FAMILY
f
_P~IU NUMBER
IEPL 101'8 B
-+-- __ ____ ___ ____ CONFIGUR6.1!Q~~ _ _ _ ----~--------l
. 10·I],;I'UT. 8·0UTI'UT. AND·OR/XOR ARRAY
'1-=-PL121~(jB 112:-iNPU1~OUTPUT, AND·OR/XOR ARRAY----------~--
CROUP I c·---EPL 141'4 B
,
-----.~-----... ~.~- ....~--.~.-.-.-.------___I
I 14·INPUT. 4 OUTPUT. AND·OR/XOR ARRAY
l-:r'C 161.,-z-B--·16·IKPU1c:z:OUTIJUTANO:OR7xo·RARRAT'----
;-EI'Li61'S-B--;1O:IM;UT.6:iNPl;i7oUTlvr:Z:-OUTPUT--:-J\Ni)DRIXORARRA'Y---~.-
tf:I'I:J61{J'S-B--Ts.I:';PlJT8FEEDllACK.8.0UTPUT.8.REGISTERED.ANDOR/XOR ARRAY--~'--CROUPII
II-:PL 16RP6il- Ts:i~PUT6FEEDBACK.2INPuT7(jliThIT~8DUTPUT,6REGISTERED.AND.OR!XOR
IEI;L 161~P4B-'U,;piIT. i'FEEDBAC·K.4:rNPUT/OUTPUT. 8·0UTPUT. 4 RF..GIS;fERED
AND·OR/XOR
ARRAY
ARRAY
Electrically Programmable Logic
N umber of Array Inputs
Resister
Output Polarity'
1'= Porgrammable Polarity
N umber of Outputs
Programming Voltage
B=I3.5V
Package Type
D= Ceramic DIP witb a quartz window (Reprogrammable)
I' = Plastic DIP (One·shot)
EPL
16
R
I'
B
o
'At time of shipment: Active·Low
ItD®®OO•
3-3
•
CMOS EPL 208
EPLIOPBB
EPLl2P6B
EPLl4P4B
EPLl6P2B
EPLl6PBB
EPLl6RPBB
EPL16RP6B
EPLl6RP4B
(Note)
m: FEATURE Cell
(OR,
ltD:
XDR,
POLARITY)
--\»>-:
FEATURE2 Cell
(POLARITY)
FEATURE1 Cell
(OR,
XOR)
-IID®@DO~--------------3-4
CMOS EPL 20B
•
Electrical Specifications
Absolute Maximum Ratings
~l~LI_~ __ Para~_t.er_~ ..
V cc
_ V_cc_~uppl~'_~0tage_
VPI'
I'd
_~]"opr
Tstg
With respect to GND
--lrljlut,,(~taz;:-----------==--=--=-
~_()utput
v()
Rated Value
~_=-o. :l-
Vpp supply voltage
V,- ---
•
Condition
Unit
7. O_ _ _ _ _ ~
-0.:l-14."
v
-O.:l- Vcc+O.:l
V
voltage
I
l\t~~~mun~~_~~~_r__cgI!~~~p_~i(~n_
[
~tl;;~~~~~ t~~~:fa~~;~e-n~~~tu!,,- f-------~---~- ----
Ta = 2;)QC
Capacitance
I
Symbol
Inpu~_eapa~tance
CIN
I---~--
COUT
--r
~
'2~911 In
r---(pin p
P",m.",
!
1----
Output capacitance (12 ~ 19 pin)
Co,di""
av to Vee
I VOUT = av, f -IMHz
VIN=
Min
-
Value
Typ.
Unit
Max
---pF -
--+i!-
-
pF
pF
D.C.Characteristics (Ta = 0 to 70"C, Ycc= 5V± 50 0)
E'
-__ Cond~
~mbj]0~
~J~~~~~~Ju~
Parameter
_ h,_
Input current leakag~_____
VIN=QV to Vc~_
~ _____ -i-. -20 I
20
: JI.I\__ ~
~_
-"!-" mput voltage
__
_
~ ____ ~ ~~-i.l.__
O.H
\',~
"H" mput~-"lli!J.twH===~*~1s~v tWL-----3>j ·1.SV
~
~
tsu-----:>>+'E-CtH~ ~-l-S-V-----------------
SV
=*=
~tc,,::.::1_
/~hijffi(iV*,---
$/;01
_-_-_-_-_-_-_-_-_-_-
k-tpo
~r
g~;~'tnat,o"al !/1iII/IIId/#i///////lX~~~============
---;---;U~"J
Output
___k____tP_IX_ _ _~}
Note:
M ffiX
-ICO©®OO
3-6
I
I
svt~tPzx1
_ _
rc~_t;"
Data unknown
i-------
CMOS EPL 208
• Configurations of EPL Logic
RICOH EPL 20B Series
Group I provides 32 input terms and 32 product terms.
RICOH EI'L 20B Series
Group II provides 32 input terms and 64 product terms.
Input pins in both groups are activated for regular logical operation at a TTL level.
All intersection points of the input terms and product terms are provided with an EPROM cell connection. These inter·
sections are connected prior to delivery.
The AKD gate are illustrated in logic diagram (a) below. The switches indicated in logic diagram (b) correspond to the
EPROM cell connections. All switches are closed when the devices are unprogrammed.
As illustrated in logic diagram (c). when neither positive input (I ) nor negative input (T) is programmed. the AND output
(1']) becomes ··inactive".
When both positive input ( I ) and negative input (T) are programmed. the AND output (P2) becomes "don't care" logically.
Each output includes a FEATURE cell in addition to the programmable AND·FIXED OR logic. The FEATURE cell enables
the user to program the logic polarity (active·high/ active low) and the logical OR, Exclusive-OR case.
,lr-v;
~
P,
~
P,
p,
a
a
1
1
a
1
+
: Programmed
'*
: Unprogrammed
(Connected)
(Open)
p,
(e)
I,
(b)
Group I Block Diagram
Group II I/O Block Diagram
Group II Registered Block Diagram
Future 2
POLARITV
I ,~,
jc>1 ~H
~~.'''ro.''m I '~=:=J c>1
I
-'"'J
--------ICD®®[}{]3-7
CMOS EPL 208
Logic Diagram
Logic Diagram
EPL10P8B
EPL12P6B
lIFUTS{o-31)
-i6=
,
+;:l
~
-i6=
,
-i6=
~'
+;:l
1bJ
-i6=
I
-i6=
~
+;;;:1
~
~
0
~~
,
0
~,
+;;;:1
~
f1i1aJ
.+;;:l
,
~
~'" ,
~
.~
.+<;;:l
.~
,
...
,
l5la)J
f1i1aJ
,
Logic Diagram
Logic Diagram
EPL14P4B
EPL16P2B
INCREM£NT
~
,
~
f1i1aJ
I
INPUTS (O-31l
.
.~
·
~
,
,
~~
J1)i3;J
,
~
. f11iaJ
~
,f11iaJ
·
~
,
~
J~
,
,
·
·
-·IID©®OO--------------3-8
CMOS I PI ;JOB
Logic Diagram
Logic Diagram
EPL16PBB
EPL16RPBB
•
Logic Diagram
Logic Diagram
EPL16RP4B
EPL16RP6B
rlRST'~
~
-------
~---
--------------~IlD©@DO~
3-9
CMOS EPL 20B
Packaging
r:-----
20-Pin Plastic DIP Packaging I-Shot (Unit: mm)
24
2'01 _ _ _
-:1
C1O]
10
.0 98 T
Y P
1
51 Y P
-~--
0/
/15
20-Pin Ceramic DIP Reprogrammable (Glass Seaied with a quartz window) (Unit: mm)
o
-ICD©®OO-~----~3-10
0
E P
L
APPLICATION MANUAL
Version 0.1
•
3-11
;::::::::::::::::::::::::~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
EPL APPLICATION MANUAL
(INDEX)
:: :: :: :: :: :: :: :: :: :: :: :: :: :: :: ::~:::: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :: :~ :: :: :: :: :: :: :: :: :: :: :: :: :: ::
Issued on December 1, 1987
CHAPTER
1
1- 1
Introduction
1- 2
Architecture of EPL
1-2-1
Feature
1- 2- 2
Configuration of EPL
1- 3
Specification of EPL
1- 3 - 1
Absolute maximum rating
1- 3 - 2
Characteristics of EPL
1- 4
EPL logic mode
1- 4 - 1
FEATURE CELL
1-4-2
Security
1- 5
Program mode
1- 5 - 1
Programming mode
1- 5 - 2
Program/Verify mode of AND Array
1-5-3
Program/Verify mode of FEATURE CELL
1- 5- 4
Programming characteristics and timing diagram
1- 5 - 5
Address table
1- 5 - 6
Preload mode
1- 6
Upper compatibility of EPL
CHAPTER 2
2- 1
"EPLASM" Design method
2- 2
Example of design using "EPLASM"
2- 2- 1
Design of 4 -Bit-Shift-Register
2- 2- 2
Example of application of incorporating logic circuit diagram into EPL
3-12
CHAPTER
1- 1
1
Introduction
PLD (Programmable Logic Devices) is the logic ICwhich allows user to program the specification
of his own, and allows to realize the logic equivalent to several pieces of standard TTL logic ICs.
Computer system consists of microprocessor, memory and peripheral circuits. The integrity of
memory, processor and etc. with improved general-purpose properties has been enhanced, and
system is compact and provides high performance. However, since the inherent peripheral circuits,
which constitute the system, can not be used in common with other systems, a number of TTL
have been incorporated. PLD is the one that meets the requirement for making peripheral circuits
inherent to this system LSI.
The fundamental configuration of PLD is based on the theory of "Any Boolean expression, no
matter how complex, may be written in sum-of-products form". In other words, PLD is configurated from AND Array, which generates product term of input signal, and OR Array, which takes
the sum of product term.
Generating method of this AND-OR Array is classified in the following 3 kinds.
(I) AND fixing, OR programmable
(2) OR fixing, AND programmable
(3) AND· OR programmable
(PROM)
(PAL)
(FPLA)
AND fixing, OR programmable PLD of (1) fixes decode logic on AND Array beforehand, as
shown on Diagram l-l-l-(a) and allows user to program OR Array. To configulate logic circuits
with PROM, truth table is written as it is.
In the OR fixing, programmable PLD of (2), OR Array have been connected beforehand, as
shown on Diagram 1-1-1- (b) and AND Array is already user programmable. EPL offered by
RICOH is of this configuration and allows erase and rewrite since it uses EPROM memory cell.
AND-OR programmable PLD allows both arrays programmable, as shown on Diagram 1-1- 1(c), and offers high level of flexibility to the user, nevertheless, undergoes delay in 2 step array and
provides complexity in design compared to PAL.
3-13
•
, , ,
rv
OR Proglamable
IV
--
(V
(V
'rv
- -
r-
- -
-
H2
-
-
+-Q
-
'-Q
-
AND Progr arnable
(a)
PROM
-
~
-
-
~
-~
~
+--Q
AND Progr arnable
(c)
PAL
OR PrograrnalJle
I"
-
( b)
-
Ie(
FPLA
Diagram 1 - I - I
ConfIguration diagram of various PLD
3-14
1- 2
Architecture of EPL
1-2-1
Feature
Lower power consumption and higher reliability with CMOS EPROM process
(2) Ceramic packaged product is capable of erasing ultraviolet rays
(3) Number of product term: 32 (Group I) Twice as much as the counterpart of PAL offered
by MMI Co.
64 (Group II)
(4) Replaceable with general-purpose logic
(5) Package: 20 pins 300 mil plastic DIP
: 20 pins 300 mil ceramic DIP (with window)
(6) Output polarity is programmable for each pin
(7) Data copy preventive function attached
(8) Input to output propagation delay time: Series 20B 35 ns (MAX)
(9) FEATURE CELL (OR, XOR) increases flexibility in logic configuration.
(10) Upper compatible with PAL of MMI Co. at pin level
(1)
1-2-2
Configuration of EPL
EPL is the programmable logic device (PLD), using CMOS EPROM process technology. With
EPL, it contributes to the compactness of the system, reduction in cost and saving in power consumption when "FEATURE CELL" architecture is induced.
Group I consists of AND-OR (fixed), while Group II consists of 2 configurations of AND-OR
(fixed) and AND-OR (fixed)- Register.
Block diagram of EPL is shown on Diagram 1-2-1.
019
018
017
016
015
014
013
012
FEATURE CELL
Program & Verify
circuit
==:> : Program Path
- - - : Logic Path
Diagram 1 - 2 - 1
Block diagram of EPL
3-)5
•
In the block diagram, the flow of signal during logic mode (during operation as logic circuit) is
represented by -+, while the flow of signal during program mode by ~. EPL makes the flow of
signal during logic mode completely independent, and is so designed that the delay in signal during
logic mode is minimized.
Fundamental configuration components are input buffer, AND Array, OR circuits and output
buffer. Reciprocal signals are generated at input buffer for all inputs and becomes the signals to
AND Array. The program of AND Array means to select the required signal among signals from
input buffer and generate the product term desired by user. By passing the output of this product
term through OR circuits, product sum Boolean equations is executed on the device. In addition
to this fundamental PLD configuration, the setup of register and feedback input will materialize
sequential circuit.
"FEATURE CELL" circuit, polarity circuit, AC test circuit, automatic powerdown circuit are
not found in the conventional PAL.
"FEATURE CELL" circuit is the circuit which allows the user to select each condition of
"BYPASS" "OR" and "XOR". "BYPASS" provides the same function as for the PAL equivalent
product, while "OR" allows to double the number of input product term to OR circuit, and
"XOR" executes excessive OR, or else of OR circuit output. With polarity circuit, it allows to
select the output polarity independently for each output pin. Powerdown circuit executes power
cutdown corresponding to the applicable condition of product term at EPL· GI. AC test circuit
allows to run the test at the plant (inspection for delayed time after assembling of mainly plastic
product.)
Security circuit is the circuit which prevents others from copying. Also, as mentioned at the
beginning, memory cell of EPROM is used as fuse for EPL, which eliminates the use of microscopic observation, thus, complete confidentiality is maintained.
These are the configulations being features of EPL. Meanwhile, EPL Series 20 family is shown
below and simple block diagram on Diagram 1-2-2.
Table 1
EPL Series 20 family
Product name
Group I
10 input
8 output
AND-OR/XOR Array
EPL 12P6 B
12 input
6 output
AND-OR/XOR Array
EPL 14P4 B
14 input
4 output
AND-OR/XOR Array
16P2 B
16 input
2 output
EPL 16P8 B
AND-OR/XOR Array
10 input 6 input output 2 output AND-OR/XOR Array
EPL 16RP8 B
8 input
8 feedback
8 output
EPL 16RP6 B
8 input
6 feedback
2 input output 6 output
6 register
AND-OR/XOR Array
EPL 16RP4 B
8 input
4 feedback
4 input output 4 output
4 register
AND-OR/XOR Array
~PL
Group II
Function
EPL 10P8 B
3-16
8 register AND-OR/XOR Array
1- 3
Specification of EPL
1-3-1
Absolute maximum rating
Absolute maximum rating of EPL is as follows.
Symbol
Parameters
Vee
vpp
Vee power supply voltage
Vpp power supply voltage
Series 20B
Input voltage
VI
Vo
Pd
With respect to GND
Output voltage
Unit
V
V
-0.3-14.5
-0.3-Vee+0.3
-0.3-Vee+0.3
Topr
Power dissipation
Operating ambient temperature
Tstg
Storage temperature
1-3-2
Value
-0.3-7.0
Conditions
Ta = 25°C
700
0-70
V
V
mW
°c
°c
-40-125
Characteristics of EPL
DC characteristics as well as AC characteristics of EPL, which uses CMOS' EPROM process
technology, have been highly improved compared to the conventional bipolar type PLD.
DC, AC characteristics of Series 20B are shown below.
D.C. characteristics EPL Series 20B
Symbol
(Ta=1J""70°C, Vcc=5V±5%)
Parameters
Conditions
VIN=OV-Vcc
Limits
Min.
-20
Typ.
Max.
20
Unit
III
Input leak current
VIL
"L" input voltage
-0.3
0.8
VIH
"H" input voltage
2.0
Vcc+0.3
V
VGL
"L" output voltage
Vcc=MIN,IOL=8mA
0.5
V
"H" output voltage
Vcc=MIN,IOH=-3.2mA
2.4
Vo=OV-Vcc
-20
VOH
0.3
JlA
V
V
4.4
OFF state
output
ILO
leak current
Gil
20
JlA
40
mA
50
mA
60
mA
Vcc=MAX, output
GI
Iccl
Supply current
current
Vcc=MAX, output
Gil
Supply current
current
(operation)
Vcc=MAX, output
=open, Vi=2.4V
(standby)
Icc2
=open, Vi=GND or Vcc
=open, Vi=GND or Vcc
Vcc=MAX, output
=open, Vi=2.4V
70
mA
GI
Vcc=MAX, output
50
mA
Gil
Vi=0.8V or 2.4V
70
mA
=open, f=1 OMHz,
3-17
I
A.C. characteristics of EPL Series 20B (Ta=CT-70°C, Vcc=5V±5%)
Symbol
Parameters
Typ.
Min.
I nput or feedback to output
25
35
nS
15
25
nS
R2=1.1kn
CL =50pF
15
15
25
25
nS
nS
25
25
35
nS
35
20
nS
MHz
Input setup time
20
20
25
nS
nS
Input hold time
a
nS
Clock to output or feedback
Propagation
delay time
Pin 11 to output enable
Pin 11 to output disable
Group II
I nput to output enable
I nput to output disable
Max. frequency
tplZ
tplX
f MAX
tWL
Low
High
1
Min. clock width
tWH
tsu
tH
Unit
Max.
R1=560n
tpD
tCLK
tpzx
tpxz
Limits
Conditions
I
nS
Input wave shape (During measurement of A.C. characteristics)
Output load
51/
INPUT PULSES
+3.0V~
__ _
l
---
Rl
560Q
ov
-'-.:l5ns
----o
Output O----~>-----....
RZ
CL
1.lkQ
+30v
Test Point
10%
Ir
-
If
--15n1-
--7\
Test j i9 capacity
included
90%
ffo
ovJ-t-==J[
5ns
5ns
A.C. characteristics is measured at 1.5V
point of both input and output.
t:
Timing diagram
5V
Clock
Input or
feedback
Registered
Output
---------------
~1.51/
----=*=
-
~twH~::::(1*«:-I___
. 51/--twL-~~15V
~
tsu----->"*k"t=~ ~-1-5-1/-------------------
-*
//Iffuffi'l////$m/Z(iV*'----_-_-=--=--=----=--=--=--===
~
~r
K---tCLK=:?1_
tpo
~:~i;atiorial I#$W////$E/mA\~~At============
iL
t=IPxz-----7!
pinl1
Output
----:--_*1.51/
k
t"x
-:
---------------
. \E-IPlX--7J
151/~~_
1-
~tP1Z
Hl-Z
11////11<
_ .
--------
-----------~
Note:
)~
Data unknown
3-18
Series 20B is fabricated under the same process technology as for 256K· CMOS· EPROM
(RD27C256). This process is the latest CMOS
two-layer polysilicone gate process which has
materialized high performance of access time 150 ns
with 27C256 upon adoption of 1.5/l rule EPROM
CELL. Thanks to this, the same delay time of
35 ns as for the standard product of bipolar PAL has
materialized.
Power supply voltage dependence characteristics
of input to output propagation delay time ( tPD ) at
room temperature is shown on Diagram 1-3-1,
while temperature dependence characteristics at
Vcc=4.7V on Diagram 1-3-2. It is readily seen
from Diagram 1-3-1 that Series 20B gives tPD-20
ns under the standard operating condition (V cc=
5.0V, room temperature: 25°C).
Diagram 1-3-3 illustrates the characteristics of
current consumption (Icc) in the case where 16
pieces and 32 pieces of product term are respectively used. From Diagram 1-3-3, when EPL· GI is
used in place of PAL (when 16 pieces of product
term are in use), Iccl=5.5mA (in static) and
Icc2=8mA (in motion : at 10 MHz) (standard
operating condition).
Diagram 1-3-4 and 1-3-5 illustrate the output
drive capacity. From Diagram 1-3-4 and 1-3-5,
Ioh=3.5mA (at Voh=4.4V) and Iol=IOmA (at
Vol=0.3V) at Vcc=4.7V, room temperature.
(f)
c
oD..
:
60
50
E
.~
>-
T a ~ 25°C
output load condition
40
:gj'" 30
v
~
B20
:J
o
:J
0.
~
EPL16P88
:J
10
Output
terminal
l.lkQ."
c:
4.0
4.5
5.0
5.5
560Q
J
50 F
P
6.0
Power supply voltage Vee WI
Diagram 1 - 3 - 1
Power supply voltage and
input output delayed
time characteristics
(f)
c:
Vee
-;; 60·
~
4.7V
D..
: 50
E
;:. 40
a;'"
"0
30
'::;
920
:J
I
EPL16P88
..
..
o
25
0
'::; 10
0.
-'=
70
Ambient temperature T a (oCI
Diagram 1 - 3 - 2
Temperature characteristics of
input output delay time
I
~ 40
tl 35
~
:;
I!=IOIIH.) When 32 pes. of
KU"
l.u.lby
/
30
u
>- 25
0.
"~ 20
~
/1.
~
'«~OMH'll When
16pcs. of product
term are 10 use, (Compa-
15
.... by
tible with PAL lOl81
EPL 10PSB
T a ~ 25°C
Output ~ Open
4.0 4.5 5.0 5.5 6.0
Povyer supply voltage Vee (VI
Diagram 1 - 3 - 3
3-19
product
term are In use.
E
Power supply current
characteristics
~
I
a
EPL 10PSB
~
Vcc=4.7V
4.7
Ta=2S'C
...J
a
> 4.5
"
o~ 4.3
"
C>
~
0
>
:J
B::l
0.5
> 0.4
0.3
>
4.1
~
::l
0.2
0
0.1
B::l
a 3.9
~
I
o
-1.0
-z.o
4.0
-3.0 -4.0 -5.0 -6.0 -7.0 -8.0
Diagram I - 3 - 4
6.0
8.0 10.0 12.0 14.0 16.0
Load current IOL (mA)
Load current IOH (mA)
Load current and "u" output
voltage characteristics
Diagram I - 3 - 5
3-20
Load current and "L" output
voltage characteristics
1- 4
EPL logic Mode
EPL has EPROM memory cells at all intersections of product term on the AND Array
and input term. For example, when converting Boolean equation, that is, Z I = A * B *
C + A * B * D ( * • • AND, + • • OR), to
gate level, it is described as Diagram 1-4-1.
1-4-1.
Then, when representing Z 1 as input term,
A,A B,B C,C D,D and as logic diagram of
2 pieces of product term, it is readily seen
that Z 1 = A * B * C + A * B * D is represented when connecting intersections, as
shown on Diagram 1-4-2.
X mark on the logic diagram represents the
condition under which CELL of EPROM
remains unprogrammed.
A
A
i~------L-__
Diagram 1-4 - 1
-
Z,
-
Z1=A*B*C+A*B*D
cc
•
-- Input Term
Product Term
~
z,
A
" ;;>
>
c--I>
B
o
.2
Diagram 1 - 4 - 2
Logic diagram of Z 1
As shown on'Diagram 1-4-3, CELL of
EPROM corresponds to the switch of AND
gate input, and when it is programmed, switch
opens. Here, if all SW1-SW4 are kept OFF
condition, that is, if EPROM is programmed
AND gate outputs "H" since it is PULL-UP,
as shown on Diagram 1-4-3.
sw'~
SW2
~SW3
SW4
12
Diagram 1-4-3
3-21
EPROM connection
As shown on Diagram 1-4-4, if intersection is (a), switch is OPEN, which indicates
the programmed condition. If intersection is
(b), switch is closed, which indicates the unprogrammed condition. Therefore, it readily
suggests to program EPROM CELL at the
intersection not required by design (tum the
switch OFF). For example, as shown on
Diagram 1-4-5, if I 1 and I 1 are not
programmed together at (a), AND_output
P 1 turns to non-active (P 1 = I 1 * I 1 = 0),
and if I 1 and I 1 are programmed together,
AND output P 2 turns logically to "Don't
care"(P2 =1 I * I I = 1).
(a)
(b)
+
+
Program (open)
Not Program (connected)
Diagram 1-4-4
Status of intersection
(il)
'J'"""-*---I-- 11
V"~---*"---+-- f1
(b)
r--+--+--- I!
--+----lIf---1?
'v--+--+-- 13
'---*--+---13
Diagram 1-4-5
1-4-1
Relationship between intersection
and output
FEATURE CELL
FEATURE CELL architecture has been adopted to EPL to allow user to enhance integrity and
handle easier.
FEATURE CELL consists of logic gate of "OR" and "XOR", logic gate of "POLARITY" and
PROM switch which selects those. Furthermore, EPL· GI has the product term of 32 which is
twice of PAL of 16. EPL· GIl allows adjacent output channels to obtain share. In other words,
EPL has the integrity 2 times to 4 times more than PAL.
Next, output block configuration of EPL is described. Diagram 1-4-6 illustrates the output
block of EPL· GI, Diagram 1-4-7 for output input block of EPL . GIl and Diagram 1-4-8
for register block of EPL· GIl. The position of switch shown as (DEFAULT PATH) in the
diagram is set at the time of shipment (erase condition). Under the erase condition, output polarity
is ACTIVE LOW, and FEATURE CELL is unused, which is under the same condition as for the
equivalent products of PAL.
3-22
Group I
(default path)
Product
term
Output pin
Product
term
Diagram 1-4-6
Group II
Output block of EPL . GI
(I/O Block)
Product
term
lnputor -=======~~--t--i--~=-------------------------------------------.J
feedback
Product
•
term
Inputor-=======~b1
feedback -
______________________________________________________~
Diagram 1-4-7
Group II
Input output block of EPL· GIl
(Register· block)
Product
pin 1
)--;=:t==l-"J
term '-,~__..r-'
Feedback======~}-----i--1~-------------------+----------~
Product
term r--.__~~
Feedback======~}-----------------------------------------~
Diagram 1-4-8
Register block of EPL· GIl
3-23
plnll
1-4-2
Security
After the data has been programmed by user, EPL will for the first time execute semantic logic
operation. In other words, for the system in which EPL is used, copy is impossible unless the data
programmed in EPL is read-out. (Even copy print substrate, it will not operate unless correct data
are programmed in EPL) EPL is equipped with security circuit for prevention of copy. After programming the data in EPL, once security fuse is programmed, it will no longer be able to read the
data subsequently programmed. Diagram 1-4-9 illustrates the operation of security circuit.
Memory cell signal of AND Array selected by X- Y decoder is read-out by AND Array Sense
Amp. On the other hand, the signal of Security Fuse is read-out by Security Sense Amp. The
output SEQ of Security Sense indicates "H" if Security Fuse is not programmed, while indicates
"L" if programmed. As shown on Diagram
1-4-9, the output of AND Array and
AND signal of SEQ equal to the input of
output buffer. Accordingly, if Security Fuse
is programmed, it gives SEQ = "L" and
output becomes "L" regardless of the
condition of read-out signal of AND Array.
diagram), EPL has independent flow of
signal during programming and independent
flow of signal during operation as logic circuit.
Since security circuit only controls flow of
SECUUTY O.
T Vee
signal during programming, it will give no
Fuse
~
influence to the operation as logic circuit.
The conventional PAL has also similar
Diagram 1-4-9
Security Circuit
function available which is called last fuse.
However, in case of PAL in which blown
type fuse is used, the programmed fuse is
physically blown and if IC chip is microscopically observed, it enables to decode the programmed
data. Contrary to this, in case of EPL, memory cell of EPROM is used and programming is
executed by movement of electron. Therefore, it is impossible to decode the data through microscopic observation. Accordingly, the use of EPL will completely wipe out the sense of insecurity
against leak of security remaining with the system configurated with standard IC and PAL of TTL
and etc.
3-24
1- 5
Program mode
1-5-1
Programming mode
Programming of EPL is executed in the same manner as usual EPROM. Pin out of program
mode is illustrated on Diagram 1-5-1. For EPL, application of program voltage (Vihp) to pin 1
(Vpp) will change it from usual logic mode to program mode and at which time, Group I turns to
128 X 8 bit EPROM, while Group II to 256 X 8 bit EPROM.
Meanwhile, there are two different program modes available as follows. (Mode table is shown on
Diagram 1-5-1).
• Program/Verify mode of AND Array
• Program/Verify mode of FEATURE CELL
PRELOAD/52/ AS 4
FPM/A4 5
Diagram 1-5-1
1-5-2
•
Pin out for program mode
Program/Verify mode of AND Array
This mode operates program and verify of AND Array.
(1)
Program
1
/
Vpp
(lPIN)
~
VIHH
FPM
(5PIN)
.--I
S1. s2
I
tSH
H ~
~
~
D<
O.4PIN)
DATA
00-07
~
VIHH
\
/
PGM/QE
tDS
tew
tDH
tDPW
3-30
tos
P
tDD
1-5-5
Address table
Address table
(Group I)
Address table
INPUT LINE No. VS. ADDRESS
INPUT LINE No. VS. ADDRESS
INPUT
LINE
NUMBER
A4
A3
A2
Al
AO
0
0
0
1
0
0
1
0
1
2
3
4
5
6
7
11
12
13
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
2
3
4
0
0
0
0
0
0
0
1
1
1
0
0
15
16
0
1
17
18
19
20
21
30-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
31
1
INPUT
LINE
NUMBER
ADDRESS PIN STATE
5
6
7
8
9
10
22
23
24
25
26
27
28
29
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
1
01
48
49
57
58
59
50
51
)ltl
!j2"
§Y Vsy
,/W' flV
/~3/ ft,
02
40
41
42
43
03
04
32
33
34
24
25
26
27
35
4¥ ,.&
..,,45/ )If
fi
~
05
16
17
18
19
V VlV
A"1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
0
1
1
30
31
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
27
28
29
Al
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
•
1
-0 r;0
1
0
0
1
AO
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
1
0
1
1
0
1
0
D1
A7
A6
AS
DO
8
9
10
0
1
0
0
0
1
56
11
3
0
1
0
1
~
~
0
0
0
L
X
1
JY
V~
ADDRESS
PIN
STATE
PRODUCT LINE NUMBER
D6
2JY /12/ /4
)1
0
0
1
1
0
0
1
1
A2
1
1
PRODUCT LINE No. VS. ADDRESS
ADDRESS
PIN
STATE
.zy V21L L3
¥ VJq/ A J4.
0
0
1
1
0
0
1
1
0
25
26
PRODUCT LINE NUMBEIt
56
1
1
1
0
0
1
1
23
24
0
1
A3
1
20
21
22
PRODUCT LINE No. VS. ADDRESS
DO
A4
1
18
19
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
ADDRESS PIN STATE
8
9
10
11
12
13
14
15
16
17
0
1
0
1
0
0
1
(Group ")
57
01
48
49
02
40
41
58
50
59
51
52
53
42
43
44
45
46
47
/JY
60
VL
61
Y vy v)" l(~9r"
_IB' IC'Y VY IC'~ iL..k'"
~ : Unused area
3-31
62
63
54
55
Dl
32
04
24
33
34
35
37
25
26
27
28
29
38
30
39
31
36
05
16
17
18
19
20
21
22
23
D6
07
A7
A6
AS
8
0
1
0
0
1
1
0
0
0
9
10
11
12
13
14
15
0
0
1
0
1
2
3
4
5
6
7
0
0
1
1
1
1
1
1
0
1
0
1
1-5-6
Preload mode
Since EPL with register attached executes inspection of logic operation including register, it is
equipped with preload function of register. With this function, it is possible to load any optional
data on the register pin (output pin with register attached: e.g. for EPLl6RP6, 6 terminals from
pin 13 through pin 18) to the register.
For EPL with register attached, input of AND Array is determined by the signal from input
terminal and feedback signal from the register. With preload function and by determining the
condition of this feedback signal, it enables to execute initial setting of AND Array and inspection
of logic operation.
• Preload
-
I
equation
FUSE PLOT
implementing function
!
,-
I
-
I
Boolean
Truth table
I
,
lJEDEC file
for PAL
f--<
Data implementIng. unctIon
for programmer
f--<
Test vector implementing
function
b;
~
Simulation function
PAL ..... EPL dilta
conversion function
/'
I
FUSE PLOT
J
<-
>-
Il JEDEC
fileJ
for EPL
"-
Il Simulation
J
results file
>I
Design document
implementing function
Boolean
equation
I
OQSign
I
document
-
~-
Diagram 2-1-4
I
/'
~;Ef66'e~~n~~~~~ ~8~n~~
lJEDEC filel
for EPL
Output>
-
Fault simulation function
<
..i
<
EPLASM
Function of EPLASM
E= ECHOES EPL DESIGN SPECIFICATION
P PRINTS THE ENTIRE FUSE PLOT
B= PR INTS ONLY THE USED PRODUCT LINES OF THE FUSE PLOT
J = GENERATES JEDEC PROGRAMMING FORMAT
A= PRINTS ALL NECESSARY OUTPUTS
C=CONVERTS MMI JEDEC FILE TO RICOH JEDEC FILE
M= GENERATES BOOLEAN EQUATIONS FROM AN MMI JEDEC FILE
V= GENERATES BOOLEAN EQUATIONS FROM A RICOH JEDEC FILE
T=SIMULATES FUNCTION TABLE VECTORS IN THE LOGIC EQ.S AND GENERATES TEST VECTORS
F = PERFORMS FAULT TESTING
R= PROCESSES ANOTHER EPL
Q= EX IT EPLASrot
=
Diagram 2-1-4
Example of command of "EPLASM"
"EPLASM" will confirm through simulation whether or not there is a contradiction between
product sum Boolean equation input by user and truth table, and convert it to "JEDEC FILE"
which is readable form of writing device' (programmer) to EPL. Also, it implements fuse plot,
executes fault test and confirms whether or not the test vector implemented from truth table
suffices operation of complete logic test. (Command "F")
3-38
In addition to these functions, it has the following functions, i.e., data conversion function from
PAL-use to EPL-use (used to convert the data of written PAL to EPL-use, Command "C"), and
the function of reverse conversion of data read-out from programmed EPL to Boolean equation
(Command "M", "V"). In addition, the input of source file can be implemented either through disc
file or direct input by interactive form. Those directly input can be saved as file. Furthermore,
the resulted output can be implemented as file form of disc or direct output to CRT. (Execute
for command other than "C", "M" and "V". Command "R").
Since "EPLASM" having these functions is written in FORTRAN 77, it allows an easy conversion
among different types of machines.
Once "JEDEC FILE" is implemented by EPLASM, it transmits to programmer and programs
EPL. Following are the programmer approved by RICOH at present.
EPL programmer list
Name of company
As of April, 1987
Body
Required accessories
Feature
Model 1870A
Model 1900
7SP-EPL20
OU-193
Model 29B
Model 60A
LOGICPACK +
303A-009
360A-00lV05
Advantest
TR 4931
TR 49301
Operation possible without personal
computer and software thereof is
coordinative.
Japan Macnics
PROMAC P3
(Ver 3.0)
R&D
FLEXY
SYPLA III
PALPACK
PAL 2040
EPLASM class assembler built·in
AVAL
Packer 10
EX-1
Hyrel
EPL writer
Ver 1.2
Yashiro Denki
EPL writer 20
Minato Electronics
DATA I/O
PLD development supporting system and development tool
Name of company
Name of software
Name of system
Required accessories
Feature
Yokogawa Hewlett
Packard
9000 Series
PLD development system
DATA I/O
Model 60A/29B
Execution possible from circuit
diagram input
Automatic logic fragmentation/
optimization up to 5 pes. possible
RICOH Co .. Ltd.
EPLASM
IBM-PC
NEC PC 9800 Series
Operation on MS-DOS
DATA
ABEL
IBM-PC
NEC PC 9800 Series
Operation on MS-DOS
I nput from state transition diagram
and truth table possible
CUPL
IBM-PC
NEC PC 9800 Series
Operation on MS-DOS
I nput from state transition diagram
and truth table possible
I/O
Japan Macnics
Co., Ltd.
3-39
2- 2
Example of design using "EPLASM"
2-2-1
(1)
Design of 4-Bit-Shift-Register
Relating to circuit function
The example of design of 4-Bit-Shift-Register is shown, which 'has 4 circuit functions of Shift
Right, Shift Left, Load (Load signals of DO ~ D3) and Hold (maintain the condition as it is) with
selective signals S I and SO. Collected circuit functions are shown on Table 2-2-1.
Selective signal
SI
SO
0
0
I
0
I
0
I
I
Circuit function
Load
Shift-Right
Shift-Left
Hold
Table 2-2-1
Circuit function
As shown on Table 1-2-2, it enables to materialize sequential circuit since EPLl6RP8, l6RP6
and 16RP4 have register and feedback installed. 4-Bit-Shift-Register requires 7 input (Clock pin,
selective pin S I, SO, Load pin D3~DO) pins, 4 output (QO~Q3) pins and input output
(Right-In & Left-{)ut, Left-In & Right-Out). Those which satisfy this requirement are EPLl6RP6
and 16RP4. Here, design takes place, using EPLl6RP6.
(2) Relating to each STATE
Load(Sl * SO) means to Load D3, D2, Dl and DO to each output (Q3, Q2, QI and QO).
Shift-Right (S I * SO) means to shift right at the next step (next condition with clock attached).
Left -in
D
--. I
03
02
01
00
+++
Diagram 2-2-1
I --. D
Right-out
Shift-Right
In other words, as shown on Diagram 2-2-2, the signal of Right-in is output to Q3, while the
signal of QO to Right-{)ut at the next step.
Q3 02 01
00
Right-out
t-
Diagram 2-2-2
At Hold (S I
*
D
Left-in
Shift-Left
SO), previous condition is output at the next step.
(3) Input file implementation to "EPLASM"
Diagram 2-2-3 shows the architecture of EPLl6RP6. As readily seen from the diagram, pin
19 and pin 12 have the archtecture of 3-STATE. Accordingly, these 2 pins are used as input
output pin (LIRO: Left-in & Right-{)ut, RILO: Right-in & Left-{)ut).
3-40
Also, each output (4 pins within pin 13~pin 18) is Active Low. In the design of this time,
Boolean equation (expresses the input of D flip-flop) i~ expressed by QO, Q 1 and Q 3, taking into
consideration Active Low. Also, it is always necessary for input to pin 11 to be "L".
Diagram 2-2-3
Architecture of EPL16RP6
•
Then, designate each pin as shown on Table 2-2-2.
Pin No
1
2
'J
J
4
5
6
7
8
9
10
Pin Name
CK
S 1
SO
03
02
01
DO
NC
NC
GNO
Table 2-2-2
Selective signal
SO
0
0
0
1
1
1
S1
0
1
1
0
0
1
Circuit function
Pin No
Pin Name
VCC
20
19
18
17
16
15
14
1 J'J
1 ...')
1 1
LIRO
NC
QO
Ql
Q2
Q3
NC
RILO
OE
EPLl6RP6 PIN assignment
Output
Input Output
LIRO RlLO
Loa d
Shift - Righ t
X
X
X
X
Shift-Left
1
0
1
0
0
1
HoI d
X
X
Table 2-2-3
0
1
State transition table
3-41
Q3
03
1
0
1
03
03
Q2
02
03
1
D3
02
02
Ql
01
02
03
02
1
1
QO
DO
Dl
02
1
0
0
( X: Uncertain)
DO
01
Boolean equation is implemented on the basis of Table 2-2-3. Let's think of output Q3.
Load
(sT*so)
Shift-Right
(Sl SO)
Shift - Left
(S 1 * SO)
Hold
(Sl*SO)
*
Q3:=ST*so*03
(D3 turns to input of D-FF)
Q3: =ST*s 0 *RI LO
(Right-in turns to input of D-FF)
-- --
Q3:=Sl*SO*Q2
(Q2 turns to input of D-FF)
Q3:=SI*SO*Q3
(Q3 turns to input of D-FF)
As well, when thinking of Q 2, Q I and Q 0, they are as follows.
Q3:=IT*80*03
.---
+S
1
Q2:=ST*so*02
--+81*80*Q3
+81*80*Ql
+81*80*Q2
* S 0 *RILO
+81*SO*Q2
+81*SO*Q3
QO:=81*SO*00
+S1*80*Ql
+S
1
* 8 0 *LIRO
+Sl*SO*QO
With regards to 2 input output pins of RILO and LIRO, RILO is used as input pin, while LIRO
as output pin at the time of Shift-Right. Accordingly, RILO is turned to high impedance condition
(Z). When Shift-Left, LIRO is turned to high impedance condition. Above will represent as
follows in case of input file to "EPLASM".
IF (8'I*SO) LIRO=QO
IF (Sl*80) RILO=Q3
If Boolean equation of IF statement in the next parenthesis is false, it indicates that high
impedance condition is allocated to the output. If Boolean equation in parenthesis is true, it
indicates that Boolean equation of right side is allocated to the output specified under the next pin
name.
3-42
OUTPUT
-
I~~PUT
Loa d
ShiftRight
ShiftLeft
HoI d
S 1 SO R·in L·in
X
X
0
0
1
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
X
1
0
0
1
Table 2-2-4
1
X
Q3 Q2 Ql QO R'out L'out
X
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
Z
0
0
0
0
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
Z
Truth table of 4·Bit·Shift-Register
(X : Uncertain, Z: High impedance, R·in: Right-in,
R . out : Right-out, L· out: Left-out)
·3-43
L·in: Left-in,
As mentioned heretofore, the configuration of 4-Bit-Shift-Register is as shown on Diagram 2-2-4
,CK,,,
FIRST
FUS~
..
..
IN
"!I
M NT
I!"~
"'011·'1111'"
Itmlll
2OZ1IlD
J'2S1U'
»BJII)I
~
=tR
NUMBE RS~~ ~
,
,: !
,
,~
D' ,
~
......."'.
....
~~-
lIRO,
~ ~'l
~
~~
",,,
.",
-1~
.1611
So
..."'''
~11
~~
..
5J1611
~~
"'.
Itbr
::
or"
~~
~~
...
~
...
"...
","
8§o;JI
!l."'Sl!
95:11
?:sa
,
~4l
~
lQZ'12
IIt: JS
II!>,? •
111'31
11" •
D1
11• •
.
,,.,
,,. "
:::
~
~
~
Ir~"'" ~
1)1,('
1116&3
W'l.
15001 u
Do
a
..........
.
"" .
:::
..........
,,''''.
-g
,,
""
NL'''''
1&32 11
~
~
~~b~71
~70 I
,'
'Wi'
'
t-C m...
,,:1
"I' ,.1111
12ll1UI
nil..
IUlZlD
"'lU1l1
.ZUII'-4---- INPUT TERM
NUMBERS
Diagram 2-2-4
Configuration of 4-Bit-Shift-Register
3-44
1J2053 NC
'8
bo'
t-J-po-00
17
t-J lOS'
V
~206Z
-vo-
02
15
-;;]'206503
bo'
14
~206aN
-PX>-'
RILO,
4E,
Input file to EPL support software "EPLASM" is shown on Diagram 2-2-5.
EPL16RP6
DESIGN SPE=IFICATIDN
A.TJUR.181985
SHIFT REGISTER
RICOH CO.LTD.
OSAKA. JAPAN
CK
51 50 OJ DZ 01 00 NC NC GND
OE RILO NC QJ QZ Q1 Q0 NC LIRO UCC
/QJ
:=/S1#/S0¥/DJ
+
/S1¥S0¥/RILO
S1>:/S0¥/QZ
S1¥S0#/QJ
/QZ
:=/S1¥/S0¥/DZ
/S1¥S0¥/QJ
S1#/se¥/Q1
S1>:S0¥/QZ
/Q1
:=/S1#/S0>:/D1
+
/S1¥S0:t/QZ
S1¥/S0¥/Q0
+
S1:tS0:t/Q1
/Q0
:=/S1#/S0¥/D0
+
/Sl:tS0>:/Q1
S1>:/LIRO¥/S0
+
S1ltS0:t/Q0
IF(/S1>:S0)/LIRO=/Q0
IF(51:t/S0)/RILO=/QJ
FUNCTION TABLE
QJ QZ Q1 a0
CK
51 S0 OJ DZ 01 00 OE
RILO
LIRO
S.R
;LOAD
C
C
L
L
L
H H X
: SHIFT RIGHT
L
H X
C
C
H X
L
C
H X
L
C
H X
C
L
H X
: SH 1FT LEFT
C
H L
X
C
C
H
H
H
H
:HOLD
C
C
C
H
L
L
L
L
X
X
X
X
H
X
L
X
L
X
L
X
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
X
X
X
x
X
L
L
L
L
L
L
L
L
X
X
X
X
X
X
L
L
L
L
L
X
X
X
L
Z
Z
X
X
X
X
X
X
X
X
H
L
H
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
----------------------------------------------------------DESCR 1 PTI ON
THIS EXAPLE ILLUTR,:;TES THE USE OF EPL
END
Diagram 2-2-5
TO
IMPLEMENT THE SHIFT REGISTER.
Input file to "EPLASM"
3-45
"JEDEC FILE" which is the execution result of "EPLASM" is shown on Diagram 2-2-6.
EPL16RP6
DESIGN SPECIFICATION
S.R
A. T JUR.1B 19Bs
SHIFT REGISTER
RICOH CO, LTD.
OSAKA,JAPAN
:lFfU
L8899 1911 9111 1111 1111 1111 1111 1111 1111 :I
L89J2 1111 1111 1119 1111 1111 1111 1111 1111 :I
L9s12 1911 1911 1111 1111 1111 1911 1111 1111 :I
L8s44 1811 8111 1111 11111 1111 1111 1111 1111 :I
L8s76 81111 11111 1111 1111 1111 1111 1111 1111 :I
L968B 8111 9111 1118 1111 1111 1111 1111 1111 :I
L976B 1811 1811 1111 1)11 1811 1111 1111 1111 :I
L8B89 1811 9111 1111 1111 1118 1111 1111 1111 :I
L9B:J2 8111 1911 1, 19 1111 1111 1111 1111 1111 :I
L8B64 8111 8111 1111 l ' 18 1111 1111 1111 1111 :I
L1924 1811 1911 1111 1811 1111 1111 1111 1111 :I
L 1856 11111 8111 1111 1111 1111 11111 1111 1111 :I
L18BB 8111 1811 1111 1118 1111 1111 1111 1111 :I
L 1128 8111 8111 1111 1111 1118 1111 1111 1111 :I
L12B9 1811 1911 1811 1111 1111 1111 1111 1111 :I
L 1:J12 1911 8111 1111 1111 1111 1111 1111 1118 :I
LI:J44 8111 1811 1111 1111 1118 1111 1111 1111 :I
L1:J76 8111 9111 1111 1111 1111 1118 1111 1111 :I
L 1792 8111 1811 1111 1111 1111 1111 1111 1111 :I
L1B24 1111 1,111 1111 1: 11 1111 1118 1111 1111 :I
L284B 8811 888 888 1l8e 8ee eee eee eee :I
C49E9:1
veeel ceeeeeeXXNeZXLLLLXZN :I
veee2 Cl1KKKKKKNeZKLLLLKZN :I
ve8e:J celXXXXKXNelXHLLLXLN :I
vee94 celKXXKXKNeeXLHLLKLN :I
Vgess celXXKXXXN88XLLHLXLN ,.
V8886 C81 XXXXXXN81lXLLL HXHN :t
V8887 C81XxxxXXNe8KLLLLXLN :I
V8e8B C18KXXXXKN8LXLLLHX1N :t
V8889 C18XXXXXXN8LXLLHLx8N :I
V8818 C18XXXXXXN8LXLHLLX8N :I
V8811 C18XXXXXXN8HXHLLLX8N ,.
V8812 ClexxxxxxNeLXLLLLxeN :I
V8el:J Cl1XXXXXXN8ZXLLLLKZN ,.
:J5AE
Diagram 2-2-6
"JEDEC FILE"
"JEDEC FILE" records the fuse information (information giving which fuse to write) and test
vector for logic test. For fuse information, for example, L0032 represents the 32nd fuse, followed
by 33, 34 to the right and it is readily seen that it comes to 0 at the 43rd. "1" represents write
and "0" represents no write.
Test vector represents the truth table. It indicates pin 1 ~ pin 20 from the left, C represents
the rise (from L to H) of Clock, N for Vcc (+5V) and GND (Ground) and Z for high impedance
condition. Logic verify is executed on the basis of this test vector. That is, to examine if actually
written EPL agrees with logic of test vector.
Diagram 2-2-7 graphically shows which fuse to write on the basis of input file.
3-46
SHIFT R£GI5T£R
:OUT:FUNC:LIN£:
1111111111222222222233
:PUT:TION: NO
0123 4567 8901 2345 6789 0123 4567 8901
:/19:
:/19:
IF
o
:/17:
+
+
+
7
xxxx
XXXX
xxxx
XXXX
XXXX
XXXX
xxxx
xxxx
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXX X
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
xxxx
XXXX
xxx x
XXXX
XXXX
XXXX
8
9
10
11
12
13
14
15
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
16
17
18
19
20
21
22
23
-X-- -X--X-- X---
24
25
26
27
28
29
:/16:
: /16:
:/16:
:/16:
3e
31
:/15:
:/15:
:/15,'
:/15:
:/14 :
:/14:
+
: /14:
: /14:
+
/51.S0*/Ql
SI1/:/L IRO./S0
SI.S0;;:/Q0
X--X -X--
X--- X---
---x
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
-X--X-X--X---
-X-X---X-X---
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
XXX X
---x
XXXX
XXXX
XXXX
XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXXXXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-X--
/51x"S0:t/Dl
---x
/SI*S0*/Q2
SI./S0*/Q0
SI.S0:#/(;Il
---x
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-X-- -X--x-- X--X--- -X-X--- X--XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
40
41
42
43
44
45
46
47
-X--X-X--X---
-X-- -X-X---X-X---
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
xxxX
XXXX
XXXX
XXxX
XXXX
XXXX
XXXX
XXX X
XXxx
XXXX
XXXX
XXxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
48
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXX X
XXxX
XXXX
XXXX
XXXX
XXXX
XXXX
xxxX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X
XXXX
XXXX
XXXX
XXxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX
XXX X
XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
54
55
IF
"S1*/ss;/oa
-X--
---x
32
33
34
35
36
37
3B
39
49
50
51
52
53
:/12:
:/12:
/51.50
/Q0
---x
xxxx
XXXX
XXXX
XXXX
XXXX
XXX X
6
: /17:
:/17:
: /17:
-x-- x---
I
2
3
4
5
56
57
58
59
60
61
62
63
-X--
/Sl~/se¥/D2
---x
---x
---- ---x
XXxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
xxxx
S1.Se.Y~2
XXXX
XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
XXxx
XXXX
XXXX
XXXX
XXX X
---x
---X
---x
X--- -X-XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
/SI;;:Se*/Q3
SI*/S0;;:/Ql
---x
Diagram 2-2-7
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
FUSE PLOT
3-47
/Sl1/:/se*/D3
/SI;;:S0;;:/RILD
S1;;:/S0:t/Q2
Sl;;:Se;;:/Q3
I
Also, "X" represents the fuse with no write, while" -" for fuse with write. Boolean equation
on the right represents the Boolean equation of QO "" Q3. For example, LINE NO 16 represents
the product term of Sf * SO * DO. OUTPUT represents the line of-product term to connect
with which output pin. "1" of pin NO represents that output is Active Low. "+" of FUNCTION
represents OR logic, "IF" for output condition term of 3-State.
3-48
2-2-2
Example of application of incorporating logic circuit diagram into EPL
Example of design of incorporating circuit diagram of 10 inputs 2 outputs shown on Diagram.
2-2-26 is illustrated.
CLEAR lJPHOlO~~~~~~====]=~11
4Bit-Counter
~ s':~lJ
Ii
I \
r--:
i'
74f1C4040
101 02 03 04 05 06 07
001
51
I
52
Diagram 2-2-26
10 input 2 output circuit diagram
(1) Outline of circuit
The output shown on Diagram 2-2-26 is 10 output of Clear, Count up, Hold signal of Q 1 Q8, 4-Bit-Counter which is the output of TTL 74HC4040. Also, the output is 2 outputs of S 1 and
S 2. The output A, B, C and D represent the input of TTL 74HC42 (Refer Diagram 2-2-27).
The output YO-Y9 of TTL 74HC42 and the output of NAND gate of input (JI-Q8 represent the input of NOR gate and output to S 1 and S 2.
3-49
A
c
8
Diagram 2-2-27
D
TTL 748C42
Since the circuit of 4-Bit-Counter must be configurated, D flip flop is necessary. As input pin,
a total 11 pins consisting of Clock, Q 1 ~ Q 8, Clear, Count or Hold of Counter is necessary. The
ELP that satisfies this requirement is EPLl6RP4. Also, since II input pins are required, 12 pins of
EPL16RP4 and 18 pins of input output pin are used as input pin. (The use of 3-State inverter
offers possibility of materialization Refer Diagram 2-2-15)
Next, each pin designation of EPLl6RP4 is shown on Table 2-2-9.
Pin No
1
2
3
4
5
6
7
8
9
10
Pin Name
C L K (Clock)
Pin No
2 0
Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
G N 0 (Ground)
Table 2-2-9
1
1
1
1
1
1
1
1
1
9
8
7
6
5
4
3
2
1
Pin Name
VCC(+5V)
S 1
C L R (Counter ,clear In)
A
B (4- Bit-Counter(J)
Output)
C
0
S2
C NT (Counter, Up, Hold In)
OE
Each pin designation of EPLl6RP4
(2) Implementation of product sum Boolean equation
To implement product sum Boolean equation relating to output S I and S 2, first of all, the
output of TTL 74HC42 by output A, B, C and D of 4-Bit-Counter is shown on Table 2-2-10.
Also, from the circuit diagram of Diagram 2-2-26, the output Q I ~ Q 8 of TTL 74HC4040 represents the input of 9 pieces of NAND gate (a ~ i) and the output of TTL 74HC42 is also
configurated with NAND gate. The output of this a ~ i and the output Y 1 ~ Y 9 of TTL 74HC42
represent the input of NOR gate. Accordingly, NAND gate and NOR gate are assumed as AND
gate. (Refer Diagram 2-2-28). As well, NOR gate is assumed to output to S I and S 2 as OR
gate.
3-50
Diagram 2-2-28
STATE
0
1
2
3
4
5
6
7
8
9
10
1 1
12
1 3
14
15
--
Logic conversion
INPUT
OUTPUT
0
C
B
A
VO VI
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 2-2-10
1
1
1
1
1
1
1
1
1
1
Y2V3~V5
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
'11)
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
V7
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
VB yg
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Output results of TTL 74HC42
As mentioned heretofore, the output results of TTL 74HC42 are described as follows.
Y5=A*a*c*o
Y6=A*B*C*O
Y7=A*B*C*O
- -Y8=A*B*C*O
Y9=A*B*C*O
YO=A*~*C*O
Yl=A*B*C*O
Y2=A*B*C*O
V3=A*B*C*O
- Y4=A*B*C*O
--
3-51
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
I
a - i, using circuit input of Q I - Q8, are described as follows.
a=Q4*Q6
b=Q2*Q3*Q4*Q7
c=Q3*Q5*Q6*Q7
d=Ql*Q2*Q3*Q5*Q8
e=Ql*Q3*Q5*Q6*Q8
f=Ql*Q2*Q3*Q4*Q7*Q8
g=Q3*Q6*Q7*Q8
h=Ql*Q2*Q5*Q6*Q7*Q8
i=Ql*Q3*Q4*Q5*Q6*Q7*Q8
Hence, product sum Boolean equation relating to the output S I and S 2 are described as follows.
Sl=Q4*Q6* A* B* c* 0
+Q2*Q3*Q4*Q7* A* B* c*
+Q3*Q5*Q6*Q7* A* B* c*
+Ql*Q2*Q3*Q5*Q8* A* B*
+Ql*Q3*Q5*Q6*Q8* A* B*
+Ql*Q2*Q3*Q4*Q7*QS* A*
+Q3 *Q6 *Q7 *(~8 * Ii. * B* c*
+Ql*Q2*QS*Q6*Q7*Q8* A*
+Ql*Q3*Q4*Q5*Q6*Q7*Q8*
S2= A* B* c* 0
+Q4*Q6* A* B* c* 0
+Q2*Q3*Q4*Q7* A* B* c*
+Q3*Q5*Q6*Q7* A* B* c*
+Ql*Q2*Q3*Q5*Q8* A* B*
+Ql*Q3*Q5*Q6*Q8* A* B*
+Ql*Q2*Q3*Q4*Q7*Q8* A*
+Q3*Q6*Q7*Q8* A* B* c*
+Ql*Q2*Q5*Q6*Q7*Q8* A*
+Ql*Q3*Q4*Q5*Q6*Q7*Q8*
3-52
0
0
c*
c*
B*
0
[l
c*
D
-c*
0
0
B*
A*
B*
c*
0
0
0
c*
c*
B*
0
0
c*
0
c*
B*
0
D
B*
A*
c*
0
(3) Input file to truth table and "EPLASM"
Truth table implemented on the basis of product sum Boolean equation derived from (2) is
illustrated on Table 2~2~11.
Counter
of State
Clear
Hold
Count up
Counter Input
CLR
1
CNT
0
X
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Hold
Counter Output
C B A
0
0
0
0
0
1
1
1
1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
0 0
0 0
Table 2~2-11
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0
0
SI
S2
X
X
X
X
X
X
X
X
0 0 0
1 1 1
1 1 1
0 0 1
1 1 1
1 0 1
1 1 1
0 0 1
1 1 1
1 0 1
1 1 1
0 0 0
1 1 1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0 0 0
1 1 1
0 0 0
1 1 1
1
1
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
01 02 03 04 05 06 07 08
X
0
1
0
Truth table
3-53
uutput ot
Circuit
Input of Circuit (TTL74HC42)
X
X
1 1
(X Uncertain)
1
0 0
1 1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
X
X
X
1
1
1
1
1
0
1
0 0
1 1
X
I
Input file to "EPLASM" is shown on Diagram 2-2-29.
ePLI6RP4
eX. UP
ePL DeSIGN SPeCIFIC~TION
/'1.8. 8/2/1985
LOGIC
RICOH CO.LTD
OS~K~.J~P~N
eX~/'IPLe
: PIN
N~/'Ie
CLK
Ql
Q2
Q3
Q4
QS
Q6
Q7
Q8
GND
/eN
CNT
S2
I
2
J
4
5
6
7
8
9
Ie
II
12
13
A
14
8
15
C
16
D
CLR
51
VCC
18
19
20
17
4-8IT UP
/~
TYPe
IN
IN
IN
IN
IN
IN
IN
IN
IN
SYSTHI CLOCK
INPUT D~T~
INPUT D~T~
INPUT D~T~
INPUT D~T~
INP:JT UHA
INPUT D~T~
INPUT D~TA
INPUT D~TA
GROUNO
eN~8Le COUNTER OUTPUTS (ACTIVE LOW)
COUNTER (UP ANO HOLD)
LOGIC OUTPUT
COUN;Ui OUTPUT
COUNTER OUTPUT
COUNTER OUTPUT
COUNTER OUTPUT
CLE~RS COUNTER
LOGIC OUTPUT
+5 VOL T5
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
COUNTER
CLR
:=
..
DESCRIPTION
CNT~./CLR~;:;
+/CNT:f/CLR:f/~
/8:=
CLR
+ CNT"/CLR,, ~" 8
+ CNT:f/CLR"/~"/8
+/CNT"/CLR,,
/8
/C:=
CLR
+ CNT"/CLR"/~"
/C
+ CNT,,/CLR:f
/8:f/C
+ CNT"/CLR¥ "''' 8" C
+/CNT"/CLR:f
/C
/D:=
CLR
+ CNT¥/CLR¥/"'''
+ CNT:f/CLR"
+ CNT"/CLR"
+ CNT,,/CLR"
/0
/8*
/D
~" 8,,/C"/0
~" 8" C" 0
:LOGIC OUTPUT SI.52
IF (GND) CLR =QI"Q2"QS"Q6"Q7"Q8"/"'''/8"/C,,D
+Ql"Q3"Q4.QS.Q6"Q7.Q8,,"'./8./C.0
IF (VCC)
51
Q4"
Q6"
~"/8"/C./D
Q2.Q3"Q4"
Q7.
/"'" 8./C./0
Q3.
QS"Q6"Q7"
"''' 8"/C"/0
+Ql.Q2"OJ.
QS.
Q8./"'./8" C./D
+QI"
QJ.
OS.Q6"
Q8" "'''/8. C./O
+Ql"Q2"Q3.Q4.
Q7.Q8./~. S. C./D
+
QJ"
Q6,,07.Q8" ~" 8" C./D
+QI"Q2"
QS.06"07.Q8"/~./8./C. D
+QI.
QJ"C4"QS"C6"Q7.a8. ~./8"/C" D
+
3-54
IF (GNO) CNT =Q3#Q6#Q7#Q8#R#8#/C#/O
+Ql.Q2*OS.Q6*07.08*/R.8*YC./O
+Ql#Q3#Q4#QS#06#Q7#Q8#R*/8#/C#/O
IF (VCC)
/R#/8#/CII/O
RII/8#/CII 0
/R*/8*/CII 0
R# 811 CII/O
S2
Q4#
Q6#
Q2.Q3*Q4*
Q7*
Q3#
QS.Q6#Q7>/:
+
+
+;1~a2*QJ.
as.
+0111
QSIIQ611
03.
QB./~.
a~
C*/D
0811 t:l1l/8* C#/D
~01*02*Q3*Q4*
Q7*08*/R*/8* C*/O
0311
Q611Q711Q8* RII 811/C./O
+01110211
OS#Q61107110811/RII 811/CII/O
+0111
031104110S#06*07#Q8# RII/811/C*/O
FUNCTiON Tt:l8LE
,FUNCTION TR8LE PIN LISTS
CLK C~R CNT 0 C S A 01 Q2 03 04 05 06 07 08 SI S2
,:--- COUNTER -------:-----INPUT Ot:lTt:l --------: OUTeurs
,CLK CLR CNT 0 C S t:l
01 02 OJ Q4 as 06 07 08
51 S2
,TEST CLEAR
H
XLLLL
C
C
L
L L L L L
x
x
x
x
x
x
x
X
x
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
X
H
: COUNT IJP
L
H
C
L
C
L
H
H
C
C
C
L
L
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L L
L L
L L
L H
H
L H
H L
H H
L
L
L H L H
H
H
H
H
L
H
H
H
H
H L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
L
L
H
L
H
L H H H
L
H L L
H L L
H L H
H L H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H H L L
H
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
x
x
x
x
x
x
x
x
x
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
,HOLD
C
OESCRIPTION
~NP
Diagram 2-2-29
Input file to "EPLASM"
3-55
x
(4) Relating to execution results of "EPLASM" and fault testing
"JEDEC FILE", which is the execution results, is shown on Diagram 2-2-30.
EPL16RP4
EPL DESIGN SPECIFICIlTION
EX. UP
I'1.B. 8/2/1985
EXIlI'1PLE LOGIC
RICOH CO.LTD
OSIlKIl.JIlPIlN
"F8"
L8888 1111 1111 1111 1111 1111 1111 1111 1111 ;;
L8832 1111 1111 1118 9118 1119 9191 1111 1111 ;;
L8864 1111 9111 81198118 1191111991111111 ;;
L 8896
L8128
L8169
L8192
L8224
LIl288
L8328
L8512
L 8544
L9576
L 8698
L 8649
L 86 72
L8768
L8889
L 8832
L8864
L8896
L 1824
Lle56
Ll988
L 1 128
L 1288
L1312
L1344
L 1536
L 1568
L1699
L 1632
L1664
L 1696
1111 1111 8111l 11 19 11181 81111 I l l l l /111 :;:
9111 8111 8118 1181 8119 1118 1111 I l l l l :;:
8111 1111 8111l 1181 8111l 9181 1111 Ill11 :;:
81118111 8111l 91811181 1111l I l l l l Ill11 :;:
11111111 Ill11l 11111 11111 Ill1l1 Ill11 Ill11 :;:
Illl1 Ill11 1191 1118 el1e e118 e l l : ell1 x
911111118191 11118 8111l 8181 Ill11 8111 ;;
1111 11111 1111 1111 1111 1111 1111 1111 :;:
111 1 1119 1118 1 111 1111 1118 1111 1181 ;;
1111 l l l e 1111l 1111 1119 1111 1111 1191 x
111 1 1 1 11l 1 1 11l 1 1 11l 1 191 1 1111 1 11 1 1 1111 ;;
1111 1 119 1 191 1191 1191 1 1111 1 111 11111 :;:
1111 1111l I 119 1 111 11 11 1 1 11 1 111 1111l "
1111 l l i l l 1111 1111 1111 1111 11111111 x
1111 1111l 111111181111111911111181"
1111 1118 1 1 11 1 1 1 il 1 1 1 e 11 11 , ; 1 1 11 e 1 "
1111 1119 1111 1191 1191 1191 1111 11111 "
11111118 11111118 111111111111 l 1 H l "
I 1 1 1 1 191 1 1 I 1 1 1 11 1 1 11 1 1 11 1 1 11 1 1 ! 1 "
11111118 111111111191118111111181 :;:
1111 1118 1111 1111 1118 1118 1111 1181 x
1 1 1 I 1 119 1 1 1 1 1 11 1 1 1 18 1 1 11 1 1 1 1 1 118 "
1711 1181 1111 1111 1111 1111 1111 1111 :;:
11111118 11111111 1111 1181 1111 1181 :;:
1111 11181111111111111118 1111 1118"
1111 1111 1111 1111 1111 1111 1111 1111 "
1111 1111 1119 1118 1118 7 118 1111 1111 ;;
1111 1111 1191 9119 1119 9191 1111 1111 Of
1111 9111
191 8118 1118 1118 13 111 1111 :;:
11111111131113 11131131131 elel 131111111 :;:
e 111 e 111 ell e l l e 1 e 1 13 1 1 1 1 e 1111 13 111 ;;
e l l l 1111 8111l l l e l 911e a181 1111 9111 Of
el11 e l l l elle illill :11e l11e el11 13111 "
11111111131113 11113 l l e l alel al11 13111 :;:
13111 e l l l 1118 l l l e 8181 e11e 8111 e l l l Of
el11 1111 elle 811e el1e elel 0111 13111 :;:
lel
eel
eee
eee
999
gea
191
991
"
a
L1728
L176e
L1824
L1856
L1888
L2e48
C775BOf
U9991 CXXXXXXXXNXXXLLLL1XN
U8992 C99899999NXIlHLLLLeLN
U8893 Cl1111111NX1HHLLL8HN
U9994 Clllll111NX1HLHLL8HN
U8995 C99191111NX1HHHLL9HN
U8896 Cl1111911NX1HLLHL9HN
U8897 C191811elNX1HHLHLeHN
ue888 Cllll1111NX1HLHHLeHN
U9ge9 ce8191111NX1HHHHL9HN
U8e18 Cl1111111NX1HLLLHeHN
U8811 C19111111NX1HHLLH8HN
ue812 Clll11111NX1LLHLHeLN
UeelJ C81lge8gellNxlLHHLH9LN
U9814 Cl1111111NX1LLLHH8LN
U8815 C8e888e99NX1LHLHHeLN
U8816 Cllllll11NX1LLHHHeLN
U8~17 ce99gee88NX1LHHHH8LN
U9818 Cl1111111NX1HLLLL8LN
U8919 cXXXXXXXXNX9XLLLL9XN
"
Of
"
:;:
"
Of
"
"
Of
"
:;:
"
"
Of
"
Of
"
"
Of
FJ21
Diagram 2-2-30
JEDEC FILE
3-56
FUSE PLOT is shown on Diagram 2-2-31.
:OUT:FUNC:LINE:
:PUT:TION: NO
79:
79:
79:
19:
19:
! 9:
79:
j 9:
IF
8
+
+
+
2
3
18:
IF
+
19:
19:
1
4
5
6
7
: /17:
: /17:
:/17:
: /16:
: /16:
: /16:
: /16:
:/16:
+
24
25
26
27
28
29
31
:/15:
40
41
42
43
44
45
46
47
,/14 :
:/14:
: /14:
13:
IF
13:
13:
13:
13:
1Z:
+
13:
13:
+
12:
IF
13:
13:
13:
+
x-x---x
X-X---x
x-x---x
x-x-
xxx x xxxx xxx X
x--- --x- ---x
x-x- x--x
XXXX xxxx xxxx
xxxx xxxx xxx x
xxxx xxxx xxxx
xxx x XXXX xxxx
xxx x xxxx xxx x
xxxx
x--x
x--x
xxxx
xxxx
xxxx
xxx x
xxx x
xxxx
x--x
x-xXXXX
xxxx
XXXX
XXXX
xxxx
--x---x
---x
---x
---x
---x
xxxx xxx x
xxxx xxxx
32
33
34
35
36
37
38
39
: /15:
:/15:
---x
--xx-xx--x
x--x
--x--x-
16
17
18
19
28
21
22
23
38
:/15:
x--x
X--X
---x
--x--xx-x--x-
15
11
12
13
14
+
---x
X--- X--X
X--X
x--- x--- x--x
x--x--x
x--- x--- x--x
x--x
xxxx
x--x--XXXX
xxxx
xxxx
XXXX
xxx x
8
9
18
:/17:
: /17:
: /17:
77 1777 7777 2222 2222 2233
8723 4567 8987 2345 6789 8723 4567 8987
48
49
58
51
52
53
54
55
56
57
58
59
68
61
62
63
---x
---x
---x
--x---x
xxxx
xxxx
--x-
Q4#Q6#11#/8#/C#/D
X--x---
Q2#Q3#Q4#Q7#/1l#8~/C#/D
Q3#Q5#Q6#Q7#11~8#/C#/D
x--x--x--- x--x--- x---
xxx x
x--x--xxxx
xxxx
xxxx
XXXX
xxxx
xxx x
x--x--xxxx
XXXX
XXXX
XXXX
xxxx
--x--x-
---x
---x
---x --x- --x--x- --x- --x-
--x--x-
---x
xxxx xxxx xxxx xxxx xxxx
xxx x xxxx xxxx xxxx xxxx
QI#Q2#Q3#Q5#Q8#/R#/8#C#/J)
Ql#Q3#Q5#Q6#Q8#1l~/8#C#/~
QI#Q2#Q3#Q4#Q7#Q8#/1l#8#C#/
Q3#Q6#Q7#Q8~1l#8#C~/D
QI~Q2~Q5#Q6~Q7#Q8./Il~/8~/C
QI#Q3#Q4#Q5#Q6#Q7#Q8#1l#.S#
CLR
CNT~/CLR#/Il#/D
CNT#/CLR#/8#/D
CNT./CLR~Il.8¥/C./D
CNT#/CLR#Il#8#C#D
/CNT./CLR¥/D
CLR
---x
---x
---x ---x
--x- --x- --x-
---x
---x
---x
---x
---x
--j(-
CNTz/CLR~/~./C
--x--x-
CNT¥/CLR¥/8¥/C
CNT¥/CLR¥Il¥B#C
---)( /CNT¥/CLR¥/C
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxx x xxxx xxxx xxxx xxxx xxxx xxxx xxxx
XXXX xxxx xxxx xxxx xxxx xxxx xxxx xxxx
--x-
CLR
---x
---x
---x
--x- --x-
--x-
---x ---x
--x- CNTl/CLRx/A¥/B
---x
xxx X xx>ix xxxx
XXXX xxxx xxxx
XXXX'
xxx).,
CNT~/CLR~~~8
---)( /CNT'/CLRx/B
)o;.'X>:.
X),X>I
xxxx XXX" xx),~ xx),), xx"x
xxxx xxxx xxxx xxxX' xxxx xxxX' xxx>:. xxxx
xxxx XXX X xxxx xxx x xxxx xx),)..' xxxX' xxxX'
--x-
---x
---x
.\
C'LR
CI\' T ... ,
-
CLRl~
/CNT¥/CLRx/,q
--->.
j(XXX XXXX XXXX xxxx xxx x XXxx XXXX ),xxx
XXXX XXXX xxxx xxxx xxxx xxxx xxx), xx),x
xxxx xxxx xxxx xxxx xxxx "XXX xxxx xxx x
xxxx xxxx xxxx xxxx xxx X xxxx
XXX)(;
xxx x
XXXX xxxx xxxx xxxx xxxx xxxx xxxx xxxx
---)( ---x ---x ---x
--xX--- X-XX--X
X--- x--- x--x
x--x--x
x--- x--- x--x
X--X
X--X
--x--x--xX-X-
---x
---x
x-xx-xx--x
---x
x-x---x x--x-x- x-----x
x--x-xx-----x x--- x---
xxxx xxxx xxxx xxxx xxxx
X--X ---x --xX--- x--- ---x ---x x-xX-X--X x--x X--X
XXXA xxx x xxxx XXXX XXXX
XXXX XXXX XXXX xxxx XXXX
xxxx XXXX xxxx XXXX XXXX
xxxx xxxx xxxx XXXX xxxx
Diagram 2-2-31
xxxx xxxx xxxx
x-x- x--- x--X--x x--- x--x-x- x--- x--XXXX xxxx XXXX
XXXX XXXX xxxx
xxx x xxxx xxxx
xxxx xxx x xxxx
FUSE PLOT
3-57
/A:l/B./C..-/D
a4.a6.A¥/B./C~D
Q2¥OJ¥04¥07¥/Il#/B¥/C¥D
QJ~05¥Q6.Q7¥Il¥B¥C¥/D
Ql#Q2#Q3#Q5¥Q8~/R¥8~C~/v
Ql¥QJ~Q5~Q6~Q8~1l./8¥C#/D
Ql.Q2.QJ.Q4.Q7.Q8./Il./8~C.
03¥06~Q7¥Q8~11#8~/C~/D~QY'Q
Q7¥Q2~Q5#Q6¥Q7#Q8~/~¥8~'C~
Ql~QJ~Q4~05~Q6~Q7#Q8~1l~/8~
I
After implementation of test vector, "EPLASM" execution command "F" is subjected to fault
test. Fault test is to examine whether or not SAO (0 degeneracy fault) and SAl (I degeneracy
fault) are detectable for all product terms which use the test vector.
In case of SAO, wiring are short-circuited and connected to the Ground, and "L" is output even
expected value is at "H" level. To detect SAO, determine the expected value so that one product
term becomes "H" level and determine the rest of product terms to become "L" level. If the
output is "L" at this point, it is readily seen that this product term is in 0 degeneracy fault. For
example, the 3rd product term of Boolean equation of S 1 derived from (2) is :
When determining expected value so that this product term becomes "H" level, they are :
Ql-+L
Q7-+H
Q2-+L
Q8-+L
Q3-+H
A-+H
Q4-+L
B-+H
Q5-+H
C-+L
Q6-+H
O-+L
The rest of product terms are all "L" and hence, SAO is detectable.
In case of SAl, wiring are short-circuited and connected to V cc, therefore, "H" is output even
output expected value is at "L" level. In this occasion, this is reverse to SAO and determine
expected value so that all product terms become "L". Fault test results are shown on Diagram
2-2-32. As readily seen from the test results, fault undetectable product terms (equation 5 1st
and 2nd product term, equation 7 1st, 2nd and 3rd product term) are shown. Input output pins of
pin 12 and pin 18, being collected pins of equation 5 and 7, are used as input pin and are indicated
as detection impossible. However, since these product terms are output to pin 13 and pin 19, using
share function of product term, practical fault detecting percent is 100%.
IF (GNO) CLR =QI¥Q2¥QS¥Q6¥Q7#Q8#/A#/8¥/C¥O
®
+QI¥03#04#OS#06#07#08#A#/8#/C¥O
IF (VCC)
51
A#/8#/C./O
/A# 8¥/C¥/O---+
02#03#04#
07¥
03#
OS#06¥07#
A# 8./C#/O
+01¥02¥03#
OS¥
08¥/A¥/8¥ C¥/O
+01.
03.
OS¥06#
OS¥ A#/8. C./O
+01¥02¥03¥04#
07#OS#/A# 8# C#/O
+
03#
06#07#OS# A# 8# C#/O
+01#02#
05#06#07¥OS#/A#/8¥/C¥ 0
+Olr
03.04.0S¥06#07#OS# Ar/8¥/C. 0
IF (GNO) CNT =03#06¥07¥OS¥A¥8./C#/O
®
----Q)
+01#02¥OS¥06¥07#OS¥/Ar8r/Cr/O
+0Ir03r04rOS#06r07rOBrAr/8r/Cr/O
IF (VCC)
52
/Ar/8./Cr/O
Ar/8r/Cr ()
04r
06r
/Ar/8r/Cr 0
02¥03r04r
07r
+
Ar 8r C./O
03r
OSr06r07r
+01#02r03.
OSr
08#/A# a. C./O
+01#
03.
OS#06r
OBr Ar/8# Cr/O
+0Ir02#03r04¥
07rOS#/A¥/8r C¥/O
+
03r
06r07rOBr Ar 8./C#/O
+01.02#
OS#06r07rOBr/Rr 8#/Cr/O
+01r
03#04rOSr06r07#OBr Ar/8r/C¥/O
+
+
3-58
®
P{1SS SIMUL{1TION
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
PRODUCT:
1 OF EQUATION.
2 OF EQUATION.
OF
OF
OF
OF
OF
OF
2 OF
3 OF
2
3
1
2
EQUATION.
EQUATION.
EQUATION.
EQUATION.
EQUATION.
EQUATION.
EQUA TION.
EQUATION.
NUMBER OF STUCK AT ONE
S
S
7
7
7
S
S
7
7
7
UNTESTED(SA1) FAUL T
UNTESTED(SA1) FAUL T
UNTESTED(SA1 ) FAUL T
UNTESTED(SA1) FAUL T
UNTESTED(SA1) FAUL T
UNTESTED(SA8) -FAUL T
UNTESTED(SA8) FAUL T
UNTESTED(SA8) FAUL T
UNTESTED(SA8) FAUL T
UNTESTED(SA8) FAUL T
(SA1) FAULTS ARE
NUMBER OF STUCK AT ZERO
(SA8) FAULTS ARE
=
37
37
88%
PRODUCT TERM COVERAGE
Diagram 2-2-32
Fault test
•
3-59
! ! ! ! ! ! ! !IC! ! ! ! ! ! ! !D©! ! ! ! ! ! ! !CID! ! ! ! ! ! ! ![}[]_~I
EPL241E
EKE-3-8803
CMOS ELECTRICALLY
PROGRAMMABLE LOGIC
• OUTLINE
The EPL241 is a field-programmable logic array with CMOSEPROM processing and AND-OR(fixed)-Register configuration.
Programming is easily handled, even on the user's side, by
writing to the EPROM memory cells arranged on the array.
This programming technique shortens the development period
greatly and simplifies circuit corrections.
Each output configuration is individually defined using 16
programmable macro I/O cells. This means you can specify
either combination output or register output, and the polarity.
Each macro cell has two feedback signals, with which you can
simultaneously feedback both the combination and register
outputs, or can feedback one of the combination and register outputs while using an I/O pin as an
input pin. The power consumption varies with the product term use efficiency (40mA when 35% use) .
• FEATURES
• Low power consumption and high reliability thanks to the CMOS-EPROM process
• 24 pins, 22 inputs, 16 outputs
• Ultraviolet ray deletion is available in ceramic-packaged products
• Package
EPL241ED
EPL241EP
24 pins
24 pins
EPL241EJ
28 pins
300 mil
300 mil
CERDIP (with window)
MOLD DIP
PLCC (under development)
• Data copy prevention function
• Input/output propagation delay 25ns (max)
• Improved functions with macro I/O cells
A. Selection of combination outputs and register outputs
B. Selection of feedback signals
C. Select jon of synchronous OE and asynchronous OE
D. Selection of output polarity
E. Selection of clock signals (CLK!, CLK2, Internal CLK)
F. Asynchronous reset (ARl, AR2, AR3)
G. Synchronous preset (SP!, SP2, SP3)
--------------ltD©®OO3-61
•
EPL241 E
• ABSOLUTE MAXIMUM RATINGS
Symbol
Parameters
Conditions
limits
Unit
Vee
Vcc Supply Voltage
-0.3 - 7.0
V
vpp
vpp Supply Voltage
-0.3 - 14.5
V
Vi
Input Voltage
-0.3 - Vcc+O.3
V
Vo
Output Voltage
Pd
Maximum Power Consumption
Topr
Operating Ambient Temperature
Tstg
Storage Temperature
With respect to GND
Ta=25°C
-0.3 - Vcc+O.3
V
0.8
W
-20-70
°c
-40 - 125
°c
• CAPACITANCE
Symbol
Parameters
Conditions
min.
Input Pin
• D.C. CHARACTERISTICS (Ta = 0 - 70 0 e
Symbol
Parameters
8
Vee= OV
Vpp Pin
max.
Unit
5
f= IMHz
I/O Pin
typo
pF
10
Vee = 5V ±5%)
' Conditions
Specified Value
min.
typo
max.
Unit
ILl
Input leak current
Vin=OV-Vce
-20
20
p.A
ILO
Output leak current for OFF state
Vo=OV-Vcc
-20
20
p.A
VIL
"L" Input Voltage
-0.3
0.8
V
VIH
"H" Input Voltage
2.0
Vcc+O.3
V
VOL
"L" Output Voltage
Vcc=MIN
Iol=8mA
0.5
V
VOH
"If' Output Voltage
Vee=MIN
Ioh=-3.2mA
Vec=MAX
f=OMHz
Ieel
Supply Voltage (standby)
Vin=GND or Vec
Vcc=MAX
Icc2
Supply Voltage (operation)
2.4
V
120
rnA
140
rnA
f=lOMHz
Vin=GND or Vee
-IID@®OO-------------3-62
EPL241E
• A.C. CHARACTERISTICS (Ta
= 0 ~ 70°C
Vee
= 5V ± 5%)
Parameters
Specified Value
Symbol
Conditions
Clock
Parameter
Unit
min.
typo
max.
Tpd
Input or I/O input to
non-registered output
25
nS
Tpix
Input or I/O input to
output disable
25
nS
Tpiz
Input or I/O input to
output enable
25
nS
Tpxz
OE to output disable
20
nS
Tpzx
OE to output enable
20
nS
Tsul
Input or I/O input setup time
Thl
Tc1kl
CLKI
(i pin)
Tpsl
Tsetl
18
Input or I/O input hold time
External
Clock
Tfpdl
Twl
CI ; 50pF
CLK2
(11 pin)
Trst
Clock to output delay
0
RI ; 560.11
Clock to non-registered output
from registered feedback
R2;1.1
k.l1
External clock width
Synchronous preset input
setup time
nS
nS
IS
nS
35
nS
IS
nS
18
nS
Clock to register preset
IS
nS
Input or I/O input to
asynchronous reset
25
nS
Tpl
Minimum clock period
fI
Maximum frequency
Tsu2
Input or I/O input setup time
5
nS
Thz
Input or I/O input hold time
10
nS
TClk2
Internal
Clock
Tfpd2
Tw2
Tps2
Tset2
CKPI
CKP2
CKP3
33
30
nS
MHz
Clock P.T. input to output delay
30
nS
Clock P.T. input to non·registered
output from registered feedback
50
nS
Clock P.T. input width
Synchronous preset input setup
time
IS
nS
5
nS
Clock P.T. input to register preset
30
nS
35
nS
Tp2
Minimum clock period
f2
Minimum frequency
Tpon
Power On Reset Time
28.6
MHz
45
Jl.S
---------------IIO@®OO3-63
I
EPL241 E
• TIMING DIAGRAM
IE- -
->i
tW2
Internal Clock
Input
tWl-*-tWl
I
eLK1
CLK2
<-
~'SU2--J ~tH2-71
,SU1--> 'H1~
Input
%
~
INPUT
of-tCLK1~
Registered
Output
~tCLK2~
X
Registered
Output
!<--!
Combinato,lcll
Output from
Registered
Feed back
k-- i
t$ET2
.J
Synchronous
Preset Output
f
Synchronous
Preset Output
" - - 'RST----,>/
Asynchronous
l
Reset Output
~'PD-->I
~
Combinatorial
Output
Power-On Reset
~
Input or
Feed back
I<-: "'X-..,
I
fOE
"ltpxz"""""""?
V"
L"'Z4
Registered
Output
l
~tPZX
V OH
Data
Input
V IL
Clock
V IH
V IL
'S_U_'~
________________________
Input Waveform
5V
INPUT PULSES
+3.0V~
__ _
RI
l
---'--:l
--
560Q
90%
10;Yo
OV
Output
O------<....----~~---_o
R2
1.lkQ
Valid
'L'
=
Q
VOL
V IH
Output
Output Load
OV
Test Point
5ns
+3.0v
r
-
-
If
If -15n1---
-
-~O%
I
CL
50pF
(Including testing jig capacitance)
OV~--L =J [
5ns
90%-
5ns
NOTE: This is the A.C. characteristic measurement
with a voltage of 1.5V on both the input and output.
--ICO©®[l{]---3-64
EPL241 E
• PIN DESCRIPTION
Function
Pin Name
Pin No.
DIP
PLCC
Operating
Programming
1
2
CLKI/ll
Vpp
2
3
PLM/12
CA4
3
4
I3
CA3
4
5
1/016
CA2
5
6
1/015
CAl
6
7
1/014
CAO
7
8
1/013
RA6
8
9
1/012
RA5
9
10
1/011
RA4
10
12
14
RA3
II
13
CLK2/I5
RA2
12
14 ·15
GND
GND
13
16
OE/16
PGM/OE
14
17
1/010
RAI
15
18
1/09
D7
Operating
I
Programming
Clock 1
I
Programming Power Supply
Pre-load
Input
Column Address Input
Input/Output
Row Address Input
Input
I
Clock 2
GND
GND
Output Enable/lnput
Programming Control
/Output Enable
Row Address Input
16
20
1/08
D6
17
21
1/07
D5
18
22
1/06
D4
19
23
1/05
D3
20
24
1/04
D2
21
25
1/03
Dl
22
26
1/02
SEQ/DO
I
23
27
1/01
RAO
Row Address Input
24
I ·28
Vcc
Vce
Input/Output
Data Input/Output
Vee
Security Data
Vee
• PIN CONFIGURATION
EPL241ED
EPL241EP
EPL241EJ
I 3
PLM elK1
/12
/II
vee vee
1/01
1/02
PLM/12
1/016
1/015
1/015
1/014
1/014
1/013
1/013
1/012
1/011
1/011
I 4
CLK2
0 E
/15 GND GND /16 1/010 1/09
----------------ICD@®OO3-65
•
EPL241 E
• BLOCK DIAGRAM
I
1--J.4,..<-
-q
H
f>-
11
SP AR
,>------------+---1:;--1
l'
f
r------,
MACAOCELL
A
~
1/010
--<14'>
W~
i''-i''--,A,.-R....:O",'_
11 h
-
16/0E
erature
Tstg
Conci'.'-i"-"-------tt--~~~~~~_~_;_~_3~_ts_7_-__-_--_-_-__
---+f--_-___-_-U=~=.i=t===~
\\.'ith respect to GND
._ _ _ _ _ _
-----------.t---
. Storage Temperature
-O.3_-_\_!_cc__+
__0_.3____--j______~
-0.3-0~7cOc+0.3
__ ---::-V____--I
-40~125
I
--!.-.---
°c
-~-
• ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Ta=O-70'C, Vcc=5V±lO%)
! Measuring Conditions
Parameters
------------------_.- - - - - - - - - - - - - - - VIfI
[nput "H"Voltage (TTL compatible)
lnput "L"Voltage (TTL-co';;~~;;hl;:) ----- - - - ------------ - - - - - -..------f-------+-------j----'---+-----VIH
[nput "H"Voltage (C-~lOS compatIble)
Symbol
---.---
----v;-;.
~_
[nput "L"Voltage (C-MOS compatible)
____. _________________j---'-'-'---__+
__~()f_I__ ~~H"V~________
10H'":-=-4mi\_ _ _ . ____- j______--t_____
VOL
Output "L"Voltage
. [ol.=4mA
iI~---' ~~-;-C~t----_---~=t=~=O~~c~~·----·
11.0
Output Leakage Current
I
Vo=O-Vcc
AC ELECTRICAL CHARACTERISTICS (Ta=O-70'C, Vcc=5V±lO%)
Symbol
Parameters
Measuring Conditions
Limits
Min
Typ
Max
Unit
tpd
Basic Gate Delay Time
2 [nput NAND (F AN OUT=3)
l.5
ns
tpdo
Output Buffer Delay Time
Cl.=lOOpF
10
ns
---------------ICO®®OO3-73
.DEVELOPMENT FLOW CHART
(USER)
(RICOH)
. SYSTEM DESIGN
. INVESTIGATE
DESIGN MANUAL
~
CELL LIBRARY
· LOGIC DESIGN
· TIMING SPEC
,t
· NETWORK ENTRY
· DESIGN RULE CHECK
•
· LOGIC SIMULATION
. LOGIC SIMULATION
. FAULT SIMULATION
CONFIRM
NO
YES
1 - - - - . , - - - - - - - - t - - - - 4..
AUTOMATIC PLACEMENT/ROUTING
•
. RE SIMULATION &
. MASK TOOLING
VERIFJCATION
. TEST PROGRAM GENERATION
NO
I
MASS PRODUCTION
,!WPTION: LOGIC DIAGRAM AND LOGIC SIMULATION DATA INTERFACE
IS AVAILABLE AS AN OPTION.
DIP 16.24,28,40,48,64 PIN
FLAT 60,80,100 PIN
PLCC 44,68,84
PIP
100,108,120 PIN
--ItO©®OO----~---------3-74
CMOS GATE ARRAY 5GH series
CELL LIST
INPUT BUFFER
INVERTER
ADDER
OUTPUT BUFFER
BUFFER
DATA-LATCH
INPUT AND OUTPUT
BUFFER
NAND
REGISTER
NOR
SHI FT REGISTER
EXCLUSIVE
CLOCK GENERATOR
AND-NOR
COMPARATOR
OR-NAND
PARITY GENERATOR
FLIP-FLOP
SYNCHRONIZER
OSCILLATOR
DECODER
MULTIPLEXER
MULTIPLEX
REGISTER
COUNTER
---------------ICO®®[}{]3-75
•
GATE ARRAY SGH CELL LIST
liD CELL
I
INPUT
BUFFER
Jrl
STANDARD
H
with RESISTANCE
for Pull-Up
with RESISTANCE
for Pull-DDwn
I
I
I
~rl
OUTPUT
BUFFER
OUTPUT AND
INPUT BUFFER
STANDARD
H
with RESISTANCE
for Pull-Up
with RESISTANCE
for Pull-Down
I
OSCILLATOR
r-
I
I
f-
I
j
CELL
FUNCTION
INTOl
INT02
INTSCH
INCOl
INC02
INCSCH
TTL Compatible
TTL
TTL
CMOS Compatible
CMOS
CMOS
Schmitt Trigger
Inverter
INT1Ul
INT2Ul
INTSUl
INC1Ul
INC2Ul
INCSUl
TTL Compatible
TTL
TTL
CMOS Compatible
CMOS
CMOS
Inverter
Buffer
Schmitt Trigger
Inverter
Buffer
Schmitt Trigger
INT1Dl
INT2Dl
INTSDl
INC1Dl
INC2Dl
INCSDl
TTL Compatible
TTL
TTL
CMOS Compatible
CMOS
CMOS
Inverter
Buffer
Schmitt Trigger
Inverter
Buffer
Schmitt Trigger
OUTINV
OUTTRI
OUTOPN
Inverter
3-State Output
Open Drain Output
10TOl
10Tl
IOT02
IOT2
10TSCH
10TSH
10COl
10Cl
IOC02
IOC2
10CSCH
10CSH
TTL Compatible
Inverter & 3-State Output
TTL Compatible
Buffer
TTL Compatible
Schmitt Trigger & 3-State Output
Inverter
Buffer
Buffer
Schmitt Trigger
& 3-State Output
CMOS Compatible
Inverter & 3-State Output
CMOS Compatible
Buffer
CMOS Compatible
Schmitt Trigger & 3-State Output
& 3-State Output
TTL Compatible
Inverter & 3-State Output
CMOS Compatible
Inverter & 3-State Output
IOT101
IOTDl
IOC101
10CDl
TTL Compatible
Inverter & 3-State Output
CMOS Compatible
Inverter & 3-State Output
XINOl
XOUT
XIO
Input
Oscillater Output
Oscillator
IOT1Ul
10TUl
10C1Ul
10CUl
-ICO®®DlJ--------------3-76
GATE ARRAY 5GH CELL LIST
GATE
INVERTER
BUFFER
I
---l
I AND-NOR
lOR-NAND
Inverter
POWER TYPE
NBUF02
NBUF03
NBUF04
Power Inverter (X2)
Power Inverter (X3)
Power Inverter (X4)
STANDARD
BUF11
Buffer
POWER TYPE
BUF12
BUF13
BUF26
Power Buffer (X2)
Power Buffer (X3)
Power Buffer (X6)
3-STATE
3BUF02
3-STATE Buffer Driver
NAND02
NAND03
NAND04
NAND05
NAND06
NAND08
2-lnput
3-lnput
4-lnput
5-lnput
6-lnput
8-lnput
DNAND2
Power 2-lnput
NOR02
NOR03
NOR04
NOR05
NOR06
NOR08
2-lnput
3-lnput
4-lnput
5-lnput
6-lnput
8-lnput
DNOR02
Power 2-lnput
XOR02
XNOR02
2-lnput Exclusive OR
2-lnput Exclusive NOR
AOl21
AOl31
AOl41
AOl22
AOl32
AOl23
AOl33
AOl24
AOl211
AOOl22
MAJ23
2-AND-NOR
3-AND-NOR
4-AND-NOR
2-lnput.2-Wide
3-1 nput. 2-Wide
2-lnput.3-Wide
3-lnput.3-Wide
2-1 nput. 4-Wide
2-AND Into 3-NOR
2-AND. 2-NOR Into 2-NOR
Inverting 2 of 3 Majority
OAI21
OAI31
OAI41
OAI22
OAI32
OAI23
OAI33
OAI24
OAI211
OAAI22
2-0R-NAND
3-0R-NAND
4-OR-NAND
2-1 nput. 2-Wide
3-1 nput. 2-Wide
2-1 nput. 3-Wide
3-lnput. 3-Wide
2-lnput. 4-Wide
2-0R Into 3-NAND
2-0R. 2-NANO Into 2-NAND
f-
POWER TYPE
STANDARD
NOR
I EXCLUSIVE
INV01
STANDARD
NAND
---1
I
STANDARD
POWER TYPE
f-
---------------IIO©®IXl3-77
•
GATE ARRAY 5GH CELL LIST
I
FLIP-FLOP
~--1
---l
lATCH
r-
RS-lATCH
r-
---l
T-FF
r-
---1
D-FF
t-
--1_
JK-FF
r-
•
~
SCAN
~
DlTOO
DlTOR
DlTOS
DlTSR
NDlTOR
NDlTOS
NDlTSR
DlGOO
DlNGOO
NDlGOR
NlNGOR
D-lATCH
Reset
Set
Set & Reset
Reset B
Set B
Set B & Reset B
Gated
Gated (Active L)
Gated, with Reset B
Gated (Active ll, with Reset B
RSlT
NRSlT
NRSClT
N2RSlT
RS-latch
RS-latch B
Separate Gate
TFFOR
TFFOS
TFFSR
NTFFOR
NTFFOS
NTFFSR
Reset
Set
Set & Reset
Reset B
Set B
Set B & Reset B
DFFOO
DFFOR
DFFOS
DFFSR
NDFFOR
NDFFOS
NDFFSR
DFFCOO
NDCOR
NDCOS
NDCSR
N2CSRT
M273C
D-FF
Reset
Set
Set & Reset
Reset B
Set B
Set B & Reset B
Clocked
Clocked, with Reset B
Clocked, with Set B
Clocked, with Set B & Reset B
Set B & Reset B
Octal D-Type Flip-Flop (74lS2731
JKOR
JKOS
JKSR
NJKOR
NJKOS
NJKSR
NJKCOS
NJKCSR
NJ2CSR
Ml12C
Reset
Set
Reset & Set
Reset B
Set B
Reset B & Set B
Clocked, with Set B
Clocked, with Set B & Reset B
Set B & Reset B No Spbufs and No SdBufs
Clocked (Active ll, with Set B & Reset B
DlTOOT
DlTMS
NDORT
NDOST
NDSRT
DCOOT
NDCORT
NDCSRT
NJCORT
NJCSRT
D-latch SCAN
D-latch into D-latch SCAN
D-F F with Reset B SCAN
D-FF with Set B SCAN
D-F F with Set B & Reset B SCAN
D-FF SCAN
D-FF with Reset B SCAN
D-F F with Set B & Reset B SCAN
JK-FF with Reset B SCAN
JK-FF with Set B & Reset B SCAN
Common Gate
--ICD©®OO--------------3-78
GATE ARRAY 5GH CELL LIST
BLOCK
I
ADDER
r-
DATA-LATCH
l
REGISTER
I
SHIFT
RESISTER
l
CLOCK
GENERATOR
f-
I
I
I~C_O_M_P_A_R_A__T_O_R__~r----
HAl
FAl
M80C
FA2
FAS2
M82C
FA4
M83C
CLAl
CLA2
FA16
Half Adder
Full Adder
Gated Full Adder (7480)
2 Bit Binary Full Adder
2 Bit Binary 2'5 Complement Full Adder, or substractor
2 Bit Binary Full Adder (7482)
4 Bit Binary Full Adder
4 Bit Binary Full Adder with Fast Carry (74LS83)
Carry Look Ahead for 4 Bit Adder
( Least Significant Nibble)
Carry Look Ahead for 4 Bit Adder
16 Bit Fast Adder
L4
L8
4 B it Data Latch
8 Bit Data Latch
R41
R42
R81
R82
4 Bit Data Register
4 Bit Data Register, Clear Direct
8 Bit Data Register
8 Bit Data Register, Clear Direct
SR41
Sfl42
M95C
SR43
SR44
SR45
SR46
SR47
M94C
M179C
M195C
M96C
M91C
M164C
M165C
M166C
M198C
M199C
4 Bit Shift Register
4 Bit Shift Register, Clear Direct
4 Bit Shift Register (74LS95)
4 Bit Shift Register, Set Direct
4 Bit Shift Register, Synchronous Parallel Load
4 Bit Shift Register, Synchronous Parallel Load and Clear
4 Bit Shift Register, Asynchronous Parallel Load
4 Bit Shift Register, Sync Clear
4 Bit Shift Register (7494)
4 Bit Parallel Access Shift Register (74179)
4 Bit Parallel-Access Shift Register (74LS195)
5 Bit Shift Register (74LS961
8 Bit Shift Register (74LS91)
8 Bit Parallel Output Serial Shift Register (74LS164)
Parallel Load 8 Bit Shift Register (74LS1651
8 Bit Shift Register (74LS166)
8 Bit Bidirectional Universal Shift Register (74198)
8 Bit Bidirectional Universal Shift Register (74199)
CPG1
CPG2
CPG3
CPG4
Two
Two
Two
Two
MAG2H
MAG2
MAG4
CMP4
M85C
CMP8
2 Bit Magn itude Comparator
2 Bit Extendable Magnitude Comparator
4 Bit Extendable Magnitude Comparator
4 Bit Magnitude Comparator Expandable
8 Bit Equality Comparator
Phase
Phase
Phase
Phase
Clock
Clock
Clock
Clock
Generator,
Generator,
Generator,
Generator,
Unbuffered,
Unbuffered,
Unbuffered,
Unbuffered,
Hi
La
Hi
La
Underlap,
Underlap,
Underlap,
Underlap,
La
Lo
Hi
Hi
I
Drive
Drive
Drive
Drive
4 Bit Equality Comparator
I
PARITY
GENERATOR
PARS
PAR9
M180C
8 Bit Odd Parity Detector
9 Bit Odd Parity Detector
9 Bit Odd/Even Parity Generator (741801
l
SYNCHRONIZER
SYNC01
SYNC10
Synchronizer for Asynchronous 0 to 1 Event
Synchronizer for Asynchronous 1 to 0 Event
--------~-------ICD©®OO3-79
GATE ARRAY 5GH CELL LIST
I
I
DECODER
MULTIPLEXER
~
~
M4555C
M139C
M155C
D24H
D24L
D24GH
D24GL
D38H
D38L
D38GH
D38GL
M138C
M138D
D410H
D410L
M154C
Binary to 1 of 4 Decoder
2 to 4 Decoder (74LS139)
Dual 2 to 4 Decoders
2 to 4 Decoder, Output Active Hi
2 to 4 Decoder, Output Active Lo
2 to 4 Decoder, Gated Output Active
2 to 4 Decoder, Gated Output Active
3 to 8 Decoder, Output Active Hi
3 to 8 Decoder, Output Active La
3 to 8 Decoder, Gated Output Active
3 to 8 Decoder, Gated Output Active
Gated 3 to 8 Decoder (74LS138)
Gated 3 to 8 Decoder (74LS138)
4 to 10 Decoder, 0 utput Active Hi
4 to 10 Decoder, Output Active La
4 to 16 Decoder (74LS154)
Hi
Lo
Hi
Lo
DM6JH
DM6JL
DM8JH
DM8JL
DM10JH
DM10JL
DM12JH
DM12JL
DMl4JH
DMl4JL
DM16JH
DM16JL
Spike Free Decoder for MOD 6 Johnson Counter, Active Hi
Spike Free Decoder for MOD 6 Johnson Counter, Active La
Spike Free Decoder for MOD 8 Johnson Counter, Active Hi
M43C
M44C
M47C
M49C
M42C
M145C
M4028C
Excess-3 to Decimal Decoder (7443)
Excess-3 Gray to Decimal Decoder (74LS44)
Bcd to 7 Segment Decoder/Driver (74LS47)
Bcd to 7 Segment Decoder/Driver (74LS49)
Bcd to Decimal Decoder (7442)
Bcd to Decimal Decoder (74LS145)
Bcd to Decimal Decoder (4028)
M298C
M157C
M158C
M153C
M151C
M152C
M150C
Quad 2-1 nput Multiplexer with Storage (74LS298)
Quad 2 Bit Gated Non Inverting Mux
Quad 2 Bit Gated Inverting Mux
Dual 4 Bit Gated Non Inverting Mux
8 Bit Gated Mux
8 Bit Inverting Mux
16 Bit Gated Inverting Mux (74LS150)
MUX31H
MUX31 L
MUX41 H
MUX41GH
MUX41 L
MUX51 H
MUX51 L
MUX61H
MUX61 L
MUX71H
MUX71 L
MUX81H
3
3
4
4
4
5
5
6
6
7
7
8
MUX22H
MUX32H
MUX42H
MUX52H
MUX62H
MUX72H
MUX82H
Dual
Dual
Dual
Dual
Dual
Dual
Dual
MUX24H
MUX24L
MUX34H
MUX44H
MUX54H
MUX64H
MUX74H
MUX84H
Quad
Quad
Ouad
Quad
Quad
Quad
Quad
Ouad
Spike Free Decocler for MOD 8
Spike
Spike
Spike
Spike
Spike
Spike
Spike
Spike
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Free
Free
Free
Free
Free
Free
Free
Free
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
for
for
for
for
for
for
for
for
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
Johnson Counter, Active La
10 Johnson
10 Johnson
12 Johnson
12 Johnson
14Johnson
14 Johnson
16 Johnson
16 Johnson
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Active
Active
Active
Active
Active
Active
Active
Active
Hi
La
Hi
La
Hi
La
Hi
La
Non Inverting Mux
Inverting Mux
Non Inverting Mux
Gated Non Inverting Mux
Inverting Mux
Non Inverting Mux
Inverting Mux
Non Inverting Mux
Inverting Mux
Non Inverting Mux
Inverting Mux
Non Inverting Mux
2
3
4
5
6
7
8
2
2
3
4
5
6
7
8
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Non
Non
Non
Non
Non
Non
Non
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
Mux
Mux
Mux
Mux
Mux
Mux
Mux
Non Inverting
Inverting Mux
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Mux
Mux
Mux
Mux
Mux
Mux
Mux
-ICO@@[](]--------------3-80
GATE 5GH ARRAY CELL LIST
! MULTIPLEX
REGISTER
r-
'------'
I
COUNTER
~nMODULO
JOHNSON
. i
COUNTER
I
MGRAY
ODULOi
COUNTER
I 1 MBINARY
ODULOj
COUNTER
J-- MODULO
BINARY
RIPPLE
COUNTER
H
J---
M
ODULOj
SHIFT
COUNTER
MR41
MR42
MR43
MR44
MRSl
MRS2
4 Bit Register with 2 Bit Multiplexed Input, Sync Clear Reset B
S Bit Register with 2 Bit Multiplexed Input
8 Bit Register with 2 Bit Multiplexed Input, Clear Direct
CM4J
CM6J
CM8J
CMlOJ
CM12J
CMl4J
CMl6J
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
4,Johnson
6, Johnson
8, Johnson
10. Johnson
12, Johnson
14, Johnson
16,Johnson
C2G
C3G
C4G
C5G
C6G
C7G
C8G
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
4, Gray Counter, Clear Direct
8, Gray Counter, Clear Direct
16, Gray Counter, Clear Direct
32, Gray Counter. Clear Direct
64, Gray Counter, Clear Direct, Prescaled
128, Gray Counter, Clear Direct, Prescaled
256, Gray Counter, Clear Direct, Prescaled
CM3B
CM4B
CM5B
CM6B
CM7B
CM8B
CM9B
CM10B
CMllB
CM12B
CM13B
CM14B
CM15B
CM16B
CM17B
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
3, Binary
4, Binary
5, Binary
6, Binary
7, Binary
8, Binary
9, Binary
10, Binary
11, Binary
12, Binary
13, Binary
14, Binary
15, Binary
16, Binary
17, Binary
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
CM8BR
CM9BR
CM10BR
CMllBR
CM12BR
CM13BR
CM14BR
CM15BR
CM16BR
CM17BR
CM18BR
CM19BR
CM20BR
CM21BR
CM22BR
CM23BR
CM24BR
CM25BR
CM26BR
CM27BR
CM28BR
CM29BR
CM30BR
CM31BR
CM32BR
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
8, Binary
9, Binary
10, Binary
11, Binary
12, Binary
13, Binary
14, Binary
15, Binary
16, Binary
17, Binary
18, Binary
19, Binary
20, Binary
21, Binary
22, Binary
23, Binary
24, Binary
25, Binary
26, Binary
27, Binary
28, Binary
29, Binary
30, Binary
31, Binary
32, Binary
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
CM5SR
CMSSR
CM9SR
CM10SR
CMl2SR
Modulo
Modulo
Modulo
Modulo
Modulo
5, Shift
8, Shift
9, Shift
10, Shift
12, Shift
4 Bit Register with 2 Bit Mu Itiplexed Input
4 Bit Register with 2 Bit Multiplexed Input, Clear Direct
4 Bit Register with 2 Bit Multiplexed Input. Sync Clear
~odulo
Counter,
Counter,
Counter,
Counter,
Counter,
Counter,
Counter.
Counter,
Counter,
Counter,
Counter,
Counter,
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Clear
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Counter, Clear
Counter,Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Counter, Clear
Clear
Clear
Clear
Clear
Clear
I
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
--------------ICO@®[}{]3-81
GATE ARRAY SGH CELL LIST
1
11
MODULO
BINARY
UP COUNTER
MODULO
UP/DOWN
COUNTER
SYNCHRONOUS
COUNTER
f - - MODULO
LINEAR
FEEDBACK
SHIFT
REGISTER
!-I
CLOCK
PRESCALER
I
I
j----
r--
j----
CB41
Modulo
CB42
Modulo
CB4C
CB5C
CB6C
CB7C
CBSC
CB4F
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
CB5F
Modulo
CB6F
Modulo
CB7F
Modulo
CBSF
Modulo
CUD41
Modulo 16, Up/Down Counter,
Expandable Enable Clear Direct
Modulo 16, Up/Down Counter,
Expandable with Asynchronous Load and Clear
CUD42
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
4
4
4
4
4
Bit
Bit
Bit
Bit
Bit
M160C
M160D
M162C
M162D
M169C
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
4
4
4
4
4
Bit
Bit
Bit
Bit
Bit
C3LSR
C4LSR
C5LSR
C6LSR
C7LSR
CSLSR
Modulo
Modulo
Modulo
Modulo
Modulo
Modulo
L
L
L
L
L
L
near
near
near
near
near
near
PS2
Divide by 2 External Clock Prescaler
with No I nput Protection
Divide by 3 External Clock Prescaler
with No Input Protection
Divide by 4 External Clock Prescaler
with No Input Protection
PS3
j----
Binary Counter (74LS1611
Binary Counter (74LS161 )
Binary Counter (74LS163)
Binary,Counter (74LS163)
Binary Counter,
Optimized for Max Clock Freq
Bcd Counter (74LS160)
Bcd Counter (74LS160)
Bcd Counter (74LS162)
Bcd Counter (74LS162)
Up/Down Counter (74LS169)
M161C
M161D
M163C
M163D
M163F
PS4
TTL / CMOS
MSI
16, Binary Up Counter,
Expandable Enable Clear Direct
16, Binary Up Counter,
Expandable Enable Sync Clear
16, Binary Up Counter Fast, Sync Clear
32, Binary Up Counter Fast, Sync Clear
64, Binary Up Counter Fast, Sync Clear
128, Binary Up Counter Fast, Sync Clear
256, Binary Up Counter Fast, Sync Clear
16, Binary Up Counter Fast,
I ndividual Reset B & Set B
32, Binary Up Counter Fast,
I ndividual Reset B & Set B
64, Binary Up Counter Fast.
Individual Reset B & Set B
128, Binary Up Counter Fast,
Individual Reset B & Set B
256, Binary Up Counter Fast,
Individual Reset B & Set 8
7,
15,
31,
63,
127,
255,
Feedback
Feedback
Feedback
Feedback
Feedback
Feedback
Shift
Shift
Shift
Shift
Shift
Shift
Register
Register
Register
Register
Register
Register
M90C
M92C
M93C
M197C
M390C
M393C
Decade Counter (74LS390)
Divided by Twelve Counter (74LS92)
4 Bit Binary Counter (74LS93)
Presetable 4 Bit Binary Counter (74LS197)
Decade Counter (74LS390)
4 Bit Binary Counter
M4017C
M4520C
Decade Counter/Driver (4017)
Dual Binary Up Counter
-IID©®OO
3-82
_IC_D_©_@_O_O{]__~I
EKG3-8805
CMOS Gate Array
5GF Series
.Outline
The Ricoh gate array 5GF s.eries complies with the CMOS 1.5J.l rule, and offers high speed operation
with a gate delay time of 1.0 ns.
The 5GF series inherits the rich library of the 5GH series, and the SRAM and mask ROM can be used
as a memory cell. The cell library is compatible with standard cell RSC-15 series. It enables LSI
development to suit any system and production scale_
• Features
1_ Number of gates
6 types, from 2100 to 8200 gates
2.
High speed operation (CMOS 1_5J.l design rule)
Gate delay time ......... 1.0 ns (Typ.)
I/O cell delay time ....... 3.0 ns (Typ.)
I
SRAM access time ....... 55 ns (Max.)
Mask ROM access time .... 60 ns (Max.)
*Typ.: F.O. = 3, wiring length = 3 mm
3_
Extensive cell library
Macro cell ....... -...... 137 types
Macro function cell ...... 251 types
Total ............... 388 types
This library is perfectlY compatible with the cell library of the conventional gate array 5GH series
and the standard cell RSC-15 series. It is easy to convert from the gate array to the standard cell.
4. Memory cell
The SRAM and the mask ROM can be used as a memory cell. The memory and the logic circuit can
be configured on one chip.
5. Test cell
10 types of scan-path format test cells are prepared.
6.
Perfect design support by CAD
As a user design tool, the 5G F series supports the user with a system based on IBM-PC, logic diagram generation software, and logic simulation software (DASH-CADAT system). The series can
interface with EWS of MENTOR Co. and DAISY Co.
DASH and CADAT are registered trade mark of FutureNet Co. and H HB-Systems Co.
----------------ICO©®OO3-83
Gate Array 5G F Series
• Absolute Maximum Ratings
Symbol
Vcc
VI
VO
Topr
Tstg
Condition
Parameter
Power supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
Unit
V
V
V
C
°c
Value
-0.3 -7
-0.3 - Vcc + 0.3
-0.3 - Vcc + 0.3
-40 - 85
-55 - 125
for GND
• Recommended Operating Condition
Symbol
Vcc
Ta
Parameter
Power supply voltage
Operating temperature
Min.
4.75
a
VIH
VIL
VIH
VIL
VOH
VOL
III
10Z
Icc
Parameter
Condition
"H" input voltage (TTL)
"L" input voltage (TTL)
"H" input voltage (CMOS)
"L" input voltage (CMOS)
"H" output voltage
"L" output voltage
Input current
Output current for off state
Power supply current
Min.
2.2
-0.3
Vcc x 0.7
-0.3
2.4
Symbol
SRAM
(Ta =
Parameter
Condition
I/O output delay time
I/O input delay time
Inner gate delay time
Min.
CL - 15pF
FO = 3, Wire length = 3mm
FO = 3, Wire length = 3mm
MaskROM
Symbol
Iccl
Icc2
Iccl
Icc2
Parameter
Min.
Stand-by current
Operation current
Stand-by current
Operation current
Symbol
a-
Value
Typ.
16
10
(Ta =
Parameter
Address access time
a-
Value
Typ.
3.0
3.0
1.0
(Ta =
• Memory Cell AC Characteristics
tACC
Value
Typ.
Max.
Vcc + 0.3
0.8
Vcc + 0.3
Vcc x 0.3
Unit
.
.
• Memory Cell DC Characteristics
Memory
Unit
V
°c
V
V
V
V
V
10H - -4mA
10L- 4mA
0.4
V
-10
10
VI - a - Vcc
/-lA
-10
VO - a - Vcc
10
/-lA
mA
Power supply current depends on gete number, clock frequency.
• AC Characteristics
Tpdo
Tpdi
Tpd
Max.
5.25
70
(Ta = a - 70°C, Vcc = 5V ± 10%)
• DC Characteristics
Symbol
Typ.
5.00
25
Min.
(SRAM)
_. -_. '(Mask' Ror.ili·--
-ICD@®OO
3-84
a-
Value
Typ.
70°C, Vcc = 5V ± 10%)
Max.
Unit
ns
ns
ns
70°C, Vcc = 5V ± 10%)
Max.
50
30
50
20
Unit
/-lA/4bit
mA/4bit
/-lA/4bit
mA/4bit
70°C, Vcc = 5V ± 10%)
Max.
55
60
Unit
ns
ns
Gate Array 5G F Series
.5GF Series Line Up
Series
5GF21
5GF26
5GF32
5GF45
5GF58
Gate number
2100
2600
3200
4500
5800
8200
4-bit config.
4 x 512
4x512
4x512
4 x 1024
4 x 2048
4 x 2048
only (bit)'ii--bi~'~~~f'i'~:
8 x 256
8 x 256
8 x 256
8 x 512
8 x 1024
8 x 1024
16 x 256
16x512
SRAM
16-bit config.
5GF82
16 x 768
24-bit config.
*§
Mask
4-bit config.
'ji; ROM
8-bit config.
:; onl'{ (bit) ........ _.. -.... -.. :tc:
16-bit con fig.
a
24-bit config.
24 x 768
4 x 1024
4 x 1024
4 x 1024
4 x 2048
4 x 4096
4 x 4096
8 x 512
8 x 512
8 x 512
8 x 1024
8 x 2048
8 x 2048
16 x 512
16 x 1024
16 x 1536
.-----------------.-
---.---
24 x 1536
"
~r------L----------T---------r---------r--------T---------T---------t_------~
a Memory mix
4 x 256
4 x 256
4 x 256
8 x 256
8 x 512
8 x 512
:::i
4x512
4x512
4 x 512
8 x 512
8 x 1024
16 x 1024
E
SRAM
Mask ROM
---------
------------~~------
16 x 512
.------------ -- -.---._--._-
Number of remaining
gates (see * 2)
290
Number of I/O (see *3)
8 x 1024
---------._--. ------_._---_. ._._--------_. ---------- .---
660
84
1060
94
1050
102
120
1440
1980
138
168
DIP
24,28,40,
48
24,28,40,
48
24,28,40,
48
24,28,40,
48
40,48
Shrink DIP
42,64
42,64
42,64
64
64
FLAT
44,60,64,
80, 100
44,-60,64,
80, 100
44,60,64,
80,100
44,60,64,
80,100,
128*4
64,80,100,
128*4,
144 *4,
160*4
80, 100,
128*4,
144*4,
160*4
LCC
44,68
44,68,84
44,68,84
44,68,84
44,68,84
44,68,84
PLCC
28,44,68
28,44,68,
84
28,44,68,
84
28,44,68,
84
44,68,84
44,68,84
'"'"
"0<0
.><
<0
*1: The memory capacities noted above are the maximum values that can be mounted on
the chip.
*2: The number of logic gates that can be mixed varies with the mounted memory capacity.
*3:
Four of the I/O pads are dedicated to Vcc and GND.
*4:
Under development .
• Development tool (for CAD interface)
Hardware
Software
• EWS ... _.. _ .... LOGICIAN (Daisy)
IDEA1000 (Mentor)
• Personal computer. IBM-PC/AT(IBM)
• SW16 (Ricoh)
@
Ricoh cell library and simulation data
@
Ricoh development software
@
DASH, CADAT (Date I/O Co., only for
development on personal computers)
@ :
sold by Ricoh
--ICO@®[){]~
3-85
•
Gate array 5G F series
.5GF Series Development Flow
Customer
RICOH
• Logic diagram
• Timing chart
• Specifications
o ROM data
(EPROM or FD)
I. Schematic
interface
____ l _________ . . . . _____ .. _____________________ _
(e
n.
o ROM data
CAD
(~PROM
or F D l f =
o RICOH cell library
interface
,---------1
• Software for
develooment
(0 ROM library)
N
Timing simulation
Confirmation
y
N
Auto placement
and wiring
Confirmation
y
Mask creation '"
sample preparation
Evaluation
Mass production
y
Notice:
Specifications in the data sheet are subject to change without notice.
-ICO®®OO
3-86
Gate Array 5G F Series
• 5GF MEMORY ARRANGEMENT
Using SRAM only
SRAM
Specs.
Bit Word
Available Gate Count (Memory Structure Efficiency: Gate Count/Bits Count)
5GF21
5GF26
5GF32
5GF45
5GF58
5GF82
4
32
1120 ( 7.7)
1490 ( 8.9)
1890 (10.2)
2870 (13.4)
3710 (16.3)
5450 (22.1)
4
64
1070 ( 4.0)
1440 ( 4.6)
1840 ( 5.3)
2820 ( 6.9)
3660 ( 8.4)
5400 (11.3)
4
128
980 ( 2.2)
1340 ( 2.5)
1750 ( 2.8)
2720 ( 3.7)
3610 ( 4.3)
5350 ( 5.7)
4
256
780 ( 1.3)
1150 ( 1.4)
1550 ( 1.6)
2520 ( 2.0)
3470 ( 2.3)
5200 ( 3.0)
4
512
290 ( 0.9)
660 ( 1.0)
1060 ( 1.0)
2030 ( 1.3)
3220 ( 1.3)
4960 ( 1.6)
4 1024
(
)
(
)
(
)
1050 ( 0.9)
2630 ( 0.8)
4360 ( 1.0)
4 2048
(
)
(
)
(
)
(
)
1440 ( 0.5)
3170 ( 0.6)
4
(
)
(
)
(
)
(
)
(
)
(
)
8
32
880 ( 4.8)
1240 ( 5.4)
1650 ( 6.0)
2620 ( 7.7)
3470 ( 9.1)
5200 (12.0)
8
64
790 ( 2.6)
1160( 2.9)
1560 ( 3.2)
2540 ( 4.0)
3380 ( 4.7)
5120( 6.2)
8
128
630 ( 1.4)
990 ( 1.6)
1400 ( 1.8)
2370 ( 2.2)
3300 ( 2.4)
5040 ( 3.2)
8
256
290 ( 0.9)
660 ( 1.0)
1060 ( 1.0)
2030 ( 1.3)
3050 ( 1.3)
4780 ( 1.7)
8
512
(
)
(
)
(
)
1060 ( 0.9)
2630 ( 0.8)
4360 ( 1.0)
8 1024
(
)
(
)
(
)
(
)
1440 ( 0.5)
3170 ( 0.6)
8
(
)
(
)
(
)
(
)
(
(
)
)
16
32
(
)
(
)
(
)
2130 ( 4.8)
2980 ( 5.5)
4710 ( 7.0)
16
64
(
)
(
)
(
)
1980 ( 2.5)
2820 ( 2.9)
4560 ( 3.6)
16
128
(
)
(
)
(
)
1670 ( 1.4)
2670 ( 1.5)
4410 ( 1.9)
16
256
(
)
(
)
(
)
1050 ( 0.9)
2210 ( 0.9)
3940 ( 1.0)
(
)
1440 ( 0.5)
3170 ( 0.6)
16
512
(
)
(
)
(
)
16
768
(
)
(
)
(
)
(
)
(
)
2400 ( 0.5)
(
)
(
)
(
)
(
)
(
)
(
16
)
24
32
(
)
(
)
(
)
(
)
(
)
4200 ( 5.3)
24
64
(
)
(
)
(
)
(
)
(
)
3970 ( 2.8)
24
128
(
)
(
)
(
)
(
)
(
)
3740 ( 1.5)
24
256
(
)
(
)
(
)
(
)
(
)
3020 ( 0.9)
24
512
(
)
(
)
(
)
(
)
(
)
1860 ( 0.5)
24
768
(
)
(
)
(
)
(
)
(
)
710 ( 0.4)
Note: If no value is found under "Available Gate Count", those memory specifications are not possible.
----- --------ltO@@[}{]---3-87
Gate Array 5GF Series
Using MROM only
MROM
Specs.
Bit Word
Available Gate Count (Memory Structure Efficiency: Gate Count/Bits CouI).t)
5GF21
5GF26
5GF32
5GF45
5GF58
5GF82
4
128
1070 ( 2.0)
1440 ( 2.3)
1840 ( 2.7)
2820 ( 3.5)
3660 ( 4.2)
5400 ( 5.6)
4
256
980 ( 1.1)
1340 ( 1.3)
1750 ( 1.4)
2720 ( 1.8)
3610 ( 2.1)
5350 ( 2.9)
4
512
780 ( 0.6)
1150 ( 0.7)
1550 ( 0.8)
2520 ( 1.0)
3470 ( l.l)
5200 ( 1.5)
4 1024
290 ( 0.4)
660 ( 0.5)
1060 ( 0.5)
2030 ( 0.6)
3220 ( 0.6)
4960 ( 0.8)
4 2048
(
)
(
)
(
)
1050 ( 0.4)
2630 ( 0.4)
4360 ( 0.5)
4 4096
(
)
(
)
(
)
(
)
1440 ( 0.3)
3170 ( 0.3)
4
(
)
(
)
(
)
(
)
(
)
(
)
4
(
)
(
)
(
)
(
)
(
)
(
)
8
128
790 ( 1.3)
1160 ( 1.4)
1560 ( 1.6)
2540 ( 2.0)
3380 ( 2.4)
5120 ( 3.1)
8
256
630 ( 0.7)
990 ( 0.8)
1400 ( 0.9)
2370 ( 1.1)
3300 ( 1.2)
5040 ( 1.6)
8
512
290 ( 0.4)
660 ( 0.5)
1060 ( 0.5)
2030 ( 0.6)
3050 ( 0.7)
4780 ( 0.9)
8 1024
(
)
(
)
(
)
1050 ( 0.4)
2630 ( 0.4)
4360 ( 0.5)
8 2048
(
)
(
)
(
)
(
)
1440 ( 0.3)
3170 ( 0.3)
8
(
)
(
)
(
)
(
)
(
)
(
)
)
(
)
(
)
8
(
)
(
)
(
)
(
16
128
(
)
(
)
(
)
1980 ( 1.3)
2820 ( 1.5)
4560 ( 1.8)
16
256
(
)
(
)
(
)
1670 ( 0.7)
2670 ( 0.8)
4410 ( 0.9)
16
512
(
)
(
)
(
)
1050 ( 0.4)
2210 ( 0.4)
3940 ( 0.5)
16 1024
(
)
(
)
(
)
(
)
1440 ( 0.3)
3170 ( 0.3)
16 1536
(
)
(
)
(
)
(
)
(
)
2400 ( 0.2)
16
(
)
(
)
(
)
(
)
(
)
(
)
16
(
)
(
)
(
)
(
)
(
)
(
)
24
128
(
)
(
)
(
)
(
)
(
)
3970 ( 1.4)
24
256
(
)
(
)
(
)
(
)
(
)
3740 ( 0.7)
24
512
(
)
(
)
(
)
(
)
(
)
3020 ( 0.4)
24 1024
(
)
(
)
(
)
(
)
(
)
1860 ( 0.3)
24 1536
(
)
(
)
(
)
(
)
(
)
710 ( 0.2)
(
)
(
)
(
)
(
)
(
)
(
24
)
Note: If no value is found under "Available Gate Count", those memory specifications are not possible.
-ICD©®OO
3-88
CMOS GATE ARRAY 5GF series
CELL LIST
•
SYNCHRO~IZER I
COUNTER
---------------ICO@®IXl3-89
GATE ARRAY
[!{O ~~LL
5GF CELL LIST
I
-------------------------,
~1'lJ2 BUFFER
CELL
FUNCTION
INTOl
INT02
INTSCH
INCOI
INC02
INCSCH
TTL Compatible
TTL
TTL
CMOS Compatible
CMOS
CMOS
Inverter
Buffer
Schmitt Trigger
Inverter
Buffer
Schmitt Trigger
INTI U1
INT2UI
INTSUI
INCI UI
INC2UI
INCSUI
TTL Compatible
TTL
TTL
CMOS Compatible
CMOS
CMOS
Inverter
Buffer
Schmitt Trigger
Inverter
Buffer
Schmitt Trigger
------1---- -
with Resistance
for pull-up
---------
----------~----J
------------------~-
INTlDI TTL Compatible
INT2Dl TTL
INTSDI TTL
INCIDI CMOS Compatible
INC2DI CMOS
INCSDl__ ~~..<_>~
- - - - - ..
---
Inverter
Buffer
Schmitt Trigger
Inverter
Buffer
_______ Schm~ttT-,igger
~------.--.
l
_ _ _ _~
-------~
~UTPUiBUFF~-------
OUTINY Inverter
OUTTRI 3-State Output
OUTOPN Open Drain Output
---------
----------------~--------
OUTPUT AND
INPUT BUFFER
-
"------
IOTOI
lOTI
IOT02
IOT2
IOTSCH
IOTSH
lOCal
lOCI
IOC02
IOC2
IOCSCH
IOCSH
TTL Compatible
Inverter & 3-State Output
TTL Compatible
Buffer & 3-State Output
TTL Compatible
Schmitt Trigger & 3-State Output
CMOS Compatible
Inverter & 3-State Output
CMOS Compatible
Buffer & 3-State Ouptut
CMOS Compatible
Schmitt Trigger & 3-State Output
lOTI UI
IOTUI
IOT2UI
lOCI UI
IOCUI
IOC2UI
TTL Compatible
Inverter
TTL Compatible
CMOS Compatible
Buffer & 3-State Output
Inverter & 3-State Output
CMOS Compatible
Buffer & 3-State Output
TTL Compatible
Inverter & 3-State
CMOS Compatible
Inverter & 3-State ou~
with Resi~;a~~OTIDI
for pull-down_J
! ~OTDI
------------ IOCIDI
IOCDI
losc~i_A_TO_-~-----------I
&-3-State-outP~~~
---------------
XINOI
Input
Oscillator Output
XOUT
Oscillator
LXIO
-_ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ __
-ICO©([)[}{]-3-90
ou~
GATE ARRAY 5GF CELL LIST
@iIC~
I INVERTE~
1--~---1
INVO!
Inverter
Power Inverter (X2)
Power Inverter (X3)
Power Inverter (X4)
------------------~
I--~--I
L -_ _ _ _ _ _
TINVBF 3-State Inverter
TINVB3
3-State Inverter (X3)
Quad 3-State Inverter
TBF368
Quad 3-State Inverter
M368C
Octal 3-State Inverter (74LS240)
M240C
MS40C ~c~~_3_-S_t_a~nv~_te_r_(_74_L_S_S4_0~)________~
~~----~[BUFll--~B_u_f_k_r_______
BUFl2
BUF13
BUF26
Power Buffer (X2)
Power Buffer (X3)
Power Buffer (X6)
,--~~-~"------------------------,
I NAND
I--~--I
3BUF02
Ml25C
M367C
M244C
M245C
M54!C
M640C·
3-State Buffer Driver
3-State Buffer
Quad 3-State Buffer
Octal 3-State Buffer (74LS244)
Octal 3-State Bus Transceiver (74LS24S)
Octal3-State Buffer (74LS541)
Octal3-State Bus Transceiver (74LS640)
1--~---1
NAND02
NAND03
NAND04
NANDOS
NAND06
NAND08
2-Input
3-Input
4-Input
5-Input
6-Input
8-Input
~~~
--~~--
'--______--=-J------I DNAND2 Power 2-Inpu_t______________________-'
[NOR--
I--~--I
'---______----1
~----~
NOR02
NOR03
NOR04
NOR05
NOR06
NOROS
2-Input
3-Input
4-Input
5-Input
6-Input
S-Input
DNOR02
Power 2-Input
[ EXCLUSIVE
~--------------------1 XOR02
'---------------'
XNOR02
I'------------AND-NOR
~-------------------1
A0I2!
A0I3!
A0I4!
A0I22
A0I32
A0I23
A0I33
A0I24
A0I2!!
A00I22
MAJ23
2-Input Exclusive OR
2-Input Exclusive NOR
2-AND-NOR
3-AND-NOR
4-AND-NOR
2-Input,2-Wide
3-Input,2-Wide
2-Input,3-Wide
3-Input,3-Wide
2-lnput,4-Wide
2-AND Into 3-NOR
2-AND, 2-NOR Into 2-NOR
Inverting 2 of 3 Majority
----------------ICO®®[l(]3-91
GATE ARRAY 5GF CELL LIST
1 - - - - - - - - - - - 1 OAI21
2-0R-NAND
OAI3l
3-0R-NAND
OAI41
4-0R-NAND
OAI22
2-Input,2-Wide
OAI32
3-Input,2-Wide
OAI23
2-Input,3-Wide
OAB3
3-Input,3-Wide
OAI24
2-Input,4-Wide
OAI21l
2-0R Into 3-NAND
OAA~2_2_ ~~~__2:_NA_N_D In,t~_2-N~A~N~D~=====i
DLTOO
D-LATCH
DLTOR
Reset
DLTOS
Set
DLTSR
Set & Reset
NDLTOR Reset B
NDLTOS Set B
NDLTSR Set B & Reset B
DLGOO
Gated
DLNGOO Gated (Active L)
NDLGOR Gated, With Reset B
NLNGOR Gated (Active L), With Reset B=====~
RSLT
NRSLT
NRSCLT
RS-Latch
RS-Latch B
Common Gale
~
~T"~F~F-~sS~Rl:J ~:~te ~te______ ~
__.
NTFFOR
NTFFOS
Set & Reset
Reset B
Set B
~=====t----~ ~;%~~=R==_~_~~_~~_~=-e_s_e_t~~~==-=_=_==_ _ _=.====~
DFFOR
DFFOS
DFFSR
NDFFOR
NDFFOS
NDFFSR
DFFCOO
NDCOR
NDCOS
NDCSR
N2CSRT
M273C
J----i
LJJlKS:-!,F'.'F____
Reset
Set
Set & Reset
Reset B
Set B
Set B & Reset B
Clocked
Clocked, With Reset B
Clocked, With Set B
Clocked, With Set B & Reset B
Set B & Reset B
Octal D-Type Flip-Flop (74LS273)
JKOR
JKOS
JKSR
NJKOR
NJKOS
NJKSR
NJKCOR
NJKCOS
NJKCSR
NJ2CSR
Reset
Set
Reset & Set
Reset B
Set B
Reset B & Set B
Clocked, with Reset B
Clocked, with Set B
Clocked, with Set B & Reset B
Set B & Reset B No Spbufs and No SdBufs
~ll2C_~90-"ke~tive-,"1",~hJ>et_B&J<6.0 1-6250-' ·-·120----4'0'48.64--S- - - - - - 80,100 ---~-----
2.0.28.44.68.84
28.44.68.84
44.68.84
68.84
68.84.100
68.84.1.00.12.0
* 1·
. This table indicates nominal value for reference purpose, because routing area is depend on the complexity of designed circuit.
2· . GRID COU:O>T ~ COLUM:-I GRID number X ROW GRID number
*
.ABSOLUTE MAXIMUM RATINGS
Topr
Operating Ambient Temperature
-----------
Tstg
Storage Temperature
• ELECTRICAL CHARACTERISTICS
1/0 CECL'S DC ELECTRICAL CHARACTERISTICS (Ta=0-70°C, Vcc=5V±10%)
Limits
Symbol
Parameters
I
Measuring Condition
Max.
Min.
- - - - - . - - - - - - - - - - - - . - - - . - t - - - - - - - - - - - - - - - - - - - - - - _ . - ---'D~p.
Vee+D.3
2..0
___ ~_·"_I_ ._.I_nput __"H_·_·_Vo~age(}TL_:_o_m_p_at_ibl~!____ _+-----------------~_.
-0.3
.0.8
__ V,,:_~~~~_"_\_·o_lt_ag_e(~T_L__
eo_m_p_.ti~e~ ___ ~-.----.-- _________.__. __. ______+_--~~-_+--------+_-
____
Vo"
Output "H" Voltage
I_O.H__~_-_4_m_A_ _ _ _ _ _ _. _ __ I - -2.4
VOL
Output "L" Voltage
10I.~4mA
IL!
Input Leakage Current
VI = O-Vcc
ILO
Output Leakage Current
Vo~
D-Vee
Units
.-
V
V
V
.0.4
V
-1.0
10
"A
-1.0
1.0
"A
AC ELECTRICAL CHARACTERISTICS(Ta=0-70·C. Vcc=5V±10%)
Symbol
Limits
Parameters
I
Measuring Condition
Min.
Typ.
Max.
Units
tpdo
Output Buffer's Delay Time
CL~50pF
5.9
ns
tpdi
Input Buffer's Delay Time
FAN
OUT~
1. Wire
length~
3mm
2.9
ns
tpd
Internal Gate's Delay Time
FAN
OUT~
3. Wire
length~
3mm
2..0
taccl
RAM's Address Access Time
FAN
OUT~
3. Wire
length~
3mm
50
ns
tacc2
ROM's Address Access Time
FAN
OUT~
3. Wire
length~
3mm
50
ns
ns
---------------ICO©®[}(f-3-99
I
.DEVELOPMENT FLOW CHART
(USER)
(RICOH)
• SYSTEM DESIGN
• INVESTIGATE
DESIGN MANUAL
~
CELL LIBRARY
• LOGIC DESIGN
• TIMING SPEC. DETERMINATION
~
• NETWORK ENTRY
· TEST PATTERN ENTRY
•t
• DESIGN RULE CHECK
• LOGIC SIMULATION
I
· LOGIC SIMULATION
• FAULT SIMULATION
CONFIRM
NO
YES
I----~--------t_--• . AUTOMATIC PLACEMENT/ROUTING
•
CONFIRM
• RE SIMULATION & VERIFICATION
• MASK TOOLING' TEST PROGRAM GENERATION
NO
MASS PRODUCTION
DIP 14.16.18.20.22.24.28.
40.42.48.64·shl'ink PI"
FLAT 44.60.80.100 1'1\
PLCC 18.20.28.44.68.84 PI\
1'(;'\ 68.84.100.120 1'1\
--
-IIU®®[]{]-------------3-100
CMOS STANDARD CELL RSC-20 series
CELL LIST
§UTBUFFER
I
I OUTPUT BUFFER I
INPUT AND
OUTPUT BUFFER
I
ICO®®[}{]3-101
STANDARD CELL RSC-20 CELL LIST
I INPUT BUFFER
FUNCTION
STANDARDJt--------j CELL
~--------------~
INTO!
INT02
l
TTL Compatible Inverter
TTL
Buffer
OUTPUT BUFFER 1 1 - - - - - - - - - - - 1 OUTTSLP
OPENSLP
OPENSL
OUTTSL
OUTPUT AND
INPUT BUFFER
J
r------
IOTSLP
IOTSL
Inverter
Open Drain Output
Buffer
TTL Compatible Inverter & 3·State Output
TTL Compatible Buffer & 3·State Output
-ICD@®[ll]-------------3-102
STANDARD CELL RSC-20 CELL LIST
~=::J
I
Inverter
INVERTER
NBUF03
NBUF04
Power Inverte-;-(X3)------=
Power Inverter (X4)
M368C
M240C
M540C
3-State Inverter
-------Quad 3-State Inverter
Quad 3-State Inverter
Octal 3-State Inverter (74LS240)
Octal3-State Inverter (74LS540)
----_._------,.
r-ri
I' -BUFFER
---------'
---------
~
-------- - ----------BUFm~-----~
STANDARD
~
_____~~ff::__________
HPOWER Type ~------I~BU_FI3
BUF04
[NANn~~rlSTANDARD ~------I
NAND02
NAND03
NAND04
NAND05
NAND08
~
Power Buffer (X3)
Power Buffer (X4)
---.------~
3-STATE
f------I 3BUF02
'---------'
M125C
M367C
M244C
M245C
M541C
M640C
_~
_.
-.----- -
----- - - - - - - - - - -
3-State Buffer Driver
3-State Buffer
Quad 3-State Buffer
Octal3-State Buffer (74LS244)
Octal 3-State Bus Transceiver (74LS245)
Octal3-State Buffer (74LS541)
Octal 3-State Bus Transceiver (74 LS640)
I
2-lnput
3-lnput
4-lnput
5-lnput
8-lnput
~
~N=A=N=D=1=3==1=3=-I=np=u=t===== ____ _
f------I~~_~~~In_J'U~witl1_~~ate Output ~
'----------'
~g~J :::E:
NOR05
NOR08
-
5-lnput
8-lnput
_.. _"..- - - - -
---
--
~~g~f __!_::;~L----
n
---
___. ~
~-
2-lnput
3-lnput
;=====4=-ln pu_t- - - - - -
---l
XOR02
j
=-J
I
2-lnput Exclusive OR
L~OI~02___2_-I~pu~clu_si_v_e_N_O_R________---'
------r:,\OI21
I AOl31
AOI22
A0I23
l
2-AND-NOR
3-AND-NOR
2-ln put,2-W.id.e
2-lnput,3-Wide
A()I~4___
2-lnp~t,_~~e_
OAI21
OA131
OAln
OAI23
OAI24
2-0R-NAND
3-0R-NAND
2-lnput,2-Wide
2-lnput,3-Wide
2-lnput,4-Wide
.~
~
-----------ICO©@o{]3-103
STANDARD CELL RSC-20 CELL LIST
I FLIP-FLOP
LATCH
- - j RS-LATCH
----l D-FF
--jJK-FF
DLGOO
DLNGOO
NDLGOR
NLNGOR
Gated
Gated (Active L)
Gated, with Reset B
Gated (Active L), with Reset B
RSLT
NRSLT
M279C
RS-Latch
RS-Latch B
(Sl, S2, R)
DFFCOO
NDCOR
NDCOS
NDCSR
N74NC
Ml75C
M273C
M374C
Clocked
Clocked, with Reset B
Clocked, with Set B
Clocked, with Set B & Reset B
Clocked (Active L), with Set B & Reset B
Quad D-FF with Reset B
Octal D-Type Flip-Flop (74LS273)
Octal D-FF with Reset B (74LS374)
JKCOO
NJKCOR
NJKCOS
NJKCSR
MIl2C
Clocked
Clocked, with Reset B
Clocked, with Set B
Clocked, with Set B & Reset B
Clocked (Active L), with Set B & Reset B
-ICO©®[J[]-------------3-104
STANDARD CELL RSC-20 CELL LIST
I SHIFT REGISTER
I DECODER
I MULTIPLEXER
4 Bit Shift Register (74LS95)
4 Bit Shift Register with 3-State Output (74LS295)
8 Bit Parallel Output Serial Shift Register (74LS164)
Parallel Load 8 Bit Shift Register (74LSI65)
8 Bit Shift Register (74LSI66)
MI39C
MI55C
MI38C
M154C
2 to 4 Decoder (74LSI39)
Dual 2 to 4 Decoder
Gated 3 to 8 Decoder (74LS!38)
4 to 16 Decoder (74LSI54)
M42C
Bcd to Decimal Decoder (7442)
M157C
M158C
M257C
M258C
M153C
M352C
M353C
M253C
M251C
M151C
MI52C
MI50C
Quad 2 Bit Gated Non Inverting Mux
Quad 2 Bit Gated Inverting Mux
Quad 2 Bit Gated Non Inverting Mux with 3-State Output
Quad 2 Bit Gated Inverting Mux with 3-State Output
Dual 4 Bit Gated Non Inverting Mux
Dual 4 Bit Gated Inverting Mux
Dual 4 Bit Gated Inverting Mux with 3-State Output
Dual 4 Bit Gated Non Inverting Mux with 3-State Output (74LS253)
8 Bit Gated Mux with 3-State Output (74LS251)
8 Bit Gated Mux
8 Bit Inverting Mux
16 Bit Gated Inverting Mux (74LSI50)
L--.
I COUNTER
~
M95C
M295C
MI64C
MI65C
MI66C
f---~HRONOUS
COUNTER
~L/CMOSMSI
I
M393SC
M161D
MI63D
Synchronous 4 Bit Binary Counter
Synchronous 4 Bit Binary Counter (74LSI61)
Synchronous 4 Bit Binary Counter (74LSI63)
M393C
4 Bit Binary Counter
---------------ItO©®DO3-105
•
STANDARD CELL RSC-20 CELL LIST
I MEMORY
I ASYNCHRONOUS SRAM}--
COMPILED CELL
Data (D)
2
• An optional combination of data length from 6bits x 8bits minimum to 32bits x 32bits
maximum is possible in unit of 2 bits. (Example) 12 x 24, 8 x 16 and so on.
• Accumulator can be built-in for cumulative multiplication and addition. In this occasion,
the maximum 8bits can be selected as an expandable bit. (Example) 12 x 12 + 32 -+
32bits output.
• The output has 3-state control attached to enable an easy connection to the bus.
• It allows to use two's-complement or sign-magnitude numbers, while switching them with
control terminals TCX & TCY.
(1)
TCX X input
Multiplier
<
Block diagram >
Y input
TCY
CKX
CKM
MSP output
<
LSP output
A C characteristics >
Data input
TCX, TCY input
(Example) 16bits x 16 bits multiplier
CKX
CKY
Ts
Bitup time
Th
Hold time
Tmc: Multiplication time
Tmc
Td
CKL
CKty1
Td
MSP output
LSP output
Tds
TSM
TSL
3-132
: Output delay time
IOnS
SnS
62nS
ISnS
Tds : Output disable time
20nS
Ten: Output enable time
20nS
(2)
Multiplier/Accumulator
<
Block diagram
>
TCX
CKX
-I
TCY Y input
X input
!
1
X register
1
1
1 Y register 1
J.
CKY
J.
Booth multiplier
~-----------------~~
J.
ACC
Accumulator
SUB
CKP
PREL
expandable product Preload input
MSP output 'Preload input
LSP output
•
output
<
AC characteristics
>
Xinput, Yinput ----..
TCX,TCY
tS
ACC, SUB
CKX
CKY
.1
)(
tH
'I
r-\
tMAC
CKP
h
~
Yinput
Preload input
TRL, TRM
TRX, PREL
Data
Output
tS
to
:1
II
tH
4,
~
11
(Example) 16bits x 16bits + expandable by 3 bits, multiplier/accumulator
Ts
Setup time
IOnS
Th
Hold time
SnS
Tmac:
Cumulative multiplication addition time
Td
Output delay time
ISnS
Tds
Output disable time
20nS
Ten
Output enable time
20nS
3-133
72nS
2. ALU
<
(ARITHMETIC LOGIC UNIT)
Features>
• Data length can be selected from 4bits minimum to 60bits maximum in unit of 4bits at
option.
<
Block diagram >
s
R
Z
R input
N
OVR
Cout
F output
F
I,
11
I.
0
0
0
R+ S +Cin
0
0
1
S - R - 1 +Cin
0
1
0
R - S - 1 +Cin
0
1
1
R or S
1
0
0
1
0
1
1
1
0
R (fl S
1
1
1
R ~ S
Function
Arithmetic
operation*
R AND S
-
Logic
operation
R AND S
*Note: Two's-complement method
<
AC characteristics>
R input
S input
(Example) 16bits ALU
V
Td: ALU operation time
I.-I,in put~
Cin input
----"
Td
F output
II
3-134
55 nS
3. ADS
<
(ADDER SUBTRACTOR)
Features>
• Data length can be selected from 4 bits minimum to 64 bits maximum in unit of 4 bits at
option .
• In case of more than 36 bits, ripple connection in 2 rows of 4 bits CLA or hierarchical
structure in 3 row of 4 bits CLA can be selected.
<
Block diagram>
S
R
SELECT
Cout
ADD/SUB
F output
Cin
F
SELECT
<
ADD/SUB
•
ADS function
+ S +Cin
0
0
1
0
1
R - S - 1 +Cin
0
R+S
1
1
R-S
R
AC characteristics>
R input
(Example)
S input
16 bits Adder Subtractor
SELECT input
Td: Addition subtraction time
Cin
ADD/SUB
Td
F output
A
3-135
40nS
4.
<
B RS
(BARREL SHIFTER)
Features>
• The number of input/output bits can be selected from 1 bit to 32 bits in unit of 1 bit at
option .
• The number of shift can be set in optional number of shift from 1 bit shift to 32bits shift
at an optional interval.
<
Example 1)
Number of input/output bit 18 bits
Number of shift 0, 1,2,4,8, 16, 17, 18,32
Example 2)
Number of input/output bit 21 bits
Number of shift 0, 1,2,3, 30, 31,32
Block diagram >
DINB
INA
FIN
out
Shift is controlled by Fin. Fin corresponds to the number of pieces of the number of shift
and has 9 pieces in case of Example 1, while 7 pieces in case of Example 2. In addition, the
number of shift is arranged in the order of smaller number such as FinO, Fin 1 . ... In case
of operating 8 bits shift in Example 1, arrange only Fin4 to "1" and FinO~ Fin3, FinS ~ Fin9
to "0"
<
AC characteristics>
Din
Fin
(Example) 16bits width 16shifts function barrel
---.-I
shifter
~/
Td : Barrel shifter delay time
Td
Dout
/
3-136
18nS
5.
<
RGF
(REGISTER FILE)
Features>
• For file configuration, the word length from 6words minimum to 256words in unit of
2 words and bit length from I bit minimum to 64 bits can be independently selected at
option.
• I port and 2 ports can be selected.
<
Block diagram>
Din
Dain
Addr
WEB
LE
A Addr
WEB
LE
B Addr.
Dout
D Aout
D Bout
In case of 2 ports, write to register is made to the address of A address. In case of read,
the data specified by A address is output to A output port, while the data specified by
B address is B output port respectively.
*Note: LE
LE
<
= I, Output Latch is transparent.
= 0, Output Latch hold data
A C characteristics >
*Read Cycle
A Addr
A Addr
OAin
(x.
XX
.x
).
WEB
tRAS
tRAH
tLES tLW
H
{
LE
,tRAH
to
~
g~~~~-----------t~------------------::t--------Note: When tLES is not satisfied spec, outputs are fixed from Address.
*Write Cycle
(Output latchs are transparent) (Output latchs are hold)
A Addr
A Addr ---..J
--'----,
DAin
JK.
L tWOS
tWAS
::I:.
tWOHJ
tWAH
tWAS tWOW
UtWAH
WEB
f-..1
LE
OAout
OBout
\
~
A
4
3-137
•
(Example) 32bits 32words 2ports register me
Tras
Read address setup
28nS
Twds: Write data setup
5nS
Trah
Read address hold
InS
Twdh: Write data hold
3nS
Twas
Write address setup
IOnS
Td
Clock -+ Output
29nS
3nS
Tad
Address -+ Output
39nS
Twah : Write address hold
6. DMX
<
(MULTIPLEXER)
Features>
• Input bit length can be selected from 1 bit to 64 bits in unit of I bit at option .
• The number of input to be selected can be selected from 2 to 8 at option.
DOin
1
D
Olin
D8in
~
1
X
If-Fin
Dout
<
AC characteristics>
Data input
~
TO
-----1
Function input
\V
Data output
\ V--
(Example)
-
16bits 4inputs multiplexer
TD: Multiplexer data passing time
3-138
22nS
7. SEQ
<
(MICRO-PROGRAM SEQUENCER)
Features>
• Address width can be selected from 1 bit minimum to 24 bits maximum at option.
• Stack depth of micro-program counter (p PC) can be selected from 2 minimum to 14
maximum in unit of 1 at option.
• Since the register counter (RIC) is equipped with stack, it enables to nest the loop using
RIC as loop counter.
• Stack depth of register counter can be selected from 2 minimum to 14 maximum in unit
of 1 at option.
<
Block diagram>
Din
r------,
ZERO
PLA
Control
signal
Dout
*Note: Each Stack can be set indevendently.
<
A C characteristics >
Clock
(Example)
Sequence controller with address width
Instruction
12 bits, stack depth at PC side 8 and stack
input
depth at RIC side 6
Data input
Data output
3-139
Tcp
Clock cycle
Td
Instruction
52nS
->
Output
23nS
Table of the function
MUX 1
MNE- I
MONIC I RIC
14 13 12 II 10
FAIL
PASS
FAIL
I
MUX2
PASS
RIC
ENABLE
DIN
Stack 1 ! D IN Stack 1 Y
Stack 2 Y
Stack 2
X
D
CLEAR D
CLEAR 0
CLEAR 0
CLEAR HOLD
PL
X
D jHOLD
D
PUSH
HOLD
PL
HOLD D
HOLD
HOLD
MAP
,---
X 0 000
CJS
--
X 0 0 0 1
---~
JZ
--
~--
X 0 0 1 0
IMAP
-------- - - -
X 0 0 1 1
--
-
CIP
- -
-----
00100
--~~~~-
X 0 1 0 1
PUSH
D
HOLD
-" L" IHOLD~O
HOLD 0
~_t---D 1IOL~ D_ HO~D PCi HOLD _~_OLD HOLD PL
X
D' HOLD I D HOL~C I PUSH PC PUSH NOTEl PL
f--
JSRP
PC HOLD
,X
D
HOLOIn'Hoill
~JpUSH_~rUSH
X 0 1 1 0
ClV
X
0
IIOW!D1~ow IPCI HOLO
X 0 1 1 1
JRP
I--
X
D
HOLD ID _
fO
D
HOLD
D
i HOLD
=0
D IHOLD
D
HOLD
l!0
D 'HOLD
D IHOLD
-
~----
r--
--
o
1 0 0 0
f--
--~
RFCT
r-- ---0 1
o
,,-, ,- ,-, I
CRTN
X
X
ClFP
------
o
1 1 0 0
~
-
---
LDCT
D
D
HOLD
D ,HOLD
HOLD
f---- -
X I-D ______ HOLD
D HOLD
D \ HOLD
-
~
-~
j~ H~IE
<-:~ ~;- ~~~T~: j-~o~~1DlHO~D
D
X1111
c--1 0 1 0 0
~----~
1 1 000
1 1 0 0 1
1 1 1 0 0
TWB
HOLD
I
D
I
HOLD
D IHOLD
HOLD
PCI POP
D
i HOLD
pel
~rOLD
-----
D HOLD
RPCT
-- - - - - - --X 1 0 1 0
F
Pet
-
F [HOLD
DEC
PC POP
HOLD
PL
D
DEC
PL
HOLD
HOLD
F
PL
POP
HOLD
-~
-
-~--~------
POP
HOLD
LOAD
PL
PC POP
HOLD
PL
HOLD
PL
D
---
-
HOLD
- - - r--
PC HOLD
--
--~-
HOLD
-
--
PCIPOP
--
1---
DEC
- - - 1--- ----I-_t__ - - - - I-- ---- --- --- - - - PC POP
HOLD
D HOLD D i HOLD D POP
~O
PL
NOTEll PL
F
DEC
PL
LOAD
PL
D
NRFCT
fO
=0
F
fO
D HOLD
I D i HOLD D HOLD D HOLD DEC
=0
F
POP
IF
X
D
PUSH
-- ----
--
D IPUSH
PC PUSH
D
NLDCT
HOLD
PC PUSH
X
NRPCT
---
PL
--f---~--
NPUSH
----
PL
----
PC HOLD
F
PL
PL
PC HOLD
-
PL
PC HOLD HOLD
1-1---
F
HOLD
~--
HOLD
PC! HOLD
-
PL
HOLD HOLD VECT
H~!:-~~12f~~ ~ l!~~E_
I
~o
0 1
D
HOLD
F
~!.l_OL?_ 1--
H?LD I
POP
,F IPOP
--
D
HOLD
----
PC POP
HOLD
-".
PC POP
PL
POP
PC HOLD
PC HOLD
LOAD
PL
PUSH
PC HOLD
PC HOLD
LOAD
PL
X: Don't care.
NOTEl: When CCEN = 'L' & CC = 'H': HOLD
Otherwise LOAD
NOTE2: These instructions are for the nested loop using register counter.
3-140
-
'"
>I.l
E-<
0
Z
8. PIP
<
(PIPE LINE REGISTER)
Features>
• Data bit length can be selected from I bit minimum to 64 bits maximum in unit of I bit at
option.
• It enables to select whether or not to have scanpath function.
• Since the output has 3-state control attached, it enables to connect to bus easily.
<
Block diagram >
Din
Cp
PI .p
(SCp)
t--(SDIN)
(SCPCP)
(SDOUT)
Paraenthesis ( ) is used when
selecting scan path function.
TRI
DOUT
<
AC characteristics>
Clock
I
--
Data input
~ Ts~
~ Th
---1
Data output
Tri
(Example)
32bits pipe line register with scanpath attached
Ts
Setup time
Th
Hold time
Td
Clock
->-
SnS
OnS
Output
18nS
Ten: 3-state enable
lSnS
Tds: 3-state disable
lSnS
,H41
•
9. M R 0
(Asynchronous Mask ROM)
< Features>
• Word by bits organization
Maximum size
Bits per word
Word length
• Fast access time
• Low power dissipation
• Two control inputs
<
can be selected within the following range.
64K bits
8 ~ 16 bits
128 ~ 32K words
55nS (4K x 16)
(Active) 28mA (Output data 16bits, f= 20 MHz)
(Standby) lOJ.!A
CEB, OEB
Block diagram >
Memory array
---0 Vee
Ao
I
---0 GND
An
< AC characteristics >
tACC
Ao
~
An _ _ _J
CEB
----,
~_.~tC~E_--I
OEb
Dout
3-142
CEB logie
--0 CEB
OEB logic
OEB
10. S R A
<
(Asynchronous SRAM)
Features>
• Word by bits organization can be selected within the following range.
Maximum size
Bits per word
16K bits
2 - 8, 16 bits
Word length
• Fast access time
• Low power dissipation
• Three control inputs
<
32 - 4K words
65nS (Bit width 16 bits)
(Active) 40mA (Output data 8bits, f= 10 MHz)
(Standby) 10pA
CEB OEB, WEB
Block diagram>
----0 Vcc
Memory array
----0 GND
Ao
I
An
0-
CEB logic
'--------'
CEB
R/W control logic --0 WEB
OEB logic
Dout
<
Din
AC characteristics >
*Read Cycle
tRC
Ao -An
--_../
tACC
CEB
tHZ
tCE
OEB
tOHZ
Dout----------4
"'--------""
3-143
--oOEB
I
*Write Cycle
WEB control
1--~~~--,tW~C ~_ _--I
Ao
~
A_n_ _---/
tCW
CEB
tAS
tWR
tWP
WEB
Din
Dout __~~~~~~----------~--K
CEB control
t WC
1------
Ao
v----
~A n
"---
tAS
tWP
tCW
"-
CEB
V
tWP
WEB
/7
"
""
tDW
Din
tLZ
Dout
I
I
tWZ
,[
3-144
I
tDH
>k==
11. S S R
<
(Synchronous SRAM)
Features>
• Word by bits organization
Maximum size
Bits per word
Word length
can be selected within the following range.
8K bits
2 - 16bits
32 - 2K words
SOnS (256 x 16)
• Fast access time
(Active) 15mA (Output data 16bits, foo 10 MHz)
• Low power dissipation
(Standby) 10j.!A
• One clock input & Three control inputs CK, CEB, OEB, WEB
<
---
--<)
GND
CEB logic
CEB
Clock buffer
CK
Memory array
Ao
Ar
<
AC.characteristics
*Read Cycle
R/W control logic
WEB
OEB logic
OEB
Din
>
*Write Cycle
CK
tPCW
tWCW
CK
Ao - A_n_ _-.f
'-_+-____+--/
Ao - A_n_ _--'
CEB
CEB
WEB
WEB
OEB ------,..
Din
Dout
------~-~========H---1-145
'---+_ _ _ _+----"
I
12. H S R
<
(Synchronous SRAM)
Features>
• Word by bits organization
Maximum size
Bits per word
Word length
• Fast access time
• Low power dissipation
can be selected within the following range.
32K bits
2 ~ 64bits
32 ~ 4K words
25nS (256 x 16)
(Active) 15mA (Output data 16bits, f= 10 MHz)
(Standby) 10pA
• One clock input & Three control inputs CK, CEB OEB, WEB
• Either Data Latch Mode or Non Data Latch Mode can be selected. Latch Mode will be
fixed after compilation.
--0 Vcc
< Block diagram >
--0
Memory array
GND
Address latch
control logic
CEB logic
Ao
I
Clock buffer
An
R/W control
logic
cS utput
latch
control logic
OEB logic
<
AC characteristics >
D out
Din
i) Data latch Mode (DlB = "l")
*Read Cycle
tPCW~t---tWCW-
CK
Ao
~A n
CEB
t-tAf±j-,
~
";(
%
tCEH- r-------------,
~
\
tWES/
r--
WEB
tOES-\
f--
OEB
~~~~~----------f. -tWEH
-
I-- tOEH
tOH-: ~tCA
Dout
::l()(I
3-146
XXX
*Write Cycle
-tPCW--tWCW-
/
CK
tAS--=t= -tAH:!
Ao
~A n
A(
tCES--!--
CEB
------------1,
f
-
-,
tWP
tWEH
±
WEB
Din
I-tCEH
-----------------
1'-:.
tDW-tDH
I DB ;K
-tWDF L
tWA
DB
.:I:
I
:1(
DA
tOH~
o out
oa:
'J.:t DA
'IX
Note: tWDF is specified from CK or WEB, whichever occurs last.
ii) Non Data Latch Mode (DLB = "H")
*Read Cycle
tPCW~f--tRCW-
CK
tAH
tAS J
Ao
~An
A(
tCES-
-
tWES-
-
tOES-
-
CEB
WEB
OEB
Dout
*-
tCKLZ:::ft;j:tCA
I:Xl(
-tCEH
-
-tWEH
~
;--tOEH
tCKHZ
tOH
'I
*Write Cycle
CK
Ao
~
tAS
An:....-._ _ _ _J1'--+_ _/I'-_t-_ _ _ _ _ _ __
tCES
CEB
WEB
Din
Dout
Note: tWDF is specified from CK or WEB, whichever occurs last.
3-147
•
• A C characteristics table.
1. MUL (MULTIPLIER)
Symbol
Parameter
A C characteristics
Ts
Data setup time
MIN IOnS
Th
Data hold time
MIN
Td
Output delay time
(Clock -* Output)
MAX l5nS
Tds
Output disable time
MAX 20nS
Ten
Output enable time
MAX 20nS
5nS
In case of multiplier
( i ) When the larger one 'of X input and
Y input is below 16 bits,
X + Y + 30nS
Tmc
Multiplication time
( ii) When the larger one of X input and
Y input is above 18 bits and below 24 bits,
(X + Y) * 1.25 + 30nS
(iii) When the larger one of X input and
Y input is above 26bits and below 32bits,
(X + Y)
*
1.25 + 40nS
In case of multiplier/accumulator
( i ) When the larger one of X input and
Y input is below 16 bits,
Y + Y + 40nS
Tmac
Cumulative multiplication
addition time
(ii) When the larger one of X input and
Y input is above 18 bits and below 24 bits,
(X + Y) * 1.25 + 40nS
(iii) When the larger one of X input and
Y input is above 26bits and below 32bits,
(X + Y) * 1.25 + 50nS
3-148
2. A L U
Symbol
(ARITHMETIC LOGIC UNIT)
Parameter
A C characteristics
Bit length
Td
ALU operation time
4, 8
12, 16
20, 24
28, 32
36, 40
44,48
52, 56
60, 64
50
55
65
70
80
90
100
110
[nS]
[ nS ]
[nS]
[nS]
[nS]
[nS]
[ nS ]
[ nS ]
3. ADS (ADDER SUBTRACTOR)
Parameter
AC characteristics
Addition substraction excution time
[nS]
5*m/16+35
(4 ~ m ~ 64, m: bit length)
Symbol
(Ripple)
---
Td
Addition subtraction excution time
(Carry look ahead)
5*m/16+35
(4 ~ m ~ 32)
5*m/16+30
(36 ~ m ~ 48)
5*mjI6+25
(52 ~ m ~ 64)
(m: bit length)
[nS]
4. BRS (BARREL SHIFTER)
Symbol
Td
Parameter
Barrel shifter passing time
A C characteristics
0.5 * m + 10
(m is bit length)
3-149
[ nS ]
•
5. R G F (REGISTER FILE)
Symbol
Parameter
A C characteristics
Tras
Read address setup time
A+ B/4 + 5
[nS 1
Trah
Read address hold time
1
[nS 1
Twas
Write address setup time
A+ 5
[nS]
Twah
Write address hold time
A/4 + 1
[nS 1
Twds
Write data setup time
Twdh
Write data hold time
A/4 + 1
[nS 1
Td
Clock -+ output delay time
WEB -+ output delay time
B/4 + 21
[nS 1
Tad
Address--+output delay time
A
*
Latch enable setup time
A
*2
[nS 1
A
[nS 1
2 + B/4 + 21
~~--
Ties
r"---""
Twdw
[nS 1
~
Write enable pulse width
B/4 + 1
[nS 1
Latch enable pulse width
B/4 + I
[nS 1
--~-"
Tlw
Note: When word length is below:
6 ~ 8 words
A= 3
A= 4
10 ~ 16 words
18 ~ 32 words
A =5
34 ~ 64 words
66 ~ 128 words
130 ~ 256 words
A=6
A=7
A=8
6. D M X (MULTIPLEXER)
Symbol
Td
Parameter
Multiplexer passing time
AC characteristics
[nS 1
m/4 + 18
(m is bit length)
7. SEQ (MICRO-PROGRAM SEQUENCER)
Symbol
Parameter
A C characteristics
Td
Instruction input --+ output delay
Tcp
Clock cycle
23
m + 40
(m is address width)
3-150
[nS 1
[nS 1
--
8. PIP (PIPE LINE REGISTER)
Symbol
Parameter
AC characteristics
Ts
Setup time
5
[ nS 1
Th
Hold time
0
[ nS 1
Ten
Output enable time
15
[ nS 1
Tds
Output disable time
15
[ nS 1
Td
Clock
-'>
9. M R 0
(Asyncronous Mask ROM)
Symbol
Parameter
[ nS 1
m/!6 + 16
(m is bit length)
output delay
Limits
Condition
Unit
Max.
Min. I Typ.
-- - -
tACC
Address access time
tCE
CEB access time
tOE
OEB access time
-~
tDF
r---tOH
Note I:
..
-------~-
OEB or CEB to output in
high Z
- - . - - - - - -..
Fan Out = 3
Wire length = 3mm
o
o
0.46 x (V-I) + 0.26 x (H-2) + 37.1
9 ~ Bit ~ 16 .................................. V
= WORD/128,
................ V
< 256 .................
= WORD/256,
V = WORD/128,
= WORD/512,
V = WORD/256,
V = WORD/128,
................ V
< 512
< 256
I
................
i
i
I
I
H = Bit
H = 2 x Bit
H = Bit
H = 4 x Bit
H = 2 x Bit
H = Bit
~
WORD
~
~
WORD
................ V = WORD/I024, H = 8 x Bit
WORD < 1024 ................ V = WORD/512, H = 4 x Bit
256
~
WORD < 512 ................ V
128
~
WORD < 256 ................ V
3-151
= WORD/256,
= WORD/128,
N d
::
nS
I----
128
Bit = 2
1024
512
................
nS
nS
I
r----f-----J
-~-
Output hold from address
change
5 ~ Bit ~ 8
256 ~ WORD
128 ~ WORD
3 ~ Bit ~4
512 ~ WORD
256 ~ WORD
~_
Notel
H = 2 x Bit
H = Bit
I
nS
I
nS
10. S R A (Asyncronous SRAM)
*Read Cycle
Symbol
Condition
Parameter
h---T~~m~~~--Min. Typ. Max.
---1---- ~--
Unit
I
tRC
Read cycle time
I
--------------------1
1--------
tACC
tCE
------
~B access time
tOE
tOH
OEB access time
i Output hold from address
r------ I change
tHZ
I
I
----~
----I- -----
I
I
I
Bit = 2, 3
........... ............... tACCjtCE
Bit = 4, 8, 16 .......................... tACCjtCE
Bit = 5, 6, 7 .......................... tACCjtCE
-
0
-----------
nS
------
-
nS
I
I
I
0
nS
----.--
30
f
l-
CEB-output disable time
Note2
-
1------+- ---I
OEB-output disable time
tOHZ
Note 2:
!
"---
nS
::;1---
-j
-
!
Fan Out = 3
Wire length = 3mm
Note2
I
I
I
-----
------------
nS
----,--------- ----
Address access time
----
----
Note2j
--
!
0
30
nS
30
nS
I
= 60nS
= 65nS
= 70nS
*Write Cycle
Symbol I
~WC
l
Limits
Condition__________ f-----,-----,------t Unit
Min. Typ. Max.
Parameter
-------------+----1
[Wri~l-e ti~e_______
tWP
i Write pulse width
tCW
[Ch!p selection to end of
60
f----+--+
45
------------+-[- - - - - - - - - - - 1
I--_ _--+I_w_rl_te ____--:- _______
~~S
tWR
nS
nS
nS
45
I
J
- - - - ,--- - + - - - + - - - - 1
I Address setup tIme
:
o
nS
! Write recovery time
I
15
nS
----+-----------~
tOW
I Data valid to end of write
to H
I
[
I
Data hold t i m e j
tWZ
I
WEB to output in high
I
15
I
CEB to output in low Z
I O!
l
i
nS
G_~-+l~_+_I,
zl
n_S--t
~--~-------------l
~O""'-- ~EB to output in low Z
I
tLZ
i nS
I
1
3-152
I
I
30
nS
I
I
i 30
I nS
11. S S R
(Syncronous SRAM)
*Read Cycle
Condition
Parameter
Symbol
tPCW
Clock width for pre charge
cycle
tRCW
Clock width for read cycle
tCA
Clock access time
tAS
Address
setup
time
-_.. _..
...
Address hold time
tAH
r---------------CEB setup time
tCES
--tCEH
CEB hold time
tWES
___
tWEH
WEB----hold time
tOES
c--------- --tOEH
OEB hold
,,'uptime
----tCKLZ 3~_t~ outp~t in low Z
------cCK to output in high Z
tCKHZ
tOH
Output hold from CK
change
Min.
60
----
60
~O
- ---
~------
JV-~~~~!~_time~
-
-------_.----
~:
~--------
~j
----1
Fan Out = 3
Wire length = 3mm
I:W: j
--.~--~.-
Less than 4K bits:
More than 4Kbits:
3
10
0
0
c---- ,
0
r------O
r-------- .
0
c---
0
2
-~-~------~--~
Note 3:
nS
nS
Note3 nS
c---nS
nS
nS
nS
nS
nS
nS
nS
5
nS
10
nS
nS
---~
-~
~-----
~-~--~
Unit
I
-~
-~
Limits
Typ. Max.
I------~-r-
50nS
59nS
*Write Cycle
Symbol
Parameter
tPCW
Clock width for precharge
cycle
Condition
-
twCW-
I----~-~-----~--
Clock width for write cycle
tWP
Write
pulse width
f-----tAS
Address setup time
------ -------tAH
Address hold time
tDW
~
- - - - - - - I __D'" vruid 'o_'nd of
tDH
Data
hold
time
c----~
tCES
CEB setup time
tCEH
CEB hold time
tWEH
WEB hold time
~----~-
-~--
Limits
. Unit
Min. ! Typ. Max.
nS
60
60
30
f----.
20
0
20
5
0
0
0
-----~------
-~.--~-----.---~
-------
-~
wri',
~---~
3-153
---
nS
nS
nS
InS
nS
nS
nS
nS
nS
12. H S R
(Synchronous SRAM)
*Read Cycle
Symbol
Parameter
Condition
r---~~--j-----
tPCW
Clock width for pre change
cycle
tRCW
Clock width for read cycle
tCA
Clock access time
tAS
Address setup time
f------tAH
Address hold time
tCES
CEB setup time
~CEH
CEB hold time
tWES ------_._-----_._-WEB setup time
r---:-;-;---- -tWEH
WEB hold time
tOES
OEB setup time
tOEH PcEB hold time
~C:KLZ- CK to output in low Z
f---tCKHZ
CK to output in high Z
r---wH- I - Output hold from CK
change
f----=-:--~c-
Limits
Typ. Max.
I
Min.
25
Unit
nS
--~-
Note4
f----
~O- r-
".-~-~--
f--~--
---------~
-~~~--
nS
nS
nS
nS
nS
nS
nS
nS
Note4
5
~6
Fan Out = 3
Wire length = 3mm
r--0
f----O
I-- 0 I
f--f---
O!
lis
0
nS
nS
nS
nS
--
10
10
I
0 I
5
*Write Cycle
Symbol
Parameter
Condition
tPCW
Clock width for prechange
cycle
f------tWCW
Clock width for write cycle
r-- tWP
Write pulse width
--tAS
Address setup time
---tAH
Address hold time
I- tDW ----Data valid to end of write
1------tDH
Data hold time
1-tCES
CEB setup time
[
f------tCEH
CEB hold time
f--:t-WEH
WEB hold____time
c _____
1------tWA
WEB access time
--I--tWDF
CK or WEB to output in
high Z
f----
Min.
25
Limits
Typ. Max.
Unit
nS
~----~-------
-
~-----
----.-,---._-"
----------------~----
I----~
---"---------------~-----
'l1s
-6
------------------===1
~-
0
0
~_
Note 4:
nS
nS
nS
nS
Note4
Note4
1-----10
5 --15
1------ 10
--
~
0
nS
nS
nS
t----nS
nS
nS
tCA, tWP = 2 x BITS x SHAPE/!6 + 1.2 x WORDSjSHAPEj256 + 3l.8 [nS]
tRCW, tWCW = 2 x BITS x SHAPE/!6 + 1.2 x WORDSjSHAPEj256 + 36.8 [nS]
BITS ............ Bits per word
WORDS ........ Word length
SHAPE ......... See right table
Word length SHAPE
I- - 32 - 512
2
513 - 1024
1-- 1025 - 2048
4
-=-----2059 - 4096
8
3-154
• DSP EMULATION CHIP SET LIST.
RICOH can offer emulation chip set for the preparation of breadboard required for the
development of product, using DSP cell library .
There are 6 different kinds of emulation chips available as follows.
l. RP5S1016
2. RP5S1010
...........
. ..........
3. RP5S3910 . ..........
16 bits x 16 bits multiplier
16 bits x 16 bits expandable by 3 bits multiplier/accumulator
Address width 16 bits micro-program sequencer
MPC side stack depth 8
R/C side stack depth 6
4. RP5S3030 . ..........
16 bits width barrel shifter (optional shift from 0 to 16 bits)
5. RP5S3010 . ..........
16 bits length arithmetic logic operation unit
6. RP5S3020
. ..........
16bits 32words 2ports register file
These chips are all offered in 64pins shrink DIP package or 64pins flat package.
Pin configuration
o
diagram
Shrink
DIP
33
3-155
•
• EMULATION CHIP.
1. RP5S1016 (16bits x 16bits multiplier)
<
Features>
• TTL compatible low power consumption CMOS multiplier
• Multiplication time 50nS
• Complements display of 2
Display of absolute values and their mixed mode multiplication
• Single + 5 V power supply
• Suppliable with shrink DIP 64pins or flat package 64pins.
<
General description >
RP5S 1a16 is high speed low power consumption 16 x 16 parallel multiplier. X and Y
input registers are independently controlled positive edge trigger D type flip-flop respectively.
Each input data can be used for either complement of 2 or absolute value display. Since the
product register has 3-state output and input and input register can also be controlled independently, it enables to connect RP5S1016 with external bus easily.
By adding I to MSB of RP5S1016, RND control, which rounds the product, is incorporated to MSP. To control FA, shift MSP by I bit, then, repeat sign bit on MSB of LSP, to
change data format for the output of complement of 2. FA control must be used only for
calculation of complement of 2. FT control makes output latch transparent.
RP5S1016 makes high speed operation possible by using modified Booth algorithm, carry
save adapter, CLA (carry foresight circuit), etc.
No
RP5SI016
Pin name
No
Pin name
No
Pin name
No
Pin name
I
X4
17
P 8, Y8
33
P 8, Y 24
49
Vee
2
X3
18
P 9, Y 9
34
P 9, Y 25
50
TCY
TCX
3
X2
19
P 10, Y 10
35
P 10, Y 26
51
4
Xl
20
PI!, YII
36
P 11, Y 27
52
RND
5
XO
21
P 12, Y 12
37
P 12, Y 28
53
CLKX
6
OEL
22
P 13, Y 13
38
P 13, Y 29
54
Xl5
7
CLKL
23
P 14, Y 14
39
P 14, Y 30
55
XI4
8
CLKY
24
PIS, Y 15
40
PIS, Y 31
56
XI3
9
PO, YO
25
PO, Y 16
41
CLKM
57
XI 2
10
PI, Y I
26
PI, Y17
42
OEP
58
XII
II
P 2, Y 2
27
P 2, Y 18
43
FA
59
XIO
12
P 3, Y3
28
P 3, Y 19
44
FT
60
X9
13
P 4, Y4
29
P 4, Y 20
45
HSPSEL
61
X8
14
30
X7
47
GND
GND
62
31
P 5, Y 21
P 6, Y 22
46
15
P 5, Y 5
P 6, Y6
63
X6
16
P 7, Y 7
32
P 7, Y 23
48
Vee
64
X5
3-156
--
2. RP5S1010 (16bits x 16bits + expandable by 3bits multiplier/accumulator)
<
Features
•
•
•
•
•
<
">
16 x 16 bits parallel multiplication/ cumulative addition
Multiplication/Cumulative addition time 65 nS
Data format displaying complement of 2 or absolute value
Single 5V power supply
Suppliable with shrink DIP 64pins or flat package 64pins
>
General description
RP5S1010 is TTL compatible high speed low power consumption 16 x 16bits multiplier/
accumulator.
Low power consumption has been achieved by CMOS, and high speed operation has been
achieved by modified Booth algorithm, carry save adapter, CLA (carry foresight circuit), etc.
RP5S1010 has 16bits input bus of 2 systems, 16bits MSP product bus of I system and
3 bits expandable bus.
Input register is the same D type positive edge trigger fli-flop as the product register.
Since the product register has 3-state function and input/output clock can also be controlled
independently, it enables to connect direct with 16bits external bus. RP5S1010 has RND
control and by adding I to MSB of LSP of the multiplier, product can be rounded to MSP.
By using preload control together with 3-state control, it initializes the content of output
register. RP5S 1010 executes multiplication and addition, multiplication and subtraction and
only multiplication depending upon the control condition of ACC and SUB. It performs
switching between complement of 2 and absolute value display with TC control.
No
RP5S1010
Pin name
No
Pin name
No
Pin name
No
Pin name
I
X6
17
P 8, Y8
33
P 24
49
Vee
2
X5
18
P g, yg
34
P 25
50
CLKY
3
X4
19
P 10, Y 10
35
P 26
51
CLKX
4
X3
20
P 11, Y11
36
P 27
52
ACC
5
X2
21
P 12, Y 12
37
P 28
53
SUB
6
Xl
22
P 13, Y 13
38
P 29
54
RND
TSL
7
XO
23
P 14, Y 14
39
P30
55
8
PO, YO
24
PIS, Y 15
40
P31
56
XIS
9
PI, Y I
25
P 16
41
P32
57
X14
10
P 2, Y 2
26
P17
42
P33
58
X13
11
P 3, Y3
27
P 18
43
P34
59
X12
12
P 4, Y4
28-
P 19
44
CLKP
60
Xli
13
P 5, Y5
29
P 20
45
TSM
61
Xl0
14
P 6, Y6
30
P 21
46
PREL
62
X9
15
P 7, Y7
31
P 22
47
TSX
63
X8
16
GND
32
P 23
48
TC
64
X7
3-157
•
3. RP5S3910 (16bits micro-program sequencer)
<
Features>
• Since address width is 16bits, it enables to use micro-cord up to 64K words.
• 16 bits down counter for loop statement and repeat statement is built-in.
• The address of micro-program can be selected among 4 including micro-program counter,
branch address bus, 8 level pPC side stack and internal retention register.
• Output bus is 3-state output.
• Clock cycle SOnS
<
General description>
RP5S3910 is the address sequencer which controls the execution sequence of microinstruction stored in the micro-program memory. In addition to the successive sequence, it
enables to perform the conditional branch under optional address in 64K microwords.
The stack of last-in first-out makes return of micro sub-routine and nesting loop possible.
It allows micro sub-routine up to 8 levels and nesting of loop up to 6 levels. The loop of
micro-instruction is countable up to 65536 times.
With individual micro-instruction, micro-program sequencer can select 16 bits address from
the following 4 sources.
As source, there are CD micro-program address register (pPC) retaining 1 additionally
incremented value from the current address, ~ Direct input (D) from external bus,
® register counter (RIC) which retains load data that have been prepared beforehand and
@ 8 levels last-in first-out stack (F).
RP5S3910
No
Pin name
No
Pin name
No
I
RLD
17
FULL2
33
YO
49
DO
2
FULLI
18
Y 15
34
CI
50
DI
D2
No
Pin name
Pin name
3
SCP
19
Y 14
35
SDIN
51
4
SCPCP
20
Y 13
36
CP
52
D3
5
SDOUT
21
Y 12
37
-
53
D4
-
PL
22
Yll
38
Y 10
39
24
Y9
40
9
--VECT
--CCEN
23
25
Y8
41
10
CC
26
Y7
42
6
7
8
MAP
-
lJ
14
27
Y6
43
12
I 3
28
Y5
44
13
I 2
29
Y4
45
14
I I
30
Y3
46
15
I 0
31
Y2
47
32
YI
48
16
-CE
3-158
-
-
54
D5
55
D6
56
D7
57
D8
58
D9
59
DI0
60
DlJ
-
61
D12
DE
62
D13
GND
63
D14
Vee
64
DIS
4.
<
R P5S3030
(16 bits barrel shifter)
Features>
• Data width 16bits
• Shift can be set at option from 0 to 16 in unit of 1 bit.
• High speed operation
<
30nS
General description >
RP5S3030 is the barrel shifter which shifts the data with optional number of bits in the
optional direction. Data width is 16 bits, and the number of shift can be set at option from
o to 16 in unit of 1 bit.
Input is 32bits, and output is 16bits. When setting the input data to the right end of barrel
shifter, rightward shift can be set from 0 to 16 at option. When setting the input data to the
1eftend, leftward shift can be set from 0 to 16 at option. When setting the input data at the
center, it sets each 8bits leftward and rightward at option.
No
RP5S3030
Pin name
No
Pin name
No
Pin name
No
Pin name
1
I 15
17
YO
33
S4
49
I 31
2
I 14
18
Y1
34
S 3
50
I 30
I 29
3
I 13
19
Y2
35
S2
51
4
I 12
20
Y3
36
S 1
52
I 28
5
III
21
Y4
37
SO
53
I 27
6
I 10
22
Y5
38
-
54
I 26
7
I 9
23
Y6
39
-
55
I 8
24
Y7
40
-
I 25
8
56
I 24
9
I 7
25
Y8
41
10
I 6
26
yg
42
-
57
I 23
58
I 22
11
I 5
27
Y 10
43
-
59
I 21
12
14
28
Yll
44
-
60
I 20
13
I 3
29
Y 12
45
119
I 2
30
Y 13
46
-
61
14
62
118
15
I 1
31
Y 14
47
GND
63
I 17
16
10
32
Y 15
48
Vee
64
116
3-159
•
5. RP5S3010 (16bits arithmetic logic operation)
<
Features>
• Data are 16bits width
• High speed operation 45 nS
<
General description
>
RP5S3010 is the high speed low power consumption arithmetic logic unit developed under
CMOS technology of 16bits data width with 8 functions. High speed has been achieved by
using CLA (carry foresight circuit) in the inside.
RP5S3010 has 3 kinds of arithmetic logic functions and 5 kinds of logic operation functions. Since it has carry propagation signal (P) and carry generation signal (G), hierarchical
structure of CLA can be fabricated by connecting it with external CLA chips.
No
RP5S3010
Pin name
No
Pin namf>
No
Pin name
No
Pin name
1
S 7
17
eIN
33
F 12
49
SIS
2
R7
18
I 2
34
F 13
50
RI5
3
S6
19
I 1
35
F 14
51
S 14
4
R6
20
IO
36
FI5
52
RI4
5
55
21
FO
37
-
53
513
6
R5
22
F 1
38
-
54
RI3
7
S4
23
F2
39
8
R4
24
F3
40
9
53
25
F4
41
10
R3
26
F5
42
11
S 2
27
F6
12
R2
28
F7
--
55
S 12
56
RI2
57
Sl1
p
58
Rll
43
G
59
S 10
44
eOUT
60
RIO
13
5 1
29
F8
45
OVR
61
S9
14
Rl
30
F9
46
ZERO
62
R9
IS
SO
31
FlO
47
GND
63
S8
16
RO
32
Fll
48
Vee
64
R8
3-160
6. RP5S3020
<
(32words x 16bits 2ports register file)
Features>
• Memory capacity of 32words 16bits
• 2 ports configuration of write input I and read output 2
• High speed access 45 nS
• Low power consumption
<
General description
>
RP5S3020 is the register file configulated with 32words 16bits 2 ports. Low power
consumption operation is possible under CMOS technology. It has I write port and 2 read
ports. Since 2 read ports have 3-state output independently, they allow connection with
different external bus.
The write operation of RP5S3020 is such that, when write enable signal (WE) is "L", the
write data' (D) in the write port is written in word line specified by address control input A.
The read operation is such that, when latch enable (LE) of the data of word line specified by
address control inputs A and B is "H", each is output from each port A and B. Read port A
and Bare 3-state output respectively and controlled by 3-state control signal OEA and OEB.
RP5S3020
Pin name
Pin name
No
Pin name
No
I
AO
17
YB3
33
YBll
49
2
Al
18
YA4
34
Y A12
50
D I
3
A2
19
YB4
35
Y B 12
51
D2
4
A3
20
YA5
36
Y A13
52
D3
5
A4
21
YB5
37
Y B 13
53
D4
6
LE
22
YA6
38
Y A14
54
D5
WE
23
YB6
39
Y B 14
55
DB
OEA
24
YA7
40
Y A15
56
D7
OEB
25
YB7
41
Y B 15
57
D8
10
YAO
26
YA8
42
B4
58
D9
11
YBO
27
YB8
43
B3
59
D 10
12
VAl
28
YA9
44
B 2
60
Dll
13
YBI
29
YB9
45
B I
61
D12
14
YA2
30
Y AI0
46
BO
62
D13
15
YB2
31
Y B 10
47
GND
63
D14
16
YA3
32
YAll
48
Vee
64
D15
No
7
8
9
Pin name
-
--
No
3-161
DO
I
• D S P development flow & tools.
Application Specific DSP
development flow chart
development tool
bigh-Ievellanguage
C, PASCAL etc.
schematic entry
DASH
NG
4.
architecture
logic, timing simulater
verification
CADAr
meta-assembler
interactive
(
function
simulater
}
timing simulater
CADAr
NG
IC
3-162
}
emulation tip
}
emulater
under development
• Application Example.
This is an example of a digital filter using DSP and RSC-15 series cells.
A sampling frequency of up to 139 KHz can be achieved by constructing a filter of more than
100 degree FIR. (The CD sampling frequency is 44.1 KHz)
16
input data
I
I
shift register
--.( V
16
I
ROM
128 x 16
J;6
~I
It=
-
multiplier/accumulator
I
~V
/
V
address counter
T
timing cont.
(counter)
T
40
I
over flow limitter
16
"'-V-
I
~r-
output latch
It
It 16
~v
output data
3-163
cscilator
•
EKM.7·8807
NMOS 64 Kbit MASK ROM
(8,192 word x 8 bit)
RP2364E
•
GENERAL DESCRIPTION
•
The RP2364E is static NMOS Read Only Memory organized as 8,192 words by 8-bits and operate from a single +5V
supply.
The RP2364E features automatic power·down mode.
When Chip ,Enable (CE) goes HIGH level, the supply
current is reduced from lOOmA (max.) to 20mA (max.).
The device has Chip Enable (CE) input and output
Enable (OEjOE) inputs allowing up to 32 wired ORs to
be tied without external decoding.
According to your order, logic of the following pins
may be selected ACTIVE LOW or ACTIVE HIGH or NC.
Pins 1,22, 26 and 27.
and Pin 20 may be selected as CE or OE.
•
PIN CONFIGURATION (Top view)
Vee
OEdOEdNC
OE,/DEi/NC
OE,/OEt/NC
As
A9
All
Al
IT/OE:/OE:,
Ao
0,
00
0,
01
0,
O.
GND
0,
05
FEATURES
•
e8,192 words X8 bits organization
eLow power dissipation: Active
550mW max.
Standby llOmW max.
e Fast access time: 200ns max.
eSingie +5V(±lO%) power supply
eCompletely TTL compatible: All outputs and inputs
•
PIN DESCRIPTION
PIN NAME
Ao
00
~
~07
OE1~OE5
CE
NC
Vcc
GND
FUNCTION
Address Input
Data Output
Output Enable
Chip Enable
No Connection
Power Supply
GND
DA T A OUTPUTS
BLOCK DIAGRAM
Al
A,
A:.
Ao
A.
A,
Ao
Alo
.+-----Q
Vee
----..0
GND
OEI/OEI
Ao
Al
A,
ADDRESS INPUTS
A12
OEdOE2
'"
OUTPUT
ENABLE
R,I92 WORD
W
0..
0..
~
x SBIT
00
V)
V)
MEMORY CELL
w
'"
- \ CHIP
CE ENABLE
Q
Q
f
-<
All
A"
ICO©®[}{]4-3
•
RP2364E
• ABSOLUTE MAXIMUM RATINGS
Condition
Symbol
Parameter
,
- - f-Supply Voltage
Vee
f-----~~- 1--~------~
Input Voltage
With respect to GND
VI
Output Voltage
Vo
Ta=25·C
Maximum Power Dissipation
Pd
I--Topr
+-Operating Ambient Temperature
Tstg
Storage Temperature
Limit
-0.5-7
-0.5-7
-0.5-7
700
0-70
-40-125
-----~-----
--1--
-~-
•
Unit
V
V
V
mW
- - I-~-
'c
'c
RECOMMENDED OPERATING CONDITIONS (Ta=O-70'C)
Symbol
Vee
-~
~~-
---~~--~----
Supply Voltage
r---input High Voltage
Input Low Voltage
VIL
•
Specified Value __
Min
Typ
Max
4.5
5.0
5.5
2.0
Vec
-0.5
0.8
Parameter
1-----
Unit
",V
V
ELECTRICAL CHARACTERISTICS
-DC ELECTRICAL CHARACTERISTICS (Ta=0--70'C. Vcc=5V±10%)
Symbol
Parameter
Test Condition
Specified Value
Typ
Min
Max
20
100
2.4
0.4
2.0
Vee
-0.5
O.S
-10
10
f---
~---
Supply Current (Standby)
IcC!
~1JPply Current (Active)
Iecz
--Output HIgh Voltage
VOH
VOL
Qutput Low Voltage
~H _ _
~~put High Voltage
_
__\111:.___ _Input Low Voltage
_
CE=Vcc
Io=OmA
IOH= -400!'A
IOL=3.2mA
-+
-;::~----t-~~t~tu;~:~~:~;~:r:tnt------
-
VI =OV-Vec
I
i
Vo=OV-Vcc
Chip Deselected
-10
10
- AC ELECTRICAL CHARACTERISTICS (Ta=0-70'C. Vce= 5V± 10%)
Symbol
~~--
Parameter
------------~~-------
Test Condition
--~~--
Read Cycle Time
tRe
Address Access Time
tACC
Chip
Enable Access Time
teE
-----'-----Output Enable Access Time
tOE
----
Specified Valve
Min Typ Max
200
SO
ns
ns
ns
ns
80
ns
200
200
---- ----------------
----~------------
tOE
Output Hold Time after
Output Enable Change
tOH
Output Hold Time after
Address Change
tCH
Output Hold Time after Chip
Enable Change
Output Load =
lTTL+ 100pF
ns
0
80
Notes: 1. Input Pulse Levels: VIL=0.6V, VIH=2.2V
2, Output Timing Reference Level: VOL =0.8V, VOH =2.0V
-ICD®®DO
4-4
Unit
ns
Unit
rnA
rnA
V
-V
V
V
!'A
!'A
RP2364E
-TERMINAL CAPACITANCE
Symbol
Ci
Co
•
Parameter
Specified Value
Typ
Min
Max
Test Condition
Input Capacitance
Output Capacitance
8
f=lMHz
12
Unit
pF
pF
TIMING CHART
tRC
ADDRESS INPUT
~
----./
<
)
tACC
(---,
'\
(OE)
_ _ _ _ _ _ _ _ _ _ _ ..J
<
I
--~
'/
/ ,'---- f - - - - - -
-
tOH
tOE
tOF
..::-.
7~
"\:
..
tCE
tCH
•
V
DATA OUTPUT
I'\.
)-
---------------ICO®®OO4-5
RP2364E
•
28 PIN PLASTIC PACKAGE (Unit: mm)
14
1~,----15.2______
4
110.25+0.13
--fg
~-ICD©(ID[)[J
4-6
-0.05
o·
15"
EKM·8·8807
NMOS 128kbit MASK ROM
(16,384word X 8blt)
RP23128E
•
GENERAL DESCRIPTION
The RP23128E is static NMOS Read Only Memory
organized as 16,384 words by 8-bits and operate from a
single + 5V supply.
The RP23128E features automatic power-down mode.
When Chip Enable (CE) goes HIGH leveL the supply
current is reduced from 100mA (max.) to 20mA (max.).
These devices have Chip Enable (CE) input and output
Enable (OE/OE) inputs allowing up to 16 wired ORs to be
tied without external decoding.
According to your order, logic of the following pins may be
selected.
Pin 22 (active low/active high)
Pin 1,27 (active low/active high/No Connection)
Pin 20 (Chip Enable/active low/active high)
•
PIN CONFIGURATION (Top view)
V"
OE,
OE.
NC
Au
A"
A.
A"
A,
A"
A,
GE) OEI
A,
CE
A"
0,
A",
0"
0.
0,
0,
OE,'OE,
0,
GND
• FEATURES
• 16,384 words X 8 bits organization
• Low power dissipation: Active 550mWmax.
Standby II0mW max.
• Fast access time: 200ns max.
• Single + 5V (±10%) power supply
• Completely TTL compatible: All outputs and inputs
•
•
PIN DESCRIPTION
PIN NAME
Ao"VAIl
00'00 7
OE,"VOE4
CE
NC
Vcc
GND
FUNCTION
Address Input
Data Output
Output Enable
Chip Enable
No Connection
Power Supply
GND
•
DATA OUTPUTS
BLOCK DIAGRAM
A"
A,
A2
~-.--,----,-;;,---,
Alll
A"
16.384 wORD
-----0
OE,/ OE ,
+---0
OEdOE,
OEo/ OE,
I
OUTPUT
J EN ABLE
OE4IOE4
xSB1T
ADDRESS IN P1JTS
ME:\10RY CELL
A,
A,
A,
-I
CE
CHIP
El'ABLE
,A."
A120---All
a---
--------------ltO®®DO4-7
RP23128E
• ABSOLUTE MAXIMUM RATINGS
•
RECOMMENDED OPERATING CONDITIONS (Ta=O-70'C)
Symbol
,
SpecIfIed Value
_~_Parameter_____ ~r.1-'I1T~ M~-;- ~mt
_. Supply Voltage _____ ~ ___ ~_.~ --~5t5.0
Input High Voltage
2.0
Input Low Voltage
- ~-=-o:-3. .
Vee
--v;;,~---
---v;;.---
5.5
Vee
V
V
0.8
-V-
• ELECTRICAL CHARACTERISTICS
-DC ELECTRICAL CHARACTERISTICS (Ta=()--70'C, Vec=5V±IO%)
'I
Symbol
I
Parameter
,
Test Condition
Specified Value
Max
I Min 'Typ
Unit
~-~{~~:~:
~~~~~:rL--~R~-==--====-~-r---J--~1-~-~-=
OutPu.tJ:l:igh.I~lt;~;-~-~--fk>H= ~400pA
...1:L_t.-_=t-
- VOH
VOL
VlH
VIL
III
V
I
----I
ILO
I
O_lltp-"t..!:ow~oltage
I·
IOL=2.0mA
=r__ ____
Input High_~ltage
Input L(),,: V oltage ~
Input Leakage Current
~
~________
_____J..."'I = OV - Vee
Vo=OV-Vcc
-
,
Output Leakage Current
__ ~.'______ 1--.0.4
~~_o_+
Vee
~ 0.3 I
O.
~ 10
1~+'
w-
~ 10
Chip Deselected
10
I
V
V
V __
pA__
pA
eAC ELECTRICAL CHARACTERISTICS (Ta=O-70'C, Vee=5V±10%)
Symbol
_______
P
t
I Specified Valve I U .
arame er______ -~yp Lr.1axL~
tRe
Read Cycle Time
tACC
A-......(---,.._r-"1;ro
A,
A,
OE./Olli }
O&/Olli OUTPUT
=
ENABLE
DE3/v!'..3
A"
Au
ADDRESS INPUTS
OUTPUTS
A,
A.
A,
A.
A,
CE
A.
A.
Au
A"
A"
1CHIP
ENABLE
---.-.:::::':::=:':::::C_________~:::J
---------------ICO©®OO4-11
I
RP23256D/E,RP23257D/E
•
ABSOLUTE MAXIMUM RATINGS
Symbol
Vee
VI
Vo
PdTopr
Tstg
•
Parameter
Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature
Storage Temperature
Unit
V
Limit
-0.5-7
-0.5-7
-0.5-7
700
0-70
-40-125
_.
With respect to GND
Ta=25'C
--y-V
mW
-----
·c
·c
RECOMMENDED OPERATING CONDITIONS (Ta=O-70'C)
Symbol
Parameter
--
Vee
_VIH
VIL
--
•
Condition
Supply Voltage
Input High Voltage
Input Low Voltage
Specified Value
Min
Typ
Max
4.5
5.0
5.5
2.0
Vee
-0.5
0.8
r--- - - -
Unit
V
V-V
ELECTRICAL CHARACTERISTICS
eDC ELECTRICAL CHARACTERISTICS (Ta=(}-70'C, Vee=5V±lO%)
Symbol
Parameter
IcC!
Icc2
VOH
VOL
VIH
VIL
r-ILl
Supply Current (Standby)
Supply Current (Active)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
ILO
Output Leakage Current
Test Condition
CE=Vec
Io=OmA
IOH= -400,uA
IOL=3.2mA
Specified Value
Typ
Min
Max
20
100
2.4
0.4
2.0
Vee
-0.5
O.S
f--
---10
-10
VI =OV-Vcc
Vo=OV-Vec
Chip Deselected
1-----
-10
10
I
Unit
mA
mA
V
V
V
V
,--,uA
,uA
eAC ELECTRICAL CHARACTERISTICS (Ta=O-70'C, Vec=5V±lO%)
Symbol
tRe
~c
teE
tOE
Parameter
Test Condition
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
tOF
Output Hold Time after
Output Enable Change
tOH
Output Hold Time after
Address Change
teH
Output Hold Time after Chip
Enable Change
I
RP23256D/257D
Min Typ Max
250
250
250
100
Output Load =
ITTL+IOOpF
RP23256E/257E
Unit
Min Typ Max
- - r---200
ns
200
ns
200
ns
80
ns
100
0
80
ns
ns
0
--
100
80
ns
Notes: I. Input Pulse Levels: VIL=O.6V, VJH=2.2V
2. Output Timing Reference Level: VOL=0.8V, VOll=2.0V
--ICO@®OO~--~~~~~~~~~~-
4-12
RP232560/E,RP232570/E
• TERMINAL CAPACITANCE
Symbol
Parameter
Ci
Co
•
Specified Value
Typ
Min
Max
Test Condi tion
-- r---
--
Input Capacitance
Output Capacitance
8
f=lMHz
12
Unit
pF
pF
TIMING CHART
tRC
ADDRESS INPUT
~
-J"
K
)(
tACC
,-----
___________ J
"',- ~
-- ......,
/
V,
'---- f - - - - - -
-
tOH
tOE
tDF
~
"...
7
tCE
tCH
•
./
DATA OUTPUT
~
"'"
) I--
---------------ICD©®DO4-13
•
RP23256D IE, RP2325 7D IE
•
28 PIN PLASTIC PACKAGE (Unit: mm)
14
15.24
110.25+0.13
-0.05
~
--ICO@®DO------4-14
o·
W
~IC_D©_@_[}(]~~/
EKM-l0-8807
NMOS 1Mbit MASK ROM
(131,073 word X 8bit)
RP231026D/E
•
•
GENERAL DESCRIPTION
The RP231026D/E is a static NMOS read only
Memory organized as l31,072 words by 8 bits and
operates from a single+5V supply.
The RP231026D/E features automatic power-down
mode. When Chip Enable (CE) goes HIGH level. the
supply current is reduced from 100mA (max.) to 30mA
(max.).
Pin 20 can be used as OE.
According to your order, Logic of the OE pin may
be selected ACTIVE LOW or ACTIVE HIGH.
PIN CONFIGURATION (Top view)
vee
AI<
A7
AI3
A6
A,
As
ADDRESS
INPUTS
<0
•
OUTPUTS
r'
Alu
M
- ClII!'
'OE ENABLE
'"
Il..
~
Ao
e131,072 words x 8 bits organization
e Low power dissipation Active
550mW max.
Standby
165mW max.
e Fast access time
RP231026D 250ns max.
RP231026E 200ns max.
eSingle +5V (±10%) power supply
e Completely TTL compatible: All outputs and inputs
e 3-state outputs for wired-OR expansion
e Pin compatible with Intel 27512
Alii
0
'"
.-<
AI
FEATURES
ADDRESS
INPUTS
Ail
Ci
A:!
A2
•
A,
~
"'-
A,
0,
11
06
01
OUTPUTS
0,
0,
o:!
BLOCK DIAGRAM
DATA OUTPUTS
--0 Vee
--0 (;ND
A,
Az
A.,
-- ) OUTPUT
ENABLE
A,
--0 OE/OE
AIO
A16
131.072 WORD
x
ADDRESS
INPUTS
A,
A,
A7
A,
H BIT
MEMORY CELL
r
:3
A,
u
~
A"
::;
:J
Al~
e:::i!
-z
u~
AI"'
AI1
--0
cr ) CHIP
ENABLE
Ali
----------------ICO©@OO4-15
RP231026D/E
• ABSOLUTE MAXIMUM RATINGS
c-~:~~h_S_U_P_PlY ~~i~m-e:r~~====~.!
~ ~~i:}~~_____t~f~~
Condition
__ ___
~._~_Input Vo!.!.<'g,,__________
With respect to GND
_-=().,,3-Vcc+:(~3_____L-\'....~_+-?utPut Voltaf(e . ______..
_. ________._______
-o.:l-Vcc+O.:l-J.. \'
Pd
: Maximum Power Dissipation
Ta~25"C=~':"'_~~IJ-==_L-~\V-::Topr 'TOp~~i~~ J\mj;;':;~t;r eJllpe~~tur<_~=--. --------______~~ ___ +_~-
Tstg
'Storage Temperature
•
RECOMMENDED OPERATING CONDITIONS (Ta=O-70"C)
•
ELECTRICAL CHARACTERISTICS
_ DC ELECTRICAL CHARACTERISTICS (1'a = 0-70"C, Vcc= 5V± 10%)
-.-h-.:~~: _~~~~~~:!:~-:~-. -.~-~-~:-~-~-?ft~!F-~~~~~
Symbol
Parameter
VOI'.-Outpu_tHi~V()ltage
VOL
OutPllt Low_V.oltage
VIII
Input High Voltage
y;;---
}"_-=1
ILO
T.est Condlt~n____
-------
-4(J-125
i"C
Specified \' alue
l::~
-~~- M", [ T"
c, .,-_
... _·-_-_J_I-o,-,=-C,OO,A_ _ _ _
. ____ :_IcJi.:..=2.,OmA
_______ .~'___
Inp,rtLo-;;Volt~g~------
Lealz. SYNC. D.-D" A,-A'5. R/W
Output Low Voltage
q". if>z. SYNC. D.-D,. A.-A 15• R/W
Power Disspation (no-load)
Input Capacitance Logic
0.-0,
SYNC. Ao-A'5. R/W
A
AND
Logical AND of memory and accumulator.
Operation: AI\M -> A
using in list
Subtract
Exclusive OR
Transfer
Transfer
Logical OR
Program Counter High
Program Counter Low
"P" Register: N,V,Z,C
The result is stored in accumulator.
"P" Register.: N,Z
A SLOne bit left shift. LSB is placed ";r". Contents of MSB is placed C.
Operation .C~ [f]6JSl4l3l2lllol ~"o"
"P" Register
N,Z,C
B B R If specific bit of zero page is a reset state, branch relatively.
I OP·Code
Low Order Address
I
Off~ 3·byte instruction
If the specific bit (a bit is decided on the instruction code) of effective address
l 00 l Low Order Addre~ is a reset state, relative branch by the I9ffsetl value on the basis of
lead address of next instruction.
Operation: branch when Mb = 0
"P" Register : not affected
BBS
If specific bit of zero page is a set state, branch relatively.
I OP·code I Low Order Address I Offset I 3·byte instruction
If the specific bit (a bit is decided on the instruction code) of effective address
100 I Low Order Address Iis a set state, relative branch by the lOffsetl value to base with lead
address of next instruction.
Operation: branch when Mb = 1
"P" Register
Not affected
BCC Branch if the carry is reset.
Operation: branch when C = 0
"P" Register
Not affected
BCS
Branch if the carry is set.
Operation: branch when C = 1
"P" Register
Not affected
BEQ
Branch if the zero flag is set.
Operation: branch when Z = 1
"P" Register : Not affected
BIT
Test the memory bit by the accumulator.
Operation: AI\M,M, -> N, M, -> V
The bit 6 and bit 7 of the memory are transferred to "P" Register.
If the result of AI\M is zero, Z= 1
"P" Register: N, V, Z
(M,)(M,)
BM I
Branch if result is negative.
Operation : branch when N = I
"P" Register
Not affected
-ICD®®o{]---------------5-16
BNE
Branch if result is not zero.
branch when Z = 0
Operation
"P" Register: Not affected
BP L
Branch if result is positive.
branch when N"- 0
Operation
"P" Register
Not affected
BRA
Unconditional branch.
"P" Register
Not affected
B R K Forced break
Operation: Execute the interrupt. In this instruction, a lead address (2-byte) of next
instruction is stored in the stack. At the same time, it is stored into contents of "P"
Register. Program-counter (FFFE) ~ PCL, (FFFF) -> PCH, and Execution of program is
same vector address with IRQ. The difference from the IRQ interrupt is that in the BKK
operation, the B flag of "P" register is set "1" and can't mask by the I flag.
BVC
BVS
"P" Register:
~
Branch if the overflow flag is reset.
Operation
branch when V = 0
"P" Register
Not affected
Branch if the overflow flag is set.
branch when V = 1
Operation
"P" Register
Not affected
"P" Register :
c
"P" Register
D
0
"P" Register
V
"P" Register
V
CLC Clear the carry flag
Operation
(C)
o _.• C
0
ClD Clear the decimal mode.
Operation
Cli
O->C
Clear the interrupt disenable flag (I).
0->1
Operation
0
ClV Clear overflow flag.
Operation
O->V
0
CMP Compare memory with accumulator.
Operation: A-M
The result is not stored. If it is nagative, N flag is set 1.
And if it is zero, Z and C flags are respectively 1.
C P X Compare memory with the index register X
Operation: YoM
Flag condition of "P" Register is the same as CMP.
If it is positive, C flag is set 1.
"P" Register
N, Z, C
"P" Register
N,Z,C
C P Y Compare memory with the index register Y.
Operation: YoM
Flag condition of "P" Register is the same as CMP.
"P" Register
N,Z,C
Decrement the contents of memory.
Operation
M ~ 1 -> M
"P" Register
N,Z
D E X Decrement the contents of index register X.
Operation: X ~ 1 -. X
"P" Register
N, Z
Decrement the contents of index register Y.
Operation
Y ~ 1 -> Y
"P" Register
N, Z
DEC
DEY
E0 R
Execute the exclusive OR of memory and accumulator.
---------------llO©®OO5-17
•
INC
Operation : AVM ---+ A
"P" Register
N, Z
Increment the contents of memory.
Operation : M + 1 ---+ M
"P" Register
N, Z
I N X Increment the contents of index register X.
Operation : X + 1 ---+ X
"P" Register
N, Z
I NY
Increment the contents of index register Y.
Operation : Y + 1 ---+ Y
"P" Register
N, Z
J MP
Execution of program jUl.lPS to designation address.
Operation:
I OP·Code I Operand I Operand I
"P"Register : Not affected
The designation address by operands with 2·bytes is placed in PCL and PCH.
J S R The execution of program jumps to designation address.
Operation: When jump to designation address, return address (lead address of next
instruction) is stored ·into stack. The return is executed by RTS.
I OP·Code I
Operand
I
Operand
I
"P"Register : Not affected
The disignation address by operands with 2 bytes is stored into the PCL and PCH.
Lead address of next instruction(2·byte)--Ms, S - 1 ---+ S
I
Ms, S - I---+S
L D A Load the contents of memory to the accumulator.
Operation : M ---+ A
"P" Register
N, Z
L D X Load the contents of memory to index register X.
Operation: M---+X
"P" Register
N, Z
L D Y Load the contents of memory to index register Y.
Operation : M ---+ Y
"P" Register : N, Z
L S R One bit right shift. MSB (7bit) is placed to 0, LSB ( 0 bit) is loaded the C.
Operation: 0 .... 17161514131211101 .... C
"P" Register: ~,Z, C
NOP
No·operation
Operation : No operation
ORA
Logical OR of memory and accumulator.
Operation : A VM ---+ A
P HP
Store the contents of the register P into the stack.
Operation: P ---+ Ms, S-1 ---+ S
"P" Register : Not affected
The result is stored into the accumulator.
"P" Register
N, Z
P H A Store the contents of the accumulator into the memory stack.
Operation: A ---+ Ms, S-l---+ S
"P" Register
Not affected
"P" Register
Not affected
P H X Store the contents of the index register X into the stack.
Operation : X ---+ Ms, S-I---+ S
"P" Register
Not affected
P H Y Store the contents of the index register Y into the stack.
Operation: Y ---+ Ms, S-I---+ S
"P" Register
Not affected
P L A Pull accumulator from stack.
Operation : Ms ---+ A, S+ 1---+ S
"P" Register
N,Z
"P" Register
Restore
P LP
Pull processer status from stack.
Operation : Ms ---+ P, S+ 1 ---+ S
-ICO©®OO--------------5-18
P L X
PLY
RM B
Pull X register from stack.
Operation
Ms ~ X, S + 1 ~ S
"P" Register
N,Z
Pull Y register from stack.
Operation
Ms ~ Y, S+ 1 ~ S
"P" Register
N,Z
Reset the specific bit in the zero page address.
[ OP·Code
[ Low Order Bit [Z-byte instruction
The specific bit (a bit is decided by the instruction code) of execution address
LQQJJow Order Address I is reset.
Operation
0 ~ Mb
"P" Register: Not affected
R0 L
Rotate left circular of one bit. The contents of the MSB are moved into the C, the contents
of the Care moved into the LSB.
Operation Y716151413~
"P" Register
N, Z, C
R0 R
Rotate right circular of one bit. The contents of the C are moved into the MSB, the
contents of the LSB are moved into the C.
Operation
0
"P" Register : N, Z, C
q7/615141312111 r------«:il
RT I
Return from interrupt. The return address in stack is loaded into the program counter,
and it becomes the lead address of a next instruction of the interrupt.
Operation
Ms- P,
S+ 1 ~S
"P" Register: Restore
Ms~PCL, S+ 1 ~S
Ms~PCH, S+ 1 ~S
RTS
Return from subroutine.
The return address in stack is loaded into the program counter. It becomes the lead
address of a next instruction of the JSK
Operation
Ms~PCL, S+ 1 ~S
"P" Register
Not affected
Ms~PCH, S+ 1 ~S
S BC
Subtract memory and borrow from accumulator, and the result is stored into the
accumulator.
_
Operation
t~t1,;;.~w~ A
"P" Register
N, V, Z, C
SEC
Set carry flag.
Operation
"P" Register
C
Set decimal flag.
Operation
"P" Register
o
Set disable interrupt status.
Operation
1 --> I
"P" Register
SED
SE I
SMB
1
1
Set the specific bit of zero page address.
[ OP-Code
1
[Low Order Bit [Z-byte instruction
It sets the specific bit (a bit is decided on the instruction code) of effective address
00 1 Low Order Address I
Operation : 1 ~ Mb
"P'" Register
Not affected
S T A Store the contents of the accumulator into the memory.
Operation
A~M
"P" Register : Not affected
-----------------ICO@®DO5-19
ST X
Store the contents of the index register X into the memory.
Operation
X --> M
"P" Register: Not affected
STY
Store the contents of the index register Y into the memory.
"P" Register
Operation
Y --> M
Not affected
STZ
Clear the contents of memory.
0 --> M
Operation
Not affected
T AX
"P" Register
Transfer the contents of the accumulator to the index register X.
Operation
A --> M
"P" Register
N, Z
Transfer the contents of the accumulator to the index register Y.
Operation
A --> Y
"P" Register
N, Z
T RB
Reset the contents of memory by accumulator, and test at the same time.
Operation : A/\M --> M
"P" Register
If the result is zero, Z flag= 1
Z
T SB
Set the contents of memory by accumulator, and test at the same time.
Operation : A VM --> M
If the result is zero, Z flag = 1
"P" Register
Z
T SX
Transfer stack pointer to the index register X.
Operation
S --> X
"P" Register
N, Z
T XA
Transfer the contents of the index register X to the accumulator.
Operation : X --> A
"P" Register
N, Z
Transfer the contents of the index register X to stack pointer.
"P" Register
Operation : X --> S
Not affected
Transfer the contents of the index register Y to the accumulator.
'''P'' Register
Operation : Y --> A
N, Z
T AY
TXS
T YA
-ICO©®[}[J--------------5-20
.40-PiN DUAL-iN-LINE PACKAGE (UNiT: mm)
•
---------------ICO©®[}[]5-21
EKH-11-8807
REAL TIME CLOCK
RP/RF/R05C15
•
GENERAL DESCRIPTION
The 5C15 is a real-time clock for microcomputer that can be connected directly with the data bus of 16- bit
CPUs such as 8086, Z8000 and 68000 as well as 8-bit CPUs such as 8085, Z-80, 6809 and 6502, and is able to set up
and read a time in the same process with READ/WRITE of the memory.
It is provided with alarm function in addition to basic functions of time and calendar, and the battery backup
is possible.
•
FEATURES
• Direct connection with CPU, and high speed
access time .
• 4-bit bi-directiona1 data bus Do -'- D3
.4-bit address input Ao - A3
• Counters for Time (hour, minute, second) and
Calendar (leap year, year, month, date, day of the
week) are built in.
• All the clock data are expressed with BCD code.
•
• ± 30 second adjustment function is built in.
• Battery backup is possible. (min. 2.0V)
• 16kHz, 1kHz, 128Hz, 16Hz, 1Hz, 1/60Hz are
selectable as the reference clock.
• Alarm signal or timing pulse (l6Hz or 1Hz) can
be put out.
BLOCK DIAGRAM
16kHz, 1kHz, 128Hz, 16Hz, 1Hz, 1160Hz
lHz,16Hz
OSC OUT
CS
('5---<>.--'
I
RD
WR
SO
'IDDRESS
DECODER
SF
I
CLK OUT
BlS
CO\TROL
CLOCK
OUTPUT
f
Do 0\ O2 D,
--------------ICO®®DO6-3
RP JRF JR-.J5C 1 5
•
PIN CONFIGURATION
cs
Vee
CS
OSCOUT
CLKOUT
All
0
>n
c
;,;
OSCI:\
C;
18
Vcc
0
Z C 0
0 '"i >fl
ALARM
Co
17
OSCOUT
4
CLKOUT
16
OSCI:\
Ali
..,'"
Q
15
ALARM
14
D:l
0'
13
1)2
12
[J,
Ih
[J~
[J,
[J"
WR
RP5C15
•
Q
A,
A,
A:)
RD
11
[J"
(;N[J
III
IVR
3 2
CLKOUT
Ao-A3
RD
GND
WR
0 0 -0 3
ALARM
OSC IN, OSC OUT
Vee
9,
NC
21
D:l
NC
D2
Az
0iC
NC
12 13 14 15 16 17 18
~
91 tJ~
Function
6-4
7.
1 28 27 26
~
Terminals for external interfacing. Valid when CS=H, CS=L. CS is
connected to the power-down detector of peripheral power supply
circiut and CS is connected to the microcomputer.
Reference clock output terminal. Open drain output. 8 kinds of mode
are selectable as seen in the table, according to content of the clock
select register.
ADDRESS pin. Connected to ADDRESS bus of CPU.
I/O control input. L when CPU·- RP5C15.
oV
I/O control input. L when CPU~RP5C15.
Bidirectional data bus. Connected to the data bus of CPU.
Alarm signal and pulse (16Hz CK or IHzCK) are put out. Open drain
output.
Crystal resonator connecting terminal. 32.768kHz.
+5V power supply.
----ICD©®DO-
'"i
0
(fl
0
NC
ALAIVvI
RF5C15
Symbol
D,I~
0
NC
A"
NC
A,
C;C
PIN DESCRIPTION
CS, CS
0
"F ~ S:J
",0
RJ5C15
RP/RF /R..J5C 15
•
ABSOLUTE MAXIMUM RATING
Symbol
Vee
V,
Vo
P,
Topr
T sts
•
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature
Storage Temperature
Limits
Conditions
With respect to GND
Ta=25·C
-0.3-7
-0.3-7
-0.3-7
Unit
V
V
V
400
-20-70
- 40-125
mW
·C
·C
RECOMMENDED OPERATING CONDITIONS (Unless Noted: Ta=-20-70·C)
Symbol
Vee
V OH
fXT
•
Parameters
Supply Voltage
Input Voltage
Parameters
Supply Voltage
Data Hold Voltage
Crystal Oscillation Frequency
Specified Value
Typ
Max
Min
4.5
2.0
5
5.5
5.5
32.768
Unit
V
V
kHz
ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS (Unless Noted: Ta = - 20-70·C , Vee = 5 V ± 10%)
Symbol
V 1H
Parameters
Measuring Conditions
Specified Value
Typ
Max
Min
V 1HCS
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output-off Leakage Current
Standby Supply Current
Operating Supply Current
CS Pin Input "L" Voltage at Backup
CS Pin Input "H" Voltage at Backup
:NOTE Ii
RD.WR Signal Frequency: 100kHz. Input TermInal fixed Vee. or GND level. Output TermInal Open
VII.
V OH
VOl
L_I
loz
-Icc I
Icu
VILes
2.0
-0.3
1",,= -4001'A
10 ,. =2mA
V,=0-5.5V
Voz=0-5.5V
fXT =32. 768kHz, Vee =2.0V
fXT =32. 768kHz, V cc = 5. 5 (NOTE!)
Vcc=2.0V
V,,=2.0V
V"TO.3
0.8
2.4
-0.2
l.8
0.4
±10
±10
15
250
0.2
2.0
Unit
V
V
V
V
I'A
J1.A
J1.A
J1.A
V
V
• AC ELECTRICAL CHARACTERISTICS (Unless Noted: Ta = -20-70·C ,V cc = 5V ± 10%1
Symbol
t"
tcc
tc '\
t RLJ
tl-![)H
\
'I'
t WllS
tWllH
tn:ll
t ... O)
Measuring Conditions
Parameters
Address '-- RD/WR Delay Time
RD/WR Pulse Width
50
120
Address Valid Time After
RD/WR Rise
Data Delay Time After RD Fall
Data Hold Time After RD Rise
Data Setup Time at Write in
Data Hold Time at Write in
Alarm Write Inhibit Time after
Alarm set
t Rn
RD/WR Recovery Time
13,000
ITTL+ 100pF Load
Unit
ns
ns
ns
10
120
10
100
10
100
Timer Enable- Timer Disable
Adjust Completed Time
t ... 1\11
Specified Value
Typ
:'vlin
Max
100
ns
ns
ns
ns
I's
J1.s
100
J1.s
1
I's
---------------ICO®®[}[]6-5
I
RP /RF /RJ5C 1 5
•
TIMING DIAGRAM
• READ CYCLE
Val id
tee
Do-D3
Val id
• WRITE CYCLE
J r - - - - - - - - - - - - , L ,---11
CS, Ao -- A3
Val id
~------------------~ ~--~1
teA
tee
WR - - - - - " " ' 1 ""_ _ _ _ _ _ _
tWDS
~ !-~-----t-R-CV------1}~-tWDH
Do-D 3
-ICO©®OO-------------6-6
RP /RF /RJ5C 1 5
•
ADDRESS ASSIGNMENT
MODE
A,-Ao
BANK 0
03
0
1 Sec. Counter
1
10 Sec. Counter
2
1 Min. Counter
3
10 Mins. Counter
4
1 Hr. Counter
10 Hrs. Counter
x
6
X
7"
1 Day Counter
10 Days Counter
9
A
10 Months Counter
B
1 Year Counter
C
10 Years Counter
0
MODE
Register
TEST
Register
RESET
Register
E
Contents
CLKOUT
Select Register
Alarm
1 Min. Register
Alarm
10 Mins Register
Alarm
1 Hr. Register
Alarm
10 Hrs. Register
Alarm
Week Register
Alarm
1 Day Register
Alarm
10 Days Register
X
X
X
x
x
12/24 Hour
Selecter
Leap Year
x
BANK 1
0,
0,
Counter
0,
Do
x
x
adjust
X
x
x
X
x
X
X
x
x
X
x
x
x
X
x
x
x
x
Timer
EN
Alarm
EN
X
X
X
x
Timer
EN
Alarm
E1\
x
BANK
1/0
Test 3
Test 2
Test 1
Test 0
Test 3
Test 2
Test 1
BANK
110
Test 0
Timer
RESET
Alarm
RESET
1Hz
ON
16Hi
ON
Timer
RESET
Alarm
RESET
1Hz
16Hz
ON
01\
x : Don't care for W R, always 0 for RD.
F
Do
X
Week Counter
1 Month Counter
0,
X
5
8
O2
• CLOCK OUTPUT SELECT REGISTER
03
x
x
X
X
X
x
x
x
O2
0
0
0
0
1
1
1
1
0,
0
0
1
1
0
0
1
1
Do
0
1
0
1
0
1
0
1
CLK OUT
"Z"
16.384kHz
1. 024kHz
128 Hz
16 Hz
1 Hz
1/60 Hz
"L"
Remark
-High Impedance
duty 50%
duty 50%
duty 50%
duty 50%
.J Second Counter Count up, duty 50%
J Minute Counter Count up, duty 50%
• ADJUST FUNCTION
BANK 1
Address (A 3 , A 2 , A" Ao)=(O, 0, 0,1)
Data (0 3 , O2 , 0" Do)=(x, x, x, 1)
If adjusted during the Second counter being 0-29, the
Second comes to be 0, and if adjusted during 30 - 59, the
minute is counted up, and the Second comes to be O.
ICD®®OO6-7
I
RP/RF /R.J5C 15
•
OSCILLATION CIRCUIT
As the output stabilizer resistor (::::: 100kO) is built in, it is not necessary to fix it externally.
c, ~ 13pF Typ.
C" ~ 39pF Typ.
• MODE REGISTER (A 3 , A 2 , AJ, Ao)
D,
D,
Timer
Alarm
E1'
EN
D,
x
(1, 1,0, 1) = D
Do
BANK 0 : Setup and Read of time
BANK 1 : Setup and Read of Alarm, 12h/24h and Leap year, Selection of
CLK OUT Operation of Adjust.
I'---~~~~~~~~. 1: Alarrr: output ENABLE
o . Alarm output DISABLE (l6Hz and 1Hz signals are independent)
: Time count starts
: Time count after Second stops
x
•
LEAP YEAR COUNTER
Do = 1 : Resetting of all alarm registers
DI = 1 . Resetting of frequency divisions before
Second
0, = 0 : 16Hz CK pulse ON
D3=0: 1Hz CK pulse OK
Leap year when DI = D2 = 0. It counts up
simultaneously with Year Counter.
• T2Fi/24h SELECTOR
24 -hour counter when Do = I
12 -hour counter when Do = 0
PYI when DI = 1, and AM when DI = 0 respectively
of 10h counter
• RESET CONTROLLER 16 Hz· IHzCK REGISTER
(A,.A,.AI.Ao)c(I,1.1.11=F
• ADDRESS
0- D
Both READ and WRITE are possible.
.ADDRESS
E-F
WRITE only is possible.
• TEST REGISTER (A 3 , A" AI, A o )=(1, I, I, O,)=E
Register to be used for our inspection.
Normal count is operated by setting up data
(0 3 .0,. D I , 0 0 )=(0, 0, 0, 0).
*Please refer to "Application :\lanual" that we offer.
-ltO@®[J{]-------------6-8
RP/RF/RJ5C15
•
PACKAGE DIMENSION (Unit: mm/inch)
eRP5C15(18pin DIP)
I~
2'-" MAX
(.976 ::vtAX)
lK
PIN~l
eRF5C15(18pin FLAT)
11 .84 l'vIAX
.466 :'vIAX
I
10.:31 ±O :1
PI"K#1
.406 ±O.1J12
~:t~J
di'--_ _---'\k
.II.
29') TYI'
~
o
0
I
-------------------------
6-9
,056 TY I'
0 bb ",>2
.026 ±n.OOIl
--llD@®DO~
RP/RF IR.J5C 15
eRJ5C15( 24pm
. PLCC)
PIN NO.1
lZ . ..\5-!:O.l.l
. ,190
-:-0.00:,
---ICD©®DO
6-10
_IC_O©_®_[}[]__~I
No. 84-01 4-1-1984
Microelectronic Specification
RP5COl
REAL TIME ClOCK WITH RAM
•
•
GENERAL DESCRIPTION
PIN CONFIGURATION (Top view)
The RP5COI bus compatible real-time clock is
designed for use with most of the popular
microprocessors such as the 8085A, Z -80 and others.
Time setting and readout can be readily done in the
same manner as writing/readout in and from
IllCPlcry. This RTC device features: counters for
complete ·time·of-day clock alarm, a hundred year
calendar, also a 26 x 4- bit RAM providing battery
back cd up functions and applications as an
involatile I,
(I, I, 0, J)
D
I>
Tinll'r
EN
EN
Time setting and readout
Alarm, 12Hr/24I1r & Leap Year setting and readout
RAM Write & Readout. ,BLOCK.IO
RAM Write & Readout. BLOCK. I I
I : Alarm output ENABLE
0: Alarm output DISABLE (l611z and IlIz signals have no relation)
: Time count starts
o : Time count after Second stops
• LEAP YEAR Counter
Leap year when DJ =D2 = O. It counts up
simultaneously with Year Counter.
• T2n/24h Selector
• ADDRESS 0- D
Both READ and WRITE are possible.
.ADRESS E-F
WRITE only is possible.
24·- hour counter when Do = I
12-hour counter when Do = ()
I'M when DJ = I, and AM when DJ = () respectively
of 10h counter
• RESET Controller 16Hz· llIzCK Register
(A 3 , A" AI> Ao)=(I, I, I, I)=F
Do = I : Resetting of all alarm registers
DJ = I : Resetting of frequency divisions before
Second
D, =() : 16Hz CK pulse ON
I), =0: 1Hz CK pulse ON
--------------llD©®[]{]-6-15
•
•
TIMING DIAGRAM
• WRITE CYCLE (CS="H")
(:s
/
\
1-- 1 ,,--1
Ir
l(
I\-
,
fWD
-- I"t~
f£
r-~~
WI(
~
-.0
I"
l
I
READ CYCLE (CS = "H")
-1,.=:1
/
)(
~
_, HI1H
I",
L
.1
IW
}
tHIl
\-
=:j
1('(
•
APPLICATION NOTES
1. Oscillating Circuit
1- 1 When using a crystal oscillating element.
The oscillator circuit is shown in Figure I.
Externally connected parts consist of :a resistor,
capacitors and a trimmer capacitor. To adjust the
frequency, use the trimmer capacitor (The 16Hz or
I Hz signal output at the ALARM pin should be
used), for calibration.
When calibrating with the 16IIz signal:
The Address is (A 3 , A2 , Ai> Ao)=(l, 1, I, 1).
The Data is (1, n, 0, x).
When calibrating with the I Hz signal:
The Address is (A 3 , A2 , A" Ao)=(l, 1, I, 1)
The Data is (0, 1, 0, x).
GNU
C,
=0
111,,1: -:111,,1-'
RP5COI
C,=o:llll'l:
Cl" S6pF
I(
= lIIokfl
(The crystal employed is Nippon Dl'lTlpa f(ogyo l\1X:~XT{)r {'qui\'ait'1l1l
Fig. 1
~ICD®®OO---------------6-16
12 When using an external Clock
The external clock should be connected through the circuits shown in Fig.2(a), and (b).
should be left with no connection.
The OSCOUT pin
o SC-"Ic:.;NCJ\'~A.__
/
/
OSC OliT
CMOS (·1O!)6)
'"'' 0<"
TTl.( 74LS04)
RP5COl
RP5COl
Fig.2 (b) TTL INVERTER CONNECTION
Fig.2 (a) CMOS INVERTER CONNECTION
2. Input/Output, and Chip selection Pins.
2-1 Input/Output Pins
In order to stabilize the potential at the Input/Output Pins during 'battery backup' operation, and a pull
-down resistor (lOO-300kO), and a pull up resistor (4.7 -47kO)
1--...-_ _ TO TilE POWER SUPPLY CIRCUIT
TO TilE POWERIJOWN
SENSING CIRCUIT
Hu
Hu
Hu
}{,,=IOOkO-:lOOk!l
H,.=4.7k!l-47k!l
Hu
----.-1
xx
II{\)
Hu
R"
Fig. 3
2-2 Chip selection Pins
There are two chip selection Pins. The C5 pin should be connected to the powerdown sensing circuit, and
the CS pin to the CPU. CS is active "II", whereas CS is active "L".
--------------IIU©®[}[]6-17
I
3. Interfacing with typical CPU
3·1 Applicable CPU
CPU
Z-8OA
(NOTE]) Not needed when the X'tal used is below
5Mllz
External Circuit
Nil
74LS74 (NOTE 1)
74LSOO, 74LS04
8085A
6800
3-2 Standard Interfacing examples.
Examples of Interfacing the RTC with typical
CPU (Z80,8085,6800) are presented hereunder.
(I) 280
The Data Bus, Address Bus, and RD, WR pins
are connected to the corresponding pins of the 2-80
(the same symbols are used). The CS pin of the
Rl'5COI should connect with the IOI{Q pin, or one
Bit of the Address Bus (e.g.Ao).
~D~
7.
b
:..:>
uuo
RP5COl
(fJ(fJ
00
---
DnD, DID). AnA, AIAl RO WR CS
--.--
'---v--'
'-':Vl
(/)(fJ
b:::J
.-,:cn
gjOJ
r.n~
0
I~I~I~
Q
Q
.-,:
Z·80
Fig. 4 CONNECTION DIAGRAM WITH Z-80
TIMING CHART
T.
CLOCK
----'
'1',
~~
'1';
Tw
rL r--u ~ r-
'-
l80
RP5COl
Z 80
Ao-" A7
lX
- D<
lOIU,
1\
J
Hil
1\
J
}
O~)'rpUT\
ilo-I);
WI(
T.
\.:.~
1\
}
RP5COl
ilo-il;
REA\)
CYCLE
INPUT
WRITE
CYCLE
l/
-IID®®OO-------------6-18
8085
The Data Bus, Address Bus, and RD, WR pins of
the RTC correspond with those of the 8085 (the
same symbols are used). The CS pin of the
R(,5COI should connect with one Bit of the 808"
Address Bus (e.g. pin Ao).
When the crystal oscillator used has a frequency of
6MIIz, a 74LS74 (externally connected circuit shown
in the dotted line) should be added to provide I
Wait.
(2)
Connection Diagram
~D
OSC,~
OSC,,!
I
RP5COl
DoD,DzJh
r-----------,
I
I
I
IJ,H.~
Bl'S
L __________ _
Fig. 5
CONNECTION EXAMPLE WITH 8085
Timing Chart
'1',
Cl.OCK
8085
{
A,-A,;
IlEAl)
'1',
I
Tw
'1',
'1',
- U-U-~U-I'---
- ):X
-
1\
1f
HEAIJ
IOlrrl'lJT1
CYCl.E
\.:~
8085
WlllTE
\
/
}
WHITE
CI'Cl.E
INl'liT
8085
HEAIlY
L..J
--------------ICO©®[JO6-19
I
connected to the ,ph and R/W pins of the 6S00, but
with the addition of the following: two 74LS04
inverters, two input NANDs and two 74LSOO.
Besides, the CS pin of the RTC should be connected
to one Bit of the 6800 Address Bus (e.g.Ao).
(3) 6800
The pin connections for the RTC are compatible
with the Data Bus, Address Bus of the 6800. (The
symbols are the same).
The 1<0, W1<, pins of the Rl'5COI should be
Connection Diagram
Timing Chart
o
6800
RP5COI
[
r
T'
J
I{/W
=><______>C
ADD
J
x=
1(1)
'lREi\1J
CYCLE
----------------~~O~lJ~Tl>l'UU~T
1J . \TiI flllS AlJlJHESS ¢, l\/W
BliS
RP5COI
WI(
r-1WRITE
6800
---------~(=======)._
Fig. 6
INl'UT
CYCLE
.
3-3 Interrupt into the CPU
The Data of
Rl'5COl is read-out by using
Interrupt to the CPU at the rate of once every
second.
(II
(2)
80SS
RP5COI
--ALAI(M
;:SO
jlllZ
RP5COI
I(ST7.:'
--AI.AI(M
8085
11112
(:;)
6800
NMI
Z·80
RP5COI
AI.AllM
/IIiZ
.------.1--,
Si(;Ni\L
NMI
6800
-ItO®®OlJ----------------6-20
4. Example of a program for setting Time/Alarm
4-1
Flowchart for the time setting operation
By setting Data (0 3 , D" 0 ,• Do) in the test register
(Address (A" A,. A" Ao)= (I, 1, 1, 0», operation of
the c,lock is maintained.
(1)
Timer Setting Program
For Time setting, the Timer is stopped, and
readout and write in should be executed within one
second,
(2)
Time Readout Program
TIMEI{ IS STOPPED
TIMEI{ IS STOPPED
MOllE I{E(;JSTER SETTIN(;
MODE RE<;JSTER SETTIN(;
111.,1),. 11,,11 11 )=10, x,O,OI
(1I"Il"Il"il ll )=IO,x,O,OI
FREQ, DIVlIIER IS I{ESET
RESET CONTIWL I IJo)=(x. x.I.O)
18 PIN PLASTIC PACKAGE (UNIT: mm)
11K
22.K6max
10
I
CJJJ
1
\I
---------------ICO@®OO6-23
I
_IC_D©_®_DO_~I
REAL TIME CLOCK
RPSC62/RFSC62
• OUTLINE
RP5C62/RF5C62 can be connected directly to SOS6, 6S000, and other CPU data buses. RP5C62/
RF5C62 are CMOS realtime clock LSIs with time, calendar, and alarm functions for microcomputer.
The built-in timer counter allows the clocks to be used as watchdog timers or interrupt timers.
• FEATURES
• RP5C62/RF5C62 can be connected directly to the CPU, and have high-speed access.
• Four-bit bi-directional data bus and four-bit address bus
• The oscillation circuit is driven by rated voltage, giving excellent oscillation frequency stability for
power supply voltage fluctuation (within ± I ppm)
•
•
•
•
Built-in timer clock
Regular period interrupts and alarm match interrupts to the CPU
Interrupt flag and interrupt inhibit
Time (hour, minute, and second), calendar (leap year, ordinary year, month, day, and day of week),
and alarm (hour and minute) functions.
•
•
•
•
•
•
Choice of 12-hour or 24-hour time
Automatic recognition of leap year
All watch and alarm data expressed in BCD code
±30 second adjustment
Automatic discrimination between valid and invalid clock data
CMOS gives low power consumption, allowing battery backup
• Single 5V power supply
• IS-pin DIP (RP5C62) or IS-pin SOP (RF5C62) packaging
• BLOCK DIAGRAM
OSCIN
OSCOUT
•
CE
cs
IVR
-~=t.J---""""14
LVDD
,r-vss
1~1
1)1 1)"1 I)'
---------------ICD@®o{]6-25
RPSC62/RFSC62
• PIN CONFIGURATION
18 PIN DIP & SOP
CS
CE
VDD
OSCOUT
OSCIN
TMOUT
AO
Al
INTR
D3
A2
D2
A3
D1
RD
DO
VSS
WR
TOP VIEW
• PIN DESCRIPTION
Symbol
Name
Function
CS
CE
Chip select
Chip enable input
CS and CE are used when interfacing external devices. They may be accessed
when CS is low and CE is high. CE is connected to a power down detector on
the system power supply side, and CS is connected to the microcomputer ad·
ress bus.
TMOUT
Timer output
Timer output may be used as an interrupt free·run timer or watchdog timer.
When CE is low (running on battery backup), operation stops (th~re is no out·
put). It is N-ch open drain output.
AO-A3
Address input
Address input is connected to the CPU address bus. It is gated internally with
CEo
RD
Read control input
When RD is set low, the contents of the counters or registers specified by A 0A 3 are output to DO - D 3. It is valid when CS is low and CE is high. It is
CMOS input.
WR
Write con tro! input
When WR is low or rises from low to high, the contents of DO - D 3 are written to registers or counters specified by A 0 - A 3. WR is valid when CS is low
and CE is high. It is CMOS input.
DO-D3
Bi-directional data
bus
DO - D 3 are connected to the CPU data bus. The input section is gated internaJIy with CEo It is CMOS input/output.
INTR
Interrupt output
INTR outputs regular alarm interrupts or alarm match interrupts to CPU. It
also operates when CE is low (at battery backup). It is N-ch open drain output.
OSCIN
OSCOUT
Oscillator circuit
input/output
Crystal oscillator of 32.768 KHz must be connected between OSCIN and
OSCOUT. Capacitance is connected externally between VDD and OSCIN and
VDD and OSCOUT, forming the oscillator circuit.
VDD
VSS
Power supply
VDD connects to +5V and VSS to ground.
-ICO©®[}{]-------------6-26
RP5C62/RF5C62
• ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
PD
TA
TSTG
Parameter
Condition
Supply Voltage
Input Voltage
Output Voltage
Maximum Power Consumption
Operating Temperature
Storage Temperature
VSS=O
TA = 25°C
-0.3 -OJ -0.3 300
-20 -40 -
• RECOMMENDED OPERATING CONDITION
Symbol
VDD
VCLK
fXT
Value
Unit
+7.0
VDD+OJ
VDD+OJ
V
V
V
mW
°c
°c
+70
+125
IVSS=OV. TA=-20 - +70°C)
Parameter
Condition
Supply Voltage
Supply Voltage of Clock
Crystal Oscillation Frequency
MIN.
Typ.
MAX.
Unit
4.0
2.0
5.0
6.0
6.0
V
V
kHz
MAX.
Unit
VDD+OJ
0.8
VDD+O.3
O.2*VDD
0.4
0.4
V
V
V
V
V
V
V
32.768
• DC CHARACTERISTICS
Symbol
Parameter
Pin Name
VIHl
VILl
VIH2
VIL2
VOHl
VOLl
VOL2
"H" input voltage
"L" input voltage
"H" input voltage
"L" input voltage
"H" output voltage
"L" output voltage
"L" output voltage
AO-A3, DO-D3
I1I:K
Input leak current
IOZ1
Output offleak
~ current
IDDI
IDD2
af
Consumption
current for
back.up
Consumption
current for
stand-by
Oscillation frequency drift for
voltage drift
Condition
CS,RD, WR
CE
DO-D3
INTR, TMOUT
AO-A3,CE,
CS,RD, WR
DD-D3
INTR, TMOUT
IOHl = -400/LA
lOll =2mA
IOL2= 2mA
MIN.
2.0
-OJ
O.8*VDD
-0.3
2.4
Typ.
VILK = VDD or VSS
-I
1
/LA
VOZI = VDD or VSS
VOZ2= VDD
-5
-2
5
2
/LA
/J.A
VDD
VDD=2.5V
Input:
VDDorVSS
3
/LA
VDD
VDD=5.5V
Output:
OPEN
8
/J.A
1
PPM
OSCIN
OSCOUT
VDD=2.5-5.5V
-I
( Unless Noted, VSS=OV, VDD=5V±IO%, TA=-20 - +70°C,)
X'tal=32.768KHz(CI~ 35Kn), CG=CD=33pF
--------------ltO@®DO-6-27
RP5C62/RF5C62
• AC CHARACTERISTICS
(vss=OV VDD=5V± 10% TA=-20-+70°C)
Symbol
Parameter
tCES
CE setup time
tCEH
CE hold time
Address setup
time (RD)
CS setup time
(RD)
RD setup time
(RD)
Data hold time
(RD)
CS output delay
time (RD)
RD output delay
time (RD)
CS setup time
(WR)
WR setup time
(WR)
CS pulse width
(WR)
WR pulse width
(WR)
Data setup time
(WR)
Address CS hold
time (WR)
Address WR hold
time (WR)
Data hold time
(WR)
tAA
tCS
tRD
tOH
tCSZ
tRDZ
tACS
tAWR
tWCS
tWR
tWDS
tCSH
tWH
tWDH
Description
Time that CE must be held high before the address is
established
Time that CE must be held high until the address changes
Time when the address must be established before CSRD =low
Time taken from when CS becomes low to when data is out·
put when RD is low after the address is established
Time taken from when RD becomes low to when data is out·
put when CS is low after the address is established
Time when dat~oes not change even though the address
changes when CS = RD = L
Time taken for the data bus line to become hig-h- impedance
after CS becomes high
Time taken for the data bus line to become high impedance
after RD becomes high
Time when the address must be established before CS
becomes
low when WR is low
-Time when the address must be established before WR
becomes low when CS is low
Pulse width at write by CS when WR is low
Pulse width at write by WR when CS is low
Time that data must be established before CS or RD
becomes high
Time that the address must be held after CS becomes high
Time that the address must be held after WR becomes high
Time that data must be held after CS or WR becomes high
• TIMING DIAGRAM
CE
CS
Read Cycle
AO-A3
RD
DO-D3
CE
CS
Write Cycle
AO-A3
WR
DO-D3
-ICO©®OO
6-28
Value
MIN
200
MIN 200
MIN
50
MAX
120
MAX
120
MIN
10
MAX
70
MAX
70
MIN
50
MIN
50
MIN
120
MIN
120
MIN
60
MIN
10
MIN
10
MIN
10
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
RP5C62/RF5C62
• PACKA GE DIMENSIONS (Unit: mm)
1) RP5C62
2) RF5C62
1.05 '/11,095
I
~~
r-'-:c==-------.+
=
to:
~~tr
rnl
WJ
~~
•
--6-29
IID®®[]{]-
No. EKH-9-871 1
aUAD.UART
RFSCS9
• GENERAL DESCRIPTION
RF5C59 is the CMOS LSI with 4 channels of serial port built-in for application to asynchronous
communication. The operations including transfer rate, transmit/receive of communication and etc.
can be specified by program independentiy for each channel and it allows the use as peripheral circuit
of CPU.
• FEATURES
• Double-buffer mode transmitter/receiver
• Dual transmit/receive of communication is practicable for all 4 channels.
• Setting of transfer rate at each channel for both hardware and software is practicable.
When input clock is 14.7456 MHz, the following rates are applicable.
614.4 KHz, 307.2 KHz, 153.6 KHz, 76.8 KHz, 38.4 KHz, 19.2 KHz, 9.6 KHz and 4.8 KHz.
• Freedom of combination of logical address with physical address for 4 channels.
• Data length 8 bit, stop bit 1 bit fixed.
• Overrun and framing error are detectable.
• Error start bit is detectable.
• Direct connection to 8 bit bidirectional data bus and data bus is practicable.
•
•
•
•
•
4 bit address input.
Hardware interrupt signal of TXRDY and RXRDY that can be masked.
Connection to high speed CPU is practicable.
5V single voltage supply.
60 pin flat package.
• PIN CONFIGURATION
:;;
TXRDY
RXRDY
WR
~
55
"
35
TiD
CLK
GND
30
60
TEST
Yeo
RXCA
RXCB
RXCC
RXCD
Yeo
TX21
TXCA
TXCB
A2
Al
AO
c/o
25
cs
TXCC
TXCD
---------------ICO@®OO-6-30
RF5C59
• BLOCK DIAGRAM
DO- D 7
AO- A 2
C/O
CS
Rii
ViR
elK
RESET
T T
R R
X X
X X
D CDC
T T
R R
X X
X X
D CDC
A A
B B
A A
T
B B
T
R R
X X
X X
T T
X X
D CDC
C C
C C
D D
R R
X X
D CDC
D D
• DESCRIPTION OF FUNCTION
RFSCS9, which is the UART for data communication, is used as peripheral circuit of CPU, and
operation under serial data transfer mode can be specified with program.
RFSCS9 has the transmit/receive ports with 4 channels, which receive parallel data from CPU,
convert them into serial data and feed them out from TXD * terminal. In addition, RFSC59 receives
data fed to RDX * terminal and feed them to CPU.
All 4 channels are controllable independently. Reading of status register I will not only make it
possible to find the condition of transmit/receive operation but also allow to notify CPU of hardware
interrupt signal from TXRDY terminal and RXRDY terminal.
The combination of logical port with physical port can be freely set with instruction register 3.
In other words, logical ports in plural number can be assigned to one physical port. The transfer
rate is 1/(24 *n) of input clock. (n: 1,2,4,8,16,32,64,128)
-ICO®®[]]-------------6-31
RF5C59
• PIN DESCRIPTION
-PIN No.
6,7,8,9
Symbol
DO
10.11
12, 13
-
I/O
I
Function
Bidirectional 3 state data bus used for transfer of command, data and status be-
tween RFSC59 and CPU.
TTL compatible input.
D7
I
Reset input. Active LOW. During reset,
• All internal registers turn to reset or default value.
• Transmit outputs TXDA and TXno turn to mark (HIGH) condition.
• All transmit/receive ports are enabled.
• TXRDY and RXRDY lines turn to active.
(CMOS compatible Schumit input)
CS
[
Chip select input. Active LOW. When CS is at LOW level, it ailows data transfer
with CPU. TTL compatible.
WR
I
WR input. When WR is LOW-;~nd
in this LSI. TTL compatible.
RD input. When RD is LOW and CS is LOW, the content of internal register of
36
RESET
5
57
-cs is
LOW, the data on 00- D7 are written
~---
58
RD
I
4
C/D
I
C/D represents the input which informs whether the data on the bus is control
information or status information. TTL compatible.
1,2,3
A2,Al
AO
RXRDY
I
Address inpu t. TTL compatible.
56
0
Interrupt signal to CPU which informs the receipt of data. If the data exist in
anyone of the receive ports being unmasked by RIM * flag of instruction register
1, it turns to LOW. When the data are read from all unmasked receive ports and
each receive buffer has the space, it turns to HIGH. When RIM * flags are all
turned to 1, it also turns to HIGH. Meanwhile, aparting fro..!!Lthis signal, CPU is
also able to confirm the existence of receive data by reading RXRDY bit of status
register.
59
20
21
22
23
CLK
TXDA
TXDB
TXDC
TXDD
I
System clock input. CMOS compatible.
0
0
0
0
Transmit receive section of channel A - D serial data output. Following the start
bit, it is output from LSB and after MSB, 1 bit of stop bits is added. During
disable of port or during idle, it holds the "MARK" condition. With 'Mark' at
HIGH level and 'Space' at LOW level, it performs Enable/Disable of coordinate
ports with bit 7 and bit 3 of instruction register 4 and 5.
15
16
17
18
29
34, 37
RXDA
RXDB
RXDC
RXDD
Vee
Vee
I
I
I
Receive section of channel A - D serial data input. Receive from LSB. 'Mark'is
HIGH and 'Space' is LOW. It performs Enable/Disable of coordinate ports with
bit 7 and bit 3 of instruction register 4 and S.
specified address is read on DO-D7.
TTL compatible.
----
[
+5V power supply. Make sure 29 Pin is connected with power supply.
14
19,60
GND
GND
55
TXRDY
0
28
TX 24
D1VAEN
DVRA2
DVRAI
DVRAO
DIVBEN
DVRB2
DVRBI
DVRBO
DIVCEN
DVRC2
DVRCI
DVRCO
D1VDEN
DVRD2
DVRDI
DVRDO
0
1/24 frequency division output of CLK input.
I
Preset input by hardware of transfer rate. When DIV*EN is LOW, transfer rate
1
register 4 and 5. All pull·up Schumit input. When CLK input is 14.7454 MHz,
the transmit rates are:
Frequency
division ratio
DVR*2
DVR*1
DVR*O
Transmit rate
(vs. CLK/24)
614.4 KHz
L
L
L
1
L
L
307.2
H
1/2
153.6
L
H
L
1/4
76.8
H
L
H
1/8
H
L
L
38.4
1/16
H
L
H
19.2
1/32
9.6
H
H
L
1/64
H
H
4.8
H
1/128
54
53
52
51
50
49
48
47
45
44
43
42
41
40
39
38
27
26
25
24
I
I
I
I
I
I
I
I
I
I
I
TXCA
TXCB
TXCC
TXCD
I
I
I
I
0
0
0
0
33
32
31
30
RXCA
RXCB
RXCC
RXCD
0
0
0
0
35
TEST
I
.
Interrupt signal to CPU which informs that the data are transmissible. If anyone
of the transmit ports unmasked by TIM * flag of instruction register 1 is in trans·
missible condition, LOW output. (NOR output of TXRDY flag of each port)
When TXRDY flags of all ports are masked, it turns to HIGH. Meanwhile, aparting from this signal, CPU is also able to confirm the condition of transmit register
buffer by reading TXRDY* flag of status register 1.
~h~~0~~iv~~J?:t~~3~~i~r~~~~/~~t~t i~~~~:~i~:; ~: R~~:t~' ~rYtfe~ i~~~sfr~~i*OO~
Transfer clock output during transmit of each port. Transmit data are output in
synchronizing with the rise of this clock.
Transfer clock output during receive of each port.
taken in synchronizing with the rise of start bit.
Frame synchronization is
1/24 frequency division circuit of CLK is
bypassed under the test mode . Normally, it is kept LOW.
It turns to test mode at HIGH active.
- -
---------------ICO@®[J{]6-32
I
RF5C59
.DC CHARACTERISTICS (Ta= 0 -70°C, Vcc= 5 V±10%)
--
• AC ELECTRICAL CHARACTERISTICS
- SY~:-l
~----r
f--MrnTTYP.-TMA~kni't
-para~eter
Test
Condition .
+- -- ---- ---..--------.--
-
---
WR data~etup .tlme_______ ....
45
I
-t-
WR after rise ~ address hold time
200
60
I
TWDH
!
WR data hold time
f-------+----....:.:::...----------··--·- I
~2:'~-+. WR before rise ~ address set~_ time ----
L
X.
----
~-
-T~-;-- I --w=R;~lse Wl~-----------
f __!WDS
Value
MIN
50
80
-r-.
ns I
tI
I
i
ns]
n~
--- - - -
----r----I
-r--
ns
ns
+- :::~------1 ~: :::e:r:~:-:-~d:~j:-:-se-~:-~d-t~-~-e:----~-r
-r--RD-P-~h;
-----+--2-0-0-+--i~s
TWA
i
0
0
-TR-R-
t
width
r----
I
::
I
::
--+1
--·----·-·-1-·-----=------------------·--
-
--::::A:R -.- ·--:~~;~~t~2--------·--------T-r-I~~=IO-~F
10
~5
RD before rise ~ address setup time
50
ns
RD after rise ~ address hold time
80
ns
I
._----_._-_._---_._----_.- --+-----+----+-----j------+----I
.. _ - - - - - - - - - - - - _ .... _ - - ' - - - - - - - - ' - - -
-ICD©®OO-----------6-33
RF5C59
• TIME CHART
A2, AI,
>
AO, C/D
IE- TCSA-i>
~TACS 7
CS
~
><
V
~TAR
__
RD
~
TR A
TRR
------;;.
/
"
~TDH~
oE__TRD----?>
/'
DO -D7
--r'"
VALID
'-.,.
"~~:-----------t-'->f,-",J,.,"~-----~
TAW
Tww
-------;;.
_o
• EXAMPLE OF APPLICATION
TXDA
Personal
r -------------------1
I
I
I
I
I
I
TXRDY
I
RXRDY
--.L
I
I
Host
QUAD
Address
control
CPU
UART
-V
Data bus
j
RF5C 59
TXDB
[
Printer
RXDB
I
I
I
I
I
TXDC
I
\
I
r
I
I
~I
L
computer
I
I
I
I
RXDA
I
Modem
Telephone line
TXDD
I
Control device
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -1
RXDD
Host machine
~
RXDC
(D&A)
fE-- Sensor signal
Peripheral devices
-----ICO©®OO6-34
•
RF5C59
• REGISTER MAP
b7
r"""
Instr
I
b6
b5
b4
b3
b2
bl
bO
RIMA
RIMB
RIMC
RIMD
TIMA
TIMB
TIMC
TIMD
L. P. A
L. P. B
L. P" C
L. P. D
L. P. A
L. P. B
L. P. C
L. P. D
ERSTB
ERSTC
ERSTD
'---
----
o : non
I : mask
t-iNIRER-~
ERSTA
o : NOP
linstr. 2
------------
---------
LPBbl
LPBbO
I : Ini tial Reset
I
mask
~~~_LLPAbO
--
o : NOP
I : Error Flag Reset
LPCbl
LPCbO
LPDbl
LPDbO
BDIVI
BDIVO
11 : physical port A
instr. 3
10 : physical port B
01 : physical port C
r------~
instr. 4
00 : physical port D
~NLPA-'-- ADIV 2-T~ADIV IDI:liVO
L. P. A
----
-~-------
o : DIS
ENLPC
instr. 5
RXRDYA
L. P. A
stat. I
CDIVO
ENLPD
DDIV2
DDIVI
RXRDYB
RXRDYC
RXRDYD
TXRDYA
L. P. B
L. P. C
L. P. D
L. P. A
DDIVO
note I
I : ENA
--
TXRDYB
--'-
L. P. B
o : transmit
0 : no recei ve data
TXRDYC
TXRDXD
L. P. C
L. P. D
busy
I : transmit ready
I : recei ve data in buffer
:----
note I
o : DIS
note I
I : ENA
--f---
physical port B
I : ENA
CDIV2 ICDIVI
o : DIS
BDIV2
o : DIS
note I
I : ENA
ENLPB
L. P. B
physical port A
FREA
FREB
FREC
FRED
OVEA
OVEB
OVED
OVEE
L. P. A
L. P. B
L. P. C
L. P. D
L. P. A
L. P. B
L. P. C
L. P. D
stat. 2 f---
0
0 : no error
no error
1 : framing error
*:
I : over run error
*
L. P.
Logical Port
note 1 : 000 : 1/1, 001: 1/2, 010: 1/4, 011: 1/8, 100: 1/16, 101: 1/32, 110: 1/64, lll: 1/128
• ADDRESS ASSIGNMENT OF REGISTER
C/D
A 2
A I
A 0
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
I---- H
L
L
L
instruction register I
instruction register I
L
L
H
instruction register 2
instruction register 2
L
H
L
instruction register 3
instruction register 3
H
H
H
H
L
H
H
instruction register 4
instruction register 4
H
H
H
L
L
instruction register 5
instruction register 5
-
1 - - - - -I---
II
L
---
wri te register
read regi ster
TXDA (Logical port)
RXDA (Logical port)
H
TXDB (Logical port)
RXDB (Logical port)
L
TXDC (Logical port)
RXDC (Logical port)
TXDD (Logical port)
RXDD (Logical port)
H
--
r----
-
L
H
status register I
H
L
status regi ster 2
I
-ICO®®DO-----------6-35
RFSCS9
• PACKAGE DIMENSIONS (60 pin FLAT)
24.8 ±O.4
(.976±0",')
20.0 TYP
(. 787 TYP )
"~o "~
. '"
~
::::
'"
~
..
.~
0
o
00
0
~ ~
~
•
.'" .'"
g
" "~00
1. 2 ±o 2
~
'"
.,;
(.047 ±OOO')
0
0
--'
~--
::::
~
'" ...:-
. - -------·---IIO®®OO6-36
ICD©®OO
I
!l ! ! ! ! R!I ! ! ! ! F!I ! ! ! ! 5!1 ! ! ! ! C!l ! ! ! ! 16!1 ! ! ! ! A!I ! ! ! ! /!I ! ! ! ! R!I ! ! ! ! P!l ! ! ! ! 5!1 ! ! ! ! C!l ! ! ! ! 16~
EKH-2
CRT CONTROLLER
• Pin configuration
• General description
RP5C16/RF5C16A are LSI developed under
CMOS process technology for application to
CRT controller. They allow to display the various
patterns on the CRT by control commands and
image data fed from 8 bit CPU including 8085,
Z80, etc. With use of this 5C16, CRT controller
system can be configurated by merely connecting
DRAM.
RF5C16A
L/d
M-LEVEL
WEM
WEL
VD,
VD,
VD,o
VD'I
VO,.
VO"
VOl.
VD"
VD,
VD,
VD,
VD,
VD,
VD,
VD,
VD,
VA,
R
G
!L
Note)
RD
RF5C16Ais the 64 pin FLAT packaged product
RP5C16 is the 64 pin DIL packaged product.
W"
e;;
DACK
DREQ
A,
A,
A,
A,
lNT
VBUS REQ
D,
• Features
D,
D,
• 4 modes
-Color picture with 80 X 25 characters
· Color picture with 640 X 200 dots
· 2 color pictures with 40 X 25 characters and
40 X 25 characters
· 2 color pictures with 320 X 200 dots and
40 X 25 characters
• Display of maximum 15 colors with RGB output (2 values or 3 values)
• Virtual screen
• Smooth scroll to horizontal and vertical directions are practicable.
• Abundant attribute function (transverse invert,
longitudinal invert, vertical invert and black
white invert)
• Cursor built-in (for mouse)
• Master/Slave mode (Superimpose practicable)
• Redefinable character set
• Buffer register and address counter built-in for
updating of V-RAM (Video RAM)
• Low power consumption for the sake of CMOS
process
• 60 Hz non-interlace display
RP5C16
NC
VBUS EN
CLOCK OUT
CLOCK
IN
C-SYNC
H-SYNC
V-SYNC
L/d
M-LEVEL
R
G
B
RD
WR
e;;
DACK
DREQ
A,
A,
A,
N,
lNT
li------_.- :i
41
:I
7
Vee
~~
158
:
II:
~:
I ;;
15
16
17
18
19
20
sO
49
48
47
46
45
10
11
12
55
54
53
CAS,
XCLK
WEM
WEL
VD,
VD,
YO'O
VO'I
VD,~
VD ,3
VD,.
VD,.
VD,
VD,
VD,
VD,
VO,
VBUS REQ
0,
0,
0,
0,
0,
0,
0,
D.
61
GND
RAS
CAS
CASo
25
26
111
27
28
29
_ill
40
39
38
37
36
30
35
31
32
34
33
VD,
VD,
VD,
VA,
VA,
VA,
VA,
VA,
VA,
VA,
VA,
---------------IID©®OO6-37
I
• Block diagram
VBUS REQ
EN
r-------------------~V~B~US
=======j:~::l=======================~==~========~~:t=====WEN
-------1 RD/WR
WEL
control
logic
[NT
Do - D,
¢:==========~
L/d
R
G
B
M-LEVEL
~:: ~~~~
V- SYNC
RAS
CAS
• Pin description
(1)
CPU interface
Name
Symbol
IN
RD
Read Strobe
IN
WR
Write Strobe
IN
Address 0 ~ Address 3
IN
Ao~A3
Do~D7
INT
(2)
input/output
Chip Select
CS
Data
O~
Data 7
Interrupt
DREQ
DMk Request
DACK
DMA Acknowledge
Logic
Active
L
L
Function
Make it possible to Read and Write of control
register address register and buffer register
L
(positive) Selective line of control register
IN/OUT (positive) Data bus
Active
OUT
H
OUT
L
IN
L
input/output
Data 0
= LSB
Data 7 = MSB
V-RAM interface
Symbol
RAS
ROW Address Strobe
OUT
CAS
Column Address Strobe
OUT
Logic
Active
L
L
CAS o
Column Address Strobe 0
OUT
L
CASl
Column Address Strobe I
OUT
L
IN
H
VIDEO BUS REQUEST
OUT
H
WEM
Write Enable MSB
OUT
L
Set Column Address, Provide Timing
CAS which turns to active only when address is
O~3 FFFH.
CAS which turns to active only when active is
4000H~ FFFH.
When L it turns CAS", "CASQ, CASl ""RAS",
WEL WEM VAo_7 and VDO_l5 to ll:i-Z.
5C16 accesses VBUS, it turns to active betore
4 clock.
Write is early write operation
WEL
Write Enable LSB
Video Memory
Address O~ 7
Video Memory
Data O~15
OUT
L
Write is early write operation
OUT
(positive)
VBUS EN
VBUS REQ
VAo~VA7
VDo~VDl5
Name
VIDEO BUS ENABLE
Function
Set Row Address, Provide Timing
0 - LSB
IN/OUT (positive) Data
Data 15 = MSB
-ICO©®OO
6-38
RF5C16A/RP5C16
(3)
Clock and Video output
Symbol
CLOCK IN
CLOCK OUT
M-LEVEL
Name
Clock In
Clock Out
Middle Level
Vee, GND
Vee, GND
Red, Green, Blue
Light and dark
Composite Synchronous
~l( G, B
Ld
C-SYNC
V-SYNC
Vertical Synchronous
H-SYNC
Horizontal Synchronous
Yo CLK
Yo CLOCK
input/output
Logic
IN
-
Function
14.31818 MHz which connects quartz crystal.
When RGB3 value output, it provides CRTC
with intermediate level
-
OUT
(positive) Video output (2 values or 3 values)
uutl?ut (open dram outpu9 when master mode
OUT/IN (negative) and
mput H-SYNC when slave mode
Output
(open drain outpupwliim master mode
OUT/IN (negative) and input
V-SYNC when slave mode
(open drain output) when master mode
OUT/IN negative) Outl?ut
and mput H-SYNC when slave mode
OUT
Clock Yo frequency division output
• Absolute maximum rating
Symbol
Parameter
Vee
VI
Vo
Pd
Ta
.Tstg
Supply voltage
Input voltage
Output voltage
Maximum power consumption
Operating ambient temperature
Storage temperature
Condition
Value
Unit
-0.3 - +7.0
-0.3 - +7.0
-0.3 - +7.0
300
-10-70
-40- 125
V
V
V
mW
°c
°c
Value
Unit
4.5 - 5.5
0
2.0 - Vee + 0.3
-0.3 - 0.8
-10 - 70
V
V
V
V
°c
Ta = 25°C
• Recommended operating condition
Symbol
Vcc
Vss
VIH
VIL
Ta
Parameter
Condition
Supply voltage
Supply voltage
"H" input voltage
"L" input volta~e
Ambient temperature
• DC electrical characteristics (Vee = S.OV ± 10%, Ta = -\0 ~ 70°C)
Symbol
VIH
VIL
VOH
VOL
ILl
ILO
Icc
VIN
ViI4>
f--------
I-
Value
Parameter
Condition
"H" input voltage
"L" input voltage
"H" output voltage
"L" output voltage
Input leakage current
3-state floating current
Supply current
Clock input "H" input voltage
Clock input "L" input voltage
IOH = -400J.l.A
IOL = 3.2mA
0';; VI';; Vee
0.4 ,;; VI';; 2.4
Min.
2.0
-0.3
2.4
Typ.
Unit
Max.
Vee + 0.3
0.8
0.4
10
10
50
0.7 x Vee
0.3 x Vee
--~ICO®®oa
6-39
V
V
V
V
J.l.A
J.l.A
rnA
V
V
•
RF5C 16A/RP5C 16
• AC characteristics (Vee = S.OV ± 10%, Ta = -1O~70°C). and Timing diagram
(1)
(Unit: ns)
CPU-5C16 READ/WRITE
No. Symbol
I
2
3
4
5
6
7
8
9
10
11
12
13
14
taee
tder
twrh
ther
tddr
thdr
tdew
twwh
twwl
thew
tsdw
thdw
tddgl
tddgh
15
tdinl I
16
17
tdinl2
tdinh
(1-1)
Parameter
Min.
Access time from CS Ao~A3 and DACK
RD delay time from CS Ao~A3 and DACK
RD pulse width (H-threshold)
CS, Ao~A3 and DACK hold time during read
Data delay time from RD
Data hold time during read
WR delay time from CS Ao~A, and DACK
WR pulse width (H~threshold)
WR pulse width (L-threshold)
CS, Ao~A3 and DACK hold time from WR
Data setup time
Data hold time during write
DREG. delay time from .CLK OUT
DREG t delay time from CLK OUT
INT • delay time from RD or WR
(End of INT by Buffer Ready)
INT • delay time from CLK OUT
INT t delay time from CLK OUT
CPU READ 5C16
(1-2)
Value
Typ.
Max.
200
90
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
410
ns
120
90
ns
ns
30
10
5
0
30
Unit
120
85
10
150
10
ISO
10
CPU WRITE IN 5C16
thew
t= tsdw--i
----<1
(1-3)
INT, DREG, DACK
eLK OUT
INT
(BUFFEJl.READY)
INT
(VSoc,HSOC)
-ICO©®DO-----6-40
i'hdW
-f~--
RFSCI6A/RPSCI6
(2)
5C16-V-RAM READ/WRITE
No. Symbol
1
2
3
4
5
6
7
8
9
10
16
17
18
19
20
21
22
23
24
25
26
trc
tras
trp
trcd
trsh
tcrs
tcas
tcp
tasr
trah'
tasc
tcah
trcs
trch
tITh
tdsr
tdhr
t W 9s
twcli
tdsw
tdhw
tdvr
thve
tsve
tdral
tdraf
27
tdwev
28
tdwef
II
12
13
14
IS
29
tdcav
30
tdcaf
31
tdvav
32
tdvaf
(2-1)
Parameter
Min.
Read cycle time
RAS pulse width
RAS pre-<:harge time
RAS-CAS delay time
RAS hold time
CAS-RAS setup time
CAS pulse width
"CAS" pre-<:harge time
Line address setup time
Line address hold time
Column address setup time
Column address hold time (CAS reference)
Read command set~ time
Read command hold time (CAS reference)
Read command hold time (RAS reference)
Da ta inpu t setup time (CAS reference)
Data input hold time (CAS reference)
Write command setup time
Write command hold time (CAS reference)
Data input setup time (CAS reference)
Data input hold time (CAS reference)
VBUS REQ delay time from CLK OUT
Hold time of VBUS EN against CLK OUT
Setup time of VBUS against CLK OUT
RAS ~ delay time from CLK OUT
Delay time for RAS from CLK OUT to turn to floating
Delay time for WEL or WEM from CLK OUT to turn to
valid
Delay time for WEL or WEM from CLK OUT to turn
to floating
Delay time for CAS, CASo and CASl from CLK OUT to
turn from floating to valid
Delay time for CAS, CASo and CASl from CLK OUT to
turn to floating
Delay time for VAo -7 and VDo -15 from CLK OUT to
turn from floating to valid
Delay time for VAo_7 and VDO_15 from CLK OUT to
turn to floating
5C16 READ V-RAM
(2-2)
Value
Typ.
Max.
Unit
279
ns
ns
ns
ns
ns
ns
ns
ns
150
90
40
80
0
ISO
60
0
20
0
40
0
0
0
60
0
0
60
0
60
';;s-
100
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
ns
60
ns
30
ns
130
ns
70
ns
60
ns
90
40
0
0
0
30
0
5C16 WRITE V-RAM
Ire
tras-·-
Irp
RAS
RAS
Ired
Irsh
CAs
CAS"
WEe - - - - - - - \
w,"
Dm~t-----....... _ _ __
---------------IID®®OO6-41
•
RF5C 16A/RR5C 16
(2-3)
(3-1)
VBUS REO, VBUS EN
ClK IK, ClK OUT
CLPK OUT
CLOCK IX
vaus
REQ
-----1f-""I'--+---t---t---CLOCK OL'T
VBUS EN
l.'.CLK
R. G. B.
«(or 80 ch.r,
640 dots mode)
-;,.
R. G. B.
(ror 40 char.
320 dots mode)
VAo-VA,
VDo-VD 1,
------l
b8
IColor code I
•• •
•
•
rbc-'_ _ _. -_ _ _b..:.,o
FF88H
A
0:0
~lbl5l"--'-1
. 1. .r-r-11
.1 . -J.bb 1.
[ f - h' -
o
~L....:..L-l-L-L-~_.~
(6)
Font of
character
code"OlH"
.:1
/
~~I~[~-J~I~[J~~/b7
00
01
10
11
@
007011
000011
• Data of character generator area
Character
generator value
Font of
character
code "OOH"
OOA811
• • • • • • • • • OOO.OOC FF88H
• • • • • • • • ~ • • • • OOO FFF811
I
Character code
Attribute
000811
006811
001811
(BCG+§>--- ••••••• 0 • • • 0000 FF7011
• • • • • • • • • 000.000
'~
1st color
font base
•
81
7 007011
[ Character}115
address
008811
BeG
•
•
Display
color
aear
lst color
~ When
displaying MSByte in
single color such as alphanumeric character, etc., all "0" or
all "1" is used.
~ When drawing the picture such
as game, etc, 4 colors can be
displayed at each dot with 2 bit
of combination such as bit 15
with bit 7, bit 14 with bit 6 and
so on.
2nd and 3rd colors are specified
by control register(C, D).
2nd color
3rd color
•
Graphic display
• 1 dot is consisted of 4 bits, and 8 dots are
allocated as I block.
• Display color is decided by 4 face synthesis of R, G, B and Lid.
BBG+2
;;
Lid
//
t
tt
BBG+4
"
Lid: L ight/dark
B: BLue
II
display screen
W
G:Green
R:Red
--------------IIO©®[]{]--·
6-45
RF5C I 6A/RP5C I 6
(7)
Attribure (character display)
• 4 kinds of attribute can be decided with bit
8 ~ bit 11 of code area data.
Black white invert
Longitudinal invert
Transverse invert
mack wllitc invert : Inverl 1st color and clear
'----_TransvcfliC invert
: l!lver! priority of display
~-----_longiludinal invert: Invert longitudinal of cell
1----------_ Vertic:!J invert
: Invert vertical of cell
b9--Q
b9~1
F.G
B.G
Vertical invert
bll~
bll
~1
~ ~
[E] [!]
B,G
0
F G
(8) Cursor
• Cross hair cursor is displayed. The coordinate of cursor in the horizontal direction is
specified with 10 bits of cursor register
CsHm and CsHL while in the vertical direction with 8 bits of CsV. 2 bits of cursor
register CsHm will not become effective
unless CSHL is written.
(9)
Shape of cursor
9 dots
Dot scroll (only back ground)
• It allows scroll of 0~7 dots in the horizon-
Shift to vertical ._ ... ,.,
directiop
:~,.
fi
tal and vertical directions. The number of
shift to the horizontal and vertical directions is specified by respective dot scroll
register SH and SV.
(10)
[f
Shift to horizon tal direction
Control of video memory area
• Base address
BG base address (BBG-M, BBG-L) is
consisted of 16 bits and allows to specify
by 1 character unit. Therefore, the change
of BG base address allows scroll in the
column or line direction. BBG-M becomes
effective when BBG-L is written. Those
subsequent to this address area fall in code
data of back ground. In case of graphic,
too, data are stored here.
FG base address (BFG-M) allows paging
of each 1,024 characters with 6 bit. Subsequent to this address, code data of fore
ground are stored in 1,000 words (40
character X 25 line).
Character generator base address (BCGM) is able to specify the start address of
character font for each 2,048 words
with 5 bit. Character font is consisted
of 1 cell 8 words and is able to select
256 patterns. (Refer diagram) It will
not be used for only graphic display.
8 7
Fore ground
OOOOH
Back ground
BBG-M, L,
BFG-M
Character
,generator
I
I
I
I
I
I
I
I
I
IL ___ Lt ____ LI
I
I
________ .w--'
mH-I
-ICD©®[]{]-------------~
6-46
RF5CI6A/RP5CI6
64 K word max.
• Width of code area (No. of character AH)
FG is fixed with 40 characters. BG can
be selected from 40 characters (320 dots),
64 characters (512 dots), 80 characters
(640 dots) and 128 characters (1,024 dots).
With this, the width of virtual screen is set.
B.C
R.c.M.L
Cade Area
80,40 character
Display
window
--------;Ac-H--------j
(Code area, number of character
in horizontal direction)
(11)
Updating function of frame buffer
• Since it has the transfer register and address
counter, it allows read/write of frame
buffer data, making use of retrace line
section in horizontal/vertical direction
without relying on externally mounted
circuit.
• Write mode/read mode/read modify write
mode (see diagram below)
• Word transfer/Byte transfer (see diagram
below)
ReadTR-M
ReadTR·L
1
I
WriteTR·M
!
WnteTR-L
I
• The mode of increment +1/+2+2 of
address counter is used in graphic
display, for example, only the face of
BLUE is rewritten in sequence.
Write mode
Read mode
Read modify write
Word tranJler Byte trander Word transfer Byte llansfer Wordtransler Byte transfer
Add+l-RT
Add+l-RT
Add+l-Wf
WT-Add+l
Wf-Add+1
WT
-RT
WT-Add+1
WT-Add+1
WI-Add+)
WT-Add+l
wr
WT
-RT
-RT
• DMA transfer
In case of DMA transfer, it is necessary to set whether to read or write to LSB
of transfer register, or to read or write to
MSB. In case of word transfer, TR-L
and TR-M vary at every 1 byte. In clijle
of byte transfer, it is always written in
the register that has been set.
ReadAdd·M
i
RewAdd-L
WriteAdd-M
WriteAdd·L
I
I
TR
Transfer register
Add: Addl'ess counter
RT
RT
RT
RT
RT : Read transfer (frame buffer read)
WT: (frame buffer write)
The rdationship •• -" betwem read/write operation of transfer reJister and read/write low;ud fume buffer
represenu Ihe sequence of pro,css. For cumple. when CPU side read TR·L register under (read mode), fU"St of
aU, number of addteu counter b set as + 1, then, perform read of frame buffer. .. - .. represents thai no steps
are beina: taken for frame buffer.
(12)
I
D-RAM refresh
• 8 addresses per 1 H (64JLs) are refreshed
within retrace line section.
D-RAM
refresh
(8 cycle)
2.31's
Horizontal
line section
Horizontal
line section
-------------ICO©®OO6-47
RF5C I 6A/RP5C I 6
• 64 pin flat package dimel,lsion (Unit: mm)
24.8~"
r-------~(976~· ..·) - - - - - - -
~U-lH.-U-U-lH.J-I [
O.S5\lAX
~i I
i
)~
I
~
-
m
O.SMAX
Q
~
~
1f.,'
I ,
1.27
2.54
!O.42tO.06
1
M
!O 4 +0.03
. _.o0?
0.4710.()(j! O.42.iO.06
I 1.5 +0.1 11"1.5±-O,l ~ I
TO-92
mini -power-mold
1
GND
2
Yin
3
Vout
----~-~---------ltD(lg®OO6-53
•
©~®!!!'!'!!!!![}O~~~I VOLTAGE DETECTORSH-9-sso7
'!II!!!!!II'!'!I!!!,!,!!!!!C!!!,!,!!!!!O
RX5VA Series
• OUTLINE
RXSV A series, developed with C-MOS processing technology, are accurate, low-power-consumption
voltage detectors. The detectors include comparators, output drivers and hysteresis circuit.
The value of detect voltage is set internally, and is accurately controlled by Laser Trimming.
There are three types of output: N-ch open-drain, P-ch open-drain, and C-MOS. There are two
convenient packages: mini-power-mold and TO-92. The RXSV A series can be used as a reference
voltage supply for rcs in many applications.
• FEATURES
. TYP. l.OMA (VDD = 3.0V)
. l.5V to 10.OV
. 0.1 V step
. ±2.S%
. TYP. ±100 PPMj"C
. N-ch open drain,
P-ch open drain,
CMOS
• Compact Package ................................. . TO-92, min-power-mold
•
•
•
•
•
•
Extremely low power consumption ...................
Wide voltage range ................................
Variety of detect voltage ...........................
High accuracy ....................................
Good temperature characteristic for detect voltage .......
Output Options ..................................
• APPLICATIONS
"Resets circuit ofP-ch, N-ch, and C-MOS microcomputers
•
•
•
•
•
•
Battery checker
Logic circuit reset
Level discriminator
Waveform shaping circuit
Switching circuit for battery backup
Power failure detector
--------------ICO©®[}o6-55
•
RX5VA
.. SELECTION GUIDE
You can define several options, including output driver type, package and packing method with the
RXSVA series.
The devices are defined by the following characters.
R X 5 VA X X X X
+-
Type number
'-0---'
iiii
abc d
Meaning
Character
Defines the packaging type
a
E: TO-92
H: Mini -power-mold
Defines the voltage value that is to be monitored
( -VDET)
b
The monitor range is 2.00V to 6.00V in 0.1 V units,
with an accuracy of ±2.S%.
Defines the output type
c
A: N -ch open drain
B
P -ch open drain
C : C-MOS
Defines the packing method
d
A-Tl
Taping-Tl type (See Fig. 1 )
A-T2
Taping-T2 type (See Fig. 1 )
A-RF: Taping - RF type (See Fig. I)
A-RR: Taping - RR type (See Fig. I)
B
Gluing (Gluing is for mini power mold package
as a sample)
C
Electric conductive bagging (for TO-92)
Table 1
-ICO©®DO
6-56
RX5VA
Example
Voltage Detect ( - VDET)
Type
number
MIN.(V) TYP.(V) MAX.(V)
Output Driver
N-ch
P-ch
Open·Drain
Open·Drain
Packing
method
Package
C~MOS
0
RX5VA20AX
1.950
RX5VA20BX
2.000
0
2.050
0
RX5VA20CX
0
RX5VA21AX
2.048
RX5VA21BX
0
2.152
2.100
0
RX5VA21CX
ATaping
0
RX5VA27AX
2.633
RX5VA27BX
2.700
0
2.767
E:TO-92
0
RX5VA27CX
RX5VA45AX
0
RX5VA45BX
4.388
0
4.612
4.500
0
RX5VA45CX
H:Minipower
mold
(SOT-89)
B:Gluing
C:Electric
Conductive
bagging
0
RX5VA47AX
RX5VA47BX
4.583
0
4.817
4.700
0
RX5VA47CX
0
RX5VA55AX
5.363
RX5VA55BX
0
5.637
5.500
0
RX5VA55CX
Table 2
* Consult
the guide to determine specifications other than those shown in Table 2.
Use the type number.
• TAPING METHODS
I_~O~
40101
,I~ ~:5~!~
r-O-O-O-O~'lo~d -¢ ¢ 1-. -::1:
P9 I( b:n:J ~~ j
r
C
~
u:::==u
u::=:JJ
Tl type
\;\ W-1S2q~l-"'I=__.M'-'-l
_
~l
c
lLdJ u::=:JJ- ~r~L
T2 type
RF type
mini -power-mold
RR type
TO-92
Figure I
---------------ICD©®OO-6~57
RXSVA
• SYSTEM BLOCK DIAGRAMS
Figure 2 is block diagrams of RX5VA series and shows the system with three terminals.
The system has three types of output drive: N-ch open-drain, P-ch open-drain, and C-MOS.
N ·ch open·drain
(RX5VAXXAX)
P·ch open·drain
C-MOS
(RX5VAXXBX)
(RX5VAXXCX)
VDD
-VDET
-+-'
....
til
..c:
vss
U
"36
>(
f-SH-A64-44
II
7-3
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* : under development
19.6
10
•
- SH I Type Configuration & Dimension
Pin Assignment
SH-A316-41
ON 1
320
-.tJ
r"'t"'f-------------;:;:-;:298.7±O.2=::-----------4'
!~
~1
(HEATER ELEMENTS)
I
l1~I
"
~
eN2
MOLEX5268
12A
eNI
MOLEX5268-IIA
ON 2
PIN
SIGNAL
PIN
1
VHD
1
NO
2
VHD
2
SB4
3
GND
3
SB3
4
GND
4
SB2
5
VDD
5
SB1
6
Vss
6
OK
7
SB8
7
[D
8
SB7
8
DI
9
SB6
9
GND
10
SB5
10
GND
11
TH
11
VHD
12
VHD
12
o
r==---11
YF=='.IG
W
@
([]J
0)
13
14
SH-A48-44
--------
ON1
r
A.~11-11~---=-~~=;~=-(HE=A~;"i;T.f,;:E~~:Mm;;T)ENT~)
--~~--~~~~I''I ~~Jn
~------------23'-----------~1
~~l
_
::;1 "
"v
b
L -_ _====~
____
@
-===~
yr---91
~\
~
NO' '51"ONAL
SIGNAL
1
VHD
2
VHD
2
3
VHD
3
1
-----
4
VHD
5
GNO-
5
6
GND
6
4
7
GND
8
GND
-
---
Vss
VDO
_._"._.
SB8
SB7
--~--
SB6
SB5
SB4
~-- ~-
eN2
Q'
SH-A68-42
~
~
-----
CN2
PIN
PIN NO,
r-~(0
CD
~
__
SIGNAL
124 + I
IIIr---~_,,;:002~-------i'
i
t
II -j
~
•
~
PIN NO,
PIN NQ.
SIGNAL
1
VHD
11
SB1
2
VHD
12
LD
3
GND
13
OK
SIGNAL
4
GND
14
DI
5
GND
15
VDD
6
GND
16
Vss
7
TH
17
NO
8
SB4
18
VHD
9
SB3
19
VHD
10
SB2
PIN NO.
SIGNAL
1
VHD
11
LD
2
VHD
12
OK
3
VHD
13
Din
4
GND
14
VDD
5
GND
15
Vss
6
GND
7
TH
8
SB3
9
SB2
10
SB1
t~
SH-B98-42
'
::::~5I
~
PIN NO.
SIGNAL
4BtO.2
(HEATER ELEMENTS)
_
~
05
22'C
10
20
15
TIme (mS)
Pulse Durability
Ambient Temperature & Optical Density
(Full Glaze Type)
15
o 25mJidot
(022msecl
dot denSity
pulse Width
paper
platen weight
rubber thickness
rubber hardness
platen diameter
10'
dot density
8dpm
pulse penod
applied voltage
5msec/hne
050
075
Applied Energy (m.J/dot)
15V
Platen weight & Optical Density
(Partial Glaze Type)
I
009
08
r
Wear Durability (Full Glaze Type)
10
~ 20lA for Lat>el
135F tor High Speed FAX
PaperRICOH120lA
dotden"ty
.
8dpm
paper
RICOH 135 F
rubber thickness 5mm
platen d1ameter 20mmjli
All Graze
energy
platen wel!Jht 3009/cm
paper feed speed
l00mm/sec
dot density
8dpm
without prlnling
S~
PaperRICOH120LA
;'05
O.2BmJ/dot
'"
PaperRICOH135F
T
100
8dpm
0.6ms
RICOH 135F
300g/cm
5mm
40'
20mmp
200
300
400
2Q
500
Paper Feed Length (km)
Platen Weight (g/cm)
7-8
30
ICO®®OO
Typical Specification
1. Pulse Resistance
2. Wear Resistance
SH I
Type
(MIN)
Pulse Number
4 x 10 7
SH II
1
X
SH I
SH II
MIN40
MIN 30
5
Type
10'
Paper Feed Length
(km)
Cycle Time
(ms/line)
10
5
Cycle Time
(ms/line)
10
Pulse Width
(ms)
1
1
Pulse Width
(ms)
1
1
0.65
0.35
(w/dot)
0.45
0.35
(mm/sec)
12.5
25
(g/cm)
300
300
SH I
SH II
Applied Power
(w/dot)
Applied Power
Paper Feed Sp.eed
o Firing One Dot in Open Air. Room Temp .•
Room Humi.
Platen Pressure
3. Environmental Condition
4. Platen Condition
Type
SH I
(Co)
Operating Temp.
(%)
Operating Humi.
(Co)
Storage Temp.
--Storage Humi.
(%)
SH II
Type
(mm)
5-40
0-40
30-85
30-85
~ller
Pressure
(g/cm)
300±50
-10-50 -20-60
~oller
Rubber Hardness (deg)
45±10
40±5
t2-5
t2-4
30-85
Roller Diameter
30-85
Rubber Thickness
(mm)
MAX 25 MAX18
300±50
5. Timing Wave Form
Type
CK
DI
LD
SH I
SH II
tcw 1
MIN (ns)
100
100
tcw 2
MIN (ns)
100
100
tds
MIN (ns)
100
100
tdh
MIN (ns)
100
100
tis
MIN (ns)
500
1500
tlw
u
58
Vout
MIN (ns)
250
350
tf
MAX (ns)
250
50
tr
MAX (ns)
250
50
* Typical specification discribed on this page is for
SH I (SH·A48-44) and SH II (SH-216-08FS-41).
,--- RICOH CUSTOM PRODUCT DEVELOPMENT FLOW CHART
,------
J
I
l
I
Confirmation of Customer
Requested Specification
Approval of Custom Development
Specification by Customer
Delivery of Engineering
Sample (E.S.)
I
I
I
I
Approval of C.S.
Specification by Customer
I
I
Evaluation of C.S. and
Approval Mass Production
I
Check of Initial
Production
~~:~~~~c~~ Section
I
Evaluation of E.S and
Approval by Customer
I
Delivery of Commercial
Sample (C.S.)
~ ;~1~~e~~jon
7-9
I
I
J
I
I
ICD®®[}{]
RICOH COMPANY, LTD.
ELECTRONIC DEVICES DIVISION
. TOKYO OFFICE
1. 15·5, MINAMIAOYAMA, MINATO·KU, TOKYO 'rlO7 JAPAN
PHONE 03 (479) 3111
. OSAKA OFFICE
34- 5 ENOKI - CHO, SUITA-SI , OSAKA
RICOH-OSAKA Building 'r564 JAPAN
PHONE 06(337) 3711
. TOKYO DEVELOPMENT CENTER
4· 13·5, NIHONBASHI ·HON·CHO, CHUO·KU, TOKYO 'r 103 JAPAN
PHONE 03 (662) 11 OS
RICOH CORPORATION
.2011 CONCOURSE DRIVE SAN JOSE CA 95131 USA
PHONE 408(434)6100
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