1988_SGS Thomson_Audio_and_Radio_ICs_Databook_1ed 1988 SGS Thomson Audio And Radio ICs Databook 1ed
User Manual: 1988_SGS-Thomson_Audio_and_Radio_ICs_Databook_1ed
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AUDIO AND RADIO ICs
DATABOOK
1st EDITION
JULY 1988
1
!
USE IN LIFE SUPPORT MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF SGS-THOMSON
Microelectronics. As used herein:
.
1. Life support devices or systems are devices or systems
which, are intended for surgical implant into the body
to support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for
use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TABLE OF CONTENTS
INTRODUCTION
ALPHANUMERICAL INDEX
Page 4
7
PRODUCT SELECTOR GUIDE
11
DATASHEET
17
~C~G~:
~
DESIGNING WITH THERMAL IMPENDANCE
MECHANICAL DATA
949
SALES OFFICES
974
963
3
TWENTY YEARS OF INNOVATION
Way back in 1969 SGS-THOMSON Microelectronics developed the World's first
monolithic audio power amplifier. Called TAA611 this trailblazing device combined
signal circuits with an integrated 1W power stage.
Introduced almost twenty years ago, SGS-THOMSON's TAA611 (left) was the first integrated
audio power amplifier. The new TDA7360 (right) is twenty-five times more powerful but only nine
times larger.
TAA611 (1969)
TDA7360(19B8)
Since then SGS-THOMSON has always remained at the forefront of audio amplifier
development, creating dassic products such as the much-copied TDA2003 & TDA2005,
innovative solution like the TDA7232160 dass D amplifier kit and new generation devices
like the TDA7360 complementary amplifier. In packages, too, SGS-THOMSON has led
the way with innovations like the Multiwatt plastic power packages and antistre~
leadframes that enhance reliability.
SGS-THOMSON audio amplifiers have special "antistress" leadframes that isolate the die from
mounting stresses, enhancing reliability. Notches and a groove between the tab and die flag
ensure that the die is unaffected even when the tab is deformed.
4
Not just the leader in technology, SGS-THOMSON is also the leader in audio amplifier
sales; to date more than 600,000,000 amplifier ICs have been produced by the company
and more than half of the car radios produced worldwide include SG5-THOMSON
amplifiers.
Audio amplifier are only a part of the present Audio &Radio portfolio. Today the company
is developing advanced signal circuits for the same markets - devices like the TDA7300
audio processor and the M114A digital sound generator.
Whatever your application, you'll probably find the best product for the job right here in
the SG5-THOMSON Audio & Radio Products databook.
Manufactured by a major US manufacturer for high-end car stereo systems, this 25W class D
amplifier module is based on two ICs specially designed for the application by SGS-THOMSON.
5
ALPHANUMERICAL INDEX
Type
Function
Page
AM6012/A
HIGH SPEED 12 BIT D/A CONVERTERS ....................................................
19
DAC0808/7/6
8 BIT D/A CONVERTERS ...............................................................................
31
L272/M
DUAL POWER OPERATIONAL AMPLIFIERS ..............................................
43
L272D
DUAL POWER OPERATIONAL AMPLIFIER .................................................
49
L293B/E
PUSH-PULL FOUR CHANNEL DRIVERS .....................................................
53
L293C
PUSH-PULL / H-BRIDGE DRIVER .................................................................
61
L293D
PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES ..............................
65
L2720/214
LOW DROP DUAL POWER OPERATIONAL AMPLIFIERS .........................
69
L2726
LOW DROP DUAL POWER OPERATIONAL AMPLIFIER ............................
77
L3654S
PRINTER SOLENOID DRIVER ......................................................................
81
L4901A
DUAL 5V REGULATOR WITH RESET ..........................................................
85
L4902A
DUAL 5V REGULATOR WITH RESET AND DISABLE .................................
95
L4903
DUAL 5V REGULATOR WITH RESET AND DISABLE .................................
105
L4904A
DUAL 5V REGULATOR WITH RESET ..........................................................
113
L4905
DUAL 5V REGULATOR WITH RESET AND DISABLE .................................
121
L4915
ADJUSTABLE VOLTAGE REGULATOR PLUS FILTER ...............................
129
L4916
VOLTAGE REGULATOR PLUS FILTER........................................................
135
L4918
VOLTAGE REGULATOR PLUS FILTER........................................................
141
L4920/21
VERY LOW DROP ADJUSTABLE REGULATORS .......................................
VERY LOW DROP 1.5A REGULATOR..........................................................
147
151
L4940
L4941
VERY LOW DROP 1A REGULATOR.............................................................
159
L4960
2.5A POWER SWITCHING REGULATORS ..................................................
165
L4962
1.5A POWER SWITCHING REGULATOR .....................................................
179
L6201
0.3 OHM DMOS FULL BRIDGE DRIVER ......................................................
191
L6202
0.3 OHM DMOS FULL BRIDGE DRIVER ......................................................
203
L6203
0.3 OHM DMOS FULL BRIDGE DRIVER ......................................................
219
L6210
DUAL SCHOTTKY DIODE BRIDGE .............................................................. .
235
L6233
PHASE LOCKED FREQUENCY CONTROLLER ..........................................
239
L6235
R-DAT BRUSHLESS DRIVER ........................................................................
247
L6236
BIDIRECTIONAL R-DAT BRUSHLESS DC MOTOR DRIVER .....................
255
LM1837/D
DUAL TAPE PREAMPLIFIER WITH AUTOREVERSE .................................
263
LS404
HIGH PERFORMANCE QUAD OPERATIONAL AMPLIFIER .......................
271·
LS4558N
HIGH PERFORMANCE DUAL OPERATIONAL AMPLIFIER ........................
281
M082/82A
TONE GENERATORS ....................................................................................
289
M083/83A
TONE GENERATORS ....................................................................................
289
M086/86A
TONE GENERATORS ....................................................................................
289
M108
SINGLE CHIP ·ORGAN .......................:............................................................
293
M112
POLYPHONIC SOUND GENERATOR ...........................................................
303
M114A
DIGITAL SOUND GENERATOR ....................................................................
319
M114S
DIGITAL SOUND GENERATOR ....................................................................
333
7
ALPHANUMERICAL INDEX
Type
Function
Page
M208
SINGLE CHIP ORGAN ....................................................................................
293
M3004
REMOTE CONTROL TRANSMITIER ...........................................................
347
M3005
REMOTE CONTROL TRANSMITIER ...........................................................
347
M5450
LED DISPLAY DRIVER ...................................................................................
357
M5451
LED DISPLAY DRIVER ............................. :.....................................................
357
M5480
LED DISPLAY DRIVER ...................................................................................
365
M5481
LED DISPLAY DRIVER ...................................................................................
371
M5482
LED DISPLAY DRIVER ..•............................................................................... .
377
M8438A
SERIAL INPUT LCD DRIVER ........................................................................ .
383
M8439
SERIAL INPUT LCD DRIVER .........................................................................
391
M8571
1024 BIT SERIAL S-BUS EEPROM ...............................................................
397
M8716A
CLOCK/CALENDAR WITH SERIAL I"C BUS ................................................ .
409
M9306
256 BIT SERIAL EEPROM .............................................................................
415
M145026
REMOTE CONTROL ENCODER/DECODER CIRCUIT ................................
421
M145027
REMOTE CONTROL ENCODER/DECODER CIRCUIT ................................
421
M145028
REMOTE CONTROL ENCODER/DECODER CIRCUIT ................................
421
TBA810CB
7W AUDIO AMPLIFIER ...................................................................................
431
TBA810P
7W AUDIO AMPLIFIER .................................................................................. .
435
439
TBA81OS
7W AUDIO AMPLIFIER ...................................................................................
TBA820M
MINIDIP 1.2W AUDIO AMPLIFIER .................................................................
443
TCA3089
FM-IF RADIO SYSTEM ...................................................................................
447
TCA3189
FM-IF HIGH QUALITY RADIO SYSTEM ........................................................
451
TDA1151
MOTOR SPEED REGULATOR ......................................................................
455
TDA1154
SPEED REGULATOR FOR DC MOTORS .....................................................
461
TDA1220B
AM-FM QUALITY RADIO ................................................................................
465
TDA1220L
LOW VOLTAGE AM-FM RADIO .....................................................................
481
TDA1904
4W AUDIO AMPLIFIER ...................................................................................
489
TDA1905
5W AUDIO AMPLIFIER WITH MUTING .........................................................
497
TDA1908
8W AUDIO AMPLIFIER .................................. ;............................................... .
509
TDA1910
lOW AUDIO AMPLIFIER WITH MUTING.......................................................
519
TDA2002
8W CAR RADIO AUDIO AMPLIFIER .............................................................
531
TDA2003
lOW CAR RADIO AUDIO AMPLIFIER ...........................................................
533
TDA2004
10+10W STEREO AMPLIFIER FOR CAR RADIO.........................................
543
TDA2005
20W BRIDGE AMPLIFIER FOR CAR .RADIO ................................................
551
TDA2006
12W AUDIO AMPLIFIER ..........................................................•......................
569
TDA2007
6+6W STEREO AMPLIFIER ...........................................................................
579
TDA2008
12W AUDIO AMPLIFIER .................................................................................
585
TDA2009
TDA2009A
10+1OW HIGH QUALITY STEREO AMPLIFIER ............................................
10+10W SHORT CIRCUIT PROT. STEREO AMPLIFIER.............................
593
603
TDA2030
14W Hi-Fi AUDIO AMPLIFIER ........................................................................
613
- - - - - - - - - - W'l SGS-1MOMSON
8
. " m i!io©oo@rn~©1lI!I@~O©$
ALPHANUMERICAL INDEX
Type
Function
Page
TDA2030A
18W Hi-Fi AMPLIFIER AND 35W DRIVER ................................................... .
623
TDA2040
20W Hi-Fi AUDIO POWER AMPLIFIER .........................................................
637
TDA2220
AMlFM RADIO .................................................................................................
647
TDA2320
INFRARED REMOTE CONTROL PREAMPLIFIER ........................... :...........
655
661
TDA2320A
MINIDIP STEREO PREAMPLIFIER ...............................................................
TDA2822
DUAL POWER AMPLIFIER ............................................................................
671
TDA2822M
DUAL LOW-VOLTAGE POWER AMPLIFIER ................................................
679
TDA2824S
DUAL POWER AMPLIFIER ............................................................................
689
TDA3410
DUAL TAPE PREAMPLIFIER WITH AUTOREVERSE .................................
695
TDA3420/D
DUAL VERY LOW NOISE PREAMPLIFIER ..................................................
703
TDA7211A/D
LOW VOLTAGE FM FRONT END ..................................................................
709
TDA7220/D
VERY LOW VOLTAGE AM-FM RADIO..........................................................
717
TDA7230A
STEREO DECODER AND HEADPHONE AMPLIFIER .................................
729
TDA7231
1.6W AUDIO AMPLIFIER ................................................................................
735
TDA7232
LOW NOISE PREAMPLIFIER COMPRESSOR .............................................
739
TDA7233/D
1W AUDIO AMPLIFIER WITH MUTE .............................................................
751
TDA7236/D
VERY LOW VOLTAGE AUDIO BRIDGE ........................................................
755
TDA7240A
20W AUDIO AMPLIFIER FOR CAR RADIO ..................................................
759
TDA7241
20W BRIDGE AMPLIFIER FOR CAR RADIO ................................................
765
TDA7250
Hi-Fi DUAL DRIVER ....................................................................................... .
769
TDA7255
22W FIR OR BRIDGE AMPLIFIER .................................................................
777
TDA7256
22W BRIDGE AMPLIFIER ..............................................................................
783
TDA7260
HIGH EFFICIENCY AUDIO PWM DRIVER ....................................................
789
TDA7270S
MULTIFUNCTION SYSTEM FOR TAPE PLAYERS ......................................
803
TDA7272
HIGH PERFORMANCE MOTOR SPEED REGULATOR ..............................
807
TDA7274
LOW-VOLTAGE DC MOTOR SPEED CONTROLLER .................................
823
TDA7275A
MOTOR SPEED REGULATOR ......................................................................
829
TDA7276
SPEED REGULATOR FOR SMALL DC MOTORS .......................................
833
TDA7282/D
STEREO LOW VOLTAGE CASSETIE PREAMPLIFIER ..............................
837
TDA7300
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR ...........................
843
TDA7302
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR ...........................
855
TDA7320
AM/FM CAR RADIO SYSTEM ........................................................................
865
TDA7322
AM/FM CAR RADIO SYSTEM ........................................................................
867
TDA7325
PLL RADIO TUNING SYNTHESIZER ............................................................
869
TDA7350
BRIDGE-STEREO AMPLIFIER FOR CAR RADIO ........................................
877
TDA7359/D
LOW VOLTAGE NBFM IF SySTEM...............................................................
883
TDA7360
BRIDGE-STEREO AMPLIFIER WITH CLIPPING DETECTOR ... .................
889
TDA7361 10
LOW VOLTAGE NBFM IF SySTEM...............................................................
895
TDA8160
INFRARED REMOTE CONTROL RECEIVER ...............................................
901
TEA1330
FM STEREO DECODER ................................................................................ .
905
9
ALPHANUMERICAL INDEX
Type
Function
Page
TEA2025B
STEREO AMPLIFIER ......................................................................................
911
TL072
LOW NOISE JFET-INPUT DUAL OPERATIONAL AMPLIFIER ....................
915
TL074
LOW NOISE JFET-INPUT QUAD OPERATIONAL AMPLIFIER ...................
923
TL082
JFET-INPUT DUAL OPERATIONAL AMPLIFIER ..........................................
931
TL084
JFET-INPUT QUAD OPERATIONAL AMPLIFIER .........................................
939
10
PRODUCT SELECTOR GUIDE
POWER AMPLIFIERS FOR CAR-RADIO
TDA7240A
TDA7241
TDA7255
TDA7256
TDA7350
TDA7360
TDA7260
TDA2003
TDA2004
TDA2005
Page
- 20W Bridge AmplHier ............................................................................................................. 759
- 20W Bridge AmplHier ............................................................................................................. 765
- 22W F/R or Bridge Amplifier ................................................................................................... 777
- 22W Bridge AmplHier ............................................................................................................. 783
- 22W Bridge/Stereo Amplifier ............................ ;..................................................................... 877
- 2x12W Amplifier with Clipping Detector .................................................................................. 889
- High Efficiency Audio PWM Driver ..................................... '" ................................................. 789
-1 OW Audio Amplifier " ..................................................................,.......................................... 533
-10+ 1OW Stereo Amplifier .......................................................................................................543
- 20W Bridge Amplifier .........................................................................................,.......... ......... 551
HI-FI AND HIGH QUALITY POWER AMPLIFIERS
TDA7250
TDA2030A
TDA2030
TDA2040
TDA2009
TDA2009A
TDA2007
TDA2006
TDA1910
- Dual Driver ............................................................................................................................. 769
- 18W Amplifier and 35W Driver ............................................................................................... 623
-14W Audio AmplHier ............................................................................................................... 613
- 20W Audio Power Amplifier .................................................................................................... 837
-10+10WStereoAmplifier .............................. :........................................................................ 593
-10+ 1OW Short Circuit Protected Stereo ................................................................................. 603
- 6+6W Stereo Amplifier ... ........................................................................................................ 579
-12W Audio Amplifier ............................................................................................................... 569
- 10W Audio Ampl. with Mute ................................................................................................... 519
- - - - - - - - - - - Gil
SGS-T1tOMSON
." ..
[i'j]U©OO@ll:~~©1fOO@~U©'"
11
PRODUCT SELECTOR GUIDE
GENERAL PURPOSE POWER AMPLIFIERS
TDA2007
TDA2008
TEA2025B
TDA2822
TDA2822M
TDA2824S
TDA7231
TDA7233
TDA1904
TDA1905
TDA1908
TDA1910
TBA820M
Page
- 6+6W Stereo Amplifier ........................................................................................................'" 579
-12W Audio Amplifier ................................................................................................................ 585
- Stereo Amplifier .............................................................................. '" .................................... 911
- Dual Power Amplifier .............................................................................................................. 671
- Dual Low-VoHage Power Amplifier ......................................................................................... 679
- Dual Power Amplifier ............................................................................................................. 689
-1.6W Audio Amplifier ................................................................................... '" ........................ 735
-1 W Audio Amplifier with Mute ................................................................................................ 751
- 4W Audio Amplifier ......................................................................... '" .................................... 469
- 5W Audio Amplifier with Mute ................................................................................................ 497
- 8W Audio Amplifier ................................................................................................................ 509
-10WAudioAmplifierwilhMute ..............................................................................:............... 519
- 1.2W Audio Amplifier .............................................................................................................. 443
LOW VOLTAGE POWER AMPLIFIER
TDA7231
TDA7233
TDA7236
TDA2822M
TEA2025B
12
-1.6W Audio Amplifier .............................................................................................................. 735
-1W.Audio Amplifierwith Mute ................................................................................................751
- Very Low VoHage Audio Bridge .............................................................................................. 755
-1.2W Audio Amplifier ............................................................................................................. 679
-Stereo Amplifier .....................................................................................................................911
PRODUCT SELECTOR GUIDE
PREAMPLIFIERS AND AUDIO PROCESSORS
TDA7300
TDA7302
TDA7232
TDA7282
TDA2320A
TDA3410
TDA3420
LM1837
LS4558N
LS404
TL072
TL074
TL082
TL084
-C-¢--o-~
Page
Digital Controlled Stereo Audio Processor ........ .-........ .- ...................... .- ................................. 843
Dig Hal Controlled Stereo Audio Processor ............................................................................. 855
Low Noise Preamplifier Compressor ...................................................................................... 739
Stereo Low VoHage Preamplffier ......... ,.................................................................................. 837
Stereo Preamplifier ................................................................................................................ 661
Dual Low NoiseAutoreverse Preamplifier ............................................................................... 695
Dual Very Low Noise Preamplffier .......................................................................................... 703
Dual Low Noise Autoreverse Preamplifier .............................................................................. 263
Dual High Performance Operational Amplffier ........................................................................ 281
High Performance Quad Operational Amplifier ....................................................................... 271
~ JFET-Input Dual Operational Amplifier ................................................................................... 915
- JFET-Input Quad. Operational Amplifier ................................................................................. 923
- JFET-Input Dual Operational AmplHier ................................................................................... 931
- JFET-Input Quad. Operational Amplifier ................................................................................. 939
-
RADIO CIRCUITS
TDA7320
TDA7322
TDA7325
TDA2220
TDA7211A
TDA7220
TDA7230A
TDA7359
TDA7361
TDA1220B
TDA1220L
TCA3089
TCA3189
TEA1330
- AM-FM Car Radio System .....................................................................................................865
- AM-FM Car Radio System .....................................................................................................867
- PLL Radio Tuning SyntheSizer ............................................................................................... 869
-AM-FM Radio .........................................................................................................................647
- Low Voltage FM Front-End ............................................................ '" ..................................... 709
- Very Low Voltage AM-FM Radio ............................................................................................ 717
- Stereo Decoder and Headphone Amplffier ............................................................................. 855
-Low Voltage NBFM IF System ............................................................................................... 883
- Low Voltage NBFM IF System ...............................................................................................895
- AM-FM QualHy Radio .............................................................................................................465
-LowVoltageAM-FM Radio ....................................................................................................481
- FM-IF Radio System ..............................................................................................................447
- FM-IF High Quality Radio System .......................................................................................... 451
- FM Stereo Decoder ................................................................................................................905
------------- ~ ~~~~mg~~~~ ------------13
PRODUCT SELECTOR GUIDE
REMOTE CONTROL
Page
-Infrared Remote Control Receiver .. ........................................................................................ 901
- Preampmier for Infrared RC ................................................................................................... 655
- Remote Control Transmitter ................................................................'0 .................................. 347
- Remote Control Transmitter ................................................................................................... 347
- Encoder Circuit ........................................................................................;............................. 421
-DecoclerClrcuit .....................................................,................................................................ 421
-DecoderClrcuit ............................................................................................................;......... 421
TDA8160
TDA2320
M3004
M3005
M145026
M145027
M145028
MUSIC SYNTHESIS
-
M114A
M114S
M112
M108
M208
M082/3/6
M082A13A16A
Digital Sound Generator .........................................................................................................319
Digital Sound Generator .........................................................................................................333
Poliphonic Sound Generator .................................................................................................. 303
Single Chip Organ .................................................................................................................. 293
Single Chip Organ .................................................................................................................. 293
Tone Generators .................................................................................................................... 289
Tone Generators .................................................................................................................... 289
DISPLAY DRIVERS
DODD
L~L~L~L~
M8438A
M8439
M5450
M5451
M5480
M5481
M5482
M8716A
14
-
Page
Serial Input LCD Driver ..........................................................................................................383
Serial Input LCD Driver ....................................:..................................................................... 391
LED Display Driver ................................................................................................................. 357
LED Display Driver ...........................................................................c..................................... 357
LED Display Driver ..................................................................................................................365
LED Display Driver .................................................................................................................371
LED Display Driver .................................................................................................................3n
ClocklCalendarwith Seriall"C BUS ....................................................................................... 409
PRODUCT SELECTOR GUIDE
MOTOR CONTROLLERS
Page
- Dual Power Operational Amplifier ............................................................................................ 49
- Dual Power Operational Amplifier ............................................................................................ 43
- Low Drop Dual Power Operational Amplifier .................................................. '" ....................... 69
- Low Drop Dual Power Operational Amplifier .................................................. '" ....................... 77
- Push-Pull Four Channel Driver ................................................................................................. 53
- Push-Pull Four Channel Driver ................................................................................................. 65
-0.30 DMOS Full Bridge Driver ............................................................................................... 191
- 0.30 DMOS Full Bridge Driver ............................................................................................... 203
- 0.30 DMOS Full Bridge Driver ............................................................................................... 219
- Phase Locked Frequency Control ...................................................... '" ., ............................... 239
- R-DAT Brushless Driver ......................................................................................................... 247
- R-DAT Brushless Driver .......................................................................................................... 255
- Motor Speed Regulator ..........................................................................................,............... 455
- Speed Regulator for DC Motors ............................................................................................. 461
- High Performance Motor Speed Regulator .................................. ,.......................................... 807
- Low Voltage DC Motor Speed Controller ................................................................................ 823
- Motor Speed Regulator ............................................................... '" ............................ '" ......... 829
- Speed Regulator for Small DC Motors ................................................................................... 833
L272D
L272IM
L2720/214
L2726
L293B1E
L293D
L6201
L6202
L6203
L6233
L6235
L6236
TDA1151
TDA1154
TDA7272
TDA7274
TDA7275A
TDA7276
VOLTAGE REGULATORS
IN
5
:I
100nF
L4901 A
L4902A
L4903
L4904A
L4905
L4915
L4916
L4918
L4920
L4921
L4940
L4941
L4960
L4962
L621 0
OUT
100nF
4
3
:I
- Dual5V Regulatorwith Reset ..................................................................................................65
- Dual5V Regulator with Reset and Disable ............................................................................... 95
- Dual5V Regulator with Reset and Disable ............................................................................. 105
- Dual5V Regulatorwith Reset ................................................................................................ 113
- Dual5V Regulator with Reset and Disable ............................................................................. 121
- Adjust. Voltage Regulator Plus Filter ...................................................................................... 129
- Voltage Regulator Plus Filter .................................................................................................. 135
- Voltage Regulator Plus Filter .................................................................................................. 141
- Very Low Drop Adjust. Regulator ........................................................................................... 147
- Very Low Drop Adjust. Regulator ........................................................................................... 147
- Very Low Drop 1.5A Regulator ............................................................................................... 151
- Very Low Drop 1A Regulator .................................................................................................. 159
- 2.5A Power Switching Regulator ............................................................................................ 165
-1.5A Power Switching Regulator ............................................................................................ 179
- Dual Schottky Diode Bridge ...................................................................................................235
-------------
~ ~~~m=~~
--------------
15
DATASHEET
17
AM6012
AM6012A
12-BIT HIGH SPEED D/A CONVERTERS
• ALL GRADES 12-BIT MONOTONIC OVER
TEMPERATURE
• DIFFERENTAL NONLINEARITY TO ±0.012%
(13 BITS) MAX OVER TEMPERATURE
(A GRADES)
• 250ns TYPICAL SETILING TIME
• FULL SCALE CURRENT 4mA
• HIGH SPEED MULTIPLYING CAPABILITY
DIP-20 Plastic
• TIUCMOS/ECUHTL COMPATIBLE
SO-20L
• HIGH OUTPUT COMPLIANCE: - 5V TO + 10V
• COMPLEMENTARY CURRENT OUTPUTS
PIN CONNECTIONS
• LOW POWER CONSUMPTION: 230mW
DESCRIPTION
The AM6012 is an industry standard monolithic
12-bit digital-to analog converter. Complementary
current output and high speed multiplying capability make the AM6012 useful in a wide range of applications such as video displays, process control
circuitry and fast AID converters. The 6012 is the
first D/A to achieve 12-bit differential linearity without the use of thin film resistors or active trimming. The 6012's unique circuit design insures
monotonicity without the precision trimming associated with most other 12-bit DAC architectures.
The AM6012 is packaged in a 20-pin plastic DIP
and is SO-20L for surface mounting. Although tested and specified at ± 15V, the AM6012 works well
over a wide range of power supply voltages. Performance is essentially independent of supply voltage over the range of + 5 volts, - 12 volts to ± 18
volts. The AM6012 series guarantees full 12-bit monotonicity for all grades and differential nonlinearity as high as 0.012% (13 bits) for the A grades
and 0.025% (12 bits) for the standard grades over
the entire temperature range.
Guaranteed monotonicity and low cost make the
AM6012 an ideal choice for high volume applications requiring fine local resolution. Typical applications include printer graphics and video displays.
These applications need a minimum of 12 bits of
resolution, although conformance to an ideal
straight line from zero to full scale is less important.
June 1988
MS9-91
20
+Vs
92
2
19
10
93
3
18
10
94
4
17
-VEE
95
5
16
COMPo
96
6
15
VREF(-)
97
7
14
VREF (+)
98
8
13
GNO/VLC
99
9
12
812-LS9
910
10
11
911
A6012-2
1112
19
AM6012-AM6012A
ABSOLUTE MAXIMUM RATINGS
o to 70
-65 to + 125
±18
-5 to +18
-8 to +12
+VS to -VEE ±18V
max Differential
1.25
Operating Temperature Range
Storage Temperature
Power Supply Voltage
Logic Inputs
Voltage at Current Outputs Pins
Reference Inputs
Reference Input Current
°C
°C
V
V
V
V
rnA
CONNECTION DIAGRAM AND ORDERING INFORMATION
Type
Differential
linearity (%)
AM6012PC
0.025
AM6012APC
0.012
AM6012 D
0.025
AM6012 AD
0.012
Temperature
Range (Ge)
Package
o to 70
DIP.20
o to 70
SO.20L
BLOCK DIAGRAM
MSB
LSB
B1
B2
B3
B4 B5 B6
B7 BB B9 B10 BU B12
2
SEGMENT
AM6012
REFERENCE
20
R R R R
CODE SELECTED
NETWORK
0111 1111 1111
SEGMENT GENERATOR
17
VEE
THERMAL DATA
Rthj-amb
2/12
20
13
GND
ItItIll-l
Thermal resistance junction-ambient
+vs
AM6012-AM6012A
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = + 15V, VEE = - 15V, IREF = 1 .OmA, over the operating temperature
range unless otherwise specified
AM6012A
Paramo
Description
Test Conditions
AM6012
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Resolution
12
12
12
12
12
12
Bits
Monotonicity
12
12
12
12
12
12
Bits
Differential
Nonlinearity
Deviation from ideal step size
-
-
±.012
-
-
±.025
%FS
13
-
12
-
-
Bits
N.L.
Nonlinearity
Deviation from ideal straight line
-
-
±.05
-
-
±0.05
%FS
IFS
Full Scale Current
VREF=10.000V
R14= R15= 10.000kll
TA=25°C
3.967
3.999
4.031
3.935
3.999
4.063
mA
±20
-
±40
ppmoC
Full Scale Temp.Co.
±5
TCIFS
D.N.L.
-
-
-
±.OO05 ±.002
Voc
Output Voltage
Compliance
D.N.L. Specification guaranteed
over compliance range
ROUT>10 megohme typo
IFSS
Full Scale
Symmetry
IFS·IFS
Izs
Zero Scale Current
Is
Setting Time
To ± 1/2 LSB, all bits ON or
OFF, TA = 25°C
-
250
500
tpLH
tpHL
Propagation
Delay • all bits
500Al to 50%
-
25
COUT
Output Capacitance
-
VIL
VIH
Logic Logic "0"
Input
Levels Logic "1"
liN
Logic Input Current
VIN= -5 to +18V
-
VIS
Logic Input Swing
VEE = -15V
IREF
Reference Current
Range
115
Reference Bias
Current
±10
±.001
-5
-
+10
-5
-
±0.2
±1.0
-
-
-
0.10
-
-
±.004 p;.FSoC
+10
V
±2.0
pA
-
0.10
pA-
-
250
500
nSec
50
-
25
50
nSec
20
-
20
-
pF
-
-
0.8
-
-
0.8
2.0
-
2.0
-
-
40
-
-
40
pA-
-5
-
+18
-5
-
+18
V
0.2
1.0
1.1
0.2
1.0
1.1
mA
0
-0.5
-2.0
0
-0.5
-2.0
pA-
±0.4
V
3/12
21
AM6012·AM6012A
ELECTRICAL CHARACTERISTICS (Continued)
AM6012A
Paramo
di/dt
Description
Reference Input
Slew Rate
PSSIFS+
Power Supply
Sensitivity
PSSIFSVs
VEE
Power Supply
Range
1+
1-
Test Conditions
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
R14(eq) = 8000
CC=OpF
4.0
8.0
-
4.0
8.0
-
rnAl~s
VS-{+13.5Vto +16.5V)
VEE= -15V
-
±.OOO05 ±.001
-
±0.OOO5 ±.OOI
VEE= -13.5V to -16.5V
Vs= +15V
-
±.00025 ±.001
-
±.00025 ±.001
7uFS/%
Power Supply
Current
PD
Power
Dissipation
Vs= +5V, VEE= -15V
Vs= +15V,VEE=-15V
Fig. 1 - Relative Accuracy Error
-10.8
8.5
-
5.7
8.5
-13.7
-18.0
-
-13.7
-18.0
5.7
8.5
-
5.7
8.5
-13.7
-18.0
-
-13.7
-18.0
234
312
234
312
291
397
-
291
397
-
18
4.5
-16
-
-10.8
-
5.7
1+
Vs= + 15V, VEE= -15V
-18
-
4.5
VOUT=OV
Vs = +5V, VEE= -15V
1-
AM6012
-
18
V
rnA
rnW
Fig. 2 - Example of Nonmonotonic Behavior
OUTPUT
OUTPUT
CURRENT
FULL SCALE
'DIFFERENTIAL LINEARITY ERRORS SEVERE
ENOUGH TO CAUSE NONMONOTONICY
~
OIaITAL INPUT CODe
Aflf/IIl-I(J:: DIS
4112
22
DIGITAL INPUT CODE
A60I2-IO:: LIB
AM6012-AM6012A
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The segmented design of the AM6012, shown in
the block diagram, insures that there are no significant differential nonlinearities in the transfer characteristic. The eight major carries of the most
significant bits are not subject to the gross differential nonlinearities that can occasionally occur
in an R-2R type DAC. This advantage is due to the
fundamentally different way that the current is handled in an AM6012.
In a conventional R-2R type DAC, when the input
code is increemented past a major carry, a current
representing the new code is substituted for the
sum of all the less significant bit currents that were previously on. To avoid any nonlinearities, the
two total currents must be extremely well matched.
In the case of the MSB major carry in a 12-bit DAC,
the match must be better than one part in 2048 to
maintain monotonicity. However, in the AM6012,
a new current is never substituted for the sum of
several smaller ones, but redirected through alternate channels and incremented one step at a time.
For example, consider the MSB carry in an
AM6012. In the initial state of 011111111111 as
shown in the block diagram, the switches in the
segment generator are set in such a way that currents 10, II and 12 are steered directly into the noninverting output lOUT. In addition, a portion of 13
is directed through the 9-bit DAC that is controlled
by the 9 least significant bits into lOUT. With the
9LSBs set to "I", all of the 13 current is directed
to lOUT except for the 1/512 that goes to ground
through the right-most transistor in the 9-bit DAC.
After the input word is changed to 100000000000,
the segment decoder switch for 13 will be all the
way to the right, the switch for 14 will be in the middle, and all the switches in the 9-bit DAC will be
to the left. lOUT will be composed of 10, 11, 12 and
13. None of 14 will be directed into lOUT until a higher code is reached. In other words, 13 is now
steered directly to lOUT instead of being divided
by a factor of 511/512 in the 9-bit DAC. Since no
major current substitution occurs, there is less
chance of a large nonlinearity at this transition than
in a comparable R-2R DAC.
that results in a maximum relative accuracy error
of 3LSB. This must be distinguished from a differentiallinearity error. Differential nonlinearity is the
measure of the variation in analog value, normalized to full scale, associated with a ILSB change
in digital input code.
For example, for a 4mA full scale output, a change of ILSB in digital input code should result in a
0.98,.A change in the analog output current
(ILSB = 4mA x 1/4096 = 0.98,.A). If in actual use,
however, a ILSB change in the input code results
ina change of only 0.24/LA (1/4LSB) in output current, the differential linearity error would be 0.74,.A
or 3/4LSB.
The AM6012 has very good differential linearity in
spite of the porr relative accuracy. Conversely, the
[JAC of Figure 1 has very good relative accuracy
but poor differential linearity. The anomaly in the
middle of the transfer function is the result of a positive differential linearity error followed by a negative differential linearity err~r greater .tha~ ~ L~B.
A negative output step for an Increase In digital Input code is referred to as no~monot~mi? beh~vior.
In general, if a DAC has a differential lineanty error specification greater than 1LSB, it may be nonmonotonic at one or more of the major carries. In
most case the worst differential linearity error will
occur at the MSB transition pOint.
As noted in the functional description, the 6012's
unique design minimizes differentiallinea~ity errors
at the transition points of the 3MSBs. ThiS results
in a tight specification on maximum differential nonlinearity over temperature. Differential linearity is
verified on all AM6012s with 100% final testing.
In many converter applications, uniform step size
(or minimum differential linearity error) is more important than conformance to an ideal straight line.
Twelve-bit onverters are usually needed for high
resolution rather than high linearity as evidenced
by the fact that few transducers are more linear
than 0.1 %. This is also true in video graphics, where the human eye has difficulty discerning nonlinearity of less than 5%. The AM6012 is especially
well suited for these applications since it has inherently low differential linearity error.
RELATIVE ACCURACY VS. DIFFERENTIAL NONLINEARITY
We defines relative accuracy as the maximum deviation of the actual, adjusted DAC output from the
ideal analog output (a straight line drawn between
the lowest code output voltage and the highest code output voltage) for any bit combination. Relative accuracy is often referred to as nonlinearity. The
DAC transfer function shown in Figure 1 has a bow
5/12
23
AM6012-AM6012A
APPLICATION INFORMATION (Continued)
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents
are provided where 10 + 10 == IFR. Current appears
at the "true" output when a "1" is applied to each
logic input. As the binary count increases, the sink
current at pin 18 increases proportionally, in the
fashion of a "positive logic" D/A converter. When
a "0" is applied to any input bit, that current is turned off at pin 18 and turned on at pin 19. A decreasing logic count increase 10 as in a negative or
inverter logic D/A converter. Both outputs may be
used simultaneously. If one of the outputs is not
required it must still be connected to ground or to
a point capable of sourcing IFR; do not leave an
unused output pin one.
Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other
voltage source. Positive compliance is 2SV above
V - and is independent of the positive supply. Negative compliance is + 10V above V - .
The dual outputs enable double the usual peak-topeak load swing when driving loads in quasidifferential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The AM6012 operates over a wide range of power
supply voltages from a total supply of 20V to 36V.
When operating with V-supplies of -10V or less,
IREF :s; 1mA is recommended. Low reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative common mode range, negative logic
input range, and negative logic threshold range;
consult the various figures fro guidance. For example, operation at - 9V with IREF = 1mA is not recommended because negative output compliance
would be reduced to near zero. Operation from lower supplies is possible, however at least 8V total
must be applied to insure turn-on of the internal
bias network.
Symmetrical supplies are not required, as the
AM6012 is quite insensitive to variations in supply
voltage. Battery operation is feasible as no ground
connection is required; however, an artificial ground
may be used to insure logic swings, etc. remain
between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and mononicity specifications of
the AM6012 are guaranteed to apply over the entire rated operating temperature range. Full scale
6/12
24
output current drift is flight, typically ± 10ppm/o C
with zero scale output current and drift essentially
negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should match and track that of the output resistor for minimum overall full scale drift.
SETTLING TIME
The AM6012 is capable of extremely fast settling
times, typically 2S0ns at IREF = 1.0mA. Judicious
circuit design and careful board layout must be employed to obtain full performance potential during
testing and application. The logic switch design
enables propagation delays of only 2Sns for each
of the 12 bits. Settling time to within 112 LSB of the
LSB is therefore 2Sns, with each progressively larger bit taking successively longer. The MSB settles in 2S0ns, thus determining the overall settling
time of 2S0ns. Settling to 1O-bit accuracy requires
about 90 to 130ms. The output capacitance of the
AM6012 including the package is approximately
20pF; therefore, the output RC time constant dominates settling time if RL > soon.
Settling time and propagation delay are relatively
insensitive to logic input amplitude and rise and fall
times, due to the high gain of the logic switches.
Settling time also remains essentially constant for
IREF values down to O.SmA, with gradual increases for lower IREF values lies in the ability to attain a given output level with lower load resistors,
thus reducing the output RC time constant.
Measurement of settling time requires the ability
to accurately resolve ± 2pA, therefore a 2.SkO load
is needed to provide adequate drive for most oscilloscopes. At IREF values of less than O.SmA, excessive RC damping of the output is difficult to
prevent while maintaining adequate sensitivity. However, the major carry from 011111111111 to
100000000000 provides an accurate indicator of
settling time. This code change does not require
the normal 6.2 time constants to settle to within
±0.1% of the final value, and thus settling times
may be observed at lower values of IREF.
AM6012 switching transients or "glitches" are very
low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time.
Fastest operation can be octained by using short
leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the
supply, reference, and VLC terminals. Supplies do
not require large electrolytic bypass capacitors as
the supply current drain is independent of input logic states; 0.1 p,F capacitors at the supply pins provide full transient protection.
AM6012-AM6012A
APPLICATION INFORMATION (Continued)
REFERENCE AMPLIFIER SETUP
The AM6012 is a multiplying DIA converter in which
the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly
zero to + 1.0mA. The full range output current is
a linear function of the reference current and is given by:
4095
IRF= --x4x(IREF)=3.999 IREF,
4096
where IREF=114
In positive reference applications, an external positive reference voltage forces current through R14
into the VREF( +) terminal (pin 14) of the reference
amplifier. Alternatively, a negative reference may
be applied to VREF( -) at pin 15. Reference current
flows from ground through R14 into VREF( +) as in
the positive reference case. This negative reference
connection has the advantage of a very high impedance presented at pin 15. The voltage at pin
14 is equal to and tracks the voltage at pin 15 due
to the high gain of the internal reference amplifier.
R15 (nominally equal to R14) is used to cancel bias
current errors. (Figure 3).
Bipolar references may be accommodated by offsetting VREF or pin 15. The negative commonmode range of the reference amplifier is given by:
VCM - = V - plus (IREF x 3ka) plus 1.SV. The positive common-mode range is V + less 1.23V.
When a DC reference is used, a reference bypass
capacitor is recommended. A 5.0V TIL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction
bypassed to ground with a 0.1,.F capacitor.
For most applications the tight relationship between
IREF and IFS will eliminate the need for trimming
IREF. If required, full scale trimming may be accomplished by adjusting the value of R14, or by
using a potentiometer for R14.
MULTIPLYING OPERATION
The AM6012 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 1mA to 1,.A.
Monotonic operation is maintained over a typical
range of IREF from 100,.A to 1.0mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to be compensated using a capacitor
from pin 16 to V - . The value of this capacitor depends on the impedance presented to pin 14. For
R14 values of 1.0, 2.5 and 5 Oka; minimum values
of Cc are 5, 12 and 25 pF. Larger values of R14
require proportionately increased values of Cc for
proper phase margin (See Figure 4 and 5).
For fastest response to a pulse, low values of R14
enabling small Cc values should be used. If pin 14
is driven be a high impedance such as a transistor
current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall compensated which
will decrease overall bandwidth and slew rate. For
R14 = 1ka and Cc = 5pF, the reference amplifier
slews at 4mAlms enabling a transition from
IREF=O to IREF= 1mA in 250ns.
Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest
full scale transition times. An internal clamp allows
quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full scale transition (0 to
1mAl occurs in 62.5ns when the equlvalent impedance at pin 14 is SOOO and Cc = O. This yields a
reference slew rate of SmAIl'S which is relatively
independent of RIN and VIN values.
LOGIC INPUTS
The AM6012 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise
immunity. This feature is made possible by the large input swing capability, 40,.A logiC input current,
and completely adjustable logic inputs may swing
between - 5 and + 1OV.
This enables direct interface with + 15V CMOS logic, even when the AM6012 is powered from a + 5V
supply. Minimum input logic swing and minimum
logic threshold may be adjusted over a wide range
by placing an appropriate voltage at the logic threshold control pin (pin 13, VLC). For TIL interface,
simply ground pin 13. When interfacing ECL, an
IREF :s; 1mA is recommended. For interfacing
other logic families, see block titled "Interfacing
with Various Logic Families". For general setup of
the logic control circuit, it should be noted that pin
13 will sink 1.1 mA typical, external circuitry should
be designed to accommodate this current (Figure 6).
7112
25
AM6012-AM6012A
Fig. 3 - Reference amplifier biasing
A14
AM6012
10 +fci - IFS
FDA ALL INPUT CODES
VINb
A1
r
V-
Reference Configuration
R14
V+
V-
A60J2-B."." LIB
R15
RIN
Cc
.01/tF
VR+/R14
-VR-/R14
IREF
Positive Reference
VR+
OV
N/C
Negative Reference
OV
VR-
N/C
.01/tF
Lo Impedance Bipolar
Reference
VR+
OV
VIN
(Note 1)
VR+/R14) + (VIN/RIN)
(Note 2)
Hi Impedance Bipolar
Reference
VR+
VIN
N/C
(Note 1)
(VR+ -VIN)/R14
(Note 3)
Pulsed Reference (Note 4)
VR+
OV
VIN
No Cap
(VR+/R14) + (VIN/RIN)
Notes:
1. The compensation capacitor a function of the impedance seen at the + VAEF input and must be at least SpF x R14(eq)
in kO. For R14 < 8000 no capacitor is necessary.
2. For negative values of VIN, VR+/R14 must be greater than -VIN MaxiRIN so that the amplifier is not turned off.
3. For positive values of VIN, VR+ must be greater than VIN Max so the amplifier is not turned off.
4. For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at pin 14
should be 8000 or less.
5. For optimum settling time, decouple V - with 200 and bypass with 22fLF tantulum capacitor.
6. Reference current and reference resistor - there is a 1 to 4 schale factor between the reference current (IREF) and
the full scale output current (lFS). If VAEF= +10V and IFS=4mA, the value of the R14 is:
8/12
26
AM6012·AM6012A
Fig. 4 - Minimum size compensation capacitor
(IFS 4mA, IREF 1.0mA)
=
=
R14(EQ)(KO)
Cc{pF)
10
1
50
25
10
5
5
0
5
2
Fig. 5 - Reference Amplifier Frequency response
I
(dB)
-1=
SMALL SIGNAL
}--
LARGE SIGNAL
3
-
/-
o
Note: A 0.01 pF capacitor is recommended for fixed reference operation.
-3
-6
k\
,,
\ \
-1
'\
\'\
I
I
R14=2K
CC= 10pF
I
0.01
1
0.1
10
(MHz)
A50J2-1f."." OI
Fig. 6 - Interfacing Circuits
Fig. 7 - Accomodating Bipolar Reference
CMOS
VREF
+
+ 15V
RREF
VIN
IREF
.p
o-~Il~·n~~1~4~~~-'
470
"A'
RIN
isla
AM6012
15'----~ 19
10
o PIN 13
510
!REF> PEAK NEGATIVE SWING OF lin
~REF
ECl
RREF 14r--~ 18
o--=---=-=j
y:.=-o
o---=---;-;:! AM60 12 /-;-;;-0
VIN HIGH INP1~T
19 10
10
(+)
-%--
IMPEDANCE
13K
VREF
-All
(+)
MUST BE ABOVE PEAK POSITIVE SWING OF VIN
o PIN 13
6.2K
- 5.2V
9/12
27
AM6012-AM6012A
Fig. 8 - AM6012 Logic Inputs
B KOhm
2 .A
--""
R1
RS
ROFF
E
RU
10 KOhm
HOV
REF
VREF
>_...._VOUT
(+)
H
R14
1.0mA
B12
RIB
10 KOhm
VREF
m
D
AM6012
G
1
OPTIONAL
(SEE CODE TABLE)
ROFF= VREF
LSB
2.0mA
Code Format
Straight bynary
one polarity
with true input
Connec.
Output
Scale
A6012-7:: LIB
LS8
MS8
10
10
Your
B1 82 83 84 85 86 87 88 89 Bl0 811 812
Positive ful! scale
Positive full scale-lSB
Zero scale
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
3.999
3.998
.000
.000
.001
3.999
9.9978
9.9951
.0000
a-g
Positive full scale
b-c
Positive full scale-LSB
R1 =R2=2.5K Zero scale
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
.000
.001
3.999
3.999
3.998
.000
9.9976
9.9951
.0000
a-c
bog
R1=R2=2.5K
code, true zero
Unipolar
output.
Complementary
binary one
polarity with
complementary
input code, true
zero output.
Symmetrical
Offset
Straight offset
binary; offset
half scale, symmetrical about
zero, no true
zero output.
a-c
bod
f-O
R1=R3=2.5K
R2=1.25K
Positive full scale
Positive full scale-LSB
( + ) Zero scale
(-) Zero scale
Negative full scale-LSB
Negative full scale
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999
3.998
2.000
1.999
.001
.000
.000
.001
1.999
2.000
3.998
3.999
9.9976
9.9927
.0024
-.0024
-9.9927
-9.9976
1's complement
a-c
bod
fog
Rl =R3=2.5K
R2=1.25K
Positive ful! scale
Positive full scale-LSB
( + ) Zero scale
(-) Zero scale
Negative full scale-LSB
Negative full scale
0
0
0
1
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
3.999
3.998
2.000
1.999
.001
.000
.000
.001
1.999
2.000
3.998
3.999
9.9976
9.9927
.0024
-.0024
-9.9927
-9.9976
offset half scale
symmetrical
about zero, no
true zero output
MSB complemented (need
inverter at B1).
Offset with
True Zero
Offset binary,
offset half
scale, true zero
output.
e-a-c
bog
Rl =R2=5K
Positive fu II scale
POSitive full scale-LSB
+LSB
Zero Scale
-LSB
Negative full scale+LSB
Negative full scale
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
_0
1
1
0
3.999
3.998
2.001
2.000
1.999
.001
.000
.000
.001
1.998
1.999
2.000
3.998
3.999
9.9951
9.9902
.0049
.000
-.0049
-9.9951
-10.000
2's complement
offset half scale
true zero output
MSB complemented (need
inverter at B1)
e-a-c
bog
Rl=R2=5K
Positive full scale
Positive full scale-LSB
+1 LSB
Zero scale
-1 LSB
Negative full scale+ LSB
Negative full scale
0
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
3.999
3.998
2.001
2.000
1.999
.001
.000
.006
.001
1.998
1.999
2.000
3.998
3.999
9.9951
9.9902
.0049
.000
-0.049
-9.9951
-10.000
ADDITIONAL CODE MODIFICATIONS
1. Any of the offset binary codes may be complemented by reversing the output terminal pair.
10/12
28
AM6012-AM6012A
Fig. 9 - Basic Negative Reference Operation
RREF
VREF (-)
~
.
R 15
Fig. 10 - Recommended Full-scale Adjustment Circuit
10
14
~18
AM6012
19
15L------~
RREF
VREF
+ 5V
4.5K
39K
10
10K
Fig. 11 - CRT Display Driver
+120V DC
"X" INPUT
"Y" INPUT
!
o
L -_ _ _ _ _ _ _ _ _ _ _ _
~
Io
-15V
-15V
~'-------------~
Io
A6012-5,' " LI
Fig. 12 - 12-BIT High-Speed AID Converter
CLOCK
LSB
+i6V
AtlAL06 IN
lo-iOVl
+ iOY
5._
IEF
!r.1IOOK
-
AM6012
COlI'
I
iGnF iuF
YI-I
iuF
YI+I
_12-11: : LIB
11112
29
AM6012-AM6012A
Fig. 13 - Interface with 8-bit Microprocessor Bus
I
7
6
5
4
3
2
1
MSB
DE
LS373
o
AM
E2
-
E1 -
I
D3A
D2A
DiA
DOA
EA
6012
EB
rr-
(l3A I-- D3B
(l2A I-- D2B
(l3B
(liA I-- DiB
(lOA
DOB
I--
(liB I--(lOB
1/2LS100
(l2B
r - LSB
1/2LS100
A6012-4.· : LIB
Fig. 14 - Interface with digital signal processor T568930/31
+lSU
r
OB-7
1BK
2B
HC374
84-2
12
30
OUT
AM6012A
11
12/12
14
AM6012
OB-
A9-11
Uref+
Us
e
TS6B93BI
31
Vref
B.lu.F
81
HCB4
3
os
E2
AS
Ei HC13B
AK
Do
1BK
8811116812-51
DAC0808
DAC0807
DAC0806
a-BIT D/A CONVERTERS
• RELATIVE ACCURACY: ±0.19% ERROR MAXIMUM (DAC0808)
• FULL SCALE CURRENT MATCH: ± 1 LSB TYP
• 7 AND 6-BIT ACCURACY AVAILABLE
(DAC0807, DAC0806)
• FAST SETTING TIME: 150 ns TYP
• NONINVERTING DIGITAL INPUTS ARE TTL
AND CMOS COMPATIBLE
• HIGH SPEED MULTIPLYING INPUT SLEW RATE: 8 mAIp,s
• POWER SUPPLY VOLTAGE RANGE: ±4.5V
to ±18V
• LOW POWER CONSUMPTION: 33 mW @ ± 5V
DIP-16 Plastic (0.25)
and Ceramic
SO-16J
PIN CONNECTION
N.C.
COMPo
GND
(-)
10
+VS
Ai
AS
A2
A7
A3
A6
A4
A5
VREF
(+) VREF
DESCRIPTION
The DAC0808 series is an 8-bit monolithic digitalto-analog converter (DAC) featuring a full scale output current settling time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference
current (IREF) trimming is required for most applications since the full scale output current is typically ± 1 LSB of 255 IREF/256. Relative accuracies
of better than 0.19% assure 8-bit monotonicity and
linearity while zero level output current of less than
4 p,A provides 8-bit zero accuracy for IREF~ 2 mA.
The power supply currents of the DAC0808 series
are independent of bit codes, and exhibits essentially constant device characteristics over the entire supply voltage range.
OACOBOB-J3
The DAC0808 will interface directly with popular
TTL, or CMOS logic levels, and is a direct replacement for the MC1508/MC1408.
June 1988
1111
31
DAC0808-0807-0806
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Vs
VEE
Digital Input Voltage V5 - V12
Reference Current, 114
Reference Amplifier Inputs, V14, V15
+18
-18
-10 V to + 18
V
V
V
5 mA
VCC, VEE
Operating Temperature Range
DAC0808L
DAC0808LC/D1
-55°CsTAS +125
OsTAS +75
Storage Temperature Range
°C
°C
-65°C to + 150°C
ORDERING INFORMATION
Temperature
range
Plastic
DIP-16
6 bit
o to 75°C
o to 75°C
o to 75°C
8 bit
-55 to 125°C
Accuracy
8 bit
7 bit
Ceramic
DIP-16
SO-16
DAC0808LCN
DAC0808LCJ
DAC0808D
DAC0807LCN
DAC0807LCJ
DAC0807D
DAC0806LCN
DAC0806LCJ
DAC0806D
-
DAC0808W
-
BLOCK DIAGRAM
+VS
Ai
A2
A3
A4
A5
A6
A7
AS
VO
+
DACOBOB-J
THERMAL DATA
Rthj-amb
2111
32
Thermal resistance junction-ambient max
Ceramic
DIP-16
50-16
Plastic
DIP-16
150 0 CIW
120°CIW
100°CIW
DAC0808-0807-0806
ELECTRICAL CHARACTERISTICS
(VS=5V, VEE= -15V, VREF/R14 = 2 mA, TA=TMIN to TMAX and aU digital inputs at high logic level
unless otherwise noted.)
Parameter
Er
tpLH
tpHL
Test Conditions
Propagation Delay Time
Digital Input Logic Levels
High Level, Logic "1"
Low Level, Logic "0"
(Figure 9)
MSB
Digital Input Current
High Level
Low Level
(Figure 9)
VIH=5V
VIL=O.BV
Reference Input Bias Current
Output Current Range
(Figure 3)
(Figure 9)
VEE = -5V
VEE= -15V, TA=25°C
Output Current
Output Current, All Bits Low
Output Voltage Compliance
VEE = -5V
VEE Below -10V
VREF=2.000V.
R14= 10000
(Figure 9)
(Figure 9)
Er sO.19%, TA=25°C
(Figure 14)
-5VSVEES -16.5V
Power Supply Current (All Bits Low)
Is
lEE
(Figure 9)
Power Supply Voltage Range
Vs
VEE
TA = 25°C (Figure 9)
All Bits High
±0.19
±0.39
±0.7B
%
%
%
ns
100
ns
150
30
ppm/oC
O.B
VDC
VDC
0
-0.003
0.040
-O.B
rnA
rnA
-1
-3
p.A
0
0
2.0
2.0
2.1
4.2
rnA
rnA
1.9
1.99
0
2.1
4
rnA
-0.55,+0.4
-5.0 ,+0.4
V
V
2.7
mAIlLS
p.A/V
4
B
0.05
2.3
-4.3
5.0
4.5
-4.5 -15
Vs = 5V.VEE = -5V
Vs=5V.VEE= -15V
Vs=15V.VEE= -5V
Vs=15V.VEE= -15V
Unit
%
2
SRIREF Reference Current Siew Rate
Output Current Power Supply
Sensitivity
Power Dissipation
All Bits Low
Max.
±20
Output Full Scale Current Drift
MSB
VIH
VIL
'0
Typ.
TA=25°C (Figure 11)
TClo
115
Min.
Relative Accuracy (Error Relative (Figure 10)
to Full Scale '0)
DACOBOBL
DACOB07LCID1
(Note 1)
DACOB06LCIDl
(Note 1)
Settling Time to Within 1/2 LSB TA=25°C (Note 2)
(Figure 11)
(Includes tpLH)
33
106
90
160
22
-13
5.5
-16.5
170
305
p.A
rnA
V
rnW
rnW
rnW
rnW
Note 1: All current switches are tested to guarantee at least 50% of rated current.
Note 2: All bits switched.
Note 3: Range control is not required.
3/11
33
DAC0808-0807-0806
Fig. 1 - Supply Current vs
Temperature
Fig. 2 - Supply Current vs Supply
Voltage (VEe)
Icc
(mA) HALL 8ITS HIGH OR LOW ~
8
114 2mA
Icc
, .', '
,
8
6
Icc
(mA) HALL 8ITS HIGH OR LOW
ALL 8ITS HIGH OR LOW
(mA)
I~E
6
Fig. 3 - Supply Current vs Supply
Voltage (Vs)
'
, ,
" A) i - i - lEE (114 -2m
-
"
6
r- lEE (114 -1mA) r- -
4
4
2
o
0
50
.~
4
8
12
2
-
I
I
I 14 =2mA
-8 -4
0
4
8
'l
(V)
16
V=-5
o
1--';1
-4
0
4
8
1211L (V
A3
A4
A5
Fig. 8 - Frequency response
34
SHADED AREA
rr-
4/11
I
!I
114- 2 mA
1114.)mA
1.2
INDICATES
PERMISSIBLE OUTPUT
VOLTAGE RANGE FOR
VEE--15V. I 14-2mA
i -i -
r- ri - r-
~~ ~ ~ ~ ~~
-50
o
50
1 0 0 T A (. C)
o
-4
-8
0.8
rJo.kmA
0.4
o
-14 -10 -6 -2
2
6
10 Vo (V)
Unless otherwise specified: R14 =
R15=1 kO,C=15pF, pin 16 to VEE;
RL =500, pin 4 to ground.
Curve A: Large Signal Bandwidth
Method of Figure 7, VREF=2 Vp-p
offset 1 V above ground
4
0:: 10: ~ ~ ~
-16
VEE--15V VEI'=-5V
2
(dB)
Vo
-8
J
2.4
1.6
A2
(V)
o i-
ALL 8ITS "ON
0.4
Fig. 7 - Output Voltage Compliance
vs Temperature
8
Vs (V)
10
(mA)
0.2
o
12
10
0.6
I
8
Fig. 6 - Output Voltage Compliance
0.8
Ai THROUGH A8
4
VEE (V)
Ai
-
-2mA) r-r- IS", (I, 14
"( , ,
Fig. 5 - Bit Transfer Characteristics
(rnA)
4
-
2
100 T A('C)
Fig. 4 - Logic Input Current vs
Input Voltage
r- lEE (I 14=2mA) r- -
!::= -
I'
"
-50
4
(1 14 -0. 2mA)
' - - IE
2
IS
f
8
........
/"" .........
i'... ~
\ ,\
-12
-16
0.1 0.2 0.5 1
\
B
A
\c
2
(MHz)
Curve B: Small Signal Bandwidth
Method of Figure 7, RL = 2500,
VREF=50 mVp-p offset 200 mV
above ground.
Curve C: Large and Small Signal
Bandwidth Method of Figure 9 (no
op amp. RL = 500), Rs = 500,
VREF= 2V, Vs = 100 mVp-p centered
at av.
DAC0808-0807~0806
Test Circuits
FIGURE 9. Notation Definitions
+VS
13
The resistor tied to pin 15 is to temperature compensate the bias current and may not be necessary for all applications.
VREF
A2
A3
IO=K(A1+A2+A3+A4+A5+A6+A7 +A8)
2
4
8 16 32 64 128 256
A4
A5
A6
A7
VREF
where K == R14
and AN = "1" if AN is at high level
AN = "0" if AN is at low level
FIGURE 10. Relative Accuracy
Ai
rfr=§~~ 12 BIT I-v_o--o0_t...,o 10V
o to
A
50 Kohm
AB
8 BIT H:>-----'I-H++-o-:o-I
COUNTERI-o---++I-+-<~
OAC0808-4
5111
35
DACOBOB-OB07-0B06
FIGURE 11. Transient Response and Settling Time
FIGURE 12. Positive VREF
./
FIGURE 13. Negative VREF
+Vs
VREF
...JL
A2
A2
A3
A4
A3
A4
A5
A5
A6
6/11
36
vo
L..r
A6
A7
A7
-VEE
-VEE
vo
L..r
DAC0808-0807-0806
FIGURE 14. Reference Current Slew Rate Measurement
n
The reference amplifier provides a voltage at pin
14 for converting the reference voltage to a current, and a turn-around circuit or current mirror for
feeding the ladder. The reference amplifier input
current, 114, must always flow into pin 14, regardless of the set-up method or reference voltage polarity.
------ 2V
L
...J
---- 0
DAC H-r:...:=~
:..
TO
SCOPE
-VEE
3
15 pF
1--- 0
,:~
, -----2
I
ts
REFERENCE AMPLIFIER DRIVE AND COMPENSATION
rnA
I
OAC08fl8-5
Connections for a positive voltage are shown in Figure 12. The reference voltage source supplies the
full current 114. For bipolar reference signals, as
in the multiplying mode, R15 can be tied to a negative voltage corresponding to the minimum input level. It is possible to eliminate R15 with only
a small sacrifice in accuracy and temperature drift.
The compensation capacitor value must be increased with increases in R14 to maintain proper phase margin; for R14 values of 1, 2.5 and 5 kO,
minimum capacitor values are 15,37 and 75 pF.
The capacitor may be tied to either VEE or ground,
but using VEE increases negative supply rejection.
APPLICATION INFORMATION
CIRCUIT DESCRIPTION
The DAC0808 consists of a reference current amplifier, an R-2R ladder, and eight high-speed current switches. For many applications, only a
reference resistor and reference voltage need be
added.
The switches are noninverting in operation, therefore a high state on the input turns on the specified output current component. The switch uses
current steering for high speed, and a termination
amplifier consisting of an active load gain stage
with unity gain feedback. The termination amplifier holds the parasitic capacitance of the ladder
at a constant voltage during switching and provides a low impedance termination of equal voltage
for all legs of the ladder.
The R-2R ladder divides the reference amplifier current into binarily-related components, which are fed
to the switches. Nota that there is always a remainder current which is equal to the last significant bit.
This current is shunted to ground, and the maximum output current is 255/256 of the reference amplifier current, or 1.992 mA for a 2.0 mA reference
amplifier current if the NPN current source pair is
perfectly matched.
A negative reference voltage may be used if R14
is grounded and the reference voltage is applied
to R15 as shown in Figure 13. A high input impedance is the main advantage of this method. Compensation involves a capacitor to VEE on pin 16,
using the values of the previous paragraph. The
negative reference voltage must be at least 3V above the VEE supply. Bipolar input signals may be
handled by connecting R14 to a positive reference voltage equal to the peak positive input level at
pin 15.
When a DC reference voltage is used, capacitive
by pass to ground is recommended. The 5V logic
supply is not recommended as a reference voltage. If a well regulated 5V supply which drives logic is to be used as the reference, R14 should be
decoupled by connecting it to 5V through another
resistor and bypassing the junction of the 2 resistors with 0.1 p,F to ground. For reference voltages
greater than 5V, a clamp diode is recommended
between pin 14 and ground.
If pin 14 is driven by a high impedance such as a
transistor current source, none of the above compensation methods apply and the amplifier must
be heavily compensated, decreasing the overall
bandwidth.
7/11
37
DAC0808-0807-0806
OUTPUT VOLTAGE RANGE
The voltage on pin 4 is restricted to a range of - 0.6
to 0.5V when VEE = - 5V due to the current switching methods employed in the DAC0808.
The negative output voltage compliance of the
DAC0808 is extended to - 5V where the negative
supply voltage is more negative than -1 OV. Using
a full-scale current of 1.992 mA and load resistor
of 2.5 kO between pin 4 and ground will yield a voltage output of 256 levels between 0 and - 4.980V.
Floating pin 1 does not affect the converter speed
or power dissipation. However, the value of the load
resistor determines the switching time due to increased voltage swing. Values of RL up to 5000
do not significantly affect performance, but a 2.5
kO load increases worst-case setting time to 1.2 pS
(when all bits are switched ON). Refer to the subsequent text section on Settling Time for more details output loading.
OUTPUT CURRENT RANGE
The output current maximum rating of 4.2 mA may
be used only for negative supply voltages more negative than - 7V, due to the increased voltage drop
across the resistors in the reference current amplifier.
ACCURACY
Absolute accuracy is the measure of each output
current level with respect to its intended value, and
is dependent upon relative accuracy and full-scale
current drift. Relative accuracy is the measure of
each output current level as a fraction of the fullscale current. The relative accuracy of the
DAC0808 is essentially constant with temperature due to the excellent temperature tracking of the
monolithic resistor ladder. The reference current
may drift with temperature, causing a change in
the absolute accuracy of output current. However,
the DAC0808 has a very low full-scale current drift
with temperature.
The DAC0808 series is guaranteed accurate to within ± 1/2 LSB at a full-scale output current of 1.992
mA. This corresponds to a reference amplifier output current drive to the ladder network of 2 mA, with
the loss of 1 LSB (8 pAl which is the ladder remainder shunted to ground. The input current to pin 14
has a guaranteed value of between 1.9 and 2.1 mA,
allowing some mis-match in the NPN current source pair. The accuracy test circuit is shown in Figure 10. The 12-bit converter is calibrated for a
full-scale output current of 1.992 mA. This is an optional step since the DAC0808 accuracy is essentially the same between 1.5 and 2.5 mAo
8111
38
Then the DAC0808 circuits' full-scale current is
trimmed to the same value with R14 so that a zero
value appears at the error amplifier output. The
counter is activated and the error band may be displayed on an oscilloscope, detected by comparators, or stored in a peak detector.
Two 8-bit D-to-A converters may not be used to construct a 16-bit accuracy D-to-A converter. 16-bit accuracy implies a total error of ± 1/2 of one part in
65,536, or ±0.00076%, which is much more accurate than the ±0.019% specification provided
by the DAC0808.
MULTIPLYING ACCURACY
The DAC0808 may be used in the multiplying mode with 8-bit accuracy when the reference current
is varied over a range of 256:1. If the reference current in the multiplying mode ranges from 16 pA to
4 mA, the additional error contributions are less
than 1.6 pA. This is well within 8-bit accuracy when
referred to full-scale.
A monotonic converter is one which supplies an
increase in current for each increment in the binary word. Typically, the DAC0808 is monotonic for
all values of reference current above 0.5 mAo The
recommended range for operation with a DC reference current is 0.5 to 4 mAo
SETTLING TIME
The "worst case" switching condition occurs when
all bits are switched "on", which corresponds to
a low-high transition for all bits. This time is typically 150 ns for settling to within ± 1/2 LSB for 8-bit
accuracy and 100 ns to 1/2 LSB for 7 and 6-bit accuracy. The turn off is typically under 100 os. These timers apply when RL ,.; 500 ohms and Co ,.; 25
pF.
The test circuit of Figure 11 requires a smaller voltage swing for the current switches due t~ internal
voltage clamping in the DAC0808 A 1.o-kilohr:n load
resistor from pin 4 to ground gives a typical settling time of 200 ns.
Thus, it is voltage swing and not the output RC time constant that determines setting time for most
.applications.
Extra care must be taken in board layout since this
is usually the dominant factor in satisfactory test
results when measuring settling time.
Short leads, 100 p.F supply bypassing for low frequencies, and minimum scope lead length are all
mondatory.
DAC0808-0807-0806
PROGRAMMABLE GAIN AMPLIFIER OR DIGITAL ATTEPUATOR
When used in the multiplying mode can be applied
as a digital attenuator. See Figure 15. One advantage of this technique is that if RS = 50 ohms, no
compensation capacitor is needed. The small and
large signal band are now identical and are shown
in Figure BC.
The best frequency response is obtained by not allowing 114 to reach zero. However, the high impedance node, pin 16, is clamped to prevent
saturation and insure fast recovery when the current through A14 goes to zero. AS can be set for
a : 1.0 mA variation in relation to 114. 114 can never be negative.
The output current is always unipolar. The quiescent dc output current level changes with the digital word which makes accoupling necessary.
CURRENT TO VOLTAGE CONVERSION
Voltage output of a larger magnitude are obtainable with the circuit of fig. 16 which uses an external operational amplifier as a current to voltage
converter. This configuration automatically keeps
the output of the DACOBOB ground potential and
the operational amplifier can generate a positive
voltage limited only by its positive supply voltage.
Frequency response and setting time are primarily determined by the characteristics of the operational amplifier. In addition, the operational amplifier
must be compensated for unity gain, and in some
cases over compensation may be desirable.
Note that this configuration results in a positive output voltage only, the magnitude of which is dependent on the digital input. The LM301 can be used
in a feedforwerd mode resulting in a full scale setting time on the order of 2.0 p.s.
COMBINED OUTPUT AMPLIFIER AND VOL TAGE REFERENCE
For many of its applications the DACOBOB requires a reference voltage and an operational amplifier. Normally the operational amplifier is used as
a current to voltage converter and its output need
only go positive. With the popular LM723 voltage
regulator both of these functions are provided in
a single package with the added bonus of up to 150
mA output current. See Figure 17. The reference
voltage is developed with respect to the negative
voltage and appears as a common-mode signal to
the reference amplifier in the D-to-A converter. This
allows use of its amplifier as a classic current-tovoltage converter with the non-inverting input
grounded.
Since: 15V and + 5.0V are normally available in
a combination digital-to-analog system, only the
-5.0 V need be developed. A resistor divider is
sufficiently accurate since the allowable range on
pin 5 is from - 2.0 to - B.O volts. The 5.0 kilohm
pulldown resistor on the amplifier output is necessary for fast negative transitions.
Full scale output may be increasing AO and raising
the + 15V supply voltage to 35 V maximum. The
resistor divider should be altered to comply with
the maximum limit of 40 volts across the LM723
Co may be decreased to maintain the same AOCo product if maximum speed is desired.
PROGRAMMABLE POWER SUPPLY
The circuit of figure 17 can be used as a digitally
programmed power supply by the addition of
thumb-wheel switches and a BCD-to-binary converter. The output voltage can be scaled in several ways, including 0 to +25.5 volts in 0.1 -volt
increments, :10 mY.
PANEL METER READOUT
The DACOBOB can be used to read out the status
of BCD or binary registers or counters a digital control system. The current output can be used to drive directly an analog panel meter. External meter
shunts may be necessary if a meter of less than
20 mA full scale is used. Full scale calibration can
be done by adjusting A14 or Vref (see fig. 1B).
CHARACTER GENERATOR
In a character generation system fig. 19 one
DACOBOB circuit uses a fixed reference voltage and
its digital input defines the starting point for a stroke. The second converter circuit has a ramp input
for the reference and its digital input defines the
slope of the stroke. Note that this approach does
not result in a 16-bit D-to-A converter (see Accuracy Section).
9/11
39
DAC0808-0807-0806
TWO-DIGIT BCD CONVERSION
Two 8-bit, O-to-A converters can be used to build
a two digit BCD O-to-A or A-to-O converter (fig. 21).
If both outputs feed the virtual ground of an operational amplifier, 10:1 current scaling can be achieved with a resistive current divider. If current output is desired, the units may be operated at full
scale current levels of 4.0 mA and 0.4 mA with the
outputs connected to sum the currents. The error
of the O-to-A converter handling the least significant bits wi" be scaled down by a factor of ten and
thus an OAC0806 may be used for the least significant word.
FIGURE 15. Programmable Gain Amplifier or Digital
Attenuator Circuit
Vsense
RS
14
14
VREF
When Vs=O. 1)4=2.0mA
Vo= (VrOf + Vs (AJR
R14 Rs
0
FIGURE 16.
m-oVREF-10V
H:>-=C:FA2
A3
A4
A5
A6
Al
A2
Vo=10V ( - + + ... -AS)
2
4
256
FIGURE 17. Combined output amplifier and voltage
reference circuit
FIGURE lS. Panel meter readout circuit
RO - 51<
CO
+5V
25pF
VREF
'"l
-15V
10/11
40
-VEE 0-......- - '
DIGITAL WORD FROM COUNTER/REGISTER
DAC0808-0807-0806
FIGURE 19. Digital summing and character generation
+v.
r
A
Vo= [Vref1 IAI+ Vref2IBI]RO
R14,
Rl~
L
FIGURE 20. Analog product of two digital words (High Speed Operation)
Vo= -101 RO= Vrel IAI RO
R14,
+v.
r
Vo
102=IBI IVol
Rl~
A
L
=~
[R (Vre!
R142
0 R14,
) IAI]
Since Ro = Rl~ and K = Vrel
R141
_-=-__-' OAC0808-J2
-VEE o---<>""'------<~--I-L.._-_-_-_-_-_-_-_<':_";_~_-
102 = K (AI (Bl
IK can be an analog variable
FIGURE 21. Two-cligit BCD conversion
(*) MOST SIGNIFICANT BCD WORD
(**) LEAST SIGNIFICANT BCD WORD
11/11
41
L272
L272M
DUAL POWER OPERATIONAL AMPLIFIERS
• OUTPUT CURRENT TO 1A
• OPERATES AT LOW VOLTAGES
• SINGLE OR SPLIT SUPPLY
•
The high gain and high output power capability
provide superior performance whatever an opera·
tional amplifier/power booster combination is
required.
LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE
• GROUND COMPATIBLE INPUTS
•
LOW SATURATION VOLTAGE
• THERMAL SHUTDOWN
The L272 and L272M are monolithic integrated
circuits in powerdip and minidip packages in·
tended for use as power operational amplifiers in
a wide range of applications including servo ampli·
fiers and power supplies, compact disc, VCR, etc.
Powerdip (8 + 8)
Minidip Plastic
ORDERING NUMBERS:
L272
L272M
ABSOLUTE MAXIMUM RATINGS
V.
VI
VI
10
Ip
Ptot
Tstg,
lj
Supply voltage
Input voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 80°C (L272), Tamb = SO°C (L272M)
T case = 7SOC (L272)
Storage and junction temperature
28
V.
± V.
1
1.S
1
S
-40 to 1S0
V
A
A
W
W
°c
BLOCK DIAGRAM
4.9.16
L272
L272M
1/6
43
L272-L272M
CONNECTION DIAGRAM
(Top view)
OUTPUT 1
OUTPUT 2
1
3
GND
INPUT ~2
5
INPUT.2
16
GND
15
GNO
14
GNO
13
GNO
12
GND
11
GND
OUTPUT I
8
INPUT-l
7
INPUT.I
OUTPUT 2
6
INPUT.2
GND
5
INPUT_2
SUPPLY VOLTAGE
2
L272M
10 GND
9
INPUT-I
GNO.
L272
SCHEMATIC DIAGRAM (one only)
r-------------~--------~--~--~----~--_o.~
.In
out
-Vs
So-S90t,l1
THERMAL DATA
Thermal resistance junction-pins
Thermal resistance junction-ambient
*
Minidip
15°C/W
70°C/W
*70°C/W
100°C/W
Thermal resistance junction-pin 4
~2/~6_________________________
44
max
max
Powerdip
~1~~~~~~~
___________________________
L272- L272M
ELECTRICAL CHARACTERISTICS (V, = 24V,
Parameter
Vs
Supply voltage
I,
Quiescent drain current
Tamb
= 25°C unless otherwise specified)
Test Conditions
Min.
Typ.
Max.
Unit
28
V
8
12
mA
7.5
11
mA
4
=
V0
, = 24V
V , = 12V
V
V,
2
Ib
Input bias current
0.3
2.5
IlA
Vos
I nput offset voltage
15
60
mV
los
Input offset current
50
250
nA
SR
Slew rate
B
Gain-bandwidth product
R,
I nput resistance
Gv
O. L. voltage gain
1
VIlls
350
KHz
Kn
500
f
=
100Hz
70
dB
f
=
1KHz
50
dB
60
eN
Input noise voltage
B
=
20KHz
10
IlV
IN
Input noise current
B
=
20KHz
200
pA
CRR
Common Mode rejection
f
=
1 KHz
60
75
dB
SVR
Supply voltage rejection
54
70
62
56
dB
dB
dB
23
22.5
V
V
60
60
dB
dB
0.5
%
145
°c
f = 100Hz
RG = 10Kn
V R = 0.5V
Vo
Cs
Vs
Vs
Vs
=
=
=
24V
±12V
± 6V
Ip
Ip
=
=
0.1A
0.5A
Output voltage swing
Channel separation
d
Distortion
T,d
Thermal shutdown
junction temperature
f
= 1KHz;
f = 1 KHz
Vs = 24V
RL = 10n; G v = 30dB
, Vs = 24V
Vs = ± 6V
Gv
RL
= 30dB
= 00
21
___________________________ ~~~~~~~~:~~~ ________________________~3/~6
45
L272- L272M
Fig. 2 -- Quiescent drain
current vs. temperature
Fig. 1 - Quiescent current
vs. supply voltage
Fig. 3 - Open loop voltage
gain
G-61%0
6-'1'9
ID
Id
, mA
'mA )
-
'dB
H-+4-H++-H-+-H-++_H
,---- -
Vs =24V
80
10
'\.
'70
I'\.
f..-"""-
/V"
50
"\,
"- "\
r- - r-
40
"I"
20
10
12
16
20
24
- 20
Fig. 4 - Output voltage
swing vs. load current
20
40
60
BO
10
TpIN"rC)
10'
"
Fig. 6 - Supply voltage
rejection vs. frequency
Fig. 5 -- Output voltage
swing vs. load current
G-6'22
(V)
(dB)
(V)
Ys-:!:.12Y
'90
Vs=±12Y.
'Is. ±12V
REF. INPUT (G y "'10 )
,80
-12
-11
11
--r- -
70.
---r-....
80
":-.;..
00
I'
4.
-10
30'
20
200
400
200
600
400
600
,-
Fig. 7 - Channel separation
vs. frequency
10
10'
10'
Fig. 8 - Common mode
rejection vs. frequency
G-612$
Vs '" +6V
(dB
(d 8)
H-++HlHI-+-++Iiffit--+..,c'-,.LJ2!f!4V~++jHifHl
80
H"!'tmttl-lod:tlfttlf-+++tltllf--+tttlllll
40 r-+_~-4--+-+--+-t--1
60
H-+tft!lll-++HfttIf-+++tltllf--'k:Ht1llll
1-+--+-+-+-+--+-+----1
50
111;i" ,
r-, ! TfT"';t)--i-H-ljIff-++HfHIf--+++I'1tIlI
G v" 30 dB
70
__________ Vo::z2V~_+_-+_t-+__1
60
I-t--+-/-::±.--I-d-,-+-+--i
50 r-+_~-4--+-+-~-t--1
30
40
f-tt1fi' ,-!-t+H.\\lf--HrHllIII--H-H+1llI
I
10
46
10'
10'
10'
f (Hz)
10
I:
'
-!-HfttIf-+++tltllf--+tttHlil
10'
10'
f (Hz)
L272- L272M
APPLICATION SUGGESTION
NOTE
In order to avoid possible instability occurring
into final stage the usual suggestions for the
linear power stages are useful, as for instance:
- layout accuracy;
A 100nF capacitor corrected between supply
pins and ground;
boucherot cell (0.1 to 0.21lF + 111 series) bet·
ween outputs and ground or across the load.
Fig. 9 - Bidirectional DC motor control with IlP compatible inputs
VS1 = logic supply voltage
Must be VS2
> VS1
E1, E2 = logic inputs
S_5931/1
Fig. 10 - Servocontrol for compact-disc
REFLECTED
BEAM
LASER
5-941511
Fig. 11 - Capstan motor control in video recorders
OIGITAL
INPUT
------------- ~ ~~t;JtI~~ ____________5-'--/6
47
L272-L272M
Fig. 12 - Motor current control circuit
.24Y
2.SKO
R7
R8
3.3KO
13KO
2.,.
2.,.
RS
36KO
10M 2.,.
2.SKO
51_SUO 11
Note: The input voltage level is compatible with L291 (S-BIT D/A converter)
Fig. 13 - Bidirectional speed control of DC motors.
For circuit stability ensure that Rx>
2R~
0
R1 where RM = internal resistance of motor. The voltage
M
2R 0 R1 and
available at the terminals of the motor is VM = 2 ( VI _ V25 ) + I Ro I. I M where I Ral
Rx
1M is the motor current.
Rx
Vin
Rl
10KO
10M
51-590912
""6/'""6_ _ _ _ _ _ _ _ _ _ _ _ ~ 1~~~mtll9@~
48
-------------
L272D
DUAL POWER OPERATIONAL AMPLIFIER
ADVANCE DATA
•
•
OUTPUT CURRENT TO 1A
OPERATES AT LOW VOLTAGES
•
•
SINGLE OR SPLIT SUPPLY
LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE
•
•
GROUND COMPATIBLE INPUTS
LOW SATURATION VOLTAGE
•
THERMALSHUTDWON
cations including servo amplifiers and power
supplies, compact disc, VCR, etc. The high gain
and high output power capability provide superior performance wheatever an operational
amplifier/power booster combination is required.
SO-16J
The L272D is a monolithic integrated circuit
in SO-16 packages intended for use as power
operational amplifier in a wide range of appli-
ORDERING NUMBER: L272D
ABSOLUTE MAXIMUM RATINGS
Supply voltage
I nput voltage
Differential input voltage
DC Output current
Peak output current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature
Vs
Vi
Vi
10
Ip
Ptot
T stg , Tj
28
Vs
± Vs
1
1.5
1.2
-40 to 150
V
A
A
W
°C
CONNECTION DIAGRAMS
N.C.
I
N.C.
OUTPUT 1
2
.I 3
16
N.C.
15
N. C,
14~
INPUT-I
SUPPLY VOll
4
13
INPUT+l
OUTPUT 2
5
12
INPUT+2
GND
6
11
INPUT-2
N.C.
7
10
N.C.
8
9
N.C.
N.C.
I
5-10671
June 1988
5-10678
1/4
This is advanced information on a "new product now in development or undergoing evaluation. Details are subject to change without notice.
49
L272D
SCHEMATIC DIAGRAM (one only)
,Vs
~----------~--------~--~--~----~---~
out
-Vs
S_!t90,/1
THERMAL DATA
Rthj-alumlna(*)
Thermal resistance junction-alumina
max 50
(*) Thermal resistance junctions-pins with the chip soldered on the middle of an alumina supporting substrate measuring
15 x 20 mm; 0.65 mm thickness and infinite heathsink.
~2/~4________________________ ~~~t~~~~~
50
__________________________
L272D
ELECTRICAL CHARACTERISTICS (Vs = 24V,
Parameter
Vs
Supply voltage
Is
Quiescent drain current
Tamb
= 25°C unless otherwise specified)
Test Conditions
Min.
Max.
Unit
28
V
8
12
rnA
7.5
11
mA
Typ.
4
= ~
V0
Vs
= 24V
Vs
=
2
12V
Ib
Input bias current
0.3
2.5
/lA
Vos
Input offset voltage
15
60
mV
los
Input offset current
50
250
nA
SR
Slew rate
B
Gain-bandwidth product
RI
I nput resistance
Gy
O.L. voltage gain
f
=
100Hz
350
KHz
Kn
f
=
70
dB
1KHz
50
dB
10
/lV
200
pA
60
75
dB
54
70
62
56
dB
dB
dB
23
22.5
V
V
60
60
dB
dB
0.5
%
145
°c
Input noise voltage
B
= 20KHz
IN
Input noise current
B
=
CRR
Common Mode rejection
f = 1 KHz
SVR
Supply voltage rejection
60
20KHz
f = 100Hz
RG = 10Kn
VR = 0.5V
V s = 24V
V 5 = ±12V
V s = ± 6V
Output voltage swing
Ip = O.lA
Ip = 0.5A
Cs
V//ls
500
eN
Vo
1
Chan nel separation
d
Distortion
Tsd
Thermal shutdown
junction temperatu re
21
f= 1KHz; RL = 10n; Gy =30dB
Vs = 24V
Vs = ± 6V
f = 1 KHz
Vs = 24V
__________________________
Gy = 30dB
RL = 00
~!~~~~~~~~~
______________________
~3~~
51
L272D
(,-
(mA
' --
.-
/
f-j
...... ........ ,...-
"..,..
Fig. 3 - Open loop voltage
gain
G
Fig. 2 - Quiescent drain
current vs. temperature
Fig. 1 - Quiescent current
vs. supply voltage
11
~6!20
IdrT-rT<-''-,,-r,-,,-r~r.
(dB
(mAH-++-H++-H-+-H-++H
"Is'" 24,,-vH -++-H -l
-
r-- -
80
50
"
40
r-- ; - -
70
I'\.
60
I'\.
I'\.
"-
30
'0
I'\.
"-
10
12
16
20
2"
-20
Fig. 4 - Output voltage
swing vs. load current
20
40
60
60
10
TpIN,,(OC)
Fig. 6 - Supply voltage
rejection vs. frequency
Fig. 5 -- Output voltage
swing vs. load current
G-6122
(V,
(dB
(V,
1--.
Ys=!12Y
-12
12
1""-
-11
--
-
..
80
-
--
. io
60
I---.
=
so
"'-
..... ,
'0
-10
10
Ys" :tllV
REF. INPUT (G y "10 )
I-
11
,
90
Vs ,,±12V
."
"
"\
10'
30
20
200
,00
600
'00
iLOAD(rnA)
1,00
600
Fig. 7 - Channel separation
vs. frequency
(dB'
60
60
70
-+-f---+-----l-----j
30
;
:
1
10
10'
' _ _ _ -+-_~_
10'
10'
. __ ._
~
f (Hz)
H-t+tttttI-+'++IftIIt-t,.u..;I;';f,t-I!
i-++ttttt!!
, ~-4. 'Ll'r';V I I
~:;~~:t;;Li-f+1'1It1;1!r-'--j-'Hi1 f--~-t+H+HtI
I
1 lt'
1--rt-H4+'-~
'-iLl. ' ,
IT ~ - •"+til'--H-Httt!I-'k1
"-f+ttt!I
+t-Hi1ltt--i-rtHltII
1-' .. ---40
~~~'--~;-4-+I++,+t1tI--++J
10
~4/~4_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~1~~~~~~~
52
, (Hz)
: 5~~=~-\tjt':!t-,
:
-t-t·+t-~----j
I
10'
Fig. 8 - Common mode
rejection vs. frequency ,_ ""
70
50
10'
10
10'
10 4
I (Hz)
--------------------------
L293B
L293E
PUSH-PULL FOUR CHANNEL DRIVERS
•
OUTPUT CURRENT 1A PER CHANNEL
•
PEAK OUTPUT CURRENT 2A PER CHAN~
NEL (NON REPETITIVE)
•
INHIBIT FACILITY
•
HIGH NOISE IMMUNITY
The L293B and L293E are packaged in 16 and 20pin plastic DIPs respectively; both use the four
center pins to conduct heat to the printed circuit
board.
• SEPARATE LOGIC SUPPLY
•
OVERTEMPERATURE PROTECTION
The L293B and L293E are quad push-pull drivers
capable of delivering output currents to 1A per
channel. Each channel is controlled by a TTLcompatible logic input and each pair of drivers
(a full bridge) is equipped with an inhibit input
which turns off all four transistors. A separate
supply input is provided for the logic so that
it may be run off a lower voltage to reduce
dissipation.
Additionally, the L293E has external connection of sensing resistors, for switch mode control.
DIP-16 Plastic
(0.4)
Powerdip
16+2+2
ORDERING NUMBERS: L293B (16 leads)
L293E (20 leads)
ABSOLUTE MAXIMUM RATINGS
Vs
Vss
Vi
V 1nh
lout
Ptot
Tstg' Tj
Supply voltage
Logic supply voltage
Input voltage
Inhibit voltage
Peak output current (non-repetitive t = 5ms)
Total power dissipation at TgrOUnd-Pins= 80°C
Storage and junction temperature
·DC motor control
June 1988
36
36
7
7
2
5
-40 to 150
V
V
V
V
A
W
°C
Bidirectional DC motor control
1/8
53
L2938 - L293E
CONNECTION AND BLOCK DIAGRAM (L293)
(top view)
CHIP ENABLE 1
16
Vss
INPUT 1
15
INPUT 4
OUTPUT 1
14
OUTPUT 4
GNO
13
GNO
GNO
12
GNO
OUTPUT 2
11
OUTPUT 3
INPUT
10
INPUT 3
2
9
Vs
CHIP ENABLE 2
's
5-4169
CONNECTION AND BLOCK DIAGRAM (L293E)
(top view)
CHIP ENABLE 1
1
INPUT 1
V,.
INPUT 4
OUTPUT 1
OUTPUT'
SENSE 1
SENSE 4
GND
GND
GND
GNO
SENSE 2
SENSE 3
OUTPUT 2
OUTPUT 3
INPUT 2
V,
INPUT 3
10
.V,
2/8
54
SCHEMATIC DIAGRAM
.--------11::
T2
T3
~
I~
~cn
§g
II
~z
~.22
,~
®
"9)
T28
~
.v
(2)
g:
~
0)
..
• I
~
,,2)
I
l
@@
r-
,,4)"3) "eX'7)
(*) In the L293 these points are not externally available. They are internally connected to the ground (substrate).
o Pins of L293
() Pins of L293E
N
I.
5 - 5184
<0
W
aJ
I
r-
N
<0
W
m
L293B - L293E
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
max
max
14
80
ELECTRICAL CHARACTERISTICS (For each channel, Vs= 24V, Vss= 5V, T amb = 25°C,
unless otherwise specified)
Test conditions
Parameter
Min.
Typ.
Max.
Unit
Vs
Supply voltage
Vss
36
V
Vss
Logic supply voltage
4.5
36
V
Is
Total quiescent supply
current
Iss
Total quiescent logic
supply current
V iL
I nput low voltage
V iH
I nput high voltage
Vi = L
10=0
V lnh = H
2
6
Vi = H
10 = 0
Vinh= H
V lnh = L
16
24
VI = L
10 = 0
V inh = H
44
Vi = H
10 -0
Vlnh- H
16
22
V inh - L
16
24
60
-0.3
1.5
V ss " 7V
2.3
Vss
> 7V
2.3
7
V ss
IlL'
Low voltage input current
V IL = 1.5V
liH
V inhL
High voltage input current
2.3V .;;; ViH .;;; Vss -0.6V
I nh ibit low voltage
V inhH
Inhibit high voltage
mA
4
mA
V
V
-10
IJA
100
IJA
-0.3
1.5
V
Vss .;;; 7V
2.3
> 7V
2.3
Vss
7
V
-100
IJA
± 10
IJA
Vss
IlnhL
Low voltage inhibit current
V.lnhL - 1.5V
linhH
High voltage inhibit
current
2.3V .;;; VinhH .;;; Vss -0.6V
30
-30
VCEsatH Source output saturation
voltage
10 --1A
1.4
1.8
V
VCEsatL Sink output saturation
voltage
10 = 1A
1.2
1.8
V
2
V
VSENS
Sensing Voltage
(pins 4, 7,14,17) (**)
tr
Rise time
0.1 to 0.9 Vo (*)
250
ns
tf
Fall time
0.9 to 0.1 Vo (*)
250
ns
ton
Turn-on delay
0.5 VI to 0.5 Vo (*)
750
ns
toff
Turn-off delay
0.5 VI to 0.5 Vo (*)
200
ns
(*) See fig. 1.
(**) Referred to L293E .
....;4/_8_ _ _ _ _ _ _ _ _ _ _
56
;::u, I~mg~~©~ ------------
L293B- L293E
TRUTH TABLE
Fig. 1 - Switching times
I
!
Vi (each channell
Vinh. (00)
Vo
H
L
H
L
H
L
H
H
L
L
X (01
X (01
Vc
(0 I High output impedance.
(cc) Relative to the considerate channel.
Fig. 2 - Saturation voltage
vs. output current
Fig. 3 - Source saturation
voltage vs. ambient temperature
-'U5
YCEsatH
VCEsat
")
IV)
Vs "Z4V
VCEsat!!---
::::: p-
-so
1.5
(mA)I---+VC-._.O"L~v---\-+_I--+-+---1
Vi "LOW
Vinh",HIGH
48
44
~~.~24~V'--'--+--t-+----\
Yinhibit"Vss"Sv
-
-so
50
Fig. 6 - Output voltage vs.
input voltage
G- '303
Vo
"
-.I, J
~
Fig. 5 - Quiescent logic
supply current vs. logic
supply voltage
-
r--
KEsatL
0.5
50
VeEsatl
IV)
3 r--~i~nh~lb~ltr·V~"~·r5_V--+_+----\---1
Vinhibit"'Vss " 5V
.....-::: :;;;;
I-~V,-.2~4~v-L-J--+-~-4---1
Fig.4 - Sink saturation voltage vs. ambient temperature
r-- Vss"Ylnhibit ,,5 V
It
,/
/
Fig. 7 - Output voltage vs.
inhibit voltage
VOr--r.V~S~·Z~47.V-.-,--,--r~~~
vs-J CE sa!H
'"
V V
50
Vss"Vi- SV
Vs=24V
I--+-+---+V--tr-l
I--Tam b=25 ·c
_Tarntf'2S"C
-12S·e
_40'e
1--t-+---+I+I'I---125"C 1---40'C
II
42
I
/,
I.
40
VeE.at L
Vee: sat L
10
20
30
Vss( V)
i o .. O.1A
1.5
2.5
1.5
------------- ~ ~~I~m?~~~~ ____________5~/8
57
l293B -l293E
APPLICATION INFORMATION
Fig. 8 - DC motor controls (with connection
to ground and to the supply voltage)
V inh
A
H
H
H
L
L= Low
L
X
M1
H
Run
L
Free running
motor stop
H = High
Run
V inh = H
Fast motor
stop
X
C = H;
O=L
Turn right
C = L;
O=H
Turn left
Fast motor stop
C=D
V inh = L
Free running
motor stop
X = Don't care
Fig. 10 - Bipolar stepping motor control
FUNCTION
INPUTS
M2
B
Fast motor
stop
Fig. 9 - Bidirectional DC motor control
C = X;
O=X
x=
H = High
L = Low
Free running
motor stop
Don't care
.v,
O.22,..,F
06
"
01
I"
'07
I
103
I
5
6/8
58
"'65
I
os
ch
lLl/'L2doomA
0'
o:V"
~
Ll
J
D4
L_____~____
01 - 08 =
{
V F .;; l.2V @ I
trr .;; 500 ns
= 300 mA
L293B-L293E
APPLICATION INFORMATION
(continued)
Fig. 11 - Stepping motor driver with phase current control and short circuit protection
~2
v,
02
,"
f:
03
....
L2
11'2
O.
'4
:y ~lJ
4JtIN4001
D5
~,
.J-
'68'5
1
~,
12°/'F
'5V
17
L,
D4
20
:-S1 !Fl'.
0'
~
"ll
1
2
:I'~F
D1
~
4'.INkOOl
'2
'0
11
L293E
f2x1N4148
0"
r--'
010
2.xlN414
[ RS2
RS' ]
'11
'11
01'
D'2
.SV
RJ
,o~
14
LM3~:
+ 9
VA
V~10K.n
'OKIl.
~ll
, pF
'OR~~r
-"-
'3
~
G:"
'pF
R'2
~
+7
'0
Kll
1~.n.
[ RI1
CP4
4
,,,
lh4339
R4
12
+
R11
1
{
JR"
10K.n.
1QQ!l.1l
.sv
01 to 08 :
RMO,:
5'11
rO.,pF
3
114
LM339
"
RS
"'~fJ
~J
10 _
[ R'
'Kll
V 10Ka
C
'RiT
10Ka
10KIl
114
lM339
2
5 +
R'S
47Kll.
47Kll.
R14
R'6
1
5-516611
V F ..; 1 .2V @ I = 300 rnA
trr"; 200 ns
------------- ~ !~I~m~~~
7/8
59
L293B-L293E
MOUNTING INSTRUCTIONS
The Rth J-amb of the L293 and the L293E can
be reduced by soldering the GND pins to a
suitable copper area of the printed circuit board
as shown in figure 12 or to an external heatsink
(figure 13).
During soldering the pins temperature must
not exceed 260°C and the soldering time must
not be longer than 12 seconds.
The external heatsink or printed circuit copper
area must be connected to electrical ground.
Fig. 12 - Example of P.C. board copper area
which is used as heatsink
Fig. 13 - External heatsink
example (R th = 30 °C/W)
mounting
p.e.BOARD
_8_/8_________________________
60
~!~~~~~~:
___________________________
L293C
PUSH-PULL FOUR CHANNEll DUAL H- BRIDGE DRIVER
PRELIMINARY DATA
•
600mA OUTPUT CURRENT CAPABILITY
PER CHANNEL
•
l.ZA PEAK OUTPUT CURRENT
REPETITIVE) PER CHANNEL
•
ENABLE FACILITY
•
OVERTEMPERATURE PROTECTION
•
LOGICAL "0" INPUT VOLTAGE UP TO
1.5V (HIGH NOISE IMMUNITY)
•
SEPARATE HIGH VOLTAGE POWER SUPPLY (UP TO 44V)
(NON
The device may easily be used as a dual H-bridge
driver: separate chip enable and high voltage
power supply pins are provided for each Hbridge. In addition, a separate power supply
is provided for the logic section of the device.
The L293C is assembled in a 20 lead plastic
package which has 4 center pins connected
together and used for heatsinking.
Powerdip
(16+2+2)
The L293C is a monolithic high voltage, high
current integrated circuit four channel driver in
a 20 pin DIP. It is designed to accept standard
TIL or DTL input logic levels and drive inductive loads (such as relays, solenoids, DC and stepping motors) and switching power transistors.
ORDER CODE: L293C
BLOCK DIAGRAM
IN 4
19
OUT4
OUTJ
IN J
18
13
12
r---+--------+--~~--+-~I~I~{)ENABLEZ
VS2U--+~------~--------------~
L293C
9
%Icr-+~------~----------------,
L---+--------1--~~--+---~-{)ENABLE
3
7
8
1
5-9Z87
5.6.15.16
INI
June 1988
OUT1
OUTZ
IN 2
1/3
61
L293C
ABSOLUTE MAXIMUM RATINGS
Supply voItage
Logic supply voltage
Input voltage
Enable voltage
Peak output current (non-repetitive t = 5ms)
Total power dissipation at Tground-Plns = BO°C
Storage and junction temperature
Vs
Vg;
VI
VEN
lout
Ptot
Tstg , TJ
CONNECTION DIAGRAM
50
7
v
7
7
1.2
5
V
V
V
A
W
°c
-40 to 150
TRUTH TABLE
{Topviewj
ENABLE
OUTPUT
H
H
H
L
H
L
X
L
Z
INPUT
Vss
ENABLE I
INPUT 4
INPUT I
OUTPUT 4
OUTPUll
. (NC)
(NC)
GND
GND
GND
Z ;= High outPut impedance
X = Don't care
SWITCHING TIMES
GND
6
(NC)
OUfPUT Z
INPUT 2
OUTPUT 3
1151
INPUT 3
VS2
ENABLE 2
5-92&8
THERMAL DATA
Rth J-case
Rthj-amb
~2/~3
62
Thermal resistance junction-case
Thermal resistance junction-ambient
_________________________
~~~;~~~~
max
max
14
80
___________________________
L293C
ELECTRICAL CHARACTERISTICS (For each channel, Vs
= 24V,
Vss
= 5V,
= 25°C,
Tamb
unless otherwise specified)
Parameter
Vs
Test Conditions
Supply voltage (pin 9,10)
Vss
Logic supply voltage (pin 20)
Is
Total quiescent supply current
(pin9,10)
Min.
Typ.
Vss
4.5
Total quiescent logic supply
current (pin 20)
Unit
44
V
7
V
V, = L;
10 = 0;
VEN = H
2
6
V, = H;
10 = 0;
V EN = H
16
24
V EN = L
Iss
Max.
mA
4
V, = L;
10 = 0;
VEN = H
44
60
V, = H;
10 = 0;
VEN = H
16
22
V EN = L
16
mA
24
V,L
Input low voltage
(pin 2,8, 12, 19)
-0.3
1.5
V
V,H
Input high voltage
(pin 2, 8,12, 19)
2.3
Vss
V
IlL
Low voltage input current
(pin 2, 8, 12, 19)
-10
IJ.A
IIH
High voltage input current
(pin 2, 8,12,19)
100
IJ.A
VENL
Enable low voltage (pin 1, 11)
-0.3
1.5
V
VENH
Enable high voltage (pin 1, 11)
2.3
IENL
Low voltage enable current
(pin 1,11)
VENL = 1.5V
IENH
High voltage enable current
(pin 1, 11)
2.3V .. VEN H .;; Vss -0.6
VCE (sat) H
Source output saturation voltage
(pins 3, 7,13,18)
10 = -0.6A
VCE(sat)L
Sink output saturation voltage
(pins 3, 7,13,18)
10 = +0.6A
tr
Rise time (*l
0.1 to 0.9 Vo
250
ns
tf
Fall time (*)
0.9 to 0.1 Vo
250
ns
Vi = 1.5V
2.3V';; V, .;; Vss -0.6V
30
Vss
V
-100
IJ.A
± 10
IJ.A
1.4
1.8
V
1.2
1.8
V
-30
ton
Turn-on delay (*)
0.5 V, to 0.5 Va
750
ns
toff
Turn-off delay (*)
0.5 V, to 0.5 Vo
200
ns
(*) See switching times diagram
___________________________
~~~~~?~~~
________________________
~3/3
63
...r.=-=
'YL SGS-THOMSON
~D©OO@~[!J~©1i'OO@[K!]D©~
L293D
PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES
PRELIMINARY DATA
•
600mA· OUTPUT CURRENT CAPABILITY
PER CHANNEL
•
1.2A PEAK OUTPUT CURRENT (NON REPETITIVE) PER CHANNEL
•
ENABLE FACILITY
•
OVERTEMPERATURE PROTECTION
•
LOGICAL "0" INPUT VILTAGE UP TO
1.5V (HIGH NOISE IMMUNITY)
•
INTERNAL CLAMP DIODES
To simplify use as two bridges each pair of channels is equipped with an enable input. A separate
supply input is provided for the logic, allowing
operation at a lower voltage and internal clamp
diodes are included.
This device is suitable for use in switching applications at frequencies up to 5 kHz.
The L293D is assembled in a 16 lead plastic
package which has 4 center pins connected
together and used for heatsink ing.
The L293D is a monolithic integrated high voltage, high current four channel driver designed to
accept standard DTL or TTL logic levels and
drive inductive loads (such as relays solenoides,
DC and stepping motors) and switching power
transistors.
Powerdip
12+2+2
ORDERING NUMBER: L293D
BLOCK DIAGRAM
Vs
B
OUT 1
\Is
3
Vss
OUT 3
11
Vs
16
IN 3
IN 1
ENABLE 1
ENABLE 2
IN 4
IN 2
4,5,12,13
6
14
L 2930
5_6573
OUT 2
June 1988
OUT 4
1/4
65
L293D
ABSOLUTE MAXIMUM RATINGS
Vs
vss
VI
Ven
10
Ptot
T stg , Tj
Supply voltage
Logic supply voltage
Input voltage
Enable voltage
Peak output current (1 OOJ.(s non repetitive)
Total power dissipation at T ground-Pins= 80°C
Storage and junction temperature
36
36
7
7
1.2
5
-40 to 150
V
V
V
V
A
W
°c
CONNECTION DIAGRAM
ENABLE 1
16
Vss
INPUT 1
15
INPUT 4
OUTPUT 1
14
OUTPUT 4
13
GND
12
GND
11
OUTPUT 3
10
INPUT 3
GND
4
GND
OUTPUT 2
6
INPUT2
Vs
ENABLE 2
S~6574
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
_2/~4_________________________
66
~~~~~~~~~
max
max
14
80
°c/w
°C/W
___________________________
L293D
ELECTRICAL CHARACTERISTICS (For each channel,
Vs
24V, Vss
unless otherwise specified)
Test condition
Parameter
Min.
Typ.
Max.
Unit
Vs
Supply voltage (pin 8)
Vss
36
V
Vss
Logic supply voltage (pin 16)
4.5
36
V
Is
Total quiescent supply
current (pin 8)
Vi = L
10 = 0
Ven = H
2
6
Vi = H
10 = 0
Ven = H
16
24
VI = L
10 = 0
Ven = H
44
60
Vi = H
10 = 0
V en = H
16
22
Ven = L
16
24
4
Ven = L
Total quiescent logic supply
current (pin 16)
Iss
V IL
Input low voitage
(pin 2, 7,10,15)
V1H
Input high voltage
(pin 2, 7,10,15)
-0.3
1.5
Vss"; 7V
2.3
Vss
> 7V
2.3
7
Vss
IlL
Low voltage input current
(pin 2, 7,10,15)
VIL = 1.5V
IIH
High voltage input current
(pin 2, 7, 10, 15)
2.3V ..; VIH ..; Vss -0.6V
V enL
Enable low voltage (pin 1,9)
V enH
Enable high voltage (pin 1,9)
30
Jl.A
100
Jl.A
V
1.5
2.3
Vss
> 7V
2.3
7
Low voltage enable current
current (pin 1, 9)
V enL = 1.5V
ienH
High voltage enable current
(pin 1,9)
2.3V ..; VenH ..; Vss -0.6V
VCEsatH
Source output saturation
voltage (pins 3, 6, 11, 14)
10=-0.6A
VCEsatL
Sink output saturation
voltage (pins 3, 6, 11,14)
VF
V
-10
-0.3
lenL
mA
V
Vss"; 7V
Vss
mA
-100
Jl.A
± 10
Jl.A
1.4
1.8
V
10=+0.6A
1.2
1.8
V
Clamp diode forward voltage
10=600mA
1.3
V
tr
Rise time (.)
0.1 to 0.9 Va
250
ns
tf
Fall time (*)
0.9 to 0.1 Vo
250
ns
ton
Turn-on delay (.)
0.5 Vi to 0.5 Va
750
ns
toff
Turn-off delay (*)
0.5 Vi to 0.5·V o
200
ns
(*)
-30
V
Seefig.l
- - - - - - - - - - - - - I i f l ~~~~m~::~~lt
____________
3~/4
67
L293D
TRUTH TABLE (One channel)
INPUT
ENABLE (*)
OUTPUT
H
H
H
L
H
L
H
L
Z
L
L
Z
Z = High output impedance
(*) Relative to the considered channel
Fig. 1 - Switching Times
0. 9Vo
-
0.5 Vo
0.1 V
t,
5-4171
-"4/""4_ _ _ _ _ _ _ _ _ _ _
ru SCiS-11tOMSON _ _ _ _ _ _ _ _ _ _ __
•J'" iI:i~©IAl@~iL~©1i"IAl@INIJ~©'"
68
L2720/2/4
LOW DROP DUAL POWER OPERATIONAL AMPLIFIERS
PRELIMINARY DATA
•
•
OUTPUT CURRENT TO 1A
OPERATES AT LOW VOLTAGES
•
•
SINGLE OR SPLIT SUPPLY
LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE
•
•
•
LOW INPUT OFFSET VOLTAGE
GROUND COMPATIBLE INPUTS
LOW SATURATION VOLTAGE
•
THERMAL SHUTDOWN
•
CLAMP DIODE
They are particularly indicated for driving, in·
ductive loads, as motor and finds applications
in compact-disc VCR automotive, etc.
The high gain and high output power capability
provide superior performance whatever an operational amplifier/power booster combination is
required.
.~~
~
....
<;;:,S\;".
.,•
\ . • ,,'
,
.
'
I,
'\
,
"
\
~/
~a
\
'
\
,
The L2720, L2722 and L2724 are monolithic integrated circuits in powerdip, minidip and SIP-9
packages, intended for use as power operational
amplifiers in a wide range of applications including servo amplifiers and power supplies.
Powerdip
Minidip
(8 + 8)
Plastic
SIP-9
ORDERING NUMBERS:
L2720
L2722
L2724
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Peak supply voltage (50ms)
Input voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 80°C (L2720), Tamb = 50°C (L2722)
T case = 75°C (L2720)
T case = 50°C (L2724)
Storage and junction temperature
28
50
V
V
V.
± V.
1
1.5
1
5
10
-40 to 150
A
A
W
W
W
°c
BLOCK DIAGRAMS
,Vs
. L2720
June 1988
L2722
L2724
1/7
69
L272012l4
CONNECTION DIAGRAMS
(Top view)
OUTPUT I
OUTPUT 2
1
16
3
GND
15
GND
14
GND
GNO
13
GND
INPUT -2
12
GND
OUTPUT 1
SUPPLY VOLTAGE
2
OUTPUT 2
INPUT-'
7
INPUT.1
6
S
GNO
11
8
INPUT.2
INPUT_2
0
L2722
10 GND
INPUT-I
9
INPUT-'
INPUT+.
7
INPUT+2
6
INPUT-2
5
GND
•
N.C.
3
OUTPUT 2
n
GND
9
8
GNO
Vs
OUTPUT I
5-971,1
L2724
L2720
SCHEMATIC DIAGRAM (one section)
THERMAL DATA
Rth j-case
Rth j-amb
Thermal resistance junction-pins
Thermal resistance junction-albient
SIP-9
Powerdip
Minidip
max
max
* Thermal resistance junction-pin 4.
~2/~7_________________________ ~I~I~~g~:
70
---------------------------
L2720/2/4
ELECTRICAL CHARACTERISTICS (Vs
= 24V. Tamb = 25°C unless otherwise specified)
Parameter
Vs
Single supply voltage
Vs
Split supply voltage
Is
Ouiescent drain current
Test Conditions
Min.
Typ.
Max.
4
28
±2
± 14
Unit
V
Vo
=
V.
2
Vs
= 24V
10
15
V.
= 8V
9
15
0.2
1
!-IA
rnA
Ib
Input bias current
Vos
Input offset voltage
10
mV
los
Input offset current
100
nA
SR
Slew rate
B
Gain-bandwidth product
Rj
Input resistance
Gv
O.l. voltage gain
2
V/!-Is
1.2
MHz
K.I1
500
f
=
100Hz
f
=
1KHz
B
=
22Hz to 22KHz
80
dB
eN
Input noise voltage
IN
Input noise current
CMR
Common Mode rejection
f
SVR
Supply voltage rejection
f = 100Hz
RG = 10K.I1
VR = 0.5V
=
70
60
1KHz
VOROP (HIGH)
Vs = 24V
Vs = ±12V
Vs = ± 6V
10
!-IV
200
pA
66
84
dB
60
70
75
80
dB
dB
dB
Ip = 100mA
0.7
Ip = 500mA
1.0
Ip = 100mA
0.3
Ip = 500mA
0.5
Vs = 24V
Vs - 6V
60
60
dB
145
°c
V
1.5
Vs = ±2.5V to ± 12V
VOROP(LOW)
V
Cs
Channel separation
Tsd
Thermal shutdown
junction temperature
___________________________
f = 1 KHz
RL = 10.11
G v = 30dB
~~~~~~~~~
1.0
________________________~3/~7
71
L2720/2/4
Fig. 1 - Quiescent current
vs. supply voltage
Fig. 2 - Open loop gain vs.
frequency
lorT-r,,-.'-,,-''-rT,rT;,
(d. )
(mA1H-l-+-i-+-+-H-++-f-++H-I
eo
" H+-H-++H++-H+H-I
H+-H-+-+=b-++-I-t+H-I
70
60
10
I
"- ['\..
50
Vs s24V
,,,"- f'\.:
40
30
"-
20
10
12
16
20
Fig. 3 - Common mode
rejection vs. frequency •. ""
0·6113
24
10'
10'
10'
1"-
10'
1,\
10'
10
flHz)
10'
Fig. 5 - Output swing vs.
load current (V. = ± 12V)
Fig. 4 - Output swing vs.
load current (V. = ± 5V)
G-612e
0-6164
IV )
(Y )
Vs.
~
5V
Vs=:I2V
IJ
r- ""- ~
" r- ""- t--;.
~~IVE
I'
PoSITIVE
200
<00
r-
-
-....
r-
POSITIVE
-
aoo
100
Fig. 6 - Supply voltage
rejection vs. frequency
(d
~~VE
I'
400
600
Fig. 7 - Channel separation
vs. frequency
6-6162
•
....I,,'
t---
70
.....
60
1,,\
60
Vs ::t6V
I-+-+--+~:: ;~dBf'-'-+--+---+-1-1
50
I\.
r-+-+-+-~~~+-~-+-+~
~
"-r--+-+--+-I-+--++-+-I
40r--"+-+-+---+-I-+-+--+-+~
50
10
104 f(Hz)
4-'-'/..:...7 _ _ _ _ _ _ _ _ _ _ _ _ ~ 1~~~m~:~4
72
10
10'
10~
. t( Hz)
_____________
L2720/2/4
APPLICATION SUGGESTION
In order to avoid possible instability occurring
into final stage the usual suggestions for the
linear power stages are useful, as for instance:
layout accuracy;
boucherot cell (0.1 to 0.2J,LF + In series) bet·
ween outputs and ground or across the load.
With single supply operation, a resistor (1Kn)
between the output and supply pin can be
necessary for stability.
A 100nF capacitor connected between supply
pins and ground;
Fig. 8 - Bidirectional DC motor control with J,LP compatible inputs
VS1 = logic supply voltage
Must be V S2
> VS1
E 1, E2 = logic inputs
~_
r,931fl
Fig. 9 - Servocontrol for compact-disc
REFLECTED
BEAM
LASER
5-9475"
Fig. 10 - Capstan motor control in video recorders
DIGITAL
INPUT
------------- ~ 1~~~mg~4 ____________~5/7
73
L2720/214
Fig. 11 - Motor current control circuit
.24V
R7
J-!F
2.5KO
R8
10
v =O.... !8V
R3*
36Kll
IOKO 2·1.
2.5KO
$...$'30/'
*<1-4
Note: The input voltage level is compatible with L291 (5-BIT D/A converterl
Fig. 12 - Bidirectional speed control of DC motors.
For circuit stability ensure that Rx> 2R3
o
RM
R1
where RM = internal resistance of motor. The voltage
V
available at the terminals of the motor is VM = 2 (VI - _5_) + IRol.
2
1M is the motor current.
1M
where 11\,1 =
2R
0
R1
Rx
and
Rx
Yin
RI
IOKCI
I~~][ ~______CR=2J-______~__C:J-__~____________~
10Ka
IOKn
~6/,","7_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~I~m&':'?Jl
74
--------------
L2720/2/4
Fig. 13 - VHS-VCR Motor control circuit
LOADING MOTOR
CASSETTE MOTOR
L2720
® CAPSTAN
MOTOR
L2720
®DRUM
M MOTOR
uP
Z8
+
CAPSTAN TACHO
DRUM POSITION
CTL
REC.PB.
REEl TACHD
RIGHT
LEFT
REEl. TACHe
....
TDA
8114
RESET
----<--'-----------
0
0
~ ~~I~mgr~!Pn4
VHS2::DIS
5-9482
___________
~717
75
L2726
LOW DROP DUAL POWER OPERATIONAL AMPLIFIER
ADVANCE DATA
It is particularly indicated for driving inductive
loads, as motor and finds applications in compact-disc VCR automotive, etc.
•
OUTPUT CURRENT TO 1A
•
OPERATES AT LOW VOLTAGES
•
SINGLE OR SPLIT SUPPLY
•
LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE
•
LOW INPUT OFFSET VOLTAGE
•
GROUND COMPATIBLE INPUTS
•
LOW SATURATION VOLTAGE
The high gain and high output power capability
provide superior performance whatever an operational amplifier/power booster combination is
required.
• THERMAL SHUTDOWN
•
'~
CLAMP DIODE
The L2726 is a monolithic integrated
in SO-20 package intended for use as
operational amplifiers in a wide range
plications including servo amplifiers and
supplies.
circuit
power
of appower
50-20
(12+4+4)
1
ORDER NUMBER: L2726
ABSOLUTE MAXIMUM RATINGS
28
50
Vs
± Vs
1
1.5
1
5
-40 to 150
Supply voltage
Peak supply voltage (50ms)
Input voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 85°C
Tease = 75°C
Storage and junction temperature
BLOCK DIAGRAM
V
V
A
A
W
W
°C
+vs
12
20
11
10
2
9
4+7
14+17
L2726-1:: DIS
June 1988
1/4
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
77
L2726
CONNECTION DIAGRAM
(Top view)
--~---
1
2
3
4
5
6
7
8
9
10
+vs
OUT 2
N.C.
GND
GND
GND
GNO
N.C.
IN 2(-)
IN 2 (+)
20
19
18
17
16
15
14
13
12
11
OUT 1
N.C.
N.C.
GND·
GND
GND
GND
N .·C.
IN 1(-)
IN 1 (+)
L2726-2:: DIS
SCHEMATIC DIAGRAM (one section)
THERMAL DATA
Thermal resistance junction-case
Thermal resistance junction-ambient (*)
max
max
15.0
65
(*l With 4 sq. cm copper area heatsink
~2/~4~
78
______________________
~I~~~~~
__________________________
L2726
ELECTRICAL CHARACTERISTICS (Vs = 24V.
Parameter
Vs
Single supply voltage
Vs
Split supply voltage
Is
Quiescent drain current
Tamb = 25°C unless otherwise specified)
Test Conditions
Min.
Typ.
Max.
4
28
±2
± 14
Unit
V
Vo
=
Vs
2
Vs
= 24V
10
15
Vs
= 8V
9
15
0.2
1
IlA
mA
Ib
Input bias current
Vos
I nput offset voltage
10
mV
los
Input offset current
100
nA
SR
Slew rate
B
Gain-bandwidth product
Ri
I nput resistance
Gy
D.L. voltage gain
eN
f
=
100Hz
f
=
1KHz
B
=
22Hz to 22KHz
Input noise current
CMR
Common Mode rejection
f
SVR
Supply voltage rejection
f = 100Hz
RG = 10Kn
VR = 0.5V
70
=
Vs
1KHz
= ±2.5V to
VOROP(LOW)
Thermal shutdown
junction temperature
-------------
MHz
Kn
80
60
VOROP (HIGH)
Tsd
1.2
dB
IN
Channel separation
V/lls
500
Input noise voltage
Cs
2
f = 1 KHz
RL = 10n
G y = 30dB
10
IlV
200
pA
66
84
dB
60
70
75
80
dB
dB
dB
Vs
Vs
Vs
= 24V
= ± 12V
= ± 6V
Ip
=
100mA
0.7
Ip
=
500mA
1.0
Ip
=
100m,/ll
0.3
Ip
=
500mA
0.5
± 12V
V
V.
Vi = 24V
Vs - 6V
~ Igtmg~l£
1.5
1.0
60
60
dB
145
°c
____________
=3/4
79
L2726
Fig. 1 - Quiescent current
vs. supply voltage
Fig. 2 - Open loop gain vs.
frequency
Fig. 3 - Common mode
rejection vs. frequency._ ....
G·'163
(~:JH++--1-++H++H++--1-l
(dB
80
" H++-I-++-H-++-H++-I-l
10 H++-I-++:±::;o.....+-H++-t-l
"I"f'...
70
60
50
40
30
20
Ys .. 24V
"I"
10
12
16
'v
)
20
24
10'
10'
10'
"I"I'
la'
10
t(Hz)
Fig. 5 - Output swing vs,
load current (V. = ± 12V)
Fig. 4 - Output swing vs.
load current (V.
± 5V)
-"
l
Vs ,,!.12V
V..!:5V
13
--
"
..... 1--1-
11
"'-
-'~~E
I'
-'~~VE
SITIVE
POSITIVE
I--
10
100
<00
600
200
Fig. 6 - Supply voltage
rejection vs. frequency
400
600
Fig. 7 - Channel separation
vs. frequency
G-6'U
'dB
v, ••
"v
Vs ;;!:.6V
80
f-+-+---+~:: ~dBf-t-+-++
r--
70
r--.
"
60
"
60 r-+-+-+---+~~~~+-+---+
5Of-+-++-+-t,----f-+-~-+--!
,/
50
30
20
10
10
.c:,4/...;.4_ _ _ _ _ _ _ _ _ _ _ _
80
--t- +--t---t-j------t-+-+-+---+
!
f- i 10
10'
10"· I(Hz)
1:.U ~~~~m&~l~~JI -------------
L3654S
PRINTER SOLENOID DRIVER
The L3654S is a printer solenoid driver containing
ten open-collector driver outputs and a ten-bit
serial-in, parallel-out register.
Data is clocked into the shift register serially
and transferred to the open-collector outputs
by an enable input. Serial input data is loaded
by the rising edge of the clock. A serial output
from the tenth bit is provided which changes
at the falling edge of the clock. This output is
not controlled by the enable input and remains
active at all time.
clamped to ground internally at 50V to dissipate
stored energy in inductive loads.
The L3654S is supplied in a 16 lead dual in-line
plastic package, and its main fields of application comprise thermal printers, cash registers
and printing pocket calculators.
DIP-16 Plastic
(0.4)
The L3654S is pin to pin compatible with the stan·
dard L3654, but can work with V. down to 4.75V.
Each output is rated at 250mA (sink) and is
ORDER ING NUMBER: L3654S
ABSOLUTE MAXIMUM RATINGS
9.5
9.5
45
0.4
4.0
1
-65 to 150
Supply voltage
Input voltage
External supply voltage
Output current (single output)
Ground current
Total power dissipation (Tamb = 70"C)
Storage and junction temperature
V.
Vi
VE
10
Ig
Ptot
Tstg' Tj
V
V
V
A
A
W
°C
BLOCK DIAGRAM
OUTPUTS
V
OUTPUT 1
EN ENABLE
V
01
DATA
INPUT
5 - 5013 /1
June 1988
1/4
81
L3654S
CONNECTION DIAGRAM
(top view)
OUTPUT ENABLE 1
16
Vs
OUTPUT 6
15
OUTPUT 5
OUTPUT 7
14
OUTPUT 4
13
OUTPUT 3
12
OUTPUT 2
OUTPUT 1
OUTPUT 8
4
OUTPUT 9
OUTPUT 10
6
11
DATA OUTPUT
7
10 DATA INPUT
GND
8
9
CLOCK
'5-5012
Fig. 1 - Timing diagram
VCLK
--j-----
--1---------
VDO
OUTPUT- -
-
s-
-
-
-
-
-
-
-
-
-
-
-
489'
THERMAL DATA
Rth
J-amb
Thermal resistance junction-ambient
~2/~4________________________ ~~~~~~~~©~
82
max
80
°C/W
__________________________
L3654S
ELECTRICAL CHARACTERISTICS
(Vs = 5V,
vE =
30V, T amb = 0° to 70°C, unless otherwise
specified)
Parameter
Min.
Test conditions
Vs
Supply voltage
IS
Supply current
4.75
T amb = 25De
Vs = 9.5V
V
V EN = OV; Voo= OV
40
mA
V EN = 2.6V
10 = 250 mA (each bit)
55
70
mA
40
V
1
mA
65
V
1.6
V
Ileak
Output leakage current
(each output)
VE = 40V
V EN = OV
Vz
I nternal clamp voltage
I z = 0.3A·
V EN = OV
VCE sat
Output satu ration voltage
10 = 250 mA
V EN = 2.6V
VOl
V CLK
V EN
I nput logic levels
(pins 1,9,10)
Low State (L)
101
Data input current
Enable input current
V OI = 2.6V
2.6
T amb = 700e
0.57
mA
0.57
V ol = 1V
T amb = 70DC
220
VCLK= 2.6V
T amb = 70DC
0.2
V CLK= 1V
T amb = 700e
125
V EN = 2.6V
T amb = 70°C
0.2
T amb = 70°C
125
Input pu II-down resistance
Clock input
T amb = 25°C
V CLK
Enable input
T amb = 25DC
V EN
Data input
T amb = 25°C
VOl
Low state (L)
V OI = OV
loo(pin 7)=
< Vs
0.5
fJ.A
8
< Vs
Kn
8
< Vs
VOO=1V
fJ.A
mA
V EN = 1V
VOI=OV
0.5
0.33
0.33
Output pull-down
resistance (pin 7)
fJ.A
mA
0.33
oOe
Output logic levels
(pin 7)
0.75
0.33
oDe
High state (H)
V OI = 2.6V
100 (pin 7) = -0.75 mA
Roo
0.3
oDe
T amb =
VOO
50
V
High state (H)
T amb =
RIN
45
0.8
T amb =
lEN
Unit
9.5
External operating supply
voltage
Clock input current
Max.
27
VE
ICLK
Typ.
4.5
a
0.01
2.6
0.5
V
3.4
V
14
Kn
• Pulsed: pulse duratIon - 300fJ.s, duty cycle - 2%
---------------------------~~~~~~~~:~~n
________________________
~3~/4
83
L3654S
ELECTRICAL CHARACTERISTICS (see fig. 1 and the section "definition of terms")
Test conditions
Parameter
Min.
Typ.
Max.
Unit
Clock, data and enable input
tCLK
4
tCLK
5.5
tSET-UP
1
tHOLO
3
J,ls
Clock to enable delay
tCLK EN
2 tBIT
tEN eLK
tBIT
Enable to clock delay
Data output delay
tpOH, tpOL R L=5Kn,
CL",10pF
0.8
2.5
J,ls
Output delay
tpOEL
3
tpoEH
3.5
J,lS
Output rise time
R L=100n, CL < 100pF
1.2
J,lS
Output fall time
RL=100n, C L < 100pF
1.2
J,lS
VOO rise time
0.4
I'S
VOO fall time
0.4
J,ls
DEFINITION OF TERMS
v
55
:
External power supply voltage. The return for open-collector relay driver outputs.
VOl, V CLK , V EN : The voltages at the data, clock and enable inputs respectively.
V DO
: The voltage at data output.
tBIT
: Period of the incoming clock.
tCLK
: The portion of tBI T when V CLK ~ 2.6V.
tCLK
: The portion of tB.IT when V CLK .,.;; O.BV.
tHOLD
: The time following the start of tCLK required to transfer data within the shift register.
tSET-UP
: The time prior to the end of tCLK required to insure valid data at the shift register input
for subsequent clock transitions.
.
.:.:4/~4~-----------I:FilI~tmg'19lt
84
-------------
L4901A
DUAL 5V REGULATOR WITH RESET
PRELIMINARY DATA
•
OUTPUT CURRENTS:
•
FIXED PRECISION OUTPUT VOLTAGE 5V
±2%
•
RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE
•
RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING
•
RESET OUTPUT LEVEL RELATED TO
OUTPUT 2
101
102
= 400mA
= 400mA
•
• OUTPUT TRANSISTORS SOA PROTEC·
TION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4901 A is a monolithic low drop dual 5V
regulator designed mainly tor supplying microprocessor systems.
Reset and data save functions during switch on/
off can be realized.
• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
•
RESET OUTPUT HIGH
LOW LEAKAGE CURRENT, LESS THAN
lilA AT OUTPUT 1
•
LOW QUIESCENT CURRENT
•
INPUT OVERVOLTAGE PROTECTION UP
TO 60V
Heptawatt
(INPUT 1)
ORDERING NUMBER: L4901A
ABSOLUTE MAXIMUM RATINGS
DC input voltage
Transient input overvoltage (t = 40 ms)
Output current
Storage and junction temperature
24
V
60
internally limited
-40 to 150
V
BLOCK DIAGRAM
Vi 1
O--T-Lt-----,--{2R~EG~.~lJ---,-f---r-o Vol
r:~=-"--D~o RESET
L:":":~J-f~OTlM'NG
4
June 1988
1/9
85
m I~
~
J:
m
s:
»-t
n
5-9349/1
1
IN.1
IN.2
C
»C)
:zJ
»
s:
2
THERMAL &
OVERVOLTA6E
PROTECTION
7
--0
III
~
I I
III
II.
.L..L
...
oun
lilUt
=n
i~
""i!
~O
I-
~!
~Z
III
I .....
~~..~~JII
II
I ,_ .....
~~f4-11
II
~
9'
I I
6
0
I
~
-;I,
I
5
--0
6ND
0
4 1
.1.
L41101:: LIB
III
3
OUT2
RESET
OUTPUT
o TIMIN6
CAPACITOR
r-
~
CD
0
....
»
L4901A
CONNECTION DIAGRAM
(Top view}
~
~
OUTPUT 1
OUTPUT 2
6
$~
RESET
GROUND
TIMING CAPACITOR
INPUT 2
INPUT 1
5
l.
J
1
~
5_7768
PIN FUNCTIONS
NAME
FUNCTION
INPUT 1
Low quiescent current 400mA regulator input.
2
INPUT 2
400mA regulator input.
3
TIMING CAPACITOR
If Reg. 2 is switched-ON the delay capacitor is charged
with a 10J.,tA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged.
4
GND
Common ground.
5
RESET OUTPUT
When pin 3 reaches 5V the reset output is switched high.
5V
Therefore tRD = Ct (10J.,tA); tRD (ms) = Ct (nF)
6
OUTPUT 2
5V - 400mA regulator output. Enabled if Vo 1 > V RT
and V IN2 > VIT' If Reg. 2 is switched-OFF the CO2
capacitor is discharged.
7
OUTPUT 1
5V - 400mA regulator output with low leakage (in
switch-OFF condition).
THERMAL DATA
Thermal resistance junction-case
max
4
--------------------------~1~1;~~:------------------------3~/9
87
L4901A
TEST CIRCUIT
ELECTRICAL CHARACTERISTICS
(V INI = V IN2 = 14,4V, Tamb = 25°C unless otherwise
specified)
Parameter
VI
Test Conditions
Min.
Typ.
DC operating input voltage
Max.
Unit
20
V
VOl
Output voltage 1
R load 1KO
4.9S
S.OS
S.1S
V
V02H
Output voltage 2 HIGH
R load 1KO
VOl-0.1
S
VOl
V
V 02L
Output voltage 2 LOW
102 = -SmA
101
Output current 1
A VOl = -100mV
I L01
Leakage output 1 current
VIN = 0
VOl';; 3V
102
Output current 2
A V 02 = -100mV
ViOl
Output 1 dropout voltage (*)
101 = 10mA
101 = 100mA
101 = 300m A
VIT
Input threshold voltage
VITH
Input threshold voltage hy&t.
AV 0 1
Line regulation 1
AV 0 2
Line regulation 2
AV 0 1
Load regulation 1
0.1
V
mA
400
1
400
V01+ 1•2
~A
mA
0.7
0.8
1.1
0.8
1
1.4
6.4
VOl+ 1.7
V
V
V
V
mV
2S0
7V < VIN < 18V
101 = SmA
S
SO
mV
102 = SmA
S
SO
mV
SmA < 101 < 400mA
SO
100
mV
AV 0 2
Load regulation 2
SO
100
mV
IQ
Quiescent current
0< V IN < 13V
7V < VIN < 13V
102 = 101 .;; SmA
4.S
1.6
6.S
3.S
mA
mA
IQ1
Quiescent current 1
6.3V < VIN 1 < 13V
VIN~ = 0
101
SmA
102 = 0
0.6
0.9
mA
SmA < 102 < 400mA
9_ _ _ _ _ _ _ _ _ _ _ _
-'4/0..:.
88
/iii. ~il~m~SJlAl ------------
L4901A
ELECTRICAL CHARACTERISTICS (continued)
Test Conditions
Parameter
V RT
Reset threshold voltage
VRTH
Reset threshold hysteresis
VRH
Reset output voltage HIGH
VRL
Reset output voltage LOW
tRD
Reset pulse delay
td
Timing capacitor discharge
time
Min.
= 500ltA
= -5mA
Ct = 10nF
Ct = 10nF
Max.
V 02 -O·15
4.9
V 02 -O,05
V
30
50
80
mV
V
V 02 -1
IR
Unit
Typ.
IR
3
4.12
V 02
0.25
0.4
V
5
11
ms
20
/los
~ Thermal drift
-20°C .. Tamb .. 125°C
0.3
-0.8
mV/oC
AV 02
AT
Thermal drift
-20°C" Tamb .. 125°C
0.3
-0.8
mV/oC
SVRl
Supply voltage rejection
f
84
dB
AT
SVR2
Supply voltage rejection
TJSO
Thermal shut down
=
100Hz
VR = 0.5V
10 = 100mA
50
50
80
dB
150
°c
• The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is
lowered of 25mV under constant output current condition.
APPLICATION INFORMATION
In power supplies for IlP systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4901A makes it very easy to
supply such equipments; it provides two voltage
regulators (both 5V high precision) with separ·
ate inputs pi us a reset output for the data save
function.
CIRCUIT OPERATION (see Fig. 1)
After switch on Reg. 1 saturates until VOl
rises to the nominal value.
When the input 2 reaches VIT and the output 1
is higher than VRT the output 2 (V 02 ) switches
on and the reset output (V R ) also goes high after
a programmable time TRD (timing capacitor).
V02 and VR are switched together at low level
when one of the following conditions occurs:
- an input overvoltage
__________________________
- an overload on the output 1 (VOl
- a switch off (VIN < VIT - VITH );
< VRT );
and they start again as before when the condition is removed.
An overload on output 2 does not switch Reg. 2,
and does not influence Reg. 1.
The VOl output features:
5V internal reference without voltage divider
between the output and the error comparator;
very low drop series regulator element utilizing current mirrors;
permit high output impedance and then very
low leakage current error even in power down
condition.
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The VOl
~~~,~~~,~
________________________5~/9
89
L4901A
CIRCUIT OPERATION (continued)
regulator also features low consumption (0.6mA
typ.) to minimize battery drain in applications
where the VI regulator is permanently connected
to a battery supply.
The V02 output can supply other non essential
5V circuits wich may be powered down when
the system is inactive, or that must be. powered
down to prevent uncorrect operation for supply
voltages below the minimum value.
The reset output can be used as a "POWER
DOWN INTERRUPT", permitting RAM access
only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV
SHADOW MEMORY when the supply is interrupted.
Fig. 1
SWITCH
ON
VOl
OVERLOAD
V02
OVERLOAD
VIN
OVERLOAD
THERMAL
SHUT
SWITCH
DOWN
OFF
APPLICATION SUGGESTIONS
Fig. 2 shows an application circuit for a IlP
system typically used in trip computers or in
car radios with programmable tuning.
Reg. 1 is permanently connected to a battery
and supplies a CMOS time-of-day clock and a
CMOS microcomputer ch ip with volatile memory.
Reg. 2 may be switched OFF when the system
is inactive.
Fig. 4 shows the L4901 A with a back up battery
on the VOl output to maintain a CMOS time-ofday clock and a stand by type N-MOS IlP. The
reset output makes sure that the RAM is forced
into the low consumption stand by state, so the
access to memory is inhibit and the back up
battery voltage cannot drop so low that memory
contents are corrupted.
In this case the main on-off switch disconnects
both regulators from the supply battery.
90
The L4901A is also ideal for microcomputer systems using battery backup CMOS static RAMs.
As shown in fig. 5 the reset output is used both to
disable the IlP and, through the address decoder
M74HC138, to ensure that the RAMS are disabled
as soon as the main supply starts to fall.
Another interesting application of the L4901A is
in IlP system with shadow memories. (see fig. 6)
When the input voltage goes below VIT , the
reset output enables the execution of a routine
that saves the machine's state in the shadow
RAM (xicor x 2201 for example).
Thanks to the low consumption of the Reg. 1
a 680llF capacitor on its input is sufficient to
provide enough energy to complete the operation.
The diode on the input guarantees the supply
of the equipment even if a short circuit on V I
occurs.
L4901A
APPLICATION SUGGESTION (continued)
Fig: 2
INl
REG.l
BATTERY
.I.
C1
O.22.u F
I
2
REG. 2
RESET
6
CMOS
.uP WITH
VOLATILE
RAM
VOO
OTHER
LOGIC
C3
10nF
I
@5V
L4901A
5
RESET OUT
RESET
4
5_7710 I J
Fig. 3 -
p.e. board component layout of fig.
2 (1 : 1 scale)
__________________________ ~~~~~~~~~~~ ________________________~7/9
91
L4901A
APPLICATION SUGGESTION (continued)
Fig. 4
~V
.I
IN1
O.22,..F
7
REG. 1
I
,..P(3875-2875)
VOO
IN 2
WITH BATTERV
REG. 2
BACKUP
11olO,..F
4.7,..FI
I
RAM
RESET
VOO
3
CT
L4901A 5
lonFI
RESET OUT
RESET
4
5_'71112
Fig. 5
VI
O,-.,-.----.,.-'-IINI
I' F
:::I:
OUT1I-'----I"-'-,---,---------,-------~VOO:;--j4--.., ~~~~
OUT2 •
1M2
L4901A
:t BATTERY
"00
4Z f
CMOS
STATIC
co
RIW
en
R/ii
.AMS
LIKE
TCSS16
OR TCSS6S
TO
OTHER
CHIPS
sv
---f-----,.-----' r+----+-----1f----------+--'
Veo
iii
VI
AIS
A14
y;;
A13
YS
TO OTHER
MEMORY
CHIPS
Yi
Y1
S-1011I J:
~8/_9________________________ ~I~~~--------------------------
92
L4901A
APPLICATION SUGGESTION (continued)
Fig. 6
ViQ--_-...-.._---!INI
OUT I
680
:I I'F
L4901A
OUT
'--------='-i INZ
r7-1""--~
ZI-'6'--1""--~Vs ADDRESS
DATA
8085
RESETI-'S'-----~TRAP
CT
GNO
10nFI
4
5_'0'jljI2
Fig. 7 - Quiescent current
(Reg. 1) VS. output current
,
lato
'a'
(rnA)
(mA)
Vj1=IZY
-
1--1-""
---
-
200
-
-
/
1
/
/
II
12
Fig. 10 - Regulator 1 output current and short circuit
current vs. input voltage
Fig. 11 - Regulator 2 output current and short circuit
current vs. input voltage
,
'S<
/'
--
BOO
r\
./
100
15
18
V Ii:
500
40 0
'00
l\
1\\
12
/'
60 0
"- .\
\'
Vi tV)
18
/
Vii IV)
.-
12
"1\\
'0 0
Vi IY)
SVR1
SVR
~
~
~
60
\
200
18
6-592'"
'VR
(dBI
70
\
15
Fig. 12 - Supply voltage
rejection regu lators 1 and 2
vs. input ripple frequence
'0
V ' \
70 0
...!...
15
-.
(m'
600
300
Vr'''Vi2
200
'00
700
400
101'" I02~5mA
101 f: 5rnA
/
/
/
Yt2=O
./
I
(m, I
500
Fig. 9 - Total quiescent current vs. input voltage
Fig. 8 - Quiescent current
(Reg. 1) vs. input voltage
6_519'1
50
\\
3
6
9
12
15
18
21
24 Vi
(y)
'0
93
SGS-THOMSON
..~
~L ~o©oo@rn[L[~©'TI'OO@[i\\!]O©~
L4902A
DUAL 5V REGULATOR WITH RESET AND DISABLE
PRELIMINARY DATA
•
DOUBLE BATTERY OPERATING
• OUTPUT CURRENTS:
•
101
102
•
= 300mA
= 300mA
• OUTPUT TRANSISTORS SOA PROTECTION
FIXED PRECISION OUTPUT VOLTAGE 5V
±2%
•
RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE
•
RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING
•
RESET OUTPUT LEVEL RELATED TO
OUTPUT 2
INPUT OVERVOLTAGE PROTECTION UP
TO 60V
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4902A is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset and data save functions and remote switch
on loff control can be realized.
• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
• OUTPUT 2 DISABLE LOGICAL INPUT
•
LOW LEAKAGE CURRENT, LESS THAN
1~A AT OUTPUT 1
•
RESET OUTPUT NORMALLY HIGH
Heptawatt
ORDERING NUMBER: L4902A
ABSOLUTE MAXIMUM RATINGS
DC input voltage
Transient input overvoltage (t = 40 ms)
Output current
Storage and junction temperature
28
V
60
internally limited
-40 to 150
V
°C
BLOCK DIAGRAM
:c
:r
DIS.
DISABLE
r:~=,_jJ5~() RESET
L~~J--r2"---UTIMING
4
June 1988
S-784013
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l>
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~Z
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'-1'
[)o
L49112: : LIB
...
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6
J:I I
1l fll ~D~WJT
j
~-
0
OUT2
5
o TIMING
5 - 9359/1
CAPACITOR
01:0
0
l>
L4902A
CONNECTION DIAGRAM
(Top view)
--
~
$~
OUTPUT 1
6
OUTPUT2
5
RESET
GROUND
DISABLE INPUT
TIMING CAPACITOR
•
3
2
INPUT
~
5-7641
PIN, FUNCTIONS
NAME
FUNCTION
INPUT 1
Regulators common input.
2
TIMING CAPACITOR
If Reg. 2 is switched-ON the delay capacitor is charged
with a 5pA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged.
3
V02 DISABLE INPUT
A high level (> VOT) disable output Reg. 2.
4
GND
Common ground.
5
RESET OUTPUT
When pin 2 reaches 5V the reset output is switched high.
5V
Therefore tRo = Ct (10,uA ); tRO (ms) = Ct (nF).
6
OUTPUT 2
5V - 300mA regulator output. Enabled if Vo 1 > V RT'
DISABLE INPUT < VOT and V IN > VIT' If Reg. 2 is
switched-OFF the CO2 capacitor is discharged.
7
OUTPUT 1
5V - 300mA. Low leakage (in switch-OFF condition)
output.
THERMAL DATA
Thermal resistance junction-case
-,-------------
~ ~~tmWl=
max
4
____________
3.-:..-../9
97
L4902A
TEST CIRCUIT
V,
6
RESET
DIS.
4.7 f F
10nF
5-936012
ELECTRICAL CHARACTERISTICS (V IN
Parameter
Vi
11
"'i
= 14.4V, T amb = 25°C unless otherwise specified)
Min.
Test Conditions
Typ.
DC operating input voltage
Max.
Unit
24
V
VOl
Output voltage 1
R load 1 K!1
4.95
5.05
5.15
V
V 02H
Output voltage 2 HIGH
R load lK!1
VOl -O.l
5
VOl
V
V 02L
Output voltage 2 LOW
102 = -5mA
101
Output current 1 max.
II VOl = -100mV
ILOI
Leakage output 1 current
VIN = 0
VOl';; 3V
102
Output current 2 max.
II V 02 = -100mV
ViOl
Output 1 dropout voltage {*l
101 = 10mA
101 = 100mA
101 = 300mA
V IT
Input threshold voltage
V iTH
Input threshold voltage
hysteresis
II VOl
Line regulation 1
II V02
Line regulation 2
II VOl
Load regu lation 1
II V 02
Load regu lation 2
IQ
Quiescent current
V RT
Reset threshold voltage
VRTH
Reset threshold hysteresis
mA
300
1
VOl +1.2
0.7
0.8
1.1
0.8
1
1.4
6.4
VOl +l.7
250
= 5mA
= 5mA
J.lA
mA
300
V
V
V
V
mV
5
50
mV
5
50
mV
5mA < 101 < 300mA
40
80
mV
5mA < 102 < 300mA
50
80
mV
4.5
2.7
1.6
6.5
4.5
3.5
mA
mA
mA
V02 -0.15
4.9
V02 -O.05
V
30
50
80
mV
7V < VIN < 24V
101
102
0T
AV02
AT
Min.
Typ.
Max.
V02 -1
4.12
V02
V
0.25
0.4
V
3
5
1.25
Vo';; 0.4V
Vo;;' 2.4V
Thermal drift
-20°C';; Tamb .;; 125°C
0.3
-0.8
Supply voltage rejection
TJSO
Thermal shut down
f = 100Hz VR=0.5V 10= 100mA
lAS
2.4
V
mVI"C
0.3
-0.8
Supply voltage rejection
ms
"A
-20°C';; Tamb .;; 125°C
SVR2
11
20
-150
-30
Thermal drift
SVR1
Unit
"A
mV/oC
50
84
50
80
dB
150
°c
dB
* The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is
lowered of 25mV under constant output current condition.
APPLICATION INFORMATION
In power supplies for Jl.P systems it is necessary
to provide power continuously to avoid loss
of information in memories and in time of day
clocks, or to save data when the primary supply
is removed. The L4902A makes it very easy to
supply such equipments; it provides two voltage
regulators (both 5V high precision) with common
inputs plus a reset output for the data save function and a Reg. 2 disable input.
CIRCUIT OPERATION (see Fig.
1)
After switch on Reg. 1 saturates until VOl
rises to the nominal value.
an input overvoltage;
an overload on the output 1 (VOl
a switch off (V 1N < V1T - V1TH );
<
V RT );
and they start again as before when the condition is removed.
An overload on output 2 does not switch Reg. 2,
and does not influence Reg_ 1.
The VOl output features:
- 5V internal reference without voltage divider
between the output and the error comparator
- very low drop series regulator element utilizing current mirrors
When the input reaches V1T and the output 1
is higher than V RT the output 2 (V 02 ) switches
on and the reset output (V R ) also goes high after
a programmable time T RO (timing capacitor).
permit high output impedance and then very
low leakage current even in power down condition.
V02 and VR are switched together at low level
when one of the following conditions occurs:
- a high level (> VOT ) is applied on pin 3;
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, allowing the use of a back-up battery.
--------------------------~~~I~~~'l9~
________________________5~/9
99
L4902A
CIRCUIT OPERATION (continued)
The V02 output can supply other non essential
5V circuits wich may be powered down when
the system is inactive, or that must be powered
down to prevent uncorrect operation for supply
voltages below the minimum value.
The reset output can be used as a "POWE R
DOWN INTERRUPT", permitting RAM access
only in correct power conditions, or as a "BACK-.
UP ENABLE" to transfer data into in a NV
SHADOW MEMORY when the supply is in·
terrupted.
The disable function can be used for remote
on/off control of .circuits connected to the V02
output.
Fig. 1
V~-r~--~~--~r+~----~------~------~------t-L---+-~------~~
SWITCH
ON
VOl
OVERLOAD
V02
OVERLOAD
VIN
OVERLOAD
t~~~MAL
DOWN
V02
DISABLE
SWITCH .
OFF
5-184212
APPLICATION SUGGESTION
Fig. 2 illustrate how the L4902A's disable input
may be used in a CMOS J.!Computer application.
The VOl regulator (low consumption) supply
permanently a CMOS time of day clock and a
CMOS J.!computer chip with volatile memory.
V02 output, supplying non-essential circuits, is
turned OFF under control of a J.!P unit.
Configurations of this type are used in products
where the OFF switch is part of a keyboard
scanned by a micro which operates continuously
even in the OF F state.
Another application for the L4902A is supplying a
shadow-ram microcomputer chip (SGS M38SH72
for exemple) where a fast NV memory is backed
up on chip by a EEPROM when a low level on
_6/_9_ _ _ _ _ _ _ _ _ _ _ _
100
the reset output occurs.
By adding two CMOS-SCHMIDT-TRIGGER
and few external components, also a watch dog
function may be realized (see fig. 5). During
normal operation the microsystem supplies a
periodical pulse waveform; if an anomalous
condition occours (in the program or in the
system), the pulses will be absent and the disable
input will be activated after a settling time determined by R1 C1. In this condition all the
circuitry connected to V 02 ' will be disabled,
the system will be restarted with a new reset
front.
The disable of V02 prevent spurious operation
during microprocessor malfunctioning.
iiii. ~~~~mg'~©~
--------------
L4902A
APPLICATION SUGGESTION (continued)
Fig.2
-1
J:.
INl
1
C~
TTERY
4.7,u F
7
REG.l
:I
IIPF
3
~
V02 DIS
6
REG. 2
VOO
OUT 1
~3
I
OUT 2
~
I tolOpf
I
VDD
OUT PORT
I
IC4
IN PORT
C~
I
CMOS
pP WITH
VOlATILE
RAM
VOO
OTHER
LOGIC
2
10nF
CMOS
CLOCK
@5V
L4902A
5
RESET OUT
RESET
I
5-78.43/1
Fig. 3 -
p.e. board and component layout of the circuit of Fig. 2
GND
DIS.
OUT2
---------------------------~~~~~~?~f~~~
(1 : 1 scale)
GND
________~--------------~7/~9
101
L4902A
APPLICATION SUGGESTION
(continued)
Fig. 4
Vi
Vol
7
Vo2
6
DISABLE
3
L4902A
J:
VDD
TO OTHER
5V CHIPS
10fF
1>}J
5
F
M38SH72
RESET
2
10nF
I
100nF
I
5- 9362/2
Fig. 5
OUT1~7~-----------------------~------~VDD
O-.......-!..IIN
OUT21C6~-----_--_-L4902A
.
3
DIS.
5
4.7}J F
RST~---+---+---4-~--------HRST}JP
TIM. 2
-------------1
OUTPUT
PORT
I
:mul
$-9363/2
~8~/9_________________________ ~1~~~~~:--------------------------
102
L4902A
APPLICATION SUGGESTION (continued)
Fig. 6- Quiescent current
vs. output current
Fig. 7 - Quiescent current
vs. input voltage
G-S8S511
'0
(mA
,
,
,
'0
IN
SYR
{dB I
'Ij ,.12¥
"02 HIGH
'o,-102 15mA
---VOZLOW
-
-YOZHGH
~
100
200
I--------:.l
~/
.':-
.-
.-
Fig. 8 - Supply voltage
rejection regulators 1 and 2
vs. input ripple frequence
)" 7~
r - --
.0
SVRI
-SYR
0
~
N
0
V
1
0
12
I!.
I'
Vi (v)
10
10'
103
L4903
DUAL5V REGULATOR WITH RESET AND DISABLE FUNCTIONS
PRELIMINARY DATA
• OUTPUT CURRENTS:
101
102
= 50mA
= 100mA
•
FIXED PRECISION OUTPUT VOLTAGE
5V ±2"1o
•
RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE
•
RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING
•
RESET OUTPUT LEVEL RELATED TO
OUTPUT 2
•
OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
•
OUTPUT 2 DISABLE LOGICAL INPUT
•
LOW LEAKAGE CURRENT, LESS THAN
1J.lA AT OUTPUT 1
•
INPUT OVERVOL TAGE PROTECTION UP
TO 60V
•
RESET OUTPUT NORMALLY LOW
•
OUTPUT TRANSISTORS SOA PROTECTION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4903 is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset, data save functions and remote switch
on/off control can be realized.
Minidip Plastic
ORDERING NUMBER: L4903
ABSOLUTE MAXIMUM RATINGS
DC input voltage
Transient input overvoltage (t = 40 ms)
Power dissipation at T amb = 50°C
Storage and junction temperature
24
V
60
1
-40 to 150
W
°C
V
BLOCK DIAGRAM
Vi I
Vi
o------.!.t---~r-~RE~G~.,~-T-t~8- - D Vol
2O------.1+-r-t-f=G~a~~~2.7---o
Vo
2
o IS.O-----s'-+---t
t----ps'---..o RE SET
L:":':~J-I'---'OTIMIN G
4
June 1988
5-!416/2
1/7
105
en
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::J:
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0
1
I,
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:Jl
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THERMAL &
OVERVOLTAGE
PROTECTION
~
IN 2 _ 2
C
:;
5 - 9422
111-
1,1
~l ~
-
1
8
1
0
OUB
~Ut
@In
:wUt
© •
~:i!
!o
~I
.L.L
fiilO
~Z
°GINSO" : :
I
r
I'
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-t
i
II
~l_~
j:{ 1"
nj
OUT2
6
-0
-~ 0
RESET
OUTPUT
TIMING
CAPACITOR
Ii
L4903
CONNECTION DIAGRAM
(Top view)
OUTPUT I
INPUT I
INPUT 2
TIMING
CAPACITOR
3
GND
4
RESET
OUTPUT
V02
DISABLE
INPUT
5-5417
PIN FUNCTIONS
NAME
FUNCTION
INPUT 1
Low quiescent current 50mA regulator input.
2
INPUT 2
100mA regulator input.
3
TIMING CAPACITOR
If Reg. 2 is switched-ON the delay capacitor is charged
with a 10J.l,A constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged.
4
GND
Common ground.
5
V 02 DISABLE INPUT
A high level (> VOT ) disables output Reg. 2.
6
RESET OUTPUT
When pin 3 reaches 5V the reset output is switched low.
5V
= Ct (10J.l,A);
tRO (ms) = Ct (nF).
Therefore tRO
7
OUTPUT 2
5V - 100mA regulator output. Enabled if Va 1 > V RT .
DISABLE INPUT < V OT and V IN 2 > VIT' If Reg. 2 is
switched OFF the CO2 capacitor is discharged.
8
OUTPUT 1
5V - 50mA regulator output with low leakage in switchOFF condition.
THERMAL DATA
Rthj-Pln
Rth j-amb
Thermal resistance junction-pin 4
Thermal resistance junction-ambient
--------------------------~I~I;~&~~
max
max
70
100
________________________
~3/7
107
L4903
TEST CIRCUIT
P.C. board and components layout
of the test circuit (1 : 1 scale)
Vi1 o--- VOT ) is applied on pin 5;
an input overvoltage;
an overload on the output 1 (VOl < V RT );
a switch off (V1N < V 1T - V 1TH );
and they start again as before when the condi·
tion is removed.
An overload on output 2 does not switch Reg. 2,
and does not influence Reg. 1.
CIRCUIT OPERATION (see Fig. 1)
The VOl output features:
5V internal reference without voltage divider
between the output and the error comparator
After switch on Reg. 1 saturates until VOl rises
to the nominal value.
When the input 2 reaches VIT and the output 1
is higher than VRT the output 2 (V02 and VR )
switches on and the reset output (V R ) goes low
after a programmable time TRO (timing capacitor).
V02 is switched at low level and VR at high level
when one of the following conditions occurs:
very low drop series regulator element utilizing current mirrors
permit high output impedance and then very
low leakage current even in power down conditions.
This output may therefore be used to supply
circuits continuously, such as volatile RAMs, al·
lowing the use of a back-up battery.
------------- ~ l~m~~JI-------------'-5/7
109
L4903
CIRCUIT OPERATION (continued)
The V02 output can supply other non essential
5V circuits wich may be powered down when
the system is inactive, or that must be powered
down to prevent uncorrect operation for supply
voltages below the minimum value.
only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV
SHADOW MEMORY when the supply is interrupted.
The disable function can be used for remote
on/off control of circuits connected to the V02
output.
The reset output can be used as a "POWE R
DOWN INTERRUPT', permitting RAM access
Fig. 1
VIN .V01 • vD
VIT
VITH
VRT
VOl
vOl.vR
SWITCH
ON
VOl
OVERLOAD
V02
OVERLOAD
vlN
OVERLOAD
~~~~M"'L
DOWN
V02
DISABLE
SWITCH
OFF
5-941911
APPLICATION SUGGESTION
Fig. 2 illustrates how the L4903's disable input
may be used in a CMOS J,lComputer application.
turned OFF under control of a J,lP unit.
Configurations of this type are used in products
where the OFF switch is part of a keyboard
scanned by a micro which operates continuously
even in the OFF state.
The VOl regulator (low consumption) supply
permanently a CMOS time of day clock and a
CMOS J,lcomputer chip with volatile memory.
V02 output, supplying non-essential circuits, is
Fig. 2
IN'
BATTERY
~
'00
OTHER
LOGIC
@sv
CT
10nF
I
L4903
6
RESET OUT
~6/~7__________________~____ ~~~~~g~:
110
RESET
__________________________
L4903
APPLICATION SUGGESTIONS (continued)
Fig. 3 - Quiescent current
(Reg. 1) vs. output current
Fig. 4 - Quiescent current
(Reg. 1) vs. input voltage
101
(rnA)
YI2"O
101~5mA
0.'
l-+-t--i---j-l-+W--l--l--l-++-W--.j
V
/
V
V
/
25
5010l(mA}
12
IS
18
VII (V)
Fig. 6 - Supply voltage rejection regulators 1 and 2
vs. input ripple frequence
Fig. 5 -- Total quiescent
current vs. input voltage
6-592411
G-58&&/1
.'Q
SYR
'dBI
'rnA I
IOl"'Io2 S5mA
---Y02 lOW
- V02 ttGH
,
I---.
80
I
II
,.
t7 lL
:SYR
~
",,!J'
- -- V
SYR1
~
60
50
J
12
15
II
Vi
(vi
___________________________
10
~~~~~~~
10 3
(Hzlfrlpple
________________________~71_7
111
L4904A
DUAL 5V REGULATOR WITH RESET
PRELIMINARY DATA
•
= 50mA
= 100mA
• FIXED PRECISION OUTPUT VOLTAGE
5V ± 2%
• OUTPUT CURRENTS:
101
102
•
RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE
•
RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING
•
RESET OUTPUT LEVEL RELATED TO
OUTPUT 2
• OUTPUT TRANSISTORS SOA PROTECTION
• SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION
The L4904A is a monolithic low drop dual 5V
regulator designed mainly for supplying microprocessor systems.
Reset and data save functions during switch on/
off can be realized.
• OUTPUT 2 INTERNALLY SWITCHED WITH
ACTIVE DISCHARGING
•
LOW LEAKAGE CURRENT, LESS THAN
11lA AT OUTPUT 1
•
LOW QUIESCENT CURRENT (INPUT 1)
•
INPUT OVERVOLTAGE PROTECTION UP
TO 60V
RESET OUTPUT NORMALLY HIGH
Minidip Plastic
ORDERING NUMBER: L4904A
ABSOLUTE MAXIMUM RATINGS
V IN
10
Ptot
Tj
DC input voltage
Transient input overvoltage It = 40 ms)
Output current
Power dissipation at Tamb = 50°C
Storage and junction temperature
24
60
internally limited
1
-40 to 150
V
V
W
°C
BLOCK DIAGRAM
Vi
I O--T--.-!.+---li-[~R~E~G.2IJ----;r*--"]__-c
Vol
:r
r:~=-"_~6~O RESET
L::":":~J-I'--O
4
June 1988
TIMING
s- 9411(1
1/8
113
+:-
en
.....
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n
I'"
:I:
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»
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I
IN.1~
b:L
IN.2 2111 _CO I
OVERVOLTAGE
PROTE~TION
I
»
G)
:lJ
»
s
I III ~ fj 0
l(
I
8
--0
OUH
7
OUT2
~
~fn
©n
aIDfn
© •
~:i!
!O
aIDiK
III
I!
~Z
I .. _.. __..__
J II
.L.L
II i .__ _-V"tn
ww.~" ~,,~.
Q
..
GND
""'"
.L
4-,
':>-9410/1
I
II
I
$
~I
I
111
0
6
3
RESET
OUTPUT
TIMING
CAPACITOR
0
r
.j::Io
co
0
.j::Io
l>
L4904A
CONNECTION DIAGRAM
(Top viewl
INPUT I
INPUT 2
TIMING
CAPACITOR
RESET
OUTPUT
6
3
GND
N.C.
PIN FUNCTIONS
NAME
FUNCTION
INPUT 1
Low quiescent current 50mA regulator input.
2
INPUT 2
100mA regulator input.
3
TIMING CAPACITOR
If Reg. 2 is switched-ON the delay capacitor is charged
with a 10~A constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged.
4
GND
Common ground.
6
RESET OUTPUT
When pin 3 reaches 5V the reset output is switched high.
5V
Therefore tRo = C; (10~A I; tRo (msl = Ct (nFI.
7
OUTPUT 2
5V - 100mA regulator output. Enabled if Vo 1 > V RT
and VIN 2 > VIT' If Reg. 2 is switched-OFF the CO2
capacitor is discharged.
8
OUTPUT 1
5V - 50mA regulator output with low leakage in switchOFF condition.
THERMAL
DATA
• 'l
~
RthJ-ari1b
Thermal resistance junction-ambient
------'~--------- ~ I~tm~
max
100
____________
/8
3_
115
L4904A
TEST CIRCUIT
p.e. board and components layout
of the test circuit (1 : 1 scale)
ELECTRICAL CHARACTERISTICS (V IN
Parameter
Vi
= 14,4V. T amb = 25°C unless otherwise specified)
Test Conditions
Min.
Typ.
DC operating input voltage
Max.
Unit
20
V
VOl
Output voltage 1
R load 1Kn
4.95
5.05
5.15
V
V02H
Output voltage 2 HIGH
R load 1Kn
VOl -0.1
5
VOl
V
V02L
Output voltage 2 LOW
102
101
Output current 1
.lIV01
IL01
Leakage output 1 current
VIN s 0
VOl'" 3V
102
Output current 2
II V 0 2
VIOl
Output 1 dropout voltage (oJ
101 s 10mA
101 = 50mA
VIT
Input threshold voltage
VITH
Input threshold voltage hyst.
II VOl
Line regulation
lIV0 2
Line regulation 2
lIV 01
Load regulation 1
lIV 02
Load regulation 2
IQ
Quiescent current
o<
IQ1
Quiescent current 1
6.3V < VIN1
VIN2 - 0
101 '" 5mA
0.1
-5mA
s
s
V
mA
50
-100mV
1
-100mV
0.7
0.75
O.B
0.9
6.4
VOl +1.7
250
7V < VIN < 1BV
VIN = BV
V
V
V
mV
101
s
5mA
5
50
102
s
5mA
5
50
mV
5mA
<
5mA
< 102 <
101
< 50mA
100mA
VIN < 13V
7V
3:
7
--0
~
III
I I
1
),
.L..L.
...
OUTi
~ua
I~
©•
~i
~O
~!I
JII
©ua
III
I ___
~Z
I
II
I . __ . __ 1+--1 I
u
____
II
I I6
I
0
OUT2
~O
y
I:(
~
-J, I
5
--0
GND~
-.1.
L41101:: LIB
111
3
RESET
OUTPUT
o TIMING
CAPACITOR
Ii
L4905
CONNECTION DIAGRAM
(Top view)
-r---"\.-
~
OUTPUT 1
OUTPUT 2
6
$"--L---..r-
RESET
GROUND
TIMING CAPACITOR
INPUT 2
INPUT 1
,5
3
2
~
S_7768
PIN FUNCTIONS
NAME
FUNCTION
INPUT 1
Low quiescent current 200mA regulator input.
2
INPUT 2
300mA regulator input.
3
TIMING CAPACITOR
If Reg. 2 is switched-ON the delay capacitor is charged
with a 10JJ.A constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged.
4
GND
Common ground.
5
RESET OUTPUT
When pin 3 reaches 5V the reset output is switched high.
5V
Therefore tRD = c; '10JJ.A); tRD (ms) = c; (nF)
6
OUTPUT 2
5V - 300mA regulator output. Enabled if Vo 1 > V RT
and V'N2
V'T' If Reg. 2 is swi.tched-OFF the CO2
>
capacitor is discharged.
7
OUTPUT 1
5V - 200mA regulator output with low leakage lin
switch-OFF condition).
THERMAL DATA
Thermal resistance junction-case
max
4
--------'------- I:fi. ~~m~ ____________
3-'--/8
123
L4905
TEST CI.RCUIT
....- - - -.. 7
.-------------~~~
6
5 RESET
3
I r,pF
4.7 fF
ELECTRICAL CHARACTERISTICS (V INl
specified)
Parameter
VI
14,4V,
Test Conditions
Tamb
Min.
25° unless otherwise
Typ.
DC operating input voltage
Max.
Unit
24
V
5.05
5.1
V
5
VOl
VOl
Output voltage 1
R load 1Kn
V02H
Output voltage 2 HIGH
R load 1Kn
V 02L
Output voltage 2 LOW
102 = -5mA
101
Output current 1
llVOI =-100mV
IL01
Leakage output 1 current
102
Output current 2
VIOl
Output 1 dropout voltage (*)
VIT
Input threshold voltage
VITH
Input threshold voltage hyst.
llVOl
Line regu lation 1
7V < VIN < 24V
101 = 5mA
5
50
mV
llV0 2
Line regulation 2
102 = 5mA
5
50
mV
llVOl
Load regulation 1
mV
llV02
Load ragu lation 2
IQ
Quiescent current
IQl
Quiescent current 1
·VOI -0.1
0.1
llV02 = -100mV
mA
1
Vol +1.2
p.A
mA
300
101 = 10mA
101 = 100mA
101 = 200mA
V
V
200
VIN = 0
. VOl <; 3V
0.7
0.8
1.05
0.8
1
1.3
6.4
VOl + 1.7
250
V
V
V
mV
5mA < 101 < 200mA
40
80
5mA < 102 < 300mA
50
100
mV
0< VIN < 13V
7V----+----1I118i: 2~"
(Tab
connected
to pin J)
5-9408
Fig. 1 - Application and test circuit
5
Vi
VO
L4918
"'·'1
2
3
eFT
11OI-IF
I
1/.JF
5-9409/1
THERMAL DATA
Rth H:ase
Thermal resistance junction-case
~2/~5________________________ ~I~~~~~~l~~~
142
max
4
--------------------------
L4918
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VI = 13.5V unless otherwise specified)
Parameter
Mi....
Test Conditions
Typ.
Max.
Unit
20
V
8.5
8.9
V
1.6
2.1
V
1
20
mV
100
mV
VI
Input voltage
Vo
Output voltage
VI = 12 to 18V
10 = 5 to 150mA
!J.VI/O
Controlled input-output
dropout voltage
VI=5to10V
10 = 5 to 150mA
!J.Vo
Line regulation
VI = 12 to 18V
10 = 10mA
!J.Vo
Load regu lati on
10 = 5 to 250mA
ton = 30/.ls
toff = ~ 1ms
!J.Vo
Load regu lation
Vi = 8.5V
10 = 5 to 150mA
ton = 30/.ls
toff = ~ lms
100
250
mV
Iq
Quiescent current
10 = 5mA
1.0
2
mA
!J.lq
Quiescent current change
V I =6to18V
10 = 5 to 150mA
Output voltage drift
10 = 10mA
Supply voltage reiection
Viae = lVrms
f = 100Hz
10 = 150mA
!J.Vo
!J.T
SVR
8.1
VIDC = 12 to 18V
V I DC = 6 to 11 V
Isc
Short circuit current
ton
Switch on time
250
mA
1.2
mVrC
71
35 (*)
dB
dB
300
mA
500 (*)
300
ms
ms
150
°c
10 = 150mA
VI=5tol1V
VI = 11 to 18V
TJSD
0.05
Thermal shut down
(*) Depending of the CFT capacitor
___________________________
~~~~~~?~~~~~
________________________
~3/5
143
L4918
PRINCIPLE OF OPERATION
During normal operation (input voltage upper
than VI MIN = VOUT NOM + /::"Vljo)· The device
works as a normal voltage regulator built around
the OP1 of the block diagram.
The series pass element use a PNP-NPN connection to reduce the dropout. The reference voltage
of the OP1 is derived from a REF through the
OP2 and Q3, acting as an active zener diode of
value V REF .
In this condition the device works in the range
(1) of the characteristic of the non linear drop
control unit (see fig. 2)
The output voltage is fixed to its nominal value:
VOUT NOM = V REF (1
V CFT (1
+ .J!.L) =
R2
age goes below VMIN the drop out is kept fixed
to about 1.6V. In this condition the device works
as a low pass filter in the range (2) of the OTA
characteristic. The ripple rejection is externally
adjustable acting on CFT as follows:
SVR (jw)
out
1 + ___....!1~o-~6_ _ __
-B!!l..-
(1
+ ..B.!..)
jwC FT
R2
Where:
gm = 2 • 1(}-s U-l = OT A'S typical transconductance value on linear region
..B.L =
+ --'il)
=I VVI Ow)
1=
(jw)
fixed ratio
R2
R2
R1
INTERNALLY FIXED RATIO = 2.4
R2
The ripple rejection is quite high (71 dB) and independent from CFT value.
On the usual voltage regulators, when the input
voltage goes below the nominal value, the regulation transistors (series element) saturate bringing
the system out of regulation making it very sensible to every variation of the input voltage. On
the contrary, a control loop on the L4918 consents to avoid the saturation of the series element
by regulating the value of the reference voltage
(pin 2). In fllct, whenever the input voltage
decreases below VI MIN the supervisor loop,
utilizing a non linear OT A, forces the reference
voltage at pin 2 to decrease by discharging CFT .
So, during the static mode, when the input volt-
CFT = value of capacitor in IJ.F
The reaction time of the supervisor loop is given
by the tranconductance of the OTA and by CFT .
When the value of the ripple voltage is so high
and its negative peak is fast/enough to determine
an istantaneous decrease of the dropout till 1.2V,
the OTA works in a higher transconductance
condition [range (3) of the characteristic] and
discharge the capacitor rapidously.
If the ripple frequency is high enough the capacitor won't charge itself completely, and the
output voltage reaches a small value allowing a
better ripple rejection; the device's again working
as a filter (fast transient range).
With C FT = 10 IJ.F; f = 100 Hz a SVR of 35 is
obtained.
Fig.2 - Nonliner transfer characteristic of the drop control unit
5-9617/2
3
2
1) Normal operating range (high ripple rejection)
2) Drop controlled range (medium ripple rejection)
3) Fast discharge of eFT
~~~5_ _ _ _ _ _ _ _ _ _ _ _ _ ~I~~;~~~~
144
---------------
L4918
Fig. 3 - Supply voltage
rejection vs. frequency
Fig. 4 - Supply voltage
rejection vs. input voltage
Fig. 5 - Output voltage vs
input voltage
C._5198
(dB)
Il=lOOmA
'0
CFT=lOf.jF
(dB)
Vr =lVRMS
70
1o=.50mA
Yo
~~:~~~~s ~-t--l-.,f==f=*,---1
(V)
'o=·aOmA
f '" 100Hz:
10
.0
/
70
7,_13.5'11
.0
'"
.0
,~
..
17
.0
I-- - -
30
~=6V
20
V
30
17
I'
Y
C FT =47/-lF
I
22/olF
'OMF
I
I
I
,
10'
10'
10'
t(Hl:)
_____________
II
'_L78M08
~,
20
10
f-
I';;;;;::;;'
10
I
12
"
~!~~~~:
VsIY)
4
6
8
10
12
14
16
18
'lis (v)
____________
5~/5
145
L4920
L4921
..~
.,L SGS-THOMSON
~o©oo@rn[brn©'D'OO@[R!]O©~
VERY LOW DROP ADJUSTABLE REGULATORS
PRELIMINARY DATA
•
VERY LOW DROP VOLTAGE
•
ADJUSTABLE OUTPUT VOLTAGE FROM
1.25V TO 20V
•
A fold back current limiter protects against load
short circuits.
The output voltage is adjustable through an
external divider from 1.25V to 20V. The minimum operating input voltage is 5.2V.
400mA OUTPUT CURRENT
•
LOW QUIESCENT CURRENT
•
OVERVOL TAGE AND REVERSE VOL TAGE PROTECTION
These regulators are designed for automotive,
industrial and consumer applications where low
consumption is particularly important.
• +60/-60V TRANSIENT PEAK VOLTAGE
In battery backup and standby applications the
low consumption of these devices extends battery life.
• SHORT CIRCUIT PROTECTION WITH
FOLDBACK CHARACTERISTICS
• THERMAL SHUT-DOWN
The L4920 and L4921 are adjustable voltage
regulators with a very low voltage drop (OAV
typo at OAA), low quiescent current and comprehensive on-chip protection.
Pentawatt
These devices are protected against load dump
transients of ± 60V, input overvoltage, polarity
reversal and over heating.
•
Minidip (4 + 4)
ORDERING NUMBERS:
L4920
L4921
BLOCK DIAGRAM
IN PUT
I
rPREREGll.ATORl--
I
DlMP
PROTECTION
1
""O~,
REFERENCE
AND
ERROR
AMPLIFIER
J
OUTP UT
+
RI
'1
-'-
I
ADJU ST
II
r
I 1r
THERMAL
PROTECTION
FOLDBACK
CURRENT
LIMITER
I
1I
I
GNo
-June 1988
R2
!.~7'1611
1/4
147
L4920 - L4921
ABSOLUTE MAXIMUM RATINGS
26
DC input operating voltage
Positive transient peak voltage (t = 300ms 1% duty cycle)
Negative transient peak voltage (t = 100ms 1% duty cycle)
Reverse input voltage
Storage temperature
Operating junction temperature
+60
-60
-18
-55 to 150
-40 to 150
CONNECTION DIAGRAMS (top view)
@II
5-7914
L
/
;:~::~
1111
5-1915
Tab connected to pin 3
Minidip
Pentawatt
APPLICATION CIRCUIT
Rl
c
R2
5-1917/2
C = 100",F is required for stabilitY (ESR " 30 over T range)
R2 = 6.2KO.
THERMAL DATA
Rthjo INPUT
5 - 256811
ORDERING NUMBERS
OUTPUT VOLTAGE
L4940V5
L4940V85
L4940Vl0
L4940V12
5V
8.5V
10V
12V
ABSOLUTE MAXIMUM RATINGS
Forward input voltage
Reverse input voltage (V o = 5V
(V o = 8.5V
(V o = 10V
(V o = 12V
Output current
Power dissipation
Junction and storage temperature
Ro
Ro
Ro
Ro
30
-15
= 100m
= 180m
= 200m
v
v
= 240n)
Internally limited
Internally limited
-40 to 150
THERMAL DATA
Rth j-<:ase
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
2_/_8_ _ _ _ _ _ _ _ _ _ _ _ _
152
max
max
3
50
~ ~~tm~::~~Al-------------
L4940 Series
TEST CIRCUITS
Fig. 1 - DC Parameters
Fig. 2 - Load Regulation
Fig.
3-
Ripple Rejection
5-10151/1
5-10159/1
ELECTRICAL CHARACTERISTICS
(Refer to the test circuits T j
= 25°C, C I = O.lIlF, Co = 221lF,
unless otherwise specified)
Parameter
Test Conditions
Min.
Typ. Max. Min. Typ. Max.
OUTPUT VOLTAGE
5
8.5
INPUT VOLTAGE (unless otherwise specified)
7
10.5
Vo
Output voltage
10 = 0.5A
4.9
5.1
10=5mAto 1.5A
4.8 I 5
5.2
(Vi= 6.5 to 16V)
5
I
8.3
V
V
8.5
8.7
8.151 8.5 18.85
(Vi= 10.2 to 16V)
VI
Operating input
voltage
10= 5mA
17
17
t:,vo
Line regulation
10 = 5 mA
10
4
(Vi= 6V to 17V)
4
9
(V I= 9.5 to 17V)
t:,vo
Load regulation
IQ
L1IQ
Vd
Quiescent current
Quiescent current
Dropout voltage
10 = 5 mA to 1.5A
8
25
12
30
10 = 0.5A to lA
5
15
8
16
5
8
4
8
10 = 5 mA
10 = 1.5 A
30
50
(V i = 6.5V)
10 = 5 mA
3
!
I
Unit
30
50
(V i = 10.2V)
V
V
mV
mV
mA
2.5
I
I
10= 1.5A
15
(V I= 6.5 to 16V)
15
(VI= 10.2 to 16V)
10 = 0.5A
200
400
200
400
10= 1.5A
500
900
500
900
mA
mV
L1Vo
Output voltage
0.5
0.8
mVI"C
68
58
66
2
2.7
t;T drift
SVR
Supply voltage
rejection
f = 120 Hz
10= 1A
Isc
Short circuit
current limit
Vi = 14V
58
2
2.7
2.2
2.9
(Vi = 6.5V)
2.9
2.2
(Vi = 10.2V)
d8
A
Zo
Output impedance
f = 1 KHz
10 = 0.5A
30
32
mfi
eN
Output noise
B = 100 Hz to 100 KHz
30
30
p.VNo
--------------~ ~~~~m~~lt
_____________
3/;...,8
153
L4940 Series
ElECTR ICAl CHARACTERISTICS (Refer to the test circuits Tj = 25°C, Ci = O.lJ,lF, Co = 22J,lF,
unless otherwise specified)
Test Conditions
Parameter
Min.
Typ.
OUTPUT VOLTAGE
INPUT VOLTAGE (unless otherwise specified)
Vo
Output voltage
Max.
Typ.
Min.
10
10.2 11.75
10 = 0.5A
9.8
10 = 5 mA to 1.5A
9.6 ] 10 110.4
(Vi= 11.7 to 16V)
12
Unit
V
14
12
10
Max.
12
V
12.25
V
11.51 12 112.5
(V;= 13.8to 17V)
Vi
Operating input
voltage
10 = 5 mA
17
17
lo,V o
Line regulation
10 = 5 mA
3
8
(Vi = 11 to 17V
3
7
(V; = 13 to 14V)
lo,V o
Load regulation
10=5mAtol.5A
15
35
15
35
10 = 0.5A to lA
10
20
10
25
4
8
4
8
V
mV
mV
IQ
Quiescent current
10 = 5 mA
10 = 1.5A
lo,lQ
Quiescent current
30
50
(Vi = 11.7V)
10 = 5 mA
2
change
I
10 = 1.5A
I 13
(V i= 11.7 to 16V)
Vd
Dropout voltage
30
50
(V; = 13.8V)
mA
1.5
I
1 10
(Vi = 13.8V)
10= 0.5A
200
400
200
400
10= 1.5A
500
900
500
900
mA
mV
lo,V o
hl
Output voltage
drilt
SVR
Supply voltage
rejection
Isc
Short circuit
current limit
1
1=120Hz
10 = lA
56
Vi = 14V
62
55
1.2
mVrc
61
dB
2
2.7
2
2.7
V;=11.7V
2.2
2.9
-
-
A
Zo
Output impedance
1= 1KHz
10 = 0.5A
36
40
m!1
eN
Output noise
voltage
B = 100 Hz to 100 KHz
30
30
/lVlVo
_4/_8_ _ _ _ _ _ _ _ _ _ _ _ _ _
154
~ ~~~;m~c~:9©~---------------
L4940 Series
Fig. 4 - Dropout voltage vs.
output current
Fig. 5 - Dropout voltage vs.
temperature
, -,
Vd
1_
(V)
0..6
C. 5 I---+--+----l---I----l-~+-V---+----l
0..6
0..5
0..4
1----1---+---+--I---+.,..4---+---l
V
0..4
0..3
f--+---+--6-4---f--l----I----l
0..3
0..2
/
1
0..2
V
V
V
/'
./
0..1
0..2
0..4
0..6
0..8
1
1.2
'0 (A)
l-
-25
5.05
to =5mA
..-
LA
I
0.
25
50.
75
100
Tj(·C)
4.90
- 50. -25
Fig. 8 - Output voltage vs.
temperature (L4040V1 0)
G-un"
V.
Vo
(V )
(V)
8.4
8.4 0.
10..10
1'--.. I
r---....
t--.....
V, =10..5 V
10 :5mA
8.3 5
9.9o.
9.80
9.70.
8.2 5
9.60
8.20.
-50.
12.00
t-
-..
0.
25
50.
75
100.
Tj
~C)
VI -7V
10 ·1.5A
30.
0.
25
50
75
100
Tj ("C)
G 6186
10
(mA )
24
12 0.
80.
60.
Iln=o.5A -
T
5-
0.
25
0.
25
50.
75
100
Tj ("C)
ICC
75
T j (OC)
II
Vi =7V
II
20.
"SA
16
V
40.
O.SA
20.
SmA
0.
___ ___________
~
50.
I - 1-1-
1•• ~mA
-50. -25
-'
I
12
10.
r-
G -6~OO 11
10.
20.
Tj (·C)
Fig. 12 - Quiescent current
vs. output current
(L4940V5)
(mA )
15
ICC
75
:~~AI
I
11.50.
-50. -25
Fig. 11 - Quiescent current
vs. input voltage (L4940V5)
10.0.
25
Vi
I.
11.60. -.-
G- UtllZ
10.
(mA )
50.
r- r--...
V
11.7 0.
-so -25
Fig. 10 - Quiescent current
vs. temperature (L4940V5)
/'
11.90
11.80
Vi =12V
10 =5mA
9. so
-25
25
12.1 0.
-.... t-.
taoo .- .....
8.3 0.
0.
~
Fig. 9 - Output voltage vs.
temperature (L4940V12)
,-
Vo
..........
I'-..
4.95
i---
(V)
V
5-
r---.
.............
o1.oL:-
G-U'II'
8.SO
Vi =7V
5.00
V
V
1 -~
-50.
Fig. 7 - Output voltage vs.
temperature (L4940V85)
V
lA_
i ........
0..1
~5A
V
G- &U!ill
Vo
(V)
I
----- __ I---
-.+~--
c--+----+-+---+---l--l----I----l
Fig. 6 - Output voltage vs.
temperature (L4940V5)
25
s.o
75
10.
.....
12.5
15
~ ~~~m~:~~~©'
Vi (V)
0..25
1/
/
V0..50.
0..75
to.
1.251c/.A)
______________
5.;,../8
155
L4940 Series
Fig. 13 - Short circuit cur·
rent VS. temperature
(L4940V5)
Fig. 14 - Peak output cur·
rent vs. input/output dif·
ferential voltage (L4940V5)
Fig. 15 - Low voltage behavior (L4940V5)
G-1401
(V)
/
10=1.5A
3.0
3.0
2.5
Vi '=2.V
/
Yo",O
2.5
..::: ::::::: r- I--
2.0
/
2.0
(
VI ';UV
1.5
1.5
1.0
1.0
0.5
0.5
o
-50 -25
0
25
50
75
100
4
Vo
I
(V)
10=1.5A
;
l-
I
6
8
10
12 Vj-Yo(Y)
Fig. 17 - Low voltage be·
havior (L4940V10)
G-61UI1
r-r--
(V)
/
II
Tj rc)
Fig. 16 - Low voltage behavior (L4940V85)
Vo
6-'4OJ
Vo
ISC
(A)
10
I
I---I-I-+-l--l-I-I---I-+--++-f--j
1---1-1--+-1-0 L=1.-,lSA-I--+-+-l--I.-H
Fig. 18 - Low voltage be·
havior (L4940V12)
Vo~,,-'-r-r'-r-"-T~~
1-+1-+-+'10 =.!,,1.5""A-+-+-++--I-7"+10.0,1-+1-+-+-,--;-+-+-HA-+-
(V)
/
8.0 HI-+-+-+--+-+-¥-H-+-+6.0
f--.-H-++---j,.lCf-+--H-++
4.0
f--.-H---b.4++-+--H-+-+-1
2.0
H ++
/-+-++-H-++-+-+-
/
/
/
If
IT
1
II
Vi (V)
Vi (V)
Fig. 19 - Supply voltage reo
jection vs. frequency
(L4940V5)
G-1317
Fig. 20 - Supply voltage rejection vs. output current
1
(dB)
70
2
3
,
.-
i
I
60
-~
'
1'..1
i
'I
co ·1OO)F":
--:;;pj rtf
ill
!'
-i-
"
"
IT
*TANTALUM
30
0.1
8
i +-1
IT
40
7
Ii
11
Ii
ii
I
I
6
lJI III
110=0.5A
g
50
5
~
I
I
I'
I
II.illll I I
0.3
10
j'
I
III
I (KHz)
G-U1'
Vi
f =120Hz
67
I
Co=221'F
24
-r-....
18
;2
I
66
I
j..- I- j-!
1,\
i
J
I\.,
-
I-
"- 0
-+--
,
I
400
800
1200 1.(mA)
l - I"-...
1/
I
.::.:6/~8_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m~~~lt
156
Fig. 21 - Load dump characteristics (L4940V5)
30
.
68
4
22~
Vi (V)
(V)
1 - --
5
100jAF
I
G-14001i/1
SY R
(dB)
10
0.2
.... ,
0.4
-
v
~
I
!
1.2
1.4 t(l
______________
L4940 Series
Fig. 22 - Line transient
response (L4940V5)
,
(mV)
'10 0
+ '0
+ 20
-100
- 20
-'00
- '0
Ptot
(WI
1"'\
'.
I/"
tv,
...
INPUT
VOLTAGE
INFINITE' EAT SINK
20
I
lo~O.5A
I'""'" C"'I"'"
Co",U,..F
0204010
CHANGE
I
I I
I
V
I
"'"'
IS
10
..
I
"-
V;n,,6Y
v,
Fig. 24 - Total power
dissipation
Fig. 23 - Load transient
response
"-
I
I"-.
\
S'CIW
"'k
;..... IO'CI W
i'- i'- ..
1b~~ -'"'-i'['S;-
20
30
--
~~
6.0
10
~
f;;""-..
(~sJ
Fig. 25 - Distributed supply with on-card L4940 and L4941 low-drop regulators
Fig. 26 - Distributed supply with on-card L4940 and L4941 low-drop regulators
5.-U •
.,0--...----,
11
SV-1.SA
Cj
2.2nF
4,3
K.ll.
GND'O-~---------------~---~
ADVANTAGES OF THESE APPLICATIONS ARE:
On card regulation with short circuit and thermal protection on each output.
Very high total system efficiency due to the switching preregulation and very low-drop postregulations.
---------------Iiii. ~~~m=I!~~ ______________7-'-/8
157
L4940 Series
Fig. 27
~~ ~.~
L ________
f
JE~D~CIL
_______
S
-.J
~'032411
ADVANTAGES OF THIS CONFIGURATION ARE:
- Very high regulation (line and load) on both the output voltages.
12V output short-circuit and thermally protected.
- Very high efficiency on the 12V output due to the very low drop regulator.
_8/;....8_ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ !~~~m~'s~
158
______________. ,.
~
L
IJa..,
SGS-THOMSON
[il"A]D©OO@~[L~©'j]'[ffi@~D©~
L4941
VERY LOW DROP 1A REGULATOR
PRELIMINARY DATA
•
LOW DROPOUT VOLTAGE (450mV TYP
AT 1A)
•
VERY LOW QUIESCENT CURRENT
TO-220
• THERMAL SHUTDOWN
• SHORT CIRCUIT PROTECTION
•
ORDERING NUMBER: L4941
REVERSE POLARITY PROTECTION
INTRODUCTION
The L4941 is a three terminal 5V positive regulator available in TO-220 package, making
it useful in a wide range of the industrial and
consumer applications. Thanks to its very low
input/ output voltage drop, this device is par-
ticularly suitable for battery powered equipment,
reducing consumption and prolonging battery
life. It employs internal current limiting, antisaturation circuit, thermal shut-down and safe
area protection.
BLOCK DIAGRAM
IN
OUT
"
"'1
~
I
PREREGULATOR
AND
PROTECTION
REFERENCE
VOLTAGE
SOA PROTECT_
& ANTISAT_
CIRCUIT r - -
r-
ERROR
.. I
,.."
2~
[J
r--
AMPLIFIER
THERMAL
SHUTDOWN
-
]
,...GNO
3'~
88L4940-oi
June 1988
1/6
159
L4941
CONNECTION DIAGRAM
(Top view)
r--'
GND
rEf)
~
2
OUTPUT
3
::> GROUND
1
:> INPUT
5 - 2568fl
ABSOLUTE MAXIMUM RATINGS
VI
ViR
10
P tot
TJ, Tstg
Forward input voltage
Reverse input voltage (Ro = lOOn)
Output current
Power dissipation
Junction and storage temperature
30
V
-15
Internally limited
Internally limited
-40 to 150
V
THERMAL DATA
Rth J-<:ase
Rth j-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
....;2/....;6_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~m=:.?©~
160
max
max
3
50
______________
L4941
TEST CIRCUITS
Fig. 1 - DC Parameters
Fig.3 - Ripple Rejection
Fig.2 - Load Regulation
S.lJl.
5-1015811
ELECTRICAL CHARACTERISTICS
5-10159/1
(Refer to the test circuits
Tj
= 25°C, C i = O.1~F, Co = 22~F,
unless otherwise specified)
Parameter
Test Conditions
Min.
Typ.
OUTPUT VOLTAGE
5
INPUT VOLTAGE (unless otherwise specified)
7
Max.
Unit
5.2
V
16
V
Vo
Output voltage
10 = 5mA to lA
Vi = 6V to 14V
Vi
Operating input
voltage
10=5mA
6V o
Line regulation
Vi = 6V to 16V
10 = 5mA
5
20
mV
6V o
Load regu lation
10 = 5mA to lA
10 = 0.5A to lA
8
5
20
15
mV
IQ
Quiescent current
10 = 5mA
4
8
10 = lA
20
40
4.8
5
mA
VI =6V
61 Q
,
Quiescent current
change
3
10 = 5mA
mA
VI = 6V to 14V
-10
10 = lA
Vd
Dropout voltage
10 = 0.5A
250
450
10 = lA
450
700
mV
6V o
Output voltage drift
0.6
mV/oC
68
dB
6T
SVR
Supply voltage
rejection
f=120Hz
10 = 0.5A
Ise
Short circuit current
limit
VI = 14V
1.6
2.0
Vi = 6V
1.8
2.2
58
A
Zo
Output impedance
f = 1 KHz
10 = 0.5A
30
mil
eN
Output noise voltage
B = 100Hz to 100KHz
30
/JV/V o
__________________________
~-~~~~~~g~:~~©~
__________________________
~3/_6
161
L4941
Fig. 4 - Dropout voltage vs.
output current
Fig. 5 - Dropout voltage
t"rnperature
Fig. 6 - Output voltage vs.
temperature
VS.
,-.
Vo
0.6
0.6 f-
0:5
0.5
04
0.4
./v
0.3
0.2
0.1
~v
./'
V
/'
0.3
V
/'
-
0.1 f---
0.2 0.4
0.6
O.B
1
10 (A)
1.2
I--
-50 -25
Fig. 7 - Quiescent current
temperature
0
5.0S
-
I-- f.--
0.2
25
...L
-
50
Vi =7V
10 z5mA
lA
75
b:h-:
I
~
5.00
,.- .......
.........
I'..
4.9s
Tj (·C)
15-641311
-so -25
0
25
50
7li
100
G-6'1111
I
IQ
)
TjrC)
Fig. 9 - Quiescent current
vs. output current
G-"12
IQ
(mA)
"
4.9 0
100
Fig. 8 - Quiescent current
vs. input voltage
VS.
39\1/1
(V)
_ ..
(mA)
VI =7V
30
24
25
20
lo,o;1A
16
20
15
-
-so -25
0.5A
-
25
SO
75
100
Tj
rc)
G"·U07
f[
ISC
12
ISC
r-r-,-,.,-,-,.,-r,-,.,-,-r"i'T'1
(A)
f:::::: rI:: rt- r-
i
t--
1.0
162
0.4
0.6
0.8
10 (A)
Fig. 12 - Low voltage behavior
G-6405
Vo
H-+-~~~-T~vo=O
10 =1A
25
so
75
/
1.25,H++-t+-H-++H+H+i
(
-;J;::
o.75,I-+-fl-H-l--+-+-++-+-++-H--t-1
0.5 H + H + H + + - 4 + - t - + + i
0
/V
1-+-l--+H-l--+-t-+-+-+-++-t=F=FI
Vi =6V
O. 5
4/6
I""
L..- ......
H-+-+-+*+-+-T-t-f::-L-"o:-t-t-t-1
1.5
-50 -25
VV
(V )
2.5
o
::;.-
0.2
Fig. 11 - Peak output current vs. input/output differential voltage
1.75H++-It++-1",+-+-fooq;+H+i
1.5
12
Vi (V)
3.0
2.0
16
mA
Fig. 10 - Short circuit current vs. temperature
(A
/ . 10V
.I
SmA -
.
0
lA
12
I
0.5A
10
Vi =6V
20
100
Tj (OC)
10
12
Vr'lo(V)
/
I
L4941
Fig. 14 - Supply voltage rejection vs. output current
Fig. 13 - Supply voltage rejection vs. frequency
Fig. 15 - Load dump characteristics
Vi
SVR
(V)
(dB)
30
~~~--+--+--+"~=~12ho~H-z~~
Co=22 ~F
I
18
;2
- ........
..-- "- -<
24
\
J
"-
f-
-
.
v
f-
(V)
I'.....
J'..i--.
I
0.25
Fig. 17 response
Fig. 16 - Line transient response
•
- 2.
,.
•
-II
,
"t.t
f\
".• '.
.2.
-
G~"
I
INFINITE
20
1
Vin,,6V
10·0.SA
IlOAi cu
C o .. 22 .... F
NT
i--.
20Ch;" ...
...
CHANGE
10
20
30
0204060
t
EA
SINK
1\
i'
15
10
15
INPUT
VOLTAGE
I
I
1
1./
-200
V,
,V,
1.l.. t(sec)
1
(W)
f\(7
1.2
0.4
Fig. 18 - Totale power dissipation
G-un,
Load transunt
(mV )
!m""
+ ,.
0.2
0.5
r-....
r--.
,..... r-..
WC/W
()Is)
NO HEAT- SINK
I-,
\
S'C/W
"""l
r"'-t---I'
t-...::
I
l,us)
25
1\
50
75
100
Tamb("C)
Fig. 19 - Distributed supply with on-card L4940 and L4941 low-drop regulators
SV-1.SA
VI 0----<>-------
L296
11
5Y-1.5A
1.2
K.ll
Ci
2.2nF
4.3
K.ll
GNDO-~~----------------------------~------~
5-1032611
ADVANTAGES OF THESE APPLICATIONS ARE:
On card regulation with short circuit and thermal protection on each output.
Very high total system efficiency due to the switching preregulation and very low-drop postregulations.
-------------- ~ ~~~m~
5/6
163
L4941
Fig. 20 - Distributed supply with on-card L4940 and L4941 low-drop regulators
"10-_--2.1
5Y-1A
5-10325/1
,;.;6/;".:6_ _ _ _ _ _ _ _ _ _ _ _ _
164
~ ~~;m=lf--------------
L4960
2.SA POWER SWITCHING REGULATOR
PRELIMINARY DATA
•
2.5A OUTPUT CURRENT
•
5.1V TO 40V OUTPUT VOLTAGE RANGE
•
PRECISE (± 2%) ON-CHIP REFERENCE
•
HIGH SWITCHING FREQUENCY
•
VERY HIGH EFFICIENCY (UP TO 90%)
•
VERY
•
SOFT START
•
INTERNAL LIMITING CURRENT
FEW
EXTERNAL COMPONENTS
• THERMAL SHUTDOWN
The L4960 is a monolithic power switching
regulator delivering 2.5A at a voltage variable
from 5V to 40V in step down configuration.
Features of the device include current limiting,
soft start, thermal protection and 0 to 100%
duty cycle for continuous operation mode.
The L4960 is mounted in a Heptawatt plastic
power package and requires very few external
components.
Efficieni: operation at switching frequencies
up to 150KHz allows a reduction in the size
and cost of external filter components.
Heptawatt
ORDERING NUMBER: L4960 (Vertical)
L4960H (Horizontal)
ABSOLUTE MAXIMUM RATINGS
V 3 , Vs
V2
13
15
Ptot
lj, Tstg
Input voltage
Input to output voltage difference
Negative output DC voltage
Negative output peak voltage at t = O.l~s; f
Voltage at pin 3 and 6
Voltage at pin 2
Pin 3 sink current
Pin 5 source current
Power dissipation at Tease ..;; 90°C
Junction and storage temperature
50
50
-1
= 100KHz
-5
5.5
7
1
20
15
-40 to 150
V
V
V
V
V
V
mA
mA
W
°c
BLOCK DIAGRAM
'.
June 1988
1/13
165
L4960
CONNECTION DIAGRAM
~DI
L
!t-119!1
OUTPUT
SOFT START
OSCILLATOR
GNO
!:
FREQ. COMP
FEEDBACK INPUT
INPUT
Tab connected to pin 4
THERMAL DATA
Thermal resistance junction-case
Thermal resistance junction-ambient
max
max
4
50
PIN FUNCTIONS
N°
NAME
1
SUPPL Y VOLT A~E
Unregulated voltage input. An internal regulator powers
the internal logic.
2
FEEDBACK INPUT
The feedback terminal of the regulation loop. The
output is connected directly to this terminal for 5.1V
operation; it is connected via a divider for higher voltages.
3
FREQUENCY
COMPENSATION
A series RC network connected between this terminal
and ground determines the regulation loop gain characteristics.
4
GROUND
Common ground terminal.
5
OSCILLATOR
A parallel RC network connected to this terminal
determines the switching frequency.
6
SOFT START
Soft start time constant. A capacitor is connected between this terminal and ground to define the soft start
time constant. This capacitor also determines the average
short circuit output current.
7
OUTPUT
Regulator output.
FUNCTION
~2/_1_3_______________________ ~!il;~?~~~
166
--------------------------
L4960
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, TJ
= 2SoC,
VI
= 35V,
unless
otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Vref
40
V
9
46
V
DYNAMIC CHARACTERISTICS
Vo
Output voltage range
V, = 46V
10= lA
VI
Input voltage range
V 0 = V ref to 36V
10 = 2.5A
Il Vo
Line regulation
VI = 10V to 40V
IlVo
Load regulation
Vrsf
10 = lA
15
50
mV
Vo=Vrsf
10 = 0.5A to 2A
10
30
mV
I nternal reference voltage
(pin 2)
V, =9V to 46V
10= lA
5.1
5.2
V
Il V ref
IlT
Average temperature
coefficient of refer. voltage
TJ = O°C to 125°C
10 = lA
0.4
Vd
Dropout voltage
10=2A
1.4
10m
Maximum operating load
current
V, =9V to 46V
Vo = V rsf to 36V
2.5
17L
Current limiting threshold
(pin 7)
VI = 9V to 46V
V 0 = V ref to 36V
3
ISH
Input average current
V, = 46V;
!J
Efficil;mcy
f = 100KHz
Vo = V rsf
75
%
10=2A
Vo = 12V
85
%
50
56
d8
85
100
SVR
Supply voltage ripple
rejection
Vo = V rsf
5
output short-circuit
Il V, = 2V rms
fr,pp'e = 100Hz
Vo = V ref
f
Switching frequency
-M
Voltage stability of
switching frequency
V, = 9V to 46V
IlV I
Ilf
IlTJ
Temperature stability of
switching frequency
T J = O°C to 125°C
f max
Maximum operating
switching frequency
Vo = V,ef
Tsd
Thermal shutdown
junction temperature
mVrC
3
V
A
30
4.5
A
60
mA
10 = lA
10 =2A
120
115
KHz
0.5
%
1
%
150
KHz
150
°c
------------- ~ 1~I~m&~~14 ___________
--'3/'--13
167
L4960
ELECTRICAL CHARACTERISTICS (continued)
Parameter
TBSt Conditions
Min.
I
Typ.
Max.
Unit
30
40
rnA
15
20
rnA
1
rnA
DC CHARACTERISTICS
11Q
Quiescent drain current
100% duty cycle
pins 5 and 7 open
VI =46V
0% duty cycle
-17L
Output leakage current
0% duty cycle
SOFT START
1650
Sou rce cu rrent
100
130
150
p.A
1651
Sink current
50
70
120
p,A
ERROR AMPLIFIER
V3H
High level output voltage
V 2 = 4.7V
13 = l00p,A
V3L
Low level output voltage
V 2 = 5.3V
13 = 100p,A
1351
Sink output current
V 2 = 5.3V
100
150
p.A
-1350
Source output current
V 2 = 4.7V
100
150
p.A
12
Input bias current
V 2 = 5.2V
Gv
DC open loop gain
V3 = 1V to 3V
3.5
V
0.5
2
46
55
10
V
IJA
dB
OSCILLATOR
-15
~4/~1_3
168
5
Oscillator source current
_______________________
~1~~~
rnA
__________________________
L4960
CIRCUIT OPERATION (refer to the block diagram)
The L4960 is a monolithic stepdown switching
regulator providing output voltages from 5.1V
to 40V and delivering 2.5A.
The regulation loop consists of a sawtooth oscillator, error amplifier, comparator and the output
stage. An error signal is produced by comparing
the output voltage with a precise 5.1 Von-chip
reference (zener zap trimmed to ± 2"10).
This error signal is then compared with the sawtooth signal to generate the fixed frequency
pulse width modulated pulses which drive the
output stage.
The gain and frequency stability of the loop can
be adjusted by an external RC network connected to pin 3. Closing the loop directly gives
an output voltage of 5.1 V. Higher voltages are
obtained by inserting a voltage divider.
Output overcurrents at switch on are prevented
by the soft start function. The error amplifier
output is initially clamped by the external capa-
citor Css and alloWed to rise, linearly, as this
capacitor is charged by a constant current source.
Output overload protection is provided in the
form of a current limiter. The load current is
sensed by an internal metal resistor connected to
a comparator. When the load current exceeds a
preset threshold this comparator sets a flip flop
which disables the output stage and discharges
the soft start capacitor. A second comparator
resets the flip flop when the voltage across the
soft start capacitor has fallen to O.4V.
The output stage is thus re-enabled and the output voltage rises under control of the soft start
network. If the overload condition is still present
the limiter will trigger again when the threshold
current is reached. The average short circuit current is limited to a safe value by the dead time
introduced by the soft start network. The
thermal overload circuit disables circuit operation when the junction temperature reaches
about 150°C and has hysteresis to prevent
unstable conditions.
Fig. 1 - Soft start waveforms
05CI~lATOR
OUTPUT
NOMINAL
ERROR AMP.----"
OUTPUT
OUTPUT
C URRE NT
S _5835
Fig. 2.- Current limiter waveforms
CURRENT
LIMITER
TRIGGERS
r--
LIMIT
::::,,"
CURRENT
- t- .L-.L-.L-.L.L-.L-L-L-L-Ll-L-Ll-L-L-L.L.:_-_~_- "'- -!-:~.
-
-
-
S_179'
__________________________
~~~~~~~~~
-
:::----;
I
______________________~5~/13
169
L4960
Fig. 3 - Test and application circuit
Rl
R4
15Kll
Rj
L1
Vi ().---~
1000
/.IF
5
Cl
C2
7
L 4960
Vo
150}JH
4
01
2.2
R2
nF
4.3Kfi
SGSBR20
OR
BYWBO
&-77t8/2
C6, C7: EKR (ROE)
L 1 = 150fJ H at 5A (COG EMA 946042)
CORE TYPE: MAGNETICS 58206-A2 MPP
N" TURNS 45, WIRE GAUGE: 0.8mm (20 AWG)
-
Fig. 5 - Quiescent drain
current vs. supply voltage
(100% duty cycle)
Fig. 4
Quiescent drain
current vs. supply voltage
(0% duty cycle)
"0
"0
"0
(rnA)
Fig. 6 - Quiescent drain cur·
rent vs. junction temperature (0% duty cycle)
(mA)
(mA)
I-+-+-+-+-++---lv:;-='.''''o+--I
25
v
5V
20
35
15
30
17
15
tttt:t:tmn
25
Il
~~~+-+-+-+-4-4-~~
'0
i
'0
20
30
40
Vi (v)
20
'0
20
30
4.0
~6/~1_3________________________ ~~~~~~?~~
170
I ... 1.-
Vi tv)
-25
0
25
50
75
100
TJ{"Cl
___________________________
L4960
Fig. 7 - Quiescent drain current vs. junction temperature (100"10 duty cycle)
1,Q r--r-,....,-r---,-r-r-T·.::.-'1""
..,
(mA) f-+-++-+-I-\-;;'--:j';~35~'+-+--1
Fig. 8 - Reference voltage
(pin 2) vs. VI
-
....
' •• , r-,.,----,--,----r--,-,--+-''I'--,
('I
~+-+--+--+--+';--o".,••-r-+~---f
(,)
Fig. 9 - Reference voltage
vs. junction temperature
(pin 2)
.
¥l=lSY
40
""'
."
5
5.1S0~+-+--+--+--+~-t-+--I----i
~+--I--r-+~-~+-+--I-~
5.100
5.125~+-+--+--+--+-I-+--+--I----i
---
30. ~+--I--:::J.-r""9I-"'--t-+-+--I-~
20~+--I--r-+~-t-+-+--I-~
-25
0
25
50
75
lOa
....
•. 075~+-+--+--+--+-If-+--+--I----i
5.0s0f-+-+-+-+-I-If-----+--+-+--1
2.f-+-++-+-I-t-+-+--I-~
Fig. 10 - Open loop frequency and phase responde
of error amplifier
30
20
'0
Tj ("C)
r-. r-...
V V
5""
_25
25
50
75
100
1,('0
Fig. 12 - Switching frequency vs. junction temperature
Fig. 11 - Switching frequency vs. input voltage
G,
(dB I
1KH z }
60
50
Vid5Y
Yo.vr.,
'-\
-e' ,\
40
30
40
"\--
\
20
10
\
104
110
102
10.
_80
100
-""
.
-110
100
os
"
f-
I- i--
90
1\
\
_10
10
100
lK
KlK
lOOK
1M
t (Hz)
10
Fig. 13 - Switching frequency vs. R2 (see test circuit)
IS
20
25
Fig. 14 response
30
35
'0
45
·",
··
100
-2S
ViIY)
Line transient
G-411
'1'
f
6-6070
"'Hz I
IItF'UT VOLTAGE
'O~'RE~
10 .. lA
0
25
".'\
.
r-. te·,.nF
,
50
11111
IIII
,0
-so
"
7S
ISO TJ (-c.J
Load transient
G-'071
1
"
(
LOAD CURRENT
- r-
,
t-
-
so
OUTPUT VOlTAGE CHANGE
I\,
-so
~I
6'0
1m'I
"
RICKA)
100 125
1
(
2
0
(m' I
SO
Fig. 15 response
3
C,l-UnF"-
10
(KHZ I
~+-+--+--+-+-I"'"I10-;.,!...:-t-l-l
.........
t Ims)
I
0.5
1.5
I (ms)
------------- ~ I~m&'~lt ____________
7/:..:..;,13
171
L4960
Fig. 16 - Supply voltage
ripple rejection vs. frequency
".
Fig. 17 - Dropout voltage
between pin 1 and pin 7
vs. current at pin 7
6-6012
(j'6086
'0
1 IIJIIIII
(dB I
Fig. 18 - Dropout voltage
between pin 1 and 7 vs.
junction temperature G-6013
'0
(V)
A'Ii"ZYIiIoIS
"j:35V
Vo=Vret
70
10 ",1,.,
60
50
r--
!
1.6
I
'-
'0
.-,
1.2
30
o.
20
I..:::: TJ:~!~:~
2S"C
fill' rP"
1,6
V
~A
1-
--I-
1.2
10
0.'
100
lK
0.5
tCH z)
Fig. 19 - Power dissipation
derating curve
1.5
2.5
G-
Ptot
~
(WI
('J,)
'11 .. 35';'
10
-~~~
"""'
'''
'0
\
~_ I--
60
~~ 6'o;:-j----1~...\- I--
50
iJ../J'+{>
~
20
40
70
I~
60
80
\\
""'" '"
~
100KHz
200KHz
(.,.)
~+--t.;'O-:'+"R-E--1Ff-+--+-+-t-t--i
90
~+-+-t----1f-+--+-+-t-t--i
60
~+-+-t-~+'OWIO~OEC-r-+-+-1
f =50KH
I--
I
BYW80
I
120 Tamb(OC I
0.5
1
1.5
2.5
10 {AI
05
1.5
Fig. 23 - Efficiency vs.
output voltage
~r-'--'-'--'--r-'~~~
(.t.)
~~~~.,L"-f~-+--~4--+---1
f '" 100KHz
~+-r--+-+---+-+--+---1
I
v) =15'1
.O~~~~
70 ~-,&""",+--+-+--+--=J5't'-+-----1
'0~~-+--+~~-+-+--+---1
DIODE
~~,_+--+'_VW_'TO_+--+___
t---
---+-- __I--+--_~+_+_
1--1
f=50~
90
80
~
~
'f
l.,,::: ~-
KHZ
10:2A
~j ::~~80- f-
70
6.
I
0.5
8/13
172
100
I
~
Fig. 22
Efficiency vs.
output current
90
50
~
I
,,,LKHz
I-50KHz
DIODE
BVWBO
'0
\
100
- Vo '" 'Ire-'
0
17: 1"
Fig. 21 - Efficiency vs.
output current
Fig. 20 - Efficiency vs.
output current
60"
6-6018
15
·25
'7 (AI
-
1.5
2.5
10 (A)
10
15
20
2S
Va (V)
10 (AI
L4960
APPLICATION INFORMATION
Fig. 24 - Typical application circuit
L1
71--_-..../yY""'>.-.......-_~---.,.() Vo
Vi
150,uH
L4960
6
Dl
5
2
4
SGS8R20
OR
BYWao
C6
40V
C7
C5
Cl
10Q).IF 63V
R2
4.3Kn
GNO
GNO
5- 9322/1
C1' C6, C'Z: EKR (ROE)
0 1 : BYW8D OR 5A SCHOTTKY DIODE
SUGGESTED INDUCTOR: LJ. = 15DI'H at 5A
CORE TYPE: MAGNETICS 5820.6 - A2 - MPP
N° TURNS: 45, WIRE GAUGE: D.8mm (20. AWG),
U15/GUP15: N° TURNS: 60., WIRE GAUGE: D.8mm (20. AWG),
COGEMA946D42
AIR GAP: lmm, COGEMA 9690.51.
Fig. 25 - P.C. board and component layout of
the Fig. 24 (1 : 1 scale)
Resistor values for
standard output voltages
____________
.~
...,l.
Vo
R3
R4
12V
15V
18V
24V
4.7Kn
4.7Kn
4.7Kn
4.7Kn
6.2Kn
9.1Kn
12Kn
18Kn
SGS-THOMSON _ _ _ _ _ _ _ _ _ _ _9'---/13
~D@rnl@rn~rn©'ii'OO@lilIa
173
L4960
APPLICATION INFORMATION (continued)
Fig. 26 - A minimal 5.1V fixed regulator; Very few component are required
v·
I
~IOO/JF
sov
I
l4960
2'!r
n~
:r
S
Q
s.y
INHIBIT
FLIP
FLOP
Q
R
0
S_179914
COGEMA946042 (TOROID CORE) 4
969051 (U15 CORE)
EKR (ROE)
Fig. 27 - Programmable power supply
4700I'F
sov
EYF
r-~------------------~
150",H
~~~/V~~~-.---~-~
SGSBR20
..
OR
BYW80
40V
Vo = 5.1 V to 15V S_7800t2 L..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _6.-_ _ _ _ _ _ _ _---J
10 = 2.5A max
Load regulation (1A to 2A) - 10mV (V o = 5.1V)
Line regulation (220V ± 15% and to 10 = 1A) = 15mV (V o = 5.1V)
.:.;lO:!./::..:13~_ _ _ _ _ _ _ _ _ _ ~ !~m~
174
------------
L4960
APPLICATION INFORMATION (continued)
Fig. 28 - Microcomputer supply with + 5.1V. -5V. + 12V and -12V outputs
Y103SV
FUSE
~~'J-J-~--FI~~O~~~--~~---'
SOY
EVF
:r:
*L~IGr2
.1N5822
-5v
I
:]2nF
O.2A
100 l'F
EKR
+5.1
v
L-----F-t---+----t--03.5A
lK.Il
RESET
~----------------~----------------o
INHIBIT
*
SGSBR20 OR
Byw80
-12V
L----I~1--o100mA
175
L4960
APPLICATION INFORMATION (continued)
Fig. 29 - DC-DC converter 5.1V/4A, ± 12V/2.5A; a suggestion how to synchronize a negative output
150pH
30V nom
L4960
Ll
*
L----*--+-+---------------------~~----~~--------_;~GND
. :J
120pF
L4960
2200}'F
L3
*
L----<~...,
EYF
2x 220pF
40V
EKR
6.2Kll.
4.7Kll.
-12V/2.SA
L---~------------~-----*-S-G-S-8-R-20--0R~B~YW--80--~~S--.-J-2J~12~--~~
L1, L3 = COGEMA 946042 (969051)
L2 = COGEMA 946044 (946045)
010 O2 • 03 = SGS8R20 or BYW80
Fig. 30 - In multiple supplies several L4960s can be synchronized as shown
L4960
5
s - 9324
.:.12:::./.:..13.:...-_ _ _ _ _ _ _ _ _ _ _
176
l4960
I
"--
iiii. !~tm~~JI -------------
L4960
APPLICATION INFORMATION (continued)
Fig. 31 - Regulator for distributed supplies
VjO-_---'-I
L4960
MOUNTING INSTRUCTION
The power dissipated in the circuit must be
removed by adding an external heatsink.
Thanks to the Heptawatt package attaching the
heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink
and the package it is better to insert a layer of
silicon grease, to optimize the thermal contact,
no electrical isolation is needed between the
two surfaces.
Fig. 32 - Mounting example
------------- ~ ~~tm?v~JI ____________
1_3/=--13
177
L4962
1.SA POWER SWITHING REGULATOR
PRELIMINARY DATA
•
•
•
•
•
•
•
•
•
1.5A OUTPUT CURRENT
5.1V TO 40V OUTPUT VOLTAGE RANGE
PRECISE (± 2 %) ON-CHIP REFERENCE
HIGH SWITCHING FREQUENCY
VERY HIGH EFFICIENCY (UP TO 90%)
VERY FEW EXTERNAL COMPONENTS
SOFT-START
INTERNAL LIMITING CURRENT
THERMAL SHUTDOWN
plastic package and Heptawatt package and
requires very few external components.
Efficient operation at switching frequencies
up to 150KHz allows a reduction in the size
and cost of external filter components.
The L4962 is a monolithic power switching
regulator delivering 1.5A at a voltage veriable
from 5V to 40V in step down configuration.
Features of device include current limiting,
soft start, thermal protection and 0 to 100%
duty cycle for continuous operating mode.
The L4962 is mounted in a 16-lead Powerdip
Heptawatt
Powerdip
(12 + 2 + 2)
ORDERING NUMBER:
L4962 (12 + 2 + 2 Powerdip)
L4962E (Heptawatt)
L4962EH (Horizontal Heptawatt)
ABSOLUTE MAXIMUM RATINGS
V ll , VIS
V10
III
114
Ptot
50
50
-1
Input voltage
Input to output voltage difference
Negative output DC voltage
Output peak voltage at t = O.lt./s, f = 100KHz
Voltage at pin 11, 15
Voltage at pin 10
Pin 11 sink current
Pin 14 source current
Power dissipation at Tp1ns ~ 90°C (Powerdip)
Tease ~ 90°C (Heptawatt)
Junction and storage temperature
-5
5.5
7
1
20
4.3
15
-40 to 150
V
V
V
V
V
V
mA
mA
W
W
°c
BLOCK DIAGRAM
L4962
Pin X
Powerdip
Pin (Xl = Heptawatt
June 1988
1/12
179
L4962
CONNECTION DIAGRAMS
(Top view)
N.C.
15
N.C
OUTPUT
15
SOFT START
N.C
1i.
OSCIl.LATOR
GNO
13
GND
GND
12
GNO
N.C
11
FREQ..COMP.
10
INPUT
FEEDBACK
~DI
L
OUTPUT
50FT START
OSCILLATOR
GNO
!:
~_n95
FREQ. COMP
FEEDBACK INPUT
INPUT
Tab connected to pin 4
N.C
N.C
5·"645
THERMAL DATA
Rth J-case
RthJ-Plns
RthJ-amb
Heptawatt
Thermal resistance junction-case
Thermal resistance junction-pins
Thermal resistance junction-ambient
Powerdip
max
max
max
• Obtained with the GND pins soldered to printed circuit with minimized copper area.
PIN FUNCTIONS
HEPTAWATT
POWERDIP
NAME
1
7
SUPPLY VOLTAGE
Unregulated voltage input. An internal regulator powers the internal logic.
2
10
FEEDBACK INPUT
The feedback terminal of the regulation loop.
The output is connected directly to this terminal for 5.1 V operation; it is connected via a
divider for higher voltages.
3
11
FREQUENCY
COMPENSATION
A series RC network connected between this
terminal and ground determines the regulation
loop gain characteristics.
4
4,5,12,13
GROUND
Common ground terminal.
5
14
OSCILLATOR
A parallel RC network connected to this terminal determines the switching frequency. This
pin must be connected to pin 7 input when the
internal oscillator is used.
6
15
SOFT START
Soft start time constant. A capacitor is connected between this terminal and ground to
define the soft start time constant. The capacitor also determines the average short circuit
output current.
7
2
OUTPUT
Regulator output.
1,3,6,
8,9,16
1.::;2_ _ _ _ _ _ _ _ _ _ _ _
.::;2/0..::
180
FUNCTION
N.C.
~ ~~~~m?lt:~~:
-------------
L4962
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25°C, VI
35V, unless
otherwise specified)
Parameter
Test Conditions
DYNAMIC CHARACTERISTICS
Vo
Output voltage range
VI = 46V
10= lA
VI
I nput voltage range
Vo = V,ef to 36V
10 = 1.5A
I::.Vo
Line regulation
VI = 10V to 40V
I::.Vo
Load regulation
Vo = V,ef
10 = 0.5A to 1.5A
Vref
I nternal reference voltage
(pin 10)
VI =9V to 46V
10 = lA
I::.Vref
I::.T
Average temperature
coefficient of refer. voltage
T j = O°C to 125°C
10 = lA
0.4
Vd
Dropout voltage
10= 1.5A
1.5
10m
Maximum operating load
current
VI = 9V to 46V
Vo = V ref to 36V
1.5
12L
Current limiting threshold
(pin 2)
VI = 9V to 46V
Vo = V ref to 36V
2
ISH
Input average current
Vi = 46V;
11
Efficiency
f = 100KHz
Vo = V ref
70
%
10= lA
Vo = 12V
80
%
50
56
dB
85
100
SVR
f
Supply voltage ripple
rejection
Vo = Vref
I::.VI = 2V rms
frlPPle = 100Hz
Vo = Vref
Voltage stability of
switching frequency
VI = 9V to 46V
Temperature stability of
switching frequency
Tj = O°C to 125°C
f max
Maximum operating
switching frequency
Vo = V,ef
Tsd
Thermal shutdown
junction temperature
I::. VI
M
I::.Tj
40
V
9
46
V
15
50
mV
8
20
mV
5.1
5.2
V
10 = lA
5
output short-circuit
mV/oC
2
V
A
15
3.3
A
30
mA
10 = lA
Switching frequency
M
V,ef
10= lA
120
115
KHz
0.5
%
1
%
150
KHz
150
°c
181
L4962
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
Min.
Typ.
I I
Max.
Unit
30
40
rnA
15
20
rnA
1
rnA
DC CHARACTERISTICS
17Q
Quiescent drain current
100% duty cycle
pins 2 and 14 open
0% duty cycle
-12L
Output leakage current
VI = 46V
0% duty cycle
SOFT START
11550
Source current
100
130
160
/J A
11551
Sink current
50
70
120
/JA
ERROR AMPLIFIER
VllH
High level output voltage
VI0 = 4.7V
III = 100/JA
VllL
Low level output voltage
V10 = 5.3V
III = 100/JA
111 51
Sink output current
V1 0 = 5.3V
100
150
/JA
-Iuso
Source output current
V 1 0 = 4.7V
100
150
/JA
110
I nput bias current
VI0 = 5.2V
Gv
DC open loop gain
V ll = IV to 3V
V
3.5
0.5
2
46
55
10
V
jJA
dB
OSCILLATOR
1-114
182
Oscillator source current
5
rnA
L4962
CIRCUIT OPERATION (refer to the block diagram)
The L4962 is a monolithic stepdown switching
regulator providing output voltages from 5.1 V
to 40V and delivering 1.5A.
The regulation loop consists of a sawtooth oscil·
lator, error amplifier, comparator and the output
stage. An error signal is produced by comparing
the output voltage with a precise 5.1V on-chip
reference (zener zap trimmed to ± 2%).
This error signal is then compared with the sawtooth signal to generate the fixed frequency
pulse width modulated pulses which drive the
output stage.
The gain and frequency stability of the loop can
be adjusted by an external RC network connected to pin 11. Closing the loop directly gives
an output voltage of 5.1 V. Higher voltages are
obtained by inserting a voltage divider.
Output overcurrents at switch on are prevented
by the soft start function. The error amplifier
output is initially clamped by the external capa-
citor Css and allowed to rise, linearly, as this
capacitor is charged by a constant current source.
Output overload protection is provided in the
form of a current limiter. The load current is
sensed by a internal metal resistor connected to
a comparator. When the load current exceeds a
preset threshold this comparator sets a flip flop
which disables the output stage and discharges
the soft start capacitor. A second comparator
resets the flip flop when the voltage across the
soft start capacitor has fallen to O.4V.
The output stage is thus re-enabled and the output voltage rises under control of the soft start
network. If the overload condition is still present
the limiter will trigger again when the threshold
current is reached. The average short circuit current is limited to a safe value by the dead time
introduced by the soft start network. The
thermal overload circuit disables circuit operation when the junction temperature reaches
about 150°C and has hysteresis to prevent
unstable conditions.
Fig. 1 - Soft start waveforms
05CILlATOR
OUTPUT
NOMINAL
ERROR AMP. .......
OUTPUT
OUTPUT
CURRENT
::. .. 5835
Fig. 2 - Current limiter waveforms
12
5-9398
___________________________
~~~~~~
________________________~5/~1~2
183
L4962
Fig. 3 - Test and application circuit (Powerdip)
R1
R4
11
7
Vi
10
L1
2
L4962
VO
150 J.lH
C1
01
2x220}JF
40V
1000IJF
63V
C7
C6
°
1) 1 : BYW98 or 3A Schottky diode, 45V of VRRM;
2) L1: CORE TYPE - MAGNETICS 58120 - A2 MPP
N° TURNS 45, WIRE GAUGE: 0.8mm (20 AWG)
3) CS, C7 : ROE, EKR 220ltF 40V
Fig. 4 - Quiescent drain
current vs. supply voltage
(0% duty cycle)
I,.
Fig. 5 - Quiescent drain
current vs. supply voltage
(100% duty cycle)
Fig. 6 - Quiescent drain
current vs. junction tern·
perature (0% duty cycle)
{mAl f-+-+-+-+-+-+-l-I-I-
(mAl f-+-+-+-+-+-I-luyc::;,J,.""yI-
G-606S
I
I
{m' l
". r-r-r-r-r-r-r-,---rr--
I
25
." I-+-+-+-+-+-+-+-+-+-
I
20
I
i
IS
10
1
1
;
1
10
20
30
40
Vi (V)
10
20
30
4.0
VI (V)
-25
0
25
50
15 100
Tj("(;)
....:S/~1.::.2 _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~I~mo~~I------------184
L4962
Fig. 8 - Reference voltage
(pin 10) vs. VI rdip) vs. VI
Fig. 7 - Quiescent drain
current vs. junction temperature (100% duty cycle)
Fig. 9 - Reference voltage
(pin 10) vs. junction temperature
r--,--r-r---r--c,-,-,.+"T'c,
Vrel
,-,.,---,-,--,-,-,--\,,-,"1-'--,
{mAl I-+-+--+-+--+-f;;--:Yj"-;',,c;;-,-+-+----J
(VI
1-+-++-+--+',,-C;.'~A-+-+--+---1
I'Q
-
'IV...I
Y,,,l§V
lo"lA
5.'25
5.'501-+-++-+--+-1-+-+-+--1
5.1251-+-+--+-+--+-1-+-+-+---1
5.100
50751-+-+--+-+--+-1-+-+-+---1
5.0501-+-+--+-+--+-+- -+-+-+--1
201-+-+--+-+--1-1-+-+-+--1
-25
0
25
50
15
10
a,
,a
"
'e'
"
-40
,,\
'" '
\
10
\
.0
-10
....
f
100
lK
10K
lOOK
100
_120
"
_I"
',(«:'
100
7!l
I-+-++-+--+~I-+,:-;.::,sv::-H
lOa
1-+f-"'--::::±=I-+-+-+-+-+--tH
.5
90
\
t (Hzl
1M
10
15
20
25
Fig. 14 response
30
35
'5
40
Y,P")
_25
G~
6-6010
INPUT VOLTAGE
VO~'RE~
0
25
SO
7S
100 125
ISO
~
(-tJ
Fig. 15 - Load transient
response
Line transient
V,
(
.,
Lolo C~RREINT
VI
Ic;tA
3
"
lOa
1KHZ)
96
Fig. 13 - Switching frequency vs. R2 (see test
circuit)
"11ft
·
· "."
·· "
,
·
50
Fig. 12 - Switching frequency vs. junction temperature
102
_.0
2S
1-+-+--+-+--+-1-1"0"'" 110 I-+--t--t--+--+-I-+--r--+----j
10. I-+-+--+-+--+-I-+--+-+-l
)
(
_25
104
\
20
'0
30
1KH z}1-+-+-+--+-+--1"'110-0.,+-...-+--1'-1
(dB )
50
20
Fig. 11 -- Switching frequency vs. input voltage
Fig. 10 - Open loop frequency and phase response
of error amplifier
60
"l5Il
5.02 5
Tj (OC)
100
-
r--..
V
/
5.07 5
- r
2
o
( AI
I-
-
1
(J.\SnF
'V)
(mV
50
-,0
Cl-Z.ZnF"-
IIIII
"
'\
10
I\,
OUTPUT VOLTAGE CHANGE
-'0
II
'V o
(mVI
.
"'
__________________________
10
.0
OUTPUT VOLTAGE CHANGE
t emsl
R1IKIU
~I~~;~~
0.'
I.'
______________________
t ems)
~7/__
12
185
L4962
Fig. 17 - Dropout voltage
between pin 7 and pin 2 vs.
current at pin 2
Fig. 16 - Supply voltage
ripple rejection vs. frequency
..
1 11:.11111
70
Yo=-Vrri
G-
,SY.,
.
AVj=ZVRM~
'iJ=J5V
Fig. 18 - Dropout voltage
between pin 7 and 2 vs.
junction temperature
Vo r-'--r-.~;-'-'--r~~~
vor-'--r-.--~'-'--r~~~
Vi .3SV
6.
DIODE
0.'
0.75
1.25
10 CA)
0.5
'0.75
1."
100KHz
8.
;;..-'
/.'?
r
Vi "J5Y
10 .111.
8.
/. :;--
..-:::: -;:::; ~
20
100KHz
/;
Vi =35'1
10=111.
DIODE
9VW98
YSII:JioO
IS
O-lU"1
~KHz
9.
OIOOt:
I.
Fig. 24-Maximum allowable
power dissipation vs. ambient temperature (Powerdip)
Plot
7.
70
1.25
0.75
G-60U
,
.-!:.SOKHZ
~~
0.'
10 tA)
Fig. 23 - Efficiency vs.
output voltage
G-601l
90
VSKJI.O
V5K340
Fig. 22 - Efficiency vs.
output voltage
,
DIODE
OKlDE
BYW98
10
"
20
....
so
~81_1_2_______________________ ~I~I;~~n --~------~--------------
186
L4962
APPLICATION INFORMATION
Fig. 25 - Typical application circuit
L1
Vj
0--_---17
21-_--'
~~~-4~_ _~~Vo
L4962
15
II;
01
1;.5.12,13 11 10
BYW98
C6
C5
Cl
10 OfF 63V
GNO
R2
t..31<11
GNO
s- 9340
Cl. C6. C7: EkR (ROE)
0 1 : BYW98 OR VISK340 (SCHOTTKY)
SUGGESTED INDUCTORS (Ll): MAGNETICS 58120 - A2MPP - 45 TURNS - .... ,.: GAUGE 0.8mm (20AWG) COGEMA 946043
OR U15. GUP15. 60 TURNS lmm. AIR GAP O.8mm (20AWG) - COGEMA969051
Fig. 26 -
p.e. board and component layout of the circuit of Fig. 25 (1
: 1 scale)
Resistor values for
standard output 7 voltages
Vo
R3
R4
12V
15V
18V
24V
4.7Kn
4.7Kn
4.7Kn
4.7Kn
6.2Kn
9.1Kn
12Kn
18Kn
------------- ~ !~t~ ___________.=.:9/~12
187
L4962
APPLICATION INFORMATION (continued)
Fig. 27 - A minimal 5.1 V fixed regulator; very few components are required
INHIBIT
FLIP
FLOP
o
R
5-&399"
4 5,12,13
* COGEMA 946043 (TOROID CORE)
969051
(U15 CORE)
** EKR (ROE)
Fig. 28 - Programmable power supply
1 N4002
•
20Y_
:i~
2200,.,
50Y
EYF
~2
~
2
.---
15
L4962
2.21J F
2.2"F:
~
I
9.1
K1l.
:io
pF
:i
~
~~~=
40Y
)
~OK.Il
10
11
:~JnF
,.----
2x
~ BYW98
14 4.5.12.13
:i~
-
I~
1
10Y_
15
)0
K.Il
Kll
~
9J~2/1
Vo = 5.1V to 15V
10 = 1.5A max
Load regulation (0.5Ato 1.5A) = 10mV (V o =5.1V)
Line regulation (220V ± 15% and to 10 = 1A) = 15mV (V o = 5.1V)
~10~/~12~_____________________ ~1~~~~~
188
__________________________
L4962
APPLICATION INFORMATION (continued)
Fig. 29 - DC-DC converter 5.1V/4A, ± 12V/1A. A suggestion how to synchronize a negative output
L4962
+12V/IA
11
BVW98
2 x 220I"F
_40V
EKR
L----*--+-+---------------------~~------~--------~~GND
+5.1V14A
":1
120pF
~H
L3
BVW98
2x220f'f
40V
EKR
S.2IHl.
4.7K 11.
_12VI1A
5-934112
L1, L3 = COGEMA946043 (969051)
L2 = COGEMA 946044 (946045)
Fig. 30 - In multiple supplies several
L4962s can be synchronized as shown
Roes
"
J ~ose
... I
Fig. 31 - Preregulator for distributed supplies
L4962
lQ-JoOV
"
...,"
I
l4962
I
I __
L
* L2 and C2 are necessary to reduce the switching frequency spikes
when linear regulators are remote from L4962
__________________________
~I~~~
______________________
~1~1/~12
189
L4962
MOUNTING INSTRUCTION
The Rth 11mb of the L4962 can be reduced by
soldering the GND pins to a suitable copper
area of the printed circuit board (Fig. 32).
The diagram of figure 33 shows the Rth j-amb as
a function of the side "Il" of two equal square
copper areas having the thickness of 35~ (1.4
Fig. 32 - Example of
used as heatsink
COPPER
mils). During soldering the pins temperature
must not exceed 260°C and the soldering time
must not be longer than 12 seconds.
The external heatsink or printed circuit copper
area must .be connected to electrical ground.
p.e. board copper area which is
AREA 3~}'
THICKNESS
",ot
Fig. 33 - Maximum dissi·
pable power and junction to
ambient thermal resistance
vs. side "Il"
O.,tI•
•
Ih
IWI
I 'Cfwl
\.
'It" j.amb
r--.
-
10
........
t-
I--
r-
f0-
Plot (lamb .?O·C)
'0
'0
10
,.
40
I (mrnl
P.C. BOARD
_12_/1_2_ _ _ _ _ _ _ _ _ _ _
190
~ !~~
____________
L6201
0.30 DMOS FULL BRIDGE DRIVER
ADVANCE DATA
to 48V and efficiently at high switching speeds.
All the logic inputs are TTL, CMOS and /lC
compatible. Each channel (half-bridge) of the
device is controlled by a separate logic input,
while a common enable controls both channels.
The L6201 is mounted in an SO.20 package.
Even at the full rated current and voltage no
external heatsink is required at normal operating
temperatures.
• SUPPLY VOLTAGE UP TO 48V
• 2A MAX PEAK CURRENT
• TOTAL RMS CURRENT UP TO 1.0A
• RDos(oN) 0.3D (TYPICAL VALUEAT25°C)
•
CROSS CONDUCTION PROTECTION
•
•
TTL COMPATIBLE DRIVE
OPERATING FREQUENCY UP TO 100KHz
•
•
•
THERMALSHUTDOWN
INTERNAL LOGIC SUPPLY
HIGH EFFICIENCY (TYPICAL 90%)
The L6201 is a full bridge driver for motor control applications realised in Multipower-BCD
technology which combines isolated DMOS
power transistors with CMOS and Bipolar circuits
on the same chip. By using mixed technology it
has been possible to optimise the logic circuitry
and the power stage to achieve the best possible
performance. The DMOS output transistors can
deliver 1.0A RMS at motor supply voltages up
BLOCK DIAGRAM
'~
SO-20
(12+4+4)
1
ORDERING NUMBER: L6201
OUT1
OUT2
20''---~
ENABLE
2
'-_--1-,
'--....b-+-+-"'------I
IN 2
18
5·101,91
June 1988
1/12
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
191
L6201
ABSOLUTE MAXIMUM RATINGS
Power supply
Input or Enable voltage
DC output current (note 1)
- non repetitive « 1ms)
Sensing voltage
Boostrap peak voltage
Total power dissipation (T pins 90°C)
(Tamb = 70°C no copper area on PCB)
Storage and junction temperature
52
V
1
A
A
5
-1 to 4
60
=
Tstg , Tj
v
-0.3 to 7
4
0.9
-40 to 150
V
V
W
W
°C
Notel: Pulse width limited only by junction temperature and the transient thermal impedance.
CONNECTION DIAGRAM
(Top view)
SENSE
ENABLE
N.C.
GND
GND
GND
GND
N.C.
OUT.2
Vref
BOOT 2
IN.2
GND
GND
GND
GND
IN.1
BOOT
OUT.1
+vs
BBL6201-CI
THERMAL DATA
Rth J-plns
Thermal resistance junction-pins
;::2/-=1=.2_ _ _ _ _ _ _ _ _ _ _ _
192
~ !~I~m?!£I~©~
max
15
-------------
L6201
PIN FUNCTIONS
PIN
NAME
FUNCTION
SENSE
A resistance Rsense connected to this pin provides feedback for motor current control
2
ENABLE
When a logic high is present on this pin the DMOS
POWER transistors are enabled to be selectively driven
by IN1 and IN2.
3
NO CONNECTION
4,5,6,7
GND
8
NO CONNECTION
9
OUT2
Output of the half bridge.
10
Vs
Supply voltage.
11
OUT1
Output of the half bridge.
12
BOOT1
A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at
high switching frequencies.
Common ground terminal.
131N1
Digital input from the motor controller.
14,15,16,17
GND
Common ground terminal.
18
IN2
Digital input from the motor controller.
19
BOOT2
A boostrap capacitor connected to this pin ensures efficient driving of the upper POWE R DMOS transistor at
high switching frequencies.
20
V ref
Internal voltage reference, a capacitor from this pin to
GND increases stability of the POWER DMOS logic drive
circuit.
------------- ~ litm&~JI-----------.::.3/~12
193
L6201
ELECTRICAL CHARACTERISTICS (Refer to the test circuits Tj = 25°C,
Vs
36V, unless
otherwise stated)
Parameter
Vs
Supply voltage
Vret
Reference voltage
Is
Quiescent supply current
Test Conditions
Min.
12
EN = H
EN = H
EN = L
VIN = L
VIN = H
Fig. 10
IL =0
Typ.
Max.
Unit
36
48
V
13.5
V
10
10
8
mA
mA
mA
fc
Commutation frequency
30
TJ
Thermal shutdown
150
°c
Td
Dead time protection
100
ns
100
KHz
TRANSISTORS
OFF
loss
Leakage cu rrent
Fig.11
100
IJA
0.3
n
ON
Ros
On resistance
VoS(ON)
Drain source voltage
V sens
Sensing voltage
Fig.9
los = 1.0A
0.36
V
4
-1
V
SOURCE DRAIN DIODE
VSd
Forward ON voltage
trr
Reverse recovery time
ttr
Forward recovery time
EN = L
Iso = 1.0A
IF=1.0A
dif
F=25A/lJs
0.9
V·
300
ns
200
ns
LOGIC LEVELS
VINL, YEN L
Input Low voltage
-0.3
VINL' VENH
Input High voltage
IINL, IENL
Input Low current
VIN, VEN = L
JINH. IENH"
Input High current
VIN, VEN = H
0.8
2
V
7
V
-10
IJA
30
IJA
LOGIC CONTROL TO POWER DRIVE TIMING
tl [Vi)
Source current turn-off delay
Fig. 12
300
ns
t2 (VI)
Source current fall time
Fig.12
200
ns
t3 (VI)
Source current turn-on delay
Fig. 12
400
ns
t4 (VII
Source current rise time
Fig. 12
200
ns
t5 (VI)
Sink current turn-off delay
Fig.13
300
ns
ts (VII
Sink current fall time
Fig. 13
200
ns
t7 (VI)
Sink current turn-on delay
Fig. 13
400
ns
ts (Vi)
Sink current rise time
Fig. 13
200
ns
1 =-2_ _ _ _ _ _ _ _ _ _ _ _
""4/c.::.
194
~ ~~m?f'1~JI-------------
L6201
Fig. 1 - Typical Is normal·
ized vs. TJ
Fig. 2 - Quiescent current
vs. frequency
-Ins
's
's
Fig. 3 - Typical Is normalized vs. Vs
's
(mA)
1.2
1.1
r-......
0.9
......
0.8
35
o. 9 f-'+--+--+-r-1~+--t--+--+-\
30
0.8
25
0.7 -
y
20
o. 7
o. 5
f-+-.+--+-+---+--.....1f-+-+--+---4
0.6
,/
'5
'0
0.6
y
0.5
-1--
0.4
+I
0.3
0.4
0.3
-25
.~.+-+-+-+-f-+-+--+--+-l
(l\Iorm.)
40
-4:'25
+50
+-75
$0
TJ ('C)
100
150
200 f(KHz)
Fig. 4 - Typical diode
behaviour in synchronous
rectification
5
10
15 20
Fig. 5 - Typical Ros
vs. Vs ~ Vref
25 30 35 40 45
\Is(V)
(ON)
G-631'
ROSON
(A)
(ll)
1.8
1.6
1.4
1.2
1.0
\
\
\
0.8
0.6
0.4
0.2
0.2 0.4 0.6
0.8
1
"
10
l2 1.4 1.6 Vso(V)
Fig. 6 - ROS (ON) normalized at 25°C vs. temperature
typical values
G-U13
Fig. 7 - Ros (ON)
transistor current
VS.
lis
,VREF(VI
DMOS
J.
, !.ROSon(Tj)
1.8
r-~. ROSon(ZS')
0.5 H-+-+-+-H-++-H-+-+-+-IH
1.6
L
1.4
1.2
/
o. 8
V
0.4H-+-+-+-H-++-H-+-+-+-IH
V
V
/'
o.zH-++-H+-HH-+HH--H
0.1
H-+++-H++-H-++HH
o. 6
-so
-25
0
+25 +50 +75 +100 TJ (-C)
6
---~--------- ~ l~nmre»JI------
HA)
_____
..:..5:..:...:/12
195
L6201
Fig. 8 - Typical power dissipation vs. IL
G
Pd
(W)
I I
I:-JIJIv Iv\
26
""iN
-'325/2
Vs::36V
L:lmH
T :2ms
2~
22
20 1-118
16
110
12
10
8
6
~
2
I~
5 :100t HzI<;-
20KHz
::-'.
''- IX
- - PHASE CHOPPING
-·_·-ENABLE CHOPPING
1'>1'
·V I2S
. ~. -V./
V j...:V
~
lMli;::::
2
3
5
6
Fig. 8a - Two phase chopping
000-_ _" " - ,
IN 1
o-<-t--+_"./
:::!6/~12==-- _ _ _ _ _ _ _ _ _ _ ~ !~;mo~lt
196
-
........'-l-~IN22
------------
L6201
Fig. Bc - Enable chopping
TEST CIRCUITS
Fig. 9 - Saturation voltage
a) Source outputs
b) Sink outputs
v..
5( A
La
I
V2
V1
r
s~
5(
13
11
r~
9
V2
18
L6201
A
10
13
18
L6201
11
9
I
V1I
GND
10492
5-10'93
For IN1 source output saturation: VI = "H"
5. = A
V = "H"
5 L =A
2
For IN1 sink output saturation:
VI = '''H''
5. = A
V = "L"
5L = A
2
For IN2 source'output saturation: VI = "H"
5. = B
V = "H"
5 L ,= B
2
For IN2 sink output saturatior1 :
VI = "H"
5. = B
V = "L"
5L = B
2
I
I
_____________
Gfi.1~~~m~
I
I
____________
7/"'-12
197
L6201
TEST CIRCUITS (continued)
Fig. 10 - Quiescent current
Fig. 11 - Leakage current
b) Sink outputs
a) Source outputs
Vs
Vs
10
10
11
L6201
9
A Sl
~-:q
11
L6201
9
B
GNO
GNO
5-10496
5-10'95
SWITCHING TIMES
Fig. 12 - Source current delay times vs. input
1...... l.0A
90,,"
10
IN
13/16
11/9
L6201
EN
GNO
5-10663
5-'066<
Fig. 13 - Sink current delay times vs. input
IN
13/18
L6201 1119
EN
GNO
5-10665
5-'0661
~8/.:.;12=--_ _ _ _ _ _ _ _ _ _ ~ !~tmoSolt
198
------------
L6201
CIRCUIT DESCRIPTION
The L6201 is a monolithic full bridge switching
motor driver realized in the new MultipowerBCD technology which allows the integration of
multiple, isolated DMOS power transistors plus
mixed CMOS/bipolar control circuits. In this way
it has been possible to make all the control
inputs TTL, CMOS and IlC compatible and
eliminate the necessity of external MOS drive
components.
the low-to-high transition a spike of the same
polarity is generated by C2, preceded by a spike
of the opposite polarity due to the charging of
t,he input capacity of the lower POWER DMOS
transistor. (Fig. 15)
Fig. 15 - Current typical spikes on the sensing pin
Voul
Vs ·36V
lp.o.SA
I.loons
LOGIC DRIVE
INPUTS
OUTPUT MOSFETS (0)
IN1
VEN= H
L
L
H
H
VEN= L
X
IN2
I
L
H
L
H
Sink 1, Sink 2
Sink 1, Source 2
Source 1, Sink 2
Source 1, Source 2
X
All transistors turned oFF
L = Low
H = H'gh
X = Don't care
(0) Numbers referred to INPUT 1 or INPUT2 controlled
ou tpu ts stages
I,·
S-10662
TRANSISTOR OPERATION
ON STATE
CROSS CONDUCTION
Although the device guarantees the absence of
cross-conduction, the presence of the intrinsic
diodes in the POWER DMOS structure causes
the gen8l'ation of current spikes on the sensing
ter'minals. This is due to charge-discharge phenomena in the capacitors C1 & C2 associated with the
drain source junctions (Fig. 14). When the output
switches from high to low, a ,current spike is
generated associated with the capacitor C1. On
Fig. 14 - Intrinsic structures in the POWER,
DMOS transistors Vs
CI
When one of the POWER DMOS transistor is
ON it can be considered as a resistor Ros (ON)
(= a.3il) throughout the recommended operating range. In this condition the dissipated
power is given by:
PON = ROSCONI • 105 2
The low Ros (ON) of the Multipower-BCD
process can provide high currents with low power
dissipation.
OFF STATE
When one of the POWE R DMOS transistor is
OFF the Vos voltage is equal to the supply voltage and only the leakage current loss flows. The
power dissipation during this period is given by:
POFF = Vs • loss
~-r-"--C Vou'
cz
5-9'1'5
The power dissipation is in the order of pW and
is negligible in comparison to that dissipated
in the ON STATE.
TRANSITIONS
Like all MOS power transistors the DMOS
POWER transistors have as intrinsic diode
between their source and drain that can operate
as a fast freewheeling diode in switched mode
------------- ~ !~~'lJO~ ____________
12
9'0--
199
L6201
applications. During recirculation with the
ENABLE input high, the voltage drop across the
transistor is Ros (ON) • 10 and when the voltage
reaches the diode voltage it is clamped to its
characteristic. When the ENABLE input is low,
the POWER MOS is OFF and the diode carries
all of the recirculation current. The power dissipated in the transitional times in the cycle
depends upon the voltage and current waveforms
in the application.
ptrans . = los (t) • Vos (t)
BOOSTRAP CAPACITORS
To ensure that the POWER DMOS transistors are
driven correctly gate source voltage of about 1OV·
must be guaranteed for all of the N-channel
DMOS transistors. This is no problem for the
lower POWER DMOS transistors as their sources
are refered to ground but a gate voltage greater
than the supply voltage is necessary to drive the
upper transistors. In the L6201 this achieved by an
internal charge pump circuit that guarantees correct DC drive in combination with the boostrap
circuit charges the external CB capacitors when
the source transistor is OFF and the sink transistor is ON giving lower commutation losses
in switched mode operation. For efficient
charging the value of the boostrap capacitor
should be greater than the input capacitance of
the power transistor which is around 1nF. It is
recommended that a capacitance of at least
10nF is used for the bootstrap. If a smaller
capacitor is used there is a risk that the POWER
transistors will not be fully turned on and they
will show a higher Ros (ON). On the other hand
if a elevated value is used it is possible that a
current spike may be produced in the sense
resistor.
REFERENCE
To stabilise the internal drive circuit it is recommended that a capacitor be placed between
this pin and ground. A value of 0.22#LF should
be sufficient for most applications.
This pin is also protected against a short circuit
to ground.
DEAD TIME
To protect the device against simultaneous
conduction in both arms of the bridge and the
________________________
_lO~/_12
200
resulting rail to rail short, the logic control
circuit provides a dead time greater tflan 40ns.
THERMAL PROTECTION
A thermal protection circuit has been included
that will disable the device if the junction temperature e reaches 150aC. When the temperature
has fallen to a safe level the device restarts under
the control of the input and enable signals.
APPLICATION INFORMATION
RECI RCU LATION
During recirculation with the ENABLE input
high, the voltage drop across the transistor is
Ros (ON). IL for voltages less than 0.7V and is
clamped at a voltage depending on the characteristics of the source~rain diode for greater
voltages. Although the device is protected against
cross conduction, turrent spikes can appear on
the current sense pin due to charge/discharge
phenomena in the intrinsic source drain capacitances. In the application this does not
cause any· problems because the voltage created
across the sense resistor is usually much less
than the peak value, although a small RC filter
can be added if necessary.
POWER DISSIPATION
In order to achieve the- high performance provided by the L6201 some attention must be paid
to ensure that it has an adequate PCB area to
dissipate the heat. The first stage of any thermal
design is to calculate the dissipated power in the
application, for this example the half step operation shown in figure 16 is considered.
RISE TIME T,
When an arm of the half bridge is turned on current begins to flow in the inductive load until
the maximum current IL is reached after a time
Tr . The dissipated energy EOFF/ON is in this
.case:
EOFF/ON = [ROS(ON)' IL2 • Tr ] ' 2/3
~~~~~~?~~
___________________________
L6201
ON TIME TON
QUIESCENT ENERGY
During this time the energy dissipated is due to
the ON resistance of the transistors EON and the
commutation ECOM . As two of the POWE R
DMOS transistors are ON EON is given by :
The last contribution to the energy dissipation is
due to the quiescent supply current and is
given by:
EQUIESCENT = IQUIESCENT • Vs • T
EON = IL2 • ROS(ON) ·2· TON
I~ the commutation the energy dissipated is:
ECOM = Vs • IL • TCOM • fswlTcH • TON
TOTAL ENERGY PER CYCLE
ETOT = EOFF/ON + EON + ECOM +
Where:
+ EON/OFF + EQUIESCENT
TCOM = Commutation Time and it is assumed
that;
TCOM = TTURN-ON = TTURN-oFF = lOOns
fswlTCH = Chopper frequency
The Total Power Dissipation POlS is simply:
FALL TIME Tf
For this example it is assumed that the energy
dissipated in this part of the cycle takes the same
form as that shown for the rise time:
EON/OFF = [Ros (ON) • I L2
•
T f 1·2/3
Rise time
ON time
Fall time
Dead time
Period
T = T, + TON + T f + Td
Fig. 16 - Load current in half step operation
I
Tr
I
Ton
I
Tf
--------------------------~!~I~~~~Jl
s- 9761
______________________~1~1~/1~2
201
L6201
Fig. 17 - Two phase Bipolar stepper motor control circuit with chopper current control and translator
8~
A
CW/CCW
STEP
a
HALF/FULL
L6281
iiEsEf
MOTOR
WIHOIHG
COHTROL (5V I
OUTPUT
EHABLE
LOGIC
C
L6281
MOTOR
Wll'fDIHG
SYHC
'5V
I
I
I
I
I
11
8BL62BI-53
SEHSE
RESISTORS
Fig. 18 - Rth junction to ambient vs. "on board" heat sink area
8BL620I-01
Rth (j -al
(·e/wl
75
\
70
\
~
65
\
60
55
" -...........
50
45
Pd • 1W
o
2
4
r--
~
6
B
On Board Heat Sink Area(aq.cm.1
~12~/~12~_____________________ ~1~~~~:
202
__________________________
L6202
0.30 DMOS FULL BRIDGE DRIVER
PRELIMINARY DATA
•
•
•
•
•
•
SUPPLY VOLTAGE UP TO 48V
5A MAX PEAK CURRENT
TOTAL RMS CURRENT UP TO 1.5A
R DS (ON) 0.3D. (TYPICAL VALUE AT 25°C)
CROSS CONDUCTION PROTECTION
TTL COMPATIBLE DRIVE
device is controlled by a separate logic input,
while a common enable controls both channels.
The L6202 is mounted in an 18-lead powerdip
package and the six center pins are used to
conduct heat to the PCB. Even at the full rated
current and voltage no external heatsink is required at normal operating temperatures.
OPERATING FREQUENCY UP TO 100KHz
• THERMAL
•• INTERNAL SHUTDOWN
LOGIC SUPPLY
•
HIGH EFFICIENCY (TYPICAL 90%)
The L6202 is a full bridge driver for motor control applications realized in Multipower-BCD
technology which combines isolated DMOS
power transistors with CMOS and Bipolar circuits
on the same chip. By using mixed technology it
has been possible to optimise the logic circuitry
and the power stage to achieve the best possible
performance. The DMOS output transistors can
deliver 1.5A RMS at motor supply voltages up
to 48V and efficiently at high switching speeds.
All the logic inputs are TTL, CMOS and IlC
compatible. Each channel (half-bridge) of the
Powerdip 12+3+3
ORDERING NUMBER: L6202
BLOCK DIAGRAM
OUT 1 OUT2
CBOOT 2
VREF 16/---~
ENABL~ H~--r--"""l
~,5,6,13,1~,15
5"939211
June 1988
1/16
203
L6202
ABSOLUTE MAXIMUM RATINGS
Power supply
Differential output voltage (Between pins 10 and 8)
Input or Enable voltage
Pulsed output current (note 1)
- non repetitive « 1ms)
Sp.!1sing voltage
Bu...:ttr:.ap peak voltage
Total-power dissipation (T pins = 90°C)
(Tamb = 70°C no copper area on PCB)
(Tamb = 70°C 4cm 2 copper area on PCB)
Storage and junction temperature
52
v
60
-0_3 to 7
5
V
V
10
-1 to 4
60
5
A
A
V
V
1.3
W
W
2
-40 to 150
W
°C
Note1: Pulse width limited only by junction temperature and the transient thermal impedance_
CONNECTION DIAGRAM
(Top view)
VREF
BOOT 2
IN 2
GNO
GNO
GNO
INI
. BOOT 1
OUT 1
~-9424
THERMAL DATA
Rthl-Plns
Rthj-amb
Thermal resistance junction-pins
Thermal resistance junction-ambient (Fig. 21)
.:::2/"-"1-'-6_ _ _ _ _ _ _ _ _ _ _ _
204
max
max
12
60
~ 1~1~=~19J1-------------
L6202
PIN FUNCTIONS
PIN
NAME
FUNCTION
SENSE
A resistance Rsense connected to this pin provides feedback for motor current control.
2
ENABLE
When a logic high is present on this pin the DMOS
POWER transistors are enabled to be selectively driven
by IN1 and IN2.
3
NO CONNECTION
4
GND
Common ground terminal.
5
GND
Common ground terminal.
6
GND
Common ground terminal.
7
NO CONNECTION
8
OUT2
Output of the half bridge.
9
V•.
Supply voltage.
10
OUTl
Output of the half bridge.
11
BOOTl
A boostrap capacitor connected to this pin ensures efficient driving of the. upper POWE R DMOS transistor at
high switching frequencies.
12
IN1
Digital input from the motor controller.
13
GND
Common ground terminal.
14
GND
Common ground terminal.
15
GND
Common ground terminal.
16
IN2
Digital input from the motor controller.
17
BOOT2
A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at
high switching frequencies.
18
Vref
Internal voltage reference, a capacitor from this pin to
GND increases stability of the POWER DMOS logic drive
circuit.
------------
~ !~m~=
___________
-"'3/<-=.::16
205
L6202
ELECTRICAL CHARACTERISTICS (Refer to the test circuits Tj
= 25°C.
Vs
= 42V.
unless
otherwise stated)
Parameter
Vs
Supply voltage
Vref
Reference voltage
IREF
Output current
Is
Ouiescent supply current
Test Conditions
Min.
12
Typ.
Max.
Unit
36
48
V
2
mA
13.5
EN = H
EN = H
EN = L
VIN = L
VIN= H
Fig. 10
V
10
10
8
IL =0
mA
mA
mA
fc
Commutation frequency
30
Tj
Thermal shutdown
150
·C
Td
Dead time protection
100
ns
100
KHz
TRANSISTORS
OFF
loss
Leakage current
Fig.11
Vs= 52V
1
mA
ON
Ros
On resistance
ROS(ON)
Drain source voltage
V sens
Sensing voltage
n
0.3
Fig.9
los=1.2A
0.36
V
4
-1
V
SOURCE DRAIN DIODE
VSd
Forward ON voltage
trr
Reverse recovery time
tfr
Forward recovery time
EN = L
Iso = 1.2A
IF= 1.2A
dif
F=25A/p.s
0.9
V
300
ns
200
ns
LOGIC LEVELS
VIN L. VENL
Input Low voltage
-0.3
0.8
V
VIN L. VENH
Input High voltage
2
7
V
liN L. lEN L
Input Low current
VIN. VEN = L
-10
p.A
IINH. IENH
Input High current
VIN. VEN = H
30
p.A
300
ns
LOGIC CONTROL TO POWER DRIVE TIMING
tl (Vi)
Source current turn-off delay
Fig. 12
t2 (Vi)
Source current fall time
Fig. 12
200
ns
t3 (Vi)
Source current turn-on delay
Fig. 12
400
ns
t4 (VI)
Source current rise time
Fig. 12
200
ns
ns
t5 (Vi)
Sink current turn-off delay
Fig. 13
300
t6 (VI)
Sink current fall time
Fig.13
200
ns
t7 (Vi)
Sink current turn-on delay
Fig. 13
400
ns
ts (VI)
Sink current rise time
Fig.13
200
ns
~4/~1~6_______________________ ~~~1;~~~:
206
______________________
~~
L6202
Fig. 2 - Quiescent current
vs. frequency
Fig. 1 - Typical Is normalized vs, T J
-
,
-
Fig. 3 - Typical Is normalized vs. Vs
,
Is
Is
(NoIm1 f-'-+-+--+-+--t_I-+-+--+---1
(mA)
40
35
30
25
20
15
10
1.2
1.1
......
1
.............
0.9
r--..
o. 8
o. 7
O. 6
o. 5
0.9 f--L+--+-+-+--+--tf--+-+-+--1
0.8 I-+-+--+-+-+--tl-+-+-+--I
0.7 f--t--+-+-+--+--tf--+-+-+--1
/'
0.6 f-+-+--+-+-+-f-+-+-+--I
0.5 f-+-+--+-+-+-f-+-+-+--I
0.4 f--+-+--+-+-+-I-+-+-+--I
""
V
O.3f--+-++--+--+-f--+--+-+--1
o. 4
0.3
-25
+25
.. 50
+75
50
TJ ("C)
100
200 f (KHz)
150
Fig. 4 - Typical diode
behaviour in synchronous
rectification
5 10 15 20 25 30 35 40 45 "o(V)
Fig. 5 - Typical Ros
vs. Vs ~ Vref
(ON)
G- 631 ~
ROSON
(1'-)
(A)
1.8
1.6
1.4
1.2
1.0
\
\
0.8
0.6
0.4
0.2
0.4
0.2
0.6 0.8
1
1.2
1.4
10
1.6 Vso(V)
Fig. 6 - Ros (ON) normalized at 25°C vs. temperature
typical values
G-UI3
Fig. 7 - Ros
(ON)
lis ,vREF(V)
vs. DMOS
transistor current
~lRoson(Tl)
1.8 -
Roson(ZS")
0.5 H-++-H-++-H-++t--I-+-l
1.6
0.4H++H-++H-++H--+-I
V
1.2
0.3 H++H-++H-++Hi""I--I
""V
o. 8
/
0.2H++H-++H-t-+Hf-t-l
/'
0.1 H++-H-++H-++Hf-t-l
o. 6
-50 -25
0
+25 +50 "75 +100
-------------
TJ (-C)
i:ii.1~m~~
6
I (A)
___________
.:;.,5/'-=16
207
L6202
Fig.8 - Typical power dissipation vs. IL
G - , 3251
) icJl,!.M
.
l; iv'I
26
21,
~ IN
Vs:36V
L=lmH
T =2ms
22
1S =100Ktiz I<:20 f- f20KHz
I'"
f'..
18
'l"-- j)(
16
·V IX
12
10
'12
./.
8
.>' /. ......
..... :..-::
6
I,
2
- - PHASE CHOPPING
-'-'-ENABLE CHOPPING
1.)- l7 17
11,
/.
~
I.i ~
2
3
5
6
Fig. 8a - Two phase chopping
, -........o-l--l'lIN'
IN 1 0-0-+_-'
Fig. 8b - One phase chopping
EN
0---+-""--'"
IN'
_
........o-l---
'"
~
~
-+-+--,--"
IN 2
GNO
~9510
(*1
June 1988
Suggested value for CeOOT1 and CeOOT2: 10nF
1/16
219
L6203
ABSOLUTE MAXIMUM RATINGS
Power supply
Differential output voltage (Between pins 1 and 3)
Input or Enable voltage
Pulsed output current (note 1)
- non repetitive « 1ms)
Sensing voltage
Boostrap peak voltage
Total power dissipation (Tease = 90°C)
(Tamb = 70°C free air)
Storage and junction temperature
52
60
-0.3 to 7
5
10
-1 to 4
60
20
2.3
-40 to 150
V
V
V
A
A
V
V
W
W
°C
Notel: Pulse width limited only by junction temperature and the transient thermal impedance.
CONNECTION DIAGRAM
(Top view)
l~
!
ENABLE
SENSE
VREF
-$- ~I
BOOT. 2
IN 2
8
7
GND
6
5
4
;t :I~~
INI
BOOT. 1
OUT 1
Vs
OUT 2
~ .....-_.J1!:==~:....-~===-!5_9514
conMcled 10 pin 6
L- Tab
THERMAL DATA
Thermal resistance junction-case
Thermal resistance junction-ambient
;:::2/;.:;1.:..6_ _ _ _ _ _ _ _ _ _ _
220
~ ~~tm~salf
max
max
3
35
-------------
L6203
PIN FUNCTIONS
PIN
NAME
FUNCTION
OUT2
Output of the half bridge.
2
Vs
Supply voltage.
3
oun
Output of the half bridge.
4
BOOT1
A boostrap capacitor connected to this pin ensures efficient driving of the upper POWE R DMOS transistor at
high switching frequencies.
5
IN1
Digital input from the motor controller.
6
GND
Common ground terminal.
7
IN2
Digital input from the motor controller.
8
BOOT2
A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at
high switching frequencies.
9
V ref
Internal voltage reference, a capacitor from this pin to
GND increases stability of the POWER DMOS logic
drive cricuit.
10
SENSE
A resistance Rsense connected to this pin provides feedback for motor current control.
11
ENABLE
When a logic high is present on this pin the DMOS
POWER transistors are enabled to be selectively driven
by IN1 and IN2.
___________________________
~~~~~~~~~
________________________~3/~1~6
221
L6203
ELECTRICAL CHARACTERISTICS (Refer to the test circuits TJ
25°C, Vs = 42V, unless
otherwise stated)
Parameter
Vs
Test Conditions
Supp Iy voltage
Vref
Reference voltage
IREF
Output current
Is
Quiescent supply current
Min.
Typ.
Max.
Unit
12
36
48
V
2
rnA
13.5
EN = H
EN = H
EN = L
V IN = L
V IN = H
Fig. 10
V
10
10
8
IL = 0
mA
mA
mA
fc
Commutation frequency
30
100
KHz
TJ
Thermal shutdown
150
°C
Td
Dead time protection
100
ns
TRANSISTORS
OFF
loss
Leakage current
Fig. 11
Vs = 52V
1
mA
ON
Ros
On resistance
VOS(ON)
Drain source voltage
Vsens
Sensi ng voltage
los = 3A
0.3
flo
0.9
V
-1
4
V
SOURCE DRAIN DIODE
VSd
Forward ON voltage
trr
Reverse recovery time
tfr
Forward recovery time
EN = L
Iso = 3A
I F =3A
dif
dt
= 25A/f.ls
1.35
V
300
ns
200
ns
LOG IC LEVE LS
-0.3
V IN L. VEN L
I nput Low voltage
V IN H. V EN H
I nput High voltage
liN L. lEN L
Input Low current
V IN • V EN = L
IINH. lEN H
Input High current
V IN • V EN = H
0.8
2
30
V
7
V
-10
f.lA
f.lA
LOGIC CONTROL TO POWER DRIVE TIMING
t1 (Vi)
Source current turn-off delay
Fig. 12
300
ns
t2 (Vi)
Source current fall time
Fig. 12
200
ns
t3 (Vi)
Source current turn-on delay
Fig. 12
400
ns
t4 (Vi)
Source current rise time
Fig. 12
200
ns
t5 (Vi)
Sink current turn-off delay
Fig. 13
300
ns
t6 (Vi)
Sink current fall time
Fig. 13
200
ns
t7 (Vi)
Sink current turn-on delay
Fig. 13
400
ns
t8 (Vi)
Sink current rise time
Fig. 13
200
ns
~4/~1~6________________________ ~~~~~~?~~:~~~
222
___________________________
L6203
Fig. 1 - Typical Is normal·
ized vs. Tj
G-6315
Fig. 3 - Typical Is normalized \Is. Vs
Fig. 2 - Quiescent current
vs. frequency
0-632&
IS
Is
Is
(Norml
(mA)
40.
1.2
1.1
1
...... t--.
0..9
......
35
0..9
30.
0..8
25
0..8
0..7
0..5
/'
10.
0..5
0..6
//
15
0..6
0..7
V
20.
0..4
C. 3
0..4
0..3
-25
+25
+50
.... 75
50.
TJ ("C)
100.
150
200 I(KHz)
Fig. 4 - Typical diode
behaviour in synchronous
rectification
5
10.
15 20.
Fig. 5 - Typical Ros
vs. Vs E!! Vref
25 30. 35 40 45
IIs(V)
(ON)
ROSON
(.tt)
(A)
1.8
.1.6
1.4
1\
\
1.2
\
1.0
0..8
0..6
0..4
0..2
0.2 0.4 0.6
0.8
1
\2
Fig. 6 - ROS (ON) normalized at 25°C vs. temperature
typical values
,
G'
VS.
lis
'VREF(V)
DMOS
ROS ONr-r-r-r-..-r-,--,--,,-.---.--r-r"T-,
ROSon(2S0)
C.4
H++H-++t-i-+++-H-l
H++H-++t-i-+++-H-l
0..3
H+H+H++-I-++-to'1--l
0..5
1.6
1.4
V
1.2
./
.8
Fig. 7 - RoS (ON)
transistor current
10.
(Al
oil Roson(Tj)
1.8 -
·6
1.4 1.6 VSO(V)
/
C. 6
-50 -25
/'
0.2H++-H-I-+-H-I-++-H-i
V
0..1
0 +25 +50 +75 +100
TJ (-<:)
H++-H-I-+-H-I-++-H-i
6
HA)
5/16
223
L6203
Fig. 8 - Typical power dissipation vs. IL
G
).,Jlt!" Iv\
\/V
26
iN'
632512
Vs:36V I
L=lmH
T =2ms
24
22
fs =lCOKHz ~
20 - 20KHz
18
16
14
:---...)<
. / )S
12
'/
'/
10
8
6
4
2
- - PHASE CHOPPING
-'-'-ENABLE CHOPPING
>, 1/,
. :" /..'/
...
/'/. ~
/..
~
~
2
3
4
5
6
7 IL (Al
Fig. 8a - Two phase chopping
;--"....o-l--<"lIN2
. Fig. 8b - One phase chopping
:::;6/'-=1.:::.,6_ _ _ _ _ _ _ _ _ _ _ _
224
~ le;m~59lf
-------------
L6203
Fig. Bc - Enable chopping
I·
!
I
EN
4l
"-~o-I"___
INI~~'Nl
TEST CIRCUITS
Fig. 9 - Saturation voltage
a) Source outputs
b)' Sink outputs
Vs
SI A
le
2
5
7
_V2
.L
11
SI
L6203
3
6
2
5
r~
7
V2
11
r 'Ill
Vl_
l.
A
5- 9768
L6203
6-10
_
For IN1 source output saturation: VI = "H"
5, = A
5L = A
·For IN2 source output saturation: VI
=
I V 2 = "H"
"H"
51 = B
5L = B
IV
__________________________
For IN1 sink output saturation:
For IN2 sink output saturation:
2
= "H"
~~~~~~~~
3
5- 9767
VI = "H"
5, = A
V = "L"
5L = A
2
I
V I = "H"
5. = B
5L = B
IV
2
= "L"
______________________~7/~16
225
L6203
TEST CIRCUITS (continued)
Fig. 10 - Quiescent current·
Fig. 11 - Leakage current
a) Source outputs
b) Sink outputs
v.
51
B
I1 l v
.L .J:. 1
.r
52
A 5L
11
B
L6203
L6203
:.i"v
.J:.2
B~
11
11
L6203
B
6-10
5-9'173/1
5-9714
5-9772/1
SWITCHING TIMES
Fig. 12 - Source current delay times vs. input chopper
Vs =42V
IN
517
L6203
EN
11
6
5-9710/1
5-9807
Fig. 13 - Sink current delay times vs. input chopper
Vs = 42V
IN
5/7
10'1,
L6203 311
EN
11
50'1,
6/10
5- 9769/1
5- 9808
!!!8/~16~_ _ _ _ _ _ _ _ _ _ _ ~ ~1~m~Jt
226
-------------
L6203
CIRCUIT DESCRIPTION
The L6203 is a monolithic full bridge switching
motor driver realized in the new MultipowerBCD technology which allows the integration of
multiple, isolated DMOS power transistors plus
mixed CMOS/bipolar control circuits. In this way
it has been possible to make all the control
inputs TTL, CMOS and JlC compatible and
eliminate the necessity of external MOS drive
components.
the low-to-high transition a spike of the same
polarity is generated by C2, preceded by a spike
of the opposite polarity due· to the charging of
the input capacity of the lower POWER DMOS
transi stor. (F ig. 15)
Fig. 15 - Current typical spikes on the sensing pin
Yout
VS=41Y
Ip .. Qf)A
T=100n5
LOGIC DRIVE
INPUTS
OUTPUT MOSFETS
I-I
IN1
IN2
VEN=H
L
L
H
H
L
H
L
H
Sink 1, Sink 2
Sink 1, Source 2
Source 1, Sink 2
Sou rce 1, Sou rc·e 2
VEN= L
X
X
All transistors turned oFF
H = High
X =Don't care
1*1 Members referred to INPUT 1 or INPUT2 controlled
outputs stages
L
= Low
CROSS CONDUCTION
Although the device guarantees the absence of
cross-conduction, the presence of the intrinsic
diodes in the POWER DMOS structure causes
the generation of current spikes on the sensing
terminals. This is due to charge-discharge phenomena in the capacitors C1 & C2 associated with the
drain source junctions (Fig. 14). When the output
switches from high to low, a current spike is
generated associated with the capacitor C1. On
Fig. 14 - Intrinsic structures in the POWER MOS
transistors
Vs
Cl
TRANSISTOR OPERATION
ON STATE
When one of the POWER DMOS transistor is
ON it can be considered as a resistor Ros (ON)
(= 0.30) throughout the recommended operating ·range. In this condition the dissipated
power is given by :
PON = ROS(ON) • los2
The low Ros (ONI of the Multipower-BCD
process can provide high currents with low power
dissipation.
OFF STATE
When one of the POWE R DMOS transistor is
OFF the Vos voltage is equal to the supply volt·
age and only the leakage current loss flows. The
power dissipation during this period is given by:
POFF = Vs • loss
+---.---~-c Vout
C2
5-941'5
The power dissipation is in the order of pW and
is negligible in comparison to that dissipated
in the ON STATE.
TRANSITIONS
Like all MOS power transistors the DMOS
POWER transistors have as intrinsic diode
between their source and drain that can operate
as a fast freewheeling diode in switched mode
------------lrii.I~tm&~SJI-----------..::.9/~16
227
L6203
applications. During recirculation with the
ENABLE input high, the voltage drop across the
transistor is Ros (ON) • 10 and when the voltage
reaches the diode voltage it is clamped to its
characteristic. When the ENABLE input is low,
the POWER MOS is OFF and the diode carries'
all of the recirculation current. The power dissipated in the transitional times in the cycle
depends upon the voltage and current waveforms
in the application.
ptrans . = los (t) • Vos (t)
BOOSTRAP CAPACITORS
To ensure that the POWER DMOS transistors are
driven correctly gate source voltage of about t OV
must be guaranteed for all of the N-channel
DMOS transistors. This is no problem for the
lower POWER DMOS trarisistors as their sources
are refered to ground but a gate v.oltage greater
than the supply voltage is necessary to drive the
upper transistors. In the L6203this achieved by an
internal charge pump circuit that guarantees correct DC drive in combination with the boostrap
circuit charges the external Ce ~apacitors when
the source transistor is OFF and the sink transistor is ON giving lower commutation losses
in switched mode operation. For efficient
charging the value of the boostrap capacitor
should be greater than the input capacitance of
the power transistor which is around tnF. It is
recommended that a capacitance of at least
tOnF is used for the bootstrap. If a smaller
capacitor is used there is a risk that the POWER
transistors 'will not be fully turned on and they
will show a !'tigher ROS(ON)' On the other hand
if a elevated value is used it is possible that a
current spike may be produced in the sense
resistor.
REFERENCE
To stabilise the internal. drive circuit it is recommended that a capacitor be placed between
this pin and ground. A value of 0.22#Fshould
be sufficient for most applications.
This pin is also protected against a short circuit
to ground.
DEAD TIME
To protect the device against· simultaneous
conduction in both arms of the bridge and the
resulting rail to rail short, the logic control
circuit provides a dead time greater than 40ns.
THERMAL PROTECTION,
A thermal protection circuit has been included
that will disable the device if the junction temperature e reaches 150°C. When the temperature
has fallen to a safe level the device restarts under
the control of the input and enable signals.
APPLICATION INFORMATION
RECIRCULATION
During recirculation with the ENABLE input
high, the voltage drop across the transistor is
Ros (ON)' IL for voltages less than 0.7V and is
clamped at a voltage depending on the characteristics of the source-drain diode for greater
Voltages. Although the device is protected against
cross conduction, current spikes can appear on
the current sense pin due to charge/discharge
phenomena in the intrinsic source drain, capacitances. tn the application this does not
cause any problems because the voltage created
across the sense resistor is usually much less
than the peak value, although a small RC filter
can be added if necessary.
POWER DISSIPATION
In order to achieve the high performance provided by the L6203 some attention must be paid
to ensure that it has an adequate PCB area to
dissipate the heat. The first stage of any thermal
design is to calculate the dissipated power in the
application, for this example the half step operation s~own in figure 16 is considered.
RISE TIME T,
When an arm of the half bridge is turned on current begins to flow in the inductive load until
the maximum current IL is reached after a time
T,. The dissipated energy EOFFioN is in this
case:
EOFF/ON = [Ros (ON) • IL2 • Tr] • 2/3
~lO~/~16~_____________________ ~I~~~~~~
228
__________________________
L6203
ON TIME TON
QUIESCENT ENERGY
During this time the energy dissipated is due to
the ON resistance of the transistors EON and the
commutation ECOM ' As two of the POWE R
DMOS transistors are ON EON is given by:
The last contribution to the energy dissipation is
due to the quiescent s~pply current and is
given by:
EQUIESCENT = IQUIESCENT • Vs • T
EON = IL2 • Ros (ON) • 2 • TON
In the commutation the energy dissipated is:
ECOM = Vs • IL • TCOM • fswlTcH • TON
TOTAL ENERGY PER CYCLE
ETOT = EOFF/ON + EON + ECOM +
+ EON/OFF + EQUIESCENT
Where:
TCOM = Commutation Time and it is assumed
that;
TCOM = TTURN-ON = TTURN-QFF = lOOns
fSWITCH = Chopper frequency
The Total Power Dissipation POlS is simply:
POlS = EToT/T
Rise time
ON time
Fall time
Dead time
Period
FALL TIME Tf
For this example it is assumed that the energy
dissipated in this part of the cycle takes the same
form as that shown for the rise time:
EON/OFF = [ROS(ON) 'I L2, Ttl· 213
Fig. 16
I
Tr
I
Toni Tf
DC MOTOR SPEED CONTROL
Since the L6203 integrates a full H-Bridge in a
single package it si idealy suited for controlling
small DC motors. When used for DC motor
co~trol the L6203 provides the power stage reqUired for both speed and direction control.
The L6203 can be combined with a current regulator like the L6506 to implement a transconductance amplifier for speed control, as shown in
__________________________
5 - 9775
figure 17. In this particular configuration only half
of the L6506 is used and the other half of the
device may be used to control a second motor.
In this configuration the L6506 sense the voltage
across the sense resistor, RSENSE, to monitor the
motor current_ The L6506 then compares the
sensed voltage against the current control input
and chops the input signals to the L6203 to
control the motor current.
~!~~@~~~~
______________________
~1~1/~16
229
L6203
Fig. 17 - Bidirectional DC motor control
5V
ENABLE Vs
11'11
OUlt
11'12
OUT2
OUT2
11'11
BOOT2
OUll
11'12
Vspeed
5V
VrefA
Vs
BOOTt
SenseA
Sense Vref
L6506
L6203
Rsense
11C!
nF
88L6283-51
BIPOLAR STEPPER MOTORS APPLICATIONS
Bipolar stepper motors can be driven with an
L297 or L6506, two L6203 bridge BCD drivers
and very few external components. Together
these three chips form a complete microprocessor-to-stepper motor interface.
As shown in Fig. 18 and Fig. 19, the controller
connect directly to the two bridge BCD drivers.
External component requirements are minimal:
an RC network to set the chopper frequency
and a resistive divider to establish the comparator
reference voltage (pin 15 for L297, pin 10 and
15 for L6506). These solutions have a very high
efficiency because of low power dissipation.
When the voltage drop across the Rsense is more
negative than -O.4V, diodes must be used between
each schottky sense output and ground.
Depending on the PCB configuration, a snubber
network would be connected between pins 1 and
3 of each IC (Generally 0.1 microF in series to 10
ohm).
HIGH CURRENT MICROSTEP DRIVE FOR
STEPPER MOTORS
The L6203 can by used in conjunction with the
L6217 to (figure 20) implement a high current
microstepping controller for stepper motors.
In this application the L6217 is used as a control
circuit and its outputs are used only to drive the
inputs of the L6203. The application" allows
easy interface to a microprocessor since the
L6217 may be connected directly to the microprocessor bus.
In the circuit shown in Figure 20, the L6217
senses the motor current by monitoring the
voltage across the sense resistors, RSENSE, and
compares this value to the output of a 6 bit
(7 bit if the L6217 A is used) D to A Converter.
The L6217 controls the current using a frequency modulated, constant off time, switching
controller. The off time of each coil may be
set using and external resistor and capacitor connected to PTA and PTB.
In this configuration the microprocessor simply
loads the appropriate value for the direction of
current floW through the coil "and the data for
the DAC into the L6217. The L6217 and L6203
then forms the complete interface between the
micro an"d the motor.
"
When the pins 3 and 4 of the L6217 (Test A and
B) are low, the bridges must be in tri-state condition.
For this reason two LM339 comparators must be
used. The outputs of the comparators act on the
enable inputs of the L6203 ICs.
A bilever operation can be used for decreasing
the minimum controllable load current. The mi-
~12~/~16~_____________________ ~!~I©~~~
230
--------------------------
L6203
nimum current that can be controlled is given by
the following expression
Vs
IL (avg.l =
Roenoe I- (2R DSon
+
RLOADI/DC
where R LOAD is the equivalent resistance of the
load DC is the duty cycle given by
If 12V is forced on pin (Reference voltage) and
the supply voltage V0 is reduced below 12V the
on resistance tends to increase above the normal
guaranteed 0.30hm.
Consequently the minimum current will also be
reduced, as given in the above expression. When a
minimum current operation is required, a high signal at point (A) can disable the pnp transistors
in fig. 20. So it's possible to operate at a V5 of
(7V - VeE).
Fig. 18 - Two phase Bipolar stepper motor control circuit with chopper current control
su
IN 1
RESET
ENABLE
-Ji---;:::=:::::JIDr-f--.-H
MOTOR
WINDING
L6283
IN 2 -J~--t:=:::::JIDr-f--.-H
L6283
I
MOTOR
WINOING
I
11
___________________________
~~~~~~~~~
SENSE
RESISTORS
______________________~1~3~/1~6
231
L6203
Fig. 19 - Two phase Bipolar stepper motor control circuit with chopper current control and translator
8~f-+-U._..,
A
CloIIte ...
STEP
HALF/FULL
L6203
ii5Ef
CONTROL
C SUI
MOTOR
IoIIHDl"G
-1---------.1
OUTPUT
ENABLE
L6203
MOTOR
UIHoIHG
SYNC
-5U
I
I
I
i i
BBL62B3-S3-1
SENSE
RESISTDRS
Fig. 20 - High current microstepping controller for stepper motors
'.luF
f1.2U
8.tuF
nu
D.
os
:r:
39
.20
3.
DYW!l8-Sa
"
04
3.
05
3.
'.luF
til
,.
L6217
:c
IAI
06
1 • 1UF
34
PH
ST.
"
.,.
lN4",S
31
4.
,vii
S
S
'7"
OUT
88L6283-S4
=..14:!.:/1:..:6'--_ _ _ _ _ _ _ _ _ _
232
~ ~~tm&~~~
-------------
L6203
THERMAL CHARACTERISTICS
Fig. 21 - Rth J..,mb of Multiwatt package vs. dissipated power
~
~
~
ill
~
~
I
'"'"
..-'"
~ :----,-..'----,
'---
0
i
>---,
>----..
free air
moun ed on
CB be rd
'"
~
w
"
~
~
'"'"
:'"
-
'"
'--
die
mount d
.5
ze
0.00
0.60
1.00
rea
1.50
.sink
q,mii
.BBa
=
dies! at-ing
HM 76 3 hea
OM
=
2.BBB sq.mi
2.00
2.60
8
3.00
3.50
4.H0
4.50
5.00
DISSIPATED POI.£R ( Watt )
Fig. 22 - Comparison of transient Rth for single pulses with and without heatsink
SINe LE
l?
mounted
~
/
/
PJLSE
Pd • 5
k::::
Pd • 2 W
~/
V
THM 7823 real
0
w
~ink
i*1
V
8.1
B.8B1
B.B1
B.1
1B
IBB
1BBB
TII'£ OR PULSE WIDTH ( S )
(*1 Rth '" g·C/W
__________________________
~~I;~&'~~
______________________
~1~5/~16
233
L6203
Fig. 23 - Peak transient Rth vs. pulse width and duty cycle
DC •
~I---
18
~I---
f----'
f.----r-
I--p
f.-'"
-I--
0.1
C0
CLE
1~
--~
~
ree
ir
~~:r~
--
100
!;
--
1800
TItE OR PULSE WIDTH ( ms )
!..:16:J.../l!..:6=---_ _ _ _ _ _ _ _ _ _
234
~ I~t~m~~lt
------------_
L6210
DUAL SCHOTTKY DIODE BRIDGE
• MONOLITHIC ARRAY
SCHOTTKY DIODES
•
OF
due to low forward voltage drop and fast reverse
recovery time, are required.
EIGHT
The L6210 is available in a 16 Pin Powerdip
Package (12+2+2) designed for the 0 to 70°C
ambient temperature range.
HIGH EFFICIENCY
• 4A PEAK CURRENT
•
LOW FORWARD VOLTAGE
•
FAST RECOVERY TIME
• TWO SEPARATED DIODE BRIDGES
The L6210 is a monolithic IC containing eight
Schottky diodes arranged as two separated
diode bridges.
Powerdip 12+2+2
This diodes connection makes this device versatile in many applications.
They are used particular in bipolar stepper motor
applications, where high efficient operation,
ORDERING NUMBER: L6210
ABSOLUTE MAXIMUM RATINGS
Repetitive forward current peak
Peak reverse voltage (per diode)
Operating ambient temperature
Storage temperature range
2
50
70
-55 to 150
BLOCK DIAGRAM
16,9.()
n 1.8
'-"'
~~
~~
~~
-~~
2
11.
v
15 .()
11.7
10 ,...
v
v
'-"'
~.
~~
~~
II. 3,6
-I
4~
11,14,...
"V
~9J20/1
4,5,12,13
June 1988
1/3
235
L6210
THERMAL DATA
RthJ-case
RthJ-amb
Thermal impedance junction-case
Thermal impedance junction-ambient without external heatsink
max
max
14
65
CONNECTION DIAGRAM
(Top view)
~
K
11
16
I2
I3
15
OUT 4
1"
A
GNO
I"
13
GNO
GNO
I5
12
GNO
A
I6
"
A
K
OUTI
A
OUT 2
7
K
8
10 OUT 3
9
K
~-9321
ELECTRICAL CHARACTERISTICS
IL
Forward voltage drop
Leakage current
25°C unless otherwise specified)
Test Condhions
Parameter
Vf
(TJ
Min.
If = 100mA
If
= 500mA
If
= lA
VR
= 40V
Tamb
= 25°C
TVp·
Max.
0.65
0.8
0.8
1
1
1.2
100
Unh
V
jJ,A
NOTE: At forward currents of greater than lA. a parasitic current of approximately 10 mA may be collected by adiacent
diodes .
.:::2/~3_ _ _ _ _ _ _ _ _ _ _ _ ~ !~~m?:!?14
236
-------------
L6210
Fig. 1 - Reverse current vs.
voltage
' ..... n
':~~~~I"il~
'" ..~
10
'i,125'c
I.
Fig. 2 - Forward voltage vs.
current
CHI064
(AI
/.~
L-.:i
TI,"12!I-C
.J
TO
lO.
lO
..
fJ .. 1S
C
!J
.,
0.2
50 "A1V)
O
Tie2S·',
0.'
0.6
0-8
MOUNTING INSTRUCTIONS
The RthJ-amb of the L6210 can be reduced by
soldering the GND pins to a suitable copper
area of the printed circuit board as shown in
figure 3 or to an external heats ink (Figure 4).
During soldering the pin temperature must not
exceed 260°C and the soldering time must not
be longer then 12s. The external heatsink or
printed circuit copper area must be connected
to electrical ground.
Fig. 3 - Example of P.C. board copper area
which is used as heatsink
Fig. 4 - Example of an
external heatsink
p.e.BOARD
-------------
~ ~~~;m~~~
____________
.::!..:3/3
237
L6233
PHASE LOCKED FREQUENCY CONTROLLER
ADVANCE DATA
•
PRECISION PHASE LOCKED FREQUENCY
CONTROL SYSTEM
•
XTAL OSCILLATOR
•
PROGRAMMABLE
QUENCY DIVIDERS
•
PHASE DETECTOR WITH ABSOLUTE FREQUENCY STEERING
•
DIGITAL LOCK INDICATOR
•
DOUBLE EDGE OPTION ON THE FREQUENCY FEEDBACK SENSE AMPLIFIER
REFERENCE
FRE'-
• TWO HIGH CURRENT OP-AMPS
•
5V REFERENCE OUTPUT
The L6233 is designed for use in phase locked
frequency control loops. While optimized for
precision speed control of DC motors, these
device is universal enough for most applications
that require phase locked control. A precise
reference frequency can be generated using the
device's high frequency oscillator and programmable frequency dividers. The oscillator operates
using a broad range of crystals, or, can function
as a buffer stage to an external frequency source.
The phase detector on these integrated circuit
compares the reference frequency with a frequency/phase feedback signal. In the case of a
motor, feedback is obtained at a hall output or
other speed detection device. This signal is
buffered by a sense amplifier that squares up the
signal as it goes into the digital phase detector.
The phase detector responds proportionally to
the phase error between the reference and the
sense amplifier output. This phase detector
includes absolute frequency steering to provide
maximum drive signals when any frequency
error exists. This feature allows optimum startup and lock times to be realized.
Two op-amps are included that can be configured to provide necessary loop filtering.
The outputs of these op-amps will source or sink
in excess of 16mA, so they can provide a low
impedance control signal to driving circuits.
Additional features include a double edge option
on the sense amplifier that can be used to double
the loop reference frequency for increased loop
bandwidths. A digital lock signal is provided
that indicates when there is zero frequency error
and a 5V reference output allows DC operating
levels to be accurately set.
20 PLCC
DIP-16 Plastic (0.25)
ORDERING NUMBERS: L6233 (DIP-16)
L6233P (20 PLCC)
CONNECTION DIAGRAMS
(Top views)
DIV 415 SELECT
16
GROUND
DIV 2141B SELECT
15
OSC. INPUT
"
OSC. OUTPUT
13
+VIN
2
LOCK INDICATOR
OUTPUT
PHASE DETECTOR
OUTPUT
DOUBLE EDGE
DISABLE
f,
12
SENSE AMP.
INPUT
11
sv
10
REF. OUTPUT
AUX,AMF
NON, INV. INPUT
,
20
19
18
PHASE DETECT.
11
OUTPUT
N.C.
DOUBLE EDGE
DISABLE
SENSE AMI?
INPUT
osc. OUTPUT
+VIN
N,C.
AUX, AMP. .
OUTPUT
1"
NON.
I~~\ ~~Ji
AUX,AMP.
INV. INPUT
OUTPUT
INV. INPUT
June 1988
OUTPUT
2
LOOP AMP
LOOP AMP.
DIP-16
AUX, AMP
J
LOCK
INDICATOR
OUTPUT
5.-9312
CHIP CARRIER
(20 PLCC)
1/8
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
239
L6233
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Power dissipation (Tamb '" 70°C)
Operating temperature range
Storage temperature
14
1
o to 70
-65 to 150
BLOCK DIAGRAMS
(DIP-16)
4
6
3
5
10
LOOP
AMPLIFIER
11
(PLCC PACKAGE)
19
18
2
3
5
8
LOOP
AMPLIFIER
~2/~8________________________ ~lil~~&'~~
240
13
14
--------------------------
L6233
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications hold for
O°C
Tamb
to +70°C; +VIN = 12V)
Parametar
IS
Test Conditions
Min.
Supply current
Typ.
Max.
Unit
mA
20
REFERENCE
V REF
Output voltage
4.75
5.0
5.25
V
LI VREF Load Regulation
lOUT = 0 to 7mA
5.0
20
mV
LI VREF Line regulation
+VIN = 8 to 12V
2.0
20
VOUT= OV
35
mA
IsC
Short circuit current
OSCILLATOR
Gv
DC voltage gain
VIS
I nput DC level
Oscillator input to oscillator output
Oscillator input pin open,
mV
16
dB
T J = 25°C
1.3
V
ZIN'
Input impedance
VIN = VIS ± 0.5V,
T J = 25°C
1.6
KO
Vo
Output DC level
Oscillator input pin open
T J = 25°C
1.4
V
f oMAX Maximum operating frequency
10
MHz
10
MHz
DIVIDERS
f oMAX
Maximum input frequency
Input = 1 Vpp at oscillator input
Input = 5V IDiv. by 4)
150
500
,.A
0.0
5.0
,.A
Div. 4/5 input current
Input = OV IDiv. by 5)
VTH
-5.0
Div. 4/5 threshold
1.6
2.2
V
Input = 5V IDiv. by 8)
0.5
150
500
,.A
Input = OV IDiv. by 2)
-500 -150
Div. 2/4/8 input current
Div. 2/4/8 open circuit voltage
Input current = O,.A IDiv. by 4)
1.5
2.5
Div. by 2 threshold
0.35
0.8
Div. by 4 threshold
1.5
Div. by 8 threshold
Volts below V REF
0.35
,.A
3.5
V
V
3.5
V
0.8
V
30
%
SENSE AMPLIFIER
VT
Threshold voltage
HT
Threshold hysteresis
Ib
Input bias current
Percent of V REF
Input = 1.5V
10
mV
-0.2
,.A
DOUBLE EDGE DISABLE INPUT
Input = 5V IDisabled)
VI
Input = OV IEnabled)
VT
150
500
,.A
-5.0
0.0
5.0
,.A
0.5
1.6
2.2
V
Input current
Threshold voltage
___________________________
~~~~~~~~
________________________~3/8
241
L6233
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions·
PHASE DETECTOR
VOH
High output level
VOL
Low output level
Negative Phase/Freq. Error
VOM
Mid output level
Zero Phase/Freq. Error, Percent of V REF
47
High level maximum source
current
VOUT= 4.3V
2.0
8.0
mA
Low level maximum sink curro
VOUT=0.7V
2.0
5.0
mA
6.0
KO
Mid level output impedance
(Note 2)
Positive Phase/Freq. Error, Volts Below VREF
lOUT = -200 to +200/LA
T j = 25°C
Saturation voltage
Freq. Error,
IOUT= 5mA
Leakage current
Zero Freq. Error
VOUT= 12V
0.2
0.5
0.2
0.5
V
50
53
%
V
LOCK INDICATOR OUTPUT
V sat
I 0.3
0.45
V
0.1
1.0
/LA
47
50
53
%
-0.8
-0.2
/LA
60
75
dB
+VIN=8t012V
70
100
dB
Source,
VOUT=OV
16
35
mA
Sink,
VOUT= 5V
16
30
mA
I
LOOP AMPLIFIER
NON INV. reference voltage
Percent of V REF
Input = 2.5V
Ib
Input bias current
Gv
Open loop gain
SVR
Supply voltage rejection
ISH
Short circuit current
AUXILIARY OP-AMP
VOS
Input offset voltage
Ib
I nput bias current
los
Input offset current
Gv
Open loop gain
8
VCM = 2.5V
'VCM= 2.5V
VCM= 2.5V
70
mV
200
mA
10
mA
120
dB
SVR
Supply voltage rejection
+VIN = 8 to 12V
70
100
dB
CMR
Common mode rejection
VCM = 0 to 10V
70
100
dB
ISH
Short circuit current
Source,
VOUT=OV
35
mA
Sink,
VOUT=5V
30
mA
* These impedance levels will vary with Tj at about 1700ppm/oC
THERMAL DATA
Rthj-amb
Thermal resistance junction-ambient
~4/_8________________________ ~!~1@~~~
242
max
100
__________________________
L6233
APPLICATION INFORMATION
Determining the Oscillator Frequency
The resulting reference frequency appearing at
the phase detector inputs is equal to the ascii·
lator frequency divided by the selected divide
ratio. If the double edge option is used, (Pin 5
low), the frequency of the sense amplifier input
signal is doubled by responding to both the rising
and falling edges of the input signal. Using this
option the loop reference frequency can be
doubled for a given motor RPM.
The frequency at the oscillator is determined by:
the desired RPM of the motor, the divide ratio
selected, the number of poles in the motor, and
the state of the double edge select pin.
fosc (Hz) = (Divide Ratio) • (Motor RPM) •
(1/60 SEC/MIN) • (No. of Rotor Polesl2) •
(x 2 if Pin 5 Low)
Fig. 1 - Recommended Oscillator Configuration Using AT Cut Quartz XT AL
MAY BE
REQUIRED
TO PREVENT
SPURIOUS
OSCILLATION
,----::: ------O.Ol,.,F .,." A
J Vr-~
Q
...I.. n n:-,-1Vpp
,
470Jl
JlJ:.'Vpp
-,
15
,
I
/,.6
,Kfl
.I.
1.3V
s- 9lU.
Fig. 2 - External Reference Frequency Input
S1J~IVpp
EXTERNAL REFE'RENCE--I
,1102 Vpp·/\./'
or
ZOOmV pp l02V
IlS
S-9315
Fig. 3 - Method for Deriving Rotation Feedback Signal From Analog Hall Effect Device
vREF OUT
n...r
*
o.',uF
--11---+----1
,
> XlOmV pp
:
LOW LEVEL
ANALOG HALL
OUTPUT
I +1.5V
I
I
_
$-9316
This signal may require filtering if chopped mode drive scheme is used.
- - - - - - - - - - - - - l i i i , ~~~~m~:~~AI
___________
--.:5~/8
243
L6233
APPLICATION INFORMATION (continued)
Phase detector operation
The phase detector on these devices is a digital
circuit that responds to. the rising edges of the
detector's two inputs. The phase detector output
has three states: a high, SV state, a low, OV state,
and a middle, 2.SV state. In the high and low
states the output impedance of the detector is
low, the middle state output impedance is high,
tipically 6.0Kn. When there is any static fre·
quency difference between the inputs the detec·
tor output is fixed at its high level if the +input
(the sense amplifier signal) is greater in frequency,
and fixed at its low level if the -input (the refer·
ence frequency signal) is greater in frequency.
When the frequencies of the two inputs to the
detector are equal the phase detector switches
between its middle state and either the high or
low states, depending on the relative phase of
the two signals. If the +input is leading in phase
then, during each period of the input frequency,
the detector output will be high for a time
equal to the time difference between the rising
edges of the inputs, and will be at its middle level
the remainder of the period. If the phase reo
lationship is reversed then the detector will go
low for a time proportional to the phase dif·
ference of the inputs. The resulting gain of the
phase detector, Kef> , is SV/47r, radians, or about
0.4 V/radian. The dynamic range of the detector
is ± 27r radians.
The operation of the phase detector is illustrated
in the figures below. The upper figure shows
typical voltage waveforms seen at the detector
output for leading and lagging phase conditions.
The lower figure is a state diagram of the phase
detector logic. In this figure, the circles represent
the 10 possible states of the logic and the con·
necting arrows the transition events/paths to
and from these states. Transition arrows that
have a clockwise rotation are the result of a
rising edge on the +input, and conversely, those
with counter-clockwise rotation are tied to the
rising edge on the-input signal.
The normal operational states of the logic are
6 and 7 for positive phase error, 1 and 2 for a
negative phase error. States 8 and 9 occur during
positive frequency error, 3 and 4 during negative
frequency error. States Sand 10 occur only as
the inputs cross over from a frequency error to
a normal phase error only condition. The level
of the phase detector output is determined
by the logic state as defined in the state diagram
figure. The lock indicator output is high, off,
when the detector is in states 1, 2, 6 or 7.
Fig. 4 - Typical Phase Detector Output Waveforms
T (ONE PERIOD
OF REFERENCE
SV
2.SV
_~=E~'-n-[C
---~
--Il.l4
SENSE AMPLIFIER INPUT
LEADING REFERENCE
FREQUENCY INPUT
BY 90 DEGREES
OV
SV
2!JV
o
J_U_U_U_IT
SENSE AMPLIFIER INPUT
TRAILING REFERENCE
FREQUENCY INPUT
BY 90 DEGREES
!o-9319
_________________________
~6/~8
244
~1~~~~
___________________________
L623.3
Fig. 5 - Phase Detector State Diagram
RISING EDGE
ON PHASt OOECTO)
-INPUT
(REfERENCE)
RISING EDGE
ON PH4SE DETECTOR
+ INPUT
CSENSE"MP)
C
+
+
I
OUTPUT·5V
OUTpuT. UV
I
OUTPUT. ow
DIGITAl lOCK INDICATOR HIGH DURING 5T4T£5 I. I. 6. ""'0 7.
s- 9421
Fig. 6 - Suggested Loop Filter Configuration
Rl
R3
VOUT (5)
FROM REF.
FILTER
Vln
V1N
RZ
Voul
+ S/wZ
R3
~
R1
1 + S/wP
TO POWER
DRIVE STAGE
wp
=
R2C1
LOOP AMP
,
VADJ.5VorOV
5-9317
wZ
Where:
•
The statistic phase error of the loop is easily adjusted
by adding resistor. R4, as shown. To lock at zero
phase error R4 is determined by :
R4 =
2.5V • R'3
(R1 + R2) C1
I AVOUTI = 1VOUT-2.5V I
and VOUT = DC Operating Voltage At Loop
Amplifier Output During Phase
Lock
(VOUT- 2.5)
(VOUT- 2.5)
> 0 R4 Goes to OV
< 0 R4 Goes to 5.0V
I AVOUT I
-----~-------
iiii 1~I~m~~lf ____________7:!.:/B
245
L6233
Fig. 7 - Reference Filter Configuration
FROM
Vin
Rl
PHASE DETECTOR o-C:J--+--c::J--.----I
OUTPUT
1
Voul TO LOOP
----<0 FILIE R
INPUT
>--..,..........
S2
S'
wN
wN'
+--+--
wN = ---;:~~:;:;
v'R1R2C1C2
_1 =_1
2Q
2
e
R1 + R2
C1
JRfR2
6=F
Note: with R1 = R2
C1
Fig. 8 - Reference Filter Design Aid - Gain
Response
Fig. 9 - Reference Filter Design Aid - Phase
Response
&-6062
(dB )
I
I II
I
VARIABLE is 11,2
-
(FOR Rl=Rzll,tcIC2)
20
-so
'/"---- 20
-10
//.:
V/fr - 5
10
Wr- - 2
I
o
~
~~
....... ~
-10
-50
'q
-zo
20
"'"."" r--.l\
- 20
- 40
-60
I:'lli:;
--10
l't"~
--5
-80
-100
~
-120
~\ ~
~ ~ ~t'-
-140
-30
-ISO
-40
6
•
~8/_8
_______________________
246
~~
-180
QI
0.1
~~~~~
2
r-I
VARIABLE IS 11£'
(FOR RI =R 2IJAtC I IC z l
••
___________________________
L6235
R-DAT BRUSH LESS DC MOTOR DRIVER
ADVANCE DATA
•
400mA OUTPUT CURRENT, CONTROLLED
IN LINEAR MODE
•
COMPATIBLE WITH ANI F-TO-V CONVERTER AND PLL SPEED CONTROL
SYSTEM
•
INHIBIT FUNCTION
•
SLEW RATE LIMITING FOR EMI REDUCTION
•
CONNECTS DIRECTLY TO HALL EFFECT
CELLS
•
THERMAL SHUTDOWN WITH HYSTERESIS
•
THREE-STATE OPERATION ALLOWS
NEGLIGIBLE POWER DISSIPATION DURING 1/3f CYCLE
•
INTERNAL PROTECTION DIODES
•
FEW EXTERNAL COMPONENTS
The L6235 is single-chip driver for three-phase
brush less DC motors capable of delivering 400mA
output current with supply voltages to l8V.
Designed to accept differential input from the
Hall effect sensors, the device drives the three
phases of a brush less DC motor and includes
all the commutation logic required for a three
phase drive.
To limit EMI emission the L6235 controls the
rise and fall times of the output stage. In addition the device is designed to limit power
dissipation: during recirculation the output stage
is switched to an off state, reducing dissipation
to a very low value and minimizing torque ripple.
A speed control input controls the base current
to the lower transistors to limit the motor current and hence control the speed. Any type of
speed control system, including F to V and
PLL system, may be used with the L6235 by
providing an analog signal at this input. The
motor current may be sensed by an external
resistor connected to a sensing pin on the device.
The power stage of the device is designed to
eliminate the possibility of simultaneous conduction of the upper and lower power transistors
of one output driver, when operating in the
right loop.
PLCC (15+5)
ORDERING NUMBER: L6235
INDEX
BLOCK DIAGRAM
+Ve-12V
'Va
Vc 13
L6235
6
9
10
12
4
S-979~
June 1988
1/7
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
247
L6235
CONNECTION DIAGRAM
(Top view)
C>
Z
o
INHIBIT
18
INDEX
11
+VS
HI (+)
16
OUT 2
H 1(-)
I~
CURRENT SENSING
H 2(+)
14
OUT 3
OUT I
'-_.L..Iu...u...L.I....L..L.L_-' ~-919l
ABSOLUTE MAXIMUM RATINGS
VS
10
Vi
Ptot
Top
Tj • T stg
Supply voltage
Peak output current each channel
non repetitive (100~s)
- repetitive (80% on - 20% off; ton = 1Oms)
- DC operation
Logic and analogic inputs
Total power dissipation at Tplns = 50°C
Operating temperature range
Storage and junction temperature
18
V
1.5
500
400
+Vs
5
o to 70
-40 to 150
A
mA
mA
W
°C
°C
THERMAL DATA
Rthj..,.mb
Rthj-Plns
Rtt
Thermal resistance junction-ambient
Thermal resistance junction-pins
Transient thermal resistance (t = 2sec.)
_________________________
~2/~7
248
~!~1;~~
max
max
max
100
20
30
___________________________
L6235
PIN FUNCTIONS
NAME
I/O
FUNCTION
4
INHIBIT
5
INDEX
6
H1 (+)
Positive input of differential amplifier on channel 1.
Interfaces with Hall Effect sensor, S1, from motor.
7
H1 (-)
Negative input of differential amplifier on channel 1.
Interfaces with Hall Effect sensor, Sl, from motor.
8
H2 (+)
Same as pin 3 for channel 2.
9
H2 (-)
Same as pin 4 for channel 2.
10
H3 (+)
Same as pin 3 for channel 3.
11
GND
Ground connection.
12
H3 (-)
Same as pin 4 for channel 3.
Output stage inhibit. When this pin is high all three output stages are in a high impedance state!
o
13
Speed control input. Connected to output of PLL in
PLL speed control applications.
14
Out 3
15
Sense
16
Out 2
o
Output motor drive for phase 3.
Current Sensing. I nput for load current sense voltage for
output stage.
o
Output motor drive for phase 2.
Motor supply voltage.
17
18
Signal pulse proportional to the motor speed. In PLL
speed control applications, this is the feedback to the
PLL. One pulse per electrical rotation. This is an open
collector output.
Out 1
o
-------------
Output motor drive for phase 1.
~ ~~~~m?:I9:
____________
3~/7
249
L6235
ELECTRICAL CHARACTERISTICS
Parameter
Vs
Supply voltage
Is
Quiescent supply current
(Tamb = 25°C; Vs
= 12V unless otherwise specified)
Test Conditions
Min.
Typ.
10
12
Without Load
30
Max.
Unit
V
60
mA
10
V
HALL AMPLIFIERS
VCM
Common mode voltage range
V io
Input offset voltage
Vi
= 6V
2
10
mV
lib
Input bias current
Vi
= 6V
2
10
!LA
'io
Input offset current
Vi
= 6V
0.1
0
!LA
SPEED CONTROL INPUT (Vel
Vi
Input voltage range
lib
Input bias current
Vic
Input clamping voltage
0
Vc
<
1
V sens
5
V
5
!LA
5.9
V
INHIBIT INPUT
V ,H
Input high voltage
2
Vs
V
V,L
Input low voltage
0
0.8
V
I'H
Input high current
10
!LA
I,L
Input low current
-50
!LA
-5
HALL LOGIC OUTPUT
VLO
Low output voltage
I = 5mA
0.8
V
'L
Leakage current
VCE = 12V
10
!LA
OUTPUT POWE R STAG E
Vsat
Total saturation voltage
VOS R
Output voltage slew-rate
V sens
Sense voltage range
0.15A
''00 == O.4A
'0 = 1.0A
0
2.2
2.5
2.7
V
100
V/ms
0.7
V
THERMAL SHUTDOWN
TJ
Junction temperature
TH
Hysteresis
24/~7_________________________ ~~~~~~~v~:~©~
250
150
°C
30
°C
---------------------------
L6235
DESCRIPTION
The output current is related to the speed control voltage by:
The L6235 is a three-phase brush less motor
driver IC containing all the power stages and
commutation logic required for a three-phase
drive. When the INHIBIT INPUT is high all
three OUTPUTS ARE PLACED in a high - IMPEDANCE STATE.
(V e
- 1)
1=--o
7 Rs
The value of the sensing resistor is given by:
Logic signals from the motor's Hall effect sensors
are decoded to generate the correct driving
sequence according to the truth table of Fig. 1.
R, = (Vx - 1)/(7 Imax)
where Vx is the full scale voltage of Ve.
When one of the push-pull output drivers is
activated the upper transistor is always in saturation while the lower transistor is controlled
in linear mode to set the desired speed in steady
state conditions.
In this way the Ve/l out characteristics can be
modified. Note that Vx max is clamped at 5.9V.
The most important feature of the L6235 is
slew rate control. With this device a typical
value of O.lV/tLs is achieved, reducing EMI to a
very low value.
In PLL speed control applications the device
provides a signal proportional to the motor
speed at pin 2 (it is the buffered H 1 input).
The output of the PLL is connected to the speed
control input of the device at pin 10, Vc.
Another key feature is three-state operation;
when the current is recirculating the corresponding phase driver is switched off and power dissipation is negligible. Current recirculates through
the free-wheeling diodes in the acceleration
phase and through the motor is steady-state
conditi.:lns. Torque ripple is also minimized.
In addition, a 1V offset is added to the speed
demand voltage to match the minimum output
of the PLL.
An external resistor, R" senses the output
stage current. The sensing voltage across this
resistor is amplified in the device by a factor of
7 to allow a reduction in the voltage drop the
resistor.
The L6235 can also operate with a brush less
motor connected in a star configuration, leaving
the centre floating.
The Hall inputs are ground compatible comparators and can work with direct active digital
Hall signals on three terminals (of the same
polarity) and a TTL level on the other three
terminals.
The amplified sensing voltage is then compared
with the speed demand signal from the PLL
and the resulting error signal sets the amplifier
output accordingly.
Fig. 1 - TRUTH TABLE
HALL EFFECT
DIFF. INPUT
UPPER DRIVER
STATUS
1 = POSITIVE
0= NEGATIVE
o =OFF
LOWER DRIVER
STATUS
1 =ON
1 =ON
O=OFF
H1
H2
H3
UD1
UD2
U03
L01
L02
L03
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
------------- ~ ~~~~mg:~~~lt ____________
::.!..:.5/7
251
L6235
Fig. 2 - Timing diagram
.0.1.2.1.4.1.0.1.2.1.4.
I.
~ :~F!lr:iifl:~
:
iii
iii
"'" ""'' ' --n I ' ! i; ii'L.J!
UPPER DRIYER
i
i
r i
: ! !
i
:
i
i
! ! ! : i
UD2-1
i
:
UDI
! !
l
i
LD2-H
~J
:
LD3
r
.
i
IOJ
i
. . r. ··r
(eM.tli
.
L
!
I
:
:
i
.
!l !l
······T··....
~
0
~-9484
OETERMINING HALL EFFECT SENSOR CODING
The L6335 assumes that the positioning of the
Hall Effect sensors in a three-phase brush less DC
bipolar motor are at 30 intervals. One can
imagine two "windows" on the rotor each of
which is 90 wide and 180 apart, see fig. 4. As
a window passes over a sensor, the sensor output
goes high. The timing diagram, fig. 2, shows the
waveforms produced. These waveforms must
appear at the Hall Effect Inputs of the L6235.
Note that the rotation in fig. 3 must be counterclockwise for forward rotation of the motor in
whatever manner that is defined for the motor.
Fig. 3 is a stylized concept for determining the
Hall Effect code pattern and does not reflect the
actual direction of rotation of the motor in a
physical sense. If a motor is chosen whose sensor
outputs do not match the L6235 desired input
pattern, a signal set conversion must be determined. It is helpful to visualize this by developing a diagram similar to that of fig. 4.
~6/~7
_____________
252
Fig. 3
_ _ _ _-2If'--'L----L_
51
For example, let us examine the output pattern
of a different type of motor (fig. 4). Assuming
90 windows at 180 intervals, then with respect to
fig. 3, a similar .diagram, fig. 5, results in sensors
60 apart with the windows rotating clockwise.
The situation results in a "forward" rotation of
the motor.
~1~~~~
_______________
L6235
Since S3 is the first sensor encountered by the
window in fig. 5, this should be used for the
L6235 Hall Effect Input, H1. After 30 of rotation CW, the H2 input of the L6235 must go
high. The inverse of Sl from the motor would
satisfy this. After an additional 30 of rotation,
the H3 input must go high. The S2 sensor is
encountered by the window. Thus, S2 is applied
to this input, H3. By continuing around the diagram, one can develop a pattern which matches
that for the L6235.
Fig. 5
53
52
--------~~~~--51
!>-9483
Fig. 4
Thus the conversion table for this particular
motor is:
L6235 Inputs
Motor Sensors
51
52
H1
S3
Sl
H2
H3
S2
Note, for the inverted signal from Sl an actual
inverter gate is not necessary with the L6235.
Since the L6235 has differential inputs, the negative input pin may be used. Therefore, with TTL
compatible Hall Effect sensors, the positive input
is connected to a reference point along with the
other negative inputs.
53
o
90
ANGLE OF ROTATION
Fig. 6 - Application circuit using the L6233 PLL-Controller
r-----'""""""---'""""""------'""""""~--{)+VS
J: 10pF
'Kn
51011
L6233P
121-~----I
13
14
15
.5V
'0
IKn
911Hl
o.41JJF
30Kfi
270Mfl
___________________________
5Kfi
~~~I~~?~~©~
________________________
~7/~7
253
L6236
BIDIRECTIONAL R-DAT BRUSHLESS DC MOTOR DRIVER
ADVANCE DATA
•
400mA OUTPUT CUR RENT, CONTROLLED
IN LINEAR MODE
•
COMPATIBLE WITH ANI F-TO-V CONVERTER AND PLL SPEED CONTROL
SYSTEM
•
SLEW RATE LIMITING FOR EMI REDUCTION
•
CONNECTS DIRECTLY TO HALL EFFECT
CELLS
•
THERMAL SHUTDOWN WITH HYSTERESIS
•
THREE-STATE OPERATION ALLOWS
NEGLIGIBLE POWER DISSIPATION DURING 1/3f CYCLE
•
INTERNAL PROTECTION DIODES
•
FEW EXTERNAL COMPONENTS
The L6236 is a single-chip driver for three-phase
brush less DC motors capable of delivering
400mA output current with supply voltages to
18V. Designed to accept differential input from
the Hall effect sensors, the device drives the three
phases of a brush less DC motor and includes
all the commutation logic required for a three
phase bidirectional drive. Both delta and wye
configurations may be used.
To limit EMI esmission the L6236 operates in a
linear mode and controls the rise and fall times
of the output stage. In addition the device is
designed to limit power dissipation: during
recirculation the output stage is switched to an
off state reducing dissipation to a very low value
and minimizing torque ripple.
A speed control input controls the base current
to the lower transistors to limit the motor current and hence control the speed. Any type of
speed control system, including F to V and PLL
systems, may be used with the L6236 by providing an analog signal at this input. The motor
current may be sensed by an external resistor
connected to a sensing pin on the device.
The power stage of the device is designed to eliminate the possibility of simultaneous conduction of the upper and lower power transistors of
one output driver, when operating in the right
loop.
PLCC (15+5)
ORDERING NUMBER: L6236
BLOCK DIAGRAM
INDEX
ONO
June 1988
1/7
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
255
! ..
L6236
CONNECTION DIAGRAM
(Top view)
G>
Z
o
FWD/REV
18
INDEX
17
+VS
H 1(+)
16
OUT 2
Ht(-)
15
SENSING
H 2(+)
14
OUT 3
9
10
11
12
OUT I
13
'--_........u....L.L...I...I-'-......,,_~ 5-9841
:I::I:
N w
Q
:I:
W
~~~~n=
ABSOLUTE MAXIMUM RATINGS
VI
Ptot
Top
Tj • T stg
Supply voltage
Peak output current each channel
- non repetitive (100Ils)
- repetitive (80% on - 20% off; ton = 10ms)
- DC operation
Logic and analogic inputs
Total power dissipation at Tplns = 50°C
Operating temperature range
Storage and junction temperature
18
V
1.5
A
mA
mA
500
400
+Vs
5
Oto 70
-40 to 150
THERMAL DATA
Rth j-amb
Rth j-plns
tt
R
Thermal resistance junction-ambient
Thermal resistance junction-pins
Transient thermal resistance (t = 2sec.)
-'2/'-7_ _ _ _ _ _ _ _ _ _ _ _
256
~ I~~;mg'l£~
max
max
max
100
20
30
-------------
L6236
PIN FUNCTIONS
NAME
I/O
FUNCTION
4
FWD/REV
5
INDEX
6
H1 (+)
Positive input of differential amplifier on channel 1.
Interfaces with Hall Effect sensor, S1, from motor.
7
H1 (-)
Negative input of differential amplifier on channel 1.
Interfaces with Hall Effect sensor, S1, from motor.
8
H2 (+)
Same as pin 3 for channel 2.
9
H2 (-)
Same as pin 4 for channel 2.
10
H3 (+)
Same as pin 3 for channel 3.
11
GND
Ground connection.
12
H3 (-)
Same as pin 4 for channel 3.
Direction Control. When this pin is low, the motor will
run in the forward direction. A high will drive the motor
in the reverse direction. Direction is defined by the
positive of the sensors in the motor.
o
Speed control input. Connected to output of PLL in
PLL speed control applications.
13
14
OUT3
15
SENSE
16
OUT2
o
Output motor drive for phase 3.
Current Sensing. Input for load current sense voltage for
output stage.
o
Output motor drive for phase 2.
Motor supply voltage.
17
18
Signal pulse proportional to the motor speed. In PLL
speed control applications, this is the feedback to the
PLL. One pulse per electrical rotation. This is an open
collector output.
OUT1
o
Output motor drive for phase 1.
------------- ~ !~tm~~AI-----------.,-3c.:...;.,/7
257
L6236
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; Vs = 12V unless otherwise specified)
Parameter
Vs
Supply voltage
Is
Quiescent supply current
Test Conditions
Min.
Typ.
10
12
30
Max.
Unit
V
60
mA
10
V
HALL AMPLIFIERS
VCM
Common mode voltage range
Vlo
Input offset voltage
VI = 6V
2
10
mV
lib
Input bias current
Vi = 6V
2
10
/lA
lio
Input offset current
Vi = 6V
0.1
0
/lA
SPEED CONTROL INPUT (Vel
VI
Input voltage range
lib
Input bias current
VIC
Input clamping voltage
0
Vc
<
1
Vsens
5
V
5
/lA
V
5.9
FWD/REVERSE INPUT
VIH
Input high voltage
2
Vs
V
VII..
Input low voltage
0
0.8
V
IIH
Input high current
10
/lA
III..
I npu t low cu rrent
-50
/lA
-5
HALL LOGIC OUTPUT
V 1..0
Low output voltage
I = 5mA
0.8
V
II..
Lea kage cu rrent
VCE = 12V
10
/lA
OUTPUT POWER STAGE
V sat
Total saturation voltage
VOSR
Output voltage slew-rate
V sens
Sense voltage range
10 = 0.15A
10 = 0.4A
10 = 1.0A
0
2.2
2.5
2.7
V
100
V/ms
0.7
V
THERMAL SHUTDOWN
Tj
Junction temperature
TH
Hysteresis
~4/~7________________________ ~~~i~~~~~©~
258
°c
150
30
°c
__________________________
L6236
DESCRIPTION
The l6236 is a three-phase brush less motor
driver IC containing all the power stages and
commutation logic required for a three-phase
bidirectional drive.
The output current is related to the speed control voltage by:
10 = (Ve -1)/7 Rs
logic signals from the motor's Hall effect sensors
are decoded to generate the correct driving
sequence according to the truth-table of Fig. 1.
The value of the sensing resistor is given by:
Rs = (Vx -1)/(7 Imax)
The direction of rotation is controlled by the
forward/reverse input (pin 1). When this pin is
at a low level the motor rotates in the forward
direction.
where Vx is the full scale voltage of Ve.
In this way the Ve/lout characteristics can be
modified. Note that Vx max is clamped at 5.9V.
When one of the push-pull output drivers is
activated the upper transistor is always in saturation while the lower transistor is controlled
in linear mode to set the desired speed in steady
state conditions.
The most important feature of the l6236 is
slew rate control. With this device a typical value
of O.lV/lls is achieved, reducing EMI to a very
low value.
In Pll speed control applications the device
provides a signal proportional to the motor
speed at pin 2 (it is the buffered H1 input). The
output of the Pll is connected to the speed
control input on the device at pin 10, Ve.
In a delta configuration a key feature is threestate operation; when the current is recirculating
the corresponding phase driver is switched off
and power dissipation is negligible. Current recirculates through the integrated free-wheeling
diodes in the acceleration phase and through the
motor in steady-state conditions. Torque ripple
is also minimized.
In addition, a lV offset is added to the speed
demand voltage to match the minimum output
on the Pll.
The l6236 can also operate with a brush less
motor connected in a star configuration, leaving
the center floating.
An external resistor, Rs , sense the output stage
current. The sensing voltage across th is resistor is
amplified in the device by a factor of 7 to allow
a reduction in the voltage drop in the resistor.
The Hall inputs are ground compatible comparators and can work with direct active digital
Hall signals on three terminals (of the same
polarity) and a TTL level on the other three
terminals.
The amplified sensing voltage is then compared
with the speed demand signal from the Pll and
the resulting error signal sets the amplifier output
accordingly.
Fig. 1 - TRUTH TABLE FOR FORWARD ROTATION
HALL EFFECT
DIFF. INPUT
UPPER DRIVER
STATUS
LOWER DRIVER
STATUS
1 = POSITIVE
NEGATIVE
1 =ON
O=OFF
1 =ON
O=OFF
o=
H1
H2
H3
UD1
UD2
UD3
LD1
LD2
LD3
1
1
1
0
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
___________________________
0
0
0
0
~~~~~~?~~~
0
0
0
0
________________________
~5/_7
259
L6236
Fig. 2 - Timing diagram
:~
,0,1,2,.
.
.
~
..
: $1·• •· i~-: :-: .i.r-·: -: J:
II
°
==t-t--l
UPPEII DIIIYEII
UDI
LOWEll ORIYEII
LDI
!!! I
--r--j
:
t-l
~:~.~~~
~-'-~_"-.....J
UDI~
j.......!. . . .p °
I.~.II.
::::::Ft44 :
>--i---ij ! ! !
I .I
:
UD2-l i
LD2
I
r--....:.._...;--; ......
.
~~i
. LJ
:
i:::
n
!
ICH··~!·I ...... ·t·
.
I
..·.. ·T ......i 0
~-9484
DETERMINING HALL EFFECT SENSOR CODING
The L6236 assumes that the positioning of the
Hall Effect sensors in a three-phase brush less DC
bipolar motor are at 30 intervals. One can
imagine two "windows" on the rotor each of
which is 90 wide and 180 apart, see fig. 4. As
a window passes over a sensor, the sensor output
goes high. The timing diagram, fig. 2, shows the
waveforms produced. These waveforms must
appear at the Hall Effect Inputs of the L6236.
Note that the rotation in fig. 3 must be counterclockwise for forward rotation of the motor in
whatever manner that is defined for the motor.
Fig. 3 is a stylized concept for determining the
Hall Effect code pattern and does not reflect the
actual direction of rotation of the motor in a
physical sense. If a motor is chose whose sensor
outputs do not match the L6236 desired input
pattern, a signal set conversion must be determined. It is helpful to visualize this by developing a diagram similar to that of fig. 4.
_6=--/7_ _ _ _--'--_ _ _ _ _ _ _
260
Fig_ 3
S1
For example, let us examine the output pattern
of a different type of motor (fig. 4). Assuming
90 windows at 180 intervals, then with respect to
fig. 3, a similar diagram, fig. 5, results in sensors
60 apart with the windows rotating clockwise.
The situation results in a "forward" rotation of
the motor.
jjfi. !~~;m?v~Jl------------
L6236
Since S3 is the first sensor encountered by the
window in fig. 5, this should be used for the
L6236 Hall Effect Input H1. After 30 of rota·
tion CW, the H2 input of the L6236 must go
high. The inverse of Sl from the motor would
satisfly this. After an additional 30 of rotation,
the H3 input must go high. The S2 sensor is
encountered by the window. Thus, S2 is applied
to this input, H3. By countinuing around the diagram, one can develop a pattern which matches
that for the L6236.
Fig. 5
53
,I
52
--------~~-L--J--51
Fig. 4
Thus the conversione table for this particular
motor is:
51
Motor Sensors
52
S3
Sl
S2
53
o
90
1 0
L6236 inputs
H1
H2
H3
Note, for the inverted signal from Sl actual
inverter gate is not necessary with the L6236.
5ince the L6236 has differential inputs, the negative input pin may be used. Therefore, with TTL
compatible Hall Effect sensors, the positive input
is connected to a reference point along with the
other negative inputs.
270
ANGLE OF ROTATION
Fig. 6 - Application circuit using the L6233 PLL-Controller
lOCI( INDICATION
~--------4~-----'-------------
OUTPUT
IKn
20
18
Rfi
__--4~-{) +Vs
IOpF
510.0
:r
lOnF
L6233P
.sv
IMO
261
~
...,L
S'S-THOMSON
I
I,'
~D©OO@rn[],,[~©'[j'OO@~D©~
LM1837
DUAL LOW NOISE TAPE PREAMPLIFIER WITH AUTOREVERSE
•
PROGRAMMABLE TURN-ON DELAY
•
TRANSIENT-FREE MUTING AND POWERUP- NO POPS
•
LOW-NOISE - 0.6 p.V CCIR/ARM
•
HIGH POWER SUPPLY REJECTION - 95dB
•
LOW DISTORTION SLEW RATE - 6V/p.s
•
SHORT CI RCUIT PROTECTION
•
INTERNAL DIODES FOR DIODE SWITCHING APPLICATIONS
and reverse (left, right) inputs wh ich are selectable
through a high impedance logic pin. It is an ideal
choice for a tape playback amplifier when a combination of low noise, autoreversing, good power
supply rejection, and no power-up transients
are desired. The application also provides transient-free muting with a single pole grounding
switch.
0.03% AND HIGH
DIP-18 Plastic
The LM 1837 is a dual autoreversing high gain tape
preamplifier for applications requiring optimum
noise performance; It has forward (left, right)
ORDERING NUMBER: LM1837
Fig. 1 - Autotoreversing tape plyback application
OS
R2
11MA
IOKO
03
VS=12V
RIGHT
OUTPUT
RIGHT FORWARD
06
10KO
INPUT
RIGHT REVERSE
INPUT
LEFT FORWARD
10K.o.
INPUT
Fl8
LEFT
18
OUTPUT
LEFT REVERSE
INPUT
16
lOGIC
FORWARD::: O.5V
REVERSE ~ 2.2V
*
10KO
012
013
10KO
*5 ..
11
2.2nF
10~F
C,
IlV
210M
.7
56KO*
OPTIONAL MUTE
011
1.2MD.
014
S_'U511
June 1988
1/8
263
LM1837
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Voltage on pins 1 and 18
Package dissipation
Storage temperature
Operating temperature
Minimum voltage on any pin
18
V
18
V
1390 mW
-65 to 150°C
o to 70°C
-0.1
V
CONNECTION DIAGRAM
(top view)
RIGHT DIODE
OUTPUT
LEFT DIODE
OUTPUT
18
LEFT OUTPUT
RIGHT OUTPUT
R(+)lN
L(+)lN
R(-)IN
L (-)IN
LEFT X25 OUT
RIGHT X25 OUT
BIAS
13
LOGIC
RIGIiT FORW.RD
INPUT
12
LEFT FORWARD
INPUT
RIGHT REVERSE
INPUT
11
LEFT REVERSE
INPUT
10
GND
+Vs
9
5 - 64" 6
SCHEMATIC DIAGRAM
=2/~8~
264
_______________________
~~~1;~~~~
___________________________
LM1837
THERMAL DATA
Rth j-amb
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (Tamb
= 25°C, Vs = 12V, see test circuits)
Test conditions
Parameter
Vs
Su pply voltage
R5 removed from circuit for
low voltage operation
Is
Su pply cu rrent
Vs = 12V
d
Total harmonic distortion
f = 1 KHz
VI = 0.3mV
pins 2 and 17, see test circuit
THD + noise (note 1)
f = 1 KHz
Vo= lV
pins 2 and 17, see test.circuit
SVR
Power supply rejection
input ref. f = 1 KHz, 1 Vrms
Cs
Channel separation (note 2)
f = 1KHz, output = 1 Vrms
Output to output
eN
Signal-to-noise (note 3)
Noise
Typ.
4
9
Max.
Unit
18
V
15
mA
0.03
0.1
%
0.25
%
80
95
dB
40
40
60
60
dB
dB
Unweighted 32Hz - 12.74 KHz
(note 1)
CCIR/ARM (note 4)
A weighted
CCIR, peak (note 5)
58
62
64
52
dB
dB
dB
dB
Output voltage CCIR/ARM (note 4)
120
200
p,V
0.5
2
p,A
Kn
dB
dB
V
mV
mA
p,A
Left to right
Forward to reverse
SIN
Min.
INPUT AMPLIFIERS
Ib
Vo
Vo
10+
10-
Input bias current
Input impedance
ACgain
AC gain imbalance
DC output voltage
Output voltage mismatch
Output source current
Output sink current
f= KHz
pins 5 and 14
pins 5 and 14
Pins 5 and 14
150
27
2.1
- 200
2
300
28
29
± 0.15
± 0.5
2.5
30
10
600
2.9
200
LOGIC LEVEL
Forward
0.5
Reverse
DC voltage change
at pins 5 and 14
V
2.2
Logic pin current
Change logic state
-100
V
2
6
p,A
20
100
mV
------------- ~ ~~i~m~l~~~ ____________
32.=./8
265
LM1837
ELECTRICAL CHARACTERISTICS (continued)
Test conditions
Parameter
Min.
Typ.
Max.
Unit
I
OUTPUTS AMPLIFIERS
Closed loop gain
stable operation
Open loop voltage gain
DC
5
V!V
100
dB
Gain bandwidth product
5
MHz
Slew rate
6
V/p,s
Vos
Input offset voltage
2
5
mV
loS
Input offset current
20
100
nA
II
Input bias current
250
500
nA
10+
Output source current
Pin 2 or 17
2
10
mA
10-
Output sink current
Pin 2 or 17
400
900
p,A
Vo
Output voltage swing
Pin 2 or 17
11
Vp-p
Output diode leakage
Voltage on pins 1 and 18 = 18V
0
Gv
10
p,A
Note:
1 - Measured with an average .responding voltmeter using the filter circuit in figure 4. This simple filter is approximately equivalent a "brick wall" filter with a passband of 20Hz to 20KHz (see Application Hints), For 1KHz THO the
400Hz high pass filter on the distortion analyzer is used.
2-
Channel separation can be measured by applyng the input signal through transformers to simulate a floating source
(see Application Hints), Care must be taken to shield the coils from extraneous signal. Actual production test
techniques simulate this floating source with a more complex op amp circuit.
3-
The numbers are referred to an output level of 160mV at pins 2 and 17 using the circuit figure 2. This corresponds
4-
Measured with an average responding. voltmeter using the Dolby lab's standard CCIR filter having a unity gain
reference 2KHz.
5-
Measured using the Rhode-Schwartz psophometer, mode UPGR.
~4/~8__________________~____ ~1~~~~~1~~~
266
--------------------------
LM1837
Fig. 2 - Test circuit
R2
Cl
2.2 nF
2-'.
LM 1837
10KA
5- 64411'
Fig. 3 distortion
Input amplifier
vs. input level
• ~~-r~~--r-~~~~~
e%)'~~'~~~A~~*-L~lFd'E~R=ONb~'+~~+-+-" I- i~i~~~ ,-+--+--+---#--~+--
Fig. 4 - Input amplifier
gain and phase vs frequency
.. .....
.. ..
.
I---
G-1114
1'-..
30
r\
'~
"" fTR=
, \ ••
6.
,
,.
Fig. 5 - Output amplifier
open loop gain and phase
vs. frequency
..
·1.
,l-\ 12.
_.
.'"
•
"
60
6-5165
.I
"'
r-....
••
PHASE
,
12.
f"'-..GAIN
I'..
00
r.....
\
\
'0
00
.0
80
Vj(mV)
'90
10
tOO
Itl.
'10K
'lOOK
1M
tOM "Hz)
-------------- ~ ~~~~m?ml9~
''''
'"'"
- - I\--.2G
180
"'-,
,so
~- I-----
fe')
·80
300
360
10
100
,~
10K
lOOK
1M
f {Hd
5/8
267
LM1837
Fig. 6 - Noise voltage vs.
frequency
Fig. 7 - Noise current vs.
frequency.
Fig. 8 - Total harmonic
distortion vs. frequency
a-
)
d
f--
'4out_1¥"..
f+ 1 "",
I
lSS
I
'"10)
-
i
I
I'!---!
~
I
WITHOUT FllTJR
0.'
I
USING 41h ORDER
'I
,
0.1
10
20Hz -20KHz FILTER
,
0.1
I
I
I ..
i
I
! , ,.
100
;1
III , .
,.
0.0
20
R"2~.05
250
150
.0
I
/
k' ., I~/
0.2
0.4
Fig. 12 - Is
II
'lis
i'-
0.8
1
Ict"
.12
R13
10KO
*.'"
1.2hUl
Fig. 19 - P.C. board and components layout of the circuit of Fig. 18 (1
8/8
270
OPTIONAL MUTE
1 scale)
LS404
HIGH PERFORMANCE QUAD OPERATIONAL AMPLIFIERS
• SINGLE OR SPLIT SUPPLY OPERATION
•
VERY LOW POWER CONSUMPTION
• SHORT CIRCUIT PROTECTION
•
LOW DISTORTION, LOW NOISE
•
HIGH GAIN-BANDWIDTH PRODUCT
•
HIGH CHANNEL SEPARATION
The LS404 is a high performance quad operational amplifier with frequency and phase compensation built into the chip. The internal phase
compensation allows stable operation as voltage
follower in spite of its high gain-bandwidth
product. The circuit presents very stable electrical characteristics over the entire supply voltage
range, and it is partucu larly intended for professional and telecom applications (active filters, etc.).
The patented input stage circuit allows small
input signal swings below the negative supply
voltage and prevents phase inversion when the
input is over driven.
DIP-14 Plastic
(0.25)
SO-14J
ABSOLUTE MAXIMUM RATINGS
VS
Vi
Supply voltage
Input voltage
Vi
Top
Differential input voltage
Operating temperature LS404
(positive)
(negative)
LS404C
Ptot
Tst9
June 1988
Power dissipation
Storage temperature
(T amb = 70°C)
± 18
+Vs
-Vs - 0.5
± (Vs - 1)
-25 to + 85
o to + 70
400
-55 to + 150
V
V
°C
°C
mW
°C
1/10
271
LS404
CONNECTION DIAGRAM AND ORDERING NUMBERS
(top view)
Tvpe
DIP 14
OUTPUT A
14
INV.INP. A
13
INV.INR 0
"
NON INV.INP. 0
OUTPUT 0
80-14
NON [NV. INP. A
-
LS404
LS404C
LS 404CB
LS 404M
LS 404CM
LS 8404
LS 8404C
-
LS8404M
LS 8404CM
3
, Vs
NON INV.INP. B
5
II
-Vs
10
NON INV.INRC
INV.INP. B
[NV, INP. C
OuTPUT B
OUTPUT C
5-3901
SCHEMATIC DIAGRAM
(one section)
NON INVERTING
INYERTING
INPUT
INPUT
R4
~
i
=!=C1 fI"
R2.
~dR19
~~4
R18
U
R14
R8
au
l'
025
~
"J.
a"
ffi"
c;
~29
024
]1 Q34
R16
~
-r--
:" RJ
- ~2
~o~ j'
[014
R2
OJ
Rl
00"
02J
.....,
~
lIe>
"
021
020
~
IH
028
RIO
RII
T
RIS
RI2
.2
"
O3SlouTP
~
~'S
OJO
T
-J{19
I L
I
S-3900
THERMAL DATA
Rthi-amb
Thermal resistance junction-ambient
max
(*) Measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mm.)
_2/_1_0_______________________
272
~1~1~~~
__________________________
LS404
ELECTRICAL CHARACTERISTICS
(Vs =
± 12V, Tamb =
25°C,
unless otherwise specified)
LS404
LS 404C
Unit
Test conditions
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Is
Supply current
1.3
2
1.5
3
mA
Ib
Input bias current
50
200
100
300
nA
Ri
I nput resistance
f = 1 KHz
0.7
2.5
0.5
5
Mn
Vos
Input offset voltage
Rg = 10Kn
I1Vos
I nput offset
voltage drift
Rg = 10Kn
T min < Top
I1T
los
Input offset current
I110s
Input offset
current drift
6T
Ise
Output short
circuit current
Gv
Large signal open
loop voltage gain
B
Gain-bandwidth
product
eN
d
Total input noise
voltage
Distortion
< T max
1
1
mV
5
5
/lV/DC
10
T min
< Top < T max
R L =2Kn
Vs = ±12V
Vs = ±4V
f = 20KHz
80
nA
0.08
0.1
nA
-°C
23
23
mA
100
95
86
100
95
dB
1.8
3
1.5
2.5
MHz
10
12
20
..)Hz
0.01
0.03
%
±3
±3
V
22
20
22
20
Vpp
1
V/I'S
f= 1 KHz
f = 20 KHz
Vs=±12V
Vs = ± 4V
20
90
f = 1 KHz
Rg = 50n
R 9 = 1Kn
R g =10Kn
unity gain
R L =2Kn
Vo=2Vpp
40
8
10
18
15
0.01
0.03
0.04
± 10
± 10
nV
DC output
voltage swi ng
RL = 2Kn
Vo
Large signal
voltage swing
f = 10KHz
SR
Slew rate
unity gain
R L =2Kn
0.8
1.5
CMR
Comm.mode
rejection
Vi = 10V
90
94
80
90
dB
SVR
Supply voltage
rejection
Vi
90
94
86
90
dB
CS
Channel separation
f = 1 KHz
100
120
120
dB
Vo
= 1V
___________________________
RL = 10 Kn
. RL = 1 Kn
f
= 100Hz
~~~~;~~~,:~~~
________________________~3/~lO
273
LS404
Fig. 1 - Supply current vs.
voltage
Fig. 3 - Output short circuit
current vs. ambient tem·
perature
Fig. 2 - Supply current vs.
ambient temperature
su~ply
0_31un
G·43)'"
Is
Isc
I.
(mA )
(mA·lf---+-+--+--+---+';Y"s=c't",rot2lTv+--+---j
I
(mA)
Vs=!.12V
1.6
-
I-"
1.2
24
--
1.4
I'-
f--+-+-+-+++-+:~-t-l
1.6
V
"'
20
""'-
"'-
'6
0.81-+--+--+-+--+--+-+-+--+-1
'2
tS
t16
±12
-so
-so
Vs(V)
Fig. 4 - Open loop frequency and phase response
0_3U1/2
~.
1____
Vs=!12V
100
""-\ i'-
80
60
RL' 2kJl
"-
"-
40
200
160
RL,2KJl_
I---
"-
I 20
"- ~If
,
'\ '-
10'
10'
10'
Tamb("C)
SYRr---"---r---r-~"""""'l
(dB)
Vs·!12V
--I-,.",-+---+--IRL=2kJl-
'00
105
F.....",,,,,,;;,""+"~...j.I,,..--·-+1---.
80
~
10'
Vs~!J- r-
(dB )
Gv
20
0 '0
Gv
'00
Fig. 6 - Supply voltage rejection vs. frequency
Fig. 5 - Open loop gain vs.
ambient temperature
G_364811
Gv
(dB)
50
--t--_Vs--t--r:\--!
\.:---1
F.....,.......+.....,I~".\d----I
'00
,
\. '\.
601---+---+---T-~-~1
80
"'
,
40
95
--~-.+
40
90
-50
10' f(Hz)
Fig. 7 - Large signal frequency response
2OL---'----'---'-_-I..._-'
50
'10
Fig. 8 - Output voltage
swing vs. load resistance
10'
10'
10'
f(ltzj
Fig. 9 - Total input noise
vs. frequency
GonUl1
)
)
\=.,2Y
I
20
Vs==12V
RL=2KA H-+lf-++I+Hf-f-\+-+++-fHl
I-I-- Gyo 2OdFl+--+++1H+H1-t--+ttH1tl
16
12 t-- d=)'I,
Rg=IOKn
'6
Vs=:!: 12V
Gv ,20dE
12
~~1~~z
.
'0
f'...,
'Kn
son;-
i
/
,
'0
'0'
~4/~1~O_______________________ ~~~I~~~~~~
274
.. .. I
_________________________
1
10'
10'
f(Hz)
LS404
APPLICATION INFORMATION
Active low-pass filter:
BUTTERWORTH
The Butterworth is a "maximally flat" amplitude response filter.
Butterwq'rth filters are used for filtering signals in data acquisition
systems to prevent aliasing errors in sampled-data applications
and for g~neral purpose low-pass filtering.
The cutoff frequency. f e• is the frequency at which the amplitude
response in down 3 dB. The attenuation rate beyond the cutoff
frequency is -n6 dB per octave of frequency where n is the order
(number of poles) of the filter.
Other oharacteristics:
• Flattest possible amplitude response.
• Excellent gain accuracy at low frequency end of passband.
Fig. 10 - Amplitude response
Ay
(dB )
~
-20
\\ .......
-40
\'
~
n=8
-60
0.1
~
II
\
.\
(1.4
\ n.6'N
II
as
fife
BESSEL
The Bes~el is a type of "linear phase" filter. Because of their linear
phase characteristics. these filters approximate a constant time
delay oller a limited frequency range. Bessel filters pass transient
waveforms with a minimum of distortion. They are also used to
provide, time delays for low pass filtering of modulated waveforms
and as Ii "running average" type filter.
The m~Jl:imum phase shift is -;" radians where n is the order
(number of poles)of the filter. The cutoff frequency. f e • is defined
as the frequency at which the phase shift is one half to this value.
For accurate delay. the cutoff frequency should be twice the maximum signal frequency. The following table can be used to obtain the -3 dB frequency of the filter.
Fig. 11 - Amplitude response
G-J1K5
Ay
(dB)
~
~'\. ~
-20
\\
\
-40
n.8 \
-3 dB frequency
Other characteristics:
• SelEiqi:ivity not as great as Chebyschev or Butterworth.
• Very small overshoot response to step inputs
• Fast rise time.
I\'.~
1\ '(
-60
0,1
as
fife
Fig. 12 - Amplitude response
(± 1 dB ripple)
CHE BYSCH EV
Chebyschev filters have greater selectivity than either Bessel or
Butterworth at the expense of ripple in the passband.
Cheby~hev filters are normally designed with peak-to-peak
rippll! va'lues from 0.2 dB to 2 dB.
Increased ripple in the passband allows increased attenuation
abovei:he cutoff frequency.
The cutoff frequency is defined as the frequency at which the
amplit\J,de response passes through the specified maximum ripple
band I\'rid enters the stop band.
Other characteristics:
• 4're~ter selectivity
• Very'nonlinear phase response
• Higll overshoot response to step inputs.
---------------------------~~~I;~~~~
n=2
.4
0.)647
Ay
I
(dB)
l'.
-20
~\
"-
n=2
\\
_40
\\ \ .4
.8\' n.6\!
I
-60
0.1
05
fife
________________________~5/~1_0
275
LS404
APPLICATION INFORMATION
(continued)
The table below shows the typical overshoot and settling time response of the low pass filter to a step
input.
NUMBER
OF POLES
PEAK
OVERSHOOT
SETTLING TIME (% of final value)
±1%
% Overshoot
± 0.1%
± 0.01%
1.9/fc sec.
3.8/fc
5.0/fc
7.lIf e
2
4
6
8
4
11
14
16
1.1/fc sec.
1.7/fc sec.
1.7/fc
2.4/fc
3.1/fc
2.8/f e
3.9/fc
2
4
6
8
0.4
0.8
0.6
0.3
0.8/fc
1.0/fc
1.3/fe
1.6/fe
1.4/fc
1.8/f e
2.1/f e
2.3/f e
. 1.7/fe
BESSEL
CHEBYSCHEV
(RIPPLE ± 0.25 dB)
2
4
6
8
11
18
21
23
1.1/fc
3.0/fc
5.9/f c
-
8.4/f e
1.6/fe
5.4/f e
10.4/fe
16.4/fc
2
4
6
8
21
28
32
34
1.6/fc
4.8/f e
" 2.7/f e .
.8.4lfe
BUTTERWORTH
CHEBYSCHEV
(RIPPLE ± 1 dB)
8.2/f e .
11.6/fc
5.1/f e
. 16.3/fe
24.8/f e
2.4/f c
2.7/fe
3.2/fe
-
-
-
Design of 2 nd order active low pass filter
(Sallen and Key configuration unity gain op-amp)
Fig. 13 - Filter configuration
C2
5-3567/2
>---+-_OVout
where:
We = 21Tfc
~
with fc = cutoff frequency
= damping factor.
_6~/l_0_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~!~I~~~:
276
___---------------------
LS404
APPLICATION INFORMATION (continued)
TAB 1
Three parameters are needed to characterize
the frequency and phase response of a 2 nd
order active filter: the gain (Gvl. the damping
factor (~) or the O-factor (0= (2 ~)-1 l. and
the cutoff frequency (f c).
The higher order responses are obtained with a
series of 2"d order sections. A simple RC section
is introduced when an odd filter is required.
The choice of '~' (or O-factor) determines the
filter response (see table).
Filter response
Bessel
Butterworth
Chebyschev
~
Q
$
1
2
$
.J2
1
2
.j2
.J2
<2 >.J2
1
Cutoff frequency
fe
Frequency at which
phase sh itt is -90"
Frequency at which
G v = -3 dB
Frequency at which
the amplitude
response passes
through specified
max. ripple band
and enters the stop
band
Fig. 14 - Filter response vs. damping factor
~-+-+++~~=~p=D~j'~'~~
=0.25
Fixed R= R1 = R2 , we have (see fig. 13)
.=D.3S
=0.5
-4 -
~=~~U'PR'03'1Yla--t-++-H-tttl
C1 =
l.L
R we
C2 =
R ~Wc
1
-,21--+-+++++-I-H---lt.....H++t-tti
-'61--+-+++++-I-H---f"~~M-+++ttH
0..2
0.5
I
1
The diagram of fig. 14 shows the amplitude response for different
values of damping factor ~ in 2 nd order filters.
5 (flfDl
EXAMPLE:
Fig. 15 - 5 th order low pass filter (Butterworth) with unity gain configuration.
Ri
151
order
------------- ~ !~m~~ ____________
7/_10
277
LS404
APPLICATION INFORMATION (continued)
In the circuit of fig. 15, for fc = 3.4 KHz and
Rj = R1 R2= Ra= R4= 10 Kn, we obtain:
=
C·I = 1 •354 • -1...
- =
R _1
21T fc
C1 = 0 421 •..!... _1_ =
·
R 21Tfc
6.33 nF
Tab. II
Damping factor for low-pass Butterworth filters
Order
1.97 nF
Cj
C2 == 1.753 ·ff·
1
21Tfc =
Ca = 0 309 • .1..._1_ =
·
R 21Tfc
8.20 nF
C3
3
1.392 0.202 3.54
5
1.45 nF
C2
0.707 1.41
0.92
4
1
C,
2
C4
1.08 0.38
C5
C&
C7
Cs
2.61
1.354 0.421 1.75 0.309 3.235
6
0.966 1.035 0.707 1.414 0.259 3.S6
7
1.336 0.488 1.53 0.623 1.604 0.222 4.49
8
0.98
1.02· 0.83 1.20 0.556 1.80 0.195 5.125
C4 == 3 325·.1..· _1_ = 15.14 nF
·
R 21Tfc
The attenuation of the filter is 30 dB at 6.8 KHz
and better than 60 dB at 15 KHz.
The same method, referring to Tab. II and fig.
16, is used to design high-pass filter. In this
case the damping factor is found by taking the
reciprocal of the numbers in Tab. II. For fc
= 5KHz and C j = C 1 = C2 = Ca = C4 = 1 nF
we obtain:
.i- 2ifc = 75.6 Kn
R2 = 1.~53 • 6. 2;fc = 18.2 Kn
R1 = 0.!21
1
Ra = 0.309
Rj = 1.i54 •
6· 2i fc =
1
1
·c·
21Tfc =
1
1
1_
R4 =3.325·C·21Tfc -
23.5 Kn
103 Kn
9.6Kn
Fig. 16 - 5 th order high-pass filter (Butterworth) with unity gain configuration.
RZ
R4
cr-I~1
Ri~:
I
I
1st order
zndorder
...;8/_1_0_ _ _ _ _ _ _ _ _ _ _ ~ ~~tm~
278
2nd order
------------
LS404
APPLICATION INFORMATION (continued)
Fig. 17 - Multiple feedback 8-pole bandpass filter.
C3
---I
C'
c•
•s
Cl
IN
Cll
C2
RI
.ll
o---jl/--=-+-1Ir--+~
O.l,..F
••
• 4
C8
.'0
.y.o----,--_+_~
R2
22K.I1
R3
22K.I1
220"'1
CD
o 22/.JF
I
C7
fc = 1.180Hz; A = 1; C2 = C3 = C5 = C6 = Cg = C9 = C IO = Cll = 3.300 pF;
R1 = R6 = R9 = R12 = 160 Kn; R5 = Rg = Rll = R14 = 330Kn; R4 = R7 = RIO = R 13 = 5.3Kn
Fig. 18 - Frequency response
of band-pass filter
II
!
(08)
(dB)
1 , 1\,
\"' ' ,
J- - , , \\
\ :\
,
i
ONE-----=-
-20
-
_'0
\
TWO"'/
, ,-
-60
OJ
.'J
_3
lWOi
.s
t'.
.6
.7
..
·8
\
AI
0.'
..
ONE "
,
\
j
,,",' rT ~ ".
,, ,
, ,
todKHz
-2
FOUR __
-80
Fig. 19 - Bandwidth of bandpass filter
f{l:rrh77T.fn-;m"'T'r.m7"7'l
9
8
~~--r-+-~--1
o
I SOURCE
~
Vs.vo
5_616611
(OPERATING AREA)
I SINK Vs. Yo
s- 299'
~ (CURRENT
--------------------------~~~~~~~l~~~
OVERLOAD AREA)
________________________3~/4
291
M0821A-M083/A - M086/A
Fig. 3 - Output loading
.14
.14
Voo
Voo
M083/A
M083/A
5-299511
5- 2996/1
APPLICATION INFORMATION
Keyboard frequencies for electronic organs (*)
OCTAVES
NOTE
0
DOH
1
3
2
4
6
5
7
8
C
16.3516 32.7032 65.4064 130.813 261.626 523.251
C#
17.3239 34.6478 69.2957 138.591 277.183 554.365 1108.73 2217.46 4434.92
D
18.3540 36.7081 73.4162 146.832 293.665 587.330 1174.66 2349.32 4698.64
0#
19.4454 38.8909 77.7817 155.563 311.127 622.254 1244.51 2489.02 4978.03
ME
E
20.6017 41.2034 82.4069 164.814 329.628 659.255 1318.51 2637.02 5274.04
FAH
F
21.8268 43.6536 87.3071
F#
23.1247 46.2493 92.4986 184.997 369.994 739.989 1479.98 2959.96 5919.91
G
24.4997 48.9994 97.9989 195.998 391.995 783.991
C#
25.9565 51.9131
A
27.5000 55.0000 110.000 220.000 440.000 880.000 1760.00 3520.00 7040.00
A#
29.1352 58.2705 116.541 233.082 466.164 932.328 1864.66 3729.31 7458.62
B
30.8671 63.7354 123.471 246.942 493.883 987.767 1975.53 3951.07 7902.13
RAY
SOH
LA
TE
1046.50 2093.00 4186.01
174.614 349.228 698.456 1396.91 2793.83 5587.65
1567.98 3135.96 6271.93
103.826 207.652 415.305 830.609 1661.22 2322.44 6644.88
The frequencies can be obtained from a 99680Hz (or multiples) master oscillator by the following division ratios,
and subsequent repeated division by 2
(*)
C#
D
Eb
E
"-
451
426
402
379
F
F#
G
G#
.,.
""-
358
338
319
301
A
Bb
B
C
284
268
+ 253
239
The frequency error in these approximations is less than ± 0.069%.
_________________________
~4/~4
292
~~~~~~~~~
___________________________
M108
M208
SINGLE CHIP ORGAN (SOLO + ACCOMPANIMENT)
•
•
•
•
•
•
•
•
•
•
SIMPLE KEY SWITCH REQUIREMENTS
FOR 61 KEYS, IN A MATRIX OF 12 x 6
LOW TIME REQUIRED FOR SCANNING
CYCLE OF 576 p.sec.
ACCEPTANCE OF ALL KEYS PRESSED
TWO KEYBOARD FORMATS: 61 KEYS
(SOLO) OR 24 + 37 (M108), 17 + 44 (M208)
KEYS (ACC. + SOLO) WITH POSSIBILITY
OF AUTOMATIC CHORDS OF THE "ACCOMPANIMENT" SECTION TOP OCTAVE
SYNTHESIZER INCORPORATED FOR
GENERATION OF 3 "FOOTAGES"
MORE THAN ONE CHIP CAN BE EMPLOYED WITH SYNCHRONIZATION
THROUGH THE RESET INPUT
SEPARATED ANALOG OUTPUTS (FOR
EACH FOOT) FOR "SOLO", "ACC'" AND
"BASS" SECTIONS (SQUARE WAVE 50%
D.C.) WITH AVERAGE VALUE CONSTANT
INTERNAL ANTI-BOUNCE CIRCUITS
KEY DOWN AND TRIGGER OUTPUTS
FOR "SOLO", "ACC." AND "BASS" SECTIONS
SUSTAIN FOR THE LAST KEYS RELEASED
IN THE "SOLO" SECTION
CHOICE OF OPERATING MODE IN "ACC."
SECTION
- MANUAL, WITH OR WITHOUT MEMORIZATION OF THE SELECTED KEY3
(FREE CHORDS WITH ALTERNATE
BASS)
•
•
•
•
- AUTOMATIC, WITH OR WITHOUT MEMORIZATION OF THE SELECTED KEY
(PRIORITY TO THE LEFT FOR AUTOMATIC CHORDS AND BASS ARPEGGIO)
MULTIPLE CHOICE POSSIBILITY ON THE
CHORDS IN AUTOMATIC MODE
- MAJOR OR MINOR THIRD
- WITH OR WITHOUTSEVENTH
LOW DISSIPATION OF ..; 600 mW
STANDARDS SINGLE SUPPLY OF +12V
± 5%
INPUTS PROTECTED FROM ELECTROSTATIC DISCHARGES
The Ml08 and M208 are realized on a single
monolithic chip using N-channel silicon gate
technology.
They are available in a 40 lead dual in-line
plastic package.
ORDERING NUMBERS: M 108 B1
M 208 B1
ABSOLUTE MAXIMUM RATINGS
Source supply voltage
Input voltage
Output current (at any pin)
Storage temperature
Operating temperature
June 1988
-0.3 to +20
-0.3 to +20
3
-65 to 150
o to 50
V
V
mA
°c
°c
1/10
293
M108-M208
PIN CONNECTIONS
*VSS
RESET
40
MCK
39
TCK
IIh,71h
38
81
415th
37
B2
IUrd
36
B3
16tROOT
3S
34
B4
BS
B"SS
"
B
33
B6
32
Fi
Fz
IT
C
10
31
NPA
11
30
F4
IT
TOB
12
29
l1iS
13
28
KPA
"
27
KPS
16'
16
25
8'
17
24
F9
4'
18
23
FlO
TEsT
19
22
FT1
**VOO
20
21
FIT
15
2E
n
F7
Fe
BLOCK DIAGRAM
S-336711
• V ss is the lowest supply voltage
•• Vee is the highest supply voltage
_2:.../1_0 _ _ _ _ _ _ _ _ _ _ _ _
294
i.;i, ~~~~m~~A1
M108-M208
GENERAL CHARACTERISTICS
The caracteristics of the M208 are similar to those of the Ml08; the only difference is the keyboard
split, which is 24+37 for the Ml08 and 17+44 for the M208 when used in "accompaniment + solo"
mode.
The circuit comprises:
a) 2 pins for clock input: one for the matrix scanning, the other for the incorporated T.O.S.;by connecting both the clock inputs to the same matrix scanning clock (1000.12 KHz). the three "footages"
generated are 16', 8' and 4'.
b) 6 inputs from the octave bars (keyboard and control scanning).
c) 3 multiplexed data inputs for addressing the bass selection. These inputs normally come from the outputs of an external memory (negative or positive logic with control inside the chip)
d) 8 signal outputs divided by section: 3 for the ·SOLO" section (16',8',4'),4 for the "ACC." section
(16' or root, 8' or 3rd, 4' or 5th, 8th!7th according to operating mode). 1 for the bass
e) 12 outputs for the matrix scanning
f) 5 "trigger" and "key down" outputs: KPS (key pressed "SOLO"), TDS (trigger decay "SOLO·), KPA
(key pressed "ACC."). NPA (pitch present in "ACC." outputs), TDB (trigger decay "BASS") respectively. These outputs, in conjunction with an external time constant, allow the formation of the envelope of the sustain and percussion effects. The duration of the trigger pulses is ~ 9 msec.
g) 1 input (reset) to synchronize the device or more than one device (with the same keyboard scanning
and using a single contact per key).
The reset action, provided by an external circuit, is of the "POWER ON RESET" (high active) type
and its duration must be ~ 0.5 msec.
h) 1 TEST pin (in use it must be connected to V DD)
i) 2 supply pins.
MATRIX ORGANIZATION (Keyboard and controls)
·M108/2«;l8
Matrix
outputs
F1
F2
F3
F4
Fs
F6
F7
Fa
Fg
FlO
Fll
F12
C 1 is
M108/208 Octave bar inputs
8}
82
83
B4
Bs
B6
C}
C}#
O}
O}#
E}
F}
F}#
G}
G}#
A}
A1#
B1
C2
C2#
°2
°2#
E2
F2
F2#
G2
G2#
A2
A2#
B2
C3
C3#
03
°3#
E3
F3
F3#
G3
G3#
A3
A3#
B3
C4
C4 #
°4
°4#
E4
F4
F4#
G4
G4 #
A4
A4#
B4
Cs
Cs #
Os
°s#
Es
Fs
Fs#
Gs
Gs #
As
As#
Bs
C6
7th OF F17th ON
3rd+/3rdSust. OFF/Sust. ON
Latch/Latch
Man/Auto
61/24 + 37 (17 + 44)
Antibounce ON/Antibounce OFF
ROM Low/ROM High
-------------------
the first key on the left, C6 is the last key on the right of the keyboard.
The main feature of this chip is the possibility of formating the keyboard either with 61 keys (only
"SOLO" without automatism) or separating it into two sections ("ACCOMPANIMENT + SOLO")
with the possibility of chord and bass automatic in the first section.
___________________________
~I~~~~?~~:
________________________
~3~/1~O
295
M108-M208
FEATURES
a) The "61/24 + 37" (17 + 44) control chooses the keyboard operating mode, i.e. the whole keyboard
dedicated to "SOLO" or 24 (17) keys dedicated to "ACCOMPANIMENT" and 37 (44) to "SOLO".
b) The "Man/Auto" control, which operates only in case of "ACC.+ SOLO", chooses the manual or the
automatic accompaniment.
c) The. "Sust OFF/Sust ON" allows the storage of the "SOLO" section and handles the whole keyboard
or 37 (44) keys depending on the operating mode.
d) The "Latch/Latch" similarly allows the storage of the "ACC." section and operates in "ACC.+ SOLO"
only.
e) The "3rd+/3rd-" which operates only in case of "ACC. + SOLO" and "AUTOMATIC", changes the
automatic chord generated from major to minor or viceversa.
f) T/1e "7th OFF/7th ON" adds the seventh to the automatic chord generated.
g) The "Antibounce ON/Antibounce OFF" disables the antibounce circuit which is usually enabled.
h) The "ROM Low/ROM High" selects between ROMs with return to "1" (Low active) or with retu'rn to
"0" (H igh active). Usually the chip is enabled for ROMs with return to "1" (Low active).
"SOLO" Operation
In this case the chip recognizes the whole keyboard as "SOLO" and does not read the controls which
concern the "ACC. + SOLO" operation.
The chip identifies all the keys pressed and transfers to the outputs of each section (ACC. and SOLO)
the analog sum of corresponding pitches.
The outputs are current generators with average value constant, therefore it is sufficient to connect the
pins to one load and send the signals on to the filters.
In the case of "Sustain OF F" each new key pressed or released is accepted or. deleted in a time"; 576 "sec.
In the case of "Sustain ON" the chip has.a different operation according to whether the new key (keys)
is pressed or released: each new key' pressed is always accepted in a time"; 576 "sec., whereas each key
released is deleted with a delay of 73 msec. and only if there are still keys pressed.
In fact, if after· the 73 msec. there are no keys pressed, the last key (or keys) released remains stored
until new keys are pressed.
In this mode it is possible to have Sustain, with external envelope shaping, for the last keys (or key)
released.
The pitch envelope is controlled by a D.C. signal KPS (any key pressed) and there is also an A.C. signal
TDS (trigger decay "SOLO") which provides a pulse whenever a key is pressed.
An appropriate anti bounce circuit, inside the chip, solves the problems associated with the keyboard
contacts.
"SOLO + ACCOMPANIMENT" Operation
In this case the chip identifies the "ACCOMPANIMENT" on the first 24 (17) keys on the left, and the
"SOLO" on the remaining 37 (44) keys and reads all the controls which concern the" ACC." section.
The "SOLO" function is identical to "61 keys" mode, but for the "ACC." section there are two pos·
sibil ities:
A) MANUAL
The chip identifies which keys are pressed in the "ACC." section, and transfers to the" ACC:' outputs
the analog sum of the corresponding pitches.
The "ACC." section is fully independent of the "SOLO" section and the signals( if there is no "LATCH")
remain at the output only while the keys are pressed even if there is "SUSTAIN ON".
296
M108-M208
The "BASS" section gives at the bass output an alternating bass between the first on the left and the
first on the right of the keys pressed in the "ACC." section; the pitch switching timing is dependent on
an external ROM (3 bits).
The "LATCH" control stores the last keys released and the output signals, including the bass output,
remain until new keys are pressed.
The TDB (trigger decay "BASS") output gives a pulse corresponding to every output change; there are
also two D.C. signals, KPA (any key pressed accompaniment) and NPA (pitches in output accompani·
ment) relative only to the "ACC." section.
The first of thes'e signals (analogous to KPS) concerns the keyboard and does not consider the
"LA TCH" condition.
The second on the contrary concerns the "ACC." output and considers the "LATCH" condition.
B) AUTOMATIC
The chip recognizes in the "ACC." section only the first on the left of the keys pressed and, according
to the setting of the following controls,produces a major or minor chord with or without seventh only
the 4' footage but with separated outputs for root, third, fifth and eighth (or seventh if the chord is
with seventh).
The bass section gives the bass arpeggio among root, third, fourth, fifth: sixth, seventh and eighth
with pitch switchinq dependent on an external ROM (3 bits).
In automatic mode the two octaves of the "ACC:' section inside the chip are connected in parallel
both for the chord and for the bass; therefore by pressing anyone of the two keys of the same note
the chip generates the same chord.
The "LATCH" control stores the major chord and the bass pitches (until new keys are pressed); the
modification of the chord stored (from major to minor, addition of seventh) is always possible by
operating the proper controls: by releasing these controls the chord becomes major again.
It is possible to delete the stored pitches both is manual and in "AUTOMATIC" mode by a Latch
control signal.
Once again there are KPA, NPA, and TDB information; however the TDB pulse, which normally
appears at each arrival of the ROM codes, does not appear if there are no pitches in the "ACC."
(and bass) outputs or, in the case of alternate bass (in manual mode) if the codes indicate conditions
of indifference.
RECOMMENDED OPERATING CONDITIONS
Parameter
Test conditions
Min.
Vss
Lowest supply voltage
0
V DD
Highest supply voltage
11.4
___________________________
~~~~~~~,:~~~
Typ.
12
Max.
Unit
0
V
12.6
V
_________________________5~/l_O
297
M108-M208
BASS TRUTH TABLES
LOW ACTIVE
External
Mamory Code
C
B
A
Bass Arpeggio Output
Alternate Bass Output
(Automatic model
(Manual model
1
1
1
No change
No change
1
1
0
Root
1st on the left
1
0
1
3rd
1
0
0
4th
-----
0
1
1
5th
1 st on the right
0
1
0
6th
---
0
0
1
7th
---
0
0
0
8th
---
HIGH ACTIVE
External
Memory Code
298
Bass Arpeggio Output
Alternate Bass Output
(Automatic model
(Manual model
C
B
A
0
0
0
No change
No change
0
0
1
Root
1 st on the left
0
1
0
3rd
---
0
1
1
4th
---
1
0
0
5th
1st on the right
1
0
1
6th
---
1
1
0
7th
1
1
1
8th
-----
M108-M208
STATIC ELECTRICAL CHARACTERISTICS
Tamb =
(Positive Logic, Voo
= +12V ± 5%, Vss =
a to 70"C unless otherwise specified)
Test conditions
Min.
Typ.
Max.
av,
I I
Unit
INPUT SIGNALS
V IH
V IL
'Ll
Input high voltage
Input low voltage
Input leakage current
Note 1
Voo-1
Voo
V
Note 2
4
18
V
Note 3
Voo-2
Voo
V
Note 1
Vss
Vss +1
V
Note 2
Vss
Vss +O·6
V
Note 3
Vss
V ss +2
V
10
jJA
300
500
G
15
25
kG
Voo
V
V I= +12.6V
T amb = 250 C
LOGIC SIGNAL OUTPUTS
RON
9utput resistance with respect
to Vss
RON
Output resistance with respect
toV oo
V OH
Output high voltage
VOL
Output low voltage
VOUT= Voo-1
(driver off)
Voo-O.4
Vss+0.2 Vss+0.4
V
POWER DISSIPATION
1'00
- Supply current
30
45
mA
ANALOG SIGNAL OUTPUTS (the external load must be connected to V 0012)
IOH
Output current with respect
to Vool2
Outputs loaded with 1 KG
'resistor versus V 00/2
8
20
jJA
IOL
Output current with respect
to Vss
Outputs loaded with 1 KG
resistor versus V 00/2
-8
-20
jJA
N{lte1: Refers only to the clock inputs.
Note 2 : Refers onlv to the inputs from the external memory.
Note 3 : Refers only to the reset input.
__________________________
~~~~~~~~@~
______________________~7/~lO
299
M108-M208
DYNAMIC ELECTRICAL CHARACTERISTICS
Parameter
Test conditions
Min.
Typ.
800
1000.12
Max.
I I
Unit
MASTER CLOCK INPUT
fi
Input clock frequency
't r • tf
Input clock rise and fall time
10% to 90%
ton, toff Input clock ON and OFF times
1000,12 KHz
KHz
40
1000 KHz
500
ns
ns
T.O.S. CLOCK INPUT
f'i
Input clock frequency
100
1000.12
2500
KHz
t r• tf
Input clock rise and fall times
10% to 90%
1000.12 KHz
40
ns
ton, toff
Input clock ON and OFF times
2000 KHz
250
ns
TDS and n5B OUTPUTS
ton
Pulse duration
1000 KHz
9.216
ms
t r , tf
Outputs rise and fall times
10%to 90%
1000 KHz
100
ns
INPUT CLOCK WAVEFORM
Ir
If
~8/~1~O________________________ ~~~~~~?~19~
300
ton
5-3368
___________________________
M108-M208
----- -----
FREQUENCY RANGE OF EACH OCTAVE (16', S', 4' footages)
16'
32
61
B
C
8'
4'
123
65
C
8
130
246
8
C
130
246
261
C
261
8
493
C
523
65
123
I-----t
C
B
130
246
I-----t
C
8
C
~
C .
C
~8
~
--8-2--
--8-3--
--8-4--
81
B
B
Ace. SECTION
493
523
B
987
1046
8
11046
B
C
987
C
19751
C
1975
B
12093
3951 1
C
8
85
SOLO SECTION
(ONlV Ml08)
(ONLY Ml08)
le46
1
C
12093
C
14186
C
I
86
5-3369"
CONNECTION OF THE KEYBOARD AND CONTROL SWITCHES
t
LAST KEY
1st OCTAVE on
THE LEFT
ii ~]'i't fiT fJ tJ t~JT n}ll' }H
Fu
2nd OCTAVE 3rd OCTAVE loth OCTAVE 5th OCTAVE
1 L_--1
OCTA~E
BAR
81
82
83
AC,C. SECTION (ONlVM108)
(2 octavE'S = 24 keys)
'i
84
L
CONTROLS
4
6W
85
SOLO SECTION (ONl.YM108)
(3 octaves =37(36.1 )keys)
86
5-3372/1
Note: The switch "OPEN" corresponds to "KEY NOT PRESSED" or "CONTROL IN THE FIRST CONDITION" (see
the drawing "MATRIX ORGANIZATION").
TYPICAL APPLICATION
n
TO
Fii
orrfDD
TO
,---------1"
.,
.,
.,
••
.
~:tR=
.----.~-
t-----~~.--+-
a
1-----4~+__+__t__+-I_+_-O::
I SOLO OUTPUTS
W
""""1
1 - - - - - - -......-+-1_+_-0 "'5th
1---------4-!--+_-O 8"lrd
Ace.
OUTPUTS
1------------I--+_-o16'/ROOT
"
"
I-----------~_o BASS OUTPUT
"
"
ii'PA
1m
35
,.
rn
"
f1jj
I•
• 2 1--------4~+__----l 37
,
..
301
M108-M208
TIMING DIAGRAMS
M~~
___________________________________________________
l' ______......J
u _ _ _ _ _......J
~----------~
5-3310
Note: MCK is the master clock input (matrix scanning), <1'1, <1'2, <1'3 are internal phases to generate
L
L
FT -;- F 12.
RESET - ,
~---------------------------------------------------------
I
I
I
LJ
I
I
LJ
LJ
LJ
LJ
~
u-L
LJ
LJ
LJ
LJ
LJ
LJ
I
I
LJ
Note: The matrix scanning starts (after the power on reset) at the second arrival in output of Ff (*) from 81 to 86 in
continuous sequence.
_1...;.0/_1_0_ _ _ _ _ _ _ _ _ _ _ _ I:iii.I~t~m?!t©~~
302
---___________
M112
POLYPHONIC SOUND GENERATOR
• 8~P PROGRAMMABLE SOUND GENERATOR CHANNELS
• 2M Hz CLOCK
• INTERNAL TOS WITH POSSIBILITY OF
EXTERNAL SYNCHRONIZATION FOR
MUL TICHIP USE
• 6 COMPLETE OCTAVE KEYBOARDS (72
KEYS)
• FIVE HOMOGENEOUS FOOTAGES ~P
PROGRAMMABLE BY ADDING A CONSTANT K TO THE KEYBOARD SITUATION
• SEVEN OCTAVE RELATED OUTPUTS
ENVELOPED WITHOUT CONSTANT DC
LEVEL (4 FOOTAGES)
• SEVEN FOOTAGE RELATED OUTPUTS
WITH DIFFERENT CONFIGURATIONS
FOR:
- FOOTAGES WITH ENVELOPE (WITHOUT
CONSTANT DC LEVEL) AND:
- FOOTAGES WITHOUT ENVELOPE (WITH
CONSTANT DC LEVEL) AND:
- VARIOUS SOUND CHANNEL DIVISIONS
(SEE OPTION I, II AND III)
• POSSIBILITY OF EXCLUDING ONE OR
MORE SOUND CHANNELS FROM THE
NON ENVELOPED FOOTAGE OUTPUTS
• ONE MONOPHONIC OUTPUT NON ENVELOPED RELATED TO SOUND CHANNEL 1 WITH THE POSSIBILITY OF CHOOSING THE FOOTAGE (TWO ADDITIONAL
MONOPHONIC OUTPUTS ON OPTION II)
• 50% DUTY CYCLE ON ALL OUTPUTS
• DIGITAL DRAWBAR CONTROL
(32 LEVELS)
• ATTACK - DECAY - SUSTAIN - RELEASE
(ADSR) ENVELOPE DEFINITION WITH
DIGITAL CONTROL ON A.D.R. AND
ANALOG CONTROL ON S
• ADDITIONAL ANALOG CONTROL ON
RELEASE
• ANALOG PERCUSSION INPUT TO ENVELOPE ONE FOOTAGE (M2) ON THE
OCTAVE RELATED OUTPUTS
• SPECIAL EXTERNAL ENVELOPE POSSIBILITY USING HOLD AND/OR RELEASE 00
HOLD AND RELEASE ooARE DEDICATED
TO DECAY AND PEDAL EFFECT
June 1988
DIP-40 Plastic
ORDERING NUMBER: M112B1
PIN CONNECTION
ANALOG GROUN,?
[~
VSA
VSS2
01E
39()';E
STROBE.STO
3
38
OItE
RESET
4
37
06E
CLOCK
5
3.6 02E
OA1A
BUS
01
6
35 03E
02
7
34
07£
OJ
04
8
9
33
CH'3I
~Tt~
32 tH6
O~
10
31 CHl
06
11
30 CHit
ADA CONTROL -VT
12
29 tHe FOR ENVW)PE
Voo
13
28 tH3
27 CHZ
6~~!;'~t;
8 CAPACITORS
FNJ
14
FMZ
15
2
FMZE
16
25 VAR-ANALOG RELEASE
FM1£
17
21. Vrwg
FH1E
18
23 VSUSTAIN CONT~OL
FLE
19
22
FL
20
21 Clm·MONOPHONIC OUT
CH1
IA.DSR
PERC.M2
!I_!i6Jl
•
N-CHANNEL TECHNOLOGY -12V SINGLE
SUPPLY.
The M112 is a polyphonic sound generator that
combines eight generators with envelope shapers
and drawbar circuitry in a single package.
This versatile circuit simplifies the design of a
wide range of polyphonic instruments and, in·
terfacing directly with a microcomputer chip,
gives designers an unprecedented degree of
flexibility. The Ml12 is realized on a single
monolithic silicon chip using low threshold
N-channel silicon gate MOS technology. It is
available in a 40 lead plastic package.
1/16
303
M112
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Off state output voltage
Total power dissipation
Storage temperature
Operating temperature
-0.3 to 20
-0.3 to Voo
-0.3 to 20
500
-65 to 150
o to 70
Stresses above those listed under "Absolute Maximum Rarings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
* All voltages are with respect to Vss.
BLOCK DIAGRAM
~-----------------------------~~~
r;:=~~=====::::;~~~~::) NON
ENVELOPEI'>
~'PUTS
DATA
BUS
S_
PERC.Ml
ANALOGUE
L..._____...:.........r---- REU.ASE
RESET
RECOMMENDED OPERATING CONDITIONS
Parameter
Voo
304
Highest Supply Voltage
Test conditions
Min.
11.4
I
I
Values
Typ.
12
I
I
Max.
12.6
Unit
V
M112
STATIC ELECTRICAL CHARACTERISTICS
(V oo
= 12V ± 5%, Vss = OV, Tamb = 0 to 50°C unless otherwise specified)
Test conditions
Paramater
INPUT SIGNALS
V'H
V'L
Input High Voltage
Input Low Voltage
Pins 3, 6 to 11
2.4
Voo
V
All other inputs
6
V
V
Pins 3, 6 to 11
-0,3
Voo
0.8
All other inputs
-0.3
1
< 10n
VSA
Analog Ground
R
VT"
ADR Control Time
R = lK
VAR
Analog Release
R = 10K
V reg
Control OFF Asymptote
R
1----
V SUST• Control Level Sustain
Perc. M2 Control Level Percussion
ILl
I nput Leakage Current
< 10n
R -lK
C = 100l'F
0
C - 11'F (note 3)
0
1
V
Voo
V
Voo
V
1
V
0
Voo
V
0
Voo
1
I'A
"A
C = 0.1"
0
C= 1001'
0
C = 100" (note 2)
R -10K
0
V
0
V,- Voo
V
OUTPUT SIGNALS (One key pressed)
IOL
Output Low current
VOL = VOO/2-1 V (note 1)
10
30
50
VOH = V O O/2+1 V (note 11
10
30
50
"A
100
300
500
10
30
50
"A
I'A
10H
Output High Current
VO H = 10V VCHN = Vo o l2(*)
10(off)
Off state output current
V OH = 10V VCHN = V o/2
Vo = Voo(all output pins)
o
Vo = VSS (pins 14·15·20 in
3 rd state I
1
"A
-1
"A
50
mA
POWER DISSIPATION
1100
Supply current
Notes: 1. Refers only to FL, FM1, FM2 (pins 20,15,14).
2. With a standard ADSR VSUST";; 4.5V
3. The best region is VT - VSUST"" 4V
(*) Refers only to octave outputs with drawbar max.
DYNAMIC ELECTRICAL CHARACTERISTICS
Parameter
Test conditions
CLOCK
fj
Input Clock Frequency
t r , tf
Rise and Fall Times 10% to 90%
250
2000.24
2.300
30
ton, taff ON and OFF Times
150
kHz
ns
ns
RESET
Pulse Width
tf
Clock = 2 MHz
Fall Time
OUTPUT SIGNALS
ton, toft Outptu duty cycle
50
__________________________ ~~~~~~~~----------------------~3/~16
305
M112
GENERAL DESCRIPTION
The M112 contains a microprocessor interface, eight programmable sound generator channels, a top
octave synthesiser, a divider chain and control circuitry, (see fig. 1). Each generator consists of logic to
select the desired notes and harmonics from 96 frequencies obtained by division, an ADSR envelope
generator and two voltage-controlled amplifiers. Programmable attenuators are included for drawbar
control of the harmonic content of the sound.
To simplify system design the signals generated in each channel are directed to octave separat.ed outputs
and footage outputs. Two voltage-controlled amplifiers are provided for each channel to keep the octave
and footage outputs separate.
The attack time, decay time, release time and sustain level are set for all eight channels by common
controls. Tone selection, the attack, decay, release parameters, drawbars and special effects are all soft·
ware controlled.
In a typical configuration (fig. i), one or more M112s are connected to a microprocessor which scans
the keyboard and front panel controls in a matrix arrangement. When the microprocessor detects a key
depression it chooses one of the sound generators and allocates it to that note. If another key is pressed
the microprocessor allocates another sound generator and so on. This process can be repeated until there
are no more free channels, i.e. when 8N keys are pressed simultaneously where' N is the number of
M112s used.
When one of the keys is released the microprocessor resets a control bit in the appropriate generator
channel which will-then be re-allocated to another key when needed.
Fig.2
Kf'(80AROS
AND
COMMANDS·
L~
~
L -_ _ _ _ _ _
OUTPUTS
The M112 has 15 music output pins. Seven of these are octave outputs, seven are footage outputs and
the last is a monophonic output from channel one. This standard configuration can be changed under
progrim control.
The octave outputs, which are enveloped, are so called because there is one output for each octave, i.e.
output signals from all eight channels that fall within the same octave are routed to the same output.
These outputs are provided to simplify the generation of sinewaves from the squarewaves generated by
the M112s digital circuitry. Since each of these outputs handles a limited range of frequencies - exactly
one octave - a simple low pass or bandpass filter will do the job. Th~ blend of harmonics sent to the
octave outputs is controlled by the drawbar attenuators.
The footage outputs are related to the five footages generated by the M112. These are referred to as L,
M1, M2, H1 and H2 (L = Low, M = mid, H = high) and can be programmed to give the three different
ranges given in table 1, adding a constant K (number of half tones) to the keyboard information.
All five ·footages can be obtained from these outputs but only four are mixed by the drawbar circuitry
and routed to the octave outputs.
~4/~16~
306
______________________
~~~~~~~~~
__________________________
M112
TABLE 1 - THE THREE FOOTAGE RANGES OF THE M112
Enveloped footage outputs (option 21
Octave outputs .
Non Enveloped Footage Outputs
~
L
M1
M2
H1
H2
0
16'
S'
4'
2'
l'
7
10 2/3'
5 1/3'
22/3'
1 1/3'
2/3:
4
12 4/5'
6 2/5'
(31/5'
13/5'
4/5'
Fig. 3 - Example of octave related output "EVEN" and "ODD" with Percussion input .
~.
.-
J
"'112
(16'8'4'n
-~
Perc.un
--t- ~ • IIV
~1
tt
01
32 -123Hz
01
130-246 Hz
03
261-493 Hz
04
,23-987 Hz
0,
1046-1975 Hz
06
2093 -3951 Hz
4186 -7902 Hz
07
"'112
Note : All the notes higher
than 7902Hz are available
divid ed by2.
01 -
(10 213 ',113' 1213'1113') 02
-
03
04
~
Peofc.(2 213 ')
0,
06
_._----.
07
I
!:I. 5671
In no case will the maximum frequency be higher than 7902 Hz (with a 2 MHz clock).
The output configuration for the octave and footage outputs can be changed under program control as
mentioned above. There are three options, including the standard configuration, and these are:
•
Option 1, the normal configuration gives four enveloped footage outputs, LE, M 1E, M2E, H 1E, and
three non-enveloped outputs, L, M 1 and M2. All eight channels are present on each output.
•
Option 2 is a special configuration for sawtooth generation (sawtooth waveforll)s are frequently used
in sound synthesis). In this case channels two and three appear only on the outputs FMl and FM2
(footages Ml and M2) and are excluded from the rest. All five footages are available as enveloped
outputs.
•
Option 3 is intended for sophisticated automatic accompaniment circuits. All the channels appear on
three non-enveloped outputs (FL, FM1, FM2) for chord generation and can be disconnected or
command. Channels 4, 5, 6 and 7 appear on four enveloped outputs for arpeggio The octave outputs
are used for the bass and include only channel 8.
-------------
~ ~~tm~l~~~
___________
---"5~/16
307
M112
TABLE 2 - OUTPUT CONFIGURATIONS
Pin
15
14
20
18
16
17
19
40
36
35
38
39
37
34
21
-
Option I
. Option II
Option III
Option IV
FM2
FMl
FL
FH1E
FM2E
FM1E
FLE
For the
8 channels
OlE
02E
03E
04E
05E
06E
07E
Monophonic out
(channel 11
FM2 (Channel 31
FMl (Channel 21
FH2E
FH1E
FM2E
FM1E
FLE
OlE
Only channels
02E
1-4-5-6-7-8
03E
04E
05E
06E
07E
Mono
(channel 11
only channels
4-5-6-7
FM1E
FLE
OlE
02E
03E
only channel B
04E
05E
06E
07E
Mono
(channel 11
FM2 (Ch. 31
FMl (Ch. 21
FH2E (Ch.4.5.6. 7.81
FH1E .
only channels
FM2E
4-5-6-7
FM1E
FLE
OlE
02E
03E
only channel B
04E
05E
06E
07E
Mono
(channel 11
Standard use
Special for sawtooth
generation etc.
Special for high class
accompaniment
Only for information
(no musical meaningl
FM2
FMl
FL
FH"
FM2E
All channels
I
} (see note 31
FL. FM1. FM2 are footage outputs not enveloped (with constant DC levell
FLE. FMl E. FM2E. FH 1E. FH2E are enveloped (without constant DC levell.
Notes:
11 H2 is available only in option 2 on FH2 enveloped outputs. It is not available on octave related outputs.
21 In. the option 2 the Sound channels 2 and 3 are available only on pins 14 and 15 and consequently are
excluded from the other outputs.
31 Each channel can be disconnected with commands NCl to NCB (register 101.
DRAWBARS AND EFFECTS
One of the significant features of the Ml12 is the implementation of drawbar control circuitry. This
consists of four programmable attenuators, one for each of the footages routed to the octave outputs,
which are used to blend harmonics to produce the desired sound.
Other features of the Ml12 include hold, pedal and percussion effects, all of which are enabled/disabled
under software control. Hold, when active, interrupts the decay of the ADSR envelope and Pedal interrupts the release curve. Hold' and pedal permit external control of the envelope. This feature can be
used, for example, to syntt!esize very realistic piano and harpisichord sounds.
A piano effect can be produced by suitably programming the envelope shapers but by using the hold
and pedal controls and a 'few external components much greater realism can be obtained. Fig. 4 shows
a simplified schematic of one of the envelope shapers together with the type of envelope generated. The.
envelope parameters are controlled by RA, RD, RR and Vsus (RA, RD and RR are programmed resistors
controlling attack, decay and release). Disabling the natural decay and release and adding a handful
of components a close approximation to the ideal waveform can be produced (fig. 5).R 1. is a very large
resistance (typically 3 Mn) to give the long (several' seconds) time constant for the second decay.
~6/~1_6_______________________ ~!~1;~~~~
308
__________________________
M112
Fig. 4 - With an external capacitor the M112's envelope shapers produce the standard ADSR envelope.
,,
r - - - - - - - - - - ----- - - - - - -- - --,
01112
r - - - -.....9VSUSTAIN
RD
x
RR
MUSIC
1..--- _______________________ I
Fig. 5 - Disabling the normal decay and release and adding a few external components a realistic piano
envelope can be produced.
r------------------- - --,
M112
:,
l·VOD
0 vSU51AIN
'
+12V
I
I
,
I
RD
RA
x
S_S61O
f
NUSIC
~---------------------:
5-561l
INPUTS
Eight pins on the M112 are used to define the elementary time interval of the ADSR envelope shapers
(Pins 26 to 33). Capacitors, nominally 11lF, are connected to these pins. Eight separate capacitors are
necessary because the envelope shapers are independently trigge~ed. Analog inputs are also· provided to .
adjust the asymptotic release level (V reg pin 24) and the charge/discharge. current for attack, decay and
release (VT pin 12) in order to compensate the differences of ADR time constant between several
'Ml12s used in the same instrument.
The sustain level is fixed by the voltage at pin 23.
The release time constant, digitally controlled by software, can' also be fine adjusted by a trimmer connected at pin 25.
__________________________
~!~~:
______________________
~7/~16
309
M112
PROGRAMMING
The M112 is programmed using five basic commands:
•
•
•
•
•
CHANNEL PROGRAM
ADSR PROGRAM
NON-ENVELOPED OUTPUT MASK
LOAD CONTROL REGISTER
DRAWBARPROGRAM
These commands all consist of 12 bits transferred to the M112 (or one of the M112s) in two six-bit
bytes through six data lines. Data is latched into the M112 synchronously by a strobe signal. The M 112
can be connected directly to an M387X series microcomputer.
Each command contains the address of the Register in which data is to be memorized (there are 16 reo
gisters) and the data.
Channel program commands consist of the channel code (4 bits), octave code (3 bits). note code (4 bits)
and a control bit, KP (key pressed). KP must be set if the key has just been pressed and reset if the note
has just been released.
01
I
CHANNEL
01
00
I
KP
I
06
02
CHANNEL
PROGRAM
NOTE
Resetting KP does not necessarily silence the channel because the sound continues after the key has been
released if the release time is non-zero. To stop a channel completely the unused note and octave codes
are used.
If an unused note code is programmed the channel is 'turned off with the output transistor in the ON
state and if an unused octave code is used the channel is turned off with the output transistor in the
OFF state. Six octave codes and twelve note codes are recognized,giving a keyboard span of 72 keys.
For example, to tell an M112 that channel three is to play F# in the, third octave the command is:
01
06
o
o
o
o
o
1,
o
CHANNEL 3 CODE IS 0010
OCTAVE 3CODE IS 011
F # NOTE CODE IS 0110
KP IS SET
The ADSR Program command sets the attack, decay and release times for all the envelope shapers,
This command takes the form:
06
01
r1
I
o
o
d2
d1
0
I
a3
I
r3
a2
I
r2
a1
ADSR
PROGRAM
The code 1000 selects the ADSR control register, a3/a2/a1 is the attack time, d2/d1 is the decay time
and r3/r2/r1 is the relase time. These times are all multiples 'of the time interval set by external capacitors. With the suggested 1MF values this time interval is 3ms. The release code 000 is used to enable
the pedal effect .
1 ..:..
6 ___________
8/c::.
.:;:
310
~ ~~m~
------------
M112
The Non-Enveloped Output Mask command is used to select which channels are to·be routed to the
non.-enveloped footage outputs. Any or all of the eight channels can be excluded by setting the appropriate bit.
01
NCG
06
o
a
1
NC5
NC4
NC3
I
NCB
NC7
NC2
NCl
OUTPUT
MASK
The Load Control Register command selects the footage and output options and enables/disables the
hold and percussion facilities.
06
01
LOAD CONTROL
REGISTER
HOLD
"NC1 m" is a control bit that excludes channel one from all outputs except the three non-enveloped
footages outputs. PO is the percussion disable bit, m2/m1 is the footage option select code for the monophonic output and OP2/0P1 the output configuration select code.
The drawbar-controlled attenuators are set independently for each footage using the Drawbar Program
Command which has the form:
~
01
•
FOOTAGE
~
ATTENUATI~
DRAWBAR
PROGRAM
Footage is selected by addressing registers R12 to R15.
Attenuation is controlled in 32 linear steps which can be conveniently reduced to the conventional 16 or
8-step logarithmic scale using a lookup table.
APPLICATIONS
The M112 is intended for a wide range of appl ications ranging from simple single-keyboard organs to
2-3 manual instruments with sophisticated synthesis and accompaniment facilities. It can also be used
in electronic pianos, harpsichords, string synthesizers etc.
DESCRIPTION
Pin 1 - VSA Analog ground
Ground connection of all outputs. It is typically connected to Vss. By adjusting its value with respect
to Vss (plus/minus) it is possible to modify the output current and compensate the differences in current between several M112s used in the same applications.
Pins 2 and 13 - V ss , Voo
Power supply connections. Voo is nominally 12V; Vss is to be connected to GND.
Pin 4 - Reset input
It is used to synchronize various M112s in multichip use. The reset is activated when the input is at H
Level. In this condition the chip is blocked.
--------------------------~I~t;~g~~~
______________________~9/~16
311
M112
Pin 5 - Clock input
It has to be connected to an external oscillator of 2 MHz.
Pin 6 to 11 - 01, 06 Data bus input
Pin 3 - STO Data Strobe input
These pins are used to transfer the 12 bits of data from the microprocessor to the registers of various
Ml12s using a two phase procedure.
The first six bits of data are latched on the positive edge of STD, while the other six bits are latched on
the negative edge of STD.
.
Each 2 x 6 bit of information contains the address of the register (4 bit/16 registers) and the data up to
8 bits to be memorized in the selected register.
2 nd PHASE
1st PHASE
01
I
AJ
A2
AI
AO
I
06
0601
X
ADDRESS OFF THE
REGISTER
X
I
X
I
X
DATA
S-'iE;75
TABLE 3 - REGISTER SELECTION
AO
A1
A2
A3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Register nO
1
2
3
4
5
6
1
1
1
1
1
13
14
1
1
15
16
1
Note-octave etc.
For Sound chahnel
7
8
9
10
11
Q
Register function
12
Control Commands
Used for test *
. .
• ThIS a.ddress sets the Ic on a test condItIon that can only be modifoed by a Reset command on pin 4 .
::..;10"-/1::..;6=--_ _ _ _ _ _ _ _ _ _ _
312
~ ~~~~m~1r~~@~
--------------
M112
Registers 1 to 8
There registers are related to the sound channels
Bus
Data
PHASE 1
01
02
03
04
05
06
A3
A2
A1
AO
KP
02
PHASE 2
01
02
03
04
05
06
01
00
N3
N2
N1
NO
must be "0"
Sound
} Channel
Selection
Key
information
AO-A2: Sound channel selection with reference to table 3, register 1 is related to channel 1, register 2 to
channel 2 and so on up to channel 8.
KP : 1 = pressed key 0 = relased key
00-01-02: Octave code of the note (Table 4).
TABLE 4
00
01
02
Code
0
0
0
0
Octave
1
0
0
1
0
1
0
2
2
1
1
0
3
3
0
0
1
4
4
Note OFF
1
0
1
5
5
0
1
1
6
6
1
1
1
7'
N2
N3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
NO-N1-N2-N3 = Note Code (Table 5)
TABLE 5
N1
NO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
1
1
1
\
1
Output
transistor
"OFF"
Note OFF
Code
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I
Note
DO
00#
RE
RE#
MI
FA
FA#
SOL
SOL#
LA
LA#
SI
Note "OFF"
Note "OFF"
Note "OFF"
Note "OFF"
I
Output
transistor
"ON"
--------------------------- ~~~I~~~~ ______________________~1~1/~16
313
M112
Register 9 to 15
These registers are related to the various control commands
TABLE 6
~
Data
R11
R10
R9
R12
R13
R14
R15
R16
1
1
1
Bus
PHASE 1
PHASE 2
01
02
03
04
05
06
01
02
03
04
05
06
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
r3
r2
1
NCB
NC7
1
1
1
1
PO
X
X
X
X
X
X
X
X
X
X
rl
d2
dl
a3
a2
a1
Ne6
NC5
NC4
NC3
NC2
NCl
HOLO
OP3
OP2
NC1m
m2
m1
X
L5
L4
L3
1,.2
L1
X
Ml 5
Ml 4
M1 3
M1 2
NIl 1
X
M25
M24
M2 3
M2 2
M2 1
X
Hl 5
Hl 4
H1 3
Hl 2
H1 1
X
X
X
Envelope Channel
off
v
Vanous
X
X
X
X
Test
Orawbar Jevel on four
footages only for
octave outputs
Register 9 - R9 selects the ADR envelope parameters for ADSR control (see fig. 6)
Attack - a1 - a2 - a3
Decay - d1 - d2
Release - r1 - r2 - r3
3 bit }
2 bit 8 bit
3 bit
Fig. 6 - ADSR envelope control
KEY
PRESSED
..J
I
WITH HOLD
(SEE REGISTER10) :-1
________
I _ _ _ __
I
I
I
VSUSTAIN
ENVELOPE
I
DECAY
I ATTACK
: 3BI!
2 BIT
I(al a2 a3ll (dl d2)
I
I
I
1~~L.3.!:F_e~i~E
II
ASVMPT. LEVEL
SUSTAIN
iRELEASE
(CONTROLLED: 3BI!
BY VOLTAGE
I (,1,2 r3)
ON PIN23)
I
V'eg
(PIN24)
I
I
~12~/~16~_____________________ ~1~~~~~
314
TABLE?)
_________________________
M112
Table 7 shows the various time constants for Attack, Decay and Release.
TABLE 7
a2
a1
d2
d1
r3
r2
r1
0
0
0
0
1
0
1
a3
0
Daeay
.Rel_
0
1
1
0
1
1
1
1
Attack
0
0
1
1
0
1
0
1
•
T/2
4T
T
2T
4T
ST
16T
32T
64T
ST
16T
T
2T
32T
4T
ST
16T
00
32T
64T
* In this case it is possible to obtain the pedal effect.
T = 3 ms is the typical time constant unit with S external capacitors of
1 IJF connected to pins 26 to 33.
Register 1() - Contains 8 commands to exclude the corresponding sound channel from the non-enveloped
. footage outputs (FL-FM1-FM2)
0= ON
1 = OFF
Register 11 - Contains the following 8 commands: m1 and m2 select one of the four footages available
for the monophonic output (C1m) according to table 8.
TABLES
m1
m2
K
0
7
0
0
16'
10 2/3'
4
12 4/5'
1
0
S'
5 1/3'
6 2/5'
0
1
4'
22/3'
1
1
2'
11/3'
3 liS'
1 3/5'
OP2-0P~ - Select thE' four output options described in table 2 according to tabel 9.
TABLE 9
~
OPTION
I
II
III
IV
----i----------
OP2
OP3
0
1
0
0
1
1
0
1
J;.V,.I~~~:
__________
........::1""3/~16
315
M112
HOLD - If 0, disconnects the external 8 capacitors of envelope (1 ~F)from the V SUSTAIN pin (pin 23)
in the decay phase.
PO (Percussion Off) - If 1, the percussion input is inhibited (see pin 22 description).
NCl m-Ifl, eliminates channel 1 from all outputs except the 3 footage outputs not enveloped (it can be
eliminated from these outputs through the command NCl of register 10).
N.B. NClm command is inoperative on the mOnophonic output (Clm) where channell is always pre·
sent.
Registers 12-13-14-15
These registers contain the drawbar control for 4 footages on the octave related output.
Footages l, Ml, M2 and Hl are controlled in 32 linear levels or for example, using conversion table in
the microprocessor in 8 or 16 logarithmic levels.
Table Hl shows an example of footage L with 32,16 and 8 step control in dB.
TABLE 10
Attenuation in dB
L
L
L
L
L
5
4
3
2
1
32 steps
16 steps
S steps
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
-29.8
-23.8
-29.3
-17.8
-15.8
-14.3
-12.9
-11.8
-10.7
-9.8
-9.0
-8.2
-7.5
-6.9
-6.3
-5.7
.-5.2
-4.7
-4.2
-3.8
-3.4
-3.0
-2.6
-2.2
-1.9
-1.5
-1.2
-0.9
-0.58
-0.29
0
OFF
-29.8
-23.8
-20.3
-17.8
-15.8
-14.3
OFF
-29.8
-23.8
-20.3
1
~14~/~16~______________________ ~!~~~~~4
316
-14.3
;
,".!"
-11.8
-9.8
-9.0
-8.2
-6.9
-5.7
-4.2
-4.2
-3.0
-1.5
0
0
---------------------------
M112
Pin 12 - VT - ADR Control
It is used to adjust the ADR time constant for several M112s used in th'e same application. Using a single
M112 it has to be connected to V DO'
.12V
i'>-__-----1VT Ml12
5-
~617
Pin 14 to 20 - FM1. FM2. FM2E. FM1E. FH1 E. FLE. FL (Footages output)
The "wired-or" function is possible on all outputs.
The non enveloped outputs (with constant DC level) are push-pull current generators.
The enveloped outputs (with non constant DC level) are open drain sink current generators. Output duty
cycle is 50%.
Pin 21 - C1m
Monophonic output of channel 1 (always present). Duty cycle of the waveform is 50%. Open drain
output.
Pin 22 - Percussion M2
Using a specific signal on this input it is possible to have a percussion effect on M2 footage for the octave related output.
Pin 23 - V
SUSTAIN
This input defines the level of sustain (see fig. 5).
Pin 24 - V rag
This pin controls the asymptote of V RELEASE through the gate of a transistor which discharges the envelope capacitor. If the performance at the end of release time is considered satisfactory. this pin must
be connected to V55- Otherwise this input can be connected to a voltage not higher than 1V.
Pin 25 - V AR Analog release
This pin is intended for analog control of the release time constant when it is required in addition to the
digital one controlled by software.
V
10Knf12
I
VAR
1IJF
Ml12
~----'
5-5678
---------------------------~~~t;~~~~:
______________________~1~5~/l~6
317
M112
It allows intermediate values not included in table 7 (see explanation of register 9). In the case of pedal
effect connect this input to vss.
Pin 26 to 33 - CH1, CH8 Envelope capacitor inputs
8 capacitors (typical value = 11lF) have to be connected for the ADSR envelopes.
Pin 34 to 40 - 01 E, 07E Octave Outputs
Octave related outputs. Duty cycle is 50%.
;:..16:..:./;;;.;16'--_ _ _ _ _ _ _ _ _ _ _
318
~ I~t~ll-------------
M114A
DIGITAL SOUND GENERATOR
• MAX EXTERNAL ADDRESSING MEMORY
OF 256K
• 16 INDEPENDENT CHANNELS
• 12 BIT EOUIVALENT D/A CONVERTER
RESOLUTION (DELTA CODING)
• SOUND GENERATED BY READING
TABLES CODED IN DELTA CODING OR
IN ABSOLUTE VALUES, SITUATED IN
AN EXTERNAL MEMORY
• 8 DIFFERENT TABLE LENGHTS AND 8
READING MODES GIVING A TOTAL OF
58 DISTINCT COMBINATIONS
DIP-48 Plastic
ORDERING NUMBER: M114A-Bl
•
16 DIFFERENT MIXABLE LAYERS BETWEEN TWO SEPARATE TABLES
• MULTIPLE READING PERMITS INTERPOLATION BETWEEN TWO ADJOINING
SAMPLES ON THE SAME TABLE
• 4 SELECTABLE ANALOG OUTPUTS
• 10 BIT INTERNAL ATTENUATOR WITH
GRADUAL AMPLITUDE VARIATION
• ROM ENABLE OUTPUT TO MINIMISE
EXTERNAL MEMORY POWER CONSUMPTION
• POSSIBILITY OF SYNCHRONOUS AND
ASYNCH RONOUS FREOUENCY-TABLE
CHANGE AT THE END OF THE READING TABLE
CONNECTION DIAGRAM
GND(digilal)
1
48
EA 1
2
47
EA 0
ROM ADDR 0
3
46
BUS STROBE
1[ 4
45
BUS 0
[ 5
44
I
[ 6
43~
I
[ 7
ROM ADDR 5
8
EA 3
9
EA 2
With this device it is possible to synthesize a
large range of sound by. simply transcribing the
most significant periods of the sound to be reproduced into an external memory and programming a suitable reading sequence for these
periods with the use of a microprocessor.
The M114A is realized on a single monolithic
silicon chip using low threshold N-channel
silicon gate MOS technology and is assembled in
plastic DIP.48.
June 1988
P
41P
I 3
1
40~
4
BUS 5
P
[ 10
39
ROM ADDR 6 [ 11
38
I 6
7 [ 12
37
1 5
8 [ 13
36
1
4
[ 14
35
10 [ 15
34
11 [ 16
33
1
1
ROM ADDR 12 [ 17
32
The M114A is a 16 channels digital polyphonic,
politimbric sound generator.
The M 114A must be driven by a microprocessor
and needs an external memory.
42
TESTING
ROM DATA 7
ROM DATA e
18
31
ROM ENABLE
CLOCK
[ 19
30
ANALOGOUT3
ANALOG OUT2
VoD(digilal)
RESET
20
29
GND(analog )
21
28
ANALOGOUTI
VDD(analog)
22
27
COMMON NODE
VREF
TABI/TAB2
23
26
ANALOG OUT 0
24
25
.,2V OUT
S 9618/1
1/13
319
M114A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Voo
VI
Vo
Unit
Value
Supply voltage
-0.3 to 7
Input voltage
-0.3 to Voo
Output voltage
-0.3 to Voo
V
V
V
800
mW
-65 to 150
°c
°c
Ptot
Total package power dissipation
Tstg
Storage temperature
Top
Operating temperature
o to
70
Stresses above those listed under "Absolute Maximum Ratings" mav cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Fig. 1 - Block Diagram
DATA
STROBE
DATA
8IJS
FORCED WM.E
TERMINATION
EAo-------~~~---+~~
TA811TAB2
RCI4
ADDRESS
L _ _ _li---c
::BLE
~;;~~~----------~-<~A
~E:~-----4~---------t--------,
......--"--.
Ll____....J.____________---'l-______--IL-______..()+12VOUT
ANALOG
OUTPUTS
~2/~1~3______________________ ~~~~~~~n
320
_______________________
M114A
Fig. 2 - System Configuration
,
~El
CHANNEl
2
CHANNEL
3
,======~~DATA
,
CHANNEL
L-----------------------~ST
I
5-9680/1
STATIC ELECTRICAL CHARACTERISTICS
(V oo
5V ± 5"10, V ss
Voo DIG = Voo Analog)
Value
Symbol
Parameter
Test Conditions
Min.
[
Typ.
I
Unit
Max.
INPUTS: RESET (pin 20), CLOCK (pin 19), ROM DATA (pins 32-39), DATA BUS (pins 40-45),.
DATA ST (pin 46)
V ,L
Low Input Level
V,H
High Input Level
I,
Input Leakage Current
V
0.8
V
2.2
± 1
V, = Voo to Vss
/lA
QIGITAL OUTPUTS(HIGH IMPEDANCe with 10 Kn pull-up): ROM-ADD(pins 3-8; 11-17),EA(pins
2,9, 10,47), ROM EN. (pin 31)
Low Output Level
10L = 1 mA
High Output Level
10H - 100 /lA
ANALOG OUTPUTS: (pins 26, 28,29, 30), V REF (pin 23)
VREF
'
0
Voltage Reference Output
10= ± 1 mA
2.5
Output Current
Zero attenuation
±1
(cu rrent generator)
Max input code to the DAC
V
mA'
POWER DISSIPATION
[ 100
* High
[ Supply Current
Voo = 5.25V
120
mA
impedance means that, when the addresses are off, the digital output is connected with an internal resistive
pull~p.
__________________________
~!~~~~~:
______________________
~3/~13
321
M114A
DYNAMIC ELECTRICAL CHARACTERISTICS
Parameter
tCK
Input Clock Frequency
t r , tf
Rise and Fall Time
tWH,tWl.
High and Low Pulse Width
Test Conditions
4.000
10% to 90%
KHz
20
ns
80
ns
750
ns
RESET
~4
Pulse Width
Clock
Fall Time
10% to 90%
MHz
DATA BUS
tw
Pulse Width
tset-up
Set-up Time to DATA Strobe
0
ns
thold
Hold time from DATA Strobe
750
ns
DATA STROBE
tw
Pulse width
1.5
tWR
Pulse Width for Internal Reset generation
128
tf, tr
Pulse and Fall Times
128
,",S
,",s
100
ns
ROM ENABLE
tl.OW
600
ns
tHIGH
350
ns
tset-up(*)
Set-up Time ROM-EN
70
ns
(*) tset-up time means that the data coming from ext. ROM must be stable at least 70 nsec before the rising edge of
ROM-EN.
PIN FUNCTIONS
Pin 1 - GND (digital)
Digital ground is linked to this pin.
Pin 21 - GND (analog)
Analog ground is linked to this pin.
Pin 3-8 and 11-17 - ROM-ADD
13 PUSH PULL type output pins for external
memory address. When the output is off (doesn't
exist an address) the output is connected to a
internal resistive pull-up of about 10Kn.
Pins 2. 9.10.47 - EA
These four pins give in output the channel number that is reading the external memory.
When the output is off (doesn't exist an address)
the output is connected to a internal pull-up.
With these 4 pins the memory is expanded up to
128 Kbyte (8 Kbyte/channel).
Pin 24 - TAB1/TAB2
It shows which one of the two tables (TAB1 or
TAB2) is read.
Pin 24 permits to double the memory so reading
256 Kbyte addressing memory (top configuration).
Pin 19 - CLOCK (4 MHz)
For correct functioning the generator must be
external to the chip and the duty cycle must be
very close to 50%.
Pin 20 - RESET
All channel are reset by reading this pin and the
13 external 'ROM address outputs toghether with
the 4 sound outputs are placed in a high impedence state.
Pin 22 - Analog power supply
The power supply for all analog parts. i.e. DAC
attenuator. etc ..... are linked to this pin. It is
therefore important that this power supply
should be very stable and well smoothed.
The internal power supply chip separation allows
a great improvement of Signal/noise ratio.
~4/~1~3_______________________ ~!~~~~&'~~
322
__________________________
M114A
PIN FUNCTIONS (continued)
Pin 23 - Voltage reference (V REF)
VREF is the average value of the DAC output.
With VSUPPly = 5V, VREF is nominally 2.5 but
could vary by chip to chip (-10mV).
It's only necessary to filter the VREF output
with an external capacitor of some tens of fJF
(Fig. 3a). To get a voltage suitable to act as VREF
towards external integrator which reconstruct the
output signal. Since such a voltage is quite the
same than DAC output for a null input code, it
automatically conforms itself, following possible
differencies between various device instances.
It is possible to modify slightly, from the external environment, the obtained VREF value with
suitable resistive networks so that the operational
integrator offset can be compensated. (Fig. 3b)
To improve the VREF it's possible to use a filter
as in Fig. 3c.
Fig. 3
An integrator together with a low pass filter are
necessary if the tables have been DELTA coded.
If on the other hand they have been coded in absolute values then only a low pass filter is needed.
If the channels do not have to be separated for
stereofonic effects or otherwise, a single output
may be used routing, by fJP programming, all
channels to this pin.
Pin 31 - ROM ENABLE (Low active)
This is a PUSH-PULL-TYPE-OUTPUT and is
used to set the external memory is stand-by so
as to reduce consumption whenever is not read.
Pin 32-39 - ROM-DATA
S input pins for data from external memory.
Pin 40-45 - DATA-BUS
6 input pins for data from the microprocessor.
S of these data groups make up a complete piece
of information.
Pin 46 - BUS-STROBE
A signal from the microprocessor must arrive at
this input in order to memorize the present code
onto the DATA-BUS
Memorization occurs on both edges.
Pin 27 - COMMON NODE
This pin permit the access to the common point
placed before the four output switches.
Pin 18 - Digital Power Supply
The power supply for all digital parts, i.e. coun·
ters, memories, etc ..... , are linked to this pin.
ANALOG
OUT
M114A
vREFI--~-o-i
5-1674
b)
ANALOG
OUT
M114A
Pin 48 - Testing
This pin is utilized only for testing and must
be left unconnected by the user.
Pin 25 (+ 12V out)
This pin is the output of an internal 5V /14V DC-DC converter and it needs an external
filtering capacitance (min 100 nF). The performances of DAC and attenuator are very improved
with an external zener that clamps the voltage
elevator output (see Fig. 4).
VREF I--....-C::l--......__ ~~~LOG
5-9673
a)
ANALOG
OUT
b)
Pin 20 (+12V out)
This pin is the output of an internal voltage
elevator and it needs of an external filtering
capacitance (min. 100 nF).
The performance of DAC and attenuator are
very improved with an external zener that clamps
the voltage elevator output (see Fig. 4).
Pins 25 - ROM-ENABLE (Low active)
This is a PUSH-PULL type output and is used
to set the external memory in stand-by so as
to reduce consumption whenever it is not read.
It is possible to double the addressable memory
size (16 Kbyte by connecting this pin to the MSB
address line of the external memory trough
an F/F.
Pins 26 & 33 - ROM-DATA
8 input pins for data from external memory.
ANALOG
Pins 2 & 14 - ROM-ADDRESS
13 PUSH-PULL type output pins for external
memory address.
OUT
c)
Pin 18 - Analog Power Supply
The power supply for all analog parts, i.e. DAC,
attenuator, etc .... , are linked to this pin.
It is therefore important that this power supply
should be very stable and well smoothed.
The internal power supply chip separation
allows a great improvement of signal/noise ratio.
Pin 15 - Digital Power Supply
The power supply for all digital parts, i.e. coun·
ters, memories, etc .... , are linked to this pin.
Pin 17 - RESET
All channels are reset by raising this pin and the
13 external ROM address outputs together with
the 4 sound outputs are placed in a high im·
pedance state.
--------------
Pins 34-39 - DATA-BUS
6 input pins for data from the microprocessor.
8 of these data groups make up a complete piece
of information.
Pin 40 - DATA-BUS Strobe
A signal from the microprocessor must arrive at
this input in order to memorise the present code
onto the DATA-BUS.
Memorization occurs on both edges.
Fig. 4
----------,
Ml14S
I
, .12VOUT
-SOKll
,
14V
~ ~~~;m?,r:;_=
5~I
l (minT
'100nF
I
-.J
S- 9676
____________
.:..:5/~14
337
M114S
GENERAL DESCRIPTION
The Ml14S is a device that allows digital sound
synthesis.
The essential system needed consists of a microprocessor, an Ml14S and an external memory
with a maximum of 8192 bytes.
Sound generation is based on cyclic reading of
a table corresponding to a waveform of the
timbre to be reproduced.
As the waveform and therefore also the spectrum
frequently change, a series of tables of form and
frequency appropriate to the sound are cyclically
scanned during sound reproduction.
The effect caused by the sudden passage from
one table to the next would be unpleasant unless
there is such a large number of tables to allow
. a smooth unnoticeable change from one table to
the following. A favourable compromise between number of
tables and quality of sound, that has been implemented in the M114S is the following: A
limited number of tables which may even diverge
from one another are chosen during an initial
phase of analysis after which, during the reproduction phase, two adjoining tables are read
simultaneously by extracting a percentage of
one and the remaining percentage of the other.
Therefore by starting with 100% of one and zero
of the other and successively increasing the
second while decreasing the first, so that the sum
of the percentages is always equal to 100, there
will come a point at which there is a 100% of the
second and zero of the first thus having achieved
a smooth passage from one table to the next. In
the M114S this passage is made up of a maximum
of 16 steps.
The tables are stored in an external memory and
may be of eight different lengths ranging from
16 to 2048 bytes. The M114S can handle up to
a maximum of 16Kbytes (see fig. 8).
The tables may be coded using waveform's
absolute value or by the dif.ference between
adjoining samples, that is, in a incremental
manner (Delta coding).
With the use of an integrator at the output
in the second case, the waveforms are coded
thus allowing easy interpolation. By simply
reading the same data n time and dividing the
amplitude of each reading by n, a ramp of n small
steps is obtained instead of a large single step.
The value of n may be 1,2 or 4.
When a waveform is coded in this way (DeltaCoding or incrementally), one must check that
the sum of the samples in an entire period is
always equal to zero or there would be a continuity which could even saturate the external
integrator.
Always the M114S completes the reading of a
table before the starting of another. This too
avoids saturation of the external integrator.
Whenever it is necessary to suddenly move from
one table to another before the read cycle has
been completed the FTT forced table termination code must be forwarded to the 8 frequency
bits.
It is possible to drive the Ml14S in such a way
that the programmed frequency becomes active
immediately, without waiting for the running
table to end (asynchronous mode); or that this
change of frequency occurs only at the end of
the running table (synchrounous-mode).
ASYNCHRONOUS MODE (SET UP AT RESET)
The frequency-information in a command causes
the immediate change of the frequency, while the
table and all the other parameters are changed
only when the running table has been completely
scanned.
This type of operation is useful for producing
vibrato effects on long tables or vibrato effects
on low frequency sounds.
In fact in these cases it is useful to be able to
vary continuously the scanning frequency of the
same table, without being bound to execute the
variation of frequency at the end of the table.
The typical resolution in Delta coding is 12 bit
with a sinusoidal wave coded in a 16-byte table.
SYNCH RONOUS MODE
A low pass filter at the output is sufficient in
the first case to reconstruct the original signal,
but very long tables would be necessary for low
frequency sounds causing a waste of memory.
The frequency-information in a command causes
the synchronous change of table and frequency;
this is obtained by delaying the frequency change
until the running table has been completely
scanned.
338
M114S
GENERAL DESCRIPTION (continued)
This command is very useful in some special
effects (glide) because it avoids the reading of the
table in part with the old frequency and in part
with the new one, thus causing an audible click.
This way-to-operate is useful in the reproduction of deep vibrato on notes placed at the octave
boundary, for glide effects and in any case when
it is necessary to go beyond the octave boundary
without discontinuity.
In fact in these causes it is necessary to schedule
in the M114S a length of table and a table frequency scanning completely different from the
previous programming.
To avoid clicks it is indispensable to finish the
old table with the old frequency before starting
the new one with new frequency.
The feature is obtained by acting in global
synchronous mode.
The commands for synchronization are:
SSG Set Global Sync. (FB Hex Code). Activates the global synchronous mode i.e.
sinchronize, also the frequency change
with the table end.
RSG Reset Sync. Global (F9 Hex Code). This
command disables global synchronous
mode.
RSS
Reverse Sync. Status (FA Hex Code).
This command inverts the synchronism
state only for the next programming
sequence.
Everyone of these three commands is accomplished by sending a complete programming
sequence with F9/FA/FB frequency codes,
respectively.
They affect the whole working mode of the
device (all its channels!.
All the remaining bits are ignored.
Note that the RSS command can be obtained by
sending eight times the 6-bit data 111110.
As shown in Tab. 3, there are six bit among
the control bits that are dedicated to the choice
of table pair length and n number of repeated
readings of each table.
The frequency of sample readings is synchronous.
This means that the frequency is a whole multiple of the table length.
In this way any problem caused by intermodula
tion is eliminated but a noise due to "collision"
is produced. As there is a single output circuit
for all channels, that is interpolator, O/A converter, attenuator, ecc., each time more than one
channel requires access to this circuit one or
more other channels must wait.
The amount of time necessary for the output
circuit to process each table, that is the period of
time for which each channel uses the circuit
during each sample reading cycle, is of 2/lS.
The delay will therefore be proportional to the
number of channels operating simultaneously
and to the frequency that they are generating.
As these parameters casually vary, so will the
delay thus producing a casual alteration of the
original waveform.
Simulation has proved that under worst possible
conditions the signal/noise ratio due to this
problem is around 60dB.
In conclusion let us mention the envelope that
has to be controlled by the microprocessor
which, at suitable intervals, must forward the
desired attenuation coefficient.
There are 64 possible attenuations each with
steps of approximately O.75dB;
These passage from one level to another may be
immediate or to gradual increments of 1/256
of the maximum amplitude at a frequency
proportional to external table reading frequency.
OPERATION
The M114S receives from the JlP a single programming sequence at a time. This programming
sequence is made up of 48 bits.
The JlP must send a 48 bit set for every Ml14S
active channel.
Each M114S channel continuously generates the
same signal, that is it reads the same table, with
the same mixing coefficient, with the same amplitude, ecc., until the microprocessor forwards a
different programming sequence (variation of
one or more parameters characterising the sound
to be generated within a single channel.
Timbre amplitude evolution and any other slight
frequency changes must be handled in real-time
by the microprocessor.
Often the microprocessor is unable to update
the amplitude with sufficient speed. For this
reason the M114S carries out a gradual change
from one amplitude to another at steps of
1/256 of maximum sample frequency am'
plitude if the change in level is greater than 128
steps, of 1/2 of this frequency if greater than 64,
of 1/4 if greater than 32 and of 1/8 if smaller
than or equal to 32 steps.
Each channel reads two samples at the sample
frequency by taking one from each table, sums
them according to the mixing coefficient and
forwards the result to the OAC whose suitably
attenuated output goes to the previously selected
output pin (Fig. 5).
339
M114S
GENERAL DESCBIPTION (c.ontinued)
This operation requires 2p.s and as there is a
single output circuit for all channels it is certain
that one or more channels will simultaneously
request the use of the circu it. Thus a priority
order has been assigned to each channel. This
order is fixed, channel zero being that of greatest
priority followed in order by the others.
Fig. 5
then CH2:
CH 1
CH 2
OUT
l~ ~ ~i ~
[},
--1 U U U l..fLJ I L-J I L
5-&833
a low pass filter if the table have been coded
using absolute values.
an integrator if in delta coding
ANALOG
OUT 0
ANALOG
OUT 1
~ ~
The signal will change from impulsive to con·
tinuous by passing through:
PAM CURRENT
PULSES
TO INTEGRATOR
M114S
n
n ~
L-f1.---J L-J L-
~
Fig. 6
OR FILTER STAGES
ANALOG
OUT 2
PROGRAMMING
48 bits subdivided into 8 groups of 6 bits each
must be forwarded in order to programme a
channel.
A group of 6 bits is memorised on every Data
Strobe switch front. As the data bus is read ap·
proximately 250ns after transition from the
Data Strobe, the 6 data bits may simultaneously
arrive with the Delta Strobe switch.
ANALOG
OUT 3
s~e'4"1
When more than one channel is simultaneously
active at the output pin there will be an overlap
of impulse sequence of each channel.
The example of Fig. 6 shows an output signal
with 2 active channels, CHl has greater priority
DATA PROGRAMMING ORDER
~
BYTE
34
, st
A5
2 nd
1
5
A4
A3
I
37
39
Al
AO
ATTENUATION
A2
TABLE 1 ADDRESS
TABLE 2 ADDRESS
6
7
0
I
4
3
2
I
4
3
2
TABLE LENGTH
L2
7
6
1
0
I
Ll
I
I
1
Ml
MO
OCTAVE
DIVISOR
0
0
0
FREQUENCY
1
2
0
IMMEDIATE
CONNECTION
CHANNEL NUMBER
3
I
1
M2
LO
2
I
READING METHOD
INTERPOLATION
3
7th
0
1
0
FREQUENCY
7
I
6
I
5
I
~8/.c:;1_4_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~tm~I~~~
340
38
TABLE 1 ADDRESS
6
8 th
36
TABLE 2 ADDRESS
4th
6th
I
35
4 OUTPUTS
3,d
5 th
I
4
I
3
I
2
-------------
M114S
GENERAL DESCRIPTION (continued)
The graph of fig. 7shows the time lapse that
must be assigned to these signal for correct
functioning.
No more than 128/.1s must pass between one
Data Strobe transition and the next during
transmission of the 8 groups of data or else
synchronisation is lost due to the internal auto-
matic reset generated after 128/.1s from the last
Data Strobe transition, causing the data to be
misinterpreted.
One should wait for at least g/.ls after the forcedzero-cross command has been given between
the last group of data of one instruction and
the first group of the next.
Fig.7
DATA
STROBE
~o
0!:750ns
';!:l,.us
i!: l,us
<12!3ps
The degree of priority of the channel and the
number of channels in use at that moment must
be taken into account in order to shorten this
wait, If there is maximum priority the wait will
be a minimum wait of approximately 2/.1s. The
same holds if the priority is not maximum but
there are no other channels in use. There will
however be a maximum wait of 2/.1s for each
active channel with greater priority than the
channel in question.
If another instruction were to be transmitted
without a sufficient wait, there would be the risk
of losing the previous instruction of forced table.
termination.
The wait is unnecessary after normal commands.
Every data group must be remain present for at
least l/.1s after Data Strobe transition.
The 48 bit functions are the following:
A) 8 address bits for the 1st table (ext. ROM)
B) 8 address bits for the 2 nd table (ext ROM)
C) 8 frequency bits (4-note and 4-twelfths of
note and ± 1 or 2/1000)
D) 6 attenuation or amplitude address bits
E) 4 interpolation bits
F) 4 channel address bits
G) 6 reading mode and table length bits (ext.
ROM)
H) 2 bits for choice between four outputs
J) 1 bit for a frequency octave change
J) 1 bit for gradual disable of envelope
While waiting for the present 1st table reading
to terminate, the above data (not immediately
--------------------------
;i!:.l,.tJS
<128ps
~l.us
NO MAX LIMIT
$-8146/1
operational) is memorized into the internal
RAM1).
The new data is transfered to RAM2 and becomes operational when the addressed channel
ends the current table scanning.
An exception is made by the 8 frequency bits
and the one varying the frequency octave as they
operate immediately (See synchronization).
All data may be made operational by giving
the forced-table-termination command.
48 PROGRAMMING BIT FOR CHANNEL
SELECTION
8 Address Bits 1st Table (ext. ROM)
These determine the most significant part of the
13 external memory address bits but according
to the table length chosen by the 6 mode bits,
some of the least significant of these 8 bits are
suitably substituted by the M114S.
In the case of a maximum table length, 2048
bytes, there will only be 2 significant bits to
address the table while the remaining 11 will
address each single table word.
By already knowing the table length, the programmer will be able to programme the most
significant bits needed for table address only and
ignore the others.
As the maximum memory that can be handled is
of 8 Kbytes, if the table has a length of 1 Kbyte
it is sufficient to program the 3 MSB bits and
ignore the other five.
~!~I;~?~~~
______________________
~9/~14
341
M114S
48 PROGRAMMING BIT FOR CHANNEL
SELECTION (continued)
8 Address Bits 2 nd Table (ext. ROM))
As above but refering to the second table.
One must consider that the forced table termination refers to the first table and that during
table mixing the second table may assume a
percentage value of zero while the first table can
only assume a minimum percentage value of 1/16
of the maximum value.
8 Frequency Bits
The 4 most significant bits characterize one of the
15 available notes with HEX. Codes from 0 to E_
Eleven movements in twelfths of a semitone may
be obtained with the remaining 4 bits as well
as ~o~r ± 1/1000 and ± 2/1000 note frequency
variatIons.
These permit the production of: Vibrato,
Glissando, chorus effect etc .....
The FF codes correspond to the forced-tabletermination command while FC maintains the
previous frequency. F9, FA, FB are synchronisation commands. The F8 code = ROMIO is a
ROM identification command.
It just sets the programmable counters of the
M114S to a very short counting modulo (8 + 0)
useless for musical purposes.
The remaining codes are used for testing and
therefore must not be used by the operator.
Table 1 shows the 240 frequencies obtainable
by setting the external clock to 4MHz and the
table length to 16 bytes, with single reading
and without inserting an octave divisor. These
are the highest octave frequencies obtainable
with the M114S.
In practice double, quadruple, etc ... frequencies may be obtained by writing 2, 4, etc. complete waveform periods in the table.
6 Attenuation Bits
These are the addresses for the internal attenuation table.
The contents of this table follow a logarithmic
pattern so as to produce a decrease of 0.75dB
for each address unit increment. See table 2.
The word length is of 10 bits.
After processing by a suitable circuit in order
to obtain a gradual amplitude variation the ten
outputs of this table are linked to .the 10 bit
attenuator.
The gradual movement from the present level to
that just programmed takes place by increasing
or decreasing the 8 most significant bits of the
attenuation table contents, with the same frequency with which the external memory tables
are being scanned if the difference in level is
greater than 128 steps, or with 1/2 of this frequency if greater than 64 steps or 1/4 if greater
than 32, or 1/8 if smaller than or equal to 32.
In conclusion, the output signal amplitude
increases of decreases at each variation by
1/256 of the maximum value.
By setting the bit that deals with the gradual
envelope there is an immediate passage from
=-10:.:,1=-14'--_ _ _ _ _ _ _ _ _ _ _
342
the present level to that programmed.
4 Interpolation Bits
These define the mixing coefficient between
the two waveform tables.
It is possible in this way to sum the 1st waveform
percentage with the remaining 2 nd waveform
percentage thus obtaining a third signal which
will be forward to the output.
In greater detail, the operation carried out is
the following:
0= (01 * (K + 1)/16) + (02 * (15 - K)/16)
where:
o is the data at the input of the OAC (8 bits
in complement with 2)
01 is the data read from the 1st table (8 bits
in complement with 2)
02 is the data read from the 2 nd table (8 bits
in complement with 2)
K is a 4 bit interpolation coefficient (from
o to 15)
Obviously only the first waveform will be output
if K = 15.
4 Channel Address Bits
These indicate to which of the 16 M114S channel the remaining 44 bits will be forwarded.
6 Mode Bits
These indicate the table couple reading mode
(ext. ROM).
For each table there are 58 distinct combinations
that include, both table lengths and the number
of repeated readings from the same address.
(ext ROM). See table n. 3.
The three most significant bits characterize the
table lengths while the other three characterise
the length ratio between tables and the number
of repeated readings.
2 Output Address Bits
These indicate to which of the 4 output pins the
corresponding channel signal must be forwarded.
This is necessary in order to obtain stereophonic
effect or to separate channels used for accompanyment from those of "SOLO", etc ...
1 Octave Divisor Bit
This is used to pass from one octave to another
without changing the table length. If octave
divisor bit is set to 1 the programming frequency
is divided by two.
1 Instant ENVELOPE Change Bit
This orders instant passage from the present amplitude to that programmed.
~ !~~mg'~~~A:
-------------
M114S
TABLE 1 NOTE
C
C#
D
D#
E
F
F#
G
G#
A
A#
FREQUENCIES
DEVIATION
·6/12
-5/12
-4/12
-3/12
-2/12
-1/12
-2/1000
-1/1000
(Hexf
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
A
1016.78
1077.01
1140.90
1209.19
1281.23
1356.85
1437.81
1523.23
1614.21
1709.40
1811.59
1919.39
2032.52
2155.17
2283.11
For
Testing
1021.45
1082.25
1146.79
1215.07
1287.00
1363.33
1445.09
1530:22
1622.06
1718.21
1819.84
1928.64
2042.90
2164.50
2293.58
For
Testing
1026.69
1087.55
1152.07
1221.00
1293.66
1369.86
1451.38
1538.46
1629.99
1727.12
1829.83
1937.98
2053.39
2176.28
2304.15
For
Testing
1031.46
1092.90
1158.08
1226.99
1299.55
1376.46
1458.79
1545.60
1638.00
1734.61
1838.24
1947.42
2063.98
2185.79
2314.81
For
Testing
1036.27
1098.30
1163.47
1232.29
1305.48
1383.13
1466.28
1552.80
1644.74
1743.68
1846.72
1956.95
2072.54
2195.39
2325.58
For
Testing
1041.67
1103.14
1168.91
1238.39
1312.34
1389.85
1472.75
1560.06
1652.89
1751.31
1855.29
1966.57
2083.33
2207.51
2339.18
For
Testing
1044.39
1106.81
1172.33
1242.24
1315.79
1393.73
1478.20
1564.95
1658.37
1757.47
1860.47
1972.39
2087.68
2212.39
2344.67
For
Testing
1045.48
1107.42
1173.71
1243.78
1317.52
1395.67
1479.29
1566.17
1659.75
1759.01
1862.20
1974.33
2089.86
2214.84
2347.42
For
Testing
B
B
2C
2C#
2D
C
D
E
F
NOTE
DEVIATION
0
+1/1000
+2/1000
+1/12
+2/12
+3/12
+4/12
+5/12
(Hex)
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
1046.57
1108.65
1174.40
1244.56
1318.39
1396.65
1480.38
1567.40
1661.13
1760.56
1863.93
1976.28
2092.05
2217.29
2350.18
1047.67
1109.88
1175.78
1245.33
1319.26
1397.62
1481.48
1568.63
1662.51
1762.11
1865.67
1978.24
2094.24
2219.76
2352.94
1048.77
1111.11
1177.16
1246.88
1321.00
1398.60
1482.58
1569.86
1663.89
1763.89
1867.41
1980.20
2096.44
2222.22
2355.71
1051.52
1114.21
1180.64
1250.78
1324.50
1403.51
1486.99
1576.04
1669.45
1768.35
1874.41
1984.13
2103.05
2227.17
2361.28
1061.57
1124.86
1191.90
1262.63
1337.79
1417.43
1501.50
1591.09
1684.92
1785.71
1892.15
2004.01
2123.14
2249.72
2383.79
1066.67
1130.58
1197.60
1269.04
1344.09
1424.50
1508.30
1598.72
1693.48
1793.72
1901.14
2014.10
2134.47
2259.89
2395.21
ROMIO
SSG
RSS
RSG
1056.52
1119.19
1186.24
1256.28
1331.56
1410.44
1494.77
1583.53
1677.85
1777.78
1883.24
1994.02
2114.16
2239.64
2372.48
PreViously
Selected
Frequency
For
Testing
For
Testing
1071.81
1135.72
1203.37
1274.70
1350.44
1430.62
1516.30
1606.43
1702.13
1803.43
1910.22
2024.29
2143.62
2272.73
2406.74
Forced
Table
Terminat.
C
C#
D
D#
E
F
F#
G
G#
A
A#
B
B
2C
2C#
20
C
0
E
F
--------------
~ ~~~~mg'~©~
___________
--=1~1/:...:1~4
343
M114S
TABLE 2 - ATTENUATION
N = six bit attenuation code decimal value (0 : 63)
V = internally decoded linear ten bit value (0 : 1023)
A = theoretical attenuation value in decibels = 20. Log ((V + 1)/1024)
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
A
N
V
A
1023
939
863
791
727
667
611
559
515
471
431
395
363
335
307
283
259
235
215
199
183
166
152
140
128
117
107
98
90
83
76
69
0.00
0.74
1.48
2.23
2.96
3.71
4.47
5.24
5.95
6.73
7.50
8.25
8.98
9.68
10.43
11.14
11.91
12.75
13.52
14.19
14.91
15.75
16.51
17.22
17.99
18.77
19.54
20.29
21.03
21.72
22.48
23.30
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
58
53
49
45
41
37
34
31
28
26
24
22
20
18
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
23.95
24.79
25.56
26.23
26.95
27.74
28.61
29.32
30.10
30.96
31.58
32.25
32.97
33.76
34.63
35.60
36.68
37.28
37.93
38.62
39.38
40.21
41.12
42.14
43.30
44.64
46.23
48.16
50.66
54.19
60.21
60.21
_12~/_14_______________________ ~~il@~~'~~
344
+ STOP
__________________________
M114S
TABLE 3 - READING MODES
LENGTH
MODE
READ N.
LENGTH
MODE
READ N.
M
L
Tl
T2
Tl
T2
M
L
Tl
T2
Tl
T2
000
000
000
000
000
000
000
000
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
16
32
64
128
256
512
1024
1048
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
100
100
100
100
100
100
100
100
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
8
16
32
64
128
256
512
1024
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
001
001
001
001
001
001
001
001
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
16
32
64
128
256
512
1024
2048
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
101
101
101
101
101
101
101
101
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
16$
16$
16
32
64
128
256
512
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010
010
010
010
010
010
010
010
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
1024"
16
32
64
128
256
512
1024
1024
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
110
110
110
110
110
110
110
110
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
4
8
16
32
64
128
256
512
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
011
011
011
011
011
011
011
011
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
16$
16
32
64
128
256
512
1024
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
111
111
111
111
111
111
111
111
000
001
010
011
100
101
110
111
16
32
64
128
256
512
1024
2048
16$
16$
16$
16
32
64
128
256
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
i
* Repetitions
$ Exceptions
___________________________
~~~~~~?~~:~~~
______________________
~1~3/~14
345
M114S
Fig. 8 - The Ml14S can handle up to 16Kbyte of memory with this application circuit.
ROM
M114S
. ROM
EN
16Kbyte
25
L
OE
CE
A13
.....
....
10nF
+5V
I
-c:J-4.7K
S
CK
r-c:J
Q I--
DF/F
G
R
0
TA B1/TAB2
SIGNAL
-
88HJJ4S 07
=:;14::!.,/1::..:4'--_ _ _ _ _ _ _ _ _ _ ~ 1~I@m?~~lf
346
------------
M3004
M3005
REMOTE CONTROL TRANSMITTERS
•
FLASHED OR MODULATED TRANSMISSIONS (M3004 = fOSC/12' M3005 = fosc)
• 7 SUB-SYSTEM ADDRESSES
• UP TO 64 COMMANDS PER SUB-SYSTEM
ADDRESS
•
HIGH-CURRENT REMOTE OUTPUT AT
V DO = 6V (lOH = -40mA)
•
LOW NUMBER OF ADDITIONAL COMPONENTS
•
KEY RELEASE DETECTION BY TOGGLE
BITS
•
"LOCK-UP" PROTECTION TO PREVENT
BATTERY DISCHARGE
•
VERY LOW STAND-BY CURRENT «2~A)
•
OPERATIONAL CURRENT
SUPPLY
< 2mA AT 6V
~
,~~u~
,
B
DIP-20 Plastic
(0.4)
M
SO-20L
ORDERING NUMBERS: M3004 B1
M3005 B1
M3004M1
M3005 M1
• WIDE SUPPLY VOLTAGE RANGE (4 TO
10.5V)
•
CERAMIC RESONATOR CONTROLLED
FREQUENCY (400 TO 600KHz)
•
CMOS SI-GATE TECHNOLOGY
PIN CONNECTION
• PACKAGES: 20-LEAD PLASTIC DI L OR
20·LEAD PLASTIC SMALL OUTLINE (SO-20)
DESCRIPTION
The M3004/M3005 transmitter ICs are designed
for infrared remote control systems. They have
a total of 448 commands which are divided into
7 sub-system groups with 64 commands each.
The sub-system code may be selected by a press
button, a slider switch or hard wired.
The M3004/M3005 generate the pattern for
driving the output stage. These patterns are pulse
distance coded, The pulses are infrared flashes
or modulated.
Modulated pulses allow receivers with narrowband preamplifier for improved noise rejection to be used. In the M3004 the modulation
frequency is f0SC/12 about 38KHz with (f osc =
455KHz) while In the M3005 the modulation
frequency corresponds to f osc . In flash mode the
M3004 and M3005 are identical. Flashed pulses require a wideband preamplifier within the receiver.
June 1988
1/10
347
M3004-M3005
PIN NAMES
1
2
3
4
5
6
7
8
9
10
REMO
SEN6N
SEN5N
SEN4N
SEN3N
SEN2N
SEN1N
SENON
ADRM
Vss
Remote data output
Key matrix sense inputs
Address mode control inputs
Ground
11
12
13
14
15
16
17
18
19
20
OSCI
OSCO
DRVON
DRV1N
DRV2N
DRV3N
DRV4N
DRV5N
DRV6N
V DD
Oscillator input
Oscillator output
Key matrix drive outputs
Positive supply
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply voltage range
-0.3 to + 12
V
VI
Input voltage range
-0.3 to V DD + 0.3
V
Vo
Output voltage range
-0.3 to V DD + 0.3
V
±I
D.C. current into any input or output
max.
10
mA
Peak REMO output current during lOlls; duty
factor = 1%
max.
-300
mA
max.
200
mW
V DD
I REMo
Ptot
Parameter
Power dissipation per package for Tamb
Tstg
Storage temperature range
Tamb
Operating ambient temperature range
= 0 to 70° C
-55 to 150
°c
o to 70
°c
Stresses above those listed under" Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these Or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating -conditions for extended
periods may affect device reliability.
2/10
~ SGS.11I0MSON
=:..:~------------~O(c;Ill@I<~I<(c;1i'Ill@I>lIO(C;$ - - - - - - - - - - - - - - -
....,l.
348
M3004 -M3005
DC CHARACTERISTICS (Vss
Symbol
Voo
Voo
(VI
-
= OV;
Tamb
= 25°C;
unless otherwise specified)
Value
Parameter
Unit
Min.
Typ.
Max.
Supply voltage
Tamb = 0 to +70°C
4
-
10.5
V
-
04
0.8
-
mA
-
-
400
-
-30
-
-
-
100
6
9
Supply current; active
f
= 455KHz'
F\'~MO output unloaded
100
--g-
R
Supply current; inactive
(stand-by model
Tamb = 25°C
fosc
4 to 11
Oscillator frequency
(ceramic resonator I
?
2
IJA
600
KHz
0.2 x Voo
V
KEYBOARD MATRIX
Inputs SENON to SEN6N
V IL
4 to 11
Input voltage LOW
-
V IH
4 to 11
Input voltage HI G H
0.8 x Voo
II
II
4
11
Input current
VI =QV
11
Input leakage current
VI = Voo
:;-n
-
V
-100
-300
,.A
-
1
,.A
--
0.3
0.5
V
-
10
,.A
Outputs DRVON to DRV6N
VOL
4
11
Output voltage "ON"
10=0.1mA
10 = 1.0mA
10
11
Output current "OFF"
Vo=llV
-
CONTROL INPUT ADRM
V IL
VIH
-
Input voltage LOW
-
-
0.2 x Voo
V
Input voltage HIGH
0.8 x Voo
-
-
V
-10
-30
-
,.A
-
-100
-300
100
300
-
Input current (switched P and
N-channel pull-pu/pull-downl
IlL
IIH
11
11
Pull-up active
stand-by voltage: OV
4
11
Pull-down active
stand-by voltage: V DO
10
30
Output vOltale HIGH
-IOH =40m
6
-
-
-
-
-
1
ms
0.8
-
2.7
,.A
-
-
Voo-l
V
1
V
.
,.A
DATA OUTPUT REMO
V OH
VOL
tOH
-g
R
'1l"
6
Output voltage LOW
10L =0.3mA
Pulse length oscillator
stopped
3
Cl?
0.1
V
V
OSCILLATOR
II
VOH
VOL
6
Input current
OSCI at Voo
6
Output vOltar HIGH
-IOL = O.lm
6
Output voltage LOW
IOH=0.1mA
349
M3004 -M3005
Fig. 1 - Transmitter with M3004/M3005
z0 z ~ z ~
;; > '"
>
>
>
0: 0:
0:
0: 0:
0
/7 ~
7,5 f
!l23 f
731 f
lY39 ~
!f'7 if
f f f f !fo
f f !f If f !fa
f / f f f A6
f f f f f ~.
if if if f' if .fa2
~
7
7
f
?
/
iss f if if If f f
163 If f if if f if
1:756
a
SEN1N
7
SEN2N
0
0
0
~
~
0
0
>
>
a: a:
20
VDD
SEN4N
SEN5N
SEN6N
,
l
lOO1 5.25
I nput current = 750 IJ.A
Vo = 3V
Vo = 1V (note 4)
Brightness In. = 0 IJ.A
Brightness In. = 100 IJ.A
Brightness In. = 750 IJ.A
0
2
12
0
2.7
15
Notes: 1. Output matching is calculated as the percent variation from I MAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 mAo
4. The Vo voltage should be regulated by the user. See figures 5 and 6 for allowable Vo versus 10 operation.
FUNCTIONAL DESCRIPTION
Both the M5450 and the M5451 are specifically designed to operate 4 or 5-digit alphanumeric displays
with minimal interface with the display and the data source. Serial data transfer from the data source to
the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are
latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display.
Outputs change only if the serial data bits differ from the previous time.
Display brightness is determined by control of the output current LED displays.
A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations.
A block diagram is shown in figure 1. For the M5450 a DATA ENABLE is used instead of the 35th
output. The DATA ENABLE input is a metal option for the M5450.
359
M5450~M5451
FUNCTIONAL DESCRIPTION (continued)
The output current is typically 20 times greater than the current into pin 19, which is set by an external
variable resistor. There is an internal limiting resistor of 400n nominal value.
Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits
of the shift registers into the latches.
At the low state of the clock a RESET signal is generated which clears all the shift registers for the next
set of data. The shift registers are static master-slave configurations. There is no clear for the master
portion of the first shift register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers will not clear.
When power is first applied to the chip an internal power ON reset signal is generated which resets all
registers and all latches. The START bit and the first clock return the chip to its normal operation.
Bit 1 is the first bit following the start bit and it will appear on pin 18. A logical "1" at the input will
turn on the appropriate LED.
Figure 3 shows the timing relationship between Data, Clock and DATA ENABLE.
A max clock frequency of 0.5 MHz is assumed.
For applications where a lesser number of outputs are used, it is possible to either increase the current
per output or operate the part at higher than 1V V OUT .
The following equation can be used for calculations.
Tj = [(V OUT) (I LED ) (No. of segments) + (V oo ·7 mA)] (124°C/W) + Tamb
where:
T j = junction temperature (150°C max)
VOUT= the voltage at the LED driver outputs
ILEO= the LED current
124°C/W = thermal coefficient of the package
T amb = ambient temperature
The above equation was used to plot figure 4, 5 and 6.
Fig. 2 - Input Data Format
CLOCK
ny'
n I;-Jn.
n n r-~ j-, n n nH n n
Y L...J L...J -_ L...J Y Y Y L...J L-
--I
oJ
I
I
: START:
DATA
-,
BITl 1
I
I
I
:BIT35: BIT361
~.)1$)1$;/'f$$;,7ft;/,M4'1;7_
n
LOAD·
(lNTERNAL)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I
L._ _ _ __
n
RESET
(INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
L._ _ __
5-5827/1
~~~7________________________ ~~~1~~~~
360
--------------------------
M5450 -M5451
Fig.3
CLOCK
DATA
300ns MIN
}
DATA ENABLE
Fig.5
Fig.4
"tot
(W)
r-,-...,...,,---,-,--,-....,-,-'-~
(110)
1-+--+~~1-1!,:'''~'
Fig.6
1--l-++-H-++--t--I--t.c-'-~~-+-1
_llJTamb~85'C
l \i
34SE M
0.5
50
5-578(.
(~~)~~+
I--++-H-t- I :ITj~l50'C(MAX)
'.8
20
lOOns MIN
'j..
3OSEGM.T"'-.
f-t-+--t-H-+++-1---;--+--H-H
Tamb('C)
16
20
24 ILED (mA)
8
12
16
28
32 34 N~Se-gm.
TYPICAL APPLICATIONS
Basic electronically tuned Radio or TV system
LED DISPLAY
M5450
DISPLAY
DRIVER
KEVBOARD
STATION
DETECT. ETC.
-------------- ~ ~~~~m~1Tr::~?©' _____________. . ;5/'-7
361
M5450-M5451
TYPICAL APPLICATIONS (continued)
Duplexing 8 Digits with One M5450
voo
,-, ,-, ,-, ,-, ,-, ,-, ,-, ,-,
O. O. 0
9 16
28 40
32
.,~.O. CJ .,~ .,~.
39
24
31
M5450
CLOCK IN _ - - - - - I
5-IiB01
DATA IN
BRIGHTNESS
CONTROL
POWER DISSIPATION OF THE IC
The power dissipation of the
Ie can be limited using different configurations.
a)
A
10
~6/~7_ _ _ _ _ _ _ _ _ _ _ _ _ _ ~1~~~~~~
362
__________________________
M5450-M5451
In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated
R=
Vc - Vo
N
MAX
-yo
MIN
MAX' 10
The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments.
In this case the current variation in the single resistor is reduced and Ptot limited.
b)
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly
chosen.
The total power dissipation of the IC depends, in a first approximation, only on the number of
segments activated.
c)
In this configuration V OUT + V 0 is constant. The total power dissipation of the IC depends only on
the number of segments activated.
--------------------------~~~I~~~~
________________________7~/7
363
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
M5480
LED DISPLAY DRIVER
• 3 112 DIGIT LED DRIVER (23 SEGMENTS)
• CURRENT GENERATOR OUTPUTS (NO
RESISTORS REQUIRED)
• CONTINUOUS
BRIGHTNESS
CONTROL
• SERIAL DATA INPUT
• NO LOAD SIGNAL REQUIRED
• WIDE
SUPPLY VOLTAGE
technology. It utilizes the M5451 die packaged in
a 28-pin plastic package making it ideal for a
3% digit dispaly. A single pin controls the LED
dispaly brightness by setting a reference current
through a variable resistor connected either to
Vee or to a separate supply of 13.2V maximum.
The M5480 is a pin-to-pin replacement of the
NSMM 5480.
OPERATION
• TTL COMPATIBILITY
Applications examples:
•
MICROPROCESSOR DISPLAYS
•
INDUSTRIAL CONTROL INDICATION
•
RELAY DRIVER
•
INSTRUMENTATION READOUTS
The'M5480 is a monolithic MOS integrated
circuit produced with a N-channel silicon gate
DIP-28 Plastic
ORDERING NUMBER: M5480 B7
ABSOLUTE M.AXIMUM RATINGS
Vee
VI
VO(Off)
10
Ptot
Supply voltage
Input voltage
Off state output voltage
Output sink current
Total package power dissipation
TJ
Top
T stg
Junction temperature
Operating temperature range
Storage temperature range
-0.3 to 15
-0.3 to 15
15
40
at 25°C
at 85°C
150
-25 to 85
-65 to 150
V
V
V
mA
940mW
490mW
°C
°C
°C
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
.periods may affect device reliability.
June 1988
1/6
365
M5480
CONNECTION DIAGRAM
Vss
~
OUTPUT BIT 12
27
OUTPUT BIT 13
OUTPUT BIT II
3
26
OUTPUT BIT 14
OUTPUT BIT 9
25
OUT PUT BIl 15
OUTPUT BIT 16
OUTPUT BIT 10
8
24
OUTPUT BIT 7
23
OUTPUT BIT 17
OUTPUT BIT 6
22
OUTPUT BIT 18
21
OUTPUT BIT 19
OUTPUT BIT
OUTPUT BIT
5
20 OUTPUT BIT 20
OUTPUT BIT 4
OUTPUT BIT 3
10
19
OUTPUT BIT 21
OUTPUT BIT 2
11
18
OUT PUT BI T 22
OUTPUT BIT I
12
17
OUTPUT BIl 23
BRIGHTNESS
CONTROL
13
16
DATA IN
VOO
14
15
CLOCK IN
5-5782
BLOCK DIAGRAM
Fig. 1
OUTPUT BI123
OUTPUT BIT1
BRIGHTNESS
CONTROL
SERIAL
DATA
--1-""':':+--1
CLOC,;.;K+_-=t-;
S-S78J
~2/~6_______________________ ~~~~~~,
366
_________________________
M5480
STATIC ELECTRICAL CHARACTERISTICS (Tamb within operating range, Voo= 4.75V to
13.2V, V55= OV, unless otherwise specified)
Parameter
Test conditions
Supply Voltage
100
Supply Current
Voo= 13.2V
VI
I nput Voltages
Logical '"0" Level
Logical '"1'" Level
± 10llA Input Bias
Brightness I nput Current
(note 2)
Ve
Brightness Input
Voltage (pin 13)
VO(off)
Off State Output Voltage
10
Output Sink Current
(note 3)
Segment OFF
Segment ON
fClock
I nput Clock Frequency
10
Output Matching (note 1)
Notes:
Typ.
Max.
Unit
13.2
V
7
mA
-0.3
2.2
Voo-2
O.B
VOO
VOO
V
V
V
0
0.75
mA
4.3
V
18
V
10
IlA
10
4
25
IlA
mA
rnA
0.5
MHz
± 20
%
4.75
VOO
Ie
Min.
4.75'; Voo'; 5.25
Voo > 5.25
I nput Current = 750 IlA
3
13.2
Vo=3V
Vo = lV (note 4)
Brightness In. = 0 IlA
Brightness In. = 100 IlA
Brightness In. = 750 IlA
0
2
12
0
2.7
15
1. Output matching is calculated as the percent variation from IMAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 mAo
4. The Vo voltage should be regulated by the user.
FUNCTIONAL DESCRIPTION
The M5480 is specifically designed to operate 3 1/ 2 digit alphanumeric displays with minimal interface
with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data
bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit
is complete, thus providing non-multiplexed, direct drive to the display.
Outputs change only if the serial data bits differ from the previous time.
Display brightness is determined by control of the output current for LED displays. A 1nF capacitor
should be connected to brightness control, pin 13, to prevent possible oscillations.
A block diagram is shown in figure 1. The output current is typically 20 times greater than the current
into pin 13, which is set by an external variable resistor.
There is an internal limiting resistor of 400n nominal value.
__________________________
~~~~;~~~
________________________3~/6
367
M5480
FUNCTIONAL DESCRIPTION (continued)
Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the
36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the
35 bits of the shift registers into the latches.
At the low state of the clock a RESET signal is generated which clears all the shift registers for the next
set of data. The shift registers are static master-slave configurations. There is no clear for the master
portion of the first register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers will not clear.
When power is first applied to the chip an internal power ON reset signal is generated which resets all
registers and all latches. The START bit and the first clock return the chip to its normal operation.
Figure 3 shows the timing relationships between Data, and Clock. A maximum clock frequency of
0.5 MHz is assumed.
Figure 4 shows the Output Data Format for the 5480. Because it uses only 23 of the possible 35 outputs,
12 of the bits are "Don't Care".
For applications where a lesser number of outputs are used, it is possible to either increase the current
per output, or operate the part.at higher than 1V V OUT '
The following equation can be used for calculations.
Tj = [(V OUT)
(lLEO)
(No. of segments) + Voo • 7 mA] (132°C/W) + Tamb
where:
Tj = junction temperature (150°C max)
VOUT= the voltage at the LED driver outputs
I LEO = the LED current
132°C/W = thermal coefficient of the package
T amb = ambient temperature
Fig. 2 - Input Data Format
CLOCK
DATA
LOAD
(lNTERNAL)
_________________
n
..;...~
L..._ _ __
n
RE5ET
(INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
L _ _ __
Fig. 3
CLOCK
DATA
300ns MIN
...;4/'-6_ _ _ _ _ _ _ _ _ _ _ _
368
l.fi, ~~tm?~s.&' ------------
M5480
Fig. 4 - Serial Data Bus/Outputs Correspondence
TYPICAL APPLICATION
BASIC 3 1/2 Digit interface.
CLOCK DATA
POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations.
a)
"ouTl
In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.
R=
Vc - V D
MAX -
V OUT
MIN
N MAX· ID
The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments.
In this case the current variation in the single resistor is reduced and Ptot limited.
------------ ~ litnlg':9lf ___________
--'-5/6
369
M5480
b)
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly
chosen.
The total power dissipation of the IC depends, in a first approximation, only on the number of segments activated.
c)
In this configuration VOUT+VO is constant. The total power dissipation of the IC depends only on
the number of segments activated.
_6;...'6_ _ _ _ _ _ _ _ _ _ _ ~ I~tm?elj
370
------------
M5481
LED DISPLAY DRIVER
DIGIT LED DRIVER (14 SEGMENTS)
• 2CURRENT
GENERATOR OUTPUTS (NO
• RESISTOR REQUIRED)
CONTINUOUS BRIGHTNESS CONTROL
• SERIAL
,
DATA INPUT
• DATA ENABLE
• WIDE SUPPLY VOLTAGE OPERATION
•
• TTL COMPATIBILITY
technology. It utilizes the M5450 die packaged
in a 20-pin plastic package copper frame, making
it ideal for a 2-c1igit display. A single pin controls
the LED display brightness by setting a reference
current through a variable resistor connected
either to Voo or to a separate supply of 13.2V
maximum.
The M5481 is a pin-to-pin replacement of the
NS MM 5481.
Application examples:
•
MICROPROCESSOR DISPLAYS
•
INDUSTRIAL CONTROL INDICATOR
•
RELAY DRIVER
•
INSTRUMENTATION READOUTS
The M5481 is a monolithic MOS integrated
circuit produced with a N-channel silicon gate
DIP-20 Plastic
(0.25)
ORDERING NUMBER: M5481 B7
ABSOLUTE MAXIMUM RATINGS
Voo
VI
VO(Off)
10
Ptot
Supply voltage
Input voltage
Off. state output voltage
Output sink current
Total package power dissipation
TJ
Top
T stg
Junction temperature
Operating temperature range
Storage temperature range
-0.3 to
-0.3 to
15
V
V
15
V
15
40
mA
at 25°C
1.5W
at 85°C 800mW
150
°C
-25 to 85
°C
-65 to 150
°C
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
June 1988
1/6
371
M5481
CONNECTION DIAGRAM
-
OUTPUT BIT 8
20
OUTPUT BIT 9
OUTPUT BIT 7
19
OUTPUT BIT 10
OUTPUT BIT 6
18
OUTPUT BIT II
OUTPUT BIT 5
17
OUTPUT BIT 12
OUTPUT BIT 4
I5
16
OUTPUT BIT 13
OUTPUT BIT 3
I6
15
VSS
14
OUTPUT BIT 14
13
DATA ENABLE
12
DATA IN
11
CLOCK
OUTPUT BIT 2
OUTPUT BIT I
BRIGHTNESS
CONTROL
VOO
I7
I8
I9
110
5-5790
BLOCK DIAGRAM
OUTPUT 81T14
Fig. 1
OUTPUT BIT 1
BRIGHTNESS
CONTROL
SERIAL
DATA _ _-.!!+--l
CLOC..:..:K__---'!...f--1
..::2:..;/6'--_ _ _ _ _ _ _ _ _ _ _
372
~ !~I;m?v'l9A1
-------------
M5481
STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to
13.2V, Vss= OV, unless otherwise specified)
Parameter
Voo
Supply Voltage
100
Supply Current
VI
Input Voltages
Logical "0" Level
Logical "1" Level
IB
Brightness Input Current
(note 21
VB
Brightness Input
Voltage (pin 91
VO(off)
Off State Output Voltage
10
Output Sink Current
(note 31
Segment OFF
Segment ON
fClock
Input Clock Frequency
10
Output Matching (note 11
Notes:
Test conditions
Min.
Typ.
Max.
Unit
13.2
V
7
mA
-0.3
2.2
Voo-2
0.8
Voo
Voo
V
V
V
0
0.75
mA
4.3
V
13.2
V
10
IJ.A
10
4
25
IJ.A
mA
mA
0.5
MHz
± 20
%
4.75
Voo= 13.2V
± 10 IJ.A Input Bias
4.75';; Voo';; 5.25
V oo > 5.25
I nput Current = 750 IJ.A
Vo = 3V
V 0 = 1 V (note 41
Brightness In. = 0 IJ.A
Brightness In. = 100 IJ.A
Brightness In. = 750 }lA
3
0
2
12
0
2.7
15
I
1. Output matching is calculates as the percent variation from I MAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 mAo
4. The Vo voltage should be regulated by the user.
FUNCTIONAL DESCRIPTION
The M5481 uses the M5450 die which is packaged to operate 2-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the
display driver is accomplished with 2. signals, serial data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete, thus providing non--multiplexed, direct drive
to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1 nF capacitor should be
connected to brightness control, pin 9, to prevent possible oscillations.
A block diagram is shown in figure 1. The output current is typically 20 times greater than the current
into pin 9, which is set by an external variable resistor.
These is an internal limiting resistor of 400n nominal value.
---------------------------~~~~~~g~l~~~~
________________________~3/~6
373
M5481
FUNCTIONAL DESCRIPTION (continued)
Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits
of the shift registers into the latches.
At the low state of the clock a RESET signal is generated which clears all the shift registers for the next
set of data. The shift registers are static master slave configurations. There is no clear for the master
portion of the first sh ift register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers will not clear.
When power is first applied to the chip an internal power ON reset signal is generated which resets all
registers and all latches. The START bit and the first clock return the chip to its normal operation.
Figure 3 shows the timing relationships between Data, Clock and DATA ENABLE.
A maximum clock frequency of 0.5 MHz is assumed.
Figure 4 shows the Output Data Format for the M5481. Because it uses only 14 of the possible 35 out·
puts, 21 of the bits are "Don't Cares".
For applications where a lesser number of outputs are used it is possible to either increase the current
per output or operate the part at higher than 1V VOUT '
The following equation can be used for calculations.
TJ == [ (V OUT ) OLEO) (No. of segments) + Voo • 7 mA] (80°C!W) + Tamb
where:
TJ = junction temperature (150°C max)
VOUT = the voltage at the LED driver outputs
ILEO= the LED current
80o C/W = thermal coefficient of the package
Tamb = ambient temperature
Fig. 2 - Input Data Format
ClOCK
OA1A
n
LOAD
(lNTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
....._ _ __
n
RESEl
(INTERNAL)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
....._ __
Fig. 3
CLOCK
DA1A
300ns MIN
DATA ENABLE
lOOns MIN
.,;,,:,4/.:,.6_ _ _ _ _ _ _ _ _ _ _
374
~ I~tmo~~
S-S1U
------------
M5481
Fig. 4 - Serial Data Bus/Outputs Correspondence
TYPICAL APPLICATION
BASIC electronically tuned TV system
LED DISPLAY
'c
1_J
M5481
DISPLAY
DRIVER
5.5791
POWER DISSIPATION OF THE IC
The power dissipation of the IC can be limited using different configurations .
•vc
a)
VoUTj
In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.
Vc - Vo MAX - Vo MIN
N MAX· 10
The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments. In this case the
current variation in the single resistor is reduced and Ptot limited.
R=
-------------
-=---="":':':":"::-'--,....--=-';;;':';':';'-
~ ~~tm~
___________
-'-.....:5/...:.6
375
M5481
b)
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly
chosen.
The total power dissipation of the IC is, in first approximation, depending only on the number of
segments activated.
c)
5_5789
In this configuration VouT+Vois constant.The total power dissipation of the IC depends only on the
number of segments activated.
_6/_6 _ _ _ _ _ _ _ _ _ _ _ _
376
~ !~~~m&~~©~
-------------
M5482
LED DISPLAY DRIVER
• 2 DIGIT LED DRIVER (15 SEGMENTS)
•
CURRENT GENERATOR OUTPUTS (NO
RESISTOR REQUIRED)
•
CONTINUOUS
BRIGHTNESS
CONTROL
• SERIAL DATA INPUT
• WIDE
SUPPLY VOLTAGE
technology. It utilizes the M5450 die packaged
in a 20-pin plastic package copper frame, making
it ideal for a 2-digit display. A single pin controls
the LED display brightness by setting a reference
current through a variable resistor connected
either to Vee or to a separate supply of 13.2V
maximum.
OPERATION
• TTL COMPATIBILITY
Application examples:
•
MICROPROCESSOR DISPLAYS
•
INDUSTRIAL CONTROL INDICATOR
•
RELAY DRIVER
•
INSTRUMENTATION READOUTS
The M5482 is a monolithic MOS integrated
circuit produced with an N-channel silicon gate
DIP-20 Plastic
(0.25)
ORDERING NUMBER: M5482 B7
ABSOLUTE MAXIMUM RATINGS
Vee
VI
Vo (off)
10
Ptot
Supply voltage
I nput voltage
Off state output voltage
Output sink current
Total package power dissipation
Tj
Top
T st9
Junction temperature
Operating temperature range
Storage temperature range
-0.3 to 15
V
-0.3 to 15
V
V
15
40
mA
at 25°C
1.5W
at 85°C 800mW
150
°C
-25 to 85
°C
-65 to 150
°C
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and fun.ctional operation of the device at these or any .other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
June 1988
,
1/6
377
M5482
CONNECTION DIAGRAM
OUTPUT BIT 8
OUTPUT BIT 9
OUTPUT BIT 7
19
OUTPUT BIT 10
OUTPUT BIT 6
18
OUTPUT BIT 11
OUTPUT BIT 5
17
OUTPUT BIT 12
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 13
6
VSS
OUTPUT BIT 2
14
OUTPUT BIT 14
OUTPUT BIT 1
13
OUTPUT BIT 15
BRJGHTNESS
CONTROL
12
OATA IN
VDD
11
CLOCK
S~S997
BLOCK DIAGRAM
OUTPUT BIT 15
Fig. 1
OUTPUT BIT 1
BRIGHTNESS
CONTROL
35 LATCHES
SERIAL
DATA --1----"'+--1
C LOC.",K-"_-"--lf---1
S -5998
378
M5482
STATIC ELECTRICAL CHARACTERISTICS (Tamb within operating range, Voo= 4.75V to
13.2V, Vss= OV, unless otherwise specified)
Parameter
Voo
Supply Voltage
100
Supply Current
VI
I nput Voltages
Logical "0" Level
Logical "1" Level
Ie
Brightn.ess Input Current
(note 2)
Ve
Brightness Input
Voltage (pin 9)
VO(off)
Off State Output Voltage
10
Output Sink Current
(note 3)
Segment OFF
Segment ON
fClock
Input Clock Frequency
10
Output Matching (note 1)
Notes:
Test conditions
Min.
Typ.
Max.
Unit
13.2
V
7
mA
-0.3
2.2
Voo-2
0.8
Voo
Voo
V
V
V
0
0.75
mA
4.3
V
13.2
V
10
/lA
10
4
25
/lA
mA
mA
0.5
MHz
± 20
%
4.75
Voo= 13.2V
± 10 /lA Input Bias
4.75';; Voo';; 5.25
V oo > 5:25
I nput Current = 750 /lA
Vo = 3V
Vo = 1V (note 4)
Brightness In . = 0 /lA
Brightness In. = 100 /lA
Brightness In. = 750 /lA
3
0
2
12
0
2.7
15
1. Output matching is calculated as the percent variation from IMAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to
another.
3. Absolute maximum for each output should be limited to 40 mAo
4. The Vo voltage should be regulated by the user.
FUNCTIONAL DESCRIPTION
The M5482 uses the M5451 die which is packaged to operate 2-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1"
followed by the 35 data bits allows data transfer without an additional load signal.
The 35 data bits are latched after the 36th bit is complete, thus providing non--multiplexed, direct drive
to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1nF capacitor should be
connected to brightness control, pin 9, to prevent possible oscillations.
A block diagram is shown in fiqure 1. The output current is typically 20 tir,les greater than the current
into pin 9, which is set by an external variable resistor.
There is an internal limiting resistor of 400n nominal value.
379
M5482
FUNCTIONAL DESCRIPTION (continued)
Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits
of the sh ift registers into the latches.
.
At the low state of the clock a RESET signal is generated which clears all the shift registers for the next
set of data. The shift registers are static master slave configurations. There is no clear for the master
portion of the first shift register, thus allowing continuous operation.
There must be a complete set of 36 clocks or the shift registers will not clear.·
When power is first applied to the chip an internal power ON reset signal is generated which resets all
registers and all latches. The START bit and the first clock return the chip to its normal operation.
Figure 3 shows the timing relationships between Data and Clock.
A maximum clock frequency of 0.5 MHz is assumed.
Figure 4 shows the Output Data Format for the M5482. Because it uses only 15 of the possible 35 outputs, 20'of the bits are "Don't Cares".
For applications where a lesser number of outputs are used it is possible to either increase the current
per output or operate the part at higher than 1V V OUT.
The following equation can be used for calculations.
Tj
where:
== [ (V OUT ) OLEO) (No. of segments) + Voo • 7 mA] (80°C/W) + Tamb
T j = junction temperature (150°C max)
VOUT = the voltage at the LED driver outputs
ILEO= the LED current
80°C/W = thermal coefficient of the package
T amb = ambient temperature
Fig. 2 - Input Data Format
CLOCK
DATA
n
LOAD
(INTERNAL)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
L _ _ _ __
n
RESET
(INTERNAL>
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
.L-_ __
S-5785/1
Fig. 3
CLOCK
DATA
4.;.:/..:.6 _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~tmg~~~
380
_____________
M5482
Fig. 4 - Serial Data Bus/Outputs Correspondence
TYPICAL APPLICATION
BASIC electronically tuned TV system
LED DISPLAY
I~
Ie
KEYBOARD
POWER DISSIPATION OF THE IC
The power dissipation of the Ie can be limited using different configurations.
,vc
a)
I
VOUT
t
5-5781
In this application R must be chosen taking into account the worst operating conditions.
R is determined by the maximum number of segments activated.
Vc - Vo MAX - Vo MIN
N MAX' 10
The worst case condition for the device is when roughly half of the maximum number of segments
are activated.
It must be checked that the total power dissipation does not exceed the absolute maximum ratings
of the device.
In critical cases more resistors can be used in conjunction with groups of segments. In this case the
current variation in the single resistor is reduced and Ptot limited.
R=
---'''---:7:.....:.:..:~--:--=:...:='-'---
--------------------------~~~I~~&~~~~~
________________________
5~/6
381
M5482
b)
In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly
chosen.
.
The total power dissipation of the IC is, ~n first approximation, depending only on the number of
segments activated.
c)
In this configuration VOUT +V 0 is constant. The total power djssipation of the IC depends only on the
number of segments activated. .
_6~/6________________________ ~1~1~~g,~~
382
--------------------------
..~
.,L SGS-1HOMSON
~D~OO@rn[]J~©'iJ'OO@~D~~
M8438A
SERIAL INPUT LCD DRIVER
o
• DRIVES UP TO 32 LCD SEGMENTS
• DATA TRANSFER: FIXED ENABLE MODE
FOR DIP-40, ENABLE AND LATCH-MODE FOR
44PLCC
• INPUTS ARE CMOS, NMOS AND TTL
COMPATIBLE
•
•
•
•
CASCADABLE
REQUIRES ONLY 3 CONTROL LINES
ON CHIP OSCILLATOR
CMOS TECHNOLOGY FOR WIDE SUPPLY
VOLTAGE RANGE
• -40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M8438A is a CMOS integrated circuit that drives an LCD display, usually under microprocessor
control. The part acts as a smart peripheral that
drives up to 32 LCD segments. It needs only three
control lines due to its serial input construction. It
latches the data to be displayed and relieves the
microprocessor from the task of generating the required waveforms.
The M8438A can drive any standard or custom parallel drive LCD whether it be field effect or dynamic scattering. Several drivers can be cascaded,
if more than 32 segments are to be driven. The AC
frequency of the LCD waveforms can be supplied
by the user or can be generated by attaching a capacitor to the OSC input which determines the frequency of an internal oscillator.
The M8438A is available in DIE form and assembled in 40 pin dual-in line plastic or 44 PLCC
packages.
B
C
DIP-40 Plastic
44 PLCC Plastic Chip Carrier
ORDERING NUMBERS: M8438A DIE 1
M8438A B6
M8438A C6
PIN CONNECTIONS
~
+Voo
CLOCK
EL
2
39
SEGl
SEG32
3
3.
SEG2
SEGl1
4
37
SEGl
SEGle
5
36
V55
SEG2S
6
3S
DO
SEG 28
7
34
DI
33
SEG4
SEG 26
,•
32
SEG 5
SEG 25
10
31
05C.
SEG24
11
30
BP
SEG23
12
29
SEG6
SEG 22
13
2.
SEG 21
14
27
SEG8
SEG 20 15
26
SEG 9
SEG 21
SEG'
SEG 19
16
25 SEG10
SEG18
17
24
SEG1?
"
23
5EG12
22
SEG1]
21
50014
SEG 16
"20
SEGlS
SEG11
!:>_8309
~
~ 8~
,,
..." ., ...
..."
...... "" "
"
BEG
SEG
SEG
SEG
SEG23
SEGn
SEGZ'I
BEG
~!=
,
i!i
=:;;
~d=¥I:g
'" U 42 "
. o.
~
13
u
15
SEGZO( 16
SEG"
SEG
$EGO
1111 »21
22 23
2~
25 16 21 JI
=e"=::!!t!::$!:.
SEG
;=m~I;!==1
~
June 1988
"
1l
8
" DO
" .EG.
"
" osc.
.,
SEGI
" .EG'
"
" He
"
....
"
SEGU
seG
g ::; :::
.
u
~
1/7
383
M8438A
BLOCK DIAGRAM
OSC.
BP
SEG.
EL
CLOCK
MODE
CONTROL
MS
DIU----~--~
1 - - - - 0 DO
So 8307
OSC :Oscillator (capacitor or drive signal)
EL
:Enable/Latch control input
MS :Mode select input (not available in 40 Pin OIL)
01
:Serial data input
DO :Serial data output
BP
:Backplane output
SEG :Segment output signal
ABSOLUTE MAXIMUM RATINGS
Symbol
(VDD-VSS)
Parameter
Supply voltage
Value
Unit
-0.3 to +12
V
V
VI
Input voltage
VSS - 0.3 to VDD + 0.3
Vo
Output voltage
VSS - 0.3 to VDD + 0.3
V
Po
Power dissipation
250
mW
Storage temperature
-55 to +125
Operating temperature
-40 to +85
DC
DC
Tstg
TA
Stresses in excess of those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions in excess of those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
217
384
M8438A
ELECTRICAL CHARACTERISTICS (Tamb =25°C and VDD =5V unless otherwise noted)
STATIC ELECTRICAL CHARACTERISTICS
Symbol
Test Condition
Parameter
Voo
Supply Voltage
100
Supply Current
Oscillator f< 15kHz
Quiescent Current
Voo=10V
IQ
VIH
Input High Level
VIL
Input Low Level
liN
Input Current
CI
Input Capacitance
VIH
Input High Level
VIL
Input Low Level
liN
Input Current
Driven mode
RON
Segment Output Impedance
RON
Backplane Output Impedance
VOFF
Output Offset Voltage
CL = 250pF between each SEG output
and BP
RON
Data Output Impedance
IL = 100p.A
Min.
Max.
3
10
V
60
/LA
10
/LA
.5Voo Voo
0
.2Voo
±5
CLOCK
DI
EL
5
Driven mode
OSC
V
V
/LA
pF
V
.9Voo
Driven mode
Unit
V
.1Voo
±10
/LA
IlL = 10p.A
40
kO
IL = 100p.A
3
kO
±50
mV
3
kO
Max.
Unit
500
ns
DYNAMIC ELECTRICAL CHARACTERISTICS
Symbol
Test Condition
Parameter
Min.
tTR
Transition Time OSC
Driven mode
tso
Data Set-up Time
Fig. 1 and 2
150
ns
tHO
Data Hold Time
Fig. 1 and 2
50
ns
tSE
EL Set-up Time
Fig. 1
100
ns
tHE
EL Hold Time
Fig. 1
100
ns
tWE
EL Pulse Width
Fig. 2
175
ns
teE
tpd
Clock to EL Time
Fig. 2
250
DO Propagation Delay
Fig. 1, 2; CL = 55pF
Clock Rate
Voo=10 50% duty cycle;
f
DC
ns
500
ns
1.5
MHz
FUNCTIONAL DESCRIPTION
LCD-AC-GENERATOR
This block generates a 50% duty cycle signal for
the backplane output. The circuit can be used in
two different modes: oscillator or driven.
OSCILLATOR MODE:
In this mode the backplane frequency is determined by the internal RC oscillator together with an
8-stage frequency divider. For generating the backplane output signal of 50% duty cycle the oscillator frequency is divided by 256. The RC oscillator
requires an external capacitor to be connected bet-
ween input OSC and VSS. A value of 18pF gives
a backplane frequency of 80Hz ± 30% at
VDD = 5V. The variation of the backplane frequency
over the entire temperature and supply voltage range is ± 50%.
DRIVEN MODE:
In this mode the signal at the backplane output BP
is in phase with an external driving signal applied
to input OSC. This mode is used to synchronize
the LCD drive of two or more cascaded driver
circuits.
3/7
385
M8438A
FUNCTIONAL DESCRIPTION (continued)
DETECTION LOGIC
The circuit is able to distinguish between the conditions for oscillator or driven mode. If the circuit
is to be in the oscillator mode, the OSC pin has
a capacitor connected to it. The oscillator will start
as soon as the supply voltage exceeds a certain
minimim value. The signal at pin OSC swings within a range from 0.3Voo to 0.7VOO. If the circuit
is to be in the driven mode, the OSC pin has to be
forced to logic levels by an external source. The
transition time between the logic levels must be
short, so that the circuit does not react on the voltage level in between. In the driven mode the
8-stage frequency divider is by-passed.
SEGMENT OUTPUTS
A logic 0 at the data input 01 causes a segment
output signal to be in phase with the backplane signal and turns the segment off. A logic 1 causes
a segment output to be in opposite phase to the
backplane signal and turns the segment on.
MICROPROCESSOR INTERFACE
The circuit can operate in two different data transfer modes: Enable mode and latch mode. One of
either mode can be chosen with the mode select
input MS. An internal pull up device is provided between this input and VDD. Enable mode is selected if MS is left open or connected to VDD.
Latch mode is selected if MS is connected to VSS.
The input MS is not available, if the device is
assembled in the 40 pin package, and is internally fixed to operate in ENABLE MODE.
ENABLE MODE
Fig. 3 shows a timing diagram of the enable mode. Data is serially shifted in and out of the shift
register on the negative transition of the clock.
Serial entry into the shift register is permitted when
the enable/latch control EL is high. When EL is low
it causes the shift register clock to be inhibited and
the content of the shift register to be loaded into
the latches that control the segment drivers.
LATCH MODE
Fig. 4 shows a timing diagram of the latch mode.
Data is serially shifted in and out of the shift register on the negative transition of the clock.
Serial entry into the shift register is permitted independently of the enable/latch control EL. When
EL is high it causes a parallel load of the content
in the shift register into the latches. It is accepta417
386
ble to tie the EL line high. Then the latches are transparent and only two lines, clock and data input,
would then be needed for data transfer.
POWER-ON LOGIC
A power on reset pulse is generated internally when
the supply voltage is being turned on. The generation of the reset pulse is level dependent and will
occur even on a slowly rising supply Voltage.
The power on reset pulse resets all shift register
stages and the latches that control the segment drivers. Therefore all segment outputs are initially in
phase with the backplane output. This causes the
display to be blanked and no arbitrary data to show
up. This condition is maintained until data is shifted into the register and loaded into the latches.
CONOITIONS FOR POWER-ON RESET FUNCTION
The POR circuit triggers on the rising slope of the
positive supply voltage Voo. A reset pulse will be
generated, if conditions a) through d) are given:
a) Level
Rising slope from V1 to V2
V1 max=0.5V
V2 min=3.0V
----V2
~
VDO
------V1
VDO
b) Rise time
tr min=10 pS
tr max= 1 s
~
-----3.OV
I
-~---- -O.5V
I
--f-!+t1
12
c) Rise function
The function of Voo between t1 und t2 may be
nonlinear, but should not show a maximum and
should not exceed 0.25 V//Ls.
d) Recovery time
The minimum time between turn-off and turnon of Voo is 1s.
CASCADE CONFIGURATION
Several LCD drivers can be cascaded if a liquid crystal display with more than 32 segments is to be
connected.
The phase correlation between all segment outputs
is achieved by using the second (and any other)
device in the driven mode.
Two different cascade configurations can be chosen depending whether the LCD frequency is to
be determined by the internal RC oscillator or by
an external signal.
Figure 3 shows the connection scheme for a self
oscillating configuration, figure 4 shows the connection of an externally controlled one.
M8438A
Fig, 1 - Timing diagram of enable mode: set-up and hold time
CLOCK
ENABLE / LATCH
DATA IN
/
--------
I
:1
-\
tHE
tSE
f:---f ------------=x
1
I
1
-----
tso
DATA OUT
·1.1
tHO
tpd
-------,..----
~-831011
Fig, 2 - Timing diagram of latch mode: set-up and hold time
tCE
CLOCK
/
----
-----
ENABLE/LATCH
DATA IN
1
I
tso
DATA OUT
.1
-\
·1.1
f>--E-------------
tpd'_ _ - - - - - - - - - - - - - -
~
'I
tWE
=:)(
•
~-831111
517
387
M8438A
Fig. 3 - Timing diagram of enable mode: Serial load into SR and parallel transfer to LCD
ENABLE I LATCH
CLOCK
DATA IN
SEGMENTS
BACKPLANE
Fig. 4 - Timing diagram of latch mode: Serial load into SR and parallel transfer to LCD
ENABLE I LATCH
CLOCK
DATA IN
SEGMENTS
BACKPLANE
6/7
388
M8438A
Fig. 5 - Cascade configuration, self oscillating
DEVICE 2
DEVICE 1
r1_0_S_C___B_Pjl
'
I
I
LCD
lo_s_c___B_p...H ..I'"_B-_P-_-_-_-..,..
• ...
DEVICE n
y. .
~
O_S_C_ _ _B_P...
NC
5- 8314
Fig. 6 - Cascade configuration, drive by external signal
LCD
DRIVING
SIGNAL
0--_.....
DEVICE 2
OSC
NC
BP
I
I
I
I
I
DEVICE n
y.
~
O_S_C_ _ _B_P
...
NC
5-8364
717
389
M8439
SERIAL INPUT LCD DRIVER
• DRIVES UP TO 32 LCD SEGMENTS
• DATA TRANSFER: LATCH MODE
• INPUTS ARE CMOS, NMOS AND TTL
COMPATIBLE
• CASCADABLE
• REQUIRES ONLY 3 CONTROL LINES
Plastic DIP-40
• ON CHIP OSCILLATOR
• CMOS TECHNOLOGY FOR WIDE SUPPLY
VOLTAGE RANGE
ORDERING NUMBERS: M8439 86
M8439 DIE 1
• -40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M8439 is a CMOS integrated circuit that drives an LCD display, usually under microprocessor
control. The part acts as a smart peripheral that
drives up to 32 LCD segments. It needs only three
control lines due to its serial input construction. It
latches the data to be displayed and relieves the
microprocessor from the task of generating the required waveforms.
The M8439 can drive any standard or custom parallel drive LCD whether it be field effect or dynamic scattering. Several drivers can be cascaded,
if more than 32 segments are to be driven. The AC
frequency of the LCD waveforms can be supplied
by the user or can be generated by attaching a capacitor to the OSC input which determines the frequency of an internal oscillator.
The M8439 is available in DIE form and assembled
in 40 pin dual-in line plastic.
PIN CONNECTIONS
+"DO
~
2
39
SEG 1
SEG32
3
3.
SEG2
SEGll
4
37
SEG 3
SEGlO
•
36
V55
DO
SEG 29
6
3.
SEa 28
7
34
01
SEG 27
33
SEG4
SEG 26
32
SEG 5
SEG 25 10
31
osc.
SEG24
11
30
BP
SEG23
12
29
SEG6
SEa 22
13
2.
SEG 21
14
27
SEGS
SEGIS 17
24
SEG11
SEGl7
,.
"
SEG 9
23
SEG12
SEGli
19
22
51:G13
SEGtS
20
21
SEG14
SEa 20 15
SEG 19
seo
seo
BEG
BEG
CLOCK
EL
16
SEG?
25 SEGtO
!>_8l09
BEG
BEG
BEG
mm m~ ~
June 1988
~
8
116
391
M8439
BLOCK DIAGRAM
BP
OSC.
SEG.
EL
MODE
CLOCK
CONTROL
SR CLOCK
DIU-------~----~
t - - - ( ) DO
S·9596
OSC Oscillator (capacitor or drive signal)
EL
Enable/Latch control input
01
Serial data input
DO :Serial data output
BP
:Backplane output
SEG :Segment output signal
ABSOLUTE MAXIMUM RATINGS
Symbol
(VDD-VSS)
Parameter
Supply voltage
Value
Unit
-0.3 to +12
V
V
VI
Input voltage
VSS - 0.3 to VDD + 0.3
Vo
Output voltage
VSS - 0.3 to VDD + 0.3
V
PD
Power dissipation
250
mW
Tstg
Storage temperature
-55 to +125
DC
DC
TA
Operating temperature
-40 to +85
Stresses in excess of those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions in excess of those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2/6
392
M8439
ELECTRICAL CHARACTERISTICS (Tamb =25°C and VDD =5V unless otherwise noted)
STATIC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Voo
Supply Voltage
100
Supply Current
Oscillator f < 15kHz
Quiescent Current
Voo=10V
10
VIH
Input High Level
VIL
Input Low Level
liN
Input Current
Min.
Max.
3
10
V
60
pA
10
/LA
.5Voo Voo
0
.2Voo
±5
CLOCK
DI
EL
CI
Input Capacitance
VIH
Input High Level
VIL
Input Low Level
liN
Input Current
Driven mode
RON
Segment Output Impedance
RON
Backplane Output Impedance
VOFF
Output Offset Voltage
CL = 250pF between each SEG output
and BP
RON
Data Output Impedance
IL = 100pA
5
1OSC
Driven mode
V
V
pA
pF
V
.9Voo
Driven mode
Unit
V
·1Voo
±10
/LA
IlL = 10pA
40
kG
IL= 100pA
3
kG
±50
mV
3
kO
Max.
Unit
500
ns
DYNAMIC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
tTR
Transition Time OSC
Driven mode
tso
Data Set-up Time
Fig. 1 and 2
150
ns
tHO
Data Hold Time
Fig. 1 and 2
50
ns
tSE
EL Set-up Time
Fig. 1
100
ns
tHE
EL Hold Time
Fig. 1
100
ns
tWE
EL Pulse Width
Fig. 2
175
ns
teE
tpd
Clock to EL Time
Fig. 2
250
ns
f
DO Propagation Delay
Fig. 1, 2; CL = 55pF
Clock Rate
Voo= 1050% duty cycle;
DC
500
ns
1.5
MHz
FUNCTIONAL DESCRIPTION
LCD-AC-GENERATOR
This block generates a 50% duty cycle signal for
the backplane output. The circuit can be used in
two different modes: oscillator or driven.
OSCILLATOR MODE:
In this mode the backplane frequency is determined by the internal RC oscillator together with an
8-stage frequency divider. For generating the backplane output signal of 50% duty cycle the oscillator frequency is divided by 256. The RC oscillator
requires an external capacitor to be connected bet-
ween inputOSC and VSS. A value of 18pF gives
a backplane frequency of 80Hz ± 30% at
VDD = 5V. The variation of the backplane frequency
over the entire temperature and supply voltage range is ± 50%.
DRIVEN MODE:
In this mode the signal at the backplane output BP
is in phase with an external driving signal applied
to input OSC. This mode is used to synchronize
the LCD drive of two or more cascaded driver
circuits.
3/6
393
M8439
FUNCTIONAL DESCRIPTION (continued)
DETECTION LOGIC
The circuit is able to distinguish between the conditions for oscillator or driven mode. If the circuit
is to be in the oscillator mode, the OSC pin has
a capacitor connected to it. The oscillator will start
as soon as the supply voltage exceeds a certain
minimim value. The signal at pin OSC swings within a range from 0.3Voo to O.7Voo. If the circuit
is to be in the driven mode, the OSC pin has to be
forced to logic levels by an external source. The
transition time between the logic levels must be
short, so that the circuit does not react on the voltage level in between. In the driven mode the
8-stage frequency divider is by-passed.
SEGMENT OUTPUTS
A logic 0 at the data input 01 causes a segment
output signal to be in phase with the backplane signal and turns the segment off. A logic 1 causes
a segment output to be in opposite phase to the
backplane signal and turns the segment on.
MICROPROCESSOR INTERFACE
Fig. 2 shows a timing diagram.
Data is serially shifted in and out of the shift register on the negative transition of the clock.
Serial entry into the shift register is permitted independently of the enable/latch control EL. When
EL is high it causes a parallel load of the content
in the shift register into the latches. It is acceptable to tie the EL line high. Then the latches are transparent and only two lines, clock and data input,
would then be needed for data transfer.
POWER·ON LOGIC
A power on reset pulse is generated internally when
the supply voltage is being turned on. The generation of the reset pulse is level dependent and will
occur even on a slowly rising supply voltage.
The power on reset pulse resets all shift register
stages and the latches that control the segment dri-
4/6
394
verso Therefore all segment outputs are initially in
phase with the backplane output. This causes the
display to be blanked and no arbitrary data to show
up. This condition is maintained until data is shifted into the register and loaded into the latches.
CONOITIONS FOR POWER-ON RESET FUNCTION
The POR circuit triggers on the rising slope of the
positive supply voltage Voo. A reset pulse will be
generated, if conditions a) through d) are given:
a) Level
Rising slope from V1 to V2
V1 max=0.5V
V2 min=3.0V
b) Rise time
tr min= 10 fLS
tr max=1 s
~
VDD
----V2
------V1
IiDo
-----3.tN
~
-~-----O.5V
I
I
--Ti-
c) Rise function
The function of Voo between t1 und t2 may be
nonlinear, but should not show a maximum and
should not exceed 0.25 V/p.S.
d) Recovery time
The minimum time between turn-off and turnon of Voo is 1s.
CASCADE CONFIGURATION
Several LCD drivers can be cascaded if a liquid crystal display with more than 32 segments is to be
connected.
The phase correlation between all segment outputs
is achieved by using the second (and any other)
device in the driven mode.
Two different cascade configurations can be chosen depending whether the LCD frequency is to
be determined by the internal RC oscillator or by
an external signal.
Figure 3 shows the connection scheme for a self
oscillating configuration, figure 4 shows the connection of an externally controlled one.
M8439
Fig. 1 - Timing diagram of latch mode: set-up and hold time
ICE
/
CLOCK
----
{
-----
ENABLE/ LATCH
~
:IIWE
1 ·1" E-;--u
[-m--------=x
1
DATA IN
ISO
..
DATA OUT
.IIPd'_ _ - - - - - - - - - - - - - -
,
5- 831111
Fig. 2 - Timing diagram of latch mode: Serial load into SR and parallel transfer to LCD
ENABLE I LATCH
CLOCK
DATA IN
SEGMENTS
BACKPLANE
5/6
395
M8439
Fig. 3 - Cascade configuration, self oscillating
DEVICE 1
DEVICE 2
..L_C_D_--.
B_p.. ,IT •1. .o_s_c___B_p~H...B_P_.......
.c1l...o_S_C_ _ _
I
:
DEVICE n
y. .
~
o_S_C_ _ _B_P...
N.C
5-8311,
Fig. 4 - Cascade configuration, driven by external signal
DEVICE
LCD
DRIVING
SIGNAL
OSC
BP
DEVICE 2
OSC
1
I
I
I
I
DEVICE n
YOSC
BP
NC
BP~NC
5-8364
6/6
396
M8571
1024 BIT SERIAL S-BUS/12C BUS NMOS EEPROM
•
•
•
•
•
•
•
•
•
•
10 YEAR DATA RETENTION
SINGLE + 5V POWER SUPPLY
AUTOMATIC POWER DOWN
INTERNAL HIGH VOLTAGE AND
SHAPING GENERATOR
SELF TIMED EIW OPERATION
AUTOMATIC ERASE BEFORE WRITE
3-WIRES S-BUS (12C BUS COMPATIBLE)
2 CHIP SELECT FOR SIMPLE
MEMORY EXTENSION
SELF INCREMENTING ADDRESS REGISTER
MULTI-MODE ADDRESSING (WHEN MS = V1H
ALLOWING:
- PARTITIONING OF THE 1024 BITS INTO:
- 128 x 8bit
- 64x 16bit
- 32x32bit
- OPCODE-L1KE ADDRESSES FOR:
- halting of a modify operation
- reading of the device "busy" status
- "block erase" operation
- reloading of the address register with the
pre-increment value
B
DIP-8
(Plastic Package)
(Ordering Information at the end of the datasheet)
PIN CONNECTIONS
eSl
Vee
esz
MS
SEN
seL
GND
SDA
DESCRIPTION
The M8571 is a 1024-bit Electrically Erasable Programmable Read Only Memory (EEPROM). It allows partitioning of the 1024-bit into: 128 x 8-bit
(bytes); 64 x 16-bit (words); 32 x 32-bit (pages).
The M8571 is manufactured with SGSTHOMSON's reliable floating gate technology. Addresses and data are transferred serially via a threeline bidirectional bus (8-BUS). When the MS pin
is at VIL the device works like the PCD 8571
CMOS RAM. The built-in address register is incremented automatically after writing or reading of
each address partition.
The M8571 is designed and tested for applications
requiring up to 10.000 erase/write cycles and data retention in excess than 100 years.
The M8571 is available in 8-pin dual in-line plastic
and ceramic packages.
PIN DESCRIPTION
- Vcc; GND: Power supplies.
- SCL: Clock line for the S-BUS system.
- SEN: Start/Stop line for the S-BUS system.
- SDA: Data line for the 8-BUS system (open drain).
- CS1/CS2: Chip Select inputs. In order to select
a device the 2 bits (7th and 6th) in the first byte
June 1988
PIN NAMES
CS
CHIP SELECT INPUTS
SEN
START/STOP INPUT
SCl
CLOCK INPUT
SDA
DATA INPUT/OUTPUT
Vcc
POWER SUPPLY
GND
GROUND
MS
MODE SELECT INPUT
of the interface protocol, must match the CS
values.
- MS: Mode Select input to determine the operating mode of the M8571 (this pin can recognize
a non standard level, VIN~ 7.5V, to enable
"Block Erase" operations).
1/11
397
M8571
BLOCK DIAGRAM
SEN
r"L
SDA
"
"
SCC
~
START
STOP
DETECTOR
~
r-t
~ ~ CHIP ADDRESS
~
RECOGNIZER
INTERFACE
TIMING
~
GENERATOR
"CSI
"CS2
t
ADDRESS+BACKUF
>-----00
REGISTERS
0---- GND
o--VCC
MS"
OPCODE DECODER
ADDRESSES
OPCODES
L
I
STATUS REG.
E/W
TIMING
CONTROL
HIGH VOLTAGE
SUPPLY
GENERATOR
SHAPER
~
~
-1 WORD~~
~
~
H
DECODER
----
-
DATA REG.
2
COLUMN
DECODER
ROW
DECODER
-
16
r-
RD/WR COMPARE
CIRCUITS
t
COLUMN
SELECTION
64.16BIT
CELL MATRIX
5-783812
ABSOLUTE MAXIMUM RATINGS
Symbol
VI
Tamb
Tstg
Parameter
All Input or Output voltages with respect to ground
Ambient temperature under bias IB1
IB6
Storage temperature range
Value
Unit
+ 6 to - 0.6
-10 to + 80
-50 to + 95
-65 to + 125
V
°C
°C
°C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
.
2/11
398
M8571
ELECTRICAL CHARACTERISTICS (0 0 to + 70°C, for standard Temperature/- 40 0 to + 85°C for extended Temperature, VCC = 5V ± 10% unless otherwise specified)
DC AND OPERATING CHARACTERISTICS
Values
Symbol
Parameter
Test Conditions
Min.
Typ.
Unit
Max.
ILl
Input load Current
VIN=5.5V
10
ILO
Output leakage Current
VOUT=5.5V
10
pA
ICC2
Vce Current Active
20
mA
10
pA
VIL
Input low Voltage
-0.1
1.5
V
VIH
Input High Voltage
3.0
Vce+ 1
V
VOL
Output low Voltage
0.4
V
IOL=3 mA
AC CHARACTERISTICS (refer to S-8US Timing Diagram)
Values
Symbol
Parameter
fSCL
SCl clock frequency
TI
Tolerable spike width on bus
tAA
SCl low to SDA data out valid
tBUF
Time the bus must be free
Test Conditions
Unit
Min.
Max.
0
125
KHz
100
ns
3.5
p.S
4
p.S
before a new transmission
can start
tHDSTA
Start condition hold time
4
p.S
tLOW
Clock low period
4
liS
tHIGH
Clock high period
4
liS
tsu STA
Start condition set-up time
4
liS
0
liS
250
ns
(for a repeated start condition)
tHO OAT
Data in hold time
tsu OAT
Data in set-up time
tR
SDA and Sel rise time
700
ns
tF
SDA and SCl fall time
300
ns
tsu STO
Stop condition set-up time
4
lis
ERASEIWRITE CHARACTERISTICS
Values
Symbol
Parameter
tEW
Erase/Write cycle time
tBe
Block erase time
Test Conditions
Min.
Note 1
5
Unit
Typ.
Max.
6
10
ms
10
ms
Note 1: The tew is the same for byte, word, and page configuration
3/11
399
M8571
S-BUS TIMING DIAGRAM
SDA
/ -_ _ _..1
f----4f--
'HDSTA-I-........
SCL
SEN
'su S1'O
---t--
$-'0'28
S-BUS DESCRIPTION
The S-BUS is a three-wire bidirectional data-bus
with functional features similar to the 12C bus. In
fact the S-BUS includes decoding of START/STOP
conditions and the arbitration procedure in case of
multi master system configuration. Both different
transmission modes are shown in figures 2a and 2b.
As it can be seen, the SOA line, in the 12C bus,
represents the ANO combination of SOA and SEN
lines in the 5-BUS.
If the SOA and the SEN lines of the S-BUS are
short-circuit connected, they appear as the SOA
line of 12C bus.
The START/STOP conditions (respectively pOints
1 and 6) are detected (by the peripherals designed
to work with S-BUS) by a transition of the SEN line
(1 - - > % - - > 1) while the SCl line is at the
high level.
The SOA line is only allowed to change during the
time the SCl line is low (points 2, 3, 4, 5). After
the START information (point 1) the SEN line
returns to the high level and remains unchanged
for all the time the transmission is performed.
When the transmission is completed (pOint 5) the
SOA line is set to high level and, at the same time,
the SEN line returns to the low level in order to supply the STOP information with a low to high transition; while the SCl line is at high level.
On the 5-BUS, as on the /2C bus, each byte of eight
bits is followed by one acknowledge bit which is
a high level put on the SOA line by transmitter.
A peripheral that acknowledges has to pull down
the SOA line during the acknowledge clock pulse
as shown in Figure 3.
4111
400
FIG. 1 - S-BUS CONFIGURATION
r--'
I
I
I . ,
--+-h
t. 1\ 1 r\
i \jJ . \JJ
SCl
1
\
\-..1'
III
SOA
~
SEN
1
1
'
1\L.,fi
t
I
I
II
I\
II
! J
: ,I !
L __
1
2
rn-
I:
i
)~---~
j!~
,--,
l r\ l rHW \lJ! !
,'7\
;
1
~lj
------rur
I
I
I
ill.
I
I
1
3
'5
I
I
I
I
I
l:!
'- __ ..1
I
6
START
STOP
S-792411
FIG. 2 ·12C BUS CONFIGURATION
FIG. 3 • ACKNOWLEDGE
r--,
~
SCL
I
I
SDA~~
, ,'
l\U
.
\
~
____
J
A
I
,
SEN
L_J
START
S-7923/1
M8571
S-BUS DESCRIPTION (Continued)
.An addressed receiver has to generate an
aknowledge after the reception of each byte; otherwise the SDA line remains at the high level during
the ninth clock pulse time.
In this case the master transmitter can generate
the STOP information, via the SEN line, in order
to abort the transfer.
FIG. 4 - SYSTEM WITH S-BUS PERIPHERALS
COMPATIBILITY S-BUS/12C BUS.
Using the 8-BUS protocol it's possible to implement
"mixed" system including S-BUSII2C bus
peripherals.
In order to have the compability with the 12C bus
peripherals, the devices including the S-BUS interface must have their SDA and SEN pins connected together as shown in figures Sa and Sb.
It is also possible to use mixed S-BUS/12C bus protocols as showed in figure Sc. S-BUS peripherals
will only react to S-BUS protocol signals, while 12C
bus peripheral will only react to 12C bus signals.
seL
seL
SOA
SOA
SEN
SEN
S-BUS
DEVICE
I'P
S-8US
PROTOCOL
~
seL
'---
SOA
~
SEN
S-8US
DEVICE
5-192512
Fig. 5 - SYSTEM WITH "MIXED" S-BUS/12C BUS PERIPHERAL
seL
5eL
seL
SOA
50A
SOA
SEN
~
L
SCL
L
SEN
M8571
)JP
SOA
SEN
M85?1
i2C BUS
MASTER .
S-BUS
PROTOCOL
L - SCL
(a)
~
-
50A
seL
SOA
12C BUS
12C BUS
SLAVE
(b)
5-1929
SLAVE
s.-'1967
seL
seL
50A
SOA
SEN
SEN
M8S71
}JP
S-BU51
PC BUS
PROTOCOL
-
SCL
'------- SOA
(e)
peBUS
SLAVE
5-864611
6i
SGS-THOMSON
':IfI.. i!iO©IRl@I<~I<©1lIRl@i:!O©®
5/11
401
M8571
8-BUS DESCRIPTION (Continued)
MUlTIMASTER SYSTEM.
The S·BUS allows the implementation of the mul·
timaster configuration (two or more master stations
and slave peripherals). In such a system if two or
more transmitter. through the SEN line (SEN 1.... 0
while SCl = 1). require the bus at the same time. the
arbitration procedure is performed as in the 12C bus.
FIG. 6 • MULTIMASTER SYSTEM
SCL
SCL
SCL
SOA
seA
seA
SEN
SEN
s.~~s
)JP
S-BUS
MASTER
MASTER
SEN
SCL
SOA
.-l
)JP
)JP
S-BUS
MASTER
12CBUS
MASTER
~
SCL
~
SCL
>--c----
seA
>--r---
SOA
SEN
"CBUS
SLAVE
M6S71
~
-
SCL
~
seA
>---
SEN
-
S-BU5
SLAVE
5-864911
402
SEN
M85?!
S~8648/1
6/11
SCL
SDA
M8571 .
S-8US INTERFACE
The serial, 3-wire, interface (SDA, SCl and SEN
wires are open drain to allow "wired-and" operation) connects several devices which can be divided
into "masters" and "slaves". A master is a device
that can manage a data transfer; as such, it drives
the Start and Stop (SEN), the clock (SCl) and the
data (SDA) lines. The bus is "multimaster" in that
more master devices can access it; arbitration
pr0gedures are provided in the bus management.
Obviously, at least one master must be present on
the "bus. The M8571 is a hardware slave device.
It can only answer the requests of the masters on
the bus; therefore SDA is an I/O, while SCl and
SEN are inputs. The S-BUS allows two operating
speed: high (125KHz) and low (2KHz). The M8571
can work at both high and low speed.
START/STOP ACKNOWLEDGE
The timing specs of the S-BUS protocol require that
data on the SDA and SEN lines be stable during
the "high" time of SCL. Two exceptions to this rule
are foreseen and they are used to signal the start
and stop condition of a data transfer.
A "high to low" transition on the SEN line with SCl
"high", is a st/irt (STA).
'
A "low to high" transition on the SEN line with SCl
"high", is a stop.
'
Data are transmitted in 8-bit groups; after each
group, a ninth bit is interposed, with the purpose
of acknowledging the transmitting sequence (the
transmitter device place a "1" on the bus, the acknowledging receiver a "0").
INTERFACE PROTOCOL
The following description deals with 8-bits data
transfers, so that it fully fits when the memory is
"seen" as 128 x 8 array. Although the basic structure of the protocol remains the same the behaviour
of the M8571 in 16 or 32 bit data transfers is somewhat different. The differencies are descibed later
on.
The interface protocol comprises:
- A start condition (STA)
- A "chip address" byte, trasmitted by the master,
containing two different informations.
a) the code identifying the device the master
wants to address (this information is present
in the first seven bits); 4bits indicates the
type of the device (i.e. memory, tuning, AID,
etc.; the code for memories is 1010); then
there is a bit at low level and 2bits that are
the Chip Select configuration that must
match the hardware present on the 2 CS
pins (this is the case of a device with 2 Chip
Select like the M8571 , for M8571 CS1 and
CS2 must match respectively the 7th and the
6th bit of the byte).
b) the direction of transmission on the bus (this
information is given in the 8th bit of the
byte); "0" means "Write", that is from the
master to the slave, while "1" means
"Read". The addressed slave must always
acknowledge.
The sequence, from now on, is different according to the value of the R/W bit.
1) RIW = "0" (WRITE)
In all the following bytes the master acts as
transmitter; the sequence follows with:
a) a "word address" byte containing the address of the selected memory word and/or
opcode (see word address/opcode section).
b) a "data" byte which will be written at the address given in the previous byte.
c) further data bytes which, due to the self incrementing address register, will be written
in the "next" memory locations. At the end
of each byte the M8571 acknowledges.
d) a stop condition (STO)
After receiving and acknowledging a data byte or
a set of data bytes to be written, the M8571 automatically erases the addressed memory locations
and rewrites them with the received data. Since the
EIW time for an EEPROM is in the order of 10 ms
the next operation can take place only after t~
(what the master can and must do is described in
the EIW TIME SPECS section).
An example of a write sequence is given below:
o. STA
1. 10100ss0 A (M8571 acknowledges only if
"ss" matches its CS code)
2. xyyyyyyy A
3. zzzzzzzz A (at this moment the M8571
starts writing zzzzzzzz at the
address yyyyyyy)
4a. t t t t t t t t H (the new data is not acknowledged while the M8571 is
busy)
4b. t t t t t t t t A (now the M8571 writes data
t t t t tt t t at address
yyyyyyy+1)
The write sequence can be composed by an unlimited number of data bytes.
7/11
403
M8571
MASTER TRANSMITS TO SLAVE RECEIVER (WRITE MODE)
acknowledge
from slave
acknowledge
from slave
Is I
acknowledge
from slave
I Msa
l
t
I
L--laat
R/W
byt~
auto increment
memory word address
2) RIW = "1" (READ)
3) MIXED SEQUENCE
In this case the slave acts as transmitter and, therefore, the transmission changes direction. The second byte of the sequence will be sent by the
M8571 and it will contain the data present in the
memory present at the address pointed by the "current" value of the address register. Following bytes
will be the data present at the "next" addresses.
At the end of each byte, the M8571 places a "1"
on the bus during acknowledge time and waits for
the master to send a "0" (meaning "acknowledge").
When the master want to stop the transfer, it gives
a "1" (not "acknowledged"): as a consequence,
the M8571 leaves the bus high so that the master
can give the stop condition. An example is given
below:
When the master wants to read a memory location
different from the one currently addressed, a longer
sequence is needed, which includes the writing of
the address register. The sequence is as follows:
O. STA
1. 10100ss0 A
2. xyyyyyyy A
3. STA
4. 10100ss1 A
5. xxxxxxxx H
Where xxxxxxxx is the data present in the yyyyyyy memory location
As appears from the example, a start condition can
be given without a previous stop condition.
O. STA
1. 10100ss1 A
2. xxxxxxxx H (xxxxxxxx is the data present
in the currently addressed
memory location; H is the high
level placed on the bus by
M8571)
MASTER READS SLAVE IMMEDIATELY AFTER FIRST BYTE (READ MODE)
acknowtedga
from slave
acknowledge
. from master
hse
~
acknowledge
from master
,
I s I ~L~VE: A~O~E~ >H : : :OA!A: : : H : : : : : : : 1, I I
p
RJw
I...--
n
bytee--ij
L----
auto increment
word address
8/11
404
n bytes------J
M8571
MASTER READS AFTER SETTING WORD ADDRESS (WRITE WORD ADDRESS; READ DATA)
acknowledge
from slave
acknowledge
from muter
~M88
S
SLAVE ADDRESS
0
A X
acknowledge
from master
A
S
SLAVE ADDRESS
at this moment master
}
transmitter becomes
master receiver and
M8571 slave receiver
becomes slave transmitter
~
1 A
jJ-tw
n
DATA
A
bytes
~
auto increment
word .tdress
1
MSB
~
WORD ADDRESS
lasl byte ----oJ
4) EIW TIME SPECS
After the beginning of an EIW operation at a certain location the M8571 is "busy" until the operation is finished. To show this busy state, the M8571
refuses acknowledge of the next data bytes to remove the M8571 from the "busy" state a data byte
must be sent after the tEW is over. This "dummy"
byte will not be acknowledged and written. The data
to be written in the next address must De sent again
and will be acknowledged and written by the
M8571.
The master device that wants to use the self increment feature must therefore keep sending the next
data byte and monitoring the acknowledge bit until it becomes active.
The communication sequence on the bus becomes, therefore.
O. STA
1. 10100ss0 A
2. xyyyyyyy A
3. zzzzzzzz A
4a. t t t t t t t t H (not acknowledged when
t "0" transition on SDA
while SCl remains at "1 ") and a subsequent address byte. By assigning a unique address to each
circuit, several circuits may be connected to the
12C BUS without interfering each other.
If the M8716A recognizes an address transmitted
on the bus as its own address, the data transfer
starts. The least significant bit of the address word
controls the direction of data transfer (R/W-control).
If it is set to "0", data is transferred from the microcomputer to the Circuit, i.e. the content of the
time counters is modified. If it is set to "1" the time information is read out by the microcomputer.
The clock frequency (SCl) may be from DC up to
100kHz. If a carry of the time counter should take
place during a data transfer, the carry will be stored and made after the data transfer. As only one
carry can be stored, the whole data transfer must
not take a time longer than one second.
SYNCHRONIZATION
For easy of synchronization with an external time
referenCE> in case of small deviations « + /30sac), only the address (with RtW = "0") has
to be transmitted, followed immediately by a stop
condition. No data is transmitted (see Fig. 4). The
second divider block (128Hz to 1Hz) and the seconds counter are reset. If the seconds counter was
at position 30 ... 59, a carry to the minutes counter takes place in addition to the reset.
POWER FAil
In case of total power fail an internal register is set
to "0". This register disables the data of the watch.
So in a read cycle the JLP recognizes "0" of the
watch content. This is a unique situation appearing only in case of a power fail. The power fail register is automatically reset by the first "write"
command.
PULSE OUTPUTS FOUT, SEC
The output frequency of the first divider block
(128Hz) is provided on the pin FOUT and facilitates adjustment of the oscillator frequency without
loading (and detuning) the oscillator.
The output SEC (1Hz) may be utilized for a blinking second indication.
Both pins FOUT and SEC can also be used as input during the functional test. A low impedance
(50 to 1000) external signal source which overrides the internal output buffer can drive the circuit
at a frequency higher than the normal rate. This
allows to reduce test time.
3/6
411
M8716A
Fig. 1 - Complete timing for an address/-read; resp. address/-write cycle
RIW
STA CONDITION (5l
=1101 001
tI __
• -=""'-=-------__
ADDRESS
~
ACKNOWLEDGE(A)
STOP CONDITIONCP)
ACK(A)
l . ._____
SUBSEQUENT
OATABYTES
---"O.:::T.::
• ...:":.:.V.:.:TE=---_ _ __
50.
_____ r 5el
Fig. 2a - Data format for one cycle address/-read (with calendar)
ADDRESS. R'W: 1
1
1
MONTH
DAY
1 1
LS
58
, " "5
HRS
..,...
Fig. 2b - Data format for one cycle address/-write (with calendar)
ADDRESS. R'Woo
o x
(MONTH
lOS
4/6
412
x x
x x
DAY
58,
LS
HRS
1058
A
LS8
M8716A
Fig. 3a - Data format for one cycle address/-read (with day of week indication)
, , x x
ADDRE55. R/W='
X
DAY
5.
,,
HR5
M5
".
MIN
M5
Fig. 3b - Data format for one cycle address/-write (with day of week indication)
x x
ADDRE55. R/W=O
HR5
MS.
MIN
MS.
L5.
Fig. 4 - Data format for synchronisation (deviation < 30sec)
51 ADDRE55. RtW=O
III
A
p
$_1980
5/6
413
M8716A
Fig. 5 - Test circuit
2Kn
+
2.4V
SCL~----l
M8716A
5-7963/1
Fig. 6 - Typical application
+'5V POWER SUPPLY
'5 to 30pF
VOO
SOA
OSC IN
+
CJ
O.l,uF
32,768KHz CJ
M8716A
SCL
OSC OUT
VSS
5-1964/1
to microcomputer
6/6
414
NiCd
ACCUMULATOR
~ SCiS-THOMSON
lit..,
[ii'A]D©rru©rn[Lrn©'j]'OO©~D©~
L
M9306
256 BIT (16 x 16) SERIAL NMOS EEPROM
• SINGLE SUPPLY READIWRITE/ERASE
OPERATIONS (5V±10%)
• TTL COMPATIBLE
• 16x 16 READIWRITE MEMORY
• LOW STANDBY CURRENT
• LOW COST SOLUTION FOR NON VOLATILE
ERASE AND WRITE MEMORY
• RELIABLE FLOTOX PROCESS
• EXTENDED TEMPERATURE RANGE
B
DIP-8
(Plastic Package)
M
S08
(Plastic Micropackage)
(Ordering Information at the end of the datasheet)
PIN CONNECTIONS
DESCRIPTION
The M9306 is a 256 bit non-volatile sequential access memory manufactured using SGSTHOMSON FLOATING GATE process. It is a
peripheral memory designed for data storage
and/or timing and is accessed via a simple serial
interface.
The device contains 256 bits organized as 16 x 16.
The M9306 has been designed to meet application
requiring up to 10000 EIW cycles per word. Written information has at least 10 years data retention. A power down mode allows consumption to
be decreased.
PIN NAMES
CS
CHIP SELECT
SK
SERIAL DATA CLOCK
01
SERIAL DATA INPUT
DO
SERIAL DATA OUTPUT
Vce
POWER SUPPLY
GND
GROUND
June 1988
~
CS
1
8 ~ Vee
SK
2
7
~
Ne
01
3
6
~
Ne
DO
4
s
~GNo
S-6969
1/6
415
M9306
BLOCK DIAGRAM
00
DI--~~--r-r-----~----4
'--------------------1 INSTRUCTION
DECODE
CONTROL
AND
CS---r------~----------~
CLOCK
GENERATORS
SK-----------------1______~--------~~
5-697011
ABSOLUTE MAXIMUM RATINGS
Symbol
VI
Tamb
T stg
Parameter
Values
UnIt
Voltage Relative to GND
+6V to -0.3
V
Ambient Operating Temperature: standard
extended
Oto +70
-40 to +85
°C
°C
°C
Ambient Storage Temperature
-65 to + 125
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other cond"ions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (except for Tamb)
2/6
416
M9306
ELECTRICAL CHARACTERISTICS (O°C to + 70°C, for standard Temperature/- 40°C to + 85°C for
extended Temperature, VCC =5V::I:: 10% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min.
Typ.
4.5
Max.
Unit
5.5
V
Vcc
Operating Voltage
ICCl
Operating Current
Vcc=5.5V, CS=1
1.5
5
mA
ICC2
Standby Current
VcC=5.5V, CS=O
1.2
3
mA
ICC3
EIW Operating Current
Vcc=5.5V
6
rnA
VIL
Input Voltage Levels
2.0
VIH
VOL
2.5
-0.1
Output Voltage Levels
Vcc+1
0.4
IOL=2.1 rnA
IOH = - 400 pA.
VOH
0.8
2.4
V
V
pA.
ILl
Input Leakage Current
VIN=5.5V
10
ILO
Output Leakage Current
VOUT= 5.5V, CS=O
10
pA.
250'
kHz
75
%
SK Frequency
SK Duty Cycle
25
Input Set-Up and Hold
Times:
less
leSH
CS
tOIS
01
0.2
,.5
0
0.2
0.2
tOIH
tpOl
Output Delay
CL=100 pF
0.5
tpDO
DO
VOL=0.8V,
0.5
tEJW
Erase/Write Pulse Width
les
Min CS Low Time (Note 1) CL= 100 pF
,.5
VOH=2.0V
5
30
ms
1
,.5
• The maximum SK Frequency is 500 KHz when SK Duty Cycle is as 500/0
Note: 1. ·CS must be brought low for a minimum of 1,.5 (VcS> between consecutive instruction cycles.
3/6
417
M9306
FUNCTIONAL DESCRIPTION
The input and output pins are controlled by
separate serial formats. Seven 9-bit instruction can
be executed. The instruction format as a logical "1"
has a start bit, four bits as an op code, and four
bits of address. The on-chip programming voltage
generator allows the user to use a single power supply (Ved. The serial output (DO) pin is valid only
during the read mode. During all other modes the
DO pin is in high impedance state, eliminating bus
contention.
READ
The read instruction is the only instruction which
outputs serial data on the DO pin. After a READ
instruction is received, the instruction and address
are decoded, followed by data transfer from the memory register into a 16 bit serial out shift register.
A dummy bit (logical "0") preceds the 16 bit data
output string. The output data changes during the
high state of the system clock.
ERASEIWRITE ENABLE AND DISABLE
Programming must be preceded once by programming enable (EWEN) instruction. Programming remains enabled until a programming disable
(EWDS) instruction in executed. The programming
disable instruction is provided to protect against
accidental data disturbance.
Execution of a READ instruction is independent of
both EWEN and EWDS instructions.
ERASE
Like most EEPROMs, the register must first be erased (all bits set to 1s) before the register can
be written (certain bits set to Os). After an ERASE
instruction is input, CS is dropped low. This falling
edge of CS determines the start of programming.
The register at the address specified in the instruction is then set entirely to 1s. When the erase/write programming time (tEtw) constraint has been
satisfied, CS is brought up for at least one SK period. A new instruction may then be input, or a low
power standby state may be achieved by dropping
CS low.
WRITE
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. This
register must have been previously erased. Like
any programming mode, erase/write time is determined by the low state of CS following the instruction. The on chip high voltage section only
generates high voltage during this programming
mode, which prevents spurious programming during other modes. When CS rises to VIH, the programming cycles ends. All programming mode
should be ended with CS high for one SK period,
or followed by another instruction.
CHIP WRITE
Entire chip can be written for ease of testing. Writing the chip means that all registers in the memory array have each bytes set as the byte sent with
the instruction.
CHIP ERASE
Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in
the memory array have each bit set to a 1. Each
register is then ready for a WRITE instruction.
INSTRUCTION SET
4/6
418
Instruction
S8
REAO
WRITE
Data
Comments
Op Code
Address
1
10XX
A3A2A1AO
1
01XX
A3A2A1AO
ERASE
1
llXX
A3A2A1AO
Erase register A3A2A1AO
EWEN
1
0011
XXXX
Erase/write enable
EWOS
1
0000
XXXX
Erase/write disable
ERAL
1
0010
XXXX
Erase all registers
WRAL
1
0001
XXXX
Read register A3A2A1AO
015-00
015-00
Write register A3A2A 1AO
Write all registers
M9306
TIMING DIAGRAMS
5K
01
cs
00
5_697112
!
* THIS 15 THE
MAXIMUM 5K FREQUENCY
SK
CS
READ
j
\\..----
~------ ~------------
01
00
------'--------_1 ~
Jlsuuuuuu v-u-v li1..fl.IU1..JL..Jl.J1.
1J
SK
cs
WRITE
I I
s.
.Jl..J1.Jl..JUl~
cs
j
01
.....J.
I
I
I
~:...:t~--------
~~
01
ERASE
1
~':-':;
•
\
0
GX:.~
SK
EWEN
EWOS
'EAA$(IWRIT(
CS
[NABlE IDISABLE I
.
01
JUUUU""LIUL
SK
[RAt
(ERAS( ALL)
CS
01
~~~A~3~~A~2~~A~1~A~0~~~~
DON'T
CARE
~ SOle: ~r
________ --_,~~
,V-U-V"""
WRAL
~
~~~~D~15~~~~
5/6
419
M9306
ORDERING INFORMATION
Part Number
Max Frequency
Supply Voltage
Temp. Range
Package
M9306B1
M9306B6
250 KHz
250 KHz
5V±10%
5V±10%
0° to + 70°C
- 40° to + 85°C
DIP-8
DIP-8
M9306M1
M9306M6
250 KHz
250 KHz
5V±10%
5V±10%
OOto +70 0 C
-40° to +85°C
S08
S08
6/6
420
M145026/7/8
REMOTE CONTROL ENCODER/DECODER CIRCUITS
•
•
M145026 ENCODER
M145027/M145028 DECODERS
data (0, 1, open) to allow 3 9 (19,683) different
codes.
•
MAY BE ADDRESSED IN EITHER BINARY
OR TRINARY
•
TRINARY ADDRESSING
NUMBER OF CODES
•
INTERFACES WITH RF, ULTRASONIC, OR
INFRARED TRANSMISSION MEDIAS
•
DOUBLE TRANSMISSIONS FOR ERROR
CHECKING
•
ON-CHIP R/C OSCILLATOR, NO CRYSTAL
REQUIRED
Two decoders are presently available. Both use
the same transmitter - the M145026. The decoders will receive the 9-bit word and will interpret some of the bits as address codes and
some as data. The M145028 treats all nine bits
as address. If no errors are received, the M145027
outputs the four data bits when the transmitter
sends address codes that match that of the
receiver. A valid transmission output goes high
on both decoders when they recognize an address
that matches that of the decoder. Other receivers
can be produced with different address/data
ratios.
•
HIGH EXTERNAL COMPONENT TOLERANCE, CAN USE 5% COMPONENTS
All the devices are available in 16 lead plastic
package.
•
STANDARD CMOS B-SERIES INPUT AND
OUTPUT CHARACTERISTICS
•
APPLICATIONS INCLUDE GARAGE DOOR
OPENERS, REMOTE CONTROLLED TOYS,
SECURITY MONITORING, ANTITHEFT
SYSTEMS, LOW END DATA TRANSMISSIONS, WIRE LESS TELEPHONES
MAXIMIZES
• 4.5V TO 18V OPERATION
DIP-16 Plastic
(0.25)
The M145026 encodes nine bits of information
and serially transmits this information upon
receipt of a transmit enable, TE, (active low)
signal. Nine inputs may be encoded with trinary
ORDER CODE: M145026 B1
M145027 B1
M145028 B1
CONNECTION DIAGRAMS
Encoder
Decoder
~
AIIDI 1
16
Decoder
Voo
AI
I
IS
Voo
AI
I
IS
A2102
2
IS
DATA OUT
A2
2
15
OS
A2
2
IS
AS
AlI03
3
14
fE
A3
3
14
07
A3
3
14
A7
13
RTC
A4
4
ASI[)5 5
12
CTC
A5
5
A4104 "
114145026
MI45027
VOO
13
08
A4
,
13
AS
12
D9
A5
5
12
A"
MI45028
Afa/D6 6
"
RS
RI
S
"
VT
RI
S
"
VT
A7107
7
10
A9/09
CI
7
10
R2/C2
CI
7
10
R2/C2
VSS
8
Vss
8
"
DATA IN
VSS
8
"
DATA IN
A8108
5-111:1
June 1988
1/10
421
M145026-M145027-M145028
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage
Input Voltage, All Inputs
DC Current Drain Per Pin
Storage Temperature Range
Operating Temperature Range
-0.5
-0.5
to
to +18
V DO +0.5
10
V
V
mA
to +150
-40 to +85
-65
°C
°C
Stresses above those listed under" Absolute Maximum Ratings" may causes permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
SWITCHING CHARACTERISTICS
(CL = 50 pF, Tamb = 25°C)
Parameter
tTLH
tTHL
Output Hise and Fall Time
lTLH
lTHL
Data In Rise and Fall Time (M145027, M145028)
fCL
Encoder Clock Frequency
fCL
tWL
Min
Typ
Max
Unit
5
10
15
-
-
100
50
40
200
100
80
ns
-
-
15
15
15
IJS
-
2
5
5
MHz
kHz
5
10
15
-
-
5
10
15
0
0
0
-
Maximum Decoder Frequency
(Referenced to Encoder C!ock) (See Figure 9)
5
10
15
-
-
-
240
410
450
TE Pulse Width
5
10
15
65
30
20
-
-
-
-
-
-
182
-
-
-
±25
±25
System Propagation Delay
(TE to Valid Transmission)
Tolerance on Timing Components
(c.RTC + c.CTC + C.R 1 + c.C1)
(c.R2 +c.C2)
~2/~1~O_______________________ ~~~I;~~I~~~
422
VDD
-
-
-
-
ns
Clock
Cycles'
%
--------------------------
M145026 -M145027 - M145028
ELECTRICAL CHARACTERISTICS
Min
Typ
Max
Min
Max
"0" Level
5
'0
'5
-
-
0.05
0.05
0.05
-
0
0
0
0.05
0.05
0.05
-
0.05
0.05
0.05
.. , .. Level
5
'0
'5
4.95
9.95
'4.95
--
-
4.95
9.95
'4.95
5
'0
'5
-
4.95
9.95
14.95
-
V
"0" Level
5
10
15
-
-
1.5
3
4
-
2.25
4.50
6.25
1.5
3
4
-
1.5
3
4
V
.. , .. Level
5
10
15
3.5
7
11
-
3.5
7
11
2.75
5.50
8.25
-
3.5
7
11
-
V
5
5
-
-2.1
-0.44
-1.1
-3
-4.2
-0.88
-2.25
-8.8
-
-1.7
-0.36
-0.9
-2.4
-
rnA
15
-2.5
-0.52
-1.3
-3.6
5
10
15
0.52
1.3
3.6
0.44
1.1
3
0.88
2.25
8.8
-
0.36
0.9
2.4
5
10
15
-
-
3
16
35
4
20
45
7
26
55
-
-
15
-
±0.3
-
±0.00001
±0.3
-
±1.0
Input Current
Al/Dl-A9/D9 (M145026)
Al-A5 (M145027)
Al-A9 (M145028)
5
10
15
-
±80
±340
±725
-
5
7.5
Quiescent Current - M145026
5
10
15
-
±55
±300
±650
I nput Capacitance (V I = 0)
-
0.0050
0.0100
0.0150
0.10
0.20
0.30
--
30
60
90
50
100
150
--
100
200
300
200
400
600
-
200
400
600
400
800
1200
VI- 0 or VDD
VIL
Input Voltage
(Va = 4.5 or 0.5V)
(VO = 0.9 or lV)
(Va = 13.5 or 1.5V)
IOL
II
II
II
CI
IDD
IDD
IT
IT
Unit
Max
VOH
IOH
+85°C
Min
Output Voltage
VI= VDD or 0
VIH
25°C
V
VOL
I
_40°C
VDD
Parameter
(Va = 0.5 or 4.5V)
(VO= 1.00r 9V)
(Va = 1.5 or 13.5V)
Output Drive Current
(VOH = 2.5V)
(VOH = 4.6VI
(VOH - 9.5V)
(VOH = 13.5V)
Source
(VOL = O.4V)
(VOL = 0.5V)
(VOL = 1.5V)
S.ink
I nput Current
TE (M145026, Puilup Device)
Input Current
RS (M145026)
Data In (M145027, M145028)
Quiescent Current
M 145027, M 145028
'0
5
10
15
Total Supply Current
M145026 (fCL = 20 kHz)
5
10
15
Total Supply Current
M145027, M145028 (tCL = 20 kHz)
5
10
15
-
-
-
--
-
-
-
-
-
V
-
rnA
p.A
p.A
p.A
pF
p.A
p.A
--
p.A
-
p.A
------------- ~ ~~tm?~~lt ___________
--:3/_10
423
M145026 - M145027 - M145028
OPERATING CHARACTERISTICS
M145026
The encoder will serially transmit nine bits of trinary data as defined by the state of the A 1/D1-A9/D9
input pins. These pins can be in either of three states (0,1, open) allowing 3 9 = 19683 possible codes.
The transmit sequence will be initiated by a low level of the TE input pin. Each time the TE input is
forced low the encoder will output two identical data words. This redundant information is used by the
receiver to reduce errors. If the TE input is kept low, the encoder will continuously transmit the data
words. The transmitted words are self-completing (two words will be transmitted for each TE pUlse).
Each transmitted data bit is encoded into two data pulses. A logic zero will be encoded as two consecutive short pulses, a logic one by two consecutive long pulses, and an open as a long pulse followed by a
short pulse. The input state is determined by using a weak output device to try to force each input first
low, then high. If only a high state results from the two tests, the input is assumed to be hard wired to
Voo. If only a low state is obtained, the input is assumed to be hard wired to Vss. If both a high and a
low can be forced at an input, it is assumed to be open and is encoded as such.
The transmit sequence is enabled by a logic zero on the TE input. This input has an internal pullup device so that a simple switch may be used to force the input low. While TE is high the encoder is completely disabled, the oscillator is inhibited and the current drain is reduced to quiescent current. When TE
is brought low, the oscillator is started, and an internal reset is generated to initialize the transmit sequence. Each input is then sequentially selected and a determination is made as to input logic state. This
information is serially transmitted via the Data Out output pin.
M145027
The decoder will receive the serial data from the encoder, check it for errors and output data if valid.
The transmitted data consisting of two identical data words is examined bit by bit as it is received. The
first five bits are assumed to be address bits and must be encoded to match the address inputs at the
receiver. If the address bits match, the next four (data) bits are stored and compared to the last valid
data stored. If this data matches, the VT pin will go high on the 2nd rising edge of the 9th bit of the
first word. Between the two data words no signal is sent for three data bit times. As the second encoded
word is received, the address must again match, and if it does, the data bits are checked against th,e
previously stored data bits. If the two words of data (four bits each) match, the data is transferred to the
output data latches and will remain until new data replaces it. At the same time, the Valid Transmission
output pin is brought high and will remain high until an error is received or until no input signal is
received for four data bit times.
Although the address information is encoded in trinary fashion, the data information must be either a
one or a zero. A trinary (open) will be decoded as a logic one.
M145028
This receiver operates in the same manner as the M145027 except that nine address bits are used and no
data output is available. The Valid Transmission output is used to indicate that a valid signal has been
received.
Although address information normally is encoded in trinary, the designer should be aware that, for the
M145028, the ninth address bit (A9) must be either a one or a zero. This part, therefore, can accept only
2 x 3 8 = 13,122 different codes. A trinary (open) A9 will be interpreted as a logic 1. However if the
transmitter sends a trinary (or logic 1) and the receiver address is a logic 1 (or trinary) respectively, the
valid transmission output will be shortened to the R1 x C1 time constant.
DOUBLE TRANSMISSION DECODING
Although the encoder sends two words for error checking, a decoder does not necessarily wait for two
transmitted words to be received before issuing a valid transmission output. Refer to the flowcharts in
Figure 7 and 8.
~4/~1~O________________________ ~~~~~~&~~~
424
___________________________
M145026- M145027 - M145028
Fig. 1 - Encoder block diagram M145026
os
Al101
ATt
o--'---+-_+----1--f--+--+--+-+-+C>I----.
A2I020--'---+--+---1--f--+--+--+-f::=:::+----+
o..!.~Voo
A3I03o--'-+-_+----1--f--+--+---KC>I------..
~ss
8
A51D5 0--'---+--t----1--f-4::::""')If--------~-+-_+l
A6/0r.0--'---+--t----1--K"C>I-------------4
A7ID1o--'-+--+-K":>i---------------+
A8/08
O--"-+--1C>l-----------------+
A9/090-"'+::=:::+-------------------'
Fig. 2 - Decoder block diagram M145027
,.------------------------+-------.::..-0 ;~~~SMIS510N
06
07
4-BIT
SHIFT
REGISTER
08
09
A2~-_+--+_-_+-~~----~
A3
O-=---+-+----ic::: ;~--------+------'
1+-_-0._ _ _ _ _ _ _09 ~~TA
A4~~-f-~: ~*------------1
AS
5_6176
------------- ~ ~~tm&'19lt
5/10
425
M145026 - M145027 - M145028
Fig. 3 - Decoder block diagram M145028
SEQUENCER CIRCUIT
9
8
6
5
4
9-81T
SHIFT
REGISTER
+-__+-__+-__+-~
~.~s__
M-_~_.()9 DATA
IN
15
14
S_6111
PIN DESCRIPTION
M145026 ENCODER
Al/Dl-A9/D9
These inputs will be encoded and the data serially output from the encoder.
Vss
The most negative supply (usually ground).
RS, CTC, RTC
These pins are part of the oscillator section of the encoder. If an external signal source is used instead
of the internal oscillator it should be connected to the RS input and the RTC and CTC pins should be
left open.
TE
This Transmit-Enable (active low) input will initiate transmission when forced low. A pullup device will
keep this input high normally.
Data Out
This is the output of the encoder that will present the serially encoded signals.
Voo
The most positive supply.
M145027/M145028 DECODERS
A1-A5 (M145027) / Al-A9 (M145028)
These are the address inputs that must match the encoder inputs A liD l-A5/D5 in the case of M145027
or A 1/D1-AO/D9 in the case of M145028, in order for the decoder to output data.
426
M145026 - M145027- M145028
06-09 (M145027)
These outputs will give the information that is presented to the encoder inputs A6/D6-A9/D9.
Note: Only binary data will be acknowledged, a trinary open will be decoded as logic one.
Rl, Cl
These pins accept a resistor and capacitor that are used to determine whether a narrow pulse or a wide
pulse has been encoded. The time constant R1 x C1 should be set to 1.72 transmit clock periods.
R 1 C1 = 3.95 RTC x CTC.
R2/C2
This pin accepts a resistor to Vss and a capacitor to Vss that are used to detect both the end of an encoded word and the end of transmission. The time constant R2 x C2 should be 33.5 transmit clock
periods (four data bit periods). This time constant is used to determine that the Data In input has remained low for four data bit times (end of transmission). A separate comparator looks at a voltage equivalent two data bit times (004 R2C2) to detect the dead time between transmitted words.
R2C2 = 77 x RTC x CTC.
Valid Transmission, VT
This output will go high when the following conditions are satisfied:
1. the transmitted address matches the receiver address, and
2. the transmitted data matches the last valid data received (M145028 only).
VT will remain high until either a mismatch is received, or no input signal is received for four data data
bit times.
Voo
The most positive supply
Vss
The most negative supply (usually ground).
Figure 4 - Encoder Oscillator Information
This oscillator will operate at a frequency determined
by the external RC network; i.e ..
f
~
1
2.3 x RTC x CTC
(Hz)
for 1 kHz"'; f "';400 kHz
where: CTC = CTC
INTERNAL
ENABLE
+ C layout + 12 pF
RS "" 2 RTC
RS ;;. 20 k
RTC ;;'10 k
400 pF < CTC < !J.F
The value for RS should be chosen to be about 2 times RTC. This range will ensure that current through
RS is insignificant compared to current through RTC. The upper limit for RS must ensure that RS x 5 pF
(input capacitance) is small compared to RTC x CTC.
--------------------------- ~~~~~~g~l~~n ________________________~7/~lO
427
M145026-M145027 -M145028
For frequencies outside the indicated range, the formula will be less accurate. The actual oscillation
range of this circuit is from less than 1 Hz to over 1 MHz.
Figure 5 - Encoder/Decoder Timing Diagram
i'E
A
~145026 ENCODER
L-..J ____________________________________________________________________________
_ ...............
':!!'iI!:l!!!'21;::::::I~:t:lI:::;=~1it
;;!~!;;!~~Ea
2.:;;;'::::=:08:&
!~@i;;~;
~:,=ROSC'UA~.JU1MIlJ4~~JUWL[lIU1Il1U1t
,II BIT
I
r---l
I"
I
I
_ _ _, - - - ,r---"1u
9"'BIt
'.'1"
I
I
'I'
I
'I
I
JlfiI1IUl1lIl1l
,!hSIT
I
ur---"1un... ~~
,IIWORO
~:::...::;N::.~~~~SSIQN
~U'----JL-n
n
I
ZndWORQ
~~~I~,TII""'!oMI56ION.---------------'''='4:::50:::27:..:A:::N=-D.::"::::'450='8e,:DECO=DE=RS'---_ _ _ _ _ _ _ _- !
Figure 6 - Encoder Data Waveforms (M145026)
ENCODER
OSCILLATOR
(PINIZ)
DATA
OUT
(PINI5)
ENCODEO
··ONE"
U 1*
U 1*
ENCODED
"ZERO"
LJl'
n
U 1*
Lrl
ENCODED
··OPEN"
•_ _ _ _ _ _..J,
I.
u
L._ _ _ _ _ _.J
,--------'
DATA PULSE PERIOD
.1
DATA BIT PERIOD
n.
*150
PULSE APPEARS AT THIS POINT
(THIS DOES NOT AFFECT THE TRANSMITTER/RECEIVER OPERATION)
~8/~1~O
428
_______________________
~~~~~~~
__________________________
Figure 7 - M145027 Flowchart
Figure 8 - M145028 Flowchart
DlSAIl.t'lT
ON THEist
ADOAE:SS MISMATCH
AND IGNORf. THE
REST OF THIS WORD
~
~~
~'!'
~:i!
II
~S
DISABLE vr
ON THE'"
DATA MISMATCH
~z
:s::
....
.r:o.
g:
~
Q)
I
5.8112,
:s::
....
.r:o.
g:
~
.....
I
"..
...."'....
...,
o
co
:s::
....
.r:o.
g:
*FQR StUFf REGISTER COMPARlSONS ...··r .. ist.lored ua"'"
~
go
M145026 -M145027 -M145028
Figure 9 - M145027/M145028 (f max vs. C,ayout)
'rna.
(KHz)
MI45026
Clock
500
10
15
20
25
30
35
40
1,5
50
!l.
6'&31
C!ayOl.lt{pFIOn plnsl-5{M1450211: Pins 1·5 and12-15 {MI450281
Figure 10 - Typical Application
'00
'00
'00
"
"
5 .
M145027
M145026
0,
07
CTc'oCTC.ClaYQuh12pF
'OOpt:5CTC:S15~F
RTCi!:IOK~RS~2RT
o.
R,?:10K
09
R22:IOOK
C2;;::700pF
VT
fost~-'-
C,2:400pF"
2.3RTCCTC·
R,Ch].9SRTCCTC
R2C2:.77RTCCTC
ICTC'
= CTC + 20 pF)
Example RIC Values
(All Resistors and Capacitors are ± 5%)
fosc 1kHz)
RTC
CTC'
RS
R1
C1
R2
C2
362
181
88.7
42.6
21.5
8.53
1.71
10 k
10 k
10 k
10 k
10 k
10 k
50k
120pF
240pF
490pF
1020 pF
2020 pF
5100 pF
5100 pF
20 k
20 k
20 k
20 k
20 k
20 k
100 k
10 k
10 k
10 k
10 k
10 k
10 k
50k
470 pF
910pF
2000 pF
3900 pF
8200 pF
0.02,.F
0.02,.F
100 k
100 k
100 k
100 k
100 k
200 k
200k
910 pF
1800pF
3900 pF
7500 pF
0.015,.F
0.02,.F
0.1,.F
10/10
430
lifi !~I@m~:~lt -------------
TBA810CB
7W AUDIO AMPLIFIER
NOT FOR NEW DESIGN
•
HIGH OUTPUT POWER (7W AT 16V/4r2;
14.4V/2n)
•
HIGH OUTPUT CURRENT (3A REPETITIVE)
•
LOAD DUMP PROTECTION UP TO 40V
•
LOAD SHORT CIRCUIT PROTECTION UP
TO Vs = 15V
•
POLARITY INVERSION PROTECTION
•
THERMAL PROTECTION
The TBA810CB is a monolithic integrated circuit
in a 12-lead quad in-line plastic package, ex-
pressly designed for use as a power audio amplifier in CB radios.
Findip
ORDERING NUMBER: TBA810CB
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
(peak)
10
10
Ptot
Peak supply voltage (50ms)
DC supply voltage
Operating supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Power dissipation at Ta~b ..;; 80°C
at Ttab ..;; 90°C
Storage and junction temperature
40
28
20
V
V
V
4
3
A
1
5
-40 to 150
A
W
W
°c
TEST AND APPLICATION CIRCUIT
R3
C9
Q.l/,F
T T
T
C6
100/,F
15V
lOon
CB
·100~F
15V
Tabs
*C3.C7 SEE FIG.6
June 1988
1/3
431
TBA810CB
CONNECTION DIAGRAM
(Top view)
SUPPLY
VOLTAGE
12
OUTPUT
N.C.
11
N. C.
SCHEMATIC DIAGRAM
Q5~~------------------------~-----K
04
09
03
R5
12
R3
10
5-2202
THERMAL DATA
Rthj-tab
Rthj-amb
Thermal resistance junction-tab
Thermal resistance junction-ambeint
max
max
12
70*
• Obtained with tabs sOldered to printed circuit with minimized copper area.
:;!2/.::..3_ _ _ _ _ _ _ _ _ _ _ _
432
~ I~m&~©~
-------------
TBA810CB
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs
= 14.4V. Tamb = 25°C unless
otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
20
V
7.2
8
V
20
rnA
Vs
Supply voltage (pin 1)
Va
Quiescent output voltage
(pin 12)
Id
Quiescent drain current
12
Ib
Input bias current (pin 8)
0.4
p.A
Po
Output power
6
7
W
W
Vi(rms)
Input saturation voltage
VI
I nput sensitivity
4
6.4
d = 10%
RL = 40
RL = 20
f = 1 kHz
5.5
5.5
220
f = 1 kHz
Po =6W
R f = 560
Rf= 220
Po= 7W
Rf= 560
R f = 220
R L =40
I nput resistance (pin 8)
8
Frequency response
(-3 dB)
RL = 40/20
C3 = 820pF
C3 = 1500pF
Distortion
Po = 50 mW to 2.5W
RL = 40/20
f = 1 kHz
Gy
Voltage gain (open loop)
RL = 40
f = 1 kHz
Gy
Voltage gain (closed loop)
RL = 40/20
f = 1 kHz
eN.
I nput noise voltage
iN
Input noise current
11
Efficiency
SVR
Supply voltage rejection
__________________________
34
Vs= 16V
B (-3 dB) = 40 to 15 000 Hz
Po=6W
f = 1 kHz
75
30
mV
mV
55
20
mV
mV
5
MO
40 to 20 000
40 to 10000
Hz
Hz
0.3
%
80
dB
RL = 20
RI
d
mV
37
40
dB
2
p.V
80
pA
75
%
48
dB
RL=40
RL=40
V rlpPle= 1 V rms
fripple= 100 Hz
~~~~;~g,~~
40
________________________
3~/3
433
TBA810P
7W AUDIO AMPLIFIER
NOT FOR NEW DESIGN
The TBS810P is an improvement of TBA810S.
It offers:
Higher output power (R L = 4n and 2n)
Low noise
Polarity inversion protection
Fortuitous open ground protection
High· supply voltage reject.ion (40dB min.)
It gives high output current (up to 3A), high efficiency (75% at 60W output) very low harmonic
and crossover distortion. The circuit is provided
with a thermal limiting circuit and can withstand
a short-circuit on the load for supply voltages
up to 15V.
The TBA810P is a monolithic integrated circuit
in a 12-lead quad in-line plastic package, intended for use as a low frequency class Bamplifier.
Findip
The TBA810P provides 7W output power at
16V/4n; 7W at 14.4l2n.
ORDER CODE: TBA810P
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Power dissipation at Tamb ..;; 80°C
Ttab ";;90°C
Storage and junction temperature
20
V
4
3
A
A
1
5
W
W
-40 to 150
°c
TEST AND APPLICATION CIRCUIT
V
C9
o.ll'
F
R3
C6
',~OVF
100ll
C8
100~F
15V
R2
100kO
June 1988
1/3
435
TBA810P
CONNECTION DIAGRAM
(Top view)
SUPPLY
VOLTAGE
N.C.
N.C.
GROUND
GROUND
COMPENSATION
5
FEEDBACK
6
5-0289
SCHEMATIC DIAGRAM
DB
THERMAL DATA
RthJ~t.b
Rthj-amb
Thermal resistance junction-tab
Thermal resistance junction-ambient
• Obtained with tabs soldered to printed circuit with minimized copper area
436
max
max
12
70*
TBA810P
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs = 14.4V, Tamb = 25°C unless
otherwise specified)
Parameter
Test Conditions
Vs
Supply voltage (pin 1)
Vo
Qu iescent output voltage
(pin 2)
Id
Quiescent drain current
Ib
Input bias current
Po
Output power
VI (rmsl
Min.
6.4
d = 10%
RL = 4>2
RL = 2>2
5.5
5.5
20
V
7.2
8
V
12
20
mA
0.4
JJA
6
7
W
W
mV
220
I nput resistance (pin 8)
B
Frequency response
(-3d8)
RL = 4>2/2>2
C3 = 820pF
C3 = 150pF
Distortion
Po = 50mW to 2.5W
RL = 4>2/2>2
f = 1KHz
Gy
Voltage gain (open loop)
RL = 4>2
f = 1KHz
Gy
Voltage gain (closed loop)
RL = 4>2/2>2
f = 1KHz
eN
I nput noise voltage
iN
Input noise current
'11
Efficiency
Po = 6W
f = 1 KHz
RL = 4>2
SVR
Supply voltage rejection
RL = 4>2
f'lPPle = 10Hz
V,IPPle= lVrms
P,
Unit
f = 1KHz
I nput saturation voltage
Fig. 1 - Output power vs.
supply voltage
Max.
4
RI
d
Typ.
ptota
M>2
40 to 20,000
40 to 10,000
Hz
Hz
0.3
%
80
34
Vs = 16V
B (-3dB) = 40 to 15,000Hz
Fig. 2 - Maximum power
dissipation vs. supply voltage
(sine wave operation)
5
40
37
dB
40
dB
2
JJV
80
pA
75
%
48
dB
Fig. 3 - Value of C3 vs.
feedback resistance for various values of B
(W)
2ll
2Jl
4A
4ll
12
16
Vs (V)
12
437
TBA810S
7W AUDIO AMPLIFIER
NOT FOR NEW DESIGN
The TBA810S is a monolithic integrated circuit in a 12-lead quad in-line plastic package,
intended for use as a low frequency class B
amplifier.
tion. In addition, the circuit is provided with a
thermal protection circuit.
The TBA810A provides 7W power output at
16V/4U, 6W at 14.4V/4U, 2.5W at 9V/4U, 1W
at 6V /4U and works with a wide range of supply
voltage (4 to 20V); it gives high output current
(up to 2.5A). high efficiency (75%) at 6W output). very low harmonic and cross-over distor-
Findip
ORDERING NUMBER: TBA810S
ABSOLUTE MAXIMUM RATINGS
VS
10
10
Ptot
T stg' T j
Supply voltage
Output peak current (non-repetitive)
Output cu rrent (repetitive)
Power dissipation: at Tamb .;;;; 70 0 e
at T tab .;;;; 900 e
Storage and junction temperature
20
3.5
2.5
5
-40 to 150
V
A
A
W
W
°e
TEST AND APPLICATION CIRCUIT
R3
C9
O.1}JF
I I
C6
100}JF
15V
1000
C8
lGO}JF
15V
Vi
12
R2
IOOkQ
C3
1500pF
C7
June 1988
r
C2
l000iJF
15V
C4
O.1}JF
1/3
439
TBA810S
CONNECTION DIAGRAM
(Top view)
SUPPlY
VOLTAGE
N.C.
N.C.
GROUN~
BOOTSTRAP
9
COMPENSATION
8
GROUND
(SUBSTRATE)
INPUT
RIPPlE
REJECTION
FEEDBACK
5·0289
SCHEMATIC DIAGRAM
01
02
R10
R6
~kn
05
OS
07
.----,..--+-...,-~~Q13
O~
Rll
THERMAL DATA
Rth j-tab
Rth j"mb
max
max
Thermal resistance junction-tab
Thermal resistance junction-ambient
* Obtained with tabs soldered to printed circuit with minimized copper area.
~2/~3
__~____________________
440
~1~!;~~~
_________________________
TBA810S
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Tamb = 25 ec)
Parameter
Vs
Supply voltage (pin 1)
Vo
Quiescent output voltage (pin 12)
Id
Quiescent drain current
Ib
Bias current (pin 8)
Po
Power output
Vi(rms)
I nput voltage
Vi
I nput sensitivity
Ri
I nput resistance (p in 8)
B
Frequency response
(-3 dB)
Test conditions
Min.
Typ.
6.4
Vs = 14.4V
d - 10%
R L = 4,n
f = 1 kHz
V 5 = 16V
V 5 = 14.4V
V 5 = 9V
V 5 = 6V
5.5
Max.
V
7.2
8
V
12
20
Vs=14.4V
R L =4,n
C3 =820pF
C3=1500pF
mA
0.4
pA
7
6
2.5
1
W
W
W
W
220
Po =6W
Vs=14.4V
R L =4,n
f = 1kHz
R f = 56,n
R f = 22,n
Unit
20
4
mV
80
35
mV
mV
5
M,n
40 to 20,000
40 to 10,000
Hz
Hz
d
Oistorsion
Po = 50mW to 3W
Vs = 14.4V
R L =4,n
f = 1kHz
0.3
%
Gy
Voltage gain
(open loop)
Vs = 14.4V
R L =4,n
f =lkHz
80
dB
Gy
Voltage gain
(closed loop)
Vs = 14.4V
R L =4,n
f = 1kHz
34
37
40
dB
eN
I nput noise voltage
Vs=14.4V
Rg=O
B (-3 dB) = 20Hz to
20,000 Hz
2
)JV
iN
I nput noise current
Vs = 14.4V
B (-3 dB) = 20 Hz to
20,000 Hz
0.1
nA
1)
Efficiency
Po =5W
Vs = 14.4V
RL=4,n
f =lkHz
70
%
SVR
Supply voltage rejection
Vs=14.4V
R L =4,n
f ripple = 100 Hz
38
dB
441
TBA820M
MINIDIP 1.2W AUDIO AMPLIFIER
The TBA820M is a monolithic integrated audio
amplifier in a 8 lead dual in-line plastic package.
It is intended for use as low frequency class B
power amplifier with wide range of supply volt·
age: 3 to 16V, in portable radios, cassette reo
corders and players etc. Main features are:
minimum working supply voltage of 3V, low
quiescent current, low number of external com·
ponents, good ripple rejection, no cross-over
distortion, low power dissipation.
Output power: Po = 2W at 12V/8Q, 1.6W at
9V/4Q and 1.2W at 9V/8Q.
Minidip Plastic
ORDERING NUMBER: TBA820M
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current
Power dissipation at T amb = 50°C
Storage and junction temperature
Vs
10
Ptot
T stg , T j
16
V
A
W
1.5
1
-40 to 150
°C
TEST AND APPLICATION CIRCUITS
Fig. 1 - Circuit diagram with load connected to the
supply voltage
Fig. 2 - Circuit diagram with load connected
to ground
+Vso-------~--~~~----~-------,
+~o--------.----~~-----.
100,...F
C2
15VI
Vi
0----.------"1
5-369612
•
June 1988
Capacitor C6 must be used when high ripple
rejection is requested.
1/4
443
TBA820M
CONNECTION DIAGRAM
(top view)
FREQUENCY
COMPENSATION
RIPPLE
REJECTION
GAIN SETTING
BOOTSTRAP
INPUT
SUPPLY VOLTAGE
GROUND
5
OUTPUT
SCHEMATIC DIAGRAM
r-------~~------~~------~~~----_o7
6
~+_~--~----~--~=r+__+--~--~_o5
8
2
1
4
THERMAL DATA
Rth j_8mb
.
Thermal resistance junction-ambient
.::!2/~4_______________________ ~ !~~~m?v'l9lf
444
max
100
°e/W
-------------------------
TBA820M
ELECTRICAL CHARACTERISTICS (Refer to the test circuits Vs= 9V, T amb = 25°C unless
otherwise specified)
Parameter
Test conditions
Min.
Vs
Supply voltage
3
Vo
Quiescent output voltage (pin 5)
4
Id
Quiescent drain current
Ib
Bias current (pin 3)
Po
Output power
d= 10%
R f = 1200
Vs= 12V
Vs=9V
Vs=9V
Vs=6V
Vs= 3.5V
Typ.
Max.
Unit
16
V
4.5
5
V
4
12
mA
0.1
IJ.A
2
1.6
1.2
0.75
0.25
W
W
W
W
W
5
MO
f = 1 kHz
RL=SO
R L =40
RL=SO
R L =40
R L =40
0.9
Ri
Input resistance (pin 3)
f = 1 kHz
B
Frequency response (-3 dB)
RL=SO
Cs = 1000"F
R,= 1200
CB= 680pF
25 to 7,000
CB= 220 pF
25 to 20,000
Po= 500 mW
R L =80
f = 1 kHz
Rf=330
0.8
Rf= 1200
0.4
d
Distortion
Hz
%
Gy
Voltage gain (open loop)
f = 1 kHz
RL=SO
75
Gy
Voltage gain (closed loop)
RL=SO
Rf= 330
45
f = 1 kHz
Rf= 1200
34
dB
dB
eN
Input noise voltage (*)
3
IJ.V
iN
Input noise current (*)
0.4
nA
S+N
Signal to noise ratio ( * J
""""N
SVR
Supply voltage rejection
(test circuit of fig. 2)
Po= 1.2W
R L =80
G y = 34dB
R1= 10KO
SO
Rl= 50 kO
70
dB
R L =80
f (ripple) = 100 Hz
C6= 47IJ.F
Rf= 1200
42
dB
(-) B = 22 Hz to 22 KHz
------------- ~ 1~I;m~~Il-----------~3/4
445
TBA820M
Fig. 3 - Output power vs.
supply voltage
G-4068
Po
(W )
1.6
t- -
r-~L.4rt/
1.4
1.2
0.8
0.6
0.4
,1
I
0.2
d rT,-r,-r,,-',,-'~~
('/0)
12
/16Il
~~4~~~6
+-H-+--f--H-i
==I~f=120Q-1f-+-t-H++-I
I., kHz
f-,
H--t-.--H+-H
/11 /
i/
r--
--+--
8n
H-
t- - -
d=10o,.
r
f--
20
Rf ·120Il
Pto t
4
6
8
10
12
14
II
an
0.8
0.4
I
/
II
I
/
Q3
L.
11+
as
1.5
Po(W)
Fig. 8 - Frequency response
Fig. 7 - Suggested value of
CB vs. Rf
Gv"rITnm-',"~-'TTI~-T°nO~"m;~
(dB) H~itttlD.RfcO_''''20~n,(7,ttt--++HftjIt-+-HttffiI
/ 1-- r--
/
V
1'1
f 2 =10kHZ.-
ri
/f2.=~OkH:a
II /
/
CB=220p
-1
m
CB=680pF
\
-2
-3
II I
0.2
OA
1.2 ",,(W)
"n
RL,,4n
0.6
as
H-
o.a
04
16 Vs(V)
Fig. 6 - Maximum power dissipation (sine wave operation)
G-406911
(W )
(Wi
;
~
2
".
40
if=lKHZ
V
eo
pto.
"-B~t
s-9Y
f=lkHz,·
60
Ii
i V
Ifl I
Fig.5-Powerdissipation and
efficiency vs. output power
G-Olln
Fig.4 - Harmonic distortion
vs. output power
f-- t-
Ilh
[, ,
: I! II
1m
, .
1-
'0'
'0
12
Fig. 10
rejection
Fig. 9 - Harmonic distorti on vs. freq uency
-
RI(O)
Supply voltage
(Fig. 2 circuit)
-4
, ,
_5
10
..
~
10'
to'
10'
~
e8
f(Hz)
Fig. 11 - Quiescent current
vs. supply voltage
GOS5S)!
d
SVR
('/0)
(dB)
lis .9V
6=47.uF
100Hz
ripple
=
15
I
,
26
I-~~
1---C"
Ftt;;;
2
10
4/4
446
468
102
2'
468
10l
36
--c---+--2
468
10 4
2468
f (Hz)
Id (output transi~tors)
45
50
100
150
Gi
SCiS-THOMSON
':Ifl. ~n~IIJ@~~~©W.l@&Wn©$
RI(a)
12
16 Vs(V)
TCA3089
FM-IF RADIO SYSTEM
NOT FOR NEW DESIGN
•
HIGH LIMITING SENSITIVITY
•
HIGH AMR
•
HIGH RECOVERED AUDIO
•
GOOD CAPTURE RATIO
•
LOW DISTORTION
•
MUTING CAPABI LlTY
- AFC and delayed AGC for FM tuner
- Switching of stereo decoder
- Driver of a field strength meter
The TCA3089 can be used for FM-IF amplifier
application in Hi-Fi, car-radios and communication receivers.
The TCA30B9 is a monolithic integrated circuit
in a 16-lead dual in-line plastic package. It provides a complete subsystem for amplification
of FM signals.
DIP-16 Plastic
(0.25)
The functions incorporated are:
-
FM amplification and detection
Interchannel controlled muting
ORDERING NUMBER: TCA3089
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current (from pin 15)
Total power dissipation at T amb
Storage temperature
Operating temperature
16
V
mA
800
mW
-55 to 150°C
-25 to 70°C
2
';;;;;
70°C
TEST CIRCUIT
.12V
5kJl.
20nF
lNPUT©;--I
r
2.7kfi
~-C:=J--..--oAFC OUT
IOnF:r
.---'-_-'-_..1-_ _ _1.----1---,
10
~.~.J:
TeA 3089
56fi
~'~:J:
2.7kn
61-C::J-_-DAUOIO OUT
20
nF
AGC OUTPUT
*L tunes with l00pF at 10.7 MHz (00=75)
June 1988
FIELD STRENGTH
METER OUTPUT
5-2600/]
1/4
447
TCA3089
CONNECTION DIAGRAM
(top view)
IF INPUT
N.C.
BYPASS
AGC OUTPUT
BYPASS
GROUND
FIELD STRENGTH
METER
GROUND
MUTE INPUT
MUTE OUTPUT
AUDIOOUTPUT
SUPPLY VOLTAGE
AFC OUTPUT
RE.F.
QUAn OUTPUT
QUAD,INPUT
BIAS
5-0398/1
BLOCK DIAGRAM
~""'....J" I)-::CFl::CEL-jO"S;=:TR=E:CNG:::T~ ~;;;~~~D
METER OUTPUT
LOGIC CIRCUITS
THERMAL DATA
Rth j-amb,
2/4
448
Thermal resistance junction-ambient
max
100
°elW
TCA3089
ELECTRICAL CHARACTERISTICS
V5= OV,
(Refer to the test circuit; V,= 12V,fo=
10.7 MHz,
T amb = 25°C)
Parameter
Test conditions
DC CHARACTERISTICS
I,
Supply current
16
23
30
mA
Vi
Voltage at the IF amplifier
input
1.2
1.9
2.4
V
V 2 ,V3
Voltage at the input bypassing
1.2
1.9
2.4
V
V6
Voltage at the audio output
5
5.6
6
V
V lO
Reference bias Voltage
5
5.6
6
V
12
25
Il V
300
400
500
mV
200
350
500
mV
0.5
1
AC CHARACTERISTICS
Vi(thre'hOld) Input limiting voltage (-3 dB)
at pin 1
f m = 1 kHz
LIt= ± 75 kHz
Recovered audio voltage
Vo
(pin 6)
V7
Recovered aud io vo Itage
(pin 7)
d
Distortion
S+N
-N-
Signal to noise ratio
V i ;;> lOO IlV
f m = 1 kHz
LIt= ± 75 kHz
Vi;;> 1 mV
f m = 1 kHz
LIt= ± 75 kHz
V i =100mV
f m = 1 kHz
LIt = ± 75 kHz
m =0.3
%
60
67
dB
45
55
dB
10
mV
AMR
Amplitude modulation
rejection
Vi
Input vo Itage for delayed
AGC action (pin 1)
V 15
AGC output
V i =100mV
L\ 17
-/)-f
AFC control slope (note 1)
V i =10mV
1.2
~
V 13
Field strength meter output
sensitivity
Vi = 0.5 mV
1.5
V
No signal mute (note 2)
muting: ON
0.5
55
V
kHz
dB
VO@Vi;;> 100 IlV
2) No signal mute = 20 log - - - - - - - VO@Vi=O
3/4
449
TCA3089
Fig. 1 - Relative recovered
audio and noise output vs.
input voltage
~
{dB)
Fig. 3 - AGC (V I5 ) and
field strength meter output
(V 13) vs. input voltage 0."'"
Fig. 2 - Capture ratio vs.
input voltage
N
(dB)
~!~(OURE rl"TTllTTlr-,mnlrT1lTITlTI-'-TTTIll1rT'
(dB)
lLUlll1
V15 'V'3
H++tItM--Htftf~4fHftii-.
"V~=12V
".O:10"MHZ
61 =0
TambdS'(
!I
\Is
.]
~-u
~
"
'
"
=0',1
I i
WJJ
~
.. '
r-~i
'0'
'0'
10
10' Vi
(}lV)
Fig. 4 - AFC output current
vs. change in tuning fre·
quency
\Is
Fig. 5 - Amplitude modulation rejection vs. input
voltage
'"'r1~IJ]~f~~~~~~
".,
AFt
"
'0
='2\1
Vi =10mV
lamb =25·C
"'5 =0
60
JO
Fig. 6 - AMR vs. change in
tuning frequency
llAMR rc---r~'---'~"~T"T-,-~-F'
(dB)
Vs=12V
Tam b- 2S'C
·60
. t'~i'lk~~Z
.90
1If=!2SkHz
m= 0.3
,"'5- 0
~'20
-100
4/4
450
-60
-60
-40
-20
0
20
40
60
Sf (kHz)
10'
~ ~~~~m~fO!~lt
\1,(/.1\1)
7S,sf(kHz)
--------------
TCA3189
FM-IF HIGH QUALITY RADIO SYSTEM
•
EXCEPTIONAL
•
VERY LOW DISTORTION (0.1% - DOUBLE
TUNED DETECTOR COIL)
LIMITING
SENSITIVITY
•
IMPROVED SIN RATIO
•
EXTERNALLY PROGRAMMABLE AUDIO
LEVEL
•
DIRECT DRIVE OF FIELD STRENGTH
METER
The TCA3189 is a monolithic integrated circuit
in a 16-lead dual in-line plastic package, which
provides a complete subsystem for amplification
of 10.7MHz FM signal in Hi-Fi, car-radios and
communications receivers.
• ON CHANNE L STEP FOR SEARCH CONTROL
• PROGRAMMABLE AGC VOLTAGE AND
AFC FOR TUNER
•
INTERCHANNEL
MUTING
•
DEVIATION MUTING
DIP-16 Plastic
(0.25)
(SQUELCH)
ORDERING NUMBER: TCA3189
• DIRECT DRIVE OF TUNING METER
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current (from pin 15)
Total power dissipation at T amb
Storage temperature
Operating temperature
16
V
mA
800
mW
-55 to 150°C
-25 to 85°C
2
..;;
70°C
Double tuned detector coil
------l
3kll
I
fmi
W:
Vs··12V
22,uH
----
I
L.l
:
I
O.05,uF
I
IO~F
5kJl.
TCA 3189
TO
PIN1]
".
J.'• .l!!;
~
re.
:r
AUDIO
OUTPUT
470A
.-....
June 1988
1/4
451
TCA3189
CONNECTION DIAGRAM
(top view)
~
I F INPUT
[1
16
BYPASS
[2
15
BYPASS
[3
14
GROUND
[4
13
DELAYED
AGe CONTROL
DELAYED
AGC OUTPUT
GROUND
FIELD STRENGTH
METER
MUTE INPUT
12
MUTE OUTPUT
AUD I 0 OUTPUT
11
SUPPLY VOLTAGE
AFe OUTPUT
10
REF. BIAS
QUAD. OUTPUT
9 ~ QUAD. INPUT
5-3286
BLOCK DIAGRAM
SKll
Ir.:-====--Q ~~~~~~6~D
LOGIC CIRCUITS
5-3858
2/4
452
TCA3189
THERMAL DATA
Rth
j-amb
Thermal resistance junction-ambient
max.
100
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs = 12V, T amb = 25°C)
Parameter
Test cond itions
Min.
Typ.
Max.
Unit
16
V
Vs
Supply voltage range
9
Is
Supply current
20
31
44
mA
Vl
Voltage at the IF amplifier input
1.2
1.9
2.4
V
No signal input, non muted
V 2 , V3
Voltage at the input bypass
1.2.
1.9
2.4
V
V l5
Voltage at the pin 15 (RF AGC)
7.5
9.5
11
V
VlO
Reference bias voltage
5
5.6
6
V
Vi
Input limiting voltage (-3 dB)
at pin 1
12
25
IlV
500
650
mV
0.5
1
%
Vo
Recovered audio voltage (pin 6)
d
Distortion (single tuned)
d
Distortion (double tuned)
S+N
Signal to noise ratio
~
AMR
Amplitude modulation rejection
fo = 10.7 MHz
f m = 1 KHz
M= ± 75 KHz
Vi;;' 50 IlV
fo = 10.7 MHz
f m= 1 KHz
M= ± 75 KHz
325
Vi;;' 1 mV
fo = 10.7 MHz
f m = 1 KHz
M= ± 75 KHz
Vi = 100mV
fo = 10.7 MHz
fm = 1 KHz
M = ± 75 KHz
AM mod. 30%
0.1
%
65
72
dB
45
55
dB
V
V l6
RF AGC threshold
1.25
M-
Ll. 17
AFC control slope
1.9
V l2
On channel step (deviation mute)
__________________________
Il A
l
± 40 KHz
5.6
V
~~~~;~~~©~
______________________
~3~/4
453
TCA3189
TEST CIRCUIT
Fig. 1 - Single tuned detector coil
r-----...,
Vs·12V
Ill!
I
I
I
I
I
22,uH
8.2kll
L1
O.05,uF C"'
I
Fig. 3
Deviation mute
threshold vs. R7- 10
Fig. 2 - Limiting and noise
characteristics
Fig. 4 - Recovered audio
and muting action vs. input
level
dBr-~-r-'--~-r-'--r-,r~~
(kHz)
Vs=12V
t :1O.7MHz
AUOI
f m =lkHz
140
120
\
.00
-50
-1--+--+
-20 f-+----1/--j--+-+-+""V.-.'"'2""V
f-+--+-j--+-+-I ~~ ~O{~~~:I: t At. J: 15KHz
-40 f-+--Jf--j--+-+-+",Od",Bf-.so""'i0m",v,-+--+
\
.0
-, ':-~
-'0
'0
Wii'SE
-10
40
-'0
20
r-...
-90
10
10'
10'
'0'
Yj(,.,Yl
10
Fig. 5 - AFC characteristics
-'0
..
R1-10(ktl.)
)
Vs .. 12V
f
""0
Fig. 7 - Field strength and
tuning meter output vs.
input level
G-4103
Fig. 6 - AGC voltage for FM
tuner vs. input level
/
-50
4/4
454
'V )
'15" 1211
f .. l0.1MHz
/
V
-50
/
/
'Is" 12'1
1/
'50
-100
V. 3
'V)
/
••0 0
-IS 0
VIS
~10.7MH:t
"50
-'0
I---b/~-+-+-+--+--+-+-+-I
.0
G-4104
1
0 TPUT
(
/
f IIIO.7MHz
V
/
"
1 -~
.'
50
100 At(KHz)
Y
10
'0
V
V
TDA1151
MOTOR SPEED REGULATOR
•
EXCELLENT VERSATILITY IN USE
•
HIGH OUTPUT CURRENT (UP TO SOOmA)
•
LOW QUIESCENT CURRENT (1.7mA)
•
LOW REFERENCE VOLTAGE (1.2V)
•
EXCELLENT PARAMETERS STABILITY
VERSUS TEMPERATURE
as speed regulator for DC motors of record
players, tape and cassette recorders, movie
cameras, toys etc.
SOT-32
The TDAl151 is a monolithic integrated circuit
in SOT-32 plastic package. It is intended for use
ORDERING NUMBER: TDAl151
ABSOLUTE MAXIMUM RATINGS
V5
Ptot
T stg, T j
Supply voltage
Total power dissipation at T amb = 70°C
at T case = 100°C
Storage and junction temperature
20
O.S
5
-40 to 150
V
W
W
°C
APPLICATION CIRCUIT
M
10nF
TDA 1151
21--~~--4------l
5-2000
June 1988
1/6
455
TDA1151
CONNECTION DIAGRAM
lab
connected 10 pin 3
TEST CIRCUIT
lOA 1151
2 t---+----<~-{
3
5-1999
-'-2/_6_ _ _ _ _ _ _ _ _ _ _
456
~ ~~~~m~~l~~©~
------------
TDA1151
THERMAL DATA
Rth j-case
Thermal resistance junction-case
max
10
Rth j-amb
Thermal resistance junction-ambient
max
100
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, T amb =
Parameter
Test conditions
~
6V
IM~
O.lA
IM~
100 Ji,A
°C/W
°C/W
25°C)
Min.
Typ.
Max.
Unit
1.1
1.2
1.3
V
V ref
Reference voltage
(between pins 1 and 2)
Vs
Id
Quiescent drain current
Vs
~
6V
I MS
Starting current
Vs
~
5V
V l -3
Minimum supply voltage
IM~
K~IM/I'r
Reflection coefficient
Vs
~
6V
IM~
O.lA
~//',V
K
s
Vs
~
6V to 18V
IM~
O.lA
0.45
%!V
~//',IM
Vs
~
6V
25 to 400 mA
0.005
%/mA
Vs
~
6V
IM~O.lA
-20 to 70° C
0.02
%/oC
IM~O.lA
0.02
%!V
IM= 25 to 400 mA
0.009
%/mA
0.02
%/"C
K
~//',T
K
O.lA
/', V ref!V ref~ -50%
IM~
mA
0.8
A
/', V ref!V ref~ -5%
18
20
2.5
V
22
-
Tamb~
/',V ref //',V s
V ref
Line regulation
Vs
~
6V to 18V
/',V ref //',IM
V ref
Load regulation
Vs
~
6V
Temperature coefficient
Vs~ 6V
I M =O.lA
T amb= -20 to 70° C
/',V ref !/',T
V ref
1.7
---------------------------~~~~~~~~f~~~
________________________~3/_6
457
TDA1151
Fig. 2 - Quiescent drain
current vs. ambient temperature
Fig.
- Quiescent drain
current vs. power supply
I.
Fig. 3 - Reference voltage
vs. supply voltage
1.
(V)
lamb = 2
IjIjI'" O.lmA
'M = o.'mA
-
I.'
1.1
I'
1.6
I.'
16
VsIV)
(',-217,
,.
-'0
Fig. 4 - Reference voltage
vs. motor current
''''
(.,
104"
mA
10) iN .. 2OOmA
5) 1M .400mA
T
.. 25:<:
1.25
1.20
1.15
I.'
"
1
2) 1M" SOmA
l) 'M =100mA
I.
4.
Vsly)
Fig. 6 - Reflection coefficient vs. supply voltage
Fig. 5 - Reference voltage
vs. ambient temperature
".,.~
15
("
N"
lamb" 25"C
mA-
... 8V
V... 6'1
llV
• 18'1 - - - _
23
22
1.4
IM·4OOmA
1.25
21
13
1.20
I.,
1.15
"
"
1.1
...0
100
_20
'00
.
ZO
"
"
IDTamb('C)
'M
"
"
"
"
"
"
'0
I'
"
"
"
4/6
458
= 25m"
"SOmA
,.100m"
=200mA
,,400mA
100
'00
16
Vs(V)
Fig. 9 - Typical minimum
supply voltage vs. motor
current
Tamb·ZS-c
!!m._
Yr.f
"
2.
2.11
19
2.lI
.,
2.4
"
"
"
'-
"
(.,
'Is ,,6V
23
22
"
-
Fig. 8
Reflection coefficient vs. ambient temperature
Fig. 7 - Reflection coefficient vs. motor current
Z5mA
20
-2.
2.
4.
1.8
60 lamb ("C)
/iii
SGS-1HOMSON
=11... ~O©rnl@~ll.rn©'ii"OO@Ii:!O©®
100
200
... ...........
TDA1151
Fig. 10 - Application circuit
Vs = +9V
RM = 14.20
2800
RT
5-1995/1
1 ko
Rs
Eg
2.9V
1M - 150mA
V M = RM • 1M + Eg
= 5.03V
Note: A ceramic capacitor of 10 nF between pins, 1 and 2 improves stability in some applications.
Fig. 11 - P.C. board and component layout of the circuit of Fig. 10 (1 : 1 scale)
------------- ~ !~tm?e~ ____________
-'-'-"5/6
459
TDA1151
Fig. 12 - Speed variation vs.
supply voltage
Fig. 13 - Speed variation vs.
motor current
G·t110
Fig. 14 - Speed variation vs.
ambient temperature
~e_
"
(rpm)
("I.)
(rpm)
4i'("10)
Tamb"25'C
('10)
Vs ,,9V
Tam b,,2S'C
2200
'"
-,
2100
-10
1800
10
•
2100
2200
20'"
2000
2000
1800
1920
2000
•
12
16
Vs (V)
('pm'
Vs = + 9V
I ,,15OmA
1104 " 150mA
10
~fi~~~~~~~~~'~"'~"~t"
1960
100
'"
180
220
[M(rnA)
-20
20
'"
Fig. 15 - Low cost application circuit
Vs
RM
RT
Rs
Eg
1M
M
10nF
+12V
14.7n
290n
1 kn
2.65V
110mA
5-2000
Fig. 16 - Speed variation vs.
supply voltage
Fig. 18 - Speed variation vs.
ambient temperature
~
-A!L
(rpm)
("/.)
Fig. 17 - Speed variation vs.
motor current
0
(rpm)
Vs ",12V
(.,.)
T.. mb "'25"
~
..
(rpm)
("IJ
Tam b=25'C
Vs =12V
'M'" 110mA
1M ",nOmA
2200
>0
2200
>0
2200
2100
2100
2000
2000
2000
-,
'900
-,
'..,0
-,
1900
-10
1800
->0
1&00
-10
1800
"
460
50
100
150
1M (rnA)
20
'"
60
TDA1154
SPEED REGULATOR FOR DC MOTORS
•
MATCHING FLEXIBILITY TO MOTORS
WITH VARIOUS CHARACTERISTICS
•
BUILT-IN CURRENT LIMIT
•
ON-CHIP 1.2V REFERENCE VOLTAGE
•
STARTING CURRENT: 0.5A@2.5V
•
REFLECTION COEFFICIENT K = 20
The circuit offers an excellent speed regulation
with much higher power supply, temperature and
load variations than conventional circuits built
around discrete components.
Minidip
The TDA 1154 is a monolithic integrated circuit
intended for speed regulation of permanent
magnet dc motors used in record players, tape
recorders, cassette recorders and toys.
ORDER CODE: TDA1154
Fig. 1 - Application circuit
r---------------------------------------~r_------_ovcc
Motor
10 nF
5
3TDA1154a~----------~----------~------~==~
Vee = 12 V
Rm = 14.70
Rt
= 290 0
Rs = 1 kO (total)
Eg
= 2.65 V
1m _ = 110mA
3: Ground
5 : Referenc.
a: Output
Other pins are not connected
June 1988
1/4
461
TDA11S4
PIN CONNECTION
N.C.
N.C.
GNO
SUBSTRATE
D
2
7
3
6
"
5
OUTPUT
N.C.
N.C.
REFERENCE
I18SrOIUt54-B2
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Power dissipation
Junction temperature
Storage temperature range
20
1.2
(see curve)
+150
-55 to +150
V
A
W
°C
°C
Fig. 2 - Test circuit
f
V(refl
H81
THERMAL DATA
R th J- amb Thermal resistance junction-ambient
R th j-amb
Thermal resistance junction-pin 4
~2/~4________________________ ~~il;~~~~
462
max
max
100
70
°C/W
°C/W
--------------------------
TDA1154
ELECTRICAL CHARACTERISTICS T amb =
+25°C (Unless otherwise specified)
Min.
Typ.
Max.
Unit
1.15
1.25
1.35
V
-
0.02
-
%f°C
-
0.02
-
%/V
-
0.009
-
%/mA
2.5
-
-
V
Vee = +5V
1.2
-
-
Vee = +2.5V
0.5
O.B
-
Test Conditions
Paramater
V(ref)
Reference voltage
t,V(ref) /t,T
V(ref)
Reference voltage
temperature coefficient
Vee= +6V
1(8)= O.lA
Vee= +6V
1(81= O.lA
T amb = -200C to +70oC
t,V(ref) /t,V ee Line regulator
V(ref)
Vee= +4V to +lBV
I(B)= O.lA
t, V (ref) /t,I(B)
V(ref)
Load regulator
V (5 -3)
Minimum supply voltage
1(8)
Starting current«)
V~e=+6V
I( )= 25 to 400 mA
1(8)= O.lA
t,V(ref) = -5%
V(ref)
t,V(ref) = -50%
V(ref)
A
10 (5)
Quiescent current on pin 5
Vee= +6V
I(B)= 100ILA
-
1.7
-
K
K = t, 1(8)
t,1 (5)
Vee= +6V
1(8)= O.lA
lB
20
22
~/t,Vee
K spread versus Vee
Vee= +6V to +lBV
1(8)= O.lA
-
0.45
-
%/V
~/t,I(B)
K spread versus 1(8)
Vee= +6V
I(B)= 25 to 400 mA
-
0.005
-
%/mA
~/t,T
K spread versus temperature
Vee= +6V 1(8)= 0.1 A
T amb = +20°C to +70°C
-
0.02
-
%/oC
K
K
reflection
coefficient
K
mA
(*) An internal protection circuit reduces the current if the temperature of the junction increase: I(B)= 0.75A at
T J = +1400C.
'
OPERATING MODE
r----------------------------------.-----------------Ovcc
Fig.3
Vlraf)
AS
..
Motor
115J~
118)
1m
3 TDA1154 81'-'__..:::..________.....____:::
..~________.J
The circuit maintains a 1.2V constant reference
voltage between pins 5 and 8:
V(5 - 8)
=
V(ref)
= 1.2V
The current (1(5)) drawn by the circuit at pin 5 is
sum of two currents.
One is constant: 10 (5) = 1.7 rnA and the other is
proportional to pin 8 current (I (8)):
1(5)= 10 (5)+1(8) K(a)
(1 0 (5)= 1.7 rnA, K= 20)
------------- ~ ~~t;m~~~ ____________3=/4
463
TDA1154
If Eg and Rm are motor back electromotive force
and motor internal resistance respectively, then:
V~I)
Eg +Rmlm= Rt [1(5) +
] + V (ref) (b)
The motor speed will be independent of the resisting torque if Eg is also independent of 1m.
Therefore, in order to determine the value of Rt
term( 1) in (d) must be zero:
From figure 2 it is seen that:
1(8) = 1m + VR;f)
>
(c)
Substituting equations (a) and (c) into (b) yields:
Eg = 1m [
KRt - Rm
+
If Rt
KR m , an instability may occur as a result
of overcompensation.
The value of Rs is determined by term (2) in (d)
so as to obtain the back electromotive force
(Eg) corresponding to required motor speed:
V(rel)
(1 +1/K)
Rs = Rt -:::--':-:-'----=--:--:-=-:- -
Eg -
(1 )
+ V(rel)
[~
Rs
(1 +
~
~)
+ 1
K
+ Rtlo(5) (d)
v~---------------J
R
V(rel) -
Rtlo(5)
V (reI)
t Eg -
V(rel) -
Rt l o(5)
Where V(ref)= 1.2Vand 10 (5)= 1.7 mA
(2)
Fig. 4 - Application circuit
22ur
u'
4.7uF
4
82811
5
M
1kll
:r:
4.7uF
TDA
1154
1kll
8
n88T01l1154-81
""4/c..;4_ _ _ _ _ _ _ _ _ _ _ _
464
i8i 1~~;mg:l~~Jl -------------
TDA1220B
AM-FM QUALITY RADIO
The TDA1220B is a monolithic integrated circuit in a 16-lead dual in-line package.
It is intended for quality receivers produced in
large quantities.
The functions incorporated are:
AM SECTION
Preamplifier and double balanced mixer
One pin local oscillator
IF amplifier with internal AGC
Detector and audio preamplifier
Very low tweet
Very high signal handling (1 VI
Sensitivity regulation facility (*)
High recovered audio signal suited for stereo
decoders and radio recorders
Very simple DC switching of AM-FM
Low current drain
AFC facility
(*) Maximum AM sensitivity can be reduced by means
of a resistor (5to 12K!1) between pin 4and ground.
FM SECTION
IF amplifier and limiter
- Quadrature detector
- Audio preamplifier
DIP-16 Plastic
(0.25)
The TDA1220B is suitable up to 30MHz AM and
for FM bands (including 450KHz narrow band)
and features:
-
Very constant characteristics (3V to 16V)
High sensitivity and low noise
ORDERING NUMBER: TDA1220BK
BLOCK DIAGRAM
LOCAL
OSCILLATOR
RF AMPLIFIER
AND MIXER
16
1+1f---Q1O
14
June 1988
12
13
5- '3171
1/16
465
TDA1220B
ABSOLUTE MAXIMUM RATINGS
Vs
Ptot
Top
Tstg • lj
Supply voltage
Total power dissipation at Tamb < 110°C
Operating temperature
Storage and junction temperature
16
400
-20 to 85
-55 to 150
CONNECTION DIAGRAM
(Top view)
LOCAL
OSCILLATOR
AM INPUT
(
I
16
IF FM INPUT
I2
15
IF FM BYPASS
MIXER OUT
14
~ IF FM
AMPLIFIED
AGG (BYPASS) 4
13
FM
DETECTOR
AM IF INPUT
12
FM
DETECTOR
BYPASS
AM DETECTOR
BYPASS
6
11
GROUND
AM DETECTOR
7
10
'V s
AGC (BYPASS)
8
AF
OUTPUT
5-5165
THERMAL DATA
RthJ-amb
Thermal resistance junction-ambient
~2/~1~6_______________________ ~!i~~&~~~
466
max
100
________________ ________
~
TDA1220B
ELECTRICAL CHARACTERISTICS (T amb
25"C, V.
9V unless otherwise specified, refer
to test circuit)
V.
Supply voltage
Id
Drain current
AM SECTION (fo
VI
Max
16
V
FM
10
15
mA
AM
14
20
mA
1 MHz; fm
12
25
p.V
AGC range
Recovered audio signal
(pin 9)
d
Distortion
VH
Unit
= KHz)
Input sensitivitY
Vo
Min.
3
SIN
VI
Typ
Test conditions
Parameter
SIN = 26 dB
m =0.3
VI = 10mV
m =0.3
45
52
b.v out = 10dB
m =0.8
94
100
dB
130
200
mV
0.4
1.2
1
"10
"10
BO
dB
Vi= 1 mV
m= 0.3
VI = 1 mV
m =0.3
m =0.8
Max input signal handling
capability
m =O.B
d< 10%
RI
Input resistance between
pins 2 and 4
m=O
7.5
Kn
CI
Input capacitance between
pins 2 and 4
m =0
18
pF
Ro
Output resistance (pin 9)
Tweet 2 IF
Tweet 3 IF
FM SECTION (fa
4.5
m =0.3
V
1
Vi = 1 mV
7
9.5
Kn
40
dB
55
dB
= 10.7 MHz; fm = 1 KHz)
22
VI
Input liri1itin"g voltage
·3 dB limiting point
AMR
Amplitude modulation
rejection
b.t
= ± 22.5 KHz
VI = 3 mV
m =0.3
40
b.f = ± 22.5 KHz
b.f = ± 75 KHz
VI=l mV
55
36
p.V
dB
50
SIN
Ultimate quieting I
d
Distortion
d
Distortion
d
Distortion (double tuned)
Va
Recovered audio signal
(pin 9)
RI
Input resistance between
pin 16 and ground
6.5
Kn
CI
Input capacitance between
pin 16 and ground
14
pF
Ro
Output resistance (pin 9)
b.f = ± 22.5 KHz
VI=l mV
Vi=l mV
dB
65
0.7
1.5
"10
0.25
0.5
"10
140
mV
0.1
b.f = ± 22.5 KHz
VI = 1 mV
BO
4.5
110
7
"10
9.5
Kn
------------ ~ l~t;R'~lf ___________-=3/~16
467
TDA1220B
Fig. 1 - Test circuit
'O.7MHz
fM It.
lorF
R.
68 n
TDA 1220 B
'---f---OAFC OUT
C3
12
R3
13
330n
tH
: d4
C 4 t:2:-:0~n>::F-~~""'"
AM3(1O,1O)
r-------,
3
2
'('-2)57 turns
(2-3)116 tlSTlS
(4-6) 24turns
I
I
,
'0.70
,
" --------,'
r
I
,
I
I
I
5-5367/2
~~~----------~o
L ______ ~
FM AM
TOIIO KACS KS86 HM
Fig. 2 - PC board and component layout (1: 1 scale) of the test circuit .
...;4/'-1_6_ _ _ _ _ _ _ _ _ _ _ _
468
~ ~~~~m~:l9Jl-------------,---
TDA1220B
Fig. 3· Audio output, noise
and tweet levels vs. input si·
gnal (AM section)
Fig. 4 . Distortion vs input
signal and modulation index
(AM section)
o
(dB)
('J.)
_
Fig. 5 . Audio output vs.
supply voltage (AM section)
'. r-r-r-Ir-r-r-r-r-r-~~T-o
f-710-,;.,t:..H;:-,t-t-t-t-t-t-+-+-H
(mVl
~:~KjZ I-f-f-f-t--t--t--t--H
Vo
·10
'"
.20
v
120
.>l
...0
~
·so
~
i/
lit- r--
.,.
-60
Vs~9Y
fo:1MH:I!
f"",IKHz
WEETa..,,..,....
"r-
~SE
1'-
f-
r-r-
m"o.3
mo"
"
Fig. 6 . Audio output and
noise level vs. input signal
(FM section)
G-5015
G·5077
("/.)
~r-
Y'"lO mV/
1/
NOSE
_ "s =9'1
'o=lOJMl-Iz
60
_1m=lKHz
I
j6.f:t22.5KHZ
10'
0'
105VI(~)
Fig. 9 . Amplitude modu·
lation rejection vs. input sig·
nal (FM section)
,-v-""T1T1TmrTIlTlTm"-"r'iii-iTIi
(dB) rTTTTITlT"",-.
lo=lo.7ht-1z
"",1KHz
:f:~;2.5KH:I! f+HfIIII-+l+++llH+t+1tIII
..
"
t:.f=t22.SKHz
'"
50
VK'..o v
80
80
60
120
1\
50
70
r- ~~~!~\KHZ I--I--I--f-f-f-f-H
fm=IKHz
-.,
"
60
'O=10.7MHz
'o=IO·7MHz
/
10
(mY)
11111111
Vo
30
'0
d
dB
Fig. 8 . Audio output vs.
supply voltage (FM section)
Fig. 7 . Distortion vs. input
signal (FM section)
10'
Fig. 10 . bDC output volt·
age (pin. 9) vs. frequency
shift (FM section)
Fig. 11 ·bDCoutput voltage
(pin 9) vs. ambient tempe·
tature (FM section)
v, "''''r\.""T""T""T""T""T""T""T""T-T'I''T'-o
6V p l n
(mv'I--I-""f-I--f-f-t--+..y-,"'.''"vJ_+-+-l
(mV)
400f-t-P-<-+-+-+-+-+-+-+-I
OR
"5· 4 . 5V
200
100
"
-100
JO
20
10
- 200 I-t--t--t--t--t--t-+"\..>,q--+-+-+-+
10 YsNl
f-
f- ......
_V
f-200
-4ool--l--f-f-f-f-f-f-t---i><-+--H
-600 '-'-'-'-'--'-'--'--'--L-1.."\....1.-l
-120
-80
-40
40
80 6t(KHz)
---------------------------~I~~~~'~~
-30 -20 -10
a
10
20
30
40
50 lambC"C)
________________________
~S~/1~6
469
TDA1220B
APPLICATION INFORMATION
AM Section
RF Amplifier and mixer stages
The RF amplifier stage (pin 2) is connected directly to the secondary winding of the ferrite rod antenna
or input tuned circuit. Bias is provided at pin 4 which must be adequately decoupled. The RF amplifier
provides stable performance extending beyond 30 MHz.
The Mixer employed is a double - balanced multiplier and the IF'output at pin 3 is connected directly to
the I F filter coil.
Local oscillator
The local oscillator is a cross coupled differential stage which oscillates at the frequency determined by
the load on pin 1.
The oscillator resonant circuit is transformer coupled to pin 1 to improve the Q factor and frequency
stability.
The oscillator level at pin 1 is about 100 mV rms and the performance extends beyond 30 MHz, however
to enhance the stability and reduce to a minimum pulling effects of the AGC operation or supply voltage
variations, a high C/l ratio should be used above 10 MHz.
An external oscillator can be injected at pin 1. The level should be 50 mV rms and pin 1 should be connected to the supply via a 1000 resistor.
IF Amplifier Detector
The IF amplifier is a wide band amplifier with a tuned output stage.
The IF filters can be either lC or mixed lC/ceramic.
AM detection occurs at pin 7. A detection capacitor is connected to pin 6 to reduce the radiation of
spurious detector products.
The Audio output is at pin 9 (for either AM or FM); the IF frequency is filtered by an external capacitor
which is also used as the FM mono de-enp'hasis network. The audio output impedance is about 7 Kn and
a high impedance load (- 50Kn) must be used.
AGe
Automatic gain control operates in two ways.
With weak signals it acts on the IF gain, maintaining the maximum SIN. For strong signals a second circuit intervenes which controls the entire chain and allows signal handling in excess of one volt (m =0.8).
At pin 8 there is a carrier envelope signal which is filtered by an external capacitor to remove the .Audio
and RF content and obtain a mean DC signal to drive the AGC circuit .
...;,;6/...;,;1..:.,.6_ _ _ _ _ _ _...,--_ _ _
470
~ ~~tmg,,~ol£
------------
TDA1220B
APPLICATION INFORMATION (continued)
FM Section
I F Amplifier and limiter
The 10.7 MHz IF signal from the ceramic filter is amplified and limited by a chain of four differential
stages.
Pin 16 is the amplifier input and has a typical input impedance of 6.5 Kn in parallel with 14 pF at
10.7 MHz.
Bias for the first stage is available at pin 14 and provides 100% DC feedback for stable operating conditions. Pin 15 is the second input to the amplifier and is decoupled to pin 14, which is grounded by a
20 nF capacitor.
An RLC network is connected to the amplifier output and gives a 90° phase shift (at the IF centre
frequency) between pins 13 and 12. The signal level at pin 13 is about 150 mV rms.
FM Detector
The circuit uses a quadrature detector and the choise of component values is determined by the acceptable level of distortion at a given recovered audio level.
With a double tuned network the linearity improves (distortion is reduced) and the phase shift can be
optimized; however this leads to a reduction in the level of the recovered audio. A satisfactory compromise for most FM receiver applications is shown in the test circuit.
Care should be taken with the physical layout.
The main recommandations are:
• Locate the phase shift coil as near as possible to pin 13.
• Shunt pins 14 and 16 with a low value resistor (between 56n and 330n).
• Ground the decoupling capacitor of pin 14 and the 10.7 MHz input filter at the same point.
AM-FM Switching
AM-FM switching is achieved by applying a DC voltage at pin 13, to switch the internal reference.
Typical DC voltages (refer to the test circuit)
Pins
1
AM
FM
2
3
4
9
1.4
9
1.4
9
0.02
9
0.02
5
6
7
8
9
10
11
12
13
14
15
16
Unit
1.4
8.4
9
0.7
1.9
9
0
0.1
0.1
8.5
8.5
8.5
V
0.02
8.5
9
0
1.7
9
0
9
9
8
8
8
V
___________________________
~~~~~?~~~~
________________________
~7/~1~6
471
TDA1220B
APPLICATION SUGGESTION
Reccomended values are referred to the test circuit of Fig. 2
Part
number
Recommended
value
Cl
100,uF
Purpose
AGC bypass
C2 (*)
100 nF
AM input
DC cut
C3 (*)
10nF
FM input
DC cut
Smaller than
recommended value
Increase of the
distortion at low audio
frequency
Increase of the AGC
time constant
Reduction of
sensitivity
- Bandwidth increase
- Higher noise
IF bandwidth increase
20 nF
20 nF
FM amplifier bypass
C6
68 pF
Ceramic filter coupling
I F bandwidth reduction
C7
100 nF
FM detector decoupling
Danger of RF irradiation
C4
C5
Larger than
recommended value
C8
100 nF
Power supply bypass
Noise increase of the
audio output
C9
10,uF
AGC bypass
Increase of the
distortion at low audio
frequency
Cl0(*)
56 pF
Tuning of the AM
oscillator at 1455 KHz
Cll
6.8nF
50,us
FM de·enphasis
C12
100 nF
Output DC
decoupling
Low audio
frequency cut
Increase of the AGC .
time constant
C13
220,uF
Power supply
decoupling
Increase of the distortion
at low frequency
C16
2.7 nF
AM detector
capacitor
Low suppression of the
I F frequency and
harmonics
Increase of the audio
distortion
Rl (*)
68 ohm
FM input matching
R2 (*)
56 ohm
AM input matching
Ceramic filter matching
FM detector
coil Q setting
Audio output decrease
and lower distortion
Audio output increase
and higher distortion
R3
330 ohm
R4
8.2 Kohm
R5
560 ohm
FM detector
load resistor
Audio output decrease
and higher AMR
R6
82 Kohm
AM detector
coil Q setting
Lower I F gain and
Lower AGC range
R7
2.2 Kohm
455 KHz IF filter
matching
R8
3.3 Kohm
Higher IF gain and
lower AGC range
455 KHz IF filter
matching
(*) Only for test circuit
~8/~1~6_______________________ ~~~I;~~~~
472
--------------------------
"T1
l>
~
cpO
-g
0
;:l.
-I
Ci)
0
'"c-
~+3"2V'
C5 to C12
-
TOtIO
4nl
I
1-'-- - - - --~
I
1
1
I
I
~
~fn
s:
-..
"T1
s:
....
~
l>
Z
Z
"T1
0
:::D
o· S
~
0
Z
n0
...
::::t
1
1
:5'
I
c:
C1)
3;
1
1
1
L 1 - 6 Turns copper wire 0.9 mm diameter.
Inner diameter 4 mm, Winding pitch 1 mm.
L2 - 5 Turns copper wire 0.9 mm diameter.
Inner diameter 4 mm, Winding pitch 0.5 mm
L3 - 4 Turns copper wire 0.9 mm diameter.
Inner diameter 4 mm. Winding pitch 2 mm.
L4 - 18 Turns copper wire 0.6 mm diameter.
Inner diameter 2.5 mm. Closely wound.
IL __________ ,. __________________ _
I
I
FM
ANTENNA
I
I
I
I
L __
L1
Rl1
XXln
5-6154
-I
~
.....
~
....
w
!~
,...
en
I\)
I\)
o
m
TDA1220B
APPLICATION INFORMATION (continued)
Fig. 13 . PC board and component layout of the fig. 12 1: 1 scale
_10...:.'_16_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~m~~©~
474
-------------
TDA1220B
APPLICATION INFORMATION (continued)
F1 - 10.7 MHz IF Coil
~:s:«'
.co
(pF)
t--
f
(MHz)
-
(D!)I~
-
TURNS
00
1-3
1-2
2-3
4-6
10.7
110
6
8
2
f
ClkHz)
00
TOKO - FMl -10xl0mm.
154 AN -7A5965R
F3 and f5 - 455 KHz IF Coil
-
Co
(pF)
1-3
180
455
'TURNS
1-3
1-2
2-3
4-6
70
57
116
24
TOKO - AM3 - 10xl0 mm.
R LC - 4A 7525N
F4 - FM Detector Coil
'.'.
CD
~®
®
1 ..
Co
f
~ (MHz)
1-3
82
10.7
TURNS
00
1-3
1-3
100
12
-
-
TOKO - 10xl0 mm.
KACS - K586 HM
-
F6 - Allil Oscillator Coil
lE:
I
f
(kHz)
L
litH)
00
1-3
1-3
1-2
2-3
4-6
220
80
2
75
8
L
(IlH)
00
1-2
1-2
TURNS
.
6
796
TOKO -10xl0 mm
RWO + 6A6574N
L5 - Antenna Coil
f
(KHz)
796
TURNS
1-2
3-4
105
7
WIRE: LlTZ - 15xO.05 mm.
CORE: 10x80 mm.
'$-6161
--------------Iifi.I~t~m?1rt~lt
___________
---'1""1'-'/1;..:.6
475
TDA1220B
APPLICATION INFORMATION (continued)
Typical performance of the radio receiver of fig.12(V s = 9V)
Parameter
WAVEBANDS
SENSITIVITY
DISTORTION
(fm = 1KHz)
FM
87.5 to 108 MHz
AM
510 to 1620 KHz
FM
SIN
AM
SIN
AM
SIN
FM
= 26dB
= 6dB
= 26dB
Po
= 0.5W
Vi
= 100"V
Po
VI
= 0.5W
= 100"V
= 0.5W
= 1 mV
Vi
= 100 "V
f---
AM
FM
SIGNAL TO NOISE
(fm = 1KHz)
Value
Test Conditions
VI
Po
AM
= 22.5KHz
= 0.3
m = 0.3
I::.f = 22.5KHz
I::.f = 75KHz
m = 0.3
m = 0,8
I::.f
1"V
m
1"V
.
10"V
0.25%
0,7%
0.4%
0,8%
I::.f
= 22.5KHz
64dB
m
= 0.3
50dB
AMPLITUDE
MODULATION
FM
ill = 22.5KHz
m
= 0.3
50dB
REJECTION
TWEET
2nd H.
f
= 911KHz
0.3%
3rd H.
f
=' 1370 KHz
0.07%
QUIESCENT CURRENT
SUPPLY VOLTAGE RANGE
~12~/~16~_____________________ ~!~~~~~~
476
20mA
3 to 12V
__________________________
TDA1220B
APPLICATION INFORMATION (continued)
Fig. 14 - Low cost 27 MHz receiver
33ft
+3-:-12\1
R3
0.11"
l--r-----,--IJcm--o ~~IO
11~-~---r---.
5-610:;6
:
i
Fig. 15 - L2 Oscillator coil
i
Fig. 16 - L 1 Antenna Coil
I i---
eooo I
eooo
eooo I
j---
I
I:
I
(0)
eooo
eooo
I
L;_;;;;,
I'
I:I:
I
Coil support: Taka 10K
Primary winding: 10 Turns of enamelled copper wire 0.16 mm diameter (pins 3-1).
Secondary winding: 4 Turns copper wire
0.16 mm diameter (pins 6-4)
-~':-3:'8
Coil support: Taka 10K.
Primary winding: as L2 (pins 3-1)
Secondary winding: 2 Turns copper wire
0.16 mm diameter (pins 6-4)
Fig. 17 - Low cost 27 MHz receiver with external xtal oscillator
MURATA CF2 455F
33ft
+3712v
R3
A4
lOOA
FROM
EXT. OSCILLATOR
(50 +100 mVrms )
TOA 1220 B
16
111--~---'---.
14
15
------------- ~ ~~i~R'£~SJJnI ___________-=.1~3/~16
477
TDA1220B
APPLICATION INFORMATION (continued)
Fig. 18 - 455 KHz FM narrow band IF
.6Y
15A
l1 =TOKO DAM 320
ll=TOKO DAM 320
L3 0: TOKO OAN 120
L4 a TOKO COil FORM 7PA - 200 TURNS pli 0.08
Fig. 19 - P.C. board and component layout of the circuit of fig. 18
INPUT
478
TDA1220B
APPLICATION INFORMATION
(continued)
Fig. 20 - Discriminator "5" curve response (circuit of fig. 18)
20 mV/div
I
Fig. 21 -' Application in sound channel of multistandard TV or in parallel AM modulated sound channel
(AM section only).
,----,------,-----"4---<>.12V
39MHz
AM IN
15pF
cAM
L2.L
B
!
3
.
I
!
L1B
Coil form: Taka 10K
N° of Turns: 5 of enamelled
copper wire
-g
Fig, 3 - Portable AM/FM radio
-g
r-
(")
l>
:j
0
z
-----------------------,
, •• ,
.of!
SWl
R22
+~,5V
c:::t
15a
C5 to C12
TOKO
Z
'TI
0
::tI
S
CY2-2212t.FT
l>
-I
0
Z
~
41
:
Itt:
~FI
~g
I
,l..... _ _ _ _ _ _ _ _ _ _ _ _ _ JI
I
~'"
il
i:lz
I
IFNI
L __________ ,. __________________ _
R19
lMfi
I
FM
ANTENNA
I
I
I
,IL __
:tOt''''
f"
r
,C31
u
I~'
I 0.1 ~F
Ll - 6
TURNS COPPER WIRE
0.9
11M DIAMETER.
INNER DIAMETER 4 11M. WINDING PITCH 1 MM.
TURNS COPPER WIRE 0.9 "'" DIAMETER.
INNER DIAMETER q MK. WINDING PITCH 0.5 MM.
l3 - 4 TURNS COPPER WIRE 0.9 "'''' DIAMETER.
INNER DIAMETER 4 MM. WINDING PITCH 2 MM.
l" - 18 TURNS COPPER WIRE 0.6 MI"I DIAM£TER.
INNER DIAMETER 2.5 MM. CLOSELY WOUND.
L2 - 5
L1
RI1
lOOIl.
:;- 6159
-t
....g
N
N
0
r-
TDA1220L
APPLICATION INFORMATION
Fig. 4 - PC board and component layout of the circuit of fig. 3. (1: 1 scale)
487
TDA1220L
APPLICATION INFORMATION (continued)
F1 - 10.7 MHz IF Coil
~.
2 :
4
I
1
Co
(pF)
f
(MHz)
-
10.7
Co
(pF)
f
(KHz)
6
I
TURNS
00
1-3
1-2
2-3
4-6
1.05
6
8
2
TaKa - FMl - 7x7 mm.
119 AN - A5066R
F3 - 455 KHz I F Coil
.4
~
2
1
I
1-3
I
6
180
455
TURNS
00
1"---1-3
1-2
2-3
4-6
70
63
81
7
TaKa - AMI - 7x7 mm.
7LC - A5070EK
F4 - FM Detector Coil
@
~
1
@
Co·
(pF)
f
1-3
1-3
-
-
10.7
100
12
-
-
f
00
1-3
®
TURNS
00
I - - - (MHz)
82
TaKa - 10xl0 mm.
KACS - K586 HM
F5 - 455 KHz I F Coil
Co
(pF)
TURNS
I--'-- (KHz)
1-3
180
1-3
1-2
2-3
4-6
455
70
41
103
20
L
(,uH)
00
1-3
1-3
1-2
2-3
4-6
320
80
90
3
9
L
II.H)
00
1-2
1-2
TOKO - AM3 - 7x7 mm.
7 LC - A5073 EK
F6 - AM Oscillator Coil
~i~
@-51~
f
(KHz)
796
TURNS
TaKa - OAM320 - 7x7 mm.
780 - A5071 DC
L5 - Antenna Coil
f
(KHz)
5 - 6162
796
TURNS
1-2
3-4
105
7
~8/'..!!.8~_ _ _ _ _ _ _ _ _ _ ~ I~tm?elt
488
WIRE: LlTZ -10xO.05 mm.
CORE: 10x80 mm.
------------
TDA1904
4W AUDIO AMPLIFIER
•
frequency power amplifier in wide range of applications in portable radio and TV sets.
HIGH OUTPUT CURRENT CAPABILITY
(UP TO 2A)
• PROTECTION AGAINST CHIP OVERTEMPERATURE
•
LOW NOISE
•
HIGH SUPPLY VOLTAGE REJECTION
Powerdip
(8 + 8)
• SUPPLY VOLTAGE RANGE: 4V TO 20V
The TDA 1904 is a monolithic integrated circuit
in POWERDIP package intended for use as low-
ORDERING NUMBER: TDA 1904
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Peak output current (non repetitive)
Peak output cu rrent (repetitive
Total power dissipation at Tamb = 80°C
at T pins = 60°C
Storage and junction temperature
20
2.5
2
1
6
-40 to 150
V
A
A
W
W
°c
TEST AND APPLICATION CIRCUIT
C7
(.) R4 is necessary only for Vs
June 1988
lO00~F
< 6V.
1/8
489
TDA1904
CONNECTION DIAGRAM
(top view)
.'-J
OUTPUT
16
~GNO
15
~ GND
BOOTSTRAP
3
14
~GND
N.C
4
13
~ GND
12
GNO
11
GND
N.c
INVERT. IN
6
SVR
10 GND
9
GND
5-5291
SCHEMATIC DIAGRAM
~
220llj An
A3
~~
~
2Skfi
d
b
Ql
.......Q12
Q13
1(xikll
>-t( Q2
lCOkfi
RS
',",Cl4
RS
~
Q~
A7
A9
liIOKA
10KA
r---'
01"~
:~SOpF
Rl
R4
Skfi
....-'Q7
'"
kQ3
K~
02
A8
05
06
Qn........
Q8
~
Q9
QS?-
R2
*
03
=~Cl ~
........014
Ql0
RIO
S_529J
7
8
91
.'6
( 6
THERMAL DATA
Rth j-case
Rth j-amb
~2/_8
Thermal resistance junction-pins
Thermal resistance junction-ambient
________________________
490
~1~~~~
max
max
15
70
°C/W
°C/W
__________________________
TDA1904
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Rth (heatsink) =
20"C/W, unless otherwise specified)
Parameter
Test conditions
Min.
Typ.
Vs
Supply voltage
Vo
Qu iescent output voltage
Vs =.4V
Vs= 14V
2.1
7.2
Id
Quiescent drain current
Vs=9V
Vs = 14V
8
10
Po
Output power
d = 10%
Vs=9V
Vs=14V
Vs= 12V
Vs=6V
d
Harmonic distortion
4
f = 1 KHz
RL =40
1.8
4
3.1
0.7
f = 1 KHz
Vs=9V
RL =40
Po = 50 mW to 1.2W
Input saturation voltage
(rms)
Vs=9V
Vs=14V
0.8
1.3
RI
I nput resistance (pin 8)
f = 1 KHz
55
7J
Efficiency
f = 1 KHz
Vs= 9V
Vs = 14V
BW
Small signal bandwidth (-3 dB)
Vs = 14V
Gy
Voltage gain (open loop)
Vs = 14V
f = 1 KHz
Gy
Voltage gain (closed loop)
Vs = 14V
f = 1 KHz
eN
Total input noise
R = 500
R~ = 10 KO
RL=40
RL =40
R =500
R~=10KO
SVR
Tsd
Note:
Supply voltage rejection
Thermal shut-down case
temperature
Po= 2W
Po =4.5W
RL =40
RL =40
Po= lW
39.5
20
V
V
15
18
rnA
W
0.3
%
V
150
KO
70
65
%
40 to 40,000
Hz
75
dB
40
40.5
(0)
1.2
2
4
(00)
2
3
/J.V
50
dB
120
°C
Vs=12V
frlpple= 100 Hz
Rg = 10 KO
VripPle= 0.5Vrms
Ptot= 2W
Unit
2
4.5
0.1
Vi
Max.
40
dB
/J.V
(0) Weighting filter = curve A.
(00) Filter with noise bendwidth: 22 Hz to 22 KHz.
------------- ~ !~~~mg~Jl------------.:::...:3/8
491
TDA1904
Fig. 1 - Test and application circuit
Rl
10
kJ'l
Ct,
100J'l
R2
(*) R4 is necessary only for Vs
< 6V
Fig.2 - P.C. board and components layout of fig. 1 (1 : 1 scale)
CS-OI63
~4/~8_________________________ ~~~~;~~Jrf~~~
492
---------------------------
TDA1904
APPLICATION SUGGESTION
The recommended values of the external components are those shown on the application
circuit of fig. 1.
When the supply voltage V 5 is less than 6V, a
resistor must be connected between pin 2
6an
Components
Rl
Recomm.
value
Purpose
10 Ko,
and pin 3 in order to obtain the maximum
output power.
Different values can be used. The following
table can help the designer.
Larger than
recommended value
Smaller than
recommended value
Increase of gain.
Decrease of gain.
Increase qu iescent
Allowed range
Min.
Max.
9 R3
current.
Feedback resistors
R2
1000,
R3
4.70,
Frequency stability
R4
680,
I ncrease of the
output swing with
low supply voltage.
Cl
2.2/lF
Input DC
decoupling.
C2
O.l/lF
Supply voltage
bypass.
C3
22/lF
Ripple rejection
Increase of SVR
increase of the
switch-on time.
C4
2.2/lF
I nverting input DC
decouplinQ.
Increase of the
switch-on noise
C5
47/lF
C6
C7
Decrease of gain.
1 Ko,
Increase of gain.
Danger of oscillation
at high frequencies
with inductive loads.
390,
2200,
Degradation of SVR.
2.2/lF
100/lF
Higher low
frequency cutoff.
O.l/lF
Bootstrap.
Increase of the
distortion at low
frequency.
10/lF
0.22/lF
Frequency stability.
Danger of oscillation.
1000/lF
Output DC
decoupl ing.
Higher low
frequency cutoff.
___________________________
Higher cost lower
noise.
Higher low
frequency cutoff.
Higher noise.
Danger of
oscillations.
~~~~~~~~©~
100J.,lF
_________________________5_1_8
493
TDA1904
Fig. 3 - Quiescent output
voltage vs. supply voltage
Yo
,,-,-....,..:.,.,-,-,--.-rr-,--.-,-'..,·=;M
H-+-+-+-I-+-+-+-H-++-H-l
"H-++-+-I-+-+-+-H-++-H-l
IV'
Fig. 5 - Output power vs.
supply voltage
G-IUS
Fig. 4 - Quiescent drain current vs. supply voltage
'.
,w,"
l=lKHz
RJ41l.
dIlIO"I.
10
)
14
"
/
10
/~
....
V 17
V
./' /
V
~
12
12
'6 Vs (V)
'---'-"I--.rrrn--'--rT'T'-f"ti"'h"
'·IolI---I.C±rH++l+l--t-t-t+
IItH-H
10
(V)
d
RL·Io!l.
t :'MHz
I" 'OOHZ,++++++---+-+-+tt1+H
,4Y
,v
V
1
1
"Iv
.!
.,
d
I I
I
~'t.
12
n
I II
II
r'
R L ,,4JL
f " 12KH1I:
0.'
Fig. 9 - Distortion vs. output power
G-61f9/1
d
("/. I
II I
I~L=2~O~Z
,
'v
BV
c.,
0.3
Fig. 10 - Distortion vs. output power
Go"S1
,
("I.
J
0.'
0.3
IZV ,4Y
BV
0.'
,
''t.
1
1+
9V
_6:.-/8_ _ _ _ _ _ _ _ _ _ _ _ ~ I~tm?elf
Po (Wl
III
~~~Z81(~Z 1
BV
",IWI
i.,
J
0.3
.iv '4~
0.3
"Iv
Fig. 11 - Distortion vs. output power
d
I I
7;;::;'
0-&151
II
'v
6V
j
03
14
Fig. 8 - Distortion vs. output power
0-6'61
RL"Ul.
12
Vs
Fig. 7 - Distortion vs. output power
Fig. 6 - Distortion vs. out·
put power
d
16
0.'
0.3
..
IT
I I
,k., .!v
Po (w)
------------
TDA1904
Fig. 12 - Distortion vs. frequency
d
I
('to )
Fig. 13 - Distortion vs. frequency
d
II
II
V._9V
R .4il.
..
('to)
Po·sOmw
...
V1.'~
.
11111
I
I
'15 ,,9'1
RL'''S.Jl.
I
1
I
~"zw
'j
V
!
0.3
I
0.'
./11
Po =50mW
,
....... ~
.....
,•
I
)
~ .. 50mW
RL,,46
,
II
..'I\.
Ys.'4V
Fig. 14 - Distortion vs. frequency
. ,
-
......
o.lw '
/
!
li!1
III
.0'
·10'
Fig. 15 - Distortion vs. frequency
.-11"
tlHz)
'OK
(w)
1--+-!-t+HttI-H++t+ttl::-::!:+t-ttHti
Vs=12Y
('/.)
P
60 f-t--l-ttttltl-HttttHIR!EI"loKn
4Jl,
'.8
RL.=4n
...
..,
I (Hz)
P'''~i!I~~~~~~~~~
l
(da)
L-IA
10'
Fig. 17 - Total power dissipation and efficiency vs.
output power
... '-T'"'I-rrTT11T-r-TTrTmr---.-rn"TTTll
~~'4V
'0'
10'
Fig. 16 - Supply voltage rejection vs. frequency
I
)
••
.00
flHz)
'.4 1--l--iF-I--I--HH-t-t-t-t-l
Po·SOmW
... ,....
!
1.2
10'
"
Fig. 18 - Total power dissipation vs. output power
(W)
'.1
80
70
.0
'0
30
.0
I.~
1.4
,8A
...
...
..,
,Jl,
20
•• 2
0.'
I.,
,..
I
0.6 I V
0.4
0.'
Po(Wl
----------------~
________
•
..
•
7
7'
,
./' ,an .......
L
40
'1•• 12'1
t .,IKHz
p."
0-1'"
(W )
P41l
/
0.'
'8A
/'
V ,,i.-'"
0.'
'l
40
:I~~'
,
l
,
I..
J,
~~~I;~~~~~
Po (WI
Po(W)
Fig. 20 - Total power dissipation vs. output power
1/
0. 4
0.8
30
10
(
'4ll
./
:
Y,,4Y'
5
'toI
(w )
10-
...
f\ 4il.
....-
0.4 Lt::=tV±±±±±j'~fj":'Hj'-3f-3f-]'0
G-1I1'"
"
('to)
70
60
f{Hz)
Fig. 19 - Total power dissipation vs. output power
G-6175/,
,Jl,
p.ot
.0.
100
I (Hz)
B80
,\8
/
,o'-..L.LJ..J..LlJJJ_L.1.LlJl.UJl.....JLl..LlllllJ
.0'
YJ'
If
0.8
3ol-+-t-HffllI-t-t-tt1ftttt-f-+tttttff
.::
B
1.6&I- PSl1
4ol-+-t-HffllIf-+-!+1'Ittttt-f-+tttttff
./
0. l
..
t
..•
-
I
I'
I
II
X'
.-
..... "I~"""" ,411
//
r.....
•• 2
-
r0-
....
....
•,.•
,.
f .1 "
•..
(
•
.. ,,(WI'
________________________
7~/8
495
TDA1904
THERMAL SHUT-DOWN
MOUNTING INSCTRUCTION
The presence of a thermal limiting circuit offers
the following advantages:
The TDA 1904 is assembled in the Powerdip, in
which 8 pins (from 9 to 16) are attached to the
frame and remove the heat produced by the chip.
1)
An overload on the output (even if it is
permanent), or an above limit ambient
temperature can be easily tolerated since
the TJ cannot be higher than 150° C.
2) The heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no possibility of device
damage due to high junction temperature.
If for any reason, the junction temperature
increase up to 150°C, the thermal shutdown simply reduces the power dissipation
and the current consumption.
Figure 21 shows a PC board copper area used
as a heatsink (I = 65 mm).
The thermal resistance junction-ambient is 35°C.
Fig. 21- Example of heatsink using PC
board copper (I = 65 mm)
~8~/8~_______________________ ~~~~~~~~~ ___________________________
496
TDA1905
5W AUDIO AMPLIFIER WITH MUTING
The TDA 1905 is a monolithic integrated circuit
in POWERDIP package, intended for use as low
frequency power amplifier in a wide range of
applications in radio and TV sets:
- muting facility
- protection against chip over temperature
- very low noise
- high supply voltage rejection
- low "switch-on" noise
- voltage range 4V to 30V
assembly ease, space and cost saving of a normal
dual in-line package but with a power dissipation
of up to 6W and a thermal resistance of 15°CIW
(junction to pins).
The TDA 1905 is assembled in a new plastic
package, the POWERDIP, that offers the same
ORDERING NUMBER: TDA 1905
Powerdip
(8 + 8)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Input voltage
Differential input voltage
Muting thresold voltage
Power dissipation at Tamb = 80°C
Tease = 60°C
Storage and junction temperature
30
3
2.5
Oto + Vs
±7
Vs
1
6
-40 to 150
V
A
A
V
V
V
W
W
°C
APPLICATION CIRCUIT
lOOn.
--(---:}-1
,
C9
lOOO"F
l6V
VT
5_401"2
June 1988
1/12
497
TDA1905
CONNECTION DIAGRAM
(Top view)
.....,
OUTPUT
l'
16
GND
Vs
12
15
GND
BOOTSTRAP
I3
14
GND
THRESHOLD
I 4
13
GND
MUTING
12
GNO
INVERT. IN
11
~GND
SVR
10~GND
9
~GND
5-2913
SCHEMATIC DIAGRAM
3000j R11
~.
R3
Q13
lOOk!!
R1
R7
l00kfi
Q4
R5
R4
Q5("'"
RG
-,-
01~
€
::: Q12
~Q2
MUTING
~
0
26kfi
R'
200Kn.
10Kft+
C:~rl(08
Gkfi
;,t"
05
~. ~' ~
Q'
OG>--
R2
;?:
03
G
Kfi
02
RB
06
T
RIO
5-3647/2
4
5
7
B
• to 16
6
THERMAL DATA
Rthi·case
Rthi·amb
Thermal resistance junction-pins
. Thermal resistance junction-amb
...:.2/""1...:.2_ _ _ _ _ _ _ _ _ _ _
498
~ !~t~m?:~lt
max
max
15 °C/W
70 °C/W
-------------
TDA1905
TEST CI RCU ITS:
WITHOUT MUTING
C7
l000",F
I
lC
R r1820
kJl
x~J n
R3
In
:;:f:~cx
RL
___ .....J
loon
R2
O.22",F
C6
S-4055'2
WITH MUTING FUNCTION
Vi
'VT
(Muling)
499
TDA1905
ELECTRICAL CHARACTERISTICS (Refer to the test circuit,
Tamb =
25°C, Rth (heatsink)
20°C/W, unless otherwise specified)
Typ.
Max.
Unit
30
V
2.1
7.2
15.5
2.5
7.S
16.S
V
V =4V
V:=14V
Vs = 30V
15
17
21
35
le= lA
0.5
le=2A
1
Test conditions
Parameter
Vs
Supply voltage
Vo
Quiescent output voltage
Id
Quiescent drain current
VeE sat
Po
d
VI
Output stage saturation
voltage
Output power
Harmonic distortion
Input sensitivity
Min.
4
V =4V
V:=14V
Vs = 30V
1.6
6.7
14.4
V
d = 10%
Vs=9V
Vs=14V
Vs=lSV
Vs= 24V
f = 1KHz
Vs=9V
Po
Vs=14V
Po
Vs = lSV
Po
Vs=24V
Po
f = 1KHz
Vs=9V
Vs=14V
Vs=lSV
Vs= 24V
f = 1KHz
RL =40 (*)
RL =40
RL=SO
RL = 160
2.2
5
5
4.5
RL =40
=50mWtol.5W
R L =40
= 50 mW to 3W
RL = SO
=50mWto3W
RL=160
= 50 mW to 3W
R L =40
RL =40
RL=SO
RL = 160
Po
Po
Po
Po
0.1
37
49
73
100
= 2.5W
= 5.5W
=5.5W
= 5.3W
RI
Input resistance (pin S)
f = 1KHz
60
Id
Drain current
f = 1 KHz
V =9V
V:=14V
Vs=lSV
Vs= 24V
RL =40
RL =40
RL=SO
RL = 160
Po
Po
Po
Po
= 2.5W
=5.5W
= 5.5W
= 5.3W
f = 1KHz
Vs=9V
Vs=14V
Vs= lSV
Vs = 24V
R L =40
R L =40
RL=SO
RL = 160
Po
Po
Po
Po
=
=
=
=
(*) With an external resistor of 1000 between pin 3 and +Vs.
500
%
0.1
O.S
1.3
1.S
2.4
Efficiency
W
0.1
V =9V
V: = 14V
Vs=lSV
Vs= 24V
11
2.5
5.5
5.5
5.3
0.1
Input saturation
voltage (rms)
Vi
mA
2.5W
5.5W
5.5W
5.3W
mV
V
100
3S0
550
410
295
73
71
74
75
KO
mA
%
TDA1905
ELECTRICAL CHARACTERISTICS (continued)
BW
Small signal
bandwidth (-3dB)
Vs = 14V
Gy
Voitage gain (open loop)
Vs=14V
f = 1 KHz
Gy
Voltage gain (closed loop)
Vs=14V
f = 1KHz
eN
Total Input noise
Supply voltage rejection
SVR
Thermal shut~own
case temperature
Tsd
R L =4n
Po = 1W
RL =4n
Po= 1W
39.5
Rg = 50n
R = 1Kn
R: = 10Kn
(0)
Rg = 50n
R = 1Kn
R:=10Kn
(00 )
Vs=14V Rg= 10Kn
Po = 5.5W Rg= 0
R L =4n
Rg = 10Kn
Rg=O
Signal to noise ratio
SIN
Min.
Test conditions
Parameter
Vs=18V RL =8n
frlPPle = 100 Hz
V ripple = 0.5Vrms
Max.
Unit
Hz
75
dB
40
40.5
1.2
1.3
1.5
4.0
2.0
2.0
2.2
6.0
dB
,.V
,.V
(0)
90
92
dB
(00 )
87
87
dB
50
dB
115
°c
Rg = 10Kn
40
Ptot = 2.5W
(.)
Typ.
40 to 40,000
MUTING FUNCTION
VTOFF
Muting-off threshold
voltage (pin 4)
1.9
4.7
V TON
Muting-on threshold
voltage (pin 4)
0
1.3
6.2
Vs
R5
Input resistance (pin 5)
R4
I nput resistance (pin 4)
AT
Muting attenuation
V
V
Muting off
80
10
Muting on
Kn
200
30
Rg+ Rl = 10Kn
50
n
Kn
150
60
dB
Note:
(0)
(00)
(*)
Weighting filter = curve A.
Filter with noise bandwidth: 22 Hz to 22 KHz.
See fig. 30 and fig. 31
-------------
~ ~~tm~s£'
___________
~5/=12
501
TDA1905
Fig. 1 - Quiescent output
voltage vs. supply voltage
I.
'0
tv)
Fig, 3 - Output power vs.
supply voltage
Fig. 2 - Quiescent drain cur·
rent vs. supply voltage
Po
...
tWl~-+ 7.,.2H~,t-rf-+,r+-~-+-r~
(mA)
d :10'10
H-+,r+--t---rf-r++-1
"
1M
20
I.
12
i
16
20
210
12
Fig. 4 - Distortion vs. out·
put power (R L = 1612)
-+
Iii
20
24
12
Fig. 5 - Distortion vs. out·
put power (R L = an)
16
20
24
Fig. 6 - Distortion vs. out·
put power (R L = 412)
r:'!F..:-: -.-
2~:·I~H hI
I I
J
0.1
J
~I
1-ft----jf-+-rt+tttI
-+-'
J
0.1
fll ~161l
f
~
1KHz
, ,
001
i'
~I
001
10
6/12
502
RL=16A
PatW)
QI
Fig. a - Distortion vs. frequency (R L = an)
Fig. 7 - Distortion vs. fre·
quen,cy (R L = 1612)
VS ,24V
, ,
001
%tWl
QI
,W
Ys~18V
1/
Rl:'SD.
"
SOmW
01 ,
...,,' , ... , ...
10'
,
10'
,
001
f(Hzl
10
~'w-
-,W
po- SOmW
QI
,
SOmW
r
~
,~."
RL=4
'r
'r
... , ... , ...",
10'
Fig. 9 - Distortion vs. frequency (R L = 412)
10'
W
SGS-THOMSON
~l. IlilO©OO@~~©'ii'IIJ@IilJO©$
001
'(Hz)
10
... ... , ...
10'
0'
10'
f(Hz)
TDA1905
Fig. 10 - Open loop frequency response
Fig. 11 - Output power
vs. input voltage
Fig. 12 - Value of capacitor ex vs. bandwidth (BW)
and gain (Gv)
%.~~~~~~~~~~~~~
.""k
/
100
H+tt~-r+:Hti "VS"C'2~"':t,IIlt,,
(n F )
'BW~'3KHz
'0
"$ 't~
1/
~o""Z+~ ~
V ,,-
1----+--,<'1.
1:'-',
c,
.,,4n • ,,8n
(W) ~
10
VVI/
""
J"-.
."-.
.0
"
~
,---
H-Httlli--+t-ttttHf-HtHtllt-f-HtttJll--t-l'WIIII
20
10'
10
10'
i
d ~tO-J.
20
40
Vi (mY)
20
SV. .--.-;-,-rTTlTr---r.,---rrrrrn
SV.
vS_,8vLL
(dB)
trippl~IOOHz
RL~811
Rg,,"lOKA
r-
=---::::-.,
•0
40
L
Gv(dBl
(W)
"5: 18V
R L,SA
Iripplt>.IOOHz
.0
........ :-.... ~ ::::-.
........ ...... ~ f::::.
lC,uF
12~FI C3
I"'- ...... '~F
50
~ot
f-----jf-H+++l4+-~c-'---++++H+l
f-f-f-H+ttt-H
40
30
Fig. 15 - Max power dissipation vs. supply voltage
(sine wave operation)
Fig. 14 - Supply voltage rejection vs. source resistance
Fig. 13 - Supply voltage rejection vs. voltage gain (ref.
to the Muting circuit)
(dBI
\.
L.._ _----'_ _-L_"--'-___LU
10-1
10
Gv :4Od8
- - --- h;lKHz
2.'
f.--t-++-+-I--I Rp 4ni'-.~nHH-..L-I--W
H-++-+-H--Ir++:
" ..
2•
..............
'0
1.5
~FIJ10
20
20
0.5 f.--t-+-r.I(~14-+++-HH++-W
30
10
~ot
"'S~14V
(W)
(
f:IKHz
Gv~40dB
fl(et\.)
3.'
/
30
-. I'
I /
2,5
2.
I.'
.0
05
I, /
VI
.0
30
fltlofl!
'It8M
:~~:~z H7I-'.,(1",6nT)--b.¥1-H-++~
q
Ptot
("I.)
(W)
10
Gv·4Od8
60
-"'-Ptot(4.Cl.J
50
20
40
I.,
30
....... r---Ptot (80)
20
rt
8
ct--H---'----'--++-H-++-H
lis
(vI
~
.0
3.0
'0
2S
40
2~
~
('4)
70
1KHz
Gy.'Od
60
Rl·16n
50
40
Ptot
f-f1~....
fM~+-1"'HPtot U6tlI-H-+++-H
1.0 ~H++-H-r--,-++-H-++-H
'0
1.5
'0
20
1.0
20
J-j-i-++H--++++-H-++-H
10
0'
1.
0.5
I-
HfI:-++-H-f-+'I"'HPtot(Sl'I.I
24
'1 5 .241/
t
70
/'
20
Fig. 18 - Power dissipation
and efficiency vs. output
power
Fig. 17 - Power dissipation
and efficiency vs. output
power
Fig. 16 - Power dissipation
and efficiency vs. output
power
)-
16
Rg (K.Ql
~(W)
---------------~!~I;~?v~~~:
Ij,(Wl
Po
(WJ
_____________~7/~1=2
503
TDA1905
APPLICATION INFORMATION
·Fig. 19 - Application circuit without muting
Fig ..20 - PC board and components lay-out
of the circuit of fig. 19 (1 : 1 scale)
..,.
C7
16V
O.22,..F
lOOil
R2
C6
(.) R4 is necessary only
for Vs < 10V.
5-4051'1
Po = S.SW (d = 10"10)
Vs=14V
Id =O.SSA
Gy = 40dB
CS-0129/1
Fig. 21 - Application circuit with muting
Fig. 22 - Delayed muting circuit
."s
.... '4
::.!8/..:.12=--_ _ _ _ _ _ _ _ _ _ ~ l~m~l9lt
S04
------------
TDA1905
APPLICATION INFORMATION (continued)
Fig. 24 - Output power vs.
supply voltage (circuit of
fig. 23)
Fig. 23 - Low-cost application circuit without bootstrap.
'Ys
"-
I
I
,WI
I. 1KHz
C-
'-
d dO.,.
-f-
~;t,n
-~.
i
--
f-
II
f-r---H-:-
rt1
I
I I
/
J
'
'--
-. ~
1
I
/'
V
V
/
!/
II /A
IM....~
Fig. 25 - Two position DC tone control using change of pin 5
resistance (muting function)
~----""'--""'-------O.Vs
Fig. 26 - Frequency response
of the circuit of fig. 25
G,
(dB)
so
"
46
C9
10
III
kll
R7
16V
"
FL
40
38
O.21,uF
C,
C3
'0
10'
10'
10'
t(Hzl
Rio
Fig. 27 - Bass Bomb tone control using change of pin 5 resistance
(muting function)
Fig. 28 - Frequency response
of the circuit of fig. 27
.....- -.....-------O.Vs
~--'--
RI
1001111
Flat
48
1000,...
CB
CI
Rio
,olin
100/1
A5
BOOST
46
I6V
R6
In
O.22,..F
FLAT
40
"
C7
------------- ~ ~~i~m?m~~
,0
10'
10'
104
t{Hz)
9/12
505
TDA190S
MUTING FUNCTION
The output signal can be inhibited applying a DC voltage VT to pin 4, as shown in fig. 29
Fig. 29
VOUT
V./2 ,--------.W/h
The input resistance at pin 5 depends on the threshold voltage V T at pin 4 and is typically:
R5 =200Ko @ 1.9V';;;VT ';;;4.7V
muting-off
OV ';;;V T ';;; 1.3V
6V';;;V T ';;;Vs
muting-on
R5 = 100
Referring tei the following input stage, the possible attenuation of the input signal and therefore of the
output signal can be found using the following expression:
R
Rf~
Y~
9
Vi
( Rs ' Rs
Rs + 5
( Rs • Rs
Rs+Rs
9
+
r"'..J
5-4058
where Rg
~
100 Ko
Considering Rg = 10 Ko the attenuation in the muting-on condition is typically AT = 60 dB. In the
muting-off condition, the attenuation is very low, tipically 1.2 dB.
A very low current is necessary to drive the threshold voltage VT because the input resistance at pin 4
is greater than 150 Ko- The muting function can be used in many cases, when a temporary inhibition
of the output signal is requested, for example:
- in switch-on condition, to avoid preamplifier power-on transients (see fig. 22)
- during switching at the input stages.
- during the receiver tuning.
The variable impedance capability at pin 5 can be useful in many application and two examples are
shown in fig. 25 and 27, where it has been used to change the feedback network, obtaining 2 different
frequency response.
~lO~/~12:.......-----------l.;i.I~tm?eAl
506
-------------
TDA1905
APPLICATION SUGGESTION
The recommended values of the external components are those shown on the application circuit of fig. 21.
When the supply voltage Vs is less than 10V, a 1000 resistor must be connected between pin 2 and pin
.
3 in order to obtain the maximum output power.
Different values can be used. The following table can help the designer.
Component
Raccom.
value
Rg+ Rl
10KO
R2
10KO
R3
1000
R4
10
Frequency stability
Rs
1000
Increase of the
output swing with
low supply voltage.
P1
20KO
Volume potentiometer
Purpose
Input signal imped.
for muting operation
Larger than
recommended value
Smaller than
recommanded value
Increase of the atte·
nuation in muting""n
condition. Decrease of
the input sensitivity.
Decrease of the atte·
nuation in muting
on condition.
Increase of gain.
Decrease of gain.
Increase quiescent
current.
Decrease of gain.
Increase of gain.
Allowed range
Min.
Max.
9 R3
Feedback resistors
Cl
C2
C3
~
Input DC
0.22"F decoupling.
Danger of oscillation
at high frequencies
with inductive loads.
47
Increase of the
switch-on noise.
Decrease of the input
impedance and of the
input level.
Higher cost
lower noise.
Higher low frequency cutoff.
Higher noise
Increase of the
switch-on noise.
Higher low frequency cutoff.
C4
2.2"F
Inverting input DC
decoupling.
Cs
0.1"F
Supply voltage
bypass.
C6
10"F
Ripple rejection
C7
47"F
Bootstrap.
Increase of the distortion at low frequency.
Cs
0.22"F
Frequency stability.
Danger of oscillation.
Cg
1000"F Output DC
decoupling.
________________________
1KO
330
10KO 100KO
0.1"F
Danger of
oscillations.
Increase of SV R
increase of the
switch-on time
Degradation of SVR
2.2"F
100"F
10"F
100"F
Higher low frequency cutoff.
~!~~~
______________________
~1~1/~12
507
TDA1905
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent!. or an above limit ambient temperature can be
easily tolerated since the Tj cannot be higher than 150°C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
If for any reason, the junction temperature increases up to 150°C, the thermal shut-down simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends upon the size of the external heatsink (Le. its thermal resistance); fig. 32 shows this dissipable power as a function of ambient temperature for different
thermal resistance.
Fig. 31 - Output power and
drain current vs. case temperature
Fig. 30 - Output power and
drain current vs. case temperature.
,-,--,-,..,-,-,--,-..,-,-,-,,--',,-0'.:;".:..,5
Id(A}
1-t+1-t-t-1-t--t-1-t--t-1 Vs"l6V
Po
~-'-r-T-'-r-T-'-'-'--''''--;r-'rT.
~~
(W)
H-+-H--H-+-H-+-HRL .. 4ft
H-+-H--H-+-H-+-HhIKHz
Fig. 32 - Maximum allowable power dissipation vs.
ambient temperature.
I.
{AI
H-+-I-+-H-+-+-1R L" 8.n
1-++-1-++-1-+-+-1, .. 1KHz
PI •• "
p.
H-I-'H-i
'.0
H++-++++ H-+++-+-+++-1
~.
H-+H+H-++-1r+-+-l-+tH
0.6
H-+-H-+-H-++-r+-+-f--jJ\-H
0.2
04
so
.00
Tcase-C
so
'00
_40
40
80
MOUNTING INSTRUCTION: See TDA1904
.:..12;;:..1.:..12::...-_ _ _ _ _ _ _ _ _ _ _
508
~ ~~~~m?~~~lt
-------------
TDA1908
8W AUDIO AMPLIFIER
The TDA 1908 is a monolithic integrated circuit
in 12 lead quad in-line plastic package intended
for low frequency power applications. The
mounting is compatible with the old types
TBA800, TBA81 OS, TCA830S and TCA940N.
Its main features are:
-
low number of external components;
high supply voltage rejection;
very low noise.
flexibility in use with a max output curent of
3A and an operating supply voltage range of
4V to 30V;
- protection against chip overtemperature;
- soft limiting in saturation conditions;
- low "switch-on" noise;
-
Findip
ORDER CODE: TDA1908
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Power dissipation: at Tamb = 80°C
at Tamb = 90°C
Storage and junction temperature
30
3.5
V
A
3
A
1
5
W
W
-40 to 150
°c
APPLICATION CIRCUIT
1000",F
I
June 1988
1/10
509
TDA1908
CONNECTION DIAGRAM
(top view)
OUTPUT
SUPPLY VOLTAGE
N.C.
N.C.
N.C.
GROUNO
GROUNO
GROUNO
GROUNO
BOOTSTRAP
sua
NON INVERTING
INPUT
N.C.
SVR
INVERTING INPUT
SCHEMATIC DIAGRAM
4
300n! Rl1
R3
e
:/tik/1
Q1
@
I
~~
0
o./al2
al3
-i(a2
RI
01
R4
lookll
look/1
RS
R6
~as
..B!
200K/1
R9
12
IOK/1
=~CI
~
6k/1
-i(
a8
",a7
~03
03 an'"
~
K~
02
JR2
R8
06
~
09
06>-1
05
010
o./al4
10
RIO
5- '044
7
_2~/1_O
510
8
__~___________________
9
6(
~I~~~~~
__________________________
TDA1908
TEST CIRCUIT
C7
IOoo,uF
I
R
~lB20
x~J It
~~~~Cx*
L-----~~II~~----~---~
loon
R2
* See fig. 12.
THERMAL DATA
Rthj-tab
Rthj-amb
(0)
Thermal resistance junction-tab
Thermal resistance junction-ambient
max
max
Obtained with tabs soldered to printed circuit board with min copper area.
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T.mb = 25°e, Rth (heatsink)=
8 °e/W, unless otherwise specified)
Typ.
Max.
Unit
30
V
2.1
9.2
15.5
2.5
10.2
16.8
V
Vs = 30V
~:: i~v
15
17.5
21
35
Output stage saturation voltage
(each output transistor!
Ic= 1A
0.5
Ic= 2.5A
1.3
Output power
d = 10%
f = 1 KHz
R L= 4n
Vs= 9V
Vs=14V
RL= 4n
R L= 4n
Vs=18V
Vs = 22V
RL= 8n
R L= 16n
Vs = 24V
2.5
5.5
9
8
5.3
Vs
Supply voltage
Vo
Qu iescent output voltage
Id
Quiescent drain current
VCEsat
Po
-------------
Min.
Test conditIon
Parameter
4
1.6
8.2
14.4
Vs=4V
Vs=18V
Vs = 30V
~ ~~t~~
mA
V
7
6.5
4.5
___________
W
.:;:.3/~lO
511
TDA1908
ELECTRICAL CHARACTERISTICS
(continued)
Parameter
Test condition
f = 1KHz
R L =4n
Vs=9V
Po = 50 mW to 1.5W
Vs=18V
R L =4n
Po = 50mW t04W
R L = 16n
Vs = 24V
Po= 50 mW to 3W
Harmonic distortion
d
V = 9V R L =
V~=14V R L =
Vs=18V R L =
Vs = 22V RL=
Vs =24V RL=
Input sensitivity
Vi
Input saturation voltage (rms)
Vi
Min.
4n
4n
4n
8n
16n
f = 1 KHz
Is
Drain current
f = 1 KHz
Vs=14V
Vs=18V
Vs=22V
Vs=24V
R L = 4Q
R L = 4n
R L = sn
R L =16n
Po= 5.5W
Po= 9W
Po =8W
Po=5.3W
!J
Efficiency
f = 1 KHz
Vs=18V
R L =4n
Po=9W
SW
Small signal bandwidth (-3 dB)
Vs= 18V R L =4n
Gv
Voltage gain (open loop)
f = 1 KHz
Gv
Voltage gain (closed loop)
Vs=lSV
f = 1 KHz
Total input noise
(0 )
(00 )
Signal to noise ratio
SIN
SVR
Supply voltage rejection
Tsd
Thermal shut-down junction
temperature
Vs=18V
P0 = 9W
R L =4n
%
37
52
64
90
110
60
Input resistance (pin S)
eN
0.1
Vs=18V
Vs = 24V
RI
Po= lW
mV
V
100
Kn
570
730
500
310
mA
72
%
40 to 40 000
Hz
75
R L =4n
Po= lW
Unit
0.1
0.8
1.3
1.S
2.4
V~=14V
Max
0.1
Po= 2.5W
Po= 5.5W
Po=9W
Po=8W
Po= 5.3W
V = 9V
Typ.
39.5
dB
dB
40
40.5
R~=10Kn
1.2
1.3
1.5
4.0
Rg = 50n
R = lKn
R~ = 10Kn
2.0
2.0
2.2
6.0
Rg= 10Kn
(0)
Rg= 0
92
94
dB
Rg= 10Kn (00 )
Rg=O
8S
90
dB
50
dB
145
°C
Rg = 50n
R = lKn
Vs=lSV
R L =4n
fripple= 100 Hz
Rg= 10Kn
(*)
40
JJV
JJV
Note:
(0)
(00)
Weighting filter = curve A.
Filter with noise bandwidth: 22 Hz to 22 KHz.
~4~/l~O________________________ ~~~i~~~~©~
512
___________________________
TDA1908
Fig. 2 - Quiescent drain current vs. supply voltage
Fig. 1 - Quiescent output
voltage vs. supply voltage
v,
IV)
,,-,,--,-,--,-,,---,-,-,,-,-i-'i"'l
H-+-+-1-++H-+++-+-+--vl-1
1.,,-r"-'---'-"-''-rT-'-~~
H-+-+-1-++H-+-+-f-++H--j
(mA)
Fig. 3 - Output power vs.
supply voltage
Gwl;219
P,
IW )
9
-
~KtJ
~"_~J-
j ____
RL7
f--
--
"A
V
/
/
/
V
V
-
/
/
I
I
t-- --
, i/
V
/
~
3
Fig. 4 - Distortion vs. output power (R L = 16n)
6
9
12
15
18
21
24
V.(V)
Fig. 6 - Distortion vs. output power (R L = 4n)
Fig. 5 - Distortion vs. output power (R L = 8n)
I~~.
~"s"9V
14V18V22V
~~~:~
I I
J
0.'
0.'
.
I
I)
J
0.'
RL~16.n
f
00.
"
~
IKH:z:
..
Po(W)
Fig. 7 - Distortion vs. frequency (R L = 16n)
..
0.01
0.'
Po(W)
Fig. 8 - Distortion vs. frequency (R L = 8n)
0,01
"
Po{W)
Fig. 9 - Distortion vs. frequency (R L = 4n)
I.
I
I
I
VS=14V
RL' 4·nt--t-+-ti>!!ltt--Htttttll
oo.~~.~.~.~,~.~.~.-+~~-+~~
IO~
t(Hz)
.0
102
10 3
___________________________
~~~~~~?~~:~~~
________________________
~5/~10
513
TDA1908
Fig. 12 - Values of capacitor
Bw
Fig. 11 - Output power vs.
input voltage
Fig. 10 - Open loop frequency response
ex versus gain and
Gv~Trrmr"mm"Tmmr~~-.rmm
C,
H+l+IIlf-++IfllIlHfIfj-llll-·ffilHllll-+++HlII
(nF)
(dB)
'0
.Is "'1-
"'-BWsSKHz
c"01':""'7~ ~
,['..
IV
.'-
"- ~
f=lKHz
d .. ,O"J.
20
1'-
\.
H+Hllll-+++lHIH--+t
'0'
10'
10'
,
L--!_,-+~-,-!-,.1----..,~'-7~.u..:_u,
10\
'0
100
'0
t(Hz)
Fig. 13 - Supply voltage
.rejection vs. voltage gain
2<1
V,(mV)
Fig. 14 - Supply voltage rejection vs. source resistance
Vs&'8vLL
VS:18V
t rippl.. IOOHz
f--t-f--t+tftH R
L·."
'ripphhlOOHz
-r-
RLsen.
80
Rg,"'OIUl.
;::::: :::::::
I'- -:-- ;:::::; ~
........ l'" ::::;; ~
10AlF C3
5",.
........ ...... 2>NF1
'0
R.L,
P,ot
IWI
L
f--j-H+t++t+::--=L-H-+t-ttH
(dBI
1- -
I .. 1KHz
--
2/011'/-
2.5
/
o.
.0
30
'0
V
/
/
10 ..
/
I--
/
/'
/
~
Rg (K.nJ
'0
Fig. 16 - Power dissipation
and efficiency vs. output
power. (Vs= 14V)
/. V
•
V'.
L
/
I.S
.0 f--t-f--t+t+Ht--f--H-tt-tftl
20
I
/
3.S
f--t-f--t+t+Ht--I---"N..t:I-tftI
'0
'0
Fig. 15 - Max power dissipation vs. supply voltage
SVR r---'-rTTTTn'-~'-rT"Tm
SVR
(dB)
30
Fig. 17 - Power dissipation
and efficiency vs. output
power (V 5= 18V)
Fig. 18 - Power dissipation
and efficiency vs. output
power (V 5= 24V)
I~-ttl"
'-i-l ~ IR;~
G-421UI1
Ptot
IWI
r-
I
"'ssl""
1
hlKHz
I-
Gv:loOdB
3.'
'.S
I
/
-.)r---.
V
•• /1 V
1/,......
VJ
.
LO
/
-
80
7
'lIM)
fJ.(4jl}
70
V
3.'
60
r-Ptot'
50
4.0.)
'.5
'0
.0
t'-Ptot(snl
\.'
20
QS
'0
0.'
f-
L
,
/
'IV
-_.
/
"101
,/' "IRL~
'I
V
I
Ptot(RL·SJl)
'Is_,av
1 .. 1KHz
"
{'/oJ
"S·Zlo"
'0
'.IKHz
Gy.40d
.0
RL-'I"
70
60
25
50
LO
40
I
P,ot
IWI
80
I'\(R L-4Jl·)
C><_
V
V
I !
----
50
Ptot
"
IS
30
.5
10
30
!_ -
G".40 d B
--
-
.0
'0
10
1
8
\tW)
-"6/'-=1..:..0_ _ _ _ _ _ _ _ _ _ _ _ ~ I~tm~~
514
-------------
TDA1908
APPLICATION INFORMATION
Fig. 19 - Application circuit with bootstrap
* R4 is necessary when V 5 is less than 1OV.
Fig. 20 - P.C. board and component lay-out of the circuit of fig. 19 (1: 1 scale)
GND
Vi
___________________________
~~~~~~~~~~
________________________~7/~lO
515
TDA1908
APPLICATION INFORMATION (continued)
Fig. 21 - Application circuit without bootstrap
..
Fig. 22 - Output power vs.
supply voltage (circuit of
fig. 21)
G-4287
ew )
"f =lKHz
d='0'" -c-
~Lf+-+I ~}'8f-f-/
.100 0", F
/
II V
II
1.11
/
"
-
I
'//
~ :..--
L
)1~ -
,.
+-
I--
I
24
VII (V)
I
Fig. 23 - Position control for car headlights
:I: O.1,uF
10011.
lM.Q.
6xl00n.
6Xl00n
,L
_____
_
5-4041/2
_8/~1_0________________________ ~!~~~~?~~~
516
___________________________
TDA1908
APPLICATION SUGGESTION
The recommended values of the external components are those shown on the application circuit of
fig. 19.
When the supply voltage Vs is less than 10V, a 100.11. resistor must be connected between pin 1 and pin 4
in order to obtain the maximum output power.
Different values can be used. The following table can help the designer.
Component
Raccom.
value
Larger than
raccomanded value
Purpose
Smaller than
raccomanded value
Allowed range
Min.
Max.
RI
10 K.I1.
Close loop gain
setting.
Increase of gain.
Decrease of gain.
Increase quiescent
current.
R2
100.11.
Close loop gain
setting.
Decrease of gain.
Increase of gain.
R3
1 .11.
Frequency stability
Danger of oscillation
at high frequencies
with inductive loads.
R4
100.11.
Increasing of output
swing with low Vs.
CI
2.2/L F
Input DC
decoupling.
C2
O.l/L F
Supply voltage
bypass.
C3
2.2/LF
Inverting input DC
decoupling.
Increase of the
switch-on noise
Higher low frequency cutoff.
O.l/L F
C4
10/LF
Ripple Rejection.
Increase of SVR.
Increase of the
switch-on time.
Degradation of
SVR.
2.2/L F
100/LF
Cs
47/LF
Bootstrap
Increase of the
distortion at low
frequency
10 "F
100 /LF
C6
0.22 "F
Frequency stability.
Danger of oscillation.
C7
1000/LF
Output DC
decoupling.
Higher low fre·
quency cutoff.
___________________________
9 R2
Rl/9
47.11.
Lower noise
Higher low frequency cutoff.
Higher noise.
330.11.
O.l/L F
Danger of
oscillations.
~~~~~~~~~©~
________________________~9/~lO
517
TDA1908
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers
the following advantages:
1) An overload on the output (even if it is
permanent), or an above limit ambient tem·
perature can be easily supported since the
lj cannot be higher than 150°C.
2) The heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no possibility of device
Fig. 24 - Output power and
drain current vs. case tem·
perature
damage due to high junction temperature.
If, for any reason, the junction temperature
increase up to 150°C, the thermal shut-down
simply reduces the power dissipation and the
current consumption.
The maximum allowable power dissipation
depends upon the size of the external heatsink
(i.e. its thermal resistance); fig. 26 shows the
dissipable power as a function of ambient tem·
perature for different thermal resistance.
Fig. 25 - Output power and
drain current vs. case temperature
Fig. 26 - Maximum power
dissipation vs. ambient tem·
perature
"·'~~m
IdlAI
(W)~
..•
"r-+-t-h--t-H+-H-+-H-+-H
_·;··+--r-+-f-H--l--I--f+ H-\-i--H '.0
'!-+--+--H-t---t-r-+-t-t-f+!H-l
r-+-t-hpo'--+-H+-H-l---Hr-I---H
,,-t"
I.
o.a
-il+-t-r-+-i--H-+-H-++-H
_-lid
0.6
·H=t-+++-H-H-H++-MH ::
r-+-t--I--f--+-H-+-H-+~l-+-H
•. 4
r-+-t--I--f--+-H+-H-+-H~-HO.2
o
50
100
50
'.0
5.
-50
100
TAmtt-t)
MOUNTING INSTRUCTIONS
The thermat' power dissipated in the circuit may
be removed by soldering the tabs to a copper
area on the PC board (see Fig. 27).
During soldering, tab temperature must not
exceed 260°C and the soldering time must not
be longer than 12 seconds.
Fig. 27 - Mounding example
Fig. 28 - Maximum power
dissipation and thermal reo
sistance vs. side "Q"
A'h
8•
•0
j-am
40
Pto1(r.mb"S'·C}
2.
10
C. SOARD
_______________________
_lO~/_IO
518
~!~~;~
•0
.
,
40
I(mm)
__________________________
TDA1910
10W AUDIO AMPLIFIER WITH MUTING
The TDA 1910 is a monolithic integrated circuit
in MU LTIWATT ® package, intended for use in
Hi-Fi audio power applications, as high quality
TV sets.
The TDA 1910 meets the DIN 45500 (d = 0.50fa)
guaranteed output power of 10W when used at
24V /4n. At 24V /sn the output power is 7W
min. Features:
- muting facility
protection against chip over temperature
very low noise
high supply voltage rejection
low "switch-on" noise.
The TDA 1910 is assembled in MUL TIWATT®
package that offers:
easy assembly
simple heatsink
space and cost savi ng
high reliability.
Multiwatt 11
ORDERING NUMBER: TDA 1910
ABSOLUTE MAXIMUM RATINGS
Vs
10
10
Vi
V,
Vll
Ptot
Tstg, TJ
Supply voltage
Output peak current (non repetitive)
Output peak current (repetitive)
Input voltage
Differential input voltage
Muting thresold voltage
Power dissipation at T case = 90°C
Storage and junction temperature
30
3.5
3.0
o to + Vs
±7
Vs
20
-40 to 150
V
A
A
V
V
V
W
°C
TEST CIRCUIT
C7
2200,..F
I
3.3 R r1820
kJl
xl
I It
1" (.)
:;$:~cx
~-------111~~--~---~
loon
R2
(.) See fig. 13.
June 1988
1/12
519
TDA1910
CONNECTION DIAGRAM (Top view)
0
0
11
THRESHOLD
10
BOOTSTRAP
9.
.vs
8;
OUTPUT
7'
5;
GND
GND
INPUT·
3!
NC
SVR
6:I
4:
CD ~I
INPUTMUTING
,/
5-3655
tab connected to pin 6
SCHEMATIC DIAGRAM
'0
30aDj
~.
k
MUTING
r-r-
R3
a2
~
J
26kll
,OOkll
100kll
RS
R6
D'~~
R4
,
R9
I~KJ!.
10KA
6
KJ!.
D2
RS
05
06
a,0
as
~
Q10
-----f:( Q3
~~
V a '2
~
R2
11
9
~~
=l=C'
)R'
Rll
5
6
2
~ !il~m?1r~l9@~
-------------
TDA1910
TEST CIRCUIT
+Vs
Rl
I
3.3 R r1820
k.ll xl I n
1" CO)
~:f:~cx
L-----n-----+------l
C4
loon
R2
(*) See fig. 13.
MUTING CIRCUIT
-VT
(Muting)
------------- ~ ~~tm~SJflt ___________
--=3/!..::.:::12
521
TDA1910
THERMAL DATA
Rth
j-c
max
Thermal resistance junction-case
3
°CIW
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Rth (heatsink) =
4°CIW, unless otherwise specified)
Parameter
Test condition
Vs
Supply voltage
Vo
Quiescent output voltage
Vs=18V
Vs = 24V
Id
Quiescent drain current
VeE sat Output stage saturation voltage
Po
d
d
Vi
Output power
Harmonic distortion
Intermodulation distortion
Input sensitivity
Min.
Max.
Unit
30
V
8
8.3
11.5
9.2
12.4
10
13.4
Vs=18V
Vs = 24V
19
21
32
35
le= 2A
1
le=3A
1.6
V
mA
V
d = 0.5% f = 40 to 15,OOOHz
Vs=18V
RL=4f!
Vs = 24V
RL=4f!
R L =8f!
Vs = 24V
6.5
10
7
7
12
7.5
W
d = 10%
Vs=18V
Vs = 24V
Vs = 24V
8.5
15
9
9.5
17
10
W
f = 1 KHz
RL=4f!
RL=4f!
R L =8f!
f = 40 to 15.000 Hz
Vs=18V
RL=4f!
Po= 50 mW to 6.5W
Vs= 24V
RL=4f!
Po= 50 mW to 10W
R L =8f!
Vs = 24V
Po= 50 mW to 7W
Vs = 24V RL=4f! Po= 10W
f 1 = 250 Hz
f2= 8 KHz
(DIN 45500)
f = 1 KHz
Vs = 18V RL=4f! P0 = 7W
Vs = 24V RL=4f! P0 = 12W
Vs = 24V R L =8f! Po= 7.5W
Vi
Input saturation voltage (rms)
Vs=18V
Vs = 24V
1.8
2.4
Ri
Input resistance (pin 5)
f = 1 KHz
60
Id
Drain current
f = 1 KHz
Vs = 24V
RL=4f!
Po= 12W
R L = 8f!
Po= 7.5W
~4~/l=2~______________________ ~~~~~~?~~~
522
Typ.
0.2
0.5
0.2
0.5
0.2
0.5
%
0.2
%
170
220
245
mV
V
100
Kf!
820
475
mA
________________ _________
~
TDA1910
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test condition
Efficiency
11
BW
Small signal bandwidth
Vs = 24V
BW
Power bandwidth
Vs = 24V
Po = 12W
Gv
Voltage gain (open loop)
f = 1 KHz
Gv
Voltage gain (closed loop)
Vs = 24V
f = 1 KHz
eN
Total input noise
Signal to noise ratio
SIN
SVR
SupplV voltage rejection
Tsd
Thermal shut-down case
temperature
Min.
f = 1 KHz
Vs = 24V
R L =4n
Po= 12W
R L =8n
Po= 7.5W
R L =4n
Vs = 24V
Po = 12W
R L =4n
Po= lW
R L =4n
d'; 0.5%
R L =4n
Po= lW
29.5
Max.
Unit
62
65
%
10 to 120,000
Hz
40 to 15,000
Hz
75
dB
30
30.5
dB
Rg = 500.
Rg = lKn (0)
R g =10Kn
1.2
1.3
1.5
3.0
3.2
4.0
p.V
Rg = 500.
Rg = lKn (00 )
R g =10Kn
2.0
2.0
2.2
5.0
5.2
6.0
p.V
Rg = 10Kn
(0)
Rg = 0
97
103
105
dB
Rg = 10Kn (00)
Rg = 0
93
100
100
dB
50
60
dB
110
125
°c
R L =4n
Vs = 24V
Rg= 10Kn
f rlPple= 100 Hz
Ptot = 8W
(*)
Tvp.
MUTING FUNCTION (Refer to Muting circuit)
VT
Muting-off threshold voltage
(pin 11)
1.9
4.7
VT
Muting-on threshold voltage
(pin 11)
0
1.3
6
Vs
RI
V
Input resistance (pin 1)
Muting off
80
Muting on
Rll
Input resistance (pin 11)
AT
Muting attenuation
V
200
10
150
Rg + R I = 10 Kn
50
Kn
30
0.
Kn
60
dB
Note:
(0)
(00)
(*)
Weighting filter = curve A.
Filter with noise bandwidth: 22 Hz to 22 KHz.
See fig. 29 and fig. 30.
-------------IJii.I~tm~
___________~5/=12
523
TDA1910
Fig. 1 - Quiescent output
voltage vs. supply voltage
Fig. 2 - Quiescent drain
current vs. supply voltag';....,
6_3612
(~)
(m~~ H--I-+-1-+-+-l-+--+-+-1H+-l-+-.j
I>"
14
Fig. 3 -Open loop frequency
response
~r--'---'--,,--.-~
(dB) 1--+----1--..-
- - - - ---1--+----1---1
20H--I-+-1·++-l-+--I--bJI4+-l-+-.j
16H--I-+-1,,+-+-l-+--I-+-1H+·l-+-.j
1214--1-+-1--1 ·+-l-+--I-+-1H+-l-+-.j
':=~=-r-:::~c---~
60
......... OPEN LOOP
40~----I----+---""':~·
Gv =30dB (test circuit)
20. 1----1-----
f----
16
20
'Is
24
(V)
12
·0
16
20
'Is
24
......
A0
(W )1-- f= 40Hz to 15KHz
d=o.s'l,
16
)
41--
f:1KHz
d=IO'I.
RL=4n
RL=4J\7
2
V
o~
8
~
12
16
1/
v
17
vV
/
2
RL=8J\
V
1/
20
/
18
V
.,-
'"
~~
Fig. 5 - Output power vs.
supply voltage
Fig. 4 - Output power vs.
supply voltage
G.3ft3
./
(V)
...... -'
-
OL-__L -__L -__
__
10
10'
10'
~
12
6
'Is
24
Fig. 7
Distortion
output power
o~
(V)
8
vs.
V
i...-- V-
12
16
V
V
V
RL =an
j:24 'Is (V)
20
Fig. 8 - Output power vs.
frequency
0.3701
%
(W)
s=24'
RL=4n
.Q2.,.
10
=01',.
...
o·'m.~~~T.~~
·1 III
0.01
LL.LL.LllL--'--'---'-L1JWl_--'---'
().3
10
1 11'
--
'l.(W)
d",Q2",
.,
.254063
10
18l!i4063
I)'
IliZli 40e
10'
,,2&
10'
~6f~1=-2_______________________ ~ 1~I~mg'l:l:
524
d=0.2,.
1 11'
10
'Oil
!(Hz)
10-'
L,'c".L".1,,,-",,-'--.L,L,.L".1,,,-"-",,,.J,L,,L,,L,.L1.1,I-J,,,
, I,-J",-"l,-l,
10 3
10 4
f(Hz)
--------------------------
TDA1910
Fig. 11 - Output power vs.
input voltage
Fig. 10 - Output power vs.
input voltage
Fig. 12 - Total input noise
vs. source resistance
6_3710
=
Ib: =-- Vs=24V
(W),
Gy=lOdB
'/
"~Ma
')
f.::.:.:.:: ...
1----'I
L-----!--L-!--~~-__:___---'--_7_'__;__'_;~
10·'
10
102
•
Vi
(mY)
10
Fig. 13 - Values of capacitor ex vs. bandwidth (BW)
and gain (G y )
30
50
100 YI(mV)
G_3696
G_3698
SVR
(dB)
Cx
(nF )
" "-
80
.::::: ~
60
"-
.........
I'....
I"-
"-:'\ ~
10KHz
Vs=24V
fripple='IOOHz
RL=4n
Rg =IOKn
.;::::: ~
........
40
Bw=5KHz
r----
SVR
(dB)
I
.:\..
10
Fig. 15 - Supply voltage rejection vs. source resitance
Fig. 14 - Supply voltage rejection vs. voltage gain
r- r----
I
Ll
Vs=24V
RL=4J\
fripple=I00Hz
80
...... ~
60
:
~ f~~~\C3
5}JF
I"--
40
2 F
20
20
15KHz
10·
30KHz
,
20
10
30
40
o
50 Gy(dB)
Fig. 16 - Power dissipation
and efficiency vs. output
power
'I.
1!s=24V
( ',,)
(W) - f=IKHz
RL=811
8
60
/
A l-
4.L F
~o t
(W)
r-
80
/'1.
6
.........
30
20
40
50 Gy(dB)
10'
40
Vs=24V
f=lKHz
RL=4J\.
r-- r-
""
.1
I
~ot
10'
G_JS75
'I.
flot
(',.)
(W )
80
14
V ~
6
/'
'0
V
/RL=41\
40
/
flot
{j
20
12
20
I(
o
16 Ib(W)
12
Rg (Il)
Fig. 18 - Max power dissipation vs. supply voltage
Fig. 17 - Power dissipation
and efficiency vs. output
power
6_3680
6_3731
~ot
o
10
16 Pc,(W)
------------- ~ l~tmg~59J1
o
~
/RL=8 n
...,
./ / '
'6
32
V.(V)
7/12
525
i
i
TDA1910
APPLICATION INFORMATION
Fig. 19 - Application circuit without muting
Fig. 20 - PC board and component lay-out of the
circuit of fig. 19 (1:1 scale)
.v,
2200,uF
C7
3.3
.n
16v
R3
lfl
Vi
Rl=4fl
loon
O.22,uF
R2
C6
S-3613
Vs
RL
Fig. 21 - Application circuit with muting
.Ys
Performance (circuits of fig. 19 and 21)
Po = 12W (40 to 15000 Hz, d "::0.5% )
Vs = 24V
Id = 0.82A
G v = 30 dB
1:..
2 _ _ _ _ _ _ _ _ _ _ _ _ ~ I~tmg,~©~
""8/c.::.
526
-------------
TDA1910
APPLICATION INFORMATION (continued)
Fig. 23 - Frequency reo
sponse of the circuit of
fig. 22
Fig. 22 - Two position DC tone control (10 dB boost 50 Hz and
20 KHz) using change of pin 1 resistance (muting function)
r--------..-----..--------<> ",,··24V
6_''''
Gy
(dB)
r-
,
2
38
C9
16V
1\
I
6
34
BOOST
~
1
III
32
.,
In
f--"
30
ilil l
1111
28
10'
10
0.22/.£
FLAT
10'
C8
C3
5-3617
Fig. 24 - 10 dB 50 Hz boost tone control using change of pin 1
resistance (muting function)
Fig. 25 - Frequency reo
sponse of the circuit of
fig. 24
r--------..-----..--------<> ",,··24V
Rl
Gy
100kll
Flat
(dB )
42
0
38
J6
J4
I
1\8005
2
0
FIJ;
I
I
8
10
100n
10 4
10'
10'
f(Hz)
RS
Fig. 26 - Squelch function in TV applications
Fig. 27 - Delayed muting circuit
,----~r--------OYs~.24V
Rl
lOOkll.
C7
I
o.1,uF
'"
C9
etO
••,n
2200~F
'"
------------- ~ ~~;mg,~ ___________
--"-'9/'-'=12
527
TDA1910
MUTING FUNCTION
The output signal can be inhibited applying a DC voltage VT to pin 11, as shown in fig. 28
Fig. 28
Your
Vsl2
Muting
on
The input resistance at pin 1 depends on the threshold voltage VT at pin 11 and is typically.
Rl = 200 Kn
@
1.9V";; VT
.,;;
OV.,;; VT
6V";;V T
.,;;
4.7V
muting-off
1.3V
";; Vs
muting-on
Referring to the following input stage, the possible attenuation of the input signal and therefore of the
output signal can be found using the following expression.
where R5
~
100 Kn
Considering Rg = 10 Kn the attenuation in the muting-on condition is typically AT= 60 dB. In the
muting-off condition, the attenuation is very low, typically 1.2 dB.
A very low current is necessary to drive the threshold voltage VT because the input resistance at pin 11
is greater than 150 Kn. The muting function can be used in many cases, when a temporary inhibition
of the output signal is requested, for example:
in switch-on condition, to avoid preamplifier power-on transients (see fig. 27)
- during commutations at the input stages.
- during the receiver tuning.
The variable impedance capability at pin 1 can be useful in many applications and we have shown 2
examples in fig. 22 and 24, where it has been used to change the feedback network, obtaining 2 different
frequency responses .
.:..10::.:./.:.;12=--_ _ _ _ _ _ _ _ _ _ _
528
~ !fi~;mg~SJ»Jl-------------
TDA1910
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 21. Different
values can be used.
The following table can help the designer.
Component
Recomm.
value
Larger than
recommended value
Smaller than
recommended value
Input signal imped.
for muting operation
I ncrease of the attenuation in muting-on
condition.Decrease of
the input sensitivity.
Decrease of the attenuation in muting
on condition.
Purpose
Rg +R1
10Kn
R2
3.3Kn
Close loop gain
setting.
Increase of gain.
Decrease of gain.
Increase quiescent
current.
R3
lOOn
Close loop gain
setting.
Decrease of gain.
I ncrease of ga in.
R4
1.11
Frequency stabil ity
Danger of oscillation
at high frequencies
with inductive loads.
P1
20Kn
Volume potentiometer.
I ncrease of the
switch-on noise.
C1
C2
C3
ljlF
ljlF
0.22jlF
C4
2.2jlF
Inverting input DC
decoupling.
C5
O.ljlF
Supp Iy vo Itage
bypass.
C6
10 jlF
Ripple Rejection.
C7
47jlF
Cs
0,22jlF
Cg
2200 JjF
(R L = 4.11)
1000 JjF
(R L = Sn)
Input DC
decoupling.
Decrease of the input
impedance and the
input level.
Allowed range
Min.
Max.
9 R3
R 2/9
10Kn
100Kn
Higher low frequency cutoff.
I ncrease of the
switch-on noise.
Higher low frequency cutoff.
0.1 JjF
Danger of
oscillations.
Degradation of
SVR.
2.2 JjF
100JjF
Bootstrap.
I ncrease of the distortion at low frequency.
10JjF
100 JjF
Frequency stability.
Danger of oscillation.
Output DC
decoupling.
Higher low frequency cutoff.
I ncrease of SVR.
I ncrease of the
switch-on time.
- - - - - - - - - - - - - ;:;i, ~~~~m~m~~
11/12
529
I.
TDA1910
THERMAL SHUT-DOWN
The presence of a thermal limiting circuit offers the following advantages:
1) An overload on the output (even if it is permanent), or an above limit ambient temperature can be
easily supported since the Tj cannot be higher than 150"C.
2) The heatsink can have a smaller factor of safety compared with that of a conventional circuit. There
is no possibility of device damage due to high junction temperature.
.
If for any reason, the junction temperature increases up to 150°C, the thermal shut-down simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its ther·
mal resistance); fig. 31 shows this dissipable power as a function of ambient temperature for different
thermal resistance.
Fig. 29 - Output power and
drain current vs. case temperature
...... '
12
Fig. 30 - Output power and
drain current vs. case temperature
6_3677
10
\
0.8
~
0.6
Q4
1\
20 40 60 80 100 120 140 Tc••e(OC)
0.2
a
Po
Id
Q8
.....,
,
1\
0.6
0.4
Q2
20 40 60 80 100 120 140 Tcase('C)
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be removed by adding an external heatsink.
Thanks to the Multiwatt@ package attaching the heatsink is very simple, a screw or a compression
spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of siljcon
grease, to optimize the thermal contact; no electrica,l isolation is needed between the two surfaces .
=--___________ ~ ~~tm~~lf -------------
12:.!o/.!C
12
.!C
530
.."='=
.,L SeiS-THOMSON
[iI'51]D©OO@rn[Lrn©'[i'OO@li\DD©~
TDA2002
8W CAR RADIO AUDIO AMPLIFIER
NOT FOR NEW DESIGN
The TDA2002 is a class B audio power amplifier
in Pentawatt® package designed for driving low
impedance loads (down to 1.6.Q).
Protection against:
a)
b)
c)
d)
The device provides a high output current capability (up'to 3.5A), very low harmonic and
cross-over distortion.
short circuit;
thermal over range;
fortuitous open ground;
load dump voltage surge.
See TDA2003 for more complete information.
In addition, the device offers the following
features:
- very low number of external comj)onents
- assembly ease, due to Pentawatt® power
package with no electrical insulation requirement
space and cost savi ng
high reliability
flexibility in use
Pentawatt
ORDER CODE: TDA2002H (Hor. Pentawatt)
TDA2002V (Ver. Pentawatt)
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10
10
Ptot
T stg , T j
Peak supply voltage (50 ms)
DC supply voltage
Operating supply voltage
Output peak current (repetitive)
Output peak current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature
40
v
28
V
18
V
3.5
4.5
15
-40 to 150
A
A
W
°C
Fig. 1 - Application circuit
r---.----.---o. v
100.,.1-,
C3
5
100
IJFI InF
R.
June 1988
= 20· R2
1
;
C.
= 21TBRI
S -1899/2
1/2
531
TDA2002
ELECTRICAL CHARACTERISTICS (Vs= 14.4V, T amb = 25°C unless otherwise specified)
I
Test conditions
Parameter
Min.
I
Typ.
I
Max.
I I
Unit
DC CHARACTERISTICS (Refer to DC test circuit)
Vs
Supply voltage
Vo
Quiescent output voltage (pin 4)
Id
Quiescent drain current (pin 5)
18
8
6.1
V
6.9
7.7
V
45
80
mA
AC CHARACTERISTICS (Refer to AC test circuit, Gy= 40 dB)
Output power
Po
d = 10%
f = 1 kHz
AL=4!l
A L =2!l
4.8
7
Vs=16V
I nput saturation voltage
Po = 0.5W
Po = 0.5W
Po = 5.2W
Po=8W
Frequency response
(-3 dB)
AL=4!l
Po= 1W
Distortion
f = 1 kHz
Po = 0.05 to 3.5W AL=4!l
Po = 0.05 to 5W
AL= 2!l
Input sensitivity
B
d
W
W
mV
300
f = 1 kHz
AL=4!l
AL=2!l
AL=4!l
AL=2!l
Vi
W
W
6.5
10
AL=4!l
A L =2!l
Vi (rms)
5,2
8
15
11
55
50
mV
mV
mV
mV
40 to 15000
Hz
0.2
0.2
%
%
70
150
k!l
39.3
40
AI
I nput resistance (pin 1)
f = 1 kHz
Gv
Voltege gain (open loop)
AL=4!l
f =1 kHz
Gv
Voltage gain (closed loop)
AL=4!l
f = 1 kHz
eN
Input noise voltage
(*)
4
JJV
iN
Input noise current
(*)
60
pA
"l
Efficiency
68
58
%
%
SVR
Supply voltage rejection
35
dB
Po = 5.2W
Po= 8W
f = 1 kHz
A L =4!l
A L =2!l
AL=4!l
Ag= 10 k!l
frlPPle= 100 Hz
dB
BO
30
40.5
dB
(*) Filter with noise bandwidth: 22 Hz to 22 KHz.
=2/~2~
532
______________________
~~~~~~~
__________________________
TDA2003
10W CAR RADIO AUDIO AMPLIFIER
The TDA 2003 has improved performance with
the same pin configuration as the TDA 2002.
The additional features of TDA 2002, very low
number of external components, ease of assembly,
space and cost saving, are maintained.
The device provides a high output current capability (up to 3.5A) very low harmonic and crossover distortion.
Completely safe operation is guaranteed due to
protection against DC and AC short circuit between all pins and ground, thermal over-range,
load dump voltage surge up to 40V and fortuitous
open ground.
Pentawatt
ORDERING NUMBERS: TDA 2003H
TDA2003V
ABSOLUTE MAXIMUM RATINGS
v.
V.
V.
10
10
Ptot
Tstg. TJ
Peak supply voltage (50 ms)
DC supply voltage
Operating supply voltage
Output peak current (repetitive)
Output peak current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature
40
28
18
3.5
4.5
20
-40 to 150
V
V
V
A
A
W
°C
TEST CIRCUIT
r---1~-_---<
ex =
June 1988
2TfSRl
.vs
5 - 3205
1/9
533
TDA2003
CONNECTION DIAGRAM
(top view)
'" ~$
.
II
..
5~!!!1~~
:,
I
:
: 'm'~'''~~~~
SUPPLY
VOLTAGE
NON INVERTING
INPUT
5-1694/1
tab connected to pin 3
SCHEMATIC DIAGRAM
RIO
06
+-+--t--f---t--I(Q1S
Z4
R9
R2
02
Rl
5-3172
THERMAL DATA
Rth
j-case
534
Thermal resistance junction-case
max
3
TDA2003
DC TEST CIRCUIT
AC TEST CIRCUIT
100nF
-470",F
RJ
R2
In
5-3168
R x =20'R2
5 - 3205
ELECTRICAL CHARACTERISTICS (Vs= 14.4V, T amb = 25°C unless otherwise specified)
Parameter
Test conditions
Min.
Typ.
Max.
I I
Unit
DC CHARACTERISTICS (Refer to DC test circuit)
Vs
Supply voltage
Vo
Quiescent output voltage (pin 4)
Id
Quiescent drain current (pin 5)
8
6.1
18
V
6.9
7.7
V
44
50
rnA
AC CHARACTERISTICS (Refer to AC test circuit, Gv = 40 dB)
Po
Output power
Vi(rms)
Input saturation voltage
Vi
I nput sensitivity
---------------------------
d= 10%
f = 1 kHz
R L =40
R L =20
R L = 3.20
R L = 1.60
5.5
9
6
10
7.5
12
300
f = 1 kHz
Po = 0.5W
Po =6W
Po = 0.5W
Po = lOW
R L =40
RL=40
R L =20
R L =20
~~~I~~~~©~
W
W
W
W
rnV
14
55
10
50
________________________
mV
rnV
mV
mV
~~~9
535
TDA2003
ELECTRICAL CHARACTERISTICS (continued)
B
Frequency response (-3 dB)
d
Po = lW
A L =40
Distortion
f = 1 kHz
Po= 0.05 to 4.5W
Po= 0.05 to 7.5W
Ai
Input resistance (pin 1)
f = 1 kHz
Gv
Voltage gain (open loop)
f = 1 kHz
f = 10 kHz
Gv
Voltage gain (closed loop)
f = 1 kHz
AL =40
eN
Input noise voltage
iN
Input noise current
'I
Efficiency
SVA
Min.
Test conditions
Parameter
A L =40
A L =20
70
Typ.
Max.
Unit
40 to 15,000
Hz
0.15
0.15
%
%
150
kO
80
60
dB
dB
40
40.3
dB
(0)
1
5
!LV
(0)
60
200
pA
Supply voltage rejection
39.3
f = 1 kHz
Po=6W
Po= lOW
AL=40
AL=20
f=100Hz
V rlpple= 0.5V
A g= 10 kO
A L =40
30
69
65
%
%
36
dB
(0) Filter with noise bandwidth: 22 Hz to 22 kHz
Fig. 1 - Quiescent output
voltage vs. supply voltage
Fig. 2 - Quiescent drain current vs. supply voltage
Fig. 3 - Output power vs.
supply voltage
G-U12
v.
p.
15
R =1.611
Gv:loOdB
f ,,1kHz
d=10"l.
2ft
3.2
10
ID
12
" v.ey)
-'4/_9_ _ _ _ _ _ _ _ _ _ _ _
536
,.
12
14
16
V.CY)
10
15
Vs(Vl
~ !~i~m~'f~~JI-------------
TDA2003
Fig. 4 - Output power vs.
load resistance RL
Po
Fig.5 - Gain vs. input sensitivity
G,
Fig. 6 - Gain vs. input sensitivity
G,
By =40
G,
" 4.4\1
f ~lkHz
d =10-"
"
f =lkHz
54
Vs =1611
"
500
RL=4A
50
46
100
"
" . .5
30
50
22
10
30
100
3'"
. ..
20
ID
Vs .,14.4
Gv =40dB
R ,,2 ... nd4fl
1.2
-20
0.8
-30
frlpple" 100Hz
Rg-'OKO
R2 =-2.2!l
./
./v
4.
-50
10
10'
10'
10'
30
t(Hz)
Fig. 11 - Power dissipation
and efficiency vs. output
power (R L = 40)
3S
H+-l-+-f-c...-:i-+-i
-20
50
G.,(dB)
v: 40dB
f :lkHz
RLIt 2Il
~-+·~L~·4~n~...L+-hJ~...L+-~-+~w
G =40dB
..
V. :14.4Y
(W)
ro
t= 1kHz
Rg .,OkA
V V
Fig. 12 - Power dissipation
and efficiency vs. outpUt
power (R L = 20)
~11J~-- - -+++-r--+-+++-1;!,.,
~=40dB
V
l,...-V
•. 5
(W)
Vr iPplE'=o.5V
I----
-40
O.
Ptot
Vs =14.4Y
Vi (mY)
./
Fig. 10 - Supply voltage
rejection vs. frequency
I--o I--I---
300
Vs=14.4V
-10
I----
~m
sv.
100
Fig. 9 - Supply voltage rejection vs. voltage gain
,-sv•
Ll•...LlliLL_...L-L...LLLLLLL--1,--l
~
30
(dB)
I--I---
~I"
..
26
10
(.,.)
~~
1 0 1L=3.2Jl
l_1
t
Jl.
1.6
5.
.O,5W
22
10-31"
•
100
"'lOW
34
Yj(mY)
Fig. S - Distortion vs. frequency
Fig. 7 - Distortion vs. output power
200
30
2B
•
500
38
34
RL(M
200
.'W
42
'V
54
50
"
,.
14.4Y
12V
MI
G,
(dB!
(W)
i 1--++-+---+-150
w
80
P, 1
R2=2.211
-40
40
R2 "In
-.0
20
10
-.0
10
10'
IO~
f (Hz)
~ !~tm?:I~~JI
____________
::.:..:5/9
537
TDA2003
Fig. 14 - Maximum allowable
power dissipation vs. ambient temperature
Fig. 13 - Maximum power
dissipation vs. supply voltage
(sine wave operation)
Fig. 15 - Typical values of
capacitor (C x ) for different
values of frequency response
(B)
6-3819
C,
(W)
(W)
IS
IS
I.ft
10
··
(nF )
10
10
,ft
10·C/W
3.211
·
··,
,
10
IS
VaCV)
so
100
B= OKH2
r-..
l'--,
r--.... r-..
...............
~
i'-- .........
20KHz
R2=2.21l
"
48
G,(dB)
APPLICATION INFORMATION
Fig. 16 - Typical application
circuit
470pF
I
3V:
I
L ____________ i
R~
.
0
20 • R2
i
C.
Fig. 17 - P.C. board and component layout for the
circuit of fig. 16 (1: 1 scale)
R3
In
I
= 2TIBRI
Fig. 18 - 20W bridge configuration application circuit (*)
Fig. 19 - P.C. board and component layout for the
circuit of fig. 18 (1: 1 scale)
R116/\
(*) The values of the capacitors
C3 and C4 are different to optimize the SVR (Typ.= 40 dB)
~6/~9________________________ ~~~~~~:~~~
538
__________________________
TDA2003
APPLICATION INFORMATION (continued)
Fig. 20 - Low cost bridge configuration application circuit (* ) (Po = 18W)
(*) In this application the device can support a short circuit between every side of
the loudspeaker and ground.
Fig. 21 - P.C. board and component layout for the low-cost bridge amplifier of fig. 20, in stereo version
(1:1 scale)
CS-0103/3
TDA 2003
1m,
C3
C5
-c=::>-
c:::::J
c::=::::J
004
Cl
m
lOA 2003
rtlllA2OO3
. C2
c:::::J
-c::JRl
TOA'2003
~
C7
C6
C2
i
-c:::::r
Rl
C6
.c::::,:::::Y
Q. C4
' "
C3~
,C:::::> C5
~
c:::::J
Cl
BUILT-IN PROTECTION SYSTEMS
Load dump voltage surge
The TDA 2003 has a circuit which enables it to
withstand a voltage pulse train, on pin 5, of the
type shown in fig. 23.
If the supply voltage peaks to more than 40V,
then an LC filter must be inserted between the
supply and pin 5, in order to assure that the
pulses at pin 5 will be held within the limits
shown in fig. 22.
___________________________
A suggested LC network is shown in fig. 23. With
this network, a train of pulses with amplitude up
to 120V and width of 2 ms can be applied at
point A. This type of protection is ON when the
supply voltage (pulsed or DC) exceeds 18V. For
this reason the maximum operating supply
voltage is 18V.
~~~~~~&~~~
________________________
~7/9
539
TDA2003
Fig. 22
Fig. 23
Vs(V)
40~
__
1,1=50ms
12 =1000ms
FROM
A
L=2mH
'
SUPPLY ~TO PIN 5
dJi,nM
3000 l'F
LINE
5-1901
14.4
I
16V
5-190011
Short-circuit (AC and DC conditions)
The TDA 2003 can withstand a permanent
short-circuit on the output for a supply voltage
up to 16V.
Polarity inversion
High current (up to 5A) can be handled by the
device with no damage for a longer period than
the blow-out time of a quick 1A fuse (normally
connected in series with the supply).
This feature is added to avoid destruction if,
during fitting to the car, a mistake on the connection of the supply is made.
Open ground
When the radio is in the ON condition and the
ground is accidentally opened, a standard audio
amplifier will be damaged. On the TDA 2003
protection diodes are included to avoid any
damage.
Inductive load
A protection diode is provided between pin 4
and 5 (see the internal schematic diagram) to
Fig. 24 - Output power and
drain current vs. case temperature (RL = 40')
allow use of the TDA 2003 with inductive loads.
In particular, the TDA 2003 can drive a coupling
transformer for audio modulation.
DC voltage
The maximum operating DC voltage on the
TDA 2003 is 18V.
However the device can withstand a DC voltage
up to 28V with no damage. This could occur
during winter if two batteries were series con·
nected to crank the engine.
'
Thermal shut-down
The presence of a thermal limiting circuit offers
the following advantages:
1) an overload on the output (even if it is per·
manent), oran excessive ambient temperature
can be easily withstood.
2) the heat-sink can have a smaller factor compared with that of a conventional circuit.
There is no device damage in the case of excessive junction temperature: all that happens
is that Po (and therefore P tot ) and Id are
reduced.
Fig. 25 - Output power and
drain current vs. case temperature (RL = 20)
I,
..
(A)
" H-+-H+-H-+-+
'0
H-+-H-+-+-++++-++I-+--l-'.8
,0
.00
Tease{"C)
~8/:.:::9 _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~mg=:
540
50
.00
leuet"C)
-------------
TDA2002
PRATICAL CONSIDERATION
Printed circuit board
The layout shown in fig. 17 is recommended. If
different layouts are used, the ground points of
input 1 and input 2 must be well decoupled from
the ground of the output through which a rather
high current flows.
Assembly suggestion
No electrical insulation is required between the
package and the heat-sink. Pin length should be
as short as possible. The soldering temperature
must not exceed 260°C for 12 seconds.
Application suggestions
The recommended component values are those
sjown in the application circuits of fig. 16.
Different values can be used. The following table
,is intended to aid the car-radio designer.
Component
Recommended
value
Cl
2.21'F
Input DC
decoupling
Noise at switch-on,
switch-off
C2
470l'F
Ripple rejection
Degradation of SVR
C3
0.1 I'F
Supply bypassing
Danger of oscillation
C4
1000l'F
Output coupling to
load
Higher low frequency
cutoff
C5
O.lI'F
Frequency stability
Danger of oscillation at
high frequencies with
inductive loads
Cx
Rl
1
2". B Rl
""
(G v-l)· R2
R2
2.2
R3
Rx
""
n
Purpose
Upper frequency
cutoff
Larger than
recommended value
Lower bandwidth
Setting of gain
Degradation of SVR
1n
Frequency stability
Danger of oscillation at
high frequencies with
inductive loads
20 R2
Upper frequency
cutoff
Poor high frequency
attenuation
__
Larger bandwidth
Increase of drain current
Setting of gain and
SVR
----------------------~
Smaller than
recommended value
~I~I~~~~
Danger of oscillation
________________________
9~/9
541
TDA2004
10+10W STEREO AMPLIFIER FOR CAR RADIO
- overrating chip temperature;
- load dump voltage surge;
- fortuitous open ground;
Space and cost saving: very low number of external components. very simple mounting system
with no electrical isolation between the package
and the heatsink.
The TDA2004 is a class B dual audio power
amplifier in MULTIWATT@package specifically
designed for car radio applications; stereo amplifiers are easily designed using this device that
provides a high current capability (up to 3.5Ai
and that can drive very low impedance loads
(down to 1.6m.
Its main features are:
Low distortion.
Low noise.
High reliability of the chip and of the package
with additional safety during operation thanks
to protections against:
- output AC short circuit to ground;
- very inductive loads
Multiwatt-11
ORDERING NUMBER: TDA2004
ABSOLUTE MAXIMUM RATINGS
v.
V.
V.
10 (*)
10 (*)
Ptot
Tj , Tstg
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50ms)
Output peak current (non repetitive t = 0.1 ms)
Output peak current (repetitive f ;;.. 10Hz)
Power dissipation at Tcase = 60°C
Storage and junction temperature
18
28
40
4.5
3.5
30
-40 to 150
V
V
V
A
A
W
°c
(*) The max. output current is internally limited.
CONNECTION DIAGRAM
(Top view)
~
BOOTSTRAP I
OUTPUT i
+Vs
OUTPUT 2
BOOTSTRAP 2
"
10
9
8
GND
INPUT+(2)
INPUT-(2)
SVRR
INPUT+(1l
INPUT-(I)
to pin 6
June 1988
5-342012
1/7
543
TDA2004
Fig. 1 - Test and application circuit
5-408813
Fig. 2 - PC board and components layout (scale 1: 1)
GND
IN
(L)
GND
IN
(R)
.Vs
!o2/~7_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m&~lt
544
-------------
TDA2004
THERMAL DATA
max
Thermal resistance junction-case
3
°C!W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Gy= 50 dB,
Rth (heatslnk) = 4°C/W, unless otherwise specified)
Parameter
Test conditions
Vs
Supply voltage
Vo
Quiescent output voltage
Vs = 14.4V
Vs = 13.2V
Id
Total quiescent drain current
Vs = 14.4V
Vs = 13.2V
IS8
Stand-by current
Pin 3 grounded
Po
Output power (each channell
f = 1 KHz
Vs = 14.4V
Min.
Typ.
Max.
Unit
18
V
7.').
6.6
7.8
7.2
V
V
65
62
120
120
rnA
rnA
8
6.6
6.0
rnA
5
d= 10%
R L =4n
R L = 3.2n
R L =2n
R L = 1.6n
6
7
9
10
6.5
8
10(-)
11
W
W
W
W
6
9
6.5
10
W
W
12
W
Vs = 13.2V
R L = 3.2n
R L = 1.6n
Vs=16V
RL=2 n
d
CT
Distortion (each channell
f = 1 KHz
Vs = 14.4V
Po= 50 mW to
Vs = 14.4V
Po= 50 mW to
Vs = 13.2V
Po= 50 mW to
Vs = 13.2V
Po= 50 mW to
Cross talk
Vs = 14.4V
Vo= 4 V rms
f = 1 KHz
f = 10 KHz
Vi
Input saturation voltage
RI
I nput resistance (non inverting
input)
f = 1 KHz
fL
Low frequency roll off (-3 dB)
R L =4n
R L =2n
R L = 3.2n
R L = 1.6n
fH
High frequency roll off
Gy
Voltage gain (open loop)
(~3
R L =4n
4W
R L = 2n
6W
R L =3.2n
3W
R L = 1.6n
6W
0.2
1
%
0.3
1
%
0.2
1
%
0.3
1
%
R L = 4n
Rg = 5 Kn
50
40
dB
dB
60
45
300
dB)
-------------
RL = 1.6n to 4n
f = 1 KHz
~ I~tm~©~
70
mV
200
Kn
35
50
40
55
15
Hz
Hz
Hz
Hz
KHz
90
dB
____________
3=.:..:../7
545
TDA2004
ELECTRICAL CHARACTERISTICS (continued)
Parameters
Test conditions
Min.
Typ.
Max.
Unit
48
50
51
dB
5
/LV
f = 1 KHz
Voltage gain (closed loop)
Gv
0.5
Closed loop gain matching
Total input noise voltage
Rg= 10 Kn(O)
SVR
Supply voltage reiection
f riPPle= 100 Hz Rg- 10 Kn
C3= 10 /LF
V ripple=0.5V rms
Efficiency
Vs = 14.4V
R L =4n
R L = 2n
Vs = 13.2V
R L = 3.2n
R L = 1.6n
1)
35
f = 1 KHz
Po= 6.5W
Po= lOW
f = 1 KHz
Po= 6.5W
Po= lOW
Thermal shut down junction
temperature
Tj
dB
1.5
eN
45
dB
70
60
%
%
70
60
%
%
°c
145
(*) 9.3W without bootstrap. .
(0) Bandwidth filter: 22 Hz to 22 KHz.
Fig. 4 - Quiescent drain
current vs. supply voltage
Fig. 3 - Quiescent output
voltage vs. supply voltage
I,
Vo
(VI
;/
V
/
V
V
rI
d
{OW
(mAl
IIIII
,.IKHz
100
I--
I
V
60
--
f-"-
II
'o'5 .,3.2V RL,)·Zlt
Gv·SOd~
",s"u.VRL·t.n
.0
;/
II
11111
f-
"'5.13.2 ... Rl'tSfl
"'5' 14,4V RL• 20
40
/
V
Fig. 5 - Distortion vs. output power
;/
10
"
12
10
Fig. 6 - Output power vs.
supply voltage
Po
(W 1
"
I
hUtH:;r:
f--
G~50dB
IV
d ~1O.,.
I
12
12
V
"
Gv~50dB
0.1
Fig. 8 - Distortion vs. frequency
V
12
V
V
V
/
V
VRl~3.2n
./
V
./
V
,/
V
V
10
546
0,01
RL~1.6.nV
d~10·1.
VRL~n
./
\lSI V)
blr(Hz
-
./
,/
16
Fig. 7 - Output power vs.
supply voltage
Po
I
(WI
RL~zn/
V
V
14
12
10
12
16
VS(VI
10
10'
10'
f(Hz!
TDA2004
Fig. 9 - Distortion vs. frequency
d
C"1o)
(dB)
Vs"IJ.2V
ee-
VS,14l,V
10
Gv:.50dB
R"'=r?n
30
50
60
0.4
10'
10
JO'
10'
III
III
!
VS,ll..J,V
RL,,4n
Rg.IOKn
Gy .39O/lfi
'ripple-.lOOHz
RL"J.n
Rg.lOKn
GV"OOQ/10Jl
f rippl.·100H z
~~
11
30
20
40
,/
CZ,!ipF
V
.#
20
Fig. 14
sensitivity
I (Hz)
Gain vs. input
G,
.".
f .1kHz
/
200
~2.5tJF
<00
so
Y
'/
_
10
10
20
;:S5~j--HJl·t]]++JJ"]]]]]]]]]]J
-tt'
31
300
,20
Vj(mV)
Fig. 17 - Total power dissipation and efficiency vs.
output power
,."."
{:~ H-+++-H-+++-+-H+-1-.J-.-j {~,
pto{
(W,
,
:: E:tT~'~Ltt~.11<;• ~,!-;:-rfi\S:~J:B,HE
20
••
100
20
Fig. 16 - Total power dissipation and efficiency vs.
output power
Fig. 15 - Maximum allowable power dissipation vs.
ambient temperature
500
RL"4A
/!:/r
/
20
JO'
'0
C2.22/J~
/
30
~
Rg.IOKA
/ C 2, 22011
50
C2'22~
40
40
l--l--
\!s.14.4V
cT /
-
~
30
Fig. 13 - Supply voltage
rejection vs. values of capacitors C2 and C3
SVA
(dBI
CJ"lO,uF
Rg=O
10
f(Hz)
Fig. 12 - Supply voltage
rejection vs. values of capacitors C2 and C3
Gv=50dB
60
-
PQ2.5~b
RL,12
Vs,1J··4V
SO
........
40
0,
50
I-
Gy.SOdB
Rg .1011.0
p. ,Z.5W
,
SVA
(dBlf--
Vrippie· O.5V
1.2
{dB
I
!rippl• • 100Hz
20
sv R
zt
5,"
r-
Fig. 11 - Supply voltage
rejection vs. frequency
Fig. 10 - Supply voltage
rejection vs. C3
~:~LtJ
~.,,~~
: ~ LL~
tb
"
12H
tlJ oe "(-'
I..,.....
.,.
;11',
60
10
I
tot
"'oJ
,71-"
"r"
i-v
"
-f;/1ill
Y'
RL"Zfi
~l
~r
40
VS·144V
40
H-+-¥'j-H-+++-HH{~!~.:~
H-+.A-+-H-+++-HHhlKHz
H-A-+++--++-1-+-H G.,..SOd~
~hlKHz
Gv·SOdB
20
20
r t-'
50
100 Tamb(-CJ
12
16
20
24
~ !~~~m&~~:
Po(W)
10
12
____________
-=.!5/:.:,.7
547
TDA2004
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 1.
Different values can be used; the following table can help the designer.
Component
Recomm.
value
RI
120Kn
Rl and R4
1 Kn
Purpose
Optimisation of the
output signal simmetry
Larger than
Smaller than
Smaller Po max
Smaller Po max
Increase of gain
Decrease of ga in
Decrease of gain
Increase of gain
Close loop gain setting (*j
R3 and Rs
3.3 n
R6 and R7
1n
CI and C2
Frequency stability
Danger of oscillation at
high frequency with
inductive load
2.2"F
Input DC decoupling
High tum-on delay
High turn-on pop
Higher low frequency
cutoff. Increase of noise.
C3
1O"F
Ripple rejection
Increase of SVR.
Increase of the switch-on
time.
Degradation of SVR.
C4 and C6
100 "F
Bootstrapping
Cs and C7
100"F
Feedback Input DC
decoupling.
Cg and C9
O.l"F
Frequency stability.
Danger of oscillation.
CIO and
CII
1000j.lF to
2200"F
Output DC decoupling.
Higher low-frequency
cut-off.
Increase of distortion
at low frequency.
(*j The closed-loop gain must be higher than 26dB
~6/~7________________________ ~~~1~~~~
548
__________________________
TDA2004
BUILT-IN PROTECTION SYSTEMS
Load dump voltage surge
Polarity inversion
The TDA2004 has a circuit which enables it to
withstand a voltage pulse train, on pin 9, of the
type shown in Fig. 19.
High current (up to 10A) can be handled by the
device with no damage for a longer period than
the blow-out time of a quick 2A fuse (normally
connected in series with the supply). This feature
is added to avoid destruction, if during fitting to
the car, a mistake on the connection of the
supply is made.
If the supply voltage peaks to more than 40V,
then an LC filter must be inserted between the
supply and pin 9, in order to assure that the
pulses at pin 9 will be held within the limits
shown.
A suggested LC network is shown in Fig. 18.
With this network, a train of pulse with ampli·
tude up to 120V and with of 2ms can be applied
to point A. This type of protection is ON when
the supply voltage (pulse or DC) exceeds 18V.
For this reason the maximum operating supply
voltage is 18V.
Open ground
When the radio is the ON condition and the
ground is accidentally opened, a standard audio
amplifier will be damaged. On the TDA2004
protection diodes are included to avoid any
damage.
Inductive load
A protection diode is provided to allow use of
the TDA2004 with inductive loads.
Fig. 18
FROM
A
DC voltage
l=2mH
SUPPLY ~TO PIN9
dl;'M'
3000 "F
LINE
5-190111
I
16V
The maximum operating DC voltage on the
TDA2004 is 18V.
However the device can withstand a DC voltage
up to 28V with no damage. This could occur
during winter if two batteries are series connected to crank the engine.
Thermal shut-down
Fig. 19
The presence of a thermal limiting circuit offers
the following advantages:
1) an overload on the output (even if it is permanent). or an excessive ambient temperature
can be easily withstood.
14.4
Short circuit (AC conditions)
The TDA2004 can withstand an accidental shortcircuit from the output to ground caused by a
wrong connection during normal working.
2) the heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no device damage in the case
of excessive junction temperature: all that
happens is the Po (and therefore P tot ) and Id
are reduced.
The maximum allowable power dissipation
depends upon the size of the external heatsink
(i.e. its thermal resistance); Fig. 20 shown this
dissipable power as a function of ambient temperature for different thermal resistance.
549
TDA2005
20W BRIDGE AMPLIFIER FOR CAR RADIO
The TDA2005 is class B dual audio power
amplifier in MUL TIWATT® package specifically
designed for car radio application: power booster
amplifiers are easily designed using this device
that provides a high current capability (up to
3.5A) and that can drive very low impedance
loads (down to 1.6n in stereo applications)
obtaining an output power of more than 20W
(bridge configuration).
Flexibility in use: bridge or stereo booster
amplifiers with or without boostrap and with
programmable gain and bandwidth.
Space and cost saving: very low number of
external components, very simple mounting
system with no electrical isolation between the
package and the heatsink (one screw only).
In addition, the circuit offers loudspeaker protec'
tion during short circuit for one wire to ground.
High output power: Po = 10 + 10W @ RL = 2n,
d 10%; Po 20W @ RL 4n, d 10%.
=
=
=
=
High reliability of the chip and package with ad·
ditional complete safety during operation thanks
to protection against:
-
Multiwatt-11 ®
output DC and AC short circuit to ground;
overrating chip temperature
load dump voltage surge
fortuitous open ground
very inductive loads
ORDERING NUMBERS:
TDA2005M - Bridge application
TDA2005S - Stereo application
ABSOLUTE· MAXIMUM RATINGS
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50ms)
Output peak current (non repetitive t = 0.1 ms)
Output peak current (repetitive f ~ 10Hz)
Power dissipation at T case = 60°C
Storage and junction temperature
18
v
28
V
V
40
4.5
3.5
30
-40 to 150
A
A
W
°c
("' The max. output current is internally limited.
CONNECTION DIAGRAM
(Top view)
/-l=~~:~~~
1===
BOOTSTRAP 1
OUTPUT 1
+Vs
OUTPUT 2
BOOTSTRAP 2
GND
.5
June 1988
lNPUT+(2l
INPUT·(2l
SVRR
INPUT-(/)
INPUh(ll
1/17
551
TDA2005
SCHEMATIC DIAGRAM
THERMAL DATA
Rth j-case
~2/~1~7
552
Thermal resistance junction-1:ase
________________________
~1~~~?~~~
max
3
°C/W
___________________________
TDA2005
BRIDGE AMPLIFIER APPLICATION (TDA 2005M)
Fig. 1 - Test and application circuit (Bridge amplifier)
INPUT
~"
.3'-"'-,1-1----1
C?,It-
l.
2,2,uF
~3V 5
.1.
2.2A1F
5- 4 0 8 613
Fig.2 - P.C. board and component layout (scale 1:1)
-----------------------------
~~~~~~?~:~~Jl
________________________
~3~/l~7
553
TDA2005
ELECTRICAL CHARACTERISTICS (Refer t9 the bridge application circuit. T amb = 25°C.
Gv = 50 dB. Rth (heatsink)= 4°C/W. unless otherwise specified).
Parameters
Test conditions
Min.
Typ.
Max.
Unit
Vs
Supply voltage
Vos
Output offset voltage(o}
(between pin 8 and 10)
Vs = 14.4V
Vs = 13.2V
Id
Total quiescent drain current
Vs = 14.4V
R L =4,n
Vs = 13.2V
RL= 3.2,n
d = 10%
f = 1 KHz
Vs = 14.4V
R L = 4,n
RL = 3.2,n
18
20
20
22
W
W
Vs = 13.2V
RL= 3.2,n
17
19
W
Output power
Po
Distortion
d
I nput sensitivity
Vi·
f = 1 KHz
Po= 2W
Po=2W
I nput resistance
f = 1 KHz
fL
Low frequency roll off (-3 dB)
RL=3.2.n
fH
High frequency roll off (-3 dB)
R L =3.2,n
Gv
Closed loop voltage gain
f = 1 KHz
RL= 4,n
R L = 3.2,n
150
150
75
150
mA
70
160
mA
1
%
1
%
mV
mV
9
8
K,n
70
40
dB
50
eN
Total input noise voltage
Rg= 10 K,n(oo}
Supply voltage rejection
Rg= 10 K,n
C4 = 10p.F
frlPPle= 100 Hz
V rlpple= 0.5 V
11
Efficiency
3
Vs=14.4V
Po = 20W
Po = 22W
Vs = 13.2V
Po = 19W
f = 1 KHz
R L =4,n
RL= 3.2,n
f = 1 KHz
R L = 3.2,n
Tj
Thermal shut~own junction
temperatu re
Vs = 14.4V
f = 1 KHz
R L = 4.11
Ptot = 13W
VOSH
Output voltage with one side
of the speaker shorted to grou nd
Vs = 14.4V
Vs= 13.2V
R L = 4,n
RL= 3.2,n
45
Hz
KHz
20
SVR
10
p.V
55
dB
60
60
%
%
58
%
145
°C
2
V
For TDA 2005M only.
Bandwidth filter: 22 Hz to 22 KHz.
~4/~1~7________________________ ~~~~~?~~n
554
V
mV
mV
f = 1 KHz
R L =4.n
Vs = 14.4V
Po = 50 mW to 15W
R L =3.2,n
V s =13.2V
Po =50mWto 13W
RI
(o)
(oo)
18
8
___________________________
TDA2005
Fig. 4 - Distortion vs. output power (Bridge amplifier)
Fig. 3 - Output offset voltage
vs. supply voltage
Fig. 5 - Distorsion vs. output power (Bridge amplifier)
vo •
(mV )
100
j
80
,.,
'8m_
/
60
/
40
20
"-I'
0.'
10
12
L--L-L...Ll.LiJJ.L_L-LLlJJWJ
Po(Wl
>0
BRIDGE AMPLIFIER DESIGN
The following considerations can be useful when designing a bridge amplifier.
Single ended
Bridge
1
2"
(V, - 2 VCE ,at)
V,-2V CE ,at
(V, - 2 VCE ,at)
V,-2V CE ,at
Parameter
Vo max
Peak output voltage
(before clipping)
10 max
Peak output current
(before clipping)
Po max
where:
rm. output power
(before clipping)
1
2"
RL
(V, - 2 VCE ,at)2
"4
2 RL
1
RL
(V. - 2 VCE ,at)2
2 RL
VCE sat= output transistors saturation voltage
Vs = allowable supply voltage
RL = load impedance.
Voltage and current swings are twice for a bridge
amplifier in comparison with single ended
amplifier. In order words, with the same RL the
bridge configuration can deliver an output power
that is four times the output power of a single
ended amplifier, while, with the same max
output current the bridge configuration can
deliver an output power that is twice the output
power of a single ended amplifier. Core must be
taken when selecting V, and RL in order to avoid
an output peak current above the absolute
maximum rating.
From the expression for 10 max, assuming V, =
14.4V and VCE sat = 2V, the minimum load
that can be driven by TDA2005 in bridge configuration is:
R
Lmln=
V, - 2 V CEsat
10 max
14.4 - 4
3.5
2.97 n
--------------------------- ~I~I;~~~ ________________________~5~/17
555
TDA2005
BRIDGE AMPLIFIER DESIGN (continued)"
Fig. 6 - Bridge configuration.
vb-I
s-
4093
The voltage gain of the bridge configuration is given by (see fig. 6):
G =
v
Vo
Vi
= 1+
R}
+ R3
( R2 • R4 )
R";
R2 + R4
G v (dB)
R} (n)
R 2= R4 (n)
R3 (n)
40
1000
39
2000
50
1000
12
2000
For sufficiently high gains (40 7 50 dB) it is
possible to put R2= R4 and R3= 2 R}. simplifing the formula in:
Gv = 4
....!!.L.
R2
STEREO AMPLIFIER APPLICATION (TDA2005S)
Fig. 7 - Typical application circuit
INPUT!
( L)
INPUT!
(R)
• v.
C'I
2.2.."
C21
z.z..,F,
5
ZZOCWF
cn
,S ·40851 1
~6/~}~7________________________ ~~~~~~~~
556
___________________________
TDA2005
ELECTRICAL CHARACTERISTICS (Refer to the stereo application circuit, T amb = 25°C,
Gy= 50 dB, Rth (heatslnk)= 4°C/W, unless otherwise specified).
Parameters
Supply voltage
Vo
Quiescent output voltage
Vs = 14.4V
Vs = 13.2V
Id
Total quiescent drain current
Vs = 14.4V
Vs = 13.2V
Po
Output power (each channel)
f = 1 KHz
Vs = 14.4V
Vs = 13.2V
Vs=16V
CT
Distortion (each channel)
Cross talk (0)
VI
Input saturation voltage
VI
I nput sensitivity
6.6
6
d = 10%
R L =40
R L = 3.20
R L = 20
R L = 1.60
R L = 3.20
R L = 1.60
R L = 20
6
7
9
10
6
9
f = 1 KHz
Vs= 14.4V
R L =40
Po = 50 mW to 4W
Vs = 14.4V
R L = 20
Po = 50 mW to 6W
Vs= 13.2V
R L =3.20
Po= 50 mW to 3W
Vs = 13.2V
R L = 1.60
Po = 40 mW to 6W
Vs= 14.4V
R L =40
Vo = 4V rms
Rg= 5 KO
Max.
Unit
18
V
7.2
6.6
7.8
7.2
V
V
65
62
120
120
mA
mA
6.5
8
10
11
6.5
10
12
W
W
W
W
W
W
W
0.2
1
%
0.3
1
%
0.2
1
%
0.3
1
%
f = 1 KHz
60
dB
f= 10KHz
45
dB
mV
300
f = 1 KHz
I nput resistance
f = 1 KHz
fL
Low frequency roll off (-3 dB)
R L =20
fH
High frequency roll off (-3 dB)
R L =20
Gv
Voltage gain (open loop)
f = 1 KHz
Gy
Voltage gain (closed loop)
f = 1 KHz
LlG v
Closed loop gain matching
eN
Total input noise voltage
Rj
Typ.
8
Vs
d
Min.
Test conditions
Po= lW
R L =40
R L = 3.20
Rg= 10 KO (00)
70
6
5.5
mV
200
KO
50
15
dB
90
48
Hz
KHz
51
dB
0.5
dB
1.5
5
jJ.V
50
(0)
For TDA 20055 only.
(00) Bandwidth filter: 22 Hz to 22 KHz.
__________________________
~~~~~~~~
______________________~7~/17
557
TDA2005
ELECTRICAL CHARACTERISTICS (continued)
Parameters
Test conditions
SVR
Supply voltage rejection
Rg= 10 KS1 ~IPPle= 100 Hz
C3= 10 j.lF
riPPle= 0.5V
Tj
Efficiency
Vs = 14.4V
R L =4S1
R L =2S1
Vs = 13.2V
R L =3.2S1
R L = 1.6S1
Tj
Typ.
35
45
dB
70
60
%
%
70
60
%
%
145
°C
f = 1 KHz
Po=6.5W
Po= 10W
f = 1 KHz
Po=6.5W
Po= 10W
Thermal shut-down junction
temperatu re
Fig. 8 - Quiescent output
voltage vs. supply voltage
.""
/
V
100
1/
/
'0
20
12
11. •
16
I
-l
"0 r-,,-,-.-.-.-r-r,-,-,-,
I
,
I
VS·14.4V R L,2,Q
i
I
I
i
1
1
-II I I I
1
1
1
1
1
0.01
~
Fig. 12 - Output power vs.
supply voltage
Po
(WJ
II
VS.112V RL,tSA
,
.c.
i
111111
l.l~
I I
0.1
Fig. 13 - Distortion vs.
frequency
I
I
hll1.Hz
"
"
s
I
I
II
VS·112V R L:3.24
V ·l.t..4VRL:J.n
,
~
hi
-
111111
I
-c
I
10
(WI
,
I I
~-+-l..
VS(VI
Fig.. 11 - Output power vs.
supply voltage
III
hlKHz
G.,.,SOdB
I
i
60
/
10
:
r"
Unit
Fig. 10- Distortion vs. output power
H-~ 1 I I ! 1 1 1
'III~I
80
/
V
(d
(mAl
/
/
/
Fig. 9 - Quiescent drain current vs. supply voltage
Max.
Min.
Gv·SI)dB
d.lO-"
Rtd
12
V
V
/
.6n.V
/
V
/Rl~2n
V
./
./
V
"
10
12 .
1&
16
Vs(V)
10
a
14
16
~8/~1~7_______________________ ~I~I~~~~
558
VS(VI
--------------------------
TDA2005
Fig. 14
.frequency
Distorsion vs.
Fig. 15 - Supply voltage rejection vs. C3
'."" "
".
'C#
(dBI
115 ,11•. .1.11
:
'ripple ,IOOH;z
10
20
1.2
'0
o.
.4
40
..........
.0
60
10
10~
10'
,YR)
(dB
I
"ss144Y
.~~:Kn
,YR
II
ill
,I
Gv·J9OfIfi
(clB)
so
A~
nl
C2"22~
40
40
V
'0 V
R L,4.Q
10'
10'
10
GV·1OOO/1011
f r lpp t.. •1OO Hz
G,
G,
'dB)
'4,=14.411
f =lkHz
54
C2.z21J~
/Vr
200
46
=6W
42
100
38
,0
~
0
"
/. V
~ ~
50
0.5
30
'/
20
10
Fig. 20 - Gain vs. input
sensitivity
,
G,
G,
10
20
Fig. 21 - Total power dissipation and efficiency vs.
output power (bridge)
(dB)
Vs=14.4
.
26
22
'0
soo
RL=4A
so
~2,s,..F
/
t (Hz)
Fig. 19 - Gain vs. input
sensitivity
/ ' C2,220,;
C2,SpF
I#'
20
\--r++jfiffl-~-+~+'R'il,~.'~OK~n~~~
40
J-.+-
"s.,14.4\1
Rg s lOKn
cr~ f-
trtppc.stOOHz
so
'0 ~~++~~~~~m~~RO~~~O~+H~
Fig. 18 - Supply voltage rejection vs. values of capacitors C2 and C3
Fig. 17 - Supply voltage
rejection vs. values of capacitors C2 and C3
1tI--t-+ttI-tttt-t-~1ttttI
GV'50dB
10
11Hz)
¥S,14.t.V
r-- C).'0jJFHt--t+t-ttttlt-H+t+ttH
I'
-
.......
~~\_
,
-n---r-r-
f----j,--H+Hl-tl, Vr ippie,O.5V
f----j'-H-+t+i-H G.",501:16
\--+-+-f-+++f+I R9 , 10Kn
Fig. 16 - Supply voltage
rejection vs. frequency
I:: H-+++-H-+++-H-+++-H (~,
'0
100
'00
20
IIj(mll)
Fig. 22 - Total power dissi·
pation and efficiency vs.
output power
P,~
,WI
H-t-+++--+
f =lkH
54
500
RL=2Il.
-".
50
60
P,ot
200
46
42
40
f-+-+-¥+-H-++++-H~S~!~~~
H-h'+-+-H+++-H-lhIKHz
100
Po =1OW
"
"
H*++-H-++++-HGv·~OdB
50
20
=O.5W
30
26
,
22
10
30
100
'00
.
II; (",V)
20
12
16
ZO.
24
Po(W)
10
12
9/17
559
TDA2005
APPLICATION SUGGESTION
The recommended values of the components are those shown on Bridge application circuit of fig. 1.
Different values can be used; the following table can help the designer.
Component
Recommended
Value
RI
120Kn
Optimization of the
output symmetry
R2
1 Kn
R3
2 Kn
Closed loop g~in
setting (see BRIDGE
AMPLIFIER
DESIGN) (*)
R4 and Rs
12 n
R6 and R7
1n
CI
2.2 "F
Input DC
decoupling
C2
2.2 "F
Optimization of
turn on pop and
turn on delay.
C3
0.1 "F
Supply by pass
C4
10"F
Ripple Rejection
Cs and C7
100"F
Bootstrapping
Increase of distortion
at low frequency.
C6 and Cs
220"F
Feedback input
DC decoupling, low
frequency cutoff.
Higher low frequency
cutoff.
C9 and CIO
0.1 "F
Frequency stability.
Danger of oscillation.
Purpose
Frequency stability
Larger than
Smaller Po max
Smaller than
Smaller Po max
Danger of oscillation
at high frequency
with inductive loads
High turn on delay
Higher tu rn on pop.
Higher low frequency
cutoff.
Increase of noise.
Danger of oscillation.
Increase of SVR.
Increase of the
switch-on time.
Degradation of SVR.
(*) The closed loop gain must be higher than 32dB.
=.;lO;:!./=.;17:...-_ _ _ _ _ _ _ _ _ _ ~ ~~m~~
560
-------------
TDA2005
APPLICATION INFORMATION
Fig. 23 - Bridge amplifier without boostrap
5-9242·
Fig. 24 -
p.e. board and component layout of the circuit of Fig. 23
---------------------------
~I~I~~?~~~~
(1 : 1 scale)
______________________
~1_1~/l_7
561
TDA2005
APPLICATION INFORMATION (continued)
Fig. 25 - Dual - Bridge amplifier
'Y.
RL
(RIGHT)
5-!l243
Fig. 26 - P.C. board and components layout of circuit of Fig. 25 (1: 1 scale)
~12:!./~17~_ _ _ _ _ _ _ _ _ _ _
562
l5ii !~~m?e~ -------------
TDA2005
APPLICATION INFORMATION (continued)
Fig. 27 - Low cost bridge amplifier (G v = 42dB)
>--+-___
~UOUT
1 nF ISO 11.
.----~~----4-1c~
.......- v OUT
~--+-=--
5- 9241
Fig. 28 - P.C. and component layout of the circuit of Fig. 27 (1: 1 scale)
+Vs OUT OUT
__________________________
~~~~;~~~~
_____________________~1~3~/l~7
563
TDA2005
APPLICATION INFORMATION (continued)
Fig. 29 - 10 + 10W stereo amplifier with tone balance and
loudness control
Fig. 30
Tone control
response (circuit of Fig. 29)
0 .. &Jll1I
~
NI
1/
10
....
....
10'
""al
Fig. 31 - 20W Bus amplifier
VS .. 14,4Y
S·4lS011
14/17
564
TDA2005
Fig. 32 - Simple 20W two way amplifier (Fe = 2KHz)
10kn
INPUT
Cl
1.80ft
5-1035111
Fig. 33 - Bridge amplifier circuit suited for low-gain applications (G v = 34dB)
·V.
INPUT!~
I
2.2.uF
5- 544111
565
TDA2005
APPLICATION INFORMATION (continued)
Fig. 34 - Example of muting circuit
L------~~_co>__--O+vs
MUTE
SWITCH
BUILT-IN PROTECTION SYSTEMS
Load dump voltage surge
Short circuit
The TDA2005 has a circuit which enables it to
withstand a voltage pulse train, on pin 9, of the
type shown in Fig. 36.
If the supply voltage peaks to more than 40V,
then an LC filter must be inserted between the
supply and pin 9, in order to assure that the
pulses at pin 9 will be held withing the limits
shown.
A suggested LC network is shown in Fig. 35.
With this network, a train of pulses with amplitude up to 120V and width of 2ms can be
applied at point A. This type of protection is
ON when the supply voltage (pulse or DC)
exceeds 18V. For this reason the maximum
operating supply voltage is 18V.
The TDA2005 can withstand a permanent shortcircuit on the output for a supply voltage up
to 16V.
Fig. 35
When the radio is in the ON condition and the
ground is accidentally opened, a standard audio
amplifier will be damaged. On the TDA2005
protection diodes are included to avoid any
damage.
FROM
A
l=2mH
SUPPLY ~TO PIN9
.l£ 3000 J'F
LINE
.nno
5-190111
I
(AC and DC conditions)
Polarity inversion
High current (up to lOA) can be handled by the
device with no damage for a longer period than
the blow-out time of a quick 2A fuse (normally
connected in series with the supply). This feature
is added to avoid destruction, if during fitting
to the car, a mistake on the connection of the
supply is made.
Open ground
I6V
Inductive load
Fig. 36
A protection diode is provided to allow use of
the TDA2005 with inductive loads.
DC voltage
The maximum operating DC voltage for the
TDA2005 is l8V.
However the device can withstand a DC voltage
up to 28V with no damage. This could occur
during winter if two batteries are series connected to crank the engine.
14.4
S - 190011
566
TDA2005
BUILT-IN PROTECTION SYSTEMS (continued)
Thermal shut-down
The maximum allowable power dissipation
depends upon the size of the external heatsink
(Le. its thermal resistance); Fig. 37 shows the
dissipable power as a function of ambient temperature for different thermal resistance.
The presence of a thermal limiting circuit offers
the following advantages:
1) an overload on the output (even if it is permanent), or an excessive ambient temperature
can be easily withstood.
2) the heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no device damage in the case
of excessive junction temperature: all that
happens is that Po (and therefore P tot ) and Id
are reduced.
Fig. 38 - Output power and
drain current vs. case temperature
Fig. 37 - Maximum allowable power dissipation vs.
ambient temperature
,
"
P,
Plot
(W )
(W
2.
"
,.
20
Loudspeaker protection
The circuit offers loudspeaker protection during
short circuit for one wire to ground.
,.
~t
"~
N..,t.t.;~,
g'h_~~~I~""c(Js.i
~
\
"'S ..14.4V
R l ·2.Q.
hlKHz
'.
f- -
f-
Fig. 39 - Output power and
drain current vs. case temperature
I.
P,
lA'
N'
Ys.13.2V
0.9
'\
0.6
"'K1iz
,.
Po
~
.,.
W
RL=12n
>'2
\
12
'--'--'-"-"-"-'----'-'1--''-' ,.
12
QJ
-so
.0
100 Tamb(-CI
40
80
120
40
.0
120
160 Tu,se{"tl
__________________________ ~~~1;~~----------------------~1~7/~17
567
TDA2006
12W AUDIO AMPLIFIER
The TDA2006 is a monolithic integrated circuit
in Pentawatt package, intended for use as a low
frequency class "AB" amplifier. At ± 12V, d =
10% typically it.provides 12W output power on
a 4n load and SW on a sn. The TDA2006 provides high output current and has very low
harmonic and cross-over distortion. Further the
device incorporates an original (and patented)
short circuit protection system comprising an
arrangement for automatically limiting the dissipated power so as to keep the working point
of the output transistors within their safe operating area. A conventional thermal shutdown
system is also included. The TDA2006 is pin to
pin equivalent to the TDA2030.
Pentawatt
ORDER CODE: TDA2006H
TDA2006V
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at T case= 90°C
Storage and junction temperature
± 15
Vs
± 12
3
20
-40 to 150
v
V
A
W
°C
TEST AND APPLICATION CIRCUIT
June 1988
1/9
569
TDA2006
CONNECTION DIAGRAM
4
3
~III~·VS
OUTPUT
-Vs
INVERTING INPUT
NON INVERTING INPUT
S-262811
tab connected to pin 3
SCHEMATIC DIAGRAM
4
~2/~9
_______________________
570
~1~~
_________________________
TDA2006
THERMAL DATA
Rth _j case
Thermal resistance junction-case
3
max
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs
= ± 12V,
Tamb
= 25°C unless
otherwise specified)
Pare meter
Test Conditions
Min.
Typ.
±6
Max.
Unit
± 15
V
mA
Vs
S\lpply voltage
Id
Quiescent drain current
40
SO
Ib
I nput bias current
0.2
3
Vos
I nput offset voltage
±S
Vs = ± 15V
los
I nput offset cu rrent
± SO
Vos
Output offset voltage
± 10
Po
Output power
Distortion
d
VI
10%
1 KHz
= 40.
= So.
Rj
Input resistance (pin 1)
Gy
Voltage gain (open loop)
Gy
Voltage gain (closed loop)
eN
I nput noise voltage
iN
Input noise current
SVR
Supply voltage rejection
Id
Drain current
Tj
Thermal shutdown junction
temperature
nA
± 100
mV
12
8
W
W
Po = 0.1 to SW
RL = 40.
f = 1 KHz
0.2
%
Po = 0.1 to 4W
RL = So.
f = 1 KHz
0.1
Input sensitivity
Frequency response (-3dB)
B
d =
f =
RL
RL
IJA
mV
6
Po = lOW
Po = 6W
f = 1 KHz
RL =40.
RL=8n
Po = SW
RL = 40.
20 Hz to 100 KHz
0.5
29.5
B (-3dB) = 22Hz to 22KHz
RL = 40.
(*)
Po = 12W
Po=SW
RL =40.
R L =8n
%
mV
mV
200
220
f = 1 KHz
RL = 40.
Rg = 22Kn
f ripple = 100Hz
1
40
5
Mn
75
dB
30
30.5
dB
3
10
IJV
SO
200
pA
50
dB
S50
500
mA
mA
145
°C
(*) ReferrlOg to Fig. 15, slOgle supply.
__ _______________________
~
~~~~~~&~I~~~
_________________________
3~/9
571
TDA2006
Fig. 1 - Output power vs.
supply voltage
G-4116
p
0
d.IO"!.
f .IKHz
..
6-4167
o
(
(W )
Fig. 3 - Distortion vs. frequency
Fig.2 - Distortion vs. output
power
I II
n
)
I
RL·a'n
o
Rl',,4.t1
16
II
Rl=4Jl./
"
12
7
V
AL",~
1
V5;;:I:12V
"'5=tI2
17
.-
""
(-.
R L ,,4.n
Po",BW
hlKHz
/
0.'
0.'
l/
V
0. 3
1/ V
0.
/ 1/
,
0. I
10
10
12
Fig. 4 - Distortion vs. fre·
10'
10
Po(W)
Fig.5 -Sensitivity vs. output
power
f (Hz)
Fig. 6 -Sensitivity vs. output
power
v, rr--r--"--,--,--rr-r-,,,,+'i'-"r...,
(nW
Y5·1:12V
~~;K8H~ f-+-+--H-++-+-+-+-+-JfGy .. 30dB
18oH++-1+.:;.G'''.:',::30~0;;..~++-+++-I
180 H-+--H-++-H4-+-f-++-H120 f-+-+-IA-+-l +-J-+-+-+-+-+--HH
60~-+--H-+~~G~'·C'~00~.~~+-+-+--H
1H4-++L.l-l-l=
Fig. 7- Frequency response
with different values of the
rolloff capacitor C a (see
fig. 13)
Fig. 8 - Value of C s vs.
voltage gain for different
bandwidths (see fig. 13)
G-4'72
G
(0
-L.l-l---I-+-+-J
elL---
"
ao
60
~~;;r
0..
~>
6-'173
c
•
(pF
VSd12V
VS,,:t12V
"."
a.2OKHz
'\."'\ ~ ~.
.1 1
,,~.~. '(
~~~
~~;~
~o._
0..'"
'0
""0
20
,
10
I'k
1\
.0
B.5OKHz
'"
r-..
~
. 10
10'
10'
10'
105
t(Hz)
20
.:!4/:.,::9_ _ _ _ _ _ _ _ _ _ _ _
572
tttttttttti:i:t±±±:1
1\
:'\.
10
'0 rT--'-.,.,rr--'--,,--'--'--r-r+~
(mA_)~+-+-+-+-+-1-++-+-+-+-++
R6; R2
A5ii3R2
Fig. 9 - Quiescent current
vs. supply voltage
30
40
G..,(dB1SO
10
~ 1~I~mo.JI------------
TDA2006
Fig. 10 - Supply voltage
rejection vs. voltage gain
Fig. 11 - Power dissipation
and efficiency vs. output
power
-,
,
+ -+-r---w.v
l
Fig. 12 - Maximum power
dissipation vs. supply voltage (sine wave operation)
,
t = lKH:I!
I'l(anl
"
60
rtf4!l.)
'0
50
Ptot(4Q
I
30
40
Fig. 13 - Application circuit with
split power supply
Y
20
,
-H+
20
R L= 411
"
30
tol 8M
'0
"
40
l.4
,
-,
,
P'o
,W
l
vi'"
.,.,.-
V
,.- V
RL=SA
V
I10
12
Po(W)
'0
"
Fig. 14 - P.C. board and component
layout for the circuit of fig. 13
------------------------~~I~~~~~n
________________________
5~/9
573
TDA2006 _______________________________________________
Fig. 15 - Application circuit with single
power supply
Fig. 16 - P.C. board and component
layout for the circuit of fig. 15
Fig. 17 - Bridge amplifier configuration with split power supply (Po
12~FX
= 24W, Vs = ± 12Vj
lN4001
680fil.
680n
5- 4316
6/9
574
TDA2006
PRACTICAL CONSIDERATION
Printed circuit board
Application suggestion
The layout shown in Fig. 14 should be adopted
by the designers. If different layout are used,
the ground points of input 1 and input 2 must be
well decoupled from ground of the output on
which a rather high current flows.
The recommended values of the components are
thf! ones shown on application circuits of Fig. 13.
Different values can be used. The following table
can help the designers.
Assembly 5uggeS1ion
No electrical isolation is needed between the
package and the heat-sink with single supply
voltage configuration.
Component
Recommended
value
Larger than
recommended value
Smaller than
recommended value
Rl
22Kn
Closed loop gain
setting
Increase of gain
Decrease of gain (ot
R2
6aOn
Closed·loop.gain
sett·ing.
Decrease of gain (ot
Increase pf ga in
R3
22Kn
Non inverting input
biasing
Increase of input
impedance
Decrease of input
impedance
R4
In
Frequency stability
Da nger of oscillation at
high frequencies with
inductive loads
Rs
3 R2
Upper frequency
cutoff
Poor high frequencies
attenuation
C1
2.2jtF
Input DC decoupling
Increase of low
freqencies cut off
C2
22jtF
Inverting input DC
decoupling
Increase of low
frequencies cutoff
C 3C4
0.1 jtF
Supply voltage by pass
Danger of oscillation
CSC6
100jtF
Supply voltage by pass
Danger of oscillation
C7
0.22 jtF
1
27rBRl
Frequency stability
Danger of oscillation
Upper frequency
cutoff
lN4001
To protect the device against output voltage spikes.
Ca
0 102
Purpose
Lower bandwidth
Danger of oscillation
Larger bandwidth
(*t Closed loop gain must be higher than 24dB
--------------------------~~I~
________________________
7~/9
575
TDA2006
SHORT CIRCUIT PROTECTION
The TDA2006 has an original circuit which
limits the current of the output transistors. Fig.
18 shows that the maximum output current is
a function of the collector emitter voltage;
hence the output transistors work within their
safe operating area (Fig. 19).
This function can therefore be considered as
being peak power limiting rather than simple
current limiting.
It reduces the possibility that the device gets
damaged during an accidental short circuit
from AC output to ground.
Fig. 18 - Maximum output
current vs. voltage Vc~ (sat)
across each output transistor
Fig. 19 - Safe operating area and
collector characteristics of the protected power transistor
\
\..-Ptot =k
Ie max.
\
\
\
.,
-2
-3
8
12
16
20.
24
VC~,(V)
28
-28 -24 -20 -16 -12
-8
-4
5-076411
THERMAL SHUT - DOWN
The presence of a thermal limiting circuit offers
the following advantages:
1) An overload on the output (even if it is
permanent), or an above limit ambient temperature can be easily supported since the
lj cannot be higher than 150°C.
2) The heatsink can have a smaller factor of
.::.8/<..::9_ _ _ _ _ _ _ _ _ _ _ _
576
safety compared with that of a conventional
circuit. There is no possibility of device
damage due to high junction temperature.
If for any reason, the junction temperature
increases up to 150°C, the thermal shutdown
simply reduces the power dissipation and
the current consumption.
~ ~~tm~~~
-------------
TDA2006
Fig. 20 - Output power and
drain current vs. case tem·
perature (R L = 4n)
G- "791]
e,
(W )
--4 RRH·
~
~~~
,
Fig. 21 - Output power and
drain current vs. case temperature (R L = 8n)
,
( AI
t
'd
e,
i
0.6
-
0.4
0.2
100
0.2
150 Tcase(·Cl
100
The maximum allowable power dissipation
depends upon the size of the external heatsink
(i.e. its thermal resistance); fig. 22 shows the
Fig. 22 - Maximum allowable power dissipation vs.
ambient temperature
dissipable power as a function of ambient temperature for different thermal resistances.
Fig. 23 - Example of heatsink
Dimension suggestion
The following table shows the lenght of the heatsink
in fig. 23 for several values of Ptot and Rth .
---------------------------~~~~~~~~~f~~~~
Ptot (W)
12
8
6
Lenght of
heatsink (mm)
60
40
30
Rth of heatsink
('C/W)
4.2
6.2
8.3
________________________~9/9
577
TDA2007
6+6W STEREO AMPLIFIER
The TDA 2007 is a class AB dual Audio power
amplifier assembled in single in line 9 pins
package, specially designed for stereo appli·
cation in music centers TV receivers and portable
radios. Its main features are:
-
SIP. 9
High output power
High current capability
Thermal overload protection
Space and cost saving: very low number of
external components and simple mounting
thanks to the SIP. 9 package.
ORDERING NUMBER: TDA 2007
ABSOLUTE MAXIMUM RATINGS
Vs
10
10
Ptat
Tstg , Tj
Supply voltage
Output peak current (repetitive f;;> 20 Hz)
Output peak current (non repetitive, t = 100 IJ-s)
Power dissipation at T case = 70°C
Storage and junction temperature
28
V
3
3.5
A
A
10
W
°C
-40 to 150
STEREO TEST CIRCUIT
+Vs
June 1988
1/6
579
TDA2007
CONNECTION DIAGRAM
(Top view)
9
OUT (1)
8
0
7
OUT (2)
6
GNO
5
INPUT+(21
4
INPUT (2)
3
n,
l
SVR
INPUT -(1)
INPUT + (1 )
S-9599
SCHEMATIC DIAGRAM
4
5
5-9600
THERMAL DATA
Rth J-case
Rth J-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
;;.;2'..;.6_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~tm~~
580
max
max
8
70
-------------
TDA2007
ELECTRICAL CHARACTERISTICS (Refer to the stereo application circuit, T amb = 25°C,
V 5 = 18V, Gy = 36 dB, unless otherwise specified)
Paramaters
Vs
Supply voltage
Vo
Qu iescent output voltage
Total quia,cent drain current
Po
Output power (each channell
CT
Typ.
8
Id
d
Min.
Test conditions
Distortion (each channell
Cross talk (000)
Ri
I nput resistance
fL
Low frequency roll off (-3 dB)
26
V
V
48
mA
6
6
W
W
f = 1 KHz, Vs = 18V, RL = 40
Po = 100 mW to 3W
0.1
%
f=l KHz, Vs=22V, R L =80
Po = 100 mW to 3W
0.05
%
f= 100 Hz to 16 KHz
d = 0.5%
RL = 40
Vs=18V
R L =80
Vs = 22V
00
Rg = 10 KO
I nput saturation voltage (rms)
Unit
8.5
RL =
Vi
Max.
5.5
5.5
f = 1 KHz
50
60
dB
f=10KHz
40
50
dB
mV
300
70
f = 1 KHz
200
KO
40
Hz
80
KHz
RL = 40, Cl0= Cll= 2200"F
fH
High frequency roll off (-3 dB)
Gv
Voltage gain (closed loop)
1I Gv
Closed loop gain matching
eN
Total input noise voltage
SVR
TJ
Supply voltage rejection
(each channell
f = 1 KHz
36.5
dB
dB
Rg = 10 KO (0)
1,5
"V
Rg = 10 KO (00)
2.5
Rg = 10 KO
friPPI.= 100 Hz
VriPPle= 0.5V
55
dB
145
°C
(00) 22 Hz to 22 KHz.
___________________________
36
0.5
Thermal shut-down junction
temperature
(0) Curve A.
35.5
~~~~~~g~~
8
"V
(000) Optimized test box.
________________________
~3/6
581
TDA2007
Fig. 1 - Stereo test circuit (G v = 36 dB)
.vs
Fig. 2 - P.C. board and components layout of the circuit of fig. 1 (1 : 1 scale)
cs- 0265
l8-I----{)
+
OUT
M f o - - - U 0 UT
IN
IN
.:.:.4/.::.6_ _ _ _ _ _ _ _ _ _ _
582
@. ~~~~m~ll~~Al------------
TDA2007
Fig. 4 - Output power vs.
supply voltage (d = 10%)
Fig. 3 - Output power vs.
supply voltage (d = 0.5%)
G-6235
,
p.
cw
G-6236
c.
Fig. 5 - Quiescent current
vs. supply voltage
'. ,
-&23711
(rnA
(W l
d .. 10'1.
d .0.5""
f=100Hz to 6KHz
70
f"IKHz
12
/
RL/
10
RL",4J1.
......- V
~
10
.....V ......- k::'
..~
12
--
16
16
/
V
I
f-
so
Rl=4!l
Rgo:l0K.Cl
f=100Hz
20
Vs(V)
'0
£
/
.".(.I. C7; "
.......- ".....-
10
4.
20
14
1.
6
22 Vs(V)
Fig. 7 - Supply voltage
rejection vs. frequency
,
10
14
18
22
'Is(V)
Fig. 8 - Total power dissipation vs. output power
G-&O$411
I
I
ao
VS,,18v
Ag =10KQ,
Pto t
(W,
Vs .. lOV
I--
RL"en
f"'Kll
F
r---.
V
L
I- ........
..... r-..,
I
1/
2.
t
10
30
o
(,.,FI
Fig. 9 - Cross-talk vs. frequency
"
10
Fig. 10 - Simple short-circuit
protection
5
6
7
8
Po (WI
Fig. 11 - Example of muting
circuit
II
(d"
¥S·18v
7.
4Jl.
SPEAKER
I-...
12KJ'l.
'-------+----<.......
u~+ys
10
10
-
-,......
50
'0
40
20
...
....
...
V
(d.
VA'
V
40
./
i-'"""""
C6'C7!2~
Vs .. 18V
V
/'
.ll.~
/
Fig. 6 - Supply voltage
rejection vs. value of capacitor C3
G-'6&'"
,
SVO
(dB
V
60
5-9603
,,'
10"
SWITCH
HHzl
-------------- fiil ~~~;m&=11 _____________
5:..:./..:.6
583
TDA2007
APPLICATION INFORMATION
Fig. 12 - 12W bridge amplifier (d = 0,5%, Gv = 4OdB)
+18V
C7
r;oo,.F
C9~O"I'F
391l
S-I801I1
R3
RS
III
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 1. Different
values can be used; the following table can help the designer.
Component
Recomm.
value
R1 and R3
1.3 Kn
R2and R4
18n
R5 and,R6
1n
C1 and C2
Purpose
Larger than
Smaller than
Increase of gain
Decrease of ga i n
Decrease of gain
Increase of gain
Close loop gain setting(")
Frequency stability
Danger of oscillation at
high frequency with
inductive load
2.21'F
Input DC decoupling
High turn-:on delay
High turn-on pop
Higher low frequency
cutoff. Increase of noise
C3
221'F
Ripple rejection
Better SVR.
I ncrease of the
switch-on time
Degradation of SVR.
C6 and C7
220l'F
Feedback I nput DC
decoupling
C8and C9
0.11'F
Frequency stability
Danger of oscillation
Cl0and Cll
1000 I'F to
2200l'F
Output DC decoupling
Higher low-'frequency
cut-off
(*) The closed loop gain must be hIgher than 26 dB.
~6/~6_______________________
584
~!~~~~~
_________________________
TDA2008
12W AUDIO AMPLIFIER (Vs=22V, RL=4Q)
-
The TDA2008 is a monolithic class B audio
power amplifier in Pentawatt®package designed
for driving low impedance loads (down to 3.2n).
The device provides a high output current capabi·
lity (up to 3A). very low harmonic and crossover
distortion.
space and cost saving;
high reliability;
flexibility in use;
thermal protection.
In addition, the device offers the following
features:
Pentawatt
- very low number of external components;
- assembly ease, due to Pentawatt® power
package with no electrical insulation require·
ments;
ORDERING NUMBER: TDA2008V
ABSOLUTE MAXIMUM RATINGS
V.
"10
10
Ptot
Tst9' TJ
DC supply voltage
Output peak current (repetitive)
Output peak current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature
28
3
4
20
-40 to 150
TYPICAL APPLICATION CIRCUIT
.-----_----.() Vs
'
C4
4
1000~F
16
l00nF
C2
470~F
3V
1
Cx
June 1988
= 2TTBRI
1/7
585
TDA2008
CONNECTION DIAGRAM
(top view)
5
$
L~
4
3
2
1
SUPPLY
VOLTAGE
OUTPUT
GROUND
INVERTING INPUT
NON INVERTING INPUT
5-189 411
tab connected to pin 3
SCHEMATIC DIAGRAM
~G4
........-1--+------1:'
07
Q15
08
L -_ _ _ _ _~
016
R1
s-
~2/:..:..7 _ _ _ _ _ _ _ _ _ _ _ _ ~ I~~m~'~~
586
4008
-------------
TDA2008
DC TEST CIRCUIT
,-----------~--------~tVs
I:.l00nF
470J..lF
R2
5- 4009
AC TEST CIRCUIT
.--------_----..;n· Vs
C4
1000 }-IF
4
C2
RI
470 }-IF
587
TDA2008
THERMAL DATA
Rth j-case
max
Thermal resistance junction-case
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,V s
3
°C/W
= 22V, T amb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Vo
Quiescent output voltage
(pin 4)
Id
Quiescent drain current
(pin 5)
Po
Output power
Min.
Test conditions
10
I nput sensitivity
65
d= 10%
RL=SU
f = 1 KHz
R L =4U
f = 1 KHz
Po = 0.5W
Po = SW
Po = 0.5W
Po = 12W
Po= 1W
R L =4U
d
Distortion
f = 1 KHz
Po =0.05 t04W RL=SU
Po = 0.05 to 6W R L = 4U
Gv
Voltage gain (open loop)
f = 1 KHz
f = 1 KHz
Gv
Voltage gain (closed loop)
eN
Input noise voltage
2S
V
V
115
S
10
RL=SU
RL=SU
R L =4U
R L =4U
Frequency response
(-3 dB)
Input resistance (pin 1)
Unit
12
W
mV
20
SO
14
70
mV
mV
mV
mV
40 to 15000
Hz
0.12
0.12
70
mA
W
300
B
Ri
Max.
10.5
Vi (RMS) Input saturation voltage
Vi
Typ.
1
1
%
%
150
KU
SO
dB
RL=SU
39.5
40
40.5
dB
1
5
/LV
60
200
pA
BW= 22Hz to 22 KHz
iN
Input noise current
SVR
Supply voltage rejection
V ripple= 0.5V
Rg = 10KU
RL =4U
f=100Hz
~4/~7_________________________ ~~~~~~~v~:~~~
588
30
36
dB
---------------------------
TDA2008
APPLICATION INFORMATION
Fig. 1 - rypical application circuit
Fig. 2 - P.C. board and component layout for
the circuit of fig. 1 (1: 1 scale)
r - - -C
- 3"---O Vs
r
O.1
/.IF
I
Cx = 2T1BRI
Fig. 3 ~ 25W bridge configuration application
circuit (0)
Fig. 4 - P.C. board and component layout for
the circuit of fig. 3 (1: 1 scale)
(0) The value of the capacitors C3 and C4 are different to optimize the SVR (Typ. = 40 dB)
---------------------------~!5!;~~~~
________________________~5/7
589
TDA2008
Fig. 5 - Quiescent current
vs. supply voltage
6-8023
'.
(mA )
Fig. 7 - Output power vs.
supply voltage
Fig. 6 - Output voltage vs.
supply voltage
G-
v.
ou
(V)
'00
/
"
.0
60
..... 1-"""
40
'""'"
'""'"
'""'"
/
'0
/
/
/
/
20
!/
12
16
20
24
28Vs{V)
d""mm-'Tnnw-rTTI~-Trmm
H-+ttttttt-t-tttttttt--++++tttlI--+ttH-tttI
20
12
2Ii
Fig. 9 - Supply voltage
rejection vs. frequency
Fig. 8 - Distortion vs. frequency
("!J
,6
"
'V.
r-
20
24
28
Fig. 10 - Maximum allowable power dissipation
vs. ambient temperature
"
II
(dB )
16
(W)
Vs ,,22V
Rg.l0
15
50
0.'
H-+ttttttt-t-tttttttt--+-Hftttll--+ttH-tttI
40
0.6
H-+tklttlt-t-tttttttt--++++tttlI--+H+I-HII
30
0.4 H-+ttMrl-tttttttt--++++tttlI--+HH-HII
20
'0'
'0'
'0'
f(Hz)
.::.6/:.!,.7_ _ _ _ _ _ _ _ _ _ _ _
590
.
10
",oelW
'0'
'0'
~ ~~~SJ»Jt
so
'00
------------
TDA2008
PRACTICAL CONSIDERATIONS
Printed circuit board
The layout shown in Fig. 2 is recommended. If
different layouts are used, the ground points of
input 1 and input 2 must be well decoupled from
the ground of the output through which a rather
high current flows.
Assembly suggestion
No electrical
insulation
is needed between
the package and the heat-sink. Pin length should
be as short as possible. The soldering temperature
must not exceed 260°C for 12 seconds.
Application suggestions
The recommended component values are those
shown in the application circuits of Fig. 1.
Different values can be used. The following table
is intended to aid the car-radio designer.
Component
Recommended
value
Purpose
Larger than
recommended value
Smaller than
recommended value
C1
2.21'F
Input DC decoupling.
Noise at switch-on,
switch-off.
C2
470l'F
Ripple rejection.
Degredation of SVR.
C3
0.11'F
Supply bypassing.
Danger of oscillation.
C4
10001' F
Output coupling.
Higher low frequency
cutoff.
C5
0.11'F
Frequency stability.
Danger of oscillation
at high frequencies
with inductive loeds.
R1
(Gv·1) • R2
Setting of gain. (*)
Increase of drain
current.
R2
2.20
Setting of gain and
SVR.
Degradation of SVR.
R3
10
Frequency stability.
Danger of oscillation
at high frequencies
with inductive loads.
(*l The closed loop gain must be higher than 26dB.
-------------
~ I~t~=~
____________
;.L;..7/7
591
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
SGS-THOMSON
~'YL [ilYA]D©OO@rn[!J~©iJ'OO@~D©~
TDA2009
10+10W HIGH QUALITY STEREO AMPLIFIER
The TDA2009 is class AB dual Hi-Fi Audio power
amplifier assembled in Multiwatt® package, specially designed for high quality stereo application
as Hi-Fi and music centers. Its main features are:
-
High output power (10+ 10W min.@ d = 0.5%)
High current capability (up to 3.5A)
Thermal overload protection
Space and cost saving: very low number of
external components and simple mounting
thanks to the MUltiwatt® package.
Multiwatt-11
ORDERING NUMBER: TDA2009
ABSOLUTE MAXIMUM RATINGS
Vs
10
10
Ptot
T stg ' TJ
Supply voltage
Output peak current (repetitive f;;;' 20Hz)
Output peak current (non repetitive, t = 100~s)
Power dissipation at Tcase = 90°C
Storage and junction temperature
28
3.5
4.5
20
-40 to 150
TEST CIRCUIT
+Vs
22"F
I
C3
2.2"F
~111---,5!J---~
(L)
Cl
1.3Kfl
Rl
C6
R2
IBll
IN
2.2"F
(R)
C2
-----O+vs
5-8S18
MUTE
SWITCH
Fig. 13 - 10W + 10W stereo amplifier with tone balance and
loudness control
Fig. 14 - Tone control reo
sponse (circuit of fig. 13)
(dB I
II I I
I
INPUl(U
J:--~'.~.K-a~r47-n-F.-~
.6
.3
I
I
'"
MID
~
REBLE
-3
1/
-6
BASS
:'\
-"
10
_6.:../9_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m?ll~:Jill1
608
10'
--------------
TDA2009A
APPLICATION INFORMATION (continued)
Fig. 15 - High quality 20 + 20W two way amplifier for ster.eo music center (one challel only)
10tUl.
1c " 2KHz
INPUT
5.6nF
(L)IO--,--n--L-III-~
L-------I''="IIIJ---i R5
~~O;1~:'O
R8
TWEETER
1..1l
5-9232
Fig. 16 -18Wbridge amplifier (d= 1%, Gv = 40dB)
Fig. 17 - P.C. board and components layout
of the circuit of fig. 16 (1 : 1 scale)
7/9
609
TDA2009A
APPLICATION SUGGESTION
The recommended values of the components are those shown on application circuit of fig. 1. Different
values can be used; the following table can help the designer.
Component
Recomm.
value
Rl and R3
1.2KO
R2 and R4
l8KO
RS and R6
Hl
Cl and C2
Purpose
Larger than
Smaller than
Increase of gain
Decrease of gain
Decrease of gain
Increase of gain
Close loop gain setting (')
Frequencv stability
Danger of oscillation at
high frequency with
inductive load
2.2~F
Input DC decoupling
High turn-on delay
High turn-on pop
Higher low frequency
cutoff. Increase of noise
C3
22~F
Ripple rejection
Better SVR.
Increase of the
Switch-on time
Degradation of SV R
C6 and C7
22O~F
Feedback input DC
decoupling.
C8 and C9
O.l~F
Frequency stability
Danger of oscillation
Output DC decoupling.
Higher low-frequency
cut-off
Cl0 and Cll
1000~F
to
22OO~F
(') Closed loop gain must be higher than 26dB
BUILD-IN PROTECTION SYSTEMS
Thermal shut-down
The presence of a thermal limiting circuit offers
the following advantages:
1 ) an overload on the output (even if it is permanentl. or an excessive ambient temperature
can be easily withstood.
2) the heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no device damage in the case
of excessive junction temperature: all that
happens is that Po (and therefore Ptot ) and
10 are reduced.
The maximum allowable power dissipation
depends upon the size of the external heatsink
(Le. its thermal resistance); fig. 18 shows this
dissipable power as a function of ambient temperature for different thermal resistance.
Short circuit (AC Conditions). The TDA2009A
can withstand an accidental short circuit from
the output and ground made by a wrong connection during normal play operation.
~8~/9~_______________________ ~1~~~~~~
610
___________________________
TDA2009A
Fig. 19 - Output power vs.
case temperature
Fig. 18 - Maximum allowable power dissipation vs.
ambient temperature
Ptot
'l,
(W l
(W l
J2
J6
20
l2
p.
Cd
(AI
~
.
-
~
RL,12n
t.IKHz
~\
~.
~,
11," ,~~
~8"c
"$. ....<
111'
-..
Jl
1\
\
~
.~
.
.0
lOO Tamb("Cl
"
Ys=24V
Rl =4n
f ,.IKHZ
+
1\
\
-
-so
1'-'
.---,---r-,---,----,----,---,--,--
(WI
Vs.13.2 V
28
24
Fig. 20 - Output power and
drain current vs. case temperature
MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be
removed by adding an external heatsink.
Thanks to the MUL TIWATT®package attaching
the heatsink is very simple, a screw or a com-
___________________________
80
llO
'0
.0
120
pression spring (clip) being sufficient. Between
the heatsink and the package it is better to insert
a layer of silicon grease, to optimize the thermal
contact; no electrical isolation is needed between
the two surfaces.
~I~~~~~~
________________________
~9/9
611
TDA2030
14W Hi-Fi AUDIO AMPLIFIER
The TDA2030 is a monolithic integrated circuit
in Pentawatt® package, intended for use as a low
frequency class AB amplifier. Typically it pro·
vides 14W output power (d = 0.5%) at 14V/
4n; at ± 14V the guaranteed output power is
12W on a 4n load and 8W on a 8n (DIN45500).
The TDA2030 provides high output current and
has very low harmonic and cross-over distortion.
Further the device incorporates an original
(and patented) short circuit protection system
comprising an arrangement for automatically
limiting the dissipated power so as to keep the
working point of the output transistors within
their safe operating area. A conventional thermal
shut-down system is also included.
Pentawatt
ORDERING NUMBER: TDA2030H
TDA2030V
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
VI
10
Ptot
Tstg , lj
Supply voltage
Input voltage
Differential input voltage
Output peak current (internally limited)
Power dissipation at Tease = 90°C
Storage and junction temperature
± 18
v
V.
i 15
3.5
20
-40 to 150
TYPICAL APPLICATION
June 1988
1/9
613
TDA2030
CONNECTION DIAGRAM
(top view)
>
5
~
+Vs
OUTPUT
4
3
-Vs
2
INVERTING INPUT
NON INVERTING INPUT
I
::'-2628/1
tab connected to pin 3
TEST CIRCUIT
.=.2/;.:.9_ _ _ _ _ _ _ _ _ _ _ "';'Iitm=~~
614
----------'---
TDA2030
THERMAL DATA
Rthl-case
Thermal resistance junction-case
3
max
°C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs = ± 14V, Tamb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Ib
I nput bias current
Vos
I nput offset voltage
I
I nput offset current
os
Po
Output power
Test conditions
B
Distortion
Power Bandwidth
(-3 dB)
40
Vs = ± l!lV
d = 0.5%
Gv = 30 dB
f = 40 to 15000 Hz
RL=4n
R L =8n
12
8
Max.
Unit
± 18
V
60
mA
0.2
2
#A
±2
± 20
mV
± 20
± 200
nA
14
9
W
W
18
11
W
W
Gv= 30dB
Po =O.l to12W
R L =4n
Gv = 30 dB
f = 40 to 15000 Hz
0.2
0.5
%
Po = 0.1 to 8W
R L =8n
G v= 30dB
f = 40 to 15 000 Hz
0.1
0.5
%
Gv = 30dB
Po= 12W
R L =4n
Ri
I nput resistance (pin 1)
Gy
Voltage gain (open loop)
Gy
Voltage gain (closed loop)
eN
I nput noise voltage
iN
I nput noise current
SVR
Supply voltage rejection
R L =4n
Gv= 30dB
Rg= 22 kn
V ripPle= 0.5 V eft
friPPle= 100 Hz
Id
Drain current
Po= 14W
P0 = 9W
Tj
Thermal shut-down junction
temperatu re
---------------------------
Typ.
±6
d = 10%
f = 1 kHz
R L =4n
R L =8n
d
Min.
0.5
f = 1 kHz
29.5
B = 22 Hz to 22 KHz
R L =4n
R L =8n
~!~t~~~~~~
40
10 to 140000
Hz
5
Mn
90
dB
30
30.5
dB
3
10
#V
80
200
pA
50
dB
900
500
mA
mA
145
°C
________________________
~3/~9
615
TDA2030
Fig. 2 - Output power vs.
supply voltage
Fig. 1 - Output power vs.
supply voltage
Fig. 3 - Distortion vs. output
power
(;-2942
40
d"Q.S'/.
f=40HztolSkHz
16
/
12
/
/
/
,,/6fl
0.' t-hi-tttttfj-t-t++lH-ltt-t-t+t+tttI
D.41-+-ii-tttttfj-t-t++lH-ltt-t-t+t+tttI
V
V
,/
0.3 f--+-ir+++tttI-H++I+!JI.-~+++t+lI
....v
,,/
V
v
"
Xl
Fig. 4 - Distortion vs. output
power
,
12
14
0.2
f--Hr++tttH-H++I-+f!!o'--f-++H++1I
0.'
t-+-i-+++tttI=-H++IH-Itt-~+++t+lI
.t.Vs (V)
'6
I
Fig. 5 - Distortion vs. output
power
l_-Li~~tt~·1
I·' '
.. if; W·-tt
I
I
Vs " t 14V
Gv=30dB
1: 1KHz
; I
I--
Fig. 6 - Distortion vs. frequency
0.4
0.3
LI
'0"
,'b CW1
'0
1-,
,
G-29~9"
I
('Io)
I
I
i
IT
0.'
i
1:11
.. 1
,
I
, I ,
V .d:14VI
f-
I
G :JOdS
f-
~~
0.2
f-
-
ft
I
_...
T.
I!,
,
i
10
,
.0
40
I
10'
rt+
10"
'it
10'
f (Hz)
Fig. 9 - Quiescent current
vs. supply voltage
I,
40
..:Hi .~
c~
MIl::
~
20
t (Hz)
60
,
80
4.:.<,/..::,9 _ _ _ _ _ _ _ _ _ _ _ _
616
10'
'"
(W)
eo
I
10'
'b
10
'00
+
;
/
0.'
,,,
I
!
I
G,
~.
,.
,_1
Fig. 8 - Frequency response
with different values of the
rolloff capacitor C8 (see
fig. 13)
I
0.' f-
1
i
0.3
,,
10'
i
"!
Ji
~.
0.'
-
(0. )
II
"
,
f-
s
0.3
I
'!
-,
)
--
lkH,
Fig. 7 - Distortion vs. frequency
.
'llll(-.1
.
iii'
+
0.'
(
Vs =.l:14V
Gv =30dB
RL=SJl
--t+
·-r
.+
_.
+ .
_.
J\
0.'
L
Po (w)
10
13-2462
("fo)
1kHz
"
lO'
'0'
~
..l'\,U
10'
~ I~~~m~':~~
f (Hz)
20
10
12
"
16
!Vs(V)
-------------
TDA2030
Fig. 11 - Power dissipation
and efficiency vs. output
power
Fig. 10 - Supply voltage
rejection vs. voltage gain
sv.
8.
"
LL
I
+--_ _ _ _ ..
12
8
6
60
40
30
4.2
6.2
8.3
--"5"'-0_ _ _ __
___________________________ ~~~~~~~~"~~~ ________________________~9/~9
621
TDA2030A
18W Hi-Fi AMPLIFIER AND 3SW DRIVER
The TDA2030A is a monolithic IC in Pentawatt®
package intended for use as low frequency class
AB amplifier.
With Vs max = 44V it is particularly suited for
more reliable applications without regulated
supply and for 35W driver circuits using lowcost complementary pairs.
The TDA2030A provides high output current
and has very low harmonic and cross-over
distortion.
Further the device incorporates a short circuit
protection system comprising an arrangement
for automatically limiting the dissipated power
so as to keep the working point of the output
transistors with in their safe operating area. A
conventional thermal shut-down system is also
included
Pentawatt
ORDERING NUMBERS: TDA2030A
TDA2030AH
ABSOLUTE MAXIMUM RATINGS
Vs
Vi
VI
10
Ptot
T stg , T J
Supply voltage
Input voltage
Differential input voltage
Peak output current (internally limited)
Total power dissipation at T case = 90°C
Storage and junction temperature
± 22
Vs
± 15
3.5
20
-40 to 150
v
TYPICAL APPLICATION
June 1988
1/14
623
TDA2030A
CONNECTION DIAGRAM
(top view)
~II
ll.::±::""~
~
~
I
••
:
NON INVERTING INPUT
5-Z62811
tab connected to pin 3
TEST CIRCUIT
THERMAL DATA
Rth j-case
624
Thermal resistance junction-case
max
3
°C/W
TDA2030A
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Vs= ±16V, Tamb = 25°C unless
otherwise specified)
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Ib
I nput bias current
Vas
I nput offset voltage
los
I nput offset current
Po
Output power
Test conditions
Min.
Typ.
Max.
Unit
± 22
V
50
80
mA
0.2
2
IJ.A
±2
± 20
mV
± 20
± 200
nA
±6
Vs = ± 22V
BW
Power bandwidth
SR
Slew Rate
Gy
Open loop voltage gain
d = 0.5%
Gy = 26 dB
f = 40 to 15000 Hz
RL=4n
R L =8n
15
10
18
12
Vs = ± 19V
R L =8n
13
16
Po~
R L =4n
15W
W
100
KHz
8
V/p.sec
80
dB
f = 1 KHz
Gy
Closed loop voltage gain
d
Total harmonic distortion
25.5
26
26.5
dB
Po= 0.1 to 14W
RL=4n
f = 40 to 15000 Hz
f = 1 KHz
0.08
0.03
%
0.05
%
0.03
%
0.08
%
Po = 0.1 to 9W
R L =8 n
f = 40 to 15000 Hz
d2
d3·
eN
Second order CC IF
intermodulation distortion
Po=4W
R L =4n
f 2 -f 1 = 1 KHz
Third order CCI F
intermodulation distortion
fl = 14 KHz
f2= 15 KHz
2 f 1 -f 2= 13KHz
I nput noise yoltage
B = curve A
2
B = 22 Hz to 22 KHz
3
p.V
iN
I nput noise current
B = curve A
50
B = 22 Hz to 22 KHz
80
R L =4n
Rg= 10 Kn
B = curve A
Po = 15W
106
Po = 1W
94
10
pA
SIN
Signal to noise ratio
200
dB
-------------- ~ ~~I~m&~I9©~ ____________~3/~1:=.4
625
TDA2030A
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
Ri
I nput resistance (pin 1)
(open loop)
f = 1 KHz
SVR
Supply voltage rejection
RL= 4 n
Rg= 22 Kn
Gv = 26 dB
f= 100Hz
Min.
Typ.
0.5
5
Mn
54
dB
145
°C
Thermal shut-down junction
temperature
Tj
Max.
Unit
Fig. 1 - Single supply amplifier
Fig. 2 - Open loop-fre·
quency response
D-
"
G.
'd.
Po
,. , 8.
)
,W J
Gv ·26dB
d =0.5·1.
I
PHASE
100
80
..
60
20
!""--...
GAIN
/
.....-
._---
C"--....
"
24
,.
20
eo
f=40Hz to15KHz
,,/
,,/
16
-
--
..........
-20
-40
~
Fig. 4 - Total harmonic
distortion vs. output power(*)
Fig. 3 - Output power vs.
supply voltage
"V
./
,,/
.......... V
K4l'l
.....~~
0.1
V
-f------
hIS KHz
-r;-.;;.:;----J)
0"'1-_-1---r'-'_1'T'·_-_+-_~-+-+--1
I
0.01 L...-'----'_-'----'_-'----'_-'---'
-60
24
"
32
36
0.1
0.3
10
30
Po{W)
*1 Test using noise filters .
.;,:4/.,::1..;,.4_ _ _ _ _ _ _ _ _ _ _ _ ~ ~tm~
626
-------------
TDA2030A
Fig. 6 - Large signal fre·
quency response
Fig. 5 - Two tone CCIF
intermodulation distortion
.,--,-,--,--,--,--,~~-.
(OW
G-U"
"0
,.".)
Vs:32V
Po"I,W
--- R L,,4n
2.
"20
Gy :26dB
f---+--t--+--t--+--+--+--i
II
0.' r-i"'=I=-;m~O:::RO;E::.:R'~2f;'-::.!'2~';j=--t-i
O,03t--t-c=l=:;1I:.:;O:::RO;JE11 l==1~:~~~~:~
/
5-262811
tab connected to pin 3
SCHEMATIC DIAGRAM
2
5-9227
THERMAL DATA
Rth j-case
638
Thermal resistance junction-case
max
3
TDA2040
ELECTRICAL CHARACTERISTICS (Refer to the test circuit,
Vs = ±16V,
Tamb = 25°C unless
otherwise specified)
Test conditions
Parameter
Vs
Supply voltage
Id
Quiescent drain current
Min.
Typ.
± 2.5
Vs= ± 4.5V
45
Ib
I nput bias current
Vos
I nput offset voltage
los
Input offset current
Po
Output power
BW
Power bandwidth
Gy
Open loop voltage gain
Vs= ± 20V
Max.
Unit
± 20
V
30
rnA
100
rnA
0.3
1
p.A
±2
± 20
rnV
±200
nA
d = 0.5%
f = 1 KHz
Tcase= 60"C
RL = 4.11
RL = 8.11
20
22
12
W
f=15KHz
RL= 4.11
15
18
W
Po= lW
R L = 4.11
100
KHz
80
dB
f = 1 KHz
Gy
Closed loop voltage gain
d
Total harmonic distortion
eN
iN
Input noise voltage
Input noise current
30
30.5
%
0.08
0.03
B = curve A
2
B = 22 Hz to 22 KHz
3
B = curve A
50
B = 22 Hz to 22 KHz
80
dB
10
pA
I nput resistance (pin 1)
SVR
Supply voltage rejection
Tj
R L =4n
f = 40 to 15000Hz
f = 1 KHz
p.V
Ri
1]
29.5
Po= 0.1 to lOW
Efficiency
R L =4n
Gy = 30 dB
f=100Hz
Rg= 22 Kn
Vripple= 0.5 V rms
f = 1 KHz
Po= 12W
Po= 22W
R L = 8.11
RL= 4.11
Thermal shut-down junction
ternperatu re
---------------------------~I~!~~&'~~
200
0.5
5
Mn
40
50
dB
66
63
%
145
°C
__ ____________________
~
~3/~1~O
639
TDA2040
Fig. 1 - Output power vs.
supply voltage
Fig. 2 - Output power vs.
supply voltage
Fig. 3 - Output power vs.
supply voltage
,..."
'WT
PoUT
(W,
(W,
Gy =30dB
d ,dO.,.
f .1KHz:
2.
RL-411.
v· lOdB
32
2.
~-+~+-~-+~~~~~RL7·A
,,~-+~+-~-+~~-I-~---J<~
d =0.5-"
1.15KHz
22
"
RL=4Jl
1/
1.
RL_8Jl
R.
20
14
1.
10
12
6
Ii
Fig. 4
frequency
d
(.",
Distortion
vs.
8
10
12
l'
16
±Vs IV)
11
Fig. 5 - Supply voltage
rejection vs. frequency
{d
G-50J6
B,
II
Gy"JOdB
RL ,,411
(dBI,r-r-r,--,-,-r-r,.-r-r-r-.-"r:-!!"!!:";-'
tr .100Hz
~ :~':6~1
~"O.5V
f-
RL=4.n.
!V. (V)
15
Fig. 6 - Supply voltage
rejection vs. voltage gain
Vs ll_16V
Po=l~W
13
70
++-1--+++-1--+--1
1-1-+-+-+-1-+-+-+-1
Rl=4 A
0.'
60
"
l/
0.4
0.3
40
I"
0.2
20
0.1
10
10'
10'
10'
I(Hz)
10'
10
Fig. 7 - Quiescent drain
current vs. supply voltage
10'
10 4
f (Hz)
10
Fig. 8 - Open loop gain vs.
frequency
80
40
Fig. 9 - Power dissipation
vs. output power
~
"rOT
(W,
t- !-....
1'\
60
12
1'\
/
50
1'\
01551'_.
16
±Vs IV)
I":
"- I'\.
10'
...:.4!..:;/l:.:.O _ _ _ _ _ _ _ _ _ _ _ _
640
10'
10'
f-- .. EFFICIENCY
.,n
10'
40
30
20
Vs " ±16
f ,,1KHz
10
1\
14
60
411.
r\
20
12
('to'
4.Il
.n:
10
40
10
GV(dB)
6-1031
,
G,
~8
30
20
f(lIa)
12
,.
20
24
Po (WI
/ifi. !~t~m?!£I~~ -------------
TDA2040
APPLICATION INFORMATION
Fig. 10 - Amplifier with split power
supply (*)
Fig. 11 - P.C. board and components layout of the
circuit of fig. 10 (1: 1 scale)
22~~:C100~~::r:::
s _·513711
Vs = ± l6V
RL= 4!1
PO;;' l5W (d
= 0.5%1
Fig. 12 - Amplifier with single supply (*)
Fig. 13 - P.C. board and components layout of the
circuit of fig. 12 (1:1 scale)
* In the case of highly inductive loads protection
diodes may be necessary.
5/10
641
TDA2040,
APPLICATION INFORMATION (continued)
Fig. 14 - 30W Bridge amplifier with split power supply
r---_----.....--_---Q+v.
811
22Mll
R7
-v
Vs = ± l6V
R L =8n
Po;;' 30W (d = 0.5%)
'-513'/3
Fig. 15 - P.C. board and components layout for the circuit of fig. 14 (1: 1 scale)
~6/~1~O______________________
642
~~~~~~~
_________________________
TDA2040
APPLICATION INFORMATION (continued)
Fig. 16 - Two way Hi-Fi system with active crossover
r-~----~'~=·~A--~t---------~~~----~----------O ••'
,.II.
WOOPe:R
INPUT
t--f----------~---1c.::;_--.-t;_::;:-----:O-I5V
TWEETER
'J>
S~UI'
Fig. 17 - P.C. board and component layout of the circuit of fig. 16 (1: 1 scale)
TWEETER
WOOFER
v
~ I~tm~~
___________
-.-:.7/~10
643
TDA2040
APPLICATION INFORMATION (continued)
Fig. 18 - Frequency response
Fig. 19 - Power distribution vs. frequency
G-4664
11111
11111
11111
0
WOOFER
(" .)
11111
111111
111111
111111
(dB)
AMP.
TWEETER AMR
Vs=:!1SV
Rl= SA
II
!7MODERN
MU51C
III
III
50
PO'" lW
"
-20
V
30
10
-'0
10'
10'
10'
f (Hz)
Multiway speaker systems and active
boxes
Multiway loudspeaker systems provide the best
possible acoustic performance since each loudspeaker is specially designed and optimized to
handle a limited range of frequencies. Commonly,
these loudspeaker systems divide the audio spectrum into two, three or four bands.
To maintain a flat frequency response over the
Hi-Fi audio range the bands covered by each
loudspeaker must overlap slightly. imbalance
between the loudspeakers produces unacceptable
results therefore it is important to ensure that
each unit generates the correct amount of
acoustic energy for its segment of the audio
spectrum. in this respect it is also important to
know the energy distribution of the music
spectrum determine the cutoff frequencies of
the crossover filters (see Fig. 19). As an example,
a 100W three-way system with crossover frequencies of 400Hz and 3KHz would require 50W
for the woofer, 35W for the midrange unit and
l5W for the tweeter.
Both active and passive filters can be used for
crossovers but today active filters cost sign ificantly less than a good passive filter using aircored inductors and non-electrolytic capacitors.
In addition, active filters do not suffer from the
typical defects of passive filters:
power loss
- increased impedance seen by the loudspeaker
(lower damping)
- difficulty of precise design due to variable
loudspeaker impedance
644
I
20
\
V
E TIN
70
'0
11111
/
~EAI(ER
80
V
10
lEe-DIN
FOR
l -I--
90
II
Y
0.02 0.04 0.080.16 0.31 0.63 1.25 2.5
5
10 20
'(KHz)
Fig. 20 - Active power filter
Vin~I-T-r
~,.
5--4479/1
Obviously, active crossovers can only be used if
a power amplifier is pro~ided for each drive unit.
This makes it particularly interesting and economically sound to use monolithic power amplifiers.
In some applications, complex filters are not
really necessary and simple RC low-pass and
high-pass networks (6dB/octave) can be recommended.
The results obtained are excellent because this
is the best type of audio filter and the only one
free from phase and transient distortion.
The rather poor out of band attenuation of
single RC filters means that the loudspeaker must
operate linearly well beyond the crossover frequency to avoid distortion.
.
A more effective solution, named" Active Power
Filter" by SGS is shown in Fig. 20.
The proposed circuit can realize combined power
amplifiers and 12dB/octave or l8dB/octave highpass or low-pass filters.
TDA2040
APPLICATION INFORMATION (continued)
SHORT CIRCUIT PROTECTION
In practice, at the input pins of the amplifier two
equal and in-phase voltages are available, as
required for the active filter operation.
The impedance at the pin (-) is of the order of
100n,while that of the pin (+) is very high,
which is also what was wanted.
The component values calculated for fc = 900Hz
using a Bessel 3rd order Sallen and Key structure
are:
The TDA2040 has an original circuit which limits
the current of the output transistors. This function can be considered as being peak power
limiting rather than simple current limiting. The
TDA2030A is thus protected against temporary
overloads or short circuit. Should the short
circuit exist for a longer time the thermal shut
down protection keeps the junction temperature
within safe limits.
THERMAL SHUT-DOWN
C1 = C2 = C3
R1
R2
R3
22nF
B.2Kn
5.6Kn
33Kn
In the block diagram of Fig. 21 is represented an
active loudspeaker system completely realized
using power integrated circuit, rather than the
traditional discrete transistors on hybrids, very
high quality is obtained by driving the audio
spectrum into three bands using active crossovers
(TDA2320A) and a separate amplifier and loud·
speakers for each band.
A modern subwoofer/midrange/tweeter solution
is used.
The presence of a thermal limiting circuit offers
the following advantages:
1) An overload on the output (even if it is
permanent), or an above limit ambient temperature can be easily supported since the Tj
cannot be higher than 150°C.
2) The heatsink can have a smaller factor of
safety compared with that of a conventional
circuit. There is no possibility of device
damage due to high junction temperature. If
for any reason, the junction temperature
increase up to 150°C, the thermal shut-down
simply reduces the power dissipation and
the current consumption.
Fig. 21 - High power active loudspeaker system using TDA2030A and TDA2040
I
I
L __
I
811
I MIDRANGE
J
I
811.
I SUBWDDFER
811.
: MIDRANGE
5-5139
------------
~ I~tm?=:
___________
""'9/:..:..:,10
645
TDA2040
PRACTICAL CONSIDERATION
Printed circuit board
Application suggestions
The layout shown in Fig. 11 should be adopted
by the designers. If different layouts are used,
the ground points of input 1 and input 2 must be
well decoupled from the gorund return of the
output in which a high current flows.
The recommended values of the components
are those shown on application circuit of Fig. 10.
Different values can be used. The following table
can help the designer.
Assembly suggestion
No electrical isolation is needed between the
package and the heatsink with single supply
voltage configuration.
Larger than
recommended value
Smaller than
recommended value
Component
Recomm.
value
R1
22KU
Non inverting input
biasing
Increase of input
impedance
Decrease of input
impedance
R2
680U
Closed loop gain
setting
Decrease of gain (*)
Increase of gain
R3
22KU
Closed loop gain
setting
Increase of gain
Decrease of gain (*)
R4
4.7U
Frequency stability
Danger of oscillation
at high frequencies
with inductive loads
C1
1J.1F
C2
Purpose
Input DC
decoupling
Increase of low frequencies cutoff
22J.1F
Inverting DC
decoupling
Increase of low frequencies cutoff
C3, C4
O.1J.1F
Supply voltage
bypass
Danger of oscillation
C5, C6
220J.lF
Supply voltage
bypass
Danger of oscillation
C7
O.1J.1F
Frequency stability
Danger of oscillation
(") The value of closed loop gain must be higher than 24dB.
;:,.10:..:../;:..10'--_ _ _ _ _ _ _ _ _ _
646
~ !~I~m?::£'
-------------
TDA2220
AM/FM RADIO
•
•
•
•
•
•
•
•
VERY WIDE RANGE OF SUPPLY VOL TAGE 3 to 16V
HIGH RECOVERED AUDIO SIGNAL (100
mV, Llf = ± 225 KHz or m = 0_3)
DESIGNED FOR USE WITH EXTERNAL
RATIO DETECTOR OR INTERNAL QUADRATURE DETECTOR
VERY GOOD AM SIGNAL HANDLING
(lV; m = 0_8)
VERY SIMPLE DC SWITCHING OF AM-FM
SECTIONS
SUITABLE FOR CAPACITANCE, VARICAP
AND INDUCTIVE TUNING
VERY LOW TWEET
COMMON (AM-FM) FIELD STRENGTH
METER OUTPUT PIN
The TDA 2220 is a high performance AM/FM
radio IC designed for use in a wide range of car
radio, portable radio and home 'radio applications, operating on a supply voltage from 3 to
16V. A special feature of this device is that it
may be used with an internal quadrature detector
or an external ratio detector. The TDA 2220 is
supplied in a 20 pin plastic DIP package.
DIP-20 Plastic
(0.4)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation at Tamb .:;;;; 70°C
Operating temperature
Storage and junction temperature
16
800
V
mW
-40 to 85°C
-55tol50
°C
BLOCK DIAGRAM
10
5-GHD
June 1988
1/8
647
TDA2220
CONNECTION DIAGRAM
LOCAL
(top view)
IF FM INPUT
OSCILLATOR
OSCILLATOR
'tIME
IF FM BYPASS
19
CONSTANT
AM INPUT
18
IF FM BVPASS
MIXER OUl
17
METER OUTPUT
AMPLIFIER
AGe (BYPASS)
LIMITER OUTPUT
AM IF
LIMITER OUTPUT
INPUT
:~p.fSE;ECTOR
7
AM DETECTOR
8
FM QUADRATURE
DETECTOR
GNO
AUDIO PREAMP.
AGe BYPASS
AF OUTPUT
INPUT
(RATIO DETECTOR)
10
11
SUPPLY VOLTAGE
5.6093/1
THERMAL DATA
Rth j-amb
Thermal resistance junction ambient
max 100 °C/W
ELECTRICAL CHARACTERISTICS (Refer to the test circuits, Tamb = 25°C,
otherwise specified)
Parameter
Vs
Supply voltage
Id
Cu rrent drai n
Vs
9V,
unless
.
Test conditions
Min.
Typ.
Max.
Unit
3
9
16
V
AM Section
10
FM Section
10
16
14
21
21
mA
12
25
p.V
AM SECTION (fo = 1 MHz; fm = 1 KHz)
Vi
S+N
-N-
I nput sensitivity
Signal to noise ratio
SIN = 26 dB
m =0.3
Vi = 10mV
m =0.3
45
dB
Vi
AGC range
c.V out = 10dB
m = 0.8
100
dB
Vo
Recovered audio signal (pin 10)
VI=1 mV
m =0.3
75
d
Distortion
120
170
0.5
%
d
Distortion
Vi = 1 mV
m =0.8
VH
Max input signal handling
capability
m = 0.8
d< 10%
Ri
I nput resistance between
pins 3 and 5
m=O
7.5
Kn
Ci
I nput capacitance between
pins 3 and 5
m=O
18
pF
Ro
Output resistance (pin 10)
Tweet 2 IF
Vi= 1mV
V m (*)
Meter output
Vi= 1 mV
%
V
7
9.5
Kn
38
dB
55
dB
130
mV
Kn.
:;:2/..:,8_ _ _ _ _ _ _ _ _ _ _ _
648
m= 0.3
3
1
4.5
m =0.3
Tweet 3 IF
(*) Meter resIstance - 1.3
2
mV
~ l~tmg'f~~AI-------------
TDA2220
ELECTRICAL CHARACTERISTICS
Parameter
FM SECTION (fo
(Continued)
Test conditions
= 10.7MHz; fm = 1 KHz)
(RATIO DETECTOR)
Vi
Input limiting voltage
-3 dB limiting point
AMR
Amplitude modulation
rejection
lit = ± 22.5KHz
Vi =3mV
m =0.3
50
60
dB
S+N
-N-
Signal to noise ratio
lit = ±22.5KHz
Vi = 10mV
55
65
dB
d
Distortion
lit = ±75KHz
Vi= lmV
0.4
d
Distortion
lit = ±22.5KHz
Vi=lmV
0.2
Vo
Recovered audio signal
(pin 10)
lit = ±22.5KHz
Vi=lmV
Ri
I nput resistance between
pin 20 and ground
lit =0
6.5
Kn
Ci
Input capacitance between
pin 20 and ground
lit = 0
14
pF
Ro
Output resistance (p!n 10)
V m (*)
Meter output
25
75
4.5
Vi= 1 mV
lit = ± 22.5 KHz
FM SECTION (fo = 10.7MHz; fm = 1 KHz)
120
7
36
0.7
IlV
%
%
170
9.5
mV
Kn
mV
110
(QUADRATURE DETECTOR)
Vi
Input limiting voltage
-3dB limiting point
AMR
Amplitude modulation
rejection
lit = ±22.5KHz
Vi= 3mV
m =0.3
35
44
dB
55
65
dB
S+N
25
36
)JV
Signal to noise ratio
lit = ±22.5KHz
Vi= 10mV
d
Distortion
lit = ±75KHz
Vi= lmV
0.7
d
Distortion
lit = ±22.5KHz
Vi= lmV
0.25
%
d
Distortion (double tuned)
0.1
%
I\J
V I = lmV
1.5
%
Vo
Recovered audio signal (pin 10)
lit = ±22.5KHz
Ri
I nput resistance between
pin 20 and ground
lit = 0
6.5
Kn
Ci
I nput capacitance between
pin 20 and ground
lit =0
14
pF
Ro
Output resistance (pin 10)
V m (*)
Meter output
60
4.5
Vi= 1 mV
lit = ± 22.5 KHz
90
7
110
130
9.5
mV
Kn
mV
(*) Meter resistance = 1.3 Kn.
------------- ~ 1~~~m~/19A1------------3-'-/8
649
TDA2220
Fig. 1 -- Test circuit with FM ratio detector
r-~~~~~~--~~~~--~----------------~~--o~
].fo2SF
r---------+-oAFC
,1--+--U-------f--o~~~'O
~~H~N o---U-~-1
TDA 2220
FM IN s>--'''+'-''F~-I
10.7 MHz R2
56n
FM
C4
o
AM
(0)
The audio output ampli·
tude can be modified
changing the resistor value
S_609~/2
Fig. 2 -- P.C. board and component layout of the circuit of fig. 1 (1: 1 scale)
4/8
650
~ ~~~~m~1J~:~~Al
--------------
TDA2220
Fig. 3 - Test circuit with FM quadrature detector
.-~~~~r---~Wl~~-t~~~~~------~~~
:Eio1ZF
r-----+-oAFC
,1--t--IIt----t---o:~~~IO
:'H~N
0----11....'-1
FM IN o-''+'-lIRH
'Kl.7 MHZ R1
H--CJ."o-.--o v m
S6n
o
AM
$-6096/1
Fig. 4 - P.C. board and component layout of the circuit of fig. 3 (1: 1 scale)
------------- ~ l~tm?:19~
5/8
651
TDA2220
L 1 - 455kHz IF Coil
Co(pF)
00
1-3
1-3
1-2
70
57
f
f----=-- (MHz)
180
455
TURNS
I
I 4-6
I 24
2-3
I 116
TOKO AM3 -10x10 mm
RLC - 4A7525N
L2 - AM Detector Coil
Co(pF)
-
1-3
f
(KHz)
00
TURNS
1-3
1-2
173
I 2-3 r 4-6
I 94 I 9
180
455
70
f
(kHz)
()L~)
00
1-3
1-3
1-2
I
2-3
4-6
220
80
2
I
75
8
TOKO AM2 - 10x10 mm.
RLC-4A7524EK
L3 - AM Oscillator Coil
796
TURNS
TOKO - 10x10 mm.
RWO - 6A6574N
L4 - FM Detector Coil
~
ill
1
Q
®
Co(pF)
- 1-3
f
(MHz)
82
10.7
0
TURNS
0
1-3
1-3
100
12
I
I
TOKO -10x10 mm
KACS - K586 HM
I-
-
I-
-
L5 - Ratio Detector
C1(pF)
C2(pF)
3-11
6-8
27
47
IN
00
f
(MHz)
3-11/4-8
10.7
70
SUMIDA
DFM
TURNS
5-6098
_6/0-8_ _ _ _ _ _ _ _ _ _ _ _ _
652
1-3
1-4
2-10
5-9
6-7
7-8
11
6%
5%
%
7
7
~ 1~I~mg~£&~
--------------
»
"tI
"tI
Fig.5 - AM/FM car radio receiver
rn
~
oz
Z
...
."
o
::XI
:s:
»
e31
IIt1O/J
L1
F
:::!
4.1,uH
o
z
MURATA
SFZ 1o!1o!iF
~
AUDIO
00
I~
aIDUI
OUT
O-I,uF
© ,
TOA 2220
Ig
-I
I
~Z
I
I
, __ J.I _____ -II
I
I
I
I
!
.,
!
F~i
'
o
I
loon
I
SWI
AM
I
I
:
FM
TUNER
RIO
I
n 2:
:
:.
L_________ I
~
OOOKn
"'CoIS:
~e"
J: 10nF
J:nl,l
~l----------------loon
"OKn
-I
Note - The transistor Q1 can be eliminated using the tuner of fig. 7.
CJ)
~
....
Ol
~
I\)
~
TDA2220
Fig. 6 - P.C. board and component layout of the circuit of fig. 5 (1: 1 scale)
==::I-==b Nco
a
I
III
u
~8~/8________________________
654
~~i~~~~~
__________________________
TDA2320
I"
!
PREAMPLIFIER FOR INFRARED REMOTE CONTROL SYSTEMS
The TDA2320 is a monolithic integrated circuit
in Minidip package specially designed to amplify
the I R signal in remot controlled TV or radio
sets. It directly interfaces with the digital control
circuitry.
The TDA 2320 incorporates a two stages ampli·
fier with excellent sensitivity and high noise
immunity. It can work with a single 5V supply
voltage and flash or carrier transmission modes
as provided for example by the M709/M710CI
MOS transmitter.
The TDA2320 is particularly intended to be used
in conjunction with the M104 and M206 +
M3870 remote control receivers.
Minidip Plastic
ORDERING NUMBER: TDA2320
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage and Junction temperature
Total power dissipation at T amb = 70°C
20
V
-40 to 150°C
400
mW
APPLICATION CIRCUIT (Flash mode preamplifier)
RS 1KJl
r-~--~--------~~~------------~~~--o+5V
1N4146
02
47Kn
1ZKJl
R7
$-4959/1
June 1988
1/5
655
TDA2320
CONNECTION AND BLOCK DIAGRAM
(top view)
OUTPUT
+Vs
A
OUTPUT B
INV.INPUT A
NON INV.INPUT A
3
6
INV.INPUT B
GNO
4
5
NON INV.INPUT B
5- 5105
SCHEMATIC DIAGRAM
(one section)
INVERTING
INPUT
NON INVERTING
INPUT
8
r---~------+-----~----~~--~----'-------~-------o~s
Rl
R7
OUTPUT
Ql&
01
02
4
~--~---*--~~---+--~------~----~------~----~-o~s
5-5155
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
=-2/~S------------liii.I~I~m?v~~lt
656
max
200
------------
TDA2320
ELECTRICAL CHARACTERISTICS (Vs= 5V, Tamb = 25°C, single amplifier, unless otherwise
specified)
Parameter
Vs
Supply voltage
Is
Total supply current
Ib
I nput bias current
Vos
I nput offset voltage
los
Input offset current
Gy
Open loop voltage gain
Test conditions
Min.
Typ.
Max.
Unit
20
V
0.8
2
mA
100
500
nA
4
Vs = 20V
R g < 10 K!l
f
= 1 KHz
f
= 100 KHz
64
0.5
mV
15
nA
70
dB
30
dB
3
MHz
B
Gain bandwidth product
f = 40 KHz
SR
Slew rate
R L = 2 K!l
1.5
V/p.s
eN
Total input noise voltage
f =40 KHz
Rg= 10K!l
20
nv;.jH;
2.5
Vpp
80
dB
Vo·
DC output voltage swing
SVR
Supply voltage rejection
1.5
f= 100 Hz
APPLICATION INFORMATION
Fig. 1 - Application circuit for carrier transmission mode
IKlt
IOI
I'F
s- 6327
------------- ~ ~~tm=£?lt ____________
-=-3/5
657
TDA2320
.APPLICATION INFORMATION (continued)
Fig.2 - Flash mode preamplifier
Fig. 3 - P.C. and components layout of the circuit of fig. 2 (1
Fig. 4 - I R transmitter using M709 or M710
1 scale)
Fig. 5 - MMC " - PLL TV Frequency synthesizer
33.n
+9Vo--------.o----r--l-----+-_
ON/OfF
..,:.4/:..:5_ _ _ _ _ _ _ _ _ _ _ _
658
~ l~m~SJI~
------------
TDA2320
APPLICATION INFORMATION (continued)
Fig. 6 - I R Preamplifier and Remote Control receiver for 32 channel voltage synthesizer (EPM - M293)
"''*
11\,1
' ' ·1.1 - :f
I
~
L,J
rI "",,'
t>
2~lnF ,
4
411'1f
~"
J,~
rl-
II,3JI\11
~/~A2J20
J
--*-
~t !
..
tl
5 ...
!'n i ," I
~ BPWIoI
4.75
"
1
~ Stand
..
B.2Kn
.n
.r"Oti'·'OlO"
".?nF
33K.n
14
~
INFRARED
5.2SV
~ BCl7S
;O~
1-
"'1\
12'ft
"'1\
£OOK1\
~
22Kfl
17
I
PREAMPLlfJER
16
,2
by
Relay
osc .
S:'OOPF
PA 26
",,25
Pc
M293
210
Po 23
• A
6 •
*-F
7
PE 22
c
• 0
M104
27
<0,
'0
9
Res. 2
"
.lO
-
1
19
II !I II II II I1 II II rl II II jl
p
+
+'
-
@l
,1;+
-,9,-
()
~
0
27KI1.
~
lJ·n
~'5
21
120
I
~
~
5-5136
-------------
RH.1
Vol.
:c'DOnF
!WI
Col.Sat.
• ,oonF
2'Z.JS..q
::C:
:r
sri hi
lOOnF
UJUl.
Con"
:!:tOOnF
.j.12V
~ ~~~m~:
____________
5~/5
659
TDA2320A
MINIDIP STEREO PREAMPLIFIER
• WIDE SUPPLY VOLTAGE RANGE (3 TO
36V)
• SINGLE OR SPLIT SUPPLY OPERATION
•
VERY LOW CURRENT CONSUMPTION
(0.8mA)
•
VERY LOW DISTORTION
•
NO POP-NOISE
players and high quality audio systems.
The TDA2320A is a monolithic integrated
circuit a 8 lead minidip.
Minidip Plastic
• SHORT CIRCUIT PROTECTION
The TDA2320A is a stereo class A preamplifier
intended for application in portable cassette
ORDERING NUMBER:
TDA 2320A
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation at Tamb = 70°C
Storage and junction temperature
36
V
400
mW
-40 to 150°C
TYPICAL APPLICATION:
Stereo preamplifier for cassette players
18kft
-ys
22,..Fr-~--=}-~-~-----t--o
~
O.J~Y
4.7
TAPE
HEAD
82Kll
F
'~
•
100
K.o.
20
:::I: 22,..F
18K.d
O~JmY4.7
APE
AD
F
1
•
5-416&/1
June 1988
1/10
661
TDA2320A
CONNECTION AND BLOCK DIAGRAM
(top view)
OUTPUT
8
A
IN'lINP.
A
B
NON INV.
INP.A
-lis
~s
OUTPUT
6
INILJNI?
NON INV.
INP. B
4
5-3590
SCHEMATIC DIAGRAM
(one section)
INVERTING
INPUT
NON INVERTING
INPUT
8
~--~------+-----~----~--~r---~~------~-------o+VS
OUTPUT
Q16
01
02
4
- - - - + . - - - - 4 - - - - -..----+--o-VS
5-51 S5
~2/:..:1.:..0 _ _ _ _ _ _ _ _ _ _ _ Gii.1~I~uI------------
662
TDA2320A
TEST CIRCUITS
Fig. 1
22 F
...c-II~--I:::::J---+--,
l,u~OUT
.1!.
G =
v
Rx
22K.Q.
+ 150
150
Gv = 20 dB for Rx = 13500
5- 4664
Fig. 2
+ 7.5V
A>-+--oOUT
_________________________
~!~~~~~~
_____________________
~3/~lO
663
TDA2320A
THERMAL DATA
Rth
j-amb
200
max
Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,
Vs = 15V,
Tamb =
25°C,
unless
otherwise specified)
Parameter
Vs
Supply voltage (*J
Is
Supply current (oJ
Ib
I nput bias current
Vas
I nput offset voltage
los
Gy
Open loop voltage gain
Test conditions
Min.
R g <10Kn
Vs=15V
Output voltage swing (*J
Max.
Unit
36
V
0.8
2
mA
150
500
nA
1
5
mV
10
50
nA
3
I nput offset current
Va
Typ.
f = 333 Hz
80
f = 1 KHz
70
f = 10 KHz
50
70
Vs = 4.5V
f = 1 KHz
f = 1 KHz
Vs= 15V
13
RL= 600n
Vs= 4.5V
2.5
dB
Vpp
B
Gain-bandwidth product
f = 20 KHz
1.5
2.5
MHz
BW
Power bandwidth (oJ
Vo= 5 Vpp
d = 1%
40
70
KHz
SR
Slew rate (*J
1.6
V//JS
d
Distortion (oJ
Total input noise
voltage ('OJ
eN
1
Vo= 2V
f = 1 KHz
0.03
Gy = 20 dB
f = 10 KHz
0.08
Curve A
B - 22 Hz to
22 KHz
Rg= 50n
1
Rg= 600n
1.1
Rg= 5 Kn
1.5
Rg= 50n
1.3
Rg- 600n
1.5
f!g~
5 Kn
%
1.4
/JV
/JV
2
Ra= 600n
9
Cs
Channel separation (ooJ
f = 1 KHz
100
dB
SVR
Supply voltage ('*J
rejection
f= 100 Hz
80
dB
f = 1 KHz
(*J
Test circuit of fig. 1.
(**J Test circuit of fig. 2.
664
nVl.JHz
TDA2320A
Fig. 3 - Supply current vs.
supply voltage
Fig. 4 - Supply current vs.
ambient temperature
G-4553
G-4554
IS
I
(rnA I
Fig. 5 - Output voltage swing
vs. load resistance
Vo r--r-T"'lrTTT'r---r-,-,-rr\%
(vpp)t--t-HH-tt-fVs= 30V.
Vs=15V
24
0.9
-
..-
0.8
f-
-
1---~-H~Wf+!Gy' 20dB
LO
20 I---I--Hl-hlf+f+! t
,.- ,....
1+++++++1
/,/
1/
0.6
0.7
r
I.. -
.,
/
.
D.•
-so
24
"
'" 1kHz
f--+-++.H+fl+ -
16
Fig. 6 - Power bandwidth
so
10'
10'
Fig. 8 - Total input noise vs.
source resistance
Fig. 7 - Total harmonic
distortion vs. output voltage
I"m-'r~~
, I--
B;;22Hzto22KHz
--_.. i '
-
0.1
curve A
,'!
I
,ii,
~~_;:t::=:~iT
"
;Ii'
0.Q3
i
0.1
0.1
-0,3
10
Fig. 10- RIAA preamplifier
response (circuit of fig. 12)
Fig. 9 - Noise density vs.
frequency
dB1
)
v,..15V [-
(
......-
j--;:---+,"
,
.
----'-.
':,'
i'l ,:,iii.
..
'I, ,ill
10'
Rg
en)
Fig. 11 - Tape preamplifier
frequency response (circuit
of fig. 14)
8IEIEIEIEIEI83
,.',
-l+I-tJIf--j--f-j-IllllHVs ,,4.5V
-·-H4H*~~j##~fE70T·':12TO~"~'~~Hm
70-
-1,
Rg ",10KIl
.......
10
IKn
- -50n
20
r----------TIB~s·
I
10'
,
I
I
(500H;c)'
"-.
i
I
! , i, ,
10'
'l'l:i
,.
10'
10
30 HKHz)
---+----'"-
,
.
10'
'20KHz
'°r--rHiffiff-ttHBffl'~±H~~~~ffiffi
30
1--
1-
.,
f{Hz)
~ !~tm~'~lt
____________
5/'-10
665
TDA2320A
APPLICATION INFORMATION
18KU
Fig. 12 - Stereo RIAA preamplifier
+ 15V
22,..Fr-~~--CR=51--"--"------"""-o
C3
C'3J:0.'I'F
:::r
OUT( L)
R6
OUT(R)
~~~I~~---O
s- lo670f2
Fig. 13 - P.C. board and components layout of the circuit of fig. 12
IN(L)
IN(R)
OUT(L) +vs
~6/~1~O________________________
666
~!~~~~~~~
___________________________
TDA2320A
APPLICATION INFORMATION (continued)
Fig. 14 - Stereo preamplifier for Walkman cassette players
18Kll
+ Vs
'~
20
K
Fig. 15 - Second order 2 KHz Butterworth crossover
filter for Hi-Fi active boxes
Fig. 16 - Frequency response
(circuit of fig. 15)
+ 15 V
,"'r
~ SKJl
Ie = 2KHz
-ISV
LOW-PASS
HIGH-P
/'"
\
WOOFER
AMPLIFIER
\
ro
\
12d8/octave
fl
T2dB/oclay~
S.6K
I.
,
IN
Id"
rro
20
O.I,uF
SKJl
TWEETER
AMPLIFIER
24
tOo,
.
tlfe
5.6Kn
5- 466211
___________________________
~~~~g~~
________________________
~7/~1~O
667
TDA2320A
APPLICATION INFORMATION (continued)
Fig. 18 - Frequency response
(circuit of fig. 17)
Fig. 17 - Third order 2.8 KHz Bessel crossover filter for Hi-Fi
.,5V
active boxes
l
-
HI H
\
INPUT
fc
=2.8KHz
12
f----+-++.H-lf++-+++I--I+J.H
16
f----+-++!-Hf++--f-!I++I--I+J.H
,0 f----+---j,f+-!-Hf++-+++I--I+J.H
TWEETER
:(I)
INPUT·>( 2)
16
1
15
N.C.
INPUT-(1)
N.C.
INPUT~(2
14
3
)
GNP
13
GNP
12
GNP
11
PUTPUT(2 )
'0
N.C.
OUTPUT(')
6
N.C.
GNP
• v.
N.C•
S-UB&
SCHEMATIC DIAGRAM
.v,
"~~~--~~--~----~-----r-------------r------------~----------~--~~r-;--'
0'
,
0U'
OUT
)11
0"
02
ONO
4,5,12,13
INPUT
,.
10
+
!NPUT
14
THERMAL DATA
Rth j-amb
Rm j-c....
Thermal resistance junction-ambient
Thermal resistance junction-pins
~2/~8________________________
672
~!~!;~~~~
max 80
max 20
°C/W
°C/W
__________________________
TDA2822
ELECTRICAL CHARACTERISTICS (v. = 6V, Tamb = 25°C, unless otherwise specified)
Parameter
Test Conditions
STEREO (Test circuit of Fig. 1)
V.
! Vc
I
Supply voltage
Quiescent output voltage
Id
Quiescent drain current
Ib
Input bias current
Po
Output power
(each channell
Gv
3
15
4
2.7
V. = 9V
V. = 6V
6
d = 10%
Vs = 9V
Vs = 6V
Vs = 4.5V
f = 1 KHz
RL = 4n
RL = 4n
RL
4n
V
V
12
nA
1.3
0.45
1.7
0.65
0.32
W
W
W
39
=
f = 1KHz
36
RI
Input resistance
f = 1KHz
100
eN
Total input noise
B = 22Hz to 22KHz
41
2.5
IlV
2
Curve A
f = 100Hz
CS
Channel separation
Rg = 10Kn
dB
Kn
Rs = 10Kn
Supply voltage rejection
mA
100
Closed loop voltage gain
SVR
V
24
f = 1KHz
30
dB
50
dB
BRIDGE (Test circuit of Fig. 2)
V.
Supply voltage
3
Id
Quiescent drain current
RL =
Vos
Output offset voltage
RL = an
Ib
Input bias current
Po
Output power
co
d = 10%
Vs = 9V
Vs = 6V
V. = 4.5V
f =
RL
RL
RL
Po = 0.5W
d
Distortion (f = 1 KHz)
RL = an
Gv
Closed loop voltage gain
f = 1KHz
RI
Input resistance
f = 1KHz
eN
Total input noise
15
V
6
12
mA
10
60
mV
100
nA
3.2
1.35
1
W
W
W
0.2
%
39
dB
1KHz
= an
= an
= 4n
2.7
0.9
Kn
100
B = 22Hz to 22KHz
3
Rs = 10Kn
IlV
curve A
SVR
Supply voltage rejection
f = 100Hz
--------------------------~!~1~~?~~~4
2.5
40
dB
________________________3~/8
673
TDA2822
Fig. 1 - Test circuit (STEREO)
INo-~~
______~+-__~
(Ll
~
C1
100,.,FI
O'l"'F
R3
TDA2822
4.7n.
INo-~~_______1~6+-__~
C5 1000,.,F
(Rl
4.5.12. 13
s- 6288/1
Fig. 2 - P.C. board and components layout of the circuit of Fig. 1 (1 : 1 scale)
cr
ILl
Z
~
<.!)
Vi
~
z
0
z
<.!)
cr
~
l?
0
z
<.!)
If)
>
+
~
~
cr
cr
~
cr
~4/~8------------------------~!~~;~~19~
674
--------------------------
TDA2822
Fig. 3 - Test circuit (BRIDGE)
TDA2822
IN 0---.----'-t--;
RL
4,5,12,13
Fig. 4 - P.C. board and components layout of the circuit of Fig. 3 (1 : 1 scale)
o
z z
~
cr
0
z
If)
>
+
~
cr
------------- ~ 1~;m~19~ ____________5~/8
675
TDA2822
Fig. 5 - Output power vs.
supply voltage (Stereo)
Fig. 6 - Output power vs.
supply voltage (Bridge)
,..
G-61~5
Po
Po
,WI
'10I
Fig. 7
Distortion
output power (Bridge)
G·&14J
I
Rl"sn
d ~10·1o
""KHz
'=IKHz
RL"all
d .. l0 ...
f" 1KHz
j
L
V/
,V
10
12
..
II
II
"
. III
6V
T
30
-
0.'
11
BRIDGE
EO
,/
-
YR "O.5VRM5
",
Vs·gy
"
'Is (V)
Fig. 13 - Total power dissipation vs. output power
(Bridge)
{WI
z.s I-
',,'II(H,z
--
"S·4.5V
..
16
PIoI
I.Z
l- i-/'
,
AL"an.
'.IKHz
I
"s"
1-1-
I---
j:::
I.S
/
s. v
o.S
O~
676
HHz)
I
1.&
So"r
I
-
/
R L,,44
RL=~~
t =IKHz
7
'mA I
Fig. 12 - Total power dis·
sipation vs. output power
(Bridge)
P lol
{WI
PloI
{W I
/
Fig. 10 - Quiescent current
vs. supply voltage
,...,,,
:~::~III
10'
Fig. 11 - Total power dissipation vs. output power
(Stereo)
V .....
I.
~(WI
10
I.Z
7
1.5
20
II
'0
t...-- V
p !-
"'stYI
6-1150
';;IKHz
I
12
Fig. 9 - Supply voltage
rejection vs. frequency
Rt"loll
1,.5'1
~
10
vs.
1>-6146
V
V
YSI'l)
Fig. 8
Distortion
output power (Bridge)
~
1
/
~~
I
"
6V
RCoan.
/
Rt"loO/
,..
vs.
.S
IS
2.5 PatWI
TDA2822
Fig. 14 - Application circuit for portable radios
r---~--~--____~'=7n~~__~'-______________-'~~__~~~____r-~'.Y
l00,..F
I
6800
"'KIt
107KIl
TEA 1330
YCO
o.l,..F
STOP
1+---+-1-""
"'~~J:.F
47Kll
22K.Q
4.'.0
4.n.
2Zo"F
Ol~~
47n~
p.n
MOUNTING INSTRUCTION
The Rthj",mb of the TDA2822 can be reduced by
soldering the GND pins to a suitable copper area
of the printed circuit board (Fig. 15 or to an
external heatsink (Fig. 161.
The diagram of figure 17 shows the maximum
dissipable power Ptot and the Rthj",mb as a function of the side "Q" of two equal square copper
areas having a thickness of
AREA
JS,.
(1.4milsl.
The external heatsink or printed circuit copper
area must be connected to electrical ground.
Fig. 15 - Example of p.e. board copper area
which is used as heatsink.
COPPER
35~
During solderinJ! the pins temperature must
not exceed 260 e and the soldering time must
not be longer than 12 seconds.
Fig. 16 - External heatsink mounting
example
THICKNESS
5-3181
P. C. BOARD
-------------------------- ~!~t~~g,~~ -------------------------7/8
677
TDA2822
MOUNTING INSTRUCTION (continued)
Fig. 6 - Maximum dissipable power and junction to
ambient thermal resistance
vs side "~ ..
O-K.
PlOt
IW)
Fig. 7 -Maximum allowable
power dissipation vs. ambient temperature
•
I
".,
6-3H111
~S
Rth i~afftb
:--...
..... ~ ~t
-- -
~
..
..0
""'a/8:..;;...._ _ _ _ _ _ _ _ _ _ _
678
'"
1("",,)
\'-
'%,~
~~4'19
-so
50
~
'.~
4~
p.
(T amb • 7O'C)
I
10
10
......
\1:\
S~
10
I\.
,,-
~
100
~t
-,.;
Tamb('C)
A.W.. ~~ - - - - - - - - - - - -
TDA2822M
DUAL LOW-VOLTAGE POWER AMPLIFIER
•
SUPPLY VOLTAGE DOWN TO 1.8V
•
LOW CROSSOVER DISTORTION
•
LOW QUIESCENT CURRENT
•
BRIDGE OR STEREO CONFIGURATION
Minidip Plastic
The TDA2822M is a monolithic integrated circuit
in 8 lead Minidip package. It is intended for use
as dual audio power amplifier in portable cassette
players and radios.
ORDERING NUMBER: TDA2822M
ABSOLUTE MAXIMUM RATINGS
VS
10
Ptot
Tstg , 1j
Supply voltage
Peak output current
Total power dissipation at Tamb = 50°C
at T case = 50°C
Storage and junction temperature
15
1.4
-40 to 150
V
A
W
W
°c
TEST CIRCUIT
(It,o--....-----L.j----I
RI
lOK.ll
~
el
o.IPF
R3
lOOPFI
4.7n
IN 0--.......-_ _ _-'<.61----1
(Rl
s
lOKa
eZI
10~F
4
5- 612711
June 1988
1/10
679
TDA2822M
CONNECTION DIAGRAM
(Top view)
OUTPUT (I)
SUPPLY VOLTAGE
2
OUTPUT(2)
GROUND
4
S~61Z5
SCHEMATIC DIAGRAM
;O~~
____--__ __ ______
~
~
- - - - + - - - - - - - - - - -__r -__________~~________~r-~__r-~~
O.
O.
01
OUT
09
alS
01.
I
alS
c,
OUT
3
01.
a,
011
04
0,
0'
019
03
0'4
07
01.
07
GNO
4
INPUT
7
•
6
+
INPUT
.
.
THERMAL DATA
Rthj-amb
RthJ-case
Thermal resistance junction-ambient
Thermal resistance junction-pin (4)
.!:.2/!..:.1c.::.O------------I8lI~tm?l:alt
680
max
max
100
70
-------------
TDA2822M
STEREO APPLICATION
Fig. 1 - Test circuit
INn-__
(LJ
~
______
~~
__
~
Rl
10KJl
Cl
l00,UFI
INO---~------~~--~
(R)
RZ
10Kn
Fig. 2 - P.C. board and component layout of the circuit of Fig. 1 (1: 1 scale)
Vo( L) n---+---~
Vs
Vo (R ) 0----f+-,,,,,a
GN 0 n---.p.:.~h'
GNO
,G++-D IN (LJ
,G++-----O IN (R)
GNO
C5_0185
------------ ~ ~~I~m&'t~©~ ____________
-=3:...:/1:.:;0
681
TDA2822M
ELECTRICAL CHARACTERISTICS (Vs = 6V,
Tamb
= 2SoC, unless otherwise specified)
Test Conditions
Parameter
Min.
ITY~. I I
Max.
Unit
15
V
STEREO (Test circuit of Fig. 1)
Vs
Supply voltage
Vo
Quiescent output voltage
1.8
V. = 3V
Id
Quiescent drain current
Ib
Input bias current
Po
Output power (each channel)
(f = 1KHz, d = 10%)
Distortion
(f = 1KHz)
Gv
Closed loop voltage gain
t.G v
Chan nel balance
RI
~nput
eN
Total input noise
resistance
V
1.2
V
6
RL = 320
d
2.7
Vs
V.
V.
Vs
Vs
=
=
=
=
=
9V
6V
4.5V
3V
2V
90
15
mA
100
nA
300
120
60
20
5
mW
RL = 160
V. = 6V
170
220
mW
RL = 80
V. = 9V
Vs = 6V
300
1000
380
mW
RL = 40
Vs = 6V
V. = 4.5V
Vs = 3V
650
320
110
mW
RL = 320
Po = 40mW
0.2
%
RL = 160
Po = 75mW
0.2
%
RL = 8n
Po = 150mW
0.2
%
450
f = 1KHz
36
f = 1KHz
39
100
B = Curve A
= 100Hz
Supply voltage rejection
f
C•
Channel separation
f -= 1KHz
...;.:4/..;,.1_0_ _ _ _ _ _ _ _ _ _ _
dB
±1
dB
2
p.V
B = 22Hz to KHz
SVR
41
KO
Rs = 10KO
682
9
Cl = C2 = 100p.F
~ !~~m?w.~J!
2.5
24
30
dB
50
dB
------------
TDA2822M
BRIDGE APPLICATION
Fig. 3 - Test circuit
IN (}---.---'+---I
8
CI
I
RL
C4
O.1~F
IO"F
-+
4.7 n
'--_ _ _ _ _-¥-5
C5
czI O.I~F
4
"OnF
..L.!
s_ 612111
Fig. 4 - P.C. board and components layout of the circuit of Fig. 3 (1 : 1 scale)
C 5-0250
GND
IN
~"rn"
0
o
CI
Rl_5054
G-'I5O
II
II
'B
(mA I
II
p.
(W I
~'L::~III
.;roGr
40
17
Fig. 7 - Output power vs.
supply voltage (THD= 10%,
f = 1 KHz Stereo)
G-.'"
VA "O.5V RMS
III
-I--
T~~O
'0
Rl"S1l.
I
0.'
J
20
0.6
16
10'
'tis (V)
10'
10'
:::~
"slY)
f(H1:)
Fig. 9
Distortion
output power (Stereo)
Fig. 8
Distortion vs.
output power (Stereo) .
./
VV
0.2
10
'" 7
V
0.4
vs.
Fig. 10 - Output power vs.
supply voltage (Bridge)
G-"5-4
(~.l~_+__I+-+_+_-+_+--+---i
I
p.
(W I
I =1KHz
~ :sl:~~ -f-_+__+-+_-+--+
d=10·'.
RL",8A
I I
"
9V
J
II
O. I
I--I-+-+H-t--+-..f..-I--I-i--l-f.-:-J
./
200
600
400
0.2
800 Po(mW)
Fig. 11 - Distortion vs.
output power (Bridge)
0.6
Fig. 12
Total power
dissipation vs. output power
(Bridge)
(WI ~l--f-H_+_+-+--+-+__J.-+__j
RV,,321l.
"lKHz,~l--H_+
0.' I--+-+-+-f-H f
0.' hhl--l-l-l-J.-J.-t--t-V-A---1---l
0.2
0.4
0.6
0.8
V
f7
Po(W)
...( r-r-r-.......,.......,--r--r---,----,-~~!....,
I.' ~l--l--HHi--1i--1--+__J.__J.-+J..__j
V
1/
Fig. 13 - Total power dissipation vs. output power
(Bridge)
P,.
I
(W I
II
I--
V
• J
0.6
1--.....+-~J'.-+-+-v.-.J.L9V-I--I-+-+-+-l
o. 6
0.4
7
o. 4
6V
0.21--I-hl--l-l-l-J.-J.-J.-t--+--l
0.'
1.5
Po {WI
I
"s·9V
R L",lS1l.
f
~
1-1-
1KHz
1
o. 2
I
0.5
1.5
685
TDA2822M
Fig. 15 - Total power dis·
sipation VS. output power
(Bridge)
Fig. 14 - Total power dis·
sipation VS. output power
(Bridge)
'"'.
I
1-'1'
I
(W I
6-5151
Pt.I
I
L,...I---"
Y._6V
I-'"'"
1......
0.'
o.
o.
"'
1/
0.6
I- ~5V
RL -8A
flO 1KHz
--
,
--
0.4
II
II
""
JV
~l;,;:~
I
0.' 1'/
0.4
0 .•
1.2
1.6
Vs=4.5V
1--'
V
0.'
,
0.4
1
(W I
I
0.2
Po(W)
0.4
0.6
0.8
1
Po(W)
Fig, 16 - Typical application in portable players
.3V
32116.n
HEADPHONE
INo-~.---------~6~--~.
(R)
10~FI
4
5-6132/1
...;,;8/'-'1_0_ _ _ _ _ _ _ _ _ _ _
686
~ !~t~m?lt~~
-------------
TDA2822M
Fig. 17 - Application circuit for portable radio receivers
474
220",F
I
1{ED
680n
41Kn
TEA 1330
veo
STOP
41Kn
22K,{l
3.9Kn
l00,..FI
Fig. 18 - Portable radio cassette players
TYPE
SUPPLY VOLTAGE
TDA 7220
TDA 7211A
1.5V to
1.2V to
TEA 1330
TDA 7282
3V to l5V
1.5V to 6V
TDA2822M
1.BV to l5V
TYPE
SUPPLY VOLTAGE
6V
6V
S_6I:J0I2
Fig. 19 - Portable stereo radios
TDA 7220
TDA 7211A
1.5V to
1.2V to
TEA 1330
3V
TDA2822M
1.BV to l5V
6V
6V
to 15V
------------ ""I.IiIID©.~~ ---------~::..;;.:.
~SGS--
9/10
687
TDA2822M
Fig. 20 Low cost application for portable players (using only one 100llF output capacitor)
IN~
IR)
IOKn
IOO,..F
I
4
5-6192
Fig. 21 - 3V Stereo cassette player with motor speed control
+3V
1DOA
~lO::./.:..lO~_ _ _ _ _ _ _ _ _ _ _ ~ !~m~r~19lt
688
-------------
TDA2824S
DUAL POWER AMPLIFIER
• SUPPLY VOLTAGE DOWN TO 3V
• HIGH SVR
•
LOW CROSSOVER DISTORTION
•
LOW QUIESCENT CURRENT
SIP. 9
• BRIDGE OR STEREO CONFIGURATION
The TDA2824S is a monolithic integrated circuit
assembled in single line 9 pins package (SIP. 9),
intended for use as dual audio power amplifier
in portable radios and TV sets.
ORDERING NUMBER: TDA2824S
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current
Total power dissipation at Tamb = 60°C
at Tease = 70°C
Storage and junction temperature
16
1.5
1.3
8
-40 to 150
TYPICAL APPLICATION CIRCUIT (Stereo)
. - -__-() +6Y
INO--~~----~r--;
III
~
Cl
~.7"'F:r
TDA2824S
IND-~------~~--~
~.7!l.
cs
(Rl
O'l"'F
R3
lOOO,.,F
RZ
10K!l.
6
June 1988
1/6
689
TDA2824S
CONNECTION DIAGRAM
(Top view)
9
OUT (2)
8
0
7
OUT (1)
6
GNO
5
INPUT-(11
4
SVR
3
INPUT+(1)
n:
INPUT + (21
INPUT - (2 )
~-9531
SCHEMATIC DIAGRAM
. out
01
.4
0,
a,
a,
a1
a18
01
.~-~0-L
__________-L______-+~__~______~~~__L-+-____~__~-+______-+__________~
INPUT
,.
,
+
INPUT
THERMAL DATA
Rthi-amb
Rthi-PlnS
Thermal resistance junction-ambient
Thermal resistance junction-pins
2 /..::.
6 ___________
::.1.
690
~ 1~~'H~Jj
max
max
70
10
------------
,
TDA2824S
ELECTRICAL CHARACTERISTICS
(v. =
Paramatar
6V, Tamb = 25°C, unless otherwise specified)
I I I I
Test Conditions
Min.
Typ.
Max.
Unit
15
V
STEREO (Test circuit of Fig. 1)
V.
Supply voltage
Vc
Quiescent output voltage
Id
Quiescent drain current
Ib
Input bias current
Po
Output power
(each channel)
d = 10%
Vs = 9V
Vs = 6V
Vs = 4.5V
Closed loop voltage gain
f
=
RI
I nput resistance
f
=
eN
Total input noise
Gv
3
V.
Vs
= 9V
= 6V
4
2.7
6
Rg
=
Supply voltage rejection
f
CS
Channel separation
Rg
12
mA
100
nA
1.3
0.45
1.7
0.65
0.32
W
W
W
1KHz
36
39
1KHz
100
=
f = 1 KHz
RL = 4n
RL = 4n
RL = 4n
B
=
22Hz to 22KHz
Kn
2.5
p.V
40
=
f
10Kn
dB
2
100Hz
=
41
10Kn
Curve A
SVR
V
V
1KHz
50
dB
50
dB
BRIDGE (Test circuit of Fig. 3)
Vs
Supply voltage
Id
Quiescent drain current
RL
=
Vos
Output offset voltage
RL
= an
Ib
Input bias current
Po
Output power
3
~
d
Distortion
f
=
1KHz;
Gv
Closed loop voltage gain
f
=
1KHz
RI
Input resistance
f
=
1KHz
eN
Total input noise
Rg
SVR
Supply voltage rejection
f = 1KHz
RL = an
RL = an
RL = 4n
d = 10%
Vs = 9V
Vs = 6V
Vs = 4.5V
f
=
=
RL
= an;
Po
2.5
0.9
= 0.5W
15
6
12
mA
10
60
mV
100
nA
3.2
1.35
1
W
W
W
0.2
%
39
dB
Kn
100
B
=
22Hz to 22KHz
V
3
p.V
10Kn
Curve A
100Hz
---------------------------~~~I~~~~~
2.5
4a
60
dB
________________________~3/6
691
TDA2824S
Fig. 1 - Test circuit (STEREO)
INo-~~---~~-4
( LI
IN o-~_---~~-1f+".
(RI
Fig. 2 -
p.e. board and components layout of the circuit of Fig.
ex:
o
5
~
+
...J
........
66
Cl
0::
...J
~ 1: z
~4/~6________________________ ~~~1;~~~~
692
1 (1: 1 scale)
_________________________
TDA2824S
Fig. 3 - Test circuit (BRIDGE)
::r::
CJ
10"F
INo----..---'+~_t·
RL
Fig. 4 - P.C. board and components layout of the circuit of the Fig. 3 (1: 1 scale)
0
+
..J
cr
Z
l?
o
..J
cr ~ z
~ SGS-tHOMSON
5/6
- - - - - - - - - - - - - - ""11..
~g©rnl@"n.rn©1i'OO@i!Jg©$ -------------=-::;
693
TDA2824S
Fig. 5 - Output power vs.
supply voltage (Stereo)
6·&1"'5
p.
IWI
.
Fig. 6 - Output power vs.
supply voltage (Bridge)
-........
Fig. 7
Distortion
output power (Bridge)
,..
, I
d
I
IWI
d.'O.,.
hlKHz
Al_all
fslKHz
..
Al·ln
d ......
t • 1KHz
J
J /
/./
.... V
~ ?-
J
V
V
.....
10
6-1146
hlKHz
- --r-
ov
'0I--+-+-+--+-I---r-1~
30f---+-+-+--+-f----r-1~
11
II
? I-"
o.
..
'0f---+-+-+--+-t---r-1-~
V
10
f---+-+-+--+-f----r-l-~
10
Fig. 11 - Quiescent current
vs. supply voltage
Id
'm'
50
.
.0
30
'0
10
10
lis (V)
1(Hz)
6-111••
..•
~~~:~
10'
Fig. 13 - Total power dis.
sipation vs. output power
(Bridge)
I
P"I
,WI
IWI
--
II IIIIII
-1~~:;';'1111
~~~2S:JJrrs
Fig. 12 - Total power dissipation vs. output power
(Stereo)
-
I
I
Rl-an.
'.IKHz
I
"s'. 1--
i--"
YsdV
, v'"
.... i""'"
16
V.
(Y)
'0
""6/_6_ _ _ _ _ _ _ _ _ _ _ _
694
12
Plot
I
1/
Fig. 10 - Supply voltage
rejection vs. frequency
(Stereo)
G-ttO
dB
r
ca=22pF t---+-I----j
50 1--+--:=JIr-...'--'''''''-+-I---r-1~
4.5\1
I.---
,.."
:~=:==:=~~:·t:~~gf~~-~·-·sf----r-1~
Aldlll
~
"SVI
dB
d
'"to
12
Fig. 9 - Supply voltage rejection vs. supply voltage
(Stereo)
,
Fig. 8
Distortion vs.
output power (Bridge)
I
IV
R l -Ill
/
RL·4n/
vs.
6·...1
I.'
/
'S'r"'
Q.
3
Po (WI
.... v
1.
~ ~~tmg'19J1-------------
..~
.,L SGS-THOMSON
~o©oo@rn[L[~©'[Joo@~o©~
TDA3410
i
I
DUAL LOW NOISE TAPE PREAMPLIFIER WITH AUTOREVERSE
The TDA3410 is a dual preamplifier with tape
auto reverse facility for the amplification of low
level signals in applications requiring very low
noise performance, as stereo cassette players.
Each channel consists of two independent amplifiers. The first has a fixed gain of 30dB while
the second one is an operational amplifier optimized for high quality audio application.
- Single supply operation
- Wide supply range
SVR = 120dB
Large output voltage swing
Tape autoreverse facility
Short circuit protection
The TDA3410 is a monolithic integrated circuit
in a 16-lead dual in-line plastic package and its
main features are:
DIP-16 PIBSlic '"
(0.4)
Very low noise
- High gain
- Low distortion
ORDERING NUMBER: TDA3410
ABSOLUTE MAXIMUM RATINGS
36
600
-40 to 150
Supply voltage
Total power dissipation at Tamb = 60"C
Storage and junction temperature
V
mW
°C
Stereo preamplifier for auto reverse cassette players
C10·
r---IO"A,lF
~.
O.3mV
---r-.
.
~;100A.lF
loon
C.:-.. :--.-0.,4.4V
.
.....
O.3mV
R
14.4V
Rl
R2
1 MA
50KA
C'!l!,uF
June 1988
lAut.
s- 405012
* Mylar
or poly carbonate capacitors
1/7
695
TDA3410
CONNECTION DIAGRAM (top view)
"-
.
OUTPUT A
16
NON INVERT.
INPUT A
~
,V s
15
OUTPUT B
INVERT.
INPUT A
14
NON INVERT.
INPUT
B
VOLTAGE REF.
13
INVERT.
INPUT B
OUTPUT
12
THRESHOLD
INPUT
11
OUTPUT
INPUT
10
INPUT
INPUT
GND
5-3241
BLOCK DIAGRAM
r---
l
>VS .
~
_______
5
3
6'
1 IL~OUTPUT
~Ch.A
L-""OUTPUT
.-----v C h. B
9
IL... _ _
12
AUTOREVER5E
"
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
~2~/7________________________ ~!~1~~~'~~~~
696
max
150
°C/W
__________________________
TDA3410
TEST CIRCUIT (Flat Gain - Gv= 60 dB)
.v.
"',
"',
CI3 *
_
RL=20Kf.
4 c>-----OYref
C14*
RL=20Kll
IOOKA
R6
• Y.o---ILM=A:::J-;CH>---[5=O=Kll}-'
CI"'F
L _____
1
~I
I
R 5 =R6=4 7KA(Y.= 14-4 V)
R 5=R6=15 K!l(V.= 30Y)
I
Autoreverse '
1
Switch
Shielded Test - Box
!
5-405'3/1
• Mylar or poly carbonate capacitors.
ELECTRICAL CHARACTERISTICS (Tarnb = 25°C, Vs= 14.4V, Gy= 60 dB, refer to the test
circuit, unless otherwise specified)
Test conditions
Parameter
Is
Supply current
Vs= 8V to 30V
10
Output current (pins 1-15)
Source
Min.
Typ.
Max.
Unit
10
rnA
10
mA
1
rnA
60
dB
80
K.I1
50
.n
0.05
0.05
%
%
Vs= 8V to30V
Sink
Gv
Closed loop gain
f = 20 Hz to 20 KHz
RI
I nput resistance
f = 1 KHz
Ro
Output resistance (pins 1-15)
f = 1 KHz
THO
Total harmonic distortion
Vo= 300mV
__________________________
50
f = 1 KHz
f = 10 KHz
~I~~~&'~~
______________________
~3~/7
697
TDA3410
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Vo
Output voltage swing (pins 1-15)
Vo
en
SIN
Test conditions
Min.
Typ.
Max.
Unit
Peak to Peak
Vs= 14.4V
Vs= 30V
12
28
.V
V
Output voltage (pins 1-15)
d = 0.5%
f = 1 KHz
Vs= 14.4V
Vs= 30V
4
8
V rms
V rms
Total input noise (0)
Rg= 50n
R g=600n
Rg= 5Kn
Signal to noise ratio (0)
0.25
0.4
1.3
0.6
/LV
/LV
/LV
V ln = 0.3 mV
R g=600n
57
dB
V ln = 1 mV
Rg= 0
73
dB
CS
Channel separation
f = 1 KHz
60
dB
CT{OOO)
Cross-talk (i:lifferential input)
f = 1 KHz
80
dB
SVR
.Supply voltage rejection (00)
f = 1 KHz
120
dB
SVR (00)
Of reference voltage (Pin 4)
f = 1 KHz
Rg= 600n
100
dB
V ref
Reference voltage (pin 4)
55
mV
R ref
Ref. voltage output resistance
(pin 4)
100
n
t.V ref
Voltage temperature
coefficient
10
/LVfDC
~
(0)
(00)
(000)
The weighting filter used for the noise measurement has a curve A frequency response.
Referred to the input.
Between a disabled input and an input ON .
7_ _ _ _ _ _ _ _ _ _ _ _
..:;4/c:..
698
Rg= 600n
/iii. !~I~m&=~ -------------
TDA3410
ELECTRICAL CHARACTERISTICS (Refer test circuit, Vs= 30V)
AMPLIFIER N° 1
Test conditions
Parameter
Gy
Gain (pins 6 to 5)
d
Distortion
Va= 300mV
en
Total input noise (0)
Za
Output impedance (pin 5)
10
Output current (pin 5)
V5
DC output voltage (pin 5)
Min.
Typ.
Max.
Unit
29
30
30.5
dB
0.05
0.05
%
Rg =600n
0.4
p.V
f = 1 KHz
100
n
1
rnA
f = 1 KHz
f = 10 KHz
1.3
Vs=10V
2
2.7
V
AMPLIFIER N° 2
Gy
Open loop voltage gain (pins2to1)
100
dB
18
Input bias current
0.2
p.A
Vas
Input offset voltage
2
mV
los
I nput offset cu rrent
0.05
p.A
BW
Small signal bandwidth
G y = 30 dB
150
KHz
en
Total input noise (0)
Rg=600n
2
p.V
RI
Input impedance
f = 1 KHz (open loop)
500
Kn
150
AUTOREVERSE
Pin
(0)
V 12
< 2V
V 12
> 4.SV
6-10
OFF
ON
7- 9
ON
OFF
The weighting filter used for the noise measurement has a curve A frequency response.
-----~------- ~ !~m~
____________
=:..5/7
699
TDA3410
Fig. 1 - Total input noise vs.
source resistance (curve A)
Fig. 3 - Total harmonic
distortion vs. output voltage
Fig. 2 - Total input noise
vs. source resistance (BW=
22 Hz to 22 KHz)
~'~~r!~~~~~I1~~~~
!
("'V)6~
aw_Cl.lrvfio
,"
I
c-0". _
I
'"
i
10'
",
Rg(/I.)
10
10'
.. ""
•
<;8
Rg(O)
_
O.OI'--O---LL"'.:"".~-7....J...7'-:'.-'-!.-'L----:-....J...,~,~
•
0.1
Fig. 4 - Very low noise stereo preamplifier for car cassette players
(with Gap Loss Correction and autoreverse function)
1
10
YoCy)
Fig. 5 ..: Frequency response
('B,r-rnl111TrTTmrnrTTTITTTlT
IlIlri-¥i'ffim
11111
40
it-+tJf
r--t+t-ttt1lt---+1
HittirtlII---t-+. tH1ttI--+t+ttHlt-+H Hlt!!
lI-- _11+++HH-+++++tIIIHtHlt-++-t-ll+lll
20~~~L-~llliill-~LUillL....J...~~
10
10 2
103
10'
f (Hz)
14.4V Rl
1M"
1
Autoreverse
*
Mylar or polycarbOnate capacitors
S- ,o49/2
6/7
700
~ !~~~m~:t
------------
TDA3410
Fig. 6 - P.C. board and component lay-out (1:1 scale) for the circuit of fig. 4
OUTPUT
OUTPUT
LEFT .Vs
INPUT
RIGHT
INPUT
(LEFT CHAN.J (RIGHT CHANJ
AUTOREVERSE
Fig. 7 - Stereo preamplifier for car cassette players, with low value
capacitors (Autoreverse function)
Fig. 8 - Frequency response
,
(dB
O.3mV
0
G-
,
111111
111111
111111
EQ.•'I2O~
0
0
0
el3 *
lSnF
I-
0
30
O.3mV
0
10
".4\1
10'
'(Hz)
Rl
lMA
1
AU1
,
*
Mylar or poly carbonate capacitms
-------------- ~ ~~m~~JI
7/7
701
TDA3420
DUAL VERY LOW NOISE PREAMPLIFIER
The TDA 3420 is a dual preamplifier for applications requiring very low noise performance, as
stereo cassette players and quality audio systems.
Each channel consists of two independent amplifiers.
The first one has a fixed gain while the second
one is an operational amplifier for audio application.
The TDA 3420 is available in two packages:
16-lead dual in-line plastic and 16 lead micropackage.
Its main features are:
- Very low noise
- High gain
- Low distortiofl
- Single supply operation
- Large output voltage swing
- Short circuit protection
DIP-16 Plastic
(0.4)
SO-16J
ORDERING NUMBER: TDA3420 (DIP-16)
TDA3420D (50-16)
BLOCK DIAGRAM(Pin numbers refer to the DIP)
r- - - - - -'
I
-:O~:O5
- - - - - -,
I
I
OUTPUT( L)
I
I
I
8~NO
I
I
OUTPUT(R)
June 1988
1/5
703
TDA3420
ABSOLUTE MAXIMUM RATINGS
Vs
Ptot
Tj , Tstg'
Supply voltage
Total power dissipation at Tamb = 700C Dip-16
SO-16
Storage and junction temperature
20
550
400
-40 to 150
V
mW
mW
°C
CONNECTION DIAGRAMS
'-'
OUTPUT A
.v.
16
NON INVERT.
INPUT A
15
OUTPUT B
INVERT.
INPUT A
14
NON INVERT.
INPUT
B
N.C.
13
INVERT.
LNPUTB
12
OUTPUT
INPUT
6
INPUT
16
NON INVERT.
:NPUT A
15
OUTPUT B
GNO
14
NON INVERT.
INPUT
B
INVERT.
INPUT A
13
GNO
INVERT.
INPUT B
OUTPUT
12
11
OUTPUT
INPUT
INPUT
10
INPUT
INPUT
GND
OUTPUT
10
INPUT
5-5233
5-5231,
50-16
DIP
THERMAL DATA
Rth J-amb
•
.Vs
INPUT
N.C.
11
GND
~
OUTPUT A
DIP
Thermal resistance junction-ambient
max
150°C/W
SO-16
200°C/W(*)
The thermal resistance is measured with the device mounted on a ceramic substrate (25 x 16 x 0.6 mml.
________________________
~2/~5
704
~!~;~~~~
__________________________
TDA3420
Fig. 1 - Test circuit
INPU~~
10 F
INPU~~
10JJF
(L)~
(R)~
5- S 236
Note: Pin numbers refer to DIP.
Fig.2 - Test circuit without input capacitors
INPUT( Ll
INPUT(R)
Note: Pin numbers refer to the DIP.
------------- ~ ~~tmg~l9~ ____________~3/5
705
TDA3420
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, Vs= 14.4V, Gv= 60 dB refer to the test
circuit of fig. 1, unless otherwise specified)
Parameter
Test conditions
Is
Supply current
Vs=8V to 20V
10
Output current
Source
Min.
Typ.
Max.
Unit
8
mA
10
mA
1
mA
Vs= 8V to 20V
Sink
Gv
Gain
Ri
.1 nput resistance
Ro
Output resistance
THD
Total harmonic distortion
without noise
60
d8·
100
Kn
50
n
f = 1 KHz
0.05
%
f=10KHz
0.05
%
12
V
f = 1 KHz
Vo= 300 mV
50
Va
Peak to peak output
voltage
f = 40 Hz to 15 KHz
en
Total input noise (0)
Rs= 50 n
Rs= 600 n
Rs= 5 Kn
SIN
(0)
Signal to noise ratio
(00 )
0.25
0.4
1.3
0.7
jJ.V
jJ.V
jJ.V
Vin= 0.3 mV
Vin= 1 mV
Rs= 600 n
Rs= 0
57
V 1n = 0.3 mV
Vin= 1 mV
Rs= 600 n
Rs= 0
55
71
dB
60
dB
110
dB
CS
Channel separation
f = 1 KHz
SVR
Supply voltage
rejection
f = 1 KHz
Rs= 600 n
f = 1 KHz
f = 10 KHz
dB
73
(000 )
AMPLIFIER N° 1
Gv
Gain (pin 6 to pin 5)
d
Distortion
Vo= 300 mV
en
Total input noise (0)
Zo
Output impedance (pin 5)
10
Output current (pin 5)
V5
DC output voltage (pin 5)
27.5
28.5
29
dB
0.05
0.05
%
Rs= 600n
0.4
jJ.V
f = 1 KHz
100
n
1
mA
Test circuit fig. 2
2.8
V
Test circuit fig. 1
~4/~5
________________________
706
~~~~~~~~~
1.0
1.5
__________________________
TDA3420
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test conditions
AMPLIFIER N° 2
Gv
Open loop voltage gain
100
dB
18
Input bias current
0.2
).LA
Vos
I nput offset voltage
2
mV
105
I nput offset current
50
nA
en
Total input noise (0)
Rs= 600n
2
).LV
Rj
I nput impedance
f = 1 KHz (open loop)
500
Kn
150
Weighting filter: curve A.
Weighting filter: Dolby CC I R/ ARM.
(000) Referred to the input.
(0)
(00)
Fig.3 - Total input noise vs.
source resistance (curve A)
Fig. 5 - Total harmonic distortion vs. output voltage
G- ,iOt
d
("
" f - - 1--j--;;K~fz '
-~
-f--
Rl',20IUl
I
.
,
,
'I
--:
i! I !
,
I'II
1-'
' I
I
I
0.'
.
0.0
.0
Rg (n)
>0'
d
('/.
,
~~t~
.. ~
++
:
iii 1III
i
I
I;t~~
Fig. 8 - Frequency response
of the circuit of fig. 10
1>"4710
.-
!
.
:
0 .•
Fig. 7 - Distortion vs. input
level (test circuit of fig. 1)
Fig. 6 - Output voltage vs.
frequency
I
I
! 'i
!
---
......
.
.1-+tt1~
H-----"
Vs=14.4V _.
IIIII
(dB)
,~tdOOHz
,
I
,
.1 I
!
,
ill
i
I
o.
+-
'f-c::=±::=:
-l------
00
eo I-'-i :+HI+--i~-i.J+lljl-j...Lll.!ill--+~fjjji,
f-cH+H++· :
-Ty~20·~'-+W~JI.
--l
I
.
o.
--------------
.~
;
f-j-~i+Hfj-·"
-"ki-ft+tf-+-I+HHIt--+-I+tmII
JO
H·+++l+lfh+thtr--+-++H+llf-
~rrt
. ,
:
i
70 f-t+1"'+!1I--C++H+lI--i.++tIt+II--t-t-H~
60
iii
I
i
IT~
03
~ ~~~~m~1T~I~~ce'
Vj
! ;'.
(mV)
____________
5/ 5
-=..<..::C
707
TDA7211A
LOW VOLTAGE FM FRONT END
•
player applications where a very low supply
voltage is used and compactness is an important
design consideration. It contains an RF amplifier,
balanced mixer, one-pin local oscillator and a
varicap diode for AFC. Very few external components are required. Mounted in a Minidip or
50-8 package, the TDA7211A is particularly
suitable for slimline cassette-type radios.
LOW OSCILLATOR RADIATION
• OPERATING
TO 6V
SUPPLY
VOLTAGE:
1.3V
• EXCELLENT GAIN STABILITY VS. SUPPLY VOLTAGE
• HIGH SIGNAL HANDLING
•
FEW EXTERNAL COMPONENTS
•
BUILT-IN VARICAP FOR AFC
• MINIDIP PACKAGE PERMITS RATIONAL
LAYOUT AND LOW PROFILE
• COVERS JAPANESE, US AND EUROPEAN
BANDS
SO-SJ
Minidip Plastic
ORDERING NUMBER: TDA7211A (Minidip)
TDA7211 D (50-SJ)
The TDA7211A is a monolithic FM turner
suitable for portable radio and radio / cassette
BLOCK DIAGRAM
f+Vs
BIAS
2
RF
IN
'"
3
'--
1
RF
PREAMPLI FIER
8
MIXER
5
'"
IF
OUT
OSCILLATOR
~~
4
-
I..
June 1988
7
AFC
6
5-6738
1/7
709
TDA7211A
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation at Tamb < 70 D C
Operating temperature
Storage and junction temperature
7
400
-20 to 85
-40 to 150
V
mW
DC
DC
CONNECTION DIAGRAM
(Top view)
8~
SUPPLY
VOLTAGE
7
~
VARICAP
(CATHODE)
3
6
~ OSCILLATOR
J,
5~
RF INPUT
1
INPUT
BIAS
2
RF TUNING
GND
I
IF OUTPUT
5-673<
SCHEMATIC DIAGRAM
osc.
OUT
3
5
6
7
01
~2/~7________________________ ~~~I;~'~
710
--------------------------
TDA7211A
THERMAL DATA
Thermal resistance junction-ambient
200
max
ELECTRICAL CHARACTERISTICS (V s = 3V, test circuit of fig. 1, T amb = 25°C, unless otherwise specified)
Parameter
Test conditions
Vs
Supply voltage
Vose
Local oscillator voltage
Is
Supply current
Vs = 1.5 to 4.5V
CAFC
AFC diode capacitance
V AFC = lV
K(*)
AFC diode variation
VAFC= 1 to 3V
Gc (**)
Conversion gain
Vs= 3V
f = 83 MHz
f = 98 MHz
Vs= 1.6V
f = 83 MHz
f = 98 MHz
VSTP
(0) K=
Typ.
Max.
Unit
1.3
3
6
V
330
mVrms
4.5
mA
2
3
4
(00) Ri = 750;
pF
0.24
Local oscillator stop
voltage
C (lV) -C (3V)
C (3V)
Min.
25
25
34
34
dB
32
32
dB
1.2
V
RL = 3000
TYPICAL DC VOLTAGES (test circuit)
Pin
1
2
3
4
5
6
7
8
(V)
2.3
3
3
0
3
2.9
0
3
------------- ;.:;z
I~m~!&~
____________
=-'-3/7
711
TDA7211A
Fig. 1 - Test circuit
'---1o--t----{) OUT
RF
TDA7211 A
IN
~-_II~~~-_c~--._---__oAFC
I
IL ______ _
s-
613511
BPFl = TAIYO YUDEN - Bl0861
Cv = C2. C3. Cll, C12 = 20 + 20 pF
L 1 = R F coil - 5 turns - 0.6 mm/4 mm.
L2 = OSC. coil - 4 turns - 0.6 mm/4 mm.
Fig. 2 - P.C. board and components layout of the test circuit (1: 1 scale)
C5-0210
GND
IN
~4/~7________________________ ~~~~~~~~
712
_________________________
TDA7211A
APPLICATION INFORMATION
Fig. 3 - Typical application for portable AM/FM radio
Fig. 4 -
p.e. board and components layout of the circuit of fig. 3 (1: 1 scale)
CS-0209/1
713
TDA7211A
APPLICATION INFORMATION (continued)
PARTS LIST (Radioreceiver of fig. 3)
Code number
Value
Description
PVC 1
FM 20pF x 2
AM 140/82 pF
rJ> 4mm.-5T# 0.6mm.
tJ> 4 mm. -4 T #0.6 mm.
600I'H PRIMARY
SEC. - 7 TURNS
221'H INDUCTOR
AA 119
TAIYO YUDEN BPF10861K
TOKO FMl - 154 AN -7A5965R
SFE 10.7 MA
TOKO CF2 455C
TOKO AM2 RLC - 4A7524EK
TOKO RWO - 6A6574N
TOKO KACS - K586HM
TOKO POLYVARICON
QT 22124
FM RF COIL
FM OSC. COIL
AM ANT. COIL with ferrite
bar J/> 10 mm. x 80 mm.
TOKO 144LY - 220K
GE DIODE
FM BAND PASS FILTER
FM 1FT
CERAMIC FILTER
AM 1FT WITH CERAMIC FILTER
AMDET.COIL
AM OSC. COIL
FM DIS.COIL
Ll
L2
L3
L4
Dl
Fl
F2
F3
F4
F5
F6
F7
Typical performance of the radio receiver of fig. 3
Parameter
WAVEBANDS
SENSITIVITY
AUDIO SIGNAL OUT
Test conditions
AMPLITUDE MODULATION
REJECTION
TWEET
FM
87 to 109 MHz
523 to 1620 KHz
FM
SIN = 26 dB
lit = ± 22.5 KHz
1.81'V
21'V
AM
SIN = 20 dB
m=0.3
400I'V
400l'V
FM
lit = ± 22.5 KHz
70mV
55mV
AM
VI=lmV/m
m =0.3
80mV
75mV
lit = ± 22.5 KHz
0.35%
0.5%
lit = 75 KHz
0.7%
0.75%
0.8%
FM
Vi = 1 mV
AM
5mV/m
100 mV/m
m =0.3
0.8%
m =0.8
2%
1.9%
FM
VI= 1 mV
lit = ± 22.5 KHz
50dB
5CdB
AM
Vj=lmV/m
m = 0.3
33 dB
32dB
FM
VI = 1 mV
lit = 22.5 KHz m = 0.3
32 dB
31 dB
1%
0.2%
1%
0.2%
13.5 mA
12.5mA
2nd H.
3rd H.
f = 911 KHz
f = 1370 KHz
QUIESCENT CURRENT
~6/_7________________________ ~~~~1n~~~
714
V s =1.6V
AM
DISTORTION (fm= 1 KHz)
SIGNAL TO NOISE
(f m = 1 KHz)
Vs= 3V
__________________________
TDA7211A
APPLICATION INFORMATION (continued)
Inversion of "S" shaped curve in quadrature discriminators
simple circuit solution to perform the inversion.
The traditional diagram is shown in figure 6 for
comparision.
This solution may be used with all the 5GS radio
circuits (TDA7220, TDA1220B, etc.) with performance equal to that achieved through the
conventional circuitry.
I n the diagram shown, the inversion of the curve
is obtained through the replacement of the inductive reactance (normally 22 IlH) with a capacitance (12 pF) and the recovery of the d.c.
voltages through L3.
L3, wh ich is forced to resonance and strongly
smoothed by R 1, also performs the function of
resistive load across the collector of the output
transistor in I F limiter.
The described circuit doesn't modify the ease
of calibration of the quadrature discriminators,
makes the amplitude modulation rejection (AM R)
more continuous and significantly reduces the
harmonic radiation from the last limiter staqe.
In FM receivers, the frequency used for the
local oscillator is usually greater than the receiving frequency_
Anyway, in some cases it may be required to
work with a local oscillator showing a frequency
lower than the frequency of the received signal.
According to this choice, the "5" shaped curve of
the discriminator is therefore either positive or
negative (the output d.c. voltage either increases
or decreases as the input frequency increases) and
the varicap diode of the AFC will have to be referred either to ground or to a reference voltage.
The additional reference voltage may be circuitally unsuitable, besides increasing the costs.
In the case of circuits using the monolithic tuner
TDA7211 (internal varicap diode, with a side
already connected to ground) the things would
get still more complicated.
To overcome the problem, figure 5 shows a
Fig.6
Fig. 5
r ______ ,
r--- ---.,
r - -I
TOKO
~I
560
L ________
KACS K586HM
I
n
:i
TOMO
I
I-..J-_+_+__+~I__I__+__+
100 f_+__+_--f'~,,-+__+~I__I__+___I
K
Vs(V)
~8/~1~1_______________________ ~~i~~~~~~
724
: i
~- ~-I-l·~-+-t--f----l
I
'
__---,
,,+-: I-~i
\6
12
i -: .
,
I
-'-+-T
I
'-•• j...-j...-r
j....ol--- i-I-l-Ail-
IIPF--
\0
:::~tr::t~~7MHz
_+_-+.........
~..ct--H
300
lmY
-ri -I
,
(~~,
-
rt
'1j ..
-: I
I.'
Fig. 17 - Drain current vs.
supply voltage
~"'f_+__+__+__+_+__+~I__I__+__+
o
I.'
Vs(Y)
II
I
v.ev)
__________________________
:!! l>
'P "V
"V
0)
I
r-
~ ~
~
~
-
-I
0
z
»
3:
-...
"TI Z
3: ."
3 0
:;' ~
1NSg,
::;.
MURATA
DfilD.7MA
BPF
'"o·C.
+3V
1
2 0L2
:nmP:
22pF
10pF
~
C9
caT
cIa
SWI
'L~-----ji~:
1 1~n I hoo"nFf"" I
I~
allU»
I:,1
1
!
s::
l>
:::!
0
Z
J90jJFJ
:::c:
...
Ii!
I
SW2
I
~o
I
C:i7nF
~!
IIL4!Z~
~.
~
[R'4L
I
:ll~O.!!F
IAM~~
-'- J£WII
~/1Jo
Kll
ANTENNA
R2'
r--5-9580/1
tv
-..I
U1
I'"
-;;
....
g
~
~
TDA7220
APPLICATION INFORMATION (continued)
Typical performance of the radio receiver of fig. 18 (V. = 3V, RL = 3251)
Parameter
Test Conditions
Value
FM
87.5 to 108 MHz
AM
510 to 1620 KHz
WAVEBANDS
SENSITIVITY
DISTORTION
(fm = 1 KHz)
FM
SIN = 26 dB
M= 22.5 KHz
3jJ'v
AM
SIN = 6 dB
m = 0.3
2jJV
AM
SIN = 26 dB
m = 0.3
10jJV
M = 22.5 KHz
0.5%
FM
Po= 20mW
M = 75 KHz
1.8%
m = 0.8
1.1%
M = 22.5 KHz
60dB
m = 0.3
45dB
AM
Vi = 100jJV
Po= 20mW
FM
Vi = 100jJV
SIGNAL TO NOISE
(fm = 1 KHz)
Po = 20 mW
AM
VI= 1 mV
AMPLITUDE
MODULATION
REJECTION
FM
VI = 100jJV
M = 22.5 KHz
QUIESCENT CURRENT
SUPPL Y VOLTAGE RANGE
~lO~/~ll~_____________________ ~~~~~~l~~n
726
m = 0.3
40dB
16mA
1.6 to 3V
--------------------------
"
l>
co
r-
cfi°
I
o
mD
s:
"
s:
o
::I
22pF
7
L2
o
I
C9
C8T
~
I:R
ilii Ut
~i!
ei
~ o~
~
s: z
.....
2° PF
lOpF
"V
"V
~I
Z
."
o
:0
s:
:c
I»
l>
0"
o
Q.
-I
Z
+3V
c;-
J::
O
I
::I
....
;:j"
I
I
C
111~g
[
L4
~o
~.
IS
~z
4.0.
5-9583
....
-..J
I\)
-..J
............
-I
~
.....
N
N
o
TDA7230A
STEREO DECODER AND HEADPHONE AMPLIFIER
•
OPERATING SUPPLY VOLTAGE RANGE:
1.8 to 6V
•
•
•
LED DRIVING FOR STEREO INDICATION
STEREO/MONO SWITCH
ONLY OSCILLATOR FREQUENCY ADJUSTMENT NECESSARY
LOW DISTORTION AND LOW NOISE
VERY LOW POP ON/OFF NOISE
FEW EXTERNAL COMPONENTS
SOFT CLIPPING
•
•
•
•
The TDA 7230A is a monolithic integrated circuit
in 16 pin plastic package designed for stereo
decoder and headphone amplifier applications in
portable rad io.
D1P-16 Plastic
(0.4)
ORDER CODE: TDA 7230A
BLOCK DIAGRAM
16
June 1988
6
1/5
This is advanced information on a new product now in development or undergofng evaluation. Details are subject to change without notice.
729
TDA7230A
ABSOLUTE MAXIMUM RATINGS
Supply voltage
LED current
Peak output current
Total power dissipation at T amb = 700
9
8
200
1
e
V
mA
mA
W
CONNECTION DIAGRAM
Veo
16
LPFI
LED
15
STEREO IN
LPF2
14
ROUT
AUDIO
IN ILl
4
13
LOUT
GvGND
5
12
AUDIO
INIRI
+Vs
6-
"
SVR
10
AUDIO
OUT (Rl
9
+Vs
GND
AUDIO
OUT (Ll
8
5-9549
THERMAL DATA
Rth j-amb
Thermal resistance junction to ambient
________________________
_2~/5
730
~!~!;~g~~~
max
80
__________________________
TDA7230A
TEST CIRCUIT
0
5
3
9
veo
16
C8
6
IOO,uF
I-"'-~--jl~ OUT
In
2.2pF
~15
R6
L
RL
Q22~C7
TDA7230A
}JF ....
C9
I00}JF
680n
7
L 13
4
II
IOjJF
CIS
InF
CI4
I"'IOO------111oUT R
In.
RL
14
ClOJ:0.22J..1F
5-9550 /1
ELECTRICAL CHARACTERISTICS (Unless otherwise stated, Tamb = 25°C, Vs =3V, f= 1 KHz)
Parameter
Vs
Supply voltage
Is
Supply cu rrent
Test Conditions
Min.
Typ.
1.8
LEDon
Max.
Unit
6
V
9.5
mA
30
48
7
mW
mW
mW
AUDIO STEREO AMPLIFIER
Po
Output power
Vs= 3V,
Vs= 3V,
Vs = 1.8V,
d
Distortion
Po= 10mW, f = 1 KHz,
RL = 32n,
RL = 16n,
RL = 32n,
d= 10%
d = 10%
d= 10%
RL = 32n
27
45
6
0.2
1
%
731
TDA7230A
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Gy
Voltage gain
RI
I npu t resistance
Test Conditions
Min.
Typ.
Max.
Unit
28
30
32
dB
15
20
Cross talk
f = 1 KHz
SVR
SUpply voltage rejection
C14= 10,..F, Rg = 10 KO, f = 100 Hz
40
eN
Total input noise voltage
RG = 10 KO
Bandwidth: 22 Hz - 22 KHz
2
Rs =10KO
KO
40
dB
dB
5
,..V
STEREO DECODER
Ri
Input resistance
Ro
Output resistance
VI
Max. Input signal
(composite)
L+R=90%
fm = 1 KHz
P= 10%
THO=5%
Sc
Channel separation
L + R = 90 mVrms
fm = 1 KHz
d
Total harmonic distortion
(Out pin 13,pin 14)
Mono
Stereo
Voltage gain
Vi = 100 mVrms
-3
Channel balance
VI = 100 mVrms
-1
LED on
Pilot input
Gy
6
25
Captu re range
P = 10mVrms
SIN
Carrier leak
P = 10 mVrms
L + R = 90mVrms
SIN
Signal to noise
19 KHz
38 KHz
Vi = 100 mVrms
-25
-40
RG =6000
~~~5------------------------~~5I~~
732
5
KO
mVrms
35
0.4
0.5
LED off
Turn OFF from Turn ON
KO
200
VI = 100 mVrms
L + R = 90 mVrms
fm = 1 KHz
P = 10mVrms
LED Hysteresis
10
dB
1
1
%
+3
dB
0
+1
dB
8
11
mVrms
6
mVrms
3
mVrms
±3
%
-32
-48
dB
dB
82
dB
--------------------------
"TI-I
cC·
-<
. -g
~-
'n
Col>
Ci1 -g
o -g
l>r
.3:... n
"TI>
lN6g,
BPF
20~P:
L2
22pF
C9
lOp
~
II:
'"(It
+3V
CST
~S
SWI
1-~-___II_l~fl
-111
LJ
1
!
1 JPOfFJ
3:-1
~. (5
:!. 2
....
'"o·a.
I:
I
Iiiil_
I
I
1JlH
SW2
100
L4
liE
RI1 n560 I R12
11
16
TDA7230A
r----..J
Col
Col
U1
.....
U1
s... 95801 2
-I
~~
»
TDA7231
1.6W AUDIO AMPLIFIER
of supply voltage in portable radios, cassette
recorders and players, etc.
• OPERATING VOLTAGE 1.8 TO 15V
•
LOW QUIESCENT CURRENT
•
HIGH POWER CAPABILITY
•
LOW CROSSOVER DISTORTION
Powerdip
(4+ 4)
• SOFT CLIPPING
The TDA7231 is a monolithic integrated circuit
in 4+4 lead minidip package. It is intended for
use as class AB power amplifier with wide range
ORDERING NUMBER: TDA7231
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation at Tamb = 50°C
at T case = 70°C
Output peak current
Storage and junction temperature
16
1.25
4
1
-40 to 150
CONNECTION DIAGRAM
(Top view)
8
OUTPUT
7
GND
INPUT INPUT +
June 1988
4
5
1/4
735
TDA7231
Fig. 1 - Test and application circuit
~
s- 9196
Fig. 2 - P.C. board and components layout
~2/~4________________________ ~~~t~~~~~~
736
__________________________
TDA7231
THERMAL DATA
Rth j-amb
Rth joplns
Thermal resistance juction ambient
Thermal resistance junction-pins
ELECTRICAL CHARACTERISTICS (Vs = 6V,
Parameter
Vs
Supply voltage
Vo
Qu iescent out voltage
80
15
max
max
Tamb
= 25°C, unless
Test Conditions
otherwise specified)
Min.
Typ.
1.8
Vs =6V
2.7
Vs = 3V
1.2
Max.
Unit
15
V
V
Id
Quiescent drain current
3.6
Ib
Input bias current
100
nA
Po
Output power
d
Distortion
Gv
Closed loop voltage gain
Rln
Input resistance
eN
Total input noise
f =
RL
RL
RL
RL
RL
RL
1 KHz
= 80
= 40
= 80
= 40
= 40
= 80
1.8
1.6
0.4
0.7
110
70
W
W
W
W
mW
mW
Po '= 0.2W
f = 1 KHz
RL = 80
0.3
%
38
dB
f
= 1 KHz
100
B = Curve A
KO
2
p.V
B
Supply voltage rejection
mA
d = 10%
Vs = 12V
Vs = 9V
Vs =.6V
Vs = 6V
Vs = 3V
Vs = 3V
Rs = 10KO
SVR
9
f = 100Hz
-------------
= 22Hz to 22KHz
Rg = 10KO
~ I~tm~':s~
3
24
33
dB
____________
3~/4
737
TDA7231
Fig. 3 - Output power versus supply
voltage
Fig. 4 - Quiescent current versus
supply voltage
G 6244
4
I
Po
(W)
-
f:1KHz
d=IO'I.
Rl =8.n.
/
2.4
2.0
,It
1.6
)
1.2
/
10-'-
I-
/
1/
II
/
/
1/
0.8
0.'
V
/
V
V
I..:I::P""
o
10
,
12
c;.- 6031
SVR
(dB )
Vo
1/
/
V
50
/
/
12
Fig. 6 - Supply voltage rejection
versus frequency
Fig. 5 - Quiescent output voltage
versus supply voltage
G - 6243
(V)
10
aW11
Vs=6V.!.I111I1
VR =0.5VRMS
Rle
Rg='0KJ1
an
,
40
/
/
V
/
/
30
V
20
10
12
",,(V)
10
10'
10
3
10 4
f (Hz)
..:;4/'-.:4------------l.flI~tm?:19J1------------738
TDA7232
LOW NOISE PREAMPLIFIER COMPRESSOR
•
SINGLE SUPPLY OPERATION (10 to 30V)
•
HIGH SUPPLY VOLTAGE REJECTION
•
COMPRESSOR FACILITY
•
VERY LOW NOISE AND DISTORTION
•
HIGH COMMON MODE REJECTION
•
SHORT CIRCUIT PROTECTION
clipping and three mUltipurpose operational
amplifiers.
A high stability voltage regulator is also included.
The TDA 7232 is assembled in a 20 lead dual in
line plastic package.
The TDA 7232 is a preamplifier mainly intended
for car-radio applications, requiring very low
noise and distortion performance.
It consists of a unity gain differential input
amplifier with a very high common mode rejection, a compressor wich avoids the output
DIP-20 Plastic
(0.4)
ORDER CODE: TDA 7232
BLOCK DIAGRAM
3
5 6
4
22M
o
2
11
2
20
VOLTAGE
REGUL.
3
4
19
June 1988
18
17
16
15
5-9615/1
1/12
739
TDA7232
ABSOLUTE MAXIMUM RATINGS
30
40
Operating supply voltage
Peak supply voltage (for 50 ms)
Input voltage
Operating temperature
Total power dissipation at Tamb = 70°C
v
V
± V.
-25 to 85
1
CONNECTION DIAGRAM
BALANCED INPUT
COMPRESSOR
1st OPER. AMPLIFIER
IN.
SUPPLY VOLTAGE
IN-
REGULATED SV (VR/2)
IN·
1
GND
'N -
4
COMPRESSOR ATTACK I
OECAY TIME SETTING
OUT
5
COMPRESSOR RECTIFIER INPUT
6
OUT
OUT
7
IN -
IN+
8
IN +
IN-
9
OUT
10
{'N-
OUT
IN.
3rd OPER. AMPLIFIER
I
2 nd OPER. AMPLIFIER
5-9584/2
THERMAL DATA
Rth
j-amb
Thermal resistance junction-ambient
""2/:..::1.::..2_ _ _ _ _ _ _ _ _ _ _ _
740
@
!~I~m?elf
max
80
-------------
TDA7232
ELECTRICAL CHARACTERISTICS (T amb = 25°C, Vs = 14.4V, Gv = 30 dB, refer to test circuit
amplifier fig. 1)
Parameter
Test conditions
Min.
Vs
Supp Iy vo Itage
Is
Supply current
Gv
Closed loop gain
Pin 1-2 to pin 15
d·
Total harmonic distortion
f = 1 KHz
out of compression Vo=2VRMS
in compression
Vo
Output volt. swing
eN
Total output noise
SVR
Supply volt. rejection (*)
TVp.
Vi = 0.7 VRMS
7.5
B = 22 Hz to 22 KHz
Rg = 50n
Curve A
Rg = 500
V R =1V RMS
f = 100 Hz
90
Unit
30
V
10
16
mA
30
31
dB
0.03
0.12
%
0.15
0.5
%
10
29
Max.
8.4
V
160
/JoV
120
/JoV
110
dB
INPUT DIFFERENTIAL AMPLIFIER
VOS
Input offset voltage
Gv
Voltage gain
f = 20 Hz to 20 KHz
eN
Total input noise voltage
Rg = 500; B = 22 Hz to 22 KHz
1.5
/JoV
Rg = 500; curve A
1.1
/JoV
0.Q1
%
0.98
1
7
mV
1
1.02
V/V
d
Distortion
RL = 2 KO
f = 1 KHz
Vo
Output swing
RL = 2 KO
7.5
8.4
Vpp
1
V!/JoS
f = 20 Hz to 20 KHz
36
50
dB
SR
Slew rate
CMR
Common mode reject.
Vo=lVRMS
COMPRESSOR
Ib
Input bias current
Vos
Input offset voltage
Rg';; 10 KO
out of compression
Vos
Output offset voltage
in compression
eN
Total input noise volt.
R g = 500; B = 22 Hz to 22 KHz
1.8
/JoV
Rg = 50n; curve A
1.3
/JoV
0.Q1
%
d
Distortion
RL = 2 KO
f = 1 KHz
SVR
Supply voltage rejection
V R = 1V,
60
300
nA
1
3.5
mV
350
mV
V pin .17= 0.7V
Vo= 1 VRMS
Gv = 20dB
f = 100 Hz,
Rg = 500
dB
86
(*) Referred to the input.
------------- ~ ~~l;m~SSJl ___________
--"'3/0.=12
741
TDA7232
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Vo
DC output voltage swing
SR
Slew rate
Test conditions
RL = 2 KO
Min.
Typ.
7.5
8.4
V
0.7
V/",S
Max.
Unit
1st AND 3rd OPERATION AMPLIFIER
Ib
I nput bias current
60
300
nA
los
Input offset current
20
50
nA
1
3.5
mV
Vos
Input offset voltage
CMR
Common mode rejection
Rg " 10 KO
dB
86
SVR
Supply volt. rejection
VR = lV,
eN
Total inp. noise volt.
R g = 500; B = 22 Hz to 22 KHz
Vo
Output volt. swing
RL = 2 KO
d
Total harmonic distortion
RL = 2 KO
f = 1 KHz
Gv
Open loop gain
RL =2 KO
SR
Slew rate
RL = 2 KO
f=l00Hz,
Rg = 500
dB
86
1.4
Rg = 500; curve A
7.5
Vo=lVRMS
Gv = 20dB
86
",V
1.1
",V
8.4
Vpp
0.01
%
100
dB
1
Vi",S
2nd OPERATIONAL AMPLIFIER (G v = 12 dB internally set)
Vos
Output offset voltage
SVR
Supply voltage rejection
eN
Total input noise voltage
4
V R = lV
f = 100 Hz
15
86
mV
dB
Rg = 500; B = 22 Hz to 22 KHz
2.2
",V
Rg = 500; curve A
1.4
",V
Vo
DC output volt. swing
RL = 2 KO
d
Total harmonic distortion
RL = 2 KO,
Vo= 1 VRMS
Gv
Voltage gain
f = 20 Hz to 20 KHz
SR
Slew rate
RL =2 KO
7.5
f = 1 KHz
11.5
8.4
V
0.D1
%
12
12.5
1
dB
V/",S
VOLTAGE REGULATOR
Vo
Output voltage
Pin 19
Isink. source
from 0 to 12 mA
10
Output max. current
Isource
'
sink
...:.:4/-"1"-2-----------I..fi.I~tm&~s:lf
742
4.6
5
5.4
V
12
mA
12
mA
-------------
TDA7232
Fig. 1 - Test circuit
330pF
2.2 R9
fl
RIO
2.2Kn
BALANCED
10
INPUT CF2H=-+-+-+=~
€:
11
12
13
16
15
10Kn
Rl
10
L -______~~~__~Kn
5-9585/1
2.2 Kfl
R.
R3
R5
2.2Kn
OUT
Fig. 2 - P.C. board and components layout of the test circuit of fig. 1 (1: 1 scale)
~ ~~~~m~'~Jl-------
_____
.::.5/<==12
743
TDA7232
Fig. 3 - Supply current vs.
supply voltage (complete
test circuit)
"
(mA1I--I--I--HH-t-t--+--+--+-f--l
12
Fig. 5 - Distortion vs. frequency (complete test circuit)
Fig.4 - Compression characteristics
'0
..
r---r----r-,--TT1rm--,---,---rTTrm
Yo .. uv
(dB)
IIII
,.,., I-f+l++li:
itJfl- i-+1-1M1j----j--f++!llII-t-J-l.i.Jillj
0.24
1-f+l++II++++-II-H+Htffi---++++IJjll-+-J-j~
0.20
Yo=2V
0.16 f--C=R",
-.
'rt,nnnJH-++fl1llf-f-++-IlllII---f-l-I-WllII
/
-11
fslKHz
-18
10
11
16
VsIVI
10'
¥j(mYI
Fig. 7 -Supply voltage rejection vs. frequency (complete test circuit)
6-m.
Fig. 6 - Distortion vs. input
signal level (complete test
circuit)
Fig. 8 - Distortion vs. out·
put voltage (input differ.
amplifier)
d
., I I
,.
,.,.,d
~PR~
0.'
0.5
11II
11111
(1111
10KHz
1KHz
1KHz
"'
OJ
10
..mIl
IIIII
,
008
801-
,', I~._}~IJIL
If!
tOl
,.
M.
M8
,"4
,
10
UHal
--
RL=ZK
I
0.12
10
,r-f.-'
\f\...
f'...
0.4
"
I
I
0.8
u
I.'
Fi. 11 - Distortion vs. frequency (compressor)
G·6ll4
,."
d
1111111
111111
I
_Rl"2Kn
Vo=lV
20KHz
020
0.16
0.12
/
lOI
6
'--13212019
4
CD'
11 ..
91
CO
..L. cao
R9
I
'"
~
Q)
-0
~
;:;.
IB
...o·
Q)
.....
'"
u
U
CD
U
:;,
n
It ~
~.
c:
;:+.
R20
c:
16
5
!!!.
:;,
(Q
....
::T
TDA 7260 15
~
.
.9
a:
.~
aoU»
!:i!
~O
6
13
1
I
B
'"-i
0
»
-..J
14
9
10
'"m
11 ~
0
Q)
c:
C19
~.
Q.
o·
~S
...
+
~Z
- DC GROUND
8-8587
V/2 - AC GROUND
"::E
s::
~RlU
I\i
u
..,.
-..J
10
1-;::.
-..J
'"
COMPONENT LIST
Al =390
A2 =25KO
A3 = 25Kn
A4 =100Kn
A5= lKO
A6= 100Kn
A1 = 470Kn
AB=2.711
A9= lKO
Al0 = 0.0250
All =200
A12 = 2011
A13 =2011
A14 = 200
A15 = (Jumper)
Al6 = (Jumper)
A17 = (Jumper\
AlB = (Jumper
A19 = 10KO
A20= 10KO
A21 = 10KO
A22 =47KO
A23= 10KO
A24 = 10KO
A25 =39KO
A26·7.5KO
A27 =3.9KO
A28 = t.b.d.
Cl = 390pF
C2 = 390pF
C3 = 150pF
C4 =2.2)lF -16V
C5 = 41jlF - 16V
C6 = l00nF pol.
C7 = 470l'F - 25V
C6 = 470l'F - 25V
C9 = 390pF
Cl0 = 470nF
Cl1 = 390pF
C12 = 100nF
C13 390pF
C14 =100nF
C15 = l00nF
C16 = 390pF
=
C17 = 4.7"F - l6V
ClB = 100nF
Cl9 = lO"F -16V
C20 = 10"F -l6V
C21 = 100nF
C22 = l"F -l6V
C23 = 100nF
C24 = 10l'F - 25V
C25 = 330pF
C26 = 220nF
C27 = 10"F - 25V
C28 = lOOnF
C29 = 4.7"F - 16V
C30 = 100nF
C3l = 100nF
L1 = lSOuH
L2 = lSuH
L3 = lSuH
NOTE
Ql = P321
Q2 = P321
Q3 = P321
Q4 P32l
(SGS)
(SGS)
(SGS)
(SGS)
WITH NO EQUALIZATION FLAT
RESPONSE, Gv tot = 42dB
(A) = OPEN
(S) =OPEN
(C) = OPEN
(O) = A = 2.2KO
(E) = A = 2.2KO
(F) =OPEN
(G) = JUMPEA
(H) = OPEN
(I) = OPEN
(L) =OPEN
(M) = JUMPEA
(N) = OPEN
(0) = OPEN
(P) = A = 2.2KIl
(Q) = A = 2.2KIl
(A) = OPEN
~
I\)
CtJ
I\)
TDA7232
Fig. 19 - P.C. board and components layout of the circuit of fig. 18 (1 : 1 scale)
en
III
N
a
I
~
.2
::E~
:::;iii
<:(
o
00
U
ZZ
If)
~
w
ZI-
~~
<:(::>
u U
<:(Z
0
<:(
-'0..
lD~
<:(
lD
u
~lO~/~12~______________________ ~!~t;~~~:
748
---------------------------
"
cpo
'"o
I
;::.
"
'"C-
40Hz
200Hz
1KHz
4.5KHz
~~~K1t ~R65BK1t ~:~8K1t ~
16KHz
Ol
::l
Q.
'"
'"
.Q
c:
!!!.
N'
!!l
:E
;:j:
::r
C'l
o
3
~
(il
~
~
o·
::l
~Ut
@!n
::l
Ig
o·
:;;JUt
Q.
Ol
~iI
@Ut
~O
~2
13
BALANCED
INPUT
+14V
Cl0
10pF
15 \6
2
100
~'il:
14
Q
P7
10Kl1.
~L
10
·LO~EQ.OUT
20
10pF
I
TDA7232
ICI2T
12
13
}11
I ~~9
OFLAT OUT
22K1l.
R28
1
10}JF
10}JF
1
'"
R30
180
l1.
PI to P5 = 100Kll LIN.
'3
.....
...
"'co" I~
5-9588
-f
~
......
N
Co)
N
TDA7232
Fig. 21 - P.C. and components layout of the circuit of Fig. 20 (1 : 1 scale)
Fig. 22 - Frequency response of the five bands equalizer circuit
dB
./
, ,
......
/
16
12
8
.,.
-
4
o
-4
-8
-12
"
'\..
-16
10
~12~/~12~
750
_____________________
100
1K
10K
~!~i;~~~
I(Hz)
__________________________
TDA7233
1W AUDIO AMPLIFIER WITH MUTE
• OPERATING VOLTAGE 1.B TO 15V
•
EXTERNAL MUTE
FUNCTION
OR
POWER DOWN
•
IMPROVED SUPPLY VOLTAGE REJECTION
•
LOW QUIESCENT CURRENT
•
HIGH POWER CAPABILITY
•
LOW CROSSOVER DISTORTION
The TDA7233 is a monolithic integrated circuit
in B pin Minidip or SO-B package, intended for
use as class AB power amplifier with a wide range
of supply voltage from 1.BV to 15V in portable
radios, cassette recorders and players.
Minidip Plastic
SO-8J
ORDERING NUMBER: TDA7233 (Minidip)
TDA7233D (SO-B)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output peak current
Totsl power dissipation at Tamb = 50°C
Storage and junction temperature
16
1
1
-40 to 150
APPLICATION CIRCUIT
+vs
June 1988
1/4
751
TDA7233
CONNECTION DIAGRAMS
(Top view)
GND
1
B
+ INPUT
GND
1
B
+ INPUT
MUTE
2
7
- INPUT
2
7
- INPUT
+VS
3
6
SVR
OUTPUT
MUTE
GND
3
6
4
5
SUR
OUTPUT
POWER
GND
5
4
+VS
5 -10679
5-961B/1
80-8
Minidip
Fig. 1 - Test and application circuit
+vs
II
C3
.J.. ..I..C6 100nF::c ::c 220uF
22UF
Yin
C4
86
3
+
THERMAL DATA
Rth J-amb
Thermal resistance junction-ambient
80-8
Minidip
max
::.!2/~4_ _ _ _ _ _ _ _ _ _ _ _ ~ 1~I~m~SJI------------
752
TDA7233
ELECTRICAL CHARACTERISTICS
Parameter
Vs
Supply vo Itage
Vo
Quiescent out voltage
Quiescent drain current
6V, Tamb
25°C, unless otherwise speficied)
Min.
Test Conditions
Typ.
1.8
Max.
Unit
15
V
2.7
V
= 3V
= 9V
1.2
4.2
V
V
MUTE HIGH
3.6
MUTE LOW
0.4
Vs
Vs
Id
(V s
9
rnA
Ib
Input bias current
Po
Output power
d = 10%
V. = 12V
Vs = 9V
Vs = 9V
Vs = 6V
Vs = 6V
Vs = 3V
Vs = 3V
f = 1KHz
RL = 8n
RL = 4n
RL = an
RL = an
RL = 4n
RL = 4n
RL = an
RL
Vs
100
nA
1.9
1.6
1
0.4
0.7
110
70
W
W
W
W
W
mW
rnW
0.3
%
39
dB
d
Distortion
Po = 0.5W
f = 1 KHz
Gv
Closed loop voltage gain
f
= 1KHz
RIN
Input resistance
f
=
eN
Total input noise
(R. = 10Kn)
B
= Curve A
2
B
=
3
SVR
1M
= an
= 9V
1KHz
100
Kn
,.V
22Hz to 22KHz
= 100Hz,
Supply voltage rejection
f
MUTE attenuation
Vo
= 10Kn
45
dB
70
dB
MUTE threshold
0.6
V
MUTE current
0.4
rnA
=
lV
Rg
f
= 100Hz to
10KHz
-------------I.iii.I~~~m?:l9lt
___________
---'3==/4
753
TDA7233
Fig. 2 - Output power vs.
supply voltage
·0
(W)
Fig. 3 - Supply voltage
rejection vs. frequency
.VR r-T""T"T"mm-rTT1TI1lr......,..,.,.,TT11T"--'F·-:r;"'i1"mn
(dB) f-'"V.W.-!IBV.!'It--H-tH1I1tf-++-Hft~++t+IHlI
RL .a.n.:f-rHTttttH-f+ffHII-f-H1illl1
f ,,1KHz
d=lO"I..
Fig. 4 - DC output voltage
vs. supply voltage
Vo rr-r"---,-r-,.-,-r-,-,,.-r:n'--,
H4-+--i'-l-+-H-++-H4-+--i---l
(YJ
2.'
2.0
'A
1.6
1.2
0.6
0.'
10
10
12
10"
Fig. 5 - Quiescent current
vs. supply voltage
10
t (Hz)
12
YsIV)
Fig. 6 - Total dissipated
power vs. supply voltage
.,ot rr-,-.,--,r-r..-r-r-r..,-".""'f'--f!"~"L,
(mW)H++-I~+H++H++-I--l
10
4/4
754
600
H++-I~--hl--++¥H++-I--l
200
H+~~4-H++H++-I--l
10
12
~ ~~~~m&';1~~
12
VsIY)
-------------
TDA7236
VERY LOW VOLTAGE AUDIO BRIDGE
ADVANCE DATA
The TDA7236 is a monolithic bridge audio
amplifier in minidip and SO-8J package intended
for use as audio power amplifier in telephone
sets, mono radio receivers, etc .. Its main features
are: minimum working supply voltage of 0.9V
and low quiescient current.
SO-8J
Minidip Plastic
ORDERING NUMBER: TDA7236 (Minidip)
TDA7236D (SO-SJ)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output power current
Total power dissipation at Tamb = 50°C
Storage and junction temperature
1.8
50
0.5
-40 to+150
Fig. 1 - Test and Application circuit
7
6
3300pF
820 pF
czll---+:C~>-----l'1-::-:'
100nF
C3
5-
June 1988
~11211
r
1/4
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
755
TDA7236
SCHEMATIC DIAGRAM
5
3
2
7
6
5-9173
CONNECTION DIAGRAM
(Top view)
B
+Vs
OUT1
2
COMP1
3
IN
4
NC
6
GND
5-9174
THERMAL DATA
RthJ-.12W
Kl
II
(dBI
0,4
14
Fig. 8 - Supply voltage
rejection vs. frequency
vs.
Fi L =8n
ID
12
1l
TDA7241
20W BRIDGE AMPLIFIER FOR CAR RADIO
ADVANCE DATA
•
Reliable operation is guaranteed by a comprehensive array of on-chip protection features.
VERY LOW STAND-BY CURRENT
• GAIN = 26dB
•
These include protection against AC and DC
output short circuits (to ground and across
the load), load dump transients, and junction
overtemperature. Additionally, the TDA7241
protects the loudspeaker when one output is
short-circuited to ground.
OUTPUT PROTECTED AGAINST SHORT
CIRCUITS TO GROUND AND ACROSS
LOAD
,
• COMPACT HEPTAWATT PACKAGE
•
DUMP TRANSIENT
• THERMAL SHUTDOWN
•
LOUDSPEAKER PROTECTION
•
HIGH CURRENT CAPABILITY
•
LOW DISTORTION / LOW NOISE
Heptawatt
The TDA7241 is a 20W bridge audio amplifier
IC designed specially for car radio applications.
Thanks to the low external part count and
compact Heptawatt 7-pin power package the
TDA7241 occupies little space on the printed
circuit board.
ORDERING NUMBERS: TDA 7241V
TDA 7241H
TEST CIRCUIT
-us
228uF
6
TDA7241
7 1---4-----.,
OUT
5 I----e-----l
e.22uF
I
88TOJ!l?241-S1
June 1988
1/3
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
765
TDA7241
CONNECTION DIAGRAM
(Top view)
~1.0UTPUT
5UPPLY VOLTAGE
OUTPUT
GND
INPUT
5VR AND 5TAND-BY .
~ I
L
tab connected to pin 4
FEEDBACK
S-9517
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10 (*)
10 (*)
Ptot
Tstg • T J
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50ms)
Peak output current (non repetitive t = 0.1 ms)
Peak output current (repetitive f ;;;. 10Hz)
Power dissipation at Tease = 70°C
Storage and junction temperature
18
28
40
4.5
3.5
20
-40 to 150
V
V
V
A
A
W
°C
(*) Internally limited
THERMAL DATA
Rth J-case
Thermal resistance junction-case
~2/~3_________________________ ~~~~~~?~~~:
766
max
4
___________________________
TDA7241
ELECTRICAL CHARACTERISTICS (Refer to the circuit of Fig. 1, Tamb = 25°C, Rth (heatsink)=
4°C/W, Vs = 14.4V)
Parameter
Test Conditions
Min •
Typ.
Max.
Unit
Supply voltage
18
V
Vos
Output offset voltage
150
mV
Id
Total quiescent current
120
mA
Po
Output power
Vs
d
..
Distortion
R L =40
f = 1 KHz
d = 10%
65
R L =40
18
20
R L =80
10
12
W
f = 1 KHz
RL=40
Po = 50 mW to 12W
0.1
0.5
R L =80
f = 1 KHz
Po = 50 mW to 6W
0.05
0.5
%
Gv
Voltage gain
f = 1 KHz
SVR
Supply voltage rejection
f=100Hz
En
Total input noise
(*)
45
26
dB
52
dB
2
4
pV
Rs= 10 KO
(**)
3
1'/
Efficiency
R L =40
Po = 20W
f = 1 KHz
Isb
Stand-by current
Ri'
I nput resistance
f = 1 KHz
Vi
Input sensitivity
f = 1 KHz
Po= 2W
R L =40
Low frequency roll off
(-3dB)
Po = 15W
R L =40
fH
High frequency roll off
(-3 dB)
Po = 15W
R L =40
As
Stand-by attenuation
Va = 2 V rms
VTH(pin.2) Stand-by threshold
(*) B = Curve A
%
1
pA
70
fL
Bandwidth
65
KO
140
mV
30
25
70
Hz
KHz
90
dB
1
V
(**) B = 22 Hz to 22 KHz
------------- ~ 1~l;mg'19~ ___________-'3~/3
767
TDA7250
60W HI-FI DUAL AUDIO DRIVER
ADVANCE DATA
The TDA7250 stereo audio driver is designed to
drive two pair of complementary output transistor in the Hi-Fi power amplifiers.
• WIDE SUPPLY VOLTAGE RANGE: 20 TO
90V (± 10 TO ± 45V)
•
VERY LOW DISTORTION
•
AUTOMATIC QUIESCENT CURRENT CONTROL FOR THE POWER TRANSISTORS
WITHOUT TEMPERATURE SENSE ELEMENTS
DIP-20 Plastic
• OVERLOAD CURRENT PROTECTION FOR
THE POWER TRANSISTORS
•
MUTE/STAND-BY FUNCTIONS
•
LOW POWER CONSUMPTION
(0.4)
ORDERING NUMBER: TDA7250
• OUTPUT POWER 60w/an AND 100W/4n
APPLICATION CIRCUIT
0.47}JF
(Rl~
STEREO
INPUT
2
16
+vs
17
0.47}JF
tLlV
18
9
19
3
TDA
7250
4
20
~____________________~~r-~101~
14
8
15
13
12
7
-vs
5- 974112
June 1988
1/8
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
769
TDA7250
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Power dissipation at Tamb = 60°C
Storage and junction temperature
100
1.4
-40 to +150
CONNECTION DIAGRAM
(Top view)
IN-CHl
IN + CHl
OUT- CHl
QUIESCENT CURR.
CHl
OUT+CHl
SENSE-CHl
SENSE+-CHl
STAND-BY/MUTEI
PLAY
CURRENT PROGR.
SENSE -CH2
AC GND
SENSE+CH2
QUIESCENT CURR.
CH2
OUT+CH2
IN +CH2
OUT-CH2
IN-CH2
THERMAL DATA
Rth j-amb
770
Thermal resistance junction-ambient
max
65
TDA7250
PIN FUNCTIONS
N°
NAME
FUNCTION
Vs- POWER SUPPLY
Negative supply voltage.
2
NON-INV. INP. CH. 1
Channel 1 input signal.
3
QUIESC. CURRENT
CONTR. CAP. CH 1
This capacitor works as an integrator, to control the
quiescent current to output devices in no-signal conditions on channel 1.
4
SENSE (-) CH.1
Negative voltage sense input for overload protection
and for automatic quiescent current control.
5
ST. BY / MUTE / PLAY
Three-functions terminal.
For VIN = 1 to 3V, the device is in MUTE and only
quiescent current flows in the power stages;- for
VIN < 1V, the device is in STAND-BY mode and no
quiescent current is present in the power stages; - for
VIN > 3V, the device is fully active.
6
CURRENT PROGRAM
High impedance power-stages monitor.
7
SENSE (-) CH.2
Negative voltage sense input for overload protection
and for automatic quiescent current control.
8
QUIESC. CURRENT
CONTR. CAP. CH.2
This capacitor works as an integrator, to control
the quiescent current to output devices in no-signal
conditions on channel 2. If the voltage at its terminals
drops under 250mV, it also resets the device from
high-impedance state of output stages.
9
NON-INV. INP. CH. 2
Channel 2 input signals.
10
Vs- POWER SUPPLY
Negative supply voltage.
11
INVERT. INP. CH. 2
Feedback from output (channel 2).
12
OUT (-) CH.2
Out signal to lower driver transistor of channel 2.
13
OUT (+) CH.2
Out signal to higher driver transistor of channel 2.
14
SENSE (+) CH.2
Positive voltage sense input for overload protection
and for automatic quiescent current control.
15
COMMON AC GROUND
AC input ground in MUTE condition.
16
Vs+ POWER SUPPLY
Positive supply voltage.
17
SENSE (+) CH. 1
Positive voltage sense input for overload protection
and for automatic quiescent current control.
18
OUT (+) CH.1
Out signal to high driver transistor of channel 1.
19
OUT (-) CH.1
Out signal to low driver transistor of channel 1.
20
INVERT. INP. CH. 1
Feedback from output (channel 1).
__________________________
~~~~~~~~
________________________3~/8
771
TDA7250
BLOCK DIAGRAM
2
o()--------,
'<;J---t-tr-U 17
20----o~~
>~L-9---~--------1---~---r~-o19
~-------v
'-C=r4-tt--olB
L---1-----~--~~3
~-o-_O------~-r_()4
5
I
HIGH
IMPEDANCE
STATE
15
I
I
I
I
14
t
9
11
12
I
I
I
I
~---'------~
-1------1
I
I
13
I
..1-
..L.c'
+VS
B
~
6
[ref
7
10
.:..:4/...:.8_ _ _ _ _ _ _ _ _ _ _ _
772
5-9743/1
~ ~~I~m?1J~~I1-------------
TDA7250
ELECTRICAL CHARACTERISTICS
(Tamb
25°C, Vs = ± 35V, play mode, unless otherwise
specified)
Parameter
Test Conditions
Vs
Supply voltage
Id
Ouiescent drain current
Min.
Typ.
±10
Stand-by mode
a
Play mode
10
Max.
Unit
± 45
V
mA
Ib
Input bias current
Vos
Input offset voltage
los
Input offset cu rrent
Gv
Open loop voltage gain
14
0.2
1
p.A
1
±10
mV
100
200
nA
f = 100Hz
90
f = 10KHz
60
RG = 600n
B = 20Hz to 20KHz
3
p.V
10
V{p.s
da
eN
Input noise voltage
SR
Slew rate
d
Total harmonic distortion
VoPP
Output voltage swing
Po
Output power (*1
Gv = 26dB
f = 1KHz
0.004
Po = 40W
f = 20KHz
0.03
Vs = ± 35V
Vs=±30V
Vs = ± 35V
%
RL = an
RL = an
RL = 4n
60
Vpp
60
40
100
W
10
Output current
±5
mA
SVR
Supply voltage rejection
f = 100Hz
75
dB
Cs
Channel separation
f = 1 KHz
75
' dB
0.1
p.A
MUTE I STANDBY I PLAY FUNCTIONS
Ii
Input current (pin 51
Vth
Comparator standby {mute
threshold (**1
H
Hysteresis standby {mute
Vth
Comparator mute {play
threshold (**1
H
Hysteresis mute {play
Mute attenuation
VI
1.0
1.5
200
2.4
f = 1 KHz
12 (*01
Input voltage max. (Pin 51
(*1 Application circuit of fig. 1
(UI Referred to -Vs
1.25
f = 1KHz;
-------------
d = 0.1%;
3.0
V
mV
3.6
V
300
mV
60
dB
V
Gv = 26dB
~ !~;m~~sa:
____________
5:::.<..::/8
773
TDA7250
<)
ELECTRICAL CHARACTERISTICS (continued)
CURRENT SURVEY CIRCUITRY
Comparator reference
0.8
0.8
to +Vs
to -VS
Delay time
td
1
1
1.4
1.4
V
V
10
j.lS
QUIESCENT CURRENT CONTROL
Capacitor current
Charge
Discharge
Comparator reference
to +VS
to -Vs
30
250
60
500
10
20
10
j.lA
j.lA
25
mV
mV
Fig. 1 - Application circuit with Power Darlingtons
r-----r-~~--,-------~====~==~====;===============~==~-+U9
112
1.SK
uF
188UFJ:
1uF
188
pF
I
1SpF
330hm
22
Kohm
18
4.7
uF
PLAY
I1UTE 0----------1 5
STANDBY
3
2.7KohlO
8
22
uF
-UII
ohm
12HBpF
It':,UT --I11---t-----~-1 2
1HH
pF
B.15
OUT
19
TDA
7250
Ill'
330hm
4
14
-~~:.:::..:~
~-----l15
2.2
uF
1
13
OUT
III
12
INPUT 1uF
I u--lII-.-----...-.......-1
9
15pF
22
Kohli
L-~--l------~--4-----------------l~--~-Us
1HB
nF
1f111111JIIl'258 -BI
NOTE: 01/02=03/04 =TIP 142/TIP147
GV = HR1/R2
~6/~8________________________ ~lil~~~©~
774
--------------------------
TDA7250
Fig. 2 - Output power vs.
supply voltage
G-UGO
Po
(W)
1
100
1
'1
d
BJt
/
0.1
......
60
V
Vs
r-
20KHz
= ±35V
VIN =1VRMS
40
J
40
c.
80
/
60
Fig. 4 - Channel separation
(da
Vs=':t35V
RL=8ll.
1
RL=4Jt
f-- d=O.1°f.
0-130'
('/0)
1
t = lKz
80
Fig. 3 - Distortion vs. output power (*)
0.01
V J
0
1KHz
20
20
~
.:!:10
0.001
±20
±30
±40
'%50
Vs(Y)
10
Fig. 5 - Supply voltage rejection vs. frequency
20
30
40
50
60
f(Hz)
3UII
Iq
Iq
(mA )
80
10'
10'
Fig. 7 - Quiescent current
vs. Tamb
Fig. 6 - Quiescent current
vs. supply voltage
G-
10'
10
Po (W)
(mA)f-+-++f--t-t;;-V.-==·...
35iu
v-t-t--
20
20f--+-~-r-+-+~--r-T-~-i
15
15 f--+-+--+--+-+---j--+--+-+--j
70
60
-
50
+Vs/GND
40
--- -
10
--~-Vs/GND
30
20
I--
f-
10
10-
-
f--+--+-+-+-+-+-+-r--10
10'
10'
10"
f (Hz)
10 20 30 40 50 60 70
(}
Fig. 8 - Total dissipated
power vs. output pow;r,,!,*)
Fig. 9 - Efficiency vs. output power (*)
Tamb('C)
Fig. 10 - Play-mute standby operation
G-6307
\!s=±25V
70
so
II V
/ /
40
o
20
10
H++-If--t+H++-f-t+H-l
20
40
60
80
100'
10
V
/
60
./
PLAvH-f-+-i-++-H-+-+-I4r+rH-j
RL=811
f =lKHz
II
/1
Po (W)
+35V
,
ST-BVH++-IYl+-H++-If--t+-H-1
,
20
'0
60
80
100
120
Po(W)
(*) Complete circuit
-------------
~ I~mg,=:
___________
---'-'-=7/8
775
TDA7250
Fig. 11 - Application circuit using power transistors
02
r-T~-T--~;==;:::::;::=::;::=====::::::;::==J--. -Us
105K
188uF
19SpF
::I:
B.15
ohm
330hm
12BBpF
1SpF
luF
'i':,UT --II--~---+---I
1:FB
I
2
22
KahN
PLAY
MUTE ......- - - - - 1
OUT
IR'
5
STANDBY
2.7Kohm
3
22
_v~':..I..-.TB.6B
TDA
uF
2. ?Kohm
B
22
4
~--+----c~-~-~~~---Us
7250
uF
-u.,,-l--':;I:..::::::.J
uF
~--.--l15
OUT
III
INPUT luF
I Ll o--III-..--o----.~
9
15pF
330hm
22
Koh'"
B.15
188
pF
ohm
L-4--4-_ _ _~--+-------4--_+~ -U.s
188
nF
1188 rOfl?2511-112
Fig. 12 - Suggested transistor types for various loads and powers.
15W
30W
50W
70W
30W
50W
90W
130W
BOX
53/54A
BOX
53/548
BOW
93/948
TIP
142/147
BOW
93/94A
BOW
93/948
BOV
64/658
MJ
11013/11014
~8/~8_ _ _ _ _ _ _ _ _ _ _ _ ~ I~;m~~lf
776
------------
..~
..,L SGS-1HOMSON
~D©~@~[],,[~©'[j'OO@[R!JD©~
TDA7255
22W FRONT REAR OR BRIDGE FULLY PROTECTED
CAR RADIO AMPLIFIER
•
•
•
HIGH OUTPUT POWER
POP FREE SWITCHING
SHORT CIRCUIT PROTECTIONS: RL
SHORT - OUT TO GROUND - OUT TO Vs
•
•
•
•
•
MUTING IlP COMPATIBLE
VERY LOW CONSUMTION STANDBY
PROGRAMMABLE TURN ON DELAY
LOW DISTORTION AND LOW NOISE
DIFFERENTIAL INPUT
The TDA7255 a class B dual fully protected
power amplifier designed for car radio applications. The device can be switched from FrontRear to Bridge configuration by changing only
the loudspeaker connection. An input fader for
Front-Rear control is available. A high current
capability allows to drive low impedance loads
(up to 106m.
Other Protections:
•
•
•
•
LOAD DUMP VOLTAGE SURGE
LOUDSPEAKER DC CURRENT
VERY INDUCTIVE LOAD
OVERRATING TEMPERATURE
•
OPEN GROUND
Multiwatt-15
ORDER CODE: TDA7255
BLOCK DIAGRAM
9 .
5-9189
June 1988
1/6
777
TDA7255
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10
10
Ptot
Tst9 ' Tj
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50ms)
Output peak current (non repetitive t = 0.1 ms)
Output peak current (repetitive f ~ 10Hz)
Power dissipation at Tease = 60°C
Storage and junction temperature
18
v
28
V
V
40
4.5
4
30
-40 to 150
A
A
W
°c
CONNECTION DIAGRAM
(Top view)
~
$-
8
7
6
-$-
L
15
14
13
12
11
10
9
5
4
3
2
1
FRONTAC GND
REAR AC GND
REAR OUTPUT
SUPPLY VOLTAGE
FRONT OUTPUT
STANO-BY
SVR·
GND
FADER
FEEDBACK
FADER CONTROL
FADER
INPUT (-)
INPUT(.)
MUTING
5-9191
Tab connected to pin 8
THERMAL DATA
Rthj-case
Rthj-amb
Thermal resistance .iunction-case
Thermal resistance junction-ambient
________________________
~2/~6
778
~~~~;~gr~:
max
max
3
40
__________________________
TDA7255
ELECTRICAL CHARACTERISTICS
(Vs
14.4V, RL
= 4U, f = 1KHz,
Tamb
= 2SoC
unless
otherwise specified)
Paremeter
Vs
Supply voltage
Id
Total quiescent drain current
RI
Input resistance
Vi
Input saturation voltage
Tj
Thermal shut down junction
temperature
Test Conditions
Mill.
Typ.
8
Max.
Unit
18
80
V
rnA
70
Kf!
300
mV
145
°c
6.5
11
12.5
W
W
W
FRONT REAR APPLICATIONS (Fig 2)
= 10%
RL = 4f!
RL = 2f!
RL = 1.6f!
Output power
THD
d
Distortion
Po
Gv
Voltage gain
eN
I nput noise voltage
RG = 10Kf!
SVR
Supply voltage rejection
RG = 100Kf! Vr
I = 300Hz
CMR
Common mode rejection
1)
Elliciency
Po
Po
= O.lW
= 6.5W
5.5
to 4W
0.05
=
36
lV
+ 6.5W
0.5
%
28
dB
2.5(**)
2 (*)
p.V
p.V
45
dB
55
dB
70
%
BRIDGE APPLICATION (Fig 1)
Vos
Output olfset voltage
Po
Output power
THD
d
Distortion
Po
Gv
Voltage gain (CL)
eN
Total input noise voltage
1)
Efficiency
Po
SVR
Supply voltage rejection
RG
250
= 10%
= O.lW
RL
RL
= 4f!
= 3.2f!
18
to 2W
= 20W
= 10Kf!,
0.05
%
36
dB
2.5(**)
2.0 (*)
RG = 10Kf!
= 1V, I = 300Hz
45
I = 100Hz to 10KHz
60
Vr
mV
W
W
22
25
10
p.V
p.V
66
%
58
dB
MUTING AND STAND-BY FUNCTIONS
Muting attenuation
V ret
Muting-on threshold voltage
Pin.l
Muting-ofl threshold voltage
Pin.l
Stand-by attenuation
Vret
=
lW
dB
2.4
=
lV
I
= 100Hz to
Stand-bY quiescent drain current
10KHz
V
0.8
V
100
p.A
60
dB
(**) B = 22Hz to 22KHz
(*) B = curve A
___________________________
~~~~~~?~~
________________________
~3/6
779
TDA7255
Fig. 1 - Test and application circuit
(Bridge amplifier)
Fig. 2 - Test and application circuit
(FIR amplifier)
TDA7255
RI
2.2n
0.22""
IC10
Two high impectance inputs available for balanced or unbalanced operation.
The fader function is automatically inserted in front/rear configuration and allows the distribution of the power between the front and the rear. An external potentiometer must be connected between pins 4 and 7 with the control
terminal connected to pin 5 through a decoupling capacitor. In bridge applications the pins 4-5-7 must be left open.
Turn on delay. The output stages are muted during the turn on transient and start rising after the charge of the
capacitor connected between pin 9 and ground. The capacitor also avoids pops during bridge F/R switching.
Fig.3 - P.C. board and component layout of the circuits of Fig. 1 and 2 (1
1 scale)
POW.GND
AC GND R
AC GNDF
OUT R
OUTF
SIGN.GND
}
BALANCED
INPUT
POW.GND
+VS
6 _ _ _ _ _ _ _ _ _ _ _ _ .~ ~~I~R'rn?ell
--'4/_
780
TDA7255
FRONT/REAR CHARACTERISTICS
Fig. 4 - Quiescent drain
current vs. supply voltage
Fig. 5 - Quiescent output
voltage vs. supply voltage
Fig. 6 - Output power vs.
supply voltage
!>-6010
I
)
90
80
-f-
--
l - f-
70
,
)'
60
so
10
16
12
Fig. 7
frequency
10
Distortion
vs.
12
16
18
10
Fig. 9 - Supply voltage
rejection vs. capacitor values
(C1)
Fig. 8
Supply voltage
rejection vs. capacitor values
(C2)
G_6014
sv.
I
IdB )
(°'.1
0.'
(dB )
I
."'s ;14.4
-
Po :2.5W
50
ss
I
/.I
:
/1
40
220:F
0.'
"
0.2
L,4fl
0.1
,,'
10
Rg:l0KQ
47,u~;
Cl· 2lOpF
til
,,'
I(Hz)
"
Fig. 10 - Output signal vs.
fader control position
G-MII6
"'5,,14.4V
VR ,,1'JRMS
Rl ,,4fl
rrr-
"
30
4OH z {Fl
111I111
·
··
·
,
,
r-
Rg::IOKO
II
II
r-
RL,,411
!
111111
Fig. 11 - Power dissipation
and efficiency vs. output
power
Fig. 12 - Power dissipation
and efficiency vs. output
power
~ot
IW)
,,
Ptot
H-+++H-+-+++-H-+++--I
~-+++H-+-+++-H-+++--I
12
10
\\,
,
II!
'is=,,,.,,v
"R=1VRMS
i
to
"
I~
"' ~
10
r- .........
11
47,u F
IS
(R) 40Hz
,.,..
C,=470
nOJ.lf
lOOpF
25
I~O)t f-++++++-+-f-+++-+-++++I~.,
)
-JO
1!'~ ,V
V
RL,,2.n
-2 0
~
MlIfIIII
so
CZ,,470pf
0.4
-to
sv.
!
H----c7'F"+bI'-+-++H ~ot
40
:~:~';VI+
20
f :lKHzit-
(Flli Hz
1KHz (R)
20
"
10
12
Po
(W)
~ ~~~~m~1rt~l:
12
16
20
24
Po (W)
_____________5~/6
781
TDA7255
BRIDGE CHARACTERISTICS
Fig. 13 - Output power
vs. supply voltage
Fig. 14 - Distortion vs. fre·
quency
.,.-,-rrmm-r"TTlTmr--,-TTrTTTTr-,-,.:;:;:;;;;;,
"-
(W)
("4)
1=IKHz
d .. l0"l.
"
H-+ttttttl-+-ttltttlt-++++tttIt--+H-H-HlI
.J r--
2.
• .. H-+ttttttl-+-ttltttlt-++++tttIt--+H-H-HlI
24
20
"
." H-+ttttttl-+-ttltttlt-++++tttIt--+H-H-HlI
12
.,
H-+t~-+-ttltttlt-++++Wh~~~-HlI
H-+tmHId-ttltttlt-++++1tJI ~t:~~
0.05
6
8
10
12
14
16
18
20
22
VS(Vl
Fig. 15 - Supply voltage
rejection vs. frequency
G-6011
Rt_all.
10'
10
10'
I{Hz)
Fig. 16 - Power dissipation
and efficiency vs. output
power
G-6012
IIIII
Ys ..
(dB)
,4.4V
Vt",IV RMS
80
RL,,4n
Rg =10Kll.
--
70
,
60
H++-1-++-H-++-f-+-+-+--+--1
20
40
10
10'
10'
::.!6/.::.6------------I:ii..I~t~'~lt
782
12
16
20
24
Po(WI
-------------
..I'=='
.,L SGS-1HOMSON
[K'A]D©OO@~[b~©,[],OO@~D©~
TDA7256
22W BRIDGE FULLY PROTECTED CAR RADIO AMPLIFIER
ADVANCE DATA
•
NO AUDIBLE POP DURING MUTE AND
STANDBY OPERATIONS
• MUTING TTL COMPATIBLE
• VERY LOW CONSUMPTION STANDBY
• PROGRAMMABLE TURN ON DELAY
• DIFFERENTIAL INPUT
• SHORT CI RCUIT PROTECTIONS:
RL SHORT - OUT TO GROUND - OUT
TO Vs
•
The TDA7256 is a class B dual fully protected
bridge power amplifier, designed for car radio
applications. A high current capability allows to
drive low impedance loads (up to 2[2).
OTHER PROTECTIONS:
- Load dump voltage surge
- Loudspeaker DC current
- Very inductive load
- Overrating temperature
- Open ground
Multiwatt-11
ORDER CODE: TDA 7256
BLOCK DIAGRAM
STD-BY
8.1uF
+Us
:::c
MUTE
TDA7256 B
18
8.22uF
11
2.2
ohm
~
OUT-
IN
9
OUT+
2.2ohm
4
188uF
:::c 8.22uF
5
GNO
June 1988
88TDII?255-Bt
1/5
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
783
TDA7256
ABSOLUTE MAXIMUM RATINGS
Operating supply voltage
DC supply voltage
Peak supply voltage (for 50 ms)
Output peak current (no repetitive t = 0.1 ms)
Output peak current repetitive f> 10Hz
Power dissipation at T case = 70°C
Storage and junction temperature
18
28
40
V
V
V
Internally limited
5.5
36
A
W
-40 to 150
°e
PIN CONNECTION
OUT(-)
Vs
OUT( +)
STAND-BY
SVR
GND
FEEDBACK
FEEDBACK
IN(-)
IN(+)
MUTE
THERMAL DATA
Rth
j-case
Thermal resistance junction-case
=-<2/..::.5 _ _ _ _ _ _ _ _ _ _ _ _ _
784
~ ~~~~m?::~~lt
max
2.2
°e/w
--------------
TDA7256
14.4V, RL = 4n, f
ELECTRICAL CHARACTERISTICS (V s
= 1 KHz,
T amb = 25°C) (unless
otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Vs
Supply voltage
10
Total quiescent drain current
80
mA
Rj
Input resistance
70
Kil
8
18
V
MUTING FUNCTION
Muting attenuation
Vref = 1 Vrms
f = 100 Hz to 10KHz
60
d8
2.4
V
Muting-on threshold voltage
Pin 1
Muting-off threshold voltage
Pin 1
Stand-by attenuation
Vref = 1 Vrms
f = 1 00 Hz to 10K Hz
0.8
60
Stand-by quiescent drain
current
Vas
Output offset voltage
Po
Output power
d= 10%
THD
Distortion
Po =50mWto13W
Gv
Voltage gain (C L)
eN
Total input noise voltage
Rg= 10 KO
B = 22 Hz to 22 KHz
SVR
Supply voltage rejection
(closed loop)
Rg = 10 Kil
f = 300 Hz
TSD
Thermal shut down junction
temperature
R L =4 il
RL = 3.2il
R L =2 il
100
p.A
150
mV
22
26
28
45
W
W
W
0.05
%
36
dB
3
V r = lVrms
V
dB
10
p.V
58
dB
145
°C
Fig. 1 - Test and application circuit
STD-BY
~-+--+-____- - . Q
lBSuF :e
II. 1uF:e
cs
C4
+Us
C7
1SS
:e uF
C6
13. -:!2uF
18
B
2.2
ohm
R~
9
TDA7256
C2
8.1uF
o-J
2
INPUT
o-J
J
11
B.luF
RJ
Cl
2.20hm
CB:e B.22uF
GHD
tt88rDlI?256-Btll
- - - - - - - - - - - W'l
SCiS-11I0MSON
,/,
~ iIiIll©OO@I 80% at rated output power)
so no heatsinks are needed. Moreover, a built-in
limiter reduces the clipping effects.
The TDA7260 is a monolithic integrated circuit
in a 20 lead dual in line plastic package.
DIP-20 Plastic
(0.4)
The TDA7260 is a new type of audio driver
mainly intended for use in car radio applications.
In conjunction with four POWER MOS in bridge
configuration it can deliver 30W (d < 3% RL =
2,u). The device acts in "class D" as a pulse
ORDERING NUMBER: TDA7260
BLOCK DIAGRAM
19
MUTE
SHORT
CIRCUIT
PROTECT.
17
SIGNAL
PROCESSING
16
PONER ~_ _...().:lS~
THERMAL
PROTECTION
MOS
DRIVER ~_ _-. ~
13
VOLTAGE
REGULATORS
.10V
12
+4.SV
5-9641
June 1988
B
9
10
11
1/13
78!;1
TDA7260
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
V 1N
Vo
Ip
Ptot
Tstg • lj
Supply voltage
Peak supply voltage (50ms)
Input voltage
Differential input voltage
Peak output current
Total power dissipation at Tamb = 70°C
Storage and junction temperature
30
40
10
±6
300
1
-40 to + 150
V
V
V
V
mA
W
°C
CONNECTION DIAGRAM
(Top view)
OUT
1
20
~ MUTE
INTEGRATOR IN-
2
19
~ Vs
IN+
3
18
~
OUT
4
17
JQH
IN -
5
16 ] VB
IN +
6
15 ] QL
OVERLOAD
CURRo
7
14] QH
AC GND(VL)
8
13] VB
IOV REGULATOR
9
1 2 ~ QL
DITHER
10
INPUT
OP. AMPL.
11
SHORT
CIRCUIT SENSE
POWER
MOS DRIVE(+)
POWER
MOS DRIVE(-)
~ GND
S 964211
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
~2/~1~3________________________ ~~~~~~~v~~~
790
max
80
---------------------------
TDA7260
TEST CIRCUITS
Fig. 1 -
Fig. 2 2K!\'
lOOK!\'
VINV-l.-..r-----,
OUT
0---+'-------,
±sv
ININ+
5-96'4
Fig. 3
Fig.4
lOOK!\.
5-9646
Fig. 5
Fig. 6
"M.o--...c::J-+
__________________________
~!~~~~
______________________
~3/~13
791
TDA7260
ELECTRICAL CHARACTERISTICS (Tamb
= 25°C, Vs = 14.4V unless otherwise specified, refer
to test ci rcu it)
Test Conditions
Parameter
OPAMP
Vos
I nput offset voltage
Ib
Input bias current
±4
mV
1
300
nA
1
± 50
nA
1
dB
1
0.005
%
1
1.8
MHz
1
120
lot
Input offset current
Gv
Open loop voltage gain
d
Total harmonic distortion
BW
Unity gain bandwith
CMRR
Common mode rejection
VIN = 1V
f = 1 KHz
70
90
dB
1
SVR
Supply voltage rejection
V r = 1V
f = 1 KHz
80
100
dB
1
1
1
80
f = 1 KHz
Av = 1
0.8
En
Input noise voltage
B = 20KHz
1
mV
In
Input noise current
B = 20KHz
20
nA
SR
Slew rate
Vo
Output swing
0.8
R L =2Kn
RIN
17
V/ms
1
V
2
100
Kn
1
240
mA
2
mV
3
2.5
p.A
3
± 250
nA
3
± 3.2
± 2.6
Av = 1
Overload indicator current
INTEGRATOR
Vos
Input offset voltage
Ib
Input bias current
lot
Input offset current
10
Output current swing
sink
source
Vo
±4
0.5
3
lIVIN=±1V
RL=O
0.4
0.4
Output voltage swing
lIV I N=±lV
RL =5Kn
±3
CMRR
Common mode rejection
V IN = lV
f = 1 KHz
SVR
Supply voltage rejection
Vr = 1V
f = 1 KHz
1
1
70
90
80
100
100
RIN
BW
Unity gain bandwidth
Gn
Forward transconductance
mA
mA
V
3
dB
3
dB
3
Kn
3
4
MHz
3
30
mAN
3
10
V
4
70
dB
4
4.5
V
4
REGULATORS
Vo
Output stabilized voltage
SVR
Supply voltage rejection
VI
Ground voltage
"'-'4/..::1..;:..3 _ _ _ _ _ _ _ _ _ _ _ _
792
f = 1 KHz
V r = 1V
~ ~~I~m&~~~
60
--------------
TDA7260
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
SYSTEM SPECIFICATION
Vs
Operating supply voltage range
Is
Supply current
V tm
Mute threshold voltage
Vtmh
Mute threshold hysteresis
VIN =0
V
6
VoH
Output swing
(QH,om,
I =70mA
25
V
6
VoH
Output swing
(QL,aI)
1= 70mA
10.8
V
6
Vo L
OutplL!.!.wi ng
(QH,QH)
I =70mA
2.8
V
6
Vo L
Outpwwing
(QL,QU
I =70mA
2.8
V
6
(*)
See fig. 24
(10.5 to 16)
VIN =0
30
4
3
VIN =0
V
60
mA
4
5.5
V
6
0.5
V st
Overload sense threshold
Vom
Muted outputs
1= 70mA Mute or
overload condition
Vx
Gate crossover voltage
f = 1 KHz
0.2
,
0.4
V
6
2.8
V
6
2
V
5
90
mA
7
COMPLETE SYSTEM
10
Supply current
VIN =0
Vof
Output offset voltage
VIN =0
5
mV
7
CMRR
Common mode ripple rejection
VIN =0.5V
f = 100Hz
60
dB
7
l>V R =0.5V
f = 100Hz
60
dB
7
SVR
~ Supply voltage ripple rejection
RL=~
Gv
Voltage gain
Po = 1W
f = 1 KHz
12
dB
7
En
Output noise voltage
B = 20KHz
VIN =0
150
p.V
7
Po
Output power
d =2%
f = 1 KHz
32
W
7
d
Total harmonic distortion
f = 1 KHz
Vo =2V
0.4
%
7
fs
Switching frequency
VIN =2V
VlO = Va
125
KHz
7
fd
Dither frequency
20
Hz
7
1/
Efficiency
85
%
7
Po = 32W
f = 1 KHz
70
(*) Device on for V pin 20 higher than Vtm
793
.....
co
"TI
cpO
""" I~
.....
»
"C
~
o·
0>
r+
o·
rvs
100Kfl
3~2PF ~
2SKn
!~
~f!t
""i!
Ii
II
IN(-)
BALANCED
INPUT
IN(;.)
R7
100
nF
Cl0
,o~h
Rll
0.025n
470nF
.--I~
D?
THERMAL
PROTECTION
;:;:
390PF
10
Kn
10Kn
I
n
~r
~
cs
RS
~
-c:J
R6100Kn
::J
I
I
PONER
MOS
DRIVER
.J..
5-9649/1
*
GND
V/2=AC GROUND
Q1 toQ4=SGSP321
"'::~
CI2
Q3
-I
g
....
N
8
TDA7260
Fig. 7a - P.C. board and components layout of the circuits of fig. 7 (1 : 1 scale)
a
z
t'>
f-
:::J
~
>-'
~
I-'
a
___________________________
~
a
z
t'>
u
«
a:
W
+
~
I
~
'a=
~~~~~~~~
a
z
t'>
________________________~7~/1~3
795
TDA7260
Fig. 8 - Quiescent current
vs. supply voltage
Fig. 10 - Distortion vs. frequency
Fig. 9 - Distortion vs. output power
G-G27911
(0/0 )
I.
r-r--
(mA )
I
RL"21L
1.5
8W
100
COMPLETE
.....-
APPLICATION
60 CIRCU'L
~
II
I-L .....v-
--
TDA7260-t-
20 ONLY
12
10
14
i\,
0.5
v.
16
G-G282
(dB)
~~1~~~
I
+8
o
"-
,
-12
-14
WITH 211.
,
-16
-18
6
12
16 20 24 26 32 Po(W)
B.
Fig. 12 - Dither frequency
versus C(PIN 10)
(HZ)~
,r=:
to'
10'
10
10 4
f (Hz)
Fig. 13
Efficiency vs.
output power
(0'0) ,--,o--,r-ro--,,,---,--,--r-r-.:r:::;..,
• •
LOAD RESISTOR
10,,~.~ft.
I,;
.....
10. _ _
-20
,
,
to'
10
10'
HHz)
Fig. 14 - Power dissipation
vs. output power
Plot r----~.:,-,-'_r,..rT---,-,R"_'t'_t
(W)
4
10'·8m~ft.
+4
-4
-8
0.1
(V)
Frequency re-
Fig. 11
sponse
0.5
'1
0.1
12
C(~F)
AC GND
19
lOA 7260
12 to 17
'
I
COMP.
12
16
20
24
Po (W)
THRESHOLD
5-9650
796
20
24 POUT(W)
Fig. 15 - Suggested application circuit using the TDA7232
preampl ifier / compressor
,v,
r-~~~~-r+-I-t.~l-t~~
~Rt.=211 I--+--H-7++-H--+-l
--llf=lKHz
/.
16
~
L1
'!"
+VS
~
C30
C251- -I
R28
R27
I -I
II
5
6
7
II
In
B
I
~ ~rniWr
R25
rt
91
R20
3
2
0'
UI
....
'"
GI
u
o·
u
:::l
n
a"
4
uii1
03
c:
;::;.
16
...----06
15
14
~~'YP91
~o
t3
1 20
ii1
""en
~i!
:E
'"
"C
~
u
TDA 7260
I~
0'1
UI
5
@,
I\,)
~-~
0
I
~
Cl
ITI., I I
ITI
C19
iiilil
~!
...
~z
+
"'STill
!\i
8-81187
- DC GROUND
V/2 - AC GROUND
U
U
COMPONENT LIST
co
-..J
-..J
I';::"
'"
Rl -39!l
R2-25KU
R3 = 25K!l
R4 = l00K!l
R5 = lK!l
R6 = 100K!l
R7 = 470K!l
RB = 2.7!l
R9=lK!l
RIO = 0.025!l
Rll = 20!l
R12=20!l
R13 - 20!l
R14 =20!l
R15 = (Jumper)
R16 = (Jumper)
R17 = (Jumper)
RIB = (Jumper)
R19-10K!l
R20 = 10K!l
R21 -10K!l
R22 = 47K!l
R23 = 10K!l
R24 = 10K!l
R25 -39K!l
R26 -7.5K!l
R27 =3.9K!l
R28 -t.b,d.
Cl = 390pF
<;2 -390pF
C3 - 150pF
C4 -"22i1F -16V
C5 - 47"F - 16V
C6 = l00nF poi.
C7 = 470"F - 25V
CB = 470"F - 25V
C9 -390pF
Cl0 = 470nF
Cl1 = 390pF
C12 = 100nF
C13 -39OpF
C14 ="100nF
C15 = l00nF
C16 = 390pF
C17 = 4.7"F -16V
C18 - 100nF
C19 = 10"F -16V
C20 - 10"F -16V
C21 - l00nF
C22 - I"F - 16V
C23 - 100nF
C24 = 10"F - 25V
C25 = 330pF
C26 = 220nF
C27 = 10"F - 25V
C28 = 100nF
C29 - 4.7"F - 16V
C30 = 100nF
C31 = 100nF
L1 = 150uH
L2 = 15uH
L3 - 15uH
Ll=33turns
.pO.6mm.
L2, L3 = 14 turn.
.pO.8mm
NOTE
01 = P321 (SGS)
Q2 = P321 (SGS)
03 - P321 (SGS)
04 P321 (SGS)
WITH NO EQUALIZATION FLAT
RESPONSE, G v tot - 42dB
(A) = OPEN
(B) = OPEN
(C) = OPEN
(D) = R = 2.2K!l
(E) = R ·2.2K!l
(F)
(G)
(H)
= OPEN
= JUMPER
= OPEN
(I) - OPEN
(L) = OPEN
1M) = JUMPER
IN) = OPEN
(0) = OPEN
(P)
= R =2.2K!l
R = 2.2K!l
(R) = OPEN
(Q) =
-I
~
.....
N
~
TDA7260
Fig. 17 - P.C. board and components layout of the circuit of fig. 16 (1: 1 scale)
'"
III
N
a
I
rJ>
u
>
I
I
..J
Q.
Q.
:Jill
III
0 0
zZ
I!> I!>
III
>
+
798
UU
0«
UJ
U
..JQ.
m-
I
L8
0
Zt«::J
«Z
I
«
m
U
0
TDA7260
APPLICATION INFORMATION
Fig. 18 - Block diagram
18
17
16
15
POINER
110105
~
DRIVER
13
.10V
9
CIRCUIT DESCRIPTION
BLOCK DIAGRAM
Fig. 18 shows the circuit block diagram. Following are described the single circuit blocks and
their functions.
VOLTAGE REGULATOR
It generates two values of reference voltage,
accessible even on external pins. 10V is the voltage that supplies all the analogic internal blocks.
4,5V (V1) is the voltage value which stands for
ground of the signal inside the chip.
12
10
11
devices. The TSM (two state modulation) system
is used.
The input amplifier is utilized in differential configuration, and refers the input signal to V1 voltage; in such way the chip turns to general use.
On the input amplifier acts a dynamic limiter
circuit, with intervention proportional to supply
voltage avoiding overload and aliasing at lower
Vs (Fig. 19).
Fig. 19 - Duty cycle input dynamic limitation.
Yo
INPUT AMPLIFIER, INTEGRATOR, COMPARATOR WITH HYSTERESIS, N-FET
BLOCK DRIVER
These components implement the control system
main loop, together with the external four power
-----,-----*~--J-----~Yi
5-9651
Fig. 20 - Free running oscillator principle
c
R2
Jl...f1...YA
Rl
L---£:R::'J21---o~
SlJl.... VB
s· 9652
-------------- ~ ~~I~m~\?©~ ____________-=1~1/!..::..=13
799
TDA7260
APPLICATION INFORMATION (continued)
A signal for supplying an external compressor
stage (i.e. TDA7232) is available.
For the effective control loop the feedback
signal is taken from switched points of external
power bridge (before LC output demodulation
filter) and sent to the integrator (see Fig. 20).
The triangle waveform at the integrator output
drives the comparator with a hysteresis, and this
supplies the correct time-intervals to the driving
stages (Fig.21).
Fig. 21
AUDIO INPUT
-- - - - - - -
--J!'---,-------"'o.,;~-----___:r_
FEEDBACK
PARTIALlY DEMODULATED
SIGNAL
( THEORETICAL)
DEMODULATION
- FilTER
(lC7N PASS)
--- --_. - 4iL.------~
.....------__r_
FUllY
DEMODULATED
SIGNAL
5-11'311
SPEAKER
When an audio signal is introduced to the integrator, it generates an offset which varies the
duty cycle and frequency of the switching
output (with no audio signal the duty cycle is
50%). The bridge POWER MOS with the drain
connected to the supply voltage, are driven in
boostrap. The choice of MOS device is suggested
by the high commutation speed and in order
to reduce the chip dissipation. The Mosfets
SGSP321 can be succesfully used. The LC filter
on the bridge output demodulates the signal
and reconstructs the sine wave on the speaker
(see Fig. 22).
Fig. 22
::: J
140---1
.::.:12~/.::.:13::.-_ _ _ _ _ _ _ _ _ _ ~ l~t~~~SJlJt
800
Vs
Ql
5-9654/i
-------------
TDA7260
APPLICATION INFORMATION (continued)
SWITCHING FREQUENCY STABILIZER
It consists of a block which stabilizes the switching frequency of the system; it receives the supply voltage and the input signal amplitude as
inputs, and accomplishes its function by varying
the histeresis thresholds of the comparator.
The purpose of such stabilizer is to reduce the
range of the switching frequency (40KHz < Fsw
< 200K Hz) avoiding greather variations versus
supply voltage, input signal, output current.
{Fig. 23).
SHORT CIRCUIT PROTECTION
It is a comparator having an offset which senses
the current drawn by the power stage by a voltage drop across an external resistor (internal
VTH = 250mV): it acts on the mute circuit.
Fig. 24
DEV.
O-N-
Fig. 23
v-
DEV.
'"'-
t
OFF
I
-r--.l
\30
STABILIZED SYSTEM
\
110
'\
1\
1\
i,
5
BV
10.5V
,
\
t
3
V2
Fig. 25
\
2
V1
,
SYSTEM
50
1
,
I
1\
\
70
o
,
5-9655/1
90
f-- - I -UNSTABILIZED
-,
6:186
6
7
6
9
Vo (peak)
DITHER OSCILLATOR
It is a low-frequency oscillator. Its frequency
(20Hz typ.) is set by an external capacitor; at
th is value it determines a frequency switching
modulation of about 10% around its nominal
value, in order to minimize the problem of the
spurious irradiations of the harmonics at the
switching frequency (EMI).
MUTE
It is a protection circuit which shuts the system
off when the supply voltage is lower than 10.5V
and higher than 16V. The switching-on is further
delayed by an external capacitor. In mute condition the outputs are low (Figs. 24, 25).
DEV.
ON·
DEV.
,
•
I
+-____--.J-j
OFF
4V
5-9656
THERMAL AND DUMP PROTECTIONS
It shuts the device off when the junction temperature rises above 150°C, and it has a hysteresis
of above 20°C typo It acts on the mute circuit ..
The device is protected against supply over- .
voltages{V s = 40V, t = 50ms).
--------------------------- ~~~~~~~~l~~~ ______________________~1~3/~13
801
TDA7270S
MULTIFUNCTION SYSTEM FOR TAPE PLAYERS
NOT FOR NEW DESIGN
The TDA7270S is a multifunction monolithic
integrated circuit in a 16-lead dual in-line plastic
package specially designed for use in car radios
cassette players, but suitable for all applications
requiring tape playback.
It has the following functions:
Motor speed regulator
Automatic stop
Manual stop
Pause
Cassette ejection
Radio - Playback automatic switching.
The circuit incorporates also:
- Thermal protection
Short circuit protection to ground (all the
pins).
Powerdip
(8+ 8)
ORDERING NUMBER: TDA7270S
ABSOLUTE MAXIMUM RATINGS
V.
Supply voltage
Sink peak current at pin 1
Sink peak current at pin 5
Power dissipation at T amb ';;;; 80"C
Storage and junction temperature
11
15
Ptot
Tstg;Tj
20
2
2
1
-40 to 150
V
A
A
W
°C
BLOCK DIAGRAM
~~----------------~
0.3V
Rs
Kmax
The "pause" condition corresponds to V3 <
50mV; in this condition the motor will stop
(Vl -8 < 0.2V), the capacitor C2 on the autostop
circuit (see below) will no longer be charged and
the pin 4 (cassette/radio switch output) will be
pulled high .
CASSIRAD
sw.
l
5-4360
This pin has the following logic.
CassiN
Paul.
Pin 4
Open
Open
Open
Close
Close
Open
Close
Close
> 6V
> 6V
< 1.7V
> 6V
.::o4/",,4~_ _ _ _ _ _ _ _ _ _ _ ~ 1~I;m?et:
B06
CASS "N
Function
motor off /radio on
motor off / radio on
motor on / casso on
pause I radio on
------------
TDA7272
HIGH PERFORMANCE MOTOR SPEED REGULATOR
•
TACHIMETRIC SPEED REGULATION WITH
NO NEED FOR AN EXTERNAL SPEED
PICK-UP
TDA7272 is an high performance motor speed
controller for small power DC motors as used
in cassette players.
Using the motor as a digital tachogenerator
itself the performance of true tacho controlied
systems is reached.
•
VII SUPPLEMENTARY PREREGULATION
•
DIGITAL CONTROL OF DIRECTION AND
MOTOR STOP
•
SEPARATE SPEED ADJUSTMENT
•
5.5V TO 18V OPERATING SUPPLY VOLTAGE
•
lA PEAK OUTPUT CURRENT
•
OUTPUT CLAMP DIODES INCLUDED
•
SHORT CIRCUIT CURRENT PROTECTION
•
THERMAL
TERESIS
•
DUMP PROTECTION (40V)
SHUT
DOWN
WITH
A dual loop control circuit provides long term
stability and fast settling behaviour.
Powerdip
(16 + 2 + 2)
HYSORDERING NUMBER: TDA7272
BLOCK DIAGRAM
3
2
14
11
13
9
tI4-...,..-M";';"'-o 12
0.8
1Kohm
19
June 1988
20
17
18
5,6, 15, 16
8 10
!>- 9485
1/15
807
TDA7272
ABSOLUTE MAXIMUM RATINGS
lj
Tstg
DC supply voltage
Dump voltage (300ms)
Output current
Power dissipation at Tp1ns = 90°C
at Tamb = 70°C
Operating junction temperature
Storage temperature
24
V
40
V
internally limited
4.3
W
1
W
-40 to 150°C
-40 to 150
°c
CONNECTION DIAGRAM
(Top view)
PWM TRIGGER INPUT
20
SPEED ADJ.
(Rl
TIMING RESISTOR
2
19
TIMING CAPACITOR
3
18
J
NC
4
17
SPEED ADJ.
GND
5
16
GND
GND
6
15
NC
7
14
IN VII LOOP
8
13
GND
INVERTING INPUT
MAIN AMPLIFIER
OUT MAIN AMPLIFIER
OUT MOTOR (Ll
9
12
OUT MOTOR (Rl
10
11
+
COMMON S.ENSE OUT
5- 9486
FUNC. CONTROL
(L)
Vs
TO.A7272:: DIS
THERMAL DATA
RthJ-amb
Rthi-Plns
Thermal resistance junction-ambient
Thermal resistance junction-pins
max
max
80
14
-------------------------- ~1~~~~~!PJl----------------------~2/~15
808
TDA7272
TEST CIRCUIT
S1
+VS
S2
V3
C1
220nF
000
pF
2
14
13
50 50
I
11
9
1
TDA7272
19 20
18
I----+--t--c-~
121---+--+-C:::J-..J
17
5-9487
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; Vs = 13.5V unless otherwise specified)
Parameter
Vs
Operating supply voltage
Is
Supply current
Test Conditions
Min.
Typ.
5.5
No load
5
Max.
Unit
18
V
12
mA
OUTPUT STAGE
10
Output current pulse
10
Output current continuous
V 1O -9,12
Voltage drop
10 = 250mA
1.2
1.5
V
V l l- 9,12
Voltage drop
10 = 250mA
1.7
2
V
_____________
~I~~~g~~
1
A
250
mA
___________
~3/~15
809
TDA7272
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
MAIN AMPLIFIER
100
R14
I nput resistance
Ib
Bias current
50
VOFF
Offset voltage
1
VR
Reference voltage
KO
nA
5
2.3
Internal at non inverting
input
mV
V
CURRENT SENSE AMPLIFIER VII LOOP
RS
I nput resistance
Loop gain
TRIGGER AND MONOSTABLE STAGE
VIN 1
I nput allowed voltage
RIN 1
I nput resistance
V TLow
Trigger level
V TB
Bias voltage Ipln 1)
VTH
Trigger histeresis
V2 REF
Reference voltage
-0.7
15
3
500
0
0
V
20
25
10
750
V
800
mV
mV
850
mV
SPEED PROGRAMMING, DIRECTION CONTROL LOGIC AND CURRENT SOURCE PROGRAMMING
V1S,19 Low
Input Low level
V18,19 High
Input High level
118,19
I nput current
V17, 20 REF
Reference voltage
0.7
2
o<
V18,19
<
~~_1_5_______________________ ~~~~~'~~
810
V
2
Vs
735
V
800
p.A
865
mV
__________________________
TDA7272
OPERATING PRINCIPLE
The TDA7272 novel applied solution is based on
a tachometer control system without using such
extra tachometer system. The information of the
actual motor speed is extracted from the motor
itself. A DC motor with an odd number of poles
generates a motor current which contains a fixed
number of discontinuities within each rotation.
(6 for the 3 pole motor example on Fig. 1)
Deriving this inherent speed information from
the motor current, it can be used as a replacement of a low resolution AC tachometer ~ystem.
Because the settling time of the control loop is
limited on principle by the resolution in time of
the tachometer, this control principle offers a
poor reaction time for motors with a low number
of poles. The realized circuit is extended by a
second feed forward loop in order to improve
such system by a fast auxiliary control path.
This additional path senses the mean output
current and varies the output voltage according
to the voltage drop across the inner motor resistance. Apart from a current averaging filter,
there is no delay in such loop and a fast settling
behaviour is reached in addition to the long term
speed motor accuracy.
Fig. 1 - Equivalent of a 3 pole DC motor (a) and typical motor current waveform (b)
lm-
E
L
R
(a)
1m
( b)
BLOCK DESCRIPTION
current magnitude and duration T, are adjustable
by external elements CT and RT.
The principle structure of the element is shown
in Fig. 2. As to be seen, the motor speed information is derived from the motor current
sense drop across the resistors Rs; capacitor CD
together with the input impedance of 500n at
pin 1 realizes a high pass filter.
The monostable is retriggerable; this function
prevents the system from fau It stabilization at
higher harmonics of the nominal frequency.
The speed programming current is generated
by two separate external adjustable current
sources. A corresponding digital input signal
enables each current source for left or right
rotation direction_ Resistor RPl and RP2 define
the speed, the logical inputs are at pin 18 and 19.
This pin is internally biased at 20mV, each negative zero transition switches the input comparator. A 10mV hysteresis improves the noise
immunity.
The trigger circuit is followed by an internal
delay time differentiator.
At the inverting input (pin 14) of the main amplifier the reference current is compared with the
pulsed monostable output current.
Thus, the system becomes widely independent
of the applied waveform at pin 1, the differentiator triggers a monostable circuit which provides a constant current duration. Both, output
For the correct motor speed, the reference current matches the mean value of the pulsed
monostable current. In this condition the charge
of the feedback capacitor becomes constant.
------------- ~ ~~tm?elt ___________
--=5<=/15
811
TDA7272
Fig. 2 - Block diagram
8-11524
The speed n of a k pole motor results:
n =
Normal operation for left and right mode:
each upper TR of the bridge is used as voltage follower whereas the lower, acts as a
switch.
10,435
CT K Rp
and becomes independent of the resistor RT
which only determines the current level and the
duty cycle which should be 1 : 1 at the nominal
speed for minimum torque ripple.
The second fast loop consists of a voltage to
current converter which is driven at pin 8 by
the low pass filter RL • CL • The output current
at this stage is injected by a PNP current mirror
into the inner resistor RB • So the driving voltage
of the output stage consists of the integrator
output voltage plus the fast loop voltage contribution across RB .
The power output stage realizes different modes
depending on the logic status at pin 18 and 19.
~6/~1~5
812
_______________________
Stop mode where the upper half is open and
the lower is conductive.
High impedance status where all power elements are switched-off.
The high impedance status is also generated when
the supply voltage overcomes the 5V to 20V
operating range or when the chip temperature
exceeds 150°C.
A short circuit protection limits the output
current at 1.5A. Integrated diodes clamp spikes
from the inductive load both at Vcc and ground.
The reference voltages are derived from a common bandgap reference. All blocks are widely
supplied by an internal 3.5V regulator which
provides a maximum supply voltage rejection.
~1~~~~~
__________________________
TDA7272
PIN FUNCTION AND APPLICATION
INFORMATION
Pin 1
Trigger input. Receives a proper voltage which
contains the information of the motor speed.
The waveform can be derived directly by the
motor current (Fig. 3). The external resistor
generates a proper voltage drop. Together with
the input resistance at pin 1 [ RIN (1) = 500n ]
the external capacitor CD realize a high pass
filter which differentiates the commutation
spikes of the motor current. The trigger level is
OV.
The biasing of the pin 1 is 20mV 'with a hysteresis of 10mV. So the sensing resistance must
be chosen high enough in order to obtain a
negative spike of the least 30mV on pin 1, also
with minimum variation of motor current:
30mV
Rs;;;' - - - - L':.I MOT min.
Such value can be too much high for the preregulation stage V-I and it could be necessary to
split them into 2 series resistors Rs = RSl + RS2
(see fig. 4) as explained on pin 8 section.
Fig. 4
Fig. 3
Co
5-9495
VII
REG
(mV)
VpIN1
5-9497
20
The information can be taken also from an
external tachogenerator. Fig. 5 shows various
sources connections:
10
, (s)
the input signal mustn't be lower than -O.7V.
5-9496
Fig. 5
TTL-MOS
5- 9498/1
__________________________
PHOTOTRANSISTOR
TACHO
~!~~~~
MAGNETIC
TACHO
_____________________
~7~/15
813
TDA7272
Pin 2
Fig. 7
Timing resistor. An internal reference voltage
(V2 = 0.8V) gives possibility to fix by an external resistor (R T ), from this pin and ground,
the output current amplitude of the monostable
circuit, which will be reflected into the timing
capacitor (pin 3); the typical value would be
about 50tlA.
10
B
Fig.6
.------12
CT
3
For compensating the motor resistance and
avoiding instability:
5- 9 4 99
..:
RMOTOR
9
Rs ""
Pin 3
Timing capacitor. A constant current, determined by the pin 2 resistor, flowing into a capacitor between pin 3 and ground provides the
output pulse width of the monostable circuit,
the max voltage at pin 3 is fixed by an internal
threshold: after reaching this value the capacitor
is rapidly discharged and the pulse width is
fixed to the value:
Ton = 2.88 RT CT (Fig. 6)
The optimization of the resistor Rs for the
tachometric control must not give a voltage too
high for the V/I stage: one solution can be to
divide in two parts, as shown in Fig. 8, with:
RM
RS2 = - - and RSl + RS2 ;;;.
10
;;;.
30mV
-/::"-I mot
- -min
--
(see pin 1 sect.)
Pin 4
Not connected.
Fig.8
Pin 5
Ground. Connected with pins 6, 15, 16.
Pin 6
Ground. Connected with pins 5, 15, 16.
B
10
Pin 7
Not connected.
Pin 8
Input V/I loop. Receives from pin 10, through
a low pass filter, the voltage with the information of the current flowing into the motor and
produces a negative resistance output:
5-9501
Rout = -9 Rs (Fig. 7)
::;8/~l.::.5 _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~I;mgr~:£~
814
-------------
TDA7272
The low pass filter R L , C L must be calculated in
order to reduce the ripple of the motor commutation at least 20dB. Another example of
possible pins 10-8 connections is showed on
Fig. 9. A choke can be used in order to reduce
the radiation.
Fig. 10
Fig. 9
10
5-9502
Pin 10
4.7}JF
I
5-950311
Pin 9
Output motor left. The four power transistors
are realized as darlington structures. The arrangement is controlled by the logic status at
pins 18 and 19.
As before explained (see block description), in
the normal left or right mode one of the lower
darlington becomes saturated whereas the other
remains open. The upper half of the bridge
operates in the linear mode.
In stop condition both upper bridge darlingtons
are off and both lower are on. In the high output
impedance state the bridge is switched completelyoff.
Connecting the motor between pins 9 and 12
both left or right rotation can be obtained. If
only one rotation sense is used the motor can be
connected at only one output, by using only the
upper bridge half. Two motors can be connected
each at the each output: in such case they will
work alternatively (See Application Section).
The internal diodes, together with the collector
substrate diodes, protect the output from inductive voltage spikes during the transition
phase (Fig. 10)
Common sense output. From this pin the output
current of the bridge configuration (motor
current) is fed into Rs external resistor in order
to generate a proper voltage drop.
The drop is supplied into pin 1 for tachometric
control and into pin 8 for V II control (See pin 1
and pin 8 sections).
Pin 11
Supply voltage.
Pin 12
Output motor right. (See pin 9 section)
Pin 13
Output main amplifier. The voltage on this pin
results from the tachometric speed control and
feeds the output stage.
The value of the capacitorC F (Fig. 11),connected
from pins 13 and 14, must be chosen low enough
in order to obtain a short reaction time of the
tachometric loop, and high enough in order to
reduce the output ripple.
A compromise is reached when the ripple voltage
(peak-to-peak) V ROP is equal to 0.1 VMOTOR:
.
with VR1P =
V FEM
+ IMOT • RMOT
and
10
815
TDA7272
with duty cycle
50%. (See pin 2-3 section)
Fig. 11
Vary the RA and CA values in order to obtain
at pin 13 a voltage signal with short response
time and without oscillations. Fig. 13 shows
the step response at pin 13 versus RA and CA
values.
Fig. 13
13
C A SHORTED
RA
TOO LARGE
13
Fig. 12
R A RIGHT
13
14
20
17
s- 9507
13
I
CA SHORTED
RA TOO SMALL
13
5-9506
CA TOO SMALL
In order to compensate the behaviour of the
whole system regulator-motor-Ioad (considering
axis friction, load torque, inertias moment of
the motor of the load. etc.) a RC series network
is also connected between pins 13 and 14 (Fig.
12). The value of CA and RA must been chosen
experimentally as follows:
Increase of 10% the speed with respect to the
nominal value by connecting in parallel to Rp
a resistor with value about 10 time larger.
~lO~/~15~
816
_____________________
~I~~~~~~
13
RA RIGHT
CA RIGHT
S-9508
__________________________
TDA7272
Fig. 14
Fig. 15
3
s- 9 50~
5-9509
Pin 14
Inverting input of main amplifier. In this pin the
current reference programmed at pins 20, 17 is
compared with the current from the monostable
(stream of rectangular pulses).
Fig. 16
In steady-state condition (constant motor speed)
the values are equal and the capacitor CF voltage is constant.
This means for the speed n (min·1) :
n
=
10.435
CT
k Rp
where Uk" is the number of collector segments.
(poles)
Fig. 17
The non inverting input of the main amplifier is
internally connected to a reference voltage (2.3V).
Pin 15
Ground.
Pin 16
Ground.
Pin 17
Left speed adjustment. The voltage at this pin
is fixed to a reference value of 0.8V. A resistor
from this pin and ground (Fig. 14) fixes the
reference current which will be compared with
the medium output current of the monostable
in order to fix the speed of the motor at the
programmed value. The correct value of Rp
would be:
.
10.435
Rp=----
CT • k • n'
Fig. 18
n = motor speed, (min ·1)
k = poles number
------------- ~ !~tm?:1~~~ ___________..!1~1/t.!.::15
817
TDA7272
The control of speed can be done in different
way:
Fig. 19
speed separately programmed in two senses
of rotation (Figg. 14-15);
only one speed for the two senses of rotation
(Fig. 16);
- speeds of the two senses a bit different (i.e. for
compensating different pulley effects) (Fig. 17);
- speed programmed with a DC voltage (Fig. 18)
i.e. with DA converter;
fast forward, by putting a resistor. In this case
it is necessary that also at the higher speed
for the duty cycle to be significatively less
than 1 (see value of RT , CT on pin 2, pin 3
sections).
Fig. 19 shows the function controlled with a J.LP.
CONDITION
Pin 18
Right function control. The voltages applied to
this pin and to pin 19 determine the function,
as showed in the table.
The typical value of the threshold (L-H) is 1.2V.
OUTPUT FUNCTION
Pin 18
Pin 19
L
H
L
H
L
L
H
H
OUTPUT VOLTAGE
Pin 12
STOP
LEFT
RIGHT
OPEN
Pin 19
Left function control. (See pin 18 sect).
Pin 9
LOW
LOW
REG
LOW
REG
LOW
HIGH IMPEDANCE
Pin 20
Right speed adjustment. (See pin 17 sect).
Fig. 20 - Typical application
ilF
Co
12
E
1B 19
A (}--I----'
5.6.15,16
B 0--1-----'
5·9488
~12~/~15~_ _ _ _ _ _ _ _ _ _ _ ~~~~~~~~:~~~
818
_ _ _ _ _ _ _ _ _ _ _ _ __
TDA7272
Fig. 21 - Tacho only speed regulation
F
lor:
I
c
5-9489/1
Fig. 22 - One direction reg. of one motor, or alternatively of two motors
+Vs
An--+----J
F
Bn--+-----'
5-9490
_________________________
~~~~~~
______________________~1~3/~15
819
TDA7272
Fig. 23 - P.C. board and compqnents layout of the circuits of Figg. 20, 21, 22
E
D
GND
GND
F
B
A
c
APPLICATION SUGGESTION (Fig. 20,21,22) - (For a 2000 r.p.m. 3 pole DC motor with RM = 160)
Compo
Recommended
value
RSl
10
RS2
1.50
RL; CL
22KO -68nF
68nF
Co
RT ;
~
Rpl; Rp2
15KO -47nF
47KO trim.
Polyester
100nF
CF
RA; CA
220KO - 220nF
Allowed range
Purpose
820
If smaller
Min.
Current sensing
tacho loop.
Max.
Tacho loop do
not regulate.
0
Motor regulator;
undercompens.
0
RMOT/9
Pulse transf.
33nF
100nF
Current source
programming
to obtain a
50% duty cycle.
6KO
30KO
Curro sensing VII
loop.
Instability may
occur.
Spike filtering.
Slow VII regulator High output
ripple ..
response.
High speed.
Set of speed.
Low speed.
Optimization of
integrator ripple
and loop response
time.
Lower ripple,
Higher ripple,
slower tachofaster response.
regulator response.
Fast response with Depending on electromechanical
no overshoot.
system.
_______________________
~14~/_15
If larger
~~~~~T~~
0
10nF
470nF
10KO
10nF
10MO
lj.1F
__________________________
TDA7272
Fig. 24 - Speed regulation
versus supply voltage
(Circuit of Fig. 20)
0.4
Fig. 25 - High current TDA7272 + 2 x L149 application
H+H++-+++-1-+-"---Lt-1
0.2 t~§/§~$~$~:O'O' '"'
-0.2 1-+-1-+-+-1-+-+-++-1-+.-1-+--1
1-+-1-+-+-++-+-++-1-++-1-+--1
0.7
1.2
-0.4
10
15
~~------~----~~~
5- 9491
Fig. 26 - In connection with a presettable counter and I/O peripheral the TDA7272 controls the speed
through a D/A converter
Z8430 eTe
~----------------417
Z8420 PIO
5-9493/1
----,------------ ~ ~~I;mW£l~JI--------------=1;.:;.5:...:/l;.:;.5
821
~
SGS-1HOMSON
~.,L [K'A]D©OO@rn[Lrn©'U'OO@[R!]D©~
TDA7274
LOW-VOLTAGE DC MOTOR SPEED CONTROLLER
•
WIDE OPERATING VOLTAGE RANGE (1.8
to 6V)
•
BUILT-IN
(0.2V)
•
LINEARITY IN SPEED ADJUSTMENT
•
HIGH
•
LOW NUMBER OF EXTERNAL PARTS
microcassettes, radio cassette players and other
consumer equipment. It is particulary suitable
for low-voltage applications. .
LOW-VOLTAGE REFERENCE
STABILITY
VS.
TEMPERATURE
The TDA 7274 is a monolithic integrated circuit
DC motor speed controller intended for use in
Minidip Plastic
ORDERING NUMBER: TDA 7274
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Motor Current
Power dissipation at T amb = 25°C
Storage and junction temperature
6
700
1.25
-40 to +150
.,
V
mA
W
°C
APPLICATION CIRCUIT
~-------1-----1-----------'----~--~+Vs
C2
Vs = 3.0V
RM = 4.9n
~-9552
RT = 220n
Eg = 1.65V
1M = 100mA
VM = RMIM+E g =2.14V
June 1988
1/6
823
TDA7274
SCHEMATIC DIAGRAM
OUT
100pA
~--~----~----------~--~--~~GNO
8
S-955311
CONTROL
CONNECTION DIAGRAM
(Top view)
N.C.
N.C.
2
6
OUT
4
5
GNO
5.0955411
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
.:.,:2/__
6 _ _ _ _ _ _ _ _ _ _ _ ~ !g~;m~~~lt
824
max
100
°C/W
------------
TDA7274
Fig. 1 - Test circuit
~-9555/1
ELECTRICAL CHARACTERISTICS
(Refer to test circuit, Vs
= 3V,
Tamb
= 25°C unless other·
wise specified)
Parameter
Vs
Test Conditions
Supply voltage range
Vref
Reference voltage
Iq
Qiescent current
Min.
Typ.
1.8
1M = 100mA
Id (Pin 6)
Quiescent current
K
Shunt ratio
1M = 100mA
V sat
Residual voltage
t. Vref It. V s
Vref
0.18
Max.
Unit
6
V
0.20
0.22
V
2.4
6.0
mA
pA
120
50
55
-
1M = 100mA
0.13
0.3
V
Line regulation
1M = 100mA
V s = 1.8 to 6V
0.20
%/V
Voltage characteristic of
shut ratio
1M = 100mA
Vs = 1.8 to 6V
0.80
%/V
t.Vref 1t.IM
Vref
Load regulation
1M = 20 to 200mA
0.004
%/mA
A!5..1t.IM
K
Current characteristic of
shut ratio
1M = 20 to 200mA
-0.03
%/mA
t.Vref
- It.Tamb
Vref
Temperature characteristic
of reference voltage
1M = 100mA
Tamb = -20 to +60°C
0.04
%/OC
t.K /t.Tamb
K
Temperature characteristic
of shut ratio
1M = 100mA
Tamb = 20 to +60°C
0.02
%/OC
~/t.Vs
K
_________________________
~~~~~~~~
45
_______________________~3/6
825
TDA7274
Fig. 2 - Quiescent current
vs. supply voltage
6-6179
I.
(mY)
230
Im~l00mA
Fig. 4 - Shunt ratio vs.
supply voltage
(;·6181
r-,-,-,-,--,--,--,--,--,--rM
f-t-+-+-+-+-+-+-+-+-+--I-l
Vr.t
I
I
ImA 1
Fig. 3 - Reference voltage
vs. supply voltage
f-+-+-+-+-+-+-+-+-+-+-+-1
210f-t-+-+-+-+-+-+-+-+-+--I-l
210 f-t-+-+-+-+-+-+-+-+-+--I-l
_f-
2°om$$w~I!m
l- f-
f-f-HHl m=200mA -f+I'-t-H
190f-f-HH 1m =100mA --l+t-t-H
im=50mA H-t-t--t--,
--
II
,-.//
Im"50mA~2,
I
-f- r"'""_ f - -
so
~
...,f1':
f- -
••
Im=lOOmA
lm=200rnA---'
I I
6I1SIV)
Fig. 5 - Reference voltage
vs. load current
Fig. 7 - Minimum supply
voltage (typical) vs. load
current
Fig. 6 - Shunt ratio vs.
load current
vrvl ,..-...,--,..--.--,---.--,--":''::::'"
'5
(mY)
'"
..
210
f-+-f-+-+--+-+--+--i
200
f---.;j..-~-+--F"'I--+--+--i
190 f-+-f-+-+--+-+---+--i
100
200
300
~
so
4.
.
115 =4.5\1
liS: 3¥
r--
i
lOO
200
Im!rnA)
100
\lr.t
ImA 1
200
300
Im(mAI
Fig. 10 - Reference voltage
vs. ambient temperature
Fig. 9 - Quiescent current
vs. ambient temperatur~ ""
I.
\
11m ,---,_+---+_+--+_-j
J...r---...,--I--
r- r::::: ~
100
Fig. 8 - Saturation voltage
vs. load current
',.
_
"
ImlrnA)
1m' I
f-~
••_,.L,_.~__
..-.+-~-+--~~
J
r--r--,r--r-r--r-r---";:-':.::"::..,'
1'1
IIS:JII
Im=100mA
"".3Y
IIS=J'"
Im3100mA
500
.00
r--....
'00
/'" V
20 0
'/
-
210 f--t--f--t--t--t--t--+---!
zoo f--i=~~+-l-"o:f'=I---+---l
r- r-
180 f--t--f--t--t--t--t--+---!
10 0
/'
100
~4/~6
100
300
Im(mAI
-loa
_______________________
826
-zo
-40
20
40
1\0
80
-20
0
20
40
60
80
TambC"C)
lambl-C I
~1~~~~~
_________________________
TDA7274
Fig. 11 - Application circuit
r-------~----~--------_.----~--{)+vs
cz
v, RM
RT
Eg
1M
VM
~-955l
3.0V
= 4.90
• 2200
• lo65V
• l00mA
- RM 1M + E. - 2.14V
Fig. 12 - P.C. board and components layout of the circuit of fig. 11 (1 : 1 scale)
OUT
+vs
GND
CS-0268
Fig. 13 - Speed variations
vs. supply voltage
(i-I'A
.N
(
N
(rpm)
..
N
Fig. 14 - Speed variations
vs. motor current
)
Fig. 15 - Speed variations
vs. ambient temperature 6-'110
I-++I-++I-+++-+++-+++-I{r~ml ~ I~H--I-H--I-H+H-I-H-I-+-Ilr:"..
A.
N
('10)
.ZOO
10
10
2100
.,
1900
-10
~t~tt±twtwt±:j"oo
1-++1-++1-+++-+++-+++-12100
.000
.,
1-++1-++~o.I..H++-+++-I2000
H--I-8.....I-I-"'I"'H-I-H-f-+-I ....
H-+H+H-I-+-I-++-1H-+-11.Z0
1800
·10
....
·zo
VstVI
,.
100
ISO
1m (moll
"0
------------- Gil. ~~tmtl~1£ ___________-=.:..=5/6
827
TDA7274
APPLICATION INFORMATION
Fig. 16
1M = Motor current at rated speed
RM = Motor resistance
Eg = Back electromotive force
VM = 1M • RM + Eg
_1M
Eg = RT Id + 1M
RT
(I(' -
The value of RT is calculated so that
R M ) + V ref
RT (max.)
RB
RT
1
Rs
Rs
K
If RT
[1 + - + - (1 +_. )]
Rs has to be adjusted so that the applied voltage
V M is suitable for a given motor, the speed is
then linearly adjustable varing RB .
(max.)
+3V
828
K • RM ,
• RM (min.)
instability may occur.
The values of C 1 (4.7 J.lF typ.)and C2 (1 J.lF typ.)
depend on the type of motor used. C 1 adjusts
WOW and flutter of the system. C2 suppresses
motor spikes.
Fig. 17 - 3V stereo cassette miniplayer with motor speed control
100.0.
>
< K(min.)
TDA7275A
MOTOR SPEED REGULATOR
ADVANCE DATA
•
EXCELLENT VERSATILITY IN USE
•
HIGH OUTPUT CURRENT (UP TO 1.5A)
•
LOW QUIESCENT CURRENT
•
LOW REFERENCE VOLTAGE (1.32V)
•
EXCELLENT PARAMETERS STABILITY
VERSUS AMBIENT TEMPERATURE
•
START/STOP FUNCTION (TTL LEVELS)
•
DUMP PROTECTION
The TDA7275A is a linear integrated circuit in
minidip plastic package. It is intended for use as
speed regulator for DC motors of record players,
tape and cassette recorders.
The dump protection make it particularly
suitable for car rad io applications.
Minidip
(4+ 4)
ORDERING NUMBER: TDA7275A
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Peak supply voltage (for 50ms)
Maximum output current
Operating temperature range
Total power dissipation Tamb = 70°C
Tp1ns = 70°C
19
45
V
1.5
-30 to 85
1
A
°C
W
W
4
V
SCHEMATIC DIAGRAM
3
--~------~--------------------~'--------------O
2
5-966"1
June 1988
1/4
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
829
TDA7275A
CONNECTION DIAGRAM
(Top view)
TORQUE RESISTOR
START ISTOP INPUT
2
GND
POWER SUPPLY
4
MOTOR
5- 9665
THERMAL DATA
Rthj .... mb
Rthj-!)lnS
Thermal resistance junction-ambient
Thermal resistance junction-pins
max
max
80
20
Fig. 1 - Test circuit
------~------._------------~--~~uvs
J!oonF
I
I
s- 9666/1
fSAl
""2/'-'4_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~tm&~~lt
830
---------------
TDA7275A
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, Vs = 12V unless otherwise specified, refer
to test circuit)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
18
V
1.35
V
Vs
Supply voltage range
Vref
Reference voltage
1M = O.lA
Iq + Id
Total quiescent current
1M = O.lmA
2
mA
Id
Ou iescent cu rrent
1M = O.lmA
1
mA
Ims
Starting motor current
l!.Vref
Vref
V4
Saturation voltage
1M = 0.5A
K = IM/IT
Reflection coefficient
1M = O.lA
l!.K/l!.Vs
8
= -50%
1M = O.lA
Vs =8V to 16V
K
1.05
1.22
A
1
18
1.7
2
20
22
V
0.5
%IV
l!.K/l!.IM
--K
1M = 25 to 200m A
-0.05
%/mA
l!.K/l!.T
1M = O.lA
Top = -30 to 85°C
0.02
%/oC
Line regulation
Vs = 8V to 16V
1M = O.lA
0.04
%IV
Load regu lation
1M = 25 to 200mA
-0.01
%/mA
l!.Vref/l!.T
-Vref
Temperature coefficient
1M = O.lA
Top = -30 to 85°C
0.02
%/oC
V2
Motor "Stop" (Acc. Following
data or grou nded)
1
V
12
Motor "Stop"
-0.05
mA
V2
Motor "Run" (Acc. following
data or open
1.5
V
12
Motor "Run"
-0.1
mA
-K-
l!.Vrefll!.Vs
Vref
l!.Vrefll!.IM
Vref
V2 = lV
V2 = 1.5V
------------- Gii.1~tmo~ ___________
....;3:.:....;./4
831
TDA7275A
Fig. 2 - Application circuit
+vso--.---.-------....----,
I
- RTtyp. = Ktyp. RMtyp. if RT > Kmin RMmin instability may accur.
- A diode across the motor could be necessary with certain kind of motor.
Fig. 3 - Quiescent current
vs. supply voltage
Fig. 4 - Speed variation vs.
supply voltage
Fig. 5 - Speed variation vs.
torque (Vs= 12V)
6'6.1118
- - .-- . ---t9.7m~
. ...,~. g
(RPM )
/i ,
I I
I I
(RPM )
.~.
Vs &12V
2200
Imc.O.1 rnA
II,'
1800
13.'
1400
2500
,
.~
Vs:.12V
4.5-
I
-r-1-:---
1//,
2000
I
1000
b
~
..
600
2
832
4
6
8
10
12
14 16 Vs (V)
2
1500
4
6
8.
10 12
14 16
18
v. (V)
0.8
1.6
2.4
3.2
4 (mWml
TDA7276
SPEED REGULATOR FOR SMALL DC MOTOR
PRELIMINARY DATA
The TDA7276 is a monolithic integrated circuit
in 4 + 4 lead minidip plastic package designed for
DC motors speed regulation in tape and cassette
recorders, toys, etc.
High temperature stability
High power capability
- Low number of external parts
It offers speed regulation versus supply voltage
temperature and load changes better than conventional circuits built with discrete components.
Main features are:
Excellent versatility in use
High output current (up to 1A)
Low reference voltage (1.25V)
Minidip
(4+ 4)
ORDERING NUMBER: TDA7276
ABSOLUTE MAXIMUM RATINGS
v.
'0
Ptot
Ptot
Tstg , 1j
Supply voltage
Output current
Total power dissipation at Tamb = 70°C
Total power dissipation at Tp1ns = 70°C
Storage and junction temperature
20
V
1.2
1
A
4
-40 to 150
W
W
°c
APPLICATION CIRCUIT
+Vs
TDA7276
4~~~~~--4--~·
1M
5-965711
June 1988
1/4
833
TDA7276
CONNECTION DIAGRAM
(Top view)
8
7
GND
5
S-9792
THERMAL DATA
Rthj-p;ns
Rthl-amb
max
max
Thermal resistance junction-pins
Thermal resistance junction-ambient
20
80
TEST CIRCUIT
TDA 7276
4 t----+----4~-f
5-6-7-8
_2~/4________________________ ~!~I;~~~
834
--------------------------
TDA7276
ELECTRICAL CHARACTERISTICS (Refer to the test circuit,
Parameter
Tamb
Test Conditions
= 25°C,
Min.
Vln
Supply voltage range
IM=O.lA
Vref
Reference voltage
(between pins 1 and 4)
1M =O.lA
Id
Quiescent drain current
1M = 100llA
IMS
Starting current
Vs = 2.5V
!:NreflVref = -50%
0.5
I MS
Starting current
Vs= 5V
6VrefIVref = -50%
1.0
K = 1M/IT
Reflection coefficient
IM=O.lA
~/6Vs
Vs = 6V to 18V
6K
1("/61M
1M = 25 to 400mA
6K
--f6T
K
Tamb = -20 to 70°C
6Vref /
- - 6Vs Line regulation
Vref
Vs = 6V to 18V
6Vref /
- - 61M
Vref
Load regu lation
1M = 25 to 400mA
6Vre f /6T
Vref
Temperature coefficient
Tamb = ·20 to 70°C
K
tNreflVref = -5%
18
= 6V)
Max.
Unit
18
V
1.25
1.35
V
1.1
2.1
mA
Typ.
2.5
1.1
1M = O.lA
Vs
A
0.8
A
20
22
-
0.45
%IV
0.005
%/mA
IM=O.le,
0.02
%foC
IM=O.lA
0.02
%/V
0.009
%/mA
0.02
%("C
I M =O.lA
------------- ~ 1~I;m?lI~lt ____________
-"-'3/4
835
TDA7276
PRINCIPLE OF OPERATION
The device acts an emf speed regulator providing
correction for the internal losses of the motor.
The voltage across Rs is kept constant by the Ie
and equal to V ret = 1.25V typo (see application
circuit) .
The current through the resistance RT is:
therefore:
RT
• [ - (1 +
Rs
where:
Id
1M
K
IRS
Rs
quiescent drain current (1.1 mA typ.)
motor current
reflection coefficient (20 typ.)
Eg being the motor's back electromotive force
and RM its internal resistance; the voltage
across the motor itself will be:
836
+ 1] + RT Id
Motor's speed ,will be independent from resisting
torque if Eg doesn't depend on 1M , then will do:
V ret
= ---
.:..:4/-'4_ _ _ _ _ _ _ _ _ _ _ _ _
I
-J
K
RT = K RM (if RT > Kmln RM min oscil·
lations may occur) - Back emf rated to th,~
wanted speed can be selected acting to Rs .,
Rs variations will lead to an hyperbolic adjustment of the speed:
Rs
i..U !~~~m~~~ -------------
TDA7282
STEREO LOW VOLTAGE CASSETTE PREAMPLIFIER
•
LOW ON/OFF POP NOISE
•
LOW OPERATING VOLTAGE
• VERY LOW DISTORTION
The TDA7282 is a monolithic integrated circuit
intended for stereo cassette players.
The TDA7282 is assembled in 8 leads plastic
minidip.
Minidip Plastic
SO-SJ
ORDERING NUMBER: TDA7282 (Minidip)
TDA7282D (50.8)
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage and junction temperature
Total power dissipation at Tamb = 70°C
10
-40 to +150
400
STEREO PREAMPLIFIER FOR CASSETTE PLAYERS
Rl
+Vs
R2
4.75, .
rOUT
10K
4_;. _
1OKTOUT
5.6K.Jl 150K.!l.
5 - 9638/1
June 1988
1/6
837
TDA7282
CONNECTION AND BLOCK DIAGRAM
OU~UT
I,
IN~INP.12
OUTPUT
B
N~~I~\\
3
6
-Vs
4
·5
IN'lJNI?
~:p'I~V.
5-3590
TEST CIRCUIT
+Vs
+Vs
22KJl.
f--+-------,
R4
20KJl.
R1
8
3
f
4.7 P F
C3
TDA7282
OUT
RL
5-9637
THERMAL DATA
Rth j ....mb
Thermal resistance junction-ambient
....;2''-6_ _ _ _ _ _ _ _ _ _ _ _ ~ !~n'~
838
max
200
-------------
TDA7282
ELECTRICAL CHARACTERISTICS (Vs
3V,
Tamb
= 25°C, f = 1KHz, Gv = 40dB, RL =
loKn, Rs =600n unless otherwise specified)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
9
V
Vs
Supply voltage
Id
Supply cu rrent
1.5
3
rnA
Ib
I nput bias cu rrent
280
500
nA
los
I nput offset cu rrent
20
iP.
Vas
Input offset voltage
0.5
mV
VaDe
Qu iescent voltage
1.1
V
Vo
Output voltage
650
mV
THD
Total harmonic distortion
f
f
f
=
=
=
1.8
THD
=
1%
550
0.08
100Hz
1 KHz
Va
= 300mV
0.07
10KHz
=
%
0.5
%
0.1
%
80
dB
Gv
Open loop voltage gain
Gv
Closed loop gain
40
dB
Channel balance
0.5
dB
1.5
p,V
65
dB
45
dB
f
eN
Total input noise voltage
Bw
Cs
Channel separation
f
=
Vo
=
1 KHz
= 22KHz
68
to 22KHz
1 KHz
= 30mV
SVR
Supply voltage rejection
RIN
Input resistance
100
K11.
Ro
Output resistance
15
11.
f
100Hz
---------------------------~~~~~~?rr~:~~~
36
________________________~3/~6
839
",(DA7282
APPLICATION INFORMATION
Fig. 1 - Stereo preamplifier for cassette players
+Vs
R1
+Vs
R2
4.7~
10K Jlr O U T
22fJF
I'
4'~
_
1 0 K J l r OUT
5.SKJl 150K.!l.
5 - 9638/1
Fig. 2 -
p.e and components layout of the circuit of
6_ _ _ _ _ _ _ _ _ _ _ _
.:::;4/c:
840
Fig. 1 (1: 1 scale)
~ ~~~;m&~I9J1-------------
TDA7282
APPLICATION INFORMATION
(continued)
Fig. 3 - Quiescent current
vs. supply voltage
'0 r-r..,.-,..,rr...r-r..,.-..,-rr-rf'-'r'-,
(rnAlf-+-+-H-++-IH-+-+-t-++-H-i
Fig. 4 - DC output voltage
vs. supply voltage
"ODe rr-r-,..,..,.-..,-rr-r-,..,..,.-+nc"
(V) f-+++-t-++-H++-I-+-+-H'-l
2.21-++H++-I-+++-1++I-+--1
2.0 f-+-+-H-++-H-+-+-t-+-::bH4
1.8 I-++H++-H~+-1"'f+I-+--1
1.6 f-+-+-H::;4;o-t""Ft-+-+-t-++-H-i
1.4I-+-I"''F-t++-I-+++-1++I-+--1
1.2 f-+-+-+-t-++-H-+-+-t-++H-i
2.6 f-+++-t-++-H++-If7f--+-H--i
2.2 f-+++-t-++-H--b+-l-+-+-H--i
1.8 f-+++-I-++-b'f++-I-+-+-H--I
1.4 f-+++-I-bo"l-H++-I-+-+-H--I
0.6 f-+T+-I-++-H-++-t-+-+-H-I
\ls(Y)
380
f-+++-t-++-H++-I4-¥H--1
340
f-+++-t-++-f-++-l7i4+-H--1
320
f-+-+-H-++-H4-+-t4+-f-+--1
300
H-++-I-+-¥H-++-f-+-+-H-I
260 H++-1++H++-I-++H-I
lIsey)
8 'Is(Y)
Fig. 6 - Distortion versus
output level
THO rr,..,.....,-,-,-rr-r-"rr-r"r'T,
("to)
Fig. 5 - Input bias current
vs. supply voltage
1-+++-1++-1-+++-1++1-+--1
Fig. 7
frequency
Distortion
vs.
THO,.,-rrTTTI11~TT1TmrrrTTTTT1Tr-+rw.nn
("10)
H'-HtItffi--t+H+llltI-+++ttf1lf-+l+HllIl
f,,1KHz
0.181-+++-1++-1-+++-1++-11-+--1
0.16
f-+-+-+-t-++-H++-I4-HH-I
0.141-+++-1++-1-+++-1+++1-+--1
0.12 f-+--f"~-++-H++-I4-+1-H-I
0.10H+-P-k-t+H++I-+-J-+-1-1
0.08
0.01
r-~+tIM:;t++1I=+mJ+~m
0.06
H-+ttt+ttl-+-t+I+lllt+++tIflll-+l+HllIl
0.05 H-tttttttt--t-tttffllt--++ttIlllf--+f+llHi/
O.08'r:t+t:~$$=I:$$f:t+t:4~
a.06r
0.oloH++-II-+-+-H4+-H-+-+-t-l
0.02H++-1I-++H++I-+++-1-1
100
200
300
1000
SOO
600
10
Vo(mV)
10'
t(Hz)
Fig. 8 - NAB response of
the circuit of Fig. 1
Fig. 9 - Supply voltage
rejection vs. frequency
G,,.,-rrTTTI11~TT1TmrrrTTTTT1Tr~nnnn
.VR r-T-rrmm-r-rnnnr..,.-rrrrrnr"+ffltnn
(dB)H-+ttltffi-++H+llltI-+t+ttHt+ttHttlI
50
(00l H-+tHtt!l-+-t+ltltIt-++++IfIII-+I+HHtI
H-++++HII"'d-+H.JHII.I-++++IHIf--+f+llHi/
50
10
10'
H-t+ttttIt-J,."Fttffllt-4++t1lllf--+f+llHi/
10
10'
K)4
f(Hz)
------------- ~ !~tm~AI------------5~/6
841
TDA7282
Fig. 10 - Stereo cassette player with motor speed control
+3Y
IOO.n.
________________________
~6/~6
842
~!~1~~~~
__________________________
TDA7300
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
PRELIMINARY DATA
•
•
•
•
•
•
•
•
SINGLE SUPPLY OPERATION
FOUR STEREO INPUT SOURCE SELECTION
MONO INPUT
TREBLE, BASS, VOLUME AND BALANCE
CONTROL
FOUR INDEPENDENT SPEAKER CONTROL (FRONT/REAR)
ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
VERY LOW NOISE AND VERY LOW
DISTORTION
POP FREE SWITCHING
Control is accomplished by serial bus microprocessor interface.
The AC signal setting is obtained by resistor
networks and analog switches combined with
operational amplifiers.
The results are: low noise, low' distortion and
high dynamic range_
DIP-28 Plastic
The TDA 7300 is a volume, tone (bass and
treble) and fader (front/rear) processor for high
quality audio applications in car radio and Hi-Fi
systems.
ORDERING NUMBER: TDA 7300
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Total power dissipation (Tamb = 25°C)
Operating ambient temperature
Storage temperature
18
2
-40 to 85
-55 to 150
BLOCK DIAGRAM
4
13
17 18
TDA7300
(Ll
(L)
INPUTS
FRONT
REAR
15
(L)
MONO
INPUT
12
11
FRONT
10
(R)
INPUTS
(R)
9
8
REAR
VS1
Vs2
(R)
2
5
19 20
8-8804
June 1988
1/11
843
TDA7300
CONNECTION DIAGRAM
TREBLE
TONE
[
VS1
seL
VS2
SEN
.&NO
SDA
]
(L)
DIG.GND
(A)
OUT (LF)
]
OUT (AF)
[
A4
OUT (AR)
A3
'~OOJ
[
OUT
REAA
OUT
BASS
B IN (A)
R2
TONE
BOUT (L)
A1
B IN(L)
MONO
LEFT
INPUTS
FRONT
J
OUT (LA)
AIGHT
INPUTS
BUS
INPUTS
~
L4
L1
L3
L2
]
LEFT
IIf'UTS
8-9807
THERMAL DATA
Thermal resistance junction-pins
Rth i-pins
max.
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; Vs1
and Rg = 600n; f = 1 KHz unless otherwise specified)
Parameter
SUPPLY
Test Conditions
12V or Vs2
Min.
= 8.5V;
65
°CIW
RL
= 10 Kn;
Typ.
Max.
Unit
(1)
V S1
Supply voltage V sl
10
12
16
V
V s2
Supply voltage V s2
6
8.5
10
V
Is
Supply current
20
30
40
mA
Vref
Reference voltage (pin 7)
3.5
4.3
5
V
SVR
Ripple rej. at V S1
f = 300 Hz to 10 KHz
80
100
dB
SVR
Ripple rej. at V s2
f= 300 Hz to 10 KHz
50
60
dB
30
45
KG
1.5
2.2
VRMS
90
100
dB
INPUT SELECTORS
Ri
Input resistance
V,N MAX Input signal
Cs
Channel separation
VI (DC)
DC Voltage level
Gy = OdB;
d = 0.3%
f = 1 KHz
f=10KHz
.::.2/""1..:.1_ _ _ _ _ _ _ _ _ _ _ _
844
~ ~~tmg,~©~
70
80
3.5
4.3
dB
5
V
-------------
TDA7300
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
VOLUME CONTROLS
G max
Control range
78
dB
Max gain
10
dB
Max attenuation
64
Step resolution
6B
2
dB
3
dB
Attenuator set error
2
dB
Tracking error
2
dB
41
dB
Gy = -50 to 10 dB
SPEAKER ATTENUATORS
Control range
35
Step resolution
38
3
dB
Attenuator set error
2
2
dB
Tracking error
2
dB
BASS AND TREBLE CONTROU2 )
Control range
± 15
Step resolution
2.5
AUDIO OUTPUT
Va
Output voltage
RL
Output load resistance
CL
Output load capacitance
Ro
Output resistance
d = 0.3%
1.5
2.2
VRMS
Kn
2
Vo (DC) DC va Itage level
3.5
1
nF
70
150
n
3.8
4.5
V
GENERAL
eNo
Output noise
Gy = 0 dB
BW = 22 Hz to 22 KHz
6
,.V
Gy = OdB
4
,.V
dB
Curve A
SIN
Signal to noise ratio
All gain = 0 dB
Vo= tvRMS BW= 22Hz to 22KHz
105
d
Distortion
f = 1 KHz;
Vo= 1V;
0.01
Frequency response (-1 dB)
Gy = OdB
High
Low
Sc
Channel separation
left/right
f= 1 KHz
f=10KHz
Gy=O
0.1
%
30
KHz
Hz
20
90
70
100
80
dB
dB
845
TDA7300
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
Min.
Typ.
Max.
BUS INPUTS
ViI.
Input LOW voltage
VIH
Input HIGH voltage
Vo
Output voltage SDA
acknowledge
0.8
V
V
2
1= 1.6mA
0.4
V
Notes:
1) The circuit can be supplied either at V 51 or at V s2 without the use of the internal voltage regulator. The circuit al~'
operates at a supply voltage Vsl lower than 10V. In this case the ripple rejection of V S2 is valid, because the voltage
regu lator saturates to about 0.8V.
2) Bass and Treble response see attached diagram. The center frequency and quality of the resonance behaviour can tie
choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback
network.
Fig. 1 - Test circuit
+Us2
CHI
:c
2213
uF
Cl
IN
(Ll
MONO
IN
(RI
[3
[3
o-J
:c
+Ua1
C12
C13
13
24
14
23
15
22
16
21
12
TDA
11
7388
C16
28
27
18
26
9
25
8
1-0
1-0
1-0
1-0
~]
FRONT
~J
REAR
~'J
SEN
BUS
SCL
OIG.GNO
C9
~ct9:(
:c :c
Rl
R4
15nF 15nF
88 TOII?388-St
4/11
846
6i
SGS·11I0MSON
~l. IiiIO©OO@IEn.moo@~D©$
C1 -C9 .2.2uF
C13-C16.2.2uF
C17-C28.18SnF
R1. R4 • 5.6K
R2. R3 • 51K
TDA7300
APPLICATION INFORMATION
Fig. 2 - P.C. board and component layout of the circuit in Fig. 11 (1: 1 scale)
Q
01-
=>=>
,
IJl
U
IJl
(-+---.;f--e:q.
~ 1---+------<11~,
,0o---i---!!\r
o
t5 o---+--~
i'CJ--+-----1i
a
a
Vee 3
IN
:xl
»
s::
ff"±ffiD""
"". J....,;~-.~:..J
DCA
~
I~
""UI
©.
~
~,o
©I
J
SA~LE
-
I
11
_IIN- LOCK
I
IllJJll,",
Vee1
VCC2
1'6
~i!
~O
I I I
II
~
LJI~IIAL
PHASE
I-----l
Hr.~~~D~NR\..t
I-----l
REFERENCE
f'lc::.f'1t I ATf"'IO
I
I f-'4- XTAl
DCS
~O
~Z
VEE
OLEN
CLB
DATA
---r
I~:
12
II
BUS/iOAD
CONTROL
LOGIC
~
:~
II
II
II
'8
TEST
-I
~
.....
W
N
U'I
TDA7325
CONNECTION DIAGRAM
TR
,.
TEST
TCA
17
XTAl
PINNING
1
2
3
4
5
6
7
8
9
Tce
16
VCC2
DCS
15
VEE
IN
,.
CLe
OUT
13
DLEN
VCeJ
12
OATA
FFM
"
FA"
13
14
Vee1
10
DCA
15
TR
TCA
TCB
DCS
IN
OUT
16
VCC3
FFM
VCCl
DCA
FAM
DATA
DLEN
CLB
VEE
VCC2
17
18
XTAL
TEST
10
11
12
5-7669
resistor/capacitors
for sample and
hold circuit
decoupling of supply
input of output amplifier
output of output amplifier
positive supply voltage of output amplifier
FM signal input
positive supply voltage of high frequency logic part
decoupling of input amplifiers
AM signal input
BUS
ground
positive supply voltage of low frequency logic part
and analogue part
reference oscillator input
test output
ABSOLUTE MAXIMUM RATINGS
V CCl ; V CC2
VCC3
Ptot
Tamb
Tstg
Supply voltage; logic and analogue part
Supply voltage; output amplifier
Total power dissipation
Operating ambient temperature range
Storage temperature range
ELECTRICAL CHARACTERISTICS
-0.3 to 13.2
V CC2 to +30
max. 800
-25 to +70
-40 to +150
V
V
mW
°C
°C
(VEE = 0 V; V CCl = V CC2 = 5 V; VCC3 = 20V; Tamb =
25°C; unless otherwise specified)
Parameter
V ecl
VCC2
VCC3
Test Conditions
Supply voltages
Min.
Typ.
Max.
Unit
4
4
VCC2
5
5
-
10
10
25
V
V
V
-
20
25
-
mA
mA
mA
Supply currents'
Itot
Ito t
ICC3
AM mode
FM mode
Itot = lecl + ICC2
in-iock; BRM = '1;
lOUT = 0
1
• When the bus is in the active mode (see BRM in Control Information), 4,5 mA should be added to the figures given,
------------- ~ ~~tmo~Jl------------3::t..:::/8
871
TDA7325
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
512 kHz
80
30
30
-
MHz
MHz
mV
mV
-
2
135
3.5
3
-30
32
150
500
500
-
RF inputs (FAM, FFM)
fFAM
fFFM
Vi(rms)
VI(rms)
Rj
Rj
CI
Cj
VsIV ns
AM input frequency
FM input frequency
Input voltage at FAM
Input voltage at FFM
Input resistance at FAM
Input resistance at FFM
Input capacitance at FAM
Input capacitance at F FM
Voltage ratio allowed between
selected and non-selected input
Crystal oscillator (XTAL)
Maximum input frequency
Crystal series resistance
V IL
V IH
-IlL
BUS inputs (DLEN, CLUB,
DATA)
Input voltage LOW
Input voltage HIGH
Input current LOW
VIL=0.8V
IIH
Input current HIGH
VIH=2.4V
BUS inputs timing
(DLEN, CLB, DATA)
Lead time for CLB to DLEN
Lead time for DATA to the
first CLB pulse
Set-up time for DLEN to CLB
CLB pulse width HIFH
CLB pulse width LOW
Set-up time for DATA to CLB
Hold time for DATA to CLB
Hold time for DLEN to CLB
Set-up time for DLEN to
CLB load pulse
Busy time from load pulse to
next start to transmission
see also Fig. 2 and
note 2
tCLBlag 1
tCLBH
tCLBL
tOATAlead
tOATAhoid
tOLENhoid
tCLBlag2
tOIST
tOIST
Busy time
asynchronous mode
Sample and hold circuit
(TR, TCA, TCB)
VTCA,VTCB Minimum output voltage
VTCA,VTCB Maximum output voltage
Capacitance at TCA
CTCA
(external)
CTA
Discharge time at TCA
tOIS
872
kn
n
-
pF
pF
dB
-
see note 1
fXTAL
Rs
tCLBlead
tTlead
-
4
-
-
MHz
-
-
150
n
0
2.4
-
0.8
V CCl
10
V
V
/lA
-
10
/lA
-
-
-
-
/lS
/lS
1
0.5
next transmission
after word 'B'
to other device
or
next transmission
to SAA1057
after word' A'
-
-
/lS
-
-
/lS
-
-
/lS
-
-
-
/lS
/lS
/lS
/lS
5
-
-
/lS
0.3
1.3
-
-
ms
ms
-
1.3
-
-
VCC2..()·7
-
5
5
5
8
0
2
2
see also notes 3; 4
REFH
REFH
REFH
REFH
=
=
=
=
'1'
'0'
'1'
'0'
-
5
6.25
2.2
2.7
V
V
nF
nF
/lS
/lS
TDA7325
ELECTRICAL CHARACTERISTICS (continued)
Test Conditions
Parameter
VTR
Iblas
Voltage at TR during discharge
Bias current into TCA, TCB
Min.
Typ.
Max.
Unit
-
0.7
10
-
V
nA
-
0.4
-
mA
-
0.023
0.07
0.23
0.7
2.3
-
in-look
Program mabie current
amplifier (PCA)
± Idlg
Gpl
Gp2
Gp3
Gp4
Gp5
STCB
llVTCB
Output current of the dig.
ph ase detector
Current gain of PCA
CP3 CP2 CPl
Pl
P2
P3
P4
PS
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
CPO
0
1
0
0
0
VCC2;;>S V (only for Pl)
-
-
Ratio between the output current of S/H into PCA and the
voltage on
CTCB
Offset voltage on TCB
in lock
-
1.0
1
-
p.A/A
V
in-lock; equal to
internal reference
voltage
-lOUT = 1 mA
IOUT= 1 mA
IOUT= 0.1 mA
VOUT=VCC3-4V
-
1.3
-
V
V CC3 -1
-
O.S
V
V
V
mA
-
Output amplifier (I N, OUT)
VIN
I nput voltage
VOUT
V OUT
VOUT
± lOUT
Output voltages minimum
Output voltages maximum
Output voltages maximum
Maximum output current
VCC3-2.SV
-
S
-
Test output (TEST) •
V TL
VTH
IToff
I Ton
Output voltage
Output voltage
Output current
Output cu rrent
LOW
HIGH
OFF
ON
-
V TH
VTL
-
0.5
12
10
lS0
-
-
V
V
p.A
p.A
-
77
70
60
-
dB
dB
dB
Ripple rejection**
at frlPPl e = 100 Hz
llVCC1/llVO UT
II V CC2/II V OUT
II VCC3/11 VOUT
*
Open collector output
•• Measured
In
VOUT " VCC3 -3V
FIg. 6
NOTES
1. Pin 17 (XTAL) can also be used as an input for an external
clock.
The values given in Fig. 1 are a typical application example.
2. See BUS information in section 'operation description.
3. The output voltage at TCB and TCA is typically 'l.zV CC2+0.3 V
when the tuning system is in-lock via the sample and hold
phase detector. The control voltage at TCB is defined as the
difference between the actual voltage at TCB and the value
calculated from the formula 'l.zVCC2+0.3V.
4. Crystal oscillator frequency fXTAL = 4 MHz.
Fig. 1 - Circuit configuration showing external
4 MHz clock
+5V-]1f
OV4MHz
..r._. . .
_.:..;17:..j XTAL
I
...J PF
CXTAL""!'"
I
5-7670
------------- ~ I~tm~~~~lf ____________
=5/8
873
TDA7325
GENERAL DESCRIPTION
OPERATION DESCRIPTION
The TDA 7325 performs the entire PPL synthesizer function (from frequency inputs to tuning
voltage output) for all types of radios with the
AM and FM frequency ranges.
The circuit comprises the following:
• Separate input amplifiers for the AM and FM
VCO-signal.
• A divider-by-10 for the FM channel.
Control information
The following functions can be controlled with
the data word bits in latch B, For data word
format and bit position see Fig. 3.
FM
FM/AM selection; '1' = FM, '0' = AM
REFH reference frequency selection; '1' = 1.25
kHz, '0' = 1 kHz (sample and hold phase
(detector)
CP3
control bits for the programmable current
CP2
amplifier (see section Electrical CharacCP1
teristics)
CPO
• A multiplexer which selects the AM or FM
input
• A sample and hold phase detector for the
in-lock condition, to achieve the high spectral
purity of the VCO signal.
• A digital memory frequency/phase detector,
which operates at a 32 times higher frequency
than the sample and hold phase detector, so
fast tuning can be achieved.
• An-in-Iock counter detects when the system is
in-lock. The digital phase detector is switchedoff automatically when an in-lock condition is
detected.
• A reference frequency oscillator followed by a
reference divider. The frequency is generated
by a 4 MHz quartz crystal. The reference frequency can be chosen either 32 kHz or 40 kHz
for the digital phase detector (that means 1
kHz and 1.25 kHz for the sample and hold
phase detector), which results in tuning steps
of 1 kHz and 1.25 kHz for AM, and 10kHz
and 12.5 kHz for FM.
•
A programmable current amplifier (charge
pump), which controls the output current of
both the digital and the sample/hold phase
detector in a range of 40 dB. It also allows the
loop gain of the runing system to be adjusted
by the microcomputer.
• A tuning voltage amplifier, which can deliver a
tuning voltage of up to 25 V.
•
BUS; this circuitry consists of a format control
part, a 16-bit sh ift register and two 15-bit
latches. Latch A contains the to be tuned frequency information in a binary code. This
binary-coded number, multiplied by the tuning
spacing, is equal to the synthesized frequency.
The programmable divider (without the fixed
divide-by-10 prescaler for FM) can be programmed in a range between 512 and 32767
(see Fig. 3). Latch B contains the control information.
~6/~8_ _ _ _ _ _ _ _ _ _ _ _
874
enables last 8 bits (SLA to TO) of data
word B;
'1' enables '0' = disables; when programmed '0', the last 8 bits of data word
B will be set to '0' automatically
SLA load mode of latch A; '1' = synchronous,
'0' asynchronous
PDM1 phase detector mode
PDMO
SB2
BRM
T3
T2
T1
TO
PDM1
PDMO
0
X
1
1
0
1
digital phase
detector
automatic
on/off
on
off
bus receiver mode bit; In thiS mode the
supply current of the BUS receiver will
be switched-off automatically after a data
transmission (current-draw is reduced);
'" = current switched; '0' = current
always on
test bit; must be programmed always '0'
test bit; selects the reference frequency
(32 or 40 kHz) to the TEST pin
test bit; must be programmed always '0'
test bit; selects the output of the programmable counter to the TEST pin
T3
0
T2
0
T1
TEST (pin 18)
0
TO
0
1
0
1
0
0
reference frequency
0
0
0
1
output progrrammable
counter
0
1
0
1
output in-lock counter
'0' = out-lock
'1' = in-lock
i.W.. !~m?I£I~~~JI -------------
Fig. 2 - BUS format
DLEN
CLB
-- --
~
I~
OjJ(II
© •
~~
X
~~=x
DATA
bit no
15
~
__
16
(1) During the zero set-up time (tLzsu) CLB can be LOW or HIGH, but no transient of the signal is permitted. This can be of use
when an I' C bus is used for other devices on the same data and clock lines
~o
0jJi:
©(II
~o
~z
Fig. 3 - Bit organization of data words A and B
DATA WORD A
512
bits stored in latch A
~ dividing number.:s;32767
DATA WORD B
-f
bits stored in latch
co
-.J
(1l
~
ex>
~
B
5-7668
"'"
to)
I\)
U1
TDA7325
APPLICATION INFORMATION
Initialize procedure
Either a train of at least 10 clock pulses should
be applied to the clock input (CLB) or word B
should be transmitted, to achieve proper initialization of the device.
For the complete initialization (defining all
control bits) a transmission of word B should
follow. This means that the IC is ready to accept
word A.
Synchronous/asynchronous operation
Synchronous loading of the frequency word into
the programmable counter can be achieved when
bit 'SLA' of word B is set to '1 '. This mode should
be used for small frequency steps where low
tuning noise is important (e.g. search and manual
~8/~8
________________________
876
tuning). This mode should not be used for frequency changes of more than 31 tuning steps.
In this case asynchronous loading is necessary.
This is achieved by setting bit 'SLA' to '0'. The
in-lock condition will then be reached more
quickly, because the frequency information is
loaded immediately into the divider.
Restrictions to the use of the programmable
current amplifier
The lowest current gain (0.023) must not be used
in the in-lock condition when the supply voltage
V CC2 is below 5 V (CP3, CP2, CP1 and CPO are
all set to '0'). This is to avoid possible instability
of the loop due to a too small range ofthe sample
and hold phase detector in this condition (see
also section 'Electrical Characteristics').
~1~!;~~~~
__________________________
TDA7350
BRIDGE-STEREO AMPLIFIER FOR CAR RADIO
ADVANCE DATA
•
VERY FEW EXTERNAL COMPONENTS
•
NO BOUCHEROT CELLS
•
NO BOOTSTRAP CAPACITORS
•
HIGH OUTPUT POWER
•
•
NO SWITCH ON/OFF NOISE
VERY LOW STAND-BY CURRENT (100~A)
• FIXED GAIN
• PROGRAMMABLE TURN-ON DELAY
The TDA7350 is a new technology class AB
Audio Power Amplifier in the Multiwatt®
package designed for car radio applications.
Thanks to the fully complementary PNP/NPN
output configuration the high power perform·
ance of the TDA7350 are obtained without
bootstrap capacitors.
A delayed turn-on mute circuit eliminates
audible on/off noise, and a novel short circuit
protection system prevents spurious intervention
with highly inductive loads.
Protections :
•
OUTPUT AC-DC SHORT CIRCUIT TO
GROUND AND TO SUPPLY VOLTAGE
•
VERY INDUCTIVE LOADS
•
OVERRATING CHIP TEMPERATURE
•
•
LOAD DUMP VOLTAGE
FORTUITOUS OPEN GROUND
Multiwatt -11
ORDERING NUMBER: TDA7350
APPLICATION CIRCUIT
-Us
22uF
J:
C4
11
SUR
7
188nF
C6
9
r--.l....-----------'-_
STAND-B'!'
22uF
C3
OUT2
J:
IN C!..J 5
8
TOA7350
IN2(+)
9.22uF
r!11
9.22uF
IN1C -)
OUT
IN1I- ) BRIDGE
OUT1
S-GHD
1B
2
_1lIfV~
June 1988
P-GND
.•
1/6
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
877
TDA7350
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10
10
Ptot
Tstg , TJ
Operating supply voltage
DC supply voltage
Peak supply voltage (for t = 50ms)
lOUT peak (non rep. t = 100,us)
lOUT peak (rep. freq. > 10Hz)
Power dissipation at Tease = 80°C
Storage and junction temperature
18
v
28
V
V
A
40
5
4
40
-40 to 150
A
W
°c
CONNECTION DIAGRAM
(Top view)
S-1002O
~11
STAND-BY
-$- 1~
OUT1
+Vs
OUT2
8
7
$
_I'h
'P"
6
P-GND
5
IN 2(+)
4
BRIDGE/STEREO
SVR
S-GND
2~ 111111111:
1
~
IN 1 (-)
IN1(+)
L-T-a-b-eJoln~n=ec=t=ed=t~o::::::p=in~6=::!J
THERMAL DATA
Rth
J-case
Thermal resistance junction-case
.:;,2/:,;;6_ _ _ _ _ _ _ _ _ _ _ _
878
~ 1~I@m&'I£~
max
1.8
------------
TDA7350
ELECTRICAL CHARACTERISTICS (Refer to the test circuits,
14.4V,
Tamb
f = 1 KHz, unless otherwise specified)
Parameter
Vs
Supply voltage
Id
Total quiescent drain current
ASB
Stand-by attenuation
ISB
Stand-by current
Test Conditions
Min.
Typ.
8
stereo configuration
60
Max.
Unit
18
V
120
mA
100
fJ.A
dB
80
STEREO
Output power (each channell
Po
d = 10%
RL
RL
RL
RL
-l.60
=20
= 3.20
=40
RL = 3.20
7
12
11
8
6.5
W
d
Distortion
0.1 to4W
SVR
Supply voltage rejection
Rs = 0 to 10KO
f = 100Hz
45
50
dB
CT
Crosstalk
f = 1 KHz
f = 10KHz
45
55
50
dB
0.5
Ri
Input resistance
30
50
Gv
Voltage gain
27
29
Gv
Voltage gain match
EIN
Input noise voltage
Rg = 500
%
KO
31
dB
1
dB
1.5
(*)
Rg = 10KO
fJ.V
2.0
2.0
Rg = 500
(**)
fJ.V
Rg = 10KO
2.7
BRIDGE
Output power
Po
d - 10%
d = 0.5%
d
Distortion
VOS
Output offset voltage
SVR
Supply voltage rejection
RI
Input resistance
Gv
Voltage gain
EIN
Input noise voltage
RL - 40
RL = 3.20
16
f = 1 KHz
RL = 40
Po = O.lW to lOW
0.15
45
%
250
mV
50
35
dB
KO
37
dB
2.0
Rg = 500
(*)
fJ.V
2.5
Rg = 500
2.7
(**)
Rg = 10KO
A;
1
50
33
Rg = 10KO
(*) Curve
W
18
RL = 40
R s =Otol0KO
f= 100Hz
20
22
fJ.V
3.2
(**) 22Hz to 22KHz
---------------------------
~~~I~~~I~~~
_________________________
3~/6
879
TDA7350
Fig. 1 - STEREO test and application circuit
SU3
+Us
C4
22uF
:c
11
:c
C6
1BBn:
C7
22BBuF
STAND-BV
OUT2
IN21
TDA7358
.~
+)
C8
2299uF
INtl<)
OUT1
OUT
Ct
IN11 -) BRIDGE S-GNO
P-GNO
U!
9.22u~----~----~----~-----p--~
2
Fig. 2 - P.C. and layout (STEREO) of the fig. 1 (1: 1 scale)
GND
(9)
IN 2 (5)
IN 1
880
~
TDA7350
Fig. 3 - BRIDGE test and application circuit
-Us
22uF
J:
C4
11
SUR
22uF
C3
199nF
C6
9
7 r---L-------------------~--~
STAND-BV
OUT2
:c
IN C~ 5
8
TDA7350
IN2 ( +)
9.22uF
r!11
oun
IN1 ( - )
Itoft (-)
B.22uF
OUT
BRIDGE
S-GND
19
P-GND
2
_TDN':J5I-1U
Fig. 4 - P.C. and layout (BRIDGE) of the fig. 3 (1: 1 scale)
1
C2
GND
(9)
IN 2 ( 5)
IN 1
(1 )
C1
OO~O
I[00] )
@
[ JUMP
I
JUMP
C 5-0275
___________________________
~I~I~~~~~:
________________________
~5/6
881
TDA7350
Fig. 5 - Output power
versus Vs (STEREO)
-
Fig. 6 - POUT versus frequency (STEREO)
88rOfl?358 01
Po
IU I
I
RL·1.6n
f. tKHz
-
12
d.191
VA
e
V/
6
~
//
Po
lUI
V2n
Cout •
2299uF
r.I3.2
59
uF
/
~
V
14
I
/
II
1/
-
3~ 199399 lK
19
3K 19K
f
IHzl
19
88'OIl?3511 05
39 199399 lK
IU I
"
45
22
59
C7IUFlu:
45 -1 9
59
49
Us.14.4U
RL.40
Rg.19Ko
35
1--29
r--
',!J
f/
1/
~r-"
18
/
Us.14.4V
RRL 3 O
I
19
i·n :lo
35
/
19
19 39 199 399 lK
3K 19K f -I Hz I
19
39
199
88rOIl?3511 O?
Id
Pta t
ImA I
lUI
V
V
'"
6
19
12
14
Us IVI
49
,
r- r- Ptot
8
12
16
29
29
24 2.Po lUI
""6/c:;6_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~I~m~
882
69
14
12
lUI
14
19
....
/'"
12
i/l
8
19
Us
lUI
Pta t
,,
,,
1/
Fig. 13 - Dissipated power
& efficiency vs. Po
(BRIDGE)
88rOfl?358-09
I
Us_l".4U
RL.3.2n
f.1KHz
,,
12
8
V
8
f IHzI
n
19
/v
lK
,,
59
49
399
Fig. 12 - Dissipated power
& efficiency vs. Po
(STEREO)
118'OIl?3511 08
Fig. 11 - Quiescent current
versus Vs
/
RL·'n
f.1KHz
d.191
r-
...
3K 19K f IHzl
88'OIl?3511 06
Po
Sur
Idbl
59
-
Fig. 10 - Output power
versus Vs (BRIDGE)
Fig. 9 - SVR versus CSVR
(STEREO)
88rOIl?358-04
55
U•• 14.4U
RL.3.20
C.2299uF
2
9
Fig. 8 - Crosstalk vs. frequency (STEREO)
CT
IdB I
d.9.51
I
U.·14.4U
RL.3.20
d.191
1999uF
Us (UI
d·191
8
1//
40
/ /'
12
t/.;::P"
/IV
rtf
6
/
-88rOfl?3511 03
118rOIl?3511 02
Po
IU I
'/
/,
//
Fig. 7 - POUT versus frequency (STEREO)
~_n
I
r-Pta t
/
1
L
69
49
l
Us_14.4U
RL.3.2n
f .IKHz
I
8
12
16
29
24
29
Po lUI
------------
TDA7359
LOW VOLTAGE NBFM IF SYSTEM
•
OPERATION FROM 1.8V TO 9V
•
LOW DRAIN CURRENT (4mA, Vs = 4V)
•
HIGH SENSITIVITY (.JdB INPUT LIMITING
AT 31lV)
The TDA7359 is designed for use in NBFM dual
conversion communication equipments using a
455KHz ceramic filter like cordless telephones,
walkie-talkies, scan receivers, etc.
• 81lV INPUT FOR 20dB SIN
•
AFC OUTPUT
•
LOW EXTERNAL FAIR COUNT
The TDA7359 is a low-power narrow band FM
IF demodulation system operable to less than 2V
supply voltage.
DIP-18 Plastic
The device includes Oscillator, Mixer, Limiting
Amplifier, Quadrature Discriminator, Op. Amp.,
Squelch, Scan Control and Mute Switch.
ORDERING NUMBERS: TDA7359 (DIP-18)
TDA7359D (SO-20L)
BLOCK DIAGRAM (PIN. NUMBERS are for DIP-18)
18
10
1.8Ka
2
3
4
5
7
5- 9630
June 1988
1/6
883
TDA7359
ABSOLUTE MAXIMUM RATINGS
Vs
Supply voltage
R F input voltage (pin 18)
Detector input voltage
Mute function voltage
Operating ambient temperature
Junction temperature
Storage temperature
VI
V8
V 14
Top
Tj
T stg
9
1
V
V rms
V pp
V
-0.5 to 5
o to 70
150
-65 to 150
°c
°c
°c
CONNECTION DIAGRAMS
(Top view)
XTAL
RF INPUT
1
XTAL
GND
MIXER
OUTPUT
AUDIO
MUTE
+vs
4
LIMITER
INPUT
DECOUPLING
6
QUAD
INPUT
l'
DEMODULAT.
FILTER
I
MIXER
OUTPUT
20
RF INPUT
19
GND
18
J
AUDIO
MUTE
SCAN
CONTROL
+Vs
I
4
17
~
SQUELCH
INPUT
LIMITER
INPUT
I 5
16
~ SQUELCH
~
SCAN
CONTROL
INPUT
FILTER
OUTPUT
FILTER
OUTPUT
DECOUPLING
6
15
FILTER
INPUT
D£COUPI.ING
7
14
QUAD
8
13
9
14 ] AUDIO OUT
AFC
AUDIO OUT
5- 9631
INPUT
DEMOOULAT.
FILTER
J
AFC
11 ]
[ 10
N.C.
FILTER
INPUT
N.C.
5-9751
SO-20L
DIP-18
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
~2/~6-------------------------~~~~~~?vT~~
884
DIP-18
SO-20L
max
---------------------------
TDA7359
PIN FUNCTION (DIP-18)
NAME
FUNCTION
1-2
XTAL OSCILLATOR
Connections for the Colpitts XTAL oscillator.
The XTAL may be replaced by an inductor (see fig. 5)
if the application does not require high stability.
3
MIXER OUT
The Mixer is double balanced to reduce spurious products. The output impedance is 1.8Kn to match the
input impedance of a 455KHz ceramic filter.
4
SUPPLY VOLTAGE
Must be well decoupled with a 100nF ceramic capacitor.
5
IF LIMITER INPUT
Input pin of the six stages amplifier with about 50~LV
limiting sensitivity and 1.8Kn input impedance. The if
output is connected to the external quadrature coil
(pin 8) via an internal 10pF capacitor.
6-7
DECOUPLING
Good quality 100nF ceramic capacitors and a suitable
layout are important.
8
QUADRATURE COIL
A quadrature detector is used to demodulate the 455KHz
FM signal. The Q of the quad coil has direct effect on
output level and distortion (see fig. 6). For proper operation the voltage should be 100mVrms •
10
AUDIO OUTPUT
The Audio signal after detection and deemphasis is
buffered by an internal emitter follower.
11
AFC OUT
AFC output, with high gain and high output impedance.
If not needed, it should be grounded or connected to
pin 9 (to double the recovered audio).
12
OP AMP. INPUT
13
OP AMP. OUTPUT
Because of the low DC bias, the swing on the operational
amplifier output is limited to 550mVrms . This can be
increased by adding a resistor from the operational
amplifier input to ground.
14
SQUELCH INPUT
15
SCAN CONTROL
16
MUTE
17
GND
Ground connection.
18
10.7MHz MIXER INPUT
Input of the wide-band mixer. Normally used as 10.7MHz/
455KHz converter, it can be also used with input frequencies up to 60MHz.
The Squelch trigger circuit with a low bias on the
input (pin 14) will force pin 15 high; and pin 16 Low.
Pulling pin 14 above mute threshold (0.65V) will force
pin 15 to an impedance of about 60Kn to ground and
pin 16 will be an open circuit.
An hysteresis of about 50mV at pin 12 will effectively
prevent jitter.
------------- ~ !~tmg,'~AI------------=3/6
885
TDA7359
ELECTRICAL CHARACTERISTICS (Vs = 4V; fo = 10.7MHz; f= ± 3KHz; fm = 1KHz; Taml:l =
25°C; unless otherwise noted)
Paramllter
Test Conditions
Min.
Typ.
Max.
Unit
1.8
4
9
V
Vs
Supply voltage range
Is
Supply current
Squelch OFF
Squelch ON
3.8
4.7
mA
Vi
Input quieting voltage
SIN = 20dB
8
p.V
Vi
Input limiting voltage
-3dB limiting
3
p.V
Vo
Recovered audio output
Vi = 10mV
150
mVrms
V IO
Detector output voltage
1.5
Voc
RIO
Detector output impedance
400
n
Detector center frequency
slope
150
mV/KHz
55
dB
1.5
Voc
20
nA
50
mV
LOW
50
n
HIGH
10
Mn
Gv
Operating amplifier gain
V 13
Operating amplifier output
voltage
Ie
Op. Amp. input bias
current
VT
Trigger hysteresis
Rm
Mute switching impedance
VIS
Scan voltage
f = 10KHz
Gv = V13 /V12
40
Pin 10
pin 14 HIGH (2V)
pin 14 LOW (OV)
3.0
0
3.4
0.5
Voc
Gc
Mixer converter gain
30
dB
Ri
Input resistance
3.3
Kn
Ci
I nput capacitance
2.2
pF
6_ _ _ _ _ _ _ _ _ _ _ _
-"4/c..:.
886
iiii. !~tm=~lt ------------
TDA7359
Fig. 2 - Test circuit
.VS
10.245MHz
0.1 pF
10.7MHz
MIXER INPUT
18
68
pF
2
17
3
16
AUDIO MUTE
4
15
SCAN CONTROL
5
14
SQUELCH INPUT
6
13
CFU455E
O.I)JF
t-ooP. AMPLIFIER
OUTPUT
510
O.I~ OP AMPLIFIER
Kll
7
12
510
INPUT
Kll
J
33Kll
150
pF%
8
11
9
10
AFC
7.5M
1
Fig. 3 - Supply current vs. supply
voltage
G-624911
Vo
(dB)
9
o
f!--- V
...- .....-
"'SQU1LCH
V
~FF
10nF
5-9628
Fig. 4 - FM IF characteristics
(rnA)
IS
AUDIO OUTPUT
Vo
'\.
-20
"-
",
-40
"'~
~
-60
-
o
--------------------------~~i~;~~~~
OdB= 150mV
Vs = 4V
fo =10.7MHz
1m-=: 1KHz
tJ.f = <3KHz
10
...........
10'
NOISE
I04RF INPUT
________________________~5/6
887
TDA7359
Fig. 5 - Colpitts XTAL oscillator
Fig. 6 - Effect of quadrature coil
on audio level and distortion
"a"
~
6251
/' 7
/ /
0,8
.A V
DISTCRTlOY
0.6
...
r7tUD~~
o TP
/
1/
Cl.4
1/
I
0,2
5-9629
o
10
20
30
40
QUAD COIL Q
!:!6/~6 _ _ _ _ _ _ _ _ _ _ _ _ ~ !~mg,rr~~JI------------
888
TDA7360
STEREO I BRIDGE AMPLIFIER WITH CLIPPING DETECTOR
ADVANCE DATA
Main features:
•
VERY FEW EXTERNAL COMPONENTS
•
•
NO BOUCHEROT CELLS
NO BOOTSTRAP CAPACITORS
•
•
•
HIGH OUTPUT POWER
NO SWITCH ON/OFF NOISE
VERY LOW STAND-BY CURRENT
• FIXED GAIN
• PROGRAMMABLE TURN-ON DELAY
• CLIPPING DETECTION
The TDA7360 is a new technology class AB
Audio Power Amplifier in Multiwatt package designed for car radio applications. Thanks to the
fully complementary PNP/NPN output configuration the high power performances of the
TDA7360 are obtained without bootstrap
capacitors.
A delayed turn-on mute circuit eliminates
audible on/off noise, and a novel short circuit
protection system prevents spurious intervention
with highly inductive loads.
The device provides a circuit for the detection of
clipping in the output stages. The output, an
open collector, is able to drive systems with automatic volume control.
Protections:
•
OUTPUT AC-DC SHORT CI RCUIT TO
GROUND AND TO SUPPLY VOLTAGE
•
•
VERY INDUCTIVE LOADS
OVERRATING CHIP TEMPERATURE
•
•
LOAD DUMP VOLTAGE
FORTUITOUS OPEN GROUND
Multiwatt-11
ORDER CODE: TDA7360
APPLICATION CIRCUIT (BRIDGE)
.--~~~-...,--~--~--o
'Us
11l9nF
9
STANO-BY
DUT2
1--<>--,
9
TOA736G
RL
11'12 ( .)
11'11 (.)
OUT
CLIP.DET .BRIDGE
OUT 1 I---Q-...J
111
S-GND
P-GND
1l.22uF
2
88 TOR?368-52
June 1988
1/6
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
889
TDA7360
ABSOLUTE MAXIMUM RATINGS
Vs
Vs
Vs
10
10
P tot
Tstg , TJ
Operating supply voltage
DC supply voltage
Peak supply voltage (for t = 50 ms)
lOUT peak (non rep. t = 100 !lsI
lOUT peak (rep. freq. > 10 Hz)
Power dissipation at Tcase = 80°C
Storage and junction temperature
18
28
40
4.5
3.5
40
-40 to 150
V
V
V
A
A
W
°C
CONNECTION DIAGRAM
(Top view)
"-"7t
l
-$-
19
9
8
7
6
-$-
L
[
-Us
OUT2
SUR
P-GND
5
11'12 ( - J
4
3
OUT BRII;lGE
S-GND
2
CLIP. DET.
~
TAB CONNECTED TO PIN 6
STAND-BY
DUT1
11'111 - J
88TOR?368-54
THERMAL DATA
Rth j-ase
Thermal resistance junction-case
"'2/..:.6_ _ _ _ _ _ _ _ _ _ _ _
890
max
1.8
°CIW
~ !~~~JI-------------
TDA7360
ELECTRICAL CHARACTERISTICS (Refer to the test circuit,
25°C, Vs = 14.4V,
Tamb
f = 1 KHz, unless otherwise specified)
Parameter
Vs
Supply voltage
Id
Total quiescent drain current
ASB
Stand·by attenuation
ISB
Stand-by current
Ico
Clip detector current average
dtco
Distortion threshold for
Clip Detect. output
Test Conditions
Min.
Typ.
8
stereo configuration
60
Max.
Unit
18
V
60
mA
80
dB
100
d~l%
IJA
-1
mA
0.5
%
12
11
8
6.5
W
W
W
W
0.05
%
55
dB
60
55
dB
dB
I nput resistance
50
Kn
Gv
Voltage gain
20
dB
Gv
Voltage gain match.
Ein
I nput noise voltage
STEREO
Output power (each channell
Po
d
d
Distortion
SVR
Supply voltage rejection
~
10%
RL ~ 1.6n
RL ~ 2 n
RL ~ 3.2n
RL~4 n
7
f ~ 1KHz 4n
100 mWto4W
Rs~
Oto 10 Kn
f~100Hz
Crosstalk
CT
f~
1 KHz
f~10KHz
RI
,
1
22 Hz to 22 KHz Rg = 50n
R g =10Kn
3
3.5
dB
IJV
IJV
BRIDGE
VOS
Output offset voltage
Po
Output power
250
d = 10%
R L =4n
RL = 3.2 n
d = 0.5%
RL = 4 n
16
mV
20
22
W
W
18
W
0.05
%
55
dB
d
Distortion
f = 1 KHz
RL = 4n
Po = 0.1 to lOW
SVR
Supply voltage rejection
Rs = Oto 10 Kn
f = 300 Hz to 3.5 KHz
Ri
I nput resistance
50
Kn
Gv
Voltage gain
26
dB
E'n
I nput noise voltage
6
IJV
IJV
22Hz to 22K Hz Rg = son
Rg = 10Kn
7
------------- ~ ~~~m~~59Al ___________---.:3=/6
891
TDA7360
APPLICATION INFORMATION
The TDA7360 is equipped with an internal
circu it able to detect the output stage saturation
providing a proper current sinking into a proper
open collector out. (pin 2) when a certain dis-
Fig. 1 - Dual
channel
distortion
tortion level is reached on each output.
This particular function allows compression
facility whenever the amplifier is overdriven,
obtaining high quality sound at all listening levels.
threshold detector
>-_----+---0 OUT1
tN1
CLIPPING
DET. 0--+----,
DISTORTION
DETECTOR
>--.......---+--0 aUT2
IN2
88 T0I1?368-81
Fig. 2 - Output from the clipping detector Pin. versus signal distortion
Uo
AUDIO
OUTPUT
SIGNAL
1
1
- -1- - 1
1
r - -1
1
CLIPPING
DET.
, OUTPUT CURRo
ICLIP
~
B
__
~
__
~
____________
L-_~
_________ ----.
time
BBTDft?368-53ft
..-"4/..;06_ _ _ _ _ _ _ _ _ _ _ _
892
~ ~~I~m&rr£~ ~------------
TDA7360
Fig. 3 - Stereo test and application circuit
22uF
C4
:c
:c
11
'Us
1BBnF
C6
9
STRND-BV
22uF
C3
DUT2
TDA736G
IN2(')
1
22BBuF
IN
INU+)
DUn 19
OUT
C 1 -1.._C_L_I_P..' ...;,O_E_T_,_B_R..
I D_G_E;;..._S;..-...;G;..N.;.;D;;...~P_-...
GN_0;;,...,J
CB
B,22u,.'
RL
4
f188TOfl?36B-Bl
Fig. 4 - P.C. and layout (STEREO) of the Fig. 3 (1: 1 scale)
___________________________
~~~~~~~~
____________________----~5/~6
893
TDA7360
Fig. 5 - Bridge test and application circuit
+Lls
22uF
C4
SLiR
22uF
C3
I
I
11313nF
C6
9
11
7 ...-_.1-._ _ _ _ _ _ _ _ _ _.1-.---,
STAND-BY
OUT2
I
~s
B
TDA736G
RL
IN2(+)
13.22uF
IN
0---1
1
C1
13.22uF
IN1C +)
OUT
CLI P. OET . BRIDGE
OUT1
S-GNO
P-GNO
113
2
t1BB TDfI?368- 82
Fig. 6 - P.C. and layout (BRIDGE) of the Fig. 5 (1: 1 scale)
~6/~6__________________________ ~~~~~~g~:J?:I
894
----------------------------
TDA7361
LOW VOLTAGE NBFM IF SYSTEM
• OPERATION FROM 1.8V TO 9V
=
•
LOW DRAIN CURENT (4mA, Vs
4VI
•
HIGH SENSITIVITY(-3dB INPUT LIMITING
AT 3~.LV)
•
81lV INPUT FOR 20dB SIN
•
LOW EXTERNAL FAIR COUNT
The TDA7361 is a low-power narrow band FM
I F demodulation system operable to less than
2V supply voltage.
The device includes Oscillator, Mixer, Limiting
Amplifier, Quadrature Discriminator, Op. Amp.
Squelch, Scan Control and Mute Switch.
The TDA7361 is designed for use in NBFM dual
conversion communication equipments using a
455KHz ceramic filter like cordless telephones,
walkie-talkies, scan receivers, etc.
DIP-16 Plastic (0.25)
SO-16J
ORDERING NUMBERS: TDA7361 (DIP-16)
TDA7361D (50-16)
BLOCK DIAGRAM
16
1.8Ka
2
June 1988
3
4
5-9632
1/6
895
TDA7361
ABSOLUTE MAXIMUM RATINGS
Vs
VI
Va
V 14
Top
T stg
9
1
1
-0.5 to 5
o to 70
-65 to 150
Supply voltage
RF input voltage (pin 16)
Detector input voltage
Mute function voltage
Operating ambient temperature
Storage temperature
V
Vrms
Vpp
V
°c
°c
CONNECTION DIAGRAM
(Top view)
16
RF INPUT
2
15
GND
MIXER
OUTPUT
3
14
AUDIO
MUTE
+Vs
4
13
SCAN
CONTROL
LIMITER
INPUT
5
12
SQUELCH
INPUT
DECOUPLING
6
11
FILTER
OUTPUT
DECOUPLING.
7
10
FILTER
INPUT
9
AUDIO OUT
XTAL
QUAD
INPUT
s- 9633
THERMAL DATA
RthJ .... mb
Thermal resistance junction-ambient
~2/~6~_______________________ ~1~1~~~~'~~
896
max
DIP·16
80-16
100°C/W
200°C/W
---------------------------
TDA7361
PIN FUNCTION
NAME
FUNCTION
1-2
XTAL OSCILLATOR
Connections for the Colpitts XTAL oscillator.
The XTAL may be replaced by an inductor (see fig. 5)
if the application does not require high stability.
3
MIXER OUT
The Mixer is double balanced to reduce spurious pro·
ducts. The output impedance is 1.8Kn to match the
input impedance of a 455KHz ceramic filter.
4
SUPPLY VOLTAGE
Must be well decoupled with a 1OOnF ceramic capacitor.
5
IF LIMITER INPUT
Input pin of the six stages amplifier with about 50p.V
limiting sensitivity and 1.8Kn input impedance. The if
output is connected to the external quadrature coil
(pin 8) via an internal 1OpF capacitor.
6-7
DECOUPLING
Good quality 100nF ceramic capacitors and a suitable
layout are important.
8
QUADRATURE COIL
A quadrature detector is used to demodulate the 455KHz
FM signal. The Q of the quad coil has direct effect on
output level and distortion (see fig. 6). For proper
operation the voltage should be 100mVrms '
9
AUDIO OUTPUT SIGNAL
The audio Output signal is buffered by an internal
emitter follower.
10
OP AMPLIFIER INPUT
11
OP AMPLIFIER OUTPUT
Because of the Low DC bias, the swing on the operational
amplifier output is limited to 500mV rms '
This can be increased by adding a resistor from the
operational amplifier input to ground.
12
SQUELCH INPUT
13
SCAN CONTROL
14
MUTE
15
GND
Ground connection.
16
10.7MHz MIXER INPUT
Input of the wide-band mixer. Normally used as 1OM Hz/
455KHz converter, it can be also used with input frequencies up to 60MHz.
___________________________
The squelch trigger circuit with a Low bias on the input
(pin 12) will force pin 13 high; and pin 14 Low.
Pulling pin 12 above mute threshold (0.65V) will force
pin 13 to an impedance of about 60Kn to ground and
pin 14 will be an open circuit.
An hysteresis of about 50mV at pin 12 will effectively
prevent jitter.
~~~~~~~~~
_________________________3~/6
897
TDA7361
ELECTRICAL CHARACTERISTICS (Vs = 4V; fo = 10.7MHz; t::.f= ± 3KHz; fm
= 1KHz; Tamb =
25°C unless otherwise noted)
Test Conditions
Paramet.r
Vs
Supply voltage range
Is
Supply current
Squelch OFF
Squelch ON
VI
Input quieting voltage
SIN
Vi
Min.
Typ.
Max.
Unit
1.8
4
9
V
3.8
4.7
mA
= 20dB
8
/lV
Input limiting voltage
-3dB limiting
3
/lV
Vo
Recovered audio output
Vi = 10mV
150
mVrms
Vg
Detector output voltage
1.5
Voc
Rg
Detector output impedance
400
n
Detector center frequency
slope
150
mV/KHz
55
dB
1.5
Voc
20
nA
50
mV
LOW
50
n
HIGH
10
Mn
Gv
Operational amplifier gain
Vn
Operational amplifier output
voltage
18
Operational amplifier input
bias current
VT
Trigger hysteresis
Rm
Mute switching impedance
V I3
Scan vo Itage
f = 10KHz
G v = Vn IVlO
40
Pin 10
Pin 12 HIGH (2V)
Pin 12 LOW (OV)
3.0
0
3.4
0.5
Voc
Gc
Mixer converter gain
30
dB
RI
Input resistance
3.3
Kn
Ci
Input capacitance
2.2
pF
898
TDA7361
Fig. 2 - Test circuit
.VS
10.7MHz
16 1---l11-......---oMIXER INPUT
68
pF
2
15
3
14 ~-----OAUDIO MUTE
4
13 ~-_---oSCAN CONTROL
5
12 1------oSQUELCH INPUT
6
11
CFU455E
~
O.I,uF
_ _ _..... ~.Op. AMPLIFIER
r-vOUTPUT
0.1~
7
TO I--_--I.----""-il
510
9
8
Kfi
7·r5,Kfil--_--OAUDIO OUTPUT
I
33K!l
S-96H
Fig. 3 - Supply current vs. supply
voltage
G 6249'1
-
IS
(rnA)
OP AMPLIFIER
INPUT
10nF
Fig.4 - FM IF characteristics
G-6250
Vo
(dB)
Vo
I\.
-20
./
SQUlLCH
~
I-- ~H
C--- V
FF
-
V
I--I--
I\.
l\.
-40
-60 r--
f--
o
~------------ ~~~~~~g'~9~
OdB = 150mV
Vs = 4V
fo =10.7MHz
f m :: 1KHz
",..,.
r-....
NOISE
I1f =!.3KHz
10
10'RF INPUT
____________
~5~/6
899
TDA7361
Fig. 5 - Colpitts XTAL oscillator
Fig. 6 - Effect of quadrature coil
on audio level and distortion
"a"
G 6251
/" --;
/ /
Q8
.A
DlSTORTION/
0.6
;...
/
0.4
'V
'/to
UDIO
TPUT
/
/
I
0.2
5- 9635
o
10
20
40
30
QUAD COIL Q
Fig. 7 - Application information (49MHz cordless receiver)
lOon
8.2Kn
9 H:::J-~-c
lOr
nF
5-9636
900
.3V
TDA8160
INFRARED REMOTE CONTROL RECEIVER
ADVANCE DATA
•
LOW SUPPLY VOLTAGE (V s = 5V)
•
LOW CURRENT CONSUMPTION (Is = 6mA)
•
INTERNAL 5.5V SHUNT REGULATOR
•
PHOTODIODE DIRECTLY COUPLED WITH
THE I.C.
•
INPUT STAGE WITH GOOD REJECTION
AT LOW FREQUENCY
•
LARGE INPUT DYNAMIC RANGE
•
FEW EXTERNAL COMPONENTS
signed to amplify the infrared signals in remote
controlled TV, Radio or VCR sets. It can be used
in flash transmission mode in conjunction with
dedicated remote control circuits (for example:
M49H94).
Minidip Plastic
The TDA 8160 is a monolithic integrated circuit
in -lead minidip plastic package specially de-
ORDERING NUMBER: TDA8160
TEST CIRCUIT
:r
BPW41N ~
3
C3
47fJF
R3
D
-loy!)
4.7Kn
4
•
TDA8160
11 10fJ S
•
I·
JL.R.1
l.l00fJ S
~Cin
100nF
OUT
5
6
!o-8660'1
4711
June 1988
1/4
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
901
TDA8160
BLOCK DIAGRAM
v,
R3
200K1\.
200Kll.
10K1\.
R2
5-
666211
ABSOLUTE MAXIMUM RATINGS
Vs
Tstg-j
Ptot
Supply voltage
Storage and junction temperature
Total power dissipation at Tamb = 70°C
16
V
-40 to 150°C
400
mW
CONNECTION DIAGRAM
(Top view)
PEAK
OUTPUT
OPEN
DETECTOR
7
DECOUPLING
SUPPLY
VOLTAGE
01 DC BIAS
~2/~4~_______________________ ~~~~~~~~:~~©~
902
GND
INPUT
___________________________
TDA8160
THERMAL DATA
max
Rthj-emb Thermal resistance junction-ambient
ELECTRICAL CHARACTERISTICS (Refer to the test circuit; Vs
= 5V,
200
fo
= 10kHz,
Tamb
=
25°C, unless otherwise specified)
Parameter
Test Conditions
Applied between pin 3 and 6
Min.
Typ.
Max.
Unit
4
5
5.25
V
Vs
Supply voltage
Is
Supply current (pin 3)
V3
Stabilized voltage at pin 3
Gv 1st
Voltage gain (1st stage)
2B
dB
gm2nd
Transconductance (2nd stage)
15
mAN
Vln
Input voltage sensitivity (pin 5)
For full swing at the output pin 1
Rgen = 600n
2
mVp
lin
Input current sensitivity (pin 5)
For full swing at the output pin 1
10
nAp
200
Kn
30
dB
200
mVpp
13 = BmA
Rln
Input impedance
Lf R
Low frequency rejection at the
input stage
C1
N
Noise signal at pin 7
C4 missing
= 100pF
f= 100Hz
6
mA
5.5
V
CIRCUIT DESCRIPTION (See the block diagram)
The infrared light received from D 1 generates an
AC signal that comes in to the device at pin 5.
The capacitor C1 and the integrated 10KU reo
sistor (pin 4) filter out the low frequency noise.
The first stage shows a voltage gain of about
--------------
28dB; the second stage is a voltage to current
converter of 50mA/V (R 2 = Zero). A sensitive
peak detector detects the amplifier signal; one
open collector output (pin 1) gives out the
recovered pulses.
~ ~~~~m~1I~:~~(G~ _ _ _ _ _ _ _ _ _ _ _ _~3/-'4
903
TDA8160
Fig. 1 -
Recommended application circuit for the drive of the IC M491 by means of a Flash Mode I R
Transmitter only, in a TV 16 station memory Remote Control subsystem.
The above shown I R receiver application must be housed inside a metal can shield.
VS=5V!5%
h
47Jl.
AI (MoA). YH(V)-lJY
A2·AI~'
Om.
3314
IIkA
TUNINI,
r--i---...---C:J--~Cl-...-C::l-,--e--C::3-,.-- VOLT"(,t
U
."".
4.7
KJl.
Be297
4.7nF
6.•
Oil.
11
32
27
28
M491
2.
30
33
J,
35
"
2.
",4
19
,.
1.
11
5.6KJ1.
t-+-+-<=--<> +12V
,6
,7
,8
ON/OFF
RELAY
'------::::::T
5-8663
AFT
22ltA
L..---1::::J.-,--VOLU.. E
4_____________
.:.J.4/c:::
904
~ ~~~~m~~~
-------------
TEA1330
FM STEREO DECODER
•
REQUIRES NO INDUCTORS
•
LOW EXTERNAL PART COUNT
•
ONLY OSCILLATOR FREQUENCY ADJUSTMENT NECESSARY
•
INTEGRAL STEREO/MONAURAL SWITCH
WITH HIGH LAMP DRIVING CAPABILITY
The TEA 1330 is a monolithic decoder circuit for
FM stereo transmissions. Packaged in a 16-pin
DIP, it functions with very few external com·
ponents and requires no inductors.
• WIDE SUPPLY RANGE: 3V TO 14V
•
EXCELLENT CHANNEL SEPARATION
MAINTAINED OVER ENTIRE AUDIO FREQUENCY RANGE
•
LOW DISTORTION: TYPICALLY 0.3% AT
150mV (RMS) COMPOSITE INPUT SIGNAL
•
EXCELLENT SCA REJECTION (76dB TYP.)
DIP-16 Plastic
(0.25)
ORDERING NUMBER: TEA1330
BLOCK DIAGRAM
l.p.F.
SEPARATION
CONTROL
S-6057f1
June 1988
1/6
905
TEA1330
ABSOLUTE MAXIMUM RATINGS
Vs
IL
Ptot
Top
Tstg
Supply voltage
Lamp current
Power dissipation T amb = 700 e
Operating temperature
Storage temperature
16
75
800
-25 to 75
-55 to to 150
V
mA
mW
°e
°e
CONNECTION DIAGRAM
(top view)
16
VCO NETWORK
INPUT
15
LOOP FILTER
AMPl1AER
OUTPUT
14
LOOP FILTER
13
PHASE OETECTOR
INPUT
OUT (LEFT)
4
OUT (RIGHT)
5
LED OUT
GNO
SEPARATION
CONTROl
12
19KHz MONITOR
11
LOWPASS FILTER
10
lOWPASS FILTER
8
VCO STOP
$-.6047
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
~2~/6~_______________________ ~!~;~~
906
max
100
°e/W
___________________________
TEA1330
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T amb = 25°C, Vs = 6V, Vi
mV-RMS (L + R = 90%, Pilot 10%), f m = 1 KHz,unless otherwise specified)
Test conditions
Parameter
Vs
Supply voltage range
Id
Current drain
Min.
Typ.
3
Lamp "OFF"
= 300
Max.
Unit
14
V
18
mA
V.
Max standard composite
input signal
d = 1%
300
mV
(RMS)
Vi
Max mono input signal
d = 1%
300
mV
(RMS)
Ri
Input resistance
Sep
Stereo channel separation
I
40
Kn
dB
R2 = variable (*)
35
50
R2 = 270 n
25
40
dB
265
mV
Va
Audio output voltage
CB
Mono channel balance
Pilot tone "OFF"
d
Total harmonic distortion
Vin= 150 mV (RMS)
0.3
%
UR
Ultrasonic frequency rejection
f = 19 KHz
32
dB
f = 38 KHz
48
dB
f = 67 KHz
76
dB
80
dB
1
V
0.8
V
SCA-R SCA rejection ('0)
SIN
Signal to noise ratio
V th
Muting threshold voltage
(pin 9)
-2
ON (VCO stop)
OFF
Lon
Pilot input level for lamp ON
f = 19 KHz
Hys
Pilot input level hysteresis for
lamp turn ON-OFF
f=19KHz
CR
Capture range
\
4
0
6
+2
9
dB
mV
3
dB
±7
%
(*) R2 has to be adjusted for best figure of channel separation.
('*) SCA = AUX. SUB. CARRIER.
---------------------------~~~I~~g~~~~
________________________~3/~6
907
TEA1330
Fig. 1 - Test circuit
r-----~----------~----------4r------O·~
C9
~
JJOOnF
LED
R7
&800
I-------~----OLEFT
vco
STOP
TEA 1330
R8
t----~--.,----.()
RIGHT
22KO
Typical DC Voltages
Pins
1
2
3
4
5
(V)
6
1.9
1.3
3
3
6
7
8
0
0.18
9
10
11
12
13
14
15
16
1.4
1.4
1.2
1.4
1.4
1.4
2.2
Fig. 2 - P.C. board and components layout of the test circuit of fig. 1 (1: 1 scale)
GND
GND
IN
OUT(L)
19KHz
veo
STOP
GND
CS-01Bl
_4~~________________________ ~~~I~~g~~~
908
---------------------------
TEA1330
Fig. 3 - Channel separation
vs. modulation frequency
Fig. 4 - Distortion vs. modulation frequency
1IIIIIIi I
(dB)
Fig. 5 - Channel separation
vs. input level
(dB)
"s,.6V
"s,,6V
1.6
55
.__ ..
50
45
~r::13!imV(90DIo)
f-
J5
PlIot,,15mV(IOO,.)
STEREO
1.2
1\
"\
rttHtIt---t+HHttII
..O'
25
0.4
20
0.:2
10
lK
100
BO
10K
f (Hz)
Pi\ot=IO-J.
1-+--+--t-+-+--tSTEREO r--r--.0
f-1+1-Ht1ll--H-Htttlt-++++HtIt--
i!
100
lK
10K
100
f(Hz)
'T'"-r'--,'-,---,.c.,-,--,--=-r=,
fm"IKHz
r--- fm"IKHz
l ..
r--- STEREO
Pilot",IO"I
2.'
2.0
I
I-+---+--t-+-+--t-I--t--+--t
1.,
40
1.2
,..... V
o.
fm:IKH;;:
1-+---+,'"i".:;":::Om",'+-+-+_I-+-+--t
2' I-+--+--t-+-+-+-I-+-+--t
60
2.4
400 "jlm'l)
I-+--+--t-+-+-+-I-+-+--t
3.2
BO
R~9O"I.
300
d
(~
Vsa6V
200
Fig. 8 - Distortion vs. supply
voltage
Fig. 7 - Channel separation
vs. supply voltage
(dBI
d
1.'
--r-...
20
_ ..
("I. l
2D
,, ,1
H-H-tttltl--H-HHttf-+f++fttIt-,,++,tt-HiiI
10
Fig. 6 - Distortion vs. input
level
2.'
I-+--+--t-+-+--t t~R~~~~.f--f-
1.0
30
"
L.R=135mV(90·/oj
Pilot:l5mV(10"1o)
STEREO
.. I-+---+--t-+-+--t-I--t--+--t
20
l -I100
200
JOO
1000
Vi
10
(mY)
VslV)
10 '1s(Y)
APPLICATION SUGGESTION (see test circuit of fig. 1)
Component
Recommended
value
C1
3.3 }JF
C2
C3 (*)
R3
R4
Purpose
Smaller than
recommended value
Larger than
recommended value
Input coupl ing
Poor low frequency
response and separation
1 }JF
LPF for stereo switch
level detector
Shorter time to switch
mono to stereo
Longer time to switch
mono to stereo
680pF
15 KO
5 KO
Set VCO free relnning
frequency
- High VCO jitter
- Wide capture range
Narrower captu re range
(*) Polyester ± 5%.
------------- ~ !~tm?::~~©~ ____________
;;,..;;;.5/6
909
TEA1330
APPLICATION SUGGESTION (continued)
Component
Recommended
value
15 nF
Smaller than
recommended value
Purpose
Larger than
recommended value
Load and deemphasis
right channel
Low output voltage
Higher distortion for
lowV s
Load and deemphasis
left channel
Low output voltage
3.9Kn
Higher distortion for
low Vs
C6
47 nF
Input PLL coupling
Poor low frequency
response and separation
C7·
C8
R1
220 nF
470 nF
1 Kn
Loop filter
High stereo distortion
Narrower capture range
Excess IC dissipation
Dim lamp
C4
R5 (00)
3.9 Kn
C5
R6 (00)
15 nF
D1
Stereo indicator
R7
Sets lamp current
R2 (000)
270 n
I
Channel separation
(00) Deemphasis = 50 !,s.
(000) Separation can be improved by trimmer adjustement (470 n).
Fig. 9 - Application circuit for portable stereo radio receivers
.v.
220,..F
1(.0
I
IQ.l,..F
680n
veo
STOP
0
22~n
o.'n:
1"F
4.1.4
4ft
'rooF
O·,ll·
4.7n1 p,n
~6/~6~_______________________ ~!~~~~?~~~~~
910
___________________________
TEA2025B
STEREO AUDIO AMPLIFIER
DUAL OR BRIDGE CONNECTION MODES
•
THERMAL PROTECTION
•
FEW EXTERNAL COMPONENTS
•
•
•
WORKS WITH LOW SUPPLY VOLTAGE: 3V
3V .;;;: Vee';;;: 12V
P = 2 x 1W, Vee = 6V, RL = 4[2
P = 2 x 2_3W, Vee = 9V, RL = 4[2
P = 2 x O.lW, Vee = 3V, RI.- = 4[2
•
•
HIGH CHANNEL SEPARATION
•
NO SHOCK NOISE WHEN SWITCH ON OR
OFF
•
MAXIMUM VOLTAGE GAIN OF 45dB
(ADJUSTABLE WITH EXTERNAL RESISTOR)
•
SOFT CLIPPING
Powerdip
12 +2 +2
ORDERING NUMBER: TEA 2025B
MAXIMUM RATINGS
Supply voltage
Output peak current
Junction temperature
Storage temperature
15
1.5
150
-40 to +150
V
A
°C
°C
BLOCK DIAGRAM
9
18
12
11
13
15
14
58a
18Ka
8
7
TEA28258
5
4
3
2
88T£Fl28258-81
June 1988
1/4
911
TEA2025B
PIN CONNECTION
BRIDGE
+Us
OUT.2
BOOT.2
OUT.1
BOOT.1
GND
GND
FEEDBACK
IN. 2 ( + )
GND
GND
FEEDBACK
IN. 1 ( + )
GND (sub.)
SUR
88 I Efl2825-Cf
SCHEMATIC DIAGRAM
Vee
7----------
~--
11
'2I -------------------~,
1
I
3'
,
1
1
1
1
I
1
1
1
I
1
1
I
+-_____+--+__-+_-+-4 0UT2
I
I
1
,
I
GNO
1
L~~
I,·
____________________
r-~o
',.
~
______ _
.'
5
---------n -----------------
1
The tWO power
amphfll,. a,.
1
I,
i l___
1
L -_ _ _ _ _ _ _
~+
l_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-___-_-_-_-_-_-_-_-_-_1~__'
THERMAL DATA
Junction-case thermal resistance
Junction-ambient thermal resistance (See note)
15
60
°C/W
°C/W
Note: The Rth(J-a) is measured on devices bonded on a 10 x 5 x 0.15cm glass-epoxy substrate with a 35'l'm thick
copper surface of 5 cm' .
~2/~4_________________________ ~~~1~~~~~~
912
__________________________
TEA20258
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, Vee = 9V, Stereo unless otherwise specified)
Parameter
Test Conditions
Min
Typ
Max
Unit
Vs
Supply voltage
3
-
12
V
IQ
Ouiescent current
-
40
50
mA
Vo
Ouiescent output voltage
-
4.5
-
V
Av
Voltage gain
43
49
45
51
47
53
dB
± 1
Stereo
Bridge
t.Av
Voltage gain difference
-
-
Rj
Imput impedance
-
30
-
Po
Output power
Vee =9V: RL = 40
RL = 80
1.7
2.3
1.3
Vee =6V : RL = 40
R L =80
0.7
-
dB
kO
f=lKHz;d=10%
Stereo - per chan nel
-
Vee=3V: RL = 40
1
0.6
-
0.1
-
-
-
4.7
2.8
-
W
Bridge
Vee =9V: R L =80
Vee =6V: R L =40
d
Distortion
Vee = 9V; RL = 40
f = 1KHz; Po = 250 mW
Stereo
Bridge
SVR
Vn
Supply voltage rejection
Input noise voltage
RG = 0, Av = 45 dB,
Vrlppl e = 150mV RMS,
f ripple = 100Hz
Cross-talk
__________________________
0.3
1.5
0.5
-
40
46
-
dB
-
-
1.5
3
3
6
p.V
40
55
-
dB
%
Av = 200,
Bandwidth: 20Hz to 20KHz
RG =0
RG = 10kO
CT
-
-
RG = 10kO;
f = 1KHz; RL =40; Po= lW
~~~~~~~~~©~
______________________~3~~
913
TEA2025B
Fig. 1 - Distortion versus output power
Fig. 2 - Distortion versus output power
88 TER2f125B 01
88 '£1128258 02
d
d
(~I
(~I
J
V.
6V
RL
4n
.. 9V
V.
I
RL
8n
[7
/'
J
9.3
'-......
B.l
B.l
~
V
8.83
8.Bl
B.B 1
B
B. 2
8.4
B. 6
8.8
1 Po I WI
Fig. 3 - Distortion versus output frequency
8
8.2
13.4
B.6
88T£1I28258 04
RL • 4n
Po
(W I
Po • 8.25W
5
V. • 9V
I~I
1 PolWI
Fig. 4 - Output power/versus supply voltage
88'£1128258 D3
d
8.8
f
3
•
1KHz
d •
lB~
RL • 4n
8.3
3
V V
'"
,,
,,
1/'
2
V
./
V
8 .1
188
lK
Fig. 5 - Bridge application
18K
f
1Hz I
2
4
6
8
lBV. (VI
Fig. 6 - Stereo application
IN
24~/4~_______________________ ~~~~~~?~:~~~
914
___________________________
TL072
LOW NOISE JFET-INPUT DUAL OPERATIONAL AMPLIFIERS
•
HIGH SLEW-RATE ... 13V/p,s TYP.
•
LOW-NOISE
•
LOW INPUT BIAS AND OFFSET CURRENTS
•
HIGH INPUT IMPEDANCE ... JFET-INPUT
STAGE
•
LOW POWER CONSUMPTION
• WIDE COMMON-MODE AND
ENTIAL VOLTAGE RANGES
voltage temperture coefficient. Each JFET-input
operational amplifier incorporates well-matched,
high-voltage JFET and bipolar transistors in a
monolithic integrated circu it.
Devices with an "I" suffix are characterized for
operation from -25°C to 85°C, and those with a
..c,. suffix are characterized for operation from
OoC to 70°C.
DIFFER-
•
OUTPUT SHORT-CIRCUIT PROTECTION
•
INTERNAL FREQUENCY COMPENSATION
•
LATCH-UP-FREE OPERATION
The TL072 JFET-input operational amplifiers
are designed to offer low-noise high slew-rate,
low input bias and offset current, and low offset
Minidip
(Plastic and Ceramic)
SO-OJ
SCHEMATIC DIAGRAM
(one section)
NONINVERTING
INPUTo---4----,
INVERTING
INPUT
s-
June 1988
OUTPUT
6091
1/7
915
TL072
ABSOLUTE MAXIMUM RATINGS
±18
±30
± 15
-25 to 85
Oto 70
150
-55 to 150
Supply voltage
Differential input voltage
Input voltage
Operating temperature (TL0721)
(TL072C)
Junction temperature
Storage temperature
CONNECTION DIAGRAM AND ORDERING NUMBERS
(Top view)
'-'
OUTPUT
A
11
I2
I
-Vs I '
IN'tINP.
A
NONIN't
INP. A
3
e
7
OUTPUT
B
6
IN'tINP.
B
5
NON INV.
INP. B
o to 70°C
-25 + 85°C
Package
TL072CJG
TL072ACJG
TL072BCJG
TL0721JG
--
Ceramic
Minidip
TL072CP
TL072ACP
TLOBCP
TL072IP
--
Plastic
Minidip
TL072CD
TL0721D
50-8
5-3590
TEST CIRCUITS
10Kll
C L :100pF
Unity gain amplifier
Gain of 10 inverting amplifier
THERMAL DATA
Plastic
Minidip
Rth J-amb Thermal resistance junction-ambient
~2/~7
_________________________
916
Ceramic
Minidip
80-8
max
~~~1~~~~~
___________________________
TL072
ELECTRICAL CHARACTERISTICS (V s = 15V, Tamb = 25°C, otherwise specified)
16
Unit
Min. Typ.
VOS
I nput offset voltage
Rs= 50n
Rs = 50n
Tamb = full range
A V os I nput offset
AT
vo Itage dr ift
los
I nput offset cu rrent
Input bias current
Tamb = full range
VCM
Gv
Large signal voltage
gain
T amb = fu II range
RL ;.2Kn
Vo=± 10V
RL;' 2Kn
Vo=± 10V
Tamb = full range
B
Unity gain bandwidth
RI
I nput resistance
CMR
Common mode
rejection
R s ;'10Kn
Supply voltage
.rejection
Rs;' 10Kn
Supply current
RL =
SVR
Is
3
00
Max. Min.
6
Typ.
Max.
3
3
2
10
6
3
13
7.5
5
9
5
TL072
TL072A
TL072B
TL072
TL072A
TL072B
30
50
5
5
5
10
30
30
30
200
20
+ 11
+12
27
RL = 10Kn
R L ;' 10Kn
R L ;' 2Kn
24
24
20
24
TL072
TL072A
TL072B
TL072
TL072A
TL072B
50
200
80
TL072
TL072A
TL072B
80
± 11
±12
± 12
24
24
20
27
25
50
50
15
25
25
50
50
50
2
2
2
200
200
200
7
7
7
pA
nA
pA
nA
V
V
24
200
200
200
V/mV
3
3
MHz
10"
10"
n
70
80
76
86
dB
70
80
80
76
86
86
25
TL072
TL072A
TL072B
±10
± 11
± 11
mV
jJ.V/oC
10
10
TL072
TL072A
TL072B
TL072
TL072A
TL072B
TL072
TL072A
TL072B
Common mode input
voltage range
VoPP Large signal voltage
swing
TL072
TL072A
TL072B
TL072
TL072A
TL072B
Rs = 500n
T amb = full range
Tamb - full range
Ib
"e"
1"
Test conditions
Parametar
86
86
2.8
5
2.8
dB
5
mA
-------------- ~ !~I~mg~©~ ____________
3/'-'-7
----=0
917
TL072
ELECTRICAL CHARACTERISTICS (continued)
"c"
"I"
Test conditions
Parameter
Min.
Typ.
Max.
Min. Typ.
Max.
Unit
Cs
Channel separation
Gv = 100
120
120
dB
SA
Slew-rate at
VI = 10V
CL = 100pF
A L =2Kn
13
13
V!I"S
Aise time
VI = 20mV
R L =2Kn
0.1
0.1
I"S
Overshot factor
CL = 100pF
10
10
%
nV
tr
Total input noise
voltage
eN
Rs= lOOn
F = 1 KHz
18
18
f = 10Hz to 10KHz
4
4
p.V
~
.JHz
IN
I nput noise cu rrent
f = 1 KHz
0.01
0.01
d
Total harmonic
distortion
Vo = 10Vrms
RS< lKn
R L >2Kn
0.Q1
0.01
.JHz
Fig. 1 - Maximum peak to
peak output voltage vs.
frequency.
f = 1 KHz
Fig. 2 - Maximum peak to
peak output voltage vs.
frequency
%
Fig. 3 - Maximum peak to
peak output voltage vs.
load resistance
G-S03JI1
Vo
30
I
Yo
(V pp )
IIIII
11111111
11111111
1111111
(Vpp I
.
RL_ 'O KA
¥s ",:1:15\1
25
IIlIU
111111
20
111111
111111
IS
25
/
'0
±I;~I~
15
:!::5V
10
.:J:ISY
11m
1111111
20
"tIOV
• __ , v
30
11111
\Is
25
1111111
ALe lKA
15
1111111
1111111
10
V
10
F
t ..
II
IIIIU
111111
111m
'00
1111111
IIIIIU
tOOk
10.
"
,M
100
f (Ha)
Fig. 4 - Large signal voltage
gain and phase shift vs.
frequency
6- SOJ'"
G.
lOOK
1M
f{Hzl
Fig. 5 Supply current vs.
ambient temperature
,.
(dB I
Is
r-'-'--'-r-r-'--r-~.~-'~"~'~"
-~
~
BO
60
""""'
"
\
40
0·
G.
loS·
"~
PHASj SHlr
10
100
1k
10K lOOK
"
\
1M
2.' r--r--:c::t:;::l=l=l=:j:;;-t-H
2.4 1-+-++-+-+"'"-1...1-+-+--1
2.0 1-+-++-+-+-1--1-+-+--1
I.'
1-+-+-+--+-+---1--1-+-+-1
1-+-+-+--+-+---1--1-+-+--1
10·
0.81-+-++-+-+-1--1-+-+--1
0.4 1-+-+-+--+-+---1--1-+-+-'"
...
1
-75
~4/~7_______________________
918
I.r-r-~'--r-r~~r-~~
2.' 1-1-+-...p...,j.......
--1--I-r-+-+-I
I 3S·
10M fOb)
Fig. 6 - Supply current vs.
supply voltage
'''''-)1-1--'--'--+-+-+--11-1-+-1
1.2
20
0.3
0.1
I-+-++-+-+-1;;-,:-;--!..-I+--1
v•• 115\1
3.2 1-+--+r--.--1I-I-+--1::: t!:alr- -
(mAI
\Is • .! 5\1 lo.!.I5Y
RL_l0K4
100
10K
"
-so
-lS
0
25
SO
75 100
J.2 r- =~~al ,-+-++-+-+-+-1
2.4 1-1-+--+--+-+-+--11-1-+-1
2.01-1-+--+--+-+-+--11-1-+-1
1.•
I.'
I-+-+-++-+-+-1I--+--+-1
1-+--+-++-+-+-1I-+--+-1
0.8 1-1-+--+--+-+-+-"'1-1-+-1
0.4 1-1-+--+--+-+-+--11-1-+-1
'.mb(-CJ
~~~~~?~~~
___________________________
TL072
Fig. 9 - Output voltage vs.
elapsed time
Fig. 8 - Voltage follower
large signal pulse response
Fig. 7 - Input bias current
vs. temperatu re
G 5031/1
",,,,:tISY
'. ,
G 504011
(m'
~~=:OKO~F-
'0 _ _
-1
0"l1li_
0.01 ' - '..........1-...L....I.-'-'..........1--'--'-''-'--'-...J
-so
-25
Fig. 10 - Equivalent input
noise voltage vs. frequency
/
/:
12
I:
1\
I
I
r
-. H
f''''
"
\
1/
-2
---7"-
-)
IjOUTPUT
1
OVERSHOOT
20
1\
NPUTI
10"1.
~- f..L f0.5
1.5
2.5
Vs ·,:!:!5V
R L ",2KA
I
I
I
I~
0.1
t (liS)
Fig. 11 - Total harmonic
distortion vs. frequency
Fig. 12
rejection
0.2
0.3
0.4
0.5
t(J.lS)
Common mode
vs. temperature
(n"";;' H-++.'J!-,.IIIUJJ.II~b,,-",,,LLftH#-+-++Htttt-++tt-lttll
t--
60
r-
Avo. 10
AS _100 .n.
v._t'Sv
.7
so
f-\-If-tJ-ItltIr-t+fttllif-tttttt1!t-+t-ttt1ttl
40
Hfltt-ltltlr-t+fttllif-tttttt1!t-+t-ttt1ttl
30
Hf-Htfflk-t+H+tI-II-tttttt1!l-+f+l+HlI
0.,. _ _
0.0 1• _ _
10
AL_l0K.Q
~-+--+--+--.--+--4--+~
••
~-+--+--+--+--+--~-+--4
.5
r--+--+--+--+--+--4--+~
'4
~-+--+--+--+--+--4--+~
.3
~-+--+--+--+--+--4--+~
Hf-H-I+lIIf-t+H+tI-II-tttttt1!l-+f+l+HlI
O.OOI'--!-'7~"--':--'-:--'c."'.~-:---'--C~-:"
10
100
"
10K
f (Hz).
100
,.
10K
f (H:!:)
-50
-25
APPLICATION INFORMATION
Fig. 13 - Low-Noise High Slew-Rate mike preamplifier (G v = 40 dB)
560 F
3.3Kfi
------------- ~ ~~~~m~1r~SJ?~
OUT
5/7
919
TL072
APPLICATION INFORMATION (continued)
Fig. 14 - Second order high Q band pass filter (fo
= 100KHz, Q = 30, gain = 4)
16K.n
220pF
Fig. 15 - Fourth-order subtractive Linkwitz-Riley crossover filter (f = 200Hz)
HIGH-PASS
~-'----~-nOUT
RIO
I1Kfi
Rll
I1Kfi
lOW-PASS
~~~--()OUT
5-919611
Fig. 16 - Frequency response of the 24dB/octave crossover filter of fig. 15
G-G324/1
dB
o
HI(~H-PASS ""-
12
LOW- PASS
/
24
/
\
36
30
________________________
~6/~7
920
100
300
lK
3K
~~~1~~~~
10K
JOK f (Hz)
__________________________
TL072
APPLICATION INFORMATION (continued)
Fig. 17- 20Hz to 200Hz variable High-pass filter (G v = 3dB)
Fig. 18 - Frequency response
of the high-pass filter of fig. 17
O.15~F
INo-J 1---<.---11----1>----"-\
OUT
_'r-~t+HH~/~P1T·TP;~·T'7~'°f-ILJ~~
PlzP2:0
47~
.n
-" 1--+-t+I+Hf--+++++IJ~-++++fj1ll
PI
-" r-~t+H+tIt-~++1Itj1ll--+~+fljjj
5- 52741'
-'a 1-+ltttH1I--+I-++f+HI--+-H+H-Hl
,.
Fig. 19 - Unity-gain absolute-value circuit
tOKA
lOKA
100
300 t (Hz)
Fig. 20 - Single supply sample and hold
10 K.fl.
10KA
IN
o--C:J-+--'--P'OUT
VIN
OtotOV
Vc
5-6750
10Kft
1 "HOLD 0---<>--1
Q"SAMPLE
Fig. 21 - Output current to voltage transformation for a DA converter
F-{=H--0
Vret
(*) The value of C may
be selected to minimize overshoot and
ringing (C '" 68 pFI.
5-611,1,/1
c*
-VS=lSV
Settling time to within 1/2 LSB (± 19.5 mY) is approximately 4.0 JJS from the time all bits are switched.
Theoretical V0
v ..
o
V ref
RI
(A)
0
:
[~+~+R+M..+&+~+-AL+~l
2
4
8
16
32
64'
128
256
Adjust V ref. Fi 1 or Ro so that V 0 with all digital inputs
at high level is equal to 9.961 volts.
V ref = 2.0 Vdc
Rl = R2 '" 1.0 kG
Ro = 5.0 kG
vo =
*
15 kl [
+ + -i
+
=
10V [
+
+
~~~ 1 =
~
+
Ji
+
~ + 1~8 + 2~61
9.961V
7/7
921
TL074
LOW NOISE JFET-INPUT QUAD OPERATIONAL AMPLIFIERS
•
LOW-NOISE
•
LOW INPUT BIAS AND OFFSET CURRENTS
•
HIGH INPUT IMPEDANCE ... JFET-INPUT
STAGE
•
LOW POWER CONSUMPTION
• WIDE COMMON-MODE AND
ENTIAL VOLTAGE RANGES
DIFFER-
•
OUTPUT SHORT-CIRCUIT PROTECTION
•
INTERNAL FREQUENCY COMPENSATION
•
LATCH-UP-FREE OPERATION
•
HIGH SLEW-RATE ... 13V//ls TYP.
The TL074 J F ET -input operational amplifiers
are designed to offer· low-noise high slew-rate,
low input bias and offset current, and low offset
voltage temperature coefficient. Each J F ET -input
operational amplifier incorporates well-matched,
high-voltage JFET and bipolar transistors in a
monolithic integrated circuit.
Devices with an "I" suffix are characterized for
operation from -2SoC to 8SoC, and those with a
"c" suffix are characterized for operation from
OoC to 70°C.
DIP-14
(Plastic and Ceramic)
SO-14J
SCHEMATIC DIAGRAM
(one section)
NONINVERTING
INPUTO-----1---INVERTING
INPUT
OUTPUT
6411.
s-
June 1988
6091
1/7
923
TL074
ABSOLUTE MAXIMUM RATINGS
± 18
±30
± 15
-25 to 85
to 70
150
-55 to 150
Supply voltage
Differential input voltage
Input voltage
Operating temperature (TL0741)
(TL074C)
Junction temperature
Storage temperature
o
CONNECTION DIAGRAM AND ORDERING NUMBERS
(Top view)
OUTPUT A
14
OUTPUT 0
lNV.INP. A
13
INV.INP. 0
12
NON INV.INP. 0
11
-Vs
10
NON INV.INP.C
NON INV. INP. A
NON INV.INP. B
3
5
INY.INP. B
INY.INP.C
OUTPUT B
OUTPUT C
o to 70°C
-25 + 85°C
Package
TL074CJ
TL074ACJ
TL074BCJ
TL0741J
-
Ceramic
DIP-14
TL074CN
TL074ACN
TL074BCN
TL0741N
-
Plastic
DIP-14
TL074CD
TL0741D
50-14
-
5-3901
TEST CIRCUITS
10K 11
Vi o--C:J-......-t
C L =100pF
s- 6740
Unity gain amplifier
Gain of 10 inverting amplifier
Ceramic
DIP-14
THERMAL DATA
Rth j-amb
Thermal resistance junction-ambient
Plastic
DIP-14
max
~2/~7________________________ ~~~1~~&'~~
924
SO-14
__________________________
TL074
ELECTRICAL CHARACTERISTICS
(V s = 15V, Tamb = 25°C, otherwise specified)
··c·,
"1"
Parameter
Test conditions
Unit
Min. Typ. Max.
Vos
I nput offset voltage
Rs = 50n
Rs = 50n
Tamb = full range
/!; V os
~
I nput offset
voltage drift
los
Input offset current
Input bias current
Tamb = full range
VCM
Common mode input
voltage range
VoPP Large signal voltage
swing
Gv
Large signal voltage
gain
T amb = full range
R L ;;'2Kn
Vo=± 10V
B
Unity gain bandwidth
RI
I nput resistance
CMR
Common mode
rejection
Rs;;' 10Kn
Supply voltage
rejection
R s ;;'10Kn
Supply current
RL =
IS
6
3
3
2
9
10
TL074
TL074A
TL074B
TL074
TL074A
TL074B
5
TL074
TL074A
TL074B
TL074
TL074A
TL074B
30
TL074
TL074A
TL074B
RL;;'2Kn
Vo=± 10V
Tamb = full range
SVR
3
Rs =50n
Tamb = full range
Tamb = full range
Ib
TL074
TL074A
TL074B
TL074
TL074A
TL074B
Min. Typ.
27
TL074
TL074A
TL074B
TL074
TL074A
TL074B
50
200
24
30
30
30
80
TL074
TL074A
TL074B
80
±10
± 11
± 11
± 11
± 12
±12
24
24
20
27
25
50
50
15
25
25
25
TL074
TL074A
TL074B
--------------------------~I~I;~~~©~
200
± 12
24
24
20
00
5
5
5
20
RL = 10Kn
RL ;;.10Kn
RL;;' 2Kn
10
6
3
13
7F>
5
mV
Ip.V/oC
10
50
10
± 11
Max.
50
50
50
2
2
2
200
200
200
7
7
7
pA
nA
pA
nA
V
V
24
200
200
200
V/mV
V/mV
3
3
MHz
10"
10"
n
86
86
5.6
10
70
8a
80
76
70
80
80
76
86
86
dB
86
86
5.6
dB
10
mA
________________________~3/7
925
TL074
ELECTRICAL CHARACTERISTICS (continued)
"e"
"I"
Test conditions
Parameter
Min.
Typ.
Max.
Min. Typ.
Unit
Max.
Cs
Channel separation
G v = 100
120
120
dB
SR
Slew-rate at
unity gain
Vi = 10V
C L = 100pF
RL=2Kn
13
13
V/jJ.s
Rise time
VI = 20mV
RL=2Kn
0.1
0.1
jJ.S
Overshot factor
CL = 100pF
10
10
%
tr
Total input noise
voltage
eN
Rs = lOOn
IN
Input noise current
f = 1KHz
d
Total harmonic
distortion
V o -l0Vrm.
Rs < lKn
RL >2Kn
Fig. 1 - Maximum peak to
peak output voltage vs.
frequency.
f = 1KHz
lB
18
nV
y'Hz
f = 10Hz to 10KHz
4
4
jJ.V
0.01
0.Q1
~
y'Hz
0.Q1
0.Q1
%
f = 1KHz
Fig. 2 - Maximum peak to
peak output voltage vs.
frequency
CO-SOUIt
v,
11l1m
llll~
1111111
(V,. )
'0
G- 503311
V,
I II IlID
(V pp )
RL"IOKA
Vs ",.:i::ISV
25
1111111
20
1111111
1111111
A l ", ZKA
2S
Illill
,s
111111
I 111m
'0
11111
111111
tOOK
'00
f eHd
1M
Fig. 4 - Large signal voltage
gain and phase shift vs.
frequency
6- 503511
G,
(dB )
,.
I
10K
lOOK
,
-
'.4
..,
-- I-\.
4.'
"tt
.-
"
PHASi SHlr
No siQnalr-- r No I~d
........
........
Fig. 6 - Supply current vs.
supply voltage
I.r-'-'--r-'-'--r-,--r~~
(~I~+-~-L-+~~+-1-~-+~
• :t 15'1
100
lit
10K
45-
3.2
2.4
20
lOOK
"
'\
1M
.0'
,,.'
,10'
,.,
o.
10M f(H%J
~4~f7_________________________ ~!~I~~~~©~
926
0)7'
0.'
~
.. _ ::~~al .--+-+-+-+-+-+-1
,~ r-t-I:~~=+~~~r-t-l
4.• ~+-+-+-+~--+-1-~-+~
O'
\
X)
0.'
,(Hz)
I I
"
'Is
Rl_'OKA
"
1M
Fig. 5 Supply current vs.
temperature
'Is • ± 5V to±15Y
60
/
1111111
IIlIli
(rnA )
.0 ......
V
'0
-.V
11I1i1
'Ok
/'
20
tl;~~
±5V
'0
'00
v. ,,_, v
'0
,s
1111111
,.
I II 11m
111/1
111111
111111
llWI
20
1111In'
'00
IIIII!
'Is • .t:1SV
"
tlOY
IS
Fig. 3 - Maximum peak to
peak output voltage vs.
load resistance
'.2
2.10
..6
~+-+-+-+~--+-1-~-+---j
~+-+-+-+~f--+-1-~-+~
1-+--+--+--+-1--+-+--+-+-1
4
6
8
10
12
14
16 Vs (!:V)
___________________________
TL074
Fig. 7 - Input bias current
vs. temperatu re
..
•..
__-
•.•• U-L-LLLl....L...LUU..LLLJ
-50
-25
25
50
75
Fig. 8 - Voltage follower
large signal pu Ise response
&·'50:11"
Vs .. ~15Y
-1
-,
-,
100 tarnb{"'C1
12
1\
!/
I
••
..
,
1\
I
..
,
0.001
'00
Vs ,,:!:: 15V
RL'"ZK.fl.
1.5
2
2.5
t
1:"'-";
"
(psI
0.1
Fig. 11 - Total harmonic
distortion vs. frequency
f 1Hz)
Ii
I:
II
.....
I
~- f.l. -
.
••
J. ....
I
Fig. 12
rejection
0.2
0.3
0.4
0.5
t(psl
Common mode
vs. temperature
(dB)
r--r-..--....,..-r-...,-,-.!.:f!!~
.,
~-+-~~~r-~~~4-~
'I 5 .. 1:15Y
RLalOKIl
"
0.01,
,.
o~~~~
I
INPUT
•. 5
,!"
,.
\
1 /
8
-4
2.
-T
/OUTPUT
C.-S04011
v.
(mV )
~t::O~~F-
Fig. 10 - Equivalent input
noise voltage vs. frequency
3.
Fig. 9 - Output voltage vs.
elapsed time
83
.,
....,
..
f (Hz)
-50
-25
25
50
75
TiI~·C)
APPLICATION INFORMATION
Fig. 13 - Low-Noise high Slew-Rate mike preamplifier (G v = 40dB)
560 F
3.3 K II
___________________
~!~~~&~~
OUT
______________________
~5~/7
927
TL074
APPLICATION INFORMATION
(continued)
Fig. 14 - Second order high Q band pass filter (fo = 100KHz, Q = 30, gain = 4)
16K.n.
220pF
INo--t43::::K}::Jl+_U _+.p...
~"""-oOUT
1.5K.!l
Fig. 15 - 100KHz quadrature oscillator
lN414B
lBKA(S•• Note"')
~--I...--_-rI---O-15V
6 sin wt
lBpF
1 Kn
18pF
"'5V
,,'5V
6 cos wt
~~----~-o
lKA
-15V
18K A
L_-~--~-C::J--o+15V
lN414B
(5 •• Not.",)
s. -
BB_4 KA
6090
Note A: these resistor values may be adjusted for a simmetrical output
Fig 16 - 20Hz to 200Hz variable High-pass filter (G v = 3dB)
Fig. 17 - Frequency response fo the high-pass
filter of fig. 16
OUT
-I. f--+-I-++Y-f-+j.iJ.j4ll--++++fjjjj
,10
928
30
100
300 t (Hz)
TL074
APPLICATION INFORMATION (continued)
Fig. 18 - Unity-gain absolute-value circuit
tOKA
10Kll
10 K.1l
tOKA
IN
o--C:r-+-----'..p..
OUT
Otol0V
Fig. 19 - Single supply sample and hold
Fig. 20 - Output current to voltage transformation for a DA converter
+V s ·5V
13
i-"'---{:=Jr-...--Q
MS! A1
..
v,.,
.,
.2
Me150a
MC11008
A'
AI
Vo
A7
.8
L.S.-
(.) The value of C may
be selected to minim ize overshoot and
ringing (C '" 68 pF).
I.
Ro
c*
-V5=15V
Settling time to within 1/2 LS8 (± 19.5 mV) is approximately 4.0 /J.S from the time all bits are switched.
Theoretical V 0
V
a
:
=~(R )[~+g+~+M..+~+~+~+~]
R1
. a
V,ef= 2.0 Vdc
Rl = R2 '" 1.0 kG
Ro = 5.0 kG
2
4
8
16
32
64'
128
256
Adjust Vref • Rl or Ro so that Vo with all digital inputs
at high level is equal to 9.961 volts.
Va'
*'
(5 kl [
+ + -i
+
• 10V [
+
~~~
+
1•
-,k + i2 + & +
1~8 + 2~6 I
9.961V
7/7
929
TL082
JFET-INPUT DUAL OPERATIONAL AMPLIFIERS
•
HIGH SLEW-RATE ... 13 V//ls TYP.
•
•
LOW· POWER CONSUMPTION
WIDE COMMON-MODE AND DIFFERENTIAL VOLTAGE RANGES
LOW INPUT BIAS AND OFFSET CURRENTS
OUTPUT SHORT-CIRCUIT PROTECTION
HIGH INPUT IMPEDANCE ... JFET -INPUT
STAGE
INTERNAL FREQUENCY COMPENSATION
LATCH-UP-FREE OPERATION
•
•
•
•
•
The TL082 JFET-input operational amplifiers
are designed to offer high slew-rate, low input
bias and offset current, and low offset voltage
temperature coefficient. Each J FET -input oper-
ational amplifier incorporates well-matched,
high-voltage J FET and bipolar transistors in a
monolithic integrated circuit.
Devices with an "I" suffix are characterized for
operation from _25°C to 85°C, and those with a
"C" suffix are characterized for operation from
O°C to 70°C. The "M" devices are characterized
for operation from -55 to 125°C.
Minidip
(Plastic and Ceramic)
SO-8J
SCHEMATIC DIAGRAM
(one section)
OUTPUT
June 1988
1/7
931
TL082
ABSOLUTE MAXIMUM RATINGS
v5
Vis
VI
Top
TJ
T stg
Supply voltage
Differential input voltage
Input voltage
Operating temperature (TL0821)
(TL082C)
(TL082M)
Junction temperature
Storage temperature
± 18
±30
±15
-25 to 85
Oto 70
-55 to 125
150
-65 to 150
V
V
V
°c
°c
°c
°c
°c
CONNECTION DIAGRAM AND ORDERING NUMBERS
(Top view)
OUTPUT
A
OUTPUT
INV.INP.
A
B
NON INV.
INP.A
6
IN'lJNP
NON INV.
IN!? B
o to 70°C
-25 to 85°C
-55 to 125°C
TL082CJG
TL082ACJG
TL082BCJG
TL0821JG
TL082MJG
TL082CP
TL082ACP
TL082BCP
'TL082IP
TL082CD
TL0821D
-
-
-
-
Package
Ceramic
Minidip
Plastic
Minidip
-
-
SO-8
5-3590
TEST CIRCUITS
10K 11
1Kll.
Vi o--CJ--2Kn
V o =± 10V
R L >2Kn
Vo=± 10V
T amb = full range
B
RI
I nput resistance
Common mode rejection
Is
Supply volags rejection
Supply current
5
3
2
6
9
TL084
TL084A
TL084B
TL0B4
TL084A
TL0B4B
5
15
6
3
20
7.5
5
3
9
mV
15
10
TL084
TL084A
TL084B
TL084
TL084A
TL084B
30
5
5
5
100
10
30
30
30
200
20
± 11
± 12
RL = 10Kn
R L >10Kn
R L >2Kn
24
24
20
27
TL084
TL084A
TL084B
TL0B4
TL084A
TL084B
50
200
24
25
Unity gain bandwidth
CMR
SVR
3
10
TL084
TL084A
TL084B
Common mode input
VoPP Large signal voltege
gain
Unit
R,=50n
Tamb = full range
V CM
TL084
TL084A
TL084B
TL084
TL084A
TL0B4B
Tamb = full range
T 8mb = full range
Ib
"M"
Min. Typ, Max. Min. Typ. Max. Min. Typ. Max.
± 10
± 11
+ 11
+ 12
± 11
± 12
24
24
20
27
25
50
60
15
25
25
200
200
200
R,>10Kn
RL
=-
__________________________
TL084
TL084A
TL084B
80
TL084
TL084A
TL084B
80
86
86
5.6
~!~~;~~~
5
400
200
200
10.
7
7
30
11.2
100
pA
20
nA
200
pA
50
nA
± 11
± 12
V
24
24
20
24
27
V
24
V/mV
15
10"
10"
R,>10Kn
200
100
100
5
3
3
3
3
~vrC
10
70
80
80
76
86
86
80
70
80
80
76
86
86
80
5.6
3
MHz
10"
.11
86
dB
86
dB
11.2
5.6
11.2
mA
________________________
~3/7
941
TL084
ELECTRICAL CHARACTERISTICS (Continued)
Test Conditions
Parameter
"."
"c"
120
120
"M"
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
120
dB
13
VI".
0.1
10
0.1
10
/.IS
26
25
CS
Channel separation
Gv = 100
SR
Slew-rate at
VI= 10V
C L = 100pF
RL=2Kn
13
12
unity gain
Rise time
Overshot factor
VI=20mV
CL = lOOpF
RL=2Kn
0.1
10
Total Input nol••
Voltage
Rs= lOOn
f= 1KHz
25
t,
eN
Fig. 2 - Maximum peak to
peak output voltage vs.
frequency
6-50321t
1lllr
mmr
30
IIII~
(V pp )
F11111
10K
"
lOOK
1M
100
f eH;
Fig. 4 - Large signal voltage
gain and phase sh ift vs.
frequency
G- SOSSI!
G,
'.B
,.
100"--1-..
60
""
40
\:
lOOK
1M
I(Hz)
..
A)'!-+--+--+----+-If...-,j"......L,...b,..+-I
v... :t1!IV
10K
0.3
Fig. 6 - Supply current vs,
supply voltage
I.r-""--r~-,--~~,--r~~
(... ,'I-+---L----'--I-I--+--+--+-+-I
.-+-++-+--+-1-1
... f-- :::::'"
••
'Ar-t-I:~~~=F~~-t-l
I-+-~-~~f'-+---+--,--I-~
46'
"IK
0.1
'.4 1-+---jr-....I-+-+-+-l:::~!:~.Ir-~
lOOK
'\
90'
2.41-+-++-+-1-1-+-++---1
I.• 1-+--+-+-+-1-1-+-++---1
,,' .. 1-+-++-+-1-1-+-++---1
I.' 1-+--+--+--1-1-+-+-+-+-1
1
I 00'
1M
10M
f(H:r:)
-75 -50 -25
:::.!4/:..:,7_ _ _ _ _ _ _ _ _ _ _ _
942
111111
0'
"~:
~
PHASj SHill " '
100
V
/
II
111111
10K
4.' I-+-+-+--+-Ips.~+--+--+-I
20
10
n
~
15
10
Is ..-.,..-...,........,...--.--,,--..-..,.-~.-:..!'.;!.'~'
(m
Vs • .:!: 5'1 to'±15v
RL·l0KA
80
..
25
20
Fig. 5 - Supply current vs.
temperature
)
~
III
III
10
TTTIIIr
TTTIIIr
TTTIIIr
100
IJI,,!
f=,
15
:t5v
10
IIIII
20
II 111m
V. a_I V
30
Vs .• ± 15'1
Z5
rmr
IS
IYppl
I111m
IIIIIH
111111
1111111
tlOV
20
Fig. 3 - Maximum peak to
peak output voltage vs.
load resistance.
y.
11111IIf
Rla 2K.Q.
111111
v•• :1:15'1
15
nV
G-S033/1
y.
1IIIm
Rl"IOKA
Illlf
%
-.1Hz
Fig. 1 - Maximum peak to
peak output voltage vs.
frequency.
)
8
0
2S
50
7'5 100
' .."'bl·C)
4
6
a
10
12
14
16 Vs{:!::V)
l:fi. ~~I~m?~~~JI -------------
TL084
Fig. 8 - Voltage follower
large signal pulse response
Fig. 7 - Input bias current
vs. temperature
_.....-
G SOIl"
Vs ·:t15V
~~::O~npF-
..
0.01 L....1-l.-"--'-.l-L....1-l.-"--'-.l-L....1-L....J
-50
-25
25
50
75
(nV/~) I-l-HfJ;u"-Lll.'
,. •bs;\;y.l.lfMtt-t-H-ItHII-1-++HHlI
AVO" 10
6.
RS·l00A
1+t+i-ttltIt-H-ttHllIf-++ttHjf/---+l+t+HII
-
!l
H
-,
...
I
i\
~- f.l..
...
2.5
-
10K
f (Hz)
0.1
0.2
0.3
0.4
0.5
1 (,.,s)
Fig. 12 - Common mode
rejection vs. temperature
,...
,
-
•..,
AVO .1
Vj(RMS) ,,6V
..
I
,
••
:1
~
-<
Fig. 11 Total harmonic
distortion vs. frequency
..=R;··SISV
'IslEt '!iV
RL_ZK.fi.
I
<.,s)
t
.,
'00
l""
Ii
I :,
....
0,01
••
---r
"
4.
3.
OVERSHOOT
I
'"PUT
-4
'·504 0
I
16
\
1\
1/
-2
-.
1m' I
2•
/OUTPUT
I
100 Tamb(-C I
Fig. 10 - Equivalent input
noise voltage vs. frequency
s.
--
Fig. 9 - Output voltage vs.
elapset time.
.......
'K
~-+-+--+--~~--~-4r-~
1--t-+--+-1--1--~-1r-1
••
1--t--+--+--1--1--~-1~1
.3
~-+--+--+--~~---r-4--~
,!
I
.,
•
.6
.s
'.K
, .,
-so
f (Hz)
-25
APPLICATION INFORMATION
Fig. 13 - Second order high Q band pass filter (fo
= 100KHz, Q = 30, gain = 4)
16K.n
220pF
30KD.
43Kll
INo--C:::J-+-U--+-F"1.5Kll
OUT
943
TL084
APPLICATION INFORMATION
Fig. 15 - High Q Notch filter
Fig. 14 - 0.5 Hz square wave oscillator
+15V
INPUT
OUTPUT
IKA
R1
9.IKA
s· 6088
C1
= R2 = 2R3 = 1.5Mn
C3
= C2 =2= 110 pF
1
f=
fo = 27TR1 Cl = 1 KHz
Fig. 16 - 100 KHz quadrature oscillator
1N4148
18KA(See Note A)
-ISV
6 sin Colt
18pF
1K n
""'5 V
~~________~_6<)coswt
1KA
-15V
18KA
L..----lW------e-lr-=J-O+1SY
1N4148
5 - 6090
(See NoteA)
88.4KA
Fig. 17 - 20 Hz to 200 Hz variable High-pass filter (G y = 3 dB)
Note A: These resistor
values may be adjusted for a symmetrical
output.
Fig. 18 - Frequency response
of the high-pass filter offig.17
•• 1---H4+fHII--+++-++tJlI--H4+1+fll
OUT
-n 1-+i-++~-+++-+fijIl-+i-++f+!lI
-1'1--+-+++I41lI--+-++WII--+-++H-HlI
-'4 1--+-+-iII-I+HI--+-+lt+J.IIlI--+-+-l+l+UI
-,ol--+--J4+!-H!I--+..H+I+l1I1--+-++H-HlI
10
JO
100
300 t (Hz)
~6/~7________________________ ~~~~~~~~ __________________________
944
TL084
APPLICATION INFORMATION (continued)
Fig. 19 - Unity-gain absolute-value circuit
10Kl1
10Kl1
10 K1l.
+15V
lN4148
IN V"""'------'--,.-----,
IN.lo148
10K11
Fig. 20 - Single supply sample and hold
Vc
, = HOLD
o-~'---i
Q"SAMPlE
Fig. 21 - Output current to voltage transformation for a DA converter
+Vs .SV
Mse A1
..
.2
.3
••
••
• 7
LS[II
A8
(') The value of C may
be selected to min imize overshoot and
ringing (C '" 68 pF).
Settling time to within 1/2 LSB (± 19.5 mV) is approximately 4.0 /J-S from the time all bits are switched.
Theoretical V0
V
o
:
=~{R )[~+~+&+~+~+~+~+~]
R1
0
V,ef= 2.0 Vdc
Rl = R2 '" 1.0 kO
Ro = 5.0 kO
2
4
8
16
32
64'
128
Vo =--H'-15kl[
++++-i+~+-i2+~+ 1~8+ 2~61
256
Adjust Vref. R 1 or Ro so that V0 with all digital inputs
at high level is equal to 9.961 volts.
= 10V
[
~~: 1 =
9.961V
7/7
945
PACKAGES
947
TECHNICAL NOTE
DESIGNING WITH THERMAL IMPEDANCE
by T. Hopkins, C. Cognetti, R. Tiziani
REPRINT FROM "SEMITHERM PROCEEDINGS~~ S. DIEGO (U.S.A.) 1988.
ABSTRACT
Power switching techniques used in many modern
control systems are characterized by single or
repetitive power pulses, which can reach several
hundred watts each. In these applications where the
pulse width is often limited to a few milliseconds, cost
effective thermal design considers the effect of thermal
capacitance. When this thermal capacitance is large
enough, it can limit the junction temperature to within
the ratings of the device even in the presence of high
dissipation peaks. This paper discusses thermal
impedance and the main parameters influencing it
Empirical measurements of the thermal impedance of
some standard plastic packages showing the effective
thermal impedance under pulsed conditions are also
presented.
INTRODUCTION
Power switching applications are becoming very
common in many industrial, computer and automotive
ICs. In these applications, such as switching power
supplies and PWM inductive load drivers, power
dissipation is limited to short times, with single or
repeated pulses. The normal description of the thermal
performance of an IC package, Ath O-a) Ounction to
ambient thermal reSistance), is of little help in these
pulsed applications and leads to a redundant and
expensive thermal design.
This paper will discuss the thermal impedance and the
main factors influencing it in plastiC semiconductor
packages. Experimental evaluations of the thermal
performance of small signal, medium power, and high
power packages will be presented as case examples.
The effects of the thermal capacitance of the packages
when dealing with low duty cycle power dissipation
will be presented and evaluated in each of the example
cases.
The thermal resistance, Ath, quantifies the capability
of a given thermal path to transfer heat. The general
definition of resistance of the thermal path, which
includes the three different modes of heat dissipation
(conduction, convection and radiation), is the ratio
between the temperature increase above the reference
and the heat flow, L::.P, and is given by the equation:
L::.T
L::.Q
L::.t
where: L::.Q = heat
L::.t =time
Thermal capacitance, Cth, is a measure of the
capability of accumulating heat, like a capacitor
accumulates a charge. For a given structural element,
Cth depends on the specific heat, c, volume V, and
density d, according to the relationship:
Cth=cdV
The resulting temperature increase when the element
has accumulated the heat Q, is given by the equation:
L::.T= L::.Q/Cth
The electrical analogy of the thermal behavior for a
given application consisting of an active device,
package, printed circuit board, external heat sink and
external ambient is a chain of RC cells, each having
a characteristic time constant:
r=RC
To show how each cell contributes to the thermal
impedance of the finished device consider the
THERMAL IMPEDANCE MODEL FOR PLASTIC simplified example shown in figure 1. The example
PACKAGES
device consists of a dissipating element (integrated
The complete thermal impedance of a device can be circuit) soldered on a copper frame surrounded by a
modeled by combining two elements, the thermal plastic compound with no external heat sink. Its
resistance and the thermal capacitance.
equivalent electrical circuit is shown in figure 2.
June 1988
1/14
949
Fig. 1 - Simplified Package Outline
<
r-----'---~
Fig. 2 - Equivalent Thermal Circuit of Simplified Package
R thsi
MOLD
R th frame R th mold
CHIP
~FRAME
C th si
C th frame C t h mold
5-10621
5-10622
The first cell, shown in figure 2, represents the thermal
characteristics of the silicon itself and is characterized
by the small volume with a correspondingly lowthermal
capacitance, in the order of a few mJ/oC. The thermal
resistance between the junction and the silicon/slug
interface is of about 0.2 to 2 OC/W, depending on die
size and on the size of the dissipating elements existing
on the silicon. The time constant of this cell is typically
in the order of a few milliseconds.
After the plastic has heated, convection and radiation
to the ambient starts. Since a negligible capacitance
is associated with this phase, it is represented by a
purely resistive element
When power is switched on, the junction temperature
increase is ruled by the heat accumulation in the cells,
each following its own time constant according with
the equation:
The second cell represents the good conductive path l:\T=Rth Pd[1-e(tlT)]
from the silicon/frame interface to the frame periphery.
In power packages, where the die is often soldered The steady state junction temperature, Tj, is a function
directly to the external tab of the package, the thermal of the Rth U- al of the system, but the temperature
capacitance can be large. The time constant for this increase is dominated by thermal impedance in the
cell is in the order of seconds.
transient phase, as is the case in switching applications.
From. this point, heat is transferred by conduction to
the molded block of the package, with a large thermal
resistance and capacitance. The time constant of the
third cell is in the order of hundreds of seconds.
A simplified example of how the time constants of each
cell contribute to the temperature rise is shown in figure
3 where the contribution of the ceiis of figure 2 is
exaggerated for a better understanding.
Fig. 3 - Time Constant Contribution of Each Thermal Cell (Qualitative Example)
TIME OR PUlSE UIDTH ( A.U.)
_2;.,./1_4_ _ _ _ _ _ _ _ _ _ _ _ ~
950
~~~~m?::~lt--------------
When working with actual packages, it is observed that
the last two sections of the equivalent circuit are not
as simple as in this model and possible changes will
be discussed later. However, with switching times
shorter than few seconds, the model is sufficient for
most situations,
dations to some extent, as it is based on test patterns
having, as dissipating element, two power transistors
and, as measurement element, a sensing diode placed
in the thermal plateau arising when the transistors are
biased in parallel.
The method used has been presented elsewhere (2)
for the pattern P432 (shown in figure 4), which uses
two small (1000 sq mils) bipolar power transistors and
EXPERIMENTAL MEASUREMENTS
has a maximum DC power capability of 40W (limited
by second breakdown of the dissipating elements),
When thermal measurements on plastic packages are
A similar methodology was followed with the new H029
performed, the first consideration is the lack of a
pattern, based on two D-Mos transistors (3) having a
standard method, At present, only draft specifications
total size of 17,000 sq mils and a DC power capability
exist, proposed last year and not yet standardized (1),
of 300 W on an infinite heat sink at room temperature
The experimental method used internally for evaluations (limited by thermal resistance and by max operating
since 1984 has anticipated these preliminary recomen- temperature of the plastics),
Fig. 4
a) P432 Test Die
D.C.
D.C.
SUPPLY
SUPPLY
D,C,
FAST
SUPPLY
DVM
PULSE
GENERATOR
STORAGE
SCOPE
b) P432 Measurement System
____________________________ ~~~~~~?~'f~~~------------------------3-I-l-4
951
Using the thermal evaluation die, four sets of
measurements were performed on an assortment of
insertion and surface mount packages produced by
SGS-Thomson Microelectronics. The complete characterization is available elsewhere (4). The four
measurements taken were:
1) Junction to Case Thermal Resistance (Power
Packages)
2) Junction to Ambient Thermal Resistance
3) Transient Thermal Impedance (Single Pulse)
4) Peak Transient Thermal Impedance (Repeated
Pulses)
Fig. 5
a) H029 Test Die
b) H029 Measurement System
_4;.../1_4_ _ _ _ _ _ _ _ _ _ _ _
952
~ ~~~~m~T:~~lt--------------
Fig. 6 - Set-up for Rth (j _ c) Measurement
PRESSURE CLIPPING
CONNECTION
THIN WIRES
WATER-COOLED
COPPER BLOCK
\..THERMAL
GREASE
5-9785
THERMOCOUPLE
The junction to case thermal resistance measurements
were taken using the well known setup shown in figure
6 where the power device is clamped against a large
mass of controlled temperature.
The junction to ambient thermal resistance in still air,
was measured with the package soldered on standard
test boards, described later, and suspensed in 1 cubic
foot box, to prevent air movement
The single pulse transient thermal impedance was
measured in still air by applying a single power pulse
of duration 10 to the device. The exponential
temperature rise in response to the power pulse is
shown qualitetively in figure 7. In the presence of one
single power pulse the temperature, !::.. Tmax, reached
at time 10, is lower than the steady state temperature
calculated from the junction to ambient thermal
resistance. The transient thermal impedance Ro, is
obtained from the ratio!::.. Tmax/Pd.
Fig. 7 - Transient Thermal Response for a Single Pulse
Tmax -t------..
Tamb
Pd
-L----I--------=="""'----
J ____ --''____ __
to
5-9784
______________________ ~~~~~~?~~:~~~-------------5~/~1~4
953
The peak transient thermal impedance for a series of
repetitive pulses was measured by applying a string
of power pulses to the device in free air. When power
pulses ofthe same height, Pd, are repeated with a given
duty cycle, DC, and the pulse length, tp, is shorter than
the total time constant of the system, tlie train of pulses
is seen as a continuous source with mean power level
given by the equation:
Fig. 8 - Transient Thermal Response for Repetitive
Pulses
a multileaded power package in which the die is
attached directly to the tab of package using a soft
solder (Pb/Sn) die attach. The tab of the package is
a 1.5 mm thick copper alloy slug. The thermal model
of the MULTIWATT, shown in figure 9b, is not much
different from that shown in figure 2. The main
difference being that when heat reaches the edge of
the slug, two parallel paths are possible; conduction
towards the molding compound, and convection and
radiation towards the ambient. After a given time,
convection and radiation taked place from the plastic.
Fig. 9
Tmax
,
,,
I
I
I
I
Tam b
d
P
----':c--,
___ J'I
1:on.l.
~n~rL __
! - - - : - .
toff .1
On the other hand, the silicon die has a thermal time
constant of 1 to 2 ms and the die temperature is able
to follow frequencies of some kHz. The result is that
Tj oscillates about the average value:
a) MULTIWATT assembly
6 Tjavg = Rth Pdavg
The resulting die temperature excursions are shown
qualitatively in figure 8. The peak thermal impedance,
Rthp, corresponding to the peak temperature, 6 T max,
at tlie equilibrium can be defined:
Rthp
R th mold
= 6 T max/Pd = F (tp, DC)
R th
C th
The value of Rthp is a function of pulse width and duty
cycle. Knowledge of Rthp is very important to avoid
a peak temperature higher than specificed values
(usually 150°C).
EXPERIMENTAL RESULTS
The experimental measurements taken on several of
the packages tested are summarized in the following
sections.
MULTIWATT Package
The MULTIWATT (R) package, shown in figure 9a, is
954
Tamb
R thsi
51
C th frame
--c=J---
Tamb
5 -10625
b) Equivalent Thermal Circuit
Using the two test die, the measured junction to case
thermal resistance is:
P432
Rth (j _ c) = 2°C/W
Rth U- c) = O.4°C/W
H029
The measured time constant is approximately 1 ms
for each of the two test patterns, but the two devices
have a different steady state temperature rise.
The second cell shown in figure 9 is dominated by
the large thermal mass of the slug. The thermal
resistance of the slug, Rthslug is about 1°C/W and the
thermal time constant of the slug is in the order of 1
second.
The third RC cell in the model has a long time constant
due to the mass of the plastic molding and its low
thermal conductivity. For this cell the steady state is
reached after hundreds of seconds.
For the MULTIWATT the DC thermal resistance of the
package in free air, Rth j _ a, is 36°C/W with the P432
die and 34.5°C/W with the H029 die.
Figure 10 shows the single pulse transient thermal
impedance for the MULTIWATT with both the P432
and H029 test die. As can be seen on the graph, the
package is capable of high dissipation for short periods
of time. For a die like the H029 the power device is
capable of 700 to 800 W for pulse widths in the range
of 1 to 10 ms. For times up to a few seconds the
effective thermal resistance for a single pulse is still
in the range of 1 to 3°C/W.
Fig. 10 - Transient Thermal Response MULTIWATT Package
I-
z:
die siz
I:!
• 34.01210
q.mi 1&
U1
z:
on die di slpat.ing
~
Pd • 2 lJa l
0.001
B.Bl
B.l
TIME OR PULSE
The peak transient thermal impedance for the
MULTIWATT package containing the P432 die in free
air is shown in figure 11.
Power DIP Package
The power DIP package is a derivative of standard
small signal DIP packages with a number of leads
connected to the die pad for heat transfer to external
heat sinks. With this technique low cost heat sinks can
be integrated on the printed circuit board as shown
in figure 12a. The thermal model of the power DIP,
shown in figure 12b accounts for the external heat sink
on the circuit board by adding a second RC cell in
parallel with the cell corresponding to the molding
compound.
eo· 16.S B sq.mi Is
n'Ount.ed on board
10
~DTH
lBB
lBBB
( s )
In this model, the second cell has a shorter time
constant than for the MULTIWATT package, due in
large part to the smaller quantity of copper in the frame
(the frame thickness is 0.4 mm compared to 1.5 mm).
Thus the capacitance is reduced and the resistance
increased.
The increased thermal impedance due to the frame
can partially be compensated by a better thermal
exchange to the ambient by adding copper to the heat
sink on the board. The DC thermal resistance between
the junction and ambient can be reduced to the same
range as the MULTIWATT package in free air, as
shown in figure 13.
_______________ ~ ~~~(;)m?1rt:~~©~ _____________7;.../1_4
955
Fig. 11,· Peak Thermal Resistance MULTIWATT Package
,
:3
u
DC • 0.5
20
IoJ
~
a:
0.4
I-
l!l
'"
'"
~
0.3
IoJ
'"
IoJ
10
F
0.2
I-
z::
I!l
z::
'"
a:
Pd • 5 Wall
""a:
free air
~
It
DC.DUTV
0.1
cve
E•••••• !.U.L.SJ,J.!, OJ,H•••• __
PULSE REPETI ION PERIOD
10
lee
Ieee
TItE DR PULSE IJIDTH ( ms
Fig. 12
a) ,Power DIP Package
b) Equivalent Thermal Circuit
~8/~1;..;4_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~mg::~~©~
956
--------------
Fig. 13 - Rth (j - a) vs. PCB Heat Sink Size 12 + 3 + 3 Power Dip
~
~
u
...z:
....
IR
1\
\
f
a:
~
z:
'"'"
...S:E
...,:::> '"
""
~
....
u
...a:z:~
~
'"
.... ""
"-.,
I--.
-
:!l
...'"
'"
~
'"
~
lB
>z:
I
~
'"a:z:
~
/
on die dis ipDl:.ing a ea - 2.000 5q.mi
25 x 1GB
die pad·
B.Bl
B.BBl
on board
mounte
...~
---
/
/
:3
B.l
1
L~
q.mil&
lB
le0
lBBe
TIt'[ OR PULSE WIOlll ( s )
Fig. 17 - Transient Thermal Impedance 0.4 mm Copper Frame DIP Packages
100
10
V /1
/ --:t//"
j
~
II
1'/ // I
I
i
r
l
,/>f/
/ ./
..
,..~'
~
0.801
I
il
I
0.01
0.1
I
Ul~ ~ -+,
DD1IPp 2140 -t?die pad· 100.13
I
die pad
=0
miis
j1i
l
sCJ·mila
I
100
10
TIME OR PULSE wIDTH ':
______________
140 ,,22
s9·
5
~ ~~~~m~::J?©'
1800
!
____________
1_1...
/1_4
959
Fig. 18 - Transient Thermal Impedance 0.25 mm Copper Frame DIP Packages
18B
F=="'F===f==='F==9"===F==n!j
on die isslpatin
mounled an board
Pd • 2
::3
tt
aeea
S INGL
= 2.
B8 sq.mi Is
PULSE
"
u
~
:=
~
til
. ~ 18
~
...~
~
DB x 135
!liz:
1B x 12B • • mil.
.mila
5
til
DIP 24:
a.a1
B.BB1
ie pad - 15B x 28B • • mil.
a.1
1B
1BB
1BBB
TIrE OR PULSE WIDTH ( s )
Fig. 19 • Transient Thermal Impedance 0.25 mm Frame PLCC Package
58
SIr
mount. donSMPC 5 board
::3
<)
Pd •
Watt
V
tI
z:
:=f,!l
...
til
1B
'"
~
'"~
..J
...
e
(Jl
z:
~
/
B.BS1
~
GLE PULSE
V
B.B1
/
V
die
ad • 2SB
die
ize • 35. 00 eq.mi 1&
2SB .q.mi
on die dl slpating a eo = 2.B8!
B.1
1S
.
5~.mils
1SB
1BBB
TIrE OR PULSE IJIDTH ( • )
_12..;,1_14
____________
960
~ ~~~~m~::~~lt
--------------
Fig. 20 - Transient Thermal Impedance 0.25 mm Copper Frame 5014 Package
SING E
~
PULS
u
~
g
UJ
'"...J
18
~
'"
UJ
2'
5 WaH
I-
--->1<- - 2 WaH
~
Vl
z:
a:
e'
I
mounl.d on SM
CB1B SGS b o d
1I]
100
TII"E OR PULSE WIDTH ( ms )
10DO
Fig. 21 - Peak Thermal Impedance 0.25 mm Copper Frame 14 Lead DIP
u
~
'"
...J
cI
B
i':
~
0-'
"
'"
10
I~
0.1
10
101]
Hi08
961
CONCLUSION
This paper has discussed a test procedure for
measuring and quantifying the thermal characteristics
of semiconductor packages. Using these test methods
the thermal impedance of standard integrated circuit
packages under pulsed and DC conditions were
evaluated. From this evaluation two important
considerations arise:
1) The true thermal impedance under repetitive pulsed
conditions needs to be considered to maintain the peak
junction temperature within the rating for the device.
A proper evaluation will result in junction temperatures
that do not exceed the specified limits under either
steady state or pulsed conditions.
2) The proper evaluation of the transient thermal
characteristics of an application should take into
account the ability to dissipate high power pulses
allowing better thermal design and possibly reducing
or eliminating expensive external heat sinks when they
are oversized or useless.
REFERENCES
(1) SEMI Draft Specifications 1377 and 1449, 1986
(2) T. Hopkins, R. Tiziani, and C. Cognetti, "Improved
thermal impedance measurements by means of
a simple integrated structure", presented at
SEMITHERM 1986
(3) C. Cini, C. Diazzi, D. Rossi and S. Storti, "High side
monolithic switch in Multipower-BCD technology",
Proceedings of Microelectronics Conference,
Munchen, November 1986
(4) Application Notes 106 through 110, SGS-THOMSON
Microelectronics, 1987
~14...:/_l_4_ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m?~~lt
962
--------------
PACKAGES
SO-8J
SO-16J
.
~~'i
~I~
~
L ..
035toO,~
, '.'
, "'-1--'
~
~
3~
j
SO-14J
SO-20L
SO-20 (12+4+4)
0.5101.17
I'
963
PACKAGES
PLCC - 20 Plastic Chip Carrier
PLCC 15 +5
8 lead Plastic Minidip
4 + 4 lead Powerdip
0
9, so m.,,
,
PLCC - 44 Plastic Chip Carrier
PO01~F6
.
8 lead Ceramic Minidip
, ,
~
;:::':
~ 1_I
0,_
r-.
"'!
.-
"" • .I
,'I
I
,
I
~ i; ; :
2.59t02.74
Ji,20to4.S
964
E:J
0.46
lQ-L
l§L-i
9'Lsm.,
,
5
,
,
PACKAGES
Findip
14 lead Ceramic Dip
14 lead Plastic Dip
16 lead Plastic Dip (0.25)
20 mo ,
€::::::I
I
I
I
i
g:::::::1
965
PACKAGES
16 lead Plastic Dip (0.4)
+ 8 lead Powerdip
12 + 2 + 2 lead Powerdip
20 lead Plastic Dip (0.25)
8
Q
~
0
_20 m, , -
"
, -,
-
.
.
18 lead Plastic Dip
12 + 3 + 3 lead Powerdip
9 + 9 lead Powerdip
~
r-"·'
·" -,:::::::J
20 lead Plastic Dip (0.4)
16 + 2 + 2 Powerdip
~~J,4
1.27'""1
.."-'22,-",,8"-.6- - - - J
2480 m . .
I
.
;
I
E::J
966
PACKA~ES
28 lead Plastic Dip
48 lead Plastic Dip
\4.1
~
I
m.all
023 ..
15.21016.68
E::::J:-:::~~ :J
I
40 lead Plastic Dip
SOT -32 (TO-126)
2.4102.7
== -
If
~.~
.~
1.27
QMJL
1
62.711""
[::::::::]
31.34"""
2.54
1'5.210'6.MI
t:::::: ::':::':::::]
I
Q10100.90
l"
(1) Within this region the cross-section 01 the leads IS uncontrolled
967
PACKAGES
PENTAWATT
TO-220
Horizontal Version
2.54
4.95105.21
0.80101.05
t3J I
~
9.201010.4
SIP-9
2.6103.0
Vertical Version
0.43
968
PACKAGES
HEPTAWATT
Horizontal Version
Vertical Version
PEJ
o amu
-
"'I:::"
I"
I
I
-
.i
~ I i I ~1112~.!02.67
1~114.91'05.21
• ___ -J.I~~ to 7. 80
920 to10.U -
=1
~
t~10.4
I
~"'''~"'-=-~'"
_
""'05.21
I.?~~9to7.80
11.29·"
-.-[.
•
I
.
15.1to .15.8
9.20
I
3.SS]
L J26'o30
m
1oo6D~O~
11
--I
MULTIWATT-11
1.9102.61
I- .
~---,"--,'--Jl,
L
1.9t02.6
969
PACKAGES
MULTIWATT -15
Horizontal Version
Vertical Version
22.10 to 22.60
~[J:::::j:::'::±E!TIr;;~U
Iii]
.~:~~jl~
--=;;''\L4~---L-t--
I
970
20.2 max
P017-D4
/
NOTES
NOTES
NOTES
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NETHERLANDS
WANCHAI
22nd Floor - Hopewell centre
183 Queen's Road East
Tef. (852-5) 8615788
Telex: 60955 ESGIES HX
Tefelax: (852-5) 8656589
5612 AM EINDHOVEN
Dillenburgstraat 25
Tel.: (31-40) 550015
Telex: 51186
Telelax: (31-40) 528835
INDIA
SINGAPORE
NEW DELHI 110048
liason Office
S114, Greater Kailash Part 2
Tel. (91) 6414537
Telex: 31-62000 SGSS IN
SINGAPORE 2056
28 Ang Mo Kia - Industrial Park 2
Tel. (65) 4821411
Telex: RS 55201 ESGIES
Telelax: (65) 4820240
974
28027 MADRID
Calle Albacete, 5
Tef_ (34-1) 4051615
Telex: 46033 TCCEE
Telefax: (34-1) 4031134
SWEDEN
S·16421 KISTA
Borgarfjordsgatan, 13 - Box 1094
Tef_: (46-8) 7939220
Telex: 12078 THSWS
Telefax: (46-8) 7504950
SWITZERLAND
1218 GRAND-SACONNEX (GENEvE)
Chemin Fran<;:ois-Lehmann, 18/A
Tel. (41-22) 986462
Telex: 28895 STM CH
Telelax: (41-22) 964869
TAIWAN
KAOHSIUNG
7FL-2 No
5 Chung Chen 3Rd Road
Tel. (886-7) 2011702
Telefax: (886-7) 2011703
TAIPEI
6th Floor, Pacific Commercial Building
285 Chung Hsiao E. Road - SEC, 4
Tel. (886-2) 7728203
Telex: 10310 ESGIE TWN
Telelax: (886-2) 7413837
UNITED KINGDOM
MARLOW, BUCKS
Planar House, Parkway
Globe Park
Tel.: (44-628) 890800
Telex: 647458
Telefax: (44-628) 890391
SALES OFFICES
U.S.A.
NORTH & SOUTH AMERICAN
MARKETING HEADQUARTERS
1000 East Bell Road
Phoenix, AI. 85022
(1 }-(602) 867-61 00
SALES & REPS COVERAGE BY STATE
AL
Huntsville - (205) 533-5995
Huntsville (Rep) - (205) 881-9270
AZ
Phoenix - (602) 867-6340
CA
Fountain Valley (Rep) - (714) 545-3255
Irvine - (714) 250-0455
Los Angeles (Rep) - (213) 879-0770
San Diego (Rep) - (619) 693-1111
Santa Clara - (408) 970-8585
Santa Clara (Rep) - (408) 727-3406
CO
Longmont - (303) 449-9000
Wheat Ridge (Rep) - (303) 422-8957
FL
Attamonte Springs (Rep) - (305) 682-4800
Deerfield Beach (Rep) - (305) 426-4601
SI. Petersburg (Rep) - (813) 823-6221
GA
Tucker (Rep) - (404) 938-4358
IL
Schaumburg - (312) 490-1890
IN
Fort Wayne (Rep) - (219) 436-3023
Greenwood (Rep) - (317) 881-0110
IA
Cedar Rapids (Rep) - (319) 362-2526
MD
Glen Burnie (Rep) - (301) 761-6000
MA
Wa~ham
- (617) 890-6688
MO
Florissant (Rep) - (314) 839-0033
Kansas City (Rep) - (816) 436-6445
NJ
PUERTO RICO
Rio Piedras (Rep) - (809) 790-4090
URUGUARY
Montevideo (Rep) - (011) 598-2-594-888
Marlton - (609) 722-9200
NY
Binghamton (Rep) - (607) 772-0651
E. Rochester (Rep) - (716) 381-8500
Hauppauge - (516) 435-1050
Jericho (Rep) - (516) 935-3200
Pittsford (Rep) - (716) 381-3186
Poughkeepsie - (914) 454-8813
Skaneateles (Rep) - (315) 685-5703
NC
Charlotte (Rep) - (704) 563-5554
Morrisville (Rep) - (919) 469-9997
OH
Chagrin Falls (Rep) - (216) 247-6655
Dayton (Rep) - (513) 866-6699
OR
Beaverton (Rep) - (503) 627-0838
PA
Butler (Rep) - (412) 285-1313
Horsham (Rep) - (215) 441-4300
TN
Jefferson City (Rep) - (615) 475-9012
TX
Austin - (512) 451-4061
Carrollton - (214) 466-8844
UT
Salt Lake City (Rep) - (801) 269-0419
WA
Bellevue (Rep) - (206) 451-3500
CANADA
Burnaby (Rep) - (604) 421-9111
Mississauga (Rep) - (416) 673-0011
Nepean (Rep) - (613) 825-0545
Quebec (Rep) - (514) 337-5022
Winnipeg (Rep) - (204) 783-4387
BRAZIL
Sao Paulo - (551) 11-883-5455
MI
Southfield - (313) 358-4250
Southfield (Rep) - (313) 358-4151
COLUMBIA
Bogota (Rep) - (011) 57-1-257-8824
MN
Bloomington (Rep) - (612) 884-6515
MEXICO
Mexico City (Rep) - (905) 577-1883
WEST GERMANY
6000 FRANKFURT 71
Rennbahnstrasse 72-74
Tel. (49-69) 6708191
Telex: 176997 689
Telelax: (49-69) 674377
8018 GRAFING BEl MUNCHEN
Haidling,17
Tel. (49-8092) 690
Telex: 527378
Telelax: (49-8092) 3964
3000 HANNOVER 1
Eckenerstrasse 5
Tel. (49-511) 634191
Teletex: 175118418
Telelax: (49-511) 633552
MUNCHEN 70
Perchtinger Str. 3
Postfach 70.19.09
Tel. (49-89) 78790
Telex: 522916
Telelax: (49-89) 7879145
8500 NURNBERG 20
Erlenstegenstrasse, 72
Tel.: (49-911) 597032
Telex: 626243
Talelax: (49-911) 5980701
5200 SIEGBURG
Frankfurter Str. 22a
Tel. (49-241) 660 84-86
Telex: 889510
Telelax: (49-241) 67584
7000 STUTTGART 1
Oberer Kirchhaldenweg 135
Tel. (49-711) 692041
Telex: 721718
Telelax: (49-711) 691408
975
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other righis of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical cGmponents in Ufe support devices or systems
without express written approval of SGS-THOMSON Microelectronics.
© 1988 SGS-THOMSON Microelectronics -
Printed in Italy -
All Rights Reserved
® : Pentawatt and Multiwatt are registered marks of SGS-THOMSON - TM: Heptawatt is an Trade-Mark of SGS-THOMSON
SGS-THOMSON Microelectronics
Australia· Belgium - Brazil - Canada - China - Denmark - France - Hong Kong - India - Italy - Japan - Korea - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A. - West Germany
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