1988_SGS Thomson_Industrial_and_Computer_Peripheral_ICs_1ed 1988 SGS Thomson Industrial And Computer Peripheral ICs 1ed

User Manual: 1988_SGS-Thomson_Industrial_and_Computer_Peripheral_ICs_1ed

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DUSTRIAL AND COMPUTER
PERIPHERAL ICs
DATABOOK
1st EDITION

OCTOBER 1988

USE IN LIFE SUPPORT MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON' PRODUCTS ARE NOT AUTHORIZED FOR USE A CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF SGS-THOMSON
Microelectronics. As used herein:
1. Life support devices or systems are devices or systems
which, are intended for surgical implant into the body to
support or sustain life, and whose failure to perfom,
when properly used in accordance with instructions for
use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.

TABLE OF CONTENTS

INTRODUCTION
ALPHANUMERICAL INDEX

Page 4

7

PRODUCT SELECTOR GUIDE

13

DATASHEETS

21

PACKAGES:
DESIGNING WITH THERMAL IMPEDANCE
MECHANICAL DATA

987
989
t003

SALES OFFICES

1022

INDUSTRIAL & COMPUTER PERIPHERAL ICs
FROM THE BRIGHTER POWER

Since the first high power ICs emerged at the end of the 1960s SGSTHOMSON has set the pace in power
IC process technology, plastic power
packages and innovative circuit design.

Originally this technology knowhow
was applied to consumer circuits such
as high power amplifiers and TV vertical deflection stages, so when motor
driving ICs arrived at the end of the seventies SGS-THOMSON already possessed a unique understanding of the
problems involved and, more important, how they could be solved.
SGS-THOMSON is not just the leader
in smart power technology, it is also
the #1 supplier of smart power ICs in
the western world (Dataquest, May
1988), selling more than any American
or European semiconductor company.

Realized with SGS-THOMSON's unique Multipower-BCD technology, the L4970 power
switching regulator delivers an impressive 10A
output current. A host of protection features
are integrated.

4

Many of the milestones in smart power
technology have been developed by
SGS-THOMSON and many are stili
unmatched. Today's leading edge is a
family of smart power technologies
integrating bipolar, CMOS and DMOS
on the same chip. Using this technology the company has produced a new
generation of ultra-efficient power ICs
that are changing the whole approach
to power system design.
Just one example of the way this technology can be applied is the L6202

Thanks to the high efficiency of Multipower-BCD technology's DMOS power transistors, the L6202
H-bridge motor driver delivers 1.5A/48V with no heatsink.

bridge driver, containing a full DMOS
H-bridge power stage plus control circuits.
Because of the very high efficiency of
the power stage this Ie can deliver
lOW to the load yet it is assembled in
a DIP package.
Many more world-beating products

are included in this databook: the
L49l0 switching regulator, L6230
brushless motor driver, L6114 quad
switch, the industrial power switch
family and much more. So if you're
looking for the brightest solution to
your industrial and computer peripheral application problems you'll find the
answer right here.

5

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ALPHANUMERICAL INDEX

Type

Function

Page
I'"

AM6012

12 BIT HIGH SPEED D/A CONVERTER ..................................................... .

21

AM6012A

12 BIT HIGH SPEED D/A CONVERTER ..................................................... .

21

DAC0806

6 BIT D/A CONVERTER ............................................................................... .

33

DAC0807

7 BIT D/A CONVERTER ............................................................................... .

33

DAC0808

8 BIT D/A CONVERTER ...............................................................................

33

ESM1600B

QUAD COMPARATOR INTERFACE CIRCUIT ............................................ .

45

ESM1602B

QUAD COMPARATOR INTERFACE CIRCUIT ............................................ .

53

GS-D050

STEPPER MOTOR DRIVER MODULE ........................................................ .

61

GS-D200

STEPPER MOTOR DRIVER MODULE ........................................................ .

79

GS-R400

SWITCH MODE REGULATOR MODULE .............................................. .

GS-R400VB

SWITCH MODE REGULATOR MODULE .................................................... .

119

GS-R400/2

SWITCH MODE REGULATOR MODULE .................................................... .

129

GS-R51212

SWITCH MODE REGULATOR MODULE .................................................... .

137

L149

4A LINEAR DRIVER ..................................................................................... .

147

97

L165

3A POWER OPERATIONAL AMPLIFIER .................................................... .

151

L200

ADJUSTABLE VOLTAGE AND CURRENT REGULATOR .......................... .

159

L272

DUAL POWER OPERATIONAL AMPLIFIER ............................................... .

169

L272D

DUAL POWER OPERATIONAL AMPLIFIER ............................................... .

175

L272M

DUAL POWER OPERATIONAL AMPLIFIER ............................................... .

169

L290

TACHOMETER CONVERTER ..................................................................... .

179
185

L291

5 BIT D/A CONVERTER AND POSITION AMPLIFIER ................................ .

L292

SWITCH MODE DRIVER FOR DC MOTORS .............................................. .

191

L293B

PUSH-PULL FOUR CHANNEL DRIVER ...................................................... .

201

L293C

PUSH-PULL FOUR CHANNEL / DUAL H-BRIDGE DRIVER ...................... .

209

L293D

PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES ............................ .

213

L293E

PUSH-PULL FOUR CHANNEL DRIVER ...................................................... .

201

L294

SWITCH MODE SOLENOID DRIVER .......................................................... .

217

L295

DUAL SWITCH MODE SOLENOID DRIVER ............................................... .

223

L296

HIGH CURRENT SWITCHING REGULATOR ............................................. .

229

L296P

HIGH CURRENT SWITCHING REGULATOR ............................................. .

229

L297

STEPPER MOTOR CONTROLLER ............................................................. .

253

L297A

STEPPER MOTOR CONTROLLER ............................................................. .

253

L298N

DUAL FULL-BRIDGE DRIVER ..................................................................... .

263

L387A

VERY LOW DROP 5V REGULATOR ........................................................... .

273

L601

DARLINGTON ARRAY ................................................................................. .

277

L602

DARLINGTON ARRAY ................................................................................. .

277

L603

DARLINGTON ARRAY ................................................................................. .

277

L604

DARLINGTON ARRAY ................................................................................. .

277

L702

2A QUAD DARLINGTON SWITCH .............................................................. .

281

L2720

LOW DROP DUAL POWER OPERATIONAL AMPLIFIER .......................... .

285

-------------

~ ~~;~~mgr::~~~,

-----------7

ALPHANUMERICAL INDEX

Type

L2722
L2724
L2726
L3654S
L4901A
L4902A
L4903
L4904A
L4905
L4920
L4921
L4940 SERIES
L4941

Function
LOW DROP DUAL POWER OPERATIONAL AMPLIFIER ...........................

Page
285

LOW DROP DUAL POWER OPERATIONAL AMPLIFIER ...........................

285

LOW DROP DUAL POWER OPERATIONAL AMPLIFIER ...........................

293

PRINTER SOLENOID DRIVER .....................................................................

297

DUAL 5V REGULATOR WITH RESET .........................................................

301

DUAL 5V REGULATOR WITH RESET AND DISABLE ................................

311

DUAL 5V REGULATOR WITH RESET .........................................................

321

DUAL 5V REGULATOR WITH RESET .........................................................

329

DUAL 5V REGULATOR WITH RESET AND DISABLE ................................

337

VERY LOW DROP ADJUSTABLE REGULATOR .........................................

345

VERY LOW DROP ADJUSTABLE REGULATOR .........................................

345

VERY LOW DROP 1.5A REGULATORS ......................................................

349

VERY LOW DROP 1A REGULATOR ............................................................

357

L4941 X

VERY LOW DROP 1A REGULATOR ............................................................

357

L4960
L4962
L4964
L4970
L5832
L6114
L6115
L6122
L6123
L6201
L6202
L6203
L6210
L6212
L6217
L6217A
L6220
L6220N
L6221A
L6221N
L6222
L6230
L6231
L6233
L6235
L6236

2.5A POWER SWITCHING REGULATOR ....................................................

363

8

1.5A POWER SWITCHING REGULATOR ....................................................

377

HIGH CURRENT SWITCHING REGULATOR ..............................................

389

HIGH CURRENT SWITCHING REGULATOR ..............................................

401

SOLENOID CONTROLLER .......................................................................... .

417

QUAD 100V DMOS SWITCH ....................................................................... .

429

QUAD 100V DMOS SWITCH .. ..... .... .... ............. .... .......... ....... ............... ....... .

429

100V DMOS SWITCH ................................................................................... .

437

100V DMOS SWITCH ................................................................................... .

437

DMOS FULL BRIDGE DRIVER ....................................................................

443

DMOS FULL BRIDGE DRIVER .....................................................................

455

DMOS FULL BRIDGE DRIVER .....................................................................

471

DUAL SCHOTTKY DIODE BRIDGE .............................................................

487

HIGH CURRENT SOLENOID DRIVER .........................................................

491

STEPPER MOTOR DRIVER ........................................................................ .

497

STEPPER MOTOR DRIVER ........................................................................ .

505

QUAD DARLINGTON SWITCH .....................................................................

513

QUAD DARLINGTON SWITCH .....................................................................

513

QUAD DARLINGTON SWITCH .....................................................................

523

QUAD DARLINGTON SWITCH .................................................................... .

523

QUAD TRANSISTOR SWITCH .................................................................... .

535

BIDIRECT. 3-PHASE BRUSHLESS DC MOTOR DRIVER ..........................

539

3-PHASE BRUSHLESS DC MOTOR DRIVER .............................................

547

PHASE LOCKED FREQUENCY CONTROLLER .........................................

555

R-DAT BRUSHLESS DC MOTOR DRIVER ..................................................

563

BIDIRECT. BRUSHLESS DC MOTOR DRIVER ...........................................

571

ALPHANUMERICAL INDEX

Type

Function

Page

L6495

HIGH SPEED OPERATIONAL AMPLIFIER ..................................................

579

L6503

HAMMER SOLENOID CONTROLLER ..........................................................

585

L6504

SOLENOID CONTROLLER ...........................................................................

591

L6506

CURRENT CONTROLLER FOR STEPPING MOTORS ...............................

599

L6570A

2-CHANNEL FLOPPY DISK READIWRITE CIRCUIT ..................................

605

L6570B

2-CHANNEL FLOPPY DISK READ/WRITE CIRCUIT ..................................

605
613

L6603

MEMORY CARD INTERFACE ......................................................................

L6604

MEMORY CARD INTERFACE ......................................................................

613

L7150

50V QUAD DARLINGTON SWITCH ............................................................ .

621

L7152

50V QUAD DARLINGTON SWITCH .............................................................

621

L7180

80V QUAD DARLINGTON SWITCH .............................................................

625

L7182

80V QUAD DARLINGTON SWITCH ............................................................ .

625

M5450

LED DISPLAY DRIVER .................................................................................

629

M5451

LED DISPLAY DRIVER .................................................................................

629

M5480

LED DISPLAY DRIVER .................................................................................

637

M5481

LED DISPLAY DRIVER .................................................................................

643

M5482

LED DISPLAY DRIVER .................................................................................

649

M8438A

SERIAL INPUT LCD DRIVER ........................................................................

655

M8439

SERIAL INPUT LCD DRIVER ........................................................................

663

M145026

REMOTE CONTROL ENCODER ................................................................. .

669
669

M145027

REMOTE CONTROL DECODER ................................................................. .

M145028

REMOTE CONTROL DECODER ..................................................................

669

MC1488

RS232C QUAD LINE DRIVER ..................................................................... .

679

MC1489

RS232C QUAD LINE RECEIVER ..................................................................

687

MC1489A

RS232C QUAD LINE RECEIVER ..................................................................

687

MC3479C

STEPPER MOTOR DRIVER ........................................................................ .

695

PBL3717A

STEPPER MOTOR DRIVER ........................................................................ .

703

SG1524

REGULATING PWM ......................................................................................

713

SG1525A

REGULATING PWM ......................................................................................

721

SG1527A

REGULATING PWM ......................................................................................

721

SG2524

REGULATING PWM ......................................................................................

713

SG2525A

REGULATING PWM ......................................................................................

721

SG2527A

REGULATING PWM ......................................................................................

721

SG3524

REGULATING PWM ......................................................................................

713

SG3525A

REGULATING PWM ......................................................................................

721

SG3527A

REGULATING PWM ......................................................................................

721

TDA0159A

PROXIMITY DETECTOR ..............................................................................

731

TDA0161

PROXIMITY DETECTOR ............................................................................ .

735

TDE0160

PROXIMITY DETECTOR ................................................................ ............. .

739

TDE1607

INTELLIGENT POWER SWITCH ..................................................................

745

9

ALPHANUMERICAL INDEX

Type

Function

INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
INTELLIGENT POWER SWITCH ................................................................. .
RELAY AND LAMP DRIVER ........................................................................ .
DUAL 2A SOURCE DRIVER ........................................................................ .
DUAL 2A SOURCE DRIVER ........................................................................ .
LOW DROP TRIPLE 1.5A SINK DRIVER .................................................... .
INTELLIGENT POWER SWITCH ................................................................. .
STEPPER MOTOR DRIVER ............................................................. .
STEPPER MOTOR DRIVER ........................................................................ .
STEPPER MOTOR DRIVER ........................................................................ .
STEPPER MOTOR DRIVER ........................................................................ .
STEPPER MOTOR DRIVER ........................................................................ .
TL7700A SERIES SUPPLY VOLTAGE SUPERVISORS ........................................................... .
TS27L2
CMOS DUAL OPERATIONAL AMPLIFIER .................................................. .
TS27L4
CMOS QUAD OPERATIONAL AMPLIFIER ..................................................
TS27M2
CMOS DUAL OPERATIONAL AMPLIFIER ...................................................
TS27M4
CMOS QUAD OPERATIONAL AMPLIFIER ..................................................
TS271
CMOS SINGLE OPERATIONAL AMPLIFIER ...............................................
TS272
CMOS DUAL OPERATIONAL AMPLIFIER ...................................................
TS274
CMOS QUAD OPERATIONAL AMPLIFIER ..................................................
UAA4002
CONTROL CIRCUIT FOR FAST-SWITCH ...................................................
SWITCH MODE REGULATOR FOR DC MOTORS ......................................
UAA4003
UAB4718
STEPPER MOTOR DRIVER ........................................................................ .
UAF4718
STEPPER MOTOR DRIVER ........................................................................ .
UAF1780
DUAL 2A LOW DROP INTELLIGENT POWER SWITCH ............................ .
UAF1781
DUAL 2A LOW DROP INTELLIGENT POWER SWITCH ............................ .
UAF1782
DUAL 2A LOW DROP INTELLIGENT POWER SWITCH .............................
UC1840
PROGRAMMABLE OFF-LINE, PWM CONTROLLER ..................................
UC1842
CURRENT MODE PWM CONTROLLER ......................................................
UC1843
CURRENT MODE PWM CONTROLLER ......................................................

TDE1647
TDE1647A
TDE1737
TDE1747
TDE1767
TDE1767A
TDE1787
TDE1787A
TDE1798
TDE1799
TDE3207
TDE3237
TDF1607
TDF1647A
TDF1737
TDF1778
TDF1779A
TDF1783
TDF1798
TEA3717
TEA3718
TEA3718S
TEF3718
TEF3718S

10

Page
745
745
755
745
759
759
759
759
767
779
789
795
745
745
755
799
807
815
767
823
831
831
845
845
851
867
877
867
877
857
867
877
887
899
907
907
915
915
915
921
931
931

ALPHANUMERICAL INDEX

Type

Function

Page

UC1844
UC1845

CURRENT MODE PWM CONTROLLER "", .. ,,"","",,",,"',"',', .. ,,",",',""""

931

CURRENT MODE PWM CONTROLLER .. ,"""" """" .. ,.. " .. "'" .. ,.... " .. ,,,,",,' ,

931

UC2840

PROGRAMMABLE OFF-LINE, PWM CONTROLLER """"" .......... " ...... ",,"

921

UC2842
UC2843

CURRENT MODE PWM CONTROLLER "" ............ " .......................... " ...... , ,
CURRENT MODE PWM CONTROLLER " .... ,,, .. ,.... ,,, .. ,, ............ ,........ ,, ...... ,

931
931

UC2844

CURRENT MODE PWM CONTROLLER ", .... " ...... "" ................ ,.. ,.... " .. "" .. ,

931

UC2845

CURRENT MODE PWM CONTROLLER ", .... ,........ " .. " .... ,.. ,.... ,........ " .. "" .. ,

931

UC3840

PROGRAMMABLE OFF-LINE, PWM CONTROLLER ............ ", .......... " ...... ,

921

UC3842

CURRENT MODE PWM CONTROLLER ........ " .. " .................................... ,,"

931

UC3843

CURRENT MODE PWM CONTROLLER "" ........ ,........ " .. ,...... " .......... " .. " .. ,

931

UC3844

CURRENT MODE PWM CONTROLLER ", .... " .. " .... " .. " ........ " .. ,........ " .. " .. , ,

931

UC3845

CURRENT MODE PWM CONTROLLER .................. " ........................ " ...... ,'

931

UCN4801A

BIMOS LATCH-DRIVER ................ ,............ " .... ,.. " .... ,.. " .. ,.................. " .. " .. ,'

939

UEB4732
ULN2001A

AC PLASMA PANEL DRIVER ...................... " ...... " ...... " ........ " ................ " .. ,
DARLINGTON ARRAy ............ " ............................................................ " .... "

943
949

ULN2002A

DARLINGTON ARRAy .................... """ .. "" .. """""""" .. " .... """" .. " .... """"

949

ULN2003A

DARLINGTON ARRAy" .... " .... """"" .. " .. "" .. " .. " .. "" .. " .. "" .. " .. "" ........ "",."

949

ULN2004A

DARLINGTON ARRAy .. " .. " .... """ .. " .. """""" .. " .. "" .. " .. "" .... """ .... " .. """"

949

ULN2064B

BOV QUAD DARLINGTON SWITCH .. ,," .. , "" ...... "" .. " "" " " " " .. " .. " " .. " .. " .. ,

953

ULN2065B

50V QUAD DARLINGTON SWITCH "'" .... ,.. " " " ,.. ," ........ ,.. " .. " .......... ," .. " .. ,

961

ULN2066B

BOV QUAD DARLINGTON SWITCH " .. """ .. """""""" .. " .. "" .. " .. "" .. "",, .. ,, ,

953

ULN2067B

50V QUAD DARLINGTON SWITCH """""""""""""""""""""""""""""" ,
BOV QUAD DARLINGTON SWITCH " .... "" .. """ .. "" .. " .. " .. "" .. ,,""" .... ,,,, .. ,, ,

961
953

ULN2069B

50V QUAD DARLINGTON SWITCH " .. """ .. """""" .. " ........ """" .. " .... ,, .... ,, ,

961

ULN2070B

BOV QUAD DARLINGTON SWITCH "'" .... "'" .. ,,, .. ,,, .. ,, .... ,,, .... ,,',, .. ,.. ,,"",, .. ,'

953

ULN2071B

50V QUAD DARLINGTON SWITCH " .. " .. "" .. " .. " .. " .. " .... " .. """" .. " .... ,, ...... ,

961

ULN2074B

BOV QUAD DARLINGTON SWITCH " .. " .. """" .. """"" .. " .. " .. " .. ",, .... ,,"" .. ,, ,

953

ULN2075B

50V QUAD DARLINGTON SWITCH " .. " .. """" .. "" .. "" .. " .. " .. " .... ,," .. " .. ,, .. ,, ,

961

ULN2076B

BOV QUAD DARLINGTON SWITCH " .. """ .. "" .. " .. """ .. " .... " .... """ .. " .. ,, .. ,'

953

ULN2077B
ULN2801A

50V QUAD DARLINGTON SWITCH """ .. """" .. """"""" .. "",,"",,,, .. ,, .. "' .. ' ,
DARLINGTON ARRAy .... " .. """" .. " .. " .. " .. ,,,,,,, .. ,,,,,,,, .. ,,,, .. ,, .. ,, .. ,,,, .. ,,,, .... ,, .. ,

961
969

ULN2802A

DARLINGTON ARRAy ...... "" .. ,.... " .. ,,, .. ,,,, .. ,, ...... ,,,,,,,,,,,,, .. ,, .. ,, .. ,,,, .... ,, .... ,, .. ,

969

ULN2803A

DARLINGTON ARRAy" .... "" .. ", .. ",,, .... ,, .... ,, ........ ,,,,,, .. ,, .. ,,,, .. ,, .... ,, .... ,,,,,, .. ,,

969

ULN2804A

DARLINGTON ARRAy ...... "" .. ,.. " .. " .. ",,,,,,,,,,,,,,,,,,,, .. ,,,,,,,, .. ,,,,,,,,,,,,,,,,,,,,,,,,,

969

ULN2805A

DARLINGTON ARRAy ...... "" .. ,,,,,,,,,, .. ,, .. ,,,,,,, .. ,,,, .. ,, .. ,,,,,,,,,,, .. ,,,, ...... ,, .... ,, .. ,,

969

ULQ2001R

DARLINGTON ARRAy", .. ,.......... ,.... ,........ " ........ " .. ,........................ """ .... ",

975

ULQ2002R

DARLINGTON ARRAy .... " ........ " ................ " ...... " ........ "", .... "",,,,,,,,,, .. ,, .... ,

975

ULQ2003R

DARLINGTON ARRAy .... " .. , .. ,.. " .... ", ...... " .. " ........ " .... " .. " .. " .... " .. ", ...... ", .. ,

975

ULQ2004R

DARLINGTON ARRAy .... " ............ "" .. ", .. " .. ",,, .. ,,,,, .. ,, .. ,, .. ,,, .... , .. ,,, .. ,, .. ,, .. ,,,,

975

VB100

HIGH VOLTAGE INTELLIGENT POWER SWITCH .. ", .. " .. """", ........ " .. ,, .. , ,

979

ULN2068B

- - - - - - - - - - - Gil scs-mOMSON - - - - - - - - - - • J, " """~©rnl!QI~~~©'irrnl!QIli'!!~©!li

11

PRODUCT SELECTOR GUIDE
SOLENOID, HAMMER, NEEDLE, RELAY

ESM1600B
ESM1602B
L294
L295
L601!2/3/4
L702
L3654S
L5832
L6114/15
L6122/23
L6212
L6220/N
L6221A1N
L6503
L6504
L7150/52
L7180/82
TDE1607/47/47A
TDE1737
TDE1747
TDE1767/67A
TDE1787/87A
TDE1798
TDE1799
TDE3207
TDE3237
TDF1607/1647A
TDF1737
TDF1778
TDF1779A
TDF1783
TDF1798
UAF1780/1/2
ULN2001A to 2004A
ULN2064B to 2077B
ULN2801A to 2805A
ULQ2001 R to 2004R
VB100

Page
- Quad comparator Interface Circuit ................................................................................ 45
- Quad Comparator Interface Circuit ............................................................................... 45
- Switch-Mode Solenoid Driver ..................................................................................... 217
- Dual Switch-Mode Solenoid Driver .............................................................................. 223
- Darlington Arrays ......................................................................................................... 277
- 2A Quad Darlington Array ........................................................................................... 281
- Printer Solenoid Driver ................................................................................................ 297
- Solenoid Controller ...................................................................................................... 417
- Quad 100V DMOS Switch ........................................................................................... 429
- 100V DMOS Switch .................................................................................................... 437
- High Current Solenoid Driver ...................................................................................... 491
- Quad Darlington Switch ............................................................................................... 513
- Quad Darlington Switch ............................................................................................... 535
- Hammer Solenoid Controller ....................................................................................... 585
- Solenoid Controller ...................................................................................................... 591
- Quad Darlington Switch ............................................................................................... 621
- Quad Darliington Switch .............................................................................................. 625
-Intelligent Power Switch .............................................................................................. 745
- Intelligent Power Switch .............................................................................................. 755
- Intelligent Power Switch .............................................................................................. 745
-Intelligent Power Switch .............................................................................................. 759
- Intelligent Power Switch .............................................................................................. 759
- Intelligent Power Switch .............................................................................................. 767
- Intelligent Power Switch .............................................................................................. 779
- Intelligent Power Switch .............................................................................................. 789
- Intelligent Power Switch .............................................................................................. 795
-Intelligent Power Switch .............................................................................................. 745
- Relay and Lamp Driver ............................................................................................... 755
- Dual 2A Source Driver ................................................................................................. 799
- Dual 2A Source Driver ................................................................................................. 807
- Low Drop Triple 1.5A Sink Driver ................................................................................ 815
- Intelligent Power Switch .............................................................................................. 767
- Dual 2A Low Drop Intelligent Power Switch ................................................................ 915
- Seven Darlington Arrays ,............................................................................................ 949
- Quad Darlington Switches ........................................................................................... 953
- Eight Darlington Arrays ............................................................................................... 969
- Seven Darlington Arrays ............................................................................................. 975
- High Voltage Intelligent Power Switch ........................................................................ 979

13

!

PRODUCT SELECTOR GUIDE
UNIPOLAR STEPPER MOTORS

L297/A
L702
L6506
L7150/52
L7180/82
ULN2064B to 2077B

-

Page
Stepper Motor Controllers ........................................................................................... 253
2A Quad Darlington Switch ............................................. :........................................... 281
Current Controller for Stepping Motors ....................................................................... 599
Quad Darlington Switch ............................................................................................... 621
Quad Darlington Switch ............................................................................................... 625
Quad Darlington Switch ............................................................................................... 953

BIPOLAR STEPPER MOTORS

L297/A
L298N
L6201
L6202
L6203
L621 0
L6217
L6117A
L6506
MC3479C
PBL3717A
TEA3717
TEA3718/S
TEF3718/S
UAB/UAF4718
GS-D050
GS-D200

-

Stepper Motor Controllers ........................................................................................... 253
Dual Full Bridge Driver ................................................................................................ 263
0.3 ohms DMOS Full Bridge Driver ............................................................................. 443
0.3 ohms OM OS Full Bridge Driver ............................................................................. 455
0.3 ohms DMOS Full Bridge Driver ............................................................................. 471
Dual Schottky Diode Bridge ........................................................................................ 487
Stepper Motor Driver .................................................... ,.............................................. 497
Stepper Motor Driver ................................................................................................... 505
Current Controller for Stepping Motors ....................................................................... 599
Stepper Motor Driver ................................................................................................... 695
Stepper Motor Driver ................................................................................................... 703
Stepper Motor Driver ................................................................................................... 823
Stepper Motor Driver ................................................................................................... 831
Stepper Motor Driver ................................................................................................... 845
Stepper Motor Driver ................................................................................................... 907
Stepper Motor Driver Module ........................................................................................ 61
Stepper Motor Driver Module ........................................................................................ 79

-------------~ ~~~~m?:~~
14

-------------

PRODUCT SELECTOR GUIDE
BRUSH LESS MOTORS

L6230
L6231
L6233
L6235
L6236

-

Page
Bidirect. 3-Phase Brushless DC Motor Driver .......................................................................... 539
Three-Phase Brushless DC Motor Driver ................................................................................. 547
Phase Locked Frequency Controller ........................................................................................ 555
R-DAT Brushless DC Motor Driver ........................................................................................... 563
Bidirectional Brushless DC Motor Driver .................................................................................. 571

DC MOTORS

~
\JLJ)

L149
L165
L272/M
L272D
L290
L291
L292
L293B/E
L293C
L293D
L298N
L2720/2/4
L2726
UAA4003
VB100

-

4A Linear Driver ....................................................................................................................... 147
3A Power Operational Amplifier ............................................................................................... 151
Dual Power Operational Amplifier ............................................................................................ 169
Dual Power Operational Amplifier ............................................................................................ 175
Tachometer Converter ............................................................................................................. 179
5 Bit 01A Converter and Position Amplifier .............................................................................. 185
Switch-Mode Driver for DC Motors ........................................................................................... 191
Push-Pull Four Channel Drivers ............................................................................................... 201
Push-Pull Four Channel ........................................................................................................... 209
Push-Pull Four Channel Driver with Diodes ............................................................................. 213
Dual Full Bridge Driver ............................................................................................................. 263
Low Drop Dual Power Operational Amplifier ............................................................................ 285
Low Drop Dual Power Operational Amplifier ............................................................................ 293
Switch Mode Regulator For DC Motors .................................................................................... 899
High Voltage Intelligent Power Switch ...................................................................................... 979

--------------~ ~~~~m~~~

------------15

PRODUCT SELECTOR GUIDE
DISPLAYS

L601/2/3/4
L3654S
M5450/1
M5480
M5481
M5482
M8438A
M8439
UCN4801A
UEB4732
ULN2001A to 2004A
ULQ2001R to 2004R

-

Page
Darlington Arrays ......................................................................................................... 277
Printer Solenoid Driver ................................................................................................ 297
Led Display Drivers ..................................................................................................... 629
Led Display Driver ....................................................................................................... 637
Led Display Driver ....................................................................................................... 643
Led Display Driver ....................................................................................................... 649
Serial Input LCD Driver ............................................................................................... 655
Serial Input LCD Driver ............................................................................................... 663
BIMOS Latch-Driver .................................................................................................... 939
AC Plasma Panel Driver .............................................................................................. 943
Seven Darlington Arrays ............................................................................................. 949
Seven Darlington Arrays ............................................................................................. 975

SPECIAL FUNCTIONS

AM6012/A
DAC0806/7/8
ESM1600B
ESM1602B
L149
L6495
L6570AlB
L6603/4
M1480261718
MC1488
MC1489/A
TDA0159A
TDA0161A
TDE0160
TL7700A SERIES
TS271
TS272/27M2/27L2
TS274/27M4/27L4

16

-12 Bit High Speed Multypling D/A Converters .............................................................. 21
- 8 Bit D/A Converters ..................................................................................................... 33
- Quad Comparator Interface Circuit ...............................................................................45
- Quad Comparator Interface Circuit ............................................................................... 53
- 4A Linear Driver .......................................................................................................... 147
- High Speed Operational Amplifier ............................................................................... 579
- 2 Channel Floppy Disk ReadlWrite Circuits ................................................................ 605
- Memory Card Interface ................................................................................................ 613
- Remote Control Encoder/Decoder .............................................................................. 669
- RS232C Quad Line Driver ........................................................................................... 679
- Quad Line Receiver ..................................................................................................... 687
- Proximity Detector ....................................................................................................... 731
- Proximity Detector ....................................................................................................... 735
- Proximity Detector ....................................................................................................... 739
- Supply Voltage Supervisor .......................................................................................... 883
- CMOS Single Operational Amplifier ............................................................................ 857
- CMOS Dual Operational Amplifier ............................................................................... 867
- CMOS Quad Operational Amplifier ............................................................................. 877

PRODUCT SELECTOR GUIDE
VOLTAGE REGULATORS

!..

IN

5

J.100nF

1:
100nF

L200
L296/P
L387 A
L4901 A
L4902A
L4903
L4904A
L4905
L4920/1
L4940 SERIES
L4941/X
L4960
L4962
L4964
L4970
SG1524/2524/3524
SG1525A/2527A/3527A
TL7700A SERIES
UA4002
UC1840/2840/3840
UC1842/2842/3842
UC1843/2843/3843
UC1844/2844/3844
UC1845/2845/3845
GS-R400
GS-R400VB
GS-R400/2
GS-R51212

-

O

J,

OUT

J: 100llF

r--'-4____-.3_____2~--~~
RESET

... -

J:

J.

OUT

Page
Adjustable Voltage and Current Regulator ................................................................. 159
High Current Switching Regulators ............................................................................. 229
Very Low Drop 5V Regulator ....................................................................................... 273
Dual 5V Regulator With Reset .................................................................................... 301
Dual 5V Regulator With Reset and Disable ................................................................ 311
Dual 5V Regulator With Reset .................................................................................... 321
Dual 5V Regulator With Reset .................................................................................... 329
Dual 5V Regulator With Reset and Disable ................................................................ 337
Very Low Drop Adjiustable Regulators ........................................................................ 345
Very Low Drop 1.5A Regulators ................................................................................ 349
Very Low Drop 1A Regulators .................................................................................... 357
Power Switching Regulator ......................................................................................... 363
Power Switching Regulator ......................................................................................... 377
High Current Switching Regulator ............................................................................... 389
High Current Switching Regulator ............................................................................... 401
Regulating Pulse Width Modulator .............................................................................. 713
Regulating Pulse Width Modulator .............................................................................. 721
Supply Voltage Supervisors ........................................................................................ 883
Control Circuit for Fast Switch ..................................................................................... 887
Programmable, Off-Line, PWM Controllers ................................................................. 921
Current Mode PWM Controllers .................................................................................. 931
Current Mode PWM Controllers .................................................................................. 931
Current Mode PWM Controllers ................................................................................. 931
Current Mode PWM Controllers .................................................................................. 931
Switch Mode Regulator Module .................................................................................... 97
Switch Mode Regulator Module .................................................................................. 119
Switch Mode Regulator Module .................................................................................. 129
Switch Mode regulator Module .................................................................................... 137

17

!

r

DATASHEETS

19

AM6012
AM6012A

!

""

12-BIT HIGH SPEED D/A CONVERTERS
• ALL GRADES 12-BIT MONOTONIC OVER
TEMPERATURE
• DIFFERENTAL NONLINEARITY TO ±0.012%
(13 BITS) MAX OVER TEMPERATURE
(A GRADES)
• 250ns TYPICAL SETTLING TIME
• FULL SCALE CURRENT 4mA
• HIGH SPEED MULTIPLYING CAPABILITY
DIP-20 Plastic

• TTLlCMOS/ECLlHTL COMPATIBLE

SO-20L

(0.4)

• HIGH OUTPUT COMPLIANCE: - 5V TO + 10V
• COMPLEMENTARY CURRENT OUTPUTS
PIN CONNECTION

• LOW POWER CONSUMPTION: 230mW

DESCRIPTION
The AM6012 is an industry standard monolithic
12-bit digital-to analog converter. Complementary
current output and high speed multiplying capability make the AM6012 useful in a wide range of applications such as video displays, process control
circuitry and fast ND converters. The 6012 is the
first D/A to achieve 12-bit differential linearity without the use of thin film resistors or active trimming. The 6012's unique circuit design insures
monotonicity without the precision trimming associated with most other 12-bit DAC architectures.
The AM6012 is packaged in a 20-pin plastic DIP
and is SO-20L for surface mounting. Although tested and specified at ± 15V, the AM6012 works well
over a wide range of power supply Voltages. Performance is essentially independent of supply voltage over the range of + 5 volts, - 12 volts to ± 18
volts. The AM6012 series guarantees full 12-bit manotonicity for all grades and differential nonlinearity as high as 0.012% (13 bits) for the A grades
and 0.025% (12 bits) for the standard grades over
the entire temperature range.
Guaranteed monotonicity and low cost make the
AM6012 an ideal choice for high volume applications requiring fine local resolution. Typical applications include printer graphics and video displays.
These applications need a minimum of 12 bits of
resolution, although conformance to an ideal
straight line from zero to full scale is less important.
June 1988

MS8-81
82

+VS
10

83

10

84

-VEE

85

COMPo

86

VREF (-)

87

VREF (+j

88

GNO/VLC

89

812-LS8

810

811
A60f2-2

1112

21

AM6012-AM6012A
ABSOLUTE MAXIMUM RATINGS

o to 70
-65 to + 125
±18
-5 to + 18
-8 to + 12
+VS to -VEE ±18V
max Differential
1.25

Operating Temperature Range
Storage Temperature
Power Supply Voltage
Logic Inputs
Voltage at Current Outputs Pins
Reference Inputs
Reference Input Current

°C
°C
V
V
V
V
mA

CONNECTION DIAGRAM AND ORDERING INFORMATION
Type

Differential
linearity (%)

AM6012PC

0.025

AM6012APC

0.012

AM6012 D

0.025

AM6012 AD

0.012

Temperature
Range (OC)

Package

o to 70

DIP.20

01070

SO.20L

BLOCK DIAGRAM
MSB

LSB

B1

B2

2

B3

B4 B5 B6

B7 BB B9 B10 B11 B12

3

AM6012

REFERENCE

20

R R R R
CODE SELECTED

NETWORK

0111 1111 1111

SEGMENT GENERATOR

17

VEE

THERMAL DATA
Rlhj-amb
2/12

22

13

GND

A6DII!-1

Thermal resistance junction-ambient

+VS

AM6012-AM6012A
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = + 15V, VEE = -15V, IREF = 1.0mA, over the operating temperature
range unless otherwise specified

",.

!

AM6012A
Paramo

Description

Test Conditions

Min.

Resolution

12

Monotonicity

12

-

D.N.L.

Differential
Nonlinearity

Deviation from ideal step size

N.L.

Nonlinearity

Deviation from ideal straight line

IFS

Full Scale Current

VREF= 10.000V
R14 = R15 = 10.000kQ
TA=2SoC

TCIFS

Full Scale Temp.Co.

Typ.

AM6012
Max.

Min.

12

12

12

Typ.

Max.

Units

12

12

12

12

12

Bits

12

12

Bits

-

±.012

-

-

±.02S

%FS

13

-

12

-

-

Bits

-

-

±.OS

-

-

±O.OS

%FS

3.967

3.999

4.031

3.93S

3.999

4.063

mA

-

±S

±20

-

±10

±40

ppmoC

-

±.OOOS

±.002

-

+10

-S

±1.0

-

Voe

Output Voltage
Compliance

D.N.L. Specification guaranteed
over compliance range
ROUT> 10 megohme typo

-S

IFSS

Full Scale
Symmetry

IFS·IFS

-

Izs

Zero Scale Current

±0.2

-

±.001

±OA

±.OO4 VoFSoC

+10

V

±2.0

~A

-

-

0.10

-

-

0.10

~A

-

2S0

SOD

-

2S0

SOD

nSec

-

2S

SO

-

2S

SO

nSec

-

20

-

pF

IS

Setting Time

To ± 112 LSB, all bits ON or
OFF, TA =2SoC

tpLH
tpHL

Propagation
Delay· all bits

SO% to SO%

COUT

Output Capacitance

-

20

-

VIL

-

-

0.8

-

-

0.8

VIH

Logic Logic "a"
Input
Levels Logic "1"

2.0

-

-

2.0

-

-

liN

Logic Input Current

VIN= -S to +18V

-

-

40

-

-

40

~A

VIS

Logic Input Swing

VEE= -lSV

-S

-

+18

-S

-

+18

V

IREF

Reference Current
Range

0.2

1.0

1.1

0.2

1.0

1.1

mA

115

Reference Bias
Current

0

-O.S

-2.0

0

-O.S

-2.0

~A

V

3/12

23

AM6012-A:M6012A
ELECTRICAL CHARACTERISTICS (Continued)
AM6012A
Paramo
di/dt

Description
Reference Input
Slew Rate

PSSIFS+
Power Supply
Sensitivity
PSSIFSVs
VEE

Power Supply
Range

Test Conditions

Min.

Typ.

Max.

Min.

Typ.

Max.

Units

RI4(eq) =8000
CC=OpF

4.0

8.0

-

4.0

8.0

-

rnAJ~s

Vs=( + 13.5V to + 16.5V)
VEE= -15V

-

±.00005 ±.001

-

±0.0005 ±.001

VEE = -13.5V to -16.5V
VS=+15V

-

±.00025 ±.001

-

±.00025 ±.001

VoFS/%

4.5

-

18

4.5

-

18

-18

-

-10.8

-18

-

-10.8

VOUT=OV

1+
Vs = +5V, VEE= -15V
1-

Power Supply
Current
Vs= +15V, VEE= -15V

1PD

V

-

5.7

8.5

-

5.7

8.5

-

-13.7

-18.0

-

-13.7

-18.0

5.7

8.5

-

5.7

8.5

-13.7

-18.0

-

-13.7

-18.0

1+

Power
Dissipation

AM6012

-

Vs= +5V, VEE= -15V

-

234

312

-

234

312

VS= +15V, VEE= -15V

-

291

397

-

291

397

Fig. 1 - Relative Accuracy Error

rnA

rnW

Fig. 2 - Example of Nonmonotonic Behavior

OUTPUT

OUTPUT
CURRENT

DIGITAL INPUT CODE

A6012-JO:: DIS

4/12

24

A60J2-fO:: LIB

AM6012-AM6012A
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The segmented design of the AM6012, shown in
the block diagram, insures that there are no sIgnIficant differential nonlinearities in the transfer characteristic. The eight major carries of the most
significant bits are not subject to the gross differential nonlinearities that can occasionally occur
in an R-2R type DAC. This advantage is due to the
fundamentally different way that the current is handled in an AM6012.
In a conventional R-2R type DAC, when the input
code is increemented past a major carry, a current
representing the new code is substituted for the
sum of all the less significant bit currents that were previously on. To avoid any nonlinearities, the
two total currents must be extremely well matched.
In the case of the MSB major carry in a 12-bit DAC,
the match must be better than one part in 2048 to
maintain monotonicity. However, in the AM6012,
a new current is never substituted for the sum of
several smaller ones, but redirected through alternate channels and incremented one step at a time.
For example, consider the MSB carry in an
AM6012. In the initial state of 011111111111 as
shown in the block diagram, the switches in the
segment generator are set in such a way that currents 10, II and 12 are steered directly into the noninverting output lOUT. In addition, a portion of 13
is directed through the 9-bit DAC that is controlled
by the 9 least significant bits into lOUT. With the
9LSBs set to "I", all of the 13 current is directed
to lOUT except for the 11512 that goes to ground
through the right-most transistor in the 9-bit DAC.
After the input word is changed to 100000000000,
the segment decoder switch for 13 will be all the
way to the right, the switch for 14 will be in the middle, and all the switches in the 9-bit DAC will be
to the left. lOUT will be composed of 10, h, 12 and
13. None of 14 will be directed into lOUT until a higher code is reached. In other words.. 13 i~ .now
steered directly to lOUT instead of being divided
by a factor of 511/512 in the 9-bit DAC. Since no
major current substitution occurs, there is less
chance of a large nonlinearity at this transition than
in a comparable R-2R DAC.

that results in a maximum relative accuracy error
of 3LSB. This must be distinguished from a differentiallinearityerror. Differential nonlinearity is the
measure of the variation in analog value, normalized to full scale, associated with a ILSB change
in digital input code.
For example, for a 4mA full scale output, a change of ILSB in digital input code should result in a
0.98fLA change in the analog output current
(ILSB = 4mA x 1/4096 = 0.98fLA). If in actual use,
however, a ILSB change in the input code results
ina change of only 0.24fLA (1/4LSB) in output current, the differential linearity error would be 0.74fLA
or 3/4LSB.
The AM6012 has very good differential linearity in
spite of the porr relative accuracy. Conversely, the
DAC of Figure 1 has very good relative accuracy
but poor differential linearity. The anomaly in the
middle of the transfer function is the result of a positive differential linearity error followed by a negative differential linearity error greatertha~ 1LS.B.
A negative output step for an increase .In dlgltal.lnput code is referred to as non monotonic behaVIOr.
In general, if a DAC has a differential linearity error specification greater than 1LSB, it may be nonmonotonic at one or more of the major carries. In
most case the worst differential linearity error will
occur at the MSB transition point.
As noted in the functional description, the 6012's
unique design minimizes differential linearity errors
at the transition points of the 3MSBs. This results
in a tight specification on maximum di~erential.no~­
linearity over temperature. Differential linearity IS
verified on all AM6012s with 100% final testing.
In many converter applications, uniform step size
(or minimum differential linearity error) is more important than conformance to an ideal straight li~e.
Twelve-bit onverters are usually needed for high
resolution rather than high linearity as evidenced
by the fact that few transducers are more linear
than 0.1 %. This is also true in video graphiCS, where the human eye has difficulty discerning nonlinearity of less than 5%. The AM6012 is especially
well suited for these applications since it has inherently low differential linearity error.

RELATIVE ACCURACY VS. DIFFERENTIAL NONLINEARITY
We defines relative accuracy as the maximum deviation of the actual, adjusted DAC output from the
ideal analog output (a straight line drawn between
the lowest code output voltage and the highest code output voltage) for any bit combination. Relative accuracy is often referred to as nonlinearity. The
DAC transfer function shown in Figure 1 has a bow

5/12

25

AM6012-AM6012A
APPLICATION INFORMATION (Continued)
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents
are provided where 10 + 10 = IFR. Current appears
at the "true" output when a "1" is applied to each
logic input. As the binary count increases, the sink
current at pin 18 increases proportionally, in the
fashion of a "positive logic" D/A converter. When
a "0" is applied to any input bit, that current is turned off at pin 18 and turned on at pin 19. A decreasing logic count increase 10 as in a negative or
inverter logic D/A converter. Both outputs may be
used simultaneously. If one of the outputs is not
required it must still be connected to ground or to
a point capable of sourcing IFR; do not leave an
unused output pin one.
Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other
voltage source. Positive compliance is 25V above
V - and is independent of the positive supply. Negative compliance is + 10V above V - .
The dual outputs enable double the usual peak-topeak load swing when driving loads in quasidifferential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The AM6012 operates over a wide range of power
supply voltages from a total supply of 20V to 36V.
When operating with V - supplies of -10Vor less,
IREF :51 mA is recommended. Low reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative common mode range, negative logic
input range, and negative logic threshold range;
consult the various figures fro guidance. For example, operation at - 9V with IREF = 1mA is not recommended because negative output compliance
would be reduced to near zero. Operation from lower supplies is possible, however at least 8V total
must be applied to insure turn-on of the internal
bias network.
Symmetrical supplies are not required, as the
AM6012 is quite insensitive to variations in supply
voltage. Battery operation is feasible as no ground
connection is required; however, an artificial ground
may be used to insure logic swings, etc. remain
between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and mononicity specifications of
the AM6012 are guaranteed to apply over the entire rated operating temperature range. Full scale
6/12

26

output current drift is flight, typically ± 10ppm/oC
with zero scale output current and drift essentially
negligible compared to 1/2 LSB.
The temperature coefficient of the reference resi·
stor R14 should match and track that of the output resistor for minimum overall full scale drift.

SETTLING TIME
The AM6012 is capable of extremely fast settling
times, typically 250ns at IREF = 1.0mA. Judicious
circuit design and careful board layout must be employed to obtain full performance potential during
testing and application. The logic switch design
enables propagation delays of only 25ns for each
of the 12 bits. Settling time to within 1/2 LSB of the
LSB is therefore 25ns, with each progressively larger bit taking successively longer. The MSB settles in 250ns, thus determining the overall settling
time of 250ns. Settling to 1O-bit accuracy requires
about 90 to 130ms. The output capacitance of the
AM6012 including the package is approximately
20pF; therefore, the output RC time constant dominates settling time if RL > 500n.
Settling time and propagation delay are relatively
insensitive to logic input amplitude and rise and fall
times, due to the high gain of the logic switches.
Settling time also remains essentially constant for
IREF values down to 0.5mA, with gradual increases for lower IREF values lies in the ability to attain a given output level with lower load resistors,
thus reducing the output RC time constant.
Measurement of settling time requires the ability
to accurately resolve ± 2p,A, therefore a 2.5kO load
is needed to provide adequate drive for most oscilloscopes. At IREF values of less than 0.5mA, excessive RC damping of the output is difficult to
prevent while maintaining adequate sensitivity. However, the major carry from 011111111111 to
100000000000 provides an accurate indicator of
settling time. This code change does not require
the normal 6.2 time constants to settle to within
± 0.1 % of the final value, and thus settling times
may be observed at lower values of IREF.
AM6012 switching transients or "glitches" are very
low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time.
Fastest operation can be octained by using short
leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the
supply, reference, and VLC terminals. Supplies do
not require large electrolytic bypass capacitors as
the supply current drain is independent of input logic states; 0.1 p,F capacitors at the supply pins provide full transient protection.

AM6012-AM6012A
APPLICATION INFORMATION (Continued)
REFERENCE AMPLIFIER SETUP
The AM6012 is a multiplying DIA converter in which
the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly
zero to + 1.0mA. The full range output current is
a linear function of the reference current and is given by:
4095
IRF= --x4x(IREF)=3.999 IREF,
4096
where IREF = 114
In positive reference applications, an external positive reference voltage forces current through R14
into the VREF( +) terminal (pin 14) of the reference
amplifier. Alternatively, a negative reference may
be applied to VREF( -) at pin 15. Reference current
flows from ground through R14 into VREF( +) as in
the positive reference case. This negative reference
connection has the advantage of a very high impedance presented at pin 15. The voltage at pin
14 is equal to and tracks the voltage at pin 15 due
to the high gain of the internal reference amplifier.
R15 (nominally equal to R14) is used to cancel bias
current errors. (Figure 3).
Bipolar references may be accommodated by offsetting VREF or pin 15. The negative commonmode range of the reference amplifier is given by:
VCM - = V - plus (lREF x 3kfl) plus 1.SV. The positive common-mode range is V + less 1.23V.
When a DC reference is used, a reference bypass
capacitor is recommended. A 5.0V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14
should be split into two resistors with the junction
bypassed to ground with a 0.11'F capacitor.
For most applications the tight relationship between
IREF and IFS will eliminate the need for trimming
IREF. If required, full scale trimming may be accomplished by adjusting the value of R14, or by
using a potentiometer for R14.

MULTIPLYING OPERATION
The AM6012 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 1mA to 11'A.
Monotonic operation is maintained over a typical
range of IREF from 100l'A to 1.0mA.

REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to be compensated using a capacitor
from pin 16 to V - . The value of this capacitor depends on the impedance presented to pin 14. For
R14 values of 1.0, 2.5 and 5 Okfl; minimum values
of Cc are 5, 12 and 25 pF. larger values of R14
require proportionately increased values of Cc for
proper phase margin (See Figure 4 and 5).
For fastest response to a pulse, low values of R14
enabling small Cc values should be used. If pin 14
is driven be a high impedance such as a transistor
current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall compensated which
will decrease overall bandwidth and slew rate. For
R14 = 1kfl and Cc = 5pF, the reference amplifier
slews at 4mAlms enabling a transition from
IREF = 0 to IREF = 1mA in 250ns.
Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest
full scale transition times. An internal clamp allows
quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full scale transition (0 to
1mAl occurs in 62.5ns when the equiyalent impedance at pin 14 is SOOfl and Cc = O. This yields a
reference slew rate of SmAIl'S which is relatively
independent of RIN and VIN values.

lOGIC INPUTS
The AM6012 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise
immunity. This feature is made possible by the large input swing capability, 40l'A logic input current,
and completely adjustable logic inputs may swing
between - 5 and + 1OV.
This enables direct interface with + 15V CMOS logic, even when the AM6012 is powered from a + 5V
supply. Minimum input logic swing and minimum
logic threshold may be adjusted over a wide range
by placing an appropriate voltage at the logic threshold control pin (pin 13, VLC). For TTL interface,
simply ground pin 13. When interfacing ECl, an
IREF ::5 1mA is recommended. For interfacing
other logic families, see block titled "Interfacing
with Various Logic Families". For general setup of
the logic control circuit, it should be noted that pin
13 will sink 1.1 mA typical, external circuitry should
be designed to accommodate this current (Figure 6).
7/12

27

AM6012-AM6012A
Fig. 3 - Reference amplifier biasing

AM6012

R14

VIN~ RIN

IO

1B

IO +IO - IFS
FOR ALL INPUT CODES

VIN~

R15

16

20

CDM~--,
CC

17

v-

Reference Configuration

---r-;--:J

I

I ~. 1

T 1:::c
v+

19

..L.0 .1..L. 22,uF

20:::C:C

v-

TANT.

(NOTE 5)

A60!2-8,',' LIB

R14

R15

RIN

Cc

Positive Reference

VR+

OV

N/C

.D1JlF

VR+/R14

Negative Reference

OV

VR-

N/C

.01JlF

-VR-/R14

La Impedance Bipolar
Reference

VR+

OV

VIN

(Note 1)

VR+/R14) + (VIN/RIN)
(Note 2)

Hi Impedance Bipolar
Reference

VR+

VIN

N/C

(Note 1)

(VR+ - VIN)/R14
(Note 3)

Pulsed Reference (Note 4)

VR+

OV

VIN

No Cap

(VR +/R14) + (VIN/RIN)

IREF

Notes:
1. The compensation capacitor a function of the impedance seen at the + VREF input and must be at least 5pF x R14(eq)
in kn. For R14 < 800n no capacitor is necessary.
2. For negative values of VIN, VR+/R14 must be greater than -VIN Max/RIN so that the amplifier is not turned off.
3. For positive values of VIN, VR + rnust be greater than VIN Max so the amplifier is not turned off.
4. For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at pin 14
should be 800n or less.
5. For optimum settling time, decouple V . with 20n and bypass with 22/,F tantulum capacitor.
6. Reference current and reference resistor - there is a 1 to 4 schale factor between the reference current (IREF) and
the full scale output current (IFS). If VREF= + 10V and IFS=4mA, the value of the R14 is:

8/12

28

AM6012-AM6012A
Fig. 4 - Minimum size compensation capacitor
(IFS 4mA, IREF 1.0mA)

=

=

R14(EQ)(KO)

Cc(pF)

10

50
25

5
2

Fig. 5 . Reference Amplifier Frequency response

(dB)

H=

10

3

5
0

o

1

5

Note: A 0.01 ~F capacitor IS recommended for fixed reference operation.

-3
-6

I

I
SMALL SIGNAL
LARGE SIGNAL

~

--;::- :.<\
,
,

\1\

rl

J

I

I
0.01

'\
\'\

I

R14=2K
Cc = 10~F

1

0.1

10
(MHz)

A6012-JJ:: OI

Fig. 6 • Interfacing Circuits

Fig. 7 • Accomodating Bipolar Reference

VAEF +

CMOS
+ 15V

RREF

VIN

RIN'

" A"

20K

IREF

o-~I~in::r-l:.l~41.=:-:-::-'

470

d

18 Io

AM6012

..C"----J 19 Io

13
3K

510

IREF > PEAK NEGATIVE SWING OF Iin

~REF

ECl

RREF 1 4 - - - , 18 Io

(+)

~

o·-=-~·::r
~

VIN HIGH

INPI~T

AM6012

~

f;-;;-o

19 Io

IMPEDANCE

13K
VREF

" A"

o

(+)

MUST BE ABOVE PEAK POSITIVE SWING OF VIN

PIN 13

6.2K
-

5.2V

9/12

29

AM6012-AM6012A
Fig. 8 • AM6012 Logic Inputs

e

2 mA

KOhm

~

RS

R1

ROFF
E

R14
10 KOhm , -_ _ _ _ _ _ _,

HOV
REF

1---4~--C::=]--i VREF (+)

AM6012
(-)

R14

VREF

1.0mA

812

R15
10 KOhm

iO,,--,-G

1

LSB

2.0mA

Slraighl bynary
one polarity
with true input
code, true zero
output.

a-c
b-g
RFR2~2.5K

Complementary
binary one
Rl
polarity with
complementary
input code, true
zero output.

Slraighloffset
binary; offset
half scale, symmetrical about
zero, no true
zero output.

a-g
b-c
~R2~2.5K

a-c
b-d
f-O
Rl

~R3~2.5K

R2~

l' s complement
offsel half scale
symmetrical
about zero, no
true zero output

Output
Scale

Connec.

Code Format

Symmetrical
Offsel

D

OPTIONAL
(SEE CODE TABLE)

ROFF = VREF

Unipolar

>_............ VOUT
10

1.25K

a-c
b-d
f-g
Rl

~R3~2.5K

R2~

1.25K

MSB comple-

.A60J2-7." ." LIB

MS8

LS8

10

10

Vour

Bl 82 83 84 85 86 87 88 89 810 811 812

Positive full scale
Positive full scale-LSB
Zero scale

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

0
0

3.999
3.998
.000

.000
.001
3.999

9.9978
9.9951
.0000

Positive full scale
Positive full scale-LSB
Zero scale

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
0
1

0
1
1

.000
.001
3.999

3.999
3.998
.000

9.9976
9.9951
.0000

Positive full scale

1
1
1
0
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
0
0
1
1
0

3.999
3.998
2.000
1.999
.001
.000

.000
.001
1.999
2.000
3.998
3.999

9.9976
9.9927
.0024
-.0024
-9.9927
-9.9976

0
0
0
I
1
I

1
I
0
I
0
0

1
1
0
1
0
0

1
I
0
1
0
0

1
I
0
1
0
0

1
1
0
1
0
0

1
I
0
I
0
0

1
1
0
1
0
0

1
I
0
1
0
0

1
I
0
I
0
0

1
I
0
1
0
0

1
0
0
1
1
0

3.999
3.998
2.000
1.999
.001
.000

.000
.001
1.999
2.000
3.998
3.999

9.9976
9.9927
.0024
-.0024
-9.9927
-9.9976

I
1
I
1
0
0
0

1
I
0
0
I
0
0

1
1
0
0
I
0
0

I
1
0
0
1
0

1
1
0
0
1

1
1
0
0
1
0
0

1
1
0
0
1
0
0

a
1
0
0

I
1
0
0
1
0

0

1
1
0
0
I
0
0

1
1
0

a

I
I
0
0
1
0
0

a

1
0
1
0
1
1
0

3.999
3.998
2.001
2.000
1.999
.001
.000

.000
.001
1.998
1.999
2.000
3.998
3.999

9.9951
9.9902
.0049
.000
-.0049
-9.9951
-10.000

0
0
0
0
I
1
1

1
I
0
0
I
0
0

1
I
0
0
I
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

I
I
0
0
I
0
0

1
1
0
0
1
0
0

1
I
0
0
1
0
0

1
1
0
0
I
0
0

I
1
0
0
1
0
0

1
1
0
0
1
0
0

1

3.999
3.998
2.001
2.000
1.999
.001
.000

.006
.001
1.998
1.999
2.000
3.998
3.999

9.9951
9.9902
.0049
.000
-0.049
-9.9951
-10.000

Posilive full scale-LSB
I + I Zero scale
I-I Zero scale
Negalive full scale-LSB
Negative fu II scale
Positive full scale
Positive full scale-LSB

I + I Zero scale
I-I Zero scale
Negalive full scale-LSB
Negative full scale

1

mented (need
inverter at B1).

Offsel binary,
offsel half
scale, true zero
output.

e-a-c

b-g
Rl~R2~5K

Positive fu II scale
Positive full scale-LSB

+LSB
Zero Scale

-LSB
Negalive full scale+LSB
Offsel wilh
True Zero

Negative full scale
2's complement

e-a-c

offsel half scale

b-g

true zero output

RI~R2~5K

Positive full scale
Positive full scale-LSB

+1 LSB

MSB com ple-

Zero scale

mented (need
inverter at B1)

-1 LSB
Negalive full scale+ LSB
Negative full scale

a

a
1
0
1
1
0

ADDITIONAL CODE MODIFICATIONS
1. Any of the offset binary codes may be complemented by reversing the output terminal pair.

10/12

30

AM6012-AM6012A
Fig. 10 - Recommended Full-scale Adjustment Circuit

Fig. 9 - Basic Negative Reference Operation

RREF

VREF (-)

~
.
R15

Io

14

~1B
AM6012

19

15L------~

VREF
+ 5V

Io

Fig. 11 - CRT Display Driver

+120V DC

"X" INPUT

"y"

INPUT

•

o

-15V
--+

10

A60t2-5: : LI .

Fig. 12 - 12-BIT High-Speed AID Converter

CLOCK

LSB

+ i5V
VAEF

ANALOB IN

lo-i0Yl

+ i0V
5.000K

lIEF

1>.1IOOK

MSB

AM6012
COlI'

I

iDnF iuF

VI-)

iuF

V1+)

A6fU2-fl: : LIB

11/12

31

AM6012-AM6012A
Fig. 13 - Interface with 8-blt Microprocessor Bus

I

MSB

7
6

DE

3
2
1

LS373

5
4

o

AM

E2

E1 -

'-

EA

D3A

I

-

6012

EB
~

D2A

G3A
Q2A

-

D3B
D2B

DiA

QiA -

DiB

GiB -

DOA

GOA

DOB

GOB

-

1/2LS100

G3B
G2B

~

-

LSB

1/2LS100
A6012-4: : LIB

Fig. 14 - Interface with digital signal processor TS68930/31

+151.)

r
DB-7

18K
Vref+

Us
28

HC374

14

B12-5

CP

B

AM6012

B

OUT

AM6012A

DB11

B4-2
12

TS6B938/
31

Vref

B.1uF

B1
HCB4

os

E2

AB

El

HC13B

00

GHD

Uref-

1BK

-UEE

CaMP

2B.
B
[2[
uF. 2uF
-15U

A9-11

12112

32

3

A.

BBIII15812-51

DAC0808
DAC0807
DAC0806

8-BIT D/A CONVERTERS
• RELATIVE ACCURACY: ±O.19% ERROR MAXIMUM (DAC0808)
• FULL SCALE CURRENT MATCH: ± 1 LSB TYP
• 7 AND 6-BIT ACCURACY AVAILABLE
(DAC0807, DAC0806)
• FAST SETTING TIME: 150 ns TYP
• NONINVERTING DIGITAL INPUTS ARE TTL
AND CMOS COMPATIBLE
• HIGH SPEED MULTIPLYING INPUT SLEW RATE: 8 mAIl's
• POWER SUPPLY VOLTAGE RANGE: ±4.5V
to ±18V
• LOW POWER CONSUMPTION: 33 mW @±5V

SO-16J

DIP-16 Plastic (0.25)
and Ceramic

PIN CONNECTION

COMP

N.C.

(-)

GNO

VREF

(+) VREF

DESCRIPTION
The DAC0808 series is an 8-bit monolithic digitalto-analog converter (DAC) featuring a full scale output current settling time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference
current (IREF) trimming is required for most applications since the full scale output current is typically ± 1 LSB of 255 IREF/256. Relative accuracies
of better than 0.19% assure 8-bit monotonicity and
linearity while zero I,evel output current of less than
41'A provides 8-bit zero accuracy for IREF~2 mAo
The power supply currents of the DAC0808 series
are independent of bit codes, and exhibits essentially constant device characteristics over the entire supply voltage range.

10

+VS

Ai

A8

A2

A7

A3

A6

A4

9

A5

DACOBOB-t3

The DAC0808 will interface directly with popular
TTL, or CMOS logic levels, and is a direct replacement for the MC1508/MC1408.
June 1988

1/11

33

DAC0808-0807-0806
ABSOLUTE MAXIMUM RATINGS
Supply Voltage

Vs

+18
V
-18
V
-10 V to + 18
V
5
rnA
VCC ,VEE

VEE
Digital Input Voltage V5 - V12
Reference Current, 114
Reference Amplifier Inputs, V14, V15
Operating Temperature Range
DAC0808L
DAC0808LCID1

-55°C:5TA:5 + 125°C
O:5TA:5 + 75°C
-65°C to + 150°C

Storage Temperature Range
ORDERING INFORMATION
Accuracy

Temperature
range

Plastic
DIP-16

Ceramic
DIP-16

SO-16

8 bit

o to 75°C

DAC0808LCN

DAC0808LCJ

DAC0808D

7 bit

o to 75°C

DAC0807LCN

DAC0807LCJ

DAC0807D

6 bit

o to 75°C

DAC0806LCN

DAC0806LCJ

DAC0806D

8 bit

-55 to 125°C

-

DAC0808W

-

BLOCK DIAGRAM

+VS

Ai

A2

A3

A4

A5

A6

A7

AS

+o--t-f--+-----.

DACOBOB-J
THERMAL DATA

Rthj-amb
2111

34

Thermal resistance junction-ambient max

Ceramic
DIP-16

SO-16

Plastic
DIP-16

150°C/W

120°C/W

100°C/W

DAC0808-0807-0806
ELECTRICAL CHARACTERISTICS
(VS=5V, VEE= -15V, VREF/R14=2 rnA, TA=TMIN to TMAX and all digital inputs at high logic level
unless otherwise noted.)
Parameter
Er

Test Conditions

tpLH
tpHL

Propagation Delay Time

TClo

Output Full Scale Current Drift

MSB
VIH
VIL

Digital Input Logic Levels
High Level, Logic "1"
Low Level, Logic "0"

(Figure 9)

MSB

Digital Input Current
High Level
Low Level

(Figure 9)
VIH=5V
VIL=O.BV

Reference Input Bias Current
Output Current Range

(Figure 3)
(Figure 9)
VEE= -5V
VEE= -15V, TA=25°C

115

10

Output Current
Output Current, All Bits Low
Output Voltage Compliance
VEE= -5V
VEE Below -10V

SRI REF

Min.

Relative Accuracy (Error Relative (Figure 10)
to Full Scale 10)
DACOBOBL
DACOB07LCIDI
(Note 1)
DACOB06LCIDI
(Note 1)
Settling Time to Within 1/2 LSB T A = 25°C (Note 2)
(Figure 11)
(Includes tpLH)

Reference Current Siew Rate
Output Current Power Supply
Sensitivity

%
%
%
ns

100

ns

150
30

ppm/DC

2

VREF = 2.000V.
RI4=1000{l
(Figure 9)
(Figure 9)
Er ",0.19%, T A =25°C

(Figure 14)
-5V",VEE'" -16.5V

Power Supply Voltage Range
Vs
VEE

T A = 25°C (Figure 9)

O.B

VDC
VDC

0
-0.003

0.040
-O.B

mA
mA

-1

-3

p.A

0
0

2.0
2.0

2.1
4.2

mA
mA

1.9

1.99
0

2.1
4

mA
p.A

-0.55, + 0.4
- 5.0 , + 0.4

V
V

2.7

mAlp.s
p.AlV

4

B
0.05

2.3
-4.3
4.5
5.0
-4.5 -15
VS=5V.vEE= -5V
Vs = 5V.VEE = -15V
Vs=15V.vEE=-5V
Vs=15V.VEE= -15V

Unit

±0.19
±0.39
±0.7B

±20

(Figure 9)

All Bits High

Max.

%

T A = 25°C (Figure 11)

Power Supply Current (All Bits Low)
IS
lEE

Power Dissipation
All Bits Low

Typ.

33
106
90
160

22
-13
5.5
-16.5
170
305

mA

V
mW
mW
mW
mW

Note 1 All current sWitches are tested to guarantee at least 50% of rated current.
Note 2 All bits switched.
Note 3 Range control is not required.

3/11

35

DAC0808-0807-0806
Fig. 1 • Supply Current vs
Temperature

Fig. 2 • Supply Current vs Supply
Voltage (VEE)

Fig. 3 • Supply Current vs Supply
Voltage IYs}

Icc

(mA) HALL 8ITS HIGH OR LOW f
8
1 1 1 1 I
~ ~ lEE (1 14 =2mA) 6
TTTTT
l -l - lEE (114 =1mA) - '"-"
4
IE (1 14 =0.2mA) ~ ~
~~

Icc

Icc
(mA) ~ALL 8ITS HIGH OR LOW

ff ALL

(mA)
8

8ITS HIGH OR LDW1
114 2mA
1
lEE

6

4

2

~

2

1,5
-50

0

50

4

12

8

T

l

10

Ai THROUGH A8 I--

II

2

0

4

8

'l

(V)

Fig. 7· Output Voltage-Compliance
vs Temperature

0.6

SHADED AREA

8 l-

-16

4/11

36

o

V=I~I
-4

0

4

8

12 VL

12

8

Vs (V)

Fig. 6 • Output Voltage Compliance

ON

ALL BITS

I

2.4

VEi=-15V VE~=-5V

I

jT

I14=2mA

A2

1.2

I1'4JmA

A3

0.8

A4
A5

0.4

IJo.~mA

INDICATES

I

PERMISSIBLE OUTPUT

\OEL;_A_GE RANGE FOR
16V. I 14-2mA

l -l l -l -

o
-4

~~

~ ~ ~ ~ ~ ~~

-8
-12

-50

o

50

1 0 0 T A(0 C)

(V)

Fig. 8 • Frequency response

'"

1\\ I\.,

A

-16
0.1 0.20.5 1

~

\c
2

-14 -10 -6 -2

2

6

10 Vo (V)

Curve A: Large Signal Bandwidth
Method of Figure 7, VREF=2 Vp·p
offset 1 V above ground

B

~ '"'
/""

~

o

Unless otherwise specified: R14 =
R15=1 kO,C=15pF,pin16toVEE;
RL = 500, pin 4 to ground.

,

4

~~ ~ ~ ~ ~~
l-

151 (II 1,4 =12 mt) f- f4

2

(dB)

Vo
(V)

o~

-

0.4

-8 -4

16

I EE (I 14 =2mA) f-

1.6

0.2

o

-

10

0.8
L-

f-

(mA)

I 14 =2mA

Ai
4

-

VEE (V)

Fig. 5 • Bit Transfer Characteristics

(mA)

4

2

1~

1 0 0 T A (0 C)

Fig. 4 • Logic Input Current vs
Input Voltage

-8

6

I

o

f

8

(MHz)

Curve B: Small Signal Bandwidth
Method of Figure 7, RL = 2500,
VREF=50 mVp·p offset 200 mV
above ground.
Curve C: Large and Small Signal
Bandwidth Method of Figure 9 (no
op amp. RL = 500), RS = 500,
VREF= 2V, Vs = 100 mVp·p centered
at OV.

DAC0808-0807-0806
Test Circuits
FIGURE 9. Notation Definitions

+Vs
13

The resistor tied to pin 15 is to temperature compensate the bias current and may not be necessary for all applications.

VREF

A3

IO=K(A1+A2+A3+A4+A5+A6+A7 +A8)
2
4
8 16 32 64 128 256

A4
A5
A6

VREF

where K == R14
and AN = "1" if AN is at high level
AN = "0" if AN is at low level

FIGURE 10. Relative Accuracy

A1

~~~~§ 12 BIT

Vo- 0 to 10V

D to A

MSB

5

13

6
7

B
DAC
8 BIT H:>-----<~++-o--:-l
9
COUNTERI--o--~+I-+-o-~ 0808
10
11
12

LSB

50 Kohm

14

950

1Kohm

OAC0808-4

-VEE

5/11

37

DAC0808-0807-0S06
FIGURE 11. Transient Response and Settling Time

Yin

(Vi

._-------

2.4
+2V

V

\

0.4
VO

(Vi

0.7

INTERNAL

r'"

SETTLING
TIME

..JL
5.10

Vo

TRANSIENT
RESPONSE

100 nF

rI

1 4V

I~

~ CLAMP

LEVEL

Is= 150ns TYP.

if-

k-

-100

OAC0808-5

FIGURE 12. Positive VREF

-------l>

~ OAC0808-14

~

FIGURE 13. Negative VREF

+Vs

VREF

...JL

A2
A3

A3

A4

A4
A5

A5
A6

6/11

38

VO

Lr

A6

A7

A7

-VEE

-VEE

vo

Lr

r--

DAC0808-0807-0806
FIGURE 14. Reference Current Slew Rate Measurement

The reference amplifier provides a voltage at pin
14 for converting the reference voltage to a current, and a turn-around circuit or current mirror for
feeding the ladder. The reference amplifier input
current, 114, must always flow into pin 14, regardless of the set-up method or reference voltage polarity,

1 Kohm

15

DAC

2

1 Kohm

TO
SCOPE
-VEE

3

15 pF

REFERENCE AMPLIFIER DRIVE AND COMPENSATION

~~~~20mA
I

'

I

ts

,

OAC0808-6

Connections for a positive voltage are shown in Figure 12. The reference voltage source supplies the
full current 114. For bipolar reference signals, as
in the multiplying mode, R15 can be tied to a negative voltage corresponding to the minimum input level. It is possible to eliminate R15 with only
a small sacrifice in accuracy and temperature drift,
The compensation capacitor value must be increased with increases in R14 to maintain proper phase margin; for R14 values of 1, 2.5 and 5 kD,
minimum capacitor values are 15,37 and 75 pF.
The capacitor may be tied to either VEE or ground,
but using VEE increases negative supply rejection.

APPLICATION INFORMATION
CIRCUIT DESCRIPTION
The DAC0808 consists of a reference current amplifier, an R-2R ladder, and eight high-speed current switches. For many applications, only a
reference resistor and reference voltage need be
added,
The switches are noninverting in operation, therefore a high state on the input turns on the specified output current component. The switch uses
current steering for high speed, and a termination
amplifier consisting of an active load gain stage
with unity gain feedback. The termination amplifier holds the parasitic capacitance of the ladder
at a constant voltage during switching and provides a low impedance termination of equal voltage
for all legs of the ladder.
The R-2R ladder divides the reference amplifier current into binarily-related components, which are fed
to the switches. Nota that there is always a remainder current which is equal to the last significant bit.
This current is shunted to ground, and the maximum output current is 255/256 of the reference amplifier current, or 1,992 mA for a 2.0 mA reference
amplifier current if the NPN current source pair is
perfectly matched,

A negative reference voltage may be used if R14
is grounded and the reference voltage is applied
to R15 as shown in Figure 13. A high input impedance is the main advantage of this method, Compensation involves a capacitor to VEE on pin 16,
using the values of the previous paragraph. The
negative reference voltage must be at least 3V above the VEE supply. Bipolar input signals may be
handled by connecting R14 to a positive reference voltage equal to the peak positive input level at
pin 15.
When a DC reference voltage is used, capacitive
by pass to ground is recommended, The 5V logic
supply is not recommended as a reference voltage, If a well regulated 5V supply which drives logic is to be used as the reference, R14 should be
decoupled by connecting it to 5V through another
resistor and bypassing the junction of the 2 resistors with 0,1 /-IF to ground, For reference voltages
greater than 5V, a clamp diode is recommended
between pin 14 and ground,
If pin 14 is driven by a high impedance such as a
transistor current source, none of the above compensation methods apply and the amplifier must
be heavily compensated, decreasing the overall
bandwidth,

7/11

39

DAC0808-0807-0806
OUTPUT VOLTAGE RANGE
The. voltage on pin 4 is restricted to a range of - 0.6
to 0.5V when VEE = - 5V due to the current switching methods employed in the DAC0808.
The negative output voltage compliance of the
DAC0808 is extended to - 5V where the negative
supply voltage is more negative than -10V. Using
a full-scale current of 1.992 mA and load resistor
of 2.5 kO between pin 4 and ground will yield a voltage output of 256 levels between 0 and - 4.980V.
Floating pin 1 does not affect the converter speed
or power dissipation. However, the value of the load
resistor determines the switching time due to increased voltage swing. Values of RL up to 5000
do not significantly affect performance, but a 2.5
kO load increases worst-case setting time to 1.2 p,s
(when all bits are switched ON). Refer to the subsequent text section on Settling Time for more details output loading.

OUTPUT CURRENT RANGE
The output current maximum rating of 4.2 mA may
be used only for negative supply voltages more negative than - 7V, due to the increased voltage drop
across the resistors in the reference current amplifier.

ACCURACY
Absolute accuracy is the measure of each output
current level with respect to its intended value, and
is dependent upon relative accuracy and full-scale
current drift. Relative accuracy is the measure of
each output current level as a fraction of the fullscale current. The relative accuracy of the
DAC0808 is essentially constant with temperature due to the excellent temperature tracking of the
monolithic resistor ladder. The reference current
may drift with temperature, causing a change in
the absolute accuracy of output current. However,
the DAC0808 has a very low full-scale current drift
with temperature.
The DAC0808 series is guaranteed accurate to within ± 1/2 LSB at a full-scale output current of 1.992
mA. This corresponds to a reference amplifier output current drive to the ladder network of 2 mA, with
the loss of 1 LSB (8 p,A) which is the ladder remainder shunted to ground. The input current to pin 14
has a guaranteed value of between 1.9 and 2.1 mA,
allowing some mis-match in the NPN current source pair. The accuracy test circuit is shown in Figure 10. The 12-bit converter is calibrated for a
full-scale output current of 1.992 mAo This is an optional step since the DAC0808 accuracy is essentially the same between 1.5 and 2.5 mA.
8111

40

Then the DAC0808 circuits' full-scale current is
trimmed to the same value with R14 so that a zero
value appears at the error amplifier output. The
counter is activated and the error band may be displayed on an oscilloscope, detected by comparators, or stored in a peak detector.
Two 8-bit D-to-A converters may not be used to construct a 16-bit accuracy D-to-A converter. 16-bit accuracy implies a total error of ± 1/2 of one part in
65,536, or ± 0.00076%, which is much more accurate than the ±0.019% specification provided
by the DAC0808.

MULTIPLYING ACCURACY
The DAC0808 may be used in the multiplying mode with 8-bit accuracy when the reference current
is varied Over a range of 256: 1. If the reference current in the multiplying mode ranges from 16 p,A to
4 mA, the additional error contributions are less
than 1.6 p,A. This is well within 8-bit accuracy when
referred to full-scale.
A monotonic converter is one which supplies an
increase in current for each increment in the binary word. Typically, the DAC0808 is monotonic for
all values of reference current above 0.5 mA. The
recommended range for operation with a DC reference current is 0.5 to 4 mAo

SETTLING TIME
The "worst case" switching condition occurs when
all bits are switched "on", which corresponds to
a low-high transition for all bits. This time is typically 150 ns for settling to within ± 1/2 LSB for 8-bit
accuracy and 100 ns to 1/2 LSB for 7 and 6-bit accuracy. The turn off is typically under 100 ns. These timers apply when RL .;;; 500 ohms and Co .;;; 25
pF.
The test circuit of Figure 11 requires a smaller voltage swing for the current switches due to internal
voltage clamping in the DAC0808 A 1.0-kilohm load
resistor from pin 4 to ground gives a typical settling time of 200 ns.
Thus, it is voltage swing and not the output RC time constant that determines setting time for most
applications.
Extra care must be taken in board layout since this
is usually the dominant factor in satisfactory test
results when measuring settling time.
Short leads, 100 p,F supply bypassing for low frequencies, and minimum scope lead length are all
mondatory.

DAC0808-0807-0806
PROGRAMMABLE GAIN AMPLIFIER OR DIGITAL ATTEPUATOR
When used in the multiplying mode can be applied
as a digital attenuator. See Figure 15. One advantage of this technique is that if Rs = 50 ohms, no
compensation capacitor is needed. The small and
large signal band are now identical and are shown
in Figure BC.
The best frequency response is obtained by not allowing 114 to reach zero. However, the high impedance node, pin 16, is clamped to prevent
saturation and insure fast recovery when the current through R14 goes to zero. Rs can be set for
a ± 1.0 mA variation in relation to 114. 114 can never be negative.
The output current is always unipolar. The quiescent dc output current level changes with the digital word which makes accoupling necessary.
CURRENT TO VOLTAGE CONVERSION
Voltage output of a larger magnitude are obtainable with the circuit of fig. 16 which uses an external operational amplifier as a current to voltage
converter. This configuration automatically keeps
the output of the DACOBOB ground potential and
the operational amplifier can generate a positive
voltage limited only by its positive supply Voltage.
Frequency response and setting time are primarily determined by the characteristics of the operational amplifier. In addition, the operational amplifier
must be compensated for unity gain, and in some
cases over compensation may be desirable.
Note that this configuration results in a positive output voltage only, the magnitude of which is dependent on the digital input. The LM301 can be used
in a feedforwerd mode resulting in a full scale setting time on the order of 2.0 f's.

voltage is developed with respect to the negative
voltage and appears as a common-mode signal to
the reference amplifier in the D-to-A converter. This
allows use of its amplifier as a classic current-tovoltage converter with the non-inverting input
grounded.
Since ± 15V and + 5.0V are normally available in
a combination digital-to-analog system, only the
-5.0 V need be developed. A resistor divider is
sufficiently accurate since the allowable range on
pin 5 is from - 2.0 to - B.O volts. The 5.0 kilohm
pulldown resistor on the amplifier output is necessary for fast negative transitions.
Full scale output may be increasing Ro and raising
the + 15V supply voltage to 35 V maximum. The
resistor divider should be altered to comply with
the maximum limit of 40 volts across the LM723
Co may be decreased to maintain the same RoCo product if maximum speed is desired.

PROGRAMMABLE POWER SUPPLY
The circuit of figure 17 can be used as a digitally
programmed power supply by the addition of
thumb-wheel switches and a BCD-to-binary converter. The output voltage can be scaled in several ways, including 0 to + 25.5 volts in 0.1 - volt
increments, ±10 mV.

PANEL METER READOUT
The DACOBOB can be used to read out the status
of BCD or binary registers or counters a digital control system. The current output can be used to drive directly an analog panel meter. External meter
shunts may be necessary if a meter of less than
20 mA full scale is used. Full scale calibration can
be done by adjusting R14 or Vref (see fig. 1S).

COMBINED OUTPUT AMPLIFIER AND VOLTAGE REFERENCE

CHARACTER GENERATOR

For many of its applications the DACOBOB requires a reference voltage and an operational amplifier. Normally the operational amplifier is used as
a current to voltage converter and its output need
only go positive. With the popular LM723 voltage
regulator both of these functions are provided in
a single package with the added bonus of up to 150
mA output current. See Figure 17. The reference

In a character generation system fig. 19 one
DACOSOB circuit uses a fixed reference voltage and
its digital input defines the starting point for a stroke. The second converter circuit has a ramp input
for the reference and its digital input defines the
slope of the stroke. Note that this approach does
not result in a 16-bit D-to-A converter (see Accuracy Section).

9/11

41

DAC0808-0807-0806
TWO-DIGIT BCD CONVERSION
Two 8-bit, D-to-A converters can be used to build
a two digit BCD D-to-A or A-to-D converter (fig. 21).
If both outputs feed the virtual ground of an operational amplifier, 10:1 current scaling can be achieved with a resistive current divider. If current output is desired, the units may be operated at full
scale current levels of 4.0 mA and 0.4 mA with the
outputs connected to sum the currents. The error
of the D-to-A converter handling the least significant bits will be scaled down by a factor of ten and
thus an DAC0806 may be used for the least significant word.

FIGURE 15. Programmable Gain Amplifier or Digital
Attenuator Circuit

Vsense
RS
R 14

VREF

-When VS=O. 1)4=2.0mA
Vo= (Vre! + Vs IAlR
R14 RS
0

14

FIGURE 16.
+5V
13

DAC0808-9

m

r-o--C:J----Q VREF= 1OV
A2
A3
A4

A2
A8)
Al
Vo=10V ( 2" + 4" + ... 256

A5
AS

A7

FIGURE 17. Combined output amplifier and voltage
reference circuit

FIGURE 18. Panel meter readout circuit

RO = 5K
+Vs
CO

+5V

25pF

13

I

14

6

VREF

4

I*J

~

l
-VEE

I*J
-15V

10/11

42

R14

a:

0--'-----'

DIGITAL WORD FROM COUNTER/REGISTER

DAC0808-0807-0806
FIGURE 19. Digital summing and character generation

+Vs

Vo = (101 + 102 ) RO

I

A

Vo= [V,ef1 [AI + V,ef2 [BI]R
R141
Rl4z
0

L
-VEE

o---C>=---I---f------o"-----l

FIGURE 20. Analog product of two digital words (High Speed Operation)

Vo=

+V.

t-=-'<0-'<='--O

I

~101

RO= V,ef [AI RO
R141

VREF
Vo

102=[BI IVol
R142

=~ [RO( V,ef
R142

) [AJ ]

R141

A

L
-VEE

Since Ro = R142 and K = V,ef

__--,

o---C>-'---+---t=======~::~==~

R141
DAC0808-/2

102 = K [A] IB]

IK can be an analog variable

FIGURE 21. Two-digit BCD conversion

(*) MOST SIGNIFICANT BCD WORD
(**) LEAST SIGNIFICANT BCD WORD

11111

43

- - - - - - - - - - .. _._------_.- .._--

ESM1600B

QUAD COMPARATOR INTERFACE CIRCUIT
• MINIMUM HYSTERESIS VOLTAGE AT EACH
INPUT: 0.3 V
• OUTPUT CURRENT: 15 mA
• LARGE SUPPLY VOLTAGE RANGE: + 10 V to
+ 35 V
• INTERNAL THERMAL PROTECTION
• INPUT AND OUTPUT CLAMPING PROTECTION DIODES.

The ESM1600B can operate in a wide supply voltage range (standard operational amplifier ± 15 V
supply or single + 12 V or + 24 V supplies used in
industrial electronic sets).
Moreover, internal thermal protection circuitry cuts
out the output current of the four comparators when
power dissipation becomes excessive.

DESCRIPTION

DIP-14/2

(PlastiC)

The ESM1600B is a quadruple comparator intented
to provide an interface between signal processing
and transmitting lines in very noisy industrial surroundings.
Output of each comparator, used as line driver, supplies a constant current (PNP output stage) and is
specially well protected against powerful overvoltages. The open collector output circuit allows the
connection of several comparators to a single transmitting line.

S016J

The ESM1600B can operate as receiver on a line
transmitting noisy high-voltage signals. Hysteresis
effect, internally implemented on inputs of each
comparator provides an excellent noise immunity.
In addition, each input is also protected against
overvoltages.

ORDER CODES: ESM1600B (DIP-14)
ESM1600BFP (S016J)

PIN CONNECTIONS (top view)
DIP-14

9
10
4

11
12

6

13
14

1 -Inverting input 1
2 - Non-inverting input 1
3 -Output 1
4 - Non-inverting input 2
5 -Inverting input 2
6-0utput2
7-GND
a -Output 3
9 -Inverting input 3
10 - Non-inverting input 3
11-0utput4
12 - Non-inverting input 4

13 -Inverting input 4
14-Vee

September 1988

S016J

3
4

6

8

1 -Inverting input 1
2 -Non-inverting input 1
3 -Output 1
4 - Non-inverting input 2
5 -Inverting input 2
6 -Output 2
7-GND
a-N.C.
9-N.C.
10 -Output 3
11 -Inverting input 3
12 -Non·inverting input 3
13 ·Output4
14 - Non-inverting input 4
15 -Inverting input 4
16-Vee

1/7

45

ESM1600B
ABSOLUTE MAXIMUM RATINGS

Sy':;;b;;!r- - --- - - ----Par;':;;ete-r-_.
- -- - I - ----- --- -- - --- ---- Vcc~uPPIY\l·0.75

2

iii
I::J

~K

a.
~

~-+-

o
25

o

~


Q.

----

"""---- r--

~

75

50

S
o

0.25 -

o
o

100

10

5

15

TEMPERATURE lOCI

OUTPUT CURRENT ImAI

Figure 3: Output saturation voltage

Figure 4: Short circuit carrent
20

I
IO=10mA

~

0_9 1-----.

---


z

~


0

~

tIC
IX:

16

-

14

-

1--

~-

1---

--

:>

o

u

----

"'-~

IX:

50

-

U

.:-IX:
0

f"'--.---

25

TEMPERATURE IUCI

48

-

!::
-

--- - -

0.6

0.5
-25

4/7

r--- -

::J
U

VI

I-

-

I-

0_8

0

::J
I-

18 1-- --- t - - - f-

.§

75

100

:I:

CIl

12 -----

10
-25

o

±L

--

---

25

50

TEMPERATURE COe)

75

100

ESM1600B
TYPICAL APPLICATIONS
Figure 5 : Conversion of DTL, TTL, MOS Signals on a Transmitting Line.

I

A +15

v

90 k!l

0------1 & I-----+-------i -

1/4

ESM1600B

> ____

.....------1+
10 k\l

-15 V

j

30 \.'

190 kl!

.------i -

1 14

ESM 1600B

>------,

O-------j & r----+------t---+--~+

- 1/4
ESMl600B

&

r--------·---'

r----+---I +
10 kn

Figure 6 : Reception of Highly Noisy Signals.
----

-

-

- - - --

- - -

- - ---. - - -

-

.-

-

24V

120 kll

.....----1- 1/4
100 kll
ESM1600B ">----0
line _ _ _..-----c_=f----t---~

+

33 kH

60 kl!

.------------- --~--- ID'/
SGS-THOMSON
'J,

5/7

~D©IliI@rn~rni:1i'IliI@Ii!D©®

49

ESM1600B
TEST CIRCUIT
Figure 7.

VI

V"
I

t33V~

t

33 V

--r\7\:

12V~~

OV~

Figure 9.
-----------------------

FigureS.

.33V------<

'av------t+

.2V------<

.2V-----t
ISC

Figure 10.

.33 V
.33 V
.2V-----'
.2V-----'

6/7

50

ESM1600B
Figure 11.

Figure 12.

133 V o-~~--+-~-....,

+

14

~

1/.
ESM1600B

E,M1600B

l200vl

1

2

v

~"1

o---t--+----+-+--+~

800 !!

Figure 13 : Response Time.
50

40

---

~

~ 30

0

-

>-

2~

"C

---

C---_

0

----

-

-

--~---

--

--

-

-V+?tr>

-~

-

-------

--

0

::>
ui

I

Tamtl

------ f--

::>

>-

--~-

20

> 10 "-

t_

-

w

"<~

!

- - - VO-f.---- -

s:;V.[
~ ~'" . ~~
I

10 kH

J

"

-

-

----

"<~

4

>
>-

3

-----

2

--

-

f---

VI

..

_-

-----

-

-

-

0

--- 1---

-

-

--

::>

"-

;;;

1

-1

o

2

3

o

4

3

4

5

6

TIME (p'l

7/7

51

ESM16028
QUAD COMPARATOR INTERFACE CIRCUIT
• MINIMUM HYSTERESIS VOLTAGE AT EACH
INPUT: 0.3 V
• OUTPUT CURRENT: 15 mA
• LARGE SUPPLY VOLTAGE RANGE: + 10 V
TO + 35 V
• INTERNAL THERMAL PROTECTION
• INPUT AND OUTPUT CLAMPING PROTECTION DIODES

The ESM1602B can operate in a wide supply voltage range (standard operational amplifier _t 15 V
supply or single + 12 V or + 24 V supplies used in
industrial electronic sets).
Moreover, internal thermal protection circuitry cuts
out the output current of the four comparators when
power dissipation becomes excessive.

DESCRIPTION
DIP-14/2

The ESM1602B is a quadruple comparator intended to provide an interface between signal processing and transmitting lines in very noisy industrial
surroundings.

(Plastic)

Output of each comparator, used as line driver, is
well protected against powerful overvoltages. The
output is a common emitter stage including complementary transistors. This arrangement ensures that
no simultaneous conduction of high and low stages
can occur in the presence of noise signals. Shortcircuit currents toward Vcc and ground are limited
to the same value.
The ESM1602B can operate as receiver on a line
transmitting noisy high-voltage signals. It has the
same input stage as ESM1600B. Hysteresis effect,
intemally implemented on inputs of each comparator provides an excellent noise immunity. In addition
each input is also protected against overvoltages.

SO-16J

ORDER CODES: ESM1602B (DIP-14)
ESM1602BFP (SO-16J)
~

----

PIN CONNECTION (top view)
DIP-14

SO-16J
1 - Inverting Input 1

1 - Inverting input 1

2 - Non-Inverting input 1

2 - Non-inverting Input 1

3 - Output 1

·16

4 - Non-Inverting Input 2
15

5 - Inverting Input 2
6 - Output 2
7 -GND

'0
4

6

"
'2
'3
'4

8 - Output 3
9 - Inverting input 3

3

'4

4

13

5

12

6

11

10 - Non-inverting Input 3
11 - Output 4
12 - Non-Inverting input 4

10

13 - Inverting input 4

==-____ _

8

L__________
September 1988

9

3 - Output 1

4 - Non-Inverting Input 2

5 - Inverting input 2
6 - Output 2
7-GND
8 - N C_
9 - N.C.
10 - Output 3

11 - Inverting input 3
12 - Non-inverting input 3
13 - Output 4
14 - Non inverting input 4

15 - inverting input 4
16 - Vee

1/8

53

ESM1602B
ABSOLUTE MAXIMUM RATINGS
~---

Symbol

Parameter
-------

..-

-

Unit

Vee

Supply Voltage

45

V

VID

Differential Input Voltage

45

V

V,

Input Voltage

10lmax)

- 0.7 to + 45
r--------------Internally Limited

Output Current

Ptot

Power Dissipation

Top

Operating Ambient Temperature Range

T stg

Storage Temperature Range

----------~

..

- -

~

- 25 to + 85
- 40 to + 150

VCC
1000

II

2500

II

BOO
(j

500

H

25
H

Common supply

and thermal
protection
Non inverting
Input

Inverting

input

70

kll

600
H

28
II

GND
1/4 ESM1602B

54

V
mA

_lntElrn~III'Li mitEl~_l_-",,_

- - I--

SCHEMATIC DIAGRAM

2/8

-,----~

Value
--

I

'C
'C

ESM1602B
ELECTRICAL CHARACTERISTICS Vee = + 35 V, - 25 'C <; Tamb <; + 85 'C
(unless otherwise specified)
Typ.

Min.

'.'

Input Voltage Range - Note 1
Non-inverting Input
Inverting Input

o

!

o~~:u~ ;a;~r;~o~~~ag; (highl~~~00

,

= - 10

i

Supply Current
RL = = for the 4 Comparators
.

--t. _ 11 " 10

.Qut~ut Slew:rat(ljF1..,-=2~~l,T Ei"'."...."" ':+:"~'C)-=--_-=--+"j _I
Input protecti:e Diode Forward Voltage (I = 20 mA,
T amb = + 25 C)

-of'Pul~es-ag;;m~t which CirCUit Output IS

(Tamb=+2~O~)

Note 5 _ .

i

"_

I

1

.

I

mA

:

V

1

I

1]'1-.'
V/~LS

I

9
11

i

12

1

I
I

1

--j 13,14
I

1
1

vII

mJ

!

I

~

-

I

~LA

__..I

I

r- -

1

8

I

15

-,

rI

Note 4

Pulsed Curr;';-Appi;d to Protecbve-O;,;(put o;ode;;--Notes:

mV

I
1
,
m
A
I
4
I
6

I

RL Common for the Comparators

1.6

I

I
I

mA)~-~-~1-~'~~--+--v--~·"

Output Saturation Voltage (low level) . (10 = + 10 mAl

1-

I

U

1

--1- v-T--=-1

33
I
33.
500 I
5

I

Short·circuit Output Current

Max.

-~--

150

Input Bias Current· Note 3

Protected
(T amb = + 25 ec)

I

I

2

Input Control Voltage (? V < V eM < 33 V) - Note 2

Energy

~ lu.:-r;~~1

Value

Parameter

20
-!

I

I

-

1

I
I

I

1"-';;:-115-1

1.---=-_L_O'4 __ l.._-=_L

I

___ I

1. When negative input is biased between a and 2 volts output IS always low.
2. Comparator hysteresis voltage on positive Input on the one hand and negative input on the other hand equals sum of Input control
voltages Ve1 + VC2 or VCJ + VC4.
3. Input current flows out of the circuit owing to PNP input stage. ThiS current is constant and independent of output level. So no load
change IS transmitted to Inputs.
4. By definition, a circuit is immunized against powerful signals when no durable charactenstic change occurs after the application of
these signals and when the circuit has not been destroyed
In industrial surroundings, parasitic signals contain usually high voltage (over 200 V) AC harmonics having variable impedance of

500nto10Kn
The power dissipation of these signals is divided between clamping diodes and the Vee. Simulation IS used to determine the maxImum energy level. The Injected current value cannot in any case exceed 3 A.
5. Output protective diodes are individually by means of positive and negative discharge voltages of a capacitor. The negative discharge control occurs through a single diode. DUring positive discharge. due to the properties of integration, a grounded collector
PNP transistor appears in parallel with the clamping diode connected to Vee. A part of the current flows through thiS transistor, VeE
being greater than Vee. If T IS the total discharge duration, energy dissipated in the cirCUit is

Comparator output

W=

J·T [i1

Vd

+ i2(Vcc + Vd)

1dt

o

For a certain injected current, the lower the current b, that is to say the lower the PNP current gain the smaller the energy is diSSipated In
the cirCUIt. Topology and technological processes have been chosen to shorten this current gain.
_ _ _ _ _ _ _ _. _ ._ _ _ _ _ _ _ ._ _ _ ._ _ . _ _ _ _ _ _ _ _ _ _ ._ _ _ _ _ _ _ _ _ ......J

3/8

55

ESM1602B
Rg 1 -

INPUT BIAS CURRENT.

Fig. 2 -

5

--

"~

fZ

0>

3

0.75

z

:::l

tJ

rn
<{

iii

~
w

1
w

-i-j

125

4

a:
a:

OUTPUT SATURATION VOLTAGE.

2

f:::l

~

11.

~

o
-25

0

>=

<{

a:

~

o

:::l
f-

0.50

<{

rn

"

25

f-

:J

""""'-- I 50

--

I~

11.

f-

:J
0

0.25

0

1()()

5

0

TEMPERATURE lOCI

Fig. 3-

15

10

OUTPUT CURRENT (mA)

Fig. 4-

OUTPUT SATURATION VOLTAGE

SHORT CIRCUIT CURRENT.

30 , . - - - _._--

1.2
IO=10mA

~

<

w

"
z

a;

a:
a:

O.B

tJ

>=

to

<{

a:
f-

tJ

u.6

a:

u,:.

<{

J:

0

25

50

TEMPERATURE (OC)

56

_.-

,

~ ....
--

It>

--

0

UI

0.4

0.2
-25

4/8

::::---...

a:

11.

0

I
tow level

:::l

Ul
f:J
f:::l

20

:J

0

:J

-~

~el

f-

f-

0

>

25

E

<{

75

100

.. - - . -

10

5
-25

0

25

50

TEMPERATURE ("C)

75

100

ESM16028
TYPICAL APPLICATIONS
Figure 5 : Conversion of DTL, TTL, MOS Signals on a Transmitting Line.

I

f

JO V

15 V

90 kH

Line

uno

- 1/4
ESM1602B>----

ES~~:mB>---

...------1+

\----t---i

+

10 kl1

15 V

Figure 6 : Reception of Highly Noisy Signals.

·21 V

120 kn
1/4

ESMl602B .r----u

100 kll

Line

I

- -....-----{:=:J----t---i +
33 k!!

60 kll

I
I

L

-----------

----- ------ LW ~~~~~gr::~~~~

-- ----- ---.-.-..----

5/8

57

ESM16028
Figure 7: Free-running Square Wave Oscillator.

~

30

v

1 Mil
30 V

68 kll
1/.
ESM1602B>---+----- Va
-I---~+
1 nF
L -_ _ _ _ _ _ _ _ _ _ _

68 kll

--""----"""----- - - - - - - - - - - - - - - - - -

TEST CIRCUITS
Figure 8.

vIt

133V~

Ov-~

'33V~

'2V~
YI~

6/8

58

+2.5 to -< 32.5 V

t

ESM16028
Figure 9.

\8

Figure 10.

v ------1+
. HV

.2 v

'sc

I

I

"2V------'

I
"

Figure 11.

~-~~"--~"~--~-- ~~

Figure 12.

- I
I
I

\ 33

+33V-----I

I

v

I
I

10

·2V - - - - - - '

I
~---~--~~---

---

I
"--""~-

"~------""-

Figure 13.

Figure 14.
--"-~--~-

Vee
.33

v

f

I
I

I

T

-~"-"-----"l

I IIT

vee
800

I
I

n

+2 V

I

I

14 13 12 11 10 Y 8

I

ESM1602B

I

.2 V

2

3

II
1

4

5

6

7

"z

8

ESM16028

I

I I 1 I
I I

ICC

"
"----------

14 13 12 11 10 '

8

oon

~~

- - --~---"""-"""-

-

L'
I

J

33 V

'"

7/8

59

ESM1602B
Figure 15.

1-'

--

_.-

-_._-_._--_._--

~
±2oovl
40nF.

- - - - - - _ _._--._._----- ------.
..

-------

Figure 16: Response Time.
50

2:
w

"

I

40 1--30

<{

r-----

--.-

~

~--

I-

0
>

20

I-

lD

:>

r

Tamb- t25°C

10kH

---+--H--~ ~VI~

Va
- --

--

\

--c~-- ~

- - - ~----, ~-

---f- -

---

f--

~

.lV

--'

1

Q.

I-

:>
0

0

ui

"!:::;

-+----j._-. -

---

-

._--

I- --

-

V,

<{

4

-

-'-'--

0

>

3 __

-

I-

:>

-

+

--- r- - -

-----

f--l

Q.

~

1L-__
-1
o

L-_L-~L-~L-~

2

__

o

4
TIME (p.s)

8/8

60

L...
,/
•J,

SCS-11-IOMSON

UliJllIOWJ@rn~rn[m~@lI!lllO@

~.- . - - - - . - - - - - - - - - - -

GS-0050
- - - - -

--~-~-----

~---~--~--~

----

~~

--~---

0.5 A SWITCH MODE BIPOLAR STEPPER MOTOR
DRIVER MODULE
•
•
•
•
•
•
•
•

NO EXTERNAL COMPONENT REQUIRED
INPUTS TTL/CMOS COMPATIBLE
LOGIC INHIBIT/ENABLE
CHOPPER REGULATION OF MOTOR BIPOLAR CURRENT
PROGRAMMABLE MOTOR CURRENT
(0.5 A max) (by steps or continuously)
WIDE VOLTAGE RANGE (10-46 V)
FULL-STEP, HALF-STEP AND QUARTERSTEP OPERATIONS
OVERTEMPERATURE PROTECTION

DESCRIPTION

ORDER CODE· GS-D050

The GS-D050 is a driver for bipolar stepper motors
that directly interfaces a microprocessor and two
phase permanent magnet motors.
The motor current is controlled in a chopping mode
up to 0.5 A. The small outline makes the GS-D050
ideal when space is a premium.

i
.
V::'= :
-_ -_

.s,t ~~~2:~~:--=~'~~ ------ABSOLUTE MAXIMUM RATINGS

L09i~IIlpU~~01_ta_ge-

:_V_' _ _

I-_~ _ _ ~~k_OU1[J~ Current_
Vref
T sfg

-=- -~

u~;;

--J=-___ 162_-_-

:

-~_-~
l

- - - - ~----' ~---1
- 40 to + 105
I cC
20 to:c85___

Reference Input Voltage
Storage Temperature Range

I

-T-c_-op-~O--p~-r-a;~-ng-C~-se-;--~m-_p~raw-re-R-il-ng-e- - - -=--~-1

-_ _

~

~cc

I

THERMAL DATA
---

~-~~

Rth

(c~a)

-----

October 1988

-~

-

---~

-~

---

Case-ambient Thermal Resistance
--

-

---

-

-

-

--

----

1/18

61

GS-0050
MECHANICAL DATA (dimension in mm)

51

MOTHER BOARD LAYOUT (top view)
~---------'--"-'-'-'-

- - - - - -

2/18
----------

62

J

69

~ ~

135

j

GS-D050
EQUIVALENT BLOCK DIAGRAM OF G5-D050

Vss
10

B

111
9

101

BRIDGE 1
11,

8

1--+-----0

PH 1

A

11
Vref
1,-12

GND

c
BRIDGE 1

I 12

6
D

3/18

63

GS-D050
PIN FUNCTIONS
Pin

Function

....

6 - 102

7 - PH2
~=!'~]

Input pin for current level and operating mode selection (see 1"

description).

Input pin for current level and operating mode selection (see 1"

description).

_--_._-

Phase 2 Logic Input

__

~~~se~Logic...'r1p.LJt _

._______________ . ___ _

. ________ _

__ 9-=-10 , __ ~rl£.u!'p.irl.!~ cur!~t level ~e~~~ lH~.~_~,,_d!lsc:r.pt~IlL _ _ _ ______ _ __________ _
10 - 1"

Input pin used, together with 101 , to select the current level according to the following table.
111/1,2 101/102
Phase Current

o
o
1
11 - Vref

o
1

o

Iph = 100 % Isel
Iph= 60%l sel
Iph = 19% Isel
No Current

Reference Input Voltage for the Chopper Comparators. The voltage applied to this pin settles the
phase current to the desired value. A 5 V ref sets a 0.5 A phase current when full-step drive is
selected.

1--'---

12 - GND

Ground Connection. Motor and logic supply voltage must be referenced, as well as the logic

r---______+-s~ig~n_a_ls~,__t_o_th_i_s~p_in_.___________
13 - V 5

Motor Unregulated Supply Voltage.
Maximum Applicable Voltage is 46 V.

f-- ----- .. - -.. --.---... ---- ... --.--------_.--._--- ------- ..

I-..!~~

__

~~~ ___

~~ge Output_A:.2~i~fJ.lJ.t....tl..~s~..s..~me phase ~fthEl_~~ivinll.sigllal

F'f:'.1._

Bridge Output B. This output has a ph------...:

BA

CD

AB

A-

10/18
------------

70

l:.'9,/ SCS-THOMSON - - - - -.. - - - - - • II

illiJD©I!I@rn~rn©~I!I@IIlD©il!

GS-D050
TWO PHASE ON OR NORMAL DRIVE
Two windings are energized at any given time according to the sequence (FWD direction).
AB & CD; CD & BA; BA & DC; DC & AB

In this case
level set.

101, 111

signals are used just for current

Fig. 9 and 10 show the timing or various signals.

Figure 9 : Two Phase on -FWD Direction.

L
101 . I II. [ 12. 102

0

-L

'''''
I

'''',

.:::

~:~

---------~i-----J.--------Jl

I

J. __

__-_-_-_.1..:

I
CD & SA

DC &. SA

AS

a. DC

I
AB &CD

11/18

71

GS-D050

---------------

Figure 10: Two Phase on -REV Direction_

-----------1
I

L
I

I

--L
I

AB & CD

BA & DC

SA &(0

AB & CD

A.

'r- 99 '> 3

I

L_MOTOR
- - _J

J'

- - - - - - - - - - - - -

18/18

78

SWITCH MODE BIPOLAR STEPPER MOTOR
DRIVER MODULE

i

• NO EXTERNAL COMPONENT REQUIRED
• NORMAL, WAVE, HALF STEP DRIVE CAPABILITY
• INPUTS TTUCMOS COMPATIBLE
• CHOPPER REGULATION OF MOTOR CURRENT
• PROGRAMMABLE MOTOR CURRENT (2 A
max)
• WIDE VOLTAGE RANGE (10-46 V)
• SELECTABLE SLOW/FAST CURRENT DECAY
• SYNCHRONIZATION FOR MULTIPLE APPLICATION
• REMOTE INHIBIT/ENABLE
• HOME POSITION INDICATOR
• OVERTEMPERATURE PROTECTION

I
I

DESCRIPTION
The GS-D200 is a complete controller and driver for
bipolar stepper motors that directly interfaces a
microprocessor and two phase permanent magnet
motors.

ORDER CODE :
GS-D200

j

The motor current is controlled in a chopping mode
up to 2 A. High flexibility in use is provided by GSD200 that, furthermore, reduces the burden on the
microprocessor and simplifies the software development in a complete microprocessor controlled
stepper motor system.

ABSOLUTE MAXIMUM RATINGS
Symbol
Supply Voltage (pin 18)

Vss

Logic Supply Voltage (pin 12)

10

Value

Parameter

Vs

Peak Output Current

T stg

Storage Temperature Range

T cop

Operating Case Temperature Range

Recommended maximum operating Input voltage

IS

Unit

48

V

7

V

2

A

- 40 to + 105

°C

- 20 to + 85

°C

46 V.

THERMAL DATA
Case-ambient Thermal Resistance
September 1988

Max

5.0

1/18

79

GS-0200
CONNECTION DIAGRAM (top view)

J

1

GNDI

SYNC

~2

RESET

~3

HALF/FULL

,

HOME

5

::~

V,,(46V max)

A

~6

-,

16

8

l'

[)

10 SET

9

13

GND2

CONTROL

10

STEP ClK
CWJl,;L.:W

OSC

-

1~

B
C

11

ENABLE
Vss

~12

(7V max)
5·9444

TYPICAL APPLICATION

RESET
ENABLE
STEP ClK

MPU

HALF/FULL
Cw/ccw
HO";'-E
CO~'-ROl

'oSET

Vss=5V

9

12

VS~46V

18
17

3

A

r-----.,
1

I

---t-

cr:

6

16

4

GS - 0200
15

7

l- I

B

cr:O

C

Ocr:
o..W
-0..
roo..
W

:'5~

5
10

14

l-

D

(/)
I

5-94105

OSC

80

I
I

L _____ ..J

8

2/18

I

0 I

11

SYNC

GNDl GND2

GS-D200
EQUIVALENT BLOCK DIAGRAM OF GS-D200
,~~~------~--

-~~---~-

---

--~

<{

ro

I

I

u

u

I

I

I

~1 ~ -I~

L o

Z

l'J

L

(f)

U)

cr

)-

w

-·-·1~

->
'f

3/18

81

GS-0200
PIN FUNCTIONS
I,

Function

Pin
1 - GNDl

i

Common Ground for Low Current Path

2 - SYNC

Output of the Module Chopper Oscillator.
Several GS-D200 can be synchronized by connecting together all SYNC pins (see later). An
if--~==~+ external chopper clock source. if used, must be injected at this pin. __________ _

~

3 - RESET

I

i

4 - HALF/Fl..JLL Ha-lf-/F-uIiStep Select Inpu-tWhe-n high or not connected, it selects half step operation, when
low it selects full step operation.

-.------.------------------f-

5 - HOME

I

Reset Asynchronous Input. An active low pulse on this input restores the module to the HOME
position (ABCD ~ 0101).

6 - STEPCLK

Output that indicates when the module is in its initial state (active low. ABCD ~ 01 01 ~ state 1).
This signal should be ANDed with the output of a mechanical home position sensor of the
motor.
A Pulse on this input moves the motor by one step. The step occurs on the rising edge of this

~ _____ ~~ignal_._____________ _____
_.___
_
_____
_ _______________ _
I 7 - CW/CCW Clockwise/Counterclockwise Direction Control Input. When high or not connected clockwise
,
rotation is selected. Physical direction of motor rotation depends also on connection of windings.
L
Direction can be changed at any time being this signal synchronized inside the module.
I
--T-he-cho-p-pe-r-fr-equency of the m-od-u-l-e-isi;;t~rn~liYfixed--a~ 17 KHz. This fr,~que~c-;-c-;nb~-increased by connecting a resistor between this Pin and Vss or decreased by connecting a
I
capacitor between this pin and GND1. When multi-GS-D200 configurations must be
synchronized, this pin is connected to ground on all but one module.

'8 - osC-

~-Io'SET- Th;Mot~ha;--C~rre~tj; Set -;;;t1A. This current can be decreasedby;;~~~cting~-;;si~

i

between this pin and GND1, or increased by connecting a 10 KIl min resistor between this pin
and Vss.
___________ . ______________________________ _
Control input that defines the motor current decay inherent to chop mode control. When low, a

L _____+-~_~_:_odre~~rr~~tObtained
110 - CONTROL

; when high, or not conn::ted,_s_lo_wcurrent decay is impose:_th_e__

11 - ENABLE
Module Enable Input. When low the module is inhibited. When high or not connected the
\
module is active.
1-------+-------------_._--_._-----_._5 V Supply Input. Maximum Voltage must not exceed 7 V.
! 12- Vss
--

--

1__ 12::GN [);2-- Co_m_m_o"-~()U n_d_forH_I_g_h_Cu rrent
--

,

14 - D

~~-c=16 - B

4/18

82

---

-----

-----

- - - - - -------- - - - - - -

Pa_th_

Phase D Output
?_h_a_s_eC_-_O_ut-p_-ut-_Phase B Output

--

---

---

17 - A

Phase A Output

18 - Vs

Module Supply Voltage. Maximum voltage must not exceed 46 V.

GS·D200
ELECTRICAL CHARACTERISTICS (T amb

r-'

=

25 'C unless otherwise specifed)

_S_Y_~~s_bO_I--+ SU~_I_y_V_O_I~a_:_~_a_m_e-_t-e=r===-_-_--j-p-in-1s_T_e_s_t_C_"Od;';"",

~i~Py£JM::T U~;':

Supply V()lt.a~ ___________ Pin 12

Vss
Is
f---- Iss

_I

Quiescent Supply Current

~,~t;,~,

Input Voltage

f--------

--

Input Current

Ii

-P~n

6, 7,

5, 4, 6,

1~sS

=

7:1-0

--r--

=

L~w +

;V~

5 25

Enable Input Current

0s
Vss

Pin 11

.v.. j .
V

mA-

10

______ _

0S
Vss

V
V

j

I

mA
-;;:;,;;. -

V, = High +
Low
High

;-1

·---·0(3
j

2_0

f-----+----------------+------------~-t-----

Vsat

1

60

d

5 V
V,

Pin 11

Enable Input Votlage

-------

5

High I 2.0

_

-----+- ----------------

475:

Pin 12 All Input High -- - - -- -

--- - - - - - - - - - -

Vi

__

~i~t ~80----~s=:;:-- 1- - 115 20

Quiescent Supply Current

--

Vee = L I
Vee=H'

----~

0.6
10

-

I

mA
flA
------

V
V

Home Output Voltage

Pin 5
Ihome = 5 mA

Source Saturat. Voltage

Pin 14, 15_,1__6_,_1_7_ _ _I--'o_=_1_A-j_ _- t_ _-+_1._S-j__V----l

0.4

LowiI
High

f--_V--,s,,-at_-t_S_ource Saturat. VO._lt_a_g~_e_ _ _-j_P_in_1_4_,_1_5_,_1_6_,_17____I_o_=_1_A-t_____+ ___+-_1_.S__ ~

Ie

Chopper Freq.

f elk

Stepclk Width

_____ --1__-+_17
Pin 6 See Fig. a

Set Up Tinle___________
Hold
Time
---------tRclk

~--.

KHz

0.5

I ~ee Fig~_~____

,llS

10+ __ +__~

a - - - - - - - - - f--. 1.0 - I
---l e e.....Fig.
-- ..- -

___

0___

flS

~

Reset Width
See Fig. b
1.0
fls
Reset to Clock Set Up Time - - S e e - F i ; b - - - - - · t 1 - o E - t - - - f l S __ ,

w __~ _ _ _ _ _ _ _ _

~

__ . _ _ _ _ _ _

_ __

Figure a.
- - - - - ----------

STE.P ClK

CW/CCW

~-9t.l.

7

5/18

83

GS-D200
Figure b.

I

STEP elK

J

RESET

,

I

J

MODULE OPERATION
The GS-D200 is a complete bipolar stepper motor
driver that incorporates all the small signal and power functions to directly interface a microprocessor
and a two phase permanent magnet motor (see the
typical application). Very few information must be
delivered by the microprocessor to the module:
_ step clock
_ direction (clockwise or counterclockwise)
_ mode (half or full step)
_ reset and enable
_ current decay (slow or fast)
Based on this information, the module generates the
proper four phases sequence to directly drive a two
phase bipolar motor. Therefore the GS-D200 greatly simplifies the task of the microprocessor and of
the system programmer.
No external component is needed to operate the
GS-D200. However, to add flexibility in use, some
internally set functions can be modified externally,
like the maximum current flowing through the motor
windings and the switching frequency of the current
chopper, by addition of few inexpensive passive
components (resistor and capacitor).

6/18

84

If any of logic input is left open, the rnodule forces
them to high level.
The GS-D200 is housed in a metal case that provides heatsink and shielding against radiated EMI.
The thermal resistance case to arnbient is about
5 °C/W. This means that for each watt of internal power dissipation the case temperature is + 5 °C above
ambient tern perature. It is recommended to keep
the case temperature below 85°C in operating
conditions.
According to ambient temperature and I or to power
dissipation, an additional heatsink may be required:
the mounting of optional heatsink is made easy by
the four holes provided on the top of the metal case.
The GS-D200 incorporates a thermal protection that
switches off the power stages when the junction
temperature of active components reaches 150 °C.
To keep the power dissipation to a minimum, two level supply voltages must be applied to the module:
5 V for logic functions and Vs from 10 to 46 V for power section.

GS-0200

----_._------------

A. BIPOLAR STEPPER MOTOR BASICS
Simplified to the bare essentials, a bipolar permanent magnet motor consists of a rotating-permanent
magnet surrounded by stator poles carrying the windings (fig. 1).

tating the voltage applied to the windings in sequence.
For a motor of this type there are three possible drive
sequences.

Bidirectional drive current is imposed on windings
A-B and C-D and the motor is stepped by commu-

Figure 1 : Simplified Bipolar Two Phase Motor.
A

D _--1-_--1//

CID

~----+--c

-~""
8

A. 1. ONE-PHASE-ON OR WAVE DRIVE

Only one winding is energized at any given time according to the sequence:
AB - CD - BA - DC

(BA means that the current is flowing from B to A).
Fig. 2 shows the sequence for a clockwise rotation
and the corresponding rotor position.

Figure 2 : One-phase-on (wave mode) drive.

I
I

8-

o~c
o~

eQc
.y-

8.

BO

7/18

85

GS-D200
A. 2. TWO-PHASE-ON OR NORMAL DRIVE
This mode gives the highest torque since two windings are energized at any given time according to
the sequence (for clockwise rotation).
AB & CD ; CD & BA ; BA & DC ; DC & AB

Fig. 3 shows the sequence and the corresponding
position of the rotor.

Figure 3: Two-phase-on (normal mode) drive.
At

A-

D_~C

D_~

W

~~+

A-

Ct

A+

~-

'V

0

C

B-

D~~C
B-

A. 3. HALF STEP DRIVE
This sequence halves the effective step angle of the
motor but gives a less regular torque being one winding or two windings alternatively energized. Eight
steps are required for a complete revolution of the
rotor.
The sequence is :
AB ; AB & CD ; CD ; CD & BA ; BA ; BA & DC ;
DC; DC &AB

as shown in fig. 4.
By the configurations of fig. 2, 3, 4 the motor would
have a step angle of 90 0 (or 45 0 in half step). Real
motors have multiple poles pairs to reduce the step
angle to a few degrees but the number of windings
(two) and the drive sequence are unchanged.

Figure 4 : Half Step Sequence.
A+

o~o
D"-VC

A-

A+

-~+

~C

~+
DQC

-~t

D~-C

B-

B-

BO

Bt

A-

A-

AO

At

O~O

D~C
B+

~_-

t~-

Bt

BO

D~

Dve

t~-

~-C
B -

5-5938

8/18

86

--l

GS-0200
B. PHASE SEQUENCE GENERATION INSIDE THE GS-0200
The GS-0200 contains a three bit counter plus
some combinational logic which generate suitable
phase sequences for half step, wave and normal full
step drive. This 3 bit counter generates a basic

eight-step Gray code master sequence as shown in
fig. 5. To select this sequence, that corresponds to
half step mode, the HALF/FULL input (pin 4) must
be kept high or left open.

Figure 5 : The Eight Step Master Sequence Corresponding to Half Step Mode.

CLOCK

A

B

c

o

ABCD" 0101

0001

1001

1000

1010

0010

0100

0110

HOME POSITION

OQ);I
I:
("
l",

o

8.
-:,-9449

The full step mode (normal and wave drive) are both
obtained from the eight step master sequence by
skipping alternate states. This is achieved by forcing
the step clock to bypass the first stage of the 3 bit
counter. The least significant bit of this counter is not
affected and therefore the generated sequence depends on the state of the counter when full step
mode is selected by forcing pin 4 (HALF/FULL) low.

If full step is selected when the counter is at any oddnumbered state, the two-phase-on (normal mode)
is implemented (see fig. 6).
On the contrary, if the full mode is selected when
the counter is at an even-numbered state, the onephase-on (wave drive) is implemented (see fig. 7).

9/18

87

GS-D200
Figure 6: Two-phase-on (normal mode) drive.

CLOCK

L
I

A8CD=0101

~~----II
I
1010

1001

HOME POSITION

0110

I

~~~~.J~'''~'.
~C'~C~'~

__ ~ ___ ____ _ __ .__.________ ._________.________ J

-------. ----.----------------.. -l

Figure 7 : One-phase-on (wave mode) drive.

!

ClOCK

H

____~----~I

L
L-__~--__

I
ABCD=OOOl

1000

0010

0100

o~, o~,o6, J~.-,
0\JVo-v' °VJo

'vSO

'oj_

eO

I
I

fl'.

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._ _ _ _

10/18

88

GS-D200
C. RESET, ENABLE AND HOME SIGNALS
The RESET is an asynchronous reset input which
restores the module to the home position (state 1 :
ABCD = 0101). Reset is active when low.

The ENABLE input is used to start up the module
after the system initialization. ENABLE is active
when high or open.

The HOME output signals this condition and it is intended to be ANDed with the output of a mechanical home position sensor.

D. MOTOR CURRENT REGULATION
the current decays until the next oscillator pulse arrives.

The two bipolar winding currents are controlled by
two internal choppers in a PWM mode to obtain
good speed and torque characteristics.

The decay time of the current can be selected by
the CONTROL input (pin 10). If the CONTROL input is kept high or open the decay is slow, as shown
in fig. 8, where the equivalent power stage of GSD200, the voltages on A and B are shown as well
as the current waveform on winding AB.

An internal oscillator supplies pulses at the chopper
frequency to both choppers.
When the outputs are enabled, the current through
the windings raises until a peak value set by loSET
and Rsense (see the equivalent block diagram) is reached. At this moment the outputs are disabled and

Figure 8 : Chopper Control with Slow Decay.

VA

','~'

1
V-c, Ptn18
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

Vs'

~I ----~r-~--------~r-~-----O

~~ L--',-,--

r-.- r-.-r-

(V,al'

Vsen".,)
'AB

I

I
I

I

I
I

I

I

I I

1 I

I

I

I

i

I

I

:

__L L

I

i

I

f--

I

I

I

I

.-l

j

~rI

I

_

I

I

I

I

I
I

+_
I

1 -.l~ -~

I

__ drive current (0,. 0,. ON)
recirculation current (0·" ON, 02, OFF. D,. ON)

11/18

89

GS-D200
When the CONTROL input is forced low, the decay is fast as shown in fig. 9.
Figure 9 : Chopper Control with Fast Oecay.
!-----~.~---~-.---

-- . ---.-------------- _ ..

--"1

v, - P,n 16
(Vd ,
VSPfls.)

1---

--

1--'-

---

lHHlli

vs. Vd

(v.. ~t

I

-

I

-

-

:

I

-- -

-

t

Vs~ns~)

'AB'

,

I

I

-

I

I

-

-

-- -

I

,

I

I

I

I

I

:

I

I

I
I

I

I

I
I

I

I

- - - drive current (Q,. Q,. ON)
.. recirculation current (Q,. Q2. OFF. D,. D2. ON)

The CONTROL input is provided on G8-0200 to allow maximum flexibility in application.
If the G8-0200 must drive a large motor that does
not store much energy in the windings, the chopper
frequency must be decreased: this is easily obtained by connecting an extemal capacitor between
08C pin and GN01.

In these conditions a fast decay (CONTROL LOW)
would impose a low average current and the torque
could be inadequate. By selecting CONTROL
HIGH, the average current is increased thanks to
the slow decay

E. MODULE PROGRAMMING
When no external component is used, the G8-0200
is set at the following conditions:
loutpeak

12/18

90

=1 A

L'J,
...,/

fc chopper frequency

=17 KHz

By addition of inexpensive passive components the
working conditions can be modified as follows.

SCS·THOMSON -_.-.-- ---..- . - IijJOI!:I'iI@rn~rn~I'iI@1Il0I!:ill

GS-D200
E.1. OUTPUT CURRENT PROGRAMMING
The output peak current (initially set at 1 A) can be
re-programmed by addition of an external resistor.

be connected between inSET and GND1 as shown
in fig. 10

If a lower peak current is desired, a resistor R 1 must

1-----

Figure 10 : Peak Current Reduction.

I
12
R,

1

GS-D200

_ _-

The value of output current, for Vss = 5 V, is related
to the value of R1 by

For example, for R1

11.2
lout =

-----

11.2 +

=

1 K£l

lout

=0.5 A.

If a higher peak current is needed, a resistor R2 must
be connected between 10SET and Vss as shown in
fig.11.

A where R1 is in KQ
12
R1

Figure 11 : Peak Current Increase.
Vss

R,

GS-D200

The output current, for Vss
value of R2 by

=

5 V, is related to the

120 + 12. R2
lout = ------ ---- - A where R2 is in Kn
12 + 11.2. R2
For example, for R2 = 24 Kn lout

Minimum value of R2 is 10 kQ. This current programmability can be used in half step sequence to
increase the current when only one phase is on : a
more regulator torque is so obtained.

=1.45 A

E.2. CHOPPER FREQUENCY PROGRAMMING
The chopper frequency is internally set at about 17
KHz. This frequency can be changed by addition of
external components as follows.

To increase the chopper frequency a resistor R3
must be connected between OSC pin and Vss as
shown in fig. 12.

91

GS-0200
.--.~~-

.. - - - - - - - -

Figure 12 : Chopper Frequency Increase.

R

1

1

12

GS-0200
~~6____________- - J

fe := 34 KHz

The new chopper frequency is given by :
fe

~

17 (1

+~-)
R3

To decrease the chopper frequency a capacitor C
must be connected between OSC pin and GND1 as
shown in fig. 13.

KHz where R3 is in Kn

For example, if Vss

~

5 V and R3

~

18 KQ

Figure 13: Chopper Frequency Decrease.

OSC

8

c

GS-0200
GN01 L-____________~~~
5-9457

The new chopper frequency is given by :
80.5

fe

~

For example, if Vss
KHz.

~ 5 V

and C

~

4.7 nF, fe := 8.5

- - - - - - - - - - KHz where C is in nF
4.7 + C

F. MULTI MODULES APPLICATION
In complex systems, many motors must be controlled and driven. In such a case more than one GS0200 must be used.
To avoid chopper frequencies noise and beats, all
the GS-D200 should be synchronized.

14/18

92

If all the motors are relatively small, the fast decay
may be used, the chopper frequency does not need
any adjustement and fig. 14 shows how to synchronize several modules.

GS-D200
Figure 14: Multimotor Sybchronization. Small Motor and Fast Current Decay.

osc 0------18

TO MOTOR 1

GS - 0200
MASTER

SYNC

10

osc

O--+--~8

SYNC

CONTROL

TO MU!UH 2

GS - 0200
SLAVE
10

osc 0>--+---18

CONTROL

TO MOTOR 3

GS - 0200
SLAVE
10

CONTROL

s- 94511

When at least one motor is relatively large a lower
chopper frequency and a slow decay may be required. In such a case the overall system chopper fre-

quency is determined by the largest motor in the system as shown in fig. 15.

Figure 15 : Multimotor Synchronization. Large and Small Motor. Slow Current Decay.
lOKI)

osc

~----18

SYNC

TO LARGE MOTOR

(2AI

GS - 0200
MASTER

I

10

OSC (>---+--.... 8
SYNC

CONTROL

TO SMALL MOTOR

(lAI

GS - 0200
SLAVE
10

CONTROL

- - - - _.. - - - -

G.THERMAL OPERATING CONDITIONS
In many cases the GS-D200 module does not require any additional cooling because the dimensions
and the shape of the metal box are studied to offer
the minimum possible thermal resistance case-toambient for a given volume.
It should be remembered that the GS-D200 module
is a power device and, depending on ambient tem-

. _ - _..

__

perature, an additional heath-sink or forced ventilation or both may be required to keep the unit within
safe temperature range. (Tcasemax < 85°C during
operation).
The concept of maximum operating ambient temperature is totally meaningless when dealing with power components because the maximum operating
15/18

._---------

93

GS-0200
ambient temperature depends on how a power device is used.
What can be unambiguously defined is the case
temperature of the GS-D200 module.
To calculate the maximum case temperature of the
module in a particular applicative environment the
designer must know the following data:
_ Input voltage
_ Motor phase current
_ Motor phase resistance
_ Maximum ambient temperature
From these data it is easy to determine whether an
additional heath-sink is required or not, and the relevant size i.e. the thermal resistance.
The step by step calculation is shown for the following example:
Vin ~ 40 V, Iphase ~ 1 A, Rph Phase resistance
10 n, Max. Tamb ~ 50°C

~

G1. Calculate the power dissipated from the indexer
logic and the level shifter (see electrical characteristics) :
Ploglc ~ (5 V . 60 mAl + (40 V . 20 mAl ~ 1.1 W
G2. Calculate the average voltage across the winding resistance:
Vout ~ (Rph . lout) ~ 10 n . 1 A ~ 10 V

G3. Calculate the required ON duty cycle (D.C.) of
the output stage to obtain the average voltage (this
D.C. is automatically adjusted by the GS-D200) :
D.C.

~ V out ~ _~ ~ 0.25
Vin

40

G4. Calculate the power dissipation of the GS-D200
output power stage. The power dissipation depends
on two main factors:
_ the selected operating mode (FAST or SLOW
DECAY)
_ the selected drive sequence (WAVE, NORMAL, HALF STEP)
1--

~F-a-st-D-e-Ca-y------

L~'owJ=>~cay

_ _ __

-

-

G4.1 FAST DECAY. For this mode of operation, the
internal voltage drop is Vsatsource + Vsatslnk during
the ON period i.e. for 25 % of the time.
During the recirculation period (75 % of the time),
the current recirculates on two internal diodes that
have a voltage drop Vd ~ 1 V, and the internal sense
resistor (0.5 [2). For this example, by assuming
maximum values for conservative calculations, the
power dissipation during one cycle is :
Ppw ~ 1.1 • [2 Vsat. Iph. DC + 2 Vd .Iph. (1 . DC) + 0.5.
IphJ
Ppw ~ 1.1 • [2 0 1.8 • 1 • 0.25 + 2. 1 • 1 • 0.75 + 0.5. 1J
Ppw ~ 1.1 • [0.9 + 1.5 + 0.5J ~ 3.19 W

The factor 1 .1 takes into account the power dissipation during the switching transient.
G4.2 SLOW DECAY. The power dissipation during
the ON period is the same. The RECIRCULATION
is made internally through a power transistor (Vsatsink) and a diode. The power dissipation is, therefore:
Ppw ~ 1.1 • [2 Vsat. Iph. DC + (Vsat + Vd) • Iph· (1·DC)J
Ppw~ 1.1. [2.1.8.1.0.25+ (1.8+ 1).1 00.75J
Ppw~1.1.[0.9+ 2.1J~ 3.3W

G4.3 WAVE MODE. When operating in this mode
the power dissipation is given by values of 4.1 or 4.2
paragraphes, because one phase is energized at
any given time.
G4.4 NORMAL MODE. At any given time, two windings are always energized. The power dissipation
of the power output stage is therefore multiplied by
a factor 2.
G4.5 HALF STEP. The power sequence, one phase
ON, two phase ON forces the power dissipation to
be 1.5 times higher than in WAVE MODE when the
motor is running. In stall condition the worst case for
power dissipation is with two phase ON i.e. a power
.
dissipation as in NORMAL MODE.
The following table summarizes the power dissipations of the output power stage of the GS-D200
when running for this example:
--

r --

-- -

C- ~ ~r~ --~~_ - ~ ~~ ~Wave

GS. Calculate the total power dissipation for the GS-

0200 :

Normal

example, an external heat-sink is required and the
thermal resistance can be calculated according to :

Ptot ~ Plogic + P pw
In this example, for slow decay and normal mode
Ptot ~ 1.1 + 6.6 ~ 7.7 W

G6. The case temperature can now be calculated:
T case

~

Tamb + (Ptot • Rth)

~

55 + (7.7. 5)

~

93.5°C

Rthtot ~ T em.!, -T~r1l~~ 8_~ __ 5~ ~ 3.9 °C/W
Ptot
7.7
and then
Rthhs ~ Rth - Rthtot

G7. If the calculated case temperature exceeds the
maximum allowed case temperature, as in this
16/18
------.-------Gi,/
SGS-niOMSON
•J,

li:ilu©l'J@rn~rn©~I'J@i'lu©$

94

Rth - Rthtot

5. 3.9
5-3.9

~ 17.7 cC/W

GS-D200
The following table gives the thermal resistance of some commercially available heath-sinks that fit on the
GS-0200 module.
1_ _ ....

Iv1~-~uf~~t~~er

Thermalloy
I

Thermalloy
Thermalloy
Fischer
Assman

~slTla~_

Part Number
6177
6152
6111
SKIS
V5440
V5382

Rth

(C/W)

Mounting

3
4
10
3
4
4

Horizontal
Vertical
Vertical
Vertical
Vertical
Horizontal

MECHANICAL DATA (dimensions in mm)

(-01)')11

17/18

95

~G~S~-D~20~O=----______________ __________ _ _________
MOTHER BOARD LAYOUT
N"4 HOLES ?2~Ol

18/18

96

GS-R400
FAMILY
140W SWITCHING VOLTAGE REGULATOR MODULES
•
•
•
•
•
•
•
•
•
•
•
•

MTBF IN EXCESS OF 200.000 HOURS
NO EXTERNAL COMPONENTS REQUIRED
PC CARD OR CHASSIS MOUNTABLE
HIGH OUTPUT CURRENT (4 A)
HIGH INPUT VOLTAGE (48 V)
FIXED OR ADJUSTABLE OUTPUT VOLTAGE
HIGH EFFICIENCY (UP TO 90%)
SOFT START
REMOTE INHIBIT/ENABLE
REMOTE OUTPUT VOLTAGE SENSE
RESET OUTPUT (GS-R405S ONLY)
NON-LATCHING SHORT CIRCUIT PROTECTION
• THERMAL PROTECTION
• CROW BAR PROTECTION FOR THE LOAD

------

.

-~---.--,

DESCRIPTION
The GS--R400 series is a complete family of HIGH
CURRENT HIGH VOLTAGE SWITCHING VOLTAGE REGULATORS available in several output voltages from 5.1 to 40 V.
These step down regulators shielded for EMI, can
provide local on-card regulation, or be used in central power su pply systems, in both professional and
industrial applications.

PRODUCTS FAMILY

r----_-_=__=__=_o=rd~e_r_=_N_=_u-m_b;_;_-_--_ _--+_-~ -

6;i;ut V~ltage-

GS-R405S

5.1 V

GS-R405

5.1 V

GS-R412

12 V

GS-R415

15 V

GS-R424

24 V

GS-R400V

Adjustable 5.1 to 40 V

September 1988

-t-I

Reset Output
Yes

[

Ii
1/21

97

GS-R400
CONNECTION DIAGRAM (side view)
GS-R 400 V

GS-R 4055

GS-R 405/412/415/424

INH

INH

INH

Vi
GND 1

Vi
GND 1

Vi
GND 1

GND 2

GND 2

GND 2

RT

5-

55+

55+
Va

5+
Vo

~a

s - 6 g] 1"

5 - 6!1]

5-6']2/1

/1

MECHANICAL DATA (dimensions in mm)

c:
--~-.

5

~--

--

36.83! 01

:JI

r-w

C·O')~/1

-~---~------------~-

2/21

98

GS-R400
PIN FUNCTIONS

l

Symbol! - - - - - INH

Pin

: - Inhibit

_I

. To be connected to GND2 when not used.

RT

. - Reset Output

Vi

I: - Input Voltage

GND ,

I

I Common gro-und for input voltage.
Common ground of high current path.

Ground

S-

- Sensing Negative

II

I

For connection to remote load, this pin senses the actual
ground of the load itself. To be connected to GND2 when not
used. This pin is connected to case.

I,Forconnecti~~to

-----t----------S+

Available on GS-R405S only. Reset voltage IS high (5.1 V)
when output voltage reaches nominal value (5.1 V) and It is
generated with a fixed 100 ms delay.

Unregulated DC voltage input. Maximum voltage must not
exceed 48 V. Recommended maximum operating voltage is
,46 V.

- Ground

GND2

Function
, TTL compatible input. A logic high level signal applied to this
I pin disables the module .

remo; I~~d~ thiS pin allo';'~~~;~;e s~n­
sing on the load itself.To be connected to Va when not used.

, - Sensing Positive

I

1- Output Voltage
1----------------- --- Output Voltage Programming
P
I

-----

-

----

------

Regulated and stabilized DC voltage is available on this pin.
Max output current is 4 A The device is protected against
short circuit of this pin to ground or to supply.
Available on GS-R400Vonly. A variable resistor (18 K£l
max) connected between this pin and S - adjusts the output
voltage.

ABSOLUTE MAXIMUM RATINGS

r

Parameter
Value
Symbol:
1 - - - - + - - - - - - - - - - - - - - -------- . ------- - -I + - - - - - - - - _ + _
V,
IRT

-~--

19c-,nput voltilgEJ_

I

Reset output sink current
------ - - - - - -

Unit

48

V

20

mA

----------------

V,NH

\ Inhibit voltage

Tstg

'Storage temperature range

Tcop

IOperating case ter11fJerature range

15

L

--------

------ -

40tO+l05

V

'C

-----

- 20 to + 85

- - - - - - - - - --

C

----------

Recommended maximum operating input voltage is 46V

3/21

99

GS-R400
ELECTRICAL CHARACTERISTICS (T amb = 25'C

unless otherwise specified)

_______ T_~y~p,e_ _ _ _ _ _ _ _ _~-G-S---R-4--~~
Symbol

Parameter

-~---I------~-

.-

GS-R 405

Vo

Output Voltage

V,=Vo+8V,lo=IA

Vo

Temperature
Stability

V, = Vo + 8V, 10 = lA

5

GS-R 4012 V :

5.15.2

5

0.2

5.1

5.2

Input Voltage

___ O_~_I

0.2
46

10 = 1A

_~

_O_u_tp_ut_~_u_rr_en_t_ _V,- = Vo+_s..v_ _ _ _ _ 22

10

Current Limit

10L

f-_I_~:_C +-~_F~_r~_;~_~_~_:;_I:y_P_ut_+-~_~_U~_P_~_:_S_\_0_r_te_d
__

1]

_ _ _+-___

Vi =

Efficiency

0.2_ _ _

Vo + BV

l_00_·~. ,o ~
___

75

fWo

Line Regulation

8

:

v

V

4

I

A

8

i

A

I

~o~-4-,~

_

85

%

2---~~;
L~--

10 = 1A V I = Vo + 3V

to 46V

---~
--------.
SVR
Supply Voltage
f = 100Hz
4
_ _ _ ~ejectio"----~'--A ____ .____ ~_... _. _______ I_
-·----I-···-------~I-------

Load Regulation

I

~61

46

75

10 = lA
r---+-------+-------------------.

15

~ O~__

5

8

VI=Vo+8V

46

8

1~:s1

11.5

---r-----~-____t-- ----~

V,

I

~;P-:-M-;;- ~~~ uni~.

I----r:.es..._c_o_nd_i~_~i_n_._T_y_p_~~

4

mVIV

I

-----

-----4-0----T mV/A

Lllo = 2A
(1 to 3 A)

20

20
-L--_

f -__
V_,__+_R_i'--pp'--l_e_V_o_lt_a=-ge__+-I-'-o"-'ot__=
__2_A_______
Soft Start Time

'

~

VINHL_

V ,NHH

Low Inhibit
Voltage

V'c=Voot+l0V

feB

0.8
-_

2.0

5.5

Crow Bar Delay
Time

2.0

--------+-----

I_,N_H__+_H__
i9'--h_______ r-"'-"-H=-~_

:

- - - ._---_. - - 1 - - - - - - - -

1----+-------+------ - tR
,

Max Differential
Voltage

L_~~_?ense

4/21

100

IRL = SmA
IRL = 15mA

Reset Delay
Time
Vo - S '

2.0
--

-----

100

-

ms

--~~:
..

mV

f-:-

---~-

""'I::

i

J~~ -;-

~
I

100

S- - GND2

_----

......

5.5

500

500
.-----

Reset High
Level

I~!
VRL
.t-Reset Low Level

25

15
0.8

,------ · - · - - - - - - - - - - r - - - - - - - - .
Input Current

~

15

I-- - - - - - - - - -

High Inhibit
Voltage

_____5_0_ _---11

______
2_5-----t----.2s...----

10_0~

_____

ms

__m_v_

i

GS-R400
ELECTRICAL CHARACTERISTICS

~~mb~

(Tamb

= 25"C unless otherwise specified)

'J:l------~-------~---l--GS-R4~
__ Parameter

Vo

Output Voltage

r=Testc~it. ---+-1MI;-r-;;--Ma0-lvI rn ._
I V,=Vo+8V

Tempera~ure

Vo

Stabillty'_ _

V,

Input Voltage

'!....'

_

= Vo + 8~_lo

1143
I
= 1Aj

10 = 1A

15

18

I

Average Input

~~~~~:ng

IS,'

-

Frequency

~S

---

--

01

02

.

.

rJlax.

Min.

24

25

51

I

-

40'

V
I

06

02/16

27
0.2

400 V

Typ. - Max.] Unit

__
0.1

!:!JY
C

46

46

V

~j02n___

4'

:

0.2

0.2

A

0.1

-1

100

-------------------

Efficiency

1")

~utPu1tAShorted---j-

:

Typ.

0 =

---- - - -

'~;

T

Vi = 46V

-

____

r

46

II~L- ~~:~~~tCL~:~nt~: :_0~:~-i=°2
[

156]23

02

_

GS-R

-----,-------------,--

-GS:I:1424

75/90

10 = 1A
V, = Vo + 8V
10=1A V,=Vo+3V

~VV-oR-~-L-i-n-e-R-e-g-U-la-ti-o-n~-to-4-6-V------Supply Voltage
f = 100Hz
_--+_R_el,--e_ct_,o_n_ _ _+--I?_._ ~_1A
_______

8

2A
LO. ad RegUlatlon~.
(1 to 3A)

1------+--------_.

60

-------.----

loot = 2A

Ripple Voltage

...:IJi~

12

mVIV

-----

----t----------~--

~Io =

6

20/90

----+-----------_.-----100

60

_~/~ ..
,

25/150

mV

---------.- ---+-------------1---------15/3S
35
ms
~~~~-S-0-ft-S-t-a-rt-T-i-m-e~-V'--'"~=-V-o'--0'--t-+-1-0-V--~---25
-~~-------+_----------__+--_____1
-------~~

Low Inhibit
Voltage

0.8

0.8

-----------1---------

High Inhibit
Voltage

2.0

5.5

S.5

2.0

2.0

----~~:t~

-~~------I------

Input Current

V ,NH

High

=

SV

SOO

500

-

SOO

.~----+----"'-------~----------

Crow Bar Delay

+__~-:~-:-i

I--____

I

:i -- --1
---t------- ---

Time

_H_'9_h

;-~-;~-;-~ ~; _._IL·_e. :~=_ -= _~ N_.

S

-------f----

-----~~-+----I

V
1

+______

_D_2_ _ _ _..L _ _ _ _ _ _ _ _ _ W"

--_:1_1_"_0_
':::::-_---1-0-0 :

~

• Maximum Output Current is guaranteed up to Va = 36V and derated linearly to 3A at Va = 40V

5/21

101

GS-R400

--------------------_.

_ _ . _ _. . _ - - -

MODULE OPERATION
level, the module restarts softly. Maximum DC voltage applicable to this pin is 15 V. When remote
control (inhibit) of the module is not used, the INH
pin must be connected to GND2.

The GSR400 series is a family of step down switching mode voltage regulators.
Unregulated DC input voltage must be higher than
nominal output voltage by, at least, 3 V. Minimum
input voltage is therefore 8 V for GS-R405S and GSR405; maximum input voltage is 48 V for all types.

The remote load sensing is another feature provided in all the models.
This function is performed by two pins (S+, S-) that
can monitor the voltage directly across the load
when this load is connected to the module by long
wires: voltage drop on these wires is automatically
compensated. Maximum drop compensation must
not exceed 100mV. The case of the module is internally connected to S-. Therefore, the case must
be always isolated from ground if the sensing function is used. The switching frequency of the module
is 100 KHz. To prevent EMI, the module is contained in a metal box that provides shielding and heatsink.

Output voltage is fixed or adjustable (GS-R400V).
The maximum current delivered by the output pin is
4 A. A minimum output current of 200 mA is required for proper module operation. In no-load condition, the module still works, but the electrical characteristics are slightly modified vs. specifications.
To prevent excessive over current at switch on, a
soft start function is provided. Nominal output voltage is approached gradually in about 15 ms.
The module can be inhibited by a TTL, NMOS or C
MOS compatible voltage applied to the INH pin.
When this voltage is at high level, the module is switched off : if the inhibit signal goes from high to low

Figure 1 : Module connection to remote or nearby loads.
- - -

----------

-

-------

~----~:
LOAD~=-=---S­
GND
REMOTE LOAD CONNECTION

5- 6 9 35/1

L

NEARBY LOAD CONNECTION
-----------------------

GS-R405S
The RESET output is provided on GS-R405S only
as an auxiliary function to reset or inhibit microprocessors when the output voltage, at switch on and
off, reaches a prefixed value of 4.9 to 5.1 V or when
the output voltage, for any reason, drops below nominal value by more than 100 mV. In any case the

6/21

,'W., SCS-niOMSON
•J,

102

minimum falling threshold value is 4.75 V or higher
and the reset output voltage is generated with a
fixed delay of 100 ms.
Time delay of the reset function also rejects wrong
information caused by occasional spikes generated
during switch on and off.

UflJI©>iI@rn~rn©1JI'iI@IIlI©i!i

---- ------.-- -----

GS-R400
Figure 2: Output voltages reset as a function of output voltage and time .
.-

OUTPUT NOW
STABLE,RESET
GOES HIGH

Vo

AN INTERRUPTION
OF SUPPLY CAUSES
RESET OF MICRO

~

RESET
THRESHOLO-

--------

I

AT POWER DOWN
MICRO IS INHIBITED
IMMEDIATELY

MONITORED
VOLTAGE

--I

V

RESET
OUTPUT

I

I
I

i

I

in
I

I

-11-

DELAY

I

_11_

DELAY

5-7(.66,1

GS-R400V
The output voltage of this model can be adjusted in
a range from 5.1 to 40 V by use of an extemal variable resistor as shown in Fig.3.
The variable resistor can be substituted by a fixed
value Rx to obtain a fixed output voltage Va according to the formula:

Rx

=

2.67.

(~.ol

- 1 ) KQ

where Va can vary from 5.1 to 40 V.

Figure 3 : Output voltage adjustment on GS-R400V.

o to

18 K 1t max

5- 691111.

7/21

103

GS-R400

---------

..

-~---

MODULE PROTECTIONS
THERMAL PROTECTION

in a soft mode: if the overload is still present, the
module switches off and the cycle is repeated until
the overload condition is removed, The average
overload current is limited to a safe value for the module itself. Input current during output short circuit is
always lower than in regular operation,

The module has inside a thermal protection. When
ambient temperature reaches prohibitive values, so
that internal junction temperature of active components reaches 150°C, the module is switched off.
Normal operation is restored when internal junction
temperature falls below 130°C: this large hysteresis allows an extremely low frequency intermittent
operation (ON - OFF) caused by thermal overload.

LOAD PROTECTION
The module protects, by a crow bar circuit, the load
connected to its output against overvoltages,
This circuit senses continuously the output voltage:
if, for any reason,the output voltage of the module
exceeds by + 20 % the nominal value (fixed or adjustable), the crow bar protection is activated and it
short circuits the output pin to ground, This protection prevents also damages to module if output pin
is wrongly connected to supply voltage,

SHORT CIRCUIT PROTECTION
The module is protected against occasional and
permanent short circuits of the output pin to ground
or against output current overloads.
When output current exceeds the maximum allowed
value for safe operation, the output is automaticaly
disabled, After a fixed time, the module starts again

THERMAL DATA
The thermal resistance module to ambient is about
5 °C/W, This means that if the internal power dissipation is 10 W, the temperature on the surface of
the module is about 50°C over ambient temperature,

Four holes are provided on the metal box of the module to allow the mounting of this optional external
heatsink,
It is recommended to keep the metal box temperature below 85 DC,

According to ambient temperature and/or to power
dissipation, an additional heatsink may be required,

TYPICAL APPLICATIONS
the module with batteries that, according to their
charge status, can show large spread on voltage,

The high input voltage range allows both cost saving on 50/60 Hz transformer when the module is
supplied from the main and the possibility to supply

Figure 4 : A typical application of GS-R400 family,

GND 1

'-----5-"-,."-

8/21

104

INH

Vi

-~~ICE

'-----1----1

GS-R400
TYPICAL APPLICATIONS (continued)
quency therefore the equivalent input circuit is as
shown in Fig. 5.

The module has. internally, an input filtering capacitor between pin Viand GND1. Atthe switching fre-

Figure 5: Equivalent input circuit of GS-R400 voltage regulator.

EXTERNAL CONNECTING WIRE

II-+---~Vi +
r -

-

I

I

I

I

: INTERNAL
I CAPACITOR

-'
5-1)939

When very long connecting wires are used, the input capacitor may be damaged by this power dissipation. For this reason it is suggested to keep input
connecting wires as short as possible.

Since II is a high frequency alternating current, the
inductance associated to long input connecting wire
can cause a voltage ripple on point VI that produces
a ripple current across internal capacitor and a power dissipation on r.

Figure 6 : Preregulators for Distributed Supplies.
--_

. ._

----

---------------,

\ - - _ - - - ( ) 5VIO.4 A

5 BV

L4805

I----------<~~O 5V/O.4A

I
I

~ "" Ig I
$- 6941

I

The fixed voltage regulators shown on Fig.6 are
available from SGS-THOMSON Microelectronics.
An over-all low power dissipation is achieved due to

I

1_

I

:
.

5V/O 4A
SYSTEM
RESET

the high efficiency of the GS-R400V and inherent
low voltage drop of fixed regulators. Up to 10 different points can be supplied, using L4805 or L387.

9/21
- - - - - - - - - -

105

GS-R400
TYPICAL APPLICATIONS (continued)
Figure 7 : 24 V to 12 V Power Conversion for Trucks.
~---

- - -

- - - - - - - - - - - - - - --

-

-

-

---

----,

I
I

12VI4A

I

5 - 69l,2

Figure 8 : Multiple output supply using preregulator.

25-35V

Ep-=
GS-R405S

5V(4A)

SYSTEM
RESET

-..

12V (4A)

5 -7187

.--------------_._---

---

- - - - - -------------------~

Figure 9 : Uninterruptable power supply.
- - - - - - - - - - -

------------------------------,

MAINS

+5V
SYSTEM

RESET

10/21

-- - - -- ----- ru,/
• J,

106

SC:;S·1HOMSON

[i;]DIOL'iI@~~~IOVI'iI@Ii!DIO$

GS-R400
EFFICIENCY VS. INPUT VOLTAGE & OUTPUT CURRENT
GS-R412

GS-R405
G

G- 5486

5485

'1

'1

(", )1--

('" )

--

80

-~

r-

t<-

-

-t-

- ----

10

~

-~

-

+-

(V)

40

I--

-

20

10

--

'-... \\
\

r-

t-

-

,\\..

--- 1---- I--- f--- f - -

--

30

--".

~ "A
i'-- ~
.........

- - I--- I--- 1--- f---

:
20

t--

"<;:

-

:

G

r-. I'....

)

~
I---

-

---

-- -

---

-

---

-

-

4A
---

40

30

(V)

GS-R424

'1

-

- - --

5487

'1

2- 3 1A

(", )

r--.. ~
K:' ~

90

"-

\.

\
--

20

30

-

40

G SUI

r-..

--- r--::~
lA

~-4A

---

......

:--......

...:.: -

~

\

10

~-

...........

\.

80

70

I--

70

--

GS-R415
('"

2A
!r---....1A""""

-

-

4A

-- '7

........

-

-----

50

-

-

1---

-

-

--

"

- ---

-

---

4A

~
~
1A

...........

60

---

~

.......... ~

70
--

-

80

..........

80

\

(V)

30

40

(V)

11/21

107

GS-R400

MOTHER BOARD LAYOUT

/-

112.SS±O.15

GS-R405S

I-

112.55+0.15

-I

II 2.SS± 0.15

-I

GS-R405
GS-R412
GS-R415
GS-R424

/'
GS-R400V

Printed Circuit Driling (Components side)
Required holes pattern to be drilled on the mother boards to allow correct mounting.

12/21

108

GS-R400
DESIGN HINTS
The hints provide a pratical guideline for the selection of the transformer, the rectifying diodes and the
filtering capacitor of a power supply based on GSR400 family.

In the following we will consider the full wave bridge
only, that allows the best transformed utilization.

Let's consider the application shown in the Figure
10. The rectifier circuit configurations suitable for
medium to high current applications, are the Full
Wave Center Tapped and the Full Wave Bridge.
(See fig.11)

5 V . 4 A = 20 W
12 V . 2.5 A = 30 W

Both configurations offer the advantage of a smaller surge current in the winding of the transformer
and the doubling of ripple frequency that allows the
filtering capacitor reduction.

The output power of the power supply is, respectively:
for GS-R405S
for GS-R412.

The total input power is, therefore
Pi = . Pg
20_ + -]Q = 62W
Eft.
.75
.85
The two values for efficiency are derived from GSR electrical characteristics.

Figure 10 : Microcomputer supply using GS-R400.
+SV
LOGIC
BOARO
RE5ET

G5-R40S5

G5-R412

+12V
FLOPPY
HARO-Dl5K

GND

~-_---()

-12V
5-8186

The maximum input voltage to the module is set up
to 40 V to work well below the Absolute Maximum
Rating (48V).
Vi (pk) = 40 V
The minimum input voltage is set uo to 16 V to alIowa minimum drop-out of 4 V on the GS-R412.

The nominal input voltage is set up at the middle of
this range to allow a larger input ripple voltage and
line voltage variations.
Vi(DC)=

40-16 +16=28V

2

Vi (min) = 16 V

13/21

109

GS-R400
DESIGN HINTS (continued)
Figure 11 : Rectifying circuits.
------ - - - - - - - - - - - - - ,

c

5-8187

Let's assume a maximum 100 (120) Hz output ripple of the two regulators of 20 mVpp. Since the ripple rejection of the two modules is, at least 50 dB
(316 times), the maximum allowed input ripple is
20 mV . 316 = 6.32 Vripple(pp)
Let's definite rf(in) as the ratio of RMS ripple to DC
voltage
rf(in)=

-~ ~.~2 28

Vi(DC)

.100 = 8 %

~eJ.Q) =

RL = 28\L = 12.73 Ohm
2.2A

- - - - -- - - -- ---- - - L"'!I

110

Vi(pk)

1..8,!

= 0.82

34V

From the graph of fig. 12b we obtain,

= __ 62W - = 2.2 A
28 V

~(D(;)

for

= 0.82

Vi(pk)

The equivalent load for the transformer + rectifier +
capacitor is therefore

14/21

Vi(pk)nom = 40 - 15 % = 34 V
Then we calculate

The input current is calculated from the input power
and voltage :

_FL_

Vi(pk) must correspond to the nominal value of the
mains plus the allowed variations. Let's assume that
the AC voltage at the primary of the transformer may
vary of ± 15 %.
At nominal AC voltage the corresponding secondary maximum DC voltage is :

(lJCRL = 8 and _Rs = 4%
RL

N
~~~~~~~~:I!~©§

-

-

-

-- -----------

GS-R400

I,

I,
DESI<;iN HINTS (continued)
Figure 12a : Input Voltage (DC/pk) Ratio Half Wave.
nn

R.
.v

+ c1 8",

90

~

.l

80

1

~~

~ "r

2

--

4

~

70

6
8

---

~

60
Vi(DC)

----%

50

Vi(PK)

30

110
2. 5

15
,n

~~

r/I'

40

~ ~~

20

r

O. 05
O. 5

35
40
50
60
70
80
90
10 o

r% ...

~ l%~

~V
V
V

10

a
0.1

10

100

1,000

wCR L (C in farads, R L in ohms)

w

_ __

-

-

___

-

~

211f, f = line frequency

_ __ r==

S(iS-ntOMSON

15/21

. ., / iI:IlD((;Iffi@~~~((;1JIffi@i!D((;®

111

GS-R400
------,---,

-----

_.,---------

------'-~-.---.---.-

----'-'-

DESIGN HINTS (continued)
Figure 12b : Input Voltage (DC/pk) Ratio Full Wave.
0.05

100

]~;~ ICEF

90

it~~

~'~~.

80

,J"

~J/

70

V
V

~

o. 5
1

2

.-

4

..-

6

--

8
1o
1 2.5
15

...-

~~
V...
~VI--

Vi(DC)

--- %
Vi(PK)

~ r:=

0 .1

...

60

2a

~ Vi.-'" ...

50

35
40

V

50

V l-

60

~
...l-

80

t:::

f-

4a

70

90

l-

00

t-

3a
0.1

AL

25
3a

~

r-

~(%)

10
wCAL (C in farads, AL in ohms)

100
W=21Tf,

1.000

f=line frequency

Therefore

8
C=--211:f· RL

8
6.28 ·100 ·12.73

= 1000 ~F

To take into account the spread of commercially available capacitors, this value is doubled: 2200 ~F 150 V.
We procede now assuming that:
Rs = 4 % RL = 0.04 . 12.73 = 0.51 Ohm
It represents the total series resistance of the transformer and the rectifying bridge.

16/21

112

GS-R400
DESIGN HINTS (continued)
Figure 13 : Ripple Voltage vs. Input Capacitance and Rs/RL.
100
Circuit

70
50
30

....

20

~~

.......

~~
I ......

10

"*

7.0

<;

5:0

"-

~

.

3.0

;;

2.0

R/R, 1%)

r'
A

:: 1.0
--10
-- 30

Half·Wave

~
~

~~

__ 0.1
--1.0
--10
--30

Full-Wave

A

~

,,-,~

,"

"

0.

~

~

~~

"

((

.::

Parameter

A

1.0

t'..:: ~

t"~
~

""r"

o. 7
0.5

........ ~

,",

0.3

....... ~
~

"

~

1'...:

~

0.2

....... ~ ~ ...... t:S:

o. 1

["", r...-:t'l'-

1.0

2.0

3.0

5.0 7.0

20

10
wCR

w=

L

30

200 300

50 70 100

(C in farads, R

27ff, f

""

L-

500

1000

in ohms)

= line frequency

From the figure 13 for WCRL = 8 and Rs/RL = 4 % it results:
rf

= 7.5 %

Therefore the peak to peak value 01 the resulting input ripple will be :
Vripple(pp) = 2 -v2 . rl . Vi(DC) = 5.9 Vpp

This value is lower than the maximum allowed (6.32 Vpp).

.

~ SCS-TlIOMSON
-- ""11
[;:t]U©I:I@~~~©1JI:I@ilU©®

-

.._

17/21
-

113

GS-R400

-----

DESIGN HINTS (continued)
Figure 14 : RMS/Average Peak/Average Diode Current relation.
10

Qj
"0

.<:!

7

0

..
e:.
~

5

>
«
u::

3

in

2

....

1

:2
a:

1

u::

"

1
1.0

u..

i
2.0

3.0

6.0 7.0

10

20

30
nweA

60

70 100

1000

200 300

L

40
Qj
"0

30

0
:;;

20

0.02
I-"

0

e:.

~
~ >--

:>

«
u.
....
Il
«
w
"-

0.05

,.:::::P""

10
7

..

6

u.
3
1.0

0.1
0.2

-

~ E::=

::...- r-

0.5
1 .0

2.0
5.0
1a

e
~

2.0

-='

~
a:

*

30

100

3.0

5.0 7.0 10

20

50

30

200 300

70 100

500 700 1000

nweRI..

n=G
w "" 2

For Half-Wave Single-Phase Rectifier Circuits
F.or Full-Wave Single-Phase Rec.tifier Circuits

C

in Farads

RL in Ohms

rr t where f = Line Frequency

Rs '"" A MS Eq uivalent Source Resistance

The minimum input DC voltage will correspond to
the minimum input AC voltage, i.e. the nominal value minus 15 %, therefore
Vi(DC)min = Vi(DC)nom - 15 %
= 28 - 15% = 23.8 V

As shown on figure 14 for 2wCRL = 16 and Rs/2RL
= 2 % we obtain:

The minimum peak voltage present at the input of
the regulators will be the minimum DC voltage minus the peak of ripple voltage:
Vi(pk)min = 23.8 -

5i

= 20.85V

well above the minimum allowed (16 V).

18/21

114

IfiRMS)
If(Av)

=2

Therefore:
Isec (RMS)= I;!,D,C) :..?

,2

2.2.2= 3.12 A (RMS)
"02

GS·R400
DESIGN HINTS (continued)

The secondary voltage must be :
l.I,(pk):I: 1.4 = 25.1 V (RMS)
\/2
where 1.4V takes into account the voltage drop on
diodes.

As shown on figure 13 for 2wCRL = 2 . 8 = 16 and
Rs/2RL = 1/2·4% = 2% we get

Then the transformer rating is calculated:
VA=25.1 3.12=78.3VA
To select the rectifying bridge of diodes, the following considerations applies.

and

Vsec (RMS) =

The forward average current is one half the total input DC current since the configuration is a bridge:
If(Av) = I~[)C)
2.2_ = 1 1 A
22'

If (pk)
.
If (Av) = 8 I.e. If (pk) = 8 . If (Av) = 8.8 A
If (RMS)
if (Avg) = 2 i.e. If (RMS) = 2 . If (Av) = 2.2 A
The surge current occurs at the maximum secondary voltage
Isurge =

1/, (flk)
Rs

40
0.51

78.4 A

HOW TO CHOOSE THE HEAT SINK

Sometimes the GS-R400 requires an external heat
sink depending both operating temperature conditions and power.
Before entering into calculation details, some basic
concepts will be explained to better understand the
problem.

Tease = Tamb + Pd· Rth = 40 + 13·5 = 105°C
This value exceeds the maximum allowed temperature and an external heat sink must be added. To
this purpose four holes are provided on top of the
case.

The thermal resistance between two points is represented by their temperature difference in front of
a specified dissipated power, and it is expressed in
Degree Centigrade per Watt.

To calculate this heat sink, let's first determine what
the total thermal resistance should be.

For GS-R400 the thermal resistance case to ambient is 5 °C/W. This means that an internal power
dissipation of 1 Watt will bring the case temperature
at 5 °C above the ambient temperature.

This value is the resulting value of the parallel
connection of the GS-R thermal resistance and of
the additional heatsink thermal resistance.

Rth = lease(mplr Tamb =

§5134~ = 3.46'C/W

R1l.(C:3$BL ~hi.Heatsin~1 = 3 46'C/W
Rth(GSR) + Rth(Heatsink)
.
The maximum allowed case temperature of the module is 85°C.
To calculate the thermal resistance of the additional
Let's suppose to have a GS-R412 that delivers a
heat sink the following equation may be used:
load current of 4 A at an ambient temperature of
Rth(Hs) = ~.46~tb{GSR) = ~.46· ~ = 10 54'C/W
40 DC.
Rth(GSR) - 3.46
5 - 3.46
.
The dissipated power in this operating condition is
about 13W, and the case temperature of the modu Ie
will be:

19/21
115

GS-R400
HOW TO CHOOSE THE HEAT SINK (continued)
The following list may help the designer to select the proper commercially available heat sink.
Sometimes it can be more convenient to use a custom made heat sink that can be experimently designed
and tested.
Manufacturers
Thermalloy

Fischer

SGE Borsari
I

Assmann

L

-t-~::
6152
6111
SK18
SK48
SK07
SR50
V5440
V5382
V5460

_ _ _ _ _ _ ----.l_-"551~

-

Rth

.. _ Moun~ng.

Fastening

J

3
3
4

Horiz----r------;;-rew
I
Vert
I
S~~ew
Vert.
Adhes.
I
Vert.
Screw,
Vert.
Screw
Vert.
Adhes.

6

Vert.

Adhes.

4
4

Vert.
Horiz.
Vert.
Vert.

Adhes.
Screw
Screw
Screw

3
4
10

__ ~ __1-

HOW TO CHOOSE THE PROTECTING FUSE
The GS-R400 family protects the load against overvoltage, by an intemal crow-bar that continuously
senses the output voltage and fires a thyristor when
the voltage is higher than the nominal + 20%. Thyristor current capability is 150 A.
The crowbar can be activated either by an overvoltage generated by an external injected voltage, or
by a failure of the module itself.
In the first case the module provides to limit the input current to a safe value, and to recover the normal operations it is sufficient to switch off the input
voltage for a time greater than the discharge time of
the input filter capacitor.
In the second case the failure is pratically a module
input-output short circuit, the input current is no
more limited by the module, and it is necessary to
provide a method for disconnecting the module from
the input voltage in a very short time to avoid failures
of the board where the module is mounted.
The simplest method foresees the use of a fuse in
the input path to limit the fault current to a safe value.

20/21

116

The proper fuse should be selected with some criteria:
_ the fuse must handle the steady state current
_ the fuse must handle the inrush current that occurs at tum-on
_ the fuse must blow if the module has an input to
output short circuit.
To this purpose, it is usual to select a fuse whose
rated current is between 150 and 250 % of the rated full-load input current.
This usually provides enough overload capability to
prevent fuse blowing from aging and fatigue due to
repeated turn-on overload.
It is also necessary to examine the opening time versus the fuse overload characteristics, and the best
choice is the high reliability, low cost, standard commercial units like 3AG, 3AB or DIN41661.
All the units must be of the fast type with fusing characteristics as depicted in dashed area of fig. 15.

GS-R400
HOW TO CHOOSE THE PROTECTING FUSE (continued)
Figure 15 : Fast fusing intervention curve.
G-5960

t

c-=-=

e

(mS)6

}l\

-

- -

t---1----

-~

1---

-

t--

1\

-

t--~~--

1---10

------

j

~
-~

-

I- .-1I-~--

-

r\..- 1---

,

[\

t----l r-- ---II--~-

r\

-

!"l\

~~-.

t'I

~

10

As an example, for a GS-R405 unit supplied by a 24
Volt minimum input voltage, the fuse rating can be
calculated as follows.
At a maximum delivered power of 20 Watt, assuming a 70 % efficiency, the input power will be 28.5
Watt and the input current 1.2 A.

-- - - - -- ----

-

-

-

j

- - (:::.--::--\- t--

I----

~

--

f-

f--- 1--

I-:=-:~: - :::==-

~:--.--:-

1--+-

-

--

I (A)

The fuse rating will be 2A that guarantees a maximum fusing time of 20 ms (typical 2 ms) for a current of 20A that can be generally accepted without
board problem.

21/21

117

I
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GS-R400VB
140W SWITCHING VOLTAGE REGULATOR MODULE
•
•
•
•
•
•
•
•
•
•
•

MTBF IN EXCESS OF 200.000 HOURS
PC CARD OR CHASSIS MOUNTABLE
HIGH OUTPUT CURRENT (4 A)
HIGH INPUT VOLTAGE (48 V)
ADJUSTABLE OUTPUT VOLTAGE (5.1 t040 V)
HIGH EFFICIENCY (up to 90%)
SOFT START
EXTERNAL SYNCHRONIZATION
REMOTE INHIBIT/ENABLE
REMOTE OUTPUT VOLTAGE SENSE
NON-LATCHING SHORT CIRCUIT PROTECTION
• THERMAL PROTECTION
• CROW BAR PROTECTION FOR THE LOAD
• MAXIMUM CURRENT LIMITING
DESCRIPTION
The GS-R400VB is a HIGH CURRENT HIGH
VOLTAGE SWITCHING VOLTAGE REGULATOR
particularly suited for designing multiple outputs power supplies.

ORDER CODE: GS-R400VB

This step down regulator shielded for EMI, can provide local on-card regulation, or be used in central
power supply systems, in both professional and industrial applications.

ABSOLUTE MAXIMUM RATINGS
~m~__

parameter-=__-=-~-=---------V~I~e -

~---+-D__C;__lnput-",olta.2.~ ~

_

__----,

G;

I

I_~ Ts'JL

l_storil(Je TerTlperatur.e....Ra.n.ge _ _

I

Output Current
Inhibit Voltage ~ --

-

---

L Teop........LOperatlnJL Cas", Temperayure .£'ange

-- -

48

-----~-, ----

-

-

-- -

1

4

----15 -

·-[U~itJ

!___
=+
--

__

---::: 40to +~05___
-- 20 to + 85

V __ ~

A
V-

j

=-c~j

__

1

C

Recommended maximum operating .Input voltage is 46 V

September 1988

_

... ______. __ ~ _ _...__._ _ _ _ .~_ _ _~_

1/9

119

GS-R400VB
CONNECTION DIAGRAM (side view)
c-·~-----··

- - - - - - - - - -..

------~.--

G

s- R400VB
INH

Vi
GND 1

OSC

SYNC
CL.

GND 2

S-

5+
Vo

p

I

S-880511

J
MECHANICAL DATA (dimension in mm)

.- . ..
-~-

~~~--

---l

[-c,----------.)JI
I 3683! 0\ I

.

~

__

i..

5

c·
85.5

120

01J~11

I

GS-R400VB
PIN FUNCTIONS
PIN

INH

Vi

FUNCTION

-Inhibit

TTL compatible input A logic high level signal applied to this pin disables the module.
To be connected to GND2 when not _used.

- Input Voltage

Unregulated DC voltage input. Maximum
voltage must not exceed 48 V. Recommen-

--I- ~~;:::~~~~~~:;~~:~:~;~:~;:-~:-~~...--

GND1

- Ground

OSC

- Oscillator Output Pin

An internal RC network determines the
100 KHz PWM switching frequency.
This pin must be connected SYNC if the unit
is a Master.

- Synchronization Input Pin

This pin must be connected to SYNC pin of
the Master unit.

f-----

--------

SYNC

f--------j--.--.-.------.--- .

C.L.

An external resistor connected between this
pin and S - fixes the maximum output current (2,2 Kn min). To be left open when current set is not used.

- Current Limit

------

f - - - - - - - - j - . - - - . - - - - - - -.... - - - - - - - - - . -

GND2

c-------S-

- Ground

Common ground of high current path.

- Sensing Negative

For connection to remote load, this pin
senses the actual ground of the load itself.
To be connected to GND2 when not used.
This pin is connected to case.

f--------j----------.---------.------ .--

For connection to remote loads this pin allows voltage sensing on the load itself. To be
connected to Va when not used.

- Sensing Positive
1 - - - - . - r--- .. -.----------------

Va

- Output Voltage

Regulated and stabilized DC voltage is available on this pin.
Max output current is 4 A.
The device is protected against short circuit
of this pin to ground or to supply.

P

- Output Voltage Programming

A variable resistor (18 KQ max) connected
between this pin and S + sets the output voltage. ______ ._ _ _ _ _ ._______ .__ _

, - - - - - - - ' - - - - - - - _ .... _--_._----- -

I

3/9

121

GS-R400VB
ELECTRICAL CHARACTERISTICS (Tamb = 25"C unless otherwise specified)
,-------------------------------------------------------,,-------------,--------~

PARAMETER

Min

Test Conditions

Typ

Max

Unit

----------~-----

Va

Output Voltage

Vi=Va+BV

Va

Temperature Stability

10 = lA

5_1

40*

Vi

Input Voltage

10 = lA

10

Output Current

Vi = Va + BV

IOL

Current Limit

Vi = Va + BV

IIsc

Average Input Current

Vi = 46V Output shorted

fs

Switching Frequency

10 = 1A

100

V

f----------------------------j----------------------------- - -- - - - - - - - ----------

Vi = Va + BV

mvrc

0_2/1.6

- - - - - - - - - - - - - - - - ----- ---------------1--------

--------

B

46

V

0.2

4*

A

5

B

A

02

0.4

A

----- - - - - - - - - - - - - - - - - t - - - - - - -

0_5

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ------+--------------+------1
------------------------------- ------------------- ---------------- - - - - - - - - - - - - - - - - - - - - - - - -

KHz

~-------------------------------------------------------

I'1Vo

Efficiency

Va = Va+BV

Line Regulation

10

~--------------------------

fa = 100 Hz

10 = lA

%

2/6

mVIV

4/12

mVIV

20/90

mV/A

25/150

mV

1'110 = 2A (1 to 3A)

Load Regulation

~-------------------------------

V,

75/90

---- ------------------ ----- --- - - - - ---- - ----------- -----------

SVR3upply Voltage Rejection
I'1Vo

la=lA

lA
Vi = Va + 3V to 4BV
=

Ripple Voltage

--------

lOUT = 2A

~------------------------------------------------------------+---

tss

Soft Start Time

VINHL

Low Inhibit Voltage

VINHH

High Inhibit Voltage

Vin = VOUT + 10V

15

f - - - - - - - - - - - - - - - - - - - - - - - - - - - - t - - - - - - - - - - - - - - - - ---- ----------

IINH

Input Current High

tCB

Crow bar Delay Time

ms
O.B

V

5.5

V

- - - -----------------+----------

2.0

500
~A
---------- - - - - - - - ---------------------j----------5
~s

VINH = 5V

----------------------------~------------------+--------------+--------

RCL

Current Limit Resistor

~------------------------

- - - -- - - - - - - ---- ------ --------- -

RSET

Voltage Setting Resistor

VSD

Max Differential Sense Voltage

Vo to S +
S-toGND2
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - ' - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

2,2

KO

- - --------------'-- 1----- -- -

0

___ _ _ _____

_

lB

KO

100

mV

_ _ _ _ _ _ _ _- - - '_ _ _ _ _ _----'

* Maximum Output Current is guaranteed up to Vo = 36V and derated linearly to 3A at Vo = 40V.

4/9

122

GS-R400VB
MOTHER BOARD LAYOUT

I

i

MODULE OPERATION
The GSR400VB is a step down switching mode voltage reg ulator.

current limiting is not used, C. L. pin must be left
open.

Unregulated DC input voltage must be higher than
nominal output voltage by, at least, 3 V. Minimum
input voltage is therefore 8 V for 5.1 V output, while
maximum input voltage is 48 V.

To prevent excessive over current at switch on, a
soft start function is provided. Nominal output voltage is approached gradually in about 15 ms.

Output voltage is adjustable. The maximum current
delivered by the output pin is 4 A and this value can
be programmed by using an external resistor
connected between C.L. pin and the S- pin. A minimum output current of 100 mA is required for proper module operation. In no-load condition, the module still works, but electrical characteristics are
slightly modified vs. specifications. When external

The module can be inhibited by a TTL, NMOS or C
MOS compatible voltage applied to the INH pin.
When this voltage is at high level, the module is switched off : if the inhibit signal goes from high to low
level, the module restarts softly.
Maximum DC voltage applicable to this pin is 15 V.
When remote control (inhibit) of the module is not
used, the INH pin must be connected to GND2.

5/9

123

GS-R400VB
The remote load sensing is another feature provided by the G8-R400VB.
This function is performed by two pins (8+, 8-) that
can monitor the voltage directly across the load
when this load is connected to the module by long
wires: voltage drop on these wires is automatically
compensated.

The case of the module is internally connected to
8-. Therefore, the case must be always isolated
from ground if 8- is used.
The switching frequency of the module is 100 KHz.
To prevent EMI, the module is contained in a metal
box that provides shielding and heat-sink.

Figure 1 : Module connection to remote or nearby loads.

rr:-- ~o+

LOAD~::-S~ __
GND
REMOTE LOAD CONNEC TlON

NEARBY '-DAD CONNECTION

The output voltage can be adjusted in a range from
5.1 to 40 V by use of an external variable resistor as
shown in Fig. 2.
The variable resistor can be substituted by a fixed
resistor; the value of Rx to obtain a fixed output volt-

age Va is calculated according to the formula:
Rx=2.67. (

Vo -1
5.1

)

KQ

where Va can vary from 5.1 to 40 V.

Figure 2 : Output voltage adjustment on G8-R400VB.

o

10 18 K

n.

ma l(

;'-8809

6/9

124

GS-R400VB
The output overcurrent protection limit can be programmed by using an external resistor RL connected between to current limit C.L. pin and S-.

The value can be selected according to the curve
shown in fig. 3.

Figure 3 : Current Limit vs programming resistor value.
G-S96311

-- -f---- - --30 f--

-

---+---I--~jc---

V

20-~ -

f----t-----V--

-

t----~-

- -- -- t-------

101----~
~

-+--+-+--+-+----- -

The G8-R400VB is designed for multiple outputs
power supplies and to this purpose two pins, named
OSCILLATOR and SYNCHRONIZATION are available.

If the unit is a slave, the SYNC input must be connected to the OSC output of the master unit, and the
OSC pin of the slave must be left open as shown in
fig. 4.

When used in a stand alone application or as a master of a multiple outputs unit, these two pins must be
tied together.

Figure 4 : GS-R400VB multiple outputs connection.
,-----------------------~---------------

-

-<>VoUTl

Rx

VI

Vo f----.------oVOUT2

SLAVE
OSC.GS-R400VB

Rx

5VNC_

GND
5-879111

The Oscillator output can drive up to four Synchronous inputs. The layout of the PCB must be accurately checked to avoid noise injection on the Oscil-

lator output line, otherwise the overall power supply
characteristics will be heavily impaired.

7/9

125

GS-R400VB
MODULE PROTECTIONS
Thermal Protection
The module has inside a thermal protection. When
ambient temperature reaches prohibitive values, so
that internal junction temperature of active components reaches 150C, the module is switched off.
Normal operation is restored when internal junction
temperature falls below 130C : this large hysteresis
allows an extremely low frequency intermittent operation (ON - OFF) caused by thermal overload.

mode : if the overload is still present, the module
switches off and the cycle is repeated until the overload condition is removed. The average overload'
current is limited to a safe value for the module itself. Input current during output short circuit is always lower than in regular operation.

Short Circuit Protection

This circuit senses continuously the output volage :
if, for any reason, the output voltage of the module
exceeds by +20% the nominal value (fixed or adjustable), the crow bar protection is activated and it
short circuits the output pin to ground. This protection prevents also damages to module if output pin
is wrongly connected to supply voltage.

The module is protected against occasional and
permanent short circuits of the output pin to ground
or against output current overloads.
When output current exceeds the maximum programmed value the output is automatically disabled.
After a fixed time, the module starts again in a soft

Load Protection
The module protects, by a crow bar circuit, the load
connected to its output against overvoltages.

THERMAL DATA
The thermal resistance module to ambient is about
5C/W. This means that if the internal power dissipation is 10 W, the temperature on the module surface
is about 50C over ambient temperature.

Four holes are provided on the metal box of the module to allow the mounting of this optional external
heat-sink.

According to ambient temperature and/or to power
dissipation, an additional heatsink may be required.

8/9

126

GS-R400VB
TYPICAL APPLICATIONS
Figure 5 : Typical application on the GS-R400VB.

-----0 5V14A

4-.-V-I------VO~___.~----012V/2A
! osc. G5-R400V8 s +

3.6K!\

12

Kil
5-8798/1

ENABLE 0 - - .

The high input voltage range allows both cost saving on 50/60 Hz transformer when the module is
supplied from the main and the possibility to supply
the module with batteries that, according to their
charge status, can show large spread on voltage.

Since II is a high frequency alternating current, the
inductance associated to long input connecting wire
can cause a voltage ripple on point VI that produces
a ripple current across internal capacitor and a power dissipation on r.

The module has, internally, an input filtering capacitor between pin VI and GND1. Therefore at the
switching frequency the equivalent input circuit is as
shown in fig. 6.

When very long connecting wires are used, the input capacitor may be damaged by this power dissipation. For this reason it is suggested to keep input
connecting wires as short as possible.

Figure 6 : Equivalent input circuit of GS-R400VB voltage regulator.
EXTERNAL CONNECTING WIRE

V

rI

I

+

-,
I
I

INTERNAL

I CAPACITOR

I

..J
I
I

_______________ J

127

GS-R400/2

__ F~~iJy
SWITCHING VOLTAGE REGULATOR MODULES
- - -

---~---

----~

-

---~-~---~-~----~------

~-.~-

---~-~

-------._----------------

•
•
•
•
•
•
•
•
•

MTBF IN EXCESS OF 500.000 HOURS
NO EXTERNAL COMPONENTS REQUIRED
PC CARD OR CHASSIS MOUNTABLE
HIGH OUTPUT CURRENT (4 A)
HIGH INPUT VOLTAGE (40 V)
FIXED OUTPUT VOLTAGE (5.1 V; 12 V)
HIGH EFFICIENCY (up to 85 %)
SOFT START
NON-LATCHING SHORT CIRCUIT PROTECTION
• THERMAL PROTECTION
• CROW BAR PROTECTION FOR THE LOAD
• HIGH POWERIVOLUME RATIO (24 Watt/cubic
inch)

I

I

I
I

DESCRIPTION
The GS-R400/2 is a family of SMALL SIZE HIGH
CURRENT HIGH VOLTAGE SWITCHING VOLTAGE REGULATORS.
These step down regulators, shielded for EMI, can
provide local on-card regulation, or be used in central power supply systems, in both professional and
industrial applications.

PRODUCTS FAMILY
- - , - . - - - - ..

-,--.~

Order Number

Output Voltage
5.1 V

GS-R405/2

12 V

GS-R412/2

' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.l. _ _ _ ... _ _ .. _ _ _ _ _ _ _ _...J
~

ABSOLUTE MAXIMUN RATINGS
V,
10

TS'9
Tcop

I~t~~~~::~:tur~range ~----_-_ ---~l.- - ----- t~~
..

Operating case temperature range

'-------------

September 1988

40

J

05-C

- 20 to + 85'C
-------

- - - - --- -

117

129

GS-R400/2
----------------~----------~-

MECHANICAL DIMENSIONS AND CONNECTION DIAGRAM (Bottom view)

508

25 I.

2032

>

Vo

2

127

1

II
tL

ro
-------< ~ -,.-;

----< ~

35

~-

GND2,
I

.I

-.

co

0
U>

('oJ
~

I
1

ro

10.86 5.08

I

VI+- GND~ 1-00 f-

-r

,.,

"'-118.1(,/'

-I

50.S

'-----~---------------~--------------------

PIN FUNCTIONS

-t'-

'---'I--~~---

,----~--

Vi

-~---,--~.--~---~

--~~~-~

PIN
FUNCTION
--~-~--.------. ~~-r_--~~~--------------- Input Voltage
Unregulated DC voltage input. Maximum voltage must not exceed 40 V.

- --~ - -.. ----~-~-----__1

--r_~.-~----~-~~----'----~-

GND,

i-Ground

-~---+--------~---

GND2

I - Ground
- Output Voltage

Common ground for input voltage

- - - - -..... ---------~~ . - -----

Regulated and stabilized DC voltage is available on this pin. Max output current
is 4 A.
The device is protected against short
circuit of this pin to ground or to supply.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
~

_____________ " ..,/ SCS-1lI0MSON
•J,

130

------1

-----------------1

The case is electrically connected to GND.

2/7

-~~-.-~--

Common ground of high current path.

iill~It:L1I@rn~rnlt:m~I@IIl~!:$

GS-R400/2
ELECTRICAL CHARACTERISTICS (T amb

---------1

=

25"C Unless otherwise specified)
GS-R 405/2

TYPE

~;;:i1~";-"o~;~:"::'
Vo
-...
Vi

Temperature
Stability
---

---~----------.--------

10

Vi
,

-

-

10 = 1 A

Output CurrenI'

Vi = 24 V

- ----------

--

Current Limit

lise

Average Input
Current

Min.

Typ.

Max.

5

5_1

5.2

11.5

0_2

-----

Typ.

Max.

12

12.5

---+
V
-

I

..

_-

mv
'C

0.5
--

9

40

16

40

0.1

4

0.1

4

A

8

A

0.2

A

----

----

UNIT

- - - - - - - ------

-

- - - ------

Vi = 40V
Output shorted

V

1···-

--

Vi = Vo + 8 V

-----

t--Min.

-

= 24 V 10 = 1 A

Input Voltage

10l

GS-R 412/2

- -----

5

8

5

0.1

0.2

0.1

--

--""

fs

Switching
Frequency
_. __._-_._...

'1

Efficiency

t;V o

Line Regulation

--

--------------

Vi = 24 V
10 = 2 A
10 = 1 A
Vi = 16to 26 V

t-----. --- - - - - - - -

SVR Supply Voltage
rejection

-------

._- ..

- - - - ---

-

-

-- -

80

85

2

2

4
- - - - -[------

-

--

Load Regulation

Vi = 24 V
10 = 0.5 to 1.5 A

20

Vr

Ripple Voltage

loul = 2 A

25

mVIV

Vn

Noise Voltage

loul = 2 A

:

"

25
-------- - - - - - -

mVIV

I
----+------------_..

~-----

----

%

6

------

t;V o

----

1--

- -[ - - - - -

--

f = 100 Hz
10 = 1 A

kHz

100

100
- -

- t-------

~

mV/A

----

50
f--------35

mV
--.-mV

---- - - - - - -

Ir

Reflected lin

Vi= 24 V
10 = 1 A

60

120

Tr1

Line Transient
recovery time

10= 1 A
Vi = 16 to 26 V

500

500

Tr2

Load Transient
recovery time

Vi = 24 V
Vi = 0.5 to 1.5

100

100

Rlh

Thermal resistance

8

8

C/W

tss

Soft start time

15

25

ms

tCB

Crow bar Delay
Time

5

5

ms

VCB

Crow bar Delay
Threshold

6

14.5

V

mA
-----

I

ms
---

I
i

ms

--

Vin=Voul +10V

--

i
,

• The maximum current can be delivered when lease < 85"C. Forced ventilation or additional heat-sink may be requtrec to
keep Tease < 85"C.

317

131

GS-R400/2
MODULE OPERATION
The GSR400/2 series is a family of step down
switching mode voltage regulators.
Unregulated DC input voltage must be higher
than nominal output voltage by, at least, 4 V.
Minimum input voltage is therefore 9 V for GSR405/2 and maximum input voltage is 40 V for all
the types.
The output voltage is fixed and the maximum current delivered by the output pin is 4A. A minimum
output current of 100 mA is required for proper

module operation. In no-load condition, the module still works, but the electrical characteristics
are slightly modified vs. specifications.
To prevent excessive over current at switch on, a
soft start function is provided. Nominal output
voltage is approached gradually in about 15 to 25
ms.
The switching frequency of the module is 100
KHz. To prevent EMI, the module is contained in
a metal box that provides shielding and heat-sink.

MODULE PROTECTIONS
Thermal Protection
The module is provided with a thermal protection.
When ambient temperature reaches prohibitive
values, so that internal junction temperature of
active components reaches 150°C, the module is
switched off. Normal operation is restored when
internal junction temperature falls below 130°C:
this large hysteresis allows an extremely low frequency intermittent operation (ON - OFF) caused
by thermal overload.
Short Circuit Protection
The module is protected against occasional and
permanent short circuits of the output pin to
ground or against output current overloads.
When the output current exceeds the maximun
allowed value for safe operation, the output is
automatically disabled. After a fixed time, the module starts again in a soft mode: if the overload is

4/7

132

still present, the module switches off and the cycle is repeated until the overload condition is removed.The average overload current is limited to
a safe value for the module itself. Input current
during output short circuit is always lower than in
regular operation.

Load Protection
The module protects, by a crow bar circuit, the
load connected to its output against overvoltages.
This circuit senses continuously the outpout voltage : if, for any reason, the output voltage of the
module exceeds by + 20 % the nominal value,
the crow bar protection is activated and it short
circuits the output pin to ground. This protection
prevents also damages to the module if the output pin is wrongly connected to the supply voltage.

Gi
SGS-ntOMSON
~I i!ilUICOOI!il.Ii©1i"IiIWU©$

GS-R400/2
OPERATING AMBIENT TEMPERATURE RANGE
The GS-R400/2 modules are power devices, i.e.
devices that deliver and dissipate power. The power dissipation is related to the delivered output
power by
Pd = Po

1

(11

By knowing the thermal resistance case to ambient RTH = 8'C / W for natural convection condition, the maximun ambient temperature for a
case maximum temperature of 85'C will be

-1)

Tamb max

= Tcase max - Pd' RTH

i.e.
where

Tamb 5v = 85 - 3.75.8 = 55'C max
11 = efficiency = Ppo
IN

Tamb 12V = 85 - 8.64 = 34'C max

The operating ambient temperature range cannot
be simply defined by numbers because it depends on many conditions that must be previously defined.
On the contrary, the operating case temperature
is well defined and it ranges from - 20 to + 85 'C.
The two extremes are imposed by reliable operation of aluminium electrolytic capacitors that are
housed inside the modules.
From these data, the maximun ambient temperature range can be easily calculated, as show in
the following example:
V IN = 24V VOUT = 5 V ; 12V

This ambient temperature can be increased by lowering the thermal resistance case to ambient.
Various methods can be adopted such as addition of external heat-sink on forced ventilation or
both.
If an external heat-sink with RTH = 10'C/W is
used, the values are modified as follows.
The total thermal resistance case to ambient is
the parallel of the two thermal resistances
RTH TOT = RTH CASE' RTH HEAT-SINK = 4's"CIW
RTH CASE + RTH HEAT-SINK
Tamb 5V

= 68'C max Tamb 12V = 56'C max

louT = 3A.

The dissipated powers of GS-R405/2 and GSR412/2 are respectively:
Pd 5V = 3.75W

Pd12V = 6.4W

5/7

133

GS-R400/2
---------------------------TYPICAL APPLICATIONS
The high input voltage range allows both cost saving on 50/60 Hz transformer when the module is
supplied from the mains, and the possibility to

supply the module with batteries that, according
to their charge status, can show large spread on
voltage.

Figure 1 - A Typical Application of GS-R400/2 Voltage Regulator
•....

j

- - - - ..

----------~

Vo
VI

GS R400/2
GND2

GND1
5-8799
----_._--_.---------------------------

The module has, internally, an input filtering capacitor between pin VI and GND1. Therefore, at

the switching frequency the equivalent input circuit is as shown in fig. 2.

Figure 2 - Equivalent Input Circuit of GS-R400/2 Voltage Regulator

--------------_.

EXTERNAL CONNEC TlNG WIRE

+
r-

"I
I
INTERNAL
CAPACITOR

L
5-6939

6/7

134

GS-R400/2
Since II is a high frequency alternating current,
the inductance associated to long input connecting wire can cause a voltage ripple on point VI
that produces a ripple current across internal capacitor and a power dissipation on r.

When very long connecting wires are used, the
input capacitor may be damaged by this power
dissipation. For this reason it is suggested to
keep input connecting wires as short as possible.

EFFECIENCY VS. INPUT VOLTAGE & OUTPUT CURRENT

(,-5965

'1

("/" )

r--

1---

- - ~-

3A
_.

80

------~

t-

-

~~

;

~K~ ~

" ........, ~

,

70

"'"

60

50

GS-R405/2

a

10

30

20

'1
("/")

1-

-

t--..

-- - - -

3A

85

.-

"~-

_.

..-'~

1A·--;

I

75

!

~~
~

GS-R412/2

-

_.-

65
-

55

a

I
10

20

30

717

135

GS-RS1212
TRIPLE OUTPUT SWITCHING VOLTAGE
REGULATOR MODULE
---_._---_._---_._._.
•
•
•
•
•
•
•
•
•
•

MTBF IN EXCESS OF 200.000 HOURS
NO EXTERNAL COMPONENTS REQUIRED
PC CARD OR CHASSIS MOUNTABLE
HIGH OUTPUT CURRENT (3.5 A on 5 V output)
HIGH INPUT VOLTAGE (40 V)
TWO 12 V; 0.15 A ISOLATED OUTPUTS
HIGH EFFICIENCY
SOFT START
RESET OUTPUT
NON-LATCHING SHORT CIRCUIT PROTECTION
• THERMAL PROTECTION
• CROW BAR PROTECTION FOR THE LOAD

DESCRIPTION
The GS-R51212 is a triple output HIGH CURRENT
HIGH VOLTAGE SWITCHING VOLTAGE REGULATOR that provides +5 V and two isolated 12 V
outputs.
This step down regulator shielded for EMI, provides
local on-card regulation. The very large input voltage range allows flexibility in both professional and
industrial applications.

ORDER CODE: GS-R51212

CONNECTION DIAGRAM (top view)

RT
GND3
V03
GND2
V02
GNDOUT

'VOl

:.
"

~

~

I~

GNDIN

~

-"I

,"'I
~
~

5-8803

- - - - - -----_.

September 198_8_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

1/9

137

GS-RS1212

[

ABSOLUTE MAXIMUM RATINGS
--

-----------

VI

DC input voltage

IRT

Reset output sink current

T5 tg

Storage temperature range

Tcop

Operating case temperature range

-

L

5

c·

85.5

2/9

138

----- L'9'J
'},

SCS-THOMSON

~~©L'iI@~~~©~L'iI@IIl~©$

-0-------

- 40 to + 105'.C
- 20 to + 85'C

MECHANICAL DATA (dimensions in mm)

_ _.. _ .

40 V
20 mA

01)~/l

GS-R51212
PIN FUNCTIONS
--"----"-"

FUNCTION

PIN

RT
----.

-----"

V,
GNDIN
GNDoUT

Reset output is high when output voltage reaches nominal value (5.1 V)
and it is gener ated with a fixed 100 ms delay. A proper resistor (270 n
min) must be connected between this pin and V01

Reset Output

-- - - - - - - - - - - - - - -

Ground

1-----Ground
-

V01

---. - - -

--

5 V Output Voltage

---------

V02

c----GND2

GND3

Commongrou nd of high current path. Thecase of the module isconnected to this pin.
---------

Regulated and stabilized DC voltage is available on this pin. Max output current is 3.5 A.
.
The device is protected against short circuit of this pin to ground or to I
supply.
Regulated and stabilized 12 V DC output at 150 mA max. current referred to GND2.
This output ca n float ± 200 V in respect to GNDoUT and GND3.

------" -""-

------- ---

Ground

Reference gro und for V02 output.

12 V Output Voltage

~
-"-"-

Common grou nd for input voltage.
------

------"

12 V Output Voltage

c------- - - - - " " - _ . V03

- - -

Unregulated D C voltage input. Maximum voltage must not exceed 40 V.

Input Voltage

~--.--

-----

'.

- - - - - - - - - ----.----

----.

-

J
I

-- ---- --" -- ----- --------------- ------- --1

Regulated and stabilized 12 V DC output at 150 mA max. current referred to GND3.
This output ca n float ± 200 V in respect to GNDoUT and GND2.

" - - _ .... _ . - - - . _ - " -

Ground

--~--

----

I

- - . " - - -- -

-- -

- - - - - --------- - - - - - - - - - " - - - - - - - -

I

----,

I Reference ground for V03 output.

- - - - " - - - " - - - - - - - - - - - -------------------

I

I
---------------

--------~

MOTHER BOARD LAYOUT Printed Circuit Drilling (components side).

Printed Circuit Drilling (component side).
- . " - - - -.." - .

~------------------------------""--.--- ..

3/9

139

GS-RS1212
ELECTRICAL CHARACTERISTICS (Tamb = 25"C unless otherwise specified)
--

Test Conditions

Min

Typ

Max

Unit

Output Voltage

Vi = 24 VIol = 2.5 A

4.95

5.1

5.2

V

V02 Output Voltage

Vi = 24 V 102 = 0.1 A

*

11.5

12.5

V

V03 Output Voltage

Vi = 24 V 103 = 0.1 A

*

11.5

12.5

V

PARAMETER

VOl

Vo

Temperature Stability

Vi

Input Voltage

101

Output Current

Vi = 24 V

102

Output Current

Vi =24 V

*

103

Output Current

Vi = 24 V

*

Ise

Average Input Current

Vi = 40 V VOUtl = 0 V

Ise

Average Input Current

Vi = 40 V V OU11/213 = 0 V

Ir

Reflected lin

fs

Switching Frequency

All Outputs

mVI"C

0.2
9.0

40

----------

0.5

--

A

.15

A

.15

A
A

------_..- --

Vi = 24 Viol = 2.5 A

V

3.5

0.2

....

-

0.4

A

160

mA

100

KHz

75

%
mV/v

102 = 0.1A 103 = 0.1 A

11

Efficiency

---

Vi = 24 VIOl = 2.5 A
102 = 0.1 A 103= 0.1 A

!!.Vo Line Regulation

101 = 2.5 A VI = 15 to 25 V
102 = 0.1 A 103 = 0.1 A

2

!!.Vo Load Regulation

Vi = 24 Viol = .5 to 2.5 A

20

mV/A

Vi = 24 V 102 = .05 to .1 A

1

mV/A

Vi = 24 V 103 = .05 to .1 A

1

mV/A

50/60Hz

4

mV/v

SVR Supply Rejection

------

---

-

-

-

."-------

Vr

Ripple Voltage

Vi = 24 Viol = 2.5 A

30

mV

Vn

Noise Voltage

Vi = 24 Viol = 2.5 A

40

mV

Ireset = 5mA

0.2

V

100

ms

500

J.ls

100

Irh

Reset leakage Current

Vrl

Reset Low Level

Trd

Reset Delay Time

Trl

Line Transient Recovery Time

101 = 2.5 A Vi = 15 to 35 V

Tr2

Load Transient Recovery Time

Vi = 24 V 10 = .5 to 2.5 A

Rth

Thermal Resistance

• loutt = 0.5 A.

4/9

140

--

---

----

~

200

J.ls

5

"CIW

GS-RS1212
MODULE OPERATION
The GS-R51212 is a triple output switching mode
voltage regulator.
Unregulated DC input voltage must be higher than
nominal output voltage by, at least, 4V. Minimum input voltage is therefore 9 V while maximum input
voltage is 40 V.

The main output voltage is 5V and the maximum
current delivered is 3.5 A. A minimum output current
of 500 mA is required for proper module operation.
The current available on the 12 Volt outputs depends on the current delivered by the main output
and the value of the input voltage.

Figure 1 : Current available from 12 V output vs. input voltage and 5 V output current.

-I
I

--r----r-

100

!
I

I

I

ilOliT SECONDARY: OuTPlif

ivs

50

~---+___
l
I
.

"",&IOUT5VI

--to

~-

.

I
L
i

i

I

,

r

20

To prevent excessive over current at switch on, a
soft start function is provided. Nominal output voltage is approached gradually in about 15 ms.
The switching frequency of the module is 100 KHz.
To prevent EMI, the module is contained in a metal
box that provides shielding and heat-sink.
The RESET output is an auxiliary function useful to
reset or inhibit microprocessors when the output
voltage, at switch on and off, reaches a prefixed value of 4.9 to 5.1 V or when the output voltage, for

any reason, drops below nominal value by more
than 100 mV. In any case the minimum falling threshold value is 4.75 V or higher and the reset output
voltage is generated with a fixed delay of 100 ms.
This is an open collector output to guarantee maximum flexibility.
Time delay of the reset function also rejects wrong
information caused by occasional spikes generated
during switch on and off.

5/9

141

I

GS-R51212
MODULE OPERATION (continued)
Figure 2 : Reset as a function of output voltage and time.

r· -.- - - .-. -. - .- --.,,--- --'-I

OUTPUT NOW
STABLE,RESET
GOES HIGH

AN INTERRUPTION
OF SUPPLY CAUSES
RESET OF MICRO

IOOmV OF
HVSTERESIS
RESET
THRESHOLD-

_j ____ v_-_~_-_-_-_-_-_-_~
__

I

AT POWER DOWN
MICRO J5 INHIBITED
IMMEDIATELV

-------

MONITORED
VOLTAGE

I

I

I
I
I I
I

I

RESET
OUTPUT

DELAY

DELAY

5-7466/1

------"- - - - - - - - -

6/9

142

GS-RS1212
MODULE PROTECTIONS
Thermal protection
The module has inside a thermal protection. When
ambient temperature reaches prohibitive values,
so that internal junction temperature to active
components reaches 1S0°C, the module is
switched off. Normal operation is restored when
internal junction temperature falls below 130°C:
this large hysteresis allows an extremely low frequency intermittent operation (ON-OFF) caused
by thermal overload
Short circuit protection
The module is protected against occasional and
permanent short circuits of the·output pins to their
respective grounds or against output current overloads.
When the S V output current exceed the maximum
allowed value for safe operation, the output is
automatically disabled. After a fixed time, the
module starts again in a soft mode: if the overload
is still present, the module switches off and the
cycle is repeated until the overload condition is
removed. The average overload current is limited
to a safe value for the module itself. Input current
during output short circuit is always lower than in
regular operation.
Load protection
The module protects, by a crow bar circuit, the load
connected to the S V output against overvoltages.
This circuit senses continuously the output voltage: if, for any reason, the output voltage of the
module exceeds 6 V, the crow bar protection is
activated and it short circuits the output pin to
ground.

THERMAL DATA
The thermal resistance module to ambient is about
SOC/W. This means that if the internal power dissipation is 10 W, the temperature of the module
surface is about SO°C over ambient temperature.
According to ambient temperature and/or to power
dissipation, an additional heat-sink may be required. Four holes are provided on the metal box of
the module to allow this mounting of this optional
external heat-sink.

TYPICAL APPLICATION
The high input voltage range allows both cost
saving on SO/60 Hz transformer when the module
is supplied from the main and the possibility to
supply the module with batteries that, according to
their charge status, can show large spread on
Voltage.
The module has, internally, an input filtering capacitor between pin VI and GND 1 . At a high switching frequency the equivalent input circuit is as
shown in Fig. 2.
Since II is a high frequency alternating current, the
inductance associated to long input connecting
wire can cause a voltage ripple on point. VI that
produces a ripple current across internal capacitor
and a power dissipation on r.
When very long connecting wires are used, the
input capacitor may be damaged by this power
dissipation. For this reason it is suggested to keep
input connecting wires as short as possible.

7/9

143

GS-RS1212
-----~---"------------~--~---"---"

---

Figure 3 : Equivalent input circuit of GS-RS1212 voltage regulator.

EXTERNAL CONNEC TlNG WIRE

-,
I
INTERNAL
CAPACITOR

L
5-69]9

~----------------{)-

Figure 4 : GS-RS1212 typical applications.

DIGITAL
BOARD
VOl

0-

GNDOUT

GNO(OIGIU

GND 2 GND(ANAl(}{,)

~-l

GS-R51212
V02
().'"----~-

~O

GN03

·\2V

1

-

i

-12V

I ANALOG
: BOARD
I
S 880/1

0----

VOl
V,

GNDOUT
V,N

G5-R51212

I

GN02
v03
VOl

C>-

(,NO

GNO)

.",--

~

G""---

--

LOGIC BOARD
_

~v

l-

-11V

OT

I

L
8/9

144

RESET
-~,-

'- _J

,)-BIlOll)

II

GS-R51212
EFFICIENCY VS. INPUT VOLTAGE

~r---~--r--.---'---'---r--~~
(o/,)

80

-r
70

50 - __-L-_+-_

50

o

10

20

30

9/9
- - - - -

145

I
I

I
I
I
I
I
I

I
I
I

I
I
I
I
I
I
I
I

I
I
I

I
I
I
I
I
I
I
I
I

I
I
I

I
I
I
I
I

I
I
I

I
I
I
I
I
I
I
I
I

I
I
I

I
I
I
I
I

I
I
I

I
I
I
I

I
I
I
I
I

I
I
I

I
I
I
I
I
I
I
I

I
I
I

I
I
I
I

L149
4A LINEAR DRIVER
- - - - - - - - - - - - - - - - - - - - - - . - _ . - - - - - - - _ . ._ - - - - - - -

•
•
•
•
•
•
•

1-

HIGH OUTPUT CURRENT (4A peak)
HIGH CURRENT GAIN (10.000 typ.)
OPERATION UP TO ± 20 V
THERMAL PROTECTION
SHORT CIRCUIT PROTECTION
OPERATION WITHIN SOA
HIGH SLEW-RATE (30 VI J.ls)

Pentawatl'"

The L 149 is a general purpose power booster in
Pentawatt® package consisting of a quasi-complementary darlington output stage with the associated
biasing system an inhibit facility.
The device is particularly suited for use with an operational amplifier inside a closed loop configuration
to increase output current.

ABSOLUTE MAXIMUM RATINGS

'~J;':'b4 _~=
,

Vs

I

'- --""--I

______ P~rameter

Value

___ _

± 20

Supply Voltage
Input\loltage

___ ---- --- - -- ---- ---

1\l5-=V41_UPP~ Power Transistor VCE

40

V

0'4 - V3 _ Lower Power Transistor VCE

40

V

3

A

I
I

1100

V 1NH

I'

I

r
,

DC Output Current
Peak Output Current (internally limited)
Input Inhibit Voltage

-T:~tJ ::~:~:;~::~:tl;~T~~p:~~u:~' .--- - - - .

4

A

- Vs + 5

V

-= \/s :-~~ .. _._+--- V
25
W
- 40 to 150

~

°C

TEST CIRCUIT

>.---.......---{) au T

- - - - - - - - - _ . _ - - _ . _ . _ - - - - - _ . _ - - - ..- - . - - - - - - - - -

September 1988

1/4

147

L149
CONNECTION DIAGRAM (top view)

>

5

0
/

4

OUTPUT

>

3

(tab connected to pin 3)

+Vs
~

- Vs

2

> INPUT

1

INHIBIT
5- 4025

SCHEMATIC DIAGRAM

INPUT

____________

2/4

148

~

~~~~.03

__
40_'8_"_ _ _ _ _ _ _ _ _ _ _

-VS _ _ _ _ _ _ _ _

J

L149
THERMAL DATA
Thermal resistance junction-case

Rthj-case

ELECTRICAL CHARACTERISTICS (Tj = 25°C, Vs = ± 16V)

:;=~--s-u-p-p--:-a-:~:-I-~-a-:--te-e-r-=r--~ __--_-;--_e_~_t_cond~~~ons
r--Id

hFE

-- -

--

---

,--------,
Min.

TY;! ::: -~~~t~

----

Quiescent drain current

Vs = ± 16V

30

Input current

Vs = ± 16V

200

mA
400

J.1A

- - - - - - . ------------- ....-- ---_.. _---------_ .. -----+-_·_--+----+---+----1
DC current gain
Vs = ± 16V
10 = 3A
6000 10000
-----_.

-----

Gv

Voltage gain

Vs =±16V

VCEsat

Saturation voltage
(for each transistor)

10 = 3A

3.5

Vs =±16V

0.3

10 = 1.5A
------- - - - - - -----.- --------t-----t---+--r-

1-------

,

V

- - - -

Vas

Input offset voltage

VINH

Inhibit input voltage (pins 1-3)

1----------

V

._----+---_ .. _-- - - - - - - - _..- -----+----+---+----j
ON condition

± 0.3

± 1.8

OFF condition
--------------j------.-.--------

RINH

Inhibit input resistance

SR

Slew rate

V

---------+---1-----+-----1

i

2.0

KQ

30

VI J.1S

--------------t---+----+-------- - c......B_ _ _
Po_w_e_r_b_a_n_d_w_id_t_h_ _ _ _-'-_V_a_=..±__ 1OV, d = 1 %, RL = 8n
2~~__ L_____ KHz
APPLICATION INFORMATION
Figure 1 : High slew-rate power operational amplifier (SR = 13VI J.1s).

.......---"1'--'O·Vs

r---~---------

RijSfl

RL

O.1,.,F

C6

~---------~---~O-V5

S-393411

3/4

149

L149
Figure 2 : Maximum saturation voltage vs. output
current.

Figure 3 : Current limiting characteristics ..

G" 360911

VCE(sat )
(V)

c,/

/

/

-If-

V

·2

- . -.
·4
·6
12
-36

Figure 4 : Supply voltage rejection vs. frequency.

18
-30

24
-24

30
-1 B

36
-12

Figure 5 : Distortion vs. output power
(f = 1 KHz).

r:

G 3608

SVR

I

(dB)

I

Iii

RohW,

! I
--L I III ,.-

Vs! lav

30

I

40

I

Jv r I

-

vOl

50

60 . -

R L=4Jl
Vs:32V

1-'-1-I

, I

./

i ,.I I

H

i rt U
I

10

M

i tITIII

l-

-

I

.Im
ri ~,i

10

-

H·'

Rl = 8a

-~

20

-

-

10'

--

10'

f'
~1j

--

t~

t(Hz)

Figure 6 : Distortion vs. output power
(f = 10 KHz).

Figure 7: Output power vs. supply voltage.

,4

,.
21

15

O.'~_,
.. _"
~.
0,01 L--.....L...J....L.LJ..J.J...jJ_...J.-..l...1....L.J..I.uI.l.J
10

4/4

150

"

L165
3A POWER OPERATIONAL AMPLIFIER
• OUTPUT CURRENT UP TO 3A
• lARGE COMMON-MODE AND DIFFERENTIAL MODE RANGES
• SOA PROTECTION
• THERMAL PROTECTION
• ± 18V SUPPLY
The l165 is a monolithic integrated circuit in Pentawatt® package, intended for use as power operational amplifier in a wide range of applications,
including servo amplifiers and power supplies. The
high gain and high output power capability provide

superior performance wherever an operational
amplifier/power booster combination is required.

Pentawatt@

ORDER CODE: l165V

ABSOLUTE MAXIMUM RATINGS

~
s

Vs - V4
V4 - V3
Vi

I

Supply voltage-

±15

V

36

Vi

Differential input voltage

10

Peak output current (internally limited)
Power dissipation at Tease

Tstg, TI

~

36

Lower power transistor VCE

I Input voltage

Ptot

Vs

±18

Upper power transistor VCE

~

90'C

Storage and junction temperature

APPLICATION CIRCUITS
Figure 1 : Gain> 10.

I

3.5

A

20

W

-40 to 150

'C

Figure 2 : Unity gain configuration.

r--

0.1 jJF

I

lN400l

0.22,uF

0.22pF

lN400l

O.1,lJF

1

-Vs

5-43"'3
S-td42

Rl

____ 1
September1988

"-------_._--------------

-----

...-

1/7

--

151

L165
CONNECTION DIAGRAM
(top view)

l

o
~~-.
~-

I
LTab connected

__

5

+Ys

4

OUTPUT

~

:::ERTING INPUT

1

NON INVERTING INPUT
5-262812

to pin 3

SCHEMATIC DIAGRAM

1
~--------~---------.

4

-0

THERMAL DATA
Thermal resistance junction-case

217

152

max

3

L165
ELECTRICAL CHARACTERISTICS (Vs = ± 15 V, TI = 25 'C unless otherwise specified)
-

,-~

-~-

---,----~-

-----,---

,-----~

Symbol~~! 3.5A).

IOK.ll
~------~

])Kfi 2-'•

•2*

r:-~

.7

D.221Jf

UKfirl.

-LT-

R,

:c
L 165

10Kfi

01 to 04: I
VFS 1.2@ I ~ 4A
trr:s: 500 ns
Note: The input voltage level is compatible with L291 (5·8IT O/A converter).

The transfer function is : ~
V,

=

R4
Rx R3

517

155

L165
Figure 11 : High current tracking regulator.

Figure 12 : Bidirectional speed control of DC
motor (Compensation networks not shown).

+15V

·V.

0----1r------'--1

r--+-~----{)

",

0.'.'
2A
DC MOTOR

O.1 ....

rt---<=_ _--,

~--ot-~--O."

.,,0-------'''------'

s- t. 370, 1

PI

A: for±185V;5±32
Note: V, must be chosen in order to verify
2 V;- V,536V
B: forV;5±18V

01,02:

I

VF51.2V@ 1=2A

trr 5 500 ns

Figure 13 : Split power supply.
cr--~-,---~-----~--0+Vo

Vi

+Bto+36V

cr~~~---~-----~~--o-Vo

5-537911

6/7

156

L165
Figure 14 : Power squarewave oscillator with independent adjustments for frequency and duty-cycle.
Rt

>"~-----1~UVout

nn

tIl

PI : duty·cycle adjust
P2 : frequency adjust (f = 700 Hz with Cl = 10 nF. P2
Kll. f = 25 Hz with Cl = 10 nF. P2 = 0)

= 100

5-53B1

7/7

157

L200
ADJUSTABLE VOLTAGE AND CURRENT REGULATOR
• ADJUSTABLE OUTPUT CURRENT UP TO 2 A
(GUARANTEED UP TO Tj = 150 ec)
• ADJUSTABLE OUTPUT VOLTAGE DOWN TO
2.85 V
• INPUT OVER VOL TAGE PROTECTION (UP TO
60 V, 10 ms)
• SHORT CIRCUIT PROTECTION
• OUTPUT TRANSISTOR S.O.A. PROTECTION
• THERMAL OVERLOAD PROTECTION
• LOW BIAS CURRENT ON REGULATION PIN
• LOW STANDBY CURRENT DRAIN

metal case. Current limiting, power limiting, thermal shutdown and input overvoltage protection (up
to 60 V) make the L200 virtually blow-out proof.
The L200 can be used to replace fixed voltage regulators when high output voltage precision is required and eliminates the need to stock a range of
fixed voltage regulators.

. . . . . . .·.··.·.e
.
,
e.
"

Pentawatt'"

TO-3 (4 lead)

DESCRIPTION
The L200 is a monolithic integrated circuit for voltage and current pro9,!;ammable regulation. It is
available in Pentawatt R package or 4-lead TO-3
ABSOLUTE MAXIMUM RATINGS

I~----- val~e=Iunit_

Parameter .. _____". - -

Symbol

~----~-----------------~-

V;

DC Input Voltage

V;

Peak Input Voltage (10 ms)

___.___ ._________,__, _

I--_~t_:_t--+_~~::rt ~i~~n

_ _ ..___

To p

40

v

:

60

v

----------------.----.---- --'-,----------------+----1

Dropout Voltage

Tstg

,

I

i Storage Temperature

~

_____

_i--- _______3_2________f-_V_

---==-~-.-----L :~::;~:::~ : : : :
I

-55to 150

I

-

25 to 150

'C

I

-

55 to 150

'c

Operating Junction Temperature for L200C

'-------'-----

for L200

-----------------.----------------~----

'c

--------~-----

THERMAL DATA

II
I

,

TO-3

--------,

Pentawatt'"

Rth j-case

Thermal Resistance Junction-case

Max

4'CIW

3 'C/W

Rth}amb

Thermal Resistance Junction-ambient

Max

35 'C/W

50 'C/W

September 1988

1/9

159

L200- - - - - CONNECTION DIAGRAMS AND ORDER CODES (top views)

5-238'11 Z
5-2555/3

I_j::

_t

BLOCK DIAGRAM

1

___

IN~I~-I-I

~

\CURRENT

/LiMITING

I
"--,.._-'

OUTPUT

~ ---..I----+--iICOMPARATOR ~ 2

l__
GROUND

s· 3926

APPLICATION CIRCUITS
Figure 1 : Programmable Voltage Regulator
with Current Limiting.

Figure 2 : Programmable Current Regulator.
R

R3

10 = Vs

~2

R

L 200

------------

2/9

160

L200
SCHEMATIC DIAGRAM

1

I,R2Q

01

D2

Iter
J

,

R6

'r •

<3.'

ELECTRICAL CHARACTERISTICS (Tamb

@imb;ir-'

=

25 'C, unless otherwise specified)

2e_~conditions_J

Parameter

Typ·T~~x.

Min.

Tun~

VOLTAGE REGULATION LOOP

I :~-I ~~:~i~~:'~;:'"''''" "--I ~ ;'::

~-'~----~'--'"

__ 1~2. . .~_92
I

B= 1 MHz

---------

---

Vo

-------------

---------

Output Voltage Range
Voltage Load Regulation
(note 1)
-~---

..

80

pV

, ,,10 =
I ,,10 =

36

2.85

2A

0.15

1.5 A

0.1

09

- - . - - - -... ---~---

I Line Regulation

Vo = 5 V

t-.Vo

'

V,=8to18V

SVR

I Supply Voltage Rejection

Vo = 5 V

48

48

and 5
_. ._ - - -

-----

Vi = 20 V

10 = 10 mA

1%

1_%

dB_

'I

60

1 - - - - - + - - - - _ - - - - - - - + - - - - . - - - - - - - - -"------+-t-.V,_o
Droupout Voltage between Pins 1 10 = 1.5 A
"Vo <0 2 %
-----------

V

-f __ I

60

10 = 500 mA

"Vi = 10V pp
f = 100 Hz (note 2)

Reference Voltage (pin 4)

I

---------

10 = 10 mA

"V,

Vref

lmAj

10 = 10 mA

2.64
i __

~

J?:~

I

I

dB

::6J: ~
3/9
161

L200
ELECTRICAL CHARACTERISTICS (continued)
,------,-------~-----~---~~-,-------

Symbol

Parameter

---~---~-

~

~~.---------

Test conditions

..

---,----,-----~--,

Min.

Typ.

Max.

Unit

-~------------.-----+----------------j---~+---+-----+-----1

!1Vref

Average Temperature Coefficient
of Reference Voltage

Vi = 20 V

10 = 10 mA
for Tf = - 25 to 125 ·C

-0.25

·1.5
f-_1_4_ _f--B
..i_a_s_C_u_rr_e_n_ta_t_p_i_n_4_ _ _ _---cIf-_____f_or_T__I_=_1_25__
tO_1_5_0_.C_____ -I___3_ _t-_ _-+__--1
'I

Average Temperature
Coefficient (pin 4)

Zo

\ Output Impedance

CURRENT REGULATION LOOP
vsc

____ ..__

2:

jEi'
Vi = 10 V

Current Limit Sense Voltage
between Pins 5 and 2

!1 Vsc
!1T·Vsc

15 = 100 mA

__0 ______ - - - - - - - -

'Average Temperature

----·~-,----r

Vo = Vref
0.38

____________________________

---

'

0.45
0.52
- _ . _ -t-0.03

.--~.-~.-.-.-~------+------------

'1

Vi= 10 V
10=0.5A
10 = 1 A
10 = 1.5 A

Peak Short Circuit Current

Isc

Vi-Vo= 14V
(pins 2 and 5 short circuited)

~L ___ ,--_
I

_
3.6

A load step of 2 A can be applied provided that input-output differential voltage is lower than 20 V (see Figure 3).
The same performance can be maintained at higher output levels if a bypassing capacitor is provided between pins 2 and 4.

Figure 3 : Typical Safe Operating Area
Protection.

Jt

l o(max )
(A)

.+.

Figure 4 : Quiescent Current vs. Supply
Voltage.
&-286011

(~~) H+H++-H+t--1++H

~v:=2~~S J: ~t=

Tj;2~·C

duty- cycle =1 0 1.

=~~c

JfuJtW;

1~~~~~A~~~(T~=~soec )
-

4.4

H-+-+-l-++-H-+--Hr++-H-+-+-l-+-l

4.2

4.0

H--+I+-l-++-H-+--Hr++-H-+--H-+-I

3.8

H-I--H-++-H-+--Hr++-H-+--H-+-I

3.6

Hl+-+-l-++-H-+--Hr++-H-+--H-+-I

3.4

H-+--Hr++-H-+-+-'f-++-H +-H-+-I

-

10

162

%
%
%

0.9

--~---.----+------

4/9

%rC

Coefficient of Vsc
Current Load Regulation

Note 1
Note 2:

V

20

10

20

30

A

L200
Figure 5 : Quiescent Current vs. Junction
Voltage.

'd

-

1

-

" t-... f',.
-

-

I--

........

I

,

~ .........

-

~ I--.

120

110

-40

--

..

I

-l-

-

.-

.-1--

I-

0.8

Q4

-- -

t

-

j

.-

Tj (IIC)

Figure 7 : Output Noise Voltage vs. Output
Voltage.

1

.-

·-f~

!

I

-

c--

-I--- .-

- -

l,~

Tf~t-IFI---~

--

-

~

=seefW

I ! ; 1-

-

'--

0-

Rth j -amb

".

--b,~1--- . -

86
r-~~~

j.). 1.. rTlr- '-

-

Vo =Vref

1

~

I.

(rnA)

Vi = ZOv

_.

~-

C.-28'6

T1

~

(mA)

Figure 6 : Quiescent Current vs. Output
Current.

1.6

12

Figure 8 : Output Noise Voltage vs.
Frequency.

(,1850

G-28Jl

t-

"N

)1-- 1.6 f-1.4

j

I--

III
B=I00Hz
Yo=Yref

.-

'.-

1

1.2

f--

0.8

I--

0.6

I--

0.4

I--

0.2

f--

I'..

10

15

Vo(V)

Figure 9 : Reference Voltage vs. Junction
Temperature.

1J=15O·
1·=75·C

I'

T-=2S·C

_.

H
10'

10'

10'

f (Hz)

Figure 10 : Voltage Load Regulation vs.
Junction Temperature.

(;-181.8

'ref
(mY)

I--

-LJ-

f--

""ref

f--

Vi ",lOY
-

1

10 =IOrnA

I-- - I--

27110

1'---

2160

Yo

I

i

I-

.

2740

-

I---

I--

-I- . - 2720

I--- I--- -

'\
~

i'\
-

-~

-

I--

-

-I
-

16

.-

.1-- _

I

-I-

_.

I--I-- 12

--

1-

/--

I--

-+
+

---

lo=~ J...--

V

-~__

t- I~
J...t-- t-

I-.~C_Io

l - I-

~

.-

1---

-

.

- 1-

-}- ~l

[
va =5.5v

I---

L
I

f

"0

(mY)

1--1- - -

1--

1.5A,-- ,.:..~

-.,.-

I--- e I--- I--- /-.

--

IAI-- ,--I- f-·

F

-

1-I---

I-- . - - I - -

2700
-40

40

80

-40

80

5/9

163

L200
Figure 12 : Dropout Voltage vs. Junction
Temperature.

Figure 11 : Supply Voltage Rejection vs.
Frequency.
SVR
(dB)

,-

~o~~I[l1j

-

Vi ",15VOC .. 2VRMS
10 ",lOrnA

85

4.5

80

f-"

75

3.5

70

2.5
65

60

1.5

55

,

50

.. ..

,

,

10'

10

,"

'"10'

,

..

0.5

-40

Figure 13 : Output Impedance vs. Frequency.

40

80

Figure 14 : Output Impedance vs. Output
Current.
Zo

Hi

(n)

1~0~4~~+-+~1~
flV

,,3V

1000

500 ~-H--f'.tc+

1.5

0.5

Vo

G 1861/1

r

~.

40

1----·---····-·.

Figure 16 : Load Transient Response.

Figure 15 : Voltage Transient Response.
(mV )

10 (A)

Ht

V;

V)

20
-

1

10

=1A

-I

--I-."""'---l-+--

-20

i
0

C2-L.= 0

0

I"~'W~

~o =S.5V • Vi =10V

~

0
I

o

6/9

164

1

Z

3

4

5

6

7

8

9

tIps)

r'::L

Vj=10V

I

10=lOmAtolA

I

--:::::7~F

Ht-,,_r..t-l-_--t+----

~,~s ;;;s ~s
1

5-2386/1

L200
Figure 17 : Load Transient Response.

Figure 18 : Current Limit Sense Voltage vs.
Junction Temperature.

Vi '" IOV
lo:lOmA lo2A

LI"i"+-+--Co = l}JF
Co :O.047pF

5-138811

-5-5382

0

Figure 21 : High Current Voltage Regulator
with Short Circuit Protection.

Figure 22 : Digitally Selected Regulator with
Inhibit.

,---------------------

lkU

I

Vi

L 200

O.22IJF R1

R2

1
5-]51,3f2

7/9

165

L200
Figure 23 : Programmable Voltage and Current Regulator.
Ir-------~:::::::::;::::::::+_------~--tR~3~.~~.--~--_o Vo
0.1 n
Rt

R2

, KIl.

vo",Vrefto26V

470 Il.

IO=35mAto1.SA

A
·Pt: CURRENT REGULATION
P2: VOLTAGE REGULATION

Note

:

5 - 41 25 {2

Connecting point A to a negative voltage (for example - 3 Vila rnA) it is possible to extend the output voltage range down to a V and
to obtain the current limiting down to this level (output short-circuit condition).

Figure 24 : High Current Regulator with NPN
Pass Transistor.

Figure 25 : High Current Tracking Regulator.

Rsc

+Vj

+Vj

1
at

0-----.,----''-1

I-'--+-~r__---o

.'.

O.1"F

I
Vo

I
Q.22pF
5-290411

>"------'-----'----{)-'.

1
A: /or±18<;V;<;±32
Note - V, must be chosen in order to verify 2V; - V, <; 36 V

8/9

166

L200
Figure 26 : High Input and Output Voltage.

~
BDX53

1l

1

L 200

~~

2Kfi

3
36V

Q.22J..1F

I

~

T

~O,uF

~

-Vz

Vj(malt)" 56v+ Vz

:~jII
RI

Figure 27 : Constant Current Battery Charger.

:ll

5-291112

L 200

,

~.,..

01

i02

r ..L

1
1
1

Vi

R2

(12V)

i
1

1

R1

- _ . _ - - ............
5-2912/1

J

The resistors R, and R2 determine the final charging voltage and
Rsc the initial charging current. 0, prevents discharge of the battery
throught the regulator.
The resistor RL limits the reverse currents through the regulator
(which should be 100 mA max) when the battery is accidentally reverse connected. If RL is in series with a bulb of 12 V/50 mA rating

this will indicate incorrect connection.

Figure 28 : 30 W Motor Speed Control.

Figure 29 : Low Turn on.
=

t

5

on

C Vo R

0.45

, Kll.

I
Figure 30 : Light Controller.
R3

s - 1..1

21,/1

L 200

I~----,--o~4

R2

I

5 - 3921

~ SCS·1HOMSON
~""I UI'iIOtl'J@~~~t~I'J@1Il0t\l)

9/9

167

I

I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I
I
I

I
I
I
I
I
I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

I
I
I

L272
L272M
DUAL POWER OPERATIONAL AMPLIFIERS
•

OUTPUT CURRENT TO 1A

•

OPERATES AT LOW VOLTAGES

• SINGLE OR SPLIT SUPPLY
•

LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE

•

GROUND COMPATIBLE INPUTS

•

LOW SATURATION VOLTAGE

The high gain and high output power capability
provide superior performance whatever an operational amplifier/power booster combination is
required.

• THERMAL SHUTDOWN
The L272 and L272M are monolithic integrated
circuits in powerdip and minidip packages intended for use as power operational amplifiers in
a wide range of applications including servo amplifiers and power supplies, compact disc, VCR, etc.

Powerdip (8 + 8)

Minidip Plastic

ORDERING NUMBERS:
L272

L272M

ABSOLUTE MAXIMUM RATINGS
Supply voltage
Input voltage
Differential input voltage
DC output current
Peak output current (non repetitive)
Power dissipation at Tamb = 80°C (L272), Tamb = 50°C (L272M)
T case = 75°C (L272)
Storage and junction temperature

28
Vs
± Vs
1
1.5
1

5
-40 to 150

V

A
A
W
W
°C

BLOCK DIAGRAM

4,9-16

L272

L272M
1/6

169

...
,

l272-l272M
CONNECTION DIAGRAM
(Top view)
16

GND

15

GND

14

GND

GND

13

GND

INPUT ·2

12

GNO

INPUT.2

11

GND

INPUT.'

10 GND

INPUT -1

9

OUTPUT 1

OUTPUT 2

1

3

OUTPUT I

8

INPUT-l

7

INPUT.I

OUTPUT 2

6

INPUT.2

GND

S

INPUT_2

SUPPLY VOLTAGE

2

L272M
GND

5_5905

L272

SCHEMATIC DIAGRAM (one only)

S_590L/l

THERMAL DATA
RthJ V51

E 1, E2 = logic inputs

5_ 5931/1

Fig. 10 - Servocontrol for compact-disc

REFLECTED
BEAM
LASER

Fig. 11 - Capstan motor control in video recorders

DIGITAL
INPUT

________________~_________ ~~~~~~~~~:~~~ ________________________~5/_6

173

L272-L272M
Fig. 12 - Motor current control circuit

Note: The input voltage level is compatible with L291 (5-BIT D/A converter)

Fig. 13 - Bidirectional speed control of DC motors.

2R~

R1 where RM = internal resistance of motor. The voltage
M
2R3 R 1 and
available at the terminals of the motor is VM = 2 ( Vi _ V2s ) + I Ro I. IM where I Rol
Rx
1M is the motor current.
For circuit stability ensure that Rx>

0

0

Rx

IOKQ

R2
IOKO

IOKn
S-5909/2

~6/~6_________________________ ~~~~~~~¥~:~~

174

___________________________

L272D
DUAL POWER OPERATIONAL AMPLIFIER
ADVANCE DATA

•

OUTPUT CURRENT TO lA

•

OPERATES AT LOW VOLTAGES

•

SINGLE OR SPLIT SUPPLY

•

LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE

•

GROUND COMPATIBLE INPUTS

•

LOW SATURATION VOLTAGE

•

THERMALSHUTDWON

cations including servo amplifiers and power
supplies, compact disc, VCR, etc. The high gain
and high output power capability provide supe·
rior performance wheatever an operational
amplifier/power booster combination is required.

SO-16J

The L272D is a monolithic integrated circuit
in SO-16 packages intended for use as power
operational amplifier in a wide range of appli·

ORDERING NUMBER: L272D

ABSOLUTE MAXIMUM RATINGS
Supply voltage
I nput voltage
Differential input voltage
DC Output current
Peak output current (non repetitive)
Power dissipation at T case = 90°C
Storage and junction temperature

Vs
Vi
Vi

10
Ip

Ptot
T stg , Tj

28
Vs
± Vs
1
1.5
1.2
-40 to 150

V

A
A
W
°C

CONNECTION DIAGRAMS

N.C.

16

N.C.

N.C.

15

N. C,

OUTPUT 1

I

3

14

INPUT·l

SUPPLY VOL T.I 4

13

~INPUT+l

OUTPUT 2
GNO

N. C.

I5
6

12 h,NPUT +2
"

10

N. C.

N.C.
N. C.

5-10617

June 1988

INPUT-2

5-10678
1/4

ThiS is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

175

L272D
SCHEMATIC DIAGRAM (one only)

.v.

out

THERMAL DATA
Rthi-alumlna(*)

Thermal resistance junction-alumina

max 50

(*) Thermal resistance junctions-pins with the chip soldered on the middle of an alumina supporting substrate measuring

15 x 20 mm; 0.65 mm thickness and infinite heathsink.

~2/~4_________________________ ~~~I~~?~~~n
176

---------------------------

L272D
ELECTRICAL CHARACTERISTICS (Vs = 24V,
Parameter

Vs

Suppiy voltage

Is

Quiescent drain current

Tamb =

25°C unless otherwise specified)

Test Conditions

Min.

Typ.

4

V a ,:

Vs

2

Max.

Unit

28

V

Vs = 24V

8

12

mA

Vs = 12V

7.5

11

mA

Ib

Input bias current

0.3

2.5

jJ.A

Vas

I nput offset voltage

15

60

mV

los

I nput offset cu rrent

50

250

nA

SR

Slew rate

B

Gain-bandwidth product

Rj

I nput resistance

Gv

O.L. voltage gain

1

V/jJ.s

350

KHz
Kn

500
f = 100Hz

70

dB

f = 1KHz

50

dB

60

eN

Input noise voltage

B = 20KHz

10

jJ.V

IN

Input noise current

B = 20KHz

200

pA

CRR

Common Mode rejection

f = 1KHz

60

75

dB

SVR

Supply voltage rejection
54

70
62
56

dB
dB
dB

23
21

22.5

V
V

60
60

dB
dB

0.5

%

145

°c

f = 100Hz
RG = 10Kn
V R = 0.5V

Vo

Vs = 24V
Vs = ± 12V
Vs = ± 6V

Output voltage swing
Ip = 0.1A
Ip = 0.5A

Cs

Channel separation

d

Distortion

Tsd

Thermal shutdown
junction temperature

f = 1KHz; RL = 10n; G v =30dB
Vs = 24V
Vs = ± 6V
f = 1KHz
Vs = 24V

Gv = 30dB
RL = 00

177

L272D
Fig. 2 -- Quiescent drain
current vs. temperature

Fig. 1 - Quiescent current
vs. supply voltage

---trl
i

'D ,

(mA

-

--j

--

r-~.

~-~

,

d
(mA

L'.>.

6D

f--'~~+-

-1--

~---

r~l

-

"'-

7D

No.

r-.....

rt-

8D

;. ++

~-

--c-

13-612

(dB

c-- -

'[-±

V

Fig. 3 - Open loop voltage
gain

13-6119

"-

5D

~-I

"-

f-- 1--- -

40

1"-

3D

"'jo..'

I'"

1

,

1"-

r-~-

i

!"

I
16

20

24

20

Fig. 4 - Output voltage
swing vs. load current
(V

13

,

1.0

10'

60

lD'

10 5

""-J.
f (Hz)

Fig. 6 - Supply voltage
rejection vs. frequency

Fig. 5 -- Output voltage
swing vs. load current
13-£112

:--t~-

--

:Vs: :!:12V

- f-- -

I........
I--

,

-12

-11

--

-

I--- 1---f--

r- I'--.

,

80

___

12V

~~!:"~_NP_U__T,(IG-'"-"10-+1:..'---j_-+----j

70

40

,

""
1----+-+--.+----'"
LI
r---+-t--t---t---t--+---+---1

30 ·f---.r·-j--f---+-_·f-

--I600

40D

I LOAD(mA)

200

4DO

5DD

ILOAD(mA)

Fig. 7 - Channel separation
vs. frequency

10 4

10

Fig. 8 - Common mode
rejection vs. frequency ,_ ""
(d B)

f--i--++tfilt-f--l-j-'jltll

80

]C

f (H z)

178

1----1--

20L--L_L_-L_L--L_L-i-L~
200

4/4

!

+-r-f---+---1

60f--~~~~~+_+-+_1-50

i

-10

1-

~- -"-rvs- " J +--+,-+-+---1
!

I--

lD

90

.--

Ys= ±12V

-13

I
---.

!

(dB'

(VI

10"

t (Hz)

f (Hz)

L290
TACHOMETER CONVERTER
The L290, a monolithic LSI circuit in a 16-lead dual
inline plastic package, is intended for use with the
L291 and L292 which together from a complete 3chip DC motor positioning system for applications such as carriage/daisy-wheel position control
in typewriters.

I

DlP-16 Plastic
(0.25)

The L290/1/2 system can be directly controiled by
a microprocessor. The L290 integrates the following functions:
_ tacho voltage generator (FIV converter)
_ reference voltage generator
_ position pulse generator

I
ORDER CODE: L290B

_ _ _ _ _ _ _ _ _ _ _ _ _ _ .._ _..1I

ABSOLUTE MAXIMUM RATING
I

Symbol

t~-------v;-

!

[

--

Vi (FTA, FTB, FTF)
___ Ptot- T stg ,. T J

Supply

Voltag~---

--[~=--_~~lue---:-=-TlJ~it;

Parameter
____ .. __

± 15

.

V

Input Signals

LT~taIPo~er_[)issiP'Iti()n.._Tamb = 70

°C

Storage and Junction Temperature

SYSTEM BLOCK DIAGRAM
_ .._ . _ - - - - - - - - - -

--------------------------------,

L292

=<}J

')

f.17J

-----------------------------

September 1988

1/6

179

L290
CONNECTION DIAGRAM (top view)

FrB

1[r--v

VAB

2[

14 STA

d

13 STB

>V o
Vbias

12 FTF
11 GNO

61

VMB
VMA

FTA

15 VAA

Vrf'f

TACHO

~16

10 STF

s[

9

- Vo

5·" 15911

BLOCK DIAGRAM
.------.~--------

---~---------.------------------

11

, 6 FTA
-

J

A'

+
I\J

FTB

'"

FTF

J

A2

STF

STA

,J SIB

TACHO

,2

10

-~VAA

'5

VA8

VMS

VMA

7 8

-----_._------------

180

L290
TEST CIRCUIT
+Vs

TACHO

3,2.5K1l..
FTA

16

I----+--+-D

5 TA

1 3 I--~-+----(:J

5 TS

14

FTS

L290

FTF

1 Ol----~-D STF

B

~~~-j~i--i==~~----------OVMB
-----------{) VM A
2,82011..

5

~]
5- 4144f4

Vbiast1.8V

Vbias-1.8V

THERMAL DATA
Rlh

J·amb

Thermal Resistance junction-ambient

Max

I

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, S in (A), Vs
unless otherwise specified)
Symbol

Parameter

Vs

Supply Voltage

Id

Quiescent Drain Current

Test Conditions

~

1-Min.

± 12

V,

Vs =±15V

Input Signal from Encoder
(pin 1, 16)

Typ.

Voltage Gam

Va

Output Voltage Swing
(pin 2, 15)

I

f = 10KHz FT A =
F!.§. = ± o.:~P
FTA = FTB = ± 1Vp

-~

20

0C/W

25 "C

± 15

I

Unit

I
.... 1

V
mA

_.,

IH'
-

~

Max.

13

f max = 20 KHz

Output Offset Voltage
FTA = FTB = 0 V
(pin 2, 15)
l~p~Bias curren;(P;;;-1,-;6)i-----------.

Tamb

± 10

INPUT AMPLIFIERS (A, and A2 )
FTA, FTB

I

80

I

± 0.6
± 55

I

mV

,- - - -

015
- - -

flA

I'

"~5--'1

"

I

dB
V

3/6

181

L290

ELECTRICAL CHARACTERISTICS (continued)
Symbol

I

Parameter--[=T~st c~nditJ;;~

I

COMPARATORS WITH HYSTERESIS (C " C 2 , and C 3 )
- - - - - - - - - - - - - - - - - --

, VTHP (0)
I

VTHN (00)

!'.FTF

~,_2:'_15L_____ ___

Threshold Hysteresis
----

VL

-------

-- --

C2, _ _ _

--------

---==_=-_ ~ ~--y-~-- ___

~ 2 rnA
FTA~FTB~FTF~OV

Output Voltage (low level)
(pin 10, 13, 14)
---

Ileak

C3

Negative Threshold Voltage

:_ _ _ _ I(Pin

,--

C , and C 2

Positive Threshold Voltage
(pin 2,12,15)

I'

I

la

-----

I

02

~::-:~~B-~ ~~: ~ 1 V

[ (pins 10, 13, 14)

+-120

I

04

.

1

-

~V

'

I

,uA

REFERENCE
GENERATOR
,
V ref

DC Reference Voltage
(pin 3)

I ref

Output Current (pin 3)

FTA ~ FTB
I,el ~ 1 rnA

~

± 0,5 Vp (')

4.5

V
rnA

L ___ _

"TACHO" AMPLIFIER (A3)
--------

Output Offset Voltage (pin 4)

FTA ~ ± 15 rnV

DC Output Voltage (pin 4)

FTA~FTB~
± 0,5 Vp
VMA ~ VMB
± 1.25 Vp

!'.Va
Va

I

I
Output Voltage Swing (pin 4)

!---

--------

FTB ~ 0.5 V

(H)
V a1

-----------------,-----I'

,

5A'

I

FT A

-6

FTB

~ 0.5

V

Note

± 1.7

4/6

182

o_r

: FTA~FTB~FTF~
C)
Phase relationship between the signals:
FTB : 90'
, FTA: 0'
.. FTA:O'
FTB:-90'
VMA~90'
... FTA: 0'
FTB : 90'
VMA ~ 90'

VM8 = 0"
VMB ~

180'

rnV

V

Sin (B) --"-_F'TA ~ FTB ~ - 0.5

1V

rnV

- 6,6
+ 150

~

- 6,5

n

± 80

16,6

V

~

Va1 + Va2

I

.

6

Vp

-----------------------

L290
..

WAVEFORMS (Neglecting threshold voltage level of the comparators).
CLOCKWISE
DIRECTION

ANTICLOCKWISE
DIRECTION

VAA

VAS

C51

C52

VMA

VMS

(58

C5A

TACHO

SYSTEM DESCRIPTION: refer to the L292 data sheet.

5/6

183

(j)

~

las

"T1

~
0-

cO·
t:

iD

..'2

...-..
~

11\

I\)

~

:::J
Ul

<
@

(")
0

-

"ll
" <

11\

o
a ·I\)

1,,-

3

1..- . :. L290

"Q.
(1)

ro

OJ

-

"0
"0

II

o·
~
o·

I\)

::t>

::J

~~

• lOV

0

~F

~

~

~019
0.%1\

Iz

I"

0
1 o.zo.
,.

!!IC/)

""t;I

Ai

Ii!
!O
;0

Q.

11

A II
1..7Kn

".7~Ay

rJH1

Ii:

... O,,'IJF

!illcn

II

0, ,

~H
.LO.H~'~iSpud

22.K.n

,jK",11
ITACHol! "9
. 10.1..,.
SKn

",,0
.. 21

9

L291

l:i

OAellN

-------OACi5'Ui"

2 SC'

,lsCl

~RO~

I,

~CAC l------H'"'
51sc

J

,lJPROCES!l~ I

,I

,Ise,
.,

J~I.G!'I._.

'V, ~

_. _ • __

Slrcb.

,..
• V.

T13
CiNO

-V,

~~; 01~

LfR-into

'0

-v,

• IZ

-12

"
0'0
HiKn

CE21CE1
13

ur

ON(H)

0"1 L)

c

L292

I~

--------~

----~-.--~-.----

5 BIT - D/A CONVERTER AND POSITION AMPLIFIER
• 5 BIT D/A CONVERTER (1/2 LSB MAX LINEARITY ERROR) ;
• ERROR AMPLIFIER;
• POSITION AMPLIFIER.

DESCRIPTION
The L291, a monolithic LSI circuit in a 16-lead dual
in-line plastic package, is intended for use with the
L290 and L292 to form a complete 3 chip DC motor
positioning system for applications such as carriage/daisy-wheel position control in typewriters,

DIP-16
(Plastic 0,25)
ORDER CODE: L291 B

The L290/291/292 system can be directly controlled
by a microprocessor.

ABSOLUTE MAXIMUM RATINGS
Symbol
Vs
Ptot
Tstg, Tj

Parameter

-----_._-----

Value

Unit

----------~--

±15

Supply Voltage

V

--

Total Power Dissipation Tamb = 70'C
Storage and Junction Temperature

1

W

-40to 150

'c

SYSTEM BLOCK DIAGRAM

'----_ _ _ _ _-----' S-4171

September 1988

1/6

185

L291
CONNECTION DIAGRAM (top view)

ERRV

1

16 POS/OUT

SC,

,5

POS/IN

SC l

,4

.V s

SC J

13

GND

,2

DAC/QUT

SC 5

N.C.

"

SIGN.

,0

7

Strobe 8

-VS
DACIIN

5-4160

BLOCK DIAGRAM

SC1
SC2

4

SC3

5

SCt.

6

SC5

D/A
CONY.
....~+---16

SIGN

POS/OUT

,

9

'--

OAC/IN

ERRV

OAC/OUT

2/6

186

POS/IN
1 15

12

~

~"fI

Strobe

SIiS·THOMSON

iIii~©!I@~~I<©'IT!I@IlI~©$

5-4157/1

B

L291
TEST CIRCUIT
,------~----------~~

SIGN

5(10-L5_8 2
5(20
5C]

L 291

SC4()--S(5

5

M58~6-rB__-T____~__~r-____~

StrobE'~--J

:,

1.158/1

"--------------------------~---~----------------,

THERMAL DATA

[RthJ~amb

I

Max

Thermal Resistance Junction-ambient

ELECTRICAL CHARACTERISTICS (refer to the circuit, 81 and 82 in (a), Vs
T amb ~ 25'C, unless otherwise specified)
Symbol
Vs

Parameter

-1;;t

co~ditions

Supply VOltage----------------

~~_ld ~le~ln
__

current-=t-= ___

!

Min.

I

Typ.

I

---t±~~--l--·-+

~

± 12

Max.

un~i

±15--j.-V-.
!

~=~. ~-_==J- ;5_±_iO-·~_ I--~A--

POSITION AMPLIFIER
Vstrobe

Enable Vol

I

tage Level
Vas

t::
Ib

----

VR
.,----

Output Offset
(pin 16)

~~~~',: ~::, : -

VOltag~_ V~robe:VL Gv
.

-

Input Bias

2 )_1 Vstrobe

- Current (pin 5

(pin 16)
O"'~"o

"go S",O,

--~~~~~

Residual
(pin 16)
----

0,.,,,",,;;'

tv"ooe

~-~-

l-;o,-

0

"'

:

:~,j

-l- -_.
501

mV

..~~~

TV
°8V " c - l

-- ----

V, , " ,"'h' , V,

I

--1---= ..... ,

= 20 dB -

Iv"~o",,______ -~ -~ ~_
0

V,

0. .3-

~:J~V

• See block diagram and the note for Position Amplifier.

~--

---- - ~rr,/
SGS·ntOMSON
""J,I ~n©L'l@rn~rn©~L'l@lIln©®

3/6

187

L291
ELECTRICAL CHARACTERISTICS (continued)

Param_e.~~~-

I Symbol I

TesUondit~

I

Min.

D/A CONVERTER

I

I ref

II

Vos

II

~~~~~\~~f~;e:::~~I_ -'~"-,-'--------ll,---0.3
Current Reference Offset
Voltage (pin 9)

Ii

I ref = 0,3 to 1.2 mA
All Inputs High

SC1 to SC5 = L

1'>10

-1~~a~~~..E:~ror

101 + 102
_

II ref =

I

0.7~

I__

Level

l--V;;-- i ~~~t~~ltage Le~~1
-"

IL -

-1.4
+ 1.4

__

i 2.~-

(digi;ai-j SC5 = MSB
VL =

O~--'-'

Digital Inputs Current (high

188

1,61

I

_i~CltEJ), __,____ ~_________ ,___L

4/6

mA

+ 1.442

j.lA

~/oFsl

±0.4

(di~;;-lsC1 ~-LSB------""------I~~

i ~~ti!)llnp~;s Current (Io,.;l

mA

-1.442

+ 21

I Pin

~_~n~~t~tage

mV

1.4

- 21

_____

12 Output Offset Current I All Inputs High
(including Error Amplifier bias
~current),
los

± 20

- - - - - + 1- - - - f - - - - +- - -

________SIGN = H(102) ~~il....

1--_ _-+_ _ _ _ ,___,____,,'

mA

----+----+----+----+---1

:~,:::::: :::::,'111 ,0 O":A --5:0 1(1 ",1- 1.358

::

1.2

0,8

":

,-----~-

+ Vs

V

-50

j.lA
j.lA

___ ._.l_ _, _ _ _ .

L291
D/A CONVERTER
The L291 contains a 5-bit D/A converter accepting a binary code and generating a bipolar output current,
the polarity of which depends on the SIGN input. The amplitude of the output current is a multiple of a reference current Iref.
The maximum output current is
IFs =

± __~L
16

Iref

The following table shows the value of 10 for different input codes. Note that the input bits are active low.

1-._-_.-

SIGN
._---_.

DIGITAL INPUT WORD

-----------

SC5
MSB

-----.----~--

-

SC4

SC3

SC2

SC1
LSB

Output Cu rrent
10

---_.. _------_.

. .. _ - - - - - - -

L

L

L

L

L

L

-

~

Iref

L

H

H

H

H

L

-16

Iref

X

H

H

H

H

H

o

H

H

H

H

H

L

H

L

L

L

L

L

+
+

16
1

1

-f6"

Iref

31

16 Iref

x=

indifferent
L = low
H= high

This D/A converter has a maximum linearity error equal to
tees its monotonicity.

± 1/2 LSB (or ± 1.61% Full Scale) ; that guaran-

ERROR AMPLIFIER
In order to have a good stability, the Error Amplifier must work with a closed loop gain greater or equal than
20 dB.
POSITION AMPLIFIER
It is inserted by means of the strobe signal, TTL and microprocessor compatible. Its output is connected to
pin 16 when Vstrobe = Low; pin 16 is grounded for Vstrobe = High.

SYSTEM DESCRIPTION: refer to the L292 data sheet.

5/6

189

L291
Figure 1

Complete Application Circuit.

IliR-infO

I

7 SIGN
_ ... -

_.
Strob~

ON!H)
OFf"(L)

-

tV s

D1 to D4: {

6/6

190

GNO

VF <; 1.2V @ I ~ 2A
trr <; 200 ns

L292
SWITCH-MODE DRIVER FOR DC MOTORS
------~~------

•
•
•
•
•
•

~~----~~

DRIVING CAPABILITY: 2 A, 36 V, 30 KHz
2 LOGIC CHIP ENABLE
EXTERNAL LOOP GAIN ADJUSTEMENT
SINGLE POWER SUPPLY (18 TO 36 V)
INPUT SIGNAL SYMMETRIC TO GROUND
THERMAL PROTECTION

The L290/1/2 system can be directly controlled by
a microprocessor.

Multiwatt 15

DESCRIPTION
The L292 is a monolithic LSI circuit in 15-lead
Multiwatt ® package. It is intended for use, together with L290 and L291, as a complete 3-chip
motor positioning system for applications such
as carriage/daisy-wheel position control in typewrites.

ORDER CODE: L292

ABSOLUTE MAXIMUM RATINGS
,------,----~~~

-~~YI1l~o-'t
Vs

--

--~~--~-~-

Parameter

Power Supply
-----

,-----

V;

---------

Input Voltage

--~---~

~.

V;nh,bH

_

..

-~

~'-

~~---~

..

-

~-

_______ ~J_-

-- V:I:e ---

--n~it

-15to+Vs

V

-

o to

Inhibit Voltage

Vs

V

~-----~-

10

2.5

Output Current

--------------------+= 75 'C)

Ptot
Tstg

~-

----

~---~-

--------~-

~

--~~--

- 40 to + 150

Storage and Junction Temperature

TRUTH TABLE

~

$-

Output Stage
Condition
Pin 12
L

L

Disabled
.-

..

L
H
I
~-----r----~
L

-------~-~-

Normal Operation
Disabled

I------r---------------~~--

- ~. -

15

"!3~

""~
,
'0

$

Pin 13

-~-

H

~:

CONNECTION DIAGRAM (top view)

Vinhibit

- -

25

Total Power Dissipation (Tease

-.-------~

8
7

6
5

CF = 92 n F SCiS-THOMSON IiIitlD©~@~~~©1i~@IIlD©$ ___ _ ---- L293B L293E PUSH-PULL FOUR CHANNEL DRIVERS • OUTPUT CURRENT 1A PER CHANNEL • PEAK OUTPUT CURRENT 2A PER CHANNEL (NON REPETITIVE) • INHIBIT FACILITY • HIGH NOISE IMMUNITY • SEPARATE LOGIC SUPPLY • OVERTEMPERATURE PROTECTION The L293B and L293E are packaged in 16 and 20pin plastic DIPs respectively; both use the four center pins to conduct heat to the printed circuit board. The L293B and L293E are quad push-pull drivers capable of delivering output currents to 1A per channel. Each channel is controlled by a TTLcompatible logic input and each pair of drivers (a full bridge) is equipped with an inhibit input which turns off all four transistors. A separate supply input is provided for the logic so that it may be run off a lower voltage to reduce dissipation. Additionally, the L293E has external connec· tion of sensing resistors, for switchmode control. DIP-16 Plastic (0.4) Powerdip 16+ 2+ 2 ORDERING NUMBERS: L293B (16 leads) L293E (20 leads) ABSOLUTE MAXIMUM RATINGS Vs Vss Vi V inh lout Ptot Tstg , Tj Supply voltage Logic supply voltage Input voltage Inhibit voltage Peak output current (non-repetitive t = 5ms) Total power dissipation at TgrOund-Pins= BO°C Storage and junction temperature DC motor control June 1988 36 36 7 7 2 5 -40 to 150 V V V V A W °C Bidirectional DC motor control 1(8 201 L293B - L293E CONNECTION AND BLOCK DIAGRAM (L293) (top view) CHIP ENABLE 1 16 V55 INPUT 1 15 INPUT 4 OUTPUT 1 14 OUTPUT 4 GNO 13 GN 0 GNO 12 GNO OUTPUT 2 11 OUTPUT 3 INPUT 2 10 v5 9 ! NPUT 3 CHIP ENABLE 2 " 5 -1..169 CONNECTION AND BLOCK DIAGRAM (L293E) (top view) CHIP ENABLE' 1 V" INPUT 1 INPUT 4 OUTPUT 1 OUTPUT 4 SENSE 1 17 SENSE 4 GNO 16 GNO GNO 15 GNO SENSE 2 14 SENSE 3 OUTPUT 2 13 OUTPUT 3 INPUT 2 12 v, 2/8 202 " INPUT 3 CHIP ENABLE 2 SCHEMATIC DIAGRAM .-----11:: T2 T3 (,1) TS [ r:: T7 II Rsl ~ iiiU» 1£1 © • ~:i! II ~T12 I ~ R2 T 17 l{g ~Z TJ5 f::S--@ (19) QR9 r- l ,. .!2. !2J@ (12 ) (14)(13) (16X17) N 5 ~ CO (0) 5184 OJ I r- ...-' o/'oJ w I'"'" ~ N CO (*) In the L293 these points are not externally available. They are internally connected to the ground (substrate). o Pins of L293 (0) m () Pins of L293E - r- L293B-L293E THERMAL DATA Rth j-case Rth j-amb Thermal resistance junction-case Thermal resistance junction-ambient max max 14 80 ELECTRICAL CHARACTERISTICS (For each channel, Vs= 24V, Vss= 5V, Tamb = 25°C, unless otherwise specified) Test conditions Parameter Min. Typ. Max. Unit Vs Supply voltage Vss 36 V Vss Logic supply voltage 4.5 36 V Is Total quiescent supply current Iss Total quiescent logic supply current V iL I nput low voltage V iH Input high voltage Vi = L Vi = H 10 = 0 10 = 0 V 1nh = H 2 6 V inh = H 16 24 Vi = L 10 = 0 44 60 Vi = H 10 = 0 V inh = H 16 22 V inh = L 16 24 -0.3 1.5 Vss ,,; 7V 2.3 Vss > 7V 2.3 7 V ss rnA 4 Vinh= L V inh = H mA V V -10 p.A 100 p.A -0.3 1.5 V Vss .;;;; 7V 2.3 > 7V 2.3 Vss 7 V -100 p.A ± 10 p.A liL' Low voltage input current V 1L = 1.5V liH V inhL High voltage input current 2.3V .;;;; ViH .;;;; Vss -0.6V I nh ibit low voltage V inhH Inhibit high voltage V ss linhL Low voltage inhibit current VinhL - 1.5V linhH High voltage inhibit current 2.3V .;;;; V inhH .;;;; Vss -0.6V 30 -30 VCEsatH Source output saturation voltage 10 --lA 1.4 1.8 V V CEsatL Sink output saturation voltage 10 = lA 1.2 1.8 V 2 V VSENS Sensing Voltage (pins 4,7,14,17) (**) tr Rise time 0.1 to 0.9 Vo (*) 250 ns tf Fall time 0.9 to 0.1 Vo (.) 250 ns ton Turn-on delay 0.5 Vi to 0.5 Vo (0) 750 ns toff Turn-off delay 0.5 Vi to 0.5 Vo (0) 200 ns (*) See fig. 1. ('*) Referred to L293E. ~4/_8_________________________ ~~~~~~~~:~~©~ 204 ___________________________ L293B- t293E TRUTH TABLE Fig. 1 - Switching times Vi (each channel) Vo V inh . (00) H L H L H L X (0) X (0) H H L L (0) High output impedance. (00) Relative to the considerate channel. 5-4'71 Fig. 3 - Source saturation voltage vs. ambient temperature Fig. 2 - Saturation voltage vs. output current VCE sat ,....,-,---,,.....,-,--,--":.r'-'-, 'n ~+-~vL,.~,,~vL-~~~--+-~ VCEsatH Fig.4 - Sink saturation volt· age vs. ambient temperature veE,.tL ,n (V) --- "s=24'1 -J J v,~.~z,~vl----'-~-r--t-~ Vinhibil=Vss ,,5V 3 ~_~I',",nh",ib",'t"rv-""-"-r5_V_r--t_+---1 Vinhibit,,'Iss ,,5V ~+-~~--+--+--+--+--- "CEsatH ~ r--t-+--r--t .--r=- 10::0.1 A 0.5 '.5 '0 (A) Fig. 5 - Quiescent logic supply current vs. logic supply voltage -so -so 50 Fig. 6 - Output voltage vs. input voltage 50 Fig. 7 - Output voltage vs. inhibit voltage vo"-'~v,~.~z~'v~,--,-,--~~~ I" "ss,,'Ij=5V (rnA) Vs=2t.V Vi :LOW 50 --- "inh=HIGH " " V 'II I--- V,/ II " " I I, VCEsat l veE sat l 10 ZO 30 "SS(V} '.5 Z.5 5/8 205 L293B-L293E APPLICATION INFORMATION Fig. 8 - DC motor controls (with connection to ground and to the supply voltage) Ml A H H Fast motor stop H Run H L Run L Fast motor stop L X Free running X Free running L = Low H = High C = H; D=L Turn right V inh = H C = L; D=H Turn left V inh = L C = X; X = Don't care L = Low ". D=X " D1 lu Free running motor stop X = Don't care H = High O.22~F D5 D6 ch luI i l2dOOmA Dr D1 - D8 = 206 Fast motor stop C=D motor stop Fig. 10 - Bipolar stepping motor control 6/8 FUNCTION INPUTS M2 B V inh motor stop Fig. 9 - Bidirectional DC motor control { V F .. l.2V @ I = 300 mA trr" 500 ns L293B-L293E APPLICATION INFORMATION (continued) Fig. 11 - Stepping motor driver with phase current control and short circuit protection ~2 V, 02 19 .f: 4.,N4001 10 08 ~13 12 07 .J.. 4"x1Nl.QOI 12 11 L293E f09 1! L2 14 :~ --;J.. 05 ..I- 16815 7 03 2.1N4148 010 ~, 17 ILl ~1 ~OjJF 0 +5V '8 r:l.. 04 20 :~ iFZ 01 1111 1 2 :E'pF ~ [ R52! lJl .L.. R52 lJl. ~1 2xlN4148 012 .L.. .5V 10K~ 0·R3 14 LMJ~: + 9 VA '" ~ "~ 10 _ [ Rl lKil 10Kn. LM339 Vret'OKll. ll.!:!Il I~F RMo,: SIn. rO.,pF "R9 10KA RIO 10K11 IOOKA 8:" I~F 100K.tl. R12 Rll ~ 114 LMJ39 + 7 D1 to D8 : 1 1.5Mfi ~18 , 10 Kil 13 12 RS .5V~ R4 3 V t 4 CP4 [ 114 10Kl1 !..OKll RU- R15 R17 10K11 2 LM339 5 + 47K.n 1,7K.n. R14 R16 I 5-516611 { V F " L2V @ I = 300 mA trr " 200 ns ___________________________ ~!~~~&~~ ________________________ ~7/~8 207 L293B-L293E MOUNTING INSTRUCTIONS The Rth j-amb of the L293 and the L293E can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board as shown in figure 12 or to an external heatsink (figure 13). Fig. 12 - Example of p.e. board copper area which is used as heatsink During soldering the pins temperature must not exceed 260 Q e and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. Fig. 13 - External heatsink example (R th = 30 °e/W) mounting p.e.BOARD ~8/~8_________________________ ~~~~~?~~~~ ~ 208 _________________________ L293C PUSH-PULL FOUR CHANNEL! DUAL H- BRIDGE DRIVER PRELIMINARY DATA • 600mA OUTPUT CURRENT CAPABILITY PER CHANNEL • 1.2A PEAK OUTPUT CURRENT REPETITIVE) PER CHANNEL • ENABLE FACILITY • OVERTEMPERATURE PROTECTION • LOGICAL "0" INPUT VOLTAGE UP TO 1.5V (HIGH NOISE IMMUNITY) (NON The device may easily be used as a dual H-bridge driver: separate chip enable and high voltage power supply pins are provided for each Hbridge. In addition, a separate power supply is provided for the logic section of the device. The L293C is. assembled in a 20 lead plastic package which has 4 center pins connected together and used for heatsinking. • SEPARATE HIGH VOLTAGE POWER SUPPL Y (UP TO 44V) Powerdip (16+2+2) The L293C is a monolithic high voltage, high current integrated circuit four channel driver in a 20 pin DIP. It is' designed to accept standard TTL or DTL input logic levels and drive inductive loads (such as relays, solenoids, DC and stepping motors) and switching power transistors. ORDER CODE: L293C BLOCK DIAGRAM IN 4 19 OUT4 OUT3 IN 3 18 13 12 r---+--------+---4~--+-~I~I~{)ENABLE2 20 10 VS2Lr-+~------~--------------~ L293C 9 ~1~-+~------~----------------' ~--+--------+--~~--+----r-o 2 3 7 INI OUTI OUT2 8 ~ ENABLE 1 -9287 5.6.15.16 June 1988 IN2 1/3 209 L293C ABSOLUTE MAXIMUM RATINGS Vs Vss VI VEN lout Ptot T stg , TJ Supply voltage Logic supply voltage Input voltage Enable voltage Peak output current (non-repetitive t = 5ms) Total power (jissipation at TgrOUnd-Plns = 80°C S:torage and junction temperature 50 V 7 7 7 1.2 5 V V V A W °c -40,to 150 TRUTH TABLE CONNECTION DIAGRAM (Top view) ENABLE OUTPUT H H H L H L X L Z INPUT 20 ENABLE I Vss INPUT I 19 INPUT 4 OUTPUT I 18 OUTPUT 4 (NC) 17 (NC) GNO 16 GNO X = Don't care GNO GNO OUTPUT 2 (NC) INPUT 2 Z = High output impedance SWITCHING TIMES OUTPUT 3 INPUT 3 . VS1" VS2 ENABLE 2 5-9288 THERMAL DATA Thermal resistance junction-case Thermal resistance junction-ambient ;::.:2/..::.3_ _ _ _ _ _ _~_ _ _ _ _ 210 ~ ~~tm~I19©~ max max 14 80 -------------- L293C ELECTRICAL CHARACTERISTICS (For each channel, Vs = 24V, Vss = 5V, Tamb = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. Max. Unit Vs Supply voltage (pin 9, 10) Vss 44 V Vss Logic supply voltage (pin 20) 4.5 7 V Is Total quiescent supply current (pin 9,10) Iss, Total quiescent logic supply current (pin 20) VI = L; 10 = 0; VEN = H 2 6 VI = H' 10 = 0; VEN = H 16 24 V EN = L Vi = L; I0 = 0; V EN = H 44 60 VI = H; 10 = VEN = H 16 22 V EN = L 16 24 0; mA 4 mA V IL Input low voltage (pin 2, 8, 12, 19) -0.3 1.5 V VIH Input high voltage (pin 2,8, 12, 19) 2.3 Vss V IlL Low voltage input cu rrent (pin 2,8, 12, 19) -10 JJA IIH High voltage input current (pin 2, 8,12,19) 100 JJA VENL Enable low voltage (pin 1, 11) -0.3 '1.5 V VENH Enable high voltage (pin 1, 11) 2.3 Vss V IENL Low voltage enable current (pin 1, 11) VENL -100 JJA IENH High voltage enable current (pin 1,11) 2.3V .;; VEN H .;; Vss -0.6 ± 10 JJA VCE (sat) H Source output saturation voltage (pins 3,7,13,18) 10 = -0.6A 1.4 1.8 V VCE(sat) L Sink output saturation voltage (pins 3, 7,13,18) 10 = +0.6A 1.2 1.B V tr Rise time (*) 0.1 to 0.9 Vo 250 ns tf Fall time (0) 0.9 to 0.1 Vo 250 ns ton Turn-on delay (*) 0.5 VI to 0.5 Vo 750 ns toft Turn-off delay (0) 0.5 VI to 0.5 Vo 200 ns VI = 1.5V 2.3V';; VI .;; Vss -0.6V = 1.5V 30 -30 (0) See switching times diagram ___________________________ ~~~~~~~~~ ________________________~3/~3 211 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L293D PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES PRELIMINARY DATA • 600mA. OUTPUT CURRENT CAPABILITY PER CHANNEL • 1.2A PEAK OUTPUT CURRENT (NON REPETITIVE) PER CHANNEL • ENABLE FACILITY • OVERTEMPERATUREPROTECTION • LOGICAL "0" INPUT VILTAGE UP TO 1.5V (HIGH NOISE IMMUNITY) • INTERNAL CLAMP DIODES To simplify use as two bridges each pair of channels is equipped with an enable input. A separate supply input is provided for the logic, allowing operation at a lower voltage and internal clamp diodes are included. This device is suitable for use in switching applications at frequencies up to 5 kHz . The L293D is assembled in a 16 lead plastic package which has 4 center pins connected together and used for heatsinking. The L293D is a monolithic integrated high voltage, high current four channel driver designed to accept standard DTL or TTL logic levels and drive inductive loads (such as relays solenoides, DC and stepping motors) and switching power transistors. Powerdip 12+2+2 ORDERING NUMBER: L293D BLOCK DIAGRAM VS 8 OUT 1 Vs 3 Vss OUT 3 11 V,. 16 10 IN 1 9 ENABLE 1 15 IN 2 4,5,12,13 6 14 OUT 2 OUT 4 IN 3 ENABLE 2 IN 4 L 2930 S_6573 June 1988 1/4 213 L293D ABSOLUTE MAXIMUM RATINGS Vs VSS Vi Ven 10 Ptot T stg , Tj Supply voltage Logic supply voltage Input voltage Enable voltage Peak output current (1 OOJ.ls non repetitive) Total power dissipation at T ground-Pins= 80°C Storage and junction temperature 36 36 7 7 1.2 5 -40 to 150 V V V V A W °c CONNECTION DIAGRAM ENABLE 1 16 Vss INPUT 1 15 INPUT 4 OUTPUT 1 14 OUTPUT 4 GNO 13 GNO" GNO 12 GNO OUTPUT 2 11 OUTPUT 3 INPUT 2 10 INPUT 3 Vs 8 ENABLE 2 5_6574 THERMAL DATA Rth j-case Rth j-amb Thermal resistance junction-case Thermal resistance junction-ambient "'2/...:.4_ _ _ _ _ _ _ _ _ _ _ 51 SGS-THOMSON . J'~ !;I)~~I!I@!l~!l~1i"I!I@~~~:O 214 max max 14 80 °C/W °C/W _ _ _ _ _ _ _ _ _ _ __ L293D ELECTRICAL CHARACTERISTICS (For each channel, Vs 24V, Vss unless otherwise specified) Parameter Vs Supply voltage (pin 8) V's Logic supply voltage (pin 16) Is Total quiescent supply current (pin 8) Test condition Min. Typ. Vss 4.5 Vi ~ L 10 ~O Vi ~ H 10 ~ 0 Ven ~ H Ven ~ H Total quiescent logic supply current (pin 16) Vi ~ L 10 ~ 0 Ven Vi ~ H 10 ~ 0 Ven~ ~ Input low voitage (pin 2, 7,10,15) V IH Input high voltage (pin 2, 7, 10, 15) 36 V 36 V 6 16 24 H 44 60 H 16 22 16 1.5 Vss';; 7V 2.3 Vss > 7V 2.3 7 IlL Low voltage input current (pin 2,7,10,15) V IL = 1.5V IIH High voltage input current (pin 2, 7, 10, 15) 2.3V .;; VIH .;; Vss -0.6V V enL Enable low voltage (pin 1,9) V enH Enable high voltage (pin 1, 9) mA 24 -0.3 Vss mA 4 Ven ~ L V IL Unit 2 Ven ~ L Iss Max. V V -10 iJ.A 100 iJ.A -0.3 1.5 V Vss';; 7V 2.3 Vss > 7V V enL = 1.5V 2.3 7 Vss lenL Low voltage enable current current (pin 1, 9) ienH High voltage enable current (pin 1,9) 2.3V .;; V enH .;; Vss -0.6V VeEsatH Source output saturation voltage (pins 3, 6, 11, 14) 10 = -0.6A VeEsatL Sink output saturation 10~+0.6A 30 V -30 -100 iJ. A ±10 iJ. A 1.4 1.8 V 1.2 1.8 V voltage (pins 3, 6, 11,14) VF Clamp diode forward voltage 10 = 600 mA 1.3 V tr Rise time (*) 0.1 to 0.9 Vo 250 ns tf Fall time (.) 0.9 to 0.1 Vo 250 ns ton Turn-on delay' *) 0.5 Vi to 0.5 Vo 750 ns toff Turn-off delay (*) 0.5 VI to 0.5·V o 200 ns '*) See fig. 1 ------------- ~ !~tm~~~~Jl------------3~/4 215 L293D TRUTH TABLE (One channel) INPUT ENABLE 1*) OUTPUT H H H L H L H L Z L L Z Z = High output impedance I') Relative to the considered channel Fig. 1 - Switching Times 216 L294 SWITCH-MODE SOLENOID DRIVER .-------~ .. • HIGH VOLTAGE OPERATION (UP TO 50V) • HIGH OUPTPUT CURRRENT CAPABILITY (UP TO 4A) • LOW SATURATION VOLTAGE • TTL-COMPATIBLE INPUT • OUTPUT SHORT CIRCUIT PROTECTION (TO GROUND, TO SUPPLY AND ACROSS THE LOAD) • THERMAL SHUTDOWN • OVERDRIVING PROTECTION • LATCHED DIAGNOSTIC OUTPUT - - . - -..--.--~~-~----~--- -------'-- tronic typewriters_ Power dissipation is reduced by efficient switch mode operation_ An extra feature of the L294 is a latched diagnostic output which indicates when the output is short circuited_ The L294 is supplied in a 11-lead Multiwatt ® plastic power package_ I I Multiwatt 11 DESCRIPTION The L294 is a monolithic switch mode solenoid driver designed for fast, high-current applications such as hammer and needle driving in printers and elec- ORDER CODE: L294 ~---------------- BLOCK DIAGRAM ~-------------- -------- 02 5-5011,/1 -_._---- - - - - - _ . _ - - - - - - - September 1988 1/6 217 L294 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit Vs Power Supply Voltage 50 V Vss Logic Supply Voltage 7 V Enable Voltage 7 V Input Voltage 7 V Vi Peak Output Current (repetitive) Ptot Total Power Dissipation (at Tease 4.5 = 75C) Storage and Junction Temperature ----------- --- 25 + ~11 -$- SINK OUTPUT 1~ CURRENT SENSING ENABLE TIMING 8 INPUT VOLTAGE GND 6 DIAGNOSTIC OUTPUT LOGIC SUPPLY ON TIME VOLTAGE LIMITER SOURC E OUTPUT POWER SUPPLY VOLTAGE Tab connected THERMAL DATA 2/6 218 . w -40 to 150 CONNECTION DIAGRAM (top view) I A - - - - - - - - - - - - - - - - - - - - - --'--------------------------'--- 1-----I -t-- to pin 6 5 - 531211 ---------------- L294 ---- ELECTRICAL CHARACTERISTICS (refer to the test circuit, Vs = 40V , Vss = 5V , Tamb = 25"C, unless otherwise specified) l Symbol 1- Parameter Test conditions ---v;-- tpower Supply Voltage (pin 1) - - Id-- Max. Unit 46 V 12 QUiescent Drain Current (pm 1 20 _______________+_V_;2___ 0_.6V; VENABLE -=-_~ ____ _ 30 7 V 5 8 mA 10 100 flA 4.5 -I'O~i~sc~~tL~gic Sup~l~ , Current mA 70 ! Logic Supply Voltage (pin 4) V~~ -I ss-- Operative Condition 1 ____ I -- Min. DIAG Output at High Impedance V; 0.6 V 0.45 _-------------------1 V, <; 0.45V ~------------- VENABLE f--IE-N-AB-L-E- -1 . V;20.6V Input Current (pin 7) '[ -- ----------- -- -------- - f_~CJI!I_L_8'J~ __________ _ Enable Input Voltage (pin 9) t E~-b!;l~;;u-t-C-u-rre-n-t-(p-in-9-) - ~IA 3 0.8 -. tV~~A;~:L-=_~=_-~_-- -100 ~ VENABLE = H__ _ I Transconductance i Rs - 0 20 I -. V 2.4 High Level ~IA 100 V, - 1V 4V 0.95 VI~ 1.05 f----_I---------.---f------- Vsat H ___,,!sal L__ Source Output Saturatio Voltage Output Leakage Current f -__K _ _-+-O_n Time Limiter 4A i Ip = 4A 4.5 -jRs-=-0-.2-0-;-V, <; 0.45-V-- 1 ---=----=----- Diagnostic Output Voltage (pin 5) IOIAG Diagnostic Leakage Current (pin 5) f--Vp;ns-- i-OP AMP and ClTA DC Gain C) V Constanl(lV~~ABLE -:L ____ VOIAG Vp;n 10 = 'S~k O~t~u~atu~ationVoltag~ fJp : 4~__ Vsal H+ Vsal L Total Saturation Voltage I'eakage lip VOIAG = 4 W - - - - - - tv:, VOltagetvPI~~= 100 to 800,;;v- t--V~~;~I_s_e_n;~n_g_v_olta_-g_;_(pI_n-~1-0_) _____ _~-1-2-~----,---I---- I IDiAG = 10 mA V mA --I 0.4 I i -+------L r ---- 1- 10 flA I --- 5 'I - - I =--=- -----=_-=J::-_~ :-:=1 =~-=c 09 After a time interval tmax === KC2, the output stages are disabled. See the block diagram. Allowed range of VSENS without the intervention of the short circuit protection. 3/6 219 L294 CIRCUIT OPERATION The L294 works as a transconductance amplifier: it can supply an output current directly proportional to an input voltage level (Vi). Furthermore, it allows complete switching control of the output current waveform (see fig.1). lar to t1. The peak current Ip depends on Vi as shown in the typical transfer function of fig.3. It can be seen that for Vi lower than 450 mV the device is not operating. The following explanation refers to the Block Diagram, to fig.1 and to the typical application circuit of fig.2. For Vi greater than 600 mV, the L294 has a transconductance of 1AlV with Rs = 0.2Q. For Vi included between 450 and 600 mV, the operation is not guaranteed. The ton time is fixed by the width of the Enable input signal (TTL compatible) : it is active low and enables the output stages "source" and "sink". At the end of ton, the load current Iload recirculates through 01 and 02, allowing fast current tum-off. The order parts of the device have protection and diagnostic functions. At pin 3 is connected an external capacitor C2, charged at constant current when the Enable is low. The rise time t, depends on the load characteristics, on Vi and on the supply voltage value (Vs, pin 1). During the ton time, Iload is converter into a voltage signal by means of the external sensing resistance Rs connected to pin 10. This signal, amplified by the op amp and converted by the transconductance amplifier OTA, charges the external RC network at pin 8 (R1, C1). The voltage at this pin is sensed by the inverting input of a comparator. The voltage on the non-inverting input of this one is fixed by the external voltage Vi (pin 7). After t" the comparator switches and the output stage "source" is switched off. The comparator output is confirmed by the voltage on the non-inverting input, which decreases of a constant fraction of Vi (1/10), allowing hysteresis operation. The current in the load now flows through 01. Two cases are possible: the time constant of the recirculation phase is higher than R1.C1 ; the time constant is lower than R1.C1. In the first case, the voltage sensed on the non-inverting input of the comparator is just the value proportional to Iload. In the second case, when the current decreases too quickly, the comparator senses the voltage signal stored in the R1 C1 network. In the first case t1 depends on the load characteristics, while in the second case it depends only on the value of R1.C1 . In other words, R1.C1 fixes the minimum value of t1 (t1 2 1/10 R1.C1. Note that C1 should be chosen in the range 2.7 to 10 nF for stability reasons of the OTA). After t1, the comparator switches again: the output is confirmed by the voltage on the non-inverting input, which reaches Vi again (hysteresis). Now the cycle starts again : t2, t4 and t6 have the same characteristics as t" while 13 and t5 are simi- 4/6 220 After a time interval equal to K . C2 (K is defined in the table of Electrical Characteristics and has the dimensions of ohms) the output stages are switched off independently by the Input signal. This avoids the load being driven in conduction for an excessive period of time (overdriving protection). The action of this protection is shown in fig.1 b. Note that the voltage ramp at pin 3 starts whenever the Enable signal becomes active (low state), regardless of the Input signal. To reset pin 3 and to restore the normal conditions, pin 9 must return high. This protection can be disabled by grounding pin 3. The thermal protection included in the L294 has a hysteresis. It switches off the output stages whenever the junction temperature increases too much. After a fall of about 20'C, the circuit starts again. Finally, the device is protected against any type of short circuit at the outputs: to ground, to supply and across the load. When the source stage current is higher than 5A andlor when the pin 10 voltage is higher then 1V (i.e. for a sink current greater than 1V/Rs) the output stages are switched off and the device is inhibited. This condition is indicated at the open-collector output DIAG (pin 5) ; the internal flip-flop FIF changes and forces the output transistor into saturation. The FIF must be supplied independently through Vss (pin 4). The DIAG signal is reset and the output stages are still operative by switching off the supply voltage at pin 1 and then by switching the device on again. After that, two cases are possible: the reason for the "bad operation" is still present and the protection acts again ; the reason has been removed and the device starts to work properly. L294 Figure 1 : Output Current Waveforms. V'''AB'''~;­ 'p.nJ i'on" :'! , L1-------L-. 1 i • t a) Figure 2 : Test and Typical Application Circuit. Vi ENABLE LJ"" -.I r Cl 47nF D1 : 3A fast diode 200 ns } trr$ 5 - 53'114 Figure 3 : Peak Output Current vs. Input Voltage. Ip (A) RS = 0.2 -- n V V V ~ Z V 1/ I Figure 4 : Output Saturation Voltages vs. Peak Output Current. 'Vsatr---,--r-,----,-,--T""""'-'.p-'-, (V J 1.5 0.5 '---"-_..1-_L..-1_--'--_-'------'_--' .t, -------_._------------ 'ptA) 5/6 221 L294 Figure 6 : Turn-off Phase. Figure 5 : Safe Operating Areas. Ie veE veE (A I I VI / '0 K I I rt\1 ~ 30 \ II ~ - - --- r\e \ _. --- 100 200 ---- ~ \ .:.....- r- 20 10 ""-. r-.. ]00 \ (nsec) CALCULATION OF THE SWITCHING TIMES Referring to the block diagram and to the waveforms of fig.1 , it is possible to calculate the switching times by means of the following relationships. tl =- L RL In (1 - It = - L RL In RL V1 .Ip) where: V1 = Vs - VsatL - VsatH- VRsens --_'!'!:_--_. V2 + RL . 10 Where: V2 = Vs + VOl + V02 IK<;lo<;lp 10 is the value of the load current at the end of ton. a) __~ RL t1 = t3 = t5 = ... In O:9Ip. RL + V3 Ip RL + V3 b) - R1 C1 In 0.9 In 12=t4=t6= ... =')0 where V3 = Vsat L + VR sens + VOl R1 C1 (Y1.:::.Il'..R,= ) V1 -IK RL Note that the time interval t1 = 13 = t5 = ... takes the longer value between case a) and case b). The switching frequency is always: fswltching = In the case a) the main regulation loop is always closed and it forces: IK = (0.9 ± S) Ip where : S = 3 % @ Vi = 1 V S= 1.5 % @ V, = 4 V In the case b), the same loop is open in the recirculation phase and IK, which is always lower than 0.9 Ip, is obtained by means of the following relationship. IK = Ip e __ t1Fit,__ .'!l. (1 - e _ _t1 .£lL..) L RL L With the typical application circuit, in the conditions Vs = 40V, Ip = 4A, the following switching times result: tl=255~s tf=174~s@lo=lp t . a) 70 ~s 1· b) 16 ~s t2 = 29 ~s 6/6 222 f=10.2 KHz L295 DUAL SWITCH-MODE SOLENOID DRIVER PRELIMINARY DATA • HIGH CURRENT CAPABILITY (up to 2.5A per channel) • HIGH VOLTAGE OPERATION (upto 46Vfor po· wer stage) • HIGH EFFICIENCY SWITCHMODE OPERA· TION • REGULATED OUTPUT CURRENT (adjustable) • FEW EXTERNAL COMPONENTS • SEPARATE LOGIC SUPPLY • THERMAL PROTECTION The L295 is a monolithic integrated circuit in a 15· lead Multiwatt ® package ; it incorporates all the functions for direct interfacing between digital circui· try and inductive loads. The L295 is designed to ac· cept standard microprocessor logic levels at the in· puts and can drive 2 solenoids. The output current is completely controlled by means of a switching teo chnique allowing very efficient operation. Further· more, it includes an enable input and dual supplies (for interfacing with peripherals running at a higher voltage than the logic). The L295 is particularly suitable for applications such as hammer driving in matrix printers, step mo· tor driving and electromagnet controllers. I Multiwatt 15 I L ORDER CODE: L295 ---------- ---------- ---- ABSOLUTE MAXIMUM RATINGS ~··~::I C~~~il~~~~~g:olt:ge-·VEN:V, 50 12 7 I Enable and input voltage Vref : Reference voltage 10 /' Peak output current (each dlannel) - non repetitive (t ~ 100 ~sec) - repetitive (80 % on - 20 % off ; Ton ~ 10 ms) , - DC operation i Total power dissipation (at Tease ~ 75°C) Ptat ---.:rstrJ,~to~il(l€l~~d J.1Jflction. temperatu re I v V 7 V V 3 2.5 A A 2 25 - 40 to 150 W cC A APPLICATION CIRCUIT -+- Vss --f '0 R' L 295 ~220~F e4 C2I'~f I -1 D, JL'---+9,-13.9 ~. K~F R~ C3 02 .i.l. - September 1988 - 1/6 223 L295 CONNECTION DIAGRAM (top view) ----~------ -------~------------ 15 ~ 14 13 12 ", 10 ------------------------~ OUTPUT H ch 2 OUTPUT L ch 2 CURRENT SENSING 2 REFERENCE VOLTAGE Z INPUT 2 LOGIC SUPPLY VOLTAGE Vss OSCILLATOR RC NETWORK GROUND ENABLE INPUT 1 REFERENCE VOLTAGE 1 CURRENT SENSING 1 OUTPUT L ch 1 OUTPUT H ch 1 SUPPLY VOLTAGE Vs I L 5- S&5&/1 Tab conne-cted 10 pin 8 BLOCK DIAGRAM ~: Rl " 12 l1 01 J THERMAL DATA Rth j-case Rth j-amb 2/6 224 Thermal resistance junction-case Thermal resistance junction-ambient ~ SCiS·1HOMSON --------- """'!1 IR'AJD@OOrn~Ireii'OO@IIlD@$ max max 3 35 °C/W °C/W L295 ELECTRICAL CHARACTERISTICS (Refer to the application circuit, Vss = 5V, Vs = 36V; TJ = 25'C; L = low; H = high; unless otherwise specified) ----- - ---- - - ---- Parameter Test conditio ns .. Supply Voltage Vs -------------- ------------- _. ------ Quiescent drain current (from VSS) Id Typ. Max. Unit 12 46 V 4.75 10 V 4 mA 46 mA ----- - ---- Logic Supply Voltage Vss Min. ----- -- ---- Vs = 46 V; V', = Vl 2 I is~-TQuiescent drain current I = Vss = 10 V (from VS) - .- _. Vil, Vi2 ; - - - 0.3 0.8 High 2.2 7 Low -0.3 0.8 High 2.2 7 Low Input Voltage ._- - V ----------- ---- - ---------- Enable Input Voltage VEN --- - --- _. V -- Vil -100 = ~A Input Current 111,112 10 Vil = VEN = L Enable Input Current lEN -100 ~A - 10 VEN = H 1----·_····· Vre t1, Input Reference Voltage Vref2 ._------------- Ire fl, Iref2m Input Reference Voltage Fosc Oscillation Frenquency --- ---- 0.2 1--._-- 2 V -5 ~A ---- C= 3.9 nF; R= 9. Vref = 1 V Rs = 0.5!) 25 KHz ------l- ~~! Transconductance (each ch.) Vref ! 1.9 2 AN 2.1 ~ ------ Vdrop c-----Vsens 1 Vsens2 n Vd,op = Total output voltage drop (each channel) n -_. External sensing resistors voltage drop 2.8 10 = 2 A 3.6 V 2 1~! ----- I t _---'--------1 VCEsal0l + VeEsa! Q2· 3/6 225 L295 APPLICATION CIRCUIT +Vs +Vss O.1~F ~20~F '5 10 e2 L295 04 OR'-1 -~113.91'Kll R3 02, 04 01,03 = 2A High speed diodes = 1A High speed diodes ) IIF I I e4 0' _ 02 (3 lrr5 200 ns R1 = R2 =2Q L1 = l2 = 5 mH FUNCTIONAL DESCRIPTION The L295 incorporates two independent driver channels with separate inputs and oytputs, each capable of driving an inductive load (see block diagram). The device is controlled by three microprocessor compatible digital inputs and two analog inputs. These inputs are: EN chip enable (digital input,active low) , enables both channels when in the low state. Vin1, Vin2 channel inputs (digital inputs,active high), enable each channel independently. A channel is actived when both EN and the appropriate channel input are active. Vref1, Vref2 reference voltages (analog inputs), used to program the peak load currents. Peak load current is proportional to Vref. Since the two channels are identical, only channel one will be described. the output transistors 01 and 02 switch on and current flows in the load according to the exponential law: - R1 t V (I -e L1 1= R1 where: R1 and L 1 are the resistance and inductance of the load and V is the voltage available on the load (Vs - VdropVsense). The current increases until the voltage on the external sensing resistor, RS1, reaches the reference voltage, Vref1. This peak current, Ip1, is given by : Vref1 Ip1 = RS1 At this point the comparator output, Comp1, sets the RS flip-flop, FF1, thatturns off the output transistor, 01. The load current flowing through D2, 02, RS1, decreases according to the law: - R1 t e The following description applies also the channel two, replacing FF2 for FF1 , Vref2 for Vref1 etc. When the channel is activated by a low level on the EN input and a high level on the channel input, Vin2, 4/6 226 where L1 VA = VCEsatQ2 + Vsense 1 + VD2 L295 If the oscillator pin (9) is connected to ground the load current falls to zero as shown in fig. 1. At the time t2 the channel 1 is disabled, by taking the inputs Vin1 low and/or EN high, and the output transistor 02 is tumed off. The load current flows through 02 and 01 according to the law: - R1 t VB VB 1= ( L1 + IT2 ) e R1 R1 where IT2 VB = = current value Vs + V01 + V02 at the time t2. Fig. 2 in shows the current waveform obtained with an RC network connected between pin 9 and ground. From to t1 the current increases as in fig. 1. A difference exists at the time t2 because the current starts to increase again. At this time a pulse is produced by the oscillator circuit that resets the flip flop, FF1 , and switches on the outout transistor, 01. The current increases until the drop on the sensing resistor Rs1 is equal to Vref1 (b) and the cycle repeats. The switching frequency depends on the values of Rand C, as shown in fig. 4 and must be chosen in the range 10 to 30 KHz. It is possible with external hardware to change the reference voltage Vref in order to obtain a high peak current Ip and a lower holding current Ih (see fig.3). The L295 is provided with a thermal protection that switches off all the output transistors when the junction temperature exceeds 150 "C. The presence of a hysteresis circuit makes the IC work again after a fall of the junction ternperature of about 20 'C. The analog input pins (Vref1, Vref2) can be left open or connected to Vss ; in this case the circuit works with an internal reference voltage of about 2.5V and the peak current in the load is fixed only by the value of Rs: 2.5 Ip = Rs SIGNAL WAVEFORMS Figure 1 : Load current waveform with pin 9 con nected to GNO. -._.-- - - - - - - - - l Il-,o- ---, _ Figure 2 : Load current waveform with external R-C network connected between pin 9 and ground. , 1I --~_ _____I II '2:_______ 1 v vee' EN! -p=---::-.----''------, I I I , I to 1 I I ,,1 12 1'31 14\1 I I I 1'1 I It I I ON 01 OFF 02 'f-I OFF ., 5/6 ---_._------ 227 L295 SIGNAL WAVEFORMS (continued) Figure 3 : With Vret changed by hardware. --------------- I II i I --+--I~ ---+-r-- I, : I II I: I " t -- I I t- 7i m 1- IIIL-t I I t ---7 " Switching frequency vs. values of I I: I1111 - Figure 4 R and C. 10 I I ~--- , ~ 10 6/6 228 G 8 100 8 R (Kill L296 L296P HIGH CURRENT SWITCHING REGULATORS • • • • • • • • • • 4 A OUTPUT CURRENT 5.1 V TO 40 V OUTPUT VOLTAGE RANGE 0 TO 100 % DUTY CYCLE RANGE PRECISE (±2 %) ON-CHIP REFERENCE SWITCHING FREQUENCY UP TO 200 KHz VERY HIGH EFFICIENCY (UP TO 90 %) VERY FEW EXTERNAL COMPONENTS SOFT START RESET OUTPUT EXTERNAL PROGRAMMABLE LIMITING CURRENT (L296P) • CONTROL CIRCUIT FOR CROWBAR SCR • INPUT FOR REMOTE INHIBIT AND SYNCHRONUS PWM • THERMAL SHUTDOWN The L296 and L296P are mounted in a is-lead Multiwatt® plastic power package and requires very few external components. Efficient operation at switching frequencies up to 200 KHz allows a reduction in the size and cost of external filter components. A voltage sense input and SCR drive output are provided for optional crowbar overvoltage protection with an external SCR. Multiwatt'") (15-lead) DESCRIPTION The L296 and L296P are stepdown power switching regulators delivering 4 A at a voltage variable from 5.1 Vto 40 V. Features of the devices include soft start, remote inhibit, thermal protection, a reset output for microprocessors and a PWM comparator input for synchronization in multichip configurations. ORDER CODES: L296 L296P The L296P incudes external programmable limiting current. L296HT L296PHT PIN CONNECTION (top view) 15 ~ 14 13 1 11 10 9 8 7 6 5 -$-~ ~1 I .."" CROWBAR DRIVE RESET OUTPUT RESET DELAY RESET INPUT OSCILLATOR FEEDBACK INPUT FREQUENCY COMPENSATION GROUND SYNC. INPUT INHIBIT INPUT SOFT-START CUR RENT LIMIT SUPPLY VOLTAGE OUTPUT CROWBAR INPUT Tab connected to pin 8 September 1988 1/23 229 L296-L296P ABSOLUTE MAXIMUM RATINGS Symbol Vi Vi - V2 V2 V1, V12 V15 V4, V5, V7, Vg, V13 V10 , V6 V 14 Test Conditions Unit Input Voltage (pin 3) Parameter 50 V Input to Output Voltage Difference 50 V - -1 -7 Output DC Voltage Output Peak Voltage at t = 0.1 ~sec f = 200KHz V - - - - - - -f - - - . - - - . - - - - - - ~I Voltage at Pins 1, 12 10 Voltage at Pin 15 15 V I Voltage at Pins 4,5,7,9 and 13 5.5 V i V I - - - - - - - - - -- - - - - - - - - - - - - -------- ------ Voltage at Pins 10 and 6 7 Voltage at Pin. __ 14 (114 :0; 1 mAl .. _._------- - - - - - - _.. _ - - _._...- ----j t---"'-I Vi - - - _.._------_ .. - ---J mA Ig Pin 9 Sink Current - - - - _ . _ - - _ .. 111 Pin 11 Source Current 114 Pin 14 Sink Current (V14 < 5 V) 50 mA Ptot Power Dissipation at T case 20 W - 40 to 150 °C 1-- --------- Tj, T stg 1 ! - - - - - - - . - . - - - 1---------------- - - - - - ---:-;-l 20 -- ----------- :0; ----------- f--------- ------- 90°C Junction and Storage Temperature mA Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 3 35 BLOCK DIAGRAM ..L .,... VY-, ..L ~ "r Y , ) RE.SE.T INPUT " L-----------+-H-----~L---_1 RESET " RESET OllTPUT 13 I INHIBIT INPUT 230 RESH [)[lAV 1, I ! ---I THERMAL DATA 2/23 I -j 0"0 I i I i L296-L296P PIN FUNCTIONS ----------- - - - - - - Name Function CROWBAR INPUT Voltage Sense Input for Crowbar Overvoltage Protection. Normally connected to the feedback input thus triggering the SCR when V out exceeds nominal by 20 %. May also monitor the input and a voltage divider can be added to increase the threshold. Connected to ground when SCR not used. ------- - -- - - - - - - - - + ....__.. _ ...... --_._. .-. . 2 OUTPUT 3 SUPPLY VOLTAGE Unrergulated Voltage Input. An internal Regulator Powers the L296s Internal Logic. 4 CURRENT LIMIT A resistor connected between this terminal and ground sets the current limiter threshold. If this terminal is left unconnected the threshold is internally set (see electrical characteristics). 5 SOFT START Soft Start Time Constant. A capacitor is connected between this terminal and ground to define the soft start time constant. This capacitor also determines the average short circuit output current. 6 INHIBIT INPUT TTL - Level Remote Inhibit. A logic high level on this input disables the device. 1------- 7 SYNC INPUT - - - - ~__8~_-+_ _~GROUND Regulator Output. Multiple L296s are synchronized by connecting the pin 7 inputs together and omitting the oscillator RC network on all but one device. Common Ground Terminal. 9 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. 10 FEEDBACK INPUT 11 OSCILLATOR A parallel RC networki connected to this terminal determines the switching frequency. This pin must be connected to pin 7 input when the internal oscillator is used. 12 RESET INPUT Input of the Reset Circuit. The threshold is roughly 5 V. It may be connected to the feedback point or via a divider to the input. 13 RESET DELAY A capacitor connected between this terminal and ground The Feedback Terminal on the Regulation Loop. The output is connected directly to this terminal for 5.1 V operation; it is '----____+-____________ con~ec;.~~_~a_a_di_vid_e!.-'9~ ~igh~r_vo_ltF R5 6lV llo 4.7 Cl UnF KG 'I' 4.l KG GNOo-~---------~-----------~~-----~-~~ INHIBIT C7, C8 : EKR (ROE) L1 : L ~ 300 ~LH a18 A n Core type: MAGNETICS 58930 - A2 MPP N' turns: 43 Wire Gauge: 1 mm (18 AWG) COGEMA 946044 Minimum suggested value (1 0 ~F) to avoid osciliations. Ripple consideration leads to typical value of 1000 8/23 236 ~F or higher. L296-L296P Figure 5: PC. Board and Component Layout of the Circuit of Figure 4 (1:1 scale). 9/23 237 L296-L296P Figure 6 : DC Test Circuits. Figure 6b. Figure 6a. ,V i * Voltm...r with input im~.nc: • .!:!>OMn ~------------------~ Figure 6c. I'O,uF 1·SetV1OFORVg=1 V 2· Change V10 to obtain V9 = 3 V 3 _Gv = DVg nVlO 2V *Voltme-t.r with mput !!..VlO Figure 6d. .v, 10/23 238 im~danc.~SOMll L296-L296P Figure 7 : Quienscent Drain Current vs. Supply Voltage (0 % Duty Cycle - see fig. 6a). - 45 40 U Sl10 -t 130 (mA ) .- [30 - (mAl ._. eo ;-- - I _. f- t, I .- JS 30 25 20 f-- -- I--..- 10 --- 75 70 1j - _.- -- - _. = -- 60 ;; ;---r - I 20 ~ , 65 r _. r - -- 10 Figure 8 : Quienscent Drain Current vs. Supply Voltage (100 % Duty Cycle see fig. 6a). 30 40 50 i ti " 40 r I [0 VdY) Figure 9 : Quiescent Drain Current vs. Junction Temperature (0 % Duty Cycle see fig. 6a). I j 20 r 40 Vi (V) 30 Figure 10 : Quiescent Drain Current vs. Junction Temperature (100 % Duty Cyclesee fig. 6a). 130 [30 (mA ) (mA ) +- VI :]5'1 36 80 34 75 - V i =35V 28 --- ,.. .- ,/" 65 60 26 55 24 50 ....... ~ 45 22 - f- --- 70 32 30 - - V ;--- -- , - - -- - t---I-- . - . - ;--- !-1 - .. - -- .- -r- -- .- i-- -- 40 20 -25 0 25 50 75 100 125 -25 ISO Ij (-C) Figure 11 : Reference Voltage (pin 10) vs. VI (see fig. 4). 0 ]5 50 75 100 125 ISO Tj (eo Figure 12 : Reference Voltage (pin 10) vs. Junction Temperature (see fig. 4). v'" (V) -- --10·2A c-5.125 5.150 5.100 ---- - 5.115 5.'100 5.075 f----+-+-f--+- i 5.075 _ _ 1--- -V ./~ - -j'----.. 1- -f----- -~+- I-H- j - i i 10 20 - - .- - ;-- -- -- 30 - 5.025-- e- - --- '-- 40 Vi (v) -25 ~ ~.,I SCiS-THOMSON 25 50 75 J--- 100 li(*O 11/23 ililU©Ii'd@~~~©1i'ii1@11!]U©i!J 239 L296-L296P Figure 13 : Open Loop Frequency and Phase Response of Error Amplifier (see fig. 6c). Figure 14 : Switching Frequency vs. Input Voltage (see fig. 4). . Go 5119 G. CdB I (KHz) --- f- - f - - 60 - - r- -- ) 30 20 104 - - I- - - 40 102 .ao 100 -10 10K lOOK c-- 96 .110 \ IK 9. -120 \ \ 100 --- - ~~ 10 10 yo·v.... - f-- ='\ ~ f - - 50 40 - 1= \ f (Hz) IN - 10 Figure 15 : Switching Frequency vs. Junction Temperature (see fig. 4). - 15 r- -20 25 30 35 105 40 Yj(V) Figure 16 : Switching Frequency vs. R1 (see fig. 4). "-5UI" G 411211 f (KHz I , (KHz) Vj-=:JIY 'b- V,., "' r- ......... , "0 lOS - 100 ·· · !DO f- '5 90 "::...." ~3=1.5nF I ~3"2.2nF:' 1111 10 .zs 0 zs 50 75 100 ". ~ 150 , ~, LLU , C'CI· 10 Figure 17: Line Transient Response (see fig. 4). RI(KQ> Figure 18 : Load Transient Response (see fig. 4). 6 Go Slot _I"~v'" V; I I.L Vo=Vr.f 10 ",2A - INPUT VOLTAGE - 100 r- - ~ 20 I OLnPUTYOLTAGE CHANGE 50 \ ·50 .100 -,-- - f- --f- I--- 30 I "0 (mY) -100 f--- - OUTPUT VOLTAGE 12/23 5 'ems) ~ ~""f/. 240 . t- 0.5 SGS-niOMSON Iliilll!::l!@l Plot (V) (W) 2.5 1.5 ~ i-- '1"'4A I -I-- 'Z=2A 50 Figure 23 : Power Dissipation (device only) vs. Input Voltage. 100 Figure 24 : Power Dissipation (device only) vs. Input Voltage. - , t",100KH z Vo=Vr(>f -- -- .- ~- Ptot (W) fo =5OKH z Vo =Vref -1, ~- -- 10 --f- lo=4A I"; 15 ..~ .' lo=2A +-~ lir - ~ )0 35 40 ~ M.- +I-~~45 ,- f--. -- 20 BYW8(} 1m. - 1--8~ I I "I: .. - """"-' I-- Io;2A -- '0 t--- Bvwao ~- 45 Vi (V) . ... lo=LoA bolBVW80 -~ -rr 25 - t--t- ,," BYW80 ~MBR1045 MBR 1045 20 --- 30 .0 13/23 241 L296-L296P Figure 26 : Power Dissipation (device only) vs. Output Voltage (see fig. 4). Figure 25 : Power Dissipation (device only) vs. Output Voltage (see fig. 4). 6~S21' G·I,!I'5 Ptot Vi ::35V IW) VozY,.t f-- 'Yj=35V '=looKHz Tj=I25-C r-c-- r- j0:--±:;:. ;;::.. ~ ~ ;..::::- ~ lo=2A~ I- ~~ Q::: fCC- _. 80 I--- - I 70 60 I . -"-- - -- ....- ~'/ MBR1045 - 50t(Hz 100KHz -+--t~ ~V 50 -- f~ZSKH~ ~ r- MBR1045 IIV~ ! ....:::::: 200KHz - I diod.N8R 1045 (Sch~t~~) -- -- -- 21 " 13 Yo (V) Figure 27 : Voltage and Current Waveforms at Pin 2 (see fig. 4). Figure 28 : Efficiency vs. Output Current. - ·2 f-++ (V) Vj =35V Vo",V,.f ~ I ! ---;--,- _.. - -- I") t;25KH~ Vl",35 1--- 80 70 ·2 1 30 ~ ~V 60 ~V ( A) '2 20 --- -- ~OKHz ~ 100kHz -+- . 50 I 10 r-- 200KHz I -+-- diode-MBA MU.5{Schottky 1 o 200 400 I--f- t (ns) 600 800 000 Figure 30 : Efficiency vs. Output Voltage. Figure 29 : Efficiency vs. Output Voltage. G 5252 'l I'. ) Yo :Yr.' f",lOOKHz f='50KH z / '10 .., 60 r-- - ~-:;;; f-- - ~ 80 Vj=15V V :::::- -- 70 + ~ F- ./ /' I: ~ 70 60 -~ (SCHOTTKY) - I t-i lo=2At04A YI_35V 50 DIODE ""BRI04S IJ 242 100KHz DIODE ""BRI04S 1--- 14/23 - ) r-- ."1' ~ SGS-THOMSON ~DICIB@I-659812 . _ _ _ _1 Figure 37 : 12 V110 A Power Supply, l! 1O.000JJF SOY r~ I z.z IOKfl ,12\1 nF --0 "'~ @j L .--------r~--~~ f ~':~=~ r-----. on.- I n",F 19123 247 l296-l296P Figure 38 : Programmable Power Supply. l - -...- - ~- ...- -.... -_ ...- ·--·-1 80VA rB4v~2~51~--~~--------' 20V~ 10 Kfl --_--05-5832/5 I V o =5.1t015V 10 = 4 A max. (min. load current = 100 mAl ripple <; 20 mV load regulation (1 A to 4 A) = 10 mV (V 0 = 5.1 V) line regulation (220 V ± 15 % and to 10 = 3 A) = 15 mV (V ~----.- ... - ... _ I I 0 ... = 5.1 V) _-_ .. J _-_ .•. _ .... _ .. _--._- Figure 39 : Preregulator for Distributed Supplies. L--r--~-T---~~5V n L2 and C2 are necessary to reduce the switching frequency spikes. _ _ _ .•• _ _ .• _ _ _ .••._ _ _ _ J 20/23 248 L296-L296P Figure 40 : In Multiple Supplies Several L296s can be Synchronized As Shown. Figure 41 : Voltage Sensing for Remote Load. 300,oH IOn -L- T ., " SYNC OSC - " OSC SYNC ! J L B -<)------- ., 10 II C ----t-----D- I -----.--- __J 10n GND---4------------~--~r-~5~5~"~"~" Figure 42 : A 5.1 V/15 V/24 V Multiple Supply. Note the Synchronization of the Three L296s. - .. - - ------, I 3~fi 2-- ) 3~~,14r t -Ll-+ • I 2x J1;>0I'F avWOOT40vT s- 5811 18 Kfi Vo =24V 47 /L 21/23 249 L296-L296P Figure 43 : 5.1 V/2 A Power Supply using External Lirniting Current Resistor and Crowbar Protection on the Supply Voltage (L296P only). 5.1V12A I 5-9347 .~~ .. ~----------------------------------.--.- SOFT-START AND REPETITIVE POWER-ON When the device is repetitively powered-on, the softstart capacitor, Css, must be discharged rapidly to ensure that each start is "soft". This can be achieved economically using the reset circuit, as shown in Fig. 44. The approximate discharge tirnes obtained with this circuit are: In this circuit the divider R1, R2 connected to pin 12 determines the minirnum supply voltage, below which the open collector transistor at the pin 14 output discharges C ss . If these times are still too long, an external PNP transistor may be added, as shown in Fig. 45 ; with this circuit discharge times of a few rnicroseconds may be obtained. Figure 44. Figure 45. ---~- .. eSs IDIS 2.2 ~F 4.7 ~F 10 ~F 200 ~s 300 ~s 600 ~s ------- ~--~~-------, 5 12 14 5-9479 S-91.,78 e55 22/23 250 l296-L296P HOW TO OBTAIN BOTH RESET AND POWER FAIL Figure 46 illustrates how it is possible to obtain at the same time both the power fail and reset functions simply by adding one diode (D) and one resistor (R). In this case the reset delay time (pin 13) can only start when the output voltage is Va? VREF - 100 mV and the voltage across R2 is higher than 4.5 V. put pin 12 hysteresis in order to increase immunity to the 100 Hz ripple present on the supply voltage. Moreover, the power fail and reset delay time are automatically locked to the soft start. Soft start and delayed reset are thus two sequential functions. The hysteresis resistor should be in the range of about 100 KQ and the pull-up resistor of 1 to 2.2 Kn. With the hysteresis resistor it is possible to fix the in- Figure 46. PULL- UP RESISTOR rt----71-.. . . fYn~-..-_{) va = 5.1 V o RESET OUT R 5- 9573 23/23 251 L297 L297A ~~~~~ • • • • • • • • • ~ --- --~- -----~ -- STEPPER MOTOR CONTROLLERS ~- ~-~ ~----~ ---~ ---~-~-~----- ~- -~ ------ and mode input signals. Since the phase are generated internally the burden on the microprocessor, and the prograrnmer, is greatly reduced. Mounted in a 20-pin plastic package, the L297 can be used with monolithic bridge drives such as the L298N or L293 E, or with discrete transistors and darlingtons. The L297A also includes a clock pulse doubler. NORMALIWAWE DRIVE HALF/FULL STEP MODES CLOCKWISE/ANTICLOCKWISE DIRECTION SWITCHMODE LOAD CURRENT REGULATION PROGRAMMABLE LOAD CURRENT FEW EXTERNAL COMPONENTS RESET INPUT & HOME OUTPUT ENABLE INPUT STEP MULSE SOUBLER (1297a only) The L297 Stepper Motor Controller IC generates four phase drive signals for two phase bipolar and four phase unipolar step motors in microcomputercontrolled applications. The motor can be driven in half step, normal and wawe drive modes and onchip PWM chopper circuits permit switch-mode control of the current in the windings. A feature of this device is that it requires only clock, direction ABSOLUTE MAXIMUM RATINGS -~~---11In;:~;~:;~---~-~~----Ptot 2sr~:_~ Total power dissipation (Tamb ~ lO'C) __ ~torag_e and junction temperature ~~~- TWO PHASE BIPOLAR STEPPER MOTOR CONTROL CIRCUIT CLOCK -~ " - 7 HALFIFD'lL 19 ENABLE - __ -- 110 '--T--T-...J SENSE2 cow ROc s'"c~ "0"'- -~ - 01 toOS ~ 2A FAST DIODES '---~~~~~---~----~--- September 1988 STEPPER MOTOR WINDINGS '0 Vrli'f ,qSIRS2~O_5fi +- +-+-' J 02 13 03 L298N L297 IlR r s ,1 04_-+_+-+-+-, 05 1 06 OJ 08 R" r ~------ -~-~~~~~-~ ~-~- ----- ~ 1/9 2.53 L297-L297A PIN CONNECTION (L297) - ~ SYNC 20 GNO 19 ~ HALF/FULL HOME 18 0 CLOCK 17 D CW/CCW 16 ~ A l297 INH 1 RESET OSC B 15 Vref C 14 SENS 1 INH 2 13 SENS 2 0 12 Vs 11 CONTROL ENABLE 10 5-5839 BLOCK DIAGRAM (L297) A INHl B C INH2 0 1-----+--0 ENABLE RESET (} TRANSLATOR DIRECTION (CWICCW) ClOCK t---+---~r- _.. ___ ------ 42 V; Vss ~ 5 V, T) ~ 25 OC ; unless otherwise specified) _T_e_stCo_n_d_ition~_ i Typ. Min. Max. Vss Logic Supply Voltage (pin 9) 4.5 Quiescent Supply Current (pin 4) Is I Ven=L VI =L V, = H [- Unit ---- J"llPp~)'Voltage.Jpin 4 )_______O_p~e_r_a__ ti_ve_C_o_n_d_it_io_n__ I~~_+_2_.5t-___+ _ V s_ _ I ___Parame~ ~ ------- 46 ---j_____ V _ _____ 5 f····· 7 13 V 22 - _?~.mA 50 VI=X t------t-------------+-~----~--_+----+_----r___--- I Quiescent Current from Vss (pin 9) Iss I '!.'_= L___ I 2_,"-_~ ___ VI = H I-v::;--~-L---V~=-;------ .__ 7 ___12 6 mA I 1 +-~~---~--+---+---+--- Input Low Voltage (pins 5.7,10,12) V'L - 0.3 . 1.5 f---------+-'----------'--------------+-----------------J---+-------1 Input High Voltage f - - - - - - + - " -(pins - - - -5,7.10,12) - ' - - ' - - - - ' - - ' - - - - - - - - - I - - - - - - - - - - - + ' _2_.3__...,[_ _ _ ! V,H IlL I I'H '1' Low Voltage Input Current (pins 5,7,10,12) V, High Voltage Input Current VI = H oS Vss - 0.6 V = L I_ t-=1oI . 30 . ---1-.-- ·---t- 1.5 Vss , High Voltage Enable Current 100 -.--- ; - 0.3 2.3-- ,IA -~ I V I - 10 Low Voltage Enable Current (pins 6,11) len = H Vss f ---1._("-p._in_s_5,.?:~t...~) ________ -+---------V en = L I Enable Low Voltage (pins 6,11) f---V-en-= H ---En~ble High Voltage (pins 6,11)--- - - - - - f..-._ _ _ _ V I Ven = H oS Vss - 0.6 V 30 100 IlA f -_ _ _ _+_(~p-in-s-6~,-11~)---------+_~--------i--- _LI_s_0_u_rc__8_s_a_tur_at_io_n_v_o_lt_ag_8___ 1:2_1_:_ . ____~ _V_C_E_s_a_1I_H_I _f>_:_~_-l :~ _v~ 3/9 265 L298N ELECTRICAL CHARACTERISTICS (continued) Symbol VeE sat Parameter Test Conditions Min. IL = 1 A (5) Sink Saturation Voltage (L) -.~ IL = 2 A (5) VeE IL = 1 A (5) Total Drop sat -- Typ. 1.2 _._--1.7 --- -1 T, (Vi) Source Current Turn-off Delay (4 ) (4 ) (1) 2 1.5 V ps T 2 (Vi) Source Current Fall Time 0.9 IL to 0.1 IL(2) Source Current Turn-on Delay 0.5 V, to 0.1 I L(2) T4 (Vi) Source Current Rise Time 0.1 I L to 0.9 I L(2) (4) T 5 (VI) Sink Current Turn-off Delay 0.5 Vi to 0.9 I L(3) (4) T6 (VI) Sink Current Fall Time 0.9 IL to 0.1 I L(3) T7 (Vi) Sink Current Turn-on Delay 0.5 Vi to 0.9 I L(3) (4) 1.6 ps T8 (V,) Sink Current Rise Time 0.1 IL to 0.9 I L(3) (4 ) 0.2 ,IS Ie (VI) Commutation Frequency IL = 2 A Source Current Turn-off Delay 0.5 Ven to 0.9 IL(2) T2 (Ven ) Source Current Fall Time 0.9 IL to 0.1 I L(2) T3 (V en ) Source Current Turn-on Delay 0.5 Ven to 0.1 IL i2 ) T4 (V en ) Source Current Rise Time 0.1 IL to 0.9 I L(2) T5 (V en ) Sink Current Turn-off Delay 0.5 Ven to 0.9 I L(3) T 6 (V en ) Sink Current Fall Time 0.9 IL to 0.1 IL(3) T?(Ven) Sink Current Turn-on Delay 0.5 Ven to 0.1 I L(3) Ts (V en ) Sink Current Rise Time 0.1 IL to 0.9 I L(3) Ie (V en ) Commutation Frequency IL = 2 A (4) (4 I 0.2 ps 2 ,IS 0.7 ps 0.7 ps 0.25 lIS 25 (4 ) (4) (4 ) (41 i4 ) 141 (4 ) (4 ) 40 3 Figure 1 : Typical Saturation Voltage vs. Output Current. J-ls ps 0.3 ,IS 0.4 ,IS 2.2 ps 0.35 ps 0.25 ,IS 0.1 J-lS 1 KHz Figure 2 : Switching Times Test Circuits. J. VSAT (V) Vs=42V vss =5V H 2.4 /L 2.0 / 1.6 ,/' ~ /' 1.2 0.8 --- 0.4 o 0.4 0.8 '.2 '.6 2.0 2.4 Io(A) KHz 1 1) Sensing voltage can be -1 V for t ~ 50 )lsec; in steady state Vsens min:::: - 0.5 V. 2) See fig. 2. 3) See fig. 4. 4) The load must be a pure resistor. 5) PIN 1 and PIN 15 connected to GND. 266 V T 3 (Vi) T, (V en ) 4/9 V 4.9 Sensing Voltage (pins 1, 15) 0.5 Vi to 0.9 I L(2) 1.62.3 3.2 IL = 2 A (5) Vsens Unit rMax~ - 5o_S85211 Note: For INPUT Switching, set EN = H For ENABLE Switching, set IN = H L298N Figure,3 : Source Current Delay Times vs. Input or Enable Switching. ,...-----------~-~-.- Imax(2A) 90·'. - 10·1. - " -- -- -----T1 Ven · (4V) I 50.1. ..- - - - - -------------7 \;:-----------.7 T3 T2 ~ \.-----------------11' J r t T4 t 5_ 5853/2 Figure 4 : Switching Times Test Circuits. VSS=5V VS=42V Note: For INPUT Switching. set EN = H For ENABLE Switching, set IN = L 5/9 267 L298N Figure 5: Sink Current Delay Times vs. Input 0 V Enable Switching. go-,. --+------_-_-_-_-_-_-_-_-_-_-_-_-_-j-_-:-r.,.--- Imax(2A) \---- -------.A 10"1. - T7 T6 TI .1 {---------------\ I ma.(2A) 90". 10 .,. ---:- -.- - -_/_------- -'\=---------.--(---~- \ T7 T8 T5 1 - -- - -- T6 .1 y---------- -----\ 5-10667 - - - - - - - - - - - - _ .. _-------- Figure 6 : Bidirectional DC Motor Control. Inputs Function ! C = H; D = L I Ven = H C = L; D= H Ven=L C=X, D=C Turn Right Turn Left r,~ . fC-._=_==_D~-.~~~~~~;=F=a=st=M=--o!=-o-r--S--t-o-p---_---11 "I . TO CONTROL CIRCUIT l' L= Low ~I o RS 01 TO D4;IA FAST RECOVERY DfODE(trr-'!200n5) 6/9 268 ~ H = High Free Running Motor Stop x == Don't care L298N Figure 7 : For higher currents, outputs can be paralleled. Take care to parallel channel 1 with channel 4 and channel 2 with channel 3. ---------- Vs Vss fOO nF 9 :J.. ENABLE INI OUT 1 IN 2 OUT 2 10 13 12 14 APPLICATION INFORMATION (Refer to the block diagram) 1.1. POWER OUTPUT STAGE The L298N integrates two power output stages (A ; B). The power output stage is a bridge configuration and its outputs can drive an inductive load in common or differenzial mode, depending on the state of the inputs. The current that flows through the load comes out from the bridge at the sense output: an external resistor (RsA; RSB.) allows to detect the intensity of this current. 1.2. INPUT STAGE Each bridge is driven by means of four gates the input of which are In1 ; In2 ; EnA and In3 ; In4 ; EnB. The In inputs set the bridge state when The En input is high; a low state of the En input inhibits the bridge. All the inputs are TTL compatible. 2. SUGGESTIONS Each input must be connected to the source of the driving signals by means of a very short path. Turn-On and Tum-Off: Before to Turn-ON the Supply Voltage and before to Turn it OFF, the Enable input must be driven to the Low state. 3. APPLICATIONS Fig 6 shows a bidirectional DC motor control Schematic Diagram for which only one bridge is needed. The external bridge of diodes 01 to 04 is made by four fast recovery elements (trr <; 200 nsec) that must be chosen of a VF as low as possible at the worst case of the load current. The sense output voltage can be used to control the current amplitude by chopping the inputs, or to provide overcurrent protection by switching low the enable input. A non inductive capacitor, usually of 100 nF, must be foreseen between both Vs and Vss, to ground, as near as possible to pin 8 (GND). When the large capacitor of the power supply is too far from the IC, a second smaller one must be foreseen near the L298N. The brake function (Fast motor stop) requires that the Absolute Maximum Rating of 2 Amps must never be overcome. The sense resistor, not of a wire wound type, must be grounded near the negative pole of Vs that must be near the GND pin of the I.C. An external bridge of diodes are required when inductive loads are driven and when the inputs of the When the repetitive peak current needed from the load is higher than 2 Amps, a paralleled configuration can be chosen (See Fig.?). 7/9 269 L298N IC are chopped; Shottky diodes would be preferred. Fig 9 shows an example of P.C.B. designed for the application of Fig 8. This solution can drive until3 Amps In DC operation and until 3.5 Amps of a repetitive peak current. Fig 10 shows a second two phase bipolar stepper motor control circuit where the current is controlled by the I.C. L6506. On Fig 8 it is shown the driving of a two phase bipolar stepper motor; the needed sig nals to drive the inputs of the L298N are generated, in this example, from the IC L297. Figure 8 : Two Phase Bipolar Stepper Motor Circuit. This circuit drives bipolar stepper motors with winding currents up to 2 A. The diodes are fast 2 A types. '5 l6V '.lnf Z osc 16 11 A 4 8 c STEPPER MOTOR WINDINGS CONTROL 5-5846/4 RS1 = RS2 = 0.5 Q Dl to D8 2 A Fast diodes { VFS1.2V@I=2A trr S 200 ns _______________________ 8/9 270 I L298N Figure 9: Suggested Printer Circuit Board Layout for the Circuit of fig. 8 (1 : 1 scale) Figure 10: Two Phase Bipolar Stepper Motor Control Circuit by Using the Current Controller L6506. 5" :J6U 1senF EN.B EN.A RESET 14 13 PHASE INPUTS { • 5" 22. L5585 12 1. 11 12 L298N 1~ ~1=r=:;Hh 11 22' 15 ,. 14 • f-f-f-HH 17 3.9nF" 1 •• nS8L2!JBN-Bt RR and Rsense depend from the load current 9/9 271 L387A VERY LOW DROP 5V REGULATOR PRECISE OUTPUT VOLTAGE (5 V ± 4 %) VERY LOW DROPOUT VOLTAGE OUTPUT CURRENT IN EXCESS OF SOOmA POWER-ON, POWER-OFF INFORMATION (RESET FUNCTION) • HIGH NOISE IMMUNITY ON RESET DELAY CAPACITOR L387 A particularly suitable for microprocessor systems. This output provides a reset signal when power is applied (after an external programmable delay) and goes low when power is removed, inhibiting the microprocessor. An hysteresis on reset delay capacitor raises the immunity to the ground noise. • • • • DESCRIPTION The L387A is a very low drop voltage regulator in a Pentawatt® package specially designed to provide stabilized SV supplies in consumer and industrial applications. Thanks to its very low input/output voltage drop this device is very useful in battery powered equipment, reducing consumption and prolonging battery life. A reset output makes the Pentawatt® ORDER CODE: L387A '----_.---------------- ABSOLUTE MAXIMUM RATINGS r Sym-vl-bo-,-' F~~';;;;;~lnput VOlt~-ge--p-ar.!.m-e-t-er -~-----.J. -==V_:I~e . 'T:~I Oper~ti-;;-g T~~p~rature R~nge· US~g, TJ I-Storage --=]--JJ~it-1 - 40 to + 125 ~~d Junction Tempe_ra_tu_re_ _ _ _ _ _ _ ._. ___ -_40_tO_+_15_0_ °C I '£J .. APPLICATION CIRCUIT OUTPUT VOL TAGE I Nv--._---l I lOOn F 5 " t-~---.--U. L387 A U I KJl J200~F 5V * RE ET OUTPUT 5-5636/1 • Min 33 ~F and max. ESR September 1988 0; 3 Q over temperature range. 1/4 273 L387A CONNECTION DIAGRAM (top views) L1:l @ \V II 51 4 1 +VOUT : DELAY CAPACITOR (Cd) :~ / (tab connected to pin 3) '"'' ~"::~ 5 - 5307 L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ _ _ _ _ _ _ ..._ _ _ _ ... _ _ _ _ _ . _ _ _ . BLOCK DIAGRAM - _..- - _ . - - - _ . _ - _ . _ - - - - - - - - - - - _ . _ - _ . _ - - - - - - - - ----------- OUTPUT INPUT 10~~--------------------~------- --------1>----05 RESET OUTPUT --1--v2 GROUND Cr-~------+-----~--~--~------~--------~---~-----~-Q) THERMAL DATA Rth 274 j·e a s e I Thermal Resistance Junction-case Max I 4 'c/w I l387A ELECTRICAL CHARACTERISTICS (refer to the test circuit, V, = 14.4 V, Tj = 25 DC, Co = 100 IlF; unless otherwise specified) ~mboll_=-~param-eter - 1I ~ Vo V, t- -- - ~!est Cond~ClI1.s ~- mA to 500 mA ,n. O~er F~I-T Ra~ge tlli1i~ TYP-"-11- lIi1ax . T J = 25 DC 4 80 5 00 40 "' T J "' 125°C 4 75 I 5 00 (- 40 to 125°C) - - - - : - - - - - ,(see note H) I II" Unit 5.20 5 25 26 -~I V t--I V I' ~~ot~,::;- !~.:: ~~'~~:O;;;A-,=5'''------l 155t-~-1 :~ V, - ' ~ =5 Output Voltage Operating Input Voltage I I t ~a -Dropout Voltage II: = '1 nl-A--;-~-~----=-1 0 0 - - ; - 350 10 = 500 mA Quiescent Current 0 - 0 NOM m 0.40 r-D.'6-5-r0.60 • 0,8 : I - 0 mA I: : 150 mA 10 =350 mA 'I 5 20 60 I ' I V I 15 35 100 j I =~2V----' -:: :~~~ :~----l ~~~ T~:~I I [20==3~gO:~ _0~ ~~.~ ~z± 5~_ ---+ h t mA ,1/; Temperature ! Output Voltage Drift, ~~j:~~o~oltage IA = 16 mA Voltage 1.5 < Vo < 4.75 V _OverFu~T(:::~ DC _"' T J "'~5 DC) Reset Output Leakage Current Vo in Regulation Over Full T Range --- Delay Time for Reset _.. Output ._--- Cd = 100 nF Over Full T Range _._.. Charging Current (current generator) V4 = 3 V __ __ __. _ - _ . r-V_AT_(O_II_)+-___._ _ _ _+-~~II~ ::~~teout H to L Transition,.:v_e_r_ IC4 VAT (on) Power on 1--_ _-+-_V._oThresh.'l~ , mV;oC 'I l' T-r I ~~:;n~utPut-- IA.:3mA-----.1g I. OUT 1 17 OUT 2 16 OUT 3 ~ 15 OUT 4 iN 5 ,. OUT 5 iN 6 13 OUT 6 iN 7 " OUT 11 OUT 8 IN • GND 10 ~~~~~I%GF~I~~ES 5-349011 ----- SCHEMATIC DIAGRAMS L601 L602 COM __------~--.-~aUT iNo-~--------~~ I L-J+--------- _J EACH DRiVER 5- 31.89 L603 L604 i 2.7kn iN 0 r--e:::J- --r I ~-+ -~--oOUT ~----< • , L~ L -1+- EACH DRIVER 2/3 278 i t..... L-J+s- 1989 EACH DRIVER _ J 5_2574 L601-L602-L603-L604 THERMAL DATA ELECTRICAL CHARACTERISTICS (Tamb = 25 'C, unless otherwise specified) SY;;'-b~-'T-- ----- ---- Test conditions Parameter T' Mi;- ~TY~. =LMaX'-rU~itj 1 -- --- ICEX .1 Output Leakage Current VCE ~ 90V ------ VCE!, a II i Collector Emitter Saturation r-_~~e~ h FE DC Forward Current Gain (L601 only) ----- V, .... - - - - - V, Minimum Input Voltage (ON condition) ----- ----- ---- Maximum Input Voltage (OFF condition) 1---Clamp Diode Reverse IR Current VF Ic Ic Ic ~ ~ ~ VCE Ic 3V ~ --- - ~ 1.7 1.2 f-- t - - 1--- - -- c--- ----- 0.55 7 0.75 -- f--- .- t--2 Turn·on Delay 0.5 V, to 0.5 Vo to ff Turn-off Delay 0.5 V, to 0.5 Vo ---- ----- 11.5 2.5 5 V V V ---- ---- V V V V . _ - - ---50 flA 2.4 V - - 0.4 -- V V V 25 flA 300 mA 1------ -1- - 1000 --- flA 300 mA --- ~ 10 --C- 2 , 300 mA ------ I 90 V ton I- ~ ---- - ---- Ic VeE ~ 3 V for L602 for L603 for L604 f-------VCE ~ 90 V Ic for L601 for L602 for L603 for L604 IF~ - - ~ ----- 18 ~ 500 ,LA 18 ~ 350 flA 18 ~ 250 flA 300 mA 200 mA 100 mA ------- ---- VR Clamp Diode Forward Voltage ------ ---------- --- f-- 0.4 . fls ---- --- fls 3/3 ----- - - - - - - - - 279 L702 2A QUAD DARLINGTON SWITCH - -- - - - - - - - - - - - - - - - ----I • SUSTAINING VOLTAGE: 70 V .2 A OUTPUT • HIGH CURRENT GAIN • IDEAL FOR DRIVING SOLENOIDS, DC MOTORS, STEPPER MOTORS, RELAYS, DISPLAYS, ETC. . •. •._•. .•. .• .• . .•.•. . .• . .• .• • .• . . •. . . •. . . n •....•....••.•.... \',"'-,,,,,\-.,, , -""',"'"\,,,",,,,,,\\ Multiwatt-11 DESCRIPTION The L702 is a monolithic integrated circuit for high current and high voltage switching applications. It comprises four darlington transistors with common emitter and open collector suitable for current sinking applications mounted on the new POWERDIP and Multiwatt® packages. Powerdip 8 + 8 ORDER CODES: This circuit reduces components, sizes and costs; it can provide direct interface between low level logic and a variety of high current applications. L702B - Powerdip L702N - Multiwatt ABSOLUTE MAXIMUM RATINGS ------------- --- --- -- Parameter Symbol Value --90 - _I Unit U ---.~---- VCEX V, Collector-emitter Voltage (input open) ._--- -- - - - Input Voltage ---------- - - - ------ Ic PIal V . _ -f---- Collector Current 3 A 4 W Total Power Dissipation at Tease oS 90 'c } Powerdip Multiwatt ---_._- T) V Total Power Dissipation at Tpin 9 to 16 oS 90'C Total Power Dissipation at Tamb oS 70'C TSl g i . - - - -c---- . 30 -- .--- 1.1 W 20 W --_._------f---- Storage Temperature -55to 150 °c Operating Junction Temperature - 25 to 150 ·C ------,~----- September 19_88 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ 1/4 281 L702 STEPPING MOTOR BUFFER -- ~I· ~·~~f I 1 L 7028(N J 01) Zl! ~ '}'-F-k~~'ffi '~.v Q1 , (10) 11" I Z1 '~,eell" 1, I __J -Q ... ... 6 I) 8c=J-r< 141 Z4 I,oo.uF I) 9 15 6) ,,- J"~" CONNECTION DIAGRAMS (top view) Powerdip Multiwatt ---.---~~ ~. -~~- 5-31,80/Z 81 1 ~ 16 -$- I 82 1 15 3 14 C2 4 13 5 12 C4 6 11 Cl GND C3 83 7 84 ~ 10 9 nc a Cl 7 C2 6 GND 5 C3 C4 3 nc 2 63 64 ~ e THE TAB 15 CONNECTED TO PIN 6 --~----- SCHEMATIC DIAGRAM (each Darlington) ----------------~------- C 34011 --4----4--<1 GND 5-3486/1 282 61 62 4 --~- 2/4 11 10 5-3749 L702 THERMAL DATA R1hj-amb Thermal Resistance Junction Ambient Rth j-pins 9/16 Thermal Resistance Junction Pins 9 to 16 Rth J-case Thermal Resistance Junction-case } Powerdip Max 70 'C/W 14 Multiwatt Max Max 'C/W 'CIW ELECTRICAL CHARACTERISTICS (Tease = 25 Symbol Parameter - - - -- - - - I CEX -------------- - - - - --- Output Leakage Current n Sustaining VCEls u s II VCEls all Collector Emitter Saturation Voltage Test conditions Vi Ton Toff --- Min. --- Typ. Max. Unit 10 50 (lA - 70 Ic = 100 mA V -----1-._---_._--------------- - - - -1----- ---1_9 Ic = 1.25 A 1.3 Ii =2mA DC Forward Current Gain 1000 Ic = 1 A VCE = 3 V -----,-~ Ii unless otherwise specified) VCE = 90 V Collector Emitter Voltage hFE r---- 'c 3 - - _ .._- - - ._--- Input Current V 4000 [---- Vi=3.75V 7 V, = 2.4 V 3 Open Collector - - - - - - - - - -1 - - - - - - - - - - - - - -------Off Condition Ic <: 0.1 mA Input Voltage VCE=70V -------On Condition 2.4 VCE = 3 V Ic21 A -----0.3 Turn On Time Vs=12V 1 Turn Off Time RL = 10 n --- - - - 11 mA mA 6 0.4 I Figure 1 : Switching Time. ----- I ----V V ._-- ~-- Figure 2 : ton and toff Test Circuit. Vio------! >-------Ovo JLzv ton toff 3/4 283 L702 ~----~~---.----- Figure 3 : Peak Collector Current vs. Duty Cycle and Number of Outputs (L702B only). Figure 4 : Collector Emitter Saturation Voltage vs. Collector Current. t-f- G·40e9 ) ) ) Tamb =70 0 C t--t- j-j--- I- T::::1QOms I~ 1.5 - - -~ f-+j- - ..I"V 2 0.5 1---- ~:;;; - - - 3 4t-- t-- f-i F f-17?'-~ V l-l _/v V__ hFE060t t- - - ~~ _~;2"'- ~ ~+ 1 -~ ~ 1-1- I~- G-360J t- 1-1 I : r -ft -, ~ r . II ' ; ,J- f-- -f.-I-~ 1-+-+I ; ICIA) 10"1. Figure 5 : Collector Current vs. Input Voltage. Figure 6 : Input Current vs. Input Voltage. G-3601 G-J602 T Ie - CA ) - t - ~~ f7' f-I- -I-- f-j ~- t-I 1-- t- I-- f-rf lf-f-- VeE ",3V I~I-I-- \f-l-- l--I-l--l-l-- -I-- I-- l-- - L I-- t- tt J +-+- -+- t- ~ a~1 I GJ6 Ie " CA) • r-- ,,"----- ~_L SINGLE PULSE H oe "E ,"f::=I--- f-' I-, I--- 40 _.1-fI-- I--f-- V 1--1-- -t- -- t- - - +-IIf-V 11 II i :~ 10 20 ttVj (V) Figure B : Safe Operating Areas (L702N). G-408211 Ie · f4=1: ttT SINGLE PULSE __ L~ I 500IJ 1\: De ,- I\. 50 ,us · " l\ , I--- ~- I ·, " , I--~ I t- - I--- 20 j-- 1 V -~ -- ~i=- 10 -2 p-V - ',// 30 f- 5ms ! sOOps' !/50jJS - i- l- ., , - f- 1--++ I'" ,- - 50 CA) ] , 60 I-- +.-t- Figure 7 : Safe Operating Areas (L702B). --t- -t- 1-- I-- I-f- 10 t- Il Cm ~- I- I--t-.~ - --- th" l:;:;pl-- , ." 10 I 10 1 2 1 ." I i 10 4/4 ~----- 284 ~~---- L2720/2/4 LOW DROP DUAL POWER OPERATIONAL AMPLIFIERS PRELIMINARY DATA • • OUTPUT CURRENT TO 1A OPERATES AT LOW VOLTAGES • • SINGLE OR SPLIT SUPPLY LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE • • • LOW INPUT OFFSET VOLTAGE GROUND COMPATIBLE INPUTS LOW SATURATION VOLTAGE • • They are particu larly indicated for driving, inductive loads, as motor and finds applications in compact-disc VCR automotive, etc. The high gain and high output power capability provide superior performance whatever an operational amplifier/power booster combination is required_ '" ~ " ..............•........••..•... C'> \ THERMAL SHUTDOWN . ......• ., CLAMP DIODE The L2720, L2722 and L2724 are monolithic integrated circuits in powerdip, minidip and SIP-9 packages, intended for use as power operational amplifiers in'a wide range of applications including servo amplifiers and power supplies. , , Powerdip (8 + 8) , />. .<;<.,),<+i>. :""0, \ ~/.'" /"". a I \ \ Minidip Plastic SIP-9 ORDERING NUMBERS: L2720 L2722 L2724 ABSOLUTE MAXIMUM RATINGS Supply voltage Peak supply voltage (50ms) Input voltage Differential input voltage DC output current Peak output current (non repetitive) Power dissipation at Tamb = 80°C (L2720), Tamb = 50°C (L2722) T case = 75°C (L2720) . Tease = 50°C (L2724) Storage and junction temperature 28 50 Vs ± Vs 1 1.5 1 5 10 -40 to 150 V V A A W W W °c BLOCK DIAGRAMS --03 L2720 June 1988 L2722 L2724 1/7 285 L2720/2/4 CONNECTION DIAGRAMS (Top view) ,---iF==9i\:===JNPUT-l 16 GNO OUTPUT t 15 GND SUPPLV VOLTAGE 14 GND 13 GND INPUT -2 12 GNO JNPUT.2 11 GHO INPUT., 10 GND INPUT -1 9 OUTPUT 1 OUTPUT 2 1 3 GND .2 8 INPUT_I 7 INPUT+! OUTPUT 2 6 INPUT.2 GND 5 INPUT_2 1~==::>JNPUT+l INPUT+2 o 1i===:>JNPUT-2 1t:::==:>GNO N.C. I~==:::>OUTPUT 2 1F===vs L2722 '---~4J...lJJl====OUTPUT 1 5-9748 GNO L2724 S-~905 L2720 SCHEMATIC DIAGRAM (one section) .v" THERMAL DATA Rth j-case Rth j-amb Thermal resistance junction-pins Thermal resistance junction-albient SIP-9 Powerdip Minidip max max • Thermal resistance junction-pin 4. ~2/~7_________________________ ~~~~~~~~:9~ 286 --------------------------- L2720/2/4 ELECTRICAL CHARACTERISTICS (Vs = 24V, Parameter Vs Single supply voltage Vs Split supply voltage Is Quiescent drain current Tamb = 25°C unless otherwise specified) Test Conditions Min. TVp. Max. 4 28 ±2 ± 14 Unit V = Vo Vs Vs 2 Vs ~ 24V 10 15 = 8V 9 15 0.2 1 !J.A mA Ib Input bias current Vos I nput offset voltage 10 mV los Input offset current 100 nA SR Slew rate B Gain-bandwidth product Rj Input resistance Gv O.L. voltage gain eN f = 100Hz f = 1KHz 1.2 MHz Kn = 22Hz to 22KHz 70 80 dB 60 Input noise voltage IN Input noise current CMR Common Mode rejection f SVR Supply voltage rejection f = 100Hz RG = 10Kn VR = 0.5V = 1KHz VDROP (HIGH) 10 !J.V 200 pA 66 84 dB 60 70 75 80 dB dB dB Vs Vs Vs = = = 24V ±12V + - 6V Ip = 100mA 0.7 Ip = 500mA 1.0 V Vs = ±2.5V to VDROP(LOW) 1.5 ± 12V Ip = 100mA 0.3 Ip = 500mA 0.5 V Channel separation f = 1 KHz RL = 10n Gv Tsd V/!J.s 500 B Cs 2 = 30dB Vs = 24V Vs - 6V Thermal shutdown 1.0 60 60 dB 145 °c junction temperature ___________________________ ~~~~~~~~~~ ________________________~3/~7 287 L2720/2/4 Fig. 1 - Quiescent current vs. supply voltage Fig. 2 - Open loop gain vs. frequency Fig. 3 - Common mode rejection vs. frequency, "" ·163 (dB ) 10 (mA}H+-+-H+t-I-t--t--H++-lI-i 60 70 "'. ""5",24'1 '"'" 60 50 40 30 20 I"'. '" 10 12 16 20 24 10' I'" '" - "'. 10' Fig. 5 - Output swing vs. load current (Vs = ± 12V) Fig. 4 - Output swing vs. load current (Vs = ± 5V) G-&164 (v I (V ) Vs ,,!5V Vs:!11V 13 -.. I" - 11 ~ ~~E ~~ r- 400 600 - -- l- I- - 1--- -- I--- f--- "'- I ~~E---- --~~ ~f:"-' I--- \0 100 'LOAO(mA) Fig. 6 - Supply voltage rejection vs. frequency 600 400 Fig. 7 - Channel separation vs. frequency G-61S2 (d B) Vs: G-G!3' (dB ) 1 121/ ~~"'€:B '0 l- 70 i'. 50 "" 40 20 .......- ~t-t re--- ! I---t 10' I{Hz) 4~/~7-------------------------~~~~~~~~T:~~©~ 288 i "" 50 30 10' 1 2V 70 I ! I i , I i i I i 10 ___________________________ L2720 12/4 APPLICATION SUGGESTION In order to avoid possible instability occurring into final stage the usual suggestions for the linear power stages are useful, as for instance: layout accuracy; A 100nF capacitor connected between supply pins and ground; boucherot cell (0.1 to 0.2 pF + H1 series) bet· ween outputs and ground or across the load. With single supply operation, a resistor (1 KQ) between the output and supply pin can be necessary for stabi I ity. Fig. 8 - Bidirectional DC motor control with pP compatible inputs V Sl = logic supply voltage Must be V S2 E 1, E2 = > V S1 logic inputs s _ ~93111 Fig. 9 - Servocontrol for compact-disc REFLECTED BEAM LASER Fig. 10 - Capstan motor control in video recorders DIGITAL INPUT - - - - - - - - - - - W'l SCS-THOMSON '], " 5/7 ~~©iru@~~:!©'firu@fiilfl©:!i 289 L2720/2/4 ~--------------------------------------------------------------------- Fig. 11 - Motor current control circuit R7 RS 2.SKn. 36KO IOKO 2.SKO 2·,. 50_593011 Note: The input voltage level is compatible with L291 (5-BIT D/A converter! Fig. 12 - Bidirectional speed control of DC motors. For circuit stability ensure that Rx> 2R3 o R1 where RM = internal resistance of motor. The voltage RM V 2R Rl available at the terminals of the motor is VM = 2 ( VI - __s__ ) + IRol. I M where I Rol = - - - - and 2 Rx I M is the motor current. 0 Rx Vin Rl 10Kn R2 lOKn -'6/_7_ _ _ _ _ _ _ _ _ _ _ _ _ 290 IOKn ~ ~~~~m~1J~:~~©~ -------------- L2720/2/4 Fig. 13 - VHS-VCR Motor control circuit LOAOING MOTOR CASSETTE MOTOR uP fM\ CAPSTAN ~ L2720 ZB + ORUM ®M MOTOR L2720 ..... TDA 8114 RESET ____~_____________________ RIGHT LEFT REEL TACHO MOTOR 0 0 ~~~~~~~,~~ VHS2::0IS 5-9482 ________________________~7/~7 291 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L2726 LOW DROP DUAL POWER OPERATIONAL AMPLIFIER ADVANCE DATA It is particularly indicated for driving inductive loads, as motor and finds applications in compact-disc VCR automotive, etc. • OUTPUT CURRENT TO 1A • OPERATES AT LOW VOLTAGES • SINGLE OR SPLIT SUPPLY • LARGE COMMON-MODE AND DIFFERENTIAL MODE RANGE • LOW INPUT OFFSET VOLTAGE • GROUND COMPATIBLE INPUTS • LOW SATURATION VOLTAGE • THERMAL SHUTDOWN • CLAMP DIODE The high gain and high output power capability provide superior performance whatever an operational amplifier/power booster combination is required. L'/~~ The L2726 is a monolithic integrated in SO-20 package intended for use as operational amplifiers in a wide range plications including servo amplifiers and supplies. 2~"' circuit power of appower 80-20 (12+4+4) 1 ORDER NUMBER: L2726 ABSOLUTE MAXIMUM RATINGS 28 50 Vs ± Vs 1 1.5 Supply voltage Peak supply voltage (50ms) I nput voltage Differential input voltage DC output current Peak output current (non repetitive) Power dissipation at Tamb = 85°C Tease = 75°C Storage and junction temperature BLOCK DIAGRAM 1 5 -40 to 150 V V A A W W °C +vs 12 20 11 10 2 9 4~7 Jj4~j7 L2726-1 .- DIS June 1988 1/4 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 293 L2726 CONNECTION DIAGRAM (Top view) +vs OUT 2 N.C. GND GND GND GND N.C. N.C. GND GND GND GND N.C. IN 2 (-) IN 1 (-) IN 2 (+) IN 1 (+) L2726-2:: DIS SCHEMATIC DIAGRAM (one section) THERMAL DATA Rth j-case Rth j-amb Thermal resistance junction-case Thermal resistance junction-ambient (*) max max 15.0 65 (*) With 4 sq. cm copper area heatsink ~2/~4_________________________ ~~~~~~?~:~~ 294 ___________________________ L2726 ELECTRICAL CHARACTERISTICS (Vs = 24V, Parameter Vs Single supply voltage Vs Split supply voltage Is Qu iescent drain current r--' Tamb = 25°C unless otherwise specified) Min. Test Conditions Typ. Max. 4 28 ±2 ± 14 Unit V Va ~ Vs Vs 2 Vs ~ 24V 10 15 ~ 8V 9 15 0.2 1 /lA mA Ib Input bias current Vas I nput offset voltage 10 mV los Input offset current 100 nA SR Slew rate B Gain-bandwidth product Ri Input resistance Gv O.L. voltage gain 2 V//ls 1.2 MHz Kn 500 f ~ 100Hz ~ 1KHz 70 80 dB f eN Input noise voltage IN Input noise current CMR Common Mode rejection f ~ SVR Supply voltage rejection f ~ B ~ RG VR 60 10 /lV 200 pA 66 84 dB 60 70 75 80 dB dB dB 22Hz to 22KHz 1KHz 100Hz 10Kn 0.5V Vs Vs Vs ~ ~ VDROP (HIGH) ~ ~ .- 24V ±12V ± 6V Ip ~ 100mA 0.7 Ip ~ 500mA 1.0 Ip ~ 100mA 0.3 Ip ~ 500mA 0.5 V Vs ~ ±2.5V to ± 12V VDROP(LOW) Cs Tsd 1.5 V Channel separation Thermal shutdown f ~ 1KHz RL ~ 10n G v ~ 30dB 24V Vs Vs - 6V ~ I 1.0 60 60 dB 145 °c junction temperature 3/4 295 L2726 Fig. 1 - Quiescent current vs. supply voltage Fig. 2 - Open loop gain vs. frequency Fig. 3 - Common mode rejection vs. frequency, . ••, , 0-616J (dB (08 I 70 ""- +" 'Is ~ 24 V ""- 50 ...... ""- 70 " "5=24'1 I- 10' - ~j . 1""- ""- r*Ht ""- - ""- 11-- f 1 I ""- 10' 0·6128 G-616' (' "'s.! I 1= -I··· i 'Is: ! 12'1 5V -~ -- I L I -- - ~ "- i - -- I- ,- ~ ........ ........ ~~E ~I~ - f (Hz) Fig. 5 - Output swing vs, load current (V s = ± 12V) Fig. 4 - Output swing vs. load current (Vs = ± 5V) (V ) 10 4 ~GATIVE - ~~ ::-r=::: ~ ~ 10 r-- - 200 400 100 600 Fig. 6 - Supply voltage rejection vs. frequency 600 ILOAO(mAl Fig. 7 - Channel separation vs. frequency 0-6162 (dB I L G-6131 (dB I --- 'i,;=S'12V ~', "\g:E 80 70 60 '0' " ....... 70 "I'\.I\. 60 70 20 I I ~--tl i I , I 10' ~4/~4___________________________ ~~~~~~g~:~~~ 296 '" ,./ 50 I 10~ f(H z) _____________________________ ..r== .,L SGS-THOMSON ~D©[ru@~[]J~©'[j'[ru@~D©~ L3654S PRINTER SOLENOID DRIVER The L3654S is a printer solenoid driver containing ten open-collector d river outputs and a ten-bit serial-in, parallel-out register. Data is clocked into the shift register serially and transferred to the open-collector outputs by an enable input. Serial input data is loaded by the rising edge of the clock. A serial output from the tenth bit is provided which changes at the falling edge of the clock. This output is not controlled by the enable input and remains active at all time. clamped to ground internally at 50V to dissipate stored energy in inductive loads. The L3654S is supplied in a 16 lead dual in-line plastic package, and its main fields of application comprise thermal printers, cash registers and printing pocket calculators. DIP-16 Plastic (0.25) The L3654S is pin to pin compatible with the standard L3654, but can work with V. down to 4.75V. Each output is rated at 250mA (sink) and is ORDER ING NUMBER: L3654S ABSOLUTE MAXIMUM RATINGS Supply voltage Input voltage External supply voltage OUtput current (single output) Ground current Total power dissipation (Tamb = 70°C) Storage and junction temperature V. Vi VE 10 19 Ptot Tst9' T j 9.5 9.5 45 0.4 4.0 1 -65 to 150 V V V A A W °C BLOCK DIAGRAM OUTPUTS 10 V OUTPUT 1 EN ENABLE V 01 DATA INPUT 5 - 5013/1 June 1988 1/4 297 l3654S CONNECTION DIAGRAM (top view) OUTPUT ENABLE 1 [ 16 Vs OUTPUT 6 2[ 15 OUTPUT 5 OUTPUT 7 3( 14 OUTPUT 4 OUTPUT 8 4[ 13 OUTPUT 3 OUTPUT 9 12 OUTPUT 2 OUTPUT 10 11 OUTPUT 1 DATA OUTPUT 7 10 DATA INPUT GND CLOCK 5-5012 Fig. 1 - Timing diagram VCLK VDO --n----:'IT I~~"' ~[- L---.lt PDEL [ I OUTPUT- - - - - - - ~ r -r--n ' , : PDEH L-----+--JijL THERMAL DATA Rth j-amb Thermal resistance junction-ambient ~2/~4~__________________________ ~ ~~~~~?:~:~?~, 298 max 80 °C/W _____________________________ L3654S ELECTRICAL CHARACTERISTICS (Vs = 5V, vE = 30V, T amb = 0° to 70 oe, unless otherwise specified) Test conditions Parameter Vs Supply voltage Is Supply current Min. Typ. 4.75 Tamb~ 25 c C ~ Vs 9.5V VEN~ ~ V 40 mA 2.6V 250 rnA (each bitl 55 70 mA 40 V 1 mA 65 V 1.6 V External operating supply voltage I'eak Output leakage current (each outputl VE Vz I nternal clamp voltage Iz ~ 0.3A * VEN~ OV VCE sat Output satu ration voltage 10 ~ 250 mA VEN~ 2.6V VDI V CLK V EN Input logic levels (pins 1,9,101 Low State (LI IDI Data input current 40V 9.5 27 VE ~ Unit OV; VDO~ OV VEN~ 10 Max. VEN~OV 45 50 0.8 V High state (HI VDI~ 2.6V 2.6 Tamb~ 70 c C 0.3 0.57 mA O°C 0.57 Tamb~ 70c C 220 Tamb~ VDI~ ICLK Clock input current 1V VCLK~ 2.6V Tamb~ 70°C /1- A 0.33 mA O°C 0.33 VCLK~1V Tamb~ 70 c C 125 VEN~ Tamb~ 70 D C Tamb~ lEN 0.2 0.75 Enable input current 2.6V 0.2 0.5 /1- A 0.33 mA O°C 0.33 VEN~1V Tamb~ 70 c C 125 Input pu II-down resistance Clock input Tamb~ 25 c C V CLK Enable input Tamb~ 25°C V EN Data input Tamb~ 25°C VDI Low state (LI OV IDO(pin 71~ Tamb~ R'N V DO Output logic levels (pin 71 VDI~ < Vs R DO Output pull-down resistance (pin 71 * Pulsed: pulse duration ~ VDI~ 300/1-5, duty cycle ~ OV Kn 8 < Vs VDO~1V /1-A 8 < Vs High state (HI VDI~ 2.6V IDO (pin 71 ~ -0.75 mA 0.5 4.5 a 0.01 2.6 0.5 V 3.4 V 14 Kn 2% 3/4 299 L3654S ELECTRICAL CHARACTERISTICS (see fig. 1 and the section "definition of terms") Test conditions Parameter Min. Typ. Max. Unit Clock. data and enable input tCLK 4 tCLK 5.5 tSET-UP 1 tHOLO 3 Il S Glock to enable delay tCLK EN 2 t81T tEN CLK t81T Enable to clock delay Data output delay tpOH. tpOL R L =5Kn. CL ';;10pF 0.8 2.5 IlS Output delay tpoEL 3 tpoEH 3.5 IlS Output rise time R L = 100 n. C L <100pF 1.2 Il S Output fall time RL=100n. CL <100pF 1.2 IlS VOO rise time 0.4 Il s VOO fall time 0.4 Il S DEFINITION OF TERMS V S5 : External power supply voltage. The return for open-collector relay driver outputs. VOl. VCLI'" V EN : The voltages at the data, clock and enable inputs respectively. VOO : The voltage at data output. t81T : Period of the incoming clock. tCLK : The portion of t81T when V CLK ;;;. 2.6V. tCLK : The portion of t81T when V CLK .;;; 0.8V. t HOLO : The time following the start of tCLK required to transfer data within the shift register. tSET-UP : The time prior to the end of tCLK required to insure valid data at the shift register input for subsequent clock transitions. ~4~/4~_________________________ ~~~~;~~~~:~~ _____________________________ 300 L4901A DUAL 5V REGULATOR WITH RESET PRELIMINARY DATA • OUTPUT CURRENTS: = 400mA 101 102 = 400mA • FIXED PRECISION OUTPUT VOLTAGE 5V ±2% • RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE • RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING • RESET OUTPUT LEVEL RELATED TO OUTPUT 2 • OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING • LOW LEAKAGE CURRENT, LESS THAN 1J1A AT OUTPUT 1 • LOW QUIESCENT CURRENT • INPUT OVERVOLTAGE PROTECTION UP TO 60V • RESET OUTPUT HIGH • OUTPUT TION TRANSISTORS SOA PROTEC- • SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION The L4901A is a monolithic low drop dual 5V regulator designed mainly tor supplying microprocessor systems. Reset and data save functions during switch onl off can be real ized. Heptawatt (INPUT 1) ORDERING NUMBER: L4901A ABSOLUTE MAXIMUM RATINGS DC input voltage Transient input overvoltage (t = 40 ms) Output current Storage and junction temperature 24 60 internally limited -40 to 150 V V BLOCK DIAGRAM Vi I o--J--i---I--L'::R~EG~':"'Ij--I~II--C Vol :r r:~=""1---l~n RESET L~~j--I'----'UTI MING 4 June 1988 1/9 301 w o r-J [" --'" en n r.j::o m 0 ::I: CD S l> l> -I 1 IN.1 IN.2 n 5-9349/1 0 l> G) 2 ::xJ THERMAL & OVERVOLTAGE PROTECTION l> S 7 --0 III ~ I I " ), OUTi OiSUt ©~ ""Ut © • ~g I! III "". ~iii!Ii II I ,,~., ~~.."~ J II \JII"'I rTA ~~ f.t-J J.J. I II Moo l' Y I rk: 6 0 ,1, 5 --0 GND 0 41 .L L49Dt::LIB OUT2 III 3 RESET OUTPUT o TIMING CAPACITOR ..... L4901A CONNECTION DIAGRAM (Top view) ~7 OUTPUT 1 2 6 OUTPUT 5 , RESET GROUND 3 TIMING CAPACITOR 2 INPUT 2 ~I INPUT 1 $~ 5-7768 PIN FUNCTIONS NAME FUNCTION INPUT 1 Low quiescent current 400mA regulator input. 2 INPUT 2 400mA regulator input. 3 TIMING CAPACITOR If Reg. 2 is switched-ON the delay capacitor is charged with a 10J.lA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. 4 GND Common ground. 5 RESET OUTPUT When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct (1 OJ.lA ); tRD (ms) = Ct (nF) 6 OUTPUT 2 5V - 400mA regulator output. Enabled if Vo 1 > V RT and V IN 2 VIT' If Reg. 2 is switched-OFF the CO2 capacitor is discharged. 7 OUTPUT 1 5V - 400mA regulator output with low leakage (in switch-OFF condition). > THERMAL DATA Rth J-case Thermal resistance junction-case ---------------------------~~~I~~g~~~ max 4 ________________________-23/~9 303 L4901A TEST CIRCUIT ELECTRICAL CHARACTERISTICS (V INl = V IN2 = 14,4V, Tamb = 25°C unless otherwise specified) Parameter Vi Min. Test Conditions Typ. DC operating input voltage Max. Unit 20 V VOl Output voltage 1 R load 1 KO 4.95 5.05 5.15 V V 02H Output voltage 2 HIGH R load 1 KO V OI -O.l 5 VOl V V 02L Output voltage 2 LOW 102 = -5mA 101 Output current 1 b. VOl = -100mV ILOl Leakage output 1 current VIN = 0 VOl" 3V 102 Output current 2 b.V 02 = -100mV VIOl Output 1 dropout voltage (0) 101 = 10mA 101 = 100mA 101 = 300mA VIT Input threshold voltage V ITH Input threshold voltage hyst. b. VOl Line regulation 1 b.V 02 Line regulation 2 b.V 01 Load regulation 1 0.1 V mA 400 1 400 V 0 1+l.2 !LA mA 0.7 0.8 1.1 0.8 1 1.4 6.4 VOl + 1.7 250 V V V V mV 7V < VIN < 18V 101 = 5mA 5 50 mV 102 = 5mA 5 50 mV 5mA < 101 < 400mA 50 100 mV b.V 02 Load regulation 2 50 100 mV IQ Quiescent current 0< VIN < 13V 7V < VIN < 13V 102 = 101 .. 5mA 4.5 1.6 6.5 3.5 mA mA IQl Qu iescent cu rrent 1 6.3V < VIN 1 < 13V VIN~ = 0 102 = 0 101 5mA 0.6 0.9 mA 5mA < 102 < 400mA _4~/9_________________________ ~!~~~~~~:~~~ 304 ___________________________ L4901A ELECTRICAL CHARACTERISTICS (continued) Test Conditions Parameter V RT Reset threshold voltage V RTH Reset threshold hysteresis Min. Typ. Max. Unit V02 -O.15 4.9 V02 -OD5 V 30 50 80 mV V 4.12 V02 0.25 0.4 V 5 11 ms 20 ItS V RH Reset output voltage HIGH VRL Reset output voltage LOW 'R = 500ltA 'R = -5mA tRD Reset pulse delay Ct = 10nF td Timing capacitor discharge time Ct = 10nF II VOl LIT Thermal drift -20°C';; Tamb .;; 125°C 0.3 -0.8 mVrC lIV 02 LIT Thermal drift -20°C';; Tamb .;; 125°C 0.3 -0.8 mV/oC SVRl Supply voltage rejection f = 100Hz 84 dB SVR2 Supply voltage rejection TJSD Thermal shut down V02 -1 3 V R = 0.5V = 100mA '0 - 50 50 80 dB 150 °c * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25mV under. constant output current condition. APPLICATION INFORMATION In power suppl ies for J.1P systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed. The L4901A makes it very easy to supply such equipments; it provides two voltage regulators (both 5V high precisiont with separate inputs plus a reset output for the data save function. CIRCUIT OPERATION (see Fig. 1) After switch on Reg. 1 saturates until VOl rises to the nominal value. When the input 2 reaches V,T and the output 1 is higher than V RT the output 2 (V 02 ) switches on and the reset output (V R) also goes high after a programmable time T RD (timing capacitor). V02 and V R are switched together at low level when one of the following conditions occurs: - an input overvoltage - an overload on the output 1 (VOl V ,T - V ,TH ); a switch off (V ,N < < V RT ); and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The VOl output features: 5V internal reference without voltage divider between the output and the error comparator; very low drop series regu lator element utilizing current mirrors; permit high output impedance and then very low leakage current error even in power down condition. This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The VOl ---------------------------~~~~~~~rr~l~~~ ________________________~5/~9 305 L4901A CIRCUIT OPERATION (continued) regulator also features low consumption (0.6mA typ.) to minimize battery drain in applications where the VI regulator is permanently connected to a battery supply. The V02 output can supply other non essential 5V circuits wich may be powered down when the system is inactive, or that must bs powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be used as a "POWER DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV SHADOW. MEMORY when the supply is interrupted. Fig. 1 SWITCH ON VOl OVERLOAD V02 OVERLOAD VIN OVERLOAD THERMAL SHUT SWITCH DOWN OFF APPLICATION SUGGESTIONS Fig. 2 shows an application circuit for a p,P system typically used in trip computers or in car radios with programmable tuning. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OF F when the system is inactive. Fig. 4 shows the L4901A with a back up battery on the VOl output to maintain a CMOS time-ofday clock and a stand by type N-MOS p,P. The reset output makes sure that the RAM is forced into the low consumption stand by state, so the. access to memory is inhibit and the back up battery voltage cannot drop so low that memory contents are corrupted. In this case the main on-off switch disconnects both regulators from the supply battery. The L4901 A is also ideal for microcomputer systems using battery backup CMOS static RAMs. As shown in fig. 5 the reset output is used both to disable the p,P and, through the address decoder M74HC 138, to ensure that the RAMS are disabled as soon as the main supply starts to fall. Another interesting application of the L4901A is in p,P system with shadow memories. (see fig. 6) When the input voltage goes below V rr , the reset output enables the execution of a routine that saves the machine's state in the shadow RAM (xicor x 2201 for example). Thanks to the low consumption of the Reg. 1 a 680p,F capacitor on its input is sufficient to provide enough energy to complete the operation. The diode on the input guarantees the supply of the equipment even if a short circuit on V I occurs. _6/~9_________________________ ~~~I~~~~:~~~ 306 --------------------------- L4901A APPLICATION SUGGESTION (continued) Fig.2 IN1 REG.1 BATTERY ~ CMOS pP WITH RESET REG. 2 VOLATILE RAM OTHER LOGIC C3 10nF @5V I LL.901 A 5 RESET OUT RESET 4 Fig. 3 - P.C. board component layout of fig. 2 (1 : 1 scale) GND IN1 OUT2 ____________ ill SGS-THOMSON .J'~ GND _ _ _ _ _ _ _ _ _ _ _--'-7/9 il)]D©IRl@~~~©'lfIRl@iRlD©ill 307 L4901A APPLICATION SUGGESTION (continued) Fig.4 IN1 ~Y REG. 1 O.22.uF .I I BACKUP BATTERY IN 2 4.?.u F 6 REG. 2 I OUT2 .0 P(3875-2875) VOO WITH BATTERY BACKUP RAM 11010/JF I RESET VOO CT L4901A 5 lonFI RESE TOUT RESET 4 5_777112 Fig.5 --,- -c.' Vi INI 1~~ OUTI 2.2.S fF~ au" J-!- r----1 21N2 I 'DO J: "00 $i'.7 F ~ J: L4901A CMOS STATIC R"MS LIKE TC5516 OR TCS5Ej5 RESET~~ .J:.--'- 10 n F' O:~R ~ 5V CHIPS :t: CT L._~G~NO::..----, --:IT .1. l -. ____~r____~_______ r4--------+------b-~----------_+~ RESET 'Is I We MREQ Z8400 U I VDD L--. Gl Vi G'A L: m ;-;1M74HC138 AI5 c AI4 B T41- A13 A "I- YflTO OTHER MEMORY CHIPS Y"61- nI- T ;:!8/..:9 _ _ _-,-_ _ _ _ _ _ _ _ _ 308 T S-to53/1 ~ ~~~~m?:1?~ .1. I 2.8tolV ~:r.LlTHIUM BATTER V L4901A APPLICATION SUGGESTION (continued) Fig.6 Vi IN1 :c 7 OUT 1 680 pF L4901A Vs OUT 2 IN 2 ADDRESS DATA IIOf'F 8085 RESET 5 CT 10 n f I TRAP GND 5_80':1512 Fig. 7 - Quiescent current (Reg. 1) vs. output current Fig. 9 - Total quiescent current vs. input voltage Fig. 8 - Quiescent current (Reg. 1) vs. input voltage 5_5795 rJ '0' I '0' (mA) (rnA) , I 15 101 (rnA) 1 700 ImA )1 --I .- -f--+! r- ls~i I 500 v V 800 1,\ V 1 ~ 700 100 \\ 15 IK 18 , " ""'- Vi (V J 18 Vi (v) Fig. 12 - Supply voltage rejection regulators 1 and 2 vs. input ripple frequence 5YR (dB } SVRl --SYR 0 \ I. ' \ . \ \ 300 ,\ 12 -- \ / 400 \\ - / 500 '\ ,\ 15 80 600 ' 300 200 .- 1 I Vi1 (V) Fig. 11 - Regu lator 2 output current and short circuit current vs. input voltage Fig. 10 - Regulator 1 output current and short circuit current vs. input voltage ImA 1 18 I-- ~ " \ 10 0 \\ 3 6 9 12 15 18 21 24 Vi (v) 10 ----------------------------- ~~~~~~~v~~~~:l ___________________________9~/9 309 L4902A DUAL 5V REGULATOR WITH RESET AND DISABLE PRELIMINARY DATA • DOUBLE BATTERY OPERATING • OUTPUT CURRENTS: • FIXED PRECISION OUTPUT VOLTAGE 5V ±2% • RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE • RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING • RESET OUTPUT LEVEL RELATED TO OUTPUT 2 • OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING 101 102 = 300mA = 300mA • OUTPUT 2 DISABLE LOGICAL INPUT • LOW LEAKAGE CURRENT, LESS THAN 1JlA AT OUTPUT 1 • RESET OUTPUT NORMALLY HIGH • INPUT OVERVOLTAGE PROTECTION UP TO 60V • OUTPUT TRANSISTORS SOA PROTECTION • SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION The L4902A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions and remote switch on / off control can be realized. Heptawatt ORDERING NUMBER: L4902A ABSOLUTE MAXIMUM RATINGS DC input voltage Transient input overvoltage (t = 40 ms) Output current Storage and junction temperature 28 V 60 internally limited -40 to 150 V °C BLOCK DIAGRAM 015. 0----4-+1 L.::~_t--r--U TIMING S-784013 June 1988 1/9 311 W r:::; en ('") Ico ~ :::I: m S » -I ('") 0 IN » G') :D » S 0 THERMAL & I OVERVOLTAGE PROTECTION ~ I III - r-, 0 li I 7 ~ ~ OUT1 ~UI !'In '9U1 ©. ~~ !'l:o ~i: ..L..L ©UI ~o iillz r D":D : : I 11 D L4S02::LIS ... j j I ~- iT ~I fll 5-9359/1 6 0 5 ~ 2 OUT2 RESET OUTPUT o TIMING CAPACITOR ... r to 0 I\,') l> L4902A CONNECTION DIAGRAM (Top view) - ~ OUTPUT 1 OUTPUT 2 RESET GROUND DISABLE INPUT TIMING CAPACITOR $~ ~ INPUT 5 -7841 PIN FUNCTIONS NAME FUNCTION INPUT 1 Regulators common input. 2 TIMING CAPACITOR If Reg. 2 is switched-ON the delay capacitor is charged with a 51lA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. 3 V02 DISABLE INPUT A high level (> V OT ) disable output Reg. 2. 4 GND Common ground. 5 RESET OUTPUT When pin 2 reaches 5V the reset output is switched high. 5V Therefore t Ro = Ct (10IlA); tRO (ms) = Ct (nF). 6 OUTPUT 2 5V - 300mA regulator output. Enabled if Vo 1 > V RT' DISABLE INPUT < V OT and V IN > VIT' If Reg. 2 is switched-OFF the CO2 capacitor is discharged. 7 OUTPUT 1 5V - 300mA. Low leakage (in switch-OFF condition) output. THERMAL DATA Rth j-case Thermal resistance junction-case max 4 ___________________________ ~~~~~~~~~:~~: ________________________~3/_9 313 L4902A TEST CIRCUIT Vol Vi 6 Vo2 5 DIS. 2.2},F 2 Ir 4.7 t'F r 10nF s -9360 I 12 2. 2},F ELECTRICAL CHARACTERISTICS (V 1N = 14.4V, T amb = 25°C unless otherwise Parameter Min. Test Conditions Typ. specified) Max. Unit 24 V VI DC operating input voltage VOl Output voltage 1 R load 1K.fl 4.95 5.05 5.15 V V 02 H Output voltage 2 H IG H R load 1K.fl Vo l -0.1 5 VOl V V02L Output voltage 2 LOW 102 = -5mA 101 Output current 1 max. IlVOl =-100mV. ILOl Leakage output 1 current V 0.1 300 mA 1 VIN = 0 p.A VOl" 3V 102 Output current 2 max. IlV02=-100mV VIOl Output 1 dropout voltage (*j 101 = 10mA 101 = 100mA 101 = 300m A VIT Input threshold voltage VITH Input threshold voltage hysteresis Il VOl Line regulation 1 IlV 02 Line reg\ilation 2 Il VOl Load regu lation 1 Il V02 Load regulation 2 IQ Quiescent current VRT Reset threshold voltage VRTH Reset threshold hysteresis VOl +1.2 0.7 0.8 1.1 0.8 1 1.4 6.4 V0 1 +1.7 250 V V V V mV 101 = 5mA 5 50 mV 102 = 5mA 5 50 mV 5mA < 101 < 300mA 40 80 mV 5mA < 102 < 300mA 50 80 mV 4.5 2.7 1.6 6.5 4.5 3.5 mA mA mA V 02cO.15 4.9 V 02 -OD5 V 30 50 80 mV 7V < V1N < 24V 0< V1N < 13V 7V < VIN < 13V V 02 LOW 7V < VIN < 13V V02 HIGH 101 = 102 .. 5mA ~4/~9_________________________ ~~~~~~~~~ 314 rnA 300 ___________________________ L4902A ELECTRICAL CHARACTERISTICS (continued) Parameter Test Conditions VRH Reset output voltage HIGH IR = 500,uA VRL Reset output voltage LOW IR = -lmA tRO Reset pulse delay Ct = 10nF td Timing capacitor discharge Ct = 10nF VOT V02 disable threshold voltage 10 V0 2 disable input current t. VOl t.T Thermal drift -20°C < Tamb < Thermal drift -20°C < t. V02 Min. Vorl 3 Typ. Max. Unit 4.12 V02 V 0.25 0.4 V 5 11 ms 20 ,us time t.T SVRl Supply voltage rejection SVR2 Supply voltage rejection TJSO Thermal shut down 1.25 Vo < OAV Vo)o 2AV Tamb < 2.4 V -150 -30 ,uA ,uA 125°C 0.3 -0.8 mV/oC 125°C 0.3 -0.8 f = 100Hz VR =0.5V 10= 100mA mV/oC 50 84 50 80 dB 150 °c dB • The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25mV under constant output current condition. APPLICATION INFORMATION In power supplies for JlP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed. The L4902A makes it very easy to supply such equipments; it provides two voltage regulators (both 5V high precision) with common inputs plus a reset output for the data save function and a Reg. 2 disable input. an input overvoltage; an overload on the output 1 (VOl a switch off (V 1N V 1T - V 1TH ); < < V RT ); and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The VOl output features: CIRCUIT OPERATION (see Fig. 1) After switch on Reg. 1 saturates until VOl rises to the nominal value. 5V internal reference without voltage divider between the output and the error comparator very low drop series regulator element utilizi ng cu rrent mirrors When the input reaches V1T and the output 1 is higher than V RT the output 2 (V 02 ) switches on and the reset output (V R) also goes high after a programmable time T RO (timing capacitor). permit high output impedance and then very low leakage current even in power down condition. V02 and V R are switched together at low level when one of the following conditions occurs: - a high level (> VOT ) is applied on pin 3; This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of 'a back-up battery. -------------- ~ ~~~~m?::~~©~ ____________ 9 --'5/_ 315 L4902A CIRCUIT OPERATION (continued) The V02 output can supply other non essential 5V circuits wich may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be used as a "POWE R DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV SHADOW MEMORY when the supply is in· terrupted. The disable function can be used for remote on/off control of circuits connected to the V02 output. Fig. 1 Vffi~----~r---~-+~-----4------+-------+-------f-L---+-~------~~ SWITCH ON V02 VIN OVERLOAD I OVERLOAD THERMAL SHUT DOWN V02 SWITCH DISABLE OFF 5-7842/2 APPLICATION SUGGESTION Fig. 2 illustrate how the L4902A's disable input may be used in a CMOS J..!Computer application. The VOl regulator (low consumption) supply permanently a CMOS time of day clock and a CMOS J..!computer chip with volatile memory. V02 output, supplying non-essential circuits, is turned OFF under control of a J..!P unit. Configurations of this type are used in products where the OF F switch is part of a keyboard scanned by a micro which operates continuously even in the OF F state. Another application for the L4902A is supplying a shadow-ram microcomputer chip (SGS M38SH72 for exemple) where a fast NV memory is backed up on chip by a EEPROM when a low level on the reset output occurs. By adding two CMOS-SCHMIDT-TRIGGER and few external components, also a watch dog function may be realized (see fig. 5). During normal operation the microsystem supplies a periodical pulse waveform; if an anomalous condition occours (in the program or in the system), the pulses will be absent and the disable input will be activated after a settling time determined by R 1 Cl. In this condition all the circuitry connected to V 02 · will be disabled, the system wi II be restarted with a new reset front. The disable of V02 prevent spurious operation during microprocessor malfunctioning. _6/~9_________________________ ~~~~~~~~~:~~~ ___________________________ 316 L4902A APPLICATION SUGGESTION (continued) Fig.2 -1 .I INI 1 C~ TTERY 7 REG.l I~3 I /-lF 47,41fI Voo OUT 1 r 3 V02 OIS +1 OUT 2 6 REG. 2 ~ J CMOS CLOCK VOO OUT PORT IN PORT CMOS /-lP WITH VOLATILE RAM ItOl0/-lf! IC4 VOO OTHER LOGIC _I I ~5V C:l2 10nF L L.902A 5 RESET OUT RESET I 5-7843/1 Fig. 3 - P.C. board and component layout of the circuit of Fig. 2 (1 : 1 scale) GND DIS. OUT2 GND ____________ ru SCS-THOMSON _ _ _ _ -----_--'-7/9 •J." i'j]D!:OO©~~~!:lI00©i'!lD!:® 317 L4902A APPLICATION SUGGESTION (continued) Fig.4 Vi Vol VDD 7 6 DISABLE 3 L4902A Vo2 :::c TO OTHER 5V CHIPS 10,u F 1>}J 5 F M38SH72 RESET 2 lOnF I 100nF I s- 93621 2 Fig.5 OUT1~7~------------------------------~------~VDD OUT2~6~----------~~----~~ L4902A . DIS. OfF RST~------~-----+----_+------------------~~RSTfP TIM. - - - - - - - - -- - - -I 33 nF OUTPUT PORT i I ~--~~~~~---~ : JUill 5 -9363/2 _8~/9____________________~~_ ~~~~~~?v~:~~ 318 --------------------------- L4902A APPLICATION SUGGESTION (continued) Fig. 6- Quiescent current vs. output current Fig. 7 - Qu iescent current vs. input voltage G 566611 G-5B6'>ll la (rnA) -~-~-k+ "" 10 e- I-- C-- 'mA - -- ) '-- - - I - - I- 1 e--,- I-I.--"" J.-- - - -- ~ f--::: I-- J.-- f-- - IdB 1 SVRI 0 t::5 -I (") IN 1 0 1 I C 5 - 9422 l> G) I :c l> THERMAL & OVERVOLTAGE PROTECTION ~ IN 2 _ 2 1,1 s: II r '11 i 8 1 1 I II I 7 il~ nI 6 0 OUH 0 OUT2 ::1:UI ll'll:'l ""UI @. Wil:i! I"lo §l].: @UI ~o III ..... __..__ J II ~z O:NSO' : : I I' .LJ. D ..I. ~ 3 --<> RESET OUTPUT TIMING CAPACITOR Ii L4903 CONNECTION DIAGRAM (Top view) OUTPUT 1 INPUT 1 INPUT 2 TIMING CAPACITOR RESET OUTPUT 3 GND 5 V02 DISABLE INPUT 5-9417 PIN FUNCTIONS NAME FUNCTION INPUT 1 Low quiescent current 50mA regulator input. 2 INPUT 2 1OOmA regulator input. 3 TIMING CAPACITOR If Reg. 2 is switched-ON the delay capacitor is charged with a 1OIlA constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged. 4 GND Common ground. 5 V 02 DISABLE INPUT A high level (> V DT ) disables output Reg. 2. 6 RESET OUTPUT When pin 3 reaches 5V the reset output is switched low. 5V Therefore tRD = Ct (10IlA); tRD (ms) = Ct (nF). 7 OUTPUT 2 5V - 100mA regulator output. Enabled if Va 1 > V RT . DISABLE INPUT < V DT and V IN 2 > VIT' If Reg. 2 is switched OFF the CO2 capacitor is discharged. 8 OUTPUT 1 5V - 50mA regulator output with low leakage in switchOFF condition. THERMAL DATA Rth j-pin Rth j-amb Thermal resistance junction-pin 4 Thermal resistance junction-ambient max max 70 100 °C/W °C/W ___________________________ ~~~~~~~~~:~~~ ________________________~3/~7 323 L4903 TEST CIRCUIT P.C. board and components layout of the test circuit (1 : 1 scale) 5- 'IoHI GNO 015, RS Vo2 Vol ELECTRICAL CHARACTERISTICS (V IN = 14,4V, T amb = 25°C unless otherwise specified) Parameter Vi Test Conditions Min. Typ. DC operating input voltage Max. Unit 20 V VOl Output voltage 1 R load lKn 4.95 5,05 5.15 V V 02H Output voltage 2 HIGH R load lKn VOl -0,1 5 VOl V V 02L Output voltage 2 LOW /01 Output current 1 max, I LOI Leakage output 1 current 0,1 102 = -5mA (*1 11 VOl = -100mV Output current 2 max, Output 1 dropout voltage VIT Input threshold voltage VITH Input threshold voltage hysteresis 1 11 V 02 = -100mV (*1 VOl +1,2 0.7 0.75 0,8 0,9 6.4 VOl +1,7 Li ne regu lation 1 Line regulation 2 11 VOl Load regulation 1 lIV 02 Load regu lation 2 IQ Quiescent current 0 V OT ) is applied on pin 5' an input overvoltage; an overload on the output 1 (VOl < V RT ); a switch off (V IN VIT - V ITH ); < and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The VOl output featu res: 5V internal reference without voltage divider between the output and the error comparator very low drop series regulator element util· izing current mirrors permit high output impedance and then very low leakage current even in power down conditions. This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. ~ ~~~~m~1J~:~~~~ _____________ 5/'-7 325 L4903 CIRCUIT OPERATION (continued) only in correct power conditions, or as a "BACKUP ENAB LE" to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. The disable function can be used for remote on/off control of circuits connected to the V02 output. The V02 output can supply other non essential 5V circuits wich may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be used as a "POWE R DOWN INTERRUPT", permitting RAM access Fig. 1 vIN.V01,VO vIN1;VIN2 V iT vtTH VOl VRT VOT V02 .vR SWITCH ON VOl OVERLOAD V02 OVERLOAD VIN OVERLOAD ~~~~MAL DOWN V02 DISABLE SWITCH OFF 5-941911 APPLICATION SUGGESTION Fig. 2 illustrates how the L4903's disable input may be used in a CMOS tIComputer application. turned OFF under control of a tiP unit. Configurations of this type are used in products where the OFF switch is part of a keyboard scanned by a micro which operates continuously even in the OFF state. The VOl regulator (low consumption) supply permanently a CMOS time of day clock and a CMOS tIcomputer chip with volatile memory. V02 output, supplying non-essential circuits, is Fig.2 REG. 2 OTHER LOGIC C3 5V C, 10nF I lL.903 6 RESET OUT RESET ~6/_7_________________________ ~~~~~~~~~~~~~ ___________________________ 326 L4903 APPLICATION SUGGESTIONS (continued) Fig. 3 - Quiescent current (Reg. 1) vs. output current Fig. 4 - Quiescent current (Reg. 1) vs. input voltage (,_579611 '0' 1-+-1-+-\-++-+--+-+-+-1-+-1-+-+-1 (m A) - ~ ----- J-J- Ll__ "12 =0 lo1t::5mA o 5 >--1--I-+-\-++-+--+-+-+->--1--I-W-< V / V V 1/ 25 50 [OlemA) 18 ViI (V) Fig. 6 - Supply voltage rejection regulators 1 and 2 vs. input ripple frequence Fig. 5 -- Total quiescent current vs. input voltage G 5B~611 SVR (CiB ) '0 (m' ) IOl~[02S5m'" ---"02 l0W -vo2iGH y I II - -1 ~ SVR " yv12 .SVRl 80 0 r-.. '\: 0 V 0 ----------------------------- ~~~~~~~~~~Jl ___________________________ 7c-/7 327 L4904A DUAL 5V REGULATOR WITH RESET PRELIMINARY DATA • OUTPUT CURRENTS: 101 102 • RESET OUTPUT NORMALLY HIGH = 50mA = 100mA • FIXED PRECISION OUTPUT VOLTAGE 5V ± 2% • RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE • RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING • RESET OUTPUT LEVEL RELATED TO OUTPUT 2 • OUTPUT TRANSISTORS SOA PROTECTION • SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION The L4904A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions during switch on/ off can be realized. • OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING • LOW LEAKAGE CURRENT, LESS THAN 1JLA AT OUTPUT 1 • LOW QUIESCENT CURRENT (INPUT 1) • INPUT OVERVOLTAGE PROTECTION UP TO 60V Minidip Plastic ORDERING NUMBER: L4904A ABSOLUTE MAXIMUM RATINGS V IN 10 Ptot Tj 24 60 internally limited 1 -40 to 150 DC input voltage Transient input overvoltage It = 40 ms) Output current Power dissipation at Tamb = 50°C Storage and junction temperature V V W °C BLOCK DIAGRAM Vi 1 0--.....--'-1-----... r:~=:_1-_L6~() RESET L::':~.J----t=---o TI MIN G 4 June 1988 5-9<11/1 1/8 329 w 0w en I~ '" n J: m s l> -I n 0 I bL I THERMAL 6: OVERVOLTAGE PROTECTION I I i II l> G') ::c I IiO tt I l> s 8 --0 ~ OUH ;!lUI lit;; © • ~i! ~O ~S ©UI ~O J.J. ... ~z I II j ~ .I. 5- 9410/1 ~ I ~. OUT2 RESET OUTPUT III 3 TIMING OR CAPACIT 0 r .j:>, (.0 0 .j:>, » L4904A CONNECTION DIAGRAM (Top view) 7 OUTPUT 2 RESET OUTPUT 5 N.C. PIN FUNCTIONS FUNCTION NAME INPUT 1 Low quiescent current 50mA regulator input. 2 INPUT 2 100mA regulator input. 3 TIMING CAPACITOR If Reg. 2 is switched-ON the delay capacitor is charged with a 10p,A constant current. When Reg. 2 is switchedOFF the delay capacitor is discharged. 4 GND Common ground. 6 RESET OUTPUT When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct (10P,A ); tRD (ms) = Ct (nF). 7 OUTPUT 2 5V - 100mA regulator output. Enabled if Vo 1 V RT and VIN 2 VIT' If Reg. 2 is switched-OFF the CO2 capacitor is discharged. 8 OUTPUT 1 5V - 50mA regulator output with low leakage in switchOFF condition. > > THERMAL DATA Rthj-amb Thermal resistance junction-ambient max 100 ___________________________ ~~~~~~~~~ __________________________ 3/_8 331 L4904A TEST CIRCUIT P.C. board and components layout of the test circuit (1 : 1 scale) 8 7 L4904A 6 RESET 3 S-9.(.1J/l = 14,4V, T amb = 25°C unless otherwise specified) ELECTRICAL CHARACTERISTICS (V 1N Parameter Vi Test Conditions Min. Typ. DC operating input voltage 20 VOl Output voltage 1 R load 1Kn 4.95 5.05 V02H Output voltage 2 HIGH R load 1Kn VOl -0.1 5 V02 L Output voltage 2 LOW 102 101 Output cu rrent 1 l::. VOl I LOl Leakage output 1 current VIN = 0 VOl" 3V 102 Output cu rrent 2 l::.V02 VIOl Output 1 dropout voltage (*) V 1T Input threshold voltage VITH Input threshold voltage hyst. l::.V Ol Line regulation l::.V 0 2 Line regulation 2 l::.V Ol Load regulation 1 l::.V02 Load regulation 2 IQ Quiescent current o< IGil Quiescent current 1 6.3V < VINl VIN2 = 0 101 .. 5mA = -5mA = = 101 101 = = V VOl. V mA 1 -100mV VOl +1.2 0.7 0.75 O.S 0.9 6.4 VOl +1.7 < VIN < lSV 101 102 VIN = SV 5mA 5mA = 5mA = 5mA < 101 < 5'OmA < 102 < 100mA VIN < 13V 7V < VIN < 13V 102 = 101 .. 5mA < 13V 102 = V V V mV 250 7V p.A mA 100 10mA 50mA V V 50 -100mV Unit 5.15 0.1 ~4/~8_________________________ ~~~~~~~~'~©~ 332 Max. 5 50 5 50 mV 5 20 10 50 4.5 1.6 6.5 3.5 mA mA 0.6 0.9 mA mV ___________________________ 0 L4904A ELECTRICAL CHARACTERISTICS (continued) Parameter Test Conditions V RT Reset threshold voltage VRTH Reset threshold hysteresis VRH Reset output voltage HIGH IR = 500MA V RL Reset output voltage LOW IR = -5mA Min. Typ. Max. Vo2 -O.15 4.9 V02 -O.05 V 30 50 80 mV 4.12 V02 V 0.25 0.4 V 11 ms 20 MS V02 -1 Unit tRD Reset pulse delay Ct - 10nF td Timing capacitor discharge time Ct = 10nF 6V OI 6T Thermal drift -20°C" Tamb " 125°C 0.3 -0.8 mVtC Thermal drift -20°C" Tamb " 125°C 0.3 -0.8 mVtC 6 V02 6T SVR1 3 Supply voltage rejection = 100Hz VR = 0.5V 10 = 50mA 50 84 dB 10 = 100mA 50 80 dB 150 °c f SVR2 Supply voltage rejection TJSD Thermal shut down * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25m V under constant output current condition. APPLICATION INFORMATION In power supplies for JJ.P systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed. The L4904A makes it very easy to supply such equipments; it provides two voltage regulators (booth 5V high precision) with separate inputs plus a reset output for thp. data save function. - an overload on the output 1 (VOl a switch off (V IN V IT - V ITH ); < < V RT ); and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The VOl output features: 5V internal reference without voltage divider between the output and the error comparator; CIRCUIT OPERATION (see Fig. 1) After switch on Reg. 1 saturates until VOl rises to the nominal value. very low drop series regulator element utilizing current mirrors; When the input 2 reaches V IT and the output 1 is higher than V RT the output 2 (V 02 ) switches 0[1 and the reset output (V R ) also goes high after a programmable time T RD (timing capacitor). permit high output impedance and then very low leakage current even in power down conditions. V02 and V R are switched together at low level when one of the following conditions occurs: - an input overvoltage ------------------------------ This output may therefore be used to supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The VOl regulator also features low consumption (O.6mA ~~~~~~~v~:~~~ ____________________________ 5~/8 333 L4904A CIRCUIT OPERATION (continued) typ.) to minimize battery drain in applications where the VI regulator is permanently connected to a battery supply. voltages below the minimum value. The reset output can be used as a "POWE R DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. The V02 output can supply other non essential 5V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply Fig. 1 SWITCH ON VOl OVERLOAD V02 THERMAL VIN OVERLOAD OVERLOAD SHUT SWITCH DOWN OFF APPLICATION SUGGESTIONS Fig. 2 shows an application circuit for a J..!P system. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-dav clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OFF when the system is inactive. Fig. 3 shows the L4904A with a back up battery __________________________ ~6/~8 334 on the VOl output to maintain a CMOS time-ofday clock and a stand by type C-MOS J..!P. The reset output makes sure that the RAM is forced into the low consumption stand by state, so the access to memory is inhibit and the back up battery voltage cannot drop so low that memory contents are corrupted. In this case the main on-off switch disconnects both regulators from the supply battery. ~~~~~~?V~:~~~ ___________________________ L4904A APPLICATION SUGGESTIONS (continued) Application Circuits of a Microprocessor system (Fig. 2) or with data save battery (Fig. 3). The reset output provide delayed rising front at the turn-off of the regulator 2. Fig. 2 [",± INI F IN2 1 REG.l 8 I 2 ~- rl REG. 2 C~ I l 1,uF 7 OUT 2 ~021 tol0,uF I l,uFI 10nF VOO OUT 1 ~COI I J CMOS CLOCK VOO CMOS ,uP WITH VOLATILE RAM RESET Voo OTHER LOGIC ~5V L4904A 6 1: RESET OUT RESET 5 - 941411 Fig. 3 ~:-r~IN~'~~~8~~ I I REG. 1 BATTERY L....._ _ _....... O.22,uF BACKUP BATTERY VOO OUT 2 IN 2 REG. 2 BACKUP 1 tol0IJF I ,uP WITH BATTERY RESET RAM VOO CT 10nF I L4904A 6 RESE TOUT RESET 4 5 - 9415/1 ____________ 51 SGS-THOMSON "'N _ _ _ _ _ _ _ _ _ _ _7:-/8 Wil~©IRI@~~~©1i'IRI@o:lfl©® 335 L4904A APPLICATION SUGGESTIONS (continued) Fig. 5 - Quiescent current (Reg. 1) vs. input voltage Fig. 4 - Quiescent current (Reg. 1) vs. output current 101 ( mAl f-+++-+++-++-H-t--+-1-+-H ~ 101 (rnA) ',112 ",0 lo1~5mA I , 0.5 f-+,++~+H+-H-+--+-f-++1 V / V 7 ./ 50101CmAl 25 12 15 18 Vii (V) Fig. 7 - Supply voltage rejection regulators 1 and 2 vs. input ripple frequence Fig. 6 - Total quiescent current vs. input voltage SYR lato1 'rnA I (dB I 101':: 102 ~ SmA. \1,1',,'1;2 , -- 1/ - I I V V- SVRI '0 SVR 70 ~ ~ ~ 60 50 15 18 -'8/_8_ _ _ _ _ _ _ _ _ _ _ _ _ 336 Vi (V) 10 ~ ~~~~m?,r~:J?lt -------------- L4905 DUAL 5V REGULATOR WITH RESET ADVANCE DATA • • DOUBLE BATTERY OPERATING OUTPUT CURRENTS: 101 =200mA 102 =300mA • RESET OUTPUT HIGH • OUTPUT TRANSISTORS SON PROTECTION • SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION • FIXED PRECISION OUTPUT VOLTAGE 5V ± 1% • RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE • RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING The L4905 is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. • RESET OUTPUT OUTPUT 2 Reset and data save functions during switch on! off can be real ized . • OUTPUT2INTERNALLYSWITCHEDWITH ACTIVE DISCHARGING • LOW LEAKAGE CURRENT, LESS THAN 1J1A AT QUTPUT 1 • • LOW QUIESCIENT CURRENT (INPUT 1) INPUT OVERVOLTAGE PROTECTION UP T060V LEVEL RELATED TO Heptawatt ORDERING NUMBER: L4905 ABSOLUTE MAXIMUM R.ATINGS DC input voltage Transient input overvoltage (t = 40 ms) Output current Storage and junction temperature 28 v 60 internally limited -40 to 150 V BLOCK DIAGRAM Vi I O--T-T---T----L!R~EG~.2.1 . j-r-t'---r--{; Vol r:::-:::-l--!i--o RESET L':':'::":'_r--,--() TIM IN G 4 June 1988 1/8 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change withe ,t notice. 337 L4905 SCHEMATIC DIAGRAM a: l- I:::J 0 0 :::J (,DO 1-1- ru ~ zl- ........ U w:::J 000.. :::E .... " wIa::::J 1-0.. 0 " U 10 " ICI (I') w !!~ ~~ W..J u..O w> a: C\I o z zz ........ / 8_ _ _ _ _ _ _ _ _ _ _ _ _ _2_ 338 (,D @. ~~~~m?1I't:~~~ -------------- L4905 CONNECTION DIAGRAM (Top view) ~- ~7 OUTPUT 1 OUTPUT 2 £> $~ RESET GROUND TIMING CAPACITOR INPUT 2 INPUT 1 5 , 3 2 ~ S_77£>8 PIN FUNCTIONS NAME FUNCTION INPUT 1 Low quiescent current 200mA regulator input. 2 INPUT 2 300mA regulator input. 3 TIMING CAPACITOR If Reg. 2 is switched-ON the delay capacitor is charged with a 10llA constant current. When Reg. 2 is switched-OFF the delay capacitor is discharged. 4 GND Common ground. 5 RESET OUTPUT When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct ( 1011 A ); tRD (ms) = Ct (nF) 6 OUTPUT 2 5V - 300mA regulator output. Enabled if Vo 1 > V RT and V 1N2 VIT' If Reg. 2 is switched-OFF the CO2 capacitor is discharged. 7 OUTPUT 1 5V - 200mA regulator output with low leakage (in switch-OFF condition). > THERMAL DATA RthJ-case Thermal resistance junction-case max ____________ 5i SGS-THOMSON •J'~ 4 _ _ _ _ _ _ _ _ _ _-'3/__8 1iii~[:IRI@~~~[:'!iIRl@i:l~©,. 339 L4905 TEST CIRCUIT Vol 7 Vi1 6 Vi2 o.ljJF 5 RESET 2 4.7 fF 1 1 r Vo2 3 10nF 2.2,PF 5-9348/1 rIr ELECTRICAL CHARACTERISTICS (V 1Nl 14,4V, Tamb 2 2jJF . 25° unless otherwise specified) Parameter Vi Test Conditions Min. Typ. DC operating input voltage Max. Unit 24 V VOl Output voltage 1 R load 1 Kn 5.0 5.05 5.1 V V 02H Output voltage 2 HIGH R load lKn VOl -0.1 5 VOl V V 02L Output voltage 2 LOW 101 Output current 1 = -5mA lIV Ol = -100mV I L01 Leakage output 1 current V 1N = 0 VOl" 3V 102 Output current 2 lIV 02 ViOl Output 1 dropout voltage (*j 101 101 101 -. V1T I nput threshold voltage V1TH Input threshold voltage hyst. lIV Ol Line regulation 1 lIV 02 Line regulation 2 lIV Ol Load regulation 1 = V mA 200 1 -100mV V ol +1.2 0.7 0.8 1.05 0.8 6.4 V 01 +1.7 1 1.3 250 7V < VIN < V V V mV 24V 101 = 5mA 5 50 mV 102 = 5mA 5 50 mV 40 80 mV 5mA < 101 5mA < 102 < 300mA Load regulation 2 IQ Qu ieseent cu rrent 0< V 1N < 13V 7V < V1N < 13V 102 = 101 " 5mA IQl Quiescent current 1 6.3V < VIN 1 VIN~ = 0 101 ~ 5mA 4_1_8 _ _ _ _ _ _ _ _ _ _ _ _ _ itA mA 300 = 10mA = 100mA = 200mA lIV 02 340 0.1 102 < < 200mA 13V 102 50 100 mV 4.5 1.6 6.5 3.5 mA mA 0.6 0.9 mA =0 ~ ~~~~m?u~:9:: ______________ L4905 ELECTRICAL CHARACTERISTICS (continued) Test Conditions Parameter V RT Reset threshold voltage VRTH Reset threshold hysteresis VRH V RL Reset output voltage HIGH Min. Typ. Max. Unit V02 -O·15 30 4.9 Vor°.o5 V 50 80 mV Vo2 -1 4.12 V02 0.4 V 11 ms 20 liS Reset output voltage LOW IR = 500"A IR = -5mA tRD Reset pulse delay Ct = 10nF td Timing capacitor discharge time Ct = 10nF t; VOl t;T Thermal drift -20°C';; Tamb .;; 125°C 0.3 - 0.8 mVrC t; V02 t;T Thermal drift -20°C';; Tamb .;; 125°C 0.3 - 0.8 mV/oC SVR1 Supply voltage rejection f = 100Hz 84 dB SVR2 Supply voltage rejection TJSD Thermal shut down 0.25 3 V R = 0.5V 10 = 100mA 5 54 50 50 V 80 dB 150 °c • The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25mV under constant output current condition. APPLICATION INFORMATION In power supplies for JJP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save data when the primary supply is removed. The L4905 makes it very easy to supply such equipments; it provides two voltage regulators (both 5V high precision) with separate inputs pi us a reset output for the data save function. CIR'CUIT OPERATION (see Fig. 1) After switch on Reg. 1 saturates until VOl rises to the nominal value. When the input 2 reaches V IT and the output 1 is higher than V RT the output 2 (V 02 ) switches on and the reset output (V R ) also goes high after a programmable time T RD (timing capacitor). V02 and V R are switched together at low level when one of the following conditions occurs: - an input overvoltage - an overload on the output 1 (VOl a switch off (V IN V IT - V ITH ); < < V RT ); and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The VOl output features: 5V internal reference without voltage divider between the output and the error comparator; very low drop series regulator element utilizing current mirrors; permit high output impedance and then very low leakage current error even in power down condition. This output may therefore be used to supply circuits continuously, such as volatile RAMs. allowing the use of a back-up battery. The VOl - _________ 51 SCiS-THOMSON _ _ _ _ _ _ _ _ _ _ _5.:..:...c. /8 • J I~ i1jJ"GO;OO@~~~GO;1i'OO@i!DGO;:;; 341 L4905 CIRCUIT OPERATION (continued) regulator also features low consumption (O.6mA typ.,) to minimize battery drain in applications where the VI regulator is permanently connected to a battery supply. The V02 output can supply other non essential 5V circuits wich may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be used as a "POWER DOWN INTERRUPT", permitting RAM access only in correct power conditions, or as a "BACKUP ENABLE" to transfer data into in a NV SHADOW MEMORY when the supply is in· terrupted. Fig. 1 SWITCH ON VOl OVERLOAD V02 OVERLOAD APPLICATION SUGGESTIONS Fig. 2 shows an application circuit for a J.l.P system typically used in trip computers or in car radios with programmable tuning. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OF F when the system is inactive. VIN OVERLOAD THERMAL SHUT SWITCH DOWN OFF Fig. 4 shows the L4905 with a back up battery on the VOl output to maintain a CMOS time-ofday clock and a stand by type N-MOS /J.P. The reset output makes sure that the RAM is forced into the low consumption stand by state, so the access to memory is inhibit and the back up battery voltage cannot drop so low that memory contents are corrupted. In this case the main on-off switch disconnects both regulators from the supply battery. ~6/_8_________________________ ~~~~~~~~~:~~~ ___________________________ 342 L4905 APPLICATION SUGGESTION (continued) Fig.2 INl REG.l Cl~ lBATTERY .I 1 ~C4 Il~F O.22~FI __ IN2 ~ VOO OUT 1 7 2 I REG. 2 6 C~ I L4905 10nF ~ 1 tol0~F I C5 -1: CMOS ~p WITH VOlATILE RAM VOO OTHER LOGIC @SV RESET OUT 5 VOO RESET OUT2 r C2± lpF 1 CMOS CLOCK RESET 5-10540 Fig. 3 - P.C. board component layout of fig. 2 (1 : 1 scale) GND IN1 OUT2 GND ----------------------------- ~~~~~~~v~~Jl ____________________________7~/8 343 L4905 APPLICATION SUGGESTION (continued) Fig.4 INI V O.22pF ± 1 IN 2 ±PF Z REG. 6 Z 4.7 P F ± I L4905 5 BACKUP RAM RESET 1 Fig. 5 - Quiescent current (Reg. 1) vs. output current ,uP WITH BATTERY VOO 11010pF RESET OUT CMOS CLOCK VS B BACKUP BATTERY OUTZ J: I I VOO _r VOO CT~ 10nF . ~~~ OUTI I LOI < lpA 7 REG. 1 OTHER LOGIC @ 5V RESET S -10541 Fig. 6 - Quiescent current (Reg. 1) vs. input voltage Fig. 7 - Total quiescent current vs. input voltage , I ) 101 (rnA) f-- Vii :12V V12 ,,0 101" 102 ::: SmA [o1~5mA Vii" Vi2 V I..- ..... 1--- J...-- l-- V / j..-- 8/8 344 ~~~~~~~~~--- @ V t---- 1/ j 12 200 V II V l/ 100 I ,~ 15 18 VII (V) 12 15 " V, (v) ~~~~m?l~:~~~~ ------~~--~--- L4920 L4921 VERY LOW DROP ADJUSTABLE REGULATORS PRELIMINARY DATA • VERY LOW DROP VOLTAGE • ADJUSTABLE OUTPUT VOLTAGE FROM 1.25 VTO 20 V • 400 mA OUTPUT CURRENT • LOW QUIESCENT CURRENT • OVERVOLTAGE AND REVERSE VOLTAGE PROTECTION • + 601- 60 V TRANSIENT PEAK VOLTAGE • SHORT CIRCUIT PROTECTION WITH FOLDBACK CHARACTERISTICS • THERMAL SHUT-DOWN These regulators are designed for automotive, industrial and consumer applications where low consumption is particularly important. In battery backup and standby applications the low consumption of these devices extends battery life. DESCRIPTION Pentawatt The L4920 and L4921 are adjustable voltage regulators with a very low voltage drop (0.4 V typo at 0.4 A Tj = 25 DC), low quiescent current and comprehensive on-chip protection. These devices are protected against load dump transients of ± 60 V, input overvoltage, polarity reversal and over heating. A foldback current limiter protects against load short circuits. The output voltage is adjustable through an external divider from 1.25 V to 20 V. The minimum operating input voltage is 5.2 V (TJ = 25 °C). Minidip (4 + 4) ORDER CODES: L4920 L4921 BLOCK DIAGRAM [ INPUT r! lPREREGLLATOOt-- .1 AMPLIFIER L- - 1 - - - - 1 - - r---'---, I PRg::'KlN } R~:!~f~E ~1 I I THERMAL J rRoTElcT'ON IC~~~i:~ JI FOLDBACK -1' OUTPUT - --:-.'- -' )::) ~fD' __ >--}L -_.- --- --). I ____ ./ OUI PU I Ir-==-==) J G R N.C. INPUI S·7QlS Tab connected to pin 3 5-7914 TEST AND APPLICATION CIRCUIT Lr"-...-.IN OUT 5-791112 c = 100 I1F is required for stability (ESR,,; 3 n over T range) R2 = 6.2 KU. THERMAL DATA Rth -amb Rth -p;n s Rth -case 214 346 l Thermal Resistance Junction-ambient Thermal Resistance Junction-pins Thermal Resistance Junction-case Minidip (4 + 4) Max Max Max 80°C/W 15 "C/W - Penta watt 60°C/W 3°C/W L4920/L4921 ELECTRICAL CHARACTERISTICS (for VI = 14.4 V; - 40::; Tj ::; 125 'C (note 1), Vo = 5 V; Co = 100 IlF, unless otherwise specified) Symbol Vi Parameter Operating Input Voltage Test Conditions Vo ;" 4.5 V 10 =400 mA VREF $ Vo < 4.5 V 10 = 400 mA Min. Max. Unit Vo + 0.9 Typ. 26 V 5.4 26 V V R'EF Reference Voltage 5.4 V < Vi < 26 V 1.25 1.33 V /l,.V o Line Regulation V 0 + 1.2 V < Vi < 26 V 10 = 5 mA Vo ;" 4.5 V 2 15 mV/v /l,.V o Load Regulation 5 mA < 10 < 400 mA (*) Vo ;" 4.5 V 5 25 mV/v Vo Dropout Voltage 0.25 0.5 0.5 0.9 V V 10 = 0 mA Vo+l.2V'> i Vt ,,35\1 ! 60 'S/1'1" I~,I 6D «\'5- ""~-----I~-'% - 50 ----- ~ 0,5 50KHz 100KHz 200KHz 1 ("I.) f--+,-,~.,,-,,-+-f.--­ - - I 100KHz 90 f---+--,----t--·+--t-+---t--j ~ 80 it,./::::t:::j:=t;t-";;-'-~15i~v ----,-70 f--~""',r. .......I---+-+-:::t_., &0 f--+--+-·-jo'C'DCCDE'---+--+--+ . ""+'-+---+ ---t-----li- iBVWBO ~_I I ' 0.5 50 100 (O/,) f-+--+---L-f-+-+--+--+-f--I vD : VREF f ,,50KHz r--- c-- I ,._- 6D DIODE BYWBO 1.5 0.5 1.5 15 10 (A) Fig. 23 Efficiency vs. output voltage _6077 (0',) t:50~ 90 ~ ~ .;:::; FL&::= !_J l~KHZ 10 =2A ~i :~;~80- f - - 1-- 12.5 _8/'-1_3_ _ _ _ _ _ _ _ _ _ _ _ _ 370 0 - Fig. 22 Efficiency vs. output current f-- r--- - 17 :lA -ti- I~~ ,.- - f" 25KHz DIODE BYW60 q; - - r-- Fig. 21 Efficiency vs. output current 607~ +_1- I \ 4> ~ - 25 17 fA) Fig. 20 Efficiency vs. output current Ptot ~ --:;: 1.2 D.S I (H-~--.-~--~ 2 x3300pF 50V EVF I L 296 *L~ IGr2; .IN5822 -5V I :]2nF . UI 220~F cS O.2A 'OOfJ F EKR ... 5.1 V ---r+-----1----~--()3.5 '------. . ~ _2.2~F A ~22,uF .J.. -'-----~---------'___O INHIBIT --:================-:+-_____________. . . * BYWBO I L 4960 10:5822 -m ~loomA 6.2Kfi ~ 100,uF . . . EKR '--___+'___~ + 1;~ I 470,uF 25V EKR ru SCS-THOMSON _ _ _ _ _ _ _ _ _ _ _ 1_1'--/13 'J I_ iiiln©I!IIQJ~~~©1JOOIQJ~D©~ 373 L4960 APPLICATION INFORMATION (continued) Fig. 29 - DC-DC converter 5.1V/4A, ± 12V/2.5A; a suggestion how to synchronize a negative output +12V12.5A 6.2K .il. 4.7K .il. L----*--+-+---------------------~~----~~---------2~GND 120pF L 3 03 2 x 220}JF 40V EKR 6.2K.il. 4.7K .il. _12V/2.5A 5-9323/2 L 1, L3 = COGEMA 946042 (969051) L2 = COGEMA 946044 (946045) 1 2 ,03 = BYW80 ° .° Fig. 30 - In multiple supplies several L4960s can be synchronized as shown L4960 L4960 .:.1:::2/..:1.:.3_ _ _ _ _ _ _ _ _ _ _ _ 374 ~ ~~~~m~,r"::~lt --------------- L4960 APPLICATION INFORMATION (continued) Fig. 31 - Regulator for distributed supplies MOUNTING INSTRUCTION The power dissipated in the circuit must be removed by adding an external heatsink. Thanks to the Heptawatt package attaching the heatsink is very simple, a screw or a compression spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon grease, to optimize the thermal contact, no electrical isolation is needed between the two surfaces. Fig. 32 - Mounting example = -------------- ~ ~~~~m&'l~~~ ____________ 1_3:..,:/1__ 3 375 L4962 1.5A POWER SWITHING REGULATOR PRELIMINARY DATA • • • • • • • • • 1.5A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE PRECISE (± 2 %) ON-CHIP REFERENCE HIGH SWITCHING FREQUENCY VERY HIGH EFFICIENCY (UP TO 90%) VERY FEW EXTERNAL COMPONENTS SOFT-START INTERNAL LIMITING CURRENT THERMAL SHUTDOWN plastic package and Heptawatt package and requires very few external components. Efficient operation at switching frequencies up to 150KHz allows a reduction in the size and cost of external filter components. The L4962 is a monolithic power switching regulator delivering 1.5A at a voltage veriable from 5V to 40V in step down configuration. Features of device include current limiting, soft start, thermal protection and 0 to 100% duty cycle for continuous operating mode. The L4962 is mounted in a 16-lead Powerdip Heptawatt Powerdip (12+ 2 +2) ORDERING NUMBER: L4962 (12 + 2 + 2 Powerdip) L4962E (Heptawatt) L4962EH (Horizontal Heptawatt) ABSOLUTE MAXIMUM RATINGS V ll , V 15 V 10 III 114 Ptot 50 50 -1 -5 5.5 7 1 20 4.3 15 -40 to 150 Input voltage Input to output voltage difference Negative output DC voltage Output peak voltage at t = O.l,us, f = 100KHz Voltage at pin 11, 15 Voltage at pin 10 Pin 11 sink current Pin 14 source current Power dissipation at T pins ~ 90°C (Powerdip) Tease ~ 90°C (Heptawatt) Junction and storage temperature V V V V V V mA mA W W °c -~-"----- BLOCK DIAGRAM --- (11 7 l496Z 1I Pin X Pin (X) September 1988 Powerdip Heptawatt 1/12 377 L4962 CONNECTION DIAGRAMS (Top view) N. C ,6 N.C OUTPUT '5 SOFT START N.C 1i. OSCILLATOR GND 13 GND GND 12 GNO NC 1I FREQ.CQMP 10 INPUT FEEDBACK l!lDI L SOFT START OSCILLATOR GND 1: FREQ, CQMP FEEDBACK INPUT }NPUT S-1195 Tab connected to pin 4 . N.C N C THERMAL DATA Rth j-case Rth j-plns Rthj-amb OUTPUT Heptawatt Thermal res stance junction-case Thermal res stance junction-pins Thermal res stance junction-ambient Powerdip max max max • Obtained with the GND pins soldered to printed circuit with minimized copper area. PIN FUNCTIONS HEPTAWATT POWERDIP NAME 1 7 SUPPLY VOLTAGE Unregulated voltage input, An internal regulator powers the internal logic. 2 10 FEEDBACK INPUT The feedback terminal of the regulation loop. The output is connected directly to this terminal for 5.1 V operation; it is connected via a divider for higher voltages. 3 11 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics, 4 4,5, 12, 13 GROUND Common ground terminal. 5 14 OSCILLATOR A parallel RC network connected to this terminal determines the switching frequency. This pin must be connected to pin 7 input when the internal oscillator is used. 6 15 SOFT START Soft start time constant. A capacitor is connected between this terminal and ground to define the soft start time constant. The capacitor also determines the average short circuit output current. 7 2 OUTPUT Regulator output. FUNCTION 11, 3, 6, I N.C. 8,9, 16 ,:::2/:..:.1=-2_ _ _ _ _ _ _ _ _ _ _ ID'l SCS-THOMSON 'J, " 378 ~Dc;IRI©~~~c;1i'IRI©iJlDc;;:; L4962 ELECTRICAL CHARACTERISTICS (Refer to the test circuit, TJ 35V, unless - otherwise specified) Parameter Test Conditions DYNAMIC CHARACTERISTICS Vo Output voltage range VI = 46V 10 = 1A VI Input voltage range V 0 = V ref to 36 V 10 = 1.5A 6.V o Line regulation VI = 10V to 40V 6.V o Load regulation Vo = V ref 10 = 0.5A to 1.5A V ref Internal reference voltage (pin 10) Vi = 9V to 46V 10 = 1A 6. V ref Average temperature coefficient of refer. voltage T j = O°C to 125°C 10 = lA 0.4 6T Vd Dropout voltage 10= 1.5A 1.5 10m Maximum operating load current VI = 9V to 46V Vo = V ref to 36V 1.5 12L Current limiting threshold (pin 2) VI =9V to 46V V 0 = V ref to 36V 2 ISH Input average current Vi = 46V; 7] Efficiency f=100KHz Vo = V ref 70 % 10 = lA Vo = 12V 80 % 50 56 dB 85 100 SVR f Supply voltage ripple rejection Vo = V ref 6. VI = 2V rms friPple = 100Hz Vo = V ref Voltage stability of switching frequency Vi = 9V to 46V Temperature stability of switching frequency T j = O°C to 125°C f max Maximum operating switchi ng freq uency Va = V,ef Tsd Thermal shutdown junction temperature I M 6.Tj 40 V 9 46 V 15 50 mV 8 20 mV 5.1 5.2 V 10 = 1A 5 output short-circuit mV/oC 2 V A 15 3.3 A 30 mA 10 = lA Switching frequency M 6.V V ref 10 = 1A 120 115 KHz 0.5 % 1 % 150 KHz 150 °c 3/12 379 L4962 ELECTRICAL CHARACTERISTICS (continued) Parameter Test Conditions DC CHARACTERISTICS 17Q Guiescent drain current ! 0% duty cycle -1 2L Output leakage current 30 100% duty cycle . I pins 2 and 14 open VI = 46V 15 0% duty cycle I 40 mA 20 mA 1 mA ! SOFT START 11550 Source current 100 130 160 fJA 11551 Sink current 50 70 120 fJA ERROR AMPLIFIER V llH High level output voltage V 10 = 4.7V III = 100fJA V llL Low level output voltage V 10 = 5.3V 111 = 100fJA 11151 Sink output current V 10 = 5.3V 100 150 fJA -1 1150 Source output current VlO = 4.7V 100 150 fJA 110 I nput bias current V 10 = 5.2V Gv DC open loop gain V ll = 1V to 3V V 3.5 0.5 2 46 55 10 V fJA dB OSCILLATOR 1-114 Oscillator source current 5 mA _4/_1_2_____________ ~ ~~~~m~1T~:~~~' --------______ 380 L4962 CIRCUIT OPERATION (refer to the block diagram) The L4962 is a monolithic stepdown switching citor Css and allowed to rise, linearly, as this regulator providing output voltages from 5.1 V capacitor is charged by a constant current source. to 40V and delivering 1.5A. Output overload protection is provided in the form of a current limiter. The load current is The regulation loop consists of a sawtooth oscilsensed by a internal metal resistor connected to lator, error amplifier, comparator and the output a comparator. When the load current exceeds a stage. An error signal is produced by comparing preset threshold this comparator sets a flip flop the output voltage with a precise 5.1 Von-chip which disables the output stage and discharges reference (zener zap trimmed to ± 2%). the soft start capacitor. A second comparator Th is error signal is then compared with the sawresets the flip flop when the voltage across the tooth signal to generate the fixed frequency soft start capacitor has fallen to O.4V. pulse width modulated pulses which drive the The output stage is thus re-enabled and the outoutput stage. put voltage rises under control of the soft start network. If the overload condition is still present The gain and frequency stability of the loop can the limiter will trigger again when the threshold be adjusted by an external RC network concurrent is reached. The average short circuit curnected to pin 11. Closing the loop directly gives rent is limited to a safe value by the dead time an output voltage of 5.1 V. Higher voltages are introduced by the soft start network. The obtained by inserting a voltage divider. thermal overload circuit disables circuit operation when the junction temperature reaches Output overcurrents at switch on are prevented by the soft start function. The error amplifier about 1500 C and has hysteresis to prevent output is initially clamped by the external capaunstable conditions. Fig. 1 - Soft start waveforms CLAMPED_ERROR O~CILLATOR AMi? OUTPUT OUTPUT NOMINAL ERROR AMP ~ OUTPUT OUTPUT CURRENT S _5835 Fig. 2 - Current limiterwaveforms CURRENT LIMITER TRIGGERS Llt-.4lT THRESHOlD AVERAGE SHORT CIRCUIT CURRENT r-r-L.~~-~~_~~~~ __ ~~~~~~L~L~~~~ _ _ _ _ _ _~ 5-9BB _____________ ml SCiS."THOMSON _ _ _ _ _ _ _ _ _ _ _ 5_1_12 • J, • jjJD~~[8cG";J,©1J:RlG~l©ili 381 L4962 Fig. 3 - Test and application circuit (Powerdip) R1 R4 10 7 L1 2 L4962 C1 1000)JF 63V C2 2.2nF 5-784611 1) D 1 : BYW98 or 3A Schottky diode, 45V of VRRM; 2) L1: CORE TYPE - MAGNETICS 58120 - A2 MPP N° TURNS 45, WIRE GAUGE: 0.8mm (20 AWG) 3) C6, C7: ROE, EKR 220llF 40V Fig. 5 - Quiescent drain current vs. supply voltage (100% duty cycle) Fig. 4 - Quiescent drain current vs. supply voltage (0% duty cycle) I,Q ImA ,_ - - G 6066 G-6D65 -t- 110 , ; ;1 j I , +- _. - I i , I 20 =r I --t-- I -- I \ I - I I I 13 -f ":.-~'+-~-+-+-+-+-4'- ir" I ----,-1 I 30 T I I 20 40 ~ ~~~~m~::~~~ V i (v) -25 0 - j_:- i _6_/1_2 _ _ _ _ _ _ _ _ _ _ _ _ 382 --t- +tJ i .- --- f+- (mA) _. Fig. 6 - Quiescent drain current vs. junction temperature (0% duty cycle) 25 50 75 100 Tj ('Cl -------------- L4962 Fig. 8 - Reference voltage (pin 10) vs. VI rdip) vs. VI Fig. 7 .. Quiescent drain current vs. junction tem· perature (100% duty cycle) + '10 c; - ~ C6 S ~rpl ------r---- (mA) +-1 Fig. 9 - Reference voltage (pin 10) vs. junction tem· perature IVI 1" f--,f---+~-+-~'i~-~~'-~ 10,,14. f--+-+--+-f--+--i 5 150 t---+---Rf--+-"-+-I ,>- " 1 96 90 -- -- \ lOOK ! f (Hz) 10 15 20 Fig. 14 response 25 30 35 40 45 'Ii (V) _25 0 25 ~t3",'.5nF LOAD CURRENT I-- - - r-- - - ---' 3 - I 1 1 I, I I I 2 f-- , I I f-- -50 C3 '" 2.2nF'" 10 - -f-- l- OUTPUT VOLTA1GE CHANGE IIIII '~.•. i'-: IIII t 10 125 I II I VI 'o"IA "- 100 RI (KA) -------------- i.U ~~~~m~lTr;1:~~l1 (ms) 1$0 TJ (~) G-680 Vi VOI"VRE~ 1 .~ 100 75 Fig. 15 .. Load transient response Line transient INPUT VOLTAGE :. 50 (;-6070 (KHz I ,"-. I-- '. \ ! 10K Vo·Vr~1 "0 -160 lK V,.J5V r-- 10' 1\ 100 ""o·Vrf'f r- Fig. 13 .' Switching fre· quency vs. R2 (see test circuit) G- 4,.2/1 f (KHz) ! _120 \ I 10 Fig. 12 .. Switching fre· quency vs. junction tem· perature - - -so ~ I--T 1,("() (KH;tJ -- i _ I--- 'f ,\ ---\-~--~ f - I \ . 'f" ! +- -.-- 60 V I (v) Fig. 11 .. Switching fre· quency vs. input voltage Fig. 10 - Open loop fre· quency and phase response of error amplifier G, IdB I 40 ---+ f- IT f- I f - L I AI f-- f= - r-- I I 1 (m.,) 7/12 383 L4962 Fig. 16 - Supply voltage ripple rejection vs. frequency '" ~'~ti~ (dBl 70 F I i! I If I ,-,--,----,---',--,--,-,---+-'-'T'-, (v) __ .. ---'I--+--+---4-+-+-+-\--I if' " -~ tJJ '0 11'1 ~2VR~5 <'-6084 '0 ,,' ft I I 1.6 - I ! . : I - 12-.1.5A I- --r" i I 075 0.5 2.5 Fig. 19 Efficiency vs. output current Fig. 20 Efficiency vs. output current ('/.) I-+.-,.-;C'~OKocH'",=:+---+---j-+-+--+---1 1.11--+----';.--+_+-+--+__+-_+-+--+ Vi :35V I r-- Va "VREF-,_-t---+---t_+--+~_-/ 90 f---t-I--+--+I--I--+-+-+---- ~ 1-~-+-I-4--+~-+-+-t---1 50 0 Fig. 21 Efficiency vs. output current ".---.~-r---r---,--,-,--r=r'-'--, ~ f=-100KHz- 90 Fig. 18 - Dropout voltage between pin 7 and 2 vs. junction temperature Vo=-Vref lolA r " -- Tr~ v, ~35V 60 50 Fig. 17 - Dropout voltage between pin 7 and pin 2 vs. current at pin 2 (0 ('/.) f---t''-.'"50i;;K-;'-H,c-'_=_+-+-t--t---t-f;'OOKHz- 90 I---.."-+.-;-.,,c-,+--~--+-t--+--+---t-- ---t 1_:2 5e-50KHz 00 60 1-+--+--+-+--+--+-t--~-+---1 1-+--+---4-+-+--- t-molJE-- f--------~ BYW9B a.' '" 0.15 10 (A) 0.5 Fig. 22 Efficiency vs. output voltage DIODE DIODE VSK31,O V5K340 0,75 10 (A) Fig. 23 Efficiency output voltage (;- ~ ('/. I vs. ~ 0.5 0.75 Fig. 24-Maximum allowable power dissipation vs. ambient temperature (Powerdip) 0-),$'11 83 ~ ,~t. ('/. I ~lS0KHZ 90 ---;; ~ :r V-- 100KHz p- ~OKHZ 90 ......-:: p- Vi .35\1 10 :lA -+ DIODE V5K340 ~I-- ---;; r::::: :::.- <, \ 20 ";, ~~1-G" Vi _35'1 10 :IA ,.I:'~~ DIODE BYW98 -I 10 384 .,.~ J'q,,+ Ii8/12 ~ f\ "'>.,. 100KHz 20 50 ~ .. :fut ~".~ -'f;t- ~ -\-" L4962 APPLICATION INFORMATION Fig. 25 - Typical application circuit L1 V; 0--_----17 ~-4~__~____~~~Vo L4962 15 14 4,5,12,13 11 10 BYW98 (6 40V C7 R4 (5 22)-' F R3 R2 4.3Kfi GND 4.7 KIt GND 5- 93.0 C1 , C6 , C7 : EKR (ROE) D 1 : BYW98 OR V ISK340 (SCHOTTKY) SUGGESTED INDUCTORS (L 1 ): MAGNETICS 58120 - A2MPP - 45 TURNS - WIRE GAUGE 0.8mm 120AWG) COGEMA 946043 OR U 15. GUP15. 60 TURNS 1mm, AIR GAP 0.8mm (20AWG) - COGEMA 969051 Fig. 26 - P.C. board and component layout of the circuit of Fig. 25 (1 : 1 scale) Resistor values for standard output 7 voltages _____________________________ ~~~~~~~~~:~~©~ Vo R3 R4 12V 15V 18V 24V 4.7Kn 4.7Kn 4.7Kn 4.7Kn 6.2Kn 9.1Kn 12Kn 18Kn __________________________ 9~/l_2 385 L4962 APPLICATION INFORMATION (continued) Fig. 27 - A minimal 5.1V fixed regulator; very few components are required INtfIBIT FLIP HOP o A 15 4 5,12,13 • COGEMA 946043 969051 •• EKR (ROE) (TOROID CORE) , (U15 CORE) 2.2IJF~C5S Fig. 28 - Programmable power supply 1~ 2. 2'J!JpF BYW98 40V 5 - 9342fl Vo = 5.1V to 15V ' 10 = 1.5A max Load regulation (0.5A to 1.5A) = 10mV (V o = 5.1V) Line regulation (220V ± 15% and to 10 = 1A) = 15mV (V o = 5.1VI ~lO~/~12~______________________ ~~~~~~g~I~~~ 386 ___________________________ L4962 APPLICATION INFORMATION (continued) Fig. 29 - DC-DC converter 5.1 V14A. ± 12V11 A. A suggestion how to synchron ize a negative output 150,uH L4962 +12V11A L1 BYW98 2, 220;"F _40 V EKR 6.2KIl 47 K Il '~--+-~----------------------~~~----------------~~GND 120pF 150,uH L 3 BYW98 2x220!,F 40V EKR 62 K·Jl 4.7 K Jl _12VI1A 5-9341/2 L1, L3 = COGEMA 946043 (969051) L2 = COGEMA 946044 (946045) Fig. 30 - In multiple supplies several L4962s can be'synchronized as shown Fig, 31 - Preregulator for distributed supplies L4962 10-4011 " L 4962 5-9339/1 * L2 and C2 are necessary to reduce the switching frequency spikes when linear regulators are remote from L4962 11/12 387 L4962 MOUNTING INSTRUCTION mils). During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. The RthJ-amb of the L4962 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 32). The diagram of figure 33 shows the Rth l-amb as a function of the side "Q" of two equa square copper areas having the thickness of 35~ (1.4 Fig. 32 - Example of P.C. board copper area which is used as heatsi nk COPPER Fig. 33 - Maximum dissipable power and junction to ambient thermal resistance vs. side "Q" AREA lSI' THICKNESS G·JtI. " ( eo r\ Rlh j-amb -...... • r--- r- >-- 40 - ~I-" f.---- '0 ~- Ptot (lamb. 'O'C) 10 ]Q 100 I {mml 31111 p, C, BOARD _12~/_12_______________________ ~1~~~~~~ 388 __________________________ L4964 HIGH CURRENT SWITCHING REGULATOR • • • • • • • • • • • 4 A OUTPUT CURRENT 5.1 V TO 28 V OUTPUT VOLTAGE RANGE 0 TO 100 % DUTY CYCLE RANGE PRECISE (± 3 %) ON-CHIP REFERENCE SWITCHING FREQUENCY UP TO 120 KHz VERY HIGH EFFICIENCY (UP TO 90 %) VERY FEW EXTERNAL COMPONENTS SOFT START RESET OUTPUT CURRENT LIMITING INPUT FOR REMOTE INHIBIT AND SYNCHRONUS PWM • THERMAL SHUTDOWN output for microprocessors and a PWM comparator input for synchronization in multichip configurations. The L4964 is mounted in a 15-lead Multiwatt® plastic power package and requires very few external components. Efficient operation at switching frequencies up to 120 KHz allows a reduction in the size and cost of external filter components. Multiwau® (15·lead) DESCRIPTION The L4964 is a stepdown power switching regulator delivering 4 A at a voltage variable from 5.1 V to 28 V. Features of the device include overload protection, soft start, remote inhibit, thermal protection, a reset ORDER CODES: L4964 L4964HT BLOCK DIAGRAM September 1988 1/12 389 L4964 ABSOLUTE MAXIMUM RATINGS Symbol Vi Vi - V 2 V2 V12 Vs, V7, Vg V1Q, VB, V1 V14 Value Unit Input Voltage (pin 3) Parameter 36 V Input to Output Voltage Difference 38 V Output DC Voltage Output Peak Voltage at t = 0.1 !lsec f = 100 kHz -1 -7 V V Voltage at Pin 12 10 V Voltage at Pins 5, 7 and 9 5.5 V Voltage at Pins 10, 6 and 13 7 V Voltage at Pin 14 (114" 1 mA) Vi Ig Pin 9 Sink Current 1 mA 111 Pin 11 Source Current 20 mA 114 Pin 14 Sink Current (V 14 < 5 V) 50 mA P101 Power Dissipation at T case" 90 °C 20 W Tj, T s1g Junction and Storage Temperature - 40 to 150 °C THERMAL DATA Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 3 35 CONNECTION DIAGRAM (top view) 4t- 15 14 13 12 11 10. g' 8 7 6 5 -$-~ ~1 / 5-581,9/2 Tab connl'Cted to pin 8 Note: Pins 1, 4, 15 must not be connected. Leave open circuit. 2/12 390 N.C. RESET OUTPUT RESET DELAY RESU INPUT OSCILLATOR FEEDBACK INPUT FREQUENCY COMPENSATION GROUND SYNC. INPUT INHIBIT INPUT SOFT-START N.C, SUPPLY VOLTAGE OUTPUT N.C. L4964 PIN FUNCTIONS N° Name 1 N.C. 2 OUTPUT 3 SUPPLY VOLTAGE Function Must not be connected. Leave open circuit. Regulator Output. Unregulated Voltage Input. An internal regulator powers the L4964's internal logic. 4 N.C. 5 SOFT START Soft Start Time Constant. A capacitor is connected between this terminal and ground to define the soft start time constant. This capacitor also determines the average short circuit output current. 6 INHIBIT INPUT TTL - Level Remote Inhibit. A logic high level on this input disables the L4964. 7 SYNC INPUT Must not be connected. Leave open circuit. Multiple L4964's are synchronized by connecting the pin 7 inputs together and omitting the oscillator RC network on all but one device. S GROUND 9 FREQUENCY COMPENSATION A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. Common Ground Terminal. 10 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1 V operation; it is connected via a divider for higher voltages. 11 OSCILLATOR A parallel RC network connected to this terminal determines the switching frequency. The pin must be connected to pin 7 input when the internal oscillator is used. 12 RESET INPUT Input of the Reset Circuit. The threshold is roughly 5 V. It may be connected to the beedback point or via a divider to the input. 13 RESET DELAY A capacitor connected between this terminal and ground determines the reset signal delay time. 14 RESET OUTPUT 15 N.C. Open Collector Reset Signal Output. This output is high when the supply is safe. Must not be connected. Leave open circuit. CIRCUIT OPERATION (refer to the block diagram) The L4964 is a monolithic stepdown switching regulator providing output voltages from 5.1 V to 28 V and delivering 4A. The regulation loop consists of a sawtooth oscillator, error amplifier, comparator and the output stage. An error signal is produced by comparing the output voltage with a precise 5.1 Von-chip reference (zener zap trimmed to ± 3 %). This error signal is then compared with the sawtooth signal to generate the fixed frequency pulse width modulated pulses which drive the output stage. The gain and frequency stability of the loop can be ajusted by an external RC network connected to pin 9. Closing the loop directly gives an output voltage of 5.1 V. Higher voltages are obtained by inserting a voltage divider. Output overcurrents at switch on are prevented by the soft start function. The error amplifier output is initially clamped by the external capacitor Css and allowed to rise, linearly, as this capacitor is charged by a constant current source. Output overload protection is provided in the form of a current limiter. The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold this comparator sets a flip flop which disables the output stage and discharges the soft start capacitor. A second comparator resets the flip flop when the voltage across the soft start capacitor has fallen to 0.4 V. The output stage is thus re-enable and the output voltage rises under contro of the soft start network. If the overload condition is still present the limiter will trigger again when the thershold current is reached. The average short circuit current is limited to a safe value by the dead time introduced by the soft start network. 3/12 391 L4964 The reset circuit generates an output signal when the supply voltage exceeds a threshold programmed by an extemal divider. The reset signal is generated with a delay time programmed by an external capacitor. When the supply falls below the threshold the reset output goes low immediately. The reset output is an open collector. A TTL - level input is provided for applications such as remote on/off control. This input is activated by high level and disables circuit operation. After an inhibit the L4964 restarts under control of the soft start network. The thermal overload circuit disables circuit operation when the junction temperature reaches about 150 and has hysteresis to prevent unstable conditions. Figure 1 : Reset Output Waveforms. OUTPUT NOW STABLE,RESET GOES HIGH IOOmV OF HYSTERESIS I AN INTERRUPTION OF SUPPLY CAUSES RESET OF MICRQ + _L_ _ .,........:....------,; RESET THRESHOLD- I AT POWER DOWN MICRO IS INHIBITED IMMEDIATELY ----- ----- - - MONITORED VOLTAGE RESET OUTPUT Figure 2 : Soft Start Waveforms. OSCILLATOR OUTPUT NOMINAL ERROR AM~­ OUTPUT OUTPUT CURRENT S _5835 4/12 392 L4964 Figure 3 : Current Limiter Waveforms. 12 5-6596(1 ELECTRICAL CHARACTERISTICS (refer to the test circuits T j specified) jSymbolj Parameter = 25 DC, Vi = 25 V, Test Conditions unless otherwise I Min. I Typ. I Max. I Unit I Fig. DYNAMIC CHARACTERISTICS (pin 6 to GND unless otherwise specified) Vo Output Voltage Range V, = 36 V 10 = 1 A Vref 28 V 4 Vi Input Voltage Range Vo =V ref to 28 V 10 = 3 A 9 36 V 4 !1Vo Line Regulation Vi = 10 V to 30 V, Vo = Vref, 10 = 2 A 15 70 mV 4 !1Vo Load Regulation 10 = 1 A to 2 A 10 30 mV 4 10 = 0.5 A to 3 A 15 50 mV 4 5.1 5.25 V 4 Vo =Vref I I Internal Reference Voltage (pin 10) Vi = 9 V to 36 V 10 = 2 A Average Temperature Coefficient of Reference Voltage Tj = a 'C to 125°C Vd Dropout Voltage between Pin 2 and Pin 3 10 = 3 A 10 m Maximum Operating Load Current VI = 9 V to 36 V, 12L Current Limiting Threshold (pin 2) Vi = 9 V to 36 V Vo = Vref to 28 V ISH Input Average Current Vi = 36 V ; Output Short-circuited Vref !J.V ref -- !J.T 4.95 10 = 2 A 10 = 2 A Vo =Vref to 28 V my/DC 0.4 2 3.2 1.5 2.4 80 4 V 4 A 4 8 A 4 140 mA 4 4 4.5 V 5/12 393 L4964 ELECTRICAL CHARACTERISTICS (continued) ISymbol1 Parameter Test Conditions Min. I Typ. I Max. I Unit I Fig. I DYNAMIC CHARACTERISTICS (continued) 11 SVR Effiency 10 = 3 A Supply Voltage Ripple Rejection 75 % 4 IVo =12V 85 % 4 I'1VI = 2 Vrms Vo =Vref f Switching Frequency I'1f -- Voltage Stability of Switching Frequency Vi = 9 V to 36 V -- I'1f I'1T J Temperature Stability of Switching Frequency T j = a °C to 125°C f max Maximum Operating Switching Frequency Vo =Vref Tsd Thermal Shutdown Junction Temperature I'1 Vi I Vo =Vref fripple = 100 Hz 10 = 2 A 46 40 56 - dB 4 50 60 kHz 4 0.5 % 4 1 % 4 kHz - °C - 120 10 = 1 A 135 145 DC CHARACTERISTICS 130 -12l I V6 = 0 Quiescent Drain Current Vi = 36 V V 7 = 0 V S1 : B S2:B Output Leakage Current Vi = 36 V, V6 = 3 V, S1 : B, S2 : A, V 7 = 0 V I V 6 =3V 66 100 mA 6a 30 50 mA 6a 2 mA 6a SOFT START Source Current V6 = 0 V, Sink Current Vs = 3 V Vs = 3 V INHIBIT V6l Low Input Voltage Vi = 9 V to 36 V V6H High Input Voltage V7 = 0 V - 16l -16H 6/12 394 Input Current with Low Vi = 9 V to 36 V Input Voltage V7 = 0 V Input Current with S1 : B High Input Voltage S2: B S1 : B S2: B - 0.3 0.8 V 6a 2 5.5 V 6a V6 = 0.8 V 20 iJA 6a V6 = 2 V 10 iJA 6a L4964 ELECTRICAL CHARACTERISTICS (continued) ISymbol1 Parameter Test Conditions I Min. I Typ. I Max. I Unit I Fig. I ERROR AMPLIFIER V 9H High Level Output Voltage V10 ~4.7V, Ig ~100flA,S1 : A, S2 :A V 9L Low Level Output Voltage V 10 ~5.3V, Ig ~100flA,S1 : A, S2 :E 1951 Sink Output Current V10 ~ 5.3 V, S1 : A, S2 :B 100 150 flA 6c Source Output Current V1o~4.7V, S1 :A, S2 :D 100 150 flA 6c S2 :C 40 55 -19 so 110 Input Bias Current V10 Gv DC Open Loop Gain Vg ~5.2 ~ V 3.4 0.6 S1 : B 1 V to 3 V, S1 : A, 2 20 V 6c V 6c flA 6c dB 6c 10 flA 6a - mA 6a Vref V 6d V 6d V 6d mV 6d OSCILLATOR AND PWM COMPARATOR ~ -17 Input Bias Current of PWM Comparator V7 -111 Oscillator Source Current V11 Rising Threshold Voltage Vi 0.5 V to 3.5 V ~2 V, S1 :A, S2: B 4 RESET V 12R V12 F V13D ~ S2: B, Delay Threshold Voltage V12~5.3V, vref Vref S1 :A, S2: B 4.3 4.5 4.7 100 Output Saturation Volt. 114 Input Bias Current V12 ~ 5 mA; ~ V12~4.7V; S1, S2: B S1 : B, S2 : B 0 V to V,ef, V12 ~ 5.3 V so Delay Source Current V13~3V I 51 Delay Sink Current S1 :A S2 : B IV12~4.7V Output Leakage Current V, 114 Vref -150mV -100mV V 14S -1 13 Vref 4.75 Falling Threshold Voltage Delay Threshold Voltage Hysteresis 113 S1 : B, -150mV -100mV -50mV V13 H 112 9 V to 36 V, ~ 36 V, V 12 ~ 5.3 V, S1 : B, S2 : A 60 0.4 V 6d 1 10 ~ 6d 110 150 8 100 flA 6d mA 6d flA 6d 7/12 395 I r L4964 Figure 4: Dynamic Test Circuit. RESET "01~--~~"J L 4964 ]"' R5 t 10 "Hn 22~F GN00--- T"-1.2nF "TI .--- J - -~ -+------- "'-------"---oONO INHIBIT C7, C8 : EKR (ROE) L1 : L ~ 300 ~H at 8 A Core type: MAGNETICS 58930 - A2 MPP R ~ 500 mil N' turns' 43 Wire Gauge: 1 mm (18 AWG) " - - - - - - - - - - - - - - - - - - - - - - - _ . _ - - - - - - - - - - - - - _ . _ - - - - - _.. Figure 5 : PC. Board and Component Layout of the Circuit of Fig. 4 (1:1 scale). 8/12 396 L4964 Figure 6: DC Test Circuits. Figure 6b. Figure 6a. i· 10Vi L 4964 ~-.--- ! lOO f.'F oB L 4964 S-684212 Figure 6c. ,V i 0--------<.-----. r / }-----1r--lIO 100 ,uF L 4964 1 - Set V ,0 FOR V9 ~ 1 V 2 - Change V10 to obtain V9 ~ 3 V 3 _Gv ~ DVo 2V *lJoltmeter with input imp.dance?:.50Mn !3.V 10 5_68l..1Ol1 '---------------------------_._------------_.- ---- J Figure 6d. ~-----------~------ l I S-684S/2 9/12 397 L4964 Figure 7 : Switching Frequency vs. R1 (see fig. 4). Figure 8 : Open Loop Frequency and Phase Response of Error Amplifier (see fig. 6c). - G !l43111 (KHz ) \ 10' I~L5nF f\ G-!J219 Gy (dB) 60 .......... Gy 50 \ .. \ r\ .8 Figure 9 : Reference Voltage (pin 10) vs. Junction Temperature (see fig. 4). - -160 \ -10 RI(Kn) 10 100 lK 10K lOOK f (Hz) 1M Figure 10 : Power Dissipation (L4964 qnly) vs. Input Voltage. G !J429 Vrot G_!J430 Ptol (W) (V ) YI=25V 5.100 5ms 'o=SOI'" . . . .'::.•. ,. . ._''\ ~.:.:-:" ".: ,.\. <" " ORDER CODE: L4970 I BLOCK DIAGRAM Multiwatt 15 , -----------"'" --------,~ --_.---------, ! S.1,U 17U 1.4 Ui is SYNC "::"::l-~~~ 1 Ct se Rose ~2 boot Ufeedb COIIP. L497G C55 fl88L49?8-BfB IN --~~~~~~~~~~~~~~---~~~~----- September 1988 _J 1/16 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 401 L4970 ABSOLUTE MAXIMUM RATINGS Symbol Test Conditions Unit Vg Input Voltage 55 V Vg Input Operating Voltage 50 V V7 Output DC Voltage Output Peak Voltage at t = 0.1 -1 -7 V V 65 V g + 15 V V V V6 Parameter ~s f = 200 KHz Bootstrap Voltage Bootstrap Operating Voltage Input Voltage at Pins 3, 11, 12 12 V4 Reset Output Voltage 50 V 14 Reset Output Sink Current 50 mA V3,Vtt,Vt2 Vs, V tO , Vt3 Is It ° 1'2 P,ot T t , Tst9 Input Voltage at Pin 5, 10, 13 Reset Delay Sink Current 7 V 30 mA Error Amplifier Output Sink Current 10 mA Soft Start Sink Current 30 mA Total Power Dissipation at T case < 120 cC 30 W - 40 to 150 'C Junction and Storage Temperature PIN CONNECTION (top views) ~ f'"h --qT Ur-ef S.1U 13 12 SYNC SOFT START FEEDBACK INPUT FREQ. COMPENSATION Ui GNO OUTPUT BOOTSTRAP 11 1B B 7 6 5 4 -$-~ L r 12U 14 ~ Teb connactlld to pin B RESET DELAY RESET OUT RESET INPUT Cose Rose 88L"!1711~Cl THERMAL DATA Thermal Resistance Junction-case Thermal Resistance Junction-ambient 2/16 402 Max Max 1 35 L4970 PIN FUNCTIONS N° Function Name 1 OSCILLATOR Rose. External resistor connected to ground determines the constant charging current of Cose. 2 OSCILLATOR Cose. External capacitor connected to ground determines (with Rosel the switching frequency. 3 RESET INPUT Input of Power Fail Circuit. The threshold is 5.1 V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 15 with an external resistor when not used. 4 RESET OUT Open Collector Reset/Power Fail Signal Output. This output is high when the supply and the output voltages are safe. 5 RESET DELAY A Cd capacitor connected between this terminal and ground determines the reset signal delay time. 6 BOOTSTRAP A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. 7 OUTPUT Regulator Output. 8 GROUND Common Ground Terminal. 9 SUPPLY VOLTAGE Unregulated Voltage Input. 10 FREQUENCY COMPENSATION A serie RC network connected between this terminal and ground determines the regulation loop gain characteristics. 11 FEEDBACK INPUT The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1 V operation ; it is connected via a divider for higher voltages. 12 SOFT START Soft Start Time Constant. A capacitor is connected between this terminal and ground to define the soft start time constant. 13 SYNC INPUT Multiple L4970's are synchronized by connecting pin 13 inputs togheter or via an external syncr. pulse. 14 Vref 5.1 V ref Device Reference Voltage. 15 Vstart Internal Start-up Circuit to Drive the Power Stage. Figure 1 : Feedforward Waveform. U2 / I / // ,, ,, ,, ,/ '/ '/ /" ~ / I- I-----; ~ Ucc=38U Ucc=15U / Uc U7 I-- - - Ucc",15 U Ucc-39 U T ~ t188L497B-B7 3/16 403 L4970 Figure 2 : Soft Start Function. CU'lMPFD ERROR AMPLI F I ER OUTPUT OSCILLATOR OUTPUT ~ NOMINAL ERROR AMPLH IE::R OUTPUT CURRENT SOFT START RAMP - - - -__ NBt Figure 3 : Limiting Current Function. ase ILLATOR CONTROL VOL rAGE VOL TAGE ACROSS THE CATCH DIODE I I I I ----------- ----------eLK I SET CLOCK CLK1 I PEAK INDUCTOR CURRENT PIN? CURRENT NBBL49?B-B9 4/16 404 L4970 Figure 4 : Reset and Power Fall Functions. A INPUT RESET FALLING THRESHOLD START - UP THRESHOLD - -TURN-OFF THRESHOLD ,OU Uo 5t::v ~.lU l ~5TERE5V5 ~ SOFT START TIME OUTPUT RESET +--,f'tOR' DELAV RESET +--+ 'tDMI -I'---TIPOUER, FAIL TIME f1BBL49?B-1B B - - - - - - - - INPUT RESET THRESHOLD START UP THRESHOLD Uo S.1U / COUTPUT RESET -,f---,'I tOR OELA'r' RESET fl88L4978-11 5/16 405 L4970 ELECTRICAL CHARACTERISTICS (refer to the test circuit, T j otherwise specified) I Symbol I Parameter Test Conditions I = 25°C, V j = 35 V, f = 200 kHz, unless Min. I Typ. I Max. I Unit Fig. 50 V 5 5.1 5.2 V 5 12 30 mV 5 10 20 30 50 mV mV 5 5.1 5.2 V 7 10 25 mV 7 40 DYNAMIC CHARACTERISTICS Vi Input Volt. Range (pin 9) Vo = Vrel to 40 V 10 = 10 A 15 Vo Output Voltage Vi = 15 V to 50 V 10 =5A;Vo =Vrel 5 t1Vo Line Regulation Vi = 15 V to 50 V 10 =2A;Vo =Vrel t1Vo Load Regulation Vo = Vrel 10 = 3 A to 6 A 10 = 2 A to lOA V REF SECTION (pin 14) Reference Voltage VREF Line Regulation t1VREF ",VREF t1V REF /t1 T IREF VSTART V ref 5 Vi=.15Vt050V V,2 = 0 Load Regulation IREF = 0 to 3 mA 20 mV 7 Average Temp. Coell. Ref. Voltage Tj =0 °C to 125°c OA mV/C 7 Short Circuit Curr. Limit VREF = 0 70 mA 7 SECTION (pin 15) Reference Voltage P '2 = 0 V 12 12.6 V 7 "'Vrel Line Regulation P,2 =OV; Vi = 15 to 50 V OA 1 V 7 "'Vrel Load Regulation Irel = 0 to 1 mA P'2 = 0 V 50 200 mV 7 I ref Short Circuit Current Limit P,2 =OV;P ,5 =OV Vd Dropout Voltage between Pin 9 and 7 10 = 5 A 10 = 10 A 17L Max Limiting Current Vi = 15 V to 50 V Vo = V rei to 40 V Efficiency 6/16 406 llA mA 7 0.55 1.1 80 0.8 1.6 V V 5 11 12.5 14 A 5 10 = 5 A Vo =Vrel Vo = 12 V 80 85 92 % % 10 = 10 A Vo=Vrel V o =12V 75 80 87 % 5 5 L4970 ELECTRICAL CHARACTERISTICS (continued) Min. Typ. Supply Voltage Ripple Reject. Vi = 2 VRMS ; 10 = 5 A 1 = 100 Hz ; Vo = Vrel 56 60 Switching Freq. R = 15 KQ ; C = 2.2 nF 180 200 M/~Vi Volt. Stability 01 Switching Freq. Vi = 15 V to 45 V 2 MIT) Temp. Stability 01 Switch. Freq. T) = 0 to 125 f max Max. Operating Switch. Freq. Vo :::: V ret Symbol SVR 1 Test Conditions Parameter 'c Max. Unit Fig. dB 5 220 KHz 5 6 % 5 % 5 KHz 5 V 7A V 7A 1 500 10 = 10 A DC CHARACTERISTICS Vgon Turn-on Thresh. V9Hys, Turn-off Hyster. 190 1900 III Quiescent Current 10 12 1 V'2=0;S1=D; S2 = C ; S4 = A Operating Quiescent Curr. V, 2 = 0 1 = 200 KHz Out Leak Current 11 10 16 mA 7A 16 20 mA 7A 2 mA 7A V 7C 0.7 V 7C Vi = 55 V ; S3 = A ; V,2 = 0 V ; 1 = 200 KHz SOFT START (pin 12) Soft Start Source Current V,2 = 3 V ; V " Output Saturation Voltage 1,2s = 20 mA ; V9 = 10 V =0 V ERROR AMPLIFIER V , OH High Level out Voltage V,0L Low Level out Voltage 1, 0 P " 1, 0 P" = - 50flA ; S2 = A = 0 V ; S1 = C 6 = 50flA ; S2 = A =6V;S1 =C Input Bias Current V = 5 ; S1 = B ; " Rs = 10K 2 10 uA 7C Input off Voltage P = Vas; " Rs = 50 Q ; S1 = A 2 10 mV 7C Gv DC Open Loop Gain PVCM = 4 V ; Rs = 50 Q ; S1 = A 60 dB 7C SVR Supply Volt. Rej. 15 < Vi < 50 V 60 dB 7C 1" VOS 80 7/16 407 L4970 RAMP GENERATOR (pin 2) Ramp Valley Ramp Peak V, = 15 V V, = 45 V Min Ramp Current S1 =A;11 =1001lA Max Ramp Current S1 = A ; 11 = 1 mA 1.5 V 7A 2.5 5.5 V V 7A Il A mA 7A Fig. 270 2.4 2.7 Min. Typ. 300 7A SYNC FUNCTION (pin 13) Symbol Parameter Test Conditions SYNC Low Input Voltage V, = 15 V to 50 V Max. Unit - 0.3 0.9 V 3.5 SYNC High Input Voltage V, 2 = 0 5.5 V - 1'3L Sync Input Current with Low Input Voltage V,3 =0.9 V 0.4 mA - 1'3 H Input Current with High Input Voltage V , 3 = 3.5 V 1.5 mA SYNC ns _~ __50 Delay Output Amplitude Output Pulse Width 5 V 0.5 Ilsec. Vref - 100 V mV 70 RESET AND P. FAIL FUNCTIONS Vref - 50 - _ ...100 120 Rising Threshold Voltage (pin 11) S1 = B 80 mV 70 V5H Delay High Threshold Voltage S1 = B 5 5.1 5.2 V 70 V5L Delay Low Threshold Voltage S1 = B 1 1.1 1.2 V 70 - 15S0 Delay Source Current V3 = 5.3 V ; Vs = 3 V S1 = A 40 55 70 Il A 70 Delay Sink Current V3 =4.7 V ;V5 =3 V S1 =A 10 mA 70 Hysteresis 15s 1 V4s 14 V3R Out Saturation Voltage 14 = 15 mA ; S2 = B 0.4 V 70 Output Leak Current V 4 = 50 V ; S2 = A 100 70 Rising Threshold Voltage Hysteresis 13 8/16 408 V, = 15 to 50 V S1 = B Vref - 150 V11R Input Bias Current 5 5.1 5.2 Il A V 0.4 0.5 0.6 V 70 1 3 Il A 70 70 ::!! cc r:: -' ... :;;:Z8 01&1 ~1'11'1> M ID N 15 9 3 ~z esl ezl e31 13 RZ 6 4 7 L-1110U~ •~ , L4970 5 B 10 I I~ Ii ".7K SYNC .8 r "0 "0 1 2 111 t ,., (") , o Vo Ii 13X~Vl: +S BIIPSIIIIO 113VEKR 113Y ell 2.7K 2.2nF -8 27 o , liND '0GND L4970-2BIS:: LIB r ..,. o(C .j:Io ~ '" <0 ..... o L4970 Figure 6: Mockup of the Circuit of Fig. 5 (1.1 scale). 10/16 -------------------410 ~~~~~~~~~~ L4970 Figure 7: DC Test Circuits. '" ~~'" '0 .u O~U15~,---15 -,1,..--2----,14 ~ J: 2.2uF 2.2uF ~ J: nBBL4!J?B-Bfi '----._-------_._--_._---- Figure 7A. Vi I o r.:H.'",:____ 1BuF o A Ii S1 9 54 ~ 8...-_ _1-,2_:--'3 I A V re f -5 .1V V7 oC 51 1.2nF 8 A1. 1. J: I 2 . 2nF N88L49?8-84 Figure 78. :I: 1BuF 9 112 12 11 8 N88L49?8-85 ~ ~.,I SGS·1HOMSON 11/16 i'!iD©OO~~rn«:1i"iiI@IllD©$ 411 L4970 Figure 7C. -----~-lfaU;- - - - ~~----I .? ~ Ui 9 l'OOUA oc } - - . . - - . . - - - l 11 I 1188L4978-82 Figure 70. ~------~-- ----5V Vi ! B 3 52 V4 15 12/16 -~----- 412 ffBBL4!J?B-B3 15mA L4970 Figure 8 : Quiescent Drain Current vs. Supply Voltage (0 % duty cycle - see fig. 7A). NBBL 497B - 14 -. 190 (mAl f·588KHz 28 18 /'~ 16 ~ -::::: r--- I---" V 14 12 18 14 I 28 48 "-., l'-- f--- - .. "- '-..., f·· 5813KHz I"~ r--:: ........- f-188KHz NB8KHZ :--- F:::: r-f-.. _. WITHOUT OSCILunOR 58 U i (U I NBB1497B-15 - "-., 5 (rnA I 1 H(d 59 t- 1 S0 1j ( • C I Figure 11 : Reference Voltage (pin 14) vs. Vi (see fig. 7). NB8L 497f1-17 r-- t,) ref ,c- IVI 22 5.128 f.588KHz 2B 5.118 L 18 f..-I-- f-288KHz 16 l- t-- f.188KHz 14 """'" 8 Figure 10 : Quiescent Drain Current vs. Duty Cycle. 1900 ~ 18 WITHOUT OSCILLATOR 38 ~ 12 I I 18 I'" 16 f.188KHz 6 ~ 18 ::::::..t--1 t:-:: f- ....- 8 --- 28 f..-- ..-+f-28~HZ I-- NBBL 497B -15 190 I (rnA I Figure 9: Quiescent Drain Current vs. Junction Temperature (0 % duty cycle). 5.188 5.898 f-- - -- . 5.888 r--- - 12 f-- - IB r--- .-- r-- - 8 L 2B 4B 5B 8B O. C. I % I Figure 12 : Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7). NBBL497f1-1B U14 ( VI IB 15 29 25 3B 35 413 45 58 VilVI Figure 13 : Reference Voltage (pin 15) vs. V, (see fig. 7). rtBBL497f1 19 VIS (UI 12.5138 S.158 12.2S8 5.125 5.188 5.875 12.1388 -- 11.758 ....-I - 11.588 11.258 5.959 11.888 Ui·35V 18.758 -59 5B 1813 T j (. CI 18 15 28 25 38 35 48 45 58 UilUI 13/16 413 L4970 Figure 14: Reference Voltage (pin 15) vs. Junction Temperature (see fig. 7). Figure 15 : Switching Frequency vs. Input Voltage (see fig. 5). f188L4978-28 f188L4978 - 21 U1S 1KHz) I U) 218 12.4 285 12.2 288 - --- 12.8 11.8 r--- 195 I-- 198 185 11.6 r--- U,.3SU _. '--- -51'1 18 15 28 25 38 35 48 45 58 58 UiIU) Figure 17 : Switching Frequency vs. R4 (see fig. 5). Figure 16 : Switching Frequency vs. Junction Temperature (see fig. 5). f188L4978-22 G· 6430 1KHz) 228 - 288 100 181'1 161'1 , -- -t _. r- 148 -~-T-- U i . 35U 121'1 10 1~O------~--~--~~-L-R4~(K~n~) -51'1 58 8 188 Tjl'C) Figure 18 : Line Transient Response (see fig. 5). f188L4978 23 I Uo·5.1U Ia.5A - /;2~~~~Z c--- 1\ f188L4978-24 U, U·i .35U Vo-Uref I U) - LOAD CURRENT r--- - 58 48 li ""Uo Figure 19 : Load Transient Response (see fig. 5). 10 IA) 8 6 38 v ImU) 4 2 ""Ua +58 ImU) If' 8 [" +588 '-../ -58 8 -588 8 14/16 414 2 3 4 tlms) 1'1.4 8.8 1.2 1.6 tlms) L4970 ---------_._----- Figure 20 : Dropout Voltage between Pin 9 and Pin 7 vs. Current at Pin 7. tl88L497{]-25 VO {VI VD tl88L4978-26 -,-- {V I 1.6 1.6 1.2 V /" 0.8 L /" V L V ~ ...--- 0.4 l# ~ o 1 2 3 T j 025" C ~ - ./ 4 5 V v 6 7 8 {W I ='1..L -- Uo=Ur'ef - c- ~ V V ~/ ....-- ---- loolGA V 20 UJ -T- 30 -- tl88L497{]-28 r--- I -- t-"Jo V V "';;- r-. / f.::: -~ 75 -- ~- - , / 65 / /" -- - -~- - - - l~-- 35 1~ Vo(V) tl88L497{]-3& n I 88 - -f.2B9KHz - ,t - ./ - 91l , l\::jA V -_. f • 199K;;'>-1-- 91l V = - HI {% Uo"Vref L.50uH 85 Vl051lV Figure 25 : Efficiency vs. Output Voltage. tl88L497&-29 95 18 5 Figure 24 : Efficiency vs. Output Current. n L=50uH - 8 40 ----f-- f0288KHz 28 14 - 150 T J {" C I 11l1l [1--- -.-- 12 Io=5A hO.5A I---"' !--lo.4A I---"' f- I003A Figure 23 : Power Dissipation (device only) vs. Output Voltage. 15 V -- V 51l --- / ,/ V V ----- -50 .- --;-- r-- /. IOolBA ...-v r--!O_7A /' /. (W I ,,- 6 79 / /"' V p to t f0200KHz L=S(3uH ~- 80 / 1l.8 17{AI /" V tl88L497&-27 P to t 8 1.2. 0.4 Figure 22 : Power Dissipation (device only) vs. Input Voltage. 10 /"' V /. Tj.125"C {% Figure 21 : Dropout Voltage between Pin 9 and Pin 7 vs. Junction Temperature. f~IlIl~~ V ...--- f.509KHz ,-- V il 79 V i.59V IOolllA Vi·5IlV --Vi.35V - 51l 2 4 6 8 Io{AI 10 20 30 40 Vo {V I 15/16 415 l4970 Figure 26 : Power Dissipation Derating Curve. PD 391J 291J 191J B 69 99 128 159 C lamb 0 n88L4!1?1I-12 Figure 27 : lOA - 5.1 V Application Circuit. RESET OUT u, SYNC R6 R1 ~~~~~~~--~--~--~-,0Uo.5.1U ro- 1LA .. High State Enable Input Current (pin 11) 10 >LA 1.3 V 1300 >LA Vref Internal Reference Voltage (pin 9) .. Iref 1.2 1--- "------ ~ Reference Current (pin 9) Iref 1.25 == V re f/Rref R,el = 1.2 K!2 Ipd Peak Duration Control Current (pin 6) Ipd = l,e1/8 tpd Peak Duration Time (pin 6) tpd = C 1 VTh Ilpd Vlh=1.4V 110 130 180 >LA - - - - - - - -r--500 >L s Cl = 4.7 nF .. lod Off Duration Con~rol Current (pin 7) lod = I,ef 18 toff Off Duration Time (pin 7) tod = C2 Vth Ilod Vth = 104V .. Id1 NPN Driving Current (pin 15) Id2 PNP Driving Current (pin 8) Ip Peak Current (emitter of NPN Darlington) --~---- 110 -_. 130 180 >LA 50 >L s C2 = 4.7 nF Idl = 100 I,ef (only present during charging phase) 80 28 Id2 = 35 Iref - - f-----...- - - . Ip = 450 mViRsens Rsens = 0.1 n I 100 130 mA 48 4.2 4.5 4.8 mA lA 70 75 85 mV 2 V n 35 -- .. ~- -- Vh Holding Current Control Voltage Vh == Rsens III Ih = Emitter Current of N PN , Darlington Hn r Pin 2 Floating Pin 2 Externally Biased Holding Current Contrallnput Impedance (Pin 2) Peak to Hold Current Ratio Pin 2 Floating 100 150 200 5.8 6 6.2 0.97 1 1.03 .. Pin 6 Shorted 18 Sense Input Bias Current (Pin 3) ..Internal Clamping (Pin 16 to 15) >LA _. 1= 200 >LA 14 16 18 V Dump Protection Threshold Voltage (Pin 1) 28 32 34 V Rdl Dump Protection Threshold Input Impedance (Pin 1) 22 32 42 Kn Thermal Drift of Reference Voltage 420 100 _. Vdt Vclamp 4111 ~ 0.5 I i InV/oC L5832 ---_.-------------------------- APPLICATION INFORMATION The L5832 solenoid controller is intended for use with one or two external darlington transistors to drive inductive loads such as solenoids, relays, electric valves and DC motors. Controlled by a logic input and an inhibit input (both TTL compatible), the device drives the external darlington (s) to produce a load current waveform as shown in figure 3. This basic waveform shows that the device produces an initial current peak followed by a lower holding current. Both the peak and hol- ding current levels are regulated by the L5832's switchmode circuitry. The duration of the peak, the peak current level and holding current level can all be adjusted by external components. Moreover, by omitting C1, C2 or both it is possible to realize single-level current control, a transitory peak followed by a regulated holding current or a simple peak (figure 1). Figure 1 : Components Connected to Pins 6 and 7 Determine the Load Current Waveshape. COMPONENTS ON PINS 6 AND 7 LOAD CURRENT WAVEFORM --~-----~----------- H C1 I 7 S-6002 I C2 s-,oo' C2 I 5- 6005 f-----------~-----~--4_---------------~ HI ~-G006/1 C2 :'-6003 f---------- .------ 4----rJ S~'OOB 1 -----~--~- ------ - -- - --------- 5/11 421 L5832 The peak current level Ip, is set by the sensing resistor, Rsens, and is fou nd from : 0.45 Altematively, this level may be varied by adding a divider to pin 2 (R1, R2) and suitable values are found from: Rsens The holding current level, Ih, is set by a voltage applied to pin 2. If this pin is left open circuit an internal reference of 75 mV supervenes and the holding current is given by : where Vx = 3V, Rx = 5850Q. Rin = 150Q (Rin of pin 2) and Vext is the external voltage applied to the divider. Ip 6 Figure 2 : Application Circuit Showing all the Optional Components. In Particular it Illustrates how the Holding Current Level is Adjusted Independently of the Peak Current (with R1, R2, Vext) and how the Internal Zener Clamp is Connected. This Circuit Produces the Waveforms Shown in Fig.3. ,------------------------ - , ,~-,~ -'----------, _~LI1) . RL + VL toff= - R Note that if the load is a motor VL = Eg + VD. (VC02 is the voltage at the collector of 02). To ensure stability, a small capacitor (about 200 pF) must be connected between the base and collector of 02 when pin 16 is used. ,--------~------ MOTOR 9/11 425 l5832 Normally A I is a design parameter therefore C2 can be calculated directly from: C2= Pd = RLlL2 + VDIL(1- 0) + Vsat· IL 0 + RsIL20 RL = resistance of valve = 2Q VD = drop across diode, VD == 1V Vsat = saturation voltage of 02, == 1V Rs=R11 =220mQ o= duty cycle = 20 % where In(ILP -A I) RL + VL -Iref· L 12 RL ILp· RL + VL This application is particularly important because it allows the use of inductive loads with the lowest possible series resistance (compatible with constructional requirements) and therefore reduces notably the power dissipation. For example, an electric valve driven from 24V which draws 2A has a series resistance of 12Q and dissipates 48W . Using this circuit a valve with a 2Q series resistance can be used and the power dissipation is: therefore: Pd = 8 + 1.6 + 0.4 + 0.16 = 10.16W This given two advantages: the size (and cost) of the valve is reduced and the drive current is reduced from 2A to about 0.4A. The same consideration is also true for DC motors. Figure 7 : Application Circuit Using Only one Darlington. The Resistor and Zener Shown Dotted Activate the Load when Power is Applied. Vee .:;Vi-45 r--~--------------~ .L, l :5K n.;.sOKll. Ir' YIN r---o-----t,o I I I I ~3.9V 10.1 , I KJl A2 I I , G 0 L __ ~~~__~----~---4~--~--~------------~ lL .f- -----~//oo',...._..,...".,._V!o.. IJ.tr----- - ' I LOAD CURRENT "' I :' ,I " ., INPUT s- 5981 10/11 426 L5832 Figure 8: P.C. Board and Component Layout of the Circuit of Fig. 7 (1 :.1 Scale) C S-O'7e Figure 9: Application Circuit Showing how two Separate Supplies can be Used. 5V~~---- ________- - , R1 8 V1N 0---_--+-----I 10 L5832 R3 16 15 lKfl 11 RZ 7 4.5.1Z.13 3 'OKll C1 GNDo---+---~~ R5 l2' Kn CZ __~__~~~~~------~ <;-5'38411 The application circuit of figure 9 is very similar to figure 2 except that it shows the use of two supplies-one for the control circuit, one for the power stage. Chose R6 so that the voltage on pin 8 does not exceed 46V DC. This can be done simply bearing in mind that the pin 8 current is 35 IreI' R6 must not be too high if a very low supply voltage is used because: V smin = R6 . 16 + 4.75 . = 750 . 35 . 10- 3 + 4.75 = 31V Vsmtn The zener diode DZ can not exceed 62V because when Q1 is off and DZtriggered - the fast recirculation - the voltage on pin 8 may not exceed 60 V. 11/11 427 L6114 L6115 QUAD 100 V, DMOS SWITCH • OUTPUT VOLTAGE TO 100 V • 0.7 Q • • • • ROS(ON) SUPPLY VOLTAGE UP TO 60 V LOW INPUT CURRENT TTUCMOS COMPATIBLE INPUTS HIGH SWITCHING FREQUENCY (200 KHz) Powerdip 14 + 3 + 3 DESCRIPTION Realized with the Multipower-BCD mixed bipolar/CMOS/DMOS process, the L6114/15 monolithic quad DMOS switch is designed for high current, high voltage switching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTUCMOS compatible for direct connection to logic circuits. Each source is available for the insertion of the sense resistors in current control applications. Two versions are available: the L6114 mounted in a Powerdip 14+3+3 package and the L6115 in a 15lead Multiwatt package. Multiwatt-15 ORDER CODES: L6114 (Powerdip) L6115 (Multiwatt-15) CONNECTION DIAGRAMS (top view) GNO 19 GNO , 51 5, Dl I. 0' 52 15 53 02 " 03 vee 13 IN' EN 12 IN3 " IN2 S4 D4 S3 D3 IN4 IN 3 IN2 -= >,! :; '" M W U zc cr >- U> U> '"N W '" ! ........, >---. :"" die >- mount don ~ ze . ~.a8e 8.58 1.06 1.50 ~lnk q.mi I dlssi oting Freo =- 2.888 sq.mi 0.66 HM 76 3 hoal 2.80 2.50 5 3.00 3.56 4.80 4.50 5.00 DISSIPATED POl.£R ( I.bll ) 7/8 435 L6114/L6115 Figure 13: Transient Thermal Resistance for Single Pulses (Multiwatt). G - 6422 , 3 S IF' GLE u Pd • 2 !.bll :/ 9.091 PULSE mau, ed on boa d ~ 9.91 / V die V ~iz ~ / • 34.808 on die dl .lpaUng c eo .. 1S.6 9.1 1 TIr£ OR PULSE UIOTH ( 19 5 Cj.mils e, ~9.mll~ 199 1999 ) Figure 14 : Peak Transient Thermal Resistance vs.Pulse width and duty cycle (Multiwatt). G-6423 , 3 u OC • 9.5 29 ~ a: .... 9.4 ~ 9.3 :':! ~ '"iEw 19 .... xc 9.2 ~ NC 10 5-10£>60 $ (l) 01 02 15 14 13 12 11 10 NC 03 IN 3 IN 2 INl GNO EN VCC 9 8 7 6 5 53 NC $- " 3 52 2 NC L Tab connected to pin 8 51 5-10659 L6123 (Mulliw. 15) L6122 (Powerdip) THERMAL DATA ,-----,------- - ----------------------,----~-------, L-t Rth i-pins Thermal Resist;nce Junction-pins - - - - Rth j-ease Thermal Resistance Junction-case H~:amb ~ermal Resistance Junction-ambient_ _ I 2/6 438 __ Max Max Max Powerdip__~-~ultiwatt -15! 14°C/W I 3°C/W 65°C/W L 35 °C/W __ J t L6122-L6123 ELECTRICAL CHARACTERISTICS (T j r__ SYV::O'- Supply = 25 DC, Vcc = 40 :~t::eter Test<:;onditions I RDS (on) ~ V EN 10 ~ VINL, VENL Input Low Voltage VINH, VENH Input High Voltage IINL, IENL Input Low Current Input High Current IINH, IENH 100 (oft) Turn off Delay Time tf Fall Time V I mA I I mA V VDs~100V mA VDS ~ 80 V T J ~ 125°C mA 0_7 ID~1_5A - 0_3 0_8 V 7 V VIN, VEN ~ L - 100 VIN, VEN ~ H 10 Il A IlA 2 tr Unit -----i-------'------ ! Turn on Delay Time ------_.--Rise Time 48 9 1 mA Vcc214V VEN, VIN ~ H Max. 3 VEN ~ L Static Drain-source on Resistance _ Typ. 14 L Output Leakage Current n ; Min, All VIN ~ H V EN ~ Square Wave (200 KHz, 50 % DC) Drain Source Breakdown Voltage --- - I Dss --,------T-------- i --------1--- ~ ',:C_~~::::~~:;;, BV DSS V, unless otherwise specified) ID ~ 15 A --------j-------- td f-----'~"'---+_-- VSD (*) VSD (on) (*) -------- t See Test Circuit and Waveforms - - - - -------- ~ Source Drain Diode Forward ISD Voltage sourc_ e Drain Forward Voltage ISD ~ 1_5 A VIN, VEN ~ H (') Pulse test: pulse width ~ 300 ~s, duty cycle ~ 1_5 A V EN ~ L 2 %_ SWITCHING TIMES RESISTIVE LOAD Figure 1 : Test Circuit. + 4011 +4011 3/6 439 L6122-L6123 Figure 2 : Waveforms. 1.54 ---- -- 1.SA 90·'. 10 10 Id(On)J II VIN SV t-S_O_"I.L..-_ • _ _ _ _ _ _~ _ _ _ __ SV - - - - - - - - f ( SV I, Id(ofl) __ J SV -- (j VIN 5-9516 5-9817 b) a) Figure 3: Static Drain-source on Resistance. Figure 4 : Normalized Breakdown Voltage vs. Temperature. , ~f--- ROS(on ) 11 -- - -- 0.9 0.8 ---- 0.6 (V) l I I-+- r _.. - 0.3 o 4 G 6143 ROS(on ) Vee =40V VEN=Y!N =SV 10=0.SA V /' G-6ll9 Hi' Hi' 60 / I 1(j' 20 / 10 3 10' V 100 ISD (A) lei' 1~=15O"C V - Figure 6 : Typical Source-drain Diode Forward Voltage. 10' // -20 / 60 20 10' 1.8 /' -20 f--- - - r/ ./ " I---"" 0.8 ID(A) Figure 5 : Normalized on Resistance vs. Temperature. f- - ~ 0.9 - 10=250JJA Vee = 40V VEN=O ,,/ I r- - 440 V r-- 1.1 j..-- o.s 0.6 G- 6341 BVoss I V- 0.7 4/6 II .~ 50'1., VEN ,f"'- - - - - - - VEN l: 10'loj o 100 1&'1 SCS-THOMSON •/, fiIilOI::II©IW<©'II'IIi@IJIJOIC$ k": IL V II ~ Vee=40V VEN=O f--- '-- I / I II I 1/ /25'e I -40'C 0.8 1.2 1.6 VSO(V) L6122-L6123 Figure 7: Rth j-amb vs. Dissipated Power (Multiwatt). G- 601 .... w ~ ....<> ~ v ~ '------, >---...., -- C> i w >--... ~ ~ tree air moun ed on CB be cd '"""' u '"a ~ '"ru I :" .........., t---- die mount don :!I zc " H.5H 1.HH 1.SH ~tnk q.mil '~.B8B dtssi oling Frea '" 2_BBB sq.mi H_DD HM 7H 3 hf)() 2.HH 2.S0 5 3.00 3.S0 4.80 4.50 5.00 OISSIPATIO POt.[R ( \Jotl ) Figure 8 : Transient Thermal Resistance for Single Pulses (Multiwatt). G - 6422 ~ w :3 SIr- GLE 0 ~ a: ~ '" w '" ~ :g'" ~ Pd - 2 Lbll 1---. ~ J!' / ----B.B01 B.Bl /' cd on boo d mou V .... z: '"0:z: "'ULSE / die siz ~ / - 34_000 on die dt .tpallng c eo • 1G.G B.l TI~ 1 OR PULSE UlOTll lB q.mi Is o sq.mi 15 lBB lBBB s) 5/6 441 L6122-L6123 Figure 9: Peak Transient Thermal Resistance vs. Pulse Width and Duty Cycle (Multiwatt). G-6423 :3 "u ...~ DC - 8.S 28 9.4 IE :!l ..."' ...~ F 8.3 II< 19 .... z: 9.2 101 '"a:z: Pd - S IJoll ~ ""a: ~ free air 8.1 S DC-DUTY cve E______ !_ll.l,.ll.E._1.!. DJIf_____ _ PULSE REPETI ION PERIOD e.l 6/6 442 1ge Ie TItE OR PULSE /JID~ ( ... ) ieee L6201 0.30 DMOS FULL BRIDGE DRIVER ADVANCE DATA • SUPPLY VOLTAGE UP TO 48V • • 2A MAX PEAK CURRENT TOTAL RMS CURRENT UP TO 1.0A (limited by power dissipation) RDDs(oN) 0.3S1 (TYPICAL VALUEAT25°C) • • CROSS CONDUCTION PROTECTION • TTL COMPATIBLE DRIVE • OPERATING FREQUENCY UP TO 100KHz • • • THERMALSHUTDOWN INTERNAL LOGIC SUPPLY HIGH EFFICIENCY (TYPICAL 90%) to 48V and efficiently at high switching speeds. All the logic inputs are TTL, CMOS and p.C compatible. Each channel (half-bridge) of the device is controlled by a separate logic input, while a common enable controls both channels. The L6201 is mounted in an SO.20 package. Even at the full rated current and voltage no external heatsink is required at normal operating temperatures. DESCRIPTION The L6201 is a full bridge driver for motor control applications realized in Multipower-BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The DMOS output transistors can deliver 1.0A RMS at motor supply voltages up BLOCK DIAGRAM SO-20 (12+4+4) ORDERING NUMBER: L6201 OUT 1 OUT2 C SOOT 1 CSOOT 2 20 ENABli t-t---." IN 1 13 IN 2 '--JJ--t-J----"'--i18 S 10491 September 1988 1/12 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 443 L6201 ABSOLUTE MAXIMUM RATINGS Power supply Input or Enable voltage DC output current (note 1) - non repetitive « 1ms) Sensing voltage Boostrap peak voltage Total power dissipation (T pins = 90°C) (Tamb = 70°C no copper area on PCB) Storage and junction temperature 52 v -0.3 to 7 V A A V V W 1 5 -1 to 4 60 4 0.9 -40 to 150 W °C Notel: Pulse width limited only by junction temperature and the transient thermal impedance. CONNECTION DIAGRAM (Top view) SENSE ENABLE N.C. GND GND GND GND N.C. OUT.2 +VS Vref BOOT 2 IN.2 GND GND GND GND IN.1 BOOT OUT.1 BBL620J-CJ THERMAL DATA RthJ-Plns Thermal resistance junction-pins ~2/~1~2_______________________ ~!~~~g~~ 444 max 15 __________________________ L6201 PIN FUNCTIONS PIN NAME FUNCTION SENSE A resistance Rsense connected to this pin provides feedback for motor current control 2 ENABLE When a logic high is present on this pin the DMOS POWER transistors are enabled to be selectively driven by IN1 and IN2. 3 NO CONNECTION 4,5,6,7 GND 8 NO CONNECTION 9 OUT2 Output of the half bridge. 10 Vs Supply voltage. 11 OUT1 Output of the half bridge. 12 BOOT1 A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at high switching frequencies. 13 IN1 Digital input from the motor controller. 14,15,16,17 GND Common ground terminal. 18 IN2 Digital input from the motor controller. 19 BOOT2 A boostrap capacitor connected to this pin ensures efficient driving of the upper POWE R DMOS transistor at high switching frequencies. 20 V ref Internal voltage reference, a capacitor from this pin to GND increases stability of the POWER DMOS logic drive circuit. Common ground terminal. ------------- ~ !~~~m&=©~ ___________ ---=-3:..=..=/12 445 L6201 ELECTRICAL CHARACTERISTICS (Refer to the test circuits Tj = 25°C, Vs 36V, unless otherwise stated) Parameter Vs Supply voltage V ref Reference voltage Is Quiescent supply current Test Conditions EN = H EN = H EN = L V'N = L V'N = H Fig. 10 Min. Typ. Max. Unit 12 36 48 V 'L =0 13.5 V 10 10 8 mA mA mA fc Commutation frequency (*1 30 TJ Thermal shutdown 150 DC Td Dead time protection 100 ns 100 KHz TRANSISTORS OFF loss Leakage current Fig. 11 100 /J A 0.3 n 0.3 V ON Ros On resistance VOS(ON) Drain source voltage V sens Sensing voltage Fig. 9 los = 1.0A -1 4 V SOURCE DRAIN DIODE VSd Forward ON voltage Iso = 1.0A trr Reverse recovery time 'F = 1.0A tfr Forward recovery time EN; L dif Cit . = 25A//Js 0.9(**1 V 300 ns 200 ns LOGIC LEVELS V'NL, YEN L Input Low voltage -0.3 0.8 V V 1NL • VENH Input High voltage 2 7 V "NL, 'EN L Input Low current V'N. VEN = L -10 /J A "NH.'ENH Input High current V'N, VEN = H 30 /JA LOGIC CONTROL TO POWER DRIVE TIMING t1 (ViI Source current turn-off delay Fig.12 300 ns t2 (Vi' Source current fall time Fig.12 200 ns t3 (V,) Source current turn-on delay Fig.12 400 ns t4 (v,1 Source current rise time Fig.12 200 ns t5 (ViI Sink current turn-off delay Fig.13 300 ns t6 {ViI Sink current fall time Fig.13 200 ns t7 (Vi' Sink current turn-on delay Fig.13 400 ns ta (ViI Sink current rise time Fig.13 200 ns i ('1 Limited by power dissipation (**1 In synchronous rectification the drain - source voltage is of 0.3V typo 4/12 ..c:.:~_ _ _ _ _ _ _ _ _ _ _ _ 446 ,1. ~ SIiS-THOMSON ... lil!lO©OO@Il:o.m©'ii'I!l@i:!O©$ - - - - - - - - - - - - - - L6201 Fig. 2 - Quiescent current vs. frequency Fig. 1 - Typical Is normalized vs. T J G- 6J1~ G- IS Fig. 3 - Typical Is normalized vs. Vs 6316 Is Is ImA ) INo'ml~_~+-_+--+-_-t-t_t----t--+--j -+-+-H ~---b+-+-I--+-+-, 40 1.2 ...... 11 1 ............ 0.9 ...... 08 30 0.8 t----t--+---t--f--t-t----t--+--t--I 0.7 --, ,/' 20 15 V 0.4 o:J 0.3 i 10 -25 +25 +50 +75 IS 0 [A 100 50 TJ ('C) -1--+-+1-+-+-+-+-+-1 ~ :-r-t+-t--+--I-'-t--+--+---I V 0.6 0.5 +--+--1--+-----1---+-+-+...., 0.9 25 0.7 _.1 ~ 35 150 200 11KHz) Fig. 4 - Typical diode behaviour in synchronous rectification t/88L62fJl fJ4 5 10 i : ! 15 25 30 35 '0 45 20 Fig. 5 - Typical Ros vs. Vs ~ Vref Vs(V) (ON) ROSON [ (it) 18 1.6 \ 1.4 \ 1.2 /' / ,/ /' 9.2 / 9.4 9.6 V / / / \ 10 08 0.6 o4 O. 2 9.8 10 1 USO(Ul Fig. 6 - Ros (ON) normalized at 25°C vs. temperature typical values (;-6313 'Is :VREFIV) Fig. 7 - ROS (ON) vs. DMOS transistor current ROSON,-_,-_,-~-~t/~8~8~L~62TfJ~1--~fJ5 [O[ ~1 ROsonlT j ) 1.8 - RoSon(25') 9.3 16 / 1.4 12 ./ O. 8 V /' 9.2 ./ ,/ O. 6 -so 9.1 -25 0 +25 +50 +75 +100 ___________________________ TJ (-C) ~~~~~~?~:~~~ I (A 1 _________________________ 5~/1_2 447 L6201 Fig. 8 - Typical power dissipation vs. IL 1188L6281-86 Pd (W) 18 / / B 6 4 2 PHASE CHOPPING -- ENABLE CHOPPING 8 8 2 Fig. 8a - Two phase chopping Fig. 8b - One phase chopping ~6/~1~2________________________ ~~~~~~?~:~~~ 448 ___________________________ L6201 Fig. 8c - Enable chopping TEST CI RCUITS Fig.9 - Saturation voltage a) Source outputs b) Sink outputs Vs vs SI A r~ I V2 v1 r 10 SI 13 r~ 18 11 L6201 ~1 , ' GND A I" r V2 v1 10 13 1B L6201 11 r s- 10"92 s - 10493 For IN1 source output saturation: VI = "H" SI = A V = "H" SL = A 2 I For IN2 source output saturation: VI = "H" S, = B SL= B IV For IN1 sink output saturation: For I N2 sink output saturation: 2 = "H" VI = "H" S, = A V SL = A 2 = "L" VI = "H" S, = B V SL = B 2 = "L" I I 449 L6201 TEST CIRCUITS (continued) Fig. 11 Fig. 10 - Quiescent current - Leakage current vs b) Sink outputs a) Source outputs 51 vs v. 13 B l r--t Lv 10 ~1 10 11 18 L6201 L6201 A 5l '~ il 11 L6201 A~ 9 B GND GND 5-101,96 5-10495 GND 5-10 .. 94 SWITCHING TIMES Fig. 12 - Source current delay times vs. input v. ~ 36 V 10 IN 13118 1119 10·/. L6201 5V EN Vin 50·/. GND 5-10663 Fig. 13 - Sink current delay times vs. input v. = 36 v 10 IN 13/18 L6201 II~ EN GND 5-10665 "-'8/-=-1-=-2_ _ _ _ _ _ _ _ _ _ _ _ 450 $- 10666 ~ ~~~~m?1r~:~~~ -----,----------- L6201 CIRCUIT DESCRIPTION The L6201 is a monolithic full bridge switching motor driver realized in the new MultipowerBCD technology which allows the integration of multiple, isolated DMOS power transistors plus mixed CMOS/bipolar control circuits. In this way it has been possible to make all the control inputs TTL, CMOS and MC compatible and eliminate the necessity of external MOS drive components. the low-to-high transition a spike of the same polarity is generated by C2, preceded by a spike of the opposite polarity due to the charging of t)1," input capacity of the lower POWER DMOS transistor. (Fig. 15) Fig. 15 - Current typical spikes on the sensing pin vs·36V Ip.o.~A fal00ns LOGIC DRIVE INPUTS OUTPUT MOSFETS (*) INl IN2 V EN = H L L H H L H L H Sink 1, Sink 2 Sink 1, Source 2 Source 1, Sink 2 Sou rce 1 , Sou rce 2 VEN= L X X All transistors turned OFF L = Low H = High X = Don't care «) Numbers referred to INPUT 1 or INPUT2 controlled outputs stages S-10661 TRANSISTOR OPERATION ON STATE CROSS CONDUCTION Although the device guarantees the absence of cross-conduction, the presence of the intrinsic diodes in the POWER DMOS structure causes the genaration of current spikes on the sensing terminals. This is due to charge-discharge phenomena in the capacitors C 1 & C2 associated with the drain source junctions (Fig.14). When the output switches from high to low, a current spike is generated associated with the capacitor C1. On Fig. 14 - Intrinsic structures in the POWER DMOS transistors 's When one of the POWE R DMOS transistor is ON it can be considered as a resistor R os (ON) (= O.3Q) throughout the recommended operating range. In this condition the dissipated power is given by: PON = ROS(ON) • los2 The low Ros (ON) of the Multipower-BCD process can provide high currents with low power dissipation. OFF STATE When one of the POWE R DMOS transistor is OFF the Vos voltage is equal to the supply voltage and only the leakage current loss flows. The power dissipation during this period is given by: POFF = Vs • ID5S The power dissipation is in the order of pW and is negligible in comparison to that dissipated in the ON STATE. TRANSITIONS 5 - 9415 Like aliMOS power transistors the DMOS . POWE R transistors have as intrinsic diode between their source and drain that can operate as a fast freewheeling diode in switched mode ~ ~~~~m~1f~:s©~ ____________ ...:9/_12 451 L6201 applications. During recirculation with the ENABLE input high, the voltage drop across the transistor is Ros (ON,-' 10 and when the voltage reaches the diode voltage it is clamped to its characteristic. When the ENABLE .input is low, the POWER MOS is OFF and the diode carries all of the recirculation current. The power dissipated in the transitional times in the cycle depends upon the voltage and current waveforms in the application. ptr_ns . = IDS (t) • Vos (t) BOOSTRAP CAPACITORS To ensure that the POWER DMOS transistors are driven correctly gate source voltage of about 10V must be guaranteed for all of the N-channel DMOS transistors. This is no problem for the lower POWER DMOS transistors as their sources are refered to ground but a gate voltage greater than the supply voltage is necessary to drive the upper transistors. In the L6201 th is ach ieved by an internal charge pump circuit that guarantees correct DC drive in combination with the boostrap circuit charges the external Ce capacitors when the source transistor is OFF and the sink transistor is ON giving lower commutation losses in switched mode operation. For efficient charging the value of the boostrap capacitor should be greater than the input capacitance of the power transistor which is around 1 nF. It is recommended that a capacitance of at least 1(}nF is used for the bootstrap. If a smaller capacitor is used there is a risk that the POWE R transistors will not be fully turned on and they will show a higher RDS (ON)' On the other hand if a elevated value is used it is possible that a current spike may be produced in the sense resistor. REFERENCE To stabilise the internal drive circuit it is reo commended that a capacitor be placed between this pin and ground. A value of O.22JlF should be sufficient for most applications. This pin is also protected against a short circuit to ground. DEAD TIME To protect the device against simultaneous conduction in both arms of the bridge and the 452 resulting rail to rail short, the logic control circuit provides a dead time greater than 40ns. THERMAL PROTECTION A thermal protection circuit has been included that will disable the device if the junction temperature e reaches 150°C. When the temperature has fallen to a safe level the device restarts under the control of the input and enable signals. APPLICATION INFORMATION RECIRCULATION During recirculation with the ENABLE input high, the voltage drop across the transistor is R DS (ON)' IL for voltages less than O.7V and is clamped at a voltage depending on the characteristics of the source-drain diode for greater voltages. Although the device is protected against cross conduction, current spikes can appear on the current sense pin due to charge/discharge phenomena in the intrinsic source drain capacitances. In the application this does not cause any -problems because the voltage created across the sense resistor is usually much less than the peak value, although a small RC filter can be added if necessary. POWER DISSIPATION In order to achieve the high performance provided by the L6201 some attention must be paid to ensure that it has an adequate PCB area to dissipate the heat. The first stage of any thermal design is to calculate the dissipated power in the application, for this example the half step operation shown in figure 16 is considered. RISE TIME Tr When an arm of the half bridge is turned on current begins to flow in the inductive load until the maximum current I L is reached after a time Tr . The dissipated energy EOFF/ON is in this case: EOFF/ON = [Ros (ON) • IL2 • Tr j. 2/3 L6201 Fig. 16 - Load current in half step operation ON TIME TON During this time the energy dissipated is due to the ON resistance of the transistors EON and the commutation E COM ' As two of the POWE R DMOS transistors are ON EON is given by: EON = IL2 • Ros (ON) ·2· TON I~ the commutation the energy dissipated is: ECOM = Vs· I Tr I Ton I Tf i T d IL • TcoM • fswlTcH • TON Where: TCOM = Commutation Time and it is assumed that; TCOM = TTURN-ON = TTURN-OFF = lOOns fswlTCH = Chopper frequency FALL TIME Tf For this example it is assumed that the energy dissipated in this part of the cycle takes the same form as that shown for the rise time: EON/OFF = [Ros (ON) • IL2 • T f j. 2/3 QUIESCENT ENERGY The last contribution to the energy dissipation is due to the quiescent supply current and is given by: EQUIESCENT = IQUIESCENT • Vs • T Fig. 17 shows a two phase Bipolar Stepper Motor Control circuit where the current is controlled by the IC L297. Between the sense resistors and each sense input of the L297 a resistor must be foreseen; if the connections between the outputs of the L297 and the inputs of the L6201 need a long path, a resistor must be connected between each input of the L6201 and ground. When the Supply Voltage is higher than 26V or if the motor is driven through long wires, a snubber network made by the series of Rand C must be foreseen very near to the output pins of the L6201. The following formulas can be used: R"'" Vs/l p C = Ipl (dv/dt) where Vs is the max supply voltage foreseen on the ap· plication; Ip is the peak of the lood current; dvldt is the needed rise time of the output voltage (200V /tlsec is generally used). TOTAL ENERGY PER CYCLE ETOT = EOFF/ON + EON + ECOM + + EON/OFF + EQUIESCENT The Total Power Dissipation POlS is simply: Tr TON Tf Td T Rise time ON time Fall time Dead time Period T Tr+ToN+Tf+Td ----------------------------- ~~~~~~?v~:~~©~ ________________________ ~1~1~/1~2 453 L6201 Fig. 17 - Two phase Bipolar stepper motor control circuit with chopper current control and translator CW/CCW STEP HALF /FULl CONTROL MOTOR L62G1 RESET WINDING f5VJ~I---------+I OUTPUT LOGIC ENABLE L62G1 MOTOR WINDING SYNC 'SU 22K SENSE RESISTORS Fig. 18 - Rth junction to ambient vs.-"on board" heat sink area 88L6201-01 Rth (j -a) (0 C/W) 75 70 1\ \ Pu = \ 65 60 55 \ ~ 50 45 o 2 1W .............. -4 r-- f-6 B On Board Heat Sink Area (sQ.cm.) ~12~/_12_________________________ ~~~~~~?~:~~~~ 454 _____________________________ L6202 0.30 DMOS FULL BRIDGE DRIVER PRELIMINARY DATA • device is controlled by a separate logic input, while a common enable controls both channels. The L6202 is mounted in an l8-lead powerdip package and the six center pins are used to conduct heat to the PCB. Even at the full rated current and voltage no external heatsink is required at normal operating temperatures. SUPPLY VOLTAGE UP TO 48V • 5A MAX PEAK CURRENT • TOTAL RMS CURRENT UP TO 1.5A • R DS • • CROSS CONDUCTION PROTECTION TTL COMPATIBLE DRIVE • OPERATING FREQUENCY UP TO 100KHz • THERMAL SHUTDOWN (ON) 0.3£2 (TYPICAL VALUE AT 25°C) • INTERNAL LOGIC SUPPLY • HIGH EFFICIENCY (TYPICAL 90%) The L6202 is a full bridge driver for motor control applications realized in Multipower-BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The DMOS output transistors can deliver 1.5A RMS at motor supply voltages up to 48V and efficiently at high switching speeds. All the logic inputs are TTL, CMOS and MC compatible. Each channel (half-bridge) of the Powerdip 12+3+3 ORDERING NUMBER: L6202 BLOCK DIAGRAM OUT 1 OUT2 VREF 1 8 1 - - - -.... ENABLE H~---r"""", 2 '--P-+-+-""----t IN 2 16 4.5,6,13,14,15 5-9392/1 September 1988 1/16 455 L6202 ABSOLUTE MAXIMUM RATINGS Power supply Differential output voltage (Between pins 10 and 8) Input or Enable voltage Pulsed output current (note 1) - non repetitive « 1ms) Sensing voltage Boostrap peak voltage Total power dissipation (T pins = 90°C) (T amb = 70°C no copper area on PCB) (Tamb = 70°C 4cm 2 copper area on PCB) Storage and junction temperature 52 v 60 -0.3 to 7 5 V V A A 10 -1 to 4 60 5 1.3 2 -40 to 150 V V W W W °C Note1: Pulse width limited only by junction temperature and the transient thermal impedance. CONNECTION DIAGRAM (Top view) VREF SENSE ENABLE BOOT Z Z N.C. IN 2 GND GND GND GND GND GND 6 !N! N.C. B0011 OUT 2 OUT1 5-9424 THERMAL DATA Rth i-pins Rthi-amb Thermal resistance junction-pins Thermal resistance junction-ambient (Fig. 21) 6 ____________ 1.::.. ::.<2/c:: 456 ~ ~~~~m~::~~l1 max max 12 60 -------------- L6202 PIN FUNCTIONS PIN NAME FUNCTION SENSE A resistance Rsense connected to this pin provides feedback for motor current control. 2 ENABLE When a logic high is present on this pin the DMOS POWE R transistors are enabled to be selectively driven by IN1 and IN2. 3 NO CONNECTION 4 GND Common ground terminal. 5 GND Common ground terminal. 6 GND Common ground terminal. 7 NO CONNECTION 8 OUT2 Output of the half bridge. 9 Vs . Supply voltage. 10 OUTl Output of the half bridge. 11 BOOTl A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at high switching frequencies. 12 IN1 Digital input from the motor controller. 13 GND Common ground terminal. 14 GND Common ground terminal. 15 GND Common ground terminal. 16 IN2 Digital input from the motor controller. 17 BOOT2 A boostrap capacitor connected to this pin ensures efficient driving of the upper POWE R DMOS transistor at high switching frequencies. 18 V ref Internal voltage reference, a capacitor from this pin to GND increases stability of the POWER DMOS logic drive circuit. -------------- ~ ~~~~m?,r;\':~~l1-------------'-....:3.:....:/1:..::;6 '457 L6202 ELECTRICAL CHARACTERISTICS (Refer to the test circuits Tj 25°C, Vs 42V, unless otherwise stated) Parameter Vs Supply voltage V ref Reference voltage IREF Output current Is Quiescent supply current Test Conditions Min. 12 Typ. Max. Unit 36 48 V 13.5 V 2 EN = H EN = H EN = L V IN = L V IN = H Fig.10 10 10 8 IL =0 mA mA mA mA fc Commutation frequency (*) 30 Tj Thermal shutdown 150 °c Td Dead time protection 100 ns 100 KHz TRANSISTORS OFF loss Leakage current Fig. 11 Vs = 52V 1 mA ON Ros On resistance ROS(ON) Drain source voltage V sens Sensing voltage n 0.3 Fig.9 los = 1.2 A 0.36 V 4 -1 V SOURCE DRAIN DIODE VSd Forward ON voltage trr Reverse recovery time tl r Forward recovery time EN = L Iso = 1.2A I F =1.2A dif dt = 25A/p.s 0.9(**) V 300 ns 200 ns LOGIC LEVELS VIN L. VENL I nput Low voltage V IN L, V EN H Input High voltage liN L, lEN L Input Low current V IN , VEN = L IINH, IENH Input High current VIN, VEN = H -0.3 0.8 2 V 7 V -10 p.A 30 p.A 300 ns ns LOGIC CONTROL TO POWER DRIVE TIMING tl (Vi) Source current turn-off delay Fig.12 t2 (Vi) Source current fall time Fig.12 200 t3 (Vi) Source current turn-on delay Fig.12 400 ns t4 (Vi) Source current rise time Fig.12 200 n. t5 (Vi) Sink current turn-off delay Fig.13 300 ns t6 (Vi) Sink current fall time Fig.13 200 ns t7 (Vi) Sink current turn-on delay Fig.13 400 ns Sink current rise time Fig.13 200 ns t8 (Vi) (*) Limited by power dissipation (**) In synchronous rectification the drain-source voltage drop Vos is shown in fig. 4. ~4/~1~6________________________ ~~~~~~~~:~~ ___________________________ 458 L6202 Fig. 2 - Quiescent current vs. frequency Fig. 1 - Typical Is normal· ized vs. T J 6-6315 IS Is (mAI I Is (Norm J 40 1.2 1.1 Fig. 3 - Typical Is normal· ized vs. Vs G-6326 -- " o. 9 o. 6 o. 7 o. 6 o. 5 35 0.9 30 0.6 25 ;--.. I - f-- 0.5 ,/ 10 +50 50 T; (OCI +75 100 200 f(KH., ISO Fig. 4 Typical diode behaviour in synchronous rectification --I -- I t- 1-- 0.4 o. 3 +25 t 0.6 V 15 .. --l- 0.7 ,/ 20 o. 4 0.3 ·25 .L --\- 5 10 15 20 Fig. 5 - Typical RDS 25 30 35 40 45 V.(VI (ON) VS,Vs""Vref G- 631 ~ ROSON (lll (AI 1.6 1.6 1.4 1.2 Vos 1.0 0.6 0.6 \ \ \ , 0.4 0.2 0.2 0.4 06 0.8 1 1.2 10 1..4 1.6 Vsd. Vos (VI Fig. 6 - RDS (ON) normal· ized at 25°C vs. temperature typical values G-6313 J. .VREF(VI Fig. 7 - RDs (ON) vs. DMOS transistor current R~ONro-''-'-rT-r'-ro-.~~~ enl 1 Vs H-+++-H+-f-H-++H-l ~ ROSon CT J ) 1.6 - ROSon (25°) 0.5 16 1.4 ./' 1.2 ./ O. 6 H-++-HH-+-+--H-++H-l 0.4H-++-HH-+-+--H-++H-l "...- 0.3 ./ ,-/' 0.1 H-t--l--H'-t-+-+--H-t--t-H-l o. 6 -50 -25 H+++-IH++-H++-ft"l-l 0.2 H-++-H'-t-+-+--H-t--t-H-l 0 +25 +50 +75 +100 TJ ,·e) 6 I (A) 5/16 459 L6202 Fig. 8 - Typical power dissipation vs. IL G 632512 I .,-lIt!'" Iv\ 26 24 22 20 - ! 18 16 Vs=36V L=lmH T =2ms r-- IN' 1s =100KHz F::20KHz "\,- X - - PHASE CHOPPING CHOPPING ,>-'v.. 14 -'-'~ENABLE . / )S 12 10 '/. 8 6 4 2 l' , ~, ' /V Y: ..-::; ..... h ~~ I" ~ 2 3 4 5 6 Fig. 8a - Two phase chopping Fig. 8b - One phase chopping EN 0-_-<""-" 'jL~LI-t>-4-+-Q;IN2 ~6/:..::1.::..6_ _ _ _ _ _ _ _ _ _ _ _ ~ lil;m~lt 460 ------------- L6202 Fig. Bc - Enable chopping TEST CIRCUITS Fig. 9 - Saturation voltage b) Sink outputs a) Source outputs vs 51 A LS I V2 V1 I 9 51 12 r~ 16 L6202 A 10 r 8 4/5/6/13/14/15 V2 v1 9 12 16 2 L6202 10 8 1 5- 9 754 For IN1 source output saturation: V l = "H" S, = A SL = A I V 2 = "H" For IN2 source output saturation: V l = "H" S, = B SL = B I ___________________________ V 2 For IN1 sink output saturation: V l = "H" S, = A V = "L" SL = A 2 For IN2 sink output saturation: V l = "H" S, = B V2 SL = B = "H" ~~~~~~?~~:~~~ I I = "L" _________________________ 7~/l~6 461 L6202 TEST CIRCUITS (continued) Fig. 11 Fig. 10 - Quiescent current - Leakage current b) Sink outputs a) Source outputs Vs Vs 12 rLV 5' B .:I,' '6 52 L6202 .r:f~\ 2 L6202 '08 .:I, A.:I, V, r:1! A 5L r~~ .415/6113/14115 5' L6202 1/41516113/14/15 5- 976611 5-9756 1/415/6/13114'15 5-9755 SWITCHING TIMES Fig. 12 - Source current delay times vs. input chopper IL Vs :42V Imax=1.2A 90'/, IN '2116 10/8 ~JL L6202 10'/, 5V Yin EN 50'/, 4/5/6/13/14115 5-9757 5-9759 Fig. 13 - Sink current delay times vs. input chopper 1L Imax=1.2A 90'/, IN 10'/, L6202 101B EN 1/4/5/6/13114/15 5- 9758 .:.<8/...::1.::..6_ _ _ _ _ _ _ _ _ _ _ _ 462 5-9760 ~ ~~~~m~1ir::~~©~ ------------- L6202 CIRCUIT DESCRIPTION The L6202 is a monolithic full bridge switching motor driver realized in the new MultipowerBCD technology which allows the integration of multiple, isolated DMOS power transistors plus mixed CMOS/bipolar control circuits. In this way it has been possible to make all the control inputs TTL, CMOS and I1C compatible and eliminate the necessity of external MOS drive components. the low-to-high transition a spike of the same polarity is generated by C2, preceded by a spike of the opposite polarity due to the charging of the input capacity of the lower POWER DMOS transistor. (Fig. 15) Fig. 15 - Current typical spikes on the sensing pin Vout VS=42V Ip=O.5A f=100ns LOGIC DRIVE INPUTS OUTPUT MOSFETS (*' IN1 IN2 VEN= H L L H H L H L H Sink 1, Sink 2 Sink 1, Source 2 Source 1, Sink 2 Sou rce 1 , Sou rce 2 VEN= L X X All transistors turned OFF lsense L - Low H = High X = Don't care (*' Numbers referred to INPUT 1 or INPUT2 controlled outputs stages ::'-9426/1 TRANSISTOR OPERATION ON STATE CROSS CONDUCTION Although the device guarantees the absence of cross-conduction, the presence of the intrinsic diodes in the POWER DMOS structure causes the generation of current spikes on the sensing terminals. This is due to charge-discharge phenomena in the capacitors C1 & C2 associated with the drain source junctions (Fig. 14). When the output switches from high to row, a current spike is generated associated with the capacitor C1. On Fig. 14 - Intrinsic structures in the POWER DMOS transistors Vs o----j Cl PaN = ROS(ON) • los2 The low Ros (ON) of the Multipower-BCD process can provide high currents with low power dissipation. OFF STATE When one of the POWE R DMOS transistor is OFF the Vos voltage is equal to the supply voltage and only the leakage current loss flows. The power dissipation during this period is given by: POFF = Vs • loss Vout ~n When one of the POWE R DMOS transistor is ON it can be considered as a resistor Ros (ON) (= O.3n) throughout the recommended operating range. In this condition the dissipated power is given by: C2 The power dissipation is in the order of pW and is negligible in comparison to that dissipated in the ON STATE. TRANSITIONS '5-9425 Like all MOS power transistors the DMOS POWER transistors have as intrinsic diode between their source and drain that can operate as a fast freewheeling diode in switched mode 463 L6202 applications. During recirculation with the ENABLE input high, the voltage drop across the transistor is Ros (ON) • 10 and when the voltage reaches the diode voltage it is clamped to its characteristic. When the ENABLE input is low, the POWER MOS is OFF and the diode carries all of the recirculation current. The power dissipated in the transitional times in the cycle depends upon the voltage and current waveforms in the application. Ptrano. = los (t) • Vos (t) BOOSTRAP CAPACITORS To ensure that the POWER DMOS transistors are driven correctly gate source voltage of about 10V must be guaranteed for all of the N-channel DMOS transistors. This is no problem for the lower POWER DMOS transistors as their sources are refered to ground but a gate voltage greater than the supply voltage is necessary to drive the upper transistors. In the L6202 this achieved by an internal charge pump circuit that guarantees correct DC drive in combination with the boostrap circuit charges the external Cs capacitors when the source transistor is OFF and the sink transistor is ON giving lower commutation losses in switched mode operation. For efficient charging the value of the boostrap capacitor should be greater than the input capacitance of the power transistor which is around 1nF. It is recommended that a capacitance of at least 10nF is used for the bootstrap. If a smaller capacitor is used there is a risk that the POWE R transistors will not be fully turned on and they will show a higher Ros (ON)' On the other hand if a elevated value is used it is possible that a current spike may be produced in the sense resistor. REFERENCE To stabilise ·the internal drive circuit it is recommended that a capacitor be placed between this pin and ground. A value of 0.221lF should be sufficient for most applications. This pin is also protected against a short circuit to ground. DEAD TIME To protect the device against simultaneous conduction in both arms of the bridge and the :.10::!./.:.:16:.....-_ _ _ _~------ 464 resulting rail to rail short, the logic control circuit provides a dead time greater than 40ns. THERMAL PROTECTION A thermal protection circuit has been included that will disable the device if the junction temperature e reaches 150°C. When the temperatur.e has fallen to a safe level the device restarts under the control of the input and enable signals. APPLICATION INFORMATION RECI RCU LATION During recirculation with the ENABLE input high the voltage drop across the transistor is ROS'(ON)' IL for voltages less than 0.7V and is clamped at a voltage depending on the, characteristics of the source-drain diode for greater voltages. Although the device is protected against cross conduction, current spikes can appear on the current sense pin due to charge/discharge phenomena in the intrinsic source drain capacitances. In the application this does not cause any problems because the voltage created across the sense resistor is usually much less than the peak value, although a small RC filter can be added if necessary. POWER DISSIPATION In order to achieve the high performance provided by the L6202 some attention must be paid to ensure that it has an adequate PCB area to dissipate the heat. The first stage of any thermal design .is to calculate the dissipated power in the application, for this example the half step operation shown in figure 16 is considered. RISE TIME Tr When an arm of the half bridge is turned on current begins to flow in the inductive load until the maximum current IL is reached after a time Tr . The dissipated energy EOFF/ON is in this case: EOFF/ON = [ROS(ON)' IL2 • Trl' 2/3 ~ I~tm~~ ------------- L6202 ON TIME TON Fig. 16 During this time the energy dissipated is due to the ON resistance of the transistors EON and the commutation E COM ' As two of the POWER DMOS transistors are ON EON is given by: EON = IL2 0 ROS(ON) 02 0 TON In the commutation the energy dissipated is: I Tr I Ton I Tf i T d 5- 9761 Where: DC MOTOR SPEED CONTROL TCOM = Commutation Time and it is assumed that; TCOM = TTURN-DN = TTURN-OFF = lOOns fSWITCH = Chopper frequency FALL TIME Tf For this example it is assumed that the energy dissipated in this part of the cycle takes the same form as that shown for the rise time: EON/OFF = [Ros (ON) olL 2 0 T f 10 2/3 QUIESCENT ENERGY The last contribution to the energy dissipation is due to the quiescent supply current and is given by: EQUIESCENT = IQUIESCENT 0 Vs 0 T TOTAL ENERGY PER CYCLE ETOT = EOFF/ON + EON + ECOM + + EON/OFF + EQUIESCENT The Total Power Dissipation POlS is simply: Tr TON Tf Td T Rise time ON time Fall time Dead time Period T = Tr + TON + T f + Td ----------------------------- Since the L6202 integrates a full H-Bridge in a single package it is idealy suited for controlling small DC motors. When used for DC motor control the L6202 provides the power stage required for both speed and direction control. The L6202 can be combined with a current regulator like the L6506 to implement a transconductance amplifier for speed control, as shown in figure 17. In this configuration the L6506 sense the voltage across the sense resistor, RSENSE, to monitor the motor current. The L6506 then compares the sensed voltage to control the speed or during the brake of the L6202. Between the sense resistor and each sense input of the L6506 a resistor must be foreseen; if the connections between the outputs of the L6506 and the inputs of the L6202 need a long path, a resistor must be connected between each input of the L6202 and ground. When the Supply Voltage is higher than 26V or if the motor is driven through long wires, a snubber network made by the series of Rand C must be foreseen very near to the output pins of the L6202. The following formulas can be used: R "" Vs/lp C = Ip/(dv/dt) where Vs is the max Supply Voltage foreseen on the appl ication; Ip is the peak of the load current; dv/dt is the needed rise time of the output voltage (200V /tlsec is generally used). Higher voltages than 26V of V s require that a diode (BYW98) is connected between each power output pin and ground as well. If the Power Supply Cannot Sink Current, a suitable large capacitance must be used and connected near the supply pin of the L6202. Sometimes a capacitor at pin 17 of the L6506 let the application better work. ~~~~~~~v~:~~©~ ________________________ ~1~1~/1~6 465 L6202 Fig. 17 - Bidirectional DC motor control Vee .5U OI~ECTIOH 6 { Uspeed.1Umax (Ip max .. 2A) ::I: 3. 3nF 16 14 5 12 11 13 ? Ref 1 ENABLE ION/OFF) L65G6 18 R4 3 18K ~1 2.2K Uee.5U V 15 R3 Ref 2 tl88L5282-8111 BIPOLAR STEPPER MOTORS APPLICATIONS Bipolar stepper motors can be driven with an L297 or L6506, two L6202 bridge BCD drivers and very few external components. Together these three chips form a complete micropro· cessor-to-stepper motor interface. As shown in Fig. 18 and Fig. 19, the controller connect directly to the two bridge BCD drivers. External component requirements are minimal: an RC network to set the chopper frequency and a resistive divider to establish the comparator reference voltage (pin 15 for L297, pin 10 and 15 for L6506). These solutions have a very high efficiency because of low power dissipation. A snubber network at the output of the L6202 and resistors between the inputs of the some IC and GND cound be foreseen (see DC Motor Speed Control). HIGH CURRENT MICROSTEP DRIVE FOR STEPPE R MOTORS The L6202 can by used in conjunction with the L6217 to (figure 20) implement a high current microstepping controller for stepper motors. In this application the L6217 is used as a control 466 circuit and its outputs are used only to drive the inputs of the L6202. The application allows easy interface to a microprocessor since the L6217 may be connected directly to the micro· processor bus. In the circuit shown in Figure 20, the L6217 senses the motor current by monitoring the voltage across the sense resistors, RSENSE, and compares this value to the output of a 6 bit (7 bit ifthe L6217 A is used) 0 to A Converter. The L6217 controls the current using a fre· quency modulated, constant off time, switching controller. The off time of each coil may be set using and external resistor and capacitor connected to PTA and PTB. In this configuration the microprocessor simply loads the appropriate value for the direction of current flow through the coil and the data for the DAC into the L6217. The L6217 and L6202 then forms the complete interface between the micro and the motor. When the pins 3 and 4 of the L6217 (Test A and B) are low, the bridges must be in tri-state con· dition. For this reason two LM339 comparators must be used. The outputs of the comparators act on the enable inputs of the L6202 ICs. A bilevel operation can be used for decreasing the minimum controllable load current. The mi· L6202 nimum current that can be controlled is .given by the following expression: Vs IL (avg.l = - - - - - - - - - - - Rsense + (2Ros on + RLoAol/DC where R LOA 0 is the equivalent resistance of the load DC is the duty cycles given by Ton If 12V is forced on pin 18 (Reference voltagel and the supply voltage V 5 is reduced below 12V the on resistance tends to increase above the normal guaranteed 0.30hm. Consequently the minimum current will also be reduced, as given in the above expression. When a minimum current operation is required, a high signal at point (AI can disable the pnp transistors in fig. 20. So it's possible to operate at a V 5 of (7V - VSEI. Fig. 18 - Two phase Bipolar stepper motor control circuit with chopper current control 5U RESET ENABLE o ~ 1-+--__-, IN 1~j---~=====4[)~----~-1 L62G2 IN 2 <>--1--1===::tJ:::>-+-----1~ L62G2 IN 4 ~----I---=:jb::l:[)+------___I MOTOR WINDING MOTOR WINDING 22K 22K SENSE RESI:iTDRS !1BBL62B2-B2f1 _______________________ ~~~~~~~~~:~~©~ ____________________ ~1~3~/1~6 467 L6202 Fig. 19 - Two phase Bipolar stepper motor control circ;uit with chopper current control and translator a~ A C~/CCIJ STEP HALFIFULL RESET B MOTOR WINOING L6282 INH1 CONTROL (SU) OUTPUT LOGIC ENABLE C L6282 MOTOR WINOING SYNC 22K 'SU 22K SENSE RESISTORS Uref NBBL 6282 - 83f1 Fig. 20 - High current microstepping controller for stepper motors OUT B.1uF DB 01 02 03 04 OS 06 PH STB AlB 12U ::I 39 22B 38 • BYW9B-Se 37 36 B.luF lee L6217 lK 0176 ::I IA) 35 8.1uF 34 33 42 lN4148 31 38 12 .7U OUT NBBLli282-B4f1 ::..:14:!../.:::.:16~ _ _ _ _ _ _ _ _ _ _ _ 468 l.fi ~~~~m~::9lf ------------- L6202 THERMAL CHARACTERISTICS Fig.21 - Rth with two "on board" square heatsink vs. side Q of! W ~ 13.00 10.50 1.00 1.S0 2.010 2.S0 3.00 3.~0 4.1313 1 l em ) Fig. 22 - Transient thermal resistance for single pulses SING LE on board 10 II Pl LSE v/ 2W ~ .~ ------- /- / .. on boar ~ heat-sin area " 6 q. ,em 0.1 e.801 e.01 0.1 1 10 1130 10ee TItE OR PULSE WIDTH ( SEC ) ____________________________ ~~~~~~~~~:~~:1 ________________________ ~1_5~/1~6 469 L6202 Fig. 23 - Peak transient Rth VS. pulse width and duty cycle ~ DC 0.4 ! ~ ~ 0.> 20 0.3 -- 10 B.2 >~ 'g" "''" / / on boo d hool ,i nk are ~-0.1 cr it 0.1 10 TIrlE OR PULSE WIDTH ( ms ) 16/16 470 - G !!iq.cm II P(peak) - 5 100 1~aa L6203 0.30 DMOS FULL BRIDGE DRIVER PRELIMINARY DATA • SUPPLY VOLTAGE UP TO 48V deliver 4A RMS at motor supply voltages up to 48V and efficiently at high switch speeds. All the logic inputs are TTL, CMOS and MC compatible. Each channel (half-bridge) of the device is controlled by a separate logic input, while a common enable controls both channels. The L6203 is mounted in a 11-iead Multiwatt package. • TOTAL RMS CURRENT UP TO 4A • • RDs(oN) 0.3D. (TYPICAL VALUE AT 25°C) CROSS CONDUCTION PROTECTION • TTL COMPATIBLE DRIVE • OPERATING FREQUENCY UP TO 100KHz • THERMAL SHUTDOWN • INTERNAL LOGIC SUPPLY • HIGH EFFICIENCY (TYPICAL 90%) • 5A MAX PEAK CURRENT ~----------------------------~ The L6203 is a full bridge driver for motor control applications realized in Multipower-BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The DMOS output transistors can Multiwatt-ll ORDERING NUMBER: L6203 BLOCK DIAGRAM OUT! ENABLE 11 OUTI '---'>----__~- GND ~-9520 '*' Suggested value for September 1988 CBOOT1 and CBOOT2: 10nF 1/16 471 L6203 ABSOLUTE MAXIMUM RATINGS Power supply Differential output voltage (Between pins 1 and 3) Input or Enable voltage Pulsed output current (note 1) - non repetitive « 1 ms) Sensing voltage Boostrap peak voltage Total power dissipation (Tease = 90°C) (T amb = 70°C free air) Storage and junction temperature 52 60 -0.3 to 7 5 10 -1 to 4 60 20 2.3 -40 to 150 Notel: Pulse width limited only by junction temperature and the transient thermal impedance. CONNECTION DIAGRAM (Top view) I ENABLE I SENSE VREF I BOOU IN 2 GNO 4p:::::r::::==::::> ---...Jt=:===::;t~~I~~ -I "- ~ IN 1 BOOT.l OUT 1 Vs OUT 2 5-9514 Tab connected to pin 6 THERMAL DATA Thermal resistance junction-case Thermal resistance junction-ambient 472 max max 3 35 V V V A A V V W W °C L6203 PIN FUNCTIONS PIN NAME OUT2 2 FUNCTION Output of the half bridge. Supply voltage. 3 OUT1 Output of the half bridge. 4 BOOT1 A boostrap capacitor connected to this pin ensures efficient driving of the upper POWE R DMOS transistor at high switching frequencies. 5 IN1 Digital input from the motor controller. 6 GND Common ground terminal. 7 IN2 Digital input from the motor controller. 8 BOOT2 A boostrap capacitor connected to this pin ensures efficient driving of the upper POWER DMOS transistor at high switching frequencies. 9 V ref Internal voltage reference, a capacitor from this pin to GND increases stability of the POWER DMOS logic drive cricuit. 10 SENSE A resistance Rsense connected to this pin provides feedback for motor current control. 11 ENABLE When a logic high is present on this pin the DMOS POWE R transistors are enabled to be selectively driven by IN1 and IN2. -------------- ~ ~~~~m?1T~l~~©~ ____________ -=3'-'/1::.6 473 L6203 ELECTRICAL CHARACTERISTICS (Refer to the test circuits T j 25°C, Vs = 42V, unless otherwise stated) Parameter Vs Supply voltage V ref Reference voltage IREF Output current Is Quiescent supply current Test Conditions Min. 12 Typ. Max. Unit 36 48 V 13.5 V 2 EN = H EN = H EN = L V 1N = L V 1N = H Fig. 10 10 10 8 IL = 0 mA mA mA mA fe Commutation frequency (*) 30 Tj Thermal shutdown 150 100 KHz °C Td Dead time protection 100 ns TRANSISTORS OFF loss Leakage current Fig. 11 Vs = 52V 1 mA ON Ros On resistance VOS(ON) Drain source voltage V sens Sensi n9 voltage IDS = 3A 0.3 n 0.9 V 4 -1 V SOURCE DRAIN DIODE VSd Forward ON voltage trr Reverse recovery time tlr Forward recovery time EN = L Iso = 3A IF= 3A dif dt = 25A/!J,s 1,35(**) V 300 ns 200 ns LOGIC LEVELS V 1N L, V EN L I nput Low voltage -0.3 0.8 V V 1N H, V EN H Input High voltage 2 7 V -10 !J,A IINL, lEN L I nput Low current V 1N , V EN = L IINH' lEN H Input High current V 1N , V EN = H 30 !J,A LOGIC CONTROL TO POWER DRIVE TIMING tl (Vi) Source current turn-off delay Fig. 12 300 ns t2 (Vi) Source current fall time Fig. 12 200 ns t3 (Vi) Source current turn-on delay Fig. 12 400 ns t4 (Vi) Source current rise time Fig. 12 200 ns ts (VI) Sink current turn-off delay Fig.13 300 ns t6 (Vi) Sink current fall time Fig. 13 200 ns t7 (Vi) Sink current turn-on delay Fig. 13 400 ns ts (Vi) Sink current rise time Fig. 13 200 ns (*) Limited by power diSSipation (**) In synchronous rectification the drain-source voltage drops Vos is shown in Fig. 4. ~4/~1~6________________________ ~~~~~~~V~:~?~' 474 ___________________________ L6203 Fig. 2 - Quiescent current vs. freq uency Fig. 1 - Typical Is normalized vs. T J Fig. 3 - Typical Is normal· ized vs. Vs (;-6326 IS (rnA) 40 35 30 25 20 15 10 1.2 ...... 11 ............ 09 -- -1--- 06 7 I 06 Is (Norm)f~+--t--t-t--+--t---t--j-t--i 5 09 V 0.8 f--t--+---t-J-+--t--t--j-t--i 0.7 f--t--+---t-J--t--+---t----1I-+--I 0.6 f--t--t---t--j--t--+--t--jc-t--i 0.5 - ---+-+-+--1-+-+--+---t----1 v ./ 0.4 f-+-+-~---J,+-+-+---t-H o3 04 03 -25 +25 +50 +75 50 TJ ('C) 100 150 200 f (KHz) Fig. 4 Typical diode behaviour in synchronous rectification ISD" (A) V DS v"'. 0.2 0.4 Q6 0.8 1 12 5 10 15 20 25 30 35 40 45 IIs(V) Fig. 5 - Typical Ros vs.Vs=O:Vref (ON) G-6Jl' ROSON (Il) 1.6 1.6 14 1.2 1.0 0.6 0.6 0.4 0.2 II \ I 10 1.4 1.6 Vsd. Vos (V) lis 'VREF(V) Fig. 7 - RoS (ON) vs. DMOS transistor current Fig. 6 - Ros (ON) normalized at 25°C vs. temperature typical values 6-5313 ROSON (11) H-+++-H-t-t--t-t-H-++-1 .,r,l.Roson(Tj) 16 r-- ROS on (25°) 16 0.4H-+++-H-+-++HH-+-+t 1.4 12 ./ ./ O. 6 V /.. 0.3 H++-H-++-H-+++-i"9---I 0.2 H-+++H-+-++HH-++t V 0.1 H-+-++H-+-+++-H-+-+t o6 -50 -25 0 +25 -+50 '-75 -+100 TJ (OC) I (A) 5/16 475 L6203 Fig.S - Typical power dissipation vs. IL G I 26 -lIJ-v- v., INN 6325/2 Vs=36V L:lmH T :2ms 24 22 fs :IOOKHz <;20 - 20KHz 18 4 2 ":,'. ,~ )< 16 14 12 10 8 6 - - PHASE CHOPPING -'-'-ENABLE CHOPPING ):7 T, ./ ~ '/ . :~ /.V 'I' V k:V' ih v, i:/' .Ml~ 2 3 4 5 6 7 IL(A) Fig.8a - Two phase chopping Fig. 8b - One phase chopping ~6/~1~6________________________ ~~~~~~~~:~~~ 476 ___________________________ L6203 Fig. Bc - Enable chopping TEST CIRCUITS Fig. 9 - Saturation voltage a) Source outputs b)' Sink outputs Vs 51 A r~ _ 2 5 51 7 V 2 .L 11 L6203 3 B 5 r~ 7 V2 11 I Vl_ 1. A L6203 3 V1I 6 5- 9768 5-9767 ForlN1 source output saturation: VI = "H" SI = A V SL For I N2 source output saturation: V 1 =A I For IN1 sink output saturation: 2 = "H" = "H" SI = B SL = B I ___________________________ For IN2 sink output saturation: V = "H" 2 ~~~~~~g~:~~~~ VI = "H" SI = A V SL = A 2 I Vl ="L" = "H" S, = B SL = B IV 2 = "L" ________________________ ~7/~l~6 477 L6203 TEST CIRCUITS (continued) Fig. 11 - Leakage current Fig. 10 - Quiescent current Vs a) Source outputs 51 b) Sink outputs B rAlv J.. J:. 1 A 5L 11 52 .P B L6203 L6203 Iv J:.2 8~ 11 11 L6203 6-10 s- 9773/1 5-9772/1 SWITCHING TIMES Fig. 12 - Source current delay times VS. input chopper lmax;:: 3A 90'1, IN 517 3/1 10'1. L6203 EN 5V 11 Yin 50'1, 5-9770/1 Fig. 13 - Sink current delay times VS. 5-9807 input chopper Vs = 42 V Imax::: 3A 90'1, IN 5/7 10'1, L6203 3/1 EN 50'1, 6/10 5-9769/1 5- 9808 ~8/~1~6__________________~____ ~~~~~~~¥~:~~~ 478 ___________________________ L6203 CIRCUIT DESCRIPTION The L6203 is a monolithic full bridge switching motor driver realized in the new MultipowerBCD technology which allows the integration of multiple, isolated DMOS power transistors plus mixed CMOS/bipolar control circuits. In this way it has been possible to make all the control inputs TTL, CMOS and MC compatible and eliminate the necessity of external MaS drive components. the low-to-high transition a spike of the same polarity is generated by C2, preceded by a spike of the opposite polarity due to the charging of the input capacity of the lower POWER DMOS transistor. (Fig. 15) Fig. 15 - Current typical spikes on the sensing pin Vs ;41.V Ip=O.5A f=100ns LOGIC DRIVE INPUTS OUTPUT MOSFETS (*1 IN1 IN2 L H L H Sink 1, Sink 2 Sink 1, Source 2 Source 1, Sink 2 Source 1, Source 2 X All transistors turned OFF V EN =H L L H H V EN =L X L = Low H = High X = Don't care (*1 Members referred to INPUT 1 or INPUT2 controlled outputs stages lsense 5-9416/1 TRANSISTOR OPERATION ON STATE CROSS CONDUCTION Although the device guarantees the absence of cross-conduction, the presence of the intrinsic diodes in the POWER DMOS structure causes the generation of current spikes on the sensing terminals. This is due to charge-discharge phenomena in the capacitors C 1 & C2 associated with the drain source junctions (Fig. 14). When the output switches from high to low, a current spike is generated associated with the capacitor C1. On Fig. 14 - Intrinsic structures in the POWER MaS transistors (I When one of the POWER DMOS transistor is ON it can be considered as a resistor Ros (ON) (= O.3U) throughout the recommended operatingrange. In this condition the dissipated power is given by: PaN = ROS(ONI ·los2 The low Ros (ON) of the Multipower-BCD process can provide high currents with low power dissipation. OFF STATE When one of the POWE R DMOS transistor is OFF the Vos voltage is equal to the supply voltage and only the leakage current loss flows. The power dissipation during this period is given by: POFF = Vs • loss The power dissipation is in the order of pW and is negligible in comparison to that dissipated in the ON STATE. ~n TRANSITIONS s- 9415 ----------------------------- Like all MaS power transistors the DMOS POWE R transistors have as intrinsic diode between their source and drain that can operate as a fast freewheeling diode in switched mode ~~~~~~?v~:~~:f __________________________ 9~/l_6 479 L6203 applications. During recirculation with the ENABLE input high, the voltage drop across the transistor is RoS (ON) 10 and when the voltage reaches the diode voltage it is clamped to its characteristic. When the ENABLE input is low, the POWER MOS is OFF and the diode carries all of the recirculation current. The power dissipated in the transitional times in the cycle depends upon the voltage and current waveforms in the application. Ptrans. = los (t) " Vos (t) BOOSTRAP CAPACITORS To ensure that the POWER DMOS transistors are driven correctly gate source voltage o'f about 10V must be guaranteed for all of the N-channel DMOS transistors. This is no problem for the lower POWER DMOS transistors as their sources are refered to ground but a gate v.oltage greater than the supply voltage is necessary to drive the upper transistors. In the L6203this achieved by an internal charge pump circuit that guarantees correct DC drive in combination with the boostrap circuit charges the external C B capacitors when the source transistor is OFF and the sink transistor is ON giving lower commutation losses in switched mode operation. For efficient charging the value of the boostrap capacitor should be greater than the input capacitance of the power transistor which is around lnF. It is recommended that a capacitance of at least 10nF is used for the bootstrap. If a smaller capacitor is used there is a risk that the POWER transistors will not be fully turned on and they will show a higher Ros (ON)' On the other hand if a elevated value is used it is possible that a current spike may be produced in the sense resistor. REFERENCE To stabilise the internal drive circuit it is recommended that a capacitor be placed between this pin and ground. A value of 0.22JlF should be sufficient for most applications. This pin is also protected against a short circuit to ground. DEAD TIME To protect the device against simultaneous conduction in both arms of the bridge and the resulting rail to rail short, the logic control circuit provides a dead time greater than 40ns. THERMAL PROTECTION A thermal protection circuit has been included that will disable the device if the junction temperature e reaches 150°C. When the temperature has fallen to a safe level the device restarts under the control of the input and enable signals. APPLICATION INFORMATION RECIRCULATION During recirculation with the ENABLE input high, the voltage drop across the transistor is Ros (ON) 'I L for voltages less than 0.7V and is clamped at a voltage depending on the characteristics of the source-drain diode for greater voltages. Although the device is protected against cross conduction, current spikes can appear on the current sense pin due to charge/discharge phenomena in the intrinsic source drain·capacitances. 1n the application th is does not cause any problems because the voltage created across the sense resistor is usually much less than the peak value, although a small RC filter can be added if necessary. POWER DISSIPATION In order to achieve the high performance provided by the L6203 some attention must be paid to ensure that it has an adequate PCB area to dissipate the heat. The first stage of any thermal design is to calculate the dissipated power in the application, for this example the half step operation shown in figure 16 is considered. RISE TIME Tr When an arm of the half bridge is turned on current begins to flow in the inductive load until the maximum current IL is reached after a time Tr . The dissipated energy EOFF/ON is in this case: EOFF/ON ~102/~16~______________________ ~~~~~~?~~~~~~ 480 = [ROS(ON) " IL2 "Trl" 2/3 ________ _________________ ~ L6203 ON TIME TON Fig. 16 During this time the energy dissipated is due to the ON resistance of the transistors EON and the commutation E COM ' As two of the POWE R DMOS transistors are ON EON is given by: EON = IL2 . RDS(ON) ,2, TON In the commutation the energy dissipated is: IT, I Ton I Tf i T d 5- 9775 Where: TCOM = Commutation Time and it is assumed that; TCOM = TTURN-ON = TTURN-OFF = 100ns fSWITCH = Chopper frequency FALL TIME T f For this example it is assumed that the energy dissipated in this part of the cycle takes the same form as that shown for the rise time: EON/OFF = [ROS(ON) ·I L2 • Ttl· 2/3 QUIESCENT ENERGY The last contribution to the energy dissipation is due to the quiescent slJPply current and is given by: EQUIESCENT = IQUIESCENT • Vs • T TOTAL ENERGY PER CYCLE ETOT = EOFF/ON + EON + ECOM + + EON/OFF + EQUIESCENT The Total Power Dissipation PDIS is simply: T, TON Tf Td T Rise time ON time Fall time Dead time Period T = T,+T oN +Tf+T d DC MOTOR SPEED CONTROL Since the L6203 integrates a full H-Bridge in a single package it si idealy suited for controlling small DC motors. When used for DC motor control the L6203 provides the power stage required for both speed and direction control. The L6203 can be combined with a current regulator like the L6506 to implement a transconductance amplifier for speed control, as shown in figure 17. In this configuration the L6506 sense the voltage across the sense resistor, RSENSE, to monitor the motor current. The L6506 then compares the sensed voltage to control the speed or during the input signals to the L6203. Between the sense resistor and each sense input of the L6506 a resistor must be foreseen; if the connections between the outputs of the L6506 and the inputs of the L6202 need a long path, a resistor must be connected between each input of the L6202 and ground. A snubber network made by the series of Rand C must be foreseen very near to the outputs pins of the L6203. The following formulas can be used: R ~ Vs/lp C = Ipi (dv/dt) where Vs is the max supply voltage foreseen on the application; Ip is the peak of the load current; dv/dt is the needed rise time of the output voltage (200V Ipsec is generally used). A diode (BYW98) is connected between each power output pin and ground as well. If the power supply cannot sink current, a suitable large capacitance must be used and connected near the supply pin of the L6202. Sometimes a capacitor at pin 17 of the L6506 let application better work. -------------- ~ ~~I;m~1r~:~~~ ___________ ----'1:.:;1;....:/1;..:,6 481 L6203 Fig. 17 - Bidirectional DC motor control Ucc.5U ..-I 22KO DIRECTION { 6 Uspeed.2lJmax IIp max.4A) 16 Ref I 4 ENABLE ION/OFF) 2 Ucc.5U :::c RI 2.2K L65G6 14 5 12 11 13 7 IN I 3 EN 3 18 R4 17 15 Ref 2 3. 3nF IN 2 L62G3 18K R3 18 lBK RS 15nF 02 B.50 1188L6283-8611 BIPOLAR STEPPER MOTORS APPLICATIONS Bipolar stepper motors can be driven with an L297 or L6506, two L6203 bridge BCD drivers and very few external components. Together these three chips form a complete microprocessor-to-stepper motor interface. As shown in Fig. 18 and Fig. 19, the controller connect directly to the two bridge BCD drivers. External component requirements are minimal: an RC network to set the chopper frequency, a resistive divider to establish the comparator reference voltage (pin 15 for L297, pin 10 and 15 for L6506) and a snubber network made by Rand C in series. The following formulas can be used: R "" Vs/lp C = Ip/(dv/dt) where Vs is the max. Supply Voltage foreseen on the application; Ip is the peak of the load current; dv/dt is the needed rise time of the output voltage (200V/lls is generally used). Depending on the Printed Circuit Board design, a resistor between each input of the L6203 and ground could be requested. These solutions have a very high efficiency because of low power dissipation. HIGH CURRENT MICROSTEP DRIVE FOR STEPPER MOTORS The L6203 can be used in conjunction with the L6217 to (figure 20) implement a high current microstepping controller for stepper motors. ;:,.12::.,/.:,.16'--_ _ _ _ _ _ _ _ _ _ _ 482 In this application the L6217 is used as a control circuit and its outputs are used only to drive the inputs of the L6203. The application allows easy interface to a microprocessor since the L6217 may be connected directly to the microprocessor bus. In the circuit shown in Figure 20, the L6217 senses the motor current by monitoring the voltage across the sense resistors, RSENSE, and compares this value to the output of a 6 bit (7 bit if the L6217A is used) D to A Converter. The L6217 controls the current using a frequency modulated, constant off time, switching controller. The off time of each coil may be set using and external resistor and capacitor connected to PTA and PTB. In this configuration the microprocessor simply loads the appropriate value for the direction of current floW through the coil and the data for the DAC into the L6217. The L6217 and L6203 then forms the complete interface between the micro and the motor. When the pins 3 and 4 of the L6217 (Test A and B) are low, the bridges must be in tri-state condition. For this reason two LM339 comparators must be used. The outputs of the comparators act on the enable inputs of the L6203 ICs. A bi level operation can be used for decreasing the minimum controllable load current. The mi- iIfi. ~~~~m?1Jrtf~~©' -------------- L62(J nimum current that can be controlled is given by the following expression IL (avg.) = Rsense' (2Ros o n + RLoAo)/DC where R LOAO is the equivalent resistance of the load DC is the duty cycle given by If 12V is forced on pin (Reference voltage) ar the supply voltage V 5 is reduced below 12V tl on resistance tends to increase above the norm guaranteed 0.30hm. Consequently the minimum current will also I reduced, as given in the above expression. Wher mi nimum current operation is required, a high gnal at point (A) can disable the pnp transistc in fig. 20. So it's possible to operate at a Vs (7V - Vsd. Fig. 18 - Two phase Bipolar stepper motor control circuit with chopper current control 5U IN RESET 1~~----~====$[~______~ R L62G3 c: IN 2~~----t=====$[~------~ L62G3 ; ! 22K I I ,~ 22K f188L62B3-B2f1 SENSE I"~ RESISTOR,' l.;;.i~ I~' /i" !~' lil /.,'" I:", i' ,;',': -------------- ~ ~~~~mg1f~:~~~~ __________i{ /.::' 6203 g. 19 - Two phase Bipolar stepper motor control circuit with chopper current control and translator 8.~ 51) 8~1-+-_--' ...-;---. A CW/CCW STEP ILF IFULL RESET B R L62G3 C INHI TROL 15V I OUTPUT LOGIC ENABLE C L62G3 R C SYNC .5V 22K 22K SENSE RESISTORS gh current microstepping controller for stepper motors OUT a .luF 121) I B.luF BY\J9B-5B L6217 lK D176 I IAI 31 I----~-_I 3B I---~-+-_I lN4148 .71) ff88L6283-B4f1 B.luF L62( THERMAL CHARACTERISTICS Fig. 21 - Rth j-amb of Multiwatt package vs. dissipated power tree air mount d die 5~ze: 0,800 0,S0 1.00 1.513 r~d HM 70- 3 hea 5 ink q,mil dissi10Ung area = 2.0138 sCl.mi 0.00 DM ed on PCB ba 2.013 2.50 5 3.00 3.50 4.!10 4.50 5.00 DISSIPATED POI...ER ( LJatt. ) Fig. 22 - Comparison of transient Rth for single pulses with and without heatsink /SINe LE // P.JLSE V b Pd / 0 /'" V ~' mounled ~~ free air Pd 0 2 W THM 7B23 ~eal:. 5 W 5 ink (*) V e.1 O.eel B.B1 B.1 18 TII"£ OR PULSE WIDTH ( 5 ) -------------- ~ ~~~~m?1r~~~ 1BBB 5203 g. 23 - Peak transient Rth vs. pulse width and duty cycle ~f-- DC ~- I----i--- f- __-r j.-----r 10 f~ p j--- I-----r cD 'CLE -- ~I 10 0. I TIME OR PULSE WIDTH !~T~ 100 ( " S a -- 1000 ms 1 --- iifi. ~~~~m~1iT~lf -------------- L6210 DUAL SCHOTTKY DIODE BRIDGE • MONOLITHIC ARRAY SCHOTTKY DIODES • HIGH EFFICIENCY OF EIGHT The L6210 is available in a 16 Pin Powerdip Package (12+2+2) designed for the 0 to 70°C ambient temperature range. • 4A PEAK CURRENT • LOW FORWARD VOLTAGE • FAST RECOVERY TIME due to low forward voltage drop and fast reverse recovery time, are required. • TWO SEPARATED DIODE BRIDGES The L6210 is a monolithic IC containing eight Schottky diodes arranged as two separated diode bridges. Powerdip 12+2+2 This diodes connection makes this device versatile in many applications. They are used particular in bipolar stepper motor applications, where high efficient operation, ORDERING NUMBER: L6210 ABSOLUTE MAXIMUM RATINGS Repetitive forward current peak Peak reverse voltage (per diode) Operating ambient temperature Storage temperature range 2 50 70 -55 to 150 BLOCK DIAGRAM 1,8 16,9 3,6 11.14 S-9JZO/l 4,5,12,13 September 1988 1/3 - 487 L6210 THERMAL DATA Rthj-case Rthj-arnb Thermal impedance junction-case Thermal impedance junction-ambient without external heatsink max max 14 65 CONNECTION DIAGRAM (Top view) K 16 ~ K OUT 1 2 15 ~ OUT 4 A 3 14 ~ GNO 4 13 GNO GNO 5 12 GNO A G 11 A OUTZ 7 10 OUT 3 I8 9 K K A ~-9311 ELECTRICAL CHARACTERISTICS (TJ Paramater Vf Forward voltage drop 25°C unless otherwise specified) Test Conditions Min. Typ. Max. I f = 100mA 0.65 O.S If = 500mA O.S 1 1 1.2 If = lA IL Leakage current VR = 40V Tarnb = 25°C 1 Unit V mA NOTE: At forward currents of greater than lA, a parasitic current of approximately lOrnA may be collected by adiacent diodes. ~2/~3____________------------~~~~~~~©~ 488 __________________________ L6210 Fig. 1 - Reverse current vs. voltage I "Ai 'R ~j!~~~~~~~I~ Tj ~1l5'C Fig. 2 - Forward voltage vs. current (;·606' Id IA I /.~ ~ TJ =125'C Tj =,s·c Ij",5'C'1/ I- Yl'l Tj"Z5*C H-t 10 '0 01 .0 50 0.2 ~(V, 0,4 0.6 0.8 MOUNTING INSTRUCTIONS The Rthi-amb of the L6210 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board as shown in figure 3 or to an external heatsink (Figure 4). During soldering the pin temperature must not exceed 260°C and the soldering time must not be longer then 12s. The external heatsink or printed circuit copper area must be connected to electrical ground. Fig. 3 - Example of P.C. board copper area which is used as heatsink Fig. 4 - Example of an external heatsink p.e.BOARD ___________________________ ~~~~~~~~~:~~©~ ________________________ ~3/~3 489 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L6212 HIGH CURRENT SOLENOID DRIVER PRELIMINARY DATA • HIGH VOLTAGE OPERATION (UP TO 50 V) • HIGH OUTPUT CURRENT CAPABILITY (UP T06A) • LOW SATURATION VOLTAGE • TTL-COMPATIBLE INPUT • OUTPUT SHORT CIRCUIT PROTECTION (TO GROUND, TO SUPPLY AND ACROSS THE LOAD) • THERMAL SHUTDOWN • OVERDRIVING PROTECTION • LATCHED DIAGNOSTIC OUTPUT switch-mode operation. An extra feature of the L6212 is a latched diagnostic output which indicates when the output is short circuit. The L6212 is supplied in an 15-lead Multiwatt plastic power package. Multiwatt-15 (Horizontal) DESCRIPTION The L6212 is a monolithic switch-mode solenoid driver designed for fast, high-current applications such as hammer driving in printers and electronic typewriters. Power dissipation is reduced by efficient ORDER CODE: L6212 CONNECTION DIAGRAM (top view) ~I i CD L . -" SINK OUTPUT CURRENT SENSING AMPLIFIER INPUT ENABLE N.C. TIMING INPUT VOLTAGE GND DIAGNOSTIC OUTPUT DIAGNOSTIC SUPPLY VOLTAGE N.C. ON TIME LIMITER N.C. SOURCE OUTPUT POWER SUPPLY VOLTAGE S-9301 Tab connected to pin 8 September 1988 1/6 491 L6212 BLOCK DIAGRAM DlAG. OUi +VSS +VS 01 2 OUTH ,-__-tJ~OAO 01 OUT l Cl Rl 5-9300 ABSOLUTE MAXIMUM RATINGS ~~-------------- Parameter f I Vs Power Supply Voltage Vss~~i~Supply Voltage . -------- ~_Enable V()lt~~ _ _ VI Ip L l ~lot ----,---- Input Voltage Peak Output Current-(repetiti;~)---------Total_F'0wer_ Dissipation (at T case i__~~t~!~o~(1e Value Unit 50 V 7 V 7 V 7 V 6.5 A ------------+-----j 25 = 75°C) 1- - 40 to + 150 and Junction Temperature W °C THERMAL DATA Thermal Resistance Junction-case Themal Resistance Junction-ambient Max Max ----------------------------~ 2/6 492 -::---,_~g;~-l ------- L6212 ELECTRICAL CHARACTERISTICS (refer to the test circuit, Vs unless otherwise specified) 1- Symbol Parameter = 37 V, Vss = 5 V, Tamb = 25 Test Conditions Vs Power Supply Voltage (pin 1) Id Quiescent Drain Current Min. Typ. 20 I Vi:> Logic Supply Voltage (pin 6) Iss Quiescent Logic Supply Current : VOIAG = L , DIAG Output at High r~p~;~~~:eOut-p~t I Non-operative Input Current (Pin 9) VENABLE ~BL-;- -En-able Input Current _""-,,tH - Source OutpU! ~aturatl()n I _\ICJ1t__ - V 5 8 rnA 10 100 flA 0.6 V V > 06 V H + VSa1 L Total Saturation Voltage --.----------- - ---- -0.3 2.4 ~9Nh ~:v~ V, = 08-V VEN=H Ve=24V IE~_~ A ___ loul = 5.5 A ------- _ _ __ ~----.----- : ""'~"""fo$~~::;::C;;:,::;:;,n ~~:f'v --=I V01AG I Diagnostic Saturation Voltage (PIn7) ~ f~~;~~st'c IOIAG Vpon 10 I ~Vpon 10 , Leakage Current OP AMP DC Voltage G-;;';--- - VOIAG = 40 V ,;~ flA flA 0.8 V -100 100 flA 2.5 V 2.5 V :bA ~o:==_2_-_1_~ 2 rnA ,loiAG = 10 rnA , Vpin V -2 -5 ____ ,! __________ ~~5---~I Output Leakage Current Source V s = 45 V PNP , Vi ,; 0.45 V Ileakage 0.45 - 045 Low Level Vsal 1,_ _ _ ~i~~_O_utput _~atlJl"_at_ion_V_o_lt_._--+_I",OU__I_= 5.5~__~ ______ _ Vsal rnA 7 Output ~~ ~ ~ Enable Input Current (Pin 12) V 30 rnA 4.5 Input Voltage (pin 9) __ "--5--! 04 V 10 fl A 100 t;800 mV --------~---------------~---~ , ! Ip'n_'_~_"" 1 rnA ______ ~5__ L__ Ipin10 + Vpin10=4VV g =V 13 =0, V pin 10 = 2 V V,3 = 0.9 V Isense Input Bias Current (pin 13) Vsense Sensing Voltage (pin 14) (H) Unit 46 70 VEN = L 0.6 V Vss Vi Max. 12 VEN = H °e, I ,! I V 10 1.5 -1 flA mA flA 0.9 V n After a lime interval tm" = KC" the output stages are disabled. (**) Allowed range of Vsense without the intervention of the short circuit protection. 3/6 493 L6212 Figure 1 : Output Current Waveforms, t1 t3 t5 Vif-_+_ _ _-"t"""-'t.....""!-_ __ V pin4 5-5365 b) a) Figure 2 : Test and Typical Application Circuit. Vi ENABLE ""l.....r r C2 47nF 5-9572 g~ ~~ :::: ~:~~: 4/6 494 } trr QOOns L6212 CIRCUIT OPERATION The L6212 works as a transconductance amplifier: it can supply an output current directly proportional to an input voltage level (Vi). Furthermore, it allows complete switching control of the output current waveform (see Fig. 1). The following explanation refers to the Block Diagram, to Fig. 1 and to the typical application circuit of Fig. 2. The ton time is fixed by the width of the Enable input signal (TTL compatible) : it is active low and enables the output stages "source" and "sink". At the end of ton, the load current haad recirculates through 01 and 02, allowing fast current turn-off. The rise time tr depends on the load characteristics, on VI and on the supply voltage value (Vs, pin 1). During the ton time haad is converter into a voltage signal by means of the external sensing resistance Rs connected to pin 13. This signal, amplified by the op amp charges the external RC network at pin 10 (R1, C1). The voltage at this pin is sensed by the Inverting input of a comparator. The voltage on the non-inverting input of this one is fixed by the external voltage Vi (pin 9). After, tr, the comparator switches and the output stage "source" is switched off. The comparator output is confirmed by the voltage on the non-Inverting input, which decreases of a constant fraction of Vi (1/10), allowing hysteresis operation. The current In the load now flows through 02. Two cases are possible: the time constant of the recirculation phase is higher than R1, C1 ; the time constant is lower than R1, C1. In the first case, the voltage sended on the non-inverting input of the comparator is just the value proportional to haad. In the second case, when the current decreases too quickly, the comparator senses the voltage signal stored in the R1 , C1 network. In the first case t1 depends on the load characteristics, while in the second case it depends only on the value of R1, C1. In the other word, R1, C1 fixed the minimum value of t1 (t1 ::> 1/10 R1 x C1. Note that C1 should be chosen in the range 2.7 to 10 nF for stability reasons of the op amp). After t1, the comparator switches again: the output is confirmed by the voltage on the non-inverting input, which reaches Vi again (hysteresis). Now the cycle starts again: t2, t4 and IE; have the same characteristics as tr, while 13 and ts are similar to t1. The peak current Ip depends on Vi as shown in the typical transfer function of Fig. 3. It can be seen that for Vi lower than 450 mV the device is not operating. For Vi included between 450 and 600 mV, the operation is not guaranteed. The other parts of the device have protection and diagnostic functions. At pin 4 is connected an external capacitor C2, charged at constant current when the Enable is low. After time interval equal to K· C1 (K is defined in the table of Electrical Characteristics and has the dimensions of £2) the output stages are switched off independently by the Input signal. This avoids the load being driven in construction for an excessive period of time (overdriving protection). The action of this protection is shown in Fig. 1b. Note that the voltage ramp at pin 4 starts whenever the Enable signal becomes active (low state), regardless of the Input signal. To reset pin 4 and to restore the normal conditions, pin 12 must return high. This protection can be disabled by grounding pin 4. In order to keep constant the energy delivered to the load, when the supply voltage changes, it's possible to modify the output maximum peak current (Ip) by means the external voltage divider R2 and R3 which "senses" the supply Voltage. Ip is given by : Vi (Rs + R2 + R3) - 5 Vs (R2 + Rs) Ip = 5 R3 Rs so the variation of Ip versus Vs is : tl.1 = _ R2 + Rs p R3 Rs The thermal protection included in the L6212 has hysteresis. It switches off the output stages whenever the junction temperature increases too much. After a fall of about 20°C, the circuit starts again. Finally, the device is protected against any type of short circuit at the outputs: to ground, to supply and across the load. When the source stage current is higher than 7A andlor when the pin 13 voltage is higher then 1 V (i.e. for a sink current greater than 1 V/Rs) the output stages are switched off and the deVice IS inhibited. This condition is indicated at the open-collector output DIAG (pin 7) ; intemal flip-flop FIF changes and forces the output transistor into saturation. The FIF 5/6 495 L6212 must be supplied independently through Vss (pin 6). The DIAG signal is reset and the output stages made operative by switching off the supply voltage at pin 1 and then by switching the device on again. After that, two cases are possible : the reason for the "bad operation" is till present and the protection acts again; the reason has been removed and the device starts to work properly. Figure 3 : Peak Output Current vs. Input Voltage. Figure 4: Peak Output Current vs. Input Voltage. G Ip Ip CAl (AJ ~ -- R2=O R3=OPEN RsO' O.13Jl. 6192 ! - -- ~bV I R2= 100 .n.. R30::33Kll. RS= 0.13.0.. / 1 //1 I /' V ) / V /,'" V ./ L /' V 0.511.522.533,54 Vi('.') Figure 5 : Peak Output Current vs. Supply Voltage. IP r--,-,--r---,--r----,--"'~'--, CAl VI = 3.5'0' R2 =100 n 6 ~ ~~~6~,~~ r----+-+--f.-+---j 5.5 f--+-+--f--+-r.-f--i----4 • .5 f---+-+--f---t--'f'-......._c:---i----4 3.5 -- .- - -I---r--- r--- - -. -j---t--~---I--1 i 10 6/6 496 15 20 25 30 35 40 Vs(V) 0.5 i 1.5 2 2.5 3 3.5 4 Vi (V) L6217 STEPPER MOTOR DRIVER • • • • • MICROSTEPPING BIPOLAR OUTPUT CURRENT UP TO 400 mA LOW SATURATION VOLTAGE BUILT-IN FAST RECOVERY DIODES OUTPUT CURRENT DIGITALLY PROGRAMMABLE • 6 BIT D/A CONVERTERS SET OUTPUT CURRENT • THERMAL SHUTDOWN for micro-stepping the motor current is internally sensed and compared to the output of the D/A converter. A monostable, programmed by an RC network sets th.e motor current decay time. The L6217 is supplied in a 44 pin PLCC with 11 of the 44 pins used for heatsinking. ,------------_.- -----------, DESCRIPTION The L6217 is a monolithic IC that controls and drives both phases of a Bipolar Stepper Motor with PWM control of the phase current. The output current level of each phase is programmed by a 6 bit D/A converter so that the device may be used in full-step, half-step and micro-step applications. The inputs for the DIA converters and the phase inputs to select the direction of current flow are latched to minimize the interface to a microprocessor. The power section of the device is a dual H-Bridge drive with internal clamp diodes for current recirculation. To maintain the degree of accuracy required PIN CONNECTION PLCC 44 (Plastic Chip-Carrier) L- - - - - - ORDER CODE: L6217 (top view) :£-' 1>- 1m I~ 1>a:4:ut/lut!) 0f ) t V'!lf)--( 6 5 4 0 UlZ 3 DO 01 MRSToL 02 PTA 03 04 VSB 05 (MSB) VSA PH VSP (+16) olGF OUT A2 OUTBl OUT B2 RSB RSA 18 19 GNo September 1988 5-9266 1/7 497 L6217 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value I V si Logic Supply Voltage 7 Vsp Motor Supply Voltage 18 Unit ---"'"- V ---~ V -~-- Logic Input Voltage VI 6 -- V ---~ Reference Input Voltage Vref Vsi ----_. 10 Output Peak Current Tj Operating Junction Temperature I Storage Temperature T stg V ----- - - 500 I mA 150 "C - 55 to + 150 °C BLOCK DIAGRAM ,--~----------------------~~----------- PH M B 0' 03 m ~ 14 " 34 04 ie! 02 3' l 3. T C H 37 E A 5 ~ 0 01 l B OIGF PTA TESTA B OUTPUT A 1 ~ 17 F E R 5 J8 DO r ~~~==f=:::l. ______-'==:::'::~';:'::~GNOOl , 8---"-0---L l A T C H E 5 ptNS) --~VREf IN R. , OUT B U F F E •5 681T DIA .STo-~l----------~--~ ~-------~------~----~-------------------------- THERMAL DATA Thermal Impedance Junction-Case ~,--,-~-,-,_T_h_e_rm_a_I_lmpedance Junction-Ambient 2/7 498 ~ __ Max_ Max_ ~~L- __ ~ __ 10 80__ ~ ----------~- L6217 PIN FUNCTION DESCRIPTION r~o ~I-------~ I I 38,39 44 I I Name --- Function R;t Active low input resets the D/A latches to 0 and disables the output. DO - 05 Data inputs for the D/A converter (DO = LSB). For a data input of 00, the corresponding outputs are held in the off , state. AlB Channel select for input data. Pin AlB selects channel A when high. PH Logic input selects direction of current flow in output bridge from A 1 (B 1) to A2 (B2) for PH = 1. Strobe MRST DL MRST - --- ---- Active low input latches input data (00-05 and PH) into input latch. The capacitor on this pin programs the power on reset delay according to the formula: T DR = (0.35) (C) 10 6 Power-on reset circuit output. (micro reset signal). This output remains low from power on until the delay capacitor has charged past the delay threshold. 10 PtA Pulse time A, an external parallel RC network tied to ground defines T ott time for channel A. ( T ott = 0.69 R2C2). 11 PtB Pulse time B, an external parallel RC network tied to ground defines toll time for channel B. (T off = 0.69 R3C3). 5 Vref In 18t~28T 40 Voltage applied to this point sets the reference for the D/A converter and threfore sets the maximum output current. (see equation 1, next two pages). - - - - - - - - - - - - - - - - - - - - - - - - - - ------- ------------------- Gnd Gnd 0 Pin must be- -connected to ground. ------ --- Logic Supply Voltage ~sp ------ Ground connection and also conducts heat to the P.C. board. ------I- - - - - - - - - I -- - ------ -- Motor Supply Voltage ------- 16,15 l o u t A1 - A2 31,30 B1 - B2 H - Bridge outputs. 43,41 CSO, CS1 Chip select inputs CSO is active high, CS1 is active low. ::7':2:91 13,12 RsA - RsB VsA - VsB Sense resistor from this pin to ground set the peak output current. I Analog inputs for sensing motor current, separate inputs are provides to allow filtering of the sense voltage if required. -------- 1-~~4-L- T~r~~o~t B I~"I-D~~ - ----- ---- ----------- ------ --- These pins are for testing of D/A outputs. Vj"~~d~p--;-e~erenc~ - - - - - - - - - - - - - - - - - _25 -_=l Reset Threshold Voltage Can be used to modify the internal comparator lockout time. In microstepping typical application a 1.8 KQ resistor must be connected between this pin and ground. 3/7 499 L6217 ELECTRICAL CHARACTERISTICS Symbol 01 cc = 5.0 V, Parameter Tj = 25 'C unless Test Conditions otherwise specified noted) . Min. Typ. Max. Unit Vsp Motor Supply Voltage 8 16 V Vsi Logic Supply Voltage 4.75 5.25 V 0.8 V LOGIC INPUTS (DO-D6, CSO, CS1, PH, RST and NB) VIL Input Low Voltage VIH Input High Voltage IlL Input Low Current IIH Input High Current 2 VSi V VI = 0.4 V - 400 ~ VI = 2.4 V 10 ~ CURRENT CONTROL AND D TO A SECTION Vref Reference Voltage 2.55 V Vrin Reference Input Range 2.0 3.0 V Monotonicity of D to A - 0.5 + 0.5 LSB -1 + 1 LSB 277 mA 5 % 36 IlS 100 ~ Vec = 5.0 V Linearity of D to A lop Peak Output Current (gain of current loop) Vref = 2.40 V Rsense = 2 g Data = 7 F (Hex) 10 Output Matching Vref = 2.38 V 2.45 225 2.50 252 MONOSTABLE Toff Cutoff Time Td Turn-off Delay loff Output Leakage Current Rt = 56 Kg Ct = 820 pF 28 1 Data = 00 (Hex) Ils RESET CIRCUITRY Vth Reset Threshold Voltage 3.9 4.1 Reset Threshold Hysteresis 70 100 10 14 3.25 3.5 3.75 70 100 Iso Delay Capacitor Charging Current Ve = 2.5 V 7 lsi Delay Capacitor Discharge Current Vc = 2.5 V 10 Vdth Vdhys 101 V sat 4/7 500 Delay Threshold Voltage Hysteresis Voltage on Delay Threshold 4.3 V mV ~ mA V mV Output Leakage Current Vo =5 V 200 Output Saturation of Reset Out 10 = 2 mA 0.4 ~ V L6217 ELECTRICAL CHARACTERISTICS (continued) I Symbol Parameter I Test Conditions I Min. I Typ. I Max. Unit SOURCE DIODE - TRANSISTOR PAIRS Saturation Voltage 10 = 400 mA Diode Forward Voltage 10 = 400 mA SINK DIODE - TRANSISTOR PAIRS Saturation Voltage 10 = 400 mA Diode Forward Voltage 10 = 400 mA AC CHARACTERISTICS TsOI(ST) ThOI(ST) TwPI TeST 01 to Strobe t Setup Time 100 ns 01 to Strobe J, Hold Time 500 ns Pulse Width Low 600 ns Strobe Setup Time 2.5 JlS AlB to Strobe J, Setup Time 100 ns TsPH(ST) PH to Strobe J, Setup Time 100 ns T~B(ST) CIRCUIT OPERATION The current control section of the L6217 A is a pulse width modulated control that senses the motor current. When the motor current reaches the peak programmed current the comparator will trigger the monostable turning off the upper transistors. After the toff time equal to 0.69 RC the upper drivers are enabled again. The peak current is given by the equation: Vref 0 lop = 4.69.Rsense 64 o = Input data (0 - 63) When the input data is 00, the ouptut stages are disabled by internal logic so that the output current decays rapidly to zero. An internal generated lockout time avoids the use of an external RC network between the sensing resistor (RsA, RsB) and the corresponding input (VsA, VsB), by disabling the comparator sensing during the lockout time. This time is typically 2.5/1s. 5/7 501 L6217 Figure 1 : Microstepping (typical application). ----- r - - - - - - _ -- - _ l~RsT -= ~~:~~ ~ __ cso ~ STROBE C51 N.C GNDO DO 39 L----------48 .----------49 D1 D2 38 ----37 36 35"------ .-------110 11 03 04 05 PH 561UJ.. t;;'\ { 2.SmH 20nTypV ~ $·9165,1 ----------.- ---- --- - - - - - - - - - - - - -....-~ Figure 2 : Microcomputer Interface Timing. I DATA ~ 1 > (; T h D 1(5 T)I ~-------+< ---- ~ STROOE CS1 T sDJ(ST~ I :r TwPl ~ ~ eso 1 I AlB '" =x-:-~---., 1 '1 6/7 502 j' ~ ------------- TsAlB(ST) 1 ----~-1-- \ TeST -.---- .1 u - Ts PH (ST) - - - - - - - - - - - S-10GGS - - - - L6217 Figure 3 : Td, Toft and .1 I Tlock out I· T\ockout .. I 5 - 10666 ~--------------------~~--~--------~~~---------" Figure 4 : Reset Waveforms. ----------------------.----- .. ---~---.-------- VS1 min Vth Hmax Vt h H --..;.;..;.;;..;.......;.....--'--_ _...,..~~:..:_:.:..t;;.;;;::.:.;;;:.._~~-- Vt h Hmin I RESET OUT s- 9268/1 7/7 503 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I ~ SGS-ntOMSON .,.., I ~O©~@~[lJ~~u~@[RI]O©~ L6217A STEPPER MOTOR DRIVER The power section of the device is a dual H-Bridge drive with internal clamp diodes for current circulation. To maintain the degree of accuracy required for microprostepping, the motor current is internally sensed and compared to the output of the D/A converter. • • • • • MICROSTEPPING BIPOLAR OUTPUT CURRENT UP TO 400 mA LOW SATURATION VOLTAGE BUILT-IN FAST RECOVERY DIODES OUTPUT CURRENT DIGITALLY PROGRAMMABLE • 7 BIT D/A CONVERTERS SET OUTPUT CURRENT • THERMAL SHUTDOWN A monostable, programmed by and RC network sets the motor current decay time. The L6217 A is supplied in a 44 pin in PLCC with 11 of the 44 pins used for heatsinking. DESCRIPTION The L6217 A is a monolithic IC that controls and drivers both phases of a Bipolar Stepper Motor with PWM control of the phase current. The output current level of each phase is programmed by a 7 bit 01 A converter so that the device may be used in fullstep, half-step and micro-step applications. The inputs for the 01 A converters and the phase inputs to select the direction of current flow are latched to minimize the interface to a microprocessor. PLCC 44 (plastic Chip-Carrier) ORDERING NUMBER: L6217A CONNECTION DIAGRAM (top view) 2 1 "43 42 41 D1 7 MRSTDL 8 02 9 D3 PTA 10 DI. PTB 11 05 VSB 12 06 (MSB) VSA 13 PH VSp (+16) DIGF OUT A2 OUTBl OUT A 1 OUT 82 RSA RSB GND September 1988 S 9272 1/8 505 L6217A ABSOLUTE MAXIMUM RATINGS Value Unit V sj Logic Supply Voltage 7 V Vsp Motor Supply Voltage 18 V Logic Input Voltage 6 V Symbol Parameter V, Vret 10 Reference Input Voltage Vsi V Ouptut Peak Current 500 mA 150 °C - 55 to + 15 °C Operating Junction Temperature Tj Storage Temperature Tstg BLOCK DIAGRAM PTA TEST A PH B D. D. .. ~ ;; 04 03 0 02 OIGF 34 J5 3. OUTPUT H-BRIOGE 1 L A T e H 37 OUTPUT A' 14 33 E 5 8 U OUTPUT A2 F F E R 5 31 01 GND(llP1NSJ STROBE rREF IN --J ~: e50 VREF A/8 VREF OUT V5P L A T e H E 8 U F F E R 339TVP[ 781T D/A COMPARATOR 5 5 5-926"1 iiS1' THERMAL DATA Thermal Impedance Junction-case Thermal Impedanc!3 Junction-ambient 2/8 506 Max Max 10 80 L6217A PIN FUNCTION DESCRIPTION N° 1 Function Name Active low input resets the D/A latches to 0 and disables the output. 40, 34 R s' DO-D6 44 AlB Channel select for input data. Pin AlB selects channel A when high. 33 PH Logic input selects direction of current flow in output bridge from A1 (B1) to A2 (B2) for PH = 1. Data inputs for the D/A converter. (DO = LSB) For a data input of 00, the corresponding outputs are held in the off state. 42 Strobe 9 MRST DL 8 MRST 10 P,A Pulse time A, an external parallel RC network tied to ground defines toll time for channel A (Toll = 0.69 RC). 11 P,B Pulse time B, an external parallel RC network tied to ground defines i oll time for channel B. (Toll = 0.69 RC). 5 Vref in 18 to 28 Gnd 2 Vsi 32 Vsp 16, 15 31,30 Out A1-A2 B1-B2 H-Bridge Outputs. 43,41 CSO, CS1 Chip select inputs CSO is active high, CS1 is active low. 17,29 RsA - RsB Sense resistor from this pin to ground set the peak output current. 13,12 VsA - VsB Analog inputs for sensing the motor current, separate inputs are provides to allow filtering of the sense voltage if required. 3,4 Test A & B 6 Vref out 7 V'h DIGF 14 Active low input latches input data (DO, D6 and PH) into input latch. The capacitor on this pin programs the power on reset delay according to the formula: TOR = (0.35) (C) 10 6 Power-on reset circuit output. (micro reset signal). This output remains low from power on until the delay capacitor has charged past the delay threshold. Voltage applied to this points sets the reference for the D/A converter and threfore sets the maximum output current. Ground connection and also conduct heat to the P.C. board. Logic Supply Voltage Motor Supply Voltage These pins are for testing of D/A outputs. 2.5 V Band Gap Reference Reset Threshold Voltage Can be used to modify the internal comparator lockout time. In microstepping typical application a 1.8 KQ resistor must be connected between this pin and ground. 3/8 507 L6217A ELECTRICAL CHARACTERISTICS (Vee Symbol = 5.0 Parameter V, Tj = 25 'C unless otherwise specified noted) Test Conditions Min. Typ. Max. Unit Vsp Motor Supply Voltage 8 16 V Vsi Logic Supply Voltage 4.75 5.25 V LOGIC INPUTS (00-06, CSO, CS1, PH, RST and NB) VIL Input Low Voltage VIH Input High Voltage 2 0.8 V Vsi V IlL Input Low Current VI = 0.4 V - 400 IIH Input High Current VI = 2.4 V 10 !lA !lA 2.55 V CURRENT CONTROL AND D TO A SECTION Vcc =5.0 V 2.45 2.50 Vrel Reference Voltage Vrin Reference Input Range 2.0 3.0 V Monotonicity of D to A - 0.5 + 0.5 LSB -1 Linearity of D to A lop Peak Output Current (gain of current loop) Vrel = 2.38 V Rsense = 2 0 Data = 7 F (Hex) 10 Ouptut Matching Vrel = 2.38 V 225 252 +1 LSB 277 mA 5 % MONOSTABLE Toll Cutoff Time Td Turn-off Delay loll Ouptut Leakage Current R t =56KO Ct = 820 pF J.Ls 28 36 1 Data = 00 (Hex) J.Ls 100 J.LA RESET CIRCUITY Vth Reset Threshold Voltage 3.9 4.1 Reset Threshold Hysteresis 70 100 10 Iso Delay Capacitor Charging Current Vc =2.5 V 7 lsi Delay Capacitor Discharge Current Vc=2.5V 10 Vdth Delay Threshold Voltage V dhys Hysteresis Voltage on Delay Threshold 101 V sat 508 V mV 14 !lA mA 3.25 3.5 70 100 3.75 V mV Output Leakage Current Vo =5 V 200 !lA Output Saturation of Reset Out 10 = 2 mA 0.4 V SOURCE DIODE - TRANSISTOR PAIRS 4/8 4.3 Saturation Voltage 10 = 400 mA Diode Forward Voltage 10 = 400 rnA L6217A ELECTRICAL CHARACTERISTICS (continued) ISymbol I Parameter Test Conditions Min. Typ. Max. Unit SINK DIODE - TRANSISTOR PAIRS Saturation Voltage 10 = 400 mA Diode Forward Voltage 10 =400 mA AC CHARACTERISTICS TsDI(ST) 01 to Strobe ThDI(ST) 01 to Strobe .J. Setup Time .J. Hold Time TwPI Pulse Width Low TeST Strobe Setup Time T,.AfB(ST) AlB to Strobe TsPH(ST) PH to Strobe .J. Setup Time .J. Setup Time 100 500 600 2.5 100 100 ns ns ns ~ ns ns CIRCUIT OPERATION The current control section of the L6217A is a pulse width modulated control that senses the motor current. When the motor current reaches the peak programmed current the comparator will trigger the monostable turning off the upper transistors. After the toff time equal to 0.69 RC the upper drivers are enabled again. The peak current is given by the equation: lop = Vref 4.69 • Rsense • When the input data is 00. the output stages are disabled by internal logic so thatthe output current decays rapidly to zero. An internal generated lockout time avoids the use of an external RC network between the sensing resistor (RsA. RsB) and the corresponding input (VsA. VsB). by disabling the comparator sensing during the lockout time. This time is typically 2.5 its. D 128. D = Input data (0 - 7F H) 5/8 509 L6217A Figure 1 : Microstepping Typical Application. VSl =5VO NC - :, 3 8 _ _ _ _ _ _ _ ~_[)Z. ~~~--~~~~~~8 L~~ 0'.' --;; D3 37 36~~~~~~~~D~4~ 35 L6217A D5 34t----------~ 321------.--1 33 -- --~~-- 31~~--, 220pF D6 PH ovsp =lZV 30 -f ~~~~~~~~~~~ ----------1! I°'PT·' 15 Jl 025 W fL~~~~~~~~~~_ -~~------- 25mH r;:;\ 201lTyp~ 6/8 510 $-9271/2 L6217A Figure 2 : Microcomputer Interface Timing. DATA ~ ~ I.. .-j \J STROBE CS1 I.. T sDI(STll TwPI :; I =t-:-t---I .1 I 1 'I I' \ I Tc ST .. I ~ ~ C50 PH <1 T h D I (5T)1 ----- AlB I 1 ~ ------------- Ts AlB(5T) ~- i:- - - - - - - - ---- - -- - - - - ____ oJ, T5 PH (5 T) 5-10665 Figure 3 : Td. TOFF and Tlock out. ,I I I. Tlockout -. 5 - 10666 7/8 511 L6217A Figure 4 : Reset Waveforms. VS1 min 4.75V 'Vth Hmax Vt h H ---.;;.;.:.:..:....ifC--~_ _"-T...:;:.:...:.:~~"---.lI~_ _ Vth Hmin RESET OUT : TOR i ~ 8/8 512 5- 9268/1 L6220 L6220N QUAD DARLINGTON SWITCHES • TWO NON INVERTING + TWO INVERTING INPUTS WITH INHIBIT • OUTPUT VOLTAGE UP TO 50 V • OUTPUT CURRENT UP TO 1.8 A • VERY LOW SATURATION VOLTAGE • TTL COMPATIBLE INPUTS • INTEGRAL FAST RECIRCULATION DIODES DESCRIPTION The L6220 monolithic quad darlington switch is designed for high current, high voltage switching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common inhibit input. All inputs are TTL-compatible for direct connection to logic circuits. switches are commoned. Any number of inputs and outputs of the same device may be paralleled. Two versions are available: the L6220 mounted in a Powerdip 12 + 2 + 2 package and the L6220N mounted in a 15-lead Multiwatt package. • -./. '-: ..... ' ' ,:, : ' , ! ,'-. ,/ •.•..•.......... 0 ...........................•.. ".....•.. Multiwatt 15 Each switch consists of an open-collector darlington transistor plus a fast diode for switching applications with inductive loads. The emitters of the four Powerdip 12 + 2 + 2 ORDER CODES: L6220 L6220N BLOCK DIAGRAM ------jl0( 5) 15(11) 6(1) YIN 15(11) VIN =o~av =O.8V ~---,16(12) 3(15) A...---"'---'16(12) 2(H) I 14 (9) 1(13) 4512.13(6) '------S-9993 ~ ___ ~_ T INH =O.BV~---,14(9) 1(13) 4.5,12,13(8) I 5 - 999" ~------------- 6/10 518 L6220-L6220N Figure 8 : Switching Times Test Circuit. Figure 9 : Switching Times Waveforms. VINH 5V 11(7 ) 9(4) VIN 1.~ YIN2 10(5) VIN2.3 VIN 3 15(11) VIN ~ 16(12) YINI 0 ~ 0 5V Vc VINH S-9996f1 5-9995/1 Figure 10: Collector Saturation Voltage vs. Collector Current. Figure 11 : Free- wheeling Diode Forward Voltage VS. Diode Current. G IC / Ji - (A) 25'C -OUT1-4 - - OUT 2-3 // 1.75 / 1.50 If IV VI Tj=25'C -QUTl-4 - - OUT 2-3 / 1// ~ / / 0.75 0.50 0.25 / 0.5 ? 6359/1 V (A) 1.5 // 1.25 I--- 1-. L V ,/ f~ ~ o o 0.7 0.9 1.1 1.3 o 1.2 1.6 Vf (V) 7/10 519 L6220-L6220N Figure 12 : Collector Saturation Voltage vs. Junction Temperature at Ic = 1 A. VCEsal (V) f-- I ---1 Figure 13 : Free-wheeling Diode Forward Voltage vs. Junction Temperature at It = 1 A . r- JI C =IA -OUTI-4 --OUT 2-3 .l- - 1. 5 H-++-+-+-+ c r--t-- - .... - ..,.. r, 0.9 l- -+ 0.7 -50 -25 25 50 t 75 100 ,.", t +-t-H +-+-t-+-++-Ht:~t- - -[: 1.1 Tj (e) -- rT - 50 -25 0 25 50 75 100 Tj (OC) Figure 15 : Free-wheeling Diode Forward Voltage vs. Junction Temperature at IF = 1.8A. v, H--+++-H-+++-+-i--+++-H (v)LLlJ.. +I _1~~:.,;eA-I--+I-_+-+-j-+-+ -OUTl-4 --OUT 2-j t ~ -1--'-1 1; t 2 H"-++~-~_:t-_+-F-d:H--::+++' Figure 14: Collector Saturation Voltage vs. Junction Temperature at Ic = 1.8A. 1.6 ++-+-+-t-f--r - -+- 1.4 1.3 "., t r-~t I 0.8 VCEsal --I-- - 1.2 1.1 f-- - +r I (V) f-J 1,=18~_~ +- --- I-- - r-OUT 1-4 ' 1.7 f--- -- OUT 2-3- f-f-- -+-+-HI-+--++-H--+-1 r- - 1.6 -T f-- l- rf-- f-- I- e-- - 1.5 1.2 H-+-+-+-H-I--+-+-H-I--+-+-H ~f.::: 1.4 r- 1.3 r1.2 O. 8 '---"---'---'--'--,---"--'---'--'--'--'--'---'--'--L...J -50 -25 0 25 50 75 100 Tj(OC) -50 Figure 16. f- -25 0 25 50 - 75 100 Tj(OC) Figure 17 : Unipolar Stepper Motor Driver. vp VSf ~ 1 :E:E "'" OUTI VIN1 v MOTOR WINDINGS ,----l I CLAMP A OUT 2 ~ Vz VIN2 ~ VIN3 v OUT3 IN B 0---,--1'5 /V'V"> • L ___ CLAMPB VIN4 OUT4 ~ INHIBIT INHIBIT 8/10 520 I 10 I ..I.. 5- 9997/1 I ....J L6220-L6220N .' APPLICATION INFORMATION When inductive loads are driven by L6220/N, a zener diode in series with the integral free-wheeling diodes increases the voltage across which energy stored in the load is discharged and therefore speeds the current decay (Fig. 16). For reliability it is suggested that the zener is chosen so that Vp + Vz < 35 V. The reasons for this are two fold: 2) The instantaneous power must be limited to avoid the reverse st;lcond breakdown. The particular internal logic allows an easier full step driving using only two input signals. ~ I IN A ( I I I : I FULL STEP DRIVING IN B 1) The zener voltage changes in temperature and current. Figure 18 : Allowed Peak Collector-current vs. Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6220). 5-9987 Figure 19 : Allowed Peak Collector Current vs. Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6220N). G-6)64 Ie (Al 1.75 1:50 1.25 \ IC (Al 1\ 1\ Tamb=70'C T = 20ms - \ \ 1\ \ I\, ~\ \ 4~ 0.75 ,,, 2 r---.. ........ ....... 0.25 o 10 1.50 1.25 1'-., ~ i'... 0.50 \ 1.75 '" - 20 30 40 - I'-- .\ '\2 \ I'\( "'- 't ~ r-.... ........ ~T~bJ.c ~ T:l0ms "" -..... ........ r--..... ...... j'-..... I"- t-- 0.50 ~ " r\. 0.75 ........ 50 60 70 \. \\ \ \\ \ 0.25 ........ l"- r- o ('I.) 10 20 30 40 50 60 70 ('I.) MOUNTING INSTRUCTION The Rth j-amb of the L6220 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 20) or to an external heatsink (Fig. 21). ving a thickness of 3511 (1.4 mils). During soldering the pins temperature must not exceed 260°C and the soldering time. must not be longer than 12 seconds. The diagram of figure 22 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side" a" of two equal square copper areas ha- The external heatsink or printed circuit copper area must be connected to electrical ground. 9/10 521 L6220-L6220N Figure 20: Example of P.C. Board Copper area which is used as Heatsink. COPPER AREA 3~}J Figure 21 : External Heatsink Mounting Example. THICKNESS P. C. BOARO Figure 22 : Maximum Dissipable Power and Junction to Ambient Thermal Resistance vs. Side "a". Figure 23 : Maximum Allowable Power Dissipation vs. Ambient Temperature. G 355912 Ptot Rth (W) (.CfW) ~j-a.mb ......... ,- ........ t-. ...... ,..-1-- ,-. V Ptot n amb =70·C) - :::. s +~ -. \ of" 'i ">1< ;:,- 'to\, '\."" ,1-& ~ !. I'\.~ -4 ~1. ""IE: - -- f-- 40 ~ r-- 20 I (mm) lfI ~ ~ 1"\" ,... c-- 40 '!. "'~1 r- - -- 30 \~ +" ~- -~h j-amb --- ~+-++ ~ 1\+ "'~.!- ( ·CfW) -- -50 50 11/11 533 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L6222 QUAD TRANSISTOR SWITCH • • • • • The emitters of the four switches are commoned. Any number of inputs and outputs of the same device may be paralleled. OUTPUT VOLTAGE TO 50 V OUTPUT CURRENT TO 1.2 A VERY LOW SATURATION VOLTAGE TTL COMPATIBLE INPUTS INTEGRAL SUPPRESSION DIODE This device is intended to drive coils such as relays, solenoids, unipolar stepper motors, LED, etc. DESCRIPTION The L6222 monolithic quad transistor switch is designed for high current, high voltage switching applications. Powerdip 12 + 2 + 2 Each of the four switches is controlled by a logic input and all four are controlled by a common enable input. All inputs are TTL-compatible for direct connection to logic circuits. Each switch consists of an open-collector transistor plus a clamp diode for applications with inductive loads. ORDER CODE : L6222 ._--- ~ "--"--' --_. Figure 1 : Unipolar Stepper Motor Drive . . ~----- -----------------------------.--- 11 IN 1 IN 2 IN 3 IN 4 L6222 16 OUT 1 15 3 OUT 2 10 6 OUT 3 9 8 OUT 4 COIL 1 COIL 2 COIL 3 COIL 4 ENABLE 14 VZ =30V 4.5.12.13 S-9198 September 1988 1/3 535 L6222 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit 50 V Logic Supply Voltage 7 V Input Voltage 15 V Collector Current (PEAK) 1.2 A Vs Output Voltage Vss V,N Ic Top Operating Temperature Range (junction) - 40 to + 150 'C T stg Storage Temperature Range - 55 to + 150 °C CONNECTION DIAGRAM (top view) OUT 1 16 CLAMP A 15 ~ oun 11, ~ ENABLE IN 1 IN 2 GND [ I, 13 GND GND I 5 12 GND OUT J 11 Vss CLAMPS 10 IN 3 9 OUT" ~ IN I, S-9Z99 TRUTH TABLE For each inpul: Enable Input Power Out H H L H L ON OFF OFF X H = High level L = Low level X = Don·' care THERMAL DATA Max. Max. 2/3 536 80 14 L6222 ELECTRICAL CHARACTERISTICS (T 8mb Symbol Vss VCE (sus) ICEX VCE (sal) Parameter 25°C, unless specified) Test Conditions Logic Supply Voltage Min. Unit 4.50 Max. Typ. 7 V Output Sustaining Voltage VIN=0.8V Ic = 100 mA Output Leakage Current VCE =50 V VIN=0.8V Collector Emitter Saturation Voltage VIN ;" 2.0V Ic =0.1 A 0.2 Ic=O.4A 0.5 Ic =0.7 A 0.9 46 V 1 V IL Input low Voltage IlL Input Low Current VIH Input High Voltage IIH Input High Current VIN;" 2.0 V Is Logic Supply Current Vss = 5 V All Outputs ON Ic = 0.7 A VIN = 0.4 V V 0.8 V -100 flA ±10 flA 85 mA 2.0 All Outputs OFF mA V 50 8 mA IR Clamp Diode Leakage Current VR = 50 V 100 VF Clamp Diode Forward Voltage IF =0.7 A 1.6 IF =1.2 A 2.0 f.lA V 3/3 537 ------------------------- --------------------- BIDIRECTIONAL THREE-PHASE BRUSHLESS DC MOTOR DRIVER PRELIMINARY DATA • 3A OUTPUT CURRENT, CONTROLLED IN LINEAR MODE • SUPPLYVOLTAGEUPT018V • COMPATIBLE WITH ANI F-TO-V CONVERTER ANDPLLSPEEDCONTROLSYSTEM • SLEW RATE LIMITING FOR EMI REDUCTION • CONNECTS DIRECTLY TO HALL EFFECT CELLS • THERMAL SHUTDOWN WITH HYSTERESIS • THREE-STATE OPERATION ALLOWS NEGLIGIBLE POWER DISSIPATION DURING 1/3 f CYCLE • INTERNAL PROTECTION DIODES • FEW EXTERNAL COMPONENTS DESCRIPTION put stage is switched to an off state, reducing dissipation to a very low value and minimizing torque ripple. A speed control input controls the base current to the lower transistors to limit the motor current and hence control the speed. Any type of speed control system, including F to V and PLL systems, may be used with the L6230 by providing an analog signal at this input. The motor current may be sensed by an external resistor connected to a sensing pin on the device. The power stage of the device is designed to eliminate the possibility of simultaneous conduction of the upper and lower power transistors of one output driver, when operating in the right loop. The L6230 is a single-chip driver for three-phase brushless DC motors capable of delivering 3A output current with supply voltages to 18 V_ Designed to accept differential input from the Hall effect sensors, the device drives the three phases of a brushless DC motor and includes all the commutation logic required for a three phase bidirectional drive_ Both delta and wye configurations may be used To limit EMI esmission the L6230 operates in a linear mode and controls the rise and fall times of the output stage. In addition the device is designed to limit power dissipation: during recirculation the out- Mulliwatt-15 (Horizontal) ORDER CODE: L6230H ~--------- ----- --------- CONNECTION DIAGRAM (top view) -~.------~ O· . o 15' 14, 13 12: 11 i l9;Oi H 3(-) H2 H2 H1 Hl 3 SENSING OUT J Vc 6' 5 4 September 1988 CURRENT GND HJ (+) 2 connE'cted to pin 8 OUT 1 'V s OUT 2 8, 7! -~--- H (+) (-) (+) INDEX FWD/REV s- 9].{.S/1 1/8 539 L6230 BLOCK DIAGRAM INDEX +Vs-12V +vs Vc 10 4 5 HA.LL LOGIC INPUT 9 GND ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vs Supply Voltage 20 V 10 Peak Output Current Each Channel - Non Repetitive (100 J.Ls) - Repetitive (t = 10 ms) - 0 C Operation 4 3.5 3 A A A Logic and Analogic Inputs Vs Vi Parameter = 75°C Ptot Total Power Dissipation T case Top Operating Temperature Range Tj, T stg Storage and Junction Temperature 25 W o to 70 °C - 40 to 150 °C THERMAL DATA Max 2/8 540 3 L6230 PIN FUNCTIONS I/O Function I Direction Control. When this pin is low, the motor will run in the forward direction. A high will drive the motor in the reverse direction. Direction is defined by the position of the sensors in the motor. INDEX 0 Signal pulse proportional to the motor speed. In PLL speed control applications, this is the feedback to the PLL. One pulse per electrical rotation. This is an open collector output. 3 HI (+) I Positive input of differential amplifier on channell. Interfaces with Hall Effect sensor, SI, from motor. 4 HI (-) I Negative input of differential amplifier on channell. Interfaces with Hall Effect sensor, SI, from motor. 5 H2 (+) I Same as Pin 3 for Channel 2 6 H2 (-) I Same as Pin 4 for Channel 2 7 H3 (+) I 8 GND Name N° 1 FWD/REV 2 Same as Pin 3 for Channel 3 Ground Connection 9 H3 (-) I Same as Pin 4 for Channel 3 10 Vc I Speed control input. Connected to output of PLL in PLL speed control applications. 11 OUT3 12 SENSE 13 OUT2 14 Vs 15 OUTI 0 I 0 Output motor drive for phase 2. 0 Output motor drive for phase 1. Motor Supply Voltage ELECTRICAL CHARACTERISTICS (T amb Symbol Output motor drive for phase 3. Current Sensing. Input for load current sense voltage for output stage. Parameter Vs Supply Voltage Is Quiescent Supply Current = 25 'C ; Vs = 12 V unless otherwise specified) Test Conditions Min. Typ. Max. 10 12 18 Unit V 60 100 mA HALL AMPLIFIERS a V CM Common Mode Voltage Range Vio Input Offset Voltage Vi =6 V lib Input Bias Current lio Input Offset Current 10 V 2 10 mV Vi =6 V 2 10 f.lA Vi =6 V 0.1 f.lA SPEED CONTROL INPUT (Vc) Vi Input Voltage Range lib Input Bias Current V,c Input Clamping Voltage a Vc < Vsens 1 5.9 5 V 5 f.lA V 3/8 541 L6230 ELECTRICAL CHARACTERISTICS (continued) ~ymboiT Para~;t;; -- - ~~ Te;t CO~dit;~n!l-=-: _!'Iin.JTy~-Max. 1- Unit FWD/REVERSE INPUT VIH Input High Voltage I--~-I~--+-:-~~~-~:-~f~~o~~;~~- I I I Vs l V! --r-------1= --- - --t- -.-J~--I-~-~ t- ~~ ! =-5-r=-~_I_llA 0 - p~u_t-_L-o:W~~c~u~rr~e_n-t~~~.~~~_ _ _-- IlL ----i-_-ln___ 2 I HALL LOGIC OUTPUT --~--.------ VLO LO.W Output Voltage I __ IL_ Leai--- LOWER DRIVER I--n UD2-; LD2 ~~i=:===i~. UD3 LD3 _ _ + - - + - -___--1 . __ T:---L _:_i-__L_J ~.-t====iL t-t=::t::=~~I:----LJ- . j . -L-{: --',-I r - 0 - -...... lOUT: (CH •.~!.~ .......;. o __.. _ - - - - - - - - - - . ---- DETERMINING HALL EFFECT SENSOR CODING at 180 intervals, then with respect to fig. 4, a similar diagram, fig. 6, results in sensors 60 apart with the windows rotating clockwise. This situation results in a "forward" rotation of the motor. The L6231 assumes that the positioning of the Hall Effect sensors in a three-phase brushless DC bipolar motor are at 30 intervals. One can imagine two "windows" on the rotor each of which is 90 wide and 180 apart, see fig. 4. As a window passes over a sensor, the sensor output goes high. The timing diagram, fig.3, shows the waveforms produced. These waveforms must appear at the Hall Effect Inputs of the L6231. Note that the rotation in fig. 4 must be counter-clockwise for forward rotation of the motor in whatever manner that is defined for the motor. Fig. 4 is a stylized concept for determining the Hall Effect code pattern and does not reflect the actual direction of rotation of the motor in a physical sense. If a motor is chosen whose sensor outputs do not match the L6231 desired input pattern, a signal set conversion must be determined. It is helpful to visualize this by developing a diagram similar to that of fig. 4. For example, let us examine the-output pattern of a differentlype of motor (fig. 5). Assuming 90 windows 6/7 552 Figure 4. S3 L6231 Since S3 is the first sensor encountered by the window in fig. 6, this should be used for the L6231 Hall Effect Input, H1. After 30 of rotation CW, the H2 input of the L6231 must go high. The inverse of S1 from the motor would satisfy this. After an additional 30 of rotation, the H3 input must go high. The S2 sensor is encountered by the window. Thus, S2 is applied to this input, H3. By continuing around the diagram, one can develop a pattem which matches that for the L6231. Figure 5. S3 \ / S2 _ _ _ _---'~---..l.- - - ' - : I . . . __________ S1 ~_ S1 . I ,.,,,,, , Thus, the conversion table for this particular motor is: L6230 Inputs Motor Sensors H1 S3 S1 H2 S2 H3 S2 S3 o Figure 6. 90 180 270 ANGLE OF ROTATION Note, forthe inverted signal from S1 an actual inverter gate is not necessary with the L6231. Since the L6231 has differential inputs, the negative input pin may be used. Therefore, with TIL compatible Hall Effect sensors, the positive input is connected to a reference point along with the Gther negative inputs. 7/7 553 L6233 .. I PHASE LOCKED FREQUENCY CONTROLLER ADVANCE DATA • PRECISION PHASE LOCKED FREQUENCY CONTROL SYSTEM • XTAL OSCILLATOR • PROGRAMMABLE QUENCY DIVIDERS • PHASE DETECTOR WITH ABSOLUTE FREQUENCY STEERING • DIGITAL LOCK INDICATOR • DOUBLE EDGE OPTION ON THE FREQUENCY FEEDBACK SENSE AMPLIFIER REFERENCE • TWO HIGH CURRENT OP-AMPS • 5V REFERENCE OUTPUT FR!::- The L6233 is designed for use in phase locked frequency control loops. While optimized for precision speed control of DC motors, these device is universal enough for most applications that require phase locked control. A precise reference frequency can be generated using the device's high frequency oscillator and program· mabie frequency dividers. The oscillator operates using a broad range of crystals, or, can function as a buffer stage to an external frequency source. The phase detector on these integrated circuit compares the reference frequency with a fre· quency/phase feedback signal. In the case of a motor, feedback is obtained at a hall output or other speed detection device. This signal is buffered by a sense amplifier that squares up the signal as it goes into the digital phase detector. The phase detector responds proportionally to the phase error between the reference and the sense amplifier output. This phase detector includes absolute frequency steering to provide maximum drive signals when any frequency error exists. This feature allows optimum startup and lock times to be realized. Two op-amps are included that can be con· figured to provide necessary loop filtering. The outputs of these op-amps will source or sink in excess of 16mA, so they can provide a low impedance control signal to driving circuits. Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths. A digital lock signal is provided that indicates when there is zero frequency error and a 5V reference output allows DC operating levels to be accurately set. 20 PlCC DIP-16 Plastic (O.25) ORDERING NUMBERS: L6233 (DIP-16) L6233P (20 PLCC) CONNECTION DIAGRAMS (Top views) 16 GROUND 2 15 osc. INPUT 4 1) +VIN DOUBLE EDGE DISABLE 12 AUX. AMP OUTPUT SENSE AMP. 11 AUX.AMF NON, INV. INPUT 0111 4/5 SELECT 0111 2/4/8 SELECT LOCK INDICATOR " OUTPUT PHASE OET ECTOR OUTPUT INPUT 5V REf OUTPUT LOOP AMP. INV. INPUT .8 osc. OUTPUT LOCK INDICATOR OUTPUT PHASE DETECT. OUTPUT N.C. DOUBLE EDGE DISABLE SENSE AMP. 'NPUT 18 osc. OUTPUT 16 N. C. AUX, AMP. +VIN OUTPUT AUX.AMP. NON. [NY. INPUT AUX.AMP INV. INPUT lOOP AMP OUTPUT DIP·16 June 1988 1/8 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 555 L6233 ABSOLUTE MAXIMUM RATINGS Supply voltage Power dissipation (Tamb .;;; 70°C) Operating temperature range Storage temperature 14 1 o to 70 -65 to 150 v w °c °c BLOCK DIAGRAMS (DIP-16) 15 14 1 2 5-9311 6 3 10 LOOP 11 AMPLIFIER 9 B 7 13 16 12 (PLCC PACKAGE) 5 B 13 LOOP 14 AMPLIFIER 20 ~2/_8_________________________ ~~~~~~~~~:9~ 556 ___________________________ L6233 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications hold for O°C to Parameter Test Conditions Min. Supply current Is Tamb +70°C; +VIN = 12V) Typ. Max. 20 Unit mA REFERENCE V REF Output voltage 4.75 5.0 5.25 V /:;VREF Load Regulation lOUT = 0 to 7mA 5.0 20 mV t;VREF Line regulation +VIN = B to 12V 2.0 20 VOUT= OV 35 mA Short circuit current Isc OSCILLATOR Gv DC voltage gain Input DC level VIB Oscillator input to oscillator output Oscillator input pin open, mV 16 dB T j = 25°C 1.3 V Input impedance VIN = VIB ± 0.5V, T j = 25°C 1.6 Kn Vo Output DC level Oscillator input pin open T j = 25°C 1.4 V foMAX Maximum operating frequency ZIN * 10 MHz 10 MHz DIVIDERS f OMAX Maximum input frequency Input = 1 Vpp at oscillator input Input = 5V (Div. by 4) 150 500 jJ.A 0.0 5.0 jJ.A Div. 4/5 input current Input = OV (Div. by 5) VTH -5.0 Div. 4/5 threshold 1.6 2.2 V Input = 5V (Div. by B) 0.5 150 500 jJ.A Input = OV (Div. by 2) -500 -150 Div. 2/4/B input current Div. 2/4/B open circuit voltage Input current = OjJ.A (Div. by 4) 1.5 2.5 Div. by 2 threshold 0.35 O.B Div. by 4 threshold 1.5 Div. by B threshold Volts below VREF 0.35 jJ.A 3.5 V 3.5 V V O.B V 30 % 10 mV -0.2 jJ.A SENSE AMPLIFIER VT Threshold voltage HT Threshold hysteresis Ib Input bias current Percent of V REF Input = 1.5V DOUBLE EDGE DISABLE INPUT Input = 5V (Disabled) VI VT 150 500 jJ.A -5.0 0.0 5.0 jJ.A 0.5 1.6 2.2 V I nput current Input = OV (Enabled) Threshold voltage ___________________________ ~~~~@~g~:~~~ ________________________ ~3/~8 557 L6233 ELECTRICAL CHARACTERISTICS (continued) Parameter Test Conditions PHASE DETECTOR V OH High output level Positive Phase/Freq. Error, Volts Below V REF _._- --.... ! 0.2 0.5 i V VOL Low output level Negative Phase/Freq. Error 0.2 0.5 V V OM Mid output level Zero Phase/Freq. Error, Percent of V REF 47 i 50 53 % High level maximum source VOUT = 4.3V 2.0 8.0 mA Low level maximum sink curro VOUT=0.7V 2.0 5.0 mA Mid level output impedance (Note 2) lOUT = -200 to +200/LA 6.0 Kn current T j = 25°C LOCK INDICATOR OUTPUT V sat Saturation voltage Freq. Error, Leakage current Zero Freq. Error LOOP AMPLIFIER Ib NON INV. reference voltage Percent of V REF Input bias current Input = 2.5V Gv Open loop gain SVR Supply voltage rejection ISH Short circuit current +VIN = 8 to 12V 47 50 -0.8 -0.2 53 % /LA 60 75 dB 70 100 dB Source, VOUT= OV 16 35 mA Sink, VOUT= 5V 16 30 mA "----- AUXILIARY OP-AMP VOS Input offset voltage VCM = 2.5V Ib Input bias current V CM = 2.5V V CM = 2.5V los Input offset current Gv Open loop gain SVR Supply voltage rejection CMR Common mode rejection ISH Short circuit current 8 mA 10 mA 70 120 dB +VIN = 8 to 12V 70 100 dB VCM = 0 to 10V 70 100 dB Source, VOUT=OV 35 mA Sink, VOUT=5V 30 mA • These impedance levels will vary with T j at about 1700ppm/oC THERMAL DATA Rth j-amb 558 mV 200 Thermal resistance junction-ambient max 100 L6233 APPLICATION INFORMATION Determining the Oscillator Frequency The resulting reference frequency appearing at the phase detector inputs is equal to the oscillator frequency divided by the selected divide ratio. If the double edge option is used, (Pin 5 low), the frequency of the sense amplifier input signal is doubled by responding to both the rising and falling edges of the input signal. Using this option the loop reference frequency can be doubled for a given motor RPM. The frequency at the oscillator is determined by: the desired RPM of the motor, the divide ratio selected, the number of poles in the motor, and the state of the double edge select pin. fos c (Hz) = (Divide Ratio) • (Motor RPM) • (1/60 SEC/MIN) • (No. of Rotor Poles/2) (x 2 if Pin 5 Low) Fig. 1 - Recommended Oscillator Configuration Using AT Cut Quartz XTAL n s . 1 Vpp MAY BE REQUIRED TO PREVENT SPURIOUS OSCILLATION -,, - lJV I' s- 9314 Fig. 2 - External Reference Frequency Input EXTERNAL 1 to 2 "pp REFERENCE /\J ----1 ns~1Vpp 14 - - , I or 200mV pp t02V nJ -~13V Z· 5-9315 Fig. 3 - Method for Deriving Rotation Feedback Signal From Analog Hall Effect Device VREF OUT OJ .... F ~I---t-----I 300mVpp LOW LEVEL ANALOG HALL OUTPUT :> 5-9316 * This signal may require filtering if chopped mode drive scheme is used. -------------- I::1i. ~~~~m?::i!~©~ _____________ ::..5:.::../8 559 ~ I L6233 APPLICATION INFORMATION (continued) Phase detector operation The phase detector on these devices is a digital circuit that responds to the rising edges of the detector's two inputs. The phase detector output has three states: a high, 5V state, a low, OV state, and a middle, 2.5V state. In the high and low states the output impedance of the detector is low, the middle state output impedance is high, tipically 6.0KQ. When there is any static frequency difference between the inputs the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the reference frequency signal) is greater in frequency. When the frequencies of the two inputs to the detector are equal the phase detector switches between its middle state and either the high or. low states, depending on the relative phase of the two signals. If the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time difference between the rising edges of the inputs, and will be at its middle level the remainder of the period. If the phase relationship is reversed then the detector will go low for a time proportional to the phase difference of the inputs. The resulting gain of the phase detector, Kef> , is 5V/41T, radians, or about 0.4 V /radian. The dynamic range of the detector is ± 21T radians. The operation of the phase detector is illustrated in the figures below. The upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions. The lower figure is a state diagram of the phase detector logic. In this figure, the circles represent the 10 possible states of the logic and the connecti ng arrows the transition events/paths to and from these states. Transition arrows that have a clockwise rotation are the result of a rising edge on the +input, and conversely, those with counter-clockwise rotation are tied to the rising edge on the-input signal. The normal operational states of the logic are 6 and 7 for positive phase error, 1 and 2 for a negative phase error. States 8 and 9 occur during positive frequency error, 3 and 4 during negative frequency error. States 5 and 10 occur only as the inputs cross over from a frequency error to a normal phase error only condition. The level of the phase detector output is determined by the logic state as defined in the state diagram figure. The lock indicator output is high, off, when the detector is in states 1, 2, 6 or 7. Fig. 4 - Typical Phase Detector Output Waveforms T (ONE PERIOD OF REFERENCE 'I FREQUENCY(. sv SENSE AMPLIFIER INPUT LEADING REFERENCE FREQUENCY INPUT BY 90 DEGREES 2.SV ov sv 2J:>V o J_U_U_U_U SENSE AMPLIFIER INPUT TRAILING REFERENCE FREQUENCY INPUT BY 90 DEGREES ~-9319 _6_/8_ _ _ _ _ _ _ _ _ _ _ _ _ 560 ~ ~~~~~~1Jr::~~~, -------------- L6233 Fig. 5 - Phase Detector State Diagram RISING EDGE ON PHASE D[TECTO~R - INPUT (R(fERENCE) RISING EDGE ON PHASE DETECTOR + INPUT (SENSE AMP) C + • I OUTPUT« 25V OUTpuT. 5V DIGITAllOC~ I OUTPUT. OIl INDICATOR HIGH DURING STATES I. 2. 6. AND 7 5- 9421 Fig.6 - Suggested Loop Filter Configuration FROM REF. FILTER Vln R3 ~ R1 1 + S/wP + S/wZ TO POWER DRIVE STAGE wp R2C1 LOOP AMP ~- * 9311 The statistic phase error of the loop is easily adjusted by adding resistor, R4, as shown. To lock at zero phase error R4 is determined by : wZ Where: It.vOUTI and V OUT (R1 + R2) C1 = 1VOUT-2.5VI = DC Operating Voltage At Loop Amplifier Output During Phase Lock (Vour 2.5) (V our 2.5) 2.5V • R'3 R4 > a R4 Goes to OV < 0 R4 Goes to 5.0V I t.VOUT I - - - - - - - - - - - 51 1 SGS-mOMSON 'J, '" 7/8 ~D©Ilil©~~rn©1JIlil@~D©(\) 561 L6233 Fig. 7 - Reference Filter Configuration S2 FROM Vin Rl PHASE DETECTOR o--C::J-......-C::-r-.....- - j OUTPUT Vout >-~"""'-Q S' 1 + --+-WN WN' TO lOOP FILTER INPUT JRl R2Cl C2 AUXILIARV OP AMP. S-9318 _l_=_l_e 20 2 Rl + R2 JR1R2 Cl =r= Note: with Rl = R2 Cl Fig. 8 - Reference Filter Design Aid - Gain Response Fig.9 - Reference Filter Design Aid - Phase Response 6·6061 G 6C61 (dBI I , I r- - 50 VARIABLE is 1/d 2 (FOR Rl ::R211.&z,.C,C2) - 20 l.0 5 tx\ 1 -10 'f I ~ -20 I - 40 - 60 I r----r-I-+---t'-pI\'t'f'\\l";;R1,ABLE 15".' (FOR R1,R211Jhi'C21 -100 -30 N -40 I I -140 -160 - 180 8 0.1 ~8/_8_____________________ ~~~~~~?v~f~~~ 562 r- : - 120 I 6 1-10 ""t"'~ -80 I "'- ~ 1--50 . . . . ~~~v .. - 20 w~ 1 - - - 2 ~ r-......~ I ~~~~~itj-20 1--+-r+rH~ 20 /,0 1---10 10 o'f .... ~:;;: L~_U--LLUll_~:::::t~i!iiilil 6 8 0.1 --------------------------- L6235 R-DAT BRUSH LESS DC MOTOR DRIVER ADVANCE DATA • 400mA OUTPUT CURRENT, CONTROLLED IN LINEAR MODE • COMPATIBLE WITH ANI F-TO-V CONVERTER AND PLL SPEED CONTROL SYSTEM • INHIBIT FUNCTION • SLEW RATE LIMITING FOR EMI REDUCTION • CONNECTS DIRECTLY TO HALL EFFECT CELLS • THERMAL SHUTDOWN WITH HYSTERESIS • THREE-STATE OPERATION ALLOWS NEGLIGIBLE POWER DISSIPATION DURING 1/3f CYCLE A • INTERNAL PROTECTION DIODES • FEW EXTERNAL COMPONENTS The L6235 is single-chip driver for three-phase brushless DC motors capable of delivering 400mA output current with supply voltages to 18V. Designed to accept differential input from the Hall effect sensors, the device drives the three phases of a brush less DC motor and includes all the commutation logic required for a three phase drive. To limit EM I emission the L6235 controls the rise and fall times of the output stage. In addition the device is designed to limit power dissipation: during recirculation the output stage is switched to an off state, reducing dissipation to a very low value and minimizing torque ripple. A speed control input controls the base current to the lower transistors to limit the motor current and hence control the speed. Any type of speed control system, including F to V and PLL system, may be used with the L6235 by providing an analog signal at this input. The motor current may be sensed by an external resistor connected to a sensing pin on the device. The power stage of the device is designed to eliminate the possibility of simultaneous conduction of the upper and lower power transistors of one output driver, when operati ng in the right loop. PLCC (15+5) ORDERING NUMBER: L6235 INDEX BLOCK DIAGRAM +V6-12V .vB 17 3Kohll 'lie 13 10 12 GND June 1988 1/7 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 563 L6235 CONNECTION DIAGRAM (Top view) Gl Z o INHIBIT 18 OUT I INDEX 17 +VS H! (+) 16 OUT 2 H 1(-) 15 SENSING H 2(+) 14 OUT 3 9 10 :r:r N ~ " w Q .!. 0 Z 12 13 :r W ~ < n ABSOLUTE MAXIMUM RATINGS VS '0 Vi Ptot Top Tj , T st9 Supply voltage Peak output current each channel non repetitive (100J.!s) - repetitive (80% on - 20% off; ton = 10ms) - DC operation Logic and analogic inputs Total power dissipation at Tpins = 50°C Operati ng temperature range Storage and junction temperature 18 V 1.5 500 400 +Vs 5 o to 70 -40 to 150 A mA mA W °C °C THERMAL DATA Rth j-amb Rth j-pins Rtt Thermal resistance junction-ambient Thermal resistance junction-pins Transient thermal resistance It = 2sec.) max max max 100 20 30 .: :;2/'-.: 7_____________ ~ ~~~~m?1I~:~~©~ -------------564 L6235 PIN FUNCTIONS NAME FUNCTION I/O 4 INHIBIT 5 INDEX 6 H1 (+) Positive input of differential amplifier on channell. Interfaces with Hall Effect sensor, Sl, from motor. 7 H1 (-) Negative input of differential amplifier on channell. Interfaces with Hall Effect sensor, S 1, from motor. 8 H2 (+) Same as pin 3 for channel 2. 9 H2 (-) Same as pin 4 for channel 2. 10 H3 (+) Same as pin 3 for channel 3. 11 GND Ground connection. 12 H3{-) Same as pin 4 for channel 3. Output stage inhibit. When this pin is high all three output stages are ina high impedance state! o Speed control input. Connected to output of PLL in PLL speed control applications. 13 14 Out 3 15 Sense 16 Out 2 o Output motor drive for phase 3. Current Sensing. Input for load current sense voltage for output stage. o 17 18 Signal pulse proportional to the motor speed. In PLL speed control appl ications, th is is the feedback to the PLL. One pulse per electrical rotation. This is an open collector output. Output motor drive for phase 2. Motor supply voltage. Out 1 o Output motor drive for phase 1. _____________________________ ~~~~~~~~~:~~~ __________________________~3/~7 565 L6235 ELECTRICAL CHARACTERISTICS (Tamb Parameter Vs Supply voltage Is Quiescent supply current = 25°C; Vs = 12V unless otherwise specified) Test Conditions Min. Typ. 10 12 Without Load 30 Max. Unit V 60 rnA 10 V HALL AMPLIFIERS V CM Common mode voltage range V io Input offset voltage Vi = 6V 2 10 mV lib Input bias current Vi = 6V 2 10 IlA lio Input offset current Vi = 6V 0.1 0 IlA SPEED CONTROL INPUT (Vel Vi Input voltage range lib Input bias current Vic Input clamping voltage 0 < Vc 1 V sens 5 V 5 IlA 5.9 V INHIBIT INPUT VIH Input high voltage 2 Vs V VIL Input low voltage 0 0.8 V IIH Input high current 10 IlA IlL Input low current -50 IlA 5mA 0.8 V = 10 IlA -5 HALL LOGIC OUTPUT = VLO Low output voltage I IL Leakage current VCE 12V OUTPUT POWE R STAG E Vsat Total saturation voltage V OSR Output voltage slew-rate V sens Sense voltage range 10 10 10 = = = 0.15A O.4A 1.0A 0 2.2 2.5 2.7 V 100 V/ms 0.7 V THERMAL SHUTDOWN Tj Ju nction temperatu re TH Hysteresis DC 150 30 DC -'4'-'/7_____________ f.U ~~~~m~1I~:J?©' -------------566 L6235 DESCRIPTION The output current is related to the speed control voltage by: The L6235 is a three-phase brush less motor driver IC containing all the power stages and commutation logic required for a three-phase drive. When the INHIBIT INPUT is high all three OUTPUTS ARE PLACED in a high - IMPEDANCE STATE. (V c - 1) 7 Rs The value of the sensi.ng resistor is given by: Logic signals from the motor's Hall effect sensors are decoded to generate the correct driving sequence according to the truth table of Fig. 1. Rs = (Vx - 1)/(7 Imax) where Vx is the full scale voltage of Vc. When one of the push-pull output drivers is activated the upper transistor is always in saturation while the lower transistor is controlled in linear mode to set the desired speed in steady state conditions. In this way the Vc/l out characteristics can be modified. Note that Vx max is clamped a't 5.9V. The most important feature of the L6235 is slew rate control. With this device a typical value of 0.1V/J.ls is achieved, reducing EMI to a very low value. In PLL speed control applications the device provides a signal proportional to the motor speed at pin 2 (it is the buffered H 1 input). The output of the PLL is connected to the speed control input of the device at pin 10, Vc. Another key feature is three-state operation; when the current is recirculating the corresponding phase driver is switched off and power dissipation is negligible. Current recirculates through the free~wheeling diodes in the acceleration phase and through the motor is steady-state conditions. Torque ripple is also minimized. In addition, a 1 V offset is added to the speed demand voltage to match the minimum output of the PLL. An external resistor, R s , senses the output stage currel'1t. The sensing voltage across this resistor is amplified in the device by a factor of 7 to allow a reduction in the voltage drop the resistor. The L6235 can also operate with a brush less motor connected in a star configuration, leaving the centre floating. • The Hall inputs are ground compatible comparators and can work with direct active digital Hall signals on three terminals (of the same polarity) and a TTL level on the other three terminals. The amplified sensing voltage is then compared with the speed demand signal from the PLL and the resulting error signal sets the amplifier output accordingly. Fig. 1 - TRUTH TABLE HALL EFFECT DIFF. INPUT UPPER DRIVER STATUS 1 = POSITIVE O' = NEGATIVE o =OFF 1 =ON 1 = ON o =OFF H1 H2 H3 UD1 UD2 UD3 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1. 0 0 0 1 1 1 0 0 LOWER DRIVER STATUS 0 0 0 0 0 LD1 LD2 LD3 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 567 L6235 Fig. 2 - Timing diagram J. . O... ; ... HALL HI DII::UETR~ :: .... UPPER DRIVER 'UDI LONER DRIVER LDI ~.. 2 3 4 ~ ~ ~ ~ ~ ~ ~ j... ~ . !. . ~. h ... ..... ... ... ... .. .... .. 0 ±Ji--'...~...L-1:::::t-..-...-t..-....~......... j.......t...... .. .... l::J=... :.......: 0 EFFECTS i. . . ·~...... n ! UD2-l . . . ·. . . l. . . ·! ...... ,..... j.......!. . . .:. . . .: ~! : ! ! I::' : : LD2+-l 0 i LJ : I n :~J.';:: . .'. .!. ~~ wi::.: ~!.! (CH •• 0 S-94B4 DETERMINING HALL EFFECT SENSOR CODING Fig. 3 The L6335 assumes that the positioning of the Hall Effect sensors in a three-phase brushless DC bipolar motor are at 30 intervals. One can imagine two "wjJ:ldows" on the rotor, each of which is 90 wide and 180 apart, see fig. 4. As a window passes over a sensor, the sensor output goes high. The timing diagram, fig. 2, shows the waveforms produced, These waveforms must appear at the Hall Effect Inputs of the L6235. Note that the rotation in fig. 3 must be counterclockwise for forward rotation of the motor in whatever manner that is defined for the motor. Fig. 3 is a stylized concept for determining the Hall Effect code pattern and does not reflect the actual direction of rotation of the motor in a physical sense, If a motor is chosen whose sensor outputs do not match the L6235 desired input pattern, a signal set conversion must be determined. It is helpful to visualize this by developing a diagram s[milarto that of fig. 4. For example, let us examine the output pattern of a different type of motor (fig. 4). Assuming 90 windows at 180 intervals, then with respect to fig. 3, a similar diagram, fig. 5, results in sensors 60 apart with the windows rotating clockwise. The situation results in a "forward" rotation of the motor. ~6/~7___________________________ ~~~~~~~~~:J?~ ------------~-------------- 568 L6235 Since S3 is the first sensor encountered by the window in fig. 5, this should be used for the L6235 Hall Effect Input, H1. After 30 of rotation CW, the H2 input of the L6235 must go high. The inverse of S1 from the motor would satisfy this. After an additional 30 of rotation, the H3 input must go high. The S2 sensor is encountered by the window. Thus, S2 is applied to this input, H3. By continuing around the diagram, one can develop a pattern which matches that for the L6235. Fig. 5 53 ,I 52 --------~~~--L--51 !.-9~83 Fig. 4 Thus the conversion table for this particular motor is: L6235 Inputs Motor Sensors 51 S2 H1 S3 H2 S1 H3 S2 Note, for the inverted signal from S1 an actual inverter gate is not necessary with the L6235. Since the L6235 has differential inputs, the negative input pin may be used. Therefore, with TTL compatible Hall Effect sensors, the positive input is connected to a reference point along with the other negative inputs. S3 o 90 180 270 ANGLE OF ROTATION Fig. 6 - Application circuit using the L6233 PLL-Controller LOCI< INDICATION ,---------~------~------------~~--~+V5 OUTPUT J: IOpF lKU 510n L6233P 12 f-.---------1 lKU 5KO ___________________________ ~~~~~~g~~©~ ________________________ ~7/7 569 L6236 BIDIRECTIONAL R-DAT BRUSH LESS DC MOTOR DRIVER ADVANCE DATA • 400mA OUTPUT CURRENT, CONTROLLED IN LINEAR MODE • COMPATIBLE WITH ANI F-TO-V CONVERTER AND PLL SPEED CONTROL SYSTEM • SLEW RATE LIMITING FOR EMI REDUCTION • CONNECTS DIRECTLY TO HALL EFFECT CELLS • THERMAL SHUTDOWN WITH HYSTERESIS • THREE-STATE OPE RATION ALLOWS NEGLIGIBLE POWER DISSIPATION DURING 1/3f CYCLE • INTERNAL PROTECTION DIODES • FEW EXTERNAL COMPONENTS The L6236 is a single-chip driver for three-phase brush less DC motors capable of delivering 400mA output current with supply voltages to 18V. Designed to accept differential input from the Hall effect sensors, the device drives the three phases of a brush less DC motor and includes all the commutation logic required for a three phase bidirectional drive. Both delta and wye configurations may be used. To limit EMI esmission the L6236 operates in a linear mode and controls the rise and fall times of the output stage. In addition the device is designed to limit power dissipation: during recirculation the output stage is switched to an off state reducing dissipation to a very low value and minimizing torque ripple. A speed control input controls the base current to the lower transistors to limit the motor cur· rent and hence control the speed. Any type of speed control system, including F to V and PLL systems, may be used with the L6236 by pro· viding an analog signal at this input. The motor current may be sensed by an external resistor connected to a sensing pin on the device. The power stage of the device is designed to eli· minate the possibility of simultaneous conduction of the upper and lower power transistors of one output driver, when operating in the right loop. PLCC (15 + 5) ORDERING NUMBER: L6236 BLOCK DIAGRAM INDEX 5- 9828 June 1988 GNO 1/7 This is advanced information on a new product now in-"development or undergoing evaluation. Details are subject to change without notice. 571 L6236 CONNECTION DIAGRAM (Top view) G> Z o FWD/REV 18 OUT I INDEX 17 +VS H 1(+) 16 OUT 2 H 1(-) 15 SENSING H 2(+) 14 OUT 3 9 10 II 12 13 _ _......................................._ - - ' 5-9841 :x: :x: !:::: w ..!., ~ :x: G> Z 0 w ~ < n ABSOLUTE MAXIMUM RATINGS Supply voltage Peak output current each channel - non repetitive (lOOJ,ls) - repetitive (80% on - 20% off; ton = 10ms) - DC operation Logic and analogic inputs Total power dissipation at T plns = 50°C Operating temperature range Storage and junction temperature 18 1.5 A 500 mA mA 400 +Vs 5 Oto 70 -40 to 150 THERMAL DATA Rth j-amb Rth j-plns Rtt 572 Thermal resistance junction-ambient Thermal resistance junction-pins Transient thermal resistance (t = 2sec.) max max max V 100 20 30 L6236 PIN FUNCTIONS NAME I/O FUNCTION 4 FWD/REV 5 INDEX 6 H1 (+) Positive input of differential amplifier on channel 1. Interfaces with Hall Effect sensor, S1, from motor. 7 H1 (-) Negative input of differential amplifier on channel 1. Interfaces with Hall Effect sensor, S1, from motor. 8 H2 (+) Same as pin 3 for channel 2. 9 H2 (-) Same as pin 4 for channel 2. 10 H3 (+) Same as pin 3 for channel 3. 11 GND Ground connection. 12 H3 (-) Same as pin 4 for channel 3. Direction Control. When this pin is low, the motor will run in the forward direction. A high will drive the motor in the reverse direction. Direction is defined by the positive of the sensors in the motor. o 13 Speed control input. Connected to output of PLL in PLL speed control applications. 14 OUT3 15 SENSE 16 OUT2 o Output motor drive for phase 3. Current Sensing. I nput for load current sense voltage "for output stage. o Output motor drive for phase 2. Motor supply voltage. 17 18 Signal pulse proportional to the motor speed. In PLL speed control applications, this is the feedback to the PLL. One pulse per electrical rotation. This is an open collector output. OUT1 o -------------- Output motor drive for phase 1. ~ ~~~~m~~:~~~ ____________ --'3/_7 573 L6236 ELECTRICAL CHARACTERISTICS (Tamb = 25°C; Vs = 12V unless otherwise specified) Parameter Vs Supply voltage Is Quiescent supply current Test Conditions Min. Typ. 10 12 30 Max. Unit V 60 rnA 10 V HALL AMPLIFIERS V CM Common mode voltage range Via Input offset voltage lib Input bias current lio Input offset current 0 Vi = 6V 2 10 mV Vi = 6V 2 10 J.lA Vi = 6V 0.1 J.lA SPEED CONTROL INPUT (Vel Vi Input voltage range lib Input bias current Vic Input clamping voltage 0 Vc < 1 V sens 5 V 5 J.lA 5.9 V FWD/REVERSE INPUT V IH Input high voltage 2 Vs V VIL Input low voltage 0 0.8 V IIH Input high current 10 J.lA IlL Input low current -50 J.lA 0.8 V 10 J.lA -5 HALL LOGIC OUTPUT = 5mA V LO Low output voltage I IL Leakage current VCE = 12V OUTPUT POWER STAGE V sat Total saturation voltage VOS R Output voltage slew-rate V sens Sense voltage range 10 = 0.15A 10 = OAA 10 = 1.0A 0 2.2 2.5 2.7 V 100 V/ms 0.7 V THERMAL SHUTDOWN Tj Junction temperature TH Hysteresis 574 °c 150 30 °c L6236 DESCRIPTION The L6236 is a three-phase brush less motor driver IC containing all the power stages and commutation logic required for a three-phase bidirectional drive. The output current is related to the speed control voltage by: 10 = (Ve -1)/7 Rs Logic signals from the motor's Hall effect sensors are decoded to generate the correct driving sequence according to the truth-table of Fig. 1. The value of the sensing resistor is given by: Rs = (V x -1)/(7 Imax) The direction of rotation.is controlled by the forward/reverse input (pin 1). When this pin is at a low level the motor rotates in the forward direction. where Vx is the full scale voltage of Ve. In this way the Vel lout characteristics can be modified. Note that Vx max is clamped at 5.9V. When one of the push-pull output drivers is activated the upper transistor is always in saturation while the lower transistor is controlled in linear mode to set the desired speed in steady state conditions. The most important feature of the L6236 is slew rate control. With this device a typical value of 0.1V/J.J.s is achieved, reducing EMI to a very low value. In PLL speed control applications the device provides a signal proportional to the motor speed at pin 2 (it is the buffered H1 input). The output of the PLL is connected to the speed control input on the device at pin 10, Ve. In a delta configuration a key feature is threestate operation; when the current is recirculating the corresponding phase driver is switched off and power dissipation is negligible. Current recirculates through the integrated free-wheeling diodes in the acceleration phase and through the motor in steady-state conditions. Torque ripple is also minimized. In addition, a 1V offset is added to the speed demand voltage to match the minimum output on the PLL. The L6236 can also operate with a brush less motor connected in a star configuration, leaving the center floating. An external resistor, Rs , sense the output stage current. The sensing voltage across this resistor is amplified in the device by a factor of 7 to allow a reduction in the voltage drop in the resistor. The Hall inputs are ground compatible comparators and can work with direct active digital Hall signals on three terminals (of the same polarity) and a TTL level on the other three terminals. The amplified sensing voltage is then compared with the speed demand signal from the PLL and the resulting error signal sets the amplifier output accordingly. Fig. 1 - TRUTH TABLE FOR FORWARD ROTATION HALL EFFECT DIFF. INPUT UPPER DRIVER STATUS LOWER DRIVER STATUS 1 = POSITIVE 0= NEGATIVE o =OFF 1 =ON 1 =ON O=OFF H1 H2 H3 UD1 UD2 UD3 LD1 LD2 LD3 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 -------------- iiil ~~t~m~:~JI-------------=..:5/..:..7 575 L6236 Fig. 2 - Timing diagram :°:1:2,3 HALL EFFECTS DIFFER. INPUTS HI ~ II :J·······~·······~······i······· 2,3,4,11, r--~-...:-..-......;.+ ...... L...... L .... :: F:::::::~f:-:::-:::l..:::-:·:-::t:::::t-~~ : ,'. i UDI! LOMER DRIVER LDI !'!-:-+-----i-+--I UD2 --i : LD2 Lq±l : !:. UPPER DRIVER . ~ LD3 -i!-+-+j- - l I' : i j j ~:---t:::::±=:::t-~ -+-1 UD3 ·F ° : ' : : i LJ . j ~ : : . I'.: ~t=t::t-n >--+-----+_-+---1 lOUT! '. '. ...... !" .....! 0 (CH ..I!.i ...... ·t· S-9464 DETERMINING HALL EFFECT SENSOR CODING Fig.3 ~ The L6236 assumes that the positioning of the Hall Effect sensors in a three-phase brush less DC bipolar motor are at 30 intervals. One can imagine two "windows" on the rotor each of which is 90 wide and 180 apart, see fig. 4. As a window passes over a sensor, the sensor output goes high. The timing diagram, fig. 2, shows the waveforms produced. These waveforms must appear at the Hall Effect Inputs of the L6236. Note that the rotation in fig. 3 must be counterclockwise for forward rotation of the motor in whatever manner that is defined for the motor. Fig. 3 is a stylized concept for determining the Hall Effect code pattern and does not reflect the actual direction of rotation of the motor in a physical sense. If a motor is chose whose sensor outputs do not match the L6236 desired input pattern, a signal set conversion must be determined. It is helpful to visualize this by developing a diagram similar to that of fig. 4. 51 For example, let us examine the output pattern of a different type of motor (fig. 4). Assuming 90 windows at 180 intervals, then with respect to fig. 3, a similar diagram, fig. 5, results in sensors 60 apart with the windows rotating clockwise. The situation results in a "forward" rotation of the motor. ~6~/7_______________________ ~~~~~~~~~l~~~ 576 53 __________________________ L6236 Since S3 is the first sensor encountered by the window in fig. 5, this should be used for the L6236 Hall Effect Input H1. After 30 of rota· tion CW, the H2 input of the L6236 must go high. The inverse of S1 from the motor would satisfly this. After an additional 30 of rotation, the H3 input must go high. The S2 sensor is encountered by the window. Thus, S2 is applied to this input, H3. By countinuing around the dia· gram, one can 'develop a pattern which matches that for the L6236. Fig.5 53 ,I 52 / --------~~-L---~--S1 ~-9483 Fig.4 Thus the coriversione table for th is particu lar motor is: 51 Motor Sensors 52 S3 S1 S2 53 o 90 180 L6236 inputs H1 H2 H3 Note, for the inverted signal from S 1 actual inverter gate is not necessary with the L6236. Since the L6236 has differential inputs, the nega· tive input pin may be used. Therefore, with TTL compatible Hall' Effect sensors, the positive input is connected to a reference point along with the other negative inputs. 270 ANGLE OF ROTATION Fig. 6 - Application circuit using the L6233 PLL-Controller LOCK INDICATION OUTPUT' r---------~------~------------~~---o.VS lO,..F ~ O,22~F lKtl S10n " I '0nF L6233P .., 12 r-~-------t 13 14 15 lMtl 91K1l Q.47pF 30Kn 27Dtr4n ___________________________ SKG ~!~~~~~~:~~~ __________________________ 7~/7 577 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L6495 HIGH SPEED OPERATIONAL AMPLIFIER ADVANCE DATA • SUITABLE FOR VIDEO APPLICATIONS • SLEW RATE 150 V/us (AV = 20 dB AND Iset = 100 ~A) • UNITY GAIN BANDWIDTH (45 MHz TYP) • LARGE SIGNAL BANDWIDTH (20 MHz TYP) • LOW NOISE (5 nV/ 'fRZ) • LOW OFFSET VOLTAGE • PROGRAMMABLE OUTPUT PEAK CURRENT • NO EXTERNAL COMPENSATION FOR AV = 20 dB OR HIGHER ------~-----·-----I I TO-99 (8 Pins) MINIDIP DESCRIPTION (plastic) The L6495 is a high performance monolithic operational amplifier with wideband and high slew rate. The frequency compensation is built into the chip for closed loop gain higher than 20 dB. Large gain bandwidth product and high slew rate make the L6495 ideally suited for wideband signal amplification or switching, in video gain blocks, line driver circuitry, driving capacitive loads and generally for all high frequency applications. ORDER CODES: L6495 (T099) L6495 DP (MINIDIP) The L6495 is available in both minidip and metal can 8 pin. BLOCK DIAGRAM +SU INPUT HI0nF 750hm I I -SU 18pF BBLtj4~5-5Z ~~~m1~8 1ffi This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 579 L6495 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vs Supply Voltage Vis Differential I nput Voltage Vi Input Voltage 10 Output Current Value Unit ± 10 V ±7 V -Vs-0.5 + V s + 0.5 V V ±100 mA o to Top Operating Temperature Ptot Power Dissipation at T amb = 70 DC Minidip TO-99 70 'C 600 500 mW mW Tj Junction Temperature - 55 to 150 °C Tstg Storage Temperature - 55 to 125 °C THERMAL DATA Thermal Resistance Junction-amb Max TO-99 Minidip 155°C/W 120°C/W CONNECTION DIAGRAMS Q COMP tUs NC IN- INt 3 4 OUT ISET -Us 88L6495-C1 2/6 580 NC ININt -Us 1 8 COMP 2 7 +Us 3 6 4 5 OUT ISET 88L5495-C2 L6495 ELECTRICAL CHARACTERISTICS (T amb specified) = 25 "C ; Vs = ± 5 V ; Iset = 100 [LA ; unless otherwise Min. Typ. Max. ±3 ± 5 ± 9 V NO LOAD 10 12 mA 8 10 Input Resistance Av = 20 dB 100 Gin Input Capacitance Av = 20 dB 5 Vas Offset Voltage 11 Vas Average Offset Voltage Drift Symbol Supply Voltage Is Supply Current Ib Input Bias Current Rin -- I1T Test Conditions Parameter Vs o to 70 cC Common Mode Voltage Range I1V o =5V; RL = 2 K!1 Large Signal Bandwidth Av = 20 dB GBW Gain Bandwidth Product Av = 0 dB Ccomp = 18 pF ; eN Equivalent Input Noise Voltage 1 KHz to 500 KHz Vo Output Voltage Swing RL = 2 K!1 10 Output Current B n Ro Output Resistance Open Loop SR Slew Rate Av = 20 dB SR Slew Rate Ccomp = 18 pF Av = 0 dB 30 pF 5 mV 10 30 !lV/DC 1 !lA ± 3 Open Loop Voltage Gain Gv !lA K!1 2 Offset Current los VCM Unit V 72 dB 20 MHz 45 MHz 5 nVIVHz ± 4 V ± 20 ± 30 mA 30 n 100 150 V/!lS 40 V/!lS CMRR Common Mode Reject. Ratio 70 dB SVR + RATIO Power Supply Rejection (positive supply) 70 dB SVR RATIO Power Supply Rejection (negative supply) 60 dB tr n Test Rise Time Av = 20 dB 20 ns CirCUit of Fig. 4. 3/6 581 L6495 Figure 1 : Output Current vs. 15et. 88L6495-D1 10 ImA ) 45 ./v 413 35 ....- V / / V 313 58 75 125lsetluA) 11313 Figure 2: Non Inverting Amplifier Configuration (AV = 20 dB). 'Us I HHlnF 3 OUT Uin -Us 88L6495-53 4/6 582 L6495 Figure 3: Buffer Configuration (AV = 0 dB). +Us HIBnF I OUT Uin nF I I 18pF -Us 88L6495-54 An external compensation capacitor at pin 8 is needed if the loop gain of the operational amplifier is less then 8. Figure 4: Bandwidth Test Circuit (closed loop gain of the L6495 ~~~~~~~~~~~~~~~~--- .---~--.------o = 20 dB). ..- - . - -.. ~~~--~~~~-- .... - - -.. -- +5V INPUT }---__.....--<> • 1 V OUT 750hm 188nF :c: R2 -su 88L5495-51 ~__._ _~_____ .-.J 5/6 583 L6495 Figure 5: Bandwidth Test Circuit (closed loop gain of the L6495 = 0 dB). +SU 750hm CABLE ¥---~~--~--~ OUT 750hm INPUT 1H{3nF !1U I I -5U 1BPF 88L6495-57 ---------------------- 6/6 584 L6503 ~~- ~~- l ---~-~-~--~~----------- HAMMER SOLENOID CONTROLLER PRELIMINARY DATA • DRIVES FOUR DARLINGTONS WITH UP TO 2.5 mA DRIVE CURRENT • FEEDBACK lOOP CONTROLS DARLINGTON CURRENT • PRESETTABlE CONDUCTION TIME • lATCHED IlC-COMPATIBlE INPUTS • DIAGNOSTIC CIRCUITRY DESCRIPTION Designed primarily for selenoid driving applications, the l6503 Hammer Solenoid Controller includes all the circuitry needed to control four darlington power devices or a quad darlington array such as the SGS l7180. The device is controlled by four latched logic inputs, which may be connected directly to a microcomputer chip, plus an analog input which sets the load current. Additionally, the conduction time of the outputs is controlled by a clock input which drives internal timers. Fault conditions may be detected thanks to diagnostic circuitry which allows the control micro to read (serially) the load current status of the extemal darlingtons. Assembled in a 20-pin DIP package, the l6503 operates on a single 5 V supply and is suitable for computer printers, solenoid valves and similar applications. 1------- -~- ~- ---- --- -~ DIP-20 Plastic (0.4) ORDER CODE: L65CJ3 ~----~----~- -~~-- -- --~ -- CONNECTION DIAGRAM (top view) ----~ DATA --- ---- --~~ Vss ---I i I I September t988 VREF 2 ClK DEC2 3 DEC4 DEC1 4 DEC3 IN 5 OUT CDE2 6 CDE4 RM2 7 RM4 CDE1 8 CDE3 RM1 9 RM3 GND 10 DROP I 1/5 585 L6503 BLOCK DIAGRAM ~ r;:=::=:=:t:;~~-~ I IN 16 DROP 11 OUT L6503 5-9174 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vss Supply Voltage 7 V ICDE Output Current 10 mA Vi Top T stg , Tj Input Voltage (for analog and logic inputs) Operating Temperature Storage and Junction Temperature OtoV ss -O.5 V o to 70 cC - 40 to 150 °C THERMAL DATA Thermal Resistance Junction-ambient 2/5 586 Max 80 L6503 PIN FUNCTIONS DESCRIPTION N° Function Name 1 DATA latches control command into the four inputs DEC1-DEC4 on the high-low transition. 2 Vref Analog reference input which sets the load current for all four channels; when lower than 0.5 V resets the logic circuitry. 3 DEC2 Data input for channel 2. Data is latched on the high-low transition of the DATA input. 4 DEC1 Data Input for Channel 1. 5 IN Input for diagnostic shift register used to cascade several device. 6 CDE2 Channel 2 output (connect to base of darlington). Up to 2.5 rnA drive. 7 RM2 Feedback input from sensing resistor of channel 2 darlington. 8 CDE1 Channel 1 Output. 9 RM1 Feedback input for channel 1 sense resistor. 10 GND Ground. Clock Input for Diagnostic Register. 11 DROP 12 RM3 Feedback input for channel 3 sense resistor. 13 CDE3 Channel 3 Output. 14 RM4 Feedback input for channel 4 sense resistor. 15 CDE4 Channel 4 Output. 16 OUT Output of Diagnostic Register. 17 DEC3 Input for Channel 3. 18 DEC4 Input for Channel 4. 19 ClK Input for clock signal which sets conduction time for all four channels. Ton = 128/fcLK . 20 Vss 5 V Supply Input Voltage. FUNCTIONAL DESCRIPTION The L6503 Hammer Solenoid Controller is designed to control a quad darlington array, such as the SGSTHOMSON l7180, in solenoid driving applications. Compatible with 5 V microcomputer and peripheral chips, the L6503 is controlled by four logic inputs one per channel (DEC1 - DEC4) - which are latched by a high-low transition on the DATA input. When one of the channels is activated the corresponding darlington is driven, with up to 2.5 mA drive current. The conduction period is determined by the frequency applied to the ClK input which clocks the 7-bit timer in each channel. The conduction time is therefore 128/fClK. Typically the ClK frequency will be of the order of 100KHz but the l6503's internal logic will operate at any clock rate within the range of practical conduction times. darlington's emitter and set by the voltage applied to the Vref input. The current depends on both the values of Vref and the sensing resistor: I = Vref/Rsense. The control microcomputer may verify correct operation of the complete drive subsystem thanks to a diagnostic circuit in the L6503. A four bit PISO shift register in the device monitors the feedback signals from the four output darlingtons and may be read serially after each command to check that the loads were driven. Typically, this register, clocked by the DROP input, will be read a short time after each drive command has been latched into the device. The input of this register (IN) is available externally so that multiple devices may be cascaded. During the conduction period the load current is controlled by feedback from a sense resistor in the 3/5 587 L6503 ELECTRICAL CHARACTERISTICS (Vss Symbol 5 V , Tamb Parameter = Test Conditions Min. Typ. Max. 0 to 70°C 4.75 5 5.25 V 75 90 mA Vss Supply Voltage Ti Iss Total Supply Current ICDE = 2 mA All Channels On = VREF Input Voltage Reference VREF Reset Logic Function IREF Input BIAS Reference Current VREF Input Voltage (pin 1, 3, 4, 5, 11, 17, 18, 19) ViL Vi Vout Output Logic Voltage (pin 16) 25°C, unless otherwise specified) = Unit 1 2.4 V 0.3 0.65 V -5 fIA o to 2.4 V 0.4 V 2.7 ViH VOL lOUT mA = VOH lOUT =- 0.4 + 1.6 V 100 2.7 f1A Ib Ib ICDE - 100 Input Bias Current (pin 1, 3, 4, 5, 11, 17,18,19) V,L Input Bias Current (pin 7, 9, 12, 14) 1 <: VRM <: 2.4 V Output Current (pin 6, 8, 13, 15) VOUT Output Voltage Range (pin 6, 8, 13, 15) VOL Error Amplifier Input Offset Voltage 1 V <: VREF <: 2.4 V ± 10 V,H = Vss - 0.5 V VOH - 100 2.5 fIA fIA mA 0.2 V Vss - 0.5 ± 10 mV 0.8 1.5 fIs 7 10 TIMING SECTION Data Ability Time t Data to CDE Delay Time t1 (1) Clock 10 CDE Delay Time t2 (1) Reset Time 13 160 =0 V VRM = 0 V VRM 1.9 Reset to CDE Delay Time t4 (1) 1.3 fIs 100 KHz 3 fIs 500 KHz Resel to Output Delay Time 18 (1) 1.3 fls Drop 10 in Delay·Time 19 (1) 1.0 fls Low Level Clock Stale t5 (1) 500 Drop Frequency Low Level'Drop State t7 (1) 100% Tested 588 fIs fIs Clock Frequency RM to OUT Delay Time 16 (1) 4/5 ns ns ns 500 L6503 Figure 1 : Application Diagram. +V •• ~ - 4 10 aND DEC2 3 111 CDE4 S!I 20 2 ·L71BO 17 13 CDE3 ... 1 ClK ~ L6503 la DRDP~ ~ OUT , CDE2 7 CDEI 1 6 II 14 16 9 I ......J 6 11 12 14 7 I [ • ~ ~ ~ .J a 18 DATA 13 '.} ' DEC3 L--. +V y+VREF IDEC1 • -DEC4 AlP y 10 6 I*i ...JT~ ... 4 2 B 1 S-9Z75 RM4 RMI [) ) 1 I Figure 2 : Timing Diagram. REF ~ -,L--......J I~-------------------Ij I DEC(n) DATA ~ CDE(n) 'lLI---,...------.::~:.:..:....------ --Tl--- 1.J;'-"'---'U 1---.~ '6 RM 4 DROP Q4 'I I"' U L-~ -1'>; ~S~---~ ~ L !:o-911611 5/5 589 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L6504 SOLENOID CONTROLLER PRELIMINARY DATA wheel printers and typewrites. The device is controlled by three logic inputs and features switch mode regulation of the load current. A key feature of the device is that the rise and fall time of the load current can be set by external components. Additionally an analog input allows the load current to be set by an external DC Voltage. An undervoltage lockout circuit guarantees the output off state for switch on phase. • SWITCH MODE CURRENT REGULATION • TTL COMPATIBLE LOGIC INPUTS • DRIVES ONE OR TWO EXTERNAL POWER TRANSISTORS • VERY PRECISE ON-CHIP REFERENCE • ANALOG CURRENT CONTROL INPUT • ADJUSTABLE CURRENT RISE AND FALL TIME~CONTROL INDEPENDENT OF SOLENOID SUPPLY VOLTAGE • UNDERVOLTAGE LOCKOUT DIP-14 Plastic (0.25) DESCRIPTION Designed for use with one external power transistor, the L6504 drives the hammer solenoid in daisy- ORDER CODE: L6504 BLOCK DIAGRAM + VS +VSS 10 LJ 1 CDNTROL'-+-- SOLENOID 2 ENABLE ~--~~----4---~~-' 3 ENABLE - , + - - ' CURRENT SENSE REF OUT REF IN ~-9393 5 R2 CURRENT RISE TIME ADJUST September 1988 B C1 :r: RISE AND FALL TIME CURRENT RISE TIME ADJUST 1/7 591 L6504 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vs Value Unit 10 V - 0,3 to 7 V V DC Supply Voltage V 2 ,3 Enable Input Voltage Range V, Control Input Voltage Range - 0,3 to 7 Vg Sense Voltage - 0,3 to 2 V 16 Reference Output Current 2 mA V11 External Reference Voltage 2 V T stg Storage Temperature - 55 to 150 °C Tj Junction Temperature - 55 to 150 Top ° Operating Temperature to 85 CONNECTION DIAGRAM (top view) \.../ CONTROL [ 1 14 ~ ENABLE [ 2 13 ~ ENABLE [ 3 12 ~ Rl [ 4 11 ~ REF, IN R2 [ 5 10 ~ SUPPLY VOLTAGE REF. OUT [ 6 9 ~ SENSING C2 [ 7 8 ~ Cl GROUND NPN DRIVING OUTPUT PNP DRIVING OUTPUT 5-9364 THERMAL DATA Max 2/7 592 100 'C °C L6504 PIN FUNCTION N° Function Name 1 CONTROL TTL Compatible Control Input. A low level activates the output, driving the load. Internal Pull-up Resistor. TTL Compatible Enable Input. A low level disables the output stage. 2 ENABLE 3 ENABLE TTL Compatible Enable Input. A high level disables the output stage. 4 R1 The value of this resistor (') sets slope of trailing edge of load current. 5 R2 The value of this resistor (') sets slope of leading edge of load current. 6 REFERENCE OUT Output for Internal Reference Voltage. 7 C2 The value of this capacitor sets the duration of power transistor switch off time. S C1 The value of this capacitor sets slope of leading and trailing edge of load current. 9 SENSING Connection for Load Current Sense Resistor. Value sets the maximum load current: I = Vref/Rs. 10 SUPPLY VOLTAGE Supply Voltage Input. 11 REFERENCE IN Input for External Reference Voltage to Control Load Current by DC-level. 12 PNP DRIVING OUTPUT Output to Control External PNP-transistor for Fast Current Discharge. 13 NPN DRIVING OUTPUT Output for Basecharge and Discharge of External Power Transistor. 14 GROUND Ground (') Value between 10 kn and 200 kn (or open). 3/7 593 l L6504 ELECTRICAL CHARACTERISTICS N° Symbol 1. Vs Operating Supply Voltage 10 2. Vsth Supply Voltage Threshold For Output Switch· off 10 VCH = LOW VE = HIGH Parameter Pin Test Conditions Min. 2.96 3. Is Quiescent Current 10 Pin 1 Highstate 4. VCl Control Voltage 1 Low State 5. VCH Control Voltage 1 High State 2.3 6. ICl Control Input Current 1 Vt Low State - 1 1 Typ. 4.5 Vt High State 3.7 7 ICH Control Input Current VEL Enable Voltage 2/3 Low State 9. VEH Enable Voltage 2/3 High State 10. liN Input Current 2/3 V2,3 Low State -10 11. liN Input Current 2/3 V2,3 High State -1 12. VOL Driving Voltage Low 13 RI3,14=5K Low State 13, 10 Driving Current 13 Vt3 = 2 V 6.5 14. VSE Sense Voltage 9 15. Vref Reference Voltage 6 16 = o. " 2 mA 1.28 Unit 10 V 4.45 V 12 mA 1.5 V 0 mA V 0.6 7. 8. Max. 5 uA 1.5 V 1 ~A 5 ~A V 2.3 0.5 V 10 16 mA 2 V 1.33 1.38 V 2 mA 0 16. Iref Reference Current 6 17. VRIN Reference Input 11 18 . ICB Charge Current 8 R2 (Pin 5) = 20 K Pin 1L 58 19. lOB Discharge Current 8 Rl (Pin 4) =20 K PinlH 20. Iso Source Current 12 V t2 =2V 21 . V sats Source Saturation Voltage 12 Isource = 0.5 mA 1.2 V 22. Vsats Sink Saturation Voltage 12 Isink = 2 mA 0.4 V 23. VV-I 24. tr Recirculation Time of Load Current 7 25. to Current Sense Delay Time 9 4/7 594 VI-Converter Voltage 4/5 0.3 10K < Rl, 2 < 200 K Rl = R2 C2 = 1.5 ns R2 = 20 Kohm 2 V 65 72 ~A 28 32.5 37 ~A 0.5 1 1.6 mA 1.26 1.32 1.4 V 27 30 33 ~s 0.3 1 2.5 ~s L6504 Figure 1 Timing Diagram Start Phase. Vel (Pin 81 ,·"t~ .. t S- 9365 APPLICATION INFORMATION Figure 2 : Free Running Load Current Leading and Trailing Edge. Figure 3. +VSS SOLENOID 9 L6504 CURRENT SENSE 6 \ \ REF OUT/IN L - - ,_ _. - - . - - - ' SWITCH OFF SLOPE DUE TO COIL TEMPERATURE , COLD HOT' 11 .... - 14 5-10575 CURRENT RISE TIME ADJUST CURRENT FALL TIME ADJUST 5-9394 5/7 595 L6504 Figure 4 : Slew Rate of Loading Edge Controlled. ---1 Figure 5. +VSS RISE AND FALL TIME ) SOLENOID L6504 9 CURRENT SENSE REF OUT/IN 11 '-----,---,--,.--' 14 CURRENT RISE TIME ADJUST H CURRENT FALL TIME ADJUST S-9395 J PIN 1 .t ~----------------------~ Figure 6 : Slew Rate Leading and Trailing Edge Controlled. - _ .__..._ - - - - - - - - - Figure 7. ~~~~~~~---, +VSS RISE AND FALL TIME l..J SOLENOID 1 L6504 9 CURRENT 6 SENSE REF OUT/IN '---.------y--,-' 11 14 CURRENT RISE TIME ADJUST 617 596 5-10671. CURRENT FALL TIME ADJUST ~-9J96 L__ ---_. ___ 1 L6504 Figure 9. Figure 8 : Free Running Leading Edge Fast Current Slope at Trailing Edge. + vs ~--+-tf:~ L6504 6 NPN RS I REF OUT/IN I L-__r -__- ,__-r~11 ~ 14 CURRENT RISE TIME ADJUST CURRENT FALL TIME ADJUST S·9J97 "---_~ .-t _ _.>.S·'""C!.3.fL67L__ _ ... _ _ _ _ _ _ _ _ _ •_ _ _ _ _ _ J 7/7 597 I I I I I I I I I I I I I I I I I I I L6506 CURRENT CONTROLLER FOR STEPPING MOTORS PRELIMINARY DATA DESCRIPTION The L6506 is a linear integrated circuit designed to sense and control the current in stepping motors and similar devices. When used in conjunction with the L293, L298, L7150, or L7180, the chip set forms a constant current drive for and inductive load and performs all the interface function from the control logic thru the power stage. DIP-18 Plastic Two or more devices may be synchronized using the sync pin. In this mode of operation the oscillator in the master chip sets the operating frequency in all chips. ORDER CODE: L6506 BLOCK DIAGRAM Vcc '8 INIU---~5~----------------~~ OUT 1 IN2U---~6~----~--------~~~ OUT 2 INJo---~------~--------~~~ l-+-~n IN4U---~8------4---~----~~~ '1 OUTJ OUT 4 POWER ENABLE VSENSE 2 REF. 2 SYNC VSENSEI REF. I R/Co--~-+---I osc. September 1988 GND 5-'283/3 1/5 599 L6506 CONNECTION DIAGRAM (top view) RIC 1 18] Vec osc. 2 17] REF 2 SYNC 3 16 ] REF 1 ENABLE 4 15) VSENSE 2 IN 1 5 14 ] OUTl IN 2 6 13] OUT 2 IN 3 7 12 ] OUT3 IN 4 e 11 ] OUT 4 9 10] VSENSE 1 POWER GND I 5-928412 ABSOLUTE MAXIMUM RATINGS Value Unit Supply Voltage 10 V Input Signals 7 V Total Power Dissipation (T amb = 70°C) 1 W Parameter Symbol Vee VI Ptot Tj Junction Temperature 150 °C T stg Storage Temperature - 40 to 150 °C THERMAL DATA Max 80 ELECTRICAL CHARACTERISTICS (Vee = 5.0 V, T amb = 25 'C ; unless otherwise noted) Symbol Vcc Icc Parameter Test Condtions Quiescent Supply Current Min. Typ. 4.5 Supply Voltage Vcc = 7 V Max. Unit 7 V 25 mA COMPARATOR SECTION VIN Input Voltage Range V sense Inputs VIO Input Offset Voltage VIN=1.4V Curre~t 110 Input Offset liB Input Bias Current Response Time 2/5 600 - 0.3 VREF = 1.4 V VSENS = 0 to 5 V 0.8 3 V ± 5.0 mV ± 200 nA 1 j.!A 1.5 ~s L6506 ELECTRICAL CHARACTERISTICS (Continued) ! Symbol! Parameter ! Test Conditions Min. ! Typ. ! Max. ! Unit ! COMPARATOR SECTION PERFORMANCE (over operating temperature range) Input Offset Voltage V 1N =1.4V Input Offset Current LOGIC SECTION(over operating temperature range) - (TTL compatible inputs & outputs) 2.0 VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage Vec = 4.75 V IOH = 400 IlA VOL Ouptut Low Voltage Vce = 4.75 V IOH = 4.0 mA IOH Ouput Source Current Outputs 1 - 4 Vcc = 4.75 V 2 Vs V 0.8 V 3.5 0.25 V 0.4 2.75 V mA OSCILLATOR 70 5 fosc Frequency Range VthL Lower Threshold Voltage 0.33 Vec VthH Higher Threshold Voltage 0.66 Vec Ri I nternal Discharge Resistor CIRCUIT OPERATION The L6506 is intended for use with dual bridge drivers, such as the L298, quad darlington arrays, such as the L7180, or discrete power transistors to drive stepper motors and other similar loads. The main function of the device is to sense and control the current in each of the load windings. A common on-chip oscillator drives the dual chop- per and sets the operating frequency for the pulse width modulated drive. The RC network on pin 1 sets the operating frequency which is given by the equation: 1 f = 0.69 RC for R > 10K The oscillator provides pulses to set the two flipflops which in tu m cause the outputs to activate the drive. When the current in the load winding reaches the programmed peak value, the voltage across the sense resistor (Rsense) is equal to V,el and the corresponding comparator resets its flip-flop interrupting the drive current until the next oscillator pulse occurs. The peak current in each winding is programmed by selecting the value of the sense resistor and V,el. Since separate inputs are provided for 0.7 1 KHz V V 1.3 Kn each chopper, each of the loads may be programmed independently allowing the device to be used to implement microstepping of the motor. Lower threshold of L6506's oscillator is 113 Vee. Upper threshold is 2/3 Vce and internal discharge resistor is 1 KQ ±30 %. Ground noise problems in multiple configurations can be avoided by synchronizing the oscillators. This may be done by connecting the sync pins of each of the devices with the oscillator output of the master device and connecting the RIC pin of the unused oscillators to ground. The equations for the active time of the sync pulse (T2) , the inactive time of the sync signal (T1) and the duty cycle can be found by looking at the figure 1 and are: T2 = 0.69 Cl R1 RIN (1 ) Rl + RIN T1 = 0.69 R1 C1 T2 DC = T1 + T2 (2) (3) 3/5 601 L6506 By substituting equations 1 and 2 into equation 3 and solving for the value of R1 the following equations for the external components can be derived: R1 1 = (DC -2) RIN T1 C1 = 0.69 R1 (4) (5) Looking at equation 1 it can easily be seen that the minimum pulse width of T2 will occur when the value of R1 is at its minimum and the value of R1 at its maximum. Therefore, when evaluating equation 4 the minimum value for R1 of 700Q (1 KQ - 30 %) should be used to guarantee the required pulse width. Figure 1 : Oscillator Circuit and Waveforms. SYNC. RIC I T2 I T1 5-9568/1 5-9567 APPLICATIONS INFORMATION The circuits shown in figures 2 and 3 use the L6506 to implement constant current drives for stepper motors. Figure 2 shows the L6506 used with the L298 to drive a 2 phase bipolar motor. Figure 3 shows the L6506 used with the L7180 to drive a 4 phase unipolar motor. The peak current can be calculated using the equation: I Vref peak = Rsense The circuit of Fig.2 can be used in applications requiring different peak and hold current values by modifying in the reference voltage. 4/5 602 The L6506 may be used to implement eitherfull step or half step drives. In the case of 2 phase bipolar stepper motor applications, if a half step drive is used, the bridge requires an additional input to disable the power stage during the half step. If used in conjunction with the L298 the enable inputs may be used for this purpose. For quad darlington array in 4 phase unipolar motor applications half step may be implemented using the 4 phase inputs. The L6506 may also be used to implement microstepping of either bipolar or unipolar motors. L6506 Figure 2 : Application Circuit Bipolar Stepper Motor Driver. 5V 36 V o lrl paR 18 POWER ENABLE 4 .....+-+·-+~ z~ 14 13 PHASE INPUTS 6 5V 12 10 11 l2 L 298N 13 14~+-~-r~~ 6 15 8 I I I I _ _ .• _ _ _ _ _ ..J Figure 3 : Application Circuit Unipolar Stepper Motor. 36V 5V ~.WER ENABLE 18 14 4 5 13 PHASE INPUTS 5V L 7180 12 L6506 11 11 15 .J.. 5/5 603 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I L6570A L6570B 2-CHANNEL FLOPPY DISK READ/ WRITE CIRCUITS - - - - - • TWO GAIN VERSIONS (A AND B) • COMPATIBLE WITH 8", 5.25" AND 3.5" DRIVES. • INTERNAL WRITE AND ERASE CURRENT SOURCES, EXTERNALLY SET • INTERNAL CENTER TAP VOLTAGE SOURCE • CONTROL SIGNALS ARE TTL COMPATIBLE • TTL SELECTABLE WRITE CURRENT BOOST • OPERATES ON + 12VAND+5 V POWER SUPPLIES - - - - --_.._ - - _ _ - - - - - .. tures a gain of 85 min and the L6570B of 300 min. All logic inputs and outputs are TTL compatible and all timing is extemally programmable for maximum design flexibility. ~--.------ ..... DIP-28 Plastic DESCRIPTION The L6570N B are integrated circuits which perform the functions of generating write signals and amplifying and processing read signals required for a double sided floppy disk drive. The L6570A fea- ORDER CODES: L6570A L6570B BLOCK DIAGRAM September 1988 1/7 605 L6570A-L6570B ABSOLUTE MAXIMUM RATINGS Symbol Test Conditions Unit Vcc 5V Supply Voltage Parameter 7 V V DD 12V Supply Voltage 14 V T stg Storage Temperature - 65 to 150 °C °C °C Tamb Ambient Operating Temperature Tj Junction Operating Temperature VI Ptot o to + 70 o to + 130 Logic Input Voltage Power Dissipation - 0.5 to 7.0 V 500 mW CONNECTION DIAGRAM (top view) +HOO Vee -HOO +AO +HOI -AO -HOI +IN CB -IN Rw GI ReCe 62 Re 01 Vdd 02 Vet RiW' RDP HSO/HSI VOl PW EI TO GNO EO 5-9518 THERMAL DATA Max 2/7 606 ~ a...,I SGS·ntOMSON IliIOICII©mIl.E1I'IIl@i!In«:i11 100 L6570A-L6570B ELECTRICAL CHARACTERISTICS (unless otherwise specified, 4.75V $ Vcc $ 5.25V ; 11.4V $ Voo 12,6V ; 0 'C $ Tamb $ 70 'C; Rw = 430 Q ; REO = 62 KQ; C E = 0.012 /IF ; REH = 62 KQ ; R Ec =220Q) $ I Symbol I Test Condtions Parameter I Min. I Typ. I Max. Unit I POWER SUPPLY CURRENTS Icc 5V Supply Current Read Mode Write Mode 35 38 rnA rnA 100 12V Supply Current Read Mode L6570A L6570B 26 35 rnA rnA Write Mode (exclude Write and Erase L6570A currents) L6570B 24 35 rnA rnA LOGIC SIGNALS-READ/WRITE (R/W), CURRENT BOOST (eB) VIL Input Low Voltage IlL Input Low Current VIH Input High Voltage IIH Input High Current VIL = OAV VIH = 2AV 0.8 V - OA rnA 20 /lA V 2.0 LOGIC SIGNALS-WRITE DATA INPUT (WDI), HEAD SELECT (HSO/HS1) VT+ Threshold Voltage, Positive-going lA 1.9 V VT- Threshold Voltage, Negative-going 0.6 1.1 V OA VT+, VT- Hysteresis IIH Input High Current VIH IlL Input Low Current VIL = 2AV = OAV V 20 !lA - 0.4 rnA Voo-O.5 V CENTER TAP VOLTAGE REFERENCE VCT Output Voltage Iwc + IE = 3 rnA to 60 rnA Voo-l.5 Vcc Turn-Off Threshold 4.0 Voo Turn-Off Threshold 9.6 VCT Disabled Voltage V V 1.0 V ERASE OUTPUTS (E1, EO) Unselected Head Leakage VEO. VEl = 12.6V IE =50 rnA 3/7 607 L6570A-L6570B ELECTRICAL CHARACTERISTICS (Continued) ISymbol I Parameter. Min. Test Conditions Typ. Max. Unit WRITE CURRENT Unselected Head Leakage VE1 , VEO = 12.6V Write Current Range Rw = 820 Q t0180 Q Current Reference Accuracy Iwc = 2.3/R w VCB (current boost) = O.5V 25 jlA 3 10 mA -5 +5 % 1.0 Write Current Unbalanced Iw c = 3 mA to 10 mA Differential Head Voltage Swing Lllwc"; 5 % 12.8 Current Boost VCB = 2.4V 1.25 1wc 1.35 1wc % Vpk ERASE TIMING Erase Delay Range RED = 39 KQ to 82 KQ CE = 0.0015 j.!F to 0.043 j.!F 0.1 1.0 ms Erase Delay Accuracy TED = 0.69 RED CE RED = 39 KQ to 82 KQ CE = 0.0015 j.!F to 0.043 j.!F -15 +15 % REH + RED = 78 KQ to 164 KQ CE = 0.0015 j.!F to 0.043 j.!F 0.2 2.0 ms T EH = 0.69 (RED + RED) CE REH + RED = 78 KQ to 164 KQ CE = 0.0015 j.!F to 0.043 j.!F -15 + 15 % LlTEO x100% TED Erase Hold Range Erase Hold Accuracy LlTEO TED x 100 % ELECTRICAL CHARACTERISTICS (Unless otherwise specified: sine wave, DC coupled to center tap. Summing amplifier load = 2 VIN (Postamplifier)= 0.2 Vpp sine wave, AC coupled; RG = open; Vee; CD = 240 pF; CTD = 100 pF; RTD = 7.5 KQ; Cpw = 47 pF ; VIN (Preamplifier) =10mVpp KQ line-line, AC coupled. Data pulse load = 1 KQ to Rpw = 7.5 KQ). READ MODE ISymbol I Parameter Test Conditions Min. Typ. Max. I Unit PREAMPLIFIER-SUMMING AMPLIFIER Diff Voltage Gain Freq. = 250 KHz L6570A L6570B Bandwidth (- 3 dB) 4/7 608 85 300 115 400 MHz 3 ± 1.0 Gain Flatness Freq. = DC to 1.5 MHz Diff. Input Impedance Freq. = 250 KHz 20 Max. Diff. Output Voltage Swing VIN = 250 KHz Sine Wave THD,.; 5 % L6570A L6570B 2.5 4.0 Small Signal Difference Output Resistance 10";1.0mApp Common Mode Rejection Ratio VIN = 300 mVpp @ 500 KHz L6570A Inputs Shorted L6570B VN dB KQ Vpp 75 Q dB 50 40 L6570A-L6570B ELECTRICAL CHARACTERISTICS (Continued) I Symbol I Parameter Test Conditions I Min. I Typ. I Max. I Unit I PREAMPLIFIER-SUMMING AMPLIFIER ~Voo ~300 mVpp @500 KHz Inputs Shorted to VCT 50 dB Channel Isolation Unselected Channel VIN ~100 mVpp @ 500 KHz. Selected Channel Input Connected to V CT 40 dB Equivalent Input Noise Power BW ~ 10kHz to 1 MHz Inputs Shorted to VCT Power Supply Rejection Ratio VCT 10 Center Tap Voltage 1.5 ~Vrms V POST AMPLIFIER-ACTIVE DIFFERENTIATOR AO, Dilt. Voltage Gain + IN, . IN to 01, 02 Freq. Bandwidth (- 3d B) +IN,·INtoD1,D2 Co Gain Flatness +IN,·INtoD1,D2 ~ Freq. ~ 250 KHz 0.1 ~ ~F, Ro 8.5 ~ 2.5 KQ 11.5 3 MHz ± 1.0 DC to 1.5 MHz Ro ~ 2.5 KQ VN dB Co~0.1~F, Max. Dilt. Output Voltage Swing VIN ~ 250 KHz Sine Wave, AC Coupled. ,; 5 % THO in Voltage across Co 5.0 Vpp Max. Dill. Input Voltage VIN ~ 250 KHz Sine Wave, AC Coupled. ,; 5 % THO in Voltage across Co, RG ~ 1.5 KQ 2.5 Vpp Dill. Input Impedance Gain Control Accuracy ~AR -----x 100 % KQ 10 AR ~ AoRG/(8 x 103 + RG) RG ~ 2 KQ - 25 + 25 % 3.7 mVpp AR Threshold Differential Input Voltage Peak Differential Network Current Min. diff. input voltage at post amp. that results in a change 01 state at RDP V1N ~ 250 KHz square wave, Co ~ 0.1 ~F Ro ~500 Q, T R, T F ,; 0.2 ~. No overshoot; Data pulse lrom each VIN transition 1.0 mA 5/7 609 L6570A-L6570B ELECTRICAL CHARACTERISTICS (Continued) I Symbol Parameter I Test Conditions I Min. I Typ. I Max. I Unit TIME DOMAIN FILTER Delay Accuracy L'.TTD - - x 100 % TTD Delay Range T TD = 0.58 RTD . (CTD + 10 .11) + 150 ns. RTD = 5 KQ to 10 KQ CTD = 56 pF VIN = 50 mV pp @ 250 KHz sq. wave T R, T F <; 20 ns, AC coupled. Delay measured from 50 % input amplitude to 1.5 V data pulse - 15 + 15 % TTD =0.58 RTD = (CTC + 10- 11 ) + 150 ns. RTD = 5 KQ to 10 KQ CTD = 56 pF to 240 pF RD = 500 Q CD = 0.1 !1F. 240 2370 ns Tpw =0.58 Rpw x (Cpw + 8 X 10- 1 2) + 20 ns Rpw = 5 KQ to 10 KQ Cpw ? 36 pF with measured at 1.5V amplitudes - 20 + 20 % 0.5 V 1225 ns DATA PULSE Width Accuracy L'. Tpw -----x 100 % Tpw Active Level Output Voltage 10H = 400 !1A Inactive Level Output Leakage 10L = 4 mA Pulse Width T pw = 0.58 Rpw x (C pw + 8 x 10. 1 2) + 20 ns Rpw = 5 KQ to 10 KQ Cpw = 36 pF to 200 pF 2.7 145 V TEST SCHEMATICS Figure 1 : Preamplifier Characteristics. Figure 2 : Postamplifier Differential Output Voltage Swing and Voltage Gain. Vout 10Kfl S-9546 6/7 610 I L6570A-L6570B TEST SCHEMATICS (Continued) Figure 3 : Postamplifier Threshold Differential Input Voltage. 4~,," 25 f=250KHz SQUARE WARE ----II 24 ~~r 21 02 20 Ro=500n 5-9547 Figure 4 : Complete Test Circuit. ROP HS8/HS1 R/W WOI CB +Ucc UOO Rpw PW 17 18 19 11 12 28 5 9 CPwI Rtd 15 CtdITO 01 Cd L657G 29 21 22 RG 23 G2 24 25 25 27 8 Re Reh 7 E1 ReCe Ice f188L65?8-B3 7/7 611 L6603 L6604 MEMORY CARD INTERFACE ADVANCE DATA • Single Power Supply operation • Internal Clock Generator or External Clock Input • Adjustable Precision of PVS Output Voltage (2 %) • 100 mVlstep of the Writing Output Voltage • 110, Reset and Clock Outputs Protection Against Short Circuit to GND and to V pvs. DIP 28 ORDER CODE: L6603 . .• .• . :. . . QiI DESCRIPTION '-',",,,"'-,",,','.' t";";:":'-";!:,:;-, The L6603 and L6604 are integrated circuits for application as interface between different types of memory card and a microprocessor which excanges data with cards. Its operate with a single power supply. PLCC 28 ORDER CODE: L6604 CONNECTION DIAGRAMS , m Us 110 -,0 / I/O RESET OUT ~ U CK uP w , ;g 0 0 I~'" PWM OUT ENABLE Vcs ENABLE FROM m RESET OUT St , U CK OUT VC5 [NAOl[ DAce XTAL DAel XTAL I*' I*' DAC2 BYPASS 1<, OA[3 Vec8 I*' I*' OAC4 10 VccC DAC5 II VccE DAC6 12 PVSI DAC? 13 PUS AD] GND 14 PUS BBL65B3-Cl Ives '* , [ DAca [ " /:-; 6 " DAC1 7] DAC2 22 OAe) ?1 DAC4 1" OACS 11 ?A 19 12 13 ~ ~ u IT "Q o 0 14 n L [~ 15 m _, C1 16 17 U ([ ::J (J1 ~ m 18 U ,:::>w r:+: l FROM .jp • PLee ,: 1 "","""<0. DIP 28 1/8 September 1988 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 613 L6603/L6604 BLOCK DIAGRAM ., 'U • J PUB ADJ I ! I ."" C2 A I ~ I I IC3 05 Q.< I I I I ,02 i 06 PUS ~CS 21 elI u= 8BL1iMU-BJ ,NOBLE DACHtD7 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Test Conditions V Operating Temperature Range - 20 to 70 °C Storage Temperature Range - 40 to 150 °C Supply Voltage Top T stg THERMAL DATA (*) Thermal Resistance Junction-ambient 2/8 614 Unit 10 Vs Max L6603/L6604 PIN FUNCTIONS Pin Name 1 1/0 2 RESET 3 St 4 CK ENABLE 5 VCS ENABLE 6 to 13 DACO to DAC7 Control Input for Reset of Memory Card FA Function Strobe for Card with Memory (TTL compatible) Commutation for ~P Cards CK ENABLE; 1 (internal clock) Control Input for VCS Supply Voltage Control Inputs for Programmation of Vpvs Supply (see operation of programming supply Vpvs ) 14 GND Ground 15 Vpvs Programmable Supply for Memory Card (no use with decoupling capacitor) Note 7 (to the credit card) 16 Vpvs Adj 17 PVS I 18 19 20 Vcs Vcc E C B 21 BYPASS 22 23 XTAL XTAL 24 CKOUT 25 PWM OUT 26 RESETIOUT 27 1/0 Out 28 Note Note Note Note Note Note Note Note Function Input of the Bidirectional Data Line 1 2 3 4 5 6 7 8 Vs Adjustment Input for 2 % Precision Vpvs Output Input for Vpvs Regulator Inputs for Connection of Power Transistor (V cc regulator) (decoupling capacitor on pin 18 > 100 nF if necessary) Note 8 (pin 18 to the credit card) Output Voltage of Regulator for Clock Circuits (decoupling capacitor> 150 nF). Note 9 Inputs for X-tal Connection. Note 10 Output for Clock Signal (TTL levels). Note 11 (to the credit card) Output for DCIDC Converter Reset Output. Note 11 (to the credit card) Output 1/0. Note 11 (to the credit card) General Power Supply For Inputs V"" enable, Reset, 1/0, St, CK enable DAC (0 - 7). For inputs DAC (0 - 7) For input CK enable For input Reset For input Vvcs enable For input 1/0 Typical internal thermal protection & current limiting system Current limiting with "fold back system" 1,1m max (A); 0.75 V Rlim Note 9 Internal current limiting system Note 10 Input for external clock (fig. 3) Note 11 Output protected against short-circuit to ground and to & Vp", 3/8 615 L6603/L6604 ELECTRICAL CHARACTERISTICS (Vs = 8.5 V; Symbol Parameter V'H Input High Voltage V'L Input Low Voltage I'H Input High Current I'L Tamb = 25 'C unless otherwise specified) Test Conditions Min. Typ. Max. 2 Input Low Current Unit 1 0.8 V 1 250 ~ 2 500 ~ 3 100 (.iA 4 400 ~ 5 - 200 (.iA 6 - 150 (.iA 2 - 300 ~ 3 + 10 ~ 4 - 200 ~ 5 - 300 (.iA 6 Isw Supply Current Writing Mode (pin 28) Vpvs = Vpvsw max tbd mA ISR Supply Current Reading Mode (pin 28) Vpvs = VPVSR tbd mA Ves Output Voltage Range Vs = 7 to 10 V ; les = 0 to - 200 mA ; T amb = - 20 to 70 'C ; 4.8 Load Regulation I es = 0 to - 200 mA 0.18 % Line Regulation Vs = 7 to 10 V ; - 50 dB Temperature Coeff. of Output Voltage Ves T amb = - 20 to 70°C 65 dB tol11 Fall Time of Ves Fig. 1 CL =30 pF 5 25 (.is toff2 Fall Time of Vpvs Fig. 1 CL =30 pF; ~ Vpvs =0.1 V 40 100 (.is Operating Curro Limit Ves=-4%; R 'im = 3 ohm ~ Ves --- 5 5.2 V ~ Ves ~ Ves --- ~ ~ Vs Ves --~ T Ics max - 220 mA - 70 - 100 mA VPVSWMAX Maximum Programming Voltage (writing mode memory) Vs = 7 to 10 V ; Ipvs = 0 to - 50 mA ; 24.5 25.5 26.5 V VPVSWMIN Minimum Programming Voltage (writing mode memory) Vs = 7 to 10 V ; Ipvs = 0 to - 50 mA ; 4.9 5.1 5.3 V Output Voltage Range of PVSP (reading mode memory) Vs = 7 to 10 V ; Ipvs = 0 to - 20 mA ; 4.8 5 5.2 V les1 VPVSR 4/8 616 Short Circuit Current limit Note V L6603/L6604 ELECTRICAL CHARACTERISTICS (continued) Symbol tlVpvs Parameter Test Conditions Min. Typ. Max. Unit Load Regulation Ipvs = 0 to - 50 mA ; 0.8 % Line Regulation Ivps = 0 mA ; Vs = 7 to 10 V 50 dB Temperature coeft. of Ouptut Voltage V PV s Ipvs = 0 mA ; T amb = - 20 to 70 °C 74 dB Note -- Vpvs tlVs --- tlVpvs tlVpvs --- tl T IpvsMAx Vpvs ADJ - Ves Short Circuit Current Limit - 50 Differential Volt. between Vpvs (reading mode) & Ves -5 = 30 pF ; - 65 - 80 mA 5 % 12 50 fls 25 100 fls tpLH1 Turn ON Time of Ves Fig. 1 CL tpLH2 Turn ON Time of Vpvs Fig. 1 CL = 30 pF ; tlVpvs = 0.1 V ton1 Rise Time of Ves Fig. 1 CL = 30 pF ; 10 50 flS ton2 Rise Time of Vpvs Fig. 1 CL = 30 pF; tl Vpvs =0.1 V 30 100 fls 5/8 617 L6603/L6604 ELECTRICAL CHARACTERISTICS (Vs = 8.5 V; ~I-'-------- P;;;;~~te-r-VOH1 I I High Output Voltage (pin 26) Tamb = 25 'C ; unless otherwise specified) Test Conditions (-PIN 26) V;s min ---IOH = - 200ljlA 1- I Mi~-:-r TYp. -,-M~-;-rUnit I I Low Output Voltage (pin 26) (PIN 26) VIH = 2 V ; IOl = + 200ljlA I-------t~-~---------------Max Output Voltage 015 V V L __l. ~r~~;:~h~:_~~~~_~ Isc2 'Short-circuit Curro Limit ~-V~H2' ~;h~~tPu;-VOIt~; I I r-VOl;-tLOW VSC2 ilOl = + 200ljlA VIH min = 0.8 V 1.9 ~~:::~~~vJu;rn:,:~37 1/O-:42V--- I-I .----- I---~----·- 0.9 V VCS + 0.3 V I I ~A-I--1 - 30 (Pin 27) l. _V_O_H_3_+-I-"~"--I~~ ~l~~_~~ta~__ _ VOH4 r- IOH = - 200ljlA ~I~ ~~tPut Voltage 'I~ +-200/~A--- VOL3 = I __ 3.5 IOH = - 10ljlA High Output Voltage +--1 V l I Max Output Voltage durrng Short-circuit I --- O~Put Voltag-e---- ~~smmaa: ~ 2 V (pin 27) mA ~~n-. Vcs IIOH = - 500ljlA (pin 27) i Note -'1-4"-8"---+-----+- V 4-.2 4.1 4.2 . 4.1 T[ 0.1 =1=V -'-~~~,"","-V-0.4 I V Vcs : V . mA I (pin 24) VSC3 -1' Max Output Voltage during Short-circuit between Pin 24 & Vpvs Output I Isc4 ------ ton toll Short-Circuit Curro ,Limit (pin 24) -- - --, -- - - - - - - - " . - - - - - - - - Rise Time of Clock Output (pin 24) Fall Time of Clock Output (pin 24) Duty Cycle (T1/T) L.. 6/8 618 -~Fi9~2 " - fXTAl = 4.91 MHz, CL = 30 pF I-I >::. 15 ns 18 ns I Fig. 2 [.,fXT, AL = 4,.91 MHz; CL = 30 pF fXTAl = 4.91 MHz; CL = 30 pF I I 40 60 I I I L , --iI % I L L6603/L6604 OPERATION OF PROGRAMMING SUPPLY Vpvs The output voltage Vpvs can be programmed from 5 V to 25.5 V by steps of 0.1 V and can be expressed as follows: code DAC 0-7 Vpvs = - - - - - - - - 10 Two operating modes are possible Reading mode (code DAC = 50) : Vpvs = 5 V ; Writing mode (code 51 to 255) : Vpvs = 5.1 to 25.5 V In this case, the voltage drop between output of converter DC/DC (PVSI) and Vpvs is constant and is tipicalIy to 3 V. Figure 1 : Ves and Vpvs Delay Times Versus Ves Enable. -----~·-I Ucs ENABLE ~ ----1--/' Ucs tPLH1~ Upus \~-----:'/~ 981r,j I toff1 181 \ tpLH2~ .~: ~~_ _..JI • toFf2 ~ +-+'-------.: toni I~ ~ ton2 I 88L6683-52 Ctot load = 30 pF. Figure 2 : Clock Output Waveform. ---_._--- I I ~ I ton Ctot load I I ~ . I tofF "l-- \ I .lo------- T1 I ~ 1" __ ~,~., H_J = 30 pF. 7/8 619 L6603/L6604 Figure 3 : Input for External Clock. · 4 8k EXT. J1f CLOCK 23 XTAL 22 XTAL 88L66fi13-S3 _____________ .______ JI ~-------------- Figure 4 : Application Circuit. )w m w " .., .... m w -' ID a: z w >.: u w -' ID a: z w LS8 620 MS8 '------y---J OAe 18 to 71 II u :> ' - - - - - - -_ _ _ _ _ _ 8/8 6.81( 22 - - - - - - - - - - - - - - - - - - _ _ _ _ _ _1 L7150 L7152 50 V QUAD DARLINGTON SWITCHES The L7150 has 350 input resistors and is compatible with TTL, DTL, LSTTL and 5 V CMOS logic. The L7152 has 3 KU input resistors for use with 6-15 V CMOS and PMOS logic. • FOUR NPN DARLINGTONS WITH ISOLATED CONNECTIONS • OUTPUT CURRENT TO 1.5 A EACH DARLINGTON • MINIMUM BREAKDOWN 50 V • MUL TIWATT PACKAGE ALLOWS OPERATION AT 1.5 A, 50 V, 100 % DUTY CYCLE, ALL FOUR DEVICES ON • INTEGRAL SUPPRESSION DIODES • VERSIONS FOR 5 VJl.ND 6-15 V LOGIC FAMILIES These devices are suitable for driving a wide range of inductive and non-inductive loads including DC motors, stepper motors, solenoids, relays, lamps, multiplexed LEOs and heaters. /_._-_ .. _ - _ . I I I Mulliwatt-1S I DESCRIPTION The L7150 and L7152 are 1.5 A quad darlington arrays mounted in the 15-lead Myltiwatt@ plastic package. Each darlington is equipped with a suppression diode for inductive loads and all three terminals are isolated. I ORDER CODES: L7150 L7152 l CONNECTION DIAGRAM (top view) - . - -. . . . • .- .. -~-- _ .. _ _. -$- -- 15 B 4 14 E4 C t.. 13 12 ------ N C. " C3 E 3 10 , 83 GNO 81 I E1 ( 1 I Vs (1 L ___________ Ta_b connected September 1988 El 81 I S-5958/' to~p~in~8~ __ ~ ... _ _ _ .___ ~. __________ J 1/4 621 L71S0-L71S2 ABSOLUTE MAXIMUM RATINGS Symbol Value Parameter Unit VCEX Output Voltage 50 V 10 Output Current 1.75 A VI Input Voltage 30 V 18 Input Current 25 mA Ptot W 25 Power Dissipation (T case = 75°C) Tamb Operating Ambient Temperature Range T stg Storage Temperature o to 70 °C - 55 to 150 °C SCHEMATIC DIAGRAM ____----o----n c s- 5957 L7150 : HN = 3 son L7152 : HN = 3Kn ELECTRICAL CHARACTERISTICS (T amb = 25 'C unless otherwise specified) Symbol Parameter ICEX Output Leakage Current Ij(on) Vj(on) Unit Fig. 100 500 J.lA J.lA 1 V 2 1.15 1.3 1.4 1.5 V V V V 3 4.3 9.6 1.8 5.2 mA mA mA mA 4 Ie = 1 A Ie = 1.5 A 2 2.5 V V 5 Ie = 1 A Ie = 1.5 A 6.5 10 V V T amb = 70°C Ie = 100 mA Vj = 0.4 V Collector-emitter Saturation Voltage Ie Ie Ie Ic 18 18 18 18 =625 J.lA = 935 J.lA = 1.25 mA = 2 mA Input Current forL7150 for L7150 forL7152 forL7152 Vj Vj Vj Vj = 2.4 V =3.75 V =5 V = 12 V VCER (sus) Collector-emitter Sustaining Voltage* VeE (sat) Max. Test Condtions VCE =50 V VCE =50 V Input Voltage = 500 mA = 750 mA =1A = 1.25 A for L7150 VeE = 2 V VeE = 2 V for L7152 VeE = 2 V VCE = 2 V Min. Typ. 35 1.4 3.3 0.6 0.7 tpLH Turn-on Delay Time 0.5 Vj to 0.5 Va 1 Ils tpHL Turn-off Delay Time 0.5 Vj to 0.5 Va 1.5 J.lS 2/4 622 L71S0-L71S2 THERMAL DATA Max Max 3 35 TEST CIRCUIT Figure 1. Figure 2. OPEN s- 59 26 Figure 3. Figure 4. OPEN OPEN 5-1986 5- t960 Figure 5. 5-1967 3/4 623 L71S0-L71S2 MOUNTING INSTRUCTIONS The power dissipated in the circuit must be removed by adding an external heatsink. Thanks to the Multiwatt@ package attaching the heatsink is very simple, a screw or compression spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon grease, to optimize the thermal contact ; no electrical isolation is needed between the two surfaces. Figure 6 : Mounting Example. -~----------~~---- ------------1 I I 4/4 624 L7180 L7182 80 V QUAD DARLINGTON SWITCHES • FOUR NPN DARLINGTONS WITH ISOLATED CONNECTIONS • OUTPUT CURRENT TO 1.5 A EACH DARLINGTON • MINIMUM BREAKDOWN 80 V • MUL TIWATT PACKAGE ALLOWS OPERATION AT 1.5 A, 80 V, 100 % DUTY CYCLE, ALL FOUR DEVICES ON • INTEGRAL SUPPRESSION DIODES • VERSIONS FOR 5 V AND 6-15 V LOGIC FAMILIES The L7180 has 350 n input resistors and is compatible with TTL, DTL, LSTTL and 5 V CMOS logic. The L 7182 has 3 Kn input resistors for use with 615 V CMOS and PMOS logic. These devices are suitable for driving a wide range of inductive and non-inductive loads including DC motors, stepper motors, solenoids, relays, lamps, multiplexed LEOs and heaters. Mu Itiwatt 15 DESCRIPTION The L7180 and L7182 are 1.5 A quad darlington arrays mounted in the 15-lead Multiwatt@ plastic package. Each darlington is equipped with a suppression diode for inductive loads, and all three terminals are isolated. ORDER CODES: L 7180 L7182 ABSOLUTE MAXIMUM RATINGS ,---,------------------------------------------- ----- Symbol Parameter V CEX Output Voltage 10 Output Current Vi Input Voltage --- __________L_~~t Co_n~~ti0l1s I 80 I __ J-l..'lit V 1.75 A 60 V f-----'--f--~-----''-----------------------~---- - - - - - - - - + - - - - - 1 18 Input Current 25 mA Ptot Power Dissipation (T case = 75°C) Tamb Operating Ambient Temperature Range T stg Storage Temperature ------ 25 W o to 70 - 55 to 150 SCHEMATIC DIAGRAM .;-----+---{) C L7180 : RIN = 350 Q L7182 : AiN = 3 KQ 5- 5957 September 1988 1/4 625 I L7180-L7182 CONNECTION AND SCHEMATIC DIAGRAMS (top view) -$- Vs B4 E4 (4 15 I. "" " Ri N,C, C B C3 I E3 B3 * GND B2 E2 (2 Vs C1 E1 B1 -'SUB 5- 5957 L7180 : R'N L7182: AiN = 350Q = 3 KQ 5-5958/1 LTab connec.ed '0 p'n 8 THERMAL DATA I Thermal Resistance Junction-case Thermal Resistance Junction-ambient ELECTRICAL CHARACTERISTICS (T amb Symbol ICEX Parameter VCE(:~t) Collector-emitter Saturation Voltage 25 'C unless otherwise specified) TestCon_d_it_io_n__s________-r_M_in_.~-T~y~p-.+_M-a-x-.-c_u-n_i_t-rF~ig~. Output Leakage Current VCER(sus) Collector-emitter Sustaining Voltage(') = I VCE=80V VCE =80 V Tamb =70 °C Ic = 50 mA V, = 0.4 V lie =500 mA Ic = 750 mA Ic -1 A 1--- ___ 1--______________ Ic: 1.5 A _ I'(on) Input Current °C/W °C/W 3 35 Maxi Max J I 18 18 18 18 100 500 =625 J.lA = 935 J.lA = 1.25 mA =2.25 mA For L7180 For L 7180 ForL7182 ForL7182 V, = 2.4 V Vi = 3.75 V V,=5V Vi=12V VCE = 2 V Ic = 1 A Ic=1.5A V 2 1.15 1.3 1.4 1.6 V V V V 3 4.3 9.6 1.8 5.2 mA mA mA mA 4 2 2.5 V V 5 6.5 10 V V 50 1.4 3.3 0.6 1.7 1 · I------.-r-------------r-------~-----_+--~-~-_+--t_~ I For L 7180 V'(an) Input Voltage ! VCE=2V ForL7182 VCE = 2 V 1 VCE = 2 V ::~~ i~;~~~~6~:;~:~:--+~: ~:.:: ~:: ~:(')t,,",, = 10IlS. Guaranteed by design; not tested 100 %. 214 626 Ie = 1 A Ic = 1.5 A -- - - - - _.. - - -- ------- 1 -- -~- 1.5 s il - - 1 - ilS L7180-L7182 TEST CIRCUITS Figure 1. Figure 2. OPEN Figure 3. Figure 4. OPEN OPEN OPEN S-19&O 5-1986 Figure 5. OPEN 5-1987 3/4 627 L7180-L7182 MOUNTING INSTRUCTIONS The power dissipated in the circuit must be removed by adding an external heatsink. Thanks to the Multiwatt® package attaching the heatsink is very simple, a screw or a compression spring (clip) being sufficient. Between the heatsink and the package it is better to insert a layer of silicon grease, to optimize the thermal contact ; no electrical isolation is needed between the two surfaces. Figure 6 : Mounting Example. 4/4 628 {"U ~~t~~~~~~· ------------- ,.r== .,L SCiS-THOMSON ~D©OO@~[L~©'[fOO@[RJJD©~ M5450 M5451 LED DISPLAY DRIVERS • M5450 34 OUTPUTS/15mA SINK • M5451 35 OUTPUTS/15mA SINK GENERATOR OUTPUTS (NO • CURRENT EXTERNAL RESISTORS REQUIRED) • CONTINUOUS BRIGHTNESS CONTROL • SERIAL DATA INPUT • ENABLE (ON M5450) • WIDE SUPPLY VOLTAGE OPERATION • TTL COMPATIBILITY silicon gate technology. They are available in 40-pin dual in-line plastic packages. A single pin controls the LED display brightness by setting a reference current through a variable resistor connected to V DD or to a separate supply of 13.2V maximum. The M5450 and M5451 are pin-to-pin replacements of the NS MM 5450 and MM 5451. Application examples: • MICROPROCESSOR DISPLAYS • INDUSTRIAL CONTROL INDICATOR • RELAY DRIVER • INSTRUMENTATION READOUTS The M5450 and M5451 are monolithic MOS integrated circuits produced with an N-channel DIP-40 Plastic ORDERING NUMBERS: M5450 B7 M5451 B7 ABSOLUTE MAXIMUM RATINGS V DD VI Vo (off) 10 Ptot Tj Top T stg Supply voltage Input voltage Off state output voltage Output sink current Total package power dissipation Junction temperature Operating temperature range Storage temperature range -0.3 to 15 -0.3 to 15 15 40 at 25°C at 85°C 150 -25 to 85 -65 to 150 V V V mA 1W 560 mW °C °C °C Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. June 1988 1/7 629 M5450-M5451 CONNECTION DIAGRAMS ~ .0 OUTPUT BIT 18 "ss OUTPUT BIT 17 2 3. OUTPUT BIT 19 OUTPUT BIT 17 2 OUTPUT BIT 16 3 38 OUTPUT BIT 20 3 OUTPUT BIT 15 • OUTPUT BIT 16 37 OUTPUT BIT 21 OUTPUT BIT 15 • 'Iss OUTPUT B[T 19 37 OUTPUT BIT 21 OUT~UT 5 36 OUTPUT BtT 22 OUTPUT BIT 14 5 36 OUTPUT BIT 13 6 35 OUTPUT BIT 23 OUTPUT BIT 13 6 35 OUTPUT BIT 23 BIT 22 OUTPUT BIT 12 ,. OUTPUT BIT 24 OUTPUT B[T 12 ,. OUTPUT B[T 24 OUTPUT BIT 11 33 OUTPUT BIT 2S OUTPUT B[T 11 33 OUTPUT BIT OUTPUT BIT 10 32 OUTPUT BIT 26 OUTPUT BIT 10 9 OUTPUT SIT 9 10 31 OUTPUT BIT 27 OUTPUT BIT 9 10 OUTPUT BIT 8 " 30 OUTPUT BIT 28 OUTPUT B[T 8 29 OUTPUT BIT 29 OUTPUT 81T 7 13 28 OUTPUT BIT 30 OUTPUT BIT.6 M5450 OUTPUT BIT S ,. 27 OUTPUT BIT 31 OUTPUT BIT ~ OUTPUT BIT 4 IS 26 OUTPUT BIT 32 OUTPUT BIT 4 15 OUTPUT BIT 3 16 25 OUTPUT BIT 33 16 17 ,. OUTPUT BIT 3 OUTPUT BIT 2 OUTPUT BIT 34 OUTPUT BIT 2 17 OUTPUT BIT 1 18 23 DATA ENABLE OUTPUT BIT I 18 BRIGHTNESS "20 22 DATA IN 21 CLOCK IN BRIGHTNESS CONTROL VOD "20 CONTROL VDD " M5451 31 2' OUTPUT BIT 29 13 '8 OUTPUT BIT)O " ,. n" OUTPUT BIT 31 21 CLOCK IN 26 OUTPUT BIT 32 Z5 5-5796 BLOCK DIAGRAM OUTPUT BIT, BRIGHTNESS ,8 CONTROL OUTPUT BIT 17 30 OUTPUT BIT 28 5_';o7'3S Fig. 1 1~ 32 OUTPUT BIT 16 "12 ,. OUTPUT BIT 6 DATA ENABLE(M5450) OUTPUT 35 (MS4,-,').....--':.::..t-SERIAL DATA-"'-''''-I,...-J CLOC."K'+_-'-'-I--- 5-5797 630 OUTPUT BIT 20 OUTPUT BIT 14 OUTPUT BIT 7 2/7 OUTPUT BIT 18 3' 38 OUTPUT BIT 33 OUTPUT BIT 34 OUTPUT BIT 35 DATA IN M5450- M5451 STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to 13.2V, Vss= OV, unless otherwise specified) Parameter VOO Supply Voltage 100 Supply Current VI Input Voltage Logical "0" Level Logical "'1" Level Is Brightness Input Current Inote 21 Vs Brightness Input Voltage Ipin 191 VO(off) Off State Out. Voltage 10 Out. Sink Current Inote 3) Segment OFF Segment ON f clock Input Clock Frequency 10 Output Matching Inote 11 Test conditions Min. Typ. Max. Unit 13.2 V 7 mA -0.3 2.2 Voo-2 0.8 Voo Voo V V V 0 0.75 mA 3 4.3 V 13.2 V 10 J.lA 10 4 25 J.lA mA mA 0.5 MHz ± 20 % 4.75 Voo= 13.2V ± 10 J.lA input bias 4.75';; Voo';; 5.25 VOO > 5.25 Input current = 750 J.lA Vo = 3V Vo = 1V Inote 41 Brightness In. = 0 J.lA Brightness In. = 100 J.lA Brightness In. = 750 J.lA Notes: 1. Output matching is calculated as the percent variation from IMAX 0 2 12 0 2.7 15 + IMIN12. 2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. 3. Absolute maximum for each output should be limited to 40 mAo 4. The Vo voltage should be regulated by the user. See figures 5 and 6 for allowable Vo versus 10 operation. FUNCTIONAL DESCRIPTION Both the M5450 and the M5451 are specifically designed to operate 4 or 5-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" follow~d by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current LED displays. A 1 nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations. A block diagram is shown in figure 1. For the M5450 a DATA ENABLE is used instead of the 35th output. The DATA ENAB LE input is a metal option for the M5450. 3/7 631 M5450-M5451 FUNCTIONAL DESCRIPTION (continued) The output current is typically 20 times greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of 400n nominal value. Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the sh ift registers into the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master-slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation. Bit 1 is the first bit following the start bit and it will appear on pin 18. A logical "1" at the input will turn on the appropriate LED. Figure 3 shows the timing relationship between Data, Clock and DATA ENABLE. A max clock frequency of 0.5 MHz is assumed. For applications where a lesser number of outputs are used, it is possible to either increase the current per output or operate the part at higher than lV V OUT ' The following equation can be used for calculations. T j = [(V OUT ) (I LED ) (No. of segments) + (Voo • 7 mAl 1 (124°C/W) + Tamb nY n n L- where: Tj = junction temperature (150°C max) VOUT= the voltage at the LED driver outputs ILEO= the LED current 124°C/W = thermal coefficient of the package T amb = ambient temperature The above equation was used to plot figure 4,5 and 6. Fig. 2 - Input Data Format CLOCK n y nn riL...Jn r-~ L,-J Y -..J L...J DATA j-,L...Jn Y n Y __ .J r I I : START: BIT' I :BIT35: BIT36' I L...J I J ~;,14f$;/I'M;/&)ffi;7;,1;/$;/4'@j_ n ~. (INTERNAL) L._ _ _ __ n RESET (INTERNAL) ' - -_ __ 5-5827/1 _4/_7_ _ _ _ _ _ _ _ _ _ _ ru SCS-THOMSON _ _ _ _ _ _ _ _ _ _ __ . J'~ ""'"O©IliI@~~~©llllil@~O©:§i 632 M5450 -M5451 Fig.3 CLOCK DATA 300ns MIN DATA ENABLE lOOns MIN Plol ,-,--"",-,-,....,-,-....,-""n (WI r-+--+'~~:--l;~:'y"c"o Fig.5 (,-1,910 I -t 1 +t- \~ Tamb(OC) - -r'" 'b. 3OSE:GM-1d.,. '" .:x -+1+ pM 60 Tam b,,8S'C Tj"l50°C(MAX) 20SEGM _+.1 0.6 Fig.6 I I 18 5 -;78 ~ 12 16 I 20 24 'LED (rnA) 8 12 16 20 ]t. 28 3234N"Segm. TYPICAL APPLICATIONS Basic electronically tuned Radio or TV system LEO DISPLAY M5450 DISPLAY DRIVER PLL SYNTHESIZER 5_5800 STATION DETECT. ETC. -------------- ~ ~~~~~~1T~:~~Al 5/7 633 M5450-M5451 TYPICAL APPLICATIONS (continued) Duplexing 8 Digits with One M5450 vDD ,-, ,-, ,-, ,-, ,-, ,-, ,-, ,-, O. O. 0 .'='./:1 ./~ ./~ .'::1. 9 16 28 40 32 39 24 31 M5450 CLOCK IN +---- 5-5801 DATA IN POWER DISSIPATION OF THE IC The power dissipation of the Ie can be limited using different configurations. a) S_S787 ~6~/7________________________ ~~~~~~?~:~~ 634 __________________________ M5450-M5451 In this application R must be chosen taking into account the worst operating conditions. R is determined by the maximum number of segments activated R= Vc - V D MAX -Va NMAX'l MIN o The worst case condition for the device is when roughly half of the maximum number of segments are activated. It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the device. In critical cases more resistors can be used in conjunction with groups of segments. In this case the current variation in the single resistor is reduced and Ptot limited. b) In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen. The total power dissipation of the IC depends, in a first approximation, only on the number of segments activated. c) I n this configuration V auT + V 0 is constant. The total power dissipation of the IC depends only on the number of segments activated. -------------- ~ ~~~~m?1r~:~~~~ ____________ ---...:7/_7 635 I I I I I I I I I I I I I I I I I I I I M5480 LED DISPLAY DRIVER • 3 112 DIGIT LED DRIVER (23 SEGMENTS) • CURRENT GENERATOR OUTPUTS (NO RESISTORS REQUIRED) • CONTINUOUS BRIGHTNESS CONTROL • SERIAL DATA INPUT • NO LOAD SIGNAL REQUIRED • WIDE • TTL COMPATIBILITY SUPPLY VOLTAGE technology. It utilizes the M5451 die packaged in a 28-pin plastic package making it ideal for a 3% digit dispaly. A single pin controls the LED dispaly brightness by setting a reference current through a variable resistor connected either to VDD or to a separate supply of 13.2V maximum. The M5480 is a pin-to-pin replacement of the NS MM 5480. OPERATION Applications examples: • MICROPROCESSOR DISPLAYS • INDUSTRIAL CONTROL INDICATION • RELAY DRIVER • INSTRUMENTATION READOUTS The'M5480 is a monolithic MOS integrated circuit produced with a N-channel silicon gate DIP-28 Plastic ORDERING NUMBER: M5480 B7 ABSOLUTE M.AXIMUM RATINGS V DD V, Vo (off) 10 Ptot Supply voltage I nput voltage Off state output voltage Output sink current Total package power dissipation Tj Top T stg Junction temperature Operating temperature range Storage temperature range -0.3 to -0.3 to 15 15 . 15 40 at 25°C at 85°C 150 -25 to 85 -65 to 150 V V V mA 940mW 490mW °C °C °C Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. June 1988 1/6 637 M5480 CONNECTION DIAGRAM Vss OUTPUT BIT 12 OUTPUT BIT 11 OUTPUT BI110 OUTPUT BIT 13 3 OUTPUT BIT 14 OUTPUT BI1 9 OUT PUT BIT 15 8 OUTPUT BIT 16 OUTPUT BI1 OUTPUT BIT 7 OUTPUT BIT 17 OUTPUT BI16 OUTPUT BIT 18 5 OUTPUT BIT 19 OUTPUT BIT OUTPUT BIT 4 OUTPUT BIT 20 OUTPUT BI13 10 OUTPUT BIT 21 OUTPUT BI1 2 11 OUT PUT BIT 22 OUTPUT Bill 11 BRIGHTNESS CONTROL 13 OATA IN VOO 14 CLOCK IN 5·S782 BLOCK DIAGRAM Fig. 1 BRIGHTNESS CONTROL 5-5783 _2/_6_ _ _ _ _ _ _ _ _ _ _-+_ 638 ~ ~~~~m~1J~~~ M5480 STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to 13.2V, V 55= OV, unless otherwise specified) Parameter Test conditions Voo Supply Voltage 100 Supply Current Voo= 13.2V VI I nput Voltages Logical "0" Level Logical "1" Level ± 10ltA Input Bias IB Brightness Input Current (note 21 VB Brightness Input Voltage (pin 131 VO(oll) Off State Output Voltage 10 Output Sink Current (note 31 Segment OFF Segment ON fclock Input Clock Frequency 10 Output Matching (note 11 Notes: Min. Typ. Max. Unit 13.2 V 7 mA -0.3 2.2 Voo-2 0.8 Voo Voo V V V 0 0.75 mA 4.3 V 18 V 10 itA 10 4 25 itA mA mA 0.5 MHz ± 20 % 4.75 4.75 .; V 00 .; 5.25 Voo > 5.25 Input Current = 750 itA 3 13.2 Vo = 3V Vo = 1V (note 41 Brightness In. = 0 itA Brightness In. = 100 itA Brightness In. = 750 itA 0 2 12 0 2.7 15 1. Output matching is calculated as the percent variation from I MAX + IM IN /2. 2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. 3. Absolute maximum for each output should be limited to 40 mAo 4. The Vo voltage should be regulated by the user. FUNCTIONAL DESCRIPTION The M5480 is specifically designed to operate 3 1/ 2 digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1nF capacitor should be connected to brightness control, pin 13, to prevent possible oscillations. A block diagram is shown in figure 1. The output current is typically 20 times greater than the current into pin 13, which is set by an external variable resistor. There is an internal limiting resistor of 400n nominal value. ___________________________ ~~~~~~g~~~ _________________________ 3~/6 639 M5480 FUNCTIONAL DESCRIPTION (continued) Figure 2 shows the input data format. A start bit of logical" 1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master-slave configurations. There is no clear for the master portion of the first register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation. Figure 3 shows the timing relationships between Data, and Clock. A maximum clock frequency of 0.5 MHz is assumed. Figure 4 shows the Output Data Format for the 5480. Because it uses only 23 of the possible 35 outputs, 12 of the bits are "Don't Care". For applications where a lesser number of outputs are used, it is possible to either increase the current per output, or operate the part at higher than 1V V OUT ' The following equation can be used for calculations. T j = [(V OUT) (I LED ) (No. of segments) + Voo • 7 mA] (132°C/W) + Tamb where: T j = junction temperature (150°C max) VOUT= the voltage at the LED driver outputs I LED = the LED current 132°C/W = thermal coefficient of the package T amb = ambient temperature Fig.2 - Input Data Format CLOCK DATA n LOAD (INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J L _ _ _ __ n RESET (INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......J Fig.3 CLOCK DATA ~ L_ \ f t.,," -4/~6-------------------------~~~~~~gT~n 640 '-_ _ __ 5_S826 ----------__--------------- M5480 Fig. 4 - Serial Data Bus/Outputs Correspondence TYPICAL APPLICATION BASIC 3 1/2 Digit interface. I ~I ~::J 1_1'- _I l~~S~G_M!t:!.~1 M5480 DISPLAY DRIVER r r 5-57. CLOCK DATA POWER DISSIPATION OF THE IC The power dissipati?n of the Ie can be limited using different configurations . •Yc a) In this application R must be chosen taking into account the worst operating conditions. R is determined by the maximum number of segments activated. R= Ve - V D N MAX - \tOUT MIN MAX· ID The worst case condition for the device is when roughly half of the maximum number of segments are activated. It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the dev ice. In critical cases more resistors can be used in conjunction with groups of segments. In this case the current variation in the single resistor is reduced and Ptot limited. -------------------------- ~~~~~~?~f~~~ ____________________~____ 5/6 641 M5480 b) 5-S788 In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen. The total power dissipation of the IC depends, in a first approximation, only on the number of segments activated. c) In this configuration VOUT+VO is constant. The total power dissipation of the IC depends only on the number of segments activated. _6'-/6_ _ _ _ _ _ _ _ _ _ _ _ 642 ~ ~~I~m?:~11 ---------------' M5481 LED DISPLAY DRIVER • 2 DIGIT LED DRIVER (14 SEGMENTS) GENERATOR OUTPUTS (NO • CURRENT RESISTOR REQUIRED) • CONTINUOUS BRIGHTNESS CONTROL • SERIAL DATA INPUT • DATA ENABLE • WIDE SUPPLY VOLTAGE • TTL COMPATIBILITY OPERATION technology. It utilizes the M5450 die packaged in a 20-pin plastic package copper frame,. making it ideal for a 2-digit display. A single pin controls the LED display brightness by setting a reference current through a variable resistor connected either to Voo or to a separate supply of 13.2V maximum. The M5481 is a pin-to-pin replacement of the NS MM 5481. Application examples: • MICROPROCESSOR DISPLAYS • INDUSTRIAL CONTROL INDICATOR • RELAY DRIVER • INSTRUMENTATION READOUTS The M5481 is a monolithic MOS integrated circuit produced with a N-channel silicon gate DIP-20 Plastic (0.25) ORDERING NUMBER: M5481 B7 ABSOLUTE MAXIMUM RATINGS Voo VI VO(Off) 10 Ptot Supply voltage Input voltage Off. state output voltage Output sink current Total package power dissipation Tj Top T stg Junction temperature Operating temperature range Storage temperature range -0.3 to -0.3 to 15 V 15 V V 15 40 mA at 25°C 1.5W at 85°C 800mW 150 °C -25 to 85 °C -65 to 150 °C Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. June 1988 1/6 643 M5481 CONNECTION DIAGRAM - - 20 OUTPUT BIT 9 OUTPUT BIT 1 19 OUTPUT BIT10 OUTPUT BIT 6 18 DOUTPUT BIT 11 OUTPUT BIT 5 17 ~ OUTPUT BIT OUTPUT BIT 4 16 OUTPUT BIT 13 15 VSS 7 14 OUTPUT BIT 14 OUTPUT BIT 8 OUTPUT BIT 3 OUTPUT BIT 2 OUTPUT BIT 1 BRIGHTNESS CONTROL VOO I6 I 12 18 13 DATA ENABLE 19 12 DATA IN 110 11 CLOCK 5-5790 BLOCK DIAGRAM OUTPUT BIT 1 OUTPUT 91T14 Fig. 1 BRIGHTNESS CONTROL SERIAL DATA -_--':o...t----j CLOC•.::K,-_.:..!...4~ 15 / 6=----_ _ _ _ _ _ _ _ _ _ _ _ -=2::..: 644 1ifi. ~~~~m~lI~:~~©~ 5- S191 -------------- M5481 STATIC ELECTRICAL CHARACTERISTICS (T amb within operating range, Voo= 4.75V to 13.2V, V 55= OV, unless otherwise specified) Parameter Voo Supply Voltage 100 Supply Current VI I nput Voltages Log ical "0" Level Logical "1" Level IB Brightness Input Current (note 2) VB Brightness Input Voltage (pin 9) Vo(o!!) Off State Output Voltage 10 Output Sink Current (note 3) Segment OFF Segment ON fCloCk Input Clock Frequency 10 Output Matching (note 1) Notes: Test conditions Min. Typ. I nput Current = 750 !J.A Vo = 3V V 0 = 1 V (note 4) Brightness In. = O,.,A Brightness In. = 100,.,A Brightness In. = 750,.,A Unit 13.2 V 7 mA -0.3 2.2 Voo-2 0.8 Voo Voo V V V 0 0.75 mA 4.3 V 13.2 V 10 ,.,A 10 4 25 ,.,A mA mA 0.5 MHz ± 20 % 4.75 Voo= 13.2V ± 10!J.A Input Bias 4.75";; Voo";; 5.25 V oo > 5.25 Max. 3 0 2 12 0 2.7 15 I 1. Output matching is calculates as the percent variation from IMAX + IMIN12. 2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. 3. Absolute maximum for each output should be limited to 40 mAo 4. The Vo voltage should be regulated by the user. FUNCTIONAL DESCRIPTION The M5481 uses the M5450 die which is packaged to operate 2-digit alphanumeric displays with mini· mal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2. signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non .. multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display bright· ness is determined by control of the output current for LED displays. A 1 nF capacitor should be connected to brightness control, pin 9, to prevent possible oscillations. A block diagram is shown in figure 1. The output current is typically 20 times greater than the current into pin 9, which is set by an external variable resistor. These is an internal limiting resistor of 400n nominal value. ~ SGS-THOMSON - - - - - - - - - - - - - - - "'Yl. IiiilO©IliI@I 5'.25 Max. 3 0 2 12 0 2.7 15 1. Output matching is calculated as the percent variation from I MAX + I M I N/2. 2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. 3. Absolute maximum for each output should be limited to 40 mAo 4. The Va voltage should be regulated by the user. FUNCTIONAL DESCRIPTION The M5482 uses the M5451 die which is packaged to operate 2-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non--multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1 nF capacitor should be connected to brightness control, pin 9, to prevent possible oscillations. A block diagram is shown in fiqure 1. The output current is typically 20 tir,les greater than the current into pin 9, which is set by an external variable resistor. There is an internal limiting resistor of 400n nominal value. ___________________________ ~~~~~~?~~~~ ________________________ ~3/~6 651 M5482 FUNCTIONAL DESCRIPTION (continued) Figure 2 shows the input data format. A start bit of logical" 1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches. At the low state of the clock a RESET signal is generated wh ich clears all the sh ift registers for the next set of data. The shift registers are static master slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear.· When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation. Figure 3 shows the timing relationships between Data and Clock. A maximum clock frequency of 0.5 MHz is assumed. Figure 4 shows the Output Data Format for the M5482. Because it uses only 15 of the possible 35 outputs, 20'of the bits are "Don't Cares". For applications where a lesser number of outputs are used it is possible to either increase the current per output or operate the part at higher than 1V V OUT' The following equation can be used for calculations. Tj where: == [ (V OUT ) (I LEO ) (No. of segments) + Voo • 7 mA 1 (80°C/W) + Tamb T j = junction temperature (150°C max) V OUT = the voltage at the LE D driver outputs I LE 0= the LED current 80°C/W = thermal coefficient of the package T amb = ambient temperature Fig. 2- I nput Data Format CLOCK n --1 1 n· n LJ LJ I I I n L.J I n LJ 36 r-~ LI j-"L.Jn LJn LJn L..Jn L.Jn L . .. _oJ I :START : BITl : DATA I I I I I I : Bn 34: BlT3Sj ---IlWmff&h7&;,7$ff)'&A?$hf%)'AWll;) n LOAD (INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--..1 L _ _ _ __ n RE5ET (INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-J L...._ __ 5-5785/1 Fig.3 CLOCK DATA 5-5826 4~/~6_________________________ ~~~~~~~~I~~~ 652 ------------------------- M5482 Fig. 4 - Serial Data Bus/Outputs Correspondence TYPICAL APPLICATION BASIC electronically tuned TV system LED DISPLAY M5482 DISPLAY DRIVER POWER DISSIPATION OF THE IC The power dissipation of the IC can be limited using different configurations . •Vc a) Your i In this application R must be chosen takiog into account the worst operating conditions. R is determined by the maximum number of segments activated. Vc -Vo MAX -Vo MIN N MAX· 10 The worst case condition for the device is when roughly half of the maximum number of segments are activated. ' It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the device. In critical cases more resistors can be used in conjunction with groups of segments. In this case the current variation in the single resistor is reduced and Ptot limited. R= ______________ -=----:-~.:..:.:....:;"--,--~-"-"-'-- ~~~~~~~~~~ _ _ _ _ _ _ _ _ _ _ _ _ _5~/~6 653 M5482 b) In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen. . The total power dissipation of the IC is, in first approximation, depending only on the number of segments activated. c) In this configuration VOUT +VD is constant. The total power dissipation of the IC depends only on the number of segments activated. . _6~/6_________________________ ~1~1~~~~n 654 --------------__----__----- M8438A SERIAL INPUT LCD DRIVER • DRIVES UP TO 32 LCD SEGMENTS • DATA TRANSFER: FIXED ENABLE MODE FOR DIP-40, ENABLE AND LATCH-MODE FOR 44PLCC • INPUTS ARE CMOS, NMOS AND TTL COMPATIBLE • • • • .CASCADABLE REQUIRES ONLY 3 CONTROL LINES ON CHIP OSCILLATOR CMOS TECHNOLOGY FOR WIDE SUPPLY VOLTAGE RANGE • -40 TO 85°C TEMPERATURE RANGE DESCRIPTION The M8438A is a CMOS integrated circuit that drives an LCD display, usually under microprocessor control. The part acts as a smart peripheral that drives up to 32 LCD segments. It needs only three control lines due to its serial input construction. It latches the data to be displayed and relieves the microprocessor from the task of generating the required waveforms. The M8438A can drive any standard or custom parallel drive LCD whether it be field effect or dynamic scattering. Several drivers can be cascaded, if more than 32 segments are to be driven. The' AC frequency of the LCD waveforms can be supplied by the user or can be generated by attaching a capacitor to the OSC input which determines the frequency of an internal oscillator. The M8438A is available in DIE form and assembled in 40 pin dual-in line plastic or 44 PLCC packages. B C DIP-40 Plastic 44 PLCC Plastic Chip Carrier ORDERING NUMBERS: M8438A DIE 1 M8438A 86 M8438A C6 PIN CONNECTIONS ~CLOCK .voo El 2 39 SEG 1 SEG 32 , 3 38 SEG 2 37 SEG 3 SEG 30 5 36 Vss SEG 29 6 35 DO SEG 28 7 SEG 27 8 " 33 SEG4 SEG 26 9 32 SEG 5 SEG 25 10 31 05C. SEG 24 11 30 BP SEG 23 12 29 SEG6 SEG 22 13 28 SEG? SEG 21 " 27 SEG8 26 5EG 9 SEG31 SEG 20 15 DI SEG 19 16 25 SEGlO SEG18 17 24 SEG17 18 23 SEG lii 19 22 SEG13 SEG15 20 21 SEG14 SEG11 SEG12 5_8309 1 444342 " SEG28 4°39 n 8 37 ~ MS p DO ~ 01 36 pSEG4 35 ~SEG5 ~ osc. SEG2' IL 34 SEG23 13 33 BP 32 pSEG6 S£GZO 16 30 B. 31 pSEG1 1& 19 ;Ill 21 12 23 2425 2627 :1& 29 ~SEG8 ~ He .',;~.,~"~.';;~ ~~~~~::~;~~~ June 1988 1/7 655 M8438A BLOCK .DIAGRAM BP OSC. SEG. EL MODE CLOCK CONTROL MS DI~-------4----~ 1 - - - 0 DO 5 8307 OSC EL MS 01 00 BP SEG :Osciliator (capacitor or drive signal) :Enable/Latch control input :Mode select input (not available in 40 Pin OIL) :Serial data input :Serial data output :Backplane output :Segment output signal ABSOLUTE MAXIMUM RATINGS Symbol (VDD-VSS) Parameter Supply voltage Value Unit -0.3 to +12 V V VI Input voltage VSS - 0.3 to VDD + 0.3 Vo Output voltage VSS - 0.3 to VDD + 0.3 V Po Power dissipation 250 mW -55 to +125 °C °C Tstg TA Storage temperature Operating temperature -40 to +85 Stresses in excess of those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2/7 656 M8438A ELECTRICAL CHARACTERISTICS (T amb = 25°C and VDD = 5V unless otherwise noted) STATIC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Voo Supply Voltage 100 Supply Current Oscillator f< 15kHz Quiescent Current Voo=10V IQ VIH Input High Level VIL Input Low Level liN Input Current CI Input Capacitance VIH Input High Level VIL Input Low Level liN Input Current Min. Max. 3 10 V 60 /LA 10 /LA V .5V oo Voo 0 .2VOO ±5 CLOCK DI EL 5 Driven mode OSC .1Voo ±10 Driven mode RON Segment Output Impedance IIL= 10/LA RON Backplane Output Impedance IL=100/LA VOF F Output Offset Voltage CL = 250pF between each SEG output and BP RON Data Output Impedance IL=100/LA V /LA pF V .9Voo Driven mode Unit 40 V /LA k{J 3 k{J ±50 mV 3 k{J Max. Unit 500 ns DYNAMIC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. tTA Transition Time OSC Driven mode tso Data Set-up Time Fig. 1 and 2 150 ns tHO Data Hold Time Fig. 1 and 2 50 ns tSE EL Set-up Time Fig. 1 100 ns tHE EL Hold Time Fig. 1 100 ns tWE EL Pulse Width Fig. 2 175 ns tCE Clock to EL Time Fig. 2 250 tpd f DO Propagation Delay Fig. 1, 2; CL = 55pF Clock Rate Voo = 10 50% duty cycle; DC ns 500 ns 1.5 MHz FUNCTION,.AL DESCRIPTION LCD-AC-GENERATOR This block generates a 50% duty cycle signal for the backplane output. The circuit can be used in two different modes: oscillator or driven. OSCILLATOR MODE: In this mode the backplane frequency is determined by the internal RC oscillator together with an 8-stage frequency divider. For generating the backplane output signal of 50% duty cycle the oscillator frequency is divided by 256. The RC oscillator requires an external capacitor to be connected bet- ween input OSC and VSS. A value of 18pF gives a backplane frequency of 80Hz ± 30% at VDD = 5V. The variation of the backplane frequency over the entire temperature and supply voltage range is ± 50%. DRIVEN MODE: In this mode the signal at the backplane output BP is in phase with an external driving signal applied to input OSC. This mode is used to synchronize the LCD drive of two or more cascaded driver circuits. 3/7 657 M8438A FUNCTIONAL DESCRIPTION (continued) DETECTION LOGIC The circuit is able to distinguish between the conditions for oscillator or driven mode. If the circuit is to be in the oscillator mode, the OSC pin has a capacitor connected to it. The oscillator will start as soon as the supply voltage exceeds a certain minimim value. The signal at pin OSC swings within a range from 0.3VDD to 0.7VDD. If the circuit is to be in the driven mode, the OSC pin has to be forced to logic levels by an external source. The transition time between the logic levels must be short, so that the circuit does not react on the voltage level in between. In the driven mode the a-stage frequency divider is by-passed. SEGMENT OUTPUTS A logic 0 at the data input DI causes a segment output signal to be in phase with the backplane signal and turns the segment off. A logic 1 causes a segment output to be in opposite phase to the backplane signal and turns the segment on. MICROPROCESSOR INTERFACE The circuit can operate in two different data transfer modes: Enable mode and latch mode. One of either mode can be chosen with the mode select input MS. An internal pull up device is provided between this input and VDD. Enable mode is selected if MS is left open or connected to VDD. Latch mode is selected if MS is connected to VSS. The input MS is not available, if the device is assembled in the 40 pin package, and is internally fixed to operate in ENABLE MODE. ENABLE MODE Fig. 3 shows a timing diagram of the enable mode. Data is serially shifted in and out of the shift register on the negative transition of the clock. Serial entry into the shift register is permitted when the enable/latch control EL is high. When EL is low it causes the shift register clock to be inhibited and the content of the shift register to be loaded into the latches that control the segment drivers. LATCH MODE Fig. 4 shows a timing diagram of the latch mode. Data is serially shifted in and out of the shift register on the negative transition of the clock. Serial entry into the shift register is permitted independently of the enable/latch control EL. When EL is high it causes a parallel load of the content in the shift register into the latches. It is accepta4/7 658 ble to tie the EL line high. Then the latches are transparent and only two lines, clock and data input, would then be needed for data transfer. POWER-ON LOGIC A power on reset pulse is generated internally when the supply voltage is being turned on. The generation of the reset pulse is level dependent and will occur even on a slowly rising supply Voltage. The power on reset pulse resets all shift register stages and the latches that control the segment drivers. Therefore all segment outputs are initially in phase with the backplane output. This causes the display to be blanked and no arbitrary data to show up. This condition is maintained until data is shifted into the register and loaded into the latches. CONDITIONS FOR POWER-ON RESET FUNCTION The paR circuit triggers on the rising slope of the positive supply voltage VDD. A reset pulse will be generated, if conditions a) through d) are given: a) Level Rising slope from V1 to V2 V1 max=0.5V V2 min=3.0V ~ VDD ----V2 ------V1 ~ -~-----O.5V VDD b) Rise time tr min = 10 /ls tr max = 1 s -----3.0V I I --f--Lt-- " 12 c) Rise function The function of VDD between t1 und t2 may be nonlinear, but should not show a maximum and should not exceed 0.25 V//ls. d) Recovery time The minimum time between turn-off and turnon of VDD is 1s. CASCADE CONFIGURATION Several LCD drivers can be cascaded if a liquid crystal display with more than 32 segments is to be connected. The phase correlation between all segment outputs is achieved by using the second (and any other) device in the driven mode. Two different cascade configurations can be chosen depending whether the LCD frequency is to be determined by the internal RC oscillator or by an external signal. Figure 3 shows the connection scheme for a self oscillating configuration, figure 4 shows the connection of an externally controlled one. M8438A Fig. 1 - Timing diagram of enable mode: set-up and hold time ---- CLOCK ENABLE I LATCH DATA IN ----- I J "-L bnn f ·I~ funmn---=x tHE tSE I -- --- tSD tHO DATA OUT .1 tpd ------------ 5-8310'1 Fig. 2 - Timing diagram of latch mode: set-up and hold time tCE CLOCK / ---- { ---- ENABLE'LATCH ~ 'I 'WE 1 DATA IN DATA OUT 1'" .1" E~::::: r nm------- =:x .1 tpd'_ _ - - - - - - - - - - - - - - , 5- 831 1'1 5/7 659 M8438A Fig. 3 - Timing diagram of enable mode: Serial load into SR and parallel transfer to LCD ENABLE/LATCH CLOCK DATA IN SEGMENTS BACKPLANE 5~8312/1 Fig. 4 - Timing diagram of latch mode: Serial load into SR and parallel transfer to LCD ENABLE/ LATCH CLOCK DATA IN SEGMENTS BACKPLANE 5-8313/1 6/7 660 M8438A Fig. 5 - Cascade configuration, self oscillating .c1. DEVICE 1 DEVICE 2 LCD B_p~1 T ~LIo_s_c____Bp..JH:B~P~~~~: 0_S_C_ _ _ I I DEVICE n B_P. .~ yLO_S_C_ _ _ _ NC 5- 8314 Fig. 6 - Cascade configuration, drive by external signal DEVICE LCD DRIIJoING U--~--"'OSC SIGNAL BP DEVICE 2 OSC I I I BP NC I I DEVICE n L1. B_P~~ 0_S_C_ _ _ _ NC 5-8364 7/7 661 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I M8439 SERIAL INPUT LCD DRIVER • DRIVES UP TO 32 LCD SEGMENTS • DATA TRANSFER: LATCH MODE • INPUTS ARE CMOS, NMOS AND TTL COMPATIBLE • CASCADABLE • REQUIRES ONLY 3 CONTROL LINES Plastic DIP-40 • ON CHIP OSCILLATOR • CMOS TECHNOLOGY FOR WIDE SUPPLY VOLTAGE RANGE ORDERING NUMBERS: M8439 86 M8439 DIE 1 • -40 TO 85°C TEMPERATURE RANGE DESCRIPTION The M8439 is a CMOS integrated circuit that drives an LCD display, usually under microprocessor control. The part acts as a smart peripheral that . drives up to 32 LCD segments. It needs only three control lines due to its serial input construction. It latches the data to be displayed and relieves the microprocessor from the task of generating the required waveforms. The M8439 can drive any standard or custom parallel drive LCD whether it be field effect or dynamic scattering. Several drivers can be cascaded, if more than 32 segments are to be driven. The AC frequency of the LCD waveforms can be supplied by the user or can be generated by attaching a capacitor to the OSC input which determines the frequency of an internal oscillator. The M8439 is available in DIE form and assembled in 40 pin dual-il') line plastic. PIN CONNECTION +Voo ~ CLOCK EL 2 39SEGl SEG32 3 38 SEG2 SEG31 4 37 SEG 3 SEG 30 5 3. • Vss 35 00 7 34 01 8 33 SEG4 SEG 26 9 32 5EG 5 SEG 25 10 31 osc. SEG24 11 30 BP SEG 23 12 29 SEG6 SEG 22 13 28 SEG 21 14 SEG 29 SEG 28 SEG 27 SEG7 27 SEG8 SEG 20 15 2. SEG 9 SEG 19 25 SEG10 I. SEG18 17 24 SEG 17 18 23 SEG12 SEG lii 19 22 SEG13 SEG 15 20 21 5EG14 SEG11 5_8309 June 1988 1/6 663 M8439 BLOCK DIAGRAM BP 05C. 5EG. EL MODE CLOCK CONTROL SR CLOCK 01 U-------~----__i f----O DO S·9596 OSC EL DI DO BP SEG :Oscillator (capacitor or drive signal) :Enable/Latch control input :Serial data input :Serial data output :Backplane output :Segment output signal ABSOLUTE MAXIMUM RATINGS Parameter Symbol (VDD-VSS) Supply voltage Value Unit -0.3 to +12 V V VI Input voltage VSS - 0.3 to VDD + 0.3 Va Output voltage VSS-0.3 to VDD+0.3 V PD Power dissipation 250 mW Storage temperature -55 to + 125 Operating temperature -40 to +85 °C °C TstQ TA Stresses in excess of those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating. only and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2/6 664 M8439 ELECTRICAL CHARACTERISTICS (T amb = 25°C and VDD = 5V unless otherwise noted) STATIC ELECTRICAL CHARACTERISTICS Symbol Test Condition Parameter VOO Supply Voltage 100 Supply Current Oscillator f< 15kHz Quiescent Current Voo=10V IQ VIH Input High Level VIL Input Low Level liN CI Input Current VIH Input High Level VIL Input Low Level liN Input Current Input Capacitance OSC Max. 3 10 V 60 /LA 10 /LA .5Voo Voo 0 .2Voo ±5 CLOCK DI EL I Min. 5 Driven mode Driven mode V V /LA pF V .9Voo Driven mode Unit V .1Voo ±10 /LA kD RON Segment Output Impedance IIL= 10llA 40 RON Backplane Output Impedance IL=100/LA 3 kD VOFF Output Offset Voltage CL = 250pF between each SEG output and BP ±50 mV RON Data Output Impedance IL=100/LA 3 kD Max. Unit 500 ns DYNAMIC ELECTRICAL CHARACTERISTICS Symbol Test Condition Parameter Min. tTR Transition Time OSC Driven mode tso Data Set-up Time Fig. 1 and 2 150 ns tHO Data Hold Time Fig. 1 and 2 50 ns tSE EL Set-up Time Fig. 1 100 ns tHE EL Hold Time Fig. 1 100 ns tWE EL Pulse Width Fig. 2 175 ns tCE Clock to EL Time Fig. 2 250 tpd DO Propagation Delay Fig. 1, 2; CL = 55pF Clock Rate Voo = 10 50% duty cycle; f DC ns 500 ns 1.5 MHz FUNCTIONAL DESCRIPTION . LCD-AC-GENERATOR This block generates a 50% duty cycle signal for the backplane output. The circuit can be used in two different modes: oscillator or driven. OSCILLATOR MODE: In this mode the backplane frequency is determined by the internal RC oscillator together with an 8-stage frequency divider. For generating the backplane output signal of 50% duty cycle the oscillator frequency is divided by 256. The RC oscillator requires an external capacitor to be connected bet- ween input OSC and VSS. A value of 18pF gives a backplane frequency of 80Hz ± 30% at VDD = 5V. The variation of the backplane frequency over the entire temperature and supply voltage range is ± 50%. DRIVEN MODE: In this mode the signal at the backplane output BP is in phase with an external driving signal applied to input OSC. This mode is used to synchronize the LCD drive of two or more cascaded driver circuits. 3/6 665 M8439 FUNCTIONAL DESCRIPTION (continued) DETECTION LOGIC The circuit is able to distinguish between the conditions for oscillator or driven mode. If the circuit is to be in the oscillator mode, the OSC pin has a capacitor connected to it. The oscillator will start as soon as the supply voltage exceeds a certain minimim value. The signal at pin OSC swings within a range from 0.3Voo to 0.7Voo. If the circuit is to be in the driven mode, the OSC pin has to be . forced to logic levels by an external source. The transition time between the logic levels must be short, so that the circuit does not react on the voltage level in between. In the driven mode the a-stage frequency divider is by-passed. SEGMENT OUTPUTS A logic 0 at the data input 01 causes a segment output signal to be in phase with the backplane signal and turns the segment off. A logic 1 causes a segment output to be in opposite phase to the backplane signal and turns the segment on. MICROPROCESSOR INTERFACE Fig. 2 shows a timing diagram. Data is serially shifted in and out of the shift register on the negative transition of the clock. Serial entry into the shift register is permitted independently of the enable/latch control EL. When EL is high it causes a parallel load of the content in the shift register into the latches. It is acceptable to tie the EL line high. Then the latches are transparent and only two lines, clock and data input, would then be needed for data transfer. POWER-ON LOGIC A power on reset pulse is generated internally when the supply voltage is being turned on. The generation of the reset pulse is level dependent and will occur even on a slowly rising supply Voltage. The power on reset pulse resets all shift register stages and the latches that control the segment dri- 4/6 666 verso Therefore all segment outputs are initially in phase with the backplane output. This causes the display to be blanked and no arbitrary data to show up. This condition is maintained until data is shifted into the register and loaded into the latches. CONOITIONS FOR POWER-ON RESET FUNCTION The POR circuit triggers on the rising slope of the positive supply voltage Voo. A reset pulse will be generated, if conditions a) through d) are given: a) Level Rising slope from V1 to V2 V1 max=0.5V V2 min = 3.0V b) Rise time tr min = 10 /ls tr max= 1 s ~ VDO ----V2 ------V1 . ~ -~-----O.5V VDO -----3.0V , I ~ t1 12 c) Rise function The function of Voo between t1 und t2 may be nonlinear, but should not show a maximum and should not exceed 0.25 V//ls. d) Recovery time The minimum time between turn-off and turnon of Voo is 1s. CASCADE CONFIGURATION Several LCD drivers can be cascaded if a liquid crystal display with more than 32 segments is to be connected. The phase correlation between all segment outputs is achieved by using the second (and any other) device in the driven mode. . Two different cascade configurations can be chosen depending whether the LCD frequency is to be determined by the internal RC oscillator or by an external signal. Figure 3 shows the connection scheme for a self oscillating configuration, figure 4 shows the connection of an externally controlled one. M8439 Fig. 1 - Timing diagram of latch mode: set-up and hold time tCE ---- CLOCK ----- ENABLE/LATCH DATA IN .1 -\ 1 tSD 1 .1" DATA OUT .1 ~ 'I tWE E~--m Eum---uu=x tpd'_ _ - - - - - - - - - - - - - - , 5- B31 1/' Fig. 2 - Timing diagram of latch mode: Serial load into SR and parallel transfer to LCD ENABLE I LATCH CLOCK DATA IN SEGMENTS BACKPLANE S-8313/1 5/6 667 M8439 Fig. 3 - Cascade configuration, self oscillating DEVICE 1 DEVICE 2 LCD B~PI T ~L.Io_s_c___B_p....Hr-L..B=P==== r1_0_S_C_ _ _ I DEVICE n 1 ~ yL.o_s_C_ _ _ _B_P.... NC 5-8314 Fig. 4 - Cascade configuration, driven by external signal DEVICE LCD DRIVING U--_-...OSC SIGNAL BP DEVICE 2 OSC NC BP 1 I I I I DEVICE n ~ yL.o_s_C_ _ _ _B_P.. NC 5-8364 6/6 668 t='!' SCiS-mOMSON ~'Yl.. UljJD©IJiI@~~~©lllJil@Ir(I]D©~ M145026/7/8 REMOTE CONTROL ENCODER/DECODER CIRCUITS • M145026 ENCODER data (0, 1, open) to allow 3 9 (19,683) different codes. • M145027/M145028 DECODERS • MAY BE ADDRESSED IN EITHER BINARY OR TRINARY • TRINARY ADDRESSING NUMBER OF CODES • INTERFACES WITH RF, ULTRASONIC, OR INFRARED TRANSMISSION MEDIAS • DOUBLE TRANSMISSIONS FOR ERROR CHECKING • 4.5V TO 18V OPERATION • ON-CHIP R/C OSCILLATOR, NO CRYSTAL REQUIRED Two decoders are presently available. Both use the same transmitter - the M 145026. The decoders will receive the 9-bit word and will interpret some of the bits as address codes and some as data. The M145028 treats all nine bits as address. If no errors are received, the M 145027 outputs the four data bits when the transmitter sends address codes that match that of the receiver. A valid transmission output goes high on both decoders when they recognize an address that matches that of the decoder. Other receivers can be produced with different address/data ratios. • HIGH EXTERNAL COMPONENT TOLERANCE, CAN USE 5% COMPONENTS All the devices are available in 16 lead plastic package. • STANDARD CMOS B-SERIES INPUT AND OUTPUT CHARACTERISTICS • APPLICATIONS INCLUDE GARAGE DOOR OPENERS, REMOTE CONTROLLED TOYS, SECURITY MONITORING, ANTITHEFT SYSTEMS, LOW END DATA TRANSMISSIONS, WIRE LESS TELEPHONES MAXIMIZES DIP-16 Plastic (0.25) The M145026 encodes nine bits of information and serially transmits this information upon receipt of a transmit enable, TE, (active low) signal. Nine inputs may be encoded with trinary ORDER CODE: M145026 B1 M145027 B1 M145028 B1 CONNECTION DIAGRAMS Encoder Decoder Decoder 11.1101 1 IS Voo AI 1 16 A,2102 2 IS DATA OUT Ai 2 15 Al/OJ 3 14 fE A3 3 14 0' 13 RTC A4 4 13 De S 12 CTC AS 5 12 09 A5 A6/06 6 11 RS Rl 6 VT Rl 10 11.9/09 Cl , 10 R2/C2 Cl V5S e 9 "'10104 4 A510S ...7/07 , VSS e M145026 June 1988 AS/08 M145027 Voo AI 1 16 Voo 06 A2 2 15 A6 3 14 A' 13 AS 5 12 A9 6 11 VT 10 R2fC2 DATA IN . A3 VSS 4 e MI45028 9 DATA IN 1/10 669 M145026-M145027-M145028 ABSOLUTE MAXIMUM RATINGS DC Supply Voltage Input Voltage, All Inputs DC Current Drain Per Pin Storage Temperature Range Operating Temperature Range -0.5 to +18 V -0.5 to V DD +0.5 V mA 10 -65 to +150 °C -40 to +85 °C Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SWITCHING CHARACTERISTICS (Cl = 50 pF, Tamb = 25°C) Parameter tTlH tTHl Output Rise and Fall Time tTlH tTHl Data In Rise and Fall Time (M145027, M145028) fel Encoder Clock Frequency VDD Min TYP Max Unit 5 10 15 - - 100 50 40 200 100 80 ns 5 10 15 - - 15 15 15 p,s 5 10 15 0 0 0 2 5 5 MHz kHz - - - fCl Maximum Decoder Frequency (Referenced to Encoder Clock) (See Figure 9) 5 10 15 - - - - 240 410 450 tWl TE Pulse Width 5 10 Hi 65 30 20 - - - - 182 - - - - ±25 ±25 System Propagation Delay (TE to Valid Transmission) Tolerance on Timing Components (L'lRTC+L'lCTC+L'lRl +L'lCl) (L'lR2 + L'lC2) O_ _ _ _ _ _ _ _ _ _ _ _ 2/c.::1..:. .::; 670 - ~ ~~~~m~~l:lt - - ns Clock Cycles % M145026 -M145027 - M145028 ELECTRICAL CHARACTERISTICS -40'C VDD Parameter 25'C +85'C Unit V Min Max Min Typ Max Min Max 5 10 15 - - 0.05 0.05 0.05 - 0 0 0 0.05 0.05 0.05 - - 0.05 0.05 0.05 5 10 15 4.95 9.95 14.95 - 4.95 9.95 14.95 5 10 15 - 4.95 9.95 14.95 - - V 5 10 15 - - 1.5 3 4 - 1.5 3 4 - 1.5 3 4 V - 2.25 4.50 6.25 "1" Level 5 10 15 3.5 7 11 - 3.5 7 11 2.75 5.50 8.25 - 3.5 7 11 - 5 5 10 15 -2.5 -0.52 -1.3 -3.6 - -2.1 -0.44 -1.1 -3 -4.2 -0.88 -2.25 -8.8 - Source - -1.7 -0.36 -0.9 -2.4 5 10 15 0.52 1.3 3.6 - 0.44 1.1 3 0.88 2.25 8.8 - 0.36 0.9 2.4 5 10 15 - - 3 16 35 4 20 45 7 26 55 - 15 - ±0.3 - ±0.00001 ±0.3 - ±1.0 A1/D1-A9/D9 (M145026) A1-A5 (M145027) A 1-A9 (M145028) 5 10 15 - - ±55 ±300 ±650 ±80 ±340 ±725 - CI I nput Capacitance (V I = 0) - - - - IDD Quiescent Current - M 145026 5 10 15 - - - - VOL Output Voltage VI= VDD or 0 VOH VI=OorVDD VIL VIH "0" Level "1" Level I nput Voltage (Va = 4.5 or 0.5V) (Va = 0.9 or 1V) (VO= 13.5 or 1.5V) (Va = 0.5 or 4.5V) (Va = 1.0 or 9V) (Va = 1.5 or 13.5V) "0" Level Output Drive Current IOH IOL II (VOH (VOH (VOH (VOH = = = = 2.5V) 4.6VI 9.5V) 13.5V) (VOL = 0.4V) (VOL = 0.5V) (VOL = 1.5V) Sink I nput Current TE (M145026, Pullup Device) II II IDD IT IT I nput Current RS (M145026) Data In (M145027, M145028) Input Current Quiescent Current M145027, M145028 Total Supply Current M145026 (fCL = 20 kHz) Total Supply Current M145027, M145028 (ICL = 20 kHz) 5 10 15 - - - - - - - - - 5 10 15 - - 5 10 15 - - - - - - - - 5 7.5 - 0.0050 O.Q1OO 0.0150 0.10 0.20 0.30 30 60 90 50 100 150 - 100 200 300 200 400 600 - 200 400 600 400 800 1200 - V - - V - - mA mA /JA - /JA /JA pF - - - - p.A - - p.A - - - p.A - p.A -------------- ~ ~~~~m?ll~:~~l: _____________3'- /1_0 671 M145026 -M145027- M145028 OPERATING CHARACTERISTICS M145026 The encoder will serially transmit nine bits of trinary data as defined by the state of the A 1/D1-A9/D9 input pins. These pins can be in either of three states (0,1, open) allowing 3 9 = 19683 possible codes. The transmit sequence will be initiated by a low level of the TE input pin. Each time the TE input is forced low the encoder will output two identical data words. This redundant information is used by the receiver to reduce errors. If the TE input is kept low, the encoder will continuously transmit the data words. The transmitted words are self-completing (two words will be transmitted for each TE pulse). Each transmitted data bit is encoded into two data pulses. A logic zero will be encoded as two consecutive short pulses, a logic one by two consecutive long pulses, and an open as a long pulse followed by a short pulse. The input state is determined by using a weak output device to try to force each input first low, then high. If only a high state results from the two tests, the input is assumed to be hard wired to V DD . If only a low state is obtained, the input is assumed to be hard wired to Vss. If both a high and a low can be forced at an input, it is assumed to be open and is encoded as such. The transmit sequence is enabled by a logic zero on the TE input. This input has an internal pullup device so that a simple switch may be used to force the input low. While TE is high the encoder is completely disabled, the oscillator is inhibited and the current drain is reduced to quiescent current. When TE is brought low, the oscillator is started, and an internal reset is generated to initialize the transmit sequence. Each input is then sequentially selected and a determination is made as to input logic state. This information is serially transmitted via the Data Out output pin. M145027 The decoder will receive the serial data from the encoder, check it for errors and output data if valid. The transmitted data consisting of two identical data words is examined bit by bit as it is received. The first five bits are assumed to be address bits and must be encoded to match the address inputs at the receiver. If the address bits match, the next four (data) bits are stored and compared to the last valid data stored. If this data matches, the VT pin will go high on the 2nd rising edge of the 9th bit of the first word. Between the two data words no signal is sent for three data bit times. As the second encoded word is received, the address must again match, and if it does,the data bits are checked against th,e previously stored data bits. If the two words of data (four bits each) match, the data is transferred to the output data latches and will remain until new data replaces it. At the same time, the Valid Transmission output pin is brought high and will remain high until an error is received or until no input signal is received for four data bit times. Although the address information is encoded in trinary fashion, the data information must be either a one or a zero. A trinary (open) will be decoded as a logic one. M145028 This receiver operates in the same manner as the M145027 except that nine address bits are used and no data output is available. The Valid Transmission output is used to indicate that a valid signal has been received. Although address information normally is encoded in trinary, the designer should be aware that, for the M145028, the ninth address bit (A9) must be either a one or a zero. This part, therefore, can accept only 2 x 3 8 = 13,122 different codes. A trinary (open) A9 will be interpreted as a logic 1. However if the transmitter sends a trinary (or logic 1) and the receiver address is a logic 1 (or trinary) respectively, the . valid transmission output will be shortened to the R1 x Cl time constant. DOUBLE TRANSMISSION DECODING Although the encoder sends two words for error checking, a decoder does not necessarily wait for two transmitted words to be received before issu ing a val id transmission output. Refer to the flowcharts in Figure 7 and 8. ~4/_1_0________________________ ~~~~~~~~~:~~©~ 672 ___________________________ M145026-M145027-M145028 Fig. 1 - Encoder block diagram M145026 !=IS ,0.1101 RTC o-~+--+-"----1--t---+--+-+-1',-:>t--, ,0.2102 o--+--+-.,----1--t---t---+-K "">1-----4 ~S5 AS/OS o-"-+--+-.,----1--K : > f - - - - - - - - - - + - - 1 A6I060-"-+--+-.,-K ::>1-------------1 ,0.7107 0-'--+--+--1K:>+-----------~---t A81080--'-+_4C>I-----------------t A9ID9o-"'l<:::::>f-------------------' Fig. 2 - Decoder block diagram M145027 , - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - ' ' ' - - 10 ~~~~SM1S5'C 06 07 4-BIT SHIFT REGISTER 08 09 A2~~-t__-_t_--+__4C A3~~_4--+__4C ~*------t_--~ A4 O-:~_4--K 1-_-..0._______09 ~~TA '0 ~ A5 '6 ~vDD B ,~Vss 5_5116 ----------------------------~~~~~~~~~:J?JI ________________________~5~/1~O 673 M145026 - M145027 - M145028 Fig. 3 - DecOder block diagram M145028 SEQUENCER CIRCUIT 9 6 6 5 4 9-BIT SHIFT REGISTER ~.~5--4---~--~---+~K ~~----------------~--~ 9 OAT A 1---__-+--__---0 IN ~VOD 15 14 S_6171 PIN DESCRIPTION M145026 ENCODER A1/D1-A9/D9 These inputs will be encoded and the data serially output from the encoder. Vss The most negative supply (usuafly ground). RS,CTC,RTC These pins are part of the oscillator section of the encoder. If an external signal source is used instead of the internal oscillator it should be connected to the RS input and the RTC and CTC pins should be left open. TE This Transmit-Enable (active low) input will initiate transmission when forced low. A pullup device will keep this input high normally. Data Out This is the output of the encoder that will present the serially encoded signals. Voo The most positive supply. M145027/M145028 DECODERS A1-A5 (M145027) 1 A1-A9 (M145028) These are the address inputs that must match the encoder inputs A 110 1-A5/05 in the case of M145027 or A 1/01-AO/09 in the case of M145028, in order for the decoder to output data. ~6/~1~O_______________________ ~~~~~~~~~~~ 674 __________________________ M145026 - M145027-M145028 06-09 (M145027) These outputs will give the information that is presented to the encoder inputs A6/D6-A9/D9. Note: Only binary data will be acknowledged, a trinary open will be decoded as logic one. R1, C1 These pins accept a resistor and capacitor that are used to determine whether a narrow pulse or a wide pulse has been encoded. The time constant R1 x C1 should be set to 1.72 transmit clock periods. R1C1 = 3.95 RTC x CTC. R2/C2 This pin accepts a resistor to Vss and a capacitor to Vss that are used to detect both the end of an encoded word and the end of transmission. The time constant R2 x C2 should be 33.5 transmit clock periods (four data bit periods). This time constant is used to determine that the Data In input has remained low for four data bit times (end of transmission). A separate comparator looks at a voltage equi· valent two data bit times (0.4 R2C2) to detect the dead time between transmitted words. R2C2 = 77 x RTC x CTC. Valid Transmission, VT This output will go high when the following conditions are satisfied: 1. the transmitted address matches the receiver address, and 2. the transmitted data matches the last valid data received (M 145028 only). VT will remain high until either a mismatch is received, or no input signal is received for four data data bit times. Voo The most positive supply Vss The most negative supply (usually ground). Figure 4 - Encoder Oscillator Information This oscillator will operate at a frequency determined by the external RC network; i.e .. 1 f "'" 2.3 x RTC x CTC ~CTC " --------- ------------ -I~ --- - " for 1 kHz";;; f ";;;400 kHz -------- where: CTC JNTERNAL ENABLE (Hz) = CTC + C layout + 12 pF RS '" 2 RTC RS ),20 k RTC ).10 k 400 pF < CTC < JlF The value for RS should be chosen to be about 2 times RTC. This range will ensure that current through RS is insignificant compared to current through RTC. The upper limit for RS must ensure that RS x 5 pF (input capacitance) is small compared to RTC x CTC. ____________________________ ~~~~~~~~~:~~©~ __________________________ 7~/l_0 675 M145026 - M145027 -M145028 For .frequencies outside the indicated range, the formula will be less accurate. The actual oscillation range of this circuit is from less than 1 Hz to over 1 MHz. Figure 5 - Encoder/Decoder Timing Diagram --D _______________________________:~~~~~:~~~~____ ----__________________________ ::::..:::"~:~~:,.O" 1 0M .. , 'I 1 ," .., 1 I' 'I OM .. , I ,-", I --~,~~~~ 'I' I I' 'I 1 'I 1s1.ORO lndWORO I l ~~~I?,T1I . . . 5MlSS10H,---------------'M"'I4.::50=2'-'7AN=D..::M:::14:::50:::28:.,:D:=ECO=0E:::;RS'-_ _ _ _ _ _ _ _---l'---l ========================~xC=== Figure 6 - Encoder Data Waveforms (M145026) ENCODER OSCILLATOR (PINI2) DATA OUT , (PIN'S) ENCODED "ONE" U I* U 1* ENCODED ·ZERO'" LJl ' n ENCODED '"OPEN'" U 1* .'--_ _ _ _ _..... I. I. U .J L . ._ _ _ _ _ _ Ul.L-._ _ _ _ _ --...J DATA PULSE PERIOD .1 DATA BIT PERIOD .1 *'50 ns PULSE APPEARS AT THIS POINT (THIS DOES NOT AFFECT THE TRANSMITTER/RECEIVER OPERATION) 8/10 676 Figure 7 - M145027 Flowchart Figure 8 - M145028 Flowchart SERIALLY SHIfT THE DISABLE "'1 ON THE ,., ADORESS ""SNATCH ADDR£SS<"l","T"l* INTO THE STORAGE AND IGNORE THE REST Of THIS WORD ~ R~ ""ell ©. ~i! ~o ",,!II: ©iji ~o DISABLE YT ON THE ,., DATA MISMATCH ~z s: ~ -'=" (J1 oI\) 0') I s: ~ -'=" (J1 oI\) ...... I s: ~ -'=" (J1 Cll -..J -..J I~>-' 0 oI\) *fOR SHIFT REGiSTER COMPARISONS,a"T"ls store<::l as a"'!" co M145026 -M145027 -M145028 Figure 9 - M145027/M145028 (fmax vs. Clayoutl fma,x (KHz) "1145026 Clock 500 10 15 20 25 30 35 40 4S 50 S 61831 C1ilyOUI{PFIOfl plns)-S{M145021): Pins 1.5 and12-15(M14502B) Figure 10 - Typical Application '00 '00 I j M145027 M145026 j 1. CTC':CTC.Clayoul.12pF lOOpfSCTCSI5j.JF RT(;;,IOK;R5::'::2RT R12:10K CE':t.QOpF R22:100K C22:700pF ll __ VT '-_...,..._--' fos c .-----.!.2.3RTC CTC' R1Ch3.95RTCCTC R2C2.17RTCCTC --------{L--_"...:,.:.:'...:',-o'_J REPEAT Of ABOVE (CTC' e CTC + 20 pFI Example RIC Values (All Resistors and Capacitors are ± 5%) fos c (kHzl RTC CTC' RS Rl 362 181 88.7 42.6 21.5 8.53 1.71 10 k 10 k 10 k 10 k 10 k 10 k 50k 120 pF 240 pF 490pF 1020 pF 2020 pF 5100 pF 5100 pF 20 k 20 k 20 k 20 k 20 k 20 k 100 k 10 10 10 10 10 10 50 _10-'-1.=.1.:..0 _ _ _ _ _ _ _ _ _ _ _ _ 678 Cl k k k k k k k 470 pF 910 pF 2000 pF 3900 pF 8200 pF 0.021'F 0.021'F R2 100 100 100 100 100 200 200 C2 k k k k k k k ~ ~~~~m~1!~:~~lt 910 pF 1800 pF 3900 pF 7500 pF 0.0151'F 0.021'F O.lI'F MC1488 RS232C QUAD LINE DRIVER • CURRENT LIMITED OUTPUT± 10 mA TYP. • POWER-OFF SOURCE IMPEDANCE 300nMIN. • SIMPLE SLEW RATE CONTROL WITH EXTERNAL CAPACITOR • FLEXIBLE OPERATING SUPPLY RANGE • INPUTS ARE TTL AND IlP COMPATIBLE DIP-14 (0.25) (Plastic and Ceramic) SO-14J DESCRIPTION The MC1488 is a monolithic quad line driver designed to interface data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. RS232C. ORDER CODES: MC1488P (Plastic DIP) MC1488L (Ceramic DIP) MC1488D (SO-14) TYPICAL APPLICATION: RS232C Data Transmission. 6 MC1489 llJr·n~ ll'_12V l_~ TTL TTL ,::~"V , or iJP :: 'I - p...:-_----' r--t---'_j R5-232C CABLEAND CONNECTOR 1 14 MC~89 Or iJP 3 -- ~.6_ 7 . _. I J 1 1'--_..--_.... ~ September 1988 .. 7776 1/7 679 MC1488 ABSOLUTE MAXIMUM RATINGS Symbol Power Supply Voltage Value 15 Unit Vs Parameter VEE Power Supply Voltage -15 V VIR Input Voltage Range - 15 <; VIR <; 7 V Vo Output Signal Voltage ± 15 V o to 75 °C - 65 to 150 °C Tamb Operating Ambient Temperature T stg Storage Temperature Range CONNECTION DIAGRAMS (top views) J VEE 1 14 INPUT 1 2 13 ] INPUT 48 OUTPUT 1 3 12 INPUT 2A I 4 11 ] OUTPUT 4 INPUT 29 I 5 10 ] INPUT 38 OUTPUT 2 I 6 9 ] INPUT 3A GND I 7 8 ] LOGIC DIAGRAM +Vs ~ INPUT V 11 ~ 13 12 4A 1 7 0 14 0 9 ~ 10 OUTPUT 3 S-1177 S _7778 THERMAL DATA Rth 217 680 j-amb I Thermal Resistance Junction-ambient max Plastic DI P - 14 Ceramic DIP - 14 SO - 14 200°C/W 165°C/W 165°C/W MC1488 ELECTRICAL CHARACTERISTICS (V s= 9 ±1 a % V, V E E= - 9 ±1 a % V, T amb = a to 75 '{; unless otherwise specified) Symbol Test Conditions Parameter IlL Input Current Low Logic State (VIL = OV) IIH Input Current High Logic State (VIH = 5V) Output Voltage High Logic State RL= 3KQ VIL = 0.8V. Vs = 9V, VEE = -9V VIL = 0.8V, Vs = 13.2V, VEE = -13.2V VOH Output Voltage VOL los + los Ro Is lEE Pc Min. Typ. 1 6 9 Low Logic State RL = 3 KD -6 VIH = 1.9V, VEE =-9V, Vs =9V VIH = 1.9V, VEE =-13.2V, Vs = 13.2\ -9 Max. Unit Fig. 1.6 mA 1 10 ~A 1 7 10.5 V V 2 2 -7 - 10.5 V V 2 2 + Positive Output Short - circuit Current 6 10 12 mA 3 + Negative Output Short-circuit Current -6 - 10 -12 mA 3 Q 4 15 4,5 19 5.5 20 6 25 7 34 12 mA 5 Output Resistance Vs = VEE = 0 IVol = ± 2V Positive Supply Current (Rj = =) VIH VIL VIH VIL VIH VIL Vs Vs Vs Vs Vs Vs Negative Supply Current (RL ==) Power Consumption SWITCHING = 1.9 V =0.8 V = 1.9 V = 0.8 V = 1.9 V =0.8 V = = = = = = 9V 9V 12 V 12 V 15 V 15 V VIH = 1.9 V VIL = 0.8 V VIH=1.9V VIL = 0.8 V VIH=1.9V VIL = 0.8 V VEE = - 9 V VEE=-9V VEE=-12V VEE=-12V VEE=-15V VEE=-15V Vs = 9 V Vs = 12 V VEE = - 9 V V EE =-12V 300 - 13 -17 -15 - 18 - 23 -15 - 34 - 2.5 333 567 mA ~A mA ~ mA mA 5 mW CHARACTERISTICS (Vs = ± 9 ±1 % V, VEE = - 9 ± 1 % V, Tamb = 25°C) tpLH Propagation Delay Time Zj = 3 KQ and 15 pF 275 350 ns tTHL Fall Time Zj = 3 Kn and 15 pF 45 75 ns 6 tpHL Propagation Delay Time Zj = 3 Kfl and 15 pF 110 175 ns 6 trLH Rise Time Zj = 3 Kn and 15 pF 55 100 ns 6 6 * MaXimum package power diSSipation may be exceeded If all outputs are shorted simultaneously 3/7 681 MC1488 TEST CIRCUITS Figure 1 : Input Current. Figure 2 : Output Voltage. J 01 "------------~-----------~ Figure 3 : Output Short-Circuit Current. Figure 4 : Output Resistance (power off). - ~---- - ------------------, 0"'-......,._...,.--' Figure 5 : Power Supply Currents. ----- Figure 6 : Switching Response. ~-------~-----~-, ';~v 1.'Kn I 115P f ' ' - -_ _ _ _ 0' VIL +O.8V " tTHl and tTlH measured IO·f. to 90"'. ~--~~- 4/7 682 --------- MC1488 Figure 8 : Short-Circuit Output Current vs. Temperature. Figure 7 : Transfer Characteristics vs. Power Supply Voltage. Yo (V) I" (mA) / ; _V.ot12V 1- Vs='±9V ., _,--Vs= ±6V +12 .' III '9 +3 .6 .3 _3 ~ _. l: =Ff-l-rl -3 -6 _9 -12 o 0.2 0.4 Yo 0.6 -, -" 0.8 1.2 _55 50 100 lamb(-C) 1.4 Figure 9 : Output Slew-Rate Load Capacitance. m Figure 10 : Output Voltage and Current-Limiting Characteristics. G 0)812 SR :~ (V/~s) , 10 -~ J.-l-: . 1 +~ ·+11 • =-= ff=" 10 \.. \ +0 r--.... ~ +4 \ ~- 1- . I 4 6 8 10 101 A· \ \ \ -0 o _12 VI~ -16 °o,OV losl\,- 1.9V I • ~ \ "0 VS=VEE=+9V 4 2 ~ _4 . IC' 3M LOAD LINE \ .~.I--' ~VO 10 - {rnA} & 8 _20 c! 1 _16 _12 _8 _4 0 +4 +8 +12 ... 16 Vo(Y) Figure 11 : Maximum Operating Temperature vs. Power-Supply Voltage. G_5811, E I 12 - ......... "" Vs 14 10 3 "- 3Kflx4 -- - "'-. ~ 6 - ~ 0 - ~ " ~ ~ 7 -- ..... I VE.E f---- --- I _55 +50 +100 lamb (.C) 5/7 683 MC1488 APPLICATION INFORMATION The Electronic Industries Association (EIA) has released the RS232C specification detailing the requirements for the interface between data processing equipment. This standard specifies not only the number and type of interface leads, but also the voltage levels to be used. The MC1488 quad driver and its companion circuit, the MC1489 quad receiver, provide a complete interface system between DTL or TTL logic levels and the RS232C defined levels. The RS232C requirements as applied to drivers are discussed herein. The required driver voltages are defined as between 5 and 15 V in magnitude and are positive for a logic "0" and negative for a logic "1 ". These voltages are so defined when the drivers are terminated with a 3000 to 70000 resistor. The MC1488 meets this voltage requirement by converting a DTLITTL logic level into RS232C levels with one stage of inversion. The RS232C specification further requires that during transitions, the driver output slew rate must not exceed 30 V per flS. The inherent slew rate of the MC1488 is much too fast for this requirement. The current limited output of the device can be used to control this slew rate by connecting a capacitor to each driver output. The required capacitor can be easily determined by using the relationship C = los x liTI liV from which Figure 12 is derived. Accordingly, a 330 pF capacitor on each output will guarantee a worst case slew rate of 30 V per J.ls. connecting cable. The worst possible signal on any conductor would be another driver using a plus or minus 15 V, 500 mA source. The MC1488 is designed to indefinitely withstand such a short to all four outputs in a package as long as the power-supply voltages are greater than 9.0 V (i.e., VS ::0: 9.0 V ; VEE S - 9.0 V). In some power-supply designs, a loss of system power causes a low impedance on the power-supply outputs. When this occurs, a low impedance to ground would exist at the power inputs to the MC1488 effectively shorting the 3000 output resistor to ground. If all four outputs were then shorted to plus or minus 15 V, the power dissipation in these resistors would be excessive. Therefore, if the system is designed to permit low impedances to ground at the power-suppies of the drivers, a diode should be placed in each power-supply lead to prevent over-heating in this fault condition. These two diodes, as shown in Figure 13, could be used to decouple all the driver packages in a system. (These same diodes will allow the MC1488 to withstand momentary shorts to the ±15 V limits specified in the earlier Standard RS232B). The addition of the diodes also permits the MC1488 to withstand faults with power-supplies of less than the 9.0 V stated above. The maximum short-circuit current allowable under fault conditions is more than guaranteed by the previously mentioned 10 mA output current limiting. The interface driver is also required to withstand an accidental short to any other conductor in an inter- Figure 12 : Slew Rate vs. Capacitance for Isc = 10mA. Figure 13: Power Supply Protection to Meet Power-off Fault Conditions. G S81') SR ,t-=FF Iv) "~ ''::~f\ !-f-I- 11 ! L'l~ ! -- ' I I ~. t- :"S -c=!OVf~S <--.. - - 10 ---:- ,- ,I ,. . ---, •, -- 65 6/7 684 I ---+- 1~333PF I 10 I 2 10 2 6. 8 ) 10 2 I 4 68 C (pFl L _________________._ ._ __ MC1488 OTHER APPLICATION The MC1488 is an extremely versatile line driver with a miriad of possible applications. Several features of the drivers enhance this versatility: 1. Output Current Limiting - this enables the circuit designer to define the ouptut voltage levels independent of power-supplies and can be accomplished by diode clamping of the output pins. 2. Power-Supply Range - as can be seen from the schematic drawing of the drivers, the positive and negative driving elements of the device are essentially independent and do not require matching po- wer-supplies. In fact, the positive supply can very from a minimum seven volts (required for driving the negative pulldown section) to the maximum specified 15 V. The negative supply can vary from approximately - 2.5 V to the minimum specified - 15 V. The MC1488 will drive the ouptutto within 2 Vofthe positive or negative supplies as long as the current output limits are not exceeded. The combination of the current-limiting and supply-voltage features alIowa wide combination of possible outputs within the same quad package. 7/7 685 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I MC1489 MC1489A QUAD LINE RECEIVERS • • • • INPUT RESISTANCE -3.0 K to 7.0 Kn INPUT SIGNAL RANGE - ± 30 V INPUT THRESHOLD HYSTERESIS BUILT-IN RESPONSE CONTROL: a) LOGIC THRESHOLD SHIFTING b) INPUT NOISE FILTERING DIP-14 (Plastic (0.25) and Ceramic) I I I DESCRIPTION The MC1489 monolithic quad line receivers are designed to interface data therminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. RS-232C. l I SO-14J aRDER CODES: MC1489L. MC1489AL (DIP-14 Ceramic) . MC1489P. MC1489AP L__ ____ ~~~~~§:~?~4~9A~~O~_1 TYPICAL APPLICATION: RS232C Data Transmission +Vs TTL TTL ~p ~p or or p..:-_--" r-1---;_-<' L ---------- September 1988 RS-232C CABLEAND CONNECTOR ------------------- ------ 1/7 687 MC1489-MC1489A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit 10 V Vs Power Supply Voltage VI Input Voltage Range ± 30 V IOL Output Load Current 20 mA Ptot 1 W o to 75 'C - 65 to 150 °C Power Dissipation Tamb Operating Ambient Temperature T stg Storage Temperature Range CONNECTION DIAGRAMS (top view) INPUT A 14 RESPONSE CONTROL A 13 INPUT D OUTPUT A 12 h RESPONSE INPUT B 11 ~ RESPONSE CONTROL B 10 OUTPUT B 9 ~ INPUT C h RESPONSE GROUND 8 ~ OUTPUT ~ CONTROL D OUTPUT D ~ CONTROL C C SCHEMATIC DIAGRAM (1/4 of circuit shown) , -____~----~-1-40VS 9Kll 5Kll t.7KJl OUT 1NPUT L---+-----~----~----~~~OGND * 2/7 688 MC1489=6.7KO Me t4B9A =t.6KO MC1489-MC1489A ELECTRICAL CHARACTERISTICS (Response control pin is open; V s unless otherwise specified) Symbol Parameter Test Condtions = 5 V, Min. IIH Positive Input Current VIH = 25 V VIH = 3 V IlL Negative Input Current VIL = - 25 V VIL=-3V VIH Input Turn-on Threshold Voltage Tamb =25 0 C VOL" 0.45 IL = 10 mA for MC1489 for MC1489A 1 1.75 0.75 VIL Input Turn-off Threshold Voltage Tamb =25 0 C VOH ~ 2.5 V IL = - 0.5 mA VOH Ouptut Voltage High VIH = 0.75 V IL =- 0.5 mA IL = 0.5 mA Input Open Circuit VOL Output Voltage Low VIL = 3 V los Output Short Circuit Current Is Power Supply Current All gates "on" VIH = 5 V Pc Power Consumption VIH = 5 V SWITCHING CHARACTERISTICS (Vs = 5 \/, Typ. 0 Max. 8.3 - 3.6 - 0.43 - 8.3 1.95 2.5 2.5 10 = a mA = 25 = 0 to 75 3.6 0.43 IL = 10 mA Tamb T amb 0 C Unit mA mA .1.5 2.25 V 1.25 V 4 4 5 5 V V 0.2 0.45 V - 3 - 4 mA 16 26 mA 80 130 mW C, see Fig. 1) Typ. Max. Unit tpLH Propagation delay Time RL = 3.9 KQ 25 85 ns ITLH Rise Time RL = 3.9 KQ 120 175 ns tpHL Propagation Delay Time RL = 390 Q 25 50 ns tTHL Fall Time RL = 390 Q 10 20 ns Symbol Test Condtions Parameter Min. TEST CIRCUITS Figure 1 : Switching Response . Figure 2 : Response Control Node. • 5V lN3064K4 1/4 NCI489A ~ RESPONSE NOOE "'0 'TLH and tTHL measured 10"1._90"1. C, capacitor is for noise filtering R, resistor is for threshold shifting 317 689 MC1489-MC1489A Figure 3 : Input Current. Figure '4 : Output Short-Circuit Current. Figure 5 : Output Voltage and Input Threshold Voltage, Figure 6 : Power Supply Current. " 7 S_179l TYPICAL CHARACTERISTICS (Vs =5 Figure 7 : Input Current. V, T amb = 25°C unless otherwise specified) Figure 8 : MC1489 Input Threshold Voltage Adjustament. G G- 5828 '; rr-tR, 1m. J V V -2 -4 -6 V ./ 5Kn Vlh .5V ./ ~;~ ./ 1-,- I R, 13Kfl t-- RT I1Kfi Vlh _5V ,- I II ! T I _ 25 -20 -15 -10 -5 0 5 10 15 Vi (V) -3 -2 _1 ~Vth J: 1--,- , "tr , ; r _'0 690 V'h .5V R, = : -8 4/7 .. ~ R, I l- ~819 MC1489-MC1489A Figure 9: MC1489A Input Threshold Voltage Adjustment. Figure 10 : Input Threshold Voltage vs. Temperature. G !l1I3' V,H - -t Jt-tt~ (VI 3.2 2.B i 2A f 1.6 r-r. -tlf -±~fH, ~9AVIH 1 1.2 MC14B9 "IH DB MC1489V1L ~ Me 1489A \IlL D.4 -3 -2 "Vi (V) L---i-.-' H ,J 1J -60 - .. 0 -rfTTnt -20 0 20 40 60 090 Tamb'·C) Figure 11 : Input Threshold vs. Power-Supply Voltage. V,H (vi _831 G' V1H MC14B9A 6 4 2 V 1H MC14B9 Vll MC1489 D. B V MC1489A IL D. 6 - - o. 4 D. 2 10 Vs (V) APPLICATION INFORMATION GENERAL INFORMATION The Electronic Industries Association (EIA) has released the RS-232C specification detailing the requirements for the interface between data processing equipment and data communications equipment. This standard specifies not only the number and type of interface leads, but also the voltage levels to be used. The MC1488 quad driver and its companion circuit, the MC1489 quad receiver, provide a complete interface system between DTL or TTL logic levels and the RS-232C defined levels. The RS-232C requirements as applied to receivers are discussed herein. The required input impedance is defined as between 3000 nand 7000 n for input voltages be- tween 3.0 and 25 V in magnitude; and any voltage on the receiver input in an open circuit condition must be less than 2.0 V in magnitude. The MC1489 circuits meet these requirements with a maximum open circuit voltage of one VSE. The receiver shall detect a voltage between - 3.0 and - 25 V as a Logic "1" and inputs between + 3.0 and + 2.5 V as a Logic "0". On some interchange leads, an open circuit of power "OFF" condition (300 n or more to ground) shall be decoded as an "OFF" condition or Logic "1 ". For the reason, the input hysteresis thresholds of the MC1489 circuits are all above ground. Thus an open or grounded input will cause the same output as a negative or Logic "1" input. 5/7 691 MC1489-MC1489A DEVICE CHARACTERISTICS The MC1489 interface receivers have internal feedback from the second stage to the input stage providing input hysteresis for noise rejection. The MC1489 input has typical turn-on voltage of 1.25 V and turn-off of 1.0 V for a typical hysteresis of 250 mV. The MC1489A has typical turn-on of 1.95 V and turn-off of 0.8 V for typically 1.15 V of hysteresis. Each receiver section has an external response control node in addition to the input and output pins, thereby allowing the designer to vary the inputthreshold voltage levels. A resistor can be connected between this node and and an external power supply. Figure 2, 4 and 5 illustrate the input threshold voltage shift possible through this technique. pulses. Figure 8 and 9 show typical noise-pulse rejection for external capacitors of various sizes. These two operations on the response node can be combined or used individually for may combinations of interfacing applications. The MC1489 circuits are particularly useful for interfacing between MOS circuits and MDTLlMTTL logic systems. In this application, the input threshold voltages are adjusted. (with the appropiate supply and resistor values) to fall in the center of the MOS voltage logic levels. (See Figure 10). This response node can also be used for the filtering of the high-frequency, high-energy noise The response node may also be used as the receiver input as long as the designer realizes that he may not drive this node with a low impedance source to a voltage greater than one diode above ground or less than one diode below ground. This feature is demonstrated in Figure 11 where two receivers are slaved to the same line that must still meet the RS-232C impedance requirement. Figure 12: Typical Turn-on Threshold vs. Capacitance from Response Control Pin to GND. Figure 13 : Typical Turn-on Threshold vs. Capacitance from Response Control Pin to GND. Vi IV) I M[14B9 -t-t l_~.i.1 300pF 50°1._ 10 6/7 692 100 1000 W{ns} 10 100 1000 W(ns) MC1489-MC1489A Figure 14: Typical Paralleling of Two MC1489/A Receivers to Meet RS-232C. RESPONSE. :- ---------------- ---:=~.1 CONTROL PIN· -r~ ftJ ,, ._~ I I I ____~ ___._______ ._____________ ._____________.J 7/7 693 o_~ _______ MC3479C STEPPER MOTOR DRIVER • SINGLE SUPPLY OPERATION + 7.2 V TO + 16 V • 350 mAl COIL DRIVE CAPABILITY • BUILT IN FAST PROTECTION DIODES • SELECTABLE CW/CCW AND FULL/HALF STEP OPERATION • SELECTABLE HIGH/LOW OUTPUT IMPEDANCE (HALF STEP MODE) • TTL/CMOS COMPATIBLE INPUTS • INPUT HYSTERESIS: 250 mV TYP. • PHASE LOGIC CAN BE INITIALIZED TO PHASE A • PHASE A OUTPUT DRIVE STATE INDICATION Powerdip 12 + 2 + 2 ORDER CODE. MC3479C ' _ _ _ _ _o _ o _ _ _ o _ o_ _ _ _ _ o __ ~ _ _- - - - " INPUT TRUTH TABLE DESCRIPTION INPUT lOW The MC3479C is designed to drive a two-phase stepper motor in the bipolar mode. The circuit consists of four input selections a logic decoding/sequencing section two driver stages for the motor coils and an output to indicate the Phase A drive state. INPUT HIGH CW/CCW CW CCW FIHS Full Step Half Step OIC High Z ClK Positive Edge Triggered low Z i BLOCK DIAGRAM ~ _ _ _ '___ 0 _ - - I 0_ _ _ _ _ _ _ _ _ 0_ _ 0_ _ _ _ _ _ _ _ _ __ Vs r -. .-~-----'!..()L 1 CLK L2 CW/CCW VD L3 FULL/HALF STEP I ole I I 5-9181/1 BIAS/SET o_ _ _ _ September 1988 o_~ GND 4.5.12.13 _ _ _ _ _ o _ _0 __ o_ _ _ _ J I 1/7 695 MC3479C ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vs Supply Voltage 16 Voc Vo Clamp Diode Cathode Voltage (pin 1) Vs Voc VOD Driver Output Voltage (pins 2, 3, 14, 15) Vs Voc 100- Driver Output Current/Coil Y'N Parameter Input Voltage (pins 7, 8, 9, 10) ± 500 mA - 0.5 to 7 Voc Iss Bias/Set Current (pin 6) 10 mA VOA Phase A Output Voltage (pin 11) 16 Voc Phase A Sink Current (pin 11) 20 mA Junction Temperature 150 'C - 55 to 150 'C IDA Tj Tstg Storage Temperature range RECOMMENDED OPERATION CONDITIONS Symbol Parameter Min. Max. 7.2 16 V Clamp Diode Cathode Voltage (DC) - Vs V mA Vs Supply Voltage (DC) Vo Unit Driver Output Current (per coil) - 350 V, DC Input Voltage (pin 7, 8, 9, 10) 0 5,5 V Iss Bias/Set Current (outputs active) - 300 75 flA 100 IDA Tamb Phase A Sink Current 0 8 mA Operating Ambient Temperature 0 70 °C CONNECTION DIAGRAMS ~ 1 Ll 16 15 LJ L1 l4 GND 13 GND GNO 1l GNO 11 PHASE A BIASfSET 6 eLK 10 CW/CCW Die 9 FULl/HA.lf STEP 5-9H12/1 THERMAL DATA Max 2/7 696 70 MC3479C PIN DESCRIPTION Symbol Name Pins Description Vs POWER SUPPLY 16 Power supply pin for both the logic circuit and the motor coil current. Voltage range is 7.2 V to 16 V. GND GROUND 4-5-12-13 Ground Pins for the Logic Circuit and the Motor Coil Current. The physical configuration of the pins dissipating heat from within the package. Vo CLAMP DIODE 1 This pin is used to protect the outputs where large voltage spikes may occur as the motor coils are switched. Typically a diode is connected between this pin and pin 16. See figure 5. L1, L2, L3, L4 DRIVER OUTPUTS 2-3 14-15 B/S BIAS/SET 6 This pins is typically 0.7 V below Vs. The current out of this pin (through a resistor to ground) determines the maximum output sink current. 11 the pin is opened (Iss < 5.0 ~A) the outputs assume a high impedance condition while the internal logic presets to a Phase A condition. CK CLOCK 7 The positive edge of the clock input switches the outputs to the next position. This input has no effect if pin 6 is open. F/HS FULUHALF STEP 9 When low (logic 0) each clock pulse will cause the motor to rotate one full step. When high, each clock puis!;! will cause the motor to rotate one-half step. (see figure 4 for sequence). CW/CCW CLOCKWISE COUNTERCLOCKWISE 10 This input allows reversing the rotation of the rotation of the motor. (see figure 4 for sequence). OIC OUT IMPEDANCE CONTROL 8 This input is relevant only in the half step mode (pin 9 > 2 V). When low (logic 0) the two driver out of the non-energized coil will be in a high impedance condition. When high the same driver outputs will be at a low impedance reference to Vs. (see figure 4). PhA PHASE A 11 This outputs indicate (when low) that the driver outputs are in the phase A condition (L 1 = L3 = VoHo ; L2 = L4 = VOLo). High Current Outputs for the Motor Coils. L 1 and L2 are connected to one coil and L3 and L4 to the other coil. 317 697 MC3479C DC ELECTRICAL CHARACTERISTICS(Specifications apply over the recommended supply voltage and temperature range, unless otherwise noted) ISymbol I Parameter Test Conditions I Min. I Typ. Max. I Unit INPUT LOGIC LEVEL VTLH Threshold Voltage (low to high) VTHL Threshold Voltage (high to low) VHYS III IIHl IIH2 2 Hysteresis Current V 0.8 V 0.4 V - 100 VI = 0.4 V VI = 5.5 V VI = 2.7 V 100 20 ~A DRIVER OUTPUT LEVELS VOHO Output High Voltage 100 =- 350 mA 100=-0.1mA IBs =- 300 ~ Vs - 2.0 Vs - 1.2 V V VOlO Output Low Voltage IBs =- 300 ~ 100 =- 350 mA 0.8 V Dvoo Difference Mode out Voltage Difference IBs =- 300 ~ 100 = 350 mA 0.15 V Cvoo Common Mode out Voltage Difference IBs =- 300 ~ 100=-0.1mA 0.15 V 10Zl Out Leakage-HiZ State 0< Vo < VM, IBs =5 ~A - 100 + 100 ~ loz2 Out Leakage·HiZ state 0< Voo < VM, IBs = - 300 ~ Pin 9 = 2 V Pin 8 = 0.8 V - 100 + 100 ~ 12 mA 75 mA CLAMP DIODES Forward Voltage 10 =350 mA Leakage Current PHASE A OUTPUT Out Low Voltage lOA = 8 mA Off State Leakage Current VOA = 16.5 V POWER SUPPLY IssB Power Supply Current in Stand by State 6 Power Supply Current (100 = 0) ; IBs = - 300 4/7 698 VBs = Vs ~A) L1 = VOHo L3 = VOHo L2 = VOlo L4 = VOHo MC3479C BIAS SET CURRENT IBS Notes: I Bias Set Current I to set PHASE A 3. DVOD ~ I VOD1.2 - VOD3.4 I VOD1.2 ~ (VOHD1 - VOHD2) or (VOHD2 - VOLD1) AND 4. eVOD ~ I VOHD1 - VOHD2 or VOHD3 - VOHD4 I AC SWITCHING CHARACTERISTICS (T amb Symbol Parameter = 25 VOD3.4 'C ; V M - 5 ~ flA (VOHD3 - VOHD4) OR (VOHD4 - VOHD3) = 12 V) Test Conditions Min. Typ. Max. Unit 30 KHz ICK Clock Frequency PWCKH Clock Pulse Width HIGH 10 PWCKl Clock Pulse Width lOW 20 fls flS 0 fls tsu Set-up Time CW/CCW and F/HS 5 tHO Hold Time CW/CCW and F/HS 10 tpCD Propagation Delay ClK-to Driver Out 8 fls tpBSD Propagation Delay Bias/Set to Driver Output 1 fls tpHLA Propagation Delay ClK-to Phase A lOW 12 fls tpLHA Propagation Delay ClK-to Phase A HIGH 5 fls fls Figure 1: AC Test Circuit. >1211 L2 1KIl. 56KIl. BIASI SET C/K MC3479c 14 O/C 8 FIHS CW/CCW 10 PHASE A S-91B3 5/7 699 MC3479C Figure 2 : Typical Application Circuit. DIGITAL INPUTS PHASE A ~ " CLOCK cr--- 7 DIRECTION I MOTOR 10 G ~~~~'HALFo--­ ~~~~lcE( S-9187 4049 Figure 3 : Bias/Set Timing (refer to fig.1). PWSS VM BIAS/SET INPUT L1-L4 OUTPUTS S-9161, Figure 4 : Clock Timing (refer to fig.1). 3V CIK Ll-L4 OUTPUTS 3V-----------------~ F/HS CW/cCW INPUTS 0-----------' I PHASEA OUTPUTS _ _ 6/7 700 ~5-.16~5l'5~V _________ ~_ MC3479C Figure 5 : Output Sequence. - - - -.. - --------_.- --- ------- - . eLK 8IASfSET~~,--+---~--~--~----~--~---7----~--~--~---7--~~ (W/CCW , ~,~,__~,~_~__~,____~__~__~'J'-~---'--~~--~--:----7I:ALB 11 L2 L3 L4 PHAS£A OUTPUT C:O A:S:C ~L'__~_~!r---:---'lL- BIA:O:C __i-__~__-1----~--i-__~__~r' , , 'I -,--~~~--t-~~__~~~--1L !7+--1 , , ,, r' ~~~'--!----L __~____r---:---,~r'----~--t---~-.J~ ~ ~ , , , ~~zl,__~__-f---i----L-__~__--i~l;__~~__r---~----;~ I I I 1 I , : I 1 1 I I 1 ' I I ~r,--~----~~~~:--~----~--~~r:--~~--7---'~ I I ~ HIGH IMPEDANCE (A)FUll STEP "ODE ffHS lOGIC ··0·· OIC DON· T CARE , , 11 ~ , I II 1m! , , Ll t1ZI I I L4 bd , I , I I , , , I , I , , 'A e ' : 8 0 ,, , , I WffhZl , I I ,, I I tzWM ,, ,, t'l/'ll4 I tzW.IA , I ,I , I 11 II L3 Izd I I I I I I , OUTPUT , I , I I C I 0 :E , F 0 I I I ,' , I ' bzaj- I f2'JJ G , wz1..I , , HIGH IMPEDA.NCE Cyi/ccw LOGIC "0" FfHS LOGIC •• , .. OIC lOGIC ··0·· J! ,, I , " ,1 I I H1A,18'C D I I I I ~(-~~--'---'----l __~___~__Jr---.----~--{---~---,L ~ , I , i I ~~~ I'l4I i" I I I PHASE A 8 I ~ I l4 , I I A B f?1Vd :, ' wzza I I Y?ZZm1 I I f'lM01 , , , A I (8) HALf STEP "ODE :I H nom WZVA I , I , , G : F I ____~__~__~__~____~_+-__~__~____~__~'~ I I , I I I U-1r-~-~--L---~~-~~r'-~-~--~ IC) HALF STEP MODE CWI(CW lOGIC "0" FfHS LOGIC "1 ,. OIC lOGIC ··0·· I _J 7/7 701 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I PBL3717A STEPPER MOTOR DRIVER • FULL STEP - HALF STEP - QUARTER STEP OPERATING MODE • BIPOLAR OUTPUT CURRENT UP TO 1 A • FROM 10 V UP TO 46 V MOTOR SUPPLY VOLTAGE • LOW SATURATION VOLTAGE WITH INTEGRATED BOOTSTRAP • BUILT IN FAST PROTECTION DIODES • EXTERNALLY SELECTABLE CURRENT LEVEL • OUTPUT CURRENT LEVEL DIGITALLY OR ANALOGUE CONTROLLED • THERMAL PROTECTION WITH SOFT INTERVENTION A monostable, programmed by an external RC network, sets the current decay time. The power section is a full H-bridge driver with four internal clamp diodes for current recirculation. An external connection to the lower emitters is available for the insertion of a sensing resistor. Two PBL3717As and few external components form a complete stepper rnotor drive subsystem. The raccomended operating ambient temperature ranges is from 0 to 70°C. The PBL3717 A is supplied in a 12 + 2 + 2 lead Powerdip package. DESCRIPTION The PBL3717 A is a monolithic IC which controls and drives one phase of a bipolar stepper motor with chopper control of the phase current. Current levels may be selected in three steps by means of two logic inputs which select one of three current comparators. When both of these inputs are high the device is disabled. A separate logic input controls the direction of current flow. Powerdip 12+2+2 ORDER CODE: PBL3717A BLOCK DIAGRAM I" REF 0--- ,- I,' I I 1223 Q I I \:z:l] 1.0. I I 11~5 I GNoo------i/:2 _ COMPARATOR INPUT September 1988 I, PULSE TIME :'EN5E RESISTOR 1/10 703 PBL3717A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vs Power Supply Voltage (pins 14, 3) 50 V Vss Logic Supply Voltage (pin 6) 7 V V, Logic Input Voltage (pins 7, 8, 9) 6 V Vc Comparator Input (pin 10) Vss Vr Reference Input Voltage (pin 11) 15 V 10 Output Current (DC operation) 1.2 A - 55 to + 150 °C DC Storage Temperature T stg 150 Operating Junction Temperature Tj CONNECTION DIAGRAM (top view) ~ 16 SENSE RESISTOR PULSE TIME IS OUTPUT A GND 13 GND GND 12 GND OUTPUT B I REFERENCE INPUT I INPUT PHASE ¢ 5- 6745 TRUTH TABLE Input 0 (pin 9) Input 1 (pin 7) H L H L H H L L No Current Low Current Medium Current High Current THERMAL DATA 11 40 • Soldered on a 35~ thick 20 em' P.C. board copper area. 2/10 704 PBL3717A PIN FUNCTIONS N° Name Function 1 OUTPUT B Output Connection (with pin 15). The output stage is a "H" bridge formed by four transistors and four diodes suitable for switching applications. 2 PULSE TIME 3 SUPPLY VOLTAGE B 4 GROUND Ground Connection. With pins 5, 12 and 13 also conducts heat from die to printed circuit copper. 5 GROUND See pin 4. 6 LOGIC SUPPLY 7 INPUT 1 This pin and pin 9 (INPUT 0) are logic inputs which select the outputs of the three comparators to set the current level. Current also depends on the sensing resistor and reference voltage. See truth table. 8 PHASE This TTL-compatible logic input sets the direction of current flow through the load. A high level causes current to flow from OUTPUT A (source) to OUTPUT B (sink). A schmitt trigger on this input provides good noise immunity and a delay circuit prevents output stage short circuits during switching. 9 INPUT 0 10 COMPARATOR INPUT 11 REFERENCE 12 GROUND 13 GROUND 14 SUPPLY VOLTAGE A 15 OUTPUT A 16 SENSE RESISTOR A parallel RC network connected to this pin sets the OFF time of the lower power transistors. The pulse generator is a monostable triggered by the rising edge of the output of the comparators (toll = 0.69 RT CT). Supply Voltage Input for Half Output Stage. See also pin 14. Supply Voltage Input for Logic Circuitry. See INPUT 1 (pin 7) . Input connected to the three comparators. The voltage across the sense resistor is feedback to this input through the low pass filter Rc Cc. The lower power transistor are disabled when the sense voltage exceeds the reference voltage of the selected comparator. When this occurs the current decays for a time set by RT CT, toll = 0.69 RT CT. A voltage applied to this pin sets the reference voltage of the three comparators, this determining the output current (also thus depending on Rs and the two inputs INPUT 0 and INPUT 1). See pin 4. See pin 4. Supply Voltage Input for Half Output Stage. See also pin 13. See pin 1. Connection to Lower Emitters of Output Stage for Insertion of Current Sense Resistor. 3/10 705 PBL3717A Figure 1 : Test and Application Circuit. REFERENCE LOGIC VOLTAGE SUPPLY + 5V +5V VR 11 LOGIC CONTROL INPUTS 11 7 10 9 6 MOTOR SUPPLY +36V 14 15 L'; 10 mH R'; 13 II MA L PBL3717A MOTOR WINDING PHASE MB RS 111 GND--~--~----~---4~----~- = 0). Figure 2 : Waveforms with MA Regulating (phase M 4/10 706 1 Ln-.:TO~N~ T~O.!...FF!-....In 7 c=~ ovLD VM=v. .S-VMA 5-6747/2 ....__ S -77l.0 PBL3717A ELECTRICAL CHARACTERISTICS (refer to the test circuit Vs = 36 V, Vss = 5 V, Tamb = 25 'C Min Max unless otherwise specified) Symbol Parameter Vs Supply Voltage (pin 3, 14) Vss Logic Supply Voltage (pin 6) Iss Logic Supply Current (pin 6) IR Reference Input Current (pin .11) Test Conditions Typ Unit 10 46 V 4.75 5.25 V 7 15 mA 0.75 1 mA 0.8 V Vss V pin 8 - 100 ~A pins 7, 9 - 400 ~A 10 ~A VR ~ 5 V LOGIC INPUTS Vil Input Low Voltage (pins 7, 8, 9) ViH Input High Voltage (pin 7, 8, 9) lil Low Voltage Input Current (pins 7, 8, 9) Vi High Voltage Input Current (pins 7, 8, 9) Vi liH 2 ~ 0.4 V ~ 2.4 V COMPARATORS VCl VCM VCH Ic Comparator Low Threshold Voltage (pin 10) VR Comparator Medium Threshold Voltage (pin 10) VR Comparator High Threshold Voltage (pin 10) VR ~ ~ ~ 5 V 5 V 5 V 10 1, ~ 10 1, ~ 10 1, ~ ~ ~ ~ L H 66 78 90 mV H L 236 251 266 mV L L 396 416 436 mV ± 20 ~A 35 ~s Comparator Input Current (pin 10) ~ 56 Kn toll Cutoff Time RT td Turn Off Delay (see fig. 2) loll Output Leakage Current (pins 1, 15) 10 ~ CT 1, H ~ ~ 820 pF 25 H 2 ~s 100 ~A SOURCE DIODE-TRANSISTOR PAIR Saturation Voltage (pins 1, 15) 1M ~- 0.5 A (see fig. 2) Conduction Period 1.7 2.1 Recirculation Period 1.1 1.35 Saturation Voltage (pins 1, 15) 1M ~- 1 A (see fig. 2) Conduction Period 2.1 2.8 Recirculation Period 1.7 2.5 ILK Leakage Current Vs ~ VF Diode Forward Voltage 1M ~- 0.5 A 1 1.25 1M ~- 1A 1.3 1.7 1M ~- 0.5 A 2 1M ~- 1A 5 Vsat V sat Isu~ Substrate Leakage Current when Clamped 46 V 300 V V ~A V mA 5/10 707 PBL3717A ELECTRICAL CHARACTERISTICS (continued) I Symbol I Parameter I Test Conditions Min. I Typ. I Max. I Unit SINK DIODE-TRANSISTOR PAIR Saturation Voltage (pins 1, 15) IM=0.5A 1.1 1.35 V 1M = 1 A 1.6 2.3 V ILK Leakage Current Vs = 46 V 300 !lA VF Diode Forward Voltage IM=0.5A 1.1 1.5 1M = 1 A 1.4 2 V sat APPLICATION CIRCUIT Figure 3 : Two Phase Bipolar Stepper Motor Driver. 0~f2-, 6 7 lOA I I II 11A Vs Vss Cl nf T F C2:f0.,,.,F UI 14 3 15 MAA PBL3717A 9 PhA 82 4 5 GND .pF ~CT RT] K 56Il 8 820pF 1 1 2 16 I 4 5 12 I 13 ..L.. RS[ III 1 K Il .:..::; 6/10 708 IMA - .JYY"\.. ( 1MB ( ( RC 10 16 MBB 1'--- PBL3717A 7 [OB 9 MBA RC CC~= ~~O pF PhB lIB 10 ~ 82~~f= RS[ ~ III :~~~ RT 56 Kil 12 11I FROM pPROCESSOR 13 MAB 11 6 1 I 3 14 '5 I S~6748/1 EPPER O~TOTOR V I PBL3717A Figure 4: P.C. Board and Component Layout of the Circuit of fig. 3 (1 : 1 scale). Cc Cc o~~m c::::) .cQ beT MRs RsOO C3 c::::> (2 c:::::::2 -eRr c::::)C i Cf cs- 0215 Figure 5 : Input and Output Sequences for Half Step and Full Step Operation. STANO BY WITH HOLDING TORQUE IM= SOmA HALF STEP MOTOR DRIVE 1M = 250mA 3 ~ 5 6 FULL STEP MOTOR DRIVE 1M =500mA 7 PhA IN PhB ---f---, 500mA---- - - - - - - - - - - - - - - - I MA _ I J - - - - --- - - --,.- ---- IL.....-_______ _ ::::p ----- c::~:._.__-+-_-+r--_~----~,.----= -500mA------- _______________________ _ OUT ~~ -500 m A - - - - - - - - - - - - - - - - - - - - - - - L....- _ _ L....- S-67~9 7/10 709 PBL3717A APPLICATION INFORMATIONS Fig. 3 shows a typical application in which two PBL371 7A control a two phase bipolar stepper motor. Like full step this can be done at any current level ; the torque is not constant but it is lower when only one winding is energized. PROGRAMMING A coil is turned off by setting 10 and Ii both high. The logic inputs 10 and Ii set at three different levels the amplitude of the current flowing in the motor winding according to the truth table of page 2. A high level on the "PHASE" logic input sets the direction of that current from output A to output B ; a low level from output B to output A. It is recommended that unused inputs are tied to pin 6 (Vss) or pin 4 (GNO) as appropriate to avoid noise problem. The current levels can be varied continuously by changing the ref. voltage on pin 11. CONTROL OF THE MOTOR The stepper motor can rotate in either directions according to the sequence of the input signals. It is possible to obtain a full step, a half step and a quarter step operation. FULL STEP OPERATION Both the windings of the stepper motor are energized all the time with the same current IMA = 1MB. QUARTER STEP OPERATION It is preferable to realize the quarter step operation at full power otherwise the steps will be of very irregular size. The extra quarter steps are added to the half steps sequence by putting one coil on half current according to the sequence. AB A -72 A B -7 B -7 2 B -7 - AB -7 -B A2 -7 A etc. MOTOR SELECTION As the PBL3717 A provides constant current drive, with a switching operation, care must be taken to select stepper motors with low hysteresis losses to prevent motor over heal. L-C FILTER To reduce EMI and chopping losses in the motor a low pass L -C filter can be inserted across the outputs ofthe PBL3717A as shown on the following picture. 10 and Ii remain fixed at Whatever torque value is required. Calling A the condition with winding A energized in one direction and A in the other direction, the sequence for full step rotation is : AB -7 AB -7 AB -7 AB etc. L 15 OUT A 1 OUTB For the rotation in the other direction the sequence must be reserved. 5-7742 In the full step operation the torque is constant each step. HALF STEP OPERATION Power is applied alternately to one winding then both accordJ0g to' Q1e s~uen~e: _ AB -7 B -7 AB -7 A -7 AB -7 B -7 AB -7 A etc. 8/10 710 MOTOR WINDING (LM,R M ) c PBL3717A L=_1_ LM - 10 PBL3717A Figure 6 : Source sat. Voltage vs. Output Current (recirc. period). Figure 7 : Source sat. Voltage vs. Output Current (conduction period). G- 5790 G 57B9 Vsat "sat (V) (V) I---- - - - >-- I--"" I-- 0.2 0.4 0.6 o.a - :- 02 HAl Figure 8: Sink sat. Voltage vs. Output Current. 0.4 l - I--"" - 0.6 0.8 I (A) Figure 9 : Comparator threshold vs. Junction Temperature. G 5791 toO -02 f-- ~ - 0.6 0.8 \ 60 40 04 \ 60 I (AJ 20 20 40 60 80 100 120 140 160 MOUNTING INSTRUCTIONS The Rth j-amb of the PBL 3717A can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board or to an external heatsink. The diagram of fig. 11 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side "a" of two equal square copper areas having a thichkness of 35~ (see fig. 10). The extemal heatsink or printed circuit copper area must be connected to electrical ground. 9/10 711 PBL3717A Figure 10 : Example of P.C. Board Copper Area Which is Used as Heatsink. COPPER AREA 35,uTHICKNESS Figure 11 : Max. Dissipable Power and Junction to Ambient Thermal Resistance vs. size "a". ±- Ptot (W) ! ~ - -. - 1\ r--- .- I--- 1---- ~ t--- 1---- ! 10/10 712 0= r- t -I ___ ~f- _ , , 'T~~i20 P.C.BOARD ~-t- 80 ~l-amb 1--- r - '-.. 1---- ~~--( 30 -E 1- - \-140 I (mm) 60 40 20 SG1524 SG2524 SG3524 REGULATING PULSE WIDTH MODULATORS • COMPLETE PWM POWER CONTROL CIRCUITRY • UNCOMMITTED OUTPUTS FOR SINGLE-ENDED OR PUSH PULL APPLICATIONS • LOW STANDBY CURRENT .. 8 mA TYPICAL • OPERATION UP TO 300 KHz • 1 % MAXIMUM TEMPERATURE VARIATION OF REFERENCE VOLTAGE DESCRIPTION The SG1524 , SG2524, and SG3524 incorporate on a single monolithic chip all the function required for the construction of regulating power supplies inverters or switching regulators. They can also be used as the control element for high power-output applications. The SG1524 family was designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless voltage doublers and polarity converter applications employing fixed-frequency, pUlse-width modulation techniques. The dual altemating outputs allows either single-ended or push-pull applications. Each device includes an on-ship reference, error amplifier, programmable oscillator, pulse-steering flipflop, two uncommitted output transistors, a highgain comparator, and current-limiting and shutdown circuitry. 5016 J DlP-16 (Plastic -0.25- and Ceramic) ORDER CODES: SG1524J - SG2524J - SG3524J (Ceramic) SG2524N - SG3524N (Plastic) SG2524P - SG3524P (SO-16J) ~_ ________ i . _. _____.... __________ ....J, BLOCK DIAGRAM ':I@--. osc. "REF ---() 16 I ! OUT CT 7 Osc. - COMPENSATION 9 - (RAMP) , CB -- _~. .>V NOR- ---- 13 EB 11, SHUTDOWN GNO ----010 '~1 September 1988 1/7 713 SG1S24-SG2S24-SG3S24 ABSOLUTE MAXIMUM RATINGS Parameter Symbol V IN Ic Value Unit Supply Voltage 40 V Collector Ouptut Current 100 mA 50 mA IR Reference Output Current IT Current Through CT Terminal - 5 mA P'o' TS'g Total Power Dissipation at Tamb = 70°C 1000 mW Storage Temperature Range - 65 to 150 °C Top Operating Ambient Temperature Range SG1524 SG2524 SG3524 - 55 to 125 - 25 to 85 o to 70 °C °C °C CONNECTION DIAGRAMS ~ 16 + 5V VREF OSC.I SYNC. 14 EMITTER B C.L.I+)SENSE 13 COL LECTOR B C.L.I-) SENSE 12 COLLECTOR A 11 EMITTER A INV· INPUT 1 NON INV. INPUT 2 GROUND 10 SHUTDOWN 9 COMPENSATION 5-6393 " THERMAL DATA R'h j-amb R'h j-alumlnla * I Themal Resistance Junction-ambient Themal Resistance Junction-aluminia Max Max Plastic DIP-16 Ceramic DIP-16 80°C/W 150°C/W - - S016J 50°C/W Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20 mm; 0.65 2/7 714 mm thickness with infinite heatsink. SG1S24-SG2S24-SG3S24 ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for TJ = - 55 'C to+ 125 'C for the SG1524, - 25 'C to + 85 'C for the SG2524, and 0 'C to + 70 'C for the 8G3524, V N = 20 V, and f = 20 KHz). Symbol Parameter SG1524 SG2524 Test conditions SG3524 Unit J Min. I Typ. Max. Min.J Typ. I Max. REFERENCE SECTION VREF ",V REF "'VREF "'VREF/"'T "'VREF 4.8 Output Voltage Line Regulation V 1N = 8 to 40 V 5 5.2 10 20 50 4.6 5 5.4 V 10 30 mV 20 50 mV Load Regulation IL = 0 to 20 mA 20 Ripple Rejection f = 120 Hz, T J = 25 cC 66 66 dB Short Circuit Current Limit VREF = 0, T J = 25 cC 100 100 mA Temp. Stability Over Operating Temp. Range 0.3 Long Term Stability T J = 125°C, t = 1000 Hrs 20 20 0.3 mV 300 300 kHz 5 5 1 1 % OSCILLATOR SECTION fMAX MI",T MaximurT) Frequency CT = 0.001 /IF, RT = 2 kQ Initial Accuracy RT and CT Constant Voltage Stability VIN = 8 to 40 V, Ti = 25 cC Temperature Stability Over Operating Temp. Range % 1 1 % 2 2 % Output Amplitude Pin 3, T J = 25 cC 3.5 3.5 V Output Pulse Width CT = 0.01 /IF, T j = 25°C 0.5 0.. 5 /ls ERROR AMPLIFIER SECTION Vas Ib Input Offset Voltage VCM = 2.5 V 0.5 5 2 10 Input Bias Current VCM =2.5 V 2 10 2 10 mV /lA Gv Open Loop Volt. Gain CMV Common Mode Volt. Tj = 25°C CMR Comm. Mode Rejec. T J = 25°C 70 70 dB B Small Signal Bandwidth Av = 0 dB, T j = 25°C 3 3 MHz Va Output Voltage Tj = 25°C 72 80 1.8 60 3.4 0.5 80 1.8 3.8 0.5 45 0 dB 3.4 V 3.8 V 45 % COMPARATOR SECTION Duty-cycle % Each Output On VIT Input Threshold Zero Duty-cycle VIT Input Threshold Maximum Duty-cycle Ib Input Bias Current 0 1 1 V 3.5 3.5 V 1 1 /lA 3/7 715 SG1S24-SG2S24-SG3S24 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter SG1524 SG2524 Test conditions SG3524 Min. I Typ. I Max. Min. I Typ. I Max. Unit CURRENT LIMITING SECTION Sense Voltage Pin 9 = 2 V With Error Amplifier Set for Max. Out. Tj = 25 DC 190 Sense Voltage T.C. CMV 200 210 180 + 1 - 1 200 0.2 Common Mode Volt. 220 mV;oC 0.2 - 1 mV + 1 OUTPUT SECTION (each output) Collector-emitter Volt. Collector Leackage Cur. tr tf Iq • 40 VeE =40 V 40 0.1 50 1 2 Saturation Voltage Ie = 50 mA Emitter Out.' Voltage VIN = 20 V Rise Time Rc = 2 KQ, Ti = 25 DC 0.2 Fall Time Re = 2 KQ, Tj = 25 DC 0.1 Total Standby Curr. VIN = 40 V 17 V 17 18 0.1 50 ~A 1 2. V 18 V 0.2 ~s 0.1 8 10 ~s 8 10 ( .) Excluding oscillator charging current, error and current limit dividers, and with outputs open. Figure 1 : Open-loop Voltage Amplification of Error Amplifier vs. Frequency. Figure 2 : Oscillator Frequency vs. Timing Components. G " (dB 60 ) RF=Q) f (Hz) I bJ'M~ ~ 300lUL _ '""'\ " :\ I I RF is - impedance from pin 9 10K "- ~ to ground.Values below 3DKJl will begin to limit the maximum dU1y- cycle. I I 100 4/7 716 ,. ·, ··, ··, 10. 100101: 1K " f {Hz} 5 133/1 c T = 1nF JnF -- 30Kll. 20 r---- , - --j Vi =11. OV r-" 100K ......... 100Kil 40 , Vi = 20Y - ....... f'.. 10nF ....... " 30nF 100nF " t----= 1"-- 100 10 20 RT (Kn) mA SG1524-SG2524-SG3524 Figure 3 : Output Dead Time vs. Timing Capacitance Value. G Figure 4 : Output Saturation Voltage vs. Load Current. G- 511,0/1 5139 E ) r-- ) VIN ::20V r VIN=20V 3.5 ./ V 2.5 Ti=1~~:~ -55"c.. 0.4 '---- 0.' O.OQ1 1.5 Note:Dead time=blanking pulse width P'Uj 01'~Ui ~i',iY I III JllJ II lIU 0.00.4 0.01 0.04 CT ./ 0.5 F- .-::::. ~ ~ CpF) 20 ,/ -- 40 V ........ V ~ ::----.- '> E< .....-: v >"' 60 Figure 5 : Open Loop Test Circuit. INPUT 2K11 'W '5 OS VREF " 13 5G1524 OUT .6 lIT 6 NJ. CT 7 PRINCIPLES OF OPERATION The SG1524 is a fixed-frequency pulse-with-modulation voltage regulator control circuit. The regulator operates at a frequency that is programmed by one timing resistor (RT) and one timing capacitor (CT). RT established a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing linear control of the output pulse width by the error amplifier. The SG1524 contains, an on-board 5 V regulator that serves as a reference as well as powering the SG1524's internal control circuitry and is also useful in !>upplying external support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common- 'N~ SHUT INPUT INPUT COMP. DOWN 2 '0 • • CURRENT LIMIT OUTP " .4 4 mode range of the error amplifier or an external reference may be used. The power supply output is sensed by a second resistor divider network to generale a feedback signal to error amplifier. The amplifier output voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain c6mparator is then steered to the appropriate output pass transistors (OA or Os) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both output are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the value of CT. The outputs 5/7 717 SG1524-SG2524-SG3524 may be applied in a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current limiting and shut- down circuitry and can be overridden by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error arnplifier, or to provide additional control to the regulator. RECOMMENDED OPERATING CONDITIONS Supply voltage VIN Reference Output Current Current through CT Terminal 8 to 40 o to 20 - 0.03 to - 2 V mA mA Timing Resistor, RT Timing Capacitor, CT 1.8 to 100 0.001 to 0.1 KQ /IF TYPICAL APPLICATIONS DATA OSCILLATOR The oscillator controls the frequency of the SG1524 and is programmed by RT and CT according to the approximate formula: where cle by clarnping the output of the error amplifier. This can easily be done with the circuit below: Figure 6. RT is in KQ CT is in /IF f is in KHz Pratical values of CT fall between 0.001 and 0.1 /IF. Pratical values of RT fall between 1.8 and 100 KQ. This results in a frequency range typically from 120 Hz to 500 KHz. BLANKING The output pulse of the oscillator is used as a blanking pulse at the output. This pulse width is controlled by the value of CT. If small values of CT are required for frequency control, the oscillator output pulse width may still be increased by applying a shunt capacitance of up to 100 pF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maximum duty cy- 6/7 718 SYNCHRONOUS OPERATION When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator ouptut terminal. The impedance to ground at this point is approximately 2 KQ. In this configuration RT CT must be selected for aclock period slightly greater than that the external clock. If two more SG1524 regulators are to be operated synchronously, all oscillator output terminals should be tied together, all CTterminals connected to a single timing capacitor, and the tirning resistor connected to a single RT terminal. The other RT terminals can be left open or shorted to VREF. Minirnum lead lengths should be used between the CT terminals. SG 1524-SG2524-SG3524 Figure 7: Flyback Converter Circuit. r--I~-4~-- 300 JL 5 Kn 1 20mA M 15 +15V '----!OII--~- -15 V 11 16 ~C=}---------~6 -10 Figure 8: PUSH-PULL transformer-coupled circuit. + ,-------------------_._--------------, 2ev ~ ,...----"::--- 1K n 1W BYWS1 +5V. SA I 1 2 ~_---.J " f----+--' 5T 13 ~----[=--}-------l 6 SG1524 1 4 f - - - - - - , 5T 10nF 10 7/7 719 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I SG1525A/27A SG2525A-3525A/27 A REGULATING PULSE WIDTH MODULATORS ----~~-~---------~ • • • • • • • • 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS • LATCHING PWM TO PREVENT MULTIPLE PULSES • DUAL SOURCE/SINK OUTPUT DRIVERS shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages~ This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator~ Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG1525A output stage features NOR logic, giving a LOW output for an OFF state. The SG1527 A utilizes OR logic which results in a HIGH output level when OFF. DIP-16 (Plastic -0.25 and Ceramic) ~.>""""'.'" ~~ U DESCRIPTION The SG1525N1527 A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in softstart circuitry with only an external timing capacitor required. A shutdown terminal controls both the softstart circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed September 1988 S016J 1/10 721 S~ 1525A/27 A-SG2525A/27 A-SG3525A/27 A CONNECTION DIAGRAM AND ORDERING NUMBERS (top view) --;.J 16 VREF N.I.INPUT 15 +Vj SYNC 14 OUTPUT 8 13 Vo 1 INV. INPUT Type 4 OSC. OUTPUT Ceramic DIP Plastic DIP SG1525A SG1525AJ SG1527A SG1527AJ S016J Cr 12 GROUND SG2525A SG2525AN SG2525AJ SG2525AP Rr 11 OUTPUT A SG2527A SG2527AN SG2527AJ SG2527AP SG3525A SG3525AN SG3525AJ SG3525AP SG3527A SG3527AN SG3527AJ SG3527AP 10 DISCHARGE SOFT - START SHUTDOWN COMP. B 5- 6.1;11, ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vi Supply Voltage 40 V Vc Collector Supply Voltage 40 V 5 mA 500 mA 50 mA 5 - 0.3 to + 5.5 - 0.3 to Vi mA V V lose Parameter Oscillator Charging Current 10 Output Current, Source or Sink IR Reference Output Current IT Current through CT Terminal Logic Inputs Analog Inputs Ptot 1000 mW Tj Junction Temperature Range - 55 to 150 °C T s1g Storage Temperature Range - 65 to 150 °C Top Operating Ambient Temperature: SG 1525A/27 A SG2525A/27 A SG3525A/27 A - 55 to 125 - 25 to 85 o to 70 °C °C °C Total Power Dissipation at T amb = 70°C THERMAL DATA (DIP-16) Rth j-pins Rth j-amb I Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Max Max Ceramic Plastic 150°C/W 50°C/W 80°C/W 50 °C/W THERMAL DATA (S016J) Rth j-alumina* Thermal Resistance Junction-alumina Max Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20 mm ; 0.65 mm thickness with infinite heats ink. 2/10 722 SG 1S2SA/27 A-SG2S2SA/27 A-SG3S2SA/27 A BLOCK DIAGRAM -~~'f i 'i 'sD-(",ROUND 11 O~---------4- 'c 01) JL OUTPUT A. ---------- - - - - Rr , 0-------- >~;c ..:.1 . I 1. ~ COMe , 0-- I :~ :~:: ~ SOFr~STARr , rv--~!. r ~ ')GI5Z5A OUTPUT C,IAGf ~~ 1 'C - -0 I] 'REF OUTPUT A .oil I 1 ,---+------~----5HUTOOWN 5K fl :=T 10 MO Gain Bandwidth Product G v = 0 dB DC Transconduct. 30 KO <; RL <; 1 MO TI = 25°C Ti = 25°C 60 75 60 75 dB 1 2 1 2 MHz 1.1 1.5 1.1 1.5 ms 3.8 5.6 3.8 5.6 V Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V CMR Comm. Mode Reject. V CM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB 45 49 45 49 0.7 0.9 0.7 0.9 PWM COMPARATOR Minimum Duty-cycle 0 Maximum Duty-cycle Input Threshold Zero Duty-cycle Maximum Duty-cycle * 4/10 724 Input Bias Current 0 % % V 3.3 3.6 3.3 3.6 V 0.05 1 0.05 1 flA SG1525A/27 A-SG2525A/27 A-SG3525A/27 A ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions SG1525A/2525A SG1527 A/2527 A I SG3525A SG3527A I I Unit I Min. Typ. Max. Min. Typ. Max. SHUTDOWN SECTION " v, Soft Start Current Vso = 0 Soft Start Low Level Vso =2.5 V Shutdown Threshold To outputs, Vss = 5.1 V T j = 25°C Shutdown Input Current Vso=2.5V Shutdown Delay Vso =2.5 V OUTPUT DRIVERS (each output) Output Low Level 25 50 80 0.4 0.7 V 0.8 1 V 1 0.4 1 mA 0.2 0.5 0.2 0.5 /lS Isink = 20 mA 0.2 0.4 0.2 0.4 V ISink = 100 mA 1 2 1 2 V 01 c Vss = 0 V 0.6 T j = 25°C 50 80 0.4 0.7 0.8 1 0.4 25 0.6 /lA = 20 V) Isource = 20 mA 18 19 18 19 V Isource = 100 mA 17 18 17 18 V Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V Output High Level Ie Collector Leakage Vc = 35 V 200 !lA t( Rise Time C L = 1 nF, T J =25 °C 100 600 200 100 600 ns tf" Fall Time C L = 1 nF, T j =25 °C 50 300 50 300 ns 14 20 14 20 mA TOTAL STANDBY CURRENT. I Supply Current Vi = 35 V I : These parameters. although guaranteed over the recommended operating condijions. are not 100 % tested in production. Tested at f", = 40 KHz (RT = 3.6 KQ, CT = 0.1 ~F. RD = 0 Q). Approximate oscillator frequency is defined by : f= 1 CT(O.7 RT+ 3 RD) • DC transconductance (gM) relates to DC open-loop voltage gain (G,) according to the following equation: G, = gM RL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum G, when the error amplifier output is loaded. 5/10 725 ..... ~ I\J -I m o O'l en -I VREF Q r--------------- -----, I :rI I REFERENCE REGULATOR (') .} , ::c c @)+V, :::::j O.1pF ... U1 I\) U1 » N » "" In G') I\) U1 I\) U1 » -- I\) . » "" , lW ~ , ~ ['~ !!lin ~~ @. lW I\) 14 • » OUT B I !o I il!J!I !;!lin .c+-~GNO ~i SOFT START I:Vos 2.(.) 3.(-) CiJ U1 I • ~;! en G') I -----I 5-6415'1 U1 -- I\) » "" SG1525A/27 A-SG2525A/27 A-SG3525A/27 A RECOMMENDED OPERATING CONDITIONS (0) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (Vc) 4.5 to 35 V Sink/Source Load Current (steady state) o to 100 mA o to 400 mA o to 20 mA Sink/Source Load Current (peak) Reference Load Current Oscillator Frequency Range 100 Hz to 400 KHz 2 KQ to 150 KQ Oscillator Timing Resistor Oscillator Timing Capacitor ~F 0.001 Dead Time Resistor Range to 0.1 ~F o to 500 Q .. (.) Range over which the device IS functional and parameter limits are guaranteed. Figure 1 : Oscillator Charge Time vs. Rr and Cr. Figure 2 : Oscillator Discharge Time vs. RD and Cr. RO (11.) 150/1 050 736 1 - ==i V mA 10 i 12 mA I _ I 1 I [100 x a V . ... ---~-r--~~- - ~ 35 f- - - 1 10 - r- r-XH;- =t=:::=:::= f-~ 10kHz _--=---+ -~_ 20 -f-'~- ~~.~_I.t.~ __ -_ Hysteresis at Detection Point C2 (PI) > 150/1 050 (MHz)~. _ _ _~5.j ___ ._~_ ~ ___ ~~_._ %_~~_.c * If the circuit is used at a frequency higher than 3 MHz, 2/4 I (MHz~ Negative Resistance on Terminals A and E (4 kQ < Rl < 50kn, 1050< 3 MI:l~ __________. HY5t I _ ·-----··----~~I <2.3~F)l Output Frequency (C3 = 0) Output Current Ripple 4 __ ---+_~ Reverse Voltage limitation (Icc = 100 mAl - it is recommended to connect a capacitor of 100 pF between terminals E and D. TDA0161 OPERATING MODE Between terminals A and E, the integrated circuit acts like a negative resistance equal to the external resistor R1 connected between terminals Band H. The oscillation sustains when loss resistance Rp of tuned circuit becomes higher than R1. Then, the supply current will be Icc 1 mA (pins G and D). The oscillation stops when loss resistance Rp of tuned circuit becomes smallerthan R1. Then, the supply current will be Icc = 10 mA (pins G and D). Eddy currents induced by coil L 1 in a metallic body, determine loss resistance Rp. R1 o I I I I I '------0 : Close metallic object I I ~ Remote metallic object ------------_._-_. ---------- TYPICAL APPLICATIONS , - - - - - - - - - - - - - - - - - - -----1 1 1 : 1 ;---- - - - - - - - - - - - ------ 1 I r-----~----+------~~---__o+ I I 1 TDA 0161 L1 E C 0 1 1 C2 1 1_ _ _ _ - I1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _I Detector 120 n 1 I I 1_ _ _ _ - _____ . Receiving circuli 3/4 737 TDA0161 ,------------.-------,---------.----------,---------_. L1 C1 R1 f ose Detection Range (*) (flH) 2 mm 30 ---------~ C2 pF (pF) (kHz) (kQ) 120 2650 6.8 47 27 470 27 3300 (1) COIL CHARACTERISTICS i Core 1 I Coil Former Cofelec 432 FP 9 x 5 SE 1/2 CAR 091 - 2 Cofelec 432 FP 14 x 8 SE 1/2 CAR 142 -- 2 Cofelec 432 FP 26 x 16 SE 1/2 CAR 262 -- 2 i I 2 I 3 THOMSON Fils et Cables Thomrex 14 (14/100 mm) THOMSON Fils et Cables Thomrex 14 (14/100 mm) i ._~____. _ L . . -__ .~_ _ _ _ _ l ** Wire" I THOMSON Fils et Cables Thomrex 14 (14/100 mm) ... I I Number of Turns 40 I I 100 I 200 ~---~--~-~-- The above results are obtained with single wire coil. When using Litz wire instead of single wire, the parallel resistance of the coil be- comes higher and the value of Rl may be increased, resulting in better sensitivity. 4/4 738 TDE0160 PROXIMITY DETECTOR ---------------------------------------i-------- • SUPPLY VOLTAGE: + 4 TO + 36 V • SUPPLY CURRENT: < 1.2 mA • OUTPUT TRANSISTORS: I = 20 mA ; VeE (sat) s; 1100 mV • OSCILLATOR FREQUENCY: < 1 MHz • LOSS RESISTANCE: 5 TO 50 kQ. DIP-14/2 (Plastic) SO-14J ~.p< •. .•. . . ~ .. ~- DESCRIPTION . ......... The TDE0160 is designed to detect metal bodies by the effect of Eddy currents on the HF losses of a coil. It has two complementary open collector outputs with peak limiting. Hysteresis is adjustable, and an electronic switching circuit is incorporated for disabling both outputs. An internal zener diode maintains the supply voltage to the circuit in "dipole" operation. ""i ........ ORDER CODES: TOE0160DP (DIP-14) TOE 0160FP (SO-14J) PIN CONNECTION DlP-14 I SO-14J Output 1 (collectorl Outputs 1 and 2 (emitter) Output 2 (collector) Hysteresis adjustment Detector filter capacitor Sensing range adjustment Oscillator circuit September 1988 Ground Switching period capacitor Switch input VCC Decoupling Zener output N.C. 1/6 739 TDE0160 ABSOLUTE MAXIMUM RATINGS Value Unit Vee Supply Voltage Parameter 36 V Va· Output Voltage' 36 V 40 rnA Symbol 10 (1 1-1 3) Output Current (11-13) Iz Zener Current Tj Junction Temperature 40 rnA + 150 °C Toper Ambient Temperature Range - 25 to + 85 °C Tst9 Storage Temperature Range - 65 to + 150 °C • Internal peak limiting to protect against transient voltage surges. SCHEMATIC DIAGRAM I, --' 2/6 740 -------~ TDE0160 ELECTRICAL CHARACTERISTICS (T amb = + 25 'C unless otherwise specified) Symbol Vcc Min. Typ. Max. Unit Pin 11 4 36 V Pins 9-11 3 - 4 V Pin 11 - - 1.2 mA Parameter Supply Voltage Vz Zener Voltage (Iz Icc Supply Current = 0.1 = 20 mAl - Limiting (I mAl Pin 1 or 3 - 42 - V - Output Transistor Saturation Voltage (1, or 13 = + 20 mAl Pin 1 or 3 - 0.9 1.1 V - Output Transistor Leakage Current (V - Switching Threshold =+ 30 V) Pin 12 Negative Resistance' (5 kQ < RH < 50 kQ; f Rs = 0) Rn - Inherent Hysteresis (R2 - Pin 1 or 3 = 100 kHz; - - 2 j.lA 90 110 130 mV = RH - - 1 2 % - % - = 0) - Programmed Hysteresis (H < 15 %) Rn Rs --- Rs + RH Oscillation Frequency - - 1 MHz - Switching Frequency (with matched oscillator circuit) - 750 - Hz - Switching Time-delay - 0.5 Cd (/IF) - s - Switching Response Time (Cd - 10 - /lS fose = 10 n F ; V cc =+ 20 V) • See characteristic curves SWITCHING OPERATION Vce -----1 lor3 I I2 'e :I If Ic exceeds Ico, where leo = V(ref) . ~' the sWitch cuts off the output transistors and tests the value of current Ie, with time constant 0.5 Cd. On power up the internal start system cuts off the output transistors until Vee reaches a value permitting normal operation of the circuit. 3/6 741 TDE0160 NEGATIVE RESISTANCE vs FREQUENCY ZENER VOLTAGE vs JUNCTION TEMPERATURE ~ 5 w ~ ~ CJ U Z ~ w II: w > w Z ~ i W N CJ I Vec = +20V w Zener current "::;: 20 rnA Z o 10 40 100 400 '---~--'-----'---~ 40 1000 175 150 0 :J: III w 125 II: :J: I- CJ Z Vee~+20J ~ 100 t-- ~ 11 f = 100 kHz ~ 10.5 _ RH= 10 kll RS=O lfi - l: U I- ~ w U > r- ~ w z - 0 50 10 w CJ -40 100 150 200 9 - 40 JUNCTION TEMPERATURE ,oCI 4/6 742 200 II: 75 50 150 Vec=+20V Ii; I'--.. .............. 100 NEGATIVE RESISTANCE vs JUNCTION TEMPERATURE SWITCHING THRESHOLD vs JUNCTION TEMPERATURE .§ a ..J 50 JUNCTION TEMPERATURE ,oCI FREQUENCY IkHzl :> 0 r.== SGS.ntOMSON At.., I IiilOCII©mIl.IIC1illl@Il!DCII! 0 50 100 150 200 JUNCTION TEMPERATURE ,oCI TDE0160 TYPICAL APPLICATION DIAGRAMS I I l . 1 I 14 I I I' I I RS [ I I I L ~ -- ~ --- - ~ b) a) +vcc 1 RH~F ov 14 2 13 3 12 Cd 0 4 <0 11 5 ;; 10 w 0 I- CA 6 RS Ca Cf Cd Co La Rd RH . Rs: RL : 10 nF 1 nF 10 nF 390 ~F 65 ~ to 1 MHz 10 Q 15 kQ 3kQ 2.2 kQ Vee :20 V fa ~ 1MHz emean = 2.5mm coil :14 mm Core COFELEC 432 FP Turns: 47 Stranded wire: 15 x 5/100 1/ La c) J 5/6 743 TDE0160 MILD STEEL lOSS RESISTANCE vs DETECTION RANGE (mml 35 c: Hp r--=---, I I 'Ss O 2! w I I t:J 30 25 J U 0 z =+ :;?5°C 0.2 i o i 0.6 r-- T case = ... 'OO°C o 234 6 r--- 0.7 .... ~ 0.6 S o :J u .... ".... I--- '" :) .. 0.5 0.4 ~;: 0.6 .... II: 0,4 0.3 ~ffi ,?a: 0.2 :t -1- 4 5 = a::J I I I I I I I I I r--/. T \\ 0.1 0 .. 0.2 ...'"'" o Q. 4 5 6 case ./ TC8$e ~ / '\"< ~ ""-C 2 r-- j..---- =+ 1~Cf'~_ r- t...;; N o =-25"C T case = + 250C ./ I\.\ 00 3 - 3 \1 0.8 t:;t 2 1------ -- - 2 .\ Q. f} t-..:: t- l"- --f- -, o " Q. "0 "'... ~ / TDE1647,A • TDE1607 eM ~ II: ~ LIMITING RESISTOR 101 TDE1647,A - TDE1607 eM .. ca~ I--- k' I-L P"' Tcas,e =+ l000~_ I lIMIT!NG R£SISTOR IIlI .... Tc---I--I ...a: ::> u .... ".... "...o .... Q. Tca:oe =-+ 25°C 0.4 I----+-+---,f--':::::r-------j il Tease =+ 1000C . 0.3 f--t----k-~-+t--_-lif---.."'::;j;::"_-C---1 0.2 I----+--i-".... .-------1 .. 0.1 - :) ~ """,+I-t------.--, o -~.-,~ .....;;;:;::===----t---l 2 3 : I i I 4 5 6 7 LIMITING RESISTOR 1m .... ".... Q. :J 0 I 0.9 0.8 0.7 I II:Z -OJ '?II: .... 0: 0.5 Ou 0.3 Ul 0.2 0.1 cc" :t '.." ~ 0.4 0 I I I / T case = -25°C I !:4 ::>- 0.6 0 .... I I I I I j I I / T cas.e--t25°C ~I ~ ;-. I I 2 - I T case == ... 10c0C :::2!; :-X. I I 3 JlI l"J I I 4 6 LIMITING RESISTOR 1m 5/10 749 TDE1647/A, TDE1747, TDE1607, TDF1607, TDF1647/A Short-circuit current versus case temperature Mimimum limiting resistor value versus supply voltage TDE1747 TDEl647.A - TDE1747 ~ w "!:;0.. .. "- 20 ::> -25 0 25 75 125 175 CASE TEMPERATURE 1°C) LIMITING RESISTOR l!ll TDE1647.A - TDE16D7 CM TDF16D7 - TDE1607 DP 40· h:O;;;~:;';-:::::;:::::J;::::;;::::::::~~:;:::J 35~~~~~~~~~~~ ~ ~ ~~~~~-----+------~----~ I- ~ 25 ~~~~------~-----}------4 '" B 20 !::: ::> u ~ "~ 15 Z w ~ 0:: ~ O. 5 >----L-+--'~~!:: > ~ -25'C u !::: ::> u 0.4 ... " 0 0.. 0.. 13 '"0 :J: to ::> 0.2 I/) 0 -25 0 25 75 125 CASE TEMPERATURE ,oCI 6/10 750 ~25°C- -' 0: ,: ~ 25 175 0.8 1.5 LIMITING RESISTOR 101 2 TDE1647/A, TDE1747, TDE1607, TDF1607, TDF1647/A TDE1647,A· TDE1747· TDE1607 eM TDE1647,A • TDE1747 ~ Tj; + 25°C ... C) :! E o > z ...a::z o a:: ~ a:: ~ ~ >- ..J :::l -.--~. 0.1 --.-----;---------c-----j -1- ----.--~--I 200 300 o 10 "!3o > z o i= « IX ::> ~ II> ...:::l ...::> II. o 0.8 TDF1607 DP • TDE1607 DP -~.-----i---_'~_" - I-+~ 0.2 4 ...z 3 E a: a:: :::l U Tj~00C ____ - o L......-'-_ _ o 50 Tj~ ""':~ Tj ~ II. ::> '" ..--4Tj~+150°C-- .... ~--'-~_ 100 ... _ 2 ....0.>- +25°C + 100°C _-_ -~.----- _"_~_ _ _..J 150 200 0 250 . !-rr -i-f+I 10 I i ! I -- '- I _ 1+_;_ ~~+-+-t o I I High level-f--- ,...- -t OUTPUT CURRENT ImAI low level i I : : I 30 20 ! I ! I I I I -f-- I 40 SUPPLY VOLTAGE IVI Supply current versus junction temperature TDE1647,A· TDE1747 - TDE1607 t-~+ Tj:I+ 25I° C 0.2 TOE1647.A 0 ·,TIET' 0 o JUNCTION TEMPERATURE lOCI 20 40 60 80 SUPPLY VOLTAGE IVI 7/10 751 TDE1647/A, TDE1747, TDE1607, TDF1607, TDF1647/A Response Time. ~ ~ w "~ 0 > ... 5 ::> 0 ...~ "!:; C( .. 0 > ( 20 .. 0 7' I 10 0 10 5 i f I o 0.4 > 1 20 ::> ~ !/ ::> 0 10 ~ j 1 ! I 0 10 oJ 5 0 > 0 w ". 1 1 i C( i i i 0 ~ ""'~ ..... I I i 0.6 1.2 ::> ! 1.6 TIME '"" Test Circuit. ,..-----..---0 VCC=24 V 10 kn V sense Vo lkn 8/10 752 ASC 0 4 8 12 16 TDE1647/A, TDE1747, TDE1607, TDF1607, TDF1647/A TYPICAL APPLICATIONS TDE1647, A - TDE1747. Basic Circuit. Output Current Extension (5 A). Vee 5n vee vsense VI l t Vee 1.5 n Vo 414) 2,,Vsense VI 0.1 n j'4.7 nF I "01 Vo GNO 4.7 nF RL .~ • Dl : required if inductive load. DRIVING LOW IMPEDANCE RELAYS (10 = 300 mAl ,..-----------_. __. __.._.... ---I 7161 •. 7 nF The device in the above application operates at : Vee = + 45 V, 10 = 300 mA with a heatsink such that Rth(j-a)S 80 "C/W. The device supports an output voltage of Vee = Vz during the current cut off time, which is decreased by the zener diode. This voltage must be ~ to the maximum supply voltage. L..-_ _ _ _ _ _ _ _ _ _ _ _ _ ...•.. _ _ _ _ _ _ •.•.• _. _ _ _ .. _ _ _ . _.....•.... _ 9/10 753 TDE1647/A, TDE1747, TDE1607, TDF1607, TDF1647/A WAVEFORMS v I I I I (FIGURE 1a) \ \ / \\ \ \ (\/ V+ o / :· .. ···· .. ·....·.. ·· ...... ···I· ..\.. ;~ I I : '~~7> ~...... RESPONSE TIME WITH THE ZENER DIODE .. t 35 ms v (-----------:=\ Vee-Vlsat) I \ \\ / I / \ I V+ /-V I 754 I \\ \ . .;""- !+++ ........ ++ ..... +.++ +++ ... ++ •• + • • • + .+.++++\.+++++++ I ; RESPONSE TIME WITHOUT THE ZENER DIODE 10/10 \ I '---......: Note: (FIGURE 1 b) '-_/:;,. 65 ms 1. In the case of the figure 1a, the TDE1647, A-eM can withstand + 60 V @ 400 mA for t ~ 5 ,us. ..... .. I TDE1737 TDF1737 INTERFACE CIRCUIT - RELAY AND LAMP-DRIVER -------"--"----"--""" " " - - - " - - - - - - - - " - - - - - - " • HIGH OUTPUT CURRENT • ADJUSTABLE SHORT-CIRCUIT PROTECTION • THERMAL PROTECTION WITH HYSTERESIS TO AVOID THE INTERMEDIATE OUTPUT LEVELS • LARGE SUPPLY VOLTAGE RANGE: + 8 V to + 45 V - - - - - The output is also protected against short-circuits with the positive power supply. The device operates over a wide range of supply voltages from standard ± 15 V operational amplifier supplies down to the single + 12 V or + 24 used for industrial electronic systems. 1 ~ . -.·• · ·. ~>e DESCRIPTION The TDE1737-TDF1737 is a monolithic amplifier designed for high current and high voltage applications, specifically to drive lamps, relays and control of stepper motors. ~ ~ I METAL CAN eM SUFFIX This device is essentially blow-out proof. Current limiting is available to limit the peak output current to a safe value, the adjustment only requires one external resistor. In addition, thermal shut down is provided to keep the I.C. from overheating. If internal dissipation becomes too great, the driver will shut down to prevent excessive heating. ORDER CODES Part Number TDE1737 TDF1737 Temperature Range - 25°C to + 85 °C 1- 40°C to + 85 °C Package . .. .. CM DP FP Example: TDE1737DP PIN CONNECTION (top views) 50-14 METAL CAN 0- MINIDIP Vee 8 Non-inverting lnPUl 2 6 Current limit 3 Inverting Input September 1988 .. GND J NC. N.C. [ 2 13 ~ N.c. N.C. [ 3 12 ~ NC. N.C. ~ 1 Output [ .. Vee ~ 5 N.C. [ 6 NON-inverting input [ 7 \,.../ 14 ~ Current limit "j 10 J 8 J 9 GNO N.C. "0" Non-inverting input Invtltting input 3 2 7 6 Output Vee GND 4 5 Current limit inven.ing input 1/4 755 TDE1737 - TDF1737 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vs Supply Voltage 50 V VI Input Voltage 50 V VIO Differential Input Voltage 50 V 10 Output Current 1000 mA Ptot Parameter Power Dissipation Toper Operating Free-air Temperature Range TDE1737 Toper Operating Free-air Temperature Range TDF1737 Tstg Internally Limited W - 25 to + 85 °C - 40 to + 85 °C - 65 to + 150 °C Value Unit METAL CAN MINIDIP 45 50 °C/W METAL CAN MINIDIP 185 120 °C/W S014 90 °C/W Junction-ceramic Substrate (case glued to substrate, substrate temperature maintened constant) S014 65 °C/W Storage Temperature Range THERMAL CHARACTERISTICS Symbol Rth(j~c) Rth(j~a) Parameter Maximum Junction-case Thermal Resistance Maximum Junction-ambient Thermal Resistance Junction-ceramic Substrate (case glued to substrate) ELECTRICAL CHARACTERISTICS TDE1737 -25 'C :":Tamb:":+ 85 ce, + 8 V:": Vee :":+ 45 V, 10 :":300 mA, T j :":+ 150 'C (unless otherwise specified) TDF1737 - 40 'C:": T amb :": + 85 ce, + 8 V:": Vee:": + 45 V, 10:": 300 mA, T j :": 150 'C Symbol Min. Typ. Max. Unit Via Input Offset Voltage - (note 1) - 2 50 mV liB Input Bias Current - 0.1 1.5 Icc Supply Current (Vee - 3 5 ~ mA VeM Common-mode Input Voltage Range Vee-2 Isc Short-circuit Current Limit (Rse Vee-Va 10L Parameter = + 24 V, 10 = 0) = 1.5 fl, Tease = + 25°C) Output Saturation Voltage (output low) (VI + - VI - 250 mV 10 = 300 mA, Rse = 0) Output Leakage Current (output high) (Va = Vee = + 24 V, T amb = + 25°C) 2 - - 500 - 1 1.5 V - - 10 Il A V mA Notes: 1. The offset voltage given is the maximum value of input voltage required to drive the output voltage within 2 V of the ground or the supply Voltage. 2. Devices bonded on a 40 cm' glass~epoxy printed circuit 0.15 cm thick with 4 cm' of cooper. 2/4 756 TDE1737 - TDF1737 SCHEMATIC DIAGRAM Vee R3 3kn .......-t---+-( Q21 limit GND 1 SIMPLIFIED SCHEMATIC InpulS >-_-+__+-_--t,--""""'OUtpUl "sc TYPICAL APPLICATION - r-------.-------~flvcc 1.2 n 3/4 757 TDE1737 - TDF1737 Available output current versus limiting resistors Peak short-circuit current versus limiting resistor < ! 1 +25"C I I + 75"C I + loO°C ~ ::!wo II: :> () ~400 l- Tease !z \ ::!ooo II: ,,~ :> () t: ~ i3700 II: :> ... ;;:300 ~ ~ '"lo: 0 ~200 0 2 ~300 3 LIMITING RESISTOR 1m I I I I ISC peak - -25°C 111 II I r J Tease = +25°~ \K .:-, LS :s:I: 500 C ~ Tcase , Tease = + 100°C ~t--I Tease "" + 125° C r":S:: ~ m 1 1.5 I~ ~ 0.5 LIMITING RESISTOR Short-circuit current versus case temperature • = .. 75C>'C 2 1m Safe operating area (non repetitive overload) 5 !zw 1 50.8 a: a: ~ tP7 a: a: t: a \. '-.. .. 06 \ i3 04 a: 0.5 - 25° C< T case< .. 125 C 0 ~5 0 .2 ~ ~ 0.3 :I: '" I ! i 0.1 -25 25 75 125 o 175 CASE TEMPERATURE lOCI 20 Satu·ration voltage versus output current +25°C o 100 200 300 400 OUTPUT CURRENT (mAl 4/4 758 40 60 80 COllECTOR·EMITTER VOLTAGE IVI TDE1767,A TDE1787,A INTERFACE CIRCUIT (RELAY AND LAMP-DRIVER) • • • • • • • • OPEN GROUND PROTECTION HIGH OUTPUT CURRENT ADJUSTABLE SHORT-CIRCUIT PROTECTION INTERNAL THERMAL PROTECTION WITH EXTERNAL RESET LARGE SUPPLY VOLTAGE RANGE ALARM OUTPUT INPUT VOLTAGE CAN BE HIGHER THAN Vee OUTPUT VOLTAGE CAN BE LOWER THAN GROUND (Vee - Va:S: Vee [max]) I DESCRIPTION The TDE1767,A/TDE1787,A are monolithic amplifiers designed for high current and high voltage applications, specifically to drive lamps, relays, stepping motors. These devices are essentially blow-out proof. The output is protected from short-circuits with the positive supply or ground. In addition thermal shut down is provided to keep the IC from overheating. If internal dissipation becomes too high, the driver will shut down to prevent excessive heating.' The output stays null after the overheating is off, if the reset input is low. If high the output will alternatively switchon and off until the overload is removed. The device operates over a wide range of supply voltages from standard 15 V operational amplifier supplies to the single + 6 V or + 48 V used for industrial electronic systems. Input voltages can be higher than the Vee. -: MINIDIP/2 ORDER CODES: TDE1767 DP TDE1767 ADP TDE1787DP ~_ _ _ _ _ _ _ _ _ _T_D_E_17_8_7_A_D_P_ _ _~ PIN CONNECTION (top view) ,----------------- Alarm output Inverting input Non-inverting input GND 08 - - - - - Current limit 2 7 V CC 3 6 Output 4 5 Reset An alarm output suitable for driving a LED is provided. This LED, normally on (if referred to ground), will die out orflash during an overload depending on the state of the reset input. The output is low in open ground conditions. THERMAL DATA RthIJ-c) Rthij-a) ! Maximum Junction-case Thermal Resistance I, --- -~-------T~C/W Maximum Junction-ambient Thermal ~_es_is_tan_ce_'_ _ _ _ _ _ ~ ____ B_O__ Devices bonded on a 40 cm2 glass-epoxy printed circuit 0.15 cm thick with 4 cm2 of copper. September 1988 ,I - _ 'C/W : 1/8 759 TDE1767,A-TDE1787,A ABSOLUTE MAXIMUM RATINGS TDE1767A/TDE1787A TDE1767/TDE1787 Unit Vee Supply Voltage 60 50 V VIO Input Differential Voltage 60 50 V VI Input Voltage - 10 to + 60 - 10 to + 50 V 10 Output Current 1.2 1.2 A - 0.5 to + 60 - 0.5 to + 50 V Symbol VI(reset) Parameter Reset Input Voltage lOA Alarm Output Current ----_._._. Ptot Power Dissipation Toper T stg __ . _ - - -f------=-'-o...!O + 20_ _ L---=-.10 to + 20 ~ Internally Limited - 25 to + 85 - 25 to + 85 °C Storage Temperature Range - 65 to + 150 - 65 to + 150 °C SCHEMATIC DIAGRAM __ ._. EQUIVALENT SCHEMATIC Vee Current limit Alarm output 1 f-----f----' 0 '------16 - - - - , Reset 5 } - - - 4 - - - 1 '--_ _ _ 760 -- Operating Ambient Temperature Range , - - - - - - - - _ . - .. 2/8 mA mW --4~-----_ _ _ _-f4IGroun~- __ .J RL TDE1767,A-TDE1787,A ---I Figure 1. I --o-----1E TDE1767 TDEl787 Vref ;;;':1 V I 0''------''----_ _ _ _ ' - - - [ ,____ ,_~_, __J The reference input can be the inverting or non-inverting one. ELECTRICAL TDE1767 A : TDE1767: TDE1787 A : TDE1787 A : - CHARACTERISTICS (Unless otherwise specified) 25 DC ::; T amb ::; + 85 DC, + 6 V ::; Vee::; + 60 V, 10 ::; 25°C::; Tamb::; + 85°C, + 6 V ::; Vee::; + 45 V, 10::; 25°C::; T amb ::; + 85 DC, + 6 V ::; Vee::; + 60 V, 10::; 25°C::; T amb ::; + 85 DC, + 6 V ::; Vee::; + 45 V, 10 ::; 500 500 300 300 mA, mA, mA, mA, T j ::; T i::; T j ::; T j ::; Symb~arameter Icc Input Offset Voltage --0~te 1) Power Supply Current (measured-~;;;-4)-----~-----Output High (T amb = + 25°C) I Output High (Vee = Vee (ma,), T J = + 150°C) , Output Low (Vee = Vee (ma,), Tamb = + 25 GC) Min Typ Max - 2 50 - 5,8 5 1.5 8 7 4 I Input Bias Current ,--~-.----------------- Common-mode Input Voltage Range (note 2) I Input Voltage Range (V,eJ 2: + 1 V) (figure 1, note 2) IV' Vsense VO(sat) ---_.. - 15 ----"'" TDE1787A, TDE1767A TDE1787, TDE1767 1 1 TDE1787A, TDE1767A TDE1787, TDE1767 0 0 TDE1767A TDE1787A - - -- Current Limit Sense Voltage: Va = Vee - 2 V, t = 10 ms :Vo =OV,t=10ms (Vo=Vee- 2V) Output Saturation Voltage (output high Vi - lIT 2: 50 mV, Rse =0, Vee =+ 30 V) TDE1787 A, TDE1767 A T J = + 25°C TDE1787, TDE1767 TDE1787A, TDE1767A T J =+150°C TDE1787, TDE1767 -,- IA Available Alarm Output Current Output Source Current (V AH = Vee - 2,5 V) Output Sink Current (in thermal shut-down) VA = 1.4 V - 60 45 700 380 - 140 130 150 140 175 165 - 1 1 1,1 1,1 - I I Reset Input Current Reset Threshold - Output Leakage --i--- V - - - - - - - - - - - - _.._ - -4 5 - --, -- (open ground) I mV I I, 1,1 1.2 1.2 1,3 100 ,-- ~A mA Curre~t ~A V ------,--------,--,---~-- Ireset 100 c----60 45 - Output Leakage Current (output low) Vth (reset) -- mA IOL I mV V Short-circuit Output Current (Vee = + 35 V, t = 10ms) Rse=O,18Q Rse = 0,33 Q Ise ._-- Unit ,- mA -,---- -,-- I'B V eM 150°C 150°C 150 DC 150°C ----- ,----- ,-------- ,------- r---y;;;- + + + + - -5 10 , --i---2 40 1.4 - 10 - I-- ~A ~- V- , - J-lA Noles: 1. The offset voltage given is the maximum value of differential input voltage required to drive the output voltage within 2 V of the ground or the supply voltage, 2, Input voltage range is independent of the supply voltage, 3/8 761 TDE1767 ,A- TDE1787 ,A Fig. 2 - ~ z w PEAK SHORT-CIRCUIT CURRENT vs LIMITING RESISTOR. 1.00 t- .90 a: a: .80 :> .70 t- .80 -t---'t----+ VCC~ +30 V TdJnb- +25°C a: (3 ,.:. a: 0 :z: 0. t::> .50 .70 o .40 ~ .30 « > .10 « 0.00 0.00 .10 .20 .30 .40 .50 .80 . .10 0.00 .10 t- Z Fig 5 - ?" 1.50 ~ 1.30 4 () ~ 0. 0. ~ 1.20 1.10 ~ 1.00 ~ .90 :;: 2 .30 .40 t::> ~ rn OUTPUT SATURATION VOLTAGE vs OUTPUT CURRENT. .80 .70 .60 :> o a 10 30 50 60 o .50 SUPPLY V;)LTAGE IV) Fig. 6 - Fig 7 - § ~ .80 OUTPUT CURRENT IAI OUTPUT TRANSISTOR SAFE OPERATING AREA (pulsed). a: NORMAL OPERATING AREA (5tlort-circuit protected). 0.1 0 t- t- Z W () 0.2 0.3 C> t::> ...~ 0. ~ ::; t- :> o 0.4 0.5 40 SUPPLY VOLTAGE (VI 762 .70 .60 4/8 .50 1.40 z o w a: a: ::> .20 LIMITING RESISTOR 1m POWER SUPPLY CURRENT (pin 4) 6 +25°C 0.00 .70 .80 o «E Tamb~ +30 V .20 LIMITING RESISTOR 1m Fig 4 - ~- VCC~ .W .40 '"«-' VS I .- .60 .30 .20. AVAILABLE OUTPUT CURRENT UMITING RESISTOR. 1.00 tZ ::> () 5() Fig. 3 - 50 SUPPLY VOLTAGE (VI 60 TDE1767,A-TDE1787,A ALARM OUTPUT CAPABILITY CURRENT Fig B Fig. 9 - CURRENT SINKING. CURRENT SOURCING T iJrnb = f- 2S°C 26 ~ E 24 ~ 12f--4~-+~+-~+----+~-+~-+---( 20 ;2 tw t- ~ 16 '" 12 ;!; B u >< en J U w --1 _ 4 {) H g:: I%: ;;) A:arm output - U It: ::J after thermal _ en o D,h~tdQ",-:n {) 2 4 2 ALARM OUTPUT VOLTAGE REFERENCED TOSUPPLY VOLTAGE (V) ALARM OUTPUT VOLTAGE REFEREI.CED TO GROUND (V) Fig. 10 - RESPONSE TIME. ? w CJ - <{ !:; - - I---- f- 0 - > t- I---- - - ;;) "- t- ;;) 0 {) it---L w J <{ 0 {) > t- ;;) "- ~ w "!:; <{ ~ - 0 > I-- 0- - J "t- J 0 --- - I ? "!:; Fig 11 - RESPONSE nME. ~ {) TIME ? w CJ \) 2.5 V <{ !:; 1-- - 0 U > t- ::J 3 "- 4 10 {) ~ (~s) 20 TIME 1,,5) Figure 12 : Test Circuit. Vcc~+ 30 V 0.22 " TDE1767 TDE1787 1.4 V o--~~~~--i JOO!! 5/8 763 TOE 1767 ,A-TOE1787 ,A TYPICAL APPLICATIONS Figure 13 : Open Load Detection. RS ~eCO----9~==J-~----~------~1 ILl Vee "1 ;;. 50 mV R2 Rs IL ;> 100 mV Figure 14 : Driving Lamps, Relays, Etc ... RSC -vee ·Current limiting r---- ~, Output TDEI7117 + Input Reset V I Alarm output t Ground 5.6 kII l00kll Cmax) ~ i- Figure 15: Common Reset. rr------- -------------------~~__oVcc "sc RSC TDE1m TDE1787 TDE1767 OutPUt TDE1187 + Ground R.... AlilrmL.....--------__~------------..J 100 leD Imaxl ~--L--4--_----.--+------~---l 6/8 ~ SGS-ntOMSON At. iIIID©MIlI!.I<©'Ii'Ii@1li1lC$ ""!I 764 LOAD TDE1767 ,A-TDE1787,A Figure 16 : Parallel Driving of Loads Up to 1 A. O.15n V ref V ref TDE1m TDEl71r7 TDE11ii7 TDEl71r7 v, 100 k!l lmaxl USING ALARM OUTPUT Figure 17 : Parallel Alarm Outputs. ----~----------------~~----------~~----------ovee 10ku Alarm signal Figure 18: Led to vcc. -----1,.---......- - - - - 0 Vee Figure 19 : Led to Ground. -----<~-------o 5.6 kn Vee 7 TDE1m TDEl71r7 7 4 TDE1167 5.6 kll TDEl187 4 7/8 765 TDE1767,A-TDE1787,A Figure 20 : Interface between High Voltage and Low Voltage Systems. r--------------.------------~------. -- ..- Vcc';; +50 V VCC;'+6V 1 RSC r----- +1 + 1 V, note 4 and 5) Ise Short·eircuit Output Current (Vee = 30 V, t = 10 ms) 10l ~u~p'u: ~o: ~ela:a5g~ ~~;rent T = + 85 I (Vee = 30 V, Vo = 0 V) I (pin 1lsou,ee I(pin 61sink ~~:~\~~~~ ~~;;:~: r-' (in thermal 8 4 40 45 1 - 45 0.7 0.9 1.3 A - 1 1.25 V oC~--_-· I I 10 ,. mA = VCC - 2.5 V) I 4 8 shut·d~wn), ~1l._6L=.~'Jl~-'-111_~+-_:::- ::~ ! I-._V.:,t",h,-,(,.::.es::.:e,-,tl,-+-R_e_s_e_t_T_h_r_e_sh~________ ____ ___ __ I,esel Reset Output Sink Current (in thermal shut·down) for V,eset,,+0.8V r-Io-l-(O-P-e-n-G-N-o-I+-o-ut-P-u-t-L-e-a-ka-ge Current (open ground) --VBRvEo:=-'--o'-ut-P-ut-T-~a-n-si-st-o-rA-v-al-;;-nch~'v-o-lt-age(Ve~'--V-~)- .f- ~5 --1 + (lB_ 2 'I 6~ ~ ~_1 ~ ___ ..2__ - -;;; __ _401 L ~ --- -- [ V -1-0-0--+-"-A---l I I ! Available Alarm Output Current Output Source Current (V (Pin 1) 65 2 15 - 25 10 = 500 mA Output Saturation Voltage j - Input Voltage Range (note 4) V, Vee - Vo -, ---+----=- . __V__ _ mA -10 - i--_1_O_O_i--.c>,_A__1 -~1_0_.L __V_.J Notes: 2. For operating at high temperature, the TDE1798 and TDF1798 must be derated based on a -150C maximum junction temperature and a junction-ambient thermal resistance of 70 'CNV. 3. The offset voltage given is the maximum value of input differential voltage required to drive the output voltage within 2 V ofthe ground or the supply voltage. 4. Input voltage range IS Independent of the supply voltage. 5. The reference input can be the inverting or the non-inverting one. 3/12 769 TDE1798/TDF1798 POWER SUPPLY CURRENT. OUTPUT SATURAnON VOLTAGE. ~ < .§ ~ w a:: a:: ~ !:; o > z o 8 OUTPUT HIGH - 6 - 1. 5 1--- f - - I - -I ~ :> .. ~ !;( .. Q, Q, 20 10 50 40 30 ...., biJIII' ..,. I-<;\~ Tj= +25D C !; o 60 0 o "00 400 200 OUTPUT CURRENT ImAl ALARM OUTPUT CURRENT SINK (alter thermal shut down). ALARM OUTPUT CURRENT SOURCE (nonnal operation). < .§ .w !;; w II: II: (.> 20 '"z iii o 10 OUTPUT VOLTAGE IVI 20 OUTPUT VOLTAGE IVI RESPONSE nME. ~ JO Rl~100 VCC~ w Cl ~ 0 !l +30 V I::J 0 ...a. :> 2.5 w Cl 0 !:; w "«!:; 0 0 IQ, ~ 1 0 770 1 « 0 2.5 0 > .... :> a. TIME I._I 4/12 0 ~ > :> JO > ~ ~ Q, SUPPLY VOLTAGE IVI ::J ~ p- 0.5 I::J 0u;r"UITLpw I - I- ?5>0C ~'tJaC ;-:'P' ::J :> f-- '\~- - II: (.> - f--- --- w ~ 0 2 4 8 TIME!,.., 10 TDE1798/TDF1798 TYPICAL APPLICATIONS TYPICAL APPLICATION AUTOMATIC RESET -,-, TYPICAL APPLICATION CONTROLLED RESET ------- ------ Vee , - - - - - - - --1 l~ to :1~:flll>11 J -1~ ~Ok I " ...,..._ _-,1-,1 1 I I 1__ ' _______ J INI'ur ___- ! - - - I .I I ~--- SHORT CIRCUIT CONDITIONS WITH AUTOMATIC RESET OU,I'UT CUHH[NT JUNCTION TlMPlfIATUH[ t p 0 0 0 t SOURC[ t nESET AND SYNCt-IRO r ----- -t---' - I ALAIlM OUTPUT I f I i I 0 0 C4J--~ : nn0 I I. SHOlll CIllelll r ·1 5/12 771 TDE1798/TDF1798 SHORT CIRCUIT CONDITIONS WITH CONTROLLED RESET OUTPUT CURRENT t fl JUNCTION TEMPl:RATURl: t I_~~_. ALARM OUTPUT SOURCE t HLSET AND t SYNCHHO v--------. -- I I I I I I I I I I I. ~;lIOFlr -CIIICUI' • I DEMAGNETIZATION OF INDUCTIVE LOADS WITHOUT EXTERNAL CLAMPING DEVICES. This method provides a very fast demagnetization of inductive loads and can be used up to 150 mJ. With no external clamping device, the energy of demagnetization is dissipated in the TDE1798 output stage, and the clamping voltage is the collector emitter breakdown voltage V(BR) CEO. The amount of energy W dissipated in the output stage during a demagnetization is : W = V(BR) RL (10 _ V(BR) - Vcc L (1 R og + VCC) ) V(BR) - Vce Vcc Vee -- v (BBlCEO'-L-_"'-_ _ VCE V(BRICtO Vcc Remark 1 : This energy is dissipated inside the case, then rnust be included in the whole power dissipation. Remark 2 : The use of extemal clamping devices is recommended in case of parallel driving of loads. 6/12 772 The dispersion of the collector-emitter breakdown voltage V(BR) would induce the circuit with the lowest V(BR) to dissipate the whole demagnetization energy (which is roughly proportionnal to 102). TDE1798/TDF1798 A 1 AMP. DRIVER (reset may be either automatic or controlled) - - -.... --~----------------- ... -.~ ....- - - - -. . ~.-.- Vee -1 I~JrUT - - - - -.... TOE 1798 Vee TOE IUSI··1 (,ATf or nleOMMANDl D 1798 Vee ALARM OUTPUT SINK ALARM OUTPUT SOURCE ,-----------~---.--~ .-_--<~---_{) .. -~ , - - - - - - - 0 Vee Vee 8 2 TOE /f/ 1798 3 4 8 6 2 TOE 1798 7 3 4 7/12 773 TDE1798/TDF1798 PARALLEL ALARM OUTPUTS r---------------------.---------------~-------------ovcc 10 k!1 8 6 8 6 2 2 TOE TOE 1798 1798 3 3 4 71----0 4 ALARM SIGNAL INTERFACE BETWEEN HIGH VOLTAGE AND LOW VOLTAGE SYSTEM , - - - - - - - - - - - - - - - - - - - - - - - - -.. ---------------------------------------~ Vcc>+ 6V Vee ';;;+45V 0---- [ +lV----;E TDE1799 V ref 0-------; E ;? 1 V The reference input can be inverting or the non-inverting one. ELECTRICAL CHARACTERISTICS - 25 'C <:: Tamb <:: + 85 DC, 6 V <:: Vee <:: + 33 V, 10 <:: 500 mA, T) <:: + 150 'C (unless otherwise specified) --- ---- Symb~I)_ r-- Input Offset Voltage I cc Power Supply Current lIB Input Bias Current Min. Typ. Max. Unit 2 50 mV 3 4 mA (note 3) T amb ~ + 25 'C --.---------J 15 VICR . ~mmon-mode Inpu~ VO_~Ol~e Rang~ ___ .. (note4_)_____.___ } __ Input Voltage Range __ Test Conditions Parameter VIO ls~__ .1 vOl r---'- 10L I-- --I sink Short-Circuit OutPut~urrent Output Saturation Voltage - - . - -.. . -----.------- Vre ! 2 + 1 V, figure 1, note 4 Ireset ~~-r (VCC ~+ 30 V, Vo ~ 30 V, T J ~_-r 85 DC) V(pin 7) $ __ V V 700 I mA V 1.25 50 100 I ~A 15 - I mA .1 2 V 6 .._ . ________ for ~A I ~33 V, t ~ 10 ms, T amb ~ 25 DC - (VI + - VI - > 50 mv,! 10 ~ 500 mA Available Alarm Output Sink Current ~:~:~~o~~nk Current 25 VCC Output off Leakage Current ::::: _ 40 __ ~ 45 . I.. ~. ~:~:~~:::ge:~a:~~~~_=I-Vth(reset) I -=- 1 - . - - V(~i~~\e $5~ 0.8 V -II_-2.__ ~I~; '~~~~~:~~:iiIT {:;,~" : : :::~Ut I C 1~- 14~--G;--1 14 =. . +-mVA'I' 1 ___ --'-- + eli-~ '~o :~:I Notes: 2. For operating at high temperature, the TDE1799 must be derated based on a + 150 °C maximum junction temperature and a junction-ambient thermal resistance of 70 °C/W. 3. The offset voltage given is the maximum value of input differential voltage required to drive the output voltage within 2 V of the ground of the supply voltage. 4. Input voltage range is independent of the supply voltage. 5. After thermal shut down, voltage required to restart. 6. When in thermal shut down the reset pin 8 draws a current. 3110 781 TDE1799 Figure 2 : Supply Current I vs. Supply Voltage. Figure 3 : Alarm Output Current and Voltage. 88TDE1799-D2 88TDE1799-Dl --=- Is 10 ImA I ImA I - -- / 28 / f-- 3.5 / 28 3 /' 2.5 V =-- i-=- ~ / 12 II f--4 2 Hl f---- - U --~- 2 48 UsIUI 38 20 4 5 8 Uo I U I Figure 4 : Saturation Voltage I vs_ Output Current. BBTDE1799-D3 Usa t I U) 1. 25 .-:::;:::::::: -s-c:- ~ ~ -25"C .75 ~ >-:: '85" C .5 180 200 308 400 588 10imAI Figure 5 : Typical Application with Automatic Reset. Vee 10kn I TDE1799 '-----------------------------------------------" 4/10 782 TDE1799 Figure 6 : Short-Circuit and Over loads Conditions Waveforms. OUTPUT CURRENT FUNCTI?: ALARM VOLTAGE AND RESET OUTPUT VOLTAGE 0 11,~Jl~ I p t~--+'I~ ~ I n n n! I ! 1 I------ SHORT -CIRCUIT WITH VCC - I .. j .g:~:~ lL__...Jj'--_________--1I~___~_ Figure 7 : Typical Application with Controlled Reset. VCC I Vcc OUTPUT STATUS ALARM RESET RESET TDE1799 INPUT 3 4 5/10 783 TDE1799 Figure 8 : Short-Circuit and Over loads Conditions Waveforms. to ~ ---, I, t I OUTPUT CURflENT I JUNCTION rEMPERATURE " I ALAHM I OUTPUT VOLTAGE _1- tj STATUS OUTPUT VOLTAGE RE.SET INPUT t VOLTAGE I~ I I I I I C- SIIORT -CmCUIT WITH Vee I' Figure 9 : Output Status Function: Open Load Detection. IV"i"J~I~ Vllin21 oL-____~~____________~--------~~--------~ OUTPUT CURRENT 0 IL-------l--~'-+-----T-----4-F-~ I I STATUS OUTPUT VOLTAGE 0 1 I I I I I I --+I____---l________ L-____.......L_______ I ~L_ ~----__ LOAD DISCONNECTE D ~ Open load detection is possible during the hachured area when (Vpin 3· Vpin 2) (Output status) 1~ 6/10 784 ~ SGS·ntOMSON ... .,I ili~II:IiB@J;il.rn©1i"IiB@IlJ~©$ ~ I TDE1799 Figure 10. l Vee R liMn R1= Rlimit· Vrel VCC - Vrel REMARK: sometimes the user considers as an open load a load greater than R limit. In this case a resistor R1 must be connected between the output and ground. Figure 11 : Output Status Function Short Duration / Short Circuit Detection. INPUT OUTPUT VOLTAGE OUTPUT CURRENT OUTPUT STATUS VOLTAGE I 1 1 I limit \ [1 I 1 .. I I .. (INPUT) OSV 1 -7 CURRENT LIMITATION REMARK: long duration short circuit are detected by the thermal shut down. 7/10 785 TDE1799 RESET AND SYNCHRONIZATION Recommended diagram when the outputs are in parallel. After thermal disjunction a restart is possible when all the circuits are returned in operating conditions. Figure 12 : Synchronous Automatic Reset (Parallel or Independent Outputs). + 15 to 50 kn 3 B 3 TUE1799 2 B B 3 TDE1799 I UE1799 5 2 51 52 ------------------ ----------------- ----0 5 51/ Figure 13 : Synchronous Controlled Reset (Parallel or Independent Outputs). + 8 3 Logical TOE1199 voltage 15 to TDE1799 TDE1799 50 kfl R R ------, - ,-- I~-- ! ~ Oplion I (open colJeclor gate) Option II MAIN FEATURES • Vec' Vec 50 V • Maximum output current 0.5 A • Full protection against overloads and short circuits • No need of deadtime during rotation reversing • TTL compatible inputs • TDE1799 and TDE1798 input signals have the same reference • No automatic restart after disjunction 8110 786 FW/CCW o l_o~FF' 0 r--O---r-->- _ 1798 ° 17"- O~ ~;FT-%H I-----L----+---- L I OFF.! OFF I OFF.~ TDE1799 Figure 14 : Two Quadrants D.C. Motor Drive. 12k INlIOU2 !:I.uk u cw/ccw TOE 1798 1k .t 22j.1F 12k o I.!r~ ON/OFF RESET INPUT o ~2j.1F o J B.2k 40V 0; 1N4148 Figure 15 : ON OFF Cycles. TOE 1799 ToE1798 c! ON/OFF I START IN RUSH TO(1708 TO[1799 CURHl:NT~ UMITATION OUTPUT CURRENTS MOTOR Bemf VOLTAGE ACCROSS MOTOR oMotor inductance demagnetization. 9/10 787 TDE1799 Figure 16: Rotation Reversing. cw/ccw TOE 1798 OUTPUT CURR[;NT TOE1799 OUTPUT CURRENT h Lr"- h ~08AI V VOLTAGE ACCROSS MOTOR VCC+ , t I I . I ~O"A 1 I .. I I -- ~ t- .., r f\ 0 f-- ~ , - vcc Figure 17: Overload Conditions. TDE17!l8 INPUT I TOJ:1798 OUT/JUT CURRENT 1 TOE1798 ALARM OUTPUT HESET INPUT 1 ON f\-, !- I~ I I I J I· 788 .I TYPICAL MINIMU~_ 20 DURATION ~ #H. OVERLOAD • For instance overload during TDE1798 operation. 10/10 TOE 1799 INPUT OISADLED -I ... TDE3207 INTERFACE CIRCUIT (RELAY AND LAMP DRIVER) • HIGH OUTPUT CURRENT • ADJUSTABLE SHORT-CIRCUIT PROTECTION TO GROUND • INTERNAL THERMAL PROTECTION WITH HYSTERESIS TO AVOID THE INTERMEDIATE OUTPUT LEVELS • LARGE SUPPLY VOLTAGE RANGE: + 10 V TO + 30 V • SHORT:CIRCUIT PROTECTION TO Vcc MINIDIP/2 DESCRIPTION The TDE3207 is a monolithic amplifier designed for high-current and high-voltage applications, specifically to drive lamps, relays and stepping motors. This device is essentially blow-out proof. Current limiting is available to limit the peak output current to a safe value, the adjustment only requires one external resistor. In addition, thermal shut down is provided to keep the IC from overheating. If extemal dissipation becomes too high, the driver will shut down to prevent excessive heating. ORDER CODE: TDE3207DP The output is also protected from short-circuits with the positive power supply. The device operates over a wide range of supply voltages from standard ± 15 V operational amplifier supplies down to the single + 12 V or + 24 V used for industrial electronic systems. PIN CONNECTION N.C. Inverting input Non-inverting input GND September 1988 N.C. VCC Current limit Output 1/5 789 TDE3207 SCHEMATIC DIAGRAM r---------.---------------.----J7 vee Inverting input Non-inverting input I I ~ Rse Th..-mal protection I I '-------£:--t------------I5 Output (Va) I I I o RL I I ABSOLUTE MAXIMUM RATINGS Value Unit Vee Supply Voltage 36 V V/D Differential Input Voltage 36 V V, Input Voltage 36 V 10 Output Current 300 mA Symbol Ptot Toper T stg 2/5 790 Parameter Internally Limited W Operating Ambient Temperature Range - 25 to + 85 'C Storage Temperature Range - 65 to + 150 °C Power Dissipation TDE3207 ELECTRICAL CHARACTERISTICS - 25 'C s Tamb S + 85 ac, + 8 V S Vee S + 30 V, 10 S 150 mA, T j S + 150 'C (unless otherwise specified) Symbol Min. Typ. Max. Unit Input Offset Voltage - (note 2) - 2 50 mV 118 Input Bias Current - 0.1 1.5 Icc Supply Current (Vcc High Level Low Level Via Parameter = + 24 V, 10 = 0, VCM Common-mode Input Voltage Range Isc Short-circuit Current Rsc = 3.30) Vcc-Vo 10L los (Tamb = T amb = + 25 'C, Vcc = Output Saturation Voltage (output high) (VI + - VI -) ~ + 50 mV, 10 = 150 mA, Rsc Output Leakage Current (output low) Va Tj = + 25 'C Tj = + 85°C Minimum Short-circuit Output Current T amb-= + 25 'C, Vec = + 24 V, Rsc = = + 24 V, 0, Tj = 0 V, Vcc + 25°C = ~A mA + 25 'C) - 4 2 10 2 - Vcc-2 V - 250 - mA - 1.2 1.8 V - 1 - - 100 500 - 50 - - ~ + 24 V mA = = Noles: 1. For operating at high temperatures, the TDE3207 must be derated based on a + 150 'C maximum junction temperature and a junction-ambient thermal resistance of 110 ·CIW. 2. The offset voltage given is the maximum value of input voltage required to drive the output voltage within 2 V of the ground or the supply voltage. TYPICAL APPLICATIONS BASIC CIRCUIT 10 kl! RSC 3.3!l 10 kl! • 01 required for inductive loads 3/5 791 TDE3207 SUPPLY CURRENT VERSUS JUNCTION TEMPERATURE AVAILABLE OUTPUT CURRENT VERSUS LIMITING RESISTOR ~ Izw II: II: :l 0 I:l 11. I:l 0 0.7 ~r 0.6 0.5 T 0.4 0.3 r~ ...I 0.2 0.1 -- j 25°e =+ +---~ ,oooe Tease =+ I 1 w ID 5 case I ~~ .~ 0 ~ 2 6 0.5 L.-..L.--'------'_-"---'---'_ _-'----'----' 50 75 100 125 25 o 7 LIMITING RESISTOR (01 JUNCTION TEMPERATURE lOCI SATURATION OUTPUT VOLTAGE VERSUS CASE TEMPERATURE AND AVAILABLE OUTPUT CURRENT SlWI'L Y CURRENT VERSUS SUPPL Y VOLTAGE ~ w 5 4 3 t- f < .-~- ~ CI ~ o > C( 1.2 r-- C- I- ~ 0.8 I::l o 0.6 z V V 0.4 II: ::l 0.2 o -- P ;.,;. ,,r-L< >< c- ~ t7 KrZ' ~ "-.i'.. ,,/ ~ ~ 30 < 25 0 20 ~ > > ...I 11. 11. :l 20 SUPPLY SUPPLY VOLTAGE vs MINIMUM lIMmNG RESISTOR VALUE 15 50 mV, Notes: 2. For operating at high temperatures, the TDE3237 must be derated on a 150°C maximum junellan temperature and a Junction-am· bient thermal resistance as showed in the thermal characteristics data base. 3. The offset voltage given is the maximum value of input voltage required to drive the output voltage within 2 V of the ground or the supply voltage. SIMPLIFIED SCHEMATIC r-------.-----------D Rl Vee 0 I ~-----1:> Output Inputs Current limiting 3/4 797 TDE3237 TYPICAL APPLICATION BASIC CIRCUIT Rl R2 AVAILABLE OUTPUT CURRENT VERSUS LIMITING RESISTOR ~ ~ 0.7 z w I ::> SUPPLY VOLTAGE VS MINIMUM LIMITING RESISTOR VALUE 40 35 a: a: 0.6 I ~ 0 0.5 I Cl T ~ ... ::> 0.4 I ~ ::> 0 0.3 1 w ~ III « ;;: > « ~ 0.2 « = + 25:1C if T c"'. ! ~~ I 0.1 0 case w ~ 3 4 5 25 " ~ 0 20 ......>::> 15 > ~+ 100°C .<". ~ -'>..-- en I 11 2 30 j 10 6 2 LIMITING RESISTOR fill OL-~~ o __L-~~__L-~~~~ 50 100 150 200 AVAILABLE OUTPUT CURRENT fmAI 798 4 MINIMUM LIMITING RESISTOR VALUE fill SATURATION OUTPUT VOLTAGE VERSUS CASE TEMPERATURE AND AVAILABLE OUTPUT CURRENT 4/4 3 250 TDF1778 DUAL 2-A SOURCE DRIVER • OUTPUT CURRENT UP TO 2.5 A • WIDE RANGE OF SUPPLY VOLTAGES: + 8 to + 32 V • CAN WITHSTAND OVERVOLTAGES OF AS HIGH AS 60 V BETWEEN Vcc AND GROUND • INTERNAL ZENER DIODE PROVIDES FAST SWITCHING OF INDUCTIVE LOADS • OUTPUT VOLTAGE CAN BE LOWER THAN GROUND MULTIWATT-11 DESCRIPTION The TDF1778 is a dual source driver delivering high output currents and capable to drive any type of loads (Electrovalves, contactors, lamps). This device is essentially blow-out proof, each output is protected against short-circuits. If internal dissipation becomes too high, drivers will shut down to prevent excessive heating. An "ALARM" output is provided to indicate the action of the thermal protection. To reactivate the power outputs, the reset input must be forced to low state. "SENSE" information of both power outputs are ORed together and then processed internally. ORDER CODE: TDF1778SP A "STROBE" input is also provided to offer the possibility of disabling the power outputs. PIN CONNECTION - Output 1 9 8 4 3 2 -vee 3 4 5 - Output 2 6 - Ground 7 8 9 - Sense output - N.C. - Strobe - Input 2 - Alarm output 10 - Reset input 11 - Input 1 September 1988 1/8 799 TDF1778 BLOCK DIAGRAM Strobe r- ----------I I I I I Output 2 Output 1 Input 2 Input 1 I Alarm output I I I L _________________ _ Q1 --l------J Reset Sense output Ground input ABSOLUTE MAXIMUM RATINGS Symbol Vcc Parameter Supply Voltage V" Vreset Input Voltage (pins 7, 10 and 11) Strobe Input Voltage V strobe 10 Ptot Toper Tj Value V - 30 to + 50 V - 0.5 to Vcc V Output Current Internally Limited A Power Dissipation Internally Limited W - 40 to + 85 °C + 150 °C Operating Ambient Temperature Range Junction Temperature THERMAL DATA Maximum Junction-case Thermal Resistance Maximum Junction-ambient Thermal Resistance 2/8 800 Unit 35 V (60V/10 ms) 3 40 TDF1778 ELECTRICAL CHARACTERISTICS Vee; + 24 V, - 40 'C < T j < + 85 'C (unless otherwise specified) Symbol Parameter Min. Vee Power Supply Voltage 8 Icc Power Supply Current (pin 6), 101 = 102 = 2 A - VIL VIH Logic Input Voltage (pins 7, 10, 11) - Typ. Max. Unit 32 V - 20 mA - 0.8 V 2 - VI Logic Input Threshold (pin 5) - 0.8 - V IIH High Level Input Current (pins 7, 10, 11) VI = + 2 V - 20 50 >t A Low Level Input Current (pins 7, 10, 11) VI = + 0.8 V -5 0 +5 !lA High Level Logic Output Voltage (pins 8, 9) 1(8) = 1(9) = - 30 >tA 2.4 4 - - 0.4 1.5 1.8 400 1000 40 44 48 - - IlL VOH VOL Vee - VOl Vee - V02 10L Low Level Logic Output Voltage (pins 8, 9) 1(8) = 1(9) = 2 mA Output Saturation Voltage (V(7) high, V(II) high, 10 = 2 A) V - Low Level Input Current (pins 1, 3) V(7) Low, V(II) Low, Vo = 0 V Vee - VOl Switch-off Output Voltage (inductive load) Vee - V0 2 101, 102 V Available Output Current (pins 1, 3), V(7) High, V(II) High, Vee - Vo = 32 V, T J = 25 cC V !lA 100 V mA - - IOalarm Available "Alarm" Output Current, V(9) = + 4 V 4 8 - mA losense Available "Sense" Output Current, V(8) = + 4 V 4 8 - mA IIHsense Output Sensing High Level Input Current (pins 1, 3) VI = + 2 V - 1 2 mA 0.8 1.9 2.5 V V IHse n S8 High Level "Sense" Input Voltage (pins 1, 3) 3/8 801 TDF1778 AVAILABLE OUTPUT CURRENT OUTPUT SATURATION VOLTAGE 2.00 ~ 2: Tj=25°C IZ ~ ...... 3 a: 1- r- ~ .. ::J U tu ~ roo .. I- ::J " '" , ..... ~ ~ I j -.- 85°C i':: 2 ::J o w -' ~ 1 .. ;{ > '.70 1.60 ~ 1.50 a 1.40 -: .......... "' .... Tj-o';2~OC ~ 5 +24 v_ ~ .- c- ~ .-- r.. I', roo .. .. 10 ::J 1.20 ~ 1.10 ~ Ii'?' I- ~ ~ .90 0.00 .25 50 I -f - t + B5 "C ,25"C 75 1.00 1.25 1.~ 1.75 2 .80 30 r----- Vee - Vo IV) OUTPUT CURRENT (AI AVAILABLE ALARM OR SENSE OUTPUT CURRENTS POWER SUPPLY CURRENT 24 r---_r--_,----~--_r--_,----,_--~--_, I S I- I- - Z ~ w a: a: a: C( ::J u U '"Z J ~ ~ '" ---- - .. --- ~ OUTPUT LOW 1---- --- T I 1:' POWE:.n SUPPLY VOLTAGE (V) ALARM OR SENse OUTPUT VOL TAG[ (V) MAXIMUM OUTPUT CURRENT VS LOAD INDUCTANCE ~ i"".. ~ ........ I- Z w a: a: J ~ CON~IDEN6E ........ ........ r-.... ""'" u r- - I I ,I I ~CC=16V ..... VCC:::30 V . I- J I::l o :; J :;; X « :;; o 25 50 75 LOAD INDUCTANCE (mH) 4/8 802 2.:"') 7.50 - - OJTf>UT H I G I I 101 -·102-= 2A I ,. ::J ~ I ;{ 12 516 (X) 16 T amb = 1- 2S Cl C ;{ '7" ~ 7' . I ~ J o --- Tj~-40"C~~ 1.00 I- - ...... ."". 1.30 « IV> -- ... fi"" I- '"i'. '" .. ..... ~ , vcc'c 1.90 1.80 100 TDF1778 OPEN LOAD DETECTION Input [1[2 Strohe ! . D 1 1 -.-1 OUIPU(-4_ _- - '_ _~_~_~-----------------current Sen'" output LLLCCl-----L Normal ----~+------- Opcr__--- _, JUrl!.;liOI-+_ _ I temlJoCrature AI.'m + __---J-:_ _ _ _ _ _ _ _ _ _ _--4_L-_ _ _~ output RESET -+__ --.-J1_ _ _ _ _ _ _ _ _ _ _l-_ 1 . . -_ _ _ _ _ __ 1 ~--- f -. I. Shor(-circuil ---~·-jl DEMAGNETIZATION UNDER INDUCTIVE LOAD Vee Vee Vo Vee~---, 6/8 804 TDF1778 TYPICAL APPLICATION TYPICAL APPLICATION WITH TDF1778 TWO INDUCTIVE LOADS 2 A - 24 V Vee ,., 24 v sTnorlr LOGICAL TDF1778 CONTROL UNIT 5[NS[ OUTPUT I\LARM OUTPUT " f--~-C'3J 9 Load: LC ~ 8OmH. Rmo. ~ Vcd2 rnA Rc·~ 6 n Load: Lc = 80 mH, Rc = 12 n Rma, = Vccl1 mA MAIN FEATURES This application protected against short circuits. The load disconnection is detected when inputs E1 and E2 are low and the sense output is high. When thermal protection is activated the pin 9 is low. Inputs and outputs are TTL comptable. 7/8 805 TDF1778 TDF1778 HIGH CURRENT APPLICATION WITH INDUCTIVE LOAD 24 V - 4 A Vee :.: 24 V I 1 C 1'~1I ~7 RES!:: r 1--------1 10 LOGICAL TDF1778 . CONTROL 'i I OUTPUT I ,I r' I . I I ~ , I.e I 0: L;l" I fIC --l .,\,.," -1 9 1_:.::AL;::::A""RM",--,o",U",TPc::uccT load: LC = 8OmH, RC '"'- 6 Rmax '- VCcl2 mA n Load: Lc ~ 80 mH, Tc Rmax ~ Vcc/2 mA ~ 6 n MAIN FEATURES This application has the same features as the dual 2 A -12 V application. 8/8 806 " '--t' C3.J 3-----J1-----..- UNIT S[NSr: T ~ 1_---=5-"T""'0"'' .;...r----15 1:1 I TDF1779A DUAL 2-A SOURCE DRIVER --------------~---------~ • OUTPUT CURRENT UP TO 2_5 A • W[DE RANGE OF SUPPLY VOLTAGE: + 8 V TO + 26 V • CAN W[THSTAND OVERVOLTAGES OF AS H[GH AS 60 V BETWEEN Vee AND GROUND • OUTPUT VOLTAGE CAN SWING TO LOWER THAN GROUND • "SENSE" AND "ALARM" OUTPUTS ARE OPEN COLLECTOR OUTPUTS ------------~--- ~~-----.--- MULT[WATT-11 ~ DESCRIPTION The TDF1779A is a dual source driver delivering hihg output currents and the capability to drive high[y inductive loads (E[ectrova[ves, contractors, re[ays ... ). . . .""""' .•.". ;.....• , x·. g.~, ;' This device is essentially b[ow~out proof, each out~ put is protected against short~circuits. [f internal dis~ sipation becomes too high, drivers will shut down to prevent excessive heating. An "ALARM" output is provided to indicate the action of the thermal protec~ tion. To reactivate the power outputs, the reset in~ put must be forced to [ow state. \ -:,- ORDER CODE: TDE 1779ASP "SENSE" information of both power outputs are ORed together and then processed internally. A "STROBE" input is also provided to offer the pos~ sibi[ity of disabling the power outputs. PIN CONNECTIONS 11 10 9 a 7 & 5 -4 3 1 - Output 1 ~ Vcc ~ Output 2 ~ N.C. 5 ~ Strobe 6 ~ Ground 7 ~ Input 2 8 ~ Sense output 9 ~ A[arm output 10 ~ Reset input 11 ~ Input 1 2 3 4 Tab is connected to pin 6 September 1988 1/7 807 TDF1779A BLOCK DIAGRAM r- ---~------- I I I I I I I I I I I Input 1 Alarm output r I I I L_________________ _ input MAXIMUM RATINGS ---_.- - - Symbol Parameter - - - - - Vee VI, V reset Vstrobe 10 _ P", Toper S_upply Voltage Input Voltage (P ins 7,10 and 11) Strobe Input Vol tage -_:- -;~t-.-te-.m-p~~,",: :-ng-e-_-_~·_· -·_-_~·_·~_-_~_ 35 V (60 V/10 ms) V - 30 to + 50 V -+ - Output Current I~WO' D;";,,t ___ Operating Ambi I 0.5 to Vcc----i---Y_ ·--:~i:.~:~. : :~;:: I. . ~ -------~- ____ Tj _ Junction Tempe rature THERMAL CHARACTERISTICS Maximum Junction-case Thermal Resistance Maximum Junction-ambient Thermal Resistance -~~------.-.----------.--- 2/7 808 _ + 150 _ I °C I TDF1779A ELECTRICAL OPERATING CHARACTERISTICS = + 24 V, - 40 'C < Ti < + 85 'C (unless otherwise specified) Vee t~_~~~~I=-~power~~p-PI;~~i~~~~h:~a:t~riStiCS -- - ---- -------~-~='-~~·l I--~:I~ :~;:rl~:~p~O~:9~e~i;~~ 1~.'111~1=IO'2, = 2A_ VIH 1_ _ _ _______ .___________ _______ IIH , High Level Input Current (pins 7,10,11 VI = + 2 V 1-=-_!IL=-r~~V'I L~~li~p~tc;;~rent(pi~~ 7,10,11) VI~~ 0.8 V -5 :___-_ _ ; Off State Ou.!pLJt.~oltag_e..(£irl~8~U(8L:J(9) =2_rTl/\ I ~~~ =~g~ V(7) Low, V(11) Low, VO = 0 V ~-- -- Vee - V01 Vee - V02 _ , - - - - - - --- -- - -- Unit 26 V 20 mA V I 0.8 V 20 ,IA 0 _ + 5 flA 0.4 V V 1.5 1.8 ----------._---------,-------+------ 400 -- -~ ,IA 1000 SWitch-off Output Voltage (Inductive load) Note 1 V 45 101, 102 _ 1 Max. !Output Saturation Voltage (V(7)high, V(11) High, 10 = 2A) '~;O-L-~'; 1.~;el-OutPut Cur~~~t pi~S-13) --- I 2 __ ....'\Ir.__~ogic;~~t_!_hr~S~~cijrlin_5_)_____________ _ , Typ. Available Ouptut Current (pins 1,3), V(7) high, V(11 p) high, Vcc-Vo=26V,TI=25°C mA 10 10 Alarme ,. Available "Alarme" Output Current, V(9) = + 4 V 4 8 mA 10 Sense I Available "Sense Ouptut Current, V(8) = + 4 V 4 8 mA IIH Sense Note: r-Ou;P~t-S-;'~sing high Level Input Current (pins 1,3) VI =~-2V 2 mA 1. An external discharge circuit is required for inductive loads. 3/7 809 TDF1779A AVAILABLE OUTPUT CURRENT I- T'-U 2.00 ~-r-.----'----'--'--.--'--'-----'----' ~ 190 .1;:'. ~. ". .. . o . " "" . Tj =85"C 1 OUTPUT SATURATION VOLTAGE o ~ i' 125~ , I I VCC= t24 v+--+~+--+-+--+_I--I I--t--I-+--+-+--+-I-+--+--:J I--t--I-+~f -+--+-1-+--+'" 1.60 1--t--I-+--+-+--t--I--b.""'f--1 1 80 1 ,70 1.SO I--t--I-+--+-+--+-t.~~'-+--­ g 1AO f---+-I-+ --t-+--:J."f--+--+--I ~ ::: t::::::t::::::t:::~::::::~~~~... ~~!~~:::t=--1I----t_--I ...... ,~. T- = 10 ~ ~ ~, 20 ~ ~ 1. 10 o 80 h"-'-M;lb-,,,,""S!SW;C-+--+'~I-+--+--1 '.00 Tj_ % w ' lj -. + 85"C 0.00 30 25 .50 75 100 1,25 1,50 175 200 225 2 POWER SUPPLY CURRENT 16 T"mb'- -t-25"C - , , 12 -OllTPLJT 10' ,02 I -_ ...... - .-- 4/7 810 , , HIJ.-l2A , OUTPur LOW ---T , 15 ALARM OR SENSE OUTPUT VOLTAGE (VI f>() OUTPUT CURRENT IAI Vee Vo IVI AVAILABLE ALARM OR SENSE OUTPUT CURRENTS +--+-1-+--+ L-~Vc...oA""r=L_"-'·_'"_.-,'2_5°_C-'---'-_L-...L-~~ POWERSUPPlV VOLTAGE IV) -, , TDF1779A OPEN LOAD DETECTION 'nPUI...,!r----'___________ --L_ _ _ __ £1-[2 I I ------'-D--l~~_ _ 51E 1 dll; LOAD a~ : ' OUTPUT...?~ H +----i LInlT I- u~c - - a- }6U I : : - CURRENT UOL TRI>E • t "-'c:a g I I !: • t : : . I I • t I CA~~~~~OR (Q: ==: =:~= =:~ - - - - - - - - - - - -~;: iL.lj ~ UOL TAGE a - 4 9: MINIMUM RESET SIGNAL DURATION (9 ~ ~ 20 ~A (Tl); ~ ~- - ~, OUERLORO PRESENCE.' lOrnA (T3) ~ 10 ~s -'_T~' ,......., • t BBTOFI?B3-55 typ) (typical values) dt dt The sequence discribed above will be repeted as long as overload conditions will remain. 5/7 819 TDF1783 Figure 8 : Thermal Shutdown. -~'--~'-~-'------l INPUT VOLTAGE I 1 L - - - - - - - - - - - - - - -__,~~--_+_r~------------~•• t : LOAD CURRENT OUTPUT VOLTAGE 1 L-____________~________~>~'~<----~I~-L----------------.. t I I '~--TH~17B·~ 1 I : - TL I --~:~------ L -____________71-------,~---L,~----------------.. DELAY CAPACITOR VOLTAGE t 6U --------~I ~U________ .L C ~"'55uA C ~ -lBmA L-__~d~t~-______~L-----~~--T_._~--~d~t--------.t I lr--< B riT4 , I The thermal protection turns off the 3 outputs simultaneously (TH - TL ~ I 88TOF1?83-S6 30°C is the thermal hysteresis). Any erra- tic restarts will be avoided when T4 is shorter than the duration given by the thermal hysteresis. • 6/7 820 TDF1783 Figure 9: Output Stage and Current Limitation . .---------~~-- .... -~--.----. ---_._---._----------------------------------------, Ucc RB iB UB Ucc RL 10 Rsc 88TDF1783-57 • Rsc calculation Tj ~ t50 °c ;2VBE (Rsc 10). 3:"5 < 460 mV } ~ _ VBE < Rsc. 10 < 0.805 V Re calculation RB= VCC-~B:. 3· (VB'" 2 V, i F: 50 IlA at 10:::: 1.5 A) 11 POWER DISSIPATION OF THE TDF 1783 P = (Vee. Icc) + n (Vee sat. lo) + iB (VB - RSC ·Io) n : number of conducting outputs Vee sat = Va - VRSC Rsc.lo = VRSC PROTECTION AGAINST ELECTROSTATIC DISCHARGES context, guarantee an electrostatic discharge protection up to 200 V. Usual cautions have to be taken to protect delay and input pins against parasitic discharges. Other pins are protected up to 2 KV. The inputs are designed to operate from - 30 to + 50 V. This characteristic, useful in an industrial 7/7 821 TEA3717 STEPPER MOTOR DRIVER -------------------- • HALF-STEP AND FULL-STEP MODE • BIPOLAR DRIVE OF STEPPER MOTOR FOR MAXIMUM MOTOR PERFORMANCE • BUILT-IN PROTECTION DIODES • WIDE RANGE OF CURRENT CONTROL 5 TO 1000 mA • WIDE VOLTAGE RANGE 10 TO 45 V • DESIGNED FOR UNSTABILIZED MOTOR SUPPLY VOLTAGE • CURRENT LEVELS CAN BE SELECTED IN STEPS OR VARIED CONTINUOUSLY POWERDIP 12 + 2 + 2 DESCRIPTION The TEA3717 is a bipolar monolithic integrated circuit intended to control and drive the current in one winding of a bipolar stepper motor. The circuit consists of an LS-TTL compatible logic input, a current sensor, a monostable and an output stage with built-in protection diodes. Two TEA3717 and a few external components form a complete control and drive unit for LS-TTL or microprocessor-controlled stepper motor systems. ORDER CODE: TEA3717DP CONNECTION DIAGRAM (top view) ~ 1 16 SENSE RESISTOR 2 15 OUTPUT A GND 13 GND GND 12 GND 11 REFERENCE OUTPUT 8 PULSE TIME V. (8) INPUT 1 PHASE September 1988 INPUT ~ 1/7 823 TEA3717 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vmm Power Supply Voltage (pins 14,3) Vcc Logic Supply Voltage (pin 6) Vin Vin Vv lin 10 Output Current Tj Junction Temperature Unit 45 V 7 V V Input Voltage Logic Inputs Analog Inputs Reference Input Input Current Logic Inputs Analog Inputs I,n Value - 0.5 to 6 Vcc 15 mA - 10 - 10 , T stg Storage Temperature Range Toper Operating Ambiant Temperature Range ±1 A + 150 °C - 55 to + 150 °C o to + 70 °C THERMAL DATA Maximum Junction-pins Thermal Resistance Maximum Junction-ambient Thermal Resistance 11 45* Soldered on a 35 mm thick 20 em' PC board copper area SCHEMATIC DIAGRAM Vmm Ph 11 10 GND c 2/7 824 T E TEA3717 RECOMMENDED OPERATING CONDITIONS Symbol Value Parameter Min. Unit Typ. Max. 5 Vcc Supply Voltage 4.75 5.25 V Vmm Supply Voltage 10 - 40 V 10 Output Current 0.020 - 0.8 A Ambient Temperature 0 - 70 °C te Rise Time. Logic Inputs - - 2 ~s tl Fall Time, Logic Inputs - - 2 ~s Tamb ELECTRICAL CHARACTERISTICS, Vee = 5 V, ± 5 %, V mm = + 10 V to + 40 V, = 0 'C to + 70 'C (unless otherwise specified) Tamb Symbol Parameter Min. Typ. Max. Unit - - 25 mA High Level Input Voltage - Logic Inputs 2.0 - - V Vil Low Level Input Voltage - Logic Inputs - - 0.8 V IIH High Level Input Current - Logic Input (V I = + 2.4 V) - - 20 ~A Low Level Input Current - Logic Inputs (VI = + 0.4 V) Icc Supply Current VIH - 0.4 - - mA VCH VCM VCl Comparator Threshold Voltage (VR = + 5.0 V), 10 = 0,1, =0 10 = 1,1, =0 10 = 0,1, = 1 390 230 65 420 250 80 440 270 90 mV Ico Comparator Input Current - 20 - 20 ~A loll Output Leakage Current (10 = 1, 1, = 1) Tamb =+ 25°C Tamb =+ 70°C, Vs =40 V, Vss =5 V - - 100 100 200 Vsat Total Saturation Voltage Drop (10 = 500 mAl - - 4.0 Ptot Total Power Dissipation 10 = 500 mA, fs = 30 kHz 10 = 800 mA, fs = 30 kHz - 1.8 3.7 2.3 toll Cut off Time (see figure 1 and 2, V mm = + 10 V, ton ~ 5 ~s) 25 30 35 td Turn off Delay (see figure 1 and 2, T amb = + 25 'C, dVC/dt ~ 50 mV/j.Ls) - 1.6 III ~A V W - j.Ls ~s 317 825 TEA3717 Figure 2. Figure 1 (see note). Motor winding ~ i-vMA. VM' VM'· VMA 0, M,\ Phase Mfl Vmm I I normalized I Is ton + toft Vcc GNDO----Ec FUNCTIONAL DESCRIPTION The circuit is intented to drive a bipolar constant current through one motor winding. The constant current is generated through switch mode regulation. The re is a choice of th ree different cu rrent leve Is with the two logic inputs 10 and h. The current can also be switched off completely. INPUT LOGIC If any of the logic inputs is left open, the circuit will, treat it as a high level input !····I·o-·rl~=_ _ ~urrent Level_ H L H L H H L L No Current Low Current Medium Current Maximum Current PHASE - This input determines the direction of current flow in the winding, depending on the motor connections. The signal is fed through a Schmidttrigger for noise immunity, and through a time delay in order to guarantee that no short-circuit occurs in the output stage during phase-shift High level on the PHASE-input causes the motor current flow from MA through the winding to Ms. Note: Rs "'" 1 0, inductance free Rc~1kn 4/7 826 Cc ~ 820 pF, ceramic Rt ~ 56kn Ct ~ 820 pF, ceramic 10 and h - The current level in the motor winding is selected with these inputs. The values of the different current levels are determined by the reference voltage VR together with the value of the sensing resistor Rs. CURRENT SENSOR This part contains a current sensing resistor (Rs), a low pass filter (Re, Ce) and three comparators. Only one comparator is active at a time. It is activated by the input logic according to the current level chosen with signals 10 and h. The motor current flows through the sensing resistor Rs. When the current has increased so that the voltage across Rs becomes higher than the reference voltage on the other comparator input, the comparator output goes high, which triggers the pulse generator and its output goes high during a fixed pulse time (toff) , thus switching off the power feed to the motor winding, and causing the motor current to decrease during toff. SINGLE-PULSE GENERATOR The pulse generator is a monostable triggered on the positive going edge of the comparator output TEA3717 The monostable output is high during the pulse time, toff, which is determined by the timing components Rt and Ct. toff = 0.69 ·R t Ct It should be noted however, that it is not permitted to short circuit the outputs. Vee, Vmm , VR The circuit will stand any order of turn-on or turn-off The single pulse switches off the power feed to the motor winding, causing the winding current to decrease du ring toff. of the supply voltages Vss and Vs. Normal dV/dt values are then assumed. If a new trigger signal should occur during toff, it is ignored. Preferably, VR should be tracking Vee during poweron and power-off. OUTPUT STAGE ANALOG CONTROL The output stage contains four Darlington transistors and four diodes, connected in an H-bridge. The two sinking transistors are used to switch the powersupplied to the motor winding, thus driving a constant current through the winding. The current levels can be varied continuously either if VR is varied or with a circuit varying the voltage fed into the comparator terminal (see fig.1). Figure 3. ,----------------------------.~.--~-.------ Motor winding GN L _________________ ~- Functional blocks A TTL compatible input logic B. Current sensor e. Single-pulse generator (monostable) D. Output stage with protection diodes. 5/7 827 TEA3717 Figure 4 : Typical Sink Saturation Voltage vs Output Current. VsatlU IVI r-4 - e- - ._-- r- 1--- - I-- - I""- o - 10- 0.1 ."".. i--'" 4 - 3 -I-- ImlAI TA ./ =-t- 2SoC V t-- - ~ ", 828 I-- - ~ ~ ~ ;,.;;;~ . -r- ~ - r--r-- r- o O.B 4 6/7 .. I- IWI 0.4 ._- t---r-- 1-- I--- - Ptat 0.2 "+ -_. -~. 1--- f-- Figure 6 : Typical Power Losses vs Output Current. , t-- r- 0.5 3 -h:L-L~ Tamb 25"C I--- - - r--- f-I- - ~ 3 - IVI Tamb =+ 2~C -- - VsatlHI ) LJ - Figure 5 : Typical Source Saturation Voltage vs Output Current. 0.6 O.B 1m IAI 0.1 0.5 0.8 ImlAI TEA3717 TYPICAL APPLICATION Figure 7 : Serial Printer Carriage Drive. o From ,. -processor Carriage stepper motor Figure 8 : Principal Operating Sequence. I Printing speed with Stand by with I halfstep motor drive holding torque I Im-250mA I -_-_-.:_J Im=90mA I I 2 3 4 5. 6 .7 8 IOA------I;-..:-.................;:;......::.......:::'"""-!~'::"'O; ! ItA I I Carriage return with full step motor drive Im=500ma .-+:______ n PhA~~------+-n---r--t--_-------------- -----~--- Phe ----1--I :~ d -500~=- ~ _____ ~ Motor current PhaseA SOOmA---- - ----- hanging --- 1_ _____ Phasee ~ p~ase at this point gives faster current decay -~n-n-- =--~~ _LrL __ : SOOnv\ __ - - - - - - - - - - - r~---=r-n-n -SOOnv\--==' ____ 1_ _ _ _ _ _ U_W__ _ 7/7 829 TEA3718 TEA3718S STEPPER MOTOR DRIVER ADVANCE DATA • HALF-STEP AND FULL-STEP MODE • BIPOLAR DRIVE OF STEPPER MOTOR FOR MAXIMUM MOTOR PERFORMANCE • BUILT-IN PROTECTION DIODES • WIDE RANGE OF CURRENT CONTROL 5 TO 1500 mA • WIDE VOLTAGE RANGE 10 TO 50 V • DESIGNED FOR UNSTABILIZED MOTOR SUPPLY VOLTAGE • CURRENT LEVELS CAN BE SELECTED IN STEPS OR VARIED CONTINUOUSLY • THERMAL OVERLOAD PROTECTION • ALARM OUTPUT (TEA3718SP) OR PREALARM OUTPUT (TEA3718SSP) DESCRIPTION The TEA3718 and TEA3718S are bipolar monolithic integrated circuits intended to control and drive the current in one winding of a bipolar stepper motor. The circuits consist of an LS-TTL compatible logic input, a current sensor, a monostable and an output stage with built-in protection diodes. Two TEA3718 or TEA3718S and a few external components form a complete control and drive unit for LS-TTL or microprocessor-controlled stepper motor systems. POWERDIP 12 + 2 + 2 ORDER CODES: TEA3718DP TEA3718SDP MULTIWATT-15 ORDER CODES: TEA3718SP TEA3718SSP PIN CONNECTIONS (top views) TEA3718 1·Vee 2·1, 3·Ph 4·10 S·G 6-Vref 7·ALARMOUT 8·GND 9·NG 10-Vmm 11-T 12-MA 13-E 14-MB 1S-Vmm TEA3718S 1 ·Vee 2·1, 3·Ph 4·10 S·C 6- Vref 7· PRE·ALARM OUT 8·GND 9·NG 10-Vmm 11-T 12-MA 13-E 14-MB. 1S-Vmm TEA3718 TEA3718S MB E MA Vmm Vmm GND GND GND GND vee VR 11 C Ph 10 September 1988 1/13 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notioe. 831 TEA3718-TEA3718S BLOCK DIAGRAM MA Vmm MB ~HASE 11 10 ,..:z::;,--+---+r--ch--+r-+' GND c T E CaMP_INPUT AND ALARM OUT ALARM OUPUl TEA3718 SP ONL Y MA MB PHASE 11 ~--+---+~~-+T-~ 10 GND c 2/13 832 T E PRE-ALARM OUPUl TEA3718SSf TEA3718-TEA3718S ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vmm Parameter Supply Voltage Value Unit 7 50 V V Input Voltage Logic Inputs Analog Inputs Reference Input Vcc 15 Input Current Logic Inputs Analog Inputs -10 -10 10 Output Current ± 1.5 A T) Junction Temperature +150 °C o to + 70 °C -55to+150 °C VI II Toper Tst9 V 6 mA Operating Ambient Temperature Range Storage Temperature Range THERMAL DATA Rth ()-c) Rth ()-a) Maximum Junction-case Thermal Resistance °C/W Powerdip Multiwatt 11 Powerdip Multiwatt 45" 40 3 Maximum Junction-ambient Thermal Resistance °C/W " Soldered on a 35 ~m thick 20 cm' PC board copper area. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Min. Typ. Max. Unit Vcc Supply Voltage 4.75 5 5.25 V Vmm Supply Voltage 10 - 45 V 1m Output Current 0.020 - 1.2 A 70 °C Tamb Ambient Temperature 0 tr Rise Time Logic Inputs - - 2 /.!S tf Fall Time Logic Inputs - - 2 /.!S 3/13 833 TEA3718-TEA3718S MAXIMUM POWER DISSIPATION Ptat 5.0 \ \ (W) 4"0 3"0 1\ \.. 1 "" '" "~ - 2"0 POWERDIP 45°C/W ~ 1.0 MULTIWATT WITH lO°C/W HEATSINK i\ ~1 ~ 0 o - \ roo- 50 100 150 TallluoC Figure 1. Motor winding ~ MA MB Phase Vee ----()Il Rs = 1 0. INDUCTANCE FREE Rc= 4700. Cc = 820 pF CERAMIC Rt= 56 ko. Ct = 820 pF CERAMIC GND O----_&;:: P =5000. R2 = 1 K I I ~ 4/13 834 TEA3718-TEA3718S ELECTRICAL CHARACTERISTICS, Vee = 5 V, ± 5 %, V mm = + 10 V to + 45 V, = 0 °C to + 70°C (unless otherwise specified) Tamb Min. Typ. Max. Unit Icc Supply Current - - 25 mA VIH High Level Input Voltage - Logic Inputs 2 - - V Vil Low Level Input Voltage - Logic Inputs - - 0.8 V IIH = + 2.4 V) Low Level Input Current - Logic Inputs (VI = + 0.4 V) Comparator Threshold Voltage (VR = + 5 V) 10 = 0,1, = 0 10 = 0, 1, = 0 10 = 0, 1, = 1 - - 20 I-lA Symbol III VCH VCM Vel Parameter High Level Input Current - Logic Inputs (VI - - mA 390 230 65 420 250 80 440 270 90 mV - 20 - 20 I-lA = 1, 1, = 1, Tamb = + 25°C) Total Saturation Voltage Drop (1m = 1 A) Powerdip - - 100 I-lA - - 2.8 Multiwatt - - 3.2 Ico Comparator Input Current IOff' Output Leakage Current (10 V sat -0.4 = 1 A, Is = 30 kHz = + 10 V, Vton > 5 I-lS) Turn off Delay (see figure 1 and 2, Tamb = + 25 ac, V Ptot Total Power Dissipation - 1m - 3.1 3.6 W toff Cut off Time (see figure 1 and 2, V mm 25 30 35 I-lS td - Vsat Iref V sat Alarm Output Saturation Voltage - 10 (only CB-501 package) = 2 mA (Powerdip) (Multiwatt) Vf Isub V sat Diode Forward Voltage Substrate Leakage Current Sink Diode Transistor Pair Saturation Voltage (Powerdip) (Multiwatt) Vf I-ls V - 0.8 - - 0.4 1 mA 1m = 0.5 A 1m = 1 A 1m - 0.5 A 1m = 1 A If = 0.5 A If = 1 A If = 1 A - 1.05 1.35 1.1 1.25 - 1.2 1.5 1.3 1.7 1.5 1.7 5 V 1m = 0.5 A 1m = 1 A 1m = 0.5 A 1m = 1 A If = 0.5 A If = 1 A - 1 1.2 1 1.1 1.2 1.3 1.3 1.5 1.4 1.5 Reference Input Current, V R = 5 V Source Diode Transistor Pair Saturation Voltage - 1.6 dVC/dt> 50 mV/I-lS) Diode Forward Voltage V V mA V V V 5/13 835 TEA3718-TEA3718S LOWE R Dlom-. VF- VS lOUT and T J SINK DRIVER VeE sat VS lOUT and Tj v v 12 Tj=250C , ~50C -:::. b==~=1~OC 0.6 I - Tj:::0250C ___ ~V~ L.,...--:b== ~~ ...... 08 12 L,.....--V ~ ~ ~~ 0.8 ~ It fj'-;C850C 0.6 i _125 0 C 0.4 04 0.2 0.4 0.6 0.8 02 1A SOURCE DRIVER VeE sat VS lOUT and Tj v 1.2 ,~ Tj:;'O~ V 08 ~ 0.6 ~~ V ~ ~ IiII"" ~ Tj;::12SoC \0 T)=65 C 0.4 0.4 0.8 0.6 1--11---4---+-+- - I - - - 1A ---- 08 0.6 ,A V rc t=5V I---- 8 6 -- I- -- -- I-----I-- I-- I---- I----- - - ~ 21--- '" tvlN comp 5V 1--- - I----- 2 r--... ~ 0.25 1A COMPARATOR INPUT CUHHFNT VS Tj ilnd Vc I '"" r"-. 0.4 0.2 'ref VS JUNCTION TEMPERATURE 0.3b 1A UPPER DIODE Vr- VS IOUTandT j 0.4 0.2 DB 0_6 04 IN c:c_np 4 - f--- 1--f - I--- 6 I'" 8 10 0.2 -]5 6/13 836 25 25 75 125 °c - 75 25 75 125 °c TEA3718-TEA3718S FUNCTIONAL BLOCKS MOTOR WINDING SCHMIDT TIME PHASE LOGIC 11 INPUTS IO·~---+----il~iI-rr-·1l GND VCC 11~ ALARM ---r RC Cc J; 820pF RS Note: T1 and R.can be omitted il MOS logic is used. 7/13 837 TEA3718-TEA3718S Figure 2. VMAVMBorVMB-VMA normalized ton + 'off Id -----4t FUNCTIONAL DESCRIPTION The circuit is intented to drive a bipolar constant current through one motor winding. The constant current is generated through switch mode regulation. There is a choice of three different cu rrent levels with the two logic inputs 10 and h. The current can also be switched off completely. INPUT LOGIC If any of the logic inputs is left open, the circuit will treat it as a hig h level input. =rrm~wcc~~~~, c~"","", I H L L L Medium Current Maximum Current PHASE - This input determines the direction of current flow in the winding, depending on the motor connections: The signal is fed through a Schmidttrigger for noise immunity, and through a time delay in order to guarantee that no short-circuit occurs in the output stage during phase-shift. High level on the PHASE input causes the motor current flow from MA through the winding to MB. 10 and h - The current level in the motor winding is selected with these inputs. The values of the different current levels are determined by the reference 8/13 838 voltage VR together with the value of the sensing resistor Rs. CURRENT SENSOR This part contains a current sensing resistor (Rs), a low pass filter (Re, Ce) and three comparators. Only one comparator is active at a time. It is activated by the input logic according to the current level chosen with signals 10 and h. The motor current flows through the sensing resistor Rs. When the current has increased so that the voltage across Rs becomes higher than the reference voltage on the other comparator input, the. comparator output goes high, which triggers the pulse generator and its output goes high during a fixed pulse time (toft), thus switching off the power feed to the motor winding, and causing the motor current to decrease during toff. SINGLE-PULSE GENERATOR The pulse generator is a monostable triggered on the positive going edge of the comparator output. The monostable output is high during the pu Ise time, toff, which is determined by the timing components Rtand Ct. toft = 0.69 . Pt Ct TEA3718-TEA3718S The single pulse switches off the power feed to the motor winding, causing the winding current to decrease during toff. If a new trigger signal should occur during toff, it is ignored. Vee, Vmm , VR The circuit will stand any order of turn-on or turn-off the supply voltages Vee and Vmm. Normal dV/dt values are then assumed. OUTPUT STAGE Preferably, VR should be tracking Vee during poweron and power-off if Vmm is established. The output stage contains four Darlington transistors and four diodes, connected in an H-bridge. The two sinking transistors are used to switch the power supplied to the motor winding, thus driving a constant current through the winding. The current levels can be varied continuously if VR is varied or with a circuit varying the voltage on the comparator terminal. ANALOG CONTROL It should be noted however, that it is not permitted to short circuit the outputs. POWER LOSSES Vs OUTPUT CURRENT P tot (WI / T A == + 25 0 C 4 ,J / 3 ,/ 2 -- ./ / ." ,/" "",. o 1.0 0.4 1.2 , ...., SC:;S-THOMSON ________ ._ _ _ _ __ 9/13 '], 1:ii~©IB@rn~rn©m::J@[i;I]~©® 839 TEA3718-TEA3718S ALARM OUTPUTS (TEA3718) When an alarm condition occurs part of the Vcc supply voltage (dividing bridge R - Rc) is fed to the comparators input pin. On alarm condition the comparator input voltage Vc will become higher than Vch, thus switching off the output stage. A circuit may monitor the voltage Vc to detect the action of the thermal protection (fig. A) For MW package the alarm output goes low if an alarm condition occurs (fig. B). Figure A : Alarm Detection For Oil Package. Figure B : Common Detection For Several Multiwatt Packages. o vee RI7000 typo J ---r---=:J -- ALARM Vc vee J AI ARM Us Rs t/BBTUi3?lB 131 t/U8Tifl3?IU H2 Depending of the RC value, the behaviour of the circuit is different on alarm condition: 1) RC>80n The output stage is switched off. 2) RC < 60 n (see figures C and D) The current IMM in the winding is reduced according to the approximate formula: VTH Vee Rc IMM= - - - - - Rs R+Re .- Rs with: VTH = Threshold of the comparator (VeH. VeM or Vel) R = 700 n (typical). 10/13 840 TEA3718-TEA3718S Figure C : (typical curve) Current Reduction In The Motor On Alarm Condition. Figure D : (Vrel 5V)Block Diagram For Half Current On Alarm Condition. I IIIN I Pc c e 330 22nF R5 I t188TEA3?18- 114 -----~.- Notes: 1. Resistance values given here are for the lue. Vch ---._--------------_.- threshold. They should be adjusted using other comparators threshold or other Vret va- ---------------------1 PRE-ALARM OUTPUT (TEA3718SSP) EA3718S MOTOR WINDING Vmm MA Vmm PHASE LOGIC 11 INPUTS·lo GND 4.7kf2 Re Vee Cc T B20pF ..:: ~ _ _ PRE·ALARM OUTPUT TEA3718SSP ONLY RS 2. When changing Rc Cc should be adjusted to keep the same Rc Cc value . • Pre-alarm output becomes low when junction temperature reaches 81 (81 typ = 170°C). 11/13 841 TEA3718-TEA3718S TYPICAL APPLICATION From .. -processor 12/13 842 Stepper motor .~___~~~_TEA3718- TEA3718S -I PRINCIPAL OPERATING SEQUENCE I Printing sp 'ed with Stand by with I Halfstep motor drive holding torque I im~ 500 mA Im~180mA lOA 11A I I 1.2 3 4 Full step motor drive 5,6,7 8 ___-_-_--' 11....____ Im~lA , '--........_______ ~ ___ _ Ph ------_Lr__L..r_L __ _ Ph~-----"T"'::l"""',---r....... __ u, I IOB---~ 11B---~ !-I------- I I lA---- fA - -n-- Changing phas~ this point gives Motor current PhaseA t,,,,, J _m_:________ PhaseS ~ o",,,m dow, -----: _____ lA __ - =--~illL _ - - _.1-_ lA _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I _I APPLICATION NOTES MOTOR SELECTION Some stepper motors are not designed for continuous operation at maximum current. As the circuit drives a constant current through the motor, its temperature might increase exceedingly both at low and high speed operation. Also, some stepper motors have such high core losses that they are not suited for switch mode current regulation. UNUSED INPUTS INTERFERENCE As the circuit operates with switch mode current regulation, interference generation problems might arise in some applications. A good measure might then be to decouple the circuit with a 15 nF ceramic capacitor, located near the package between power line Vmm and ground. The ground lead between Rs, Cc and circuit GND should be kept as short as possible. This applies also to the lead between the sensing resistor Rs and point S, see FUNCTIONAL BLOCKS. Unused inputs should be connected to proper voltage levels in order to get the highest noise immunity. 13/13 843 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TEF3718 TEF3718S STEPPER MOTOR DRIVER • HALF AND FULL-STEP MODES • BIPOLAR DRIVE OF STEPPER MOTOR FOR MAXIMUM MOTOR PERFORMANCE • BUILT-IN PROTECTION DIODES • WIDE RANGE OF CURRENT CONTROL: 5 TO 1500 mA • WIDE VOLTAGE RANGE: 10 TO 50 V • DESIGNED FOR UNSTABILIZED MOTOR SUPPLY VOLTAGE • CURRENT LEVELS CAN BE SELECTED IN STEPS OR VARIED CONTINUOUSLY • THERMAL OVERLOAD PROTECTION • ALARM OUTPUT' (TEF3718SP) OR PREALARM OUTPUT (TEF3718SSP) POWERDIP 12 + 2 + 2 ORDER CODE: TEF3718DP TEF3718SDP DESCRIPTION The TEF3718 and TEF3718S are bipolar monolithic integrated circuits intended to control and drive the current in one widing of a bipolar stepper motor. The circuits consists of an LS-TLL - compatible logic input, a current sensor, a monostable and an output stage with built-in protection diodes. Two TEF3718 or TEF3718S and a few external components form a complete control and drive unit for LS-TTL or microprocessor controlled stepper motor systems. MULTIWATT 15 ORDER CODE : TEF3718SP TEF3718SSP PIN CONNECTON TEF3718 1 2 3 4 5 - Vee 1 2 3 4 5 - Ii - Ph -10 -C 6 -Vref 7 -ALARM OUT 8 -GND 9 -NC 10-Vmm ll-T 12-MA 13 - E 14-MB 15-Vmm September 1988 TEF3718 TEF3718S TEF3718S 1 J 5 1 • 11 IJ IS - Vee - Ii - Ph -10 -C 6 - Vref 7 - PRE-ALARM OUT 8 -GND 9 -NC 10-Vmm ll-T 12-MA 13-E 14-MB 15-Vmm MB Mil. GND vmm GND GND II Ph '0 1/5 845 TEF3718-TEF3718S BLOCK DIAGRAM (TEF3718) Vmm MA MB Vmm PHASE I, 10 ;::z:;-+--+t4t--1-r--h C E T CaMP. INPUT AND ALARM OUT Al. OUT TEF 3718 SPONLV BLOCK DIAGRAM (TEF3718S) Vmm MA MB PHASE I, ~r--+----~-t~fy-t. 10 GNO C 2/5 846 T E PRE·ALARM OUPUl TEF3718SSP ONLY TEF3718-TEF3718S ABSOLUTE MAXIMUM RATINGS Symbol Vcc VMM Parameter Value II V ---- ~~--- VI Unit 7 50 Supply Voltage Input Voltage: Logic Inputs Analog Inputs Reference Input --- ~---- V 6 Vcc 15 Input Current: Logic Inputs Analog Inputs mA 10 10 10 Output Current ± 1.5 A Ti Junction Temperature + 150 C Operating Ambient Temperature Range - 40 to + 85 °C Storage Temperature Range - 55 to 150 °C Value Unit POWERDIP MULTIW 11 °C/W POWERDIP MULTIW 45 (*) 40 Toper T 5tg THERMAL CHARACTERISTICS Symbol RthU ·C ) RthU-a) Parameter Maximum Junction-case Thermal Resistance 3 Maximum Junction-ambient Thermal Resistance n Soldered on a 35 ~m thick 20 cm 2 °C/W PC board cooper area. RECOMMENDED OPERATING CONDITIONS Symbol Vee V MM 1m Tamb Parameter Min. Typ. Max. Unit 4.75 10 5 V - 5.25 45 Output Current 0.020 - Ambient Temperature - 40 - Supply Voltage tr Rise Time Logic Inputs - tf Fall Time Logic Inputs - - i 1.2 A 85 °C 2 fls 2 fls 3/5 847 TEF3718-TEF3718S ELECTRICAL CHARACTERISTICS ± 5 %. V MM = -10 V to + 45 V. Tamb Vee = 5 V Symbol Min. Icc Supply Current V IH High Level Input Voltage Logic Input Vil Low Level Input Voltage Input IIH High Level Input Current Logic Input (VI = 2.4 V) III Low Level Input Current Logic Input (VI = 0.4 V ) Comparator Treshold Voltage (VR = + 5 V) Ico Comparator Input Current loff Output Leakage Current (10 1, 11 = 1) V sat Total Saturation Voltage Drop (1m = 1 A,) Ptot Total Power Dissipation (1m = 1 A, fs = 30 kHz) td Vsat _Iref V sat ------- 10=01, =0 10 = 1 1, = 0 10 = 01 , = 1 - , Vsat Vf 4/5 848 230 65 420 250 80 mA 0.7 V 20 ~A 440 270 90 mV ~s) 25 20 ~A ~A 2.9 3.3 V 3.1 3.6 W 30 35 Alarm Output Saturation Voltage 10 = 2 mA 0.8 Reference Input Current, VR = 5 V 0.4 .. _ - - - _ . - ~A 100 - 20 -----_._-----1--------1--- V 1 mA mA 1m =0.5 A 1m = 1 A 1.35 1.75 POWERDIP Im=0.5A 1m = 1 A 1.25 1.55 I Diode Forward Voltage If = 0.5 A If = 1 A Substrate Leakage Current If = 1 A Sink Diode Transistor Pair MULTIWATT 1m =0.5 A 1m = 1 A 1.35 1.55 POWERDIP 1m = 0.5 A 1m = 1 A 1.25 1.35 If = 0.5 A If = 1 A 1.5 1.8 Saturation Voltage Diode Forward Voltage ~s I1S MULTIWATT Vf Isub c-f9: -I 1.6 Saturation Voltage Unit 25 -- Turn off Delay (see figures 1 and 2, T amb =+ 25 'C dVC/dt,; 50 mV/~s) Source Diode Transistor Pair Max. V POWERDIP MULTIWATT Cult off Time (see figures 1 and 2 V mm = + 10 V, Vton ,; 5 - Typ. 2 VCH VCM VCl toff 'C (Unless otherwise specified) = - 40 C to + 85 Characteristics 1.5 1.7 10 TEF3718-TEF3718S 5.0 Ptot (WI \ \ 4.0 3.0 \ I\.. \ I\.. 45°CIW (POWERDIP) '10- "" 2.0 I-- ~ - "\ 1.0 f- MULTIWATT WITH 10°CIW HEATSINK 1\ "\. \ 0 o 50 100 N 150 Tamb"C Figure 2. Figure 1. MotOf lNiOOtng -------. - MA " MB VMA-VMB or VUB-VUA v"..,.. Rs vee = 1 n inductance free Rc=470n Cc = 820 pF ceramic GND Rt =56kn Ct = 820 pF ceramic P = 500n '0 R2 = r~ 1K :: l--[1------0i · 5/5 849 TL7700A Series SUPPLY VOLTAGE SUPERVISORS • POWER-ON RESET GENERATOR • AUTOMATIC RESET GENERATION AFTER VOLTAGE DROP • WIDE SUPPLY VOLTAGE RANGE ... 3 V TO 18 V • PRECISION VOLTAGE SENSOR • TEMPERATURE-COMPENSATED VOLTAGE REFERENCE • TRUE AND COMPLEMENT RESET OUTPUTS • EXTERNALLY ADJUSTABLE PULSE WIDTH DESCRIPTION The TL7700A series are monolithic integrated circuit supply voltage supervisors specifically designed for. use as reset controllers in microcomputer and microprocessor systems. During power-up the device tests the supply voltage and keeps the RESET and RESET outputs active (high and low, respectively) as long as the supply voltage has not reached its nominal voltage value. Taking RESIN low has the same effect. To ensure that the microcomputer system has reset, the TL7700A then initiates an internal time delay that delays the return of the reset outputs to their inactive states. Since the time delay for most microcomputers and microproces- sors is in the order of several machine cycles, the device internal time delay is determined by an external time delay is determined by an external capacitor connected to the CT input (pin 3). td = 1.3 x 104 X CT Where: CT is in farads (F) and td in seconds (s). In addition, when the supply voltage drops below the nominal value, the outputs will be active until the supply voltage returns to the nominal value. An external capacitor (typically 0.1 flF) must be connected to the REF output (pin 1) to reduce the influence of fast transients in the supply Voltage. The TL7700AI series is characterized for operation from - 25°C to 85°C; the TL7700AC series is characterized from O°C to 70°C. Plastic Minidip 50-8 J BLOCK DIAGRAM Cr SENSE 7 INPUT ~ ~--r-------4---~----~ '--------------+--------I--'---REf GNO !;'-B031 *( See Note A) TL7702A R1 = OQ, R2= open; TL7705A R1 = 7.8 Kn, R2 = 10 Kn ;TL7709A R1 = 19.7KQ, R2 = 10 Kil ;TL7712A R1 =32.7KQ, R2 = 10 KQ; TL7715A R1 = 43.4 KQ, R2 = 10 KQ. September 1988 1/5 851 TL 7700A-Series ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit 20 V Vs Supply Voltage. Vee (see note 1) Vi Input Voltage Range at RESIN Vi Input Voltage at SENSE: 10H High-level Output Current at RESET - 30 mA 10L Low-level Output Current at RESET 30 mA - 25 to 85 o to 70 °C °C - 65 to 150 °C Tamb T stg Noles: TL7702A (see note 2) TL7705A TL7709A TL7712A TL7715A Operating Free-air Temperature Range: TL77XXAI TL77XXAC Storage Temperature Range - 0.3 to 20 V - V V V V V 0.3 to 6 0.3 to 10 0.3 to 15 0.3 to 20 0.3 to 20 1. All voltage values are wilt1 respect to lt1e network ground terminal. 2. For lt1e TL7700A. the voltage applied to the SENSE terminal must never exceed Vs. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Vs Supply Voltage V,H High-level Input Voltage at RESIN V,L Low-level Input Voltage at RESIN Vi Min. Max. Unit 3.6 18 V 2 V 0.6 Voltage at Sense Input TL7702A 0 TL7705A 0 10 TL7709A 0 15 TL7712A 0 20 TL7715A 0 V See Note 3 V 20 10H High-level Output Current at RESET -16 mA 10L Low-I.evel Output Current at RESE;T 16 mA Tamb Nole : Operating Free-air Temperature Range TL77 - AI - 25 85 °C 70 TL77 - AC 0 3. For proper operanon of the TL7702A. the voltage applied to lt1e SENSE terrmnal should not exceed Vs - 1 V or 6 V. whichever IS less. CONNECTION DIAGRAM AND ORDER CODE Temperature Range "\...r-REf RE51N 8 GND 4 o to 70°C 5EN5E I NPU"{ 2 CT Commercial V5 6 RE5ET & RE5ET Industrial - 40 to 85°C S 8040 2/5 852 ~ ~'" SGS-ntOMSON Il!lll©l!l@lrnil.£ii"liIlOOlllC$ Plastic Minidip SO-8 TL77XXACP TL77XXACD TL77XXAIP TL77XXAID TL 7700A-Series THERMAL DATA Thermal Resistance Junction-ambient Max. 120 ELECTRICAL CHARACTERISTICS these specifications unless otherwise specified, apply for: Tamb = - 25 to 85 'C (TLXXAI) ; T amb = 0 to 70 'C (TL77XXAC) Symbol Parameter Test Conditions (1) VO H High-level Output Voltage at RESET VOL Low-Level Output Voltage at RESET IOL~16mA Vret Reference Voltage T amb ~ 25 'C VT Threshold Voltage at SENSE Input VT+,VT- Hysteresis (2) at SENSE Input mA TL7705A TL7712A Threshold Voltage at SENSE Input ~-16 TL7702A TL7709A VT IOH Vs ~ 3.6 V to 18 V T amb ~ 25°C V 2.53 2.58 2.48 2.53 2.58 4.5 4.55 4.6 7.5 7.6 7.7 10.6 10.8 11.0 13.5 13.8 2.58 TL7705A 4.45 4.55 4.6 TL7709A 7.4 7.6 7.7 TL7712A 10.4 10.8 11.0 TL7715A 13.0 13.5 13.8 ~ 3.6 V to 18 V TL7702A TL7705A V 15 Vs ~ 3.6 V to 18 V T amb ~ 25°C 20 mV 35 45 Vi~2.4VtoVs TL7702A V 10 VI ~ 20 - 100 0.4 V Vee! < V, < Vs -1.5 V IOH High-level Output Current at RESET Vo ~ 18 V IOL Low-level Output Current at RESET Vo ~ 0V Supply Current All Inputs and out. open Is V 2.48 2.53 TL7715A Notes: V 13.2 Vs Unit 0.4 2.45 Input Current at RESIN Input Input Current at SENSE Input Max. TL7715A TL7712A II Typ. TL7702A TL7709A II Min. Vs-l.5 0.5 2 IlA 50 - 50 1.8 3.3 mA 1. All characteristics are measured with C = 0.1 ~F from Pin 1 to GND, and with C = 0.1 ~F from Pin 3 to GND. 2. Hysteresis is the difference between the positive going input threshold Voltage. VT" and the negative going input threshold voltage, VT_. 3/5 853 TL 7700A-Series SWITCHING CHARACTERISTICS Symbol Parameter Test Conditions Min. Vih = Vityp + 0.04 x Vi ViL = Vityp - 0.04 x Vi 0.9 Pulse Width at Output CI =0.1 IlF 0.65 tpdHL Propagation Delay Time from RESIN to RESET tr/l Rise/Falitime at RESET and RESET tpi Pulse Width at SENSE Input tpi Pulse Width at RESIN Input tpo Typ. 0.4 2.6 Ils ms CL=100pF Vs =5 V RL =4.7 KQ 1 Ils CL=10pF RL =4.7 KQ 1 Ils 1.3 Vs=5 V + 5V 0----.._---, 22Kll. Vs SENSE 2 RESIN SENSE RESET 1-"----,p--<~---'2'-iRESIN TL7712 RESET SYSTEM RESET Tl7705 O.1,.,F OV SENSE RESIN RESET~5~----J Tl7712 -12V o----<~----<~----' 4/5 854 Unit Ils Figure 1 : Multiple Power Supply System Reset Generation. +12V Max. Gi SGS-ntOMSON ~I iIIilD!:Dl©~I!.I + + u u > E88TS271-03 3/10 859 TS271 OFFSET VOLTAGE NULL CIRCUIT RESISTOR BIASING \Icc 25kl! Vee E88TS27H)4 E88TS271·05 OFFSET COMPENSATION GUARANTEED FOR TS271 SCX (Iset > 25 flA), TS271 ACX (Iset > 90 flA) Rset CONNECTED TO GROUND RsetCONNECTED TO Vcc(Rset VALUE: SEE FIG. 1) Figure 1 : Rset Connected to Vee. 1\ 10MU I' "I~ lMH vce.· = 5V VCC-: - 5V " "- I\. , lOOkU "- ~ lOkU O.lpA lpA lOpA 1DOW' E88TS271·06 4/10 860 TS271 ELECTRICAL CHARACTERISTICS Tamb = 25 °C, Vee = 10 V, Iset = 1.51JA (unless otherwise specified) RL Connected to Vee Symbol Via Parameter Min. TS271C Typ. Max. Input Offset Voltage Vo=1.4V TS271 T min < T < T max TS271A TS271B T min < T < T max VIO 1'0 Ib VDH AVd G wr CMR SVR Icc Is Is (Sink) Svo om Kov Vn Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Va = 5 V T min < T < T max Input Bias Current V, =5 V, Va = 5 V T min < T < T max High Output Voltage (note 1) Vi = 10 mV RL = 1 mQ T min < T < T max Large Signal Voltage Gain Va = 1 V to 6 V Vi =5 V RL = 1 mQ T min < T < T max Gain Bandwidth Product Av = 40 dB RL = 1 MQ CL =100pF fin = 10 KHz Common-mode Rejection Ratio Vo=1.4V Vi = 1 V to 7.4 V Supply Voltage Rejection Ratio Vcc = 5 V to 10 V Vo=1.4V Supply Current (per amplifier) Av = 1, no Load Va = 5 V, Vi = 5 V T min < T < T max Output Current Vi=10mV,Vo=OV Output Current Vi =-10 mY, Va =Vcc Slew Rate at Unity Gain Phase Margin at Unity Gain Av = 40 dB RL = 1 MQ CL = 10 pF CL =100pF Overshoot Factor CL = 10 pF CL=100pF Input Equivalent Noise Voltage F = 1 KHz Rs = 10 Q Unit mV 10 12 5 6.5 2 3.5 T min < T < T max a TS2711, TS271 M Min. Typ. Max. 10 12 5 6.5 2 3.5 0.7 0.7 f.tV/°C pA 1 1 100 200 pA 1 1 150 300 V 8.8 8.8 9 8.7 9 8.6 V/mV 30 30 100 100 20 20 MHz 0.1 0.1 dB 60 80 60 80 60 80 60 80 dB 10 15 10 17 15 !-LA 18 mA 45 60 85 45 60 85 35 45 0.04 65 35 45 0.04 65 mA 35 10 35 10 40 70 70 40 70 70 V/llS Degrees % nV/..JHz Note: 1. Low output voltage is less than 50mV. 5/10 861 TS271 ELECTRICAL CHARACTERISTICS Tamb = 25°C, Vee = 10 V, Iset = 25 RL Connected to Vee Symbol V,O a V,O liO Ib VOH AVd J.IA (unless otherwise specified) Parameter Input Offset Voltage Vo=1.4V TS271 T min < T < T max TS271A T min < T < T max TS271B T min < T < T max Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Vo = 5 V T min < T < T max Input Bias Current Vi =5 V, Vo =5 V T min < T < T max High Output Voltage (note 1) Vi = 10 mV RL = 100KQ T min < T < T max Large Signal Voltage Gain Vo = 1 V to 6 V Vi = 5 V RL = 100 KQ T min < T < T max Gain Bandwidth Product Av = 40 dB RL=100KQ CL = 100 pF fin = 100 KHz Common-mode Rejection Ratio CMR Vo=1.4V Vi = 1 V to 7.4 V SVR Supply Voltage Rejection Ratio Vcc = 5 V to 10 V Vo=1.4V Supply Current (per amplifier) Icc Av = 1, no Load Vo = 5 V , Vi =5 V T min < T < T max Output Current Is V i =10mV,V o =OV Output Current Is (Sink) Vi =-10 mV, Vo =Vcc Slew Rate at Unity Gain Svo Phase Margin at Unity Gain om Av = 40 dB RL = 100 KQ C L = 10 pF CL = 100pF Overshoot Factor Kov CL = 10 pF CL = 100 pF Input Equivalent Noise Voltage Vn F = 1 KHz Rs =10 Q Note: 1. Low output voltage is less than 50mV. Min. TS271C Max. Typ. TS2711, TS271 M Min. Typ. Max. mV 10 12 5 6.5 2 3.5 10 12 5 6.5 2 3.5 flV/oC pA 2 2 1 1 100 200 pA 1 1 150 300 V 8.7 8.7 8.9 8.9 8.5 8.6 V/mV 30 50 30 20 50 10 MHz G wc 6/10 862 Unit 0.7 0.7 dB 60 80 60 80 60 80 60 80 dB flA 150 200 150 250 200 300 mA 45 60 85 45 60 85 35 45 0.6 65 35 45 0.6 65 mA 50 30 50 30 30 50 38 30 50 38 V/flS Degrees % nVdHz TS271 ELECTRICAL CHARACTERISTICS Tamb = 25°C, Vcc = 10 V, Iset = 130 J..lA (unless otherwise specified) RL Connected to Vcc Symbol Vio Parameter Input Offset Voltage Vo=1.4V TS271 T min < T < T max TS271A T min < < T max TS271B T min < T < T max Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Vo = 5 V T min < T < T max Input Bias Current Vi =5 V, Vo = 5 V T min < T < T max High Output Voltage (note 1) V, = 10 mV RL = 10 KQ T min < T < T max Large Signal Voltage Gain Vo = 1 V to 6 V Vi =5 V RL = 10 KQ T min < T < T max Gain Bandwidth Product Av = 40 dB RL = 10 KQ C L =100pF fin = 200 KHz Common·mode Rejection Ratio Vo=1.4V Vi = 1 V to 7.4 V Supply Voltage Rejection Ratio Vcc=5Vt010V Vo=1.4V Supply Current (per amplifier) Av = 1, no Load Vo = 5 V , Vi =5 V T min < T < T max Output Current V, = 10 mY, Vo = 0 V Min. TS271 C Typ. Max. VIO lio Ib VOH AVd G wr CMR SVR Icc Is Is (Sink) Svo 0m Kav Vn Output Current Vi =. 10 mY, Vo =Vcc Slew Rate at Unity Gain Phase Margin at Unity Gain Av = 40 dB RL = 10 KQ C L = 10 pF C L = 100 pF Overshoot Factor C L = 10 pF C L = 100 pF Input Equivalent Noise Voltage F =1 KHz Rs = 10 Q Unit mV 10 12 5 6.5 2 3.5 1 a TS2711, TS271 M Min. Typ. Max. 10 12 5 6.5 2 3.5 5 5 1 1 IlV/ o C pA 100 200 pA 1 1 150 300 V 8.2 8.4 8.2 8.1 8.4 8 V/mV 10 10 15 7 15 6 MHz 2.3 2.3 dB 60 80 60 80 60 70 60 70 dB 800 1300 800 1400 1300 IlA 1500 mA 45 60 85 45 60 85 35 45 4.5 65 35 45 4.5 65 mA 56 56 56 56 30 30 30 30 30 30 V/IlS Degrees % nV/.JHz Note: 1. Low output voltage is less than 50mV. 7/10 863 TS271 GAIN (dB) sot--_ Ise! = 130 f.lA 10K OPEN LOOP FREQUENCY RESPONSE AND PHASlo SHIFT VCC±5V,RL=10K!l,CL=I00pF, Tamb~ 25°C E88TS271-07 PHASE GAIN IdB) o so 45 r-. r-- r-. 40 30 ""--- r-. 20 Ise! = 25 f.lA 90 ....... 10 135 lBO i'.. " o -10 -20 FREQUENCY (Hz) lK lOOK 10K 1M OPEN LOOP FREQUENCY RESPONSE AND PHASE SHIFT VCC ± 5 V, RL = 100 GAIN (dB) 40 ~ 30 = 1.5 f.lA E88TS271-08 PHASE I so J-..... Ise! Kll, Cl = 100 pF. Tamb = 25°C 45 r--1-,... 90 """" r-. J-...... 20 o 10 o 135 180 '" "'-" -10 i -20 lK 10K "- I' lOOK ( r- " FREQUENCY (Hz) 1M OPEN lOOP FREQUENCY RESPONSE AND PHASE SHIFT VCC ± 5 V, Rl = 1 Mu' Cl ~ 100 pF, T am b=250C 8/10 864 E88TS271-QS T8271 ORDER CODES Part Number TS271C TS271AC TS271BC TS2711 TS271M TS271AI TS271AM TS271 BI TS271 BM Temperature Range °C Package N D • • o to o to o to - 40 55 40 55 40 55 + 70 + 70 + 70 to + 105 to + 125 to + 105 to + 125 to + 105 to + 125 • • • • • • • • • • J • • • Examples: TS271 ACN, TS271 CD PACKAGE MECHANICAL DATA 8 PINS - PLASTIC DIP OR CERDIP O.51mm ~ '-----r-----Llf _t \-i (1) Nominal dimension (2) True geometrical position 8 pins 9/10 865 TS271 PACKAGE MECHANICAL DATA (continued) 8 PINS - PLASTIC MICROPACKAGE SO 0,185 0,265 1,75 max.. 8 Outputs 10/10 866 TS272 TS27M2/TS27L2 CMOS DUAL OPERATIONAL AMPLIFIERS • EXCELLENT PHASE MARGIN ON CAPACITANCELOADS • SYMMETRICAL OUTPUT CURRENTS • HIGH GAIN BANDWIDTH PRODUCT FOR TS272 • LOW OUTPUT DYNAMIC IMPEDANCE N DIP8 (Plastic package) • THE TRANSFER FUNCTION IS LINEAR • PIN COMPATIBLE TO STANDARD DUAL OPERATIONAL AMPLIFIERS (TL082 - LM358) J CERDIP8 (Cerdip package) • STABLE AND LOW OFFSET VOLTAGE • INTERNAL ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS • THREE INPUT OFFSET VOLTAGE SELECTIONS : STANDARD (10 mV), A (5 mV), B(2mV) D 508 (Plastic micropackage) (Order Codes at the end of the Data sheet) DESCRIPTION The TS272 series are low cost, low power dual operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the SGS THOMSON Microelectronics silicon gate I,.IN MOS process giving them an excellent consumption speed ratio. These series are ideally suited for low consumption applications. Three power consumptions are available allowing to have always the best consumption-speed ratio. • Icc = 10 f.LA per amplifier: TS27L2 (Low bias versions) • Icc = 150 f.LA per amplifier: TS27M2 (Medium bias versions) • Icc = 1 rnA per amplifier: TS272 (High bias versions) The input impedance is similar to the J-FET input impedance. Very high input impedance and extremely low input offset and bias currents. They allow to minimize the static errors in low impedance applications. November 1988 PIN CONNECTIONS (top view) 8 2 7 3 6 4 5 E88TS272·01 12345678- Output 1 Inverting input 1 Non-inverting input 1 VccNon-inverting input 2 Inverting input 2 Output 2 Vce+ 1/10 867 TS2721TS27M2/TS27 L2 BLOCK DIAGRAM Vee + source xl InPut differential <;tage Output E88TS272-02 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Supply Voltage (note 1) Vid Differential Input Voltage (note 2) Vi Input Voltage (note 3) Toper Unit 12 V ±12 V - 0.3 to 12 Operating Free-air Temperature V °C TS272C TS2721 TS272M TS27M2C TS27M21 TS27M2M TS27L2C TS27L21 TS27L2M T. 'g Value o to 70 -40t0105 -5510125 01070 - 4010105 -5510125 o to 70 - 40to 105 - 55 to 125 - 65 to 150 Storage Temperalure ac Notes: 1. All voltage values, except differential voltages, are wtth respect to network ground terminal. 2. Differential voltages are at the non-inverting input terminal respect to the terminal. 3. The magnttude of the input voltage must never exceed the magnitude of the positive supply voltage. OPTIMAL OPERATING CONDITIONS Symbol Vee Vi Value Unit Supply Voltage (note 1) Parameter 4 to 10 V Common Mode Input Vollage Vee = 10 V 0109 V ------------- L", ~~~;~:r~~'= 2110 868 TS272/TS27M2/TS27L2 SCHEMATIC DIAGRAM (For 1/2 TS27x2) ...... co l- I- ~ + l! u + u u > ..... '" l- OJ '" t- I~ .!: ES8TS272-03 3110 869 TS272/TS27M2/TS27l2 ELECTRICAL CHARACTERISTICS FOR TS272 Tamb = 25 °C, Vee = 10 V (unless otherwise specified) RL Connected to Vee Symbol Vio a Vio lio lIB VDH AVd G wr CMR SVR Icc Is Is (sink) Svo om Kov Vn Vo 1 N 02 Parameter Input Offset Voltage Vo=1.4V TS272 T min < T < T max TS272A T min < T < T max TS272B T min < T < T max Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Vo = 5 V T min< T < T max Input Bias Current Vi =5 V, Vo = 5 V T min < T < T max High Output Voltage (note 1) Vi = 10 mV RL = 10 kQ T min < T < T max Large Signal Voltage Gain Vo = 1 V to 6 V Vi =5 V RL = 10 KQ T min < T < T max Gain Bandwidth Product Av = 40 dB RL = 10 kQ CL = 100 pF Fin = 200 KHz Common Mode Rejection Ratio Vo=1.4V V i = 1 V to 7.4 V Supply Voltage Rejection Ratio Vec =5 Vto 10 V Vo=1.4V Supply Current (per amplifier) Av = 1, no Load Va =5 V T min < T < T max Output Current Vi = 10 mV, Va =0 V Output Current Vi =- 10 mV, Va = Vce Slew Rate at Unity Gain Phase Margin at Unity Gain Av = 40dB RL = 10 kQ CL = 100 pF Overshoot Factor Input Equivalent Noise Voltage f = 1 KHz Rs = 10 Q Cross Talk Attenuation Note: 1. Low ou1pu1 voltage is less than 50mV. 4/10 870 Min. TS272C Typ. Max. TS2721/TS272M Min. Typ. Max. Unit mV 10 12 5 6.5 2 3.5 10 12 5 6.5 2 3.5 flV /o C 5 5 1 0.2 pA nA 0.3 pA nA 1 0.1 1 1 0.15 V 8.2 8.4 8.2 8.1 8.4 8 V/mV 10 15 10 15 6 7 MHz 3.5 65 60 3.5 80 65 80 dB 70 60 70 dB 1000 1500 1000 1600 1500 flA 1700 mA 45 60 85 45 60 85 35 45 5.5 65 35 45 5.5 65 mA V/flS Degrees 45 45 30 30 30 30 nV/..JHz 120 120 dB % TS272/TS27M2/TS27L2 ELECTRICAL CHARACTERISTICS FOR TS27M2 Tamb = 25 DC, VCC = 10 V (unless otherwise specified) RL Connected to Vcc Symbol Via 0'. Via liD 118 V OH AVd G wr CMR SVR Icc Is Is (sink) Sva em Kov Vn Vo 1 No 2 Parameter Input Offset Voltage Va=1.4V TS27M2 T min- < T < T max TS27M2A T min < T < T max TS27M2B T min < T < T max Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Va = 5 V T min < T < T max Input Bias Current Vi =5 V, Va = 5 V T min < T < T max High Output Voltage (note 1) Vi = 10 mV RL = 100 kn T min < T < T max Large Signal Voltage Gain Va = 1 V to 6 V RL = 100 kn Vi =5 V T min < T < T max Gain Bandwidth Product Av= 40dB RL = 100 kn CL=100pF Fin = 100 KHz Common-mode Rejection Ratio Va=1.4V Vi = 1 V to 7.4 V Supply Voltage Rejection Ratio Vcc=5Vt010V Va=1.4V Supply Current (per amplifier) Av = 1, no Load Va = 5 V T min < T < T max Output Current Vi = 10 mV, Va = 0 V Output Current Vi = - 10 mV, Va = V cc Slew Rate at Unity Gain Phase Margin at Unity Gain Av = 40 dB RL =100kn CL = 100 pF Overshoot Factor Input Equivalent Noise Voltage f = 1 KHz Rs = 10 n Cross Talk Attenuation Min. TS27M2C Typ. Max. TS27M21/TS27M2M Min. Typ. Max. Unit mV 10 12 5 6.5 2 3.5 10 12 5 6.5 2 3.5 2 2 1 I1V/ C D 0.2 pA nA 0.3 pA nA 1 0.1 1 1 0.15 V 8.7 8.9 8.7 8.9 8.5 8.6 V/mV 30 50 30 50 10 20 MHz 1 1 65 80 65 80 dB 60 80 60 80 dB 150 200 150 250 200 I1A 300 mA 45 60 85 45 60 85 35 45 0.6 65 35 45 0.6 65 mA V/I1S Degrees 45 45 30 38 30 38 nVf\lHz 120 120 dB % Note: 1. Low outpul voltage is less than 50mV. 5/10 871 TS272/TS27M2ITS27l2 ELECTRICAL CHARACTERISTICS FOR TS27L2 Tamb = 25 DC, VCC = 10 V (unless otherwise specified) RL Connected to V cc - Symbol Via Parameter Min. TS27L2C Typ. Max. lio 5 6.5 2 3.5 Temperature Coefficient of Input Voltage Input Offset Current Vi =5 V, Vo = 5 V 2 3.5 0.7 1 0.1 0.2 1 1 0.3 0.15 T min < T < T max !lV/DC 0.7 1 Input Bias Current Vi = 5 V, Vo = 5 V High Output Voltage (note 1) Vi = 10 mV RL = 1 MQ T min < T < T max Large Signal Voltage Gain AVd Vo = 1 V to 6 V RL = 1 MQ Vi =5 V T min < T < T max Gain Bandwidth Product G wr Av = 40 dB 1 MQ RL = CL = 100 pF Fin = 100 KHz CMR Common Mode Rejection Ratio Vo=1.4V Vi = 1 V to 7.4 V SVR Supply Voltage Rejection Ratio Vcc =5 Vto 10 V Vo=1.4V Supply Current (per amplifier) Icc Av = 1, no Load Vo = 5 V T min < T < T max Output Current Is Vi=10mV,Vo =OV Output Current Is (Sink) Vi =-10 mV, Vo =Vcc Slew Rate at Unity Gain Svo 0m Phase Margin at Unity Gain Av = 40dB '. RL = 1 MQ C L = 100 pF Overshoot Factor Kov Input Equivalent Noise Voltage Vn f = 1 KHz Rs = 10 Q V0 1 /V02 Cross Talk Attenuation 10 12 5 6.5 10 12 T min < T < T max 118 VDH Note: 1. Low output voltage is less than 50mV. 6/10 872 Unit mV Input Offset Voltage Vo=1.4V TS27L2 T min < T < T max TS27L2A T min < T < T max TS27L2B T min < T < T max a Vio TS27L21ITS27L2M Min. Typ. Max. 8.8 8.8 9 8.7 pA nA pA nA V 9 8.6 V/mV 60 100 60 45 100 40 MHz 0.1 0.1 65 80 65 80 dB 60 80 60 80 dB 10 15 10 15 IlA 18 17 mA 45 60 85 45 60 85 35 45 0.04 65 35 45 0.04 65 mA V/!lS Degrees 45 45 30 70 30 70 nV/~Hz 120 120 dB % TS272/TS27M2/TS27L2 ICC (IIA) I I I HIGH-BIAS VERSIONS 1000 ,"r I ----- I MEDIUM-BIAS VERSIONS -- .' 100 LOW-BIAS VERSIONS ·10 /'- - -_ ..- ...- 10 12 14 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Vo = V,e = 0.2 Vee, T amb= 25 "C, NO LOAD 16 EB8TS272-04 ICC (IIA) I I I HIGH-BIAS VERSIONS j 1000 I I I MEDIUM-BIAS VERSIONS 100 LOW-BIAS VERSIONS 10 ,. -50 -25 25 50 75 100 125 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Vcc= 10V, V'c =5 V, Vo= 5 V, NO LOAD E88TS272-05 7/10 873 TS272/TS27M2/TS27 L2 GAIN(IIBI 100 T" PHASE r"-r-. eo 60 1 I 'j [[[[1"[ , !!!!!!!! ,. , ~~HASE SHIFT 'tltl scale) r"-r-. GAIN Uellscalel 40 45 !'.~ 90 !'." TS272 135 '1' t- 180 20 10 100 1.000 10.000 100.000 1.000.000 10.000.000 FREQUENCY 1Hz! OPEN LOOP FREOUENCY RESPONSE AND PHASE SHIFT E88T8272·06 Vee = 10V, RL;;; 10kn£L= 100pF. T.m&= 25°C GAIN(dBI 100 ~ ilASl " r-. 80 ~~ 1""- ''' 60 GAIN IIlJltsee ','I ..... r-. f- TS27M2 111111 111111111 II PIiASt SHIf ;'t'r'JYhlllCilllt:' '" 90 f' 20 135 18. 10 100 1.000 10.000 100.000 1.000.000 Fft£QUENCY IH.lI OPEN LOOP FREQUENCY RESPONSE AND PHASE SHIFT Vee =1DV, RL "'DDkn,eL = 100pF, Tamb =:!!i·e E88T8272-1J7 GAIN IdB) PHASE 1'1' 80 60 11111 I~ , GAIN Iteftsc~11J1 40 TS27L2 1111mlii 111"(ugh J(:alel 1"'- ... !""PHASE SHIFT 45 ' 'r-. 1'" 20 f' 135 18. 20 I. TOO 1.000 10.000 .100.000 FREQUENCY (Hz I OPEN LOOP FREOUENCY RESPONSE AND PHASE SHIFT Vee =10V. RL = 1MD.CL =100pF. T.mb= 25°C 8/10 874 E88TS272-08 TS272/TS27M2/TS27L2 ORDER CODES Part Number TS272C TS272AC TS272BC TS2721 TS272M TS27M2C TS27M2AC TS27M2BC TS27M21 TS27M2M TS27L2C TS27L2AC TS27L2BC TS27M21 TS27L2M TS272AI TS272BI TS272AM TS272BM TS27M2AI TS27M2BI TS27L2AI TS27L2BI TS27M2AM TS27M2BM TS27L2AM TS27L2BM Temperature Range °C o to 70 o to 70 o to 70 - 40 to 105 - 55 to 125 o to 70 o to 70 o to 70 - 40 to 105 - 55 to 125 o to 70 o to 70 o to 70 - 40 to 105 - 55 to 125 - 40 to 105 -40t0105 - 55 to 125 - 55 to 125 - 40 to 105 - 40 to 105 - 40 to 105 - 40 to 105 - 55 to 125 - 55 to 125 - 55 to 125 - 55 to 125 Package N • • • • • • • • • • • • • 0 J • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Examples : TS27L2ACN, TS272CD PACKAGE MECHANICAL DATA 8 PINS - PLASTIC DIP OR CERDIP (11 Nominal dimension (2) True geometrical position 8 pins 9/10 875 TS272/TS27M2/TS27L2 PACKAGE MECHANICAL DATA (continued) 8 PINS - PLASTIC MICROPACKAGE SO .-1.27 o _I 0.185 0.265 e 0.35 0.45 tum 1.75 mall. 8 Outputs 10/10 ------------- 876 ~ SCiS ......_ .... ·"/Ililo©oo~~ TS274 TS27M4/TS27L4 CMOS QUAD OPERATIONAL AMPLIFIERS • EXCELLENT PHASE MARGIN ON CAPACITIVE LOADS • -SYMMETRICAL OUTPUT CURRENTS • HIGH GAIN BANDWIDTH PRODUCT FOR TS274 • LOW OUTPUT DYNAMIC IMPEDANCE N • THE TRANSFER FUNCTION IS LINEAR DIP14 (Plastic Package) • PIN COMPATIBLE TO STANDARD QUAD OPERATIONAL AMPLIFIERS (TL084-LM324) J CERDIP14 • STABLE AND LOW OFFSET VOLTAGE (Cerdip Package) • INTERNAL E1.ECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITS • THREE INPUT OFFSET VOLTAGE SELECTIONS: STANDARD (10 mV), A (5 mV), B(2mV) D 5014 (Plastic Micropackage) (Order Codes at the end of the datasheet) PIN CONNECTIONS (top view) DESCRIPTION. The TS274 series are low cost, low power quad operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the SGS-THOMSON Microelectronics silicon gate LIN MOS process giving them an excellent consumption-speed ratio_ These series are ideally suited for low consumption applications. Three power consumptions are available allowing to have always the best consumption-speed ratio. • Icc = 10 ~ per amplifier: TS27L4 (Low bias versions) • Icc = 15011A per amplifier: TS27M4 (Medium bias versions) • Icc = 1 rnA per amplifier: TS274 (High bias ver~ions) The input impedance is similar to the J-FET input impedance: very high input inpedance and extremely low input offset and bias currents. They allow to minimize the static errors in low impedance applications. November 1988 14 2 13 3 12 4 11 5 10 6 9 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - Output 1 E88TS274-01 Inverting input 1 Non-inverting input t Vce+ Nan-inverting input 2 Inverting. input 2 Output2 Output 3 Inverting input 3 Non-inverting input 3 VccNon-inverting input 4 Inverting input 4 Output 4 1/10 an TS27 4/TS27M4/TS27 L4 BLOCK DIAGRAM E88TS272-02 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vee Supply Voltage (note 1) Vid Differential Input Voltage (note 2) Vi Input Voltage (note 3) Toper T stg 2. 3. Unit 12 V ± 12 V - 0.3 to 12 Operating Free-air Temperature V °C TS274C TS2741 TS274M TS27M4C TS27M41 TS27M4M TS27L4C TS27L41 TS27L4M Noles: 1. Value Storage Temperature o to 70 -40tol05 - 55 to 125 o to 70 -40tol05 -55to125 o to 70 -40tol05 - 55 to 125 -65to150 OC All voltage values, except differential voltages, are with respect to network ground terminal. Differential voltages are at the noninverting input terminal with respect to the input terminal. The magnitude of the input voltage must never exceed the magnitude of the positive supply voltage. OPTIMAL OPERATING CONDITIONS Symbol . Vee Vi 2/10 878 Parameter Supply Voltage (note 1) Common Mode Input Voltage Vee = 10 V Value Unit 4 to 10 V o to 9 V TS274/TS27M4/TS27L4 I SCHEMATIC DIAGRAM (for 1/4 T527 x 4) I L I to "- f-- f-- ~ r + u + u u > "- 00 N f-- N t- I~ "' E88TS272-Q3 3/10 879 TS274/TS27M4/TS27l4 ELECTRICAL CHARACTERISTICS FOR TS274 Tamb = 25 ac, Vee = 10 V (unless otherwise specified) RL Connected to Vee Symbol Vio ex Vio lio Ib VOH AVd G wr CMR SVR Icc Is Is (Sink) Svo 0m Kov Vn V0 1 iV 0 2 Parameter 880 TS274C Typ. Max. TS2741/TS274M Min. Typ. Max. I~ut Offset Voltage §=1.4V T 274 T min < T < T max TS274A T min < T < T max TS274B T min < T < T max Temperature Coefficient of Input Voltage l'lfut Offset Current i = 5 V , Vo = 5 V T min < T < T max I~ut Bias Current i=5V, Vo=5V T min < T < T max H~h Output Voltage (note 1) i = 10 mV RL = 10 kQ T min < T < T max Large Signal Voltage Gain Va = 1 V to 6 V R L =10kQ Vi =5 V T min < T < T max Gain Bandwidth Product Av = 40 dB RL=10kQ CL = 100 pF fin = 200 KHz Common Mode Rejection Ratio Vo=1.4V V i = 1 V to 7.4 V Supply Voltage Rejection Ratio V cc = 5 V to 10 V Va=1.4V Supply Current (per amplifier) Av = 1, no Load Vo = 5 V T min < T < T max Output Current V i =10mV,V a =OV Output Current Vi = - 10 mV, Va = Vcc Slew Rate at Unity Gain Phase Mar~in at Unity Gain Av = 40 d R L =10kQ CL = 100 pF Overshoot Factor Input E~ivalent Noise Voltage f =1 K z Rs = 10 Q Cross Talk Attenuation Note: 1. Low output voltage is less than 50mV. 4/10 Min. Unit mV 10 12 5 6.5 2 3.5 10 12 5 6.5 2 3.5 5 1 1 0.1 0.2 1 1 0.15 8.2 0.3 8.2 8.4 pA nA pA nA V 8.4 8 8.1 10 ~V/oC 5 V/mV 15 10 15 6 7 MHz 3.5 3.5 65 80 65 80 dB 60 70 60 70 dB 1000 1500 1000 1600 1500 ~ 1700 mA 45 60 85 45 60 85 35 45 5.5 65 35 45 5.5 65 mA V/~S Degrees 45 45 30 30 30 30 nV/..JHZ 120 120 dB % TS274/TS27M4ITS27L4 ELECTRICAL CHARACTERISTICS FOR TS27M4 Tamb = 25 ac, Vee = 10 V (unless otherwise specified) RL Connected to Vee Symbol Vio Parameter Min. TS27M4C Typ. Max. I~ut 10 12 5 6.5 2 3.5 TS27M4A T min < T < T max TS27M4B T min < T < T max lio Temperature Coefficient of Input Voltage l'\rut Offset Current i=5V, Vo=5V AVd G wr CMR SVR Icc Is Bias Current i=5V, Vo=5V HJ:h Output Voltage (note 1) i = 10 mV RL = 100 kQ T min < T < T max Large Signal Voltage Gain Va = 1 V to 6 V RL=100kQ Vi =5 V T min < T < T max Gain Bandwidth Product Av = 40 dB RL = 100 kQ CL = 100 pF fin = 100 KHz Common Mode Rejection Ratio Vo=1.4V Vi = 1 V to 7.4 V Supply Voltage Rejection Ratio Vee = 5 V to 10 V Vo=1.4V Supply Current (per amplifier) Av = 1, no Load Vo = 5 V T min < T < T max Output Current Vi=10mV,V o =OV Output Current Vi =- 10 mY, Vo =Vcc Sv 0 om Slew Rate at Unity Gain Phase Mar~in at Unity Gain Av = 40 d RL = 100 kQ CL = 100 pF Overshoot Factor Input Equivalent Noise Voltage f = 1 KHz Rs = 10 Q Cross Talk Attenuation V01 N 02 1 0.1 0.2 I~ut Is (Sink) Kov Vn Jlvrc 2 1 1 1 0.15 T min < T < T max V OH 10 12 5 6.5 2 3.5 2 T min < T < T max Ib Unit mV Offset Voltage = 1.4 V TS27M4 T min < T < T max a Vio TS27M41/TS27M4M Min. Max. Typ. 8.7 8.9 0.3 8.7 8.6 pA nA pA nA V 8.9 8.5 Vim V 30 50 30 20 50 10 MHz 1 1 65 80 65 80 dB 60 80 60 80 dB 150 200 150 250 200 JlA 300 mA 45 60 85 45 60 85 35 45 0.6 65 35 45 0.6 65 mA V/JlS Degrees 45 45 30 38 30 38 nV/"IHz 120 120 dB % Note: 1. Low output voltage is less than 50mV. 5/10 881 TS274/TS27M4/TS27L4 ELECTRICAL CHARACTERISTICS FOR TS27L4 25°C, Vee = 10 V (unless otherwise specified) RL Connected to Vee - Tamb = Symbol Via a Vio liD Ib Parameter Min. TS27L4C Typ. Max. 10 12 5 6.5 2 3.5 AVd Large Signal Voltage Gain Vo = 1 II to 6 V RL = 100 kQ Vi =5 V T min < T < T max Gain Bandwidth Product Av = 40 dB 1 MQ RL = C L = 100 ~F fin = 10K z Common Mode Rejection Ratio Vo=1.4V V j = 1 V to 7.4 V Supply Voltage Rejection Ratio Vee = 5 V to 1 0 V Vo=1.4V Supply Current (per amplifier) Av = 1, no Load Vo = 5 V T min < T < T max Output Current Vi=10mV,Vo=OV G wr CMR SVR Icc Is Is (Sink) Svo om Kov Vn 1 V0 1 /Vo 2 6/10 882 0.2 pA nA 0.3 pA nA 1 0.15 V T min < T < T max 8.7 Note: 1. Low output voltage is less than 50mV. j.iVrC 1 0.1 8.8 Slew Rate at Unity Gain Phase Margin at Unity Gain Av= 40dB RL = 1 MQ CL = 100 pF Overshoot Factor Input Equivalent Noise Voltage f = 1 KHz Rs = 10 Q Cross Talk Attenuation 0.7 1 Output Voltage (note 1) i = 10 mV RL = 1 MQ Output Current Vj =. 10 mV, Vo =Vcc' 10 12 5 6.5 2 3.5 0.7 T min < T < T max H~h Unit mV l'lfut Offset Voltage = 1.4 V TS27L4 T min < T < T max TS27L4A T min < T < T max TS27L4B T min < T < T max Temperature Coefficient of Input Voltage I~ut Offset Current i = 5 V, Vo = 5 V T min < T < T max l'\,Put Bias Current ,=5V, Vo=5V VOH TS27L41/TS27L4M Min. Typ. Max. 8.8 9 9 8.6 V/mV 60 100 60 100 40 45 MHz 0.1 0.1 65 80 65 80 dB 60 80 60 80 dB j.iA 10 10 15 17 15 18 mA 45 60 85 45 60 85 35 45 0.04 65 35 45 0.04 65 mA V/j.iS Degrees 45 45 30 70 30 70 nV/,JHz 120 120 dB % TS274/TS27M4/TS27l4 ICC(~) I I I HIGH-BIAS VERSIONS ----- 1000 ,'f I I MEDIUM·BIAS VERSIONS ,- 100 LOW-BIAS VERSIONS 10 -....... - ...- ,,-- r-Vcc(V) 10 12 14 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Vo = Vie = 0.2 Vee, T amb= 25°C, NO LOAD 16 E88TS274-02 ICC(~) I I I HIGH-BIAS VERSIONS J 1000 I I I MEDIUM-BIAS VERSIONS 100 LOW-BIAS VERSIONS 10 ". TA('C) -50 -25 25 50 75 100 SUPPLY CURRENT vs FREE-AIR TEMPERATURE Vcc =10V, V,c=5V, Vo =5V, NO LOAD 125 E88TS274-03 7/10 883 TS27 4/TS27 M4/TS27 L4 i :Ilil liil! U~U ~rf]l iiJlI li- I 1!111'1i 1·li" I i TS274 ~ i i j [1 ,., .. , ~ lii!!i 1I i 'IiI ~HASESHIFTU'\lhl~("irl - ' .", lli" "";: " U ,Il[. i i i'l I l III "I"- 1'-:-- Ill: ,I l'~~"~',,,,, i ''0 I I 100 1,000 10,000 100000 90 i ~ ~J '0 '0 I-I I'HA$F ~(l 1,000 000 000:- 000 FREOUE~CY IH1) OPEN lOOP FMEOUENCY RESPONSE AND PHASE SHIFT Vee:: 10V. Rt...;:: 10k n.el =:: lOOpF. Tamb = 25°C EBBTS274-04 GAIN(dBI , HASf: [[[[II [[ 1[[11 r-- ~1' tftIHI GALN Uph TS27M4 IICl'I ~, [ PHAS~ Tillll'ii'~,'~ca,e) f ..... r-. 45 I" , 0 90 0 " I u , 0 10 100 1.000 10,000 100.000 1000.000 FREOUENCY (Hli OPEN lOOP FREQUENCY RESPONSE AND PHASE SHIFT Vee:::: lOV, RL -= toOkU. CL -:: l00pF, Tamb = 25 °c E8BTS274-05 GAIN (dB) 100 ao I I"" , TS27L4 GAl" to,.. I PHASE 1[[[1 11 [I [ 1IIIIIf PHASE SHIFT (ngh "".,-I!) ',~! K"".L I, I i"- 40 90 It 20 135 I..... b[ It 20 10 10 000 f 180 I 100 000 REOUE~CY IH;) OPEN LOOP FREQUENCY RESPONSE AND PHASE SHIFT Vee:::: 10V, RL:::: lMn: ,el :: lOOpF, Tamb 8/10 884 = 25"C E8BTS274-06 TS27 4/TS27M4ITS27 L4 ORDER CODES Part Number TS274C TS274AC TS274BC TS2741 TS274M TS27M4C TS27M4AC TS27M48C TS27M4t TS27M4M TS27L4C TS27L4AC TS27L4BC TS27M4t TS27L4M TS27M4AI TS27M4AM TS27M4BI TS27M4BM TS27L4AI TS2714AM TS27L4BI TS27L4BM Temperature Range °C o to + 70 o to + 70 o to + 70 - 40 to + 105 - 55 to + 125 o to + 70 o to + 70 o to + 70 - 40 to + 105 - 55 to + 125 o to + 70 o to + 70 o to + 70 - 40 to + 105 - 55 to + 125 - 40 to + 105 - 55 to + 125 - 40 to + 105 - 55 to + 125 - 40 to + 105 - 55 to + 125 - 40 to + 105 - 55 to ± 125 Package N • • • • • • • • • • • 0 J • • • • • • • • • • • • • • • • • • • • • • • • • • • • Examples: TS27L4ACN, TS274CD PACKAGE MECHANICAL DATA 14 PINS - PLASTIC DIP OR CERDIP Dotum tl) NominID dimension (2) True geometrical position 6.35 (I) 9/10 885 TS274/TS27M4/TS27L4 PACKAGE MECHANICAL DATA (continued) 14 PINS - PLASTIC MICROPACKAGE SO h 1.27 -, • t • t· t • t. t • ,- iii iii 8.55 8.75 0,185 0.265 -t+-'""""-"--- 1.75 max. 14 10/10 886 PINS UAA4002 CONTROL CIRCUIT FOR FAST SWITCHING TRANSISTORS • DIRECT DRIVE OF THE SWITCHING TRANSISTOR • SELF REGULATED POSITIVE BASE CURRENT (1 A max) • NEGATIVE BASE CURRENT ENSURING FAST TURN-OFF (3 A max) • THE OUTPUT CURRENT CAN BE INCREASED BY MEANS OF ONE (or more) EXTERNAL TRANSISTOR(S) • MINIMUM CONDUCTING TIME (or no conduction) TO ALLOW THE DISCHARGE OF A RDC NETWORK • PROTECTION AGAINST SATURATION FAILURE OFTHE POWER TRANSISTOR DURING CONDUCTING PERIOD, WITH ADJUSTABLE DETECTION THRESHOLD • INSTANTANEOUS-COLLECTOR CURRENT LIMITATION • POSITIVE SUPPLY (Vee) MONITORING • NEGATIVE SUPPLY MONITORING WITH ADJUSTABLETHRESHOLD • • • • • ON-CHIP THERMAL PROTECTION PROGRAMMABLE MAXIMUM ON TIME TTL AND CMOS COMPATIBLE INPUT CAN BE DRIVEN WITH ALTERNATE PULSES ADJUSTABLE DELAY BETWEEN THE RISING EDGE OF THE INPUT SIGNAL AND THE BEGINNING OF THE POSITIVE BASE DRIVE I '" ' ··fI,!I·.··· ,',,',"', DIP·16/2 ORDER CODE: UAA4002DP Figure 1: Block Diagram Rt RSD IS2 VINH SE E W Rt Ct IS1 V+ Vcc VCE Ic Rso Rd GNO ct October 1988 Output sink current Negative power supply (power stage) Inhibition input Input selection Input Negative supply monitoring time resistor Minimum conducting time resistor Minimum conducting time capacitor Output source current Positive power supply (power stage) Positive supply voltage VCE(sat) sensing Collector current monitoring input VCE(sat) threshold voltage monitoring Delay time resistor Ground Ground 1/12 887 UAA4002 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Vcc V+ Supply Voltage + 15 V Positive Supply Voltage (power stage) + 15 V V- Negative Supply Voltage (power stage) -10 V Voltage between Pins 15 and 2 + 18 V Positive Output Current + 1.5 - 3.5 A ±5 mA 5 kQ V+ - VIS1 Parameter 182 Negative Output Current Ic Current into Input Ic (internal protection diodes) A - Minimum Value of Resistors Rt and RD - Voltage between Input and V- + 18 V Tj Junction Temperature Range - 40 to + 150 'C Storage Temperature Range - 40 to + 150 °C T stg Note: 1. Pin 2 (V-) should not be left open. PIN CONNECTION (top view) 182 V- INH SE E RRt Ct 181 V+ VCC VCE IC RSD RD GND IS2 VINH SE E RRt Ct IS1 V+ Vcc VCE Ic RSD R 2.5 V, input SE tied to ground) V- - -2 V - Current into Input E (V (5) Input SE Left Open Input SE Grounded - 10 0.2 50 0.3 mA V ~ 0 V) - Low Level on Input INH 0 - 0.8 - High Level on Input INH 2 - Vee ~A V Time Constant ton min (R, between pin 7 and ground) 0.06 R, (kU) ~s td Delay between Input Pulse and Rise of Output Current (Ro between pin 10 and ground) 0.05 Ro (kO) ~s - Propagation between Input Pulse and Rise of Output Current 0.3 ~s ton(min) Vso W Desaturation Threshold (Rso between pin 11 and ground) V- min Detection Resistor Value (W between pin 6 and V-) BL 2 ton(max) - Time Constant ton max (C, between pin 8 and ground) Thermal Shut Down V 10 x Rso R, (1 + V-min 5 ) U 2R,C, s 150 °C APPLICATION INFORMATION The coexistence of a power circuit handling high voltages and currents, and a control circuit carrying low amplitude signals, does not represent any special difficulty provided that a few simple rules are observed. Positive and negative supply voltages of the integrated circuit must be carefully filtered by means of capacitors located very close to the device. The device itself must by situated close to the power transistor, using short connections. The control circuit ground (pin 9) and the power circuit ground (emitter of the power transistor) must be linked by a single connection, as short as possible and of adequate cross-section. A ground plane on the printed circuit board may be favourable in noisy environments. With regards to upper switches of a bridge configuration, the auxiliary supplies of the integrated circuit must have a low parasitic capacitor with respect to the ground potentiel. In the same way, the isolated components 3/12 889 UAA4002 bridge systems), adiode (1 N4148) must be connected between pin 13 and ground (cathode on pin 13 and anode on ground) in order to limit the negative voltage applied to this pin during the conduction of the free-wheel diode. driving the UAA4002 (optocoupler or pulse transformer) must have also a low parasitic capacitor in order to reduce dvit phenomenons and to avoid risks of reswitching or conduction cut-off. If a free-wheel diode is connected in parallel with the power transistor (witch is generally the case in CIRCUIT DESCRIPTION (see block diagram figure 1) INPUT INTERFACE E AND SE INPUT current of the switching does not flow through the shunt. A voltage below - 0.2 Von input Ic causes comparator to change state. This information is transmitted to the logic unit, which blocks the output pulses from the circuit until the next positive transition of the input signal. If the voltage across the measuring shunt exceeds 0.2 V for the required limiting current value, a voltage divider bridge may be used (see application note NA031A). It translates the input signal into the logic levels required by the internal processor. It also includes a RS flip-flop for the pulse mode operation. FAULT DETECTORS • Power transistor collector current limiting (Ic input) .The collector current of the power transistor is measured by means of a shunt connected in the negative return of the power supply. As a result the current rather than the emitter current, since the base If input Ic not used, it must be connected directly to ground. Figure 2 : Level Mode SE = 1. InputE ~ I I I I I I Alternate pulse SE = 0 ---.ll n*- - -Input E -----.U.-....,:rr:-------- I LJ'LL' I I I I I Output ~ "These parasitic pulses are not taken into account. Note: Pulse duration> 100ns. 4/12 890 I u* __ _ UAA4002 Figure 3 : Switching Transistor Collector Current Measurement. _ Protection against desaturation of the power transistor. Without resistor Rso, the threshold is set internally at + 5.6 V. A comparator monitors continuously during the conduction that the collector voltage on the switching transistor remains lower than the preset value. In case of overstep, the information is transmitted to the logic unit, which tums the output off until the next positive edge of the input signal. To enable the switching transistor collector emitter voltage to fall when conduction begins, the protection function against desaturation is disabled during ton min (see application note NA031A). The preset value VRSO (see figure 4) is given by : Rso Rso= 5 Vx 2 - Rt This protection is disabled by connecting pin RSD directly to V. Current I set by external resistor Rt is : 5 (V) (FOR THRESHOLD EXCEEDING 5.5 V SEE NA031EA). I (mA) = Rt (k) Figure 4 : VCEsat Voltage Monitoring. ------_. __. VCE lp To logiC processor 16 RB 'B1 I VCE Sot 'B2 UAA4002 R· 0,"" 0 ' " " "' " ","" ,,"0 0 "0" "",0 " : """"" 0 " , """" do. 00 ""d" om",", "''''" w""" '" 0 " " " ' ' ',m " '"' ", I 5/12 891 UAA4002 SUPPLY DEFECT TIME CONSTANTS .. Negative supply (R input, see figure 4). 4t is .-possible to disable 'Itle output pulses if the negative supply voltage V is insufficient to guaramee the switching of the power transistor (optional). .. Minimum conducting time (At input) Toena"ble'thecapacitor of the switcAing aid network asSOciated with power transistor to discharge completely, the logic processor ensures that the integrated circuit output pulse has a minimum duration ton min; To be effective, this must be at'least four times ttteiime constant of the RDC network. (FOR USING WITHOUTNEGATlVE POWER SUPPLY SEE NA031 A) For this a resistor R is tied between pin 6 and the negative supply. The value of tan min is prDgrammed by a resistor At TypicaUy ton min (s) = 0.06 x Rt (k) A current 2 I flows into it, and the threshold of the detector is + 5 Von pin 6. The {Jsab1e range of values forton min is between 1 and 12 s. Resistor At has a key role in the operation of the UAA4002 integrated circuit. It sets the value of a bias current internal to the circuit: Thus giving the relatiooship : 5+V-min 5 At V-min =2xR-=-(1 + - - ) 2 5 ARt This function can be disabled ty tying pin 6 to ground. 5 J(mA)= - Rt(k) .. Positive supply (Vce input) too min embodies a priority function : no other secufity,function can stop the conduction during ton min. The tan min function cannot be disabled. An internal comparator ensures that there is no output voltage if positive supply Vcc is less than + 7 V. This threshold is not adjustable. • Inhibition (INH input) • Maximum conducting time (Rt and Ct inputs) The action of the inhibition input is shown in the diagram below. This input is CMOS and TTL compatible. Jf not used, it must be connected directly to ground. .. Thermal protection At the start of each conduction period the capacitor Ct is loaded by a constant current 1/2, where I is the current through resistor At (I = 5/Rt). When the voltage across Ct reaches + 5 V the conduction is stopped. The value of ton max is thus given by the equation: The UAA4002 is protected against excessive overheating by a thermal cut-out which automatically cuts off the output pulses if the chip temperature exceeds + 150 ·C. The interruption is stored for a complete conduction period, but the output pulses reappear as soon as the chip temperature falls below the limiting temperature value. !po max (s) =2 x Rt (k) x Ct (nF) if the ton max function is not to be used, it is only necessary to replace capacitor Ct with a short-circuit. • Time delay function A constanttime delay may be implemented between the rising edge of the control pulse and the begin- Figure 5. Input Inhibition I I I I I I ----~:~rlLJl I I I I Output 892 I I I I I I ~-----------~~~----ON 6/12 I I I OFF ON UAA4002 ning of the conduction pulse at the circuit output = (1 to 20 ~ by using resistor Ro, td (IlS) = 0.05 RD (kQ). LOGIC PROCESSOR A logic unit processes the information coming from the fault detectors, and ensures that the output signal fulfils two conditions: Figure 6. ~---~--~- . -------~--, input - - - - - - ' Output ---->---jll'-------I I I I ~ 'd • No double pulsing within a period: the occurence of a defect is memorized until the end of the period. • ToO aHow the discharge of a snubber network, the minimum output pulse width is set at a given value ton min. OUTPUT STAGE : V+, V-, IS1, IS2, INPUTS • Introduction The highly sophisticated output ·stage of the UAA4002 offers high performance is terms of switching transistor control. Its principal features are as follows: _ the switching transistor is direct driven _ the transistor remains in a quasi-saturated state, whence reduced storage time _ control power is limited to the strict minimum it is easy to use This stage is in fact in two parts, a positive driver stage which turns on the transistor and a negative driver stage which turns off the transistor. Figure 7. ------------, High voltage supplv ----------------------~ 7/12 893 UAA4002 • Power transistor conduction The maximum value of the positive base current is determined by the limitation resistor R (lsI 1 A). A regulation loop is used to keep Tp in a quasi-saturation mode: the more Tp becomes saturated, the more diode 0 will shunt an important part of the drive current lSI, through diode 01. Rs is a low value resistor (about 1 ) which helps to stabilize the regulation loop. Voltage VCE across transistor Q is : VCE (V) = VSE (V) + Rs () lSI (A) If the required drive current is greater than 0.5 A, one external NPN transistor may be added. In this case: VCE (V) = 2 VSE (V) + Rs ().Is (A) • Turn-off switching of power transistors The closing of contact K2 (figure 10) causes Darlington T2 to conduct. The negative supply voltage is applied to the base of transistor Tp and a high negative base current IS2 flows, permitting the rapid evacuation of charges stored in the base-emitter junction of transistor T p. The Darlington T2 can carry a maximum current of 3 A. The corresponding saturation voltage is typically 3 V. Like the positive stage, this stage is designed for easy augmentation of the available output current by the addition of one or more external transistors. • Typical inductive load waveforms When conduction begins, the base current assumes a high value briefly and then reverts to zero. This base current spike permits rapid switching on of the power transistor. The base current value is then that required for quasi-saturation of the transistor. The base current CUNe is generally cUNed upwardy, due to the decreased gain of the power transistor with increased collector current. Figure 9. Figure 8. ----------, A low-value inductor L may be required between the base of transistor T p and the IS2 output of the UAA4002, so as to limit the gradient dls2fdt (see "The Power Transistor in its Environment" published by the Discrete Semiconductors Division of Thomson-CSF). In many cases, this inductor is not required. Vee --------, UAA4002 v_____ ---1 v The external PNP transistor increases the negative current available while decreasing the power dissipation in the UAM002. 8/12 894 UAA4002 I Figure 10. ! -------------------------------------------- l I Power transistor collector current d1B2~ dt Power transistor base current Voltage on pin VeE of UAA4(X)2 ov------------------- CONTROL OF MOS POWER TRANSISTORS Ideally,MOS power transistors should be voltagecontrolled_ In practice, in order to benefit from the high speed typical of this type of transistor it is necessary to charge and discharge the spurious input capacitance at high speed, so that high currents flow. By virtue of the high current capability of its output stages, the UAA4002 is particularly suitable for controlling MOS power transistors. The output of the positive stage is connected directly to the gate of the MOS transistor, to switch it into conduction very fast. The negative stage controls the turning off of the MOS transistor, by discharging the gate capacitance of the transistor. There is no need for a high negative supply voltage, and the ar- rangement described in the previous section is therefore used. In this circuit the UAA4002 is used in a completely conventional manner, in "Ievel" control mode. The time constant Ion min is set at 2.8 s, which is four times the time constant of the snubber network associated with the BUV37 transistor. The positive output stage of the UAA4002 is connected to the Vcc rail through a 15 resistor. The maximum base current is approximately 0.45 A. The collector current is measured using a 0.10 shunt, and is limited to 10 A. The BUV37 Darlington for which the specified value of ICsat is 12 A, is thus operated with a considerable safety margin. 9/12 895 UAA4002 Figure 11. -t lOOV 47.n 0 GI Tp FOR MORE INFORMATION SEE NA031A TYPICAL APPLICATIONS Figure 12: 8 A. 400 V switch. I"~ BA 1591 .....~t---------, 270 III n 6W *Note 1 BY 218 400 HT -5V 390 .n L---____________~~------------------~~-------------------Ol , Noles: 1. Switching aid network. 2. Polypropylene capacitor. 3. With heatsink. RrlT < 3.5 "/W. 10/12 896 I UAA4002 Figure 13: 150 W Forward Type Power Supply. - - - - - - ---------------------------- ----------1 II' Lee I r 10 rbA '0·· ,e ",," >'V.,I- c,pnmJ'VJn!l'lwcr""I,,,y,,,,,,, ¢. • ~"ma'yg'Olln<:l Seeonda'Y9H1un d I '------------~~~~_~___.J Performance • Output voltage stability: For an input voltage varying from 190 to 245 V, the maximum relative variation in the output voltage is 0.7 % at nominal operating conditions. (VOUT = 25 V, lOUT = 6 A). For a variation in the load from 0 to 100 % the relative variation in the output voltage IS 1.3 %. For a variation in the load from 10 to 100 % (lOUT = 0.6 to 6 A), the relative variation in the output voltage is 0.4 %. • Efficiency 80 % under nominal operating conditions. • Behaviour on overload: The power supply is fully protected against overloads and short-circuits, the output current being limited to 7 A. 11/12 897 UAA4002 Figure 14 : Capacitor Type Half Bridge Symmetrical Converter. '+Io---------------------~~~--, HC>------..!.-.!------....-4-.....J Figure 15: 200 A, 700 V Switch. BATfi!)! ~--~oJ---- II r- I fJ 12/12 898 - -------~ : i LSM 4120 WOO I , 170°C), the two output stages are disabled, After a decrease of the junction temperature (typically . 30°C), the outputs are again enabled. TYPICAL APPLICATION EXAMPLE OF APPLICATION A complete application can be built with only one UA.4718 and three external components (2 resis- tors and 1 capacitor). On the figure below, 10 A per output, the switching frequency is 35 KHz. Figure 4. ,---- - - - - fROM 5 n • .Kl Mb ~J~_ _ _ _ _ _ _ _ _- . E.b 1-'---1=1-0 Md ~"_ _ _ _ _--, MICHOI'HOCl:>SOR " '0 OS<; o SHYf'l R MOTOH 8/8 914 UAF1780-1781-1782 DUAL 2 A LOW DROP OUT INTELLIGENT POWER SWITCH ADVANCE DATA • LOW POWER DISSIPATION (LOW VSAT: 0.6 V @2A) • ALL INPUTS ARE OPERATIONAL WITH CONTROL SIGNALS HIGHER THAN Vee • ALL INPUTS WITHSTAND VOLTAGES LOWER THAN GROUND • HIGH OUTPUT CURRENTS • PROTECTION OF OUTPUT TRANSISTORS (UPTO + 32 V) • THE OUTPUTS CAN WITHSTAND VOLTAGES LOWER THAN GROUND • WITHSTAND ON Vee SPIKES UP TO (60 V, 10 ms) • DIFFERENTIAL INPUTS MUL TIWATT-15 ORDER CODES: UAF1780SP UAF1782SP UAF1780HSP UAF1782HSP DIP-16/2 DESCRIPTION The UAF1780-1781-1782 are dual interface circuits delivering high output currents and capable of driving any type of load. An on-chip dc/dc conversion unit in conjuction with a few low-cost external components (a low value inductor and a low voltage capacitor) are implemented to limit the saturation voltage thereby optimizing the efficiency. The devices are particularly well protected against destructive overloads. Each output implements a current limit circuitry, a desaturation monitoring unit for the detection of overloads and short-circuits, and a thermal protection feature. Corresponding output is turned off in case of prolonged desaturation or excessive internal dissipation. This condition is reflected by a low level on ALARM output terminal. This protection unit can be reactivated by applying a logic low signal to RESET input. However, for inductive loads, a delay is imposed on signal applied to this RESET input so as to prevent a rapid and premature conduction of output transistors. A logic high signal applied to STROBE input will disable both power outputs. ORDER CODE: UAFI780DP-1781DP PIN CONNECTIONS Input 1 Delay 1 Reset Output 1 Strobe Alarm 1 Ground Current limit adjust Oscillator Vee Reference Alarm 2 V(aux) Input 2 The devices operates within a supply voltage range of + 8 V to + 32 V. September 1988 1/6 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 915 UAF1780-1781-1782 PIN CONNECTIONS 1 -Oscillator 9-Vcc 10-0utput 1 11-Alarm 1 12-Delay 1 13 -!!!.2.~.U 14-Reset 15-Strobe 2 -V(aux) 2 6 3 5 8 7 10 9 12 11 3 -Input 2 4-Delay 2 5-Alarm 2 6 -Reference 7 -Output 2 8-Ground 14 13 15 I i _J ABSOLUTE MAXIMUM RATINGS - Symbol n -- Parameter ~ ..- . - ,------ Value Unit ~-- Supply Voltage + 35 V Input Voltages 30 to + 55 V 10 Output Current Internally Limited A IL Current In DC/DC Converter Inductance Vcc V I1 Vl2 Vreset Vstrobe P tot Toper TJ Total Power Dissipation Operating Free-air Temperature Range --- Junction Temperature 0.4 A Internally Limited W - 40 to + 85 'C + 150 'C 25 2.5 70 40 'C/W • + 60 V (10 mS) THERMAL DATA RthIJ-c) Maximum Junction-case Thermal Resistance Rth(J-a) Maximum Junction-ambient Thermal Resistance 216 916 DIP.16 Multiwatt DIP.16 Multiwatt I 'C/W -- III r o ("') "ci> G) :II Oscillator » s: ,. --_.1.._--, I I I CONVERTER IL _ _ _ _ _ _ _ _ _ _ _ _ 10 ADJUST I L ___ ...,.____I I -------------~--------~ ~ ;!SUI ~~ @. ~i! ~o ~! ~o ~z c »"T1 Reference Alarm 1 Input 1 STROBE Reset Input 2 Alarm 2 Only in CB·79 package \/ersion ...... o . . ..... (Xl ..... ...... (Xl (0 ...., ...... ~ (Xl 1\:1 UAF1780-1781-1782 ELECTRICAL CHARACTERISTICS Vee = + 24 V, - 40 DC, <:: Tamb <:: + 85 'C (unless otherwise specified) Syv::~ I-Supply Voltage parameter _______ tMi~ ___TYp.___t=M:2x- . ~u~~~ I!I --------------+----+----+---_+--__1 mA Icc Supply Current Input 1 = Input 2 : Low 7 __ ~p~=lnput 1 : High, 10 ~_~X_2_A_._____________+__--+_-2-5-+1-3-2-_t_--__1 1, Input Current (all inputs) I V,>V cel , 15 I 50 V, < Vcel a i r--'-"---+-------~--~---- I ~ 10HA a High Level Alarm Output Leakage Current (V A = + 10 V) ~. Level 10 flA Alarm Output Voltage (IA = + 10 mAl ___~_I' __1~__1-1---,3--+----V--__1 Po~er Outputs Dropout Voltage V I 10 = 0,5 A 0.15 I 0.25 i 10 = 1 A 0,3 0,4 I 10 = 2 A __________ 0,6 I 07_"----_ f-i_--_I-O-L-_~-+-~~o-w-e-r-o-!'=_tP~u-~t-s=L=e=a-k_a=_g-e-C_-u--rr-e~_ . 100 I flA00LA I Vee - Vo- I I' ----1-L t cese ! Reset Pulse Duration ( C1 = C2 = 1 flF) Delay Time before Desaturation Monitoring Unit Becomes--- -Active VccVceVcc - Vcel Icel 10 ! I I Reference Input Current (Vcel = 1,4 V) All Inputs < Vcel All Inputs> Vee I - 1 mS ------I-- mS- 20 10 5 1,4 55 I I V flA 80 a 150 +1 Available Output Current UAF1780DP 2,5 Ro = = Ro = 2 KQ I UAF1780SP UAF1781 DP II I 400 --~-T-- (C1 = C2 = 1flF) Vo=+12V Vo=+24V Vo = + 32 V Reference Input Voltage I I I Ro = = Ro = 2 KQ I' A 1 25 2~ _+I-------------.---t----1 -+-____-+___-_+_-50-+--V-~ _______ 1---- _ _ _ _ _ _ _ ~__~ _ _ _U_A_F_1_7_8_2_S_P_ _ _ _ _ _ r-V~c~c_-_V~0-t-_M_a_x_im_u_m_O_u_t~p_ut_V_o_l_ta~g~e_S_w_i_ng~___________ ~____ Vaux - Vcc 4/6 918 DC/DC Output Voltage 0.5 A < 10 < 2 A (each output) CO = 47 flF, L = 100 flH I i 1.25 V UAF1780-1781-1782 Fig 1 - DIP. 16 PACKAGE. Fig 2 - ~ z o i= ~ i'. 50 25 I-~~-t on on I'\. o 9 o 0:: w I' "Ii' 4 75 25 50 75 100 125 150 AMBIENT TEMPERATURF (oC~ AMBIENT TEMPERATURE (OC) Fig. 3 - MUL TIWATI PACKAGE AVAILABLE OUTPUT CURREIIT VS EXTERNAL RESISTAI;CE VALUE DIP. 16 PACKAGE. Fig 4 - SATURATlON VOLTAGE VS ou II-'U 1 CUHflitl=N I 2 a: ~ 1.2 UAF1/0e~ I- L / ~B~ ~ '"'"::J U I- ::J "- I- :J 0 0.5 8 w Q w 1.5 / V ,y o V L /' « I- §;--' 0.8 I---:;/;_~~-+--'-'r-:.::;::..:...:::r:-- z o i= « § 0.4 I--+--t---t-+--t---+~-i""-=--t--r-----t----j I- « UJ 0.5 \.5 o 2.5 2 .4 R1 RESISTOR UALUEIKohm) Fig 5 RFSPONSE TIME. Fig.6 ::: w c.:J « I- /1 --' o > l- 0 I ii: I I I- co o o i z « I- co l 1.2 16 RESPONSE TIME ~ . w Q '~_2A J \ I- o--' > 0 \'O=05A , I::J "I- co - o o « '" 0 .8 OUTPUT CURRENT (AI 0 I::J "- z "~ 1 0.4 T"~E IpS) 0.8 4 10 TIMf: (PS) 5/6 919 UAF1780-1781-1782 Figure 7 : Typical Application. Vee ~-------------------r----'---.-------r-----.---r---r--,r--, • RO only necessary with DP package _ Lo and Co are the external elements of the dc/dc converter. Typical values and characteristics of these components are as follows: For Lo : - inductance = 100 ~H (tolerance ±10%) - maximal current :2: 400 mA Size Evaluation For dc/dc Inductance 10 max. 5 max. f For Co : The value of this capacitor is not critical, a capacitor of C1 :2: 47 F, Vn :2: 6.3 V will be suitable for the majority of the applications. _ The on-chip dc/dc converter can be disabled by connecting V(aux) terminal to Vec and leaving "Oscillator" pin floating. 6/6 920 ~ 'OA~ ~ _ C1 and C2 implement two distinct functions: - response time required by the desaturation monitoring unit to become active. time delay imposed on each power output prior to conduction. t _ C· 3.5 V d 7 ~A With C2 = C3 = 1 ~F, the outputs are protected against voltage transients of as high as + 32 V and the response time of the desaturation monitoring unit is 400 ms. _ DZ1 and DZ2 Zener Diodes are required in the case of inductive loads. Vz of these diodes should be < 60 V. _ Ro determines the value of maximum output current (DIP package). Its value is given in curve 3, where output current values are plotted against the corresponding values of this resistor. UC1840 UC2840 UC3840 PROGRAMMABLE, OFF-LINE, PWM CONTROLLER • ALL CONTROL, DRIVING, MONITORING, AND PROTECTION FUNCTIONS INCLUDED • LOW-CURRENT, OFF-LINE START CIRCUIT • FEED-FORWARD LINE REGULATION OVER 4 TO 1 INPUT RANGE • PWM LATCH FOR SINGLE PULSE PER PERIOD • PULSE-BY-PULSE CURRENT LIMITING PLUS Sf-:jUTDOWN FOR OVER-CURRENT FAULT • NO START-UP OR SHUTDOWN TRANSIENTS • SLOW TURN-ON AND MAXIMUM DUTY-CYCLE CLAMP • SHUTDOWN UPON OVER-OR UNDERVOLTAGE SENSING • LATCH OFF OR CONTINUOUS RETRY AFTER FAULT • REMOTE, PULSE-COMMANDABLE START/ STOP • PWM OUTPUT SWITCH USABLE TO 1A PEAK CURRENT • 1% REFERENCE ACCURACY • 500 kHz OPERATION -- ----- ------- - - I DIP-18 (Plastic and Ceramic) DESCRIPTION Although containing most of the features required by all types of switching power supply controllers, the UC1840 family has been optimized for highlyefficient boot-strapped primaryside operation in forward or flyback power converters. Two important features for this mode are a starting circuit which requires little current from the primary input voltage and feed-forward control for constant volt-second operation over a wide input voltage range. In addition to startup and normal regulating PWM functions, these devices otter built-in protection from over-voltage, under-voltage, and over-current fault conditions. This monitoring circuitry contains the ad c ded features that any fault will initiate a complete shutdown with provisions for either latch off or automatic restart. In the latch-off mode, the controller may be started and stopped with external pulsed or steady-state commands. September 1988 Other performance features of these devices include a 1% accurate reference, provision for slowturn-on and duty-cycle limiting, and highspeed pulse-by-pulse current limiting in addition to current fault shutdown. The UC1840's PWM output stage includes a latch to insure only a single pulse per period and is designed to optimize the turn off of an external switching device by conducting during the "OFF" time with a capability for both high peak current and low saturation Voltage. These devices are available in an 18pin dual-in-line plastic or ceramic package. The UC 1840 is characterized for operation over the full military temperature range of -55"C to + 125"C. The UC2840 and UC3840 are designed for operation from -25"C to +85"C and O"C to +70"C, respectively. 1/10 921 UC1840-UC2840-UC3840 PIN CONNECTION AND ORDER CODES ~ COMP(NSATION , 1(\ NON INV INPUT INY INPUT START I UV 11 a v SENSE '6 STOP " S .Vi SUPPLY DRIVER BIAS 1L RESET cuRRENT THRESHOLD 13 CURRENT SENSE 11 5LDW- START ,,~ R T' C T [ S '0 v REF GROUND Type Plastic Ceramic UC1840 UC2840 UC3840 UC2840N UC3840N UC1840J UC2840J UC3840J OUTPUT PWM V I SENSE P RAMP 5-6"001 ABSOLUTE MAXIMUM RATINGS Symbol Vi Parameter Supply Voltage + Vi (pin 15) Voltage Driven Current Driven 100 mA Maximum Test Conditions Unit 32 Self Limiting V Vo PWM Output Volage (pin 12) 40 V 10 PWM Output Current, Steady-state (pin 12) 400 mA 20 -200 ~ mA - 50 20 10 - 0.5 to + 55 - 0.3 to + 32 mA mA mA V V Eop lo(REF) Ptot PWM Output Peak Energy Discharge Driver Bias Current (pin 14) Reference Output Current (pin 16) Slow Start Sink Current (pin 8) Vi Sense Current (pin 11) Current Limit Inputs (pin 6, 7) Comparator Inputs (pins 2, 3, 4, 5, 17, 18) 1000 mW Junction Temperature Range - 55 to + 150 °C Top Operating Ambient Temperature Range: UC1840 UC2840 UC3840 - 55 to + 125 - 25 to + 85 o to + 70 °C °C °C Totg Storage Temperature - 65 to + 150 °C Tj Power Dissipation at T amb = 70 OC THERMAL DATA Thermal Resistance Junction-ambient 2110 922 Max 80 UC1840-UC2840-UC3840 BLOCK DIAGRAM SENSE ~--~--------------------------~10R4MP ®>---~~~~~ COIolP INY.INPUT N.l.INPUl srART/UV RE50El lHRESHOLD --,J-:-@OJRU"" - 7 ~~~iNT 'OOm'" FUNCTIONAL DESCRIPTION Function Name PWM CONTROL OSCILLATOR Generates a fixed-frequency internal clock from an external RT and CT. Frequency = Kc ~~ where Kc is a first-order correction factor ~ RTCT 0.3 log (C T x 10 '2 ). RAMP GENERATOR Develops a linear ramp with a slope defined externally by dv sense vOltage C R is normally selected <; CT and dt RR CR its value will have some effect upon valley voltage. CR terminal can be used as an input port for current mode control. ERROR AMPLIFIER Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance: unity-gain stable. REFERENCE GENERATOR Precision 5.0 V for internal and external usage to 50 mA. Tracking 3.0 V reference for internal usage only with nominal accuracy of ± 2 'Yo. 40 V clamp zener for chip O. V. protection, 100 mA maximum current. PWM COMPARATOR Generates output pulse wich starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. PWM LATCH PWM OUTPUT SWITCH Terminates the PWM output pulse when set by inputs for either the PWM comparator, the pulse-by-pulse current limit comparator, or the error latch. Resets wich each internal clock pulse. Transistor capable of sinking current to ground wich is off during the PWM on-time and turns on to terminate the power pulse. Current capacity is 400 mA saturated with peak capacitance discharge in excess of one amp. 3/10 923 UC1840-UC2840-UC3840 FUNCTIONAL DESCRIPTION (continued) .-------.----.--~-.-.---.----------.----, Name Function _ I SEQUENCING FUNCTIONS START/U. V. SENSE i------ This comparator performs three functions. With an increasing voltage, it generates a turn-on signal at a start threshold With a decreasing voltage, it generates a U. V. fault signal at a lower level separated by a 200 J.lA hysteresis current. At the U. V. threshold, it also resets the Error Latch if the Reset Latch has been _ls EJt _________ - - - - _ - - - - - - - - - -- _ - - - j Disables most of the chip to hold internal current consumption low, and Driver I .1.B~s..0F'F':_urltil input_vol~ge reacl1e~tartt.hreshold_.___________ --.--1 I Supplies drive current to external power switch to provide turn-on bias. I I I O:I:I:::II::H [ SLOW START Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RsC s for slow increase of output pulse width. Also used to clamp maximum duty cycle with divider Rs Roc. START LATCH Keeps low input voltage at initial turn-on from being defined as a U. V. fault Sets at start level to monitor for U. V fault RESET LATCH When reset, this latch insures no reset signal to either Start or Error latches so that first fault will lock the PWM off. When set, this latch resets the Start and Error latches at the U. V low threshold, allowing a restart ! L--· ! I I I I PROTECTION FUNCTIONS ERROR LATCH r-I 4/10 924 CURRENTLIMITING When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a, U, V. low (after turn-on) b, 0, V high c, Step low d, Current Sense 400 mV over threshold Error Latch resets at U, V, threshold if Reset Latch is set. Differential input comparator terminates individual outp~tpu-I~e;;_-~;~hti~~ensel voltage rises above threshold, I When sense voltage rises to 400 mV above threshold, a shutdown signal it sent to Error Latch, UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (refer to the test circuit. Unless otherwise stated, these specifications apply for T, = - 55 to + 125 'C for the UC1840, - 25 'C to + 85 'C for the UC2840 and 0 to + 70 'C for the UC3840; Vi = 20 V, RT = 20 Kn, C T = 0,001JlF, C R = 0,001 JlF, current limit threshold = 200 mV) I lI Unit POWER INPUTS liST Start-up Current I V, = 30 V, Pin 2 = 2 5 V, ~Start-ufl. Cu!ren~T c'I:~ :~~ Z~_~ 2~5_V 1_ _ _ _ =_ L__ -, ~-:,1 ' r----" ___tOPeratII19Cur':Elr1t___V,"'3°v,Pln2_=35V: 5 1_1~ l~_ 33 40 1 ~~pply ~ ~ ~arl1P_ _ -" = ~O _m A _ _ _ REFERENCE SECTION I VREF , Reference Voltage ~~::; ~~:dRR;:::::::, I TJ i :::::: ~~A !1V.REF~!1 ~'LTemperature cae.ft'. Isc I Short Circuit Curr, 15 ~5~05T [_ ---~. : over .. oP.' TemP. . . ' Range ". 5 L 3_3__, ___ _ ___ r ...-,---+---+i%-. ::-1- +i:- :-2S;'C- - - -- -1~95 ,- 5 - ---.---~------------~----- _5052 . .'. .... i .+...0. 4.9- -5-----:5:1:-"'-1 A.I. . II - 80 _'--\.Irl EF -'" ~2!-", ~5--"-~ ______-_8~~-_100L ____ :~ -I ~: --1----···-- . ± 0.4 j mV;oC . - 100 I mA OSCILLATOR RAMP GENERATOR 5110 925 UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter UC1840 UC2840 UC3840 Min. I Typ. I Max. Min. I Typ. I Max. 0.5 5 2 10 mV 0.5 2 1 5 !JA 0.5 !1A Test Conditions Unit ERROR AMPLIFIER Vas Input Offset Voltage VCM = 5 V Ib Input Bias Current los Input Offset Current Gv Open Loop Gain i'1Vo = 1 to 3 V 60 Output Swing (max Out S; Ramp Peak 100 mV) Minimum Total Range 0.3 CMR Common Mode Rejection VCM = 1.5 to 5.5 V 70 80 70 80 dB SVR Supply Voltage Rejection Vi = 8 to 30 V 40 50 40 50 dB 0.5 Isc Short Circuit Current Vcomp = OV B' Gain Bandwidth Tj = 25°C. Gv = 0 dB Slew Rate T J = 25°C, Gv = 0 dB SA' 66 3.5 -4 1 60 0.3 1 0.8 dB 3.5 -4 -10 2 66 - 10 V mA 2 MHz 0.8 V/!1s PWM SECTION 'Continuous Duty Cycle Range (other than zero) Min. Total Cont. Range Ramp Peak < 4.2 V 5 95 5 95 % V Volsat ) Output Saturation 0.2 OA 0.2 OA Volsat ) Output Saturation 10 = 200 mA 1.7 2.2 1.7 2.2 V 10L Output Leakage Vo = 40 V 0.1 10 0.1 10 !1A Cd 'Comparator Delay Pin 8 to pin 12 Tj = 25°C, RL = 1 KG 300 500 300 500 ns 3 3.2 2.8 3 3.2 V -1 -3 !1A 120 180 240 !1A . 10 = 20 mA SEQUENCING FUNCTIONS VT Ib 6/10 926 Comparator Threshold Pins 2, 3, 4, 5 Input Bias Current Pins 3, 4, 5 = OV StartlUV Hysteresis Current Pin 2 = 2.5 V, Tj = 25°C Input Leakage Vi = 20 V Driver Bias Saturation Voltage V1N-VOH IB =-50 mA 2.8 120 - 1 -3 180 240 0.1 10 0.1 10 !1A 2 3 2 3 V Driver Bias Leakage VB = OV - 0.1 - 10 - 0.1 -10 Slow-start Saturation Is = 2 mA 0.2 0.5 0.2 0.5 !1A V Slow-start Leakage Vs = 4.5 V 0.1 2 0.1 2 !1A UC1840-UC2840-UC3840 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter UC1840 UC2840 Test Conditions UC3840 I Typ. I Max. Min. Min. JTyp.! Max. Unit CURRENT CONTROL 0 5 400 440 -2 -5 Current Limit Offset 340 Current Shutdown Offset Ib Input Bias Current Pin 7 = OV - 0.3 'Common mode Range 'td' Current Limit Delay 340 200 10 mV 440 mV -2 -5 !lA 3 V 400 ns - 0.3 3 Tj =25 °C, Pin 7 to 12 RL = 1 KO 0 400 400 200 • Guaranteed by design. Not 100 % tested in production. Figure 1 : Open Loop Test Circuit. suPPlV VOLrAGE RR 1,00KIl RS[ 180Kll ROC 2 1 '5 V'N SLOW ST. 8 16 VREF. RT 0:° OA~ l1V1N SENSE ::I:' nF CT£R' 20K.ft. R2 9KIl DRIV. BIAS 14 L=1Kfl. OUT MOl GNO 13 r - 10 RAMP , CR~ COMP. __ l:nF --- - STOP 4 RESET 5 INV. '7 ,. N.!. C/L(-) e/L(+) 6 7 GoJ VREF fO"I'F + UC1840 3.0V SENS 'OA OR Cs PWM OUT 12 9R T'CT 2 START J UV R' r---<----o Ilt 'OKA 10KA L...-....I PWM ADJ. )t. ).o,,---i )1° I 4" KIl L.... KIl KJl CURRENT SENSE S-6101l Nominal frequency = Start voltage = RTCT = 50 kHz 3 (R1 + R2 + R3) + 0.2 RJ R2+R3 . = 12 V -I.. .~ TEST O.V. fault voltage = 3 (R1 +:~ + R3) = 32 V Current limit = 200mV Current fault voltage = 600mV Duty cycle clamp = 50% U.v. fault voltage = 3 (R1 + R2 + R3) = 8 V R2+R3 7/10 927 UC1840-UC2840-UC3840 Figure 2 : Start U.V. Hysteresis Current. Figure 3 : PWM Output Saturation Voltage. - G-!)364/1 Go 5365 'H VCE(sat ) 'V) (,tJAI -~-+''V::-;n-020:::C-V-~+--+-----j--+-+--1 275 Vin=20V LOW DUTV-C~LE PULSE TEST 250r-_r~~;;n~2~O_2_.5_V+-----j_~_-r_~_+-~ t--- I-- Tj=25"C f-- 125 100 I: ~ 1// -,~ ~ L--_L-----'_--'-_-'-_-"--_L----'._-' -50 -25 25 50 7S 100 Figure 4 : Oscillator Frequency. 10 20 50 60 100 200 10 RT(Io(!l) SO 100 200 fo (KHz) V4 -~ '"" - - "--- - -- - ~ GAIN V8 5 'V) 1K 10K l'" DUTy CYClE CLAMP VOLTAGE Cs =0 c5 >0 " " t---~- - PHASE INPUT loJXT. STOP - '""' - - -- - r- - r- '""' - Vl220 'V) f\--- 180 lOOK 1M f 1H z PWM ouTPUT VOLTAGE! 270 -"""'r- 928 30 'V) ~- 8/10 20 Figure 7 : Shutdown Timing. Vjn =2OV 40 100 400 10 (mAl ~ -~ 300 G 5368 - 20 200 Figure 5 : PWM Output Minimum Pulse Width. Figure 6 : Error Amplifier Open-loop Gain and Phase. Gy (dBI ./ v 100 Tj (·C) ---::::p::= .L T"..-55"C ~ I 360 ) 500 1000 UC1840-UC2840-UC3840 APPLICATION INFORMATION Figure 8 : Programmable PWM Controller in a Simplified Flyback Regulator. DC INPUT LINE CONTROL VOLTAGE In this application [see Fig.8] complete control is maintained on the primary side. Control power is provided by RIN and CIN during start-up, and by a primary-referenced low voltage winding. N2, for efficient operation after start. The error amplifier loop is closed to regulate the DC voltage from N2 with other outputs following through their magnetic coupling - a task made even easier with the UC 1840's feed-forward line regulation. IT IT IT The UC 1840 will readily accept digital start/stop commands transmitted from the secondary side by means of optical couplers. Not shown are protective snubbers or additional interface circuitry which may be required by the choice of the high-voltage switch, Os, or the application 9/10 929 UC1840-UC2840-UC3840 Figure 9 : Power Sequencing Functions. D E I I A I G I HI J III "N 0 I I I III H I J I I I M N 0 Q R S I I I Vc (NOTE!) DRIVER BIAS SLOW- START PWM OUTPUT EXT. STOP U RESET I I oE I I I I Q R S U I v Notes: 1. VG represents an analog of the output voltage generated by a primary·referenced secondary winding of the power transformer. It is the voltage monitored by the start/U.V. comparator and. in most cases, is the supply voltage, Vi, for the UG1840. 2. Although input to External Stop, Pin 4, is shown, results are the same for any fault input which sets the Error Latch. POWER FREQUENCY FUNCTIONS -- -- --- --- Time --- -~-- ITi~e Event A Initial Turn-on, Vc Rises with Light Load B Start Threshold. Driver Bias Loads Vc C Operating PWM Regulates Vc D Stop Input Sets Error Latch Turning off PWM I M i U. V. Low Threshold. Error Latch Remain Set F Start Turns on Driver Bias Bus Error Latch Still Set G Vc and Driver Bias Continue to Cycle H - I -- -- - Stop Command Removed -- .. -- - --_.- Event --.--~-- Reset Latch Set Signal Removed 1- N Error Latch Set with Momentary Fault 0 Error Latch does not reset as Reset Latch is I reset I P Q R I S ..- Error Latch Reset at U. V. Low Threshold K Start Threshold Now Removes Slow-start Clam 930 I I - J 10/10 ....-... - E ~~ -- Return to Normal Run State - -- Vc and Driver Bias Recycle with no Turn-on I Reset Latch Set is Set with Momentary Reset Signal I Vc must Complete Cycle to Turn-on T Start and Error Latches Reset U Normal Start Initiated ~ I V- Return to Normal Run State i UC1842/3/4/S UC2842/3/4/S UC3842/3/4/S CURRENT MODE PWM CONTROLLER • OPTIMIZED FOR OFF-LINE AND DC TO DC CONVERTERS • LOW START-UP CURRENT « 1 mAl • AUTOMATIC FEED FORWARD COMPENSATION • PULSE-BY-PULSE CURRENT LIMITING • ENHANCED LOAD RESPONSE CHARACTERISTICS • UNDER-VOLTAGE LOCKOUT WITH HYSTERESIS • DOUBLE PULSE SUPPRESSION • HIGH CURRENT TOTEM POLE OUTPUT • INTERNALLY TRIMMED BANDGAP REFERENCE • 500 KHz OPERATION • LOW Ro ERROR AMP tor which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC 1842 and UC 1844 have UVLO thresholds of 16 V (on) and 10 V (off), ideally suited to off-line applications. The corresponding thresholds for the UC 1843 and UC1845 are 8.5 V and 7.9 V. The UC1842 and UC1843 can operate to duty cycles approaching 100 %. A range of the zero to < 50 % is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. DESCRIPTION The UC 1842/3/4/5 family of controllCs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under voltage lockout featuring start-up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM com para- Minidip Plastic and Ceramic 50-14 J 01 P-14 Plastic BLOCK DIAGRAM (toggle flip flop used only in UC1844 and UC1845) Vi 5(9) GROUND VREF 5V SOmA VFS 2(3) 1(1} COM. 0 - - - - - - ' 3(5) CURRENT SENSE September 1988 1/8 931 UC1842/3/4/5-UC2842/3/4/5-UC3842/3/4/5 ABSOLUTE MAXIMUM RATINGS' Symbol Parameter Vi Supply Voltage (low impedance source) Vi Supply Voltage (Ii < 30 mAl 10 Output Current Eo Output Energy (capacitive load) Unit 30 V Self Limiting Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Power Dissipation at Tamb"; 50 ° C (minidip, DIP-14) Ptot Power Dissipation at Tamb"; 25 ° C (SO-14) T stg Storage Temperature Range TL Value Lead Temperature (soldering 10 s) ± 1 A 5 iJJ - 0.3 to 6.3 V 10 mA 1 W 725 mW - 65 to 150 °C 300 °C • All voltages are w~h respect to pin 5, all currents are positive into the specified terminal. BLOCK DIAGRAM (top view) DIP-14/ SO-14. Minidip Plastic and Ceramic. r--v t 14 N.C. 2 13 N.C. VFB 3 12 Vi N.C. 4 11 Vo ISENSE 5 10 COMPo VREF COMP ISENSE 3 OUTPUT OUTPUT 5 N.C. 6 9 GROUND RT/C T 7 8 POWER GROUND GROUNO 5-9"'3 ORDERING NUMBERS TYPE PLASTIC MINIDIP UC1842 UC1843 UC1844 UC1845 218 932 CERAMIC MINI DIP DIP-14 50-14 UC1842J UC1843J UC1844J UC1845J UC2842 UC2843 UC2844 UC2845 UC2842N UC2843N UC2844N UC2845N UC2842J UC2843J UC2844J UC2845J UC2842B UC2843B UC2844B UC2845B UC2842D UC2843D UC2844D UC2845D UC3842 UC3843 UC3844 UC3845 UC3842N UC3843N UC3844N UC3845N UC3842J UC3843J UC3844J UC3845J UC3842B UC3843B UC3844B UC3845B UC3842D UC3843D UC3844D UC3845D Gi SGS·1HOMSON ~I ~n©IIOO1!.I<©"irIl@llln©$ UC1842/3/4/5-U C2842/3/4/5- UC3842/3/4/5 THERMAL DATA Rth j-amb I Thermal Resistance Junction-ambient Ceramic Minidip Plastic DIP-14 Minidip Plastic 200°C/W 100°C/W 100°C/W SO-14 165°C/W ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for - 55 <:: Tamb <:: 125 'C for UC184X , - 25 <:: Tamb <:: 85 'C for UC284X ; 0 <:: Tamb <:: 70 'C for UC384X ; V, = 15 V (Note 5) ; RT = 10 K ; C T = 3.3 nF) I UC184X 284X Test Conditions Parameter Symbol I Min.! Typ.! Max. I Unit UC384X I I ! Min.! Typ.! Max. ! REFERENCE SECTION VREF Output Voltage TJ '" V REF Line Regulation 12 V ,; Vi'; 25 V ~ 25 DC 10 ~ 1 mA Load Regulation 1,; 10 '; 20 mA '" VREF/"'T Temperature Stability (Note 2) Total Output Variation Line, Load, Temperature (Note 2) eN Output Noise Voltage 10Hz,; f ,; 10KHz TJ (Note 2) Long Term Stability T amb I" Output Short Circuit '" V REF ~ ~ 4.95 5.00 5.05 6 20 -30 5.10 V 6 20 mV 6 25 6 25 mV 0.4 0.2 0.4 mV/oC 5.1 4.82 50 125°C, 1000 Hrs (Note 2) 5.00 0.2 4.9 25°C 4.90 5.18 50 5 25 -100 -180 - 30 52 57 47 0.2 1 5 V ~V 25 -100 -180 mV mA OSCILLATOR SECTION Is V4 Initial Accuracy T J = 25°C (Note 6) Voltage Stability 12~Vi~25V Temperature Stability T MIN ~ T amb ~ T MAX (Note 2) Amplitude V PIN4 Peak to Peak 47 52 57 KHz 0.2 1 % 5 5 % 1.7 1.7 V ERROR AMP SECTION V2 Input Voltage Ib Input Bias Current V PIN1 = 2.5 V 2.45 AvoL 2~Vo~4V 65 2.50 2.55 - 0.3 - 1 2.42 90 65 2.50 2.58 - 0.3 -2 V IlA 90 dB Unity Gain Bandwidth (Note 2) 0.7 1 0.7 1 MHz Supply Voltage Rejection 12 ~ V, ~ 25 V 60 70 60 70 dB 10 Output Sink Current V PIN2 = 2.7 V VPIN1 = 1.1 V 2 6 2 6 mA 10 Output Source Current VPIN2 = 2.3 V VPIN1 =5 V VOUT High V PIN2 = 2.3 V; RL = 15 KQ to Ground V OUT Low V PIN2 =2.7 V; RL=15 Kn to Pin 8 B SVR - 0.5 - 0.8 5 - 0.5 - 0.8 6 0.7 5 1.1 mA V 6 0.7 1.1 V 3/8 933 UC1842/3/4/5-UC2842/3/4/5-UC3842/3/4/5 ELECTRICAL CHARACTERISTICS (continued) Parameter Test Conditions CURRENT SENSE SECTION Gv Gain (Notes 3 & 4) 2.85 3 3.15 2.8 3 3.2 V3 Maximum Input Signal VPIN1 = 5 V (Note 3) 0.9 1 1.1 0.9 1 1.1 Supply Voltage Rejection 12 ,; V, ,; 25 V (Note 3) SVR Ib 70 70 VN V dB Input Bias Current -2 - 10 -2 -10 ~A Delay to Output 150 300 150 300 ns ISINK 0.1 0.4 0.1 0.4 ISINK 1.5 2.2 1.5 2.2 OUTPUT SECTION IOL Output Low Level IOH Output High Level tr Rise Time = 20 rnA = 200 rnA ISOURCE = 20 rnA ISOURCE = 200 rnA CL = 1 nF Ti = 25°C 13 13.5 13 13.5 12 13.5 12 13.5 V V 50 150 50 150 ns 50 150 50 150 ns (Note 2) tf Fall Time Ti = 25°C CL = 1 nF (Note 2) UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min. Operating Voltage After Turn-on X842/4 15 16 17 14.5 16 17.5 X843/5 7.8 8.4 9.0 7.8 8.4 9.0 X842/4 9 10 11 8.5 10 11.5 X843/5 7.0 7.6 8.2 7.0 7.6 8.2 X842/3 93 97 100 93 97 100 X844/5 44 48 50 45 48 50 V V PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0 % 0 % TOTAL STANDBY CURRENT 1st Start-up Current 0.5 1 0.5 1 rnA I, Operating Supply Current VPIN2 = VPIN3 = 0 V 11 20 11 20 rnA Zener Voltage 1,=25mA 34 Viz Notes: 2. These parameters, although guaranteec, are not 100%testec in production. 3. Parameter measured at trip point of latch with VPIN2 = O. 4. Gai n definec as : A= dVPIN1 ;0,;VPIN,,,0.8V d VPIN3 5. Adjust V, above the start threshold before setting at 15 V. 6. Output frequency equals oscillator frequency for the UC1842 and UC1843. OUlput frequency is one half oscillator frequency for the UC1844 and UCI845. 4/8 934 34 V UC1842/3/4/5-UC2842/3/4/5- UC3842/3/4/5 Figure 1 : Error Amp Configuration. I 2.5V Error amp can source or sink up to O.5mA Figure 2 : Under Voltage Lockout. lee UC1842 UC1843 UClS44 UC1845 VON 16V 8.4V "OFF 10V 7.&11 During Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor 5KQ). 10 I Rr'C r ---i-i 4 I I : '~"H Cr I I l _ _ _ _ _ _ 1I 0.3 '-------'-------'----'----------'-----' 2.2 Figure 6 : Timing Resistance vs. Frequency. 4.7 10 22 Figure 7 : Output Saturation Characteristics. RT~~r-Tr'-Tr~-'rr--'-~~-. V(sat) (KnJ (V) f----t--+--H+tHt- 10 , , '0' 10' 10' 10' f (Hz) Figure 8 : Error Amplifier Open-loop Frequency Response. G_5781 . GV t" (dB) 80 60 -45 40 -90 20 _,35 -'80 '0 6/8 936 '00 'K 10K lOOK 1M f(HZ) !o (A) UC1842/3/4/5-UC2842/3/4/5-UC3842/3/4/5 I, i Figure 9 : Open Loop Test Circuit. i.. VREF COMP VFB • v, lW lKfi UC1842 OUTPUT OUTPUT ISENSE RTfC r GROUND ---~O GROUND Cr '--,______________________________~.~~_"_________________" ___J High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KQ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 10: Shutdown Techniques. l 1 COMP 3 iSENSE SHUTDOWN TO CURRENT SENSE RESISTOR 5-111111 Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method cause the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shut- down condition at pins 1and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling Vi below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset. 7/8 937 UC1842/3/4/5-UC2842/3/4/5-UC3842/3/4/5 Figure 11 : Off-line Flyback Regulator. ---------------------------- -- -- --- ------- '2 56"" 2W " '" "3 1... 3612 ' r--"---, t-R-{'=':J-'"-'IUlr--'-l~ -~ ~--l T4~F 2!)V J~F - J ,_ _ --L~_~~ 25'1 ~ • Q, ..-- UCI8~' "U1QJ\Q, " co "",F 600' R!llHQ C5 UOl .... 5GSPJ6i H0613 '--..----' R13 RWl 201';0 ,0.55.0 '~"""~--+- .. . "" 27K.Q , - ------------- - - - - - - Power Supply Specifications 1. Input Voltage: 95 VAC to 130 VAC (50 Hz/50 Hz) 2. Line Isolation: 3750 V 3. Switching Frequency: 40 KHz 4. Efficiency @ Full Load: 70 % 5. Output Voltage: A. + 5 V, ± 5 % : 1 A to 4 A load Ripple voltage: 50 mV P-P Max. g. + 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage: 100 mV P-P Max. C. - 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage: 100 mV P-P Max. Figure 12 : Slope Compensation. ~ Isense Rsense S-9461 A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50 %. 8/8 938 SLOPEC::LIB Note that capacitor, C, forms a filter with R2 to supress the leading edge switch spikes. UCN4801A BIMOS LATCH/DRIVERS ADVANCE DATA • HIGH-VOLTAGE, HIGH-CURRENT OUTPUTS • OUTPUT TRANSIENT PROTECTION • CMOS, PMOS, NMOS, TTL COMPATIBLE INPUTS • INTERNAL PULL-DOWN RESISTORS • LOW-POWER CMOS LATCHES the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. DESCRIPTION The UCN4801 A is a high-voltage, high-current latch/driver comprised of eight CMOS data latches, a bipolar Darlington transistor driver for each latch, and CMOS control circuitry for the common CLEAR, STROBE, and OUTPUT ENABLE functions. The bipolar/MOS combination provides an extremely lowpower latch with maximum interface flexibility. DIP-22 (Plastic) The CMOS inputs are compatible with standard CMOS, PMOS and NMOS circuits. TTL or DTL circuits may require the use of appropriate pull-up resistors. The bipolar outputs are suitable for use with relays, solenoids, stepping motors, LED or incandescent displays, and other high-power load. The unit feature open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will sustain at least 50 V in the OFF state. Because of limitations on package power dissipation, ORDER CODE: UCN4801ADP PIN CONNECTIONS (Top view) 22 21 3 20 4 19 5 18 6 17 8 15 16 9 14 10 13 11 12 1- Clear 2- Strobe 3- Input 1 4-lnput2 5- Input 3 6-lnput4 7 - Input 5 8- Input 6 9- Input 7 10- Input 8 11- GND 22 - Output enable 21- Vcc 20- Output 1 19- Output 2 18- Output 3 17 - Output 4 16- Output 5 15- Output 6 14- Output 7 13- Output 8 12- Common September 1988 1/4 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change withou1 notice. 939 UCN4801A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vo Output Voltage 50 V Vee Supply Voltage 18 V - 0.3 to Vee + 0.3 V mA VI Input Voltage Range Ie Continuous Collector Current 500 Power Dissipation' 2.0 W Ptot Top Operating Ambient Temperature Range - 20 to + 85 °C T stg Storage Temperature - 55 to + 125 °C • Derate atthe rate of 20 mrc above T,mb ~ + 25·C SCHEMATIC DIAGRAM Input N Common /----.-~ Output N Strobe Clear Outpu t enalje CONTROL 2/4 940 LATCH . DRIVER UCN4801A ELECTRICAL CHARACTERISTICS Tamb Symbol Parameter Output Leakage Current (Va Tamb ~ + 25 'C Tamb ~ + 70 'C 10 V OISa !) = + 25 ~ leelon) (each stage) leeloll) IR VF Note: V (unless otherwise specified) Min. Typ. Max. - - 50 100 0.9 1.1 1.3 1.1 1.3 1.6 Unit [LA - Collector-emitter Saturation Voltage 10 ~ 100 mA 10 ~ 200 mA 10 ~ 350 mA, Vee ~ 7 V V - - 13.5 8.5 3.5 Vee~5V-(note1) R'N = 5 50 V) Input Voltage Vec ~ 15 V Vee ~ 10 V Vila) V '(1 ) ae, Vee - 1 - - V KU Input Resistance Vee ~ 15 V Vee ~ 10 V Vee ~ 5 V 50 50 50 200 300 600 - Supply Current - Outputs Open Vee ~ 15 V Vee ~ 10 V Vee ~ 5 V All Drivers off, All Inputs ~ 0 V - 1 0.9 0.7 50 2 1.7 1 100 - - - 50 100 - 1.7 2 mA Clamp Diode Leakage Current (VR Tamb ~ + 25°C T amb ~ + 70°C Clamp Diode Forward Voltage IF ~ ~ 50 V) 350 mA [LA [LA V 1. Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to Insure the minimum logic '"["'. TRUTH TABLE Output INN Strobe Clear Enable t-1 t 0 1 0 0 OFF 1 1 0 0 X X X X X 1 X X OFF X 1 X OFF 0 0 0 ON ON X X x OUT N Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. ON irrelevant t-1 = previous output state t = present output state = 3/4 941 UCN4801A TIMING CONDITIONS ,--------------------------------------------------------- (Logic levels are Vcc and GND) Vcc = 5 V, Tamb + 25'C CLEAR-------------------------------- STROBE-----' ~~~~~~---4--+------+---~-------t-----J -• Er-- --'IIL__ OUTN _ _ _-' '-_ _ _ _ ~------------- - - - - - A. Minimum data active time before strobe enabled (data set-up time) tOO ns 100 ns 300 ns 500 ns 500 ns 300 ns 500 ns B. Minimum data active time after strobe disabled (data hold time) C. Minimum strobe pulse width D. Typical time between strobe activation and output on to off transition E. Typical time between strobe activation and output off to on transition F. Minimum clear pulse width G. Minimum data pulse width o~ II ~ f- 450 I « « 400 lor 2 !" 350 f- ...... E f- ~ 300 a: a: :> u a: 250 f- 200 0 ~ -' 0 150 u w -' «. '" 'g" -' '" 4/4 942 :\ 1'\1\1\ \ 1\r"\ '\, ~ll'- r-er-e- +-- 10 /fB 20 I J 30 3r'-4 I' r-I' r'-- "' ..... "'- Number of outputs conducting simultaneously I 100 0 I'-... l\.t\. r-e- ,... -""1"'> r-r--f'::: J 40 I .-J 50 60 70 PERCENT DUTY CYCLE 80 90 100 ---- I ------~ UEB4732 A.C. PLASMA PANEL DRIVER • 32-BIT SHIFT REGISTER WITH LATCHES • DECODING LOGIC CIRCUIT • LOW TO HIGH VOLTAGE INTERFACE FOR DIRECT CONNECTION TO 32 ELECTRODES DESCRIPTION UEB4732 is a BIMOS* IC's especially designed to provide selective and sustain signals needed by the X and Y electrodes of an A.C. plasma panel. Realizing a complete A.C. plasma panel control system requires only UEB4732 and two high voltage common amplifiers for rows and columns of the panel. The whole network is driven by a few CMOS logical signals. • Bipolar CMOS and complementary DMOS on same chip. 1-------· .- ----- --.- ··---·--1 DIP-40 (Plastic) i I I I ORDER CODE: UEB4732DP I I IL- _ _ _ _ J PIN CONNECTION Clock Inverting input Strobe Output 1 VCC1 01 Ground (logic) Output 32 Output 2 Output 31 Output 3 Output 30 Output 4 Output 29 Output 5 Output 28 Output 6 Output Il Output 7 Output 26 Output 8 Output 25 Output 9 Output 24 Output 10 Output 23 Output 11 Output Z2. Output 12 Output 21 Output 13 Output 20 Output 14 Output 19 Output 15 Output 18 Output 16 Output 17 VA3 September 1988 4 CMOS compatible logic inputs: 01, Clock, Strobe, Inv. 32 totem pole 100 V outputs, with clamping diodes to the VA2 and VA3 inputs. Logic supplies (Ground and VCC1) separated from hight voltage (VA2, VA3) to avoid disturbances. VA2 1/6 943 UEB4732 TYPICAL APPLICATION Power supply (Gnd, -I 12 V, + 100 V, - Logica) command 100 V) II , V U~B HV Power supply 4737 AMPLI Floating power A. supplV Translator . UEB F ..- I ~ ~ () ~ COLUMNS 4732 "I I 11 9 1 0 !J I c a 1 ~Vee UEB 4732 - VA3 .. I 9 01 a Clock ... Srrobe ..... 1 5 .. S -+ i 944 K 0 w = = ::: InV .... 216 To 32 electrodes - s n _ _ VA2 .. . A.C PLASMA PANEL UEB4732 ABSOLUTE MAXIMUM RATINGS Parameter _. Symbol VCC1 Logic Supply Voltage V A2 V A2 Voltage (V A2 V A3 V A3 Voltage ;" 18 ._-------------_._-- V A3) V --- 120 V 10 V ._-- - - - - - - - - - - ---- ... --------- - 0.3 to VCC1 + 0.3 Input Voltage Range Vi Unit Value V - - - - - - ------ ---_.- NOTE: Voltage values are with respect 10 network ground terminal (ground logic). SCHEMATIC DIAGRAM ,---------------------------------------~. Clock DI Invert ing mput Strobe VA2 VA3 1 Output , I) elp.(·, ndf'~ stage "----.... ....----~ ~---~---For 1 outpuT 31·blt shift register ELECTRICAL OPERATING CHARACTERISTICS (over recommended operating range) Symbol VOH VOL VOK fclock Parameter Min. Typ. Max. 5 10 20 10 V Low Level Dropout Voltage (for one output) V A3 = Ground - 10L = 10 mA -IOL = 20 (llA 5 10 10 20 V Dropout Clamp Voltage - 10 = ± 100 mA in One Output - 10 = ± 100 mA Simultaneously in the 32 Outputs Maximum Clock Pulse Frequency Unit V High Level Dropout Voltage (for one output) V A2 > 20 V -IOH=-10mA -loH=-20mA 2 3 4 8 MHz • All typical values are alVcc1= 12V, T"",= 25°C. 3/6 945 UE84732 RECOMMANDED OPERATING CONDITIONS (voltage values are referred to .logic ground of the Ie) Symbol Min. Parameter Vee Logic Supply Voltage VA2 V A2 Voltage (VA2 VA3 VA3 Voltage 10 10 ;0, VA3) Unit 15 V - 0.6 120 V - 0.6 10 Typ. Peak Current (for one output) - High Level VA2 > 20 V - Low Level VA3 = Ground - 20 20 Peak Clamp Current (for one output) ± 100 V mA Operating Free Air Temperature UEB4732 Tamb Max. 10 mA °C 0 + 70 FUNCTION TABLE Functions Data LOAD LATCH STROBE H i Strobe Latchs R32 L1 L2 L32 X X H L R1n R1n R31n R31n R1s R1s R2s R2s R32s R32s Levels at 01 through 032 depend on Inv. and strobe (see "strobe"). L H J. J. R1n R1n R2n R2n R32n R32n R1n R1n R2n R2n R32n R32n R1n - L H L H L L H H Levels at R1 through R32 depend only on data and clock (see "load"). R1s R1s R1 R1 R2s R2s R2 R2 R32s R32s R32 R32 R1s R2s R32s - - - l' l' X X X X H H X X X X X X X X L = Low level X J. = = Irrelevant High to low transition For the outputs. the high level (H) is VA2, the low level (L) is VA'. R1 ...... R32 R1 n.... R32n = Levels currently at internal outputs of shift register. = Levels at shift register outputs R1 through R32, respectively, before the most recent i transition of clock. R1 s .... R32s = Levels at shift register outputs R1 through R32, respectively, before the most recent transition of strobe (levels currenfly stored by the 32 latchs L 1 through L32). R1s ..... R32s 4/6 946 Outputs R2 H L Low to high transition Shift Register R1 Inv. = High level = Inputs Clock = Logical inversion of R1s ..... R32s. J. 01 R1n R1s L H 02 R2n 032 R32n R32n -- -- R2n R2s L H R32s L H UEB4732 SCHEMATIC OF ONE OUTPUT STAGE " - - - - - - - - - - - - - - - - - - - - - - _.. During the sustaining signal, VA2 = VA3 and the current flows through the two clamp diodes. ...---t---i> OUTPUT During the selective signals (write and erase on the plasma panel), VA2 is at high voltage (typ.1 00 V, referred to logic ground) VA3 is equal to logic ground, and the output is selectively adressed by complementary by DMOS stage. FROM LOGIC ------__~----------4_----~------VA3 DESCRIPTION The UEB4732 is designed to provide easily the line and the column select operation of a plasma display panel. For an use on the X axis of the panel, the Inv. input is set at a steady low level, the outputs are normally low and are selectively switched high when the strobe input is low. For an use on the Y axis of the panel, the Inv. input is set at a steady high level, the outputs are normally high and are selectively switched low when the strobe input is low (the 32 bit data is inverted). The Inv. input may also be used as a sustain input: when strobe is high, if the Inv. input is switched low, all outputs switch low, if the Inv. input is switched high, all outputs switch high. Data is enterred serially in the shift register, on the low to high level transition of clock. It is stored in the 32 latchs on the high to low level transition of strobe, so the outputs are stable during the low level of strobe, regradless of the state of clock and data, and a new data can be enterred immediately. The logical voltage reference (ground logic) and the high voltage reference (VA3) are separated to avoid disturbances. All output stages are complementary DMOS and contain clamp diodes to the VA2 and VA3 supply inputs. These diodes are designed to provide the peak current of the sustaining signal (typ. 100 mNoutput) without distorsion of the signal. 5/6 947 UEB4732 TIMING DIAGRAM TYPICAL OPERATIONG SEQUENCE 32 pulses r tit 32 pulses r",,--.;.tIt--_, "" UlJlJl ________ .r-LJ1JUl_________ Jr----,L Clock DI StrObe ::: } LJ m~de __________~/lL_________/L ::00 ,,---t OutpuT , , " \ + 100 V 0 V ~ VAJ _______ J ---------~ '---..,y--';/ Output Sustam Note: X mode circuits are referred to ground. Y mode ones are floating on sustaining voltage. In X mode, Inv. input is low. In Y mode, Inv. input is high. 6/6 948 ~ -------~ roode y VA> Write Erase v o:v ,'OOV ULN2001A-ULN2003A ULN2002A-ULN2004A SEVEN DARLINGTON ARRAYS These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal printheads and high power buffers. • SEVEN OARLINGTONS PER PACKAGE • OUTPUT CURRENT 500 mA PER DRIVER (600 mA PEAK) • OUTPUT VOLTAGE 50 V • INTEGRAL SUPPRESSION DIODES FOR INDUCTIVE LOADS • OUTPUTS CAN BE PARALLELED FOR HIGHER CURRENT • TTUCMOS/PMOSIDTL COMPATIBLE INPUTS • INPUTS PINNED OPPOSITE OUTPUTS TO SIMPLIFY LAYOUT The ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO-16) as ULN20010/20020/20030/20040. 1--------_._------------ 1 DESCRIPTION The ULN2001A, ULN2002A, ULN2003 and ULN2004A are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters. Each channel is rated at 500 mA and can withstand peak currents of 600 mAo Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. I I i I I I I 1 i DIP-16 Plastic : I (0.251 i I I I The four versions interface to all common logic families: ULN2001A General Purpose, DTL, TTL, PMOS, CMOS . _________ ~ ULN~002A~4-2~ V PMOS ULN2003A 5 V TTL, CMOS ULN2004A 6-15 V CMOS, PMOS ____I ~ _ I ORD::-~:JDES. I I JI ULN2001AJ2A/3AJ4A (DIP-16) ULN2001 D/2D/3D/4D (SO-16) I -~- ABSOLUTE MAXIMUM RATINGS -S--Y--~o-bO-I+-O-u-tP~tV~lt;ge ------ ~LA Il A Fig ---_.- 1 - Input Current for for for for Vi = 2-4 V Vi = 3.75 V V, =5 V Vi = 12 V ----_.- -_. - - - - - - - - - - - for ULN2064B VCE = 2 V VCE = 2 V for ULN2066B VCE = 2 V VCE = 2 V Input Voltage Turn - on Delay Time 0.5 Vi to 0.5 Vo tpHL Turn - off Delay Time 0.5 Vi to 0.5 Vo IR Clamp Diode Leakage Current for ULN2064B V R = 80 V VR = 80 V Clamp Diode Forward Voltage 35 1-1 1-2 1.3 1-4 - V -V V V V ... 4.3 9.6 1.8 5-2 r----- mA mA mA mA -- Ic = 1 A Ic=15A 2 2.5 V V Ic = 1 A Ic=15A 65 10.._- -- 1-4 3.3 0.6 1.7 ~ ... _- -- - - - - r- ------- - --- -------~--- ULN2064B ULN2064B ULN2066B ULN2066B tpLH VF - Typ. .-~-. for ULN2064B ULN2066B Ic=100mA Vi = 0-4 V --------Ic = 500 mA Is =6251lA Ic = 750 mA Is = 935 IlA Is = 1-25 mA Ic = 1 A Ic = 1.25 A Is = 2 mA --- Vi(on) --,----Min. -- - - - - - - - - " - - - - - - - - - - - --- --. --- Output Leakage Current for ULN2064B - ULN2066B VCE =50 V VCE =50 V T amb = 70°C VCE(sus) li(on) - Test Conditions 1 - - - - r----1.5 --- 2 ---- - 3 ---- -- 4 .. _-"- 5 V V - - r----Il s Il s ULN2066B T amb = 70°C -- IF = 1 A IF = 1.5 A - 50 100 - - -1.75 2 Il A Il A 6 V V 7 Noles: 1. Input voltage is with reference to the substrate (no connection to any other pins) for the ULN2074B and ULN2076B reference is ground for all other types. 2. Input current may be limited by maximum allowable input voltage. SCHEMATIC DIAGRAM ..-----+---(') C B I I ~ 5-5922 ULN2068B : RIN = 2.5 kQ ULN2070B : RIN = 11.6 kQ Rs= 9000 Rs= 3-4 KHO 3/8 955 ULN2064B-ULN2066B-ULN2068B-ULN2070B-ULN2074B-ULN2076B ELECTRICAL CHARACTERISTICS (V s = 5 V for ULN2068B, V s = 12 V for ULN2070B, Tamb = 25 "C unless otherwise specified) Symbol ICEX Parameter Min, Test Conditions Output Leakage Current for ULN2068B - ULN2070B VCE =50 V T amb = 70 DC VCE =50 V VCE(suS) Collector-emitter Sustaining Voltage for ULN2068B - ULN2070B Ic = 100 mA Vi = 0.4 V VCE(sa!) Collector-emitter Saturation Voltage for ULN2068B Ic =500 mA Ic = 750 mA Ic = 1 A Ic = 1.25 A for ULN2070B Is =500 mA = 750 mA Is = 1 A = 1.25 A Vi Vi Vi Vi = 2.75 = 2.75 = 2.75 =2.75 Vi Vi Vi Vi =5 =5 =5 =5 ULN2068B ULN2068B ULN2070B ULN2070B Vi Vi Vi Vi '8 '8 li(on) Vi(on) Is for for for for Input Current Input Voltage VCE = 2 V for ULN2068B for ULN2070B tpLH Turn-on Delay Time 0.5 Vi to 0.5 Vo tpHL Turn-off Delay Time 0.5 Vi to 0.5 Vo Clamp Diode Leakage Current Clamp Diode Forward Voltage IR VF Fig 100 500 ~A ~A 1 V 2 V V V V V V V V 1.1 1.2 1.3 1.4 V V V V =2.75 V =3.75 V =5 V = 12 V 550 1000 400 1250 ~A ~A ~ 4 2.75 5 V V 5 6 mA 4.5 mA 2 ~A Ic = 1.5 A 8 1 ~s 1.5 ~s for ULN2068B - ULN2070B VR = 50 V VR = 50 V T amb = 70 DC 50 100 ~A ~A 6 IF = 1 A IF = 1.5 A 1.75 2 V V 7 Ic = 1.25 A ~-....--oc B E S-5921. ULN2074B : RIN = 350 Q ULN2076B : RIN = 3 kQ 956 Unit 1.1 1.2 1.3 1.4 V V V V SCHEMATIC DIAGRAM 4/8 Max. 35 for ULN2068B Ic =500 mA Vi = 2.75 V for ULN2070B Ic =500 mA Vi =5 V Supply Current Typ, ULN2064B-ULN2066B-ULN2068B-ULN2070B-ULN2074B-ULN2076B i ELECTRICAL CHARACTERISTICS (T amb Symbol . I CEX Parameter Output Leakage Current I ----~~--- = 25 "C unless otherwise specified) for ULN20748 - ULN20768 VCE=50V VCE = 50 V T amb- = 70 "C -- 35 VCE(sus) Collector-emitter Sustaining Voltage for ULN20748 - ULN20768 V, = 0.4 V Ic = 100 mA VCF(sat) Collector-emitter Saturation Voltage Ic Ic Ic Ic for for for for Input Current l'lon) = = = = 500 mA 750 mA 1 A 1.25 A ULN20748 ULN20748 ULN20768 ULN20768 for ULN20748 VCE = 2 V VCE = 2 V for ULN20768 VCE = 2 V VCE = 2 V Input Voltage V1(on) I Min. _0_- Test Conditions tpLH .1 Turn-on Delay Tim-; 0.5 V, to 0.5 Vo tpHL Turn-off Delay Time 0.5 V, to 0.5 Vo 18 18 18 18 =625 [lA = 935 [lA = 1.25 mA = 2 mA V, Vi V, Vi = 2.4 V =3.75 V =5 V = 12 V ~~1":J~1 --U---r -.. Typ. - -- ffl~ 1.1 I 1 I 1 -+---1.4 - - - - V 1.2 1.3 1.4 V V V I --- - -_.- 4.3 9.6 1.8 5.2 mA mA mA mA Ic = 1 A Ic=1.5A 2 2.5 V V Ic = 1 A Ic = 1.5 A 6.5 10 V V 1 [ls i I ! i 3.3 0.6 1.7 ' 3 ' --- 4 --1---- .---- .L..1~ 5 [ls ---- TEST CIRCUITS Figure 1. Figure 2. I I--------;p~---~I I : I I ! 1 Figure 4. Figure 3. I OPEN OPEN 1 I OPEN Ie I L -_ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ __ l 5-1966 5/8 957 i I. '" I ULN2064B-ULN2066B-ULN2068B-ULN2070B-ULN2074B-ULN2076B Figure 6. Figure 5. OPEN ,.,A OPEN~ 0- V-- 5-5721 __ Figure 7. FigureS. Figure 9 : Input Current as a Function of Input Voltage. Figure 10 : Input Current as a Function of Input Voltage. 15 6/8 958 2.0 2.5 3.0 3.S 4_0 4.!J 5.0 Vj(VJ 10 11 ULN2064B-ULN2066B-ULN2068B-ULN2070B-ULN2074B-ULN2076B Figure 11 : Collector Current as a Function of Input Current. Ie (AI 1.5 ~ --+ ~. MAXIMUM REQUIRED I, I . - L j I UlN 2064/66B ULN 207411681 - ~T=r-t=~ 0.5 J 1.0 I 20 TYPICAL APPLICATIONS Figure 12: Common-anode LED Drivers. Figure 13: Common-cathode LED Drivers. If;n,fl~l/t~,t/, "U,tlf/f; / i I _____ J 7/8 959 ULN2064B-ULN2066B-ULN2068B-ULN2070B-ULN2074B-ULN2076B MOUNTING INSTRUCTIONS The Rthj-amb can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 14) or to an external heatsink (Fig. 15). During soldering the pins temperature must not exceed 260 'C and the soldering time must not be longer than 12 seconds. The diagram of figure 16 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side "a" of two equal square copper areas having a thickness of 35 Jl (1.4 mils). The external heatsink or printed circuit copper area must be connected to electrical ground. Figure 14: Example of P.C. Board Copper Area which is Used as Heatsink. (OPPER AREA 3'J)J Figure 15: External Heatsink Mounting Example. THICKNfSS I ~ P. c. BOARD Figure 16: Maximum Dissipable Power and Junction to Ambient Thermal Resistance vs. Side "a". Figure 17 : Maximum Allowable Power Dissipation vs. Ambient Temperature. G 3558 G 1559 \1 ~/'\ 7~ . .)... 22- ".>.. ~7 ~ ,,.. --+--+---+- + m~ .~ '2: -I-- _- .:. ...~" ~./, "'1>, _A ~ --+-+-~~ ~ f-'- ~I '/~ '''S~L --:p=~+ -~ -~ffii-;' -'--r,---'-1 1 "I-. -1- 10 8/8 960 20 30 .t,O I (mm) -50 50 ~ 100 Tamb("C) ULN2065B ULN2067B ULN2069B ULN2071 B ULN2075B ULN20778 80 V - 1.5 A QUAD DARLINGTON SWITCHES tible with 6-15 VCMOS and PMOS. The ULN2069B and ULN2071 B include a predriver stage to provide extragain, reducing the load on control logic. • OUTPUT CURRENT TO 1.5 A EACH DARLINGTON • MINIMUM BREAKDOWN 80 V • SUSTAINING VOLTAGE AT LEAST 50 V • INTEGRAL SUPPRESSION DIODES (ULN2065B, ULN2067B, ULN2069B and ULN2071B) • ISOLATED DARLINGTON PINOUT (ULN2075B and ULN2077B) • VERSIONS COMPATIBLE WITH ALL POPULAR LOGIC FAMILIES '- --~-- - .. DESCRIPTION Designed to interface logic to a wide variety of high current, high voltage loads, these devices each contain four NPN darlington switches delivering up to 1.5 A with a specified minimum breakdown of 80 V and a sustaining voltage of 50 V. The ULN2065B, ULN2067B, ULN2069B and ULN2071 B contain integral suppression diodes for inductive loads and have common emitters ; the ULN2075B and ULN2077B feature isolated darlington pinouts and are intended for applications such as emitter follower configurations. Inputs of the ULN2065B, ULN2069B and ULN2075B are compatible with popular 5 V logic families and the ULN2067B, ULN2071 Band ULN2077B are compa- - -,---,-~--,-- - ----- POWERDIP 12 + 2 + 2 PIN CONNECTIONS AND ORDER CODES ,---------~ - .. ~-~~,----,~,-----,- - - - - ~~---'---- : :_~tTIT:: : I, e J GND ~ 0"; I . 1 I - J..I B 6~ir I' JjL_ C B 1~ Vs 13 GND " G," ,,7 C ULN2065B ULN2067B September 1988 ULN2069B ULN2071 B " ULN2075B ULN2077B 1/8 961 ULN2065B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2077B ABSOLUTE MAXIMUM RATINGS ~SymbOI - - - Parameter f~ VCEX Output Voltage I VCE!sus) Output Sustaining Voltage I 10 Output Cu rrent \ Vi Input Voltage II Vs Input Current Supply VoltaQ'efo;--ULN2069S------------ Ii __--+-Ptot Value Unit i 80 V 50 V 1.75 A for ULN2075B - 2077B 60 for ULN2067B - 2071 B 30 __ ~0~~~0~E3. ____206~B_ _ _ _ _ _ _ _ _ _ _ _ ~___ I ~. I I - 1-- forULN2071B_________ ____ i Power Dissipation: at T pins = 90°C \ at T amb = 70°C V V V I 25 10 mAl V ~ 4.3! 1 I W W . ~O _____ +-_V_~ I T amb [Operating Ambient Temperature Range - 20 to 85 I °C I T stg [Storage Temperature - 55 to 150 \ °C I SCHEMATIC DIAGRAM ,--------------------------------------- /"'----+---0 c B ULN2065B : RIN = 350 Q ULN2067B : RIN = 3 kQ 2/8 962 " ULN2065B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2~ ELECTRICAL CHARACTERISTICS (T amb = 25 'C unless otherwise specified) Symbol ICEX VCE(sus) li(on) Vi(on) Min. for ULN20658 - ULN20678 VCE = 80 V VCE =80 V Tamb = 70 'C Collector-emitter Sustaining Voltage . , VCE(sal) Test Conditions Parameter Output Leakage Current for ULN20658 - ULN20678 Ic = 100 mA Vi = 0.4 V Typ.1 Max. I U~itT~~ ~lA 100 500 flA 1.1 1.2 1.3 1.4 V V V V 50 V Ic = 500 mA 18 = 625 ~A Ic = 750 mA 18=935~A Ic = 1 A 18 = 1.25 mA Ic = 1.25 A 18 = 2 mA for ULN20658 - ULN20678 Ic = 1.5 A 18 = 2.25 mA Collector-emitter Saturation Voltage Input Current for for for for for ULN·20658 VCE = 2 V VCE = 2 V for ULN20678 VCE = 2 V VCE = 2 V Input Voltage 1.5 V mA mA mA mA 4 Ic = 1 A Ic = 1.5 A 2 2.5 V V 5 Ic = 1 A Ic = 1.5 A 6.5 10 V V 1.4 3.3 0.6 1.7 0.5 Vi to 0.5 Vo 1 ~s 0.5 Vi to 0.5 Vo 1.5 ~s Clamp Diode Leakage Current for ULN20658 - ULN20678 V R = 80 V VR = 80 V T amb = 70 'C 50 100 ~A Clamp Diode Forward Voltage IF = 1 A IF = 1.5 A 1.75 2 V V VF 3 4.3 9.6 1.8 5.2 ULN20658 Vi = 2.4 V ULN20658 Vi = 3.75 V ULN20678 Vi =5 V ULN20678 Vi = 12 V Turn-on Delay Time IR 2 ------.-~---.- tpHL ..... :rul"n-off D~lay Time tpLH ! _- ~A 6 7 ----_. ------_. -------_ .. Notes: 1. Input voltage is with reference to the substrate (no connection to any other pins) for the ULN2075B and ULN2077B refe· renee is ground for all other types. 2. Input current may be limited by maximum allowable input voltage. ._.----- SCHEMATIC DIAGRAM B ~--+----() : C I ....* I I 5-5922 ULN2069B : RIN = 2.5 KQ, ULN2071 B : RIN = 11.6 KQ, Rs= 900Q Rs = 3.4 KQ 3/8 963 35B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2077B _ECTRICAL CHARACTERISTICS (V s = 5 V for ULN2069S, Vs = 12 V for ULN2071 S, T amb = 25 'C unless otherwise specified) Symbol ICEX Parameter Output Leakage Current Test Conditions Min. for ULN2069B - ULN2071 B VCE=80V VCE=80V T amb = 70°C VCE(sus) Collector-emitter Sustaining Voltage for ULN2069B - ULN2071 B Ic=100mA Vi = 0.4 V VCE(sat) Collector-emitter Saturation Voltage for ULN2069B Ic=500mA Ic = 750 mA Ic = 1 A Ic = 1.25 A Ic = 1.5 A for ULN2071 B Ic=500mA Ic = 750 mA Ic = 1 A Ic =1.25A Ic = 1.5 A li(on) Vi(on) Is Input Current Input Voltage Supply Current for for for for ULN2069B ULN2069B ULN2071 B ULN2071 B 100 500 IlA IlA 1 V 2 1.1 1.2 1.3 1.4 1.5 V V V V V 2 = 2.75 =2.75 = 2.75 =2.75 =2.75 V V V V V Vi Vi Vi Vi Vi =5 =5 =5 =5 =5 V V V V V 1.1 1.2 1.3 1.4 1.5 V V V V V Vi Vi Vi Vi = 2.75 V =3.75 V =5 V = 12 V 550 1000 400 1250 IlA IlA IlA IlA 4 2.75 5 V 5 6 mA 4.5 mA 8 1 !lS !lS for ULN2069B - ULN2071 B VR = 80 V VR = 80 V Tamb = 70°C 50 100 IlA IlA 6 IF = 1 A IF = 1.5 A 1.75 2 V V 7 0.5 Vi to 0.5 Vo Turn-off Delay Time 0.5 Vi to 0.5 Vo Clamp Diode Leakage Current Clamp Diode Forward Voltage Ic = 1.25 A SCHEMATIC DIAGRAM ___---.,--0 c E 5-5924 ULN2075B : RIN = 350 n ULN2077B : RIN = 3 kn 964 Fig. 1.5 Turn-on Delay Time 4/8 Unit Vi Vi Vi Vi Vi for ULN2069B Ic = 500 mA Vi = 2.75 V for ULN2071 B Ic = 500 mA Vi =5 V tpHL VF Max. 50 Ic = 1.5 A VCE =2 V for ULN2069B for ULN2071 B tpLH IR Typ. ULN20658-ULN20678-ULN20698-ULN20718-ULN20758-ULN20778 ELECTRICAL CHARACTERISTICS (T amb Symbol IcEX Parameter = 25 'C unless otherwise specified) Test Conditions Output Leakage Current Min. for ULN2075B - ULN2077B VeE = 80 V VeE =80V T amb = 70 'C VeE(,Us) Collector-emitter Sustaining Voltage for ULN2075B - ULN2077B Ic=100mA Vi = 0.4 V VeE(,at) Collector-emitter Saturation Voltage Ic = 500 mA 18 = 625 f.lA Ic = 750 mA 18 = 935 IlA 18 = 1.25 mA Ic = 1 A Ic = 1.25 A 18 = 2 mA for ULN2075B - ULN2077B Ic = 1.5 A 18 = 2.25 mA li(on) Input Current for for for for V,(on) Input Voltage for ULN2075B VeE = 2 V VCE = 2 V for ULN2077B VeE = 2 V VCE = 2 V ULN2075B ULN2075B ULN2077B ULN2077B Typ. Max. Unit Fig. 100 500 f.lA f.lA 1 V 2 1.1 1.2 1.3 1.4 V V V V 3 50 1.5 V 4.3 9.6 1.8 5.2 mA mA mA mA Ie = 1 A Ie = 1.5 A 2 2.5 V V Ic = 1 A Ie = 1.5 A 6.5 10 V V V, V, V, Vi = = = = 2.4 V 3.75 V 5 V 12 V 1.4 3.3 0.6 1.7 4 5 tpLH Turn-on Delay Time 0.5 Vi to 0.5 Va 1 f.ls tpHL Turn-off Delay Time 0.5 Vi to 0.5 Va 1.5 f.lS TEST CIRCUITS Figure 2. Figure 1. OPEN Figure 4. Figure 3. OPE.N OPEN OPEN 5-5927 5/8 965 ULN2065B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2077B Figure 5. Figure 6. l I I i I I _J Figure 7. Figure 8. I _J Figure 9 : Input Current as a Function of Input Voltage. I, .--r--r--'--.--'---'~~~ (rnA) Figure 10 : Input Current as a Function of Input Voltage. I; (rnA) 14 7 J_ ULN 20678 UlN 20778 12 10 1.5 6/8 966 20 2.5 3.0 ].5 4.0 4.~ 5.0 Vi{V) 10 11 V I (V) ULN2065B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2077B Figure 11 : Collector Current as a Function of Input Current. Ie tAl ~~-~--~--e--+--+--+- 1.5 1.0 0.5 1.0 2.0 ).0 I, (mAl MOUNTING INSTRUCTIONS The Rth j-amb can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board (Fig. 12) or to an external heatsink (Fig. 13). During soldering the pins temperature must not exceed 260°C and the soldering time must not be longer than 12 seconds. The diagram of figure 14 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side "oc" of two equal square copper areas having a thickness of 35 Il (1.4 mils). The external heatsink or printed circuit copper area must be connected to electrical ground. Figure 12: Example of P.C. Board Area which is Figure 13: External Heatsink Mounting Example. Used as Heatsink. (OPPER P AREA ]5}' THICKNESS c. BOARD ~ ..'1' SGS-niOMSON 7/8 I&iD©OOlll!.rn~OO@IlID©$ 967 ULN2065B-ULN2067B-ULN2069B-ULN2071 B-ULN2075B-ULN2077B Figure 14: Maximum Dissipable Power and Junc- Figure 15: Maximum Allowable Power Dissipa- tion to Ambient Thermal Resistance vs. Side "I". Ptot tion vs. Ambient Temperature. G lS59 r--r-,----,---,--,-r--r-.,-''''T''-J Rt h (W) ,\\t (-CfW) -+- -+--+--1 80 '\''''~-S-I I\~~ -~ l 20 t1f + 10 8/8 968 20 30 .t,O I (mm) ~ :,~~ ~ ~r "~;te~~..,.,, 't "'"'It,. 60 -50 1 . ~ '1J,a-"P. ~~ . -+ r "':{;, K'" ~ ~1t Hl' r.;~ 50 100 Tamb<-C) ULN2801A ULN2802A ULN2803A ULN2804A ULN2805A EIGHT DARLINGTON ARRAYS • EIGHT DARLINGTONS WITH COMMON EMITTERS • OUTPUT CURRENT TO 500 mA • OUTPUT VOLTAGE TO 50 V • INTEGRAL SUPPRESSION DIODES • VERSIONS FOR ALL POPULAR LOGIC FAMILIES • OUTPUT CAN BE PARALLELED • INPUTS PINNED OPPOSITE OUTPUTS TO SIMPLIFY BOARD LAYOUT the ULN2804A has a 10.5 KQ input resistor for 6-15 V CMOS and the ULN2805A is designed to sink a minimum of 350 mA for standard and Schottky TTL where higher output current is required. All types are supplied in a 18-lead plastic DIP with a copper lead from and feature the convenient input-opposite-output pinout to simplify board layout. DESCRIPTION The ULN2801 A-ULN2805A each contain eight darlington transistors with common emitters and integral suppression diodes for inductive loads. Each darlington features a peak load current rating of 600 mA (500 mA continuous) and can withstand at least 50 V in the off state. Outputs may be paralleled for higher current capability. Five versions are available to simplify interfacing to standard logic families: the ULN2801 A is designed for general purpose applications with a current limit resistor; the ULN2802A has a 10.5 KQ input resistor and zener for 14-25 V PMOS ; the ULN2803A has a 2.7 KQ input resistor for 5 V TTL and CMOS; DIP-18 (Plastic) ' - - - - - - - - - - - - - ---.-........! CONNECTION DIAGRAM (top view) I IN 1 1 18 OUT 1 IN 2 2 17 OUT 2 IN 3 3 16 OUT 3 IN 4 4 15 OUT 4 IN 5 5 14 OUT 5 IN 6 6 13 OUT 6 -- 7 IN 8 11 9 '() COMMON FREE GND I I IN 7 8 I r"""1-t--i1'2 OUT 7 OUT B WHEELING OIOO£S 5-)1.90/1 I I ~ '-------------------------------_._------_.- September 1988 1/6 969 UlN2801 A-U lN2802A-U lN2803A-UlN2804A-U lN2805A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Output Voltage 50 Vi Input Voltage for ULN2802A, 2803A, 2804A for ULN2805A 30 15 Ie Continuous Collector Current 500 18 Continuous Base Current 25 Ptot - .- . ~.-,--,---~ ~.-- I .. - 20 to 85 Operating Ambient Temperature Range T stg I I I I 1,0 2.25 Power Dissipation (one Darlington pair) (total package) Tamb r---.1-- i i Value Vo I I .--~~~. - 55 to 150 Storage Temperature Range ~--.~--. Unit V V V mA mA W W °C °C SCHEMATIC DIAGRAM AND ORDER CODES For ULN2802A (each driver for 14-15 V PMOS) For ULN2801A (each driver for PMOS-CMOS) r -JIoI-----<)COM ,, L_,... ________ _ L._~~~~~~~~~ _ _ _ _ _ J I For ULN2803A (each driver for 5 V, TTUCMOS) For ULN2804A (each driver for 6-15 V CMOS/PMOS I 2.7kn INO----r-------c:::J- - T<-----.------+/ -,--I:.., : i : L~o~o~ ... ,. EACH DRIVER -1~ _~ 1 '''"' EACH DRIVER For ULN2805A (each driver for high out TTL) -~-l 2/6 970 -Ji+--{)COM 'N~~~O I,~I'"0-1J-I -"T--{)our __ ~-}-- I __J VO "' ULN2801A-ULN2802A-ULN2803A-ULN2804A-ULN2805A THERMAL DATA ~-ambl T~ermal Resistance Ju~;ionamb~n; ------------------------ ELECTRICAL CHARACTERISTICS (T amb - i ---,---- --------,.- Output Leakage Current --- 1-- - - - - -- Collector-emitter Saturation Voltage ---- - ---------.-.---- -- - Input Current VCE = 50 V T amb = 70 cC T amb = 70 °C for ULN2802A VCE = 50 V for ULN2804A VCE=50V I - - for ULN2805A Ic = 500 flA i Input Voltage for ULN2802A VCE = 2 V for ULN2803A VCE = 2 V VCE = 2 V VCE = 2 V for ULN2804A VCE = 2 V VCE = 2 V VCE = 2 V VCE = 2 V for ULN2805A VCE = 2 V ] ] I I] I I hFE Ci DC Forward Current Gain for ULN2801A VCE = 2 V - = 17 V = 3.85 V =5 V = 12 V =3 V -- 0.35 093 1 1.5 - - ------ 50 U" 0.5 1.45 2.4 1- 1b - 2 mA mA mA mA mA 3 Il A 4 - - -f - - - - ,---- I Ic = 300 mA 13 V Ic = 200 mA Ic = 250 mA Ic = 300 mA 2.4 2.7 3 V V V 5 6 7 8 V V V V 5 Ic Ic Ic Ic 125 =200 = 275 = 350 = mA mA mA mA Ic = 350 mA V 2.4 - - I 1000 Ic = 350 mA - 2 pF - fls - 1 ~IS - 50 100 Il A IlA 6 2 V 7 ! 15 tpLH Turn-on Delay Time 0.5 Vi to 0.5 Va tpHL Turn-off Delay Time 0.5 Vi to 0.5 Va 0.25 Clamp Diode Leakage Current VR = 50 V Tamb = 70 DC Clamp Diode Forward Voltage IF = 350 mA VF 1b -- 1.25 I 25 0.25 I 1 IR flA V V V --- ------ 65 - 1.1 1.3 1.6 ------- 0.82 500 --- 0.9 1.1 1.3 ---------------- T amb = 70°C Vilon) ---- - IB = 250 flA IB = 350 flA IB =500 flA Input Current I ~IA 500 I ] V, = 1 V ~(Off] ] ' 1 V, = 6 V -----.---- for ULN2802A for ULN2803A for ULN2804A I I I l I i(on) :~~~rTr':1 Min;i-iyp. VCE = 50 V - - ------- - - . , - -- - - - Ic = 100 mA Ic = 200 mA Ic = 350 mA ... ------ Vi Vi Vi Vi Vi ) I -55 ---~-;'C!WJ 25 'C unless otherwise specified) Test Conditions --_.----,-- I VCE(sa!] = --- Parameter isymbol I CEX - u-M~=_=---- Input Capacitance VR = 50 V ------_·_--1 1.7 I I 3/6 971 ULN2801A-ULN2802A-ULN2803A-ULN2804A-ULN2805A TEST CIRCUITS Figure 1a. Figure 1b. --.-----------------~ Figure 2. Figure 3. CX'EN I OPEN I I l_ _ Figure 4. OPEN Figure 5. 1 - "2 ··f · L I ..,."" - - - - - - " - - " - - - - - -_ _ _ -._0 _ _ - Figure 6. -----l I I I S· '5727 ! ~----------------~ 4/6 972 Figure 7. 1-I J --------------, U LN2801 A-ULN2802A-U LN2803A-U LN2804A-ULN2805A Figure 8 : Collector Current as a Function of Saturation Voltage. Figure 9 : Collector Current as a Function of Input Current. I,.--'---r--.--'---r--~~~, (mA) 600 400f---+-++-+-----t---+--fL--+-+-+-;f--j 400 200 05 200 10 Figure 10 : Allowable Average Power Dissipation as a Function of Ambient Temperature. It-- 2.0 r\\ - (rnA) 300 \~. (;..~- 10 - -+i +-+-+--+-+-1- \ I 150 100 10 Figure 12 : Peak Collector Current as a Function of Duty. I I T3mh=50'C 400 30 o REcaMMENaE; \. }- "" \AZ~\~~'!!." ~ >-. ~ ~ ~g~g~~T~GOUTP~ SIMULTANEOUSLY 200 ]0 40 50 I; ~l-rT\}~ 1I 10 "- ~ t': " "- t...... :---... ~ I I t--- r----.. r----.. DUTY CVCLE(°/ol / 1- V 1.0 0.5 -- r-- L' "/ 15 ~ I 60 Figure 13 : Input Current as a Function of Input Voltage (for ULN2802A). (mA --- 1\\\ r 100 ~+--+--t-+-+ \ 50 500 f--+---+--+--"I.-"'<-f'" - \ 0.5 I ~+-~t\--'I-'I+'..-+--"~--+-__f-"o,J- '00 \ 15 Figure 11 : Peak Collector Current as a Function of Duty Cycle. 'C DIEV!C~ lI~1T wo V V 9 ./ ./ "" q'<-~ ~, ./ V ./ V./ I I 20 '0 60 DUTY CYCLE("I.) 12 14 16 ,e 20 22 24 Vi (V) 5/6 973 ULN2801A-ULN2802A-ULN2803A-ULN2804A-ULN2805A ---------------------------------------Figure 14 : Input Current as a Function of Input Voltage (for ULN2804A) (mA 'f--l -J- - Ii I -T -- i -- - - (mA -- L / V f---'0 V k..-' ~~ - - - ';-.0- r------- ,/ I. '5 r------- ,/ ~" ,-<~y .L, ~ ~~ c /]~~ ~ 10 --- - I--- 11 20 Figure 16 : Input Current as a Function of Input Voltage (for ULN2805A) , 4.0 3.5 .A1 3.0 A ~~ ~. ~~~ ~ ~\\-~, ~~ \\' ~\~ AREA Of NORMAL /' ~ ~ OPERATION WITH "\\' - 10 '5 . 1.0 V.J./ 0.5 1.5 6/6 974 1.0 -- r- :-:- -~ . 10 15 I f ~ ~'I" 05 L I / I- - (mA I "\-./ -I'~ -- .~ r--- 05 , 10 I 1.5 -- Figure 15 : Input Current as a Function of Input Voltage (for ULN2803A) STA,NDARD OR SCHOTTKY TTL 1.5 3.0 3.5 II I (v) 25 30 35 40 45 50 55 60 Vi (V) ULQ2001 R/2R ULQ2003R/4R SEVEN DARLINGTON ARRAYS - - - - -- - - - -----------_.-- -------------------- • SEVEN DARLINGTONS PER PACKAGE • OUTPUT CURRENT 500 mA PER DRIVER (600 mA PEAK) • OUTPUT VOLTAGE 50 V • INTEGRAL SUPPRESSION DIODES FOR INDUCTIVE LOADS • OUTPUT CAN BE PARRALLELED FOR HIGHER CURRENT • TTUCMOS/PMOSfDTL COMPATIBLE INPUTS • INPUTS PINNED OPPOSITE OUTPUTS TO SIMPLIFY LAYOUT DESCRIPTION - ~ ..-.L;.:. ....... -... '- ... DIP-16 Ceramic \ --------l PIN CONNECTION The ULQ2001 R, ULQ2002R, ULQ2003R and ULQ2004R are high voltage, high current darlington arrays each containing seven open collector darlington pairs with common emitters. Each channel is rated at 500 mA and can withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. IN 1 1 16 >o-~-t--j1\5 I OUT 1 IN 2 2 IN 3 3 >o-~-t--j114 OUT 3 IN 4 4 .:>o-~--t--f113 OUT 4 IN 5 5 >o-~-t--jI12 OUT 5 IN 6 6 .:>o-~-t--fl" OUT 6 IN 7 7 X>-~-+-~I'O OUT 7 OUT 2 The four versions interface to all common families. ' lJL02001 R :_ Gen~ral pu.rpose, DTl, TTL, CMOS Ul02002R ' 15-25 VPMOS ~ Ul02()03R _~2..\1.!2S.c;rv1..<:l~ I i ____________ I _Ul020.t:tl-F:::- l I Current Tamb = 70°C I I I I I iV;;-;/:~le~tor-emitter I Saturation Voltage ___ ~~_~ f- i I'/on) I Input Current I I ___ ---I- ___ I Gain - C,_. - Input Capacitance - - - - _. . _-_._- tpLH tPH~_ V, = 1 V 500~_ Y~___L __ ~ IB = 250 >tA 0.9 1.1 I B = 350 IlA I ! 1.1 1.3 IB=500IlA.l- ____ f_1.~_+1~6 for U LQ2002R for ULQ2003R V, = 17 V V, = 3.85 V ~r =~~~OO~R_~,~~ V V CE=2V VCE = 2 V VCE = 2 V IR VCE =2 V Turn-on Delay Time I I Clamp Diode Leakage i I I 1.25 1.35 >tA 1b 2 2 I __ 2__.J mA mA 10~-4 _;~ I I 3 3 .1-; 50 ----L~_+___-_-: _.J:l.~_1__ ~_J I ! Ic=300mA 13 V 15 I Ic = 200 mA Ic = 250 mA Ic = 300 mA 2.4 2.7 3 V V V 5 5 : 5 IC=125mAtt Ic = 200 mA Ic = 275 mA 5 I 6 7 8 I I ____ -'~_ 2 Ic =350 mA 11000 ' ._- ---- 0.82 0.93 I Ic = 500 IlA 0.5 V, to 0.5 Vo - +Tljrn-of!.Delay Time I Ic = 100 mA Ic = 200 mA Ic=350mA _._- .... i 1a I f--..-.-.-t--~--.--.-~~---+-'Ic5- = 2....V. __ ~~5~A hFE DC Forward Current for ULQ2001 R ,-_. I 500 VCE=2V i for ULQ2003R I VCE = 2 V I VCE = 2 V I VCE = 2 V I for ULQ2004R I I I >tA V,=6V I Input Current I T amb = 70 'C vi;:,~-I-I~~tV~~;-~--TI.fur-ULQ2002R : I I 100 I T amb = 70°C for ULQ2002R VCE=50V for ULQ2004R VCE = 50 V I'/Off) I I I VCE = 50 V I 15 25 0.25 1 --- 0.5 V, to 0.5 V o . I VR = 50 V I. 0.25 I 50 IlA I 6 Current _t~"Cb = 70 '~.f1 = 50 V -L---L-~-l-..1.~-;--J!~~-~ I Clamp Diode Forward I IF = 350 mA I i 1.7 I 2 , V I 7 I Voltage ~ _ _ _ _ _ _ _ _ _ _ _ _L ___,-I _ . ...L _ _ J I VF l 3/4 977 ULQ2001 R·ULQ2002R-ULQ2003R·ULQ2004R TEST CIRCUITS Figure la. Figure lb. Figure 2. Figure 3. r----~ -.-~-- OPEN I OPEN $-1986 5-1980 Figure 4. Figure 5. OPEN OPEN 5 -1987 Figure 6. 4/4 978 Figure 7. VB100 HIGH VOLTAGE DUTY CYCLE CONTROLLER ADVANCE DATA • • • • • • • • • INTEGRATED 4S0V POWER DARLINGTON OUTPUT CURRENT UP TO SA HIGH IMPEDANCE DIFFERENTIAL INPUTS PROGRAMMABLE DRIVER CURRENT DUTY CYCLE CONTROL LINEARITY WITHIN 1.S% SWITCHING FREQUENCY UP TO 100 kHz THERMAL PROTECTION INTEGRATED PROTECTION AT COMPARATOR INPUTS MINIMUM EXTERNAL COMPONENT COUNT The VB100 is mainly intended as a D.C. motor and high voltage inductive load driver. It is able to adjust the output voltage duty cycle as a function of the input control voltage, at a switching frequency set by an internal stable sawtooh generator. Built in thermal shut down switches off the power Darlington whenever the junction temperature exceeds an internally set value, typically 1S0°C with a SV supply. MULTIWATT-11 The VB100 is a monolithic integrated circuit which acts as a fully independent duty cycle controller with high voltage, high current open collector darIi ngton output. It is made using the innovative VI Power M1 technology merging a high voltage vertical discrete Darlington transistor together with bipolar control circuitry. TEST AND APPLICATION CIRCUIT September 1988 1/7 This is advanced information on a new product in development or undergoing evaluation. Details are subject to change without notice. 979 VB100 ABSOLUTE MAXIMUM RATINGS VCE Power Darlington collector voltage 450 V Ic VD Power Darlington collector current 8 A Driver stage supply voltage 15 V Vs Control stage supply voltage ID Driver stage current V1N,V N1 Comparator input voltage Ptot Power dissipation Top Tstg Junction operating temperature -45 to 150 °C Storage temperature -55 to 150 °C 15 V 350 mA V Vs to -10 internally limited THERMAL DATA Rthj _case Thermal resistance junction-case max 3.0 °CIW CONNECTION DIAGRAM (Top view) '-./ 11 10 9 8 7 6 o o 5 4 o 3 2 r-"\ 1 ) TAB CONNECTED TO PIN 6 PC-0290 _2/_7_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m~TI~:J?©~ 980 ______________ VB100 PIN FUNCTION N° NAME High voltage Darlington emitter FUNCTION Output stage ground n.1. It must be short circuited with VE2 ; if no current sensing is used, a filtering capacitor must be provided between this pin and the high voltage supply. If current sensing is required, a shunt resistor can be connected between pin VE1 and VE2 and power ground and the filtering capacitor must be connected between ground and high voltage supply. 1 V E1 2 V SN1 Signal negative supply voltage This pin is connected to the PWM ground and to the control circuit substrate. Supply range is from 0 to - 5V. The applied negative supply voltage must be the most negative voltage of the device and must be the same voltage of pin VSN2 ' 3 VSN2 High current negative supply voltage This pin is connected to the driver ground. Supply range is from 0 to - 5V. An applied negative supply, speeds-up the output Darlington. 4 Vo Driver stage supply voltage This pin supplies the base current for the darlington driver during tON (output darlington on-time) 10 (on) = (V s - V 0 (sat))/R o' 5 Vs Control circuit power supply Supply voltage input. Being the internal reference voltage taken from Vs a 5V ±5% D.C. supply is required. 6 Vc High voltage output collector This pin is internally connected to package header. It is the high voltage open collector output. 7 VIN Inverting input Input of the PWM comparator. A D.C. value between VCHL and VCHH sets the output duty cycle from minimum to maximum value. 8 V CH Non inverting input Non inverting input of the PWM comparator and external capacitance pin. The capacitance ~EXT (togheter with REXT) fixes the sawtooth generator frequency (fose)' A low leakage capacitance is necessary for a linear operation. The relationship between frequency and CEXT REXT is: fose z 1.1/(REXT x CEXT) 9 VR It fixes the current leh of the current generator which changes according to the following relation: leh = 0.56 x V siR EXT 10 GND Analog ground It is the control circuit ground: for a reliable circuit operation only few millivolt drop « 10mV) are allowed between this pin and CEXT ' REXT common point. 11 VE2 High voltage darlington emitter Output stage ground n 2. It must be short circuited with VE1 ; if no current sensing is used, a filtering capacitor must be provided between this pin and the high voltage supply. If current sensing is required, a shunt resistor can be connected between pins V E1 and VE2 and power ground and a filtering capacitor must be connected between power ground and high voltage supply. Biasing Resistor ----------------------------~~~~~~?~~~J?©~ ___________________________ 3_/7 981 VB100 ELECTRICAL CHARACTERISTICS: Vs= 5V; Vee= 300V; VA = 2V; VB = OV; RIN = 10kD; REXT = 50KD; Ree= 88D; Ro= 330D; ReH = 100D; Tc= Tcase= 25°C See fig. 1. - unless otherwise specified. Parameters Test Conditions Min. VeE Voltage between pins 6 and 1 IC (leak) High voltage collector leakage current Vee= 350 V VeE (sat) Saturation voltage of the output Darlington (between pins 6 and 1) VB = 2 V le= 3 A le= 5 A VA = 0 10= 150 mA 10= 250 mA Vo (sat) Saturation voltage between pins 4 and 1 VB = 2 V 10= 50 mA VA = 0 le= 2A Vs Control circuit power supply Is off Control circuit current Is on Control circut current VB = 2 V VinTHH PWM comparator high threshold VB = 2 V Ve= 50 V Te= -40 to 130°C VA = 0-+3V-1 (see fig. 2) PWM comparator low threshold VinTHL Vi nTH (hyst.) PWM comparator hysteresis V mA 2.5 2.7 2.9 3.3 V V 2.8 3.5 V 4.75 5.0 5.25 V 20 30 45 mA 2.5 6 10 mA 0 120 mV VB = 2 V Ve= 50 V Te= -40 to 130°C VA = 3V-+0~ (see fig. 2) 100 260 mV VB = 2 V Ve= 50 V Te= -40 to 130°C (see fig. 2) 50 250 mV 1 10 fJ-A 2.45 2.55 2.8 V 0.4 0.5 0.7 V +7 % VA = 0 VB = 2 V Te= -40 to 130°C Ve= 0.3 V VCHH High level threshold sawtooth generator V A = 0 V -+ 3.2 V - 1 V B = 0.3 V V eHL Low level threshold sawtooth generator VA = 3.2 V -+ 0 V ~ ICH - IR External capacitor charging current, pin 8 versus IR' pin 9 IR= 50 to 110 fJ-A VA = 1 V VB = 0.3 V _4/_7_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~mg::~~cc:, 982 Unit 1 PWM comparator input bias current IR Max. 450 liN --- Typ. -7 ______________ VB100 ELECTRICAL CHARACTERISTICS: Test Conditions Parameters ICH T , X VA = 1 V IR= 100 ,"A 1 Capacitor charging ICH current change with temperature (pin 8) IR= 100 ,"A tr Rise time of the Darlington collector current, Ic (see fig. 3) ID= 150 mA Ic= 3 A ts Storage time of the Darlington collector current, Ic (see fig. 3) Ic= 3 A V SN = -5 V V SN = 0 V ID= 150 mA Fall time of the Darlington collector current, Ic (see fig. 3) Ic= 3 A V SN = -5 V V SN = 0 V ID= 150 mA Minimum duration of the Darlington collector current, Ic (see fig. 3) Ic= 3 A VSN = -5 V V SN = 0 V ID= 150 mA Max. Unit 300 ~- ppm °C 2.7 Reference bias voltage pin 11 tON (min) Typ. Vs= 0.3 V Tc= -40t0130°C VR tf Min. 2.8 2.92 V 0.25 ,"s 1.5 8.0 ,"s ,"s 0.2 1.0 ,"s 2.0 10.0 ,"s ,"s ,"S ICH' = ICH (130°C) - ICH (- 40°C) N.B.' pulsed operation: t rep . = 10 ms Fig. 1 Test Circuit RO REXT IR VR 5 Rc 4 6 9 ~ GND Vs VB100 Vcc RCH VCH VA VB S[-0312 ~-------------~~~~~~?~~~~n ~ ____________ 5/_7 983 VB100 Fig. 2 Comparator threshold hysteresis Fig. 3 Switching waveforms \ OFF 1(1%1 90 VinTHfhist.l _ ~C~•.!l _+-__---+--O-N-- 10 -- \ / S(-0251/2 Fig. 4 Switching waveforms :: z---------~ O~----_.------------------~-----+ ICH ICHl -v O.10mA 0 ~H2 rv -lOrnA 5C-0315 984 VB100 APPLICATION INFORMATION The VB100 is mainly intended as a quarter bridge controller. The sawtooth generator frequency is set by two external components, REXTand C EXT.: the output stage. As VIN increases tON increases following the relationship: REXT. x CEXT. tON = t s +tf +t,+0.91 x x VIN (VCHH - V CHL) in the range: fose = 1 .1/(R EXT . x CEXTJ 0.5Hz < fos e. < 5 kHz 0.5Hz < fos e. < 20 kHz in the ranges: 23.3 kl] 400pF 0.5 Hz < REXT. < CEXT. < fose. < 100 kl] < 200 ftF < 100kHz The input voltage VIN sets the duration of tON for with VSN = 0 with VSN = - 5 V If an inductive load is used, it is necessary to provide a current limiting circuit. The device can form part of a closed loop control by just adding a few external components; fig. 5 shows a typical application example. Fig. 5 Application Circuit Vee TACHOMETER Rs MOTOR R2 V V VB100 R, R" S[-03'4 R1 = R2 = R3= R4= 100 33 I] 1 kl] 0.15 I] R5= Rs= R7= Rs= 100 kl] 1.8 kl] 2 kQ 100 kQ R9 =50kQ C 1 = 1 nF R10 = 3.3 kQ C2 = 1 nF R11 = 4.7 kQ REXT = 50 kl] C 3 = 33 nF C EXT = 1.8 nF - - - - - - - - - - - ru'l SGS-THOMSON 'J, '" J:lJU(gIiil©~r"~C::1fIiil©UIlU(g:i! 7/7 -------------- 985 PACKAGES 987 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TECHNICAL NOTE DESIGNING WITH THERMAL IMPEDANCE by T. Hopkins, C. Cognetti, R. Tiziani REPRINT FROM "SEMITHERM PROCEEDINGS" S. DIEGO (U.S.A.) 1988. ABSTRACT Power switching techniques used in many modern control systems are characterized by single or repetitive power pulses, which can reach several hundred watts each. In these applications where the pulse width is often limited to a few milliseconds, cost effective thermal design considers the effect of thl3rmal capacitance. When this thermal capacitance is large enough, it can limit the junction temperature to within the ratings of the device even in the presence of high dissipation peaks. This paper discusses thermal impedance and the main parameters influencing it. Empirical measurements of the thermal impedance of some standard plastic packages showing the effective thermal impedance under pulsed conditions are also presented. INTRODUCTION Power switching applications are becoming very common in many industrial, computer and automotive ICs. In these applications, such as switching power supplies and PWM inductive load drivers, power dissipation is limited to short times, with single or repeated pulses. The normal description ofthe thermal performance of an IC package, Rth U-a) Uunction to ambient thermal resistance), is of little help in these pulsed applications and leads to a redundant and expensive thermal design. This paper will discuss the thermal impedance and the main factors influencing it in plastic semiconductor packages. Experimental evaluations of the thermal performance of small signal, medium power, and high power packages will be presented as case examples. The effects of the thermal capacitance of the packages when dealing with low duty cycle power dissipation will be presented and evaluated in each of the example cases. The thermal resistance, Rth, quantifies the capability of a given thermal path to transfer heat. The general definition of resistance of the thermal path, which includes the three different modes of heat dissipation (conduction, convection and radiation), is the ratio between the temperature increase above the reference and the heat flow, L,P, and is given by the equation: Rth = L,T L,P = L,T L,Q L,t where: L,Q = heat L,t = time Thermal capacitance, Cth, is a measure of the capability of accumulating heat, like a capacitor accumulates a charge. For a given structural elemen~ Cth depends on the specific hea~ c, volume V, and density d, according to the relationship: Cth=cdV The resulting temperature increase when the element has accumulated the heat Q, is given by the equation: L, T = L,Q/Cth The electrical analogy of the thermal behavior for a given application consisting of an active device, package, printed circuit board, external heat sink and external ambient is a chain of RC cells, each having a characteristic time constant: To show how each cell contributes to the thermal impedance of the finished device consider the THERMAL IMPEDANCE MODEL FOR PLASTIC simplified example shown in figure 1. The example PACKAGES device consists of a dissipating element (integrated The complete thermal impedance of a device can be circuit) soldered on a copper frame surrounded by a modeled by combining two elements, the thermal plastic compound with no external heat sink. Its resistance and the thermal capacitance. equivalent electrical circuit is shown in figure 2. TN 204/0588 1/14 989 Fig. 2 - Equivalent Thermal Circuit of Simplified Package Fig. 1 - Simplified Package Outline < MOLD r-----=------'-- R th si R th frame R th mold C th si C th frame C t h mold CH IP ~:rFRAME 5-10621 5-10622 The first cell, shown in figure 2, represents the thermal characteristics of the silicon itself and is characterized by the small volume with a correspondingly lew thermal capacitance, in the order of a few mJ/oC. The thermal resistance between the junction and the siliconlslug interface is of about 0.2 to 2 °C/W, dependin~l on die size and on the size of the dissipating elements existing on the silicon. The time constant of this cell is typically in the order of a few milliseconds. After the plastic has heated, convection and radiation to the ambient starts. Since a negligible capacitance is associated with this phase, it is represented by a purely resistive element. When power is switched on, the junction temperature increase is ruled by the heat accumulation in the cells, each following its own time constant according with the equation: 6T = Rth Pd [1 - e (tl T) 1 The second cell represents the good conductive path from the siliconlframe interface to the frame periphery. In power packages, where the die is often soldered directly to the extemal tab of the package, the thermal capacitance can be large. The time constant for this cell is in the order of seconds. The steady state junction temperature, Tj, is a function of the Rth (j _ a) of the system, but the temperature increase is dominated by thermal impedance in the transient phase, as is the case in switching applications. From. this point, heat is transferred by conduction to the molded block of the package, with a large thermal resistance and capacitance. The time constant of the third cell is in the order of hundreds of seconds. A simplified example of how the time constants of each cell contribute to the temperature rise is shown in figure 3 where the contribution of the cells of figure 2 is exaggerated for a better understanding. Fig. 3 - Time Constant Contribution of Each Thermal Cell (Qualitative Example) 8.BBt 8.Bl 8.1 t te teB lBBB TII'E OR PULSl: UIOllf ( A.U.) _2/_1_4 _ _ _ _ _ _ _ _ _ _ _ Gi SGS-THOMSON _ _ _ _ _ _ _ _ _ _ __ • J I" i!;lni£:OO@~~~i£:1JiIil@~Di£:~ 990 When working with actual packages, it is observed that the last two sections of the equivalent circuit are not as simple as in this model and possible changes will be discussed later. However, with switching times shorter than few seconds, the model is sufficient for most situations. EXPERIMENTAL MEASUREMENTS When thermal measurements on plastic packages are performed, the first consideration is the lack of a standard method. At presen~ only draft specifications exi~ proposed last year and not yet standardized (1). The experimental method used internally for evaluations since 1984 has anticipated these preliminary recomen- dations to some extent, as it is based on test patterns having, as dissipating elemen~ two power transistors and, as measurement element, a sensing diode placed in the thermal plateau arising when the transistors are biased in parallel. The method used has been presented elsewhere (2) for the pattern P432 (shown in figure 4), which uses two small (1000 sq mils) bipolar power transistors and has a maximum DC power capability of 40W (limited by second breakdown of the dissipating elements). A similar methodology was followed with the new H029 pattern, based on two D-Mos transistors (3) having a total size of 17,000 sq mils and a DC power capability of 300 W on an infinite heat sink at room temperature (limited by thermal resistance and by max operating temperature of the plastics). Fig. 4 a) P432 Test Die D.C. D.C. SUPPLY SUPPLY D.C. SUPPLY FAST DVM PULSE GENERATOR STORAGE SCOPE b) P432 Measurement System --------------lijl ~~~~m=~9A1------------....;3/-1-4 991 Using the thermal evaluation die, four sets of measurements were performed on an assortment of insertion and surface mount packages produced by SGS-Thomson Microelectronics. The complete characterization is available elsewhere (4). The four measurements taken were: 1) Junction to Case Thermal Resistance (Power Packages) 2) Junction to Ambient Thermal Resistance 3) Transient Thermal Impedance (Single Pulse) 4) Peak Transient Thermal Impedance (Repeated Pulses) Fig. 5 a) H029 Test Die b) H029 Measurement System _4/~1_4_ _ _ _ _ _ _ _ _ _ _ _ _ 992 i:1i ~~~~m?1f~:~~Al-------------- Fig. 6 - Set-up for Rth (j _ c) Measurement PRESSURE CLIPPING CONNECTION THIN WIRES WATER-COOLED COPPER BLOCK ~THERMAL GREASE 5-9785 THERMOCOUPLE The junction to case thermal resistance measurements were taken using the well known setup shown in figure 6 where the power device is clamped against a large mass of controlled temperature. The junction to ambient thermal resistance in still air, was measured with the package soldered on standard test boards. described later. and suspensed in 1 cubic foot box. to prevent air movement. The single pulse transient thermal impedance was measured in still air by applying a single power pulse of duration to to the device. The exponential temperature rise in response to the power pulse is shown qualitetively in figure 7. In the presence of one single power pulse the temperature. 6 T max. reached at time to. is lower than the steady state temperature calculated from the junction to ambient thermal resistance. The transient thermal impedance Ro. is obtained from the ratio 6 T max/Pd. Fig. 7 - Transient Thermal Response for a Single Pulse Tmax --l----~ J ______ ' - - I_ __ to 5-9784 ______________________________ ~~~~~~~~:~~------------------------~5~/1~4 993 The peak transient thermal impedance for a series of repetitive pulses was measured by applying a string of power pulses to the device in free air. When power pulses ofthe same height, Pd, are repeated with a given duty cycle, DC, and the pulse length, tp, is shorter than the total time constant of the system, the train of pulses is seen as a continuous source with mean power level given by the equation: Fig. 8 - Transient Thermal Response for Repetitive Pulses a multileaded power package in which the die is attached directly to the tab of package using a soft solder (Pb/Sn) die attach. The tab of the package is a 1.5 mm thick copper alloy slug. The thermal model of the MULTIWATT, shown in figure 9b, is not much different from that shown in figure 2. The main difference being that when heat reaches the edge of the slug, two parallel paths are possible; conduction towards the molding compound, and convection and radiation towards the ambient. After a given time, convection and radiation taked place from the plastic. Fig. 9 Tmax Tmin. I I I I 1 1 I Tamb d P ---':c--c,:-------------- ___ J!'I ~n~rL r---;-. :on~l.. toft ..I __ 5-9786 On the other hand, the silicOn die has a thermal time constant of 1 to 2 ms and the die temperature is able to follow frequencies of some kHz. The result is that Tj oscillates about the average value: t::. Tjavg = a) MULTIWATTassembly Rth Pdavg R th mold The resulting die temperature excursions are shown qualitatively in figure 8. The peak thermal impedance, Rthp, corresponding to the peak temperature, t::. T max, at the equilibrium can be defined: Rthp = t::. T max/Pd = Tamb F (tp, DC) C th 5' The value of Rthp is a function of pulse width and duty cycle. Knowledge of Rthp is very important to avoid a peak temperature higher than specificed values (usually 150°C). EXPERIMENTAL RESULTS The experimental measurements taken on several of the packages tested are summarized in the following sections. MULTIWATT Package The MULTIWATT (R) package, shown in figure 9a, is l l_4_ _ _ _ _ _ _ _ _ _ _ _ _ _6:... 994 C th frame L---C::J--- S --10625 b) Equivalent Thermal Circuit Using the two test die, the measured junction to case thermal resistance is: P432 Rth U- c) = 2°C/W Rth (j - c) = O.4°C/W H029 The measured time constant is approximately 1 ms for each of the two test patterns, but the two devices have a different steady state temperature rise. lifi ~~~~m~1J~:9~ -------------- package in free air, Rth j _ a, is 36°C/W with the P432 die and 34.5°C/W with the H029 die. The second cell shown in figure 9 is dominated by the large thermal mass of the slug. The thermal resistance of the slug, Rthslug is about 1°C/W and the thermal time constant of the slug is in the order of 1 second. Figure 10 shows the single pulse transient thermal impedance for the MULTIWATT with both the P432 and H029 test die. As can be seen on the graph, the package is capable of high dissipation for short periods of time. For a die like the H029 the power device is capable of 700 to 800 W for pulse widths in the range of 1 to 10 ms. For times up to a few seconds the effective thermal resistance for a single pulse is still in the range of 1 to 3°C/W. The third RC cell in the model has a long time constant due to the mass of the plastic molding and its low thermal conductivity. For this cell the steady state is reached after hundreds of seconds. For the M ULTIWATT the DC thermal resistance of the Fig. 10 - Transient Thermal Response MULTIWATT Package ~ Ul P4 32 :3 0 ~ ~ Pd - 2 t- :'1 '"OJ '" ~ '"OJ F t- HI2'J - z: die siz i'l '"z: '" ~ on die di ~ipctin9 Pd - 2 Wa l 2 • 34.000 q.mi Is eo· 1S.S 0 ~q.mi Is mJunled on board '" 0.001 0.01 10 0.1 TII'E OR PULSE IlIOTH ( 5 ) The peak transient thermal impedance for the MULTIWATT package containing the P432 die in free air is shown in figure 11. Power DIP Package The power DIP package is a derivative of standard small signal DIP packages with a number of leads connected to the die pad for heat transfer to external heat sinks. With this technique low cost heat sinks can be integrated on the printed circuit board as shown in figure 12a. The thermal model of the power DIP, shown in figure 12b accounts for the extemal heat sink on the circuit board by adding a second RC cell in parallel with the cell corresponding to the molding compound. 1000 In this model, the second cell has a shorter time constant than for the MULTIWATT package, due in large part to the smaller quantity of copper in the frame (the frame thickness is 0.4 mm compared to 1.5 mm). Thus the capacitance is reduced and the resistance increased. The increased thermal impedance due to the frame can partially be compensated by a better thermal exchange to the ambient by adding copper to the heat sink on the board. The DC thermal resistance between the junction and ambient can be reduced to the same range as the MULTIWATT package in free air, as shown in figure 13. - - - - - - - - - - - - r u •'J, l" SCiS-THOMSON _ _ _ _ _ _ _ _ _ _ _7.;.../1_4 IJiJDIt:~@~~~It:1T~@ilD©® 995 Fig. 11 - Peak Thermal Resistance MULTIWATT Package , :3 u DC - 2~ .... ~.S l.! a.4 '".... '" lI! .... '" la if B.3 § a.2 >z:: !;j z:: a: ~ '"It'a: ~ - ~ l------ ~ ------------Pd-SWaH free air D}!L ___ DC-DUTY CYC E---- __ !..U.L_S_I';._"L PULSE REPETI ION PERIOD 10 a.l laa laaa THE DR PULSE IJIDTH ( ms ) Fig. 12 R th mold Ti thtram.!G~-D--Tamb -00 Rthsi R "", '''''=. 5-10626 a) Power DIP Package _8;.../1_4_ _ _ _ _ _ _ _ _ _ _ _ _ ~ 996 C th mold ~~-f"l-'.m" C th board b) Equivalent Thermal Circuit ~~~~m~vT:~~©~ --------------- Fi~. 13 - Rth (i - a) vs. PCB Heat Sink Size 12 + 3 + 3 Power Dip CS> ~ '" u ~ 'z: 1\ \ II> ~ z: S t; z: ...,:::> ~ M 6.eB 6.5e 1.66 1.56 2.66 2.56 3.66 3.56 4.66 1 ( em ) As a comparison, figure 14 compares the thermal performance of the power DIP and the MULTIWATT package. It is clearly seen that even though the DC thermal resistance may be similar, the MULTIWATT is superior in its performance for pulsed applications. Fig. 14 - Transient Thermal Impedance for Single Pulses in Power DIP and MULTIWATT Packages SIN Pd lB LE = 2 DIP(12+3+ ) with 6 SQ.CM 0 BOARD HEAT SINK AREA B.BBl B.Bl IR B.l lB lBB lBBS TIME DR PULSE IJIDTH ( s ) 9/14 ------------- ~ S~~~~m~1i~:~?~~-----------.....;..- 997 Standard Signal Packages In standard, small signal, packages the easiest thermal path is from the die to the ambient through the molding compound. However, if a high conductivity frame, like a copper lead frame, is used another path exists in parallel. Figure 15 shows the equivalent thermal model of such a package. The effectiveness of a copper frame in transferring heat to the board can be seen in the experimental results in DC conditions. Fig. 15 R th mold t lamb 5-10627 a) DIP Package Mounted on PCB b) Equivalent Thermal Circuit DIP Package on PCB Table 1 shows the thermal resistance of some standard signal packages in two different conditions; with the device floating in still air connected to the measurement circuit by thin wires and the same device soldered on a test board. Table 1 - Thermal Resistance of Signal Packages Package DIP8 DIP 14 DIP 16 DIP 20 DIP 14 DIP 20 DIP 24 DIP 20 SO 14 PLCC 44 DC/W Frame Thickness & Material Rth O-a) floating (0.4 mm Copper) (0.4 mm Copper) (0.4 mm Copper) (0.4 mm Copper) (0.25 mm Copper) (0.25 mm Copper) (0.25 mm Copper) (0.25 mm Alloy 42) (0.25 mm Copper) (0.25 mm Copper) 125-165 78-90 98-128 64-73 95-124 62-71 58-69 85-112 115-147 84-95 100-134 76-87 67-84 61-68 158-184 133-145 218-250 105-180 66-83 48-72 on board The transient thermal resistance for single pulses for the various packages are shown in figures 16 through 20. The results of the tests, as shown in the preceding figures, show the true capabilities of the packages. For example, the DIP 20 with a Alloy 42 frame is a typical package used for signal processing applications and can dissipate only 0.5 to 0.7 W in steady state conditions. However, the transient thermal impedance for short pulses is low (11DC/W for tp = 100 ms) and almost 7 Watts can be dissipated for 100 ms while. keeping the junction temperature rise below 80DC. The packages using a 0.4 mm Copper frame have a low steady state thermal resistance, especially in the case of the DIP 20. The thicker lead frame increases the thermal capacitance of the die flag, which greatly improves the transient thermal impedance. In the case of the DIP 20, which has the largest die pad, the transient Rth for 100 ms pulses is about 4.3DC/W. This allows the device to dissipate an 18 Watt power pulse while keeping the temperature rise below 80DC. As with the previous examples the peak transient thermal impedance for repetitive pulses depends on the pulse length and duty cycle as shown in figure 14. With the signal package, however, the effect of the duty cycle becomes much less effective for longer pulses, due primarily to the lower thermal capacitance and hence lower time constant of the frame. _1..;;O/....;1~4_ _ _ _ _ _ _ _ _ _ _ _ _ ~ ~~~~m?1i~:J?©~ 998 -------------- Fig. 16 - Transient Thermal Impedance DIP 20 (Alloy 42) .--1- 100 SINe LE ~ u Pd - 1 IJ H ~ t- ~ '" L.J '" 10 V ~ tzo V ~ '" zo a ~ 0.001 0.01 on board mounle a g p ~LSE V - V / on die dis ipcl:.ing a eo - 2.000 5q.mi l!lo die pad '" 125 x 1sa 0.1 TIME OR PULSE WIDTIl ( q.mi 15 10 5 100 1000 ) Fig. 17 - Transient Thermal Impedance 0.4 mm Copper Frame DIP Packages 10 \) ~ i 10 1800 TInE OR PULSE lIlOTH ____________ 51 SGS-THOMSON 'J'" _ _ _ _ _ _ _ _ _ _ _1_1:../1_4 IiijJn©rnI@~~~©lIrn1@~~©~ 999 Fig. 18 - Transient Thermal Impedance 0.25 mm Copper Frame DIP Packages 100 on die area::: 2. 00 sq. mils issipotin 20 moun led on board , Pd - 2 :3 tl SINGL PULSE u '" lE ~ ~ '" '" . '" ~ '"'" F 10 ... § 00x135. .mils ie pad .. '" z: a: ~ 'B.01 0.BBl DIP 20 119 x 129 • .mils DIP 24 150x280. .mi Is 0.1 1B lBB 10BB TII1: DR PULSE WIDTH ( s ) Fig. 19 - Transient Thermal Impedance 0.25 mm Frame PLCC Package 50 sn , GLE V I:l z: ~ ~ '" '" '" ..J 19 ~ '"~ ... ~ '"z: ...8i V Watt Pd - V 9.001 / 0.91 ~ PULSE mounl donSI1PC 5 board :3 u V ad - 269 die ize • 35. 8fJ aq.mils on die dl sipating B.l 269 sq.mi s di. 1 0 eo 19 = 2.08e sq.mils 100 1990 TII1: OR PULSE UIDTH ( s ) _12..;.I_l_4_ _ _ _ _ _ _ _ _ _ _ _ 1000 l.U ~~~~mg~:~~~, -------------- Fig. 20 - Transient Thermal Impedance 0.25 mm Copper Frame 5014 Package 100~========~==========~========~==~~CDcrTI~ , 3 u 5 WaH mounled on SM 10 --->1<- - 2 WaH CB1 B SGS board 100 1080 10000 TIl'[ OR PULSE WroTH ( ms ) Fig. 21 - Peak Thermal Impedance 0.25 mm Copper Frame 14 Lead DIP Sf) :3 ~ ~ '-'~I W ~ --" a: ~ f- >::: B ,~ z= f:: 10 w "- IJ.1 18 100 1000 -------------- I.:fl ~~~~~g~:~~~~ ____________..;;1..;;3.:../;;..14 1001 CONCLUSION This paper has discussed a test procedure for measuring and quantifying the thermal characteristics of semiconductor packages. Using these test methods the thermal impedance of standard integrated circuit packages under pulsed and DC conditions were evaluated. From this evaluation two important considerations arise: 1) The true thermal impedance under repetitive pulsed conditions needs to be considered to maintain the peak junction temperature within the rating for the device. A proper evaluation will result in junction temperatures that do not exceed the specified limits under either steady state or pulsed conditions. 2) The proper evaluation of the transient thermal characteristics of an application should take into account the ability to dissipate high power pulses _14..;1_1_4_ _ _ _,....-_ _ _ _ _ _ _ 1002 allowing better thermal design and possibly reducing or eliminating expensive extemal heat sinks when they are oversized or useless. REFERENCES (1) SEMI Draft Specifications 1377 and 1449, 1986 (2) T. Hopkins, R. Tiziani, and C. Cognetti, "Improved thermal impedance measurements by means of a simple integrated structure", presented at SEMITHERM 1986 (3) C. Cini, C. Diazzi, D. Rossi and S. Storti, "High side monolithic switch in Multipower-BCD technology", Proceedings of Microelectronics Conference, Munchen, November 1986 (4) Application Notes 106 through 110, SGS-THOMSON Microelectronics, 1987 @. ~~~~m~1J~:~~~ -------------- PACKAGES SO-8J SO-16J SO-14J SO-20L SO-20 (12+4+4) 1003 PACKAGES PLCC - 20 Plastic Chip Carrier PLCC 15 + 5 PLCC - 44 Plastic Chip Carrier PLCC -28 Plastic Chip Carrier 8 lead Plastic Minidip 4+4 lead Powerdip : .--~-:;;--o.a~!,Q-l:J..n-, rF--:2~_-2S ,) I I EIj;I .... 1 'I I - ~ ' -+- 'ri O.9--++--""'--_H= LU"" , '''\ 1153 ~2-:7~.~_-l 1004 P001-F6 PACKAGES 8 lead Plastic Minidip/2 """''" -t--t-tj"'"1' ' ' ''',m " _._-._- l ~_.J.~' 63.'J(1) 14 lead Plastic Dip III Nominal dimension 121 Truegeometri~.l position J 8 lead Ceramic Minidip 14 lead Plastic Dip/2 (1) Nominaldimt!nsign 121 TruegllOmetric:alposillon 1005 PACKAGES 14 lead Ceramic Dip 16 lead Plastic Dip (0.4) 8+8 lead Powerdip 12+2+2 lead Powerdip ~J R38toO.50 I i wcLj 1 - - - - -- ~~--------j 01 16 lead Plastic Dip/2 16 lead Plastic Dip (0.25) 2.54 RL. I I LJl,L-j I i ~:::::::i 1006 PACKAGES 18 lead Ceramic Dip 16 lead Ceramic Dip ~ 18.95109.521 [::::::1 I 18 lead Plastic Dip I 20.3 8.95'09.52 ~ ~ 20 lead Plastic Dip (0.25) 12+3+3 lead Powerdip Q ~ [ ~ ,::::::J - .''''"''----, 1007 PACKAGES 20 lead Plastic Dip (0.4) 16+2+2 Powerdip 14+3+3 Powerdip 28 lead Plastic Dip 14.1 ~ .Q,L-~J.4 1.27"'''1 ---±'22'""'.86'---_~ I CJ 37.34- (TliU 023'0 15.2'016.68 I [:::::: :::::1 22 lead Plastic Dip 40 lead Plastic Dip 14.1 rna. '"~ Or 0 ----~--- "- " ," " 8" " u . 9..o! " 1008 (1) Nomlnaldimens,on (2) T",eg80IllI!tricalposjrion t:::::: ::'::~::::::: I Q23t0031 15.21016.68 PACKAGES PENTAWATT TO-220 4.8rna~ ~ 3.85 jii.$. 3.65 I Horizontal Version ~I~' 01 1.20to~ ;::;1 I i L I 2.~~ 0.35 to 0.55 1:"- SOT-82 Vertical Version ~ IX> $2 -~ .1\ N c E


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