1988_Samsung_MOS_Memory_Data_Book 1988 Samsung MOS Memory Data Book
User Manual: 1988_Samsung_MOS_Memory_Data_Book
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ciS
SAIUISUNG
MOS Memory
Data ~ Book
1988
Copyright 1988 by Samsung Semiconductor
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electronic, mechanical, photo
copying, recording, or otherwise, without the prior written permission of Samsung
Semiconductor.
The information contained herein is subject to change without notice. Samsung
assumes no responsibility for the use of any circuitry other than circuitry embodied in
a Samsung product.
No other circuit patent licenses are implied.
SAMSUNG SEMICONDUCTOR
DATA BOOK LIST
I. Semiconductor Product Guide
II. Transistor Data Book
Vol. 1: Small Signal TR
Vol. 2: Bipolar Power TR
Vol. 3: TR Pellet
III. Linear IC Data Book
Vol. 1: AudiolVideo
Vol. 2: Telecom/Industrial/Data Converter Ie
IV. MOS Product Data Book
V. High Performance CMOS Logic Data Book
VI. MOS Memory Data Book
VII. SFET Data Book
TABLE OF CONTENTS
I.
PRODUCT GUIDE
1. Introduction .............................................................................................. 11
2. product Guide ......................................................................................... 14
3. Ordering Information ............................................................................... 17
II.
DRAM DATA SHEETS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
III.
SRAM DATA SHEETS
1.
2.
3.
4.
5.
6.
7.
8.
IV.
KM6264A/KM6264AL .............................................................................. 141
KM62256AP/KM62256ALP .......................................................................149
KM6165 ..................................................................................................... 156
KM6465 .....................................................................................................157
KM6865 .....................................................................................................158
KM61257 ...................................................................................................159
KM64257 ...................................................................................................160
KM68257 ...................................................................................................161
EEPROM DATA SHEETS
1.
2.
3.
4.
5.
6.
7.
8.
V.
KM4164B ................................................................................................. 21
KM41256A/KM41257A ............................................................................ 32
KM41464A ............................................................................................... 47
KM41C1000 ............................................................................................. 59
KM41C1001 ............................................................................................. 73
KM41C1002 ............................................................................................. 74
KM44C256 .............................................................................................. 89
KM44C258 ................... ··········································································1 04
KMM4(5)8256/KMM4(5)8257 ...................................................................105
KMM4(5)9256/KMM4(5)9257 ...................................................................114
KMM4(5)81000/KMM4(5)81001 .............................................................. 123
KMM4(5)91000/KMM4(5)91001 ...............................................................131
KM2816A ................................................................ ·.... ·····························165
KM2817A ....................................................................................·· .. ··········172
KM28C16 ........................................................... ·......... ·· ... ························179
KM28C17 ...............................................................................·... ·· ... ··········187
KM2864A/KM2864AH ....................................................... ····.···················195
KM2865A1KM2865AH .......................................................................········202
KM28C64/KM28C65 ............................................................... ···.·· ... ··········209
KM28C256 .........................................................·· ... ···.··············.···············217
SALES OFFICES and MANUFACTURER'S
REPRESENTATIVES ......................................................·····················219
PRODUCT GUIDE
•
1. INTRODUCTION
1.1 Dynamic RAM
KM4164B-10
KM4164B-12
KM4164B-15
KM41256A-10
KM41256A-12
KM41256A-15
KM41257A-10
KM41257A-12
KM41257A-15
KM41464A-12
H
KM41464A-15
KM41 C1 000-1 0
KM41C1000-12
KM41C1001-10
(TBA)
KM41C1001-12
(TBA)
KM41C1002-10
KM41C1002-12
KM44C256-10
KM44C256-12
KM44C258-10
(TBA)
KM44C258-12
(TBA)
t New Product
• Preliminary Product
Development
(TBA): To Be Announced
tt Under
c8
SAMSUNG SEMICONDUCTOR
11
PRODUCT GUIDE
1.2 Static RAM
KM6264AL-7
KM6264AL-10
KM6264AL-12
KM6264A-7
KM6264A-10
KM6264A-12
ttr--------.
KM6865-35
tt
KM6865-75
....-------. '" tt..--------.
KM6465-25
KM6165-25
ttr--------.
KM6165-35
KM62256AP- 8
KM62256AP-10
KM62256ALP- 8
KM62256ALP-10
tt ...-------,
KM64257-25
KM61257-25
KM68257-45
tt
tt
KM6865-55
ttr-----....,
KM6465-45
KM6465-35
KM68257-35
tt
tt
tt
KM6165-45
KM62256AP-12
-I
tt
KM62256ALP-121
KM68257-55
KM64257 -35
tt
KM64257-45
KM61257-35
tt
KM61257-45
t New Product
• Preliminary Product
ttUnder Development
(TBA): To Be Announced
c8
SAMSUNG SEMICONDUCTOR
12
PRODUCT GUIDE
1.3 EEPROM
KM2816A-25
KM2816A-30
KM2816A-35
KM2817A-25
KM2817A-30
KM2817A-35
KM2864A-20
KM2864A-25
KM2864A-30
KM2865A-20
KM2865A-25
KM2865A-30
KM2864AH-20
KM2864AH-25
KM2864AH-30
KM2865AH-20
KM2865AH-25
KM2865AH-30
KM28C16-15
~
KM28C17-20
KM28C17-15
KM28C64-20
KM28C65-20
KM28C256-15
(TBA)
KM28C16-20
+
KM28C64-25
+
KM28C65-25
KM28C256-20
H
KM28C16-25
KM28C17-25
KM28C256-25
(TBA)
t New Product
* Preliminary Product
ttUnder Development
(TBA): To Be Announced
=8
SAMSUNG SEMICONDUCTOR
13
I
PRODUCT GUIDE
2. PRODUCT GUIDE
2.1 Dynamic RAM
Capacity
64K bit
256K bit
1M bit
Speed
(ns)
Technology
64Kxl
64Kx 1
120
150
NMOS
NMOS
Page Mode
Page Mode
16-Pin DIP
16-Pin DIP
Now
Now
KM41256AP-12
KM41256AP-15
KM41256AJ-12
KM41256AJ-15
KM41256AZ-12
KM41256AZ-15
KM41257AP-12
KM41257AP-15
KM41257AJ-12
KM41257AJ-15
KM41257AZ-12
KM41257AZ-15
KM41464AP-12
KM41464AP-15
KM41464AJ-12
KM41464AJ-15
KM41464AZ-12
KM41464AZ-15
256Kx 1
256K x 1
256Kx 1
256Kx 1
256Kx 1
256Kxl
256Kx 1
256Kx 1
256Kxl
256Kxl
256Kx 1
256Kxl
64Kx4
64Kx4
64Kx4
64Kx4
64Kx4
64Kx4
120
150
120
150
120
150
120
150
120
150
120
150
120
150
120
150
120
150
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
16-Pin
16-Pin
18-Pin
18-Pin
16-Pin
16-Pin
16-Pin
16-Pin
18-Pin
18-Pin
16-Pin
16-Pin
18-Pin
18-Pin
18-Pin
18-Pin
20-Pin
20-Pin
DIP
DIP
PLCC
PLCC
ZIP
ZIP
DIP
DIP
PLCC
PLCC
ZIP
ZIP
DIP
DIP
PLCC
PLCC
ZIP
ZIP
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
KM41C1000P-l0
KM41C1000P-12
KM41Cl000J-l0
KM41Cl000J-12
KM41Cl000Z-l0
KM41Cl000Z-12
KM41Cl002P-l0
KM41Cl002P-12
tKM44C256J-l0
tKM44C256J-12
1M x 1
1M x1
1M xl
1Mxl
lMxl
1M xl
1Mxl
1M x 1
256Kx4
256Kx4
100
120
100
120
100
120
100
120
100
120
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
S. Column Mode
S. Column Mode
Fast Page Mode
Fast Page Mode
18-Pin
18-Pin
20-Pin
20-Pin
20-Pin
20-Pin
18-Pin
18-Pin
20-Pin
20-Pin
DIP
DIP
SOJ
SOJ
ZIP
ZIP
DIP
DIP
SOJ
SOJ
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Part Number
Organization
KM4164B-12
KM4164B-15
Features
Remark
Packages
• KM41Cl00l (Nibble Mode) and KM44C258 (Static Column Mode) are available in Q4,'88.
2.2 Dynamic RAM MODULE
Org~nization
Speed
(ns)
Technology
KMM48256-12
KMM48256-15
KMM58256-12
256Kx8
256Kx8
256K x8
120
150
120
NMOS
NMOS
NMOS
Page Mode
Page Mode
Page Mode
KMM58256-15
256Kx8
150
NMOS
Page Mode
KMM49256-12
KMM49256-15
KMM59256-12
256Kx9
256Kx9
256Kx9
120
150
120
NMOS
NMOS
NMOS
Page Mode
Page Mode
Page Mode
KMM59256-15
256Kx9
150
NMOS
Page Mode
Part Number
Features
Packages
Remark
30-Pin SIP
30-Pin SIP
30-Pin SIMM
(Edge Connector)
30-Pin SIMM
(Edge Connector)
Call Factory
Call Factory
Call Factory
30-Pin SIP
30-Pin SIP
3O-Pin SIMM
(Edge Connector)
3O-Pin SIMM
(Edge Connector)
Call Factory
Call Factory
Call Factory
Call Factory
Call Factory
t New Product
ciS
SAMSUNG SEMICONDUCTOR
14
PRODUCT GUIDE
2.2 Dynamic RAM MODULE
(Continued)
Part Number
Organization
Speed
(ns)
Technology
Features
Packages
Remark
KMM481000·10
KMM481000·12
KMM581000·10
1M x8
1M x8
1M x8
100
120
100
CMOS
CMOS
CMOS
Fast Page Mode
Fast Page Mode
Fast Page Mode
Call Factory
Call Factory
Call Factory
KMM581000·12
1M x8
120
CMOS
Fast Page Mode
30·Pin SIP
30·Pin SIP
30·Pin SIMM
(Edge Connector)
30·Pin SIMM
(Edge Connector)
KMM491000·10
KMM491000·12
KMM591000·10
1M x9
1M x9
1M x9
100
120
100
CMOS
CMOS
CMOS
Fast Page Mode
Fast Page Mode
Fast Page Mode
Call Factory
Call Factory
Call Factory
KMM591oo0·12
1M x9
120
CMOS
Fast Page Mode
30·Pin SIP
30·Pin SIP
30·Pin SIMM
(Edge Connector)
30·Pin SIMM
(Edge Connector)
Call Factory
Call Factory
2.3 Static RAM
Capacity
Part Number
64K bit
tKM6264A·7
KM6264A·10
KM6264A·12
tKM6264AL·7
KM6264AL·10
KM6264AL·12
ttKM6165·25
KM6165·35
KM6165-45
KM6465·25
64K bit
KM6465·35
KM6465·45
KM6865·35
KM6865·45
KM6865·55
KM62256p·10
KM62256p·12
KM62256p·15
KM62256Lp·10
KM62256Lp·12
KM62256Lp·15
ttKM61257·25
256K bit
KM61257·35
KM61257·45
KM64257·25
KM64257·35
KM64257·45
KM68257·35
KM68257·45
KM68257·55
Organization
Current
Speed
Technology Active, mA Standby, /LA
(ns)
Typ (max) Typ (max)
8Kx8
8Kx8
8Kx8
8Kx8
8Kx8
8Kx8
70
100
120
70
100
120
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
64Kx1
64Kx1
64Kx 1
16Kx4
16Kx4
16Kx4
8Kx8
8Kx8
8Kx8
25
35
45
25
35
45
35
45
55
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
256Kx 1
256Kx 1
256K x 1
64Kx4
64Kx4
64Kx4
32Kx8
32Kx8
32Kx8
100
120
150
100
120
150
25
35
45
25
35
45
35
45
55
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
35
35
35
35
35
35
(70)
(70)
(70)
(70)
(70)
(70)
Packages
Remark
(1mA)
(1mA)
(1mA)
(1mA)
2 (0.1mA)
2 (0.1mA)
28·Pin
28·Pin
28·Pin
28·Pin
28·Pin
28·Pin
DIP
DIP
DIP
DIP
DIP
DIP
Now
Now
Now
Now
Now
Now
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
22·Pin
22·Pin
22·Pin
22·Pin
22·Pin
22·Pin
28·Pin
28·Pin
28·Pin
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
under development
under development
under development
under development
under development
under development
under development
under development
under development
35 (60)
35 (60)
35 (60)
35 (60)
35 (60)
35 (60)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(1mA)
(1mA)
(1mA)
(0.1mA)
(0.1mA)
(0.1mA)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
28·Pin
28·Pin
28·Pin
28·Pin
28·Pin
28·Pin
24·Pin
24·Pin
24·Pin
24·Pin
24·Pin
24·Pin
28·Pin
28·Pin
28·Pin
DIP
DIP
DIP
DIP
DIP
DIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
DIP
DIP
DIP
Now
Now
Now
Now
Now
Now
under development
under development
under development
under development
under development
under development
under development
under development
under development
t New Product
tt Under Development
c8
SAMSUNG SEMICONDUCTOR
15
PRODUCT GUIDE
2.4 EEPROM
Write Cycle
Speed
Technology Time (min)
(ns)
(ms)
Capacity
Part Number
16K bit
KM2B16A-25
KM2B16A-30
KM2B16A-35
KM2B17A-25
KM2B17A-30
KM2B17A-35
tKM2BC16-15
tKM2BC16-20
tKM2BC16-25
tKM2BC17-15
tKM2BC17-20
tKM2BC17-25
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
2KxB
250
300
350
250
300
350
150
200
250
150
200
250
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
10
10
10
10
10
10
2
2
2
2
2
2
KM2864A-20
KM2864A-25
KM2864A-3O
KM2865A-20
BKxB
BKxB
BKxB
BKxB
200
250
300
200
NMOS
NMOS
NMOS
NMOS
10
10
10
10
KM2865A-25
BKxB
250
NMOS
10
KM2865A-30
BKxB
300
NMOS
10
KM2864AH-20
KM2864AH-25
KM2864AH-30
KM2865AH-20
BKxB
BKxB
BKx.B
BKxB
200
250
300
200
NMOS
NMOS
NMOS
NMOS
2
2
2
2
KM2865AH-25
BKxB
250
NMOS
2
KM2865AH-3O
BKxB
300
NMOS
2
KM2BC64-20
BKxB
200
CMOS
5
KM2BC64-25
BKxB
250
CMOS
5
KM2BC65-20
BKxB
200
CMOS
5
KM2BC65-25
BKxB
250
CMOS
5
ttKM2BC256-15
32KxB
130
CMOS
5
ttKM2BC256-20
32KxB
200
CMOS
5
ttKM2BC256-25
32KxB
250
CMOS
5
64K bit
256K
Organization
Features
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Data Polling
Data Polling
Data Polling
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling
Data Polling
Data Polling
Data Polling,
Ready/Busy
Data Polling,
, Ready/Busy
Data Polling,
Ready/Busy
Data Polling,
Page Mode
Data Polling,
Page Mode
Ready/Busy,
Page Mode
Ready/Busy,
Page Mode
Packages
Remark
24-Pin
24-Pin
24-Pin
2B-Pin
2B-Pin
28-Pin
24-Pin
24-Pin
24-Pin
2B-Pin
28-Pin
2B-Pin
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Now
Now
Now
Now
Now
Now
under development
under development
under development
under development
under development
under development
2B-Pin
2B-Pin
28-Pin
2B-Pin
DIP
DIP
DIP
DIP
Now
Now
Now
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
28-Pin
2B-Pin
2B-Pin
2B-Pin
DIP
DIP
DIP
DIP
Now
Now
Now
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
2B-Pin DIP
Now
Data Polling, 2B-Pin DIP under development
Toggle bit
Data Polling, 28-Pin DIP under development
Toggle bit
Data Polling, 2B-Pin DIP under development
Toggle bit
t
New Product
ttUnder Development
c8
SAMSUNG SEMICONDUCTOR
16
PRODUCT GUIDE
•
3. ORDERING INFORMATION
KM
~MSU.O J
xxxx
x
X
xx
X -
XX
l
MEMORY
COMPONENT
sPE".
010:
012:
015:
020:
100ns
120ns
150ns
200ns
025: 250ns
030: 300ns
035: 350ns
PART
NUMBER
TEMPERATURE RANGE
oBLANK 0-70°C
01
-40-+85°C
oM
- 55- + 125°C
REVISION - - - - - - - PERFORMANCE---------~
oBLANK-STANDARD
oH
-HIGH SPEED
oL
-LOW POWER
' - - - - - - - - - PACKAGE
op PLASTIC DIP
oJ PLASTIC PLCC (256KD)
oJ SOIC J LEAD (1MD)
oG SOIC GULLWING
KMM
X
~_.
MEMORY~
SAMSUNO
xxxx
'I
MODULE
4: SIP (SINGLE IN LINE
PINS ON ONE EDGE)
5: SIMM (EDGE CONNECTOR)
X -
XX
lSPEED
012: 120ns
015: 150ns
'------REViSiON
PARTNUMBER-----------~
c8
SAMSUNG SEMICONDUCTOR
17
NOTES
9. K~ M4(5)8256/KM M4(5)~257
10. KMM4(5)92,56/KMM4(5)9257
,11;."KMM4(5)81 OOO/KM M4(5)81
12. KM M4(5)91 OOO/KM
Dynamic RAM
Capacity
64K bit
256K bit
1M bit
Organization
Speed
(ns)
Technology
64Kx1
64Kx1
120
150
NMOS
NMOS
Page Mode
Page Mode
16-Pin DIP
16-Pin DIP
KM41256AP-12
KM41256AP-15
KM41256AJ-12
KM41256AJ-15
KM41256AZ-12
KM41256AZ-15
KM41257AP-12
KM41257AP-15
KM41257AJ-12
KM41257AJ-15
KM41257AZ-12
KM41257AZ-15
KM41464AP-12
KM41464AP-15
KM41464AJ-12
KM41464AJ-15
KM41464AZ-12
KM41464AZ-15
256Kx 1
256K x 1
256K x 1
256Kx1
256Kx1
256Kx1
256Kx1
256Kx 1
256Kx1
256Kx1
256Kx 1
256Kx1
64Kx4
64Kx4
64Kx4
64Kx4
64Kx4
64Kx4
120
150
120
150
120
150
120
150
120
150
120
150
120
150
120
150
120
150
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Nibble Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
Page Mode
16-Pin
16-Pin
18-Pin
18-Pin
16-Pin
16-Pin
16-Pin
16-Pin
18-Pin
18-Pin
16-Pin
16-Pin
18-Pin
18-Pin
18-Pin
18-Pin
20-Pin
20-Pin
DIP
DIP
PLCC
PLCC
ZIP
ZIP
DIP
DIP
PLCC
PLCC
ZIP
ZIP
DIP
DIP
PLCC
PLCC
ZIP
ZIP
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
KM41C1000P-10
KM41C1000P-12
KM41C1000J-10
KM41C1000J-12
KM41C1000Z-10
KM41C1000Z-12
KM41C1002P-10
KM41C1002P-12
tKM44C256J-10
tKM44C256J-12
1M x1
1M x1
1M x1
1M x1
1M x1
1M x1
1M x1
1M x1
256Kx4
256Kx4
100
120
100
120
100
120
100
120
100
120
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
Fast Page Mode
S. Column Mode
S. Column Mode
Fast Page Mode
Fast Page Mode
18-Pin
18-Pin
20-Pin
20-Pin
20-Pin
20-Pin
18-Pin
18-Pin
20-Pin
20-Pin
DIP
DIP
SOJ
SOJ
ZIP
ZIP
DIP
DIP
SOJ
SOJ
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Part Number
KM4164B-12
KM4164B-15
Features
Packages
• KM41C1001 (Nibble Mode) and KM44C258 (Static Column Mode) are available in 04,'88.
Remark
Now
Now
KM4164B
NMOS DRAM
64K x 1 Bit Dynamic RAM with Page Mode
FEATURES
GENERAL DESCRIPTION
• Performance range
The KM4164B is a fully decoded NMOS Dynamic Random Access Memory organized as 65,536 one-bit words,
The design is optimized for high speed, high performance applications such as computer memory, peripheral storage and environments where low power
dissipation and compact layout are required.
•
•
•
•
•
•
•
•
tRAC
tCAC
tRC
KM4164B-10
100ns
55ns
190ns
KM4164B-12
120ns
60ns
220ns
KM4164B-15
150ns
75ns
260ns
The KM4164B features page mode which allows high
speed random access of up to 256-bits within the same
row. Multiplexed row and column address inputs permit the KM4164B to be housed in a standard 16-pin DIP.
Page Mode capability
Single +5V :t10% power supply
Common I/O using early write
TTL compatible Inputs and output
Schmitt Triggers on all input control lines
RAS-only and Hidden Refresh capability
128 cycle/2ms refresh
Jedec standard pinout in 16-pin DIP
The KM4164B is fabricated using Samsung's advanced silicon gate NMOS process. This process, coupled
with single transistor memory storage cells, permits
maximum circuit density and minimal chip size.
Clock timing requirements are noncritical, and power
supply tolerance is very wide. All inputs and output are
TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
PIN CONFIGURATION
DATA
IN
BUFFER
D
DATA
OUT
BUFFER
Q
COWMN DECODER
SENSE AMPS &
110 GATINGS
Ao
Al
A2
Aa
A4 A5
A6
A,
c8
C1)
a:
w
u.
u.
a:
w
0
0
<.l
MEMORY ARRAY
C1)
C1)
0
MEMORY CELLS
0
0
0
a:
~
CD
w
a:
...:
w
5:
Pin Name
Pin Function
AD-A,
Address inputs
-vee
0
Data In
-vss
Q
Data Out
W
ReadlWrite Input
65,356
SAMSUNG SEMICONDUCTOR
RAS
Row Address Strobe
CAS
Column Address Strobe
Vee
Power (+5V)
Vss
Ground
21
•
KM4164B
NMOS DRAM
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Rating
Units
V
VIN, VOUT
-2.0 to + 7.0
Voltage on Vee supply relative to Vss
Vee
-1 to + 7.5
V
Storage Temperature
Tstg
-65 to +150
°C
Power Dissipation
Po
1.0
W
Short Circuit Output Current
los
50
mA
Voltage on any pin relative to Vss
* Permanent device damage may occur of ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should
be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
(Voltages referenced to Vss, TA=O to 70°C)
Min
Typ
Max
Unit
V
Supply Voltage
Vee
4.5
5.0
5.5
Ground
Vss
0
0
0
Input High Voltage
VIH
2.4
Input Low Voltage
VIL
-2.0
V
-
Vee +1
V
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Para!"'leter
Operating Current*
(RAS and CAS cycling; @tRC= min.)
Symbol
KM4164B·10
KM4164B·12
KM4164B·15
Standby Current
(RAS = CAS = VIH after 8 RAS cycles min.)
ICCl
Icc2
RAS-Only Refresh Current*
(CAS = VIH, RAS cycling; @tRC= min.)
KM4164B-10
KM4164B-12
KM4164B-15
Icc3
Page Mode Current*
KM4164B-10
KM4164B-12
KM4164B-15
IcC4
(RAS = VIL, CAS cycling; @tpc= min.)
Min
Max
Units
-
60
50
45
mA
mA
mA
4
mA
-
50
40
35
mA
mA
mA
45
35
30
mA
mA
-
Input Leakage Current
(Any input OSVINS5.5V, Vcc=5.5V, Vss=OV,
all other pins not under test = 0 volts.)
IlL
-10
10
p.A
Output Leakage Current
(Data out is disabled, OSVouTS5.5V, Vee = 5.5V,
Vss= OV)
I~L
-10
10
p.A
Output High Voltage Level (loH =- 5mA)
VOH
2.4
-
V
VOL
-
0.4
V
Output Low Voltage Level (loL
=4.2mA)
*Note: Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open.
lec is specified as an average current.
c8
SAMSUNG SEMICONDUCTOR
22
NMOS DRAM
KM4164B
CAPACITANCE
(TA=25·C)
Symbol
Min
Max
Unit
Input capacitance (Ao-A7, D)
C ,N•
pF
C ,N,
7
pF
Output Capacitance (a)
COUT
-
5
Input capacitance (RAS, CAS, W)
6
pF
Parameter
AC CHARACTERISTICS
•
(0·C::5TA::570·C, Vcc=5.0V±10%. See notes 1,2.)
Parameter
KM4164B-10 KM4164B-12 KM4164B-15
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
Random read or write cycle time
tRC
190
220
260
Read-modify-write cycle time
tRWC
215
255
300
Access time from RAS
tRAC
100
120
150 ns
3, 4
tCAC
55
60
75 ns
3,5
6
Access time from CAS
ns
ns
Output buffer turn-off delay time
tOFF
0
25
0
30
0
35 ns
Transition time (rise and fall)
IT
3
100
3
100
3
100 ns
RAS precharge time
tRP
80
90
100
ns
RAS pulse width
tRAS
100
10,000 120
10,000 150
10,000 ns
RAS hold time
tRsH
55
CAS pulse width
tCAS
55
CAS hold time
tCSH
100
RAS to CAS delay time
tRCO
15
CAS to RAS precharge time
tCRP
0
60
10,000
60
10,000
120
45
20
0
60
75
ns
75
10,000 ns
150
ns
25
75
ns
0
ns
Row address set-up time
tASR
0
0
0
ns
Row address hold time
tRAH
15
18
20
ns
Column address set-up time
tASC
0
0
0
ns
tCAH
25
30
35
ns
Column address hold time referenced to RAS
tAR
70
90
110
ns
Read command set-up time
tRcs
0
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
0
ns
Read command hold time referenced to RAS
tRRH
0
0
0
ns
Write command set-up time
twcs
0
0
0
ns
Write command hold time
tWCH
30
35
45
ns
Write command pulse width
twp
30
35
45
ns
ns
ns
Column address hold time
Write command to RAS lead time
tRwL
25
35
45
Write command to CAS lead time
tCWL
25
35
45
Data-in set-up time
tDS
0
0
0
ns
Data-in hold time
tDH
30
35
40
ns
CAS to write enable delay time
tCWD
50
55
65
ns
eSc••
SAMSUNG SEMICONDUCTOR
~
7
7
23
NMOS DRAM
KM4164B
AC CHARACTERISTICS
(Continued)
Parameter
Symbol
KM4164B-10 KM4164B-12 KM4164B-15
Min
Max
Min
Min
Max
Max
Units Notes
RAS to write enable delay time
tRwo
95
115
140
ns
Write command hold time referenced to RAS
tWCR
75
95
120
ns
Data-in hold time referenced to RAS
tOHR
75
95
115
ns
Page mode cycle time
tpc
105
120
145
ns
CAS precharge time (page mode only)
tcp
40
45
60
ns
tCPN
25
25
30
ns
CAS
precharge time (all cycles except page mode)
Refresh period
tREF
2
2
7
2 ms
NOTES
1. An initial pause of 100"s is required after power-up followed by any 8 RAS cycles before proper device operation
is achieved.
2. V1H(min) and V1L(mas) are reference levels for measuring timing of input signals. Transition times are measured
between V1H(min) and V1L(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the TRCO(max) limit insures that TRAc(max) can be met. tRco(max) is specified as a reference point
only. If tRCO is greater than the specified tRCO(max) limit, then access time is controlled exclusively by TCAC.
5. Assumes that tRco~tRCO(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced
to VOH or VOL'
7. tewo and tAWo are restrictive operating parameters for the read-modify-write cycle only. If twcs~twcs(min), the
cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. If
tewo~tewo(min) and tAWo>tRwo(min), the cycle is a late write cycle and the data output will contain data read from
the selected cell. If neither of the above conditions are met, the condition of the data out (at access time until
CAS goes back to V1H) is indeterminate.
c8
SAMSUNG SEMICONDUCTOR
24
KM4164B
NMOS DRAM
TIMING DIAGRAMS
READ CYCLE
•
IRC
IRAS
IAR-----
\.
ICSH
-IRCD
CAS
,,\
VIH_
VIL-
D
IRAH
_IASRA
VIHVIL-
ID
ROW
ADDRESS
I--:--IRP-
IASC
-ICRP-
tRSH
ICAS
~
J
_ICPN-
ICAH
--I
----
I-
.,nn
~
COLUMN
ADDRESS
MXX¥NxN-X
I\-
:"X
,x
I-IIRRHI-IRCS-j
W
VIHVtL_
i&.i&.
~
.~
'(xxxx :xxx.f-
-
ICAC
tRAC
VOH- _ _ _ _ _ _ _ _ _ _ _ _
a
tACH
OPEN
IOFF
VOL-
WRITE CYCLE (EARLY WRITE)
IRC
RAS
IRAS
VIHVIL-
IAR
ICSH
tRSH
tRCD
CAS
VIHVIL-
i\.
\
ICAS
~IRP-!\
-ICRP-
V J
-ICPN-
IASR
A
VIH_
VIL_
W
IRAH
IASC
teAH
f--[jROW
ADDRESS
"-
r-- I--
~
. '\.lU,I'
COLUMN
ADDRESS
'6f
:XXXXX¥:J\.X
"
M.fx~
ICWL
J--Iwcs-
W
VIH_
VIL_
x.fxM ,x ,x
I-lwCHIwp
,XJ\.
:X X J\.J\.J\.X XX
X :X
xxxM
IRWL
~tWCR
IDS
0
VIH_
VIL-
a
VOHVOL-
XX
~MMf
f---
,XXT
,)IJ "-
i---IDHVALID
DATA
[V}
:'1
XXXXXX'
,J\.X
W0xl'"'X
,#Ix
IDHR
- - - -____________________
OPEN ______________________________
mDON'TCARE
c8
SAMSUNG SEMICONDUCTOR
25
KM4164B
NMOS DRAM
TIMING DIAGRAMS
(Continued)
READ·WRITEIREAD·MODIFY·WRITE CYCLE
tRWC
RAS
VIH_
VIL_
tRAS
~
~
tAR
~.
-:-tRPI--tCRP-
tCSH
r------ tRCD
CAS
A
VIHVIL-
VIH_
VIL-
-
r-:-
~
ROW
ADDRESS
tASR
tASC
-
~
tRCS
W
VIH_
~
-
~
-=i
tRSH
tCAS
1\'
I-
'I
) r-- tCPN-l'-
~
COLUMN
ADDRESS
r-
I--tCWLL~
tRWD
tCWD
I---tRWL
L
I-tw~
r---tCAC-
a
VOHVOL-
VIH_ XX
VIL-
-
f--tOFF
VALID
DATA
OPEN
tRAC
D
.'X
~
Xl~
VIL-
~
C1f2XX~
VALID
DATA
X
.Jl.XX
~X
PAGE MODE READ CYCLE
~-----------------------tRAS--------------------------~_~--~L
tAR
tRP
tRSH
tCRPt------t
tOFF
a
VOH- __________~_
VOL{RRH
~
tRCS
VIH_
i2~~~~1_-----------,~~r--------------t}----------~------_,~~~
VIL_
mmOON'TCARE
c8
SAMSUNG SEMICONDUCTOR
26
NMOS DRAM
KM41648
TIMING DIAGRAMS (Continued)
I
PAGE MODE WRITE CYCLE
RAS
V,H_
V,L-
eAS
V,HV,L_
A
W
D
VIH_
V,L-
V,H_
V'L_
V,H_
VIL-
tDHA
~·ONLY REFRESH CYCLE
Note: CAS V,H W,D Don't care
=
=
tRAs-------I
V,H_ - - - - - - - - - -
~tAsA
A
~::~ ~-R-O..;W-AD-D-R-E-S-S
Q
VOH- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OPEN - - - - - - - - - - - - - - - - - - - VOL-
~DON'TCARE
=8
SAMSUNG SEMICONDUCTOR
27
KM4164B
NMOS DRAM
TIMING DIAGRAMS (Continued)
HIDDEN REFRESH CYCLE
lAC
IRAS
RAS
V,HV,L_
IRC
IRAS~
!--IRP-
!---IRP-
~
IAR---j
I\-
i---IRSHI----IACO
CAS
V'H_
V,L-
~
~
VI
V,H_
V,L_
tllllM .~
ROW
ADDRESS
II)
\
COLUMN
ADDRESS
~
IASR
~
-
IASC
V'H_
V,L-
a
ICAS
~
A
I ICRP
')(X,
~
'Y)(
ROW
ADDRESS
1=
---ICPN--1
IRAH
:XX xxxxxxxXX xXVvN
-1 IRCS
1I
VOHVOL-
~
I'<)&X
,x.f>tM.lf//XXXX'i.'l'h r~
'YVVY
~
IRAC
ICAC
-
-----\I~
IOFF
l'-----VALI
DATA
D
KM4164B OPERATION
Device Operation
FiAS
The KM4164B contains 65,536 memory locations. Six·
teen address bits are required to address a particular
memory location. Since the KM4164B has only 8 address
input pins, time multiplexed addressing is used to in·
put 8 row and 8 column addresses. The multiplexing is
controlled by the timing relationship between the row
address strobe (RAS), the column address strobe (CAS)
and the valid address inputs.
The minimum RAS and CAS pulse width are specified
by tRAs(min) and tCAs(min) respectively. These minimum
pulse widths must be satisfied for proper device opera·
tion and data integrity. Once a cycle is initiated by bring·
ing RAS low, it must not be aborted prior to satisfying
the minimum RAS and CAS pulse widths. In addition,
a new cycle must not begin until the minimum RAS
precharge time, tRP, has been satisfied. Once a cycle
begins, internal clocks and other circuits within the
KM4164B begin a complex sequence of events. If the
sequence is broken by violating minimum timing reo
qUirements, loss of data integrity can occur.
Operation of the KM4164B begins by strobing in a valid
row address with RAS while CAS remains high. Then the
address on the 8 address input pins is changed from
a row address to a column address and is strobed in
by CAS. This is the beginning of any KM4164B cycle in
which a memory location is accessed. The specific type
of cycle is determined by the state of the write enable
pin and various timing relationships. The cycle is ter·
minated when both RAS and CAS have returned to the
high state. Another cycle can be initiated after RAS reo
mains high long enough to satisfy the RAS precharge
time (tAP) requirement.
c8
SAMSUNG SEMICONDUCTOR
and CAS Timing
Read
A read cycle is achieved by maintaining the write enable
input (W) high during a RAS/CAS cycle. The output of
the KM4164B remains in the Hi·Z state until valid data
appears at the output. If CAS goes low before tACO(max),
the access time to valid data is specified by tRAG, If CAS
goes low after tRCO(max), the access time is measured
28
KM41648
DEVICE OPERATION
NMOS DRAM
(Continued)
from CAS and is specified by tCAC. In order to achieve
the minimum access time, tRAdmin), it is necessary to
bring CAS low before tRCD(max).
Hi-Z Output State: Early Write, RAS-only Refresh, Page
Mode write, CAS-only cycle.
Indeterminate Output State: Delayed Write
Write
The KM4164B can perform early write, late write and
read-modify-write cycles. The difference between these
cycles is in the state of data-out and is determined by
the timing relationship between Vii and CAS. In any type
of write cycle, Data-in must be valid at or before the faIling edge of Vii or CAS, whichever is later.
Early Write: An early write cycle is performed by bringing W low before CAS. The data at the data input pin
(D) is written into the addressed memory cell.
Throughout the early write cycle the output remains in
the Hi-Z state. This cycle is good for common 1/0 applications because the data-in and data-out pins may
be tied together without bus contention.
Read-Modify-Write: In this cycle, valid data from the addressed cell appears at the output before and during the
time that data is being written into the same cell location. This cycle is achieved by bringing Vii low after CAS
and meeting the data sheet read-modify-write cycle timing requirements. This cycle requires using a separate
1/0 to avoid bus contention.
Late Write: If Vii is brought low after CAS, a late write
cycle will occur. The late write cycle is very similar to
the read-modify-write cycle except that the timing
parameters, tRWD and tCWD, are not necessarily met. The
state of data-tRWo(min), the cycle is a late write cycle and the data output will contain data read from
the selected cell. If neither of the above conditions are met, the condition of the data out (at access time until
CAS goes back to V,H) is indeterminate.
TIMING DIAGRAMS
READ CYCLE
tRC
tRAS
RAS
V,H_
V,L_
tAR
r'\
tCSH
I---tRco
tRSH
teAs
VIH_
CAS
tAse
A
VIL-
~
r- tASR -
ROW
ADDRESS
~
........
_tCPN_
teAH
D - - tRAH
VIH-
I /f-
\ \
V,L·-
f---,--tRPj--tCRP-
COLUMN
ADDRESS
~Jf\
.\;
"-
:~xiUX
.XX
I--ltRRH-
-
r-tRCS --1
W
VIH_
VIL-
l&J2Sc
~
tCAC
tRAC
Q
VOH-
tRCH
-
tOFF
_ _ _ _ _ _ _ _ _ _ _ _ OPEN
VOL-
t&8&1
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
36
KM41256A1KM41257A
TIMING DIAGRAMS
NMOS DRAM
(Continued)
WRITE CYCLE (EARLY WRITE)
I
IRC
RAS
tRAS
V,HV,L-
IAR
\
1----tACO
V,H_
CAS
rL-IRP-ICRP-
ICSH
tASH
teAs
~ \
V'L_
-- /
J
-ICPN-
tASR
~
A
VIHV'L_
W
IASC
tRAH
H -
ROW
ADDRESS
I-----
l-
.........
---
~
COLUMN
ADDRESS
V,H-
V'L-
MMxxx
Iwp
U
.~,l'x~
.f
XXXXA.
:XX .XXX
tCWL
_Iwcs·
W
I\-
teAH
r- IWCH '~xU¥Xx"XxN
y 'y¥.
)t'
.XXX
l~xXll>
tRWL
tWCA
IDSD
VIHV,L-
XXXXXX:M
r--
t--IDHVALID
DATA
XYxb
IX'.fV11:xx
XXX
'XxN¥l..f
:XXXX ,XJlJl
XXXxx\x
tOHR
a
VOH_
VOL-
--------------------------------OPEN----------------------------------
READ·WRITE/READ·MODIFY·WRITE CYCLE
tRWC
RAS
VIH_
V,l_
tRAS
~
IAR
I---;-IRP-ICRP-
tCSH
j----IRCD
CAS
A
teAS
V'H_
Vil_
VIHV,L_
tASR
-
r:-
~
ROW
ADDRESS
-
~
VIH_
V,L_
........
~
~
--j
I-
_ICPN-1'-
~
[QQ<,cY
COLUMN
ADDRESS
.XJlA
ICWD
a
L
I--IWP-=!
V'HVIL-
-
_tOFF
VALID
DATA
OPEN
~~
tRAC
D
I---IRWL-
XX~
f----ICAC-
VOHVOL-
V
.X
I--- tCWL----1
tRWD
~
i'-
t I
1\.'
tAse
IRCS
W
tRSH
.XXX~W~
VALID
DATA
~XX
,f
~DON'TCAAE
c8
SAMSUNG SEMICONDUCTOR
37
KM41256A1KM41257A
TIMING DIAGRAMS
NMOS DRAM
(Continued)
PAGE MODE READ CYCLE (KM41256A)
CAS
V,HV,L-
A
V,HV,L-
Q
-+-_
VOH- _ _ _ _ _
VOL-
PAGE MODE WRITE CYCLE (KM41256A)
CAS
VIHV,L_
A
V,H_
V,L_
W
V'H_
V,L_
e
V'H_
V,L-
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
38
KM41256A1KM41257A
TIMING DIAGRAMS
NMOS DRAM
(Continued)
NIBBLE MODE READ CYCLE (KM41257A)
V'H-
I
'!l'nI~++--""""ll
V'L-
A
w
Q
V,HV,L-
V,H-
1n,~::'0.
0>
.... >o
d
0.150 (3.81)
TYP
0.320 (8.13)
0.327 (8.31)
16·LEAD PLASTIC ZIG·ZAG IN-LINE PACKAGE
0.805 (20.45)
0.113 (2.87)
0.815 (20.70)
0.123 (3.12)
~\
roM
"
....
~e.
~ ~
C"! "!
o 0
O--INDEX
0.068 (1.73)
0.072 (1.83)
-+---'"""
0.008 (0.20)
0.012 (0.30)
0.018(0.46)
0.022(0.56)
=8
~
SAMSUNG SEMICONDUCTOR
0.05Q(1.27)
TYP
0.120 (3.05)
MIN
0.100 (2.54)
TYP
46
KM41464A
NMOS DRAM
64K x 4 Bit Dynamic RAM with Page Mode
FEATURES
GENERAL DESCRIPTION
• Performance range
The KM41464A isa fully decoded 65,536x4 NMOS
Dynamic Random Access MemOlY. The design is optimiz·
ed for high speed, high performance applications such
as computer memory, buffer memory, peripheral storage
and environments where low power dissipation and
compact layout are required.
tRAC
•
•
•
•
•
•
•
•
tRC
tCAC
KM41464A·12
120ns
60ns
220ns
KM41464A·15
150ns
75ns
260ns
The KM41464A features page mode which allows
high speed random access of memory cells within the
same row. CAS·before·RAS refresh capability provides
on·chip auto refresh as an alternative to RAS·only reo
fresh. Multiplexed row and column address inputs per·
mit the KM41464A to be housed in standard packages.
Page Mode capability
CAS·before·RAS Refresh capability
~·only and Hidden Refresh capability
TTL compatible inputs and outputs
Early Write or Output Enable Controlled Write
Single +5V:!:10% power supply
256 cycle/4ms refresh
JEDEC standard pinout in 18·pin DIP,
18·lead PLCC and 20.p.in ZIP.
The KM41464A is fabricated using Samsung'sadvanc·
ed silicon gate NMOS process. This process, coupled
with single transistor memory storage cells, permits
maximum circuit density and minimal chip size.
Clock timing requirements are noncritical, and power
supply tolerance is very wide. All inputs and outputs are
TTL complible.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
• KM41464AP
RAS
CAS
IN
• KM41464AJ
DATA IN
BUFFER
• KM41464AZ
CAS
D03
DATA
OUT
BUFFER
DO,
Ao
TO
DO.
A'
A2
COUUMN DECODER
SENSE AMPS
AO
'"wa:
IL
IL
:::>
'"'"
'"a:w
0
0
A7 «
& 1/0
GATINGS
a:
W
0
0
0
w
0
~a:
MEMORY ARRAY
MEMORY CELLS
Pin Name
262,144
-vee
-vss
Pin Function
Ao·A7
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
W
ReadlWrite Input
OE
Output Enable
DQ,·DQ.
Data InlOut
Vee
Power (+5V)
Vss
Ground
47
I
NMOS DRAM
KM41464A
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Rating
Units
Voltage on any pin relative to Vss
VIN, VOIJT
-1 to +7.0
V
Voltage on Vcc supply relative to Vss
Vcc
-1 to +7.0
V
Storage Temperature
Tstg
-55 to +150
·C
Power Dissipation
Po
1.0
W
50
mA
Short Circuit Output Current
los
"Note: Permanent device damage may occur of ABSOLUTE MAXIMUM RATINGS are exceeded. Functional opera·
tion should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
(Voltages referenced to Vss, TA=O to 70·C)
Min
Typ
Max
Unit
V
Supply Voltage
Vcc
4.5
5.0
5.5
Ground
Vss
0
0
0
Input High Voltage
VIH
2.4
Input Low Voltage
VIL
-1.0
-
V
Vcc+ 1
V
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
OPERATING CURRENT"
(RAS and CAS cycling; @tRC= min.)
Symbol
KM41464A·12
KM41464A·15
STANDBY CURRENT
(RAS = CAS = VIH after 8 RAS cycles min.)
Icc,
Icc2
RAS·ONLY REFRESH CURRENT"
(CAS = VIH, RAS cycling; @tRC= min.)
KM41464A·12
KM41464A·15
IcC3
PAGE MODE CURRENT"
(RAS=VIL, CAS cycling; @tpc=min.)
KM41464A·12
KM41464A·15
Ico.
CAS·BEFORE·RAS REFRESH CURRENT
(RAS cycling; @tRc=min.)
KM41464A·12
KM41464A·15
1CC5
Min
Max
Units
-
75
65
mA
mA
4.5
mA
65
60
mA
mA
55
45
mA
mA
65
60
mA
mA
INPUT LEAKAGE CURRENT
(Any input 0~VIN:s:5.5V, Vcc = 5.5V, Vss = OV,
all other pins not under test =0 volts.)
IlL
-10
10
p,A
OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV:s:VolJT:s:5.5V
IDOL
-10
10
p,A
OUTPUT HIGH VOLTAGE LEVEL (loH=-5mA)
VOH
2.4
-
V
OUTPUT LOW VOLTAGE LEVEL (loL=4.2mA)
VOL
-
0.4
V
"Note: Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open .
. Icc is specified as an average current.
c8
SAMSUNG SEMICONDUCTOR
48
KM41464A
NMOS DRAM
CAPACITANCE
(TA=25·C)
Parameter
Symbol
Input Capacitance (Ao-A7)
Input Capacitance
(RAS, CAS,
W, OE)
Output Capacitance (00,-00.)
AC CHARACTERISTICS
C1N '
C1N2
Coo
Min
Max
Unit
-
7
pF
10
pF
7
pF
I
(0·CsTAs70·C, Vcc=5.0V±10%. See notes 1,2)
KM41464A STANDARD OPERATION
KM41464A-12
Parameter
Unit
Min
-
KM41464A-15
Symbol
Max
Min
Notes
Max
Random read or write cycle time
tRC
220
260
ns
Read-modify-write cycle time
tAWC
305
355
ns
Access time from RAS
tRAC
120
150
ns
3, 4
Access time from CAS
tCAC
60
75
ns
3, 5
0
40
ns
6
3
50
ns
Output buffer turn-off delay time
0
30
tOFF
Transition time (rise and fall)
RAS precharge time
IT
3
50
tRP
90
RAS pulse width
tRAS
120
RAS hold time
tRSH
60
65
CAS precharge time (all cycles except page mode)
tCPN
30
35
CAS pulse width
tCAS
60
CAS hold time
tCSH
120
RAS to CAS delay time
tRCD
25
CAS to RAS precharge time
tCRP
10
100
10,000
10,000
150
75
ns
10,000
ns
ns
10,000
25
ns
ns
150
60
ns
75
ns
10
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
15
15
ns
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
20
25
ns
Column address hold time referenced to RAS
tAR
80
100
ns
Read command set-up time
tRCS
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
ns
Read command hold time referenced to RAS
tRRH
20
20
ns
Write command set-up time
twcs
0
0
ns
Write command hold time
tWCH
40
45
ns
Write command pulse width
twp
40
45
ns
Write command to RAS lead time
tAWl
40
45
ns
Write command to CAS lead time
tCWl
40
45
ns
=8
SAMSUNG SEMICONDUcroR
4
7
49
NMOS DRAM
KM41464A
KM41464A STANDARD OPERATION (Continued)
Parameter
Symbol
KM41464A·12
Min
Data·in set·up time
Max
KM41464A·15
Min
Units
Notes
Max
tos
0
0
ns
tOH
40
45
ns
CAS to write enable delay time
tewo
100
120
ns
7
RAS to write enable delay time
tRWO
160
195
ns
7
Write command hold time referenced to RAS
tWCR
100
120
ns
Data·in hold time referenced to RAS
tOHR
100
120
Access time from OE
tOEA
OE to Data in delay time
Data·in hold time
ns
40
30
40
ns
ns
tOEO
30
Output Buffer turn off delay from OE
tOEZ
0
OE hold time referenced to W
tOEH
25
25
ns
OE to RAS inactive setup time
tOES
0
0
ns
Din to CAS delay time
tozc
0
0
ns
8
Din to OE delay time
tozo
0
0
ns
8
Refresh period (256 cycles)
tREF
30
0
4
40
4
ns
ms
KM41464A CAS·BEFORE·RAS REFRESH
CAS setup time (CAS·before·RAS Refresh)
tCSR
25
30
ns
CAS hold time (CAS·before·RAS Refresh)
tCHR
55
60
ns
tPRC
20
20
ns
RAS precharge to CAS hold time
KM41464A PAGE MODE
Page mode cycle time
CAS precharge time (page mode only)
NOTES
1. An initial pause of 1001'S is required after power·up
followed by any 8 RAS cycles before proper device
operation is achieved.
2. V'H(min) and V'L(max) are reference levels for
measuring timing of input signals. Transition times
are measured between V'H(min) and V,dmax) and are
assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TIL loads and
1oopF.
4. Operation within the tRCo(max) limit insures that
tRAC(max) can be met. tRCO(max) is specified as a
reference point only. If tRCO is greater than the
specified tACo(max) limit, then access time is con·
trolled exclusively by tCAC.
5. Assumes that tACOO!:: tRco(max).
c8
SAMSUNG SEMICONDUCTOR
6. This parameter defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
7. tewo and t AWO are restrictive operating parameters for
the read·modify·write cycle only. If twcsO!::twcs(min),
the cycle is an early write cycle and the data output
will remain open circuit throughout the entire cycle.
If tewoO!::tcwo(min) and tAWo>tAWo(min), the cycle is a
late write cycle and the data output will contain data
read from the selected cell. If neither of the above
conditions are met, the condition of the data out (at
access time until CAS goes back to V'H) is indeter·
minate.
8. Either tozc or tozo must be" satisfied for all cycles.
50
NMOS DRAM
KM41464A
TIMING DIAGRAMS
•
READ CYCLE
tRC
1-------tRAs
VIHVIL_
RAS
1-------tcSH--+-----~
1-_+_
tRCo _ _
VIH_
CAS
"'""""=r--++--""lt!-_
tRP
tCRP
VIL-
A
VIH_
W
VIHVIL-
DATA
(OUT)
VOH-
DATA
VIH_
(IN)
VIL_
VIL_
VOL-
VIH_
VIL_
OE
WRITE CYCLE (EARLY WRITE)
OE = Don't Care
A
w
DATA
(IN)
DATA
(OUT)
VOHVOL-
-------------HIGH-Z------------~oON'TCARE
c8
SAMSUNG SEMICONDUCTOR
51
KM41464A
NMOS DRAM
TIMING DIAGRAMS
(Continued)
READ·WRITEIREAD·MODIFY·WRITE CYCLE
IRWC
RAS
VIH_
VIL_
CAS
VIH_
VIL_
tRAS
tCAS
VIH_
A
VIL_
W
VIHVIL-
DATA (IN)
VIHVIL_
DAT~
VOHVOL-
DE
(OUT)
VIHVIL-
PAGE MODE READ CYCLE
1IAS
VIH_
VIL_
CAS
VIH_
VIL_
- -......U - - - - - - - - - - t R A S - - - - - - - - d - Y - - - - i :
1f'i::::::=T.;=::::::::::r;------i .......-----~f--tRP__j\_
--~~~
IRSH
~~-------
VIH_
A
VIL_
W
VIH_
VIL_
DATA
(IN)
VIH_
VIL-
DATA
(OUn
VOL-
O!:
VIHVIL-
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
52
NMOS DRAM
KM41464A
TIMING DIAGRAMS
(Continued)
PAGE MODE WRITE CYCLE
I
OE = Don't Care
A
w
DATA
(IN)
DATA
(OUT)
VOHVOL-
--------------HIGH-Z--tlt-t-------------
PAGE MODE READ·MODIFY·WRITE CYCLE
~---------------------tAAS-----------------~----~
~~~
A
w
tASH-=:i- ~tAP-J '-
V'H-
~~r.~~~~~.~~~.~~~L~~~~~_~~l~~~~~~~~~~
V,L-
t:::JJ~~ft-i!T~~~~~~~~~~~~~~~4Ju.~u.~C!~
V'H_
~m~-+-""""lIl
V'L-
DATA
(OUT)
DATA
(IN)
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
53
NMOS DRAM
KM41464A
TIMING DIAGRAMS
(Continued)
RAS-ONLY REFRESH CYCLE
NOTE: CAS
=VIH; W, OE, D =Don't Care
f----------tRC----------J
_ _ _ _ _ _ _ _""" i----tRAs---
AAS
VIHVIL-
A
VIHVIL-
DATA
(OUT)
VOH- - - - - - - - - - - - - - - H I G H - Z _ _ _ _ _ _ _ _ _ _ _ __
VOL-
CAS-BEFORE-W REFRESH CYCLE
NOTE: Address, W, OE, D = Don't Care
RAS
VIH_
VIL_
CAS
VIH_
VIL_
DATA
(OUT)
VOH_
VOL_
l-__________ HIGH.Z: _ _ _ _ _ _ _ _ _ _ _ _ __
HIDDEN REFRESH CYCLE
VIH_
i------tRC-----:----+-------..J
VIL_
tCRP
A
DATA
(OUT)
-1~-~---~V~A~L~ID~D~A~TA~O~UT~----_:_~
VOH_ -HIGH.Z ..
VOLVIH-
DATA
(IN)
VIL VIH VIL-
::f=tDZC
~
_toze
_ _ _ _ _ _ __
".
HIGH·Z--------------4
~
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
54
KM41464A
NMOS DRAM
KM41464A OPERATION
Device Operation
Write
The KM41464A contains 262,144 memory locations
organized as 65,536 x 4-bit words. Sixteen address bits
are required to address a particular 4-bit word in the
memory array. Since the KM41464A has only 8 address
input pins, time multiplexed addressing is used to input 8 row and 8 column addresses. The multiplexing is
controlled by the timing relationship between the row
address strobe (RAS), the column address strobe (CAS)
and the valid address inputs.
The KM41464Acan perform early write,and read-modifywrite cycles. The difference between these cycles is in
the state of data-out and is determined by the timing
relationship between W, OE and CAS. In any type of
write cycle, Data-in must be valid at or before the failing edge of W or CAS, whichever is later.
Operation of the KM41464A begi ns by strobi ng ina val id
row address with RAS while CAS remains high. Then
the address on the 8 address input pins is changed from
a row address to a column address and is strobed in
by CAS. This is the beginning of any KM41464A cycle in
which a memory location is accessed. The specific type
of cycle is determined by the state of the write enable
pin and various timing relationships. The cycle is ter'minated when both RAS and CAS have returned to the
high state. Another cycle can be initiated after RAS
remains high long enough to satisfy the RAS precharge
time (tAP) requirement.
RAS and CAS Timing
The minimum RAS and CAS pulse width are specified
by tAAS(min) and tCAs(min) respectively. These minimum
pulse widths must be satisfied for proper device operation and data integrity. Once a cycle is initiated by bringing RAS low, it must not be aborted prior to satisfying
the minimum RAS and CAS pulse widths. In addition,
a new cycle must not begin until the minimum RAS
precharge time, tAP, has been satisfied. Once a cycle
begins, internal clocks and other circuits within the
KM41464A begin a complex sequence of events. If the
sequence is broken by violating minimum timing requirements, loss of data integrity can occur.
Read
A read cycle is achieved by maintaining the write enable
input f'N) high during a RAS/CAS cycle. The four outputs of the KM41464A remains in the Hi-Z state until valid
data appears at the output. The KM41464A has common
data 1/0 pins. For this reason an output enable control
input (OE) has been provided so the output buffer can
be precisely controlled. For data to appear at the outputs, OE must be low for the period of time defined by
tOEA and tOEZ' If CAS goes low ,before tAco(max), the
access time to valid data is specified by tRAC. If CAS
goes low after tAco(max), the access time is measured
from CAS and is specified by tCAc. In order to achieve
the minimum access time, tRAc(min), it is necessary to
bring CAS low before tAco(max).
c8
SAMSUNG SEMICONDUCTOR
Early Write: An early write cycle is performed by bringing W low before CAS. The 4-bit wide data at the data
input pins is written into the addressed memory cells.
Throughout the early write cycle the outputs remain in
the Hi-Z state regardless of the state of the OE input.
Read-Modify-Write: In this cycle, valid data from the
addressed cell appears at the outputs before and during the time that data is being written into the same cell
locations. This cycle is achieved by bringing W low after
CAS and meeting the data sheet read-modify-write timing requirements. The output enable input (OE) must be
low during the time defined by tOEA and tOEZ for data to
appear at the outputs. 'If tCWD and tAWD are not met the
output may contain invalid data. Conforming to the OE
timing requirements prevents bus contention on the
KM41464's DQ pins.
Data Output
The KM41464A has tri-state output buffers which are controlled by CAS and OE. When either CAS or OE is high
(VI H), the output are in the high impedance (Hi-Z) state.
In any cycle in which valid data appears at the outputs,
the outputs first remains in the Hi-Z state until the data
is valid and then the valid data appears at the outputs.
The valid data remains at the outputs until CAS or OE
retums high. This is true even if a new RAS cycle occurs
(as in hidden refresh). Each of the KM41464A operating
cycles are listed below after the corresponding output
state produced by the cycle.
Valid Output Data: Read, Read-Modify-Write, Hidden
Refresh, Page Mode Read, Page Mode Read-ModifyWrite.
Hi-Z Output State: Early Write, RAS-only Refresh, Page
Mode write, CAS-only cycle.
Indeterminate Output State: Delayed Write (tewo or tRWO
are not met)
Refresh
The data in the KM41464A is stored on a tiny capacitor
within each memory cell. Due to leakage, the data will
leak off after a period of time. To maintain data integrity it is necessary to refresh each of the rows every 4
ms. There are several ways to accomplish this.
RAS-Only Refresh: This is the most common method
55
I
KM41464A
KM41464A OPERATION
NMOS DRAM
(Continued)
for performing refresh. It is performed by strobing in a
row address with RAS while CAS remains high. This
must be performed on each of the 256 row addresses
(AO-A7) every 4ms.
CAS-Before-RAS Refresh:The KM41464A has CAS-before·
RAS on-chip refreshing qapability that eliminates the
need for external refresh addresses. If CAS Is held low
for the specified set up time (tcsRJ before RAS goes low,
the on-chip refresh circuitry is enabled. An internal
refresh operation automatically occurs and the on-chip
refresh address counter is internally incremented in
preparation for the next CAS·before-RAS refresh cycle.
Hidden Refresh: A hidden refresh cycle may be performed while maintaining the latest valid data at the output
by extending the CAS active time and cycling RAS. The
KM41464A hidden refresh cycle Is actually a CAS-beforeRAS refresh cycle within an extended read cycle. The
refresh row address is provided by the on-chip refresh
address counter. This eliminates the need for the
external row address that is required in hidden refresh
cycles by DRAMS that do not have CAS-before-RAS
refresh capability.
Other Refresh Methods: It is also possible to refresh the
KM41464A by using read, write or read-modify-write cycles.
Whenever a row is accessed, all the cells in that row
are automatically refreshed. There are certain applications in which it might be advantageous to perform
refresh~his manner but in general RAS-only or CAS·
before-RAS refresh are the preferred methods.
Page Mode
Page mode memory cycles provide faster access and
lower power dissipaton than normal memory cycles. In
page mode, it is possible to perform read, write or readmodify-write cycles. As long as the applicable timing requirements are observed, it is possible to mix these
cycles in any order. A page mode cycle begins with a
normal cycle. While ~ is kept low to maintain the row
address, CAS is cycled to strobe in additional column
addresses. This eliminates the time required to set up
and strobe sequential row addresses for the same page.
Power-up
If RAS=Vssduring power-up the KM41464A\might begin
an active cycle. This condition results in higher than
necessary current demands from the power supply during power·up. It is recommended that RAS and CAS track
with Vee during power-up or be held at a valid V1H in
order to minimize the power-up current.
An initial pause of 100l'sec is required after power-up
c8
SAMSUNG SEMICONDUCTOR
followed by 8 initialization cycles before proper device
operation is assured. Eight initialization cycles are also
required after any 4 msec period in which there are no
RAS cycles. An initialization cycle is any cycle in which
FiAS is cycled.
Termination
The lines from the TIL driver circuits to the KM41464A
inputs act like unterminated transmission lines resulting
insignificant positive and negative overshoots at the
inputs. To minimize overshoot it is advisable to terminate
the input lines and to keep them as short as possible.
Although either series or parallel termination may be used, series termination is generally recommended since
it is simple and draws no additional power. It consists
of a resistor in series with the input line placed close
to the KM41464A input pin. Theoptimum valuedepends
on the board layout. It must be determined experimentally and is usually in the range of 20 to 40 ohms.
Board Layout
It is important to lay out the power and ground lines on
memory boards in such a way that switching transient
effects are minimized. The recommended methods are
gridded power and ground lines or separate power and
ground planes. The power and ground lines act like
transmission lines to the high frequency transients
generated by DRAMS. The impedance is minimized if
all the power supply traces to all the DRAMS run both
horizontally and vertically and are connected at each in·
tersection or better yet if power and ground planes are
used.
Address and control lines should be as short as possi·
ble to avoid skew. In boards with many DRAMS these .
lines should fan out from a central point like a fork or
comb rather than being connected in a serpentine pattern. Also the control logic should be centrally located
on large memory boards to facilitate the shortest possible address and control lines to all the DRAMs.
Decoupling
The importance of proper decoupling cannot be over emphasized. Excessive transient noise or voltage droop on
the Vee line can cause loss of data integrity (soft errors). The total combined voltage changes over time in
the Vee to Vss voltage (measured at the device pins)
should not exceed 500mV.
A high frequency 0.31'F ceramic decoupling capacitor
should be connected between the Vee and ground pins
of each KM41464A using the shortest possible traces.
56
KM41464A
NMOS DRAM
KM41464A OPERATION
(Continued)
These capacitors act as a low impedance shunt for the
high frequency switching transients generated by the
KM41464A and they su pply much ofthe current used by
the KM41464A during cycling.
In addition, a large tantalum capacitor with a value of
4lj.IF to 100/-IF should be used for bulk decoupling to
recharge the O.3/-1F capacitors between cycles, thereby
reducing power line droop. The bulk decoupling
capacitor should be placed near the point where the
power traces meet the power grid or power plane. Even
better results may be achieved by distributing more than
one tantalum capacitor around the memory array.
PACKAGE DIMENSIONS
18·LEAD PLASTIC DUAL IN·LlNE PACKAGE
Units: Inches (millimeters)
.1-.0-100
INDEX
0.899'(22.183)
0.909'(23.109)
0.008 (0.2)
0.012 (0.3)
0.140 (3.57)
0.180 (4.57)
0.120 (3.05)
MIN
0.100 (2.54)
0.050 (1.27)
TYP
TYP
c8
SAMSUNG SEMICONDUCTOR
0.020 (0.51)
MIN
57
•
KM41464A
NMOS DRAM
PACKAGE DIMENSIONS (Continued)
18-PIN PLASTIC LEADED CHIP CARRIER
Units: Inches (millimeters)
0.140 (3.56)
0.320 (8.13)
0.327 (8.31)
MAX
0.080 (2.03)
0.084 (2.13)
0.288 (7.31)
0.292 (7.41)
/
·n n n
0
0.020 (0.51)
~
n
0.027 (0.68)
0.031 (0.78)
1
~6)
a; a; [
0
--
~
<"!
gg "'<'Ii ...N [
'"'"
'"'" illSl[
cici
~
....
J
66[
P
.U
U
U
LJ
0.050 (1.27)
0.030 (0.76)
TYP
TYP
2O·PIN PLASTIC ZIGZAG·IN·LlNE PACKAGE
1.025 (26.04)
1.035 (26.29)
rlNDEX
?'
I
0.113 (2.87)
0.123 (3.12)
co;::""
'"
'"
!&~
"''''
'" '"
"''''
cci
I
0.018 (0.46) [
0.022 (0.58)
c8
~-
0.008 (0.20)
0.012 (0.30)
I
0.050 (1.27)
0.100(2.54)
TYP
TYP
SAMSUNG SEMICONDUCTOR
58
KM41C1000
CMOS DRAM
1M x 1 Bit Dynamic RAM with Fast Page Mode
FEATURES
GENERAL DESCRIPTION
• Performance range:
tRAc
tCAC
KM41C1000-10
100ns
25ns
190ns
KM41C1000-12
120ns
30ns
220ns
tRC
• Fast Page Mode operation
• CAS-before-RAS refresh
·IRAS-onlyand Hidden Refresh
• TTL compatible inputs and output
• Common I/O using early write
• Single + 5V ± 10% power supply
• 512 cycle/8ms refresh
• 256K x 4 fast test mode
• JEDEC standard pinout available in Plastic DIP,
SOJ, ZIP packages_
The Samsung KM41C10oo is a CMOS high speed
1,048,576 x 1 Dynamic Random Access Memory. Its
design is optimized for high performance applications
such as mainframes and mini computers, graphics and
high performance microprocessor systems.
The KM41C1000 features Fast Page Mode operation
which allows high speed random access of memory
cells within the same row.
CAS-before-RAS Refresh capability provides on-chip
auto refresh as an alternative to RAS-only Refresh. All
inputs and output are fully TTL compatible.
The KM41C1000 is fabricated using Samsung's
advanced CMOS process.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
• KM41C1000P
RAS_r-----,
• KM41C1000J
D
w_.,...,.__---'
CAS
W[
D
AO
6
A1
7
15
14
13
12
11
T.F.
SENSE AMPS & 1/0 GATINGS
AO-f~L-r---------'-----
'"
a:
w
~
:::>
tRwL
'---j tWCR
I--
tDS
0
VIH_
VIL-
hhxxxw
t---tDH-
:XXXAJr
XXAXXXI'"
VALID
DATA
,x
:XXXXXAXX
:XXXAX
x
AX
.XXXJ(
.X ,xx
tDHA
a
VOH_
VOL-
- -....................- - - -....................- - - -....... OPEN .....- -..........- -...................................................
READ·WRITEIREAD·MODIFY·WRITE CYCLE
tRWC
RAS
VIH_
VIL_
tRAS
""""""""""'I
tAR
--,-tRP-
tCSH
~tRCD
CAS
A
tCAS
VIHVIL-
VIHVIL-
-
tASR
~
r------tRAD--;-i
tAse
~
ROW
ADDRESS
iN
a
VIH_
VIL_
J(XJ(X
..........
'\AoAI'
---j
,xXJt:Hi
j
~
COLUMN
ADDRESS
~
tRCS
f-
tRWD
tCWD
_tw;=:.j
I---tCLZ
OPEN
~It"
tRAC
0
t----tCWL_~
-tAWL
L
t--;~~
.AAX
.xxxNitI).
JJ
.X :X
tAWD
,J(
I---tCPN~
tRAL
[((XXXXXXXAXXX
tM
VOHVOL-
VIHVIL_
~
\'
- -
I-:-
'--
~tCRP-
tRSH
-
f-tOFF
VALID
DATA
~~
VALID
DATA
x
~XXXJlAX~XXXXXXXW
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
64
KM41C1000
CMOS DRAM
TIMING DIAGRAMS
FAST PAGE MODE READ CYCLE
I
~--~---------------------IMSP--------------------------~ ~____~
RAS
VIH-
IAR
VIL-
IRP
ICSH
IpC
CAS
A
a
ICRP
VIH-
VIL-
VIHVIL-
-+
VOH- __________
VOL-
w
FAST PAGE MODE WRITE CYCLE
I---------------------------IRASP---------------------------i
RAS
VIH-
CAS
VIHVIL-
A
VIH-
VIL-
VIL-
W
VIHVIL-
0
VIHVILIOHR
a
VOH-
------------------------------~OPEN------------------
_________________
VOL!-
~
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
65
KM41C1000
TIMING DIAGRAMS
CMOS DRAM
(Continued)
FAST PAGE MODE READ-WRITE CYCLE
tAASP
V,H RAS
V,L tCSH
tASH
r---tPAWC
tCAP
tACO
tCAS
tcp
tcp
tCAS
tCAS
V,H CAS
V,L -
A
V,H -
A)~1\j\'7'dV\jI\AA7';r-t--+"""'
V,L - .t::.I.~~c.t;~~'.Y
o
V,H - "lr':1MI"7t"'lr-rint'"lrJt:"lr.Int'"klMO:'1I
V,L -
Q
.t;,L~~Cl4~::i:lC::L~+-lUUV
VOHVOL -
----------------~~
~
c8
SAMSUNG SEMICONDUCTOR
DON't CARE
66
KM41C1000
CMOS DRAM
TIMING DIAGRAMS
(Continued)
RAS·ONLY REFRESH CYCLE
Note: CAS = V,H, W,D, Ag = Don't Care
•
tAAS - - - - - - - i
RAS
V'H_
VJL_
~tASR
~:~.=- ~
A
ROW ADDRESS
VOH- _______________________________
_______________________________
OPEN
a
VOL-
HIDDEN REFRESH CYCLE
f---------tAC-------4-----tAC---i----tAAS-------i
RAS
VIH-
tAP
f-----tAAS
---tAR
V'l_
-tASH
tACO-+--t--+t----tcAS----------j
CAS
VIH_
VIL-
VIH_
A
VIL-
VIH_
W
VIL-
AA
~
tRAC-~~~
VOH-
a
_ ________________~tCLZ
~------------------------------VALID
DATA
------------------------
VOL-
CAS·BEFORE·RAS REFRESH CYCLE
RAS
VIH -
f---------tRC:------------i
tAP
- - - - - - ' " i - - - - - t R A S - - - - - - - i iI---~----,J
V,L -
CAS
V'HV,L -
a
VOHVOL-
--------------OPEN--------------------mDON'TCARE
c8
SAMSUNG SEMICONDUCTOR
67
KM41C1000
CMOS DRAM
TIMING DIAGRAMS (Continued)
CAS-BEfORE-RAS REfRESH COUNTER TEST CYCLE
tAP
hAAS
RAS
VIH-
i\
VIL-
CAS
VIHVIL-
A
VIHVIL-
~
tCAS
tASC
-
~X XXXXXXX XXXXXXXx XX£YJ(
~
,¥X¥0x
xx
X
tRAL
r-tAA-
~F
~~
VOHVOL-
VIHVIL -
t
COWMN ~XXXX
ADDRESS
xxx
I-
1\
VALID DATA
~
l-
tACS
W
I
_tCH:JF==,
READ CYCLE
Q
J
I
tASH
.r.
tAAH
I-
~~~~~~~~~~~~~~~~~~y
tACH
WRIT': CYCLE
Q
tRWL
VOH_
OPEN
VOL-
tCWL
twos
W
D
VIHVIL-
VIHVIL-
r--tWc~=:j
f-
'l'l0l':ll XlxXlxX X~XxX~X.fll\
twp
-
tos
r-
ll>&N0l'UxNflxNXY \l.
i-
READ·WRITE CYCLE
Q
X~
VALID DATA
~
1:1lNM
W
:/Y::lXx&.
f-tAA-
-
r-t~
VOHVOL-
.X~X
tOH
VALID DATA
tre- ~
t-
~F
~
tCWL
-tAWO-tAwL-
-tcwo-
W
D
VIH-
x xx
~
lx~XVtl/
"
~,
If-~
VILI-
XX~X~"''''''''''~
VIHVIL'-
~NX X~X"'~X"'XXX XXX XXX~XXXXXXX~VALID DATA~YxXXXX~XX Xx
r
~
~
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
68
CMOS DRAM
KM41C1000
KM41C1000 OPERATION
Device Operation
Write
The KM41C1000 contains 1,048,576 memory locations.
Twenty address bits are require9 to address a particular memory location. Since the KM41C1000 has only 10
address input pins, time multiplexed addressing is used
to input 10 row and 10 column addresses. The multiplexing is controlled by the timing relation.ship between the
row address strobe (RAS), the column address strobe
(CAS) and the valid row and column address inputs.
Operation of the KM41C1000 begins by strob[ng in
a valid' row address with RAS while CAS remains high.
Then the address on the 10 address input pins is
changed from a row address to a column address and
is strobed in by CAS. This is the beginning of any
KM41C1000 cycle In which a memory location is accessed. The specific type of cycle is determined by the
state of the write enable pin and various timing relationships. The cycle is terminated when both RAS and CAS
have returned to the high state. Another cycle can be
initiated after RAg remains high long enough to satisfy the RAS precharge time (tRP) requirement.
The KM41C1000 can perform early write, late write
and read-modify·write cycles. The differece between
these cycles is in the state of data-out and is determined
by the timing relationship between Wand CAS. In any
type of write cycle, Data-in must be valid at or before
the falling edge of W or CAS, whichever is later.
RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tCAS(min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is initiated by bringing RAS low, it must not be aborted prior
to satisfying the minimum RAS and CAS pulse widths.
In addition, a new cycle must not begin until the minimum RAS precharge time, tRP, has been satisfied. Once
a cycle begins, internal clocks and other circuits within
the KM41C1000 begin a complex sequence of events.
If the sequence is broken by violating minimum timing
requirements, loss of data integrity can occur.
Read
A read cycle is achieved by maintaining the write enable input(Wj high during a RAS/CAS cycle. The access
time is normally specified with respect to the falling
edge of RAS. But the access time also depends on the
falling edge of CAS and on the valid column address
transition.
If CAS goes low before tRCD(max) and if the column
address is valid before tRAD(max) then the access time
to valid data is specified by tRAC(min). However, if CAS
goes low after tRCD(max) or if the column address becomes valid after tRAD(max), the access time is specified by tCAC or tAA. In, order to achieve the minimum
access time, tRAC(min), it is necessary to meet both
tRCD(max) and tRAD(max).
c8
SAMSUNG SEMICONDUCTOR
Early Write: An early write cycle is performed by bringing W low before CAS. The data at the data input pin
(D) is written into the addressed memory cell. Throughout the early write cycle the output remains in the Hi-Z
state. This cycle is good for common 1/0 applications
because the data-in and data-out pins may be tied
together without bus contention.
Read-Modify·Write: In this cycle, valid data from the ad·
dressed cell appears at the output before and during
the time that data is being written into the same cell
location. This cycle is achieved by bringing W low after CAS and meeting the data sheet read-modify-write
cycle timing requirements. This cycle requires using a
separate 1/0 to avoid bus contention.
Late Write: If W is brought low after CAS, a late write
cycle will occur. The late write cycle is very similar to
the read-modify-write cycle except that the timing
parameters, tRWD, tCWD and tAWD, are not necessarily
met. The state of data-out is indeterminate since the output can be either Hi-Z or contain data depending on the
timing conditions. This cycle requires a separate 1/0 to
avoid bus contention.
Data Output
The KM41C1000 has a tri-state output buffer which
is controlled by CAS. Whenever CAS is high (VIH) the
output is in the high impedance (Hi-Z) state. In any cycle in which valid data appears at the output the output goes into the low impedance state in a time
specified by tCLl after the falling edge of CAS. Invalid
data may be present at the output during the time after
tCLl and before the valid data appears at the output.
The timing parameters tCAC, tRAC and tAA specify
when the valid data will be present at the output. The
valid data remains at the output until CAS returns high.
This is true even if a new RAS cycle occurs (as in hidden refresh). Each of the KM41C1000 operating cycles
is listed below after the corresponding output state
produced by the cycle.
69
•
CMOS DRAM
KM41C1000
DEVICE OPERATION
(Continued)
CAS·before·RAS Refresh Counter Test Cycle
Valid Output Data: Read, Read-Modify-Write, Hidden
Refresh, Fast Page Mode Read, Fast Page Mode Read,
Modify-Write.
,
Hi-Z Output State: Early Write, RAS-only Refresh, Fast
Page Mode Write, CAS-before-RAg Refresh, CAS-only
cycle.
Indeterminate Output State: Delayed Write
Refresh
The data in th!l KM41C1000 is stored on a tiny capacitor within each memory cell. Due to leakage the data
may leak off after a period of time. To maintain data integrity it is necessary to refresh each of the rows every
8 ms. Either a burst refresh or distributed refresh may
be used. There are several ways to accomplish this.
RAS-Only Refresh: T.his is the most common method
for performing refresh. It is performed by strobing in a
row address with RAS while CAS remains high. This cy·
cle must be repeated for each of the 512 row addresses,
(AO-A8). The state of address A9 is ignored during
refresh.
CAS-before-RAS Refresh: The KM41C1000 has CAS·
before-RAS on-chip refresh capability that eliminates the
need for external refresh addresses. If CAS is held low
for the specified set up time (tCSR) before RAS goes
low, the on-chip refresh circuitry is enabled. An inter·
nal refresh operation automatically occurs. The refresh
address is supplied by the on-chip refresh address counter which is then internally incremented in preparation
for the next CAS-before-RAS refresh cycle.
Hidden Refresh: A hidden refresh cycle may be per·
formed while maintaining the latest valid data at the output by extending the CAS active time and cycling RAS.
The KM41C1000 hidden refresh cycle is actually a CASbefore-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip
refresh address counter.
Other Refresh Methods: It is also possible to refresh
the KM41C1000 by using read, write or read-modify-write
cycles. Whenever a row is accessed, all the cells in that
row are automatically refreshed. There are certain applications in which it might be advantageous to perform
refresh in this manner but in general RAS-only or CASbefore-RAS refresh is the preferred method.
c8
SAMSUNG SEMICONDUCTOR
A special timing sequence using the CAS-before-RAS
refresh counter test cycle provides a convenient method
of verifying the functionality of the CAS-before-RAS
refresh activated circuitry. The cycle begins as a CAS·
before·RAS refresh operation. Then, if CAS is brought
high and then low again while RAS is held low, the read
and write operations are enabled. In this mode, the row
address bits AO through A8 are supplied by the on-chip
refresh counter. The A9 bit is set high internally.
Fast Page Mode
The KM41C1000 has Fast Page mode capability which
provides high speed read, write or read·modify-write access to all memory cells within a selected row. These
cycles may be mixed in any order. A fast page mode
cycle begins with a normal cycle. Then, while RAS is
kept low to maintain the row address, CAS is cycled to
strobe in additional column addresses. This eliminates
the time required to set up and strobe sequential row
addresses for the same page.
Power·up
=
If RAS Vss during power-up, the KM41C1000 could
begin an active cycle. This condition results in higher
than necessary current demands from the power sup·
ply during power-up. It is recommended that RAS and
CAS track with Vee during power-up or be held at a
valid VIH in order to minimize the power-up current.
An initial pause of 200 /Lsec is required after powerup followed by 8 initialization cycles before proper
device operation is assured. Eight initialization cycles
are also required after any 8 msec period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
Termination
The lines from the TTL driver circuits to the
KM41C1000 inputs act like unterminated transmission
lines resulting in significant positive and negative over·
shoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them as
short as possible. Although either series or parallel termination may be used, series termination is generally
recommended since it is simple and draws no additional
power. It consists of a resistor in series with the input
line placed close to the KM41C1000 input pin. The optimum value depends on the board layout. It must be
determined experimentally and is usually in the range
of 20 to 40 ohms.
70
CMOS DRAM
KM41C1000
DEVICE OPERATION
(Continued)
Board Layout
Decoupling
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended methods
are gridded power and ground lines or separate power
and ground planes. The power and ground lines act like
transmission lines to the high frequency transients
generated by DRAMS. The impedance is minimized if all
the power supply traces to all the DRAMS run both horizontally and vertically and are connected at each intersection or better yet if power and ground planes are used.
Address and control lines should be as short as possible to avoid skew. In boards with many DRAMS these
lines should fan out from a central point like a fork or
comb rather than being connected in a serpentine pat·
tern. Also the control logic should be centrally located
on large memory boards to facilitate the shortest possible address and control lines to all the DRAMS.
The importance of properdecoupling can not be over
emphasized. Excessive transient noise or voltage droop
on the Vee line can cause loss of data integrity (soft errors). It is recommended that the total combined voltage changes-over time in the VCC to VSS voltage
(measured at the device pins) should not exceed SOOmV.
A high frequency O.3I'F ceramic decoupling capaci·
tor should be connected between the Vee and ground
pins of each KM41Cl000 using the shortest possible
traces. These capacitors act as a low impedance shunt
for the high frequency switching transients generated
by the KM41Cl000 and they supply much of the current
used by the KM41Cl000 during cycling.
In addition, a large tantalum capacitor with a value
of 471'F to lOOI'F should be used for bulk decoupling
to recharge the O.3I'F capacitors between cycles, thereby reducing power line droop. The bulk decoupling capacitor should be placed near the point where the power
traces meet the power grid or power plane. Even better
results may be achieved by distributing more·than one
tantalum capacitor around the memory array.
PACKAGE DIMENSIONS
Units: Inches (millimeters)
18·LEAD PLASTIC DUAL IN·LlNE PACKAGE
18
17
16
15
14
13
12
11
10
~{ : : : : : : :311
.
\
1
0.8605 (21.84)6
0.875 (22.23)
8
~
~
0.008(0.~
0.012 (0.30)
0.020 (0.51)
MIN
0.197(5.00)
~
0.135 (3.43)
).145 (3.68)
0.100 (2.54)
TYP
ciS
0.047 (1.19)
0.059 (1.49)
SAMSUNG SEMICONDUCTOR
~
•
0.118(3.00)
~
~032
(0.81)
0.040 (1.02)
71
I
CMOS DRAM
KM41C1000
PACKAGE DIMENSIONS
20/26-PIN PLASTIC SMALL OUT·LINE J·LEAD
Unit: Inches (millimeters)
0.093 (2.36)
0.103 (2.62)
I
--- -
I
----,- - - - -
---tgj
I
INDEX DOT
~
do
0.129 (3.04)
0.140 (3.56)
2O-LEAD PLASTIC ZIGZAG·IN·LlNE PACKAGE
1.025 (26.04)
1.035 (26.29)
~
rI
0.Q18 (0.46)
0.022 (0.56)
c8
I ~~
Units: Inches (millimeters)
---1
0.113 (2.87)
0.123 (3.12)
~~
e.e.
INDEX
'"o '"cigs
l:j
.0.008 (0.20)
I
0.012 (0.30)
0.050 (1.27)
0.100 (2.54)
TYP
TYP
SAMSUNG SEMICONDUCTOR
72
PRELIMINARY SPECIFICA TlON
CMOS DRAM
KM41C1001
1M X 1 Bit Dynamic RAM with Nibble Mode
FEATURES
GENERAL DESCRIPTION
• Performance range:
•
•
•
•
•
•
•
•
•
t RAC
tCAC
tRC
KM41C1001-10
100ns
25ns
190ns
KM41C1001-12
120ns
30ns
220ns
Nibble Mode Operation
CAS-before-RAS Refresh
RAS-only and Hidden Refresh
TTL compatible inputs and output
Common 110 using early write
Single +5V:!:10% power supply
512 cycle/8ms refresh
256K)( 4 fast test mode
JEDEC standard pinout available in Plastic DIP,
SOJ, ZIP packages_
FUNCTIONAL BLOCK DIAGRAM
The Samsung KM41C1001 is a CMOS high speed
1,048,576 x 1 Dynamic Random Access Memory, Its
design is optimized for high performance applications
such as mainframes and mini computers, graphics and
high performance microprocessor systems.
The KM41C1001 features Nibble Mode operation
which allows high speed random access of up to 4-bits
of data.
CAS-before-RAS Refresh capability provides on-chip
auto refresh as an alternative to RAS-only Refresh. All
inputs and output are fully TTL compatible.
The KM41C1001 is fabricated using Samsung's
advanced CMOS process.
PIN CONFIGURATION
• KM41C1001P
• KM41C1001J
,..
D
Wd
RAll...-l---""
20
19
18
17
16
RAS_[ 3
CAS
.~ ~
T.F.
Vi
N.C
AO [ 6
A,
~~
A2
A3 [ 9
Vee [ 10
COWMN DECODER
0
15
14
13
12
11
• KM41C1001Z
vss
a
CAS
N.C.
A9
As
A7
A6
A5
A4
SENSE AMPS & I/O GATINGS
AO
lQ
w
a:
ED
&l
u.
u.
:::>
w
c
0
'"
ffl c
~
ga:
Pin Name
MEMORY ARRAY
1,048,576 CELLS
-Vee
a:
A9-~<~~_____________~
-Vss
Address Inputs
RAS
Row Address Strobe
D
Q
CAS
W
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Ao-Ag
Data In
Data Out
Column Address Strobe
ReadlWrite Input
Vee
Power (+5V)
Vss
Ground
T.F.
Test Function
N.C.
No Connection
N.L.
No Lead
73
•
CMOS DRAM
KM41C1002
1M x 1 Bit Dynamic RAM with Static Column Mode
FEATURES
GENERAL DESCRIPTION
• Perfonnance range:
The Samsung KM41Cl002 is a CMOS high speed
1,048,576.x 1 dynamic Random Access Memory. Its design is optimized for high performance applications
such as cache based mainframes and mini computers,
graphics, digital signal processing and high performance microprocessor systems.
•
•
•
•
•
•
•
•
•
tRAC
\cAC
KM41Cl002-10
lOOns
25ns
lOOns
KM41Cl002-12
120ns
30ns
220ns
tAC
ran-
Static Column Mode Operation allows high speed
dom or Sequential access within a row. The KM41Cl002
offers high performance while relaxing many critical sys·
tem timing requirements for fast usable speed.
Static Column Mode operation
CS-before·RAS refresh capability
RAS·only and Hidden Refresh capability
TTL compatible inputs and output
Common 1/0 using 'Early Write'
Single + 5V:t 10% power supply
512 cycles/8ms refresh
JEDEC standard pinout
Available in Plastic DIP, SOJ and ZIP
CS-before-RAS refresh capability provides on-chip
auto refresh as an alternative to RAS-only Refresh. All
inputs and output are fully TTL compatible.
The KM41Cl002 is fabricated using Samsung's ad·
vanced CMOS process.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
• KM41C1002J
• KM41C1002P
DATA IN
BUFFER
1
D
Vss
17 Q
D [ 1 0 \,J
4
5
20
19
18
17
16
Ao [ 6
A1 [ 7
A2
As
Vee [ 10
15
14
13
12
11
W 2
liAS" 3
T.F.
N.C.
DATA
OUT
BUFFER
Q
i~
COLUMN DECODER
AO
A1
A2
A3
A4
AfJ
A6
A7
A8
A9
'"a:w
::>
.,
LL
LL
~
w
a:
c
c
A8
A7
A6
As
A4
a:
w
c
0
&lc
MEMORY ARRAY
-Vee
1,048,576 MEMORY CELLS
-Vss
~
a:
0(
Pin Name
Ao-Ag
RAS
Pin Function
Address Inputs
Row Address Strobe
CS
Chip Select Input
W
ReadlWrite Input
0
Data In
Q
T.F.
c8
0
• KM41C1002Z
Data Out
Test Function
Vee
Power (+5V)
Vss
Ground
N.C.
No Connection
N.L.
No Lead
H
SAMSUNG SEMICONDUCTOR
74
CMOS DRAM
KM41C1002
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
VIN, Your
Value
.. -1 to + 7.0
Vcc
-1 to + 7.0
V
Tsig
-55 to +150
·C
Power Dissipation
Po
600
mW
Short Circuit Output Current
los
50
mA
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Storage Temperature
Units
I
V
-
, Permanent deVice damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage
Parameter
referenced to Vss, TA=O to 70·C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
V
VIL
-1.0
-
6.5
Input Low Voltage
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter
Symbol
Min
Max
Units
60
50
mA
mA
2
mA
60
50
mA
mA
RAS-Only Refresh Current'
(CS = VIH, RAS Cycling @tRC= min)
KM41C1002-10
KM41C1002-12
Icc3
Static Column Mode Current'
(RAS = VIL, CS = VIL @tsc= min)
KM41C1002-10
KM41C1002-12
IcC4
-
40
30
mA
mA
Icc5
-
1
mA
1CC5
-
60
50
mA
mA
Operating Current'
(RAS and CS Cycling @tRc=min)
KM41C1002·10
KM41C1002-12
Standby Current
(RAS = CS = VIH)
Icc2
Standby Current
(RAS = CS = Vcc - 0.2V)
CS~Before-RAS Refresh Current'
(RAS and CS Cycling @tsc= min)
Icc1
KM41C1002-10
KM41C1002-12
Input Leakage Current
(Any input OSVINS6.5V,
ali other pins not under test = 0 volts)
IlL
-10
10
p.A
Output Leakage Current
(Data out is disabled, OSVourS5.5V
10L
-10
10
p.A
Output High Voltage Level
(loH= -5mA)
VOH
2.4
-
V
Output Low Voltage Level
(IOL = 4.2mA)
VOL
-
0.4
V
'NOTE: Icc," 1CC3, 1CC4, and Icee are dependent on output loading and cycle rates. Specified values are obtained with
the output open. Icc is specified as an average current.
ciS
SAMSUNG SEMICONDUCTOR
75
KM41C1002
CMOS DRAM
CAPACITANCE
(TA=25·C)
Parameter
Symbol
Input Capacitance (D)
Input Capacitance (Ao·Ag)
CIN '
CIN2
Input Capacitance (RAS, CS, W)
CIN3
Output Capacitance (0)
COUT
AC CHARACTERISTICS
Min
Max
Unit
5
pF
-
6
pF
7
pF
7
pF
(0·CsTAs70·C, Vcc =5.0V:t10%. See notes 1.2)
STANDARD OPERATION
Parameter
Symbol
KM41Cl002·10
KM41Cl002·12
Min
Min
Max
Max
Units
ns
Random Read or Write Cycle Time
tRC
190
220
Read·modify·write Cycle Time
tRWC
220
255
ns
Static Column Mode Cycle Time
tsc
55
65
ns
Static Column Mode Read·write Cycle Time
tSRWC
100
ns
120
100
Notes
120
ns
3,4,10
Access Time from RAS
tRAC
Access Time from CS
tCAC
25
30
ns
3, 4, 5
Access Time from Column Address
tAA
50
60
ns
3,10
Access Time from Last Write
tALW
95
115
ns
3, 11
CS to Output in LOw·Z
tCL2
5
ns
3
tOFF
0
ns
6
Output Buffer Turn·off Delay Time
Output Data Hold Time from Column Address
Output Data Enable Time from
W
tAOH
5
30
5
0
ns
5
85
70
tow
35
ns
ns
Output Data Hold Time from W
tWOH
0
Transition Time (rise and fall)
tr
3
RAS Precharge Time
tRP
80
RAS Pulse Width
tRAS
100
10,000
120
10,000
ns
tAASC
100
100,000
120
100,000
ns
RAS
Pulse Width (static column mode)
0
50
3
50
90
ns
2
ns
CS to RAS Hold Time
tRSH
25
30
RAS to CS Hold Time
tCSH
100
120
ns
CS Pulse Width
tcs
25
30
ns
RAS toGS Delay Time
tACD
25
75
25
90
ns
4
RAS to Column Address Delay Time
tRAD
20
50
20
60
ns
10
CS to RAS Precharge Time
tCAP
10
10
ns
CS Precharge Time (static column mode)
tcp
10
15
ns
Row Address Set·up Time
tASA
0
0
ns
Row Address Hold Time
tRAH
15
15
ns
Column Address Set·up Time
tASC
0
0
ns
Column Address Hold Time
tCAH
20
25
ns
Write Address Hold Time Referenced to RAS
tAWA
95
115
ns
c8
SAMSUNG SEMICONDUCTOR
ns
76
CMOS DRAM
KM41C1002
STANDARD OPERATION
(Continued)
KM41C1002·10
Parameter
Symbol
Min
Max
KM41C1002·12
Min
Max
Units
Notes
Column Address Hold Time Referenced to RAS
tAA
115
140
ns
Column Address to RAS Lead Time
tAAL
50
60
ns
Column Address Hold Time Referenced to RAS Rise
tAH
10
15
ns
Write Command to CS Lead Time
tewL
25
30
Last Write to Column Address Delay Time
tLWAo
25
Last Write to Column Address Hold Time
tAHLW
95
115
ns
Read Command Set·up Time Referenced to RAS
tAcs
0
0
ns
Read Command Hold Time Referenced to CS
tACH
0
0
ns
8
Read Command Hold Time Referenced to RAS
tAAH
0
0
ns
8
Write Command Hold Time
tWCH
20
25
ns
Write Command Hold Time Referenced to RAS
tWCA
95
115
ns
Write Command Pulse Width
twp
20
25
ns
45
30
ns
55
ns
Write Command Inactive Time
tWI
10
15
ns
Write Command to RAS Lead Time
tAWL
25
30
ns
Data·in Set·up Time
tos
0
0
ns
9
Data·in Hold Time
toH
20
25
ns
9
Data·in Hold Time Referenced to RAS
toHA
95
115
ns
Refresh Period (512 cycles)
tAEF
Write Command Set·up Time
twcs
CS to Write Enable Delay Time (read·write cycle)
tewo
25
RAS to Write Enable Delay Time (read·write cycle)
tAWo
100
tAWo
50
CS Setup Time (CS·before·RAS refresh)
tCSA
CS Hold Time (CS·before·RAS refresh)
8
8
--
ms
ns
7
30
ns
7
120
ns
7
60
ns
7
10
10
ns
tCHA
30
30
ns
tAPC
10
10
ns
CS Precharge Time (refresh counter test)
tCPT
50
60
ns
CS Precharge Time
IcPN
15
20
ns
Column Address to
W Delay Time
RAS Precharge to CS Hold Time
0
0
--
NOTES
1. An initial pause of 200"s is required after power·up
followed by any 8 RAS cycles before proper device
operation is achieved.
2. V,H(min) and V,L(max) are reference levels for meas·
uring timing of input signals. Transition times are
measured between V,H(min) and V,dmax) and are
assumed to be 5ns for all inputs.
=8
SAMSUNG SEMICONDUCTOR
3. Measured with a load equivalent to 2 TTL loads and
100pF.
4. Operation within the tACo(max) limit insures that
tAAdmax) can be met. tRCo(max) is specified as a
reference point only. If tAco is greater than the
specified tACo(max) limit, then access time is con·
trolled exclusively by tCAC'
77
I
CMOS DRAM
KM41C1002
NOTES
(Continued)
10. Operation within the tAAo(max) limit insures that
tAAc(max) can be met. tRAO(max) is specified as a
reference point only. If tAAO is greater than the
specified tAAo(max) limit, then access time is controlled by t M .
11. Operation within the tLwAO(max) limit insures that
tALw(max) can be met. tLwAO(max) is specified as a
reference point only. If tLWAO is greater than the
specified tLwAO(max) limit, then access time is controlled by tAA.
12. Normal operation requires the "T.F." pin to be connected to Vss or TIL logic low level or left unconnected on the printed wiring board.
13. When the "T.F." pin is connected to a defined positive voltage, the internal test function may be activated. Contact Sam sung Semiconductor for specific
operational details of the "test function".
5. Assumes that tACOtwcs(min)
the cycle is an early write cycle and the data output will remain high impedance for the duration of
the cycle. If tcwo
0
0
MEMORY ARRAY
w
262.144x4
:;:
MEMORY CELLS
()
'"'"a:w
0
<
7
8
9
10
0
15R A8
14 ~ A7
13Q A6
12p A5
11"P A4
a:
w
CD
0
0
6
0
a:
-vee
-vss
Pin Name
A(rAs
Pin Function
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
W
ReadlWrlte Input
OE
Data Output Enable
OQ,-OQ4
Data In/Data Out
Vee
Power (+5V)
Vss
Ground
N.C.
No Connection
N.L.
No Lead
89
•
CMOS DRAM
KM44C256
ABSOLUTE MAXIMUM RATINGS·
Symbol
Value
Units
V,N, VOUT
-1 to + 7.0
V
Vcc
-1 to + 7.0
V
°C
Power Dissipation
T" g
PD
-55 to +150
600
mW
Short Circuit Output Current
los
50
mA
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Storage Temperature
- Permanent device damage may occur If "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage
Parameter
reference to Vss, TA=O to WC)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
V,H
2.4
-
6.5
V
Input Low Voltage
V'L
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter
Operating Current(RAS and CAS Cycling @tRc=min)
KM44C256-10
KM44C256-12
Standby Current
(RAS = CAS = V,H)
Symbol
Min
Max
Units
Iccl
-
70
60
mA
mA
Icc2
-
2
mA
-
70
60
mA
mA
RAS-Only Refresh Current(CAS = V,H, RAS CYCling @tRC = min)
KM44C256-10
KM44C256-12
Icc3
-
Fast Page Mode Current(RAS = V,L, CAS CYCling @tpc= min)
KM44C256-10
KM44C256-12
IcC4
-
-
50
40
mA
mA
Iccs
-
1
mA
Ices
-
70
60
mA
mA
Standby Current
(RAS = CAS = Vcc - 0.2V)
CAS-Before-RAS Refresh Current(RAS and CAS Cycling @tRC= min)
KM44C256-10
KM44C256-12
-
Input Leakage Current
(Any input OSV'NS6.5V,
all other pins not under test = 0 volts)
I'L
-10
10
p.A
Output Leakage Current
(Data out is disabled, OSVouTs5.5V
10L
-10
10
p.A
Output High Voltage Level
(loH= -5mA)
VOH
2.4
-
V
Output Low Voltage Level
(ioL=4.2mA)
VOL
-
0.4
V
-NOTE: ICC1, 1CC3, IcC4, and Ices are dependent on output loading and cycle rates. Specified values are obtained with
the output open. Icc is specified as an average current.
c8
SAMSUNG SEMICONDUCTOR
90
KM44C256
CMOS DRAM
CAPACITANCE
(TA=25°C)
Parameter
Symbol
Min
C ,N '
C 'N2
C,N/OUT
-
Input Capacitance (Ao-A.)
Input Capacitance (RAS,
cAs,
W, OE)
Output Capacitance (00,-00 4)
AC CHARACTERISTICS
Max
Unit
-
6
pF
-
7
pF
7
pF
I
(0°C~TA~70°C, Vcc=5_0V±10%_ See notes 1, 2)
Parameter
Symbol
KM44C256-10
KM44C256-12
Min
Min
Max
Max
Units
Random Read or Write Cycle Time
tRc
190
220
ns
Read-modify-write Cycle Time
tRWC
255
295
ns
Fast Page Mode Cycle Time
tpc
60
70
ns
tPRwc
110
130
ns
Fast Page Mode Read-modify-write Cycle Time
Notes
Access Time from RAS
tRAC
100
120
ns
3, 4, 10
Access Time from CAS
tCAC
25
30
ns
3, 4, 5
Access Time from Column Address
tAA
50
60
ns
3, 10
Access Time from CAS Precharge
tCPA
55
65
ns
3
CAS to Output in Low-Z
tCLZ
5
Output Buffer Turn-off Delay
tOFF
0
30
0
Transition Time (rise and fall)
tr
3
50
3
RAS Precharge Time
tRP
80
RAS Pulse Width
tRAS
100
10,000
120
10,000
ns
RAS Pulse Width (fast page mode)
tRASP
100
100,000
120
100,000
ns
RAS Hold Time
tRSH
25
30
ns
CAS Hold Time
tcSH
100
120
ns
CAS Pulse Width
tCAS
25
10,000
30
10,000
ns
RAS to CAS Delay Time
tRCO
25
75
25
90
ns
4
50
20
60
ns
10
--
ns
3
35
ns
6
50
ns
2
5
ns
90
RAS to Column Address Delay Time
tRAD
20
CAS to RAS Precharge Time
tCRP
10
10
CAS Precharge time
tCPN
15
20
CAS Precharge Time (fast page mode)
tcp
10
15
Row Address Set-up Time
tASR
0
0
ns
Row Address Hold Time
tRAH
15
15
ns
Column Address Set-up Time
tASC
0
0
ns
Column Address Hold Time
tCAH
20
25
ns
Column Address Hold Time Reference to RAS
tAR
95
115
ns
Column Address to RAS Lead Time
tRAl
50
60
ns
c8
SAMSUNG SEMICONDUCTOR
ns
ns
91
CMOS DRAM
KM44C256
AC CHARACTERISTICS
(Continued)
Symbol
Parameter
KM44C256·10
KM44C256·12
Min
Min
Max
Max
Units
Notes
Read Command Set·up Time
tRCS
0
0
ns
Read Command Hold Time
tRCH
0
0
ns
8
Read Command Hold Time Reference to RAS
IRRH
0
0
ns
8
Write Command Hold Time
tWCH
20
25
ns
Write Command Hold Time Referenced 10 RAS
IwcR
95
115
ns
twp
20
25
ns
Write Command Pulse Width
Write Command 10 RAS Lead Time
IRWL
25
30
ns
Write Command to CAS Lead Time
ICWL
25
30
ns
Dala Set-up Time
tos
0
0
ns
9
Dala Hold Time
IOH
20
25
ns
9
Dala Hold Time Referenced 10 RAS
IOHR
95
115
ns
Refresh Period
IREF
8
8
ms
0
ns
7
60
70
ns
7
135
160
ns
7
85
100
ns
7
IcsR
10
10
ns
CAS Hold Time (CAS before RAS cycle)
ICHR
30
30
ns
RAS to CAS Precharge Time
IRPc
10
10
ns
CAS Precharge Time (CAS before RAS
counter test cycle)
tCPT
50
60
ns
20
Write Command Sel-up Time
Iwcs
CAS 10 W Delay Time
Icwo
RAS to W Delay Time
tAWO
Column Address to W Delay Time
tAWO
CAS Set-up Time (CAS before RAS cycle)
0
RAS Hold Time Reference to OE
tROH
OE Access Time
IOEA
OE 10 Dala Delay
tOEO
25
tOEZ
0
tOEH
25
Output Buffer Turn Off Delay Time from
OE
OE Command Hold Time
20
25
ns
30
30
25
0
30
ns
ns
30
ns
ns
NOTES
1. An initial pause of 200,..s is required after power-up
followed by any 8 RAS cycles before proper device
operation is achieved.
2. V1H(min) and V1L(max) are reference levels for measuring timing of input signals. Transition limes are
measured between V1H(min) and V1L(max) and are
assumed to be 5ns for all inputs.
c8
SAMSUNG SEMICONDUCTOR
3. Measured with a load equivalent to 2 TIL loads and
100pF.
4. Operation within the tRCO(max) limit insures that
tRAc(max) can be met. tRCO(max) is specified as a
reference pOint only. If tRCO is greater than the
specified IRco(max) limit, Ihen access time is controlled exclusively by tCAC'
92
KM44C256
NOTES
CMOS DRAM
(Continued)
5. Assumes that tRCD~tRCD(max).
6. This parameter defines the time at which the out·
put achieves the open circuit condition and is not
referenced to VOH or VOL.
7. t wcs , tRWD, tCWD and tAWD are non restrictive operat·
ing parameters. They are included in the data sheet
as electrical characteristics only. If twcs>twcs(min)
the cycle is an early write cycle and the data out·
put will remain high impedance for the duration of
the cycle. If tCWD~ tcwo(min), tRWo~tRWo(min) and
tAwo~tAwoCmin), then the cycle is a read·write cycle
and the data output will contain the data read from
the selected address. If neither of the above conditions are satisfied, the condition of the data out is
indeterminate.
8. Either tRCH or tRRH must be satisfied for a read
cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading
edge in read-write cycles.
10. Operation within the tRAoCmax) limit insures that
tRCO(max) can be met. tRAO(max) is specified as a
reference point only. If tR...D is greater than the
specified tR... oCmax) limit, then access time is controlled by tA....
TIMING DIAGRAMS
READ CYCLE
tRC
RAS
tR ...S
VIHVll-
tRP
tAR
tCSH
tRCO
tCPN-
tRSH
CAS
,A
tRCH
tRRH
w
tOFF
tCAC'
f----tRAC
VOH- - - - - - - O P E N
VOl-
+----+---1
--+---..t
tOEZ
~...I...----...,/
VALID DATA-OUT
tCLZ
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
93
I
CMOS DRAM
KM44C256
TIMING DIAGRAMS
(Continued)
WRITE CYCLE (EARLY WRITE)
I
IRC
IRAS
VIH-
RAS
IL-JIR=:J
11
IAR
VIL-
~
VIH-
ICSH
f------
f -
CAS
VIL-
~ ~
I"SR
A
ICAS-
~
rxrlCX
COLUMN
ADDRESS
ROW
VIL- 'YX [lClClClCX\iI ADDRESS,
-IR:o:.
V
I
ICPN
IRAL
~
IASC
I--VIH-
,
I
IRSH
IRCO
\
IIIlX
ex
:X
.. :lllll't'fuyvy [W
r~;v
XXV
tCWL
VIH-
W
VIL-
r lWCS
!.lxN/x
:XX [lClC
[lC
(YV
(Y
"-
I-lwCHIwp f----
IfllltXllP
ilC
:~
IWCR I-----IRWL
VIHVIL-
'lxxNr-ll AX \
xx :0- N 'xlI X:CY (X iXWlllb. ~lXNNl~xx~
XlC
los
VIH-
00,·00.
-
tOHR
I---i-IoH-
VALID DATA·IN
VIL-
OPEN
WRITE CYCLE (OE CONTROLLED WRITE)
f - - - - - - - - - - - IRC-----------~
f - - - - - - - - IRAS-------.1
VIH- - - - - - i J - - - I A R - - - - - - l
RAS
VILe------.ICSH-+----~
- - - I - - - - l - IRSH - - - + - - - <
~--- ICPN----<
,,---1" ICAS---if
VIH- 'Ir'ft'......:ll'nJ.:--.....-.i.,..".j"..J...-...i.---s.ntl~~~~~~~'"'~""~'r7'r:~II"lr'"
A
VIL- o.ol:ktl.t::Ji).If"'':'::::::':=~·
ICWL
00,·00.
IRWL
VIH-
"Xl',,",,"~~~7nI:~,",~,,"~~rm-1
VIL -
.A/.1.O.£1.O.£~::..£lo~AA/:J:j~.u.I.O.£~~Cl.q.~
VIH-
7\1iJf:l'J'J~~~1U'\1U'I~n~---1+-""*It7t1U'\~~:mI':7\1iJf:l~~1U'I7U'I7U'I:7'O'I'Jf:IiJf:lm71:
VIL -
c.c.CJ.I:,lOl:lAC~liao(~~o/y
_____,;(&AAt:JI::,,/:J:j.u.'./:ii.~~~Mt:JI::,,/:J:jtAJ.~~
VIHVIL- _ _ _- J
IZZI
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
94
CMOS DRAM
KM44C256
TIMING DIAGRAMS
(Continued)
•
READ·MODIFY·WRITE
1---------------tRwc-- ---------------,---__1
1--------------- tRAS-------------j
V'H- ----:(1
tAA----
V'L- tCSH--
------------1
---+--1------ t A S H - - - - - - - + - i
~~~--------_i~,
tcAs-------~,~--;l~--~\
tCAH
A
V'H- ~~J~r.t~~~~~~C~O~L~u~M~N~-i~~~UO~~~~~~O\.~~~~~UO~~J--------V,L _
ADDRESS
. tAWO- - - - -
r------
-----
tcwD'-----i
~---+---~-'AWD--------__I
w
V'H-
--------t-----+------t---;------------------iJ
V'L-
OE
V'H- ~~~.,.;)~IJV~~~~"*'V'I
V,L -
VIIDH -
V,/DL _
lQ,j:l.l:l.I:i.A.a..~Q,Q.tJ.J,~~Aa~~(Jf'"'""_+--J
-----------------------+----V\~===.:..I["
FAST PAGE MODE READ CYCLE
RAS
CAS
A
V'H- ~~~~otr_~_t------1_tt~~-----fl'~tr~~~----_1_r~~~~~
V,L -
~iC./i.a..~M
OE
~
c8
SAMSUNG SEMICONDUCTOR
DON'T CARE
95
CMOS DRAM
KM44C256
TIMING DIAGRAMS
(Continued)
FAST PAGE MODE WRITE CYCLE
RAS
VIH-
----::Nc---!'-__~---!_------------------~
VIL-
A
VIH-
TXlU-:±~.",,~"":-:~~-I.A:7'II'I'mc",.J~~~~u,nril7l!1\r~~;:;-iJt~~~m
VIL-
VIH-
"lnIt7n'~rmrmPm.
VIL-
VIH-
---t---""t'~1"O!:~:r---it'V:~7'\7Irr--....;.tr-tJ\;'O"tI'il"\~7V''if':1~~''i1\!
VIL-
VIH-~~~7V~F--V~~~~~7VvlJ-~~-~J~~~~I"~~~~~~~~~~~~
VIL -
..cJ.~~~n;""''::':;:';';';;':'''''.f"\AO.D/J~~;';';;';';';;'~"'-'l~OO'l-~~::'::''~ \j~CoQ;CoQ;CoQ;Q,Q,QQC.
FAST PAGE MODE READ·MODIFY·WRITE
~-------------------------IRASP-------------------------~
VIHVILICSH
IpRWC
I-------IRSH CRP
VIHVILtASR
A
VIHVIL-
VIHVILtwp
VIHVIL-
IOH
VIIOH VUOL _
----+'M'
~DON'TCAFIE
c8
SAMSUNG SEMICONDUCTOR
96
KM44C256
CMOS DRAM
TIMING DIAGRAMS
(Continued)
•
RAS·ONLY REFRESH CYCLE
Note:
W, OE = Don't care
f---------------jtAC---.tAP-·
VIH-----~I
I\J------~tAAS------1J
RAS
V'H-
----:1:---++--------------...;...-+-..,------
A
CAS·BEFORE·RAS REFRESH CYCLE
Note: W, OE, A = Don't care
tAC
_tAP_
r----tAP~
V'HRAS
V'L-
tAAS
..J
V'L-
J
f-tAPCtCPN
tCSA
L
tCHR
~
V'HCAS
Il
---1
1
-
tAPC
tCPN
\
~
V'OHOPEN
DO,-DO.
V'OL-
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
97
CMOS DRAM
KM44C256
TIMING DIAGRAMS
(Continued)
HIDDEN REFRESH CYCLE (READ)
f--------tRc -------l--------tRC---------"
A
V1H-
~A,lI;'J'V,"~~t'I-_+-----""-~':'mim~~~"""mo:7\1~~"""mo:~"Jf:7m~!:"7\"~
Vll- ~CA~c..r:.J:./
ICLZ
1----tRAC
--+--1
VOH- ______~__________~
tOEZ
~------------~--~
VALID DATA·OUT
__
VOl~V,~--------------------- ~
HIDDEN REFRESH CYCLE (WRITE)
------~-------IRC-------~
A
V1H-
w
c8
V1H-
~'7\}~~'V'\:"""c*Af.:m~7\J~m\A''''''~~_m~m\A'~~~~~~~~\A'~~
Vll-
..lLw.l..lL~l..lLw.~~~~t::;I.~~~.c.t.~~~.c.t.~.t::.J.~.i::.I.~.t:::./.~~CI.Ll~~~~oC:iD.
SAMSUNG SEMICONDUCTOR
98
KM44C256
CMOS DRAM
TIMING DIAGRAMS
(Continued)
CAS·BEFORE·RAS REFRESH COUNTER TEST CYCLE
~~~-----
I
I A A S - - - - -- ---------
RAS
ICHA
tCPT
- - - IASH------j
r"'±----
CAS
A
READ CYCLE
w
V,H -
7'iJ'il\J~~'!'ili.7'ili.7\Ji7'\}lJ'i}ViJ\Ji}\Ji}0\'!'ili.7OI7v'1~
V,L -
[j£,loa.I~~oe:.OIJtu:..At..t:;C.~i.Ql~¥-~~~tl:J.t.q:.-+_----q::q:.lOo1~~~DC.t::L.~
VOHVOL- - - - - - - -
WRITE CYCLE
w
OE
V'H-
------------~-~~---------~-~-----
VIL-
-------------t--:--r,------;------,--,-----IOH
VIHVIL _
- - - - - OPEN ------KI~-,.VA,..L-ID-D-A-T-A.-IN-_'I
ICWL
READ·MODIFY·WRITE
W
t
IAWL~
f---++-- I A W O I - - - -
VIHVIL-
VIH-
OE
VILIOH
VIIOHV I I O L - - - - - - - - - - - - - - -......~L"
~~~~IN ~-------~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
99
KM44C256
CMOS DRAM
KM44C256 OPERAliON
Device Operation
Write
The KM44C256 contains 1,048,576 memory locations
organized as 262,144 four-bit words. Eighteen address
bits are required to address a particular 4-bit word in
the memory array. Since the KM44C256 has only 9 address input pins, time multiplexed addressing is used
to input 9 row and 9 column addresses. The multiplexing is controlled by the timing relationship between the
row address strobe (RAS), the column address strobe
(CAS) and the valid address inputs.
Operation of the KM44C256 begins by strobing in a
valid row address with RAS while CAS remains high.
Then the address on the 9 address input pins is changed
from a row address to a column address and is strobed
in by CAS. This is the beginning of any KM44C256 cycle in which a memory location is accessed. The specific type of cycle is determined by the state of the write
enable pin and various timing relationships. The cycle
is terminated when both RAS and CAS have returned
to the high state. Another cycle can be initiated after
RAS remains high long enough to satisfy the RAS
precharge time (tRP) requirement.
The KM44C256 can perform early write and readmodify-write cycles. The differece between these cycles
is in the state of data-out and is determined by the timing relationship between W, OE and CAS. In any type of
write cycle Data-in must be valid at or before the failing edge of W or CAS, whichever is later.
RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tCAS(min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is initiated by bringing RAS low, it must not be aborted prior
to satisfying the minimum RAS and CAS pulse widths.
In addition, a new cycle must not begin until the minimum RAS precharge time, tRP, has been satisfied. Once
a cycle begins, internal clocks and other circuits within
the KM44C256 begin a complex sequence of events. If
the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.
Read
A read cycle is achieved by maintaining the write enable input(W) high during a RAS/CAS cycle. The access
time is normally specified with respect to the falling
edge of RAS. But the access time also depends on the
falling edge of CAS and on the valid column address
transition.
If CAS goes low before tRCD(max) and if the column
address is valid before tRAD(max) then the access time
to valid data is specified by tRAC(min). However, if CAS
goes low after tRCD(max) or if the column address becomes valid after tRAD(max), access is specified by
tCAC or tAA. In order to achieve the minimum access
time, tRAC(min), it is necessary to meet both tRCD(max)
and tRAD(max).
The KM44C256 has common data I/O pins. For this
reason an output enable control input (OE) has been
provided so the output buffer can be precisely controlled. For data to appear at the outputs, OE must be
low for the period of time defined by tOEA and tOEZ.
c8
SAMSUNG SEMICONDUCTOR
Early Write: An early write cycle is performed by bringing W low before CAS. The 4-bit wide data at the data
input pins is written into the addressed memory cells.
Throughout the early write cycle the outputs remain in
the H i-Z state. In the early write cycle the output buffers
remain in he Hi-Z state regardless of the state of the
OE input.
Read-Modify-Write: In this cycle, valid data from the addressed cells appears at the outputs before and during
the time that data is being written into the same cell
locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet read-modify-write
timing requirements. This output enable input (OE) must
be low during the time defined by tOEA and tOEl for
data to appear at the outputs. If tCWD and tRWD are
not met the output may contain invalid data. Conforming to the OE timing requirements prevents bus contention on the KM44C256's DO pins.
Data Output
The KM44C256 has a tri-state output buffers which
are controlled by CAS and 010. When either CAS or OE is
high (VIH) the output are in the high impedance (Hi-Z)
state. In any cycle in which valid data appears at the
output the output goes into the low impedance state
in a time specified by tCLZ after the falling edge of CAS.
Invalid data may be present at the output during the time
after tCLZ and before the valid data appears at the output. The timing parameters tCAC, tRAC and tAA specify when the valid data will be present at the output. This
is true even if a new RAS cycle occurs (as in hidden
refresh). Each of the KM44C256 operating cycles is listed below after the corresponding output state produced
by the cycle.
Valid Output Data: Read, Read-Modify-Write, Hidden
Refresh, Fast Page Mode Read, Fast Page Mode ReadModify-Write.
Hi-Z Output State: Early Write, RAS-only Refresh, Fast
Page Mode Write, CAS-only cycle.
Indeterminate Output State: Delayed Write (tCWD or
tRWD are not met)
100
CMOS DRAM
KM44C256
DEVICE OPERATION
(Continued)
Refresh
The data in the KM44C256 is stored on a tiny capacitor within each memory cell. Due to leakage the data
may leak off after a period of time. To maintain data integrity it is necessary to refresh each of the rows every
8 ms. Either a burst refresh or distributed refresh may
be used. There are several ways to accomplish this.
selected row. These cycles may be mixed in any order.
A fast page mode cycle begins with a normal cycle.
Then, while RAS is kept low to maintain the row address,
CAS is cycled to strobe in additional column addresses. This eliminates the time required to set up and
strobe sequential row addresses for the same page.
RAS-Only Refresh: This is the most common method
for performing refresh. It is performed by strobing in a
row address with RAS while CAS remains high. This
Power·up
cycle must be repeated for each of the 512 row addresses, (AO-A8).
CAS-before-RAS Refresh: The KM44C256 has CASbefore-RAS on-chip refresh capability that eliminates the
need for external refresh addresses. If CAS is held low
for the specified set up time (tCSR) before RAS goes
low, the on-chip refresh circuitry is enabled. An internal refresh operation automatically occurs. The refresh
address is supplied by the on-chip refresh address counter which is then internally incremented in preparation
for the next CAS-before-RAS refresh cycle.
Hidden Refresh: A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the CAS active time and cycling RAS.
The KM44C256 hidden refresh cycle is actually a CASbefore-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip
refresh address counter.
Other Refresh Methods: It is also possible to refresh
the KM44C256 by using read, write or read-modify-write
cycles. Whenever a row is accessed, all the cells in that
row are automatically refreshed. There are certain applications in which it might be advantageous to perform
refresh in this manner but in general RAS-only or CASbefore-RAS refresh is the preferred method.
CAS·before·RAS Refresh Counter Test Cycle
A special timing sequence using the CAS-before-RAS
refresh counter test cycle provides a convenient method
of verifying the functionality of the CAS-before-RAS
refresh activated circuitry. The cycle begins as a CASbefore-RAS refresh operation. Then, if CAS is brought
high and then low again while RAS is held low, the read
and write operations are enabled. In this mode, the row
address bits AO through A8 are supplied by the on-chip
refresh counter.
Fast Page Mode
Fast page mode provides high speed read, write or
read-modify-write access to all memory cells within a
c8
SAMSUNG SEMICONDUCTOR
If RAS = Vss during power-up, the KM44C256 could
begin an active cycle. This condition results in higher
than necessary current demands from the power supply during power-up. It is recommended that RAS and
CAS track with Vee during power-up or be held at a
valid VIH in order to minimize the power-up current.
An initial pause of 200 !,sec is required after powerup followed by 8 initialization cycles before proper
device operation is assured: Eight initialization cycles
are also required after any 8 msec period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
Termination
The lines from the TTL driver circuits to the
KM44C256 inputs act like unterminated transmission
lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them as
short as possible. Although either series or parallel termination may be used, series termination is generally
recommended since it is simple and draws no additional
power. It consists of a resistor in series with the input
line placed close to the KM44C256 input pin. The optimum value depends on the board layout. It must be determined experimentally and is usually in the range of
20 to 40 ohms.
Board Layout
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended methods
are gridded power and ground lines or separate power
and ground planes. The power and ground lines act like
transmission lines to the high frequency transients
generated by DRAMS. The impedance is minimized if all
the power supply traces to all the DRAMS run both horizontally and vertically and are connected at each intersection or better yet if power and ground planes are used.
Address and control lines should be as short as possible to avoid skew. In boards with many DRAMS these
lines should fan out from a central point like a fork or
comb rather than being connected in a serpentine pattern. Also the control logic should be centrally located
on large memory boards to facilitate the shortest possible address and control lines to all the DRAMS.
101
•
KM44C256
CMOS DRAM
DEVICE OPERATION
(Continued)
Decoupling
by the KM44C256 and they supply much of the current
used by the KM44C256 during cycling.
In addition, a large tantalum capacitor with a value
of 47/,F to 100/,F should be used for bulk decoupling
to recharge the O.3/,F capacitors between cycles, thereby reducing power line droop. The bulk decoupling capacitor should be placed near the point where the power
traces meet the power grid or power plane. Even better
results may be achieved by distributing more than one
tantalum capacitor around the memory array.
The importance of proper decoupling can not be over
emphasized. Excessive transient noise or voltage droop
on the Vee line can cause loss of data integrity (soft er·
rors). It is recommended that the total combined vol·
tage changes over time in the VCC to VSS voltage
(measured at the device pins) should not exceed 500mV.
A high frequency O.3/,F ceramic decoupling capaci·
tor should be connected between the Vee and ground
pins of each KM44C256 using the shortest possible
traces. These capacitors act as a low impedance shunt
for the high frequency switching transients generated
PACKAGE DIMENSIONS
2O·LEAD PLASTIC DUAL IN·L1NE PACKAGE
Units: Inches (millimeters)
~ : : : : : : :311
~
0.962(24.43)
-------------------
~
t:.a.
0>0>-
'"o
~
0.972 (241.69)
-=--1
-T-
0.008 (0.20)
0.020 (0.51)
0.012 (0.30)
MIN
0.197 (5.00)
MAX
0.135 (3.43)
0.145 (3.68)
0.100(2.54)
TVP
c8
0.047 (1.19)
0.059 (1.49)
SAMSUNG SEMICONDUCTOR
~
,
0.118(3.00)
MIN
0.032 (0.81)
0.040 (1.02)
102
KM44C256
CMOS DRAM
PACKAGE DIMENSIONS (Continued)
20·LEAD PLASTIC SMALL OUT·L1NE J·LEAD
units: inches (millimeters)
o~;~
r-
m
&l g
ci ci
Q ci
o
~rr~~-r~------~~~~~~~
~iii
e.e.
...io'j ...~
..... ~~
0.670 (17.02)
0.Q93 (2.36)
0.680 (17.27)
0.103 (2.62)
0.120 (3.04)
0.140 (3.56)
20·PIN PLASTIC ZIGZAG·IN·L1NE PACKAGE
0.113 (2.87)
0.123 (3.12)
1.025 (26.04)
1.035 (26.29)
7
$'-:::
6
lNDEX
I
0
'"5!2.~
"'
"''" '"'"
"''''
00
,
I
0.018 (0.46)
0.022 (0.56)
c8
~-
0.008 (0.20)
0.012 (0.30)
0.050 (1.27)
0.100(2.54)
TYP
TYP
SAMSUNG SEMICONDUCTOR
103
PRELIMINARY SPECIFICATION
KM44C258
CMOS DRAM
256K x 4 Bit CMOS Dynamic RAM with Static Column Mode
FEATURES
GENERAL DESCRIPTION
• Performance range:
The Samsung KM44C258 is a CMOS high speed
262,144 x 4 bit Dynamic Random Access Memory. Its
design is optimized for high performance applications
such as mainframes and mini computers, graphics and
high performance microprocessor systems.
KM44C258-10
KM44C258-12
•
•
•
•
•
•
•
•
•
tRAC
tCAC
100ns
25ns
190ns
120ns
35ns
220ns
tRC
The KM44C258 features Static Column Mode which
allows high speed random access of memory cells within the same row. CAS-before-RAS refresh capability
provides on-chip auto refresh as an alternative to RASonly Refresh. All inputs and outputs are fully TTL compatible.
Static Column Mode operation
CS·before·RAS refresh
RAS·only and Hidden refresh
TTL compatible Inputs and output
Early Write or Output Enable Controlled Write
Single + 5V:t 10% power supply
512 cycles/8ms refresh
JEDEC standard pinout
Available in Plastic 20·pin DIP, SOJ and ZIP
The KM44C258 is fabricated using Samsung's advanced CMOS process.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
• KM44C258P
RAS'--.J----'
cs
W
• KM44C258J
I - - - - - - - - - - r - - l D~~A
-n-;:==-L-_-,
BUFF
D01
D02
D01
to
D04
SENSE AMPS & 1/0 GATING
OE
CIl
II:
W
U.
0
II:
W
u.
:>
III
0
0
«
A8
.c8
RAS
N,C
5
~~
vss
D04
18 D03
17
16 5E
cs
4
AO 6
A1 7
A2 8
A3 9
Vee 10
COLUMN DECODER
AO
Iii
1
2
3
• KM44C258Z
0
15
14
13
12
11
A8
A7
A6
A5
A4
0
0
w
0
:;;:
0
II:
MEMORY ARRAY
1,048,576 CELLS
-Vee
Pin Name
-vss
Ao-As
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
RAS
Row Address Strobe
CS
Column Address Strobe
DQ,-DQ.
Data InlData Out
W
ReadlWrite Input
OE
Data Output Enable
Vee
Power (+5V)
Vss
Ground
N.C.
No Connection
N.L.
No Lead
104
KMM48256/KMM48257
KMM58256/KMM58257
MEMORY MODULES
256K x 8 Bit DRAM Memory Modules SIP/SIMM
FEATURES
GENERAL DESCRIPTION
• 262,144x8·bit Organization
• Performance range:
tRAC
•
•
•
•
•
•
•
tCAC
The Samsung KMM48256, KMM48257, KMM58256
and KMM58257 are 256K x 8 dynamic RAM high density memory modules. Samsung's 256K x 8 memory
modules consists of eight KM41256/7 DRAMs in 18-pin
PLCC packages mounted on a 30 pin glass-epoxy
substrate. A 0.22,..F decoupling capacitor is mounted
under each DRAM.
tRC
KMM48256/7·12
120ns
60ns
230ns
KMM58256/7·12
120ns
60ns
230ns
KMM48256/7·15
150ns
75ns
260ns
KMM58256/7·15
150ns
75ns
260ns
Page Mode capability: KMM48256 and KMM58256
Nibble Mode capability: KMM48257 and KMM58257
CAS·before·RAS Refresh capability
RAS·only and Hidden Refresh capability
TTL compatible inputs and outputs
Single + 5V :!: 10% power supply
256 cycle/4ms refresh
FUNCTIONAL BLOCK DIAGRAM
The 256K x 8 DRAM modules are available in two
package styles. The KMM48256 and KMM48257 are
SIPs with leads suitable for through hole mounting or
for mounting in a socket. The KMM58256 and
KMM58257 are SIMMs with edge connections and are
intended for mounting into 30 pin edge connector
sockets.
PIN CONFIGURATION
Ao-A8 G----1r----------,
RAS G - - H - - - - - - ,
D
D
CA!'
W
DO~
D
006
D
003
Pin Name
Ao-AB
004
DOS
PART NUMBERS
Pin Function
Address Inputs
DQ
Data In/Out
W
ReadlWrite Input
RAS
Row Address Strobe
KMM48256·12
120ns
SIP
Page Mode
CAS
Column Address Strobe
KMM48256·15
150ns
SIP
Page Mode
Vee
Power (+5V)
KMM58256·12
120ns
SIMM
Page Mode
Vss
Ground
KMM58256·15
150ns
SIMM
Page Mode
N.C.
No Connection
KMM48257·12
120ns
SIP
Nibble Mode
KMM48257·15
150ns
SIP
Nibble Mode
KMM58257·12
120ns
SIMM
Nibble Mode
KMM58257·15
150ns
SIMM
Nibble Mode
c8
o
SAMSUNG SEMICONDUCTOR
D
D
D
D
o
105
I
KMM48256/KMM48257
KMM58256/KMM58257
MEMORY MODULES
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Rating
Units
Voltage on any pin relative to Vss
VIN, Your
-1 to + 7.0
V
Voltage on Vee supply relative to Vss
Vec
-1 to + 7.0
V
Storage Temperature
Tstg
-55 to + 150
·C
Power Dissipation
Po
8
W
Short Circuit Output Current
los
50
mA
'Note: Permanent device damage may occur of ABSOLUTE MAXIMUM RATINGS are exceeded. Functional opera·
tion should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Min
Symbol
(Voltages referenced to Vss, TA=O to 70·C)
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
,-
Vee + 1
V
Input Low Voltage
VIL
-
0.8
V
-1
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Symbol
Parameter
OPERATING CURRENT'
(RAS and CAS cycling; @tRC= min)
STANDBY CURRENT
(RAS=CAS=VIH after 8
RAS
KMM48256/7-12, KMM58256/7·12
KMM48256/7-15, KMM58256/7-15
leci
.lec2
cycles min)
RAS-ONLY REFRESH CURRENT'
(CAS = VIH, RAS cycling; @tRC= min)
KMM48256/7-12, KMM58256/7-12
PAGE MODE CURRENT'
(RAS = VIL, CAS cycling; @tpc = min)
KMM48256-12, KMM58256-12
KMM48256/7-15, KMM58256/7-15
IcC3
ICC4
KMM48256-15, KMM58256-15
NIBBLE MODE CURRENT*
(RAS = VIL, CAS cycling; @tNC= min)
KMM48257-12, KMM58257-12
CAS-BEFORE-RAS REFRESH CURRENT*
(RAS cycling; @tRC= min)
KMM48256/7-12, KMM58256/7·12
KMM48257-15, KMM58257-15
KMM48256/7-15, KMM58256/7-15
Icc5
Icc6
Min
Max
Units
-
600
mA
520
mA
36
mA
520
mA
480
mA
440
mA
360
mA
440
mA
360
mA
520
mA
480
mA
INPUT LEAKAGE CURRENT (Any input, 0:sVIN :s5.5V,
Vcc = 5.5V, Vss = OV, all other pins not under test = 0 volts.)
IlL
-80
80
/LA
OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV:sVour:s5.5V, Vee=5.5V, Vss=OV)
10L
-10
10
/LA
OUTPUT HIGH VOLTAGE LEVEL (lOH = - 5mA)
VOH
2.4
-
V
OUTPUT LOW VOLTAGE LEVEL (loL=4.2mA)
VOL
-
0.4
V
"NOTE: Icc," Icc3, ICC4, IcC5 and Ices are dependent on output loading and cycle rates. Specified values are obtained
with the output open. lee is specified as average current.
c8
SAMSUNG SEMICONDUCTOR
106
KMM48256/KMM48257
KMM58256/KMM58257
CAPACITANCE
MEMORY MODULES
(TA=25°C)
Parameter
Symbol
Input capacitance (Ao - Ag)
CA
Input capacitance (RAS)
CRAS
Input capacitance (CAS)
CCAS
Input capacitance (W)
Cw
Input capacitance (DQ, - DQB)
Coa
AC CHARACTERISTICS
Min
Max
Unit
-
56
pF
64
pF
64
pF
64
pF
17
pF
(0°CSTAS70°C, Vcc=5.0V±10%. See notes 1,2.)
STANDARD OPERATION
Parameter
Symbol
KMM4825617·12
KMM5825617·12
KMM4825617·15
KMM5825617·15
Min
Min
Max
230
Unit
Notes
Max
Random read or write cycle time
tRC
Access time from RAS
tRAC
120
150
ns
3,4
Access time from CAS
tCAC
60
75
ns
3,5
Output buffer turn-off delay time
tOFF
0
30
0
40
ns
6
Transition time (rise and fall)
tr
3
50
3
50
ns
RAS precharge time
10,000
150
tRp
100
RAS pulse width
tRAS
120
260
ns
100
ns
10,000
ns
RAS hold time
tRSH
60
75
CAS precharge time (all cycles except page mode)
tCPN
50
60
CAS pulse width
tCAS
60
CAS hold time
tCSH
120
RAS to CAS delay time
tRCO
25
CAS to RAS precharge time
tCRP
10
10
ns
Row address set·up time
tAsR
0
0
ns
10,000
75
ns
ns
10,000
150
60
25
ns
ns
75
ns
Row address hold time
tRAH
15
15
ns
Column address set·up time
tASC
0
0
ns
Column address hold time
tCAH
20
25
ns
Column address hold time referenced to RAS
tAR
80
100
ns
Read command set·up time
tRCS
0
0
ns
tRCH
0
0
ns
Read command hold time referenced to CAS
Read command hold time referenced to RAS
tRRH
20
20
ns
Write command set·up time
twcs
0
0
ns
Write command hold time
tWCH
40
45
ns
Write command pulse width
twp
40
45
ns
c8
SAMSUNG SEMICONDUCTOR
4
107
KMM48256/KMM48257
KMM58256/KMM58257
MEMORY MODULES
STANDARD OPERATION (Continued)
KMM48256J7-12 KMM48256/7-15
Symbol KMM58256/7-12 KMM58256/7-15 Units
Min
Max
Min
Max
Parameter
Write command to RAS lead time
tRWL
40
45
Write command to CAS lead time
tCWL
40
45
ns
Data-in set-up time
tos
0
0
ns
ns
Data-in hold time
tOH
40
45
ns
Write command hold time referenced to RAS
tWCR
100
120
ns
tOHR
100
120
Data-in hold time referenced to RAS
ns
ms
Refresh period (256 cycles)
tREF
CAS setup time (CAS-before-RAS refresh)
tCSR
25
30
ns
tCHR
55
60
ns
tRPC
20
20
ns
tNC
60
75
CAS hold time (CAS-before-RAS
refresh~
RAS precharge to CAS active time
4
Notes
4
PAGE MODE (KMM48256/KMM58256)
Page mod6' cycle time
CAS precharge time (page mode only)
NIBBLE MODE (KMM48257/KMM58257)
Nibble mode read or write cycle time
ns
40
30
ns
Nibble mode access time
tNCAC
Nibble mode CAS pulse width
tNCAS
30
40
ns
Nibble mode CAS precharge time
tNCP
25
30
ns
Nibble mode RAS hold time
tNRSH
40
50
ns
Nibble mode CAS hold time referenced to RAS
tRNH
20
20
ns
Nibble Mode CAS to W delay
tNcwo
30
35
ns
tNCWL
25
30
ns
Nibble Mode W to CAS lead time
NOTES
1. An initial pause of 100j.ls is required after power-up
followed by any 8 RAS cycles before proper device
operation is achieved. Before using the internal
refresh counter, 8 CAS-before-RAS refresh initialization cycles are required (instead of 8 RAS cycles).
2. VIH (min) and VIL (max) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH (min) and VIL (max), and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TIL loads and
100pF.
c8
SAMSUNG SEMICONDUCTOR
4. Operation within the tRCO (max) limit insures that
tRAC (max) can be met, tRco (max) is specified as a
reference point only. If tRCO is greater than the
specified fRCO (max) limit, then access time is con.
trolled exclusively by tCAc.
5. Assumes that tRCO :2:tRco (max).
6. This parameter defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL·
108
KMM48256/KMM48257
KMM58256/KMM58257
MEMORY MODULES
TIMING DIAGRAMS
•
READ CYCLE
f------------tRC'------------i
_ _ _ _"\I
V,H_
1---------tRAS----------t
11'----"""\1
-xf----tAR----i
V,LtRP
t----------tCSHt---------f
t R C D - - - t - + - - - tRSH----+-f
V,H_
-----++----......1-_ f - - f - - - t C A S - - - - - i
teRP
, ...........-----"""\1
V'L_
A
w
VIH-~W-I--n~
VIL-~
tC_A_C~_~~~_
f - - - - - - - tRAc _ _ _
a
VOH _ _ _ _ _ _ _ _ _ _ _ _
VOL-
OPEN
_ _...,
_
~~~~
WRITE CYCLE (EARLY WRITE)
IRC
RAS
tRAS
V'H_
V,L-
i\
~tRPr
tAR
ICSH
tRSH
tRCD
CAS
VIHVIL-
ICRP -
tCAS
1\ \
V}
j------- ICPN -
tASR
tRAH
tASC
f------[jA
VIH_
~
V,L- ........
ROW
ADDRESS
f\-
tCAH
f--
J@
I-----
COLUMN
ADDRESS
,&X
f-'
>I
,~
tCWL
I--twcs.
W
VIHV,L-
xxx
:X
J--tWCHtwp
[XA
I..c:XX
:X¥ .XX
'X
lXXAX
twcs(min) the cycle is an early
write cycle and the data output will remain open circuit throughout the entire cycle.
c8
SAMSUNG SEMICONDUCTOR
8. Either tRCH or tRRH must be satisfied for a read
cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading
edge in read-write cycles.
10. Operation within the tRAO(max) limit insures that
tRco(max) can be met. tRAO(max) is specified as a
reference point only. If tRAo is greater than the
specified tRAO(max) limit, then access time is controlled by tAA.
11. Normal operation requires the "T.F." pin to be connected to Vss or TTL logic low level or left unconnected on the printed wiring board.
12. When the "T.F." pin is connected to a defined posi·
tive voltage, the internal test function may be actio
vated. Contact Samsung Semiconductor for specific
operational details of the "test function".
126
KMM481 OOO/KM M581 000
MEMORY MODULES
TIMING DIAGRAMS
•
READ CYCLE
1-------------------tAC--------------------~
V'HV'L-
----"I
~I----
~----------~----------~I
V'H-
----+t----"'""'"'"'
V'L-
A
w
a
V'H- ~'1':1~'1':1("7'/:~~d~..:...-_+-----------""""i-~~----
V,L -
lCloC!.l.:...c..Q..:;~~4J
VOH- _ _ _ _ _ _ __
VOL-
WRITE CYCLE (EARLY WRITE)
lAC
RAS
tAAS
V'HV'L-
\
IAA
.l
f---tAPt--tCRP-.
ICSH
-IACO
CAS
V'HV'L-
tASH
-IRAOIASR
A
V'HV'L-
--
~
~
tRAl
I
IRAH
f------ --,
ROW
ADDRESS
W
V'L-
XX )(060ctxx
f-------tCPN -
~
ICAH
IASC-
~
..........
r-- -
COLUMN
ADDRESS
~Xx.Il#'M
ICWL
~
V'H-
1/ Jr-
ICAS
f\ \
X~
-
I
~
t-twp
.; '&y xlJXlYt..
1~'X.l
[WAf xx :N>f7-.."I¥lv. II
.7-..
IA L
IWCR
10S-
0
V'H-
r--
V'L-
~\'X¥¥' .~
VOHVOL-
----------------OPEN------------------
VALID DATA
10H~
a
-Iow-~
)Q .f-" ..f-"'¥-x.z.I:-Nx
.
'XX"xM xxNi:x.
~DON.TCARE
c8
SAMSUNG SEMICONDUCTOR
127
KMM481000/KMM581000
TIMING DIAGRAMS
MEMORY MODULES
(Continued)
FAST PAGE MODE READ CYCLE
RAS
CAS
A
Q
w
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
r-------------------------I~SP--------------------~
RAS
f----,-- ICSH
CAS
V'H-
--++--.....,
IRSH
ICRP
V'l-
A
w
o
Q
V'H-
V'l-
'.lI.X.~'" ~"':::="""f'C\Cltlf" ~.....!:::.!.:~'<¥l~OQj~ty ~-=~~-'<¥Y:£lOC'IY:::lc:t:::,;~
VOH-
------------------------------OPEN-----i1~------------------------
VOl-
~OON'TCARE
c8
SAMSUNG SEMICONDUCTOR
128
KMM481 OOO/KM M581000
TIMING DIAGRAMS
MEMORY MODULES
(Continued)
RAS-ONLY REFRESH CYCLE
NOTE: CAS-V'H' W, i5 =Don't Care
A
a
•
f----------tRC'---------1
V'H-
:"'V'i'j\J~1I:7'i7\1\7t1\ .Ir-----""""'\I 1'\7.~~1\7I';7\'1""""'7'\J'oV\J'O"C1\7I';7\'1~1'\7'I7\1\l'V
V,L -
~lLlo<'-lILl..w:~~v
I'------JI
,,~~o.c..w:~t::;/;.\,Q,j~~::.Llw'-llLl..w:~OL::.LlwQL.l~
VOH- _ _ _ _ _ _ _ _ _ _ _ _ _ _ O P E N - - - - - - - - - - - - - - VOL-
HIDDEN REFRESH CYCLE
f------- tRC------f-------
VIH_·--~:\_~---tAR
RAS
V'LtRSH
CAS
A
VIH-~'Jt--=~~1-"--I.-~ f7It:1~m"I:m"m7'J'!j"t'f'\74~"m7'\7~1'\7'I7\J'O"C.,.".i7'V~7'\?i7V.
V'L-
w
a
VOH- _ _ __
VOL-
CAS·BEFORE·RAS REFRESH CYCLE
NOTE: Address, W, jj
=Don't Care
tRC
tRP
RAS
tRAS
VIH-
V'L-
V,H
CAS
a
ttc~
tCHR
y
tRPC
\
V'L-
VOHVOL-
OPEN
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
129
KMM481000/KMM581 000
MEMORY MODULES
PACKAGE DIMENSIONS
KMM58~OOO
(1M x 8 SIMM)
Units: Inches (millimeters)
1------------:3.500 (88.90)---------------1
1-----------3.234 (82.14)--------------1
0.200 (5.08)
RO.067(1.70)
MAX
0.125 DIA±0.02 (3.18±0.51)
MAX
DDDDDD
0.047 (1.19)
-jl
0.080 (2.03)
0.053 (1.36)
0.300 (7.62)
TOLERANCES: ±0.005 (0.13) UNLESS OTHERWISE SPECIFIED
KMM481000 (1M x 8 SIP)
I
I
3.200 ± 0.005 (81.28±0.13)
10.200 (5.08)
MAX
DDDDDDDD
mmwvvvrnrmlVVVml1
0.018±0.OO~. (0.46±0.05)
c8
I
I
SAMSUNG SEMICONDUCTOR
0.051 ±0.OO5
(1.30±0.13)
I
I
0.100±.005
(2.54±0.13)
O.O~~
(025 ± 0.05)
II
130
MEMORY MODULES
KMM491 OOO/KM M591 000
1Mx9 DRAM SIP and SIMM Memory Modules
FEATURES
GENERAL DESCRIPTION
• 1,048,576)( 9-bit Organization
• Ninth device has separate 0, Q and CAS for Parity
applications.
• Performance range:
The Siimsung KMM491000 and KMM591000 are
1M x 9 dynamic RAM high density memory modules.
The ninth bit is generally used for parity and is controlled
by CAS9. Samsung 1M x 9 memory modu les consist of
nine KM41C1000 DRAMS in 20-pin SOJ packages
mounted on a 30 pin glass-epoxy substrate. A 0.22"F
decouping capacitor is mounted under each DRAM.
tRAC
tCAc
KMM491000-10
100ns
25ns
tRc
190ns
KMM591000-10
100ns
25ns
190ns
KMM491000-12
120ns
30ns
220ns
KMM591000-12
120ns
30ns
220ns
The 1M x 9 DRAM modules are available in two package styles. The KMM491000 is SIP with leads suitable
for through hole mounting or for mounting in a socket.
The KMM591000 is SIMM with edge connections and
is intended for mounting into 30 pin edge connector
socket.
Fast Page Mode capability
CAS·before·RAS Refresh capability
RAS·only and Hidden Refresh capability
TTL compatible Inputs and outputs
Single + 5V:!: 10% power supply
512 cycles/8ms refresh
JEDEC standard pinout
•
•
•
•
•
•
•
PIN CONFIGURATION ~~~
FUNCTIONAL BLOCK DIAGRAM
AO-A9
o---~or___------,
RASO---~r------,
CAS o----rlt--------,
W <>--1o-H-t------.,
001
DOS
006
PIN NAMES
Pin Name
DO?
008
09
CAS9
09
PIN NAMES
Ao-A9
Pin Function
Address Inputs
DO
Data InlOut
Os
Data In
09
Data Out
W
ReadlWrite Input
RAS
Row Address Strobe
CAS
Column Address Strobe
Column Address Strobe
KM M491 000-1 0 100ns SIP
Page Mode
CASs
KMM491000-12 120ns SIP
Page Mode
Vee
Power (+5V)
KMM591000-10 100ns SIMM Page Mode
Vss
Ground
KMM591000-12 120ns SIMM Page Mode
N.C.
No Connection
o
c=J
CJ
CJ
c=J
CJ
CJ
CJ
CJ
CJ
o
• FOR PARITY BIT
., TEST FUNCTION ON PIN 24 ALSO
WILL BE AVAILABLE BY OPTION
c8
SAMSUNG SEMICONDUCTOR
131
I
KMM491 OOO/KM M591 000
MEMORY MODULES
ABSOLUTE MAXIMUM RATINGS·
Parameter
Voltage on Any Pin Relative to Vss
Symbol
Value
Unit
VIN, VOUT
-1 to + 7.0
V
Vcc
-1 to + 7.0
V
Voltage on Vcc Supply Relative to Vss
-55 to +150
Power Dissipation
T"Q
PD
·C
5.4
mW
Short Circuit Output Current
los
50
rnA
Storage Temperature
* Permanent device damage may occur If "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage
referenced to Vss, TA=O to 70·C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
6.5
V
Input Low Voltage
VIL
-1.0
-
0.8
V
Parameter
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter
Operating Current*
(RAS and CAS Cycling @tRC = min)
Symbol
KMM491 000·10, KMM591000-10
KMM491000-12, KMM591000·12
Standby Current
(RAS = CAS = VI H)
Icc1
Icc2
RAS-Only Refresh Current*
(CAS = VIH, RAS Cycling @tRC= min)
KMM491000·10, KMM591000-10
KMM491000·12, KMM591000-12
Icc3
Fast Page Mode Current*
(RAS=VIL, CAS Cycling @tpc=min)
KMM491000·10, KMM591000·10
KMM491000·12, KMM591000-12
IcC4
Standby Current
(RAS = CAS = Vee - 0.2V)
CAS-Before-RAS Refresh Current*
(RAS and CAS Cycling @tRc=min)
IcC5
KMM491000-10, KMM591000-10
KMM491000·12, KMM591000-12
Ices
Min
Max
Unit
-
540
450
rnA
rnA
18
rnA
540
450
rnA
rnA
360
270
rnA
rnA
9
rnA
540
450
rnA
rnA
-
-
Input Leakage Current
(Any input 0:sVIN :s6.5V,
all other pins not under test = 0 volts)
IlL
-90
90
,.A
Output Leakage Current
(Data out is disabled, 0:sVouT :s5.5V
10L
-10
10
,.A
Output High Voltage Level
(loH= -5mA)
VOH
2.4
-
V
Output Low Voltage Level
(loL = 4.2mA)
VOL
-
0.4
V
*NOTE: ICCh ICC3, IcC4, and Ices are dependent on output loading and cycle rates. Specified values are obtained with
the output open. Icc is specified as an average current.
c8
SAMSUNG SEMICONDUCTOR
132
KMM4910001KMM5910oo
CAPACITANCE
MEMORY MODULES
(TA=25"C)
Parameter
Symbol
Min
Max
Unit
Input Capacitance (Ao-Ag, W, CAS, RAS)
C,N,
-
60
pF
Input Capacitance (Dg, CASg)
C'N2
-
7
pF
Input Capacitance (00,-008)
Coa
-
15
pF
Output Capacitance (Dg)
COg
-
10
pF
AC CHARACTERISTICS
I
(O·CsTAsWC, Vcc=5.0V±10%. See notes 1, 2)
Parameter
Symbol
KMM4(5)91000·10
Min
Max
190
KMM4(5)91000·12
Min
Max
Units
Notes
ns
Random Read or Write Cycle Time
tRC
Access Time from RAS
tRAC
100
220
120
ns
3,4, 10
Access Time from CAS
tCAC
25
30
ns
3, 4, 5
3, 10
Access Time from Column Address
tAA
50
60
ns
Access Time from CAS Precharge
tCPA
55
65
ns
3
CAS to Output in Low-Z
tCLZ
5
ns
3
Output Buffer Turn-off Delay Time
tOFF
0
30
0
35
ns
6
Transition Time (rise and fall)
h
3
50
3
50
ns
2
RAS Precharge Time
5
ns
tRP
80
RAS Pulse Width
tRAS
100
RAS Hold Time
tRSH
25
30
ns
CAS Precharge time (except fast page)
tCPN
15
20
ns
CAS Hold Time
tCSH
100
120
CAS Pulse Width
tCAS
25
10,000
30
10,000
ns
RAS to CAS Delay Time
tRCD
25
75
25
90
ns
4
RAS to Column Address Delay Time
tRAD
20
50
20
60
ns
10
CAS to RAS Precharge Time
tCRP
10
10
ns
Row Address Set-up Time
tASR
0
0
ns
Row Address Hold Time
tRAH
15
15
ns
Column Address Set-up Time
tASC
0
0
ns
Column Address Hold Time
tCAH
20
25
ns
Column Address Hold Time Reference to RAS
tAR
95
115
ns
. tRAl
50
60
ns
ns
Column Address to RAS Lead Time
90
10,000
120
10,000
ns
ns
Read Command Set-up Time
tRCS
0
0
Read Command Hold Time Referenced to CAS
tRCH
0
0
ns
8
Read Command Hold Time Reference to RAS
tRRH
0
0
ns
8
Write Command Hold Time
tWCH
20
25
ns
c8
SAMSUNG SEMICONDUCTOR
133
KMM491OOO/KMM591000
AC CHARACTERISTICS
MEMORY MODULES
(Continued)
Parameter
Symbol
KMM4(5)91000·10
KMM4(5)91000·12
Min
Min
Max
Max
Units
Notes
Write Command Hold Time Referenced to RAS
tWCA
95
115
ns
Write Command Pulse Width
twp
20
25
ns
Write Command to RAS Lead Time
tAWL
25
30
ns
Write Command to CAS Lead Time
tewL
25
30
ns
Data-in Set-up Time
t DS
0
0
ns
9
tDH
20
25
ns
9
Data-in Hold Time Referenced to RAS
tDHR
95
Refresh Period (512 cycles)
tREF
Data-in Hold Time
115
ns
8
8
ms
Write Command Set-up Time
twcs
0
0
ns
CAS Set·up Time (CAS before RAS refresh)
tCSR
10
10
ns
CAS Hold Time (CAS before RAS refresh)
tCHR
30
30
ns
RAS Precharge to CAS Hold Time
tAPC
10
10
ns
tpc
60
70
ns
Fast Page Mode Cycle Time
----- --
---
\---
CAS Precharge Time (fast page mode)
tcp
10
RAS Pulse Width (fast page mode)
t RASP
100
15
100,000
120
7
ns
100,000
ns
NOTES
1. An initial pause of 2001's is required after power-up
followed by any 8 RAS cycles before proper device
operation is achieved.
2. V'H(min) and V'L(max) are reference levels for measuring timing of input signals. Transition times are
measured between V'H(min) and V,dmax) and are
assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and
100pF.
4. Operation within the tACD(max) limit insures that
tRAc(max) can be met. tACD(max) is specified as a
reference pOint only. If tACO is greater than the
specified tACD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tAcD~tACD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not
referenced to VOH or VOL.
7. twcs is non restrictive operating parameters. It is
included in the data sheet as electrical characteris- .
tics only. If twcs>twcs(min) the cycle is an early
write cycle and the data output will remain open cir·
cuit throughout the entire cycle.
ciS SAMSUNG SEMICONDUCTOR
8. Either tACH or tARH must be satisfied for a read
cycle.
9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading
edge in read-write cycles.
10. Operation within the tAAD(max) limit insures that
tACD(max) can be met. tAAD(max) is specified as a
reference point only. If tAAD is greater than the
specified tAAD(max) limit, then access time is controlled by t AA •
11. Normal operation requires the "T.F." pin to be connected to Vss or TTL logic low level or left unconnected on the printed wiring board.
12. When the "T.F." pin is connected to a defined positive voltage, the internal test function may be actio
vated. Contact Samsung Semiconductor for specific
operational details of the "test function".
134
KMM491 OOO/KM M591 000
MEMORY MODULES
TIMING DIAGRAMS
READ CYCLE
I
tAAS----
- - - _ _ _ _ _ -1
---tAA--
- - tAP
tCRP
V'H-
-----+-+-----.t--..
V'L-
A
w
V'H-
~~~~~~~~~+_--+_------------~-~------
t---
tAA _ _ _ _
f------f--------Q
tCAC--
f--- tCLZ -
VOH- _ _ _ _ _ _ _ _ _ O P E N - - - - - - - - < Y
VOL-
WRITE CYCLE (EARLY WRITE)
"'...
1------- \$---_ _ _ _~ f - - - - - - - - - - V'HRAS
-
IOFF
IAAC---------.-j
VALID
DATA
lAC - - - - - - - - - -
IAAS--------I
11-----.1
IAA--
V'L-
CAS
V'HV'L-
w
f-----+--I--f----rlIWCA-
IAWL---
----1
?v~7\,~?V~?V~I~D~Sl~·~_~_I_D_H_~~~~~~~~~~~~~~~~~~
o
VALID DATA
- - IDHA----~
Q
VOH- _ _ _ _ _-'-_ _ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
VOL-
~DON'TCARE
c8
SAMSUNG SEMICONDUCTOR
135
KMM491OOO/KMM591000
TIMING DIAGRAMS
MEMORY MODULES
(Continued)
FAST PAGE MODE READ CYCLE
t-------------tRAsP
---------------1
f-------,--lcsH
f---f--Ipc
CAS
A
VIH-
-IRSH
-i--,---,..---.-l
tc~
ICRP
-++--""""b..
VIL-
VIH- n. ..r.:=L
VIL-
Q
1r
lRRH
IRCH--j
.......
VIH-
~~~~&-------.....r,~r------~\-----------I~m....,..,XX)(
VIL-
,¥Ji.~IoLl.c"
.~
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
VIHVIL-
VIHVIL-
A
VIL-
w
VIH-
D
Q
VIL-
VOHVOL-
r--
IOHR
---1
------------------OPEN
---~fl~------------------~
c8
SAMSUNG SEMICONDUCTOR
(;JON'TCARE
136
MEMORY MODULES
KMM491OOO/KMM591000
TIMING DIAGRAMS
(Continued)
RAS·ONLY REfRESH CYCLE
NOTE: CAS
I
=VIH, TN, A9 =Don't Care
r----------------IRC----------------~
---------1
VIH-
r - - - - - - - IRAS-----1
1""--------L
VIL-
A
VOHIOPEN
------------------------~
VOL-
HIDDEN REfRESH CYCLE
lAC
IRC
tRP
tRAS
tAR
VIH-
VILtRSH
tCHR
- - tCAS
VIHCAS
VIL-
IASR
VIH-
A
VIL-
VIHVILtRAC
tCAC
tCLZ
VOH-
OPEN --~r)()d'
Q
VOL-
VALID DATA
CAS-BEfORE·RAS REfRESH CYCLE
NOTE: Address,
TN,
D
=Don't Care
r--------tRC---------~
r------tRAS------1
VIH-
tRP----\
------~
VILtCSR
tCHR
CAS
VOH-
Q
VOL_-------------- OPEN - - - - - - - - - - - - - - - - -
~DON.TCARE
c8
SAMSUNG SEMICONDUcrOR
137
KMM491 OOO/KM M591 000
MEMORY MODULES
PACKAGE DIMENSIONS
KMM591000 (1 M )( 9 SIMM)
Units: Inches (millimeters)
1-----------3.500 (88.90),-------------1
3.234 (82.14)
10
Tg iil
RO.067(1.70)
0.125 DIA. ±0.02
0.200 (5.08)
MAX
(3.18±0.51)
~
~gg~~,ggD~~
0.300 (7.62)
~I
0.047 (1.19)
0.053 (1.35)
KMM491000 (1M)( 9 SIP)
I
I
3.200000.005 (81.28±0.13)
H
0.200 (5.08)
MAX
TI DDDDDDDDD
rr
-
II
---j
c8
0.018±0.002
(0.46±0.05)
III
~
1---(1.-:-30-±0'-.1-:-3)
SAMSUNG SEMICONDUCTOR
0.010±0.0021L(0.25 ± 0.05) I
138
Static RAM
Capacity
Pari Number
64K bit
tKM6264A-7
KM6264A-10
KM6264A-12
tKM6264AL-7
KM6264AL-10
KM6264AL-12
ttKM6165-25
KM6165-35
KM6165-45
KM6465-25
64K bit
KM6465-35
KM6465-45
KM6865-35
KM6865-45
KM6865-55
KM62256P-10
KM62256P-12
KM62256P-15
KM62256LP-10
KM62256LP-12
KM62256LP-15
ttKM61257-25
KM61257-35
256K bit
KM61257-45
KM64257-25
KM64257-35
KM64257-45
KM68257-35
KM68257-45
KM68257-55
t New Product
tt Under Development
Organization
Current
Speed
Technology Active, mA Standby, p.A Packages
(ns)
Typ (max) Typ (max)
35
35
35
35
35
35
(70)
(70)
(70)
(70)
(70)
(70)
(1mA)
(1mA)
(1mA)
(1mA)
2 (0.1mA)
2 (0.1mA)
28-Pin DIP
28-Pin DIP
28-Pin DIP
28-PinDIP
28-Pin DIP
28-Pin DIP
Remark
Now
Now
Now
Now
Now
Now
8Kx8
8Kx8
8Kx8
8Kx8
8Kx8
8Kx8
70
100
120
70
100
120
CMOS
CMOS
. CMOS
CMOS
CMOS
CMOS
64Kx1
64Kx1
64Kx 1
16Kx4
16Kx4
16Kx4
8Kx8
8Kx8
8Kx8
25
35
45
25
35
45
35,
45
55
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
22-Pin
22-Pin
22-Pin
22-Pin
22-Pin
22-Pin
28-Pin
28-Pin
28-Pin
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
under development
under development
under development
under development
under development
under development
under development
under development
under development
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
32Kx8
256Kx 1
256Kx 1
256Kx 1
64Kx4
64Kx4
64Kx4
32Kx8
32Kx8
32Kx8
100
120
150
100
120
150
25
35
45
25
35
45
35
45
55
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
35 (60)
35 (60)
35 (60)
35 (60)
35 (60)
35 (60)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(1mA)
(1mA)
(1mA)
(0.1mA)
(0.1mA)
(0.1mA)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
(100)
28-Pin
28-Pin
28-Pin
28-Pin
28-Pin
28-Pin
24-Pin
24-Pin
24-Pin
24-Pin
24-Pin
24-Pin
28-Pln
28-Pin
28-Pin
DIP
DIP
DIP
DIP
DIP
DIP
SDIP
SDIP
SDIP
SDIP
SDIP
SDIP
DIP
DIP
DIP
Now
Now
Now
Now
Now
Now
under development
under development
under development
under development
under development
under development
under development
under development
under development
KM6264A1KM6264AL
CMOS SRAM
BK x B Bit Static RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The KM6264A/AL is a 65,538·bit high speed Static
Random Access Memory organized as 8,192 words by
8 bits. This device is fabricated using Samsung's
advanced CMOS process.
Fast Access Time 70, 100, 120ns (max.)
Low Standby Current: 100pA (max.)
Low Data Retention Current: 50pA (max.)
Capability of Battery Back·up Operation
Data Retention Voltage: 2.0V (min.)
Single 5V:t 10% supply
TTL compatible Inputs and outputs
Pin compatible with 84K EPROMS
Fully Static Operation
Standard 28 pin DIP
Common 1/0, Tristate Output
The KM6264A/AL has an output enable input for
precise control of the data outputs. It also has chip
enable inputs for the minimum current power down
mode. The KM6264A/AL has been designed for high
speed and low power applications. It is particularly
well suited for battery backup non-volatile memory
applications.
Two versions are availabl~; the KM6264A and
KM6264AL. The L·version is specified with lower
standby and data retention currents than the standard
version. Otherwise the two versions are identical.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
PRECHARGE CIRCUIT
-vee
-vss
A3 o-J~~I====1
0::
A4
w
A5o-j~~===l
A6o-j~~===l
A7 o-l~~===l
AS o-l~I:=j:===l
A 10
o-I-r::SI=;I====1
A 12
o-l---t~I====l
0
0
()
w
0
w
0::
a.
s:0
18
'"x
~
()
w
0
==
0
0::
co
on
18
co
co
. .
'"x
'"x
()
w
0
==
0
0::
0::
I/O,o---~--t.;l-:-I
I
1/0. o-~++---t.;l----1ICON
Pin Name
~-A'2
WE
5Eo---~cLr_-....,
WE
Write Enable
CS" CS2
Chip Select
OE
1/0,-1/0.
c8 SAMSUN~
SEMICONDUCTOR
Pin Function
Address Inputs
Output Enable
Data InputslOutputs
Vee
Power (+5V)
Vss
Ground
N.C.
No Connection
141
•
KM6264A1KM6264Al
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
(See Note)
Symbol
Rating
Units
Voltage on any pin relative to v.ss
V'N, VOUT
-0.3 to Vee + 0.5
V
Voltage on Vee supply relative Vss
Vee
-0.5 to + 7.0
V
Parameter
Power Dissipation
Po
1.0
W
Storage Temperature
Tstg
-55 to + 125
·C
Operating Temperature
TA
o to
·C
+70
• Note: Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operations sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
(TA=O·C to 70·C)
Symbol
Min
Typ
Max
Unit
5.0
5.5
V
0
0
V
Supply Voltage
Vee
4.5
Ground
Vss
0
Input High Voltage
V'H
2.2
-
Vcc+ 0.3
V
V'L
-0.3·
-
0.8
V
Input Low Voltage
·Note: V'L (min) = - 3.0V for:s50ns pulse.
DC CHARACTERISTICS
(TA= O·C to 70·C, Vee = 5V ± 10%, unless otherwise specified)
Parameter
Test Conditions
Symbol
Input Leakage Current
Device
Min
Typ
Max Units
III
V'N = Vss to Vee
2
I'A
Output Leakage Current
ILO
CS1 = V'H or CS2 = V'L or
OE = V'H, Vss:sVllo:sVee
2
I'A
Operating Power Supply Current
ICCl
CS1 = V'L, CS2 = V'H,
louT=OmA
40
mA
Average Operating Current
Icc2
Min Cycle, 100% Duty
CS1 = V'L, CS2 = V'H
70
mA
Standby Power Supply Current
ISB
CS1 = V'H or CS2 = V'L
3
mA
ISBl
CS1 ~ Vcc - 0.2V
KM6264A
1
mA
- 0.3V :sCS2:s0.2V
KM6264AL
100
~
Output High Voltage
VOH
IOH= -1.0mA
Output Low Voltage
VOL
IOL=2.1mA
CAPACITANCE
35
2
2.4
V
0.4
V
(f=1MHz, TA=25·C)'
Parameter
Symbol
Test Conditions
Input Capacitance
C'N
V'N=OV
Input/Output Capacitance
CliO
VIIO=OV
Min
Max
Unit
-
6
pF
8
pF
·Note: Capacitance is sampled and not 100% tested.
c8
SAMSUNG SEMICONDUCTOR
142
KM6264A1KM6264AL
CMOS SRAM
AC CHARACTERISTICS
(Ta=O·C to 70·C, Vcc =5V±10%, unless otherwise specified.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
r--
•
0.8 to 2.4V
Input Rise and Fall Times
5 ns
Input and Output Timing
Reference Level
1.5V
1 TTL Load and C L' 100pF
(including scope and jig capacitance)
Output Load
'C L =30pF for KM6264A-7, KM6264AL-7
READ CYCLE
Parameter
Symbol
KM6264A-7
KM6264AL-7
KM6264A-10
KM6264AL-10
KM6264A-12
KM6264AL-12
Min
Min
Min
Max
Read Cycle Time
tAC
tAA
70
100
120
ns
tco" tC02
70
100
120
ns
tOE
35
50
60
ns
Output Enable to Valid Output
Chip Enable to Low-Z Output
t lZ " tlZ2
100
Unit
Max
Address Cycle Time
Chip Select to Output
70
Max
120
10
5
ns
10
ns
5
ns
Output Enable to Low-Z Output
tOlZ
5
Chip Disable to High-Z Output
tHZ" tHZ2
0
30
0
35
0
40
Output Disable to High-Z Output
tOHZ
0
30
0
35
0
40
Output Hold from Address Change
tOH
10
5
10
15
ns
ns
ns
WRITE CYCLE
Parameter
Symbol
KM6264A-7
KM6264AL-7
KM6264A-10
KM6264AL-10
KM6264A-12
KM6264AL-12
Min
Min
Min
Max
Max
Unit
Max
Write Cycle Time
twc
70
100
120
Chip Select to End of Write
tew
60
80
85
ns
Address Set-up Time
tAS
0
0
0
ns
Address Valid to End of Write
tAw
60
80
85
ns
Write Pulse Width
twp
40
60
70
ns
ns
Write Recovery from CS1 or WE
ns
tWA" tWA
0
5
5
Write Recovery from CS2
tWR2
10
15
15
Write to Output High-Z
tWHZ
0
Data to Write Time Overlap
tow
30
40
50
Data Hold from Write Time
tOH
0
0
0
ns
End of Write to Output Low-Z
tow
5
5
10
ns
c8
SAMSUNG SEMICONDUCTOR
30
0
35
0
ns
40
ns
ns
143
KM6284A1KM6264AL
CMOS SRAM
NOTES: 1. tHZ AND tOHZ are defined as
2.
3.
4.
5.
6.
7.
S.
9.
10.
11.
12.
the time at which the outputs achieve the open circuit condition and
are not referenced to the VOH or VOL levels.
At any given temperature and voltage condition, tHZ max is less than tLl min both for a given device
and from device to device.
A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the
latest transition among CS1 going low, CS2 going high and WE going low: A write ends at the earli·
est transition among CS1 going high, CS2 going low and WE going high. twp is measured from the
beginning of write to the end of write.
tew is measured from the later of CS1 going low or CS2 gOing high to the end of write.
tAS Is measured from the address valid to the beginning of write.
tWA is measured from the end of write to the address change. tWR1 applied in case a write ends at
CS1, or WE going high, tWR2 applied In case a write ends at CS2 going low.
If OE, CS2 and WE are In the Re8ci Mode during this period, the I/O pins are in the output 10woZ
state. Inputs of opposite phase to the outputs must not be applied because bus contention can occur.
If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in
high impedance state.
Dour is the read data of the new address.
If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Therefore, the input
signals of opposite phase to the output must not be applied to them.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
When CS1 Is low and CS2 is high, the address input must not be in the high impedance state.
TIMING DIAGRAMS
REAAD CYCLE (WE = V1H)
f----------tRc
-----------j
A
CS2
Dour
c8
------HIGH·Z ------{)('
SAMSUNG SEMICONDUCTOR
144
KM6264A1KM6264AL
TIMING DIAGRAMS
CMOS SRAM
(Continued)
WRITE CYCLE (WE CONTROLLED)
----twc-------------j
•
A
f - - - - - - - - - tAW _ _ _ _ __
~:-r.r-t""'!"'T"........." ' I _ - - - - - -
tew (4)------1r.,....,..'1""'r'.,....,..'1""'r''1''"'r'r-r:~,..,
-------tcw (4)-------1
CS2
-------..+.......................... I - - - - - l w p ( 3 ) . - - - - 1
r--------
r;=_t_DW_-_-_-_-t-~-_-_-_-_t_DH_---"I.
DIN
(10)
DATA VALID
- - - - - - - HIGH·Z+-----{
tWHZ (7)
DOUT
\ ) - - - - HIGH·Z
WRITE CYCLE (CS1 CONTROLLED)
- - - - ---------- IWC-------------i
A
1 - - - - - - - - I A W - - - - -_ __
~:-m""r't'"'"'t""'r'~\""\
f - - - - - - ICW (4) _ _ _ _._ _ '''T''T''T''T''T''TTT"t-rT7"T7"T'
- - t - - - - - - tew ( 4 ) , - - - - - - - 1 - CS2
(II)
DIN
HIGH·Z-+-----{
tLZ
DOUT
c8
low--+--
IWHZ(7)
'-----------
HIGH.Z ____~QS/QS/~~-------HIGH.Z-------
SAMSUNO SEMICONDUCTOR
145
o
KM6264A1KM6264AL
TIMING DIAGRAMS
CMOS SRAM
(Continued)
WRITE CYCLE (CS2 CONTROLLED)
~-------------------~--------------------~
A
~---------------tAW - - - - - - - - - - - - - - - - - j - - t w R I (6)
_+-__~f----------tcw(4)-----------I r-------t - - - - - - - - - - - - t c w (4) - - - -
0$2
t---------twP (3) - - - - - - - I
toW--+---tOH-
-----+-_HIGH.Z
DOUT
-+-----1(
(10)
DATA VALID
---HIGH·Z - - W I l \ f l { V \ N \ ( \ / J f - - - - - - H I G H · Z - - - - - - -
DATA RETENTION CHARACTERISTICS
Parameter
Vee for Data Retention
Data Retention
(TA=O·C to +70·C)
Tesl Condition
Symbol
Min
Typ
Max
Units
2.0
-
5.5
V
5.5
V
1
50"
p.A
1
50"
p.A
VORl
CS1~Vee-0.2V,
CS2~Vee-0.2V or
VOR2
CS2;S0.2V
2.0
IORI
Vcc53.0V, CS1~Vee-0.2V,
CS2~Vee-0.2V or CS2;S0.2V
IOR2
Vee = 3.0V, CS2;S0.2V
-
Data Retention Set·up Time
tsOR
Recovery Time
tROR
CS2;S0.2V
See Data Retention
Wave forms (below)
0
ns
tRC ""
ns
" 2Op.A max at T,,=O 40·C, KM6264A: 1.0mA (MAX) _
"" tRC = Read Cycle Time
c8
SAMSUNG SEMICONDUcroR
146
KM6264A1KM6264AL
CMOS SRAM
DATA RETENTION WAVEFORM (1) (CS1 Controlled)
-t----Data Retention Mode - - - + -
---1----
--+-_1
I
Cs1"Vee -O.2V
OV - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DATA RETENTION WAVEFORM (2) (CS2 Controlled)
Data Retention Mode
Vee
4.5V - - - - - - - - - tSDR
CS2
O.4V - - - - - - O.3V ",CS2",O.2V
OV _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
NOTE: In Data Retention Mode, CS2 controls the Address, WE, CS'1, OE and Din buffer. If CS2 controls data
retention mode, VIN for these inputs can be in the high impedance state. If CS1 controls the data
retention mode, CS2 must satisfy either CS2~ Vee - O.2Vor CS2:s0.2V. The other input levels (address,
WE, OE, 110) can be In the high impedance state.
FUNCTION TABLE
WE
CS1
CS2
OE
Mode
110 Pin
Vee Current
X
X
H
X
X
Power Down
High-Z
Ise
X
L
X
Power Down
High-Z
Ise
H
L
H
H
Output Disabled
High-Z
Icc
H
L
H
L
Read
Dour
Icc
L
L
H
X
Write
DIN
Icc
c8
SAMSUNG SEMICONDUCTOR
147
CMOS SRAM
KM6264A1KM6264AL
PACKAGE DIMENSIONS
Units: Inches (millimeters)
28 LEAD PLASTIC DUAL IN LINE PACKAGE
C!
j-------
f----+----H-;:. ~
III
~
d
==i
~-------------1.~~5~(37-.2~)------------~
0.008 ( 0 . 2 ; f
0.012 (0.30)
MAX
0.120 (3.05)
V_-+--L---.:::MIN
0.022 (0.56)
..
eSC SAMSUNG SEMICONDUCTOR
MIN
148
KM62256AP/KM62256ALP
CMOSSRAM
32K x 8 Bit Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access TIme 80, 100, 120ns (max.)
• Low Power Dissipation
Standby: O.SSmW (max.)
Operating: 248mW (max.)
• Low Data Retention Current: SOItA (max.)
• Capability of Battery Back·up Operation
• Data Retention Voltage: 2.0V (min.)
• Single SV:!: 10% supply
• TTL compatible Inputs and outputs
• Pin compatible with 256K EPROMS
• Full Static Operation
- No clock or refresh required
• Standard 28 pin DIP
• Common 110, Tristate Output
The KM62256AP/ALP is a 262,144 bit high speed Static
Random Access Memory organized as 32,768 words by 8
bits.
This device is fabricated using Samsung's advanced
CMOS technology with polysilicon resistors.
The KM62256AP/ALP has an output enable for precise
control of the data output.
It also has a chip enable for the minimum current power down mode. The KM62256AP/ALP has been designed
for high speed and low power applications. It is particularly
well suited for battery backup non-volatile memory applications.
Two versions are available the KM62256ALP and
KM62256ALP. The L-version is specified with lower standby
and data retention currents than the standard version.
Otherwise the two versions are identical.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
PRECHARGE CIRCUIT
-Vee
-Vss
;;;
'"
@ ;;;
'"
c
;;;
'"
0
w
c
!!
~a:
co
~a:
x
x
!!
x
~
~
"'x
!!
Pin Name
Ao-AI4
WE
Write Enable
es
Chip Select
BE
Output Enable
1/01-I/Oa
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data Inputs/Outputs
Vee
+ 5V
Vss
Ground
Power Supply
149
•
CMOSSRAM
KM62256AP/KM62256ALP
ABSOLUTE MAXIMUM RATINGS
(See Note)'
Rating
Symbol
Value
Units
Voltage on any Pin Relative to Vss
VIN, VOUT
-0.3 to Vee + 0.5
V
Voltage on Vee Supply Relative Vee
Vee
-0.5 to +7.0
V
Power Dissipation
Po
1.0
W
Storage Temperature
TSla
-55 to +125
Operating Temperature
TA
'c
'c
o to
+70
°Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and "functional operation of the device at these or any other condl·
tions above those Indicated in the operational sections of this specification Is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(TA=O'C to 70'C)
Parameter
Symbol
Min
Typ
Max
Unit
V
Supply Voltage
Vee
4.5
5.0
5.5
Ground
Vss
0
0
0
V
Input H"igh Voltage
VIH
2.2
Vee+0.5
V
Input Low Voltage
VIL
-
0.8
V
Device
Min
-0.3'
Note: Vldmin) = - 3.0V fors50ns pulse
DC AND OPERATING CHARACTERISTICS
(TA=O'C to 70'"C, Vce =5V±10%, unless otherwise"specified)
Parameter
. Input Leakage Current
Symbol
Test Conditions
ILl
VIN = Vss to Vee
Output Leakage Current
ILO
= VIH or OE' = VIH
VIIO = Vss to Vee
Operating Power Supply
Current
Icc1
CS=VIL,
lOUT = OmA
Average Operating Current
1=
Min Cycle, 100% Duty
CS=VIL,loUT=OmA
Iss
CS=VIH
Standby Power Supply
Current
as
Iss1
CS~Vcc-0.2V
Output Low Voltage
VOL
IOL=2.1mA
Output High Voltage
VOH
IOH= -1.0mA
c8
SAMSUNG SEMICONDUCTOR
Typ
--
35
KM622~AP
KM62256ALP
2
2.4
Max
Units
1
pA
1
p.A
45
mA
60
mA
2
mA
1
mA
100
pA
0.4
V
V
150
CMOSSRAM
KM82256AP/KM82256ALP
CAPACITANCE
(T,,=25·C, Vee = 5V, f=1.0 MHz)
Pa...m.t.r
Symbol
Conditions
Input Capacitance
C'N
V'N=OV
Input/Output Capacitance
CI/O
Vl/o=OV
Min
Max
Unit
-
6
pF
8
pF
I
Note: Capacitance Is periodically sampled and not 100% tested.
AC CHARACTERISTICS
(TA=O·C to 70·C, Vcc =5V ± 10%, unless otherwise specified)
TEST CONDITIONS
Valu.
P....m.t.r
0.8 to 2.4V
Input Pulse Levels
Input Rise and Fall Times
5 ns
Input and Output Timing
Reference Levels
1.5V
1 TIL Load and CL = 100 pF
(Including scope and jig capacitance)
Output Load
READ CYCLE
Paramet.r
Symbol
KM82258AP-8
KM6284ALP-8
Min
Read Cycle Time
tRC
Address Access Time
Chip Select to Output
---'--
-
Max
Min
Max
100
80
t""
t ACS
KM82258AP·10
KM6284ALP·10
KM82258Ap·12
KM6284ALP·12
Min
Unit
Max
120
ns
80
100
120
ns
80
100
120
ns
Output Enable to Valid Output
tOE
Chip Enable to Low·Z Output
tCLZ
5
10
10
ns
Output Enable to Low·Z Output
tOLZ
5
5
5
ns
Chip Disable to Hlgh·Z Output
tCHZ
0
30
Output Disable to High·Z Output
tOHZ
0
30
Output Hold from Address Change
tOH
5
--
40
60
50
0
35
0
35
10
ns
0
40
ns
0
40
ns
15
ns
/j
c8
SAMSUNG SEMICONDUCTOR
151
CMOSSRAM
KM62256AP/KM62256ALP
WRITE CYCLE
Parameter
Symbol
KM62256AP.s
KM62256ALP.s
Min
Max
KM62256AP-10
KM62256ALP-10
Min
Write Cycle Time
twc
80
100
Chip Select to End of Write
tew
80
Address Set-up Time
tAS
Address Valid to End of Write
tAW
Write Pulse Width
twp
Write Recovery Time
tWR
Write to Output High-Z
tWHz
70
0
70
55
0
0
Data to Write Time Overlap
tow
30
Data Hold from Write Time
tOH
End of Write to Output Low-Z
tow
0
5
NOTES:
KM62256AP-12
KM62256ALP-12
Min
Max
120
85
0
85
70
5
0
50
0
10
0
80
80
30
5
0
40
0
10
35
Unit
Max
ns
ns
ns
ns
ns
ns
40
ns
ns
ns
ns
1. tCHZ and tOHZ are definded as the time at which the outputs achieve the open circuit condition and
are not referenced to the VOH or VOL level.
2. At any given temperature and voltage condition, tCHZ max is less then tClZ min both for a given device
and from device to device.
3. WE is high for read cycle.
4. Address valid prior to or coincident with CS transition low.
5. A write occurs during the overlap (twp) of a low CS and a low WE.
6. During this period, 1/0 pins are in the output state. The input signals out of phase must not applied.
7. CS or WE must be high during address transition.
8. If OE is high, 1/0 pins remain in a high-impedance state.
9. OE is continuously low. (OE VII)
10. When Chip Select (CS) is low, the address input must not be in the high impedance state.
=
TIMING DIAGRAMS
READ CYCLE (NOTE 1,2,3,4)
tr-------tRC-------IJr
. ~.
1-------t1
tAA
'X:I:Nxx
Ix xl'x\. 0t.
:x Xl(XX :xxxx
tOH.
tACS
,xx ,x
~Mxt :xMt
~xXXX
I.
tOE
x ,XXlC.l(XXXX
.XXX
lx:x.,...,..xxx S'xN .'l""xxxx
tOlZ
tClZ(2)
DOUT
c8
SAMSUNG SEMICONDUCTOR
r-1tCHZ-
(1)
xxx
,xx ,xx
,x ,xx .xx
,xx ,xx .l'lxN
I
f--- ~OHZ--
(1)
I I I 1/ VALID DATA \1\ \ \ \.
\\\\ I\.
11111
152
KM62256AP/KM62256ALP
CMOSSRAM
TIMING DIAGRAMS (Continued)
WRITE CYCLE 1 (WE CONTROLLED) (NOTE 5,6,7,8)
Iwe
•
I
'I(
)1\.
)
-twR-
~~
\
lew
l(l(l(l(
'/xU
:x
lX :JU..
t-l'.
.1'.1'. .I'.:xxM
,1'."1'." .1'. .1'." ."
.x.f¥J:-
r---
.1'.
IAS -
lAW
~r\\\\\\\~
t---IWHZ ( 6 ) _
DOUT
I
-.1[
j
Iwp(5)
,\\ \\\\\\\\\ \\\ \\\\\
II III II I II II II I III/
'DW-~-t----'DHI
WRITE CYCLE 2 (CS CONTROLLED) (NOTE 5,6,7,8,9)
f--------Iwe-------
f-----ew (4)1 _ _----1_lw
_ R_
r - - - - - - - IAW' - - - - - - - !
f----IOH----;
r---IOW
DOUT
_
c8
_
-----1I,~IDW----"DH-i~
SAMSUNG SEMICONDUCTOR
L~
;»»»)
153
CMOSSRAM
KM62256AP/KM62256ALP.
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
(TA=O·C to +70·C)
Test Condition
Vee for Data Retention
VOR
CS:?!Vee-0.2V
Data Retention Current
lOR
Vee = 3.0V
e5:?!Vee- 0.2V
Data Retention Set-up Time
tsOR
Recovery Time
tRoR
* tRe = Read
See Data Retention
Wave forms (below)
Min
Typ
2.0
1
0
tRe
.
Max
Units
5.5
V
50
pA
ns
ns
Cycle Time
DATA RETENTION WAVEFORM
tsOR-+_---Data Retention Mode----+--
vee
4.5V
CS~Vee-O.2\j
ov
Note: The Other inputs (Address,
c8
eYE, WE,
SAMSUNG SEMICONDUCTOR
I/O) can be in a high impedance state
154
KM62256AP/KM62256ALP
CMOSSRAM
PACKAGE DIMENSIONS
28 LEAD PLASTIC DUAL IN LINE PACKAGE
Units: Inches (millimeters)
~0'-15.
I
!
1.465 (37.2)
MAX
~
~
0.012 (0.30)
c8
SAMSUNG SEMICONDUcroR
155
ADVANCED INFORMATION
KM6165
CMOS SRAM
64K x 1 Bit Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 25, 35, 45ns (max.)
• Low Power Dissipation
Standby (TTL): 2mA (max.)
(CMOS): 100~ (max.)
Operating
: 100mA (max.)
• Single 5V:t 10% supply
• TTL compatible Inputs and outputs
• Full Static Operation
-No clock or refresh required
• Tristate Output
• Low Data Retention Current: 50~ (max.)
• Battery Back-up Operation
-2V (min.) Data Retention
• Standard 24·pln DIP (300 mil)
The KM6165 is a 65,538-bit high speed Static Random
Access Memory organized as 65,538 words by 1 bit. The
device is fabricated using Samsung's advanced CMOS
process.
The KM6165 has a chip enable input for the minimum
current power down mode.
The KM6165 has been designed for high speed applications. It is particularly well suited for the use in high
speed and low power applications in which battery back
up for nonvolatility is required.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
PRECHARGE CIRCUIT
All o----i~~==1
-Vee
A12
c::
w
c
A13
A14 0----i1-t~==1
A15
o----iI-t~==1
Ao
~~LJo<~=",J
§
c
MEMORY ARRAY
-vss
128 Rows
512 Columns
~
A3
1/0 CIRCUIT
DOUT
O----+------
C
A4
--vss
A13
i.!:-
DOUT
A17
Al
PIN NAMES
SELECT
I
Ih~ .l.~ ~~ .l.~J ~j d;d J~
A7 A8 A9 Al0AllA12A13A14AI5A16
SAMSUNG SEMICONDUCTOR
Pin Name
Aq-A"
Pin Function
Address Inputs
WE
Write Enable
CS
Chip Select
DIN/DOUT
Data Inputs/Outputs
Vee
+ 5V
Vss
Ground
Power Supply
159
•
ADVANCED INFORMATION
CMOS SRAM
KM64257
64K x 4 Bit Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 25, 35, 45ns (max.)
• Low Power Dissipation
Standby (TTL) : 2mA (max.,
(CMOS): 100~ (max.)
Operating
: 100mA (max.)
• Single 5V:!: 10% supply
• TTL compatible Inputs and outputs
• Full Static Operation
-No clock or refresh required
• Common 110, Tristate Output
• Low Data Retention Current: 50~ (max.)
• Battery Back·up Operation
-2V (min.) Data Retention
• Standard 24-pin DIP (300 mil)
The KM64257 is a 262,144-bit high speed Static Ran·
dom Access Memory organized as 65,538 words by 4
bits. The device is fabricated using Samsung's advanced
CMOS process.
The KM64257 has a chip enable input for the minimum current power down mode.
The KM64257 has been designed for high speed applications. It is particularly well suited for the use in high
speed and low power applications in which battery back
up for nonvoiatility is required.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
PRECHARGE CIRCUIT
A15o---I~~==f---'
AO
~-.l.J-Q:::::I=:=:I
A1 o---+~=I==I
A2 ~--.lJ-Q:±:::::::J
A3
_--.lJ-Q:±:::::::J
- - vee
II:
W
o
@
o
MEMORY ARRAY
- - vss
256 Rows
1024 Columns
A4
A5 _--.lJ-Q:±:::::::J
A6
o---+~=t====1
1/010---.._--1
I
I/O.o--_+--~
PIN NAMES
Pin Name
Ao-A15
WE
WE
Write Enable
CS
Chip Select
1/01-1/0.
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data inputs/Outputs
Vee
+ 5V
Vss
Ground
Power Supply
160
ADVANCED INFORMATION
KM68257
CMOS SRAM
32K x 8 Bit Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 35, 45, 55ns (max.)
• Low Power Dissipation
Standby (TTLj : 2mA (max.)!
(CMOS): 100,.A (max.)
Operating
: 100mA (max.)
• Single 5V:t 10% supply
• TTL compatible Inputs and outputs
• Full Static Operation
-No clock or refresh required
• Common 1/0, Tristate Output
• Low Data Retention Current: 5O,.A (max.)
• Battery Back·up Operation
-2V (min.) Data Retention
• Standard 28·pln DIP (600 mil)
The KM68257 is a 262,144·bit high speed Static Ran·
dom Access Memory organized as 32,767 words by 8
bits. The device is fabricated using Samsung's advanced
CMQS process.
The KM68257 has an output enable input for precise
control of the data outputs. It also has a chip enable
input for the minimum current power down mode.
The KM68257 has been designed for high speed ap·
plications. It is particularly well suited for the use in high
speed and low power applications in which battery back
up for nonvolatility is required.
FUNCTIONAL BLOCK DIAGRAM
CLOCK
A3
GEN
~=t==f
AE
AS"
A7o-
ABc>--
~
....
o
&l
!-'
-V-
A14
A,3
C-
512 Rows
512 Columns
1/08
,J1'!
r
W-
1 Al0
~
CS
a:
1/07
W:::-
o---_-~-l
-veo
- v••
ARRAY
MEMORY
0
A13"
!
I
w
0
~~=F==l
CIRCUIT
a:
....
A12 _ _ _
1/0,
PRECHARGE
..lo----I::r
. .~=r--,
A4 - -... ...
PIN CONFIGURATION
I
INPUT
DATA
CONTROL
C~~~K
1/0 CIRCUIT
rrn ________--1
f-----j
t--:::
II ICO~UMN SEL~CT
~ ~ ~ ~ ~ ~~
At
~1 ~2
At
A~O
All
PIN NAMES
Pin Name
A,;,·A,4
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O,·I/Oa
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data Inputs/Outputs
Vee
+ 5V Power Supply
V••
Ground
161
I
NOTES
EEPROM
Write Cycle
Speed
Technology Time (min)
(ns)
(ms)
Capacity
Part Number
Organization
16K bit
KM2S16A-25
KM2S16A-30
KM2S16A-35
KM2S17A-25
KM2S17A-30
KM2S17A-35
tKM2SC16-15
tKM2SC16-20
tKM2SC16-25
tKM2SC17-15
tKM2SC17-20
tKM2SC17-25
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
2KxS
250
300
350
250
300
350
150
200
250
150
200
250
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
10
10
10
10
10
10
2
2
2
2
2
2
KM2864A-20
KM2864A-25
KM2S64A-30
KM2S65A-20
SKxS
SKxS
SKxS
SKxS
200
250
300
200
NMOS
NMOS
NMOS
NMOS
10
10
10
10
KM2S65A-25
SKxS
250
NMOS
10
KM2S65A-30
SKxS
300
NMOS
10
KM2864AH-20
KM2864AH-25
KM2864AH-30
KM2865AH-20
SKxS
SKxS
SKxS
SKxS
200
250
300
200
NMOS
NMOS
NMOS
NMOS
2
2
2
2
KM 2865A H-25
SKxS
250
NMOS
2
KM2865AH-30
SKxS
300
NMOS
2
KM2SC64-20
SKxS
200
CMOS
5
KM2SC64-25
SKxS
250
CMOS
5
KM2SC65-20
SKxS
200
CMOS
5
KM2SC65-25
SKxS
250
CMOS
5
ttKM2SC256-15
32KxS
130
CMOS
5
ttKM2SC256-20
32KxS
200
CMOS
5
ttKM2SC256-25
32KxS
250
CMOS
5
64K bit
256K
t New Product
ttUnder Development
Features
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Data Polling
Data Polling
Data Polling
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling
Data POlling
Data Polling
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling,
Ready/Busy
Data Polling,
Page Mode
Data Polling,
Page Mode
Ready/Busy,
Page Mode
Ready/Busy,
Page Mode
Packages
Remark
24-Pln
24-Pln
24-Pln
28-Pln
28-Pln
2S-Pln
24-Pln
24-Pln
24-Pln
2S-Pln
2S-Pln
2S-Pln
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
DIP
Now
Now
Now
Now
Now
Now
under development
under development
under development
under development
under development
under development
2S-Pln
2S-Pln
2S-Pln
2S-Pln
DIP
DIP
DIP
DIP
Now
Now
Now
Now
i
2S-Pln DIP
Now
2S-Pln DIP
Now
2S-Pln
2S-Pln
2S-Pln
2S-Pln
DIP
DIP
DIP
DIP
Now
Now
Now
Now
2S-Pln DIP
Now
2S-Pln DIP
Now
2S-Pln DIP
Now
2S-Pln DIP
Now
2S-Pln DIP
Now
2S-Pln DIP
Now
Data Polling, 2S-Pln DIP under development
Toggle bit
Data Polling, 2S-Pln DIP under development
Toggle bit
Data Polling, 2S-Pln DIP under development
Toggle bit
KM2816A
NMOS EEPROM
2K x 8 Bit EEPROM with Latches and Auto-Write
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase-before-Write
- Automatic Write Timing
• Enhanced Write Protection
• Single 5 volt Supply
• Byte Write: 10ms max
• Fast Access Time: 2S0ns
• Power: SOmA-Standby (max)
110mA-Operating (max)
• Two Line Control-Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte-wide Memory Pinout
The KM2816A is a 16,384 bit Electrically Erasable and
Programmable Read-Only-Memory organized as 2,048
words by 8-bits, Its data can be modified using simple
TTL level signals and a single 5 volt power supply.
FUNCTIONAL BLOCK DIAGRAM
X Buffers Latches
and Decoder
Y Buffers Latches
and Decoder
Writing data into the KM2816A is very simple. The in·
ternally self·timed write cycle latches both address and
data to provide a free system bus during the 10ms (max)
write period.
The KM2816A is fabricated with the well defined
floating gate NMOS technology using Fowler-Nordheim
tunneling for erasing and programming.
PIN CONFIGURATION
16,384 Bit E'PROM
Memory Array
I/O Buffers
and Latches
Pin Name
OE
Control Logic
and Timing
Ao·A,o
I/O,-1I0a
CE
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
WE
Write Enable
Vee
Power (+ 5V)
Vss
Ground
165
I
NMOS EEPROM
KM2816A
ABSOLUTE MAXIMUM RATINGS·
Parameter
Rating
Symbol
Units
Voltage on any pin relative to Vss
V,N
-1 to + 7.0
V
Temperature Under Bias
Tbias
-40 to +85
·C
Storage Temperature
Totg
-65 to +125
·C
Short Circuit Output Current
los
5
mA
"NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maXimum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to Vss, TA=O to 70·C)
Parameter
Symbol
Min
Typ
Max
Unit
Vee
4.5
5.0
5.5
V
Supply Voltage
Ground
Vss
0
0
0
V
Input High Voltage
V,H
2.0
Vcc+ 1
V
Input Low Voltage
V'L
-1
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Max
Units
Operating Current
Icc
CE=OE=V,L
All I/O's = OPEN
Other Inputs = Vee
-
110
mA
Standby Current
19B
CE=V,H
All I/O's = OPEN
Other Inputs = Vee
-
50
mA
Input Leakage Current
III
V,N = 0 to 5.5V
p.A
ILO
VOUT=O to 5.5V
-
10
Output Leakage Current
10
p.A
Output High Voltage Level
VOH
10H= -400 p.A
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1 mA
-
0.4
V
Write Inhibit Vee Level
VWI
3.5
-
V
CAPACITANCE
(TA =25·C, Vce=5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
Input/Output Capacitance
CliO
VIIO=OV
pF
C,N
V,N=OV
-
10
Input Capacitance
6
pF
Note: Capacitance is periodically sampled and not 100% tested.
=8
SAMSUNG SEMICONDUCTOR
166
NMOS EEPROM
KM2816A
MODE SELECTION
CE
Mode
1/0
Power
Read
DouT
Active
Write
DIN
Active
High-Z
Standby
OE
WE
L
L
H
L
H
L
H
X
X
Standby and Write Inhibit
X
L
X
Write Inhibit
-
-
X
X
H
Write Inhibit
-
-
I
AC CHARACTERISTICS
(TA = o·c to 70·C, Vcc = 5V ± 10%, unless otherwise noted.)
TEST CONDITIONS
Value
Parameter
o to 3.0V
Input Pulse Levels
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
1 TTL Gate and CL = 100 pF
Output Load
READ CYCLE
Parameter
Read Cycle Time
Symbol
tAC
KM2816A·25
KM2816A·30
KM2816A·35
Min
Min
Min
Max
250
Max
300
Max
Unit
ns
350
Chip Enable Access Time
tCE
250
300
350
ns
Address Access Time
tAA
250
300
350
ns
120
ns
100
ns
100
ns
Output Enable Access Time
tOE
Chip Enable to Output in Low·Z
tu
10
Chip Disable to Output in High-Z
tHZ
10
Output Enable to Output in Low·Z
120
120
10
100
10
tou
50
50
Output Disable to Output in High-Z
tOHZ
10
10
Output Hold from Address Change
tOH
20
c8
SAMSUNG SEMICONDUCTOR
60
20
10
100
10
ns
ns
50
80
10
20
ns
167
KM2816A
NMOS EEPROM
WRITE CYCLE
Parameter
Symbol
Min
Max
Units
Write Cycle Time
twe
10
ms
Address Set-up Time
tAS
10
ns
Address Hold Time
tAH
70
ns
Write Set-up Time
tcs
0
ns
tCH
0
ns
Chip Enable to End of Write Input
tcw
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width
twp
100
ns
Data Latch Time
tOl
50
Write Hold Time
Data Valid Time
ns
1
tov
p's
Data Set-up Time
tos
50
ns
Data Hold Time
tOH
15
ns
TIMING DIAGRAMS
READ CYCLE
WE=V1H
A
ADDRESS
ADDRESS
tOH
DOUT
c8
SAMSUNG SEMICONDUCTOR
VALID DATA
168
KM2816A
NMOS EEPROM
TIMING DIAGRAMS
(Continued)
WE CONTROLLED WRITE CYCLE
I-----------IWC-----------l
A
ADDRESS
---i---tAH
tcs
•
tOES
f-----twp-----j
WE
Dour
~rr-----....
('"-.....,~m~'OOOO(r-~
~HIGH.Z--+--------+-------t
--f---tos--+--
CE
CONTROLLED WRITE CYCLE
f-----------twc-----------!
A
ADDRESS
---i---tAH
tcs
WE
tCH
· v v V V ' V V \ A.....
tOES
f-----tcw----l
Dour
~HIGH.Z--I--------+------I
--f---tos--+--
D,N IVVVVVV'VV\FV\.'YYVY'IA",l\l\Ivv"v
c8
SAMSUNG SEMICONDUCTOR
169
NMOS EEPROM
KM2816A
DEVICE OPERATION
Read
Reading data from the KM2816A is similar to reading
data from a static RAM. A read cycle occurs when WE
is high and both CE and OE are low. If either CE or OE
goes high the read cycle is terminated. This two line
control eliminates bus contention in a system environment. The Data 1/0 pins are in the high impedance state
whenever CE or OE is high.
Write
Writing data into the KM2816A is very easy. Only a single
5V supply and TTL level signals are required. The onchip data latches, address latches, high voltage
generator, and fully self-timed control logic make writing
as easy as writing to a static RAM.
A write cycle occurs when OE is high and both CE and
WE are low. The address is latched by the falling edge
of CE or WE, whichever occurs last. The data is latched
by the rising edge of CE or WE, whichever occurs first.
Address and data are conveniently latched in less than
200ns during a write operation. Once a byte write cycle
is initiated it will automatically continue to completion
within 10 ms or less. The existing data at the selected
address is automatically erased and the new data is
automatically written.
Standby
Power consumption may be reduced ",bout 60%.-EY
deselecting the device with a high input on CEo
c8
SAMSUNG SEMICONDUCTOR
Whenever CE is high, the device is in the standby mode
and 110, -1I0 s are in the high impedance state,
regardless of the state of OE or WE.
Data Protection
Features have been designed into the KM2816A that
prevent unwanted write cycles during power supply
transitions and system noise periods.
Write cycles are inhibited when Vee is less than
VW1 3.5 volts, the Write Inhibit Vee level. During powerup the KM2816A automatically prevents any write
operation for a period of 9 ms (Typical) after Vee
reaches the VW1 level. This will provide the system with
sufficient time to bring WE or CE to a high level before
a write can occur. Read cycles can be executed during
this initialization period.
Holding either OE low or WE high or CE high during
power-on and power-off with inhibit inadvertent writes.
=
Endurance and Data Retention
The KM2816A is designed for applications requiring, up
to 10,000 write cycles per E2PROM byte and ten years
of data retention. This means that each byte may be
reliably written 10,000 times without degrading device
operation, and that the data in the byte will remain valid
after its last write operation for ten years with or without
power applied.
170
NMOS EEPROM
KM2816A
PACKAGE DIMENSIONS
24 LEAD PLASTIC DUAL IN LINE PACKAGE
Units: Inches (millimeters)
~0-15"
I
I
-- - -------+ -
-~-
-$-"----1
--,"1="26=-=-°0:::(32::.:.0,-)_ _ _ '-"
MAX
c8
SAMSUNG SEMICONDUCTOR
v
I
-----I
~~
0.OO8(~
0.012 (0.30)
171
KM2817A
NMOS EEPROM
2K x 8 Bit EEPROM with Ready/Busy Function
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase·before·Wrlte
- Automatic Write Timing
- Ready/Busy Output Pin
• Enhanced Write Protection
• Single S volt Supply
• Byte Write: 10ms (max)
• Fast Access Time: 250ns
• Power: SOmA-Standby (max)
110mA-Operatlng (max)
• Two Line Control· Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte·wide Memory Pinout
The KM2817A is a 16,384 bit Electrically Erasable and
Programmable Read·Only·Memory organized as 2,048
words by 8·bits. Its data can be modified using simple
TTL level signals and a single 5 volt power supply.
FUNCTIONAL BLOCK DIAGRAM
Writing data into the KM2817A is very simple. The in·
ternally self-timed write cycle latches both address and
data to provide a free system bus during the 10ms (max)
write period.
The KM2817A has an open-drain Ready/Busy output
on pin 1 which signals when the write operation is complete. This device is fabricated with the well defined
floating gate NMOS technology using Flowler-Nordheim
tunneling for erasing and programming.
PIN CONFIGURATION
X Buffers Latches
and Decoder
16,384 Bit E2PROM
Memory Array
Y Buffer. Latche.
and Decoder
I/O Buffer.
and Latches
Pin Name
Control Logic
and Timing
Ao-A'0
ROY/BSY
1/0,-1/08
Chip Enable
OE
Output Enable
WE
Write Enable
N.C.
SAMSUNG SEMICONDUCTOR
Data Inputs/Outputs
CE
RDY/BSY
c8
Pin Function
Address Inputs
Ready/Busy Output
No Connection
Vee
Power (+5V)
Vss
Ground
172
KM2817A
NMOS EEPROM
ABSOLUTE MAXIMUM RATINGS·
Parameter
Symbol
Rating
Units.
Voltage on any pin relative to Vss
V,N
-1 to +7.0
V
Temperature Under Bias
Tb,as
-40 to +85
·C
Storage Temperature
Tstg
-65 to + 125
·C
Short Circuit Output Current
los
5
mA
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to Vss , TA=O to 70·C)
Parameter
Symbol
Min
Typ
Max
Unit
V
Supply Voltage
Vee
4.5
5.0
5.5
Ground
Vss
0
0
0
V
Input High Voltage
V,H
2.0
Vee + 1
V
Input Low Voltage
V,L
-1
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Max
Units
Operating Current
Icc
CE=OE=V,L
All 110's = OPEN
Other Inputs = Vee
-
110
mA
Standby Current
IS8
CE=V,H
All 110's = OPEN
Other Inputs = Vee
-
50
mA
Input Leakage Current
10
p.A
10
p.A
III
V,N = 0 to 5.5V
Output Leakage Current
ILo
VOUT=O to 5.5V
-
Output High Voltage Level
VOH
10H = - 400 p.A
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1 mA
-
0.4
V
Write Inhibit Vee Level
VWI
3.5
-
V
CAPACITANCE
(TA=25·C, Vee=5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
Input/Output Capacitance
CliO
VIIO=OV
pF
C'N
V,N=OV
-
10
Input Capacitance
6
pF
Note: Capacitance is periodically sampled and not 100% tested.
=8
SAMSUNG SEMICONDUCTOR
173
I
~
NMOS EEPROM
KM2817A
MODE SELECTION
CE
1/0
Power
Read
DouT
Active
Write
DIN
Active
High-Z
Standby
-
-
Mode
OE
WE
L
L
H
L
H
L
H
X
X
Standby and Write Inhibit
X
L
X
Write Inhibit
X
X
H
Write Inhibit
AC CHARACTERISTICS
(TA
=o·c to lO·C, Vcc =5V ± 10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
o to 3.0V
Input Pulse Levels
Input Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
1 TTL Gate and Cl
=100 pF
READ CYCLE
Parameter
Symbol
KM281lA·25
KM281lA·30
KM2817A·35
Min
Min
Min
Max
250
Max
Max
Unit
ns
Read Cycle Time
tRC
Chip Enable Access Time
tCE
250
300
350
Address Access Time
tM
250
300
350
ns
Output Enable Access Time
tOE
120
120
120
ns
Chip Enable to Output in Low-Z
tLZ
10
Chip Disable to Output in High-Z
tHZ
10
Output Enable to Output in Low·Z
tOLZ
50
Output Disable to Output in High-Z
tOHZ
10
Output Hold from Address Change
tOH
20
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SAMSUNG SEMICONDUCTOR
350
300
10
100
10
10
100
50
60
10
20
10
ns
100
10
20
ns
ns
50
80
ns
100
ns
ns
174
KM2817A
NMOS EEPROM
WRITE CYCLE
Parameter
Symbol
Min
Max
Units
Write Cycle Time
twc
10
ms
Address Set-up Time
tAS
10
ns
Address Hold Time
tAH
70
ns
Write Set-up Time
tCB
0
ns
ns
tCH
0
Chip Enable to End of Write Input
tcw
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width
twp
100
ns
Data Latch Time
tOl
50
Data Valid Time
tov
Data Set-up Time
tos
Data Hold Time
tOH
Time to Device Busy
tOB
Busy to Write Recovery Time
tBWR
Write Hold Time
ns
1
50
15
fls
ns
ns
120
50
•
ns
ns
TIMING DIAGRAMS
READ CYCLE
WE=V1H
A
ADDRESS
ADDRESS
1------tRC-----j
tOH
DOUT
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SAMSUNG SEMICONDUCTOR
175
NMOS EEPROM
KM2817A
TIMING DIAGRAMS
(CDntinued)
WE CONTROLLED WRITE CYCLE
Iwc
A
ADDRESS
lAS
IAH
ICH
ICS
CE
DE
IOES
Iwp
WE
DOUT
~HIGH.Z
10H
los
lov
VALID DATA
DIN
lOB
RDY/BSY
CE CONTROLLED WRITE CYCLE
Iwc
A
IAH
WE
DE
IOES
Icw
CE
DOUT
~HIGH.Z
lov
DIN
10H
los
VALID DATA
IDB
IBWR
RDY/BSY
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SAMSUNG SEMICONDUCTOR
176
KM2817A
NMOS EEPROM
DEVICE OPERATION
Read
Reading data from the KM2817A is similar to reading
data from a static RAM. A read cycle occurs when WE
is high and both CE and OE are low. If either CE or OE
goes high the read cycle is terminated. This two line
control eliminates bus contention in a system environment. The Data I/O pins are in the high impedance state
whenever CE or OE is high.
Write
Writing data into the KM2817A is very easy. Only asingle
5V supply and TTL level signals are required. The onchip data latches, address latches, high voltage
generator, and fully self-timed control logic make writing
as easy as writing to a static RAM.
A write cycle occurs when OE is high and both CE and
WE are low. The address is latched by the falling edge
of CE or WE, whichever occurs last. The data is latched
by the rising edge of CE or WE, whichever occurs first.
Address and data are conveniently latched in less than
200ns during a write operation. Once a byte write cycle
is initiated;it will automatically continue to completion
within 10 ms or less. The existing data at the selected
address is automatically erased and the new data is
automatically written.
Standby
Power consumption may be reduced about 60% by
deselecting the device with a high input on CEo
Whenever CE is high, the device is in the standby mode
and I/O, -I/Os are in the high impedance state,
regardless of the state of OE or WE.
Data Protection
Features have been incorporated into the KM2817A
design that prevent unwanted write cycles during power
supply transitions and system noise periods.
c8
SAMSUNG SEMICONDUCTOR
Write cycles are inhibited when Vee is less than 3.5
volts, the Write Inhibit Vee level. During power-up the
KM2817A automatically prevents any write operation for
a period of 9 ms (Typical) after Vee reaches the VW1
level. This will provide the system with sufficient time
to bring WE or CE to a high level before a write can occur. Read cycles can be executed during this initialization period.
Holding either OE low or WE high or CE high during
power-on and power-off with inhibit inadvertent writes.
Ready/Busy
The KM2817A has a Ready/Busy output pin ·that indicates when the write cycle is complete. The pin is normally high except when a nonvolatile write cycle is in
progress, in which case the pin is low.
The Ready/Busy output is configured as open-drain
driver there-by allowing two or more Ready/Busy output to be or-tied. This pin requires an appropriate pullup register for proper operation. The pull-up resistor
value for the Ready/Busy output maybe calculated as
follows:
R _ Vee (MAX) - VOL (MAX) _
5.1V
p IOL + IL
- 2.1mA + IL
Where IL is the sum of the input currents of all devices
tied to the Ready/Busy pin.
Endurance and Data Retention
The KM2817 A is designed for applications requiring, up
to 10,000 write cycles per E2PROM byte and ten years
of data retention. This means that each byte may be
reliably written 10,000 times without degrading device
operation, and that the data in the byte will remain valid
after its last rewrite operation for ten years with or
without power applied.
177
•
KM2817A
NMOS EEPROM
PACKAGE DIMENSIONS
Units: Inches (millimeters)
28 LEAD PLASTIC DUAL IN LINE PACKAGE
-,~0-15'
S
+ - - - - - - f--+---tt-;! ~
~ ~
~~
~____________~1.4~65~(37_.2~)____________~
0.008
MAX
(0.2;;-J
0.012 (0.30)
0.014 (0.36)
0.1 (2.54)
TYP
0.022 (0.56)
TYP
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SAMSUNG SEMICONDUCTOR
178
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
2K x 8 CMOS Electrically Erasable PROM
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase-Before-Write
- Automatic Write Timing
- DATA Polling and Verification
• 32-byte page Write 2ms max
- Effective 62_5,.slbyte write
• Enhanced Write Protection
• Single 5 volt Supply
• Fast Access Time: 150ns
• Power: 100,.A-Standby (max)
3OmA-Operatlng (max)
• Two Line Control-Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte-wide Memory Pin put
The KM28C16 is a 2,048 x 8 bit electrically erasable and programmable read-only-memory. Its data can
be modified using simple TTL level signals and a single 5 volt power supply.
Writing data into the KM28C16 is very simple. The internally self-timed write cycle latches both address and
data to provide a free system bus during the 2ms (max)
write period.
A 32-byte page write enables an entire chip written
in 128ms.
The KM28C16 features DATA-polling, which enables
the EEPROM to signal the processor that a write operation is complete without requiring the use of any external hardware.
The KM28C16 is fabricated with the well defined
floating-gate CMOS technology using Fowler-Nordheim
tunneling for erasing and programming.
FUNCTIONAL BLOCK DIAGRAM
x
PIN CONFIGURATION
Page Buffers
Buffers
A6
Lalches
and
16,384 Bit
Decoder
E'PROM
AS
A3
Memory
A2
Array
A1
AD
110 Buffers
and Latches
Conlrol Logic
and
Timing
PIN NAMES
Pin Name
Ao-A1O
1/0,-1/08
CE
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SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data Inputs/Outputs
Chip Enable
OE
Output Enable
WE
Write Enable
Vee
+5V
Vss
Ground
179
I
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Unit
Rating
Voltage on Any Pin Relative to Vss
VIN
-0.3 to 7.0
V
Temperature Under Bias
Tblas
-10 to +85
·C
Storage Temperature
T.tg
-65 to +125
·C
5
mA
Short Circuit Output Current
los
• Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
(Voltage referenced to Vss, TA=O to 70·C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Supply Voltage
Vss
0
0
0
V
Input High Voltage, all Inputs
VIH
2.0
Vee + 0.3
V
Input Low Voltage, all Inputs
VIL
-0.3
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
Test Conditions
Min
Max
Unit
Operating Current
lee
CE = OE = VIL, WE = VIH
All 110'5 = OPEN
All Addresses' (note 1)
-
30
mA
Standby Current (TTL)
ISBl
CE=VIH
All 110'5 = OPEN
1
mA
Standby Current (CMOS)
ISB2
100
pA
10
p.A
Parameter
CE~Vee-0.2
III
VIN =0 to Vee
Output Leakage Current
ILO
VOUT=O to Vee
-
10
p.A
Output High Voltage Level
VOH
IOH= -4oop.A
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1mA
-
0.4
V
Write Inhibit Vee Level
VWI
3.5
-
V
Input Leakage Current
All 110'5 = OPEN
• Note ,1. All addresses toggling from VIL to VIH at 5MHz
CAPACITANCE
(TA=25·C, Vee =5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
Input/Output Capacitance
ClIO
VIIO=OV
6
pF
Input Capacitance
CIN
VIN=OV
-
10
pF
Note: Capacitance is periodically sampled and not 100% tested.
c8
SAMSUNG SEMICONDUCTOR
180
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
MODE SELECTION
-
CE
OE
WE
L
L
H
Read
Dour
Active
L
H
L
Write
DIN
Active
Mode
I/O
Power
L
L
H
DATA-Polling
IlOa = Da
Active
H
X
X
Standby & Write Inhibit
High-Z
Standby
X
L
X
Write Inhibit
X
X
H
Write Inhibit
-
-
AC CHARACTERISTICS
•
(TA == O°C to 70°C Vee = 5V ± 10%, unless otherwise noted).
TEST CONDITIONS
Value
Parameter
0.45 to 2.4V
Input Pulse Levels
Input Rise and Fall Times
20 ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL Gate and Cl
= 100pF
READ CYCLE
Parameter
Symbol
KM28C16·15
Min
Max
KM28C16·20
KM28C16·25
Min
Min
Max
Max
Unit
Read Cycle Time
tRe
Chip Enable Access Time
teE
150
200
250
ns
Address Access Time
tM
150
200
250
ns
Output Enable Access Time
tOE
100
ns
Chip Enable to Output in Low-Z
tLZ
0
Chip Disable to Output in High-Z
tHz
5
Output Enable to Output in Low-Z
tOLZ
5
Output Disable to Output in High-Z
tOHZ
5
Output Hold from Address Change
tOH
10
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SAMSUNG SEMICONDUCTOR
150
200
80
60
0
50
5
0
70
5
50
5
10
ns
250
5
ns
90
5
70
5
10
ns
ns
90
ns
ns
181
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
WRITE CYCLE
Parameter
Symbol
Min
Max
Unit
Write Cycle Time
twc
2
ms
Address Set-Up Time
tAs
0
ns
Address Hold Time
tAH
80
ns
Write Set-Up Time
tcs
0
ns
Write Hold Time
tCH
0
ns
ns
Chip Enable to End of Write Input
tcw
100
Output Enable Set-Up Time
tOES
10
ns
Output Enable Hold Time
tOEH
ns
Write Pulse Width
twp
10
100
Data Set-Up Time
tos
50
ns
Data Hold Time
tOH
10
tslC
0.2
Byte Load Cycle
ns
ns
100
p's
Note: The timer for tSlC is reset at a falling edge of WE and starts at a rising edge of WE.
TIMING DIAGRAMS
READ CYCLE WE = V1H
ADD
f----IAA--
- IOH
Dour
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SAMSUNG SEMICONDUCTOR
VALID DATA
10HZ
VALID DATA
182
PRELIMINARY SPECIFICATION
CMOS EEPROM
KM28C16
TIMING DIAGRAMS
(Continued)
WE CONTROLLED WRITE CYCLE
ADD
•
IOES
DOUT
~HIGH.Z----------+-+-------H.----+--
CE CONTROLLED WRITE
ADD
WE
~
lAS
DE
lew
CE
DOUT
~HIGH.Z
los
DIN
c8
SAMSUNG SEMICONDUCTOR
183
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
TIMING DIAGRAMS
(Continued)
PAGE MODE WRITE (WE CONTROLLED WRITE CYCLE)
ADD
DATA
PAGE MODE WRITE (CE CONTROLLED WRITE CYCLE)
ADD
DATA
·NOTE 1. Tristate for 110,-1107, Doorn for 1I0e if the chip Is read. (See Data-polling)
c8
SAMSUNG SEMICONDUCTOR
184
PRELIMINARY SPECIFICATION
CMOS EEPROM
KM28C16
DEVICE OPERATION
READ
Reading data from the KM28C16 is similar to reading
data from a SRAM. A read cycle occurs when WE is high
and CE and OE are low. If either CE or OE goes high
the read cycle is terminated. This two line control
eliminates bus contention in a system environment. The
Data 1/0 pins are in the high impedance state whenever
OE or CE is high.
WRITE
Writing data into the KM28C16 is very easy. Only a sin·
gle 5V supply and TTL level signals are required. The
on-chip data latches, address latches, high voltage
generator, and fully self-timed control logic make writ·
ing as easy as writing to a SRAM .
•••• BYTE WRITE MODE····
The byte write mode of the KM28C16 is only a part of
the page write mode. A single byte data loading followed
by a taLe time·out and by a nonvolatile write cycle will
complete a byte mode write. In this mode, the write is
exactly identical to that of the KM2816A.
•••• PAGE WRITE MODE ••••
The KM28C16 allows up to 32 byte to be written in a
single page write cycle. A page write cycle consists of
a data loading period, in which from 1 to 32 byte data
are loaded into the KM28C16 internal registers and a
nonvolatile write period, in which the loaded data in the
registers are written to the EEPROM cells of the select·
ed page.
Data are loaded into the KM28C16 by sequentially pulsing WE with CE low and OE high. ON each WE, address
is latched on the falling edge of the WE and data is
latched on the rising edge of the WE. The data can be
loaded in any "Y" address order and can be renewed
in a data loading period.
Since the timer for the data loading period (taLC) is reset
at the falling edge of WE and starts at every rising edge
of WE, the only requirement on WE to continue the data
loading is that the interval between WE pulses does not
exceed the maximum taLe (1oo,..s). If OE goes Low duro
ing the data loading period, further attempt to load the
data will be ignored because the external WE signal is
blocked by OE signal internally. Consequently, the taLe
timer is not reset by the external WE pulse if OE is low.
The page address for the nonvolatile write is the "X"
address (A5-A10) latched on the last WE. The nonvolatile write period consists of an erase cycle and a program cycle. During the erase cycle, the existing data
of the locations being addressed are erased. The new
c8
SAMSUNG SEMICONDUCTOR
data latched at the register are written into the locations
during the program cycle. Note that only the addressed
location in a page are rewritten during a page write
cycle.
The KM28C16 also supports CE controlled write cycle.
That means CE can be used to latch address and data
as well as WE.
STANDBY
Power consumption is reduced to less than 1oo,..A by
deselecting the device with a high input on CE.
Whenever CE is high, the device is in the standby mode
and 1/0,-I/Os are in the high impedance state, regardless of the state of OE or WE.
DATA PROTECTION
Features have been designed into the KM28C16 that prevent unwanted write cycles during power supply transitions and system noise periods.
The KM28C16 has a protection feature against WE
noises: a WE noise the width shorter than 20ns (typ.)
will not start any unwanted write cycle.
Write cycles are also inhibited when Vee is less than
VW1 3.5 volts, the Write Inhibits Vee level.
During power-up, the KM28C16 automatically prevents
any write operation for a period of 2ms (typ.) after Vee
reaches the VW1 level. This will provide the system with
sufficient time to bring WE and CE to a high level before a write can occur. Read cycles can be executed during this initialization period. Holding either OE low or
WE high or CE high during power-on and power-off will
inhibit inadvertent writes.
=
DATA POLLING
The KM28C16 features DATA-Polling at II0 s to detect
the completion of a write cycle using a simple read and
compare operation. Such a scheme does not require any
external hardware. Reading the device at any time during a write operation will produce, at I10 s, an inverted
vale of last data loaded in to the EEPROM (1/0,-1/0 7
are at the high impedance state). True data will be
produced at allllO's once the write cycle has been completed.
ENDURANCE AND DATA RETENTION
KM28C16 is designed for applications requiring up to
10,000 write cycles per EEPROM byte and ten years of
data retention. This means that each byte may be reliably written 10,000 times without degrading device operation and that the data in the byte will remain valid after
its last write operation for ten years with or without power applied.
185
PRELIMINARY SPECIFICATION
KM28C16
CMOS EEPROM
PACKAGE DIMENSIONS
24 LEAD PLASTIC DUAL IN LINE PACKAGE
-- -
- - ------t-
-
Units: Inches (millimeters)
---$---
-<1>.
~0.008
I
L
(-;;,.,y
0.012 (0.30)
0.1 (2.54)
TYP
0.060 (1.52)
TYP
c8
SAMSUNG SEMICONDUCTOR
186
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
2K x 8 CMOS Electrically Erasable PROM
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Intemal Erase·Before·Wrlte
- Automatic Write Timing
- DATA Polling and Verification
- Ready/Busy Output Pin (KM28C17)
• 32·byte page Write 2ms max
- Effective 62.5p.&iby1e write
• Enhanced Write Protection
• Single 5 volt Supply
• Fast Access Time: 150ns
• Power: 100pA-Standby (max)
30mA-Operating (max)
• Two Line Control·Ellminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte·wide Memory Pinput
The KM28C17 is a 2,048 x 8 bit electrically erasable
and programmable read·only·memory. Its data can be
modified using simple TTL level signals and a single
5 volt power supply.
Writing data into the KM28C17 is very simple. The in·
ternally self·timed write cycle latches both address and
data to provide a free system bus during the 2ms (max)
write period.
A 32·byte page write enables an entire chip written
in 128ms.
The KM28C17 features DATA·polling, which enables
the EEPROM to signal the processor that a write oper·
ation is complete without requiring the use of any ex·
ternal hardware. Ready/Busy is a hardware scheme in
which Pin 1 is used to signal the status of the write oper·
ation and is especially useful in interrupt driven systems.
The KM28C17 is fabricated with the well defined
floating·gate CMOS technology using Fowler·Nordheim
tunneling for erasing and programming.
FUNCTIONAL BLOCK DIAGRAM
---;-
I
Page Buffers
r-
X
Buffers
latches
and
Decoder
r- r--
16,384 Bit
E'PROM
Memory
Array
\
Ao- A10
1
~
Y
Buffers
Latches
and
Decoder
I
110 Buffers
and Latches
r- r-f-
?
I
Pin Name
Control
Ao·A,o
Logic and
I/O,·I/Os
Timing
E-
I
I/O,-I/Os
E-
wE -
PIN CONFIGURATION
~
ROYIBSY
CE
OE
Pin Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
RDY/BSY
N.C.
c8
Ready/Busy Output
No Connection
Vee
+5V
Vss
Ground
SAMSUNG SEMICONDUCTOR
187
I
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
ELECTRICAL CHARACTERISTICS
Unit
Parameter
Symbol
Rating
Voltage on Any Pin Relative to Vss
VIN
-0.3 to 7.0
V
Temperature Under Bias
Tbl..
-10to +85
·C
Storage Temperature
Tst•
-65 to + 125
·C
Short Circuit Output Current
los
5
rnA
• Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
(Voltage referenced to Vss, TA=O to 70·C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Supply Voltage
Vss
0
0
0
V
Input High Voltage, all Inputs
VIH
2.0
Vee+ 0.3
V
Input Low Voltage, all Inputs
VIL
-0.3
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
Test Conditions
Min
Max
Unit
Operating Current
lee
CE=OE=VIL, WE=VIH
All 1I0's = OPEN
All Addresses' (note 1)
-
30
rnA
Standby Current (TTL)
IS81
CE=VIH
All 1I0's = OPEN
1
mA
Standby Current (CMOS)
ISB2
100
p.A
Parameter
CE~Vee-0.2
Input Leakage Current
III
VIN=O to Vee
Output Leakage Current
ILo
Vour=O to Vee
-
Output High Voltage Level
VOH
IOH= -400p.A
Output Low Voltage Level
VOL
IOL=2.1mA
Write Inhibit Vee Level
VWI
All 1I0's = OPEN
10
p.A
10
p.A
2.4
-
V
-
0.4
V
3.5
-
V
• Note 1. All addresses toggling from VIL to VIH at 5MHz
CAPACITANCE
(TA= 25·C, Vee=5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
InputlOutput Capacitance
ClIO
VIIO=OV
pF
CIN
VIN=OV
-
6
Input CapaCitance
10
pF
Note: CapaCitance is periodically sampled and not 100% tested ..
c8
SAMSUNG SEMICONDUCTOR
188
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
MODE SELECTION
CE
OE
WE
L
L
H
Read
DouT
Active
L
H
L
Write
D'N
Active
L
L
H
DATA·Polling
1/08=08
Active
H
X
X
Standby & Write Inhibit
High·Z
Standby
X
L
X
Write Inhibit
X
X
H
Write Inhibit
-
-
AC CHARACTERISTICS
Mode
1/0
Power
I
(TA=O·C to 70·C,V cc =5V±10%, unless otherwise noted).
TEST CONDITIONS
Parameter
Value
0.45 to 2.4V
Input Pulse Levels
Input Rise and Fall Times
20 ns
Input and Output Timing Levels
O.BV and 2.0V
Output Load
1 TTL Gate and CL = 100pF
READ CYCLE
Parameter
Read Cycle Time
Chip Enable Access Time
Address Access Time
Symbol
t RC
KM28C17·15
KM28C17·20
KM28C17·25
Min
Min
Min
Max
150
Max
200
Max
Unit
ns
250
tCE
150
200
250
ns
tM
150
200
250
ns
Output Enable Access Time
tOE
60
BO
100
ns
Chip Enable to Output in Low·Z
tcz
0
Chip Disable to Output in High·Z
tHZ
5
Output Enable to Output in Low·Z
tOLZ
5
Output Disable to Output in High·Z
tOHZ
5
Output Hold from Address Change
tOH
10
c8
SAMSUNG SEMICONDUCTOR
0
50
5
0
70
5
50
5
10
5
ns
90
ns
90
ns
5
70
5
10
ns
ns
189
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
WRITE CYCLE
Symbol
Parameter
Min
Max
Unit
twc
2
ms
tAS
0
ns
tAH
80
ns
Write Set·Up Time
tcs
0
ns
Write Hold Time
tCH
0
ns
Chip Enable to End of Write Input
tcw
100
ns
Output Enable Set·Up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width
twp
100
ns
Data Set·Up Time
tos
50
ns
Data Hold Time
tOH
10
Time to Device Busy
tOB
Write Cycle Time
Address Set·Up Time
Address Hold Time
Busy to Write Recovery Time
tBWR
50
Byte Load Cycle
tBlC
0.2
ns
100
ns
100
ps
ns
Note: The timer for tBlC is reset at a falling edge of WE and starts at a rising edge of WE.
TIMING DIAGRAMS
READ CYCLE WE = V1H
ADD
I-----IRC---,---j
- _. - -~ tAA ------
.-IOH
DOUT
c8
SAMSUNG SEMICONDUCTOR
VALID DATA
10HZ
VALID DATA
190
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
TIMING DIAGRAMS
(Continued)
WE CONTROLLED WRITE CYCLE
t------twc------i
ADD
I
Dour
~HIGH'Z ---------~----~)_--__t--
READY/BIlSV _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
...I....~
CE CONTROLLED WRITE
t - - - - - - twc-----j
ADD
tCH
WE
OE
tOEH IV 'V' " " " , , " , ' vvV"V'.IV'-'V
tOES
t----tcw - - - - I
CE
Dour
~HIGH'Z - - - - - - - - - t + - - - - - - ' I t ' - - - - - t - -
READY/"I!U§Y
-----------------,,1
tBWR
c8
SAMSUNG SEMICONDUCTOR
191
PRELIMINARY SPECIFICATION
CMOS EEPROM
KM28C17
TIMING DIAGRAMS
(Continued)
PAGE MODE WRITE (WE CONTROLLED WRITE CYCLE)
ADD
tOES
~~- ...;::}-
~
DATA
DINn
~ax=
"NOTE 1
READY/SUSV
------"-'----,L
tBWR
'-------H-----------'l~:r_
PAGE MODE WRITE (CE CONTROLLED WRITE CYCLE)
ADD
DATA
READY/BOSV _ _ _ _ _ _
"NOTE 1
--.J._~
t:J-
----------~~--------------~j
'NOTE 1. Tristate for 1/0,-1/07, DOUTn for II0a if the chip Is read. (See Dala.polling)
c8
SAMSUNG SEMICONDUCTOR
192
PRELIMINARY SPECIFICATION
KM28C17
CMOS EEPROM
DEVICE OPERATION
READ
Reading data from the KM28C17 is similar to reading
data from a SRAM. A read cycle occurs when WE is high
and CE and OE are low. If either CE or OE goes high
the read cycle is terminated. This two line control
eliminates bus contention in a system environment. The
Data 110 pins are in the high impedance state whenever
OE or CE is high.
WRITE
Writing data into the KM28C17 is very easy. Only a single 5V supply and TTL level signals are required. The
on-chip data latches, address latches, high voltage
generator, and fully self-timed control logic make writing as easy as' writing to a SRAM.
•••• BYTE WRITE MODE' •••
The byte write mode of the KM28C17 is only a part of
the page write mode. A single byte data loading followed
by a tSLC time·out and by a nonvolatile write cycle will
complete a byte mode write. In this mode, the write is
exactly identical to that of the KM2817A.
•••• PAGE WRITE MODE ••••
The KM28C17 allows up to 32 byte to be written in a
single page write cycle. A page write cycle consists of
a data loading period, in which from 1 to 32 byte data
are loaded into the KM28C17 internal registers and a
nonvolatile write period, in which the loaded data in the
registers are written to the EEPROM cells of the select·
ed page.
Data are loaded into the KM28C17 by sequentially pulsing WE with CE low and OE high. ON each WE, address
is latched on the falling edge of the WE and data is
latched on the rising edge of the WE. The data can be
loaded in any "Y" address order and can be renewed
in a data loading period.
Since the timer for the data loading period (tSLC) is reset
at the falling edge of WE and starts at every rising edge
of WE, the only requirement on WE to continue the data
loading is that the interval between WE pulses does not
exceed the maximum tSLC (1oo,.s). If OE goes Low during the data loading period, further attempt to load the
data will be ignored because the external WE signal is
blocked by OE signal internally. Consequently, the tSLC
timer is not reset by the external WE pulse if OE is low.
data latched at the register are written into the locations
during the program cycle. Note that only the addressed
location in a page are rewritten during a page write
cycle.
The KM28C17 also supports CE controlled write cycle.
That means CE can be used to latch address and data
as well as WE.
STANDBY
Power consumption is reduced to less than 100,.A~
deselecting the device with a high input on CE.
Whenever CE is high, the device is in the standby mode
and 1/0,-1I0a are in the high impedance state, regard·
less of the state of OE or WE.
DATA PROTECTION
Features have been designed into the KM28C17 that prevent unwanted write cycles during power supply transitions and system noise periods.
The KM28C17 has a protection feature against WE
noises: a WE noise the width shorter than 20ns (typ.)
will not start any unwanted write cycle.
Write cycles are also inhibited when Vcc is less than
VW1 3.5 volts, the Write Inhibits Vcc level.
During power-up, the KM28C17 automatically prevents
any write operation for a period of 2ms (typ.) after Vcc
reaches the VW1 level. This will provide the system with
sufficient time to bring WE and CE to a high level be·
fore a write can occur. Read cycles can be executed during this initialization period. Holding either 01: low or
WE high or CE high during power-on and power-off will
inhibit inadvertent writes.
=
DATA POLLING
The KM28C17 features DATA-Polling at I/0a to detect
the completion of a write cycle using a simple read and
compare operation. Such a scheme does not require any
external hardware: Reading the device at any time during a write operation will produce, at 1I0a, an inverted
value of last data loaded in to the EEPROM (110,-110 7
are at the high impedance state). True data will be
produced at alll/.)'s once the write cycle has been completed.
The page address for the nonvolatile write is the "X"
address (A5-A10) latched on the last WE. The nonvolatile write period consists of an erase cycle and a program cycle. During the erase cycle, the existing data
of the locations being addressed are erased. The new
c8
SAMSUNG SEMICONDUCTOR
193
•
PRELIMINARY SPECIFICATION
CMOS EEPROM
KM28C17
DEVICE OPERATION
READY/BUSY
ENDURANCE AND DATA RETENTION
The KM28C17 has a Ready/Busy output on pin 1 that
indicates when the write cycle is complete. The pin is
normally high except when a write cycle is in progress
in which case the pin is low.
The Ready/Busy output is configured as open-drain
driver there-by allowing two or more Ready/Busy out·
put to be OR-tied. This pin requires an appropriate pull·
up resistor for proper operation. The pull-up resistor
value maybe calculated as follows.
RP _ Vcdmax)-VOL(max) _
5.W
IOL+IL
- 2.1mA+k
where IL is the sum of the input currents of all devices
tied to the Ready/Busy pin.
KM28C17 is designed for applications requiring up to
10,000 write cycles per EEPROM byte and ten years of
data retention. This means that each byte may be reliably written 10,000 times without degrading device oper·
ation and that the data in the byte will remain valid after
its last write operation for ten years with or without power applied.
PACKAGE DIMENSIONS
28 LEAD PLASTIC DUAL IN LINE PACKAGE
Units: Inches (millimeters)
~o-~
~~
-1
~______________~1.4~65~(3~7.2~)______________
0.008 ( 0 . 2 0 i f
0.012 (0.30)
MAX
0.120 (3.05)
__-+--,-_. MIN
c8
SAMSUNG SEMICONDUCTOR
194
KM2864A1KM2864AH
NMOS EEPROM
BK x B Bit EEPROM with Latches and Auto-Write
GENERAL DESCRIPTION
FEATURES
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase-before-Write
- Automatic Write Timing
- DATA Polling and Verification
• Enhanced Write Protection
• Single 5 volt Supply
• Byte Write: 10ms (max)-KM2864A
2ms (max)-KM2864AH
• Fast Access Time: 200ns
• Power: SOmA-Standby (max)
120mA-Operating (max)
• Two Line Control-Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte-wide Memory Pinout
FUNCTIONAL BLOCK DIAGRAM
The KM2864A/AH is a 65,536 bit Electrically Erasable
and Programmable Read-Only-Memory organized as 8,192
words by 8-bits. Its data can be modified using simple
TTL level signals and a single 5 volt power supply.
Writing data into the KM2864A1AH is very simple. The
internally self-timed write cycle latches both address and
data to provide a free system bus during the write period
which is 10ms (max) for the KM2864A or 2ms (max) for
the KM2864AH.
The KM2864A/AH features DATA Polling, a software
scheme to detect the eariy completion of a write cycle
without requiring the use of any additional external
hardware. The KM2864A/AH is fabricated with the well
defined floating gate NMOS technology using FowlerNordheim tunneling for erasing and programming.
PIN CONFIGURATION
X Buffers Latches
and Decoder
65,536 Bit E'PROM
Memory Array
Y Buffers Latche,
and Decoder
1/0 Buffers
and Latches
Control Lagle
and Timing
Pin Name
~-A'2
110,-1/08
c8
SAMSUNG SEMICONDUCTOR
Pin Function
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
N.C.
No Connection
Vee
Power (+5V)
Vss
Ground
195
I
KM2864A1KM2864AH
NMOS EEPROM
ABSOLUTE MAXIMUM RATINGS·
Parameter
Voltage on any pin relative to Vss
Temperature Under Bias
Storage Temperature
Symbol
Rating
V'N
Tb,..
-1 to +6.0
V
-40 to +85
·C
-65 to +125
·C
5
mA
T" 9
los
Short Circuit Output Current
Units
"NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to Vss, TA = 0 to 70·C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
V'H
2.0
Vcc+ 0.3
V
Input Low Voltage
V'L
-1
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Symbol
Test Conditions
Min
Max
Units
Operating Current
Icc
CE=OE=V,L
All I/O's = OPEN
Other Inputs = Vee
-
120
mA
Standby Current
ISB
CE=V,H
All I/O's = OPEN
Other Inputs = Vcc
-
50
mA
Parameter
Input Leakage Current
III
V'N = 0 to 5.5V
/loA
ko
VQUT=O to 5.5V
-
10
Output Leakage Current
10
/loA
Output High Voltage Level
VOH
IOH= -400 /loA
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1 mA
-
0.4
V
Write Inhibit Vee Level
Vw,
3.5
-
V
CAPACITANCE
(TA=25·C, Vcc =5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Input/Output Capacitance
CliO
V'IO=OV
C'N
V'N=OV
Input Capacitance
Min
Max
Unit
-
10
pF
6
pF
Note: Capacitance is periodically sampled and not 100% tested.
c8
SAMSUNG SEMICONDUCTOR
196
NMOS EEPROM
KM2864A1KM2864AH
MODE SELECTION
CE
1/0
Power
Read
Dour
Active
Write
D'N
Active
High·Z
Standby
-
-
Mode
OE
WE
L
L
H
L
H
L
H
X
X
Standby and Write Inhibit
X
L
X
Write Inhibit
X
X
H
Write Inhibit
I
AC CHARACTERISTICS
(TA=O°C to 70°C, Vcc =5V±10%, unless otherwise noted.)
TEST'CONDITIONS
Value
Parameter
o to 3.0V
Input Pulse Levels
10 ns
Input Rise and Fall Times
Input and Output Timing Levels
1.5V
1 TIL Gate and C L = 100 pF
Output Load
READ CYCLE
Parameter
Symbol
KM2864A·20
KM2864AH·20
Min
Max
Min
Max
Min'
Unit
Max
Read Cycle Time
t AC
tCE
200
250
300
ns
Address Access Time
tAA
200
250
300
ns
Output Enable Access Time
tOE
150
ns
Chip Enable to Output in Low·Z
tLZ
10
Chip Disable to Output in High·Z
tHZ
10
Output Enable to Output in Low·Z
tOLZ
50
Output Disable to Output in High·Z
tOHZ
10
tOH
20
=8
SAMSUNG SEMICONDUCTOR
250
KM2864A·30
KM2864AH·30
Chip Enable Access Time
Output Hold from Address Change
200
KM2864A·25
KM2864AH·25
100
300
120
10
100
10
10
100
50
60
10
20
ns
10
ns
100
50
80
10
20
ns
ns
100
ns
ns
197
KM2864A1KM2864AH
NMOS EEPROM
WRITE CYCLE
Parameter
Write Cycle Time
I
I
Symbol
Min
KM2864A
KM2864AH
Max
10
twc
Units
ms
2
Address Set-up Time
tAS
10
Address Hold Time
tAH
120
ns
Write Set-up Time
tcs
0
ns
Write Hold Time
tCH
0
ns
ns
Chip Enable to End of Write Input
tew
150
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width
twp
150
ns
Data Latch Time
tOL
50
ns
Data Valid Time
1
tov
Data Set-up Time
tos
50
ns
Data Hold Time
tOH
10
ns
P.s
TIMING DIAGRAMS
READ CYCLE
WE=V1H
A
ADDRESS
ADDRESS
DOUT
c8
SAMSUNG SEMICONDUCTOR
198
KM2864A1KM2864AH
TIMING DIAGRAMS
NMOS EEPROM
(Continued)
WE CONTROLLED' WRITE CYCLE
I
Dour
~HIGH_Z--+-_ _ _-+------tl-~------tl--+---105
D,N ~XX)()()()()(XX:XiJ()()(W)()cOO'M
tOH---1
_
VALID DATA
'-------'
CE CONTROLLED WRITE CYCLE
A
IOES
I----Icw -----I
CE
Dour
~~--------~
r----riMT?~~~~--~
~HIGH-Z-+--------------+---------U---------t
-+--toS--t--tOH
VALID DATA
c8
SAMSUNG SEMICONDUCTOR
199
KM2864A1KM2864AH
NMOS EEPROM
DEVICE OPERATION
Read
Reading data from the KM2864A/AH is similar to
reading data from a static RAM. A reading cycle occurs
when WE is high and both CE and Oi:: are low. If either
CE orM goes high,lhe read cycle is terminated. This
two line control eliminates bus contention in a system
environment. The Data 1/0 pins are in the high im·
pedance state whenever OE or CE is high.
Write
Writing Data into the KM2864A/AH is very easy.
Only a single 5V supply and TTL level signals are reo
quired. The on-chip data latches, address latches, high
voltage generator, and fully self·timed control logic
make writing as easy as writing to a static RAM.
A write cycle occurs when OE is high and both CE and
WE are low. The address is latched by the falling edge
of CE or WE, whichever occurs last. The data is latched
by the rising edge of CE or WE, whichever occurs first.
Address and data are conveniently latched in less than
200ns during a write operation. Once a byte write cycle
is initiated,it will automatically continue to completion
within 10ms (max) for the KM~864A or 2ms (max) for the
KM2864AH. The existing data at the selected address
is automatically erased and the new data is auto·
matically written.
Standby
Power consumption may be reduced about 60% by
deselecting the device with a high input on CEo
Whenever CE is high, the device is in the standby mode
and 1/0 1 -I/Oa are in the high impedance state,
regardless of the state of OE or WE.
Data Protection
Features have been designed into the KM2864A/AH that
prevent unwanted write cycles during power supply
transitions and system noise periods.
ciS
SAMSUNG SEMICONDUCTOR
Write cycles are Inhibited when Vee is less than
VW1 = 3.5 volts, the Write Inhibit Vee level.
During power·up the KM2864A/AH automatically
prevents any write operaion for a period of 9ms for the
KM2864A or 2ms for the KM2864AH after Vee reaches
the VW1 level. This will provide the system with
sufficient time to bring WE or CE to a high level before
a write can occur. Read cycles can be executed during
this initialization period.
Holding either OE low or WE high or CE high during
power·on and power·off will inhibit inadvertent writes.
Data Polling
The KM2864A/AH features DATA Polling to detect the
completion of a write cycle using a simple read and
compare operation. Such a scheme does not required
any external hardware. During a write cycle the most
significant bit of the byte written to the KM2864A/AH
is inverted and routed to the output buffer. The 1/0 pins,
1/01.1/07 , remain in a high impedance state until a read
command is initiated. Reading the device during the
write operation will produce this inverted bit at I/0 a
(1/0 1.1/07 are indeterminate). True data will be produced
at I/0a once the write cycle has been completed.
Endurance and Data Retention
The KM2864A/AH is designed for applications requiring,
up to 10,000 write cycles per E2PROM byte and ten
years of data retention. This means that each byte may
be reliably written 10,000 times without degrading device
operation, and that the data in the byte will remain valid
after its last rewrite operation for ten years with or
without power applied.
200
KM2864A1KM2864AH
NMOS EEPROM
PACKAGE DIMENSIONS
Units: Inches (millimeters)
28 LEAD PLASTIC DUAL IN LINE PACKAGE
--,~0-15"
I
€f
+----t+__~ ~
ill ::;;
ci
:=+
1.465 (37.2)
~------------~MA~X~------------~
0.008 (0.20)
0.012 (0.30)
(--,---rnO'"'.120 (3.05)
__+--,--_MIN
0.020 (0.51)
MIN
TYP
TYP
c8
SAMSUNG SEMICONDUCTOR
201
NMOS EEPROM
KM2865A1KM2865AH
BK x B Bit EEPROM with Latches and Auto-Write
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Fast Byte Write Time
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase·before·Write
- Automatic Write Timing
- DATA Polling and Verification
- Ready/Busy Output Pin
• Enhanced Write Protection
• Single 5 volt Supply
• Byte Write: 10ms (max)-KM2865A
2ms (max)-KM2865AH
• Fast Access Time: 200ns
• Power: 50mA-Standby (max)
120mA-Operatlng (max)
• Two Line Control·Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte·wide Memory Pinout
FUNCTIONAL BLOCK DIAGRAM
The KM2865A/AH is a 65,536 bit Electrically Erasable
and Programmable Read·Only·Memory organized as 8,192
words by 8·bits. Its data can be modified using simple
TTL level signals and a single 5 volt power supply.
Writing data into the K1Ii'I2865A/AH is very simple. The
internally self·timed write cycle latches both address and
data to provide a free system bus during the write period
which is 10ms (max) for the KM2865A or 2ms (max) for
the KM2865AH .
The KM2865A/AH features two end of write detection
schemes to provide maximum design flexibility while
enhancing the system performance. DATA Polling is a
software scheme to detect the early completion of a write
cycle without using any additional hardware. Ready/Busy
is a hardware scheme in which Pin 1 is used to signal
the status of the write operation and is especially useful
in interrupt driven systems.
The KM2865A/AH is fabricated with the well defined
floating gate NMOS technology using Fowler·Nordheim
tunneling for erasing and programming.
PIN CONFIGURATION
X
Buffers
Latches
and
65,536 Bit
E'PROM
Decoder
Y
Buffers
Latches
and
Decoder
Memory
Array
110 Buffers
Pin Name
Control
Logic and
Ac·A'2
Timing
RDYIBSY
1I0,-IIOs
CE
SAMSUNG SEMICONDUCTOR
Data Inputs/Outputs
Chip Enable
OE
Output Enable
WE
Write Enable
RDY/BSY
c8
Pin Function
Address Inputs
Ready/Busy Output
N.C.
No Connection
Vee
Power (+5V)
Vss
Ground
202
NMOS EEPROM
KM2865A1KM2865AH
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Rating
Y'N
Tbias
-1 to +6.0
V
Temperature Under Bias
-40 to +85
·C
Storage Temperature
T.'g
-65 to + 125
·C
IShort Circuit Output Current
los
5
mA
Voltage on any pin relative to Vss
Units
'NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to Vss, TA=O to 70·C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
V,H
2.0
-
Vee +0.3
V
Input Low Voltage
V,L
-1
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Symbol
Test Conditions
Min
Max
Units
Operating Current
Icc
CE=OE=V,L
All 1I0's = OPEN
Other Inputs = Vee
-
120
mA
Standby Current
ISB
CE=V,H
All 1I0's = OPEN
Other Inputs = Vee
-
50
mA
Parameter
Input Leakage Current
III
Y'N = 0 to 5.5V
pA
ILO
VOUT = 0 to 5.5V
-
10
Output Leakage Current
10
/LA
Output High Voltage Level
VOH
10H = -400 /LA
2.4
-
V
Output Low Voltage Level
VOL
IOL=2.1 mA
-
0.4
V
Write Inhibit Vee Level
VWI
3.5
-
V
Unit
CAPACITANCE
(TA=25·C, Vee =5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Input/Output Capacitance
CliO
VIIO=OV
pF
C'N
V,N=OV
-
10
Input Capacitance
6
pF
Note: Capacitance is periodically sampled and not 100% tested.
c8
SAMSUNG SEMICONDUCTOR
203
I
NMOS EEPROM
KM2865A1KM2865AH
MODE SELECTION
CE
OE
WE
L
L
H
L
H
L
H
X
X
Standby and Write Inhibit
1/0
Power
Read
Dour
Active
Write
DIN
Active
High-Z
Standby
-
-
Mode
X
L
X
Write Inhibit
X
X
H
Write Inhibit
AC CHARACTERISTICS
(TA=O·C to 70·C, Vcc =5V± 10%, unless otherwise noted.)
TEST CONDITIONS
Value
Parameter
o to 3.0V
Input Pulse Levels
Input Rise and Fall Times
10 ns
1.5V
Input and Output Timing Levels
Output Load
1 TIL Gate and CL = 100 pF
READ CYCLE
Parameter
Symbol
KM2865A-20
KM2865AH·20
Min
Read Cycle Time
tRC
Max
200
KM2865A·25
KM2865AH·25
Min
Max
250
KM2865A·30
KM2865AH·30
Min
Unit
Max
ns
300
Chip Enable Access Time
tCE
200
Address Access Time
tAA
200
250
300
ns
Output Enable Access Time
tOE
100
120
150
ns
Chip Enable to Output in Low-Z
tLZ
10
Chip Disable to Output in High-Z
tHZ
10
100
ns
Output Enable to Output in Low-Z
tOLZ
50
tOHZ
10
Output Disable to Output in High-Z
Output Hold from Address Change
c8
tOH
SAMSUNG SEMICONDUCTOR
20
250
300
ns
10
100
10
10
100
50
60
10
20
10
ns
50
80
10
20
ns
100
ns
ns
204
KM2865A1KM2865AH
NMOS EEPROM
WRITE CYCLE
Parameter
Write Cycle Time
Symbol
l
KM2865A
I
KM2865AH
Min
Max
Units
10
twc
ms
2
Address Set-up Time
tAS
10
ns
Address Hold Time
tAH
120
ns
Write Set-up Time
tcs
0
ns
Write Hold Time
tCH
0
ns
Chip Enable to End of Write Input
tew
150
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width
twp
150
ns
Data Latch Time
tOL
50
Data Valid Time
tov
Data Set-up Time
tos
50
10
Data Hold Time
tOH
Time to Device Busy
toe
Busy to Write Recovery Time
tewR
•
ns
1
P.s
ns
ns
120
ns
ns
50
TIMING DIAGRAMS
READ CYCLE
WE=V1H
A
ADDRESS
ADDRESS
i------IRC-----i
ICE
IOE
IOLZ
DOUT
c8
SAMSUNG SEMICONDUCTOR
IOH
VALID DATA
10HZ
VALID DATA
205
KM2865A1KM2865AH
TIMING DIAGRAMS
NMOS EEPROM
(Continued)
WE CONTROLLED WRITE CYCLE
A
ADDRESS
---j---tAH
tcs
tOES
r----twP---WE
Dour
~~--------~
r----~~~~~~r-~
~HIGH.Z---1---------+-----..H-----+--;--tDS--!--tDH
D,N AIVvV'.rv'"""V\,rvvvv,,,,
VALID DATA
tDe
RDY/BSY
----------------t--,
CE CONTROLLED WRITE CYCLE
r----------twc-------,----!
A
ADDRESS
---t---tAH
tcs
tCH
Dour ~HIGH.Z-+--------+-----..H------rtDv _--+-_tDS_-!-_tDH
tDe
RDY/BSY
=8
---------------+-,
SAMSUNG SEMICONDUCTOR
tewR
206
KM2865A1KM2865AH
NMOS EEPROM
DEVICE OPERATION
Read
Reading data from the KM2865A/AH is similar to
reading data from a static RAM. A reading cycle occurs
when WE is high and both CE and OE are low. If either
CE or OE goes high,the read cycle is terminated. This
two line control eliminates bus contention in a system
environment. The Data 110 pins are in the high impedance state whenever OE or CE is high.
Write
Writing Data into the KM2865A/AH is very easy. Only
a single 5V supply and TTL level Signals are required.
The on-chip data latches, address latches, high voltage
generator, and fully self-timed control logic make writing
as easy as writing to a static RAM.
_
A write cycle occurs when OE is high and both CE and
WE are low. The address is latched by the falling edge
of CE or WE, whichever occurs last. The data is latched
by the rising edge of CE or WE, whichever occurs first.
Address and data are conveniently latched in less than
200ns during a write operation. Once a byte write cycle
is initiated it will automatically continue to completion
within 10ms (max) for the KM2865A or 2ms (max) for the
KM2865AH. The existing data at the selected address
is automatically erased and the new data is automatically written.
Standby
Power consumption may be reduced about 60% ~
deselecting the device with a high input on CE.
Whenever CE is high, the device is in the standby mode
and 110, -I/Oa are in the high impedance state,
regardless of the state of OE or WE.
Data Protection
Features have been designed into the KM2865A/AH that
prevent unwanted write cycles during power supply
transitions and system noise periods.
Write cycles are inhibited when Vee is less than
VW1 = 3.5 volts, the Write Inhibit Vee level.
During power-up the KM2865A/AH automatically
prevents any write operaion for a period of 9ms for the
KM2865A or 2ms for the KM2865AH after Vee reaches
..
eSC SAMSUNG SEMICONDUCTOR
the VW1 level. This will provide the system with
sufficient time to bring WE or CE to a high level before
a write can occur. Read cycles can be executed during
this initialization period.
Holding either OE low or WE high or CE high during
power-on and power-off will inhibit inadvertent writes.
Data Polling
The KM2865A/AH features DATA Polling to detect the
completion of a write cycle using a simple read and
compare operation. Such a scheme does not required
any external hardware. During a write cycle the most
significant bit of the byte written to the KM2865A/AH
is inverted and routed to the output buffer. The 110 pins,
1/0,-1107, remain in a high impedance state until a read
command is initiated. Reading the device during the
write operation will produce this inverted bit at II0a
(110,-1107 are indeterminate). True data will be produced
at II0a once the write cycle has been completed.
Ready/Busy
The KM2865AH has a ReadylBusy output pin that indicates when the write cycle is complete. The pin is normally high except when a write cycle is in progress, in
which case the pin is low.
The ReadylBusy output is configured as open-drain
driver there-by allowing two or more Ready/Busy output to be or-tied. This pin requires an appropriate pullup register for proper operation. The pull-up resistor
value for the ReadylBusy output maybe calculated as
follows:
R _ Vee (MAX) - VOL (MAX) _
5.1V
p 10L + IL
- 2.1mA + IL
Where IL is the sum of the input currents of all devices
tied to the ReadylBusy pin.
Endurance and Data Retention
The KM2865A/AH is designed for applications requiring, up to 10,000 write cycles per E2PROM byte and
ten years of data retention. This means that each byte
may be reliably written 10,000 times without degrading
device operation, and that the data in the byte will remain valid after its last rewrite operation for ten years
with or without power applied.
207
I
KM2865A1KM2865AH
NMOS EEPROM
PACKAGE DIMENSIONS
Units: Inches (millimeters)
28 LEAD PLASTIC DUAL IN LINE PACKAGE
6'
-+---t+-t ~
:il ::;;
o
~
(0.20~
1.465 (37.2)
MAX
0.008
0.012 (0.30)
-'---''''0=.120 (3.05)
v_-+--L_MIN
MIN
c8
SAMSUNG SEMICONDUCTOR
208
CMOS EEPROM
KM28C64IKM28C65
BK x B Bit CMOS EEPROM
FEATURES
GENERAL DESCRIPTION
• Simple Byte Write
- Single TTL Level Write Signal
- Latched Address and Data
- Automatic Internal Erase-before-Wrlte
- Automatic Write Timing
- ~ Polling and Verification
- Ready/Busy Output Pin (KM28C65)
• 32-byte page write: 5ms max
- Effective 150,.sJbyte write
• Enhanced Write Protection
• Single 5 volt Supply
• Fast Access Time: 200ns
• Power: 100 ,.A - Standby (max)
30 mA - Operating (max)
• Two Line Control-Eliminates Bus Contention
• 10,000 Cycle Endurance
• JEDEC Byte-wide Memory Pinout
The KM28C64/C65 is a 65,536 bit electrically erasable and programmable Read-Only-Memory. Its data
can be modified using simple TTL level signals and
a single 5 volt power supply.
Writing data into the KM28C641C65 is very simple. The
internally self-timed write cycle latches both address
and data to provide a free system bus during the 5ms
(max) write period.
A 32-byte page write enables an entire chip written
in 1.3 second.
The KM28C64/C65 features DATA-polling, which
enables the EEPROM to signal the processor that a
write operation is complete without requiring the use
of any external hardware. Ready/Busy is a hardware
scheme in which Pin 1 is used to signal the status of
the write operation and is especially useful in interrupt driven systems.
The KM28C64/C65 is fabricated with the well defined
floating gate CMOS technology using FowlerNordheim tunneling for erasing and programming.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
N.C. or
RDY/BSY
A12 2
A7 3
Page Buffers
X Buffers
Latches
and
Decoder
Y Buffers
Latches
and
Decoder
65,536 Bit
E'PROM
Memory
Array
I/O Buffers
and Latches
Control Logic
and Timing
Pin Name
RDY/BSV
Ao-A12
1/01-1/08
Chip Enable
OE
Output Enable
WE
Write Enable
N.C.
SAMSUNG SEMICONDUCTOR
Data Inputs/Outputs
CE
RDY/BSY
c8
Pin Function
Address Inputs
Ready/Busy Output
No Connection
Vee
+5V
Vss
Ground
209
I
CMOS EEPROM
KM28C64/KM28C65
ABSOLUTE MAXIMUM RATINGS·
Symbol
Rating
Units
Value
Voltage on any Pin Relative to Vss
VIN
-0.3 to 7.0
V
Temperature Under Bias
Tblas
-10to+85
°C
Storage Temperature
T.tg
-65 to +125
°C
Short Circuit Output Current
los
5
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to Vss, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Vee
4.5
5.0
5.5
V
Vss
0
0
0
V
-
Vee+0.3
V
0.8
V
Supply Voltage
Supply Voltage
Input High Voltage, Inputs
VIH
2.0
Input Low Voltage, all Inputs
VIL
-0.3
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Max
Units
Operating Current
Icc
CE = OE = VIL, WE = VIH
aill/O's=open
all addresses' (NOTE 1)
30
mA
Standby Current (TTL)
IS8t
CE=VIH
all I/O's = open
1
mA
Standby Current (CMOS)
IS82
CE=Vee-0.2V
all I/O's = open
100
p.A
Input Leakage Current
III
VIN=O to Vee
10
p.A
Output Leakage Current
ILO
Vln=O to Vee
10
p.A
Output High Voltage Level
VOH
10H= -400p.A
Output Low Voltage Level
VOL
IOL=2.1mA
Write Inhibit Vee Level
VWL
2.4
V
0.4
3.5
V
V
• Note 1. All addresses toggling from VIL to VIH at 5MHz
ciS
SAMSUNG SEMICONDUCTOR
210
KM28C64/KM28C65
CAPACITANCE
CMOS EEPROM
(TA=25·C, Vee =5V, f=1.0 MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
InputlOutput Capacitance
CliO
VIIO=OV
-
B
pF
Input Capacitance
CIN
VIN=OV
-
B
pF
Note: Capacitance is periodically sampled and not 100% tested.
I
MODE SELECTION
CE
OE
WE
Mode
1/0
Power
Active
L
L
H
Read
DouT
L
H
L
Write
DIN
H
X
X
Standby & Write Inhibit
High-Z
Standby
I/0s = Os
Active
Active
L
L
H
Data-Polling
X
L
X
Write Inhibit
-
-
X
X
HI
Write Inhibit
-
-
AC CHARACTERISTICS
(TA = o·c to 70·C, Vee = 5V ± 10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
20 ns
Input and Output Timing Levels
O.BV and 2.0V
Output Load
1 TTL Gate and CL = 100 pF
READ CYCLE
Parameter
Symbol
KM28C64-20
KM28C65-20
Min
Max
KM28C64-25
KM28C65-25
Min
Units
Max
Read Cycle Time
tRc
Chip Enable Access Time
teE
200
250
ns
Address Access Time
tAA
100
ns
Output Enable Access Time
tOE
BO
BO
100
ns
Chip Enable to Output in Low-Z
tLZ
0
Chip Disable to Output in High-Z
tHZ
5
Output Enable to Output in Low-Z
tOLZ
5
Output Disable to Output in High-Z
tOHZ
5
Output Hold from Address Change
tOH
10
ciS
SAMSUNG SEMICONDUCTOR
200
250
ns
0
70
5
ns
90
5
70
5
10
ns
ns
90
ns
ns
211
KM28C64/KM28C65
CMOS EEPROM
WRITE CYCLE
Symbol
Min
Write Cycle Time
twc
Address Set-Up Time
tAs
5
0
80
0
0
100
10
10
100
50
10
Parameter
Address Hold Time
tAH
Write Set-Up Time
tcs
Write Hold Time
tCH
Chip Enable to End of Write Input
tew
Output Enable Set-Up Time
tOES
Output Enable Hold Time
tOEH
Write Pulse Width
twp
Data Set-Up Time
tos
Data Hold Time
tOH
Time to Device Busy
tOB
Busy to Write Recovery Time
tBWA
Byte Load Cycle
tBlC
50
0.2
Max
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
ns
30
,.s
ns
Note: The timer for tBlC is reset at a falling edge of WE and start at a rising edge of WE.
TIMING DIAGRAMS
READ CYCLE WE =V1H
A
f-----IAC-----i
IOE
lOll
DOUT
c8
i----IAA-----i
10HZ
IOH
VALID DATA
SAMSUNG SEMICONDUCTOR
VALID DATA
212
CMOS EEPROM
KM28C64IKM28C65
TIMING DIAGRAMS
(Continued)
WE CONTROLLED WRITE CYCLE
twc
A
tAH
tAS
tcs
tCH
CE
I
DE
tOES.
twp
WE
Dour
D-HIGH-Z
tDS
D,N
RDY/BSY
CE CONTROLLED WRITE CYCLE
twc
A
tAH
tAS
tcs
tCH
WE
DE
tOEH
tOEs
tcw
CE
Dour
D-HIGH-Z
D,N
RDY/BSY
c8
SAMSUNG SEMICONDUCTOR
213
KM28C64IKM28C65
CMOS EEPROM
TIMING DIAGRAMS (Continued)
PAGE MODE WRITE (WE CONTROLLED WRITE CYCLE)
ADD
i-----1 t WC - - - - /
~
DATA
"NOTE 1. tBWR--iJ==.
RDY/BSY
~--------~H
PAGE MODE WRITE
(CE
I~
CONTROLLED WRITE CYCLE)
ADD
DATA
RDY/BSY
'Note 1. Tristate for 1/0,-1/07, Dou,n for II0 a if the chip is read (see Dafii-polling)
c8
SAMSUNG SEMICONDUCTOR
214
KM28C64/KM28C65
CMOS EEPROM
DEVICE OPERATION
Read
Reading data from the KM28C64/C65 is similar to
reading data from a SRAM. A read cycle occurs when
WE is high and CE and OE are low. If either CE or OE
goes high the read cycle is terminated. This two line
control eliminates bus contention in a system environment. The Data 110 pins are in the high impedance state
whenever OE or CE is high.
Write
Writing data into the KM28C64/C65 is very easy.
Only a single 5V supply and TIL level signals are required. The on-chip data latches, address latches, high
voltage generator and fully self-timed control logic make
writing as easy as writing to a SRAM.
* * * * BYTE WRITE MODE * * * *
The byte write mode of the KM28C64/C65 is only a
part of the page write mode. A single byte data loading
followed by a tBLe time out and by a write cycle will
complete a byte mode write. In this mode, the write is
exactly identical to that of the KM2864A/65A.
** •• PAGE WRITE MODE ••••
The KM28C64/C65 allows up to 32 bytes to be written
in a single page write cycle. A page write cycle consists
of a data loading period, in which from 1 to 32 bytes data
are loaded into the KM28C64/C65 internal registers and
a write period, in which the loaded datas in the registers
are written to the EEPROM cells of the selected page.
Data are loaded into the KM28C64/C65 by sequentially
pulsing WE with CE LOW and OE HIGH. On each WE,
address is latched on the falling edge of the WE and
data is latched on the rising edge of th'e WE. The data
can be loaded.in any "Y" address order and can be
renewed in the data loading period.
Since the timer for the data loading period (tBLd is
reset at the falling edge of WE and starts at every
rising edge of WE, the only requirement on WE to continue the data loading is that the interval between WE
pulses does not exceed the maximum tBLC (30I-'s). If OE
goes LOW during the data loading period, further attempt to load the data will be ignored because the external WE signal is blocked by OE signal internally,
Consequently, the tBLe timer is not reset by the
external WE pulse if OE is LOW.
The page address for the write is the "X" address
(A5-A12) latched on the last WE. The write period consists of an erase cycle followed by a program cycle.
During the erase cycle the existing data of the locations
being addressed are erased. The new data latched at
c8
SAMSUNG SEMICONDUCTOR
the registers are written into the locations during the
program cycle. Note that only the addressed locations
in a page are rewritten during a page write cycle.
The KM28C64/C65 also supports CE controlled write
cycle. That means CE can be used to latch address and
data as well as WE.
Standby
Power consumption may be reduced to less than
100l-'A by deselecting the device with a high input on
CE. Whenever CE is high, the device is in the standby
mode and 1I0,-IIOa are in the high impedance state,
regardless of the state of OE or WE.
Data Protection
Features have been designed into the KM28C64/C65
that prevent unwanted write cycles during power supply
transitions and system noise periods.
The KM28C64/C65 has an protection feature against
WE noises, a WE noise having width shorter than 20ns
(typ.) will not start any unwanted write cycle.
Write cycles are also inhibited when Vee is less than
VW1 = 3.5 volts, the Write Inhibits Vee level.
During power-up, the KM28C64/C65 automatically
prevents any write operation for a period of 5ms (max.)
after Vee reaches the VW1 level. This will provide the
system with sufficient time to bring WE and CE to a high
level before a write can occur. Read cycles can be executed during this initialization period,
Holding either OE low or WE high or CE high during
power-On and power-Off will inhibit inadvertent writes,
Data Polling
The KM28C64/C65 features DATA-Polling at 1I0 a to
detect the completion of a write cycle using a simple
read and compare operation. Such a scheme does not
require any external hardware, Reading the device at any
time during a write operation will produce, at 1I0a an inverted value of Last data loaded into the EEPROM
(110,-110 7 are at the high impedance state). True data
will be produced at 1I0a once the write cycle has
been completed,
Ready/Busy
The KM28C65 has a Ready/Busy output on pin 1 that
indicates when the write cycle is complete. The
pin is normally high except when a write cycle is in
progress, in which case the pin is low.
215
•
KM28C64IKM28C65
DEVICE OPERAliON
CMOS EEPROM
(Continued)
The Read/Busy output 'is configured as open-draln
driver there-by allowing two or more Ready/Busy output to be OR-tied. This pin requires an appropriate pullup resistor for proper operation. The pull-up resistor
value maybe calculated as follows
Rp - Vcc(max)-VoL!maxL
5.1V
IOL + IL
2.1mA+ IL
where IL Is the sum of the input currents of all devices
tied to the Ready/Busy pin.
Endurance and Data Retention
The KM28C641C65 is designed for applications requiring up to 10,000 write cycles per EEPROM byte and ten
years of data retention. This means that each byte may
be reliably written 10,000 times without degrading device
operation and that the data in the byte will remain valid
after its last write operation for ten years with or without
power applied.
PACKAGE DIMENSIONS
28 LEAD PLASTIC DUAL IN LINE PACKAGE
~O-15.
S
-t-----tt-
t:8
o
~
::E
~
1.465 (37.2)
MAX
0.008(0.20
0.012 (0.30)
(----,---,,0"'.120 (3.05)
~
v_-+---'-_
TYP
c8
SAMSUNG SEMICONDUCTOR
MIN
216
ADVANCEDINFORMAnON
KM28C256
CMOS EEPROM
256K CMOS EEPROM
FEATURES
DESCRIPTION
• High Performance Advanced CMOS Technology
• 150 nsec maximum Access Time
• Low Power
- 100"A Standby Current
-60mA Active Current
• Fast Write Cycle times
-Byte or Page Write Cycle: 5ms Typical
-64·Byte Page Write
-Effective 80"sec/Byte Write
-Complete Memory Rewite: 2.5 sec
• Write Cycle Completion Indication
-Data Polling
-Toggle bit
• Enhanced Write Protection
-Software Write Protection
- Hardware Write Protection
-Programmable Write Inhibit Vee Level
• High Endurance
-10,000 Cycle Endurance/Byte
-10 Year Data Retention
• JEDEC Approved Byte·wlde Pinout
The KM28C256 is a CMOS 5V Only 32K x 8 Electrically Erasable Programmable Read Only Memory. It is
fabricated with the well defined floating gate CMOS
technology using Fowler-Nordheim tunnelling for erasing and programming_
The KM28C256 provides easy of use features: The in·
temally self-timed write cycle latches both address and
data to give a free system bus during the 5ms(max) write
period. A 64·byte page write enables an entire chip writ·
ten in less than 2_5 seconds. The data polling scheme
enables the EEPROM to signal the processor that a write
operation is complete without requiring the use of any
external hardware.
The KM28C256 is designed for applications up to
10,000 write cycles per byte and over 10 years of data
retention_ The chip, however, endures typically 50,000
write cycles per byte without any failure_
PIN CONFIGURATION
vee
FUNCTIONAL BLOCK DIAGRAM
WE
X
,Ao-AI4
As
Buffers
Latches
and
Decoder
256K Bit
EEPROM
Array
ECC Circuitry
V
)
~
wE-
1107
Buffers
Latches
110 Buffers
and
Decoder
[
cE oE -
and Latches
f-
I
1100-1107
I
PIN NAMES
Ao-A'4
Logic &
1100-1107
Timing
SAMSUNG SEMICONDUCTOR
Pin Function
Pin Name
Control
vceVss-
c8
A'3
Page Buffers
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
Vee
+5V
Vss
Ground
217
I
NOTES
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
1. U.S.A
SALES OFFICES
CALIFORNIA
201 East Sandpoint
Suite 220 Santa Ana 92707
714-662·3406
2700 Augustine Drive
Suite 198 Santa Clara 95054
408-727·7433
ILLINOIS
901 Warrenville Rd.
Suite 120 Usle, 60532-1359
312-852·2011
TEXAS
1 5851 Dallas Parkway
Suite 745
Dallas 75248-3307
214-239·0754
MASSACHUSETTS
NORTH CAROLINA
20 Burlington Mall Road
SUite 205 Burlington 01803
617·273·4888
3200 Nothline Ave
Suite 501G
Forum VI Greensboro, 27408
919-294-5141
MANUFACTURER'S REPRESENTATIVES
ALABAMA
COLORADO
EMA
ELECTRODYNE
1200 Jordan Lane, Suite 4
Jordan Center
Huntsville 35805
205-536-3044
2620 S. Parker Road
Suite 11 0 Aurora 8001 4
303-695-8903
ARIZONA
CONNECTICUT
HAAS & ASSOC., INC.
PHOENIX SALES
7505 East Main
Suite 300
Scottsdale 85252
602·994·3813
257 Main Street
Torrington, 06790
203-476-7709
CALIFORNIA
SYN PAC
3945 Freedom Circle Suite 650
Santa Clara 95054
408-988·6988
WESTAR REP COMPANY
1801 Parkcourt Place
Suite 103D Santa Ana 92701
714-835·4711
QUEST-REP, INC.
San Diego, CA.
619-546-1933
CANADA
TERRIER ELECTRONICS
1 45 The West Mall
Etobicoke, Ontario M9C 1C2
416-622-7558
c8
SAMSUNG SEMICONDUCTOR
GEORGIA
EMA
6695 Peachtree Industrial Boulevard
Suite 101 Atlanta 30360
404·448-1 21 5
FLORIDA
MICRO ELECTRONIC COMPONENTS
989 Woodgade Dr
Palm Harbor, 33563
813-784-8561
ILLINOIS
IRI
8430 Gross Pointe Road
Skokie 60076
312-967-8430
I
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
INDIANA
OHIO
STB & ASSOCIATES
J.N. BAILEY & ASSOCIATES
3003 E. 96th Street
Suite 102 Indianapolis 46240
317-844-9227
13071 Old Dayton Road
New Lebanon 45345
51>3-687-1325
1667 Devonshire Drive
Brunswick'44212
216-273-3798
2679 Indianola Avenue
Columbus 43202
614-262-7274
MICHIGAN
C.B. JENSEN & ASSOC.
21 45 Crooks Road
Troy 48084
313-643-0506
MARYLAND
ADVANCED TECHNOLOGY SALES
809 Hammonds Ferry
Lithicum 21 090
301-789-9360
MASSACHUSETTS
Contact local sales, office
MINNESOTA
COMSTRAND INC
2852 Anthong Lane South
Minneapolis, 55418
612-788-9234
NEW JERSEY
NECCO
2460 Lemoine Avenue
Ft. Lee 07024
20'1-4611-2789
PENNSYLVANIA
RIVCO JANUARY, INC.
78 South Trooper Road
Norristown 1 9403
215-631-1414
SOUTH CAROLINA
EMA
210 W. Stone Avenue,
Greenville, 29609
803-233-4637
TEXAS
VIELOCK ASSOCIATES
720 E. Park Boulevard
Suite 102 Plano 75074
214-881-1940
UTAH
NEW MEXICO
ELECTRODYNE
Contact local sales office
2480 South Main Street
Suite 109 Salt Lake City 8411 5
801-486-3801
NORTH CAROLINA
Contact local sales office
WISCONSIN
OREGON
IRI
EARL & BROWN
631 Mayfair
Milwaukee 53226
414-259-0965
7719 S. W. Capitol Highway
Portland 97219
503-245-2283
WASHINGTON
NEW YORK
EARL & BROWN
NECCO
2447-A 152nd Avenue, N.E.
Redmond 98052
206-885-5064
2460 Lemoine Avenue
Ft. Lee 07024
201-4611-2789
c8
SAMSUNG SEMICONDUCTOR
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
2. EUROPE
W/GERMANY
BYTECH LTD
SILCOM ELEKTRONICS
2 The Western centre,
Western Road.
Bracknell Berkshire RG12 lRW.
Tel: Sales 0344 482211,
Accounts/Admin, 0344 424222
Tlx: 848215
Neusser Str. 336·338
0·4050 Muchengladbach
Tel: (02161) 60752
Tlx: 852189
MICRONETICS VERTRIEB8GESELLSCHAFT ELEKTRONISCHER
BAUELEMENTE and SYSTEME GmbH
Weil der Stadter StraBe 45
7253 Renningen 1
Tel: (07159) 6019
Tlx: 724708
RAPID SILICON
Rapid House Denmrak Street
High Wycombe Buckinghamshire HP 11 2 ER
Tel: 0494 26271;
Sales hot line; 0494 442266
Tlx: 837931
Fax: 0494 21860
STEATITE ELECTRONICS LTD.
ING. THEO HENSKES GmbH
Laatzener Str. 1 9
Postfach 721226
30000 Hannover 72
Tel: (0511) 865075
Tlx: 923509
Fax: 876004
ZEPHYR HOUSE WARING STREET.
WEST NORWOOD LONDON SE279 LH
Tel: (01) 670·8663
Tlx: 892425
HAGLEY HOUSE HAGLEY ROAD
EDGBASTON BIRMINGHAM B1680W
Tel: (021) 454·2655
Tlx: 337046
ASTRONIC GmbH
SWEDEN
Winzerer Str. 47 d
8000 Munchen 40
Tel: (089) 309031
Tlx: 521687
Fax: (089) 3006001
NOR DISK ELEKTRONIK AB
FRANCE
ASIAMOS
Batiment EVOLIC 1
155, Boulevard de Valmy
92705 Colombes, France
Tel: (1) 47601255
Tlx: 613890F
Fax: (1) 47601582
Huvudstagatan 1 Box 1409
5·17127 Solna
Tel: (08) 7349770
Tlx: 10547
Fax: (08) 272204
SWITZERLAND
PANATEL AG
HardstraBe 7 2
CH·5430 Wettingen Zurich
Tel: (056) 275275
Tlx: 58068
Fax: (056) 271924
FINLAND
UNITED KINGDOM
INSTRUMENTARIUM ELEKTRONIIKKA
KORD DISTRIBUTION LTD.
P.O. Box 64, Vitikka
SF·02631 Espoo, Helsinki
Finland
Tel: (358) 05284320
Tlx: 124426
Fax: (358) 0524986
Watchmoor Road, Camberley
Surrey GU 1 53AO
Tel: 0276 685741
Tlx: 859919 KORDIS G.
cis
SAMSUNG SEMICONDUCTOR
I
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
AUSTRIA
ITALY
ABRAHAMCZIK + DEMEL
GesmbH &: CO. KG
MOXEL S.P.A.
EichenstraBe 58·6411
A·1"120 Vienna
Tel: (0222).857661
Tlx: 134273
Fax: 833583
BELGJUM
NEWTEC INTERNATIONAL
ChauSSlle de Louvain 186
1 940 WoIuwelSt·Etienne
Leuvensesteenweg 186
, 940·Sint·Stevens·Woluwe
Tel: (02) 7250900
Tlx: 25820
Fax: (02) 7250813
NETHERlANDS
BV HANDELMIJ. MALCHUS
Fokkerstraat 511 ·513
Poatbus 48
NL·3100 AA Schiedam
Tel: (010) 373777
Tlx: 21598
c8
SAMSUNG SEMICONDUCTOR
20092 Cinisello Balsamo (MI)
Via C. Frova. 34
Tel: (02) 61290521
Tlx: 352045
Fax: (02: 617.2582
DIS. EL S.R.L.
101.48 Torino
VIS Ala di Slura 71118
Tel: (220) 1522345
Tlx: 215118
SPAIN
SEMICONDUCTORES S.A.
Ronda General Mitre. 240
Barcelona·6
Tel: (93) 2172340
TIx: 97787 SMCD E
Fax: 2175698
SANTOS DEt VALLE, S.A.
Galileo, 54, 56
28015 Madrid
Tel: (91) 4468141/44
TIx: 42615 LUSA E.
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
3. ASIA
HONG KONG
JAPAN
OCEAN OFFICE AUTOMATION LTD.
ADO ELECTRONIC INDUSTRIAL CO., LTD.
UNITS 1&9 2ND FLOOR
FOOK HONG INDUSTRIAL BUILDING
19 SHEUNG YUET ROAD, KOWLOON BAY
KOWLOON, HONG KONG
Tel: 3-7993723 (7 LINES)
Tlx: 52289 OCCOM HX
Fax: 3-7992398, 3-7992082
7th FL., SASAGE BLDG. 4-6 SOTOKANDA
2-CHOME CHIYODA-KU, TOKYO 101, JAPAN
Tel: 03-257-1618
Fax: 03-257-1579
TAIWAN
INTERCOMPO INC.
IHI BLDG., 1-6·7, SHIBUYA, SHIBUYA·KU,
TOKYO 150, JAPAN
Tel: 03-406-5612
Fax: 03-409-4834
YOSUN INDUSTRIAL CORP.
RIKEI CO.
MIN SHENG COMMERCIAL BUILDING
10F_, No. 481, MIN-5HENG EAST RD.,
TAIPEI, TAIWAN, R.O.C.
Tel: 501-0700 (10 LINES)
Tlx: 26777 YOSUNIND
Fax: (02) 503-1278
SHINJUKU NOMURA BLDG. 1-26-2 NISHISHINJUKU, SHINJUKU-KU, TOKYO 163, JAPAN
Tel: 03-345-1411
Fax: 03-344-3949
SINGAPORE
GO UP
585 NORTH BRIDGE ROAD
#12·12 BLANCO COURT, S'PORE 0718
Tel: 2940917/2941101
Tlx: RS 37154 GOUP
Fax: 2913979
c8
SAMSUNG SEMICONDUCTOR
TOMEN ELECTRONICS CORP.
1-1, USCHISAIWAI-CHO, 2-CHOME
CHIYODA-KU, TOKYO 100, JAPAN
Tel: 03-506-3473
Fax: 03-506-3497
DIA SEMICON SYSTEMS INC.
WACORE 641-37-8 SANGENJAYA
SETAGAYA-KU, TOKYO 154, JAPAN
Tel: 03-487-0386
Fax: 03-487-8088
I
SALES
OFFtCESIMANUFACTURER~S
REPRESENTATIVES
4. K·OREA
NA1:WAE ELECTRIC CO., LTD.
Room 403, 2200ng SuminBldg,
#1·6-1, Hangangra-2ka, Yongaanku,
Seoul Korea.
Tel: 701-7341"'5
Fax: 717-1246
SAMSUNG
LIGHT-elECTRONICS CO., LTO.
149-Jang Sa Dong
Jongroku, Seoul Korea
Tel: 744-2110, 269-6187/8
Fax: 744-4803
SEGVU.NG ELECTRONICS
182-2 Jang Sa Dong
Jongroku, Seoul Korea
Tel: 272-6811 "'6
Fax: 273-6597
c8
SAMSUNG SEMICONDUCTOR
NEW CASTLE
SEMICONDUCTOR CO., LTD.
123-1, Joo Kyo Dong
Joongku, Seoul Korea
Tel: 274-3220, 3458
HANKOOK SEMICONDUCTOR
1131-9 Kurodong, Kuroku,
Seoul Korea
Tel: 868-0277"'9
Fax: 868-4604
••
qs ~..!UNG
HEAD OFFICE :
9/10FL. SAMSUNG MAIN BLDG .
250, 2-KA , TAEPYUNG-RO ,
CHUNG-KU , SEOUL, KOREA
C.P.O. BOX 8233
TELEX : KORSST K27970
TEL: (SEOUL) 751-2114
FAX : 753-0967
BUCHEON PLANT:
82-3 , DODANG-DONG,
BUCHEON, KYUNGKI-DO, KOREA
C.P.O. BOX 5779 SEOUL 100
TELEX : KORSEM K28390
TEL: (SEOUL) 741-0066, 662-0066
FAX : 741-4273
KIHEUNG PLANT:
SAN 124 NONGSUH-RI, KIHEUNG-MYUN
YONGIN-GUN, KYUNGKI-DO, KOREAC.P.O. BOX 37 SUWON
TELEX : KORSST K23813
TEL : (SEOUL).7 41-062017
FAX : 741-0628
GUMI BRANCH:
259 , GONDAN-DONG , GUMI ,
KYUNGSANGBUK~O,KOREA
TELEX : SSTGUMI K54371
TEL: (GUM I) 2-2570
FAX : (GUMI) 52-7942
SAMSUNG SEMICONDUCTOR INC .:
3725 NORTH FIRST STREET
SANJOSE, CA 95134-1708, USA
TEL : (408) 434-5400
TELEX : 339544
FAX : (408) 434-5650
HONG KONG BRANCH :
13FL. BANK OF AMERICA TOWER
12 HARCOURT ROAD, HONG KONG
TEL : (5) 21-0307/9 , 21-0300 , 23-7764
TELEX : 80303 SSTC HX
FAX : (5) 84-50787
TAIWAN OFFICE:
RM 1102, LT . BLDG, NO. 385
TUN-HWA S, RD , TAIPEI, TAIWAN
TEL: (2) 777-1044/5
FAX : (2) 777-3629
SAMSUNG JAPAN CO .:
RM 3108, KASUMIGASEKI BLDG .
2-5 , 3-CHOME KASUMIGASEKI
CHIYODA-KU , TOKYO , 100 JAPAN
TEL: (03) 581 -181617585
TELEX : J24244
FAX : (03) 581 -7088
SAMSUNG SEMICONDUCTOR EUROPE GMBH :
MERGENTHA TER ALLEE 38-40
6236 ESCHBORN , WIG .
TEL: 0-6196-90090
FAX: 0-6196-900989
TLX : 4072678 SSED
SAMSUNG (U .K.) LTD.:
6 FL. VICTORIA HOUSE SO\JTHAMPTON
ROW W.C. 1 LONDON . ENGLAND
TELEX : 297987 STARS LG
TEL: 831-6951/5
FAX : (01) 430-0096
PRINTED IN KOREA
JUNE, 1988
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