1988_Siemens_Linear_and_Digital_Integrated_Circuits 1988 Siemens Linear And Digital Integrated Circuits

User Manual: 1988_Siemens_Linear_and_Digital_Integrated_Circuits

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Linear and Digital
Integrated Circuits
Data Book 1988/89

SIEMENS

Linear &. Digital Integrated Circuits
Data Book 1988/89

Published by Siemens Components U.S.A.
2191 Laurelwood Rd., Santa Clara, CA 95054

For the circuits, descriptions, and tables indicated no responsibility is assumed as far as patents or other rights
of third parties are concerned.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery, and prices please contact the Offices of Siemens Components.

Table of Contents
Summary of Types
General Information
ICs for Data Conversion
ICs for Industrial Applications

ICs for Communications
ICs for Sensing Applications
ICs for Video Applications
ICs for Radiol Audio Applications
ICs for Universal Applications
ICs for Power Supply Control
Package Outlines

Table of Contents
Summary of Types

Table of Contents
Page
1.0 Summary of Types ............................................................... .
1.1
Types in Alphanumerical Order ................................................... .
1.2

Types in Application-Oriented Order .............................................. .

2.0 General Information .............................................................. .
2.1
Type Designation Code for ICs ................................................... .

1-1
1-2
1-4

2.2

Mounting Instructions ........................................................... .

2.3

Assembly Instructions for MIKROPACKS .......................................... .

2-1
2-1
2-1
2-1

2.4

Processing Guidelines for ICs .......................•.............................

2-6

3.0 ICs for Data Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

4.0 ICs for Industrial Applications ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . .

4-1

5.0 ICs for Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

6.0 ICs for Sensing Applications.......................................................

6-1

7.0 ICs for Video Applications.........................................................

7-1

8.0 ICs for RadlolAudio Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1

9.0 ICs for Universal Applications.....................................................

9-1

10.0 ICs for Power Supply Control......................................................

10-1

11.0 Package Outlines ............................................. '....................

11-1

1-1

Summary of Types
1.1 Types in Alphanumerical Order
Type
HKZ 101
S041P
S 042P
SAB 0600/0601/0602
SAE 0531
SAE 0700
SAE 81C52P;G
SAE 81C54P;G
SAE 81C80
SAS 231W
SDA 0808A;B;N
SDA 0810A;B;N
SDA 0812
SDA 2112-2
SDA 2121
SDA 2208-2
SDA 2211
SDA 2506
SDA 2516
SDA 2526
SDA 3112
SDA 3202-2;2X
SDA 3203
SDA 3208
SDA 3252
SDA 4212
SDA 5200N
SDA 5200S
SDA 6020
SDA 8005
SDA 8010
SDA 8020
SDA 8200
SDA 8800
SLB 0586
SLE 4501
SLE 4502
SLE 4520
SLE 5001/5002
TBB 042G

1-2

Name
Hall Effect Vane Switch .........................'................ .
FM IF Amplifier with Demodulator ................. : .............. .
Mixer ......................................................... .
Audible Signal Devices .......................................... .
60 Hz Timer ................................................... .
Audible Signal Device ..... '...................................... .
Static CMOS RAM .............................................. .
Static CMOS RAM ................................• '............•.
Dual Port RAM ...................................•..............
Linear Hall Effect Device ........................................ .
8-Bit CMOS AID Converter ...................................... .
1O-Bit CMOS AID Converter. -' .................... ,' .............. .
12-Bit CMOS AID Converter ................ : .................... .
PLLfor TV, CATV, Tuning Systems ........................ : ...... .
PLL for Digital Tuning in AMIFM Receivers ........................ .
IR Transmitter, Manchester Biphase Code ......................... .
1.3 GHz Prescaler..1:64 ECL Output ........ : ...................... .
128 x 8 EEPROM, 3 Wire Control ................................. .
128 x 8 EEPROM, IIC Bus Control ................................ .
256 x 8 EEPROM, IIC Bus Control .........•.......................
PLLfor TV, CATV, Digital Tuning Systems ......................... .
PLL for Tuning Systems with IIC Bus Control ..•.....................
1.3 GHz PLL for Tuning Systems ...............................•..
IR Transmitter ................................................. .
PLL Tuner Control .............................................. .
1.3 GHz Prescaler, 64:256 ........•..•...........•................
6-Bit AID Converter ...................................•.........
6-Bit AID Converter .....•..•.............•.............•..•.....
6-Bit AID Converter, 50 MHz ......•..•••.......•.........•.......
8-Bit 01 A Converter, 100 MHz ................................... .
8-Bit AID Converter, 100 MHz ................................... .
Data Acquisition Shift Register DASR ........•.....................
6-Bit AID Converter, 300 MHz .....•...•..........................
Data Acquisition Controller .............................•.........
Electronic Dimmer .........•.................................... \
Non Volatile Counter ............................................ .
Prescaler for 4501 .............................................. .
3 Phase PWM Motor Controller .................................. ..
UniversallR Transmitter ..........•...............................
Balanced Mixer •................................. " .........•....

Page
6-1
8-1
8-7
4-1
9-1
4-9
9-15

9-23
9-27
6-7
3-1
3-7
3-13
7-1
8-12
9-44

7-13
7-18
7-22
7-27
7-32
7-42
7-52
9-53

7-61
7-73
3-19

3-25
3-31
3-37
3-49

3-58
3-74
3-86
4-14
4-21
4-34
4-41
9-62
5-1

1.1 Types in Alphanumerical Order (Continued)
Type

TBB 200;G
TCA 205A;K
TCA 305A;G;K/355B;G
TCA 440
TCA 785
TCA 1560B
TCA 1561B
TDA 1037
TDA 2025
TDA 4010
TDA4050B
TDA 4060/TDE 4060
TDA 4061/TDE 4061
TDA 4210-3
TDA4282T
TDA 4601;D
TDA 4605
TDA 4814A
TDA 4917A;G
TDA 4918A;G
TDA 4919A;G
TDA4930
TDA 4935
TDA 5400-2
TDA 5660P
TDA 5835
TDA 5850
TFA 1001W
TLE 4201A;S
TLE 4202
TLE 4211
TLE 4901F;K
TLE 4902F
TLE 4903F
TLE 4910K
TLE 4950
TUA 1574
TUA 2005
TUA 2006
UAA 170
UAA 180

Name

PLL Frequency Synthesizer ...................................... .
Proximity Switch ............................................... .
Proximity Switch ............................................... .
AM Receiver ................................................... .
Phase ControllC, 250 mA Output ................................. .
Stepper Motor Driver ........................................... .
Stepper Motor Driver ........................................... .
5 Watt Power Amplifier .......................................... .
50 Watt Power Amplifier ......................................... .
AM Receiver IC ................................................ .
IR Preamplifier ................................................. .
IR Preamplifier, 5V ............................................. .
IR Preamplifier with Demodulator, 5V ..........................•...
FM IF Amplifier with Multipath Detection ..................•.........
Quasi-Parallel Sound IC ......................................... .
Control IC for SMPS ............................................ .
ControllC for SMPS with SIPMOS Drive ........................... .
IC for Active Line Filters ......................................... .
Supervisory IC for Power Supplies ................................ .
ControllC for SMPS ............................................ .
ControllC for SMPS ............................................ .
2 x 10 Watt AF Power Amplifier ................................... .
2 x 14 Watt AF Power Amplifier ................................... .
Video IF Amplifier with AFC ...................................•...
VHF/UHF Modulator IC for Video and Sound ...................... .
Video IF IC Quasi-Parallel Sound and AFC ......................... .
Video Switch with Two Inputs .................................... .
Photodiode with Amplifier ....................................... .
DC Motor Driver ................................................ .
DC Motor Driver ................................................ .
Low Side Dual Switch, 2A ...•....................................
Hall Effect IC, Bipolar Field ....... : .............................. .
Hall Effect IC, Bipolar Field ...................................... .
Hall Effect IC, Unipolar Field ..................................... .
Hall Effect IC, Linear ...•...•.....................................
Current Monitoring IC ......•.....................................
FMTunerlC .............................•......................
VHF Tuner IC, 700 MHz ......................................... .
VHF Tuner IC, 700 MHz .......................................... .
LED Array Driver for Dot Display ................................... .
LED Array Driver for Bar Display .......................•...........

Page

5-6
6-9
6-15
8-24
4-48
4-64
4-64
8-41
8-50
8-56
9-71
9-76
9-83
8-63
7-81
10-1
10-17
10-30
10-37
10-44
10-52
8-69
8-83
7-86
7-91
7-135
7-144
6-23
4-76
4-85
4-92
6-35
6-39
6-43
6-47
10-60
8-96
7-147
7-154
9-88
9-95

1-3

, Summary of Types
1.2 Types In Application-Oriented Order
IC's for Data Conversion
SOA 0808A;B;N
SDA 0810A;B;N
SDA 0812

8-Bit CMOS AID Converter .. , .. , •.... , .. ", .. , .... ,.'. ,., , , ... , ,.
1O-Bit CMOS AID Converter. , .. , . , .•... , , , , . , , . , ... , , ... , , .... , . ,
12-Bit CMOS AID Converter. , ........ , . , , , , ...... , • , , .. , , ..... , . ,

Page
3-1
3-7

6-Bit AID Converter ....................................•........

3·13
3-19
3-25

SDA 6020

6-Bit AID Converter, 50 MHz .......................•.............

3-31

SDA 8005
SDA 8010

8-Bit 01 A Converter, 100 MHz ................................... .
8-Bit AID Converter, 100 MHz ................................... .
Data Acquisition Shift Register DASR ............................. .

3-37
3-49

SDA 5200N
SDA 5200S

SDA 8020
SDA 8200
SDA 8800

6-Bit AID Converter , .. ,." ... ,., ... ",.,.,.'., .. ,., ...........•.

6-Bit AID Converter, 300 MHz . '.................................. .

3-58
3-74:

Oata Acquisition Controller ...................................... .

3-86

IC's for Industrial Applications
SAB 0600/0601/0602

Audible Signal Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .

4-1

SAE 0700

Audible Signal Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .

4-9

SLB 0586
SLE 4501
SLE 4502

Electronic Dimmer .............................................. .

4-14

Non Volatile Counter ........•....................................
Prescaler for 4501 ...........................................•...

SLE 4520

3 Phase PWM Motor Controller .................................. ..

4·21
4-34
4-41

TCA 785

Phase ControllC, 250 mA Output ..•..............••...............

4-48

TCA 1560B
TCA 1561B

Stepper Motor Driver ........................................... .

4-64

Stepper Motor Driver ....... '............•...............•........
DC Motor Driver ...........................•.....................

4-64
4-76

DC Motor Driver ...........................•.....................

4-85

Low Side Dual Switch, 2A ....................................... .

4-92

TLE 4201A;S
TLE 4202
TLE 4211

IC's for Communications
TBB 042G

Balanced Mixer .................... ',' .......................... .

5-1

TBB 200;G

PLL Frequency Synthesizer ...................................... .

5·6

IC's for Sensing Applications
HKZ 101
SAS 231 W

Hall Effect Vane Switch ................................••........
Linear Hall Effect Device ........................................ .

TCA 205A;K
TCA 305A;G;K/355B;G

Proximity Switch ............................................... .
Proximity Switch ...................•. : ... '....•..................

TFA 1001W
TLE 4901F;K

Photodiode with Amplifier ....................................... .
Hall Effect IC, Bipolar Field .................. , ................... .

TLE 4902F
TLE 4903F

Hall Effect IC, Bipolar Field ...................••.•......•.........

6-35
6-39

Hall Effect IC, Unipolar, Field ...............•............•....•....

6-43

TLE 4910K

Hall Effect IC, Linear .......•...........•.........................

6-47

1-4

6·1
6·7
6·9
6-15
6-23

1.2 Types In Application-Oriented Order

(Continue!1>

IC's for Video Applications
SDA 2112-2
PLLforTV, CATV, TuningSyatema ............ ;...................
SDA 2211
1.3 GHz Prescaler,1:64 ECL Output...............................
SDA 2506
128 x 8 EEPROM, 3 Wire Control..................................
SDA 2516
128 x 8 EEPROM,IIC BUB Control.................................
SDA 2526
256 x 8 EEPROM,IIC Bus Control....................... ....•. ....
SDA 3112
PLL for TV, CATV, Digital Tuning Systems ....•••.••...••.....•....•
SDA 3202-2;2X
PLL for Tuning Systems with IIC Bus Control ••••.•..•••......•••.•..
SDA 3203
1.3 GHz PLL for Tuning Systems .......•..•.••.•..••.•........•...
PLL Tuner Control •.......•.•....••.•.••...•..•..•....•.•.••..•..
SDA 3252
SDA 4212
1.3 GHz Prescaler, 64:256 ............••.•••••.•••.•.•.....••.....
Quasi-Parallel Sound IC ..•.••.•..•.......•..••••..•..............
TDA4282T
TDA 5400-2
Video IF Amplifier with AFC .•.••...•....•..••...••...•.....••••...
TDA5660P
VHF/UHF Modulator IC for Video and Sound •...•••...••.•...•••.•.
TDA 5835
Video IF IC Quasi-Parallel Sound and AFC •••.••••.••••••..•.••....•
TDA 5850
Video Switch with Two Inputs .................................... .
TUA2005
VHF Tuner IC, 700 MHz •..•..•.•.•..•••.••..•..•..•..•...••......
VHF Tuner IC, 700 MHz ....•..........•..•••••.•••.•.•.•...•••...
TUA2006
IC's for RadlolAudio
S 041P
S 042P
SDA 2121
TCA 440
TDA 1037
TDA 2025
TDA 4010
TDA 4210-3
TDA4930
TDA 4935
TUA 1574

Applications
FM IFAmplifi~rwith Demodulator.................................
"Mixer ...•.•...........•••...•• ; • • . . • • • • • . . • • . • . • • . . . • • • • . • • . • . .
PLL for Digital Tuning in AM/FM Receivers.........................
AM Receiver. . . • . . • . . • • . . . • • • • • . . • • • . . . . • • . • • • • • • . . . . • • . • . • • • . . .
5 Watt Power Amplifier ............••••...•..•••.•..••......•.....
50 Watt Power Amplifier .•..••.•.•.•..••.••••..•••••.•••••..••.•••
AM Receiver IC ........•.•....•.•...•••.••..•...••....... , •.....
FM IF Amplifier with Multipath Detection •..•.•.••.•.•..•............
2 x 10 Watt AF Power Amplifier ..•.•••••.•••••••••••...•••...•..•..
2 x 14 Watt AF Power Amplifier ................................... .
FM Tuner IC •.•.•.••...•......•.•••.••..•.•.••••••..•••..•..•••.

IC's for Universal Applications
SAE 0531
60 Hz Timer .......•..•.....•.••...•.•....•••.••.....•........•.
SAE 81C52P;G
Static CMOS RAM. ..............................................
SAE 81 C54P;G
Static CMOS RAM. . . . • . . . • . • . . • . . • • . . • • . . . • . . • • • . . • • . . . • . . . . • . . .
SAE 81C80
Dual Port RAM..................................................
SDA 2208-2
IR Transmitter, Manchester Bipha.. Code .••••..••.•••••••••.••••••
IR Transmitter .........•..•.•...•••.••••••.••••.••..•.•.•.•••...
SDA 3208
SLE 5001/5002
UniversallR Transmitter .••..••••..••.••..•.••••.•••••• , ••.••.•.•.
TDA 4050B
IR Preamplifier ..•......••.••••.•.•.•••••.•••.•••••••.•••...•.••.
TDA 4060/TDE 4060
IR Preamplifier, 5V .............•.....•...•...•..•••.•••••..•••••
TDA 4061/TDE 4061
IR Preamplifier with Demodulator, 5V ............................. .
UAA 170
LED Array Driver for Dot Display •••..•••••.••••.••..•.••..•••..••.•
UAA 180
LED Array Driver for Bar Display .................................. .

Page
7-1
7-13
7-18
7-22
7-27
7-32
7-42
7-52
7-61
7-73
7-81
7-86
7-91
7-135
7-144
7-147
7-154'-,

8-1
8-7
8-12
8-24
8-41
8-50
8-56 .
8-63
8-69
8-83
8-96

9-1
9-15
9-23
9-27
9-44
9-53
9-62
9-71
9-76
9-83
9-88
9-95

1-5

1.2 Types In Application-Oriented Order (Continued)
IC's for Power Supply Control
TDA 4601;0
Control IC for SMPS ....•.............. ~ . . . . . . . . . • . . . . . . . . . . . . . . .
TDA 4605
ControllC for SMPS with SIPMOS Drive. . . • . . . . . .. .. . . . . . . . . . . . . . . •
IC for Active Line Filters. ; '.......... '............'.................. .
TDA 4814A
TDA 4917A;G
Supervisory IC for Power Supplies ................................ .
TDA 4918A;G
ControllC for SMPS ... ; ..... :'.................................. .
ControllC for SMPS ............. '........ :. ~ ..................... .
TDA4919A;G
Current Monitoring IC ......•• " ..•..............•.................
TLE 4950

-

,1-6

....

Page
10·1
10·17
10·30
10·37
10·44
10·52
10·60

General Information

General Information
2.1 Type Designation Code for ICs
The IC type designations are based on the European code system of Pro Electron. The code system is
explained in the Pro Electron brochure D is, edition
1982, which can be obtained from:
Pro Electron
Boulevard de Waterloo 103
B-1000 Bruxelles

2.3 Assembly Instructions for
MIKROPACKs
2.3.1 Delivery Package
The MIKROPACK PSB 7510 is generally delivered
on metal film spools in metal cans. For prototypes,
the IC can also be packed individually. MOS handling is necessary.

2.3.2 Substrate Connections

2.2 Mounting Instructions

For assembly of the MIKROPACK, the connection
points on the substrate must be coated with solder.
This can be achieved by:

2.2.1 Plastic and Ceramic Plug-In Package
The plug-in packages are soldered to the PCB with
the solder joints at the back of the board. The pins
are bent down at an angle of 90°. They fit into holes
of 0.7 to 0.9 mm diameter, spaced at an equal distance of 2.54 mm. The dimension x is shown in the
corresponding package outline drawing.

• Galvanic deposition and melting
• Screen printing and melting
• Dip or wave tinning
Solder tin composition: Sn 60 I Pb 40
Thickness of the layer: approx. 15 ,...m (after melting)

The bottom of the package does not touch the printed circuit board after insertion, because the pins
have shoulders just below the package (see Figure).

Un. identical t. the copt••

ada••1til. MIKROPACKS

O.to,l "A"
.lHeosure ofter etchmg

After inserting the package into the printed circuit
board, two or more pins should be bent at an angle
of approximately 30° relative to the printed circuit
board so that the package need not be held down
during soldering. The maximum permissible soldering temperature for iron soldering is 265°C (max.
iDs) and for dip soldering 240°C (max 4s).

I Substrote ,onneel,onl

substrote (Onnectlons

Plastic Plug-In Package

0010-3

Dimensions in mm

0010-1

Note:
Necking of the connection leads is not required in
the case of galvanically deposited Sn/Pb and subsequent melting.

Ceramic Plug-In Package
2.3.3 Assembly Recommendations

~e

All assembly recommendations are valid for the following substrate materials:
.

+ ...........

-12541-·
0010-2

Dimensions in mm

•
•
•
.•

Epoxy resin
Hard-paper
Ceramic (thick-thin-film)
Flexible materials, as for example polyimide

• Glass

2-1

•

General Information

I. Prototypes and Small Quantities
(e.g., up to approx. 1.0/year)

Procedure
Cautlonl The general rules for the processing of
MOS components must be followed during
all operations.

Recommended Processing Method:

Cut MIKROPACK leads free with hand tool (for components delivered on spools only).

Manual Soldering with Mini Soldering Iron

Principle

Cutting Dimensions: 9.2
11.4 ± 0.05 mm

± 0.05 mm x

tapton spacer material

/

Required Equipment and Accessories

• Hair brush
• Sodium-free flux according to DIN 8511 (e.g., pure
colophonium dissolved in alcohol)
• Cleaning agents (if required): e.g., Freon T-P 35
and TF

I

I
I
I
I
I

I·

I
I

0

x

---

dIrection

0

g

9

L~ ;4~'~~.-~

(

on

I

I

• Devices for cutting and punching (only when processing from tape)

• Stereo microscope (magnification 6...40 x)
• Suction tub or tweezers

\

-8-:
1
L
~ -

~

0010-4

• Forming tools
• Temperature-regulated miniature soldering .iron,
certified for the soldering of MOS components

/

r

11

\

N

j

0010-5

Caution I Only cut free along the dashed linesl
Do not cut the 4 capton spacers.
Form MIKROPACK leads with hand. tool.
(For the relief of mechanical stress when mounted)

Forming Dimensions

• Bench top suited for the processing of MOS components

Soldering Data
• Soldering temperature at the soldering iron tip:
230·C max.
• Soldering time: approx. 1-2 s

2-2

0010-8

Dimensions in mm

General Information

,

-

\- Punch "A"

D.Io,1 "A"

-Etf

-

0

0

o

0

<

•

0010-7

Punch MIKROPACK out of the film tape with hand
tool (for components delivered on spools only)
Lay down the punched MIKROPACK onto an electrically conductive surface vacuum pickup.

Required Equipment and Accessories
As in I., only instead of 'the soldering iron:
Pulse Soldering Device

Coat the mounting points on the substrate with flux
(with brush by hand).
Position the MIKROPACK and adjust by hand under
stereo microscope (approx. 5 to 10x magnification).

Pulse Soldering Head
(dimensions according to the drawing)

~

Solder the individual leads by hand with soldering
iron under stereo microscope.
Importantl First solder two opposite leads. This prevents a shifting of the MIKROPACK during the soldering process.

Solder,ng oren

!

:5-

Cleaning (if required)

I

8.21005

Move the substrates one after the other for approx.
1 minute in T-P 35 and TF for example (no ultrasonic
cleaning).
Place the cleaning substrates on an electrically conductive surface or in appropriate trays.

0,6, 08
0010-9

Dimensions in mm

(e.g., up to approx. 30.0/year)

Head holder
Control device (temperature, time)
Substrate holder (with micro-manipulator, if necessary)
Stereo microscope

Recommended Assembling Method:

Soldering Data

II. Medium Quantities

Pulse Soldering with Manual Device

Principle

Soldering temperature at the pulse soldering head:
230·C max.

Soldering heod
I Pulse resistance heating)

Soldering time: approx. 2s plus an additional holding
time of 1s until the solder becomes solidified.

~

-~

Solder-Ioot.d

Substrote

O:"::,.r

It

~

0010-8

2-3

General Information
Procedure
As described in I. including the positioning of the
MIKAOPACK onto the substrate and the adjustment.

After the Pb/Sn solder becomes solidified (holding
time, observation through stereo microscope) raise
the soldering head and place the substrate onto an
electrically conductive surface or in an appropriate
tray.

Cautlonl Ceramic and glass substrates must be preFurther Steps
'Position the substrate with the positioned MIKAOPACK onto the substrate holder of the pulse soldering device.
Lower, adjust and set down the soldering head onto
the MIKAOPACK leads manually, then trigger the
soldering pulse.

,heated and the stated temperatures must
be maintained during the soldering process.
Ceramic: 150·C
Glass:
125·C
Neither preheating nor cooling may be sudden (danger of breakage).
I

Cleaning (if required): as in I.

III. Large Quantities
(e.g., approx. 30.0/year)

Recom,mended Assembling Method:
Semi-Automatic Pulse Soldering

Principle
Vacuum pickup tool

MIKROPACIC

\

0010-10

rake up
1

r

(ut free

1

[--~I'--rn-.- ~ - -,.I~
:
I

I

I

Punch out

L ___ Pulse sotdenng
0010-11

2-4

General Information
Required Equipment and Accessories

IV. Very Large Quantities

Sem'i-automatic pulse soldering device including
tools for cutting, forming and punching.

(e.g., approx. 500.0/year)

Stero microscope (magnification 6 to 40x).

Recommended Assembling Method:

Flux according to DIN 8511 (e.g., pure colophonium
dissolved in alcohol).

Fully Automatic Pulse Soldering

Cleaning agents (if necessary): Freon T-P 35 and
TF.
Soldering Data
Soldering temperature at the pulse soldering head
230°C max.
Soldering time: approx. 2s plus an additional holding
time of 1s until the solder becomes solidified.

2.3.4 Final Inspection
It is recommended, that a final visual inspection of
the mounted MIKROPACKs be included after soldering, respectively cleaning (under the stereo microscope, magnification 6 to 40x).
Important Criteria
The solder transition between the MIKROPACK
leads and the substrate traces should be concave
tapered.

Procedure
Position the supply roll in the pulse soldering device.
Coat the mounting positions on the substrate with
flux by hand or machine.
Position the substrate onto the substrate holder.
Caution! Ceramic and glass substrates must be preheated and the state temperatures must
be maintained during the soldering process.
Ceramic: 150°C
Glass: 125°C.
Neither preheating nor cooling may be sudden (danger of breakage).
Machine-cut, form,
MIKROPACK.

Processing method as in III. but fully automatic

punch

and

pre-adjust the

Fine-adjust with micro-manipulator (under the stereo
microscope or on a monitor).

The connections to the semiconductor IC must not
be damaged.
The solder on all substrate leads must be visibly
melted.
MIKROPACK and substrate surface must not show
signs of soiling after soldering, respectively cleaning.

2.3.5 Replacment
Experience shows that MIKROPACKs can be replaced as many as five times depending on sub·
strate material and layer construction.
Desolder the MIKROPACK with miniature soldering
iron or hot air gun and tweezers. The leads are heat·
ed to the melting point of the Pb/Sn solder and bent
up with the tweezers.
Plane the mounting spots and recoat with flux.

Pulse-solder by machine.
Place the substrate onto an electrically conductive
surface or in an appropriate tray.

Solder in a new MIKROPACK using one of,the meth·
ods described.

Cleaning: (if required): as in I.

2·5

•

General Information

MOS and CMOS devices generally have integrated
protective circuits and it is hardly possible any more
for them to be destroyed by purely static electricity.
On the other hand, there is acute danger from electrostatic discharges (ESO).

2. ICs may only be handled at specially equipped
work stations. These stations must have work surfaces covered with a conductive material of the
order of 106 to 109 {Vcm.
3. With humidity of > 50% a coat of pure cotton is
sufficient. In the case of chargeable synthetic fibers the clothing should be worn close-fitting. The
wrist strap must be worn snugly on the skin and
be grounded across a resistor of 50 to 100 kO.
4. If conductive floors, R = 5 X 104 to 107 0 are
provided, further protection can be achieved by
using so-called MOS chairs and shoes with a conductive sole (R z 105 to 107 0).

Of the multitude of possible sources of discharge,
charged devices should be mentioned in addition to
charged persons. With low-resistive discharges it is
possible for peak power amounting to kilowatts to be
produced.

5. All transport containers for ESS devices and assembled circuit boards must first be brought to
the same potential by being placed on the work
surface or touched by the operator before the individual devices may be handled. The potential
equalization should be across a resistor of 106 to

2.4 Processing Guidelines for ICs
Integrated circuits (ICs) are electrostatic-sensitive
(ESS) devices. The requirement for greater packing
density has llild to increasingly small structures on
semiconductor 'chips, with the result that today every
IC, whether bipolar, MOS, or CMOS, has to be protected against electrostatics.

108 O.
For the protection of devices·the fol,lowing principles
'
should be observed:
a) Reduction of charging voltage, below 200V if possible.
Means which are effective here are an increase in
relative humidity to ~ 60% and the replacement
of highly charging plastics by antistatic materials.
b) With every kind of contact with the device pins a
charge equalization is to be expected. This should
, always be highly resistive (ideally R = 106 to
10S nj.
All in all this means that ICs call for special handling,
because uncontrolled charges, voltages from ungrounded equipment or persons, surge voltage
spikes and similar influences can destroy a device.
Even if devices have protective circuits (e.g., protective diodes) on their inputs, the following guidelines,
for thlilir handling should nevertheless be observed.

2.4.1 Identification
The packing of ESS devices is provided with the following label by the manufacturer:

2.4.2 Scope
The guidelines apply to the storage, transport, testing, and processing of all kinds of ICs, equipped and
soldered circuit boards that comprise such components.

2.4.3 Handling of Devices
1. ICs must be left in their containers until they are
processed.

2-6

6. When loading machines and production devices it
should be noted that the devices come out of the
transport magazine charged and can be damaged
if they touch metal, e.g., machine parts.
Example 1) conductive (black) tubes.
,The devices may be destroyed in the
tube by charged persons or come out
of the tube charged if this is emptied
by a charged person.
Conductive tubes may only be handled at ESS work stations (high-resistance work-station and person
grounding).
Example 2) anti-static (transparent) tub~s.
The devices cannot be destroyed by
charged persons in the tube (there
may be a rare exception in the case
of custom ICs with unprotected gate
pins). The devices can be endangered as in 1) when the tube is emptied if the latter, especially at low humidity, is no longer sufficiently antistatic after a long period of storage
(> 1 year).
In both cases damage can be avoided by discharging the devices across a grounded adapter of highresistance material (z 106 to 108 O/cm) between
the tube and the machine.
The use of metal tubes-especially of anodized aluminum-is not advisable because of the danger of
low-resistance device discharge.

General Information
2.4.4 Stor:age
ESS devices should only be stored in identified locations provided for the purpose. During storage the
devices should remain in the packing in which they
are supplied. The storage temperature should not
exceed 60·C.

2.4.5 Transport
ESS devices in approved packing tubes should only
be transported in suitable containers of conductive
or longterm anti-static-treated plastic or possibly unvarnished wood. Containers of high-charging plastic
or very low-resistance materials are in like manner
unsuitable.
Transfer cars and their rollers should exhibit adequate electrical conductivity (R < 106 fi). Sliding
contacts and grounding chains will not reliably eliminate charges.

2.4.6 Incoming Inspection
In incoming inspection the preceding guidelines
should be observed. Otherwise any right to refund or
replacement if devices fail inspection may be lost.

2.4.7 Material and Mounting
1. The drive belts of machines used for the processing of the devices, in as much as they come into
contact with them (e.g., bending and cutting machines, conveyor belts), should be treated with
anti-static spray (e.g., anti-static spray 100 from
Kontaktchemie). It is better, however, to avoid the
contact completely.
2. If ESS devices have to be soldered or desoldered
manually, soldering irons with thyristor control
may not be used. Siemens EM I-suppression capacitors of the type 8 81711-831 ...-B36 have
proven very effective against line transients.
3. Circuit boards fitted and soldered with ESS devices are always to be considered as endangered.

2.4.8 Electrical Tests
1. The devices should be processed with observation of these guidelines. 8efore assembled and
soldered circuit boards are tested, remove any
shorting rings.
2. Test receptacles must not be conducting any voltage when individual devices or assembled circuit
boards are inserted or withdrawn, unless works
specifications state otherwise. Ensure that the

test devices do not produce any voltage spikes,
either when being turned on and off in normal operation or if the power fuse blows or other fuses
respond.
3. Signal voltages may only be applied to the inputs
of ICs when or after the supply voltage is turned
on. They must be disconnected before or when
the supply voltage is turned off.
4. Observe any notes and instructions in the respective data books.

2.4.9 Packing of Assembled PC Boards or
Flatpack Units
The packing material should exhibit low volume cohductivity:
105 fi/cm < p < 1010 !Vcm.
In most cases-especially with humidity of > 40%this requirement is fulfilled by simple corrugated
board. Better protection is obtained with bags of
conductive polyethylene foam (e.g., RCAS 1200
from Richmond of Redlands, California).
One should always ensure that boards cannot
touch.
In special cases it may be necessary to provide protection against strong electric fields, such as can be
generated by conveyor belts for example. For this
purpose a sheath of aluminum foil is recommended,
although direct contact between the film and the
PCB must be avoided. Cardboard boxes with an aluminum-foil lining, such as those used for shipping
our devices, are available from Laber of Munich.

2.4.10 Ultrasonic Cleaning of ICs
The following recommendation applies to plastic
packages. For cavity packages (metal and also ceramic) separate regulations have to be observed.
Freon and isopropyl alcohol (trade name: propanol)
can be used as solvents. These solvents can also
be used for plastic packages because they do not
eat into the plastic material.
An ultrasonic bath in double halfwave operation is
advisable because of the low component stress.
The ultrasonic limits are as follows:
sound frequency
f >40 kHz
exposure
t < 2min
alternating sound pressure
p < 0.29 bar
sound power
N < 0.5 W/cm 2/litre

2-7

•

ICs for Data Conversion

•

SIEMENS

SDA 0808 A, SDA 0808 B, SDA 0808 N
8-Bit CMOS Analog-to-Digital Converters
with 8-Channel Multiplexers
• OV to 5V Analog Input Voltage Range

• Resolution 8 Bits
• Total Unadjusted Error

± % LSB

• No Offset or Gain Adjustments Required

• No Missing Codes

• Latched TRI-STATE Outputs

• Fast Conversion Time (15 p.s)

• Outputs Meet TTL Voltage Level
Specifications

• Single Supply 5 VOC
• 8-Channel Multiplexer with Latched Control
Logic

• CMOS Low Power Consumption, -15 mW

• Easy Interface to All Microprocessors, or
Stand Alone Operation

• Extended Temperature Range
- 40"C to + 125"C (SDA 0808B)

• 28-Pin P-DIP Standard Package or PLCC

Pin Configurations
Top View

SDA0808N
A.NS

AINl

28

AIN4

AINS

AIN2

AIN6

27

AINl

4

26

AINO

AIN6

25

ADDO

AIN7

24

ADD 1

soc

23

ADD2

Eoe

22

ALE

2'

21

OEN

20

2"

10

19

2')

vee

II

18

2"

REF(+)

12

17

2 0(lS8)

GNO

13

16

REF(-)

2"

14

15

2"

elK

".'11)

3

2

AI\!

4,1'1.2

AIN4
I

~

A,NO

28 27 26

AI1\I7

soc
eoe

2 I (MS8)

:5

AOO~

~.

ADO'

-.

AO~l

2'

~LE

OE"

.:" ',\1S31

CLr.

'0

vee

"

! I

:1

:.J

..

'!
=IE' .:
GN:>

AErH

2"

2'

l4ClSJl

0077-1

0077-4

The SOAOSOS is a monolithic CMOS S-bit analog to digital converter, with'S-channel analog multiplexer, with a
single supply of 5 Voe. The device has a microprocessor compatible control logic and an S-bit data bus. It is a
pin-to-pin compatible device to the data acquisition component ADC OSOS/OS09.
The SDAOSOS uses the method of successive approximation with a capacitor network as conversion technique. The converter features a temperature stabilized differential comparator, S-channel multiplexer for S
analog inputs and a sample and hold circuit. The device needs no external offset or gain adjustments. Easy
interfacing to microprocessors is provided by 3-bit address latches, S-bit data-output latches and an S-bit TRISTATE® databus.
The temperature range of the SDA OSOSA is - 40'C to
@Siemens Components, Inc.

3-1

+ S5"C and for the SDA OSOS8

- 40'C to

+ 125·C.
April 1988

SDA 0808 A, SDA 0808 8, SDA 0808 N

Pin Definitions
Pin No.

Symbol

Function

1 to 5
6
7
8
9
10
11
12
13
14,15
16
17 to 21
22
23 to 25
26 to 28

AIN3toAIN7
SOC
EOC
2- 5
OEN
CLK
Voo
REF(+)
GND
2- 7 ,2- 6
REF(-)
2- 8 t02- 1
ALE
ADD2to ADDO
AINOto AIN2

Analog Inputs
Start of Conversion
End of Conversion
Digital Output Signal
Output Enable
External Clock Input
Pos. Supply Voltage
Pos. Reference Voltage
Ground
Digital Output Signals
Neg. Reference Voltage
Digital Output Signals
Address Latch Enable
Address Inputs
Analog Inputs

Technology
Advanced CMOS (ACMOS) process.

Functional Description
The Converter
The converter is partitioned into 3 major sections:
An approximately 50 pF capacitor network as a sample and hold circuit, the successive approximation
register and the comparator. The capacitor network
includes a circuit configuration, which provides the
first output for a transition when the analog signal
has reached + % LSB.
The AID converter's successive approximation register (SAR) is reset on the positive edge of the start
of conversion (SOC) pulse. The conversion starts after the falling edge of the start of conversion pulse
with the next rising edge of the external clock signal.
A conversion in process will be interrupted by a SOC
pulse.
The end of conversion output (EOC) will go low after
the rising edge of the start of conversion pulse. It is
set to logical one with the first rising edge of the
external clk after the internal latch pulse. The autozeroed, high resolution, low drift comparator
makes the AID-converter extremely immune to temperature errors.

AID Converter Timing
After a conversion has been started, the analog voltage at the selected input channel is sampled for 10
external clock cycles which will then be held at the
sampled level for the rest of the conversion time.

3-2

The external analog source must be strong enough
to source the current in order to load the sample and
hold capacitance, being approximately 50 pF, within
those 10 clock cycles.
Conversion of the sampled analog voltage takes
place between the 11th and 19th clock cycle after
sampling has been completed. In the 19Jh clock cycle the converted result is moved to the output data
latch. With the leading edge of the 20th clock cycle
at the end of conversion signal is set.

Multiplexer
The device provides eight multiplexed analog input
channels. A particular input channel is selected by
programming 3 address lines (AD2, AD1, ADO). Table I shows the input states for the address lines to
select a channel. The address is latched on the rising slope of the ALE signal.
Table I
Selected
Analog Channel

Address Lines
AD2

AD1

A!)O

AIN

L

L

L

AINO

L

L

H

AIN1

L

H

L

AIN2

L

H

H

AIN3

H

L

L

AIN4

H

L

H

AIN5

H

H

L

AIN6

H

H

H

AIN7

SDA 0808 A, SDA 0808 B, SDA 0808 N

Absolute Maximum Ratings*
SupplyVoltage(1) (Vee> .....•....•.......... S.5V
Input Voltage Range (VI) ....• - 0.3V to Vee + 0.3V
Continuous Total Power Dissipation
(at or below 25·C Free-Air
Temperature Range) .................... 875 mW

'Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Free-Air Temperature Range
SDA 0808A (TA) .............. - 40·C to + B5·C
SDA 08088 (TA) ............. -40·C to + 125·C
Storage Temperature
Range (Tstg) .........•...... - 65·C to

+ 150·C

Note:

1. All voltage values are with respect to' network ground
terminal.

Recommended Operating Conditions
Parameter

vee =

5V; T A = 25·C

Symbol

limits

Conditions

Min Typ
Supply Voltage

Vee

Positive Reference Voltage

VREF+(3)

4.5

5
Vee Vee
0

Negative Reference Voltage

VREF-

Differential Reference Voltage

llVREF = VREF+ - VREF-

Start Pulse Duration

Units
Max
6

V

+ 0.1

V

-0.1

5

V
V

200

ns

Address Load Control Pulse Width tw(ALe)

200

ns

Address Setup Time

tsu

50

ns

Address Hold'Time

th

50

Clock Frequency

fclock

10

twiSi

ns
640

1500

kHz

Note:

3. Care must be taken that this rating is observed even during power up.

Electrical Characteristics
over recommended operating free-air temperature range, Vee = 4.75V to 5.25V (unless otherwise noted)

Total Device
Parameter

Symbol

Limits

Conditions
Min

High-Level Input Voltage, Control Inputs

VIH

Vee

Low-Level Input Voltage, Control Inputs

=
=

5V

VIL

Vee

High-Level Output Voltage

VOH

10 = -360/J-A

Low-Level Output Voltage
Data Outputs
End of Conversion

VOL
VOL

10 = 1.6mA
10 = 1.2mA

Typ

Units
Max
V

Vee - 1.5
1.5

5V

V
V

Vee - 0.4
0.45
0.45

V
V

3-3

SDA 0808 A, SDA 0808 B, SDA 0808 N

Electrical Characteristics over recommended operating free-air temperature range, Vee = 4.75V to
5.25V (unless otherwise noted) (Continued)
Total Device (Continued)
Parameter

Symbol

Min
Off-State (High Impedance-State)

loz

Control Input Current at Maximum
Input Voltage

II

Low-Level Control Input Current

IlL

Supply Current

Icc

Input Capacitance, Control Inputs

CI

Input Capacitance, Data Outputs

Co

vee

.Max

= 5V
Vo = 0
VI = 5V
= OV
fclock = 640 kHz
TA = 25·C
TA = 25·C

3

,...A

-3

,...A

1

,...A

-1

,...A

0.3

3

mA

10

15

pF

10

15

pF

VI

Resistance from Pin 12 to Pin 16

Analog Multiplexer

Typ

Units

Vo

loz

Output Current

--

Limits

Condltl.ons

1

1000

kn

= 5V; TA = 25·C

Parameter

Symbol

Limits

Conditions
Min

Channel On-State Current(4)

Ion

Channel Off-State Current

loff

Typ

Units
Max

VI = 5V,
fclock = 640 kHz

2

,...A

VI = OV,
fclock = 640 kHz

-2

,...A

Vee = 5V,
TA = 25·C, VI
Vee = 5V,
TA = 25·C, VI

= 5V, VI
Vee = OV, VI
Vee

= 5V

10

200

nA

= OV
= 5V
= OV

-10

-200

nA

1

,...A

-1

,...A
Note:
4. Channel on-state current is primarily due to the bias current into or out of the threshold detector, and it varies directly with
clock frequency.

Operating Characteristics
TA

=

25·C, vee

Parameter

=

VREF+

Symbol

=

5V, VREF'- = OV, fcloCk
Conditions

=

640 kHz (unless otherwise noted)
SDA0808A
Limits

Min
Supply Voltage
Sensitivity

ksvs

Vee = VREF+
= 4.75V to 5.25V,
TA = - 40·C to + a5·C(S)

Typ
±0.05

Max

SDA0808B
Limits
Min

Typ

Units

Max

±0.05

%IV

Linearity Error(S)

±0.25

±0.25

LSB

Zero Error(7)

±0.25

±0.25

LSB

3-4

SDA 0808 A, SDA 0808 B, SDA 0808 N

Electrical Characteristics over recommended operating free-air temperature range, Vee = 4.75V to
5.25V (unless otherwise noted) (Continued)
Operating Characteristics
= 25°C, Vee = VREF+ = 5V,

TA

Parameter

(Continued)
VREF- = OV, fclock

Symbol

=

640 kHz (unless otherwise noted)

Min

Output Disable Time tdis

=
TA =
TA =
Cl =
Cl =

Conversion Time

tconv

fclock

Delay Time, End of
Conversion Output

td(EOC)(9,10)

Total Adjusted
Error(S)

TA

Output Enable Time ten

SDA0808B
Limits

SDA0808A
Limits

Conditions

+25°C

Typ

Max

Min

Typ

±0.25 ±0.5 LSB

±0.5

LSB
±0.5 LSB

-40°C to +125°C

10 pF, Rl

=

=
=

Max

±0.25 ±0.5

-40°C to + 85°C

50pF,Rl

Units

10kn

80

250

80

250

ns

10 kn

105

250

105

250

ns

15

16

15

16

J.l.s

14.5

J.l.s

1.5 MHz(10)

14.5

0

0

Notes:
5. Supply voltage sensitivity relates to the ability of an analog to digital converter to maintain accuracy as the supply voltage
varies. The supply and VREF + are varied together and the change in accuracy is measured with respect to full-scale.
6. linearity error is the maximum deviation from a straight line through the end pOints of the AID transfer characteristic .
. 7. Zero error is the difference between the output of an ideal converter and the actual AID converter for zero input voltage.
S. Total unadjusted error is the maximum sum of linearity error, zero error, and full scale error.
9. For clock frequencies other than 640 kHz, Id(EOC) maximum is S clock periods plus 2 "'S.
10. Refer to the operating sequence diagram.

Functional Block Diagram
START OF CONVERSION

CLOCK

CONTROL & TIMING

8
ANALOG
INPUTS

ENDOF
CONVERSION

SA.R.

8
CHANNEL
ANALOG
MUX

C
N
E

T

3 81T
ADDRESS

JI

8BIT
OUTPUTS

ADDRESS
LATCH
AND
DECODER

ADDRESS
LATCH
ENABLE
REF(-) REF( +)

OUTPUT
ENABLE
0077-2

3-5

SDA 0808 A, SDA 0808 B, SDA 0808 N
Operation Sequence
Clock
Start Conversion

AddreH Latch
Enable

~j\:'5;;;."~_ _ __

-r-r-1'------

Addr...

twlSI

,

I

:
-.-!++-+:
tw(ALE)

~W'Dnab!,

SO" ~50i:::"i~,.j_ _ _ _ __

ts'!..~tttl

Analog Input

Y

Analog Value

:

-=?________

:!::E~~I;np:u~t5~m~~~e==;:;:~::::~·
~:~:~~;OUtPut =±xi
Analog Valu. : =::x-------: i
..

--------

,

End of Conversion ~

:'-jtcl(EOCJ -.:
,-

!cony

:

~r.... ~

Output Ena~e

---------I~,

Latch Outputs

-------------

ien~r-

HIZ State

Ordering Information
Type

Ordering Code

Package

SDAOBOBA

QS7100-AB12B

P-DIP28

SDA0808B

QS7100-AB129

P-DIP28

SDAOBOBN

QS7100-A820S

PLCC-28

3-S

r, ;."
I

~

,

., ......

~
+: fldtS
,

~
10,.
'0"

II~

oon-3

SIEMENS

SDA 0810 A, SDA 0810 B, SDA 0810 N
10-Bit CMOS Analog-to-Digital Converters with
8-Channel Multiplexers
• OV to 5V Analog Input Voltage Range

• Resolution 10 Bits
• Total Unadjusted Error

± % LSB

• No Offset or Gain Adjustments Required

• No Missing Codes

• Latched TRI-STATE Outputs

• Fast Conversion Time (15 p.s)

• Outputs Meet TIL Voltage Level
Specifications

• Single Supply 5 VOC

• CMOS Low Power Consumption, -15 mW

• 8-Channel Multiplexer with Latched
Control Logic

• 28-Pin P-OIP Standard Package or 28-Pin
PLCC

• Easy Interface to All Microprocessors, or
Stand Alone Operation

• Extended Temperature Range
--40°C to + 125°C (SOA 0810 B)

Pin Configurations
(Top View)
AIN3

AIN4

AINS
AIN6

"N'
SOC

(Top View)
AINl

"'IIIIfMl",.JlltNtJ_
,
.I • JI I. I •

AIN1

•

"
"
,."

ADD 1

ADOO

'l

ADD 2

"

Ale

oeN
eLK
vee

I..

21

'0

10
11

REFe.)

u

GNO

13

2,

,.

17

16
15

1st BYTE

l

"NO

,.

eoe

Indent

,.

Z-'(MS8)

,.
,.

/Ift7

5

50<

•

--'" .,

2'
Z-IO(LSB)

lIIII

•

"It

10

W.

11

,,.

bld,YTf
IstBYTE

IndBYTE

AtDO

"

%J

",IVTE

UtlY"

REFe-)

,.

Z5

" 0

0

4

Indl,,--t
0080-4

0080-1

The SOA 0810 is a monolithic CMOS 10-bit analog to digital converter with 8-channel analog multiplexer, with
a single supply of S VOC. The device has a microproce~sor compatible control logic and an 8-bit data bus. It is
a pin-to-pin compatible device to the data acquisition component AOC 0808/0809, with the 10-bit data output
in a two-byte format for interface with 8-bit microprocessors.
The SOA 0810 uses the method of successive approximation with a capacitor network as conversion technique. The converter features a temperature stabilized differential comparator, 8-channel multiplexer for 8
analog inputs and a sample and hold circuit. The device needs no external offset or gain adjustments. Easy
interfacing to microprocessors is provided by 3-bit address latches, 10-bit data-output latches and a 8-bit TRISTATE databus. The temperature range of the SOA 0810 A is -40·C to +8S·C and for the SOA 0810 B
- 40·C to + 12S·C.
Advanced CMOS (ACMOS) process.
@Siemens Components. Inc.

3-7

April 1988

SDA 0810 A, SDA 0810 B, SDA 0810 N

Pin Definitions
Pin No.

Function

Symbol
1st Byte

1 t05
6
7
8
9
10
11
12
13
14,15
16
17 to 19
20
21
22
23 to 25
26 to 28

Analog Inputs
Start of Conversion
End of Conversion
Digital Output Signal
Output Enable
External Clock Input
Pos. Supply Voltage
Pos. Reference Voltage
Ground
Digital Output Signals
Neg. Reference Voltage
Digital Output Signals
Digital Output Signal
Digital Output Signal
Address Latch Enable
Address Inputs
Analog Inputs

AIN3to AIN7
SOC
EOC
2- 5
OEN
CLK
Voo
REF(+)
GND
2- 7,2- 6
REF(-)
2- 8 to 2- 3
2- 2
2- 1
ALE
ADD2toADDO
AINOto AIN2

Functional Description
The Converter
The converter is partitioned into 3 major sections:
An approximately 50 pF capacitor network as a sample and hold circuit, the successive approximation
register and the comparator. The capacitor network
includes a circuit configuration, which provides the
first output for a transition when the analog signal
has reached + 1f2 LSB.
The AID converter's successive approximation register (SAR) is reset on the positive edge of the start
of conversion (SOC) pulse. The conversion starts after the falling edge of the start of conversion pulse
with the next rising edge of the external clock signal.
A conversion process will be interrupted by a SOC
pulse.
The end of conversion output (EOC) will go low after
the rising edge of the start of conversion pulse. It is
set to logical one with the first rising edge of the
external clk after the internal latch pulse. The comparator is an autozeroed fully differential comparator
for a high power supply rejection ratio.

3-8

Symbol
2nd Byte

0

0
0
2- 10
2- 9 (LSB)

AID Converter Timing
After a conversion has been started, the an.alog voltage at the selected input channel is sampled for 4
external clock cycles which will then be held at the
sampled level for the rest of the conversion time.
The external analog source must be strong enough
to source the current in order to load the sample and
hold capacitance, being approximately 50 pF, within
those 4 clock cycles.
Conversion of the sampled analog voltage takes
place between the 5th and 15th clock cycle after
sampling has been completed. In the 15th clock cycle the converted result is moved to the output data
latch. With the leading edge of the 16th clock cycle
the end of conversion signal is set.

Multiplexer
The device provides eight multiplexed analog input,
channels. A particular input channel is selected by
programming 3 address lines (AD2, AD1, ADO). Table I shows the input states for the address lines to
select a channel. The address is latched on the rising slope of the ALE signal. '

SDA 0810 A, SDA 0810

Reading the Conversion Results: On the SDA
0810, the data is read as two 8-bit bytes. The converter's digital outputs are positive true. Data is left
justified and is presented high byte first. The first
OEN high after completing a conversion will enable
high byte (2- 1 to 2- 8 ) on the output buffers, the
second OEN pulse will enable the low byte (2- 9 to
2- 1°), the unused bits of this byte are fixed to
ground. The BYTE CONTROL logic determines
which byte is to be read. On each read a flip-flop is
toggled so that on successive reads alternative
bytes will be output. This flip-flop is always reset to
the high byte at the end of a conversion.

Table 1
Selected
Analog Channel

Address Lines
AD2

AD1

ADO

AIN

L

L

L

AINO

L

L

H

AIN1

L

H

L

AIN2

L

H

H

AIN3

H

L

L

AIN4

H

L

H

AINS

H

H

L

AIN6

H

H

H

AIN7

e, SDA 0810 N

Data Bit Locations:

Absolute Maximum Ratings*
SupplyVoltage(1) (Vccl ..................... S.SV
Input Voltage Range (VI)' .... -0.3V to Vcc

+ 0.3V

Continuous Total Power Dissipation
(at or below 2SoC Free-Air
Temperature Range) ..... " ............. 87S mW

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Free-Air Temperature Range
SDA 0810 A (TA) ............. -40°C to + 8SoC
SDA 0810 B (TA) ............ -40°C to + 12SoC
Storage Temperature
Range (T5tg) ................ - 6SoC to + 1S0°C
Note:
1. All voltage values are with respect to network ground
terminal.

Recommended Operating Conditions
Parameter
, Supply Voltage

vcc

=

SV; T A

Symbol

Positive Reference Voltage

Vcc
VREF+(3)

Negative Reference Voltage

VREF-

Differential Reference Voltage

AVREF = VREF+ - VREF-

Start Pulse Duration

twiSi

Address Load Control Pulse Width tw(ALC)
Address Setup Time
tsu
Address Hold Time

th

Clock Frequency
fclock
Note:
3. Care must be taken that this rating is observed even during power up.

=

2Soc
Limits

, Conditions

Min Typ
S'
4.S

Units
Max
6

Vcc Vcc + 0.1
-0.1
0

V
V
V
V

S
200

ns

200

ns

SO

ns

SO
SO

ns
640

1000

kHz

3-9

SDA 0810 A, SDA 0810 B, SDA 0810 N

Electrical Characteristics
over recommended operating Free-Air Temperature Range Vee = 4.75V to 5.25V unless otherwise noted

Total Device
Parameter

Limits

Conditions

Symbol

Min
High-Level Input Voltage, Control Inputs

= 5V
= 5V

VIH

Vee

Low-Level Input Voltf,lge, Control Inputs

VIL

Vee

High-Level Output Voltage

VOH

10

Low-Level Output Voltage
Data Outputs
End of Conversion

VOL
VOL

Off-State (High Impedance-State)

loz

Output Current

loz

Control Input Current at
Maximum Input Voltage

II

= 1.6mA
= 1.2mA
Vo = 5V
Vo = OV
VI = 5V

Low-Level Control Input Current

IlL

Supply Current

Icc

Input Capacitance, Control Inputs

CI

Output Capacitance, Data Outputs

Co

= -360 p.A

Units
Max

Vee - 1.5

V
1.5

10
10

= OV
fclock = 640 kHz
TA = 25°C
TA = 25°C

0.45
0.45

V
V

3

p.A

-3

p.A

1

p.A

-1

p.A

0.3

3

mA

10
. 10

15

pF

15

VI

1

V
V

Vee - 0.4

Resistance from Pin 12 to Pin 16

Analog

Typ

1000

pF
kn

Multiplex~r

vee = 5V; TA = 25°C

Parameter

Symbol

Limits

Conditions
Min

Channel On-State Current(4)

Ion

Channel Off-State Current

loff

= 5V, 'clock = 640 kHz
= OV, fClock = 640 kHz
Vee = 5V, TA = 25°C, VI = 5V
Vee = 5V, TA = 25°C, VI = OV
Vee = 5V, VI = 5V
Vee = 5V, VI = OV

Typ

VI
VI

10
-10

Units
Max
2
-2

p.A
p.A

200
-200
1
-1

nA
nA
p.A
p.A

Note:

4. Channel on state current is primarily due to the bias current into or out of the threshold detector and it varies directly with
clock frequency.

3-10

SDA 0810 A, SDA 0810 B, SDA 0810 N

Operating Characteristics
TA = 2S0C, vec = VREF+ = SV, VREF- = OV, fclock = 640 kHz, (unless otherwise noted)

Limits
Parameter

Symbol

SDA0810A

Conditions

Min
Supply Voltage Sensitivity ksvs

Vce = VREF+ = 4.7SV
to S.2SV, T A = -40"C to
+8soC(5)

Typ

SDA0810B

Max Min

±O.OS

Units

Typ - Max

%IV

±O.OS

Linearity Error(6)

±O.S

±0.5

LSB

Zero Error(7)

±O.S

±O.S

LSB

±O.S
±O.S

±O.S

Total Unadjusted Error(B)

TA = 2SoC
TA= -40°C to +8SoC
TA = -40°C to + 12SoC

±O.S

LSB
LSB
LSB

Output Enable Time

ten

CL = SO pF, RL

80

2S0

80

2S0

ns

Output Disable Time

10S

2S0

10S

2S0

ns

1S

16

1S

16

,""S

14.S

,""S

= 10 kO
10 pF, RL = 10 kO

~is

CL =

Conversion Time

teonv

fclock = 1.S MHz(10)

Delay Time, End of
Conversion Output

td(EOC) (Notes 9,10)

0

14.S

0

Notes:
5. Supply voltage sensitivity relates to the ability of an analog to digital converter to maintain accuracy as the supply voltage
varies. The supply and VREF+ are varied together and the change in accuracy is measured with respect to full-scale.
6. Linearity error is the maximum deviation from a straight line through the end points of the AID transfer characteristic.
7. Zero error is the difference between the output of an ideal converter and the actual AID converter for zero input voltage.
8. Total unadjusted error is the maximum sum of linearity error, zero error, and full scale error.
9. For clock frequencies other than 640 kHz, Ic!(EOC) maximum is 8 clock periods plus 2 /Jos.
10. Refer to the operating sequence diagram.

Ordering Information
Type

Ordering Code

Package

SDA0810A

067100·A8130

P·DIP28

SDA0810 B

067100·A8144

P·DIP28

SDA0810 N

067100·A8207

PLCC28

3·11

SDA 0810 A, SDA 0810 B, SDA 0810 N

Functional Block Diagram
ADC10
START OF CONVERSION

CLOCK

CONTROL & TIMING
END OF
CONVERSION

S.A.R

8
CHANNEL
ANALOG

8
ANALOG
INPUTS

MUX

C
N
E

T

'3 BIT
ADDRESS

JI

BBIT
OUTPUTS

ADDRESS
LATCH
AND
DECODER

ADDRESS
LATCH
ENABLE
OUTPUT
ENABLE

VRN VRP

0080-2

Operation Sequence

Clock

Start Conversion
Address Latch

Enable
~=uumL-

Address

Analog Input

~~~~~i Output

_____ D____________________________

~---------D-------------------------

~_~~~n~al~og~v~a~lu~.~_____

:::::::J(___________________________
==:::;j'

I+--+--!- Input Stable
:=::txo+j------A-na-,-os--v.-,-ue

, ,
,, ,,

"
,
EndofCOnvenion ~

:..-4
"

tci(EOQ . .'

. !4

'leon.

nil

=:::x-------------------------t,

II ------------~
..,

50'1

Output Enable

Latch Outputs

HIZState

10'1
0080-3

3-12

SIEMENS

SDA 0812
12-Bit CMOS Analog-to-Digital C,onverters
with 4-Channel Multiplexers
• 12-Bit Monolithic Successive Approximation
ADC

• Easy Interface to 8- and 16"Bit
Microprocessors

• Autocalibration Circuitry

• Data Output.in a Two-Byte Format

• No Offset or Gain Adjustments Required,
Autocalibration

• OV to 5V Analog Input Voltage Range

• Total Unadjusted Error ± % LSB

• Digital Inputs and Outputs are TTL
Compatible

• No Missing Codes

• CMOS Low Power Consumption

• Fast Conversion Time (17 !-'-s)

• 28-Pin P-.DIP Standard Package

• Single 5V DC Supply

• Temperature Range - 40°C to

+ 85°C

• 4-Channel Multiplexer with Latched Control
Logic

Pin Configuration
(Top View)

"

-/)0

25,

(~~I~C'

::

'"

I.,.

:3

ACP.jD

"
;:s;

I

:~',j

B
;,~

,"'

c;

OB'

'j

I )~)
I ,.,
,
:-~

0111-1

The SDA 0812 is a monolithic CMOS 12-bit analog-to-digital converter with a 4-channel analog multiplexer. It
needs only a 5V supply and achieves a conversion tim13 of 17 JLs. An autocalibration circuit guarantees a total
unadjusted error within ± % LSB max. Therefore the device needs no external offset or gain adjustments. The
converter features a temperature stabilized differential comparator, and a sample and hold circuit. It uses the
method of successive approximation based on a capacitor network and a 12-bit data output in a two-byte
format. Designed for easy microprocessor interface using standard control signals CS, RD and WR. The 4channel input multiplexer is controlled via address inputs A9 and A 1.
Two converter busy flags are available to facilitate polling of the converter's status. The temperature range of
the SDA 0812 is -40°C to + 85°C. The SDA 0812 is compatible to AD7582 with few pins having different
specifications.
Advanced CMOS (ACMOS) process.
©Siemens Components, Inc.

3-13

April 1988

SDA 0812

Pin Description
Pin
1

Symbol
CAZ

2-5

AINOtoAIN3

6

VREF+

7

VREFDGND

e
9
10-17

Vee
DBOto DB7

10
11
12
13
14
15
16
17

Symbol
(BYSl = HIGH)
BUSY
LOW
LOW
LOW
DB11 (MSB)
DB10
DB9
DBe

18

m5

19
20

WR

21

BYSL

22

BUSY

23

CLK

24-25

AOtoA1

26

CAL (NC)

27

AGND

28

VDD

3·14

~

Description
Special function pin (see output modes, and internal clock operation), connect
pin to a capacitor (2.2 /-LF) and the other side of capacitor to AGND, or connect
Pin CAZ to AGND.
Analog Inputs, channel 0 to channel 3.
Pos. voltage reference input, VREF+ = + 5V.
Neg. voltage reference input, VREF _ = OV.
Digital ground, DGND = OV.
Logic supply voltage, Vee = +5V.
Three state data outputs.
DATA BUS OUTPUT (~, m5 = LOW)
Symbol
(BYSl = lOW)
DB7
BUSY
is an active high converter status flag. It is high
DB6
during a conversion and during autocalibration.
DB5
LOW
Pin 11 to Pin 13 are tied to DGND when BYSL =
DB4
High.
DB3
DB11
is the MSB.
DB2
DBO
is the LSB.
DB1
DBO(LSB)
READ INPUT, active low, is used to read the data outputs In combination with ~
and BYSL.
CHIP SELECT INPUT, active low.
WRITE INPUT, active low, is used to start a new conversion and to select an
analog channel via address inputs AO, A1 in combination with CS low. The
minimum WR pulse width is 100 ns. It is independent of internal/external clock
operation.
BYTE SELECT INPUT, is used to select high or low data output byte in
combination with ~ and RD. See description of Pins 10 to 17.
Converter Status output. BUSY is low during conversion or autocalibration. BUSY
is high after the converter has finished its operation.
.ClOCK INPUT for internal I external clock operation. For external clock operation
connect PIN 23 to a 74 Hc compatible clock source. For internal clock operation
connect PIN 23 to RIC timing components (see clock operation description).
ADDRESS INPUTS, are used to select one of four analog inputs channels, in
combination with ~ and WR. The address inputs are latched with the rising edge
ofWR.
Selected
AO
A1
Channel
Low
Low
AI NO
High
Low
AIN1
High
Low
AIN2
High
High
AIN3
CALIBRATION INPUT. An autocalibration cycle is initiated with CAL = high. The
CAL input also may remain unconnected like a NC Pin. In this case
autocalibration Is only initiated by power on. The minimum pulse width of CAL is
100 ns.
ANALOG GROUND, AGND = OV.
ANALOG SUPPLY, VDD = + 5V.

SDA 0812

Block Diagram
RD

CS

WR OYSL CAL CAl

~~~BUSY
AIND
AIN 1
AIN 2
AIN3

---+
---+
---+
---+

ANALOGMUX

INP
MUX

DOD

OUTP

D07

AD

---+

ADDR
LATCH

&
DECODER

A1

---+
MICRO
CONTROLLER

VRN - - - - - - - - - '
VRP _ _ _ _ _ _---J
0111-2

Functional Description

AID Converter Timing

The SDA 0812 is a4-channeI12-bit CMOS AID converter. Its successive approximation technique provides 17 ,...s conversion time. An autocalibration
technique guarantees a total unadjusted error within
± % LSB maximum over the entire temperature
range. The major components are shown in the
Block Diagram of the converter.

After a conversion has been started (with the rising
edge of WR) the analog input voltage at the selected
input channel is sampled for 5 clock cycles. The external analog source must be capable of sourcing
the current to load the 50 pF sample and hold capacitance within those 5 clock cycles. Conversion of
the sampled analog voltage takes place between
the 6th and 17th clock cycle after sampling has
been completed. The CAZ Pin is not used for normal
operation, therefore it can directly be connected to
AGND or DGND.o

The comparator is a fully differential autozeroed
comparator for a high power supply rejection ratio
and very low offset voltages. The capacitor network
is binary weighted, providing 12-bit resolution. A
Sub-C Network is used to correct linearity-errors in
the Main-Capacitor Network. The correction terms
are calculated by a microcontroller in an autocalibration cycle, started by Power up or an external CAL
signal. The correction terms are stored in a calibration memory. The stability of integrated C-Networks
guarantees the correction terms to be valid over
time and temperature. In the case of a power fail
new calibration cycles will be initiated automatically.
This guarantees the integrity of the correction terms.
Three state output drivers with multiplexer fo( two
byte data format, an analog multiplexer with address
latch and a clock oscillator with external or internal
clock operation complete the functional components
of the device.

An autocalibration cycle is started with CAL = high,
and takes 114 clock cycles. Finally, a normal conversion cycle (17 clock cycles) is added automatically. An external CAL signal is ignored if calibration is
already in progress. The external CAL Signal is
stored if a conversion cycle is in progress, and the
calibration starts after finishing this cycle.
During an autocalibration or conversion cycle each
power supply voltage and each reference voltage
has to be stable. Therefore an internal timer is integrated to provide a waiting period of 58368 clock
cycles between power up and autocalibration function. This timer is not activated by external calibration function.
o Note:
However CAZ serves as an additional programming
pin when selecting the output mode or measuring
the internal clock frequency.

3-15

SDA 0812

Internal Clock Operation

The rise and fall times have to be 200 ns maximum.

The external circuitry for internal clock operation is
shown in Figure 1, C1 may be omitted.

There is no synchronizing between external clock
and any other signal necessary.

Typical Internal Clock Frequency
Versus Temperature
feloeK MHz

23 elK

e,

1.2

I
~

1.1

SDA 0812

0.;. 560pFT

1.0

DGND

0.9
0111-3

O.B

Figure 1
·40

·25

The internal clock frequency only depends on the R1
value.

K
fclock = R1
if R1 = 100 kn.

K

= 1011

The internal clock frequency may be read out on PIN
17 by CS, RD active in combination with CAZ = high
and BYSL =. high. So it is possible to adjust internal
clock frequencies via variations of R1.

External Clock Operation
The required circuitry for external clock operation is
shown in Figure 2.

23 elK

r----

= 1 MHz

~

SDAOS12

125

oC
01"-5

Figure 3

Normal Mode (Transparent)
On the SDA OB 12 the data is read as two B-bit bytes.
The converters digital outputs deliver positive true
logic signals. Data is presented in right justified format (I.e., the LSB is the most right-hand bit in a 16bit word). Two READ operations are required, the
BYSL input determines which byte is to be read. Because the conversion results are held in a successive approximation register the high byte may be
read out before the conversion is finished.
The 4 most significant bits are valid in the 9th clock
cycle after starting a conversion. Valid 12-bit data is
available for reading after the BUSY PIN has gone
high, or internal status flag BUSY (available on PIN
10) has gone low.

Latched Output Mode

T~e

latched ~utput ":lay be activated by writin9.J!
high on DBO (Into an Internal register) with WR, CS
active in combination with CAZ and BYSL PIN high.

I

I

DGND
0111-4

Figure 2
The external clock source has to perform O.B Vmax
for low voltage level and 3.0 Vmin for high voltage
level.
3-16

100

An additional function in reading the data is available
via an integrated data latch, which is transparent in
normal function mode.

r------

CLOCK SOURCE

fCl!(

75

Output Modes

The actual operating frequency of the internal clock
oscillator can vary from device to device by up to
20%. This is due to parameter variations of the
CMOS processes. Therefore for precisely defined
conversion times usage of an external clock generator is recommended.

74 He

50

fclock = 1 MHz

Note that the specifications are referenced to
fclock = 1 MHz external.

COMPATIBLE

25

DBO WR CS CAZ BYSL

Setting Data Latch

High Low Low High High

Enabled

Low Low Low High High

X

Low Low High Low

Transparent
Forbidden! Otherwise
Unpredictable Behavior

SDA 0812
The data latch is set transparent by POWER UP function.
Activating the latch function an internal generated latch enable signal shifts the data from the SAR into a 12-bit
latch. This occurs when BUSY gets inactive (HIGH). The conversion result is valid during the next conversion
cycle until new data is latched. Therefore it may be read out even after starting a new conversion.

Absolute Maximum Ratings*
Supply Voltages(1) (Vee, VDD) ............... 6.SV
Input Voltage Range
All Inputs (VI) ............. -0.3V to Vee +0.3V
Package DiSSipation
(at or below 2S·C Free-Air
Temperature Range) .................. 875 mW

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Free-Air
Temperature Range (TpJ ...... - 40·C to + 8S·C
Storage Temperature Range .... - 6S·C to + 1S0·C
Note:
1. All voltage values are with respect to network ground
terminal.

Specifications
VDD = +SV, VREF+ = +SV, VREF- = OV, DGND
specifications Tmin to Tmax unless otherwise noted
Parameter

OV, AGND

OV,

Conditions/Comments

felK

MHz external, all

- 40·C to + 8S·C

Units

Accuracy
Resolution
Total Unadjusted Error(1)

All Channels, AINO-AIN3

12

Bits

±%
±%

LSB max
LSB max

Differential Nonlinearity

No Missing Codes Guaranteed

Full Scale Error (Gain Error)

All Channels, AINO-AIN3
Full Scale TC is Typically 5 ppm/·C

±%

LSB max

Offset Error

All Channels, AINO-AIN3
Offset Error TC is Typically 5 ppm/·C

±%

LSB max

±%

LSB max

Channel to Channel Mismatch
Analog Inputs
Analog Input Range

VREF = S.OV

CAIN, On Channel Input Capacitance
lAIN, Input Leakage Current
+2S·C
Tmin tOTmax

OtoS

V

50

pFTyp

10
100

nAmax
nAmax

5

V

4t06

V

AINO-AIN3; OV to + SV

Reference Input
VREF (for Specified Performance)

±5%

VREFRange

Degraded Transfer Accuracy

VREF Input Reference Current

VREF = S.OV

mAmax

3-17

SDA 0812

Specifications (Continued)
Voo = +5V, VREF+ = +5V, VREF- = OV, DGND
specifications T min to T max unless otherwise noted
Parameter

OV, AGND

1 MHz external, all

OV, fClK

Conditions/Comments

- 40°C to + 85°C

Units

Power Supply Rejection
Voo

Voo

=

4.75Vt05.25V

±Ya

LSBTyp

VCC

=

+5V ±5%

0.8
2.4

Vmax
Vmin

±1
10

,.,.Amax
,.,.Amax

0.8
3.0
±10
1.5

Vmax
Vmin
,.,.Amax
mAmax

0.4
4.0

Vmax
Vmin

15
±1

,.,.Amax

15

pFmax

Logic Inputs
CAZ (Pin 1), RD (Pin 18),
CS (Pin 19), WR (Pin 20),
BYSL (Pin 21), AO (Pin 24),
A1 (Pin 25)
Vil Input Low Voltage
VIH Input High Voltage
liN Input Current
+ 25°C
Tmin to Tmax
CLK (Pin 23)
Vll, Input Low Voltage
VIH, Input High Voltage
Vll, Input Low Current
IIH, Input High Current

VIN

=

OtoVCC

VCC +5V ±5%

Logic Outputs
DBO-DB7 (Pins 10-17),
BUSY (Pin 22)(2)
VOL Output Low Voltage
VOH Output High Voltage

VCC
VCC

Floating State Leakage Current
(Pins 10-17)

VOUT

=
=

+5V ±5%,ISINK = 1.6mA(2)
+ 5V ± 5%, ISOURCE = 200 ,.,.A

=

OV to Vcc

Floating State Output Capacitance
Conversion Tlme(3)
with External Clock
with Internal Clock, TA

fClK

=

25°C

=

1 MHz

Using Recommended Clock Components
as Shown in Figure 1.

17

,.,.smin

17/20

,.,.smin/max

Power Requirements
Voo

± 5% for Specified Performance

5

VNOM

VCC

± 5% for Specified Performance

5

VNOM

100

Typically 4 mA with Voo

Icc

VIN

=

Vil or VIH

Power Dissipation

WR

=

RD

=

CS

=

BUSY

Notes:

1. Includes Full Scale Error, Offset Error and Relative Accuracy.
2. ISINK for BUSY (Pin 22) is 1.0 mAo
3. Conversion Time includes autozero cycle time.

3-18

=

5V

=

Logic HIGH

7.5

mAmax

100
1.0

,.,.ATyp
mAmax

20

mWTyp

SIEMENS

SDA5200 N
6-Bit Analog/Digital Converter
The SDA 5200 N is an ultrafast AID converter with 6 bit resolution and overflow output.
After cascading, it enables straightforward construction of 7 or 8 bit AID converters, respecitively (refer to application circuit).
Apart from a guaranteed strobe frequency of 100 MHz and an excellent linearity, the
SDA 5200 N is outstanding for a broad analog bandwidth which - from the analog side enables application up to the limit of the Nyquist theorem.
The SDA 5200 N is pin-compatible to the ICs SDA 5010, SDA 6020, and SDA 5200 S
(differing output code in the overflow).
Features
•
•
•
•
•
•
•
•
•
•
•
•

Strobe frequency 100 MHz
6 bit resolution (1.6%)
Overflow output (7th bit) at simultaneous blocking of the remaining outputs~ simple
cascading for 7 bit or 8 bit AID converters
Broad analog bandwidth (140 MHz)
High slew rate of the input stages (typ. 0.5 Vlns)
Processing of analog signals up to the Nyquist limit
Linearity ± 1/4 lSB
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
Power dissipation 550 mW
ECl compatible
logic-compatible supply voltage + 5 V; - 5.2 V

The following versions1) are available upon request:
•
•

IC with a nonlinear conversion characteristic of a given characteristic curve
IC with any output code (e.g. gray code)

1) Conditions upon request.

3-19

•

SDA5200 N

Block diagram

3

~--------------------------------------I
Rl
Rz
________ _ ___
R6l
RiO
Ri5.,
2.

d
I

:'~IR

I,'

I

sf
VlhyO---=+----~
I",

,

Comparator
stages

Strobe

I.

I
I
I

1 st encoding I AND)

2 nd encoding lOR)

8+-- - /
- Vs 0--..:.
1

I

17 o+Vs
I

. Output stages

I

I
____________JI

L
I _________ _

.13- 14- 15

1

D1

3·20

D2

D3

D4 Ds

D6

Do

SDA5200 N

Transfer characteristic and truth table

!

Do 06 05 04 03 02

--

:!: 1/4

01

H

L

L

l

L

l

L

H

H

H

H

H

IH

L

H

H

H

H

H

l

LSB

I--:-

L
/

F
I
L

L

L

L

L

H

L

L

L

L

IL

L

L

H

L

L

L

L

L

L

L

X
0

X
1

/
2

V

!

I

!
i

I

,

,

62

63

I ..
64

Pin configuration

top view
OS2

Do

06

05

04

03 02

01

16

15

14

13

12

11

10

9

3

4

5

6

7

8

2
0S1 + VIR

Pin

1
2
3
4
5
6
7

8
9 to 14
15
16

VIA - VIR Vihy Strobe +Vs -Vs

Symbol
OS1

+VIR
VIA
-VIR
Vlhy

Strobe
+Vs
-Vs

01 to 06
Do
OS2

Function

Digital ground 1
Positive reference voltage (+2 V)
Analog signal input (max. +2 V; -3 V)
Negative reference voltage (-3 V)
Hysteresis contro'l (9 V to +2.5 V)
Strobe input (ECL)
Positive supply voltage (+5 V)
Negative supply voltage (-5.2 V)
Data outputs, bits 1 to 6 (ECl)
Overflow output
Digital ground 2
3-21

SDA5200N

Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Ambient temperature
Junction temperature
Storage temperature

+Vs
-Vs

Thermal resistance
System-air

RthSA

VIA, +VIR' -VIR
V.I,abe
Vlhy
OSI -OS2

TA

~.

Tstg

Characteristics
Power supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at +Vs = +5.0 V, VIA;:;; -VIR
at -Vs =-5.2 V, VIA;:;; -VIR

+Vs
-Vs

Lower
IimitB

Upper
limit A

-0.3
-6.0
-3.5

6.0
0.3
2.5
0
3.0
0.5
70
125
125

V
V
V
V
V
V
°C
°C
°C

85

K/W

-Vs
0
-0.5
0
-55

Lower
limit B

typ

Upper
limit A

4.5
-5.7

5.0
-5.2

5.5
-4.7

V
V

50
55

80
80

rnA
rnA

+VIRmax
5

V
V
V
V
V

500
500

IlA
nA

Is+
Is-

Analog section
Signal input
, Max. input voltage
VI Rmax = I (+ VI Rmax) - (-VI Rmin) I
VI Afor 6 bit resolution
VIA for 1/2 LSB linearity
VIA for 1/4 LSB linearity
Input current
at VIA =+VIR
at VI A < -l'I R
Input capacitance
at VIA < -VIR

VI Amax

-VI Rmin
1.2
2.4

IIA
IIA

0.3
0.6
1.2
150

-500

pF

25

CIA

Reference inputs
Pos. reference voltage
Neg. reference voltage
Reference resistance

+VIR
-VIR
R,ef

25
.
1--3.0
96

1128

1~.5
195

I~

Digital section
Strobe input
H input voltage
L input voltage
H input current
C.-input current

VIH

Vil
IIH
III

Data outputs (100 Q to -2 V)
H output voltage
L output voltage

3-22

VQH
VQl

-1.1
-2.0

1-

1 .1
-2.0

-0.9
-1.7
6
6

1-

0 .9
-1.7

-0.6
-1.6
50
50

1-

0 .7
-1.5

V
V
Il A
IlA

I~

SDA5200N

Characteristics (cont'd)

Lower
limit B

Dynamic parameters
Aperture time
Aperture jitter
Strobe
Signal transition time
Signal transition t'ime
Strobe frequency
Max. slew rate
bandwidth (-3 dB)

typ

2
25
5
12
12

td

tstrobe
td Hold
td Set
'strobe

100
0.5
140

B

17
17

ns
ps
ns
ns
ns
MHz
V/ns
MHz

Input current versus input voltage

Pulse diagram of strobe input
and data outputs
Signal input

Upper
limit A

max

IIA

t

min - I - - + _ - - - - I - - - - + - -

3-23

SDA5200 N

Measurement circuit
Analog ground DIgItal ground
I'"

470Q

'".!.I:!!1"H

Clatch

50Q
1~16

~

~

!.0!l_H_

-o in
(- '"
u

~

• V'R

00

V'A

06

o :E

f--f--- 0.0

*loonf
Analog
Input

.,.

!.~~

'rj'"-::~ 0.6
In

>--

=Fl00nF

Strobe

- V'R

05

IoJkY

04

Strobe

03

• Vs

02

8

- Vs

>--

-

01 9

1

r 50Q

~

7x 100Q

100nF =r ' =rl00nF
Ground plane

Application circuit
7 bit AID converter with SDA 5200 Sand SDA 5200 N

L __
Do

Do

SDA
5200S
-

01

-

- V'R

rt:F
• VIR -

Do
06

SDA
5200N
~

01

AIN Strobe

3·24

1

- VIR

u

O:E

---<

0.5

o in

-

0.4

~!~

~

== l00nF

-( -'"

07
06
05
04
03
02
01

-2V

-( '"u

o :E ~'~
o - f-f

In

0.3
0.2

:!!

o~

~

I--< 0.1

To memory
and computer

SIEMENS

SDA5200 S
6-Bit Analog/Digital Converter
The SDA 5200 S is an ultrafast 6 bit AID converter with overflow output. It has been designed
as terminating device for a 7 bit or 8 bit AID converter comprising several cascaded les
(refer to application circuit), or exclusively for 6 bit operation.
Apart from a guaranteed strobe frequency of 100 MHz and an excellent linearity, the SDA
5200 S is outstanding for a broad analog bandwidth which - from the analog side - enables
application up to the limit of the Nyquist theorem.
The SDA 5200 S is pin-compatible to the les SDA 5010, SDA 6020, and SDA 5200 N (differing
output code in the overflow).
Features

•
•
•
•
•
•
•
•
•
•
•
•

Strobe frequency 100 MHz
6 bit resolution (1.6%)
Overflow output (7th bit)
Broad analog bandwidth (140 MHz)
High slew rate of the input stages (typ. 0.5 V/ns)
Processing of analog signals up to the Nyquist limit
Linearity ± 1/4 lSB
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
Power dissipation 550 mW
Eel compatible
logic-compatible supply voltage + 5 V; - 5.2 V

The following versions 1) are available upon request:

•
•

Ie with a nonlinear conversion characteristic of a given characteristic curve
Ie with any output code (e.g. gray code)

1) Conditions upon request.

3-25

SDA 5200 S

Block diagram

-------------------,

3
~-----------------4:
R,
R2
________ ____

R63

R64

R65

12

I
1

I

I

II

51

I

1

Comparator
stages

Strobe
Register

1

I

1

I.,

1 st encoding I ANDI

2 nd encoding (OR)

8.;...:--1
- Vs 0--.::.

17

---',-'---<:0 + Vs

I

I

I

I ____ _
L

_ ________ ...1I

15
052

3·26

01

02

03

04

05

06

00

SDA5200 S

Transfer characteristic and truth table
00 06 OS

:!:1/4 LSB

01

L

L

L

L

L

H

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

1

~

2

64

62 63 64

VIA

~

Pin configuration
top view
0 52
16

00 06

OS

04 03 02 01

14

13

12

11

3

4

S

6

15

2
051 +VIR

Pin
1
2
3
4
5
6

7
8
9 to 14
15
16

VIA - VIR Vihy Strobe

10

9

7

8

+Vs -Vs

Symbol

Function

OSl

Digital ground 1
Positive reference voltage (+2 V)
Analog signal input (max. +2 V; -3 V)
Negative reference voltage (-3 V)
Hysteresis control (9 V to +2.5 V)
Strobe input (ECL)
Positive supply voltage (+5 V)
Negative supply voltage (-5.2 V)
Data outputs, bits 1 to 6 (ECL)
Overflow output
Digital ground 2

+VIR
VIA
-VIR
V lhy

Strobe

+Vs
-Vs
01 to 06
Do
OS2

3-27

SDA5200S

Maximum ratings

.

Lower
IimitB

+Vs
-Vs

Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Ambient temperature
Junction temperature
Storage temperature

VIA. +VIR• -VIR
Vst;obe '
III hy
OSI-0S2
TA

-0.3
-6.0
-3.5

-Vs
0
-0.5
0

7j
-55

Tstg

Thermal resistance
System-air

RthSA

Characteristics
Power supply
Pos. supply voltage
Neg. supply voltage
Current consumption
at +Vs = +5.0 V. VIA ~ -VIR
at -Vs - -5.2 V. VIA ~ -VIR

+Vs
-Vs

'.

Upper
limit A
6.0
0.3
2.5
0
3.0
0.5
70
125
125

V
V
V,
V
V
V
°C
°C
°C

85

K!W

Lower
IimitB

typ

Upper
limit A

4.5
-5.7

5.0
-5.2

5.5
-4.7

V
V

50
55

80
80

mA
mA

+VIRmax
5-

V
V
V
V
V

500
500

",A
nA

Is+
Is-

Analog section
Signal input
Max. input voltage
VI Rmax = I (+ VI Rmax) - (-VI Rmin) I
VI A for 6 bit resolution
VI A for 1/2 LSB linearity
VIA for 1/4 LSB linearity
Input current
at VIA =+VIR
at VIA < -VIR
Input capacitance
at VIA < -VIR

VI Amax

-VIFlmln
0.3
0.6
1.2

1.2
2.4
IIA
IIA

150
-500

pF

25

CIA

Reference inputs
Pas. reference voltage
Neg. reference voltage
Reference resistance

+VIR
-VIR

R,ef

1-

25
.
-3.0
96

1
1128

~.5
'
195

"

I~

Digital section
Strobe input
H input voltage
L input voltage
H iIlput current
L-input current

Data outputs (100 Q
H output voltage
L output voltage
3·28

VIH
VIL
IIH
IlL

to -2 V)
VOH
VOL

-1.1
-2.0

1-

1. 1
-2.0

~0.9

-1.7
6'
6·

1-

0 .9
":"1.7

-0.6
-1.6_.
50
50

1-

0 .7
-1.5

V
V
",A
",A

I~

SDA5200S

Characteristics (cont'd)

Lower
limit B

Dynamic parameters
Aperture time
Aperture jitter
Strobe
Signal transition time
Signal transition time
Strobe frequency
Max. slew rate
Bandwidth (-3 dB)

typ

2
25
5
12
12

td
tstrobe
td Hold
tdset
tstrobe

100
0.5
140

B

Pulse diagram of strobe input
and data outputs

Upper
limit A

17
17

ns
ps
ns
ns
ns
MHz
V/ns
MHz

Input current versus input voltage

max
IIA

t

min

+-_~

___+-___+-_

3-29'

SDA5200S

Measurement circuit
Analog ground DIgItal ground
.~

I'"

4701'2

t latth

- !.!!.Ii
501'2

-

1"'---"
OSI

r---

.....

16

-~I-

Oszr

~OJ_H_

0-----

• VIR

Do

VIA

06

-C '"uo~

t-- Qo

*100nF
Analog
input

!~~

~

=Fl00nF

~

- VIR

OS

!-Joy

04

Strobe

03

.Vs

02
~

8

-Vs

501'2
100nF=f

01 9

)

7.1001'2

T,I00nF

Ground plane

Application circuit
7 bit AID converter with SOA 5200 Sand SOA 5200 N
• VIR

1-_
DO

Do

SDA
5200S
r---

r--

01

r-

-VIR

r~
+VIR .....

DO

SDA
S200N
~

!
3-30

07
06
05
04
03
02

01

o ~ t---

QS

~t---

Qt.

-c '"u

o ~ t---

Q3,

~I-

Q2

~

J.

=F= 100nF

Q6

-c '"u-

~
~

Strobe

~t--

01

-2V

E~

o ~ I~

Ql

To memory
and computer

SIEMENS

SDA6020
6-Bit Analog/Digital Converter
The SDA 6020· is an ultrafast ND converter with 6 bit resolution. In addition to a
scanning frequency of typically 50 MHz and excellen·t linearity, the SDA 6020 has the
following outstanding features:
•
•
•
•
•
•
•

6-bit resolution (1.6%), simple expansion to 8 bits
± 1/4 LSB linearity
No sample and hold required
Dynamic driving of reference inputs for analog addition and multiplication
ECL compatible (ECL - TIL matching possible, e.g. with SH 100.255)
Low power dissipation 450 mW
Logic compatible supply voltage +5 V; -5.2 V

Maximum ratings
Supply voltage
Supply voltage
Input voltages
Strobe
Hysteresis control
Voltage difference
Operating temperature
Storage temperature

+Vs
-Vs
VIA, +~R' -VIR
VStrobe

VIH
OrOD
Tamb
Ts

3-31

Lower
limit B

Upper
limit A

Unit

-0.3
-6.0
-3.0
-Vs
0
-0.5
0
-55

6.0
0.3
3.0
0
3.0
0.5
70
125

V
V
V
V
V
V
°C
°C

SDA6020

OS2

Pin configuration

16

00 06
15 14

05
13

04 03
12 11

02
10

01
9

top view

2345678
OS1 +VIR

Pin
1
2

Function

OS1

Digital ground
Positive reference voltage « + 2.5 V)
Analog signal input (max. ± 2.5 V)
Negative reference voltage (> - 2.5 V)
Hysteresis control (0 V to + 2.5 V)
Strobe Input (ECL)
Positive supply voltage (+ 5V)
Negative supply voltage (- 5.2 V)
Data outputs, bits 1 to 6 (ECL)
Overflow
Digital ground of output stages

Strobe

+Vs
-Vs
01 to 06
Do

15
16

IoihyStrobe +VS -VS

Symbol
+VIR
VIA
-VIR
VIhy

3
4
5
6
7
8
9 to 14

VIA -VIR

OS2

Block diagram .

r-~f-----------------------------c---,
Overflow
63

r--l----t---<> Do
62

VIA 0----

..go I--+---o
I---t---<> 05

06

til

Memory

-J-. Comparator stages r--

and
encoder stages

-- =
!

04

c5 I--t--!-o 03
I--+---o 02
l----t--o 01

"-II

2

I
I

L__

I

l

I

__. ________ _

I
I

---------~---------~
• VIR

3-32

Vlhy

Strobe

SDA6020

Characteristics

Lower
IimitB

typ

Upper
limit A

4.5
-5.7

5.0
-5.2

5.5
-4.7

V
V

30
55

60
80

rnA
rnA

+VIAmax
5

V
V
V
V
V

800
10
10

J.LA
J.LA
J.LA

35

pF

Power supply
Positive supply voltage
Negative supply voltage
Current consumption
at +Vs= +5.0 V; VIA::; -VIA
at-Vs =-5.2 V; VIA :S:-VIA

+Vs
-Vs
Is
Is

Analog section

TA =25°C; +Vs =5 V; -Vs =5.2 V
Signal input
Maximum input voltage
VI Amax = I (+VI Amax) - (-VI Amin) I
VI A for 6-bit resolution
VI A for 1/2 LSB linearity
VI A for 114 LSB linearity
Input current
at VI A = +VI A in sample mode
at VI A < -VI A in sample mode
-VIA < VIA < +VIA in hold mode
Input capacitance
at VIA < -VIA

VI Amax

-VIAmln

VIA
VIA
VIA

1.2
2.4

IIA
IIA
IIA

-10
-10

0.3
0.6
1.2
200

CIA

Reference inputs
Positive reference voltage
Negative reference voltage
Reference resistance

+VIA
-VIA

64R

2
1-2.5
96

1
1128

~.5
256

I~

Digital section
Strobe input
H input voltage
L input voltage
H input current
L input current

VIH
VIL
IIH
IlL

Data outputs (100 Q to -2 V)
H output voltage
L output voltage

VOH
' Val

I

-1.1
-2.0
5
5

1-

1. 1
-2.0

-0.9
-1.7
30
30

1-

0 .9
-1.7

-0.6
-1.5
100
100

1-

0 .6
-1.5

V
V

J.LA
J.LA

I~

3-33

SOA 6020

Pulse diagram of strobe inputs
and data output

Input current versus input voltage

~xt----------------!

~rA :I

I

fStrobe
I

I
I

I

:

I

j

Strobe Input

Free
run

min

~~~--------+I--------~----

'- VIR
1)

• VIR

undef !ned output levels

Test circuit

Digital ground

• ~ 470Q

or-

~

Do ~____________-..-1_1- - - 0 Overflow

11

05 ,~--------_-t--+-----o
O------------------1~

11
04r-------~~_t_-+---~

o-t-----------+~---i Strobe

03~-----~-+-+-~-+---~

.l.
o---------~~_+_--~I~

m~~

o-________~~_+_--~8-~
CSOQ

11

02r-~~r_+_1+-+.- ~
I

!

0, r9~_+~--r_r_+_1-1I---oLSB

~-----..

l) U[ ) I)

7xl00Q

~------------~~~~~-+~--~-2V

100nF

TT

l00nF

Groundplane
"Lines effected as Microdrlp

3-34

SDA 6020

Circuit example for expansion to 7 bit

i

+VIR

----- VIA

Do

--

06
05

03

~~

O2

I---

0

6 Bit
,-----AID O~
r-

Strobe
-VIR

0, t--

~
+I'IR

Do
VIA

6 Bit

I

AID

I

~-- Strobe

I

-IIjR

0,
05
04
0]

O2 - r-0,

0

----

0
0

1 1

VA Strobe

-VR

3-35

SDA 6020

Circuit example for expansion to 8 bit

L~
V

1
+ VIR

Do

06
05
6 AID 0
4
No.4
03
r- Strobe O2 t - 0, t--VIR

r-:-- VIA

[R

L~

314 VR

.1

>-V

1
00
06
05
6A/0
04
No.3
03
>-- Strobe O2 ,....-. I--<
0,
-VIR
1

....... -

R

L~
V

VIA

~
+VIR
~

r-

[R

VIA

6-A/0
No.2

14VR ~V

[R
Strobe

R

3-36

[J

-

12VR ~

L~

~

+VIR

r

Strobe
-VIR

00
06
05
04
03

~

!)

°2f-- +-

0, t--

j

1
+VIR

00
06
VIA
6A/O 05
04
No.1
03
Strobe
O2
0,
-VIR

J

0~
-U

D.

SIEMENS

SDA8005
8-Bit/7 ns DigitallAnalog Converter
The SDA 8005 is a high-speed D/A converter with splendid dynamic qualities and offers
the following features:
•
•
•
•
•
•

Settling time typo 7 ns
Extremely small glitch area
Digital input register
Data inputs 10 Kand 100 K ECl-compatible
Single power supply -5.2 V
Deglitch control input

Functional description
The SDA 8005 is a high-speed 8-bit D/A converter with ECl-compatible data and strobe
inputs.
The data word is received in the input buffer with the low active strobe. An external
reference voltage source with a reference resistor is needed. At a reference current of
2.5 rnA the full-scale output current amounts to 40 rnA.
The output glitches can be minimized by adjusting the deglitch input voltage between
-2.3 V and -2.9 V. The deglitch input can also be left unwired.

3·37

SDA8005

Pin configuration
(top view)

16 DO (LSB)

GNO

I ref

2

15 01

Oegl

3

14 02

Str 4

13 03

+1

5

12 04

-I

6

11 05

C 7

10 06

VEE

9

8

07(MSB)

Pin description
Pin

Symbol

Function
Ground
Reference current input
Oeglitch input
Strobe
Complementary current outputs
+I: zero current if DO to 07 are High
Stabilization
Supply voltage -5.2 V
Data input 0 (LSB) to 7 (MSB)

1

GNO

2.

I ref

3
4

Oegl
Str

5,6

+1,-1

7
8

9

16to 9

3·38

VEE

DO to 07

SDA8005

Block diagram
+1 -1

11

Strobe Deglitch
VREF ext --I..:=:JI--- Val -

Lower
IimitB

Upper
limit A

-6.0
-3.0
-4.0
-5.2
-1.9

0.3
0
0
0
5
125
85
125.

V
V
V
V
V
DC
DC
DC

85

KlW

7j
-25
-55

TA
Tslg

Thermal resistance

RthJA

Characteristics

Lower
limit B

Analog outputs

typ

Upper
limit A

Static performance
Ratio of full-scale output current
to reference current
Absolute unadjusted error
Integral nonlinearity
Differential nonlinearity
Full-scale temperature coefficient
-25 DC to +25 DC
+25 DC to +85 DC
Zero-code output current
Full-scale output current
Output voltage range
Supply voltage sensitivity

IaFs/lref
ERR
INL
DNL
TC
TC

16
-1
0.401)
0.61)
80
50
6 1)

lao
I aFs
Va
5 vs

-1.4
0.031)

+1 2 )
0.55 2 )
12 )

%
LSB
LSB

120
80
30 3)
40 2 )
+5
0.04 2 )

ppm/DC
ppm/DC
j.lA
mA
V

%/%

Dynamic performance 1)
Output rise time
Output settling time
Adjusted worst case glitch area
Digital crosstalk attenuation
Data
Strobe

3-40

fra
fsa

1.3
7
80

ns
ns
pVs

aOata
"Strobe

154 )
304 )

pVs
pVs

SDA8005

Characteristics

Lower
limit 8

Digital inputs

typ

Upper
limit A

DC characteristics
H input voltage
L input voltage
Input capacitance 07

06
00 to 05
Strobe
H input current

VIH
VIL
C I07
C ID6
C IDO ... 05
C ISt ,

07
06
00 to 05

llH06

Strobe

llHSt'

-1.105
-1.850

-0.810
-1.505
1.2
0.8
0.5
1.5
25
12
6
75

lIH07
lIH 00 ... 05

binary

Input coding

V
V
pF
pF
pF
pF
iJ.A
iJ.A
iJ.A
iJ. A

Switching characteristics
Setup time
Hold time
Strobe time
(see Fig. 1)

tSt,

0.5
2.5
2

llDegl
llDegl
-VOegl

-150
+2.9

tsetup
t Hold

ns
ns
ns

Deglitch input
Oeglitch input current
at VDegl = 2.3 V
at VOegl = 2.9 V
Oeglitch voltage range
Oeglitch voltage (not connected)

200
+2.3
0.5XVEE

VOgl

iJ.A
iJ.A
V
V

Power supply')
Supply voltage
Supply current
Power consumption

VEE
hE
Po

-5.46
98
495

-4.94
105

V
rnA
mW

3-41

SDA8005

Commetnts
1) Measured at:

25°C
VEE =-5.2 V
Full-scale output current la = 20 mA
Output load == 50 n

2) Guaranteed at:

-25°C to +85 °C
-5.46 V to -4.94 V
Full-scale output current Ia == 1 mA to 40 mA

3) Measured at

100°C

4)

Full-$cale output current Ia = 20 mA
VOegl == -2.3 V
VEE ==-5.2 V
~H =;-0.95 V
~L

=-1.6 V

Input signal rise time tr = 3 ns
Switching all inputs at the same time in the same direction (worst
case).
The crosstalk attenuation can be reduced by using other input signals.

3·42

SDA8005

Pulse diagram of the inputs

~r-_ _ _ _ _---,VW____DO-D7

tHald

tSltup mIn

=0,5 ns

tStr min

= 2 ns
= 2 ns

t Ha1d min

Figure 1

3-43

SDA8005

Terminology
Absolute unadjusted error
The full-scale output current with the same reference voltage and reference resistance is
different for different chips. The variation results from the deviation of technology param.
eters. The specification is the maximum deviation from an average value.
Integral nonlinearity
The integral nonlinearity is the maximum deviation of the output of a linear regression
from the output values of all possible input codes.
Differential nonlinearity
Differential nonlinearity is the difference be~een the actual and the ideal deviation between
any two adjacent input codes, this being 1 LSB. A specified differential nonlinearity of
± 1 LSB max. over the entire operating temperature range ensures monotonicity.
Supply voltage sensitivity
The supply voltage sensitivity is the dependence of the analog output current on the
supply voltage VEE with all other parameters or conditions constant. It is specified in %
per%.
Output rise time
The output rise time is the time between the 10% value and the 90% value of Va max. at
the leading edge.
'
Output settling time
'The output settling time is the time from the 50% point of the trailing strobe edge to the
last entry of the analog output signal into an admissible error window of ±1/2 LSB.
The specified value is measured by using a comparator to detect the entry time point
(see fig. 2).
Adjusted worst case glitch area
Glitches which arise from input code switching can be minimized by varying the deglitch
input voltage.
The specified value can be measured under the following conditions:
•
•
•

Input code change from 01111111 to 10000000 and vice versa
Input data are received with strobe
Deglitch input voltage is optimized for switching in both directions

3-44

SDA8005

Figure 2 shows the test circuit and the timing diagram for the determination of the output
settling time.

Ultrafast ECl
comparator

+It--........- - - t

Data input

........,Q:-------.-__ Oscilloscope

SOA 8005
00-07

-I
100 Q

100 f!

•

'--""""-<>-2 V

1. 5 kQ
Variable
J-~~-[=I---o comparison voltage

220 Q

Tl00nF ..

11 lSB

--

______ 1_ +1

r------r
II
I

hlSB

-1.------- --

I 1

td comparator
delay time

-f----=:ttd- ,.:.1-+1-+----comparator circuit 1
,..output
I r----- comparator circuit 2
output·

1
-------1111

II

comparator circuit 3
output

Figure 2

3-45

SDA8005

Application instructions
Board with at least one ground area in its entirety.
- Ground pin should be connected very close to the large grQund area by using contact
studs or by direct soldering.
-

Voltage supply must be blocked directly attheVEE pin by using a 100-nF ceramic
capacitor (preferably small chip capacitors).
The analog outputs should be loaded with 50 0 as near as possible to the package.
Each of the DC voltages
ripple and noise.

(VEE.

DEGL. V's,) has to be checked for its suitability as regards

If a D/A output is connected to the 50-0 input of a scope, an attenuator should be
arranged on the D/A converter side of the connecting line to prevent the reflection from
the oscilloscope from seeing the practically open line termination (output impedance of
D/A c«;mverter approx. 20 kO); the ground connection between the board and the
instrument should have a very low impedance.
- To minimize the crosstalk of used strobe to' the output you can place a voltage divider
at the strobe input to form an RC filter in combination with the input capacitance (see
figure).

strobe

-2V

3-46

SDA8005

Figure 3 shows an application where the output signal is transmitted over a 50-0 line to
a receiver with a 50-0 input, possibly a high-speed oscilloscope.

I rel may be adjusted by varying
1 kO.

V,el

Alternatively Rrel can be changed with

I~

between 0 V and 2.5 V, reference resistor Rrel being
V,el

constant.

Data bus
____________
_ _ _ _ _ _ _ _ _ _- , \
~A~

SDA 8005
GND

I ret
2

Degl
3

Str
4

+1
S

-I
6

7

8
[(

[8

H

10nF 100nF

-S.2V
Vr.t=O-+2.5V

son
SOQ strobe line

Receiver

Figure 3

3-47

SDA8005

Here the strobe input is connected to a- voltage divider, which forms an RC filter together
with the input capacitance, and in this way reduces the digital crosstalk from strobe to
output. The 100-0 output line from +1 is terminated at both ends.
The high maximum, full-scale output current in this case also allows an acceptable voltage
range.

Data bus
II

/

\
I ,

SDA B005
GND

str
4

+/
5

C
7

-/

6

VEE

8

C(

Ca

H

10nF 100nF

-5,2 V

- 2V---*--;::=:J---.

1000 line
1000

SOQ strobe line

Figure 4

3-48

Receiver

SIEMENS

SDA8010
8-Bit Analog/Digital Converter
• Maximum Conversion Rate> 100 MHz

• Extremely low Error Rates

• 8-Bit Resolution

• Balanced Input Voltage Range

• 6.3 Effective Bits (FAN

=

30 MHz)

• ECl 100k Compatible Output Data

• Nonlin~arity < % lSB
• Excellent large-Signal Bandwidth

• low Power Dissipation
• Small 24-Pin Ceramic Package

Pin Configuration

Pin Definitions
Pin

(Top View)
Vu

I[

GND

2[

Vee

l[

Sir 1

4[

J21 07
J22' 06
J21 os

.V,.t s[

]20 04

.v,.., .• 6(
AIN

7[

a[
9[
Yrtr...
v,., IO[
"V"f,. 11[
Sir 2 12[
AIN

824 GNO 1

] 19 01

pIa

02

Pl7 01
P 16 DO

PIS
P14

p11,

Symbol

Function

Negative Supply Voltage,
1
VEE
Analog Section
2
GND
Ground
3
Positive Supply Voltage,
Vec
Analog Section
4
STR1
Strobe Signal 1
5
+VREF .pos. Reference Voltage
6
+VREF,S Pos. Reference Voltage Sense
7
Analog Input
AIN
8
AIN
Analog Input
9
VREF,M Center Tap of Voltage Divider
10
-VREF Negative Reference Voltage
11
-VREF,S Negative Reference Voltage
Sense
12
STR2
Strobe Signal 2
Negative Supply Voltage,
13
VEE,D
Digital Section
14
Positive Supply Voltage, Digital
Vcc, 0
Section
15
GND
Ground
16 to 23 DOtoD7 Digital Output Signal
24
GND1
Ground Connection for Output
Emitter Follower

~

ONO

Vee,.
Vu ••
0152-1

The SDA 8010 is an ultrafast AID converter according to the parallel principle, with a resolution of 8 bits and a
guaranteed strobe frequency of 100 MHz. The device is capable of digitizing analog signals with full scale
(± 1V) frequency components up to 50 MHz at a power consumption of typically 1.3W. Due to the symmetric
input voltage range it can be driven directly by a customary 50.0 source.

@SiemensComponents,lnc.

3-49

May 1988

SDA 8010

Block Diagram
r------------------~---------... V,.."I

R,

-v,.,

R..

CH-C:J-"T

-------------------------,

,{:::l-......-r:::'':}4."T-It:::jf-.-c'h----------,r--r::lI-1-C~_I_o.v...

I

I

I
I

(OIIpIIralar

(OIIJIIII'GIW

1-64

65-Ul

I
Tit.

-\-eVc<
I

~GNO
I
I

I

I

-t-oV".o
I
I
TVII.o
.-~'-

______~__~~~~________~~____~

II

I
I
IL __
Strobt 1

•

-

-t;~o
I

II
I "GND1
I

----------------~

Strobt 2
0152-2

Functional Description
The SDA 8010 is an ultrafast AID converter according to the "flash" or parallel principle: A field of 255
comparators simultaneously compares the analog
signal with 255 reference voltages spread linearly
over the input voltage range. The result of this comparison, delivered in the so-called thermometer
code, is converted into \:>inary representation by
three encoding stages and is then available as a
digital signal with Eel levels at the outputs (See
Block Diagram).
An individual comparator consists of a differential
amplifier and a masterI slave register stage. They
are activated alternately by means of two strobe signals STR1 and STR2, thereby sampling the analog
signal and holding the corresponding logical state.
The sequence of the conversion process is given in
the pulse diagram.

3-50

During the l phase of STR1, the a,nalog signal is
compared with the reference voltages. With the rising edge of STR1 the result of the comparison is
passed into the first register stage and held there
until the falling edge of STR1. Towards the end of
this hold period the signal is accepted into the second flipflop with the l phase of the second strobe
STR2 and stored with the riSing edge. After a delay
teI,a this data appears at the output and remains valid for the period tv,a.
Driving the converter's analog input is an easy task.
Due to the ground-symmetrical input voltage range
and the low input capacitance, the converter can be
operated in a customary 50n system without any
preamplifiers or level shifters. Nevertheless, lower
impedance driving would be a means for further improving the device's specified dynamic parameters.
Two input pins AIN ensure low lead inductance. The
internal reference voltages are generated by an

SDA 8010
on-chip resistor string. The potentials at its end
pOints. + VREF and - VREF. respectively. determine
the input voltage range which is resolved with an
accuracy of 8 bits. Additional sense pins + VREF S
and -VREF,S allow compensation of voltage drops
across parasitic resistances at top and bottom of the
string. The assignment of the digitaL output code to
the input voltage is shown in the transfer characteristic. As no overflow function is provide~, the output
will remain at a value of 255 when the reference
voltage range is exceeded.
Connection VREF,M only serves for RF decoupling;
no additional adjustment is required for maintaining
the specified accuracy of ± 0.5 LSB.
The use of two supply systems. Vee, VEE and
Vee,D. VEE,D and an additional ground Ii~e GND1 for
the output stages reduces the mutual mfluence of
analog and digital signals. Additionally, the separate
return of the analog signal ground line is recommended (See Test Circuit).

Strobe Timing
Symbol

(Note 1)
Min

Typ

Units

tSTR1

4

5

ns

tsTR2

3

3.5

ns

tse! Up, STR2

-2.0
(Note 2)

-1.5
(Note 2)

ns

tHOLD,STR2

2

ns

Notes:
1. This is the recommended strobe setting for operation at
100 MHz. At lower strobe frequencies the timing more and
more becomes uncritical. Below 75 MHz complementary
strobe signals with a duty cycle of 50% may be used.
2. Negative values of Iset up, STR2 indicate, that the rising
edge of STR2 should appear aiter the falling edge of STRt.

Pulse Diagram

0152-3

3-51

SDA 8010

Absolute Maximum Ratings·
Positive Supply Voltages
(Vee, Vee, D) •.•.••..•.•••.... -0.3V to + S.OV
Negative Supply Voltages
(VEE,VEE,O) ................. -S.OVto+0.3V
Reference Voltages (Note 1)
(+VREF, -VREF .. · ..... ·.;··. -2.5Vto +1.5V
Analog Input Voltage (VAIN) ....... - 2.5V to +: 1.5V

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may' affect device
reliability. '
'

Digital Input Voltages
(VSTR1,VSTR2) ........... '.' ....... -3.5VtoOV

Storage Temperature (Tstg) ........ : ... : ... 125°C

Output Current (100-107)' ..•.....•.....•... 20 mA
Junction T ~mperature (Tj) ................. ',125°C

Ambient Temperature (TA)
(Without Dissipator) . : ................. : .. 50·C
Thermal Resistance Junction-Air
,(Without Dissipator) ......,............. 50 KIW
Note:
1. + VREF always has to be more positive than - VREF.

Electrical Characteristics
vee, Veea

=

5V ±5%; VEE, VEE,O

=

Parameter

-4.5V ±5%; 25°C

Symbol

< Tj :;;; +125°C
Limits

Conditions

Typ

Min

"

Power Supply
Pas. Supply Current, Analog

Units
Max

95

Icc

Pas. Supply Current, Digital

lee,o

85

Total Pos. Supply Current

Icc + Icc, 0

180

Neg. Supply Current, Analog

lEE

70

Neg. Supply Current, Digital

IEE,O

20

Total Neg. Supply Current

lEE + lEE, 0

Power Dissipation

Po,

Permissible Supply
Voltage Difference

AVcc,AVEE

mA
mA
200

mA
mA
mA

90

100

mA

1.3

1.5

W

700

mV

Reference Inputs
+ VREF, - VREF

-2

Total Reference Resistance

RREF

105

Temperature Coefficient of
Reference Resistor

Te

Reference Voltages (Note 1)

150
3

x

1

V

190

.n

10- 3

11K

Analog Input
Input Current (Note 2)

II

VAIN:2: +VREF
VAIN:;;; -VREF

Input Capacitance (Note 3)

CAIN

VAIN:2: +VREF
VAIN:;;; -VREF

3-52

700
1

150
45
55

p.A
p.A
pF
pF

SDA 8010

Electrical Characteristics (Continued)
Vee, Veeo = 5V ±5%; VEE, VEE,D = -4.5V ±5%; 25°C
Parameter

Symbol

< Tj

~ +125°C

Limits

Conditions
Min

Typ

Units
Max

Strobe Inputs
Input High Voltage

-1.165

VIH

Input Low Voltage

Vil

Input High Current

IIH

Input Low Current

III

V

2

VSTR = VIH
VSTR = Vil

Max. Strobe Frequency

fS;r. Max

Aperture Delay
Aperture Jitter

-1.475

V

30

p.A

40

nA

125

MHz

fd, ap

1

ns

tjit

15

ps

100

Data Outputs
Output High Voltage

VOH

100.0 to '-2V

-1.025

-0.880

V

Output Low Voltage

VOL

100.0 to -2V

-1.810

-1.620

V

Signal Transition Time

td,01 (Note 4)
td, 02 ,(Note 5)

10.5
14

ns
ns

"

Time of Valid Output
Data (Note 6)

fSTR = 100 MHz

tv, 0

4

6

ns

Notes:
1. +VREF always has to be more positive then -VREF.
2. The input current is linearly dependent on the input voltage.
3. In good approximation the dependency on VAIN is linear (See Figure 2).
4. Delay from the rising edge of STR2 to the begin of validity of the associated output data. The typical temperature dependency is given in Figure 3.
5. Delay falling edge of STR2/0utput data.
6. Time interval, during vyhich the conversion of a 30 MHz 2 Vpp signal at 100 MHz sampling rate yields an SNR of more than
40 dB. The typical temperature dependency is given in Figure 3. Note the variation of the position of this period with
temperature.,
Characteristics include the guaranteed distribution boundaries of the values which are maintained by the
integrated circuit in the specified operating range. The typical characteristics are mean values which are
expected from manufacture. Unless otherwise specified, the typical characteristics are valid at T A = 25°C.

Transfer CharacteristiC
07 06 05 04 03 D2 01 00
H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H' H

H

L

H

%

,

.~

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

..J'
1

/

/

X
0

%

..

'L
2

-

253 254 255 256 V,/L 56

bl

0152-4

3-53

SDA 8010

Conversion Characteristics

vee, vee, D =

SV ±S%, VEE, VEE, D = -4.SV ±S%; 2S"C

Parameter

Symbol

< Tj <

Conditions

+12S"C

Min

Typ

Max

Units

O.S

LSB·

O.S

0.6

LSB

Static Nonlinearity (Note 1)
Integral Nonlinearity

INL

aVREF

Differential Nonlinearity

DNL

aVREF

= 1.SV
= 1.SV

Dynamic Performance (Note 2)
Large Signal Bandwidth

fads

Signal-to-Noise Ratio

SNR

fAN
fAN

Total Harmonic
Distortion

THO
THO

fAN
fAN

Effective Bits

Neff

fAN
fAN
fAN

MHz

SO

= 30 MHz
= 4SMHz
= 30 MHz
= 4SMHz
= 1 MHz
= 30 MHz
= 4SMHz

40

6.0
'

43
3S

dB
dB

-43
-30

dB
dB

7.4
6.3
4.S

Notes:
1. The actual transfer characteristic is measured by means of the well-known servo loop principle at both low sampling rates
(100 'kHz) and slow strobe edges (>500 ns).
2. Dynamic measurements are performed at 100 MHz sampling rate using the typical strobe timing. All specified parameters
are derived from the FFT of the converter's response to a full scale (2 Vpp) sine wave input. The analog source impedance is
25n (50n line with 50n termination). The test circuit is shown in Figure 1.
.

Definition of Terms

Large Signal Bandwidth

Static Nonlinearity
Deviation of the actual transfer characteristic (output
code as a function of input voltage) from that of an
ideal ADC. It is expressed in terms of the measured
transition voltages Vi (input voltage, at which the
output code transition (i -1) -- i occurs):
Integral nonlinearity INL-maximum deviation of the
mean input voltage associated with any output code
from the ideal value (in LSB), so
INL = max 1 (Vi + 2VI + 1 - ( -VREF) ) X
256

'I

Differential nonlinearity DNL-maximum deviation of
the input voltage range associated with any output
code from the ideal value (in LSB), so
=

max 1(Vi+l - VI) X +VREF

~~-VREF) -

11

Given values of INL and DNL are related to a reference voltage range a VREF = (+ VREF - (- VREF»
of 1.SV.

3-S4

Signal-to-Noise Ratio SNR
Energy ratio (in dB) of the fundamental to the sum of
all other spectral components except harmonics in
the spectrum of the quantized representation resulting from the conversion of a 2 Vpp input sine wave
at 100 MHz sampling rate.

+VREF - (-VREF) - I

DNL

That frequency of a sinusoidal 2 Vpp input Signal, at
which the amplitude of the signal derived from digital
output data has decreased by 3 dB compared to the
low-frequency value. The measurement is carried
out at a sampling rate of 100 MHz in a son system.
As this impedance together with the input capacitance forms the main limitation, bandwidth could be
further increased by driving the input from a lowerimpedance source.

Total Harmonic Distortions THD
Energy ratio (in dB) of harmonic distortions (mainly
resulting from 2nd and 3rd order harmonics) to the
fundamental spectral component (see SNR).

SDA 8010
N

Effective Bits

_ SNRT [dB] - 1.8

6

elf -

Resolution of an ideal converter that would give a
quantization noise equal to the total noise and distortions produced by the tested device. It is related
to the total SNR (including harmonics) by

"

with SNRT

=

-10 log [ 10

SNR
-10

-THD]
+ 10 10

Diagrams
Analog Input Capacitance
versus Input Bias Voltage
pF (+VREF = 1V; -VREF = -1V)

2
10

T

..- ~

I, ~

...- l- I- i -

50

-1

o

o
o

+4V

20

40

60

....

---

Iv

45

-

80

100

12O·C

-7,
0152-6

0152-7

Figure 2

d8
2

Figure 3
Signal-to-Noise Ratio SNR
and Harmonic Distortions THD2, 3
III versus Analog Frequency

Amplitude Response versus
Analog Frequency

~

d8
0

SNR

f

. . . r-."

40

rho

-30

20
-6
10"'

10'

0152-8

0152-9

Figure 5
a) Including voltage drop across source impedance
(250)
b) Without voltage drop across source impedance
(250)
Figure 4

3-55

~

i

<»

(")

""'"

,.100QY

v"

V"

LTiiNo1

Q0 I000t :::'10

.-2Y·

;::;

Baad

~

ReI Yallagel-l,lVI

C,
61()

~
C

07

6NO -

06

Vee

I

O!

Hast (a,"put.r

-+-Cs'
I +C,

:!!

CD
II:

....Cil
low DlStar"an
RF Saurc.

2 it:
I
r
C,

K.I'IR

Voltag.
S.ur,. S'

.J.

==

,..e,'

• VAfF

O•

.VAfFs

03

A IN

02

AIN

01

V.'M

DO

-VAlF

6NOI

-Vlrfs

Vcco

~
o

100 "Hz

~:2

V"ol

Perfo,,"ng
OSP I FFT , OFT)

:'>-+-

E(l RAM
hlK

'"

I +C,,_ f.
+C,
~

,..e.
•

'i:fD

( .......ratars
AD 96.5

-2V

C. (, to (" 100 nF (h,p Capa,,'a ..

0152-5

en

g

!....
Q

SDA 8010

Diagrams (Continued)

Ordering Information

Effective Resolution Neff
versus Analog Frequency

Type

Ordering Code

SDA8010

Q67000-A2566

BIT
8
Neff

7

r

6

"'- ~

~

'\,
\

5

\

4

o

10

20

30

40

50

60 MHz

-Fan
0152-10

Figure 6

3-57

SIEMENS

SDA 8020
Data Acquisition Shift Register (DASR)
• Cascadable, thereby Automatically
Decreasing the TTL Clock Frequency

• a-Bit x 4 Shift Register
• ECL-Serial or TTL-Parallel Loading

• Two Clock Outputs, TTLCLK and W, for
Easy Handling

.125 MHz Shift Clock Frequency Typically
• Latches for Parallel TTL Input/Output Data

• Interface between High Speed ECL and
Slower TTL-Circuits

• TTL-Compatible Control Pins

• Power Consumption Typically 1.5W

Pin Configuration
(Top View)
o

0

0

0

DGDODDDDDD

0'

)

4

"

I

I

7
,

N
0

2

1 6167'"

,
GNO!

•

7

5"

3

0
]

o

1
3

2
1

)
]

..
]

5
1

646

6
1

1
1

"

veel
5TR

CASI

nLCLK

CASO

vo

CAse

VI

DING

oouro

DIN!

DOUTt

DOUT2

OlN2
DINl

OOUTJ

DIN4

ooun

DINS

DOUTS

DIN6

DOur,

01.7

DOUT7

VEE

"0

selK

010(

HOLD
GNOI

GND2

DDDDDOODVDDDDDOOD
76543210(7654]210
2 2 2 2 2 2 2 2 ( 4 4 4 4 4 4 .. 4

0113-1

The OASR SOA 8020 with ECl signal compatble inputs is capable of DEMUlTIPLEXING an 8-bit wide data
stream with a clock rate of up to 100 MHz into four parallel 8-bit TIL data channels with a clock rate of one
fourth of the serial clock. In a second operating mode a MULTIPLEX function combining four 8-bit wide TIL
data channels into one 8-bit ECl compatible channel with up to 100 MHz clock rate is provided.
For the circuits, descriptions and tables indicated no responsibility is assumed as far as patents or other rights
of third parties are concerned.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Liability for patent rights of third parties for components per se, not for circuitries/applications.
@Siemens Components, Inc.

3-58

May 1988

SDA 8020

Basic Configuration
PIN 68-61

PIN 34·27

PIN 9-2

II ll.

PIN 23
PIN I.PIN 10
PIN 26. PIN44
PIN 3S. PIN60
PIN IS·22

~
--+

PIN4]']6

II II

Do, 071
Do2 072
VEE
GND.GNDI.
GND2.GN03
VCC.VCCI

DoJ On

000 0"

W
nLCLK
DOUTO... 7

DIN 0... 7
CASI

CASO

EIO

SClK

PIN 47

REs HOlD

DIRC

VO

VI

STR

~
~
~

PINSS-48

~
PIN 24

CASC

PIN2S PIN 46 PINS7 PINS6 PINS9 PIN I.

P!NII
II

SCLK

"

V

/

TTL
·2V

·2V

Note:

0113-2

1. Only at multiplexing mode.

Pin Definitions and Functions
Pin

Type

1
9-2
34-27
43-36
68-61

Symbol

1/0

GND
TTL
TTL
TTL
TTL

10

D01- D71
D02- D72
D04- D74
D03- D73

Function
TTL Data Ground

1,0
1,0
1,0
1,0

GND1

These are the 32 parallel TTL inputs or outputs (dependent c;m the
DIRC input) of the si~gle shift register cells. The fanout of these
outputs is 2 TTL loads.
EClGround

11

TTL

RES

I

By activating this input (low active) all 32 shift register cells ar&
cleared and the c!2,ck generator is reset (DOUTO-DOUT7 = low,
TTlClK = low, W = High).

12,13

-

CASI,CASO

1,0

Cascading in, Cascading out (see Figure 2): These two pins control
in connection with the Cascading control input the TTL-Clock rate
and internal strobe timing. Used only to establish the clock loop.
They don't provide ECl compatibility.

14

TTL

CASC

I

Cascading Control: The required logic level at this input depends
on the cascading configuration (see chapter "Cascading" and
Figure 2). A single chip configuration requires a high level.

15-22

ECl

DINO-DIN7

I

ECl data input byte

24

ECl

SClK

I

The single shift register cells are clocked by this signal. Data
pending at DINO-DIN7 are transferred with the falling clock edge.

25

TTL

HOLD

I

A logic low at the HOLD input inhibits the shift clock and sets the
32 parallel liDs into the high impedance state. The register is
inactive.

VEE

23

26

GND2

Negative supply voltage; ECl section

TTL ground; clock and control section
3-59

SDA 8020

Pin Definitions and Functions (Continued)
Pin

Type

Symbol

Function

I/O

35

VCC

Positive supply voltage; TIL data section

44

GND3

Ground for ECl output emitter followers

58

TIL

TIlClK

0

The frequency of the TIL-Clock in single chip operation is % of the
shift clock frequency. In a cascaded configuration the TIL-Clock
frequency is automatically decreased.

46

TIL

DIRC

I

A logic high on the DIRC configurates the DASR for parallel in/
serial out (multiplexing, parallel loading), and a logic low for
serial in/parallel out (demultiplexing, serial loading) operation.

47

ECl

EIO

1,0

Enables the internal data transfer from the latches to the shift
registers in multiplexing mode. In this mode the EIOs provide
internal timing information to all cascaded DASRs. This pin must
be connected to - 2V via 1k resistor (see Figure 2). In
demultiplexing mode the EIO pin has no influence on internal
timing and could be left open.

55-48

ECl

DOUTO-DOUT7

0

ECl data output byte. Data are transferred to the output on the
falling SClK edge.

56,57

TIL

V1, VO

I

With VO, V1 one of four possible delay times of the W signal'is
selected.

45

TIL

W

0

The W output has the same frequency as the TIlClK but other
duty cycle (% in single chip operation). It could be used as the
write or chip select siQnal for high speed MOS SRAMs which are
placed at the parallel Inputs/outputs. It can be delayed in multiples
of shift clock periods programmable by VO, V1 (see Programming
Table for VO, V1 below).

59

TIL

STR

I

The four 8-bit data words are latched in the first input/second
output latch by the Strobe. A high strobe level makes these latches '
transparent.

VCC1

60

Positive supply voltage; TIL clocks and control signal section.

Programming Table for VO, V1
VO

V1

DelayofW

0

0

o SClK-Period

0

1

1 SClK-Period

1

0

2 SClK-Periods '

1

1

3 SClK-Periods

Circuit Description
The DASR contains eight parallel 4-bit long shift registers, each of them with two internally cascaded
level-operated input/output latches. The device has
8 ECl compatible serial inputs and outputs and 32
parallel TIL compatible common inputs/outputs.
Beside the data inputs and outputs the device is

3-60

equipped with 7 mode control inputs and it provides
2 clock signals which especially support the use of
the DASR together with fast static MOS RAMs in a
data acquisition system. All these inputs and outputs
are TIL compatible.
The clock section comprises a 1-bit x 4 shift register
whose output (CASO) is fed back to its input (CASI)
via the external clock loop. If the cascade control
input (CASC) is set to H a single pulse is written into
the first shift register cell. When HOLD is released
this single clock pulse is moved around the clock
loop and all timing signals are derived from this
pulse.
The DASR is intended primarily as an interface between a high speed AID or D/ A converter and the
memories in a data acquisition or waveform generating system. Further applications are high speed logic
analyzers and digital word generators.

SOA 8020

Operation Mode

Parallel In/Serial Out

The OASR has two distinct operation modes, selected by the OIRC. For avoiding excessive power dissipation those circuit parts, which are unused in one
mode, are switched off.

Synchronous parallel loading is accomplished by applying four 8-bit TIL data words at 001-074 and
taking the STR high.
Every fourth SCLK-period, beginning with the 6th
of SCLK after starting operation with a
high HOLO, the second input latch is transparent for
one SCLK-cycle. With the next falling edge of SCLK
the data are written into the shift register cells. The
first valid data at OOUT appear not before the 8th
falling edge of SCLK from the beginning onwards.
Those data pending at 004-074 are shifted out first
and those at 001-071 at last within a TILCLK eycle. For getting defined starting conditions at OOUT,
DIN should be set to logic low. The setup and hold
times tS,O,SCLK, tH,O,SCLK apply ~nly if the first input
latch is made transparent by setting STR to H.
fallin~e

Serial In/Parallel Out
After activating the OASR by asynchronous RES
and HOLD (see Figure 3 for recommended HOLO,
RES-timing), the 8-bit wide ECL data words (present
at 0INO-0IN7) are loaded synchronously into the
register by the falling SCLK edge. Shortly after every
fourth trailing SCLK-edge the content of the single
shift register cells are strobed into the first output
latch by an internally created clock. These four data
bytes appear at the outputs (001-071, 004-074)
after they are passed to the second output latch by
the external STR signal. This latch can be also made
transparent by setting STR to H or not connecting
this pin. The first acquired data byte appears at
004-074, the second at 003-073, the third at
002-072 and the fourth at 001-071. Oue to the
inherent skew of the latches a falling edge of the
external STR must not appear during a short interval
(tH STR 0) after every fourth SCLK period (because
output 'latch 1 is just made transparent; see Figure
6).
An acquisition cycle is finished by a negative HOLO
level, which is internally synchronized first with the
leading TILCLK edge and second with the leading
Wedge. This double synchronization eases stopping the acquisition on a well-defined sample (see
application example, Figure 10).
There are a few possibilities of the TILCLK-waveform at the end of an operation cycle depending on
the delay of W (see Figure 3). W remains high after
stopping the OASR. When inhibiting SCLK by HOLO
the TIL data outputs change to the high impedance
state.

In either operating mode the first rising edge of the
TILCLK appears two falling edges of shift clock after activating the OASR. The first W pulse with a
duration of one SCLK cycle and a delay programmed by VO and V1 is provided after the third
falling edge of SCLK.

Cascading
The ability to cascade the OASR enables lower TIL
data rates in connection with the advantage of a
100 MHz shift clock. By cascading the OASR the
CASO of one device must be connected with the
CASI of the next. This clock loop is closed by connecting the CASO of the last OASR with the CASI of
the first one. Furthermore the Cascading control input (CASC) only of one OASR is set high (see Figure
2). The position of the OASR with a high CASC input
determines the moment of the internal strobes for
transferring data to the second input latch and to the
single shift register cells, in parallel in/serial out
mode (see Figure 5). The first internal strobes appear at the same time as in single chip operation
and their period depends on the length of the shift
register cascade. In a system with cascaded OASRs
the first edge of W or TILCLK is offered at that
OASR with CASC = H. The Wand TILCLK signals
of the other SOA 8020s are provided in such a succession as they are interconnected via CASI, CASO.

3-61

SDA 8020
TTLCLK period a STR pulse with a duration of maxi·
mal 4 SCLK periods must be used, e.g.: W (see Fig·
ure 4). The signals at the EIOs are -for internal use
only (see Figure 2).

The time delay between the rising edges of the
TTLCLK signals is four SCLK periods. In parallel inl
serial out mode all EIOs must be tied together and
connected to -2V via a 1 kO resistor. In serial inl
parallel out mode the position of the DASR with a
high CASC is unimportant for internal timing. In this
mode the period of the internal strobe (for output
latch 1) is not increased. So the data of the shift
registers are strobed to the output latch 1 every
fourth SCLK period. For getting valid TTL output
data over the whole

The TTL·Clock high phase of the DASRs with a low
CASC is doubled. When cascading the DASR the W
signal can be delayed not only in four steps as in the
single chip configuration but over the whole TTL
clock period by using the W output of the appropri·
ate chip.

Functional Block Diagram

•

i

132

-I INPUT Latch 1

:

...1INPUT Latch Z

:

OUTPUT Latch 1

ECL-nL

,.

..

0--

t

I
OUTPUT Latch 2 I

m~ECL

DIRe

STR

I

132

..

.l

_t
/32
f

12 I

I

l'

I
8-Bitx4

I

DIN 0 ... 7

;
SHIFT REGISTER

I

•

OUT 0 .. 7

• D

seLK

CASI
CAse

c
c

EIO

c

~I
~I

CASO ..

CONTROL LOGIC

CLOCK GENERATOR

I
law

.....------r-"T"'"------I~

II

VO

TILeLK

VI

0113-3

Figure 1

3·62

SDA 8020

.-

Cascading Block Diagram

., -..

f
~

§

>

N

~
Q

.,,

~

'" S

01
.....
-,,'

0:
..... ,

S4 -

-,,

.

!
-..

~

I

'~"

0

2..t - - - -..

i·

~

....
r

i

~

§

g

0

S

0:
..... ,

-,,
.,

~
-..

~

~
{}
ii
ii
ii
ii

~
oJ

§

~

'"

.,

~

0

~

:,c

.5

!

~

.,, .... §
~

g

:I

ii
ii
ii

II

..

U)

3
i4-

'"

~

:a

1

i"

~

'"

+,
,

H

0

~

9
~

s

~

.2
~

~

!S

I

;\

~

~

~

~

0',

2

54-

.....
-,'

!

a.
......

...

~

..... '

I

I

0
ii
;:

-',

===:::;>

'ii

i!as

+

0:

~

~

i·

'" 2

'" S

.i:

.'

.

9c

..

i"

I

~

•

L
Figure 2

3-63

SDA 8020
HOLD/RES-Timing
CONTROL

1s.H&••'
tw....I r - - t t - - - - - -

t 2 J 4

SCLK

TTLCLK

Hi5ffi (internal) _ _ _ _...J
Note:
1. Dependent on the programmed delay of W; solid line shows conditions for VO

0113-6

= 0, V1 = O.

Figure 3

Cascading of Two DASRs-Serlal In/Parallel Out

~

~32

32

L

DOl ... D74

STR

....

8

I
seLK

DlNG ... 7

I'
CASI
SCLK

1

W

r--

4

DOUTG ...7

8

DOl. D74

STR

....

DINO .. 7

I'

2

W

DOUTO ... 7

8

EIO

CAsl
SCLK

I

I

I

I

1

!

I

!

CASO
CASC

I-

CASC

CASO
EIO

~

]

--

vee

GND
0113-7

Figure4a

3-64

SDA 8020
Cascading of Two DASRs-Serialln/Paraliel Out
2

3

SCLK
DINO ... 7,1
TTLCLK,I
iN,l

001 ... 74,1
DINO ... 7,2
TTLCLK,2
W,2
001...74,2
STR,1= STR,2
STRO,I,2°)

Jl
0113-8

·Controls output latch 1 of either DASR.

Figure 4b

Cascading of Two DASRs-Paralielln/Serlal Out

"'~2

'32

L

~ "?'

I\.

!

Low

5eLK

8

I

~

DOl .D74

STR

DINO 7

I'
CASI
SCLK

I\.

DOUTO 7

1

8

DINO.7

I'
CASI
SCLK

CASO
CASC

£10

I

I

1

I
,

vee

;,

DOl. .D74

STR

W

W

J

DOUTO.7

2

8
CASO

CASC

--

GND

£10

~

I'

l
-,....!!....

~
·2V
0113-9

Figure 5a

3·65

SDA 8020
Cascading of Two DASRs-Paralielln/Serlal Out
34567.

SCLK
001. .74,1

TTLCLK,l

W,l
001 ... 74,2

TTLCLK,2

¥V,2
STR,1 .STR,2
DDUTO ... 7,2

STRI,l,2')
0113-10

·Controls Input Latch 2 of either DASR.

Flgure5b

Timing Relations at Serlalln/Paraliel Out Operation
SCLK

DIN

STR

't4.SCLK.D

ool ... D74
0113-11

Figure 6

3·66

SDA 8020
Timing Relations at Parallel In/Serial Out Operation
SClK
Control

~-r+-------------~

__--~--~-----+---------------------

STR

iiOffi
!z.
001·D7..

DOUT

TTlClK

iN
0113-12

Figure 7

Absolu.te Maximum Ratings·
Maximum ratings are absolute limits. The integrated
circuit may be destroyed if only a single value is exceeded.
Maximum Rating for
AmbientTemperature .... -25·C

< TA <

+70·C

Positive Supply
Voltages (Vee> ................ - 0.3V to + 6.0V
Negative Supply
Voltages (VEE) .•.•••...•.....• - 6.0V to + 0.3V
ECLInput Voltages .................. - 3.5V to OV

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Output Current
at 001-074 ........... -10(1) mA to + 10(2) rnA
Output Current
at TTlClK ........... - 20(1) mA to + 20(20) mA
Output Current
at OOUTO-OOUT7 ..... : ...... - 20 mA to 0 mA

ECl Output Voltages ......................... 1V

Output Current at EIO ............ -10 mA !o 0 mA

TTL Input and Output
Voltages ..•.................. - 0.6V to + 5.5V

Junction Temperature (TJ) ................. 12S·C

Tri-State Currents
into 001-074 ........................... 1 mA
Output Current at W ...... - 40(1) mA to + 40(2) mA
Notes:

1. High-State.
2. Low-State.

Storage Temperature (Ts) ...... - SS·C to + 12S·C

Thermal Resistance:
System-Air (RthSA> ...................... 30 K/W
System-Package (RthSP) ...............•. 15 K/W

3-67

SDA 8020

Electrical Characteristics
The electrical characteristics include the guaranteed distribution boundaries of the values which are maintained by the integrated circuit in the specified operating range. The typical characteristics are mean values
which are expected from fabrication. Unless otherwise specified, the typical characteristics are valid at T A =
25·C and the specified supply voltage.
Supply Voltages: Vcc = 5V ±5%, VEE = -4.5V ±~%, Ivcc - vccll
Ambient Temperature: -25·C < TA < 70·C

Parameter

Symbol

Conditions

< 0.5V

Test
Circuit

LImits
Min

Units

Typ

Max

Power Supply
Positive Supply Current

Icc

65

80

rnA

Negative Supply Current

lEE

240

250

rnA

TTL-Pins
High-level Input Voltage

VIHT

Low-Level Input Voltage

VllT

2

V
0.8

High-Level Input Current

IIHT

Vcc

Low-Level Input Current

lilT

Vcc

High-Level Output Voltage VOHT

Vcc

Low-Level Output Voltage VOLT

Vcc

Off-State Output Current

IOZlT

Vcc

IOZHT

Vcc

=
=
=
=
=
=

= 2.4V
= 0.5V
Min; IIOH = -800/J-A
Min; IOl = 3.2 rnA.
Max; Vo = 0.5V
Max; Vo = 2.4V

V

Max; VI

30

/J- A

Max; VI

-1.6

rnA

a

V

2.4
0.5

a

·V

-50

/J- A

50

/J- A

ECl-Plns
High-Levei input Voit~ge
Low-Level Input Voltage

VIHE

-1.165

-0.66

V·

VILE

-1.81

-1.475

V

High-Level Output Voltage VOHE

c

-1.025

-0.88

V

Low-Level Output Voltage ValE

c

-1.81

-1.62

V

-0.65

V

-1.35

V

CASI,CASO
High-Level Input Voltage

VIHC

-1.0

Low-Level Input Voltage

V,lC

-1.6

High-Level Output Voltage VOHC
Low-Level Output Voltage VOlC
Maximum Load Capacity
atCASO

3-68

V

-0.9

·v

-1:55

.'

CCASO

5

pF

SDA 8020

Timing Characteristics
Parameter

Symbol

Conditions

Test
Circuit

Limits
Min

Typ

Units
Max

tS,DIN

0.5

ns

Hold Time DIN 0-7 to SCLK

tH,DIN

2.0

ns

Setup Time 001-074 to STR

tS,D(1)

8.0

ns

Setup Time DIN 0-7 to SLCK

Hold Time D01-074 to STR

tH,D(1)

0

Setup Time Control to HOLD

tS,CONT(2)

30

7

ns

Hold Time Control to HOLD

tH,CONT(2,6)

20

0

ns

Min. Setup Time STR to SCLK

tS,STR,D(1, 3)

-4.5

ns

Min. Hold Time STR to SCLK

tH,STR,D(1, 3)

6.5

Min. Setup Time HOLD to SCLK

tS,HOLD,S

14

Setup Time HOLD to TILCLK

tS,HOLD,T

20

tS,RES

20

Setup Time RES to HOLD

ns

ns
20

ns
ns
ns

Min Setup Time STR to SCLK

tS,STR,SCLK(4, 7)

3

Min Hold Time STR to SCLK

tH,STR,SCLK(4, 7)

0

ns

Min Setup Time 001-074 to SCLK

ts,D,SCLK(5)

5

ns

Min Hold Time 001-074 to SCLK

T H,D,SCLK(5)

1

ns

24

ns

Delay SCLK-001-074

td,SCLK,D

RL = 1200,
CL = 15pF

a

Delay STR-001-D74

td,D

RL = 1200,
CL = 15pF

a

Delay DIRC, HOLD-001-D74

tZL, tZH

Ru = 1200,
CL = 15pF

b

Delay DIRC, HOLD-001-074

tHZ, tLZ(6)

Ru = 1200,
CL = 15pF

b

Delay SCLK-W

tdHL,W

RL = 1200,
CL = 40pF

a

Delay SCLK-W

tdLH,w

RL = 1200,
CL = 40 pF

a

Delay SCLK-TILCLK

tdLH,TTLCLK

RL = 1200,
CL = 15pF

a

Delay SCLK-TILCLK

tdHL,TTLCLK

RL = 1200,
CL= 15pF

a

Delay SCLK- OOUT 0-7

td,DOUT

Delay RES-DOUT 0-7

~

Pulse Width of SCLK

tw

Pulse Width of RES

tW,RES

Min Pulse Width of STR

tSTR

Max SCLK Frequency

fSCLK
Notes:
1. Only every 4th SCLK-period from the 4th trailing edge on.
2. Control: Signals DIRC, VO, V,1, CASCo
3. Doesn't apply if output latch 2 is transparent.
4. Doesn't apply if input latch 1 is transparent.
5. Only every 4th SCLK-period and if input latch 1 is transparent.
6. Refers to HOLD after internal synchronization.
7. Only every 4th SCLK period from the 7th trailing edge on.

16.5

21

ns

23

ns

40

ns

25

ns

9.5

13

ns

9

11

ns

11

13

ns

12.5

15

ns

c

5

7.5

ns

'c

15

ns

4

ns

30

ns

100

6

ns

125

MHz

3-69

SDA 8020
Test Circuits
b)

a)

Vee

Vee

~.,

R..
LA

5,

"ilz

T<

N

:s~
"ilz

"i~

t<

0113-13

Ru
-ua

~7
"i7

f'
0113-1.

'C)

~ ~o
••

·2V
0113-15

FigureS

Application Examples
Data Acquisition (Serial In/Parallel Out)
(See Figure 10 and Figure 11)

In the first example a high speed data acquisition
system consisting of an 8-bit!100 MHz AID-converter (SDA 8010); CMOS SRAMs (tacc s 35 ns), a p.Pinterface (SAB 8286) and a high speed TTL address
counter is shown.
The analog input signal with frequency components
of up to 50 MHz is sampled and converted to 8-bit
digital data by the SDA 8010. These ECL data are
demultiplexed into four TTL data streams by the
DASR. Writing the TTL data to the fast CMOS
SRAMs is supported by DASR -signals Wand
TTLCLK. When an acquisition cycle is finished, e.g.
after the counter has clocked out the memories' top
address, a low HOLD disables the DASR and the
TTL data outputs change to the high impedance
state. Now a microprocessor or -controller access to
the acquired data is possible via the single bus
transceivers.
.
The input!output configuration is attained by setting
DIRC to low. The best way for starting the system is
to reset the DASR before activating it by a rising

3-70

HOLD edge. Now data acquisition can be easily interrupted and restarted (e.g. after the memories are
read out via the bus transceivers) only by HOLD.
The critical time relations in this system are set by
the requirement of the CMOS memories. Usually the
chip select signal for the memories must be high
during address transitions (CS controlled write cycle). This high pulse should be as short as possible
for easy memory timing. Additionally, the time qf valid data at the parallel TTL outputs (i.e. the memory
inputs) is in a tight relation to the chip select signal.
These requirements can be met by connecting the
W with the Strobe (STR) and adjusting the IN delay
time by VO, V1. Sometimes, especially when the
memories are operated near their frequency limit, it
could become necessary to delay IN slightly by an
external device (T1), but this should not be the normal case. Because the data out valid time of the
DASR is correlated with the memories' chip select
signal by the Strobe, the timing demands of the
memories are fulfilled. The delay of IN is mainly determined by the memories' address transitions,
which have to be during the CS high phase. To get a
close time relation between the DASR and the address counter the TTLCLK is used as the counter's
clock. RCOUNT is a signal of lower frequency than
TTLCLK for read!!!a....the memories to the p.P-data
bus (HOLD = L, CS1 = L, W1 = H).

SDA 8020
Data Acquisition System

Address

COUNTER
RCOUNT

Analog
Input

LOGIC

SDA8010
AIDConverter

DASR SDA 8020

DDUT 0

7

~~~~L~;____~~5_C__E710___Dlr~__~REr5__V~O__~V~I__SrU___H~O~LD__~W~______-J

GJ

r---~

SptemClock
0113-16

Figure 10

Serlalln/Paraliel Out (End of Operation)
SClK

DINO-7

TTlClK

ool ... D71

bo4... D74
ADDRESS

0113-17

Notes:
1. Delay programmed by VO, V1.
2. Additional delay by external circuit.

Figure 11

3-71

SDA 8020
The data acquisition system of Figure 10 is not configured for all SCLK frequencies. If fre'l!!..ency independent operation is required the rising Wedge and
that TTLCLK edge, which clocks the address counter, must have the same reference edge of SCLK.
This is attained bVhe falling TTLCLK edge and the
second possible W pulse (VO = 0, V1 = 1; reference edge is the fourth SCLK edge) or by the leading TTLCLK edge and the fourth possible W pulse
(VO = 1, V1 = 1; reference edge is the ~ilcth SCLK
edge). In the second case the first TTLCLK's leading
edge after starting must be suppressed for writing
defined data to the whole memory or the counter's
start/stop-addresses are manipulated suitably.
Waveform Generation (Parallel In/Serial Out)
(See Figure 12 and Figure 13)
The second example shows a waveform generating
system consisting of two cascaded DASRs, an 8-bit!
7 ns 0/ A-converter (SDA 8005), CMOS SRAMs
(tacc ::;; 75 ns), the same p.P-interface as above and
a fast TTL counter, preferably a programmable one.
With these few components a very versatile waveform generating system can be constructed. First
the desired waveform must be written into an
EPROM. These data are then transferred to the
fast SRAMs, e.g. memories with 45 ns access time
organized as 8k words of 8 bits each, under control of the SAB 8051. With such memories the avail-

able memory space for the digitized waveform is 64k
words of 8 bits. The cascaded shift registers represent an 8 to 1 multiplexer with 100 MHz data at the
outputs DOUTO-DOUT7 of the second DASR. The
digital data are converted to the analog waveform by
the SDA 8005.
The following timing mainly depends on the speed of
the memories and on the delay time of the counter
which provides the memory addresses. After valid
memory addresses and the subsequent address access time, data applied at the parallel TTL inputs of
the DASR are valid only for a short time tvalid (assuming memories with 45 ns read cycle time and a
100 MHz shift clock rate, tvaiid amounts to about
40 ns).
During this time slot the data must be read into the
first latch stages of both DASRs by the strobe hi9b.
pulse. This could be reached by connecting the W
output of the second DASR to the strobe inputs and
adjusting the required delay time by delaying W via
VO, V1 (in this· case W is delayed two shift clock
periods). The data are then received into the next
latch stage by an internal clock. Afterwards they are
shifted out serially with the shift clock rate. To avoid
bus contention, when the memories are written by
the microcontroller, the outputs of the counter must
be set to the high impedance state.
The control inputs of the memories, CS and W, must
be provided by the system processor or could be
easily aerived from DASR Signals

Waveform Generation System

,

SDA 8020
In DIIIC Riim

on

·zv

vee

.'IV

liB

GND

vee
0113-18

Figure 12
3-72

SOA 8020
Parallel In/Serial Out (Start of Operation)
SCLK

TILCLK,I

TILCLK,2

W,20 STR,1,2
DOl.071
00.
.. 074 1,2 _ _ _ _ _---'\-_ _ _ _ _ _--''--_ _ _ _ _J\_ _ _ _ _.J\.._ _

'--_~r'_

ADDRESS

m.m
DDUTO 7,2

\

-------------------------------~
0113-19

Figure 13

3-73

SIEMENS

SDA 8200
6 Bit 300 MHz AID Converter'
• 300 MHz Conversion Rate

• Optionally 2:1 Demultiplexed Output Data

.5.4 Eft. Bits (fanalog = 100 MHz)

• No Pipelining in "Transparent Mode"

• ±0.25 LSB

• Data Ready Clock Output

Max. Linearity Error

• ± 1V Input Voltage Range

• Overflow Output

• 12 pF Input Capacitance

Pin Configuration
ClK!

ClK!

GNOA

GN01

Veec

ClKO,

DB

HOLD

D 12
011
010
GND1
09

AIN

08

AIN

07

-V,Ef.S

06

NC

GN01

OS

VcCD

04

GNDA

03

GNDD

02
01

SO

DO

DEM

GN01
0105-1

a

The SDA 8200 is an ultrafast AID converter according to the parallel principle with resolution of 6 bits, a
guaranteed clock frequency of 300 MHz and high performance up to 150 MHz full scale inputs.
For the circuits. descriptions and tables indicated no responsibility is assumed as far as patents or other rights of third parties
are concerned.
The information describes the type of component and .shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Liability for patent rights of third parties for components per se, not for circuitries! applications.

@Siemens Components, Inc.

3-74

April 1988

SDA 8200

Block Diagram
so
O.mullrpl ••••

Output
013
012
011
DID

09
08
07

OMUX

CLK I

-Ii"",

-v."

Clock 0"...

A IN
0105-2

Figure 2

3-75

SOA 8200

Pin Description
Pin

Name

Symbol

Description

10, 11

Analog Input

AIN

Input for the signal to be digitized. To
lower parasitic inductance two pins are
used for this input.

13,12,
8,9

Reference Inputs

-VREF -:-VREF,S
+ VREF + VREF,S

Bottom and top of the reference-resistorstring. The inputs may either be used as
sense and force for a Kelvin connection or
connected in parallel to minimize parasitic
resistance.

40, 1

Conversion Clock

ClKI,ClKI

Every rising edge of a signal applied to
ClKI initiates sampling of the analog ,
signal. Either ECl (differential or singleended) or sinewave clock inputs may be
used.

38

Clock Output

ClKO

Provides an ECl signal which can be used
to control the takeover of the digital
outputs into subsequent circuits (not
available in the transparent mode). In the
demultiplexing mode the frequency of
ClKO is half the sampling frequency (see
"Modes of Operation").

22,23,
24,25,
26,28,
29

Output Word 1

00-06

ECl outputs including overflow bit (06)
valid only in the demultiplexing mode. In
this mode every first digital word of a pair
of subsequent samples is delivered with a
clock rate of half the sampling frequency.
In the direct modes undefined data are
shown at these outputs.

30,31,
32,34,
35,36,
37

Output Word 2

07-013

ECl outputs (013 overflow) delivering the
second word of a pair in the
demultiplexing mode. In the direct modes
the digital data at these outputs appear
with a clock rate equal to the sampling
rate.

19

Set Overflow

SO

A logic H at this ECl input or strapping the
pin to GNOO causes the overflow bit to be
H and the data bits to be l when the
analog signal exceeds the uppermost
comparator threshold. If the pin is not
connected or l is applied the data bits
remain H in case of overflow.

20

Oemultiplexing

OEM

Setting this pin to H or strapping it to
GNOO sets the device into the direct
mode.

7

Set Transparent

TRP

A logic H (or GNOO}'at this input sets the
device into the transparent mode (no
pipelining). In this mode both OEM and
HOLD input become ineffective. Besides,
no clock output is provided.

3-76

SDA 8200

Pin Description (Continued)
Pin

Symbol

Name

Description

4

Hold

HOLD

H active ECL input that immediately stops
data transfer to the outputs (00-013) and
inhibits the clock output. The last data
word remains at the output and CLKO is
forced to low.
In the direct mode the first valid output
data together with the output clock appear
one clock cycle after HOLD is released. In
the demultiplexing mode clock and valid
data appear ,after two conversion clock
cycles with the first data word
(corresponding to the first sampled value
after HOLD is set to L) always shown at
00-06.
HOLD is inactive in the transparent mode.

5,6,2,16,
15,18,17,
3

Analog Supply
Digital Supply
Clock Supply

VCCA, VEEAGNOA
VCC 0, VEE 0 GNO 0
VCCC

,Supply Voltages

21,27,
33,39

,Output Ground

GN01

Return path for the current of the emitter
followers in the ECL output stages.

Circuit Description

Clock Input (ClKI)

The AID conversion iS,carried out in an array of 64
comparators connected in parallel to the analog input AIN. The signal is compared simultaneously with
64 equally spaced referellce voltages provided by
the resistor string R1-R65. With the rising edge, of
the conversion clock CLKI the result of the comparison is stored in the first comparator latch and afterwards passed to the second latch in a pipelining operation. Then the digital result of the comparison is
pending at the comparators' output in a so-called
thermometer code. Three subsequent encoding
stages form the binary representation of the sampled value and a demultiplexer optionally divides the
300 MHz output data stream into two 150 MHz
channels which are converted to ECL levels by two
parallel output driver blocks. ,All clock signals for the
pipelining and de multiplexing stages are formed internally by a clock driver circuit connected to the
e~ernal conversion clock via CLKI. A clock signal
for taking over the output data into subsequent 'circuitry is provided at CLKO. If, however, the pipelined
operation is disadvantageous (e.g. in subranging
converter applications), all internal latches fqllowing
the comparators may be set transparent via the programming input TRP. So any encode command directly causes the appearance of the respective output data after a short delay.

The clock inputs are designed to be driven differentially with ECL IElvels (Figure 3a). Since CLKI is internally biased to -1.32V, it is possible to use CLKI
single-ended, too. With this configuration a bypass
capacitor from CLKI to GNOC is recommended.
In this case the clock has to be stable with regard to
the internal reference voltage to ensure the specified timing (tWH ClKI tWl ClKI) over the operating
range. For continuously applied input clock the configuration shown in Figure 3b is recommended. A
capacitively coupled sinewave clock input (typ.
300 mVpp) can then be employed without degradation in performance (Figure,3c).

Analog and Reference Inputs
The input voltage range is determined by the voltages applied to the top (+ VREF) and bottom
(- VREF) of the resistor string. Two pins for each
voltage allow a Kelvin connection (sense, force) if
highest precision is required. Otherwise the parallel
connection of these pins ensures low parasitic resistances. The analog input can be driven from a
customary SOn. source since the, input capacitance
is a very low 12 pF, independent of input voltage,

3-77

SDA 8200
and the input voltage range may be set symmetric to
ground.

Supply System
The supply system breaks down into three parts.
The analog supply Vee A, VEE A is connected to the
first comparator stages, the digital supply Vee 0,
VEE 0 serves for encoding, demultiplexer and output
stages and a special clock supply Vee e is provided
to separate the high and noisy driver currents from
the other supply systems. Additionally a separate retum path for the currents of the output emitter foliowers is established via GN01.

Modes of Operation
The analog signal is sampied with every rising edge
of the clock signal CLKI. By programming the TRP
and OEM inputs three different output modes can be
chosen:
a) Direct modes (Figure 4):
The output data appear at the outputs 07-013
with a word rate equal to the sampling rate.
The logic state of the outputs 00-06 is not defined.
One of two submodes 9an be chosen:
,(I) Normal Mode (TRP low, OEM high)
Due to internal pipelining the output data appear one clock cycle after the rising edge of
CLKI (sampling moment). CLKQ delivers a
clock signal with the same frequency as
CLKI.

(II) Transparent Mode (TRP high)
After a sampling command the associated
output data appear directly with a delay of
less than 7 ns. No output clock Is available.
b) Demultlple~lng mode (TAP low, D!IIlow; FigureS)
The output words corresponding to two subsequent samples appear simultaneously at the outputs 00-06 and 07-013, respectively, with half
the clockrate of the conversion clock CLKI. After
a HOLD pulse the word belonging to the first
sample Is aly/ays shown at 00-06 and the delay
between the first sample and output Is two cycles
of the conversion clock CLKI. At CLKQ a clock
signal with half the frequency of the conversion
clock, synchronous to the output data, is provided.
In all modes the output format in the overflow status
can be programmed via the SO input. Setting SO to
H causes the overflow bits (06 and 013, respectively) to remain H and the data bits (DO-OS and 07012, respectively) to go to L when the analog signal
exceeds the,threshold of comparator 64. If SO is set
to L or not connected all data and overflow bits remain H in case of overflow (Figure 6). This enables
easy cascading of two SoA 8200 to a 7 bit AID-system by connecting them as shown in Figure 7 and
strapping the SO input of the lower one to H.
The HOLD Input allows to stop the digital data
stream of the output and to restart with defined output conditions. It Is disabled in the transparent
mode.

Absolute Maximum Ratings·
Positive Suppiy Voltages
CVecA), (Vcco), (Vece> ......• -0.3Vto +6.0V
Negative Supply Voltages
CVEEM, (VEE 0) .••..•.•....... -6.0Vto +0.3V
Analog Input Voltages
(+ VREF), (- VREF), (VAIN) ... - 2.5V(1) to + 1.SV
Digital Input Voltages
CVCLKI), (V~), (VOEM),
(Vso), (VTRP) ................. -3.0Vto +0.3V
Output Current (100-1013), ••••••• ~ ..••••••• 20 mA
Junction Temperature (TJ) ....•.•.•••.... , .• 12SoC
Ambient Temperature
(without oissipator) (TM ••••.•..•...••.... 5O"C
Storage Temperature (Tstg) •••....•.•••••.• 125°C

3-78

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Thermal Resistances

Junction-Air (without oissipator) .....•••••. 4S K/W
Note:
1. Reference voltages below - 2V must not be applied without the negative supply voltage.

SOA 8200

Characteristics
vec A. vcc D. vcc C = 5V ±5%. VEE A. VEE 0 = -4.5V ±5%. 25°C
Parameter

Symbol

< Tj < 125°C
Limits

Conditions
Min

Typ

Units
Max

Supply
Positive Supply Current

IVCCA
IVCCD
Ivccc

50
65
35

rnA
rnA
rnA

Negative Supply Current

IVEEA
IVEED

45
125

rnA
rnA

Power Dissipation

P

1.5

Permissible Supply

IlVcc

Voltage Difference

IlVEE

1.B

W

100

mV

1

V

700

,...A

Analog Section
SIgnal Input
-2

Voltage Range

VAIN

Max. Input Current
(VAIN = + VREF)

lAIN

500

Input Capacitance

CI

12

pF

Reference Inputs
Reference Voltage(1)

-2

+VREF

Reference Resistance

RR

Temperature Coefficient
of Reference Resistor

TC

1

V

120

n

1.7

10- 3/K

Digital Section
LogIc Levels
Input H Voltage(2)

VIH

Input L Voltage(2)

Vil

-1.165

Output H Voltage(3)

VOH

Rl

Output L Voltage(3)

Val

Rl

=
=

V
-1.475

V

100n

-1.025

-O.BB

V

100n

-1.B10

-1.620

V

Clock Inputs(4)
Input Current

IClKI

Maximum Clock
Frequency

fe•max

Aperture Delay

tA

Hold Time

tWH.ClKI

1.2

ns

Strobe Time

tWL.ClKI

1.2

ns

20
300

,...A

350

MHz

7

ns

3-79

SDA 8200

Characteristics
Vee A. Vcc D. Vcc C

(Continued)
= 5V ±5%. VEE A. VEE D

Parameter

Symbol

=

-4.5V ±5%. 25"C

<

Tj

<

125"C

Limits

Conditions
Min

Units

Typ

Max

Digital Section (Continued)
Programming Inputs(2)
Input H Current

IIH

80

,...A

Input L Current

IlL

60

,...A

Hold Input
Setup Time

ts.HOLD

0.5

ns

Release Time

tr.HOLD

2

ns

High Pulse Width

tW.HOLD

1

ns

Data Outputs(S)
Data Valid Range
Normal Mode

tV.N

fc

Transparent Mode

tV.T

fc

Demultiplexing Mode.

tV.D

fc

= 250 MHz
= 250MHz
= 300 MHz

3

ns

3.5

ns

2.5
5

5.8

ns

Output Delay
Normal Mode

0.5

tet.N

Transparent Mode

tet.T

Demultiplexing Mode

td.D

ns
8

ns

0

ns

Clock Output
Maximum Frequency(6)

fa•max

Clock Delay LH

tetLH

250

MHz

6

ns

Clock Delay HL
5.5
ns
tetHL
Notes:
1. +VREF has to be more positive than -VREF.
2. Applies for DEM. SO. HOLD. TRP
3. Applies for CLKQ. DO-D13
4. See "Circuit Description"
5. Values refer to sinewave clock inputs (duty cycle 50%).
6. Has been chosen lower than maximum sampling frequency because at very high input clock rates the device should
preferably be operated i~ the demultiplexing mode.

Conversion Characteristics
vcc A. vcc D. vcc C

=

5V ±5%. VEE A. VEE D

Parameter

I

Symbol

I
I

INL

I

=

-4.5V ±5%, TA

Conditions

I
I

=

25"C
Limits

Min

I

Typ

I

Max

I
1

0.25

I
I

Units

Static Nonlinearity
Integral Nonlinearity .
Differential Nonlinearity

3·80

DNL

I
I

I
I

I
I

0.25

I
I

LSB
LSB

SDA 8200

Conversion Characteristics
=

Vee A. Vee D. Vee e

(Continued)
SV ±S%. VEE A. VEE D = -4.SV ±S%. TA

Parameter

Symbol

=

2SoC
Limits

Conditions
Min

Units

Typ

Max

Dynamic Performance(1)
Large Signal Bandwidth

f3dB

Effective
fAIN =
fAIN =
fAIN =
fAIN =

beff

Resolution(1)
10MHz
50 MHz
100 MHz
150 MHz

fc = 300 MHz
VAIN = 2Vpp
5.6
5.3

Signal-to-Noise Ratio(2)
fAIN = SO MHz
fAIN = 100 MHz
fAIN = 50 MHz
fAIN = 100 MHz

SNR

Total Harmonic Distortion
fAIN = 50 MHz
fAIN = 100 MHz

THD

fc = 300 MHz
VAIN = 2Vpp
VAIN

=

1 Vpp

VAIN

=

2Vpp

36
3S

250

MHz

5.9
5.B
5.4
5.0

Bit
Bit
Bit
Bit

37.5
36
37
36

dB
dB
dB
dB

-44
-33

dB
dB

Notes:
1. Measured in a 50n analog system at 300 MHz sampling rate (300 mVpp sinewave clock).
2. Includes both noise and harmonic distortions.
3. Without the effect of harmonics; thus bell. SNR[dB] and THD[dB] are related by
bell = (-10 log (10-SNR/10 - 10TH0/10) - 1.8)16

Clock Input
GNDA

lkn

1-1...c::J--II.,--132V
Clock Amplifier

l--....c:J--- 11., - -1 32 V

0105-4

Flgure3b
0105-3

Figure 3a
lkn

rr-C::I--II.,--1.32V

0105-5

Figure 3c

3-81

SDA 8200
Timing Diagram Direct Modes
Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Sample 6 Sample 7 Sample 8 Sample 9 Sample 10

CLK I

-+_______---IJ

HOlO _ _ _

ClKa
normal

-+____________

00-06 _ _ _

~~=__ _ _ _ _~-----------

07_013---~r.rl-~~-,~r-~OT~~r-----,~r--nWT-~~-~~-,~r--nWT-~~­

normal ----~~+-~~--~~~~~_,L~~~~~--~~~~~~6¥~~~L-~~~~~~~~--

07-013
transparent

0105-6

Figure 4

Demultiplexing Mode
Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Sample 6 Sample 7 Sample 8 Sample 9 Sample 10 Sample 11

Analog

CLK I

HOLD

ClK Q

00-06

01-013

!<
)§§(

~mple1J<

Sample 3

Sample 8

!< Sample 10

LtV.D-l
)J8!(

Sample 2

)J8!(

Sample 4

)J8!(

Sample 9

JlIlR

Sample 11
0105-7

Figure 5

3-82

SDA 8200
Transfer Characteristic and Truth Table

-

06 OS 04 03 02 01 DO

H H H H H H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

L

,
L

L

L

L

L

H

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

.%

A

/

X
1

~
/

2

"

62 63 64

0105-8

a) SO set to "L" or not connected

-A

06 OS 04 03 02 01 DO
H

L

L

L

L

L

L

L

H

H

H

H

H

H

L

H

H

H

H

H

L

~L5B

&p

p
L

L

H

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

A

L

/

.%
0

1

i

62 63 64

0105-9

b) SO set to "H" or strapped to ground

, Figure 6

3·83

SDA 8200
Block Diagram of a 7 Bit AID-System with Two SDA 8200
VTQ p

I

I

013 ~ ,-------<' 06
012
OS, Word 2

.

-so
~

.D~

.VREFS

.VR[F

DO

07
D6
05:-

AIN

,....- ClKI

I

DO
-V"EF

-VREI'S

Y

n

'

013i012f;-

I- 50

f-

07~ f...- Lo

r--- I-- AIN
I--

,

.VAEFS

.VAEF

ClKI

-VAEF

06

06
05

OJ ~ord 1

DO

DO

-VREFS

I

I

AIN ClK I
0105-10

Figure 7
Test Circuit

1

ClKI

""

5011

J

5011

L

=1=

2

=!=

.5V

'"

HOLD

1

I

10kll

1

~= F J

-2V

.

,

1...

15.10011

lL-

3

38

ClKQ

4

37

013

5

=!==!=
Hf-I

TRP

1

..L

6
7

8

~

==
10

'"

AIN

5011

1 IT

I ,i

11

==

29

07

30

06

13

~
15
1,5~H

~

-lI-- 100 nF Chip
~ to

DVOld

.I~

latch-up effect

_4,5V

SOl

=F

.l

16

~
'F 18
19

DEMl

21

22

DO

I--0105-11

3-84

SDA 8200

Ordering Information
Type

Order Code

SDA8200

Q67100-Hxxxx

3-85

SIEMENS

SDA8800
Data Acquisition Controller
• Controls HSDA Cache Memories with Sizes
from 1 kByte to Several MBytes

• Supports 8-, 16- and 32-bit Data Bus
Widths

• Supports Static CMOS RAMs

• High Speed DMA Data Transfer Capability

• Allows the Design of Data Acquisition and
Data Transmission Systems

• 16 bits Address Range for the Cache,
Extendable to 20 bits

• Fully Register Programmable

• Programmable Pre-/posttrigger Function

e Compatible with SIEMENS HSDA
Components

e 2 ,...m ACMOS Technology, PLCC 68
Package

• Compatible with SIEMENSIINTEL 80xx,
80xxx and MOTOROLA 68xxx
Microprocessors

Pin Configuration
,

"
"

67

2

I

•

5

,

7

I

,

0

~ "

u "

~

" "

»
'I

"
20

is

2'

50

2Z

"
52

2.

i'
II

H

51

27

2J

25

51

21

57

It

55

JO

55

II

so

J2

51

II

S)

so

0115-21

The DACO SDA 8800 is the controller for High Speed Data Acquisition (HSDA) cache memories. Together
with the Data Acquisition Shift Register (DASR) SDA 8020, fast 100 MHz caches with sizes in the range of
1 kByte up to several MBytes can be designed with static CMOS RAMs. The DACO makes the whole HSDA
cache to behave like a microprocessor peripheral device. It handles autonomously the acquisition or transmission of data, and offers a variety of microprocessor access structures, including high speed DMA·based data
transfers.

@Siemens Components. Inc.

3·86

May 1988

SDA 8800

,Block Diagram
REGISTERS

DO

4

D7

-I

AD. A19

DEN
Adr3

AdrO

Stop Address

WR(DRDY)_

RD(RrW)_

Cs

_

MCS

_

DACK

_

Micro-

Processor
Interface

4

--I
•

DRQ (DiiQ)

Memory
Interface

Pre/Posttngger
Interrupt
T C. Mask

Transfer

.. Transfer Control
4

RESET(~

11M

(DTACK)

Cache

Address read back

4

INTR (lNTR)
ClK
_

READY

AEN

Start Address

4

Ready
Generator

•-

Parameter Mask
Logic

Status

·1

TRIG_

Control

Parameter

~
DIRC
DAClK _

Logic

!

Delay

Data

Acquisition

Interface

~

CHSO. CHS3
DEC EN

FDP~C
DT/R

•

ME

MWi'

ffO[5
RESD
0115-1

Figure 1

General Description
The Data Acquistion Controller SDA 8800, together
with the Data Acquisition Shift Register (DASR) SDA
8020, provides a complete,' highly integrated solution for the design of fast cache memories. The
range of applications spans from DSO's, logic analyzers and transient recorders over waveform and
pattern generators to radar and high resolution image processing systems, whereby the cache forms
the front-end of the digital data processing unit.
The high flexibility of the HSDA system stems from
its unique architecture. All the fast data handling
functions are assigned to the DASR. This device can
be arranged in serial, parallel and serial/parallel
configurations according to the specific application
requirements. With its ECl to TTL level conversion
and speed reduction it minimizes the system's power consumption and communicates directly with the
DACO.

grammable device suited to a large variety of applications and environments. The DACO can be
strapped to interface SIEMENS/INTEL and MOTOROLA microprocessor systems. It makes the whole
HSDA system to be viewed as a peripheral device to
the microprocessor with communication links via interrupt and DMA request lines.
The DACO supports both systems with and without
a DMA-controller by providing high DMA t~ansfer
rates as well as the memory-saving "Direct Processor Access" mode. The main part of the DACO for
controlling the HSDA system are two 16-bit counters
for the address generation and the trigger delay,
which can be extended to 20-bit by internal prescalers. With these counters the DACO is also prepared
to support future SRAM-types like the 1M x 4-bit,
and provides a posttrigger delay range of at least 4M
samples (with 1 DASR). Both counters can be operated up to 25 MHz, thus 100 MHz data acquisition or
transmission systems can be implemented with 1
DASR.

The DACO SDA 8800 performs all the controlling
functions of the HSDA system. It is a register pro-

3-87

SDA 8800

Pin Definitions and Functions
Pin

1/0

1-4

I

61-68

Symbol

AdrO-Adr3

1/0 DO-D7

Function

Address lines to System Address Bus. These lines are used to select
the appropriate registers when the DACO is in programming mode and
to select the appropriate data channel in the DPAC mode.
8-bit data bus used to read from or write to an internal register of the
DACO.

58

0

DEN

Data Enable signal, used as a transmit signal for an external data bus
driver at the Di lines. Normally DEN is low.

47

I

11M

The 11M pin straps the DACO to an INTEL 80xxx or a MOTOROLA
68xxx environment.

57

I

RD
(R/iN)

56

I
(0)

(1)

WR
(DRDY)

(1)

Read strobe used to clock out the contents of an internal register or an
HSDA-memory location. (The R/iN line determines the direction of the
data transfer).
Write strobe used to write data to an internal register or an HSDAmemory location. (Ready for single cycle DMA transfers.)

55

I

CS

Chip select for programming cycles.

54

I

MCS

Memory chip select line to get access to any memory location in the
DPACmode.

48

I

CLK

Clock input of the DACO. The system clock should be used to drive
this input preferably.

51

0

READY (DTACK) (1) Output of the internal READY or DTACK generator for all HSDAmemory accesses.

5

0

DPAC

Direct processor access signal. Serves as an output enable to the
address latch in the DPAC-mode.

6

0

DT/R

Data transmit/receive, used to set the direction of the data flow
through the data latches.

8,
11-13

0

CHSO-CHS3

Channel select lines for the data latches and the cache memories,
applied either directly or via an address decoder depending on the
data bus width and the number of DASR's in the HSDA-system.

7

0

DECEN

Decoder enable line for an address decoder attached to the CHSi
signals.

25-21,
37-33,
19-15,
31-27

0

AO-A19

Address output bus for the HSDA-memory. In DPAC-mode these lines
are in a tristate condition.

39

0

ME

Memory enable signal providing the selection of the whole HSDAmemory for the DT-mode and DMA-read mode.

14

0

AEN

Address enable for an external address buffer driver.

38

0

MWE

Memory write enable signal, is tied low in all cases that require a write
access to the HSDA-memory.

41

I

DACLK

Data acquisition clock input, used to clock out consecutive addresses
for the HSDA-memory when the DACO is in the DA or DT mode.

45

0'

HOLD

HOLD line, brings the DASR's into an inactive condition, i.e. in the
DMA- and DPAC-modes.

40

0

DIRC

Direction pin, determines the data transfer direction of the HSDA
system (low: DA, high: DT).

46
3-88

I

TRIG

Trigger input. Starts the operation of the trigger counter.

SDA 8800

Pin Definitions and Functions (Continued)
Pin

1/0

52

0

DRO
(DRO)(I)

DMA-request line. It is activated in order to obtain a DMA service. The
DRO pulse width is determined by the EOD-bit of the transfer control
register.

53

I

DACK

DMA-acknowledge, used as a chip select for DMA transfers.

50

0

INTR (INTR)

Interrupt request line. H is reset at the first CPU access to the DACO's
interrupt register.

49

I

RESET (RESET)

Reset input. Brings the DACO in the idle mode. All counters and
registers are cleared.

44

0

RESD

Reset to DASR, issued prior to the release of the HOLD signal at the
beginning of a data acquisition or transmission process.

10,26,
43,60

I

VDD

Positive power supply ( + 5V).

9,20,
32,42,
59

I

GND

Negative power supply (OV).

Symbol

Function

Note:
1. Pin definition for MOTOROLA 68xxx systems 11M strapped low).

Functional Overview
The DACO can be divided into the data acquisition,
the cache memory and the microprocessor interfaces as shown in the block diagram of Figure 1. All
transactions are controlled by the register block of
the device, which can be read or written via the microprocessor interface according to the address selection summarized in Table 1.
The DACO can be operated in 4 distinctive modes
which can be selected by programming cycles:
(1) Data acquisition (DA)/Data transmission (DT)
(2) DMA-transfer/lnterrupt
(3) DPAC (Direct processor access)
(4) Idle
All possible mode transitions are depicted on the
state diagram of Figure 2.
Modes (1) to (4) are characterized by two bits (SO,
S1) of the status register. The data flow direction is
set by the DIR bit.
As can be seen from the state diagram, all modes
can be entered or left under the control of the microprocessor by setting the status bits appropriately.
Additional mode transitions may occur either if a

task is finished or if a new task has to be started
automatically. The latter cases may be chosen optionally in order to minimize the processor's intervention. The DACO locks internal and external requests for mode· transitions mutually in order to
avoid time race conditions. However, external mode
transitions requests may only be delayed but not
suppressed by internal ones.

Microprocessor Interface
The DACO offers interfaces to SIEMENSIiNTEl
and MOTOROLA micrQProcessor systems, adjustable by the strap pin 11M. The interfaces provide an
easy to use connection to all important microprocessors of both families. low cost systems with only
few external circuits as well as high performance
- systems allowing for high data transfer rates can be
implemented.
Although the DACO has an asynchronous interface
it needs a clock (elK) in order to generate a lot of
correctly timed sequences. The ClK signal needs
not necessarily be synchronous to the processors
system clock but it is recommended to establish a
constant phase relationship between these two
clocks in order to avoid a lot of timing uncertainties.

3-89

SDA 8800
DACO State Diagram
RESET

0115_2

Figure 2
SIEMENSIINTEL Interface
With its 11M pin strapped high, the DACO's MP-interface directly fits to 8086 (8088), 80186 (80188) and
80286 systems. Bus transfers should operate without wait states, if the HSDA memory is fast enough.
If not, the DACO generates a programmable READY
signal.
The chip select signals.(CS, MCS and DACK) serve
as enable inputs for the microprocessor interface
and have to be asserted throughout a whole bus
cycle or throughout a series of bus cycles. The data
transfers are controlled by the RD and WR strobes
of the processor system.

without wait states should be possible in 68000,
68008, 68010 and 68020 systems, if the HSDA
memory is fast enough.
The DACO latches R/iN and Adri at each falli!!£!
edge of CS, MCS and DACK. This requires that RIW
and Adri are stable just at the beginning of the bus
cycle with some setup and hold times to the select
signal.
DTACK is an open-drain output with an active dynamic pullup which can be programmed to delay its
falling edge for 1 to 3 ClK periods.

READY (DTACK) Generation
READY is an open-drain output. If no wait states are
required (programmed value = 0), READY remains
in a stable high-impedance state. If it's programmed
to 1, 2 or 3 the DACO pulls the READY output low
for the corresponding number of ClK periods.

MOTOROLA Interface
The DACO has an asynchronous interface for 68000
systems when 11M is strapped low. Bus transfers

3-90

The DACO provides a programmable READY or
DTACK Generator for bus access to the HSDA
memory in order to insert a sufficient number of wait
states in the processor's bus cycle. This allows to
use various types of memories and access structures without the need for additional hardware. The
READY (DTACK) line may be delayed by 1 . . . 3
ClK periods, depending on the delay register value.

SDA 8800
Bus access to the internal registers should not require any wait states with all popular microprocessors, thus the DACO provides the READY (DTACK)
signal without any delay in programming cycles.

cessing the HSDA memory. Thus RDA has to be
programme~ to 0 (then it is ignored) or to a value
greater than RDY.

The DACO provides two insertion mode:

Programming Cycles

1) Insertion of wait states into every DMA or DPAC
bus cycle. The number of the wait states can be
programmed via the RDYO and RDY1 bits of the delay register.

Programming cycles can be initialized from each
mode at any time by read or write accesses to the
DACO via its microprocessor interface. In general all
changes of the register contents will affect the operation of the DACO immediately.

2) Insertion of wait states at address transitions only.
This dynamic insertion mode which can be applied in
DMA based systems only reduces the number of
wait states significantly. When reading the HSDA
memory all SRAMs are enabled continuously. As a
consequence wait states need only be inserted in
the first bus cycles after each address transition until
all the memories data become valid (see Figure 3).
On the contrary, when writing the memories, wait
states are necessary only in advance of each address transition-provided that data latches form the
connection between data bus and memories, so that
all memories can be written at once (see Figure 4).
The number of wait states can be programmed via
the RDAO and RDA1 bits of the delay register (See:
Application examples: How to use slow SRAMs).
If both, the RDY and RDA delays are set the DACO
will apply RDA to each bus cycle at address transitions and RDY to all the remaining bus cycles ac-

If the DACO is in DA or DT mode, programming cycles may be executed without interrupting the
DAIDT process, as far as no relevant parameters
are changed.

Note:
Each microprocessor write access to the status register effects immediately a termination of the current
operation mode and the DACO enters into the programmed mode via the idle mode. When changes of
the status bits occur, e.g. at the end of a DAlDT-process or via programming, the DACO disables further
programming of the status bits for 8 ClK periods.
The programming of single bits of the parameter and
the transfer control registers can be done very easily
by the use of the corresponding mask registers. If a
mask bit is set (high) the corresponding bit will not
be changed and vice versa. Thus additional read cycles and bit manipulations by the microprocessor
can be avoided.

Dynamical Wait State Insertion (Acquisition System-DMA Read from DACO)
Buscycle

A,

X~

__________________~X~______

AO_+_1_____

u

READvalU

iSTACKbl

, Clif,cl

Clif,d)

c:J

u

tJ tJ

~

r.J l

-~'----~

DECEN

a) for IAPX systems
b) for MOTOROLA systems

c) 4 channels systems (1 DASR)
0115-3
d) more than 4 channels, with address decoder

Figure 3

3-91

SDA 8800
Dynamical Walt State Insertion (Latched Data Transmission System-DMA Write toDACe)
Buscycle

A,

u

READYa)

OTACKb)

CH5, c)

CH5,d)

0115-4

a) for IAPX systems
b) for MOTOROLA systems

.
c) 4 channels systems (1 DASR)
d) more than 4 channels, with ~ddress decoder

Figure 4

Idle Mode
In the idle mode the DACe is in a "do nothing" condition. It is entered at a hardware reset, a software
reset (SO = S1 = 0) or after finishing a DMA process according to the state diagram of Figure .2.
When the idle mode is entered via a hardware reset,
all counters and registers of the DACe are set to
zero. However, if the idle mode is entered via software, the contents of the counters and registers will
not change, the output lines with exception of INTR
will be switched to the inactive state and DO ... 07
will be set to input. It is recommended to program
the DACe in the idle mode only and start the next
transaction by changing the status bits in the last
programming cycle.
The DACe changes from one operation mode to another always via the idle mode.

Data Acquisition/Transmission Mode
In the data acquisition/transmission mode the
DACe will activate the HSDA-system. It is characterized by both status bits being set. The DACe can
distinguish data acquisition from data transmission
by the value of the DIR bit of the status register,
Each acquisition/transmission process starts at the
start address Ao.

3-92

Two operating modes, depending on the LIS bit of
the status register, are supported (see Figure 5):
-Loop mode
- Start/stop mode
Depending whether the start/stop or the loop m~de
is used, the trigger input accommodates,for starting
or stopping the DA/DT process, respectively. In DA
systems, both the pre- and posttrigger function can
be provided in the loop mode only. Thus, the loop
mode will be preferred for DSe or Logic Analyzer
applications. The start/stop mode can be regarded,
as a "single shot" with potential, but not exclusive
applications in the field of arbitrary waveform generation or other DT systems. It provides the posttrigger
feature only.

Trigger Counter
The trigger counter is loaded with the trigger register
contents when entering the DAIDT mode. The external trigger input is sampled at the positive edge of
the DACLK if the DACLK is active or level-triggered
asynchronously if not. When TRIG is sampled low,
the internal 16-bit trigger counter, which was set to
the predefined value from the pre-/posttrigger re~is­
ters up to now, is started. At each DACLK leading.
edge the trigger counter is decremented by 1. By

SDA 8800
reaching OOOOH, the DT/DA process is started or
stopped and the trigger counter is reloaded. An extended posttrigger range can be chosen by setting
the EP-(Extended Posttrigger) bit of the status register. With this extension the DACO provides,a posttrigger range of 1 million DACLK periods! In the DA
loop mode the trigger recognition circuit is sensitive
to the falling TRIG edge. The DACO assures that the
whole active memory range is filled up with data by
gating the trigger input during the first loop (see Figure 5b). The trigger counter is not retriggerable. If a
trigger events the DACO is insensitive to further triggering until the current operation cycle is finished.

Address Counter
The address counter generally is loaded with Ao
when entering the DAIDT or DMAIINT mode. As an
exception the content of the counter is maintained
over DA-Ioop mode to DMA transitions. At each data
acquisition or data transmission process, a sequence of consecutive addresses is clocked out of
the DACO. by each DACLK leading edge. The address range is defined by the current values of the
start and stop address Ao and An, respectively. With
its fully programmable 16-bit address counter, the
DACO can process up to 65.536 groups of (parallel)
samples. Also, Ao and An may define an address
range between any two. address locations.
Optionally, a 4-bit prescaler can extend the address
range to 20-bit when the Extended Address (EA) bit
of the parameter register is set. In this configuration
Ao and An can be set to each 16th address location,
Le., the prescaler is always set to OH and compared
to FH. The full 20-bit counter value can be read via
the virtual address readback registers (see Table 1).

Note:
If the programmed stop address equals the programmed start address the whole memory range will
be passed through. Furthermore, setting the stop
address one or two addresses higher than the start'
address is forbidden.

DMA/lNT·Mode
In the DMAIINT-mode the status bits SO, S1 of the
DACO have to be set to 1 and 0, respectively. This
can be done ,either by programming the appropriate
value, or by entering the DMAIINT-mode automatically after a DAIDT process has been completed. In
this case the status bits are set internally.
When entering the DMA/INT-mode, the DACO raises its DRO line in order to signal the DMA-controller
that it requires a DMA service. The EOD bit of the

transfer control register controls the activation time
of the DRO line, hence source and destination synchronized and unsynchronized DMA transfers can
be implemented. When high, DRO is activated
throughout the complete DMA transfer of all data
within the range defined by the start and stop address. In this case the DACO controls the length of
the DMA transfer. When low, DRO is deactivated in
the first DMA transfer cycle. The DRO signal is
cleared also when the DMAIINT mode is left.
The INTR line is activated in order to request for
programming cycles after some DMA sequences
whose length are controlled by the DACO (see Operational Description and Table 4). If the INT bit of
the parameter register (see Tables 2, 3) is set, the
DACO will assert INTR pulses together with DRO for
all applications where an interrupt to th'e CPU should
be issued after DAIDT in order to obtain any kind of
service, for example DPAC. In general, the INT bit
will be set in systems without a DMA controller, because the DRO signal cannot be used there. Additional INTR pulses are issued at some error conditions. At any time when INTR is asserted, DACO
sets a bit of the interrupt register characterizing the
exact reason of the interrupt (see Table 3c). The
INTR signal as well as the INT-register itself will be
cleared by the first read cycle accessing the INTregister.
For DMA transfers the cache memory data are accessed by read-or write cycles when DACK is asserted. Note, that the DIR bit has to be set in accordance with the direction of the data transfer, otherwise an INT7 will occur. If the SC-(Single cycle) bit is
set, the RD and WR lines are interchanged internally. In 68xxx systems, the R/IN line is interpreted inversly and no DTACK but the DRDY signal is issued.
The DACO provides all signals needed for the transfer of data between the system data bus and the
HSDA memory, regardless of the data bus width. 8-,
16- and 32-bit data buses can be supported by programming the BWO and BW1 bits of the transfer
control register appropriately. In the same way the
number of DASR's in the system has to be adjusted'
correctly. On RESET, the DACO is programmed for
8-bit data buses and 1 DASR.
In a DMA transfer cycle, the DACO will continuously
apply addresses and channel select signals to the
HSDA memory in order to maintain the correct order
of the transferred' data. Normally, the DACO will
transfer the data in ascending order, starting with
channel 0 at the starting address. However, when
the DACO changes from the DA loop mode to the
DMA mode automatically, it will start transfers at the
address that contains the "oldest" data (Ak) as it is
shown in Figure 6.

3-93

SDA 8800
Start/Stop vs. Loop Mode (Data Acquistlon)
Trigger
count

FFFFH

~Trigger
_ _ _ _ _ _ _ _T_r_ig_gerRan_g_e_ _ _ _ _ _ _ _ _ _ _ _ _ _ ~Trigger

BFFFH
7FFFH
3FFFH
OOOOH

Address Ranbe
510p
Address

51arl

Addres,

r--r--~~----------

b) Loop Mode

a) StartlStop Mode

0115-5

FigureS

DPACMode
The direct processor access mode is mainly important for low end HSDA systems. In this mode the
fast HSDA memory can be made part of the system
memory temporarily. The DPAC-mode can be entered by programming the DACO status bits SO, S1
to 0, 1. When entered, the DACO will activate its
~ line and tristates its cache memory address
bus In order to allow the processor to access the
memory via its own address bus. If an external address buffer is used, its drivers can be tristated by
the AEN line of the DACO. DPAC cycles have to be
performed via the normal data, address and control
buses of the processor and the DACO has to be
addressed by its MCS (memory chip select) line.
In DPAC mode, the DACO aut~maticallY uses the
required address lines and, depending on the system COnfigUrationi:rsvides the correct channel select signals at its H i and DECEN outputs (see Tables 5, 6, 7). For example, if the system is equipped
when an 8-bit wide data bus and 1 DASR, the DACO

3-94

uses the lowest two address lines (AO, A 1) to select
1 of the 4 channels of the HSDA system to be accessed.
By using the DPAC mode, the processor can make
any modification of the data in the HSDA memory
and, after its completion, return to a DTIDA cycle
again. Then the DACO has the complete control of
the HSDA system and the processor can perform
other tasks with its remaining system memory simultaneously. Note, however, that the DIR bit has to be
set in accordance with the direction of the data
transfer, otherwise an INT7 will occur.

Operational Description
Bus Operation
The DACO provides an asynchronous interface to
80xxx, 80xx and 68xxx systems are strapped b~
It is addressed via CS for ~ramming, via
for DMA transfers and via MCS for DPAC.

SDA 8800
DMA Transfer for the Loop Mode
FFFF(F)

DMA·transfer
Stop Address An

Ao

Sta rt Add ress Ao

0000(0)
0115-6

Figure 6
After RESET, the DACO first has to be programmed
for its specific task. This requires a number of write
operations to its internal registers. It is recommended to perform this programming sequence from the
idle mode (SO = S1 = 0) and alter the status bits by
the last write command.
Note:
The DACO will accept programming bus cycles from
any operating mode, however, it will accept DMA or
DPAC bus cycles in the corresponding mode only.

Data Acquisition
In data acquisition systems, normally the DA mode
will be entered after programming. In the startlstop
mode (LIS = 0), the DACO will enter a DA waiting
state. It continues to activate its HOLD line, thereby
keeping the clock system of the DASR disabled and
expects to receive a trigger pulse. Upon this event it
releases its HOLD line. As a consequence DACLK
will become active and start to decrement the trigger
counter. By reaching OOOOH, it starts the address
counter and the data acquisition process will take
place by writing data to the HSDA memory in the
address range as previously defined by the start and
stop addresses. This sequence guarantees a virtually constant time delay from the trigger event to the
stored data range. This is important for time critical
applications.
In the loop mode (LIS = 1) the trigger pulse is sampled by the positive DACLK edge. Thus an inherent

time uncertainty between 4 and 16 samples is introduced into the delay from the trigger event to the
stored data range according to the DACLK period.
On the other hand, the pretrigger characteristics can
be realized in the loop mode only. As a consequence it might be necessary to measure the trigger
offset with respect to the DACLK by a fast external
hardware and correct it appropriately by the microprocessor system for all these systems that require
the pretrigger and cannot tolerate the time uncertainty.
According to Table 4a six different operating sequences may be chosen by setting the AA, EOD and
LIS bits for DMA based systems. These operational
sequences also can be seen from the state diagram
of Figure 2. With low performance systems, the
DPAC mode may be the preferrable choice for further data processing. In this case, all sequences
have to be performed via programming according to
Figure 2.
DMA based systems need some more detailed evaluations.
In all sequences the DACO will activate its DRO line
when entering a DMA cycle. The length of the DRO
pulse is determined by the EOD bit. Additionally the
DACO can assert its INTR line together with DRO
for all sequences but sequences 3 and 4 in order to
support easy communication with the processor in
DPAC based systems if the INT bit is set. In the
sequences 3 and 4 (characterized by AA = 0 and
EOD = 1) the INTR line is issued when entering the

3-95

SDA 8800
idle mode after a source synchronized DMA operation in order to signal the processor the end of the
sequence.
.

Data Transmission
In data transmission systems the HSDA memory
usually has to be loaded after the initial programming sequence. This can be done in the DPAC
mode or in the DMA mode. In systems employing
DPAC all mode transitions have to be performed via
programming, according to Figure 2. DMA based
systems allow for additional mode transitions. All
possible operational sequences that can be chosen
by the AA, EOD and LIS bits are summarized in Table4b.
Generally, it is anticipated that the beginning of the
data transmission process has to be exactly controlled. For this reason a DT waiting state is provided
in all operational sequences. When entering this
state the DACO releases the HOLD line but provides

the start address at its address port until a trigger
has occurred and the trigger counter is decremented
to OOOOH. Additionally, all operational sequences but
sequence 8 (AA = EOD = LIS = 1) enter the idle
mode before DT in order to avoid unintended DT
processes.
In startlstop mode data transmission the AA bit controls whether repeated DT processes, released by
consecutive trigger pulses, but with the same memory content should occur (AA = 0), or whether the
HSDA memory content should be updated after
each DT process (AA = 1). Loop mode DT processes have to be interrupted by programming in any
case. In the DT mode, the DACO will activate its
DRQ line upon entering the DMA mode, and it will
activate its INTR line in se~uences 3, 4 and 7 upon
entering the idle mode in order to obtain a programming cycle from the processor. The latter sequences
are characterized by EOD = 1 which enables the
DACO to detect the end of the DMA cycle. If the INT
bit is set, additional INTR pulses are issued in sequences 5 and 7 when entering the DMA mode.

Table 1 Register Selection
Adrl

2

1

0

0

0

0

0

Start Address Low Byte

R/W

0

0

0

1

Start Address High Byte

R/W

0

0

1

0

Stop Address Low Byte

R/W

0

0

1

1

Stop Address High Byte

R/W

0

1

0

0

Address Low Byte, Ao ... A7

0

1

0

1

Address High Byte, As ... A15

0

1

1

0

Address/Trigger Extension Nibbles,
A16·· .A19, T16··· T19

0

1

1

1

Interrupt

RW

1

0

0

0

Pre-/Posttrigger Low Byte

R/W

1

0

0

1

Pre-/Posttrigger High Byte

R/W

1

0

1

0

Delay

R/W

t

0

1

1

Status

R/W

1

1

0

0

Transfer Control

R/W

1

1

0

1

Transfer Control Mask

1

1

1

0

Parameter

1

1

1

1

Parameter Mask

Note:
1. A16 ... A19 read only.

3-96

R/W

Register Name

3

R
R

R/W(1)

R/W
c

R/W
R/W

SDA 8800
Table 2. Register Bit Map
Bit Mapping

5

4

3

2

1

0

Transfer Control

SC

EOD

SR1

SRO

BW1

BWO

Parameter

EA

EP

6

7

Delay

TO

AA

LIS

INT

RDA1

RDAD

RDY1

RDYO

Interrupt

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INTO

Address/Trigger Ext.

T19

T1B

T17

T16

A19

AlB

A17

A16

DIR

S1

SO

Status
Table 3a. Transfer Control
Register Bit Description
BWO,
BW1

Bus Width:

SRO,
SR1

Number of
DASR'sin
System

EOD

High: DRO is activated as long as the
whole address range defined by the
start and stop addresses is transferred.
low: DRO is activated at the beginning
of the DMA-transfer only.
Single Cycle: If set, the DACO
interchanges its RD and WR .!!!les upon
DMA access or interprets R/W inversly.

SC

BW1
0
0
1
1

BWO
0
1
0
1

SR1
0
0
1
1

SRO
0
1
0
1

Table 3b. Parameter Register Bit Description
INT

Interrupt/DMA Mode:
High: INTR is activated together with
DRO.
low: INTR is not activated together with
DRO.

LIS

High: loop mode
low: Start/stop mode

AA

Auto-Acquisition: This bit controls the
operational sequences according to Table
5.

TO

The trigger occurred bit is cleared when
entering OAiDT mode and set by the first
detected trigger pulse.

EP

Extended Posttrigger: When set, the
trigger counter is extended to 20-bit
thereby widening the posttrigger range of
the DACO to 1 Msamples.

EA

Extended Address: When set, the
address bus is extended from 16- to 20bit.

a-bit
16-bit
32·bit

1 DASR
2DASR
3DASR
4DASR

Table 3c. Wait State Programming
RDY1
RDA1

RDYO
RDAO

Number of
Delay ClK Cycles

0
0
1
1

0
1
0
1

0
1
2
3

3-97

SOA 8800
Table 3d. Interrupt Source Description
INTO

(I NT = 1) Data transfer or data
modification in HSDA memory required
(e.g. after DA if finished).

INT1

All transactions completed, DACO enters
the idle mode and expects further
instructions from the processor.

INT2

DMA address range overflow (EOD = 0)
or DMA-transfer requests unallowed in the
current DACO mode.

INT3

Reserved

INT4

Reserved

INT5

Reserved

INT6

Reserved

INT7

Direction error (DIR bit didn't correspond
to the direction of microprocessor
access), bus cycle terminated without
valid data transfer.

Table 3e. Status Register Bit Description
SO, DACO S1 SO
S1 Status: 0 0 Idle
0 1 DMA-!ransfer
1 0 Direct Processor Access
1 1 Data Acquisition/Transmission
DIR Direction Bit:
/DPAC read/DMA
Low: Data Acquisition
read
High: Data Transmission /DPAC write/DMA
write

Table 4. DMA Based Operational Sequences

AA

EOD

Sequence

L/S

No.

a) Data Acquisition Systems

0

0

0

DA w - T - DA - (!!) DMA d, u. - P

1

0
0

0

1

DA - T - (II) DMA d, u - P

2

1

0

DA w - T - DA - DMAs - (!) Idle

3

0

.1

1

DA - T - DMA s - (!) Idle

4

1

0

0

not permitted

5

1

0

1

not permitted

6

1

1

0

DA

1

1

1

DA - T - (!!) DMA s - DA

w-T - DA - (!!) DMA s - DA w

7

8

b) Data Transmission Systems

0

0

0

DMA s, u - P - DT w - T - DT - DT vi - T - DT - ... - P

1

0

0

1

DMA s, u - P - DT w - T - DT - P

2

0

1.

0

DMA d - (!) Idle - P - DT w - T- DT - DT w - T - DT - ... P

3

0

1

1

DMA d - (!) Idle - P - DT w - T - DT - P

4

1

0

0

DMA s, u - P - DT w - T - DT - (II) DMA s, u

5

1

0

1

Not Permitted

6

1

1

0

DMA d - (!) Idle - P - DT w - T - DT - (II) DMA d

1
1
1
T = Tngger
P = Programming
d = destination synchronized

3-98

DMA d - DT w - T - DT - P
u = unsynchronlzed
s = source synchronized
w = waiting

7

8
(I) = INTR to CPU ISSUed
(!!) = INTR to CPU issued, if INT·bit is
set

SDA 8800
Table 5. Address Decoding Adrl -

3

CHSI (Direct Processor Access Mode)

8-bltBUS

1 DASR

2DASR

3DASR

4DASR

Adr-Lines
used for
decoding

AdrO, Adr1

AdrO-Adr2

-

AdrO-Adr3

CRSl

Adri
2 1

CHSi
1 0

0

3

2

1

0

EN

3

2

1
1

1

0
1
1
1

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
0
0

0
0

0

0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0
0
0
0
0

0
0
0
0

0 '0
0 1
1 0

1
1
1

1

1

0

1
1
1
1

0
0

0

1
1

0

1
1
1

1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1

1

0

1
1
1
1

0
0

0

1
1

0

1
1
1

0

1

0

1

1

1

1

0
1
1
1

0
1
1
1

0
1
1
1

1
1
1

0
1
1
1

0
1
1
1

0
1
1

0
1
1
1

0
1
1
1

0
1
1
1

1
1

1
1
1

1
1

1

EN

3

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

2

CHSi
1 0

CRSl

EN

not
applicable
for
DPACmode

3

2

1

0

EN

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

Table 6

3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

16-bltBUS

1DASR

2DASR

3DASR

4DASR

Adr-Lines
used for
decoding

AdrO

AdrO, Adr1

-

AdrO-Adr2

Adri
2 1

0
0
0
0
1
1
1
1
0
0
0

0
1
1
1
1

0

3

2

0
0

0

1
1
0

0

0

1

1
1

0

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
1
1

1
1

0
1
0
1
0
1

0
0

0

1
1

0

1
1

CHSi
1 0
1

0

0

1

1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1

0
1
0
1
0
1
0
1
0
1
0
1

EN

3

2

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
0
1
1
1
0
1
1
1
0
1
1
1

1
1

0

0
1
1
1
0
1
1
1
0
1
1
1
0
1

CHSi
1 0
1

0

0

1
1
1
0
1
1
1
0
1
1
1
0
1
1
1

1
1
1
0
1
1
1
0
1
1
1
0
1
1

EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

3

2

CHSi
1 0

not
applicabl,e
for
DPACmode

EN

CHSi
1 0

3

2

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
0
0

0
0

(J

1
1

0

1
1
1
1
0
0

0
0

0
0
1
1
1
1

1

1
0
1
1 0
1 . 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1

EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

3·99

SDA 8800
Table 7
32-blt BUS

, 1 DASR

Adr-Lines
used for
decoding

-

3

Adri
2 1

0

3

2

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

O.
0
0
0
1
1
1
1
0
0
0
0
1
1
1 ,
1

O'
1
0
1
0
1
0
1
O.
1
0
1
0
1
0
1

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
1
1
0
0
1
1
O·
0
1
1
0
0
1
1

~bsolute

AdrO

CHSi
1 0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

2DASR "

0
0
0
0
0
0
'0
0
0
0
0
0
0
0
0
0

EN

3

2

0
0
0
0
0
0
0
0
'0
0
0
0
0
0
0
0

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

'x
x
·x
x
x
x'
x
x
x
x
x
x
x
x
'x
x

CHSi
1 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

EN

3

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

2

3DASR

4DASR

-

AdrO, Adr1

CHSi
1 0

EN

not
applicable
for
DPACmode

3

2

1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O.

1
1
0
1
1
1
0
1
1
1

CHSi
1 0

1
0
1
1
1
0
1
1
1
0
0 1
1. 1
1 1
1 0
0 1
1 1

EN

0
1 .
1
1
0
1
1
1
0
1
1
1
0
1
1
1

0
0
0
O.
0
0
0
0
0
0
0
0
0
0
0
0

Maximum Ratings·

+ 70°C
+ 150°C

Ambient Temperature Under Bias .... O°C to
Storage Temperature .......... -65°C to

Voltage on Any Pin with
Respect to Ground ........ - 0.3V to VDD

+ 0.3V

.• Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

DC Power Supply .................. -0.3V to 7.0V
Power Dissipation ........................... 1W

D.C. Characteristics TA = O°C to 70°C, Vee = 5V ± 10%
Parameter

Symbol

Limits

Conditions
Min

Units

Max

Input Low Voltage

VIL

-

0

0.8

V

Input High Voltage

VIH

-

2.0

VDD

V

IOH

3.5

-

V

Other Outputs:, 3.2 mA

-

0.4

V

70

pF

Output High Voltage

VOH

Output Low Voltage ME,
MWE,DT/R,READY, HOLD

VOL

Load Capacitance

CL

3-100

= -2.8mA
IOL = 6.4 mA

SDA 8800

A.C. Characteristics TA = O·Cto +70·C, vee = 5V ±100/0
Timing Requirements: all timings measured at 1.5V unless otherwise specified
No.

Parameter

Limit Values

Symbol
Min

Typ

Units
Max

1

Di Delay

35

ns

2

Adri Hold

3

ns

3

Adri to Data Valid Setup

42

ns

4

Command, Select Pulse Width

150

ns

5

Select to Command Setup

3

ns

6

Select Hold

3

ns

7

Di, DEN Hold

15

ns

8

RD to Di Float, DEN low Delay

23

ns

9

DECENDelay

10

CHSiDeiay

26

ns
ns

11

Di Setup

30
15 (5)(a)

12

DiHold

15

ns

13

Adri, R/W Setup

5

ns

14

Adri Hold

ns

15

MCS, DACK to ClK Setup

15 (10)(a)

ns

16

DTACK, READY High Setup

30

ns

17

MCS, DACK to DTACK, READY Delay

18

ns

18

ClK High to DTACK, READY Delay

18

ns

25

19

MCS, DACK to DTACK High Delay

20

DTACK Active High Pullup

21

ClK Period

22

ClK High, low

23

DAClK Period

24

DAClK High, low

25

WR (CS, DACK) Inactive Setup

26

ns
~

40

Test
Condition

35

ns

- 20

ns
ns
ns

40
16

ns

ClK to Control, Ai Delay

26

ns

28

DAClK to Ai Delay

20

ns

29

TRIG to HOLD Inactive Delay

20

ns

30

DAClK to HOLD Active Delay

28

ns

7

ns

27

ns

31

HOLD to ClK Setup

32

Address Valid

33

TRIG to DAClK Setup

34

TRIG Pulse Width

35

Command, CS to ME, HOLD
Inactive Delay

>t23

36

DRQ, INTR Inactive Delay

40

ns

37

TRIG Hold

3

ns

Note:
(a) Timing specifications for Motorola 68 xxx systems (11M strapped low).

3-101

S~A

8800

SIEMENSIINTEL Interface Bus Cycle Timing

__-+-_--,. 1+-----{4>---"1=~t:::L__
im', Wi!"

,(write)

~,DACK

CRS;

tmm"
O,PAC
OMA
mod

A,

Mr (OMA write, ROAO,1 >0)

@
ORO

CLK
0115-7

3-102

SDA 8800

MOTOROLA Interface Bus Cycle Timing

14

RrW

-"

~

-..-l
----I

t;j\

@
\

~---"'j

~

I

0, (read )
Prog
mod

~
/

DEN (re ad)

r---=@--I @
;t

D,(write)

~---.!

;t

-

@I+-

----I

(9)-

\.

DTACK

ji

\

MCS,DACK

----t

... - ------ --- -- ---- --DECEN

DPAC

'"

1'9'-

.>

/ -----~~~------------ .

\

./--j

@r)i

Ai

DM'"

--j

mode

@~ ,..-

\

J

iiiit(DM A write, RDAO,1 >0)

['--

~@-1
~
CLK

~

~

(0) In systems using the DPAC mode a sufficient MCS to Adr hold time has to be provided in order.

0"5-B

3-103

SDA 8800
DTACK, DRDY Programming
ClK

-----~:-i\-----::\+-------.;-

\
Programmed value:

-----------"""

\

o

3
0115-9

READY Programming
ClK

WR.iffi

@
READY

@

.'

Programmed value:
0115-10 '

ClK-lnputs

ClK

DAClK

0115-11

3-104

SDA 8800
IDLE-DA
CLK

MWE

DIRC

RESD

--+G>
.,

....................:.1.1=------------

HOlD

fRiG
DACLK
111 him

AI a)

ance

AI b)

Idle

Transition

Data AcquIsition
011',-','

(a) Loop mode
(b) Start/Stop mode

IDLE-DT
CLK

ME
H

MWE
H

DIRC

RESD

HOm
TRIG

DACLK

Ai

hi him edance

Idle

Transition

Data Transmission

DTw
I

Trogger count = OOOOH
0115-13

3-105

SDA 8800
DA-IDLE
CLK

ME

H

-. GY .MWE

I
3CLK

DIRC

/

Peroods

\

RESD

HOi])
H

TRIG

~

'DACLK

Data AcquIsition

(a) depends on 'Ii programmed as DAS

3·106

hiahomDeda nee

An

Ai

Transition

I

Idle
0115-14

SDA 8800
DT-IDLE
ClK

ME

:
,

H

liiiWt
3ClK

H

DIRC

Period~

/

,,
,,
,,,
,,
,,
,,
,

,

RESD

\

Filml
H

i'iiiG

\

DAClK

hlghlmpedance

An

Ai

Data Transmission

Tran~itlon

I

Idle
0115-15

(a) depends on W programmed at DAS

End of DT-mode by Programming

DIRC

DT/if

HOLD

DAClK

(a) depends on programming of W at DASR

0115-16

3-107

SDA 8800
DMA/Prog - DT - DMA Cycle
CLK
WR «(5, OACK)
CH51,OECEN

DIRC
DT/R

HOLD

TRIG
OACLK

INTR,ORQ
DMAwnte
Prog.

I

OT

Transition
Trigger count =OOOOH

0115-17

\

c)

I·

3-108

Transition

DMA
write
0115-18

SDA 8800
DMA/Prog - DA - DMA
CLK
WR ((5, DACK)
CH51, DECEN

DIRC
DT/R

TRIG

~r---m----------t-----------------------------~..-,~---------------------~--------

xxxxxxxxx~

\.

DACLK

XXXXXXXXX

AI
DRQ,INT

. DMAwrite
Prog.

I

Data Acquisition

Transition

0115-19

TransItion

DMA
read
0115-20

(a) Loop
(b) Start-Stop
(e) depends on

Wprog. at DASR

3-109

SDA 8800

Pin Definitions
Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

ADRO
ADR1
ADR2
ADR3
DPAC
DT/R
i5ECEN
CHSO
GND
VDD
C'RS1

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

A2
A1
AO
MWE
ME
DIRC
DAClK
GND
VDD
RE'SD

CRS2
CHS3
AEN
A19
A 18
A17
A16
A 15
GND
A14
A 13
A12
A 11
A10
VDD
A9
A8
A7
A6
A5
GND
A4
A3

Ordering Information
Type

Ordering Code

SDA8800

Q67000·Axxxx

3·110

FiC5IJ)

TRiG
11M
ClK
RESET
INTR
READY
DRQ
DACK
MCS

OS
WR
RD
DEN
GND
VDD
DO
01
02
03
04
05
06'
07

les for Industrial Applications

SIEMENS

SAB 0600, SAB 0601, SAB 0602
Three-Tone Chime,
Single-Tone Chime, Dual Tone Chime
Three-tone chime SAB 0600
This Ie generates the tone sequence of a 3-tone chime. The sound pattern is created by
three harmonically tuned frequencies which are switched in succession to a sl:lmming point
and decay individually in amplitude.
The tone color is adjusted by an external RC network (R" C" and C2). An 8 Q loudspeaker
can be connected directly via a 100 IlF capacitor.
An appropriate design of the loudspeaker housing (shaped as tube or horn) enhances the
volume and tone quality and contributes to a pleasant, melodious sound.

Features
•
•
•
•

Melodious sound
Few components required
Integrated output stage for 8 Q loudspeaker
Standby current < 1 IlA

Single-tone chime SAB 0601 and dual-tone chime SAB 0602
The two variants SAB 0601 and SAB 0602 were derived from type SAB 0600 by suppressing
the last two tones or last tone, respectively, of the three-tone sequence. The SAB 0600 data
applies correspondingly.

Maximum ratings
Supply voltage
Input voltage at E
Neg. input current at E
Load resistance at Q
Current consumption at
start of tone sequence
refer to
end of tone sequence
measurement circuit
Oscillator frequency at C
(due to power dissipation)

Vs
VE

Lower
IimitB

Upper
limit A

-0.5
-0.5

11

-IE
RL

J

Vs

2

rnA
Q

90
35

rnA
rnA
kHz

150
125

°c
°c

120

K/W

7

ISM

Iso
fosc

6

Junction temperature
Storage temperature

TJ
Tstg

-55

Thermal resistance (system-air)

RthSA

V
V

Operating range
Supply voltage
Ambient temperature
Oscillator frequency at C

Vs
Tamb

fosc
4-1

I~

111
70
100

IV°c
kHz

SAB0600
SAB0601
SAB0602
Characteristics
Vs = 7 V to 10 V;

max
10
35

Vopp

<1
20
0.16
2.8

.1VOM

±5

25 °C

Standby input current
Supply current with open output
Max. output power at 8 Q (tone 3)
Max. output voltage at Q (tone 3)
Deviation of the max. individual
amplifudes referred to tone 3
Frequency variation of basic
oscillator with R1• C1 = const.
Triggering voltage at E
Input current at E (VE = 6 V)
Noise voltage immunity at E
Triggering delay at fo = 13.2 kHz
(td varies in inverse proportion to fo)
Min. value of external load resistor
Max. value of external load resistor

4·2

typ

min
Tamb =

. 10
Iso

Po

.1fo
VE

IE

R1
R1

%

±5
1.5
500

VENPP
td

4.0

Vs
700
0.3

2

5
10
100

IJA
mA
W
V

%
V
IJA
V
ms

kQ
kQ

SAB0600
SAB0601
SAB0602
M...urement circuit
R,
33kO

SAB 0600
4 GNO

2 Vs

~-{1=k0:::J--'-_ _ _ storage

Jaw-type probe

OSC Is =fftJ

Rt

[tT100fjF

Vs

Figure 1

Integral current consumption in the measurement circuit

mA
120

~mA

eo

.........

0 r-... ~

60

" '"

V" "

i'oo....

2

6

Typical run
at Vs = 10V and
'ose = 13.2 kHz

20

o

;,-Max. permissible limi t value

o

3

~

4

~

150= 35mA

>--

............. r---

5

7

8

9

10 s

-t
Figure 2
4-3

SAB0600
SAB 0601
SAB0602
Block diagram

-----.----t-----,>--------------~-----.

E

Power supply

Triggering

Digital tone generation

Summing pOint circuit

I
I

lOkt±l!
Figure 3

4-4

+

o

~

SAB0600
SAB0601
SAB0602
Typical application circuit

o---------_..::E'-I1

.8 L C2 100nF

Vs

~0--------------"-I2

7... 11V

7 R 33kQ

6 (

5

Figure 4

Functional description
The three frequencies - 660 Hz, 550 Hz, and 440 Hz - are obtained by dividing the output of
a 13.2 kHz oscillator. One of these three frequencies is divided again to obtain the time base
for the tone-decay process. From this time base, 4-bit D/A converters (one for each tone)
generate the decay voltage with which the three tones are successively activated and, overlapping each other, are attenuated. The basic frequency is determined by an external Re
network (pins R and e).
The output stage can drive an 8 Q loudspeaker with approximately 0.16 W via 100 J.LF. The
output voltage is of square shape. To obtain a melodions output tone as required, the
higher harmonics may be reduced by shunting pin L through a suitable capacitor to ground.
The output volume can be regulated here by means of a potentiometer.
The circuit only draws current in the active state, and automatically switches off after the
tones have decayed. The circuit is activated by a short pulse, between 1.5 V and Vs in
amplitude, applied to the triggering connection E (pin 1). If the trigger voltage is still, or again,
present when the tones have decayed, the three tones are repeated.
The circuit is not activated when a trigger pulse on E is shorter than 2 ms (interference
suppression).
To prevent triggering of the circuit by cross-talk voltages, especially in case of long input
lines, the noise voltage peaks should be limited to 0.3 V at the Ie input. For this purpose
the control line (possibly in front of a series resistor) can be shunted to ground through a
suitable capacitor.

4-5

SAB0600
SAB0601
SAB0602
Application for ac and dc triggering (figure 5)

The input can alternatively be triggered with direct or alternating 'current. An internal diode
circuit hereby short-circuits the input for negative halfwaves.
The peak voltage of the positive halfwave is added to the battery voltage. A series resistor
must be connected into the trigger line to limit the voltage at input E (pin 1) to a maximum
value equal to Vs.
The minimum input current at pin E of the SAB 0600 (pin 1) is 500 IlA at 6 V. If the voltage
drop occurring at 500 IlA at the series resistor R3 (figure 5) amounts to at least the ac peak
voltage between A and B WAS -), the Ie will be safe.

R

The formula

-

3 min -

\i:AS max.
500 IlA

determines the lower limit for R3 .
The upper limit for R3 is determined by the lowest trigger voltage between A and 0 (pin 4).
In the application shown in figure 5, this will be the battery voltage if the device is also to be
operated independently of the bell system (triggering by short circuit of A and B).
For reliable triggering, the SAB 0600 requires a current of at least 50 IlA with approx. 1.5 V
at pin E. Assuming this current, the voltage drop at R3 must, therefore, not exceed Vs - 1.5 V.
R

The formula

_

3 max -

Vs min. -1.5 V
50llA

results in the upper limit for R3 .

calculation example for the circuit in figure 5

max. VAS rms = 25 V

==

max. V'AS = 25 V x

v'2 =

35.4 V

35.4 V = 70.8 kO
500 llA

min. Vs=6V
(The operating range of the SAB 0600 may extend to 6 V for individual components).

,R3 max

=

6 V -1.5 = 90 kO
50llA

In this example, a value of 82 kO

4-6

± 10% would be suitable for R3•

SAB0600
SAB0601
SAB0602
Circuit for SAB 0600 application in home chime installations utilizing
ac and dc triggering; adjustable sound and volume

u..

c

~

c::0

:;::
~

...J

co

r-

OJ

Ln

C1.

0

(DO
....
OJ
:t:
"Ei
....Cl .Dc:I
....
C.

:§
..z

tTl

d

0

IS

0

.!:

~

"C

....ucu

c:I

III
VI

cu
c
c

~
OJ
c:
>-

0

u

C£

cu

....Qj:>

.c
>-

-0

Cl

e

III
.D

Cl

4i
.c.
.!!!

...
c0

0

1....0

Z

~I

:;::
c

....cu

<

«

IX!

U!J

CU~

._N
...IN

...

-

x~>g;

- - - - j - - ' - - - - - t - -...- - - - - - - - ~\C ~

FigureS

PCB layout information: Because of the high peak currents at Vs, Q, and 0 (ground) and to
avoid RF oscillations, the lines should be designed in a flatspread way or as star pattern.
Star points are the terminals of capacitor C4 •
4-7

SAB0600
SAB 0601
SAB0602
Further details regarding the circuit in figure 5
Because an ohmic contact between A and B causes triggering of the chime, no bell may be
connected in parallel to the chime. However, paralleling several chimes does not cause any
problems.
In older batteries, the higher internal resistance of the battery may cause voltage drops
becoming apparent as distortions. C4 serves as a buffer element expanding the service life of
the battery.
The trigger line connected to pin A acts - in open state - as antenna for noise pulses which
could trigger the chime unintentionally. Capacitor Cs will largely suppress such interference.
If there is the risk of incorrect polarity connection when changing the battery, the battery
line should be protected by a diode.
For the selection of components, the following recommendations are given:

Capacitors:
C 1:
C2 :
C3 :
C4 :
C s, C s:

4.7 nF/~ 10 V, ± 5%; e.g. MKT
100 nF/~ 10 V, ± 20%; e.g. MKT
100 IlF/~6.3 V, ± 1001-10%; e.g. aluminum electrolytic
100 IlF/~ 10 V, + ,100/-10%; e.g. aluminum electrolytic
330 nF/~ 50 V, + 1001-20%; e.g. ceramic

Resistors:

R3:

R1 :

4·8

82 k0/0.1 W, ± 10%, carbon film resistor
When a fixed resistor is used, 0.1 W ± 5% metal film resistor.

SIEMENS
SAE 0700
Audible Signal Device
The audible signal device SAE 0700 generates two tone frequencies in a ratio of approx. 1.4 : 1
that follow one another in a periodic sequence. The tone frequency can be varied throughout
a range between 100 Hz and 15 kHz by an external resistor. The switching frequency of
0.5 to 50 Hz is set by an external capacitor. The SAE 0700 can be used to drive either a
loudspeaker or a piezo-ceramic transducer. The SAE 0700 can be supplied with voltage in
two ways:
1. rms ac voltage from 10 V
2. dc voltage from 9 to 25 V
The SAE 0700 issues the tone sequence for as long as the supply voltage is applied. After
application of the supply voltage, the tone sequence commences with the higher of the two
tones.

Features

•
•
•
•

Direct ac-voltage feeding possible through integrated bridge rectifier
Integrated overvoltage protection through Z diode, approx. 28 V
Bridge rectifier provides for protection against incorrect polarity in dc operation
Few external components (one resistor and one capacitor minimum)

Block diagram (with external components for dc supply)

7 Voe

Bridge rechfler

@~

v..e,8 t-Vs

1

VA(

2

Ir--

Threshold
CircuIt

-

SWitching
frequency
generator

r-

Tone
frequency
generator

SAE 0700

-

Output
stage

f-

~
V.

~ P,ezo

=r= resonator

2 GND

3

4)RT

== Cs

Figure 1

4-9

SAE0700

Functional description

The audible signal device SAE 0700 (see blcok diagram, fig. 1) includes the following functional
blocks:
•
•
•
•
•

bridge (for voltage supply) and overvoltage protection
threshold circuit
switching-frequency generator
tone-frequency generator
output stage

Bridge rectifier: The bridge rectifier enables direct feeding with ac voltage or dc voltage

(independent of polarity). DC-voltage supply without integrated bridge is also possible via
pins Voc and GND.
.
If. the voltage is supplied via the bridge, the input voltage VS1 should be dimensioned such
that at least 9 V appear at the pin Voc (also with output loading). It should also be noted that
in the case of voltage supply via the bridge, the maximum output current has to be limited
to 50 mAo
Response of the SAE 0700 as a result of spikes on the AC line is prevented by a built-in
initial resistance R 1N1• In a voltageless condition RINI provides for discharging the storage
capacitor of Voc to ground.
The Z diode following the bridge serves as overvoltage protection. The bridge circuitry shown
in figure 2 efficiently protects the SAE 0700 against damage as a result of the following
voltage values:
• overvoltages in acc. with VDE 0433 (2 kV - 101700 Ils)
• ac voltages up to 220 V/50 Hz for a duration of 30 s

Vab

j
bo----t--------'
...100nF
7.5Hz

Figure 2

4-10

...16kQ/1700Hz

SAE0700

Threshold circuit: With a threshold voltage of typically 8.6 V this ensures that the SAE 0700
is not activated by noise pulses.
Switching-frequency generator: This switches periodically between the two frequencies
produced by the tone-frequency generator. Wiring with a capacitor Cs produces a switching
frequency fs according to the following formula:

f [Hz] =
s

750

C [nF]

± 25%

(valid from 0.5 to 50 Hz)

Tone-frequency generator: This generates a squarewave voltage with the two tone frequencies fT1 and fT2 • The basic frequency fT1 and the second tone frequency fT2 are calculated according to the following formulae:

fn [Hz] =

fT2

2.72 X 104
R [kQ]

± 25%

(valid from 0.1 to 15 kHz)

[Hz] = fn x (0.725 ± 5%)

The tone-frequency generator is temperature-compensated for better stability.
Output stage: This boosts the generated tone voltage for direct driving of a piezo-ceramic
transducer or a loudspeaker, possibly across a dropping resistor.

Pin configuration

Pin No.

Symbol

Function

1
2
3

VAC2
GND
Cs
RT'
Q
N.C.
Voc
VAC1

AC-voltage input
Ground
Connection for capacitor Cs
Connection for resistor RT
Output
Not connected
DC~voltage input
AC-voltage input

4
5

6
7

8

4-11

SAEO,700

Maximum ratings
Voltage at pin 7
Voltage at pin 3'
Voltage at pin 4
Output voltage at pin 5
AC voltage at pin 8 and 1
(peak value)
Input current of bridge
AC input current of bridge
Output current
(50 Ils, duty cycle 1 : 10)
Output current
Total power dissipation (Tamb = 25°C)
Junction temperature
Storage temperature
Thermal resistance (system-air)

Voc
V32
V42
Va

Lower
limit

Upper limit

-0.5
-0.5
-0.5
-0.5

26
5.5
7
Voc+0.5

V
V
V
V

-50

28
50
25

V
rnA
rnA

100
50
0.8
150
125

rnA
rnA

W

120

K/W

VAC
ISl
ISl

rms
-100

10
lorms
PIal

1j
Tstg

-40

R lhSA

°C
°C

Operating range
Supply voltage
Tone frequency
Ambient temperature

Voc

tn
Tamb

Characteristics
Tamb =

Test conditions

-25 °C to 85 °C

Current consumption

loc

Switching threshold
Initial resistance

RINI

Output-voltage swing
Tone frequency
Switching frequency
Tone frequency ratio
Temperature
coefficient of tone
frequencies

4-12

tTl
fs
fTllfT2

TCf

~.1

see characteristic,
figure 3
lo=± 10mA
Voc -15 V, V32 -O V,
RT = 16 kQ
Voc =15 V, Cs =100 nF

15
25

-25

1

1 85

~HZ
°C

typ

Upper
limit A

1.5

1.8

rnA

8
3.5

8.6
4.7

9
6

V

Voc -3.7
1.275

Voc -3
1.700

2.125

~Hz

5.6
1.31

7.5
1.38

9.4
1.45

Hz

Lower
limitS

Voc -9 V to 25 V,
wlo load

VOCON/OFf

Va

1

8 x 10-4

kQ

V

K-l

SAE0700

Characteristic curves

mA

Current consumption versus
supply voltage Voe
without output load

Tone frequencies 'T 1 and
versus resistance RT
kHz
10

3

5

If

I'

'rz
2

'T 2

2

--- ~A:

~

'Tl

\

1

'11: '12 =1.3S

__- .1...1'I

~~

.~J

-

~

0.5

- . §j

1\

-oS

I

0.2

o if
o

0,1

30 V

10

1

2

5

10

20

50

100 HI

-RT

Hi

Switching frequency's versus
capacitance Cs

100

so

.400 ms), the angle of current flow will be varied
continuously. It runs across its control loop in approximately 7.6s (e.g, bright-dark-bright) and continues this sequence until the sensor is released,

The integrated circuit replaces mechanical wall
switches in conventional light circuit installations. All
functions can be selected from several switching
points (extensions).
The brightness is set by phase control. Its digital logic is synchronized with the line frequency (see block
diagram, Figure 1).
It is possible to supply the Ie via a two-wire connection, as the angle of current flow is limited to a maximum of 152°e of the half wave.

Operation (Refer to Figure 2)
The integrated circuit can distinguish the instruction
"ON/OFF" and "Dimming" by the duration for which
control input is operated, i.e. the sensor is touched.

Turning On/Off
Short touching (50 to 400 ms) of the sensor area
turns the lamp on or off, depending on its preceding
state. The switching process is activated as soon as
the sensor is released.
'

Easy operation, even in the lower brightness range,
is enabled by the following procedure: the phase
control angle is controlled such that the lamp brightness varies physiologically-linear 'I'oIith the operating
time and rests for a short period when the minimum
brightness is reached,

Control Behavior
The three functions A, B, e, differ in their control
behavior. The required function is set with the programming input.
Type A With turn-on, the maximum brightness level
is set.; with dimming, control starts from the
minimum brightness level. With repeated
dimming, control is carried out in the same
direction (e.g, "brighter"),
Type B With turn-off, the selected brightness is
stored and set again when the switch is
turned on. Dimming starts at this stored value and the control direction is reversed with
repeated dimming.
Type e With turn-on, the maximum brightness is
set; with dimming, control is started from
the minimum brightness. the control direction is reversed with repeated dimming.

4-15

SLB 0586

Programming of the Various Functions
Type A:
Type B:
Type C:

Vss (L)

open (tristate)
Voo (H)

V12 = Level at pin 2

Control Behavior of Function Types AlBIC: (Schematic)

s~ ;J
n III'

n

1

c4: L-__-+____
3D"

9

I

11

I

I

, ,

9

I:
:
..--_-------- ~ ------- __ at -r! -_ .. -----r-----1 -------- .. -1-- -_ ..

~_- -~-

:

I

I

I

I

I

__ __-,
I

~

VLIII'"

I
I

I
I

I
I

,

, I
I
I

..-..--_-.:.--t------.. ---t-t--.. -.. --.:------..

~_--

~:

!

~----+_--~----------------------------~------_+;_----~----+_------~!~--L-~=O

n III'

n

r

I - _ ..... - - ........

'I

i--.. . .
I

VLInIft

L----4----~----+---~----------------------------_i------_t~----~----+_------1!~--L-~.O

,10'

~:

,,

-..------ ....... :I..... --------~-~-. -----~------:--: I
I ; . -... ----.:----:
•

I

I

I

I

I

t

!

I

I

VL ......

3D'

0 L---~--~~--4_---+----r---_r--_,----,_--~----r_--,_--_.~--~~_r--_,r_~-~.D
12
13
14
15
10
11
6
7
8
9
3
4

a = Angle of current flow
VL = Lamp voltage

S = Control signal: S Sensor touched
(S:0.4s, :?: O.4s)

S Sensor not touched
Types A and C permit "soft" turn-on, i.e. brightness is increased from 0 to maximum within 380 ms.
Figure 2

4-16

0109-2

SLB 0586

Absolute Maximum Ratings·
Maximum ratings are absolute ratings; exceeding
only one of these values may cause irreversible
damage to the integrated circuit (Voo = OV).
(without external protective circuitry)

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Supply Voltage (Vss) ............ -7.5V to + 0.3V
Input Voltage (Vi) ............ Vss -0.3V to +O.3V
Junction Temperature (Tj) .................. 125°C
Storage Temperature (Tslg) ..... - 55°C to + 125°C
Total Power Dissipation
(TA = 25°C) .......................... 10 mW
Thermal Resistance
(System-Air) (RlhSA) .................. 135 K/W

Operating Range
In the operating range the functions given in the circuit description will be fulfilled. Deviations from the
characteristics are possible. All voltages are referred
to Voo = OV.
Supply Voltage (Vss) ............ -4.SV to -5.SV
AmbientTemperature (TA) .......... O°C to + SO°C

Integrated circuits exhibit optimum reliability and
service life when the junction temperature does not
exceed 125°C during operation. In principle, an IC
can tolerate a maximum junction temperature of
150°C. It has to be considered, however, that operation at maximum ratings for prolonged periods may
adversely effect component·reliability.

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
will apply at TA = 25°C, Vss = 5V (Voo = OV).
Parameter

Symbol

Limits

Conditions
Min

=
=

Supply Current

Iss

f sync

Supply Current with
Missing Sync Signal

Iss

fsync

Input Reverse Current

II

Input Capacitance

CI

UI = OV
f = 1 MHz

VIH
VIL
IIH

with Series
%Vss+1.1
Resistor 10 Mn at
220V Line

tTHL

Synchronized
with 50/60 Hz
Clock at Sync
Input

50/60 Hz

Units

Typ

Max

0.45/0.46

0.6

mA

0.45

mA

0
0.5

nA

5

pF

Sensor Input (Pin 5)
H Input Voltage
L Input Voltage
Peak Input Current
HL Transition Time
(Trigger Transition)
LH Transition Time
Frequency with Active Signal

tTLH
f

33

%Vss-1.1
37

V
V
p.A

Line Sine
Wave
Hz

50/60

Extensions (Pin 6)
H Input Voltage
L Input Voltage
Input Current

VIH
VIL
IIH

%Vss+1.1
%Vss-1.1
Vss - 0.3V
(or Voo + 0.3V)

0.5

V
V
p.A

4-17

SLB 0586

Characteristics (Continued)
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
will apply at T A = 25°C, Vss = 5V (Voo = OV).
Parameter

Symbol

Limits

Conditions
Min

Units

Typ

Max

207

%Vss -1.1
240

Sync Input (Pin 4)
H Input Voltage
L Input Voltage
Input Current

VrH
VrL
IrH

HL Transition Time
(Trigger Transition)
LH Transition Time
Frequency

tTHL

with Series Resis- %Vss
tor 1.5 Mn from
220V Line

+

1.1

V
V
/LA

Supply Sine
Wave

tTLH
f

50/60

Hz

7

pF

Programming Input (Pin 2)
Input Capacitance to Vss

Cr

Load Capacitance through
Board with TRISTATE

C

7

pF

330
120

kn

Programming of Function Types (See Figure 2)
Integrator (Pin 3)
Application Circuit

Cs
Rl0

Ref: Figure 3

L Output Current

10

Vss = -5V
VOL =' -3V

L Pulse Width

taL

50 Hz Supply
60 Hz Supply

L Output Voltage

VL

68
82

100
100

!"IF

Output (Pin 8)

HL Transition Time
LH Transition Time

25

rnA
39.0
32.6

/Ls
/Ls
V

Voo - 0.6

tHLO

20

/Ls

tLHO

20

/Ls

Description of Application Circuit

• Sensitivity setting of the sensor (R7)

(See Figure 3)

• Current limitation in case of incorrect polarization
of the extension (Rs, Rs). Both resistors can be
omitted if no extension is connected. In this case
pin 6 must be connected to Vss (pin 7).

The suggested circuit design for the SLB 0586 has
the following functions:
• Current supply for the circuit (Rl' C2, 01, 02, Ca).
• Filtered signal for synchronizing the internal time
base (PLL circuit) with the line frequency (R2, C4)'
For special applications C4 may be increased to
15 nF, but only at the expense of the lamp brightness! Brightness wil be reduced (shift of the control range to the left)
• Integrator for internal PLL circuit (Cs, Rl0)
• User protection (Re, Re)

4-18

• 03: Reduction of positive voltages, which may
arise during the triggered state at the gate of some
triacs, to values below Vss + 0.3V (compare
characteristics). If suitable triacs are used, diode
03 can be omitted. (This feature of the triac depends on the anode current and on the internal
resistance between G and A 1; it can be measured
and specified by the manufacturer.)

SLB 0586

Application Circuit
Ph...

~~:c

I
I
I
I
I
I
I
I
I

-------------------~I

R7
1 ...
4.7MO

I
I
I
I
I

Eleclron.
Exlen·
sion

I
I

~--~~~~~~I~~----~
Exlensions

10.1pF

I 25DV.c
I

I
I
I
I
I
I

OV

D1

C,

100pF
6.JV

AI 110V /60 K.llne:

Dl

·5.JV

a: 100 nFI 160

lis

V.,

-""
Sensor
Extension

Mp .
0109-3

Figure 3
• Dr: The choke and C1 are integrated for EMI suppression. The elements for EMI suppression have
to be dimensioned in accordance with
VDE 0875/Part 2 (general)
VDE 0550/Part 6 (chokes)
or in accordance with other relevant regulations,
depending on the application intended.

• Response time approx. 2 ms
• Return delay time approx. 30 ms
• Protection against incorrect polarization (R1, 01,

Si)
Note:

Reference values: 1.4 mH ... 2 mH, Q = 11 ... 24

The extension input must be connected to Vss, if
this input is not required.

Extensions

Operation of the Control Inputs

All switching and control functions can also be performed from extensions which are connected to the
extension input. The main sensor input and the extension inputs have equal priority. Electronic sensor
switches or mechanical pushbutton switches can be
connected to the extensions. During operation "H"
potential must be applied to the extension input for
both half cycles.

Input potential during both half ways of the line
phase:

An electronic circuit suitable for this purpose is
shown in the application example (Figure 4). The circuit operates as return delay and takes over the triggering of the switching transistors during the negative half cycle.

Function
Operated

Not
Operated

Sensor
Input

Extension
Input

L

H

Negative

0

H

Positive

H

Negative

0

L or ~
OiL

Line
Half Wave
Positive

I

4-19

SLB 0586

Application Circuit-Electronic Extension

0

Pha,.

~----

-------------------~

10nF

BZX55

C6V8

1N

BZX85

C6V8

4007

220W
IW

f'N\

~---- ----~---------~----~
SensOr

\!!I Central Unit with SLB058&

0109-4

Figure 4

Wireless Remote Control.
llle connection of a wireless remote control to the
extension is very easy. All functions of the 5L8 0586
can be performed with the aid of a single transmission channel.

The control characteristic of the synchronous oscillator (PL:L circuit) is designed such that interference
due to ripple control Signals may cause slight variations in brightness. However, they will not lead to
malfunction of the dimmer.

General Information
Interference Immunity
A digitally determined immunity period of approximately 50 ms ensures a high interference immunity
against electrical variations on the control inputs and
additionally allows almost delay-free operation.
Due to the special logic of the extension input, even
large ground capacitances of the control line will not
lead to interference.
In case of power failure the set switching state with
the recommended external circuitry remains stored.
After prolonged power failure the circuit turns into
off-state.

4-20

All time specifications refer to a line frequency of
50 Hz. In case of iii line frequency of 60 Hz, the times
are reduced accordingly.

Ordering Information
Type

Ordering Code

5L80586

Q671 00-H8605

SIEMENS

SLE 4501
Nonvolatile Safety Counter
Preliminary Data
Type

Ordering Code

Package

SLE 4501
SLE 4501 K

Q67100-H8377
in preparation

P-DIP 8
MIKROPACK

Features

•
•
•
•
•
•
•
•

Internal generation of programming voltage
Counting range 22 bits binary, nonvolatile storage
Count output in serial binary code
Counting operation is executed under on-chip control and cannot be influenced
externally
Disconnection of the operating voltage, even during a counting operation, has no effect
on the stored count
The count is protected against manipulation by internal safety logic after blowing a
fusible link
Additional 64x8 bit EEPROM area with serial access (byte organization)
Extended temperature range: -40 ... +110°C

Pin Configuration

Pin Description

Vss 1

8 Vee

4>2

7 TO

03

6T1

L4

5 ([

Pin

Symbol

Funktion

1
2
3
4

Vss
fP

D
L

5
6
7

CI
T1
TO

8

Vee

Ground
Clock input
Data inpuVoutput
Chip select for data input
(active high) and indication
of storage operation
(active low)
Counter input (active high)
Fusible link
Control input test operation
and fusible link
Operating voltage

Edition 3.87
4-21

SLE 4501

Circuit Description
The nonvolatile counter (NC) has a counting range of 22 binary bits and retains its count
even after the operating voltage has been disconnected. The safety logic of the device
prevents any alteration other than the intended incrementing of the cbunt from being
caused by supply voltage failures; ego during a counting operation. Before the fusible link
Is blown, a desired count can be preset in a test operation. After the fusible link is blown,
the count can only be altered by a count request. Thus it is only possible to increment
the counter.
The count is binary coded- and can be sampled serially on a thr.ee-wire bus (section 4).
A counting operation has priority in any case and will terminate any 'readout operation
that has been started.
The 64x8 bit EEPROM area (NVM) is addressed serially by a 1-byte OP code (see
programming and readout operation). Addresses 16 through 63 can no longer be reprogrammed after the fusible link is blown. Before the fusible link is blown, test input TO should
be set low for normal operation.
An on-chip reset circuit ensures operational reliability. Its function is described on page 5.
Counting Operation (fig. 1 c)
The integrated circuit consists of a 22-step, asynchronous 'counter and a nonvolatile,
electrically reprogrammable memory (EEPROM) for nonvolatile storage of the counter content.
For reasons of operational reliability, the counting operation is executed entirely under
on-chip control. The device includes the necessary sequence control for which it ge.nerates
an internal clock of approx. 50 kHz. A pulse at input CI causes the asynchronous counter
to be incremented by 1.
The new count is stored as nonvolatile information. This storage operation is indicated
by low on input/output L. During storage no other count events are registered resulting
in a dead time of 10 ms max. in the rated-voltage range. The operating voltage must
be maintained in the rated-voltage range for at least anolher 10 ms after the start of a
storage operation, or else the last count event might not be permanently stored (response
time). Counts that have already been stored are not at all affected if the operating voltage
is s.witched off during a storage operation and thus cannot be manipulated. If the operating
. voltage is reduced during the counting operation, the dead time and the response time will
become longer, but storage reliability is not affected due to the integrated programmingduration control. The device is inactive outside the operating-voltage- window defined by the
reset circuit.
The nonvolatile counter includes overflow protection. If all counter bits are 1, any further
count pulses are ignored.

4·22

SLE 4501

Count Readout (fig. 1 d)
For sampling the count, input/output L is first set low and then the two instruction bits BO,
B1 are clocked in. After this, pin L goes high again. With the trailing edge of each further
clock pulse cp there appears on pin D, starting with the most significant bit, the next
least significant bit. The entire count is read out with 22 clock pulses. A low pulse on
input/output L switches pin D back to high impedance.
A storage operation (nonvolatile counter or 64x8 bit EEPROM) indicated by a low on pin L
always has priority. During this time the device cannot be addressed. A count request
will terminate any readout operation that has already been started.
Programming of NVM (fig. 1 a)
The input/output L must be set low. Then the 8-bit data word (DO as the 1st bit) is first
clocked in, followed by the 8-bit instruction word (consisting of six address bits AO through A5
and two instruction bits BO, B1). After pin L has gone high again, the programming
operation, indicated by low on the input/output L, begins following a further clock pulse CP.
When the internally controlled storage operation has been completed, L returns to high.
In the rated-voltage range, the maximum programming time is 10 ms.
Readout of NVM (fig. 1 b)
The input/output L must be set low. Then the 8-bit instruction word (consisting of 6 address
bits AO through A5 and two instruction bits BO, B1) is clocked in. After pin L has gone
high again, one bit (beginning with DO) of the respective data word appears on pin D
with the trailing edge of each further clock pulse CP. The entire data word is read out
with eight clock pulses. A low pulse on input/output L switches pin D back to high
impedance.
Fusible Link (fig. 4)
Blowing the fusible link has the following irreversible effects:
a) The count can now only be altered by count pulses on count input CI.
b) It is no longer possible to program the entire NVM in one operation.
c) Addresses 16 through 63 of the NVM can no longer be reprogrammed.
In order to blow the fusible link, the following conditions have to be produced on the inputs
(cf. fig. 4):
a) Test input TO on 17 V
b) Test input T1 on 17 V with max. 1 IJ.s edge rise time.
The fusible link melts within 100 ms. On test input TO there is a temporary peak current
of up to 100 mA which can be taken from a storage capacitor for instance.
For the blowing process, test input TO must be connected according to fig. 4b, otherwise
the device might be destroyed.

4-23

SLE 4501

Test Operation (fig. 2a, 2 b, 2c)

Provided the fusible link is not blown, the following modes of test operation are possible
(T1 must always be kept low and TO high):
a) Presetting of count (fig.2a)
The input/output L is set low and then the 22 bits constituting the required count are
clocked in starting with the most significant bit. Here it should be noted that the counter
bits CBO through CB3 can only be programmed uniformly as a or 1. After the two bits
of the instruction code have been clocked in, pin L is set high again.
Differing values for CBO through CB3 will lead to undefined counts.
A high on count input CI starts the programming operation. which is indicated by a low
on pin L. In order to activate the safety logic for the present count, TO must then be set
low and the supply voltage briefly switched off.
b) Erasure of entire NVM (fig.2b)
Writing into entire NVM (fig. 2c)
Input/output L is set low and the two bits BO, B1 of the instruction code are clocked in.
After switching pin L to high, a high on input rp will start the programming operation
which is indicated by a low on input/output L. Input rp must be kept high for at least
50 ms because the internal timing control for the NVM is off and the programming duration
(t prog ) is defined for the length of the rp pulse.

4-24

SLE 4501

Instruction Codes

a) TO low or after blowing the fusible link:
Function

80

81

Program NVM
Read out NVM
Read out counter

1
1

a

a

1
1

Function

80

81

Preset counter

a

a

80

81

b) TO high (test operation):
Started by pulse at CI

Started by clock pulse ~
Function
Erase entire NVM
Write into entire NVM

a

Reset Function

For reasons of operational reliability the device contains an internal reset circuit that
limits the active range of a voltage window. The lower limit is a maximum of 4.5 V and
the upper limit a minimum of 5.5V.
If the supply voltage is outside this window, even if only because of spikes, the device
will reset. As soon as the supply voltage is again within the voltage window, an internal
reset routine is run which is indicated by a low on inpuVoutput L and means a dead
time of 100 ms max. in the rated-voltage range.

4-25

SLE 4501

Maximum Ratings
min.
Supply voltage
Input voltage
Power dissipation
Storage temperature
Thermal resistance
system-air

Vcc

iii

-0.3
-0.3

max.

Unit

6
6

V
V
mW

40

Po
TSIQ

typo

-55

RthSA

125

DC

K/W

100

Operating Range
Supply voltage
Ambient temperature

4.75
-40

5.25
110

Maximum Ratings

Maximum ratings are absolute ratings. Exceeding even one of them may result in the destruction
of the integrated circuit.
Operating Range

Within the operating range the functions mentioned in the circuit description will be fulfilled.
Deviations from the characteristics are possible.

4-26

SLE 4501

Characteristics
typo

max.

Unit

7

5.25
10

V
mA

0.8
Vec
10
100

V
V
Il A
Il A

IL
IH

10

mA
Il A

t dead

100
10
1000

min.
Supply voltage
Supply current

Vee
Icc

Inputs
(CP, L, CI, D, TO, T1)
(CP, L, CI, D, T1)
(TO)

VI
VH

Outputs (D, L)
(open drain, Vi

4.75
0.5
2.2

IH
IH

1
=

5 V)

Counting dead time
Counting response time
Clock cP

t resp

5
5
1

tH
tL
tf

Interval start pulse/
trailing edge L
Count input CI

5
5

tST
tCI

Programming time NVM
(p~r byte)

t prog

Programming time NVM
(total memory)

tprog

Blowing of fusible link:
TO

VH

T1

IH
VH
tr
ts

Il s
Il s

50

10

ms

100

ms

17
100

17
10
1

IH

,

100

ms
ms
Il s
Il s
Il s

V
mA
V
Il A
Il s
ms

DC Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics will apply at TA = 25°C and mean supply voltage.

4-27

SLE 4501

Block Diagram

Programming
Voltage
Generation

64.8 Bit
EEPROM

22- Bit Shift Register

Sequence
Control

2 - Bit Shift
Register
([nstruction Code)

22- Bit Binary Counter

Power-On
Detection

22 - Bit Register 1
Nonvolatile
(Redu ndant )

4-28

22-Blt Register 2
Nonvolatile
(Redundant)

Fusible
Link

SLE 4501

a) Programming of NVM

D~~~~~EE~~~~~~~~~~~
L

~~

______________________________________

~

Figure 1 a

b) Readout of NVM

4> ____....
D

L

u

Figure 1b

4·29

SLE 4501

c) Counting Operation

----:tCJr-

(I __________~H~
L

________________________________________
Forced. !~~~rnally

Figure 1c

d) Reading Out Count

f/> ______---I
0 _ _ _ _...;.;....1
L

Figure 1d

4-30

cao

m

High-Imp.

·····----------u

m

SLE 4501

a) Presetting Count on NC

TO
(I

...l.

L

----------------~~~----I
I

81

L

~~

_________________

~Hi9h-tmp. $
r1 Forced

_ _ _ _ _ _ _ _ _ _ _ _.....,Hf-+;:;;[n:;.;;;ter.~~!l.Y__.r
_

I

It-tST

Figure2a

b) Erasure of Entire NVM

TO

..J

4>-----1

.--__--.., L

o
L

Figure2b

c) Writing i~to Entire NVM

TO

..J

4> ___---'

L

o
L

Figure2c

4-31

SLE 4501

Application Circuit

P13

P 12

P11

I

P 10
XTAL 2

DODI
ClK

SAB 8051
SAB 8048

tf;

t

tf;

0

ENA

CO

L

CI

SLE 4501

SLE 4502
r---- CI
Vss

1
From Speedometer Pulse Cienerator

Figure 3

4-32

Voo

Vss

1

1

+sv

Voo

1

+sv

SLE 4501

Blowing Fusible Link
a)

""I----fs

T1

----'I

In"

(min 100 ms l-----II.-li

I~'~-------

TO
b)

\'------

.--

~-------1-------BYS 21-45
..L

l

\~
From Tester

3xO, 82 1lF

~ Stacked Blocking C

The Circuit is Connected Directly to Pin 7

Figure 4

4·33

SIEMENS

SLE 4502

Prescaler for Safety Counter
Preliminary Data
Type

Ordering Code

Package

SlE 4502

067100-H8378

P-DIP 8

The SlE 4502 integrated circuit transforms the speed pulses for the SlE 4501. nonvolatile
safety counter.
Features

• CMOS technology
• Inputs/outputs protected against latch-up
• NMOS-compatible inputs and outputs
• Standby current (1 J..LA)
• Schmitt trigger input for counter
• 4-bit miles counter with a programmable prescaler (between 1 and 6.5000)
• i6-bit register for miles-counter function with external time base
• 16-bit register for trip counter resettable
• Serial three-wire bus
• Power-fail flag
• Extended temperature range: -40 ... +85 °C

Pin Configuration

Voo'

ENA Z

Pin Description

8 [I
7 [lK

Pin

Symbol

Function

1
2
3

Voo

ENA

Supply voltage +5 V
Enable input
Clock input for
data inpuVoutput
Data output data input
Supply voltage OV
Counter output
Clock input for IC
timing
Count pulse input

!II

cf>3

6[0

4

DODI

DO DI 4

5 Vss

5
6
7

CO
ClK

8

CI

. Edition 3.87
4·34

Vss

SLE 4502

Circuit Description
1. Counter Function
The arriving count pulses are sent to the count output via a programmable 16-bit counter
and a fixed 4-bit counter. At a 12-MHz clock frequency, the output pulse width is 10 Ils.
The contents of the 4-bit counter is readable over the serial interface.
2. Trip Counter
The output pulses of the programmable divider are counted in an additional 16-bit register.
This counter is readable and resettable.
3. Speedometer
The clock frequency reaches a 16-bit interval counter, which is programmable in a
16-bit register, over a 5-bit prescaler. The speed pulses are counted during an interval
and stored in a latch at the end of the interval. This latch may be read at any time.
4. Power-Fail Flag
Upon an increase in the supply voltage from OV to 5V a reset is generated. The power-fail
flag indicates this condition. The power-fail flag is reset when it is read out.
5. Instruction Code
Function

83

82

81

80

Program divider factor
of miles counter

1

1

0

0

Program divider factor
of speedometer

1

0

1

0

Reset trip counter

1

0

0

1

Read out miles counter

0

1

0

0

Read out trip counter

0

0

0

1

Read out speedometer

0

0

1

0

Read out power-fail flag

0

1

1

1

4-35

SLE 4502

Maximum Ratings
min.
Supply voltage
Input voltage'
Power dissipation per output
Total power dissipation
Storage temperature

Voo

\liM 1
Po
Ptot

typo

-0.3
-0.3

Tstg

-50

Voo
Ioos

4.5

max.

6
Voo+0.3
50
150
125

Unit

V
V
'mW
mW
°C

Operating Range
Supply voltage
DC supply currrent
Supply current (meas. circuit)
Operating frequency
Ambient temperature

100
fCLK

TA

1
-40

5

5.5
1
1
15,
+85

V
IlA
rnA
MHz "
°C

Maximum Ratings
Maximum ratings are absolute ratings. Exceeding even one of them may result in the destruction
of the integrated circuit.
Operating Range
Within the operating range the function mentioned in the circuit description will be fulfilled. Deviations
from the characteristics are possible.
4-36

SLE 4502

Characteristics
TA = 25°C
min.

max.

Unit

Voo

V
V
pF
IJ.A

AU input signals except CI
H input voltage
l input voltage
Input capacitance
l input current

VIH
ViL
CI
/IL

2.2
0

0.8
10
1

Input signal CI
H input voltage
l input voltage
Input capacitance
l input current
Hysteresis

ViH
ViL
CI
/IH
VH

Voo -1

Voo

0

1
10
1
2

V
V
pF
IJ.A
V

Output signals
H output voltage

VOH

V

Voo -0.4

/0=0.5 rnA
l output voltage

VOL

0.4

V

15
500
500

MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

/0 = 1.6 rnA

AC Characteristics
TA = 25°C
Clock frequency
Pulse duration ClK
Pulse spacing ClK
Pulse duration«p
Pulse spacing«p
Enable low to«P
«p low to enable
Data setup
Data hold
Output delay
Enable low to data high-impedance
Output pulse width CI

'CLK
tCLKH
tCLKL
tH
tL
tE
tE
ts
tH
to
tHZ
tCI

1
50
50
100
100
6lfCLK
50
50
50
50
6lfCLK
128/fCLK

DC Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics will apply at TA - 25 DC and mean supply voltage.

4-37

SLE 4502

Block Diagram

Programmable 16-Bit
Divider

~---CO

16-Bit Register for
Divider Ratio

Programmable 16 - Bit
Divider
16-Blt Counter
for
Speedometer Pulses

16- Bit Register for
DIvider Ratio

16-Bit Shift Register

4-38

SLE 4502

Measurement Circuit

+5.5V

([ 8
f= 15MHz

(LK 7
3

q,

(06

4 DOD!

Vss

5

Application Circuit

P13

P 12

I

P 11

P 10

OODI

XTAL2

q,

(LK

SAB 8051
SAB 8048

t

ENA

0
(0

SLE 4502

r---

q,

L

(1

SLE 4501

(I

vss

1

voo

vss

1

1

+5V

Voo

!

+5V

From Speedometer Pulse Cienerotor

4-39

SLE 4502

Diagrams

.

Wnte

ENA

f/>
0001

~$ij
t--t4>H

--~l,'
OODI

tsal 831s21811so fWI'IA
-I"
t4>L
-I
~~-----~~---------

-----'~~--+i-~XIolo---'___
I

I

I

t--ts -----r--tH...-.l

Read
ENA

f/>

,..,_ _ _ _~
1

1

--ltE4>--

--ftE--tE4>---.j

tsBl
I

t--tHZOODI

4-40

i ~

it I
--lor----

~Hlgh Z~
I

SIEMENS

SLE 4520
3 Phase Pulse Width Modulator
• Generation of Three Pairs of Pulse Width
Modulated Rectangular Pulses (Phase
Angle between One Phase and the Next is,
for Example, 120°C) to Drive Six Individual
Transistors of an Inverter Power Block

• Direction of Rotation is Software-Reversed
by Changing between Two Phases
• Sine-Wave Frequency Range about 0 Hz to
>3,000 Hz
• Switching Frequency Range
>23 kHz

• Programmable Deadtime to Safely Drive
Both Power Switches of Half-Bridge from

oto 15 x

6

< 1 kHz to

• a-Bit Resolution of the Desired Sine-Wave
Function with a Switching Frequency of

4

-f- - or 15 x - - in 15
crystal
fcrystal
.
Steps. The Negative Edge is always
Delayed because the Output Signal is
Active Low

fcrystal or 7 Bit Resolution with fcrystal

6 X 28

6 X 27

(fcrystal = 12 MHz and Resolution = 7 Bits
Result in a 15.6 kHz Switching Frequency)

• Programmable Predivider in the Pulse
Width Modulator to Obtain Low Switching
Frequencies (for Output Stages with
Thyristors, GTOs, and Bipolar Transistors)
and at the Same Time to Operate the
Microcontroller at Higher Crystal
Frequencies

• Smallest Increment of the Pulse Width is
333 ns with fcrystal = 12 MHz and Divider
Ratio 1:4
• Changing the Switching Frequency Cycle in
1 JLs Steps Allows the Transition from One
Sine-Wave Frequency Stage to the Next
Quasi Continuously (Virtually Analog)

• .Direct Drive of an Optocoupler Interface to
Isolate Control and Load Circuits (Isink =
20 mA Maximum)

• Evaluating the Bit Pattern at One Port of
the Microcontroller Enables Many (256)
Different Speed Control Programs to be
Selected

• All Six Outputs of the SLE 4520 are Set to
High Level either Dynamically by an Inhibit
Signal (INHIBIT) or Statically by an R-S
Flipflop (SET STATUS) Thus Blocking of all
Six Individual Transistors of the Power
Circuit is Possible

• Low Current Consumption of the Pulse
Width Modulator because of ACMOS
Technology

• DC Braking by Selecting Different Fixed
Duty Cycles in the Three Output Pairs
• Digital sinus-synthesis for controlling the speed of rotation and the torque of three-phase motors.
• 2-chip solution (e.g. SAB 8051 with SLE 4520) for easy configuration of a powerful frequency converter.
• Motor frequencies from 0 Hz to 3.000 Hz and above with a switching frequency selectable up to 23.4 kHz.
• Adaption to different output stages through a programmable deadtime.
• Functional and performance features determined by dedicated software.
The new pulse width modulator converts an 8-bit data word into a rectangular signal of corresponding width.

@Siemens Components, Inc.

4-41

April 1988

SLE 4520

Pin Configuration

Pin Definitions

(Top View)
21
2

27

3

2'
25

•
,
5

14
23

7

22

,

21

10
11

"

12

17

13

"

1

,.

Symbol

Pin

20

1
2
3
4
5
6
7
8
9
10
11
12
13

Voo
XTAL1
XTAL2
P7
P6
P5
P4
P3
P2
P1
PO
PH3/2
PH3/1

14
15
16

Vss

17
18

PH1/2
PH1/1

19

INHIBIT

20
21
22
23
24

STATUS
CLEAR STATUS
SET STATUS
RES
WR

25

ALE

26
27

CS
SYNC

28

CLKOUT

11

PH2/2
PH2/1

15

0151-2

Function

+ 5V Connection
Crystal Connection
Crystal Connection

Data Bus Connections
(Inputs)

Output Phase 3 Inverted
Output Phase 3 Normal
(Active Low)
Output Phase 2 Inverted
Ground Connecting
Output Phase 2 Normal
(Active Low)
Output Phase 1 Inverted
Output Phase 1 Normal
(Active Low)
Inhibit (Active High) Sets
All Phase Outputs to
High
Output of Status Flipflop
Resets Status Flipflop
Sets Status Flipflop
Chip Reset
Input for WR Pulse from
Microcontroller
Input for ~LE Clock from
Microcontroller
Chip Select
Input for Trigger Pulse
from Microcontroller
Output Crystal
Frequency for
Microcontroller

Three independently operating channels consisting of a latch, loadable counter and zero detector are used for
this purpose. Together with a microcontroller (e.g. SAB 8051) and suitable software, pulses are generated to
drive AC converters and inverters (three-phase) with an almost unlimited range of waveforms (sinusoidal,
triangular) and phase relationships. An oscillator with clock output, a programmable prescaler to adapt the
switching frequency to the requirements of the output stage, an interlocking stage with status flipflop and the
ability to program deadtimes are features that recommend the SLE 4520 for use in frequency converters to
drive three-phase induction motors.
. ,
Speed control of three-phase motors is easily done when such motors are supplied with a three-phase voltage
of which the Ulf ratio is kept almost constant with variable frequency. To generate this three-phase voltage a
frequency converter is required to rectify andJilter the AC supply voltage and subsequently reconvert it into an
AC voltage of different frequency by a drive circuit and three power half-bridges. To avoid high losses the
output stages operate in a switched mode and are driven by rectangular pulses which increase or decrease in
width, depending on the waveform of the sinusoidal function. To produce such pulses with a repetition frequency (switching frequency) up to the limit of the audible range, a drive block consisting of the SAB 8051
microcontroller and the SLE 4520 PWM as a minimum configuration proves to be best suited to the job.
4-42

SLE 4520

Block Diagram

ALE

Add,es.
Decoder

latch
1:4

SYNC
CTransfer)

Enable (dur n.tus)

SWltch-off Ff

In

Disable set status

Status
0151-1

Principle of Function
The combination of the SLE 4520 and the SAB 8051
microcontroller are described here. Other hardware
combinations are in general possible.
Oscillator on-chip feeds the programmable prescaler
and has a buffered output for the connected microcontroller. Interface to microcontroller has a width of
8 bits.
Data from the SAB 8051 p.C to the SLE 4520 PWM
are transferred via the data bus PO using control signals ALE and WR. Three 8-bit registers for the three
phases and two 4-bit registers to preset deadtime
and prescaler ratios, as well as an address decoder
latch to buffer particular addresses, are connected
to the internal data bus of the SLE 4520 (see block
diagram).
Addresses are as

follo~s:

Address

Register

00
01
02
03
04

8-Bit Register for Phase 1
8-Bit Register for Phase 2
.8-Bit Register for Phase 3
Deadtime Control Register
Divider Control Register

The last two registers have to be written only once
when initialized. In the case of a controller output the
above mentioned 3-bit address is latched and decoded with the falling e~ of the ALE clock. With
the rising edge of the WR signal data are loaded

from the bus into the registers of the pulse width
modulator. Divider ratio is selected by divider control
register.
To produce low switching frequencies with a simultaneously high microcontroller operating frequency the
divider control register is loaded in the initial routine
with an appropriate number. Allocation of value and ,
divider ratio is shown in Table 1.

Table 1. Allocation of Value In the Divider
Register to the Divider Ratio by Which the
SLE 4520 Operating Frequency Is Selected
Value

Divider Ratio
Counter

Divider Ratio

0
1
2
3
4
5
6
7

1:4
1:6
1:8
1:12
1:16
1:24
1:32
1:48

1:4
1:6
1:4
1:6
1:4
1:6
1:4
1:6

Delay Clock

The switching cycle should be selected after the ratio is fixed so as to barely reach·the maximum pulse
width. This means that with a PWM counter clock of,
e.g. 1 MHz (oscillatqr frequency of 12 MHz, divider
ratio 1: 12) and a table value of 127 (7 bits) the counter reaches zero after 128 p.s (switching frequency
cycle 128 ItS). Table 2 gives a number of useful allocations of counter and switching frequencies for the
SA~ 8051 (12 MHz clock).
4-43

SLE 4520
Table 2. Allocation of Counter Frequency and Switching Frequency of SAB 8051
Divider Ratio

Counter
Frequency

Operating Time
Timer 0

Switching
Frequency

Resolution

1:6
1:6
1:12
1:12
1:24
1:24
1:48
1:48

2MHz
2MHz
1 MHz
1 MHz
500kHz
500kHz
250kHz
250kHz

64",s
128 "'S
128 "'S
256 "'S
256",s
2x256",s
2x256",s
4x256",s

15.6 kHz
7.8 kHz
7.8 kHz
3.9 kHz
3.9 kHz
1.95 kHz
1.95 kHz
975Hz

7-Bit
8-Bit
7-Bit
8-Bit
7-Bit
8-Bit
7-Bit
8-Bit

Converting a Data Word Into a Pulse Width
Pulse generation in the three processing channels is
done by a presettable 8-bit downcounter and a zero
detector (NOR gate) which is connected to the eight
counter outputs. With the trigger pulse from the microcontrolier (which is one instruction cycle) whose
repetition rate determines the switching frequency,
the presettable counter is loaded with the contents
of the appropriate register and 0 appears at the zero
detector's output (provided the register does not
contain OOH).
This 0 digit enables the counter and starts it running
down. When zero is reached the pulse ends and the
counter is stopped until the next transfer pulse arrives. The crystal frequency multiplied by the divider
ratio clocks the PWM counter.

Selecting Deadtime by Presetting Control
Register to Avoid Overlapping Switching
Operations
Deadtime is defined as the period of time between
switching on one of the half-bridge transistors while
the other switches off, and vice versa, to obviate
dangerous overlapping of switching operations
("shoot-through"). In the pulse width modulator the
dead time is obtained by linking the pulse width
modulated source Signal and its delayed Signal. The
delay is obtained by passing the source signal
through a 15-bit shift register with 15 outputs.

Deadtime depends on the crystal frequency and the
preset divider ratio (1:4 or 1:6). For a 12 MHz crystal
frequency the programmable deadtimes are given in
Table 3.
Table 3. Deadtlme Presettable in the Deadtime
Register Using Divider Ratios of 1:4 and 1:6
Word In
Deadtlme
Memory

Divider
Ratio 1:4
Deadtlme (,...s)

Divider
Ratio 1:6
Deadtlme (,...s)

0
1
2.
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0.33
0.66
1.0
1.33
1.66
2.0
2.33
2.66
·3.0
3.33
3.66
4.0
4.33
4.66
5.0

0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5

Interface to the Power Circuit Provided by
Outputs PH1/1 t9 PH3/2

on the contents of the divider control register.

Without deadtime PH1 12 is inverted to PH1 11, PH21
2 to PH2/1 and PH3/2 to PH3/1. The active switching state is low.

16 deadtimes are presettable (including zero dead- time) by writing a value between 0 and OFH into the
appropriate control register.

With a programmed deadtime the negative edges of
the output signal are shifted to the right by the deadtime.

The shift pulse is either fC1;tal or fcry;taL, depending

4-44

SLE 4520
The outputs are capable of directly driving TIL devices or optocouplers for voltage isolation of drive
blocks and power circuits with currents up to 20 mAo

As the SAB 8051 sets the port outputs to high when
switched on, only one port pin of the microcontroller
has to be connected to inhibit. At the end of the
initialization routine this port pin is set to low. Another way of inhibiting the outputs (hold function) is to
apply a high pulse to the Set input (Pin 22) of the
status flipflop. This inhibit state is indicated by the
"Status" output (Pin 20) and can be used to indicate
or inform the microcontroller (active high; used, for
example, in the event of power failure, short circuit,
excess temperature, etc.).

Static or Dynamic Interlocking of Outputs
is Possible
All outputs are set to high level during the inhibit
signal (Pin 19): Hence, the light emitting diodes of
the connected optocouplers are currentless and all
six individual transistors of the power circuit are
blocked. This option is particularly needed when
switching on the drive block, as proper pulses at the
pulse width modulator output are only available after
the oscillator output has set up and the initialization
routine has been executed.

The status flipflop is cleared by a high pulse at the
"Clear Status" input (Pin 21).

Absolute Maximum Ratings·
Maximum ratings are absolute ratings. Exceeding even one of them may result in the destruction of the
integrated circuit.
parameter

Pos
1

Storage Temperature

Symbol
Ts

Min

Max

Units

-50

+125

·C

2

Total Power Dissipation

Ptot

500

mW

3

Power Dissipation per Output

Po

50

mW

4

Input Voltage

VIN

-0.3

Voo + 0.3

V

5

Supply Voltage

Voo

-0.3

6

V

'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Operating Range
Within the operating range the functions mentioned in the circuit description will be fulfilled. Deviations from
the characteristics are possible.
'
Symbol

Min

Typ

Max

Units

1

Supply Voltage

Vee

4.5

5

5.5

V

2

Supply Current
(Outputs Not Connected)

100

15

mA

12

MHz

+85

·C

Pos

Parameter

3

Operating Frequency

feLK

4

Ambient Temperature

TA

-40

D.C. Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
will apply at T A = 25·C and mean supply voltage.
Pos

Parameter

Symbol

Conditions

Min

Typ

Max

Units
V

All Input Signals Except XTAL 2

1

H-Input Voltage

2

L-Input Voltage

3

Input Capacitance

4

Input Current

VIH

2.2

Voo

VIL

0

0.8

V

CI

10

pF

IlL

1

p.A
4-45

SLE 4520

D.C. Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
will apply at TA = 2S"C and mean supply voltage. (Continued)
Pos

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Voo
0.3

V

Input Signal XTAL2 for External Clock

5

H-Input Voltage

VIH

4.0

6

L-Input Voltage

VIL

0

7

Input Capacitance

CI

10

pF

8

Input Current

IlL

1

p.A

V

Output Signals STATUS, Clockout

9

H-Output Voltage

VOH

10 = O.SmA

10

L-Output Voltage

VOL

10 = 1.6mA

V

Voo - 0.8
0.4

V

Output Signal8 PH1/1, PH1I2, PH2/1, PH2/2, PH3/1, PH3/2
11

L-Output Voltage

VOL

10 = 20mA

12

H-Output Voltage

VOH

10=1mA

Voo - 0.8

1

V

Voo

V

A.C. Characteristics
Parameter

Symbol

Min

TLHLL

100

ns

Address Setup to ALE

TAVLL

30

ns

Address Hold after ALE

ALE Pulse Width

Max

Units

TLLAX

30

ns

WRN Pulse Width

TWLWH

200

ns

WRN High to ALE High

TWHLH

SO

ns

Data Setup after WRN Low

TOVWL

20

ns

ALE Low to WRN Low

TLLWL

100

ns

Data Hold after WRN*

TWHQX

30

ns

Oscillator Period

Tosc

83

ns

High Time

TOSCH

3S

ns

Low Time

TOSCL

3S

ns

TYHYL

200

ns

SYNC Pulse Width
INHIBIT Low to Output Enable

TILOE

100

ns

Delay between SYNC High
to Output Active

TYHOA

97 Tosc
+20

ns

Chip Select Setup to ALE Low

TCHLL

Chip Select Hold after WRN High

TWHCL

30

ns

Reset Pulse Width

TRHRL

12Tosc

Set Status Pulse Width

TSHSL

200

ns
. ns

Clear Status Pulse Width

TCHCL

200

ns

4-46

4 Tosc
20

ns

SLE 4520

A.C. Characteristics

(Continued)

Parameter

Symbol

Min

Max

Units

TIHOD

100

ns

Set Status High to Output Disable

TSHOD

100

ns

Clear Status High to Output Enable

TCHOD

100

ns

INHIBIT High to Output Disable

Set Status Pulse Length
Clear Status Pulse Length
Inhibit Pulse Length
• If TWLWH shorter as 2 Tosc

+ 20 ns. then TWHQX

TSHTH

100

ns

TCHTl

100

ns

100

ns

TIHll
is 50 ns.

Pulse Diagram
T. . .

T.....

ALE
T.....

DATA

cs

Clodcout

..m

~
SYNC

PH111

T,_

~

'-

~

PH1/z

INHIIIl

t

0151-3

Ordering Information
Ordering Code
Q 671 OO-H 8271

4-47

SIEMENS

TCA 785

Phase Control
This phase control IC is intended to control. thyristors, triacs, and transistors. The trigger
pulses can be shifted within a phase angle between 0° and 180°. Typical applications
include converter circuits, AC controllers and three-phase current controllers.
This IC replaces the previous types TCA 780 and TCA 780 D

Features
•
•
•
•
•
•
•
•

Reliable recognition of zero passage
Large application scope
May be used as zero point switch
LSL compatible
Three-phase operation possible (3 ICs)
Output current 250 mA
Large ramp current range·
Large temperature range

Pin configuration
top view
Vs

16

Q2 Q1
1S 14

2

3

OS Q2 au

Pin No.

Symbol

Function
Ground
Output 2 inverted
Output U
Output 1 inverted
Synchronous voltage
Inhibit
Output Z
Reference voltage
Ramp resistance
Ramp capacitance
Control voltage
Pulse extension
Long pulse
Output 1
Output 2
Supply voltage

L

(,2

V
"

(,0

R9

13

12

11

10

1

9

Os

2
3
4
5
6
7
8
9
10

02

4
S 6 7
Q1 VSYNC I QZ

8
V.tab

OU

01
VSYNC
I
OZ
Vstab

Rg
C,o
V"
C'2
L

11

12
13
14
15
16

01
02
Vs

4·48

TCA 785

Functional description
The synchronization signal is obtained via a high-ohmic resistance from the line voltage
(voltage V5 ). A zero voltage detector evaluates the zero passages and transfers them to
the synchronization register.
This synchronization register controls a ramp generator the capacitor ClO of which is
charged by a constant current (determined by Rg). If the ramp voltage VlO exceeds the
control voltage V11 (triggering angle q> ), a signal is processed to the logic. Dependent on
the magnitude of the control voltage V11 , the triggering angle q> can be shifted within a
phase angle of 0 0 to 1800 •
For every half wave, a positive pulse of approx. 30 j.Ls duration appears at the outputs 1
and 2. The pulse duration can be prolonged up to 180 0 via a capacitor C12• If pin 12 is
. connected to ground, pulses with a duration between q> and 180 0 will result.
Outputs a 1 and Q 2 supply the inverse signals of a 1 and a 2.
A signal of rp +180 0 which can be used for controlling an external logic, is available at pin 3.
A signal which corresponds to the NOR link of a 1 and a 2 is available at output az (pin 7).
The inhibit input can be used to disable outputs a 1, a 2, a 1, a 2, au.
Pin 13 can be used to extend the outputs Q1 and Q 2 to full pulse length (180 0 - q».

a

a

~ Pulse

Block diagram

[12

12 extension

VSYNC 5
Sync. register

Vs

14 0.1

16

4 li1
logic

15 0.2

z liz
3 QU

7 QZ

GND 1

Discharge
transistor

8
V,tab

10 V" 11

[
10

T -

_Control
voltage

6 13
Inhibit long-pulse
commutation

4·49

TeA 785

Pulse diagram

Vs Synchronization voltage

v'o Ramp peak voltage
v'o Ramp voltage

v"

(ontrol voltage

V,o Min_ ramp voltage =Vsat

OV

v's -Q2
V'4 -Q1

V,5 -Q2 Pin 12 to GND
V,4- Q1 Pin 12 to GND
____ ...II

V2 - Q2 Pin 13 to GND
V4 -Q1

V) - QU
V, - QZ

o 'P

4·50

180 0

Pin 13 to GND

TeA 785

Maximum ratings
Supply voltage
Output current at pin 14, 15
Inhibit voltage
Control voltage
Voltage short-pulse circuit
Synchronization input current
Output voltage at pin 14, 15
Output current at pin 2, 3, 4, 7
Output voltage at pin 2, 3, 4, 7
Junction temperature
Storage temperature

Vs

Thermal resistance (system-air)

RthSA

Lower
limitS

Upper
limit A

-0.5
-10
-0.5
-0.5
-0.5
-200

18
400

Vo

Vs

Tj

125
125

V
mA
V
V
V
IlA
V
mA
V
°C
°C

80

KIW

10

V6
VII
V13
Is
Vo

± 200
Vs

10

10
T stg

Vs
Vs
Vs

-55

Operating range
Supply voltage
Operating frequency
Ambient temperature range

Vs
f
Tamb

810
1 -25

500
18
1 85

I~z°C

4-51

TeA 785

Characteristics
8:5:Vs :5:18 V; -25°C:5:Tamb :5: 85°C;f= 50 Hz

Test
circuit
No.

Lower
limitS

f=50 Hz
Vs =15 V
typ

Upper
limit A

Supply current consumption
S 1 ... S 6 open
V11 =OV
C10 -47 nF; Rg -=100 kQ

1

4.5

6.5

10

I:

30

Is

Synchronization pin 5
Input current
R2 varied
Offset voltage

.1V5

Control input pin 11
Control voltage range
Input resistance

R11

Ramp generator
Load current
Max. ramp voltage
Saturation volt. at capacitor
Ramp resistance
Sawtooth return time
Inhibit pin 6
switch-over of pin 7
Outputs disabled
Outputs enabled
Signal transition time
Input current
Vs=8V
Input current
Vs -1.7V
Deviation of 110
Rg=const.
Vs -12 V; C10 = 47 nF
Deviation of 110
Rg-const.
Vs=8to 18V
Deviation of the ramp voltage
between 2 following
half-waves. Vs =const.

4-52

I 5 ,ms

V11

I~

110
VlO

V10
Rg

tf

VSl
VSH

t,

130

1

1 0.2

100
3

ISH

~A

mV

1

225

1000
Vs-2
350
300

80

4
1

I

1 V10peak
115

10 ,
1
1.6
1
1

200
1 75

rnA

3.3
3.3

~Q
~A

V
mV
kQ
~s

2.5

V
V

5
800

~s

500
150

200

~A

~A

-Isl

80

110

-5

5

%

1,0

-20

20

%

.1V10 max

±1

%

TeA 785

Characteristics
8~Vs~18 V; -25°C~Tamb~85°C;

Long pulse switch-over
pin 13
switch-over of S 8
Short pulse at output
Long pulse at output
Input current
V13 =8V
Input current
V13 = 1.7 V
Outputs pin 2. 3. 4. 7
Reverse current
Vo=Vs
Saturation voltage
10=2 rnA

f= 50 Hz

3.5

-113l

45

Vsat

Internal voltage control
Reference voltage
Parallel connection of
10 ICs possible
TC of reference voltage

Lower
IimitB

V13H
V13l
113H

ICED

Outputs pin 14. 15
H output voltage
-10=250 rnA
L output voltage
10=2mA
Pulse width (short pulse)
S 9 open
Pulse width (short pulse)
with C12

Test
circuit
No.

26
1 .
2.6

I

0.1

f=50 Hz
Vs=15V
typ

Upper
limit A

2.5
2.5

65

2
10

V
V
I1A

100

I1A

I~O

10.4

I

:A

V14115H

3.6

Vs-3

Vs-2.5

Vs -1.0

V

V14/15l

2.6

0.3

0.8

2

V

tp

20

30

40

I1s

tp

530

620

760

I1s/nF

V,ef

2.8

3.1

3.4

V

2 X 10-4

5 X 10-4

11K

(X,ef

Application hints for external components
Ramp capacitance

C 10

Triggering point

tT,=

Charging current

lID""

min

max

500pF

111 Ft )

VII xRg xC10

2)

The minimum and maximum values of lID are
to be observed

V'ef x K

V,efxK

2)

Ramp voltage
Vl0max Vs -2 V
0=

Rg

V10 0=

V,elX K x t

Rg

X

2)

CIO

1) Attenuation to flyback times

2) K = 1.10 ± 20%

4-53

TeA 785

Pulse extension versus temperature
IIs/nF

780'
720

-

660

r--

600
c:
.iii
c:
0

i!

540

Vs=15V
C12=1nF

--

480

x

OJ

OJ
VI

"5

a.

420
360
300
240
180
60.1

f

o

-40

o

-20

20

40

80

60

100

O(

-T

Output voltage measured to

- \oj411S

f

3.7
3.5
3.3

~

Vs=15V

3.1
2.9
2.7
2.5

+ Vs

.-

.-

2.3

L~

2.1
1.9
.~1.7
1.5

IY

---

.....

~

......... r-

....

:::-:
...... --;;::::-.....

---------------~

~-

.-

-2S0( ~..-:.: ~
~ ~O(

/l+25°(

~

.

1.3

1.1
0.2 i'

o
o
4-54

1i
100

200

300

400
-lQ

500 rnA

Phase Control

TeA 785

Supply current versus supply voltage

rnA

6.5

. . .t:

Is 7.9

1/ ~25°(

.." "

f7.3
6.7
6.1

..~".,.
,c. --- 1;"

... "" ,,'10-'
. .r

4.9

/

/

-I/' ......

1/V-

."

5.5

""
L.-r

1-'
~."

I
I

;t

.' "

[,'

y ~5°(

r

l..~

'':85°(

I
I

II
I
I
I
I
I

4.3

1
6

10

12

14

16

18

20 V

-Vs

4·55

TCA 785

Test and measu,.ment circuit 1

;!:

~

\!!

N'

,....

...

u...
c

~

$:!

.~
CI'I
0

VI
S '"

-'

GI

Co..

f.f!

....-

.&;111
cOl
>oGl

VI'-

o..

CI'I.f!
... III
c:I'.&;111

... c:

III c:I

.- o..
c
-

...

L--+____ ...:.....{ H
~

~

~t

VI

It is necessary for all measurements to adjust the ramp with
the aid of C'0and R9 in the way that 3 V S Vrampmax S Vs -2 V

e.g. C'0-47 nF;18 V; Rg-47 kQ; 8 V; Rg-120 kQ

4·56

TeA 785

Test and measurement circuits
Measurement circuit 2

Pin
2,3,4,7,
14,15

I Vo.
f (V,al)

I
The residual pins are connected as in measurement circuit 1

Measurement circuit 3

Pin
14,15

The residual pins are connected as in measurement circuit 1

4·57

TCA 785

Measurement circuit 4
Vs/mV

r----------

75

I

I

70+---~----~-------------t

7S

• t

v

Pin S

T

10 llF

Residual pins are connected as in measurement circuit 1
The 10

~F

capacitor at pin 5 serves only for test purposes

Measurement circuit 5

Measurement circuit 6

+
Pin 3

Pin 11

t-------if------o

r;;-

Pin 1

4-58

0.5 V

TeA 785

Inhibit 6

Long pulse 13
-----1>----.--+

12 Jill

ZO
6.5

Outputs

Pulse extension 12

Reference voltage 8

-~-~---------1>---+

----...--.--+

t----t---<> Q

4·59

TeA 785

Additional circuit description
Application examples
Triac control for up to 50 mA gate trigger current

-=

L

R
)4.7kQ

I RSYNC

9W

220kQ

"\ 71N4005

Load

0.47 IJF!
LI

~

1

1

4.7kQ
B~61

15

VI

2~ ~ ~
220V...

470

BAY BAY
61 61

15V

~ 1=i ~-

16¥-

Q22IJF
~

25~

1

14

.!!.

13

1

.....

B~Y61
TCA 785

5

12

6

11

~

10

!

9

:zs

=*= 2.2IJFIMKHI
V10kQ

~

2.2kQ

J..

Te
TXC10M60~

22kQ[

=

0.1IJF

) =~= ;::

:Ok~ ~

(10

(12

47

150

nF pF

Mp

A phase control with a diretly controlled triac is shown in the figure. Th~ triggering angle of
the triac can be adjusted continuously between 0 0 and 1800 with the aid of an external
potentiometer. During the positive half wave of the line voltage, the triac receives a positive
gate pulse from the Ie output pin 15. During the negative half wave, it receives also a
positive trigger pulse from pin 14. Trigger pulse width is approx. 100 ILs.
4-60

TeA 785

Fully controlled AC power controller
Circuit for two high-power thyristors
<1:>

... i--------i--~~---l ~ ~

:I:

°

I
I

l

1

I -J

I'J

"'3:
0 ...
~~

~~
I

I

L___ .:- ~I--_- _____ -;._J

I-

I

JO.
'01

~

Q:

....,

- - - -------- t--"iC:-- ---------r---- f - -"ia

......

§
~

...""

0

~~

~~

...
iiiiiiiiiiiiiiit::

~

iiiiiiiiiOOiii

:--;-

...=...
a

~

~~

...'"

t:

In

c

..!!.

. d. . . . .

~","

LL

§:o:
ZNN

....c:

_IDU

Ii

~

~~r

a".

....

,....!:!.,

cl!! II

a
:::l

ID",

;:- m~~=
~
~
u ~fTI
g :::

LLc:

n:::
II

LL

.... II::'

aoX

*~

:::l

II,!:

.... II~

n

"iLL

it'

LL

~=?

:!!

\!!

;!

..."ll - I~
N

~

...:::

a

'"

.,.l:

L{~

~

d

P

- ...

rCA 785

,... ..,

In

!e_
m",

'"

...

eI>

v).,

"",-~:

~

""

~

1------------

T~
S!

In

I

~r--"''------_;..

.J

c:

~~
~.~
-u

I

Shown is the possibility to trigger two antiparalleled thyristors with one IC TCA 785. The
trigger pulses can be shifted continuously within a phase angle between 0 0 and 1800 by
means of a potentiometer. During the negative line half wave the trigger pulse of pin 14 is
fed to the relevant thyristor via a trigger pulse transformer. During the positive line half wave,
the gate of the second thyristor is triggered by a trigger pulse transformer at pin 15.
4-61

TeA 785

Half-controlled single-phase bridge circuit with trigger pulse transfonner and direct
control for low-power thyristors

......

J:

.c

...

I-

$!

:c

~

~

0

0

N

0

Q

.

Q

~

/'"

'"
Q

N

l-

X

N

/"

c:
...

E

§

~

~

~

;-;;

......,

c:

........

,..:!..,

c:
0

c:
0

....
~II~

~

:;;

~1I!:i
II

N
N

?c

'"

N
N

~

.. II'E

?cL

...

c:

CD

...

....

~

'"
N

c:
...

::::

N

jt

~I

II

~

!;Q

;!

]

-

~S

Q::~~

~

"'I

"'1

"'I

?c

II

..... co:O
...

~

~~

ci

>

!;Q

5:1::. §'"
~~ ~
v

>
0

4-62

.
II

u
OJ

;::

$!

'"

...

"'1

""I

TeA 785

~

...
!:i

~

'S.~

'"

~5:1
~:>.
d

~

R

"%
o I»
:E:::;:
4.7kQ

n

CD
.. 0

RSYNC

9W

;:~

2.SSI004~ 0

220kQ

-Vo

lN4005

02

01

ill a.

fi
22 Vo[

0.47pF: ~

~

w

]
BAY BAY
61 61

~

5

t!L

I

15

1

=1=;~15V

-I

n
l>
-..3
CD

U1

BAY 61

220Q

..

220Q

B~Y61

14

I»

RL

,--

~.

12 : F:2.2pF

6

11

1

10

.!

9

V

p,J

2.2kQ

n~II.lle I

lDkQ

1T1 ...
lN4001

n~1 ./11:

2.2~ T2

2 .'

~

a.

2.2kQ

co
CD

lN4001

\

2.

\

a
§:
~.

(,.

F:

R,~
l00kQ

~

;:
-Vo

:

(12

~;n~ ~p

CD

:::!.

Thl Th2
22kQ '"

"en

~

13

O.lpF:

Mp

!e.

ce.CD

, 4.7kQ
1

1001DpF
.16 'de

l~
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2xBSt01D41

i

-.
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co
co
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ii1
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ill

.0-

~

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,
0'

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J>

....

co

U'I

SIEMENS

TeA 1561 B, TeA 1560 B
Bipolar Ie Stepper Motor Drivers
• Simple Drive

• 2.5A Peak Current
•

High-~peed

Integrated Clamp Diodes

• Thermal Overload Protection with
Hysteresis

Pin Configurations

Pin Definitions

TeA 1561 B
(Top View)

TeA 1561 B
Pin

Symbol

Function

,

1

01

Phase Input 2

2
3

Output 01
Phase Input
Enable Input
Actual Curre.1t
Supply Voltage
GND
Sync InputlRC
Nominal Current Input
Output 02

Q'

Enabl. Input :3

Actual Current 4

v,

4

o

S

GND 6

5
6
7
8
9

Sync Input/RC 7
Nominal Current Input •
Q2 9

TeA 1560B
(Top View)

TeA 1560B
Pin

Q, ,
Phase Input 2
Enable Input 3
4

Vs

5

GNO

6

GND

Sync Input IRC

7

Nominal Currtnt Input

8

Q2

9

02

The cooling fin is connected internally to pin 6 (ground).

0158-1

Actual Current

Vs
Os
RC

,,.

Mu,t be Conneded
to PHI 6

1

01

2
3
4
5
6
7
8
9

Vs
Os

10-18

0158-19

Symbol

RC

02

Function
Output 01
Phase Input
Enable Input
Actual Current
Supply Voltage
GND
Sync InputlRC
Nominal Current Input
Output 02
Ground (Must be
Connected to Pin 6)

The TCA 1561 8 is a bipolar monolithic IC deSigned to control the motor current in one phase of a bipolar
stepper motor. It can also be used to drive direct-current motors as weil as all inductive loads operated by
constant current.
'
The IC has TIL-compatible logic inputs and contains a full-bridge driver with integrated, high-speed clamp
diodes and chopper-operated dynamic motor current limiting. The nominal current is infinitely variable with a
control voltage. Using minimum external components and a single supply voltage, two TCA 1561 8 ICs form a
complete and directly MC-drivable system for two-phase bipolar stepper motors with output currents up to
2.5A per phase. The functionally identical TCA 1560 8 in the P-DIP-18-L9 package is designed for output
currents up to 1.25A.

@Siemens Components, Inc.

4-64

May 1988

TCA 1561 B, TCA 1560 B

Block Diagram
.24V

TTl-Levet

TTl-Level

lOOnF

Sync Input/RC Pin 7
Switch Position
a. Sync Operation
b. Free-Running Operation

Circuit Description
Outputs
Outputs 01, 02 (Pins 1, 9) are fed by push-pull output stages. The two integrated clamp diodes, referred to ground or supply voltage respectively, protect the IC against flyback voltages from an inductive load.

Enable
Outputs 01 and 02 are turned off when voltage
VI3 ~ O.8V is applied to pin 3. The supply current
then decreases maximally to 1 mA. The same occurs if pin 3 is open. The sink transistors are. turned
on when VI3 ~ 2V.

Phase
The voltage at pin 2 determines the phase position
of the output current. Output 01 acts as sink for VI2
~ O.8V and as source for VI2 ~ 2V.
Similarly output 02 acts as
Sink when VI2 ~ 2V and
Source when VI2 ~ O.8V
The sink transistors are .current-chopped. An internal
circuit avoids undesired cross-over currents at
phase change.

0158-2

Nominal Current Input
The peak current in the motor winding is determined
by the voltage at pin 8. A comparator compares this
with the voltage drop at the actual current sensor at
pin 4. If the nominal current is exceeded, the output
. sink transistors are turned off by a logic circuit.

Sync InputlRC
Outputs are turned on by a signal at pin 7. Two operation modes are possible: Synchronizing by a fed-in
TTL signal or free-running with the external AC combination.

Free-Running Operation
When the supply voltage is applied, capacitor C7 at
pin 7 charges to a limiting voltage, typically 2.4V.
With increasing current in the motor winding, the
voltage rises at the actual current sensor A4 (pin 4).
After exceeding the predetermined value at the
nominal current input (pin 8) the comparator, in conjunction with pulse suppression, resets an AS flipflop. The logic turns off sink transistors T3 and T4.
C7 ceases charging and the parallel resistance A7
then discharges C7. The sink transistors remain
turned off until the lower threshold voltage of the
Schmitt trigger is reached. This off period is thus
controlled by the time constant ts = A7 X C7. After
the lower trigger threshold has been passed, the

4-65

TCA 1561 B, TCA 1560 B
monoflop is triggered by the falling edge of the
. Schmitt trigger output and, provided the voltage at
the actual current sensor (pin 4) is lower than the
nominal value at pin 8, the RS flipflop is reset. The
logic circuit then turns on the sink transistors T3 or
T4 and recharges capacitor C7. If the voltage at pin
4 rises above the comparator value at pin 8, the sink
transistors T3 and T4 are turned off again. Turn-on
cannot be repeated until capacitor C7 has discharged to the lower trigger threshold, the discharge
time being a function of R7 and C7.

Synchronous Operation
If a TIL level sync signal is fed to pin 7, the negative
edge sets the RS flipflop, via the Schmitt trigger/monoflop combination, provided that the voltage at pin
4 is below the nominal value at pin 8. As in the freerunning operation mode, the relevant output transistors become conducting. Similarly they are cut off by
resetting the RS flipflop once the voltage at pin 4 is
higher than the nominal value at pin 8.

Pulse Suppression
In all cases the puse suppression circuit eliminates
positive pulses, typically of 0.5 JLs duration, at pin 4.

These can result from cross-over currents in chopper operation through the integrated clamp diodes.
As a result, the voltage at pin 4 rises well above the
nominal value, and without pulse suppression this
would lead to dynamic current limiting. The duration
of these basically unavoidable cross-over currents is
of the same order of magnitude as the reverse-recovery time of the clamp diodes.

Temperature Safeguard
If the temperature of the IC rises to approximately
150·C, the final stages are turned off. At approximately 1300C they are turned on again.
Logic Table
Enable

L

L

H

H

Phase

L

H

L

H

OutputQ1

/

/

L

H
L

OutputQ2

/

I

H

Transistor T1
Transistor T2
Transistor T3
Transistor T 4

X
X
X
X

X
X
X
X

X

L
H
X
•
••

•

••
X

•

X
X

••

at:
V4> 10mV
R4>

on

= Low voltage level, Input open
= High voltage level
= Transistor turned off

= Transistor conducting
= Transistor conducting with current limiting turned on
I = Output high-impedance

Absolute Maximum Ratings·
Tc = -25·C to +85·C
·Stresses above those listed under, "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Supply Voltage, Pin 5 (Vs) ......... -0.3Vto +45V
Supply Current, Pin 5 (Is) ............. OA to + 2.5A
Peak Current in Output
Transistors, Pins 1, 9 (Ia) ....... - 2.5A to + 2.5A

Diode Currents
Diode against + VS (lFH) .................. 2.5A
Diode against Ground (IFU ................ 2.5A
Input Voltage, Pins 2, 3, 7, 8 (VI) ....• -0.3V to + 6V
Output Current, Pin 4 (14) .............'..... - 2.5A
Voltage, Pin 4 (V4) ................ - 0.3V to + 5V
Ground Current, Pin 6 (16) ................... 2.5A

4-66

Junction Temperature (Tj) ................. 150·C·
Storage Temperature (Tstg) •.••• - 40·C to + 125·C
Thermal Resistance
System-Ambient (Rth sAl ........•...... 70 K/W
System-Package (Rth sel ................ 8 K/W

Operation Range
Supply Voltage, Pin 5 (Vs) .......... , ... 8V to 40V
Package Temperature (Tel ....... - 25·C to + 85·C
Input Voltage, Pins 2, 3, 7 (VI) .................. 5V
Output Current (Ia) ..... '............ - 2A to + 2A
"ICs provide optimal reliability and service life if the junction
temperature does not exceed 125°C in operation. Operation
up to the maximum permissible limit of the junction temperature at 1500C is possible in principle. It should be noted,
however, that exposure to absolute maximum rating conditions for extended periods may effect device reliability.
Within the operating range the functions given in the circuit
description will be fulfilled. However, deviations from the
characteristics are possible.

TCA 1561 B, TCA 1560 B

Characteristics Tc = 25°C; Vs = 24V
The listed characteristics are ensured over the operating mage of the integrated circuit at the given supply
voltage and ambient temperature. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics will apply at Tc = 25°C and Vs = 24V.
.-

Parameter

Symbol

Limits

Conditions

Units

Typ

Max

VI3 = VIH

18

30

mA

Is

VI3 = VIL

0.5

1

mA

Output Voltage: Source

VOH

1101

1.9

V

VaH

1101

= 1A
= 1.5A

1.7

Output Voltage: Source

1.9

2.1

V

VOL

1.2

1.4

V

1.5

1.7

V

Min
Supply Current, Pin 5
Supply Current, Pin 5

Is

Output, Pins 1, 9

Output Voltage: Sink
Output Voltage: Sink

VOL

1101 = 1A
1101 = 1.5A

Reverse Current

11051
tT

Figure 1

Phase Dead Time

0.1

300

p.A

0.3

1.0

p.s

1.0

1.2

V

1.1

1.3

V

Forward Voltage of Diodes
against +Vs

VFH
VFH

IFH = 1A
IFH = 1.5A

Forward Voltage of Diodes
against Ground

VFL

IFL = 1A

1.1

1.3

V

IFL =1.5A

1.3

1.5

V

H Input Voltage

VIH

0.8

V

100

p.A

100

p.A

2

p.s

VFL
Inputs: Enable, Pin 3 and Phase, Pin 2

L Input Voltage

VIL

H Input Current

L Input Current

IIH
-IlL

Rise and Fall Time

tr, tf

2
VIH
VIL

= 5V
= OV

V
50

Nominal Current, Pin 8
Control Range

0

Input Current

VI8
-118

Input Offset Voltage

VI (8-41

VI8 = OV
Figure 5·

Control Range

VI4

Figure 5

Turn-Off Delay

td

Figure 3

2

V

5

p.A
mV

0

Actual Current, Pin 4
0

2

V

3

P.s

1

100

kHz

0.1

0.9

2

Sync Input/RC, Pin 7
Sync Frequency

f

Duty Cycle: 0.5

Rise and Fall Time

"tr, tf

f = 40kHz

Output Current, Pin 7

-107

Trigger Threshold, Pin 7

VL7

Duty Cycle

Charging Limit C7
Off Period
Dynamic Input
Resistance, Pin 7

2
1.2
Figure 2
2.2

VG7
ts

Figure 4

RI7

V7 = 1.5V

1.6

2.0

P.s
mA

0.6

0.8

V

2.4

V

64

,..,S

1

kfi

4-67

TCA 1561 B, TCA 1560 B

Absolute Maximum Ratings·

Storage Temperature (Tstg) ..•.. - 40·C to + 12S·C

Tc = -2S·C to +8S0C

Thermal Resistance
System-Ambient (Rth sA> ....•..••••.•.. 70 K/W
System-Package Measured
at Pin 14 (Rth SC> •..........•...••..... 1S K/W

*Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Range
Supply Voltage, Pin S (Vs) •.•..•.....••. 8V to 40V

Supply Voltage, Pin S (Vs) •.•...... - 0.3V to + 4SV
Supply Current, Pin S (Is) ...•...•••. OA to + 1.2SA

Package Temperature Measured
at Pin 14 (Tc) ................ - 2S·C to + 8S·C

Peak Current in Output
Transistors, Pins 1, 9 (10) •••. -1.2SA to + 1.2SA

Output Current, Pins 1, 9 .(10) ......... -1 A to + 1A

Diode Currents, Pins 1,9
Diode against + Vs (IFH) •.•.•.••.•....... 1.2SA
Diode against Ground (1Ft.> ...•...•....... 1.2SA
Input Voltage, Pins 2, 3, 7, 8 (VI) .•..• - 0.3V to + 6V
Output Current, Pin 4 (14) ••••••••••••••••• -1.2SA
Voltage, Pin 4 (V4) ................ - 0.3V to + SV
Ground Current, Pin 6 (16) .................. 1.2SA

Input Voltage, Pins 2, 3, 7 (VI) .................. SV
*ICs provide optimal reliability and service life if the junction
temperature does not exceed 125'C in operation. Operation
, up to the maximum permissible limit of the junction temperature at 150"C is possible in principle. It should be noted.
however, that exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Within the operation range the functions given in the circuit
description will be fulfilled. However, deviations from the
characteristics are possible.

Junction Temperature (Tj) .............•... 1S0·C·

Characteristics Tc

= 2S·C; Vs = 24V
The listed characteristics are ensured over the operating range of the integrated circuit at the given supply
voltage and ambient temperature. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics will apply at T C = 2S·C and Vs = 24V.

Parameter

Symbol

Limits

Conditions
Min

Typ

Units
Max

Supply Current, Pin S

Is

VI3 = VIH

18

. 30

mA

Supply Cutrent, Pin S

Is

VI3 = VIL

O.S

1

mA

Output Voltage: Source

VOH

1101 = O.SA

1.6

1.8

V

Output Voltage: Source

VaH

1101 = 0.7SA

1.6S

1.90

V

Output Voltage: Sink

VOL

1101 = O.SA

1.0

1.2

V

Output Voltage: Sink

VOL

1101 = 0.7SA

1.1

Output, Pins 1, 9

1.4

V

300

,...A

0.3

1.0

,...s

0.9

1.1

V

IFH = 0.7SA

0.9S

1.1S

V

IFL = O.SA

0.9S

1.1S

V

1.0

1.2

V

Reverse Current

11051

Phase Dead Time

tT

Figure 1

Forward Voltage of Diodes
against +Vs

VFH

IFH = O.SA

VFH

Forward Voltage of Diodes
against Ground

VFL
VFL

0.1

IFL = 0.7SA

Inputs: Enable, Pin 3 and Phase, Pin 2
H Input Voltage

VIH

L Input Voltage

VIL

2

H Input Current

IIH

VIH = SV

L Input Current

-IlL

VIL = OV

Rise and Fall Time

t r, tf

4-68

V
SO

0.8

V

100

,...A

100

,...A

2

,...s

TCA 1561 B, TCA 1560 B

Characteristics Tc = 25"C; Vs = 24V (Continued)
The listed characteristics are ensured over the operating range of the integrated circuit at the given supply
voltage and ambient temperature. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics will apply at Tc = 25"C and Vs = 24V.
Parameter

Symbol

Limits

Conditions
Min

Typ

Units
Max

Nominal Current, Pin 8
Control Range

0

VIS

Input Current

-lis

VIS = OV

Input Offset Voltage

VI/S-4)

Figure 5

VI4

Figure 5

td

Figure 3

2
5
0

V
/LA
mV

Actual Current, Pin 4
Regulating Range
Turn-Off Delay

0

2

V

3

/Ls

1

100

kHz

0.1

0.9

2

Sync Input/RC, Pin 7
Sync Frequency

f

Duty Cycle: 0.5

Duty Cycle

1J

f = 40kHz

Rise and Fall Time

tr, tf

Output Current, Pin 7

-IQ7

Trigger Threshold, Pin 7

VL7

Charging Limit C7

VG7

Off Period

ts

Figure 4

Dynamic Input
Resistance, Pin 7

RI7

V7 = 1.5V

1.2
Figure 2
2.2

2

/Ls

1.6

2.0

mA

0.6

0.8

V

2.4

V

64

/Ls

1

kn

Internal Wiring of·Pins
Sync InputlRC

Ph... rz-C'O=kal--~_ _

-v,

-+

=

H>--t-+--+-'!' Output,

3 k0I--_--I:.
Enoble",,3-C

+--+---I~9 Output!

ZOkA

Nominal B

Current

GND

Actual Current
0158-3

4-69

TCA 1561 B, TCA 1560 B
Phase Dead Time

r:-./

v;
Pln3

Phase Dead Time

Pin 2Vi'I L---1
Pin/f
~::::::::::::~~:::::::SO%
H

Pm9

\

~f'

f,.f, S5On.

~---_+--~~5O%

'k---7F----~,...--__"I~50V.

0158-4

Figure 1

Trigger Threshold

Turn-Off Delay
Vaz

Pin 9

t

50%

-f
0158-5

Figure 2
Pin 4

_I
0158-6

Figure 3

Off Period Ts = f(cq)

00.1

10

lOnF

-[,

0158-7

Figure 4

4-70

TCA 1561 B, TCA 1560 B
Control Range, Input Offset Voltage

v..

t

PinS

OY''------

~O~Y~

foY=f--- 2Y

Pin 4

Va,

Pin 9

----

f

r_I
0158-8

Figure 5
Quiescent Current, Iq
versus Supply Voltage Vs

Permissible Power Dissipation Ptot
versus Package Temperature Tc

mA

W
16

40

t- -1\

\

1\

10
~

\

ZO

\

.......... V

\

4

10

1\

o
o

10

ZO

-v.

30

40

Forward Current IF of Clamp
Diodes versus Forward Voltages VF
A
2,5

,,/"
. /V

1,5

........

/'

1,0

1/

25 50 75 100 125 ISO 175'(
0158-1

2,5

Source
~

\

-25 0

-7i:

Output Saturation Voltages Vsat
versus Output Current la
v
V.!Z4V
-r, .25'(

o

50V

/'

V

I II
f 2,0 r-- agalnst+l~ II I
7,=25'(
II
1,5

If

DIOde

III

1,0

k..24V
TJ =25'(
0,5
r-- Sink

f
I

0,5

1,0

-1.

1,5

2,0

2,5A

o
o

DlOde
against Ground

7,.Z5'(

U

l

0.5

I

]
0,5

1,0

1,5

-v,

Z,OV
0158-10

4-71

TCA 1561

e, TCA

1560

e

Quiescent Current Iq
versus Supply Voltage Vs

Permissible Power Dissipation Ptot
versus Package Temperature Tc

mA
40

W
12

Plot

t
20

....-

r\
\

....

~

\

\

10

\

o
o

w

~

~

u

~V

1\

o

-25 0 25

~

-\IS

75 100 125 1~ 175°(
-------- 7( I
0158-11

Output Saturation Voltages Vsat
versus Output Current IQ
v
2,0

Forward Current IF of Clamp
Diodes versus Forward Voltages VF
A

r-- Vs!24V
r- r, =25°(
I-- Source

- - ---

v..,

f 1,5

....

....

....

....
0,5

I

,
8

r-

D,od.
against. I's

r, =25°(

0,6

,

0,4

-V,=24V
t- ~ =2S0(

Diode
against Ground-

r- Sink

o

o

4-72

1,0

0,2

r, =2S

0,2

0,4

-I.

0,6

0,8

1.0 A

o
o

0,5

0 (

I
I
1,0

1,5

2,OV

-II,
0158-12

TCA 1561 B, TCA 1560 B

0158-13

Pulse Diagram for Application Circuit
v,..

~----u---u----

- - - ---,

v,.~~---

v,.
v..

r~ -,gJ

00

IXI IXI

bSL _

-=;~~:::J~~~;~~~Z=
=---r5!1!
&:r
IXI

IXI

tOi~ __..r:=====-=..:-:....:-:...:J~__________
Jl
CJ
c=

l,'_J----~--~Tc===----_--_-_-~--~~--~'~--~~-c==J

1~----I.r=J---I.....,c:::::Jr----r-..L.r----=-_-lJ--r-LCl----'--,LJr---r-..r=J--...L..,-L
.
Siundb,

Hall-Slop Driving I=O,SA

I

Hul'-Slop Driving I·IA
0158-14

4-73

TCA 1561 B, TCA 1560 B
tOFF = Turn-Off Time

Calculation of Power Dissipation

tdON = Turn-On Delay Time

The total power dissipation Ptot comprises
(Transistor saturation voltage
Saturation
and diode forward voltages)
Losses Psat
Quiescent Current (Quiescent current multipled by
Losses Po
supply voltage)
Switching
Losses Ps

(Turn-on/Turn-off operation)

Turn-Off Delay Time
T = Cycle Duration

" = Duty Cycle tplT
Vsatu = Saturation Voltage of
Sink Transistor (T3, 4)
Vsate = Saturation Voltage of
Source Transistor (T1, 2)

The following equations give the power dissipation .
for chopper operation without phase reversal. This
can be regarded as "worst case", as, in addition to
the switching losses, full-load current flows for the
entire time.

= Psat + Pq + Ps
+ VFo (1

Ptot

~OFF =

with Psat "" IR (Vsatu - v

- v)

VFo = Forward Voltage of Clamp
Diode (01, 2)
Vs

= Supply Voltage

+ VsatoJ

Pq = Iq-Vs
Ps ""

IR

Vs {id-idON
Od + ir)
IR (
)
T
- - 2 - + - 4 - +"2 tdOFF + tOFF

}

= Rated Current (Mean Value)

Iq = Quiescent Current
id = Reverse Current During
Turn-On Delay Time
R

ir = Peak Reverse Current
tp = Conducting Time of Chop Transistor

0158-15

tON = Turn-On Time

Calculation of Power Dissipation
Turn-Off

Turn-On

'.

~---i~----~
0158-16

Characteristics for determining the typical power dissipation during chopper operation without phase reversal.
Parameters: Lload

4-74

=

10 mH, C7

=

820 pF; R7

=

33 kO; T c

=

2S"C

TCA 1561 B, TCA 1560 B

Quiescent Current Loss Pq
versus Supply Voltage Vs
w

Saturation Loss Psat versus
Phase Current I

w

\0

7

/
/

0,6

I

IL

0.5

0,3

/~=2tald 3Bi'

f

0,2

V

V

I

0,4

V

I

1

O,B
0,7

J

o

r

0.9

/

'/

0,1

o

\0

\5
-1

2,0 A

o

0510152025303540V

-v,

0158-17

Characteristics for determining the typical power dissipation during chopper operation without phase reversal.
Parameters: Lload = 10 Il)H, C7 = B20 pF; R7 = 33 kO; Tc = 25°C

Switching Loss Ps
versus Phase Current I

Total Power Dissipation Ptot
versus Phase Current I
w

w

\0

Ps

f

9

0,9

8

0,8

117

/

0,6

~

114
V,=3av

0,3

..IV

112
~
o -""

o

7
6

I

0,5

0,1

I

l's=3BV

V

V,=24V

3

/11'

~ , / ~=24V

0,5

1,0

\5
-I

2PA

0,5

1P

1,5

2,0 A

-I
0168-18

Ordering Information
Type

Ordering Code

TCA 1561 B

Q67000-AB209

P-SIP-9

Package

TCA 1560 B

Q67000-AB208

P-DIP-18-L9

4-75

SIEMENS

TLE 4201 A, TLE 4201 S
DC Motor Driver
The TLE 4201 IC is a dual comparator that is particularly suitable as a driver for reversible
dc motors and may also be used as a versatile power driver.
The push-pull power-output stages work in a switch mode and can be combined into a full
bridge configuration.
The driving of the comparators may be analog in the form of a window discriminator, or it
can be accomplished very simply with digital logic.
Typical applications are follow-up controls, servo drives, servo motors, drive mechanisms,
etc.
Features

•
•
•
•
•
•
•
•

Max. output current 2.5 A
Open-loop gain 80 dB typo
PNP input stages
Large common-mode input-voltage range
Wide control range
Low saturation voltages
SOA protective circuit
Temperature protection

The TLE 4201 IC comes in two different packages: with the SIP 9 package it is possible to
remove the heat by way of a cooling fin to a suitable heatsink, whereas with the DIP 18-L9
package the pins 10 through 18 are thermally linked to the chip and provide for heat dissipation
by way of the circuit board.

4-76

TLE 4201 A
TLE 42015

Block diagram
Supply
5

95kn

~

3
Inputs

~

Amp 1

odB

BOdB

-/
V

2

Divider
potential 6

7

r--

1
Power
limiter
and
temperature
protection

TLE 4201

\;---"

Inputs

f'l

Amp 2

odB

BOdB

B

1 Output Q1

V

9 Output Q2

V

87kn

4

GND
Figure 1

4-77

TLE4201 A
TLE4201 S

Pin configuration
TLE4201 A
Pin No.

TLE 4201 S
Pin No.

1
2
3

1

2
3
4

4

5
6

5
6
7

7
8
9
10 to 18

8
9

Function
Output of 1st amplifier
Inverting input of 1st amplifier
Non-inverting input of 1st amplifier
Ground
Supply voltage
Divider potential
Non-inverting input of 2nd amplifier
Inverting input of 2nd amplifier
Output of 2nd amplifier
Ground; to be connected to pin 4

Circuit description
The IC contains two amplifiers featuring a typical open-loop voltage gain of 80 dB at 500 Hz.
The input stages are PNP differential amplifiers. This results in a common-mode input voltage
range from 0 V to almost the value of Vs, and in a maximum input differential voltage of I Vs I.
To obtain low saturation voltages, the sink transistor (lower transistor) of the push-pull AB
output stage is internally bootstrapped. An SON protective circuit protects the IC against
motor short circuits and ground short circuits. An internal overtemperature protection protects
the IC against overheating in case of failure due to insufficient cooling or overload.
For logic control, a divider potential of approx. Vs/2 is available at pin 6 (see application
circuit 2). This makes the IC particularly suitable for digital circuits, as power driver.

Application
Figure 2 shows a window discriminator operation with the control voltage VI.
The window within which the motor is to stop is set by R2 .
Figure 3 shows driving by logic inputs A and B. The motor is controlled according to the
following truth table.

A

B

Output

L
L
H
H

L
H
L
H

Motor stopped (slowed down)
Motor turns right
Motor turns left
Motor stopped (slowed down)

4-78

TLE4201A
TLE4201 S

Application circuits
Operated as window discriminator

r-----....----------o + Vs
5
51kQ
3

2

VI

TLE

6
1kQ

R2

c

4201

100nF

.t1 12V I OJA

7

9
B

Figure 2

Digital control
for input signals applies: H ~ 0.6 Vs
L s: 0.3 Vs
.-----.-~--~+Vs

5

A

3-+-_-1

0 -_ _ _

2

6

TLE 4201

B c>--_+--...:.7-+-_-I
9

8

, Figure3
4-79

TLE4201 A
TLE4201 S

Maximum ratings

Upper
limit A

Lower
IimitB

Tease = -35°C to 85°C
Supply voltage
Supply voltage (t~ 50 ms)
Output current
Voltage of pins 2, 3, 6, 7, 8
Voltage of pins 1, 9
Junction temperature
Storage temperature

10
V
V

-0.3
-0.3

Vs

7j

150
125

-55

Tstg

Thermal resistance
TLE 4201 S: system-air
system-case
TLE 4201 A: system-air1)
system-PC board 1)

V
V
A
V
V
°C
°C

25
36
2.5

Vs
Vs

R thJA

65

RthJC

8

R thJA

60

RthJA1

44 1)

K/W
K/W
K/W
K/W

Operating range
Supply voltage
Case temperature
Voltage gain
(at negative feedback with external components)

Characteristics
Is
Gvo
RI
Va 10

sink operation

Va 20

Rise time of Va
Fall time of Va
Turn-on delay time
Turn-off delay time
Input current
(pins 2, 3, 7, 8)
Input offset voltage

tr
tf
ton
toft

1) see figure 8

4-80

Tease

Gv

Test
conditions

Vs=13V, Tease = 25°C
Supply current
Open-loop voltage gain
Input resistance
Saturation voltages,
source operation

3.5
-35
25

Vs

II
VIO

Figure 4: S =
f=500 Hz
f-1 kHz
Figure 5:
10 =0.3 A
10 = 1.0 A
10 =-0.3 A
10 =-1.0 A
Figure 4 and
Figure 4 and
Figure 4 and
Figure 4 and
Figure 5
V2• 3.7, B =0
Figure 7

V
°C
dB

17
85

Upper
limit A

Lower
limit B

typ

30

1

20
80
5
1.0
1.2
0.35
0.7
1.5
1.5
3.0
1.5

1.1
1.6
0.5
1.0

V
V
V
V
J..Ls
J..Ls
Ils
Ils

1.5

3.0
20

IlA
mV

1

rnA
dB

MO

S1

rr
1
2
2
6
6
6
6

-20

TLE 4201 A
TLE 4201 S

Test circuits
+ Vs

r

5
JOOIIF
2
soon
S

soon

OOnF

220nF

~

3
6

VQ

TLE 4201

15n

9W

B

9

Iv,

I

t-t

7

220nF

51kn

Figure 4

+Vs

5

2

3

1

S1

2

I

6

I
I

B

I

9

I
I

1

S12
~21Q
A

TLE 4201

7

~n

I

10W

I

1

I

I

J
VQ2

I

l

l_________ ~ ------t--------- J
FigureS
4-81

TLE 4201 A
TLE 4201 S

Pulse diagram

0.5 VI

/

o

/

\

v
0.9 VQ
0.5 VQ

/

0.1 VQ

/

1\

/I

Figure6·

4-82

-

-.I

t.on

tr

i+-

I-

-

toff

~

tf

1\
'--

l-

TLE4201 A
TLE4201 S

Test and measurement circuit
,.

+ VS12

'r-

:1100nF I

I

son )son

~1100fJF I

4.9Skn

-

I

s

~

2
VIC

free

t

1

V

3

o------i

TLE 4201

~

7
VIO '

100" VIO

~
8

9

V

100" VIO

J
4

4.9Skn

-

sonl )son
,I.

1

-.l1100fJF

1

II
I
:1100nF I

,

Figure 7

4·83

TLE4201A
TLE4201 S

Thermal resistance of TLE 4201 A
Thermal resistance, junction-alr, Rth JA 1 (standard) versus side length 1 of a square copperclad cooling surface (35 IJ.m copper plate)
0) ... 60 KIW
Tamb:S: 70°C
Pv-1 W
substrate vertical
circuit vertical
static air

Rth JA (/-

1.0
R lhJA1 (IJ
RthJAU=ol

0.9

f
0.8

o
FigureS

4-84

so
1-

100 mm

SIEMENS

TLE 4202
Power Bridge
• Max Output Current 2.5A

• Wide Control Range

• Open-Loop Gain 80 dB Typ

• Low Saturation Voltages

• PNP Input Stages

• SOA Protective Circuit

• Large Common-Mode Input-Voltage Range

• Temperature Protection

Pin Definitions

-

Pin

Symbol

Function

1

11

2
3
4
5
6
7

T

Input 1
Input 3 Inverted
Output
Ground
Output
Supply Voltage
Input 2

01
GND

02
Vs

12

The TLE 4202 IC is a power dual comparator that is particularly suitable as a driver for reversible DC motors
and may also be used as a versatile power driver.
The two power comparators may, either in combination in a full bridge, or separately, switch magnets, -motors
and other loads. The IC is designed for automotive applications. It functions at package temperatures from
-40·C to + 130·C.
The driving of the comparators may be analog in the form of a window discriminator, or it can be accomplished
very simply with digital logic.
Typical applications are follow-up controls, servo drives, servo motors, drive mechanisms, etc.

@Siemens Components, Inc.

4-85

April 1988

TLE 4202

Block Diagram
Supply
Vs

6

L.

095k!l
Input I
I,

~

~

~

VI

r

BOdS

OdS'-

-/

~

I3
L.

utput I

Q,

Output
Limiter
Input 3
Inverted
I)

Input 2

TLE4202

2;J-

and
Temperature
protection

7"

~

~
BOdS

Iz

V
[

OdS,....-

V2

V

IS
utput2

Qz

B7kO

S4t
round

GND
0081-1

4-86

TLE 4202

Circuit Description
The IC includes two amplifiers with an open loop gain of 80 dB at 500 Hz.
The input stages consist of PNP differential amplifiers. This results in an input common mode range of OV to
almost Vs and a maximum differential input voltage of Vs. In order to achieve lower saturation voltages the
sink transistor ("low transistor") of the push-pull-AB-output stage is internally loaded (boot strapped). The IC is
protected against short circuits to ground using an SOA protection circuit.

Absolute Maximum Ratings*
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings for case Temperature -40·C
Pos

Parameter

< Tc <

Symbol

130·C
Limits

Conditions
Min

1

Supply Voltage

Vs
Vs

2

Supply Voltage (t ::;; 50 ms)

3

Output Current

10

4

Voltage at the Pins 11. 12. T

V1,2,7

5

Voltage at the Pins 01. 02

V3,5

6

Junction Temperature

TJ

7

Storage Temperature

Ts

Tc::;; 85·C

Units

Max
25

V

36

V

3.0

A

-0.3

Vs

V

-0.7

Vs + 0.7

V

150

·C

125

·C

-3.0

-55

Operating Range
Maximum ratings are absolute limiting values; any of which if exceeded may result in destroying the integrated
circuit.
Pos

Parameter

Symbol

limits

Conditions

Min

Units

Max

1

Supply Voltage

Vs

3.5

17

V

2

Case Temperature During Operation

Tc

-40

+85

·C

3

Voltage Gain (with Feedback
with External Circuit)

Vu

dB

30

Thermal Resistances
4

System-Case

RthSC

5.0

K/W

Outputs 01 and 02 short circuit protected to GND.

4-87

TLE 4202

Ratings
Aatings encompass the reproducibility of the values as limited by the stated operating range of the integrated
circuits. Mid-range values to be expected from a production run are noted under typical ratings. Unless
otherwise indicated, typical ratings apply at Tc = 25°C and a supply voltage Vs of 13V.

Pos

Parameter

Symbol

Conditions

Measuring
Circuit

LImits
Min

Units

Typ

Max

30

40

General Characteristics
1

Quiescent Current

2

Open Loop Gain

Is

S=1

1

Vuo

f=500Hz

1

111,7

Vll, 12 = 0

2

f = 1 kHz

70

80

rnA
dB

Input Characteristics
3

Input Current (Pins 11, 12)

4

Input Impedance

All,7

5

Input Off-Set Voltage

VIO

1.5

1

1

3

-20

3.0

5

p.A
Mn

20

mV

Output Characteristics

6

Source Drive

Va

10 = -0.3A
10 = -1.0A

S1 = 1
S1 = 1

2
2

1.0
1.2

1.1
1.6

V
V

7

Sink Drive

Va

10 = +0.3A .S1 = 2
10 = +1.0A S1 = 2

2
2

0.35
0.7

0.5
1.0

V
V

8

Current Limit

lOmax

Source Drive

2

3.0

9

Short Circuit Current

ISh

Vs = 7V;Vo = OV

2

Rise-Time from Va

tr

Figure 1

1

11

Fall-Time from Va

tf

Figure 1

12

Turn-On Delay

13

Turn-Off Delay

ton
to"

Figure 1
Figure 1

2.0

2.5

A

1.8

2.3

A

Switching Times
10

4·88

1.5

p.s

1

1.5

p.s

1

3.0

p.s

1

1.5

p.s

TLE 4202

Test Circuits
Test Circuit 1

10k

51kll

~.

VQ1

TLE4202

lVI

l.

27k

l.

VQ2

~

l.
10k

51kll

1

0081-2

Test Circuit 2

10k

51

,

,i

I

I'·

10k

t____________ ___

4

1

--------------_ .. _-- ... _-_ .. _---------- --_ .... -- ..... - ....... _..... _--0081-3

4-89

TLE 4202

, Test Circuits

(Continued)

Test Circuit 3

..

'IjVnF
SOli

[ 5011

'tto

,,

F

"

4,9Skll

T

6
~

VIO

t

,

:::-..:--...
VI

'OOxV~ 1
]

-;/'
'\.

2

7

VG~

TLE4202

-~
VZ

5

~ .......

IOO'v,·l

.....
4

1

'.9Skll

'~F
O!

SOD

SOD

- -

..

'~nF

"
I

,

0081-4

Application Circuit
1---~----"t-"t-..,..........,---o']V

10k

VII

V"

10k

0081-5

4-90

TLE 4202
Diagram
V

5

.5

o

VQt V

/

O.5V

~

/

-t

o.9

/

o.5

o.1
J

-

-

ton

\

/

\
t,

-

~

-

-

toH

-t
tf

:..-

~

ooe1-6

Figure 1

Ordering Information

4-91

SIEMENS

TLE 4211
Intelligent Low-Side Driver
• Double Low Side Driver, 2 x 2A
• Protection Against Reversed Polarity

• Integrated Power-Z-Diodes
• Failure Monitoring
• Supply Voltage 5.0V ... 32V
• Temperature Range -40°C ... 125°C

• Output Power Limiting
• Overtemperature Protection

Pin Definitions

,

Pin

Symbol

Function

1
2

Os
11
01
GND
02
12
Vs

Status Output
Control Input 1
Output 1
Ground
Output 2
Control Input 2
. Supply Voltage

3
4

5
6
7

-

This device has been designed for the industrial and automotive electronics application field requiring intelligent power switches activated by logic signals, which are also short-circuit resistant and provide for error
feedback.
The TLE 4211 includes two of these power switches (low-side driver). During inductive loads, the integrated
power Z-diodes clamp the self-induced voltage.
By means of the TTL signals at the control inputs (active low), both switches can be activated independently of
one another.
The status output (open collector) signals the following interferences through low potential:
-Overload
- Open circuit
- Short-circuits to ground
- Overvoltage

@Siemens Components. Inc.

4-92

April 1988

TLE 4211
Block Diagram

ontrol
,"put

2

protective
circuit

protective
circuit
2
open CirCUit output 1

overload oulpull
short-circuit to ground output'

dead time

open c,rcult output 2
overload output 2
,hort-Clrcult to ground output 2

outpu

. . . .------------I4t-----------..J
ground

Note:

0082-1

1. Reverse biased diode

Description of Circuitry
Input Circuits
The control inputs comprise TTL compatible Schmitt
~riggers with hysteresis. Driven by these stages, the
Inverted buffer amplifiers convert the logic signal for
driving the power NPN transistors.

Switching Stages
The output stages comprise NPN power transistors
with open collectors. Since the protective circuitry
allocated to each stage limits the power dissipation,
the outputs are short-circuit proof to the supply voltage over the entire functional range. Positive voltage
peaks, which occur during the switching of inductive
loads, are limited by the integrated power Z-diodes.

Monitoring and Protective Functions
The outputs during the activated status are. monitored for open circuit, overload, and short-circuit to
ground. In addition large sections of the circuit are
deactivated in response to unduly high supply voltages Vs. Linked to the OR gate, the information regarding these malfunctions effects the status output
(open collector, normally high). An internally established dead time applied to all malfunctions with the
exception of overvoltage prevents the output of
messages for short-term malfunctions.
Furthermore, a temperature protection circuit avoids
thermal destruction. An integrated reverse diode
protects the supply voltage against reversed polarities. Similarly the load is protected against reversed
polarities within the limits established by the maximum ratings (no short-circuit of the load at the same
time!).
At supply voltages below the functional range an undervoltage detector avoids activating of status or
outputs.

4-93

TLE 4211

Absolute Maximum Ratings
*Stresses above those listed under "Absolute Maximur:n Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Position

Parameter

Symbol

Umlts

Conditions

Min

Max

-45

+45
+80
+45
+45

Units

Voltages
1

Supply Voltage (Pin 7)

2
3

Input Voltage (Pin 2; Pin 6)
Output Voltage (Pin 1)

Vs
Vs
VI
Vo

t::;; 500ms
-5
-0.3

V
V
V
V

Currents
10
10

VI = VIL;TG::;; 85'C
TG ::;; 85'C

10
10
10
IGND
101

VI
VI
VI

10

Output Current (Pin 3; Pin 5)
Current with Reversed
Polarity (Pin 3; Pin 5)
Z-Current (Pin 3; Pin 5)
Z-Current (Pin 3; Pin 5)
Z-Current (Pin 3; Pin 5)
Ground Current (Pin 4)
Output Current (Pin 1)

11
12

Junction Temperature
Storage Temperature

TJ
Ts

4
5
6
7
8

9

+2.8
-2.8

= VIH, V = 1(1)
= VIH, t = 10 ms, V = 0.2(1)
= VIH, t = 1 ms, V = 0.2(1)
-5.6

-50

A
+0.5
+1.5
+2.2
+5.6
+10

A
A
A
A
mA

+150
+150

'c
'c

Note:
1. See page 12. The optimal reliability and operating life of' the integrated circuit is ensured, if the junction temperature does
not exceed 125'C during operation. Although it is possible in prinCiple to operate the system at a max. Junction temperature of
150'C, the reliability of the IC may diminish In proportion to the duration of the max. junction temperature.

Functional Range
Within the functional range, the IC operates as described; deviations from the characteristic data are possible.
Position

'I
2

Parameter
Supply Voltage
Case Temperature

Symbol
Vs
Tc

Umlts

Conditions
(Note 1)

Units

Min

Max

5.0
-40

32
125

'c

5
65

K/W
K/W

V

Thermal Resistances
3
4

System-Casing
System-Air

Notes
1. Lower limit = 4.2V, if Vs

4-94

~

RthSC
RthSA

5V before (hysteresis)

TLE 4211

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
apply at T C = 25°C and Vs = 12V.
Position

Parameter

Symbol

Conditions

Test
Circuit

Limits

Units

Min Typ Max

General Characteristics
1
2
3
4
5

Quiescent Current
Quiescent Current
Overvoltage Threshold
Underload Voltage Threshold
Underload Current

Is
Is
VST
VOT
lou

= W = VIH
= W = VIL
10 = 5 rnA; Vo < O.4V
10 = 5 mA; Vo < O.4V
Vo = You
VI
VI

1
1
1
1
1

34
75

2
80
36
100

4
120
38
125
50

rnA
rnA
V
mV
mA

1.0

V
V
V

10
10

p,A
p,A

20

0.4
30

V
p,s

0.6

0.8

V

300

p,A

Logic
6
7
8

9
10

Control Input
H-Input Voltage
L-Input Voltage
Hysteresis of
Input Voltage
H-Input Current
L-Input Current

1
1
1

VIH
VIL
~VI

=
=

5V
0.5V

2.0
0.7

1
1

IIH
-IlL

VI
VI

VOL
tds

10 = 5mA
(Note 1)

1
1

1

Status Output (Open Collector)
11
12

L-Saturation Voltage
Status Dead Time

12

Switching Stages

21

Short-Circuit Current

22

Leakage Current

10

= 2A; VI = VIL
Vo = VS;VI = VIL
Vo = VS;VI = VIH

23

Switch-On Time

ldE

Figure 2

1

50

p,s

24

Switch-Off Time

tdA

Figure 2

1

50

p,s

25

Flow Voltage of
Substrate Diode

VOF

10

=

1

1.3

1.5

Vo
rZ

10

= 0.1A
< 10 < 2A

36
2

38

OA

20

Saturation Voltage

VOL
Ish

Power Z-Oiode (Vs
26
27

10

-2.5A

1

2.2

2.5

1

A

V

= 40V; 81 Open)

Z-Voltage
L-Internallmpedance

1
1

34

V

.n

Note:
1. Time from the beginning of the interference at one channel (exception: overvoltage) until the 50% value of the status
switching edge.

4-95

TLE 4211

Test Circuit (1)

IS

7
'0

I,'

6

--['0 ["

VI

TLE
4211

10'

4

Vo

1. 1. 1.

1.

I

Vo

1.

0092-2

Figure 1
VI

t

VIH
50%

VIL

-+t
tetE

..-

'0 A

t

2

0082-3

Figure 2

4-96

TLE 4211

Application Circuit
I

.Vs_UVO

220nFI

7

2
6
statu,
output

C.:2: L1112

11

3

control
inputs

c·

I
I
I
I
I
I
I
I
I
I
I

TLE
4211

L1
12

5
L2

Vuttl'Y

+ L2122

(45V - VS)2

0082-4

4·97

TLE 4211

Diagrams
Quiescent Current Is as a
Function of the Casing
Temperature Tc in the OFF Status
mA

A

I

IvsVI ==VI"12V= VII" /.

Is

L
2

Short Current 10 as a Function
of the Output Voltage Vo

"

·50

10

I.Vs = 12V

1

VI:I VI\.

\

\

~

..........

o

'""

50

100
_ _ Tc

I

r\

~

·c

40V
30
_ _ Yo

20

10

~

0082-5

Output Voltage Vo as a Function
of the Output Currrent 10
v

Permissable Z-Current loz as a
Function of the Pulse Duration tI~
A

t05~

____

~ ~~~
__

____

I
.:......-

Yo

~

v

-

o F------+------t------+-i

v=0.2

1------+---------11------+--1

*

+--

r---.....::: ~O

~t:::

0.5

·1.0

= tplT

T

2

·0.5

I

Vs = 12V
V, = V'H

_=1

t-----'''''''''...,j;;:=-----t------+-i
0.2

0082-6

Ordering Information
Package
Similar to TO-220/7

4-98

ICs for Communications

'SIEMENS

TBB042G
Mixer
The TBB 042 G is a symmetrical mixer applicable for frequencies up to 200 MHz. It can
be driven either by an, external source or by a built-in oscillator.
Common applications are in receivers, converters, and demodulators' for AM and FM
signals.
Features

•
•
•
•
•

Wide range of supply voltage
Few external components
High conversion transconductance
High pulse strength
Lownoise

,.

5-1

TBB 042 G

Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
Thermal resistance (system - air)

Tstg
RthSA

Operating range
Supply voltage range
Ambient temperature range

Vs
TA

15
150
-40 to 125
125

Vs

7j

14 to 15
-15 to 70

V
°C
°C

K/W

1

~C

Characteristics
Vs=12V,TA=25°C
Current consumption
Output current
-"
Output current difference
Supply current
Power gain
(t; = 100 MHz, fos c ,= 110.7 MHz)
Breakdown voltage
(/2,3 = 10 mA; V7 ,a = 0 V)
Output capacitance
Conversion transductance
(f= 455 kHz)
Noise figure

5-2

/s =

/2

+ /3 + /5
/2

=

/3

- /2

/3

/s

Gp
V2 , V3

min.

typo

max.

1.4
0.36
-60
0.7
14

2.15
0.52

2.9
0.68
60
1.6

1.1
16.5

25

mA
mA
mA
mA
dB
V

C2_M' C3 -M
S=~ = /3

5

pF
mS

NF

7

dB

V7 -Va

V7 -Va

6

TBB 042 G

Test circuit
~F

10nF

=10,7 MHz

r--i

fosc

F

3/3 turns

= 110.7 MHz

Application circuit
Mixer for remote control receiver
self-oscillating
10nF

f,

1

J-tr---.--+--------,
: 460 kHz
I

fosc

~F

= 26,66 MHz

For harmonic crystals~ an inductor between pins 9 and 11 which will prevent oscillations on the fundamental is recommended.
5-3

TBB042G

Circuit diagram
2

4

3

Bkn
6

2,2kn

2,2kn

7
10
3,3kn
12

L-------4----l-+---+----o 1,5,8,13,14
-11

9

It is recommendable to establish a galvanic connection between pins 6 and 7 and pins 10
and 12 through coupling windings.
A resistor of at least 220 0 may be connected between pins 9 and 14 (GND) and pins 11
and 14 to increase the currents and thus the conversion transconductance. Pins 9 and 11
may be connected via any impedance. In case of a direct connection between pins 9 and 11
the resistance from this connection to pin 14 may be at least 100 O. Depending on the
layout, a capacitor (10 to 50 pF) may be required between pins 6 and 7 to prevent
oscillations in the VHF band.

5-4

TBB 042 G

Total current consumption
versus supply voltage

Output current
versus supply voltage

mA

IJA
800

4

,
3

,.
,.";

2
",'

.' .;" l/'
,.- ,.-

","

;/

,,1;'

....

...

"

t

600

_...

....

500

; /~

1/

/

..

Iz=I3 700

i-"

.....

400
300

...

1"-- - .-

1--1--

-

-

- - .-- .--- -

.~-

~

.....
~~

f--

.-

200

,. 10-',,"

,,;

100

0 4 5 6 7 B 9 10 11 12 13 14 15 V

04 5 6 7 8 9 10 11 12 13 14 15 V
-Vs

-Vs

Power gain
versus supply voltage

dB
18

j' ~

1/ ~
1/
14

~

i;""

..... I-"

--

12

10

8

6 4 5 6 7 8 9 10 11 12 13 14 15 V
-Vs

5-5

SIEMENS

TBB 200, TBB 200 G
PLLFrequency Synthesizer
Type

Ordering code

TBB 200
TBB200G

Q67100-H8215
Q67100-H8216

Package

P-DIP-14

I P-DSO-14 (SMD)

The TBB 200 is a CMOS IC which has been specially developed for use in radio equipment.
It is both suitable for single frequency synthesis and dual modulus synthesis.
Features

• Bit seriai control with 2 lines (12C bus)
• Modulus switching
• Voltage doubler for high phase-detector output voltage
. ' Direct VCO drive without operational amplifier
• High input sensitivity (10 mV), and high input frequencies (70 MHz) for single modulus
operation
• Low supply voltage, wide temperature range
• Standby circuit
• Extremely fast phase-detector with very short anti-backlash pulse
• Large dividing ratios
- A divider 1 to
127
- N divider 3 to 4095
- R divider 3 to 65535
• Switchable phase-detector polarity
• Switchable phase-detector fine tuning rate
• PORT output addressable via 12C bus
- for prescaler standby
- for programming the prescaler (128 or 64)

2C bus is a patented bus system of Philips.

5·6

TBB200
TBB200G

Circuit Description

The TBB 200 is a complex PLL component in CMOS technology for processor controlled
frequency synthesis. The SID pin sets the operating mode, i.e. Single or Dual modulus
operation. The function settings and selection of the divider ratios are made via an 12C bus
interface on the SDA and SCL pins. A PRT output port enables the control of further
circuits (e.g. standby). The reference frequency is supplied via the RI input; this may be
up to 30 MHz. The VCO frequency is supplied via the FI pin; in single modulus operation
this may up to a max. of 70 MHz and in dual modulus operation up to a max. of 30 MHz.
The PLL can be operated with or without the voltage doubler as required, depending on
the desired frequency variation (varicap). For operation with a voltage doubler a capacitor
of typically 1 ~F (MKH) should be connected to pin C. C must be grounded if the voltage
doubler is not used.
The frequency fVD is derived from RI. The divider factor is set via the 12C bus. The PD output
supplies the phase detector Signal with especially short anti-backlash pulses for the
compensation of even the smallest deviations in phase. The polarity and current level of
the PD output are selectable via the 12C bus. The LD output provides a static lock detector
signal and the FV output supplied the divided VCO frequency. LD and FV are open drain
outputs.

Operating mode

SID

MOD

Single modulus
Dual modulus

L
H

H

UH

5-7

TBB200
TBB 200 G

Pin Configuration
(top vi.ew)

14 LD

Voo

RI

13

2

[

12 PO

SID
SDA

4

11

SCL

5

10 FV

PRT

6

9

GND 2

MOD

7

8

FI

GND1

Pin Description
Pin

1
2

3
4
5
6
7
8
9
10
11
12

13
14

5·8

Symbol

Function

Voo
RI

Supply voltage
Reference frequency
Operating mode (single modulus/dual modulus)
12C bus data
12C bus clock
12C PORT
Modulus control
VCO frequency
Ground
Comparison frequency
Ground
Phase detector
Voltage doubler capacitor
Lock detector

SID
SDA
SCL
PRT
MOD
FI
GND2
FV
GND
PD
C
LD

R[

1

I

I

1l(

-I

U

~
~

Standby

7-Bit SIR

"7
7-Blt Latch

1 ~}
PD
Polarity

f--

~7- Bit A Counter

I
I

I

~

r

F[

Y'
U)

'"---'

GNO 2

Voltage
Doubler

I+-

(

Phase
Detector

r---

PO

Lock
Detector

t-- LO

I
I

I

GNO 1

Vee

I

16-Bit SIR

~
12-Bit SIR

1

{}

I

12- Bit N Counter

~

.---!-Y-

I

,L~
~

.f ~

I •

I--

~

"

Y.12-Bit Latch

• I

1

iii

:I

16-Bit L,t"

I

I 2 C Interface

SI I

U)

A

Volt. Doubler OnlOff
Clock

PORT

iii"

r

T/R

PRT

:II\"

C

.()-

Data

SCL

I've
I

116-Bit R counterl

Latch
Enable
Frequency

.sOA

+2
(+4)

m
is"

n

Control
logic

I

FVN

alai
mm
1\)1\)

MOD

00
00
G)

TBB200
TBB200G

Maximum Ratings
min.
Supply voltage
Input voltage
Output voltage at C
Power dissipation per output
Total power dissipation
Storage temperature

'Voo
ViM 1
ViM 2

typo

-0.3
-0.3
-Voo

Po
Ptot
Tstg

-50

Voo

3

max.

Unit

6
Voo+0.3
0
10
300
125

V
V
V

5.5
3.5
3
1

V
mA
mA
\-1 A
mA

85

°C

mW
mW
°C

Notes

Exception: C
(internally
generated)

I

Operating Range
Voo=5 V, TA =25°C
Supply voltage
Supply current single mode
dual mode
standby
standby preamp. on
prescaler off
Ambient temperature

[DO
[DO
[DO
[DO

TA

1.5
-40

Test conditions, PLL locked, RI -10 MHz
for(j)
for®
(1=50MHz
VFI =150 mV
NT, RT >1000
Operatio~ without
voltage doubler

5-10

5
2.5
2

(1=10 MHz
VFI =500 mV
NT, RT >1000
Operation without
voltage doubler

(j)
®
®
®

for®
(1=50 MHz
VFI =150 mV
Output circuitry
see application circuit

TBB200
TBB 200 G

Characteristics
Test
conditions

min.

max.

Unit

0.7 x Voo
0

Voo
0.3 X Voo
10
10

V
V
pF

Voo
0.3 X Voo
10
10

V
V
pF
!-LA

10
10

MHz
mV
pF
!-LA

10
10

MHz
mV
!-LA
pF

Input signals SOA, SCl
H input voltage
L input voltage
Input capacitance
Input current

IIjH
IIjL

CI
11M

IIj = Voo=5.5 V

~A

Input signal S/O
Input voltage
L input voltage
Input capacitance
Input current

0.7 x Voo
0

IIjH
IIjL
CI

liM

IIj = Voo =5.5 V

'1

Voo = 4.5 V
(sine)

Input signal RI
Max. input frequency
Input voltage
Input capacitance
Input current

IIj rms
CI

30
100

11M

IIj = Voo =4.5 V

'1

Voo = 4.5 V
(sine)
IIj = Voo =4.5 V

30
50

voo = 4.5 V
(sine)

70
10

Input signal FI (dual modulus)
Max. input frequency
Input voltage
Input current
Input capacitance

IIj rms

11M
CI

Input signal FI (single modulus)
Max. input frequency
Input voltage
Input capacitance
Input current
Input frequency

11M
'1

1Ij= Voo =4.5 V
Voo =3 V

10
10
35

MHz
mV
pF
!-LA
MHz

VOL

10 =3.0 mA

0.4

V

'1
IIj rms
CI

Output signal SOA, lO
(open-drain output)
L output voltage

Voo =3 V
C L = 400 pF

5-11

'.

TBB200
TBB200G

CharacteristiC$
Voo = 4.5 V to 5.5 V; TA = -40 to 85 DC
Test
conditions

max.

typo

max.

Unit

± 1.9
±0.475

±2.5
±0.625
±50

±3.1
±0.775

rnA
rnA
nA

0.4

V

Output signal PO
(tristate output)
H current mode
L current mode
Tristate

IOH

Voo =5 V

IOL

10

TA =-25 to 60°C

L output voltage

VOL

1 rnA
Voo=5 V
CL =30 pF

L output pulse width

tOWL

Output signal FV
(open-drain output)
IOL =

1/FI

Output signals MOD, PRT
(push-pull output)
H output voltage

VOH

L output voltage

VOL

IOH - 0.5 rnA
Voo = 5 V
IOL =0.5 rnA
Voo= 5 V

V

Voo -o.4
0.4

V

I 0.4

Iv

0.4

V

Output signal MOD
(open-drain output)
L output voltage

-0.5 rnA
Voo=5 V

VOL

IOL

VOL

I OL =3mA

Output Signal LD
(open-drain output)
L output voltage

Voo=5 V
CL =30 pF
L output pulse width

towL

Pulse Diagram

Signal LD

fnWL

5·12

10

ns

TBB200
TBB 200 G

Dynamic Characteristics
Voo = 5 V; TA =-40 to 85 DC
Test
conditions

min.

Voo =5 V
Voo =5 V
Voo = 5 V

5
5
5

ns
ns
ns

Voo = 5 V
Voo =5 V
Voo =5 V

3.5
3.5
3.5

ns
ns
ns

Voo =5 V
Voo = 5 V
Voo =5 V

5
5
10

ns
ns
ns

max.

Unit

Input signal RI
Rise time
Fall time
Pulse width

fiR
flF
f lw

Input signal FI
Dual modulus
Rise time
Fall time
Pulse width

tlR
tlF
tlW

Single modulus
Rise time
Fall time
Pulse width

fiR
flF
f lw

Pulse Diagram

5-13

TBB 200,
TBB 200 G

Dynamic Characteristics
Voo = 5 V; TA =-40 to 85°C

Voltage doubler
Output voltage

Test
conditions

min.

vac'

fvo=2 MHz

Vac

lac == 0 ILA
Voo = 5 V
fvo =2 MHz

Vac

Vac

Current consumption

loo

loo

5·14

lac = 100 ILA
Voo = 5 V
fvo =2 MHz
lac=O ILA
Voo =3 V
fvo;" 2 MHz
lac = 100 ILA
Voo =3 V
Voo =5 V
lac =0 ILA
fvo =2 MHz
Voo=3 V
lac = 0 ILA
fvo =2 MHz

typo

max.

Unit

-Voo+0.8 V

Voo

V

-Voo +1.5 V

Voo

V

-Voo+0.8 V

Voo

V

-Voo +1.5 V

Voo

V

250

ILA

180

ILA

TBB200
TBB200G

Dynamic Characteristics
Vee = 5 V; TA =-40 to 85°C
Test
conditions

min.

max.

Unit

1
1

Il s
Il s

Output signal PRT
Rise time
Fall time

Vee" 5 V; CL .. 30 pF
Vee = 5 V; CL = 30 pF

tOR
tOF

Output signal FV
Fall time

I

30 pF

I 20

I ns

tOR
tOF
teoLH

Vee = 5 V, CL = 30 pF
Vee = 5 V, CL = 30 pF
Vee = 5 V, CL = 30 pF

10
10
25

ns
ns
ns

teoHL

Vee = 5 V, CL - 30 pF

15

ns

tOF

veo = 5 V,

cL -

Output signal MOD
Rise time
Fall time
Delay time
L-H on FI
Delay time
H-L on FI

Pulse Diagram

:: ==~_=='=~__~~~~~==::.~=-~j_--=--===--=-__-~_=_-===s~g~~_~~~~-_~
1/

~MI
I
VCH

------- -

~~L
Signal MOD

I

~-------_ _ _ _.1\

----------------

---------------

\

---i

5-15

~

Cf'
......

I»
:I
In

Q)

:3

ii'

S·
:I

~

Sub Address

I - - - Main Address

i
,

I

(IC Address)

,
I

,

..-----n

I

SDA

2-

Data ----------<~.....:

.. I •

g

I
I

2-

,
,

~

-!ol_ _-

I

;:;

o

I

9

SCL

,,
,,
,
,,
I

///

I
'I
I

I
I
I
I

I
I
I
I

I
!
I
I
I
I
I
I
, , '

(
I

J l,
---_______

I
I

O~tput
:
,first
I
'Data Word'

::
!!

L__

_-------

......... _---

-l (
J

I

II,
II

I

::

:I

_J

I

I

l

::

............... '1

,

I

:

l..,

:

,

I

I

I

:

,

fSTART CONDITION :
,SDAT. whenSCL=H,
I

:I

I

I

~

:,

/')

II

I
i
i,
I
,

I
I
I
I

I
I
I
,

I

Output nth Data Word

I

,

l.,,,-

"../"'/

I

,Select· Readl Write 'Acknowledge from Slav~1 I Acknowledge from Slave ,
iL=OutputtromMaster iReady Confirmation
I !IPrompt for further Output)'

I
I

:

I
I

:
,

,
I

:

i

:
)

,Slave:

-I

I

I
1
I
,

:

r:Acknowledg~l
... __ .... __

,

r
I
I

I

I

!
i

!

ID

c

In

l. ____ _.

-----,

'STOP CONDITION i
~DA.l""When SCL=H I
",

I

1
Acknowledge
v.Slave

I
I

i

alai

mm
~~

00
00
G)

TBB200
TBB200G

Transmission Protocol for Programming
STATUS
SDA

Start
1
2

Single Modulus

3

ICA
D
R

4
5
6

S
S

7
8
ACK
1
2

E

E

3

SU8A
D
R

4
5
6

S
S

7
8

E

E

1
1
0
0
0
1
0
0
0
0
0
0
1.
0
0
0

Dual Modulus

1
0
0
0
1
0
0
0
0
0
0
1
0

ACK
2

3
4
5
6

7
8

S
T
A
T
U
S

PORT
Counter
FI, RI
PD-Polarity
PD-Current
Voltage-Doubler Frequency
Voltage-Doubler Status
Modulus Output

Statusbit

0
Low""
off"
off"
neg.
0,625 rnA
+2
off
push pull

High""
on
on
pas.
2,5 rnA
+4
on
open drain

ACK
Stop

• Standby
•• PORT-output state

5-17

TBB200
TBB200G

Transmission Protocol for Programming
R Counter

SDA

SingleModulus

ICA
0
R

E
S
S

E
SUBA
0
R

E
S
S

E

Start
1
2
3
4

5
6
7
8

SDA

DualModulus

1

1

0
0
0

0
0
0

0
0

0

1

ACK
2
3
4

5
6
7
8

0
0
0
0
0
1
0
0

0
0
0
0
0
1
0

3
4
5
6
7
8

R

C
0
U
N

ACK
1
2
3
4
5
6
7
8

5
6
7
8

0
0
0

5
6
7
8

0
0

R

LSB

0

1
2
3
4

0
0
0
0

1
2
3
4

0
0
0
0

5
6
7
8

1
1

5
6
7
8

1
0

0
0

1
2
3
4
5
6
7
8

ACK
X
X
X
X
MSB
N

C

ACK
2
3
4
5
6
7
8

ACK

ACK

Stop

Stop

X
X
X
X
X
MSB

A
C

0

ACK

0

U
N

1
2
3
4
5
6
7
8

U
N

T
E

R

LSB

1
2
3
4
5
6
7
8

T
E
LSB

ACK
Stop

R

MSB
N

ACK
2
3
4
5
6
7
8

5·18

1
0
0
0

ACK

T
E

AlN Counter
Dual·Modulus

Start
1
2
3
4

ACK
MSB

SDA

Single-Modulus

Start
1
2
3
4

ACK

ACK
1
2

N-Counter

C
0
U
N

T
E

R
LSB

TBB 200
TBB 200 G

min.

max.

Unit

'SCl
tHO. OAT
tBUF

0
0

100

kHz
IJ.s

4.7

IJ.s

Start condition hold time (the first
CLOCK pulse is generated after this period)

tHo, STA

4.0

IJ.s

Clock LOW phase
Clock HIGH phase

tl
tH

4.7
4.0

DATA set-up time
SDA and SCL signal rise time
SDA and SCL signal fall time
SCL clock set-up time on STOP condition

tsu, DATA
tR
"t F
tsu, STOP

250

Set-up time for status
(SID) programming

tso

IJ.s
IJ.s
ns
IJ.s
ns
IJ.s
ns

PRT delay time relative to
stop condition

tOPRT

Clock frequency
Hold period for data at SCL LOW
Inaktive period before restart of transmission

All figures are referred to the specified input levels

~H

and

1
300
. 4.7
500
500

IJ.s

~l'

•

Pulse Diagrams for 12C Bus, SID, PRT

SDA

SCL

SID

~~tso+--F___

I

_~;--t'~f=

__
PR_T

5-19

TBB200
TBB200G

Application Circuits

liP

TBB 200

PO

MOO PRT

r----'

GND'l

L ____ --'I

GNO

til

MOO
IN~----------------~

TBB 202

H

iN
VDD

Operation: Dual modulus (fmax = 30 MHz on FI)

liP

12 c Bus

T

y

SeA SCL

RI

LD

SID

Voo

TBB 200'

GNO 2 FI

,-------,

I,

I

~ Prestaler __- - - - - - -....
IL ______ .JI

Operation: Single modulus (fmax == 70 MHz on FI)
LF: loop filter

5·20

TBB200
TBB 200 G

Application Circuit for VCO Coupling
+

Voo
TBB 200

GNO 1

PO

r-----'r--------,I
I
I
I

C

VCO I
I
I Vpo

I
L ____ ...l

I

L _______

I
I

o~

Vpo ~Voo

i

J

Operation without voltage doubler (status bit 7 = 0)

+

Voo

O~

Vpo

~

2 Voo

Operation without voltage doubler (status bit 1 = 0)
LF: loop filter

5-21

U1

i\,

J>

I

\lP

I\)

t

'D

"2-

I2C Bus

.---.

..........

±
'1 Hz

G

""

SDA SCL

Voo

-

o

:::I

!

l Modulat~r J

!

I
LD SID

SDA SCL

+

~

AF

--c::J---<

LD

T

SID

RI
GND2

TBB ZOO
FI

PO

MOD PRT

VCO

t--

GND1

RI
GND 2

ii'

...0'

TBB ZOO
FI

3

:D
III
Do

Voo

925,ZMHz
f----<~

=

'D

veo

PO

ci"
f--

'6"
3

PRT GND 1

LF

m
c

.Q

a

LF

III
:::I

-'-

~
GND

Do
:D
III
Do

....

34,3MHz
L..-

J

0"
~

Q1 MOD

~

IN
TBB 202

IN

Voo

!

H~

!!.

CD
'D
:::I'"

o

:::I

IX

V
•

S"
1.IF
10,7MHz

:F
CD
CD

011. <:Mi-I?

Receiving Frequency

"~MHz

o
o

iii:

Transmitting Frequency %
N

:D

CD
CO

g"

alai

mm
1\)1\)

00
00
G)

TBB200
TBB200G

Pulse Diagram
Phase Detector
I

I

jti-

RI

i I

(RI.

R)

---n

FI

nL-_. . .nL..-------InL-__

JuI

,

,

I

fv
(FI: N)

J

PChanne~1-._ _...1.1-.
~ ---..1-.- - - + - - - - ( P o l a r l t y Pos.)

Tristate

Status Bit 4 = H

N Channel

PO

J

PChann~e1-.- - . . . , . .

Tristate

~- ---+----IPolcrrity Neg)
1-.

Status Bit 4 =L

N Channel

LO

u

u

5-23

TBB200
TBB 200 G

The following requirements are made for the loop filter configuration:
a) the PLL should behave as a PT2 network,
b) an additional time constant should provide effective attenuation of the reference frequency
lines in the spectrum.
The network shown satisfies these requirements.
Loop filter

F(S) =

1 +S'2
sC 1 (1

+ ST2~)

(1 )

Fig. 1

According to Gardner /1/ this circuit corresponds to a PLL, type 2, 3rd order. A deeper
examination of this control circuit can be made in the Bode diagram (fig. 3).
Complete control circuit with corresponding frequency response of the open loop circuit

(2)

Fig. 2

K

5-24

C
= - -2+ 1
C1

TBB200
TBB 200 G

Bode diagram for the open loop control circuit, normalised to

WN

= 1

dB
-80
IFI -60

t

i"'-..

K- t---'

"- IFi

r- r-YK f-YK-

-40
-20

"-

~

o

il

I-"

40
60
80

--

--t-:
Cl)T!

20

Cl)REF

.......

a,

T--

--- - ""'- 'r"........

i--'

t

1""- -

'r;-

9',....... ~

100
10-2

(:)'t'2

Cl)N

Cl)K't'

9',=0

r

i'

~,

~

II

W

5

5

W

......
5

Degree
0
20
40
60
80
100 9'
120
140
160
180

~

102

Fig. 3

In this diagram a point WN is indicated where the true curve cuts the asymptotic amplitude
characteristic. Also the phase edge W, reaches its maximum exactly at this point. which
can be calculated from W N = ..;

(0'2

X

"!!2

X K'

(3)

In the region of this point the amplitude characteristic approaches a positive slope of
20 dB/dec. There is therefore the possibility of being able to describe the control circuit
with the PT2 parameter attenuation d and the self-resonant frequency w N• In order to obtain
the required phase. edge at the point WN' the ratio K of the time constants (see fig. 2)
is varied.
With regard to applications it is interesting to know after which period t a given tolerance
band B is entered but not left again for a step change in frequency. The step response
of a PT2 network is therefore analysed with d < 1.

5·25

TBB200
TBB200G

Transient Response

! !

\

I

\

f~

I \ ['...

H

....

28

/

I

.......
~

, [

h(t) =M

,.....

~

e-dwt '
+ ~

sin\ ~ wNt+ q;
I

)]

(4)

V

/IEnvel~pe
I I

II
II

I

!
I

!

i
fON

fOFF

___ t

Fig. 4

The computational formulae result from these observations. The chosen attenuation factor d,
the stabilization period TOFF and the tolerance band 8. The natural frequency (UN can be
calculated from these given parameters.

5·26

TBB200
TBB 200 G

-I n (8 -v'1-d2)'

(5)

dxT
A

WN

=tg (~+arc tan (2d))

(6)

..... REF

K

(7)

The relationship 7 can be simplified for the case wN«

If the parameters
be calculated.

~, Kvco

KvcoXK~

Cl

=

C2

=(K -1) C l

R2

WNX

NW N2X

y'J<1

";1{'
C2

W REF to

and N are known, the loop filter elements C l , C2 and R2 can

(8)
(9)

(10)

Application Example
The frequency range should be varied in steps of 25 kHz with half channel displacement.
The reference frequency is therefore set to fREF = 12.5 kHz. The IF bandwidth is 6 kHz.
For a change of channel, the oscillator frequency should have be so close to the final
frequency in the given time of 10 ms, that the channel can be evaluated. The tolerance
band is chosen as 114 of the IF bandwidth.

5-27

TBB200
TBB 200 G

B

1,5 kHz
25 kHz

0,06
= 1- (-1) =0318 rnA
41t
'
rad
rad
Kvco = 5,03 x 10 6 Vs

#Kq,

Phase detector constant

veo constant

'min

=900,0125MHz

Nmoo =

'moo

'max

= 900,9875 MHz
'max

= 72001

Nmax = -,-

'REF

= 72079

REF

The PLL should be designed for the average dividing factor N:

N

= ";NmaxX Nmon '= 72040

wN

=

A

=tan (_N_ +arc tan (2d))

K

= (A

C,

=

C2

=

R2

5-28

-In (BF-d2)'
dxToff

=4501/s

W

W REF

+1 A2 +

1')2

Kq, Kvco
N XW 2 X .y'I(1=34,8 nF
N

(K - 1) C, = 308 nF

-Ii('
wNx C2 =

22,6 kO

33 nF selected
300 nF selected
22.6 kO selected

TBB200
TBB 200 G

Explanation of Symbols:

PFD

Phase Frequency Detector

N

Divider ratio

'veo
KN

VCO frequency
Transfer coefficient of the divider

Kq,

Transfer coefficient of the PFD

Kveo

Transfer coefficient of the VCO

Td

Dead time

'REF

Reference frequency

Fa
K
B

Frequency response of the open loop control circuit
Ratio relationship of the time constants
Tolerance band

d

Setting time
Attenuation damping factor

wN
I

Output current of the PFD

TOIf

Natural frequency of the loop

Literature:

Gardner, Floyd: Charge-Pump Phase Locked Loops
IEEE Vol. COM-28, 11.80

5-29

ICs for Sensing Applications

SIEMENS

HKZ 101
Hall-Effect Vane Switch
The Hall-effect vane switch HKZ 101 is a contactless switch consisting of a monolithic integrated Hall-effect circuit and a special magnetic circuit hermetically sealed in a plastic package.
The switch is actuated by a shoft-iron vane which is passed through the air gap between
magnet and Hall sensor.
The main application field is in cars, i.e. as a breakerless trigger in electronic ignition systems.
Numerous industrial applications can be found in control engineering, especially in those
areas where switches must operate maintenance-free under harsh environmetal conditions
(e.g. rpm sensor, limit switch, position sensor, speed measurement, shaft encoder, scanning
of coding disks, etc.).
Features
•
•
•
•
•
•
•
•

Contactless switch with open collector output (40 mA)
Static switching
High switching frequency
Hermetically sealed with plastic
Unaffected by dirt, light, vibration
Large temperature and voltage range
Integrated overvoltage protection
High interference immunity

Special package

green black
rOJ
rOV)
-, Change to 130 H mm in prepllration

6-1

•

Function
The Hall-effect switch is actuated by a soft-iron vane that passes through the air gap between
magnet and Hall-effect sensor. The vane short-circuits the magnetic flux before the Hall-effect
sensor, as shown in figure 1. The open collector output is conductive (LOW) when the vane is
outside the air gap, and blocks (HIGH) when the vane is introduced into the air gap. The output
remains HIGH as long as the vane remains in the air gap. This static function does not require
a minimum operating frequency. The output signal shape is independent of the operating
frequency.
The Circllit features integrated overvoltage protection against most of the voltage peaks occurring in automotive and industrial applications. The output stage has a Schmitt trigger
characteristic. Most electronic circuits can be driven directly due to the open collector output
current of max. 40 mAo

Principle of operation

o

Hall IC

Fe Flux conductors

a) Magnetic flux through the
Hall-effect switch
with no vane
in the gap

Case

Magnet

Fe
Fe vane

==~~.

b) Magnetic flux
short-circuited by
the soft-iron
vane

Figure 1

Mechanical characteristics
The Hall-effect vane switch is hermetically sealed in a special plastic, so that it can also be used
under harsh environmental conditions. The package is waterproof, vibration-resistant and resistant to gasoline, oil and salt. Two tubular rivets are incorporated in the package to mount
the sensor on its carrier plate. The circuit has three flexible leads for power supply and output.
6-2

HKZ101

Application notes
The output current of the aopen collectorn must be limited to the maximum permissible
value by a load resistor adapted to the application.

For optimum efficiency of the integrated overvoltage protection, it is suggested that a resistor of approx. 100 Q be provided in the component's power supply to limit the current.

-.-----0 +vs

1

100n

red

40mA max.

green

Test conditions

Maximum ratings
Supply voltage

Vs

Lower
IimitB

Upper
limit A

-1.2

24
30
30
200

V
V
V
mA
mA
°C

Tamb -25°C

Va
-Is

Output voltage in OFF-state
Inverse supply current
(limited externally)
Output current
Inverse output current
Ambient temperature
during operation
Storage temperature

Ie
-Ia

Thermal resistance (system-air) ,

RthSA

-0.8
Tamb~80°C

mA

t~1

h
without vane

Tamb

-40

40
30
135

Tst9

-40

150

°C

170

K/W

130
24

V

Operating range
Ambient temperature
Supply voltage
Vane l ): thickness
width
gap length
immersion depth
gap height

Tamb
Vs
a
b
c
h
d

-40
4.5
0.5
8
8
4.6
17.3-h

9

°C
mm
mm
mm
mm
mm

1) see figure 3

6-3

HKZ101

Characteristics
Vs -5Vt018V;
Tamb --30 DC to 130 DC
Output saturation
voltage
Output reverse current
Supply current
Delay time
Overvoltage protection
- Supply voltage (Vs)
- Output (Va)

Test conditions

tLH. tHL

without vane
10 -40 mA
Tamb --30 to 110°C
Tamb -110 to 130°C
with vane
without vane
10 -40 mA

Vsz
Vso

I s -16mA
I s -16 mA

' Vasat

lOR

Is

Lower
IimltB

32
32

Upper
limit A

0.4
0.6
10
12
1

V
V
IlA

42
42

V
V

mA
Ils

Switching point characteristics
Definitions
In most applications, the switching point is' set exactly by mechanical adjustment, thus
compensating all mechanical tolerances in the system including the scatter of the Hall-effect
vane switch. For the function of the device in operation, only the deviations of those
characteristics depending on temperature and operating voltage are important.
The characteristic values of the switching points are, therefore. not directly referred to the
mechanical dimensions of the vane switch, but to an electrically defined symmetry 8 0
according to formula 1):
1) 8 0 ", (ONlell + OFFleII + ON'lght + OFFrlght): 4
8 0 ", Ao±O.3 mm
The definition of the operate and release pOints is shown in figure 2.
Operate point fON is obtained by subtracting the measured ON operate value from the
reference point 8 0 :

2) fON - ONrlght - 8 0 - 8 0 - ON'eII
The release point fOFF Is calculated from the difference between the appropriate ON and
OFF points:
'
3) fOFF '" ONrlght - OFFrlght - OFFleII - ONleII
fON 0 and fOFF 0 are the switching points measured for the individual component under
normal conditions (VS -12 V, Tamb - 25 DC) within the characteristic device deviation
The deviations of the operate and release points are defined according to 4):
4) .dfON-foN-foNO
.1fOFF '" fOFF - foFFo

6·4

HKZ101

Switching point definitions

I

/

o

Aa=Mechanical symmetry aXIs
6 0 =Electrical symmetry axis

Bo=Ao:!: O.3mm

--<---'--'L--

Va ,

I
I

:
:..
I
I
I
I

ONf r

right

off_

f on

~--------~4T~~--~----·f

o

_

fon

left

•f off
aNI 'OF",

i !:

: I:I:

p2222

i??2?i

Va+~
nUla

Va'

I

!a

l l ?2

• 1<---11
Bo

Figure 2

6-5

HKZ101

Mechanical measurement conditions
a) Measuring vane (material:soft iron)

b) Immersion depth
Fe vane

Fe vane

b-l-c
Figure 3

Switching point characteristics
Vane: a =0.75 mm. b=8 mm. c-10 mm
Position: center of air gap
Vs=5 Vto 18 V
Test conditions

HKZ101
Operate point
Deviations

.1fON

Release point
Deviations

fOFFO
.1foFF

6-6

fON~

Vs -12V. Tam b-25°C
Tamb - -30 to 25°C
Tamb - 25 to 80°C
Tamb -80 to 130°C
Vs -12V. Tam b-25°C
Tamb - -30 to 25°C
Tamb - 25 to 80°C
Tamb -80 to 130°C

Lower
IimitB

typ

Upper
limit A

0.85
-0.4
-0.2
-0.4
1.54
-0.8
-0.4
-0.8

1.45
+0.15
+0.15
+0.2
2.54
+0.3
+0.3
+0.4

2.05
+0.7
+0.4
+0.7
3.54
1.4
0.8
1.4

mm
mm
mm
mm
mm
mm
mm
mm

SIEMENS

SAS 231 W
Hall-Effect Ie with Output Voltage
Proportional to Magnetic Field
Pin Configuration
Os

Zero point
adjustment
SensItivIty
adjustment
0112-1

The IC SAS 231 generates an output voltage proportional to the magnetic flux density. The output voltage
increases when the south pole of a magnet approaches the top surface of the chip. The zero point is adjusted
by external components. The steepness of the characteristic curve Va as a function of B can be varied by
external components.

Absolute Maximum Ratings*
Supply Voltage (Vs) .................. ov to + 18V

'Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Output Current(la) ....................... 10 mA
Storage Temperature (Tstg) •.... - 40·C to + 125·C
Operating Range

Supply Voltage (Vs) ................. 4.75V to 15V
Output Current (Ia) ......................... 5 mA
AmbientTemperature (TA) ............ O·C to 70·C

Electrical Characteristics Vs = 10V, TA = 25·C, unless otherwise specified
Parameter

Symbol

Limits

Conditions
Min

Open-Loop Supply Current
Consumption

Is

RL =

Output Voltage

Va

RL=10kfl

Steepness
(without Adjustment)

S

"Zero" Component
Linearity Error

Bo

( Referred to Va =

00

Va = 0.5V

~s)

Temperature Coefficient

@Siemens Components, Inc.

a

TA = O·Cto +70·C

6-7

Max

6

10

mA

Vs - 2

V

140

mV/mT

35

mT

0.05
60

Units

Typ

100

-35
2

%

0.4

mT/k

April 1988

SAS 231 W
Application Circuit
1Io.,.3V
10 Sensi'lv.ty
k'1 adjust..on'

Output Characteristic without
Adjustment
v Output Voltage versus Flux Density

Vs

1

Output

Q

14
12

-Zero point

adJuslmonl

r !I
•
' j,

llcSl

10

lOkI)<1

'0;

,- roo- -

v.-

4

RL

2
0112-2

,

#-_

/'

/

L.
1/

0(L40
20
0

-

1/

V.

V

/
V, = lOY

--

V,=5V

- -160

10

r:~

~

100

120

140

160

110 liT

---.. Flux dlnsity B
0112-3

6-8

SIEMENS

TCA205A; K
Proximity Switch
This Ie is intended for applications in inductive proximity switches. The outputs switch when
the oscillation is damped, e.g. by the approach of a metal object.

Operation schematic
Oscillator not damped

Oscillator damped
~+---o Q

r+-t---o

Features
•
•
•
•
•
•

Large supply voltage range
High output current
Antivalent outputs
Adjustable switching distance
Adjustable hysteresis
Turn-on delay

6-9

Q

•

TCA20SA;K

Maximum ratings
Supply voltage
Output voltage
Output current
Junction temperature
Storage temperature range

Va
la
1j

Thermal resistance (system-air) TCA 205 A

Tstg

30
30
50
125
-55 to 125

V
V
mA
,oC
°C

R1hSA

,85

KIW

Vs

Operating range
Supply voltage
Ambient temperature

Vs

Characteristics
Vs -12 V; TA -25°C

. Test
conditions

Open-loop supply
current consumption
L output voltage per output
H .output current per output
Integrating capacitance
Internal resistance at 3
Threshold voltage at 3
Distance adjustment
circuit 1
Hysteresis adjustment
Distance adjustment }
circuit 2
Hysteresis adjustment
Turn-on delay
Oscillating frequency
Switching frequency without C,

J

Is
Val
Val
IaH
C,

Rhy

Rhy'" co
Rdl ... co

f8

1) Parallel connection of Rhy to Rdl may at least amount to 6 kC

6-10

10
350
1.3

Upper
limit A

2
1
1.5
10

kg

V

1.5
5

mS/I1F
MHz
kHz

200
0.015

mA
V
V
I1A
nF

660
1.5

6
0
61)
61)

fdon

fosc

typ

1
0.8
1.25

200

VS3
Rdl
R hy

Rdl

Lower
limitS

open pins
lal- 5mA
lal- 5OmA
VaH -30 V

R J3

I~C

14.75 to 30
-25 to 85

TA

kg
kg
kg
kg

TCA205A; K

Pin configurations
TCA205A

TCA205 K

Ground

14 Hysteresis

Distance 2

13 Oscillator

Integrating
3
capacitance

12 Oscillator

4

11 + Vs

Q output 5

10

Ground 6

a output

Ground

10

014 HysteresIs

Distance
Integrating
capac itance

20

013 Oscillator

30

012 Oscillator

0.

50

011 + Vs

Ground

60

9 Turn - on delay

7

o

9 Turn-on delay

07

B

a.

Block diagram
9 Turn-on delay

R

Delay

-.lL

~ontrul

I
12
OSC
13

Oscillator

-cP-

I

Rectifier

t---

--B*

Driver

Threshold
l-

f

t--P-

[>

r--f)

switch

7 Output a

5 Output

Q

~
TCA 205

1
2
Distance

14
Hysteresis

3 Integrating
capacitance

1,6 Ground

6·11

TCA205A;K

Schematic circuit diagrams
Oscillator

Tum-on delay
+ ---1>-------,

,---------- +

t--+---Q9
Demodulator
Output
transistors

Threshold
switch

13

12

14

2

Integrating capacitor

Outputs

Vs
+

R(

Demodulator---«:

5.7

Cj

R,3

6
3

6-12

TCA205A; K

Application circuit
with 1 coil as proximity switch __ _
with 2 coils as slot switch _ . _ . _ .

11
OSC1

12

7

5
9

6
Os

oscillator
distance adjustment
hysteresis adjustment
integrating capacitor
delay capacitor

The resistance of distance and hysteresis
may be applied as follows:

Rdi

and Rhy, for proximity switch TCA 205 A; K

1. Series hysteresis

2. Parallel hysteresis

2

2

TCA 205

14

TCA 205 14

Circuit 1 is more suitable for proximity switches with oscillator frequencies of f > 200 kHz
to 300 kHz, and small distances. Circuit 2 is more favorable for AF proximity switches having
larger distances. This is due to the lower Rhy values enabled by circuit 1 (min. 0 0) compared
with circuit 2 (min. 6 kO). Starting at frequencies of 200 kHz, high Rhy values effect in addition
to the hysteresis also the oscillator phase. Practical applications, however, require little phase
response to receive a clear evaluation.

6·13

TCA205A;K

Application example for a proximity switch
Coil data

pot core
865939-A-X22
coil former
865940-A-M1
o =25mmx8.9mm
L =6421J.H
n = 100 CuLS 30 x 0.05

Measuring plate

30 mm x 30 mm x 1 mm, Fe

Circuitry

~di = 56 to 200 kQ, metal layer
Rhy = 00

Co = 1500 pF, STYROFLEX
= 162 kHz

f

Switching distance versus
ambient temperature
13
~

12

off
_on

Rd,= 200krl -

10
9

-l-+i

-r

----t ---

I

I

!Rd,= 56krl
'

!

~:;:
on

:1--I-t-i-f
- - t-J
I __J ____ J _ !
L__

- 40

- 20

0

20

'40

60

-----TA

6-14

80 0 (

I

circuit 2

SIEMENS

TCA305A;G
TCA355 B; G
Proximity Switch
The devices TCA 305 and TCA 355 contain all the functions necessary to design inductive
proximity switches. By approaching a standard metal plate to the coil, the resonant circuit
is damped and the outputs are switched.
Operation schematic: see TCA 205
The types TCA 305 and TCA 355 have been developed from the type TCA 205 and are
outstanding for the following characteristics:
Lower open-loop current consumption; Is < 1 mA
Lower output saturation voltage
The temperature dependency of the switching distance is lower and the compensation
of the resonant circuit TC (temperature coefficient) is more easily possible.
The sensitivity is greater, so that larger switching distances are possible and coils of
inferior quality can be used.
The switching hysteresis remains constant as regards temperature, supply voltage and
switching distance.
The TCA 305 even functions without external integrating capacitance. With an external
capacitance (or with RC combination) good noise suppression can be achieved.
The outputs are temporarily short-circuit proof (approx. 10 s to 1 min depending on the
package)
The outputs are disabled when Vs < approx. 4.5 V and they are enabled when the
oscillator is working steadily (from Vs min =- 5 V)
Higher switching frequencies can be obtained.
Miniature packages

Logic functions
Oscillator
not damped
damped

Outputs

Q

Q

H
L

L
H

6-15

TCA305A;G
TCA355 B;'G

Pin configuration
TCA305A

TCA355B

14 HystereSIS

GNO

8 HysteresIs

2

13 OscIllator

'2 OSCIllator

Distance' 2
Integrating 3
Capacitanc/?

7 Oscillator

Integrating 3
Capacitance
4

11 Vs '

a output

Q Output

5

10 VREF

GND

6

a Output

7

9 Turn-on
Delay
8

GND
DIstance

TCA305G

4

5

Q

Output

TCA355G

GNO

HystereSIS

GNO

Distance

Oscillator

Distance

Integrating
Capacitance

Oscillator

Inte grating 3
Capacitance
11 Output, 4

4

+VS "

a olltput

5

VREF

GNO

6

Turn-on Delay

a Output

7

6·16

6 Vs

8 HysteresIs

2

7 Oscillator

6 Its
5 a Output

TCA305A;G
TCA355 B,G

Block diagram

r:z

I/:ontrol

r
Rectifier

Oscillator

OS ( 21

---.7""-

r--

-*

Threshold
0-

J

Driver

!--<

[>

~

switch

Output

a

Output

II

~
Delay

JI..

)

Diotance

Hysteresis

Integrating
capacitance

11

Turn-on delay

l

GND

1) TCA 305 only
2) Connected internally in case of TCA 355

6-17

TCA30SA
TCA30SG

Maximum ratings
Supply voltage
Output voltage
Output current
Distance. hysteresis resistance
Capacitances
Junction temperature
Storage temperature range

V
V
mA

Tslg

35
35
50
0
5
125
-55 to 125

RlhSA
RlhSA

85
140

KIW
KlW

Vs
fosc
TA

5to 30
0.015 to 1.5
-25 to 85

V
MHz
°C

Vs
Va

Ia
Rdio Rhy
C!. Cd

7j

Thermal resistance (system-air) TCA305 A
TCA305 G

0
J.LF
°C
°C

Operating range
Supply voltage
Oscillator frequency
Ambient temperature

Characteristics

Vs -12 V.

TA "'-25°C

Open-loop current consumption
Reference voltage
L output voltage
per output
H output current
per output
Threshold at 3
Hysteresis at 3
Turn-on delay
Switching frequency w/o C 1

6-18

Test
conditions

to 85°C
Is
V,ef
Val
VOL
VOL
IaH

outputs open
I,ef<10 IlA
·Iol -5mA
IOl -25 mA
IOl -50mA
VaH -30V

VS3
V\1y
fdon

fs

Lower
limitS

TA =25°C

typ
0.6
3.2
0.04
0.10
0.22

0.4
-25%

2.1
0.5
600

Upper
limit A
1.0
0.15
0.35
0.75
10

0.6
-25%
5

mA
V
V
V

'!
J.LA
V
V
mS/J.LF
kHz

TCA355 B
TCA355G

Maximum ratings
Supply voltage
Output voltage
Output current
Distance, hysteresis resistance
Junction temperature
Storage temperature range

Vs
Va

10
Rdl , Rhy

r;

T.1g

Thermal resistance (system-air) TCA 355 S
TCA355 G

R1hSA

R1hSA

35
35
50
0
125
-55 to 125

V
V
rnA
Q
°C
°C

135
200

KlW
KlW

5 to 30
0.015 to 1.5
-25 to 85

V
MHz
°C

Operating range
Supply voltage
Oscillator frequency
Ambient temperature

Characteristics
Vs =12 V; TA =-25

Vs
'ose
TA

Test
conditions

to 85°C

Open-loop current consumption
L output voltage
per output
H output reverse current
per output
Threshold at 3
Hysteresis at 3
Switching frequency w/o C 1

Lower
limitS

outputs open
IOl =5 rnA
IOl =25 rnA
IOl =50 rnA
VOH =30 V

Is
Val
Val
Val
IOH

0.6
0.04
0.10
0.22

VS3
0.4

Vhy

'.

Standard turn-on delay referred to

TA

typ

2.1
0.5

Upper
limit A
1.0
0.15
0.35
0.75
10

rnA
V
V
V
IJ.A

0.6
5

V
V
kHz

= 25°C

10
8
6

4

2

r----

1
0,8
0,6

-

r--

--

approx.1%/K

0,4

0,2

0,1
-30

-20

-10

0

10

20

30

40

50

60

70

-lA

80

°c
6-19

TCA305A,G
TCA355B,G

Schematic circuH diagrams
Oscillator

Tum-on delay for TeA 305

r---~~---'-----+

+--~~--------~

9

+---------------- Demodulator
Threshold
switch

Output
transistors

GND
13

12

14

2

llGND)

Integrating capacitor

Outputs

------~--------------~------.-----+

Demodulator

Rc

-----I:

5.7

approx. 1.8 V

I
3

6·20

(m'ernal

JJ

6

TCA305A,G
TCA355 B,G

Application circuits

VS

Vs

j~d

I11
7

12

TCA 305

13

Lo

1 14

[0

2

5

9

RhY
RI

0

Rd.

r[1

Q

Q

6

r

Vs

lis

Is
6

7

7

rCA 355
5

2

1

Lo

Q

3

8

CO
OS

.':+

Rd.
Rtoy

('I'"

6-21

TCA305AjG
TCA305BjG

Lo, Co

Resonant circuit

Rhy

Hysteresis adjustment

Rdl

Distance adjustment

D

Temperature compensation of the resonant circuit;
, possibly with series resistance for the purpose of adjustment.
The diode is not absolutely necessary.
Whether it is used or not depends on the temperature coefficient
of the resonant circuit.

R(; C(

Integration element

Cd

Delay capacitor

Dimensioning examples in accordance with CENELEC Standard (flush)

Ferrite pot core
Number of turns
Cross section of wire

Lo
Co

(STYROFLEX~)

fose

Sn
RA (Metal)
Cd

M 12

M 18

M30

M33 (7.35x3.6) mm
100
0.1 CuL
206IJH
1000 pF
appro 350 kHz
4mm
8.2 kO +330'0
100 nF

N22 (14.4x7.5) mm
80
20xO.05
268IJH
1.2 nF
appro 280 kHz
8mm
33kO
100nF

N22 (25x8.9) mm
100
10xO.1
585IJH
3.3 nF
appr.115 kHz
15mm
22 kO +2.7 kO
100nF

Note:

At pin 3 (integrating capacitance) we recommend a capacitor of typ.' 1 nF. To increase
noise immunity this capacitor can be substituted by an RC circuit with, e.g., R( =1. MO
and C(-10 nF.

6-22

SIEMENS
TFA 1001 W
Photodiode with Amplifier
The bipolar IC TFA 1001 W contains a photodiode and an amplifier. At its output (open NPN
collector). the TFA 1001 W supplies a current directly proportional to the illuminance. Another
pin permits a linearized characteristic curve at low illuminances and can be used to inhibit
the output.

Application
•
•
•
•
•
•
•

Exposure meters
Exposure control systems
Electronic flashes
Optical follow-up control
Smoke detectors
Linear optocouplers
Color identification

Features
•
•
•
•
•
•

High sensitivity
High output current linearity
Good spectral sensitivity
Low current consumption
Wide modulation range
Large operating voltage range

Pin configuration
Rad iant- sensi tive
area on the chip

TfA 1001 W
Frequency
1c===:::::::j
compensation
2
Adjustment.lnhibit 2 c===::::::J

3
-VsC:===~

/1=====:::1 V.tnb
5

~==:::::J + \IS
4
t===:::::J
Output

6·23

TFA1001 W

Maximum ratings
Supply voltage
Output current
Power dissipation
Junction'temperature
Storage temperature

Vs
IQ
Ptot
1j

Thermal resistance (system-air)

R1hSA

Tstg

Characteristics at Tamb = 25 DC,
supply voltage applied to pin 5
Supply voltage
Current consumption at Ev - 0 Ix
Ambient temperature (during operation)
Illuminance
Sensitivity in range
Ev = 1 Ix to 1000 Ix
Output current at
Ev =0.05Ix
Ev= 1 Ix
Ev = 1000 Ix
Ev = 5000 Ix
Stabilized voltage at pin 6
Supply voltage dependence of
stabilized voltage Vstab
Temperature dependence of
stabilized voltage Vstab

6-24

Lower
IimitB

Upper
IimitA -

-40

15
50
200
100
85

V
mA
mW
DC
-DC

250

K/W

Lower
IimitB

Vs
Is

typ

2.5
-10

Tamb '

Ev

0

S

2.5

IQ
IQ
IQ
IQ

2.5
2.5

Vstab

1.2

.dVsta~.dVs
.dVstab/.dTamb

5
0.25
5
5
25
1.35

Upper
limit A
15
1
70
5000

V
mA
DC
Ix

7.5

IJoAllx

7.5
7.5
1.5

IJoA
IJoA
mA
mA
V

2

mVN

-0.3

mV/oC

TFA1001W

Photocurrent versus illuminance

1a. 5

t

-- .

...

c--

,

I
5

LI

i

I

5

I
5

I
5

f:~t:~n~ .w~t~~~~ing~
Ij
h

"'" lex f~~~~I~le

5

10-1
10-2 .

5 10'1

5 10°

I

meQn~

ina

5 10 2

5 10 3

5 10 4 Ix

-Ev

6-25

TFA1001W

Possible applications of TFA 1001 W as Ii~htlcurrent transducer .

1) for operating voltage 2.5 to 15 V
+Vs
(2.5. 15 V)

TFA 1001 W

6

2

5

3

2) for low operating voltage 1.2 to 1.5 V
TFA 1001 W

6

s

2

+Vs
(1.2 1.5 V)

3

3) for especially low illuminance down to 0.01 Ix
+Vs
(2.5 ...15V)

TFA l00lW

R2

2

s

3

4 -Ie.

R, 10kQ 10MQ

In case of low illuminance (see characteristic: output current versus illuminance). the output
current can be balanced by means of the adjustment control R,. The lower range of the
output characteristic can be linearized even more by setting a dark current of about 5 nA.

6·26

TFA1001 W

Dynamic behavior

TFA 1001W

6
2

4

5 -10.

The dynamic behavior can be influenced at connection 2 by connecting capacitors.

dB
+10

".....

"'"

-5

[=10nF

-10
-15

.... f =0

.....

......... r-....~

':..... i'

A=f(f)

Ev=1Olx

r-.

'""
'""

r-.

-20
-25

5

5

10~

2 Hz

-f

Attenuation A =

10 (t)
10(f=0)

6-27

TFA1001 W

Inhibiting the output

s
6
2
3

4

The output can be inhibited by connecting the balancing input with the stabilized voltage
(switch, PNP transistor, FET).

6-28

TFA1001 W

Relative spectral sensitivity
versus wavelength
0/0

100

(

\

II
60

/
40

/

\

/
\

\
\
\

V

20

\

o
400

1000 nm

600

Output current
versus supply voltage

Relative output current
versus ambient temperature
in range Ev = 1 Ix to 1000 Ix

1.4

1.0
".. ~

:,..... ~

...... ".. I--'"

80

"..

60

0.8
40
0.6

20

o

o
-20

0

20

40

60

80

-TQmb

100

O(

o

2

4

6

8

10

n

~

~

V

-Vs
6·29

TFA1001 W

Application examples
Simple threshold switch with TAB 1453 A op amp

~

TfA ,00' W

Jf~~

2~~~

.:r.,u' T--.,
I

It,

1

1
I

i

1
The illustration shows a simple threshold switch as can, for example, be used in cameras to
change the aperture or indicate the iIIumillance. Operational amplifier TAB 1453 A serves as
comparator. It has a PNP input and is able to operate at very low supply voltage.
The output is an open collector which can switch currents up to 70 mAo
Since the stabilized voltage at pin 6 is used as reference voltage, the circuit is highly independent of the supply voltage.

6-30

TFA1001 W

Shutter speed or exposure control

Vs 12.5 .. 15 VI

1.35 V
TFA 1001 W

6
10MI'l
10kl'l

[

2
3

~

RL

5
5
4

The illustration above shows a light/time control which can, e.g. be used to control the shutter
speed in cameras or for exposure time control in enlargers. This circuit operates also largely
independently of the supply voltage. A further essential advantage is, that for the major part
of the exposure time the comparator input current is insignificant as the corresponding input
transistor remains fully off-state. By means of potentiometer P, the operating range can be
extended to lower illuminance values. Opening the switch starts the exposure, and capacitor C is charged from pin 4 of the photo IC. The comparator switches if the voltage Vc falls
below the reference voltage determined by resistors 'R1 and R2• The relationship between
illuminance and time is defined by capaC;:itor C and precision adjustment is possible by
means of V1; V1, however, must not become less than 0.4 V.

6-31

TFA1001 W

The dark current may be set in the circuit by means of potentiometer P. For this purpose,
capacitor C is removed. P is then adjusted in darkness'such that the output of the comparator
is just blocked. Capacitor C is then inserted. (See illustration below).

Comparator
output voltage

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-----------------~

Ang Ie of rota tion of P
Fi,nal setti ng

Schematic circuit diagram for an electronic flash control
1MQ
TFA 1001 W

6
Camp,
2

3

~

5

[

4
to flash
disconnection

TFA 1001 W can also be used for electronic flash control. It must, however, be ensured that
the illuminance does not exceed 5 klx; use a grey filter if necessary. To be able to control very
short times, it is useful to connect an additional capacitor to pin 1.
6-32

TFA1001 W

Combined aperture and exposure control

?.. Vs (2.5.

15V)
VREF 1.35 V

TFA 1001 W

6
2

3

~

Shutter
contact

R,

S
Shutter

4

R3
Aperture
switch

The aperture and exposure control may be combined, with the information for a:perture
switching being taken from the total current of the photo Ie (voltage drop at Rs).

Aperture follow-up control for cine cameras

r-------------------~----------_+--~+~
1.35V

TFA 1001W
1

2
3

R3

~

R,

5

4

The op amp compares the voltage drop at R3 , generated by the photoelectric current, with
a reference voltage derived from the stabilized voltage, and controls the aperture via motor M.
6-33

TFA1001 W

Ughtlfrequency transducer

+Vs
2.SV .8V

15nf

K2~ ~kQ[ )12kQ [ 1MQ

=

1)1kQ
lBC177

~

~-

25kQ[}

l~F
-r-

J. TFA1001W .§...

1~

2

~

.1

E1

]150Q

2- -

~

4

~

-"

2f'~AW76
+
6
TAB 1453 5
3_

5.6 [
kQ

)68Q[

II
Output

l~
~

V4

1kQ
1nF

==

1Pcl.

1kQ
76

Sensitivity: approx. 600 Hz/Ix
Ra,nge:
4 Hz to 400 000 Hz

High resolution
Fully temperature-compensated
Wide operating voltage range
High operating voltage suppression
Wide dynamic range (5 decades)

Particularly suitable for digital processing.

6-34

3.3kQ

II

f

~7BAW

•
•
•
•
•

2'~rF

------l

SIEMENS

TLE 4901 F, TLE 4901 K
Integrated Hall-Effect Switch
for Alternating Magnetic Fields
• Low Switching Thresholds with Good LongTerm Stability

• Extended Temperature Range
-40°C to + 135°C

• High Interference Immunity

• Insensitive to Mechanical Stress

• Overvoltage Protection

• Flat Plastic Package (1.5 mm) or Micropack

Pin Configurations

Pin Definitions

TLE4901 F

TLE4901 F

f-~
--

~f

0-

Pin

Symbol

Function

1

2
3

+Vs
Os
Q

Supply Voltage
Ground
Output

Pin

Symbol

Function

+Vs
Q

Supply Voltage
Output
Ground

3_

~=t10. ~
'+V.

Q

0085-1

TLE4901 K

~,

Q~
2

Cl

lin
,"""

Q-t ~i~
"
"

r

TLE4901 K

S

1

2
3

3
po.

Os

v,
tl·
1

.,

0085-10

Dimensions in mm

The Hall-effect IC TLE 4901 is a static contactless switch operated by an alternating magnetic field. The output
is switched to the conducting state by the south pole of the magnetic field and blocked by its north pole.
The IC is provided with an integrated overvoltage protection against most of the transients occuring in automotive and industrial applications.
The IC is particularly intended as an rpm sensor or an angle indicator. Multiple pole ring magnets are especially suited to switching the !C.

©Siemens Components, Inc.

6-35

April 1988

TLE 4901 F, TLE 4901 K

Block Diagram

0085-2 (

Circuit Description
The circuit includes a Hall generator, amplifier and a
Schmitt trigger. The supply and the output terminals
have protection circuits with Z characteristics to prevent overvoltage.
A magnetic field perpendicular to the chip surface
induces a voltage at the sensor contacts of the integrated Hall generator. This voltage is amplified,
Schmitt triggered, and used to control an NPN transistor with a collector output. The output-stage transistor conducts when the applied flux density exceeds the switching level. If the flux density is reduced by the hysteresis flux density, the output
stops conducting.
To minimize the effects of supply voltage and temperature variations on the switching level, the Hall
sensor is supplied by a stabilized current source,
which is in turn derived from a reference voltage.

Functional Description
When a magnetic field is applied in the direction
shown, and the turn-on flux density is exceeded, the
IC's output conducts. Reversal of the current direction in the electromagnet (i.e., reversal of the magnetic field) and falling below the turn-off flux density,
leaves the output non-conducting.

6-36

• Vs ...
0085-3

Switching Characteristics

f I'=--~H--­

~=~+~st:7=Magl1lhC

;'\ -u-

Flu. DonSlty

I

OUtput Voltage

-,
0085-4

TLE 4901 F, TLE 4901 K

Supply Voltage (Vs) ................ -1.2V to 30V

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Output Voltage
Output Off-State (Va) ..................... 30V

Operating Range

Absolute Maximum Ratings·
TA = -40°C to + 135°C

Output Current
Output On-State (10) .................... 40 mA

Supply Voltage (Vs) .................. 4.5V to 30V

Flux Density Range (B) ................ unlimited T

Notes:

Junction Temperature
t < 70,000h (Tj) ................•....... 150°C

1. Thermal resistance of TlE 4901 K depends on type of
mounting.
2. An optimal reliability and lifetime of the IC are assured as
long as the junction temperature does not exceed 125·C.
Though operation of the IC at the given max. junction temperature of 150·C is possible, a continuous operation at this
rating could nevertheless impair the reliability of the Ie considerably.

Ambient Temperature (TA) ...... - 40°C to + 135°C

Storage Temperature
t < 70,000h (Tstg) ........... - 55°C to + 150°C
Thermal Resistance
System-Air (Rth SA) ................. 250 k/W(l)
Overvoltage Umits
Current through Protection
Devices (Iz) t < 2 ms .... - 200 mA to + 200 mA

Characteristics Vs = 6V to 16V; TA =
Parameter

Symbol

- 30·C to + 125°C

Measurement
Circuit

Limits
Min

Supply Current
B::; BOFF
B;;,: BON

Is

Flux Density for "ON"
TA = 25·C

BON

2

Flux Density for "OFF"
TA = 25°C

BOFF

2

Flux Density for "ON"
TA = -25°C to +85°C

BON

2

Flux Density for "OFF"
TA = -25·Cto +85°C

BOFF

2

Hysteresis
TA = ":'25°Cto +85°C

BH

2

Flux Density for "ON"

BON

2

Flux Density for "OFF"

BOFF

2

-15

Hysteresis

BH

2

2

Output Leakage Current
B::; BOFF

10H

2

Output Voltage
10l = 16 mA, B ;;,: BON

Val

2

tHl
tlH

1
1

Transition Times of Output
Fall Time
Rise Time

2
2

Typ

2
3

Units
Max
8
13

mA
mA

10

mT

-10

mT
12

mT

,

-12
3

mT
14

mT

15

mT
mT

0.3
0.5

15

mT

10

/LA

0.4

V

1
1

/Ls
/Ls

Note:
The listed characteristics are ensured over the operating range of the IC when using the supply voltage and ambient temperature stated. Typical characteristics specify mean values expected over the production spread.

6-37

TLE 4901 F, TLE 4901,,!<

Measurement Circuits
Vs'

Pulse Diagrams
Q

Flux Density

Va.

L

B> BON

B

B

< BOFF

H

The characteristics include the following extreme
cases:

Harlong
SIde
0085-5

BON = BON max

B~
.~+-

t

,Figure 1

Be.

-

. ----iur-

tOI

...

Output Voltage

_t

....-.
Figure 2

0085-8

, BOFF = BOFF min
B

to

Application Circuit

!A I

1Io.,......-n-'--~rl-~-

~~;Z~v=:'~l'~"agnehc Flux DInsoty

I'Baf. I

f,--_l__'

II!

R,

r

_'_outPUtVOltoge

HarkIng

_I

t'----'.Vs

Sode

0085-9
0085-7

For optimum protection against destruction, Rs is required to be as high as possible.

Ordering Information
Type

Dimensioning:

R - VSXmin-VSmin

s-

IS max

VSX min is the minimum supply voltage in each appli-

cation.

6-38

Ordering Code

Package

TLE 4901 F Q67000~A2518 Plastic Flatpack
TLE4901 K Q67000-A2399 MIKROPACK (SMD)

SIEMENS

TLE 4902 F
Integrated Hall-Effect Switch
for Alternating Magnetic Fields
• Low Switching Threshold With Good
Long-Term Stability

• Suited To Low-Cost Applications. e.g.
Electronic Commutation of Electric Motors

• Extended Temperature Range
-40·C to +125·C

• Insensitive to Mechanical Stress

• Flat Plastic Package (1.5 mm)

Pin Configuration

Pin Definitions

~gf-'"

~

,l;

--

3_ _

Pin

Symbol

Function

1

+Vs
Os
Q

Supply Voltage
Ground
Open Collector Output

2
3

I

~=i1
~
+v.o.a
0086-1

The Hall-Effect IC TLE 4902 F is a static contactless switch operated by an alternating magnetic field. The
output is switched to the conducting state by the south pole of a magnetic field and is blocked by its north pole.
The IC is especially suited to applications as an rpm sensor or an angle indicator.

@Siemens Components. Inc.

6-39

April 1988

TLE 4902 F

Circuit Description

Functional Description

The circuit includes a Hall generator, amplifier, a
Schmitt trigger and an open collector output.

When a magnetic field is applied in the direction
shown, and the turn-on flux density is exceeded, the
IC's output conducts.

A magnetic field perpendicular to the chip surface
induces a voltage at the sensor contacts of the integrated Hall generator. This voltage is amplified,
Schmitt triggered, and used to control an NPN transistor with a collector output. The output-stage transistor conducts when the applied flux density exceeds the switching level. If the flux density is reduced by the hysteresis flux density, the output
stops conducting.

Reversal of the current direction in the electromagnet (i.e. reversal of the magnetic field) and falling
below the turn-off flux density, leaves the output
non-conducting.

Block Diagram

r---_--___1-----.vs
Output

.

Q

~

,s

ooee-3

Switching Characteristics
8

ooee-2

t~

!AI
Hagnehc Flux OlnSlty

's"" /

~I

"-./

liT

--u-

Output Voltage

_t
0088-4

6-40

TLE 4902 F

Absolute Maximum Ratings·
TA = -40·C to

+ 125·C

Supply Voltage (Vs) ............... -0.5V to

+ 7V

Output Voltage (Va)
Output Off-State .......................... 30V
Output Current (10)
Output On-State ....................... 20 mA

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Magnetic Flux Density Range (B) ....... Unlimited T

Operating Range

Junction Temperature (TJ)
t < 70,000h ...................•........ 150·C

Ambient Temperature (TA) ...... - 40·C to

Storage Temperature (Tstg)
t < 70,000h ................ -40·C to

+ 150·C

Thermal Resistance (Rth SA)
System-Air .......................... 240 k/W

Supply Voltage (Vs) .................. 4.5V to 6.8V

+ 125·C

Notes:
Maximum Ratings-Maximum ratings are absolute rated
values; exceeding only one value may destroy the IC.
Operating Rang_Within the functional range, the integrated circuit operates as described; deviations from the
characteristic data are possible.

Characteristics
TA

=

O°C to 85°C; Vs

=

4.5V to 5.5V (unless otherwise specified)

Parameter

Symbol

Measurement
Circuit

Limits
Min

Flux Density for "ON"
TA = 25°C

BON

2

Flux Density for "OFF"
TA = 25°C

BOFF

2

Flux Density for "ON"

BON

2

Flux Density for "OFF"

BOFF

2

-15

Hysteresis

BH

2

3

Flux Density for "ON"
TA = -40·Cto + 125°C
Vs = 4.5V to 6.8V

BON

2

Flux Density for "OFF"
TA = -40·C to + 125°C
Vs = 4.5V to 6.8V

BOFF

Hysteresis
TA = -40°C to + 125°C
Vs = 4.5V to 6.8V

BH

Output Current
B S; BOFF

laH

2

Output Voltage
laL = 16mA; B ~ BON

VOL

2

Typ

Units
Max
10

mT
mT

10
15

mT
mT

14

mT

20

mT

2
-20

mT

2
2

15

mT

10

p,A

0.4

V

6-41

TLE 4902 F

Characteristics (Continued)
T A = O·C to 85·C; Vs = 4.5V to 5.5V (unless otherwise specified)
Symbol

Parameter
Transition Times of O~tput
Fall Time
Rise Time

LImits

Measurement
Circuit

tHL
tLH

1
1

Is
Is

2
2

Min

Units

Typ

Max

0.3
0.5

1
1

p.s
p.s

5.5
6.5

mA
mA

Supply Current

B S; BOFF
B ~ BON

2
3

Note:
The listed characteristics are ensured over the operating range of the Ie when using the supply voltage and ambient tempera·
ture stated. Typical characteristics specify mean values expected over the production spread.

Measurement Circuits
.vs

Pulse Diagrams

s.SV

8

Flux Density

Q

B> BON

L

B < BOFF

H

The characteristics include the following extreme
cases:
0088-5

BON

= BONmax

t'~MagnthC
o

Figure 1

FlullDensit,

Of

II

. ---i
'ut -

tAl
~+--'---""'Output

Output Voltage

_I
0088-8

0086-6

Figure 2

BOFF = BOFF min
8

tOhrlla~·c:Jt:=~~/:::
1,/\
I'
'8aFf I
r

. Application Circuit
- p - - - p - -..... vs

A

'Il L

!.----,M----'l~-

1\

Q

0086-7

u-

Hagnlhc Flux D....ty

Output Voltage

_I

......

Ordering Information

6-42

Ordering Code

Package

Q67000·A8048

Plastic Flatpack

SIEMENS

TLE 4903 F
Integr~ted

Hall-Effect Switch
for Unipolar Magnetic Fields
• Low Switching Thresholds with Good LongTerm Stability

• Extended Temperature Range
- 40·C to + 130·C

• High Interference Immunity

• Insensitive to Mechanical Stress

• Overvoltage Protection

• Flat Plastic Package (1.5 mm)

Pin Configuration

Pin Definitions

f~~
-

~f

Pin

Symbol

Function

1

+Vs
Os
Q

Supply Voltage
Ground
Open Collector Output

2
3

~

3_

~11~
+v.o.

Q

Dimensions in mm

0084-8

The integrated Hall IC TLE 4903 F is a contactless switch operated by a magnetic field. On reaching the turnon flux density of the south-pole of a magnetic field, the output conducts. As the flux density strength sinks
below the turn-off level, the output stops conducting. The IC is provided with an integrated overvoltage
protection against most of the transients occurring in automotive and industrial applications.

@Siemens Components, Inc.

6-43

April 1988

TLE 4903 F

Block Diagram

O._. . .- . . .-----.. . -----___. . .

_....J

Circuit Description
The circuit includes a Hall generator, amplifier,
Schmitt trigger and an open collector output. The
supply and the output terminals have protection circuits to prevent overvoltage.
'
A magnetic field perpendicular to the chip surface
induces a voltage at the sensor contacts of the integrated Hall generator. This voltage is amplified,
Schmitt triggered and used to control an NPN transistor with a collector output. The output-stage transistor conducts when the applied flux density exceeds the switching level. If the flux density is reduced by the hysteresis flux density, the output
stops conducting.
To minimize the effects of supply voltage and temperature variations on the Switching level, the Hall
sensor is supplied by a stabilized current source,
which is in turn derived from a reference voltage.

Functional Description
When a magnetic field is applied in the direction
shown, and the turn-on flux density is exceeded, the
Ie's output conducts. Reduction .of the current and
falling below the turn-off flux density, leaves the output non-conducting.

6-44

• Vs 0084-2

SWitching Characteristics

f t;;~::;;¢:s;;:::::::::;=

Magnllic Flux Dnity

II:tQL_

Output Voltage

_

-t
0084-3

TLE 4903 F

Absolute Maximum Ratings'"
TA = -40·C to + 130·C
Supply Voltage (Vs) ................ -1.2V to 30V
Output Current (Ia) ....................... 40 mA
Junction Temperature
t < 70,OOOh (Tj) ............. - 40·C to + 150·C

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Storage Temperature (Tstg) ..... - 55·C to + 125·C
Thermal Resistance
System-Air (Rth SA) ................... 240 k/W
Flux Density Range (B) .............. - co to + co

Operating Range
Supply Voltage (Vs) .................. 4.3V to 24V

Output Voltage (Va) ......................... 30V
Overvoltage LImits
Current through Protection
Devices at Pins 1
and 3, t < 10 ~s ......... -200 mA to +200 mA

Characteristics

Vs

Ambient Temperature (TA) ...... -40·C to + 130·C
Note:
An optimal reliability and lifetime of the IC are assured as
long as the junction temperature does not exceed 12S·C.
Though operation of the IC at the given max. junction temperature of 1SO"C is possible, a continuous operation at this
rating could nevertheless impair the reliability of the IC considerably.

= 14V; TA = 25·C

Parameter

Symbol

Conditions

Test
Circuit

Min

limits

2

20
18
18
12

50
52
57
58

mT"
mT
mT
mT

2

15
19
8
7

35
34
42
43

mT
mT
mT
mT

2

5

15

mT

10

~A

Typ

Units
Max

Magnetic Parameters·
Flux Density "ON"

BON

TA
TA
TA
TA

= 25·C
= O·Cto +70·C

= -30·C to + 100·C
= -30·C to + 125·C
TA = 25·C
TA = O·Cto +70·C
TA = -30·C to + 100·C
TA = -30·C to + 125·C

Flux Density "OFF"

BOFF'

Hysteresis
(BON - BOFF)

BH

Output Junction Current

lao

B < BOFF; VOH
TA = 25·C

Supply Current

Is

B < BON
B> BOFF

1
1

13
14

mA
mA

Output Voltage

Va

la

2

0.4

V

Rise Time

tLH

1

~s

Fall Time

tHL

= 30mA
la = 10mA
la = 10mA

1

~s

Supply Voltage

Vsz

Is

32

42

V

Output

Vaz

32

42

V

~

= 24V

Overvoltage LImit

= 16mA
laz = 16mA

Notes:
'The magnetic parameters are specified for a homogenous magnetic field at the sensor center as per Figure 3.

"1 mT = 10G
The listed characteristics are ensured over the operating range of the IC when using the supply voltage and ambient temperature stated. Typical characteristics specify mean values expected over the production spread,

6-45

TLE4903 F

Measurement Circuits

B

l1arl<'ng
SOlie
0084-5
0084-4

Figure 2

Figure 1

For optimum protection against destruction, Rs is required to be as high as possible.

Application Circuit

Dimensioning:

R

= VSXmin - VSmin

s

IS max

VSX min is the minimum supply voltage in each appli-

~-+-"""--oVQ

cation.
0084-6

Ordering Information

Pulse Diagram

f~
I

!

I
i

I
i

~f

rtL,kL·

_t
0084-7

6-46

Ordering Code

Package

Q67000-AB047

Plastic Flatpack

SIEMENS

TLE 4910 K
Bipolar Hall-Effect

Ie with Analog Output

Pin Configurations

Pin Definitions
Pin

(Top View)

1
2
3
4
5
6
7
8
9

Function

Vs
Vref
Ground
Zero Adj., + Vadj
Zero Adj., - Vadj
Sensitivity adj.
Vprobe
Vtemp

Vo

0083-7

The Ie TLE 4910 K generates an output voltage proportional to the magnetic flux density.
The Ie is made northpole or southpole active by adjusting the zero point. The zero point of the transfer
characteristics and the sensitivity of the device is adjusted with external components (Figure 4). The -Ie is
suited as sensor for professional applications requiring enhanced temperature and improved data ranges e.g.,
measurement of pressure, acceleration, distance and torsion.

@Siemens Components, Inc.

6-47

April 1988

TLE 4910 K

Absolute Maximum Ratings·
Maximum Ratings are absolute limits. The integrated circuit may
ed.

Parameter

pe destroyed if only a single value is exceedLimits

Symbol

Units

Typ

Min
-40

Max
+150

·C

Ambient Temperature

TA

Supply Voltage

Vs

30

V

Output Current

10

10

mA

Junction Temperature

TJ

+125

·C

-40

Storage Temperature

Ts'

Thermal Resistance (Junction-Air)

RthJA

Induction

B

-00

+00

ladi

-1

+1

Zero Adjustment Current

+125

·C

Mounting Dependent
mA

·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Reliability and lifetime of the IC is assured as long as the junction temperature does not exceed 125·C, though
operation of the IC at the given maximum junction temperature of 150"C is possible. Nevertheless, a continuous operation at this rating could impair the reliability of the IC considerably.

Block Diagram

+Vs

-- Amp

./

~

Output stage

lm
SensItiVIty adjustment
0083-1

Functional Description
The IC TLE 4910 K can be operated at supply voltages between 4.75V to 18V. It's output signal is a
voltage with reference to ground which can supply
up to 5 mAo
As shown in the block diagram the Hallsensor is fed
with regulated current from an internal current con-

6-48

troller. The output signal of the Hallsensor is first
amplified in a differential amplifier to a suffiCiently
high level and,then converted into a grounded signal.
The endstage comprises of an operational amplifier
with internal feedback whose inverting input is led
out and can be used for tuning the sensitivity of the
'device.

TLE 4910 K

Functional Range
The functions stated in the circuit description are fulfilled within the range of the operating data.

Parameter

Symbol

Supply Voltage

Vs

Output Current

10

Ambient Temperature

Limits

Conditions

TA

Units

Min

Max

4.7S

18

V

S

rnA

-40

13S

DC

Electrical Characteristics
The electrical characteristics include the guaranteed tolerances of the values maintained by an IC for the
specified operating range.
Vs = 4.7SV to 1SV; TA = - 2SDC to + 12SoC unless otherwise specified.

Parameter

Symbol

Conditions

Limits

Figure
Min

Supply Current

Is

B<-20mT

1

Output Voltage Range

Vo

RL = 10k
Vs = SV

1

Sensitivity

S.

O.OS

1

Magnetic Offset

Bo

Linearity Error

L

1

Temperature Coefficient
of the Magnetic Offset

ocBO

Temperature Coefficient
of the Sensitivity

ocs

Reference Voltage

Vref

TA

Output Voltage/Adjustment
Current (Pin 4)

VO/ladj

Output Voltagel Adjustment
Current (Pin S)
Voltage at Pin 4 and Pin S

Typ

-20
1

1

2SoC

1

TA

2SDC

2

VO/ladj

TA

=

2SoC

2

10

rnA

Vs - 2

V

30

B = 0 mT to 100 mT

=
=

Units
Max

2.9

mV/mT
+20

mT

2

%

±0.03

mT/k

±O.S

%/k

30

3.1

V

+0.3

V//J-A

-0.3

V//J-A

.-

Vadj

TA = 2SDC

Temperature Voltage

Vtemp

Vs
TA

Temperature Coefficient
of the Vtemp

OCVtemp

Output Impedance

Ro

SV, R
2SoC

Vs

=
=
=

Vs

=

SV

2

=

S.1 L

R = S.1k

3
3

10 < SmA
Sensitivity Change Due
to VS Changes

ASI/)"vs

TA = 2SoC

1

Magnetic Offset Change
Due to Vs Changes

ABo/AVs

TA

2SDC

1

=

30

110

mV

1.4

1.7

V

+3.S

4.S

mV/k

10

.n

0.2

%IV

20

/J-TIV

70

6-49

TLE 4910 K

Test Circuits

'5

+

+vs

f

v,.,
9

0083-'

0083-3

Figure 1

Figure 2

0083-4

Figure 3

Application Circuits

10k

l

vo
0083-5

Ie without adjustment

(a)

(b)
Zero adjustment

Figure 4

6-50

Sensitivity adjustment

TLE 4910 K

Functional Diagram
Transfer Characteristics

VA

t

"/ .
: ~l,:'.:·i
. );f;, ....... ,'

"

,~

,

Sensitivity adjust.

.........

.: ....

"

,'
. ,

I

100

_B

Zero adjust.
0083-6

FigureS

Ordering Information
Type

Ordering Code

TLE4910 K

Q67000-A 2398

6-51

les for Video Applications

SIEMENS

SOA 2112-2
TV PLL for 125 kHz Resolution
The SOA 2112-2 is fabricated in ASBC technology. In connection with a VCO (tuner) and
a high-speed 1 :64 divider, it forms a digitally programmable phase-locked loop for TV sets
designed. to use the PLL frequency sythesis tuning principle. The PLL enables crystalcontrolled setting of the tuner oscillator frequency for a 125 kHz resolution in the frequency
bands lIlli, IV, and V.
A serial interface provides for simple connection to a microprocessor. The latter loads the
programmable divider and the band-selection outputs with the appropriate information.

Features

•
•
•

No external integrator necessary
Internal buffer
Microprocessor compatible

•

7-1

SDA2112-2

Maximum ratings
Supply voltage
pin 18

I -0.3 to 7.5

VS1

Inputs

01,02, F, F
pin 1, 2, 15, 16
CPl, IFO, PlE
pin 7, 8,10

Iv
+ 0.2

V

VI

-0.3 to VS1

VI

-0.3 to 5.5

V

Va

-0.3 to 16

V

V6

-0.3 to
3
-0.3 to
3
-0.3 to
1
-0.3 to
-0.3 to
8
140

V
rnA
V
rnA
V
rnA
V
V
rnA
°C
°C

Outputs

UHF, VHF, Bd 1/111
pin 3, 4, 5
ClK (pin 6)

16

lDM (pin 17)

V17
117

lOCK INO (pin 12)
PD (pin 14)
Vo (pin 11)
OSC (pin 13)

V12
114

V11
V13
1 13

16
7.5

VS1 +0.2
33
VS1

Junction temperature
Storage temperature range

7;
T.1Q

-40 to 125

Thermal resistance (system-air)

RthSA

80

+ 0.2

K/W

Operating range
Supply voltage range
Input frequency
Divider factor
Crystal frequency
Tuning voltage
Ambient temperature

7-2

VS1
fF.F
N
fa
Vo

TA

4.5 to 7.15
16
256t08191
3
0.3 to 33
Oto 70

V
MHz
MHz
V
°C

SDA2112-2

Characteristics
VS1 =5V; TA=25°C
Test
circuit
Supply current, pin 18
Oscillator output, pin 13
RL2 =3.5 kQ
OSC
RL2=3.5 kQ
Signal inputs F/F, pin 15, 16
Input voltage
Input current
V15 =5 V ,
Input sensitivity (peak-to-peak)
Sine push-pull f = 16 MHz
Bus inputs CPl, IFO, PlE, pin 7,8,10
Upper threshold voltage
Lower threshold voltage
Hysteresis
H input current
V7H =5 V
L input current
V7l =0.4 V
Band selection outputs UHF, VHF, Bd 11111
pins 3, 4, 5
Reverse current
V3H =15 V
Forward current (current drain)

IS1
V13H

4

V13L

4

V15H
V15L
115

1
1
1

V15,1S

I min

typ

max

20

35

mA
V

0.7

V

4.1
3.8

VS1+0.2
Vs1 -O.1
50

V
V
ILA

300

1200

mV

1.6
1.0

V
V
V
ILA

4.5

V7u
V7I
L1V7
I7H

2
2
2
2

1.0
0.5

I7l

2

-50

I3H

3

I3L

3

0.8

VS H

4

14

VSL

4

V11

5

0.3

1,4

5

-150

114

5

-450

1.3
0.7
0.6

8

ILA

10

ILA

1.7

mA

•

2V~ V3~15V

Clock output ClK, pin 6
H output voltage
VS3=15 V
L output voltage
RL1 =6.8 kQ
Tuning section VD, PO, pins 11, 14
Tuning voltage
Vs2 =33V
Charge-pump current
PLLlocked
PLL unlocked

V
1.5

V

32.5

V

±100

150

!LA

±300

450

!LA

7-3

SDA2112-2

Characteristics (cant'd)
VS1 =15 V; TA =25°C
Test
circuit

min

S
S

2.8

typ

max

Lock indication, pin 12
H output voltage
L output voltage

V12H
V12 L

0.4

V
V

117

10

~A

V17 L

0.4

V

Carry synchronous divider LDM
Pin 17 (open collector)
Reverse current
V17H =SV
L output voltage
RL =S kQ

Switching times
IFO, PLE
Set-up time
Hold time
ClK
H pulse width
L pulse width
Hl transition time
RL1 =6.8 kQ
LH transition time
Cu=SOpF
CPL
H pulse width
L pulse width
OSC
H pulse width
L pulse width
Hl transition time
RL2 =3.S kQ
LH transition time
C L2 =8 pF

7·4

ts
tH
tTH
tTL
tTHL

2
2

4
4
4

tTLH

2
2

~s

~s
~s

0

1.S

~s

133

tOHL

4
4
4

tOLH

4

tOH
tOL

8.0
8.0

~s

O.S

2
2

tCLH

~s

0

2
2

tCH

1.S
1.S

1.S
1.S

~s
~s

200
20

ns
ns
ns

SO

ns

SDA2112-2

Circuit description (refer to block diagram)

F,

F

lDM
IFO
CPl
PlE

A switchable 16/17 counter is triggered by the ECl signal inputs F/F. The counter,
in connection with a 4-bit and a 9-bit programmable, synchronous counter, forms
a programmable, 13-bit synchronous divider using the dual-modulus technique,
the 4-bit counter contrOlling the switchover from 16 to 17. Divider ratios of
N = 256 to 8191 are possible. For test purposes the carry of the synchronous
divider is available at the lDM output (open collector).
The 16-bit shift register and latch is subdivided into 13 bits for storing the divider
ratio Nand 3 bits for controlling the three band-selection outputs.
The telegram is shifted in via the serial data input IFO with the Hl edge of the
shift clock CPl when the enable input PlE is also on high level. First the com"plement
of the divider ratio N, beginning with the lSB, is inserted in binary code, followed
by the three control bits for the band-selection switching (see truth table). The 16-bit
latch takes the data from the shift register when the enable input PlE is on low
level.

01,02 The IC includes a crystal-controlled, 3-MHz clock oscillator. The output signal is
divided down to 1.953125 kHz (reference signal) by a 111536 reference divider.
OSC
The oscillator frequency appears at the TTL output OSC.
ClK

The clock of 62.5 kHz is available at the open-collector output ClK.

PD

The divided input signal is compared with the reference signal in a digital phase
detector. If the falling edge of the input signal appears prior to the falling edge
of the reference signal, the DOWN output of the phase detector turns to high
level for the duration of this phase difference. In the reverse case the UP output turns
to high level. If the two signals are in phase, both outputs remain at low level.
The UP/DOWN outputs control the two current sources 1+ und 1- (charge pump).
If the two outputs are low (Pll locked), the charge-pump output PD will turn to
the high-impedance state (TRISTATE).

lOCK
IND

An l signal appears at the lOCK IND output if frequency and phase are
synchronous. The current sourcesI+ and 1- are then reduced from 3,00 to 100 iJ.A.

Vo

The current pulses generated by the charge pump are integrated to form the
tuning voltage by means of an active lowpass filter (external pull-up resistor to
supply VS2 and external RC circuitry). The dc output signal appears at lio and
serves as a tuning voltage for the VCO.
The band-selection outputs (UHF, VHF, Bd 1/111) contain current drains with open
collectors. In this way PNP transistors working as band-selection switches can be
connected directly without current-limiting resistors (see application circuit).

UHF
VHF
Bd 1/111

7-5

SDA2112-2

Pin description
Pin

1
2
3
4

5
6
7
8
9

10
11
12
13
14
15
16

Symbol

Function

02
01

Crystal
Crystal

UHF
VHF
Bd 1/111
ClK
CPl
IFO
GND
PlE

Vo
lOCK IND
OSC
VPD

F

17

F
lDM

18

Vs ,

7-6

'} Band selection outputs
Clock output
Clock input
Data input
Ground
Shift register enable input
Tuning voltage
lock indication output
Oscillator output '
Phase detector voltage
Inverted input
Input
Carry
Supply voltage

SDA2112-2

Block diagram

Vs,

GNO

625kHz

OSC
Q1

LOCKINO

PO

Q2

[,

.

I

Vo

c

F

Gl

rn

Tuning
Voltage

f

16-Blt SR + Memory'

~

VHF

UHF

BdI/III

Interface to IlP

7-7

SDA2112-2

Computation for loop filter
Loop bandwidth: wR

P

=J

.. Prescaler

N
Ip
'Kvco
R, C,

Ip x Kvco
C, xPxN

Attenuation: ( = 0.5 X w R x R X C,

= Programmable divider

... Pump current
= Tuner slope
... Loop filter

Example for channel 47:

P=64;
N=5760;
Ip=100IlA;
Kvco,:,,"18.7MHz/V;
C, == 330 nF;
W R = 124 Hz;
tn == 20 Hz;
( = 0.675
Postfiltar: Rt ==10 kO;

R==33kO

Ct ==47 nF

Standard dimensioning: C2 = C"5

Vs, = 5 V;

VS2 =33 V;

VS3 =12 V;

R2 to R4 ==22 kO;

RL =22 kO

Application circuit
[1

"

Tuner

H

Oivider:64

'ose
3MHz

°1

lI."orlCop

18pF
01
Filter

[,

F F
16

15

18
13

R

PLLIC
SDA 2112-2

[2

5

8
10
7

CPL

62,5kHz LO[K LOM GNO

7-8

IFO
PLE

3

INO

OSC
Serial Interface to I1C

SDA2112-2

Truth table

Input "IFO" bit

Outputs

Meaning

2 13

214

2 15

Bdl/III

VHF

UHF

H

H

L

H

H

L

"UHF"

H

L

H

H

L

H

"Bd I/VHF"

L

L

H

L

L

H

"Bd IIIIVHF"

L

H

H

L

H

H

"Bd III/VHF"

At positive logic, the "IFO" bits 20 ... 212 complement the dual code from divider ratio N.

Pulse diagram

~ - . . . . . "'. . . . . . . . . . . ,. . . . . . U
. . . . . ,. . . . . . """. . LJ ill JL

IIILSB

PLE

O...="---_ _~

.__ n
~L

MSB

I

:1-1- - -

I-- Divider Ratio N ---+j
LSB
- - H:LHHLHLHLLLHHILL
20

I

12 13
N = 1874, Bd ill !VHF

I'------y-----------./I
liFO Evaluated by CPL and PLE

I

I

I

7-9

SOA 2112-2

Pulse

~jagram

OSC
ClK

PLE
90%

7-10

SDA2112-2

Test and measurement circuits
5V

18

116 16

~6

/15

V15

15

Signal
Inputs
Push-Pull

Test circuit 1

•

17,8,10

V7, 8, 1

7,8,10

CPLlIFO/PLE
BUS Inputs

Test circuit 2

/30,:..,4;::.,5-+3"-,4..:.,:,5_---.
V3, 4, ~5- - 1

Band
Selection
Outputs

Test circuit 3
7-11

SDA 2112-2

Test and measurement circuits

CrystalOs"iilator

h
OutputCLK

Test circuit 4

33V
22k12

10k12
Tuning Section
Inputs/Outputs

V

114

14---~-1~4r-------------~

Test circuit 5
7-12

SIEMENS

SDA 2211
Pre-scaler 1:64 for 1.3 GHz
with Low Current Consumption
Preliminary data

The Ie has been designed for application in TV receivers using the frequency control of the frequency synthesis rough copy concept. It includes a pre-amplifier and an Eel pre-scaler with
a 1:64 scaling rate and symmetrical Eel push-pull outputs. The operating range of the Ie extends
to an input frequency of 1.3 GHz .
• Minimal current consumption
• High input sensitivity

Maximum ratings

-------

V

Vi2.3

-0.3t06
2.5

Vq6.7

Vs

V

-/q6,7

to

mA

7j
Tstg

125
40 to 125

°C
°C

RthSA

115

K/W

Vs

4.5 to 5.5
70 to 1300
o to 70

V

Vs

Supply voltage
Input voltage
Output voltage
Output cu rrent
Junction temperature
Storage temperature range
Thermal resistance:
System-air

Vpp

Range of operation
Supply voltage
Input frequency
Ambient temperature range

f
Tamb

7-13

MHz

°C

Pre-scaler 1:64 for 1 GHz with low current consumption

Characteristics (Vs = 4.5 - 5.5 V;

Tamb = 0 - 70°C)

min
Current consumption
inputs blocked,
outputs free
Output voltage shift
(at each output)
CL:s;15 pF
CL=60 pF
Input level
("Input sensitivity")
70 MHz
80 MHz
120 MHz
250 MHz
600 MHz
1000 MHz
1100 MHz
1200 MHz
1300 Mhz

SDA 2211

typ

max

23

29

mA

0.5
0.35

1.2

dBm
dBm

-26
-27
-30
·32
·27
·27
·27
·21
·15

3
3
3
3

dBm
dBm.
dBm
dBm
dBm
dBm
dBm
dBm
dBm

Is

Vq

VI

~
3
3
3
3

Circuit description
The pre-amplifier of the IC features symmetrical push-pull outputs. If one of the signal inputs
is in an asymmetrical driving mode the other input should be grounded by a capacitor t 1.5 nF)
with low series inductivity. The pre-scaler of the IC consists of several status controlled master
slave flip flops with a 1:64 scaling rate.
.
The asymmetrical push-pull outputs of the pre-scaler have been designed with an internal
resistance of 5000 each. The DC voltage level of the outputs is connected to the supply voltage
Vs (output "high" = Vs). The typical shift is 1 Vpp.

Pin configuration

Pin·No.

Function

1
2
3
4
5
6
7
8

N.C.
Input 11
Input 12
Ground
N.C.
Output 02
Output 01
Supply voltage Vs

7-14

Pre-scaler 1:64 for 1 GHz with low current consumption

SOA 2211

Block diagram

,....

C\J

o

o

ci
z

oE
o..c:::
LOO

oE
LOO

O.c:

"C

c:::

::J

0
....

q-

(/)

>

(!l

(0

,....

IX)

C\J

u

q-

C')

,....

z

7-15

Pre-scaler 1:64 for 1 GHz with low current consumption

SOA 2211

Test and measurement circuits
Signal generator calibration

Signal
generator

son

6 dB
Attenuator

l

;'

I
I

,-

I
I

r - - - -

no cable

I

;'

I
_ _ _ _ _ _ _ .v'

","

;'

50
Ohm

Power
measurement
device

'"

;'

",'"

'"

I '

Measurement configuration for input sensitivity and the output voltage swing

Signal
generator
50 Ohm

+5V

L... _ _ _ _ _ _

r

Frequency
counter

I
7 1 - - - - -....
Oscillator

5

15pF

I(60 I
PF)

Test circuit 1

7-16

Capacitive load definition
for output voltage swing
measurement:
CLoad + capacities of the
measurement devices = 15 pF
(60 pF)

Pre-scaler 1:64 for 1 GHz with low current consumption

SDA 2211

Typical input sensitivity of pre-scaler
Vs=5 V; Tamb=25°C
1000 mV
10dBm

•
•
•

100 mV

•

•

OdBm

•
-10dBm

-20dBm

10 mV
-30dBm

-40dBm

1 mV
-50dBm

N

::t:

N

::t:

N

::t:

::1!

::1!

::1!

o

o

o
o

l5

C»

N

N

::t:

::t:

C\I

15

::1!
o
o

::1!
o

N

::t:

'::1!
o
o
C\j

7-17

SIEMENS

SOA 2506
Nonvolatile Memory 1-kbit E2PROM
• Word-Organized Programmable Nonvolatile
Memory in N-Channel Floating-Gate
Technology

• Data (8 Bits), Address (7 Bits), and Control
Information Input (1 Bit) as we" as Serial
Data Output

• 128 x 8 Bit Organization

• More than 104 Reprogramming Cycles Per
Address

• Supply Voltage 5V

• Data Retention in Excess of 10 Years
(Operating Temperature Range)

• A Total of Three Lines Between Control
Processor and the E2PROM for Data
Transfer and Chip Control

• Unlimited Number of Reads without
Refresh
• Erase and Write in 10 ms

Pin Configuration
vss 1 I:
CE 21:
Voo 3 I:
o 41:

'-../

Pin Description

P 8 TG
P7TP
P 6 N.C.

Pin

Symbol

Function

1
2

Vss
CE
VCC
D

GND
Chip Enable
Supply Voltage 5V
Data Input/Output
Clock Input
' Not Connected
Test Input, at Vss
Test Input, Remains Open

3
4

ps.

5
6

0091-3

7
8

ell
N.C.
TP
TG

The SDA 2506 is a serial E2PROM organized as 128 words by 8 bits. Packaged in an 8-pin plastic dual-in-line
package, the device is controlled via a three-wire serial bus. The device requires only a single 5V supply for
operation.

@Siemens Components, Inc.

7-18

April 1988

SDA 2506

Data Transfer and Chip Control
The total data transfer between the control processor and the E2PROM requires three lines, each of
which has several functions:
a.
-

Data Line D
Bidirectional serial data transfer
Serial address input
Clocked input of control information
Direct control input

b.
-

Clock Line cI>
Data, address, and control bit input
Data output
Start of read with transfer of data from memory
into shift register and/or start of data change during reprogramming

c. Chip Enable Line CE
- Chip reset and data input (active high)
- Chip enable (active low)
Prior to chip enable, the data, address, and control
information is clocked via the bidirectional data bus.
During the reprogramming and read process, this
data is retained in the shift register up to the second
clock pulse. The following data formats must be entered:
a. Read Memory:
one a-bit control word comprising:
- 7 address bits AO to A6 (AO goes first as LSB)
- 1 control bit, SB = "0", after A6
b. Reprogram Memory:
(erase and/or write operation)
16-bit input information comprising:
- a bits, DO to 07 new memory information (DO
goes first as LSB)
- 7 bits, AO to A6 address information (AO as LSB
goes first after 07)
-1 bit, control information, SB = "1", after A6

Read

(Figure 1)

Subsequent to data input and with SB = "0", the
read process of the selected word address is started
when CE changes from "1" to "0". The information
on the data line is not effective during chip enable.

With the first clock pulse after CE = "0", the data
word of the selected memory address is transferred
into the shift register. After the first cI> pulse has ended, the data output becomes low in impedance and
the first data bit can be read at the data pin. During
each additional clock pulse, a data bit is shifted to
the output. The data line returns to high-impedance
mode when CE transitions from "0" to "1".

Reprogramming

(Figure 2)

A full reprogramming process comprises an eni.se
and a subsequent write process. During the erase
process, all bits of the selected word are set to the
"1" state. During a write process, the "0" states are
set according to the information in the shift register.
The reprogramming process is started after data input during chip enable when the information SB =
"1" is available in the relevant cell of the shift register. The selection of an erase or write process depends on the information on data line 0 during chip
enable.
An erase process in the "1" state requires a "1" at
the data input when CE transitions to low. Similarly,
a write process in the "0" state requires that a "0"
be present on the data line during chip enable.
To start the programming process, a start pulse
must be present at clock input cI>. The control information on 0 must remain stable up to the riSing edge
of the start pulse. The active data change begins
with the trailing edge of the start pulse. The programming process ~ended by terminating chip enable, that is, when CE = "1".
The reprogramming of a word begins during the start
and execution of the erase process. The erase process is ended when CE = "1". The control bit SB =
"1" also required for the write process remains stable in the shift register after the erase process is
terminated. The writing of the selected word, therefore, requires nothing more than changing da~ine,
from"1" to "0", enabling the chip again with CE =
"0" and starting the data change with the start
pulse.

o

The erase and write processes can be performed
separately. In order to ensure a uniform "1" sta,t!3 for
all eight bits of the selected memory address during
the erase process, a data word with eight times "1"
must be entered prior to the erase process. When
writing a word which was not erased previously, the
"0" states of old and new information are added up.

7-19

SDA 2506

Reset

Absolute Maximum Ratings·

A non-selected memory is automatically in the reset
state due to CE' = ''1'~. All flipflops of the process
control are reset. However, the information in the
shift register is retained and changed only by shifting
the data. The reset state is also set by on-chip circuitry during memory power on.

Supply Voltage Range (Vee> ............... 0.3V to 6V

Certain applications require a "clear all" function.
This can be done in the test mode as follows:

Input Voltage Range (Vi) ............. -0.3V to 6V
Power Dissipation (Pv) ................. : .. 40 mW
Storage Temperature Range (T81g) • - 40·C to 125·C
Thermal Resistance
(System-Air) (RlhSA) ....•...•..•••..•• 100 K!W

1) activate test mode by connecting TP (Pin 7) to
Vee (5V).

Operating Range

2) ,send address 0 (Ao ... ~) and control bit SB =
1.
3) set CE to "0" for 25 ms. The device will then
"clear all".

Supply Voltage (Vee) .......•...... 4. 75V to 5.25V

4) The process is terminated by switching CE to "1",
and connecting TP to ground.

Ambient Temperature (TA) ..••...••... O·C to 70"C
·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Static Characteristics
Parameter

Limits

Symbol

Supply Voltage

Units

Typ

Max

5

5.25

V

3

mA

0.8
10

V
V
p.A

IL

0.5

mA

IH

10

p.A

60

p.s

Min
Vee

Supply Current ,

lee

Inputs
0,41, CE
VH = 5.25V

VL
VH
IH

4.75

,

2.4

Data Output D (Open Drain)
VL
VH

= 0.8V
= 5.25V

Clock Pulse 41
High Duration
Low Duration

41H

Before! After «IIH

«IlL

Before! After CE Transition
Before! After 0 Change

2.5
5

p.s

41L

5

p.s

41L

2.5

p.s

DH
DL '

2.5
2.5

p.s
p.s

~t

2.5
10
10

DataD
Before! After 41 Trailing Edge
Time Between Rising and
Trailing Edge
CE Referenced to 0
Erase Time
Write Time

7-20

tar
twr

20
20

p.s
ms
ms

SDA 2506
Read Cycle (1-kbit E2PROM)

1-------....,

\...._ _ _ _ _ _ _ _ _ _-',~

CE 0

_______

q,

~ .JL~fi\

o

! ~:]'mSB="O"~~:»..;:.D7:..._
I

Data Inpu~ Addr...
and Conlrol BII

ISota.tart I

___

m

I

Data al Qulpul

Transfer
0091-1

Figure 1

Reprogramming Cycle (1-kbit E2PROM)

\...._ _ _--'f\~_ _ _--',-

CE
q,

~

-FL ~......Q;~:.=~;a....._

o ~ ~:::xmSB="I" D="I"~

I

Data Input Data Word,
Address and Conlrol Bil

IErase
Start I

r. f

L-£ol&
...~.:.:=~:.:.:.

_'{i\..:..1

0="0"

I I SlBrt
Wril.

~
I

IWf

0091-2

Figure 2

Ordering Information
Type

Ordering Code

SDA2506

067100-H8115

7-21

SIEMENS

SDA 2516
Nonvolatile Memory 1·kbit E2PROM
with 12C Bus Interface
• Word-Organized Programmable Nonvolatile
Memory in n-Channel Floating-Gate
Technology (E2PROM)

• Reprogramming Mode, 15 ms Erase/Write
Cycle
.

• 128 x 8 Bit Organization

• Reprogramming by Means of On-Chip
Control (without External Control)

• Supply Voltage 5V

• Data Retention in Excess of 10 Years

• Serial 2-Line Bus for Data Input and Output
(12C Bus)

• More than 104 Reprogramming Cycles per
Address

Pin Configuration

Pin Definitions

(Top View)

v§'n8V~

CSO 2

7 N.C.

CSI 3

6 SCL

CS2/TP 4

,

,

Pin

Symbol

1
2
3

Vss
CSO
CS1
CS2/TP
SDA
SCl
N.C.
Vee

4
5
6
7
8

5 SOA
0092-3

Function
GND
}
.

Chip Select Inputs
Test Operation Control

Data Line } 12C B
Clock Line
us
Not Connected
Supply Voltage

The 12C bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists
of a serial data line SDA and a serial clock line SCL. Both lines require an external pull-up resistor to Voo
(open drain output stages).
The possible operational states of the 12C bus are shown in Figure 1. In the quiescent state, both lines SDA
and SCl are high, i.e. the output stages are disabled. As long as SCl remains "1", information changes on the
data bus indicate the start or the end of a data transfer between two components. The transition on SOA from
"1" to "0" is a start condition, the transition from "0" to "1" a stop condition. During a data transfer the
information on the data bus will only change while the clock line SCl is "0". The information on SOA is valid as
long as SCl is "1".
In conjunction with an 12C bus system, the memory component can operate as a receiver, and as a transmitter
(slave receiver/listener, or slave transmitter/talker). Between a start and a stop condition, information is
always transmitted in byte-organized form (8 bits). Between the trailing edge of the eighth transmission pulse
and a ninth acknowledge clock pulse, the memory component sets the SDA line to low as a confirmation of
reception, if the chip select conditions have been met. During the output of data, the data output becomes high
in impedance if the master receiver leaves the SOA line high during the acknowledge clock pulse.
The signal timing required for the operation of the 12C bus is summarized in Figure 2 (high-speed mode).

\

@Siemens Components, Inc.

7-22

April 1988

SDA 2516
Control Functions of the 12C Bus
The memory component is controlled by the controller (master) via the 12C bus in two operating modes:
read cycle, and reprogramming cycle, including
erase and write to a memory address. In both operating modes, the controller, as transmitter, has to
provide 3 bytes and an additional acknowledge
clock pulse to the bus after the start condition: A
rapid read mode enables the reading of data immediately after the slave address has been input. During a memory read, at least eight additional clock
pulses are required to accept the data from the
memory, before the stop condition may follow. In the
programming case, the active programming process
is only started by the stop condition after data input.
With a 3-bit chip select word (CSO, CS1, CS2) it is
possible for the user to individually address 8 memory components connected in parallel. Chip select is
achieved when the three control bits logically correspond to the selected conditions at the three select
inputs CSO, CS1, CS2.

During erase, all eight bits of the selected word are
set into the "1" state. During write, "0" states are
generated according to the information in the internal data register, i.e. according to the third input control word.
After the 27th and last clock of the control word input, the active programming process is started by
the stop condition. The active reprogramming process is executed under on-chip control and can be
terminated by addressing the component via SeL
and SDA.
The time required for reprogramming depends on
component deviation and data patterns. Therefore,
with rated supply voltage the erase/write process
extends over maximum 30 ms or, more typically,
15 ms. For the input of a data word without write
request (write request is defined as data bit in the
data register set to "0"), the write process is suppressed and the programming time is shortened.
During a subsequent programming of an already
erased memory address, the erase process is suppressed again, so that the reprogramming time is
also shortened.

Memory Read
After the input of the first two control words and 18
SCL pulses, a resetting of the start condition and the
input of a third control word, the memory is set ready
to read. During acknowledge clock nine, the memory
information is transferred in parallel mode to the internal data register. Subsequent to the trailing edge
of the acknowledge clock, the data output is low-ohmic and the first data bit can be sampled. With each
shift clock, an additional bit reaches the output. After
reading a byte, the internal address counter is automatically incremented through the master receiver
acknowledge, so that any number of memory locations can be read one after the other. At address
127, an overflow to address 0 is initiated. With the
stop condition, the data output returns to high-impedance mode. The internal sequence control of the
memory component is reset from the read to the
quiescent state with the stop condition.

Memory Reprogramming

Switch-On Mode and Chip Reset
After the supply voltage Vee has been connected,
the data output will be in the high impedance mode.
As a rule, the first operating mode to be entered
should be the read process of a word address. Subsequent to data output and the stop condition, the
internal control logic is reset. However, in case of a
subsequent active programming operation, the stop
condition will not reset the control logic.

Test Mode-Total Erase
The address register is loaded with address 0, the
data register with FF (hex) by entering the control
word "programming". However, immediately prior to
generating the stop condition, input CS2/TP is connected from OV to 12V. The subl!equent stop condition triggers a total erase procedure. which has to be
performed under the component address 0 (CSO =
L, CS1 = L, CS2 = L).

The reprogramming cycle of a memory word comprises an erase and a subsequent write process.

7-23

SDA 2516

Absolute Maximum Ratings·
Supply Voltage Range (Vee> ........ - 0.3V to + 6V
Input Voltage Range (Vi) ........... -0.3V to + 6V
Power Dissipation (Pv) .................... 50 mW
Storage Temperature
Range (Tstg) ................ -40·C to + 125·C
Thermal Resistance (RthSA>
(System-Air) ............•............ 100 K/W

Operating Range

Supply Voltage (Vce> .............. 4. 75V to 5.25V
Ambient Temperature (TA) .......... O·C to + 70·C
*Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability..

Characteristics
Parameter

Limits

Symbol
Min

Supply Voltage

Vce

Supply Current

Ice

Typ

4.75

Units
Max

5.25

V

8

rnA

1.5

V

Voo

V

Inputs Sel/SDA

Low Level Input

Vil

High Level Input

VIH

High Current (VIH = Voo Max>

IIH

10

/LA

Low Current (VOL = 0.4V)

IOl

3.0

rnA

Leakage Current (VOH = VOO Max)

IOH

10

/LA

Low Level Input

Vil

0.2

V

High Level Input

VIH

Vec

V

High Current Input

IIH

100

/LA

Clock Frequency

fSCl

100

KHz

Reprogramming Duration
(Erasing and Writing)

tprog

30

ms

3.0

OutputSDA

Inputs CSO, CS1, CS2/TP
4.5

15

Input Capacity

CI

10

pF

Full Erase Duration
(Test Mode Full Erase)

tar

50

ms

7-24

SDA 2516

Operational States of the 12C Bus

r-----------------------,
I
I

SDA

I

I

SCL
I~ _______________________ JI

Slllll

Cllta T...... _

willi Acknowlodge BK

Slop

Figure 1

Timing Conditions for the 12C Bus (High-Speed Mode)
SDA

SCL

SDA
tSU,STO

....-2

Figure 2
tBUF

t> tLOWMin

The minimum time the bus must be free
before a new transmission can start

tHD; STA

t> tHIGH Min

Start Condition Hold Time

tLOWMin

4.7/J-s

Clock lOW Period

tHIGH Min

4/J-s

Clock HIGH Period

tSU;STA

t> tLOWMin

Start condition set-up time, only valid for
reported start code

tHD;DAT

t> O/J-s

Data Hold Time

tSU;DAT

t>250ns

Data Set-Up Time

tR

t < 1 /J-s

Rise Time of both the SOA and SCl Line

tF

t<300ns

Fall Time of both the SOA and SCl line

tSU;STO

t > tLOWMin

Stop Condition Set-Up Time

Note:
All values refer to VIH and VIL levels.

7-25

SDA 2516
Control Word Input Read
a) Complete (with Word Address Input)
ST

IAs I

CS/E

IAs I ST

WA

IAs I

CS/A

OA

IAml

OA

SP

t

n Bytes
Last Byte
Automatic Incrementation
of the Word Address
(b) Shortened
(Read Starts with Last
Used Word Address)

!

IAs I

CS/A

ST

OA

IAml

n Bytes

OA. .
Last Byte

Control Word Input Program

I ST I

CS/E

IAs I

WA

IAs I

OE

IAs. I

(Reprogramming Starts
after This Stop Condition)

SP

Control Word Table
Clock No.

1

2

3

4

CS/E

1

0

1

0

CS2 CS1 CSO

5

CS2 CS1 CSO

7

8

9

(Acknowledge)

0

0

Through Memory

CS/A

1

0

1

0

1

0

Through Memory

WA

X

A6

A5

A4

A3

A2

A1

AO

0

Through Memory

OE

07

06

05

04

03

02

01

00

0

Through Memory

OA

07

06

05

04

03

02

01

DO-

0

Through Master

Control Word Input Key:
CS/E
Chip Select for Oata Input into
Memory
CSt A
Chip Select for Oata Output out of
Memory
WA
Memory Word Address
OE
Oata Word for Memory
OA
Oata Word Read out of Memory
00 to 07
Oata Bits
ST
Start Condition
SP
Stop Condition
As
Acknowledge Bit from Memory
Am
Acknowledge Bit from Master
CSO, CS1, CS2 Chip Select Bits
AO to A6
Memory Word Address Bits

7-26

6

Ordering Information
Type

Ordering Code

SOA2516

Q67100-H8133

SP

SIEMENS

SOA 2526
Nonvolatile Memory 2-kbit E2PROM with 12C Bus Interface
• Word-Organized Programmable Nonvolatile
Memory in n-Channel Floating-Gate
Technology (E2PROM)

• Reprogramming Mode, 15 ms Erase/Write
Cycle
• Reprogramming by Means of On-Chip
Control (without External Control)

• 256 x 8 Bit Organization
• Supply Voltage 5V

• Data Retention in Excess of 10 Years

• Serial 2-Line Bus for Data Input and Output
(12C Bus)

• More than 10 4 Reprogramming Cycles per
Address

Pin Configuration

Pin Definitions

(Top View)
vss

CE
vcc
0

1C
2C
3C
4C

'-.../

::::I

8 TG

::::17 TP

::::I

6 N.C.

::::15.

Pin

Symbol

Function

1
2
3
4
5

VSS
CE
VCC
D

N.C.
TP
TG

Ground
Chip Enable
Supply Voltage 5V
Data Input/Output·
Clock Input
Not Connected
Test Input to Vss
Test Input, Remains Open

6
7

0093-4

8

The 12C bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists
of a serial data line SDA and a serial clock line SCL. Both lines require an external pull-up resistor to VOO
(open drain output stages).
The possible operational states of the 12C bus are shown in Figure 1. In the quiescent state, both lines SDA
and SCL are high, I.e. the output stages are disabled. As long as SCL remains "1 ", information changes on the
data bus indicate the start or the end of a data transfer between two components. The transition on SDA from
"1" to "0" is a start condition, the transition from "0" to "1" a stop condition. During a data transfer the
information on the data bus will only change while the clock line SCL is "0". The information on SDA is valid as
long as SCL is "1".
In conjunction with an 12C bus system, the memory component can operate as a receiver, and as a transmitter
(slave receiver/listener, or slave transmitter/talker). Between a start and a stop condition, information is
always transmitted in byte-organized form (8 bits). Between the trailing edge of the eighth transmission pulse
and a ninth acknowledge clock pulse, the memory component sets the SDA line to low as a confirmation of
reception, if the chip select conditions have been met. During the output of data, the data output becomes high
in impedance if the master receiver leaves the SDA line high during the acknowledge clock pulse.
The signal timing required for the operation of the 12C bus is summarized in Figure 2 (high-speed mode).

©Siemens Components, Inc.

7-27

April 1988

SDA 2526

Control Functions of the 12C Bus
The memory component is controlled by the controller (master) via the 12C bus in two operating modes:
read cycle, and reprogramming cycle, including
erase and write to a memory address. In both operating modes, the controller, as transmitter, has to
provide 3 bytes and an additional acknowledge
clock pulse to the bus after the start condition. A
rapid read mode enables the reading of data immediatley after the slave address has been input. During a memory read, at least eight additional clock
pulses are required to accept the data from the
memory, before the'stop condition may follow. In the
programming case, the active programming process
is only started by the stop condition after data input.
With a 3-bit chip select word (CSO, CS1, CS2) it is
possible for the user to individually address 8 'memory components connected in parallel. Chip select is
achieved when the three control bits logically correspond to the selected conditions at the three select
inputs CSO, CS1, CS2.

During erase, all eight bits of the selected word are
set into the "1" state. During write, "0" states are
generated according to the information in the internal data register, i.e. according to the third input control word.
After the 27th and last clock of the control word input, the active programming process is started by
the stop condition. The active reprogramming process is executed under on-chip control and can be
tel1T1inated by addressing the component via SCl
and SDA.
The time required fro reprogramming depends on
components deviation and data patterns. Therefore.
with rated supply voltage the erase/write process
extends over maximum 30 ms or, more typically, 15
ms. For the input of a data word without write request (write request is defined as data bit in the data
register set to "0"), the write process is suppressed
and the programming time is shortened. During a
subsequent programming of an already erased
memory address, the erase process is suppressed
again, so that the reprogramming time is also shortened.
-

Memory Read
After the input of the first two control words and 18
SCl pulses, a resetting of the start condition and the
input of a third control word, the memory is set ready
to read. During acknowledge clock nine, the memory
information is transferred in parallel mode to the internal data register. Subsequent to the trailing edge
of the acknowledge clock, the data output is low-ohmic and the first data bit can be sampled. With each
shift clock, an additional bit reaches the output. After
reading a byte, the internal address counter is automatically incremented through the master receiver
acknowledge, so that any number of memory locations can be read one after the other. At address
255, an overflow to address 0 is initiated. With the
stop condition, the data output returns to high-impedance mode. The internal sequence control of the
memory component is reset from the read to the
quiescent state with the stop condition.

Memory Reprogramming
The reprogramming cycle of a memory word comprises an erase and a subsequent write process.

Switch-On Mode and Chip Reset
After the supply voltage Vee has been connected,
the data output will be in the high'impedance mode.
As a rule, the first operating mode to be entered
should be the read process of a word address. Subsequent to data output and the stop condition, the
internal control logic is reset. However, in case of a
subsequent active programming operation, the stop
condition will not reset the control logic.

Test Mode-Total Erase
The address register is loaded with address 0, the
data register with FF (hex) by entering the control
word "programming". However, immediately prior to
generating the stop condition, input CS2/TP is connected from OV to 12V. The subsequent stop condition triggers a total erase procedure. which has to be
performed under the component address 0 (CSO =
l, CS1 = l, CS2 = l).

SDA 2526

Absolute Maximum Ratings·
Supply Voltage Range (Vee> ........ -0.3V to
Input Voltage Range (Vi) ........... -0.3V to
Storage Temperature
Range (Tstg) ................ - 40·C to

+ 6V
+ 6V

+ 125·C

Thermal Resistance (RthSA)
(System-Air) ......................... 100 k/W

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Range
Supply Voltage (Vee> .............. 4.75V to 5.25V
Ambient Temperature (TA) .......... O·C to

+ 70·C

Characteristics
Parameter

limits

Symbol

Min·
Supply Voltage

Vcc

Supply Current

Typ

4.75

Units
Max
5.25

V

Ice

10

rnA

Low Level

VIL

0.8

V

High Level

VIH

Inputs Sel/SOA

High Current (VIH

3.0

Voo

V
p,A

=

Voo Max>

IIH

10

=

0.4V)

IOL

2.0

rnA

=

IOH

10

p,A

OutputSOA
Low Current (VOL

Leakage Current (VOH

VOO Max)

Inputs eso, eS1, eS2/TP
Low Level

VIL
4.5

0.2

V

VOO

V

High Level

VIH

High Current

IIH

100

p,A

Clock Frequency

fSCL

100

kHz

Reprogramming Duration
(Erasing and Writing)

t prog

30

ms

15

Input Capacity

CI

10

pF

Full Erase Duration
(Test Mode Full Erase)

tar

50

ms

13

V

Condition

VCS2/TP

11

12

7-29

SDA 2526

Timing Conditions for the 12C Bus
(High-Speed Mode)

Operational States of the 12C Bus
~-----------------------,

,i

SDA

'

SDA

SCL

,L _______________________ J,
SCL
SIaII

• Da1a TlII1OIIIloaIon .... ~ BR
0093-1

FIgure 1

SDA
tsu,sTO

tsu,STA

0093-2

Figure 2
The minimum time the bus must be free
before a new transmission can start

tBUF

t> tLOWMin

tHO;STA

t> tHIGH Min

Start Condition Hold Time

tLOWMin

4.7 p.s

Clock LOW Period

tHIGH Min

4 p.s

Clock HIGH Period

tsU;STA

t> tLOWMin

Start condition set·up time, only valid for
reported start code .

tHO; OAT

t> 0 p.s

Data Hold Time

tsu; OAT

t>250ns

Data Set· Up Time

tR

t < 1 p.s

Rise Time of both the SOA and SCL Line

tF

t<300ns

Fall Time of both the SOA and SCL Line

Stop Condition Set·Up Time
t> tLOWMln
tSU;STO
Note:
All values refer to VIH and VIL levels.
Control Word Input Read
a) Complete (with Word Address Input)

I ST I

CS/E

IAsl

WA

IAsl ST

CS/A

IAsl

OA
n Bytes

~ml

t

OA

11 I

SP

11

SP

LastByte

Automatic Incrementation
of the Word Address

~

b) Shortened
(Read Starts with Last
Used Word Address)

ST

CS/A

IAsl

DA
n Bytes

fml

OA

I

Last Byte

Control Word Input Program
ST

CS/E

IAsl

WA

IAsl

DE

IAsj SP

(reprogramming starts
after this stop condition)
0093-3

7-30

SDA 2526
Control Word Table
Clock No.

1

2

3

4

CS/E

1

0

1

0

CS2 CS1 CSO
CS2 CS1 CSO

5

CS/A

7

8

9

(Acknowledge)

0

0

Through Memory

CS/A

1

0

1

0

1

0

Through Memory

WA

X

A6

A5

A4

A3

A2

A1

AO

0

Through Memory

DE

D7

06

05

04

03

02

01

DO

0

Through Memory

OA

07

06

05

04

03

02

01

DO

0

Through Master

Control Word Input Key:
CS/E

6

Chip Select for Data Input into
Memory
Chip Select for Data Output out of
Memory

Ordering Information
Type

Ordering Code

SOA2526

Q67100·H8184

WA
DE
OA
DO to 07
ST
SP
As

Memory Word Address
Data Word for Memory
Data Word Read out of Memory
Data Bits
Start Condition
Stop Condition
Acknowledge Bit from Memory
Am
Acknowledge Bit from Master
CSO, CS1, CS2 Chip Select Bits
AOtoA6
Memory Word Address Bits

7-31

SIEME.NS

SDA 3112
TVPLL
The SDA 3112 is produced in ASBCtechnology.ln connection with VCO (tuner) and a fast prescaler
(prescaler factor 1:64), it represents a digitally programmable PLL for a TV set with frequency synthesis tuning. The PLL enables a crystal exact adjustment of the tuner oscillator frequencies for
the TV ranges band III/IVN in 125 kHz resolution (frequency range: 128 to 2000 MHz). A serial interface enables a simple connection to a microprocessor. This microprocessor loads the prescaler
and band selection outputs with the appropriate information. At the output LOCK the PLL sup·'
plies a state information (locked/released).
Features
• No need 'for an external integrator
• Noise free telegram transmission
• Integration time constant controlled by software
• Microprocessor compatible
Maximum ratings
Supply voltage

V

Vs

-0.3 to 7,5

VI
VI
VI
VI

-0,3 to
-0,3 to
-0,3 to
-0.3 to

Vo
Vo

-03 to Vs
-0.3 to 33
-7
-0,3 to 16
-1 to 5

V
V
rnA
V
rnA

Inputs

01,02,Irel
IFO, CPL, PLE
PLE
F,F
Outputs

PO
UO
BS1~BSs

IOL

--

Vo

Vs
Vs +0.5

7.8

Vs + 0.5

V
V
V
V

LOCK

10

Internal pull-up RL = 3 kO
Junction temperature
Storage temperature range

r;
Tstg

140
-55 to 150

°C
°C

Thermal resistance (system-air)

RthSA

80

K/W

Vs

V
MHz

R,

4.5 to 5.5
32
1024 to 16383
80

Vo

0.3 to 33

V

Tamb

Oto 85

°C

Operating range
Supply voltage range
Input frequency
Divider ratio
Resistance for, Irel
I rel = (Vs -o.8)RI
Tuning voltage range
open collector
Ambient temperature range

fF,

ff

N

7-32

kQ

SDA3112

Characteristics (VS = 5 V ± 0.5 V;

Tamb

= 0 to 70 ec)
min

typ

max

22
4

35

Supply current
Crystal frequency Series C = 18 pf
Signal inputs Fir:
Input voltage

Is
fq

15

V'6H
V'6L

3.92
3.8

Input current
V'6=5 V
Input sensitivity at
sine push-pullitriggering; f= 32 MHz

1'6

Inputs (IFO, CPL, PLE)
Upper threshold voltage
Lower threshold voltage
Input current
VSH =5 V
VSl =0.4 V
VSL=0.8 V
Band select outputs (BS1 .... BS5)
Reverse current
V3H =15 V
Current drain
2V;;;V3 ;;;15V
Tuning section PO, UD, I ref , LOCK
Charge pump current
Ipump = 10 x Ire!; RI = 120 k~; Vs = 5V
Tuning voltage
l,sL = 1.5 mA
Reverse current
V,sH=33 V
Reference current
ext.R =120 kO
Output voltage
int. RL =3 kO
I'2H =-100 J.LA
I'2l =100 J.LA

IFO, PLE
Set-up time for
release
data
Hold time for:
release
data
CPL
H pulse width
L pulse width

V'6

120

VSH
VSL

2.4

mA
MHz

Vs +0.12 V
V
Vs
50

p.A

1200

mVpp

V
0.8

V
J.LA
J.LA

ISl

8
-550
-500

I3H

10

J.LA

ISH
ISL

/LA

I3H

0.5

3

mA

1'3

±250

±550

J.LA

V'SL

0.3

V

I,sH

20

J.LA

40

I1 A

1'4

30

V'2H

4.5

V

0.7

V'2L

V

tvo

2
2

J.Ls
J.Ls

tHE
tHO

2
2

J.Ls
J.Ls

tCH
tCl

2
2

J.Ls
J.Ls

tVE

7·33

SDA3112

Circuit description
_
Triggered by the ECI inputs F/F a switchable 32133 counter operates as a 14 bit synchronous prescaler
in the dual modulus method by combining it with a5 and 9 bit programmable synchronous counter.
In this combination the 5 bit counter controls the switch·overfrom 32 to 33 (block diagram 1). Dividing
ratios of N= 1024 to 16383 are possible.
The 18 bit deep shift register latc~ is subdivided into 14 bits for storing the dividing ratio N, as well
as 1 biUorselecting the pump current and 3 bits for controlling the5 band selection outputs. ,
The telegram is inserted over the serial data input IFO with the H-L slope of the shift clock CPL,
when the enable input is set at H. Beginning with LSB, the complement of the dividing ratio is inserted in binary code, then the select bit 214 for the pump current and the band selection control
bits 215, 216, 217 (please refer to enclosed table).
An integrated control circuit checks the world length (18 bit) of the dl;lta telegram. The 18 bi~ latch
accepts the data from the shift register during the L state of the enable input PLE.
A 4 MHz crystal controlled clock oscillator has been integrated in the IC. An internal reference divider
divides the output signal ofthe crystal oscillator (fose =4 MHz) by 2048 resulting in 1.953125 kHz
(reference signal), providing a frequency resolution of 125 kHzby means of the asynchronous permanent prescaler (dividing factor 1:64).
'
In a digital phase detector the divided VCO input signal is compared with the reference signal.
If the falling slope of the VCO input signal appears before the falling slope of the reference signal,
the output DOWN of the phase detector will be in the H state for the duration of the phase difference. However, if above signal sequence is reversed, the output UP will be in the H state instead.
The outputs UP/DOWN control the two current sources I + and 1- (charge pump). In case both
outputs are in the L state, the charge pump output will be in the high impedance mode (TRI-STATE).
Information with respect to either the H or L state wi II be provided at the LOCK output by the logical
"NOR" of the outputs UPIDOWN.
The output current of the charg-e pump (source current =drain current) is adjusted by an external
resistor between pin /ref and Vee. In addition, this output current can be generated by the control
bit forthe pump current at the same value or at a value increased by a factor of 10 (refer to enclosed table).
'
The current pulses generated by the charge pump are integrated into the tuning voltage by means
of an active low pass filter (on-chip loop amplifier and external RC circuit). The dc output signal
of the low pass filter is available at Vo and is used as tuning voltage for the VCO. In order to provide tuning voltages higher than Vee =5 V, the output stage of the amplifier consists of a transistor
with an open collector. The external collector resistor can be connected to voltages up to 33 V.
To switch voltages higher than Vs =5 V, the band selection outputs (BS1, BS2, BS3, BS4, BS5) include current drains with open collectors. It is therefore possible to directly connect transistors
operating as band selection switches without the use of current limiting resistors (please refer
to enclosed application current).

7-34

SDA3112

Pin configuration

Pin No.

1
2
3
4

5
6
7

8
9
10
11
12
13
14
15

16
17
18

Symbol

Function

Q1
Q2
BS1
BS2
BS3
BS4
BS5
PLE
GND
CPL
IFO

Crystal
Crystal
Standard switchover output
Band selection output BS
Band selection output VH F
Band selection output UHF
Band selection output 11111
Release input for shift register
Ground
Shift clock pulse input
Data input
Lock output
Amplifier input/charge pump output
Current adjustment for charge pump
Tuning voltage output
Signal input
Signal input
Supply voltage

LOCK
PD
Iref

Vo
F
F

Vs

7·35

SDA3112

Loop-filter calculations

=

Loop bandwidth:

j f~ ::;~

Attenuation

1/2xWRXRxC,=.e

prescaler

= programmable divider ratio
= pump current
= tuner voltage characteristic

=W R

=

loop filter

Example for channel 47:

=

N "" 11520
Ip = 200 IJ.A Svco 18.7 MHzIV
R = 33 kC
C1 ... 330 nF
P == 64
WR ... 124 Hz
fR = 20 Hz
= 0.675 Standard dimensioning: C2 "" C1I5

e

Block diagram
4 MHz

Vs

o

GNO

LOCK

3ZV

<-

of!
...

QI

SDA3112

F

~

TUning
voltage

QI

!S

.J:.

c..

120kQ

zo__________________ Z'3
18 bit SR + memory with

\ CPL

PLE

v

Interface to

7·36

IFO /
~P

2'4

as decoder

SDA3112

Truth Table
"IFO" bit 214

Pump Current Ip

L
H

Iref

10 x Iref

"IFO" bit

=
=

Band selection outputs (L conducting,
H blocking)
BS1
BS2
BS3
BS4
BS5

215

216

217

L
L
L
L

L
L
H

H

H

H

H

L
L
H

L
H
L

H

H

H

H

H

H

H

H
H

L
L

L
L
L
L
H
H

L
L
H

L
H
L
H
L
H
L
H

H
L
L

L
H
H
H
L
H
H
H

H
H
L
H
H
H
L
H

Pulse diagram
(PL
I
I

I

II

I

PLEJ 'I
I
I

I
I

II

I

I

I

I I

I

IFO

II

L

I I I
I

!rr......
I UJ! 1

rr n I
-1 U U

I"""""-~!I

j
~----I
1- ~LHLHHH LLLLHHHLHLL
ILSB

I..
I

I
20
First bit

MSBi

Prescaler ratio
N=1930

iii
I

.. ~=},J.--

l-:-luHFI...-

I

I

I

213 z1~z15

I
z17

Last bit

7-37

SDA3112

Pulse diagram
Set-up and hold times

IFO

PLE

CPL

7·38

SDA3112

Test and measurement circuits

sv

bus inputs
PLECPLIFO

18

V16

[16

10kO
16

~,10,11

[17

V17

[S,10,11

PIN 8,10,11

20kO

10kO

17

Signal
mputs
push-pull

100llA

Test circuit 2
9

Test circuit 1

30kQ
V

[3,4,5,6,7
3,4,5,6,7

PIN
3,4,5,6,7

Band selection

Test circuit 3

7·39

SDA3112

Test and measurement circuits

15,,1

1krl

1krl

115"
4MHz

1 PIN 1
4 MHz c::J

T I~Z....,.,..,....,_-+-_ _~
'----I18pF PIN 2
Crystal oscillator

Test circuit 4

SV
[ref I
10 * [ref

120kQ
Skrl

[,4

14
33V

V,4

;!:

~

z:

z:

a:

a:
22krl
['S
V'S

15
30krl

Tuning section
inputs loutputs

3krl
[12

12

V13

113
~

13
PIN 13

Test circuit 5
7-40

z:

a:

V'z

SDA3112

Application circuit

Design proposal

RI = 120 kO (/p = 35/350 IlA)
RL = 22 kO, R2 ... R4 = 22 kO
Loop filter: R = 33 kO, C, = 330 nF, C 2 = 47 nF
Post filter (in the tuner): RT = 10 kO, CT = 47 nF

[T

"

Tuner

"F
H 'asc

Prescaler: 64
Vs

VS3
4 MHz

0

V\uner

RL

RI
Q1

Filter

Q2

F

F

Iref

PO

LOCK

R

IFO

[2

PLL IC

SDA3112

Vlun
Vsz
VHF

PLE

~

N
en

III

!il

III

Serial Interface to flC

CPL

~

GND

BdIt III
. VS2
UHF

7-41

SIEMENS

SDA 3202

1.3 GHz PLL with 12C Bus
• Cost-Effective and Space-Saving Design
• Prescaler Output Frequency is Free from
Interference Radiation

• Low Current Consumption
• Message Transmission Via 12C Bus
• 4 Software-Controlled Outputs

Pin Configuration

Pin Definitions
Pin
1

Top View

2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10
0100-12

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

Symbol
PO
01
02
SOA
SCL
P7
P6
P5
P4
P3
P2
P1
PO
Vs
. UHFIVHF
REF
GNO
Vo

Function
Input for Active Filter/Output for
Charge Pump
Crystal
Crystal
Data I/O for 12C Bus
Clock Input for 12C Bus
Port Output (Open Collector)
Port Output (Open Collector)
Port Output (Open Collector)
Port· Output (Open Collector)
Port Output (Current Sink)
Port Output (Current Sink)
Port Output (Current Sink)
Port Output (Current Sink) .
Supply Voltage
Signal Input
Amplifier-Reference Input
Ground
Output of Active Filter

Combined with a VCO (tuner), the SOA 3203 comprises a digital programmable phase-locked loop for television devices designed to use the PLL frequency synthesis tuning principle.
The PLL provides a cyrstal-stable frequency for tuner oscillators between 16 ... 1300 MHz in the 62.5 KHz
raster. By including an external prescaler 1/2, the component can also be used for synthesizing applications of
up to 2.4 GHz (e.g. satellite receivers). As a result, the resolution is doubled to 125 KHz. The tuning process is
controlled via an 12C bus by the microprocessor.

@Siemens Components, Inc.

7-42

May 1988

m

0'

n

~

C

~.

iiJ
3

14

15IUHF~
VHF

1.=UP

Cy
Phase
Frequency
Comparator

21al
lBPF

I

4MHz!9=

31 02

OSC
4 MHz

7,B125 kHz

fREF

l-=OOWN'

8-BilBus

51 SCL
41~~

TO (TrIstate Ii i 5 I

12C Bus
Control

PO IPl Ip2 Ip3 Ip4 Ips
13 112 111 110 19 18
0100-1

en

g
Co)

.....

N

~

Q

N

I

SDA 3202

Circuit Description
Tuning Section (refer to block diagram)
UHFIVHF The tuner signal is capacitively coupled
at the UHFIVHF input and subsequently
amplified.
REF

01, 02

The reference input REF should be disabled by a capacitor of low series inductance. The amplified signal passes
through an asynchronous divider with a
fixed ratio of P = 8 and an adjustable
divider N = 256...32767. Subsequent to
this process, the signal is compared in a
digital frequency phase detector with a
reference frequency fREF = 7.8125 kHz.

P4 ... P7 The open collector outputs P4, P5,' P6,
P7 can be used for a variety of different
applications.
12C Bus Interface
SCl, SOA An asynchronous bidirectional data bus
is used for data transfer between the
processor and the PlL. As a rule, the
clock pulse is supplied by the processor
(input SCl), while pin SOA operates as
input or output depending on the direction of data flow (open collector, external
pull-up resistor).
The data from the processor pass
through an 12C bus control. Depending
on their function, the data are subsequently filed in registers (latch 0-3). If
the bus is free, both lines will be in the
marking state (SOA, SCl are HIGH!.
Each tele- begins with the start condItions of SOA returning into low, while
SCl remains in High. All additional information transfer takes place during SCl
= low and the data is forwarded to the
control with the positive clock edge.
However, if SOA returns to High, while
SCl is in High, the message is ended
since the Pll acknowledges a stop condition.

This frequency has been derived from a
4 MHz crystal oscillator (pin 01, 02) by
dividing its output signal by.O = 512.
The phase detector includes two outputS
UP and DOWN which control the two
current sources I + and 1- of a charge
pump. If the negative edge of the divided
VCO signal appears prior to the negative
edge of the reference signal, the current
source I + will pulsate for the duration of
the phase difference. However, during
the reversed sequence of the negative
edges, the current source 1- will begin
to pulsate.

PO, Vo

For the following, also refer to table
"logic allocation".

If both signals are in phase, the charge
pump output PO changes into the high
impedance state (Pll in lock). An active
low pass filter (internal amplifier, external
output transistor at Vo, and RC combination) integrates the current pulses as the
tuning voltage for the VCO.

All messages are transmitted byte-bybyte, followed by a 9. clock pulse, while
the control returns the SOA line to low
(acknowledge conditions). The first byte
is comprised of 7 address bits. These are
used by the processor to select the Pll
from several peripheral components
(chip-select). The 8. bit is always low.

With the control bit 5 I the pump current
can be switched between two values per
software. Through this switch-over, the
control characteristics of the Pll during
lock-in can be changed, Le. varying tuner
characteristics in the various TV bands
can be adjusted.
PO ... P3 The software-controllable outputs PO,
P1, P2 and P3 can drive external PNP
transistors (internal current limit) which
operate as band selection switch.

7-44

In the data portion of the message the 1.
bit of the 1. or 3. data byte determines
whether a divider ratio or a control information is to follow. In each case, the 2.
byte of the same data type or a stop condition has to follow the 1. byte.
Vs, GNO

When the supply voltage is injected, a
Power on Reset circuit prevents the Pll
from setting the SOA line at low which
would disable the bus.

SDA 3202

Absolute Maximum Ratings*
Supply Voltage (Vs) ................. -0.3V to 6V

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Output PO (V1) ...•.................. -0.3V to Vs
Crystal 01 (V2) ........•............ -0.3V to Vs
Crystal 02 (V3) ..•..•...........•.•. -0.3V to Vs
Bus Input/Output SDA (V4) .........•• -0.3V to.vs

Port Output P5 (Iau
Open Collector ....••..•....• -1 mA to + 5 mA

Bus Input SCL (Vs) .................. -0.3V to Vs
Port Output P7 (Vs) .............. - 0.3V to + 16V
Port Output P6 (V7) ............•. -0.3V to + 16V

Port Output P4 (lgU
Open Collector .•••.......... -1 mA to + 5 mA

Port Output P5 (Va) .•....•.•...•. - 0.3V to + 16V

Junction Temperature (Tj) ........•..•..•.•• 125·C

Port Output P4 (Vg) .............. - 0.3V to + 16V

Storage Temperature
Range (Tstg) ......•......... - 40·C to + 125·C

Port Output P3 (V10) ..........•... -0.3V to + 16V

Thermal Resistance
System-Air (Rth SA) ...........•......... 80 K/W

Port Output P2 (V 11) .............. - 0.3V to + 16V
Port Output P1 (V12) ............•. - 0.3V to + 16V
Port Output PO (V 13) .•.•.........• - 0.3V to + 16V
Signal Input UHFIVHF (V1S) ...•.. -0.3V to + 2.5V

Operating Range

Reference Input REF (V16) .....•. -0.3V to + 2.5V

Supply Voltage (Vs) ....••.•.•..•..•. .4.5V to 5.5V

Output Active Filter Vo (V1a) .......... -0.3V to Vs

Ambient Temperature (TA) •.••.•..•..• O·C to 85·C

Bus Output SDA (l4U
Open Collector .............. -1 mA to + 5 mA

Input Frequency (f1S) ......... 16 MHz to 1300 MHz
Crystal Frequency (f2, 3) .........•..•....•. 4 MHz

Port Output P7 (Isu
Open Collector ...... '........ -1 mA to +5 mA

Divider Factor (N) •..............•..• 256 to 32767

Port Output P6 (17U
Open Collector .•....•.•.•... -1 mA to + 5 mA

Characteristics

=

Vs

5V; T A

Parameter

=

25·C

Symbol

Test
Circuit

Limits

Units

Min

Typ

Max

35

55

75

mA

4

MHz

Current Consumption

Is

1

Crystal Frequency
Series Capacitance 18 pF

f2,3"

1

80 ... 500 MHz

a15

2

-27110

3/315

dBm/·

500 ••. 1000 MHz

a15

2

-24/14

3/315

dBm/·

a15

2

-15/40

3/315

dBm/·

10

p.A

1.5

mA

Input Sensitivity UHF/VHF
f15
f15
f15

=
=
=

1200 MHz

Band Selection Outputs PO ... P3 (current sinks with internal resistance Ri = 12 k!l)
Leakage Current, V13H
Sink Current, V 13H

=

=

13.5V

12V

113H

3

113l

3

0.7

1

Port Outputs P4 ... P7 (switch with open collector)
Leakage Current, VgH
Residual Voltage, 19l

= 13.5V
= 1.7 mA

19H

4

10

pA

V9l

4

0.3

V

·Usted as mV,rns with 50n

7-45

SDA 3202

Characteristics Vs

= 5V; TA = 25°C (Continued)

Parameter
Phase Detector Output PD (Vs

Symbol

Test
Circuit

11H

5

Charge Pump Current
5 I = Low; V1 = 2V

11H

5

Output Voltage Locked

VIL

5

Active Filter Output Yo (Test modus TO

= 90 p.A
Output Voltage, V1L = OV

Units

Min

Typ

Max

±90

±220

±300

p.A

±22

±50

±75

p.A

2.5

V

= 5V)

Charge Pump Current
5 I = High; V1 = 2V

Output Current
V18 = O.BV; 114

Limits

1.5

= 1, PD = Tristate)

118

5

V18

5

V5H
V5L

6

15L
15L

p.A

500
100

mV

5.5
1.5

V
V

6
6

50
-100

p.A
p.A

V4H
V4L

6
6

12
0.4

V
V

tR

6

15

p.s

tF

6

15

p.s

Frequency

15

6

0

100

KHz

H-Pulse Width

t5HIGH

6

4

p.s

t5LOW

6

4

p.s

Set-UpTime

tsUSTA

6

4

p.s

Hold Time

tHDSTA

6

4

p.s

tsUSTO

6

4

p.s

teuF

6

4

Set-UpTime

tSUDAT

6

0.3

p.s

Hold Time

tHDDAT

6

0

p.s

Bus Inputs SCL, SDA
Input Voltage
Input Current
,V5H = Vs
V5L = OV

3

Output SDA (open collector)
Output Voltage
V4H = 5.5V
14L = 2mA
Edges SCL, SDA
Rise Time
Fall Time
Shift Register Clock Pulse SCL

L-Pulse Width
Start

Stop
Set-UpTime
Bus Free Time
Data Transfer

7-46

p.s

,

SDA 3202

Measurement Circuit 1
14

I,.

o-~~~--~------------~

__ ___
~

4pF

~

4pF

Crystal Oscillalo'

01
•

18 PF

I

125pA

4MHz=

02

17
o---------~------------~~-----GND

0100-2

Measurement Circuit 2
Calibration of Signal Generator
1--"'--+..,

OutpUi

Measu,ement
Device
500
Otoo-3

Measurement of Input Sensitivity
+5V

14
Signal

Generator

soO

*

6dS
Attenuation
Link

0100-4

Test mode: T1 = High
• no cable

Measurement Circuit 3

Measurement Circuit 4

n-,
V, ",9__....~...
, -tsoCl

2 k:Jn"
13-t'C
v,,'o.3__....1,:;:

0100-5

0100..6

7·47

SDA 3202

Measurement Circuit 5
v, 0----'"/,-----,

0100-7

Measurement Circuit 6a
tsUSTA
Set-up time (start)
tHDSTA
Hold time (start)
tHIGH
H-pulse width (clock)
tLOW
L-pulse width (clock)
tSUDAT
Set-up time (Data transfer)
tHDDAT
Hold time (Data transfer)
tSUSTO
Set-up time (Stop)
tauF
Bus free time
tF
Fall time
tR
Rise time
Above times are referenced to VIH and VIL values'

12C Bus Time Diagram

0100-8

Measurement Circuit 6b

lOkR

SCL

Is

150Q

V,o--- .................... 60 K/W

Port Output P1 (V 11)' ............. - 0.3V to + 16V
Port Output P2 (V12) .............. -0.3V to + 16V

Operating Range

Port Output P3 (V13) .............. -0.3V to + 16V

Supply Voltage (Vs) .................. 4.5V to 5.5V

Port Output P4 (V14) .............. -0.3V to + 16V

Ambient Temperature (TA> .......... O·C to + 70·C
Input Frequency (f15) ......... 16 MHz to 1300 MHz

Signal Input UHFIVHF (V15) ........ - 0.3V to + 3V

Crystal Frequency (fs. 7) ................... 4 MHz
Divider Factor (N) ................... 256 to 32767

Characteristics Vs = 5V; TA = 25·C
Parameter
Current Consumption, Vs

Symbol

= 5V

Crystal Frequency
Series Capacity 18 pF

Test
Circuit

Is

1

fS.7

1

Limits

Units

Min

Typ

Max

20

50

70

rnA

4

MHz

Input Sensitivity UHF/VHF
f15
f15
f15

= 80 MHz-100 MHz
= 100 MHz-1000 MHz
= 1300 MHz

Input DC Voltage
UHFIVHF and REF not connected

a15

2

-24/14

3/315

dBm*

a15

2

-27/10

3/315

dBm*

a15

2

-15/40

3/315

dBm*

V15

2

2

Band Selection Outputs P1-P4 (Current Sinks with Internal Resistance RI

= 13.5V
= 12V

= 12 kG)

Leakage Current, V11 H

I11H

3

10

IlA

Sink Current, VllL

111 L

3

0.7

1.0

1.5

rnA

Pump Current Lock In

110

5

±90

±150

±220

IlA

Output Voltage Lock In

V1C

5

1.5

2.5

V

Leakage Current Lock In

110

5

-0.2

0.2

IlA

Ig

5

500

Phase Detector Output PD Vs

= 5V
,

Active Filter Output VD
Output Current, Vo

= 0.8V

IlA

7-55

SDA 3203

Characteristics Vs = 5V; TA = 25°C (Continued)
Parameter

Test
Circuit

Min

V1H

6

:3

Vs

V

V1L
11H
11L

6
6
6

0.8
50
-100

V
p.A
p.A

V2L

6

0.4

V

V2H
12H

6
6

5.5

V
p.A

Symbol

Limits
Typ

Units
Max

Test Input TEST1
Input Voltage
Input Current
V1H = 5V
V1L = OV

Test Output CLOCK, DATA (Open Collector)
Output Voltage. 12L

= 1 mA

Leakage Current
V2H = 5V

10

Output 62.5 kHz (Current Sink with Open Collector)
Output Voltage
Output Current

V20
120

4
4

0.4
100

5.5
200

V
p.A

V2H
V2L

6
6

3

Vs
0.8

V
V

12H
12L

6
6

50
-100

p.A
p.A

Set-Up Time DATA

tsUDAT

6

2

p.s

Hold Time DATA

tHDDAT

6

2

p's

tHIGH

6

2

p.s

tSUEN

6

2

p.s

tHDEN

6

2

p.s

Bus Input CLOCK, DATA, ENABLE
input Voltage
Input Current
V2H = 5V
V2L = OV

Data Transfer

CLOCK
H-Pulse Width CLOCK

ENABLE
Set-Up Time ENABLE
Hold Time ENABLE
'Listed as mVrms with 50n.

7-56

SI;)A 3203

Measurement Circuit 1
1~8~l~,~__~________~__,--~
~pF

+-::=;:-:;::=t:=:::
+-

CrystalOadlt.tor

10 Reference
Divider

QI

18pF:c
~MHz=

Q2

-4-________~_ _ _ _ 6ND

1~6______

0101-2

Measurement Circuit 2
Calibration of Signal Generator

0101-3

Measurement of Input'Sensltivlty

.sv
18
IS
17

SO.., 3203

"}snF

16
GND
010t-4

Test Mode 2

'No Cable

Measurement Circuit 3

Measurement Circuit 4

.

20

I"

IsDn

VlO<>-----:::;::::J-~

0101-5

Valid for P1-P4

0101-8

62.5 kHz Output

7-57

SDA 3203

Measurement Circuit 5
I~

10

IS0R

v,P-~~--~r----,

lua

I,

v,

150R

'
0101-7

Charge Pump Outputs PO, VD

Measurement Circuit 6a
12C Bus Time Diagram
90%

Data

Clock

0101-8

tsUEN
tttDEN
tHIGH
tsUDAT
tHDDAT

Set-Up Time (Enable)
Hold Time (Enable)
H Pulse Width (Clock)
Set-Up TIme (Data Transfer)
Hold TIme (Data Transfer)

Measurement Circuit 6b

Test 1
Enable

150Q

V,G----C:J-{

Clock
.Data

v,o----C::r,.....{

0101-9

7-58

SDA3203

Application Circuit
Tuner

"F
lose

1nF

Vs

)------jVo

PLL
SDA 3203

GNO

Clock

Data
Enable

Loop Filter

L---+_ _ _ _---'

computation for Loop Filter'
Ip x Kvco
C1 xPXN
= 0.5 X CIlR X R X C1

Loop bandwidth: CIlFi =
Attenuation:
P
N

Ip
Kvco
R, C1

=
=
=
=
=

~

Prescaler

W

0101-10

Example for Channel 47
P = 8; N = 11520;.lp = 100 IlA;
Kvco = 18.7 MHz/V; R = 22 k.n;
C1 = 180 nF; CIlR = 336 Hz;
fn = 54 Hz; ~ = 0.67

Standard Dimensioning: C2 = C1/5

Progr. Divider
Pump Current
Tuner Slope
Loop Filter

7-59

SDA 3203

Pulse Diagram
,

2

3

4

5

6

7

a

9

m

H U

a a

~

~

fl

a

CICKk
Data

Enable

Jr---------------------,L
0101-11

N = n13 X 8192 + n12 X 4096 + n11 X 2048 + n10 x 1024 + n9 x 512
n8 x 256 + n7 x 128 + 'n6 X 64 + n5 x 32 + n4 x 16 + n3 x 8 + n2 x 4
n1 x 2 + nO
Example: N = 11508
Band Selection
P1-P4 = 1 Current Sinks are Active
VCO (Tuner) Frequency fveo = 8 x N X 7.8125 KHz
Example: fveo = 719.25 MHz
TVSAT = N.C. Bit 4 is P1
TVSAT = OV Bit 4 is n14
Divider Ratio

Ordering Information
Type

Ordering Code

SDA3203

Q67000·A2526

7·60

+
+

SIEMENS

SDA 3252
1.3 GHz-PLL with Digital Tuner Alignment
Pin Configuration

Pin Definitions
Pin

(Top View)

2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20

0098-2

Function
Supply Voltage VS2 (5V)
Signal Input RF
Band Selection Output BW1
Band Selection Output BW2
Band Selection Output BW3
Phase Detector Output PD
Tuning Output V03
Output Active Filter Vo
Tuning Output V02
Tuning Output V01
Supply Voltage VS1 (33V)
Bus Input/Output SDA
Bus Input SCL
Crystal 02
Crystal 01
Port Output PO
Port Output P1
Port Output P2
Port Output P3
Ground (GND)

Combined with a VCO (tuner). the SDA 3252 comprises a digital programmable phase looked loop for television devices designed to use the PLL frequency synthesis tuning principle.
The PLL provides:
• The tuner oscillator with a crystal-stable frequency between 16 MHz-1300 MHz providjng a 62.5 KHz raster.
as well as a 2.4 GHz pre-scaler 1:2 for TVSAT applications. providing in this case a 125 KHz raster

@Siemens Components. Inc.

7-61

May 1988

~

(I)

~

N

~

III

I}o

} RF

-[>{~.~
P=8

1/16 or
1117

~

&",.

01

OSC

4

02

4 MHl

11

rMHz
L..--

H

Dlvlde,_
Q = 512

P

SCl

11 SOA

y

48,1 Swallow
Counl.,

VS2 (5V)

,.

~

11 B,I MaIn
Counter

~

II

I

LATCH I

TO(T... laleJ

II
II

IL H

LATCH 4
Pori mform.lIIO"

II
LATCH]
Controllnformdtlon

LL-

6 BIT-BUS

T

I

r==9

fiii

LK

3

rVQ

LalchS

,------J

F=f

BBIT-BUS

II

Control

'"

_IJI1WN

L-'--

divider ratio

VSl (33V)

liP

I-~

pha.e

0'
~

"

Vo

.~ /~

frequency

comparator

'.tt'

latthlmpul\t'

12C-8US

II

78125kHz

LATCH 2
diVider r allo

a

to

PO

11128
-11136

i
18p 15

GNO

II

latch6

~
llm+
OACl

OAC

2

-nn..-

r---1

H

latch7

OAC3

••••••

f-

~"

~.
v(U

"

r ~~I

IOI,I}IJ 1415

I
R,,,I

L.I(h rmpul~

'It-'
aWl

HWI

J

PO PI

.WI

•

~

CY'I

P~~P P

.t."

118

TlICylf,.,)

voIlage
gener I

L

Un."

I,.
0098-1

g
w

~

SDA 3252

Description of Functions,
Applications and Circuitry
Functions and Applications
Combined with a VCO (tuner), the SDA 3252 comprises a digital programmable phase-locked loop for
television devices designed to use the PLL frequency synthesis tuning principle.
The PLL provides the tuner oscillator with a crystalstable frequency between 16 MHz-1300 MHz providing a 62.5 KHz raster, as well as with a 2.4 GHz
prescaler 1:2 in the TVSAT range, providing in this
case a 125 KHz raster. The three outputs V01, V02,
and V03 control the vector diodes of the circuitry.
These tuning voltages differ from the oscillator tuning voltages by a programmable amount. The tuning
process as well as the difference between the tuning
voltages are controlled by a microprocessor via an
12C bus.
Operating voltage Vs = 5V.

Description of Circuitry

PO, Vo

output transistor at VD, and RC combination) integrates the current pulses as the tuning voltage for the VCO.
With the control bit 51 the pump current can be switched between two
values per software. Through this
switch-over, the control characteristics of the PLL during lock in can be
changed, i.e., varying tuner characteristics in the various TV bands can
be adjust.
BW1 ... BW3 The software-controllable band selection outputs BW1, BW2 and BW3
can drive external PNP transistors
operating as band selection switch
(internal current limiting).
PO ... P3
PO, P1 and P3 are open collector
output which can be used for a variety of applications.

V01, V02, V03 The circuitry for the digital tuner
alignment includes three digital-toanalog converters and a logic circuit
which can store three B-bit information. Six of these bits are forwarded
to one digital-to-analog converter
each. The three output magnitudes
are added to the tuning voltage Vo.

Tuning Section (See Block Diagram)
RF

The tuner signal is capacitively coupled at the RF input and amplified.
Subsequently, the signal passes
through an asynchronous divider
with a fixed ratio of P = 8, and an
adjustable divider N = 2546 ...
32767. The signal is then compared
in a digital frequency phase detector
with a reference frequency fref =
7.8125 KHz. This frequency has
been derived from a 4 MHz crystal
oscillator (Pin 01, 02) by dividing its
output Signal by 0 = 512.
The phase detector includes two outputs UP and DOWN which control
the two current sources I + and 1of a charge pump. If the negative
edge of the divided VC signal. occurs
prior to the negative edge of the reference Signal, the current source I +
will pulsate for the duration of the
phase difference. However, during
the reversed sequence of the negative edges, current source 1- will begin to pulsate. If both signals are in
phase, the charge pump output PO
changes into the high-impedance
state (PLL in lock). An active low
pass filter (internal amplifier, external

12C-BUS-lnterface
The PLL (output VD) and the alignment of the tuner circuitry (outputs
V01, V02, and V03) are accessed via
two separate addressed which are
injected via common interface SCL,
SDA.
Data bytes can be read in any number and order after the respective address bytes input for PLL-tuning
function or for digital tuner alignment.
12C-BU8-lnterface for PLL-Tuning Section
(Outputs, V01, V02, and V03)
SCL,SDA

The processor and the PLL exchange information via an asynchronous, bi-directional data bus. The
clock is always supplied by the processor (input SCL). Pin SDA operates
as input or output depending on the
direction of the data stream (open
collector, external pull-up resistor).
The data from the processor passes
through an 12C bus control. Depending on their function, the data are
subsequently latched in registers
0-3. If the bus is not in the busy
state, both lines are in the marking
7-63

SDA 3252
state (SOA, SCL are high). Each telegram begins with the start conditions
of SOA returning to LOW, while SCL
remains in HIGH. All additional information is transferred during SCL =
LOW, and the data is forwarded to
the control with the positive clock
edge. However, if SOA returns to
HIGH, while SCL is in HIGH, the telegram is ended since the PLL acknowledges a stop condition.
In what follows the "logical allocation" table is used as basis.
All telegrams are, transmitted byteby-byte, followed by a 9th clock
pulse, while the control returns the
SOA line to LOW (acknowledge condition). The first byte comprises 7 address bits. These are used by the
processor to select the PLL from
several peripheral components (chipselect). The 8th bit is always LOW. In
the data portion of the telegram, the
first bit of the first or third data byte
determines whether a divider ratio or
a control information is to follow. In
each case, the second byte of the
same data type or a stop condition
has to follow the first byte.

12C-BUS-lnterface for Digital Tuner Alignment
(Outputs V01, V02, and V03)

VS2,GNO

Each data transfer begins with a
START condition: SOA goes to LOW,
while SCL remains HIGH.
The data is accepted with a positive
clock edge and transferred byte-bybyte. Each byte requires nine clock
pulses. During the first eight pulses,
the data is transferred, and during
the ninth clock pulses the addressed
component 'generates an acknowledge signal (ACK). (The SOA line is
returned to LOW.) The first byte after
a start condition contains the component address.
The subsequent bytes contain the
sub-addresses for the three digitalto-analog converters (07, 06) and
the 6-bit information which determines the (analog) voltage value (05
. . . ~O). The data transfer is ended
with the STOP condition. SOA goes
to HIGH, while SCL remains in LOW.
Subsequently, SCL returns to HIGH
as well.
A POWER ON RESET circuitry prevents SOA from going into LOW and
blocking the bus, when the supply
voltage VS2 is injected.

Description of Functions, Applications and Circuitry
Logical Allocation-PLL Alignment
MSB

LSB

Address Byte

0

0

0

0,

'

0

J!.CK

Prog. Divider
Byte 1

0

n14

n13

n12

n11

n10

n9

n8

ACK

Prog. Divider
Byte 2

n7

n6

n5

n4

n3

n2

n1

nO

ACK

51

T1

TO

0

ACK

P2

P1

PO

BW1

ACK

Control Info.
Byte 1
Control Info.
Byte 2

P3

X

BW3

BW2

Divider Ratio:
N = 16384*n14 + 8192*n13 + 4096·n12 + 2048·n11
64*n6 + 32*n5 + 16*n4 + 8·n3 + 4·n2 + 2·n1

7-64

+
+

1024·n10
nO

+

512·n9

+

256·n8

+

128·n7

+

SDA 3252

Description of Functions, Applications and Circuitry (Continued)
Band Selection:
BW1 ... BW3 = 1 Current Sink is Active

Pump Current Switch-Over:
51 = 1
High Current

Port Outputs:

Test Mode:

P3 ... PO=1

Open Collector Output is Active

T1, TO = 0,0
T1 = 1

Standard Operation
P2 = fref; P3 = Cy
TAl-STATE Charge Pump

TO = 1

MSB

LSB

o

Address Byte

o

o

o

o

Address
Data Byte

07

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
1
1

06

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
1
0
1

05

o
o

o

ACK

AJW

04

03

02

01

DO

ACK
OffsetSpg./V

o

o
o

o
o

o
o

o

-2.650
-2.566

1

-0.084
0.000
+0.084

o

etc.

o

1

o
o

1

o
o

1

1

o

o
o

o

o
o

etc.

+2.566
OJ A-Converter 1
OJ A-Converter 2
OJ A-Converter 3

X

X

X

X

X

X

7-65

SDA 3252

Absolute Maximum Ratings·
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Range T U = 25·C

Pos

Parameter

1

Supply Voltage 1

Symbol

Min

Max

Units

-0.3

+36

V

2
3

Supply Voltage 2

VS2

Output PO

Vpo

-0.3

+6

V

-0.3

VS2

4

Crystal 01

V01

V

-0.3

VS2

5

Crystal 02

V

V02

-0.3

VS2

6

Busl/OSDA

V

VSOA

-0.3

+6

7

Bus Input SCl

V

VSCl

-0.3

+6

8
9

Port Input P3

V

VP3

-0.3

+16

Port Input P2

V

VP2

-0.3

+16

V

10
11

Port Input P1

VP1

-0.3

+16

V

Port Input PO

VPO

-0.3

' +16

V

12

Band Selection BW3

VSW3

-0.3

+16

V

13

Band Selection BW2

VSW2

-0.3

+16

V

14

Band Selection BW1

VSW1

-0.3

+16

V

15

Signal Input RF

VHF

-0.3

+2.5

V

16

Output Active Filter Vo

VYO

-0.3

VS1

V

17

Output V01 ... V03

VY01. UY02. UY03

-0.3

VS1

V

18

Bus Output SDA

ISOAl

-1

+5

mA

Open Collector

19

Port Output P3

IP3l

-1

+5

mA

Open Collector

20

Port Output P2

Ip2l

-1

+5

mA

Open Collector

21

Port Output P1

Ip1l

-1

+5

mA

Open Collector

22

Port Output PO

IpOl

-1

+5

mA

Open Collector

23

Output Current

I(V01 2 3)

1

mA

(Short Circuit)

24

Chip Temperature,

(Tc)

+125

·C

25

Storage Temperature
Thermal Resistance:

Ts

+125

·C

26

System-Air

(RthSU)

56

K/W

VS1

-40

Remarks

Functional Range
Within the function range integrated circuit operates as described; derivations from the characteristic data are
possible

Pos
1

7-66

Functional Range
Supply Voltage 1

Symbol

Conditions

Limits

Units

Min

Max

VS1

+31.5

+36

V

2

Supply Voltage 2

VS2

+4.5

+5.5

V

3

Ambient Temperature

Tamb

0

+70

·C

16

1300

MHz

4

MHz

4

Input Frequency

fRF

5

Crystal Frequency

fCrystal

6

Divider Factor

N

256

32767

-

SDA 3252

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not stated otherwise. typical characteristics will
be apply at T amb = 25°C and mean supply voltage.
Characteristics of the Operating Range: VS1 = 33V. VS2 = 5V. Tc = 25"C
Pos

Parameter

Symbol

Conditions

Limits

Test
Min

Typ

Units
Max

1 Current Consumption 1 IS1

5

4

rnA

2 Current Consumption 2 IS2

2

60

rnA

3 Output Voltage

Vo. V01.2.3

5

4 Tuning Voltage
• ·See Definition 1

AV01. 2. 3

5

5 Temperature Deviation
of Tuning Voltage in
Temperature Range
··See Definition 2
6 Crystal Frequency

27.5

V

±2.5

±2.65 ±2.8

V

-60

+60

mV

4

MHz

0.3

5

fCrystal

Series Capacity 18 pF

2

Input Sensitivity
1 -27/10
= 80 MHz-500 MHz
= 500 MHz-1000 MHz 1 -24/14
9
1 -15/40
fRF = 1200 MHz
aRF
Band Selection BW1-BW3 (Current Sink with Internal Resistance RI = 12k)
10 Leakage Current
3
Vew = 13.5V
lew
11 Sink Current
3
0.7
Vew = 12V
lew
7

aRF

fRF

3/315 dBml*

8

aRF

fRF

3/315 dBm/·
3/315 dBm/·

1

10

p,A

1.5

rnA

Port Outputs PO-P3 (Switch with Open Col/ector)
12 Leakage Current
13 Residual Voltage

UP1H

4

10

p,A

VP1L

Ip1L

4

0.5

V

Phase Detector Output PO (Vs
14 Pump Current

= 13.5V
= 1.7mA

Ip1H

= 5V)
= HIGH; Vpo = 2V
= LOW; Vpo = 2V

IPOH

51

15 Pump Current

IpOH

51

16 Output Voltage

VPOL

Lockin

5

±90

±220 ±300

p,A

±50

5

±22

±75

p,A

5

1.5

2.5

V

6

3

5.5

V

1.5

V

Bus Inpu~ SCl, SDA
20 Input Voltage

VSClH

21

VSCll

22 Input Current

ISClH

23

ISCll

6

= US2
VSCll = OV

6

50

p,A

6

-100

p.A

VSCLH

Output SDA (Open Col/ector)
24 Output Voltage

ISOAH

VSOAH = 5.5V

6

10

p.A

25

VSOAl

ISOAl = 2mA

6

0.4

V

Edges SCl, SDA
26 Rise Time

TR

6

1

p,s

27 Fal/Time

TF

6

0.3

p.s
7-67

SDA 3252

Characteristics (Continued)
The listed characteristics are ensured over the operating range of the integrated circuit Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
be applied at Tamb = 25°C and mean supply voltage.
Characteristics of the Operating Range: VS1 = 33V, VS2 = 5V, Tc = 25°C
Pos

Parameter

Symbol

Conditions

limits

Test
Min

Typ

Units
Max

Shift Register Clock SCl

28

Frequency

fSCL

6

0

29

H·Pulse Width

THIGH

6

4

100

KHz
p.s

30

L·Pulse Width

TLOW

6

4

p.s

31

Set·UpTime

TSUSTA

6

4

p.s

32

Hold Time

THDSTA

6

4

p.s

33

Set·UpTime

TsUSTO

6

4

p.s

34

TOffTime

TBUF

6

4

p.s

Start

Stop

Data Transfer

,

,

35

Set· Up Time

TSUDAT

6

0.3

p.s

36

Hold Time

THDDAT

6

0

p.s

. ..

a VOl = VOl - Vo
aV02 = V02 - Vo
aVD3 = VD3 - Vo
'Unit in mVrms @ 500
"Not more than 1 driver will be driven simultaneously.

Definition 1:

...

Deflnltion,2: Reference Voltage VOl, 2, 3 @ 25°C

Internal Circuit (Crystal Oscillator)

....--..-------1------..----VS2

....-:.----~=:::;==~-r-..
+-__•

toRef
dev,d.r

~--~~--------~--~----GNO

7-68

SDA 3252

Measurement Circuit 1
Signal Generator Calibration

r

gna
~enerator
'
OOhm

jI

.

I:::nuatlon L
I 'Ink

Q

I

Output
measure-

mentdevoce
50 Ohm
0098-13

Input Sensitivity Measurement

?V

f..-

lSlgna,
I
~enerator
OOhm
I

6dB
attenuation nF
1
I"nk
•

v"
HF

~~ti

P5

H

frequency
counter

I

G~O
Test Mode: T1 = HIGH

·without cable.

0098-'

Internal Circuit 4
(Port Output PO, P1, P2, P3)

Internal Circuit
(Band Selection BW1, BW2, BW3)

V~2

30k

....-5
....-6

Internal Circuit 5 (Outputs PO, VD, VD1, 2, 3)
V'D

.... -7

7-69

SDA 3252

Internal Circuit (Bus Input SDA, SCl)
12C-BUS-Time Diagram
TBUF

-'\JSTO

TSUOAT

I,DATA TRANSFER

-

-

THOOAT

I

0098-.

TSUSTA
Setup Time (Start)
Hold Time (Start)
THDSTA
THIGH
H-Pulse Width (Clock)
L-Pulse Width (Clock)
TLOW
Set-Up Time (Data Transfer)
TSUDAT
THDDAT
Hold Time (Data Transfer)
Set-Up Time (Stop)
TSUSTO
TSUF
TOffTime
Fall Time
TF
TR
Rise Time
Above times are referenced to VIH and VIL values.

SCL,SDA

I
I

~
7-70

10k

+-

only for SOA

....-.

SDA 3252

Application Circuit

"

Q.

0'

Q,

'0

Vo

22_

180n

VSZ (SV)

Vo

GND
V,.

VSI (nv)

VOl

PLL

SDA3252
VOl

VOl

(DIP 20)
SCL
SDA

VOl

VOl

from

IlC

12V
aWl aW3
aW2
22k

0098-10

7-71

SDA 3252

Tuner Section Pulse Diagram
Telegram Samples
••.•....•..••••.•Address'ng •••••••••.•.••..••••..••..•.I·ACK·I·-········2.Byte··········I·ACK·I···········N BVle··········I·ACK.'

START

vOlA

vOlA

' - -_ _ _ _ _ _ _ _-'---l=;;.&..--&. -

'SDA

}"i3i]

IMSB'

,-

JilJ9LJ1lJ2L _

SCL

STOP

~.D/A
LSB
8

9
0098-11

··············-·····Addreosing···············-·····.······-I-ACK·I····I.Byte····I·ACK·'··-2.Byte·····'·ACK·/····3 Byte····I·ACK·'···-4.Byte •••.'·ACK·1

'-------ICL--- ~

C

~

.C

~

C

~

I

SLJLJl SLJLJl SLJLJl JlJlJ
START 1

2

3

4

5

6

7

8

8

9

9

8

9

8

9

8

9 STOP
0096-12

Telegram Samples
Start·Adr·Tv1·Tv2·St1-St2-Stop
Start-Adr-Sn-St2-Tv1-Tv2-Stop
, Start-Adr-Tv1-Tv2-St1-Stop
Start-Adr-St1-St2-Tv1-Stop
Start-Adr-Tv1-Tv2-Stop
Start-Adr-St1-St2-Stop
Start-Adr-Tv1-Stop
Start-Adr-St1-Stop

Ordering Information
Type

Order-Nr.

SDA3252

Q67000-AB039

7-72

Start
Adr
Tv1
Tv2
St1
St2
Stop

Start Conditions
Addressing
Divider Ratio 1 Byte
Divider Ratio 2 Byte
Control Word 1 ,Byte
Control Word 2 Byte
= Stop Conditions
=
=
=
=
=
=

SIEMENS

SDA4212
Divider 1:64 I 1:256 up to 1.3 GHz
Preliminary Data
Type
SDA4212

! Ordering code
Q67000-A8049

Package
P-DIP8

The SDA 4212 has been designed for application in television receivers operating according
to the frequency synthesis tuning principle. It includes a preamplifier and an Eel divider
stage with symmetrical Eel push-pull outputs. It can be operated with a divider ratio of
1 : 64 or 1 : 256.
The operating range of the Ie extends to an input frequency of 1.3 GHz.

Features
• Pin programmable divider ratio of 1 : 64 or 1 : 256
• Symmetrical push-pull input
• low harmonic wave
• Minimal current consumption of 23 mA
Circuit Description
The preamplifier of the component has been designed with symmetrical push-pull inputs.
During the asymmetrical drive of one of the inputs, the other input has to be disabled to
ground by a capacitor (approx. 1.5 nF) of low series inductance.
The divider stage of the component is comprised of several status-controlled master':'slave
flipflops. Their divider ratio can be set with the switch-over input M as follows:
Mto Vs=1 :64
M to ground = 1 : 256
The symmetrical push-pull outputs of the divider include an internal resistor of 500 Q each.
The DC voltage level at the outputs is connected to the supply voltage Vs (output "High" = Vs).
The typical voltage swing is 1.0 V (peak-to-peak).

7-73

SDA4212

Maximum Ratings
min

max

Unit

-0.3

6

V

Supply voltage

Vs

Input voltage (peak-to-peak)
(pin 2, pin 3)

V;

2.5

V

Output voltage
(pin 6, pin 71
OutPUt current
(pin 6, pin 7)

Vq

Vs

V

-Iq

10

mA

Input voltage
(pin 5)

VM

-0.3

Vs

V

Junction temp~rature
Storage temperature range

7j
Ts1g

-55

125
125

°C
°C

Thermal resistance
System-air

RthSA

115

K/W

Overload resistance1)
(ESO protection single
discharge of 220 pF
capacitor through a 1 kQ
resistor to each pin)

VMOS

-600

1000

V

Vs
fi

4.5
70
0

5.5
1300
70

V
MHz

Operating Range
Supply voltage
Input frequency
Ambient temperature

1) not required pins float; pin 4 always to ground

7-74

TA

·

°C

SDA 4212

Charactericstics
Vs =5 V; TA =25°C
Test
circuit
Current consumption
inputs decoupled outputs enabled;
M enabled

Is

Input level
("input sensitivity")
70 MHz
80 MHz
120 MHz
250 MHz
600 MHz
1000 MHz
1100 MHz
1200 MHz
1300 MHz

Vi

Output voltage swing
(peak-to-peak)
CL S:15 pF; fS:l000 MHz

min

1
1
1
1
1
1
1
1
1

-26/11
-27/10
-30/7
-32/5.5
-27/10
-27/10
-22/18
-15/40
- 9/80

Vq

1

0.4

DC voltage offset of outputs

.!lVq

3

M-input current "Low"
(divider ratio 1 :256)
M = ground

1M

1

M-input current "High"
(divider ratio 1 :64)
M=Vs

1M

1

M-input voltage "High"
M-input voltage "Low"

VMH
VML

1
1

Amplitude of the 3rd
harmonic at output
(referenced to 1st harmonic)
f = 700 ... 900 MHz; M=Vs

83

1.4
2.4

typ

max

Unit

23.5

29.5

mA

3/315
3/315
3/315
3/315
3/315
3/315
3/315
3/315
3/315

dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV
dBm/mV

0.6

V

100

mV

2

100

IlA

a

50

IlA

0.2

V
V

3

-30
-:35

•

dB
dB

7-75

SDA4212

Block Diagram
Vs

8
VREF
N.C.

1

7

11

2
1: 64

6

1: 256
12

4
GND

Pin Definitions
Pin

Function

1
2
3
4
5
6
7

Not connected
Inputl1
Inpl!t 12
Ground
Switch-over input M for divider ratio
Output 02
Output 01
Supply voltage Vs

7-76

Q2

3
5

8

Q1

M

SDA4212

Measurement Circuit 1
Calibration of Signal Generator

Signal
Generator

Output
Measurement
Device

6dB
Attenuator

50Q

50Q

• no cable

Measurement of Input Sensitivity and Output Voltage Swing

r-

I
I
I
I
I

I100nF

B
Signal
Generator

50Q

*

6dB
Attenuator

1,5 nF V

11

*

2

7 Val

3

6 V02

Spectrum
Analyser

Frequency
Counter

tI

I
I
+Vs I
I

OSCilloscope

4
liSPF lClead
• no cable

1.1

.1

Clead + capacitance

of the measurement
devices - 15 pF
(For output voltage
swing measurement)

7-77

SDA 4212

Measurement Circuit 2
calibration of Signal Generator

Signal
Generator

6dS
Attenuator

500

/--+-..,

Output
Measurement
Device .

SOQ

• no cable

Measurement of Input Sensitivity and Output Voltage Swing

Spectrum
Analyser

Frequency
Counter

Signal
Generator

500

*

6dS
Attenuator

1,S nFv

*

11

2

r--......;.-+-----i>---i

3

6

4

1
"0

7·78

cable

Oscilloscope

VQ2

1I
6 pF

Cload

Cload + capacities of the
measurement devices - 56 pF
(for output voltage swing
measurement)

SDA4212

Measurement Circuit 3

I,oonF
T

-L

B
VI'

+ Vs

2

7

Va,

3

6

Va2

4

r,·snF

+Vs

-1

Voltmeter

I.

1

Note: press key T until outputs turn over

7-79

Front View

~

Rear View

~

Q.

i

0

CD

3:

m

In

~~

7

g...

c

- ..

Vs

Test
Jack for
Connection of
Probe
2pF;10MQ

3:

m
In

c

i

3
~

..9.

3

~

Q

g

;:;:
.j:o

...

Co)

Q.

~

:I:

...

\IJ

3

0

~

1

1
Bright areas: copper-clad
Dark areas: with etched lining
Double-clad PC board, terminals through-contacted

I

n'

6 dB Attenuation
To Transmitter

en

g
~

~

N

SIEMENS

TDA4282T
Quasi-Parallel Sound IC with FM IF,
Sym. Input and Volume Control
The TDA 4282 T is a controlled AM amplifier with FM demodulator (to produce an intercarrier)
and subsequent sound-IF limiting amplifier with coincidence demodulator, standard VCR
connection and separate AF-output with volume control.
• Outstanding limiting qualities
• Connection for video recorder
• Little external circuitry

Maximum ratings
Supply voltage

Vs
Vs

t.r;; 1 min
Thermal resistance (system-ambient air)
Junction temperature
Storage temperature

R'hSA

7;
Tstg

15
16.5
65
150
-40 to 125

V
V
K/W
°C
°C

11 to 15
10 to 60
0.01 to 12
Oto 5
0.3 to 1
Oto60

V
MHz
MHz
V
mA
°C

Operational range
Supply voltage
Frequency range AM part
FM part
Control voltage AM part
Switch current FM part
Ambient temperature in operation

Vs
tAM
tFM

V2
18
T.mb

7-81

TDA 4282 T

Characteristics (VS

= 15V, Tamb = 25°C)
min

Current consumption

Is

typ

max

60

80

mA

AM-part:
AGC-range
AGC-voltage
Input resistance
Input impedance at max. gain
at min. gain
Output resistance

FM-part: (fz

= 5.5 MHz; fmod = 1 kHz)

Input impedance
AM-suppression
(V,9.10 = 1 mV; f= 12.5 MHz; m = 30%)
Signal-to-noise ratio (V,9.10 = 10 mV)
Input voltage for limiting
(.1 f = 30 kHz)
Demodulator output resistance
Output re~istance for VCR-recording
Input resistance for VCR-playback
Integrated resistor for deemphasis
AF-.output voltage
(V, ~ 10 mV; with CDA 5.5 MC 10, Rq 11 = 2.90)
(.1 f = 12.5 kHz)
AF-gain during VCR-playback
Total harmonic distortion
Cross talk (V, = 1 mV)
V,2 = 2 V,ms
V,2 = 0.3 V,ms
Range of volume control.

7-82

10
1.8/2
1.9/0
500
500

dB
V
kO
kO/pF
kO/pF
0
0

800
42

0
dB

V,lIm

85
60

dB
!-IV

Rq,S.,6

5.4

.1G
V2

55
0

R i3""
Z,20.21
Z,20-21
Rq6
Rq7
Zi9.10
BAM

BS/N

Rq12
R,'2
R17
Vq12
Vq11

VAFma•
VAFmln

10
600
300

kO
0
kO
kO
mV,ms
mV,ms

0.5
1

%

52
65
85

dB
dB
dB

500
10

260

VI2 .
"
THD'2

C,2-"
C,2-,1

5

50
60
70

TDA 4282 T

Circuit description

The TDA 4282 T contains essentially two functional blocks:
1. A regulated AM amplifier with a peak rectifier to generate the AGC voltage. The AM
amplifier drives an FM demodulator, at the output of which the differential sound carrier
(38.9 MHz-33.4 MHz = 5.5 MHz) is available. The double sideband portions close to the
carrier are suppressed. The 5.5 MHz carrier reaches the functional block via an external
selection.
2. An FM limiter amplifier with coincidence demodulator, a standard VCR connector and
a separate AF output with volume control.

Pin assignment

Pin No.
1

2
3
4

5
6
7
8
9
10
11
12
13
14

15
16
17
18
19

20
21
22

Pin designation
Ground
AM-IF control
AM amplifier demodulator
AM amplifier demodulator
Supply voltage (plus)
AM amplifier sound carrier output IT 1
AM amplifier sound carrier output IT 2
AM-IF amplifier negative feedback for working point
AM-IF amplifier negative feedback for working point
FM-IF amplifier IF input
AF output
VCR connection
FM-IF amplifier emitter follower output
FM-IF amplifier emitter follower output
FM amplifier demodulator
FM amplifier demodulator
Deemphasis condensator
Volume control
AM-IF negative feedback for working point
AM-IF amplifier IF input
AM-IF amplifier IF input
AM-IF negative feedback amplifier for working point

•

7-83

......

t

v

CD

1:1

IL-..

<>------..

0'
n

CQA 5.5M( 10

0-4.8V

~

VqVCR

~

..

;'

180pF

VC
21

120

119

118

14.7nF
117

116

mf-J

14

15

ea

III

13

:I

1..

III

...=
~

CD

~

n

~'

c

;:;:

470Q

I

7

I

0.5 II F

~
38.9 MHz

B

r-:r
22nF

1 1

+Vs

TT1

TT2

'pO

1"

"I'" 22n~

~ SFE ~5MB

--t

g

1

+VVCR

VqAF

-1mA

it
CIO
N

-~

+VAV

-t

»

'C

V.V(R

'2.

..

ii'
III

0'

::I

r--------l

:---U:
I
I
I ---

I

••

I

L __

68k12

;:;:

TDA 4282 T

I
I
I

21

31

41

;HH:
'TI~I

o5~F 1.

I

____ JI

22k12

I
L~_-':"......J

Dl0 N

,

II

0

61

I

7

L -_ _

~

•

0 V,AF

112k\l

10k12

11lH

b
.
TT' TTZ)

.

...ilQo-n,)·

~100nF
47k12

51

I

22k12

• Vs

~.

C

11
I

n

12

T

~Vv'deo
15012 (pas)

I

: 91l H

15

-rl00nF
14 13

D 10 N

,..----------,
1.-- -,

1nF

TDA 5610

r-----t~--I

:

i 4312

V'IF~t~~t~

~

.1

Irs=:'"

11.1

.1

.1.1.1.1

I

I

I
I

:

19l.!__ fj.11iU~j __ !~j

.....
.,. .

7.SIlH

.l.
47k12

-f
C

»

t

&:

UI

V.wltch fromVCR

(record i ng OV
ploy bock:.1Z V)

!'cont IF

v.ont Tuner

AGC threshold

5 Vpp H AFC ON/OFF

~
-f

SIEMENS

TDA 5400-2
Video IF IC with AFC
The high gain, controlled video IF amplifier with controlled demodulator includes lowimpedance outputs for the positive and negative video signal, gated control as well as
delayed tuner control and an AFC output.
TDA 5400-2: for PNP tuners

Features

•
•
•

High degree of integration
Extensive control range
High input sensitivity .

Maximum ratings
Supply voltage
Junction temperature
Storage temperature range
Thermal resistance (system-air)

V

Ts1g

16.5
150
-40 to 125

R1hSA

70

KlW

Vs

10 to 15.8
15 to 75
Oto 70

V

Vs

Tj

DC
DC

Operational range
Supply voltage
IF frequency
Ambient temperature

flF
TA

7-86

MHz

DC

TDAS400-2

Characteristics
Vs =13 V; TA =25°C
Current consumption
Stabilized reference voltage
Control current for tuner
V16 =0.5 V13
Tuner AGC threshold
Gating pulse voltage
pos. gating pulse
neg. gating pulse
Input voltage at Gmax
1V3=3Vpp
AGC range
IF control voltage
Vmax
Vmon
AFC output current
AFC switching
Vs=Vg;R=10 kO
Vs=Vg;R=oo
AFC direction
di/df> 0
di/df< 0

OFF
ON

Video output voltage (pos.)
RL = 0 0
Sync pulse level
DC voltage V2 = 4 V; V17J1S = 0
Output current
to ground through R
to plus V3 = 7 V
Video output voltage (neg.) (RL =00)
Sync pulse level
DC voltage (V2 = 4 V; V17J18 =- 0)
Output current
to ground through R
to plus V4 = V13

116

60
6.0
4.0

mA
Vdc
mA

V15/12

o to 4

Vdc

V1
V1

+3.0
-3.0

V
V

Vi17l1S

max 100

ILV

..:1G

60

dB

V2/12
V2/12

minO
max 4.0

Vdc
Vdc

lq6

± 1.0

mA

VSI12
VS/12

max 4.0
6.0

Vdc
Vdc

V5/12
V5112

4.0 to V13
oto 1.0

Vdc
Vdc

Vq3Pp

3.0

V

V3/12
V3112

2.0
5.3

Vdc
Vdc

Iq3
Iq3

-5.0
+2.0

Vq4Pp
V4112
V4112

3.0
V13 -2.0
V13 -5.3

V
Vdc
Vdc

Iq4
Iq4

-5.0
+1.0

mA
mA

Zi17I1S

kO/pF
kO/pF
kO

BYldeo

1.8/2
6.612
20
150
150
10
6.0

mV
MHz

a

45

dB

It3
V14I12

I

mA
mA

Additional application datal)
Input impedance
Output impedance
AFC input impedance
Output resistance
Output resistance
Residual IF (basic frequency)
Video bandwidth (-3 dB)
Intermodulation ratio with
reference to fcc
(sound-color-beat frequency)

Zql0/ll
Zi8/9

Rq3
Rq4
V3; V4

0
0

1) not measured

7-87

TDAS400-2

Circuit description
The integrated circuit is comprised of a 4-stage controlled AM amplifier, a limiter and mixer
for synchronous demodulation of the video signals as well as an FM demodulator to generate
positive or negative AFC voltages. In addition, an amplifier for both the positive and negative
video output signal is included. The positive video signal together with the positive flyback
pulse are used for gated control.

Pin description
Pin
1

2
3
4
5
6
7

8
9
10
11
12

13
14
15
16
17
18

7-88

Function
Gating pulse
Time constant AGC
Positive video output
Negative video output
AFC polarity switch '
AFC output
White level adjustment
AFC circuit
AFC circuit
Tank circuit
Tank circuit
GND
Supply voltage
Referehce voltage
Tuner AGC
Delayed AGC output
Video IF input
Video IF input

TDAS400-2

Block diagram

Tuner
Control

..
17

16

15

I I ~ T""~
M
I M'-----I--+-..'-r-CO~"~I

14

Delayed

13

11

12

10

~

4.

~ ~r-------l

I-'

~ 1 :vy--{ ~ /1--I-----IJ7\}-,

1'--=2,L...--,.,
Voltage
Amplifier

I

TDA 5400-2

I--

1

Keyed
Amplifier

Video
Amplifier

I--

Polarity ~
,..... Switch r-----..+----L---1

h

~Il

'1--+----

1

JL~

2

3

Iv

4

-

1\

5
+/~AFC
Va

7·

6

WhileLev~

. ~ AFC.

I

........

8

9

H~
L-.--.:):..

""L....,J-

~

7

7:.ae

......

I:

cO

I

0

Tuner
Control

Delayed
Tuner
Co!1trol

fI)

c

Vstab

;

+Vs

..
CD

:::I

500

18

=*=22nF

HIH

117

100nF

100nF

tH

H

15

116

O.
C;
c;::;:

/
22pF

13

12

11

6

7

8

110

TDA 5400-2

2

3

4

5

V-I .1'\

I
Jl
"'
I

~~~
AFCOFF

W
"

Video +

tJ

9

7.5 Turns
AFC
+/-AFC

AFC

White Level

g
8o
~

SIEMENS

TDA5660 P
Modulator for TV, Video and Sound Signals
The monolithically integrated circuit TDA 5660 P is especially suitable as modulator for
the 48 to 860 MHz frequency range and is applied e.g. in video recorders, cable converters,
TV converter installations, demodulators, video generators, video security systems, amateur
TV applications, as well as personal computers.
•
•
•
•
•
•
•
•
•
•
•
•
•

Synchronizing level-clamping circuit
Peak white value gain control
Continuous adjustment of modulation index for positive and negative modulation
Dynamic residual carrier setting
FM sound modulator
AM sound modulator
Picture carrier to sound carrier adjustment
Symmetrical mixer output
Symmetrical oscillator with own RF ground
Low radiation
Superior frequency stability of/main oscillator
Superior frequency stabi,lity of sound oscillator
Internal reference voltage'

Circuit description

Via pin 1, the sound signal is capacitively coupled to the AF input for the FM modulation
of the oscillator. An external circuitry sets the preemphasis. This signal is forwarded to a
mixer which is influenced by the AM modulation input of pin 16. The picture to sound carrier
ratio can be changed by connecting an external voltage to pin 16, which deviates from the
internal reference voltage. In case, the sound carrier should not be FM but AM modulated,
pin 1 should be connected to pin 2, while the AF signal is capacitively coupled to pin 16.
Through an additional external dc voltage at pin 16, the set AM modulation index can be
changed by overriding the internally adjusted control voltage for a fixed AM modulation index.
At the output of the above described mixer the FM and/or AM modulated sound signal is
added to the video signal and mixed with the oscillator signal in the RF mixer. A parallel
resonant circuit is connected to the sound carrier oscillator at pin 17, 18. The unloaded Q of
the resonant circuit must be Q = 25 and the parallel resistor RT = 6.8 kQ to ensure a
picture to sound carrier ratio of 12.5 dB. At the same time, the capacitative and/or inductive
reactance for the resonance frequency should have a value of Xc "'" XL "'" 800 Q.
The video signal with the negative synchronous level is capacitively connected to pin 10.
The internal clamping circuit is referenced to the synchronizing level. Should the video
signal change by 6 dB, this change will be compensated by the resonant circuit which is
,set to the peak white value. At pin 11, the current pulses of the peak white detector are
filtered through the capacitor which also determines the control time constant. When pin 12
is connected to ground, the RF carrier switches from negative to positive video modulation.
7-91

TDA5660 P

With the variable resistor of R = 00 •••• 0 Q at pin 12, the modulation depth, beginning with
R = 00 and a negative modulation of m OIN = 80%, can be increased to m OIN = 100% and
continued with a positive modulation of m o/P = 100% down to m o/P = 88% with R = 0 Q.
The internal reference voltage has to be capacitively blocked at pin 2.
The amplifier of the RF oscillator is. available at pins 3-7. The oscillator operates as a
symmetrical ECO circuit. The capacitive reactance for the resonance frequency should
be Xc "" 70 Q between pins 3, 4 and 6, 7 and Xc "" 26 Q between pins 4, 6. In order to
set the required residual carrier suppression, pin 9 is used to compensate for any dynamic
asymmetry of the RF mixer during high frequencies of > 300 MHz. The oscillator chip ground,
pin 5, should be connected to ground at the oscillator resonant circuit shielding. Via pin 3
and 7 an external oscillator signal can be injected inductively or capacitively. The
peripheral layout of the pc board should be provided with a minimum shielding attenuation
of approx. 80 dB between the oscillator pins 3-7 and the modulator outputs 13-15.
For optimum residual carrier suppression, the symmetric mixer outputs at pins 13, 15 should
be connected to a matched balanced-to-unbalanced broadband transformer with excellent
phase precision at 0 and 180 degrees, e.g. a Guanella transformer. The transmission loss
should be less than 3 dB. In addition, an LC low pass filter combination is required at the
output. The cut-off frequency of the low pass filter combination must exceed the maxirnum
operating frequency.
If the application circuit according to figure 1, 2 is used, a multiplication factor VlRF
(application) = VlRF (data sheet) 3.9 must be used to convert a 300 Q symmetrical
impe:dance to an asymmetrical impedance of 75 Q for the stated RF output voltage Vq of
the type specification in order to ensure a transmission attenuation of 0 dB for the balanced. to-unbalanced mixer.

7-92

TDA5660 P

Maximum ratings
Remarks

min

max

-0.3
0

14.5
2

V
mA

V2 +2
1
1.5

V
V
V

Supply voltage
Current from pin 2

-12

Voltage at pin 1
Voltage at pin 9
Voltage at pin 10

VI
V9
VIOPP

V2 -2
-4

Capacitance at pin 2
Capacitance at pin 11
Voltage at pin 12
Voltage at pin 13
Voltage at pin 15
Voltage at pin 16

C2
CII
VI2
VI3

0
0
-0.3
V2
V2
V2 -1.5

100
15
1.4
Vs
Vs
V2 +1.5

nF
iJ.F
V
V
V
V

-40

150
125

°C
°C

80

KlW

9.5
0
0
48

. 13.5
5
20
860

V
MHz
kHz
MHz

0
4
V2

70
7
Vs

°C
MHz
V

Vs

v,s

VIS

V2 =7t08V
Vs = 9.5 to 13.5 V
Vs =9.5 to 13.5 V
only via C
(max. 1 iJ.F)

Vs = 9.5 to 13.5 V

Only the external circuitry shown
in application circuits
1 and 2 may be connected
to pins 3, 4, 6, 7, 17 and 18
Junction temperature
Storage temperature

7;

Thermal resistance (system-air)

R1hSA

Tstg

Operating range
Supply voltage
Video input frequency
Sound input frequency
Output frequency

Ambient tempe(ature
Sound oscillator
Voltage at pin 13, 15

Vs
f VIDEO
fAF

fq

TA

fosc
V,3.IS

depending on the
oscillator circuitry
at pins 3-7

7-93

TDA5660 P

Characteristics
Vs = 11 V; TA =25°C

Test conditions

Current consumption
Ia
Reference voltage
V2
Oscillator frequency range fosc
Turn-on start-up drift

.1fosc

Frequency drift as
function of Vs

-.1fosc

Video input current
at pin 10
Video input voltage
at pin 10

-110

Modulation depth
VVIDEOpp = 1 V; fVIDEO200 kHz sine signal
Output impedance
RF output voltage
Modulation signal in
neg. modulation
pin 12 open
Output capacitance

v'opp

mDIN
mD/P

Z13;Z15

Vqrms

min

typ

max

1; 2
1; 2

22
7
48

30
7.5

40
8
860

mA
V
MHz

1; 2
1; 2
1; 2

0
0
0

-50
-200

-500
-500

kHz
kHz

5

-150
0

150
10

kHz
IlA

at coupling capac.
C:5.1 IlF
Ileak:5. ±0.3IlA
neg. mod.
pos. mod.

21;22

0.7

1.4

V

1; 16
2;16

75
83

80
88

85
93

%
%

static
Ch40

24
1b

10
2.5

3.5

5.5

kQ
mV

25

0.5

2.0

pF

. 12 =0 mA
0:5.12 :5.1 mA
External circuitry
adjusted to
frequency
TC value of
capacitor in osc.
circuit is 0; drift is
referenced only to
self-heating of the
component
t=0.5-10s;
TA =const.
Ch 30
Ch40
Vs = 9.5-13.5 V
TA =const.
Ch 40
ClO :5.1 IlF

C13 =C15

S parameter at pins
3,4 and 6, 7
RF output phase
0'.13,15
RF output voltage
.1Vq
change; adjustment
range
RF output voltage change .1Vq
RF output voltage change .1Vq
Oscillator interference FM
caused by AM modulation and
coupling of the modulator
output with the oscillator
resonant circuit;
VVIDEOPP = 1 V;
fVIDEO = 10 kHz; sine signal
Ch30
Ch 40

7-94

Figure

26
140

f = 543.25-623.25
.1f=80 MHz
Ch 30-Ch 40
f = 100-300 MHz
f=48-100 MHz

1
6
6

0
0
0

1; 9
1; 9

0
0

180

5
7

220

degrees

1.5
1.5
1.5

dB
dB
dB

15
21

kHz
kHz

TDA5660 P

Characteristics
Vs =11 V; TA =25°C
Intermodulation ratio
Harmonic wave ratio

aMR
aH

Harmonic wave ratio
Harmonic wave ratio

aH
aH

Sound carrier ratio
Color picture to sound
carrier ratio

ap/s
ap

All remaining harmonic
waves

a

Amplitude response of
the video signal

av

Residual carrier
suppression
Static mixer balance
characteristic
Dynamic mixer balance
characteristics
Stability of set
modulation depth

aR

Stability of set
modLllation depth
Stability of set
modulation depth
Stability of set
modulation depth

Figure

fp+1.07 MHz
fp +8.8 MHz without video
signal 19, 20, 21 unmodulated
video and sound carrier,
measured with the spectrum
analyzer as difference between
video carrier signal level and
sideband signal level without
video and sound modulation.
fp +2fs
fp +3f s
Vq with spectrum analyzer;
loaded Q factor Q L of the sound
oscillator resonant circuit
adjusted by Rs to provide the
required picture to sound carrier
ratio of 12.5 dB; Rs -6.8 kQ;
Q u = 25 of the sound oscillator
circuit.

1; 7; 15 54
1; 7; 15 35

75

dB
dB

1; 7
1; 7

48
48

dB
dB

fp +4.4 MHz (dependent on
video signal)
Multiple of fundamental wave
of picture carrier, without video
signal, measured with. spectrum
analyzer;
fp/s = 523.25-623.25 MHz
VVIOEO pp == 1 V with additional
modulation f=15 kHz-5 MHz
sine signal between black
and white

15

1.5

0

1; 12

32

21;23

-100 0

21; 23

0

.1mo

f -100 ... 300 MHz

6

.1mo

TA -0-60°C; Vs == 12 V

dB
dB
dB

1; 13

6

.1mo

12.5
17

max

15

.1mo

V,3 rms

35
42

1; 7; 17 10
1

With adjustment at pin 9
Ch 30 ... Ch 40
V9 adjusted to .1V13/15
minimum
V9 adjusted to V13rms
minimum
Video input voltage changes
with sine signals
f = 0.2 MHz; .1VVloEO pp == 1 V
±3 dB; Ch 30 ... Ch 40;
Vs == 12 V; TA ==const.
f-48 ... 100 MHz

.1V,3I15

min

typ

Test conditions

dB

+100 mV
10

mV

±2.5 %

±2.5 %
2

±4

%

±2.5 .%

7-95

TDA5660P

Characteristics
Vii =11 V; TA =25°C
Test conditions
Stability of set
modulation depth
Interference product
ratio sound in video;
sound carrier FM mod.
Signal-to-noise ratio in
video; sound carrier
unmodulated
Interference product
ratio sound in video
sound carrier AM mod.
Umweighted FM noise level
ratio video in sound;
FuBK test picture as
video Signal
Unwelghted FM nOise level
ratio video in sound

typ

max
±2.5

%

aSIP

1;11

48

60

dB

aNlp

Ch30 ... Ch40

1;11

48

74

dB

aSIP

Ch30 ... Ch40

1;11

20

33

dB

apls

Ch39

1a; 8

48

54

dB

apls

Ch 39; test picture VU
G-Y;UN
Ch 39; color bar
Ch 39; uniform red level
Ch 39; uniform white level
Ch 39; test pattern
Ch 39; white bar
Ch 39; bar
Ch 39; 20T/2T
Ch 39; 30% white level
Ch 39; 250 kHz
Ch 39; multiburst
Ch 39; ramp

2;8

48

56

dB

2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
2;8
1a;8

46
48
45
48
46
45
43
48
46
46
44
48

52
58
51
55
52
50.8
49
58
52
53
50
54

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

~Ignal-to-noise ratio of

aSIN

Gdll

7-96

min

Vs =9.5-13;5V;
TA-const
Ch30 ... Ch40

Limo

sound oscillator
Differential gain

Differential phase
Period required for peak
white detector to reach
steady state for full
modulation depth with
1 white pulse per half
frame with control in
steady state

Figure

measured with measurement demodulator,
video test Signals
and vector scope

Cj)dll

t

Catpin11-10f,LF;
Ileak~2f,LA

6

10

%

15
50

%
f,Ls

TDA5660 P

Characteristics
Vs =11 V; TA ==25°C

Test conditions

Setting time for video signal
change from 0 Vpp to 1.4 Vpp
Setting time for video
blanking signal from 100%
white level to 42% grey level
with subsequent rise in grey
level to 71% of video blanking
signal (due to decontrol
process)
Sound oscillator frequency
range

Figure

min

Video blanking
signal content is
uniform white level

fs/osc

Unloaded Q factor
of resonant circuit
Q u - 25; resonance
frequency 5.66 MHz

Turn-on start-up drift

.Ilfs/osc

Sound oscillator frequency
operating voltage

.Ilts/osc

Capacitor TC value
in sound oscillator
circuit is 0, drift is
based only on
component heating
TA -consl;
fs/osc - 5.5 MHz
Vi -9.5-13.5 V;
fs/osc -5.5 MHz;
TA -const.; Qu -25
19; 19a
V, rms -150 mV
1

FM mod. harmonic distortion
THDFM
Audio preamplifier input
Z,
impedance (dyn.); FM operation
FM sound modulator, static
.Ilfs/osc
modulation characteristic

.IlV;/2 ... V;-V2-± 1V;
fs/osc -5.5 MHz;
Qu- 25

FM sound modulation
characteristic (dynamic)
AM sound modulation factor

.IlfM/.:lV;
m

VAF -0.3 V

AM sound modulation
harmonic distortion

THDAM

m-86%;

AM audio preamplifier input
impedance
AM sound modulator input
voltage

Z'6

typ

max

120

500

I-Is

2.25

5

s

7

MHz

5

15

kHz

5

15

kHz

0.6

1.5

%
kQ

4

200

1; 14

±210

±270

±330

kHz

1a; 10a

0.3

0.38

0.46

2;3;
4a, b

30

40

50

kHzl
mV
%

0.7

3

%

VAF -0.64 V;
f AF -1 kHz
VAF

m-90%;
fAF=1 kHz

2

25

50

75

kQ

2

0.5

0.67

0.84

V

7-97

TDA5660 P

Pin description
Pin

1
2

3
4
5

6
7
8
9.
10
11

12

13
14
15
16
17

18

7·98

Function

AF input for FM modulation
Internal reference vol~ge
Symmetrical oscillator input
Symmetrical oscillator output
Oscillator ground
Symmetrical oscillator output
Symmetrical oscillator input
Supply voltage
Dynamic residual carrier adjustment
Video input with clamping .
Connection for smoothing capacitor
for video control loop
Switch for positive and negative modulation
as well as residual carrier control
Symmetrical RF output
Remaining ground of component
Symmetrical RF output .
Picture to sound carrier ratio (adjustment and AM sound input)
Sound oscillator symmetrical input for tank circuit
Sound oscillator symmetrical input for tank circuit

m

18

17

16

15

1S

13

12

1

I

IC.lam~ing

FM Sound Oscillator

~

Ia.

10

11

CircUit

Modulator Output Buffer Stage

~

ii'

ea

;

3

~
~

/~

, \ Sound /
+AM
Carrier
Sound
Input

1\1

~bZ

<

AM Sound
Modulator

Gain

~~d

Index

Video
Buffer
Stage

~
Oscillator Buffer Stage

*,

Vstab
~

~~

[

=?

V\

j:t\

Oscillator

Input
AmplifierFM

1

==

2

3

4
)

5

Carrier
Adjustm.

6

7

8

9

g-t
UI

G)
G)

~

o

'1J

TDA5660 P

Test and measurement circuit 1

for FM sound carrier and negative video modulation

Anzac 183-4

5.5 MHz
Sound Oscillator Tank
Circuit

RT 6,8kQ

33pF
18

17

TDA 5660 P

1

22kQ 2

220 pF --r.;;
..l20nF

220kQ

1

Reference 7.5 V

O,5~FT

!

2.7pF

I

,
47kQ

33 kQ

,22pF

885058
47kQ

+Vd

Channel 30 ... 40
VON 10 ... 28

Figure 1

7-100

H

Vs - 9.5-13.5 V

9-------L-,I-----~
r22PF,

9

10nF

2'2 PF

_

,

FM AF Input

2,2 pF

8

Dynamic Residual
Carrier Adjustment
(If Required)

at Pin 2

TDA5660 P

Test and measurement circuit 1

for FM sound carrier and negative video modulation

50Q

Vq

Anzac 183-4

I
5.5 MHz
Sound Oscillator Tank
Circuit

Measurement

t---;r~-;Receiver

1 nF

1nF

RT6,8kQ
33pF

18

17

15

14

TDA 5660 P

2
22kQ

J I
OSpF

FM AF Inpu

3

I

4

5

1.8pF

Z2

100F

r

'F

Reference 7.5 V

22PF

47kQ

6

8

7

I

!~

H

Z2

2,1,F

'F

Vs-9.5-13.5V

BB50~5B 22pF
10nF

9

10nF

1.8pF

Dynamic Residual
Carrier Adjustment
(If Required)

47kQ

HChannel 30 ... 40
+Vd

at Pin 2

Vo/V 10 ... 28

Figure1a

7-101

TDA5660P

Test and measurement circuit 1

for FM sound carrier and negative video modulation

50 I'l

Vq
Anzac 183-4

I
5.5 MHz
Sound Oscillator Tank
Circuit

Measuremen
Receiver

I
H

I-

<==5

3

2

1nF

22

H

PinS 0 - - - - - 0 Pin S
5"

180 0

522

+-+-+-+-HH-+++fl'+++t-t-H-t-t"1

Zo=7SQ

Figure 24

7·128

TDA5660 P

r

Application circuit 1

Signal Output

1nF

+Vs

0 - - -..........

Le ... Lg Balun Transformer with
Ferrite Core
5.5 MHz
Sound Oscillator Circuit

I

33pF

1nF

17

18

15

14

13

TDA 5660 P

2
22kQ
220

I

1

10nF

7

pF

FM AF Input

10nF

H

2'2 pF

3,9 pF

Reference 7.5 V

,TO's

8

1~

L• t - - - - 4
-i.il..

+-_ _ _

1

22pF

at Pin 2

+Vd
Channel 30 ... 40
VON 10 ... 28

7-129

TDA5660 P

Application circuit 2

r

Signal Output

Le···Le Balun Transformer with
Ferrite Core

1nF
5.5 MHz
+Vs
Sound Oscillator Circuit

RT 6.8kQ
7SQ Video

10~Fl~O.S~F

39pF
18

17

16

14

1S

13

12

11

7

8

TDA 5660 P

22kQ

3

2

220kQ
220pF "]OnF

·
r

I-i

L,

10nF

Vs -9.5-13.5 V

Reference 7.5 V

TO.S~F
FM AFlnput

27 PF

.

47pF

BBSOSB

47kQ

Channel 3

7-130

9

10nF

J-4

TDA5660 P

Application circuit 3
Signal Output
5.5 MHz
Sound Oscillator Circuit

1

..t~F

10nF

Ls ... Lg Balun Transformer with
Ferrite Core

A
IVidee

+Vs
RT6.8krl

La

33pF

17

18

16

75rl

L9

13

15

10fJF
11

0.5jJF
10

8

9

TDA 5660 P

2

3

220pF

r

FM AF Input

6

L,1I

0 L2211J.lF
10nF

Reference 7.5 V
5 fJ F

TO.

5

Quartz

22 krl

220krl

4

7

10nF

H

18pF
Vs = 9.5-13.5 V
Symmetrical Oscillator Layout
Harmonic Crystal
Operated in Series Resonance
TV IF 38.9 MHz

IF Filter Neosid
1) 2 Turns
2) 12 Turns

7-131

TDA5660 P

Application circuit 4

..tH

5.5 MHz
Sound Oscillator Circuit

Signal Output

L16~:'L9

Balun Transformer
with Ferrite Core

+Vs~--r-_

RT 6,8kn
33pF

I

La L9

75n

videe

'--_.....

18

17

10pF
13

15

16

V ~V
O,5pF

11

10

8

9

TDA 5660 P

3

2

22kn
220pF

4

7

120pF

r -r
10nF

=

133

uartz

10nF

H
pF

Vs =9.5V-13.5V
to Pin2
Residual Carrier Adjustment
If Required

7-132

TDA5660P

Application circuit 5
~ Signal Output

5.5 MHz
Sound Oscillator Circuit

1nF
L6 ... Lq Balun
Transformer
with Ferrile Core

+Vs

RT 6.8 kl!

•

33pF

I10~F
17

18

16

o~

Vide~n"-"J:

O,SpF

11

10

8

9

TDA 5660 P

7

2

220kl!

2~::· W.F

'----.

I

T O,S ~F
FMAFlnput

Alternative 2:
Series Crystal Oscillator with
Harmonic Crystal
Good Oscillating Characteristics
TV IF 38.9 MHz

Ir~

147

pF

10nF

H
Vs -9.5V-13.5V
1uF
to Pin 2
Residual Carrier Adjustment
If Required

7-133

.1...H

.....
~

i

Signal Output
1nF

I. 10nF

";'I

+Vs~

!.o

L6 ... L9 Balun Transformer
with Ferrite Core

:I

n

a"::;:

3,37 V

P,1A 5kQ

Dual Audio Stereo Signal

5.5 +5.75 MHz

~

ca.2,9V r'Yz,75V
1:€1nF

I
I

22 kQ

RB/T

appro 5 ...10kQ
VHFJ17118

1~F

::10mV,m

20iiQ
'18

H
117

16

15

.I10~F 1-CJ--1
5Q

I

1,5pF

..L
I.,J~VideO

1nF

.L O,5pF

114

13

12

111

1;

8

19

A

. TDA 5660 P

2

4

5

6

~rI
~2,2pF
~

r'v'

FM AF Inp'ut

10nF

H

220pF ..Lr1onF12,2PF

L.-_~. Reference 7,5 V

17
2,7pF

22kQ

22 PF'

r

Vs -9.5V-13.5V

BB 505 B

22 pF

I

mll't::"

Channel 30 .. .40
VDIV 10 ... 28

Dynamic
Residual Carrier Adjustment
If Required

g-I
en

at Pin 2

i
"

SIEMENS

TOA 5835
Video IF IC with Quasi-Parallel Sound and AFC
Pin Configuration

Pin Definitions

Top View

2
3
4
5
6

7
8
9
10
11

Pin

Function

1

Supply Voltage
Demodulator Tank Circuit QPS
Demodulator Tank Circuit QPS
Push-Pull CUrrent Output AFC
Demodulator Tank Cirucit AFC
Demodulator Tank Circuit AFC
and Switch-Off
Tuner AGC Threshold
Reference Voltage
Demodulator Tank Circuit Video IF
Demodulator Tank Circuit Video IF
Video Output
Gating Pulse Input
AGC Time Constant Video IF
Delayed Tuner AGC
Video IF Input
Video IF Input
GND
QPS IF Input
QPS IF Input
AGC Time Constant QPS
Sound Carrier Output
GND

2
3
4
5
6

22
21
20
19
18
17
16
15
14
13
12

7
8

9
10
11
12
13
14
15
16
17
18

0157-18

19
20
21
22

Video IF Section
Controlled AM broadband amplifier with synchronous demodulator, video amplifier, and AGC voltage generation for the video IF amplifier and tuner.

Quasi-Parallel Sound Section
Controlled AM broadband amplifier with quadrature demodulator, sound carrier output, internal AGC voltage
generation, and an AFC section which can be disabled.
The TDA 5835 is especially suitable for application with black and white or color television receivers and/or
VTR systems with PNP/MOS tuners for TV standards with negative video modulation and FM sound.

®Siemens Components, Inc.

7-135

May 1988

TDA 5835

Block Diagram

22

0157-1

Circuit Description
The video IF section is comprised of a 4-stage controllable AM amplifier, a limiter, and a mixer for the
synchronous demodulation of video signals as well
as an amplifier for the positive video output signal.
The positive signal is used for gated control and a
threshold amplifier to derive th~ delayed tuner AGC
from the AGC voltage.
The quasi-parallel sound section also includes a 4stage AM amplifier, a limiter, and a mixer for the
quadrature demodulation of the 1st sound IF with
subsequent sound carrier output for the 1st sound
IF. The control voltage is generated by a peak value
rectifier from the 2nd sound IF signal. The quasi-parallel sound also drives the AFC section.

Alignment Procedures
VIDEO IF
At a video carrier input level of V15/16 rms = 10 mV
and a superimposed AGC voltage of V13 = 3V, the
demodulator tank circuit is preliminarily aligned so
that the demodulated video signal V11pp reaches its
maximum output level at the positive video output.

7-136

Any suitable video test signal can be used for modulation. Subsequently, the AGC voltage V13 is reduced until the video signal equals approx. 3V
(peak-to-peak). By fine-aligning the demodulator
tank circuit, the maximum output level of the video
signal is reached.
The flat response characteristic of the demodulator
ensures a non-critical alignment procedure.

QPS
At an input signal of V18/19 rms = 10 mV the demodulator tank circuit is preliminarily aligned until a
max. AM suppression of the demodulated video signal V21 is reached at the sound carrie~ output. A
video signal critical for the sound-interference ratio
should be used for modulation (whitel staircase,
FuBK). Subsequent fine-aligning is performed by
measuring the sound-interference ratio,at the output
of a FM demodulator and fine-aligning the demodulator tank circuit for a max. interference ratio. If severaJ sound carriers are used in a device, the sound
carrier with the lowest level should be used for alignment purposes.

TDA 5835

Absolute Maximum Ratings*
Supply Voltage (Vl) ...•..................... 13V
Maximum DC Voltage (V2, 3) •............. Va to Vl
Maximum DC Voltage (V4) ............... OV to V1
Maximum DC Voltage (V5, 6) .•.•....•.•.•. Va to Vl
Maximum DC Voltage (V7) ....•.•......•. OV to Vl
Maximum DC Current (Is) ........ - 2 rnA to + 2 rnA
Maximum DC Voltage (V9, 10) .......•..... Va to Vl
Maximum DC Current (-111) ....• -1 rnA to + 3 rnA
Maximum DC Voltage (V12) .....•..... -10V to Vl
Maximum DC Voltage (V13, 14, 15) .•....... OV to Vl
Maximum DC Voltage (V16, lS) .•.•........ OV to Vl
Maximum DC Voltage (V19, 20) .•..••...... OV to Vl
Maximum DC Current (121) ....... -1 rnA to + 2 rnA
Junction Temperature (Tj) ........•......... 1S0·C
Storage Temperature
Range (T5tg) ................ - 40·C to + 12S'C
Thermal Resistance
(System-Air) (Rth SA) ........•.•.•..... 55 K/W

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Range
Supply Voltage (Vs) .•.•..........• 10.SVto 12.6V
IF Frequency (fIF) ........•.•.•. 15 MHz to 75 MHz
Ambient Temperature (TA) .....••.•. O'C to + 70'C

Characteristics Vs = 12V; TA = 2S'C
Parameter

Symbol

Conditions

Min

Typ

Max

Units

Current Consumption

11

102

134

rnA

Stab. Reference Voltage

VS/22

6.7

7.0

V

114

4.5

Video IF

Control Current for Tuner
Tuner AGC Threshold

V7I22

Gating Pulse Voltage

V12
V12

Positive Gating Pulse
Negative Gating Pulse
Vl1 pp = 3V

Input Voltage at Gmax

VI 15/16

AGCRange

aG

IF Control Voltage

V13/,22
V13/22

Gmax
Gmin

Vq 11 pp

RL =

Video Output Voltage

rnA

0

4.0

V

4.0
-10

V1
-4.0

V
V

60

/-LV

30
60

dB

0
4.0

V
V

3.0

V

V11/22

2.0

V

V13 = 4V; V15/16 = OV

V11/22

5.3

V

Output Current

Iq 11
Iq 11

-5.0
+2.0

rnA
rnA

Sync Pulse Level

00

DC Voltage
to ground via R
to plus Vll = 7V

7-137

-

TDA 5835

- Characteristics

Vs

= 12V;TA = 25°C (Continued)

Parameter
AFC Output Current

Symbol
Iq4

Conditions
di/df

Min

<0

Typ

Max

±1

Units
mA

OFF

VS/22

Vs = V6;R = 10kn

ON

VS/22

Vs = V6; R =

Sound Carrier Output Voltage

Vq21

ViPC = 1 mV
Vise = 300 P.V

Input Voltage at Gmax

Vi18/19

V21 = V21 -3 dB

50

AGCRange

AG

V21 = V21 ±3 dB

60

dB

61

dB

66

dB

AFC

4.0

0

V
V

6.0

00

Quasi-Parallel Sound

Signal-To-Noise-Ratio

IEC468

White/Staircase Signal

Peak Weighting

mV

10

Black Picture

100

p.V

Test Conditions
Video Carrier/Sound Carrier

1P

dB

Modulation Frequency

1

KHz

Frequency Deviation

50

KHz

IF Input Voltage

20

mV

Design-Related Characteristics
Input Impedance

Zi1S/16
Zi18/19

1.8/2
1.8/2

kn/pF
kn/pF

Output Impedance

Zq%
Zq9/10

kn/pF
kn/pF
kn

~S/6

6.6/2
6.6/2
20

Output Resistance

Rq11

150

n

Residual IF (Fundamental Wave)

V11

10

mV

6.0

MHz

50

dB

200

n

Video Bandwidth (-3 dB)

Bvideo

Intermodulation Ratio
with Reference to fcc

aiM

Output Resistance

Rq21

IF Control Voltage

V20/22
V20/22

7-138

Sound Color
Interference

Gmax
Gmin

0
4

V
V

TDA 5835
Measurement Circuit
Gating Pulse

22

18

17

16

14

TDA 5835

5

2
22pF

10
68pF

11

100nF

H

.Vs

12.5 Tum.
CuLS 0.25mm
VldooCarrier

7.5 Tums
CuLS 0.25 mm
VldooCarrier

12.5 Tum.
CuLSO.25mm
V1dooCarrier

I,'F(

TunerAGC VREF
Threshold

Vqvldeo
0157-2

Application Circuit
Tuner Control
CUlTent

SC

Gating
Pulse

n
II

U
1kll
22

21

16

15

12

14

TDA 5835

2 22pF

12.5 Tum.
CuLSO.25mm

'Vs

4

5 68pF

9

22pF

10

12.5 Turns
CuLSO.25mm

11

.Video
0157-3

7-139

TDA 5835
Demodulator Tank Circuit QPS
12.STllmolll.2 CUI.

a..so

I,

.3I.'"Hz,'.I.511111

"

Z.nA

--

To..-

.....-+-

0157-4

Demodulator Tank Circuit AFC

"pF
7.5TllmoiCuI.

_eam.
0157-5

Tuner AGC Threshold and Output

I

t
7·140

01157-8

TDA 5835
Demodulator Tank Circuit Video IF
12.5 _ . 2 CUI.

a•• 50

22pF

f • • 31.9MHI, B.l.5MHz

10
3,3kll

Ukn

ToUm"-r
ondlll_

t--+-

0157-8

Reference Voltage

22

0157-7

Positive Video Output

3.3kll

-

V_6V

Gating Pulse Input

10011

t--Cll--oll
2m"
0157-1

0157-10

7-141

TDA 5835

AGC Time Constant Video IF

t,p 6V

------+/dllCh.,..

13 ~-/ch.rp

.---+---0-'--1

I

I

....

=r

l20nF

I

-

.J..
From Gated

eo_
0157-11

IF Input Video IF
IF Input QPS

Sound Carrier Output QPS

1000
'SI1'IO---+-~-IC

, ..A
'6n91O---+---+--~
0157-14

2.2kR

2.2kO

220-------+
0157-12

AGC Time Constant QPS

rI

I
!

------oiI

eo_
F_

I

AmpIkl

l
To~_

0157-13

7-142

TDA 5835
Positive Video Output
~::Icarri.r,+

Measurement Configuration

______________

Pin
7 Open
S3V

T
VvldeoPp

1

Sync.
Leve12.0V

(SAW 361 OJ
(SAW 36' S)
0157-16

Test signal: fvc = 38.9 MHz with test signal modulated
with 10% residual carrier; sound carrier -13 dB (Transmitter Side)

0157-15

.:. . :. :.

Intermodulatlon

'::~:l
30'~

1I~
..'. . ,. 1I
0157-17

V·d (f = 1 MHz)
20 log V . VI 81t _ f
_ f )

Intermodulation ratio: aiM

=

The 50% IRE signal with

± 50% IRE color carrier corresponds to Cyan with 75% color saturation.

vIdeo

-

SC

CC

Ordering Information

I

Type

I

Ordering Code

Package

7-143

SIEMENS

TDA5850
Video Switch

Ie

The TDA 5850 is a switchable video amplifier with connections for the French and IEC VCR
standards.

Features

•
•
•

Standard connection for VCR (CCIR) and Peri TV sets
Input clamping
Positive and negative video outputs

Maximum ratings
V

Tstg

16.5
150
-40 to 125

RthSA

70

KlW

Vs

10 to 15.8
6
to 70

V

Supply voltage
Junction temperature
Storage temperature range

7j

Thermal resistance (system-air)

Vs

°C
°C

Operating range
Supply voltage range
Video bandwidth
Ambient temperature range

BVldeo
Tamb

7-144

o

MHz

°C

TDA5850

Characteristics (VS = 13 V;

Tamb

= 25 DC)
min

typ

max

Current consumption (pin 2 open)

h

Switch input VCR recording
Switch input VCR playback
Switch input V3/l = 15 V

V3/l
V3/l
13

Video output voltage pos.
(V3 = 1.2 V; Ve pp = 3 V)
Video output voltage pos.
(V3 ~ 3 V; V4 = 1 Vpp)
Sync pulse level

Vspp

3.0

V

Vspp

3.0

V

VSI1

2.0

Vdc

Output current (to ground)
Output current (to +)
Output resistance
Video output voltage neg.
(V3=1.2V; Ve=3Vpp)
Video output voltage neg.
(V3 ~ 3 V; V4 = 1 Vpp)
Sync pulse level

Is
Is
Rs
Vspp

-5.0
2.0
150
3.0

mA
mA
V

Vspp

3.0

V

VSI1

V7-2

Vdc

Output current (to ground)
Output current (to +)
Output resistance
Video output voltage pos.
(Vepp = 3 V; R211 = 75 Q)
Sync pulse level
(R2/l =75 Q)

Is

mA
mA

Rs
V2pp

-5.0
1.0
150
1.0

V

V2/l

1.0

Vdc

Output current (to ground)
Output current (to +)
Output resistance

12
.12
R2

-30.0
2.0
75

mA
mA

Video input current (Ve pp = 3 V)
Video input current (V4 pp = 1 V)
Video gain (Vapp = 3 V; R2/l = 75 Q)
Video gain (Vapp = 3 V; V3 = 1.2 V)
Video gain (Va pp = 3 V; V3 = 1.2 V)
Video gain (V4 pp = 1 V; V3 ~ 3 V)
Video gain (V4 pp = 1 V; V3 ~ 3 V)
Video bandwidth (-3 dB)
Cross talk rejection referred to Vs pp = 3 V
(f=50 Hz .. 6.0 MHz; V3= 1.2 V; V4pp=1 V)

23.0
0
3.0

Is

Vdc
Vdc
mA

Q

Q

Q

Il A
Il A

1/3
1
-1
3
-3

G S/4

a

1.2
V7
1.0

40
20

Ia
14
G 2/a
Gs/a
G s/e
G S/4
BVldeo

mA

6.0
50

MHz
dB

7-145

TDA5850

Block diagram, test circuit and application circuit

JJJ\j
3Vpp

fromVideo
amplifier

I

i~~d~tO
+j

iii iii

0.47!JF

8

::t:
Video
S
Video
t---.r-_·.''9t-:+--'amplifier
pre amplifier

1
f

r
lOA 5850

Playback!
recording

VCR

.~

1
,

2
VCRoutput

17sn

,10

4

3

==

r T\flv

pp

+12V

• • •

VCR input

Playback I recording
VCR switch over

7-146

O.47!JF

SIEMENS

TUA 2005
Bipolar Television Tuner Ie
for Frequency Ranges up to 700 MHz
• Symmetrical Mixer Output

RF Section
• Few External Components

• Low-Noise, Internal Reference Voltage

• Frequency and Amplitude-Stable Oscillator
• Optimal Suppression of Oscillator and Input
Frequency at IF Output

IF SAW Driver Section
• Optimal Crosstalk Suppression

• High Resistance to Interference Voltages

• High-Impedance, Asymmetrical Input with
High Signal Modulation Capability

• High-Impedance Symmetrical Mixer Input

• Low-Impedance Symmetrical Output for
, Driving SAW Filters

• IF Post-Amplifier for UHF-IF Signal

Pin Configuration

Pin Definitions

(Top View)

11:

'-./

2C
3C
4C
sC
6C
7C
8C

Pin

Function

1

Low-Impedance Symmetrical Output of SAW
Driver
Low-Impedance Symmetrical Output of SAW
Driver Anti-Phased to Pin 1
GND
High-Impedance Input of Oscillator Amplifier
Low-Impedance Output of Oscillator
Amplifier
Oscillator Signal Output for PLL Systems
with Possible Open Collector Output
Blocking Capacitor for Controlling Oscillator
Amplitude
Symmetrical Mixer Output
Symmetrical Mixer Output Anti-Phased
to Pin 8
Switching Voltage Input for VHFIUHF
Switch-Over
High-Impedance Asymmetrical RF Input for
UHF-IF Signal
High-Impedance Symmetrical RF Input of
VHF Mixer
High-Impedance Symmetrical RF Input of
VHF Mixer, Anti-Phased to Pin 12
Supply Voltage
Blocking Point of Internal Reference Voltage
High-Impedance Asymmetrical IF Input of
SAW Driver

2

P;6
P1S
tJ 14
:::J13
:::J12
:::Jll
:::Jl0
:::J9

3
4
5
6

7
8

0089-10

9
10
11
12
13
14
15
16

The TUA 2005 has been designed as a monolithically integrated circuit suitable as a TV tuner for a CATV
frequency range extended to 700 MHz.

@Siemens Components, Inc.

7-147

April 1988

TUA 2005

Block Diagram
16

15

0089-1

Circuit Description

During UHF operation the oscillator and the mixer
are disabled and the asymmetrical, low-noise UHFIF coupling stage is activated.
-

RFSectlon
The integrated circuit includes a symmetrical highimpedance, low-noise mixer input and a multiplicative mixer.
The amplitude of the oscillator is controlled for maintaining suitable resonant circuit voltages cif the oscillator circuit. All operating currents and voltages of
the oscillator are intemally stabilized. The amplitude
and the frequency of the' oscillator are therefore
largely independent of changes in temperature or
operating voltages.

7-148

IF SAW Driver Section
The IF SAW driver includes a high-impedance,
asymmetrical input. The low-impedance symmetrical
output of the IF SAW driver has two open collectors.
The basic volume and the output resistance can be
further reduced by an ohmic symmetrical load resistor. When the operating voltage is not connected to
the collectors, the current consumption of the IF
SAW driver section is zero. The signal modulation
capability of the Ie depends on the connected supply voltage.

TUA 2005

Absolute Maximum Ratings·
Vs = 10V to 13.5V
Supply Voltage (Vs) .........•.... -0.3V to + 14V

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Current from Pin 15 (-115)' ....•.•... 0 mA to 2 mA
Voltage at Pin 1 (VI) ................. -0.3V to Vs
Voltage at Pin 2 (V2) ................. -0.3V to Vs
Voltage at Pin 8 (Va) .....•.............. V14 to Vs

Operating Range

Voltage at Pin 9 (V9)' .......•........... V14 to Vs

Supply Voltage (Vs) ................. 1OV to 13.5V

Voltage at Pin 10 (V1Q) .............•. -0.3V to Vs

Mixer Input Frequency (fM) ..... 20 MHz to 650 MHz

Capacitance at Pin 15 (CI5) ......... 0 nF to 100 nF
Capacitance at Pin 7 (C3) ............ 0 /LF to 1 /LF

UHF-IF Input Frequency
(fUHF) ..................... 20 MHz to 650 MHz

Only the provided external components can be connected to pins 4, 5, 6, 11, 12, 13, 16.

Mixer IF Output
Frequency (fMIF) ............ 20 MHz to 650 MHz

Junction Temperature (Tj) .................• 150·C

Oscillator Frequency (fosC> .... 20 MHz to 700 MHz

Storage Temperature (T5tg) ..... - 40·C to + 125·C

Voltage at Pin 8,9 (Va, 9) ................ V14 to Vs

Thermal Resistance (RthSA)
.
(System-Air) .......................... 80 K/W

Voltage at Pin 1,2 (VI, 2) ................. 5V to Vs

Characteristics

Vs

Parameter

=

12V, TA

=

Ambient Temperature (TA) .......... O·C to + 70·C

25·C

Symbol

Test Conditions

limits

Test
Circuit

Min

Typ

Max

1

18

28

37

mA

7.5

8

8.5

V

700

MHz

-500

kHz

-250

+250

kHz

7

Vs

V

0

3

V

Units

RFSectlon
Current Consumption

114

115

Reference Voltage

=

OmA;V1Q

=

Vs

V15

0:::: 115:::: 1 mA

1

Oscillator Frequency
Range

fosc

External Circuitry Tuned
to Frequency

1

Turn-On Start-Up Drift

~fosc

TC Value of Cap. in Osc.
Circuit is 0; Drift is Only
Referenced to Self-Heating
of Component.
t = 0.5s to 10s
ChannelS20

1

48

0

Frequency Drift
versus Vs

-~fosc

Vs = 10Vto 13.5V
S20

1

UHF Switching Voltage

Vl0

VI(U) = - 25 dBm;
Va:?! -5dBm

1

VHF Switching Voltage

Vl0

VI(U) = - 25 dBm;
Va:::: -30dBm

1

Output Impedance

Za; Z9

Static

7

10

Output Capacitance

Ca

6

0.5

=

C9

-100

kO
1

2.0

pF

7-149

TUA 2005

Characteristics

Vs

= 12V, TA = 25°C(Continued)

Parameter

Symbol

Test Conditions

Test
Circuit

Limits

Units

Min

Typ

Max

140

180

220

degrees

25

27

29

dB

25

27

29

dB

25

27

29

dB

31

33

35

dB

RF Section (Continued)
RF Output Phase

as.s

Mixer Gain

Gs

Mixer Gain

Channel 3; RG

= 100n
= 100n

1

Channel 9; RG
f = 294.25 MHz

= 100n

Mixer Gain

GS20

Channel S20; RG
f = 294.25 MHz

Mixer Gain

G21
Wt21

Channel Wt21; RG
f = 421.25 MHz

UHF·IFGain

UHF

Mixer ~oise Figure

NFs

Mixer Noise Figure

NFs

= 200n; flF = 36.5 MHz
Channel 9; RG = 100n
f = 203.25 MHz
Channel 3; RG = 100n
Channel S20; RG = 100n
Channel 21; RG = 100n
RG = 200n
RL = 200n; Channel 3

Mixer Noise Figure

NFS20

Mixer Noise Figure

NF21

UHF·IF Noise Figure

NFUHF

qscillator Output
Signal for PLL or
Frequency Divider

V6

= 100n

RG

1
1
1

1

8

dB

1

10

dB

1

14

dB

1

7

dB

-17

dBm

28

mA

1
-27

S20

SAW IF Driver

= 12V

17 .

Current Consumption

11+ 12

Vs

Input Impedance

Z16

S-Parameter
Measurement

2

Input Capacitance

C16

S·Parameter
Measurement

2

Symmetrical
Output Resistance

Iz%1

S-Parameter
Measurement

5

Linearity
(Permissible Input Signal)

V16

ms = 80%; fs = 36.5 MHz
Total Harmonic Distortion
of Output Signal
Va is THO = 1%

3

Noise Figure

NF

RG

Gain

G

RL

7·150

= 200n
= RG = 50n

.

50

22
3

kn

1.5

pF

100

250

4

10

3

-16

200

n

mV

dB
dB·

TUA 2005

Measurement Circuit 1

+Vs
10pF

VHFIUHF

lnF

Swl1ch-Ove,

10nF

16

15

TUA 2005

15pF

8,2pF

-'~
330 II
10 nF

I
I

HI.I
I
I
I
L.+...!'L ___ J

Swilchlng
Voltage Bd 1/111

Swt1chlng Section can be
Added WRequired

Tuning valtage + Va
0089-2

Measurement Circuit 2
+Vs-12V
10nF
BAWdrlve,
TUA2005

1

0089-3

The Input reflection factor S16 is measured at 36.5 MHz for computing the parallel equivalent circuit.

7·151

TUA 2005

Measurement Circuit 3
10nF

'Ill. Input capacHanc. 01
"'.BAWI_ls
com_ted with
this col
0089-4

Measurement Circuit 4

/

'Ill. Input cepacHance
01 the BAW nller
Is compen88ted
wlthlhlacoH
0089-5

Measurement Circuit 5
IOnF
BAWD....,
1UA2005

1

lnF 16

f.

v,.

The 4-pole matrix 811. 812. 821. 822 is measured at 36.5 MHz for computing that

7-152

'/I"

....-.

equivalent circuit.

TUA 2005

Measurement Circuit 6

I
I 10mH

I..b

'10nF

I

I
110mH
I

TUA 2005
18
• • 1nF

I

I

Natwork Analyse,

0089-7

The 4-pole matrix 581.582.591.592 is measured at 100 MHz for computing the output capacitance.

Measurement Circuit 7 Measurement of Static Output Impedance
I,,(/IJI

t
Vs

I,
I,

--1-~------------1----I

i

I

f-.w--l

I
Ze3 = AV83
Ale3

I

I

i

9,5

13,5

......

Z93 = AV93
AI93

0089-8

Ordering Information
Ordering Code
Q67000-AB033

7·153

SIEMENS

TUA 2006
Television Tuner for
Frequency Ranges up to 700 MHz
• Symmetrical Mixer Output

RFSection
• Few External Components

• Low-Noise, Internal Reference Voltage

• Frequency and Amplitude-Stable Oscillator '
• Optimal Suppression of Oscillator and
Output Frequency at IF Output

IF SAW Driver Section
• Optimal Crosstalk Suppression

• High Resistance to Interference Voltages

• High-Impedance, Asymmetrical Input with
High Signal Modulation Capability

• High-Impedance Symmetrical Mixer'lnput
• IF Post-Amplifier for UHF-IF Signal

• Low-Impedance Symmetrical Output for
Driving SAW Filters

Pin Definitions
Pin
1

Function
Low-impedance symmetrical output of SAW driver

2

Low-impedance symmetrical output of SAW driver anti-phased to pin 1

3

GND

4

High-impedance input of oscillator amplifier (VHF)

5

Low-impedance output of oscillator amplifier (VHF)

6

Oscillator signal output for PLL system and divider

7

Low-impedance output of oscillator amplifier (hyperband)

8

High-impedance input of oscillator amplifier (hyperband)

9

Blocking capacitor for controlling oscillator amplitude

10

Symmetrical mixer output

11

Symmetrical mixer output anti-phased to pin 10

12

Switching voltage input for VHF/hyperband/UHF switch-over

13

High-impedance asymmetrical RF input for UHF-IF signal

14

High-impedance symmetrical RF input of hyperband mixer

15

High-impedance symmetrical RF input of hyperband mixer anti-phased to pin 14

16

High-impedance symmetrical RF input of VHF mixer

17

High-impedance symmetrical RF input of VHF mixer anti-phased to pin 16

18

Supply voltage

19

Blocking point of internal reference voltage

20

High-impedance asymmetrical IF input of SAW driver

The TUA2006 has been designed as a monolithically integrated tuner circuit suitable as a TV tuner for a CATV
frequency range extended to 700 MHz.

@Siemens Components, Inc.

7-154

April 1988

TUA 2006
Block Diagram
20

11

Switching
Stage

OFWIF
Driver

0090-1

Circuit Description

During UHF operation both the oscillator and the
mixer are disabled and the asymmetrical, low-noise
UHF-IF coupling stage is activated.

RFSection
The integrated circuit includes a symmetrical highimpedance, low-noise mixer input and a multiplicative mixer.
The amplitude of the operating oscillator is controlled for maintaining suitable resonant circuit voltages of the oscillator circuit. All operating currents
and voltages of the oscillator are internally stabilized. The amplitude and the frequency of the oscillator are therefore largely independent of changes in
temperature or operatinQ voltages.

IF SAW Driver Section
The IF SAW driver includes a high-impedance,
asymmetrical input. The low-impedance symmetrical
output of the IF SAW driver has two open collectors.
The basic volume and the output resistance can be
further reduced by an ohmic symmetrical load resistor. When the operating voltage is not connected to
the collectors, the current consumption of the IF
SAW driver section is zero. The signal modulation.
capability of the Ie depends on the connected supply voltage.

7-155

TUA 2006

Absolute Maximum Ratings'"
Vs = 10V to 15.5V
Supply Voltage (Vs) .............. -0.3V to + 14V
Current Form Pin 15 (-115) .......... 0 mA to 2 mA
Voltage at Pin 1 (V1) ................. -0.3V to Vs
Voltage at Pin 2 (V2) ................. -0.3V to Vs
Voltage at Pin 8 (Vo) .................... V14 to Vs
Voltage at Pin 9 (Ve) .................... V14 to Vs
Voltage at Pin 10 (V10) ............... -0.3V to Vs
Capacitance at Pin 15 (C15) ......... 0 nF to 100 nF
Capacitance at Pin 7 (Cs) .....•...... O,...F to 1 ,...F
Only the provided external components can be connected to pins 4,5,6,'11,12,13,16.
Junction Temperature (Tj) ......••.......... 150·C
Storage Temperature (Tstg) .•... -40·C to + 125·C
Thermal Resistance
System-Air (RthSA) .......•.. '.......... 80 K/W

Characteristics

Vs

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Operating Range
Supply Voltage (Vs) ................. 10Vto 13.5V
Mixer Input Frequency (fM) •.... 20 MHz to 650 MHz
UHF-IF Input
Frequency (fUHF) ........... 20 MHz to 650 MHz
Mixer IF Output
Frequency (fMIF)' .....•....• 20 MHz to 650 MHz
Oscillator Frequency (fosC> .... 20 MHz to 700 MHz
Voltage at Pin 8, 9 (Vo, 9) ........ · .•• · ... V14 to Vs
Voltage at Pin 1,2 (V1, 2) ................. 5V to Vs
Ambient Temperature (TA) ............ O·C to 70·C

= 12V; TA = 25·C

Parameter

Symbol

Conditions

Limits

Test
Circuit

Min

Typ

Units
Max

RFSectlon

= 0 mA, V12 = Vs

Current Consumption

110

119

18

30

40

Reference Voltage

V19

o s: 119 s: 1 mA

7.5

8

8.5

Oscillator Frequency
Range

fOSCVHF

Ext. Circuitry Tuned
to Frequency

48
48

500
700 .

MHz
MHz

Turn-On Start-Up
Drift

afosc hyperb. TC Value of Cap. in Osc.
Circuits is 0; Drift is Only
Referenced to Self-Heating
of Component
t = 0.5 sec. to 10 sec.;
ChannelS20

0

-100 -500

kHz

mA
V

Vs = 10V to 13.5V
S20

-:2'50

+250

kHz

UHF Switching Voltage V12,

VI(U) = -25 dBm;
Va;;:: -5dBm;

8.5

Vs

V

VHF Switching Voltage V

VI(U) = -25 dBm;
VaS: -30dBm;

0

3

V

4.5

7.5

V

Frequency Drift
versus Vi,

-afosc

Hyperband Switching
Voltage

V

Output Impedance

Z10; Z11

Output Capacitance

C10

RF Output Phase

a10,11

Mixer Gain VHF

Ga

7-156

Static

= C11

6

10

5
Channel 3; RG = 100n
f = 55.25 MHz

i

kn

0.5

1

2.0

pF

140

180

220

degrees

25

27

29

dB

TUA 2006

Characteristics

Vs = 12V; T A = 25°C (Continued)
Symbol

Parameter

Conditions

Test
'Circuit

Limits

Units

Min

Typ

Max

25

27

29

dB

25

27

29

dB

25

27

29

dB

31

33

35

dB

8

dB

RF Section (Continued)
Mixer Gain VHF

Mixer Gain
Hyperband

Gg

Channel 9; RG = 100n
f = 203.25 MHz

GS20

Channel S20; RG = 100n
f = 294.25 MHz

G3

Channel 3; RG = 100n
f '= 55.25 MHz

Gg

Channel 9; RG = 100n
f = 203.25 MHz

GS20

Channel S20; RG = 100n
f = 294.25 MHz

1

1

UHF-IF Gain

GUHF

RG=200n; fIF=36.5MHz

Mixer Noise Figure VHF

NF3

Channel 3; RG = 100n
f=55.25 MHz

NFg

Channel 9; RG = 100n
f= 203.25 MHz

NFs20

Channel S20; RG = 100n
f = 294.25 MHz

10

dB

NF3

Channel 3; RG = 100n
f=55.25 MHz

8

dB

NFg

Channel 9; RG = 100n
f = 203.25 MHz

NFS20

Channel S20; RG = 100n
f=294.25 MHz

10

dB

NFUHF

UHF; RG = 200n

14

dB

V6

RL = 50n; Channel 3...S20
-6

dBm

32

rnA

Mixer Noise Figure
Hyperband

Mixer Noise Figure
Oscillator Output
Signal for PLL or
Frequency Divider

-20

SAW IF Driver
Current Consumption

11

Input Impedance

+ 12

19

25

Z20

S-Parameter, Measurement

1

3

kn

Input Capacitance

C20

S-Parameter, Measurement

1

1.5

pF

Symmetrical
Output Resistance

IZV21

S-Parameter,
Measurement

4

Linearity
(Permissible Input Signal)

V20

ms = 80%; fs = 36.5 MHz
Total Harmonic Distortion
of Output Signal Va
isTHD = 1%

2

,

50

100

200

n

250

mV

Noise Figure

NF

RG = 200n

3

10

dB

Gain

G

RL = RG = 50n

2

-16

dB

\

7-157

TUA 2006

Measurement Circuit 1
+Vs-t2V
10nF

SAW Driver
TUA2006
SAW
Filter

0090-'

The input reflection factor S'6 is measured at 36.5 MHz for computing the parallel equivalent circuit.

Measurement Circuit 2
+Vs-12V
10nF

/

The Input capacitance 01 the
SAW filter Is compensated
with this coil
0090-3

Measurement ~Ircult 3
+Vs-12V
10nF
SAW Driver
TUA2006
1

H

I
The Input capaCitance
01 the SAW filter
Is compenssted
with this coli
0090-4

7·158

TUA 2006

Measurement Circuit 4
+Vs·12V

HH

SAW Dnvar
TUA2006

1
SAWFIllar
OFWG3203

(ZPH
=i"'lnF

I

=.. lnF

Network Analyser

I

~
yr, yrr
0090-5

The 4-pole matrix 51" 512. 521. 522. is measured at 36.5 MHz for computing the.". equivalent circuit.

Measurement Circuit 5

I
I 10mH

=io-l0nF

I
110 mH
I

I

r;;-TUA 2006
110

-F-lnF

I

-·1 nF

Network Analyser

I

....-.

The 4-pole matrix 581.582.591.592. is measured at 100 MHz for computing the output capacitance.

7-159

TUA 2006

Measurement Circuit 6

I,
II

--1--~-------------f--------, ,i
I

I
,
,

I
I

t-.:lv-j
I

!
9,5

I

!
13,5 V
~V9](V8])
0090-8

0090-7

Ordering Information
Ordering Code
Q67000-A8045

7-160

ICs for Radio! Audio Applications

SIEMENS

S041 P
FM IF Amplifier with Demodulator
5041 P is a symmetrical, six-stage amplifier with symmetrical coincidence demodulator for amplifying, limiting, and demodulating frequency-modulated signals. The Ie is particularly'suited for
sets where low current consumption is of importance, or where major supply fluctuations occur.
The pin configuration corresponds to the well-known TBA 120. Pin 5 of S 041 P, however,
is not connected internally. These types are especially suited for applications in narrow-band
FM systems (455 kHz) and in conventional or standard FM IF systems (10.7 MHz).

Features

•
•
•
•

Good limiting properties
Wide voltage range
Low current consumption
Few external components

Maximum ratings
V

Tstg

15
150
-40 to 125

RthSA

90

K/W

Vs

Supply voltage
Junction temperature
Storage temperature range

1j

°C
°C

Thermal resistance (system-air)
S 041 P

Operating range
Supply voltage range
Frequency range
Ambient temperature range

Vs
fl
Tamb

8-1

14 to 15
o to 35
-25 to 85

1

~HZ
°C

S041P

Characteristics (VS == 12 V, Q approx. 35, f mod = 1 kHz, Tamb = 25 DC)

Current consumption
AF output voltage
(fl -10.7 MHz, .df- ± 50 kHz, VI ~10 mV)
Total harmonic distortion
(fl -10.7 MHz, .df- ± 50 kHz, VI-10 mV)
Deviation of AF output voltage
(VS -15 V~ 4 V, fl -10.7 MHz,
.df- ±50 kHz)
Input voltage for limiting
(fl -10.7 MHz, .df-±50 kHz)
IF voltage gain (fl-10.7 MHz)
IF output voltage for limiting
(each output)
Input impedance fl = 10.7 MHz
fl =455 kHz
Output resistance (pin 8)
Voltage drop at AF ballast resistance
AM suppression
(VI ~ 10 mV, Llf= ± 50 kHz, m" 30%)

min

typ

max

Is

4.0

100

5.4
170

6.8

Vqrms ,

0.55

'1.0

THO

1.5
30 ,

Vqpp
ZI
ZI
Rq

3.5

aAM

All connections mentioned in the index refer to S 041 P (e.g. V11 )

Test circuit

10nF

f, =10.7MHz
V,

14
r-It----.-----O---I
220pF

8-2

12 turns
0.25 (uLS

%

dB

60

f.LV

68'

dB

130
20/2

mV
kO/pF
kO/pF
kO

50/4
5

1.5
60

V11 - 8

'mA
mV

8.5

V
dB

~1l

c

::;:
Q,

iii'

CQ

11

8

ii1
:I

6kr!

12x
700r!

4.2kr!

Skr!

Skr!

Skr!

Skr!
1.7kr!

3.6kr!

3.6kr!

S.5kr!

Skr!

110

4

13

10

2 6 9

7

en

o

~

:!t
"0

8041 P

Application circuit for 10.7 MHz (FM IF)
and 455 kHz (narrow-band FM)

220pF

L2

Data in parentheses for 455 kHz (narrow- band FM)

Coils

10.7 MHz

455 kHz

L,

15 turns/0.15 CuLS
12 turns/0.25 CuLS
041-2165

71.5 turnsl12 x 0,04 CuLS
71.5 turns/12 x 0.04 CuLS
o 41-2393 of Messrs. Vogt

L2
Coil set

8·4

S041P

AF output voltage and total
harmonic distortion versus
supply voltage
fl =10.7 MHz; Af-±50 kHz
mV fmod =1 kHz; a approx. 35

Current consumption
versus supply voltage

mA

%

5

250

10

v"Frms

r 200

.,

.'"

...

6

5

i-"

...

4

I

3

II"

"""'

.... ~

150

.....

I
100

-

"--

2

~

~

---

3

- --

2

~,

-mean value
--- max value -

II

r

, ~ '1'"

--

,

I--

50
THO

o
o

10

5

o

15 V

-\'s

o

2

4

6

8

--"'"

10

12

--- 0

14 16 V

-L's

DC output voltage difference
versus supply voltage
(without signal)

V

Input voltage for limiting
versus supply voltage
fl -10.7 MHz; Af-± 50 kHz
IJV fmod -1 kHz; a approx. 35

3

160
~lim 140

t

120

2

100

/

80

~

60

J

I

\

40

--

----- ---

I

r-.....
20

o

o

2

4

6

8

10 12 14 16 V
_Vs

'-

o

o

2

4

6

B

ro n

~

~V

-\'s
8-5

S041P

AM suppression versus
supply voltage·
fl=10.7 MHz; ~f=±50 kHz;
'" -10 mV, fmod -1 kHz, m =-30%

AF output voltage and total
harmonic distortion Versus Q..factor
Vs =12 V; f; =10.7 MHz,
~f=±50 kHz, fmod -1 kHz

dB

mV
300

0/0

80

1.5

r

V.

fflO

i

If

,J

50

1.0

1----j---j---j------2<----j

200

40
30

0.5

100

20
10

THO generator =0.3 %

0

0
0

2

4

6

8

10

12

-Vs

8-6

14 16V

0
0

10

20

30

40

50
- Q fl1ctor

SIEMENS

S042P
Mixer
Symmetrical mixer for frequencies up to 200 MHz. It can be driven by an external source or by the
built·in oscillator. The input signals are suppressed at the outputs. In addition to the
usual mixer applications In receivers, converters, and demodulators for AM avd FM, the
S 042 P can also be used as electronic polarity switches, multipliers, etc.

Features
•
•
•
•
•

Versatile application
Wide range of supply voltage
Few external components
High conversion transconductance
Low noise figure

Maximum ratings
Supply voltage
Junction temperature
Storage temperature range

Tj
Tstg

Thermal resistance (system-air) S 042 P:

Rth SA

Vs

15
150
-1\0 \0125
90

IJ

'C
'C
K/W

Operating range
Supply voltage range
Ambient temperature range

Vs
Tamb

8·7

14 to 15
-15 to 70

\ ~c

Ii

S042P

Characteristics (VS "" 12 V.

Tamb -

Current consumption
Output current
Output current difference
Supply current
power gain
(fl -=100-MHz. fose -110.7 MHz)
Breakdown voltage
(h.~ -10 mf.; V7.8 -0 V)
Output capa:itance
Conversion tansconductance
(f =455 kHz
Noile figure

25°C)
min

typ

max

2.15
0.52

2.9
0.68
60
1.6

Gp

1.4
0.36
-60
0.7
14

V2• V3

25

Is - 12 + 13 + Is
12 -13
13-12
Is

C2-M.C3-M

12

s---V7 -VS

13
V7 -Va

NF

All ()nnections mentioned in the index refer to S 042 P (o.g. 12 )

\
Testcrcu~
.---1~t-----{ ~ - 12V

"F= 10.7 MHz

t

..

~ 3/3 turns

10nF

fast -110.7 MHz

Connections in parentheses apply to S 042 E

8-8

1.1
16.5

mA
mA
mA
mA
dB
V

6

pF

5

mS

7

dB

S042P

Circuit diagram

5

2

3

Bkn
7
2.2kn

2.2kn
B
11

3.3kn

13

1.4kn
~------~-+--l-~---o

12

1,4,6,9,14

10

A galvanic connection between pins 7 and 8 and pins 11 and 13 through coupling windings
is recommended.
Between pins 10 and 14 (ground) and between pins 12 and 14, one resistance each of at
least 220 Q may be connected to increase the currents and thus the conversion transconductance. Pins 10 and 12 may be connected through any impedance. In case of a direct
connection between pins 10 and 12, the resistance from this pin to 14 may be at least
100 Q. Depending on the layout, a capacitor (10 to 50 pF) may be required between pins 7
and 8 to prevent oscillations in the VHF band.

8-9

•

S042P

Output current versus
supply voltage

Total current consumption
versus supply voltage
~A

rnA
4

800
- - - ----

f - t--

--

f- f-

--

V

2

v'

V
t.....

~

...

"

~

l,.;'

V

~

.....

~,

..

f'"

- t;;

~

~

",

I....-" -- -

...

..

~.

~" -

-

-

....

--

e-.-

~

...

-

500

.

..... 1.-'

dB
18

----

I .
.... ~

......

;.....

..... ~

-

~

I

._--

I
-~-

1--

iI

-

12

II

8
6
4 5 6 7 8 9 10 11 12 13 14 15 V

-Ys
8-10

400

-

300

~.

i- • ~

~

.~

i-

t...-

I

- 1-1
I-

I

H

1--

o

Power gain verSus
supply voltage

10

~

-

100

-Vs

14

....

I I.

4 5 6 7 8 9 10 11 12 13 14 15 V

16

-I-

-.-

.

200

..... 1"'"

o

1

~~

""""
~

. -

~

nn B
-Ys

4 5 6 7 6 9 W

~ ~V

S042P

Application circuits
VHF mixer with inductive tuning

Mixer for remote control receivers
without oscillator

1O.7MH:z:

mM~'
I

I
I
I

I
IL

___ _

For overtone crystals an adequate
inductance is recommended between
'pins 10 and 12 to avoid oscillations to the
fundamental tone.

Mixer for short-wave application

in self-oscillating operation

10nF

l-41--e-~--'

Differential amplifier with internal neutralization, also suited for use as limiter
for frequencies up to 50 MHz or at
higher currents up to 100 MHz

1.6 ... 4.8MHz

ffi:"

I

I
I

I
I
I

i
I
I
IL ____ _

4.7nF
40 turns

1.4.6,9,14

8-11

SIEMENS

SDA 2121
CMOS PLL with 12C Bus for AM/FM Receivers
• High Input Sensitivity
(50 mVrms on FM and 10 mVrms on AM)

• Adjustable Raster Width
« 1 KHz for AM, < 12.5 KHz for FM)*

• High Input Frequencies
(150 MHz on FM and 35 MHz on AM)

• Two-Pin Oscillator Provides Connection of
a Piezoelectric Crystal for Reference
Frequency Generation

• Extremely Fast Phase Detector with Very
Short Anti-Backlash Pulses
'
.,2C Bus

• Switchable Phase Detector Polarity
• Switchable Phase Detector Current
(0.25/1 mA)

• Large Divider Rations:
-16 Bit N Divider
-16 Bit R Divider
- Divider Factor Without Vacancy
OSCIN 2-65535
AM IN 2-65535
FMIN/2 2-65535 .

• One Phase Detector Output Each for FM
and AM with the Corresponding Analog
Phase Detector Outputs
• Open Drain Band Selection Outputs for 10V
~Raster width

= Input Frequency/Divider Factor
[On FMIN input frequenCY/2 is to be used due to the prescaler)

Pin Configuration
(Top VIew)
Veo

I

.0 GNDi
19 OSCOUT

SeL 2
SDA

3

18 OSC'N

AD

4

l1LD

PAT 5

16 PDAMA

awl

6

15 POAM

8W2

•

14 POFM

BW3

8

13 POFMA

FM

9

12 AM..

FMIN 10'

"

GND2
00&7-4

The SOA 2121 is an integrated circuit in CMOS technology which has been especially deSigned for application
in radio eqUipment. It serves as a PLL for frequency synthesis concepts.

@)Siemens Components. Inc.

8-12

April 1988

SDA 2121

Pin Definitions
Pin

Symbol

Function

1

VOO

Supply Voltage

2

SCl

12C Bus Clock

3

SDA

12C Bus Data Input and Acknowledge Output
Address Input

4

AO

5

PRT

Port Output (Only with 20-Pin Packages)

6

Band Selection Output (Open Drain Output for 10V)

8

BW1
BW2
BW3

9

FM

10

FMIN

7

Band Selection Output (Open Drain Output, 10V)
Switching AM/FM Operation
FM Input

11

GND2

Ground Connection for AM and FM Amplifier

12

AMIN

AM Input

13

PDFMA

14
15

PDFM
PDAM

16

PDAMA

17

lD

18
19

OSCIN
OSCOUT

20

GND1

Analog Output Corresponding to the Phase Detector
Output, in Test Operation Open Drain Output of FVN
Signal
Phase Detector Output for AM or FM Active or
Tristate Depending on Operating Mode
Analog Output Corresponding to the Phase Detector
Output, in Test Operation Open Drain Output of FRN
Signal
lock-Detect Output (Only with 20-Pin Packages)
Connection for Reference Oscillator Input or Output
Ground

Circuit Description
The SDA 2121 is a complex Pll component in
CMOS technology for processor controlled frequency synthesis.
Function, and dividing ratios are selected via an 12C
bus interface (licensed by Philips) at pins SCl, SDA
'and AO. The chip address is set via address input
AO. Thus it is possible to address two components
via the 12C bus. The reference frequency can be applied at input OSC IN or it can be gererated internally
by a piezoelectric crystal. Its maximum value is

15 MHz. The VCO frequency is applied at input FM
or AM respectively. Its maximum value is 150 MHz at
the FM input and 35 MHz at the AM input. The FM
input signal is divided by two by an asynchronous
prescaler.
Outputs PDFM and PDAM supply the phase detector signal with especially short anti-backlash pulses
to neutralize even the smallest phase deviations.
Polarity and current of the PD outputs can be
switched. The component also has corre~ponding
analog phase detector outputs. A lock-detect output
(lD) and a port output (PRT) are provided on the 20pin version.

8-13

•

SDA 2121

Absolute Maximum Ratings·

Operating Range

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Within the functional range, the integrated circuit operates as described; deviations from the characteristics data are possible.

Pos

Parameter

Limits

Symbol

Units

Min Typ Max
Supply Voltage (Voo) ................ -0.3V to 6V
Input Voltage (VI)' ..•.•.•.••. -0.3V to Voo + 0.3V
Power Dissipation per
Output (Po) ..........•...•...•.•...... 10 mW
Tolal Power Dissipation (Ptot> •....•..•.•. 300 mW
Storage Temperature (TS) •.•••• - 4,o·C to + 125·C
Output Voltage Band Selection
Outputs (VOH) ...•...............•.•.... 10.5V

1 Supply Voltage

Voo

2 Supply Current

4.5

5

5.5

V

100

10

mA

3 Bias Current

100

30

,."A

4 Ambient
Temperature

TA

+85

·C

-25

5 Output Voltage VOH
Band Selection
10
V
Outputs
.. for pos. 2
..
Test Conditions
Test conditions for pos. 3
- Vee = 5.5V
-Voe = 5.5V
-TA = 25°C
-TA = 25°C
- Outputs not connected
- FM. AM, OSCIN on Vee
- No test operation
- Outputs not connected
- No test operation
- Max.. permissible
operating frequency
on AM, FM, OSCIN
- VIFM, VIAM. VIOSCIN minimal
- Minimal divider ratios
- PLL in in-lock condition

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
apply at TA = 25·C and the listed supply voltage. (All voltages referenced to GND.)

Pos

Parameter

Symbol

limits

Conditions
Min

Typ

Units
Max

Input Signals SCl, SDA, AO
1

H Input Voltage

VIH

0.7 X Voo

Voo

V

2

L Input Voltage

VIL

0

0.3 X Voo

V

3

Input Capacitance

CI

10

pF

4

Input Current

II

VI = Voo

10

,."A

Input Frequency

f

Voo = 4.5V

15

MHz

10

Input Voltage

VI

(Sine Wave)

11

Input CapaCitance

CI

12

Input Current

I,

Input Signal OSCIN
9

8-14

V, = Voo

100

mVrms
10

pF

10

,."A

SDA 2121

Characteristics (Continued)
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
apply at T A = 25·C and the listed supply voltage. (All voltages referenced to GNO.)
Pos

Parameter

Symbol

Limits

Conditions
Min

Typ

Units
Max

Input Signal AM

=

13

Input Frequency

f

Voo

14

Input Voltage

VI

(Sine Wave)

15

Input Capacitance

CI

16

Input Current

II

VI

=

35

4.5V
10

MHz
mVrms

Voo

10

pF

10

/LA

150

MHz

Input Signal FM

=

17

Input Frequency

f

Voo

18

Input Voltage

VI

(Sine Wave)

19

Input Capacitance

CI

20

Input Current

II

VI

=

4.5V
50

mVrms

Voo

10

pF

10

/LA

Output Signal PDFM (Tristate Output)
21

PO Current "High"

10

Voo

22

PO Current "Low"

10

TA

23

PO Current "Tristate"

= 5V

=

-25·C to +60·C

10

±1

mA

±0.25

mA

±50

nA

±1

mA

±0.25

mA

±50

nA

Output Signal PDAM (Tristate Output)
24

PO Current "High"

10

Voo

25

PO Current "Low"

10

TA

26

PO Current "Tristate"

10

=

=

5V

-25·Cto +60·C

Output Signal PDAMA, PDFMA (Analog Output)
27

H Output Current

10H

Vpo

= Voo

28

L Output Current

10l

Vpo

=

GNO

1
0.1

0.5

2

mA
mA

voo
[)

PDAM,PDFM

3k

---4 f---+ PDAMA,PDFMA

[J

22k
0087-1

8-15

'SDA 2121

Characteristics (Continued)
The listed characteristics are ensured over the operating range of the integrated circuit Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
apply at TA = 25°C and the listed supply voltage. (All voltages referenced to GND.)
Pos

Parameter

Symbol

Limits

Conditions
Min

Typ

Units
Max

Output Signal FVN, FRN (Open Drain Outputs, Active only In Test Operation)
29

L Output Voltage

30

H Output Voltage

VOH

31

Fall Time

taF

32

Rise TIme

taR

Val

*

V

•
•
•

V
ns
ns

Output Signal LD (Open Drain Output)
33

34

L Output Signal

. L Output Pulse Width

Val

IOl = 3mA
Voo = 5V
CL = 20pF

0.4

*

taWl

-::+::10,::

Vo<-

V
ns

_

. .#!~~.!.~~--------.
---

0097-2

Output Signal PRT
35

H Output Voltage

VOH

IOH = 0.5mA

36

L Output Voltage

Val

IOl = 0.5mA.

V

Voo - 0.4
0.4

V

Output Signal OSCOUT
37
38

H Output Voltage
L Output Voltage

Val

•

Val

•

Output Signal BW 1,2, 3 and FM (Open Drain Band Selection Outputs)
39

L Output Voltage

Val

IOl=1mA
Voo = 5V

0.4

V

Val

IOl=3mA
Voo = 5V
CL = 400pF

0.4

V

Output Signal SDA
40

L Output Voltage

·Values not available at this time.

8-16

!!!

Ia

OSC'N

•_n_QBin_ nn_ n_____n_ :I_-__

n~~~~~=----nh---n~==~]~---------i---------n---

D

OSCoUT

11'

16·Bit Latch

----:rr

SDA

;4--+1

16-BI' i·SlR

DAI

FC
Interface

"'d

- AO

I

Clock
Latch
enable

c::::::+f
t-

B· Bit Latch

I

,I

iJ
a·Bit SR

AM'N

:

t
:
I

Source

I
I

I

FM

:

Curren
Source

1PDFM

'----10

-.,.

FM'N

PDAM

:

(Digital)

Lock
Detector

BW3

I

r- Current
AM
~i~

-~

BW2

; PDAMAlFR

Follower

Phase

DJ
3

t~

~r AM Source

U

II.

~

I

16·B,t Latch

16·B,t N Divider

-nl ::,

I

16·Bit SIR

i

:

I
I

:

I
I

4PDFMAlFvt
I

:

'------------+~ ~ LD

--~------_e---------.----------------------------------

GND2

GNDI

______ . __________________________________________________

I

VDO
0097-3

(I)

g
cp
....
...,

....NN

•

....

SDA 2121

Application Circuit

I

I

pP

Vee

!)

f
SCL

rH
H

R:
I

SOA

\

~

VOO

LO

POAM
AO
POAMA

-

OSC e••

SDA2121

LF

---- veo

L

1

+ !~f301"

OSC,
POFM

AM TU.ner

,

e-fr1.J::"-r 10.
-:--'

FM
Tuner

veo

I

~~

POFMA

LF
G'IOl

AM

FM

G'IOZ

-.L

==

==

--

Status Programming Tabla
Bit

Paramater

1
2
3

PRT
BW1
BW2
BW3
FM
PO analog/test
PO polarity
PO current

4
5
6
7
8

Status Bit

0

1

L
L
L
L
L (FM operation)
PO analog
neg.
O.25mA

H
H
H
H
H (AM operation)'
Test"
pos.
1 mA (AM or FM operation)

'When the band selection output FM IS switched from "H" to "L" via bit 5 (FM). operation IS switched from AM to FM
PDAM Is in tristate and vice versa
ooln test operation PDFMA and PDAMA outputs are switched as FVN and FRN outputs respectively

8·18

SDA 2121

12C Transfer Protocol

SDA
IC-

SDA
5t.r~

~t.rt

IC

...

A

0
0

0
0

0"-

0'1-

>c<

ACK

Sus·

SUB·
A
0
0

}

AC'

.~

aWl
aW2
aW3

FM
TeSllPD analog

>C",",5; ...,

Statu.

1)0 polarity

PO current
>C<

N dlVloer

>C,

,"58

.5a
RdlYlder

ACK

>c<
StOD

L58

At<
Stoo
0097-6

·Chip select is achieved via bit 7 for the IC address. The contents are compared with the value set on Pin AO. If the values
are identical, the respective chip is selected.

8-19

•

SDA 2121

Programming Example
SDA

SDA

S1a"

.c·
A

D
D

IUB·
A

D
D

AC<
M58

aWl
PRT

}

aW2

•0

0'0

aWl
FM

00
00

StatuI

00
0'

THtlPD analog
AC_

00

PDpol.",y
PDcu".nt

AC.

M58

L5B

Rd.vide,
_2000-='\11

LIB

Input
Raeter
IF
Signal Frequency
Width
[MHz]
[MHz]
[KHz]

.1&O.FM

Divider

100

10.7

25

2000

N DIvider

AM IN

1

0.455

1

1000

N DIvider

OSCIN

4

FMIN
AM.&OOO_

Divider
RatIo

25/1

160/4000 R DIvider
0007-7

8-20

i

~

ill
::I

...'"

!

0>

+

···
:..
·
·

'"cD

:

MdlnAdd'e"-

:

:

CIC~'ftH):

I

•

.:.

I

,:
,
,
:,

I
I
I

,
,

"

I
I

I
•

II

I'

............ ,

I

I'

I

.
,

I
I

.
I
I
I

:, ,,,
-_ .. --_ .. -_. :,,
,,

~OA ~wtaenSCL .. :Hlgh

,

I

•

r

,

,

.,,
,

I

·,

Se~' R••dlWfI1to

.

r

SDA

: OperatIon)

,

,

OutPUlot

,,
,
,,
,

ht

I

I

•

,

I

"
I

I

D"t.WO:~ ..... J

Oytput of a...t 0 ... WOrd

·'---------------1 (------At.

Ht!'ddllll!'u

.

.,

:"'knowINg.:
... ...........

:

Ad, nowledg@- from 51i1vt'
(Prompt tor Addltlon._ Oulput)

t-}

SI.v.

............

,, ,
,"

I

,,

I

,

"'

I

I

I

I
I

,
I

I

'_

::

.:
, ,

' ........ ,

I

I
I
I
•
,

, ,:

I

•

I

______rLn.-l : IReset" lIe Bus Ready 'or
STOP

I
,
I
I
I

I

I

nuwl~gl!' hom Sldve
:
: lOW,., Output hurn Md"'t.1 (lJuh,m"ttun u' R(t\poIIW
I

sel

~
~

•

:
:, ,,
, ,
,: :

.: .,,,

'- ... ........

• !tJARJCONDITtON "",•

,

,.1.

't..;'___.....

:,
II

ia

L.lth (ndb'.

:

,

I
I

sel

-:..

•

I

0.1.-

:

.
.

I

SDA

Sub Add'Il"\\-

:

...

--- .............. ,

-STOP COHOtTION

jSOAl IwhenSCl~ High

:
t,I"'"

,

.

.......... ~

: Acknowledge
: fromSlilve

:

!

Pulse Sequence Alter POWER ON to Release a Possible lock of the SDA Input

L-

:
: START

0097-8

en

~

~
....

....NN

....

SDA 2121

12C Bus TIming, PRT

SOA

SCL

-t~o

Parameter

Symbol

-- t'l:

OAT

Umlta

0'"

Units

Xf-f--

Min Max
PAT

Clock Frequency

fSCL

0

Hold Time Data to SClLOW

tHO; OAT

0

Inactive Time Prior to Next Transfer tBUF

4.7

Hold Time During Start Condition
(First CLOCK Pulse is Generated
after This Time Period)

tHO;STA

4.0

lOW Clock Phase

tLOW

4.7

HIGH Clock Phase

tHIGH

4.0

Set-Up TIme for DATA

tsU;OAT 250

Rise Time for SDA and SCl Signal

tR

-

Fall TIme for SOA and SCl Signal

tF

Set-Up TIme for SCl Clock during
Stop Condition

tsU;STO

PRT Delay TIme Relative to Stop
Condition

tOPRT

100

KHz
/l-s

-

/l-S
/l-s
/l-s

-

/l-s

-

ns

1

/l-s

-

300

ns

4.7

-

/los

-

500

/los

All values are referenced to specified input levels VIH and VIL.

8-22

-

tSU\·o: '

--+

.;:t:~.

-

0097-8

SDA 2121

Pulse Diagram: Phase Detector/Lock Detector
, ,

jJ-

OSC'N

1

1

Jl------Jn,-------,n,-------,nl---FM,AM

i

i

1

I,

--n.r-

fv
(FM/AM:N)

.",""' ~
TrIState

N Channel
PO

.'"'"~'~
TrIState

N Channel

~

J

J

~

u

u

(Polaroty pos )
Status Bot 1 H

=

(Polaroty neg)
Status Bot 1 L

=

LD

0097-10

Ordering Information
Type

Order No.

SDA2121

Q67100-H8621

8-23

SIEMENS

TCA440
AM Receiver Circuit
AM receiver circuit for LW, MW, and SW in battery and line operated radio receivers. It
includes an RF prestage with AGC, a balanced mixer, separate oscillator, and an IF amplifier
with AGC. Because of its internal stabilization, all characteristics are largely independent of the
supply voltage. For use in high quality radio sets the TDA 4001 should be preferred to the
TCA440.

Features

• Separately controlled prestage
• Multiplicative push-pull mixer with separate oscillator
• High large signal capability from 4.5 V supply voltage on
.100 dB feedback control range in 5 stages
• Direct connection for tuning meter
• Few external components

Maximum ratings
Supply voltage
Storage temperature range
Junction temperature

T819

Thermal resistance (system-air)

V

~

15
-40 to 125
150

R1hSA

120

K/W

Vs

°C
°C

Operating range
Supply voltage
Ambient temperature

Vs
TA

8-24

14.5 to 15
-15 to 80

1

~c

TCA440

Characteristics
Vs = 9 V; TA = 25 °C: f,RF = 600 kHz; 'mad = 1 kHz
Total current consumption
LlVAF = 6 dB
RF level deviation for
LlVAF =10dB
m=80%

Is
LlG RF
LlG RF

10.5
65
80

mA
dB
dB

AF output voltage for V,RF
(symm. measured at 1-2)
for m =80%

V,RF=20 J.LV
V,RF= 1 mV
V,RF=500 mV

VAFrms
VAFrms
VAFrms

140
260
350

mV
mV
mV'

for m=30%

V,RF = 20 J.LV
V,RF= 1 mV
V,RF=500 mV

VAFrms
VAFrms
VAFrms

50
100
130

mV
mV
mV

Input sensitivity
(measured at 60

0, t, RF = 1 MHz, m = 30% 10%, RG = 540 0)

at signal-to-nolse ratio
(in acc. with DIN 45405)

~~N

= 6 dB

V,RF

S~N

=26dB

V,RF

S+N =58dB
N

J.LV

7

;

J.LV

1

I mV

V,RF

RF stage
Input frequency range
Output frequency tlF =tosc -tIRF
Control range
Input voltage (for 600 kHz, m = 80%)
for overdrive (THD AF = 10%),
symmetrically measured at pins 1 and 2
(mean carrier .value)
IF suppression between 1-2 and 15
RF input Impedance
a) unsymmetrical coupling
at GRFmax
at GRFmln
b) symmetrical coupling
at GRFmax
at GRFm,n
Mixer output Impedance
(pins 15 or 16)

t,RF
tlF
LI Gv

VIRFpp
V,RFrms
alF

ZI
ZI
Z,
Z,
Zq

o to 50
460
38

MHz
kHz
dB

2.6
0.5
'20

V
V
dB

I 2/5

kWpF
kO/pF

I1 2.2/1.5
4.5
4.5/1.5
250/4.5

I

kO/pF
kQ/pF
kO/pF

8-25

TCA440

IF stage
Input frequency range

oto 2

MHz

Control range at 460 kHz

62

dB

200

mV

mV
mV
mV
mV

Input voltage (mean carrier value)
at Gmln for overdrive
(THDAF -10%), measured at pin 12
(60 0 to ground, fliF - 460 kHz, m - SO%; f mod -1 kHz)
AF output voltage for VI IF at 60 Q (pin 12)
ViIF-30""V, m-SO%;fmod -1 kHz
ViIF-3mV,
m-SO%;fmod -1 kHz
Vi IF -3 mV,
m -30%; fmod -1 kHz
ViIF-200 ""V; m -30%, flF -455 kHz; fqAF -1 kHz

V7 AFrms
V7 AFrms
V7 AFrms '
V7AFrms

50
200
70
35 to 60

IF input impedance (unsymm. coupling)

ZI

3/3

kQ/pF

IF output impedance

Zq7

200/S

kO/pF

Tuning meter
Recommended instruments: 500 IlA (RI = 800 kC)
or 300 ""A (R I .... 1.5 kC)
The Ie offers a tuning meter voltage of 600 mVEMF max. with a source impedance of
approx. 400 C. ,

8-26

TCA440

Measurement circuit for output voltage

BV

47nF

son

455kHz

47nF

16

10

14

9

TCA 440

5

39kn

6

8

3x
100nF
VqAF

AA 11B

------Coil Assembly Vogt 041-2519

400
Turns

47pF

nkO

T

100F

8-27

TCA440

Circuit diagram
~

1

~
~

~

.;:

...

,

--t-J"

l=.?

'* *~

I
c

aT

.i..

~

-~

240
540
1.2kQ
2.2kQ
4,8kQ

j'~

SF 4550

CD
'i"

AA 11B

[)I

,

OVqAF

T,

5IJF

12kQ

~.
~

39kQ

I'
iii

go

V;RFO~+---------------~

Z, =60Q

2x100nF

T
1,BkQ
B,2kQ
25IJF
L,-L2 M 25 pot core
L3-L11 with coil assembly Vogt 041-2519

T

[

L, 2+6 turns 6x12xO.04 Cu LS
L2 n turns 0.15 Cu L
L3 90 turns 12xO.04 Cu LS

L4 35 turns 12xO.04 Cu LS
L5 15 turns 0.10 Cu L
L6 70 turns 12xO.04 Cu
"L7 35 turns 12xO.04 Cu
La 60 turns 12xO.04 Cu
LlO 22 turns 12 x 0.04 Cu
L" 68 turns 0.06 CuL

LS
LS
LS
LS

Switch

A

18

C

off

Ion

off

separate prestage control

®

on

I off

on

prestage control voltage
derived from IF control
voltage

®

',-1 MHz; m-30%

~

5

AA 118

Kl

r----:L

-r--

:L -,---

o+Vs

'0
'0

!o

L7

::I

E
:I

2,2kQ
Cf':i

r~fTuning Me~ter ~'''PF
..,

)/

i

/

.. !»

'0

CD

.

;-- -- --H

0'

rit--1-_1JM"""
7

I

SF 455 D

~

AA.118
OVAF

39kQ

3,3!fL

I

Q=:F
I

~

l>
".

~

12kQ

+

V,RF o

2x100nF

T
8,2kQ

T

T 251lF

L 1-L 2 with coif assembly Vogt 021-2375.1
L3 -L l1 with coif assembly Vogt 041-2519

105 turns 12xO.04 Cu LS
7 turns
0.10 Cu L
80 turns 12xO.04 Cu LS
35 turns 12 xO.04 Cu LS
15 turns
0.10 Cu L
20 turns 12xO.04 Cu LS
50 turns 12 xO.04 Cu LS
L10 22 turns 12xO.04 Cu LS
Lll 400 turns
0.06 Cu LS
Ll

L2
L3
L4
L5
La
Lg

~
3>

~
.....

8

TCA440

Prestage control TeA 440

mV
CD
Cl

ill

600

:g+V3

500

g

~r
Cl

300

I!!

200

~

Q.

_-<.

..........

I----II--<~

100nF

9V

: QB= 108

400

I

Vi

100

=600 kHz

Unmod

V15 =460 kHz Unmad.

0

0

10

20

dB

40

30
-

Attenuation ,d6v

The input ist not power matched and can be driven with a higher resistance. The selected Vi
ensures a constant V15 (50 mV peak-to-peak).

IF control

mV
+\)

800

t 700
I

600

~ 500

ill

g

400

~o

300

>'-......~--.....c~F

Y:: 200

BnF

o

100
20

30

40

50
-

The selected V1F (469 kHz; m = 80%; fmod

8-32

=

60

dB

Attenuation ,d6v

1 kHz) ensures a constant VAF (200 mV, rms).

TCA440

AF output voltage versus RF input voltage

mV
150 '-r-r-TTTlTrr--r-,,,,,rT'",,rrnr--rTTrTTTTr--r,TTTTTTr---r-.--rrrrm--r-oI-r,Tr
IIIJrml

VAF rms

t

.1 II.

,",od=1kHz
f,RF =1MHz

=

f--+-t+H-tttt- m 0.3

Vs =15V

ffi-ttt---+-t--H-H+tt---+-t-Httttt---j'-l-+t1H-Ht-t--t-'t-t1~

1.J."H+H-H--+-+"'I"'T

~-

IJ.lr-+-+-tllrro

...-,...-4.5

Measured Symmetrically at 1 and 2

O~~~~.~~=-~~~~I~~II~I~lli~IIII~I~I~II~II=IIIII~I~~
10. 3
10. 2
10.1
10°
101
102
103 mV
-V'RF

Example for medium wave applications
AF output voltage versus output frequency
Total harmonic distortion versus modulation
frequency
mVrms
0/0
150
15

,.'

.i\

THO

\

"\

100

10

t

'\ (;HO'~

75

Passband characteristic versus Input
frequency, measured from input to
output of the circuit

dB

(:+
i
-10

I---I'f--

'-without Detuning
-3kHz Detuning

50

25

I
I

.....

"

"-

o

0.5

1\
=fmod

, ,rr

fAF

THO

-20 t----+
5

o

10kHz

-~~_L-_~_~_~_~

1432

14~

1448

1456

1464 1472 kHz

_f

8-33

TCA440

Total harmonic distortion versus detuning (parameter: modulation frequency)
Vs - 9 V '
fose = 1.455 MHz ± tJ.f
m" 30%
flRF -1 MHz
flF - 455 kHz
V,RF - 20 mV rms

%
14

/ r'\.,

T:

/

8

V

'I 1\
j, \
,

~HZ

6
4

~z
2

~~
1 ~

"

/
II

___ 1\

1kHz

'~

~~ ~

o
-8

-10

' -6

-4

-2

o

VI

~

'--"'" 2kHz

-

~

2

1kHz

4

6810kHz

____ Detuning Llf

Total harmonic distortion versus detunlng (parameter: RF input voltage)
%

8

~-----

Figure 2~ V,RF =2~Vrms
LFigure 20: V,RF =20mVrms
Figure 200: V,RF =200mVrms

m =80%

/, ~

200
5

'"

VL

'\ L

4 2
3

~....:s--.....,

-"""V

~

./

2:1

Vj

/ \ /

I/.~
I"""'""

/

..Jo.

\

J

\~

1

2
~

~

..........

........

~ .,L

,~

~

o
-10

-8

-6

-4

-2

o

2

4

_

8·34

6
Detuning Llf

8

10kHz

TCA440

AF output voltage and noise
figure versus RF input voltage
switching position 60Q
~

/

~1SQ

,/~

o

10'

-ViRF at 60Q
8-35

TCA440

Application example for MW
Prestage control is derived from IF control

.----,.---..-~--.._-----------o+4.S .... 1SV

2.2kQ
100nF

T
47pF

r-~~i

330pF

4<·"'1

Lt-f--_L ","',.

I
I
I
I

7

SF 4SS ,

AA 118

~C=370pFi

3.3nF

I

I

39kQ

I

Ii\RFO----------~

100nF

T

2x100 nF

T

12kQ

SIIF

T

1.8kQ
8.2kQ

L1 105 turns 12xO.04 Cu LS
L2
7 turns
0.10 Cu L
L3 80turns-12xO.04CuLS
L4 35 turns 12xO.04 Cu LS
Ls 15 turns
0.10 Cu L
L8 20 turns 12xO.04 Cu LS
Lg 50 turns 12xO.04 Cu LS
L10 22 turns 12xO.04 Cu LS
L11 400 turns
0.04 Cu L

8-36

370llA I'

1,SkQ

L1-L2 WHh Call Assembly Vogt 0 21-2375.1
L3-L11 With Call Assembly Vogt 0 41-2519

TCA440

Test figures for application example for MW
Total harmonic distortion and AF output voltage
versus RF input voltage
measured symmetrically at pins 1 and 2
fl = 1 MHz, fmod = 1 kHz, flF - 455 kHz, Vs - 9 V

8-37

TCA440

Application example for MW using BB 113 varicap diodes
r - - - " f - - - " f -__- - " f - - - - - - - - - - - - < > + Vs (4.5-15 V)

100nF

T
330pF

3.3nF

I
100nF
10nF

+VO

V,

I

L, - L2 With Coil Assembly Vogt 021-2375.1

L3 -L" With Coil Assembly Vogt 041-2519

lII"n= a.5V - " = aOOkHz
"tun= 30 V-f, = 1620kHz

8·38'

T
L, 105 turns
L2
7 turns
L3 80 turns
~ 35 turns
Ls 15 turns
La 20 turns
La 50 turns
LlO 22 turns
L'1 400 turns

12kQ

5IJF

12 xO.04 Cu
0.10 Cu
12xO.04 Cu
12xO.04 Cu
0.10 Cu
12xO.04 Cu
12xO.04 Cu
12xO.04 Cu
0.06 Cu

LS
LS
LS
LS
LS
LS
LS
LS
L

TCA440

Conversion ~ransconductance versus oscillator voltage
mS

35

I

/'

20

VV

V

1--

/

15

S=~=2

y
V'_2
V'_2
V, = Canst. -1 mV at Pin 1 r-i--rf, =1MHz;m=0%
fosc= 1.455MHz

10

5

flF

o
10mVrms

= 455kHz

Vs = +9V
V3 = OmV
100 mVrms

1Vrms

_

Vase at 5 (4 With Capacitance to Ground)

8·39

TCA440

Measured values for application example for,MW using diode BB 113
AF output voltage and total harmonic distortion versus RF Input voltage
fj -1 MHz; fmod -1 kHz; flF - 455 kHz
Vs - 9 V; VIRF symmetrically measured at pins 1 and 2

mVrms

°/0
15

t

THO

10

300 ~--'--rTTTTTT.--,,---rr~

Ii

V.

t~O

~,

!

200
I

,

I

I

i'
i:
iii:
I

I
I

.... fo-, ~ (m= 80 %)

I

ItillI

,

I

II j j'

I

J
~LL
i
l
1
i
i
,
r-r
~II
Iii
+:

100W14~ru"-- -I
: ! II

50~-o

I-lH

..;1'

1501-~
l,lf!l,
I
I III1 ~~ i~~
:Ii
5

/'tc::;
.... w
l 'I'll

I

I

jj

;11 1

_.

I

II"'!

t"f

ff

~

I i I!~ll.Lll_~.ulL_
(""r-..

a

L--L...J...L.U.

10-3

.-.- .... -

'

1

I'

0

r--i"-.!. ....... -

j

THO(m=30 %)

__ LllJTIIT

l

10 1

10°

II

i:+

'i'

;::1,

: I':
It' ... : I, '

~F (m- 30 YO)THO(m=BOO/~~bI~ ~,'

10-1

10-2

I

II
III
!

iI I

1

I

i...I ill'
__

10 2,
-V,RF

103 mV

Tuning meter voltage versus IF control voltage
(parameter: impedance of tuning meter)

mV
~O.-,--.--.-,--,-,~.-~

Example for moving coil instruments

100

f--+--H+~-i---+--j-+--1

Rj

Full-service deflection

1.5 kO
1.5 kO
2 kO
350

100 \loA
170 !-LA
200 !-LA
500 !-LA

a

200
8-40

400

600

800mV

SIEMENS

TOA 1037
AF Power Amplifier Ie
with Thermal Shutdown
AF power amplifier designed for a wide range of supply voltages to enable versatile
application in entertainment electronics. The amplifier operates in the push-pull B mode
and is available in the SIP 9 package. The integrated shutdown protects the Ie from
overheating.

Features

•
•
•
•

Wide supply voltage range: 4 V to 28 V
High output power up to 8 W
Large output current up to 2.5 A
Simple mounting

Maximum ratings
RL ~ 16 Q
RL ~ 8 Q
RL ~ 4 Q
Output peak cur~ent (not repetitive)
Output current (repetitive)
Junction temperature 1)
Storage temperature range
Supply voltage

Vs
Vs
Vs

lq
lq
~
Tstg

Thermal resistance
junction-case
system-air

V
V
V
A
A

30
24
20
3.5
2.5
150
-40 to 125

°C
°C

RthJC
R thSA

112
70

I K/W
K/W

Vs

14 to 28
-25 to 85

1

Operating range
Supply voltage
Ambient temperature

TA

') May not be exceeded even as instantaneous value.

8-41

~C

TDA1037

Characteristics
with reference to test circuit
1. Vs = 12 V; RL = 4 0; C1 = 1000 f.LF; fi = 1 kHz; TA = 25°C

Quiescent output voltage
Quiescent drain current
Input DC current
Output power THD= 1%
THD=10%

LB
Pq
Pq

Voltage gain (closed loop)
Voltage gain (open loop)

Gv
Gvo

Tolal harmonic distortion (Pq = 0.05 to 2.5 W)
Noise voltage referred to input
(fi = 3 Hz to 20 kHz)
Disturbance voltage in acc. with
DIN 45405 referred to input
Hum suppression (fhum = 100 Hz)
Frequency range (-3 dB)
C4 = 560 pF
C4 = 1000 pF

THD

Input resistance

Vq2

min

typ

max

5.4

6.0
12
0.4
3.5
4.5

6,6
20
4

40
80

43

13+14
2.5
3.5
37

0.2
3.8

Vn

40
40

dB
dB
%

10

~Vs

~V

dB
20,000
10,000

Hz
Hz

MO

5

RiB

~A

W
W

2.5
48

Vd
ahum

V
mA

2. Vs =24 V; RL =160; C1 =220 f.LF; fl =1 kHz; TA =25°C
Quiescent output voltage
Quiescent drain current
Input DC current
Output power THD= 1%
THD=10%

La
Pq
Pq

Voltage gain (closed loop)
Voltage gain (open loop)

Gv
Gvo

Total harmonic distortion (Pq = 0.05 to 3 W)
Noise voltage with reference to input
fj =3 Hz to 20 kHz
Disturbance voltage in acc. with
DIN 45405 referred to input
Hum suppression (fhum =100 Hz)

THD

Vq2

8-42

4.5
37

Vn

12
18
0.8
3.5
5.0

13
30
8

40
80

43

dB
dB

0.2
5

0.5
15

%

40
40
RiB

~A

J.LVs
J.LV
dB

20,000
10,000
5

V
mA
W
W

3.8
40

Vd
ahum

Frequency range (-3 dB)
C4 = 560 pF
C4 = 1000 pF
Input resistance

11

13+14

Hz
Hz

MO

TDA1037

Circuit diagram

340Q
~~~--~--~--~-+-------r---+---o3

6~--------~~-r--r--c=r--~--~--~-+~~-------+---o2

7~--------~---r--'

R,
8

1,7 k{!

T1

5
04

R7

Ra

R,a

9

9

Measurement circuit
~~--------------O+12 V/+ 21tV

S Closed for Noise ,Measurement

8-43

TDA1037

Application circuit

T l00IJF
30V
100nF

V;

8
o--!t--- 10V

mA

20 Hz to 50 KHz
5
34

p.V

36

3S

dB

0.25

0.5

V

The Characteristics listed above are ensured over the operating range of the TDA 2025. Typical Characteris·
tics specify mean values expected over the production spread. Typical characteristics apply to Ta = 25°C at
mean supply voltage unless otherwise stated.

Test Circuit

Typical Application
.IIV

J,III

IIIIf

"'--....-~

III - - r - - I - - - i
ID

....-.
S·52

TDA 2025

Performance Characteristics
= 1 KHz, Load Resistance = 4n

Test Conditions: Frequency

y.(V)

I. (A)

Py(W)

Pq(W)

n(%)

THO(%)

8.06
8.02
8.02
8.01
8.00

0.453
0.801
0.835
0.940
0.997

2.64
3.24
3.23
3.19
3.20

3.65
6.42
6.69
7.53
7.98

28
50
52
58
60

0.10
0.59
0.99
5.01
10.02

14.46
14.44
14.43
14.42
14.40

1.448
1.630
1.677
1.830
1.942

10.43
10.12
10.10
9.81
9.66

20.93
23.53
24.20
26.38
27.98

50
57
58
63
65

0.12
0.59
0.99
5.00
10.01

22.15
22.09
22.09
22.07
22.05

1.742
2.316
2.368
2.562
2.725

23.60
24.39
24.31
24.10
24.02

38.59
51.17
52.31
56.54
60.10

39
52
54
57
60

0.11
0.59
0.99
4.99
10.01

Note:
Vs = 24V Max. with RL = 4ft

Test Conditions: Frequency

=

1 KHz, Load Resistance

= 8n

y.(V)

I. (A)

Py(W)

Pq(W)

n(%)

THO(%)

28.06
28.03
28.02
28.00
27.99

1.512
1.735
1.880
2.016
2.135

19.93
18.66
17.33
16.21
15.33

42.43
42.64
52.68
56.44
59.76

53
62
67
71
74

0.05
0.12
0.99
5.00
10.01

32.15
32.12
32.09
32.07
32.06

1.613
1.888
2.140
2.281
2.423

26.87
25.62
23.08
21.75
20.56

51.86
60.63
68.66
73.15
77.67

48
58
66
70
74

0.04
0.10
0.99
5.00
10.00

36.15
36.12
36.09
36.07
36.06

1.787
2.033
2.357
2.510
2.667

34.57
33.47
29.90
28.20
26.70

64.62
73.45
85.06
90.53
96.18

46
54
65
69
72

0.05
0.10
0.99
4.99
9.99

Note:
Vs = 45V Max. with RL = Stl.

8-53

TDA 2025

w

Power Dissipation vs
Output Power

r
IS

J

~

Y..

I

If' :~~I
I"L.III I

,.

J

,
o

&5

t

~

/

JO

I

ZO

.0

JO

o

SOW

j

s

ZO

11

JO

sow

«I

/'

/
,
,

5

-(
10

/~

«I

V~

L

10

Is

:=./
f If',.111

"-

Quiescent Current vs
Power Supply Voltage

Efficiency vs
Output Power

10

ZO

JO

fIN
0096-6

Supply Current vs
Output Power

THD vs Output Power

Output Power vs
Power Supply Voltage

w

A

II

It

,I

t·

,
,

t

2.5

2.0
f _ 1kHz
Ws-nllrl
RL

-tr'," •

1.S

.IQ

1.0

0.' I /

~

o

10

JO

20

«I

o

SOW

...

I

_ ItIII
UII

f

/

" ... 1J'
1·
'/
j

~

I

,klll

II . , "

I ......

JO

"

/. 'If • Iklll ~

10

11

20

30

o

sow

&0

.,~"
11

L~:'':

ZO

JO

-

_
0096-7

..

Hum Suppression vs
Frequency

THD vs Frequency

t• s

dl
11M

t

- ~r :=.1
..... ID

0.5

"'

~~

::::;.' •• '5WJ.
,,, I la-lfl

"-

L

'.·-t

!Is ••IV
",.ID
iii • 101d1
II.

.o.sv,

'-

~

0,'
1

-'-

20

111

I"

100Ma
0096-8

8·54

TDA 2025

Ordering Information
Type

Ordering Code

TOA2025

Q67000·A8186

8·55

SIEMENS

TDA4010
AM Receiver for
, AM Stereo
Compare to TDA 4001 the TDA 4010 is an extended AM-receiver. This type is suitable for applications in car radios.
The IF-output

V\QF

is at pin 15.

Features
•
•
•
•
•
•

Internal demodulation
Search tuning stop signal
low total harmonic distortion
Minimal IF leakage at the AF output
2-stage ingrated low pass
'
Standard IF-output

Function description
The monolithic integrated bipolar receiver has been designed to convert, amplify and demodulate
AM - signals. In addition, the component provides a search tuning pulse.
The search tuning stop pulses are processed from the input signal.
The standard AM-IF signal is available at the output of the IR-receiver.

Circuit description
The impedance converter forwards the input signal ViRFto the symmetrical double balanced mixer.
Subsequently the signal is converted to IF with the amplitude-controlled oscillator. An external
filter forwards the IF signal to the controlled IF ampljfier. The amplifier IF signal and the carrier
signal will be converted to AF in the subsequent synchronous demodulator. The 2-stage low pass
filter forwards the available AF to the AF output.
Via an additional limiter amplifier (LA), the AF uses the carrier signal to control the coincidence
demodulator (CD). The output signal of the coincidence demodulator provides the stop pulse during
exact tuning and sufficient field strength.

8-56

TDA4010

Maximum Ratings
Maximum ratings cannot be exceeded without causing irreversible damage
to the integrated ciruit.
Pos.

1
2
3
4

Maximum rating for
Tamb=25°C
Operating voltage
Current consumption
Junction temperature
Storage temperature

Thennal resistance
5
chip ambient
chip package
6

Symbol

min

max

dim

-40

15.6
33.0
150
+125

V
mA
°C
°C

78

KIW

Vs
Is

TJ
Ts

RthSU

remarks

RthSG

Functional Range
Within the functional range, the integrated circuit operates as described; deviations from the
characteristic data are possible.
Pos.

Maximum rating for
Tamb = 25°C

1
2

Operating voltage
Temperature range

Symbol

min

max

dim

VBatt

7
-25

15

V

+85

°C

t:.a

remarks

8·57

TDA4010

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production- spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and the listed supply voltage.
Pos. Parameter

Symbol Test conditions

Supply voltage
Ambient temperature

Test
circuit

5
6

7
B

9
10
11
12

8-58

Typ

Max

Dim

Vs= 12V
Tv=25°C

1 Current consumption Is
2 Reference voltage
VSTAB
3 IF-output voltage
VqNF
4

Min

m=O.B
m=0.3
Total harmonic
k
m=0.3
IF-output voltage
VqNF 20 • Ig (VqNF/30mV:
VqNF/1mV
Input sensitivity
VIHF
VqNF for VIHF =
1mV-3dB
Signal-to-noise
S+N m=0.3
ratio
N
VIHF = 101'Veil
Signal-to-noise
S+N m=0.3VIHF=1mV
Oscillator voltage
VOse
Counteroutputvoltage Vqz
Control range
a
(AVq IF=6dB)
3dB limit frequency
of the integrated TP

'g

15

mA
V
mVell

4.B
BOO
m=O.B

2%
%
+3

dB

30
6

J.Nell

46
100
60

dB
mVss
mVss
dB

5

kHz

dB

100

TDA4010

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not stated
otherwise, typical characteristics will apply at tamb =25°C and the listed supply voltage.
Pos. Parameter

Symbol Test conditions

Supply voltage
Ambient temperature
13
14
15
16
17
18
19
20
~1

22
23
24

IR-suppression
AIF
Conversion gain
Vm
IF-output Pin 15
VqlF
AFC-Offset current IAFc
without signal
AFC-Offset current ' t:l./AFc
over control range
AFC-current
IAFc
SLS-output voltage
V12
SLS-output voltage
V12
SLS-output voltage
V12
SLS-output voltage
V12
Input impedance
ZIHF
Input impedance
ZiHF

Test
circuit

Min

Typ

Max

Dim

Vs= 12V
Tv = 25°C
40
30
10
±10

fIHF= 1MHz±3kHz
fZF = 455kHz
FZF=OV
fZF>455kHz + 3kHz
fZF >455kHz - 3kHz
Pin 3,4
Pin 18

dB
dB
mett
p.A

11
11
11

10/1.5
3.311.5

±10

p.A

±80
0.4

p.A
V
V
C
V
kOllpF
kOllpF

-,
8-59

;

til

I

a.

~.

iii
3

....
~

g
Q

TDA4010

Pin configuration

Pin·Nr.

1
2
3
4
5

6
7
8
9
10
11
12
13
14
15
16
17
18

pin function

Ground
Mixer output, IF-circuit
RF·input
RF-input
VStap

Oscillator
Supply voltage
counter output
FM·Demodulator circuit IF·circuit
FM·Demodulator circuit IF·circuit
AFC·output
Search tuning stop output
AF-output
IF-time constant
min. IF-output
IF·AP follow up device
IF-AP follow up device
IF-input

18
2

17

3

16

4

15

5

14

6

13

7

12

8

11

9

10

8-61

!~

~

::::t.

~

Q.

g::;:

68 11
2.2n

15k

-I

g

g
o

SIEMENS

TDA 4210-3
FM IF Ie with Search Tuning Stop Pulse,
Field Strength Indicator,
Mute Setting and Multipath Detector
The TDA 4210-3 has been designed as FM IF component with a special demodulator for
application in car radios. The sensitivity level of the input amplifier can be adjusted for
applications with search tuning mode. In addition, a search tuning stop pulse is generated.
Moreover, the included multipath identification circuit activates an interference suppression
circuit in case of multipath interference. The TDA 4210-3 is especially suitable for application in car radios and home receivers which require a search tuning stop pulse and
include an interference suppression circuit.

Features
• Multipath identification circuit
• 7-stage limiter amplifier
• Product demodulator
• AFCoutput
• Field strength dependent volume control
• Generation of search tuning stop pulse
• Adjustable limiter threshold
• Adjustable muting depth

Circuit description
The integrated circuit' includes a 7-stage limiter amplifier with demodulator and noncontrolled AF output. The limiter threshold can be raised by a~prox. 44 dB by means of
external circuitry. Within this range the AF output signal can be continuously attenuated
by max. 39 dB to eliminate the usually occurring noise products.
To suppress variable interference products, e.g. multipath interference, the TDA 4210-3
includes an identification circuit with an externally adjustable time constant.
Also included are a field strength output, an AFC output, as well as an open collector output.
The latter will be activated at the zero crossing of the detector S-curve.

8-63

TDA4210-3

Maximum ratings
Ground
MUTE input
Muting depth

V,
V2
V3

0
Vs

Vii

V
V
V

AFoutput
Search tuning stop signal output
AFCoutput

V4

Is

Vs
5
Vs

V
mA
V

5
Vs
Vs

mA
V
V

5
5
Vs
18
Va
Va
Va

mA
mA
V
V
V
V
V

Va
125
-40 to 125

V
°C
°C

7.5 to 15
0.4 to 15
0.4 to 15
0.02 to 150
-25 to 85

V
MHz
MHz
kHz
°C

V6

Reference voltage output
Phase shift
Phase shift

17

Field strength
Identification output
Demodulator time constant
Supply voltage
Identification input
Limiter threshold
Operating point feedback

1'0
I"

IF input
Junction temperature
Storage temperature range

Va
V9

V'2
Vs
V'4
V,s
V, 6. 17
V,a

1j
Tstg

Operating range
Supply voltage
IF section demodulator
Overall frequency
AF (VqAF - 1 dB)
Ambient temperature

8-64

Vs
flF
f
fAF

TA

TDA4210-3

Characteristics
Vs = 8.5 V; Vi IF rms = 10 mV; filF = 10.7 MHz; Llf =
adjustment when 17 = 0; test circuit 1

± 75 kHz; fmod == 1 kHz; OB

Test conditions

min

"" 20; TA

= 25 °C;

typ

max

27

33

rnA

3.8
0

0.1

V
V

Current consumption

113

Field strength output
voltage

V 10

"IIFrms - 50 mV
"IIFrms -0 V,

Vq4rmS
THO

380

520

mV

IAFc-O

0.7

1.5

%

Input voltage for
limiter threshold

"IIFrms

Vq4 -3

15

30

I1 V

AM suppression

BAM

tri -30%

AF output voltage
Total harmonic distortion
during FM IF mode

1110

3.0
270

dB

Signal-to-nolse ratio

BSIN

Current deviation of
AFC output

A.h

f= fliF ±50 kHz

AFC offset

A.fofl

VI = 20 I1V .. 10 mV

Search tuning stop
window

AfsT

R6- 7 -22 kO

Search tuning stop
threshold FM

"1ST

V6 = VS f2

Search tuning stop
threshold AM

"1ST

V6

Stabilized voltage

V7

Adjustable range
of limiter threshold
via pin 15
AF mute

' "IIF

BAF
aAF

dB

60

dB

70
±110
±15

3.6

V2
V2

-0; Ra-1 - 00
=0; R3- 1 -0

4.1

70

I1 V

500

I1 V

4.6

V
dB

44

VREF

3
31

kHz
kHz

±18

= VSf2

V15 ... 0; V15 -

I1A

7
39

11
47

dB
dB

0.5

0.75

V

AF mute switch-off voltage

V2

MP sensitivity for full
drive at pin 1

"I14rms

f=20 kHz

Charge current pin 12

112

pin 14 to ground

3

rnA

Discharge current pin 12

112

pin 14 open,

10

I1A

mV

5

V'2

<1 V

Additional data with respect to application
(data does not apply to series measurement)
DC voltage AF output

Vq5

2.8

Internal DC current of
emitter follower output

14

0.75

Input resistance for
demodulator circuit

R9-10

Search tuning stop "low"

Va

Search tuning stop "high"

Va

27

3.8

4.8

rnA
kO

35
1.3

7

V

V
V
8-65

TDA4210-3

Pin description
Pin

1
2

3

4
5

6

7
8/9
10
11

12
13
14

15
16/17

18

8-66

Function

Ground: capacitors for operating point feedback, Vs , and VREF decoupling are
to be connected directly to pin 1
Mute input for (usually derived from field strength output voltage) dc voltage
which attenuates, the AF output voltage by the set muting depth (pin 4).
Max. attenuation when ~ = 0 V, no attenuation when V2 ~O. 75 V
Muting depth adjustment: by connecting a resistor to ground the requested
muting depth can be set. Maximal, attenu~tion of AF output voltage with R - 0
(approx. 39 dB), minimal attenuation with R ... 00 (approx. 7 dB)
AF output for demodulated FM-IF
Search tuning stop (Sn output is connected when the input field strength
exceeds the search tuning stop pulse threshold and the input frequency
lies within the search tuning stop pulse window. ,
,
AFC output: push-pull current output, referenced via a resistor connected to
a fixed 'voltage source (e.g. VREF). The voltage generated at the resistor is in
proportion to the deviation from the nominal input frequency and can be
applied for retuning purposes.
Reference voltage: should be RF decoupled to pin 1. The AFC resistor and
the potentiometer for the limiter threshold are referenced to VREF •
Demodulator tank circuit: driven via two integrated capacitors (approx.
40 pF ± 25%). The circuit voltage should be approx. 200 mV (peak-to-peak)
Field strength output: supplies a dc voltage proportional to the input level,
which q!Jickly adjusts to changes in the input voltage
'
Identification outp~t: designed asan open NPN collector output, which connects
an additional time constant in parallel to pin 2 during multipath interference,
or activates another circuit to suppress variable interference.
Demodulator time constant: determines the response and hold time of the
identification circuit.
Supply voltage: to be RF decoupled to pin 1
Identification input: high impedance input (R j - 10 kO). This input receives
variable interference forwarded on the field strength voltage via a high-pass
filter.
Input for setting limiter threshold: with' a potential between VREF arid 0 V, the
limiter threshold can be varied by approx. 44 dB.
Operating point feedback to be RF decoupled. For efficient push-push
suppression, pin 16 should be blocked against pin 17 and latter to ground
(pin 1).
IF input: frequency modulated IF voltage is injected at pin 18.

TDA4210-3

Block diagram

v"

.1
18

17

2

16

15

4

5

6
VAF(

VM =
f(VFl
VqAF + Vs

VST

T

7

8

9

VREF

T

8-67

TDA4210-3

Measurement circuit
RG=50Q

22 nFl

Vs

V,MP

-50Q

22nFl2~lnF

J.

II

18

v,o

V"

17

10 IlF

1
16

15

13

14

12

I

100
kQ

10
kQ

~

~

11

10

8

9

TDA 4210-3

2

3

4

II

MUTE

6

5

1100
kQ

MUTE

T4.7JJF

ON/OFF Depth

VqAF

+ lis

!10 JJF

V. tab

STS

li

8-68

7

* Rj <10Q

SIEMENS

TDA4930
Stereo/Bridge AF'Amplifier 2 x 10 W/20 W
The TDA 4930 can be applied as a class B stereo amplifier or mono amplifier in bridge
configuration for AF signals. In addition, the component is provided with a protective circuitry
against overtemperature and overload.
Features

•
•
•
•

Universal application as stereo amplifier or mono amplifier in bridge configuration
Wide supply voltage range
Minimum of external components
Outputs AC and DC short-circuit resistant

Maximum ratings
Supply voltage
Output peak current
Input voltage range
Junction temperature
Storage temperature range

Vs
II; Igpp
V2 ; V3 ; V7

Thermal resistance (system-case)

R1hJC

7j
T.tg

32
2.5
-0.3 to Vs
150
-40 to 125 '

I6

V

A
V
°C
°C

IKIW

Operating range
Supply voltage
RL~8

Q

Vs
Vs
Tc

RL=4Q
Case temperature

Pv =10W

8-69

8 to 26
8 to 22
-20 to 85

I~c

TDA4930

Characteristics
Vs ==19 V; TA ==25 DC
Test
circuit
Quiescent current (W= 0) ,
Output voltage (V; = 0)
Input resistance1)
Output power (t = 1 kHz)
- stereo operation
THO= 1%
THO =10%
- bridge operation
THO= 1%
THO=10%

min

typ

max

9

30
9.5
20

60
10

7
9

8
10

W

14
18

16
20

W
W

40

46

,dB

15
Vq9 ;1

R j7 ;3

Pq9 ;1
Pq9 ;1
Pq9 ;1
Pq9 ;1

2
2

rnA
V
kQ

W

Line hum suppression 2 )
t,= 100 Hz; V, -0.5 V

ahum

Current consumption

15

1.5

A

"

70

%

Pg -P1 =10 W; t, =1 kHz
Efficiency
Pg -P1 =10 W; tl =1 kHz

THD

0.2

a e,
Cross-talk rejection
-1 kHz; Pg or P1 -10 W
Transmission range3 )
B
Disturbance voltage (B - 30 Hz to 20 kHz) , Vd
in acc. with DIN 45405 referred to input")
Noise voltage (CCIR filter)
Vn
in accordance with DIN 45405
referred to the input4 )
Difference in transmission measure
.dG v
Pg -P1 =7W
=40 Hz to 20 kHz

50

Total harmonic distortion
P9/1 - 0.05 to 6 W
'1 =40 Hz to 15 kHz

'j

0.5

%

dB

40 Hz to 60 kHz
w
5

JlV

15

IlVs

'1

dB

'1

Voltage gain stereo
Voltage gain bridge configuration

Gv
Gv

1
2

30
36

DC output voltage at
active DC protection
ifS1/9 is closed; Vs~1OV

Vq9 ;1

2

0.15

1)
2)
3)
4)

52a(b) open/closed
51a(b) and 53 in position 2
Pgl1 - 6 W; -3 dB referred to 1 kHz
51a(b) in position 2

8-70

dB
dB

0.30

V

TDA4930

Circuit description
The IC contains 2 complete amplifiers and can be used for a wide variety of applications
with a minimum of external circuitry.
The TDA 4930 can be applied as stereo amplifier or amplifier in bridge configuration for
operating voltages ranging between '8 V and 26 V, with speakerload impedance from 1 to 16 Q.
The prestages are differential amplifiers with strong negative feedback. Internal frequency
compensation in the driver amplifier limits the gain-bandwidth product to 4.5 MHz.
The power output stages are comprised of quasi PNP transistors (small saturation voltage).
Each power element is equipped with an independent protective circuit, rendering the outputs
of the amplifiers AC and DC short-circuit resistant.
A DC protective circuit of the outputs prevents overloading of the loudspeakers, if ground
connections become apparent during bridge, operations. To avoid overheating, a temperature
fuse affecting both amplifiers prevents current supply to the power output stages during
inadmissibly high chip temperatures.
As a special economic feature, the negative feedback' resistances for Gv = 30 dB and the
input voltage reference divider have been integrated.

Pin description
Pin

Function

1

Output right channel
Inverting input right channel
(more than 22 kQ)
Non-inverting input right channel
GND
+Vs
GND
Non-inverting input left channel
Line hum suppression right and left channel
Output left channel

2

3
4
5
6

7
8
9

8·71

TDA4930

Block diagram

R

30,6 R

9

Output
Left

7
+ Input
Left
20kQ

+Vs 5
H~m

Line Hum
Suppression 8
Circuit

Suppresslon

Power
Supply
and
OverTemperature
Protection

Protection
Circuit

DC Output
Protectlve
Circuit

4.6
GND

Protection
Circuit

20kQ

+Input 3
Right
-Input 2
Right

Output
Right
22kQ

R

8-72

30,6R

TDA4930

Test and measurement circuit
1. Stereo operation

TDA 4930
Power Supply
+

15,3 kR

22 kR
500R

500Q

20 kR
7

9

4,6

5

2 3

100nF
20 kR

20kQ

lmF

S2 a

+Vs

S2b

GND

8-73

TDA.4930

Test and measurement circuit

2. Bridge operation

TDA 4930
r--r--

~

y

/- -

Power Supply

~-

-

+
0---

1]15.3 kn

[ 15.3 kn

15.3 kn[]

~

-

.

I---

246n[

500n[ ]

)1 kn

~

-

500nl]

~

22 knO

~

-

7

9

a

5

4;6

1

2 3

= :=1~F

1pF = :=

-an

~
220nF= =

V,

-

~

100~F=

i=

= := 220 nF

H{

O,n
100nF
II
/I

1~F
UI

+Vs

8-74

GND

1 ~F=

TDA4930

Application circuit
1. Stereo operation

lOA 4930
Power Supply
+

15.3 kQ
22kQ
500Q

246Q

20 kQ
7
220nF

9
[4

5

2 3

220nF

[2
[6

220nF

220nF

[3

[5

RL

[7

11;

+Vs

•

100 nF

VI

GND

Vs

19V

RL

4Q

26V
8Q

[L

OOO~F

470flF

8-75

TDA4930

LayoutlPlug-in location plan

8-76

TDA4930

Application circuit
2. Bridge operation (only one channel)

lOA 4930
r-r--

~

/- -

Power Supply

/

~-

-

+

.-.-15,3 kl'lO

I]15,3kl'l

015,3 kl'l

m£!

-

~

-

t--

500l'lO

246l'lO

500l'll]

I}kl'l

~
7
[8

-

22kl'lIJ

~

-

9

8

5

4;6

1

2 3

=

220 nF =~

r=220nF

[7

220nF=~[1

[2 =~220nF

R2

[4

}Q

•

n100nF
II

I
I

1000 pF

nr

v,

220nF=p [6

Vs

RL

I 19V I 26V I
I 8l'l I 16l'l I

GND

8-77

TDA4930

Layout/Plug-in location plan

C)OL()

8-78

IL() ()-

TDA4930

Quiescent current versus
supply voltage
rnA
50

Typical operating range of the
final transistors adjusted by
internal protective circuits
A (SOA = Safe Operating Area)
2,5
'//'r~
2,375 ;..I~

- .

Ie

I
./

II

35

./

V

V
./'

30

V-

25

1,625
1,5

~

~l ~
~\

~\
~\
1,0

',/

V
./'

~
;..-

Dynamic Straight
for 4 Q/19V

~

~

'~

~

\

~

I

20

2,0

\\ SOA '/~

0,5

\ Dy~amiC

~
'/,

Straight

~r8W26V
8

12

16

20

24

28

32 V

o ////
o

~

'/,

5

10

15

20

25

~

30

35 V

-VCE

Stereo operation

Stereo operation

Output power versus
W supply voltage

Output power versus
W supply voltage
10

II

V
VV /

f = 1kHz
RL = 4Q
THO =10%

8

12

/

!

f = 1kHz
RL= 8Q
THO =10·/'

VV

6

,
4

VJ
/

VII,! /

2

~

o

8

/
,/

8

6

VI . Rf ==1kHz
4Q- -

,/

L

THO-1%

4

V

/ V

V

V

,/ L '/
'/

V /

V /V

V

f =1kHz RL =8Q

V

,/

THD=1%

2

o
10

~

V

L

12

14

16

18

20 V

16

18

20

22

24

26V

8·79

TDA4930

Bridge operation
Output power versus
W supply voltage
20

Pq

t

,

I
IL

f = 1kHz
RL= 8Q

16

Stereo operation
Total harmonic distortion
% versus output power
10
Vs = 26V
f = 1kHz
RL = aQ

IL V
VV V

THO= 10%

12

~

8

4

6

V/
V

L~

tL IL

VV
V

= 1kHz
RL = 8Q
HO= 1%
f

t-

Y

2

~V

o
o

10

4

12

14

16

18

20 V

I)

o
o

a

4

12

16W

-Vs

Stereo operation
Total harmonic distortion versus
% output power

Stereo operation
Power dissipation (each channel)
W versus output power

10

6

THO

I

8

J

I
Vs = 19V
.f = 1kHz- tRL = 4Q

6

II

......

VS = 19V
f = 1kHz
RL = 4Q

I

3

r---- J"...

V

I

1"-

"

4

I

1I

2

o
o

2

.l
2

4

6

a

10 W

o

o

2

4

6

a

-Pq
8·80

10 W

TDA4930

Stereo operation

Stereo operation

Efficiency versus output
% power
100

Power dissipation (each channel)
Wversus output power

6

I

I
)

V

~

k.. I

II

4

I
I

I
I

I

i I

I'-k

!
,

3 I

I

I

K

Vs = 19V
f = 1kHz
RL = 4n

~

60

Vs = 26V
f = 1kHz I-- I-, RL = an I--I--

I

2

I

./

/'

17

V

. . .V

40

/

I

!

V

20

/
/

1

o
o

2

4

a

6

10

o

12 W

o

2

4

a

6

Stereo operation

Stereo operation

Power dissipation (each channel)

Efficiency versus output
% power

W versus supply voltage

100

5

/

~ot

.,,-

60

/

40

20

/

I

V

/

V

V

1

/'

4

V

f = 1kHz
RL= 4n

3

V

Vs= 26V
f = 1kHz
RL= an

2

V

J
4

a

J

V

V

THO-1%j

1/

o
o

10 W

12 W

o
a

II

/

12

)

1/

If =1kHz
RL=an
THO-1%

V

16

20

24

28 V

-VS
8-81

TDA4930

Stereo oper~tion

Stereo operation

Supply current (one channel
A modulated) versus output power

Total harmonic distortion
% versus frequency

1,0

10

Is

t

THO 5

Vs = 19V
f =1kHz

0,8

RL = 4f2

,/

V

0,6

/

,/

/

0,4

J

1/

/1/

0,2

/
/

/

V

V

t

./

2

./

Pq

V

Vs = 26V_ rf = 1 kHz

=8

wV

0,5

RL = 8f2- I---

V

/11
0,2

'/1

o

Vs = 19V
RL = 4f2

.... ~ ~Pq

0,1

"

=7W

111111

o

2

4

8

6

10

12W

10 4 Hz

-f

Line hum suppression versus
dB frequency

Cross-talk rejection
dB versus frequency

50

70nnTIr-'TTnurr-.-rn~~

1111
i

i

!
40

I

iI

I

Vs= 19V
RL = 4f2
. Rs= 10kf2
r = O,5V

v

I

II

!!lLJ-~,

/'

!

i

Bcr

t

I

I

!II
LL iii

i

\1 I

JIIIII

I111

!J!JI!II Vs=19V
~~ RiL~I'~ r I

\1
I

\
\

I
I

50

30

~4i±:jl:tt'mt=:t:HN..uDll\\j
:i

I Pq

= 10W

\

\

10' Hz

-f

8-82

\

-f

SIEMENS

TDA4935
Stereo/Bridge AF Amplifier 2 x 15 W/30 W
The TDA 4935 can be applied as a class B stereo amplifier or mono amplifier in bridge
configuration for AF signals. In addition, the component is provided with a protective circuitry
against overtemperature and overload.
Features

•
•
•

Universal application as stereo amplifier or mono amplifier in bridge configuration
Wide supply voltage range
Minimum of external components

Maximum ratings
Supply voltage
Output peak current
Input voltage range
Junction temperature
Storage temperature range

V

T.tg

32
2.8
-0.3 to Vs
150
-40 to 125

RthJC

4

KlW

Vs
Vs
Vs
Tc

8to 30
8to 24
-20 to 85

V
V
°C

Vs

II; 19
V2 ; V3 ; V7
~

Thermal resistance Jsystem-case)

A
V
°C
°C

Operating range
Supply voltage
RL~80

RL =40
Case temperature
Pv=15 W

8-83

, TDA4935

Characteristics
Vs .. 24 V; Tc .... 25 DC
Quiescent current

Test
circuit

min

Is

typ

max

40

89

rnA

12

13

V

lIt-O
Output voltage

lIt-O
Input resistance 1)
Output power
f-1 kHz
- stereo operation

THO- 1%
THO-10%

11

Vq1 ;9

R13 ;7

20

kQ

Pq1 ;9
Pq1 ;9

1
1

10
13

12
15

W
W

Pq1 ;g
Pq1 ;g

2
2
1

20
26
40

24
30
46

W
W
dB

Is

1.8

A

TJ

70

%

THO

0.2

a~r

50

- bridge operation

THO- 1%
THO-10%
Line hum suppression 2 )
fR -100 Hz; VR-0.5 V
Current consumption
P9 -P l -15W;fl -1 kHz
Efficiency
Pg - P1 -10 W; '1 - 1 kHz
Total harmonic distortion
Pgl1 -0.05 -10 W
fl -40 Hz to 15 kHz
Cross-talk rejection
fl -1 kHz;
Pg orP l -15 W
Transmission range3 )
Disturbance voltage (B'" 30 Hz to 20 kHz)
in acc. with DIN 45405
referred to input4 )
Noise voltage (CCIR filter)
In acc. with DIN 45405
referred to the Input4 )
Difference in transmission measure
Pg -P1 ""10 W
fl -40 Hz to 20 kHz
Voltage gain
stereo
, bridge configuration

1)
2)
3)
4)

S2a(b) open/closed
S1a(b) and S3 in position 2
P9/l - 6 W; -3 dB referred to 1 kHz
S1a(b) in position 2

8-84

ahum

B
Vd

40 Hz to 60 kHz
5
15

Vn
.4G v

Gv
Gv

0.5

%
dB

j.LV

j.LVs

dB

1
2

30
36

dB
dB

TDA4935

Circuit description
The Ie contains 2 complete amplifiers and can be used for a wide variety of applications
with a minimum of external circuitry.
The TDA 4935 can be applied as stereo amplifier or amplifier in bridge configuration for
operating voltages ranging between 8 V and 26 V.
The prestages are differential amplifiers with strong negative feedback. Internal frequency
compensation in the driver amplifier limits the gain-bandwidth product to 4.5 MHz.
The power output stages are comprised of quasi PNP transistors (small saturation voltage).
To avoid overheating, a temperature fuse affecting both amplifiers prevents current supply
to the power output stages during inadmissibly high chip temperatures.
As a special economic feature, the negative feedback resistances for Gv = 30 dB and the input
voltage reference divider have been integrated.

Pin description
Pin

Function

1

Output right channel
Inverting input right channel
(more than 22 kO)
Non-inverting input right channel
GND

2

3
4
5
6

7
8

9

+Vs
GND
Non-inverting Input left channel
Line hum suppression right and left channel
Output left channel

•
8-85

TDA4935

Block diagram

R

30,6R

>------;9

+ Input 7
Left

t--.,---1

Output
Left

20kQ

+Vs

5 t---I----1------I

Hum
8 t - -.......--1 SupLine Hum
pression
Suppression
Circuit

Power
Supply
and
Temper- 1 - - - - - - - - - - - - - 1 4,6
ature
GND
Protection

20kQ

+ Input 3

t-----;

Right

>-----1>------1 1

-Input 2 t--2L2=k:J
Q-'--;
Right

R

·8-86

30,6R

Output
Right

TDA4935

Test and measurement circuit

1. Stereo operation

TDA 4935
Power Supply
+

soon

7

6

2

s

B

10;6

20kQ
S2a

2

3

20kn
.......c..:...J-..--'" 40 ms (1 /30s)·.
With connection of the supply voltage, the circuit is
automatically reset. A timing period does not commence if 0 potential is applied to S.

Triac Stage
Pin TS (triac synchronization) is the input of a zero
voltage switch and serves to synchronize the output
T (open collector) with the load voltage or the load
current.
With Vs

Mains frequency = 50(60)* Hz; set range 1 (base
time = 1s); D, F and I are connected to A (value =
37): resulting delay time is 37 seconds.
The timer allows two operation modes which are set
through pin FC (function changeover):
1. The "momentary switching function" in accordance with DIN 46120.
The triac at pin T turns "on" with the rising edge
at the start input S and turns "off" when the set
time has passed, independent of the start pulse
length.
2. The "swltch-off-delay" in accordance with DIN
46120.
The triac turns "on" with the rising edge at S. The
falling edge at S starts the timing period. The triac
remains in on-state until the set period has
passed.
Fu~ction

To protect the start input S against external interference and contact bounce, it has a dead time of
between 20 and 40 ms (1/60s to 1/30s)' for positive switching edge, depending on the phase of the
50(60)* Hz line. Both operation modes are retriggerable during the timing period.

Changeover:
FC

Operation Mode

L Momentary Switch Function
H

< 3V, the output current is disconnected.

The input TC has a double function:
• To change TS over to voltage synchronization.
• To adjust the triac trigger pulse width (by connecting a capacitor Ce to TC) in case of current synchronization.
Three operation modes are possible by varying the
connection of the pins TC and/or TS:
Operation Mode 1:
TCtoVS:

Output T is connected to the zero
voltage switch. T operates when
Vs -1.3V s: Vrs s: Vs +1.3V.
Is utilized in case of voltage synchronization; see application circuit 1 (operation with resistive
loads) and pulse diagram.

Note:
'Valid for 60 Hz version.

Switch-Off-Delay
9-3

SAE 0530, SAE 0531
Operation Mode 2:
TC via Ce to Q:

Output T is connected to the zero
voltage switch via a monoflop. If
Vs -1.3V is fallen below or Vs
+ 1.3V exceeded at TS, the output T releases a triac gate trigger
pulse determined by Ceo
Is utilized in case of current synchronization; see application circuit 2 and pulse diagram.

RG =

Vs - VTL - Gate Trigger Voltage

-"----:'""~-:----:-'------~

Gate Trigger Current

0.6 x rms Line Voltage x - Vs
Rv = Is + Average Gate Trigger Current
(With or Without Diode D)
Average Gate Trigger Current = 0.1(0.12)·
Trigger Current x Z (Z in ms)

x Gate

Power Dissipation at Rs _ (rms Line Voltage)2
(Without Diode D)
Rs

Operation Mode 3:
TC and TS to Vs: Output T conducts after release
of start pulse.
Is utilized for any load in case of
continuous triac triggering (e.g.
low performance), or if any other
load is to be operated instead of
the triac (see application circuits
3,4,6).

Operation with Line Voltage
A series resistor Rs and a charging capacitor Cch
serve for line voltage supply. If a diode is connected
in series with Rs (anode to N), the rms current consumption is halved. The series resistor may also be
an RC combination (see application circuit 6).

Operation with DC Voltage
This IC can also be operated with DC voltage or
current (see application circuits 4 and 6).

(rms Line Voltage)2
Power Dissipation at Rs _
(With Diode D)
- 0.6
Rs
CL = 20(17)*

x r~s Line Voltage

,

s

(Residual AC Voltage at Vs

s

[p.F, V, k!l]

0.6 VSS)

NoteforCL:
If short-term line failures are to be compensated, CL
has to be accordingly larger. (Approx. 1000 p.F for s
6s line failure.)
,
Note:
·Valid for 60 Hz Version.

Application Circuit 1 (Voltage Synchronization'
for Resistive Load)
0.22(0.27)·
RSyn =
;<:

x Z x rms Line Voltage -1.3
0.04

Peak Line Voltage [k'" V
]
4
u, ,ms

(Valid for Z

s

1.5 ms)

Dimensioning the Application Circuits
The following formulas give reference values for operation with sine-shaped DC voltages of 50(60)· Hz.
The triac is always triggered with negative gate current.
Trigger Pulse = 5(4.18)· x Holding Current [ms]'
Length Z:Z
rms Load Current
'
Applies to Z s 1 ms

Note:
·Valid for 60 Hz version.

Notes for Application Circuit 1
An average ITS of 0.04 mA was inserted into the
formulas approximating RSYNC. As ITS + and ITScontain production deviations, utilizing the determined RSYNC requires certain tolerance,s to be taken into account for pulse length Z.
To minimize the effect of these tolerances, a resistor
may be connected between VS and TS, which generates a constant current of

V~s to be added to ITS.

However, a TC of -4 mViK should be noted.

Note:
·Valid for 60 Hz version.

9-4

SAE 0530, SAE 0531

Application Circuit 2 (Current Synchronization)
Ce

=

Application Circuit 4

22 X Z [nF, msl

RN :::: 15 X AC Voltage 50(60)' Hz [kn, Veffl

RSYNC ~

1
Max. On - State Voltage - 1.3 [
I
kn, V, mA
TSmin

RSYNC ~

Peak Line voltage [
1
4
kn, V

RSYNC

V
1
GateTrigger Voltage -1.3 [
I
kn, ,mA
TSmax

s:

Application Circuit 5
RN see above. The AC voltage for the timing base
must be greater than (supply voltage -4.8V).
R

R1 =

Notes for Application Circuit 2
In this circuit, an even shorter pulse length than determined for Z is' sufficient to trigger the triac. This is
possible by the trigger pulse being automatically repeated until the holding current is reached. Overdimensioning of Z for safety reasons is, therefore, not
necessary. The disadvantage of multiple trigger
pulses, however, is a somewhat larger interference
band during the triggering.
The interference band and/or the interference amplitude generated also depend on the amount of the
gate trigger voltage necessary to trigger the triac after each current zero passage. That voltage is determined by the size of RSYNC and should not be more
than 20V.

+ Supply Voltage -6.8V I
_ I
I
Is + IR1
R1 - B (TO) + R2

o=

6.8V - VTL - VBcrO)
_
I
= IR2 - 0.05 IB(TO)
R1

- VBcro)
R2IR2

Application Circuit 6
- 4(3.3)' [ F k 1
Cs-~,...,n
Rss = 0.2 X Rs
To limit the inrush current, Rss has to be ~ 0.2 As.
Otherwise, the circuit may be damaged.

Note:
'Valid for 60 Hz version.

Application Circuit 3
Dimensioning of Rs, RG and Cch as described at the
beginning of this section.

Absolute Maximum Ratings*
·Stresses above those listed under "Absolute Maximum Aatings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to
the integrated circuit. Max. ratings for case temperature - 25·C to + 85·C.

Parameter

Symbol

Supply Voltage at Impressed DC Voltage

Vs

Peak Current at N

-INP

Limits

Units

Notes

Min

Max

-0.3

+5.5

V

18

mA

50 Hz Operation with Vs

-50

+50

mA

50 or 60 Hz Operation

s:

DC Current from N (rms)

-INrms

AC at N with Impressed Current

INrms

35

mA

rmsValue

Peak Current at N

INP
INP

-200
-350

+200
+350

mA
mA

2 ms/1 00 ms Duty Cycle
0.3 ms/1 00 ms Duty Cycle

Voltage at A, S, C, FC, A, S

VA

-0.3

7.5

V

7.5V

9-5

SAE 0530, SAE 0531

Absolute Maximum Ratings· (Continued)
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to
the integrated circuit. Max. ratings for case temperature - 25·C to + 85·C.

Parameter

Symbol

Limits

Units

Min

Max

Vo

-0.3

7.5

V

Voltage at N, with N Utilized as Clock Input

VNT

-0.3

Vs

V

VoltageatT

VT

-0.3

7.5

V

VTC

-0.3

Vs

V

Voltage at D, E, F, G, H, I

Voltage at TC
Current in D, E, F, G, H, I

10

0.5

mA

Continuous Current in T

IT

100

mA

Peak Current in T

ITS

Current at TS

ITS

Junction Temperature

Tj

Storage Temperature

Tstg

150

mA

-4

+4

mA

125

·C

-55

+125

·C

70

K/W

Thermal Resistance: System Air
RthSA
.' specified.
All the voltages refer to pin 0, unless otherwise

Notes
D ... I Off-State

D ..• IOn-State
1 ms/10 ms Duty Cycle

Operating Range
Within the functional range, the IC operates as described; deviations from the characteristic data are possible.

Parameter

Limits,

Symbol
Min

Max
5.5(8.2)

Units

Notes

V

•

•
•

Supply Voltage

Vs

4.5

DC Supply at N(rms)··

-IN

2.5

18

mA

INeff

5

35

mA

AC Supply at N(rms)**

·C
-25
Ambient Temperature
85
TA
Notes:
'The operating voltage should not exceed 5.5V when AC voltage is impressed. The IC can also be operated with AC or DC
current. In case current is impressed at N the Vs is limited between 6V and 8.;!V (typ. 7.5V). The IC functions, however, up to
4.5V.
• 'Only the supply current for the IC, i.e. without triac gate current. The rms gate current flows additionally through N.

9-6

SAE 0530, SAE 0531

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not stated otherwise, typical characteristics will
apply at 4.5 ::;; Vs ::;; 5.5 (7.5)' V; -25·C ::;; TA ::;; 85·C.
Parameter

Symbol

Conditions

Test
Circuit

Limits
Min

Units

Typ

Max

Supply Current

Is

VlnputS = OV

1.5

2.5

rnA

Vs with Impressed Current at N:'
Vs Impressed AC'
Vs Impressed DC

Vs
Vs

INeff = 5 rnA
-IN = 2.5 rnA

7.5
7.5

8.2
8.2

V
V

Switching Threshold at:
A,B,C,S,FU,R

VA

1.1

1.8

2.2

V

H-Switching Threshold at N"

VN

2

2.4

L-Switching Threshold at N"

VN

0.8

1.1

Switching Threshold at TC

Vre

Switching Threshold at TS
(For Voltages> Vs)

Vrs+

Switching Threshold at TS
(For Voltages < Vs)

Vrs-

L-Input Current at:
A,B,C,FC,R

-IA

VA = OV

L-Input at S

-llnS

L-Input Current at N"

-IN

H-Input Current at:
A,B,C,S,FU,R

"IA

3.4

V
V

4.5

V

Vs+1.3

.v

Vs-1.3

V

20

30

p.A

VlnputS = OV

60

90

p.A

VN = OV

40

60

p.A

1

p.A

VA = Vs

H-Input Current at N"

IN

VN = Vs

H-Input Current at TC

Ire

4.5::;; Vre::;; Vs

1

p.A

20

40

p.A

Positive Switching Current at TS

Irs +

20

40

80

p.A

Negative Switching Current at TS

Irs-

20

40

80

p.A

10 = 0.5 rnA

0.2

0.4

V

1

p.A

Ir=1mA
Ir = 10mA
Ir = 100mA

0.7
0.8
1

1.1
1.2
1.5

V
V
V

L-Voltage at D, E, F, G, H, I

Vo

H-Reverse Current at D, E, F, G, H, I

10

L-Output Voltage at T

Notes:

'With current impressed at N
"For N as clock input

Va
Va
Va

SAE 0530, SAE 0531

Application Circuits
9peratlon with Resistive Load

~.. " . " ; ; ; ; ;

I

ONSFCABCRD

i

, . . - - -0" - - - .. - - - .. - - - ... - . - . ,

I~

20V/SOor6OHz

CL

L--+-+r".:~,
R.

,I

1

1

I,

....rt~
OorVs

l.......l---j
"'set

Load

, 'D(option)
0150-2

Operation with Resistive, Capacitive or Inductive Loads

S;~

RG

r--+-+-______--l:=l~AI

.•" ",~.. " • ~ ~··:··~···;···:···1:
SOor 60 Hz

Co

c.. 1I
ONSFCABCRD

L-~-+--l-7":.J

....rt

,I

1

1

I,

i

~---j

"----v----J ,...,
OorVs

RS
'D(optlon)

0150-3

9-8

SAE 0530, SAE 0531

Application Circuits (Continued)
Operation with Any Load and Continuous Triac Triggering

RG

I.
Vs T5
220V150o,60H.

=~CL

T TC

;

~ ~ ~ ~

D

:

:

ONSFCABCRD,

~

1

'v

)

.1

1

1

I.

!.....l.-j

stln '-----.....,,-reset
OorVs'

0150-4

Operation with 5V DC Voltage
+SV

."'011 ....

so or 60 Hz 1>2.SV
0150-5

9-9

SAE 0530, SAE 0531

Application Circuits (Continued)
Pul.e Generator
Vs

VS(5V)

Vs TS T TC

H G F E

I

)
0

N

5 FC A

8

C

R D

dock Input
SV/SOor60" HI

Off~ ...Jon

o

trigger
output

o
Ot50-6

II

-l

trigger output ____

~

--Il__---'n

I--

tl (Pulse· Width) = 40 ms (1/30s)·
t:! (Selected Time) = 15s

nL-__....JrL
to

moo

--.j
0150-7

Not..:
·Valid for 60 Hz version.
The pulse width t, is determined by the clock frequency at clock input N:
tl = 2/f = 2/50 (2/60)· = 40 ms (1/30s)·
.
Direct after switch on the pulse width tl and the first time period t2 can be shorter by 20 ms (1/60s)· depending on the phase
of 50 Hz or 60 Hz clock inpul
The output T is conducting after switch on and remains on L-potential throughout the operating time.

9-10

SAE 0530, SAE 0531

Time Control for Bathroom Ventilator Motor, (Adjustable to 3, 6 or 12 minutes ventilation)

I

light sWitch

r·_·_·_·_·_·_·_·_·_·_·_·_·_·_·_·_·_·_·
1lO

+~ iI 12011 1I0V

vs

TS T TC

I

S~

'SDk

I~:.~

,.--

TXC01ESO

._.,

I I
H

G

F

rE
I

D
220V/SOor

0

60Hz.

N

5 FC A

B

C

R

D

I I

-"
2,211~~OV

I

l)~

2 x IN4005

.....:.-

O.15(O.l.W"f:~

680k

12

400 V

Uk

22011.

'-~

L.._._._._._ '-'-'-'-'-'-'-'-'-'-'-'-'
ventilator motor
220V/25W

~ ~ room lighting

._ •...J

9

M
0150-8

Application Description of a Ventilator Motor Control:

The ventilator is activated with the light switch and automatically switches the motor off after a programmable time delay
of 3, 6 or 12 minutes after the light switch is tumed off.
(We don't take any responsibility for the component values in this application.)
'Valid for 60 Hz version .

. Diagrams
Pulse diagrams of the two operation modes set with pin Fe:

Momentary Switching Function
>40ms

start pulse at 5

(>1/30s)·

voltage at the load
_

set tome

__

max 31.Shrs

voltage at RID ..1

--

--

S-deadtime

R-deadtome

20to40ms

4Om.
(1130.)'

(1/60511o.1/30s)'

0150-9

9-11

SAE 0530, SAE 0531

Diagrams (Continued)
Pulse Diagrams of the two operation modes set with pin FC (Continued)

Switch-Oft-Delay
> 40ms

- >40m,

stan pulse at S

(>1130,)-

(>11300)'

L

voltage at the load

set time

mix 31,5tvs

-- -

voltage at RID... I

-.

S-deadtime

S-deadtime

R-deadtime

20 to .0 ms
(1160 ,to 1130.)'

20to40ms
(116O.to 1130.)'

(11300)'

.om.

0150-10

'Valld for 60 Hz version.

Pulse Diagrams for Triac Operation Modes 1 and 2

Operation Mode 1 Voltage Synchronization with Resistive Loads (TC to Vs)
... Vat theloed
... 1 at theloed

Vs

.
Vs

ill

..... .

..f.:.
I! I

Vs

[jJ

0

!

··
i

~

.."iK.
.

r-"'
7--

~VT

I! I

"

ill

·
I

VTS

0
0150-11

Operation Mode 2 Current Synchronization with Nonresistive Loads (Capacitance Ce to TC)
... v at the 100d
.... atthe 100d
'vs------~--~f------4.---~------~--~~----

~+-!-----"

t--..

!
VTS
vS--::::::~~/~!!~--------4v~~1~_-_-_-_-_-_~-_-_-~~1------

Vs

--...:....----.;;~t-bi-~T:..;;.-.-----:;..+l1J+-r-t:..:-----,.D-,r-::..~-VT

1=

f(CoI

o
0150-12

9-12

SAE 0530, SAE 0531

Appendix
Internal Connection of the Input, Output and Supply Pins
s
FC;A;B;C;R

0150-13

D;E;F"G;H;I

VS.-.-.-.---------------.-----------~

o

TS
0150-14

Vref

TC

, - - - - -.... T

0150-15

•

Comparison of the Different Timers
Characteristics

Type

Package

SAB0529

SAE0530

SAE0531

DIP 18,S020

DIP 18, SO 20

DIP 18, SO 20

Same Pin Configuration

so Hz

Mains Frequency
Temperature Range

O·Cto +70·C

Switch in Delay at S

For Leading Edge

Switch in Delay at R
Start Response after
Connecting Vs

so Hz

60Hz
- 2S"C to + 8S"C

For Leading as Well as Trailing Edge

No

Yes

S=L

No Start

No Start

S=H

Undefined

Timer Starts

9·13

SAE 0530, SAE 0531

Comparison of the Different Timers
Characteristics

Type

Integrated Pull-Up
Resistance at S

(Continued)
·SAB0529

SAE0530

SAE0531

No

Yes

Switching Threshold at
A,B,C,S,FU,R

0.6V

1.8V

Switching Threshold at N

1.2V.

1, YzV,
Hysteresis of 0.9V

State of Pins D to I after Reset

L

H

Output Voltage at T by 100 mA

1.8V

1V

Operation as Pulse Generator

With External
Components

Without External
Components

Note:
For other minor deviation please see max. ratings and characteristics of the components.

Ordering Information
Type

Ordering Code

SAE0530

Q 67000-H8403

DIP 18

SAE 0531

Q 67000-H8431

DIP18

9-14

Package

SIEMENS

SAE 81 C 52
256 x 8-Bit Static CMOS RAM
NMOS-Compatible
Preliminary data
Type

Ordering code

Package

SAE S1C52 P
SAE S1C52 G

067100-HS003
067100-HS004

DIP 16
SO-20

The SAB S1 C 52 P is a CMOS silicon gate, static random access memory (RAM), organized
as 256 words by S bits. The multiplexed address and data bus allows to interface directly
to S-bit NMOS microprocessors/microcomputers without any timing or level problems,
e.g. the families SAB SOS5, SAB SOSS, SAB S04S, SAB-S051. and SAB S0515.
All inputs and outputs are fully compatible with NMOS circuits, except CS 1. Data retention is given up to Voo ~1.0 V. The SAB S1 C 52 P has three different inputs for two chip
select modes which allow to inhibit either the address/data lines (AD O... AD 7) and the
control lines (WR, RD, ALE, CS 2, CS 3), or only the control lines RD, WR.
The power consumption is max. 5.51JW in standby mode and max. 2.75 mW in operation.
In standby mode, the power consumption will not increase if the control inputs are on
undefined potential.

Features
• 256 x S-bit organization
• standby mode
• compatible with the IJC/IJP families SAB SOS5, SAB SOSS, SAB S048, SAB S051,
the new SAB S0515, etc.
.
• very low power dissipation
• data retention up to Voo = 1 V
• three different chip select inputs for two chip select modes
• no increasing power consumption in standby mode if the control inputs are on
undefined potential
• Temperature range: SAB S1 e 52
ooe to 700 e
SAE 81 e 52
-40 oC to +85OC *)
• Package: DIP 16 or SO-20'

0) Values for applications up to -40"C to +11 O°C upon request.

9-15

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Pin configurations
(top view)
SAB 81C52 P
SAE 81C52 P

SAE 81C52 G
ADO 1

20 Voo
19 RD

ADO

1

16 Voo

AD1 2

AD1

2

15 RD

3

AD2

3

14 WR

AD 24

AD3

4

13 ALE

AD3

AD4

5

12 (51

AD4 6

15 (51

ADS

6

11

AD7

ADS 7

14 AD7

Vss

7

10 AD6

8

13

(52

8

9 (53

9

12 AD6

(52 10

11 (53

Vss

~

18
17 WR
16 ALE

Pin designation
Pin No.

Symbol

SAE 81C52 G

SAB 81C52 P
SAE 81C52 P

1,2,4,5,6 }
7, 12, 14
15

1 .. : 6
10, 11
'12

16
17
19
20
9
10

13
14
15
16
7
·8

ALE
WR
RD
Voo
Vss
CS 2

11

9

CS 3

9-16

}

Function

AD 0 ... 7 Address/data lines
CS 1

Chip select 1 (standby)
active low;
inhibits all lines including control
Address latch enable
Write enable
' Read enable
Power supply
GND
Chip select 2;
inhibits control inputs RD, WR
Counterpart to CS 2

nn~s

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Logic symbol

(S1
Address! data
bus, B bits

(S 2

(S3

SAB

ALE

81(52

RD
WR

Truth table

CS 1 CS 2 CS 3 ALE
L
H
H
H
H
H

RD

WR AD 0 ... AD 7

*X *X *H *H *H
H
H
L

L
L

X
X r H

*: Level =

L
L
L
L

L
H

H
L

X
X

X
X

floating (tristate)
addresses to memory
data from memory
data to memory
floating (tristate)
floating (tristate)

Function
standby
store addresses
read
write
none
none

/

Vss··· Voo

X: Level = LOW or HIGH

9-17

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Block diagram

~

Addrl'ss
latches

Gated,
row
decoder

A2. A7

32

x

64

Matrix

Read logic

I--

--V

Wnte logic

I---<

:-----

Gated column
decoder

£J
ADO ... AD7

¢::>

Bus
Interface

"-

--

ALE

R5
WR

(51
(52

.

9·18

(53

Control
logic

~
'--v'

Address
latches
AO,A1

-

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Maximum ratings
Maximum ratings are absolute limits. The integrated circuit may be destroyed if only a
single value is exceeded.
Supply voltage reftered to GND (Vss)
All input and output voltages
Total power dissipation
Power dissipation for each output
Junction temperature
Storage temperature
Thermal resistance

Ptot

Po
~
Tstg
R thSA

v

-0.3 to 6
Vss -0.3
VDD +0.3
250
50
125
-55 to 125
70

V
V
mW
mW
bC

°c
K/W

Operating range
In the operating range, the functions shown in the circuit description will be fulfilled.
Deviations from the electrical characteristics may be possible.
Supply voltage
Ambient temperature: SAE 81 C 52
SAB 81C52

Vs
Tamb
Tamb

14.5 to 5.5
-40 to 85 *)
0 to 70

1

~C
°C

0) Values for applications up to 110"C upon request

9-19

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Electrical Characteristics
The electrical characteristics include the guaranteed tolerance of the values which the Ie
stays withi,n for the specified operating range.
The typical characteristics are average values which can be expected from production.
Unless otherwise specified, the typical characteristics apply to Tamb and the specified
supply voltage.
DC characteristics
SAE 81 C 52:
SAB 81 C52:

Tamb
Tamb

= -40°C to +85 0C;}
= OOC to 700C;

Voo

= 4.5 V to

5.5 V,

Vss

Test conditions
Standby supply current
Supply current
Standby voltage for data retention
L input current (for each input)
Output leakage current

100

L input voltage
H input voltage
L output voltage
H output voltage
L input voltage CS1
H input voltage CS1

V IL

100

IOIK

V IH

V

min.

max.
1
500

f= 1 MHz

1
1

IJA
IJA
V
IJA
IJA

0.8

V

0.4

V
V
V
V

1.0

Voo
IlL

=0

VI = 0 to Voo
Vo = 0 to Voo
tristate

} except CS1

VOL

IOL

V OH

IOH

= 1 rnA
= 1 rnA

2.2
2.6

1

V IL

II:'H

\£0

-1

AC characteristics
SAE 81C52: T.
= -40°C to,+85°C*); }
mb
SAB 81C52·• a
=m
500C to
700C·
b,

i

Voo

ALE pulse width
ALE LOW to RD LOW
RD HIGH to ALE HIGH
ALE LOW to WR LOW
WR HIGH to ALE HIGH
Address setup before ALE
Address hold after ALE
WR or RD pulse width
Data setup before WR
Data hold after WR
Data hold after RD
Chip select (2, 3) before RD, WR
Chip select (2, 3) after RD, WR
Chip select 1 before ALE
Chip select 1 after RD, WR
Output delay time
Input capacitance against Vss (for each input)
0) Values for applications up to 110°C upon request

9·20

= 4.5 V to

5.5 V;
tLHLL
tLLRL
tRHLH
t LLWL
tWHLH
t AVLL
tLLAX
t WLWH
tOVWH
t WHOX

=• 0 V
max.
min.

Vss

100
50
30
50
30
25
20
250
100
30
90

t RHOX

tcs
tsc
tcsLH
tCSWH
t RLOV

C,

50
50
20
50
200
10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF

256 x 8 Bit Static CMOS RAM
NMOS-Compatible

SAB 81C52
SAE 81C52

Timing diagram

ALE

C52/C53

C51

9-21

256 x 8 Bit Static CMOS RAM

SAB 81C52
SAE 81C52

NMOS~ompatible

Application circuit
SAB 81 C 52 P with the !-IC SAB 8051
+5V
401
19

ri'PFJo1
P
L 1O

18

Vee
XTAL1

XTAL2

SAB

2011 .
Vss
Pl.0
Pl.1
Pl.2
Pl.3
P14
P1.5
Pl.6
8051
Pl.7

SAB 8751
+5V

_HI

9

l~~F
31

RE5ETIVpo

EAlVoo

~
-JJ,.

1I0{

P3.0 (RXD)
P3.1 (TXD)
P3.2 (INTO)
.-1l P33 (iNii)
~ P34 (TO)
.-!2. P3 S (T1)
16 P3.6 (WR)
~ P3.7 (RO)
ALE/PROG P5EN
30
129

-¥

r!-JrL
~

rL
~
JrL

21
P2.0
P2.1
P2.2
P2.3 ~
P2.4 ~
P2.5 ~
P2.6
P2.7

110

&

rD-

r?L
r?!-

PO.O
PO 1
PO 2
PO.3
PO 4
PO.S
PO 6
PO.7

• SV

)110

39
38
37
36
35
34
33
32

ADO
AD 1
AD2
AD 3
AD4
ADS
A06
AD7

m

GNO

I

I

Voo

Vss

SAB
81 (52 P
256 x 8 bits
RAM

RD
WR
ALE
+5V

Power
failure
logic

9-22

0.---

(S2
(51

"'L.r

The information describes the type of component
and shall not be considered as assured characteristics

SIEMENS

SAE 81C54
CMOS Static RAM
.512 x a-Bit Organization

• Two Chip Select

• Multiplexed Address and Data Bus

• Wide Supply Voltage Range: 2.5V to 6V

• Tri-State Address/Data Lines

• Data Retention 1.0V

• On-Chip Address Register

• Package: DIP 16, SO-20

• Very Low Power Consumption
Standby 1 J.LA at 6V

Pin Configuration

Pin Definitions

(Top View)
ADO 1

16 Vee

2

15 RD/

AD2 3

14 WR/

ADI

AD3 4

13 ALE

AD4 5

12 CS

AD5 6

11 A8

AD6 7

10 AD7

Vss 8

9

CS/

Pin

Symbol

Function

1-7,10
8
9
11
12
13
14
15
16

ADO-7

Address/Data Lines
Ground (OV)
Chip Select
Address Line
Chip Select
Address Latch Enable
Write Enable
Aead Enable
Power Supply (2.5V -6V)

Vss
CS/
A8
CS
ALE
WA/
AD/
Voo

0114-1

The SAE 81C54 is a 4096-bit static random access memory (AAM)organized as 512 words by 8 bits, manufactured using advanced CMOS technology. The multiplexed address and data bus allows direct interface with
8-bit organized processors and microcomputers, for example with SAB 8085, SAB 8086, SAB 8088,
SAB 8048, SAB OC48, SAB 8051 and SAB 80C482. Low standby power dissipation « 1 JlA) minimizes system
'
power requirements.

@Slemens Components, Inc.

9-23

May 1988

SAE 81C54

Block Diagram
A8

address

gated

2x32x64

latches

ROW

MATRIX

A3 "AS

decoder

DO

ID

. LRead-Log,k

DO

I

ADO AD7

ID

Wrote-Log,k

r--r---

•
gated
column decoder

•

I

C5I

~

ALE

~I

control

cs

logIC

RD/

I
address latches
AO,Al.A2

I

WRJ
0114-3

B<.

Truth Table for Control
and Data Bus Pin Status

Logic Symbol
CSi

C5
RDI

:L:
Aa

'5AE

81C54

Add".. I D...
Bus,
ab,lS

>

CSI CS RDI WRI

01104-2

H

X

X

L
H
H

L
L

X
X

X
X

L
H

H
L

AD O-AD 7 During
Data Portion
Function
of Cycle
Floating
No Function
No Function
Floating
Data from Memory
Read
Data to Memory
Write

Absolute Maximum Ratings·
Ambient Temperature
under Bias (TA) .............. - 40'C to
Storage Temperature (T51g) .•... - 55'C to

+ 11 O'C
+ 125'C

Supply Voltage with
Respect to GND (Vss) (V) ............. OV to 7V
Total Power Dissipation (PIot> ............. 250 mW
All Input and Output Voltage . - O.SV to Voo

9-24

+ O.SV

*Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

SAE 81C54

D.C. Characteristics TA = -40·Cto +85·C·;(Voo = 2.5Vt06V;Vss = OV)
Parameter

Symbol

Limits

Conditions
Min

Standby Supply Current

lee

Operating Supply Current

lee

Operating Supply Voltage

Vee

Standby Voltage

Vee

for Data Retention

Input Current

III

Output Leakage Current

IOL

L Input Voltage
(Vee < 4.5V)

VIL

L Input Voltage
(Vee> 4.5V)

VIL

H Input Voltage

VIH

H Input Voltage

VIH

Vee = 5V

L Output Voltage
(Vee < 4.5V)

VOL

IOL=1mA

L Output Voltage
(Vee> 4.5V)

VOL

IOL = 2mA

H Output Voltage
(Vee < 4.5V)

VOH

IOH = 1 mA

H Output Voltage
(Vee> 4.5V)

VOH

IOH = 2mA

Units

Typ

Max
1

100 kHz ALE

p.A

500

p.A

2.5

6

V

1.0

6

V

VI = OV to 6V

1

p.A

VO = OVt06V
High Impedance

1

p.A

-0.8

0.6

V

-0.8

0.8

V

0.6 X Vee

Vee + 0.8

V

2.0

Vee + 0.8

V

0.4

V

0.4

V

0.75 x Vee

v

0.75 x Vee

V

A.C. Characteristics T A = -40·C to + 85·C, Vee = 5V; Vss = OV
Parameter

Limits

Symbol
Min

ALE Pulse Width

tLL

Address Set-Up before ALE

Typ

Units
Max

60

ns

tAL

10

ns

Address Hold from ALE

tLA

45

ns

RD, WR Pulse Width

tec

150

Data Set-Up before WR

tew

100

Data Hold after WR

twe

25

Data Hold after RD

teR

0

RD to Data Out Access Time

tRe

Address Float to RD

-

ns
ns
ns
95

ns

150

ns

tAFC

0

ns

CS before ALE

tcs

30

ns

CS After WR or RD

tsc

30

ns

ALE to RD-WR control

tLC

100

ns

RD-WR Control to ALE High

tCL

30

ns
9-25

SAE 81C54

Timing Waveforms
Read
ALE

RDI

...
BUS

'Io.tlng

Dota

'"

eSI
es

0114-4

Write
ALE

WRI

BUS

.....,'"

'IOMIng

CSI
es
0114-5

Ordering Information
Type

Ordering Code

Package

5AE81C54P

Q 67100-H8486

DIP 16

5AE81C54G

Q 67100-H8487

50-20

9-26

SIEMENS

SAE 81 C80
Dual Port RAM
Preliminary Data
Type

Ordering Code

Package

SAE 81C80

Q67100-H8390

PLCC44

The SAE 81 C80 dual port RAM (DPR) is a CMOS memory IC with two processor interfaces and a capacity of 504 bytes. It enables the exchange of data between two processors
without handshake signals and without wait states. Eight scheduling registers support
the management of data areas or external resources.

Features
•
•
•
•
•
•
•
•
•
•
•
•

ACMOS technology
All functions fully static
SAB 8048/8051/80515 and 8096 compatible
Memory capacity 504 bytes and 8 scheduling registers
On-chip oscillator with separate clock output
3 loadable counters for processor monitoring or as longterm counters
Hardware watchdog
Both processors can operate fully asynchronously
Data retention down to 1V
TIL-, NMOS- and CMOS-compatible
Extended temperature range from -40°C to +85 °C
Package: PLCC 44

Edition 3.87

SMD - Surface Mounted Device

9-27

SAE 81C80

Pin Configuration

1 44

40

39

0

AD10
ADli
AD12
AD13
AD14
AD15
AD16
AD17
ALEl
WDl
WD2

29
18

RD2
A2B
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
ALE2

28

Pin Description
Pin

Symbol

6

AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
A18

37
36
35
34
33
32
31
30
38

AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
A28

7

8
9
10
11
12
13
14

9-28

Function

Data and address bus port 1

Address 8 port 1

Data and address bus port 2

Address 8 port 2

SAE 81 C80

Pin Description
Pin

Symbol

Function

15
29

ALE1
ALE2

Address latch enable port 1
Address latch enable port 2
These signals serve to separate data from addresses on the bus.
The address is stored on the falling edge of the signal.

5
39

RD1
RD2

Read signal port 1 (active low)
Read signal port 2 (active low)

4
40

WR1
WR2

Write signal port 1 (active low)
Write signal port 2 (active low)

3

CS1

Chip select port 1

2

CS1

Chip select port 1 (active low)

41

CS2

42

CS2

Chip select port 2
Chip select port 2 (active low)
The chip select inputs select a port when both inputs have
active level.

27

RES

Reset input
Resets the IC to a defined start state. Simultaneously, the outputs
WDO, WD1, WD2, WD3 are switched to low for the duration of the
reset pulse.
The oscillator is not affected.

28

PD

Power down.
Disables all inputs and the oscillator

44
1
43

Vss

19
20
21

XTAL1
XTAL2
CLKO

Negative supply voltage
Positive supply voltage
Connection for battery (negative pole, positive pole of the battery
must be connected to Voo )
,
Quartz 'connection (must be open for external clock supply)
Quartz connection or external clock supply
Clock output
'

22

WDO

Oscillator watchdog (open drain output)
High indicates that oscillator is in operation

16
17
18

WD1
WD2
WD3

(Open drain output)
(Open drain output)
(Open drain output)

26

TS3

Hardware signal to start timer B

23
.24

INT1
INT2

(Open drain output, active low)
(Open drain output, active low)

25

INT3

(Open drain output, active low)
Outputs that can be controlled via the port, for example,
to generate an interrupt at one of the processors.

Voo
VBATT

I

outputs of the 3 timers

'
9·29

SAE 81C80

Functional Description
Dual Port RAM
The dual port RAM has a capacity of 504 bytes, which can be accessed by both processors.
The memory locations are selected via a multiplexed address and data bus and two chip
select inputs. The RD and WR inputs define the direction of data transfer. During simultaneous
access to the same memory location, no undefined states occur, especially not in such
cases, when both processors write to the same memory location. Depending on the internal
status of the access control, and of the real physical sequence, the value of one of the
ports will be stored. Even during simultaneous reading of and writing to the same memory
location, there will be no mixing of data, Le. ~ither the old data or the new data will
be read.
Interrupt Outputs
The dual port RAM has three outputs that can be directly set and reset by writing to an
address (table 1). The interrupt outputs are located in the same address range as the
scheduling registers. However, only bit 2 and bit 3 are relevant for the interrupt outputs.
In order not to affect the scheduling registers, at least one of the bits 0 or 1 should
not be "0". The function of the outputs is shown in the diagram to follow.
RES

Bit 3

Bit 2

Output

1
1
1
1

0
0

0
1

no change
1

1
1

0

0

1

undefined
1

0

-

-

Reset
The reset is necessary to set the DPR control circuits into a defined start state. During
a reset, the timer mode registers are loaded with the value OOOOXXXOs (for timers 1 and 2),
or with OOOOOXXOs (for timer 3). The INT outputs are set to "1".
.
While the reset input is low, outputs WD1, WD2 and WD3 are set low. After the reset
pulse these outputs are high.
.
A reset is also necessary when the DPR is activated again from the pow~r down mode.
The contents of the RAM and the oscillator are not affected by the reset
.

9-30

SAE 81C80

Power Down
When the power down pin is activated. all inputs and the oscillator are disabled. so that
any levels are allowed at the remaining inputs.
Battery Connection
An external battery can be connected to pin VBATT• The negative pole connects to pin VBATT•
the positive pole to V~o. During failure of the normal supply voltage at Voo the RAM will
be automatically supplied from the battery so that the RAM contents are saved. All other
information is lost If no battery is used. VBATT must be connected to Voo.
Scheduling Register
Special circuits within the dual port RAM prevent a mixing of data from the two ports.
With continuous data over several bytes. it is possible that old and new data is read
at one port if the other port writes to the same memory region at the same time. In order
to avoid this conflict. the dual port RAM has 8 scheduling registers. Any of these registers
can be used by a processor to indicate that it is accessing a data region assigned to
this register. In order to make the operation with these registers as simple as possible.
they have special features:

They are 2 bit registers (bit 0. bit 1 of the byte). Bit 0 indicates who "owns" the register
and bit 1 indicates that it is occupied. The appropriate bits are already set during reading
of these registers. and the processor receives the correct values (fig. 1). Reset is achieved
by writing the value "XXXXXX11 .If a read access is attempted from both ports simultaneously.
port 1 is given priority and port 2 receives the corresponding message.
The assignment of the scheduling registers to a location in the RAM is done by software.
This means. the user is completely flexible in the assignment of the registers. It is. for
example. also possible to use these registers as access management for external resources.

a

s·

The addresses of the scheduling registers are listed in table 1. The unused six bits
will read all "0".

•
9-31

SAE 81 C80

Status Diagram of the Scheduling Registers

Occupied = 1
Free = 0

Owner = 1
Not Owner =0

Port 1 Reads "01"
Port 1 Writes" QO,"

Port 2 Reads" 01"
Port 2'Writes "00"

Notes:
1) The owner bit shows who accessed the register last.
21 During simultaneous access. port '1 has priori ty
3) A write is only possible If the respective port IS "owner" of the register.

Figure 1

9·32

SAE 81 C80

Oscillator Watchdog
This output provides a means to control the oscillator circuit and the crystal.
Whenever the clock frequency drops below a threshold of approx. 100 kHz, this output
switches to low.
Timer

The three timers are 24-bit counters with a clock frequency of feLK/6. Each of the counters
can be set by writing to 3 specific RAM addresses. The value is simultaneously stored
in the RAM and in a buffer register of the timer. When writing to the low byte, all three bytes
are transferred to the reload register. The value in the reload register is maintained in
all modes until the corresponding low byte is written again. The counters are down counters.
The counters can be started by setting bit 7 in the corresponding TMR. Additionally,
counter 3 can be started by an external trigger signal Crs 3). Each counter can be
configured by a timer mode register (TMR). The meaning of the bits of the TMR is described
below.
Bit 0:

Bit

4:

Bit 5:

Protects the reload register against overwriting.
Application: After writing to the reload register, the parallel RAM region can be
used after the timer is started - by writing to the corresponding protection bit without influencing the reload register (reset state = 0).
Serves to switch output signal polarity (reset state = 0)
Bit 4 = 0; idle state 1, active 0
Bit 4 = 1 ; idle state 0, active 1
Selects the mode (reset state = 0):
Bit 5 = 0 single shot, i.e. when the counter is started, the output signal goes
active. After zero is reached, the output signal returns to idle. To genera,e
another count period, the timer must be started again. During this, the values
from the reload register are loaded into the counter.
Bit 5 = 1 auto-reload, i.e. the value of the reload register is loaded into the
counter when the counter is started. When reaching zero, the counter outputs
a pulse (-4 J.1s) and reloads the old value automatically, starting the process
again, so that a frequency can be adjusted with a 24-bit resolution. If a new
start pulse occurs during the counting period (even without "STOP"), no pulse
is output and the counter is reloaded.

Bit 6:

In the reload mode the timer can be stopped by setting this bit. .(During a new
start the contents of the counter are-lost, but not the contents of the reload register).

Bit 7:

Setting this bit starts the counter.

Only for Timer 1 and 2

Bit 1- 3:

In conjunction with bit 0 serve to switch the watchdog mode on or off.

Only for Timer 3

Bit 1-2:

Reserved (must always be 0 for proper operation)

Bit 3:

Switches all 3 timers to test mode, i. e. only the upper 12 bits are used to
generate the output signal. (Reset state = 0).

9-33

~
~

SAE 81C80

Watchdog Mode

A special mode is provided for timers l' and 2, which can be used to monitor the two
processors that are connected. For this mode, an additional register (address see table 1)
- referred to as control register (CR) in the following - is used per timer. Watchdog mode
is enabled by loading the TMR with the value "101X1111 B", bit 4 being used to freely
select the polarity of the output signal. This mode operates in a similar manner as the
auto-reload mode, except that in this case, neither the contents of the reload register
nor the TMR can be changed.
In the watchdog mode the timer can only be restarted (and thus suppressing the output
pulse) when first 055 H and then OAAH is written into the control register: There is no time
limit between these two write accesses, however no other value must be written into the
timer mode register nor into the control register between these two operations, otherwise
the sequence must be started again.
In order to reset the timer into the normal mode, the following sequence must be performed.
First the value 055 H must be written into the control register, then the value 011 XOOOO B
into the TMR, and finally the value OAAH into the control register. The same condition
applies for this sequence; if any other value is written into one of the two registers, the
total operation must be started over again. There is no time limit between the accesses.
The appendix shows the operation of the timer in watchdog mode as an example program
for the 8051.

Figure 2: Bit ~ssignment of the Timer Mode Registers for Timer 1 and Timer 2

Bit 7

Bit 6

Bit 5

Bit 4

Software
start (-1)

Timer
stop (=1)
for
auto-reload

Polarity of
Mode
(auto-reload the output
-1
pulse
single shot ~high=O)
-0)

Bit 3

Bit 2

Bit 1

Bit 0

Onlyfor .
watchdog
mode
(normal
mode-Oj

Only for
watchdog
mode
(normal
mode-Oj

Only for
watchdog
mode
(normal
mode-Oj

Protection (-1)
write
protects the
reload
register

Figure 3: Bit Assignment of the Timer ~ode Register for Timer 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Software
start (-1)

Timer
stop (-1)
for
auto-reload

Mode
(auto-reload
=1
single shot
-0)

Polarity of
the output
pulse
(high-O)

Test (-1)
switches
timer into
test mode

Reserved
(normal
mode-Oj

Reserved
(normal
mode-Oj

Protection (-1)
write
protects the
reload
register

9-34

SAE 81 C80

Address Assignment of the DPR Registers (Preliminary)

Register
Scheduling
Scheduling
Scheduling
Scheduling
Scheduling
Scheduling
Scheduling
Scheduling

Address
register
register
register
register
register
register
register
register

1
2
3
4
5
6
7
8

1F8H
1F9H
1FAH
1FBH
1FCH
1FDH
1FEH
1FFH

Timer mode register
Timer mode register
Timer mode register

1
2
3

1EOH
1E4H
1E8H

High byte timer
Medium byte timer
Low byte timer

1
1
1

1E3H
1E2H
1E1H

High byte timer
Medium byte timer
Low byte timer

2
2
2

1E7H
1E6H
1E5H

High byte timer
Medium byte timer
Low byte timer

3
3
3

1EBH
1EAH
1E9H

Control register timer
Control register timer

1
2

1ECH
1EDH

Interrupt output
Interrupt output
Interrupt output

1
2
3

1F8H
1F9H
1FAH

•

Table 1

9-35

~

IJJ

0'

m

n

'tfI/:'

C

ir

CO

Q;

·3

A 18

'---

A010 .A017

~

ALE 1

rV

I--

WR1
CS 1

f-f-f--

Interface
Port 1

I--

r-r--

Bus
Interfac-e
Port 2

~

I-i-io4-

~

Voo
Vss
VBATT

f-l;L

1'r

f-- Bus

RO 1

m

RAM
S04xB Bit

Battery
Switch

Timer

.

r-7

Status
Register

TS 3 WO 1 WO 2 WO 3 INT 1 INT 2 INT 3

A2B
A020 .. AD27
ALE 2
RO 2
WR Z
(S 2
CS 2

,
Access
Control

PO

RES

I-

Oscillator t-With Monitor
Circuit
t--

WOO

XTAL1
XTAL 2

(lK 0

~

~

o

C»

o

SAE 81 C80

Maximum Ratings
TA = -40 to +85 °C

min.
Supply voltage
Input voltage

Voo
VA

Power dissipation per output
Total power dissipation

Po
Ptot

Storage temperature

Tstg

-50

Voo

4.5

typo

-0.3
-0.3

max.

Unit

6
Voo +0.3

V
V

50
500

mW
mW

125

°C

5.5
20

V
mA

12
+85
1

MHz

Operating Range
Supply voltage
Supply current
(without output loading)
Operating frequency
Ambient temperature
Standby current
Data retention voltage
Battery voltage
(referred to Voo)
(with sufficiently low internal
impedance)

100

fs

TA

-40

l oo .lsATT

VOA
VSATT

1
-1

5

-3

°C
!-LA
V
V

Maximum Ratings
Maximum ratings are absolute ratings. Exceeding even one of them may result in the destruction
of the integrated circuit. All voltages refer to Vss.
Operating Range

Within the operating range the functions mentioned in the circuit description will be fulfilled. Deviations
from the characteristics are possible. All voltages refer to Vss.

9-37

SAE81C80

Characteristics

TA -25°C
min.

max.

Unit

ViH
Vil
CI
II

2.2
0

Vee
0.8
10
1

V
V
pF
J.LA

VOH

2.4

Vee

V

Val

Vss

0.4

V

Val

Vss

0.4

V

H output voltage
IOH-0.5 mA
L output voltage
IOl -1.6 mA

VOH

2.4

Vee

V

Val

Vss

0.4

V

Load capacitance

Cl

80

pF

All input signals
H input voltage
L input voltage
Input capacitance
Input current

Output signals
A010-17, A020-27
H output voltage
10 -0.5 mA
L output voltage
10 -1.6 mA

Output signals
W01, ~, W03, WOO
(Open-drain outputs)
L output voltages
10 -1.6 mA
Output signal CLKO

DC Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics will apply at TA - 25°C and mean supply voltage. All voltages refer to Vss.
9-38

SAE 81C80

AC Characteristics
TA

=25°C
min.

max.

Unit

ALE pulse width
Address setup to ALE low
Address hold time after ALE low

tLHLL
t AVLL
tLLAX

60
30
40

ns
ns
ns

AD pulse width
WA pulse width

tRLRH
tWLWH

2 Tosc +20
2 Tosc+20

ns
ns

ALE low to AD or WA active
AD active valid data out
(chip select active)

t LLWL
tRLOV

60

Data hold after AD inactive
ALE low to valid data out

tRHOX
tLLOV

Valid data in after WA low
WA low to ALE high

tOVWL
tWLLL

1/2 Tosc
3 Tosc

Data setup before WA high
Data hold after WA high

tQVWH
tWHQX

30
40

Delay AD low to both chip
selects active
Delay WA low to both
chip selects active

tRLCH

40

ns

t WLCH

40

ns

2 Tosc

ns
ns

30
3 Tosc +20

ns
ns

2 Tos c ·)

ns
ns
ns
ns

Chip-select setup to AD
Chip-select setup to WA

tCLRL
tCLWL

0
0

ns
ns

Active pulse width of timer outputs
Pulse width TS 3

tACT
tTHTL

48 Tosc
2 Tosc

ns
ns

Oscillator pulse width
High time
Low time

tosc
tOSCH
tOSCL

83
25
25

ns
ns
ns

Aise time
Fall time

tr
t,

40
40

ns
ns

The AC characteristics apply throughout the operating range.
oJ Only applies If the WR signal Is longer than 2 Tosc.
Changes of the data bus Signals after this time will have no effect

·9-39

•

SAE 81C80

Pulse Diagrams

Read Cycle

ALE

ADXO-ADX 7
AX

e

AS

'Write Cycle

ALE
CSi\~LS

tOVWL t:=taVwti
ADX O-ADX 7

Axe

·9·40

==>--<_____
A7-AO

~

...J

AS
(~______
- J)

~"~~

Dato

<==

SAE 81 C80

Pulse Diagram

Oscillator
..

~

~

I

Timer
Single Shot Mode (TMR= "8~H'" High Byte=Medium Byte = "OOH",
Low B)te= "02H")
Timer Clock

=rl=
"THTL

rimer Start
(TS 3)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Auto Reload Mode (TMR = '60H", High Byte =Med,um Byte = "OOH ",
Low 3yt€="OSu")

Timer Clock
Timer Start ..J\~

_________________
>-------'A[T ---

Timer Out

--------~\
I

-----I

~
I

~---

9-41

:'2.

~
vS5 PtO I - -

Voo
XTAl1

4 "1
5

SAB 80S1

TSPFT

XTAL2
30llF
+SV

RI'

1

RpcetlVpo

111

I

+SV

+SV

EAlVoo

-

P 3.0IRXDI
P 3.1(TXDI
- P 3.2 IiNfO I
P 3.3(1NT 11
- P 3.4ITOI
- P 3.5(T11
.--- P3.6(WRI
,-- P 3.7(RDI
P5EN

+SV

Pt1 t-P1.2 t-P1.3 I-P1.4 I-PtS I-P1.6 ~
P1.7 I - -

l~

.--~

==
VBATT

Voo Vss X2

AD1C
AD 11
AD12
ADn
AD14
AD15
AD16 SAE 81 (80
AD 17 504 x 8 Bit

P2.0
P2.1
P2.2 t-P2.3 ~
P2.4 ~
P2.S ~
P2.6 r-P2.7 r-ALE

A18

m

I~

Xl

eLK 0
AD 20
AD 21
AD 22
AD23
AD24
AD2S
AD 26
AD27
A28
[52

ALE 2

WRi

RD2 f - -

[51

ALE1
WR2 I-W02WDOWD1 RE5 PO

Vss
P1 0 I-P1.1 I-P1.2 I-P1 3 I - 80S1 P1.4 I-Pl.S I-Pl.6 ~
Pl.7 I--

XTAL2
PO.O
PO,1
PO 2
PO.l
PO.4

ResetlVpo

Q

~

::;:

~~F
IU

+SV

EAlVoo

po.s

-

[52 I--.SV _

r - - RD1

VO!!
XTALI

SAB

T Hm-

PO.O
PO.1
PO.2
PO.3
PO.4
PO.S
PO.6
PO.7

r--

-

'-

-

~

PO.6
PO.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.S
P2.6
P2.7
ALE

P3.0 IRXDJ I-P3 11TXDI I-P3.2 (lNTOI I-P3.3IINT11
P 3.4(T01 ~
P3.S(T11 ~
PMIWRI
P3 7 (Rill f----

P5EN

I

I'
I

IJ
+SV

=
m

Reset

+SV

~

n

!

SAE 81C80

8051 - Program for Timer Operation in Watchdog Mode

HBYTE
TMR
KR
REST1
REST2
WDAUS

EQU
EQU
EQU
EQU
EQU
EQU

1E3H
1EOH
1ECH
055H
OAAH
060H

: Address high byte reload register
: Address timer mode register
: Address control register
: 1 value to restart timer
: 2 value to restart timer
: Value to switch off watchdog mode

: Load reload register
MOV
CLR
MOVX
DEC
MOV
MOVX
DEC
MOVX

DPTR, # HBYTE
A
@DPTR,A
DPL
A,#OFFH
@DPTR,A
DPL
@DPTR,A

: Switch on watchdog mode and start timer
MOV
DEC
MOVX

A,#OAFH
DPL
@DPTR,A

: Reset timer
MOV
MOV
MOVX
MOV
MOVX

DPTR,#KR
A,#REST1
@DPTR,A
A,#REST2
@DPTR,A

•

: Switch off watchdog mode and stop timer
MOV
MOV
MOVX
MOV
MOV
MOVX
MOV
MOV
MOVX

DPTR,#KR
A,#REST1
@DPTR,A
A,#WDAUS
DPTR,#TMR
@DPTR,A
A,#REST2
DPTR,# KR
@DPTR,A

END

9-43

SIEMENS

SDA 2208-2
IR Remote Control
Transmitter with IR Diode Driver
The SDA 2208 is designed as a remote control transmitter for direct driving of infrared
transmitter diodes. The instructions are generated by an input matrix (i.e. keyboard) in the
form of biphase codes. Distributed over 8 levels, there are a max. of 512 instructions available.

Maximum ratings
Supply voltage range
Matrix rows
Matrix cQlumns
Programming pin (PPIN)
Oscillator input (ClKI)
Infrared output (IRA)

Vs
Vrow
Veol
Vpp
"'osc

inhlbi~ed

-0.3 to 10.5
-0.3 to Us
-0.3 to Us
-0.3 to Us
-0.3 to 2

V
V
V
V
V
V
V
DC
DC

in operation
Junctio~ temperature
Storage temperature range

1j

rstg

-0.3 to 10.5
-0.3 to 8
150
-40 to 125

Thermal resistance
(system-air)

R'hSA

60

KlW

4 to 10

V
DC
kHz

Vq
Vq

Operating range
Supply voltage
Ambient temperature
Oscillator frequency

o to 70

430 to 530

Characteristics
Vs =7 V; TA =25°C
min
Current consumption·)
transmitting' phase
stalldby mode
Output clJrrent IRA
2 V0

.:;.
(,)

..H
n27h1'l"

T3

-/2

2.2}1F

~

15V

l

100kll
100nF

H

V4

g-I
~

0
0

U'I

Dr

j

5'~

~

n'U
:-'U

"""--J:

r

.-=
ng

2.2kQ

--Ic:::J
10pF Signal input

I

at

~ 1pF\
7i

5'

[J:

0

en _.
-n
(1) a
-c

T 10PF 5 r--

6

g:

-g~

+ Vs

~;:;:

6-::l

33kQ
56kQ

1.5nF

6V

~il'\BP104

I
I

1OOmH~:
I

"

!~I~kQ

~

. Irb L

I

T

.::b. 2.ZpF

I-t

1.akQ

kQ

10kQ

2

3.3nF

3

33kQ

1.5nF

4

-t

~

.Signal output

~
~

m

TDA4050B

Application circuit II
without coil
1.5kQ
~----------------·r---~~~=r~~--~--~+Vs

82kQ

3.9kQ
3.3nF

BAW76

J--4
I

3.9k~

T::
.
E
1.5nF

I

I

I
I

I

R-D-R

Notes
Circuit I uses an LC resonant circuit and is of superior quality due to its high selectivity
feature (approx. 3 kHz bandwidth at -3 dB).
Circuit 2 offers the lower cost solution without coil incl. broadband input selection. Higher
requirements as to steady radiation and large signal stability can be met by means of
resistor-diode-resistor connection (RDR).

9-75

SIEMENS

TDA 4060/TDE 4060/TDE 4060 G

Infrared Signal Receiver
• Simplified Bandpass Circuitry without
External Inductance

• Only 5V Supply Voltage
• Supply Current Max. 0.6 mA

• Extended Temperature Range
-40°C to + 110°C (TOE 4060)

• DIP 8 or SO 8 Package

Pin Configuration

Pin Description
Pin Function for Package DIP 8

Output

8

RC1

RO

Cs

1

6

5

0
1

2

3

G~d

CfOII

Vs

4
Input
Infra
0075-5

Pin

Function

1
2
3
4
S
6
7
8

Ground
Creg
Vs
Input Infra
Cs
RC2
RC1
Output

The digital signals transmitted to an infrared receiving diode must be amplified. The application range of the
TDA 4060 designed for this purpose covers the entire area of infrared signal transmission. The IC is therefore
especially suitable for use in radio, TV, video as well as automobile electronics.
Through the application of a high-speed bipolar circuitry, high frequencies are processed at low curent consumption. The number of external components used with older versions has also been reduced.

Block Diagram

yS
0,utput

low-noise
r.re-amClifier
(ontro ler)

Input
Infra

r+-r

bandpass

f--

driver \

I

C...

-

11

drain

-

TOA 4060

-

'--

I
A

Ground

!

C,

RCZ

RCI

0075-4

@Siemens Components, Inc.

9-76

May 1988

TDA 4060/TDE 4060/TDE 4060 G

Description of Functions and
Applications
Dimension and Structure
The IC can be used in all infrared systems. Depending on the chosen carrier frequency, several optimal
applications are possible.

trol. The time constant is determined by Crego If a
biphase code is used (i.e. TV sets), we recommend
to have 470 nF. If signal codes, which do not have
any presignals for regulation, are used, Creg can be
decreased to 10 nF. It may happen that the IC oscillates if low capacitances are used.
Double-T-Element at RC1 and RC2
The double-T-Filter solution has proven to be the
best one. The junction frequency is calculated according to the formula

Infrared Receiver Diode
This diode, together with the cathode, leads, for example, to the supply voltage of the IC. This means
that any interference of this line is delivered to the
input infra by the junction capacitance of the diode.
Therefore, we recommend to put an RC low pass
between the plus supply and the cathode of the diode.

0075-2

+5V

oo75-t

Input Infra
This input is high-impedance and requires only nanoampere driving currents. Therefore, we recommend to put the anode of the IR diode directly at the
input.
Capacitance Cs
This capacitance Cs causes the preamplifier to become an RC-high pass filter; moreover, it also works
in connection with Creg and the double T-element.
The transient response in particular is influenced by
the application used. When working with standard IR
systems the following values should be observed:
Carrier Frequency Approx. 30 KHz: Cs = 100 nF
Carrier Frequency Approx. 120 KHz: Cs = 10 nF
Capacitance Creg
It is possible to control the gain of the preamplifier:
the higher the IF input signal the higher the gain con-

The junction frequency has to be identical with the
carrier frequency of the IR signal. This can be obtained by different combinations of R + C. The maximum value for R should not exceed 100 kn; otherwise the voltage drop at the DC current path circuit
would be too large. If an oscillation occurs, it may be
reduced by a lower resistance R for amplifying the
circuit.
Output
The output is an open collector. If the transistor is
conducted, the maximum collector current is 1 mA.
We recommend to keep the collector current as
small as possible since it may happen that the circuitry oscillates due to a direct feedback of the input
and output. If the collector current does not exceed
200 p.A, it is very unlikely that the circuitry oscillates-even in case of a poor p.c. board layout.
In General
The pin connection has been chosen because it
keeps a crosstalk, which may occur between critical
pins, as small as possible. This fact should be taken
into consideration of when any layout is developed.
Perhaps the supply voltage has to be blocked with a
capacitance, primarily due to the current deviation,
which is generated by the output.

9-77

TOA 4060/TOE 4060/TDE 4060 G

Application Circuit
Application Example
TV remote control with mit biphase code.
Carrier frequency approx. 30 KHz; output signal non-demodulated.
5V
....-_-L""l4

I"fr.rot·
rece,verdiod.

41k

Us

Output

TDA4060

410"

RCI

RC2
R
2C

C

0075-3

Measurement Circuit
The infrared diode receives the signal as well as the
infrared spectrum of emitted daylight, the 100 Hz
line noise of light bulbs and portions from the spectrum of fluorescent lights.
The current sink, shown in the block diagram, drains
the unwanted low frequency diode currents and, at
the same time, stabilizes the operating point at the
input of the low-noise preamplifiers to approximately
1.4V.
In the low-noise preamplifier the signal is sufficiently
amplified to provide the bandpass filter with a suitable amplitude. The gain of the low-noise preamplifier is regulated in accordance with the input amplitude. When the Signal amplitude is larger than the
interference amplitude (e.g. of fluorescent light), this

9-78

type of gain control prevents that the interference
amplitu'de alone overdrives the amplifier and the
useful signal is "swallowed". It is therefore possible
(with limited sensitivity) to evaluate distorted signals'
as well.
The bandpass filter improves the signal-to-noise ratio of the signal. The edge jitter of the output Signal
is therefore reduced. The external RC combination
should include band trap characteristics and a DC
current path. The cut-off frequency of the external
RC combination is identical with the carrier frequency of the useful signal.
The driver includes an open collector output. The
output is in high without an input signal.
The modulated signals will not be demodulated at
the output.
'

TOA 4060/TOE 4060/TOE 4060 G

Absolute Maximum Ratings·
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings cannot be exceeded without causing iffeversible damage to the integrated circuit
Position
1

Parameter
Maximum Rating for T A = 2S'C

Symbol

LImits

Conditions

Units

Min

Max

-0.3

7

V

Supply Voltage

Vs

2

Input Infra

Iinfra

10

mA

3

Cs. Creg

ICs,Creg

10

mA

4

RC1. RC2

VRC1, RC2

-0.3

Us

V

5

Output

Va

-0.3

7

V

6

Thermal Resistance

DIP8

RthSU

System·Casing
7

S08

Storage Temperature

3

mA

100

K/W

200

K/W

+125

'C

0

la

-40

Ts

Range of Functions
Within the functional range. the integrated circuit operates as described; deviations from the characteristic
data are possible.
Position

Parameter

Symbol

1

Supply Voltage

Us

2

Current Sink
Input Infra

ISink

3

Input Voltage

Vlnfra

4

Frequency Range
(for Modulation)

5

Ambient Temperature

TA

Limits

Conditions

Units

Min

Max

-4.0

6.5

V

0

2.0

mA

0.6

600

mVeff

20

200

KHz

TDA4060

0

+70

'C

TDE4060

-40

+110

·C

ZiGen

< 100n

9·79

'fDA 4060/TDE 4060/TDE 4060 G

Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit Typical characteristics
specify mean values eXpected over the production spread If not stated otherwise, typical characteristics will
apply at TA = 2S'C and the listed supply Voltage.

Position

Parameter

Symbol

Condl,ions

Supply Voltage
Ambient Temperature

Test
Circuit

Limits
Min

Typ

Units
Max

Vs= SV
TA = +2S'C

1

Current Consumption

Is

2

Input Sensitivity by
Assured Signal
at the Output

I'nfra

600
Diode DC Current
IOiode < 1 ,.,.A
IOiode < 10,.,.A

,.,.A

1.3

nAss

3.4

nAss

6.0.

nAss

IOiode < 100,.,.A

12

nAss

IOiode < 1000,.,.A

15

nAss

IOiode < 30 ,.,.A

3

Output Current
(Output High)

10

0< Va < 7V

4

Output Current
(Output Low)

Ua

0-

'fL~L

11

3

4

5

~t :l.L

8

~L .L~

9-89

UAA170

Scale display with light emitting diodes
Scale displays by means of a wandering light spot are particularly suitable for indicating
approximate values. Applications of this kind are level sensors, VU-meters, tachometers,
radio ,scales etc. When applying the displays in measuring equipment, multicolored light
emitting diodes can be used as range limitation. Ring scales are obtained by a circular
arrangement of the diodes. The IC UAA 170 has especially been developed for driving a
scale,of 16 LEOs.
The input voltages at pins 11, 12 and 13 are freely selectable between 0 and 6 V. Any kind
of adjustment becomes possible by suitable voltage drivers. The OC value Vcontrol is always
assigned to a certain spot of the diode chain.
The voltage difference between pins 12 and 13 thereby corresponds to the possible indication
range. LlV12/13 defines at the same time the light transition between two diodes. With
LlV12/1~ approx. 1.4 V, the light point glides smoothly along the scale. With increasing voltage
difference, the passage becomes more abrupt. With LlV12/13 approx. 4 V, the light point
jumps from diode to diode.
Input voltages beyond the selected indication range cause the diodes 01 or 016 respectively, to light up, Identifying only that the range has been exceeded.
'

Block diagram
V,

Vstab

15

14

Vref max

13

Vref min

12

\'cantral

Vs

11

10

9

6

7

8

Matrix

1

Ground
9·90

2

3

5

UAA170

Indication for smooth transition UAA 170

III

I·

016
015
014
013
012

1.4V ---

j

--

I

SOIl
:: 010
~ 0 9

I

II

-0-

~OB

o7

o6
o5

------

o4
o3
o2

o1

~~--------~------+--------+---------V...fmQx = v.:ontrol max
Veontrol

Indication for abrupt transition UAA 170
4.0V

gl~l
014

>----..0..0-

013

1/1

000-

012

..0-

SOll

-0-

-' 010
'50 9
~ 0B
07

..0..0-

... ~
-0-

o6

..0-

OS

..0-

04
03
02

..0..0-

01 - - -

--

-

f--

J)

V,.fmln = v.:ontrol min

~ontrol

V,.fmQx= ~ontrol max

9-91

UAA170

Brightness control
BP101II/R/m

Photo transistor
or resistor
as required

'"

10k12

16

UAA 170

Pins 14, 15, and 16 serve to detennine the diode current. Corresponding to the desired
light intenSity, the forward current of the diodes is linearly variable in the range I, approx.
o to 50 mAo The resistance at pin 15 defines the adjusting range. The resistances between
pin 14 and 16 determine the current.
With the aid of a phototransistor, such as BP 101, the light intensity of the LEOs can be
adjusted to the light fluctuations of the environment.

DIode current versus base emitter resistance
Vs = 12 V; T"mb - 25 DC; V14 "" 5.4 V; red LEOs
rnA

50.--.---.---.--.---.----.--.---.---.--.

10

o

01020

9-92

301,0506070
-Ra

UAA170

Operation of less than 16 LEOs
Control of 9 LEOs

161

I

I

I

P
461

~L

I

f9

I

UAA 170

I LB

L

11
9"LD

I

,.+. . r

rrr

.l~L

~l~L~

.l

i>
+V

Control of 11 LEOs
161

1

1

~

1

1

r9

1

1

I

La

UAA 170

I

11
;-

r

~rft -<0-<

11"LD 461 ~

0-

.L~L ~Lf:.
0-

' - - - -<

if:. 3"SA 127
,Ll:>

9·93

UAA170

Application circuit for the control of 30 LEDs with 2 x UAA 170
Range of control voltage v.,ontrol -= 0 to 5 V '
Voltage difference V,2113 = 2 x 1.2 V'" 2.4 V
Since the diodes 016 or 017 are permanently lit when the maximum or minimum voltages
V,3 or V,2 adjusted by R3, R4, R5 , are exceeded or fall short the diodes should be covered,
if necessary.
V,ontrol

lOki!

56kD

UkSl

22kD

22kD

, 1
Ikl!

16

15

14

P

13

11

12

10

~

1
-r03Z
L0461

[o~

2

}

4

~l

........ r-

5

r[o~

~,

L

R,
56k1!
,JslkD )~1

lkl!

L

15

P

UAA 170
6

Q

L8

['~ t"l 017

~

-r'

016

13

12

11

10

5

6

L

£"

UAA 170
2

]

~:

......... r-

1

~r-~

Vs
.12V

~

1
'-116
L

o to.5V

!""

h

I

4

[o~

r-

~

8

~r->-

[o,['~ .. ,,01

~

The figure shows an expansion of the circuit to 30 diodes with 2 ICs UAA 170. The diodes
016 or 017 light permanently, when the reCiprocal absolute ratings are exceeded. They
should be covered. The reference voltage AV,2113 '" 2 x 1.2 = 2.4 V is derived from a stabilized
dc voltage of typo 5 V available at pin 14. A resistance of 6.2 kG provides an overlapping of
the ranges in order to ensure a smooth transition from 015 to 01B.The control voltage Vcontrol
is forwarded in a parallel mode to pins 11 via a divider R, : R2.The voltage divider is to be
dimensioned according to the desired input voltage. With ,a divider current of I ... 100 J.lA
and a control voltage of Vcontrol = 10 V, the following is valid:
.

L1 V,2113
R2 -- I
R, =

Vcontrol -

I

2.4 -- 24 k n~" an d
0.1

... -

.111,2113

=

7.6 ... 76 kG
0.1
,

The nearest standard value is R, ... 75 kG. The voltage difference for switching an incremental
step is then .1 Vcontrol =

9-94

10 V
30 ... 0.16 V.

SIEMENS

UAA 180
LED Driver for Light Band Displays
Integrated circuit for driving 12 light emitting diodes. Corresponding to the input voltage the
LEOs forming a light band are controlled similar to a thermometer scale.
By using an appropriate circuitry the brightness of the LEOs can be varied and the light
passage between two adjacent LEOs can be arranged between "smooth" and "abrupt".

Maximum ratings
Supply voltage
Input voltage

Vs
Va
V16
V17

Storage temperature range
Junction temperature

Tstg

Tj

-40 to 125
150

V
V
V
V
°C
°C

Thermal resistance (system-air)

RthSA

78

K/W

18

6
6
6

Operating range
Supply·voltage range
Ambient temperature range

Vs
Tamb

9-95

11ot018
-25 to 85

1

~C

UAA180

Characteristics (VS "'12 V. Tamb '" 25°C)
typ

max

118

5.5

8.2

13
116
117

0.3
0.3
0.3

min
Current consumption (12 - 0)
(without LED current)
Input currents
(V3-V16 < 2 V)
Voltage difference for
smooth light transition
Voltage difference for
abrupt light transition
Diode current per diode
Tolerance of LED forward voltages

I'A
I'A
I'A
V

V16/3 ·

4

V16/3

10

V
mA
V

10

.I1 Vo

Measurement circuit
+12V

12>cLD 461

1".- .".... ...." "v 1" "

T

18

...

""

II'""

10

I"

10

k~ ~R5

100
kQ

Il1MQ P

UAA 180
1

I
1kQ

....f."'"

V,OOkQ

P,
Pz

9-96

light band test
brightness test

mA

~

\

""

.......

....

UAA 180

Scale display with light emitting diodes

Scale displays by means of a growing light band are particularly suitable for the measuring
of approximate values. Applications of this kind are level sensors, VU meters, tachometers,
field strength indicators etc. When applying the displays in measuring equipment, multicolored LEDs can be used as range limitation.
The voltage difference between pins 16 and 3 thereby corresponds to the possible indication range. L1V16/3 defines at the same time the light passage between two diodes. With
L1V16/3 ~ 1 V, the light band glides smoothly along the scale. With increasing voltage difference,
the passage becomes more abrupt. With L1V16/3 approx. 4 V, the light band jumps from diode
to diode.
Each quartet must consist of identical diodes in order to maintain its functional characteristics.
It is therefore possible to design the first and third quartet as diodes emitting the color
red and the second quartet as diodes emitting the color green to delineate a certain
operational area.
'
Pin 2 serves to determine the diode current. Corresponding to the desired light intensity,
the forward current of the diodes is variably linear in the range If approx. 0 to 10 mA.
Application circuit 1 shows the possibility of designing this resistance, adjustable by means
of a phototransistor BP 101, in order to adapt the light intensity to changing ambient
brightness. The adjusting range of the diode current lies between If approx. 5 mA (BP 101
not lit) and If approx. 10 mA (BP 101 fully lit). If pin 2 is open the diode current is 10 mA.

Block diagram
15

14

6

13

5

I
I

!
I-

I

LE D driver uni t

I
I

4

I

.

L ___ ... __ _

I

Supply unlf
2

......-·-+--+-~18

+ Vs

1~

Veonlrol- 17

3 V reI

R
Vrelmln

16

R

I

R

1 st row

2nd row

3 rd row

9-97

mo'

UAA180

Application circuit 1
Vret min + Vs

Veontrol

//

... ....... .." .......
....

18

~

R

17

16

)1MQ P

15 14 13

2xLD 466

" "... .......

r
12

11

10

7

8

L

.." r....

..

".... "

//
....

UAA 180

BP 101 I
1
.'

2

3

4

5

6

OR

.. ..

+ Vref max

Depending on the actual maximum ratings, the resistances R1 to R7 can be varied widely
as follows:
R3 ==S20 0
R4== 56 kO
R5 = 220 kO
R6 == 2.2 kO ... 100 kO

If a quartet does not need the full number of ·display diodes and if the first wired diodes
'shall be left luminous at full driving, bridges have to be inserted replacing the missing LEOs.
Otherwise the first diodes of the quartet switch off when their display range is exceeded.

9-98

UAA180

Application circuit 2
for cascading several UAA 180 ICs (up to 7)
l~

>

'"+

l.l.

X

'"

e

L~

L=-

I

0-

I

~.l

I
..-

l.l.

[

[

<{
<{

:::>

~:\

~~

T~

0
00

I

52

I

I

~

L:\
L.l.
L~

'---

['

L~
~.l

~

l:\

l~

I

0-

J

l~

.....

T~
)

[

<{
<{

L~

:::>

~~

L=---.,

I
0
00

I

52

I

I

~

.1.0

L:\

,

l~

t.l.
i..l.

]~
c

+

9-99

UAA180

Application circuit 3
for field strength indication
+12V

1krl

S.6V

TCA 440 or
TDA 1046. lOA 1047

9-100

ICs for Power Supply Control

SIEMENS

lDA 4601, lDA 4601 D
Control ICs for Switched-Mode
Power Supplies
• Low Start-Up Current

• Base Current Drive Proportional to
Collector Current

• Reversing Linear Overload Characteristic

• Protective Circuit for Case of Disturbance

• Direct Control of the Switching Transistor

Pin Configurations

Pin Descriptions

SIP9

Pin

DIP 18

0094-19

1

18

2
3
4
5

17

14

6

13

7

12

8

11

9

10

1
2
3
4
5
6

16
15

7
8

Function
VREF Output
Zero Passage Identification
Input Control Amplifier, Overload Amplifier
Collector Current Simulation
Connection for Additional Protective Circuit
Ground (Rigidly Connected to Substrate
Mounting Plate)
DC Output for. Charging Coupling Capacitor
Pulse Output-Driving of Switching
Transisto~

9

Supply Voltage

10-18 Ground (TDA 4601 D)

0094-20

The integrated circuit TDA 4601/0 is designed for driving, controlling and protecting the switching transistor in
self-oscillating flyback converter power supplies as well as for protecting the overall power supply unit. In case
of disturbance the rise of the secondary voltage is prevented. In addition to the IC's application range including
TV receivers, video tape recorders, hifi devices and active loud speakers, it can also be used in power supply
units for professional applications due to its wide control range and high voltage stability during increased load
changes.

@Siemens Components, Inc.

10-1

April 1988

lDA 4601, lDA 4601 D
Block Diagram

~
'

Control
Ampllfter

I

Slart-Up
Circuit

Slandby
Operation

Voltage
Control

II--

I

~U

rl

,I
t-U~~"ector

I~rioad
Identification ~ rl
Relerence
Voltage

I

Zero Passage
Identification

I

3

Coupllng-CCharging
Circuit

Control
Logic

I
I

Base Current
Shut-Down

t

,
5

The TDA 4601 is designed for driving, controllin~
and protecting the switching transistor in flyback
converter power supplies during start-up, normal
and overload operations as well as during disturbed
operation. In case of disturbance the drive of the
switching transistor is inhibited and a secondary voltage rise is prevented.

I. Start-Up
The start-up procedures (on-mode) include three
consecuti~e operating phases as follows:

1. Build-Up of Internal Reference Voltage
The internal reference voltage supplies the voltage regulator and effects charging of the coupling
electrolytic capacitor connected to the switching
transistor. Current consumption will remain at 19 <
3.2 mA with a supply voltage up to V9 approx.
12V.

2. Enabling of Internal Voltage-Reference
'

Simultaneously with V9 reaching approx. 12V, an
internal voltage becomes available, providing all
component elements, with the exception of the
control logiC, with a thermally stable and overload-resistant current supply.
3. Enabling of Control Logic
In conjunction with the generation of the reference voltage, the current supply for the control
logic is activated by means of an additional stabilization circuit. The integrated circuit is then ready
for operation.

10-2

~

Base Current
Amplifier

4

Circuit Description

Voltage V1 = 4V

rri

,

curren,
.mulation

t
2

Trigger
Slart
Hold

Ext Blocking
Alternatives

T
6

r
-

r
789

The above described start-up phases are necessary
for ensuring the charging of the coupling electrolytic
capacitor, which in turn supplies the switching tran, sistor. Only then is it possible to ,ensure that the transistor switches accurately.
'

II. Normal Operating Mode/Control
Operating Mode
At the input of pin 2 the zero passage of the frequency provided by the feedback coil is registered and
forwarded to the control logic. Pin 3 (control input,
overload and standby identification) receives the
rectified amplitude fluctuations of the feedback coil.
The control amplifier operates with an input voltage
of approx. 2V and a current of approx. 1.4 mA. Depending on the internal voltage reference, the overload identification limits in conjunction with collector
current simulator pin 4 the operating range of the
control amplifier. The collector current is simulated
by an external RC combination present at pin 4 and
internally set threshold voltages. The largest possible collector current applicable with the switching
transistor (point of return) increases in proportion to
the increased capacitance (10 nF). Thus the required operating range of the control amplifier is established. The range of control lies between a DC
voltage clamped at 2V and a sawtooth-shaped rising
AC voltage, which can vary up to a max. amplitude
of 4V (reference voltage). During secondary load reduction to approx. 20W, the switching frequency is
increased (approx. 50 kHz) at an almost constant
pulse duty factor (1 :3). During additional secondary
load decreases to approx. 1W, the switching frequency increases to approx. 70 kHz and pulse duty
factor to approx. 1: 11. At the same time collector
peak current is reduced to < 1A.

TDA 4601, TDA 4601 0
The output levels of the control amplifier as well as
those of the overload identification and collector currenl simulator are com'pared in the trigger and forwarded to the control logic. Via pin 5 it is possible to
externally inhibit the operations of the IC. The output
at pin 8 will be inhibited when voltages of
VREF
:5: -2- - 0.1V are present at pin 5.
Flipflops for contrOlling the base current amplifier
and the base current shut-down are set in the control logic depending on the start-up circuit, the zero
passage identification as well as enabling by the trigger. The base current amplifier forwards the sawtooth-shaped V4 voltage to the output of pin 8. A
current feedback with an external resistor (R =
0.680) is present between pin 8 and pin 7. The applied value of the resistor determines the max. amplitude of the base driving current for the switching
transistor.

III. Protective Operating Mode
The base current shut-down activated by the control
logic clamps the output of pin 7 to 1.6V. As a result,
the drive of the switching transistor is inhibited. This
protective measure is enabled if the supply voltage
at pin 9 reaches a value :5:6.7V or if voltages of
:5:

V~EF -

0.1V are present at pin 5.

In case of short-circuits occurring in the secondary
windings of the switched-mode power supply, the integrated circuit continuously monitors the fault conditions. During secondary, completely load-free operation only a small pulse duty factor is set. As a
result the total power consumption of the power supply is held at N = 6W ... 10W during both operating
modes. After the output has been inhibited for a voltage supply of :5:6.7V, the reference voltage (4V) is
switched off if the voltage supply is further reduced
by IlVg = 0.6V.
Protective Operating Mode at Pin 5
In Case of Disturbance
The protection against disturbance such as primary'
undervoltages and/or secondary over voltages (e.g.,
by changing the component parameters for the
switched-mode power supply) is realized as follows:
O'n application circuit 1; 10 kfi/3W.

Protective Operating Mode with Continuous
Fault Condit,lon Monitoring
In case of disturbance the output pulses at pin 8 are
inhibited by falling below the protective threshold Vs,
with a typical value of V1/2. As a result current consumption is reduced (Ig ~ 14 rnA at Vg = 10V).
With a corresponding high-impedance start-up resistor', supply voltage V9 will fall below the minimum
shut-down threshold (5.7V) for reference voltage V 1.
V1 will be switched off and current consumption is
further reduced to Ig :5: 3.2 rnA at Vg :5: 10V.
Because of these reductions in current consumption, the supply voltage can rise again to reach the
switch-on threshold of Vg ~ 12.3V. The protective
threshold at pin 5 is released and the power supply
is again ready for operation.
In case of continuing problems of disturbance (Vs :5:
V1/2 - 0.1V) the switch-on mode is interrupted by
the periodic protective operating mode described
above, i.e., pin 8 is inhibited and Vg is falling, etc.

IV. SwitCh-On in the Wide Range Power
Supply (90 Vac to 270 Vac)
(Application Circuit 2)
Self-oscillating flyback converters designed as wide
range power supplies require a power source independent of the rectified line voltage for TDA 4601.
Therefore the winding polarity of winding 11/13 corresponds to the secondary side of the flyback converter transformer. Start-up is not as smooth as with
an immediately available supply voltage, because
TDA 4601 has to be supplied by the start-up circuit
until the entire secondary load has been charged.
This leads to long switch-on times, especially i: low
line voltages are applied.
However, the switch-on time can be shortened by
applying the special start-up circuit (dotted line). The
uncontrolled phase of feedback control winding
15/9 is used for activating purposes. Subsequent to
activation, the transistor T1 begins to block when
winding 11/13 generates the current supply for TDA
4601. Therefore, the control circuit cannot be influenced during operation.

10-3

TDA 4601, TDA 4601 D

Absolute Maximum Ratings·
·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum.rating
conditions for extended periods may affect device
reliability.
Supply Voltage (Vg) .................... OV to 20V

VOltages
Reference Output (V1) ................ OV to + 6V
Zero Passage
Identification (V2) ............. - 0.6V to + 0.6V .
Control Amplifier (V3) ................. OV to + 3V
Collector Current
Simulation (V4) .............•....... OV to + 8V
Blocking Input (V5) .......•............ OV to +8V
Base Current Cut·Off Point (V7) ........... OV to Vg
Base Current Amplifier
Output (Va) ...........•.............. OV to Vg

Currents
Zero Passage
Identification (112l ....•........ - 5 rnA to + 5 mA
Control Amplifier (113) ............ - 3 mA to + 3 mA
Collector Current
Simulation (114) ................. 0 mA to + 5 mA

Blocking Input (li5) .••...••.•...... 0 mA to + 5 rnA
Base Current Cut·Off
Point (lq7) ...•....••.••...••.... -1A to + 1.5A
Base Current Amplifier
Output (Iqa) ...................... -1.5A to OA
Junction Temperature (TJ) ••••••••••.•.••.•. 125·C
Storage Temperature
Range (Tstg) .... ; ........... -4Q"C to + 125·C
Thermal Resistances
System·Air lOA 4601 (RthW ..••.••..... 70 K/W
System·Case TDA 4601 (RthSC>' ....•..• 15 K/W
System·Air(1) TDA 4601 0 (RthSA) ....... 66 K/W
System·Air(1) lOA 4601 0 (RthSAd .•..•• 44 K/W

Opefatlng Range
Supply Voltage (Vg) ..•..••......• + 7.8V to + 18V
Case Temperature TDA 4601
(TC) ........... ; ................ 00Cto +85·C
Ambient Temperature(3)
TDA 4601 0 (TA) ................ O·C to + 70·C
Notes: .
.
1. Case soldered on PC board without cooling surface.
2. Case soldered on PC board with copper-clad 35 110m lay·
er, cooling surface 25 cm2•
3. RthSA1 = 44 K/W and Pv = 1W.

Characteristics TA = 25°C; according to measurement circuit 1 and diagram
Parameter

Limits

Symbol
Min

Start Operation
Current Consumption
(V1 not yet Switched On)
Vg = 2V
Vo = 5V
Vg = 10V

Ig
Ig
Ig

Switching Point for V1

Vg

Normal Operation
Vo = 10V; Vcont = -10V; Vclock = ±5.0V; f

11.0

Units

Typ

Max

1.5
2.4

0.5
2.0
3.2

rnA
rnA
rnA

11.8

'12.3

V

= 20 kHz; Duty Cycle 1:2 afterSwitch·On

Current Consumption
Vcont = -10V
Vcont = OV

Ig
Ig

110
50

135
75

160
100

ITIA
rnA

Reference Voltage
11 < 0.1 mA
11 = 5mA

V1
V1

4.0
4.0

4.2
4.2

4.5
4.4

V
V

Temperature Coefficient of Reference Voltage

TC1

10-4

10-3

11K

TDA 4601, TDA 4601 D

Characteristics

TA = 2SoC; according to measurement circuit 1 and diagram (Continued)

Parameter

Min
Normal Operation (Continued)
Vg = 10V; Veont = -10V; Veloek

I

Limits

Symbol

Typ

Max

I

Units

= ±S.OV; f = 20 kHz; Duty Cycle 1:2 after Switch-On

= OV

Va

2.3

2.6

2.9

V

Collector Current Simulation Voltage
Veont = OV
Veont = OV/-10V

V4*
I:J.V4*

1.8
0.3

2.2
0.4

2.S
O.S

V
V

Clamping Voltage

Vs

6.0

7.0

8.0

V

Output Voltages
Vcont = OV
Veont = OV
Veont = OV/-10V

Vq7*
VqB"
I:J.VqB

2.7
2.7
1.6

3.3
3.4
2.0

4.0
4.0
2.4

V
V
V

Feedback Voltage

V2

Control Voltage Veont

Protective Operation V9

0.2

V

= 10V; Veont = -10V; Vclock = ± O.SV; f = 20 kHz; Duty Cycle 1:2

Current Consumption
Vs < 1.9V

Ig

Switch-Off Voltage
Vs < 1.9V

Vq7

Switch-Off Voltage
Vs < 1.9V

V4

Blocking Input
Blocking Voltage
Veont = OV

Vs

Supply Voltage Blocked for VB
Vcont = OV

Vg

V1 Off (with Further Reduction of Vg)

I:J.Vg

14

22

28

mA

1.3

1.S

1.8

V

1.8

2.1

2.S

V

V1
--01
2
.

V1
2

6.7

7.4

7.8

V

0.3

0.6

1.0

V

V

Note:

"DC component only

Characteristics

TA = 2SoC; according to measurement circuit 2

Parameter

Limits

Symbol
Min

Switching Time (Secondary Voltage)

Units

Typ'

Max

ton

3S0

4S0

ms

Voltage Variation
I:J.Na = 20W

S3

= Closed

I:J. V2see

100

SOO'

mV

Voltage Deviation
I:J.N2 = 1SW

S2

= Closed

I:J. V2see

SOO

1000

mV

20
7S
10

30

V
kHz
VA

Standby Operation
S1 = Open
Secondary Useful Load = 3W

I:J.V2see
f
Nprimary

70

12

The COOling conditions have to be optimized with regard to maximum ratings (Tc; Tj; RthSC; RthSA).
10-S

TDA 4601, TDA 4601 0
'~Ircult

Diagram

....-2

Test and Measurement Circuit 1

Test Diagram: Overload Operation
v
Vaocll

o

r'~+-~~~~-+~~~~--~
-,

~s

-0,5

TOA 4601

-V.=-10V
--- V. =0

v,

ps
-f

f
VCIocI&

Vcontrol

V•
....-3

+--------------------_-t ps
.... -4

10-6

TDA 4601, TDA 4601 D

Test and Measurement Circuit 2

.-------. 220Voc

o
lN~OO7

Notes:
1. Limits Ie max of BU 208 if the
permissible output power is exceeded.
2. Adjustment of secondary voltage.
3. Must be discharged before IC
Change.
- - - Protective circuit against rise
of secondary voltage in cases of
disturbance.

0004-5

Notes on application circuit 1

Protective Circuit Against Secondary Voltage
Rise even In Case of Disturbance
During standby this circuit type is necessary only under certain conditions. If switch S1 is open and the
secondary side is loaded with no more than 1W to
5W, a secondary voltage overshoot of approx. 20%
will occur.
In case of disturbance (e.g., if the potentiometer is
loosely.contacted resulting in 10 kn(2), if the capacitor exhibits a 1 ,...F loss in capacitance, or if the 2 kn
resistor increases to a high-impedance value of
32 kn), the protective effect of the standard turn-off
is not active before the point of return has been
reached. The result is that during disturbance energy

is pumped into the secondary side, which will not
ease off before reaching the point of return and, in
the worst case, entails an instantaneous doubling of
the voltage to 300V (endangering the secondary
electrolytic capacitors).
This additional protective circuit, which identifies the
energy surge as voltage overshoot, is directly active
at control winding 9/15. Through the 5sn resistor
and the 1N4001 rectifier the negative portion is deducted and stored in the 10 nF capacitor. If the amplitude exceeds the voltage of Z diode SZX 83/39,
pin 5 is drawn below the turn-off threshold, inhibiting
further control pulses at pin 8. During disturbance
conditions the voltage overshoot on the secondary
side will assume maximum values of approx. 30%.

10-7

•

TDA 4601, TDA 4601 D

Supplements to Test and Measurement Circuit 2
kHz

100

Frequency Versus Output Power

Efficiency Versus Output Power

%
100

~
r--...

r-....

o

20

40

/
I
20 II

-r- -

r-

20

o

/

I

60

40

10

100

o

120 W

Output power

o

20

40

60

10

v Loa dChara cters
I tl cs V2sec = f(1 2secl

160

- -- -- -- -- -- --,
,
/

, /
,, V'

, '/

~/
250V

220V

Jw

40

o

") l)

.1<'11,,,,

v" .. 180V;:7/ ~'"

.Jr;'

20
~

o

100 200

300

~

400 500

600 700 800 900 1000 1100 1200 mA
Output current I. u c 0094-8

v Output Voltage V2sec (Line Change)

151

t

lSO-

:f

f

.....V

1

148

147

......

V

'/

V
........-

149

/'r'
ISO

160

V
170

,./

180

190

200

210

220

230

240

250

,260 V

Line voIlage 0094-9

10-8

100

~--

0094-6

120 W
0094-7

lOA 4601, lOA 46010
Application Circuit 2 Wide Range from 80 Vac to 270 Vac
80 Vac to
270Vac

~,7nfJf:i!I'o,7r1
I~

0

B2501

i 'r

v:
IY'+
(1000

P

C25100

~

Y

~~

TOA 4601

I

2

5

~

2201l
12kll

100~tV

4

3

~

~I,II

7

6

(18

9
IIN22

~'

~

IU

Si 1,25A

12
kll

10kll

270Ml

21

1O~

Jr

IpF 5V
UI

47nF1I

"0'
a

V-

~kll

1OO1~25V
IU

~
2.

:aIOO~F/25V

IN4007
1.s~H

BY

360

e,\nF

A~TL·J29

~

II

270kll
C12

1

5.11
kill

'p~hOOV

BY360

IS

_.J

L..~lne.I~latl.on .

I

._._ . . .
16

Notes:
1. Limits Ie max a f BU 208 if permissible output power is exceed-

ed.
2. Adjustment of secondary voltage.
3. Must be discharged before Ie
change.

BY 360

BY 231

0139

IU

1001l[

~BU208

BY~9

j"F

1
331l
•
I
13
II
•9
'-'-'-'-'-' _._. ._.. ._. ._. . •._4 .
14
• 5

12

1

O,IIl
270PFt BYW29
lOOO~F

~ff--O
V3

270PF~

iJ

BY298~

~~

~~

v.

v,

270 pF

BY 299

0094-10

Notes on application circuit 2

Wide Range SMPS
Filtering of t~e rectified Ad voltage has been increased up to 470 ,...F to ensure an constant and
hum-free supply at Vline = 80 Vac. The stabilized
phase is tapped for supplying the IC. In order to ensure good start-up conditions for the SMPS in the
low voltage range, the non-stabilized phase of winding 13/15 is used as a starting aid (BD 139), which is
turned off after start-up by means of Z diode C12.
In comparison to the 22 Vae standard circuit, however, the collector-emitter circuit had'to be altered to
improve the switching be~avior of BU 208 for the

entire voltage range (80 Vac to 270 Vac). Diode
BY 231 is necessary to prevent inverse operation of
BU 208 and may be integrated for switching times
with a secondary power <75W (BU 208 D) .
Compared to the IC TDA 4600-2, the TOA 4601 has
been improved in turn-off during undervoltage at pin
5. The TDA 4601 is additionally provided with a differential amplifier input at pin 5 enabling precise
turn-off at the output of pin 8 accompanied by hysteresis. For wide range SMPS, TDA 4601 is recommendable instead of TOA 4600-2. If a constant quality standard like that of the standard Circuit is to be
maintained, wide range SMPS (80 Vac to 270 Vac)
with secondary power of 120W can only be implemented at the expense of time.
10-9

•

TDA 4601, TDA 4601 0

Further Application Circuits
Application Circuit 3
9OV-270Vac

1..,nFl[

'I'

1.~.1nF
T

I
I
I
I
I

I
IK231 ~
I
I
, II
, I
cl I
;1 I

5,:1

~
_

TOA 4601

(100:

1

_J

2

tSkl'!

10 220pF 31

~~

ISOkI'!
I.2A

UnF 11

~k1'l21

",

p~~

UI

8.~~F
II

------561'!

.,

BY 3601
I
I
BZX831
02 I

1
I
I
I,

;or

~
rlN~01
-------BY360

~~I
2,~~F
II

I
-1

Skl'l
BY360
11pF
;ill - ....
IS

~/('

51412: B78108
-K I

"i(

l pF{fV

l00~!SV

:: =1OO:~116V

21Okl'!

~

Ji'

,I

"N22
2.1kl'!
ISkl'!l1

10kI'! 12kI'!

I
I

6

5

1

21OkI'I WI'!

I,

I

3 4

IU

,I II
,," II
I ,
,
,

I

0

I

~Turnol ~
II·

13

*

I
2*

L
16
14

Notes:
1. Limits Ie max of BU 208 if permissible output power is exceeded.
2. Adjustment 0 f secondary voltage.
3. Must be discharged before Ie
change.

12'

BYW29

BYW29~

U___

I 2.2aoF

lmEin
IU

2A

2.1k1'1

lOB

71IOS

I 41pFi
VoI5V

V.18.5V

Y,/345 V
0094-12

Notes on application circuit 3

Fully Insulated, Clamp-Contacted PTC
Thermistor Suitable for SMPS Applications at
Increased Start-Up Currents
The newly developed PTe thermistor 063100P2462-J29 is designed for applications in SMPS as
well as in various other electronic circuits, which, for
'example, receive the supply voltage directly from the
rectified line voltage and require an increased current during turn-on. Used in the flyback converter

10-10

power supply of TV sets, an application proved millions of times over, the new PTe, thermistor in 'the
auxiliary circuit branch has resulted in a power saving of no less than 2W. This increase 'in efficiency
has a highly favorable effect, on the standby opera,
tion of TV s e t s . '
The required turn-on current needs only 6s to 8s
until the operating temperature of the PTe thermistor is reached. Low thermal capacitance of the PTe
thermistor allows ,the circuit to be operated again after no more than 2s. Another positive feature is the
improved short-circuit strength. The clamp contacts

TDA 4601, TDA 4601 D
permit more or less unlimited switching operations
and thus guarantee high reliability. A flame-retardant
plastic package and small dimensions are additional
advantages of this newly developed PTC thermistor.

Technical Data

Thermal Resistance
Standardized, ambient-related thermal resistance
RthJA1 lateral length I of a square copper-clad cooling area (35 tJ-m copper cladding).
RthJA (I

Breakdown Voltage at
TA = 60°C (VSA rmsl ..................... 350V
Resistance at TA = 25°C (R25) •............. 5 kfl
Resistance Tolerance (~R25) •........•.....• 25%

=

0) = 60 K/W
TA ~ 70°C
Pd = 1W
PC board in vertical position
Circuit in vertical position
Still air

Trip Current (Typ) (IK) ...•........•..•..... 20 mA
Leakage Current at VA max (Ilk) ...•.••....... 2 mA

1.0,------,.--------,

Max. Application Voltage (Vop max rmsl .•...... 265V
Reference Temperature (typ) (Tref) ....•..•.. 190°C
Temperature Coefficient (typ) (TC) .•....... 26 %/K

Max. Operating Current (Imax) .....•......•.•. 0.1A
Storage Temperature
Range (Tstg) ................ - 25°C to

+ 125°C

0.61----+-------1

50

100 mm
-I
0094-11

•
10-11

lDA 4601, lDA 4601 0
Application Circuit 4

o
PTe ,-J29

2.7kn

1.2SA

BY'2S8/200

4,7

2'1OpF

Notes:
1. Limits Ie max of BU 508 A if permissible output power is exceed-

ed.
2. Adjustment of secondary voltage.
3. Must be discharged before Ie
change.

VJs. c

V211C

V, sec:
0094-13

Notes on application circuit 4
Improved Load Control and
Short·Clrcult Characteristics
Turn-on is the same as for circuit 3.
To make the price more attractive, switching transistor au 508 A was selected.
To ensure optimum standby conditions, the capacitance between pins 2 and 3 was increased to
100 pF.
Z diode C6.2 transfers control voltage I!. Vcont directly to pin 3' resulting in improved load control.

10-12

Design and coupling conditions of various flyback
transformers were sometimes a reason for overshoot spectra, which, despite the RC attenuating element 330 x 22 nF and the 10 kO resistor, even
penetrated across feedback winding 9/15 to the
zero passage indicator input (pin 2) and activated
double and multiple pulses in the IC. Double and
multiple pulses, however, lead to magnetic saturation in the flyback transformer and thus increase the
risk of damaging the switched-mode power supply.
These overshoots are produced in particular when
high power is being carried, this occuring in the vicinity of the point of return. The switched-mode power
supply, however, reduces its own power to a minimum for all cases of overload or short-circuit. A series resonant circuit, whose resonance corresponds

TDA 4601, TDA 4601 D

Application Circuit 5
nOVae

Cj>PE
I

±330nF

I
I
I
I

n

2.

47mH

5,2A

IDA 46010
2

3

4

5

~
10kfl
~nF

lkn

N

22r

I
I
I

3.3pH

15OJ!tf

II

3~lnF

non

270kn

•
non

270kn

BY360

~

f-J~soeA
2~r"

j

II

Notes:
1. Limits Ie max of BU
508 A if permissible output Yoltage is exceeded.
2. Adjustment of secondary Yoltage.
3. Must be discharged
before IC change.
4. Optional use, depending on safety class:
Safety Class II 1 nF
only.
Safety Class I with nonfused grounded conductor 3.3 nF only.

to the transformer's self-oscillation, was created
through combination of the 4.7 pH inductance and
the 22 nF capacitance. This resonant circuit shortcircuits overshoots via a 33n resistor.

(f

= 211

~ :::: 500 kHZ)

Notes on application circuit 5

12V

41V

but, on the other hand, are implemented for economical reasons. An electrically isolated flyback
converter with a highly stable secondary side must
receive the control information from this secondary
side. There are only two possibilities of meeting this
requirement: either through a transformer which is
magnetically isolated from the flyback converter or
by means of an optocoupler. The development of
CNY 17 has enabled the manufacture of a component suitable for electrical isolation and characterized by high reliability and long-term stability.

Highly Stable Secondary Side
Power supplies for commercial purposes require
highly constant low voltages and high currents
which, on the basis of the flyback converter principle, can be realized only under certain conditions,

IC TDA 4601 0 is the successor of the TDA 4600 D.
It is compatible with its predecessor in all operational functions and in the control of a self-oscillating
flyback converter. Pin 3 is the input for the control
information, where the latter is compared with the

10-13

•
,

TDA 4601, TDA 4601 D

Application Circuit 6
Non-Fused
Grounded
Conductor

?

90Vac to
260V DC
330nF
~
47mH

,
,,
,
,,
,,
,
I
I

181

I
I

I

~

,

:

~y

K23

I

I
I
I

82501
(lOGO
(2540

151

J

~
~~

I

16

171

14\

13\

2

I 220Q
1.2kQ

lOOfEltV

5

4

~

lOOtfn/25V

~
2.1<£ 68111

12
kQ

•

~

,

" "'00~FI16V

f'N~OO7

C

l¢~35V

..

4.7t"

~kQ2)

"

2.2pH
BY360

~

II

270kQ

I
I

(11

I

I,

&639

I

51kQ

lpFlr"

I
I

BY 360

~~508A

2.2t

IU

BY 360

l00Q

L __

t -- ,

33nF

6
,
Lt -----.._._.

22nF

.

Notes:
1. Limits IC max of BU 508 A H permissible output power is exceed·

ed.
2. Adjustment of secondary voltage.
3. Must be discharged before Ie
change.

5

. . ._.

4
'-'-'

---

I

560Q

1

._._.

x3

.

. •1
BYW72

~

+

~~
V,44V/l0 .. A

The previous feedback and control information winding is not necessary. The feedback information (zero
passage) is obtained from winding 3/4-supply
winding. The'time constant chain 3300/3:3 nF and
3300/2.2 nF was Implemented in series with
150 p.H to prevent interference at pin 2. The LC element forms a series resonant circuit for overshoots
of the flyback converter and short·circuits them.

.

270PF~

270pFt BY360

I-<>

.

.4

10

11/12

reference voltage prevailing at pin 1 and the control
information from the optocoupler and subsequently
transformed into a frequency/pulse width control.

on application circuit 6

•

___ N22
51urns

'--

I

10-14

P7C .•J29

"

7J!
"N229
39Q I I

~

10
kQ

3.3unF

N~tes

i"

6

IU

.•

101

TDA4601D

1

5,0.5A

,
,,,
,
,,

111

121

V, 12V12A
0094-15

Wide Range Plug SMPS up to 30W

Due to their volume and weight, plug SMPS were So
far limited to a restricted primary voltage and a secondary power of no more than 6W.
The line-isolated wide range flyback converter presented here has a variable frequency and is capable
of producing a secondary power of 30W. It is characterized by a compact design with an approx. weight
of 400g. The entire line voltage range of 90 Vac to
260 Vac IS stabilized by to ± 1.5% on the secondary
side. Load fluctuations between 0.1 A and 2.0A are
regulated to within 5%. The output (secondary side)
is overload, short-circuit, and open-loop·proof.

TDA 4601, TDA 4601 D
Application Circuit 7
90VQ( to
260VQ(

~nFJi"~1I4 7nf
i

~

i i

! I.
!
!

I

!K!31
I

i
i

!

V'::

0

B2501
ClOOO
C2540

J

-

Y ~+

~~

!

TDA4601

1

I00pFI~V

220n
12kn

4

3

2

~

~
C18

l00~:25V

12
kn

10kn

270iin

'2

47nF1I

'il'
II

10kfl f-

MJ135V
UI
II

lN4007

I

i

~.

51
kn

lpFI!OOV
100nl

.

.J" BU208

'-'

1
I

11

._.

'-'

14

16

Notes:
1. Limits IC max of BU 208 if permissible output power is exceeded.
2. Adjustment 0 f secondalY voltage.
3. Must be discharged before IC
change.

~

33n

._. '-'-'

12

1

:r~
1--0

Notes on application circuit 7
Wide Range-SMPS with Reducing Peak
Collector Current ICBU 208 for Rising Line
Voltage (Variable Point of Return)

Wide range SMPS have to be dimensioned at line
voltages of 90 Vac to 260 Vac. The difference between the maximum collector current Ic BU 208 max
and the largest possible limit current Ic BU 208 limit
which causes magnetic saturation of the f1yback
transformer and flows through the primary inductance winding 5/7 is to be determined at VaCmin (Ic
BU 308 limit ~ 1.2 X IC BU 208 max>. Then, the transmissible power of the flyback transformer and its value at Vacmax is to be determined. In the standard

v,

j"F

•
x9
x5
x4

270PFt BY 299

O.ln
270PFt BYW29

BY 360

BY 299

BY 360
13

j

BY 231

639

'---

15 x

t!:!ne !so!aU~n .

,

15pH

A

C12

IU

~
2.

33kn

270kn

I
I

IU

ra lOO pFI16V

~IB

BY
360

B~rF

_.J

-J29

27kn

IU

So1.25A

i
i i
I i

A~TC

IlN229
7~J
0470 "

6

5

=EJ

BY298~

~O~

~~

270PF

v,
0094-16

circuit the collector current ICBU 208 max is almost
constant at the point of return independently of the
line voltage. The transmissible power on the secondary side, however, increases at the point of return in proportion to the rising rectified line voltage
applied (Figures 1 and 2).
In the wide range SMPS a line voltage ratio of
270/90 = 3/1 is obtained causing doubling of the
transmissible power on the secondary side, i.e., in
the wide range SMPS a flyback transformer had to
be implemented that was mLich too large.
The point of return protecting the SMPS against
overloads or short circuits, is derived from the time
constant at pin 4. T4 = 270 k!l x 4.7 nF. Thus, the
largest possible pulse width is determined.

10-15

•
•

TDA 4601, .TDA 4601 D
With the introduction of the 33 kO resistor this time
constant is reduced as a function of the control voltage applied to winding 13/15, rectified by diode
BY 360 and filtered by the 1 ""F capacitance, which
means that the pulse time becomes shorter. By
means of the Z diode C18 the line voltage level can
be defined at which the influence of the time constant correction becomes noticeable. The change in
the rectified voltage of winding 13/15 is proportional
to the change in the rectified line voltage.

At the point of return Ie BU 208 the peak collector
current has been reduced with the aid of the given
values from 5.2A at 90 Vac to 3.3A at 270 Vac. The
transmissible power at the point of return remains
stable between 125 Vac and 270 Vac due to the set
activation point of the point of return correction (unbroken curve in Figure 2).

Load Characteristic
V

200

v'"

t~~~dJy

180

I:

Con In>IIt...
'--

120

":'nt.'~rn

~2kJ.

-..

...;-

~50kHz

;{118kHZ

100

80

V

60

V
/

/

I

OWtrload Rangl

/

~~

40

fA h

Shy" Cirtuit

20

'NV

3kHz

l .,kHZ

o

o

"

~

~

u

~

u -1_
"

~A
0094-17

Figure 1
V
14

.....,

r:

i"'" .....

I

-.::::-.....

....,i!!01 Rotum

-.-

'1

I-

'If'125\

9OV'"\

f

...

"

./ my

/

V /
!/V

_\

fo'

V

/.
V

I&'

'- ...... fo'

~fo'

o

-I'

o

~

U

U

U

U

~

U

~

_ I...

UA
0094-18

Figure 2

Ordering Information
Type

Ordering Code

Package

TDA4601
TDA4601 D

Q67000-A2379
Q67000-A2390

SIP9
DIP 18 L9 (Pin 6
and Pins 10to 18
Grounded)

10-16

SIEMENS

TDA 4605
SMPS IC for Control of SIPMOS Transistors
• Direct Control of the Switching Transistor

Pin Configuration

Pin Description
Pin Designation

(Top View)
v 1 lC
v 2 2C
V3

GND

'-/

3C
4C

• Reversing Linear Overload Characteristic

:J B Vs
:J 7 v7
:J 6 va
~5 Q
0095-12

Function

1 Control
Voltage

Information input for secondary voltage. By
comparison of the control voltage derived from the
control winding of the transformer with the internal
reference voltage the output pulse width at pin 5 is
matched to the load on the secondary side (normal,
overload, short-circuit, open-circuit).

2 PrimaryCurrent
Simulation

Information input for primary voltage. The primarycurrent rise in the primary winding is simulated as a
voltage rise at pin 2 by means of an external RC
network. When a value derived from the control
voltage at pin 1 is reached, the output pulse at pin 5
is terminated. The maximum power in the point of
return is set with the RC network.

3 Undervoltage Input for primary-voltage monitoring. The IC is cut
out upon line undervoltage by comparison with an
Detector
internal reference. The voltage at pin 3 is used for
point-of-return correction.

4 Ground
5 Output

Push-pull C output supplies ± 1.5 A for fast charge
reversal of the gate capacitances of the power MOS
transistor.

S Supply

Input for the supply voltage. From this a stable
internal reference VREF and the switching
thresholds VSA, VSE, Vsmax and VSmin for monitoring
of the operating voltage are derived. VREF is turned
on for Vs < VSE and turned off for Vs < VSA.
The logic is only enabled for VSmin < Vs < Vsmax.

Voltage

7 Point-ofReturn
Correction

Input for point-of-return correction. The network on
this pin to ground influences internal correction
(slope and response).

8 Zero-

Input for oscillator feedback. After build-up each
zero passage of the feedback voltage (falling edge)
triggers an output pulse at pin 5. The trigger
threshold is typo + 50 mY.

Passage
Detector

This IC is designed for controlling an MOS power transistor and performing all necessary protective and
control functions in self-oscillating flyback converter power supplies. Owing to the IC's outstanding voltage
stability, which is maintained even at substantial fluctuations, the IC is suited for consumer as well as for
industrial applications.

@Siemens Components, Inc.

10-17

April 1988

•

TDA 4605

Block Diagram

0095-'

Functional Description
The power transistor and primary winding of the flyback transformer, which are connected in series, receive direct supply of the input voltage. During the
on-phase of the transistor, energy is stored in the
primary winding and during the off-phase it is released to the consumer via the secondary winding.
The IC controls the power transistor in such a way
that the secondary voltages are kept at constant values independently of input or load changes. The
control information required is obtained from the input voltage during the on-phase and from a control
winding (secondary winding) during the off-phase.
Load differences are compensated by altering the
frequency, input voltage fluctuations are additionally
counteracted by altering the pulse duty factor. This
results in the following load-dependent modes of the
SMPS:
- Open-loop or Output voltage slightly above set
small load:
value
-

Control:

Load-independent output voltage

-

Overload:

In case of overload or short-circuit,
the secondary voltage is decreased from the point of return as
a function of the load current, following a reversing characteristic

Typical values of pulse duty factor v, switching frequency f and duration of primary phase t of the power transistor:

Mode

v

Open-Loop
Small Load (5W)
Control Mode (30W -1 OOW)
Reversing Point 150W
Short-Circuit

0.1
0.33
0.33
<0.5
0.02

150
80
40
20
1.5

0.7
2.5
5.6
<25
<15

Description of Operation
A flyback converter designed for color TV sets, applicable between 30W and 120W and for line voltages ranging from 90V to 140V, is shown in one of
the following figures. On the subsequent pages the
major pulses can be found.
The line voltage is rectified by bridge rectifier Gr1
and smoothed by Ca.
During start-up the IC current is supplied via resistors R2 and Ra, and in the post-transient condition it
is additionally supplied via winding 13/11 and rectifier D3. The size of filter capacitor Cs determines the
turn-on behavior.
Switching transistor T1 is a BUZ 45. Parallel capacitance C9 and primary winding 117 form a resonant
circuit, thus limiting the frequency and amplitude of
drain-source voltage overshoots during turn-off of
T1. Self-oscillation is attenuated by R14. Diode D5
limits positive overshoots. R12 prevents static charging of the gate of
D1 improves the turn-off be-

n.

10-18

f/KHz tIlLs

TDA 4605
havior. The current rise in T1 is determined by the
inductance of the primary winding. This sawtoothshaped rise is simulated at network R7 C4 and applied to pin 2 of the IC.
Depending on the dimensioning of the primary inductance, timing element R7C4 is to be adapted to
the current rise angle in T1. Thus, during the onphase, the IC receives the control information in the
form of the simulated energy content of the primary
winding at pin 2 as a function of line voltage versus
time.
The control deviation at pin 1 is recorded by control
winding 9/15. This measure requires fixed coupling
with the secondary winding 2/16. The control winding is also used for feedback and permits self-oscillation of the parallel circuit Cs/primary inductance if
the power transistor is inhibited. Thus, the maximum
possible open-loop frequency is determined.
The control voltage required for pin 1 is rectified by
diode D4 and smoothed by capacitor C7' Furthermore, R13 and Ce form a timing element, which
serves for filtering fast changes in the control voltage, i.e. the final element does not become active
until several periods have occurred. By means of the
voltage divider formed of resistors Re, Rs, R10, the
secondary voltage can be set. Reason: in the IC the
control voltage produced at pin 1 is compared with a
stable, internal reference voltage.
According to the result of this comparison, frequency and pulse duty factor are corrected until the secondary voltage selected by R10 has established itself. For all operating modes of the SMPS, the zero
passages of the voltage at the control winding contain information on pulse duty factor and switching
frequency of the switching transistor T1, or the
open-loop frequency. Conditioning of the corresponding signal at pin 8 is performed by series resistor R11 and by integrated limiter diodes.
An SMPS based on these principles would have a
point of return dependent on the line voltage. With
respect to the distance to the saturation point, the
transformer must be dimensioned for maximum
power, i.e. for maximum line voltage and the power
then occurring at the point of return.
In order to keep the size of the transformer as small
as possible, the IC makes the point of return largely
independent of the rectified line voltage. If necessary, the reverse point correction of the IC can be
altered by a network from pin 7 to ground. The information on the line voltage is applied to pin 3. Before
the line voltage falls below its minimum value, the
SMPS must be turned off by the IC in order to obtain
defined turn-off conditions.

During undervoltage, the information required for
turn-off is applied to pin 3 via the resistive divider
R4/Rs. On 'the secondary side the output voltages
V1 sec to V4 sec are available. If the secondary side
is further deloaded, standby is set automatically. Resistor R1S forms a basic load of voltage V1 sec and
contributes to maintaining standby conditions (Vsec
rise 20%). Capacitors C10 and C13 prevent spikes
generated by reversing the rectifiers D7 through D9.
The secondary voltages are smoothed by charging
electrolytic capaCitors C14 through C17.

1.0 Start-up Behavior
In Figure 1, the start-up behavior of the application
circuit is illustrated for a line voltage that is barely
above the value for undervoltage.
After application of the line voltage at the point in
time to, the following voltages build up:
- Vs according to the halfwave charge across R2
and R3
- V2 to V2 max (typ. 6.2V)
- V3 to the value given by divider R4/Rs.
The current consumption of the IC in this mode of
operation is smaller than 1.5 mA. When Vs reaches
the threshold VSE (time t1), the IC turns on the internal reference voltage. The current consumption increases to typically 12 mAo The primary-current voltage transformer reduces V2 to V2B and between
time ts and ts the start-pulse generator will produce
the start pulse. The feedback at pin 8 starts the next
pulse and so on. All pulses, including the start pulse,
are controlled in width by the control voltage at pin
1. Upon turn-on this corresponds to the case of
short-circuit, i.e. V1 = OV. Thus, the IC starts with
"short-circuit pulses" that widen according to the
feed-back control voltage. The IC operates in the
point of return. Afterwards the peak values rapidly
drop to V2 because the IC is operating in the control
range. The control loop is stabilized. If voltage Vs
falls below the output threshold VSmin before, the
point of return is reached, the start will be interrupted (pin 5 goes Low). The IC remains turned on, so
Va drops further to VSA. Then the IC turns off, Va can
build up again (time t4) and a new turn-on attempt
begins at time t1' If the rectified line AC voltage (primary voltage) breaks down because of the load, V3
can, as happens at time t3, fall below V3A (turn-on
attempt with undervoltage). The primary-voltage
monitoring then clamps V3 to V3S until the IC turns
off (Va < VaA). Then a new turn-on attempt is started at time t1'

10-19'

__
,

TDA 4605

2.0 Control, Overload and OpenCircuit Behavior
When the Ie has started up, it operates in the control range. The voltage on pin 1 is typically 400 mV.
When the output is loaded, the control amplifier permits wider charge pulses (V5 = H). The peak value
of the voltage at pin 2 increases to V25 max' If the
secondary load is increased further, the overload
amplifier will start to reduce the pulse width. Because the change in pulse width reverses, this is
called the point of return of the power supply. The Ie
supply voltage Va is directly proportional to the secondary voltage, so it breaks down according to the
overload control response. If Va falls below the value Va min' the Ie will go into sampling operation. The
time constant of the halfwave start-up is relatively
large, so the short-circuit power remains small. The

overload amplifier reduces to the pulse width tpsh'
This pulse width must remain possible so that the Ie
can start without any problems from the virtual shortcircuit, i.e. the turn-on with V1 = o.
If the load is reduced on the secondary side, the
charge pulses (V5 = H) become narrower. The frequency increases up to the natural frequency of the
system. If the load is reduced further, the secondary
voltages build up to Va. At Va = Va max the logic is
blocked. The Ie goes into sampling operation. Thus
the circuit is absolutely open-circuit-proof.

3.0 Overtemperature Response
An integrated temperature cutout blocks the logic if
the chip temperature becomes inadmissibly high.
The Ie automatically samples the temperature and
starts as soon as it drops to an admissible level.

Absolute Maximum Ratings'"
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Limits
Parameter
Symbol
Units
Remarks
Min
Max
Voltages
Pin 1
-0.3
V
+3
V1
Pin 2
0.3
V
V2
Pin 3
-0.3
V
V3
Pin 5
-0.3
V
V5
Vs
+20,
Pin a
Supply Voltage
0.3
V
Vs
Pin 7
-0.3
V
V7
Pin 8
-0.3
V
Ve
Currents
Pin 1
-3
mA
+1
11
Pin 2
-3
mA
+3
12
Pin 3
3
mA
+3
13
-1.5
to s; 50 ,,"s; v s; 0.5
A
Pin 4
14
-1.5
+1.5
A
Pin 5
to s; 50 "'s; v S; 0.5
Is
Pin a
0.01
+1.5
A
to S; 50 ,,"8; v S; 0.5
Is
Pin 7
3
mA
+1
17
Pin 8
-3
mA
+3
Ie
·C
Junction Temperature
125
TJ
·C
Storage Temperature Range
40
+125
Tstg
Thermal Resistances
Junction-Air
100
K/W
RthJA
Junction-Case
70
K/W
RIhJC
Measured at Pin 4
Operating Range
Supply Voltage
7.5
15
V
Vs
·C
-20
Case Temperature
+85
Tc

10-20

TDA 4605

Characteristics TA - 25°C
Parameter

Symbol

Measurement
Circuit

J Units

limits
Min

Typ

I Max I

Start-Up Hysteresis
Start-Up Current Consumption
Vs - 5V

IS/5

1

0.5

0.75

mA

Start-Up Current Consumption
V6 - 8V

IS/8

1

1

1.5

mA

Turn-On Voltage

VSE

1

11

12

13

V

6

6.5

7

V

16

mA

Turn-Off Voltage

VSA

1

Turn-On Current
V6 - VSE

ISE

1

12

Turn-Off Current
V6 - V6A

ISA

1

10

Voltage Limiter
(V6 = 10V,ICTurnedOff)
at Pin 2 (V6 < V6E)
12 - 1 mA

V4max

Voltage Limiter
(Vs = 10V, IC Turned Off)
at Pin 3 (V6 < VSE)
la- 1mA

V5max

mA

1

5.6

6.6

7.6

V

1

5.6

6.6

7.6

V

Control Range
Control Input Voltage

V1cont

Gain in Control Range
d (V2S - V2B)
Gcont =
dV1

Gcont

2

400

mV

2

-400

mV

Prlmary-Current Simulation Voltage
Basic Value

V2B

2

1

V

Maximum Peak Value
G1 - V1cont(2VlVcont>

V2Smax

2

3

V

V1U

2

400

mV

2

150

mV

2

2

2

360

mV

2

-140

/LA

Overload and Short-CIrcuit Operation
Overload Range Upper Limit
Overload Range Lower Limit

V1L

Gain in Overload Range
d(V2S - V2B)
Gover =
dV1

Gover

Input Voltage in Overload Range
Vcont - 3.5V

V1

Input Current in Short-Circuit Operation
Vcont - OV

11

10-21

lOA 4605

Characteristics

TA = 25°C (Continued)

Parameter

Symbol

Measurement
Circuit

Limits
Min

Typ

Units
Max

Overload and Short-CIrcuit Operation (Continued)
Peak Value in Overload Range
Vcont = 3.5V

V20ver

2

3.0

V

Peak Value in Short-Circuit Operation
Vcont = OV

V2sh

2

2.7

V

Output Pulse Width in Overload Range
Vcont = 3.5V

1pover

2

8.5

}Ls

Output Pulse Width in Short-Circuit Operation
Vcont = OV

tpsh

2

7.5

}Ls

Current Consumption in Overload Range
Vcont = 3.5V

Is

2

12

mA

Current Consumption in
Short-Circuit Operation
Vcont = OV

Is
2

10

rnA

2

5

V

1

-460

}LA

V

Generally Valid Data (VS = 10V)
Point-of-Return Correction
Point-of-Return Correction Voltage
V3 = 5V;V2 = OV

V7

Poiot-of-Return Correction Current
V3 = 5V;V2 = OV

V4

Zero-Passage Detector Voltage
Positive Value

VBP:

2

0.7

Negative Value

VBN

2

-0.2

V

tcl4

2

2

}Ls

S in Setting 1 of Upper Transistor
1.SA
15 -

VsatU

1

2

V

S in Setting 1 of Lower Transistor
15 - +1.5A

VsatL

1

2

V

2

10

VI}Ls

2

50

V/}Ls

Delay between VB and V2
Output-Stage Data
Saturation Voltages

Slew Rate of Output Voltage
Rising Edge
Vcont.= 3.5V

+dV5/dt

Falling Edge
Vcont = 3.5V

-dV5/dt

10-22

TDA 4605

Characteristics TA = 25·C (Continued)
Parameter

Symbol

Measurement
Circuit

Min

Limits
Typ

Max

2

0.3

0.5

1

V

14

15

16

V

Units

Protective Circuits
1. Undervoltage protection for Ve:
Voltage on Pin 5 = VSmin
When Ve < Vemin
(With Vemin = VeA + t;,. Ve)

t;,.Ve

2. Overvoltage Protection for Ve:
Voltage on Pin 5 = VSmin
When Ve < Vemin

Vemax

3. Undervoltage Protection for Vline:
Voltage on Pin 5 = VSmin
When Vs > VSA, V2" = OV

VSA

4. Overtemperature:
Chip Temperature at Which
IC Switches Vs to VSmin

TJ

Voltage on Pin, 3 after Response
of Protective Function
(Vs is Clamped Until Ve < VeAl
Is = 3mA

Vs

Sampling Current Consumption
Vs = V2 = OV

Ie

1

1

V

2

125

·C

1

0.2

1

12

mA

V1S
V2S
VSS
V4S

3
3
3
3

95
26
15
8.5

V
V
V
V

Turn-On Time for
Secondary Voltages

ton

3

120

ms

Voltage Alteration
between S5 Open and S5 Closed

t;,.V1S

3

100

500

mV

Load Variation Cross-Talk
Voltage Alteration
between S6 Open and S6 Closed

t;,.V1S
3

500

1000

mV

20
80
10

30

V
KHz
VA

Normal Operation
(Vline = 220V; S1, S2, S3, S4 closed)
1. Secondary Voltage
2. Secondary Voltage
3. Secondary Voltage
4. Secondary Voltage

Standby Operation
(Vline = 220V; Psec :s;: 2W)
Voltage Build-Up
Frequency
Power Consumption
Point-of-Return Stability

aV1S
f
Pprim

Maximum Secondary Current
(secondary point of return)
S1 Closed 11Smax is set with R17
V1S = 85V

11Smax

Relative Alteration of 11Smax
80V < Vline < 140V

t;,.1 1Smax

3
3
3

3

3

75

0.4

15

1.85

V

A

±10

%

10-23

lOA 4605
Measurement Circuit 1

::j
TDA 4605
6

v,

s·

H
Measurement Circuit 2

.v.

Vconl

91011

1

.. rnF

3.3nF=j=

1

U

2

loon

3

10-24

J:O~F ~ Fl00 nF

20kn I ]lokn

10kn

J----!!

8

1kn

v,

I

L--o
TDA 4605

6

s ~rF
II

0095-3

TDA 4605

Measurement Circuit 3
Fl

2,5A

l1'n.-80 to

r-:---:-=:-f------------------;;-I

140Vac

V,.ec

Trl similar to
AZY2100

R,
150kQ

03

13

11
09

.-~
S3

15

Discharge C3
before IC Change

RI,
150
15W

Switched as Shcwn
unless Stated Otherwise

Line solation

0095-4

Application Circuit
Fl

C"C2i,~

~l

2,5A

~.;;;.:o to r.--:':l{.r_4+-_-t'---~--r--~--~t'-~----------------------~------------~--;,ii' r.2,----r-..,°1;l7h r-.,-_--.,.-<> V.I.' _ 95 V
llec, -nom. 800 rnA
-max. 1100 mA

R"
33kO

Tr 1 similar to
AZY2100
270pF

08

03

VI8C2-26V

.,;......-eIl-.-~-----O/... 2 _ nom. 100 mA

13

- max. 1200 mA

I

C-----ro~--~::~--r--_+~·~1
C,
14nF

Discharge C.
before IC Change

05
BY258

•

I

15

I

I
I

I

V.ec4 -8.5V

F=-.-EiII---,;:-....----<> I .... _ nom, 300 mA

i

,I
I

!

Line Isolation
0095-5

10·25

lOA 4605

1
J

\
Start

•h

~\."

-I

....
\.,

,,
\

Stop

_I

,-- ---T"--'

s

I
I

I
I

,
1 ,
-I

Ia

t

.,

V

~"""II
I
I
I

.....1

I

II
I
'

l

-I

\

~
-I
0095-6

Figure 1

10-26

TDA 4605

Magnified Extract
'for TImed I

f

VSE 4-----..
Vs +----;.-+--P--.

_t

_t
0095-7

Figure 2

&I

10-27

TDA 4605

1. Start-Up Hysteresis

f

2. Operation in Measurement Circuit 2

- -

l ••
I ..

V,

t

10

5V

20

40

50 ps

r ~p+;-------;-------;---

V6E VSmax

VElA Vemln 8V

30

1------1-1

-w

-I

--I

w

V. N
0095-8

v,

fv,s~i=========~====~~

f~. .

+ - - - - - - - I - r -....

0095-9

Frequency f versus
power P1S

Efficiency '11 versus
%secondary power P1S

kHz secondary
100

100

V.. -140V

f

fa

fa

0

\.

60

40

\\ I',
\ ,

~'

60

../

ae- 14OV-

Vae-SOV"

i'..

"

I
p2S-r3S-p4~-OW

50

100

I

I

,

Measurement Clrcun

0

-

/

40

..........
20

0

ISO

~

-200 W

20
Measuremenl Clrcun3
P,s-~3S-P,siow

0

50

100

1SO

200 W
0095-10

10-28

TDA 4605
Secondary Voltage
V15 versus Secondary
v Current 115
120

Peak Collector Current Ie max
of Switching Transistor versus
A Primary Voltage Vllne

10

l

r~o ~ r--

Vac -140V

I

["\\

0

V.c-!I~

~

6

0
4
40

2

20

Measurement Cln:uH

Measurement Circuli

o

P2S- P3S- P4S- 0 \l

i

0,4

-.I

G.B

1,2

1,6

2,0 A

-----ViS

0

P 2S-P3S-P4S -OW
V'·-1110V i

..1

80

100

120

140

160 V

---..V,1"8
0095-11

Ordering Information
Ordering Code
Q67000-A8078

•
10-29

SIEMENS

TDA 4814A
Ie for Active Line Filters
Pin Configuration

Pin Definitions

(Top View)

Pin

Symbol

Function

1
2
3
4

10
11
12
13

Os
QD
Vs
-ICOMP
+ I Op AmplVREF
I START
N.C.
QSTART
QSTOP
I STOP
IM1
-IOPAmp
QOpAmp/l M2

14

IDET

Ground
Driver Output
Supply voltage
Negative Comparator Input
Positive Input Op AmplVREF
Start Input
NOt Connected
Start Output
Stop Output
Stop Input
Multiplier Input
Negative Input Op Amp
Op Amp Output/Multiplier
Input 2
Detector Input

......
Os

1[

14 I DET

QD

2[

1~

Vs

3[

12 -lOp Amp

-I COMP 4[
+1 Op Amp/V..,

S[

I START

6[
7[

NC.

Q OpAmplIH2

5
6
7
8
9

11 IMI
10 I STOP
]9

Q STOP

]8

Q START
0078-1

This device contains the components for designing a switched-mode power supply with sinusoidal line-current
consumption. Sinusoidal line current is drawn from the supply network in particular when there is high power
consumption. One possible application is in electronic ballasts for fluorescent lamps, especially when a large
number of these lamps are concentrated on one supply point. This IC is additionally suitable for general driving
of switched-mode power supplies. The possibility for regulating the output voltage will enable operation on
different line voltages (110 Vac/220 Vac) without any switchover.
A monitoring circuit makes it possible to control various turn-on and turn-off functions of different units of
equipment.

@SiemensComponents, Inc.

10-30

May 1988

TDA 4814 A

Circuit Description

Driver Output Q for SIPMOS Transistors

The IC switches from standby to full current consumption when the turn-on threshold on Vs is exceeded. Turn-off is controlled by hysteresis. The integrated Z diode limits the voltage on Vs when impressed current is fed.

The output driver is deSigned as a push-pull stage.
There is a resistor of 10n in series with the output
for the purpose of current limiting. Between Q and
ground there is a resistor of 10kn. This keeps the
SIPMOS transistor reliably turned off during standby.

The operational amplifier (op amp) can be wired as a
control amplifier. It will then compare the divided
output voltage Va to a reference voltage VREF that
is stable with temperature. The output voltage of the
op amp that is produced in this way is multiplied by a
sine-magnitude voltage in the multiplier (M). At the
output of the latter a sine-magnitude voltage then
appears that is variable in amplitude. This nominal
voltage is applied to the plus input of the comparator. The nominal voltage at the multiplier output can
then be compared via the comparator to a voltage
derived from the actual line current. The output of,
the comparator feeds the reference signal via a logic
circuit to the driver that switches the SIPMOS transistor. No current gaps may appear in the choke,
otherwise the line current would no longer be sinusoidal. To achieve that, the detector input I DET senses when the choke current has fallen to zero after
turn-off of the SIPMOS transistor. This ensures that
the SIPMOS transistor does not turn on too early
and that no current gaps occur.

The Q output is additionally connected to the supply
voltage Vs and to ground by way of diodes.

When the detector input I DET is on High potential,
the SIPMOS driver Q is blocked. At the same time
the flipflop can be set by the comparator.
When I DET is Low, the Q output is enabled and can
be disabled again by the comparator by resetting the
flipflop.
Consequently the choke is always currentless when
the SIPMOS transistor turns on and no current gaps
appear in the choke.

When the supply voltage to the switched-mode power supply is turned on, the diode towards Vs conducts the capacitive displacement currents from the
gate of the SIPMOS transistor into the smoothing
capacitor on Vs. The voltage Vs may not exceed
0.7V if the SIPMOS transistor is to remain turned off.
The diode towards ground clamps negative voltages
on Q to -0.7V. Capacitive currents produced by
voltage incursion on the drain of the SIPMOS transistor are thus able to flow away unhindered.

Reference Voltage (VREF)
The reference-voltage source is highly stable with
temperature. It can be used if additional, external
components are wired.

Monitoring Circuit (I START,I STOP,
Q START, Q STOP)
The monitoring circuit guarantees the secure operation of a unit of equipment. Any circuitry that is shut
down because of a fault, for instance, cannot be
started up again until the monitoring start (I START I
Q STARn has 'turned on and a positive voltage
pulse has been impressed on Q START.
If there is a defect present, the monitoring stop
(I STOP/Q STOP) will turn on and shut down either
the entire unit or simply the circuitry that has to be
protected. No restart is then possible until the hold
current impressed on I START or I STOP has been
interrupted (e.g., by a power-down).

10-31

TDA 4814 A

Absolute Maximum Ratlngs*
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter
Supply Voltage

Symbol
Vs

Limits

Conditions
. Vz = Z Voltage

Units

Min

Max

-0.3

Vz

V

Inputs
Comparator

VICOMP
V-ICOMP

-0.3
-0.3

33
33

V
V

OpAmp

VIOpAmp
V-I'OpAmp

-0.3
-0.3

6
6

V
V

Multiplier M1

VM1

-0.3

33

V

Output Op Amp

Va OpAmp/lM2

-0.3

6

V

Z Current Vs GND

Iz

Driver Output

Va

Q Clamping Diodes

laD

Input

START
STOP

VI START
VI STOP

Output

START
STOP

Va START
Va STOP

Detector Input

VIDET

Detector Clamping Diodes

VIDET

CapaCitance at I START
to Ground

CISTART

Junction Temperature

Ti

Storage Temperature

Tstg

Thermal Resistance
System-Air I

RthSA

0

300

mA

-0.3

Vs

V

Va>Vsor
Va < -0.3V

-10

10

mA

See Characteristics
See Characteristics

-0.3
-0.3

25
33

V
V

-10
-0.3

3
6

V
V

0.9

6

V

-10

10

mA

150

,..,F

125

·C

125

·C

65

K/W

VSON

Vz

V

0

200

rnA

Observe Pmax

VIDET> 6Vor
VI DET < 0.9V

-55

Operating Range
Supply Voltage

Vs

Values for Vs ON. Vz
See Characteristics

ZCurrent

Iz

Observe Pmax

Driver Current

laD

-300

+300

rnA

TA

-25

+85

·C

Operating Temperature

10-32

lOA 4814 A

Characteristics

(VSON*

< Vs < vz;

Parameter

- 25°C

< TA <

+B5°C)
Limits

Symbol

Units

Min

Typ

Max

2.5

5

0.5
6.5

mA
mA

15

mA

11.2

V

Current Consumption
Without Load on Driver a
and VREF; a Low
OV < Vs < VSON
VSON < Vs < Vz

Is

Load on aD with SIPMOS gate;
Dynamic Operation 50 kHz
Vs = 12V; Load on a = 10 nF

Is

Hysteresis on Vs
Turn-On Threshold for Vs Rising

VhyH

9.6

10.4

Switching Hysteresis

VShy

1.0

1.7

V

Input Offset Voltage

VIO

-10

+10

mV

Input Current

-II

2

p.A

3.5

V

Comparator (COMP)

Common-Mode Input Voltage Range

VIC

0

Open-Loop Voltage Gain

GVO

60

Input Offset Voltage

VIO

-30

Input Current

-II

Common-Mode Input Voltage Range

VIC

Operational Amplifier (Op Amp)
BO

dB
-10

mV

2

p.A

0

3.5

V

10 Op Amp

-3

+1.5

rnA

Va Op Amp

1.2

Output Current
Output Voltage
Transition Frequency

fT

2

MHz

Transition Phase

CPT

120

degrees

4

V

Output Driver (00)
Output Voltage High
10 = -10mA

VaH

Output Voltage Low
10 = +10mA

Val

Output Current
Rising Edge Cl = 10 nF
Falling Edge Cl = 10 nF

-10
10

5

200
250

V

300
350

1

V

400
450

rnA
rnA

10-33

TDA 4814 A

Characteristics (VSON· < Vs < Vz; -25°C < TA < +85°C)(Continued)
Parameter

Umits

Symbol

Units

Min

Typ

Max

VREF

1.8

2

2.2

V

0

3

mA

5
20

mV
mV

+0.5

mVlK

17

V

Reference-Voltage Source
Voltage
0< IREF < 3mA
Load Current

-IL

Voltage Change
10V < Vs < Vz
o mA < IREF < 3 mA

AVREF

Temperature Response

AVREF/AT

-0.5

Z-Dlode (Vs-GND)
. ZVoltage
Iz = 200mA
Observe Pmax

Vz
13

15.5

Multiplier (M1)(1)
Quadrant for Input Voltages

quo

1

Input Voltage M1

VM1

Reference Level for M1

VREFM1

Input Voltage M2

VM2

Reference Level for M2

VREFM2

0

1

V

VREF+1

V

0
VREF

V
V

VREF

Input Current M1, M2

-II

0

Coefficient for OutputVoltage Source

Co

0.4

Temperature Response of
Output-Voltage Coefficient

ATC/CO

2

p.A

0.6

0.8

. ltV

-0.3

-0.1

0.1

%/K

Monitoring Circuit
Input I START
Turn-On Voltage
Turn-On Current
Turn-Off Voltage
Turn-Off Current

VI ON START
II ON START
VI OFF START
II OFF START

17
50
2
70

22
90
3.5
110

26
130
5
150

V
p.A
V
p.A

Input I STOp··
Turn-On Voltage
Turn-On Current
Turn-Off Voltage
Turn-Off Current

VI ON STOP
II ON STOP
VI OFF STOP
II OFF STOP

27
100
4.5
175

30
150
6.5
250

33
200
8.5
320

V
p.A
V
p.A

400

600

800

mA

Transfer I START-Q START
Output Current on Q START
VSTART = 15V;
VOSTART = 2V

-10 START

··The tum·on voltage of ISTOP exceeds the tum-on voltage of ISTART by at least 3V.

10-34

TDA 4814 A

Characteristics

(VSON*

< Vs < Vz;

-25°C

Parameter

< TA < + 85°C) (Continued)
Limits

Symbol

Units

Min

Typ

0.9

1.2

mA

90

150

/LA

1.3

Max

Monitoring Circuit (Continued)
Transfer I STOP - 0 STOP
Output Current on 0 STOP
ISTOP = 1.5 mA;
VSTOP = 18V;
VQSTOP = 1.2V

-IQSTOP

ISTOP = 0.4 mA;
VSTOp:::: 7V;
VQSTOP = 1.2V
Detector (I DET)
Upper Switching Voltage
for Voltage Rising (H)

VOETH

1

lower Switching Voltage
for Voltage Falling (l)

VOETL

0.95

Switching Hysteresis

VShy

Input Current
0.9V < VOET

-IOET
IOET

V
V

50

300
5

< SV

Clamping-Diode Current
VOET > SV or VOET < 0.9V

1.S

-3

mV
/LA

3

mA

500

ns

Delay Times
. Input Comparator --+ 0(2)

t

200

Notes:
1. Calculation of the output voltage YOM: VOM = C· VM1* • VM2* in V. The voltages of VM1* and VM2* are referred to the
particular reference level.
2. Step functions at comparator input .1VCOMP = -100 mV .1 VCOMP = + 100 mY.
*Vs ON means that VSH has been exceeded but that the voltage is still greater than VSL.

Use and Advantages of IC TDA 4814
in Switched Mode Power Supplies
and Electronic Ballasts

are more than compensated by the fact that a subsequent converter can constantly be operated at an
optimal operating point because of the input control
of the operating voltage.

1_0 Switched Mode Power Supplies

The extra effort that is necessary, compared to an
SMPS without an active harmonics filter, is made
good upwards of about 500W by savings elsewhere
(e.g., smalier smoothing capacitance and transistors
of a higher resistance in the SMPS). With the wideranging power supplies that are in increasing demand, i.e., power supplies that can work on a line of
90 Vac through 240 Vac without any switching
changes, the power pay-off limit reduces markedly.

The "active harmonics filter" consists of a rectifier
arrangement in a bridge circuit followed by an upconverter. Through a controlier action it is possible
to draw a virtually sinusoidal current from the singlephase line and produce a regulated dc voltage at the
output.
In the case of an SMPS with conventional line rectification it is possible to achieve a power factor (ratio
of active power to apparent power) of 0.5 to 0.7. The
active harmonics filter serves for improving the power factor, which reaches a value of almost 1, and for
reducing the load on the line produced by harmonics. The losses caused by the active harmonics filter

2.0 Electronic Ballasts for
Fluorescent Lamps
The VDE and the EVUs require of industrial consumers that these take "sinusoidal current" from the

10-35

•

TDA 4814 A
line, i.e., exhibit a purely ohmic response. This is the
case with incandescent lamps, cooker rings and
heating fixtures.
In all electronic devices with rectification and a CR
load the current drain is pulsed, i.e., afflicted by a
large harmonic content and impermissible according
to VDE. The reflected current ripple can interfere
with installations for AF power-line carrier control for
instance, i.e., lead to faulty switching. The harmonic
content of the current consequently may not exceed
certain values.
In the line current for a ballast operating with a stable fluorescent lamp must be such that the share of
harmonics in relation to the fundamental does not
exceed the values given in Table 1.

Table 1. Llne-Current Harmonic Content
According to VDE 0712, Part 2
Harmonics
3rd Harmonic
Sth Harmonic
7th Harmonic
9th Harmonic
11 th Harmonic
, 13th Harmonic
and Higher
Note:

Admissible
Harmonic Content(1)
In%

A
2SX0.9
7
4
3
2
1

1. A is the power factor.
The values 9iven here are achieved using the TDA 4814 A
to drive a SIPMOS in an up-converter regulating circuit.

Application Example
Electronic Ballast
Lln.o----A

.my

,-

v.

1-

TDA4814A
QSTW
•

9
0078-2

Remark:
Kindly note that the SIEMENS AG holds patents on electronic ballasts for fluorescent lamps, published in "Siemens
and Automation", Vol. II, No.2. March/April1985.

En~rgy

Ordering Information
Type

Ordering Code

TDA4814 A

Q67000-A8163

10-36

SIEMENS

TDA 4917 A/TDA 4917 G
Monitoring Ie for Power Supplies
• Monitors 5

+

2 Independent Voltages

• Freely Selectable Tolerance Width of Five
Input

• Three-Independent, Variable Timing
Networks for Three Signaling Outputs
• Supply Undervoltage Monitoring

• Overvoltage and Undervoltage Signaling

• AC Monitoring

• Power-Fail Signal

• Balanced Reference-Voltage Source

2.5V ±1%

• DIP 20 or SO 20 Package

Pin Configuration

Pin Definitions
Pin

OV
V,

20

Vq,EI:

'9

INIJl

"Ul

3

18

INO.z

'POl

4

17

'PUJ

INUl
INOI

6

1
2

OV
Vs
IpU1
Ip01
INU1
IN01
IpU2
Ip02
IpF

16

'POJ

3

15

QOlJOlC

4

l'Ul

7

14

QUVDN

'P02

8

13

QPFN

IPf

9

12

C3

C1

10

11

C2

Symbol

Function

P-DIP 20 Package (TDA 4917 A) or
SO 20 Package (TDA 4917 G)

5
6
7
8
9
10
11
12
13
14
15

0079-2

16
17
18

19
20

C1
C2
C3
QPFN
QUVDN
QOVDX

Ip03
IpU3
IN02
INU2

VREF2.5V

Ground
Supply Voltage
Input Positive Undervoltage 1
Input Positive Overvoltage 1
Input Negative Undervoltage 1
Input Negative Overvoltage 1
Input Positive Undervoltage 2
Input Positive Overvoltage 2
Power-Fail
Capacitor C1
Capacitor C2
Capacitor C3
Output Power-Fail
Output Undervoltage Shutdown
Output Overvoltage Shutdown
Input Positive Overvoltage 3
Input Positive Undervoltage 3
Input Negative Overvoltage 2
Input Negative Undervoltage 2
Reference Voltage

With integrated circuit TDA 4917A1G it is possible, depending on the grade of function required, to monitor a
maximum of S. + 2 independent voltages. This monitoring establishes whether preset limit values are exceeded or, at the lower end, not maintained.

@Siemens Components, Inc.

10-37

April 1988

TDA 4917 A/TDA 4917 G

Circuit Description
The following circuit description is best understood
by reference to the block diagram and timing diagrams.
PNP comparators K1 through K12 are internally connected with one input to VREF1 or VREF2 or ground.
The other input is in each case brought out on a pin.
K11 serves for monitoring the supply voltage of the
circuit itself.
Overvoltages are to trigger different functions to un- _
dervoltages, so the comparators are routed by way
of different logic circuits to the three outputs.
Three positive voltage levels, referred to ground,
with magnitudes of more than 2.5V can be detected
for overvoltage. In the same way two negative voltages, referred to ground, can be monitored for overvoltage.

Of the voltages that are to be monitored for undervoltage, likewise three can be positive (switching
threshold > 2.5V) and two can be n,egative, referred
to ground.

Comparators K6 through K12 possess switching
hysteresis on their inputs. The values for this hysteresis cal'! be matched by the sum resistance of the
external voltage divider to the particular monitoring
function.
Three different signal delay times can be freely selected within wide limits by means of three external
capacitors. The minimum delays that are possible
are obtained if pins C1 through C3 remain unwired.
When current sources· ISOURCE2, ISOURCE4 or
ISOURCES are active, the voltage on C1, C2 or C3
drops to approximately 50 mY.
The available outputs are "Overvoltage shutdown"
(Qovox), "Undervoltage shutdown" (QUVON) and
"Power-fail" (QPFN)' The "Power-fail" output (QPFN)
is Low for supply undervoltage on the device.
.'
, With the command designations in the block diagram the code is as follows:
-

X as final letter means effect for High level

- N as final letter means effect for Low level
-

Curr- -:t sources produce current when driven
High

Calculatit. T) ot -1, 1'2, 1'3:
·1 1.1·"'Is1

10-38

= Cn[nF1 x 0.83

TDA 4917 A/TDA 4917 G

Block Diagram

,----,M=;onoflop T3

C3
VREF
UVON

Vs
undervoltage

Power-fail

0079-1

••• Output QPFN shown simplified; TTL-compatible

10-39

TDA 4917 A/TDA 4917 G

Absolute Maximum Ratings*
·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Pos

Parameter

Symbol

Limits

Conditions

Units

Min

Max

-0.3

30

Maximum Ratings for Ambient Temperature TA "" - 40·C to + 85·C
1

Input Comparator K1
through K12

VIKn

2

Clamping Diodes on Inputs
of K1 through K12

IKn

3

Supply Voltage

Vs

-0.3

30

V

VC1, C2, C3

-0.3

2.5

V

VaOVDX
laOVDX

0> IOVDX> -70 mA
-0.3V > VOVDX > Vs + 0.3V

-°0.3 Vs + 0.3V
-10
+10

V
mA
V
rnA

-0.3V> VKn

V

-1

mA

4

C1, C2, C3

5

Output Overvoltage QOVDX

6

Output Undervoltage QUVDN VaUVDN
laUVDN

50 mA > IUVDN > 0
-0.3V> UUVDN

-0.3
-10

7

Output Power-Fail QPFN

50 mA > IpFN > -50 mA
-0.3V> VPFN> Vs + O.3V

-0.3 Vs + 0.3V
,-10
+10

VaPFN
laPFN

30

V
mA

Operating Range
Within the operating range the functions stated in the circuit description are fulfilled. Here deviations from the
characteristics are possible.

Pos
1

Parameter

Limits

Symbol

Supply Voltage

Vs

Units

Min

Max

4.5

+30

V

2

Input Voltage K1 through K12

VIKn

-0.3

+30

V

3

Ambient Temperature

TA

-40

+85

·C

4

Junction Temperature

Tj

125
150

·C
·C

5

Storage Temperature

Tstg

6

Thermal Resistance
System-Air

...

-AdmisSible by hmltlng useful hfe to 70,000 h.

10-40

RthSA

-60

Notes

125

·C

60
90

K/W
K/W

•
P-DIP20
SO 20

TDA 4917 A/TDA 4917 G

Characteristics
The characteristics cover the variance of the values maintained by the integrated circuit at the stated supply
voltage and ambient temperature. The typical values are average values that are expected from a manufacturing viewpoint.

Pos

Parameter

Symbol

Limits

Conditions
Min

Typ

Units
Max

Supply Voltage
4.5V < Vs < 30V
Ambient Temperature -40·C < TA < +85·C
1

Current Drain

Is

3.5

6.5

rnA

-0.5

0.5

p.A

VREF1
-10mV

VREF1
+ 10mV

V

+10

mV

VREF2
+ 10mV

V

Inputs Ip01, Ip02,Ip03, IN01,IN02, IpU1, IpU2, IpU3,INU1, INU2, IpF
2

Input Current

II

3

Switching Voltage of
Ipo,. Ip02, Ip03, IpU1, IpU2, IpU3, IpF

Vswp

4

Switching Voltage of
IN01,IN02

Uswno

5

Switching Voltage of
INU1,INU2

Vswnu

-10

0

VREF2
-10mV

Voltage Supply on Vs
6

Level on Vs for Supply
Undervoltage (Voltage Dropping)

4.5

4.6

4.7

V

Switching Hysteresis of Supply
Undervoltage (on Vs)*

90

100

110

mV

7

10

13
0.1

7

10

13
0.1

p.A
p.A
p.A
p.A

2.1

3

3.9

p.A

7

10

13

rnA

2.1

3

3.9

p.A

7

10

13

rnA

Switching Hysteresis
7

Comparators K6, K7, K8, K12
Hysteresis Current

Ihyh
Ihyl

8

Comparators K9, K10
Hysteresis Current

-Ihyh
-Ihyl

< Vswp
> Vswp
V(-K) > Vswn
V(-K) < Vswp
V(+K)
V(+K)

DelaYT1
9

Charge Current on C1
(VC1 rising)

-IC1ch

10

Discharge Current on C1
(VC1 Dropping)

IC1dis

DelaYT2
11
12

Charge Current on C2
(VC2 Rising)

Discharge Current on C2
(VC2 Dropping)
·Set with K11

-IC2ch
'C2dis

10-41

•

TDA 4917 A/TDA 4917 G

Characteristics

(Continued)
The characteristics cover the variance of the values maintained by the integrated circuit at the stated supply
voltage and ambient temperature. The typical values are average values that are expected from a manufacturing viewpoint.

Pos

Parameter

Symbol

Limits

Conditions

I

Units

Min

Typ

Max

2.1

3

3.9

/AoA

7

10

13

mA

MONOFLOPT3
13

Charge Current on C3
(Vea Rising)

14

Discharge Current on C3 leadis
(VC3 Dropping)

-leach

OUTPUT OVERVOLTAGE (QOVDX)
15

Output High

-IOVDX

Vs= 5V
VOVDX = 1V

16

Output High

VHOVDX

-IOVDX = 10 mA

40

mA

Vs -1

V

1.5

V

OUTPUT UNDERVOLTAGE (QUVDN)

17 Output Low

VLUVDN

IUVDN = 40mA

OUTPUT POWER-FAIL (QPFN)
18

Output High

-lpFN

Vs= 5V
VPFN = 1V

19

Output High·

VHPFN

-lpFN = 10mA
-lpFN = 40/AoA

20

Output Low

IpFN

VPFN = 3V

21

Output Low

VLPFN

20

30

40

V
V

Us - 2.5
Us - 1.5
20

30

40

mA

0.4

V
V

2.525

V

3

mA

10
5

mV
mV

1.5

IpFN = 10 mA
IpFN = 1.6 mA

mA

REFERENCE VOLTAGE 1 (VREFd
Voltage··

VREF1

23

Load Current

-IREF1

24

Voltage Alteration

aVREF1

25

Temperature
Response

aVREF1 /aT

26

Shortcircuit Current
(Admissable Sustained)-

Isc

22

IREF1 = 1 mA; Tamb = 25°C;
2.475
Vs = 12V

2.5

0
Vs ±20%
IREF1 ±20%
-0.3
VREF1 = OV

+0.3 mVlk
10

mA

REFERENCE VOLTAGE 2 (VREF2)
27

Voltage···

VREF2

Tamb = 25°C; Vs = 12V;
VREF1 = 2.5V

'Max. 6.5V however
"When adjusted (± 1%); without adjustment ±6%
"'VREF2 is derived by voltage divider (R1 + R2)/R2 = 25 from VREF1.

10-42

97

100

103

mV

TDA 4917 AlTDA 4917 G
Diagram

QOVDX

QPFN

QUVD

·'NO and INU are logically identical like Ipo and Ipu. but have switching levels OV.
During '/"1 QUVDN cannot go low (turn-on procedure).

0079-4

'/"2 suppresses undervoltage spikes.
'/"3 ensures minimum duration of power-fail signal (QPFN).

Ordering Information
Type

Ordering Code

Package

TDA4917 A
TDA4917G

Q67000-A8131
Q67000-A8132

P-DIP20
5020

10-43

SIEMENS

TDA 4918 A; G
Ie for Push-Pull Switched-Mode Power Supplies
with SIPMOS Driver Output
Pin Configuration

Pin Definitions

Top View
~

GNOOSIP

1[

Q SIP 1 2[

3[
[
v, s[

QSIP2
VSOSI,

~

020

GNO ov

] 19 OOpAmp/lKI
] 18 IOpAmpH
] 17 IOpAmp (+1
] 16

-/OYNKS

eMfI d'rt

6[

] 1S ./oYN KS

C,

7[

D14

R,

8~

013IUVK4

CR 9 [

0'2 I ov K 3

1St 10 [

0 11

RR

VREF
0087-1

Pin

Function

1
2
3
4
5
6
7
' 8
9
10
11
12
13
14
15
16
17
18
19

GNDQSIP
Output SIPMOS t;lriver Q SIP 1
Output SIPMOS driver Q SIP 2
Supply Voltage VS Q SIP
Supply Voltage Vs
Soft Start Csoft start
VCOCT
VCORT
Ramp Generator CR
Input Standby I St
Reference Voltage VREF
Input Overvoltage K 3
Input Overvoltage K 4
Ramp Generator RR
Input Dynamic Current Limitation K 5 (+)
Input Dynamic Current Limitation K 5 ( - )
Input Operational Amplifier ( + )
Input Operational Amplifier ( - )
Output Operational Amplifier
Q OpAmp/1 COMP K 1
GNDOV

20

This versatile switched-mode power supply control IC for the control of SIPMOS power transistors comprises
digital and analog functions. These functions are required in the design of high quality flyback and forward
converters in single-phase and push-pull operation in normal, half-bridge and full bridge circuits. The component can also be used for single-ended voltage multipliers and speed-controlled motors. Malfunctions in the
electrical operation of the switched-mode power supply are recognized by the comparators in the SMPS IC
and activate protective functions.

@Siemens Components, Inc.,

10-44

AprIl 1988

ID

0'

R-

ei

IrA

cZji;

9

3

r r I 14

Iv.

&1

~

r

~

I iI

V, aSIP

j2

QSIPI

I
I

IK llQOP 19 Input Comparator Kl
Output

..J

opamp

Input
-lOP 18 OpAmp(-)

Turn-off FF

-,

Input
.IOP 17 OpAmp(+)

~

~

1
1
1
Output a SIP 21

T

~

I
I
I

II 13

Q SIP 2

act,ve H L _________ ..J

_ _ _ _ _~

Supply Voltage + V,

___ nu.r... ' .......n+

_Reference Voltage

F

+ VREF

Input Standby (I St)

ISt= L

-I.,

IS'

= 25 ~A

1

10 lSI

I l0~F

lHrlst
Overvoltage

Soft Start
-6--CIOft.t.ln

lpF

Under-

voltage
13

;r-lov

luv

Dvn Current

limitation

15
·/OYN

,16
-/oYN

-I

0087-3

g
.a:-

....CDCD

....
o

1:

b.

Q

I

TDA 4918 A; G

Circuit Description

Comparator K 1 (Duty Cycle Control)

The various functional units of the component and
their interaction are described in the following.

The two plus inputs of the comparator are switched
such that the lower plus level is always compared
with the level of the minus input. As soon as the
voltage of the rising sawtooth edge (minus input) ~x­
ceeds the lower level of the two plus inputs, the currently active output is disabled via the turn-off flipflop. The "high" -duration of the respectively active
output can thus be infinitely varied. As the frequency
remains constant, this process corresponds to a
change in duty cycle.

Supply Voltage Vs
The IC enables the two outputs not before the turnon threshold (Vs ON) at Vs is exceeded. The duty
cycle (active time/disable time) at the enabled outputs can then rise from zero to the value set with K 1
in the time specified by the soft start.
An undervoltage at the standby input causes the
current consumption Is to remain at the very low
standby current level independent of the voltage Vs.

Voltage Controlled Oscillator (VCO)
The VCO is connected with the capacitor CT and the
resistor RT. The charge current at CT flows continuously and is set with resistor RT. The discharge current is active during the discharge of CT and is set
internally.
In the typical mode of operation the duration of the
rising edge is considerably greater than that of the
falling edge. During the falling edge the VCO passes
a trigger signal to the ramp generator thus discharging the ramp generator capacitance. Additionally,
the trigger signal is routed to other parts of the IC.

Operational Amplifier (Op Amp)
The op amp is a high quality operational amplifier. It
can be used in the control circuit to transmit the amplified variations of the voltage to be regulated to the
free plus input of comparator K 1. A voltage change
is thus converted to a duty cycle change.

Turn-Off FlipFlop
The falling edge of the VCO causes a pulse at the
turn-off flipflop set input. It can, however, only be
actually set if no reset signal is pending. With the
turn-off flipflop set, the two outputs are enabled and
one of them can be active. Upon an error signal from
K 5 or upon a ,turn-off signal from K 1 the flipflop
disables the outputs.

ZDiode
Ramp Generator
The ramp generator is controlled by the VCO and
operates at the same frequency as the VCO. The
duration of the ramp generator falling edge must be
shorter than the VCO fall time. Only then do the
ramp generator upper ,and lower switching levels
reach their rated values.
To control the pulse width at the output, the voltage
of the ramp generator rising edge is compared with
an externally adjustable dc voltage at comparator
K 1. The slope of the rising edge is adjusted via the
current by means of RR. This provides the possibility
of an additional superimposed control of the output
duty cycle. This control capability (feed-forward control) permits the compensation of known interference (e.g., input voltage ripple). A superimposed
load current control (current mode control) however, can also be implemented.

Push-Pull FlipFlop
The push-pull flipflop is switched by the falling edge
of the VCO. This ensures that only one output of the
two push-pull outputs is enabled at a time.

10-46

The Z diode limits the voltage at capacitor Csoft start
to a maximum of 5V. The ramp generator voltage
can reach 5.5V. For an appropriate slope of the rising ramp generator edge, the duty cycle can be limited to a desired maximum value. This can be a possible advantage in flyback converter operation.
~omparator

K2

The comparator has its switching threshold at 1.5V
at the plus input, and with its output sets the error
flipflop if the voltage at capacitor Csoft start is below
1.5V. The error flipflop, however, will only accept the
set pulse if no reset pulse (error) is pending. This
prevents a restart of the outputs as long as an error
signal is pending.

Soft Start
The lower of the two voltages at the K 1 plus inputs--compared with the ramp generator voltageis a measure for the duty cycle at the output. At
component turn-on, the voltage at capacitor
Csoft start is equal to OV. As long as no error exists,

TDA 4918 A; G
the capacitor will be charged to the maximum value
of 5V with a current of 6 pA
In the case of an error, Csoft start is discharged with a
current of 2 pA The currently active output, however, is immediately disabled by the error flipflop. 8eIowa charge voltage of 1.5V, a set signal is pending
at the error flipflop and the outputs are enabled if no
reset signal is pending at the same time. As the minimum ramp generator voltage, however, is 1.8V, the
duty cycle at the outputs is actually only increased
slowly and continuously after the voltage at
Csoft start exceeds 1.8V.

Standby Input (I St)
This input switches with voltage and current hysteresis. The voltage levels for switching from standby to
active operation can be set with an external voltage
divider between Vs-standby input-ground.

Reference Voltage (VREF)
The reference voltage source is a highly constant
source with regard to its temperature behavior. It
can be used for the external wiring of the op amp;
the error comparators, the ramp generator. or other
external components.

Error FlipFlop
Error signals, routed to the error flipflop reset input,
cause an immediate disabling of the output (low),
and after elimination of the error, a restart of the
component by soft start.

Comparators K 3 (Overvoltage),
VREF Overcurrent, Vs Undervoltage
These are error detectors that on error, cause the
error flipflop to immediately disable the outputs. After elimination of the error, the duty cycle is raised
again using the soft start. Upon overvoltage, a current is impressed at the input of K 3, that can be
used to enable an adjustable hysteresis or a holding
function.

Comparator K 4 (Undervoltage)
Comparator K 4 switches with an adjustable hysteresis. The value of the hysteresis is derived from the
internal resistance of the external control source
and the current impressed internally at the input of
K 4. In the undervoltage case, the set current flows
into the component in the technical direction of current flow. In the error case (undervoltage). both outputs are disabled. The component restarts by soft
start.
'

Comparator K 5 (Dynamic Current Limiter)
K 5 serves to recognize overcurrents at the switching transistors. 80th inputs of the comparator are
externally accessible. After elimination of the error,
the outputs are enabled with the VCO trigger pulse
at the turn-off flipflop. The delay time between occurrence of an error and disabling of the outputs is
only approximately 250 ns.

SIPMOS Driver Output (QSIP)
The two outputs operate in the push-pull mode.
They are active high. The duration during which one
of the outputs is active"can be varied infinitely. The
duration of the falling edge at the frequency generator is equal to the minimum duration during which
both outputs are simultaneously low.
The output driver is designed as a push-pull stage.
The output current is internally limited to the specified values.
A 10 kn resistor is connected between the output
and ground. This resistor holds the slPMOs transistor reliably disabled during standby operation (undervoltage at 1St). Output Q SIP is connected with the
supply voltage Vs Q SIP and with ground via diodes.
The diode connected to Vs Q SIP routes the capacitive shift currents from the slPMOs transistor gate
to the filter capacitor at Vs Q SIP during turning on
the sMPs supply voltage. The voltage at Vs Q SIP
can reach approximately 2.3V without the slPMOs
transistor being turned on.
The diode connected to ground connects negative
voltages at Q SIP to -0.7V. This provides an unimpeded flow off of capacitive currents occuring during
voltage breakdown at the sl,PMOs transistor drain
connection.
For supply voltages starting at approximately 2V,
both outputs are active low in the disabled state.
The function of the diode connected to Vs Q SIP is
then taken over by the pull-down source.

10-47

•

lOA 4918 A; G

Absolute Maximum Ratings·
·Stresses above thoslil listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter

Umlts

Symbol

Units

Min

Max

Vs

-0.3

33

Voltage at RT/CT

VCT, VRT

-0.3

Vcr> 6V

Icr

Supply Voltage
Inputs K 1, Op Amp, K 3, K 4, K 5,1 St

V

Frequency Generator (VCO)
6

V

3

rnA

Ramp Generator
Voltage at CR/RR

VCR,VRR

-0.3

6

V

Reference Voltage

VREF

-0.3

6

V

Output Op Amp

Vaopamp

-0.3

6

V

Driver Output Q SIP

VaSIP{I)

-0.3

6

V

Q SIP Clamp Diodes at Q SIP
Va SIP > VsorVaSIP < -0.3V

laSIP

-10

10

rnA

6

V

Junction Temperature

VCsoftstart
Tj(2)

-0.3

125

·C

Storage Temperature

Tsta

-65

Thermal Resistance TDA 4918 A
(System-Air)
TDA4918 G

RIhSA
RthSA

SottStart

125

·C

63
90

K/W
K/W

Operating Range
Supply Voltage

VS(3)

Frequency Generator (VCO)

fvee

Ramp Generator

fR

Ambient Temperature

TA

VSON

-40

30

V

300

KHz

300

KHz

85

·C

Notes:
1. With this, the maximum power dissipation or junction temperature must be taken into account!
2. At a planned maximum operating time of 70,000 hours a continuous maximum junction temperature of 150·C is permitted.
3. For Vs ON values refer to characteristic data.

Characteristics

VSON(1)

< Vs < 30V;TA =

Parameter

Symbol

-40·Cto +85·C
Limits

Conditions
Min

Typ

Units
Max

Current Consumption
Without Load at VREF
QOP, QSIP 1, 2

Is

Standby Operation

1St

Cr = 1 nF Frequency
Generator with 100 kHz

20

rnA

3.5

rnA

9.6

V

Hysteresis at Vs
Turn-On Threshold for Vs Rising

VSH

Turn-Off Threshold for Vs Falling

VSL

8.3

Von-THR;;' VOn-THR H

7.6

V

Reference Voltage
Voltage

VREF

IREF = 1 rnA
TA = 25·C
Vs = 15V

2.475

2.525

V

Load Current

-IREF

3

rnA

Voltage Change

aVREF

Vs ±200/0

10

mV

Voltage Change

aVREF

IREF ±200/0

3

mV

Temperature Response

aVREF/aT

+0.3

mV/K

10-48

0

2.5

-0.3

lOA 4918 A; G
Characteristics Vs ON(l) < Vs < 30V; TA
Parameter

= -40°C to +85°C (Continued)

Symbol

Conditions
Min

Reference Voltage (Continued)
Response Threshold for
IREF Overcurrent
Short-Circuit Current
Frequency Generator (VCO)
Frequency Range
Frequency Change
Tolerance

Charging Current for CT
(perm) = Current at Pin RT
Discharging Current for CT
CTRange(2)

lov

= OV

Isc

VREF

fvco
Aflfo
Aflfo

Vs ±20%

IRT

= 0.2nF
= 50kO
= 25°C
IRT = VREF/RT

Idch

Internally Fixed

CT
RT
TA

Units
Max

7

mA

10

rnA
300
1

KHz
%

-7

+7

%

0

1

mA

2
1000

Upper Switching Threshold

Vu

Lower Switching Threshold
Ramp Generator
Frequency Range

VI
fR

Maximum Voltage at CR

VCRH

Minimum Voltage at CR
Charging Current for CR
(perm) = Current at Pin RR
Discharging Current for CR

VCRl
Ich

VRR Approx. 0.7V

Idch

Internally Fixed

Ratio IRRIICR charge

Limits
Typ

5
2
300
5.5
1.65

IRR

= 0.5 rnA

1.8

0

-

KHz
V

1.95

V

1

mA

·3
0.95

rnA
nF
V
V

mA
1.1

Comparator K1
Input Current
2
/LA
IIKl
Turn-Off Delay Time(3) (Signal
500
ns
Transit Time Input K 1 to Q SIP)
Common-Mode Input
VIC
0
V
VCRH
Voltage Range
Operational Amplifier
Open-Loop Voltage Gain
60
80
dB
Gvo
Pin 10 n.c.
-10
Input Offset Voltage
+10
mV
VIO
Input Current
2
-II OP amp
/LA
Common-Mode Input
VIC
0
4
V
Voltage Range
Output Current
0
2
rnA
10 OP amp
Output Voltage Range
0.5
V
OmA < 10 < 2mA
Vo 00 amo
VCRH
Transition Frequency
3
MHz
fT
Transition Phase
120
degrees
T
Notes:
1. Vs ON means that Vs HIGH has been exceeded, while Vs lOW has not yet been exceeded.
2. Cr = 0.2 nF corresponds to a fall time of 0.2 /Ls (±30%) if the discharge current largely exceeds the charge current. The
fall time equals the minimum dead time at the output.
3. Step function AV = -100 mV ..f AV = + 100 mV, for transit time from input comparator to Q SIP.

10-49

•

TOA 4918 Ai G

Characteristics

VSON(l)

< Vs < 30V;TA =

Parameter,

Symbol

-40·Cto +8S·C(Continued)
Limits

Conditions
Min

Typ

Max

I

Units

Operational Amplifier (Continued)
Temperature Coefficient of VIO

TC

Source Currenl at Q Op Amp

lop amI'

-30
0.5V < Va < 5.5V

+30

/LV/K

120

/LA

SoH Start
Charging Current for Csoft start

-Ich

6

/LA

Discharging Current for Csofl start

Idch

2

/LA

Upper Limiting Voltage

VUm

5

V

VK2

1.5

V

Switching Voltage of K 2
Dynamic Current Limitation K 5
Input Current

-IIDYN

2

/LA

Input Offset Voltage

VIO

-10

+10

mV

Common-Mode Input
Voltage Range

VIC

0

Vs - 3

'V

Turn-Off Delay Time(S)

t

400

ns

Rated Load 3 nF
atQSIP

250

Undervoltage K 4
Input Current at K 4

-IIK4

Switching Voltage at K 4

Vsw

Hysteresis Current

IHy4H
IHy4l

Turn-Off Delay TIme(5)

t

VREF
-10mV
V(+K4)VSW
VI+K4)VSW

12

18

0.2

/LA

VREF
'+ 10mV

V

25
0.1

/LA
/LA

3

/Ls

0.2

/LA

VREF
+ 10mV

V

Overvoltage K 3
Input Current

-IIK3

Switching Voltage

VSw

Turn-Off Delay TIme(5)

t

Hysteresis Current

-IHy3H
-IHy3l

V(-K3) > Vsw
VI-K3)  VSON

VISIl
VI SI > VI SI H'
VISI < VISIl

Notes:
4. Dynamic maximum current during rising of falling edge.
5. Step function VREF = -100 mV.-r VREF = +100 mv} for transit time from
6. Step function AV = -100 mV.-r AV = +100 mV'
input comparator to Q SIP.

10-S0

TDA 4918 A; G

Pulse Diagram
VCT V Voltage at

t V
2

o

VI

V

rs'~

1,8

~/ ~/ \ ...

a~ CR
> V. rated > Vi

Voltage
VCR

CT

L

5

7':'i!I

V1

'/

t~

tV

ll/

Vc soft start
VIK2 (+)

o
VOl

V

Voltage at QSIP 1

t H~

I
I

1

o

VQ2 VVoltage at

t

J

VSsoft start

t

~

~

QR

~ax.

~

Possible
Duty Cycle
r-at Vlrated

O,5T
1T
1,5T
Soft Start - Error - ON/OFF

I
I

t-

vz

50

1,8

1,5

t_
0087-2

Ordering Information
Type

Ordering Code

Package

TDA491SA

Q67000-AS021

DIP 20

TDA4918 G

Q67000-AS142

50-20

10-51

SIEMENS

TDA 4919 A; G
Bipolar Ie for Single-Phase Switched-Mode
Power Supplies with SIPMOS Driver Output
Pin Conflgur!lt1on

Pin Definitions

(Top View)
GND Q SIP

1

20 GND 0 V

N.C.

2

19 Q OpAmp/1 K 1

Q SIP

3

18 I OpAmp H

V,al"

4

17

16

-/OYN K5

Clott Itart

6

15

+/DYN k5

V.

IOpAmp (+)

Cr

7

14 RR

Rr

8

131uvK4

CR

9

12 I ov K 3

I St 10

11

v...
1lO8II-1

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

GNDQSIP
N.C.
SIPMOS driver Q SIP
Supply Voltage Vs a SIP
Supply Voltage Vs
Soft Start Csofl start
VCOCr
VCORr
Ramp Generator CR
Input Standby I St
Reference Voltage VREF
Input Overvoltage K 3
'Input Overvoltage K 4
Ramp Generator RR
Input Dynamic Current Limitation K 5 ( + )
Input Dynamic Current Limitation K 5 ( - )
Input Operational Amplifier ( + )
Input Operational Amplifier ( - )
Output Operational Amplifierllnput
Comparator
GNDOV

20

This versatile single-phase switched-mode power supply control IC for the direct control of SIPMOS power
transistors comprises digital and analog functions. These functions are required in the design of high quality
flyback, forward, and choke converters with switching frequencies up to 300 kHz. The IC can also be used for
single-ended voltage multipliers and speed-controlled motors. Malfunctions in the electrical operation of the
switched· mode power supply are recognized by the comparators in the SMPS IC and activate protective
functions.

®Siemens Components, Inc.

10-52

April 1988

m
0'
n
~

C

g
iii

3

~I
I

'K 110 op 19 Input Comparator K1
Output
op amp
120JlA

..---- 6V

ICT

Supply Voltsge
Inputs K 1, OpAmp, K 3, K4, K 5,1 St

V

Frequency Generator (VCO)
6

V

3

mA

Ramp Generator
Voltage at CR/RR

VCR,VRR

-0.3

6

V

Reference Voltage

VREF

-0.3

6

V

Output Op Amp

Va op amp

-0.3

6

V

Va op amp > 6V

10 op amp

2

mA

Driver Output a SIP(!)

Va SIP

-0.3

a SIP Clamp Diodes at a SIP

10 SIP

-10

Vs
10

mA

Soft Start

VCsoftstart

-0.3

VCsoftslart > 6V
Junction Temperature

Ic soft start
Tj

Storage Temperature

TSIg

Thermal Resistance (System-Air)
TDA4919 A
TDA4919G

RIhSA
RlhSA

Va SIP> Vs or Va SIP

<

V

-0.3V

-65

6

V

100
125

/LA
·C

125

·C

63
90

K/W
K/W

Operating Range
Supply Voltage(2)

Vs

Frequency Generator (VCO)

tyco

Ramp Generator

fR

Ambient Temperature

TA

30

V

300

KHz

300

KHz

85

·C

VSON

-40

Notes:
1. With this, the maximum power dissipation or junction temperature must be taken into accountl
2. For Vs ON values refer to characteristic data.

Characteristics VSON(l) < Vs < 30V;TA = -40·Cto +85·C
Parameter

Symbol

Conditions

LImits
,Min

Typ

Units
Max

Current Consumption
Without Load at VREF
ooP,aslP

Is

Standby Operation

151

~ = 1 nF Frequency
Generator with 100 kHz

20

mA

3.5

mA

9.6

V

Hysteresis at Vs
Turn-On Threshold for Vs Rising

VSH

Turn-Off Threshold for Vs Falling

VSL

Von-THR ~ Von-THR H

8.3
7.6

V

Reference Voltage
Voltage

VREF

IREF = 1 mA
TA = 25·C
Vs = 15V

2.475

2.5

2.525

V

Load Current

-IREF

3

mA

Voltage Change

AVREF

Vs ±20%

10

mV

Voltage Change

AVREF

IREF ±20%

3

mV

10-56

0

TDA 4919 A; G

Characteristics Vs ON(l) < Vs < 30V; T A
Parameter

Symbol

= -40°C to

+ 85°C (Continued)

Conditions
Min

Reference Voltage (Continued)
Temperature Response
Response Threshold for
IREF Overcurrent
Short-Circuit Current
Frequency Generator (YCO)
Frequency Range
Frequency Change
Tolerance

-0.3

AVREF/AT
lov
ISC
fveo
Af/fo
At/fa

VREF = OV

Vs ±20%
CT = 0.2nF
RT=50kO
TA = 25°C

Charging Current for Cy
(perm) = Current at Pin RT
Discharging Current for CT
CTRange(2)

IRT

IRT = VREF/RT

Idch

Internally Fixed

Upper Switching Threshold
Lower Switching Threshold
Ramp Generator
Frequency Range
Maximum Voltage at CR
Minimum Voltage at CR
Charging Current for CR
(perm) = Current at Pin RR
Discharging Current for CR

Vu
VI

Ratio IRR/ICR charge
Comparator K 1
Input Current
Turn-Off Delay Tlme(3) (Signal
Transit Time Input K 1 to Q SIP)
Common-Mode Input
Voltage Range
Operational Amplifier
Open-Loop Voltage Gain
Input Offset Voltage
Input Current

Limits
Typ

Units
Max
+0.3

7

rnA

10

rnA
300
1

kHz
%

-7

+7

%

0

1

rnA

2
1000
5
2
300

fR
VCRH
VCRl
Ich

VRR Approx. 0.7V

Idch

Internally Fixed

1.65

IRR = 0.5 rnA

5.5
1.8

0

0.95·

GVO
VIO
-ilopamp

Common-Mode Input
Voltage Range
Output Current

VIC

Output Voltage Range

VOopamp

60
-10

0

lOop amp
OmA VSW
V(-K3) < Vsw

Output Voltage High

VaH

Output Voltage Low

Val
Val

Output Current

laslP
-laslP

= -300mA
= +300 mA
= +10mA
CaslP = 10nF

7

10

3

/J-s

13
0.1

IJ-A
IJ-A

2.1
1.4

Output Driver Q SIP
laslP

V

Vs - 3

500
300

700
500

V
V
mA(4)
mA(4)

6.3

6.9

7.5

V

5.6

6.2

6.8

V

35

50

2
65

p.A
p.A

laslP
laslP

Input Standby I St
Turn-On Threshold for
VI St Rising

VIStH

Turn-Off Threshold for
VIStFailing
Hysteresis Current

VIStl
-IHyStH
IHyStl

Vs> VSON

VISt> VIStH
VISt < VIStl

Notes:
4. Dynamic maximum current during rising of falling edge.
5. Step function VREF = -100 mV - ' VREF = + 100 mv} for transit time from
6. Step function I:N = -100 mV - ' aV = + 100 mV
Input comparator to a SIP.

10-S8

,

TDA 4919 A; G

Pulse Diagram

Vc ..fta.... ~

Z

fH

0

O+r~~~~~~~~-+~~~,-~--

1
I

I

3 4 5

DutV Cvcle

9 10 11 12 13 14 15.

-t

(active/disabled)

1 2

-t
0088-4

0088-2

Ordering Information
Type

Ordering Code

Package

TDA4919 G

067000-A8018

SO-20L

TDA4919 A

067000-A8143

P-DIP 20

•
10-59

SIEMENS

TLE 4950
Current Monitoring IC
• Input Currents Max. 25 /J-A, Meaning That
Protective Resistors Can Be Connected in
Series

• Input-Voltage Range Up to 32V,
Independent of Supply Voltage

• Range of Supply Voltage 4.5V to 32V

• Switching Threshold of Comparators
Dependent on Supply Voltage,
Corresponding to the Characteristic of
Lamps

• DIP 14 or SO 14 Package (TLE 4950 T)

• Temperature Range -40°C to

• Effective Protection against Destruction by
Voltage Surges in Automobiles

Pin Configuration

+ 125°C

Pin Definitions

(Top View)

I [ ......, PI4
Z[
PI]
J [
pl2
4[
p"
5 [
pIa
,[
P'
7 [
Oe
0110-8

Pin

Symbol

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14

01
A1
81
02
A2
82
Os
03
A3
83
04
A4
84
Vs

Output 1
Input A1
Input 81
Output 2
Input A2
Input 82
GND
Output 3
InputA3
Input 83
Output 4
Input A4
Input 84
Supply Voltage

This integrated circuit serves to monitor the performance of circuits, in particular the functioning of filament
lamps in automobiles. The IC comprises four identical comparator stages, the logic function of which corresponds to an exclusive-OR gate. With each comparator, it is possible to monitor pairs of lamps or single lamps
by means of the voltage drops across shunt resistors (Rs) in the positive supply line (See Application Circuits 1
and 2).
The inputs and outputs are protected internally by zener diodes. Protective resistors (Rp) can be connected in
series because of small differential input currents. This provides a high degree of protection against destruction by the interfering voltages produced in an automobile.

@Siemens Components. Inc.

10-60

April 1988

TLE 4950
Current Monitoring of:

Block Diagram

• Filament Lamps

Vs

• Electric Motors
• Relays
01

• Glow Plugs

A1
81

• Circuits
Especially Suitable for:
• Automotive Electronics

02

• Industrial Plants

A2
82

Circuit Description
The IC incorporates four identical comparator circuits. Each of these functional blocks has two equivalent inputs and an open-collector output Q. If the
voltages differ by more than approximately 15 mV,
the status changes from H (off-state) to L (on-state).

03
A3
83

For an input voltage of <7V on both inputs the output can go H independent of the differential input
voltage.

04
A4
84

For an input voltage of <2:5V the output is securely
off-state.

05
0110-2

10-61

TLE 4950

Absolute Maximum Ratings·
Maximum ratings are absolute ratings; exceeding
even one of these values may cause irreversible
damage to the integrated circuit.
Maximum ratings for ambient temperature T A of
-40·C to + 125·C.

·Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Supply Voltage (Vs) .....•........ -0.5Vto +32V

Operating Range

Input Voltages (VA, B) ............. -0.5V to + 32V

In the operating range the functions given in the circuit description will be fulfilled. However, deviations
from the characteristics are possible.

Output Voltages (Vo) ............. -0.5V to + 32V
Current through Protective Structures:
On Inputs A, B
(t < 2 ms) (ISA,B) ........ - 200 mA to + 200 mA
On Inputs A, B
(t < 200 ms) (ISA B) ........ -50 mA to + 50 mA
On Supply Pin Vs
'
(t < 2 ms) (Isvs) ......... - 600 mA to + 600 mA
On Output 0
(t < 2 ms) (Iso) ......... -400 mA to +400 mA

Supply Voltage (Vs) .................. 4.5V to 32V
Ambient Temperature (TA>

..•.•. -

40·C to + 125·C

Common-Mode Input Range (VGI)
(Independent of Vs) ................. 7V to 32V

Voltage Surges Permissible Short-Term with Series
Resistors Rp:
+ VA,B,VS,O = ISA,B,VS,O X RpA,B,VS,O + 32V
- VA,B,VS,O = -ISA,B,VS,O X RpA,B,VS,O .

Characteristics
Characteristics are ensured over the operating range of the integrated circuit at the given supply voltage. and
ambient temperature. Typical characteristics specify mean values expected over the production spread.
SupplyVoltage;Vs = 10Vt016V,AmbientTemperature;TA = -30·Cto +110·C

Parameter
Current Consumption
01 = 02 = 03 = 04
01 = 02 = 03 = 04

Symbol

=H
=L

Switching Threshold
with Rp = 1k; Vs = 13.5V
withoutRp
Vs = 13.5V

Test
Circuit

Limits
Min

Typ

Units
Max

Is
1

3

7
4

14

B

mA
mA

20
12

mV
mV

VDiff·
VDiff·

2
1

Input Current
VA = VB

IA,B

1

25

p.A

Output Saturation Voltage
10 = 30mA

VOL

1

0.4

V

Output Leakage Current
VOH = 32V

10H

1

10

p.A

10-62

B

TLE 4950
Diagrams
AV(mV)
28

i

26

24
22

20

18
16
14
12
10

8
6
4

=

I!"v 2.6 + 1.95 Rp + 0.4 Vs + 0.3 Rp Vs
(~V in mV, Rp in

kn, Vs in V)
1 .5

16
Vs(V)_
0110-1

Differential Switching Voltage ~V = f(Supply Voltage Vs)
Parameter:

Protective Resistors On
Inputs RpA,B

The above function approximates to the function "Current Consumption vs. Supply Voltage" of a gas·filled tungsten
filament lamp commonly found in automobiles.

Test Circuit 1

•

0110-3

10·63

TLE 4950

Test Circuit 2

0110-4

Application Circuits
Difference Measurement
+ '2 V (vehicle elKtncal system)
RS

RPQ

Lamp Currents Same:
Q = H
Lamp Currents Not Same: Q = L

'0110-5

Absolute-Value Measurement
+ 12 V (vehicle electrical system)

RS

Lamp Ok:
Q = L
Lamp Defective: Q = H
RPB

0110-8

Recommended Protective Resistors: RPA, B = 1 kO
RPVS = 1000
RPQ~ 5000

10-64

TLE 4950

Application Circuits

(Continued)

Voltage Supply Separate from Vehicle Supply
+ 12 V (vehlde electrical system)
r----'---<>
RS

4.S
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