1988_Siliconix_Integrated_Circuits_Data_Book 1988 Siliconix Integrated Circuits Data Book
User Manual: 1988_Siliconix_Integrated_Circuits_Data_Book
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General Information . Process Option Flows •
Selector Guide _
Cross Reference
Analog Switches and Multiplexers
Data Conversion
III
III
D
WidebandNideo _
Special Functions _
Display Drivers . .
Power Conversion
II!I
ASIC
ID
Packaging
Applications
Publications Index
Worldwide Sales Offices and Distributors
lEI
III
III
III
1988
INTEGRATED CIRCUITS
DATA BOOK
trW"
~
Siliconix
incorporated
..... Siliconix
incorporated
~
SlIIconlx Incorporated reserves the rIght to make changes In the cIrcuItry or
specIfIcatIons at any tIme wIthout notIce and assumes no responsIbility for the use
of any cIrcuIts descrIbed hereIn and makes no representatIons that they are free
from patent InfrIngement.
WarnIng RegardIng LIfe Support ApplicatIons
SlIIconlx products are not sold for applicatIons In any medIcal equIpment Intended for use as a
component of any life support system unless a specIfic wrItten agreement pertaInIng to such
Intended use Is executed between the manufacturer and SlIIconlx. Such agreement will requIre
the equIpment manufacturer eIther to contract for addItIonal reliability testIng of the SlIIconlx
parts and/or to commIt to undertake such testIng as a part of Its manufacturIng process. In
addItIon, such manufacturer must agree to IndemnIfy and hold SlIIconlx harmless from any
claIms arisIng out of the use of the SlIIconlx parts In life support equIpment.
Stresses listed under· Absolute Maximum RatIngs· may be applied (one at a tIme) to
devices wIthout resultIng In permanent damage. ThIs Is a stress ratIng only and not subject
to productIon testIng. Exposure to absolute maxImum ratIng condItIons for extended perIods
may effect devIce reliability.
@1988 SlIIconlx Incorporated
Printed In U.S.A.
WY Siliconix
~
incorporated
SILICONIX
INTEGRATED CIRCUITS
For over 25 years, Siliconix, has been a leading supplier of small-signal FETs,
power MOSFETs, and a broad selection of analog integrated circuits (ICs). With
worldwide corporate and manufacturing headquarters in Santa Clara, California,
Siliconix also has manufacturing facilities in Wales, Hong Kong and Taiwan.
The IC products detailed in this data book include analog switches and mUltiplexers, data converters, wide band/video switches and multiplexers, display
drivers, power conversion ICs, and special function ICs and analog/digital gate
arrays. These products are designed for applications in the industrial, computer
peripherals, communications, and military markets. Siliconix serves these customers with products of unequaled performance, quality and reliability through
the use of our leading design, processing, packaging and testing technologies.
The product specifications listed in this data book are arranged in a new, simplified format. The electrical tables and performance curves contain detailed information, simplifying the tasks of design and component engineers. Each of the
data sheets has been controlled by the Siliconix quality assurance organization
which guarantees that all limits stated are fully tested in production.
We solicit your comments and suggestions, and look forward to continually serving your future analog integrated circuit requirements.
~
~
Siliconix
incorporated
About This Edition of the
Siliconix Integrated Circuit Data Book
NEW PRODUCT DATA SHEETS APPEARING FOR THE FIRST TIME:
PART NUMBER
DESCRIPTION
PAGE NUMBER
ANALOG SWITCHES AND MULTIPLEXERS
DGP201A
DGP303A
DG400-405
DG408/409
DG411/412/413
DG417/418/419
DG421/423/425
DG441/442
DG444/445
DG480
DG485
DGP508A
DG548/549
DG566
DG601
DG908/909
Precision Quad Analog Switch (A/S) •...............•••....
Precision Dual SPDT A/S • • . . . . . . . . • . . . . . . . . . . . . . . . • . . . • .•
High Performance A/S . • . • . . . . . . • . . . . • • . • . . . . . . . . . • . . . . ..
High Performance 8-ChannellDifferential 4-Channel
Multiplexers (MUX) ..••......•..•..•.•...................
High Performance Quad A/Ss •• • . • • • • . • • • . • . • . • . . . . . . . • • .•
High Performance Mini DIP Switches .........•.............
High Performance Dual A/Ss With Latches ....•.........•...
Improved Si-Gate Quad A/Ss (DG201 A/202 Upgrade) .•.•.....
Improved Si-Gate Quad A/Ss (DG211/212 Upgrade) .•.•..••.•
8-Channel Switch Array ..•.• . . • . . . • . . . • . . . . • . • . . • . • . . • • .•
8-Channel Low-Power Switch Array .•........•....•.....•.•
Precision 8-Channel MUX ..•....•.....•..................
8-Channel/Differential 4-Channel Overvoltage Protected MUXs ..
Serial-loading Octal High-Voltage A/S ..................••..
Low Charge High-Speed Quad A/S ..•.•........•....•..•..
8-ChannellDifferential 4-Channel Fault-Protected MUXs . . . . • • ..
5-102
5-173
5-212
5-229
5-234
5-245
5-255
5-265
5-274
5-282
5-288
5-314
5-369
5-375
5-407
5-414
DATA CONVERSION INTEGRATED CIRCUITS
Si2504
Si7240
Si7533
Si7541
Si7541A
Si7542
Si7543
Si7545
Si7820
Si8603
Si8604
High Speed CMOS Successive Approximation Register •••.•.•.. 6-22
12-Bit Voltage-Output DAC ....•.•.....•.•.....•..•........ 6-43
10-Bit CMOS Multiplying DAC ......•......•.•.......•.•.... 6-51
12-Bi! CMOS Multiplying DAC (MDAC) •.....•.•.•..•......... 6-58
12-Bit CMOS Multiplying DAC ....•.......•..•....••.•..•... 6-67
12-Bit CMOS MDAC With 4-Bit Latches .......•.......•.•.... 6-76
12-Bit CMOS MDAC With Serial Input . . . . . . . . . . . . . . . . . . . . . . .. 6-90
12-Bit CMOS MDAC With Latches •..••.........•..•.....•.• 6-104
8-Bit Half Flash A/D Converter ..............•......•...••. 6-120
8-Bit AID Converter With Sample/Hold ..................•.. 6-130
8-Bit A/D Converter With Sample/Hold ...•..............•.. 6-141
WIDEBANDIVIDEO INTEGRATED CIRCUITS
DG534
DG535
DG536
DG538
DG540
DG541
DG542
4-Channel WidebandlVideo MUX .••.••••..................•. 7-3
16-Channel WidebandlVideo MUX (DIP-28) •.•••..•••.•....... 7-21
16-Channel WidebandlVideo MUX (PLCC-44) ...••............ 7-34
8-ChannellDual 4-Channel WidebandlVideo MUX ••..•.•....... 7-47
Quad WidebandlVideo "T" Switch (20 Lead) ..•...••••....•.. 7-65
Quad WidebandlVideo "T" Switch (16 Lead) ..•...........••. 7-70
Dual SPDT WidebandlVideo "T" Switch .•.•....•........•.... 7-75
...... 5i1iconix
incorporated
~
NEW PRODUCT DATA SHEETS APPEARING FOR THE FIRST TIME (Cont'd)
DESCRIPTION
PART NUMBER
PAGE NUMBER
SPECIAL FUNCTIONS
0470
SI7652
Octal Driver/Buffer Switch Array . . • . . . . . . • . • . . . • . . • . • . • • . . .. 8-29
Low-Noise Chopper-Stabilized Op-Amp ....•••.....••.•••.... 8-56
DISPLAY DRIVERS
Si9560
Electroluminescent Symmetric Row Driver ....•.•...........• 9-27
ASIC
IS05
15-Volt Analog/Digital Gate Arrays .••.•.......•..•.........• 11-3
POWER CONVERSION
519100/5i9101
Si9102
Si9110/S19111
5i9115/Si9116
1-Watt. High-Voltage Switchmode Regulators ................
1-Watt. High-Voltage Switch mode Regulator ....••••.........
High-Voltage Switchmode Controllers ....••.•...•.•..•.•••..
Off-Line 5witchmode Controllers . • • . • • . • • . . . . . • • . . • • . • . • . .•
DISCONTINUED/NEW UPGRADE CROSS REFERENCE:
PART NUMBER
0123
DF320/320A
DF322A
DF331/332
DF820
DG151/153
DG152/154
DG161/163
DG162/164
DG200
DG201
·DG300-308
DG381-390
DG491
DG506-509
DG5240.2,4
DG5241.3.5
G115-117
G122/123
PWM25
PWM27
PMW125
Si25HC04
5i8020/21
AVAILABILITY/REPLACEMENT/UPGRADE
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
DG200A
DG201A. DGP201A. DG441
DG300A-308A
DG381A-390A
Note 1
DG506A-509A
Note 1
DG421/423/425
Note 2
Note 2
Note 1
Note 1
Note 1
Si2504
Note 1
NOTES:
1. Obsolete product.
2. Contact factory on availability.
10-16
10-26
10-35
10-43
.... Siliconix
incorporated
~
TABLE OF CONTENTS
Section 1.
General Information
Device Ordering Information • . • . . • . . • . • . . . . . . . . . • • . . . . • • . • . . • • • . . • • • . • . • . • • • . •• 1-1
Die Ordering Information . . . . . . • . . . . • • . . . • . • • . • . . . . • • . . . . . . • . • • . . . . . • . • . • . . • . .. 1-3
BS9000 Ordering Information •.•....•..•........•....••...••.••••••.••..••.•.•. 1-5
JAN38510 Ordering Information ..•.............•..•••.•.•.•......••..•.•...•••. 1-6
Standard Military Drawing (SMD) .••...•.••.••.••..•••.•.•••.•.•..••.•..•.•.•••. 1-8
Burn-In Connections .•...•••.•.••.•..•.........•....••.•.••.•••.•••..•••.••• 1-12
Section 2.
Process Option Flows
Process Option Flow Charts ••...•....•...... . . . • . . . . . . . . • . . • . • • . • • • . • . • . . • . • .• 2-1
Section 3.
Selector Guide .................................................... 3-1
Section 4.
Cross Reference ............................. ; ..................... 4-1
.Section 5.
Analog Switches and Multiplexers
Table of Contents
Introduction .••....••.•..•••.•••...•..•.....•..•••.•.•••.•.•..•••.•.•.•..•.• 5-1
DG123: 5-Channel SPST PMOS Analog Switch •..•.....••..•..•.•...••••.•.•..••.. 5-8
DG125: 5-Channel SPST PMOS Analog Switch • • . • . . • . • • • • . . . • • • . • . • • . . • . • • • . . • •. 5-11
DG126/129/140: Dual DPST JFET Analog Switches ...•....•.•.••.•.•....•.•...••• 5-15
DG133/134/141: Dual SPST JFET Analog Switches ...•.•••..•.•..•...•.••..•.•••• 5-22
DG139/142/145: Dual DPDT JFET Analog Switches .•........••.•.•..•.•.••..••..• 5-30
DG143/144/146: SPOT JFET Analog Switches •..•.....••.•.••••.••••••.•••.••••• 5-38
DG172: Monolithic 4-Channel PMOS Analog Switch .........••..•.•....•.•.•.....• 5-46
DG180/181/182: High-Speed Driver with Dual SPST JFET Switches •.••••.•..••.••••. 5-51
DG183/184/185: High-Speed Driver with Dual DPST JFET Switches ..•••..•...•.....• 5-62
DG186/187/188: High-Speed Driver with SPDT JFET Switch •...•...•..•.•.....•..•. 5-74
DG189/190/191: High-Speed Driver with Dual SPDT JFET Switches ••.••.•..••...•... 5-85
DG200A: Dual Monolithic SPST CMOS Analog Sy.-itch •..••••.•..•••••.•..•.•.••.•. 5-96
DGP201A: Precision Monolithic Quad SPST CMOS Analog Switch •••..•.•.....•.•.. 5-102
DG201 A/202: Quad Monolithic SPST CMOS Analog Switches . . • • • • • • . • . • . . • . . . . • .. 5-117
DG211/212: Low Cost 4-Channel Monolithic SPST CMOS Analog Switches ••.••....• 5-129
DG221: 4-Channel Monolithic SPST CMOS Analog Switch with Data Latches ....•.... 5-143
DG243: Monolithic General Purpose CMOS Analog Switch .•...••.••..••••.•.....• 5-151
DG271: High-Speed Quad Monolithic SPST CMOS Analog Switch •.••••••.•..•••.•• 5-156
DG300A/301A/302A/303A: CMOS Analog Switches •.•.•.•••..••••.••.•.••...••• 5-161
DPG303A: Precision Dual SPDT CMOS Analog Switch ••.•.••••.•••••...•..•...•.. 5-173
DG304A/305A/306A/307A: CMOS Analog Switches ...•.•..•...•....•..•.....••.. 5-184
DG308A/309: Quad Monolithic SPST CMOS Analog Switches ..••••.•..•••...•.•... 5-195
DG381A/384A/387A/390A: General Purpose CMOS Analog Switches ••.•.•...•.•••. 5-201
DG400-405: Low-Power - High-Speed CMOS Analog Switches ••..••..•••..•..•..• 5-212
DG408/409: 8-Channel/Dual 4-Channel High Performance
CMOS Analog Multiplexers ....•.•..•........•.......•••..••...•••.•••..•. 5-229
DG411/412/413: Precision Monolithic Quad SPST CMOS Analog Switches ••..•...... 5-234
DG417/418/419: Precision MiniDIP CMOS Analog Switches •.•.•..•...••.•••.•.••. 5-245
DG421 1423/425: Low-Power - High-Speed Latchable CMOS Analog Switches ...•..•. 5-255
fI"1T Siliconix
~
Section 5.
incorporated
Analog Switches and Multiplexers (Cont'd)
DG441 1442: Monolithic Quad Switches SPST CMOS Analog Switches .•...••...•.••.
DG444/445: Monolithic Quad SPST CMOS Analog Switches .......•...•..•....••..
DG480: High-Speed CMOS Octal Analog Switch Array .•.•..•.•......•.....•.••..
DG485: Low-Power - High-Speed CMOS Octal Analog Switch Array ...•............
DG501: 8-Channel Multiplex Switch with Decode .,. . . . . . . . . . . . . • • . . . . . . . . . . . . . .•
DG503: 8-Channel Multiplex Switch with Decode ......•......•.•......•..•...•..
DG506A/507A: 16-Channel/Dual 8-Channel CMOS Analog Multiplexers .•.••......•..
DGP508A: Precision 8-Channel CMOS Multiplexer/Demultiplexer •..•.•.••..•••••..•
DG508A/509A: 8-Channel/Dual 4-Channel CMOS Analog Multiplexers .......••..•...
DG526/527: 16-Channel and Dual 8-Channel Latchable Multiplexers ........•..•....
DG528/529: 8-Channel and Dual 4-Channel Latchable Multiplexers ...•.•...•...•...
DG548/549: 8-Channel and Dual 4-Channel CMOS Analog Multiplexers with
Overvoltage protection ••.••...••••.•....•..•.••.•.........•.•...•...•...
DG566: Serial-Loading Octal SPST High-Voltage Analog Switch .•..•.•.•••••..•..••
DG568/569: 8- and Dual 4-Channel High-Voltage CMOS Multiplexers with Latches ...•
DG5040-5045: Monolithic General Purpose CMOS Analog Switches .••..••.•.......
DG5140/5141 1514215143/5144/5145: Low-Power - High-Speed CMOS
Analog Switches ••...•.•..........•...•.......•...•..•.••......•.••....
DG601: High-Speed Quad SPST CMOS Analog Switch •.•.•..••.•.•.•.•....••.••.
DG908/909: 8-Channel/Dual 4-Channel Fault Protected CMOS Analog Multiplexers .•.•
Gl18: Monolithic 6-Channel Enhancement-Type MOSFET Switch •...••.••.•..•.••••
Gl19: Monolithic 6-Channel Enhancement-Type MOSFET Switch ••..•.•.•.•..••.•.•
Si3002: Monolithic SPDT MOS Switch with Driver ••..•.•.•..•.•..•.••.........••.
Section 6.
5-265
5-274
5-282
5-288
5-294
5-299
5-303
5-314
5-331
5-345
5-357
5-369
5-375
5-381
5-389
5-398
5-407
5-414
5-419
5-422
5-425
Data Conversion .
Table of Contents
Introduction ................................................................. 6-1
LDll 0/111 A: 3 1/2-Digit AID Converter Set • . . . . • . . . . • . . • • . . • • • • • • . . • • . . • . . . • • . •• 6-4
LD120/121A: 4 1/2-Digit AID Converter Set .••••..•••.••.•.•.••••.•••••..••....• 6-10
LD122/121A: 4 1/2-Digit AID Converter Set .•..•..•••..•.•••••.••.•.•••...••..•• 6-16
Si2504: High Speed 12-Bit SAR •..•••••.••...•••.••.•••..•..•.....••.••..•.••. 6-22
Si7135: Precision 4 1/2-Digit Single Chip CMOS AID Converter .••.....••...•..•••. 6-31
Si7240: 12-Bit CMOS Voltage-Output DAC ••.•.••..••••••.•.••.••..•...•..••.••. 6-43
Si7533: CMOS 10-Bit Multiplying DAC .••.••••.•••.•...••.••.•••.•.•.••••...•.•. 6-51
Si7541: CMOS 12-Bit Multiplying DAC .......................................... 6-58
Si7541 A: CMOS 12-Bit Multiplying DAC • . . • . • . . • . . . • • . . • . . . • • • . . • . . . • . • . . • • • • . .. 6-67
Si7542: Microprocessor-Compatible 12-Bit CMOS Multiplying DAC •••..•...•......•. 6-76
Si7543: CMOS 12-Bit Serial Input DAC .........••.••...••..••...............•.. 6-90
Si7545: CMOS 12-Bit Buffered Multiplying DAC ...•.•...•..•....•...•.........•. 6-104
Si7820: CMOS Subranging 8-Bit AID Converter .••.•..•....•.••....•.•••..••••.• 6-120
S18601/03: 8-Bit Data Acquisition Systems ........••........•.••........•••..•• 6-130
Si8602/04: 8-Bit Data Acquisition Systems ...................................... 6-141
Section 7.
WidebandNideo
Table of Contents
Introduction •..••••.•....••.•...••...•......•••.••....••.....•.....•.•....•• 7-1
DG534: 4-Channel/Dual 2-Channel WidebandlVideo Multiplexer ••.••..•..•....••••••• 7-3
DG535: 16-Channel WidebandlVideo Multiplexer ••...••.•..••.•....•.••••.•....•• 7-21
DG536: l6-Channel WidebandlVideo Multiplexer •. ; •.•..•.•.••••.•....•.........• 7-34
..,. Siliconix
incorporated
~
Section 7.
WidebandlVideo (Cont'd)
DG538: 8-Channel/Dual 4-Channel WidebandlVideo Multiplexer .....................
DG540: Quad SPST WidebandlVideo "T" Switch ................•................
DG541: Quad SPST WidebandlVideo "T" Switch .................................
DG542: Dual SPOT WidebandlVideo "T" Switch ......•..........................
SD5000/5001/5002: DMOS FET Quad Analog Switch Arrays .......................
SD5400/5401/5402: DMOS FET Quad Analog Switch Arrays ......•................
Section 8.
7-47
7-65
7-70
7-75
7-81
7-88
Special Functions
Table of Contents
Introduction ................................................................ 8-1
0125: Monolithic 6-Channel FET Switch Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
0129: 4-Channel MOSFET Switch Driver with Decode .............................. 8-6
0139: Monolithic 2-Channel FET Switch Driver ........................•........... 8-9
0169: Dual High-Voltage Driver ............................................... 8-13
0469: Quad High-Current Power Driver . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .. 8-23
0470: Low-Power - High-Speed Octal CMOS Driver with Serial Interface ............. 8-29
L144: Low-Power Triple Operational Amplifier ..........•....•................... 8-35
L 161: Micropower Quad Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-41
Si7250: Bubble Memory Power Driver .......................................... 8-52
Si7652: Chopper Stabilized Operational Amplifier ..................•..•.......... 8-56
Si8901: Ring Demodulator/Balanced Mixer ...................................... 8-67
Section 9.
Display Drivers
Table of Contents
Introduction ...........................................•....•............... 9-1
DF412: 4-Digit LCD Decoder/Driver ............................................. 9-2
Si9551/9552: Electroluminescent Row Drivers ................................... 9-12
Si9553/9554/9555/9556: Electroluminescent Column Drivers ....................... 9-18
Si9560: Electroluminescent Symmetric Row Driver ...............•...•........... 9-27
Section 10.
Power Conversion
Table of Contents
Introduction ...........................................................•..• 10-1
Si7660: Monolithic CMOS Voltage Converter .............................•...... 10-2
Si7661: Monolithic CMOS Voltage Converter .................................... 10-9
Si91 00/91 01: 1-Watt. High-Voltage Switchmode Regulators ....................... 10-16
Si9102: 1-Watt. High-Voltage Switchmode Regulator ............................ 10-26
Si9110/9111: High-Voltage Switch mode Controllers ...........•................. 10-35
Si9115/9116: OFF-Line Switchmode Controllers ........••...........•......•.•.. 10-43
Section 11.
ASIC
Introduction ............................................................... 11-1
IS05: HCMOS Gate Array Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . .. 11-3
Section 12.
Packaging
Table of Contents
Plastic DIP (J. N Suffix). 8-16 Leads ....................................•.•....
Plastic DIP (J. N Suffix). 24-48 Leads . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • • . . . . . . . . . ..
Plastic DIP (J. N Suffix). 24 Leads. 0.3" Narrow Body ............................
CerDIP (K. Q Suffix). 14-20 Leads ...............................•............
CerDIP (K. Q Suffix). 24-40 Leads. 0.6" Wide Body ......................•.......
12-1
12-2
12-3
12-4
12-5
~
~
Section 12.
Siliconix
incorporated
Packaging (Cont'd)
Side Braze DIP (P, 0 Suffix), 14-24 Leads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-6
Side Braze DIP (P, R, 0 Suffix) 24-48 Leads, 0.6" Wide Body ..................... 12-7
SO Package (Y Suffix), 8-16 Leads ............................................ 12-8
SO Package (Y Suffix), 16-28 Leads, Wide Body ................................ 12-9
PLCC Package (N, P Suffix), 20-84 Leads ........................... . • . . . . . . .. 12-10
CerQuad Package (M Suffix), 28 & 44 Leads ......•.•......................... 12-11
CLCC Package (M Suffix), 44 Lead .......................................... 12-12
LCC Package (Z, E Suffix), 20 & 28 Leads .................................... 12-13
Flat Package (L Suffix), 14 Lead, Obsolete Version ............................. 12-14
Flat Package (L Suffix), 14 & 16 Leads ....................................... 12-15
MO-002AG (Formerly TO-78) ............................................... 12-16
MO-002AK (Formerly TO-99) ................................................ 12-17
MO-006AD (Formerly TO-100) .............................................. 12-18
Section 13.
Applications
Table of Contents
AN88-2: Microprocessor Compatible Multiplexers Facilitate
Video Switching Designs ..............................'................... 13-1
AN88-1: Applications For the 0469 - A High Current Power Driver ................. 13-24
AN87-4: Improve System Precision with the Si7652 Chopper-Stabilized
Optional Amplifier ...................................................... 13-29
AN87 -3: The Si7541 A 12-Bit CMOS Multiplying DAC Theory and Applications ........ 13-41
AN87-2: Efficient ISDN Power Converters Using the Si9100 ....................... 13-67
AN87 -1: A 1-Watt Flyback Converter Using the Si9100 . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-74
AN86-1: The DG535/536 Wideband Multiplexer Suits a Wide Variety
of Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-85
AN84-2: Theory and Applications of the Si7660 and Si7661 Voltage Converters ..... 13-102
AN83-14: A Simple Approach to Si7135/8085 Interfacing ........................ 13-114
AN83-13: Si8601 Data Acquisition System Interfaces for I/O or
Memory Mapped Operation ............................................. 13-122
AN83-7: A High Quality Audio Crosspoint Switch ............................... 13-128
AN83-6: A System Solution to HP-IL Equipment Interface ....................... 13-131
AN83-4: Improved System Performance Using Microprocessor
Compatible Multiplexers ................................................ 13-138
AN83-3: A Microprocessor Compatible Analog Switch Makes Interfacing Easy ...... 13-151
AN83-1: The DG308A Digitally Switches Analog Signals ......................... 13-157
AN76-7: Function/Application of the L161 Micropower Comparator ................ 13-165
AN76-6: DG300A Series Analog Switch Applications . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-173
AN75-1: CMOS Analoq Switches - A Powerful Design Tool ...................... 13-189
AN74-2: Analog Switches in Sample and Hold Circuits .......................... 13-206
AN73-6: Function/Application of the L144 Programmable Micropower
Triple Op Amp ... , .................................................... 13-214
AN73-2: IC Multiplexer IncreE!ses Analog Switching Speeds ...................... 13-221
TA87-1: Eliminate the Guesswork in Your Analog Switching Error Analysis ......... 13-227
TA73-1: Multiplexer Adds Efficiency to 32-Channel Telephone System ............. 13-232
Section 14.
Publications Index ............................................... 14-1
Section 15.
Worldwide Sales Offices and Distributors . ......................... , . 15-1
'7
..r Siliconix
incorporated
~
ALPHA-NUMERIC INDEX
D125 •...
D129 •...
D139 ....
D169 ....
D469 •...
D470 ••..
DF412 ...
DG123 ...
DG125 ...
DG126 ...
DG129 •.•
DG133 ...
DG134 ...
DG139 ...
DG140 ..•
DG141 •.•
DG142 ..•
DG143 .•.
DG144 ...
DG145 .••
DG146 .••
DG172 .•.
DG180 .•.
DG181 .••
DG182 .•.
DG183 .•.
DG184 ..•
DG185 •..
DG186 •..
DG187 .•.
DG188 ...
DG189 ...
DG190 .•.
DG191 •.•
DG200A ..
DG201A ..
DG202 • "
DG211 ...
DG212 ...
DG221 ..•
DG243 ..•
DG271 ...
8-3
8-6
8-9
8-13
8-23
8-29
9-2
5-8
5-11
5-15
5-15
5-22
5-22
5-30
5-15
5-22
5-30
5-38
5-38
5-30
5-38
5-46
5-51
5-51
5-51
5-62
5-62
5-62
5-74
5-74
5-74
5-85
5-85
5-85
5-96
5-117
5-117
5-129
5-129
5-143
5-151
5-156
DG300A •. 5-161
DG301A .. 5-161
DG302A .. 5-161
DG303A .. 5-161
DG304A .. 5-184
DG305A .. 5-184
DG306A .. 5-184
DG307A •. 5-184
DG308A .. 5-195
DG309 '" 5-195
DG381A .. 5-201
DG384A .. 5-201
DG387 A .. 5-201
DG390A .. 5-201
DG400 ... 5-212
DG401 · .. 5-212
DG402 · .. 5-212
DG403 · .. 5-212
DG404 · .• 5-212
DG405 · .. 5-212
DG408 ... 5-229
DG409 ... 5-229
DG411 ..• 5-234
DG412 .•. 5-234
DG413 ... 5-234
DG417 ... 5-245
DG418 ••. 5-245
DG419 ... 5-245
DG421 · •• 5-255
DG423 · •. 5-255
DG425 .•. 5-255
D<3441 ... 5-265
DG442 .•. 5-265
DG444 '" 5-274
DG445 '" 5-274
DG480 ..• 5-282
DG485 ... 5-288
DG501 .•. 5-294
DG503 ... 5-299
DG526 ... 5-345
DG527 ... 5-345
DG528 .•. 5-357
DG529
DG534
DG535
DG536
DG538 .
DG540
DG541
DG542
DG548
DG549
DG566
DG568
DG569
DG601
DG908
DG909
DG5040
DG5041
DG5042
DG5043
DG5044
DG5045
DG506A
DG507A
DG508A
DG5140
DG5141
DG5142
DG5143
DG5144
DG5145
DGP201A
DGP303A
DGP508A
G118 ....
G119 •.•.
IS05 ....
L144 ....
L161
LD110 ..•
LD111 A •.
LD120 ...
·.
·
·.
·.
·.
....
5-357
7-3
7-21
7-34
7-47
7-65
7-70
7-75
5-369
5-369
5-375
5-381
5-381
5-407
5-414
5-414
5-389
5-389
5-389
5-389
5-389
5-389
5-303
5-303
5-331
5-398
5-398
5-398
5-398
5-398
5-398
5-102
5-173
5-314
5-419
5-422
11-3
8-35
8-41
6-4
6-4
6-10
LD121A ..
LD122 ...
SD5000 ..
SD5001 •.
SD5002 ..
SD5400 ..
SD5401 .•
SD5402 ..
Si2504 • ..
Si3002 • ..
Si7135 • ..
Si7240 . ..
Si7250 . ..
Si7533 ...
Si7541 •..
Si7541 A ..
Si7542 ...
Si7543 . ..
Si7545 ..•
Si7652 . ..
Si7660 . ..
Si7661 ...
Si7820 •..
SiB601 .••
Si8602 ...
Si8603 ...
Si8604 ...
SiB901 ...
Si9100 .•.
Si9101 .,.
Si9102 ...
Si9110 ...
Si9111 ...
Si9115 ...
Si9116 •..
Si9551 ..•
Si9552 ..•
Si9553 . ..
Si9554 . ..
Si9555 . •.
Si9556 • ..
Si9560 . ..
6-10,6-16
6-16
7-81
7-81
7-81
7-88
7-88
7-88
6-22
5-425
6-31
6-43
8-52
6-51
6-58
6-67
6-76
6-90
6-104
8-56
10-2
10-9
6-120
6-130
6-141
6-130
6-141
8-67
10-16
10-16
10-26
10-35
10-35
10-43
10-43
9-12
9-12
9-18
9-18
9-18
9-18
9-27
.-F' 8i1iconix
~
incorporated
NUMERIC-ALPHA INDEX
1805 ....
LOll0 ...
LOlllA ..
Gl18 ....
Gl19 ....
L0120 ...
L0121A ..
L0122 ...
OG123 ...
0125 ....
OG125 ...
OG126 ...
0129 ....
OG129 ...
OG133 ...
OG134 ...
0139 ....
OG139 ...
OG140 ...
DG141 ...
DG142 .,.
OG143 ...
DG144 ...
L144 ....
OG145 ...
OG146 ...
L161 . ...
0169 ....
DG172 ...
DG180 ...
OG181 ...
DG182 ...
OG183 ...
OG184 ...
OG185 ...
OG186 ...
OG187 ...
OG188 ...
OG189 ...
OG190 ...
OG191 ...
OG200A ..
11-3
6-4
6-4
5-419
5-422
6-10
6-10, 6-16
6-16
5-8
8-3
5-11
5-15
8-6
5-15
5-22
5-22
8-9
5-30
5-15
5-22
5-30
5-38
5-38
8-35
5-30
5-38
8-41
8-13
5-46
5-51
5-51
5-51
5-62
5-62
5-62
5-74
5-74
5-74
5-85
5-85
5-85
5-96
OG201A .. 5-117
OGP201 A . 5-102
OG202 ... 5-117
OG211 ... 5-129
OG212 ... 5-129
OG221 ... 5-143
OG243 ... 5-151
OG271 · .. 5-156
OG300A .. 5-161
OG301A .. 5-161
OG302A .. 5-161
OG303A .. 5-161
OGP303A . 5-173
OG304A .. 5-184
OG305A .. 5-184
OG306A .. 5-184
OG307A .. 5-184
OG308A .. 5-195
OG309 ... 5-195
OG381A .. 5-201
DG384A .. 5-201
DG387 A .. 5-201
DG390A .. 5-201
OG400 ... 5-212
OG401 · .. 5-212
OG402 · .. 5-212
OG403 ... 5-212
OG404 ... 5-212
OG405 ... 5-212
DG408 ... 5-229
OG409 ... 5-229
OG411 ... 5-234
OF412 ... 9-2
OG412 ... 5-234
OG413 ... 5-234
OG417 ... 5-245
OG418 ... 5-245
OG419 ... 5-245
OG421 ... 5-255
OG423 ... 5-255
OG425 ... 5-255
OG441 ... 5-265
·
OG442
.
OG444 · .
OG445 · .
0469 ....
0470 ....
OG480
OG485 · .
OG501 · .
OG503 · .
OG506A
OG507A
OG508A
OGP508A
OG526
OG527 .
OG528
OG529
OG534
OG535 · .
DG536 ·
OG538 .
OG540
OG541 · .
OG542 · .
OG548 · .
OG549 · .
OG566 · .
OG568 .
OG569
OG601 · .
DG908 · .
OG909 · .
8i2504 .
8i3002 · .
805000 ..
805001 ..
805002 ..
OG5040
OG5041
OG5042
OG5043
OG5044
·.
·.
·
·.
·.
·.
.
·
·.
·
·.
·
5-265
5-274
5-274
8-23
8-29
5-282
5-288
5-294
5-299
5-303
5-303
5-331
5-314
5-345
5-345
5-357
5-357
7-3
7-21
7-34
7-47
7-65
7-70
7-75
5-369
5-369
5-375
5-381
5-381
5-407
5-414
5-414
6-22
5-425
7-81
7-81
7-81
5-389
5-389
5-389
5-389
5-389
OG5045 ..
OG5140 ..
OG5141 ..
OG5142 ..
OG5143 ..
OG5144 ..
OG5145 ..
805400 ..
805401 ..
805402 ..
8i7135 ...
8i7240 . ..
8i7250 . ..
8i7533 ...
8i7541 ...
8i7541 A ..
8i7542 ...
8i7543 . ..
8i7545 ...
8i7652 . ..
8i7660 . ..
8i7661 ...
8i7820 . ..
8i8601 ...
8i8602 ...
8i8603 . ..
8i8604 ...
8i8901 ...
8i9100 ...
8i9101 ...
8i9102 ...
8i9110 ...
8i9111 ...
8i9115 ...
8i9116 ...
8i9551 ...
8i9552 . ..
8i9553 . ..
8i9554 . ..
8i9555 . ..
8i9556 . ..
8i9560 . ..
5-389
5-398
5-398
5-398
5-398
5-398
5-398
7-88
7-88
7-88
6-31
6-43
8-52
6-51
6-58
6-67
6-76
6-90
6-104
8-56
10-2
10-9
6-120
6-130
6-141
6-130
6-141
8-67
10-16
10-16
10-26
10-35
10-35
10-43
10-43
9-12
9-12
9-18
9-18
9-18
9-18
9-27
"-I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
General Information . .
Siliconix
incorporated
H
DEVICE ORDERING INFORMATION
Integrated Circuits and Power ICs
DG
DG
DG
Device Family
T
Device Number
187
303
506
A
A
A
B
C
P
K
1883
-4
J
T
Device Revision (when used)
Operating Temperature Range
Package
Process Option
DEVICE FAMILY
(1, 2, or 3 Letters)
D
DF DG DGP G
L
LD SD SI
-
Drivers for FET Switches
Digital Function
Analog Switches and Analog Multiplexers
Precision Analog Switch
Multi-Channel FETs
Linear
Linear Digital Combinations
SlIIconlx DMOS Product
SlIIconlx Proprietary Integrated Circuit or
Second Source Part
SJ M - QPL Listed Part
DEVICE NUMBER
(3 or 4 Digit Numbers)
PACKAGE
(1 Letter)
A
H
J
K
L
M
N
P
R
Y
Z
-
Metal Can
Eight Pin Mini Dip-Plastic
Dual-In-Line Package-Plastic
Dual-In-Line Package-CERDIP
Flat Package
Ceramic J Bend Quad (CLeC)
PLCC
Dual-In-Line Package-Side Braze
Dual-In-Line Package-Side Braze
Small Outline Package (SOIC)
Leadless Chip Carrier (LCC)
PROCESS OPTION
Processing to the current revision of MIL-STD-663,
Level B. Compliant-Non JAN
-2 - Non Compliant-Non JAN"
-4 - 160 Hour Burn-In
IBS - BS9000 Compliant
1883 -
OPERATING TEMPERATURE RANGE
(1 Letter)
A -55 to 1250 C
B
C
D
-25 to 85 0 C
0 to 70 0 C
-40 to 85 0 C
" Many older -2 processed parts are now upgraded to
1863 process flows.
Band D temperature range parts receive Industrial processing
unless a process option dash number Is added to the part
number.
C temperature range parts are given commercial processing.
All possible combinations of device types, temperature
ranges, package types and MIL-883 process options are not
necessarily available. Consult Individual data book pages or
sales office for complete Information.
Note: Please refer to the following page for data acquisition
nomenclature.
1-1
..... Siliconix
,,6;11 incorporated
Data Acquisiton
Si
7545
T
Device Family
G
u
T
Device Number
Gain Error Designator (optional)
Temperature Range and Grade
Package
Process Option
TEMPERATURE RANGE
GRADE
PACKAGE
(1 Letter)
-40 to 85°C
-40 to 85 0 e
-40 to 85°C
Good
Better
Best
o to 70°C
o to 70°C
o to 70°C
0
E
N
P
Q
Good
Better
Best
S -55 to 1250 e
T -55 to 125°C
U -55 to 125°C
Good
Better
Best
(1 Letter)
A
B
C
J
K
L
1-2
-
Side Braze DIP
Lee
Plastic DIP
PLCC (Plastic Quad J-Bend)
CERDIP
D
1883
(or 883)
~
Siliconix
.t£II incorporated
DIE ORDERING INFORMATION
MONOLITHIC CHIPS
Example:
DG
201
A
TL
A
DICE
Form
Screening Criteria
Device Revision (If/when used)
Device Number
III
Device Family
DEVICE FAMILY
SCREENING CRITERIA
(1, 2 or 3 Leiters)
(1 LETTER)
D
DG DGP G
L
Si -
Drivers for FET Switches
Analog Switches
Precision Analog Switch
Multi-Channel FETs
Linear
Siliconix Proprietary or Second Source Part
DEVICE NUMBER
A - Electrically probed @ 25°C; visual criteria
screening to MIL-STD-883, Method 2010
Condition B.
- Electrically probed @ 25°C; visual criteria
screening to Siliconix Specification 501 B.
FORM
(4 Leiters)
(3 or 4 Digit Numbers)
DICE
- Chips waffle packaged per Figure 1 in
Die Process Information
MULTICHIP
OPTIONS
To order die which form multichip devices the driver
chip and corresponding JFETs should be ordered using the geometry designations as shown in Table 1.
The following options are considered .. special" and a
special part number will be assigned:
Example: For DG190 die, order
CMJB1000
and NC1000
To determine number of JFETs required to go with
each driver in a multichip device, see number in parenthesis following geometry codes as shown in
Table 1.
1. Die in wafer form
2. Gold Backing on Integrated Circuit dice
3. Class A visual
4. Customer visual criteria
Please identify as .. similar to _ _ _ _ _ _with
following additional conditions _ _ _ _ _ _ __
1-3
B
Table 1
Sillconix
Plfj NQ.
1-4
Geometry Code
Drivir
FE!
TechnQIQ9Y
DG126
LODC1000
NC2000(4)
JFET Switch
DG129
LODC1000
NC1000(4)
JFET Switch
DG133
LODC1000
NC1000(2)
JFET Switch
DG134
LODC1000
NC2000(2)
JFET Switch
DG139
LODF1000
NC1000(4)
JFET Switch
DG140
LODC1000
NIP1000(4)
JFET Switch
DG141
LODC1000
NIP1000(2)
JFET Switch
DG142
LODF1000
NC2000(4)
JFET Switch
DG143
LODF1000
NC2000(2)
JFET Switch
DG144
LODF1000
NC1000(2)
JFET Switch
DG145
LODF1000
NIP1000(4)
JFET Switch
DG146
LODF1000
NIP1000(2)
JFET Switch
DG180
CMJB1000
NIP1000(2)
JFET Switch
DG181
CMJB1000
NC1000(2)
JFET Switch
DG182
CMJB1000
NC20PO(2)
JFET Switch
DG183
CMJA1000
NIP1000(4)
JFET Switch
DG184
CMJA1000
NC1000(4)
JFET Switch
DG185
CMJA1000
NC2000(4)
JFET Switch
DG186
CMJC1000
NIP1000(2)
JFET Switch
DG187
CMJC1000
NC1000(2)
JFET Switch
DG188
CMJC1000
NC2000(2)
JFET Switch
DG189
CMJB1000
NIP1000(4)
JFET Switch
DG190
CMJB1000
NC1000(4)
JFET Switch
DG191
CMJB1000
NC2000(4)
JFET Switch
Siliconix
incorporated
.-r 8i1iconix
incorporated
~
8S9000 ORDERING INFORMATION
ANALOG SWITCHES AND MULTIPLEXERS
BS9000 Part Numbering System
I
I
DG181
I I I I I
A
P
BS
S2
Screening Level
Device Type Number
BS9000 Approval
I
I
Package
Temperature Range
A -55 to 125°C
I
A
P, R
K
Metal Can
8idebraze
CerDIP
Available Parts
Ordering Part No.
DG181AAB882
DG185APB8 82
DG187APB8 82
DG189APB882
DG190APB882
DG191APB882
DG200AAAB8 82
DG200AAKB8 82
Ordering Part No.
Ordering Part No.
DG300AAAB8
DG300AAKB8
DG301 AAAB8
DG301 AAKB8
DG302AAKB8
DG303AAKB8
DG304AAAB8
DG305AAAB8
DG307 AAKB8
DG308AAKB8
DG384AAKB8 82
DG390AAKB8 82
82
82
82
82
82
82
82
82
82
82
DG506AAKB8
DG507 AAKB8
DG508AAKB8
DG509AAKB8
82
82
82
82
Contact one of the 8i1iconix sales offices for latest information.
1-5
Ir'F Siliconix
~
incorporated
,JAN38510 ORDERING INFORMATION
ANALOG SWITCHES AND MULTIPLEXERS
Several Siliconix Analog Switches and multiplexers are available fully certified on the QPL (Qualified Parts List)
published monthly by befense Electronics Supply Center (DESC). The QPL numbers follow this format:
JM38510/XXXXX. Refer to the current Siliconix Price list for available part types and order numbers.
JAN Part Numbering System
J
- --
M38510 1111 07 B E C
r-- • r- "r- ••••
"JAN" Certification Mark
Military Designator
Lead Finish
-
I
A--Solder Dip
C--Gold Plate
Detail Specification (Slash Sheet)
Series
1116--DG300A Series
1123--0G200A Series
1190--DG506 . Series
1111--DG181
Case Outline
C--14-Lead Side Braze
L----I E--1S-Lead Side Braze
1--l0-Lead Metal Can
A--14-Lead Flatpack
Device Type
01-013181
02-0G182
03-0G184
04-0G185
05-0G187
06-0G188
07-0G190
08-0G191
01-0G300A
02-0G301A
03-0G302A
04-0G303A
05-0G304A
06-0G305A
07-0G30SA
08-0G307A
1123
01-0G200A
02-0G201A
1190
01-0G50SA
03-0G507A
07-0G508A
08-0G509A
1111
1116
Device Class
S--Class S
B--Class B
Available JAN Parts
Generic ParI Number
1-6
JAN ParI Number
Order ParI Number
OG181AP/883
OG181AP/883
DG181AA/883
OG181ALl883
JM38510/11101BCC
JM3851 0/111 01 BCA
JM38510/11101BIC
JM38510/11101BAC
SJM181BCC
SJM181BCA
SJM181BIC
SJM181BAC
OG182AP/883
OG182AP/883
OG182AA/883
OG182AL/883
JM3851 0/111 02BCC
JM38510/11102BCA
JM38510/11102BIC
JM3851 0/111 02BAC
SJM182BCC
SJM182BCA
SJM182BIC
SJM182BAC
OG184AP/883
OG184AP/883
OG184ALl883
JM38510/11103BEC
JM38510111103BEA
JM38510/11103BAC
SJM184BEC
SJM184BEA
SJM184BAC
DG185AP/883
OG185AP/883
DG185AL/883
JM38510111104BEC
JM38510/11104BEA
JM38510/11104BAC
SJM185BEC
SJM185BEA
SJM185BAC
~
~
Siliconix
incorporated
Available JAN Parts (continued)
Generic Part Number
JAN Part Number
DG187AP/883
DG187AP/883
DG187AA/883
DG187AL/883
JM38510/11105BCC
JM38510/11105BCA
JM38510/11105BIC
JM3851 0/111 05BAC
Order Part Number
SJM187BCC
SJM187BCA
SJM187BIC
SJM187BAC
DG188AP/883
DG188AP/883
DG188AA/883
DG188ALl883
JM38510/11106BCC
JM38510/11106BCA
JM38510/11106BIC
JM38510/11106BAC
SJM188BCC
SJM188BCA
SJM188BIC
SJM188BAC
DG190AP/883
DG190AP/883
DG190ALl883
JM38510/11107BEC
JM38510/11107BEA
JM38510/11107BAC
SJM190BEC
SJM190BEA
SJM190BAC
DG191AP/883
DG191AP/883
DG191AL/883
JM38510/11108BEC
JM3851 0/111 08BEA
JM3851 0/111 08BAC
SJM191BEC
SJM191BEA
SJM191BAC
DG200AAP/883
DG200AAP/883
DG200AAAl883
JM38510/12301BCC
JM38510/12301BCA
JM3851 0/12301 BIC
SJM200BCC
SJM200BCA
SJM200BIC
DG201AAP/883
DG201AAP/883
JM38510/12302BEC
JM38510/12302BEA
SJM201BEC
SJM201BEA
DG300AAP/883
DG300AAP/883
DG300AAA/883
JM38510/11601BCC
JM3851 0/11601 BCA
JM38510/11601BIC
SJM300BCC
SJM300BCA
SJM300BIC
DG301AAP/883
DG301AAP/883
DG301AAA/883
JM38510/11602BCC
JM38510/11602BCA
JM38510/11602BIC
SJM301BCC
SJM301BCA
SJM301BIC
DG302AAP/883
DG302AAP/883
JM38510111603BCC
JM38510111603BCA
SJM301BCC
SJM301BCA
DG303AAP/883
DG303AAP/883
JM38510/11604BCC
JM38510/11604BCA
SJM303BCC
SJM303BCA
DG304AAP/883
DG304AAP/883
DG304AAA/883
JM38510/11605BCC
JM38510/11605BCA
JM38510/11605BIC
SJM304BCC
SJM304BCA
SJM304BIC
DG305AAP/883
DG305AAP/883
DG305AAA/883
JM38510/11606BCC
JM38510111606BCA
JM38510/11606BIC
SJM305BCC
SJM305BCA
SJM305BIC
DG306AAP/883
DG306AAP/883
JM38510111607BCC
JM38510/11607BCA
SJM306BCC
SJM306BCA
DG307AAP/883
DG307AAP/883
JM38510/11608BCC
JM38510/11608BCA
SJM307BCC
SJM307BCA
DG506AAR/883
DG507AAR/883
DG508AAP/883
DG508AAP/883
DG509AAP/883
DG509AAP/883
JM38510/19001BXC
JM38510/19003BXC
JM38510/19007BEA
JM38510/19007BEC
JM38510/19008BEA
JM38510/19008BEC
SJM506BXC
SJM507BXC
SJM508BEA
SJM508BEC
SJM509BEA
SJM509BEC
III
1-7
trY' Siliconix
~
incorporated
STANDARD MILITARY DRAWING (SMD)
/883 Compliant/Non JAN
Class B
Siliconix offers products which meet requirements of MIL-STD-883 paragraph 1.2.1 "Provisions for the use of
MIL-STD-883 in conjunction with compliant non-JAN devices."
SMD CompliantINon JAN
SMD/DESC Part #
7705201EA
7705201EC
770520FC
7705301EA
7705301EC
7801401CA
7801401CC
81 00601 EA
81006011C
8100602EA
81006021C
8100603EA
81006031C
8100604EA
8100605EA
81006051C
8100606EA
8100609EA
81006091C
8100610EA
8100610lC
8100611EA
81006111C
8100612EA
8100613EA
81006131C
8100614EA
Generic Part #
DG508AAK DESC
DG508AAK DESC
DG508AAL DESC
DG201AAK DESC
DG201AAP DESC
DG129AP DESC
DG129AP DESC
DG5140AK DESC
DG5140AA DESC
DG5141AK DESC
DG5141AA DESC
DG5142AK DESC
DG5142AA DESC
DG5143AK DESC
DG5144AK DESC
DG5144AA DESC
DG5145AK DESC
DG5140AK DESC
DG5140AA DESC
DG5141AK DESC
DG5141AA DESC
DG5142AK DESC
DG5142AA DESC
DG5143AK DESC
DG5144AK DESC
DG5144AA DESC
DG5145AK DESC
Class B
1883 CompliantINon JAN
Industry Part #
Sillconix Part #
Industry Part #
AD7506JD/883
AD7507JD/883
AD7541ASD/883
AD7541ATD/883
AD7545SD/883
AD7545TD/883
DG506AAR/883
DG507AAR/883
SI7541 ASD/883
SI7541 A TD/883
SI7545SD/883
SI7545TD/883
AD7545UD/883
AH0126D/883
AH0129D/883
AH0133D/883
AH0134D/883
AH0139D/883
SI7545UD/883
DG126AP/883
DG129AP/883
DG133AP/883
DG134AP/883
DG139AP/883
1-8
Silicon Ix Part #
Industry Part #
Silicon Ix Part #
AH0140D/883
AH0141D/883
AH0143D/883
AH0144D/883
AH0145D/883
AH0146D/883
DG140AP/883
DG141AP/883
DG143AP/883
DG144AP/883
DG145AP/883
DG146AP/883
AH0163D/883
AH0164D/883
DGM184AK/HR
DGM184AK/883B
DGM185AK/HR
DGM185AK/883B
DG145AP/883
DG139AP/883
DG405AK/883
DG405AK/883
DG405AK/883
DG405AK/883
AH0151D/883
AH0152D/883
AH0153D/883
AH0154D/883
AH0161D/883
AH0162D/883
DG141AP/883
DG133AP/883
DG140AP/883
DG129AP/883
DG146AP/883
DG144AP/883
DGM190AK/HR
DGM190AK/883B
DGM191AK/HR
DGP201AAK/883
DGP201AAZ/883
DGP303AAK/883
DG403AK/883
DG403AK/883
DG403AK/883
DGP201AAK/883
DGP201 AAZ/883
DGP303AAK/883
.-r
~
Siliconix
incorporated
Class 8
1883 Compliant/Non JAN (Cont'd)
Industry Part #
Silicon Ix Part #
Industry Part #
Silicon Ix Part #
Industry Part #
Siliconix Part #
DGP303AAZ/883
DGP508AAK/883
DGP508AAZ/883
DG123AL
DG123AL-2
DG123ALlHR
DGP303AAZ/883
DGP508AAK/883
DGP508AAZl883
DG123ALl883
DG123ALl883
DG123ALl883
DG141AL
DG141AL-2
DG141ALlHR
DG141ALl883
DG141AP-2
DG141AP/883
DG141ALl883
DG141ALl883
DG141ALl883
DG141ALl883
DG141AP/883
DG141AP/883
DG163AL-2
DG163ALl883
DG163AP-2
DG163AP/883
DG164AL-2
DG164ALl883
DG145ALl883
DG145ALl883
DG145AP/883
DG145AP/883
DG139ALl883
DG139ALl883
DG123ALl883
DG123AP-2
DG123AP/HR
DG123AP/883
DG125AL
DG125AL-2
DG123ALl883
DG123AP/883
DG123AP/883
DG123AP/883
DG125ALl883
DG125ALl883
DG142AL
DG142AL-2
DG142ALlHR
DG142ALl883
DG142ALl883B
DG142AP-2
DG142ALl883
DG142ALl883
DG142ALl883
DG142ALl883
DG142ALl883
DG142AP/883
DG164AP-2
DG164AP/883
DGl72AL
DG172AL-2
DG172ALl883
DG180AA-2
DG139AP/883
DG139AP/883
DGl72ALl883
DGl72ALl883
DGl72ALl883
DG180AA/883
DG125ALlHR
DG125AL/883
DG125AP-2
DG125AP/HR
DG125AP/883
DG126AK/HR
DG125ALl883
DG125ALl883
DG125AP/883
DG125AP/883
DG125AP/883
DG126AP/883
DG142AP/883
DG143AL
DG143AL-2
DG143ALlHR
DG143AL/883
DG143ALl883B
DG142AP/883
DG143ALl883
DG143ALl883
DG143ALl883
DG143ALl883
DG143ALl883
DG180AA/883
DG180AL
DG180AL-2
DG180ALl883
DG180AP-2
DG180AP/883
DG180AA/883
DG180ALl883
DG180ALl883
DG180AL/883
DG180AP/883
DG180AP/883
DG126AL
DG126AL-2
DG126AL/HR
DG126AL/883
DG126ALl883B
DG126AP-2
DG126ALl883
DG126ALl883
DG126ALl883
DG126ALl883
DG126ALl883
DG126AP/883
DG143AP-2
DG143AP/883
DG144AL
DG144AL-2
DG144ALlHR
DG144ALl883
DG143AP/883
DG143AP/883
DG144ALl883
DG144ALl883
DG144ALl883
DG144ALl883
DG181AA-2
DG181AA/883
DG181AL
DG181AL-2
DG181ALl883
DG181AP-2
DG181AA/883
DG181AA/883
DG181AL/883
DG181AL/883
DG181ALl883
DG181AP/883
DG126AP/883
DG129AL
DG129AL-2
DG129ALlHR
DG129AL/883
DG129AL/883B
DG126AP/883
DG129ALl883
DG129ALl883
DG129ALl883
DG129AL/883
DG129ALl883
DG144ALl883B
DG144AP-2
DG144AP/883
DG145AL
DG145AL-2
DG145ALl883
DG144ALl883
DG144AP/883
DG144AP/883
DG145ALl883
DG145ALl883
DG145ALl883
DG181AP/883
DG182AA-2
DG182AA/883
DG182AL
DG182AL-2
DG182ALl883
DG181AP/883
DG182AA/883
DG182AA/883
DG182ALl883
DG182ALl883
DG182ALl883
DG129AP-2
DG129AP/883
DG133AL
DG133AL-2
DG133AL/HR
DG133ALl883
DG129AP/883
DG129AP/883
DG133AL/883
DG133ALl883
DG133ALl883
DG133ALl883
DG145AP-2
DG145AP/883
DG146AL-2
DG146ALl883
DG146AP-2
DG146AP/883
DG145AP/883
DG145AP/883
DG146ALl883
DG146AL/883
DG146AP/883
DG146AP/883
DG182AP-2
DG182AP/883
DG183AL
DG183AL-2
DG183ALl883
DG183AP-2
DG182AP/883
DG182AP/883
DG183ALl883
DG183ALl883
DG183ALl883
DG183AP/883
DG133AL/883B
DG133AP-2
DG133AP/883
DG134AL
DG134AL-2
DG134ALlHR
DG133ALl883
DG133AP/883
DG133AP/883
DG134AL/883
DG134ALl883
DG134ALl883
DG151AL-2
DG151ALl883
DG151AP-2
DG151AP/883
DG152AL-2
DG152ALl883
DG141AL/883
DG141AL/883
DG141AP/883
DG141AP/883
DG133ALl883
DG133ALl883
DG183AP/883
DG184AL
DG184AL-2
DG184AL/883
DG184AP-2
DG184AP/883
DG183AP/883
DG184ALl883
DG184ALl883
DG184ALl883
DG184AP/883
DG184AP/883
DG134ALl883
DG134ALl883B
DG134AP-2
DG134AP/883
DG139AL
DG139AL-2
DG134ALl883
DG134ALl883
DG134AP/883
DG134AP/883
DG139ALl883
DG139ALl883
DG152AP-2
DG152AP/883
DG153AL-2
DG153ALl883
DG153AP-2
DG153AP/883
DG133AP/883
DG133AP/883
DG140ALl883
DG140ALl883
DG140AP/883
DG140AP/883
DG185AL
DG185AL-2
DG185ALl883
DG185AP-2
DG185AP/883
DG186AA-2
DG185ALl883
DG185ALl883
DG185ALl883
DG185AP/883
DG185AP/883
DG186AA/883
DG139AL/HR
DG139ALl883
DG139ALl883B
DG139AP-2
DG139AP/883
DG140AL
DG139ALl883
DG139ALl883
DG139ALl883
DG139AP/883
DG139AP/883
DG140ALl883
DG154AL-2
DG154ALl883
DG154AP-2
DG154AP/883
DG161AL-2
DG161 ALl883
DG129ALl883
DG129ALl883
DG129AP/883
DG129AP/883
DG146ALl883
DG146AL/883
DG186AA/883
DG186AL
DG186AL-2
DG186ALl883
DG186AP-2
DG186AP/883
DG186AA/883
DG186ALl883
DG186ALl883
DG186ALl883
DG186AP/883
DG186AP/883
DG140AL-2
DG140AL/HR
DG140AL/883
DG140AP-2
DG140AP/HR
DG140AP/883
DG140ALl883
DG140ALl883
DG140ALl883
DG140AP/883
DG140AP/883
DG140AP/883
DG161AP-2
DG161AP/883
DG162AL-2
DG162ALl883
DG162AP-2
DG162AP/883
DG146AP/883
DG146AP/883
DG144AL/883
DG144ALl883
DG144AP/883
DG144AP/883
DG187AA-2
DG187AA/883
DG187AL
DG187AL-2
DG187ALl883
DG187AP-2
DG187AA/883
DG187AA/883
DG187ALl883
DG187ALl883
DG187ALl883
DG187AP/883
1-9
III
IrY" Siliconix
~
incorporated
Class B
1883 Compliant/Non JAN (Cont'd)
Industry Part #
SlIIconlx Part #
Industry Part #
Silicon Ix Part #
DG187AP/883
DG188AA-2
DG188AA/883
DG188AL
DG188AL-2
DG188ALl883
DG187AP/883
DG188AA/883
DG188AA/883
DG188ALl883
DG188ALl883
DG188AL/883
DG301AAK-2
DG301AAK/883
DG301AAZ/883
DG302AAK-2
DG302AAK/883
DG303AAK-2
DG301AAK/883
DG301AAK/883
DG301AAZ/883
DG302AAK/883
DG302AAK/883
DG303AAK/883
DG501AP-2
DG501AP/883
DG503AP-2
DG5040AK-2
DG5040AK/883
DG5041AK-2
DG501AP/883
DG501AP/883
DG503AP/883
DG5040AK/883
DG5040AK/883
DG5041 AK/883
DG188AP-2
DG188AP/883
DG189AL
DG189AL-2
DG189ALl883
DG189AP-2
DG188AP/883
DG188AP/883
DG189ALl883
DG189ALl883
DG189ALl883
DG189AP/883
DG303AAK/883
DG303AAZ/883
DG304AAA-2
DG304AAA/883
DG304AAK-2
DG304AAK/883
DG303AAK/883
DG303AAZl883
DG304AAA/883
DG304AAA/883
DG304AAK/883
DG304AAK/883
DG5041AK/883
DG5042AK-2
DG5042AK/883
DG5043AK-2
DG5043AK/883
DG5044AK-2
DG5041AK/883
DG5042AK/883
DG5042AK/883
DG5043AK/883
DG5043AK/883
DG5044AK/883
DG189AP/883
DG190AL
DG190AL-2
DG190ALl883
DG190AP-2
DG190AP/883
DG189AP/883
DG190ALl883
DG190ALl883
DG190ALl883
DG190AP/883
DG190AP/883
DG305AAA-2
DG305AAA/883
DG305AAK-2
DG305AAK/883
DG30SAAK-2
DG30SAAK/883
DG305AAA/883
DG305AAA/883
DG305AAK/883
DG305AAK/883
DG30SAAK/883
DG30SAAK/883
DG5044AK/883
DG5045AK-2
DG5045AK/883
DG5048AK/883
DG5049AK/883
DG5050AK/883
DG5044AK/883
DG5045AK/883
DG5045AK/883
DG5048AK/883
DG5049AK/883
DG5050AK/883
DG191AL
DG191AL-2
DG191ALl883
DG191AP-2
DG191AP/883
DG200AAA-2
DG191ALl883
DG191ALl883
DG191ALl883
DG191AP/883
DG191AP/883
DG200AAA/883
DG307AAK-2
DG307AAK/883
DG307AAZ/883
DG308AAK-2
DG308AAK/883
DG309AK-2
DG307AAK/883
DG307 AAK/883
DG307AAZ/883
DG308AAK/883
DG308AAK/883
DG309AK/883
DG5051AK/883
DG50SAAK-2
DG50SAAK/883
DG50SAAR-2
DG50SAAR/883
DG50SAAZ/883
DG5051AK/883
DG50SAAK/883
DG50SAAK/883
DG50SAAR/883
DG50SAAR/883
DG50SAAZ/883
DG200AAA/883
DG200AAK-2
DG200AAK/883
DG200AAP-2
DG200AAP/883
DG201AAK-2
DG200AAA/883
DG200AAK/883
DG200AAK/883
DG200AAP/883
DG200AAP/883
DG201AAK/883
DG309AK/883
DG381AAA-2
DG381AAA/883
DG381AAK-2
DG381AAK/883
DG384AAK-2
DG309AK/883
DG381 AAA/883
DG381AAA/883
DG381AAK/883
DG381AAK/883
DG405AK/883
DG507AAK-2
DG507AAK/883
DG507AAR-2
DG507AAR/883
DG507AAZ/883
DG508AAK-2
DG507AAK/883
DG507AAK/883
DG507AAR/883
DG507AAR/883
DG507 AAZ/883
DG508AAK/883
DG201AAK/883
DG201AAZ/883
DG201AK/883
DG202AK-2
DG202AK/883
DG221AK-2
DG201AAK/883
DG201AAZ/883
DG201AAK/883
DG202AK/883
DG202AK/883
DG221AK/883
DG384AAK/883
DG387AAA-2
DG387 AAA/883
DG387AAK-2
DG387AAK/883
DG390AAK-2
DG405AK/883
DG387AAA/883
DG387AAA/883
DG387AAK/883
DG387AAK/883
DG403AK/883
DG508AAK/883
DG508AAZ/883
DG509AAK-2
DG509AAK/883
DG509AAZ/883
DG5140AK/883
DG508AAK/883
DG508AAZ/883
DG509AAK/883
DG509AAK/883
DG509AAZ/883
DG5140AK/883
DG221AK/883
DG243AK-2
DG243AK/883
DG271AK-2
DG271AK/883
DG271AZ/883
DG221AK/883
DG243AK/883
DG243AK/883
DG271AK/883
DG271AK/883
DG271AZ/883
DG390AAK/883
DG400AK/883
DG401AK/883
DG401AZ
DG401AZ/883
DG402AK/883
DG403AK/883
DG400AK/883
DG401AK/883
DG401 AZ/883
DG401 AZ/883
DG402AK/883
DG5141AK/883
DG5142AK/883
DG5143AK/883
DG5144AK/883
DG5145AK/883
DG534AP/883
DG5141AK/883
DG5142AK/883
DG5243AK/883
DG5144AK/883
DG5145AK/883
DG534AP/883
DG281AA-2
DG281AAl883
DG281AP-2
DG281AP/883
DG284AP-2
DG284AP/883
DG181AA/883
DG181AA/883
DG181AP/883
DG181AP/883
DG184AP/883
DG184AP/883
DG403AK/883
DG403AZ
DG403AZ/883
DG404AK/883
DG405AK/883
DG405AZ
DG403AK/883
DG403AZ/883
DG403AZ/883
DG404AK/883
DG405AK/883
DG405AZ/883
DG535AP/883
DG53SAM/883
DG538AP/883
DG540AP/883
DG541AK/883
DG542AK/883
DG535AP/883
DG53SAM/883
DG538AP/883
DG540AP/883
DG541AK/883
DG542AK/883
DG287AA-2
DG287AA/883
DG287AP-2
DG287AP/883
DG290AP-2
DG290AP/883
DG 187AA/883
DG187AA/883
DG187AP/883
DG187AP/883
DG190AP/883
DG190AP/883
DG405AZ/883
DG411AK/883
DG411AZ/883
DG412AK/883
DG412AZ/883
DG413AK/883
DG405AZ/883
DG411 AK/883
DG411AZ/883
DG412AK/883
DG412AZ/883
DG413AK/883
DG548AK/883
DG548AZ/883
DGS01AP/883
DG841AM/883
DG908AK/883
DG908AZ/883
DG548AK/883
DG548AZ/883
DGS01AP/883
DG841 AM/883
DG908AK/883
DG908AZ/883
DG300AAA-2
DG300AAA/883
DG300AAK-2
DG300AAK/883
DG301AAA-2
DG301AAA/883
DG300AAA/883
DG300AAA/883
DG300AAK/883
DG300AAK/883
DG301AAA/883
DG301AAA/883
DG413AZ/883
DG417AK/883
DG418AK/883
DG419AK/883
DG480AK/883
DG485AK/883
DG413AZ/883
DG417AK/883
DG418AK/883
DG419AK/883
DG480AK/883
DG485AK/8B3
D123AK/HR
D123AL-2
D123ALl883
D123AP-2
D123AP/883
D125AK/HR
D123AK/883
D123AL/883
D123ALl88
D123AP/883
D123AP/883
D125AK/883
1-10
Industry Part #
Sillconlx Part #
....'
.-r
~
Siliconix
incorporated
Class B
1883 Compliant/Non JAN (Cont'd)
Industry Part #
SlIleonlx Part #
Industry Part #
Silleonix Part #
Industry Part #
Sillconix Part #
D125AL-2
D125ALlHR
D125ALlBB3
D125AP-2
D125AP/BB3
D129AL-2
D125ALlBB3
D125AL/BB3
D125ALlBB3
D125AP/BB3
D125AP/BB3
D125ALlBB3
HI1-5041-8
HI1-5042-8
HI1-5043-8
HI1-5044-8
HI1-5045-8
HI1-506-8
DG5041AK/883
DG5042AK/883
DG5043AK/883
DG5044AK/883
DG5045AK/883
DG506AAR/883
IH5144MJE/883
IH5145MJE/883
L161AL-2
L161ALl883
L161AP-2
L161AP/883
DG5144AK/883
DG5145AK/883
L161ALl883
L161AL/883
L161AP/B83
L161AP/883
D129ALlHR
D129ALlBB3
D129AP-2
D129AP/HR
D129AP/BB3
D139AA-2
D129AL/BB3
D129ALlBB3
D129AP/BB3
D129AP/BB3
D129AP/BB3
D139AA/BB3
HI1-506L-8
HI1-507-8
HI1-507L-8
HI1-508-8
HI1-508L-8
HI1-509-8
DG526AK/883
DG507 AAR/883
DG527 AK/883
DG508AAK/883
DG528AK/883
DG509AAK/883
AD7541ASD/883
AD7541ASE/883
AD7541ATD/883
AD7541ATE/883
AD7541 SD/883
AD7541 SE/883
SI7541ASD/883
SI7541ASE/883
SI7541ATD/883
SI7541ATE/883
SI7541 SD/883
SI7541 SE/883
D139AP-2
D139AP/BB3
D169AK-2
D169AK/883
D169AP-2
D169AP/883
D139AP/BB3
D139AP/BB3
D169AK/883
D169AK/BB3
D169AP/B83
D169AP/B83
HI1-509L-8
HI2-200-8
HI2-300-8
HI2-301-8
HI2-304-8
HI2-305-8
DG529AK/883
DG200AAA/883
DG300AAA/883
DG301AAA/883
DG304AAA/883
DG305AAA/883
AD7541 TD/883
AD7541TE/883
AD7542SD/883
AD7542TD/883
AD7543SD/883
AD7543TD/883
SI7541TD/883
S17541TE/883
SI7542SD/883
SI7542TD/883
SI7543SD/883
SI7543TD/883
D469AP-2
D469AP/883
D470AP/883
HI1-200-8
HI1-201-8
HI1-300-8
D469AP/8B3
D469AP/BB3
D470AP/B83
DG200AAK/883
DG201AAK/8B3
DG300AAK/8B3
HI2-381-8
HI2-387-8
IH5040MJE/HR
IH5040MJE/883
IH5041 MJE/HR
IH5041 MJE/883
DG381AAA/883
DG387AAA/883
DG5040AK/883
DG5040AK/883
DG5041AK/883
DG5041 AK/883
AD7545UD/8B3
AD7545UE/883
SIB603AK/883
SI8604AK/883
SW-01BQ883
SW-02BQ883
SI7545UD/883
SI7545UE/883
SI8603AK/883
SI8604AK/883
DG201AAK/883
DG202AAK/883
HI1-301-8
HI1-302-8
HI1-303-8
HI1-304-8
HI1-305-8
HI1-306-8
DG301AAK/8B3
DG302AAK/883
DG303AAK/883
DG304AAK/883
DG305AAK/883
DG306AAK/883
IH5042MJE/HR
IH5042MJE/883
IH5043MJE/HR
IH5043MJE/883
IH5044MJE/HR
IH5044MJE/883
DG5042AK/883
DG5042AK/883
DG5043AK/883
DG5043AK/883
DG5044AK/883
DG5044AK/883
SW-05BK883
SW-05BY883
DG200AAA/8B3
DG200AAK/883
HI1-307-8
HI1-381-8
HI1-384-8
HI1-387-8
HI1-390-8
HI1-5040-8
DG307AAK/883
DG381 AAK/883
DG405AK/883
DG387AAK/883
DG403AK/883
DG5040AK/883
IH5045MJE/HR
IH5045MJE/883
IH5140MJE/883
IH5141MJE/883
IH5142MJE/883
IH5143MJE/883
DG5045AK/883
DG5045AK/883
DG5140AK/883
DG5141AK/883
DG5142AK/883
DG5143AK/883
1-11
..
BURN·IN CONNECTIONS
Siliconix
incorporated
Package
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Dl25
P/L
-30V
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
10KGND
D129
P/L
(7)
(7)
(7)
GND
(7)
(7)
10K+5V
GND
-30V
(13)
(13)
(13)
10K+5V
+5V
D139
D169
P/L
-
N/C
10KPin 3
10KPin 4
+5V
+10V
+5V
GND
-20V
GND 1OK- N/C
Pin 12
N/C
GND
+10V
GND
+10V
+10V GND
GND
+10V
GND
N/C
N/C
N/C
+10V
GND
GND
GND
Part
Type
D469
N/C
DGl23
P/L
GND
GND
GND
-20V 4.7K- 4.7K- 4.7K- 4.7K- 4.7K- GND +5V
+5V
+5V
+5V
+5V +5V
DGl25
P/L
GND
GND
GND
-20V
DG126
DG129
P/L
10KGND
+10V 10KGND
DGl33
DG134
P/L
10KGND
+10V 10KGND
DG139
DG140
P/L
10KGND
+10V 10KGND
10KGND
DG141
10V
1OKGND
--
GND
+5V
GND
GND
GND
+10V
GND
GND +10V
-20V
GND
+10V
1OKGND
+10V
GND
GND +10V
-20V
GND
+10V
+10V 1OKGND
10KGND
+10V
GND
GND +10V
-20V
GND
+10V
10V
10KGND
1OKGND
10V
GND
GND 10V
-20V
GND
10V
+10V 10KGND
10KGND
+10V
GND
GND +10V
-20V
GND
+10V
GND
GND
GND
+10V 10KGND
1OKGND
+10V 10KGND
GND
+5V
DG142
DGl43
P/L
10KGND
+10V 1OKGND
DG144
DG145
P/L
10KGND
+10V 10KGND
-
+10V 10KGND
10KGND
+10V
GND
GND +10V
-20V
GND
+10V
DG146
P/L
10KGND
+10V 10KGND
-
+10V 10KGND
1OKGND
+10V
GND
GND +10V
-20V
GND
+10V
DG172
P/L
To
-20V GND
+5V
+5V
+5V
+5V
+5V
To
7.5K-20V
pin
14
GND
GND
DG180
DG181
A
+15V
10K- GND
GND
DG180
DG181
P/L
+15V
1OKGND
DGl82
P/L
+15V
10KGND
DG182
DG186
A
+15V
DG183
DG184
DG185
L
-15V
DGl83
DG184
DG185
P
10KGND
DG184
P
DG185
+15V
+5V
GND
-15V
GND
10KGND
+15V
GND
pin
14
-
-
GND +15V
+5V
GND
-15V
GND
-
-
-
--
GND
+15V
+5V
GND
-15V
GND
-
-
10K- GND
GND
+15V
+5V
GND
-15V
GND
10KGND
+15V
10K- 10KGND GND
+15V
GND
+15V
+5V
GND
-15V
GND +15V
10KGND
-15V
-15V 10KGND
--
10KGND
+15V
-15V
10K- 10KGND GND
+15V
GND
+15V
+5V
GND
P
-15V
1OK- 10KGND GND
+15V
GND
+15V
+5V
DG18S
DG187
DG188
P/L
-15V
10K- 10KGND GND
+15V
GND
+15V
DG187
DG188
A
+15V
1OK- GND
GND
+15V
+5V
DG189
DG190
DG191
L
-15V
10K- 1OKGND GND
+15V
GND
DG189
DG190
DG191
P
1OKGND
-15V
-15V 10KGND
1-12
--
-
1OKGND
15
10KGND
+15V
1OKGND
+15V
1OKGND
1OKGND
-15V
GND +15V
+5V
GND
-15V GND
-15V
GND +15V
10KGND
10KGND
-15V
GND
-15V
GND +15V
10KGND
10KGND
+5V
GND
-15V
GND +15V
10KGND
10KGND
-15V
GND
-15V
GND
1OKGND
+15V
+15V
+5V
GND
-15V
GND +15V
10KGND
1OKGND
-15V
-
1OKGND
+15V
GND +15V
+5V
GND
-15V GND
16
+15V
+15V
17
18
BURN-IN CONNECTIONS
Siliconix
incorporated
Part
Packagl
Type
Type
1
2
3
+15V GND
15
16
(15)
10KGND
+15V
+15V
1OKGND
10KGND
+15V
+5V
+15V
(15)
10KGND
+15V
10K- 10KGND GND
+5V
+15V
10KGND
1OKGND
-15V
-15V 15V
10KGND
10KGND
15V
9
10
1OKGND
+15V
-
(10)
+15V
10K- +15V
GND
4
5
6
7
(9)
(9)
-15V
-
(10)
(10)
-15V
-15V
GND
(15)
(15)
-15V
GND
10KGND
-15V
GND
(15)
11
12
13
14
1OKGND
-
+15V
-
+15V
+15V
(15)
(15)
-
+15V
+15V
10K- 10KGND GND
N/C
+15V
+15V
(15)
-15V
8
(9)
DG200
A
+15V
DCl200A
P/L
+15V
-
GND
DCl201
DG201A
P/L
+15V
(15)
(15)
+15V
10K- 10KGND GND
+15V
(15)
DG212
-15V
10K- 10KGND GND
-15V
GND
10KGND
10K- -15V
GND
DG221
15V
1OK- 10KGND GND
-15V
GND
10KGND
10KGND
15V
15V
10K- 1OKGND GND
DG243
(16)
(16)
(16)
(16)
-
(16)
(16)
GND
DG271
+15V
-15V
GND
1OKGND
1OK- +15V
GND
+15V
10K- 1OKGND GND
DG202
DCl211
P
(16)
10K- 10KGND GND
(15)
(15)
15V
5V
GND
-15V GND
1OKGND
N/C
+15V
10KGND
10KGND
+15V
(13)
(13)
1OKGND
+15V
(9)
GND
-
GND
-15V
GND
(9)
1OKGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(9)
GND
-
GND
-15V
GND
(9)
10KGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
1OKGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
1OKGND
+15V
(9)
GND
-
GND
-15V
GND
(9)
10KGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
(9)
GND
-
GND
-15V
GND
(9)
1OKGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
(9)
GND
-
GND
-15V
GND
(9)
10KGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
(9)
GND
-
GND
-15V
GND
(9)
1OKGND
+15V
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
+15V
(15)
(15)
-15V
GND
(15)
(15)
+15V
+15V
(15)
(15)
-
+15V
(15)
10KGND
+15V
-15V
(15)
(15)
-15V
GND
(15)
(15)
-15V
-15V
(15)
(15)
-
(15)
(15)
10KGND
-15V
N/C
N/C
GND
+15V
+5V
GND
-15V
GND
N/C
N/C
1OKGND
+15V
-
-
GND
+15V
+5V
GND
-15V
GND
-
-
10KGND
+15V
DG300A
A
(9)
DG300A
P/L
-
DG301A
A
(9)
DG301A
PIL
DG302A
P/L
-
DG303A
P/L
-
DG304A
A
(9)
DG304A
P/L
-
DG305A
A
(9)
DG305A
P/L
-
DG306A
P
(9)
DG306A
P/L
DG307A
P
DG307A
P/L
DG308A
P
DG309
-
(15)
-
(9)
DG381A
A
+15V
1OKGND
DG381A
P
+15V
10KGND
17
18
--
1-13
BURN·IN CONNECTIONS
PackagE
Type
1
DG384A
L
-15V
DG384A
P
10KGND
DG387A
P'
DG390A
P
Part
Type
2
8
9
10
11
12
GND
-15V
GND
+15V
10KGND
10K- -15V
GND
10KGND
+15V
GND
+15V
+BV
GND
GND
-15V
GND
+15V
1OKGND
10K- -15V
GND
-15V 1OKGND
1OKGND
+15V
GND
+15V
+BV
GND
6
4
5
+15V
GND
1OKGND
-15V
-15V 10KGND
-15V
1OK- 1OKGND GND
+15V
GND
1OKGND
10KGND
-15V
3
10K- 10KGND GND
-
Siliconix
incorporated
7
+15V +BV
-
+15V +BV
13
14
15
16
GND
+15V
-15V
GND
+15V
-15V
DG400
10KGND
N/C
1OKGND
10KGND
10K- 10K- N/C
GND GND
10KGND
10KGND
GND
+15V
+5V
GND
-16V
GND
10KGND
DG401
10KGND
N/C
10KGND
1OKGND
1OK- 10K- N/C
GND GND
10KGND
1OKGND
GND
+15V
+BV
GND
-15V
GND
1OKGND
DG402
10KGND
N/C
10KGND
10KGND
10K- 10K- N/C
GND GND
1OKGND
10KGND
GND
+15V
+BV
GND
-15V
GND
10KGND
DG403
10KGND
N/C
10KGND
10KGND
10K- 10K- N/C
GND GND
10KGND
1OKGND
GND
+15V
+BV
GND
-15V
GND
10KGND
DG404
10KGND
N/C
10KGND
1OKGND
1OKGND
1OK- N/C
GND
10KGND
1OKGND
GND
+15V
+BV
GND
-15V
GND
1OKGND
DG405
1OKGND
N/C
10KGND
10KGND
10K- 10K- N/C
GND GND
1OKGND
10KGND
GND
+15V
+BV
GND
-15V
GND
1OKGND
+15V
+15V
(15)
(15)
+BV
+15V
(15)
10KGND
+15V
DG411
P
+15V
(15)
(15)
-15V
GND
(15)
(15)
DG417
K
10KGND
N/C
GND
+15V
+BV
+15V
-15V
(3)
DG421
10KGND
GND
10KGND
10K- ,10K- 10K- GND
GND GND GND
1OKGND
10KGND
GND
+15V
+5V
GND
-15V
GND
1OKGND
DG423
10KGND
GND
10KGND
1OKGND
10K 1OKGND GND
GND
10KGND
1OKGND
GND
+15V
+BV
GND
-15V
GND
10KGND
DG425
10KGND
GND
10KGND
10KGND
10K- 10K- GND
GND GND
10KGND
1OKGND
GND
+15V
+BV
GND
-15V
GND
10KGND
17
18
DGSOI
DG503
813705
P/L
(IS)
(4)
(4)
+10V
(12)
(12)
(12)
(12)
(12)
(12)
(12)
-10V
-15V
(15)
(IS)
GND
DG508A
P/L
GND
GND
-15V
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
10KGND
+15V
GND
GND
GND
DG509A
P/L
GND
GND
-15V
(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)
10KGND
+15V
GND
GND
DG528
P
GND
GND
GND
-15V
(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)
10KGND
+15V
GND
GND GND
GND
DG529
P
GND
GND
GND
-15V
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
10KGND
+15V
GND
GND
GND
DG568
GND
GND
10K+15V
-60
(13)
(13)
(13)
(13)
(13)
(13)
(13)
(13)
10K- 10KGND +80,
GND
GND GND
GND
DG5S9
GND
GND
10K+15V
1OK-60
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
10KGND
10K+80
GND GND
GND
10KGND
1OKGND
1OKGND
10K- N/C
GND
10KGND
10KGND
GND +15V
+BV
GND
-15V
GND
10KGND
10KGND
10KGND
10K- 10KGND GND
1OKGND
10K- . GND +15V
GND
+BV
GND
-15V
GND
1OKGND
10KGND
10K- 10KGND GND
1OKGND
10KGND
10KGND
GND
+15V
+BV
GND
-15V GND
10KGND
10KGND
10KGND
10KGND
1OKGND
10KGND
GND
+15V
+BV
GND
-15V GND
10KGND
DG5040
DG5041
P
10KGND
DGS042
DG5043
P
10KGND
DGS044
DGS045
P
10KGND
DGS140
1-14
10KGND
N/C
1OKGND
N/C
BURN·IN CONNECTIONS
Siliconix
incorporated
Part
Type
Package
Type
6
7
8
9
10
11
12
13
10K- 1OKGND GND
10KGND
N/C
10KGND
10KGND
GND
+15V
+5V
GND
-15V GND
10KGND
10KGND
10K- 10KGND GND
1OKGND
N/C
10KGND
1OKGND
GND
+15V
+5V
GND
-15V GND
1OKGND
N/C
10KGND
10K- 10KGND GND
10KGND
N/C
10KGND
1OKGND
GND
+15V
+5V
GND
-15V GND
10KGND
10KGND
N/C
10KGND
1OK- 10KGND GND
10KGND
N/C
10KGND
10KGND
GND
+15V
+5V
GND
-15V GND
1OKGND
10KGND
N/C
10KGND
10K- 10KGND GND
1OKGND
N/C
10KGND
1OKGND
GND
+15V
+5V
GND
-15V GND
1OKGND
(13)
(13)
(13)
(13)
GND
GND
-15V
GND
(13)
(13)
(13)
10KGND
+15V
-15V -15V
-15V -15V
-15V
(14)
(14)
(14)
(14)
(14)
(14)
(14)
10K+10V
-15V -15V
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
10K+10V
(9)
-
-
(6)
220-15V
(3)
GND
(2)
220+15V
1
2
3
DG5141
10KGND
N/C
1OKGND
DG5142
10KGND
N/C
DG5143
10KGND
DG5144
DG5145
4
5
DGP303
P/L
-
G118
P/L
-15V
G119
P/L
(14)
(14)
-15V
L144
P/L
3M.o.
+15V
(13)
(11)
L161
P
-15V
+15V -15V
+15V -15V
+15V
-15V +15V
-15V
10o.n. GND
5V
18K5V
GND
GND
LD110
3K5V
3K5V
3K5V
3K5V
6K5V
18.0.
5V
LD111
N/C
GND
+15V
GND
10K+15
-15V
LD121
(18)
(18)
5V
GND
5K5V
5K5V
813002
N/C
N/C
N/C
Pin 9 GND
-20V
817240
GND
GND
GND
1K15V
1K15V
1K15V
817250
N/C
GND
N/C
N/C
N/C
817541
GND
GND
GND
16
817541 A
GND
GND
GND
817542
GND
GND
817543
GND
GND
817652
To
8
8
Pin
817660
-
817661
818603
818604
18
•
+15V
N/C
Pin 11 GND
Pin 9
N/C
-1.36 -15V GND
V
20KI
200K
-15V
(18)
(18)
(18)
(18)
(18)
5V
-15V
(18)
(18)
2.5K
5V
GND
GND
Pin 4
+10V
1K15V
1K15V
1K15V
1K15V
1K15V
1K15V
1K15V
1K15V
1K15V
1K15V
10V
10V
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
12V
16
16
16
16
16
16
16
16
16
16
16
1K+15V
+10V +10V
16
16
16
16
16
16
16
16
16
16
16
16
1K+15V
+10V +10V
GND
GND
GND
1K5V
1K5V
GND
GND
1K5V
1K5V
GND
1K5V
1K15V
1K15V
1K15V
GND
GND
GND
1K6V
1KSV
GND
GND
1K5V
1KSV
GND
1K1SV
1K1SV
1K1SV
1K15V
Pin
10
To
N/C
Pin 4
+15
N/C
N/C
N/C
GND
+SV
Pins
(16)
910.0. N/C
10K
To
GND
GND
N/C
N/C
GND
+5V
CLK
5.6K- S.6K
15V
15V
N/C
5.6K- 5.6K
15V
15V
1KSV
1K-15V
GND
-
68o.n. .1J1.F
GND To
Pin
2
-
-
N/C
N/C
3K5V
17
GND 3K5V
Pin
CLK
3M.o.
+15V
16
18.0.
5V
-
+5V
15
30K5V
.1J1.F .1J1.F N/C
To
14
3K5V
+15V
1K5V
1K1SV
5.6K- 5.6K- Pins
15V
15V
(11)
(16)
GND
5.6K- 5.6K- Pins
15V
15V
!11)
16)
GND
(17)
GND
+5V
Pins
(16)
(17)
S.6K- 5.6K- 5.6K- 5.6K- 22KGND GND GND GND GND
(11)
(7)
5.6K- 5.6K- 5.6K- 5.6K- 22KGND GND GND GND GND
(11)
(7)
1-15
BURN-IN CONNECTIONS
Partl
Pkg
Type
0470
28 Pin
CDIP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
(2)
-t5V
+15V
(18) -15V (18)' +15V (18)
1
-15\
(18) +lSV NC
DGS07A/R
-lSV (18) +lSV
+15~
GND GND 10K -15V +lSV 10K -lSV
GND
GND
(18)
+15V (18)
~?~
~?:"
10K 10K 10K 10K 10K 10K 10K
2.SV 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
10K
2.5V
10K 10K
2.5V 2.5V
GND GND
-t5V 10K
2.5V
10K 430 10K 10K 10K 10K
10K
2.5V 2.5"
2.SV 2.5V 2.5V 2.SV
2.5V
~?:~
10K
2.5V
10K
2.5V
+15"
(28)
(28)
(28)
DF412/P
DGS06
DGSOSA
Siliconix
incorporated
15V 10K
GND
.n.
~?:"
GND GND GND -t5V
(28)
(28)
(28)
(28)
(28) -15V 10K
GND
--
(2)
(2)
(2)
(2)
(2)
(2)
(2)
-15V (2)
15V
(28)
GND
(28)
(28)
(28)
(28)
(28)
(28) -15V 10K
GND
lSV
(28)
GND
(28)
(28)
(28)
(28)
(28) -lSV 10K
GND
GND
18
18
18
18
18
18
18
18
18
18
10K
+lSV
(28)
10K
2.5V
GND -t5V GND -t5V
GND 400
pf-t5V
10K 10K 10K 10K
2.5V 2.5V 2.SV 2.SV
GND GND GND GND GND
(28)
(28)
(28)
(28)
GND GND GND GND GND
(2)
(2)
(2)
(2)
GND GND GND GND GND GND GND
(28)
(28)
(28)
(28)
(28)
GND GND GND GND GND GND GND
(28)
(28)
(28)
(28)
18
GND GND GND GND GND GND 18
18
10KGND
18
18
(28)
(28)
(28)
(28)
(28)
GND
(2)
(2)
(2)
(2)
(2)
GND
(28)
(28)
(28)
(28)
(28)
(28)
(28)
(28)
(28)
18
18
18
18
-
DG52S
(28)
(28)
DG527
DG535
!~~\
GND
(28)
(28)
(28)
(28)
(28)
N/C 1.SK
GND
PIN
14
1.SK 1.SK 1.SK 1.SK 1.SK 1.SK N/C +S
GND GND GND GND GND GND
GND
1.5 .1JJF S.8m .1J,Lf .1J.LF
To
To
J.LF GND
~In
GND
GND Gin
10K
GND 10K GND 10K 10K GND GNC GND GND GND GND 10K 10K 10K GND 10K
GND
+lSV
+15V
+lSV +lSV
+lSV +lSV GND
+lSV
10K GND
+lSV
DG536
DG5SS1
SB/J
PLCC
(28)
(28)
(28)
10K
GND
(28)
(28)
(28)
(28) 10K
SOV
10K
SOV
(19)
(19)
(19)
(19)
(19)
(19)
(28)
(28)
GND CLK
2KH
Pin
3
N/C
l.SK l.SK 1.SK 1.5K
GND GND GND GND
1.SK
GND
1.5K N/C
GND
N/C
N/C
N/C
N/C
N/C
20K
To
Pin
26
N/C -t5
Clk
15
15
15
lK- GND GND lK- lKlK+15V
+15V +15V +15V
-t5V
-t5V
GND
(28)
SI2504
1.5K
GND +5V
100
400K
-t5
lOOK
-SV GND
.n.
S17135
.n.
N/C
GNC 20K
-t5V
20K
Pin
20
N/C
N/C
N/C
GND
GNC GND
15
15
15
15
15
GND ~O~ 100
N/C
N/C
N/C
b~~ .n.
..."
15
15
15
S17545
-t5V 8KHZ 5.SK
Clk
5V
5.SK 5.SK 5.SK 22K GND GND GNt GND GND -t5V
5V 5V
5V
GND
+15" +15V 5.6K
Clk
+15V
~;~~
5.SK 5.SK
GND GND
5.SK 22K GND
GND GND
+SV
GND -t5V
GND
(7)
-t5V
(27)
+10V (27)
(7)
SI8S01
SI8S02
1-16
5.SK
GND
5.SK 5.SK (27)
+15V +15V
GND GND GN[ GND GND +15V +15V +15V +lSV GND +15V GND
Process Option Flows
IIJI
~
~
Siliconix
incorporated
PROCESS OPTION FLOW CHARTS
Military and Extended Hi-Rei
Column I:
The first column identifies Siliconix' MIL-M-3B510 Compliant JAN, Class B, process
flow option. MIL-M-38510 JAN product will be processed in accordance with the applicable detail slash sheet requirements.
Column II:
The /883 Compliant/Non-JAN, Class B process flow meets the requirements of MILSTD-B83, paragraph 1.2.1. Devices which are processed to this flow are identified
within the generic part number suffix as /883.
Column III:
The Extended Hi-Rei 1 flow offers customers, with Space type requirements, the option of a Space Rated flow for generation of specification control drawings.
Column IV:
The Extended Hi-Rei 2 flow is offered to customers that can accept product that has
SEM and a 240 hour static burn-in.
2-1
lEI
Siliconix
incorporated
PROCESS OPTION FLOW CHART
MII-M-38510 JAN
Class B
P
1883 Compliant/Non-JAN
Method 5004/5005
*
Extended HIIRel 1
Extended HIIRel 2
**
INTERNAL VISUAL
Method 2010, Cond A
INTERNAL VISUAL
Method 2010, Cond B
E
NOT
Method 2023
R
S
L
A
S
H
S
H
E
E
T
INTERIM ELECTRICAL
(Post Burn In)
Static @ 25°C POA=50/0
Functional @ 26°C,
POA=30/0
datal
ANAL ELECTRICAL
per data sheet
minImax oper temp
*
**
***
2-2
MIL-STD-883
The latest revision of
MIL-STD-883 at time
of order Is applicable.
Available Option SEM
Dual bum-In may be
performed In reverse.
~
~.
Siliconix
incorporated
Hi-Rei and Standard Flow
Column I:
This flow is for Military/ Aerospace/Industrial customers that can use a noncompliant/
non-JAN device in their equipment. while gaining the advantage of environmental and
infant mortality screening.
Column II:
The standard flow outlined within this column is intended for plastic and hermetic
packages with burn-in.
Column III:
The standard flow outline within this column is intended for plastic and hermetic packages without burn-in.
•
2-3
Siliconix
incorporated
PROCESS OPTION FLOW CHART
HI-Rei
STD (Burn-In)
INTERNAL VISUAL
(Industrial)
STD
INTERNAL VISUAL
(Industrial)
TEMP CYCLE
Method 1010, Cond C
(Plastic only)
GROSS LEAK
Method 1014, Cond C
(Hermetic only)
BURN-IN 160 hrs
Method 1015
Cond A or C
QCI
QA electrical (AQL)
T":!SoC
100% EXTERNAL
VISUAL
Method 1009
2-4
EXTERNAL
VISUAL (AQL)
Method 1009
QCI
QA electrical (AQL)
T..:!5°C
...... Siliconix
.c;II incorporated
Die Shipments
Column I:
This flow offers customers the option of assembling canned sample to verify the die
are capable of meeting the military temperature range. electrical test limits. Die Attach and Bond Strength will also be performed to insure assembly operation.
Column II:
Column II is the same as die/canned sample flow with burn-in added for confidence
that die samples do not shift across this screen. Die Attach and Bond Strength will
also be performed to insure assembly operation.
Column III:
This column identifies Siliconix' die shipment option without canned samples.
--
2-5
Siliconix
incorporated
PROCESS OPTION FLOW CHART
DIE SHIP
CANNED SAMPLES
WAFER SCREEN: •
CANNED SAMPLE:
LTPD=10
DIE SHIP
CANNED SAMPLES
WITH BURN-IN
WAFER SCREEN: •
CANNED SAMPLE:
LTPD=10
FINAL ELECT
Static @ 25°C
Min operating temp
Max oparatlng temp
(per data sheet)
FINAL ELECT
Static @ 25°C
Min operating temp
Max operating tamp
(per data sheet)
• Available Option SEM
2-6
DIE SHIP
WAFER SCREEN:
•
...... Siliconix
incorporated
~
Die Process Information
Siliconix is a large-volume supplier of dice to the hybrid industry. Screening includes 100% DC electrical
probe and 100% visual inspection of each die.
ASSEMBLY
The customer's interests will best be served if static
sensitivity handling procedures are used.
PHYSICAL DATA
PART NUMBER DESIGNATIONS
Physical layout and dimensions are presented in the
Die Topography section Dimensions are shown as
'(';'~i. Dice are supplied to length and width dimensions which have an accuracy of ±3 mils. Thickness
will be 15 ±1 mils for integrated circuit die with gold
backing, and 21 ±1 mils without gold backing, and 8
±2 mils for FETs.
See ordering information.
Bonding pad location may be identified from the die
topography shown. Contact factory for ordering information. Each die or wafer is passivated with approximately 8000 A of either silicon nitride or non-crystalline glass. FET chips are supplied with gold backing;
gold backing is available as an option for integrated
circuits. Die metallization is deposited aluminum approximately 12000 Athick.
DIE SCREENING CRITERIA
Electrical Probe -- All dice are 100% probed in wafer
form at 25°C to DC parameters as shown on the wafer test limits specification (available upon request).
Hot chuck is also available at additional cost.
Visual Criteria -- Each die receives a visual inspection to MIL- STD-883. Method 2010, Condition B criteria. Siliconix QC Department samples each lot to an
LTPD of 10%. Alternative visual criteria, including
Method 2010, Condition A, or Siliconix industrial criteria are available as options.
PACKAGING
Die are supplied in dust-proof, anti-static waffle
packs (see illustration - Figure 1)
OPTIONS
(Price will be quoted upon request.)
SEM -- Scanning electron microscope examination
and control in accordance with MIL-STD-883 Method
2018 can be ordered on die and wafers. SEM wafer
qualification should be specified as a separate line
item on a request for quote.
Wafer Qualification to Unprobed Parameters -Sample testing of purchased die to demonstrate capability to perform at data sheet temperature extremes or to switching times test limits by use of
LTPD techniques can be provided at additional cost.
Visual inspection to customer generated specifications can be provided.
Gold Backing -- IC dice may be purchased with gold
alloyed to the backside. This is a special order item.
Gold thickness would be as follows:
FETs (NC, NIP)
1500
A minimum
ICs (all)
3500
A minimum
Hot Chuck -- Siliconix can perform wafer sort at the
high-temperature limit, at additional cost.
CHIP PACKAGING
Chips are packaged as individual die in the flat waffle
carrier illustrated in Figure 1 . The carrier has a cavity
size adequate to allow ease of loading and unloading
and it also prevents die from rotating within the cavity.
2-7
~'
..... Siliconix
incorporated
~
DG190 consists of a separate driver chip (CMJB) and
four separate JFET transistors (NCB). Figure 2 illustrates the bonding diagram arrangement in the DIP
package. The driver and the JFET switches are
mounted so that the substrates are electrically isolated. The substrate of the driver is at the negative
supply voltage while the substrate of the JFET
switches is the gate connection. A pattern-bottom
side braze package is used to connect the driver to
the JFET gate.
The pin connections for the JFET switch chips can be
determined from the chip section and switch chips
can be determined from the chip section and switch
pin-out in the data sheet.
Ole Diagrams/Dimensions
NOTE: CARRIER TOP & BOTTOM SECURED BY CLIPS
MULTI-CHIP DIE TOPOGRAPHY
INFORMATION
The negative image photos show the metallization
pattern. Scale is normally 20x. Bonding pads are 4
mil (0.10 mm) square, glass-free aluminum
metallization. Pad identification numbers usually correspond to pin numbers for the dual-in-llne package
on data sheets.
Some of Siliconix's analog switches are of multi-chip
design with inter-chip connections. For example, the
Wafer test limits are available upon request.
Figure 1
7
8
9
10
Figure 2.
2-8
DG190 JFET Analog Switch
..
H
Siliconix
incorporated
8S9000 Series Process Option
Flow Chart
..
RAPID CHANGE OF
TEMPERATURE
BS9400 1.2.6.13
10 CYCLES
-65 to 150°C
ACCELERATION STEADY STATE
BS94001.2.6.9
294,000 m/s'
IN DIRECTION Y2
FINE AND GROSS LEAK TESTS
BS9400
1.2.6.14 (1), (2)
ELECTRICAL TESTS at 25 ° C
AS SUBGROUP A3(a) of the
SPECIFICATION
BURN-IN SCREEN
BS94001.2.7.2.1
168 HOUR MINIMUM at 125°C
FINAL ELECTRICAL TESTS at
25°C AS SUBGROUP A3(a)
of the SPECIFICATION
INSPECTION REQUIREMENTS: All tests performed at T amb
= 25°C unless otherwIse specified.
100% SCREENING TEST PROCEDURES
Production batches containing greater than 10% defective units subsequent to burn-In will not be Issued for release.
For complete details of screening and Inspection refer to the appropriate detail specification available on request from
your nearest SlIIconlx sales offices.
2-9
..,
..
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Selector Guide . .
\..
~
:j"cn
ANALOG SWITCH SELECTOR CHART
0=
00'
-'0
"O::l
Q s("
el.
CD
0.
SWITCHING SPEED t(on) OR t(off) , WHICHEVER IS GREATER
20/35 to
60/75 ns
10 ns
125/150 ns
500/600 ns
300 ns
250 ns
200 ns
DG441 (0,Q,8S)
DG442 (0,Q,85)
100
,n,
0G444 (C,a,SS)
QI
'0;
a.
0G30BA (0,
55)
DG309 (c,a,SS)
212.5118
DG123 (P,S,CD,r)
513002 (P,S,SD,r)
OG125 (P,S,CD,r)
DG221 (C,a, 55, L)
DG445 (C, 0, 58)
o
c:
U>
1.5/1.6)18
lJ1S
(C, a, SS) DGl72 (P,S,CD,r) 0G211 (C, a, SS)
0G212 (C, a, SS)
DGP201A(C,Q,SS
0G202
,n,
~
750 ns
DG201A (0,Q,85)
175
DG126 (J,D,DS)
DGl82 (J,D,SS)
0G540 (0, a, SS)
0G541 (O,a,SS)
80
,n,
OGl85 (J,O,OS)
OGl34 (J,O,SS)
DG200A (0,0,88) OG142 (J,Q,DD)
DG143 (J, S,SD)
DGl88 (J,S,SD)
OG191 (J, 0, SO)
DG542 (0,0,88)
~
Radiation
ResIstant
QI
a:
Z
o
QI
...
o
:::I
o
50210 (D,$,SS,rl
DG271 (0,0,88)
80211 (D,S,8S,r)
S0212 (O,S,SS,r)
50 50213 (D,S,SS,r)
(O,5,S5,r)
,n, 50214
80215 (O,8,88,r)
502100(0,5, SS, r)
S02110(0,8,5S,r)
502120(0,5, SS,r)
DG5140 (C, S, 58)
DG5141 (0,0,$8)
DG5142
DG5143
0G5144
OGS145
(0,8, SO)
(0,0,50)
(C,S,OS)
(C,O,OS)
DG304A (0,0,88) DG300A
DG305A (0,8,80) DG301A
0G306A (C,O,OS) 0G302A
DG307A (C,O,SO) 0G303A
OGP303A(C, 0, SO 0G381A
DG566 (H,8,SS,r)
DG243(C,D.SD,M
(0,0,88) DGS048 (C, 0, 58)
(C,S,SD) 0G5049 (C,O,OS)
(C, 0, OS) OGS050 (C, S, SO)
(C,O,SO) DGS051 (O,O,SD)
(0,0,58)
OGS040 (C, S, SS)
OGS041
OGS042
OGS043
OGS044
DGS045
0G384A (C, 0, OS)
0G387A (C,8,80)
0G390A (0,0,50)
(0,0,55)
(C,S,SO)
(C, 0, SO)
(0,5,05)
(0,0, OS)
(f)
I
o
i'
c:
"eo
30 505000(0, Q, 55, r) OG601 (L, a, 55)
,n,
505001 (D,Q,SS,r)
5D5002{0,Q, 55, r)
SD5400(D,a,85,r)
to SD5401(O,a,5S,r)
S05402(0,Q,8S,r)
SD5200(D,a,S5,r)
25
,n,
'2
OG181
OGl84
OG1B7
DG190
OG129 (J, 0, OS)
(J,0,S5)
(J,O,DS)
(J,5,50)
(J,O,SD)
OGl33 (J,O,SS)
OG139 (J,D,DD)
DGl44 (J,S,50)
}
Radiation
Resistant
00400 (0,5,5S)
0G401 (0,0, SS)
00402 (C,5,50)
0G403 (C,O,SO)
S122oo(0,5,8S,r)
812400(0, S, S5,r)
0G404 (C,S,OS)
0G405 (C,O,OS)
~
00411 (O,a,5S)
00412 (O,Q,SS)
(f)
0G413 (C,a,SS)
0G417 (C,S,SS)
...o
i
00418 (O,S,SS)
0G419 (C,SO,S)
0G421 (C,D,SS,L
00423 (C,D,SO,L
00425 (O,D,OS,L
OG180
OG183
OG186
OG189
10
,n,
(J, 0, 5S)
(J,D,DS)
(J,S,SO)
(J,O,5D)
---_.-
ParenthAsls Information
(C,
a,
SS, L)
II I
L - Mlscelianeous
Configuration
No. per Package
Process
o
J
P
H
Er=
= Plus-40 OMOS or 44 V 51-Gate
= DM05 or DICMOS
= JFET
= PMOS
= High Voltage
L
= Low Voltago CMOS (PolyMOS)
°
NO
S
D
Q
8
per
Radiation
Resistant
~
= Dual (2 per package)
= auad (4 per package
= Eight per package
(O/CMOS)
~
I
OG140 (J,O,OS)
OG141 (J,O,SS)
OG145 (J,O,DO)
OG146 (J,S,SD)
- _ . - -_.
----
package
= Single (1 per package)
{
55
SO
OS
00
CD
Single-Pole SlOgle-Throw
Single-Pole Double-Throw
Double-Pole Single-Throw
Double-Pole Double-Throw
Common Drain
Miscellaneous
r
M
L
=-
=
=
rOS(ON) is a function of drive voltage
Make-Befera-Break
Latchable Inputs
If
.1\)
ANALOG SWITCHES
Functional
Conflguratlon
Basic
Part
Number
Switch
Type
rOS(on
MAX IS (off)
(~)
M
(2)
Supply
Voltage
Package and Temperature Range Offerings:
Switching
n!I~AX
~~
V+
v-
L
(3)
Volt.
Range
(2)
V,
(
ton
) MAX
Supp.
toff Range
Analog
Voltage
Range
(V)
logic
Input
for ON
Switch
Levels
~ r-V
InL
V
InH
Commants
Plastl Plastl
DIP
SO
CerDIP
1 Ch. SPS DG417
1 Ch. SPS 00418
1 Ch. SPS 0G400
CMOS + 40
CMOS + 40
CMOS + 40
35
35
25
0.25
0.25
0.25
15
15
15
-15
-15
-15
5
5
5
30
30
30
175
175
175
146
145
146
44
44
44
V+ to VV+ to VV+ to V-
0
1
1
0.8 2.4 Mini DIP, Low Power
0.8 2.4 Mini OJP, Low Power
0.8 2.4 Low Power, High Perf.
OJ
OJ
OJ
1 Ch. SPS ~
1 Ch. SPS ~
CMOS
+ 40
+ 40
30
50
0.50
16
-15
44
1
1
AK,CK
30
v+ to Vv+ to Y-
OJ
-15
125
500
0.8 2.4 Use DG400 for New Designs
15
200
1000
44
1.00
5
5
3Q
CMOS
0.8 2.4 Use DG400 for New Designs
CJ
AK,CK
MOS
25
0.25
15
-15
5
30
125
75
44
V+ to V-
1
O.B 2.4 Low Power, High Perf.
OJ
AK
35
25
0.25
0.50
15
15
-15
-15
5
6
30
30
175
126
145
75
44
44
V+ to VV+ to V-
1
1
0.8 2.4 On Board Latches
0.8 2.4 Low Charge Injection
OJ
OJ
AK
AK
2 Ch. SPS DG6141
2 Ch. SPS DG181
pMOS + 40
N-JFET
30
30
0.50
1.00
16
10
-15
-20
6
6
30
20
200
150
126
130
44
36
V+ to V(V+) to (V-)+7.5
1
0
0.8 2.4 Use DG401 for New Designs
0.8 2.0 Usa 00401 for New Designs
CJ
AK,CK
2 Ch. SPS oG181
2 Ch. SPS" ~
N-JFET
N-JFET
30
30
1.00
1.00
15
12
-15
-18
5
15
20
150 130
600 1600
38
(V+)-2 to (V-)+8
0
1
0.8 2.0 Use 0G401 for New Designs
0.8 2.5 Usa 0G401 for New Designs
2 Ch. SPS" DG304A CMOS + 40
2 Ch. SPS 0G381A CMOS + 40
50
50
1.00
1.00
15
15
-15
-15
30
30
250
300
150
250
44
44
V+ to VV+ to V-
1
0
3.5 11.0 JAN Qualified
0.8 4.0 Use 00401 for New Designs
CJ
CJ
AK,BK,CK
AK.BK,CK
2Ch. SPS DG300A CMOS+4O
2Ch. SPS ~ CMOS+4O
30
30
300
1000
OJ
CJ
AK,BK,CK
AK,CK
2
2
2
2
50
50
1.00
1.00
15
15
-15
-15
SPS oGl82
SPS OGl82
SPS OGl34
SPS
75
75
80
10
1.00
1.00
1.00
10.00
10
15
12
10
-20
i5Ci'18O
N-JFET
N-JFET
N-JFET
N-JFET
-15
-18
-20
2 Ch. SPS OG180
2 Ch. SPS QQlll
N-JFET
N-JFET
10
10
10.00
10.00
15
12
-15
-18
70
2.00
15
-15
35
35
35
175
175
175
175
175
0.25
0.25
0.25
0.25
0.26
0.25
0.25
0.25
15
15
15
15
15
22
15
15
-15
-15
-15
-16
-15
2 Ch. SPS DG200A CMOS + 40
4
4
4
4
4
4
4
4
Ch.
Ch.
Ch.
Ch.
Ch.
Ch.
Ch.
Ch.
SPS
SPS
SPS
SPS
SPS
SPS
SPS"
SPS
NOTES: 1.
2.
00411
00412
0G413
0G441
0G445
OGP2011
00442
0G444
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
IoMOS
CMOS
+ 40
+ 40
+ 40
+ 40
+ 40
+ 40
+ 40
+ 40
5
5
5
5
5
5
5
5
5
-22
-15
-15
5
I
AI(
+ 40
Ch.
Ch.
Ch.
Ch.
Metal
Can
OY
OY
2 Ch. SPS 0G421
PMOS + 40
2 Ch. SPS DGS048 PMOS + 40
2 Ch. SPS 00401
Side
Flat
Braze Lee Pac
I
i
i
AZ
I
IAP,BP
AL
AA,BA
!AP,BP
IAP,BP
AL
AL
AA,BA
'I'
I
AA'BA'C~
AA,BA,C~
250
500
44
44
V+toVV+toV-
1
1
0.8 4.0 JAN Qualified
0.8 2.4 Usa 00401 for New Designs
20
20
20
20
250 130
260 130
600 1800
300 260
36
(V+) to (V-)+5
(V+)-2 to (V-)+5
(V+) to (V-)+7.5
0.8
0.8
0.8
0.8
Designs
Designs
Designs
Designs
!AP,BP
IAP,BP
BP
!AP:BP
AL
AL
AL
AL
AA,BA
AA,BA
36
36
0
0
1
0
15
20
300 250
1000 2500
AL
AL
AA,BA
(V+)-2 to (V-)+8
0.8 2.0 Use 00401 for New Designs
0.8 2.5 Use 00401 for New Designs
IAP,BP
36
0
1
30
1000
500
44
V+ 10 V-
0
0.8 2.4 JAN Cuallfled
AL
AA,BA,CA
30
30
30
30
30
44
30
30
175
175
175
175
175
600
175
175
145
146
145
145
145
450
145
145
44
44
44
44
44
44
44
44
v+
V+
V+
V+
V+
V+
V+
V+
~
to Vto Vto v10 Vto Vto Vto Vto V-
0
0.8
1
0.8
!Note (6) 0.8
0
0.8
0
0.8
0
0.8
0
0.8
0
0.8
2.0
2.0
2.5
2.0
2.4
2.4
2.4
2.4
2.4
2.4
2.4
2.4
Use 0G401
Use 0G401
Us.0G401
Use 0G401
for
for
for
for
New
New
New
New
Low Power, High Perf.
Low Power, High Parf.
Low Power, High PorI.
0G201A Upgrade
0G212 Upgrade
High Precision
00202 Upgrade
00211 Upgrade
Not recommended for new designs.
For most products, the analog voltage range Is a function of supply voltages. For PMOS or CMOS SWitch, r DS(on) Is also a function of supply and
analog voltage. Sea Individual data sheats for mora details.
3.
4.
5.
Logic supply voltage required for TTL compatible Inputs.
Preliminary product. Specifications subject to change. Contact the factory for availability.
Input reference voltage of 2.5V Is required. See Inchvldual data sheets for more details.
6.
See data sheets for sWitch states of differential and multiple switches.
AA.BA,C~
lAp
~,BP
OJ
OJ
OJ
OJ
OJ
OJ
OJ
OJ
OJ
AK,BK,CK
DY
OY
OY
OY
OY
OY
OY
DY
I
AA,BA,
I
AI<
AI<
AI(
AK
AI<
AI(
AK
AI<
AZ
I
~
:r(J)
0=
00'
"'0
'0:3
~x·
iii
c.
\i
tq
:rcn
0=
ANALOG SWITCHES
00'
"'0
"0:;3
Qx'
Switching
Supply
Functional
Basic
Conflgura-
Part
lion
Number
Switch
Type
rDS(on
MAX ) IS(off)
(.e.)
MAX2
(2)
nA
VL
(3)
ton
toff
30
30
30
30
20
30
75
200
200
550
300
600
75
150
150
340
750
450
450
10.00
10,00
12
10
90
60
18
(V+) -6 toV-
0
10
90
50
18
(V+) -5 toV-
0
15
15
-3
-3
-15
-15
30
30
1000
500
500
44
44
V+ to vV+ to V-
300 2000
36
(V+) to (V-)+10
1500 124
(V+)-10 to (V-)
0
60
O/CMOS
60
4 Ch. SPST DG212
CMOS +41
175
4 Ch. SPST DG211
CMOS +41
175
6,00
5,00
10
-20
5
20
60
-60
15
100
5 Ch, SPST DG125
PMOS
100
1,00
8 Ch, SPST DGS66
D/CMOS
100
5.00
1 Ch. SPOT DG305A
1 Ch. SPOT ~
1 Ch. SPOT DG1e8
1 Ch.
1 Ch.
1 Ch.
1 Ch.
1 Ch,
1 Ch,
SPOT
SPOT
SPOT
SPDT
SPOT
SPOT
NOTES:
OGI66
~
OGI86
~
OGI86
~
N-JFET
N-JFET
N-JFET
CMOS +4
CMOS +41
CMOS +4
CMOS +4
N-JFET
N-JFET
N-JFET
N-JFET
PMOS
N-JFET
N-JFET
12
25
25
25
30
30
30
30
0,25
0,25
15
15
0.50
0.50
1.00
1,00
15
15
1.00
50
50
50
50
1.00
1.00
1.00
1.00
1.00
12
15
15
75
75
80
10
100
10
10
-
0.8
0.8
0.8
0.8
600
O/CMOS
+4
+41
+41
+4
V+to V-
0
0
0
I
30
4 Ch. SPST OG541
CMOS
CMOS
CMOS
CMOS
0.8 2.0 High Speed, Low Charge InJ.
3.5 11,0 Single Supply
3,5 11.0 Single Supply
-15
4 Ch. SPST OG540
1 Ch, SPOT DG419
1 Ch. SPOT OG402
1 Ch, SPOT DGS050
1 Ch. SPOT DG5142
1 Ch. SPOT OG187
1 Ch. SPOT DG187
1 Ch, SPOT ~
1 Ch. SPOT OG301A
1 Ch, SPOT OG387A
V1nL lv'nH
0
0
I
15
4 Ch. SPST DG202
175
175
Switch
-15
-15
PMOS
CMOS +4
CMOS +4(
4 Ch. SPST DG201A
(V)
V+ to VV+ to V-
v-
CMOS +4
OG309
for aN
1--..-
15
15
15
t5
10
15
DG221
DG271
Supp.
Range
Input
V+
.l2lillZ
SPST
SPST
SPST
SPST
SPST
Voltage
Range
1.00
1,00
10.00
1,00
10.00
10,00
10
15
15
15
15
10
12
15
10
10
12
-16
-15
-20
-15
-15
-15
-15
-15
-20
-15
-18
-15
-15
-15
-15
-15
-20
-18
-15
-20
-20
-18
5
5
5
5
5
5
5
5
5
5
5
2000
30
30
30
30
20
15
125
125
125
200
150
150
20
800
30
30
30
300
300
250
1000
30
6
20
20
5
20
16
20
5
1000
20
20
75
76
75
125
130
130
1600
250
250
150
44
44
44
44
36
44
44
44
44
44
44
38
36
44
44
44
44
V+to VV+to V(V+) 10 (V-)+10
Vi-toV-
DIP
SO
CarOIP
OY
OY
AK.BK.CK
AK,BK,CK
OY
OY
AK,BK,OK
2.4 Latchabla Inputs
CJ
CJ
2.0 Chip Select Function
OJ
2.4 JAN Qualified
2.4 JAN Qualified
CJ
OY
AK,BK,CK
AK,BK,CK
0.8
2.4 Wldeband Video
0.8
2.4 Wldeband Video
OJ
OJ
ON
OY
I
0.8
2.4 low Cost
0
0.8
2.4 low Cost
CJ
CJ
OY
OY
0
0.5
4.6 low Standby Power
Note
V+ to VNote
V+ to VNote
V+to VNota
(V+) to (V-)+7.S Note
V+ to V-
6
6
6
6
6
Note 6
(V+)-2 to (V-)+8 NoteS
V+to VNota 6
V+to vV+ to VV+to V-
Nota 6
NoteS
NoteS
NoteS
250
800
36
300
1000
300
(V+) to (V-)+5 NoteS
(V+)-2 to (V-)+5 Nota 5
Note 6
1500
250
3S
36
(V+) to (V-)+10
(V+) to (V-) +7.
1000 2500
36
36
250
NoteS
Nota 6
(V+)-2 to (V-)+8 NoteS
Comments
CJ
2.4 Mini DIP, low Power
OJ
OJ
2.0
0,8
3.0 Use DG402 for New Designs
4.0 JAN Qualified
2.4 Use DG402 for New Designs
2.0 Usa DG402 for New Designs
2.0
USB
2.0
2,0
3,0
2,0
2,0
2.0
3,0
~
3.
4.
logic supply voltage required for TTL compatible Inputs.
Preliminary product. Specifications subject to change. Contact the factory for availability.
5.
lnput reference voltage of 2.SV Is required.
6.
See data sheets for SWitch states of differential and multlpla switches.
See IndiVidual data sheets for more details.
I
AZ
AP
AP
AL
AP,OF
AK
AK
AK,CK
AP,BP
AP,BP
AP,BP
CJ
CJ
AK,BK,CK
AK,BK,CK
OJ
AK,BK,CK
CJ
AL
AL
AL
AL
AL
AA,BA
AA,BA,CA
AA,BA,CA
AK,CK
Usa DG402 for New Designs
AL
AL
AL
AL
Usa DG402 for New Designs
Usa DG402 for New Designs
AP,BP
Use DG402 for New Designs
AP,BP
AL
AL
Use DG402 for New Designs
Usa DG402 for New Designs
AA.BA
AA,BA,CA
AP,BP
AP,BP
AP,BP
AP,BP
Not recommended for new designs.
For most products, the analog voltage ranga Is a function of supply voltages. For PMOS or CMOS switch, rDS(on) Is also a function of supply and
1.
2.
CJ
LCI Pack
Metal
Can
AK,BK,CK
DG402 for New Designs
0,8 4.0 Use DG402 for New Designs
3.5 11.0 JAN Qualified
0.8 2.4 Break-Befor&-Maka
0,8 2,0 Use 0G402 for New DeSigns
0,8
2.0
0,8
0,8
0.8
OJ
Flat
A2
AP.BP
0,8
0,8
0.8
0,8
0,8
0,8
2.4 low Power, High Perf.
2.4 low Charge Injection
Side
Braze
AP,BP
OJ
4,0 11,0 High V, Serial load
analog voltaga. Sea Individual data sheets for more details.
'f
c..>
Plaltl Plastl
CJ
CJ
500
130
130
1600
250
Package and Temperature Range Offerings:
Levels
Analog
MAX
1.00
1.00
1.00
1,00
1.00
1.00
1.00
DG308A
Ch.
Ch.
Ch,
Ch.
Ch.
Time
(ns MAX)
Volt.
Range
(2)
CMOS +4(
CMOS +4
CMOS +4(
4
4
4
4
4
50
100
100
100
150
Voltage
AA,BA
AA,BA
AA,BA
AA,8A
i
w
.J,..
ANALOG SWITCHES
Switching
Time
Supply
rOS(on
Functional
Conflgura-
Ch,
Ch,
Ch,
Ch,
Ch,
Ch,
Ch,
Part
Number
lion
2
2
2
2
2
2
2
Basic
SPD
SPD
SPD
SPO
SPD
SPe
SPD
OG423
DG403
OGS051
DGP3030'
DGSI43
DG542
DG190
2 Ch. SPO DGlgo
2
2
2
2
Ch,
Ch,
Ch,
Ch,
Ch,
2 Ch,
2 Ch,
SPD
SPD
SPD
SPO
SPD
SPe
SPe
Switch
Typo
CMOS +40
CMOS +40
CMOS +40
CMOS +40
CMOS +40
D/CMOS
N-JFET
N-JFET
OG307A CMOS +40
DG303A CMOS +40
~
CMOS +40
DG243
DGlgl
CMOS +40
00191
DGISQ
2 Ch, SPe DG189
2 Ch. SPO
CMOS +40
N-JFET
N-JFET
N-JFET
N-JFET
1 Ch. DPS DG404
1 Ch, OPS DGSI44
1 Ch, DPS ~
CMOS +40
2
2
2
2
2
2
CMOS+40
Ch,
Ch,
Ch,
Ch,
Ch,
Ch,
DPS
DPS
DPSl
DPS
DPS
OPS
NOTES: 1.
2.
DG425
DG405
DGS049
DGSI45
DGI84
DGI84
CMOS +40
CMOS +40
CMOS +40
CMOS +40
CMOS +40
N-JFET
N-JFET
MAX
I.n.)
(2)
ISloff)
MAX2
nA
25
25
25
50
30
0,25
0,25
0,50
0,50
0,50
Voltage
V+
V-
VL
(3)
-15
-16
-15
5
5
6
(ns Max)
Analog
MAX
-16
5
6
5
5
5
-15
-16
-15
5
5
5
30
30
30
125 75
200 125
1000 500
44
44
44
125
125
125
200
150
150
44
44
44
44
36
60
30
30
50
50
50
50
50
75
75
10
10
10.00
1,00
1,00
1,00
1,00
1,00
1,00
1,00
1,00
1,00
10,00
10,00
25
30
50
0,25
0,50
1,00
15
16
15
0,25
0,25
0,50
0,50
1,00
1,00
15 -16
-15
-3
-15
-20
-15
-15
-15
-15
-15
-20
-15
-20
15
-15
15
15
10
15
-15
-15
-20
-15
6
5
5
5
6
5
5
30
30
30
30
20
15
Range
toff Range
125 75
125 75
125 75
300 250
200 125
go 50
150 130
150 130
250 150
300 250
1000 500
300 250
1000 500
250 130
250 130
300 250
300 250
-22
Voltage
Supp.
Ion
30
30
30
30
30
10
15
20
30
30
30
30
30
20
20
20
15
15
15
15
22
15
12
15
10
15
15
15
15
15
10
15
10
16
25
25
25
30
30
30
Volt.
Range
(2)
75
76
75
125
130
130
44
44
44
44
44
18
IV)
v+ to vv+ to Vv+ to v-
v+ to vV+ taV-
Logic
Input
for ON
Switch
Not06
NoteS
Note 6
NoteS
NoteS
IV+) -5 10 V-
NoteS
NoteS
36
44
44
44
44
44
36
IV+) 10 IV-)+7,5
NoteS
V+ to VV+ to VV+ to V-
NoteS
to Vto v-
NoteS
IV+) 10 IV-)+5
Noto 6
Noto 6
36
IV+) 10 IV-)+7,5
NoteS
V+
v+
NotaS
NoteS
NoteS
Note 6
V+
to v-
Note 6
V+
to V-
Note 6
v+ to v-
Note 6
V+
to V-
v+ toVV+ to VV+ to v-
IV+) 10 IV-)+7,5
r-r-Comments
VlnL V lnH
0,8 2,4 On Board Latches
0,8 2,4 Low Power, High ParI,
0,8 2,4 low Charge Injection
0,8 4,0 High Precision
0,8 2,4 Usa DG403 for New Design
0,8 2,4 Wldeband Video
0,8 2,0 Usa DG403 for New Design
0,8 2,0 Usa DG4Q3 for New Design
3,5 11,0 JAN Qualified
0,8 4,0 JAN Qualified
0,8 2,4 Usa 00403 for New Design
0,8 4,0 Use OG403 for New Design
0,8 2,0 Use DG403 for New Design
0,8 2,0 Usa DG403 for New Design
0,8 2,0 Use DG403 tor New Design
0,8 2,0 Use OG403 tor New DeSign
0,8 2,0 Use DG403 for New Design
0,8
0,8
0,8
Nota 6 0,8
1
I
I
1
1
Package and Temperature Range Offerings:
logic
Levels
0,8
0,8
0,8
0,8
0,8
analog voltage. See Individual data sheets for more details.
logic supply voltage required tor TTL compatible Inputs.
4.
Preliminary product. Specifications subject to change. Contact the factory for availability.
5.
Input reference voltage of 2.5V Is required.
6.
See data sheets for SWitch states of differential and multiple switches.
See IndiVidual data sheets for more details.
OJ
OJ
OJ
OJ
CJ
OJ
CJ
OJ
OJ
OJ
CJ
OJ
CJ
OJ
2,4 Ion Board Latches
2,4
Power, High Perf,
2,4 ~se DG405 for New Designs
2,4 ~se DG405 tor New Designs
2,0 ~se DG405 for New Designs
2,0 ~sa DG405 for New Designs
OJ
!-ow
OY
DY
DY
OY
CerDlP
Side
Flat
Braze LCe Pack
OJ
OJ
CJ
Metal
Can
AI<
AZ
AI<
AI<
AZ
AI<
AK,CK
ON
DY
AP
AP,BP
AP,BP
AK,BK,CK
AK,BK,CK
AL
AL
AZ
AK,CK
AK,BK,CK
AK, CK
AP,BP
AP,BP
AP,BP
AP,BP
2,4 Low Power, High Perf.
2,4 Use DG404 for New DeSign
2,4 Use OG404 tor New Design
~ Not recommended for new designs.
For most products, the analog voltage range Is a function of supply voltages. For PMOS or CMOS switch, rOS(an) Is also a function of supply and
3.
Plastl Plastl
DIP
SO
AL
AL
AL
AL
AK
AK,CK
AK,CK
DY
DY
DY
AK
AK
IAz
AI<
AK,CK
jAP,BP
jAP,BP
AL
AL
~
S°(J)
0::::
00'
"0
'O::J
Qs('
a
CD
Co
\j
~
S'(/)
ANALOG SWITCHES
Functional
Conflgura-
Basic
Part
Number
lion
Switch
Type
2 Ch. DPST DGI85
2 Ch. DPST DG126
2 Ch. DPST DG183
2 Ch. DPSt DG140
00'
-'0
"0:;,
0
-'
-,x
Switching
Time
Supply
Voltage
V+
V-
VL
(3)
Volt.
Range
(ns Max)
MAX
Supp.
(2)
Ion
toff Range
1.00
12 -18
1600
36
1.00
15 -15
20
30
600
50
300
250
50
1.00
15 -15
30
250
150
50
50
1.00
1.00
15 -15
30
300
250
CMOS +40
15 -15
30
N-JFET
N-JFET
75
75
500
130
44
44
44
44
N-JFET
N-JFET
N-JFET
SO
N-JFET
2 Ch. DPST DG129
2 Ch. DPST DG302A CMOS +40
2 Ch. DPST DG306A CMOS +40
2 Ch. OPST DG384A CMOS +40
2 Ch. DPST ~
2 Ch. DPST DGI85
rOS(on)
IS (off)
MAX
(.0.)
MAX2
(2)
nA
0=
30
to
2 Ch. DPST DGI83
N-JFET
10
10
1 Ch. DPDT ~
1 Ch. DPDT ~
1 Ch. OPOT DGI45
N-JFET
30
N-JFET
N-JFET
80
10
Analog
Logic
Voltage
Range
Input
(V)
(V+)-2 to (V-)+8
V+ to V-
V+ to V-
V+to V-
v+ to V-
r--
for ON
Switch VlnL VlnH
0.8
I
I
1
0.8 4.0 JAN Qualified
3.5 11.0 JAN Qualified
0.8 4.0 Use DG405 for New Design
0.8 2.4 Use 0G405 for New Design
0.8 2.0 Use DG405 for New Design
1
1
0.8
0.8
1
1
0.8
0.8
1
0.8
I
1
1.00
15 -15
5
20
1.00
1.00
10 -20
12 -18
5
20
250
130
20
600
10.00
10.00
15 -15
5
16
300
1600
250
20
1000 2500
300
250
36
36
(V+)-2 10 (V-)+8
(V+) to (V-)+8
(V+)-2 to (V-)+8 NoteS 2.0
(V+)-2 to (V-)+5 NoteS 2.0
(V+)-2 to (V-)+8 NoteS 2.0
12 -18
5
36
36
10.00
10 -20
1.00
1.00
12 -18
12 -18
20
SOD
SOD
1600
36
36
10.00
12 -18
20
1000 2500
36
20
20
1600
(V+) to (V-)+5
(V+)-2 to (V-)+5
Comments
1
1000
250
6.
See data sheets for switch states of dlffarentlal and multiple switches.
c..>
0,
I
SO
CorOlP
CJ
AK,BK,CK
CJ
AK,BK,CK
CJ
CJ
AK,BK,CK
AK,CK
Side
Flat
Braze LCC Pack
AP,BP
AL
AL
AP,BP
2.5 Use DG4D5 for New Design
2.0 Use DG405 for New Design
AL
AL
AP,B?
2.5 Use DG40S for New Design
2.0 Use DG40S for New Design
AP,BP
AP,BP
3.0 USB 0G403 for New Design
AP,BP
AP,ap
AP,ap
3.0 Use 0G403 for New Design
3.0 Use 0G403 fot New Design
0.
Metal
Can
I
AP,BP
2.0 Use DG405 for New Design
NOTES: 1. ~ Not recommended for new designs.
2. For most products, the analog voltage range Is a function of supply voltages. For PMOS or CMOS SWitch, rOS(on) Is also a function of supply and
analog voltage. Saa Individual data sheets for more details.
logic supply voltage required for TTL compatible Inputs.
Preliminary product. Specifications subject to change. Contact the factory for availability.
Input reference voltage of 2.SV Is required. See Individual data sheets for more details.
PI~~C Plestl
2.6 Use DG405 10r New Designs
---
3.
4.
5.
!!!.
([)
Package and Temperature Range Offerings:
Logic
Levels
AP,BP
AL
AL
AL
AL
AL
AL
AA,BA
AA,BA
Cf
m
DRIVERS
Package and Temperature Ranges:
Basic
#
Part
of
0125
logic for VlnL Vln~
VOUTL (V) (V)
01
Number Inputs
Function
Outputs
6
6
MAX
Input
#
Six Separate
MAX
Output Drive
Output
Break
Current
(mA)
Swing
(V)
down
(V)
Optimum Supply Voltage
len
lotI
(ns)
(ns)
V+
V-
VL
0
0.5
4.6
-5
-30
36
500 1500
10
-20
5
1
0.7
2.2
-10
50
50
300 1500
10
-20
5
0
10
30
36
170
200
10
-20
5
0
Side
Braze
Plastic
Comments
VR
DIP
CelOIP
4
7
Four Channel Driver
Metal
Can
AP
AL
AP/883 1AL/883
JFET Drivers
Drivers
0129
Flat
Pack
JFET Drivers
with Decode
0139
4
2
Note 3
Dual Driver with
0
5
0169
4
2
Note 3
Dual Driver With
0.8
33
+/-40
2
36
170
200
-15
15
5
Smaller MOSPOWER
0
Outputs
4
8
Quad Driver with
Note 3
0.8
3
+/- 500
Nota 3
0.8
2.4
+1-100
12.6
8
8
AI(
AP
AK/863 AP/863
14
100
100
12
0
nla
nla
MOSPOWEA Driver,
4 Separate Drivers,
Low-V H-Brldge Driver
CJ
AP
AP/863
BP
44
100
100
15
-15
nla
nla
FET Driver. 8 Separato
Drivers, Serial Data Input
OJ
AP
Complementary
Inputs
0470
AP
AP/863
CJ
Driver I 2-112 Bridge
Lewl Shifter. Line Driver
Complementary
0469
CJ
Level Shifter I
JFET Driver
Decode
Octal Driver with
Serial Input
+/-15
AA
AA-2
FET SWITCHES
Capacitances (pF)
Pull-up
Basic
SWitch
Part
Number
G118
G119
S05000
S05001
S05002
S05400
SD5401
SD5402
Sources
6
6
4
4
4
4
4
4
Drains
1
2
4
4
4
4
4
4
Gates
Typo
8
3
4
4
4
OP3T
4 X SPST
4 X SPST
4
4
4
SP6T
4
4
4
4
X SPST
X SPST
X SPST
X SPST
On
Gate
No
Ves
No
No
No
No
No
No
VGS(lh)
rOS(on)MAX
VS = 10V
100
100
50
50
50
50
50
50
VS = -10 V BVOSS
450
450
-30
-30
20
10
15
20
10
15
IS (off)
(nA)
MIN
MAX
0.5
0.5
10.0
-1.5
10.0
10.0
10.0
10.0
10.0
0.1
0.1
0.1
0.1
0.1
-4.0
-4.0
2.0
2.0
2.0
-1.5
0.1
2.0
2.0
2.0
egs
(Cg)
MAX
0.9(lyp)
1.8(lyp)
(3.5)
(3.5)
(3.5)
(3.5)
(3.5)
(3.5)
GIs
(Cd)
MAX
0.4(typ)
0.4(lyp)
(1.6)
(1.6)
(1.6)
(1.6)
(1.6)
(1.6)
Csb
(Cs)
MAX
Packages and Temp.
Sid.
Braze
Flat
Pack
2(typ)
AP,AP-2
AL,AL-2
2(typ)
(5)
(5)
(5)
(5)
(5)
(5)
AP,AP-2
AL,AL-2
tq
3'cn
00'
0=
"0
'0::>
QX·
~
a.
\i
tq
s·w
ANALOG MULTIPLEXERS
0=
00'
-'0
"O:::l
MAX
rOS(on)
Basic
Part
Number
Function
Input
Latche,
(.e.)
ID(off)
(2)
(nA)
Analog
Range
(V)
(2)
rans
V-
+1-15
-5 to +10
0.2
0.2
0.2
0.3
O.B
O.B
O.B
O.B
+/-15
+/-15
O.B
2.4
15
-15
0.6
0.6
0.6
O.B
O.B
O.B
3.5
3.5
3.5
2.4
2.4
2.4
-20
-20
-20
-15
-15
-15
2.0
1.0
5
6
10
15
15
15
4.0 11.0 60
O.B 2.4 15
4.5 10.5
4.5 10.5
O.B 2.4
O.B 2.4
15
15
16
15
0
0
-15
-15
Latches On Board
OJ
-15
-5
High Performance
Wldeband/Vldeo
DJ
DJ
Wldeband/Vldeo
DJ
Eight Channel MUX .... Enable
DG90B
NO
1000
1
+/-15
1.0
Eight Channel MUX + Enable
DG501
Eight Channel MUX + Enable
Eight Channel MUX + Enable
~
NO
NO
NO
NO
NO
YES
YES
NO
150
150
150
400
400
+/-5
+/-5
400
100
1500
B
B
B
2
10
10
1.5
1.5
1.5
1.0
1.0
1.0
120
10
+/-50
Eight Channel MUX + Enable
Eight Channel MUX + Enable
Eight Channel MUX + Enable
Eight Channel MUX + Enable
+1-15
+/-15
+/-15
-60
-16
90
10
o to 10
10
10
10
o to 10
YES
90
400
400
+/-15
0.3
0.3
1.0
1.0
DG409
DG53B
NO
YES
100
90
1
10
+/-15
-5 to +10
0.2
0.3
O.B
O.B
2.4
2.4
15
15
Four Ch. Single/Two Ch. Diff. MUX
DG534
YES
90
10
-5 to +10
0.3
O.B
2.4
15
-5
Four Channel Dual MUX
NO
YES
NO
YES
400
400
400
100
10
10
10
120
+/-15
+/-50
1.0
1.0
1.0
2.0
O.B
O.B
O.B
4.0
2.4 15
2.4 15
2.4 15
11.0 60
-15
-15
-15
Four Channel Dual MUX
DGP509A
DG529
DG509A
DG569
Eight Channel Dual MUX + Enable
DG507A
Eight ChaMaI Dual MUX + Enable
DG527
NO
YES
400
400
5
5
+1-15
+1-15
1.0
1.0
O.B
0.8
YES
YES
NO
Sixteen Channel MUX + Enable
DG536
DG535
DG506A
DG526
Four Channel Dual MUX
Eight Ch. Single/Four Ch. Dlff. MUX
Sixteen Channel MUX + Enable
Sixteen Channel MUX + Enable
Sixteen Channel MUX + Enable
Four Channel Dual MUX
Four Channel Dual MUX
+1-15
+/-15
+/-15
5
Any 01 Eight
Low Power DG480
Plastl
DIP
15
15
15
15
1
1
1
10
+/-10
+/-15
Comments
2.4
2.4
2.4
2.4
75
75
100
90
DG503
DGP50BA
DG50BA
DG52B
DG56B
DG54BA
VL
-15
-15
-15
-5
YES
YES
NO
YES
2.4
2.4
15
15
-60
-15
-15
High Performance
Wldeband/Vldeo
Fault Protected
OJ
OJ
DJ
DJ
DJ
CarOlP
Latches On Board
15
High Voltage
Over Vol. Prot.
2.
15
~
I
AL
AL
CY,DY
CY,DY
AK,BK,CK
BP
AK,BK
AZ
AP
AK,BK,CK IAR,BR,CR
AK,BK,CK
DY
DN
AZ
DY
AK
AP
AP
Precision
High Voltage
AK,BK,CK
AK,BK,CK
AK,BK,CK
OJ
OJ
AK,BK,CK IAR,BR,CR
Latches On Board
AZ
AZ
AK,BK,CK
DN
DN
AZ
DY
AZ
DY
BP
For most products, the analog voltage range Is a function of supply voltages. For PMOS or CMOS switch, rDS(on)ls also a function of supply and
c..>
AZ
AK,BK,CK
2QQS. Not recommended for new designs.
analog voltage. See Individual data sheets for more details.
192P
AP,BP
AK,BK,CK
CJ
OJ
OJ
OJ
Latches On Board
DN
DY
AM
DJ
OJ
SO
AP,BP
WldabandNldeo
WldebandIVldeo
AZ
AK
142K,I43K
OJ
DJ
CJ
CJ
CJ
CJ
Hermetic Quad Flat
Quad/LOe PLC( Pack
I
DY
AP
OJ
Precision
Side
Braze
AK
AK
AK
--
Notes: 1.
~x'
CD
Package and Temp. Range Offerings:
vO'l~fes
(JIS) VlnL V lnH V+
DG4BO
DG485
DG408
DG53B
Eight Channel MUX + Enable
Supply
Time
Eight Ch. Serial Input Switch Array
Eight Channel MUX + Enable
Eight Ch. Single/Four Ch. Dlff. MUX
Eight Ch. Serial Input Switch Array
logic
Levels
(V)
AZ
I
I
a.
VJ
OJ
HIGH VOLTAGE MULTIPLEXERS
Part
Number
Function
Eight Channel MUX
+ Enable
Four Channel Dual MUX
Analog
Voltage
MAX
Basic
Input
Latches
rDS(on)
(,0, )
Transition
Logic Levels
(V)
Supply Voltages
IO(OFF)
(nA)
Range
(V)
Time
(JIS)
Vlnl
VlnH
V+
V-
VL
2.0
4.0
11.0
60
-60
2.0
4.0
11.0
60
-60
OG568
YES
100
120
(V+) - 10 to (V-)
OG569
YES
100
120
(V+) - 10 to (V-)
Pkg. and Temp.
(V)
Plastic
Side Braze
DIP
DIP
15
CJ
AP,BP
15
CJ
AP,BP
DATA CONVERSION PRODUCTS: AIDs AND D/As
Function
8 Ch. Data Acq. Sys.
~ Ch. Data Acq. Sys.
Basic
Rosol ...
Part
tlon
Number
818601
SI8602
SI8603
SI8604
Successive Approx. Reg.
SI2504
S17135
4 1/2 Digit AID Converter
L01201121A
4 112 Digit AID Converter
4 1/2 Digit AID Converter
LOI221121A
3 1/2 Digit AID Converter
LOll0llllA
S17533
CMOS Mult. DAC
S17541
CMOS Mult. OAC
S17541A
CMOS Mult. OAC
SI7240
CMOS Voltage Out DAC
CMOS Mult. DAC w/Latches S17545
CMOS Mult. DAC w/Latches S17542
CMOS Mult. DAC Serial In
S17543
AID Converter
AID Converter
(Bits)
8
8
8
8
12
15
15
15
11
10
12
12
12
12
12
12
INL
Gain
Error
± LSB
0.5
0.5
0.25
0.25
nla
1
1
1
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Settling!
Converslon
Time
logic
Levels
(VSupply =
15 V)
Logic
Levels
(VSupply =
5V)
Package and Temp. Range Offerings:
MAX
Supply
Volt
HermePlastic
(jIS)
VlnL
VlnH
Vinl
VinH
0.25
0.25
0.25
0.25
nla
25.0
25.0
25.0
25.0
nla
ni.
1.5
nla
1.5
nla
nia
13.5
nla
13.5
nla
1.5
nla
1.5
nla
0.8
1
1
1
1
14
12.5
1
1
1
1
1
500000
200000
200000
25000
0.6
0.6
0.6
0.6
2
2
2
nla
0.5
0.5
0.5
0.8
0.8
0.8
0.8
1.5
0.8
0.8
nla
4
4
4
2.4
2.4
2.4
2.4
13.5
2.4
2.4
0.8
nla
nla
nl.
nl.
nl.
nla
nla
0.8
0.8
0.8
3.5
nla
3.5
nla
2.4
2.8
nla
nla
nla
nla
nla
nla
nla
2.4
2.4
2.4
V+
V-
Comments
6.5
o II P Interface, 8tH on-board
o liP Interfacs, 8tH on-board
15
o II P Interface, SJH on-board
6.5
o JlP Interface, 8tH on-board
15
o 40 MHz Operation, Low Power
7.5
-9 DVM/DMM Applications
6
15 -15 DVM/DMM Applications
15 -15 DVM/DMM Applications
15 -15 DVM/DMM Applications
15
a Replaces AD7520 and AD7533
15
o Reduced Output Capacitance
o Reduced Output Capacitance
15
15
o Reduced Output Capacitance
a JlP Compatible
15
o 4 Bit Bus Input
15
15
o Serial In
DIP
OJ
OJ
OJ
OJ
CJ
CJ
CJ
CJ
CJ
IN,KN,LN
IN,KN
IN,KN
IN,KN
IN,KN,LN
IN,KN,GKN
IN,KN,GKN
CerOIP
Side
Braze
tic
Quadl
LCC
AK, AKI883
AK, AKI883
AK, AKI883
Quad
PLCC
ON
AK, AKI883
ON
AK
CK
AQ,BQ,CQ
ON
SO,TO,UO
SO,TO
SO,TO
SO,TO
SO, TO, GUO
SO,TO,GTO
SO,TO,GTO
TE
TE
TE
TE
GUE
GUE
GUE
JP,KP
JP,KP
JP,LP
tq
s·C/)
Notes: 1.
2.
~ Not recommended for
0=
new designs
For most products, the analog voltage range Is a function of supply voltages. For PMOS or CMOS switch,
analog voltage. See Individual data sheets for more details.
rDS(on) is also a function of supply and
00'
"'0
'0:;,
0-'
..,x
III
m
c.
,,
tq
:rcn
0=
LINEARS
00'
-.0
"0::1
Qx'
i
Co
Pkg. and Temp. Aangest
Functional
Configuration
Basic
Part
Number Technology
Open
Loop
Gain
(dB)
TC
MIN
MAX
Input
Input
Supply Supply
Offset
Offset
Voltage Voltage Voltage
(jlV/oC)
(V)
(V)
(mV) MAX
Comments
DIP
Side
Braze
Programmable Supply Current
CJ
AP,BP, 1883
CJ
AP,BP, 1883
Plastic
Triple Op Amp
L144
Bipolar
80.0
+1-1.5
+/-18
5.0
Quad Comparator
L161
Bipolar
80.0
+1-1.5
+/-18
3.0
nla
Programmable Supply Current
CMOS
120.0
+/-3
+/-9
0.005
0.05
Ultra Precision
Chopper Stabilized Op Amp S17652
3.3
OJ,OH
CorDIP
Metal
Can
OK
OA
HIGH-VOLTAGE DISPLAY DRIVERS
Part
Number
Description
MaxlmumClock
Rate
TA = 25°0
Pkg. & Temp Ranges:
Output Voltage
@
Rated Currant
Supply Voltages
=0.5 rnA
CN
AM
VL
10.8 to 15 V
VOO =60V
=
IL
100
= 0.5 rnA
=1 rnA
CN
AM
V L = 10.8 to 15 V
VOO=80V
IL
100
= 0.6 rnA
=5 rnA
CN
AM
IL
= 0.5 mA
CN
OM
100
=8 rnA
4 MHz
YOLO =30 V(MAX) @8OmA
IOFF 10jl A@ VOO = 200 V
VL
8195531
819554
32-Channal Push-pull
Output AC EL Column
Drivers w/Serlal Data
Input
10 MHz
YOLO = 8 V(MAX) @ 15 rnA
VOHO = 50 V(MIN) @ 15 rnA
8195551
819556
32-Channel Push-pull
Output AC EL Column
Driver w/Serlal Data
Input
10 MHz
YOLO = 8 V(MAX) @ 15 rnA
VOHO = 70 V(MIN) @ 15 mA
819560
34-Channel
Symmetric AC
ELRow Orl_
4 MHz
YOLO
= 30 V(MAX) @ 70 rnA
VOHO
=
VL
= 10.8 to 15 V
VOO =225 V
Notes: 1. Assuming 1 rnA of constant--current drive.
Available In Commercial. Industrial. and MIlitary versions
w
cb
I
44-Pln
CLCC
IL
32-Channel Open Drain
Output AC EL Row Drlvars w/Serlal Data Input
*
44-Pln
PLCC
= 10.8 to 15 V
S195511
SI9552
195 V(MIN) @ 70 mA
Supply Currents
(Worst Case Over Temp.)
.
w
~
o
VOLTAGE CONVERTERS
MAX
Basic
Part
Functional
Technology
MIN
MAX
MIN
Pkg. & Temp. Ranges:
MAX
Input Supply Supply Output Output
Current Voltage Voltage Voltage Voltage
(rnA)
Configuration
Number
Voltage Doubler Iinverter
517660
CMOS
0.5
Voltage Doubler Iinverter
517661
CMOS
2.0
(V)
(V)
(V)
(V)
1.5
10
-10.0
20.0
60.0
20
-20.0
40.0
Comments
Increased Voltage Range
Plastic
Metal
DIP
Can
SO
CJ
AA, AA/883
CY
CJ
AA, AA/883
CY
SWITCHMODE REGULATORS/CONTROLLERS*
Pkg. & Temp. Ranges:
Basic
Part
Number
519100
TYP
I SOURCE
(rnA)
TYP
I SINK
(rnA)
VREF
Plastic
Accuracy
DIP
-
-
-
::t 1%
DJ
TYP
MAX
MAX MAX
V,N VOUT rDS(ON) ROUT
(,0,)
(,0,)
(V)
(V)
70
150
5
Cerdlp
Surface-Mount
AK
DN
519101
70
150
5
-
-
-
:t 10%
DJ
AK
DN
819102
120
200
7
-
-
-
± 1%
DJ
AK
DN
819110
120
-
150
200
::!::1%
DJ
AK
DY
120
-
20
519111
20
150
200
±10%
DJ
AK
DY
$191151
819116
300
-
-
-
150
200
± 1%
DJ
AK
DY
*
Regulators (819100/01/02) have onboard output MOSFETs,
Controilers (819110/11/15/16) are designed to drive external MOSFETs.
~
S'!:Q
85'
"0
'0:>
0
-'
.,x
!>l
(jj
a.
Cross Reference
lEI
B
Cross Reference
Siliconix
incorporated
Sillconix Direct Replacement
Suggestions are based on the similarity of, mechanical and electrical
characteristics, as reported in the manufacturer's published data.
Interchangeability is not guaranteed. Before selecting a device as a substitute, compare the specifications.
Siliconix Similar Replacement
Suggestions are based on the similarity of electrical characteristics, as
reported in the manufacturer's published data. Interchangeablity is not
guaranteed, as these parts may have different pin configurations. Before
selecting a device as a substitute, compare the specifications. For devices
not shown in this guide, or for additional information, the user should contact
the nearest Siliconix sales office.
SlIIconlx
Part
Number
ADG200AA
ADG200AA/883
ADG200AP
ADG200AP/883
ADG200BA
ADG200BP
ADG200CJ
ADG201ABO
ADG201AKN
ADG201AP
ADG201AP/883
ADG201ATO
ADG201ATO/883
ADG201BP
ADG2010J
ADG202ABO
ADG202AKN
ADG202ATO
AD0145CD
AD7240JN
AD7240KN
AD7240AO
AD7240BO
AD7240TD
AD72405D
AD7501JD
AD7501JN
AD7501KD
AD7501KN
AD75015D
AD7503JD
AD7503JN
AD7503KD
AD7503KN
AD75035D
AD7506JD
AD7506JD/883
AD7506JN
AD7506KD
AD7506KN
AD75065D
AD7506TD
AD7507JD
AD7507JD/883
AD7507JN
AD7507KD
AD7507KN
AD75075D
AD7507TD
AD7508KD
AD7508KN
AD75085D
AD7509KD
AD7509KN
AD75095D
AD7521JN
Direct
Replacement
SlIIconlx
Similar
Replacement
DG200AAA
DG200AAA/883
DG200AAP
DG200AAP1883
DG200ABA
DG200ABP
DG200ACJ
DG411AK
DG411DJ
DG411AK
DG411AK/883
DG411AK
DG411AK/883
DG411AK
DG411DJ
DG412AK
DG412DJ
DG412AK
DG145BP
517240JN
517240KN
517240AO
517240BO
517240TD
5172405D
DG501BK
DG501CJ
DGS01BK
DG5010J
DGS01AK
DGS03BK
DGS030J
DGS03BK
DGS030J
DGS03AK
DGS06ABK
DGS06AAR/883
DG506AOJ
DG506ABR
DGS06ACJ
DGS06AAK
DGS06AAR
DGS07ABK
DGS07AAR/883
DGS07AOJ
DGS07ABR
DG507ACJ
DG507AAK
DGS07AAR
DGS08ABK
DGS08ACJ
DG508AAK
DG509ABK
DGS09ACJ
DGS09AAK
517541AJN
Part
Number
AD7521JP
AD7521KN
AD7521KP
AD7521LN
AD75215D
AD7521TD
AD7521UD
AD7533AO
AD7533BO
AD753300
AD7533JN
AD7533KN
AD7533LN
AD7533LP
AD75335D
AD7533TD
AD7533UD
AD7541AAO
AD7541ABO
AD7541AJN
AD7!';41AJP
AD7541AKN
AD7541AKP
AD7541AO
AD7541A5D
AD7541A5D/883
AD7541ATD
AD7541ATD/883
AD7541BO
AD7545AO
AD7545BO
AD754500
AD7545GOO
AD7545GLN
AD7545GUD
AD7545JN
AD7545JP
AD7545KN
AD7545LN
AD7545LP
AD75455D
AD75455D/883
AD7545TD
AD7545TD/883
AD7545UD
AD7545UD/883
AD7820LN
AD7820KN
AD7820LP
AD7820KP
AD7820CO
AD7820BO
AD7820UO
AD7820TO
AH0126CD
SlIIconlx
Direct
Replacement
SlIIconlx
Similar
Replacement
517541AJP
517541AKN
517541AKP
517541AKN
517541A5D
517541ATD
517541A5D
517533AO
517533BO
51753300
517533JN
517533KN
517533LN
517533LP
5175335D
517533TD
517533UD
517541AAO
517541ABO
517541AJN
517541AJP
517541AKN
517541AKP
517541AO
517541A5D
517541A5D883
517541ATD
517541ATD883
517541BO
517545AO
517545BO
51754500
517545GCO
517545GLN
517545GUD
517545JN
517545JP
517545KN
517545LN
517545LP
5175455D
5175455D/883
517545TD
517545TD/883
517545UD
517545UD/883
517820LN
517820KN
517820LP
517820KP
517820CO
517820BO
517820UO
517820TO
DG126BP
III
4-1
Cross Reference
Part
Number
AH0126D
AH0126DI883
AH0129CD
AH0129D
AH0129D1883
AHOl33CD
AH0133D
AH0133D1883
AH0134CD
AHOl34D
AH0134D1883
AH0139CD
AH0139D
AH0139DI883
AH0140CD
AH0140D
AH0140D1883
AH0141CD
AH0141D
AH0141 D1883
AH0142CD
AH0142D
AHOl43D
AH0143DI883
AHOl44CD
AHOl44D
AH0144D1883
AH0145D
AH0145DI883
AH0146CD
AH0146D
AH0146D1883
AH0151CD
AH0151D
AH0151D1883
AH0152CD
AH0152D
AH0152DI883
AH0153CD
AH0153D
AH0153D1883
AH0154CD
AH0154D
AHOl54DI883
AH0161CD
AH0161D
AH0161DI883
AH0162CD
AH0162D
AH0162DI883
AHOl63CD
AH0163D
AH0163DI883
AH0164CD
AH0164D
AH0164D1883
AM25L04XC
AM2504C
AM2504XC
AM3705CD
AM3705D
AN0120NA
AN0130NA
AN0140NA
CDG201AK
CDG201BJ
CDG201BK
CDG211CJ
CDG308AK
CDG308BJ
CDG308BK
CDG308CJ
CDG308J
CDG308N
4-2
Slllconlx
Direct
Replacement
H
SlIIconlx
Similar
Replacement
DG126AP
DG126API883
DG129BP
DG129AP
DG129AP1883
DGl33BP
DGl33AP
DGl33API883
DGl34BP
DGl34AP
DGl34API883
DG139BP
DG139AP
DG139API883
DG140BP
DG140AP
DG 140AP 1883
DG141BP
DG141AP
DG141AP1883
DG142BP
DG142AP
DG143AP
DG143API883
DG144BP
DG144AP
DG144AP1883
DG145AP
DG145API883
DG146AP
DG146AP
DG146AP1883
DG141BP
DG141AP
DG141AP1883
DG133BP
DGl33AP
DGl33API883
DG140BP
DG140AP
DG 140AP 1883
DG129BP
DG129AP
DG 129AP 1883
DG146AP
DG146AP
DG146API883
DG144BP
DG144AP
DG144API883
DG145BP
DG145AP
DG145API883
DG139BP
DG139AP
DG139AP1883
SI25HC04CJ
S125HC04CJ
S125HC04CJ
DG501BP
DG501AP
SN0120NA
SN0130NA
SN0140NA
DG411AK
DG411DJ
DG411AK
DG411DJ
DG411AK
DG411DJ
DG411AK
DG411DJ
DG411AK
DG411DJ
Part
Number
CDG309AK
CDG309BJ
CDG309BK
CDG309CJ
CDG309J
CDG309N
D123AK
D123AKIHR
D123AP
D123AP-2
D123API883
D123BK
D123BP
D125AKIHR
D125AL
D125AL-2
D125ALIHR
D125ALl883
D125AP
D125AP-2
D125API883
Dl25BK
Dl25BP
D129AK
D129AL
D129AL-2
D129ALlHR
D129ALl883
D129AP
D129AP-2
D129APIHR
D129API883
D129BK
D129BP
D139AA
D139AA-2
D139AAI883
D139AP
D139AP-2
D139AP1883
D139BA
D139BP
D139CJ
D169AK
D169AK-2
D169AKI883
D169AP
D169AP-2
D169API883
D169CJ
D469AP
D469AP-2
D469API883
D469BP
D469CJ
D470AP
D470API883
D470DJ
DG123AL
DG123AL-2
DG123ALIHR
DG123ALl883
DG123AP
DG123AP-2
DG123APIHR
DG123API883
DG123BP
DG125AL
DG125AL-2
DG125ALIHR
DG125ALl883
DG125AP
DG125AP-2
DG125APIHR
Sillconix
Direct
Replacement
Siliconix
incorporated
Siliconix
SlmIJar
Replacement
DG412AK
DG412DJ
DG412AK
DG412DJ
DG412AK
DG412DJ
D123AP
D123AKI883
D123AP
D123AP1883
D123AP1883
D123BP
Dl23BP
Dl25API883
D125AL
D125ALl883
Dl25ALl883
D125ALl883
D125AP
D125API883
D125AP1883
D125BP
D125BP
D129AP
D129AL
D129ALI883
D129ALl883
D129AL1883
D129AP
D129API883
D129AP1883
D129API883
D129BP
D129BP
D139AA
D139AA1883
D139AAI883
D139AP
D139API883
D139API883
D139AA
D139BP
D139CJ
D169AK
D169AK1883
D169AK1883
D169AP
D169AP1883
D169AP1883
D169CJ
D469AP
D469API883
D469API883
D469BP
D469CJ
D470AP
D470AP1883
D470DJ
DG123ALI883
DG123AL1883
DG123ALl883
DG123ALl883
DG123AP
DG123API883
DG123API883
DG 123AP1883
DG123BP
DG125ALI883
DG125ALI883
DG125ALl883
DG125ALl883
DG125AP
DG125AP1883
DG125API883
':;:f
H
Cross Reference
Siliconix
incorporated
Part
Number
DG125AP/883
DG125BP
DG126AK
DG126AK/HR
DG126AK/883
DG126AL
DG126AL-2
DG126ALIHR
DG126AL/883
DG126AP
DG126AP-2
DG126APIHR
DG126AP/883
DG126BK
DG126BP
DG129AK
DG129AK/HR
DG129AK1883
DG129AL
DG129AL-2
DG129ALlHR
DG129AL/883
DG129AP
DG129AP-2
DG129AP/HR
DG129AP1883
DG129BK
DG129BP
DG133AK
DG133AK/HR
DG133AKI883
DG133AL
DG133AL-2
DG133ALIHR
DG133AL1883
DG133AP
DG133AP-2
DG133AP/883
DG133BK
DG133BP
DG134AK
DG134AK-2
DG134AK/HR
DG134AKI883
DG134AL
DG134AL-2
DG134ALIHR
DG134AL/883
DG134AP
DG134AP-2
DG134AP1883
DG134BK
DG134BP
DG139AK
DG139AKIHR
DG139AK1883
DG139AL
DG139AL-2
DG139AL/HR
DG139AL/883
DG139AP
DG139AP-2
DG139APIHR
DG139AP1883
DG139BK
DG139BP
DG140AK
DG140AKIHR
DG140AK1883
DG140AL
DG140AL-2
DG140ALIHR
DG 140AL/883
Sillconix
Direct
Replacement
Similar
Part
Direct
Sillconix
Similar
Replacement
Number
Replacement
Replacement
DG125AP/883
DG125BP
DG126AP
DG126AP/883
DG 126AP1883
DG126AL/883
DG126ALI883
DG126AL1883
DG126AL/883
DG126AP
DG126AP/883
DG126AP1883
DG126AP/883
DG126BP
DG126BP
DG129AP
DG129AP1883
DG129AP/883
DG129ALI883
DG129ALl883
DG129ALl883
DG129AL1883
DG129AP
DG129AP1883
DG129API883
DG129AP/883
DG129BP
DG129BP
DG133AP
DG133API883
DG133AP/883
DG133AL1883
DG133ALl883
DG 133ALl883
DG133ALI883
DG133AP
DG133API883
DG133AP/883
DG133BP
DG133BP
DG134AP
DG134AP1883
DG134AP/883
DG134AP/883
DG134AL1883
DG134ALl883
DG134AL/883
DG134AL/883
DG134AP
DG134AP/883
DG134AP1883
DG134BP
DG134BP
DG139AP
DG139AP1883
DG139/883
DG139AL1883
DG139AL1883
DG139ALl883
DG139ALl883
DG139AP
DG139AP/883
DG139AP1883
DG139AP/883
DG139BP
DG139BP
DG140AP
DG140AP/883
DG140/883
DG140AL1883
DG140AL/883
DG140AL/883
DG140AL/883
SlIIconlx
SlIIconlx
DG140AP
DG140AP-2
DG140AP/HR
DG140AP/883
DG140BK
DG140BP
DG141AK
DG141AKIHR
DG141AKI883
DG141AL
DG141AL-2
DG141AL/HR
DG141ALl883
DG141AP
DG141AP-2
DG141APIHR
DG141AP1883
DG141BK
DG141BP
DG142AK
DG142AK/HR
DG142AK1883
DG142AL
DG142AL-2
DG142ALIHR
DG142AL/883
DG142AP
DG142AP-2
DG142APIHR
DG142API883
DG142BP
DG143AK
DG143AK/HR
DG143AK1883
DG143AL
DG143AL-2
DG143ALlHR
DG143AL/883
DG143AP
DG143AP-2
DG143AP/HR
DG143AP/883
DG143BK
DG143BP
DG144AK
DG144AK/HR
DG144AK/883
DG144AL
DG144AL-2
DG144ALIHR
DG144ALl883
DG144AP
DG144AP-2
DG144APIHR
DG144AP1883
DG144BK
DG144BP
DG145AK
DG145AK-2
DG145AK/HR
DG145AL
DG145AL-2
DG145ALIHR
DG145AL/883
DG145AP
DG145AP-2
DG145APIHR
DG145AP1883
DG145BK
DG145BP
DG146AP
DG146AK-2
DG146AK/HR
DG140AP
DG140AP/883
DG140AP/883
DG140AP/883
DG140BP
DG140BP
DG141AP
DG141AP1883
DG1411883
DG141ALI883
DG141ALI883
DG141AL1883
DG141ALl883
DG141AP
DG141AP/883
DG141AP/883
DG141AP1883
DG141BP
DG141BP
DG142AP
DG142AP/883
DG142AP/883
DG142AL1883
DG142ALl883
DG142ALI883
DG142AL1883
DG142AP
DG142AP/883
DG142AL1883
DG142AP/883
DG142BP
DG143AP
DG143AP/883
DG143AP1883
DG143AL/883
DG143AL1883
DG143ALI883
DG143ALl883
DG143AP
DG143AP/883
DG143API883
DG143AP/883
DG143AP
DG143AP
DG144AP
DG144AP1883
DG144API883
DG144AL/883
DG144AL/883
DG144ALI883
DG144ALl883
DG144AP
DG144API883
DG144API883
DG144AP1883
DG144AP
DG144AP
DG145AP/883
DG145AP/883
DG145API883
DG145ALl883
DG145AL/883
DG145ALl883
DG145AL/883
DG145AP
DG145API883
DG145AP1883
DG145AP1883
DG145BP
DG145APDG146AK
DG146AP/883
DG146AP1883
4-3
III
Cross Reference
Part
Number
DGI46AK/883
DG146AL
DGI46AL-2
DG146AL/HR
DGI46AL/883
DG146AP
DG146AP-2
DG146AP/HR
DG146AP/883
DG146BK
DG146BP
DG151AL
DGI51AL-2
DGI51ALl883
DG151AP
DGI51AP-2
DGI51AP/B83
DG151BP
DGI52AL
DGI52AL-2
DGI52AL/883
DG152AP
DGI52AP-2
DGI52AP/B83
DGI52BP
DGI53AL
DGI53AL-2
DGI53ALl883
DGI53AP
DGI53AP-2
DGI53AP/883
DGI53BP
DGI54AL
DGI54AL-2
DGI54AL/883
DGI54AP
DGI54AP-2
DGI54AP/B83
DGI54BP
DG161AL
DGI61AL-2
DGI61AL/883
DG161AP
DG161AP-2
DGI61AP/883
DG161BP
DGI82AL
DGI82AL-2
DGI82ALl883
DGI82AP
DGI82AP-2
DGI82AP/883
DGI62BP
DGI63AL
DGI63AL-2
DGI63AL/883
DGI63AP
DGI63AP-2
DGI63AP/883
DGI63BP
DGI64AL
DGI64AL-2
DGI64AL/B83
DGI84AP
DG164AP-2
DGI84AP/883
DGI64BP
DG172AL
DGI72AL-2
DGI72AL/883
DG180AA
DGI80AA-2
DGI80AA/883
4-4
H
Siliconix
Direct
Siliconix
Similar
Replacement
Replacement
DGI46AP/883
DG146AL
DG146AL/883
DGI46AL/883
DGI46ALl883
DG146AP
DGI46AP/883
DGI46AP/883
DGI46AP/883
DG146AP
DG146AP
DG141AL
DGI41AL/883
DG141AL/883
DG141AP
DG141AP/883
DG141 AP/883
DG141BP
DGI33AL
DGI33AL/883
DGI33AL/883
DGI33AP
DGI33AP/883
DGI33AP/883
DG133BP
DG140AL
DGI4AL/B83
DGI40AL/883
DG140AP
DG140AP/883
DGI40AP/B83
DG140BP
DG129AL
DGI29AL/883
DGI29AL/883
DG129AP
DG129AP/883
DGI29AP/883
DG129BP
DG146AL
DGI46ALl883
DGI46ALl883
DG146AP
DGI46AP/883
DGI46AP/883
DG146AP
DG144AL
DGI44AL/883
DGI4o!Ali883
DG144AP
DGI44AP/883
DGI44AP/883
DGI44Ap
DGI45AL
DGI45AL/883
DGI45ALl883
DG145AP
DGI45AP/883
DG145AP/883
DG145BP
DG139AL
DG139ALl8B3
DGI39AL/883
DG139AP
DG139AP/883
DGI39AP/883
DG139BP
DG172AL/883
DG172AL/883
DG172AL/883
DG180AA
DG180AA/883
DG180AA/883
Siliconix
Par!
Number
DG180AL
DGI80AL-2
DGI80AL/883
DG180AP
DG180AP-2
DG180AP/883
DGI80BA
DG180BP
DG181AA
DG181AA-2
DG181AA/883
DG181AL
DGI81AL-2
DGI81ALl883
DG181AP
DG181AP-2
DGI81AP/B83
DG181BA
DG181BP
DG182AA
DGI82AA-2
DGI82AA/883
DGI82AL
DGI82AL-2
DGI82AL/883
DGI82AP
DGI82AP-2
DGI82AP/BB3
DGI82BA
DGI82BP
DGI83AL
DGI83AL-2
DGI83AL/88S
DGI83AP
DGI83AP-2
DGI83AP/883
DGI83BP
DGI84AL
DGI84AL-2
DGI84AL/883
DG184AP
DG184AP-2
DGI84AP/883
DGI84BP
DG185AL
DGI85AL-2
DGI85AL/883
DGI85AP
DGI85AP-2
DGI85AP/883
DGI85BP
DG186AA
DG186AA-2
DG186AA/BB3
DG186AL
DGI86AL-2
DGI86AL/883
DG186AP
DGI86AP-2
DGI86AP/883
DG186BA
DG1&6BP
DG187AA
DG1B7AA-2
DG187AA/883
DG187AL
DGi87AL-2
DG187AL/883
DG187AP
DGI87AP-2
DGI87AP/883
DG187BA
DG187BK
Direct
Replacement
DGI80ALl883
DGI80AL/883
DG180AL/883
DG180AP
DG180AP/883
DG180AP/883
DG180BA
DG180BP
DG181AA
DG181AA/883
DG181AA/883
DGI81AL/883
DGI81AL/883 .
DG181AL/883
DG181AP
DGI81AP/883
DGI81AP/883
DG181BA
DG181BP
DGI82AA
DGI82AA/8B3
DGI82AA/883
DGI82AL/883
DGI82AL/883
DG 182AL/883
DGI82AP
DGI82AP/883
DGI82AP/883
DGI82BA
DGI82BP
DGI83AL/883
DGI83AL/B83
DGI83AL/883
DGI83AP
DGI83AP/883
DGI83AP/883
DGI83BP
DGI84AL/883
DGI84AL/883
DGI84AL/883
DGI84AP
DGI84AP/8B3
DGI84AP/883
DGI84BP
DGI85AL/B83
DGI85ALl883
DGI85AL/883
DGI85AP
DGI85AP/883
DGI85AP/883
DG185BP
DG186AA
DG186AA/883
DG186AA/8B3
DGI86AL/B83
DGI86AL/883
DG1B6AL/883
DG186AP
DGI86AP/883
DG186AP/883
DG1B6BA
DG186BP
DG187AA
DG187AA/883
DG187AA/883
DGI87AL/883
DG187AL/883
DGI87AL/883
DG187AP
DG187AP/883
DGI87AP/883
DG187BA
DG187BK
Siliconix
incorporated
Siliconix
Similar
Replacement
;;'J'
H
Cross Reference
Siliconix
incorporated
Part
Number
Slliconlx
Direct
Replacement
DG187BP
DG188AA
DG188AA-2
DG188AA/883
DG188AL
DG188AL-2
DG188ALl883
DG188AP
DG188AP-2
DG188AP/883
DG188BA
DG188BP
DG189AL
DG189AL-2
DG189ALl883
DG189AP
DG189AP-2
DG 189AP 1883
DG189BP
DG190AL
DG190AL-2
DG190ALl883
DG190AP
DG190AP-2
DG190AP/883
DG190BP
DG191AL
DG191AL-2
DG191AL/883
DG191AP
DG191AP-2
DG191AP/883
DG191BP
DG200AA
DG200AAA
DG200AAA-2
DG200AAA/883
DG200AAK
DG200AAK-2
DG200AAK/883
DG200AAP
DG200AAP-2
DG200AAP1883
DG200ABA
DG200ABK
DG200ABP
DG200ACA
DG200ACJ
DG200AK
DG200BA
DG200BK
DG200CJ
DG201AAK
DG201AAK-2
DG201 AAK/883
DG201 AAZ/883
DG201ABK
DG201ACJ
DG201ACY
DG201ADY
DG201AK
DG201AK/883
DG201BK
DG201CJ
DG202AK
DG202AK-2
DG202AK/883
DG202BK
DG202CJ
DG211CJ
DG211CY
DG211DY
DG212CJ
DG212CY
DG212DY
DG187BP
DG188AA
DG188AA/883
DG188AA/883
DG188ALl883
DG188ALl883
DG188ALl883
DG188AP
DG188AP/883
DG 188AP1883
DG188BA
DG188BP
DG 189ALl883
DG189ALl883
DG 189AL/883
DG189AP
DG 189AP1883
DG 189AP 1883
DG189BP
DG190ALl883
DG 190ALl883
DG190ALl883
DG190AP
DG 190AP1883
DG 190AP1883
DG190BP
DG191ALl883
DG191ALl883
DG191ALl883
DG191AP
DG191AP/883
DG191AP/883
DG191BP
DG200AAA
DG200AAA
DG200AAA/883
DG200AAA/883
DG200AAK
DG200AAK/883
DG200AAK/883
DG200AAP
DG200AAP/883
DG200AAP 1883
DG200ABA
DG200ABK
DG200ABP
DG200ACA
DG200ACJ
DG200AAK
DG200ABA
DG200ABK
DG200ACJ
DG201AAK
DG201AAK/883
DG201AAK/883
DG201AAZ/883
DG201ABK
DG201ACJ
DG201ADY
DG201ADY
DG201AAK
DG201AAK/883
DG201ABK
DG201ACJ
DG202AK
DG202AK/883
DG202AK/883
DG202AK
DG202CJ
DG211CJ
DG211DY
DG211DY
DG212CJ
DG212DY
DG212DY
Sltlconlx
Similar
Replacement
Slliconlx
Part
Number
DG221AK
DG221AK-2
DG221 AK/883
DG221BK
DG221CJ
DG221CK
DG221CY
DG221DY
DG243AK
DG243AK-2
DG243AK/883
DG243CJ
DG243CK
DG243DJ
DG243DK
DG271AK
DG271AK-2
DG271AK/883
DG271AZ/883
DG271BK
DG271CJ
DG271CK
DG271CY
DG271DY
DG281AA
DG281AA-2
DG281AA/883
DG281AP
DG281AP-2
DG281 AP 1883
DG281BA
DG281BP
DG284AP
DG284AP-2
DG284AP/883
DG284BP
DG287AA
DG287AA-2
DG287 AA/883
DG287AP
DG287AP-2
DG287AP/883
DG287BA
DG287BP
DG290AP
DG290AP-2
DG290AP/883
DG290BP
DG300AAA
DG300AAA-2
DG300AAA/883
DG300AAK
DG300AAK-2
DG300AAK/883
DG300ABA
DG300ACA
DG300ACJ
DG300ACK
DG301AAA
DG301AAA-2
DG301 AAA/883
DG301AAK
DG301AAK-2
DG301 AAK/883
DG301 AAZ/883
DG301ABA
DG301ACA
DG301ACJ
DG301ACK
DG302AAK
DG302AAK-2
DG302AAK/883
DG302ACJ
DG302ACK
Direct
Replacement
Slllconlx
Similar
Replacement
DG221AK
DG221 AK/883
DG221 AK/883
DG221BK
DG221CJ
DG221CK
DG221DY
DG221DY
DG243AK
DG243AK/883
DG243AK/883
DG243DJ
DG243DK
DG243DJ
DG243DK
DG271AK
DG271AK/883
DG271 AK/883
DG271AZ/883
DG271BK
DG271CJ
DG271CK
DG271DY
DG271DY
DGI81AA
DG181AA/883
DG181AA/883
DG181AP
DG181AP/883
DG181AP/883
DG181BA
DG181BP
DG184AP
DG184AP/883
DG184AP/883
DG184BP
DG187AA
DG 187AA/883
DG187AA/883
DG187AP
DG187AP/883
DG187AP/883
DG187BA
DG187BP
DG190AP
DG190AP/883
DG190AP/883
DG190BP
DG300AAA
DG300AAA/883
DG300AAA/883
DG300AAK
DG300AAK/883
DG300AAK/883
DG300ABA
DG300ACA
DG300ACJ
DG300ACK
DG301AAA
DG301AAA/883
DG301AAA/883
DG301AAK
DG301AAK/883
DG301AAK/883
DG301AAZ/883
DG301ABA
DG301ACA
DG301ACJ
DG301ACK
DG302AAK
DG302AAK/883
DG302AAK/883
DG302ACJ
DG302ACK
4-5
lEI
Cross Reference
Part
Number
Siliconix
Direct
Replacement
DOO03AAK
DOO03AAK-2
DOO03AAK/883
DOO03AAZ/883
DOO03ACJ
DOO03ACK
DOO03ACY
DG303ADY
DOO04AAA
DOO04AAA-2
DOO04AAA/883
DOO04AAK
DOO04AAK-2
DOO04AAK/883
DOO04ABA
DOO04ACA
DOO04ACJ
DOO04ACK
DOO05AAA
DOO05AAA-2
DOO05AAA/883
DOO05AAK
DOO05AAK-2
DOO05AAK/883
DOO05ABA
DOO05ABK
DOO05ACA
DOO0SACJ
DOO05ACK
DOO08AAK
DOO06AAK-2
DOO06AAK/883
DOO06ABK
DG306ACJ
DOO06ACK
DOO07AAK
DOO07AAK-2
DOO07AAK/S83
DOO07AAZ/S83
DOO07ABK
DG307ACJ
DOO07ACK
DOO08AAK
DOO08AAK-2
DG308AAKiS83
DOO0SACJ
DOO0SACK
DG308ADY
DOO09AK
DG309AK-2
DOO09AK/883
DOO09CJ
DOO09CK
DOO09DY
DOO81AAA
DOO81AAA-2
DOO81AAA/S83
DOOS1AAK
DOO81AAK-2
DOO81AAK/883
DG381 ABA
DOO81ABK
DOO81ACA
DOO81ACJ
DOO81ACK
DOO84AAK
DOO84AAK-2
DG384AAK/883
DOO84ABK
DOO84ACJ
DOO84ACK
DOO87AAA
DOO87AAA-2
DOO87AAA/883
DOO87AAK
DOO03AAK
DOO03AAK/883
DOO03AAK/883
DOO03AAZ/883
DG303ACJ
DOO03AAK
DOO03ADY
DOO03ADY
DOO04AAA
DOO04AAA/883
DOO04AAA/883
DOO04AAK
DOO04AAK/883
DOO04AAK/883
DOO04ABA
DOO04ACA
DOO04ACJ
DOO04ACK
DOO0SAAA
DOO0SAAA/883
DG30SAAA/883
DOO0SAAK
DOO0SAAK/883
DOO0SAAK/883
DOO0SAAA
DOO05AAK
DOO05AAA
DOO05AAK
DOO05AAK
DOO06AAK
DOO06AAK/883
DOO06AAK/883
DOO06AAK
DOO06AAK
DOO06AAK
DOO07AAK
DOO07AAK/883
DOO07AAK/S83
DOO07AAZ/883
DOO07ABK
DOO07ACJ
DOO07ACK
DG30SAAK
DOO0SAAK/883
DOO0SAAK/S83
DOO0SACJ
DOO08ACK
DOO0SADY
DOO09AK
DOO09AK/S83
DOO09AK/S83
DOO09CJ
DOO09CK
DOO09DY
DOOS1AAA
DOO81AAA/883
DOO81AAA/S83
DOO81AAK
DOO81 AAK/8B3
DOO81AAK/8B3
DOO81 ABA
DOO81ABK
DOO81ACA
DOO81ACJ
DOO81ACK
DOO84AAK
DOO84AAK/883
DOO84AAK/883
DOO84ABK
DOO84ACJ
DOO84ACK
DOO87AAA
DOO87AAA/883
DOO87AAA/883
DOO87AAK
4-6
H
Siliconix
Similar
Replacement
Part
Number
DOO87AAK-2
DOO87AAK/883
DOO87ABA
DOO87ABK
DOO87ACA
DOO87ACJ
DOO87ACK
DOO90AAK
DOO90AAK-2
DOO90AAK/883
DOO90ABK
DOO90ACJ
DOO90ACK
DG400AK
DG400AK/883
DG400CJ
DG400CK
DG400DJ
DG400DY
DG401AK
DG401AK/883
DG401AZ
DG401 AZ/883
DG401CJ
DG401CK
DG401DJ
DG401DY
DG402AK
DG402AK/883
DG402CJ
DG402CK
DG402DJ
DG402DY
DG403AK
DG403AK/8B3
DG403AZ
DG403AZ/SS3
DG403CJ
DG403CK
DG403DJ
DG403DY
DG404AK
DG404AK/883
DG404CJ
DG404CK
DG404DJ
DG404DY
DG405AK
DG405AKlS83
DG405AZ
DG405AZ/883
DG40SCJ
DG40SCK
DG40SDJ
DG405DY
DG408AK
DG408AK/S83
DG408CJ
DG409AK
DG409AK/883
DG409DJ
DG409DY
DG411AK
DG411 AKl883
DG411DJ
DG411DY
DG412AK
DG412AK/883
DG412DJ
DG412DY
DG413AK
DG413AKi883
DG413DJ
DG413DY
Siliconix
Direct
Replacement
DG387 AAK/883
DG387 AAK/883
DG387ABA
DOO87ABK
DOO87ACA
DG387ACJ
DOO87ACK
DOO90AAK
DOO90AAK/883
DOO90AAK/883
DOO90ABK
DOO90ACJ
DOO90ACK
DG400AK
DG400AK/883
DG400DJ
DG400AK
DG400DJ
DG400DY
DG401AK
DG401AK/8B3
DG401AZ
DG401AZ/883
DG401DJ
DG401AK
DG401DJ
DG401DY
DG402AK
DG402AK/883
DG402DJ
DG402AK
DG402DJ
DG402DY
DG403AK
DG403AK/8B3
DG403AZ/S83
DG403AZ/S83
DG403DJ
DG403AK
DG403DJ
DG403DY
DG404AK
DG404AK/S83
DG404DJ
DG404AK
DG404DJ
DG404DY
DG405AK
DG405AK/883
DG405AZ/S83
DG405AZ/S83
DG405DJ
DG405AK
DG405DJ
DG405DY
DG40SAK
DG40SAK/883
DG408DJ
DG409AK
DG409AKi883
DG409DJ
DG409DY
DG411AK
DG411AK/883
DG411DJ
DG411DY
DG412AK
DG412AK/883
DG412DJ
DG412DY
DG413AK
DG413AK/883
DG413DJ
DG413DY
Siliconix
incorporated
Siliconix
Similar
Replacement
':7
H
Cross Reference
Siliconix
incorporated
Siliconi.
Siliconi.
Part
Number
Direct
Replacement
Similar
Replacement
DG417AK
DG417AK/883
DG417DJ
DG417DY
DG418AK
DG418AK/883
DG418DJ
DG418DY
DG419AK
DG419AK/883
DG419DJ
DG419DY
DG421AK
DG421 AK/883
DG421DJ
DG421DY
DG423AK
DG423AK/883
DG423DJ
DG423DY
DG425AK
DG425AK/883
DG425DJ
DG425DY
DG441AK
DG441AK/883
DG441DJ
DG441DY
DG442AK
DG442AK/883
DG442DJ
DG442DY
DG444AK
DG444AK/883
DG444DJ
DG444DY
DG445AK
DG445AK/883
DG445DJ
DG445DY
DG480AK
DG480AK/883
DG480DJ
DG485AK
DG485AK/883
DG485DJ
DGS01AK
DGS01AP
DGS01AP-2
DGS01AP/883
DGS01BK
DGS01BP
DGS01CJ
DGS01DK
DGS03AK
DGS03AP
DGS03AP-2
DG503BP
DGS03CJ
DGS040AK
DGS040AK-2
DGS040AK/883
DGS040CJ
DG5040CK
DGS041AK
DGS041AK-2
DG5041 AK/883
DGS041CJ
DGS041CK
DGS042AK
DG5042AK-2
DG5042AK/883
DGS042CJ
DGS042CK
DGS043AK
DG417AK
DG417AK/883
DG417DJ
DG417DY
DG418AK
DG418AK/883
DG418DJ
DG418DY
DG419AK
DG419AK/883
DG419DJ
DG419DY
DG421AK
DG421AK/883
DG421DJ
DG421DY
DG423AK
DG423AK/883
DG423DJ
DG423DY
DG425AK
DG425AK/883
DG425DJ
DG425DY
DG441AK
DG441 AK/883
DG441DJ
DG441DY
DG442AK
DG442AK/883
DG442DJ
DG442DY
DG444AK
DG444AK/883
DG444DJ
DG444DY
DG445AK
DG445AK/883
DG445DJ
DG445DY
DG480AK
DG480AK/883
DG480DJ
DG485AK
DG485AK/883
DG485DJ
DGS01AP
DGS01AP
DG501AP/883
DGS01AP/883
DGS01AP
DG501AP
DG501CJ
DGS01AP
DG503AP
DG503AP
DGS03AP1883
DG503AP
DG503CJ
DG400AK
DG400AK/883
DG400AK/883
DG400DJ
DG400AK
DG401AK
DG401AK/883
DG401AK/883
DG401DJ
DG401AK
DG402AK
DG402AK/883
DG402AK/883
DG402DJ
DG402AK
DG403AK
Siliconi.
Part
Number
DG5043AK-2
DG5043AK/883
DGS043CJ
DGS043CK
DG5044AK
DG5044AK-2
DGS044AK/883
DG5044CJ
DG5044CK
DG5045AK
DGS045AK-2
DGS045AK/883
DG5045CJ
DG5045CK
DGS048AK/883
DG506AAK
DG506AAK-2
DGS06AAK/883
DG506AAR
DG506AAR-2
DGS06AAR/883
DG506AAZ/883
DG506ABR
DGS06ACJ
DG506ACR
DG507AAK
DG507AAK-2
DG507AAK/883
DGS07AAR
DG507AAR-2
DG507AAR/883
DG507AAZ/883
DG507ABR
DG507ACJ
DG507ACR
DG508AAK
DG508AAK-2
DG508AAK/883
DGS08AAZ/883
DG508ABK
DG508ACJ
DGS08ACK
DGS08ACY
DGS08ADY
DGS09AAK
DGS09AAK-2
DGS09AAK/883
DGS09AAZ/883
DGS09ABK
DGS09ACJ
DGS09ACK
DGS09ADY
DGS140AK
DG5140AK/883
DGS140CJ
DG5140CK
DG5141AK
DG5141AK/883
DGS141CJ
DGS141CK
DG5142AK
DGS142AK/883
DGS142CJ
DG5142CK
DGS143AK/883
DGS143AKE
DG5143CJ
DG5143CK
DGSl44AK
DG5144AK/883
DG5144CJ
DG5144CK
DGS145AK
DG5145AK/883
Direct
Replacement
SllIoonl.
Similar
Replacement
DG403AK/883
DG303AK/883
DG403DJ
DG403AK
DG404AK
DG404AK/883
DG404AK/883
DG404DJ
DG404AK
DG405AK
DG405AK/883
DG405AK/883
DG405DJ
DG405AK
DGS048AK/883
DG506AAK
DG506AAK/883
DG506AAK/883
DG506AAR
DG506AAR/883
DG506AAR/883
DG506AAZ/883
DGS06ABR
DG506ACJ
DGS06ACR
DGS07AAK
DGS07AAK/883
DGS07AAK/883
DGS07AAR
DGS07AAR/883
DGS07AAR/883
DGS07AAZ/883
DGS07ABR
DGS07ACJ
DGS07ACR
DG508AAK
DG508AAK/883
DGS08AAK/883
DGS08AAZ/883
DGS08ABK
DG508ACJ
DGS08ACK
DGS08ACY
DG508ADY
DGS09AAK
DGS09AAK/883
DG509AAK/883
DGS09AAZ/883
DG509ABK
DG509ACJ
DG509ACK
DG509ADY
DG400AK
DG400AK/883
DG400DJ
DG400AK
DG401AK
DG401AK/883
DG401DJ
DG401AK
DG402AK
DG402AK/883
DG402DJ
DG402AK
DG403AK/883
DG403AK
DG403DJ
DG403AK
DG404AK
DG404AK/883
DG404DJ
DG404AK
DG405AK
DG405AK/883
III
4-7
Cross Reference
Par!
Number
DG5145CJ
DG5145CK
DG5241AK
DG5241CJ
DG5241CK
DG5243AK
DG5243CJ
DG5243CK
DG5245AK
DG5245CJ
DG5245CK
DG526AR
DG527AR
DG528AR
DG529AR
DGS34AP1883
DGS34DJ
DG535AP
DG535AP1883
DG535CY
DG535DJ
DG536AM
DG536CV
DG536DN
DG536DV
DG538AP
DG538DJ
DG538DN
DG546AK/883
DG546AZ/883
DG546DJ
DG548AAK
DG548AAKl883
DG548AAZ
DG548ABK
DG548ACJ
DG548ADV
DG548DJ
DG566AP
DG566AP-2
DG566CJ
DG566DP
DG568AP
DG568AP-2
DG568BP
DG568CJ
DG569AP
DG569AP-2
DG569BP
DG569CJ
DG611AP/883
DG611DJ
DG611DV
DG841AM/883
DG841 ON
DG908AK
DG908AK/883
DG908DJ
DG908DV
DGM181AA
DGM181AA/HR
DGM181AA/883B
DGM181AK
DGM181AK/HR
DGM181AKl883B
DGM181BA
DGM181BK
DGM181CJ
DGM182AA
DGMl82AA/HR
DGM182AA/883B
DGMl82AK
DGM182AK/HR
DGM182AL
DGMl82AL/HR
4-8
H
Siliconix
Direct
Siliconix
Similar
Replacement
Replacement
DG405DJ
DG405AK
DG421AK
DG421 OJ
DG421AK
DG423AK
DG423DJ
DG423AK
DG425AK
DG425DJ
DG425AK
DG526AR
DG527AR
DG528AR
DG529AR
DGS34AP1883
DGS34DJ
DG535AP/883
DG535AP/883
DG536DN
DG535DJ
DG536AM
DG536DN
DG536DN
DG536DV
DG538AP
DG538DJ
DG538DN
DG546AK/883
DG546AZ/883
DG546DJ
DG548AAK
DG548AAK/883
DG548AAZ
DG548ABK
DG548ACJ
DG548ADV
DG548DJ
DG566AP
DG566AP-2
DG566CJ
DG566DP
DG568AP
DG568AP-2
DG568BP
DG568CJ
DG569AP
DG569AP-2
DG569BP
DG569CJ
DG601AP/883
DG601DJ
DG601DV
DG841AM/883
DG841 ON
DG908AK
DG908AK/883
DG908DJ
DG908DV
DOO81AAA
DOO81AAA/883
DOO81AAA/883
DOO81AAK
DOO81AAK
DOO81AAKl883
00081 ABA
DOO81ABK
DOO81ACJ
DOO81AAA
DOO81AAA/883
00081 AAA/883
DOO81AAK
00081 AAK/883
DOO81AAL
DOO81AAL/883
Par!
Number
DGM182AL/883B
DGM182BA
DGM182BK
DGM182CJ
DGM184AK
DGM184AK/HR
DGM184AKl8B<1B
DGM184AL
DGM184AL/HR
DGM184ALl883B
DGM184BK
DGM184CJ
DGM185AK
DGM185AK/HR
DGM185AK/883B
DGM185AL
DGM185AL/HA
DGMl85AL/883B
DGMl85BK
DGM185CJ
DGM187AA
DGM187AAlHR
DGM187AA/883B
DGM187AK
DGM187AK/HR
DGM187AK/883B
DGM187BA
DGM187BK
DGM187CJ
DGM188AA
DGM188AA/HR
DGM188AA/883B
DGM188AK
DGM188AK/HR
DGM188AL
DGM188AL/HR
DGM188AL/883B
DGM188BA
DGM188BK
DGM188CJ
DGM190AK
DGM190AK/HR
DGM190AK/883B
DGM190AL
DGM190AL/HR
DGM190AL/883B
DGM190BK
DGMl90CJ
DGM191AK
DGM191AK/HR
DGM191AK/883B
DGM191AL
DGM191AL/HR
DGM191AL/883B
DGM191BK
DGM191CJ
DGP201AAK
DGP201AAK883
DGP201AAZ883
DGP201ADJ
DGP201ADV
DGP303AAK883
DGP303AAZ883
DGP303ADJ
DGP303ADV
DGP508AAK
DGP508AAK883
DGP508AAZ883
DGP508ADJ
G116AP-2
G116BP
G117AL
G117AL-2
G118AP
Siliconix
incorporated
Siliconix
Direct
Siliconix
Similar
Replacement
Replacement
00081 AAL/883
DOO81ABA
DOO81ABK
DOO81ACJ
DG405AK
DG405AK/883
DG405AK/883
DGl84AL
DG184AL/883
DG184AL/883
DG405AK
DG405DJ
DG405AK
DG405AK/883
DG405AK/883
DGl85AL
DGl85AL/883
DG185AL/883
DG405AK
DG405DJ
DOO87AAA
00087AAAl883
00087AAA/883
DOO87AAK
DG387AAK
00087AAK/883
DOO87ABA
DOO87ABK
DG387ACJ
DG387AAA
00087AAA/883
00087AAA/883
DOO87AAK
DOO87AAK
DOO87AAL
00087 AALl883
00087 AAL/883
DOO87ABA
DOO87ABK
DOO87ACJ
DG403AK
DG403AK/883
DG403AK/883
DG190AL
DG190AL/883
DG190AL/883
DG403AK
DG403DJ
DG403AK
DG403AK/883
DG403AK
DG191AL
DG191ALl883
DG191AL/883
DG403AK
DG403DJ
DGP201AAK
DGP201AAK883
DGP201AAZ883
DGP201ADJ
DGP201ADV
DGP303AAK883
DGP303AAZ883
DGP303ADJ
DGP303ADY
DGP508AAK
DGP508AAK883
DGP508AAZ883
DGP508ADJ
G116AP
G116BP
G117AL
G117AL
G118AP
:;;p
H
Cross Reference
Siliconix
incorporated
Part
NUmber
Gl19AL
Gl19AL-2
Gl19AP
HI1-200-2
HI1-200-4
HI1-200-5
HI1-200-B
HI1-201-2
HI1-201-B
H11-201HS2
H11-201HSS
H11-201HSB
HI1--30D-2
HI1--300-S
HI1--300-8
HI1--301-2
HI1--301-5
HI1--301-B
HI1--302-2
HI1--302-5
Hll--302-B
HI1--303-2
Hll--303-5
HI1--303-B
HI1--304-2
Hll--304-5
Hll--304-B
HI1--30S-2
HI1--30S-5
HI1--305-B
HI1--30S-2
HI1--30S-5
HI1--30S-B
HI1--307-2
HI1--307-5
HI1--307-B
HI1--381-2
Hll--3Bl-5
Hll--3Bl-B
HI1--3B4-2
Hll--3B4-5
Hll--3B4-B
HI1-3B7-2
HI1-3B7-5
HI1-387-B
Hll-390-2
HI1-390-5
HI1-390-B
HI1-5040-2
HI1-5040-5
HI1-5040-B
HI1-5041-2
HI1-S041-5
HI1-5041-B
HI1-5042-2
HI1-5042-5
HI1-5042-B
HI1-5043-2
HI1-5043-5
HI1-5043-B
HI1-5044-2
Hil-5044-5
HI1-5044-B
HI1-5045-2
HI1-5045-5
HI1-5045-B
HI1-50S-2
HI1-50S-7
Hll-505-B
HI1-50SA-2
HI1-506A-5
HI1-50SA-7
HI1-50SA-B
HI1-50SL-2
HI1-50SL-5
SlIIconlx
Direct
Replacement
Slliconlx
Similar
Replacement
Gl19AL
GII9AL
Gl19AP
DG200AAK
DG200ABK
DG200ACK
DG200AAK/BB3
DG201AAK
DG201AAK/BB3
DG271AK
DG271AK
DG271 AK/8B3
DG300AAK
DG300ACK
DG300AAK/BB3
DG301AAK
DG301ACK
DG301AAK/8B3
DG302AAK
DG302ACK
DG302AAK/883
DG303AAK
DG303ACK
DG303AAK/883
DG304AAK
DG304ACK
DOO04AAK/883
DG30SAAK
DOO0SACK
DG305AAK/883
DOO0SAAK
DG30SACK
DG30SAAK/BB3
DG307AAK
DG307ACK
DOO07AAK/8B3
DG3B1AAK
DG3dlACK
DG331AAK/BB3
DG3B4AAK
DG3B4AAK
DG3B4AAK/BB3
DOOB7AAK
DOOB7ACK
DG387AAK/883
DOO90AAK
DG390AAK
DOO90AAK/883
DG400AK
DG400AK
DG400AK/883
DG401AK
DG401AK
DG401AK/883
DG402AK
DG402AK
DG402AK/8B3
DG403AK
DG403AK
DG403AK/883
DG404AK
DG404AK
DG404AK/B83
DG405AK
DG405AK
DG405AK/883
DG50SAAR
DG50SAAR/B83
DGSOSAAR/883
DGSOSAAR
DG50SABR
DG50SAAR/8B3
DGSOSAAR/BB3
DGS2SAK
DGS2SCK
Part
Number
HI1-50SL-B
HI1-507-2
HI1-507-B
HI1-507A-2
HI1-507A-5
HI1-507A-7
HI1-507A-B
HI1-507L-2
HI1-507L-5
HI1-507L-B
HI1-50B-2
Hll-S0B-S
HI1-S0B-B
Hll-S08A-2
Hll-S0BA-5
HI1-50BA-7
HI1-508A-B
HI1-50BL-2
HI1-508L-5
Hll-S08L-8
HI1-509-2
Hll-S09-5
Hll-S09-B
HI1-509L-2
HI1-509L-S
HI1-509L-8
Hll-S4B-l
Hll-S48-S
HI1-548-8
HI1-549-1
HI1-549-5
HI1-549-B
HI1-7541JD-5
HI1-7541KD-5
HI1-7541 SD-2
HI1-7541TD-2
HI2-200-2
HI2-200-4
HI2-200-5
HI2-200-B
HI2-300-2
HI2--300-5
HI2-300-B
HI2-301-2
HI2-301-5
HI2-301-8
HI2-304-2
HI2-304-5
HI2-304-8
HI2-305-2
HI2-305-5
HI2--305-B
HI2-381-2
HI2-381-5
HI2-3Bl-B
HI2-3B7-2
HI2-3B7-5
HI2-387-B
HI3-200-5
HI3-201-5
HI3-201HS5
HI3-300-5
HI3-301-5
HI3-302-5
HI3-303-5
HI3-304-S
HI3-305-5
HI3-30S-5
HI3-307-5
HI3-3Bl-5
HI3-3B4-5
HI3-3B7-5
HI3-390-5
HI3-5040-5
Slilconix
Direct
Replacement
SlIIconlx
Similar
Replacement
DG52SAK/BB3
DGS07AAR
DG507AAR/BB3
DG507AAR
DG507ACR
DGS07AAR/BB3
DG507AAR/8B3
DG527AK
DG527CK
DG527 AK/8B3
DGSOBAAK
DGSOBACK
DGSOBAAK/8B3
DG548AK
DG54BCK
DG548AK/8B3
DG54BAK/BB3
DGS2BAK
DGS2BCK
DGS28AK/883
DGS09AAK
DGS09ACK
DGS09AAK/BB3
DGS29AK
DGS29CK
DG529AK/883
DGS4BAK
DGS48DJ
DGS4BAK/883
DG549AK
DG549DJ
DG549AK/BB3
SI7541AJN
SI7541AKN
SI7541ASD
SI7541ATD
DG200AAA
DG200ABA
DG200ACA
DG200AAA/BB3
DOO00AAA
DG300ACA
DG300AAA/BB3
DG301AAA
DG301ACA
DG301AAA/883
DG304AAA
DG304ACA
DG304AAA/8B3
DG305AAA
DG305ACA
DG305AAA/883
DOO81AAA
DG381ACA
DG381AAA/883
DG387AAA
DG387ACA
DG387AAA/883
DG200ACJ
DG201ACJ
111
DG271DJ
DG300ACJ
DG301ACJ
DG302ACJ
DOO03ACJ
DOO04ACJ
DG305ACJ
DG30SACJ
DG307ACJ
DG381ACJ
DG3B4ADJ
DG3B7ACJ
DOO90ADJ
DG400DJ
4-9
Cross Reference
Part
Number
HI3-5041-5
HI3-5042-5
HI3-5043-5
HI3-5044-5
HI3-5045-5
HI3-506-5
HI3-506L-5
HI3-507A-5
HI3-507L-5
HI3-508-5
HI3-508A-5
HI3-508L-5
HI3-509-5
HI3-509L-5
HI4-506-B
HI4-506A-B
H14-507A-B
HI4-508A-B
ICL7135CJI
ICL7135CPI
ICL7652CPA
ICL7652CPD
ICL7652CTV
ICL7652IJD
ICL7652ITV
ICL7660CBA
ICL7660CPA
ICL7660CTV
ICL7660MTV
ICL7660SCBA
ICL7660SCPA
ICL7660SCTV
ICL7660SMTV
ICL7682CPA
ICL7682CTV
IH181CJD
IH181CTW
IH181MTW
IHl82CJD
IH182CTW
IH182MJD
IHl82MTW
IHl84CJE
IHl84MJE
IH185CJE
IHl85MJE
IH187CTW
IH187MJD
IH187MTW
IH188CJD
IH188CTW
IH188MJD
IH188MTW
IH190CJE
IH190MJE
IH191CJE
IHS040CJE
IHS040CPE
IHS040MJE
IHS040MJE/HR
IHS040MJE/883
IHS041CJE
IHS041CPE
IHS041MJE
IHS041MJE/HR
IHS041 MJE/883
IH5042CJE
1H5042CPE
IH5042MJE
IH5042MJE/HR
IH5042MJE/883
IHS043CJE
IHS043CPE
IHS043MJE
IHS043MJE/HR
4-10
Slliconlx
Direct
Replacement
H
SlIIconlx
Similar
Replacement
DG401DJ
DG402DJ
DG403DJ
DG404DJ
DG405DJ
DGS06ACJ
DG526ACJ
DG507ACJ
DG527CJ
DGS08ACJ
DG548CJ
DG528CJ
DGS09ACJ
DGS29CJ
DGS06AAZ/883
DG506AAZ/883
D0507 AAZ/883
DG547AZ/883
SI7135CK
SI7135CJ
SI7652DH
S17652DJ
SI7652DA
S17652DK
S17652DA
SI7660DY
SI7660CJ
S17660CA
SI7660AA
S17660DY
SI7660CJ
SI7660CA
S17660AA
SI7661CJ
S17661CA
DG181BP
DG181BA
DG181AA
DG182BP
DG182BA
DG182AP
DG182AA
DG184BP
DGl84AP
DG185BP
DGl85AP
DG187BA
DG187AP
DG187AA
DG187BP
DG188BA
DG188AP
DG188AA
DG190BP
DG190AP
DG191BP
DG400AK
DG400DJ
DG400AK
DG400AK/883
DG400AK/883
DG401AK
DG401DJ
DG401AK
DG401AK/883
DG401 AK/883
DG402AK
DG402DJ
DG402AK
DG402AK/883
DG402AKl883
DG403AK
DG403DJ
DG403AK
DG403AK/883
Part
Number
IHS043MJE/883
IHS044CJE
IHS044CPE
IHS044MJE
IHS044MJE/HR
IHS044MJE/883
IHS045CJE
IHS045CPE
IHS045MJE
IHS045MJE/HR
IHS045MJE/883
IH5108CPE
IHS1081JE
IHS108MJE
IHS140CJE
IHS140CPE
IHS140MJE
IHS140MJE/883
IHS141CJE
IHS141CPE
IHS141MJE
IHS141 MJE/883
IHS142CJE
IHS142CPE
IHS142MJE
IHS142MJE/883
IHSl43CJE
IHS143CPE
IHS143MJE
IHSl43MJE/883
IHSl44CJE
IHSl44CPE
IHSl44MJE
IHS144MJE/883
IHSl45CJE
IHSl45CPE
IHSl45MJE
IHSl45MJE/883
1H5208CPE
IHS2081JE
IHS208MJE
IH6108CJE
1H6108CPE
IH6108MJE
1H6116CJI
IH6116CPI
1H6116MJI
1H6208CJE
IH8208CPE
IH6208MJE
1H8216CJI
IH8216CPI
IH6216MJI
IH9108CPE
IH91081JE
IH9108MJE
LDIIOCJ
LDlllACJ
LDII4CR
LD120CJ
LD121ACJ
LDI22CJ
LFl1201D
LFl1201N
LFl1202D
LFl2201D
LFl2202D
LFl2202N
LFl3201D
LFl3201N
LF13202D
LFl3202N
LTC1044CH
LTC1044MH
Siliconix
Direct
Replacement
Siliconix
incorporated
Slliconlx
Similar
Replacement
DG403AK/883
DG404AK
DG404DJ
DG404AK
DG404AK/883
DG404AK/883
DG405AK
DG405DJ
DG405AK
DG405AK/883
DG405AK/883
DG908DJ
DG908DK
DG908AK
DG400AAK
DG400ADJ
DG400AK
DG400AK/883
DG401AK
DG401DJ
DG401AK
DG401 AK/883
DG402AK
DG402DJ
DG402AK
DG402AK/883
DG403AK
DG403DJ
DG403AK
DG403AK/883
DG404AK
DG404DJ
DG404AK
DG404AK/883
DG405AK
DG405DJ
DG405AK
DG405AK/883
DGS09ADJ
DGS09ADK
DGS09AAK
DG508ACK
DGS08ACJ
DGS08AAK
DGS06ACK
DG506ACJ
DGS06AAK
DG509ACK
DG509ACJ
DG509AAK
DG507ACK
DG507ACJ
DG507AAK
DG568CJ
DGS68BP
DGS68AP
LDll0CJ
LDlllACJ
LDl14CR
LD120CJ
LD121ACJ
LDl22CJ
DG411AK
DG411DJ
DG412AK
DG411AK
DG412AK
DG412DJ
DG411AK
DG411DJ
DG412AK
DG412DJ
SI7660CA
SI7660AA
;J
H
Cross Reference
Siliconix
incorporated
SlIIconlx
Part
Number
LTC1052CH
LTC1052CJ
LTC1052CN
LTC1052MH
LTC1052MJ
LTC7652CH
LI44AL
LI44BL
L161AL-2
L161AL/883
L161AP
L161AP-2
L161AP/883
L161BP
L161CJ
MAX331MJE
MAX332MJE
MPC16S
MPC4D
MPC8D
MPC8S
MP200DlAA
MP200DIAP
MP200DIBA
MP200DICJ
MP200DIPB
M?201DIAP
MP201DIBP
MP201DICJ
MP302DIAP
MP302DIBP
MP302DICJ
MP303DIAP
MP303DIBP
MP303DICJ
MP7501JD
MP7501JN
MP7501KD
MP7501KN
MP7501SD
MP7501TD
MP7503JD
MP7503JN
MP7503KD
MP7503KN
MP75038D
MP7503TD
MP7506JD
MP7506JN
MP7506KD
MP7506KN
MP75068D
MP7506TD
MP7507JD
MP7507JN
MP7507KD
MP7507KN
MP7507SD
MP7507TD
MP7508KD
MP7508KN
MP7508SD
MP7509KD
MP7509KN
MP75098D
MP7541TD
MP7621JN
MP7621KN
MP76218D
MP7621TD
MP7623JN
MP7623KN
MP7623SD
MP7623TD
PM7541AAX
Direct
Replacement
Siliconix
Similar
Replacement
SI7652DHI
SI7652DK
SI7652CJ
SI7652AA
SI7652AK
SI7652DHI
LI44AL
LI44AL
L161ALi883
L161AL/883
L161AP
L161AP/883
L161AP/883
L161BP
L161CJ
DG411AK
DG412AK
DGS06ABK
DG509ADK
DGS07ABK
DGS08ADK
DG200AAA
DG200AAK
DG200ABA
DG200ACJ
DG200ABK
DG411AK
DG411AK
DG411DJ
DG302AP
DG302BP
DG302CJ
DG303AP
DG303BP
DG303CJ
DGS01BK
DG501CJ
DG501BK
DG501CJ
DG501AK
DG501AK
DGS03BK
DGS03CJ
DG503BK
DG503CJ
DG503AK
DG503AK
DGS06ABK
DGS06ACJ
DGS06ABR
DGS06ACJ
DG506AAK
DG506AAR
DGS07ABK
DGS07ACJ
DG507ABR
DG507ACJ
DG507AAK
DG507AAR
DG508ABK
DG508ACJ
DG508AAK
DG509ABK
DG509ACJ
DG509AAK
SI7541ATD
SI7541AJN
SI7541AKN
SI7541ASD
817541ATD
817541AJN
817541AKN
SI7541ASD
SI7541ATD
SI7541ATD
Part
Number
PM7541ABX
PM7541AGP
PM7541ANP
PM7545AR
PM7545BR
PM7545GP
PM7545HP
PM7645AR
PM7645BR
PM7645GP
PM7645HP
S125HC04CJ
S12504CJ
SI3002
S13002A
S13002AA
SI3002AP
S13002BK
SI3002BP
SI3705DK
S13705142K
S13705143K
S13705192K
S13705192P
S13705193K
SI6009DL
SI7240JN
SI7240KN
817240AQ
817240BQ
817240TD
817240SD
SI7250CK
SI7533AQ
817533BQ
817533CQ
SI7533JN
817533JP
817533KN
S17533KP
817533LN
817533SD
SI7533TD
SI7533UD
SI7541AJN
817541AKN
SI7541A8D
SI7541 ASD883
SI7541 A8E883
SI7541ATD
SI7541 ATD883
S17541 A TE883
SI7541JN
SI7541KN
SI7541SD
817541 SD/883
SI7541 SE/883
S17541TD
SI7541TD/883
817541TE/883
817542JN
817542KN
S17542SD/883
SI7542TD/883
817543JN
SI7543KN
817543SD/883
S17543TD/883
SI7545AE
817545GLN
SI7545GUD
S17545GUD/883
S17545GUE/883
SI7545JN
Siliconix
Direct
Replacement
SlIIconlx
Similar
Replacement
SI7541ASD
SI7541AKN
SI7541AJN
S17545GUD
S17545UD
SI7545GLN
SI7545LN
SI8045GUD
SI8045UD
SI8045GLN
SI8045LN
S12504CJ
SI2504CJ
S13002AA
S13002AA
SI3002AA
S13002AP
S13002BP
SI3002BP
DGS01DK
DG501DK
DG501DK
DG501DK
DG501DK
DG501DK
G118AL
SI7240JN
SI7240KN
SI7240AQ
SI7240BQ
SI7240TD
SI72408D
SI7250CK
817533AQ
SI7533BQ
817533CQ
SI7533JN
SI7533JP
SI7533KN
817533KP
SI7533LN
S175338D
817533TD
817533UD
SI7541AJN
817541AKN
SI7541A8D
S17541A8D883
817541A8E883
SI7541ATD
SI7541ATD883
S17541ATE883
817541JN
S17541KN
8175418D
SI7541SD/883
SI75418E/883
817541TD
SI7541TD/883
SI7541TE/883
817542JN
SI7542KN
817542SD/883
S17542TD/883
SI7543JN
SI7543KN
S17543SD/883
S17543TD/883
SI7545AE
SI7545GLN
SI7545GUD
817545GUD883
S17545GUE883
SI7545JN
III
4-11
Cross Reference
Part
Number
S17545KN
S17545LN
SI7545SD
SI7545TD
SI7545UD
S17545UD/883
SI7545UE/883
SI7652BA
SI7652BK
S176520A
S176520H
S176520J
SI7652DA
SI7652DH
SI7652DJ
SI7652DK
SI7660AA
SI76600A
SI76600J
SI7660DY
SI7661AA
SI76610A
SI7661OJ
SI7820LN
S17820KN
SI7820LP
SI7820KP
SI78200Q
SI7820BQ
SI7820UQ
SI7820TQ
SI7820TD/883
SI8601AK/883
SI8601DJ
SI8601DK
SI8602AK/883
SI8602DJ
SI8602DI<
S18603AK/883
SI8603DJ
SI8603DK
S18604AK/883
SI8604DJ
SI8604DK
SW-D1BQ
SW-D1BQ883
SW-D1FQ
SW-D2BQ
SW-D2BQ883
SW-D2FQ
SW-05BK
SW-05BK883
SW-05BY
SW-05BY883
SW-D5FK
SW-05FY
SW-05GP
SW-201BQ
SW-201BQB83
SW-201FQ
SW-201GP
SW-202BQ
SW-202BQ883
SW-202FQ
SW-202GP
TL520N
TS07135CJI
TS071350Pl
TS07541JN
TS07541KN
TS07541SD
TS07541TD
TS0766000A
TS076600PA
11090D
4-12
H
Sillconix
Direct
SlIIccnlx
Similar
Replacement
Replacement
SI7645KN
S17545LN
S17545SD
SI7545TD
SI7s4sUD
SI7Si1SUD/883
S17545UE/883
SI7652DA
SI7652DK;
SI7652DA
Si7652DH
S17652DJ
SI7652DA
SI7652DH
S17652DJ
SI7652DK
Si7660AA
SI76600A
SI7660CJ
S17660DY
S17661AA
S176610A
S17661CJ
SI7B20LN
SI7820KN
SI7820LP
SI7820KP
SI78200Q
SI7820BQ
SI7820UQ
SI7820TQ
SI7820TD/883
SI8601 AK/883
SI8601DJ
SI8601DK
S18602AK/883
SI8602DJ
S18602DK
S18603AK/883
SI8603DJ
SI8603DK
SI8604AK/883
SI8604DJ
SI8604DK
DG201AAK
DG201 AAK/883
DG201ABK
DG202AAK
DG202AAK/883
DG202ABK
DG200AAA
DG200AAA/883
DG200AAK
DG200AAK/883
DG200ABA
DG200ABK
DG200AOJ
DG411AK
DG411AK/883
DG411AK
DG411DJ
DG412AK
DG412AK/883
DG412AK
DG412DJ
SI8601DJ
S171350K
S171350J
SI7541AJN
SI7541AKN
SI7541ASD
SI7541ATD
SI7660DY
SI76600J
DG400AK
Part
Number
11090P
1109MD
11100D
1110MD
11100P
11110D
11110P
llllMD
11120D
11120P
1112MD
11130D
11130P
1113MD
11140D
11140P
1114MD
11150D
11150P
1115MD
11160D
11160P
1116MD
36510/11101BAO
36510/11101BOA
36510/11101BOO
36510/11101B10
36510/11102BAO
38510/11102BOA
38510/11102BOO
38510/11102BI0
38510/11103BAO
36510/11103BEA
36510/11103BEO
38510/11104BAO
38510/11104BEA
38510/11104BEO
38510/11105BAO
38510/11105BOA
38510/11105BOO
38510/11105BI0
38510/11106BAO
38510/11106BOA
38510/11106BOO
38510/11106B10
38510/11107BAO
38510/11107BEA
38510/11107BEO
38510/11108BAO
38510111108BEA
38510/11108BEO
38510111601BOA
38510/11601BOO
38510/11601BI0
38510/11602BOA
38510111602BOO
38510/11602B10
38510/11603BOA
38510111603BOO
38510/11604BOA
38510/11604BOO
38510/11605BOA
38510/11605BOO
38510/11605BI0
38510111606BOA
38510/11606BOO
38510/11606810
38510/11607BOA
38510111607800
38510111608BOA
38510/11608500
38510112301ABOA
38510/12301A800
38510/1230lJ.BI0
Siliconix
incorporated
SlIIccnlx
Direct
Sillconix
Similar
Replacement
Replacement
DG400DJ
DG400AK
DG401AK
DG401AK
DG401DJ
DG402AK
DG402DJ
DG402AK
DG403AK
DG403DJ
DG403AK
DG404AK
DG404DJ
DG404AK
DG405AK
DG405DJ
DG405AK
DG406AK
DG406DJ
DG406AK
DG407AK
DG407DJ
DG407AK
SJM181BAO
SJM181 BOA
SJM181BOO
SJM181BI0
SJMI82BAO
SJMI82BOA
SJMI82BOO
SJMI82BIO
SJMI84BAO
SJM184BEA
SJM184BEO
SJM185BAO
SJMI85BEA
SJMI85BEO
SJM187BAO
SJM187BOA
SJM187BOO
SJM187BI0
SJM188BAO
SJM188BOA
SJM188BOO
SJM188BI0
SJM190BAO
SJM190BEA
SJM190BEO
SJM191BAO
SJM191BEA
SJM191BEO
SJM300BOA
SJM300BOO
SJM300B10
SJM301BOA
SJM301BOO
SJM301B10
SJM302BOA
SJM302BOO
SJM303BOA
SJM303BOO
SJM304BOA
SJM304BOO
SJM304BIO
SJM305BOO
SJM305BOA
SJM305BIO
SJM306BOA
SJM306BOO
SJM307BOA
SJM307BOO
SJM200ABOA
SJM200ABOO
SJM200ABI0
Cross Reference
SiJiconix
incorporated
Part
Number
SlIIconlx
Direct
Replacement
38510/12302ABEA
38510/12302ABEC
38510/19001BXC
38510/19003BXC
38510/19007BEC
38510/19008BEC
7705201EA
7705201EC
7705301EA
7705301EC
7801401CA
7801401CC
8100601EA
81006011C
8100602EA
81006021C
SJM201ABEA
SJM201ABEC
SJM506BXC
SJM507BXC
SJM508ABEC
SJM509ABEC
DG508AAK DESC
DG508AAK DESC
DG201 AAK DESC
DG201AAK DESC
DG129AK DESO
DG129AP DESC
DG5140AK DESC
DG5140AA DESO
DG5141AK DESO
DG5141AA DESC
Sillconix
Similar
Replacement
Part
Number
8100603EA
810060310
8100604EA
8100605EA
81006051C
8100606EA
8100609EA
81006091C
8100610EA
810061010
8100611EA
81006111C
8100612EA
8100613EA
81006131C
8100614EA
Silicon Ix
Direct
Replacement
Silicon Ix
Similar
Replacement
DG5142AK DESC
DG5142AA DESC
DG5143AK DESO
DG5144AK DESO
DG5144AA DESO
DG5145AK DESC
DG5140AK DESC
DG5140AA DESO
DG5141AK DESC
DG5141AA DESO
DG5142AK DESO
DG5142AA DESO
DG5143AK DESC
DG5144AK DESO
DG5144AA DESC
DG5145AK DESO
III
This Cross Reference material Is accurate to the best knowledge and belief of SlIIconlx Incorporated. Since Individual
circuit design and layout can Influence device performance, the purchaser must be responsible for the ultimate selection
and determination of Interchangeability.
4-13
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Analog Switches and Multiplexers . .
WY'Siliconix
incorporated
~
TABLE OF CONTENTS
Introduction .•.•.........••......•....•......•..•.•...•.•••.•......•..•..•....•...•. 5-1
DG123: 5-Channel SPST PMOS Analog Switch ........•....•..•............•...•....•...•. 5-8
DG125: 5-Channel SPST PMOS Analog Switch ...........•.....•.••..•......•............ 5-11
DG126/129/140: Dual DPST JFET Analog Switches .......•........•.••......•....•....... 5-15
DG133/134/141: Dual SPST JFET Analog Switches .........•..•............•..•...•.....• 5-22
DG139/142/145: Dual DPDT JFET Analog Switches .....•••.•............••........•....•• 5-30
.--' DG143/144/146: SPDT JFET Analog Switches ...........•..•.•.•.•.........•....•...•... 5-38
DG172: Monolithic 4-Channel PMOS Analog Switch ....••....•.•.•...........•..•......... 5-46
DG180/181/182: High-Speed Driver with Dual SPST JFET Switches ........•.........•....•. 5-51
DG183/184/185: High-Speed Driver with Dual DPST JFET Switches ..•.••.•...•.....•....... 5-62
" DG186/187/188: High-Speed Driver with SPDT JFET Switch ..................•............• 5-74
. - DG189/190/191: High-Speed Drive~ with Dual SPDT JFET Switches ...........•..••..•.•...• 5-85
DG200A: Dual Monolithic SPST CMOS Analog Switch ................•.......•..•.•....... 5-96
DGP201A: Precision Monolithic Quad SPST CMOS Analog Switch •.....••.................. 5-102
DG201A/202: Quad Monolithic SPST CMOS Analog Switches •...•.•...•.•..........•..... 5-117
DG211/212: Low Cost 4-Channel Monolithic SPST CMOS Analog Switches .•..........•..... 5-129
DG221: 4-Channel Monolithic SPST CMOS Analog Switch with Data Latches ..........•...... 5-143
DG243: Monolithic General Purpose CMOS Analog Switch ...............••.....•...•....• 5-151
DG271: High-Speed Quad Monolithic SPST CMOS Analog Switch .•.••..•.•....•..........• 5-156
DG300A/301A/302A/303A: CMOS Analog Switches .•..........................•........ 5-161
DPG303A: Precision Dual SPDT CMOS Analog Switch .•.......•.•.......•....•....•..... 5-173
DG304A/305A/306A/307A: CMOS Analog Switches ..••.....•...•....••.•...............• 5-184
DG308A/309: Quad Monolithic SPST CMOS Analog Switches •......•.••.•.............•.• 5-195
DG381A/384A/387A/390A: General Purpose CMOS Analog Switches ..........•.......•...• 5-201
DG400-405: Low-Power - High-Speed CMOS Analog Switches ..•.....•.....••....•...••.. 5-212
DG408/409: 8-Channel/Dual 4-Channel High Performance
CMOS Analog Multiplexers . ; ..•.•......•......•...•.•.•.•..•..•.•................ 5-229
DG411/412/413: Precision Monolithic Quad SPST CMOS Analog Switches ...•........•...•.. 5-234
DG417/418/419: Precision MiniDIP CMOS Analog Switches ................•.....•.•.•.•.. 5-245
DG421/423/425: Low-Power - High-Speed Latchable CMOS Analog Switches ..•...•...•..•.• 5-255
DG441/442: Monolithic Quad Switches SPST CMOS Analog Switches ••....••.•.......•.•... 5-265
DG444/445: Monolithic Quad SPST CMOS Analog Switches .....•••••.••.••.••..•..••.•.•• 5-274
DG480: High-Speed CMOS Octal Analog Switch Array •.•...•...•..•.••..........•....... 5-282
DG485: Low-Power - High-Speed CMOS Octal Analog Switch Array ..•....•..•..••...•....• 5-288
DG501: 8-Channel Multiplex Switch with Decode ..•......•.....•..•.•.•.....•..•.•...... 5-294
DG503: a-Channel Multiplex Switch with Decode .....•...•.•........••......•.....•..... 5-299
DG506A1507 A: 16-Channel/Dual 8-Channel CMOS Analog Multiplexers ............•.•...•.. 5-303
DGP508A: Precision 8-Channel CMOS Multiplexer/Demultiplexer .....•.••......•..•........ 5-314
DG508A/509A: 8-Channel/Dual 4-Channel CMOS Analog Multiplexers •.•.......•..•.•...... 5-331
DG526/527: 16-Channel and Dual 8-Channel Latchable Multiplexers ..•......•..•........... 5-345
DG528/529: 8-Channel and Dual 4-Channel Latchable Multiplexers ...•.....•.••...••....... 5-357
DG548/549: 8-Channel and Dual 4-Channel CMOS Analog Multiplexers with
Overvoltage protection . . . . • • . . • . . . . . . . . . . . . • . . . . . . . • . . . . . . . . . • . . . . . . • . . . . . . . . . . • 5-369
DG566: Serial-Loading Octal SPST High-Voltage Analog Switch ......•..•.................. 5-375
DG568/569: 8- and Dual 4-Channel High-Voltage CMOS Multiplexers with Latches ........•... 5-381
DG5040-5045: Monolithic General Purpose CMOS Analog Switches •.......•.............•. 5-389
DG5140/5141/5142/5143/5144/5145: Low-Power - High-Speed CMOS
Analog Switches •...................•.....•..•....•......•.........•........... 5-398
DG601: High-Speed Quad SPST CMOS Analog Switch ......•......•.........•........... 5-407
DG908/909: 8-Channel/Dual 4-Channel Fault Protected CMOS Analog Multiplexers .....•....• 5-414
G118: Monolithic 6-Channel Enhancement-Type MOSFET Switch .......................... 5-419
G119: Monolithic 6-Channel Enhancement-Type MOSFET Switch .................•......•. 5-422
Si3002: Monolithic SPDT MOS Switch with Driver ........•.•......•............•........ 5-425
...... Sillconix
incorporated
~
ANALOG SWITCHES AND MULTIPLEXERS
INTRODUCTION
Siliconix is the world's leading supplier of high performance, precision solid-state analog switches and mUltiplexers. Through the implementation of state-of-the-art technologies (CMOS, DMOS, bipolar/PMOS, and JFET
processes) in conjunction with advanced design techniques, the products shown in this section represent a
broad selection of industrial, military, and commercial grade parts suiting a wide range of applications. Siliconix
is dedicated to giving the designer the widest range of functions, performance, and packaging as standards to
ensure ease of design.
The products in this section include all of the popular Siliconix "OG" series of single, dual, and quad analog
switches, single-ended and differential multiplexers plus many new and preliminary devices.
Siliconix is branching out into the higher performance switch and multiplexer arena with our proprietary high
voltage silicon gate OG400 family. The established OG200, OG300, and OG500 families are made on our mature
metal gate process which gives adequate performance for many applications. If higher performance (i.e. lower
ON resistance, leakage currents, and power dissipation with faster switching) is required in your application,
then the OG400 family is recommended. Most of our DG4XX devices, including analog switches, multiplexers,
latched switches, and switch arrays, incorporate ESOS protection> ±4000 V. Single supply operation, charge
injection optimization, and a wide range of packaging options including gull-wing small outline, PLCC and LCC
packages are additional benefits of this family.
A wide range of preliminary products are covered in this section including multiplexers (01 and silicon gate),
PolyMOS'" fast switches, and silicon gate switch arrays. In the near future, Siliconix will release two 01 (dielectric
isolation) multiplexers with overvoltage (DG548) and/or fault protection (OG908) and two high performance
silicon gate multiplexers (OG408/409). If extremely fast switching and very low ON resistance are the most
important parameters in your system, then the OG601 PolyMOS'" quad analog switches, pin compatible with the
industry standards OG201A/202, are the devices of choice.
Switch arrays (serial-in, parallel-out) are a new architecture giving designers greater levels of flexibility in routing
signals. The OG480/485 are silicon gate switch array multiplexers that allow control of any of eight switches.
Now, summing node applications can be accomplished using a high performance switch array architecture.
Finally, Siliconix continues to expand the increasingly popular lines of U.S. MIL-M38510 QPL and European
8S9000 approved parts which have been screened for use in military applications.
The following discuss important selection criteria for analog switches and multiplexers. See the detailed selector guide to make the job of selecting the correct part for a specific application easier.
Functional Description
One of the most common control elements in electrical circuitry is the ON-OFF switch. The switch has evolved
over the years from the manually operated circuit breaker of the early experimenters to the mUlti-switch integrated circuits of today. However, the function of the switch has remained the same; to electrically isolate or
connect two sections of a circuit. The ideal switch has the following characteristics:
1) Zero ON resistance
2) Infinite OFF resistance
3) Instantaneous tON and tOFF times
5-1
~
__
WY'Siliconix
incorporated
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Although an analog switch is not perfect and can have many different parasitic elements (Figure 1), it can still
be a very good approximation of the ideal switch. ON resistance (rDS(ON) can be as low as 10 n, OFF isolation
can be as high as 90 dB (at 1 MHz), and switching speeds can reach 60 ns for a CMOS part, while PolyMOS™
can obtain 30 ns switching speeds.
Ideal
ON
o--1i
0
OFF
~
0
OFF
ON
Analog Switch
SO
0
I~I
RLEAKAGE
D
S
OD
~t~
I
t
I
Figure 1. Comparison of the "Ideal" Switch to a Solid-state Analog Switch
Analog Switch Types
Before discussing specific parameters of the Siliconix analog switch product line, a brief description and the
prime differences between the four processes used in analog switches is provided.
JFET
The n-channel JFETs used in analog switches such as the DG180 family are depletion mode devices. To maintain a depletion mode JFET switch in the ON state, the valueVGs should be at or near zero. The switch is turned
OFF by making VGS more negative than 6 volts. When the switch is ON, VGS is maintained at zero by a floating
gate drive circuit. This makes the ON resistance extremely constant over the entire analog signal range (Figure
2) .
ros
o
+10 V
Figure 2. JFET "ON" Resistance
5-2
...... Sillconix
.,1;11 incorporated
PMOS
To maintain an enhancement mode PMOS switch In the ON state, the gate is held at a negative voltage that
ensures that Vas exceeds the threshold voltage of the FET even when the analog signal is at the extremes of its
range. However, since the rOS(ON) of a MOSFET is a function of Vas , the ON resistance will vary with the analog
signal voltage (Figure 3).
The variation in ON resistance of the PMOS analog switch is a serious limitation In some applications since it can
cause distortion of the analog signal. This effect can be minimized if the load resistance is high compared to the
switch resistance.
CMOS
DMOS (double diffused MOS) switches are n-channel (NMOS) enhancement mode devices capable of subnanosecond switching speeds due to their short channel length and lateral, as opposed to vertical, current flow.
Lateral construction also allows low parasitic capacitances which makes DMOS switches ideal for wideband
signals (> 500 MHz). However, they exhibit similar ON resistance variations as the PMOS switches.
CMOS
Since CMOS analog switches are parallel combinations of p- and n-channel MOSFETs, the effective ON resistance is a combination of the PMOS and NMOS resistance curves (Figure 4). This gives a fairly constant ON
resistance over the entire analog voltage range. The CMOS switch also has the advantage of very low quiescent
supply current because other than for channel leakage, no current flows in the driver except when a control
input transition occurs.
PMOS
roe
NMOS
roe
EFFECTIVE PARALLEL RESISTANCE
VA = -10
~e
-10
=
o
-20
+10 V
-30 V
Figure 3. Variation of PMOS Switch
ReSistance with Signal Voltage
-15 V
+15 V
Figure 4. Graph of CMOS Switch Resistance
vs. Analog Signal
Metal Gate And Silicon Gate CMOS
Both metal and silicon gate technologies are incorporated into our CMOS processes, but each is used with
separate product lines. The mature metal gate process, is used for our DG200, DG300, and DG500 families. Our
newer silicon gate process (DG400 family) is recommended for applications needing state-of-the-art performance and versatility.
5-3
...... Siliconix
incorporated
~
Figure 5 gives a comparison of the ON resistance curves fora JFET (DG180), a PMOS (DG172), a metal gate
CMOS (DG201A) and a silicon gate CMOS (DG400) analog switches.
1k
"
100
rOS(ON)
(.0. )
10
--
~
PMOS (OG172)
I - - CMOS (OG201A)--L
/OG4111
JET (06180)
V+
VTA
1
-15
I
=15 V
=-15V
=25°C
-10
-5
0
5
10
Vo- ANALOG SIGNAL VOLTAGE (V)
15
Figure 5. Performance of FET Switches
Important Switch Parameters
Each switch family in the Siliconix product line has a set of distinct characteristics that make it suitable for
certain types of applications. Several major specifications should be compared and prioritized before selecting
an analog switch for a particular circuit.
This specification is simply the dc resistance of the channel when the analog switch is in the ON state. As
explained earlier, the ON resistance of an analog switch depends upon the device type and the analog signal
magnitude. Although the resistance may vary across the entire analog signal range, the worst case is normally
specified on the data sheet.
Switching Speed
Switching speed is the elapsed time from the application of the control signal on the input pin to the appearance
(or disappearance) of the analog signal at the output. Switching speed can be affected by the load on the
analog switch. Each data sheet shows a switching time test circuit with a standard load for comparison purposes.
Switch Current
The amount of current that can be fed through the switch channel is sometimes important. For example, the
DG411 can handle up to 100 rnA of pulsed current or 30 rnA of continuous current, while the DG180 can pass up
to 200 rnA of continuous current.
Break-Before-Make vs. Make-Before-Break
For most analog switch applications, break-before-make switching is desired. This is the case because in most
applications it is necessary to disconnect one signal source before connecting another to avoid source
crosstalk. However, make-before-break switching is critical in some control circuits such as the feedback resistor gain selector for programmable gain op amps, to avoid opening the loop.
5-4
~
~
Siliconix
incorporated
Electrostatic Discharge Sensitivity (ESDS)
Electrostatic discharge is the transfer of charge that occurs when an object makes contact with a device at a
different potential. The government, per MIL-883C method 3015, has classified three levels of voltage protection that a device must withstand on all pins (logic input pins are the most susceptible). Class 1 devices are
protected to 1999 V, Class 2 from 2000 to 3999 V, and Class 3 protection is greater than 4000 V. Our DG200,
DG300, DG506-509 families of metal gate devices are designed to withstand between 600 and 1999 V. 8eginning with the DG411 series, all our new devices have Class 2 or 3 ESDS ratings and are marked accordingly.
Charge Injection
Charge injection is the transfer of charge to a load from the gates of the FETs during switching. In a sample and
hold circuit, charge injection is critical as the charge added or subtracted from the holding capacitor is seen as
an error. The lower the charge injection the better. The DG400 family, especially the DG44X and DG411 series,
are designed for balanced (near zero) charge injection. The DG601 and DG44X use internal compensation on
the drain and/or source to minimize the charge injection seen by applications sensitive to this parameter.
Power Supplies and Power Consumption
A bipolar supply means positive and negative voltages are used, while single supply means the negative supply
is grounded. Most analog designs use bipolar supplies, but a growing number are turning to single supply
operation to save board space and cost. Most of our devices work well with bipolar supplies but only a few
function properly in the single supply mode. The DG400 family of analog switches and multiplexers not only
functions superbly in a single supply mode, but is fully characterized and specified with V+ at 12 V and V- at
GND. The lower the power consumed by a device within a system the better. The DG400 family generally
consumes under 10 J.lA of supply current compared to the milliamps required by previous products.
Interfacing
This can be one of the most important parameters of an analog switch application since so many possibilities
exist. The two most important interface criteria are logic compatibility and microprocessor compatibility.
The two most common logic families are TTL and CMOS. The standard logic levels for both logics are displayed
in Table 1. Remember that not all analog switches are compatible with both types of logic. Refer to the functional diagram section of each data sheet to determine the required logic levels.
Table 1
LOGIC
TTL
uO"
~
1011"
2: 2.4 V
0.8 V
CMOS
~
1.5 V
2: Vcc-1.5 V
Logic Levels for TTL and CMOS Compatibility
Microprocessor compatibility is a growing concern when designing with analog switches. Standard analog
switches require a constant control signal present on the input to hold the switch in the desired position (ON or
OFF). This could tie up a microprocessor control system unless external latches are added to control the switch.
The DG221 and DG42X series have incorporated these latches, complete with control logic, onboard to minimize parts count and ease interface to microprocessor-based control systems.
5-5
III
W'r' Siliconix
~
incorporated
Multiplexing
Analog multiplexers represent a higher level of integration of analog switches. They have many (4, 8, 16, or
more) inputs with only 1 or 2 common outputs. Multiplexers are used where it is necessary to transfer information from many signal channels at a transmitting point to a central or common receiving point, or vice versa.
This is most often used when only one transmission line is available for all data transfer between points. The
transmitted signals are in either analog or digital form, with multiplexers in this section being the analog variety
that pass bipolar voltages or currents which are often obtained from transducers. The analog signals may
represent any physical phenomenon such as temperature, pressure, velocity, speech, etc. Examples of this
can be found in data acquisition, industrial process control, aircraft systems monitoring, medical electronics,
telemetry, and communications.
Differential vs. Single-Ended Multiplexing
When is it better to select a differential multiplexer versus a single-ended configuration? Figures 6 and 7 demonstrate both options. Single-ended multiplexing, as shown in Figure 6, applies to systems that have signal
sources that are close to full-scale range and are referenced to a common point (usually ground). Another case
is where differential signal sources with small signal amplitude (millivolt range) are generated by transducers.
Instrumentation amplifiers can be used to provide a common reference for all of the signals and reduce
feedthrough errors and losses while tailoring each signal source to a desired voltage (or current) to obtain the
maximum resolution available in an AID or D/A converter or other device driven by the multiplexer.
Differential multiplexing (Figure 7) is utilized when all signal sources are uniform or close to full-scale range and
can tolerate switching transients or some mismatch without a significant degradation of the signal accuracy via
the multiplexer. Major considerations are switch matching (rDS(ON), I (OFF) ,and capacitance), common-mode
rejection, and the system's tolerance to switching transients introduced by the break-before-make switching
sequence.
2e>-----A 1
I
I
+---0 OUTPUT
:5~
H =t: =~,
0----40-
OUTPUT B
I
::
N: ft:=j :
I
ABC
Figure 6.
5-6
Single-Ended Multiplexing
Figure 7.
Differential Multiplexing
~
~
Siliconix
incorporated
Factors Affecting System Performance
In any multiplexer application, the following factors should be considered:
1) System Attenuation -- Includes loss in the analog signal caused by the multiplexer and the transmission
path. This is a frequency dependent factor.
2) Channel Isolation -- At low frequencies, this is principally a function of channel OFF leakage currents,
and at high frequencies, it is a function of device and system capacitances.
3) Crosstalk -- There are several sources of crosstalk, the main ones being overlapped between switching
channels due to imperfect break-before-make switching, switch leakages, OFF switch capacitances,
inter-switch capacitances, stray circuit capacitances, distortion in the transmission medium, etc.
4) Noise -- There are several sources of noise, including thermal or Johnson noise generated in any
resistive components, crosstalk, leakages, switching transients, as well a thermal EMFs and transmission path pickup.
5) Switching Rate -- This is important in sampling system where it determines the maximum bandwidth
frequency of the multiplexer (via the sampling theorem) and defines crosstalk errors •
..
5-7
'"
DG123
5-Channel SPST
PMOS Analog Switch
WY'Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Low Level Logic Control
• Reduces External
Components Required
• Feedback Switching for
Op Amps
• Reduces Switching Errors
• Commutation Systems
• Make-Before-Break
Switching Action
• Portable and Remote
Operation
• Very Low Standby Power
Requirements
DESCRIPTION
The DG123 is a 5-channel single-pole, single-throw
analog switch deSigned for low level logic controlled
analog switching in instrumentation, process
control, and communications systems. Featuring
make-before-break action, the DG123 can be used
inside closed loop systems to select one of five
inputs for multiplexing/demultiplexing of analog
signals, or for gain bandwidth control (by switching
passive elements), without opening the loop. The
reference pin (VR) Is normally connected to ground
to allow a low-level input (0.4 V to 1.3 V) to control
the ON-OFF conditi.on of each switch. The standby
or OFF state power consumption is less than
0.5 mW. The DG123 is a bi-directional MOS switch,
rated to handle ±10 V analog signals at up to 30 mA
continuous current. Each switch will block 20 V
peak-to-peak signals when OFF. Package options
are the 14-pin ceramic DIP and flatpack. The former
is characterized for operation over the standard
industrial, B suffix and military, A suffix temperature
ranges, while the latter is specified for the military
range only.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
S 1 o-+------'------...-I--o D
Flat Package
82!1~14
11
8 1
D
2
3
IN 1
IN2
IN 3
5
10
6
9
v-
13
12
4
S2o-+-----~~----+
S3O-~----~;O~--~
S4o-~----_r4_To~-~
S5O-~----~4_T_~~-J
83
84
IN1o-~-~~~
8S
v+
V R (Inhibit)
INS
IN4
7
:
IN 2 0-1-+-.,"'1
I
I
I
I
I
I
IN 3 <>-11-1--11'1
IN 4 0-1-+-.,"'\
Top View
Order Number: DG123ALl883
Dual-In-Llne Package
____ .J
IN 5 0-1-+-.,"'\
V-
VR
(Inhibit)
85
v-
v+
IN 1
V R (Inhibit)
Top View
Order Numbers: DG123AP or DG123BP
One 5-Channel Switch per Package"
Truth Table
LOGIC
0
1
SWITCH
OFF
ON
Logic '0' < 0.4 V
Logic "1" ~ 1.3 V
Switches Shown for Logic "1' Input
5-8
Not Recommended for New Designs
DG123
W'P' Siliconix
~
incorporated
ABSOLUTE MAXIMUM RATINGS
V+ to V- ..................................... 36 V
Current (Any Terminal) ....................... 30 mA
Vo to V- ...................................... 36 V
Storage Temperature .................... -65 to 150°C
Vs to V- ...................................... 36 V
VotoVs
..................................... 25V
VstoVo
..................................... 25V
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
Power Dissipation (Package)'
Flat Package" ............................. 750 mW
14-Pln DIP'"
.............................. 825 mW
VR to V- ...................................... 30 V
VIN to V-
30 V
VR toVIN
6V
VIN toVR
2V
All leads soldered or welded to PC board.
•• Derate 10 mW'oC above 75°C.
••• Derate 11 mW'oC above 75°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
B
A
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 10 V
3=-55,-25°C -55 to 125°C -25 to 85°C
V- = -20 V
VR = 0 V
TEMP TYpd MINb MA>f MINb MAXb UNIT
SYMBOL
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
-10
1,2,3
VANALOG
Is=-lmA
liN = 1 mA
rOS(ON)
10
-10
10
Vo= 10 V
1,3
2
70
100
125
125
150
Vo= 0
1,3
2
100
200
250
225
300
Vo= -10 V
1,3
2
270
450
600
500
600
Source OFF
Leakage Current
Is(oFF)
Vs = -10 V, Vo = 10 V
VIN = 0.4V
1
2
-1
-1000
-5
-100
Drain OFF
Leakage Current
lo(oFF)
Vo = -10 V, Vs= 10 V
VIN = 0.4V
1
2
-1
-4000
-10
-300
Channel ON
Leakage Current
IO(ON) +
IS(ON)
Vo=Vs=10V
liN = 1 mA
1
2
4
4000
10
300
V
.0.
nA
INPUT
Input Voltage HIGH
V INH
liN = 1 mA
1
2
3
1
.8
1.3
1
1.0
1.3
V
Input Current with
Input Voltage LOW
IINL
VIN = 0.4 V
1,3
2
1
100
5
100
,lJ.A
1
0.3
0.5
1
2
2
<
DYNAMIC
Turn-ON Time
Turn-OFF Time
tON
tOFF
See Switching
Time Test Circuit
(C L= 35 pF, RL=2 k.(l.)
Not Recommended for New Designs
,lJ.s
5-9
~
~
DG123
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 10 V
3=-55,-25°C -55 to 125°C -25 to 8SoC
V- = -20 V
VR= 0 V
TEMP TYpd MINb MA>f MINb MAXb UNIT
DYNAMIC (Cont'd)
Source-OFF Capacitance
CS(OFF)
Vs=OV.lo=O
f = 1 MHz
1
5
Drain-OFF Capacitance
CO(OFF)
Vo=OV.ls=O
f = 1 MHz
1
18
R L = 100.n. CL= 3 pF
f = 5 MHz
1
>50
pF
Off Isolation
dB
SUPPLY
Positive Supply Current
Ii-
Negative Supply Current
l-
Reference Supply Current
1
One Channel ON
IIN= 1 mA
3
3
1
-6
-6
IR
1
-0.5
-0.5
Positive Supply Current
1+
1
Negative Supply Current
1-
Reference Supply Current
IR
All Channels OFF
VIN = 0.4 V
15
mA
25
1
-20
-40
1
-10
-20
.l1A
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebralo convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be +
or - as per switching time test circuit. Vo is the steady state output with switch on. Feedthrough via gate
capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC
INPUT
1.2V
0V
SWITCH
INPUT
S
= +10 V o--t-------(Y
VS
SWITCH
OUTPUT
V OUT
--HD-_---1~
IN,
SWITCH
INPUT
SWITCH
OUTPUT
t r <10ns
t,<10ns
0V
_-+-J
(Repeat test
for 5 channels)
(LOGIC '1' = SWITCH ON)
5-10
V OUT =V s
RL
R L+ r OSION)
Not Recommended for New Designs
DG125
5-Channel SPST
PMOS Analog Switch
~ Siliconix
,,1;;11 incorporated
FEATURES
BENEFITS
APPLICATIONS
• Internal Zener Diode
Protection
• Reduces Switching Errors
• Communication Systems
• Reduces External
Components
• Portable and Battery
Operation
• Low Standby Power
Requirements
(P SrDBY < 0.5 mW)
• Op Amp Switching
• Variable Gain Switching
• Low OFF Leakage
• Low Level Logic Control
DESCRIPTION
The DG125 is a 5-channel single-pole, single-throw
analog switch designed for low level logic controlled
analog switching in instrumentation, process
control, and communications systems. Featuring
make-before-break action, the DG125, built on
Siliconix's PMOS process, can be used inside
closed loop systems to select one or more of five
inputs for multiplexing/demultiplexing, summing of
analog signals, or for gain bandwidth control (by
switching passive elements), without opening the
loop.
In standby or OFF state, power consumption is less
than 0.5 mW. The DG125 is a bi-directional MOS
switch, rated to handle ±10 V analog signals at up
to 30 mA continuqus current. Each switch will block
20 V peak-to-peak signals when OFF.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Flat Package
Packaging for the DG125 includes 14-pin side braze
and flatpack options. Performance grades include
both the military, A suffix (-55 to 125°C) and
industrial, B suffix (-25 to 85°C) temperature
ranges. The flatpack option is only available in the
military grade.
S 1 O-t------<>"I.'---:c----t-+-o D
S20-t-----~~~~---+
S30-t-----~~T~~--+
S40-~----~+_~f~--+
S50-~----~+_+_~r~~
IN 1 o-t-- 50
1
1.4
1
-2.4
Off Isolation
3
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Logic Supply Current
IL
1
1.15
3
3
Positive Supply Current
1+
1
0.1
15
25
Negative Supply Current
1-
1
-0.02
Logic Supply Current
IL
1
0.04
One Channel ON
VIN = 0.5 V
All Channels OFF
VIN =4.1 V
3
-6
3
-6
-20
mA
-40
20
J.lA
20
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC
INPUT
LOGIC "0" = SW ON
4.5 V
t r < 10 ns
t f < 10 ns
C>--it---O""" I &...jK>-.._--.-O v 0 SWITCH
OUTPUT
LOGIC
INPUT
v(REPEAT TEST FOR IN2 )
Not Recommended for New Designs
5-13
DG125
.... Siliconix
incorporated
~
APPLICATION HINTS
5-14
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
VL
Logic
Supply
Voltage
(V)
VIN
Logic Input
Voltage
VINHMin/
VIN~Max
V)
Vs or Vo
Analog
Voltage
Range
(V)
10
15
20
-20
-15
-10
4.5
4.5
4.5
4.1/0.5
4.1/0.5
4.1/0.5
-10 to 10
-5 to 15
o to 20
Not Recommended for New Designs
DG126/129/140
Dual DPST JFET
Analog Switches
...... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• < 1 mW Standby Power
• Minimizes Standby
Power Requirements
• Portable and Battery
Powered Systems
• Better Radiation Tolerance
• Switching in Satellite
Applications
III
Bipolar Drivers
• Constant rDSION)
Over Signal Range
• Less Distortion
• OFF Isolation> 60 dB
@ 1 MHz
• Low Distortion Circuits
• Higher Frequency
Switching
• High Frequency Switching
Circuits
DESCRIPTION
The DG126, DG129 and DG140 are dual double-pole
single-throw
analog
switches
for
use
in
instrumentation, process control, and audio
communication systems.
This series is ideally
suited for applications requiring a constant ON
resistance over the entire analog range.
ON resistance for the DG126 is < 80 n, the DG129
< 30 n and the DG140 < 10 n, and ON leakage for
all three is < 2 nA. With all switches OFF, total
power consumption is < 750 IJ.W. These switches
have Make-Before-Break action and due to the
processing are relatively Radiation tolerant.
An
enable pin
(VR)
simplifies interfacing with
microprocessor, or other logic. Package options
are the 14-pin side braze and flat pack.
Each device contains four junction-type field-effect
transistors (JFETS) to achieve constant on
resistance. Level-shifting drivers enable low-level
inputs (0.8 to 2.5 V) to control the ON-OFF state of
each switch. With logic "0" at the driver input the
switches will be OFF. With a logic "1" at the input
the switches will be ON. In the ON state each
switch will conduct current in either direction, and in
the OFF state each switch will block voltages up to
20 V peak-to-peak.
Packaging for this series includes 14-pin side braze
and flatpack options. Performance grades include
both military, A suffix (-55 to 125°C) and industrial,
B suffix (-25 to 85°C) temperature ranges. The
flatpack option is only available in the military
grade.
PIN CONFIGURATION
Dual-In-Une Package
Flat Package
82
IN2
v-
v+
V R(Enable)
IN1
8 1
Top View
Top View
Order Numbers:
Order Numbers:
DG126ALl883, DG129ALl883,
DG140ALl883
DG126AP, DG126BP
DG129AP, DG129BP
DG140AP, DG140BP
Not Recommended for New Designs
5-15
DG126/129/140
..... Siliconix
Jt;II incorporated
FUNCTIONAL BLOCK DIAGRAM
Logic '0' < 0.8 V
Logic '1' ~ 2.5 V
• Switches Shown for Logic '1' Input
Two OPST Switches per Package"
ABSOLUTE MAXIMUM RATINGS
V+ to V- ...............•.....••.•.•••....•••. 36 V
V+ to Vo ..•................. , . • . . . . • . • • . . • • . .. 36 V·
Vo orVs to V- ................................ 36
Vo toYs .................................... :!:22
V+ to,VR .••..•••...•••••..•••.....••...••..•• 25
VR to V- ..••.•••••••••••••.•••.....•••••••..•• 25
VIN to V- .•••••••.•.•.•••.••••....•••...••.••• 30
25
V
V
V
V
V
V
±6V
Current (Any Terminal) .........•............. 30 mA
Storage Temperature ........•........... -65 to 150°C
Operating Temperature (A Suffix) ..•...... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
Power Dissipation'
Flat Package" ............................. 750 mW
14-pln DIP'" ............................... 825 mW
All leads welded or soldered to PC board.
•• Derate 10 mW/oC above 75°C.
••• Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
DG126
LIMITS
PARAMETER
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55,-25°C -55 to 125°C -25 to 85°C
V- = -18 V
VR = 0 V
SYMBOL
TEMP TYpd MINb MA>f MINb MAXt UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
Is=-10mA
VIN = 2.5 V
5-16
Vo= 10 V
1,3
2
30
Vo= 8 V
1,3
2
25
Vs= 10 V
Vo = - 10 V
1
2
0.01
Vs= 8 V
Vo = -8 V
1
0.05
2
Vo = 10 V
Vs= -10 V
1
2
0.005
Vo = 8 V
Vs= -8 V
1
2
0.025
10
80
150
-8
8
V
150
.0.
100
150
1
100
IS(OFF)
VI!\! = 0.8 V
Drain OFF
Leakage Current
-10
5
100
nA
1
100
IO(OFF)
5
100
Not Recommended for New Designs
DG126/129/140
.-F' Siliconix
~
incorporated
DG126
ELECTRICAL CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=_55,_25° C -55 to 125 c C -25 to 85 c C
V- = -16 V
VR = 0 V
TEMP TYpd MINb MAx" MINb MAXt
UNIT
SWITCH (Cont'd)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
Vo=Vs=-10V
1
2
-0.02
Vo = Vs = -6 V
1
'2
-0.05
-2
-100
nA
VIN = 2.5 V
-5
-100
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
20
60
120
100
150
Input Current with
Input Voltage LOW
IINL
VIN = 0.6 V
1,3
2
0.004
0.1
2
4
4
1
0.4
0.6
1
1
1.3
1.6
2
Vs=O,lo=O
1
2.4
Vo=O,ls=O
1
2.4
Vo=Vs=O
1
2.6
= 1 MHz
1
>60
1
2.1
1
-1.2
-1.6
-2.0
-1.4
-1.5
J.lA
DYNAMIC
Turn-ON Time e
tON
See Switching
Time Test Circuit
Turn-OFF Time e
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
f = 1 MHz
CO+S(ON)
RL
Off Isolation
= 75.0.,
f
J.ls
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1
Positive Supply Current
1+
1
0.1
Negative Supply Current
1-
1
-0.5
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
One Channel ON
VIN = 2.5 V
All Channels OFF
Both VIN = 0 V
Not Recommended for New Designs
3
3.3
25
'mA
25
J.lA
5-17
DG126/129/140
Siliconix
incorporated
DG129
ELECTRICAL CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55,-25°C -55 to 125°C -25 to 85°C
V- = -18 V
VR = 0 V
TEMP TYpd MINb MA>f MINbMAX t
UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
Is= -10 mA
VIN = 2.5 V
-10
Vo= 10 V
1,3
2
20
VO= 8 V
1,3
2
30
Vs = 10 V
Vo = - 10 V
1
2
0.03
Vs= 8 V
Vo = -8 V
1
2
Vo = 10 V
Vs= -10 V
1
2
0.02
Vo = 8 V
Vs= -8 V
1
2
0.1
Vo = Vs = -10 V
1
2
-0.03
Vo = Vs = -8 V
1
2
-0.08
10
-8
8
V
30
60
.n.
50
75
1
100
IS(OFF)
5
100
VIN = 0.8 V
Drain OFF
Leakage Current
lo(oFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
1
100
nA
5
100
-2
-100
VIN = 2.5 V
-5
-100
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
15
60
120
100
150
Input Current with
Input Voltage LOW
IINL
VIN = 0.8 V
1,3
2
0.005
0.1
2
4
4
1
0.5
0.6
1
1
1.1
1.6
2
Vs=O,lo=O
1
2.4
Vo = 0, Is = 0
1
2.4
Vo=Vs=O
1
2.8
1
>60
JiA
DYNAMIC
Turn-ON Time e
Turn-OFF Time e
tON
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
Off Isolation
5-18
See Switching
Time Test Circuit
CO+S(ON)
f = 1 MHz
RL = 75.n., f = 1 MHz
JiS
pF
dB
Not Recommended for New Designs
H
DG126/129/140
Siliconix
incorporated
DG129
EL.ECTRICAL. CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=126,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55, -25 ° C -55 to 125°C -25 to 85°C
V- = -18 V
VR = 0 V
TEMP TYpd MINb MA'lf MINb MAXt UNIT
SUPP1.Y
1
2.6
1
-1.6
-1.8
-2.0
IR
1
-1.1
-1.4
-1.5
Positive Supply Current
1+
1
0.1
Negative Supply Current
1-
1
-0.5
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
One Channel ON
VIN = 2.5 V
All Channels OFF
Both VIN = 0 V
3
3.3
25
rnA
25
JJ.A
EL.ECTRICAL. CHARACTERISTICS a
DG140
LIMITS
PARAMETER
SYMBOL
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55, -25 ° C -55 to 125°C -25 to 85°C
V- = -18 V
VR= 0 V
TEMP TYpd MINb MA'lf MINb MAXb UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
Is=-10rnA
VIN = 2.5 V
Channel ON
Leakage Current
Vo= 10 V
1,3
2
6.3
Vo= 8 V
1,3
2
9.5
Vs= 10 V
Vo = - 10 V
1
2
0.04
Vs= 8 V
Vo = -8 V
1
2
0.06
Vo = 10 V
Vs= -10 V
1
2
Vo = 8 V
Vs= -8 V
1
2
10
-8
8
10
20
15
25
V
.n.
10
1000
IS(OFF)
VIN = 0.8 V
Drain OFF
Leakage Current
-10
15
300
10
1000
nA
IO(OFF)
IO(ON)+
IS(ON)
15
300
Vo = Vs = -10 V
1
2
-0.4
Vo = Vs = -8 V
1
2
-1
VIN = 2.5 V
Not Recommended for New Designs
-2
-100
-5
-100
5-19
DG126/129/140
....,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
DG140
LIMITS
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55,-25°C -55 to 125°C -25 to 85°C
V- = -18 V
VR = 0 V
TEMP TYpd MINb MAX' MINb MAXt
UNIT
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
13
60
120
100
150
Input Current with
Input Voltage LOW
IINL
VIN = 0.8 V
1,3
2
0.004
0.1
2
4
4
1
0.6
1
1.5
1
1.15
2.5
2.5
VS=O,ID=O
1
3
VD=O,ls=O
1
3
VD=VS=O
1
2.8
1
>50
1
2.4
1
-1.5
-1.8
-2.0
-1.4
-1.5
jJ.A
DYNAMIC
Turn-ON Time e
tON
Turn-OFF Time e
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CD(OFF)
Channel ON Capacitance
CD+S(ON)
See Switching
Time Test Circuit
f = 1 MHz
R L = 75.0., f = 1 MHz
Off Isolation
jJ.S
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1
Positive Supply Current
1+
1
0.1
Negative Supply Current
1-
1
-0.5
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
One Channel ON
VIN = 2.5 V
All Channels OFF
Both VIN = 0 V
3.3
3
25
mA
25
jJ.A
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
'
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN must be a step function with a minimum rise and fall time of 1 V ljJ.s •
5-20
Not Recommended for New Designs
DG126/129/140
.... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs may be +
or - as per switching time test circuit. Va is the steady state output with switch on. Feedthrough via gate
capacitance may result in spikes at leading and trailing edge of output waveform.
tOFF:-VS
tON:+VS
t r < 10 ns
LOGIC
INPUT
tf
< 10 ns
SWITCH
INPUT
OV
FrrtIJ¥H
Vs
---1--------+----
(LOGIC "1"
12 V
(REPEAT TEST FOR
S3AND IN2' S2 & S4)
SWITCH
OUTPUT
S,
0-11-----0-"": ............D'-- 60 dB @ 1 MHz)
• High Frequency Switching
Circuits
DESCRIPTION
The DG133, DG134, and DG141 are dual precision
single-pole, single-throw analog switches for use in
process control, communication, and instrumentation applications. This series is ideally suited for
applications requiring a constant ON resistance
over the entire analog range.
ON resistance of the DG134 is < 80 n, the DG133 is
< 30 n, and the DG141 is < 10 n, and ON shunt
leakage for all three is < 2 nA. With both drivers in
the "switch OFF" state, total power consumption is
750 jJ.W. Because JFET and bipolar processing is
used, all three devices are relatively radiation
tolerant.
The DG133, DG134, and DG141 each contain two
junction-type field-effect transistors (JFETs) de-
signed to function as two single-pole, single-throw
electronic switches. Level-shifting drivers enable
low-level inputs (0.8 to 2.5 V) to control the
ON-OFF state of each switch. With a positive logic
"0" at the driver input the switches will be OFF.
With a positive logic "1" at the input the switches
will be ON. In the ON state each switch will conduct
current in either direction, and in the OFF state
each switch will block voltages up to 20 V
peak-to-peak.
Packaging for this series include a 14-pin side braze
and flatpack options. Performance grades include
both a military, A suffix (-55 to 125°C) and
industrial, B suffix (-25 to 85°C) temperature
range. The flatpack option is only available in the
military grade.
PIN CONFIGURATION
Dual-In-Llne Package
Flat Package
02~~14 v_w
NO
NC
NO
NO
NO
01
2
3
4
5
6
7
13
12
11
10
9
8
°2
NO
52
IN2
v+
NO
VR(Enable)
IN1
51
NO
52
IN2
vv+
vR
(Enable)
IN1
Tap View
51
Order Numbers:
DG133ALl883. DG134ALl883
DG141ALl883
*
5-22
SIde Braze:
Order Numbers:
DG133AP. DG133BP
DG134AP. DG134BP
DG141AP. DG141BP
Common to Substats and Base of Package
Not Recommended for New Designs
DG133/134/141
...,. Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
S1 o~------------------------------
Truth Table
IN1
VR
(Enable)
0-------.
Switch
a
OFF
1
ON
Logic "0"
Logic "1"
IN 2 0-------------1
S2
Logic
~
~
0.8 V
2.5 V
'Switches Shown for Logic "1" Input
o--------------------------------<~ D2
Two SPST Switches per Package'
ABSOLUTE MAXIMUM RATINGS
V+ to V-
36 V
Current (Any Terminal) ....................... 30 mA
V+ toVo
..................................... 36 V
Storage Temperature .................... -65 to 150°C
VoorVstoV- ................................ 36V
Operating Temperature (A Suffix) ......... -55 to 125°C
(B Suffix) .......... -25 to 85°C
VotoVs
.................................... ±22 V
V+ toVR
•.••.•.•••••..••.••••••••.••••••••••.
25 V
Power Dissipation'
Flat Package" ............................. 750 mW
14-Pin DIP'"
.............................. 825 mW
V R to V- ...................................... 25 V
30 V
VIN to VV+ toV IN
25 V
VIN toV R
±6 V
All leads welded or soldered to PC board.
.. Derate 10 mW/oC above 75°C.
.. , Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
DG133
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 12 V
V-=-18V
VR = a
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd
MINb MAXt UNIT
MINb MAX'
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
IS(OFF)
-10
Vo= 10 V
1,3
2
20
Vo= 8 V
1,3
2
30
Vs= 10 V
Vo= -10 V
1
2
0.03
Vs= 8 V
Vo= -8 V
1
2
Is=-10mA
VIN = 2.5 V
10
-8
8
30
60
V
.n
50
75
1
100
nA
VIN = 0.8 V
Not Recommended for New Designs
5
100
5-23
..
DG133/134/141
..... Siliconix
,.1;11 incorporated
DG133
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0 V
PARAMETER
SYMBOL
LIMITS
1=25°C
A
2=125,S5°C
SUFFIX
3=-55,-25· C -55 to 125°C
B
SUFFIX
-25 to S5°C
MINb MAX'
MINb MAX
TEMP TYpd
UNIT
SWITCH (Cont'd)
Drain OFF
Leakage Current
10(OFF)
Vo= 10 V
Vs= -10 V
1
2
0.02
VO= 8 V
Vs= -S V
1
2
0.1
Vo=Vs= -10 V
1
2
-0.03
V o =Vs=-8V
1
2
-O.OS
1
100
VIN = O.S V
5
100
nA
Channel ON
Leakage Current
10(ON) +
IS(ON)
-2
-100
VIN = 2.5 V
-5
-100
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
60
120
100
150
VIN = 0.8 V
1,3
2
0.1
2
4
4
1
0.6
1
.uA
Input Current with
Input Voltage LOW
IINL
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Clrcult e
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
COlON) +
CS(ON)
OFF Isolation
OIRR
.us
1
f = 1 MHz
1.6
2
Vo = 0 V
Is = 0
1
2.4
Vs= 0 V
10 = 0
1
2.4
Vo=Vs=O
1
2.8
1
>60
1
2.1
1
-1.2
-1.8
-2
1
-1
-1.4
-1.5
R L = 75.n, f = 1 MHz
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
5-24
One Channel ON
VIN = 2.5 V
3
3.3
mA
Not Recommended for New Designs
DG133/134/141
WY' Siliconix
~
incorporated
DG133
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55,
-25
°
C
-55
to
125°C
-25
to
85°C
V-=-18V
VR = a V
b
b
TYpd
MIN
MAXt
UNIT
TEMP
MIN MAX'
SYMBOL
SUPPLY (Cont'd)
Positive Supply Current
1+
Negative Supply Current
1-
Reference Supply Current
IR
All Channels OFF
Both VIN = a V
1
0.1
25
25
1
-0.5
-25
-25
1
-0.5
-25
-25
jJ.A
DG134
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 12 V
V- = -18 V
VR = a V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
MINb MAX' MINb MAXb UNIT
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
1,2,3
VANALOG
rOS(ON)
Source OFF
Leakage Current
IS(OFF)
Drain OFF
Leakage Current
I o (OFF)
Channel ON
Leakage Current
IO(ON) +
Is(oN)
Vo= 10 V
1,3
2
30
Vo= 8 V
1,3
2
35
Vs= 10 V
Vo= -10 V
1
2
0.01
Vs= 8 V
Vo= -8 V
1
2
0.05
Vo= 10 V
Vs= -10 V
1
2
0.005
Vo= 8 V
Vs= -8 V
1
2
0.025
Vo=Vs= -10 V
1
2
-0.02
Vo=Vs= -8 V
1
2
-0.05
Is= -10 rnA
V 1N = 2.5 V
V 1N = 0.8 V
V1N = 0.8 V
-10
10
-8
8
V
80
150
.0.
100
150
1
100
5
100
1
100
nA
5
100
-2
-100
VIN = 2.5 V
Not Recommended for New Designs
-5
-100
5-25
DG133/134/141
wy" Siliconix
incorporated
~
DG134
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V
3=-55,-25°C -55 to 125°C -25 to 85°C
V- = -16 V'
VR = 0 V
TEMP TYpd MINb MAX' MINb MAXt UNIT
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
60
120
100
150
Input Current with
Input Voltage LOW
IINL
VIN = 0.6 V
1,3
2
0.1
2
4
4
1
0.6
1
1
1.6
2
J.lA
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Clrculte
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
CO(ON) +
CS(ON)
OFF Isolation
OIRR
f = 1 MHz
J.ls
Vo= 0 V
Is = 0
1
2.4
Vs= 0 V
10 = 0
1
2.4
Vo=Vs=O
1
2.6
1
>60
1
2.1
1
-1.2
-1.6
-2
-1.4
-1.5
R L = 75.0., f = 1 MHz
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1
Positive Supply Current
1+
1
0.1
Negative Supply Current
1-
1
-0.5
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
5-26
One Channel ON
VIN = 2.5 V
All Channels OFF
Both VIN = 0 V
3
3.3
25
mA
25
J.lA
Not Recommended for New Designs
DG133/134/141
..... Siliconix
incorporated
~
DG141
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 12 V
V- = -18 V
VR = a V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
TEMP TYpd
MINb MA>f
B
SUFFIX
-25 to 85°C
MINb MAXt
UNIT
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
IS(OFF)
Drain OFF
Leakage Current
10(OFF)
Channel ON
Leakage Current
10(ON) +
IS(ON)
-10
Vo= 10 V
1,3
2
6.3
VO= 8 V
1,3
2
9.5
Vs= 10 V
Vo= -10 V
1
2
0.04
Vs= 8 V
Vo= -8 V
1
2
0.06
Vo= 10 V
Vs= -10 V
1
2
VO= 8 V
Vs= -8 V
1
2
Vo=Vs= -10 V
1
2
-0.4
Vo=V s =-8V
1
2
-1.0
Is=-10mA
VIN = 2.5 V
10
-8
8
V
10
20
.0.
15
25
10
1000
VIN = 0.8 V
15
300
10
1000
nA
VIN = 0.8 V
15
300
-2
-100
VIN = 2.5 V
-5
-100
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.5 V
1,2
3
60
120
100
150
Input Current with
Input Voltage LOW
IINL
VIN = 0.8 V
1,3
2
0.1
2
4
4
1
1
1.5
2.5
2.5
J,lA
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Clrculte
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
C S(OFF)
Channel-ON Capacitance
COlON) +
CS(ON)
OFF Isolation
OIRR
f = 1 MHz
J,ls
1
1.15
Vo= a V
Is = a
1
3
aV
a
1
3
1
2.8
1
>50
Vs=
10 =
Vo=Vs=O
RL = 75.0., f = 1 MHz
Not Recommended for New Designs
pF
dB
5-27
DG133/134/141
..... Siliconix
incorporated
~
DG141
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0 V
PARAMETER
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55,-25°C -55 to 125°C -25 to 85°C
TEMP TVpd MINb MA.J MINbMAX t
SYMBOL
UNIT
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
1
2.1
1
-1.2
-1.8
-2
IR
1
-1
-1.4
-1.5
Positive Supply Current
1+
1
0.1
Negative Supply Current
1-
1
-0.5
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
One Channel ON
VIN = 2.5 V
All Channels OFF
Both VIN = 0 V
3
3.3
25
mA
25
)lA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN must be a step function with a minimum rise and fall time of f V l)ls .
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic Input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC
INPUT
t,< 10 ne
tf< 10 ns
3V
OV
SWITCH
INPUT
Switch
Input
Switch
Output
ton' +Vs Sl
t off , -Vs
Vs
SWITCH 0 V
OUTPUT
0
-0.1
-Vs
-1 B V
(LOGIC "1" = SWITCH ON)
5-28
Vs = 10 V A Suffix
Vs = B V B Suffix
(Repeat Test for S3
and IN 2 • ~ and S4 )
Vo=Vs~
RL + rOS(on)
Not Recommended for New Designs
DG133/134/141
.... Siliconix
incorporated
..c.
APPLICATION HINTS
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
12
15
10
-18
-15
-10
VR
Reference
Voltage
(V)
VIN
Logic Input
Voltage
VINH MinI
VINLMax
(V)
Vs or Vo
Analog
Voltage
Range
(V)
0
0
0
2.5/0.8
2.5/0.8
2.5/0.8
-10 to 10
-5 to 13
o to 8
Not Recommended for New Designs
5-29
DG139/1421145
Dual DPDT JFET
Analog Swiches
..... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• ( < 1 Jl.W) Standby Power
• Minimizes Standby
Power Requirement
• Portable and Battery
Powered Systems
• Constant rDS(ON)
Over Signal Range
• Better Radiation Tolerance
than CMOS
• Switching in Satellite
Applications
• High Off Isolation
( > 60 dB @ 1 MHz)
• Less Signal Distortion
than CMOS
• Low Distortion Circuits
• Bipolar Drivers
• Higher Frequency
Switching
• High Frequency Switching
Circuits
DESCRIPTION
The DG139. DG142. and DG145 are precision dual
double-pole double-throw analog switches designed
for use in low distortion. high frequency circuits.
ON resistance of the DG139 is < 30 n. the DG142
n and the DG145 is < 10 n an::! ON shunt
leakage for all three is < 2 nA. With buth drivers in
the ·switch OFF" state. total power consumption is
< 750 Jl.W. By using the JFET process. all three
analog switches are relatively radiation tolerant.
< 80
The DG139. DG142 and DG145 each contain four
junction-type
field-effect
transistors
(JFETs)
designed to function as two double-pole
double-throw electronic switches. Level-shifting
drivers enable low-level inputs (2 V" to 3 V) to
control the ON-OFF state of the switches. The driver
inputs are connected differentially. therefore with
input IN2 connected to a 2.5 voltage reference, a
positive logic "0" at the input IN1 will turn switches
1 and 3 OFF and switches 2 and 4 ON. A positive
logic" 1" at IN1 will turn switches 1 and 3 ON and
switches 2 and 4 OFF. The normally grounded VR
terminal may be used as an "inhibit" terminal. in
which case all switches may be held OFF with a
positive voltage applied to YR. In the ON state each
switch conducts equally well in either direction. and
in the OFF state each switch will block voltages up
to 20 V peak-to-peak.
Packaging for this series includes the 14-pin side
braze and flatpack options. Performance grades
include both a military. A suffix (-55 to 125°C) and
industrial. B suffix (-25 to 85°C) temperature
range. The f1atpack option is only available in the
military grade.
PIN CONFIGURATION
Flat Package
Dual-In-Llne Package
02~~14 v-v+
84
2
13
04
NO
03
3
12
4
5
6
10
83
01
2
IN2
8
11
9
V R (Inhibit)
IN1
81
Top View
Order Numbers:
DG139ALl883, DG142ALl883
DG145ALl883
5-30
Order Numbers:
DG139AP, DG139BP
DG142AP. DG142BP
Not Recommended for New Designs
DG139/1421145
. . . . Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
S2
o---------~~
~~D4
S40
Truth Table
I
IN:! 0
IN1
Two DPDT Switches per Package*
D2
~ ____
--1
O------iV- ----,
I
S1 0~-------_4~ D1
I
S3
o---------<~
Logic
SW1
SW3
SW2
SW4
0
1
OFF
ON
ON
OFF
* Switches Shown for Logic "1" Input
at IN1 and a 2.5 V reference at IN2
D3
ABSOLUTE MAXIMUM RATINGS
V+ to V-, Vo orVs
........................... 36 V
Current, (Any Terminal)
...................... 30 mA
VoorVstoV- ................................ 36V
Storage Temperature .................... -65 to 150°C
Vo toYs ..................................... ±22 V
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
V+ toV R
•••••••.••••.•••••.•••••••••••••••••••
V+ to VIN1
or V IN2
25 V
............................ 25 V
V R to V- ...................................... 25 V
V IN1 toVIN2
V IN1 orV IN2 toVR
Power Dissipation *
Flat Package* * ............................. 750 mW
14-Pin DIP* * * .............................. 825 mW
±6 V
.............................
±6 V
V IN1 or V IN2 to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 V
All leads welded or soldered to PC board.
** Derate 10 mW/oC above 75°C.
*** Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
DG139
Test Conditions
LIMITS
Unless Otherwise Specified: 1=25°C
A
B
2=125,B5°C
V+ = 12 V
SUFFIX
SUFFIX
V-=-1BV
3=-5S,-2SoC -55 to 125°C -25 to BSoC
VR = 0
VIN2 = 2.5 V
TEMP TYpd MINb MAX' MINb MAXt
UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Source OFF
Leakage Current
c
1,2,3
VANALOG
rOS(ON)
IS(OFF)
Is= -10
V IN1 = 3
(SW1, 3
V IN1 = 2
(SW2, 4
mA
V
ON)
V
ON)
V IN1 =2V
(SW1, 3 OFF)
V IN1 = 3 V
(SW2, 4 OFF)
-10
Vo= 10 V
1,3
2
20
Vo= 8 V
1,3
2
35
Vs= 10 V
Vo= -10 V
1
2
0.15
Vs= 8 V
Vo= -8 V
1
2
0.75
10
-B
B
V
30
60
.0.
Not Recommended for New Designs
50
75
1
100
nA
5
100
5-31
DG139/1421145
Siliconix
incorporated
DG139
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
V+ = 12 V
2=125,85°C
SUFFIX
SUFFIX
V- = -18 V
3=-55,-25°C -55 to 125°C -25 to 85°C
VR = 0
V IN2 = 2.5 V
TEMP TYpd MINb MAX' MINb MAXb UNIT
SWITCH (Cont'd)
Drain OFF
Leakage Current
10(OFF)
VIN1 =
(SW1,
V IN1 =
(SW2,
2
3
3
4
V
OFF)
V
OFF)
Vo= 10 V
Vs= -10 V
1
2
0.03
Vo= 8 V
Vs= -8 V
1
2
0.15
VIN1 =
(SW1,
V IN1 =
(SW2,
3
3
2
4
V
ON)
V
ON)
Vo=Vs= -10 V
1
2
-O.OS
Vo=Vs= -8 V
1
2
-0.12
1
100
5
100
nA
Channel ON
Leakage Current
10(ON) +
IS(ON)
-2
-100
-5
-100
INPUT
1 Current Input
oltage LOW
IIN1L
VIN1 = 2 V
1,3
2
0.001
0.1
2
4
4
Input 2 Current Input
2 Voltage LOW
IIN2L
V IN2 = 2 V, VIN1 = 2.5 V
1,3
2
0.001
0.1
2
4
4
Input 1 Current Input
1 Voltage HIGH
IIN1H
VIN1 = 3 V
1,2
3
20
60
120
100
1S0
IIN2H
VIN2 = 3 V, V IN1 = 2.5 V
1,2
3
20
60
120
100
150
1
0.8
1
1
1.6
2
In~ut
1
.I1A
In~ut
2
2 Current Input
oltage HIGH
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test CircuitS
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
CO(ON) +
CS(ON)
OFF Isolation
OIRR
f = 1 MHz
.I1s
Vo = 0 V
Is = 0
1
2.4
Vs= 0 V
10 = 0
1
2.4
Vo=Vs=OV
1
2.8
1
>60
1
2.6
1
-1.3
-2
-2.2
1
-1.4
-2.2
-2.4
R L = 7S.o., f = 1 MHz
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
5-32
One Channel ON
V IN1 = 2 V or V IN1 = 3 V
4.2
4.S
mA
Not Recommended for New Designs
DG139/1421145
.",. Siliconix
incorporated
~
DG139
ELECTRICAL CHARACTERISTICS q
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
SUFFIX
V+ = 12 V
SUFFIX
V- = -18 V
3=-55,-25°C -55 to 125°C -25 to 85°C
VR = 0
V IN2 = 2.5 V
TEMP TYpd MINb MAX' MINb MAXt UNIT
SUPPLY (Cont'd)
Positive Supply Current
1+
Negative Supply Current
1-
Reference Supply Current
IR
All Channels OFF
V IN1 =VIN2 = 0.8 V
1
0.75
25
25
1
-1
-25
-25
1
-0.2
-25
-25
)J.A
ELECTRICAL CHARACTERISTICS a
DG142
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 12 V
V- = -18 V
VR = 0
V IN2 = 2.5 V
SYMBOL
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55, -25 ° C -55 to 125°C -25 to 85°C
TEMP TYpd
MINb MAX' MINb MAXt UNIT
III
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
IS(OFF)
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON) +
IS(ON)
Is=-10mA
VIN1 = 3 V
(SW1, 3 ON)
VIN1 = 2 V
(SW2, 4 ON)
-10
Vo=10V
1,3
2
30
Vo= 8 V
1,3
2
35
10
-8
8
V
80
150
.0.
V IN1 =
(SW1,
V IN1 =
(SW2,
2
3
3
4
V
OFF)
V
OFF)
Vs= 10 V
Vo= -10 V
1
2
0.01
Vs= 8 V
VO= -8 V
1
2
0.05
VIN1 =
(SW1,
VIN1 =
(SW2,
2
3
3
4
V
OFF)
V
OFF)
Vo= 10 V
Vs= -10 V
1
2
0.005
Vo= 6 V
Vs= -8 V
1
2
0.025
VIN1 =
(SW1,
V IN1 =
(SW2,
3
3
2
4
V
ON)
V
ON)
Vo=Vs= -10 V
1
2
-0.02
VD=VS= -8 V
1
2
-0.05
100
150
1
100
5
100
1
100
nA
Not Recommended for New Designs
5
100
-2
100
-5
-100
5-33
DG139/1421145
..... Siliconix
incorporated
~
DG142
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0
V IN2 = 2.5 V
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55, -25 ° C -55 to 125°C -25 to 85°C
EMP Typd
MINb MAX' MINb MAX
UNIT
INPUT
Input 1 Current Input
1 Voltage LOW
In~ut
2
2 Current Input
oltage LOW
IIN1L
IIN2L
V IN1
=2 V
1,3
2
0.0005
0.1
2
4
4
1,3
2
0.001
0.1
2
4
4
1,2
3
25
60
120
100
150
1,2
3
25
60
120
100
150
1
0.5
0.8
1
1
1.1
1.6
2.0
Vo = 0 V
Is =0
1
2.4
Vs= 0 V
10 = 0
1
2.4
1
2.8
1
>60
1
2.6
1
-1.3
-2
-2.2
-2.2
-2.4
V IN2 = 2 V, V IN1 = 2.5 V
Jl.A
In~ut
1 Current Input
oltage HIGH
IIN1H
Input 2 Current Input
2 Voltage HIGH
IIN2H
1
VIN1
=3 V
V IN2 = 3 V, V IN1 = 2.5 V
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Clrculte
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
COlON) +
CS(ON)
OFF Isolation
OIRR
f = 1 MHz
VD=VS=OV
R L = 75!l., f = 1 MHz
Jl.s
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1.4
Positive Supply Current
1+
1
0.75
Negative Supply Current
1-
1
-1
-25
-25
Reference Supply Current
IR
1
-0.2
-25
-25
5-34
One Channel ON
V IN1 = 2 V, V IN1 = 3 V
All Channels OFF
V IN1 = V IN2 = 0.8 V
4.2
4.5
25
mA
25
Jl.A
Not Recommended for New Designs
DG139/1421145
Siliconix
incorporated
DG145
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0
V IN2 = 2.5 V
SYMBOL
PARAMETER
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3--55, -25 ° C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt
UNIT
SWITCH
Analog Signal Range
c
Drain-Souroe
ON Resistance
1,2,3
VANALOG
rOS(ON)
Source OFF
Leakage Current
IS(OFF)
Drain OFF
Leakage Current
10(OFF)
Channel ON
Leakage Current
10(ON) +
IS(ON)
Is=-10mA
V IN1 = 3 V
(SW1, 3 ON)
VIN1 = 2 V
(SW2, 4 ON)
VO= 10 V
1,3
2
Vo= 8 V
1,3
2
VIN1 =
(SW1,
V IN1 =
(SW2,
2
3
3
4
V
OFF)
V
OFF)
Vs=10V
Vo= -10 V
1
2
Vs= 8 V
Vo= -8 V
1
2
V IN1 =
(SW1,
V IN1 =
(SW2,
2
3
3
4
V
OFF)
V
OFF)
Vo= 10 V
Vs= -10 V
1
2
Vo= 8 V
Vs= -8 V
1
2
V IN1 =
(SW1,
VIN1 =
(SW2,
3
3
2
4
V
ON)
V
ON)
Vo=Vs= -10 V
1
2
V o =V s =-8V
1
2
-10
7
10
-8
8
10
20
V
.n
15
25
0.1
10
1000
15
300
0.1
10
1000
nA
15
300
-0.04
-2
100
-5
-100
INPUT
InIVut 1 Current Input
1 oltage LOW
IIN1L
V IN1 = 2 V
1,3
,nIVut 2 Current Input
2 oltage LOW
IIN2L
V IN2 = 2 V, V IN1 = 2.5 V
1,3
,nIVut 1 Current Input
1 oltage HIGH
IIN1H
VIN1 = 3 V
Input 2 Current Input
2 Voltage HIGH
IIN2H
V IN2 = 3 V, V IN1 = 2.5 V
0.001
2
4
4
0.001
0.1
2
4
4
1,2
3
20
60
120
100
150
1,2
3
20
60
120
100
150
1
0.5
1
1.5
1
1.2
2.5
2.5
Vo = 0 V
Is = 0
1
3
Vs= 0 V
10 = 0
1
3
Vo=Vs=O
1
2.8
2
2
0.1
.uA
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circult e
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
COlON) +
CS(ON)
f = 1 MHz
Not Recommended for New Designs
.us
pF
5-35
DG139/1421145
H
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
DG145
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 12 V
V- = -16 V
VR = 0
VIN2 = 2.5 V
OIRR
RL = 75.n., f = 1 MHz
LIMITS
1=2SoC
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MINb MAX' MINb MAXt UNIT
DYNAMIC (Cont'd)
OFF Isolation
1
>50
dB
1
2.6
1
-1.2
-2
-2.2
-2.2
-2.4
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1.4
Positive Supply Current
1+
1
0.75
Negative Supply Current
1-
1
-1
-25
-25
Reference Supply Current
IR
1
-0.2
-25
-25
One Channel ON
VIN1 = 2 V, VIN1 = 3 V
All Channels OFF
VIN1 = V IN2 = 0.8 V
4.2
4.5
25
mA
25
jJ.A
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN must be a step function with a minimum rise and fall time of 1 V/jJ.s.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
t,< 10 ns
tf < 10 ns
LOGIC
INPUT
~~V~U~
VS
Switch
Input
Switch
Output
S2
~~---------<~-·-t~~~~~Vo
OV
SWITCH
INPUT
12 V
V+
---+-------+----:----
-o.P
ton +Vs
toff -Vs
Logic
Input
Sl
0 V------+----'
-16 V
(LOGIC "1" = SWITCH ON)
5-36
(Repeat Test for S3 &
(DG139)
~
)
Vs = ±10 V A Suffix
Vs = ± B V B Suffix
Not Recommended for New Designs
DG139/1421145
..... Siliconix
incorporated
~
APPLICATION HINTS
Reference
Voltage
VIN1
Input 1
Voltage
VINHIVINL
VIN2
Input 2
Voltage
(V)
(V)
(V)
(V)
(V)
-18
-15
-15
0
0
0
3/2
3/2
3/2
2.5
2.5
2.5
-10 to 10
-5 to 13
-5 to 3
V+
V-
Positive
Supply
Voltage
Negative
Supply
Voltage
(V)
12
15
5
VR
Not Recommended for New Designs
Vs or Vo
Analog
Voltage
Range
5-37
W1P'" Siliconix
DG143/144/146
SPOT JFET
Analog Swiches
~
FEATURES
BENEFITS
APPLICATIONS
• Low Standby Power « 1 Jl.W)
• Minimizes Standby
Power Requirement
• Portable and Battery
Powered Systems
• Better Radiation Tolerance
• Switching in Satellite
Applications
• Bipolar Drivers
• Constant rDS(ON)
Over Signal Range
• High Off Isolation
(> 60 dB @ 1 MHz)
• Less Signal Distortion
incorporated
• Low Distortion Circuits
• Higher Frequency
Switching
• High Frequency Switching
Circuits
DESCRIPTION
The DG143, DG144, and DG146 are precIsion
single-pole double-throw analog switches designed
for use in low distortion, high frequency circuits.
ON resistance of the DG143 is < 80 .n, the DG144
< 30 .n and the DG146 is < 10 .n and ON shunt
leakage for all three is < 2 nA. With the driver in the
"switch OFF" state, total power consumption is
< 750 Jl.W. By using the JFET process, all three
analog switches are relatively radiation tolerant.
The DG143, DG144 and DG146 each contain two
(JFETs)
junction-type field-effect
transistors
designed to function as single-pole double-throw
electronic switches. Level-shifting drivers enable
low-level inputs (2 to 3 V) to control the ON-OFF
state of the switches. The driver inputs are
connected differentially, therefore with input IN2
connected to a 2.5 voltage reference, a positive
logic "0" at the input IN 1 will turn switch 1 OFF and
switch 2 ON. A positive logic "1" at IN 1 will turn
switch 1 ON and switch 2 OFF. The normally
grounded VR terminal may be used as an "inhibit"
terminal, in which case all switches may be held
OFF with a positive voltage applied to VR. In the ON
state each switch conducts equally well in either
direction, and in the OFF state each switch will
block voltages up to 20 V peak-to-peak.
Packaging for this series include a 14-pin side braze
and flatpack options. Performance grades include
both a military, A suffix (-55 to 125°C) and
industrial, B suffix (-25 to 85°C) temperature
range. The flatpack option is only available in the
military grade.
PIN CONFIGURATION
Flat Package
FUNCTIONAL BLOCK DIAGRAM
82
Dual-In-Une Package
:02~JM14
: =
~
NO
NO
NO
01
4
5
6
7
11
10
9
8
v+
VR INHIBIT
IN1
81
VR INHIBIT
NO
IN1
51
Top View
One 5POT 8wltch per Package'
Top View
Order Numbers:
DG143AL/883, DG144AL/883
or DG146ALl883
Order Numbers:
DG143AP. DG143BP
DG144AP. DG144BP
DG146AP. DG146BP
Truth Table
LOGIC
0
1
SWl
OFF
ON
SW2
ON
OFF
·Swltches Shown for Logic "1" Input at
INI. and 2.5 V Reference at IN2-
5-38
Not Recommended for New Designs
DG143/144/146
. , . Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
V+ to V-, Vo orVs
Current, (Any Terminal)
........................... 36 V
Vo orVs to V- .................•.............. 36 V
Storage Temperature .................... -65 to 150°C
VotoVs ..................................... ±22 V
Operating Temperature (A Suffix) ......... -55 to 125°C
(9 Suffix) .......... -25 to 85°C
V+ to VR ...................................... 25 V
V+ to VIN1
orVIN2
...................... 30 mA
............................ 25 V
Power Dissipation"
Flat Package"" ............................. 750 mW
14-Pln DIP""" .............................. 825 mW
VR to V- ...................................... 25 V
±6 V
All leads welded or soldered to PC board.
Derate 10 mW/oC above 75°C.
""" Derate 11 mW/OC above 75°C.
V IN1 or VIN2 to V R ............................. ±6 V
VIN1 or V IN2 to V- . . . . . . . . . . . . . . . . . . . . . . • . . . . .. 30 V
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
DG143
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
V+ = 12 V
SUFFIX
SUFFIX
V- = -18 V
3=-55,-25°C -55 to 125°C -25 to 85°C
VR = 0 V
V IN2 = 2.5 V
EMP TVpd MINb MA>f MINb MAXb UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Source OFF
Leakage Current
C
1,2,3
VANALOG
rOS(ON)
Is=-10mA
V IN1 =3V
(SW10N)
V IN1 = 2 V
(SW2 ON)
-10
Vo= 10 V
1,3
2
30
Vo= 8 V
1,3
2
35
Vs= 10 V
Vo= -10 V
1
2
0.15
Vs= 8 V
Vo= -8 V
1
2
0.75
Vo= 10 V
Vs= -10 V
1
2
0.03
Vo= 8 V
Vs= -8 V
1
2
0.15
Vo=Vs= -10 V
1
2
-0.05
1
-0.12
10
-8
8
V
80
150
.0.
100
150
1
100
IS(OFF)
V IN1 = 2 V
(SWl OFF)
VIN1=3V
(SW2 OFF)
Drain OFF
Leakage Current
I o (OFF)
Channel ON
Leakage Current
IO(ON) +
IS(ON)
V IN1 = 3 V
(SW10N)
V IN1 = 2 V
(SW2 ON)
V o =Vs=-8V
5
100
1
100
nA
5
100
-2
-100
-5
-100
2
INPUT
In~ut
1 Current Input
oltage LOW
IIN1L
V IN1 =2V
Input 2 Current Input
2 Voltage LOW
IIN2L
VIN2 = 2 V, VIN1 = 2.5 V
1
1,3
2
0.001
0.1
2
4
4
1,3
0.001
0.1
2
4
4
JJ.A
Not Recommended for New Designs
2
5-39
W'F' Siliconix
DG143/144/146
~
incorporated
DG143
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0 V
VIN2 = 2.5 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MINb MAX' MINb MAXt UNIT
INPUT (Cont'd)
In~ut
1
1 Current Input
oltage HIGH
1,2
3
25
35
60
120
100
150
1,2
3
25
35
60
120
100
150
1
0.5
0.8
1
1
1.1
1.6
2
Vo = 0 V
Is = 0
1
2.4
Vs= 0 V
10 = 0
1
2.4
1
2.8
1
>60
1
2.6
1
-1.3
-2
-2.2
-2.2
-2.4
VIN1 =3V
IIN1H
JJ.A
In~ut
2
2 Current. Input
oltage HIGH
IIN2H
V IN2
=3 V,
V IN1 = 2.5 V
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test CircuitS
Turn-OFF Time
tOFF
Drain-OFF Capacitance
CO(OFF)
Source-OFF CapaCitance
CS(OFF)
Channel-ON Capacitance
CO(ON) +
CS(ON)
f = 1 MHz
Vo=Vs=OV
R L = 75.{1, f = 1 MHz
OFF Isolation
JJ.s
pF
dB
SUPPL.Y
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1.4
Positive Supply Current
1+
1
0.75
Negative Supply Current
1-
1
-1
-25
-25
Reference Supply Current
IR
1
0.5
-25
-25
5-40
One Channel ON
V IN1 = 2 V or VIN1 = 3V
All Channels OFF
VIN1 =VIN2 = 0.8 V
4.2
4.5
25
mA
25
JJ.A
Not Recommended for New Designs
DG143/144/146
WY' Siliconix
~
incorporated
DG144
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
V+ = 12 V
SUFFIX
SUFFIX
V- = -18 V
3=-55,-25°C -55 to 125°C -25 to 85°C
VR = 0 V
V 1N2 = 2.5 V
TEMP TYpd MINb MAX' MINb MAX
UNIT
SWITCH
Analog Signal Range
c
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
I s =-10mA
VINl = 3 V
(SW10N)
V 1N1 = 2 V
(SW2 ON)
Channel ON
Leakage Current
Vo=10V
1,3
2
20
Vo= 8 V
1,3
2
35
Vs=10V
Vo= -10 V
1
2
0.15
Vs= 8 V
Vo= -8 V
1
2
0.75
VO= 10 V
Vs= -10 V
1
2
0.03
Vo= 8 V
Vs= -8 V
1
2
0.15
Vo=Vs= -10 V
1
2
-0.05
Vo=V s =-8V
1
2
-0.12
10
-8
8
30
60
V
.0.
50
75
1
100
IS(OFF)
V 1N1 =2V
(SW10FF)
V 1N1 = 3 V
(SW2 OFF)
Drain OFF
Leakage Current
-10
5
100
1
100
nA
IO(OFF)
IO(ON) +
IS(ON)
V 1N1 = 3 V
(SW10N)
V 1N1 = 2 V
(SW2 ON)
5
100
-2
-100
-5
-100
INPUT
Input 1 Current Input
1 Voltage LOW
In~ut
2
2 Current Input
oltage LOW
IIN1L
V 1N1 = 2 V
1,3
2
0.001
0.1
2
4
4
IIN2L
V 1N2 = 2 V, V 1N1 = 2.5 V
1,3
2
0.001
0.1
2
4
4
20
60
120
100
150
J,lA
In~ut
1
1 Current Input
oltage HIGH
In~ut
2
2 Current Input
oltage HIGH
IIN1H
V 1N1 = 3 V
1,2
3
IIN2H
VIN2 = 3 V, V 1Nl = 2.5 V
1,2
3
20
60
120
100
150
1
0.5
0.8
1
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit"
Turn-OFF Time
tOFF
Not Recommended for New Designs
J,ls
1
1.0
1.6
2
5-41
DG143/144/146
. . . . Siliconix
incorporated
~
DG144
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0 V
V IN2 = 2.5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt UNIT
DYNAMIC (Cont'd)
Drain-OFF Capacitance
CO(OFF)
Source-OFF Capacitance
CS(OFF)
Channel-ON Capacitance
CO(ON) +
CS(ON)
f = 1 MHz
Vo= 0 V
Is = 0
1
2.4
Vs= 0 V
10 = 0
1
2.4
Vo = Vs = 0 V
1
2.8
1
>60
1
2.6
1
-1.3
-2
-2.2
-2.2
-2.4
RL = 75.0., f = 1 MHz
OFF Isolation
pF
dB
SUPPLY
4.2
4.5
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
IR
1
-1.4
Positive Supply Current
1+
1
0.75
Negative Supply Current
1-
1
-1
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
One Channel ON
VIN1 = 2 V or VIN1 = 3V
All Channels OFF
VIN1 =VIN2 = 0.8 V
25
mA
25
.I1A
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
DG146
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B
2=125,85°C
V+ = 12 V
SUFFIX
SUFFIX
V- = -18 V
3=-55, -25 ° C -55 to 125°C -25 to 85°C
VR = 0 V
VIN2 = 2.5 V
TEMP TYpd MINb MAX' MINb MAXb UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
5-42
c
1,2,3
VANALOG
rOS(ON)
Is=-10mA
V IN1 = 3 V
(SW10N)
V IN1 = 2 V
(SW2 ON)
Vo= 10 V
1,3
2
VO= B V
1,3
2
-10
7
10
-8
8
V
10
20
.0.
15
25
Not Recommended for New Designs
DG143/144/146
. . , . Siliconix
incorporated
~
DG146
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V-=-18V
VR = a V
V 1N2 = 2.5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
MINb MAX' MINb MAXb UNIT
SWITCH (Cont'd)
Source OFF
Leakage Current
Vs= 10 V
Vo= -10 V
1
2
Vs= 8 V
Vo= -8 V
1
2
Vo= 10 V
V s =-10V
1
2
Vo= 8 V
Vs= -8 V
1
2
Vo=Vs= -10 V
1
2
Vo=Vs= -8 V
1
2
0.1
10
1000
ISIOFF)
V 1N1 = 2 V
(SW10FF)
V 1N1 = 3 V
(SW2 OFF)
Drain OFF
Leakage Current
10IOFF)
Channel ON
Leakage Current
1010N) +
ISION)
V 1N1 = 3 V
(SW10N)
V 1N1 = 2 V
(SW2 ON)
15
300
0.1
10
1000
nA
15
300
-0.04
-2
-100
-5
-100
INPUT
Input 1 Current Input
1 Voltage LOW
IIN1L
V 1N1 = 2 V
1,3
2
0.001
0.1
2
4
4
Input 2 Current Input
2 Voltage LOW
IIN2L
V 1N2 = 2 V, V 1N1 = 2.5 V
1,3
2
0.001
0.1
2
4
4
1,2
3
20
60
120
100
150
1,2
3
20
60
120
100
150
1
0.5
1
1.5
1
1.2
2.5
2.5
Vo = 0 V
Is = 0
1
3
Vs= 0 V
10 = 0
1
3
Vo=Vs=OV
1
2.8
f = 1 MHz
1
>50
J1A
Input 1 Current Input
1 Voltage HIGH
IIN1H
V 1N1 = 3 V
Input 2 Current Input
2 Voltage HIGH
IIN2H
V 1N2 = 3 V, V 1N1 = 2.5 V
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit"
Turn-OFF Time
tOFF
Drain-OFF Capacitance
COIOFF)
Source-OFF Capacitance
C SIOFF)
Channel-ON Capacitance
COlON) +
CS(ON)
OFF Isolation
f = 1 MHz
R L = 75.n"
Not Recommended for New Designs
J1S
pF
dB
5-43
DG143/144/146
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
DG146
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = -18 V
VR = 0 V
V IN2 = 2.5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd
MINb MAXt UNIT
MINb MAX'
SUPPLY
Positive Supply Current
1+
Negative Supply Current
l-
Reference Supply Current
4.2
4.5
1
2.6
1
-1.2
-2
-2.2
IR
1
-1.4
-2.2
-2.4
Positive Supply Current
1+
1
0.75
Negative Supply Current
1-
1
-1
-25
-25
Reference Supply Current
IR
1
-0.5
-25
-25
One Channel ON
V IN1 = 2 V or V IN1 = 3V
All Channels OFF
VIN1 = V IN2 = 0.8 V
25
mA
25
J.lA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN must be a step function with a minimum rise and fall time of 1 V/)J,s.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
2.5 V
tr
tf
LOGIC
3.0 VINPUT 0 V
2.5 V
S'f~~~~
Vs __
12 V
< 10 ns
< 10 ns
2.5 V
__
S'f~~~~
~___~====~ ~==
SWITCH
OUTPUT 0 V _ - j - - J
t OFF: - V s
tON: + V s
Jrt+~~~
S
02+-----o--;-:o~t- D
S1
S2
S3
S4
I
I
I
I
IN 1
IN2
Logic "0" < 0.8 V
Logic "1" ~ 2.0 V
__ J
IN3
'Switches Shown for Logic "1" Input
IN4
VOne 4-Channel Switch per Package'
ABSOLUTE MAXIMUM RATINGS
Storage Temperature (A & 8 Suffix) ....... -65 to 150°C
(C Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
(C Suffix) ............ a to 70°C
Power Dissipation (Package)'
Flat Package" ............................. 750 mW
14-Pin Ceramic DIP'" ....................... 825 mW
14-Pln Plastic DiP' .. ' ....................... 470 mW
V+ to V- ..................................... 36 V
V+ to V D ...................................... 25 V
V+toVs ······································25V
Vs to V- ...................................... 36 V
V D to V- ...................................... 36 V
VStoVD ...................................... 25V
V L to V- ...................................... 30 V
V L toV IN
V L toVR
V IN toVR
..................................... ±6 V
••••••••••••.••••••.•••.•••.••.•••••••
±6 V
.••••••••.•..••.••.••••.•..••..••....
±6 V
All leads welded or soldered to PC board.
Derate 10 mW/oC above 75°C.
Derate 11 mW/oC above 75°C.
.. " Derate 6.3 mW/oC above 75°C.
Current (Any Terminal) ........................ 20 mA
ELECTRICAL CHARACTERISTICS a
Test Conditions Unless
Otherwise Specified:
PARAMETER
SYMBOL
V+ = 10 V
V- = -20 V
VR = a V
VL = 5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd
MINb MAX
MINb
-10
-10
MINb MAX'
C
SUFFIX
a to 70°C
MAX~ UNIT
SWITCH
Analog Signal Range c VANALOG
V D = 10 V
Drain-Source
ON Resistance
rDS(ON)
-10
1,2,3
Is=-1 mA
VD=
V IN = 0.8 V
aV
VD= -10 V
10
10
10
1,3
2
100
150
250
150
250
200
1,3
2
130
200
350
225
300
300
1,3
2
300
450
600
500
600
600
Not Recommended for New Designs
V
.n
5-47
..
~
~
DG172
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions Unless
Otherwise Specified:
PARAMETER
SYMBOL
V+ = 10 V
V- = -20 V
VR = 0 V
VL = 5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
C
SUFFIX
o to 70°C
MINb MAX'
MINb MAXi
MINb MAXt UNIT
-1
-1000
-5
-100
-10
-4
-10
-300
-10
SWITCH (Cant'd)
Souroe OFF
Leakage Current
IS(OFF)
Vs = -10 V, Vo = 10 V
V IN=2V
1
2
-0.03
Drain OFF
Leakage Current
I o (OFF)
Vo = -10 V, Vs= 10 V
VIN = 2 V
1
2
-0.12
Channel ON
Leakage Current
IO(ON) +
IS(ON)
Vo=Vs=10V
VIN = 0.8 V
1
2
4
4000
10
300
10
Input Current with
Input Voltage HIGH
IINH
VIN=5V
1,3
2
0.1
10
1
10
1
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,3
2
-4000
nA
INPUT
-1
-1
-0.5
-0.5
-1
.lJ.A
mA
DYNAMIC
Turn-ON Time
tON
1
0.3
0.5
1
0.75
1.0
See Switohlng
Time Test Circuit
Turn-OFF Time
tOFF
.lJ.s
Source OFF c
Capacitance
CS(OFF)
Vs=OV,lo=O
f = 1 MHz
1
5
Drain OFF c
Capacitance
CO(OFF)
Vo = 0 V, Is = 0
f = 1 MHz
1
18
1
28
1
>50
1
1.3
1
-2.0
1
2.5
5.7
5.7
5.7
One Channel ON
VIN=OV
IR = 0
1
0.8
2.1
2.1
2.1
One Channel ON
VIN=OV
1
-1.5
ChannelON c
Capacitance
CO(ON) + Vo=VS=OV,VIN=OV
f = 140 kHz
CS(ON)
RL = 100 .n, C L = 3 pF
f = 5 MHz
Off Isolation c
pF
dB
SUPPLY
Positive Supply
Current
1+
Negative Supply
Current
l-
Logic Supply Current
IL
Reference Supply
Current
5-48
IR
One Channel ON
VIN=OV
3
3
-5.1
-3.6
-5.1
-3.6
3
-5.1
mA
-3.6
Not Recommended for New Designs
DG172
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions Unless
Otherwise Specified:
PARAMETER
V+ = 10 V
V- = -20 V
VR = 0 V
VL = 5 V
SYMBOL
LIMITS
1=25·C
A
B
2=125,85·C
SUFFIX
SUFFIX
3=-55,-25·C -55 to 125°C -25 to 85°C
C
SUFFIX
o to 70°C
TEMP TYpd MINb MA>f MINb MAXt
MINb MAX
UNIT
SUPPLY
Positive Supply
Current
1+
Negative Supply
Current
1-
Logic Supply Current
'L
1
0.1
10
10
10
1
-0.01
1
2.0
4.5
4.5
4.5
mA
All Channels OFF
V,N = 5 V
IR = 0
1
0.1
10
10
10
.I1A
All Channels OFF
V,N =5V
1
2.0
JlA
Reference Supply
Current
IR
All Channels OFF
V,N=5V
-20
-4.5
-20
-20
-4.5
-4.5
mA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
..
DIE TOPOGRAPHY
1
r
L..::":~:::~==:!!::.J [CID"C"
Pad
No.
Function
1
2
3
5
6
7
8
9
10
11
12
13
14
Source 3
Source 4
Drain
V- (Substrate)
Input 4
Input 3
Input 2
Input 1
VL
VR
V+
Source 1
Source 2
20X
CMDA
8 Resistors
8 P-channel enhancement MOSFETs
4 PNP Bipolar Transistors
4 NPN Bipolar Transistors
7 Diodes
Not Recommended for New Designs
5-49
DG172
...... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
5V
10 V
SWITCH
INPUT S1
LOGIC 5 V
INPUT 0 V
t,<10ns
tf < 10 ns
SWITCH
OUTPUT
V S ,,+10 V o-If----O"":" ""--+<).---t-~-oV OUT
C
lI
35 pF
S'r~~5~ VS-I-~==:t~-SWITCH
OUTPUT 0 V --I----J
VOUT =Vs
(1/4 CIRCUIT SHOWN)
REPEAT FOR S 2 - S4
Rl
Rl
+ r DS(ON)
APPLICATION HINTS·
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
VR
Reference
Pin
Connection
VL
Logic
Supply
Voltage
(V)
10··
10··
-20
-20
GND
OPEN
5
5
15
-15
GND
5
20
-10
GND
5
5
-15
GND
5
5
-25
GND
5
VIN
Logic Input
VOlt~e
VINH inl
VINL Max
(V)
2.010.8
4.6/0.5
2.010.8
2.010.8
2.010.8
2.010.8
Vs
Analog
Signal
Range
(V)
-10 to 10
-10 to 10
-5 to 15
o to
20
-5 to 5
-15 to 5
• Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing .
•• Electrical Characteristics are based on V+ = +10 V, V- = -20 V only.
5-50
Not Recommended for New Designs
DG180/181/182
High-Speed Driver with
Dual SPST JFET Switches
. . . Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Constant ON Resistance
over Entire Analog Range
• Low Distortion
• Audio Switching
• Eliminates Large Signal
Errors
• Video Switching
• High Bandwidth
Capability
• 0/ A Ladder Switches
Q
Low Leakage
• Low Crosstalk
• Sample/Hold
DESCRIPTION
The DG180-182 are precIsion dual single-pole,
single-throw (SPST) analog switches designed to
provide accurate switching of video and audio
signals. This series, like the entire DG180 family, is
ideally suited for applications requiring a constant
ON resistance over the entire analog range.
Each· device comprises four N-channel JFET
tfMSistors and a bipolar driver (TTL compatible) to
!!I(;hieve fast and aoqurate switch performance. In
the ON state, each switoh conducts current equally
welf in either direction. In· the ·OFF condition, the
switches will block up ·to 20 V peak-to-peak, with
feedthrough less than -60 dB at 10 MHz.
The major design difference fs the ON resistance,
being 10, 30, and 7S ,cHor the DC;; 1SO. D~H~1, Md
DG182 respectively. Reduced switching errors are
achieved through law· leakage current ( IS(OFF)
< 1 nA for the DG181/1 92). Applications which
benefit from flat ON resistance include audio
switching, video switching, and sample and holds.
Packaging options for the DG180-182 include a
14-pin side braze and 10-pin metal can options.
The flatpack version is only available for the DG181.
Performance grades include both a military, A suffix
(-55 to 125°C) and industrial, B suffix (-25 to
85°C) temperature ranges. The flatpack option is
only available in the military grade.
PIN CONFIGURATION
Top View
Dual-In-Llne Package
82
Top View
Flat Package
81
01
82
02
NO
NO
NO
IN 1
IN2
v+
v-
VL
VR
Order Numbers:
Side Braze:
DG1BOAP or DG1BOBP
DG1B1AP or DG1B1BP
DG1B2AP or DG1B2BP
01
2
13
8 1 =3 C12
.14
NO
4
11
NO
IN 1
5
10
v+
vL
6
7
9
8
Top View
Order Number:
DG1B1ALfB83
02
82
NO
NO
IN2
V-'
vR
vL
Metal Can Package
Order Numbers:
DG1 BOAA or DG1 BOBA
DG1B1AA or DG1B1BA
DG1 B2AA or DG1 B2BA
·Common to Substrate and Case
5-51
OG180/181/182
.... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
a-'f"'----0
81 0
IN 1
o---Q-l>-J
~"'----o 02
82 0
IN2
Truth Table'
01
Logic ·0· < 0.8 V
Logic ·1· ~ 2.0 V
o---Q-l>-J
'Switches Shown for Logic ·1· Input
Two SPST SWitches per Package
ABSOLUTE MAXIMUM RATINGS
Current (All Other Pins) .•.•..•••..•....•....•. 30 mA
V+ to V- .••..•..•.•...•••...••.•.••.••....••. 36 V
V+ toVo •.••••.•....••.•••.......•••...•...•• 33 V
Vo to V- .•••..•••.•..•..•••.••....•••.......•• 33 V
VotoV8 .•.•...••.•••..••..•..•.•••.....••.•• ±22V
VL to V- .••••••••••••••••••..•••..•••.....•.•• 36 V
VL toVIN ....•••..•....••....•..••••.••..••••.• 8 V
VL toVR .....•.....•...••..•....•••....•..•.•.• 8 V
VIN toVR ..•••.•••...•...••.......•••..••..•••. 8V
VR to V- ..••....•.....•..••...•.•••.•••...•••. 27 V
VRtoVIN ...................•......•..•....... 2V
Current (S or D) DG180 ..•••••....••••...•.•• 200 mA
Current (S or D) DG181 , DG182 ................ 30 mA
Storage Temperature .•........••..••.... -65 to 150·C
Operating Temperature (A Suffix) ..••.... -55 to 125·C
(8 Suffix) •••.••... -25 to 85·C
Power Dissipation'
10-Pln Metal Can" ..•...••...•....•......... 450 mW
14-Pln DIP'" .............................. 825 mW
14-Pln Flat Pack .. •• ...•....••..••.•..•...•. 900 mW
All leads welded or soldered to PC board.
Derate 6 mW/·C above 75·C.
Derate 11 mW/·C above 75·C .
•••• Derate 10 mW/·C above 75·C.
SCHEMATIC DIAGRAM (Typical Channel)
V+
S
IN
D
R
5-52
DG180/181/182
trY' Siliconix
~
incorporated
DG180
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1_25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
MINb MAx"
MIN' MAXi
-7.5
-7.5
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
rOS(ON)
IS(OFF)
VIN = 2.0 V
15
V
.(1
1,3
2
7.5
10
20
15
25
1
2
0.05
V+=10V,V-=-20V
10
1000
15
300
Vs= 7.5 V
Vo=-7.5V
1
2
0.05
10
1000
15
300
1
2
0.04
V+ = 10 V, V- = -20 V
10
1000
15
300
Vs= -7.5 V
V o =7.5V
1
2
0.03
10
1000
15
300
Is = -10 mA, Vo= -7.5 V
VIN = 0.8 V
Vs= 10 V, VO= -10 V
Source OFF
Leakage Current
15
Vs= -10 V, Vo= 10 V
Drain OFF
Leakage Current
10(OFF)
Channel ON
Leakage Current
10(ON)+
IS(ON)
Vo=Vs= -7.5 V
VIN = 0.8 V
1
2
-0.1
loss
2 ms Pulse Duration
1
300
Input Current with
Input Voltage HIGH
IINH
VIN=5V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-30
1
240
300
350
1
140
250
300
Vs= -5 V, 10 = 0
1
21
Vo=-5V,ls=0
1
17
Vo=Vs= 0 V
1
17
1
>55
Saturation Drain Current
nA
-10
-200
-2
-200
mA
INPUT
10
20
10
20
.l1A
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
OFF Isolation
COlON) +
CS(ON)
f = 1 MHz
f = 1 MHz, R L = 75.(1
ns
pF
dB
5-53
DG180/181/182
H
Siliconix
incorporated
DG180
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt UNIT
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1
0.6
1
-2.7
1.5
1.5
-5
-5
mA
VIN = 0 V or 5 V
Logic Supply Current
IL
1
3
Reference Supply Current
IR
1
-1
4.5
-2
4.5
-2
DG181
EL.ECTRICAL. CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd
MIN b MAX'
MINb MAXt UNIT
-7.5
-7.5
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
rOS(ON)
IS(OFF)
VIN = 2.0 v
15
V
.0.
1,3
2
18
30
60
50
75
1
2
0.05
V+=10V,V-=-20V
1
100
5
100
Vs=7.5V
Vo=-7.5V
1
2
0.07
1
100
5
100
1
2
0.5
V+ = 10 V, V- = -20 V
1
100
5
100
V s =-7.5V
V o =7.5V
1
2
0.6
1
100
5
100
Is = -10 mA, Vo= -7.5 V
VIN = 0.8 V
Vs= 10 V, VO= -10 V
Source OFF
Leakage Current
15
Vs= -10 V, Vo= 10 V
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
Vo=Vs= - 7.5 V
VIN = 0.8 V
1
2
-0.02
Input Current with
Input Voltage HIGH
IINH
VIN=5V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN=OV
1,2,3
-30
-2
-200
nA
-10
-200
INPUT
10
20
10
20
J1A
5-54
-250
-250
DG180/181/182
tI'7' Siliconix
~
incorporated
DG181
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,_25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt
UNIT
DYNAMIC
Turn-ON Time
1
85
150
180
1
~5
130
150
V S = -5 V, 10 = 0
1
9
Vo=-5V,l s =0
1
6
Vo=Vs=OV
1
14
1
>50
1
0.6
1
-2.7
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
COlON) +
CS(ON)
f = 1 MHz
f = 1 MHz, R L = 75!l.
OFF Isolation
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1.5
-5
1.5
-5
rnA
V IN =OVor5V
Logic Supply Current
IL
1
3.1
Reference Supply Current
IR
1
-1
4.5
-2
4.5
-2
ELECTRICAL CHARACTERISTICS a
DG182
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP Typd
B
SUFFIX
-25 to 85°C
MINb MAX' MINb MAXb UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
rOS(ON)
I s =-10mA, V o =-10V
VIN = 0.8 V
IS(OFF)
VIN = 2.0 V
15
-10
15
V
!l.
1,3
2
35
75
150
100
150
1
2
0.05
V+ = 10 V, V- = -20 V
1
100
5
100
Vs=10V
Vo = -10 V
1
2
0.07
1
100
5
100
Vs= 10 V, VO= -10 V
Source OFF
Leakage Current
-10
1,2,3
VANALOG
nA
5-55
iii
DG180/181/182
fI"fr Siliconix
~
incorporated
DG182
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MINb MAX'
MI~ MAXt UNIT
SWITCH (Cont'd)
Vs=-10V,Vo=10V
Drain OFF
Leakag~ Current
Channel ON
Leakage Current
IO(OFF)
VIN = 2.0 V
V+ = 10 V, V- = -20 V
Vs= -10 V
Vo = 10 V
IO(ON)+
IS(ON)
V o =V s =-10V
VIN = 0.6 V
1
2
0.4
1
100
5
100
1
2
0.5
1
100
5
100
1
2
-0.02
nA
-10
-200
-2
-200
INPUT
Input Current with
Input Voltage HIGH
IINH
V IN =5V
1
2
<0.01
10
20
10
20
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-30
1
120
250
300
1
100
130
150
V s =-5V,l o =0
1
9
Vo=-5V,l s =0
1
6
Vo=Vs=OV
1
14
1
>50
1
0.6
1
-2.7
.llA
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
COlON) +
CS(ON)
f = 1 MHz
f = 1 MHz, RL = 75.(1
OFF Isolation
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1.5
-5
1.5
-5
VIN = 0 V or 5 V
mA
Logic Supply Current
IL
1
3.1
Reference Supply Current
IR
1
-1
4.5
-2
4.5
-2
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
5-56
DG180/181/182
.-F' Siliconix
~
incorporated
DIE TOPOGRAPHY
Interchlp Pad Connections
A
No connection
D
E
From JFET 2, Source
From JFET 1, Source
To JFET 1, Gate
No Connection
No Connection
C To JFET 2, Gate
-t
D
No Connection
B
F
G
H
44 mils
E~=~:l
Pad
No,
20X
10
11
12
13
14
15
CMJB
6
7
8
2
Capacitors
Resistors
P-channel enhancement MOSFET
N-channel depletion JFET
8 PNP Bipolar Transistors
4 NPN Bipolar Transistors
4 Diodes
Function
Input 2
V+
VL
VR
V- (Substrate)
Input 1
TYPICAL CHARACTERSITICS
Supply Current
VS,
Temperature
liN
5
4
YiN and Temperature
VS.
100
~
,
80
--i""" t- .........
"""-
~~ r-......... r-...,:-I-
2
liN
Yi~L
"i
.......... ......
60
.......:IINL
(JlA)
.........
40
r-......
............
-Il20
1+
o
-55 -35 -15
5 25 45 65 85 105 125
T - TEMPERATURE (OC)
-55 -35 -15 5
25 45 65 85
T - TEMPERATURE (OC)
I" -
-VA (MAX),
10mA
-
230
1,,A
210
".,
./
190
rOS(ON)
(.0.) 10
~
110
0
2'5
50
75
T - TEMPEI;lATURE (OC)
100 125
tc;~
Vo = 7.5 V ':;; /Vo = -7.5'(- I-tON, 170
.A' I _ ~
./
tOFF
tOFF
../
~~
(ns) 150
".,
~
Vo=-7.5V
i-"'
130
-50 -25
105 125
10 n DG180
Switching Time VS, Vo and Temperature
=
\b
IINH
o
10 n DG180
rOS(on) vs, Temperature
100
d
=
H =5V
- ,,-
:::;.... I-""
T~
~=/5VI
1
1
1
1
1
1
90
-55 -35 -15
5 25 45 65 85 105 125
T - TEMPERATURE (OC)
5-57
DG180/181/182
flY' Siliconix
~
incorporated
TYPICAL CHARACTERSITICS (Cont'd)
30.n DG181
rOS(on) vs. Temperature
10.n DG180
Leakage VS. Temperature
1000
100
V+ - 10 V
V- = -20 V
~ =5V
R=O
Vs - -VA (MAX).
10= 1 mA
/
10
10 , Is
(nA)
IS OFF /
rOS(ON)
(.0.) 100
"
VV
......r~ ,~",
0.1
IC(fFF) , -
-
85
105
45
65
T - TEMPERATURE (OC)
25
125
10 ~
-55
~
-15
25
65
T - TEMPERATURE (OC)
110
Vo=7.5V __
100
-.A'
90
...,
./
L'
~
./
t:::I""'"
100
./
'Ie ~~5V
~N~ ~V~
80
10
(nA) 10
i= B SUFFIX
~--
~
tOFF I""'"
""-Vo ~ 7.5, V
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
1000
~,.
ASUFFIX'~
0.1
25
75.n DG182
rOS(on) VB. Temperature
45
65
85
105
T - TEMPERATURE (OC)
Vs = -10 V
10 = -10 mA
130
120
./
./
100
B SUFFIX
rOS(ON) 100
(.0. )
,..
10
-55
-
A SUFFIX - I -
-15
25
65
T - TEMPERATURE (OC)
125
75.n DG182
Switching Time VS. 'Ie and Temperature
110
5-58
105
TEST LIMITS :: V+ = 10 V, V- = -20 V
• B SUFFIX - VL = 5 V,VR = 0
• A SUFFIX - Vc = -10 V, Vs = 10 V
120
60
A jUFilX
1000
130
70
10-
30.n DG181
IC(OFF) vs. Temperature
30.n DG181
Switching Time vs. Vo and Temperature
tON,
tOFF
(ns)
.......
..
1010N) + ISION)
~
-
B SUFFIX
70
60
105
Vo =
7~5 V
.A"
tON, 90
tOFF
(ns) 80
--
i:;II"'"
./
~
r;;;o"""
--
-< ./
././ •
Vo = -7.5 V
~~ ~~V
-
:,.......r-
tOFF I...t,;
~Vo=7.5V
I
I
I
I
I I
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
~
~
DG180/181/182
Siliconix
incorporated
TYPICAL CHARACTERSITICS (Cont'd)
75.n DG182
10(OFF) VS. Temperature
Capacitance vs. Vo orVs (10.0. FET)
30
1000
TEST LIMITS :: V+ = 10 V. V- =-20 V
• B SUFFIX - VL = 5 V.VR = 0
eA SUFFIX - Vo =-10 V. Vs = 10 V
26
100
10
(nA)
10
f: B SUFFIX
22
....... ~FF(_ -
18
t'-..
Cs.C o
(pF)
-
A SUFFIX
~
14
C~(OFi)
10
25
45
65
85
105
T - TEMPERATURE (OC)
-8
125
I I
1
I
........
8
.........
6
80
CS(OFF)
.........
8
V+" 15 V
V-" -15 V
VR = 0
VL = 5 V
RL = 75.0.
VIN ?; 220 mV RMS
.......
ISO. 60
(dB)
..... t---
4
"OFF" Isolation vs. Frequency (10.0. FET)
100
VINL = 0.8 V
V INH =2 V
f = 1 MHz
16 '- Co (ON) + CS(ON)
14
o
-4
Vo orVs - DRAIN or SOURCE VOLTAGE (V)
Capacitance vs. Vo or Vs (30-75 .0. FET)
20
18
~Co (ON) + CS(ON)
~
".
0.1
Cs.Co 12
(pF) 10
VINL = 0.8 V
VINH = 2 V
f = 1 MHz
I\..
r--....
i'o
40
......
CO(OFF)-
i'
20
4
CAPACITANCE IS MEASURED FkoMI _
TEST TERMINAL TO COMMON
2
o
-10
-8
-6
-4 -2
0
2
4
6
8
10
o
10·
10.
107
Vo orVs - DRAIN or SOURCE VOLTAGE (V)
f - FREQUENCY (Hz)
"OFF" Isolation vs. Frequency (30-75 .0. FET)
Typical delay. rise. fall. settling times.
and switching transients In this circuit.
100
90
.......
80
i'
70
60
ISO.
(dB) 50
V+ = 15 V
V- = -15 V
VR = 0
VLOG'9 = +5 V
RL = 5.0.
VIN ?; 220 mV RMS
40
30
20
10
o
10·
"f
10·
I 1111111
10.
"
.....
I I
107
f - FREQUENCY (Hz)
10·
If Rgen. RL. or C L Is Increased. there
will be proportional Increases In rise
and/or fall times.
5-59
DG180/181/182
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
OG181. OG182
OG180
6
VIN 4
(V) 2
6
-
o
I
Vo
(V)
4
2
o
Vo
(V)
2
0
2
J
LOGIC INPUT
Vo
\
(V)
.... 1"-0.,
Vgen
6
(V)
/,
I
J
1\
,..,
"
r
Vo
(V)
Vgen
V
1\
4
2
o
=5 V
Vo
(V)
Vgen
1
Vgen
= 10 V
Vgen
=5 V
2
0
I
11
\..
A
II
-2
=0
Vgen
2
=0
~ r-
'
2
.A
0
\
Vo -2
V
(V) -4
Vo
(V)
J
-6
/
-2
......
V
-4
J
I~
Vgen
-6
=-5 V
5
=
Vgen
-5 V
~
j
j
5
~
Vo 0
(V) -5
,
\
/
IV
o
Vo
(V)
~
/
-10
5-60
5
o
= 10 V
,
10
6
-2
o
-
LOGIC INPUT
Vo 10
5
4
o
o
(V)
V IN
Vgen
= -10 V
0.8
1.2
t - TIME (Us)
1.6
0.4
0
-5
/
-10
Vgen
o
0.4
"""-
-
= -10 V
0.8
1.2
t - TIME (US)
1.6
DG180/181/182
.,.. Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC
INPUT
tON :VS =t3V
I OFF: Vs = -3 V
3V
t r < 10"9
If < 10 ns
OV
SWITCH
INPUT
Vs
SWrrCH
OUTPUT
OV
15V
swrrCH
OUTPUT
Vo
(REPEAT TEST FOR
IN2.~. 02)
APPLICATION HINTS·
Switch
Family
10 .n
and
30 n
75
.n
V+
Positive
Supply
Voltage
VNegative
Supply
Voltage
VL
Logic
Supply
Voltage
VR
Reference
Supply
Voltage
VIN
Logic Input
Voltage
VINHMinl
VINLMax
(V)
(V)
(V)
(V)
(V)
(V)
Vs
Analog
Voltage
Range
•
15""
-15
5
GND
2.0/0.8
-7.5 to 15
10
-20
5
GND
2.0/0.8
-12.5 to 10
12
-12
5
GND
2.0/0.8
-4.5 to 12
15""
-15
5
GND
2.0/0.8
-10 t015
10
-20
5
GND
2.0/0.8
-15 to 10
12
-12
5
GND
2.0/0.8
-7 to 12
Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
"" Electrical Parameter Chart based on V+ = 15 V, V- = -15 V, VL = 5 V, VR = GND.
5-61
-DG183/184/185
High-Speed Driver with
Dual DPST JFET Switches
WF Siliconix
,.6;11 incorporated
FEATURES
BENEFITS
APPLICATIONS
• Constant ON Resistance
over Entire Analog Range
• Low Distortion
• Audio Switching
• Reduced Switching Errors
• Precision Switching
• Low Leakage
• Improved Channel
Isolation
• Video Switching
• Eliminates Inadvertent
Shorting Between
Channels
• Sample/Hold
0/ A Ladder Switches
• Low Crosstalk
• Break-Before-Make
Switching
• Video Routing
DESCRIPTION
The DG183-185 are precision dual double-pole,
achieve fast and accurate switch performance. The
single-throw (DPST) analog switches designed to
driver is designed to achieve Break-Before-Make
/:~w'rtOhing action, eliminating inadvertent shorting
provide accurate switching of audio and viqlil9
signals. This series is ideally suited for apJ;Slicaticms ';
·,'(arid.'·; the crosstalk betwee~ channels that may
requiring a constant ON resistance over:~ en~rp\·;.. i..rlii~ul~;}n the ON s.t'i!t~ e~¢~'$WltCh conducts current
analog range.
Y::,;; -\.: '., ::':";i' ~quallx. wetl ~n eit~'dir~~iol1'~~ln the OFF condition
.. :v..... :....
:::
..... th~~:SWitch~~;wi~·.pr.«;lck ·i)tqq·~:~O V peak-to-peak,
The major design difference is in ON":i,&Sistance, :\". wiitfleedthI'6Ugh.ress ..than,:::;eo'dB at 10 MHz.
being 10, 30, and 75 n for the DG183, DG184:and
;:.;2t :.":,'.>
'::';.;:::,.;.'
DG185, respectively.
.. '.:. '.
::;.:··i!.. '.: ;\
.. " ': :.
::":
'. " .. ~.: . ::;':
'.'
'\:.1.'PacrQIging options for the DG183-185 include a
Reducing switchin~0.~r.s ':~ a~!), a.~P9,mPIi~. ':~.
i 16-pin side braze and flat pack. Performance
{JVf'.{i:>r ihe"
grades include both the military, A suffix (-55 to
through low leakagea (nS(C:if.ll:;)
125°C) and industrial, B suffix (-25 to 85°C)
DG184/185). APPlid~ifp,..~~Jvtir~/:'~·neM from flat
ON resistance inclt.id~..,:,·~aydio switching, video
temperature ranges. The flat pack option is only
switching, and sample and holds.
available in the military grade.
\:<
Each device consists of four N-channel JFET
transistors and a bipolar driver (TIL compatible) to
.
The DG184 and DG185 are JAN qualified devices.
PIN CONFIGURATION
Dual-In-Llne Package
Flat Package
Top View
Order Numbers:
DG184AL/883. DG185AL/883
Top View
Order Numbers:
Side Braze: .
DG183AP. DG183BP
DG184AP.DG184BP
DG185AP. DG185BP
5-62
...r Siliconix
incorporated
DG183/184/185
~
FUCTIONAL BLOCK DIAGRAM
S1~01
S3~03
IN1
o--Q---C>_...J
S2~02
S4~04
IN2
o--Q---C>_...J
LogIc "0" $ 0.8 V
LogIc "1" ::: 2.0 V
"'Swltches Shown for Logic 111" Input
Two OPST Switches per Package"
ABSOLUTE MAXIMUM RATINGS
V+ to V- ......•.............................. 36 V
V+ toVo .••............••..........•......•.. 33 V
Vo to V- ........•••...•.•..•..............•... 33 V
Vo toYS ....•................................ ±22 V
VL to V- ...................•....••.....•...... 36 V
VL toVIN ...................................... 8 V
VLtoVR ·······································8V
VIN toVR ...............................•...... 8 V
VR to V- ........•...•.....•.................. 27 V
VR to V- ...............•...................... 27 V
VR toVIN
............•............•.....•..•.. 2 V
Current (S or D) DG183 ........••..•......•.. 200 mA
Current (S or D) DG184, DG185 ............... 30 mA
Current (All Other PIns) ....•..........•.•..•.. 30 mA
Storage Temperature •..•................ -65 to 150°C
OperatIng Temperature (A SuffIx) ........ -55 to 125°C
(8 SuffIx) ......... -25 to 85°C
Power DIssIpatIon16-Pln DIP-- ...•..........•.....•..•..••..•. 900 mW
Flat Pack- - - .................•......•...... 900 mW
All leads welded or soldered to PC board
Derate 12 mW'oC above 75°C
Derate 10 mW'oC above 75°C
SCHEMATIC DIAGRAM (Typical Channel)
S
IN
o
5-63
..
DG183/184/185
Siliconix
incorporated
DG183
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-26 to 85°C
TEMP TYpd MINb MAX' MINb MAXt UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
rDS(ON)
Is(oFF)
VIN = 0.8 V
15
-7.5
15
V
.n
1,3
2
7.5
10
20
15
25
1
2
0.05
V+ = 10 V, V- = -20 V
10
1000
15
300
Vs= 7.5 V
Vo = -7.5 V
1
2
0.05
10
1000
15
300
Vs= -10 V, Vo= 10 V
1
2
0.04
V+ = 10 V, V- = -20 V
10
1000
15
300
Vs= -7.5 V
V o =7.5V
1
2
0.03
10
1000
15,
300
Is=-10mA, Vo=-7.5V
VIN = 2.0 V
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
-7.5
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
Vo=Vs= - 7.5 V
VIN = 2.0 V
1
2
-0.1
loss
2 ms Pulse Duration
1
300
IINH
VIN = 5 V
1
2
<0.01
IINL
VIN=OV
1,2,3
-30
1
240
300
350
1
140
250
300
V s =-5V,l o =0
1
21
Vo=-5V,ls=0
1
17
Vo=Vs=O
1
17
1
>55
Saturation Drain Current
-2
-200
nA
-10
-200
mA
INPUT
Input Current with
Input Voltage HIGH
10
20
10
20
JlA
Input Current with
Input Voltage LOW
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
CO(ON) +
CS(ON)
Off Isolation
5-64
f = 1 MHz
f = 1 MHz, RL= 75.0.
ns
pF
dB
H
DG183/184/185
Siliconix
incorporated
DG183
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt UNIT
SUPPLY
Positive Supply Current
Negative Supply Current
VIN (All) = 0 V
1
3
3
VIN (All) = 5 V
1
0.1
0.1
VIN (All) = 0 V
1
-5.5
-5.5
VIN (All) = 5 V
1
-4
-4
VIN (All) = 0 V
1
4.5
4.5
VIN (All) = 5 V
1
4.5
4.5
VIN (All) = 0 V
1
-2
-2
VIN (All) = 5 V
1
-2
-2
1+
1-
mA
Logic Supply Current
Reference Supply Current
IL
IR
ELECTRICAL CHARACTERISTICS a
DG184
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
B
SUFFiX
-25 to 85°C
MINb MAX'
MINb MAXb UNIT
-7.5
-7.5
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
rOS(ON)
Is = -10 mA, Vo= -7.5 V
VIN = 2.0 V
IS(OFF)
VIN = 0.8 V
Drain OFF
Leakage Current
I o (OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
15
V
.0.
1,3
2
22
30
60
50
75
1
2
0.06
V+ = 10 V, V- = -20 V
1
100
5
100
Vs= 7.5 V
Vo = -7.5 V
1
2
0.05
1
100
5
100
Vs= -10 V, VO= 10 V
1
2
0.04
V+ = 10 V, V- = -20 V
1
100
5
100
Vs= -7.5 V
V o =7.5V
1
2
0.03
1
100
5
100
1
2
-0.02
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
15
Vo=Vs= - 7.5 V
VIN = 2.0 V
-2
-200
nA
-10
-200
5-65
DG183/184/185
..... Siliconix
incorporated
~
DG184
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
Input Current with
Input Voltage HIGH
IINH
V IN=5V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN=OV
1,2,3
-30
1
85
PARAMETER
B
SUFFIX
-25 to 85°C
TEMP Typd MINb MAX' MINb MAX
UNIT
INPUT
10
20
10
20
JlA
-250
-250
DYNAMIC
Turn-ON Time
tON
150
180
See Switching
Time Test Circuit
Turn-OFF Time
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
1
95
Vs=-5V,1 0 =0
1
9
V o =-5V,l s =0
1
6
Vo=Vs=O
1
14
1
>50
tOFF
Source-OFF Capacitance
COlON) +
CS(ON)
f = 1 MHz
f = 1 MHz, R L = 75n.
Off Isolation
ns
130
150
pF
dB
SUPPW
Positive Supply Current
Negative Supply Current
VIN (All) = 0 V
1
3
3
VIN (All) = 5 V
1
0.1
0.1
VIN (All) = 0 V
1
-5.5
-5.5
VIN (All) = 5 V
1
-4
-4
VIN (All) = 0 V
1
4.5
4.5
VIN (All) = 5 V
1
4.5
4.5
VIN (All) = 0 V
1
-2
-2
VIN (All) = 5 V
1
-2
-2
1+
1-
mA
Logic Supply Current
Reference Supply Current
5-66
IL
IR
DG183/184/185
..,. Siliconix
incorporated
~
DG185
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,BSoC
SUFFIX
o
3=-S5,-2S C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to B5°C
MINb MAXt UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
rOS(ON)
I s =-10mA, V o =-10V
VIN = 2.0 V
IS(OFF)
VIN = 0.8 V
Drain OFF
Leakage Current
10(OFF)
Channel ON
Leakage Current
10(oN)+
IS(ON)
15
-10
15
V
.0.
1,3
2
35
75
150
100
150
1
2
0.05
V+ = 10 V, V- = -20 V
1
100
5
100
Vs=10V
Vo = -10 V
1
2
0.07
1
100
5
100
Vs= -10 V, Vo= 10 V
1
2
0.04
1
100
5
100
1
2
0.03
1
100
5
100
1
2
-0.03
1
2
<0.01
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
-10
V+ = 10 V, V- = -20 V
Vs= -10 V
Vo = 10 V
Vo=Vs= -10 V
VIN = 2.0 V
nA
-10
-200
-2
-200
INPUT
Input Current with
Input Voltage HIGH
VIN = 5 V
IINH
10
20
20
J.lA
Input Current with
Input Voltage LOW
1,2,3
-35
1
120
250
300
1
100
130
150
Vs= -5 V, 10 = 0
1
9
Vo=-5V,ls=0
1
6
Vo=Vs=OV
1
14
1
>50
VIN=OV
IINL
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
CO(ON) +
CS(ON)
Off Isolation
f = 1 MHz
f = 1 MHz, RL = 75.0.
ns
pF
dB
5-67
..
DG183/184/185
..... Siliconix
incorporated
~
DG185
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MINb MA>f MINb MAXt UNIT
SUPPLY
=0 V
1
3
3
VIN (All) = 5 V
1
0.1
0.1
VIN (All) = 0 V
1
-5.5
-5.5
VIN (All) = 5 V
1
-4
-4
VIN (All) = 0 V
1
4.5
4.5
VIN (All) = 5 V
1
4.5
4.5
=0 V
1
-2
-2
VIN (All) = 5 V
1
-2
-2
VIN (All)
Positive Supply Current
Negative Supply Current
1+
1-
mA
Logic Supply Current
IL
VIN (All)
Reference Supply Current
IR
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
DIE TOPOGRAPHY (DRIVER)
Interchlp Pad Connections
A
B
C
D
E
F
G
H
Pad
No.
10
11
12
13
14
15
CMJA
8 Capacitors
7 Resistors
12 P-channel enhancement MOSFETs
4 N-channel depletion JFETs
5-68
10 PNP Bipolar Transistors
4 NPN Bipolar Transistors
4 Diodes
From JFET
To JFET 1,
To JFET 3,
From JFET
From JFET
To JFET 4,
To JFET 2,
From JFET
1, Source
Gate
Gate
3, Source
4, Source
Gate
Gate
2, Source
Function
Input 2
V+
VL
VR
v-
(Substrate)
Input 1
DG183/184/185
..w'" Siliconix
~
incorporated
TYPICAL CHARACTERSITICS
Supply Current vs. Temperature
liN vs. \'IN and Temperature
100
5
d
\'INL =
"'ir H = 5 V
4
I L • 1I+,IR
(mA)
~
3
80
...... r--.;;:: t-
--
r-..
r----. .......
"""-
.......
2
'" ........ .....
60
IL-
.........-IINL
liN
-1-
.........
(J.LA) 40
r.......
........... .....
-IR
20
1+
o
-55 -35 -15
5
25
45
65
85 105 125
T - TEMPERATURE (OC)
10
n
IINH
o
-55 -35 -15 5
25 45 65 85
T - TEMPERATURE (OC)
DG183
10
n DG183
SwItchIng TIme vs. Vo and Temperature
rOS(on) vs. Temperature
100
230
V
I
rOS(ON)
(.0. )
105 125
[T
-V AMAX).
10mA
--
10
.,.
210
./
190
130
-
1/
l."...."
A' I_ i.--"'
./
tOFF-
......:~
-....-::::
~
VI=~
.;>
~=/5VI
I'
i"""'
110 ~
-50 -25
0
25
50 75 100 125
T - TEMPERATURE (OC)
t;~
Vo = 7.5 V '-::;; ~VO =-7.5V- f--
170
tON
tOFF
(ns) 150
L:
.A'
I
I
90
-55 -35 -15
I
5
25
45
65
85 105 125
T - TEMPERATURE (OC)
n
10 n DG183
Leakage VS. Tempe,ature
30
DG184
rOS(on) vs. Temperature
100
1000
V+ - 10 V
V- = -20 V
~ 5V
R=O
Vs - -VA (MAX).
10-1 mA
/
10
10, Is
(nA)
Is OFFV
rOS(ON) 100
(.0.)
VV "
B SUFFIX
~
A.;>I'
0.1
25
45
I'
10TFF)I-
65
65
105
T - TEMPERATURE (OC)
-
.
1010N) + ISION)
-
",..
125
10
-55
~
~
-15
~
25
A jUFI'X
65
105
T - TEMPERATURE (OC)
5-69
DG183/184/185
...... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
30.n OG184
10(OFF) vs. Temperature
30.n OG184
Switching Time vs. Vo and Temperature
1000
130
TEST LIMITS :: V+ - 10 V, V- - -20 V
_ B SUFFIX - VL = 5 V,VR = 0
A SUFFIX - Vo = -10 V, Vs = 10 V
120
V'
110
tON
tOFF
(ns)
/'
L'
Vo=7.5V / ' ./"
V
';'~5V
.A'
100
90
~~ ~V~
80
70
60
e
f:::iI"'"
-- -
~ L-- I'7"'t OF
L
~
100
10
(nA)
10
f: B SUFFIX
.... ~
~
I..!.
I-"""'"Vo
~ 7.51V
~
0.1
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
25
75.n OG185
rOS(on) vs. Temperature
1000
....... 1"'"
A SUFFIX ~
45
65
85
105
T - TEMPERATURE (OC)
75.n OG185
Switching Time vs. Vo and Temperature
130
Vs - -10 V
10 - -10 mA
120
/'
110
/'
-< /'
100
rOS(ON) 100
(.0. )
'" -
10
-55
-
70
60
-15
25
65
T - TEMPERATURE (OC)
Vo = 7 j 5 V . / / '
.A
Vo=-7.5V
tON
tOFF' 90
(ns)
80
B SUFFIX
A SUFFIX -
/'
~
to!:;...
14
Capacitance vs.Vo or Vs 10.0. FET
=
26
V1NL = 0.8 V
VINH = 2 V
f
= 1 MHz
I'..
.......
22
10
B SUFFIX
....
-
Cs,Co
(pF)
~
A SUFFIX'§
125
~FF(_ Co (ON)~+ CS(ON)
-
"'" ....
14
10
45
65
85
105
T - TEMPERATURE (OC)
:-....
18
~I"'"
0.1
25
L.--r
~VOj'7.5IV
30
100
5-70
./
I
I
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
105
TEST LIMITS
V+ - 10 V, V- - -20 V
-B SUFFIX - V L = 5 V,VR = 0
eA SUFFIX - Vo = -10 V, Vs = 10 V
10
(nA)
~~ ~Iv~v
~
75.n OG185
10(OFF) vs. Temperature
1000
125
C~(OFI)
-8
-4
o
4
8
Vo orVs - DRAIN or SOURCE VOLTAGE (V)
DG183/184/185
..... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
·OFF" Isolation vs. Frequency 10.0. FET
Capacitance vs. Vo orVs 30-75.0. FET
20
16
.I
I
1I
16 i-CO(ON) + CS(ON)
14
12
Cs,Co
10
(pF)
6
6
4
2
.......
100
V 1NL = 0.6 V
VINH=2V
f = 1 MHz
60
V+ = 15 V
V- = -15 V
VR = 0
VL = 5 V
RL = 75.0.
V1N 2: 220 mV RMS
.........
60
--
~
CS(OFF)
........ I'--..
r-....
ISO.
(dB)
-
40
....
~
CO(OFF)-
....
20
CAPACITANCE IS MEASURED F~OMI
TEST TERMINAL TO COMMON
-
o
o
-10 -6 -6 -4 -2 0 2
4 6
6 10
Vo orVs - DRAIN or SOURCE VOLTAGE (V)
10.
107
f - FREQUENCY (Hz)
105
10·
Typical delay, rise, fall, settling times,
and switching transients In this circuit.
·OFF" Isolation vs. Frequency 30-75.0. FET
100
90
.........
60
....
70
60
ISO.
(dB)
"-
50
40
V+ = 15 V
V- = -15 V
VR = 0
VLOGI9 = +5 V
RL = 5.0.
V1N 2: 220 mV RMS
30
20
HI
o
"f
10'
I 1111111
10.
I I
107
10·
f - FREQUENCY (Hz)
5-71
DG183/184/185
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
....-'I/IIIr-o-lf-------4)'f.'-f-O--.---t---O Vo
If R gen , RL , or C L Is Increased, there
will be proportional Increases In rise
andlor fall times.
OG184, OG185
OG183
+6
6
VIN
Y\tl :
(V)
o
V
(V)
5
o
:
o
r~
J
r~
(V)
..... 1-00..
Vgen
J
I
= 10 V
V
1\
(V)
........
..-
~
Vgen
r~
=0
,
\
J
J
Vgen
+2
0
-2
(
= 10 V
1\
1
\.
Vgen
=5 V
A
Vgen
=0
\ ".....
..
+2
0
\
~
~
-4
I
Vgen
/
-2
Vgen = -5 V
,.
I
I
+5
0
\
-5
r~
. / i"'"'
)
-10
Vgen
=-10 V
0.8
1.2
t - TIME (Jl.S)
1.6
I~
o
0.4
......
-4
-6
= -5
5
5-72
+4
+2
o
A
-6
r~
LOGIC INPUT
+6
'"'
r
-2
+10
+5
o
Vgen - 5 V
2
0
-2
2
0
V
~
.(
6
r~
o
LOGIC INPUT
10
+4
+2
0
I
-5
I
-10
L
Vgen
o
0.4
V
=-10 V
-
0.8
1.2
t - TIME (Jl.S)
1.6
DG183/184/185
If"r' Siliconix
~
incorporated
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC
3.0 V-,-------..
INPUT 0 V
1.5 V
SWITCH
INPUT
15 V
:Vs= +3 V
t,< 10 ns
tON
tf
t OFF:V S=-3V .........L.._ _ _...I.....,
< 10 ns
SI
SWITCH o-II-----a'
INPUT
VS--i-:;:::==I:=:-- ±3 V
(REPEAT TEST
FOR IN2' 8.!ANO 02)
SWITCH
OUTPUT
"'-+O:--"---1~V OUT
SWITCH
OUTPUT 0 V --+--'
tON
(LOGIC "1" = SWITCH ON)
APPLICATION HINTS·
Switch
Family
10 11
and
30 11
75 11
V+
Positive
Supply
Voltage
VNegative
Supply
Voltage
VL
Logic
Supply
Voltage
VR
Reference
Voltage
VIN
Logic Input
Voltage
VINHMinl
VINLMax
(V)
(V)
(V)
(V)
(V)
(V)
15**
-15
5
GND
2.010.8
-7.5 to 15
10
-20
5
GND
2.010.8
-12.5 to 10
12
-12
5
GND
2.010.8
-4.5 to 12
15""
-15
5
GND
2.010.8
-10 t015
10
-20
5
GND
2.010.8
-15 to 10
12
-12
5
GND
2.010.8
-7 to 12
Vs
Analog
Voltage
Range
Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
"" Electrical Parameter Chart based on V+ +15 V, V- -15 V, VL 5 V, VR GND.
=
=
=
=
5-73
DG186/187/188
High-Speed Driver
with SPOT JFET Switch
~
~
FEATURES
BENEFITS
APPLICATIONS
• Constant ON Resistance
over Entire Analog Range
• Low Distortion
• Audio Switching
• Eliminates Large Signal
Errors
• Video Switching
• Low Leakage
• Low Crosstalk
• High Bandwidth
Capability
Siliconix
incorporated
• Sample/Hold
e D/ A Ladder Switches
DESCRIPTION
DG1B6-1BB
are
precision
single-pole,
The
double-throw (SPDT) analog switches designed to_
provide accurate switching of video and audio'
signals. This series, like the entire DG180 family; is __ '
ideally suited for applications requiring a constant
ON resistance over the entire analog raoge;The major design difference is the ON- resistance,
being 10, 30, and 75 !l for the OG186. DG18i. and
DG 188 respectively + Reduced -s~itchin~ j ~rrors are
achieved through low i$akage current ( is(6FF)
< 1 nA for the DG187118a) -. Applications which
benefit from flat ON resistance include audio
switching, video switching, and sample-and-holds.
Each device comprises four N-channel JFET
transistors and a bipolar driver (TTL compatible) to
achieve fast and accurate switch performance. The
. driver is designed to achieve break-before-make
swlt~hlng
action, eliminating the inadvertent
shorting between ohannels and the crosstalk which
would result, In the QN state, e~ch switch conducts
current equally wei! -in erther'dlrection. In the OFF
condition, the Switches wilt block up to 20 V
peak.to-peak. With feedthrough less than -60 dB at
10 MHz.
Packaging for the DG186-188 includes a 14-pin side
braze, flatpack, and 10-pin metal can options.
Performance grades include both a military, A suffix
(-55 to 125°C) and industrial, B suffix (-25 to
85°C) temperature range. The flatpack option is
only available in the military grade.
PIN CONFIGURATION
Top View
Dual-In-Une Package
02
Top View
Flat Package
NC
2
13
N
CI
01
3 I_
12 1 4
81
4
11
IN
5
10
v+
VL
NC
NC
NC
02
82
NC
9
V-
8
VR
V-'
VL
Top View
Order Numbers:
Side Braze:
DG186AP or DG186BP
DG187AP or DG187BP
DG188AP or DG188BP
Order Numbers:
DG167 ALl663 or DG188ALl883
Metal Can Package
Order Numbers:
DG186AA or DG186BA
DG187AA or DG187BA
DG188AA or DG188BA
* Common
5-74
to Substrate and Case
DG186/187/188
.... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
S1~01
Truth Table'
I LOGIC I
~.t.......---o 02
S2 0
I
I
I
IN
o--D--t>-..J
~
I
SW 1
OFF
ON
Logic "0"
Logic "1"
~
~
SW2
ON
OFF
0.8 V
2.0 V
• Switches Shown for Logic "1" Input
One SPDT Switch per Package
ABSOLUTE MAXIMUM RATINGS
Current (All Other Pins) .•..................... 30 mA
V+ to V- •.••.••..•..•....••......•...•.....•. 36 V
V+ toVo .....••..•...•...•••...••••.......... 33 V
Vo to V- .•.....•......••..•••...••••.•...•.... 33 V
Storage Temperature .................... -65 to 150°C
VotoVs •..••.•.•.•...•...••....•............ ±22V
Operating Temperature (A Suffix) ........ -55 to 125°C
(8 Suffix) ......... -25 to 85°C
VL to V- •.•••••.•••..•...••....•.............. 36 V
Power Dissipation'
VL tOVIN .••••••••..•..••••.........•.•.•..•... 8
V L toVR .••.................•.................. 8
VIN toVR ...................................... 8
VR to V- ...••....•............................ 27
V
V
Metal Can"
V
V
Flat Pack···· .............................. 900 mW
14-Pln DIP'"
................................ 450 mW
.............................. 825 mW
Alllea::!s welded or soldered to PC board.
Derate 6 mW/oC above 75°C.
Derate 11 mW/oC above 75°C.
•••• Derate 10 mW/OC above 75°C.
V R toVIN ..................................•.. 2 V
Current (S or D) DG186 .................•.... 200 mA
Current (S or D) DG187. DG188 ..............•. 30 mA
SCHEMATIC DIAGRAM (Typical Channel)
V+
S
IN
D
R
5-75
DG186/187/188
. . . . Siliconix
incorporated
~
DG186
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
V L = 5V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55, -25 ° C -55 to 125°C -25 to 85°C
TEMP TYpd MINb MAX' MINb MAXi
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
1,2,3
VANALOG
Vo= -7.5 V
Is=-10mA
rOS(ON)
10(OFF)
Channel ON
Leakage Current
10(ON)+
I SION)
15
V
.0.
10
20
15
25
1
2
0.05
10
1000
15
300
1
2
0.05
10
1000
15
300
1
2
0.04
V+ = 10 V, V- = -20 V
10
1000
15
300
Vs= -7.5 V
Vo=7.5V
1
2
0.03
10
1000
15
300
Vo=Vs=-7.5V
1
2
-0.1
Vs=7.5V
V o =-7.5V
VIN = 0.6 V
or 2.0 ve Vs= -10 V, Vo= 10 V
Drain OFF
Leakage Current
-7.5
7.5
V+ = 10 V, V- = -20 V
IS(OFF)
15
1,3
2
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
-7.5
-2
-200
-10
-200
loss
2 ms Pulse Duration
1
300
Input Current with
Input Voltage HIGH
IINH
VIN=5V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-30
1
240
300
350
1
140
250
300
Vs= -5 V, 10 = 0
1
21
V o =-5V,l s =0
·1
17
Vo=Vs=OV
1
17
1
>55
Saturation Drain Current
nA
mA
INPUT
10
20
10
20
jJ.A
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CSIOFF)
Drain-OFF Capacitance
COIOFF)
Channel ON Capacitance
COlON) +
C SION )
OFF Isolation
5-76
f = 1 MHz
f = 1 MHz, RL = 75.0.
ns
pF
dB
H
DG186/187/188
Siliconix
incorporated
DG186
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
MINb MAX'
MIN' MAX
TEMP TYpd
UNIT
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
0.8
1
-3
-3
1
0.8
mA
VIN = 0 V or 5 V
Logic Supply Current
IL
1
Reference Supply Current
IR
1
3.2
3.2
-2
-2
ELECTRICAL CHARACTERISTICS a
DG187
Test Conditions
Unless Otherwise Specified.
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5V
V R = OV
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
MINb MAX'
MINb MAXb UNIT
-7.5
-7.5
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
1,2,3
VANALOG
Vo= -7.5 V
rOS(ON)
IS(OFF)
VIN = 0.8 V
or 2.0 ve
Drain OFF
Leakage Current
Channel ON
Leakage Current
IO(OFF)
IO(ON)+
IS(ON)
15
V
n
1,3
2
22
30
60
50
75
1
2
0.06
V+ = 10 V, V- = -20 V
1
100
5
100
Vs= 7.5 V
V o =-7.5V
1
2
0.13
1
100
5
100
Vs= -10 V, Vo= 10 V
1
2
0.04
V+ = 10 V, V- = -20 V
1
100
5
100
V s =-7.5V
V o =7.5V
1
2
0.03
1
100
5
100
Vo=Vs=-7.5V
1
2
-0.02
Is=-10mA
Vs= 10 V, VO= -10 V
Source OFF
Leakage Current
15
-2
-200
nA
-10
-200
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 5 V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-30
10
20
10
20
.llA
-250
-250
5-77
.-yo Siliconix
DG186/187/188
~
incorporated
DG187
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt
UNIT
DYNAMIC
Turn-ON Time
1
65
150
160
1
95
130
150
V s =-5V,l o =0
1
9
Vo=-5V,ls=0
1
6
Vo=Vs=OV
1
14
1
>50
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
COlON) +
CS(ON)
f = 1 MHz
f = 1 MHz, RL = 75.n.
OFF Isolation
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1
0.8
1
-3
0.8
-3
rnA
VIN All = 0 V or 5 V
Logic Supply Current
IL
1
Reference Supply Current
IR
1
3.2
-2
3.2
-2
ELECTRICAL CHARACTERISTICS a
DG188
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL= 5 V
VR= 0 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXt UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
5-78
Vo= -10 V, VIN = 2.0 or 0.8 VB
rOS(ON)
-10
1,2,3
VANALOG
I s =-10mA
1,3
2
35
15
75
150
-10
15
V
100
150
!l.
H
DG186/187/188
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
DG188
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V-=-15V
V L = 5V
V R = OV
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXb UNIT
SWITCH (Cant'd)
1
2
0.05
V+ = 10 V, V- = -20 V
1
100
5
100
Vs=10V
Vo = -10 V
1
2
0.07
1
100
5
100
1
2
0.04
1
100
5
100
Vs= -10 V
Vo = 10 V
1
2
0.05
1
100
5
100
Vo=Vs= -10 V
1
2
-0.03
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
IS(OFP)
Drain OFF
Leakage Current
lo(oFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
V IN = 0.8 V Vs= -10 V, Vo= 10 V
or 2.0 V· V+ = 10 V, V- = -20 V
-2
-200
nA
-10
-200
INPUT
Input Current with
Input Voltage HIGH
IINH
V IN =5V
1
2
<0.01
10
20
IINL
V IN = 0 V
1,2,3
-30
1
120
250
300
1
100
130
150
V s =-5V,l o =0
1
9
V o =-5V,l s =0
1
6
1
14
1
>50
10
20
.ll.A
Input Current with
Input Voltage LOW
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
C S(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
C O(ON) +
CS(ON)
OFF Isolation
f = 1 MHz
Vo=Vs= 0 V
f = 1 MHz, RL = 75!l.
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
0.8
1
1
-3
0.8
-3
mA
V IN = 0 V or 5 V
Logic Supply Current
IL
1
Reference Supply Current
IR
1
3.2
-2
3.2
-2
5-79
DG186/187/188
..,.. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
DIE TOPOGRAPHY (DRIVER)
Interchlp Pad Connections
1.......- - -
A
B
C
D
E
F
G
H
80 mils - - -.....
~
D
Not Connected
From JFET 2, Source
Not Connected
Not Connected
To JFET 2, Gate
Not Connected
To JFET 1, Gate
From JFET 1, Source
44 mils
E~~~:+
20X
Pad
No.
Function
5
6
7
8
9
10
Input 1
V+
VL
V
N~ Connected
V - (Substrate)
CMJC
4
4
6
4
Capacitors
Resistors
P-channel enhancement MOSFET
N-channel depletion JFET
5 PN P Bipolar Transistors
4 NPN Bipolar Transistors
" Diodes
TYPICAL CHARACTERSITICS
Supply Current vs. Temperature
liN vs. "iN and Temperature
5
100
"i~L =
"iH=5V
0'
4
3
~
80
.....;;: ....... I-...
-
r---. t-..... r-- ~-
60
..... r-.......
........ ~
",1-
2
.....
o
I
-55 -35 -15
5 25 45 65 85 105 125
T - TEMPERATURE' (OC)
5-80
"""" r-.....
40
-IR
1+
........."'"
20
o
r-...:IINL
IINH
-55 -35 -15 5
25 45 65 85
T - TEMPERATURE (OC)
105 125
DG186/187/188
...... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
10.n DG186
Switching Time VS. Vo and Temperature
10.n DG186
rOS(on) VS. Temperature
230
100
\b- VA (MAX).
I
-
(.0. )
10
210
--
rOS(ON)
-
/tON
I.,
P'"
Vo = 7.5 V '-;;; VVo =-7.((- I tON, 170
tOFF
(ns) 150
130
110
.Y"
....-,V~=~
./
./
- -
I/"
..... ~
-:':'I'
,,
~i"'"
,,
--
tOFF--::
V~=7.5VI
:;,.--
1
1
90
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
10.n DG186
Leakage VS. Temperature
30.n DG187
rOS(on) VS. Temperature
100
1000
V+ = 10 V
V- -20 V
~ =5V
R=O
Vs = VA (MAX).
10= 1 mA '
V
10
10, Is
(nA)
Is OFF
V
rOS(ON) 100
1/
V
(.0. )
L
.,.
..-I
J
./""'" V'..-I
0.1
25
V'
10(OFF)- I -
T
'I
45
65
85
105
T - TEMPERATURE (OC)
125
"..
10
-55
30.n DG187
Switching Time VS. Vo and Temperature
130
........-
......
--
-15
25
65
T - TEMPERATURE (OC)
1000
./
100
Vo =7.5V . . /
l..A"
90
/'
~
"::7
60
1/
~ i"-"
105
=
V+ = 10 V, V- = -20 V
TEST LIMITS
• B SUFFIX - VL =5V,VR =0
• A SUFFIX
Vo = -10 V, Vs = 10 V
100
-1--...J
I
IN1
LOGIC
SW1
SW2
SW3
SW4
0
1
OFF
ON
ON
OFF
82~02
84 0
~~04
Logic "0· < 0.8 V
Logic "1" ~ 2.0 V
I
o---O-t>-...J
I
IN2
• Switches Shown for Logic " 1" Input
Two SPDT Switches per Package'
ABSOLUTE MAXIMUM RATINGS
Current (S or D) DG190, DG191 ............... 30 mA
V+ to V- ..................................... 36 V
V+ toVo ........•............................ 33 V
Vo to V- ...................................... 33 V
VotoV8 ..................................... ±22 V
V L to V- ...................................•.. 36 V
V L toVIN ...................................... 8 V
V L toVR .................................•..... 8 V
VIN toVR ....................................•. 8 V
VR to V- ...................................... 27 V
V R toVIN ..................................... 2 V
Current (S or D) DG189 ...................... 200 mA
Current (All Other Pins) .................•..... 30 mA
Storage Temperature ., .................. -65 to 150°C
Operating Temperature (A Suffix) ........ -55 to 125°C
(8 Suffix) ......... -25 to 8SoC
Power Dissipation'
16-Pln DIP"
................................ 900 mW
14-Pln Flat Pack'"
......................... 900 mW
All leads welded or soldered to PC board.
Derate 12 mW/oC above 75°C.
Derate 10 mW/OC above 75°C.
SCHEMATIC DIAGRAM (Typical Channel)
V+
S
D
R
5-86
DG189/190/191
trY' Siliconix
~
incorporated
DG189
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
B
SUFFIX
-25 to 85°C
MINb MAX' MINb MAXt
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
Vo= -7.5 V
rOS(ON)
Is(oFF)
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
Saturation Drain Current
15
-7.5
15
V
.n
1,3
2
7.5
10
20
15
25
1
2
0.05
V+ = 10 V, V- = -20 V
10
1000
15
300
V s =7.5V
V o =-7.5V
1
2
0.05
10
1000
15
300
1
2
0.04
10
1000
15
300
V s =-7.5V
V o =7.5V
1
2
0.03
10
1000
15
300
Vo=Vs= - 7.5 V
1
2
-0.1
Is=-10mA
Vs= 10 V, Vo= -10 V
Source OFF
Leakage Current
-7.5
1,2,3
VANALOG
VIN = O.B V Vs= -10 V, Vo= 10 V
or 2.0 Va V+ = 10 V, V- = -20 V
loss
2 ms Pulse Duration
1
300
IINH
V IN =5V
1
2
<0.01
-2
-200
nA
-10
-200
rnA
INPUT
Input Current with
Input Voltage HIGH
10
20
10
20
J.lA
Input Current with
Input Voltage LOW
1,2,3
-30
1
240
300
350
1
140
250
300
Vs=-5V,lo=0
1
21
V o =-5V,l s =0
1
17
1
17
1
>55
VIN=OV
IINL
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
OFF Isolation
COlON) +
CS(ON)
f = 1 MHz
Vo=Vs= 0 V
f = 1 MHz, R L = 75.n
ns
pF
dB
5-87
DG189/190/191
...... Siliconix
incorporated
~
DG189
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
B
A
2=125,85°C
SUFFIX
SUFFIX
3=-55,-25°C -55 to 125°C -25 to 85°C
TEMP TYpd MINb MAY: MINb MAXi: UNIT
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1
0.6
1
-2.7
3.1
-1
1.5
-5
1.5
-5
mA
VIN (All) = 0 V or 5 V
Logic Supply Current
IL
1
Reference Supply Current
IR
1
4.5
-2
4.5
-2
DG19D
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
LIMITS
1=25°C
B
A
2=125,85°C
SUFFIX
SUFFIX
3=-55, -25 ° C -55 to 125°C -25 to 85°C
TEMP TYpd MIN b MAY: MINb MAX
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
Source OFF
Leakage Current
1,2,3
VANALOG
rOS(ON)
IS(OFF)
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON)+,
IS(ON)
-7.5
15
-7.5
15
V
.n
Vo= -7.5 V
Is=-10mA
1,3
2
1B
30
60
50
75
Vs= 10 V, Vo= -10 V
1
2
0.06
V+ = 10 V, V- = -20 V
1
100
5
100
V s =7.5V
Vo=-7.5V
1
2
0.1
1
100
5
100
1
2
0.05
1
100
5
100
Vs =-7.5V
Vo = 7.5 V
1
2
0.06
1
100
5
100
Vo=Vs= - 7.5 V
1
2
-0.02
VIN = O.B V Vs= -10 V, Vo= 10 V
or 2.0 va V+ = 10 V, V- = -20 V
-2
-200
nA
-10
-200
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 5 V
1
2
<0.01
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-30
10
20
10
20
.lJ.A
5-88
-250
-250
DG189/190/191
tr"F Siliconix
~
incorporated
DG190
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL = 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
MINb MAX'
MIN' MAX
TEMP TYpd
UNIT
DYNAMIC
Turn-ON Time
1
85
150
180
1
95
130
150
V S = -5 V, 10 = 0
1
9
V o =-5V,l s =0
1
6
1
14
1
>50
1
0.6
1
-2.7
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacltarce
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
f = 1 MHz
COlON) +
CS(ON)
Vo=Vs=OV
f = 1 MHz, RL = 75.0.
OFF Isolation
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1.5
-5
1.5
-5
mA
VIN (All) = 0 V or 5 V
Logic Supply Current
IL
1
3.1
Reference Supply Current
IR
1
-1
4.5
-2
4.5
-2
ELECTRICAL CHARACTERISTICS a
DG191
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
VR = 0 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-25°C -55 to 125°C
TEMP TYpd
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXb UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
Vo = -10 V, VIN = 2.0 or 0.6 V e
rDS(ON)
-10
1,2,3
VANALOG
Is=-10mA
1,3
2
35
15
75
150
-10
15
V
100
150
.0.
5-89
III
DG189/190/191
...... Siliconix
incorporated
~
DG191
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 15 V
V- = -15 V
VL= 5 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3--55,-25°C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MIN b MA>f MINbMAX I UNIT
SWITCH (Cont'd)
Vs= 10 V, VO= -10 V
Source OFF
Leakage Current
1
2
0.05
V+ = 10 V, V- = -20 V
1
100
5
100
Vs= 10 V
Vo = -10 V
1
2
0.07
1
100
5
100
1
2
0.04
1
100
5
100
1
2
0.05
1
100
5
100
1
2
-0.03
IS(OFF)
VIN = O.B V Vs= -10 V, VO= 10 V
or 2.0 va V+=10V,V-=-20V
Drain OFF
Leakage Current
I o (OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
Vs= -10 V
Vo = 10 V
Vo=Vs= -10 V
-2
-200
nA
-10
-200
INPUT
10
20
Input Current with
Input Voltage HIGH
IINH
V IN=5V
1
2
<0.01
10
20
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1,2,3
-35
1
120
250
300
1
100
130
150
V s =-5V,l o =0
1
9
V o =-5V,ls=0
1
6
1
14
1
>50
1
0.6
1
-2.7
3.1
-1
.l1A
-250
-250
DYNAMIC
Turn-ON Time
tON
See Switching
Time Test Circuit
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
CO(ON) +
CS(ON)
f = 1 MHz
Vo=Vs= 0 V
f = 1 MHz, RL = 75.0.
OFF Isolation
ns
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1.5
-5
1.5
-5
mA
VIN (All) = 0 V or 5 V
Logic Supply Current
IL
1
Reference Supply Current
IR
1
5-90
4.5
-2
4.5
-2
DG189/190/191
. . . . Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
DIE TOPOGRAPHY (DRIVER)
tnterchlp Pad Connections
With 2 JFET's
D
13
A
B
C
0
E
F
G
H
t
With 4 JFET' s
44 mils
E~~~:J
A
B
C
0
E
F
G
H
20X
Pad
No.
10
11
12
13
14
15
CMJB
8 Capacitors
7 Resistors
12 P-channel enhancement MOSFET
4 N-channel depletion JFET
No Connection
No connection
To JFET 2, Gate
From JFET 2, Source
From JFET 1. Source
To JFET 1, Gate
No Connection
No Connection
10 PNP Bipolar Transistors
4 NPN Bipolar Transistors
4 Diodes
From JFET 1, Source
To JFET 1. Gate
To JFET 3. Gate
From JFET 3, Source
From JFET 4, Gate
To JFET 4, Gate
To JFET 2, Gate
From JFET 2, Source
Function
Input 2
V+
VL
VR
V- (Substrate)
Input 1
II
TYPICAL CHARACTERSITICS
Supply Current vs. Temperature
5
4
3
liN vs. YiN and Temperature
100
~
-
-~ t--
T
80
-..
..........
-.. ~"-
r--.......
60
.......... 1-0...
......... r-.....,-I-
2
~IINL
.........
40
r-.......
f"'"
-IR
1+
o
Y
YiNL = 0
"i~H =5V
I
-55 -35 -15
5 25 45 65 85 105 125
T - TEMPERATURE (DC)
"
20
o
IINH
-55 -35 -15 5
25 45 65 85
T - TEMPERATURE (DC)
105 125
5-91
DG189/190/191
...... Siliconix
,,1;;11 incorporated
TYPICAL CHARACTERSITICS (Cont'd)
10 .n OG189
Switching Time vs. Vo and Temperature
10.n OG189
rOS(on) VS. Temperature
230
100
V 0- -VA(MAX).
10 mA
I
-
.,
I
"
210
/'tON
./
190
rOS(ON)
(.0.)
---
10
tON, 170
tOFF
(ns) 150
130
110
-50 -25
0 25
50 75 100 125
T - TEMPERATURE (OC)
Vo = 7.5 V ':;;;; /Vo=-7.~- f-I _ ~
./
.Y"
./
~
./
~
~
-
I
30.n OG190
rOS(on) vs. Temperature
/
Is OFF /
1010N) + ISION)
.L
25
rOS(ON) 100
(.0.)
VV "
B SUFFIX
...
",
10(,FF)I....... .......
45
65
85
105
T - TEMPERATURE (OC)
/
0.1
/
125
130
10
-55
....- ~
A jUFilX
-15
25
65
T - TEMPERATURE (OC)
105
30.n OG190
10(OFF) vs. Temperature
1000
TEST LIMITS :: V+ = 10 V, V- = -20 V
120
• B SUFFIX - VL =5V,VR=0
..., ./"
110
Vo=7.5V./~
100
.A
90
80
i::::I"""
--
IL
~~ ~V~V
tOFF I...l.,.
• A SUFFIX -
Vo = -10 V, Vs = 10 V
100
-<./
Vo = -7.5 V
10
(nA) 10
~
B SUFFIX
.......I-'""'"I Vo = 7.5 V
i"""""
"A.....SUFFIX'~
~
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
5-92
~i""
~
30 .n OG190
Switching Time vs. Vo and Temperature
60
I
90
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
Vs - VA (MAX).
10= 1 mA
10, Is
(nA)
70
t=~
1000
V+ = 10 V
V- - -20 V
~ =5V
R=O
10
tON,
tOFF
(ns)
-I
VI-~
...... ~=7~5VI
-",'
~
10 .n OG189
Leakage vs. Temperature
100
I., ~
0.1
25
45
65
85
105
T - TEMPERATURE (OC)
125
tI'Y'
~
DG189/190/191
Siliconix
Incorporated
TYPICAL CHARACTERSITICS (Cont'd)
n DG191
n
75
Switching Time VS.
75
OG191
rOS(on) VS. Temperature
1000
Vs
10 -
Yo
and Temperature
130
10 V
lamA
120
..-'
110
"
Vo =7 j 5V",..-' ~..-'
A"
Vo = -7.5 V
100
tON,
tOFF
(ns)
B SUFFIX
rOS(ON) 100
(.0. )
A SUFFIX -
-
90
.- ~N~ ~V~
...t,.
L--r"
80
......
~
70
I?"
60
-15
25
65
T - TEMPERATURE (OC)
Capacitance vs.Vo orVs (10.0. FET)
TEST LIMITS ::: V+ - 10 V, V- - -20 V
• B SUFFIX - VL = 5 V,VR = 0
.A SUFFIX - Vo = -10 V, Vs = 10 V
26
100
~
~
22
Cs,C o
(pF)
10 10
(nA)
r-
...... i"o...
-
18
B SUFFIX
_i""""'"
..",.,.
ASUFFIX~
14
0.1
10
25
45
65
85
105
T - TEMPERATURE (OC)
-8
125
18
,I 1
1
I
'"
4
80
-10
-8 -6
o
-4
a
2
4
6
8
I".....
i'
......
CO(OFF)-
-4 -2
4
V+ = 15 V
V- = -15 V
VR = 0
VL = 5 V
R L =75.o.
VIN i!: 220 mV RMS
40
CAPACITANCE IS MEASURED F~OMI_
TEST TERMINAL TO COMMON
2
C?(0'j)
........
ISO.
(dB)
CS(OFF)
........ .........
......
'OFF" Isolation VS. Frequency (10.0. FET)
60
.......
r--
Co (ON) + CS(ON)
100
VINL = 0.8 V
V INH =2V
f = 1 MHz
16 -CO(ON) + CS(ON)
14
qOFF(_
VINL = 0.8 V
VINH = 2 V
f
= 1 MHz
Vo orVs - DRAIN or SOURCE VOLTAGE (V)
Capacitance VS. Vo orVs (30-75.0. FET)
20
o
I
30
1000
6
I
50
-55 -35 -15 5 25 45 65 85 105 125
T - TEMPERATURE (OC)
105
75 n DG191
10(OFF) VS. Temperature
8
--:-VOi7.5IV
I
10
-55
12
Cs,C o
10
(pF)
-
tOFF
./
8
10
Vo orVs - DRAIN or SOURCE' VOLTAGE (V)
i'
20
o
10'
10.
107
10·
f - FREQUENCY (Hz)
5-93
DG189/190/191
WY'Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
Typical delay, rise, fall, settling times,
and switching transients In this circuit.
'OFF' Isolation vs. Frequency (30-75.0. FET)
100
90
......
BO
"
70
60
f'..
ISO. 50
(dB)
V+ = 15 V
V- = -15 V
VR = 0
VLOGI9 = +5 V
RL = 5.0.
VIN ~ 220 mV RMS
40
30
20
10
o
10'
6
VIN
(V)
4
"f , "" 10.
"' "
f - FREQUENCY (Hz)
If R gen' RL, or C L Is Increased, there
will be proportional Increases In rise
and/or fall times.
OG1B9
OG190, OG191
107
2
10
(V)
5
o
10·
LbGI6
I
I
Vo
(V)
Vo
(V)
Vo
(V)
I
J
2
0
-2
r
Vo
(V)
Vo
(V)
"
Vgen
,
=5 V
=0
2
0
-2
I
2
0
-2
.A
\
-2
-4
~I
I
Vr
5
0
-5
-10
\
i
Vo
(V)
-5,
Vo
(V)
Jll't""
/
0.4
O.B
t - .TIME (j1S)
Vgen
i
1.2
6
4
2
o
Vo
(V)
Vgen
10
5
I.l
I
"
= 10 V
I
I
1.6
I
Vgen
= 10 V
Vgen
=5 V
1\
\,
J
A
.
\
-.-:"
Vgen
=0
I
A
I
I
-4
-6
I
I
I
o
I
I
.A"" I
Vrn
5
0
-5
-10
I
!\
I
J
= 10 V
1\
\
o
5-94
I
~
-6
Vo
(V)
I
L6GICI INP0T-
2
o
.....
o
2
0
IN~UT
i\..
1
Vgen
6
4
2
6
I4
I-
o
Vo
"
I
=1- 5
'1
i..,..oo"
./
0.4
= 10 V
Y J I
Vgen
O.B
t - TIME (liS)
1.2
1.6
-
DG189/190/191
..... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
=
Switch output waveform shown for Vs constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
5V
(LOGIC "1" = SWITCH ON)
t,<10ns
t,<10ns
LOGIC
INPUT 0 V
'----
15 V
tON:Vs=+3V S
8;r·n~~
t OFF: V S = -3 V 03+----<>""':"":L....+-c5...-o__---o-oV OUT
S~~~~~ s,
sm~2~ vS----t-!;==:j:~-- ±3v
o-I----f
MI~
MAXb UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Delta Drain-Source
ON Resistance
C
1,2,3
VANALOG
rOS(ON)
d
rOS(ON)
IO(ON)
+IS(ON)
15
115
175
250
175
250
V+ = 10.B V, V- = 10.B V
Is= 1 rnA, Vo =±7.5V
V IN = 0.4 V
V+ = 22 V, V- = -22 V
Is = 1 rnA, Vo = ± 15 V
1,3
2
145
250
325
250
325
1,3
2
B5
125
225
125
225
1,3
2
5
10
15
10
15
Vo - +5,0, -5 V, Is - ±1 rnA
VIN = O.B V
Worst Combination
V+ = 22 V
V- = -22 V
= -15.5 V
= -15.5 V
1
2
0.015 -0.25
-20
0.25
20
-0.25
-2
0.25
2
= +15.5 V
= +15.5 V
1
2
0.015 -0.25
-20
0.25
20
-0.25
-2
0.25
2
Vo = -21 V
V s =-21V
1
2
0.15
-2
-200
2
200
-2
-20
2
20
Vo = +21 V
VS=+21 V
1
2
0.15
-2
-200
2
200
-2
-200
2
200
Vo = -5 V
Vs = -5 V
2
-10,
10
-2
2
Vo = +5 V
Vs = +5 V
2
-10
10
-2
2
V+ = 13.5 V
V- = -13.5 V Vo = +12.5 V
Vs = -12.5 V
Vo = -15.5 V
Vs = +15.5 V
V+ = 16.5 V
V- = -16.5 V Vo = +15.5 V
Vs = -15.5 V
Is (OFF)
Vo = -21 V
V+ = 22 V
V- = -22 V
VIN =3V
5-104
-15
1,3
2
Vo = -12.5 V
Vs = +12.5 V
Source OFF
Leakage Current
15
V+ = 13.5 V, V- = -13.5 V
Is= 1 rnA, Vo=±10.0V
Vo
Vs
V+ = 16.5 V
V- = -16.5 V Vo
Vs
Channel ON
Leakage Current
-15
1
2
-0.01
1
2
-0.01
1
2
0.015
1
2
-0.015 -0.25
-10
1
2
0.15
Vs=+21 V
Vo = +21 V
Vs=-21V
1
2
-0.15
Vo = -5 V
Vs = +5 V
2
Vo = +5 V
Vs = -5 V
2
0.25
1
0.25
10
-0.25
-10
-0.25
-1
0.25
1
0.25
10
-0.25
-1
1
10
1
100
-1
-100
-1
-10
1
5
-5
-1
V
.n
nA
H
DGP201A
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VIN = 2.4 V, O.B Va
LIMITS
1=25·C
D
A
2=125,85·C
SUFFIX
SUFFIX
3=-55,-40·C -55 to 125°C -40 to 85°C
b
b
TEMP TYpd MIN MA~ MIN MAXb UNIT
SWITCH (Cont'd)
Vo = -12.5 V
Vs = +12.5 V
0.01
1
2
-0.01
Vo = -15.5 V
Vs = +15.5 V
1
2
0.015
Vs = -15.5 V
1
2
-0.015 -0.25
-10
V+ = 16.5 V
V- = -16.5 V Vo = +15.5 V
Drain OFF
Leakage Current
IO(OFF)
Vo = -21 V
V+ = 22 V
V- = -22 V
VIN = 3 V
0.25
10
1
2
V+ = 13.5 V
V- = -13.5 V Vo = +12.5 V
Vs = -12.5 V
Vs=+21 V
Vo = +21 V
Vs=-21V
-0.25
-10
0.25
1
-0.25
-1
0.25
10
0.25
1
-0.25
-1
nA
1
2
0.15
1
2
-0.15
1
100
-1
-100
1
10
-1
-10
Vo = -5 V
Vs = +5 V
5
2
1
Vo = +5 V
Vs = -5 V
-5
2
-1
INPUT
Input current with VIN
HIGH
Input current with VIN
LOW
IIH
IlL
v+ = 22 V, v- = -22 V
VIN under test = 2.4 V
1
2
-0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
V+ = 22 V, V- = -22 V
VIN under test = 22 V
1
2
-0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
V+ = 22 V, V- = -22 V
VIN under test = 0 V
1
2
0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
1
2,3
450
1
2,3
JlA
DYNAMIC
Turn-ON Time
tON
See Switching Time
Test Circuits
600
600
BOO
BOO
320
450
600
450
600
Turn-OFF Time
tOFF
Delta tON
/:;.
tON
Worst Combination among
channels of the tON
measurements
1
2,3
30
50
100
50
100
Delta tOFF
/:;.
tOFF
Worst Combination among
channels of the t OFF
measurements
1
2,3
30
50
100
50
100
Vgan = 0 V
1
25
50
50
Vgen = ±10 V
1
33
100
100
1
4.5
ns
Charge Injection
Source OFF Capacitance d
Q
CS(OFF)
R gan = 0.0.
CL = 10 nF
pC
f = 1 MHz, V s = 0 V
pF
5-105
DGP201A
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
LIMITS
1=25·C
A
0
2=125,85·C
SUFFIX
SUFFIX
3=-55,-40·C -55 to 125°C -40 to 85°C
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VIN = 2.4 V, 0.8 V e
Co (OFF)
f=lMHz,Vs =OV
1
5.5
Co (ON)
+ CS(ON)
f=lMHz,Vs =OV
1
15
Crosstalk
(Channel-to-Channel)
RL= 50.0.
CL = 5 pF
f = 1 MHz
1
95
OFF Isolation
C L = 5 pF
RL = 50.0.
f = 1 MHz
1
80
PARAMETER
TEMP TYpd
I
MINb MA'If MINb MAXb UNIT
DYNAMIC (Cont'd)
Drain OFF Capacitance d
pF
Channel ON Capacltance d
dB
SUPPLY
Positive Supply
Current
1+
V 1N=00r5V
V±=±16.5 V
1
2
0.8
Negative Supply
Current
1-
V 1N =00r5V
V±=±16.5 V
1
2
0.26
1.5
2.5
1.5
2.5
-1
-2
mA
-1
-2
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebralo oonventlon whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
o. Guaranteed by design, not subJeot to production test.
d. Typloal values are for DESIGN AID ONLY, not guaranteed nor subJeot to produotlon testing.
e. VIN = Input voltage to perform proper funotlon.
DIE TOPOGRAPHY
.....1 - - - - 80 mils - - -.....~
l
4
13 72 mils
:~J
9
20X
ICMCB
8 Capaoltors
9 Resistors
5-106
49 P-ohannel enhancement MOSFET
45 N-ohannel enhanoement MOSFET
Pad
No.
Function
1
2
3
Input 1
Drain 1
Source 1
4
5
6
7
8
9
10
11
13
14
15
16
V-
GND
Souroe 4
Drain 4
Input 4
Input 3
Drain 3
Souroe 3
V+ (Substrata)
Souroe 2
Drain 2
Input 2
Ir7'
~
DGP201A
Siliconix
incorporated
TYPICAL CHARACTERSITICS
rDS(ON) vs,VD and
Power Supply Voltage
Charge Injection vs.
Analog Voltage (Vs )
500
40
~
35
A: ct. = 10k pF
B: 0L = lk pF
0: q:= 100 pF
30
20
.....
"-
/
A
~V
. /V
25
Q
(pC)
II
V .....
~
A: v+=
B : v+=
o : V+ =
400 I-- D : V+ =
V+ =
350 r-- F : V+ =
450
.-.--
r--
E:
300
10
5
I
0
-15
-s
-10
0
v+ = +15 V
v- = -15 V
o
5
10
50
-25
15
ct.
10k pF
B: 0L= lkpF
30
15
V
10
1/
220
I--
A 125 :0
B 85.0 HV+=+15V
L.-
200
I--
VB
~ ~g:g
180
5
o
120
./
100
V
80
V
5
7
9
11
13 15 17
19 21
V- = -15 V
~.g
~
A
"-,
C/' ..~
r-"./
/ - l'..~ ~
~ ~ "-
r-=
F
60
-15
23 25
g
/"
160
rDS(ON)
140
(n)
'/"
V
25
rDS(ON) vs. V D and
Temperature
1/ 1/
20
15
5
240
I}V
1/
25
Q
(pC)
I
F
VD (VOLTS)
40
A:
TA =1 25 • 0
~....:;JE
-s
-15
Charge Injection vs.
Power Supply Voltage
]
=
=
=
=
I
~~_oJ_
100
Vs(VOLTS)
35
VVVV-
,u..
150
l-
V,
V,
V,
V,
II
"-
200
.-'
v-=
8 VI
rDS(ON)
250
(n)
15
-5 V
-8V I--10 V
-12 V I--15 V
-20 V I--
5 V, v- =
10
12
15
20
-10
-----
,...E
o
-5
POSITIVE/NEGATIVE SUPPLIES
(VOLTS)
EI
I--""
10
5
15
VD (VOLTS)
Charge Injection vs.
Power Supply Voltage
( one supply held constant )
25
Q
(pC)
,
'\
20
15
V
\
80
60
-""
V+ +15 V
v - -15 V
--
1
40
liN
(pA)
0
-20
-40
-SO
5
,/
V
V
V
-80
o
-25
j
20
/
'\
10
100
I V- = -15 v l
I V+= +15 V I
30
-100
-15
-S
5
15
POSITIVE/NEGATIVE SUPPLIES
(VOLTS)
25
o
2
4
6
8
10
12
14
16
V IN (VOLTS)
5-107
DGP201A
...... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS
Supply Current VB. Supply Voltage
( one supply held constant )
Capacitance vs.
Analog Voltage
20
2000
1700
"1
V+ =+15 V
V- =-15 V
1400
(rnA)
C
(pF)
1+
1+
500
./
200
-100
-400
-700
-1000
-15
-25
I
10
I
Co (OFF)
6
'"'"
15
5
4
CS(OFF)
2
o
-15
25
-10
Supply Current VB. VIN
15
Capacitance VS. Temperature
20
18
3
I
C
(pF)
0
i\
V+=+15V
V- =-15 V
1=1 MHz
L
14
1+
~
I-
12
t---c- r- CS(ON) +
Co (ON)
10
8
~
-2
~
16
I
2
-1
10
Vo (VOLTS)
4
(rnA)
o
-5
POSITIVE/NEGATIVE SUPPLIES
(VOLTS)
1-,1+
I
12 r---,CS(ON) + COlON)
8
I- .....
l-
V+=+15V
V-=-15 V
1=1 MHz
14
/
800
~
16
/
1100
1-, 1+
18
t'
Co (OFF)
6
4
-<3
r-:- t- Ct(Oj)
2
o
2
4
6
8
10
12
14
16
0
-55 -- _.J
FREQUENCY
TESTED
IN 2
r-'f MIN MAXb UNIT
SUPPLY
Positive Supply Current
1+
1
0.9
1
-0.3
2
2
All Channels ON or OFF
Negative Supply Current
1-
mA
-1
-1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a'maxlmum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Signals onSx, Ox' or IN x exceeding V+ or V- will be clamped by Internal diodes. Umlt forward
diode current to maximum current ratings.
f. ID(ON) Is leakage from driver Into "ON" switch.
DIE TOPOGRAPHY
DG201A
- . - - - 80 m l l s - - - "
4
-r
72 mils
:~J
20X
ICMCB
8 Capacitors
9 Resistors
5-120
49 P-channel enhancement MOSFETs
45 N-channel enhancement MOSFETs
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
Function
Input 1
Drain 1
Source 1
VGND
Source 4
Drain 4
Input 4
Input 3
Drain 3
Source 3
V+ (Substrate)
Source 2
Drain 2
Input 2
IrY'
DG201A1202
Siliconix
,,1;;11 incorporated
DIE TOPOGRAPHY
DG202
1----'
v-o-------~-------+--------~------------------~
APPLICATION HiNTS·
V+
Positive
Supply
Voltage
(V)
VIN
Logic Input
Voltage
VINHMin/
VINLMax
(V)
Vs or Vo
Analog
Voltage
Range
(V)
15 ••
-15
2.4/0.8
-15 to 15
12
-12
2.4/0.8
-12t012
10
-10
-8
2.4/0.8
-10 to 10
-8 to 8
8 ***
...
VNegative
Supply
Voltage
(V)
Application Hints are for DESIGN AID ONLY,
not guaranteed nor subject to production
testing.
Electrical Characteristic chart based on
V+ = +15 V, V- = =15 V .
Operation below 8 V is not recommended.
5-126
DG201A
LOGIC
INPUT
SWITCH
STATE
0
ON
~0.8
1
OFF
~
LOGIC
VOLT LEVEL
V
2.4 V
DG202
LOGIC
INPUT
SWITCH
STATE
0
OFF
~0.8 V
1
ON
~
LOGIC
VOLT LEVEL
2.4 V
DG201A1202
...... Siliconix
incorporated
~
APPLICATIONS
7
160r---~--~----~--~----~---'
'C4
SELECT O---I-"="'-Ir<-!
10
'03
120~---+----+----1----~----~--4
SELECTo--~~~~~
TTL
CONTROL
15
'C2
SELECTo--~~~~~
80 I-----I----""kVoltage
'Cl
Gain - dB
SELECTo--~~~~~
o 1----f------"1Mc%=1 M
FREQUENCY - Hz
~~6~_ _ _ _ _~~-oVOUT
AL(VOLTAGE GAIN BELOW BREAK FREQUENCY)
8
= %= 100 (40 dB)
'e
~=10K
R,
(BREAK FREQUENCY) =----1.27r%Cx
'L (UNITY GAIN FREQUENCY) = _ _1_ _
27r R, Cx
MAX ATTENUATION =
'OS (on)
10 K
.. -40 dB
Active Low Pass Filter with Digitally Selected Break Frequency
III
15
16
t-____HlVOUT
TYPICAL PERFORMANCE
AQUISITION TIME
=25.11S
APERTURE TIME
=I.11S
=5mV
SAMPLE TO HOLD OFFSET
OROOPRATE
=5 mV/S
Sample and Hold
5-127
DG201A1202
..,. Siliconix
incorporated
~
APPLICATIONS
VOUT
+-_____-0"1 .......-;--+_"---'
VIN2 0-4
RF1
18 k.n.
14
15
11
10
6
7
RG1
2k.n.
GAIN 1 (X1) O----rlf-C==::-'t'-l
REF
GND'o--+-----'
~----~--~----------oODX
INXo----JVV\--~~~
V- o-------~----------
__~------~-------------------'
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
Logic
Input INl
tr
tf
+5
< 20ns
< 20ns
Switch
Input
Switch
Input
V
+15
V
Dl
Sl
Vo
Vs
lkn
0.9 Vo
Switch
OutputVo
Switch
Output
RL1CL
35 pF
0
OV
Vo
= Vs
-15
V
__
R_L_
RL + rDS(on)
(Repeat Test for IN2
and IN3 • and I~ )
5-139
DG211/212
Siliconix
incorporated
APPLICATIONS
1 V
2V
3V
4V
3
14
Vo
11
6
10 k.o.
-
4
Vo 3
VOLTS 2
1
IN2 _ _ _ _ _......
IN31 _________________
~
IN41______________________~
Figure 4. Four-Channel Analog Multiplexer
PRECISION ,RTTENUATOR
+5V
+5V
r
+15V
VIN
VIN (MAX) = +150 V
13
00 2
1
9 M.o.
2
3
03
DATA BUS
02
900 k.o.
01
DO
15
14
74175
QUAD
0
FF
PROCESSOR
SYSTEM BUS
R
90 k.o.
11
10
9 k.o.
CLK
7
6
OG211 or
OG212
1 k.o.
-15 V
Figure 5.
5-140
Microprocessor Controlled Analog Signal Attenuator
VOUT
""
DG211/212
...... Siliconix
incorporated
~
APPLICATIONS (Cont'd)
FET INPUT
OPAMP
VINo-------I
:>~----~~----------------oVOUT
GAIN ERROR IS DETERMINED ONLY BY
THE RESISTOR TOLERANCE. OP AMP
OFFSET AND CMRR WILL LIMIT ACCURACY
OF CIRCUIT.
+5V
3
2
GAIN 1 o---+-!-.......d
AV = 1
90 kn
14
15
5kn
GAIN2 o-_ _+,,16"1-d
AV = 10
VOUT
R1 + R2 + R3 + R4
VIN =
R4
= 100
11
WITH SW4 CLOSED
4kn
GAIN 3 o----I--I-d
Av =20
GAIN 4
6
o-_ _~8-1-d
AV = 100
1 kn
OG211 or OG212
-15 V
Figure 6.
..
Precision-Weighted Resistor Programmable-Gain Amplifier
V1
15
16
OG211
VOUT
Figure 7.
DG211 Sample-and-Hold
5-141
DG211/212
Siliconix
incorporated
APPLICATION HINTS*
DG211. DG212
V+
Positive
Supply
Voltage
VNegative
Supply
Voltage
VL
Logic
Supply
Voltage
VIN
Logic Input
Voltage
VINH Mini
VINL Max
Vs or VD
Analog
Voltage
Range
(V)
(V)
(V)
(V)
(V)
20
-20
5
2.4/0.8
-20 to 20
15
-15
5
2.4/0.8
-15 to 15
* Application Hints are for DESIGN AID ONLY. not
12
-12
5
2.4/0.8
-12 to 12
10
-10
5
2.4/0.8
-10 to 10
8**
-8
5
2.4/0.8
-8 to 8
10
-10
10
5/2
-10 to 10
guaranteed and not subject to production testing.
Operation below ±8 V Is not recommended.
r------------------~
INl
I
o--t---I+
+16 V
°i:EJ BELOW)
-15 V
TO
SCOPE
~~~~~6~~ -t~~~:.wr I
:
TO Sl
+15 V
100
k.n
I
I
I
J-2--~1 M!l.1
I
I
I
I
R
I
(SEE BELO~~)
I
I _
I
~------------------~
~~: ~ WO~PD~~~E~~~G~~[t.BLE BANDWIDTH, SLEW RATE,
6
100
k.n
R IS ADDED FOR EXTRA GAIN ACCORDING TO FORMULA
VOLTAGE GAIN = 2 + 1..QQIs.
R
Figure 8.
5-142
The 'Scope Extender" Which Displays 4-Channels Simultaneously On A Single Trace Scope
DG221
4-Channel Monolithic SPST
CMOS Analog Switch with Data Latches
...... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Accepts 230 ns Write
Pulse Width
• Compatible with Most
ILP Buses
• ILP Based Systems
• On Chip Regulator
411
• Built on PLUS-40 Process
• Latches Are Transparent
with WR Low
• Automatic Test Equipment
Allows Wide Power Supply
Tolerance Without Affecting
TTL Compatibility
• Communication Systems
• Data Acquisition Systems
• Reduced Power Supply
Considerations
• Allows Flexibility of Design
DESCRIPTION
The DG221 is a monolithic quad single-pole,
single-throw analog switch designed for precision
switching applications in communication, instrumentation and process control systems. Featuring
independent onboard latches and a common WR
pin, each DG221 can be memory mapped, and
addressed as a single data byte for simultaneous
switching.
Designed on the Siliconix PLUS-40 CMOS process
to combine low power dissipation and ON
resistance (60 .n typ.) while handling continuous
currents up to 20 mAo An epitaxial layer prevents
latchup.
PIN CONFIGURATION
This device features true bidirectional performance
in the ON condition, and will block signals to 30 V
peak-to-peak in the OFF condition. ON resistance is
extremely flat over the ±15 V analog signal range.
Packaging for this device includes 16-pin ceramic,
plastic, and small outline options. Performance
grades include military, A suffix (-55 to 125°C),
both industrial, Band D suffix (-25, -40 to 85°C),
and commercial, C suffix (0 to 70°C) temperature
ranges.
FUNCTIONAL BLOCK DIAGRAM & TRUTH TABLE
Dual-ln-L1ne Package
_~S'
IN,
~D,
_~S2
IN2
~D2
_~S3
Top View
Order Numbers:
CerDIP: DG221AK, DG221AK/883,
DG221BK, DG221CK
IN3
~D3
Plastic: DG221CJ
IN4
Q
SO Package
(Same pinout as DIPI
, 2 3 4 5 6 7 8
Order Number:
DG221DY
-
~S4
Truth Table
IN x
0
WR
0
1
0
OFF
1
Maintains
Previous
State
X
Logic "0"
Logic "1"
SWITCH
ON
~
~
0.8 V
2.4 V
iNA
Input Is level
sensitive (not
edge triggered)
~D4
WR 0 - - - - - '
Four Latchable SPST Switches Per Package'
Top View
• Switches Shown for Logic "1" Input
5-143
DG221
Siliconix
incorporated
ABSOLUTE MAXIMUM RATINGS
Operating Temperature (A
(8
(C
(0
Voltages referenced to VV+ ........................................... 44 V
GND ......................................... 25 V
Digital Inputs, WR, V s , Vof . .. (V-) -2 V to (V+) +2 V or
...................... , 20 mA, whichever occurs first
Power
16-Pin
16-Pin
16-Pln
Current, Any Terminal Except S or 0 ............ 30 mA
Suffix)
Suffix)
Suffix)
Suffix)
......... -55 to 125°C
.......... -25 to 85°C
............ 0 to 70°C
.......... -40 to 85°C
Dissipation (Package)·
CerDIP·· ............................ 900 mW
Plastic DIp··· ........................ 470 mW
SO···· .............................. 600 mW
Continuous Current, S or 0 .................... 20 mA
Device mounted with all leads soldered or
welded to PC board.
Derate 12 mW/oC above 75°C.
Derate 6.5 mW/oC above 75°C.
•••• Derate 7.7 mW/oC above 75°C.
Peak Current S or 0
(Pulsed at 1 ms, 10% duty cycle max) .......... 70 mA
Storage Temperature (A & 8 Suffix) ....... -65 to 150°C
(C & 0 Suffix) ...... -65 to 125°C
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = +15 V
V- = -15 V
GND =WR = 0 V
LIMITS
1_25°C
A
2=125,B5,70°C
SUFFIX
3=-55,-40,O°C -55 to 125°C
!TEMP
TYpd
MINb MAx"
B,C,D
SUFFIX
MINb MAXt UNIT
SUPPLY
Analog Signal Range
Drain-Source e
ON Resistance
Source OFF
Leakage Current
C
1,2,3
VANALOG
rOS(ON)
-15
15
-15
15
Vo = 10 V
1,3
2
60
90
135
90
135
Vo = -10 V
1,3
2
70
90
135
90
135
Vs= 14 V
Vo= -14 V
1
2
0.01
1
100
5
100
Vs= -14 V
Vo= 14 V
1
2
-0.02
Vs= -14 V
Vo= 14 V
1
2
0.01
Vs= 14 V
Vo= -14 V
1
2
-0.02
Vo=Vs = 14V
1
2
0.1
Vo=Vs=-14V
1
2
-0.15
-1
-200
-5
-200
VIN = 2.4 V
1
2
-0.0001
-1
-10
-1
-10
VIN = 15 V
1
2
0.003
VIN = 0 V
1
2
-0.0004
VIN = 0.8 V
Is = -1 mA
V
.0.
IS(OFF)
-1
-100
-5
-100
VIN = 2.4 V
Drain OFF
Leakage Current
Drain ON
Leakage Current
1
100
5
100
nA
IO(OFF)
IO(ON)
-1
-100
-5
-100
1
200
5
200
VIN = 0.8 V
INPUT
Input Current with
Input Voltage HIGH
Input Current with
Input Voltage LOW
5-144
IINH
IWRH
IINL
IWRL
1
10
-1
-10
1
10
-1
-10
J.LA
H
DG221
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = +15 V
V- = -15 V
GND = WR = 0 V
LIMITS
1=25·C
A
2=125,85,70·C
SUFFIX
3=-55,-40,0 ·C -55 to 125°C
TEMP
TYpd
B,C,D
SUFFIX
MIN b MAX' MINb MAXt UNIT
DYNAMIC
Turn-ON Time
Turn-OFF Time
tON
tOFF
See Switching
Time Test Circuit
Figure 1
1
550
550
1
340
340
1
550
550
1
340
340
ns
Turn-ON Time Write
Turn-OFF Time Write
Charge Injection
tON' WR
tOFF, WR
Q
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Channel ON Capacitance
CO(ON) +
CS(ON)
OFF Isolation
See Switching
Time Test Circuit
Figure 2
C L = 1000 pF, Vgen = 0 V
Rgen = O!l.
1
20
Vs= 0 V
VIN=5V
1
8
Vo = 0 V
VIN =5V
1
9
Vo=Vs= 0 V
VIN=OV
1
29
V IN =5V
1
70
Vs = 1 VP-P' f= 100 kHz
CL = 15 pF, RL = 1 k!l.
1
90
1
0.8
1
-0.4
f = 1 MHz
pC
pF
dB
Interchannel
Crosstalk Isolation
SUPPLY
Positive Supply Current
Negative Supply Current
1+
1-
All Channels ON or OFF
VIN = 0 V or 2.4 V
1.5
1.5
mA
-1
-1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. ArOS\ON) Is guaranteed to be within ±5% swltch-to-swltch within a package (not a tested parameter).
f. Signa on Sx, D x , WR, IN x exceeding V+ or V- will be clamped by Internal diodes. Limit forward diode current to
maximum current ratings.
5-145
DG221
..,. Siliconix
.6;11 incorporated
DIE TOPOGRAPHY
.....---@IIS----I...~I
l ' 16
Pad
No.
15
3
4
l
J
13
5
6
~------~~----~~
leMMA
8 Capacitors
11 Resistors
66 P-channel depletion MOSFETs
20X
83 mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
Input 1
Drain 1
Source 1
v-
GND
Source 4
Drain 4
Input 4
Input 3
Drain 3
Source 3
WR
V + (Substrate)
Source 2
Drain 2
Input 2
68 N-channel depletion MOSFETs
2 NPN Bipolar Transistors
FUNCTIONAL SCHEMATIC (Single Channel Shown)
v+
Sx
GND
INx
Ox
WR
V-
5-146
DG221
wy" Siliconix
~
incorporated
SWITCHING TIME TEST CIRCUIT
=
Switch output waveform shown for Vs
constant with logic input waveform as shown. Note that Vs may be +
or - as per switching time test circuit. Vo is the steady state output with switch ON. Feedthrough via gate
capacitance may result in spikes at leading and trailing edge of output waveform.
oV
LOGIC 3 V
INPUT 0 V
t r <10ns
tj<10ns
+15 V
SWITCH
SWITCH
INPUT S 1
OUTPUT
V S =+2 V 0-1-----0"': "'--1_0:-_-__-0 V OUT
sf~~~~ VS--t--~====~==~-SWITCH
OUTPUT 0 V ---1I--...J
VOUT = Vs
LOGIC ·0" = SWITCH ON
RL
R L+ rOS(ON)
(REPEAT TEST FOR
IN2 .IN3 AND IN4 )
Figure 1
WR SWITCHING TIME TEST CIRCUIT
LOGIC
INPUT
t r < 20 ns
tj < 20 ns
+15 V
V+
3V
WR
SWITCH
SWITCH
INPUT S 1
OUTPUT
V S =+2 V 0-1-----0" "'~-O:-....,..-~_oV OUT
OV
V OUT
CL:T
35 PF.-L
VS----I---~===t==~
OV---+---J
V OUT = V S
LOGIC "0· = SWITCH ON
RL
(REPEAT TEST FOR
R L+ rOS(ON) IN2.IN3 AND IN4 )
Figure 2
WR SETUP CONDITIONS
WR/INPUT MINIMUM TIMING REQUIREMENTS
PARAMETER
Write Pulse Width
MIN LIMIT
tww
230
Data Valid to Write
tow
180
Data Valid After Write
two
30
UNIT
ns
Figure 3
5-147
DG221
. . . Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
RGEN
~
Sx
Vo
V GEN .=.
1
T
"-
INX~
WR
-
-.1_
AVO = measured voltage error due to charge InJection.
The error voltage In coulombs Is AQ CL xA Vo.
=
-
OFF ISOLATION TEST CIRCUIT
+15 V
CHANA
ANALYZER
CHAN B 1 - - - - '
C = O.OOlJl.F 1I1Jl.F
CHIP CAPACITORS
5-148
OFF ISOLATION = 20 LOG
I~ ~ I
DG221
.... Siliconix
incorporated
~
CHANNEL TO CHANNEL CROSSTALK TEST CIRCUIT
+15 V
~
v D1
V S1
I
I
I
-=-
-
_...1
ov
r-
-=-
OV
I
I
I
CHANA
VS2
-=VC2
ANALYZER
NC
CHANBI---....I
-
~
-
C = O.001JLF" 1JLF
CHIP CAPACITORS
-15 V
CCRR = 20 LOGI
~I
APPLICATION HINTS
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
GND
(V)
(V)
Input
Logic
Voltage
(V)
-WR
Analog
Signal
Range
(V)
15
-15
0
0.8/2.4
0.8/2.4
±15
20
-20
0
0.8/2.4
0.8/2.4
± 20
10
-10
0
0.8/2.4
0.8/2.4
±10
10
-5
0
0.8/2.4
0.8/2.4
+10/-5
5-149
DG221
..... Siliconix
incorporated
~
APPLICATIONS
IN1
IN2
IN3
IN4
WR"
0
0
0
0
0
1
1
1
1
0
WR
IN1
IN2
IN3
IN4
All
0
0
1
1
1
0.1
None
0
1
0
1
1
0.01
ON Switch
Gain
0
1
1
1
0
1
0
1
1
0
1
0.001
1
0
1
1
0
2
0
1
1
1
0
0.0001
1
1
0
1
0
3
1
1
1
0
0
4
" WR may be held at '0" for temporary operation similar
to DG201A's. With WR at '0" SW1 will remain ON as
long as' IN 1" Is held at "0".
+15 V
V+
9M.n.
DG221
IN1
DATABUS
900 k.n.
>
90 k.n.
9 k.n.
1 k.n.
>--,--oVo
-15 V
Figure 4.
jJ.
P Controlled Analog Signal Attenuator
The TL081 Is used as unity gain buffer while DG221
selected voltage divider provides attenuation.
5-150
DG243
Monolithic General Purpose
CMOS Analog Switch
IrF' Siliconix
~
incorporated
FEATURES
II
PLUS-40 Process
II
Make-Before-Break
Operation
II
Full Rail-to-Rail Analog
Signal Range
II
True TIL Compatibility
BENEFITS
APPLICATIONS
o Reduced Power Supply
Considerations
o Programmable Gain
Amplifiers
o Reduced Switching Noise
o Analog Multiplexing
o Reduced Need for Buffers
til
Servo Control Systems
• Pull-Up Resistors Not
Required
DESCRIPTION
The DG243 is a monolithic dual SPDT analog switch
designed for general switching applications in
communication, instrumentation, and process
control systems. Featuring make-before-break
action, the DG243 can be used in closed loop
systems to switch gain or bandwidth networks
without opening the loop.
with a high breakdown voltage rating of 40 V. An
epitaxial layer prevents latchup.
Each switch conducts equally well in both directions
when ON, and blocks up to 30 Volts peak-to-peak
when OFF. ON resistance is fairly flat over the full
±15 V analog signal range.
The DG243 is designed on the Siliconix PLUS-40
CMOS process to combine low power dissipation
Packaging for this device includes a 16-pin CerDIP
and plastic options. Performance grades include
military, A suffix (-55 to 125°C) and commercial, C
suffix (0 to 70°C) temperature ranges.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
S1~D1
Dual-ln-L1ne Package
S3
IN 1
~A--oD3
I
0
o-----D--C>-..J
S2~D2
~A--oD4
S4 0
o-----D--C>-..J
I
IN 2
Two SPST Switches per Package'
Top View
Order Numbers:
CerDIP: DG243AK, DG243AK/883
Plastic: DG243CK. DG243CJ
Truth Table
SW1
SW3
SW2
SW4
0
OFF
ON
ON
1
OFF
Logic "0" < 0.8 V
Logic "1" ~ 2.0 V
LOGIC
• Switches Shown for Logic "1" Input
5-151
Siliconix
incorporated
DG243
ABSOLUTE MAXIMUM RATINGS
vv+ ...........................................
Voltages referenced to
44 V
V L ............................ (GND -0.3 V) to 44 V
GND ......................................... 25 V
DlgitallnputsaVs, Vo .............. -2 V to (V+ +2V) or
. . . . . . . . . . . . . . . . . . . . . .. 30 mA, whichever occurs first
Current, Any Terminal Except S or D ............ 30 mA
Continuous Current, S or D .................... 30 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max)
......... 100 mA
Storage Temperature (A Suffix) ........... -65 to 150°C
(C Suffix) ........... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(C Suffix) ............ 0 to 70°C
Power Dissipation·
16-Pin CerDIP·· ............................ 900 mW
16-Pin Plastic DIp··· ........................ 450 mW
All leads soldered or welded to PC board.
Derate 12 mW/oC above 75°C.
••• Derate 6 mW/OC above 75°C.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
SYMBOL
PARAMETER
V+ = +15 V
V- = -15 V
GND = 0
VL = 5 V
LIMITS
1=25°C
A
2=125,85,70°C
SUFFIX
3--55,-0°C
-55 to· 125°C
EMP
TYpd
MIN b MAX'
C
SUFFIX
o to 70°C
MINb MAXt UNIT
SWITCH
Analog Signal Range
C
Drain-Source
ON Resistance
rOS(ON)
Source OFF
Leakage Current
IS(OFF)
Drain OFF
Leakage Current
Vo = ± 10 V
Is=10mA
1,3
Vs= 14 V
Vo= -14 V
Vs= -14 V
Vo= 14 V
2
Vs= -14 V
Vo= 14V
1
2
0.17
Vs= 14 V
Vo= -14 V
1
2
-0.35
1
0.05
15
-15
15
V
.n
30
50
75
50
75
1
2
0.2
1
100
1
100
1
-0.3
2
-1
-100
-1
-100
1
100
1
100
nA
lo(oFF)
Vs=Vo=14V
Drain ON
Leakage Current
-15
1,2,3
VANALOG
-1
-100
-1
-100
2
200
2
2
200
lo(oN)
-2
Vs=Vo=-14V
1
2
-0.04
-2
-200
1
-0.01
2
-1
-1
1
1
-1
-1
1
1
-0.005
-1
-1
1
1
-1
-1
1
1
-200
INPUT
Input Current with
Input Voltage HIGH
IINH
VIN = 2.0 V
Input Current with
Input Voltage LOW
IINL
VIN = O.B V
.llA
5-152
1
2
H
DG243
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+=+15V
V-=-15V
GND = 0
VL = 5 V
LIMITS
1=25·C
A
2=125,85,70·C
SUFFIX
3=-55,O·C
-55 to 125°C
TEMP
MINb MAx"
TYpd
C
SUFFIX
a to 70°C
MINb MAXb UNIT
DYNAMIC
Turn-ON Time
tON
Turn-OFF Tlma
tOFF
Charge Injection
Q
Source-OFF Capacitance
Drain-OFF Capacitance
Channel ON Capacitance
C L = 1000 pF, Vgen = 0 V
Rgen = O.n.
CS(OFF)
CD(OFF)
1
250
500
700
1
390
1000
1200
1
60
1
15
1
17
1
45
See Switching
Time Test Circuit
VD=VS= 0 V
VIN = 0 V
f = 1 MHz
CD(ON) +
CS(ON)
ns
OFF IsolationS
VIN = 5 V, ZL=75.n.
1
75
Crosstalk
( Channel-to-Channel)
Vs= 2.0 V, f = lMHz
1
89
pC
pF
dB
I
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1
180
1
-150
IL
1
100
IGND
1
-140
300
-300
300
-300
~A
All Channels ON or OFF
Logic Supply Current
Ground Supply Current
300
-300
300
-300
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
For Logic "1" - V INH = 2.0 V
For Logic "0" - V INL = 0.8 V
5-153
DG243
...... Siliconix
incorporated
~
DIE TOPOGRAPHY
"'~"----107 m l l s s - - - - -...... ,
Pad
No.
~l
1
3
4
5
6
8
9
10
11
12
13
14
15
16
10
9
!
69 mils
3
8
~--~------------------~~
Function
Drain 1
Drain 3
Source 3
Source 4
Drain 4
Drain 2
Source 2
Input 2
V + (Substrate)
VL
GND
VInput 1
Source 1
ICMKC
9 Capacitors
6 Resistors
31 P-channel enhancement MOSFET
33 N-channel enhancement MOSFETs
9 Diodes
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs =constant with logic input waveform as shown. Note that VS may be +
or - as per switching time test circuit. Vo is the steady state output with switch ON. Feedthrough via gate
capacitance may result in spikes at leading and trailing edge of output waveform.
+5 V
t r <20ns
tf <20 ns
LOGIC
INPUT 0 V
S~~S~
+15 V
SWITCH
INPUT S 1
Vs
= ±10 V
SWITCH
OUTPUT
0-1-----0"': "-t-CI'--r--r-o V OUT
+-___
Vs_~~_ _ _ _
SWITCH
OUTPUT 0 V ---1-J
(REPEAT TEST
FOR IN2)
NOTE: Logic Input waveform Is Inverted for
switches that have the opposite logic
sense control.
CHARGE INJECTION TEST CIRCUIT
INX~F
=measured voltage error due to charge InJection.
The charge Injection In coulombs Is b. Q = C L X b. V0-
b. Vo
5-154
DG243
..... Siliconix
,.1;11 incorporated
SCHEMATIC DIAGRAM (Typical Channel)
V+
~----~----~--~--OSx
LOGIC
TRIPPOINT
REF
CaMP
1--1---1
GND 0 - - " - - - - '
IN x
L-----~--~-------oDx
o----'\M~--4---'
VAPPLICATIONS
The make-before-break operation of the DG243
provides simple transient suppression in these two
important applications.
Figure 1 shows a minimum amount of glitching
during changes of gain states. The relatively low
impedance of the gain setting resistors 10k, 1 kil,
100 il shunt the injected charge to ground
minimizing transient effects occurring at the
inverting input of the op amp. Consequently, these
transients are not amplified to VOUT.
-
V IN - - - - - - - - - - - ~-------~--oVOUT
VOUT~
10 k.rl
IN~
100 k.rl
CLEAN TRANSITIONS NO GLITCHES
DUE TO CHARGE COUPLING
1/2 DG243
Figure 1. Improving Transient Response In Programmable
Gain Amplifiers. "Getting Rid of Glitches" .
Figure 2 takes advantage of the make-before-break
operation of the DG243 by shorting transition
current to real ground instead of virtual ground. The
best results are obtained by selecting an op amp
with the proper offset voltage specification.
DG243
>---+-0
V IN2 o-..JVI/I.r--il---~-<:r
V OUT
'"--i--'
Figure 2. Minimizing Glitches In Audio Switching
5-155
.-po Siliconix
DG271
High-Speed Quad Monolithic
SPST CMOS Analog Switch
~
FEATURES
BENEFITS
APPLICATIONS
• Fast Switching
tON, tOFF < 60 ns
• Faster System Operation
• High Speed Switching
• Reduced Switching Glitches
• Sample/Hold
• Charge Injection < 9 pC
• Low Impedance Operation
• rDS(ON) < 50
n
incorporated
• Digital Filters
• Op Amp Gain Switching
• TIL Compatible
• Disk Drives
DESCRIPTION
The DG271
high speed quad single-pole
single-throw analog switch is intended for
applications that require low ON resistance
(rDS(ON) < 50 n), low leakage currents (I S(ON)
< 1 nA), and fast switching speeds (toN < 60 ns).
Built on Siliconix' proprietary high voltage silicon
gate process to achieve superior ON/OFF
performance, each switch conducts equally well in
both directions when ON, and blocks up to 30 volts
peak-to-peak when OFF.
An epitaxial layer
prevents latchup.
Packaging for this device includes the 20-pin LCC,
16-pin CerDIP, plastic DIP, and small outline
options. Performance grades include military, A
suffix (-55 to 125°C), commercial, C suffix (0 to
70°C), and both industrial, Band D suffixes (-25,
-40 to 85°C) temperature ranges.
PIN CONFIGURATION
Dual-In-Llne Package
SO Package
IN 1 1
01
IN2
O2
S2
v-
v+
GNO
NO
(Same pinout as OiP)
1 234 5 6 7 8
S3
Top View
Order Number:
Top View
DG271DY
Order Numbers:
CerDIP: DG271AK. DG271AK/883
DG271BK, DG271CK
PlastIc:
5-156
DG271CJ
Order Number:
DG271AZ/883
DG271
..... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
LOGIC
SWITCH
0
1
ON
OFF
Logic "0" .!i: 0.8 V
Logic "1" .:2: 2.0 Y
• Switches Shown for Logic "1" Input
Four SPST Switches per Package"
ABSOLUTE MAXIMUM RATINGS
(C Suffix) ...........• 0 to 70°C
(D Suffix) .......... -40 to 85°C
V+ to V- ..................................... 44 V
GND to V- .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Dlgltallnputs8 Vs. Vo ... ..... (V-) -2 V to (V+) +2 V or
. . . . . . . . . . . . . . . . . . . . .. 20 mAo whichever occurs first.
Current. Any Terminal Except S or D ............ 30 mA
Continuous Current. S or D ..................•. 20 mA
Peak Current. S or D
(Pulsed at 1 ms, 10% duty cycle max) ......... 100 mA
Storage Temperature (A. 8 & D Suffix) .... -65 to 150°C
(C Suffix) ........... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
Power
16-Pln
16-Pln
16-Pln
20-Pln
Dissipation (Package)"
CerDIP" ....................•.......
Plastic DIP"" ........................
Plastic SO ...........................
LCC""""" ..................•.........
900
470
600
750
mW
mW
mW
mW
Device mounted with all leads soldered or welded to
PC board.
Derate 12 mW/oC above 75°C.
Derate 6.5 mW/oC above 75°C.
Derate 7.6 mW/oC above 75°C.
Derate 7.6 mW/oC above 75°C.
5-i57
DG271
II'1P" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = +15 V
V- = -15 V
GND = 0 V
PARAMETER
LIMITS
1=25·C
A
2=125,85,70·C
SUFFIX
3=-55,-40,-25,O·C -55 to 125°C
SYMBOL
TEMP
VANALOG
1,2,3
TYpd
B,C,D
SUFFIX
o to 70°C
-25 to 85°C
MINb MAX' MINb MAXI
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
rOS(ON)
Source OFF
Leakage Current
IS(OFF)
Is = 1 mA,VIN = 0.8 V
Vo = ± 10 V
-15
15
-15
15
V
.n
1
2,3
32
50
75
50
75
Vs= 14 V
Vo= -14 V
1
2,3
0.05
1
100
1
100
Vs= -14 V
Vo= 14 V
1
2,3
0.05
Vo= 14 V
Vs= -14 V
1
2,3
0.05
VO= -14 V
Vs= 14 V
1
2,3
0.05
Vo =Vs = 14 V
1
2,3
0.05
Vo=Vs=-14V
1
2,3
0.05
-1
-200
-1
-200
VIN = 2.0 V
1
2,3
0.010
-1
-10
-1 '
-10
VIN = 15 V
1
2,3
0.010
VIN=OV
1
2,3
0.010
-1
-100
-1
-100
VIN = 2.0 V
Drain OFF
Leakage Current
IO(OFF)
Channel ON
Leakage Current
IO(ON)+
IS(ON)
1
100
1
100
nA
-1
-100
-1
-100
1
200
1
200
VIN = 0.8 V
INPUT
Input Current with
Input Voltage HIGH
Input Current with
Input Voltage LOW
IINH
IINL
1
10
-1
-10
1
10
JlA
-1
-10
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
Charge Injection
Q
See Switching
Time Test Circuit
C L = 1000 pF, Vgen =
Rgen = o.n
1
2,3
50
60
75
60
75
1
2,3
45
60
75
60
75
1
9
1
2,3
4.3
1
2,3
-3.4
ns
aV
pC
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
All Channels ON or OFF
5-158
7.5
11
7.5
11
mA
-6
-10
-6
-10
DG271
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. V 1N = Input voltage to perform proper function.
For Logic "1" - VINH = 2.0 V
For Logic "0" - V 1NL = 0.8 V
DIE TOPOGRAPHY
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
........- - - 8 1 mils - - -...
2
3
4
5
6
7
Function
Input 1
Drain 1
Source 1
VGND
Source 4
Drain 4
Input 4
Input 3
Drain 3
Source 3
V + (Substrate)
Source 2
Drain 2
Input 2
CSHB
4 Capacitors (1.71pF)
6 Resistors
46 P-channel enhancement MOSFETs
54 N-channel enhancement MOSFET
8 Diodes
TYPICAL CHARACTERSITICS
Leakage Currents
rOS(ON) vs. Vo and Power Supply Voltage
80
rOS(ON)
(.0. )
A:
B:
C:
0:
±5 V Supplies
±7.5 V
+10 V
±15 V
I
V --
60
""
i/o"-
40
~ r--.....
T A = 25°C
Is =-10mA
~
C
0
"
15 ,10
(pA)
V
-
V
20
-15
-10 -5
0
5
10 15
V o - DRAIN VOLTAGE (V)
Analog Voltage
IS(OFF) or 10(OFF)
o
Al
1/
VB.
-50
-100
---
~Nl
// VI
Il
-150
-15
TA = 25°C
I
-10
-5
o
5
10
15
5-159
..
DG271
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
Input Switching Threshold vs. V+ and VSupply Voltages
2.5
Supply Currents vs. Switching Frequency
r---,....---r---"'T'"---'
8
7
2.01---+----+---1""...-:.
6
1.5
I---+----I--...~'
5
1+,1(rnA)
VT
(V) 1.01---+----,"
4
./~
1+
....... 1'
3
1-
0.51---t.:.-'''----I----t----I
2
O~----~----------~----~
o
±5
±10
±15
±20
10 4
V+, V- POSITIVE & NEGATIVE SUPPLIES (V)
10 5
10 s
SWITCHING FREQUENCY
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs =constant with logic input waveform as shown. Note that VS may be +
or - as per switching time test circuit. Vo is the steady state output with switch ON. Feedthrough via gate
capacitance may result in spikes at leading and trailing edge of ou~put waveform.
+15 V
V+
LOGIC 5 V
INPUT 0 V
50%
t r <20 ns
t! < 20 ns
Vs
SWITCH
INPUT S 1
= ±10 V o-I-----o~
SWITCH
OUTPUT
...-i-O'--,..-...,....OV 0
S'r~~5~ Vs
g;r+~5~ V 0
_----if-oJ
(REPEAT TEST
FORIN2' IN3 ' 11Il4)
BURN-IN CIRCUIT
r-ir:==:::;-""t-Q +16 V
160--1-.
16
14
130--1-"
12
11
10
9
+16 V
Note: All Resistors are 10 k
5-160
.n unless otherwise specified
Note: LCC package uses same circuit and conditions as the DIP
DG300A/301 A/302A/303A
CMOS Analog Switches
..,. Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Analog Signal Range
±15 V
• Full Rail to Rail Analog
Signal Range
• Low Level Switching
Circuits
• Fast Switching « 250 ns)
• Low Signal Error
• Low rDS(ON) « 50 n)
o Low Power Dissipation
• Programmable Gain
Amplifiers
III
• Single Supply Operation
Portable and Battery
Operated Circuits
• Latchproof CMOS
DESCRIPTION
The DG300A-DG303A family of monolithic CMOS
switches feature three switch configuration options
(SPST, SPDT, and DPST) for precisior, applications
in communications, instrumentation and process
control, where low leakage switching combined with
low power consumption are required.
Designed on the Siliconix PLUS-40 CMOS process,
these switches are latch proof, and are designed to
block up to 30 Volts peal¥-to-peak when OF~. An
epitaxial layer prevel'TtS latchup.
Featuring low power consumption (a few mW)
these switches are ideal for battery powered
applications, without sacrificing switching speed.
Designed for break-before-make switching action,
these devices are quasi m and CMOS compatible.
Single supply operation is allowed by connecting
the V- rail to 0 volts.
In the ON condition the switches conduct equally
well in both directions (with no offset voltage) and
minimize error conditions with their fairly flat ON
resistance.
Package options for this series include 14-pin
CerDIP and plastic DIP. Performance grades include
the military, A suffix (-55 to 125 D C), commercial, C
suffix (0 to 70 D C) , and industrial, B suffix (-25
to 85 D C) temperature ranges. Additionally, the
DG300A and DG301 A are available in 10-pin metal
cans, while the DG301A and DG303A are available
in 20-pin LCC packages.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DG300A
Metal Can Package
Dual-In-Llne Package
S, o----ll-----~:)_I."--I_o() 0,
Top View
Top View
V+ (SUBSTRATE & CASE)
~
NC
IN,
GNO 7
~~~-
Two SPST Switches per Package"
GNO
Order Numbers:
DG300AAA, DG300AAA/883
DG300ABA. DG300ACA
CerDIP: DG300AAK. DG300AAK/883
DG300ABK, DG300ACK
Plastic: DG300ACJ
Logic "0" S 0.8 V
Logic "1" ~4.0 V
Switches Shown for Logic" 1" Input
5-161
.-F' Siliconix
DG300Al301 Al302A1303A
~
incorporated
FUNCTIONAL BLOCK DIAGRAM (Cont'd)
PIN CONFIGURATION (Cont'd)
Dual-In-Llne Package
Metal Can Package
Top View
Top View
V+
Dl
D2
NO
NO
DG301A
52
IN
51 o---~-----------o~
NO
NO
52 o---~-----------o~
V-
GND
Order Numbers:
CerDIP: DG301AAK, DG301AAK/883
DG301ACK, DG301ABK
Plastic: DG301ACJ
Order Numbers:
DG301AAA,DG301AAA/8B3
DG301ABA, DG301ACA
DN N
One SPOT Switch per Package'
0
N O0E
+ 2l l NO
NO
NO
51
NO
IN
V D
Top View
52
NO
NO
LCC Package
Order Number:
DG301AAZ/883
NO
I
N
G N V N
NO - 0
D
Dual-In-Llne Package
51
0---1------------0..,.-
Dl
Top View
53
o---I------------o-r....-J.--o
D3
IN2
s20---1------------O~1L-
D2
540---t:::::::::::~::~:t--oD4
Two DPST Switches per Package'
Order Numbers:
CerDIP: DG302AAK, DG302AAK/883
DG302ABK, DG302ACK
Plastic: DG302ACJ
DG303A
51
Dual-In-Llne Package
Top View
5 N
Top View
V+
54
D4
D2
52
53
N V 5
o'CJ~
NO
Dl
NO
NO
51
NO
52
~
INl
IN2
52
0---1------------<)-:-....-10--0
54
D4
IN2
V-
Order Numbers:
CerDIP: DG303AAK, DG303AAK/883
DG303ABK, DG303ACK
Plastic: DG303ACJ
I G N V I
N N 0 - N
1 D
2
Two SPOT Switches per Package'
TRUTH TABLE""
LCC Package
LOGIC
Order Number:
DG303AAZ/883
0
1
SWl
SW2
OFF
ON
SW3
SW4
ON
OFF
" 5wltches 5hown for logic "1" Input
"" Logic "0" .:;0.8 V, Logic "1" ::.4.0 V
5-162
D2
DG300Al301 Al302A1303A
..... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
Voltages Referenoed to VV+ ........................................... 44 V
GND ......................................... 25 V
Digital Inputs, Vs, Voe ........ (V-) -2 V to (V+) +2Vor
..................... , 30 mA, whichever oocurs first.
Current, Any Terminal Except S or D ............ 30 mA
Operating Temperature (A Suffix) ......... -55 to 125·C
(8 Suffix) .......... -25 to 85·C
(C Suffix) ..........•. 0 to 70·C
Power
14-Pln
10-Pln
14-Pln
Continuous Current, S or D ...............•.... 30 mA
(Pulsed at 1 ms, 10% duty cycle max) ......... 100 mA
Storage Temperature (A & 8 Suffix) ....... -65 to 150·C
(C Suffix) ........... -65 to 125·C
Dissipation·
CerDIP (K)·· ......................... 825 mW
Metal Can (A)··· ..................... 450 mW
Plastic DIP (J) .......... " ...... , , " " 470 mW
Device mounted with all leads soldered or welded to
PC board.
Derate 11 mW'·C above 75·C.
Derate 6 mW'·C above 75·C.
Derate 6.5 mW'·C above 75·C.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Speclfed:
PARAMETER
V+ = 15 V
V- = -15 V
GND = 0 V
SYMBOL
LIMITS
1=25·C
2=125,85,70 ·C
3=-55,-25,0 ·C
TEMP
TYpd
A
SUFFIX
-55 to 125°C
B, C
SUFFIX
MINb MAXb MINb MAXb UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
Source OFF
Leakage Current
VANALOG
1,2,3
-15
15
-15
15
Vo= 10 V
Is= -10 mA
1,3
2
30
50
75
50
75
Vo= -10 V
Is=10mA
1,3
2
30
50
75
50
75
Vs= 14 V
Vo= -14 V
1
2
0.1
1
100
5
100
Vs= -14 V
Vo= 14 V
1
2
-0.1
Vo= 14 V
Vs= -14 V
1
2
0.1
Vo= -14 V
Vs= 14 V
1
2
-0.1
Vo=Vs= 14 V
1
2
0.1
Vo=Vs= -14 V
1
2
-0.1
-2
-200
-5
-200
VIN =5V
1
2,3
-0.001
-1
-1
-1
VIN = 15 V
1
2,3
0.001
VIN=OV
1
2,3
-0.001
rOS(ON)
V
.n
IS(OFF)
VIN = 0.8 V
-1
-100
-5
-100
or
Drain OFF
Leakage Current
Drain ON
Leakage Current
VIN = 4.0 V
1
100
5
100
IO(OFF)
nA
-1
-100
-5
-100
5
100
1
100
IO(ON)
r
INPUT
Input Current with
Input Voltage HIGH
Input Current with
Input Voltage LOW
IINH
IINL
1
1
1
-1
-1
jl.A
-1
5-163
..
DG300Al301 Al302A1303A
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specilied:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
GND = 0 V
LIMITS
1_25°C
2=125,85,70°C
3=-55,-25,O°C
A
SUFFIX
-55 to 125°C
B,C
SUFFIX
MINb MAXb MINb MAXb UNIT
TEMP
TYpd
1
150
300
1
130
250
1
50
1
3
Vs= 0 V
1
14
Vo= 0 V
1
14
Vs=Vo=OV
1
40
VIN=OV
1
6
VIN = 15 V
1
7
1
62
1
74
1,2
3
0.23
1,3
2
-0.001
1,3
2
0.001
1,3
2
-0.001
DYNAMIC
Turn-ON Time
Turn-OFF Time
Break-Belore-Make
Interval
Charge Inlectlon
tON
See Switching
Time Test Circuit
tOFF
tON -tOFF
Q
Source-OFF
Capacitance
CS(OFF)
Drain-OFF
Capacitance
CO(OFF)
See Break-Belore-Make
Test Time Circuit
DG301A1303A ONLY
C L = 1 nF, Rgen = 0.0.
Vgen=OV
VIN = 0.8 V
or
VIN = 4.0 V
ns
pC
,
1=1 MHz
Channel-ON
Capacitance
Input Capacitance
CO(ON) +
CS(ON)
C in
1= 1 MHz
VIN=OV
RL = 1 k.n
Vs = 1 V rms
1= 500 kHz
OFF Isolation
Crosstalk
(Channel-to-Channel)
pF
dB
SUPPLY
Positive Supply Current
1+
VIN = 4.0 V (One Input)
(All Others = 0 V)
Negative Supply Current
1-
Positive Supply Current
1+
1.0
0.5
1
-10
-100
mA
-100
100
10
100
.I1A
VIN = 0.8 V (All Inputs)
Negative Supply Current
1-
-10
-100
-100
NOTES:
a. Refer to PROCESS OPTION FLOWCHART lor additionallnlormatlon.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are lor DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Signals on Sx, D x , or IN xexceedlng V+ or V- will be clamped by Internal.dlodes. Limit diode lorward current to maximum
current ratings.
V
I. OFF Isolation: 20 log V~
Vs = Input to OFF switch, Vo = Output.
5-164
-=
lDG300Al301 Al302A1303A
trY" Siliconix
~
incorporated
DIE TOPOGRAPHY
DG300A
I
4
87 mils
Pad
No
2
4
6
7
8
9
11
13
14
Function
Drain 1
Source 1
Input 1
Ground
V-
Input 2
Source 2
Drain 2
V+ (Substrate)
1
6
20X
ICMJA
4 Capacitors
22 N-channel depletion MOSFET
4 Diodes
2 Resistors
18 P-channel depletion MOSFET
DG301A
I~
11
I
87 mils
Pad
No
2
4
6
7
8
11
13
14
Function
Drain 1
Source 1
Input
Ground
v-
Source 2
Drain 2
V + (Substrate)
1
6
20X
ICMJB
4 Capacitors
15 N-channel depletion MOSFET
1 Resistor
2 Diodes
11 P-channel depletion MOSFET
5-165
DG300Al301 Al302A1303A
..... Siliconix
incorporated
~
DIE TOPOGRAPHY (Cont'd)
DG302A
Pad
No.
I
3
4
5
10"1'"
2
3
4
5
6
7
6
9
10
11
12
13
14
Function
Source 3
Drain 3
Drain 1
Souce 1
Input 1
Ground
VInput 2
Source 2
Drain 2
Drain 4
Source 4
V + (Substrate)
ICMJA
8 Capacitors
2 Resistors
22 P-channel depletion MOSFET
30 N-channel depletion MOSFET
4 Diodes
DG303A
~I
3
4
11
5~___~=--=-- ~1087r
___
ICMJC
8 Capacitors
2 Resistors
22 P-channel depletion MOSFET
5-166
30 N-channel depletion MOSFET
4 Diodes
Pad
No.
Function
2
3
4
5
6
7
Source 3
Drain 3
Drain 1
Souce 1
Input 1
Ground
8
V-
9
10
11
12
13
14
Input 2
Source 2
Drain 2
Drain 4
Source 4
V + (Substrate)
DG300Al301 Al302A1303A
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS
rOS(ON) vs.Vo and Temperature
rOS(ON) vs. Vo and Power Supply Voltage
130
110
90
A:
B:
C:
D:
E:
F:
V+
V+
V+
V+
V+
V+
=
=
=
=
=
=
5 V,
B V,
10 V,
12 V,
15 V,
20 V,
VVVVVV-
=
=
=
=
=
=
-5
-B
-10
-12
-15
-20
60
V
V
V --1----1
V
V
V --+----1
V+ = ~15 V
V- = -15 V
50
...-- ............
40
rOS(ON)
(.n)
70 t----1r---t....t:lf-V---+---I
rOS(ON)
(.n)
30
--
5 0 t - - - i - - + -__~---1r---i
-
20
10~--~----~----~--~~--~
-25
-5
-15
5
15
A: 125°C
B: 25°C
C: -55°C
10
-15
25
.............
.............
-10
B
~
r'..
-5
0
Vo (V)
Vo(V)
30
Q
(pC)
20
10
o
I
'/
-15
tON,
tOFF
(ns)
- ~\.
-10
/
'"""
-5
o
400
1\
\
300
tOF
15
Vs (V)
Input Switching Threshold vs. Positive
Supply Voltage
7
I
600
500
400
~--
-
1+, 1(j.lA)
300
200
DG301/DG303 ONLY
o
5
10
15
V+ - POSITIVE SUPPLY VOLTAGE (V)
V+I = +115 V
V-=-15V
VIN = 4 V (one Input)
_
(all other = 0)
5
10
15
V+ - POSITIVE SUPPLY VOLTAGE (V)
- -460j.lA
1+
- :--
0
-Oj015fA
-200
-55 -35 -15
-
220j.lA
I-
100
-100
o
~
700
5
2
~
Supply Current vs. Temperature
.I,
4
\ '\
r--
BOO
6 i - V- = -15 V
T A= 25°C
3
15
toN' ~,
o
10
10
= -15 V
T A= 25°C
VINH = 4.0 V
VINL =OV
I'\.
200
100
../
5
---
v-
500
V+ = +15 V
V- = -15 V
C L = 1 nF
40
5
Switching Time and Break-Before-Make
Time vs. Positive Supply Voltage
Charge Injection vs. Analog Voltage (Vs)
50
--...---
A
.............
1-
10. lB
r
A
5 25 45 65 B5 105 125
TEMPERATURE (OC)
5-167
DG300Al301 Al302A1303A
W'F' Siliconix
~
incorporated
TYPICAL CHARACTERSITICS (Cont'd)
Off Isolation vs. Frequency
150
100
rISO.
(dB)
50
o
""
V+=+15V
V-=-15V
r-- RL = 50.0.
l"ITlll"TITlii[1
0.0001
0.001
0.01
1"--1'
~
0.1
10
100
FREQUENCY (MHz)
Crosstalk vs. Frequency
120
--
1" 1'1"-
100
V+ = +15 V
V-=-15V
RL = 50.0.
See CROSSTALK Test Setup
XTALK
(dB)
1\
80
\..
~I"-
i"
60
0.0001
0.001
0.01
0.1
10
100
FREQUENCY (MHz)
Supply Currents vs. Switching Frequency
15
I Z,~I~II+Nv"'
V- = -15 V
I O(OFF) or I S(OFF) vs. Temperature
~
10
3
10
IV+ ~ +15 1V
V- = -15 V
~,Vo = 14 V
2
1+, 1(mA)
IO(OFF),10
~
IS(OFF)
(nA) 10 1
5
1+
o
I-
10°
5-168
I
§
~
10
-
V
Os
./
1
L-
10 1
10 2
FREQUENCY (kHz)
....
10 3
V-
V
V
./
10-2
-55 -35 -15 5 25 45 65 85
TEMPERATURE (OC)
105 125
~
~
DG300Al301 Al302A1303A
Siliconix
incorporated
TYPICAL CHARACTERSITICS (Cont'd)
Switching Time
I D(ON) vs. Temperature
~
IV+ ~ +lSIV
V- = -15 V
r - I VD = ±14 V
IS(ON)
(nA)
10'
V
10-2
-55 -35 -15
V+ = 115 V
V- = -15 V
350
y
,
Power Supply Voltage
400
~
,
VS.
450
V
300
tON'
tOFF 250
(ns)
200
, V
150
"
"""'-- ""-
tON
'-
to~~
100
50
o
5 25 45 65 85 105 125
TEMPERATURE ('C)
Switching Time
10
VS.
12
14
16
18
20
22
POSITIVE/NEGATIVE SUPPLIES (V)
Temperature
500
450 -IV+='+15 IV
400 '-- V- = -15 V
Vs= +3 V
350
tON. 300
tOFF
(ns) 250
200
150
100
-.....
-- -
•
tON
~
I---~
I---
-~ ~
50
~OFF
~--
a
-55 -35 -15
5 25 45 65 85 105 125
TEMPERATURE ('C)
SCHEMATIC DIAGRAM (Typical Channel)
V+O---~~--~----~----~--------~----~----~--~----~
GNDo-~------~----~
DRAIN
V-o-~------------------~---------+----~--~~---+--------~
INPUT PROTECTION
LOGIC INTERFACE AND SWITCH DRIVERS
ANALOG SWITCH
5-169
DG300Al301 Al302A1303A
..,. Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
Rgen
I
/ /:lvo
Sx
....---A.J"""-If--"--=---1"-----1r--......-'II
..
R",i5"'""......."R>IV'7.-+
'-----------~:-1
CMOS LOGIC
GAIN SELECT
HIGH = Av = 101
76 klL
67 klL
t
-15V
RSET programs L 144 power dissipation, gain-bandwidth product.
Refer to AN73-6 and the L 144 data sheet.
Voltage gain of the Instrumentation amplifier Is :
Av
=1 +
2R2 (In the circuit shown, AV1
R1
= 10.4,
AV2
Low' Power Instrumentation Amplifier with
Digitally Selectable Inputs and Gain
5-172
= 101)
DGP303A
Precision Dual
SPOT CMOS Analog Switch
W'1r' Siliconix
~
incorporated
FEATURES
•
± 22 Volt Input Range
• 10 .n Max ~rOS(ON)
Any Combination
Of Switches
• 0.5 nA Max At 25°C,
±15 V
• Tested ~ tON and
~ tOFF < 50 ns
• Pin Compatible with DG303A
BENEFITS
APPLICATIONS
• Fully Tested Around
±10.8, ±16.5 And
±22 V Supplies
• Precision Data
Acquisition
• Increased Signal Range
• Automatic Test
Equipment
• Reduced Switching Errors
• Precision Instrumentation
• Better Channel-to-Channel
Matching
• Radar Systems
• Simplifies Worst Case
Analysis
• Simplifies Upgrades
DESCRIPTION
The DGP303A is a precIsion dual single-pole
double-throw analog switch designed for critical
applications requiring improved performance over
that obtainable with the popular DG303A. Produced
on an enhanced proprietary high voltage process,
the DGP303A has been fully specified with input
analog signals to ±22 V, making it an ideal choice
for high voltage applications or where the added
margin of safety over traditional switches is of
importance.
rOS(ON), tON and tOFF have been tested and
guaranteed at various input voltages to assure
worst-case error analysis.
An epitaxial layer
prevents latchup.
In addition to the low current leakage specifications,
Packaging for this device includes the 14-pin CerDIP
and plastic DIP options. Performance grades
include military, A suffix (-55 to 125°C) and
industrial, D suffix (-40 to 85°C) temperature
ranges. Customers interested in SO packaging
should design-in the DG403DY.
PIN CONFIGURATION
FUNCTION BLOCK DIAGRAM
Dual-In-Llne Package
81
O--I-------.......,r&--I--o
8 3 0--1-------.....-:
D1
D3
IN1
IN 2
0--f--i
82
0--1-------....,...,1'"&--1--0 D2
84
0-+-------0"
--+-0
D4
Two SPOT Switches per Package
Truth Table
Top View
Order Numbers:
CerOIP: OGP303AAK
OGP303AAK883
Plastic: OGP303AOJ
LOGIC
0
1
SWITCH 1,2 SWITCH 3,4
OFF
ON
ON
OFF
Logic' O· S; 0.8 V
Logic' 1· > 4.0 V
5-173
DGP303A
..,.. Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to Vv+ ........................................... 44 V
GND .•.••..•....•............................ 25 V
Digital Inputs Vs. Vol ............ (V-) -2V to (V+) +2V
. . . . . . . . . . . . . . . . . . . . . or 30 mA. whichever occurs first
Continuous Current (Any Terminal) .............. 30 mA
Current. S or D (Pulsed 1 ms 10% duty) ........ 100 mA
Storage Temperature (A Suffix) .......... -65 to 150°C
(D Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(D Suffix) .......... -40 to B5°C
Power Dissipation (Package)'
14-Pln Plastic DIP" ......................... 450 mW
14-Pln CerDIP'" ........................... 900 mW
All leads welded or soldered to PC board.
•• Derate 6 mW ,oC above 75°C.
••• Derate 12 mW ,oC above 75°C.
Signals on Sx. Dx. or INx exceeding V+ or V- will be
clamped by Internal diodes. LImit forward diode
current to maximum current ratings.
THE DGP FAMILY OF ANALOG SWITCHES AND MULTIPLEXERS
Siliconix has improved its high-voltage metal-gate
CMOS process to allow for lower leakage. higher
voltage
and
lower
variation
performance.
Additionally. through dramatic improvements in
automated testing technology. specifications and
limits that were previously untestable are now 100%
tested and specified on the DGP303A data sheet.
The data sheet specification tables are in a new
format as well. The format is that of a military
drawing. where all specifications are 100% tested.
eliminating any uncertainty about what is actually
tested. Many parameters that were previously listed
as "typical" or "guaranteed by design" are now
100% tested with minimum and maximum values,
so that a worst case design can be realized.
The DGP303A also specified certain parameters
that have never been seen on a DG303A standard
product data sheet in minImax or typical form. An
important example of this is the variation of the
switching time over all channels, which is specified
with a maximum of 50 ns. The variation of "ON"
resistance is Similarly specified and 100% tested to
be less than 10 .n over six different drain voltage
and source current conditions, over all four
channels tested, resulting in 24 different readings.
5-174
This specification is necessary for determining the
worst-case distortion and signal level variation due
to differences in channel resistance and "ON"
resistance modulation effects. Also note that
rDS(ON) is measured at the lower eX1reme of the
voltage operating level, (e.g. ±13.5 V instead of
±15 V) where rDS(ON) is highest.
Leakage currents are specified and tested to new
lower limits at both room temperature and over the
full temperature range. For example, the industrial
range devices' leakages have been reduced from
100 nA (over temp) on the DG303A to 5 nA (over
temp) on the DGP version. Additionally, the
leakages are specified at the eX1remes of the
operating ranges (e.g. ±16.5 V instead of ±15 V),
where the leakages tend to be the highest. This is
essential for designs where worst-case leakage
must be well known, such as precision instruments
and sample-and-hold amplifiers.
The operating range of the DGP303A, up to ±22 V
and down to ±10.8 V. This allows the switches to
have guaranteed performance limits with power
supplies as low as ±12 V (±10%), ±15 V (±10%),
and up to ±20 V (±10%).
DGP303A
.-F' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VIN = 2.4 V, 0.8 Va
LIMITS
1=2SoC
A
2=12S,8SoC
SUFFIX
3=-SS, -40 ° C -S5 to 12SoC
TEMP TYpd
0
SUFFIX
-40 to 8SoC
MINb MAX' MINb MAXb UNIT
SWITCH
Analog Signal Range
Drain-Source
ON Resistance
Delta Drain-Source
ON Resistance
C
1,2,3
VANALOG
rOS(ON)
.6.
rOS(ON)
50
75
50
75
V+ = 10.8 V, V- - 10.8 V
Is=1 mA, Vo =±7.5V
V IN = 0.4 V
1,3
2
40
75
100
75
100
V+ = 22 V, V- = -22 V
Is = 1 mA, Vo = ± 15 V
1,3
2
25
40
60
40
60
Vo - +5,0, -5 V, Is - ±1 mA
VIN = 0.8 V
Worst Combination
1,3
2
3
10
15
10
15
Vs =Vo = 15.5 V
1
2
0.1
-0.5
-60
0.5
60
-0.5
-6
0.5
6
Vs = Vo = -15.5 V
1
2
0.1
-0.5
-60
0.5
60
-0.5
-6
0.5
6
Vo=Vs=21V
1
2
0.4
-2
-200
2
200
-2
-20
2
20
Vo = Vs = -21 V
1
2
0.4
-2
-200
2
200
-2
-20
2
20
Vo = -12.5 V
Vs = +12.5 V
1
2
0.1
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = +12.5 V
Vs = -12.5 V
1
2
-0.1
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = -15.5 V
Vs = +15.5 V
1
2
0.15
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = +15.5 V
Vs = -15.5 V
1
2
-0.15
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = -21 V
1
2
0.2
-2
-100
2
100
-2
2
Vs=+21 V
Vo = +21 V
V s =-21 V
1
2
-0.2
-2
-100
2
100
-2
-10
2
10
Vo = -12.5 V
Vs = +12.5 V
1
2
0.1
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = +12.5 V
Vs = -12.5 V
1
2
-0.1
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = -15.5 V
Vs = +15.5 V
1
2
0.15
-0.5
-50
0.5
50
-0.5
-5
0.5
5
Vo = +15.5 V
1
2
-0.15
-0.5
-50
0.5
50
-0.5
-5
0.5
5
V+ = 13.5 V
V- = -13.5 V
V+ = 16.5 V
V- = -16.S V
V+ = 22 V
V- = -22 V
V+ = 13.5 V
V- = -13.5 V
Drain OFF
Leakage Current
15
30
V+ = 22 V
V- = -22 V
IS (OFF)
-15
1,3
2
IO(ON)+
IS(ON)
Source OFF
Leakage Current
15
V+ = 13.5 V, V- = -13.5 V
Is = 1 mA, Vo = ±10.0 V
V+ = 16.5 V
V- = -16.5 V
Channel ON
Leakage Current
-15
V
.n
nA
IO(OFF)
V+ = 16.5 V
V- = -16.5 V
Vs = -15.5 V
5-175
DGP303A
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
V IN = 2.4 V, 0.8 V e
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
0
3=-55,-40 C -55 to 125°C
TEMP TYpd
D
SUFFIX
-40 to 85°C
MINb MAX' MINb MAXb UNIT
SWITCH (Cont'd)
Vo = -21 V
Drain OFF
Leakage Current
IO(OFF)
1
2
0.2
-2
-100
2
100
-2
-10
2
10
-0.2
V S =-21 V
1
2
-2
-100
2
100
-2
-10
2
10
V+ = 22 V, V- = -22 V
V IN under test = 5 V
1
2
0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
V+ = 22 V, V- = -22 V
VIN under test = 22 V
1
2
0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
V+ = 22 V, V- = -22 V
VIN under test = 0 V
1
2
0.005
-0.5
-5
0.5
5
-0.5
-5
0.5
5
1,3
2
150
300
400
300
400
1,3
2
130
250
350
250
350
V+ = 22 V
V- = -22 V
VS=+21 V
Vo = +21 V
nA
INPUT
Input current with VIN
HIGH
Input current with VIN
LOW
IIH
IlL
J.l.A
DYNAMIC
Turn-ON Time
tON
Tum-OFF Time
tOFF
Delta tON
Delta tOFF
Charge Injection
See Switching Time
Test Circuits
ns
f1
Worst Combination among
channels of the tON
measurements
1,3
2
30
50
100
50
100
f1
Worst Combination among
channels of the tOFF
measurements
1.3
2
30
50
100
50
100
Vgen = 0 V
1
35
Vgen=±10V
1
45
1
14
1
14
1
40
1
64
tON
tOFF
Q
Source OFF CapaCitance d
CS(OFF)
Drain OFF Capacitance d
Co (OFF)
Rgen = 0.0.
~= 10 nF
pC
f=IMHz,V s =OV
pF
f=IMHz,V s =OV
Channel ON Capacltance d
Co + S(ON)
Crosstalk
(Channel-to-Channel)
RL = 75.0.
CL = 5 pF
f = 1 MHz
OFF Isolation
C L = 5 pF
RL = 75.0.
f = 1 MHz
pF
dB
5-176
1
56
DGP303A
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
Test Conditions
Unless Otherwise Specified:
V+=15V,V-=-15V
GND = 0 V
VIN = 2.4 V, 0.8 Va
LIMITS
1=25·C
A
2=125,85·C
SUFFIX
3=-55,-40·C -55 to 125°C
TEMP TYpd
0
SUFFIX
-40 to 85°C
MINb MAX' MINb MAXb UNIT
SUPPLY
Positive Supply
Current
1+
Negative Supply
Current
1-
VIN (One Input) = 4V
All Others = 0 V
V.1 =.116.5 V
1
2
0.45
0.6
1
0.6
1
V IN = 0.8 V, All Inputs
V.1=.116.5 V
1
2
0.001
10
100
10
100
VIN (One Input) = 4 V
All Others = 0 V
V±=.116.5 V
1
2
-0.001
-10
-100
-10
-100
VIN = 0.8 V, All Inputs
V.1=.116.5 V
1
2
-0.001
-10
-100
-10
-100
mA
.llA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
DIE TOPOGRAPHY
20X
Pad
No.
Function
2
3
4
5
6
7
8
9
10
11
12
13
14
Source 3
Drain 3
Drain 1
Source 1
Input 1
Ground
VInput 2
Source 2
Drain 2
Drain 4
Source 4
V+ (Substrate)
ICMJC
8 Capacitors
2 Resistors
22 P-channel depletion MOSFETs
30 N-channel depletion MOSFETs
4 Diodes
5-177
tI"F
DGP303A
~
Siliconix
incorporated
TYPICAL CHARACTERSITICS
rOS(ON) vs.Vo and Temperature
rOS(ON) vs. Vo and Power Supply Voltage
130
110
90
rOS(ON)
(.0. )
60~---r~~~~~---r-A~:~12~5~0~C~
A: V+ = 5 V. V- = - 5 V
B: V+ = 8 V, V- = - 8 V
C: V+ = 10 V, V- = -10 V
V+ = 12 V, V- = -12 V
E: V+=15V,V-=-15V
F: V+ = 20 V, V- = -20 V
V+ = +15 V
V- = -15 V
0:
50~--+---~---r---+---;--~
40~~~--~---r---+--~--~
A/\
70
rOS(ON)
tv
50
-
30
10
-25
T A = 25°C
(.0.)
~ ~ 0':"0 E :.,/'"
'- ' ...
-E
-
-5
-15
B: 250C
C: -550C
15
5
30~--+---~--~~~~~--~
10L-~~~--~==~~~-J
25
-15
-10
-5
0
Vo{V)
VO(V)
Charge Injection
VS.
600
500
30
20
/
-15
I \.
-10
-5
V+ = +15 V
V- = -15 V
VIN = 4 V (one Input)
(all other = 0)
700
40
o
15
800
V+ = +15 V
V- = -15 V
10
10
Supply Current vs. Temperature
Analog Voltage (Vs)
50
Q
(pC)
5
1+, 1_ 400
(JlA) 300
CL = 1 nF
200
o
5
10
-r- -..
22~JlA
1+
100
1/
./
""'"
- --460J1A
o
-100
-200
-55 -35 -15
15
1-
-0.015JlA
Vs(V)
0.18J1A
5 25 45 65 85 105 125
TEMPERATURE (OC)
Off Isolation vs. Frequency
150
100
ISO.
(dB)
50 -
o
""
V+ = +15 V
V- = -15 V
R L = 50.0.
nT[I~rT Iim~1
0.0001
0.001
0.01
0.1
FREQUENCY (MHz)
5-178
r-...
""ro-
"
10
100
DGP303A
II"r Siliconix
~
incorporated
TYPICAL CHARACTERSITICS
Crosstalk vs Frequency
120
-
r--. 1-0"",
100
V+ = +15 V
V- = -15 V
RL= 50.0.
See CROSSTALK Test Setup
X TALK
(dB)
1\
80
~ 1'-,
.......
60
0.0001
0.01
0.001
10
0.1
100
FREQUENCY (MHz)
VS.
15
Supply Currents
Switching Frequency
10 4
J11~I~lJ V
I D(OFF) or I SCOFF) VS. Temperature
IV+ ~ +15 1V
V- = -15 V
10 3 !r-- VD = ±14 V
10
illllill
1+.1(mA)
10 2
Is,1 D 10 1
(nA)
5
,!~
o
~
10°
~
10-1
lif
10 1
10 2
FREQUENCY (kHz)
100
/
10-2
-55 -35 -15
10 3
10 1
1
V-
I>'
V I'
V
-55 -35 -15
,/
5 25 45 65 85
TEMPERATURE (OC)
450 _lV+=1+15 1V
_
V-=-15V
400
Vs= +3 V
350
~
~
10-2
"
105 125
500
V
~
,/
Switching Time VS. Temperature
I D(ON) VS. Temperature
IV+ ~ +15 1V
V- = -15 V
§,VD = ±14 V
I D(ON)
(nA)
,,-
V
I>'
300
tON.
tOFF 250
(ns) 200
150
I--~
L-
~ .....
-
tON
~
~
tlOFF
1--1-
-po
l,...- i-- foo-
100
50
o
5 25 45 65 85 105 125
TEMPERATURE (OC)
-55 -35 -15
5 25 45 65 85 105 125
TEMPERATURE (OC)
5-179
DGP303A
..... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS
Switching Time vs. Power Supply Voltage
450
400
350
300
tON, 250
tOFF
(ns) 200
""""'- ~
tON
""""-
150
to~r-
100
50
o
10
12
14
16
16
20
22
POSITIVEINEGATIVE SUPPLIES (V)
SWITCHING TIME TEST CIRCUITS
Vo is the steady state output with the switch ON. Feedthrough via switch capacitance may result
in spikes at the leading and trailing edge of the output waveform.
+15 V
~~~
4.0V
OV
SWITCH
INPUT
Vs
~
.J
::::::
50%~
II..
_i\~~~~=.;t=OF=F=j~_
VS=3.0
v Bjr----~&...,
SWITCH
INPUT
SWITCH OV
OUTPUT
For load conditions, See Electrical Characteristics
(Includes fixture and stray capacitance)
'1..
Vo
= Vs
RL
---=--RL + ROS(ON)
CHARGE INJECTION TEST CIRCUIT
+15 V
V+
IN x
5-180
OFF
ON
DGP303A
. , . Siliconix
incorporated
~
CROSSTALK TEST CIRCUIT
+15 V
Signal
Generator 0.0 dBm
FREQUENCY
TESTED
100 Hz to
13 MHz
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
Chan A
-15V
Chan B
OFF ISOLATION TEST CIRCUIT
+15V
Signal
Generator 0.0 dBm
FREQUENCY
TESTED
-<~+e_a:;...Y;
4
V
100 Hz to
13 MHz
Analyzer
Chan A
-16 V
Chan B
INSERTION LOSS TEST CIRCUIT
+15V
~C'r-V_+~______~
Signal
Generator
0.0 dBm
Vs
aV,4V
-<"1-+-8-0
100 Hz to
13 MHz
Analyzer
Chan A
Chan B
FREQUENCY
TESTED
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
-15 V
5-181
iii
DGP303A
~
~
Siliconix
incorporated
SOURCE/DRAIN ON CAPACITANCE
+15 V
E
C
v+
Vs
CAPACITANCE
METER
t----+-'''----,
METER
OV
BOONTON 72BD
Capacitance
Meter
or equivalent
SOURCE/DRAIN OFF CAPACITANCE
+15 V
METER
BOONTON 72BD
Capacitance
Meter
or equivalent
SCHEMATIC DIAGRAM (Typical Channel)
~---------~oo
5-182
DGP303A
...... Siliconix
incorporated
~
BURN-IN CIRCUIT
+15 V
Note: All Resistors are 10k
n
unless otherwise specified
APPLICATION HINTS
The figure below shows a precIsion sample-andhold amplifier using the DGP303A. The errors
contributed by the analog switch are mostly
attributed to charge injection and leakage. Charge
injection causes a dc offset to appear on the
holding capacitor.
The low leakage of the DGP303A reduces the droop
rate of the sample and hold.
+15 V
+7.5 V -7.5V
-15 V
B
2
"t'-=-t...,....+--------1r-o Vout
LOGIC
CONTROL
J507
1 = SAMPLE
0= HOLD
-15 V
Precision Sample & Hold
5-183
DG304A130SAl30SAl307A
CMOS Analog Switches
wy" Siliconix
~
FEATURES
BENEFITS
APPLICATIONS
• ± 15 V Input Range
• Full Rail-to-Rail Analog
Signal Range
• Low Level Switching
Circuits
• Low rDSloNI « 500)
• Low Signal Error
• Single Supply Operation
• Wide Dynamic Range
• Programmable Gain
Amplifiers
• Fast Switching « 250 ns)
• CMOS Logic Levels
• Low Power Dissipation
incorporated
• Portable Battery Operation
DESCRIPTION
The DG304A through DG307 A series of monolithic
CMOS switches were designed for applications in
communications. instrumentation and ,process
control. This series is well suited for applicatiOns
requiring fast switching and nearly' flat Q~''',
resistance over the entire analog range. " ' ;~"
Each switch conducts equally well in both directions
when ON. and blocks up to 30 volts peak-to-peak
when,' OFF.
1cOmpatible.
These switches are CMOS
input
There: are :four' ~eVlces ,iff: ~hl~ series. which are
differentiated by' 'the type' of switch action.
,Pack'a9ing f6hhi~,.series include the 14-pin CerDIP
,end'plastic options. The 10-pin metal can option is
also available for the DG304A/DG305A. Performance grades include the military. A suffix (-55 to
125°C). commercial. C suffix (0 to 70°C). and
industrial. B suffix (-25 to 85°C) temperature
ranges. Additionally. the DG307A is available in the
LCC package.
Designed on Siliconix PLUS-40 CMOS proceSS to
achieve low power consumption',,{a fevi'rnilliwatts)
and excellent ON/OFF: switch peif6rmanc8; making
these ideal for battery Po,!"er~d applications;"
without sacrificing switching' IilpeecL Bn!ll!k~befcire
make switching action is guaranteed. and an
epitaxial layer prevents latch up. Single supply
operation (for positive switch voltages) is afforded
by connecting the V- rail to 0 V.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DG304A
Metal Can Package
Dual-ln-L1ne Package
Top View
Top View
v+
S1
°1
IN1
V+
(SUBSTRATE & CASE)
°2
NC
S2
NO
IN2
~
NC
IN1
IN2
-..,
I
S2
°2
Two SPST SwItches per Package'
GNO
Order Numbers:
DG304AAA, DG304AAA/883
DG304ABA. DG304ACA
Order Numbers:
CerDIP: DG304AAK. DG304AAK/883
DG304ABK. DG304ACK
Plastic: DG304ACJ
LogiC "0" ~ 3.5 V
LogiC "1" ~ 11 V
• Switches Shewn for Logic "1" Input
5-184
DG304A1305A1306A1307A
flY' Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM (Cont'd)
PIN CONFIGURATION (Cont'd)
DG305A
Dual-In-Llne Package
Metal Can Package
Top View
Top View
52o-~r-----------or
V+
°2
NO
52
NO
IN
NO
GNO
V-
IN
One SPDT Switch per Package'
Order Numbers:
Order Numbers:
DG305AAA, DG305AAA/883
DG305ABA, DG305ACA
CerDIP: DG305AAK, DG305AAK/883
DG305ABK, DG305ACK
Plastic: DG305ACJ
DG306A
Dual-In-Llne Package
51
Top View
°1
03
53
V+
INI
54
°4
IN2
°2
52
52
IN2
°2
54
°4
V-
Two DPST Switches per Package'
Order Numbers:
CerDIP: DG306AAK, DG306AAK/883
DG306ABK, DG306ACK
Plastic: DG306ACJ
Dual-In-Llne Package
LCC Package
Top View
S N N V S
3 0 0 + 4
3 2 1 2019
NO
V+
S3
S4
°1
°2
S2
°4
IN2
V-
"'8"
NO 5
01 6
NO 7
Top View
SI B
9
I
N
1
Order Numbers:
CerDIP: DG307AAK, DG307AAK/883
DG307ABK, DG307ACK
Plastic: DG307ACJ
51
53
10111213
G N V I
N 0 _ N
2
°
Order Number:
DG307AAZ/883
°4
17 NO
16 02
15 NO
14 S2
INI
IN2
52
54
Two SPDT Switches per Package'
TRUTH TABLE"
LOGIC
SW1
SW2
0
1
OFF
ON
SW3
SW4
ON
OFF
• Switches Shown for Logic "1" Input
... Logic "0" S. 3.5 VI Logic "1" 2: 4.0 V
5-185
•
DG304A130SAl30SAl307A
...... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
V+ to v- ..................................... 44 V
GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Digital Inputs, Vs, Voe ........ (V-) -2 V to (V+) +2Vor
30 mA, whichever occurs first.
Current, Any Terminal Except S or D ............ 30 mA
Continuous Current, S or D .................... 30 mA
(Pulsed at 1 ms, 10% duty cycle max) ......... 100 mA
Storage Temperature (A & 8 Suffix) ....... -65 to 150·C
(C Suffix) .......... -65 to 125·C
Operating Temperature (A Suffix) ......... -55 to 125·C
(8 Suffix) .......... -25 to 65·C
(C Suffix) ........... 0 to 70·C
Power
14-Pln
14-Pln
10-Pln
20-Pln
Dissipation'
CerDIP (K)" .........................
Plastic DIP (J)'" .....................
Metal Can (A)"" ....................
LCC (Z)"'" ........................
625
470
450
750
mW
mW
mW
mW
Device mounted with all leads soldered or welded to
PC board.
Derate 11 mW'·C above 75·C.
Derate 6.5 mW'·C above 25·C.
Derate 6 mW'·C above 75·C.
Derate 10 mW'·C above 75·C.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless otherwise specified:
PARAMETER
V+ = 15 V
V- = -15 V
GND = 0 V
SYMBOL
LIMITS
1=25·C
2=125,85,70·C
3=-55,-25,0·C
TEMP
TYpd
A
SUFFIX
-55 to 125°C
B, C
SUFFIX
MINb MAXb MINb MAXb UNIT
SWITCH
Analog Signal Range c
Drain-Source
ON Resistance
Source OFF
Leakage Current
VANALOG
Is=10mA
VIN = 3.5 or 11 VI
1,2,3
Vo= 10 V
Is= -10 mA
1,3
Vo= -10 V
Is=10mA
Vs= 14 V
Vo= -14 V
2
Vs= -14 V
Vo= 14 V
2
Vs= -14 V
Vo= 14 V
2
Vs= 14 V
Vo= -14 V
2
-15
15
-15
15
30
50
75
50
75
1,3
2
30
50
75
50
75
1
0.1
1
100
5
100
2
rOS(ON)
V
.n
IS(OFF)
VIN = 3.5 V
1
-0.1
-1
-100
-5
-100
or
Drain OFF
Leakage Current
Drain ON
Leakage Current
VIN = 11 VI
1
0.1
1
100
5
100
IO(OFF)
nA
1
-0.1
Vo=Vs=14V
1
2
0.1
Vo=Vs= -14 V
1
2
-0.1
VIN = 5 V
1
2,3
-0.001
VIN = 15 V
1
2,3
0.001
VIN=OV
1
2,3
-0.001
-1
-100
-5
-100
1
100
5
100
IO(ON)
-2
-5
-200
-200
INPUT
Input Current with
Input Voltage HIGH
Input Current with
Input Voltage LOW
5-186
IINH
IINL
-1
-1
-1
1
1
1
-1
-1
-1
J,lA
H
DG304A1305A1306A1307A
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless otherwise specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
GND = 0 V
LIMITS
1=25·C
2=125,85,70 ·C
3=-55,-25,0 ·C
A
SUFFIX
-55 to 125°C
B, C
SUFFIX
MINb MAXb MINb MAXb UNIT
TEMP
TYpd
1
110
250
1
70
150
DYNAMIC
Turn-ON Time
Turn-OFF Time
Break-Before-Make
Interval
Charge Injection
tON
See Switching
Time Test Circuit
tOFF
tON -tOFF
See Break-Before-Make
Test Time Circuit
DG305A/307A ONLY
1
50
Q
C L = O.Ol.MF, Rgen = 1.n.
Vgen=OV
1
30
Vs= 0 V
1
14
Vo = 0 V
1
14
Vs=Vo=OV
1
40
VIN = 0 V
1
6
VIN = 15 V
1
7
1
62
1
74
1,3
2
0.001
Source-OFF
Capacitance
CS(OFF)
Drain-OFF
Capacitance
CO(OFF)
VIN = 3.5 V
or
VIN = 11 V f
ns
pC
f = 1 MHz
Channel-ON
Capacitance
Input Capacitance
CO(ON) +
CS(ON)
C IN
f = 1 MHz
VIN=OV
RL = 1 k.n.
Vs = 1 V rrn •
f = 500 kHz
OFF Isolation 9
Crosstalk
(Channel-to-Channel)
pF
dB
SUPPLY
Positive Supply Current
1+
VIN = 15 V (All Inputs)
Negative Supply Current
1-
1,3
2
-0.001
Positive Supply Current
1+
1,3
2
0.001
Negative Supply Current
1-
1,3
2
-0.001
10
100
-10
-100
100
-100
.MA
10
100
100
VIN = 0 V (All Inputs)
-10
-100
-100
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Signals on Sx, Ox' or IN xexceeding V+ or V- will be clamped by Internal diodes. Limit diode forward current to maximum
current ratings.
f. VIN = Input voltage to perform proper function.
g. OFF Isolation = 20 log
~~.
Vs = Input to OFF switch, Vo= Output.
5-187
DG304A1305A1306A1307A
...... Siliconix
,.J;II incorporated
DIE TOPOGRAPHY
DG304A
·1
"'~.----88 mlls----~
1
,1'4
13
"1
87 mils
Pad
No.
Function
2
4
6
7
8
9
11
13
14
Drain 1
Source 1
Input 1
Ground
v-
Input 2
Source 2
Drain 2
V+ (Substrate)
_1
6
7
8
9
20X
ICMJD
4 Capacitors
2 Resistors
16 P-channel depletion MOSFETs
20 N-channel depletion MOSFETs
4 Diodes
DG305A
88
mlls----~I
14
13
Pad
No.
Function
2
4
Drain 1
Source 1
Input
Ground
VSource 2
Drain 2
V+ (Substrate)
6
7
8
11
13
14
4
20X
ICMJE
4 Capacitors
14 N-channel depletion MOSFETs
1 Resistor
2 Diodes
10 P-channel depletion MOSFETs
5-188
DG304A130SAl30SAl307A
.... Siliconix
incorporated
~
DIE TOPOGRAPHY (Cont'd)
DG306A
1......- - - 8 8
2
mlls-----1~~1
14
13
" tI
3
4
5
11
87 mils
~J
Pad
No.
Function
2
3
4
5
6
7
Source 3
Drain 3
Drain 1
Source 1
Input 1
Ground
9
10
11
12
13
14
Input 2
Source 2
Drain 2
Drain 4
Source 4
V+ (Substrate)
Pad
No.
Function
2
3
4
5
6
7
6
9
10
11
12
13
14
Source 3
Drain 3
Drain 1
Source 1
Input 1
Ground
VInput 2
Source 2
Drain 2
Drain 4
Source 4
V + (Substrate)
6
V-
ICMJD
6 Capacitors
2 Resistors
22 P-channel depletion MOSFETs
30 N-channel depletion MOSFETs
4 Diodes
DG307A
.......- - - - 88 mlls----I~
1
2
14
13
r
3
4
....1"
5 ....._ _ _ _ _ _ _ _ _
7
T"
6
20X
ICMJF
8 Capacitors
2 Resistors
22 P-channel de letlon MOSFETs
30 N-channel depletion MOSFETs
4 Diodes
5-189
DG304A1305A1306A1307A
W'F' Siliconix
~
incorporated
TYPICAL CHARACTERSITICS
rOS(ON) vs.Voand Power Supply Voltage
100
A:
B:
C:
D:
E:
80
rOS(ON)
(.0.)
±5 V
±7.5 V
+10V
±15 V
±20 V
T A = 25°C
A
-
o
-20 -15 -10
rOS(ON)
(.0.)
,
C V
"...,
20
)
60
V
1,....00- r0-
40
,...
=
=
=
=
+7.5 V
+10 V
+15 V
+20 V
TA = 25°C
-
C
-'
D
100..
f-
"-E. "....
A: V+
B: V+
C: V+
D: V+
II'
r-.. ~ /
If'
./ ~ ~
~
If'-'
80
I' Y
I
i""'-
...
100
A
60
40
rOS(ON) vs. Vo and Power Supply Voltage
V- = 0 V
20
-5
0
5
10
15
20
o
5
Vo - DRAIN VOLTAGE (V)
10
15
20
25
Vo - DRAIN VOLTAGE - (V)
Leakage Currents vs. Analog Voltage
10
I
I
.1
II
I
I
or
o - I StOFF)
'j
-10
10 , Is
(pA) -20
~n
ret
-
10(OFF)
..J.-
r-; ~(O~)
I
-30
-40
o
-15
15
O~----~----~------~--~
o
±5
Switching Time vs. Positive Supply
Voltage
240
\
\.
tON.
tOFF 160
(ns)
I\.
120
I
~
"
10
±20
=
=
=
=
+15 V
25°C
+15 V
0
",tON
~
tOFF
V+ - POSITIVE SUPPLY VOLTAGE (V)
5-190
V+
TA
V 1NH
VINL
120
.............
............
-
r--
80
---5
200
tON.
tOFF 160
(ns)
i'...
o
240
,"ON
,"OFF
80
40
~
±15
Switching Time vs. Negative Supply
Voltage
V- = -15 V
TA = 25°C V 1NH = +15 V _
VINL=OV
~
200
±10
V+. V- POSITIVE & NEGATIVE SUPPLIES (V)
VsorVo- (V)
15
40
o
-5
-10
-15
V- - NEGATIVE SUPPLY VOLTAGE (V)
DG304A130SAl30SAl307A
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
Supply Currents vs. Toggle Frequency
8
vlll!llt I
RL = 00
6
CL = 0
Vs = OPEN
1+. 1(mAl 4
2
1/
o
10 4
10 3
II
10 5
10 6
TOGGLE FREQUENCY
(Hzl
SCHEMATIC DIAGRAM (Typical Channel)
DRAIN
INPUT PROTECTION
LOGIC INTERFACE AND SWITCH DRIVERS
ANALOG SWITCH
CHARGE INJECTION TEST CIRCUIT
Rgen
Sx
.--.JV'IN-I---o1 " - - ' - + _ - 0
/ f1 v o
Vo--_J,
Vo
Vgen
...._ _+_IN_X_..1
'1"
CL= 10000 pF
INX
f1 Vo
ON
\
OFF~
IS THE MEASURED VOLTAGE ERROR DUE TO CHARGE INJECTION
THE CHARGE INJECTION IN COULOMBS IS
f1Q
= C LX f1 Vo
5-191
DG304A1305A1306A1307A
...", Siliconix
incorporated
~
BREAK-BEFORE-MAKE TIME TEST CIRCUIT SPOT (OG305A, OG307A)
LOGIC" 1" = SWITCH ON
VINH-lI'
LOGIC
INPUT
T
0 V----'
+15V
V+
\'----
50%
Sl
VSl
VS1-----:;=.====~:---
=3
V
SWITCH
OUTPUT
VOl
01
0'--1-------0...,- ....-t--(>'----t"---,..-O
VS2 = 3 v S
02_-+_____--(J'
SWITCH
VOl
OUTPUT 0 V " ' : : ' : " - - - J
VS2:===~I---I-:-::;::::=
V02
SWITCH
OUTPUT
V-15 V
SWITCHING TIME TEST CIRCUIT
LOGIC" 1" = SWITCH ON
VINH
LOGIC
INPUT
+15 V
tr<20 ns
tf< 20 ns
50%
S
OV---J
Vs = 3 V
0--11------0--
o
VS------t-~==~~-----
g'C'fT.rJi- 0 V
- - - - tJ
tON
V-15 V
APPLICATION HINTS
5-192
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
15
-15
20
-20
15
0
VIN
Logic Input
Voltage
VINHMin/
VINLMax
(V)
11/3.5
11/3.5
11/3.5
SWITCH
OUTPUT
.....~-o-1--,..---oVO
Vs
Analog
Voltage
Range
(V)
-15 to 15
-20 to 20
o to
15
DG304A1305A1306A1307A
..... Siliconix
incorporated
~
APPLICATIONS
2) slower switching speed. Typical curves for
design aid are given in the figures below. The
analog voltage should not go above or below the
supply voltages which in single operation are V+
and 0 volts.
The DG300A series of analog switches will switch
positive analog signals while using a single positive
supply. This facilitates their use in applications
where only one supply is available. The trade-offs
of using single supplies are: 1) Increased rDS(ON):
Input Threshold Voltage vs. Positive
Supply
reStON) vs. Ve and Power Supply Voltage
V- = 0 V
A: V+ - +7.5 V
100
B: V+ = +10 V
All
C: V+ = +15 V
D: V+ =+20 V
80
j
T A =25°C
,.....
5~--~---+----~--~---+----~
4r---+_--+---~---r---+--~
reStON)
VTH
60
(.n. )
(V) 3r---~--~--~--+_--+_--~
40
,..
"- ~ /
"..-- ........ ....
",.
C
D
.......
20
o
o
5
10
15
V+ - POSITIVE SUPPLY VOLTAGE (V)
5
10
15
20
Ve - DRAIN VOLTAGE - (V)
25
+15 V
-15 V
1 M.o.
VIN
10 k.o.
11
9
VOUT
+15 V
-15 V
10 k.o.
8
-
-
13
2
--, rI
I
I
4
6
I
I
I
J
L
11
9
DG304A
A1
1 M.o.
-
7
Ao
Binary
Input
Gain
11
10
01
00
1
10
100
1000
Low Power Binary to Ion Gain
Low Frequency Amplifier
5-193
DG304A1305A1306A1307A
.,.. Siliconix
incorporated
~
APPLICATIONS (Cont'd)
-15 V
RSET
+15 V
VrN1
VrN2
CMOS LOGIC
INPUT SELECT ~4
HIGH = \fNl
1/4 CD4001
2
3M.o.
5
>-......-
0.1
10
100
FREQUENCY (MHz)
Crosstalk vs. Frequency
120
.-.,
I"
I"-l"
100
V+ = +15 V
V- = -15 V
RL = 50
See CROSSTALK Test Setup
X TALK
(dB)
1\
80
i'. ~r-.
~
60
0.0001
0.001
0.01
0.1
10
100
FREQUENCY (MHz)
Supply Currents vs. Switching Frequency
15
~}lIllUl~~1
:Y.
1+, 1(mA)
N-
l-
10
~lli
5
li~
o
~
I D(OFF) or I SCOFF) VB. Temperature
IV+ = +15 V
3
V- = -15 V
10 I:r- VD = 14 V
10 2
IS(OFF)
(nA) 10 1
V
10 0
1
liii
10 0
5-208
10 2
10 1
FREQUENCY (kHz)
10-2
10 3
./
-55 -35 -15
V
""
V
~
I'
5 25 45 65 85
TEMPERATURE (OC)
105 125
DG381 AJ384AJ387AJ390A
..... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
Switching Time VS. Power Supply Voltage
I D(ON) VS. Temperature
450
§
V+ = +15 V
V- = -15 V
. - V D = ±14 V
350
300
/"
IS(ON) 10 1
(nA)
V
,/
1
10-2
,/
-55 -35 -15
V+ = 115 V
V- = -15 V
400
tON. 250
tOFF
(ns) 200
~
150
I"
100
",.
--
tON
I-.
'-
to~~
50
o
5 25 45 65 85 105 125
TEMPERATURE (OC)
10
12
14
16
18
20
22
POSITIVEINEGATIVE SUPPLIES (V)
Switching Time VS. Temperature
500
450 _IV+ =1 +15 1v
_
V- = -15 V
400
Vs= +3 V
350
tON'
tOFF
(ns)
300
250
200
..
- --tON
~
~
150
100
....
~
---r-
~ I--
tlOFF
1----
50
o
-55 -35 -15
5 25 45 65 85 105 125
TEMPERATURE (OC)
SCHEMATIC DIAGRAM (Typical Channel)
V+
CONTROL
IN
GND
DRAIN
V-
INPUT PROTECTION
LOGIC INTERFACE AND SWITCH DRIVERS
ANALOG SWITCH
5-209
DG381 A/384A/387A/390A
...... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
LOGIC "I"
VINH
LOGIC
INPUT
= SWITCH
ON
50%
o
S
OV----'
SWITCH
OUTPUT
......+-!'
LOGIC
INPUT
T
0 V----'
50%
\'---
VS1---------:;=.====;-:-----SWITCH
OUTPUT 0
+15 V
V+
SI
VSl = 3 V
o-:--~------o
01
SWITCH
OUTPUT
__ ..._f_--<~--__,---r_o VOl
_ -+_______<0'"
Vsz = 3 V S
02
VOl
v"":';:"'---JI
v~====~~-----lr-~=
V02
SWITCH
OUTPUT
V-15V
APPLICATIONS
The DG38XA series of analog switches will switch
positive analog signals while using a single positive
supply. This allows their use in applications where
only one supply is available. The trade-offs or
performance given up while using single supplies
are: 1) Increased rOSION): 2) slower switching
5-210
speed. Typical curves for aid in designing with
single supplies are supplied in the figures below.
The analog voltage should not go above or below
the supply voltages which in single operation are V+
and 0 volts.
DG381 Al384A1387Al390A
..... Siliconix
incorporated
~
APPLICATIONS (Cant'd)
rOS(ON) vs. Analog and Positive
Supply Voltage With V- = 0 V
v-
170
I
130
110
rOS(ON)
(.0. )
4
. . . t\.
J
If
V+ = +iI
90
70
50
~
~I'
I- ~
30
10
o
V- = L
0 V __
T A= 25°C
~ OIV I
T A = 25°C
~
150
Switching Tllrne vs.
(V+) - Positive Supply Voltage
5
2
-4
tON.
tOFF
(ns)
UN
II
\
8
10
tON
'\.
tOFF
Yrtll6
2
r-r-
= +10 V
I
3
12
o
14
VA - ANALOG VOLTAGE (V)
o
5
i'.....
10
15
(V+) - POSITIVE SUPPLY VOLTAGE (V)
..
Input Threshold Voltage vs. Positive
Supply
7
V-
Jo V
I
6 '- T A = 2Soc
5
VTH
(V)
4
3
2
~ ...
~
o
S
o>
,
,
"
10
-
',.;...
15
(V+) - POSITIVE SUPPLY VOLTAGE (V)
5-211
DG400-405
Low-Power - High-Speed
CMOS Analog Switches
...... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• ± 15 V Input Range
• Wide Dynamic Range
• ON Resistance < 35 .n
• Low Signal Errors and
Distortion
• High Performance Audio
and Video Switching
• Fast Switching Action
tON < 150 ns
tOFF < 100 ns
• Ultra Low Power
Requirements (Po < 35 IlW)
• Sample and Hold Circuits
• Break-Before-Make
Switching Action
• Battery Operation
• Simple Interfacing
• TTL, CMOS Compatible
DESCRIPTION
The DG400 family of monolithic analog switches
were designed to provide precIsion, high
performance
switching
of
analog
signals.
Combining low power « 35 IlW) with high speed
(toN < 150 ns), the DG400 series is ideally suited
for portable and battery powered industrial and
military applications.
Built on the Siliconix proprietary high voltage silicon
gate process to achieve high voltage rating and
superior switch ON/OFF performance, breakbefore-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions
when ON, and blocks up to 30 volts peak-to-peak
when OFF. ON resistance is very flat over the full
±15 V analog range, rivaling JFET performance
without the inherent dynamic range limitations.
The six devices in this series are differentiated by
the type of switch action as shown in the functional
block diagrams. Package options include the 16-pin
plastic, CerDIP and LCC package. Performance
grades include industrial, D suffix (-40 to 85°C),
and military, A suffix (-55 to 125°C). Additionally,
the DG403 and DG405 are available in the narrow
body surface mount package, SO-16.
FUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION AND TRUTH TABLE
Dual-In-Llne Package
DG405
LCC Package
I
NON 5 N
C 1 C 1 1
3 2 12019
034
8 V-
53 5
NC 6
7GNO
6 NC
B.!
]5
7
"1..
Logic· 0 •
Logic· 1· ~
0.8 V
2.4 V
4 V+
04 8
50 Package
9 10111213
NON 5 I
C 2 C 2 N
2
Top View
Order Numbers:
CerDIP: DG405AK
DG405AK/883
Plastic: DG405DJ
5-212
Order Number:
DG405AZ
Top View
Order Number:
DG405DY
DG400-405
trY' Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION AND TRUTH TABLE (Cont'd)
Dual-In-Une Package
DG400
One SPST Switch per Package
Logic· 0 •
Logic· 1 •
0.8 V
2.4 V
Order Numbers:
CerDIP: DG400AK
DG400AK/883
Plastic: DG400DJ
Dual-In-llne Package
LCC Package
I
N D N S N
C 1 C 1 1
DG401
N C 4 G 3 2 1 2 0 1 9 BVNCS
NC 6
NC 7
NC 8
Two SPST Switches per Package
7GND
Top View
l6 NC
S VL
4 V+
9 10111213
N D N S I
C 2 C 2 N
2
Order Numbers:
CerDIP: DG401AK
DG401AK/883
Plastic: DG401DJ
Logic· O' :::;;
Logic· l ' ~
0.8 V
2.4 V
Order Number:
DG401AZ
Dual-In-Llne Package
DG402
One SPDT Switch per Package
Truth Table
LOGIC
0
1
Top View
SWITCH 1 SWITCH 2
OFF
ON
ON
OFF
Logic· O· :::;; 0.8 V
Logic· 1 • ~ 2.4 V
Order Numbers:
CerDIP: DG402AK
DG402AK/883
Plastic: DG402DJ
5-213
DG400-405
~
~
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION AND TRUTH TABLE (Cont'd)
Dual-In-Llne Package
DG403
Leadless Chip Carrier
Two SPOT Switches per Package
Truth Table
I
N D N S N
o 1 0 1 1
LOGIC
D 3 4 8 3 2 1 2 0 1 9 BVS35
NO 6
Top View
~7
D4 B
OFF
ON
0
1
7GND
6 NO
SWITCH 1 SWITCH 3
SWITCH 2 SWITCH 4
ON
OFF
Logic· O· :::;; 0.8 V
Logic· 1 • ~ 2.4 V
5"\..
4 V+
SO Package
9 10111213
N D N S I
o 2 02 N
2
Top View
Order Numbers:
CerDIP: DG403AK
DG403AK/883
Plastic: DG403DJ
Order Number:
DG403AZ
Top View
Order Number:
DG403DY
Dual-In-Llne Package
DG404
V-
One OPST Switch per Package
Logic· O·
Logic· 1 •
Top View
0.8 V
2.4 V
Order Numbers:
CerDIP: DG404AK
DG404AK/883
Plastic: DG404DJ
ABSOLUTE MAXIMUM RATINGS
V+ to V- ..................•....•.........•.... 44V
GND to V- . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25V
VL to V- ....................•• (GND - 0.3 V) to 44 V
Dlgltallnputs1 Vs. VD ........ (V-) -2 V to (V+ plus 2 V)
• • • . . • • . • • . . . • . . . . . . • . or 30 mA. whichever occurs first
Current (Any Terminal) Continuous •.........•... 30 mA
Current. S or D (Pulsed 1 ms 10% duty) ........ 100 mA
Storage Temperature
(A Suffix) ........ -65 to 150°C
(D Suffix) ........ -65 to 125°C
Operating Temperature (A Suffix) ........ -55 to 125°C
(0 Suffix) ......... -40 to 85°C
5-214
Power Dissipation (Package)·
16-Pln Plastic DIp·· ....................•..•.
16-Pln CerDIP··· .•.......•.................
20-Pln LCC···· • . . . . . . . . . . . . . . . . . . . . . . . . . . ..
16-Pln SO····· .............................
450
900
750
600
mW
mW
mW
mW
All leads welded or soldered to PC board.
Derate 6 mW/oC above 75°C
Derate 12 mW/oC above 75°C
Derate 10 mW/oC above 75°C
••••• Derate 7.6 mW/oC above 75°C
1 Signals on Sx. Ox or INx exceeding V+ or V- will be
clamped by Internal diodes. limit forward diode current to
maximum current ratings.
DG400-405
...,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V
V- = -15 V
VL = 5 V
GND = 0 V
V IN = 2.4V, 0.8 Va
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40°C -55 to 125°C
0
SUFFIX
-40 to 85°C
TEMP TYpd
MINb MAXI
MINb MAX'
UNIT
SWITCH
Analog Signal Range C
-15
VANALOG
15
-15
15
V
rOS(ON)
V+ = 13.5 V, V- = -13.5 V
Is=-10mA'Vo =±10V
1
2,3
20
35
45
45
55
.o.rOS(ON)
V+ = 16.5 V, V- = -16.5 V
Is= -10 mA, Vo= 5,0, -5 V
1
2,3
3.0
3.0
5.0
3.0
5.0
1
2
-.01
-0.25
-20
0.25
20
-0.50
-20
0.50
20
Vo= 15.5 V, Vs= -15.5 V
1
2
-.01
-0.25
-20
0.25
20
-0.50
-20
0.50
20
IO(ON)+
IS(ON)
V+ = 16.5 V, V- = -16.5 V
Vo=Vs= ±15.5 V
1
2
-0.04
-0.4
-40
0.4
40
-1.0
-40
1.0
40
In8ut Current with VIN
L W
IlL
VIN Under Test = 0.8 V
All Other = 2.4 V
1,2
.005
-1.0
1.0
-1.0
1.0
Inrcut Current with VIN
HGH
IIH
VIN Under Test = 2.4 V
All Other = 0.8 V
1,2
.005
-1.0
1.0
-1.0
1.0
1
100
150
150
1
60
100
100
ns
100
pC
Drain-Source
ON Resistance
.0.
Delta Drain-Source
ON Resistance
IS(OFF)
Switch OFF Leakage
Current
IO(OFF)
Channel ON
Leakage Current
V+ = 16.5 V, V- = -16.5 V
Vo= -15.5 V, Vs= 15.5 V
nA
INPUT
JJ.A
II
DYNAMIC
Turn-ON Time
Turn-OFF Time
tON
RL = 300.0., C L = 35 pF
See Figure 1A
tOFF
Break-Belere-Make
Time Delay
to
RL = 300.0., C L = 35 pF
DG402/DG403
1
20
Charge injection
Q
C L = 10,000 pF
Vgen = 0 V, Rgan = 0.0.
1
60
RL = 100.0., C L = 5 pF
1=1 MHz
1
72
Any Other Channel Switches
R L = 100.0., C L = 5 pF
1=1 MHz
1
90
1
12
1
12
1
39
Ofl Iselation
Crosstalk'
(Channel-to-Channel)
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Drain and Source ON
Capacitance
CO(ON) +
CS(ON)
Vs= 0 V
1=1 MHz
10.0
10.0
100
dB
pF
5-215
OG400-405
..... Siliconix
,,6;11 incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V
V- = -15 V
VL = 5 V
GND = 0 V
VIN = 2.4V, 0.8 VB
LIMITS
1=25°C
A
D
2",125,85°C
SUFFIX
SUFFIX
3",-55, -40 ° C -55 to 125°C -40 to 85°C
TEMP TVpd MINb MA>f MINb MAXb UNIT
SUPPLY
1
2,3
0.01
1
2,3
-0.01
IL
1
2,3
0.01
IGND
1
2,3
-0.01
Positive Supply Current
1+
Negative Supply Current
1V+ = 16.5 V, V- '" -16.5 V
VIN = 0.0 or 5.0 V
Logic Supply Current
Ground Current
1
5
1
5
-1
-5
-1
-5
J.LA
1
5
-1
-5
1
5
-1
-5
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
f. Crosstalk performance Is Improved to 110 dB (typ.) with LCC package.
D!E TOPOGRAPHY
DG400
14
Pad
No.
·1
r
8
65 mils
"l
9
10
15
14
20X
CSHCA/B
2 Capacitors
2 Resistors
8 P-channel enhancement MOSFETs
5-216
10 N-channel enhancement MOSFETs
2 Diodes
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
V+
VL
GND
VIN
S
DG400-405
.... Siliconix
incorporated
~
DIE TOPOGRAPHY (Cant'd)
DG401
•
~
Pad
No.
Function
1
2
3
4
5
01
NC
NC
NC
NC
NC
NC
02
82
IN2
r
"~
8
6
7
8
9
65 mils
9
10
10
11
12
13
14
15
16
15
11
12 13
14
20X
v+
VL
GND
VINI
81
CSHCA/B
4 Capacitors
4 Resistors
16 P-channel enhancement M08FETs
20 N-channel enhancement M08FETs
4 Diodes
II
DG402
1--
·1
3
I
8
65 mils
9
"
15
10 11
12 13
14
~
20X
Pad
No.
Function
1
2
3
4
5
6
01
NC
02
82
NC
NC
NC
NC
NC
NC
7
8
9
10
11
12
13
14
15
16
V+
VL
GND
VINI
81
CSHCA
2 Resistors
15 N-channel enhancement M08FETs
4 Capacitors
2 Diodes
11 P-channel enhancement MOSFETs
5-217
trY'
DG400-405
~
Siliconix
incorporated
DIE TOPOGRAPHY (Cont'd)
DG403
Pad
No.
Function
1
2
01
NC
03
3
4
5
6
r
8
7
8
9
65 mils
1:~~~____~~____~~~:: !
11
CSHCA
8 Capacitors
4 Resistors
22 P-channel enhancement M05FETs
12 13
10
11
12
13
14
15
16
14
20X
30 N-channel enhancement M05FETs
53
54
04
NC
02
52
IN2
V+
VL
GNO
VIN1
51
4 Diodes
DG404
.....f--::::--- 82 mils - - -. .
@-'
6 ~ 5
4
Pad
No.
Function
1
01
NC
02
52
NC
NC
NC
NC
NC
NC
2
r
8
1:~____________________
~::
1
12 13
20X
14
65 mils
!
CSHCB
2 Resistors
15 N-channel enhancement M05FETs
4 Capacitors
2 Diodes
11 P-channel enhancement M05FETs
5-218
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V+
VL
GND
VIN1
51
DG400-405
. . . Siliconix
incorporated
~
DIE TOPOGRAPHY (Cent'd)
DG405
Function
Pad
No.
1
2
3
4
5
t
8
6
7
65 mils
9
10
~~----~~----~~
Dl
NC
D3
83
84
D4
NC
D2
82
IN2
V+
VL
GND
VINI
81
B
d
9
CSHCB
8 Capacitors
30 N-channel enhancement M08FETs
4 Resistors
4 Diodes
10
11
12
13
14
15
16
22 P-channel enhancement M08FETs
TYPICAL CHARACTERISTICS
Input Switching Threshold vs.
Logic Supply Voltage
10
~
I
V+=+15 V
v-= -15 V
I
TA = 25·0
/
-
Input Switching Threshold vs.
Power Supply Voltage
V
./
\ ......
-
'/
I
VL =+5 ~
t-
TA = 25 0
r-
t--r-
o
o
o 2
4
6
VL
40
'E'
.c.
8
'2 25
8
UI
0
0::
20
15
8 10 12 14 16 18 20
rDS(ON) VS. V D and
Power Supply Voltage
g
~.g
60
~V+=+15V
V- =-15 V ~
VL = +5 V
~ ~:g
--
~
r----
Io'B
.....
r-.
~
~ '-
_o~
D
E
-10
6
rDS(ON) VS. V D and
Temperature
r-.....'" ~
10
-15
4
POSITIVE/NEGATIVE SUPPLES (VOLTS)
B 85.0
30 ~
2
(VOLTS)
A 125 :0
35 f---
o
10 12 14 16 18 20
8
-5
o
5
Vo (VOLTS)
10
-
15
A V+= 6 V
D V+ = 10 V
50 r-- o V+= 12V
D V+= 15 V
E V+ = 20 V
F V+=22V
'.c.E'
8 40
'2
8 30
UI
0
0::
20
V-= -BV
V-= -10 V
V- = -12 V
V-=-15 V
V-= -20 V
V-=-22V
f\J
-
25·0
TA
A
~ ~ ~~ -2D
~
10
-25
-15
I--
F
-5
5
15
25
Yo (VOLTS)
5-219
DG400·405
.... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
200
Z
180
Id
160
wa
120
0
J:
A: ct.= 10kpF
B: CL = lkpF
C: CL. = 100 pF
140
~
i
i
Charge Injection vs.
Analog Voltage (Vs)
a
100
U
80
I
60
~
40
RV+=+15V
V-=-15 V
VL = +5 V
L
A..L
I"
I
/ ~
Iff
I
~
L-
r-.....
A
~~
20
0
-15
.::::; ~A
-10
-5
0
5
10
15
Vs (VOLTS)
Insertion Loss vs. Frequency
0.0
V+ = +15 V
V-=-15 V
VL - +5 V
VS=lVRMS
See INSERTION LOSS
Test Setup
Iii'
~ -0.6
~
-1.0
~
E
-1.5
i
RL - 600 .n
~1 t'
RL =50 .n
RL = 75.n
-2.0
lK
100
I'
'"1M
lOOK
10K
10M
100M
FREQUENCY (Hz)
IS(OFF) VB. Temperature
I D(OFF) VB. Temperature
l00.0'-'r?=~~::Ij,..,r-rTi
100.01-,rr=====:IJT...,.-r-T""
10.0
It
~
10.0
It
0.1
~
0.01-1.-'"'1-+--7"'"
0.001
0.1-1r""'1i-O.Ol-1Ir.:::.01'+~""
0.001
O.OOOl-+-r--r--Iof:....+--+-~+-l~
-55 -35 -15
5
25
45
TEMPERATURE
65
85 105 125
(OC)
-55 -35 -15
5
25
45
TEMPERATURE
65
85 105 125
(OC)
Leakage currents In this region are determined by extrapolation. Attempts to measure In production are
limited by the ability to control humidity and leakages pin to pin below the dew point (where water condenses).
5-220
DG400-405
..... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
Leakage Current VS.
Analog Voltage
ID(ON) + IS(ON) VS. Temperature
90
100.0
~
u
WHEN VANALOG EXCEEDS
60 f- POWER SUPPLY SWITCH.
SUBSTRATE DIODES
30 I- BEGIN TO CONDUCT.
I
a !e,(OFF) i--.lIIS(OFF)
-(l0
'"
-60
8
10.0
~
,
12
::J
z
a
..!!l
0.1
+
Z
[!]
~
0.01-10:-1-+7
a
.f1 0.001
!-i--'rI
I V+= 15 V
'1.=5V
-90
-55 -35 -15
I; is 4?
TEMPERATU~E
V- -15/ [
TA =25 C
I FOR IS(OFF)' VD = 0 v
-150
-20 -15 -10 -5
65 105 125
65
ID(ON)
+ 1StON)
FOR ID(OFF)' VS= a v .
-120
0.0001 ~1-.,......,.......IIoF--+-+--+-+--+--1
t-l-
Vs/Vo
(Oe)
a
5
10
15
r
20
(VOLTS)
Supply Current VS.
Temperature
100.0
10.0 -
~
.s
~ vv+ = + 15V
= -15 V
::
1.0
~
.!. 0.1
~
...J
±.
0.01
II
vL=+5V
IL
~
~
,.
~
I~
V
~ ~L
~
F= =E"
0.001
-55 -35 -15
5
25
45
65
TEMPERATURE
Break-Betore-Make VS.
Analog Voltage
20
15
~0
~
~
r"\
\
10
5
0
S
r
J
H·
r
-6
\.
-10
-15
f+=+15V
V-=-15 v
II vL =+5 v
'iii'
o
Break-Betore-Make vs.
Power Supply Voltage
40
35
r\.
30
25
20
Not measurable due~
-
\~~~~rfJ~~~
10
BREAK -
\
15
5
...... Vs =+10 V
_ Vs =-10V
HTest
See BBM
Setup I
l
VL = +5 V
"
'-..
10
HTest
SeeBBM
Setup I
-20
85 105 125
(0 C)
'""
"'-
o
20
30
40
50
BErDRE - MAKE TIME
o
5
10
15
20
25
POSmVE/NEGAllVE SUPPLES (VOLTS)
(ns)
Leakage currents In this region are determined by extrapolation. Attempts to measure In production are
limited by the ability to control humidity and leakages pin to pin below the dew point (where water condenses).
5-221
fI"lr' Siliconix
DG400-405
~
incorporated
TYPICAL CHARACTERISTICS (Cont'd)
Switching Time VS ••
Input Logic Voltage (V,N)
V+- +15 V
v- =-15 V
VL =+5 V
Vs =+10V
...... Vs =-10V
540
'iii'
[;
480
w
420
~
-
'iii'
r-
w
[;
360
!:!!
300
~
240
:f
Switching Time
Temperature
240
600
tON I
150
!:!!
120
~
~
.....
120
V+-+15V
V-=-15V
-tON
L
, ,
VL = +5 V
L
...... tOFF
l
-
tOFF
~
I--'"
I-"
V~ = +10 V
L
r-
90 - V S =-10V
Vii. = -10 V -
60
rl-
v
30
60
0
0
o
180
~
:f
180
~
210
VB • •
5
4
3
2
-55 -35 -15
6
5
25
45
65
65 105 125
TEMPERATURE (DC)
Switching Time VS ••
Power Supply Voltage
240
210
[;
180
w
150
~
!:!!
~
~
VL = +5 V
~
'iii'
-
tON
...... tOFF
t
120
w
vs'=-s v
90
t:-.::
60
~
Vs = -s V'-.;
~
p-
~
!:!!
~
~
Vs =.:5'v
30
140
'iii'
[;
Vs = +5 v
\.\.
Switching Time VB ••
Analog Voltage
160
120
r-r--
V+ =+15 V
V- =-15 v
VL = +5 V
100
-
80
60
40
5
10
20
15
-15
25
-10
Vs
Switching Time VS •••
Input Logic Voltage (V,N)
160
V+ - +15 V
V- =-15 V
VL = +5 V
VS=+10V
400
300
250
!:!!
200
1=
150
:f
~
ff-
•
50
0
15
w
100
80
-
~~
60
~
40
20
rv; =-10V
~ I"'"
]
Vs;v
:f
""'"
.LI--""
l- i""""'
I
I
I
Vs --10 V
I
I
I
I
V+- +15 V
V-= -16 V
VL =+5V
-tON
-tOFF
r
0
o
2
VIN
3
4
5
[VOLTS)
• REFER TO FIGURE lA FOR TEST CONDmONS
•• REFER TO FIGURE 18 FOR TEST CONDITIONS
5-222
120
1=
\..
r - - l t OFF
[;
~
!l
tON
100
10
'VS~+16v
140
'iii'
Vs =-10V I--
-
6
(VOLTS)
Switching Time VB •••
Temperature
450
~
o
-s
posrnvEINEGA11VE SUPPLIES (VOLTS)
w
r-r--
o
o
350
...... tOFF
20
o
I
-tON
6
-55 -35 -15
5
25
45
65
TEMPERATURE
65 105 125
(DC)
DG400·405
.... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
Switching Time vs .••
Analog Voltage
Switching Time vs .••
Power Supply Voltage
160
180
'j;i'
160
..s
140
w
120
~
!Z:;:
~
L
I\.\'S =;5 v
Vs =-5V ~
/' I'
V/
VS-+~~~
100
-L
80
Vs = -5 V
60
40
20
-
I
0
o
~
VL = +5 V
I
tON
10
5
~ tOFF
15
140
'j;i'
..s
120
w
100
~
!Z:;:
~
80
60
40 r---I v+::: +15 V
v- = -15 V
r--I VL = +5 V
0
-15
20
-10
..s
w
~
!Z:;:
U
~
180
~
r---- C ~'\..
~'\..
150
r----
F
I A,
6, E
c, D
210
\
D
""""- Vs
E I'><.\ .
90
+5V
Fi">o....~
~
..s
-
-
w
~
!Z:;:
7'
!-'! ~D
'-
i
60
30
I-tON
270
'j;i'
""'" tOFF
A, F
I c,6, ED
240
210
6~'\.
150
o
D
60 I - - E
F
30
5
10
15
20
o
25
POSITIVE SUPPLY [VOLTS)
Switching Time vs .••
Positive Supply Voltage
A, F
I 6, E
C, D
~
~
:;:
~
~
240
210
180
150
120
f',.,
.¢
-I¢'"
I-toN
5
10
15
...... tOFF
20
25
Switching Time vs .••
Positive Supply Voltage
300
270
w
~
POSITIVE SUPPLY (VOLTS)
300
..s
"
90
-
;
cr-..,,'\..'
120
t
0
0
'j;i'
V-=
0 v,
V- = -5
V
= 15 V
v
Vs =-5V
I\,
180
15
[VOLTS)
300
0 v,
-5
V
-15 V
V
..... .......
~'\..
120
vV- =
=
10
Switching Time vs .•
Positive Supply Voltage
Switching Time vs .•
Positive Supply Voltage
240 I - - 6
t---
tOFF
5
Vs
300
270
-
-5
POSITIVE/NEGATIVE SUPPUES [VOLTS)
'j;i'
t--
-tON
20
V0 vV
V- =
= -5
V- -15 v
VS=+5V
A
6
..s
-
w
hE
~
.....
60
30
~
~
:;:
~
.~ ~F
~
i"""""""
I-toN
~
A, F
I B, E
C, D
270
'j;i'
r>
-c~
~~ r-.."
90
~
240
210
V- = -15 V
Vs=-5V
180
A
150 _ 6
C
120
~~
90
t
-
l»
~
h f.?D
,..
~/
60
30
tOFF
V =
- -5
0 vV
v-
I-tON
...... tOFF
0
o
5
10
15
20
POSITIVE SUPPLY [VOLTS)
25
o
5
10
15
20
25
POSITIVE SUPPLY (VOLTS)
• REFER TO FIGURE lA FOR TEST CONDITIONS
REFER TO FIGURE 16 FOR TEST CONDITIONS
5-223
DG400·405
...... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
rOSION) vs. Vo and
Positive Supply Voltage
V-=OV
70
so
'E'
s;;
8
'C
8
50
40
UI
,p
3D
AV+ 7.5V
OV+ 10V
CV+ 12V
OV+ 15V
E V+ 20V
F V+ 22 V
A
ir--i\
A..
~
J
TA=26C-
~ ~ ~-
--
20
-
A
0
F
10
o
5
10
15
20
26
Vo (VOLTS)
SWITCHING TIME TEST CIRCUIT
Vo is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes
at the leading and trailing edge of the output waveform.
LOGIC 3.0 V
INPUT
~~'J¥H
oV
1'-
Vs
11vc;-;;::;;0~.9~V~o=l-
j. tOFF
SWITCH 0 V
OUTPUT
fN~'J¥H
~ !r< 20 ns
50%~f < 20 ns
..J.
-Vs
VS= +10 V
for tON
Vs= -10 V
for tOFF
RL = 300
5V
+15 V
~
n
=35pF
SWITCH S1Iot---<1! '"'--11---'4)---,
INPUT IN1
r--Ot-OC..........
:Lx.::
Repeat test for IN2and ~
For load conditions. See Electrical Characteristics
CL (Includes fixture and stray capacitance)
NOTE: Logic Input waveform Is Inverted for
switches that have the opposite logic
sense control
RL
Vo = Vs ........
RL + rOS(ON)
--=---
Figure 1
BREAK·BEFORE·MAKE TEST CIRCUIT
LOGIC3.0V ~
INPUT
50%
OV
VS1---------
V01~
v----.!I _.- ._, .............
+15 V
VS1= +10 V
VS2= +10 V
r-....r..._--,-., D1
Vol
~~----~-+~------~-.
RLl
S2 Ot----<1! ......+--o--.
SWITCH 0
OUTPUTVS2 _____--I____- f_____
LOGIC..n.:
INPUT
SWITCH 0 V
OUTPUT
RL =300
(Includes fixture and straY capacitance)
5·224
n
CL = 35 pF
DG400-405
..... Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
t:.V~ ,-_ _ _ _......
VO---.J
IN x -----..
ON
OFF
ON
OFF ISOLATION TEST CIRCUIT
+15 V
Signal
Generator
- ± 4000 V
•
•
•
•
•
• Data Acquisition Systems
• Audio Signal Routing and
Multiplexing I Demultiplexing
Reduced Switching Errors
Reduced Glitching
Improved Data Throughput
Reduced Power Consumption
Increased Ruggedness
• ATE Systems
• Battery Operated Systems
• High Rei Systems
DESCRIPTION
The DG408 is an 8-channel single-ended analog
multiplexer designed to connect 1 of 8 inputs to a
common output as determined by a 3-bit binary
address (Ao. Alo A2). The DG409. is a 4-channel
differential analog multiplexer designed to connect
1 of 4 differential inputs to a common dual output
as determined by its 2 bit binary address (Ao. Al).
Break-before-make switching action protects
against momentary crosstalk between adjacent
channels.
An ON channel conducts current equally well in both
directions. In the OFF state each channel blocks
voltages up to the power supply rails. An enable
(EN) function allows the user to reset the
multiplexer/demultiplexer to all switches OFF for
stacking several devices. All control inputs.
address (Ax) and enable (EN) are TTL compatible
over the full specified operating temperature range.
Applications for the DG408/409 include high speed
data acquisition. audio signal switching and routing.
ATE systems. and avionics. High performance and
low power dissipation make them ideal for battery
operated and remote instrumentation applications.
Designed in the 44 V silicon-gate CMOS process.
the absolute maximum voltage rating is extended to
44 volts. allowing operation with ±20 V supplies.
Additionally. single supply operation is also allowed .
An expitaxial layer prevents latchup.
Both DG408 and DG409 are available in dual-in-line
ceramic and plastic packages. and are specified
for operation over the military. A suffix (-55 to
125°C) and industrial. 0 suffix (-40 to 85°C)
temperature ranges.
PIN CONFIGURATION
Dual-In-Llne Package
Top View
Dual-In-Llne Package
Top View
- ,_ _ _ _. . - 5 8
Order Numbers:
CerDIP: DG408AK
Plastic: DG408DJ
Preliminary
Order Numbers:
CerDIP: DG409AK
Plastic: DG409DJ
5-229
..
DG40S/409
WY'Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
V-
GND
V-
V+
GND
S 1 o-+----------a,~~f_() D
S la·o-t---------~I....Mt_oD a
S2o-~-----------~~~~
S2ao-t------~~·-_4~
S3o-+-------~~r_r_~
S3ao-t-----~L--;_-~~
S4o-+------0I~~~r_~
S4ao-t--aI~--+---~-~~
S5o-r--------a,~T_+-4-~_+
Slbo-t--+---+---4--~I~~t_oDb
S6o-r------aI~+_+-+-~~_+
S2bo-+--~--~--~~~--_7~
S7o-r---~~L~~~~~_r_+
S3bo-+---~--~·L---;_----~
S8~~~~~-4_;_;~~~
S4bo-+--a~~---r----~----~
A2
A1
Ao
A1
EN
Ao
EN
00409
Differential 4 Channel Multiplexer
DG408
8 Channel Single Ended Multiplexer
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VV+ ..................................•........ 44 V
GND ......................................... 25 V
Digital Inputs g, Vs, Vo ..•... (V-) -2 V to (V+) +2 V or
. • . . . . . . . . . . . . . • . . . . .. 20 mA, whichever occurs first.
Current (Any Terminal, Except S or D) .......... 30 mA
Continuous Current, S or D ..•................. 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) ...•...... 40 mA
Operating Temperature (A Suffix) ..•...... -55 to 125°C
(D Suffix) ..•......• -40 to 85°C
Storage Temperature (A Suffix) ..••..•...• -65 to 150°C
(D Suffix) ........•. -65 to 125°C
Power Dissipation (Package)·
16-Pln Ceramic DIp·· ........................ 900 mW
16-Pln Plastic DIp··· ....•......••...•..•...• 470 mW
All leads soldered or welded to PC board.
•• Derate 12 mW/oC above 75°C .
••• Derate 6.3 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
2=125,85°C
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-40°C -55 to 125°C
GND = 0 V
PARAMETER
TEMP TYpd
SYMBOL
0
SUFFIX
MINb MAXb MINb MAXt UNIT
SWITCH
Analog Signal Range C
1,2,3
VANALOG
Drain-Source e
ON Resistance
rOS(ON)
Vo =±10 V, VAL = 0.8 V
Is = -200J1A,VAH = 2.4 V
Seauence Each Switch ON
1
2,3
Greatest Change In r OBION)
Between Channels f
rOS(ON)
A
-10 V 2.4 V
SWITCHING TIME TEST CIRCUIT
SWITCH
OUTPUT
Vo
-=- -=-
-=-
SWITCH
OUTPUT
Vo
S'a-S4a
&Oa
00409
S4b
50%
t.<20ns
tf<20ns
S, ON
o.avs,
OV
VSa
o.a Vs
tTRANS
tTRANS
SWITCH
OUTPUT
VOb
0
5-232
50%
OV
Vs,
-=+'5 V
-=- -=-
3V
LOGIC
INPUT
-=-
Figure 1
Preliminary
...
;:-
tI'F
~
DG40S/409
Siliconix
incorporated
SWITCHING TIME TEST CIRCUIT (Cont'd)
+15V
r----1'~0_-I AO
v+
S1
DG40B
-5V
S2 -S 81--0----.
-=-
SWITCH
OUTPUT
VD
DI-o-_-o__-o
3V
LOGIC
INPUT
50%
tr<20ns
tf<20ns
50%
OV
tOFF(EN)
tON(EN
OV
O.IVo
r--~_o_iAo
SWITCH
OUTPUT
VD
-5V
Sla- S4a l--<>-_---.
S2b-S4b
-::&Da
D I--O-.....
AI
Vo
SWITCH
OUTPUT
-_-.Q VDb
-=-
Figure 2
+15 V
3V
V+
All S &Da
EN
AO
Al
LOGIC
INPUT
+5V
DG408
DG409
SWITCH
OUTPUT
VD
OV
Vs
SWITCH
OUTPUT
Vo
-::-
-=-
-::-
OV
-::-
\
tr<20ns
tt<20ns
~ht·
-+I
tOPEN
Figure 3
Preliminary
/
5-233
III
DG411/4121413
Precision Monolithic Quad
SPST CMOS Analog Switches
..... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• ± 15 Volt Input Range
• Widest Dynamic Range
• High Performance Audio
and Video Switching
• ON Resistance < 35
.n
• Low Signal Errors and
Distortion
• Fast Switching Action
tON < 175 ns
tOFF < 145 ns
• Break-Before-Make
Switching Action
• Simple Interfacing
• Ultra Low Power
Requirements
(Po < 35 IlW)
• Precision Automatic Test
Equipment
• Precision Data
Acquisition
• Sample and Hold Circuits
• Communication Systems
• TTL, CMOS Compatible
• Battery Operated Systems
• ESDS Protection> ±4000 V
DESCRIPTION
Each switch conducts equally well in both directions
when ON, and blocks up to 30 volts peak-to-peak
when OFF. ON resistance is very flat over the full
±15 V analog range, rivaling JFET performance
without the inherent dynamic range limitation.
The DG411 series of monolithic quad analog
switches was designed to provide high speed, low
error switching of precision analog, audio and video
signals. Combining low power « 351lW) with high
speed (tON < 175 ns), the DG411 family is ideally
suited for portable and battery powered industrial
and military applications.
The three devices in this series are differentiated by
the type of switch action as shown in the functional
block diagrams. Package options include the 16-pin
CerDIP, plastic and small outline (SO) packages.
Performance grades include both the industrial, 0
suffix (-40 to 85°C), and the military, A suffix (-55
to 125°C) temperature ranges.
To achieve high-voltage ratings and superior
switching performance, the DG411 series was built
on Siliconix's high voltage silicon gate process. An
epitaxial layer prevents latchup.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Dual-ln-L1ne Package
51
01
SO Package
52
OG411
Four SPST Switches per Package
(Same pinout as DIP)
1 234 5 6 7 8
Top View
Top View
Order Numbers:
CerOIP: OG411AK
OG411AK/883
Plastic: OG4110J
5-234
Order Number:
OG4110Y
IN3
Logic' O· ::5:
Logic' l ' ~
0.8 V
2.4 V
·Swltches shown for logic "1" Input.
DG411/4121413
.-y' Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Dual-in-Line Package
OG412
Four SPST Switches per Package
SO Package
IN2
°2
83
Top View
IN3
03
Order Number:
DG412DY
Top View
Logic· o· ~
Logic· 1· ;::::
0.8 V
2.4 V
84
Order Numbers:
CerDIP: DG412AK
DG412AK/883
Plastic: DG412DJ
,.. Switches shown for logic "1" Input.
IN4
Dual-in-Line Package
81
IN2
SO Package
INl
OG413
0,
82
V+
Four SPST Switches per Package
Truth Table·
IN2
VL
°2
83
Top View
IN3
Order Number:
DG413DY
03
84
Top View
Order Numbers:
CerDIP: DG413AK
DG413AK/883
Plastic: DG413DJ
IN4
LOGIC
0
1
SWITCH SWITCH
1,4
2, 3
OFF
ON
Logic· o· ~
Logic· 1· ;::::
ON
OFF
0.8 V
2.4 V
·Swltches shown for logic 111" Input.
°4
ABSOLUTE MAXIMUM RATINGS
V+ to V- .........•........................... 44 V
GNO to V- • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
V L ......................•..... (GND -0.3 V) to 44 V
Digital Inputs, V 8, VOl
.......... (V-) -2 V to (V+) +2 V
or 30 mA, whichever occurs first
Continuous Current (Any Terminal) .............. 30 mA
Current, S or D (Pulsed 1 ms, 10% Duty Cycle) . 100 mA
Storage Temperature (A Suffix) .......... -65 to 150°C
(D Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(D Suffix) ......... -40 to 85°C
Power
16-Pln
16-Pln
16-Pln
Dissipation (Package)·
Plastic DIp·· ......................... 470 mW
CerDIP··· ..................•.....•.. 900 mW
SO···· .............................. 600 mW
All leads welded or soldered to PC board.
Derate 6 mW 1°C above 25°C.
Derate 12 mW 1°C above 75°C.
Derate 7.6 mW/oC above 75°C.
Signals on Sx, Ox, or INx exceeding V+ or V- will be
clamped by Internal diodes. Limit forward diode
current to maximum current ratings.
5-235
DG411/4121413
fI"'lr' Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
0
A
2=125,85°C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-40°C -55 to 125°C -40 to 85°C
VL=5V, GND=OV
VIN = 2.4 V, 0.8 ve
TEMP TYpd MINb MA>f MINbMAX t
SYMBOL
PARAMETER
UNIT
,
,
SWITCH
Analog Signal Range C
-15
VANALOG
Drain-Source ON
Resistance
-15
15
V
35
45
n
rOS(ON)
Is=-10mA, V o =±8.5V
V+ = 13.5 V, V- = -13.5 V
1,3
2
25
Vo= -15.5 V
VS= 15.5 V
1,3
2
-0.1
IS(OFF)
-0.25
-20
0.25
20
-0,25
-20
0.25
20
Vo= 15.5 V
Vs= -15.5 V
1,3
2
-0.1
-0.25
-20
0.25
20
-0.25
-20
0.25
20
Vs =Vo= ±15.5 V
1,3
2
-0.1
-0.4
-40
0.4
40
-0.4
-40
0.4
40
Switch OFF Leakage
Current
I o (OFF)
IO(ON) +
IS(ON)
Channel ON Leakage
Current
15
V+=16.5V
V- = -16.5 V
35
45
nA
INPUT
~8W Current with VIN
IlL
VIN Under Test = 0.8 V
All Other = 2.4 V
1,2,3
.005
-0.5
0.5
-0.5
0.5
Infcut Current with VIN
HGH
IIH
VIN Under Test = 2.4 V
All Other = 0.8 V
1,2,3
.005
-0.5
0.5
-0.5
0.5
1,3
110
175
175
1,3
100
145
145
1
25
1
5
RL = 50n,C L = 5 pF
1=1 MHz
1
68
Any Other Channel Switches
RL=50n,CL=5pF
f - 1 MHz
1
85
1
9
1
9
1
18
Jl.A
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
Break-Belore-Make
Time Delay
to
Charge Injection
Q
OFF Isolatlon C
Crosstalk C
(Channel-to-Channel)
Source OFF CapaCitance C
CS(OFF)
Drain OFF Capacitance
CO(OFF)
Drain and Source ON
Capacitance
5-236
C
C
CO(ON)
+CS(ON)
RL = 300n , C L = 35 pF
See Switching Time Test Circuit
Vs =±10 V
DG413 Only
RL = 300n , C L = 35 pF
Vgen = 0 V, Rgen = on
C L = 10 nF
f = 1 MHz
10
ns
10
pC
dB
pF
DG411/4121413
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
0
2=125,85°C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3--55,-40° C -55 to 125°C -40 to 85°C
VL= 5 V, GND = a V
VIN = 2.4 V, 0.8 ve
TEMP TYpd MINb MAX' MIN b MAX
UNIT
SUPPLY
Positive Supply Current
1+
1
2
.0001
Negative Supply Current
1-
1
2
-.0001
IL
1
2
-.0001
1
2
-.0001
IGND
Logic Supply Current
Ground Current
V+ = 16.5 V, V- = -16.5 V
VIN = 0 or 5 V
1
5
-1
-5
1
5
-1
-5
J1A
1
5
-1
-5
1
5
-1
-5
(UNIPOLAR SUPPLY)
ELECTRICAL CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified: 1=25°C
A
0
2=125,85°C
SUFFIX
SUFFIX
V+ = 12 V, V- = 0 V
3=-55,-40·C
-40
to
85°C
-55
to
125°C
VL= 5 V, GND = a V
VIN = 2.4 V, 0.8 ve
b
b
TYpd
TEMP
MIN MAX' MIN MAXb UNIT
SWITCH
Analog Signal Range C
Drain-Source ON
Resistance
0
VANALOG
rOS(ON)
Is = -10 mA, VD = 3.8 V
V+ = 10.8 V
12
0
12
V
.0.
1,3
2
40
80
100
80
100
1,3
175
250
250
1,3
95
125
125
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
RL = 300.0. , C L = 35 pF
See Switching Time Test Circuit
Vs = 8 V
Break-Belore-Make
Time Delay
to
DG413 Only
RL = 300.0. , C L = 35 pF
1
25
Charge Injection
Q
Vgen = 0 V, Rgen = 0.0.
C L = 10 nF
1
25
1
2
.0001
1
2
-.0001
1
2
-.0001
1
2
-.0001
10
ns
10
pC
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
V+ = 13.2 V
1
5
-1
-5
1
5
-1
-5
VIN = 0 or 5 V
Logic Supply Current
Ground Current
IL
IGNO
J1A
V L = 5.25 V
1
1
5
5
-1
-5
-1
-5
5-237
DG411/4121413
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
NOTES:
I
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. V 1N = Input voltage to perform proper function.
DIE TOPOGRAPHY
DG411/412/413
....t------ 109 mils - - - - - - .
13 12
14
Pad
No.
11
l
15
16
1
2
3
4
5
6
7
70 mils
8
3
4
5
8
9
10
11
12
13
14
15
16
l
7
6
20X
CSHN-A,
e,
8 Capacitors
5 Resistors
Function
C
36 P-Channel Enhancement MOSFETs
44 N-Channel Enhancement MOSFETs
8 Diodes
TYPICAL CHARACTERISTICS
ON-Resistance vs. Vo and
Power Supply Voltage
Switching Time vs. Temperature
240
50
45
40
35
rOS(ON)
30
25
(.0.)
20
A
AV=±.5V
B V=±.8 v
o V=±.10 v
o V=±,12V
E V=±.15 v
F v=t?0v
I
~
,.
F
16
J
A
,
E...... ~
[""-. ;::-
10
5
-~
tON,
tOFF
0
~O
TA = 25·0
t--
150
(ns)
.-.
120
90
60
l- e--
V~
=-15 V
~+5IV
I-- I--
---
-'ON
=+10 V
IVL
...... IOFF
I-- I--
~
t:.-I-io""""
--
30
o
0
-20
-15
-10
-5
0
5
10
V o - DRAIN VOLTAGE (V)
5-238
~+=1+15Iv
V-
180
AB
-
t--
210
A
15
20
-55 -35 -15
6
25
45
65
85 105 125
T - TEMPERATURE (OC)
DG411/4121413
..-F' Siliconix
~
incorporated
TYPICAL CHARACTERISTICS (Cont'd)
S~PIY Current VS.
Leakage Current vs.
Analog Voltage
Input
40
30
---
20
10
0
Is,lo
(pA)
-10
-20
........:::
-50
V
-60
-15
10(OFF)r
I-::::: ~
I S(OFF)
IY"
-30
-40
~
.......
-10
-
::::::1
/'
r
10.l1A
10'
10+S(ON)
I
I
0
5
1 mA
100.l1A
v+= 15 V v- = -15.V
"l=5V
TA =25 C
-5
10mA
t
I.11A
100 nA
10 nA
10
15
10
100
1k
200
140
j
170
110
110
50
Q
(pC)
20
80
~
V+ = +15 V
V- = -15 V
VL -+5 V
A
20
-40
-10
0
5
10M
10
15
.J~
~
-40
-15
-10
V O - DRAIN VOLTAGE (V)
/
I
AI!. r
50
-10
-5
1M
A: CL= 10k pF
B: CL = 1k pF
C: ~"=5oo pF
140
80
-10
100 k
Charge Inlectlon vs.
Analog Vo tage (VS )
Charge Inlectlon vs.
Analog Voltage (Vo)
-70
-15
10 k
f - FREQUENCY (Hz)
Vo or Vs - DRAIN OR SOURCE VOLTAGE (V)
Q
(pC)
witching Frequency
100 mA
AA
~
~
V
C'\:
"
-5
o
5
10
15
V S - SOURCE VOLTAGE (V)
SWITCHING TIME TEST CIRCUIT
Vo is the steady state output with the switch ON. Feedthrough via switch capacitance may result in
spikes at the leading and trailing edge of the output waveform.
+5 V
LOGIC 3.0 V
INPUT
+15 V
SwrrCH
OUTPUT
tr <: 20 ns
50%
If<20ns
~~IJTCH
S1
ot----o'! ......-+---'-1--t"--o Vo
ov
~~CH
Vs
swrrCH
OV
-tv.:;-;;:::;=:==::;t--
OUTPLrr
Repeat lest for al1lN and S.
For load conditions, See Electrical Characteristics
(Includes fixture and stray capacitance)
G..
NOTE:
Vo
= Vs
RL
---=---RL + ROS(ON)
5-239
DG411/4121413
WY'Siliconix
incorporated
~
BREAK-BEFORE-MAKE TIME TEST CIRCUIT
3.0V
LOGIC
INPUT
..J"
5 V
t'---_
50%
OV
+15 V
S1~~----~~
VS1
V
= +10 v o-t-----~'1.'--+<)---------------......--..,...._o01
VS1---------------------0.9 Vo
~
01
SWITCH
OUTPUT 1
OV
VS2--------+-----~-----
(Includes fixture and stray capacitance)
CHARGE INJECTION TEST CIRCUIT
V+
RGEN
GEN
V
1
ar.
01
v-
GND
Vo
I~
IN x
OFF
ON
OFF
OFF
ON
OFF
-=IN x dependent on switch configuration
Input polarity determined by sense of switch
CROSSTALK TEST CIRCUIT
+15 V
C
Signal
Generator 0 dbM
V+
~'r--'--"""
50.n.
FREQUENCY
TESTED
100 Hz to
13 MHz
Analyzer
t----....P--Er-I-':.....----....a-....----t-_o
-15V
5-240
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
~
~
DG411/4121413
Siliconix
incorporated
OFF ISOLATION TEST CIRCUIT
+15 V
Signal
Generator 0.0 dBm
FREQUENCY
TESTED
<1-~I-f3-a:....ov,
2.4 V
100 Hz to
13 MHz
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
-15V
INSERTION LOSS TEST CIRCUIT
+15V
Signal
Generator
0 dBm
FREQUENCY
TESTED
aV,2.4V
-<:1--+-08-0
100 Hz to
13 MHz
-15 V
SOURCE/DRAIN ON CAPACITANCE
+15 V
C
~
CAPACITANCE
METER
V+
Vs
METER
IN x
":"
f = lMHz
Vo
av
BOONTON 72BD
Capacitance
Meter
or equivalent
5-241
DG411/4121413
..... Siliconix
incorporated
~
SOURCE/DRAIN OFF CAPACITANCE
+15V
METER
2.4
CAPACITANCE
METER
-<1--1--0
BOONTON 72BD
Capacitance
Meter
or equivalent
v
f = 1MHz
-15V
SCHEMATIC DIAGRAM (Typical Channel)
V+
SOURCE
VL
VIN
DRAIN
GND
V-
BURN-IN CIRCUITS
-15 V
-15V
0--1-1-0
DG411
+15V
-15 V
b--I--I--o
D--+-+-o
+5 V
+15 V
+5 V
DG412
Note: All resistors are 10 kfi unless otherwise specified.
5-242
0--1-1-0
DG413
+15 V
+5 V
DG411/4121413
tI"1P" Siliconix
~
incorporated
PIN DESCRIPTION
SYMBOL
DESCRIPTION
S
Analog Channel Input or Output
Analog Channel Output or Input
Logic Control input
Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Logic Supply Voltage
D
IN
V+
VGND
VL
APPLICATIONS
Single Supply Operation:
Fast Sample and Hold:
The DG411/412/413 are characterized and tested for
single supply operation at 12 volts. Although these
devices can be operated with single supplies from
7.5 up to 22 V, 12 volts was selected as the test
voltage because a majority of the applications use
12 volts. To function properly 12 volts is tied to pin
13 and 0 volts is tied to pin 4. Note: Pin 12 still
requires 5 volts for proper TTL compatible switching.
The bulk of errors in sample and hold circuits
attributed to analog switches come from two
parameters - leakage currents and charge injection.
Both parameters cause completely different errors to
take place. Leakage currents discharge the holding
capacitor (CH> with time causing droop, while charge
The
injection causes a dc offset to occur.
DG411/412/413's very low leakage current (250 pA)
and charge injection (5 pC) specifications enhance
sample and hold (Figure 1) accuracy .
+15V
+15V
381
+5V
01 2
+15 V
+15 V
100 k.n.
DG411
8W2
14 82
6
02 15
VOUT
6
VIN
16 1N2
5
-15 V
-15 V
Figure 1. Fast, Accurate Sample and Hold
5-243
..
DG411/4121413
..... Siliconix
incorporated
~
APPLICATIONS (Cont'd)
Summing Amplifier
When driving a high impedance, high capacitance
load such as shown in Figure 2, where the inputs to
the summing amplifier have some noise filtering, it
is necessary to have shunt switches for rapid
discharge of the filter capacitor thus preventing
offsets from occuring at the output.
00413
Rs
VOl o~--------~~
VA2 0 1 - - - - - >---4---0 VOUT
V~o-----~
Rs
Figure 2.
5-244
Summing Amplifier
~
~
DG417/418/419
Precision MiniDIP
CMOS Analog Switches
Siliconix
incorporated
FEATURES
BENEFITS
APPLICATIONS
• ± 15 Volt InpLit Range
• Wide Dynamic Range
• Precision Test
Equipment
• ON Resistance < 35
.n
• Fast Switching Action
tON < 175 ns
tOFF < 145 ns
• Ultra Low Power
Requirements
(PD~35 IlW)
• TTL and CMOS Compatible
• Low Signal Errors and
Distortion
• Precision Instrumentation
• Break-Before-Make
Switching Action
• Battery Operated
Systems
• Simple Interfacing
• Sample and Hold Circuits
• Reduced Board Space
• Improved Reliability
• MiniDIP and SO Packaging
• ESDS Protection > ± 4000 V
DESCRIPTION
The DG417, DG41 i3 and DG419 monolithic CMOS
analog switches were designed to provide high
analog
signals.
performance
switching
of
Combining low power « 35 IlW), low leakages,
high speed, low ON resistance and small physical
size, the DG417 series is ideally suited for portable
and battery powered industrial and military
applications reqUlnng high performance and
efficient use of board space.
To achieve high voltage ratings aNd superior
switching performance, the DG417 series is built on
Sliconix's high voltage silicon gate (HVSG) process.
Break-before-make is guaranteed for the DG419,
which is an SPDT configuration. An epitaxial layer
prevents latchup.
Each switch conducts equally well in both directions
when ON, and blocks up to 30 volts peak-to-peak
when OFF. ON resistance is very flat over the full
±15 V analog range, rivaling JFET performance
without the inherent dynamic range and supply
voltage limitations.
The three devices are differentiated by their switch
action as shown in the functional block diagrams.
Package options include the 8-pin plastic and
ceramic DIP, and the small outline. Performance
grades include both the industrial, D suffix (-40 to
85°C) and the military, A suffix (-55 to 125°C)
temperature ranges.
PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM
Dual-In-Llne Package
SO Package
DG417
One SPST Switch per Package
(SAME PINOUT AS DIP)
Top View
Top View
Order Numbers:
CerDIP: DG417AK. DG417AK/883
Plastic: DG417DJ
Preliminary
Order Number:
DG417DY
Logic" 0 •
Logic" 1 •
• Switch Shown for Logic "1' Input
5-245
DG417/418/419
..... Siliconix
incorporated
~
PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM (Cont'd)
Dual-In-Llne Package
SO Package
DG418
(SAME PINOUT AS DIP)
Top View
Top View
Order Numbers:
One SPST Switch per Package
Truth Table'
.:s;;
Order Number:
DG41BDY
Logic· 0
O.B V
Logic· 1 • ~ 2.4 V
SO Package
DG419
CerDIP: DG418AK, DG418AK/883
Plastic: DG418DJ
Dual-In-Llne Package
One SPOT Switch per Package
(SAME PINOUT AS DIP)
Top View
Top View
Order Numbers:
Order Number:
DG419DY
CerDIP: DG419AK, DG419AK/883
Plastic: DG419DJ
:s;;
Logic· O·
0.8 V
Logic· 1 • ~ 2.4 V
• Switches Shown for Logic ·1" Input
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VV+ ........................................... 44 V
GND ..••.••.•.••....••.•..••••.•.••......•••. 25 V
VL •.•••.....•....•.•.......... (GND -0.3 V) to 44 V
Digital Inputs Vs, VD1 ...•.•..•• (V-) -2 V to (V+) + 2 V
.....•••...••....•••. or 30 mA, whichever occurs first
Current, (Any Terminal) Continuous ............. 30 mA
Current (S or D) Pulsed 1 ms, 10% duty cycle •.. 100 mA
Storage Temperature (A Suffix) .......... -65 to 150'C
(0 Suffix) ••....•... -65 to 125'C
5-246
Operating Temperature (A Suffix) •••..••.• -55 to 125'C
(0 Suffix) •......•.• -40 to 85'C
Power Dissipation (Package)'
8-Pln Plastic DIP" ••.....•.•••••••.•••••.••• 400 mW
B-Pln CerDIP'" •..•.........••••..•.•••.••. 600 mW
8-Pln SO···· •.....•...........•••.....•..•. 400 mW
All leads welded or soldered to PC board •
Derate 6 mW/'C above 75·C.
Derate 12 mW"C above 75·C.
•••• Derate 6.5 mW/'C above 75·C.
Signals on S, 0, or IN exceeding V+ or V- will be clamped
by Internal diodes. Limit forward diode current to maxi
mum current ratings.
Preliminary
=
DG417/418/419
W'1P'" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
A
D
2=125,85·C
V+ = 15 V, V- = -15 V
SUFFIX
SUFFIX
3=-55,-40·C
-55
to
125°C
-40
to
85°C
V L = 5 V, GND = 0 V
VIN = 2.4 V, 0.8 Ve
b
b
TYpd
TEMP
MIN MAX' MIN MAXb UNIT
SWITCH
Analog Signal Range
C
Drain-Source ON
Res)stance
-15
VANALOG
rOS(ON)
Is = -10 mA, Vo = ±12.5 V
V+ = 13.5 V, V- = -13.5 V
)S(OFF)
Switch OFF
Leakage Current
DG417
DG418
lo(oFF)
V+ = 16.5 V, V- = -16.5 V
Vo= -15.5 V, Vs= 15.5 V
Vo= 15.5 V, Vs= -15.5 V
DG419
Channel ON
Leakage Current
DG417
DG418
IO(ON)
DG419
V+ = 16.5 V, V- = -16.5 V
Vs = Vo = ±15.5 V
15
-15
35
45
15
V
35
45
.0.
1
2,3
20
1
2,3
-0.1
-0.25
-20
0.25
20
-0.25
-20
0.25
20
1
2,3
-0.1
-0.25
-20
0.25
20
-0.25
-20
0.25
20
1
2,3
-0.1
-0.75
-60
0.75
60
-0.75
-60
0.75
60
1
2,3
-0.4
-0.4
-40
0.4
40
-0.4
-40
0.4
40
1
2,3
-0.4
-0.75
-60
0.75
60
-0.75
-60
0.75
60
nA
INPUT
Input Current with VIN
Low
IlL
VIN = 0.8 V
1,2,3
.005
-0.5
0.5
-0.5
0.5
Input Current with VIN
High
IIH
VIN = 2.4 V
1,2,3
.005
-0.5
0.5
-0.5
0.5
1
2,3
100
175
250
175
250
1
2,3
60
145
210
145
210
175
250
175
250
J.lA
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
Transition Time
ttrans
Break-before-Make
Time Delay
to
Charge InJect)on
Q
Source OFF Capacltance d
DG417, DG418 ONLY
RL = 300.0., C L = 35 pF
Vs=±10V
See Sw)tchlng Time
Test Circuit
DG419 ONLY
RL= 300.0., C L = 35 pF
VS1 = ±10 V, VS2 = :j:10 V
DG419 ONLY
RL= 300.0., C L = 35 pF
VS1 = VS2 = ±10 V
C L = 10 nF
Vgen = 0 V, Rgen = 0.0.
CS(OFF)
ns
1
2,3
1
13
1
60
1
8
DG417
DG418
Preliminary
CO(OFF)
5
pC
pF
f = 1 MHz, Vs = 0 V
Drain OFF
Capac It anced
5
1
8
5-247
DG417/418/419
...,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a.,
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specilled: 1=25·C
A
0
2=12S,85°C
V+ = 15 V, V- = -15 V
SUFFIX
SUFFIX
3=-55,-40·C -55 to 125°C -40 to 85°C
V L =5V, GND=OV
VIN = 2.4 V, 0.8 VB
TEMP TYpd MINb MAX' MINb MAXb UNIT
SYMBOL
DYNAMIC (Cont'd)
DG417
DG418
Channel ON
Capacltance d
Co(ON) +
CS(ON)
1
30
1
35
1
2,3
.0001
1
2,3
-.0001
1= 1 MHz, Vs = 0 V
pF
DG419
SUPPLY
Positive Supply Current
1+
Negative Supply
Current
1-
Logic Supply Current
IL
1
2,3
.0001
IGND
1
2,3
-.0001
Ground Current
V+ = 16.5 V, V- = -16.5 V
VIN = 0.0 or 5.0 V
1
5
1
5
-1
-5
-1
-5
j.l.A
1
5
1
5
-1
-S
-1
-5
NOTES:
a. Reier to PROCESS OPTION FLOWCHART lor addltlonallnlormatlon.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are lor DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
DIE TOPOGRAPHY
DG417
I
-55
4
Pad
No.
mils-I
3,
D
2
54
5
Function
mi1ls
2
3
S
4
V+ (substrate)
5
VL
6
7
IN
V-
GND
J
6
7
20X
CSHH-A
8 P-Channel MOSFETs
10 N-Channel MOSFETs
2 Diodes
5-248
1 Resistor
2 Capacitors
Preliminary
=
DG417/418/419
. . . . Siliconix
incorporated
~
DIE TOPOGRAPHY (Cant'd)
DG418
Pad
No.
Function
0
3
1
54 mils
a
6
7
4
5
6
7
a
GND
V+ (substrate)
VL
IN
V5
1
20X
CSHH-A
a P-Channel
M05FETs
10 N-Channel M05FETs
2 Diodes
1 Resistor
2 Capacitors
DG419
Pad
No.
Function
DA
I
- 5 5 mils-I
4
3
2
2
1
9 54 mils
a
6
7
1
3
51
GND
4
5
6
7
VL
IN
V-
a
9
V+ (substrate)
52
DB
20X
CSHH-A
11 P-Channel M05FETs
15 N-Channel M05FETs
2 Diodes
Preliminary
1 Resistor
4 Capacitors
5-249
DG417/418/419
H
Siliconix
incorporated
SWITCHING TIME TEST CIRCUIT (DG417 AND DG418 ONLY)
Vo is the steady state output with the switch ON. Feedthrough via switch
capacitance may result in spikes at the leading and trailing edge of the
output waveform.
+5 V
LOGIC 3.0 V
~
INPUT
SWITCH
INPUT
+15 V
~:r < 20 ns
50%
-:Lf
< 20 ns
ov
1'-
Vs
-IV;-;;:::;:~;:::=~-
"" IOFF
SWITCH 0 V
OUTPUT
For load conditions, See Electlcal Characteristics
~ (includes fixture and stray capacItance)
NOTE:
;~~~~~~~l,~ah:~c:n~so~~~;f~ I~~C
RL
Va
sense control
= Vs - - - - " ' - - RL + ROS(ON)
BREAK-BEFORE-MAKE TIME TEST CIRCUIT (DG419 ONLY)
5 V
LOGIC
INPUT
3.0V
~
+15 V
Ir < 20 ns
\
o
t1 < 20 ns
ov
VS1= V S 2 ' - - - - - - - - - - - - - - - Va
0.9Vo
o V ---t---+------t--+--
SWITCH
OUTPUT
For Load Conditions, See Electrical Characteristics
(CL Includes fixture and stray capacitance)
TRANSITION TIME TEST CIRCUIT (DG419 ONLY)
+15 V
LOGIC 3.0 V
INPUT
tr < 20 ns
50%
+5 V
V+
11 < 20 ns
OV
S2'Of_ _ _-<~~
VSl
IN
-
VOl
SWITCH
OUTPUT
VS2
-
GNO
For Load Conditions, See Electrical Characteristics
(CL Includes fixture and stray capacitance)
5-250
Preliminary
DG417/418/419
.... Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
IN X
NOTE: FOR DG419
OFF
ON
RGEN1= RGEN2
V GEN1= V GEN2
BURN-IN CIRCUITS
10 k.O.
+15 V
SCHEMATIC DIAGRAM (Typical Channel)
V+
SOURCE
VL
VIN
GND
DRAIN
V-
Preliminary
5-251
DG417/418/419
...... Siliconix
incorporated
~
CROSSTALK TEST CIRCUIT (DG419 ONLY)
50n.
0.0 dBm
FREQUENCY
TESTED
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
100 Hz to
13 MHz
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
FREQUENCY
TESTED
SIGNAL
GENERATOR
ANALYZER
100 Hz to
13 MHz
Analyzer
v-
-=- VIN = 0.8 -15 V
REPEAT TEST, INTERCHANGING S 1 AND S2' VIN
= 2.4
OFF ISOLATION TEST CIRCUIT
+15 V
0.0 dBm
FREQUENCY
TESTED
--_--0
V OUT
The DG417 minimizes offset errors due to its low charge injection.
Throughput is improved because of its low ON resistance and fast
switching speed.
Preliminary
5-253
DG417/418/419
~
~
Siliconix
incorporated
PROGRAMMABLE GAIN AMPLIFIER
OG419
The DG419 accurately allows gain selection in a small package. Switching
into virtual ground reduces distortion caused by rOS(ON) variation as
a function of analog signal amplitude.
PIN DESCRIPTION
SYMBOL
DESCRIPTION
S
An Analog channel Input or Output
An Analog Channel Output or Input
Logic Control Input
Positive Supply Voltage
Negative Supply Voltage
Digital Ground
Logic Supply Voltage
D
IN
V+
VGND
VL
5-254
Preliminary
DG421 1423/425
.... Siliconix
incorporated
~
Low-Power - High-Speed
Latchable CMOS Analog Switches
FEATURES
BENEFITS
APPLICATIONS
• Latched Inputs
• Wide Dynamic Range
• ±15 Volt
• J.LP Compatible
• High Performance
Data Bus Switching
Input Range
• Reduced Component Count
• Precision Sample and
Hold Circuits
• Fast Switching Action
tON < 250 ns
• Low Signal Errors and
Distortion
• Digital Filters
• Ultra Low Power
Requirements
(Po < 35 J.LW)
• Break-Before-Make
Switching Action
• J.LP Controlled Analog
Systems
• ON Resistance < 35
n
• Battery Operation
• TIL, CMOS Compatible
DESCRIPTION
The DG421 series of dual monolithic analog
switches features latchable logic inputs which
simplify interfacing with microprocessors. This
series combines fast switching speed (toN < 250
ns), and low ON resistance (rOS(ON) < 35 n)
making it ideally suited for battery powered
industrial and military applications that require J.LP
compatible analog switches.
To achieve high-voltage ratings and superior
switching performance, the DG421 series is built on
Siliconix's high voltage silicon gate CMOS process.
Break-before-make is guaranteed for the DG423.
An epitaxial layer prevents latchup.
±15
V analog range, rivaling JFET performance
without the inherent dynamic range and supply
voltage limitations.
When WR is set LOW the ""!!!put data latches
become transparent. When WR goes HIGH the
latches store the logic control data. The RS pin is
used to reset all the switches in the circuit to the
default value (all inputs LOW) when it is set LOW.
Each switch conducts equally well in both directions
when ON and blocks up to 30 volts peak-to-peak
when OFF. ON resistance is nearly flat over the full
This family offers three devices, which are
differentiated by switch action as shown in the
functional block diagrams. Packaging includes the
16-pin plastic and CerDIP DIPs. Performance
grades include both the industrial, D suffix (-40 to
85°C) and the military, A suffix (-55 to 125°C)
temperature ranges.
PIN CONFIGURATION
FUNCTION BLOCK DIAGRAM
DG421
Dual-In-Llne Package
~ ~r---------~rr~ro
WR ~r--"'---'
IN,
NC
v-
NC
GND
IN, 0-;--+1
IN2
As ~r---+----'
NC
~o-+------o.-..-+-oo..z
NC
Two SPST Switches per Package
Truth Table
Top View
Order Numbers:
CerOIP: OG421AK, OG421AK/883
Plastic: OG4210J
Preliminary
Logic· 0 .::;; 0.8 V
Logic· 1 •
2.4 V
>
5-255
DG421 1423/425
".,. Siliconix
incorporated
~
FUNCTION BLOCK DIAGRAM
PIN CONFIGURATION
DG423
Oual-ln-Llne Package
Sl o-l------,..,.,~::::-J--oDj
03
S3
WR
1!::!1-rr"LIL"'-"i.------,
RSo--1l+~~-
~,"",='-------'
IN2
~~---------+~~-~
B.!
04
Two SPOT Switches per Package
Top View
Order Numbers:
CerDIP: DG423AK, DG423AK/BB3
Plastic: DG423DJ
Logic' O· S
Logic· 1· ;;::
O.B V
2.4 V
DG425
Oual-In-Llne Package
Sl
S3
,......j1-----.......!"""=~_t_-oDj
03
WR o--1l-t-fCI'COll--I
1!::!1..--,rrULr:u.lr-----,
RSo-J~~
IN2
~ o--1l-------+O~~J--o O2
B.!
04
Two DPST Switches per Package
Truth Table
Top View
Order Numbers:
CerDIP: DG425AK, DG425AK/B83
Plastic: DG425DJ
WR
o
RS
IN X
o
1
Logic· 0 • S O.B V
Logic· 1 • ;;:: 2.4 V
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VV+ •.•..•••••••.••.•••••••.•••.•••••..•••••... 44 V
GND ••••••.•••.••.••.••••••••.•.•••.•••••..•• 25 V
VL ............................ (GND -0.3 V) to 44 V
DlgltallnputsVs, V01 ••.•. V- minus 2 V to (V+ plus 2 V)
•••••••••.••••.•.••.• or 30 mA, whichever occurs first
Continuous Current (Any Terminal) •••.••••.•.••. 30 mA
Current, S or 0 (Pulsed 1 ms, 10% duty) ....••. 100 mA
Storage Temperature (A Suffix) •.••.•••.• -B5 to 150·C
(0 Suffix) .......... -65 to 125·C
5-256
Operating Temperature (A Suffix) ..•...... -55 to 125·C
(0 Suffix) •••••••••• -40 to B5·C
Power Dissipation (Package)"
16-Pln Plastic DIP"" ......................... 450 mW
16-Pln CerDIP""" ....••.•..•.•.•..•.•.••.... 900 mW
All leads welded or soldered to PC Board •
"" Derate 6 mW/·C above 75·C.
""" Derate 12 mW/·C above 75·C.
Signals on Sx, Ox, or INx exceeding V+ or V- will be
clamped by Internal diodes. Limit forward diode
current to maximum current ratings.
Preliminary
DG421 1423/425
..-F' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
0
2=125,85°C
SUFFIX
V+ = 15 V, V- = -15 V
SUFFIX
3=-55,-40°C
55
to
125°C
-40
to
85°C
V L = 5 V, GND = 0 V
VIN = 2.4 V, 0.8 va
b
b
TYpd
MIN MA>f MIN MAXb UNIT
TEMP
SWITCH
Analog Signal Range
C
Drain-Source ON
Resistance
-15
VANALOG
rOS(ON)
IS(OFF)
Switch OFF Leakage
Current
IO(OFF)
Is = -10 mA, Vo =± 8.5 V
V+ = 13.5 V, V- = -13.5 V
V+ = 16.5 V, V- = -16.5 V
Vo= -15.5 V, Vs= 15.5 V
Vo = 15.5 V, Vs = -15.5 V
15
-15
35
45
15
V
35
45
.0.
1,3
2
25
1
2
-0.01
-0.25
-20
0.25
20
-0.25
-20
0.25
20
1
2
-0.01
-0.25
-20
0.25
20
-0.25
-20
0.25
20
IO(ON)
V+ = 16.5 V, V- = -16.5 V
Vs = V D = ±15.5 V
1
2
-0.04
-0.4
-40
0.4
40
-0.4
-40
0.4
40
Input Current with VIN
Low
IlL
V IN under test = 0.8 V
all other = 2.4 V
1,2
0.005
-0.5
0.5
-0.5
0.5
Input Current with VIN
High
IIH
V IN under test = 2.4 V
all other = 0.8 V
1,2
0.005
-0.5
0.5
-0.5
0.5
1
170
250
250
1
140
200
200
Channel ON Leakage
Current
nA
INPUT
/-LA
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
R L = 300.0., C L = 35 pF
See Switching Time
Test Circuit
tww
1
200
200
ns
RL= 300.0., C L = 35 pF
Latch Timing
tow
1
100
100
1
30
30
10
10
Vs=±10V
two
Break-before-Make
Time Delay
to
DG423 Only
RL= 300.0., C L = 35 pF
1
25
Charge Injection C
Q
C L = 10 nF
Vgen = 0 V, Rgen = 0.0.
1
60
1
68
1
85
OFF Isolation Reject Ratio
Crosstalk
(Channel to Channel)
Preliminary
R L =50.o., C L =35pF
f = 1 MHz
Between Any Two Channels
R L = 50 .0., f = 1 MHz
C L= 5 pF
100
100
pC
dB
5-257
..
DG421/423/425
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified: 1=25·C
2=125,85·C
V+ = 15 V. V- = -15 V
3=-55,-40·C
VL = 5 V. GND = 0 V
SYMBOL
PARAMETER
VIN = 2.4 V. 0.8 VB
LIMITS
A
SUFFIX
55 to 125°C
D
SUFFIX
-40 to 85°C
TEMP TYpd MINb MA'if MINb MAXb UNIT
,.
DYNAMIC (Cont'd)
'\
Source OFF Capacitance
CS(OFF)
1
9
Drain OFF Capacitance
Ca(OFF)
1
9
Channel ON Capacitance
Ca(ON) +
CS(ON)
1
18
Positive Supply Current
1+
1
2
.0001
Negative Supply
Current
1-
1
2
-.0001
IL
1
2
.0001
IGND
1
2
-.0001
f = 1 MHz
pF
SUPPLY
V+ = 16.5 V. V- = -16.5 V
VIN = 0 or 5 V
Logic Supply Current
Ground Current
1
5
1
5
-1
-5
-1
-5
j.l.A
1
5
1
5
-1
-5
-1
-5
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
DIE TOPOGRAPHY
93 mils
9
DG421
Pad
No.
8
11
r
;'®1
6
12
5
83 mils
13
14
15
CSHDIA or CSHDIB
126 NMOS
114 PMOS
5-258
16 Capacitors
12 Diodes
12 Resistors
16
20X
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
Ih
WR
NC
NC
NC
NC
RS
D2
S2
IN2
V + (substrate)
VL
GND
VIN1
Sl
Preliminary
DG421 1423/425
..-F' Siliconix
~
incorporated
DIE TOPOGRAPHY (Cont'd)
DG423
...f - - - - - 93 mlliss----___..
Pad
No .
Function
1
2
I2.J...
3
03
4
S3
5
S4
6
~
7
8
RS
02
9
S2
10
11
12
13
14
15
16
16
15
IN2
V+ (substrate)
VL
GND
VIN,
S,
2
20X
CSHD-IA
126 NMOS
114 PMOS
16 Capacitors
WR
12 Diodes
12 Resistors
DG425
Pad
No.
.....- - - - 93 m l l s s - - - -.......
11
!,.
:@"r
12
13
14
15
~--------~------~
2
CSHD-IB
r
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
I2.J...
WR
03
S3
S4
~
RS
O2
S2
IN2
V+ (substrate
VL
GND
VIN,
S,
20X
126 NMOS
12 Diodes
114 PMOS
12 Resistors
16 Capacitors
Preliminary
5-259
..w'" Siliconix
DG421 1423/425
~
incorporated
TYPICAL CHARACTERSITICS
rDS(ON) VS. VD and Power Supply Voltage
V- = 0 V
rDS(ON) VS. V D and Power Supply Voltage
V- = 0 V
60
Is, I D -50 H''----+--j---t--:7I''-----i---i
rDS(ON)
(.n. )
(pA)
I
50
40
/
.,B \
-.
./
C
'\
D
o
5
10
15
........
20
V D - DRAIN VOLTAGE (V)
rDS(ON) VS. VD and Power Supply Voltage
Supply Currents vs. Switching Frequency
A:
B:
C:
D:
E:
±5 V
±7.5 V
+10 V
±15 V
±20 V
1/\
-
T A ~ 25°6
I s =-10mA
4
i](v ,
40
3
1/
, ""-
30
20
20
+7.5 V
+10 V
+15V
+20 V
VANALOG (V)
50
rDS(ON)
(.n.)
--
I
~
A:
B:
C:
D:
:~
-
30
,
1/\
A
\
Ir-' \
1/
-100~~~-~--+_-_+--~-~
-150 '-_..J-_......_....I-_....I._....,j~___I
-15
-5
0
-10
5
10
15
T A = 25°C
Is =-10mA
,
I"
70
o
--
10
-20
B
r-
/
......
J
-10
-5
(rnA)
/'\
C
-
:--....
-15
1+, 1-
'\
D
0
5
2
...
~E
10
~
15
1+&
20
10 3
/
10 4
10 5
10 6
SWITCHING FREQUENCY (Hz)
V D - DRAIN VOLTAGE (V)
Input Switching Threshold vs. V+ and VSupply Voltages
2.5
r------..;...;..-.....;;.----...,
2.0
1.5
1.0
0.5
O~--~--~--~-----I
o
±5
±10
±15
±20
V+, V- POSITIVE & NEGATIVE SUPPLIES (V)
5-260
Preliminary
DG421 1423/425
Siliconix
incorporated
SWITCHING TIME TEST CIRCUIT
Vo is the steady state output with the switch ON. Feedthrough via switch
capacitance may result in spikes at the leading and trailing edge of the
output waveform.
VS= +10 V
for tON
LOGIC 3.0 V
INPUT
~~:JTCH
~:r < 20 ns
..J.
50%
~f < 20
ns
OV
1'-
Vs
-t-----.:..---+--
~
5V
tOFF
SWITCH OV
OUTPUT
~~iJTCH
+15 V
VS= -10 V
fortOFF
SWITCH
INPUT
Repeat test for IN2 and S2
For load conditions, See Electlcal Characteristics
G.. (Includes fixture and stray capacitance)
-Vs
NOTE:
BREAK-BEFORE-MAKE TIME TEST CIRCUIT
LOGIC
INPUT
3.0 V
-.l
50%
OV
t'----_
V S1' - - - - - - - - - - -
V01~
SWITCH
OUTPUT 1
+15 V
VS1=+10V
SIIC>t----O'j" ....
VS2= +10 V
01
+....:....------o---,
V02
S,~~_ _~~~~~~
RLI
300.[).
ov------.l1 ..... I ""VS2'----~--_4~--
SWITCH
OUTPUT 2 0 V
(Includes fixture and stray capacitance)
CHARGE INJECTION TEST CIRCUIT
+15 V
1'1-
IN X--O-F-~-"
ON
OFF
V IN =3.0 V
Preliminary
5-261
DG421 1423/425
H
Siliconix
incorporated
CROSSTALK TEST CIRCUIT
+15V
Signal
Generator
0.0 dBm
FREQUENCY
TESTED
100 Hz to
13 MHz
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
Analyzer
Chan A
RL
Chan B
OFF ISOLATION TEST CIRCUIT
+15 V
FREQUENCY
TESTED
- ±4000 V
DESCRIPTION
The DG444 series of monolithic quad analog
switches was designed to provide high speed, low
error switching of analog signals. Combining low
power « 35 microwatts). with high speed (toN
< 160 ns), the DG444/445 Is ideally suited for
upgrading DG211IDG212 sockets. Charge injection
has been minimized on the drain for use in
sample-and-hold circUits.
To achieve high-voltage ratings and superior
switching performance, the DG444 series was built
on Siliconix's high-voltage silicon-gate process. An
epitaxial layer prevents latchup.
Each switch conducts equally well in both directions
when ON, and blocks up to 30 volts peak-to-peak
when OFF. ON resistance is very flat over the full
±15 V analog range, rivaling JFET performance
without the inherent dynamic range limitation.
The two devices in this series are differentiated by
the type of switch action as shown in the functional
block diagrams for each. Packaging options include
the 16-pin plastic and small outline. The
performance grade for this series is the industrial,
D suffix (-40 to 85°C) temperature range.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Dual-In-Llne Package
IN
DG444
2
O2
so Package
16 15 14 13 12 11 10
S2
V+
9
(Same pInout as DIP)
vL
12345678
Logic· 0 •
Logic· 1 •
S3
03
Top VIew
Order Number:
IN
DG444DY
3
Top VIew
Order Numbers:
DG444DJ
5-274
Preliminary
DG444/445
.-JP'" Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
Dual-In-Une Package
IN
2
O2
DG445
S2
SO Package
Four SPST Switches per Package
V+
16 15 14 13 12 11 10 9
VL
(Sarno pinout as DIP)
12345678
Logic" O· ::;;;
Logic" l ' ;;;::
S3
03
Top View
Order Number:
DG445DY
0.8 V
2.4 V
IN
3
Top View
Order Numbers:
DG445DJ
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VV+ ...........................................
GND .........................................
VL ........................... (GND -0.,3 V) to
DlgltallnputsVs ,vol .,. (V- minus 2 V) to (V+ plus
Operating Temperature (D Suffix) .......... -40 to 85°C
44 V
25 V
44 V
2 V)
. . . . . . . . . . . . . . . . . . . . . or 30 mA, whichever occurs first
Current (Any Terminal) continuous .............. 30 mA
Current (S or D) Pulsed 1 ms. 10% duty ........ 100 mA
Storage Temperature (D Suffix) .......... -65 to 125°C
Power Dissipation (Package)·
16-Pln Plastic DIp·· ......................... 450 mW
16-Pln SO··· ............................... 600 mW
All leads welded or soldered to PC Board .
•• Derate 6 mW'oC above 75°C.
••• Derate 7.6 mW'oC above 75°C.
1
Signals on Sx, Dx, or INx exceeding V+ or V- will be
clamped by Internal diodes. Limit forward diode
current to maximum current ratings.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
GND = 0 V
VIN = 2.4,0.8 VB
LIMITS
1=2SoC
2=8SoC
3=_40°C
TEMP
D
SUFFIX
-40 to 85°C
TYpd
MIN'
MAXb
UNIT
-15
15
V
80
100
.n
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
VANALOG
rOS(ON)
ISIOFF)
Switch OFF Leakage
Current
Is = -10 mA, V o = ± 8.5 V
V+ = 13.5 V, V- = -13.5 V
V+ = 16.5 V, V- = -16.5 V
Vo = ± 15.5 V, Vs = ± 15.5 V
10IOFF)
Channel ON
Leakage Current
Preliminary
1010N) +
'S(ON)
V+ = 16.5 V, V- = -16.5 V
Vs = Vo =
± 15.5 V
1,3
2
1
2
-0.25
-20
0.25
20
1
2
-0.25
-20
0.25
20
1
2
-0.4
-40
0.4
-40
nA
5-275
..
ft'tr
DG444/445
~
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V
V- = -15 V
VL = 5 V
GND = 0 V
=
2.4,0.8 v e
VIN
LIMITS
1=2SoC
2=8SoC
3=_40°C
TEMP
0
SUFFIX
-40 to 85°C
TYpd
MIN b MAXb
UNIT
INPUT
~8W Current with VIN
IlL
VIN Under Test = 0.8 V
All Other = 2.4 V
1,2
-0.5
0.5
Input Current with VIN
HIGH
IIH
VIN Under Test = 2.4 V
All Other = 0.8 V
1,2
-0.5
0.5
JJ.A
DYNAMIC
Turn-ON Time
Turn-OFF Time
Charge InJectlon C
tON
tOFF
Q
RL=1 k.n., CL=5pF
See Figure 1
Vs = ±10 V
C L = 10 nF, Vs = 0 V
Vgen = 0 V, Rgen = 0 .n
1
160
1
80
ns
1
-10
10
pC
SUPPLY
Positive Supply Current
1+
1
2
Negative Supply Current
1-
1
2
Logic Supply Current
IL
1
2
IGNO
1
2
Ground Current
V+ = 16.5 V, V- = -16.5 V
VIN = 0 or 5 V
1
5
-1
-5
(UNIPOLAR SUPPLY)
Test Conditions
Unless Otherwise Specified:
SYMBOL
-1
-5
JJ.A
ELECTRICAL CHARACTERiStics a
PARAMETER
1
5
V+ = 12 V
V- = 0 V
VL = 5 V
GND = 0 V
VIN = 2.4,0.8 Va
LIMITS
1=25°C
2=8SoC
3=_40 oC
TEMP
0
SUFFIX
-40 to 85°C
TYP d MIN b MAX b
UNIT
0
12
V
160
200
.n
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
5-276
VANALOG
rOSION)
Is = -10 mA,
V+ = 10.8 V,
Vo = 3 V, 8 V
V L = 5.25 V
1
2,3
Preliminary
DG444/445
Siliconix
incorporated
(UNIPOLAR SUPPLY)
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
SYMBOL
PARAMETER
V+ = 12 V
V- = 0 V
VL = 5 V
GND = 0 V
VIN = 2.4,0.8 Va
LIMITS
1=25·C
2=85·C
3=-40·C
TEMP
0
SUFFIX
-40 to 8SoC
TVP d MIN b MAX b
UNIT
DYNAMIC
Turn-ON Time
tON
Turn-OFF Time
tOFF
R L = 1 k.n., C L = 35 pF
See Figure 1
Vs = B V
1
400
1
200
ns
Q
CL - 10 nF, VL - 5.25 V
Vgen = 6.6 V, Rgen = 0
V+ = 13.2 V
1
Positive Supply Current
1+
V+ = 13.2 V
VIN = 0 or 5 V
1
2,3
Negative Supply Current
1-
VIN = 0 or 5 V
1
2,3
IL
V L = 5.25 V
VIN = 0 or 5 V
1
2,3
IGNO
VIN = 0 or 5 V
1
2,3
Charge InJectlon C
.n
-40
40
pC
SUPPLY
1
5
-1
-5
,JJ.A
Logic Supply Current
Ground Current
1
5
-1
-5
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
SWITCHING TIME TEST CIRCUIT
Vo Is the steady state outrut with the switch ON. Feedthrough via switch capacitance may result In spikes at the
leading and trailing edge 0 the output waveform.
LOGIC 3.0V
INPUT
oV
SWITCH
INPUT
Vs
~ ::::~::
J
50%~
SWITCH
INPUT
r-......--~.....,01
Vo
S10+----o1 "'--+-'--1:_-.
1'J.. tOFF
-'tV;;-;;::;::;:=.==;t3.0V
SWITCH 0 V
OUTPUT
NOTE:
Repeat test for Ch 2, 3, 4
For load conditions, See Electrical Characteristics
'1. (includes fixture and stray capacitance)
Vo = Vs
RL
---=---RL + 'OS(ON)
Preliminary
5-277
DG444/445
.... Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
V+
RGEN
-=-
1
Va
01
VGEN
1~
VIN =3.0V
ON
OFF
ON
OFF
Q=l!.voc L
I N x dependent on switch configuration
Input Polarity determined by sense of switch
BURN-IN CIRCUITS
-15V
-15 V
1:1--+-+-0
P--+-+-o
DG444
0--+-+-0 +15 V
P--+-+-o +5 V
+15 V
+5 V
+15 V
DG445
Note: All Resistors are 10 kll. unless otherwise specified
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+ o---~------------------~--------~----~------~------.
NXo---~-----------i
GNO'o----r--------------~--~~----~
V-o---~----------------------------------+-------~------~----------~
5-278
Preliminary
DG444/445
trY' Siliconix
~
incorporated
CROSSTALK TEST CIRCUIT
+15V
Signal
Generator 0.0 dBm
FREQUENCY
TESTED
100 Hz to
13 MHz
Analyzer I----I_--A,...-f-=------'.....--+--o
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
-15 V
OFF ISOLATION TEST CIRCUIT
+15 V
FREQUENCY
TESTED
- ±4000 V
DESCRIPTION
The DG480 is an analog switch array configured as
an 8-channel multiplexer for use in serial input data
applications.
Combining low ON resistance
(rDS(ON) < 100 0) and fast switching (tOFF
< 200 ns) the DG480 is ideally suited for data
acquisition, process control, communication, and
avionic applications. Any, all or none of the 8
switches may be closed at any given time.
This device loads the input data serially into the
input shift register with each clock pulse. The state
of the shift register can be latched via LD at any
point into an address register which holds the logic
function to control the array. An RS pin resets all
the latches to a LOW condition. A serial output
terminal DOUT allows chaining of arrays for larger
matrix systems.
The DG480 is built on Siliconix high voltage silicon
gate process to achieve high voltage ratings and
superior switch ON/OFF performance. An epitaxial
layer prevents latchup.
Each channel conducts equally well in either
direction when ON and blocks up to 30 volts
peak-to-peak when OFF. ON resistance is very flat
over the full ±15 V analog range, rivaling JFET
performance without the inherent dynamic range
limitation.
Packaging for the DG480 consists of the 18-pin
CerDIP and plastic DIP packages. Temperature
ranges available are military, A suffix (-55 to
125°C) and industrial, 0 suffix (-40 to 85°C).
PIN CONFIGURATION
Dual-In-Llne Package
Top View
Order Numbers:
CerDIP: DG4BOAK, DG4BOAK/BB3
Plastic: DG4BODJ
5-282
Preliminary
~
DG480
Siliconix
..cII incorporated
FUNCTIONAL BLOCK DIAGRAM
...
r r
r
!
....-:.
~
I
I
I
I
Lll
V-
GND
V+
.........
D
~
I
I
I
....
I
I
121 L3: L4: Ls! La l L71 Ls:
J
I--
OCTAL LATCH
011
DaII4I
~I
-
Dsl Osl D71 Dsl
SHIFT REGISTER
CLK
LD
DoUT
TRUTH TABLES
RS
1
1
1
0
CLK'
DIN
Dl
DN
0
0
DN-l
1
1
DN-l
X
Dl
X
0
LD'
f
f
'X
DN
(NO CHANGE
0
f
f
'-
DN
LN
SWN
0
0
OFF
1
1
ON
DN
LN
(NO CHANGE)
'CLK and LD Inputs are Level Triggered
ABSOLUTE MAXIMUM RATINGS
V+ to V- .•......•............................ 44 V
GND to V- . . . • • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 V
Digital Inputs Vs. Vol. . . . . . . . .. (V-) -2 V to (V+)+ 2 V
. . . . . . . . . . . . . . . • • . . •• or 30 mAo whichever occurs first
Continuous Current (Any Terminal) ..•........... 30 mA
Power Dissipation (Package)'
18-Pln CerDIP" ..........•................. 600 mW
18-Pln Plastic DIP'" ....••...•......•....... 470 mW
All leads welded or soldered to PC Board .
Derate 9.2 mW/·C above 75·C.
Derate 16.5 mW/·C above 25·C.
Current. S or D (Pulsed 1 ms. 10% duty cycle) .. 100 mA
Storage Temperature (A Suffix) .....•.... -65 to 150·C
(D Suffix) .......... -65 to 125·C
Operating Temperature (A Suffix) ......... -55 to 125·C
(D Suffix) .......... -40 to 85·C
Preliminary
Signals on Sx. Dx. or INx exceeding V+ or V- will be
clamped by Internal diodes. Limit forward diode
current to maximum current ratings.
5-283
DG480
. . . . Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified: 1=25°C
2=125,85°C
V+ = 15 V, V- = -15 V
3=-55,-40°C
GND = 0 V
PARAMETER
VIN = 2.0 V, 0.8 VB
SYMBOL
TEMP TYpd
LIMITS
A
SUFFIX
55 to 125°C
MINb MAX'
D
SUFFIX
-40 to 85°C
MINb MAXb UNIT
SWITCH
Analog Signal Range
C
Drain-Source ON
Resistance
Delta Drain-Source ON
Resistance
-15
VANALOG
15
-15
15
V
rOS(ON)
Is = -10 mA, VO= ±10 V
V+ = 13.5 V, V- = -13.5 V
1,3
2
75
100
75
100
.n
IIrOS(ON)
"rOS(ON) rOS(ONl MAX - rOS(ON) MIN
rOS(ON) AVG
1
10
10
%
IS(OFF)
V+ = 16.5 V, V- = -16.5 V
Vo= -14 V, Vs= 14 V
Vo= 14 V, Vs= -14 V
Switch OFF Leakage
Current
IO(OFF)
1
2
-1
-20
1
20
-1
-20
1
20
1
2
-10
-200
10
200
-10
-200
10
200
IO(ON) +
IS(ON)
V+ = 16.5 V, V- = -16.5 V
Vs = Vo = ±14 V
1
2
-20
-500
20
500
-20
-500
20
500
Input Current with VIN
Low
IlL
VIN under test = 0.8 V
all other = 2.0 V
1
2
-1
-5
1
5
-1
-5
1
5
Input Current with VIN
High
IIH
VIN under test = 2.0 V
all other = 0.8 V
1
2
-1
-5
1
5
-1
-5
1
5
VOL
VIN under test = 0.8 V
all other = 2.4 V
1,2
Channel ON Leakage
Current
nA
INPUT
Il A
OUTPUT
Output Voltage with VIN
Low - SO
0.4
0.4
V
,
DYNAMIC
Pulse Width for
Logic
tLOGIC
(DIN' LD, CLK, RS)
See Figure
1
2
Transition Time
tTRAN
RL= 1 M.n, C L = 35 pF
V Sl = 10 V, V S2 = -10 V
50% of V LO to 90% of Vo
See Figure
1
2
Data Setup Time
tow
1
80
150
80
150
200
250
50
200
250
50
ns
Break-Before-Make
tBREAK
Turn-ON Time
tON
Turn-OFF Time
tOFF
5-284
RL= 1 k.n, C L = 35 pF
V S1 =VS2 = 10 V
90% of Vo to 90% of Vo
See Figure
50% of LD, RS to 90% of Vo
RL= 1 k.n, C L = 35 pF
See Figure lA
1
2
10
20
10
20
1
2
200
250
200
250
1
2
150
200
150
200
Preliminary
DG480
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified: I_25°C
2=125,85°C
V+ = 15 V, V- = -15 V
3=-55,-40°C
GND = a V
VIN = 2.0 V, 0.8 Va
SYMBOL
PARAMETER
TEMP TYpd
LIMITS
A
SUFFIX
55 to 125°C
MINb MAX'
D
SUFFIX
-40 to 85°C
MINb MAXb UNIT
DYNAMIC (Cont'd)
a V,
1
40
pC
1
-65
dB
1
7
1
55
CS(ON) +
COlON)
1
200
Positive Supply Current
1+
1,2,3
Negative Supply
Current
1-
Ground Current
IGNO
Charge Injection
Vs=
Q
C L = 1000 pF
RL = 50.0., C L = 5 pF
f = 1 MHz
OFF Isolation
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Drain and Source ON
Capacitance
Vgen =
a V, Rgen = 0.0.
f = 1 MHz
pF
SUPPLY
V+ = 16.5 V, V- = -16.5 V
VIN = a or 5 V
100
100
1,2,3
-1
-1
1,2,3
-100
-100
j.l.A
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
INPUT TIMING REQUIRMENTS
J
C=-\
I
I
I,
\
/
\
t-- ---i
LDj
I
r-- tLOGIC
I
\
I
-I·
I
I
I
\
/
~
tLOGIC~
I
= for CLK and LD Inputs of the same frequency
The recommended phase delay of LD from CLK
Is 1/2 t LOGIC to t LOGIC
t LOGidMIN) : 80 ns at 25°C
150 ns at 125°C
Preliminary
V+ = +15 V
V- = -15 V
GND = a V
5-285
..
wr Siliconix
incorporated
DG480
~
INPUT TIMING REQUIRMENTS (Cont'd)
SHIFT REGISTER SETUP
DAT_A______
-J~~------~---------
OlK________
DATA TO OlK
J;rr--------
~r______
t 30 ns at 25·0
50 ns at 125·0
j
As
------'
I
~I'------~"r_-------
O~lK~______I ____
__J1'
Ast TO OlK t 30
ns at 25°0
50 ns at 125·0
SHIFT REGISTER HOLD
DATA
----'1
DATA FROM CLKt 30 ns at 25·0
50 ns at 125°0
ADDRESS REGISTER SETUP
1
OLK
As
I_--------~.I
lD
1----
"
________________
-JI
\
======:::::r-I- -
j;Io
lD __________I________~~~----
As , TO LOt
OlK t TO LOt 30 ns at 25·C
50 ns at 125°0
30 ns at 25 °0
60 ns at 125·0
ADDRESS REGISTER ENABLE
1
OlK
I.
I
LO
As
T\
t
1'------
=
=-
5-286
I,
lD
I
As' TO LO'
OLK TO LO' 100 ns at 25·0
150 ns at 125·0
V+ +15 V. V15 V. GND
INPUTS ARE 0 V TO 3 V
\
.'
'1
/
100 ns at 25°0
150 ns at 125°0
=0 V
Preliminary
...r incorporated
Siliconix
DG480
~
TIMING DIAGRAM
RS
u
.J
DIN
elK
lD
Sl
S2
S3
____-F--------IL____
L -________~~~_ _ _ __ _
S4
S5
________
~~
______
--l----~L-
_______
~
____
S6
S7
Sa
--------______
~rrL
________________
~
DOUT _ _ _ _ _ _ _ _ _-.1
S 1- Sa and DOUT are expected output with the drain connected high.
The sources require pull-downs of 1 k.n. •
Preliminary
5-287
DG485
Low-Power - High-Speed
CMOS Octal Analog Switch Array
rJr Siliconix
.1;11 incorporated
FEATURES
BENEFITS
APPLICATIONS
• ± 15 Volt Input Range
• Low Signal Distortion
• Audio Switching and Routing
• ON Resistance < 100 il
• Reduced Switch Errors
• Precision Switching
• Serial Data Input/Output
• Devices Can Be Chained
For System Expansion
• Serial Data Acquisition
and Process Control
• TIL and CMOS Compatible
• Reduced Power Supply
• Battery and Remote
Systems
• Any Combination of
8 SPST to the
Output
• Simple Interfacing
• Low Power (Po < 35 IlW)
• Automotive, Avionics and
ATE Systems
• ESDS Protection> ±4000 V
DESCRIPTION
The DG485 is an analog switch array configured as
a low power 8-channel multiplexer for use in serial
input applications. Combining low ON resistance
(rDS(ON) < 100 il) and fast switching (tOFF
< 200 ns), the DG485 is ideally suited for data
acquisition, process control, communication, and
avionic applications. Any, all or none of the 8
switches may be closed at any given time.
This device loads the input data serially into the
input shift register with each clock pulse. The state
of the shift register can be latched via LOAD at any
point into an address register which holds the logic
function to control the array. An RS pin resets all
latch inputs to a LOW condition. A serial output
terminal (DOUT) allows chaining of arrays for larger
matrix systems.
Built on the Siliconix high voltage silicon gate
process the DG485 has a wide 44 V range. An
epitaxial layer prevents latchup.
Each channel conducts equally well in either
direction when ON and blocks up to 30 volts
peak-to-peak when OFF. ON resistance is very flat
over the full ±15 V analog range, rivaling JFET
performance without the inherent dynamic range
limitation.
Packaging for the DG485 consists of the 18-pin
CerDIP and plastiC DIP. Temperature ranges
available are military, A suffix (-55 to 125 D C) and
industrial, 0 suffix (-40 to 85 D C).
PIN CONFIGURATION
Dual-ln-L1ne Package
Top View
Order Numbers:
CerDIP: DG4B5AK, DG4B5AK/BB3
Plastic: DG485DJ
5-288
Preliminary
DG485
trY' Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
V-
i i- 1 i
GND
V+
I
~
...-:.
D
/.
I
I
L1 I
I ......:.
I
I
I
I
I
I
1.21 13j L4j Ls: L6
! L71
La:
,-
OCTAL LATCH
~l I>f MINb MAXb UNIT
va
DYNAMIC (Cont'd)
1
2
200
250
200
250
1
2
150
200
150
200
Vs= 0 V, C L = 1000 pF
1
60
60
RL=50.o., CL=5pF
f = 1 MHz
1
-65
1
7
1
55
CS(ON) +
CO(ON)
1
200
Positive Supply Current
1+
1,2
Negative Supply
Current
1-
1,2
Logic Supply Current
IL
Turn-ON Time
tON
Turn-OFF Time
tOFF
Charge Injection
Q
OFF Isolatlon C
Source-OFF Capacitance C
CS(OFF)
Drain-OFF Capacitance C
CO(OFF)
Drain and Source ON
Capacltance C
50% of LD, RS to 90% of Vo
RL= 1 k.o., C L = 35 pF
See Figure lA
Vgen = 0 V, Rgen = 0.0.
f = 1 MHz
ns
pC
dB
pF
..
SUPPLY
Ground Current
laNo
V+ = 16.5 V, V- = -16.5 V
VIN=00r5V
VL = 5.25 V
1
-1
1
-1
IlA
1.2
1,2
1
-1
1
-1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
Preliminary
5-291
DG485
W"lI' Siliconix
~
incorporated
INPUT TIMING REQUIRMENTS
\'---'" = for CLK and LD Inputs of the same frequency
The recommended phase delay of LD from CLK
Is 112 t LOGie to t LOGie
V+ = +15 V
t LOGle(MIN) : 80 ns at 25°C
V- = -15 V
150 ns at 125°C
GND 0 V
=
SHIFT REGISTER SETUP
DATA
X
,
,"I
eLK
DATA TO eLK , 30 no at 25·e
50 no at 125·e
I
As
------'~
t
I
~I·------~·Ir--------
-JJ'
e_LK_ _ _ _ _
' __
As'
TO eLK' 30 no at 25·e
50 ns at 125°C
SHIFT REGISTER HOLD
X
DATA
I.
II
--~====L''---==
_----J~
DATA FROM eLK' 30 no at 25·e
50 no at 125·e
ADDRESS REGISTER SETUP
eLK
I
RS
1oo"_ _ _ _ _ _ _ _ _~.1
i
LO
yr---
\.
~I"~=======:"fl-----
LO __________I___________ ~r---
----------------~I
eLK' TO LO' 30 no at 25·e
60 no at 125·e
As'TO LO' 30 ns at 25·e
50 ns at 125·e
ADDRESS REGISTER ENABLE
eLK
I
I-
LO
.1
11\
1'-----
eLK' TO LO' 100 ns at 25·e
160 ns at 125·e
'1
LO
I /
As' TO LO' 100 ns at 25·e
150 ns at 125·e
V+ = +15 V, V- = - 15 V, GND = 0 V
INPUTS ARE 0 V TO 3 V
5-292
Preliminary
DG485
WY'Siliconix
incorporated
~
TIMING DIAGRAM
u
As .J
DIN
elK
lD
81
82
83
____-F--------IL____
~~
________
L -________~~~_ _ _ __ _
84
85 ------~~--~L-_ _ _ _ _ _ _~L___ _
86
87
8a
______________
~rtL
________________
~
DoUT ----------------~
81- 8 8 and DOUT are expected output with the drain connected high.
The sources require pull-downs of 1 k.n .
Preliminary
..
5-293
WY Siliconix
DG501
a-Channel Multiplex
Switch with Decode
,.1;11 incorporated
FEATURES
BENEFITS
APPLICATIONS
• Break-Before-Make
Switching
• Reduced System
Cross-Talk
• Multiplexing ±5 V
Analog Signals
• Pull-Up Resistors on Inputs
• Easily Interfaced to TIL
• Data Acquisition Systems
• Bi-Directional Signal
Handling
DESCRIPTION
Designed for applications where single-ended,
Break-Before-Make switching action is required, the
DG501 is an 8-channel analog multiplexer that is
capable of handling bi-directional signals up to
±5 V. In addition, an ·OFF" state can be activated
by using a chip enable signal. In" the OFF state, this
device can block up to 10 V peak-to-peak signals.
An on-chip decoder accepts a 3 bit binary word
which enables the seleciton of anyone of the eight
analog switches to be turned on individually. Pull-up
resistors are provided at each logic input to simplify
TIL interface. This device is available in either a
16-pin plastic or ceramic DIP and is available in
commercial, C suffix (0 to 70°C), industrial, B suffix
(-25 to 85°C) and military, A suffix (-55 to 125°C)
temperature ranges.
PIN CONFIGURATION
TRUTH TABLE
LOGIC INPUTS
Dual-In-Une Package
Top View
Order Numbers:
Side Braze: DG501AP, DG501BP.
Plastic: DG501CJ
CHANNEL
Ao
L
A1
L
A2
L
EN
H
'ON'
Sl
H
L
L
H
S2
L
H
L
H
S3
H
H
L
H
S4
L
L
H
H
S5
H
L
H
H
S6
L
H
H
H
S7
H
H
H
H
Sa
X
X
X
L
OFF
Logic Levels'
LOW: VL = VLOW < 0.6 V
HIGH:VH = VHIGH > 3.5 V
*
5-294
Both V+ lines are Internally connected. either one
or both may be used. V+ common to substrate.
• For supply'voltages of 5 V and -20 V
Not Recommended for New Designs
DG501
WY'Siliconix
incorporated
~
FUNCTION BLOCK DIAGRAM
SIGNAL INPUTS
EN
LOGIC
INPUTS
Ao
20
20
Al
D
"1
21
A2
22
22
SIGNAL INPUTS
ABSOLUTE MAXIMUM RATINGS
V+ to V- .....................••.••........... 3D V
V- to V+ .................................... -0.3 V
V+ toVA, VEN .......•......................... 30V
VA' VEN to V+ ................................ -0.3 V
V+ toVo orVs .....••......................... 3D V
Vo Vs to V+ •.••..•......••••..••.•.......•..• -0.3 V
Vo toYs ............•••.••..........••....... ±25 V
VA,VENtOV- .......•••.•...........••........ 30V
VoorVstoV- ......•.............•.•........ 30V
Current, (Any Terminal) •..........•..••...... -20 mA
Storage Temperature (A & 8 Suffix) ....... -65 to 150°C
(C Suffix) .•....•.... -65 to 125°C
Operating Temperature (A Suffix) •••••.... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
(C Suffix) ..........•. 0 to 70°C
Power Dissipation"
16-Pln Ceramic DIP"" ••.••••..•......••.••..• SOD mW
l6-Pln Plastic DIP""" ........................ 470 mW
Device mounted with all leads welded or soldered to
PC board.
Derate 12 mW'oC above 7SoC.
""" Derate 6.S mW'oC above 2SoC.
Not Recommended for New Designs
5-295
DG501
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specilied:
PARAMETER
SYMBOl.
V+ = 5 V, V- = -20 V
V EN =3.5V
V AL =0.6V
V AH = 3.5 V
l.IMITS
1=25°C
A
2=125,85,70°C
SUFFIX
3=-55,-25,0°C -55 to 125°C
TEMP
Analog Signal Range c
,
-5
1,2,3
VANALOG
I s =-100JJ.A
V- = -15 V
Drain-Source
ON Resistance
MINb MAXb MINb MAXt UNIT
TYpd
SWITCH
B,C
SUFFIX
5
-5
5
VD= 5 V
1,3
2
75
200
300
200
300
VD= 0 V
1,3
2
97
250
375
250
350
V D = -5 V
1,3
2
140
600
900
800
900
VD= 5 V
1,3
2
65
150
225
150
200
VD= 0 V
1,3
2
80
200
300
200
300
V D = -5 V
1,3
2
100
250
375
250
350
V
.0,
rDS(ON)
Is=-l mA
V- = -20 V
Source OFF
l.eakage Current
IS(OFF)
V s =-5V, V D =5V
V EN = 0.6 V
1
2
-0.005
-1
-1000
-3
-150
Drain OFF
l.eakage Current
ID(OFF)
VD=-5V,Vs=5V
V EN = 0.6 V
1
2
-0.07
-6
-4000
-10
-500
Channel ON
l.eakage Current
ID(ON)+
IS(ON)
V D =Vs =5V
1
2
0.1
VAL = 0
1
0.8
IINH
V AH =3.5V
1
-150
-150
1
1.5
2
tTRANS
See Switching Time
V- = -20 V
Test Circuit
V S1 = ±1 V
Vss= +1 V
V S2 thru V S? = 0 V V- = -15 V
1
2.5
3
6
4000
nA
10
500
INPUT
Logic Input Current
Input Voltage l.OW
l.ogic Input Current
Input Voltage HIGH
IINL
-1.2
-1.2
mA
JJ.A
DYNAMIC
Switching Time
Break-Belore-Make
Interval
tOPEN
Turn-ON Time
tON
Turn-OFF Time
tOFF
5-296
See Switching Time
Test Circuit
VS(AII) = 1 V
1
0.05
1
1.2
1
0.6
JJ.s
Not Recommended for New Designs
~
~
DG501
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
SYMBOL
PARAMETER
V+ = 5 V, V- = -20 V
VEN=3.5V
VAL = 0.6 V
V AH =3.5V
LIMITS
1=25°C
A
2=125,85,70°C
SUFFIX
3=-55,-25,0°C -55 to 125°C
EMP
TYpd
See Switching Time
Test Circuit
VS(AII) = 1 V
V- = -15 V
1
2
1
0.8
Vs=Vo= 5 V
V EN = 0.6 V
f = 1 MHz
1
10
1
20
1
-2.6
B, C
SUFFIX
MINb MAXb MINb MAXt UNIT
DYNAMIC (Cont'd)
Turn-ON Time
tON
Turn-OFF Time
tOFF
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CO(OFF)
Jls
pF
SUPPLY
Drain Supply Current
1-
Source Supply Current
1+
1
5.6
Drain Supply Current
1-
1
-2.4
Source Supply Current
1+
1
4.9
V EN = 0 V
VAL(AII) = 0 V
-6
-6
8
8
mA
V EN = 3.5 V
VAL(AII) = 0 V
-6
-6
7
7
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SWITCHING TIME TEST CIRCUIT
S1
INPUT
5V
S2
S3
va
s4
VS2-7
s5
va
S6
S7
Sa
V sao--<>!'-II-----.:-
Al
I
I
.d.
CMOS DECODE LOGIC
!
I
I
~
?
~
I
I
I
I
I
~I
A3
1-
I
d
- 2.4 V
tTRANS
DG506A1507A
..... Siliconix
incorporated
~
tON(EN) AND tOFF(EN) TIME TEST CIRCUIT
SWITCH
OUTPUT
Vo
3V
LOGIC
INPUT
50%
tr<:20 ns
If <20 ns
50%
OV
-=-
-=- -=-
-=-
IOFF(EN)
I ON (EN
OV
O. IVa
+15 V
SWITCH
OUTPUT
Vo
A2
Va
AI
,-=-
AO
SWITCH
OUTPUT
Vo
-=- -=Figure 2
_---.J/
\
tr<:20ns
t1<20n5
'----
SCHEMATIC DIAGRAM
V+o-~----~--~------~~--------------~
CaMP
LOGIC
TRIP- 1--1-_ _-1
POINT
REF
GNDo-----.l---...J
LOGIC A x o----IVVv---"-....l
INPUT or
EN
~---T----~--4--osx
DECODER
Ax
L-----~--~~-----oDX
V-o-----~----------~------------~----------~
LOGIC INTERFACE
AND LEVEL SHIFTER
TYPICAL
SWITCH
5-311
DG506A1507A
...... Siliconix
incorporated
~
APPLICATION HINTS*
V+
Positive
Supply
Voltage
(V)
VNegative
Supply
Voltage
(V)
15 ••
-15
12
-12
10
8 ***
VIN
Logic Input
Voltage
VINHMinl
VINLMax
(V)
Vs or Vo
Analog
Voltage
Range
(V)
-15 to 15
-10
2.4/0.S
2.410.6
2.4/0.5
-S
2.4/0.3
-S to S
-12 to 12
-10 to 10
• Application Hints are for DESIGN AID ONLY, not guaranteed and
not subject to production testing.
•• Electrical Characteristics chart based on V+ = +15 V, V- = -15 V .
••• Operation below ±S V is not recommended due to the shift in VINL(MAX).
Overvoltage Protection
A very convenient form of overvoltage protection
consists of adding two small signal diodes (1 N414S,
1N914 type) in series with the supply pins (see
figure). This arrangement effectively blocks the
flow of reverse currents. It also floats the supply pin
above or below the normal V+ or V- value. In this
case the overvoltage signal actually becomes the
power supply of the IC. From the point of view of
the chip, nothing has changed, as long as the
difference Vs - (V-) doesn't exceed +44 V. The
addition of these diodes will reduce the analog
signal range to 1 V below V+ and 1 V above V-, but
it preserves the low channel resistance and low
leakage characteristics.
5-312
lN4148
V+ S Vg S V-
---+--uo
VOvervoltage Protection Using Blocking Diodes
DG506A1507A
...r'Siliconix
incorporated
~
APPLICATIONS
CHANNEL 16
CHANNEL 17
CHANNEL 1
DGS06A
# 1
A3
A3
A2
A2
A1
A1
AO
CHANNEL 48
CHANNEL 33
CHANNEL 32
DGS06A
#2
D
v+
A3
A3
A2
A2
A1
A1
EN AO
Ao
CHANNEL 49
DGS06A
#3
A3
A3
A2
A2
A1
A1
AO
v+
CHANNEL 64
DG506A
#4
D
v+
EN
v+
S18601
BUS
DATA
CONTROL
ADDRESS
BUS
DATA
CONTROL
ADDRESS
MICROPROCESSOR
64-Channel 2-Level Multiplex System
5-313
DGP508A
Precision 8-Channel
CMOS Multiplexer/Demultiplexer
...... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Fully Tested Around
± 10.8,±16.5 and ± 20 V
Supplies
• Simplifies Worst-Case
Analysis
• Automatic Test Equipment
• Reduces Channel-to-Channel
Variations
• Precision Data Acquisition
• 10% (Max.) delta rDS(ON)
• 2.0 nA (Max.) Leakage
at 25°C, ±16.5 V
• Reduces Switching Errors
• Low Charge Injection
(Q < 15 pC)
• Simplifies Upgrading
• Communication Systems
• Precision Instrumentation
• Upgrading Old Designs
• Reduces Switching Noise
• Pin-Compatible with
DG508A
DESCRIPTION
The DGP508A is a precision 8-channel CMOS
analog multiplexerfdemultiplexer which is specified
with improved static and dynamic performance
limits. The DGP508A features tighter leakage and
delta rDS(ON) limits and wider analog signal ranges
than the industry-standard DG508A, yet maintains
100% pin and functional compatibility. This allows
for precision system performance upgrading
without redesign or layout of circuit boards. In
addition, the specification limits and associated test
conditions are in a military drawing format,
simplifying source-control documentation and
ensuring performance based upon a worst-case
analysis. Refer to the "Detailed Description" for
more information on the "DGP" family.
Produced on a proprietary high-voltage CMOS
process, the DGP508A has been fully specified for
signals up to ±20 V, making it an ideal choice for
extended range operation, or in systems with
additional headroom 'requirements. An epitaxial
layer prevents latchup.
PIN CONFIGURATION
TRUTH TABLE
The DGP508A is available in a 16-pin plastic DIP for
the industrial, D suffix (-40 to 85°C) temperature
range and the CerDIP for military (available with
f883 processing) , A suffix (-55 to 125°C)
temperature operation.
For more information on the DGP508A, please refer
to Siliconix Technical Article TA87-1.
Dual-In-Llne Package
Order Numbers:
CerDIP:
DGP50BAAK
DGP50BAAK/BB3
Plastic:
DGP50BADJ
Top View
5-314
ON
SWITCH
NONE
A2
Al
Ao
EN
X
X
X
0
0
0
0
1
1
0
0
1
1
2
0
1
0
1
3
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
B
Logic '0"
Logic "1"
= VAL
= VAH
< O.B V
> 2.4 V
DGP508A
flY' Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
v+
v-
GNO
51
S2 o-~---------o"1
53
0-11---------<>'1 ....-+---+---.
55
0-1-------0'1 ....-I---I--L-_+
o-li------<>'1 ....-t--+----.J'-7--+
S6
CH~---o~ A-r~,-+--+-r__+
S4
o
S7 U-1----O'1 A-l--1f--+-+-..,---.---"
S8
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to VV+ ........................................... 44 V
GND ......................................... 25 V
Digital Inputs V 5 , V 0 1 ........... (V-) -2 V to (V+) +2 V
Operating Temperature (A Suffix) ......... -55 to 125°C
(D Suffix) .......... -40 to 85°C
Power
16-Pln
16-Pln
16-Pln
. . . . . . . . . . . . . . . . . . . .. or 30 mA, whichever occurs first
Current (Any Terminal) Continuous .............. 30 mA
Current (S or D) Pulsed 1 ms 10% duty ......... 100 mA
Storage Temperature (A Suffix) .......... -65 to 150°C
(D Suffix) .......... -65 to 125°C
Dissipation (Package)·
Plastic DIp·· ......................... 450 mW
CerDIP··· ........................... 900 mW
Small Outline .. •• ..................... 900 mW
All leads welded or soldered to PC board.
Derate 6 mW/oC above 75°C.
Derate 12 mW/oC above 75°C.
Derate 7.7 mW/oC above 75°C.
Signals on Sx ,Dx or IN x exceeding V+ or V- will be
clamped by Internal diodes. Limit forward diode current
to maximum current ratings.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VAH = 2.4 V, VAL = 0.8 V
VEN = 2.4 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40°C -55 to 125°C
TEMP TYpd
D
SUFFIX
-40 to 85°C
MINb MAXb MINb MAXb UNIT
SWITCH
Drain-Source e
ON Resistance
Delta Drain-Source e
ON ReSistance
rOSION)
fl.
rOSION)
V+ = 13.5 V, V- = -13.5 V
15=1 mA, Vo =±10.0V
1,3
2
265
400
500
400
500
V+ = 10.8 V, V - 10.8 V
15=1 mA, Vo =±7.5V
V IN = 0.4 V
1,3
2
300
450
550
450
550
V+ = 20 V, V- = -20 V
15=1 mA, Vo=±15V
1,3
2
200
350
450
350
450
Vo - +5,0, -5 V, 15 - ±1 mA
VIN = 0.8 V
Worst Combination
1
2,3
20
40
50
40
50
.n.
5-315
DGP508A
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND=OV
VAH = 2.4 V, VAL = 0.8 V
VEN = 2.4 V
LIMITS
1=25·C
A
0
2=125,85·C
SUFFIX
SUFFIX
3=-55,-40·C -55 to 125°C -40 to 85°C
TEMP TYpd
MINb MAXi
MINb MAXb UNIT
SWITCH (Cont'd)
V+ = 13.5 V
V- = -13.5 V
V+ = 16.5 V
V- = -16.5 V
Source OFF
Leakage Current
IS (OFF)
V+ = 20 V
V- = -20 V
-0.25
-10
0.25
10
-0.25
-2
0.25
2
Vo = +12.5 V
Vs = -12.5 V
1
2
-0.01
-0.25
-10
0.25
10
-0.25
-2
0.25
2
Vo = -15.5 V
Vs = +15.5 V
1
2
0.01
-0.25
-10
0.25
10
-0.25
-2
0.25
2
Vo = +15.5 V
Vs = -15.5 V
1
2
-0.01
-0.25
-10
0.25
10
-0.25
-2
0.25
2
Vo = -19 V
Vs = +19 V
1
2
0.03
-1
-50
1
50
-1
-10
1
10
Vo = +19 V
V s =-19V
1
2
-0.03
-1
-50
1
50
-1
-10
1
10
-5
5
-2
2
Vo = +5 V
Vs = -5 V
2
-5
5
-2
2
Vo = -12.5 V
Vs = +12.5 V
1
2
0.08
-2
-100
2
100
-2
-20
2
20
Vo = +12.5 V
Vs = -12.5 V
1
2
-0.08
-2
-100
2
100
-2
-20
2
20
Vo = -15.5 V
Vs = +15.5 V
1
2
0.10
-2
-100
2
100
-2
-20
2
20
Vo = +15.5 V
Vs = -15.5 V
1
2
-0.10
-2
-100
2
100
-2
-20
2
20
Vo = -19 V
Vs = +19 V
1
2
0.25
-5
-200
5
200
-5
-50
5
50
Vo = +19 V
V s =-19V
1
2
-0.25
-5
-200
5
200
-5
-50
5
50
nA
IO(OFF)
V+ = 20 V
V- = -20 V
Vo = -5 V
Vs = +5 V
2
-50
50
-20
20
Vo = +5 V
Vs = -5 V
2
-50 .
50
-20
20
V+ = 16.5 V
V- = -16.5 V
IO(ON)+
IS(ON)
V+ = 20 V
V- = -20 V
5-316
0.01
2
V+ = 16.5 V
V- = -16.5 V
Channel ON"
Leakage Current
1
2
Vo = -5 V
Vs = +5 V
V+ = 13.5 V
v- = -13.5 V
Drain OFF
Leakage Current
Vo = -12.5 V
Vs = +12.5 V
Vo = +15.5 V
Vs = +15.5 V
1
2
0.10
-2
-100
2
100
-2
-20
2
20
Vo = -15.5 V
Vs = -15.5 V
1
2
-0.10
-2
-100
2
100
-2
-20
2
20
Vo = +19 V
Vs = +19 V
1
2
0.25
-5
-200
5
200
-5
-50
5
50
Vo = -19 V
V s =-19V
1
2
-0.25
-5
-200
5
200
-5
-50
5
50
DGP508A
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VAH = 2.4 V, VAL = 0.8 V
VEN = 2.4 V
IO(ON)+
Vo = +5 V
Vs = +5 V
2
-50
50
-20
20
Vo = -5 V
Vs = -5 V
2
-50
50
-20
20
LIMITS
1=25·C
A
2=125,85·C
SUFFIX
3=-55,-40·C -55 to 125 Q C
TEMP TYpd
0
SUFFIX
-40 to 85 Q C
MINb MA'if MIN1MAXb
UNIT
SWITCH (Cont'd)
Channel ONe
Leakage Current
(Continued)
IS(ON)
nA
SUPPLY
1,2
3
1.3
2.4
3
2.4
3
1,2
3
1.3
2.4
3
2.4
3
1,2
3
-0.65
-1.5
-2
-1.5
-2
1,2
3
-0.65
-1.5
-2
-1.5
-2
V+ = 20 V, V- = -20 V
VINunder test = 2.4 V
1,2
-0.001
-0.5
0.5
-0.5
0.5
V+ = 20 V, V- = -20 V
V IN under test = 20 V
1,2
0.004
-0.5
0.5
-0.5
0.5
V+ = 20 V, V- = -20 V
VIN under test = 0 V
1,2
0.01
-0.5
0.5
-0.5
0.5
1,3
2
750
1000
1500
1000
1500
1,3
2
350
1000
1500
1000
1500
1000
1500
1000
1500
1+
Positive Supply
Current
I+STANOBY
VIN = 2.4 V
V A =00r2.4V
1-
V±=±16.5V
Negative Supply
Current
I-STANOBY
mA
INPUT
Input Current With YiN
High
Input Current With YiN
Low
IAH
IAL
/-LA
DYNAMIC
Enable Turn-ON Time
tON(EN)
Enable Turn-OFF Time
tOFF(EN)
See Switching Time
Test Circuits
ns
Multiplexer Switching
Time
tTRANS
1,3
2
700
Break-Before-Make
Interval
t OPEN
1
450
1
5.5
Charge Injection
Q
Rgen = 0.0.
C L= 10 nF
Vgen = 0 V
50
50
15
15
pC
Vgen = ± 10 V
1
7
20
20
5-317
DGP508A
WY'Siliconix
,,1;11 incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
Test Conditions
Unless Otherwise Specified:
V+ = 15 V, V- = -15 V
GND = 0 V
VAH = 2.4 V, VAL = 0.8 V
VEN = 2.4 V
LIMITS
1=2SoC
A
0
2=125,85°C
SUFFIX
SUFFIX
3=-5S,-40·C -55 to 125°C -40 to 85°C
TEMP TYpd
MINb MAX' MINb MAXb UNIT
DYNAMIC (Cont'd)
Source OFF Capacitance
CS(OFF)
DraIn OFF CapacItance
Co (OFF)
DraIn and Source ON
Capacitance
CS(ON) +
COlON)
f = 1 MHz
Crosstalk
OFF IsolatIon
f = 100 kHz
InsertIon Loss
1
5
1
25
1
30
1
-60
1
-60
1
-1.6
pF
dB
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for addItIonal InformatIon.
b. The algebraIc conventIon whereby the most negatIve value Is a mInImum and the most posItIve a maximum, Is used In
thIs data sheet.
c. Guaranteed by design, not sublect to productIon test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testIng.
e. Sequence each switch ON.
DIE TOPOGRAPHY
...
Pad
No.
2
1
73 mils
'-----------.lJ
10
ICMGA
4 CapacItors
7 ResIstors
12 DIodes
5-318
11
12 13 14
85 P-channel enhancement MOSFETs
89 N-channel enhancement MOSFETs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FunctIon
Address 0
Enable
VSource 1
Source 2
Source 3
Source 4
DraIn
Source 8
Source 7
Source 6
Source 5
V+ (Substrate)
Ground
Address 2
Address 1
DGP508A
..... Siliconix
incorporated
~
tON(EN) AND tOFF(EN) TEST CIRCUIT
tr<20ns
11<20no
3.0V
LOGIC
INPUT
+15 V
V+
Vs
S l l - - - - - o -5 v
50%
0 V
----...11
ov
---=~::..::.-+-....,
IOFF(EN)
swrrCH
OUTPUT
Vo
0.1 Vo
~2
VO-------
SB
RL
Vo
=
Vs
---~-
RL + ROS(ON)
tOPEN TEST CIRCUIT
_/
3V
LOGIC
INPUT
+15 V
2.4 V
EN
A2
A1
V+
OV
Vo
Sl
Vs
+5V
SWITCH
OUTPUT
Vo
SB
50%
OV
SWrrCH
OUTPUT
tr<20ns
\
If <20 no
'---
-1£
tTRANSITION TEST CIRCUIT
3.0 V
LOGIC
INPUT
+15 V
2.4V
rE;'N:;--~V~+:-SS;-ll------o
+10 V
S2
S7
SWITCH
OUTPUT
Vo
0 V _ _ _ _...JI
50%
tr<20ns
11<20no
O.B VS 1
OV
VSB _ _
O_.B_V_S::lI..--+_=
ro;;;;....--=.2.....::':":"-4J
ITRANsmON
SBi--------T-o OUTPUT
5-319
DGP508A
. . , Siliconix
incorporated
~
OFF ISOLATION TEST CIRCUIT
+15 V
O .........o-_---Q
SIGNAL
GENERATOR
FREQUENCY
TESTED
-=-
100 Hz to
13 MHz
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
Analyzer
Chan A
OFF
ISOLATION
= 20 log
VOUT
VGEN
Chan B
CROSSTALK TEST CIRCUIT
2.4 V
51
+15 V
EN
V+
~2
O.........O-_---Q
58
A2
A1
1 k.n.
FREQUENCY
TESTED
100 Hz to
13 Mt-tz
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
SIGNAL
GENERATOR
ANALYZER
HP3330B
Automatic
Synthesizer
HP3571A
Tracking
Spectrum
Analyzer
Analyzer
Chan A
CROSSTALK
= 20 log
VOUT
VGEN
Char B
INSERTION LOSS TEST CIRCUIT
2.4 V
+15 V
EN
V+
Ot-o--t----Q
FREQUENCY
TESTED
SIGNAL
100 Hz to
13 MHz
GEN~RATOR
Analyzer
Chan A
INSERTION _ 20 log
LOSS
-
Chan B
5-320
VOUT
VGEN
~
~
DGP508A
Siliconix
incorporated
DRAIN ON CAPACITANCE
OV
+15 V
EN
v+
SI
A2
CHAN N'l {
Al
SELECT
METER
S~
D
AO
-15 V
BOONTON 72BO
CapacItance
Meter
or equIvalent
CAPACITANCE
METER
-=-
SOURCE/DRAIN OFF CAPACITANCE
OV
+15 V
SI
METER
A2
S8
CHANN'l {
CAPACITANCE
METER
Al
SELECT
AO
D
BOONTON 72BO
CapacItance
Meter
or equIvalent
-=-
-15 V
-=-
CHARGE TRANSFER ERROR
3V~
LOGIC
INPUT 0 v
OV
SWITCH
OUTPUT
+15 v
EN
V+
SI
/
'-_ _ _ _ _ _...J
----/
/:::;. Vo Is the measured voltage
due to charge transfer error I Q
A2
S8
C_NEL{
SELECT
A1
AO
-=-
D
r
cL
10nF
5-321
DGP508A
.... Siliconix
incorporated
~
SCHEMATIC DIAGRAM
4
7
12
85
89
~
Capacitors
Resistors
Diodes
P-channel enhancement MOSFET
N-channel enhancement MOSFET
____________
~l-
I
....
In
2.4 V
Logic "0" VAL < 0.8 V
TIMING DIAGRAMS
3V~1.5V
o
~
J
3v _____f1ww
AO. A 1. (A2)
EN
0 _ _ _ _-'
~jC'~
2.0 V
Figure 1
As
-""
OUTPUT
3V~
0
1.5V
v,
_
d
~ ":~
0
''''
L)
O.B Vo
O.B V
Figure 2
5-351
DG526/527
B
Siliconix
incorporated
TRANSITION TIME TEST CIRCUIT
+2 4 V
LOGIC
INPUT
t r < 20 n.
tl< 20 ns
+15V
SV
50%
EN
o
As
v+
AO
Al
A2
VS1=---t.,
O.BVSl
SWITCH
OUTPUT
Vo
Sl
S2thru S 15
S16
DG526
r--r-+--o-; AS
SWITCH
OUTPUT
0
Vo
135pF
lM.o.
VSB
-::-
O.BVSB
+24V
+15V
S10N
V+
Slb
Sla thru
SBaOa
S2b andS 7b
SBb
SWITCH
OUTPUT
DG527
Db
VOb
-::-
135pF
Figure 3
ENABLE tONI tOFF TIME TEST CIRCUIT
LOGIC
INPUT
t r < 20 n.
tl<20n.
SV
50%
,..,..---0-; EN
S,
0
0
O. lVO
SWITCH
OUTPUT
o 1--<>-1~"""'--o
SWITCH
OUTPUT
Vo
1 k.o. -::0. 9VO
Vo
Vs
EN
AO
Al
A2
135
Vo
pF
S,
S'a thru SBa
S4a Oa
S2bthru SBb
-::-
DG527
SWITCH
OUTPUT
Db
VOb
-::-
Figure 4
5-352
135PF
DG526/527
...,. Siliconix
incorporated
~
OPEN TIME (B.B.M.) INTERVAL TEST CIRCUIT
+15 V
+2.4 V
LOGIC
INPUT
t r < 20 ns
tf<20ns
3V
50%
V+
EN
o
Vs
As
ALL SAND Da
,.--....,1-1
SWITCH
OUTPUT
1--0-_......- 0
BO%
SWITCH
OUTPUT
VD
+5 V
00526
00527
VD
OV
1
50.0.
1- tOPEN
35pF
WRITE TURN-ON TIME tONI WR)TEST CIRCUIT
+15V
3
WR
1.5V
50%
SWITCH
OUTPUT
Vo
V+
Slor S 'b
EN
0
AO,A1,
A2, (A3l
-tOFF(WRr-k
'O. 2VO
OV
As
REMAINING
SWITCHES
":'
00526
00527
SWITCH
OUTPUT
DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE
Vo
..
1
35PF
Figure 6
":'
RESET TURN-OFF TIME tOFFC'Rs)TEST CIRCUIT
+15 V
EN
AO,A1,
A2, (A3l
":'
SWITCH
OUTPUT
Vo
V+
Slor S 'b
REMAINING
SWITCHES
00526
00527
O.BVO
SWITCH
OUTPUT
Vo
LOGIC
INPUT
Figure 7
":'
":'
CHARGE INJECTION TEST CIRCUIT
+15V
EN~
2.4 V
, AYo
Rgen
r--'VI<'V--+""":S;:"X:;""O' ....._--'''-f--......- - Q
Vo
T
Vgen
r
VO~
A. Vo IS THE MEASURED VOLTAGE ERROR
Figure 8
DUE TO CHARGE INJECTION. THE CHARGE
IN COULOMBS IS a = CLx A. Vo
5-353
DG526/527
.... Siliconix
incorporated
~
DETAILED DESCRIPTION
The internal structure of the DG526 and DG527
includes a 5 V logic interface with input protection
circuitry followed by a latch, level shifter, decoder
and finally the switch constructed with parallel N
and P-channel MOSFETs (see figure 9).
The input protection on the logic lines Ao, Alo A2,
As, EN and control lines WR, RS shown in figure 9
minimize susceptibility to static encour.tered during
handling and operational transients.
The logic interface circuit compares the TIL input
signal against a TIL threshold reference voltage.
The output of the comparator feeds the data input
of a D type latch. The level sensitive D latch
continuously places th~x input signal on the Ox
output when the ClK (WR) input is low, resulting in
transparent operation. As soon as ClK (WR)
returns high the latch holds the data last present on
the DX input at the Ox output, subject to the
"Minimum Input Timing Requirements" table.
t
Following the latches the Ox signals are level
shifted and decoded to provide proper drive levels
for the CMOS switches. This level shifting insures
full ON/OFF switch operation for any analog signal
present between the V+ and V- supply pins.
The enable (EN) pin is used to enable the address
latches during the WR pulse. It can be hard wired to
the logic supply if one of the channels will always be
used (except during a reset) or it can be tied to
address decoding circuitry for memory mapped
operation. The RS pin is used as a master reset. All
latches are cleared regardless Q!..!he state of any
other latch or control line. The WR pin is used to
transfer the state of the address control lines to
their latches, except during a reset or when EN is
low (see Truth Tables).
r---------------------------------------------------~------------"v+
LEVEL
SHIFT
DECODE
~-----I---O S,
------L
Sa
L----------+---------~
____________O
v-
Figure 9. OG526/527 Slmplifed Internal Structure
APPLICATIONS
INTRODUCTION
The DG526 and DG527 minimize the amount of
interface hardware between a microprocessor
system bus and the analog system being controlled
or measured. The internal TIL compatible latches
give these multiplexers write-only memory, that is,
they can be programmed to stay in a particular
5-354
switch state (e.g., switch 1 ON) until the
microprocessor determines it is necessary to turn
different switches ON or turn all switches OFF.
The input latches become transparent when WR is
held low; therefore, these multiplexers operate by
direct command of the coded switch state on the
address inputs. In this mode the DG526 is identical
~
~
DG526/527
Siliconix
incorporated
APPLICATIONS (Cont'd)
to the very popular DG506 even sharing the same
pin locations. The same is true of the DG527 versus
the popular DG507.
information in the Ao, A" A2, A3, and EN latches is
decoded and the appropriate switch is turned ON.
The EN latch allows all switches to be turned OFF
under program control. This becomes useful when
two or more DG526s are cascaded to build 32-line
and larger analog Signal input multiplexers.
CIRCUIT OPERATION (See Figure 10)
Initially during system power-up RS would be active
LOW maintaining all 16 switches in the OFF state.
After RS returned HIGH the DG526 maintains all
switches in the OFF state. As soon as the system
program was ready to perform a write operation to
the address assigned to the DG526, the address
decoder would provide a CS active LOW signal
which is gated with the WRITE (WR) control signal.
At this time the data on the DATA BUS (that will
determine which switch to close) is stabilizing.
When the WR signal returns to the HIGH state,
(positive edge) the input latches of the DG526 save
the data from the DATA BUS. The coded
DATA BUS
Figure 11 illustrates one use of the DG527. Dual
multiplexers are generally used with differential or
instrumentation amplifiers in process control
applications to eliminate errors due to common
mode signals. In this circuit however, advantage is
taken of the dual multiplexing capability of the
switch. This is achieved by using the multiplexer to
select pairs of R.C. networks to control the pulse
width of the multivibrator. This can be a particularly
useful feature in process control applications where
there is a requirement for a variable width sample
"window" for different control signals.
>~~
---------~
t1
3)
EN
DG526
PROCESSOR
SYSTEM
BUS
RESETC>---------iRs
o
v-
1 OF 16
ANALOG
OUTPUT
-15 V
Figure 10
5-355
. . , . Siliconix
incorporated
DG526/527
~
APPLICATIONS (Cent'd)
vOG527
DATA BUS
EN -18
AD -17
A1 -16
A2 -15
Vee
R1
R2
19
20
R3
21
R4
22
R5
23
R6
24
R7
25
R8
26
28
Q
Q
RS
WR
ADD BUS
Figure 11. j1P-selected Pulse-Width Control
APPLICATIONS HINTS
5-356
V+
Positive
Supply
Voltage
VNegative
Supply
Voltage
GND
Analog &
Power
Supply
GND
VIN
Logic Input
Voltage
VINHMinl
VINLMax
Vs orVo
Analog
Voltage
Range
(V)
(V)
(V)
(V)
(V)
20
-20
GND
2.4/0.8
± 20
15
-15
GND
2.4/0.8
±15
8
-8
GND
2.4/0.8
±8
DG528/529
a-Channel and Dual
4-Channel Latchable Multiplexers
...... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• TTL Compatible
• Easily Interfaced
• Data Acquisition Systems
• 44 V Power Supply
Rating
• Increased Analog Signal
Range
• Automatic Test Equipment
• On-board Address Latches
• Microprocessor Bus
Compatible
• rDSION) < 400 n
• Break-Before-Make
• Avionics And Military
Systems
• Communication Systems
• Improved System
Accuracy
• Microprocessor Controlled
Systems
• Reduced Crosstalk
• Audio Signal Multiplexing
DESCRIPTION
DG528 and DG529 are 8 and 4-channel analog
multiplexers. respectively. with on-Chip address
and control latches to simplify design in
microprocessor based applications. Break-beforemake switching action protects against momentary
shorting of the input signals. Designed on the
Siliconix PLUS-40 CMOS process. each bidirectional
switch features low 400 n ON resistance over the
full analog range, and will block signals to 30 V
peak-to-peak in the unselected channels. All logic
levels are TTL compatible.
DG528 is an 8-channel single-ended analog
multiplexer designed to connect 1 of 8 inputs to a
common output as determined by a 3-bit binary
address (Ao. Al. A2). DG529. a 4-channel dual
analog multiplexer. is designed to connect 1 of 4
dual inputs to a common dual output as determined
by its 2-bit binary address (Ao. Al) logic. An
epitaxial layer prevents latchup.
The on-board TTL-compatible address latches
simplify the digital interface design and reduce
board space in bus-controlled systems such as
data acquisition systems. process controls.
avionics. and ATE. The DG528 is available in 18-pin
CerDIP in the military, A suffix (-55 to 125°C).
industrial. B suffix (-25 to 85°C) and commercial. C
suffix (0 to 70°C) temperature ranges. and in the
plastic DIP for commercial temperature operation.
For more information on the DG528 and DG529.
please refer to Siliconix Application Note AN83-4.
PIN CONFIGURATION
Dual-In-Line Package
Top View
Dual-ln-Llne Package
Top View
R8
A1
A2
GND
v+
82
85
86
Order Numbers:
CerDIP: DG52BAK. DG52BBK.
DG52BCK
Plastic: DG52BCJ
Order Numbers:
CerDIP: DG529AK. DG529BK.
DG529CK
Plastic: DG529CJ
5-357
DG528/529
".,. Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
S1
S2
S3
S4
S5
D
S6
S7
Sa
S1a
S2a
S3a
S4a
S1b
Da
S2b
S3b
S4b
RS
Db
WRo-+-------;
A1
DG528
8-Channel Single-Ended Multiplexer
DG529
Differential 4-Channel Multiplexer
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VV+ ........................................... 44 V
GND ...............•..••.••.......•.......... 25 V
Digital Inputs, Vs ,Voh ...... (V-) -2 V to (V+) +2 V or
. . . . . . . • • • • • • . . . . . . . . .. 20 mA, whichever occurs first.
Current (Any Terminal Except S or D) ........... 30 mA
Continuous Current, S or 0 .................... 20 mA
Peak Current, S or 0
(Pulsed at 1 ms, 10% Duty Cycle Max) .......... 40 mA
5-358
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 85°C
(C Suffix) ..•......... 0 to 70°C
Storage Temperature (A & 8 Suffix) •••.•.. -65 to 150°C
(C Suffix) ...•••..•. -65 to 125°C
Power Dissipation (Package)'
18-Pln Ceramic DIP" . .. . . . • . . • . .. • .. . . . . . . .. 900 mW
18-Pln Plastic DIP**' ••.•.•.....•............ 470 mW
All leads soldered or welded to PC board.
** Derate 12 mW/oC above 75°C.
••• Derate 6.3 mW/OC above 75°C.
DG528/529
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
B,C
2=125,70,85°C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-25,O°C -55 to 125°C
GND = 0, WR = 0
RS = 2.4 V
TEMP TYpd
MINiMAX b MIN MAXb UNIT
SWITCH
Analog Signal Range C
-15
1,2,3
VANALOG
15
-15
400
500
15
V
450
500
.0.
Drain-Source e
ON Resistance
rOS(ON)
Vo =±10 V, VAL = 0.8 V
Is = -200.llA,VAH = 2.4 V
1,3
2
270
Greatest Change In r os (ON)
Between Channels f
rOS(ON)
t.
-10 V --i EN
o
AO
0,....--+..
Al
O. lVO
SWITCH
SWITCH
00528
A2
OUTPL1T
o I--o-r-""'?'-O
135
OLITPUT
Vo
0. 9VO
VOb
PF
Vo
Vs
r-"t""---o--i EN
Slathru S4a Oa
S2b S3b S4b
AO
SWITCH
00529
OLITPLIT
Obt--o-.,....-r---o VOb
........:::r=-~;:.:-~or--....I
Figure 4
5-364
135
PF
~
~
DG528/529
Siliconix
incorporated
OPEN TIME (B.B.M.) INTERVAL TEST CIRCUIT
+2.4 V
LOGIC
INPUT
t r < 20 ns
tf< 20 ns
+15 V
3V
V+
50%
EN
0
As
Vs
SWITCH
OUTPUT
80%
SWITCH
OUTPUT
VD
+5V
ALL SAND Da
OG528
OG529
1--0-_......- 0
VD
OV
1
1- tOPEN
35PF
Figure 5
WRITE TURN-ON TIME tONe WR) TEST CIRCUIT
+15V
3
1.5 V
:"-ION(WRI
SWITCH
OUTPUT
Vo
V+
50%
o
EN
-.1
S, or S,b
AO.A,. (A21 REMAINING
SWITCHES
o v _________.J~O
.-----0-1 As
-=-
OG528
OG529
SWITCH
OUTPUT
DEVICE MUST BE RESET PRIOR TO APPLING WR PULSE
Vo
LOGIC 1-,;;;.;;;.-----;-....1
1 kn.
INPUT
1
35PF
-=Figure 6
RESET TURN-OFF T!ME tOFF( RS) TEST CIRCUIT
+15V
V+
EN
AO.A,. (A21 REMAINING
SWITCHES
-tOFF(RSI-
~~~~ -----------~I
Vo
SIO,S'b
OG528
OG529
0. 8VO
SWITCH
OUTPUT
I-D-t--,......-o
LOGIC 1-';;;';;;'-";';;';-_"';'_....1
INPUT
Vo
1
35PF
Figure 7
5-365
DG528/529
...... Siliconix
incorporated
~
CHARGE INJECTION TEST CIRCUIT
EN~
2.4V
Rgen
S
--.....kTo-"T--O
1
~
V
O~
ct. = 1000 pF
Vgen
r
Vo
-=-
T
Figure 8
/:)" Vo IS THE MEASURE VOLTAGE ERROR
DUE TO CHARGE INJECTION. THE CHARGE
INJECTION IN COULOMBS IS Q = C LX /:)" Vo
DETAILED DESCRIPTION
The internal structure of the OG528 and OG529
includes a 5 V logic interface with input protection
circuitry followed by a latch. level shifter. decoder
and finally the switch constructed with parallel N
and P-channel MOSFETs (see figure 9).
the Ox input at the Qx output. subject to the
"Minimum Input Timing Requirements" table.
Following the latches the Qx signals are level
shifted and decoded to provide proper drive levels
for the CMOS switches. This level shifting insures
full ON/OFF switch operation for any analog signal
present between the V+ and V- supply pins.
The input protection on the logic lines Ao. Al. A2.
EN and control lines WR. RS shown in figure 9
minimize susceptibility to static encountered during
handling and operational transients.
The enable (EN) pin is used to enable the address
latches during the WR pulse. It can be hard wired to
the logic supply if one of the channels will always be
used (except during a reset) or it can be tied to
address decoding circuitry for memory mapped
operation. The RS pin is used as a master reset. All
latches are cleared regardless of the state of any
other latch or control line. The WR pin is used to
transfer the state of the address control lines to
their latches. except during a reset or when EN is
low (see Truth Tabies).
The logic interface circuit compares the TIL input
signal against a TIL threshold reference voltage.
The output of the comparator feeds the data input
of a 0 type latch. The level sensitive 0 latch
continuously places th~x input signal on the Qx
output when the CLK (WR) input is low. resulting in
transparent operation. As soon as CLK (WR)
returns high the latch holds the data last present on
r--------------------------~------~V+
TTL THRESHOLD
VOLTAGE
?o;':;:::=h----o 0
>---1 On
LEveL
SHIFT
DeCODe
4 WIDE
LATCH
L..4--+-0S 1
------L,"
~----~----~------~V-
Figure 9. DG528/529 Simplified Internal Structure
5-366
DG528/529
...... Siliconix
incorporated
~
APPLICATIONS
BUS INTERFACING (See Figure 10)
The DG528 and DG529 minimize the amount of
interface hardware between a microprocessor
system bus and the analog system being controlled
or measured. The internal TTL compatible latches
give these multiplexers write-only memory, that is,
they can be programmed to stay in a particular
switch state (e.g., switch 1 ON) until the
microprocessor determines it is necessary to turn
different switches ON or turn all switches OFF.
The input latches become transparent when WR is
held low; therefore, these multiplexers operate by
direct command of the coded switch state on A2,
A1, Ao. In this mode the DG528 is identical to the
very popular DG508 even sharing the same pin
locations. The same is true of the DG529 versus the
popular DG509.
Initially during system power-up RS would be active
LOW maintaining all 8 switches in the OFF state.
After RS returned HIGH the DG528 maintains all
switches in the OFF state. As soon as the system
program was ready to perform a write operation to
the address assigned to th~DG528, the address
decoder would provide a CS active LOW signal
which is gated with the WRITE (WR) control signal.
At this time the data on the DATA BUS (that will
determine which switch to close) is stabilizing.
When the WR signal returns to the HIGH state,
(positive edge) the input latches of the DG528 save
the data from the DATA BUS. The coded
information in the Ao, Alo A2, and EN latches is
decoded and the appropriate switch is turned ON.
The EN latch allows all switches to be turned OFF
under program control. This becomes useful when
two or more DG528s are cascaded to build 16-line
and larger analog Signal input multiplexers.
DATA BUS
PROCESSOR
SYSTEM
BUS
R E S E T ( ) o - - - - - - - - I RS
D
v-
10FB
ANALOG
OUTPUT
-15V
Figure 10. Bus Interface
5-367
DG528/529
~
~
APPLICATIONS HINTS
5-368
VIN
Logic Input
Voltage
VINHMinl
VINLMax
Vs orVD
Analog
Voltage
Range
V+
Positive
Supply
Voltage
VNegative
Supply
Voltage
GND
Analog &
Power
Supply
GND
(V)
(V)
(V)
(V)
(V)
20
-20
GND
2.4/0.8
± 20
15
-15
GND
2.4/0.8
±15
8
-8
GND
2.4/0.8
±8
Siliconix
incorporated
DG548/549
8-Channel and Dual 4-Channel CMOS Analog
Multiplexers with Overvoltage Protection
..,. Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Analog/Digital
Overvoltage Protection
• Improved Ruggedness
• Data Acquisition Systems
• Power Loss Protected
• Fail Safe With Power Loss
(No Latchup)
• Prevents Adjacent Channel
Crosstalk
• Industrial Process
Control
• Break-Before-Make Switching
• Standard Logic Interface
• Avionics Test Equipment
• High Rei Control Systems
• TTL and CMOS Compatible
Inputs
DESCRIPTION
The DG548 and DG549 are dielectrically isolated 8and 4-channel analog multiplexers, respectively,
incorporating overvoltage protection. They withstand analog input voltages greater than the
supplies. This is advantageous in systems where
the analog inputs originate outside the equipment.
The DG548/DG549 can withstand continuous inputs
up to 10 volts greater than either supply, which
eliminates the possibility of damage when supplies
are lost, while input Signals are still present. These
multiplexers can withstand brief input transient
spikes of several hundred volts which otherwise
would
require
complex external
protection
networks. Necessarily, ON resistance is higher than
the DG508A/DG509A but very low leakage currents
combine to produce low errors.
The DG548 and DG549 are pin compatible with the
industry-standard DG508A and DG509A multiplexers.
The DG548 and DG549 are offered in 16-pin plastic
and CerDIP packages for operation over the
commerCial, C suffix (0 to 70°C) and military, A
suffix (-55 to 125°C) temperature ranges.
PIN CONFIGURATION
Dual-In-Llne Package
Top View
Order Numbers:
DG548AK, DG548BK
DG548CK, DG548CJ
Preliminary
Dual-In-Llne Package
Top View
Order Numbers:
DG549AK, DG549BK
DG549CK, DG549CJ
5-369
DG548/549
~
~
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
V-
V+
GND
V-
V+
..
GND
s2o-t-------------~71'~~
S1ao-t-----------------~,.,
S2ao-t-----------~r,6----r_i
S3o-t-----------~~_r_r~
S3ao-t-------afo~--;_----~
S4o-.-----------ao~_;~~
S4ao-t--g,~--_+----4_----~
S1o-t---------------~~,
D
S5o-~-------oI~T_+-~~_t
S1bo-.---r----+----4---~r.,
S6o-~-----a,~+-+-~~~_t
S2bo-t---~---7--~~6----~
S7o-~--~,~~+-7_+_~~_t
S3bo-t---~--~L---4-----r_i
SBo-~~,..,~~+-+_+_;_;_~
S4bo-t--g,~--_r----;_----~
A2
A1
Ao
Da
A1
EN
Ao
EN
DG549
Differential 4 Channel Multiplexer
DG548
8 Channel Single Ended Multiplexer
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VV+ ..........•......•......................... 44 V
GND ......................................... 25 V
VEN, VA, Digital Input ........... (V-) -4 V to (V+) +4 V
, V s, Analog Input Overvoltage with Power ON
.......................•.... (V-) -20 V to (V+) +20 V
V s' Analog Input Overvoltage with Power OFF
. . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -35 V to +35 V
Continuous Current, S or D .................... 20 mA
Peak current, S or D
(Pulsed at 1 ms, 10% duty cycle max) .....•.... 40 mA
Operating Temperature (A Suffix) ......... -55 to 125·C
(C Suffix) .........•.. 0 to lO·C
Storage Temperature (A Suffix) ........... -65 to 150·C
(C Suffix) .........•• -65 to 125·C
Power Dissipation (Package)·
16-Pln Ceramic DIp·· ............•.........•. 900 mW
16-Pln Plastic DIp··· ........................ 600 mW
All leads soldered or welded to PC board.
•• Derate 12 mW/·C above l5·C.
••• Derate 6.'3 mW/·C above 25·C.
Stresses above those listed under • Absolute Maximum
Ratings' may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
A
C
2=125,lO·C
V+ = 15 V, V- = -15 V
SUFFIX
SUFFIX
3=-55,-0·C -55 to 125°C
o to lOoC
GND = 0 V
V AH = 4.0 V, VAL = 0.8 V
TEMP TYpd MINb MAXb MINb MAXt UNIT
SWITCH
Analog Signal Range C
ON Resistance"
rOS(ON)
rOS(ON) Match
Between Channels f
rOS(ON)
5-370
1,2,3
VANALOG
t:.
-15
Vo =±10 V, 10 = -100,JJ.A
1
2,3
1.2
Vs = 0 V, 10 = -100,JJ.A
1
6
15
1.5
1.8
-15
15
V
1.8
2.0
k.O.
%
Preliminary
DG548/549
flY' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
C
A
2=125,70·C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-0·C
-55
to
125°C
o
to
70°C
GND = 0 V
VAH=4.0V, VAL=O.BV
b
b
TYpd
MIN MAXb MIN MAXt UNIT
TEMP
SYMBOL
PARAMETER
SWITCH (Cont-d)
Source OFF
Leakage Current
IS(OFF)
DG548
Drain OFF
Leakage Current
VEN = 0 V
Vs= ±10 V
Vo= +10 V
1
2,3
0.03
-0.5
-50
0.5
50
-0.5
-50
0.5
50
Vo= ±10 V
Vs= +10 V
1
2,3
1
-5
-250
5
250
-5
-250
5
250
Vo= ±10 V
Vs= +10 V
1
2,3
0.5
-2.5
-125
2.5
125
-2.5
-125
2.5
125
4
-20
20
-2000 2000
-20
-2000
20
2000
IO(OFF)
DG549
IO(OFF) with Input
Overvoltage Applied
loov
Analog Overvoltage = ± 33 V
(See Figure 1)
1
2,3
Differential OFF
Drain Leakage Current
IOIFF
DG549 Only
1,2,3
DG54B
Drain ON
Leakage Current
IO(ON)
Vs=Vo=±10V
DG549
Sequence
Each Switch
ON
VAL= O.B V
V AH = 2.4 V
-50
50
-50
50
1
2,3
0.1
-1
-250
1
250
-1
-250
1
250
1
2,3
0.05
-0.5
-125
0.5
125
-0.5
-125
0.5
125
nA
INPUT
Input LOW Threshold
VAL
1,2,3
Input HIGH Threshold
VAH
1,2,3
2.4
1,2,3
-1
0.8
O.B
V
Logic Input Current
IA
V A = 2.4 Vor O.B V
2.4
1
-1
1
JiA
1
.I1S
ns
DYNAMIC
tA
See Figure 2
1
0.5
Break-Before-Make
Interval
tOPEN
See Figure 3
1
BO
Enable Delay
Turn ON Time
tON(EN)
1
2,3
300
500
1000
500
1000
Enable Delay,
Turn OFF Tme
tOFF(EN)
1
2,3
300
500
1000
500
1000
0.1 %
1
1.2
0.025%
1
3.5
VEN =7V,RL=1 k.o.
C L = 3 pF, Vs= 3 VRMS
f = 500 kHz
1
6B
dB
1
5
pF
Access Time
Settling Time
See Figure 4
ts
OFF Isolation
Logic Input Capacitance
Preliminary
Cln
1
25
25
.I1s
f = 1 MHZ
5-371
DG548/549
flY' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
A
C
2=125,85·C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-40·C -55 to 125°C
o to 70°C
GNO = 0 V
VAH = 4.0 V, VAL = 0.8 V
TEMP TYpd MIN" MAXb MIN b MAXb UNIT
DYNAMIC (Cont'd)
Souroe OFF Capaoltanoe
. CS(OFF)
OG548
Oraln OFF
Capaoltanoe
1
5
1
25
1
12
1
30
1
17
1,2,3
0.5
CO(OFF)
OG549
013548
ON State Input
Capaoltanoe
pF
CS(ON)
OG549
Positive Supply Current
1+
Negative Supply Current
VEN = HIGH or LOW
VA=OV
1-
2.0
2.0
mA
1,2,3 -0.02
-1
-1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for addltlonallriformatlon.
b. The algebralo oonventlon whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
o. Guaranteed by design, not subJeot to production test.
d. Typical values are for OESIGN AIO ONLY, not guaranteed nor subJeot to production testing.
SWITCHING TIME TEST CIRCUITS
18
ANALOGINPLrr
CURRENT (liN)
15
12
(liN) ANALOG
INPLrr CURRENT
9
(rnA)
j
6
3
o
V
17
±IS
±IS
"'"
V
-
10'
V
V
-
1/
V
V
s
41 o (OFF)
(nA)
3
2
VoLrrPUT OFF
LEAKAGE CURRENT
10 (OFF)
±21
±24
±27
:tOO :t33
±36
VIN - ANALOG INPLrr OVERVOLTAGE (VOLTS)
Figure 1. Analog Input Overvoltage Charaoterlstlos
5-372
Preliminary
DG548/549
. . . Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUITS (Cont'd)
• Similar Connection for DG549
Figure 2. Access Time vs. Logic Level (High)
ACCESS TIME
LOGIC
INPUT
1\
V A INPUT
4V--r----""'\
50%
l"- t- 2 V/DIV.
1\
OV
+10 V ----1---,
1'1
OUTPUT A
-10 V
\
OUTPUT A
V/PIV'1
f
J
iii
I
200 ns/dlv
Figure 3. Access Time
+1SV
+4V
LOGIC
INPUT
I-o-~-_-o
........;;::;::--.;.;-.....1
SWITCH
OUTPUT
VS----...,
Vo
SWITCH
OUTPUT
Vo
ov
-----1--.. . .
tOPEN
• Similar Connection for DG549
Figure 4. Break-Before-Make Delay
Preliminary
5-373
DG548/549
..... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUITS (Cont'd)
+15V
VAH=4V
V+ S1
4V
+10 V
OG54B
ENABLE
INPUT
S2 -s 81-0----.
SWITCH
.". OUTPUT
50%
OV
Vs
Vo
SwrrCH
OUV~T
OV
• Similar Connection for OG549
Figure 6. Enable Delay
TRUTH TABLES
OG549
OG54B
A2
A1
Ao
EN
sw?tb~
A1
Ao
EN
~CIi
X
X
X
0
NONE
X
X
0
NONE
0
0
0
1
1
0
0
1
1
0
0
1
1
2
0
1
1
2
0
1
0
1
3
1
0
1
3
0
1
1
1
4
1
1
1
4
1
0
0
1
5
6
1
0
1
1
1
1
0
1
7
1
1
1
1
B
Logic '0'
5-374
=VAL
5 O.B Logic "1"
= VAH ~ 2.4 V
Preliminary
DG566
Serial-loading Octal SPST
High-Voltage Analog Switch
.... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• ± 50 Volt Analog Range
• Extended Voltage Range
• Ultrasound Systems
8
Serial Data Interface
• Low rOS(ON) « 40 .n
with ± 60 V Supplies)
Single Wire Interface
• Reduced Switching Errors
• Microprocessor-Controlled
Systems
• Blocks Bipolar Signals
• Automatic Test Equipment
CI
• Bidirectional Switching
DESCRIPTION
• High Voltage (± 60 V)
Systems
PIN CONFIGURATION
The DG566 is a high voltage D/CMOS octal
(8-channel) array of analog switches with a serial
data interface controlling the state of each switch
independently. This allows selection of none, any or
all eight channels simultaneously. In addition to its
high analog voltage range of ±50 V, the DG566
features low ON-resistance (30 .n typical), low
quiescent power consumption (270 IJ.W maximum),
and bidirectional switching over the full analog
signal range.
Cerquad Package
Top View
NO
04
S5
NO
4321282726
NO
S4
Os
03
S2
The serial data interface simplifies control in remote
applications. The WR pin controls latching of the
analog switch control inputs. The clock input (CK)
shifts the data through the register, but does not
change the state of the switches until the latches
are enabled via WR. The logic levels are set by the
VL input, ranging from a minimum of 8 V to a rated
maximum of 18 V.
02
07
S1
Ss
2
v+
11
Os
19 00UT
GNO
NO
OLK
12 13 14 15 16 1 18
v-
VL
ON
WR
Order Number: OG566DM
Built in a proprietary high-voltage D/CMOS process,
the DG566 achieves high voltage signal control
while maintaining low ON-resistance, low leakage
( I S(OFF) < 5 nA at 50 V), and fast transition times
« 2 IJ.s).
The DG566 is available in the Cerquad package for
surface mount applications. It is specified for
operation over the industrial, D suffix (-40 to 85°C)
temperature
range.
5-375
DG566
. . . Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM & TRUTH TABLE
V-
V+
GND
S1o-~~~L-----------------------------------------~--o
D1
S2
D2
S3
D3
S4
D4
S5
S6
S7
S8
Ds
Ds
D7
D8
SHIFT REGISTER
Dour
CK
8 Latchable SPST SWitches Per Package •
DIN X
-WR
SWITCH
0
0
OFF
1
0
ON
X
1
Maintains
Previous
State
Logic '0"
~
Loglc'1"
~11.5V
3.5 V
WR Input Is level sensitive
(not edge-triggered)
'SWlTCHES SHOWN FOR
LOGIC '1" INPUT
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Storage Temperature ...........•.....••. -65 to 125°C
V+ •.•••.••..•.....••..••..•••••..........••.. 62 V
V- .......................................... -62 V
VL
••••••••••••••••••.••••••••••••••••••••••••
18 V
Logic Input Voltage ••.•••.••.•..• -0.3 V to VL + 0.3 V
Continuous Current, S or D .••........•...•••.. 90 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) ..•.•••.. 400 mA
5-376
Operating Temperature (D Suffix) .....••••• -40 to 85°C
Power Dissipation'
28-Pln Cerquad" ........................... 450 mW
Device mounted with all leads soldered or welded to a
PC board.
Derate 6 mW/oC above 75°C.
DG566
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
-WR
V+ = 60 V
V- = -60 V
V L = 15 V
= GND = 0 V
LIMITS
1=25°C
2=85°C
3=-40°C
TEMP
D
SUFFIX
-40 to 85°C
TYP
d
MIN b MAX b
UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
ON Resistance
Variation
Source OFF
Leakage Current
Drain OFF
Leakage Current
Drain ON
Leakage Current
rOS(ON)
.o.rOS(ON)
I S(OFF)
10(OFF)
-50
1,2,3
VANALOG
50
-50 V < Vo < 30 V
1
2,3
25
40
60
30 V < Vo < 40 V
1
2,3
30
50
60
40 V < Vo < 50 V
1
2,3
50
100
150
1
±2
±5
Vs= 0 V
1
2,3
0.5
2
50
Vs = 50 V
1
2,3
1
5
100
Vo= 0 V
1
2,3
0.5
2
50
Vo= 50 V
1
2,3
1
5
100
Vs=Vo=OV
1
2,3
2
10
5k
Vs =Vo= 50 V
1
2,3
5
20
10 k
Is = 20 mA
10(all) = 5 mA
VS(all) = 0 V
V
.n
%
Vo= -50 V
Vs = -50 V
nA
10(ON)
INPUT f
Logic Input
LOW Voltage
V INL
1
Logic Input
HIGH Voltage
V INH
1
Logic Input Current
Input Voltage LOW
IINL
Logic Input Current
Input Voltage HIGH
IINH
Turn ON Time
tON
3.5
V
Turn OFF Time
VIN =OV
1
11.5
0.002
2.0
jJ.A
tOFF
VIN = VL
RL = 5 k.n
C L = 50 pF
See Figures 1 and 2
1
0.002
2.0
1
0.5
2
1
0.2
1.5
i
jJ.s
5-377
DG566
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 60 V
V- = -60 V
VL = 15 V
WR = GND = 0 V
-
LIMITS
1-25 ·C
2=85·C
3=-40 ·C
D
SUFFIX
-40 to 85 ·C
TEMP
TYP d
20
MIN b MAX
b
UNIT
DYNAMIC
-
100
Setup Time to WR
tso
1
Hold Time from WR
tHO
1
25
Write Pulse Width
tWR
1
35
See Figure 2
ns
Clock Delay to
Data Out
too
1
Data Setup Time
to Clock
tsu
1
0
Data Hold Time
from Clock
tH
1
35
250
30
Source OFF Capacitance
CS(OFF)
Vs = 0 V
1
15
Drain OFF Capacitance
CO(OFF)
Vo= 0 V
1
15
Channel ON Capacitance
COlON)
+CS(ON)
Vs = 0 V, ViiiiR =VL
f = 140 kHz
1
110
1
65
1
2,3
0.002
2
2
1
2,3
0.002
2
2
1
2,3
0.002
2
2
RL = 2 k.n, C L = 3 pF
OFF Isolation
Vs = 10 Vp-p,
f=10kHz
pF
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
Logic Supply Current
IL
V1N(all) = 0 V or 15 VI
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
_
e. Pulsed at 1 ms, 10% duty cycle.
f. "Inputs' refer to digital Inputs D 1 - D s , WR and CK.
5-378
J.l.A
H
DG566
Siliconix
incorporated
DIE TOPOGRAPHY
..
--I
218 mils
23
Pad Function
No.
1
2
3
4
5
6
7
8
9
10
11
12
16
15
24
14
13
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
159
mils
12
11
10
2
3
6
5
4
8
7
S4
D4
NC
NC
S3
D3
S2
D2
Sl
D1
V+
V- (substrate)
GND
VL
NC
DN
ClK
WR
DOUT
D8
S8
D7
S7
D6
S6
NC
Ds
Ss
9
III
20X
LNDEH
lVNMOS
lVPMOS
lVDMOS
HVPMOS
84
84
16
32
HVDMOS
N+ RESISTORS
DIODE
32
26
18
TYPICAL CHARACTERSITICS
Drain-Source ON Resistance
vs.Vo and Power Supply Voltages
Drain-Source ON Resistance
vs. Temperature
10
10
V+ = 60 V, V- = -60 V
80
-
V+ = 40 V, V- = -40 V· .......
I- V+ = 50 V, V- = -50 V :'V+ = 60 V, V- = -60 V,.....::.. .......
80
........
60
rOS(ON)
(.0. )
40
60
J
f V J
.," ./
rOS(ON)
(.0. )
125°C
V V.
- --,..-'"
p..... ....... ~ ~ ;;....- I-"'" VJ
~
"
20
.J!
5°C.....
5 0
40
11
r---_
20
55
!leo
-40
-20
o
20
VO- DRAIN VOLTAGE (V)
40
60
0
;,so
-40
-20
20
T
?- l -
0
40
60
VO- DRAIN VOLTAGE (V)
5-379
DG566
Siliconix
incorporated
SWITCHING TIME TEST CIRCUITS
LOGIC "1" = SWITCH ON
60V
15V
SWITCH
OUTPUT
V+
LOGIC
INPUT
VS= 50 v o--II---------CT
S
OV-----J
---Ic-Clf-t--...,...-o Vo
VS------t-~;=====~~-----swrrCH
OUTPUT
ov-----I-J
DINX
WRo-~:;~~~~____~~
VCK 0 - - - - - - - '
-SO V
SEE FIGURE 2 FOR PROPER CONTROL TIMING
Figure 1. Switching Time Test Circuit
TIMING DIAGRAM
Figure 2. Timing Olagram
5-380
DG568/569
8- and Dual 4-Channel High-Voltage
CMOS Multiplexers with Latches
trY' Siliconix
~
incorporated
FEATURES
BENEFITS
APPLICATIONS
• ± 50 V Signal Range
• Extended Voltage Range
• On-Board Address Latches
" Microprocessor Compatible
(15 V CMOS)
• High Voltage
(± 60 V) Systems
• Low rDS(ON)
« 40 .n with
± 60 V Supplies)
• Reduced Switching Errors
• Blocks Bipolar Signals
• Bidirectional Switching
• Microprocessor Controlled
Systems
• Automatic Test Equipment
• Communications Systems
DESCRIPTION
The DG568 and DG569 are 8- and 4-channel
multiplexers respectively, designed for high voltage
(±50 V) applications in microprocessor based
instrumentation
and
process control.
Both
multiplexers feature low ON resistance (30 ohms
typ.) and true bi-directional switch action over the
full analog signal range. In addition, on-board data
latches and control inputs are provided to simplify
interfacing with most microprocessors.
and A2), chip select WR and device reset RS (all
channels off), are the logic controls which store, or
clear, the switch address-inputs. RS also simplifies
switch turn-off during system powerup or reset.
The DG568 provides 8-channel single ended
multiplexing and demultiplexing, while the DG569 is
designed for 4-channel differential switching
applications. Address inputs with latches (Ao, Al,
Both devices are provided in the 18-pin side braze
package, and are specified over the military, A
suffix (-55 to 125°C) and industrial, B suffix (-25 to
85°C) temperature ranges.
Built in a proprietary high-voltage D/CMOS process,
these devices achieve high voltage signal control,
while maintaining low ON-resistance, low leakage,
and fast transition times.
PIN CONFIGURATION
Dual-In-Llne Package
Top View
Order Numbers:
Side Braze: DG568AP, DG568BP
Dual-In-Llne Package
Top View
Order Numbers:
Side Braze: DG569AP, DG569BP
5-381
..
WY'Siliconix
incorporated
DG568/569
~
FUNCTIONAL BLOCK DIAGRAM
V+
V-
GND
V+
s2o-~---------------f
B
SUFFIX
-25 to 85°C
MIN b MAXb UNIT
SWITCH
Source OFF
Leakage Current
Drain OFF
Leakage Current
Drain ON
Leakage Current
IS(OFF)
IO(OFF)
IO(ON)
Vs= 0 V
1
2,3
0.5
2
500
2
50
Vs= 50 V
1
2,3
1
5
750
5
100
Vo= 0 V
1
2,3
1.5
10
10,000
10
1000
Vo= 50 V
1
2,3
5
25
15,000
25
2000
Vs=Vo= 0 V
1
2,3
2
10
10,000
10
5000
Vo= 50 V
1
2,3
5
20
20,000
20
10,000
See Figure 1
V o =-50V
See Figure 2
Vs= -50 V
nA
See Figure 3
INPUTs
Logic Input Current
Input Voltage LOW
IINL
VIN=OV
1
0.002
2
2
IINH
VIN =VL
1
0.002
2
2
tON(WR)
RL= 2 JQl., CL = 50 pF
See Figure 4
1
0.5
2
2
tOFF{Rs)
R L= 2 JQl., C L = 50 pF
See Figure 5
JJ.A
Logic Input Current
Input Voltage HIGH
DYNAMIC
Turn-ON Time
JJ.s
Turn-OFF Time
Break-Belore-Make
Interval
Access Time
tssM
tA
1
0.2
1
1
1
300
50
50
1
100
20
20
1
60
300
300
1
90
300
300
See Figure 4
Write Pulse Width
tWA
Reset Pulse Width
tFiS
See Figure 5
ns
Source-OFF
Capacitance
CS(OFF)
VS=
aV
1
15
Drain-OFF
CapaCitance
CO(OFF)
VO=
aV
1
85
Channel ON
Capacitance
COlON) +
CS(ON)
VS= 0 V, V WA =V L
f = 140 kHz to 1 MHz
1
110
VFiS =OV, RL=2k,CL=3pF
Vs= 10Vp-p ' f= 10 kHz
1
65
Olf Isolation
pF
dB
5-383
DG568/569
.... Siliconix
,4;11 incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = 60 V
V- = -60 V
VL =VRS =15V
V'J'JR = GND = 0 V
SYMBOL
PARAMETER
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
B
SUFFIX
-25 to 85°C
TEMP TYpd MINb MAX' MIN b MAXb UNIT
SUPPLY
Positive Supply
Current
1+
Negative Supply
Current
1-
Logic Supply Current
1
2,3
0.002
2
20
2
2
1
2,3
0.003
2
30
2
2
IL
1
2,3
0.002
2
10
2
2
Minimum Supply Voltage
V+(min)
1
40
Minimum Logic Supply
Voltage
Vdmln)
1
B
VIN (All) = 0 V or 15 V e
J.lA
V
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, nO!J!.uaranteed nor subject to production testing.
e. "Inputs· refer to digital Inputs A o, A 1, A 2 , RS and WR .
DIE TOPOGRAPHY
159 mils
6
5
@
DG568
4
Pad
No.
1
2
3
4
5
6
7
8
9
8
9
20X
218
mils
WR
Ao
VL
V - (Substrate)
S1
S2
S3
S4
D
Sa
S7
S6
S5
V+
GND
A2
fu.
RS
LNDEA
10
11
12
16
13
5-384
10
11
12
13
14
15
16
17
18
Function
14
15
LVNMOS
LVPMOS
LVDMOS
HVPMOS
HVDMOS
N+ RESISTORS
DIODE
84
84
16
32
32
26
18
OG568/569
...r'Siliconix
incorporated
~
DIE TOPOGRAPHY (Cont'd)
218 mils - - - - - - - - - - - - - - .
OG569
Pad
No.
8
1
WR
2
Ao
3
VL
V-
4
9
5
6
7
8
9
10
11
12
13
14
15
16
17
18
159
mils
10
11
18
12
17
13
14
Function
Sla
S2a
S3a
S4a
Da
Db
S4b
S3b
S2b
Slb
V+
GND
fu
RS
LNOEB
LVNMOS
LVPMOS
LVDMOS
HVPMOS
HVDMOS
N+ RESISTORS
DIODE
84
84
16
32
32
26
18
15
20X
TRUTH TABLES
OGS6S
A2
Al
Ao
X
X
X
X
X
X
WR
RS
OGS69
ON Switch
Al
Ao
WR
RS
ON Switch
1
Maintains previous
switch condition
X
X
S
1
Maintains previous
switch condition
X
0
NONE
X
X
X
0
NONE
1
S
0
0
0
0
1
1
0
0
0
1
0
0
1
0
1
2
0
1
0
1
2
0
1
0
0
1
3
1
0
0
1
3
0
1
1
0
1
4
1
1
0
1
4
1
0
0
0
1
5
1
0
1
0
1
6
1
1
0
0
1
7
1
1
1
0
1
8
Logic "1" :VIN
Logic "1": VIN
=ViNAH l!:
=ViNAL :S
0.7 VL
1V
5-385
DG568/569
.... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
I SCOFF) VB, Vs
rOS(ON) vs.Vo
440
96
I
66
64
(.0. )
I
I
I
400
56
48
32
""
24
16
c-
A-
280
IS(OFF) 240
,
1
j
(pA)
If' I( I(
..:.,. V
~
/ V "/
V V :,;-
80
-60 -50 -40 -30 -20 -10 0
1/ 1/ 11/
'!..so -50 -40 -30 -20 -10
10 20 30 40 50 60
Vo - DRAIN VOLTAGE (V)
12
11
11
10
10
-
r-
9
A: V+=60V, V-=-60V
B: V+=50V, V-=-50V
0: V+=40V, V-=-40V
8
i-J
7
I o (OFF)
(nA)
6
V
5
2
Af/--
5
I
J
)
~
2
IB
0
10 20 30 40 50 60
-60 -50 -40 -30 -20 -10 0
10 20 30 40 50 60
Vo - DRAIN VOLTAGE (V)
rOS(ON) vs.Vo and Temperature
Threshold Voltage VB. Logic Supply Voltage
10
100
9
8
A
7
6
A
VT
5
IA
3
~
2
2
4
80
A
60
I
rOS(ON)
(.0. )
~
4
VJ
40
.4
8
10
12
14
16
18
o
V V
.....
+25°0
20
6
.... V'" V
+125°0
V L - LOGIC VOLTAGE (V)
5-386
I
6
Vo - DRAIN VOLTAGE (V)
00
A:
V+=60V, V-=-60V
B: V+ = 50 V, V- = -50 V
0: V+ = 40 V, V- = -40 V
3
F- -
-60 -50 -40 -30 -20 -10 0
r-
4
I B
V. ~
3
r
7
IO(ON)
(nA)
)I
4
(V)
10 20 30 40 50 60
IO(ON) vs.Vo
IO(OFF) VS. Vo
8
0
Vs- SOURCE VOLTAGE (V)
12
9
B
~ ......0 - t--
,,' .......: ::::;..
120
40
---
I-
I'
." ..... 1"
200
160
8
o
B: V+=50V, V-=-50V
0: V+=40V, V-=-40V
320 I - -
......
I i
40
r- r - I A: Iv+ !60 lv, ~_=I-60IV
360
-
r- y = to ~' V"j = 1'0 ~
r ~+=ro~, V"j=1°~
r- V+=80V, V-=-60V
72
rOS(ON)
I
J+=~oJ
v~=-1oJ
.....
I
I
I'
I
I
I
-
80
-5fO
-60 -48 -36 -24
-12
0
12
24
36
VO- DRAIN VOLTAGE (V)
48
60
OG568/569
fI'Y' Siliconix
~
incorporated
LEAKAGE TEST CIRCUITS
60 V
15 V
Vs
VD
-50 V
VD
OV
+15 V
Figure 1. I S(OFF) Test Circuit
• Similar connections for DG569
Figure
2.
Figure
I D(OFF) Test Circuit
3.
I D(ON) Test Circuit
tON(WR) TIME TEST CIRCUIT
+60 V
+15 V
vL------~
I.r---------~
ADDRESS
SWITCH
INPUT
ov--~X~~ I~____~____~
OV __
50
OUTPUT
I--o-~--~---() v D
L.-~_'::::':::;;~
VD
OV--------------~
VL-------------------------------
As
• Similar connections for DG569
v--
OUTPUT
OV-Figure 4.
WRITE Turn-ON Time
t OFF(RS) TIME TEST CIRCUIT
SWITCH
INPUT
See Truth Table
for proper logic
OV-50 V ------------,-----
OUTPUT
~~~--~----OVD
L.--+_~~
OUTPUT
VD
ov
VL---------------------------WR
• Similar connections for DG569
ov-
Figure 5. RESET Turn-OFF Time
5-387
DG568/569
..... Silicon Ix
incorporated
~
BREAK-BEFORE-MAKE TEST CIRCUIT
...--+-(161
+--+--f MINb MAXt UNIT
SWITCH
Analog Signal Range C
Drain-Source
ON Resistance
,
1,2,3
VANALOG
rOS(ON)
IS(OFF)
Switch OFF Leakage
Current
Is= -10 rnA, Vo=±10 V
Vo= -14 V, Vs= 14 V
Vo= 14 V, Vs= -14 V
IO(OFF)
-15
1,3
2
15
-15
50
75
1
2
-1
-100
1
100
1
2
-1
-100
1
100
-1
-100
-1
-100
15
V
50
75
.n.
1
100
1
100
nA
Channel ON
Leakage Current
Vs= Vo = 14 V
1
2
Vs= Vo = -14 V
1
2
-2
-200
VIN under test = 0.6 V
1,2
-1.0
1.0
-1.0
1.0
VIN under test = 2.0 V
1,2
-1.0
1.0
-1.0
1.0
IO(ON)+
IS(ON)
2
200
2
200
-2
-200
INPUT
In8ut Current with VIN
L W
IlL
Inrcut Current with VIN
HGH
IIH
JlA
DYNAMIC
:
Turn-ON Time
tON
Turn-OFF Time
tOFF
Vs=±10V
RL = 1 k.n., CL = 35 pF
See Figure 1A
1
1000
1200
1
500
700
ns
C L = 10,000 pF
Vgen = 0 V, Agen = O.n.
1
30
Off Isolatlon C
RL = 75.n., C L = 5 pF
f = 1 MHz
1
75
CrosstalkC
(Channel-to-Channel)
RL= 75.n., Vs= 2 Vp-p
f = 1 MHz
1
69
1
15
1
17
1
45
Charge InjectlonC
Q
pC
dB
Source-OFF Capacitance C
CS(OFF)
Drain-OFF Capacitance C
CO(OFF)
Channel ON CapacltanceC
CO(ON)+
CS(ON)
5-392
Vo=Vs= 0 V
f = 1 MHz
pF
H
DG5040-5045
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
LIMITS
Unless Otherwise Specified:
1=25°C
A
C
V+ = 15 V
2=125,70°C
V- = -15 V
SUFFIX
SUFFIX
VL = 5 V
3=-55,O°C
o to 70°C
-55 to 125°C
GND = 0 V
VIN = 2.0 V, 0.8 V e
TEMP TYpd MIN b MAX' MINb MAXt
UNIT
SUPPLY
Positive Supply Current
1+
1,2
Negative Supply Current
1-
1,2
Logic Supply Current
IL
1,2
IGND
1,2
300
-300
300
-300
JlA
VIN = 0.0 or 2.4 V
Ground Current
300
-300
300
-300
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
f. Signals on S x' D x or IN x exceeding V+ or V- will be clamped by Internal diodes. Limit forward diode current to 30 mAo
DIE TOPOGRAPHY
DG5040
-,
69 mils
11~~~_l
Pad
No.
1
11
12
13
14
15
16
Function
Drain
V+ (Substrate)
VL
GND
VInput
Source
20X
ICMKA
3 Capacitors
5 Resistors
13 P-channel enhancement MOSFET
12 N-channel enhancement MOSFET
7 Diodes
5-393
DG5040-5045
..... Siliconix
JI;II incorporated
DIE TOPOGRAPHY (Cont'd)
DG5041
Pad
No.
...1 - - - - - 107 mils
1
8
9
10
11
12
13
14
15
16
8
®
Function
Drain 1
Drain 2
Source 2
Input 2
V+ (Substrate)
VL
GND
VInput 1
Source 1
20X
ICMKA
5 Capacitors
6 Resistors
25 P-channel enhancement MOSFET
23 N-channel enhancement MOSFET
9 Diodes
DG5042
-,
69 mils
~~~::!
ICMKB
4 Capacitors
5 Resistors
16 P-channel enhancement MOSFET
5-394
17 N-channel enhancement MOSFET
7 Diodes
Pad
No.
1
3
4
11
12
13
14
15
16
Function
Drain 1
Drain 2
Source 2
V+ (Substrate)
VL
GND
VInput 1
Source 1
DG5040-5045
Ir'JP'" Siliconix
~
incorporated
DIE TOPOGRAPHY (Cont'd)
DG5043
-1
69 mils
~~:d
Pad
No.
1
3
4
5
6
8
9
10
11
12
13
14
15
16
Function
Drain 1
Drain 3
Source 3
Source 4
Drain 4
Drain 2
Souce 2
Input 2
V + (Substrate)
VL
GND
VInput 1
Source 1
ICMKB
7 Capacitors
33 N-channel enhancement MOSFET
6 Resistors
9 Diodes
31 P-channel enhancement MOSFET
..
DG5044
Pad
No.
1
69 mils
~~::!
1
3
4
11
12
13
14
15
16
Function
Drain 1
Drain 2
Source 2
V + (Substrate)
VL
GND
VInput 1
Source 1
ICMKA
4 Capacitors
5 Resistors
16 P-channel enhancement MOSFET
17 N-channel enhancement MOSFET
7 Diodes
5-395
DG5040-5045
rP'Siliconix
incorporated
~
DIE TOPOGRAPHY (Cont'd)
DG5045
Pad
No.
Function
1
3
4
Drain 1
Drain 3
Source 3
Source 4
Drain 4
Drain 2
Source 2
Input 2
V+ (Substrate)
VL
GND
VInput 1
Source 1
5
6
8
9
10
11
12
13
14
15
16
ICMKA
33 N-channel enhancement MOSFET
9 Diodes
7 Capacitors
6 Resistors
31 P-channel enhancement MOSFET
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC "0" = SW ON
LOGIC
INPUT
VO= Vs ___
R....
L __
3V
SWITCH
INPUT Sl
VS
= +10
LOGIC
INPUT
~~~
RL+ rOS(on)
SWITCH
OUTPUT
v <>-ll---O"l A....II-<>....- .....-o
l ' CL
IN1
r-'O-t- 5 pF
f - 1 MHz
1
-54
-50
1
1
10
100
-54
150
pC
-50
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
Logic Supply Current
Ground Current
1
VIN = 0 V or 5 V
Switch Duty Cycle < 10%
-1
-10
J.lA
IL
1
ICONO
1
1
-1
10
-10
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
f. Signals on Sx, Ox or INx exceeding V+ or V- will be clamped by Internal diodes. Limit forward diode current to 30 mAo
5-402
DG5140-5145
...... Siliconix
incorporated
~
DIE TOPOGRAPHY
OG5140
Pad
No.
82 mils
I
65 mils
16
15
~
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
V+ (substrate)
VL
GND
VIN
5
CSHCA/B
2 Capacitors
2 Resistors
8 P-channel enhancement M05FET5
lON-channel enhancement M05FET5
2 Diodes
OG5141
Pad
No.
82 mils
I
8
65 mils
9
10
11
12 13
20X
14
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
D,
NC
NC
NC
NC
NC
NC
D2
52
IN2
V+ (substrate)
VL
GND
VIN,
5,
CSHCA/B
4 Capacitors
4 Resistors
20 N-channel enhancement M05FET5
4 Diodes
16 P-channel enhancement M05FET5
5-403
DG5140-5145
WY'Siliconix
,.6;11 incorporated
DIE TOPOGRAPHY (Cont'd)
8
9
10
CSHCA
2 Resistors
4 Capacitors
11 P-channel enhancement M05FET5
15 N-channel enhancement M05FET5
2 Diodes
DG5143
8
..
-,
65 mils
9
10
16
15
~
CSHCA
8 Capacitors
30 N-channel enhancement M05FET5
4 Resistors
4 Diodes
22 P-channel enhancement M05FET5
5-404
Pad
No.
Function
1
2
3
4
5
6
D1
NC
D3
53
54
D4
NC
D2
52
7
8
9
10
11
12
13
14
15
16
I~
V+ (substrate)
VL
GND
VIN1
51
~
~
DG5140-5145
Siliconix
incorporated
DIE TOPOGRAPHY (Cont'd)
DG5144
•
Pad
No.
I
65 mils
16
10
15
12 13
14
~
20X
CSHCB
2 Resistors
4 Capacitors
11 P-channel enhancement MOSFETS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
Dl
NC
D2
S2
NC
NC
NC
NC
NC
NC
V + (substrate)
VL
GND
VINI
SI
15 N-channel enhancement MOSFETS
2 Diodes
DG5145
....1 - - - - 82
Pad Function
No.
mlls----I~
I
9
10
L..~~--~~-- --!:: "r
11
12 13
20X
__
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Dl
NC
D3
S3
S4
D4
NC
D2
S2
IN:!
V+ (substrate)
VL
GND
VINI
SI
CSHCB
8 Capacitors
30 N-channel enhancement MOSFETS
4 Resistors
4 Diodes
22 P-channel enhancement MOSFETS
5-405
DG5140-5145
Siliconix
incorporated
SWITCHING TIME TEST CIRCUITS
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
3V
LOGIC
INPUT
VS=IOVlor tON
Vs = -10 V lor 'OFF
+15 V
OV
RL + rDS(on)
SWITCH
INPUT
Vs
SWITCH
OUTPUT
OV
SWITCH
OUTPUT
LOGIC
INPUT
SWITCH
-vS
INPUT
OV
-IS V
(REPEAT TEST FOR IN2,1N3AND IN 4 )
Figure 1.
3V~
LOGIC
INPUT
oV
-.-7'
VSI
--:-:-~k=:::::;:;:::;)-
OU70
""-
SWITCH
OUTPUT 0 V
(REPEAT TEST FOR IN2 )
VS3------~--------_r-------
SWITCH
OUTPUT
+5 V
+15 V
RLI
300n.
l
CL3
35pF
GND 0 V
-IS V
Figure 2.
5-406
I
CLI
35 pF
--(Includes fixture and stray capacitance)
DG601
High-Speed Quad SPST
CMOS Analog Switch
tI'Y' Siliconix
~
incorporated
FEATURES
BENEFITS
APPLICATIONS
• Fast Switching Action
tON < 20 ns
tOFF < 35 ns
• Improved Data Throughput
• Fast Sample/Hold
• Reduced Switching Errors
• Precision Instrumentation
• Simplified Power Supply
• Computer Peripherals
• Reduced Switching
Transients
• Low Noise
Op Amp Gain Switching
• Simplified Interfacing
• Military Systems
• Low ON Resistance
(rDS(ON) < 30 n)
• Single-Supply Operation
(5 V to 12 V)
• Improved Reliability
• Low Charge Injection
(Q < 10 pC)
• TTL Compatible
• ESDS Protection >
±4000 V
DESCRIPTION
The DG601 is a high performance quad SPST CMOS
analog switch intended for applications where fast
switching, low charge injection and low ON
resistance are required. The DG601 features
single-supply operation, and is TTL-compatible with
either a single 12 V supply. a single 5 V supply. or
with 5 V supplies.
Applications for the DG601 include 12 V systems
requiring TTL or 5 V logic levels. such as disk drives
and other computer peripherals. The fast switching
time and low charge injection make the DG601 ideal
for high speed data acquisition applications such as
sample and hold amplifiers. channel selection and
gain ranging.
The DG601 is built on the Siliconix proprietary
PolyMOS process.
allowing 22 V rail-to-rail
maximum operation and low parasitic capacitance
to facilitate high speed switching. It is available in
16-pin plastic DIP and SO packages for industrial. D
suffix (-40 to 85°C). and in the CerDIP for military.
A suffix (-55 to 125°C) temperature ranges.
FUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION & TRUTH TABLE
Dual-In-llne Package
SO Package
v+
(Same pinout as DIP)
NO
1234567 8
Top View
Order Number:
DG601DY
Logic' 0 • S 0.8 V
Logic' 1 • f MINb MAXt UNIT
SWITCH
Analog Signal Range
C
Drain-Source
ON Resistance
Delta Drain-Source
ON Resistance
1,2,3
VANALOG
0
12
0
12
rOS(ON)
V+" 10.8
Is" 1 mA, Vo" 10 V, 2 V
1,3
2
30
50
30
50
llrOS(ON)
V+" 10.8
Is" -10 mA, Vo" 3 V, 9 V
1,3
2
3
5
3
5
IS(OFF)
Switch OFF Leakage
Current
I o (OFF)
V+" 13.2 V, V- " 0 V
Vo= 12.2 V, 1 V
Vs" 1 V, 12.2 V
1
2
-1
-100
1
100
-1
-100
1
100
1
2
-1
-100
1
100
-1
-100
1
100
1
200
-1
-200
1
200
IO(ON) +
IS(ON)
V+ " 13.2 V, V-" 0 V
Vs, VO " 1 V, 12.2 V
1
2
-1
-200
In8ut Current wlthVIN
L W
IlL
VIN Under Test" 0 V
All Other" 5 V
1,2
-10
Infcut Current with VIN
HGH
IIH
VIN Under Test" 5 V
All Other" 0 V
1,2
10
10
1
35
35
1
20
20
Channel ON
Leakage Current
V,
.n.
nA
INPUT
-10
.I1A
DYNAMIC
Turn-ON Time
Turn-OFF Time
Break-Before-Make
Time Delay
5-408
tON
RL,,300.o., C L ,,35pF
See Figure 1
tOFF
td
RL" 300.0., C L " 35 pF
1
15
ns
15
Preliminary
DG601
Siliconix
incorporated
PART 1
ELECTRICAL CHARACTERISTICS a
LIMITS
SYMBOL
PARAMETER
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
V+ = 12 V
SUFFIX
SUFFIX
V- = 0 V
3=-55, -40 ° C -55 to 125°C -40 to 85°C
GND = 0 V
VIN = 2.0, 0.8 V e
TEMP TYpd MINb MAX' MINb MAXt UNIT
DYNAMIC (Cont'd)
Charge Injection
Q
OIRR
Off Isolation
Crosstalk
(Channel-to-Channel)
Source-OFF Capacitance
CS(OFF)
Drain-OFF Capacitance
CD(OFF)
C L - 1,000 pF
Vgen = 6 V, Rgen = O.n
See Figure 2
1
R L = 75.0., C L = 5 pF
f = 1 MHz
1
Any Other Channel Switches
R L = 75.0., C L = 5 pF
f - 1 MHz
1
15
pC
dB
1
f = 1 MHz
Vs= 0 V
pF
1
CS(ON) +
CD(ON)
1
Positive Supply Current
1+
1,2
3
Negative Supply Current
1-
Drain and Source ON
Capacitance
15
SUPPLY
6
8
6
8
VIN = 0.0 V or 5.0 V
rnA
1,2
3
-6
-8
-6
-8
ELECTRICAL CHARACTERISTICS a
PART 2
LIMITS
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
V+ = 5 V
SUFFIX
SUFFIX
V- = -5 V
3=-55,-40°C -55 to 125°C -40 to 85°C
GND = 0 V
VIN = 2.0, 0.8 V e
TEMP TYpd MINb MAX' MINb MAX
UNIT
SWITCH
Analog Signal Range
C
Drain-Source
ON Resistance
Delta Drain-Source
ON Resistance
VANALOG
rDS(ON)
ArDS(ON)
Is(oFF)
PreHminary
V+ = 4.5 V, V- = -4.5 V
Is = -10 rnA, V D =±
V+ = 4.5 V, V- = -4.5 V
Is = -10 rnA, V D = 5,0, -5 V
ID(oFF)
V+ = 5.5 V, V- = -5.5 V
V D = ± 4.5 V
Vs=+4.5V
ID(oN) +
IS(ON)
V+ = 5.5 V, V- = -5.5 V
VS=VD = ± 4.5 V
Switch OFF Leal MINb MAXt
UNIT
SWITCH
Analog Signal Range
C
Drain-Source
ON Resistance
Delta Drain-Source
ON Resistance
VANALOG
1,2,3
5
a
5
rDS(ON)
V+ = 4.5 V
Is = -10 mA, V D = 2,3.5 V
1,3
2
100
125
100
125
ArDS(ON)
V+ = 4.5 V
Is = -10 mA, V D = 2,3.5 V
1,3
2
10
12.5
10
12.5
IS(OFF)
Switch OFF Leakage
Current
VD= 1 V
Vs= 4.5 V
1
2
-1
-100
1
100
-1
-100
1
100
V D = 4.5 V
VS= 1 V
1
2
-1
-100
1
100
-1
-100
1
100
1
200
-1
-200
1
200
V
n
V+ = 5.5 V
ID(OFF)
Channel ON
Leakage Current
a
nA
ID(ON) +
IS(ON)
V+ = 5.5 V
Vs =VD = 4.5, 1 V
1
2
-1
-200
IlL
VIN Under Test = 0 V
All Other = 5 V
1,2
-10
IIH
VIN Under Test = 5 V
All Other = 0 V
1,2
10
10
1
55
55
1
35
35
ns
15
pC
INPUT
~btJS Current with VIN
-10
.uA
Input Current with VIN
HIGH
DYNAMIC
Turn-ON Time
tON
RL = 300.0., C L = 35 pF
See Figure 1
Turn-OFF Time
tOFF
Break-Before-Make
Time Delay
td
RL = 300.0., C L = 35 pF
1
20
Charge Injection
Q
C L = 1,000 pF
Vgen = 2.5 V, Rgen = 0
See Figure 2
1
-15
Off Isolation
OIRR
Crosstalk
(Channel-te-Channel)
Source-OFF Capacitance
C S(OFF)
Drain-OFF Capacitance
CD(OFF)
Drain and Seurce ON
Capacitance
Preliminary
CS(ON) +
CD(ON)
n
RL = 75.0., C L = 5 pF
f = 1 MHz
1
Any Other Channel Switches
R L = 75.0., C L = 5 pF
f - 1 MHz
1
20
15
-15
dB
1
f = 1 MHz
Vs= 0 V
1
pF
1
5-411
DG601
B
Siliconix
incorporated
PART 3
ELECTRICAL CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
V+ = 5 V
SUFFIX
SUFFIX
V- = 0 V
3=-55,-40°C -55 to 125°C -40 to 85°C
GND = 0 V
VIN = 2.0,0.8 V e
TEMP TYpd MINb MA>f MINb MAXt UNIT
SUPPLY
Positive Supply Current
1+
= 5.5 V
= 0.0 V or 5.0
1,2
3
V+
VIN
Negative Supply Current
3
4
3
4
mA
V
1
2,3
1-
-3
-4
-3
-4
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
2, 7, 10, 15
3,6,11,14
1,8,9,16
13
4
5
DESCRIPTION
D
An Analog Channel Input or Output
S
An Analog Channel Il1put or Output
IN
Logic Control Input
V+
Positive Supply Voltage
V-
Negative Supply Voltage
GND
Digital Ground
SWITCHING TIME TEST CIRCUITS
Vo is the steady state output with the switch on. Feedthrough via switch capacitance may result
in spikes at the leading and trailing edge of the output waveform.
LOGIC 3.0V
INPUT
SWITCH
INPUT
v+
~ ~r<10ns
..J.
50%
~f
< 10 ns
OV
, ....
Vs
I- tOFF
--t;;;;;::;;:==::jr--
VS=2V
SWrrCH
INPUT
SWITCH OV
OUTPUT
Repeat tast for Ch 2, 3, 4
For load conditions. See Electrical Characteristics
~ (Includes fixture and stray capacitance)
NOTE:
logic Input waveform Is Inverted for
SWitches that have the opposite logic
Va
sense
= Vs
---=--RL
RL + rOS(ON)
Figure 1
5-412
Preliminary
~
~
DG601
Siliconix
incorporated
CHARGE INJECTION TEST CIRCUIT
+12V
V+
RGEN
~AA~~--f~--4-~O-~
ON
GND
OFF
V-
OV
-oV
V 1N =2.0V
Figure 2
BURN-IN CIRCUIT
16 n---+-~
~----n2
15
~----n3
14
.----4----1, 4
13 D---+-~
f----4------in 5
12
~----n6
11
~----n 7
10
B
Note: All Resistors are 10 k.n unless otherwise specified.
SO Package Is the same as the DIP.
9
V+ = 12 V
Preliminary
5-413
DG90S/gOg
a-Channel/Dual 4-Channel Fault
Protected CMOS Analog Multiplexers
APPLICATIONS
FEATURES
BENEFITS
• All Channels OFF When
Power OFF, For Analog
Signals Up to ± 25 V
• Increased Reliability
and Ruggedness
• Any Channel Turns OFF If
Input Exceeds Supply
Rails
• Fast Switching (300 ns max)
• Break-Before-Make
Switching
• TTL And CMOS Compatible
.... Siliconix
incorporated
~
• Power-Down and
Overvoltage Protected
• Increased Throughput Rate
• Channels Remain Isolated
When A Fault Condition
Occurs
• Avionics
• Data Acquisition
Systems
• Industrial Process
Control Systems
• High-Rei Control
Systems
• Audio Signal Routing
• Simplified Logic
Interface
DESCRIPTION
The DG908 and DG909 are 8-channel and dual
4-channel, respectively, dielectrically isolated
CMOS monolithic analog multiplexers. These
multiplexers are pin and function compatible with
the DG508A/DG509A and similar devices, but add
power-down, overvoltage and fault protection
features. A series N-P-N MOSFET switch structure
ensures"that OFF channels will stay OFF even if the
inputs exceed the supply rails by up to ±35 V. An
ON channel will be limited to an output level of
about 1.5 V less than the supply rails, thus
affording protection to any following circuitry.
Binary 3-bit address and Enable inputs allow
selection of any or none of the channels. All logic
inputs are TTL compatible for easy logic interface;
the Enable input also facilitates MUX expansion and
cascading.
The DG908 and DG909 are intended for applications
where the multiplexer inputs must look directly to
the outside world, such as data acquisition system
front ends, and other analog multiplexing
applications where high device ruggedness is
required.
Packaging options include the 16-pin plastic DIP for
operation over the industrial, 0 suffix (-40 to 85°C)
temperature range, and the 16-pin CerDIP for
military, A suffix (-55 to 125°C) temperature
operation.
PIN CONFIGURATION
Dual-In-Llne Package
Dual-In-Llne Package
Top View
Top View
AO
1
EN
vSlb
S2b
1 S3b
Order Numbers:
CerDIP: DG908AK
Plastic: DG908DJ
5-414
---,.---
S4b
Db
Order Numbers:
CerDIP: DG909AK
Plastic: DG909DJ
Preliminary
~
~
DG90S/909
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
V-
V+
GND
V+
V-
GND
Slo-t---------------~~,.,
Slao-t---------------~~,.,
S2o-t-------------~~,~_1
S2ao-t-----------~,A---_r_+
S3o-t-----------~~·_r_r_1
S3ao-t-----~Yr·~--r_--_r_+
s4o-t---------~~A,__r~_1
S4ao-+-~I~--~----~--~-J
S5o-t-------~r,~,_1_~~_1
o
Slbo-+---r_--~----r-~~.,
S6o-t------o,~+_4-4-~~_1
S2bo-r_~~--~--~rA---~~
S7o-~--~,A-r_~~~~~_+
S3bo-r_~~~~·--~r_--~~
S8o-t-~I~r-+_+_;_;__r_r-J
S4bo-r_~~A---~--~~--,_~
A2
Al
Ao
Al
EN
DG908
8-Channel Single Ended Multiplexer
Da
Ao
EN
DG909
Differential 4-Channel Multiplexer
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
DG908AK
-55 to 125°C
DG908DJ
-40 to 85°C
DG909AK
-55 to 125°C
DG909DJ
-40 to 85°C
PACKAGE
CerDIP
•
PDIP
CerDIP
PDIP
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VV+ •..••••...•••.•••...•.••........•.....•.•.. 44 V
GND .••.•..••••••..••.•.••.••.••.••..•.••••.. 25 V
VEN, VA Digital Input •..•.•.••... (V-) -4V to (V+) +4 V
V s , Analog Input Overvoltage
With Power ON ..•.•.••.•..•. (V-) -20 V to (V+) +20 V
Vs, Analog Input Overvoltage
With Power OFF ...................... -35 V to +35 V
Continuous Current, S or 0 .................... 20 mA
Peak Current, S or 0
(Pulsed at 1 ms, 10% duty cycle max) ••••••••.. 40 mA
Operating Temperature (A Suffix) •.....•.. -55 to 125·C
(0 Suffix) .......... -40 to 85·C
Storage Temperature (A Suffix) ..•••...... -65 to 150·C
(0 Suffix) •••...•.•• -65 to 125·C
Power dissipation (package)·
16-Pln Plastic DIp·· ......................... 600 mW
16-Pln CerDIP··· ........................... 900 mW
All leads soldered or welded to PC board.
•• Derate 6.3 mW/·C above 25·C
••• Derate 12 mW/·C above 75·C.
CAUTION
Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These are stress ratings only. and
functional operation of the device at these or any
other conditions above those indicated in the
Preliminary
operational sections of the specifications is not
implied, Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
5-415
DG90S/gOg
WY'Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
LIMIT!,!
Test Conditions
Unless Otherwise Specified: 1=2S·C
A
D
2=12S,8S·C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-S5,-40·C
-55
to
125°C
-40
to
85°C
GND = 0 V
VAL = 0.0 V,VAH =2.4V
b
b
TYpd
MIN MAXb MIN MAXt UNIT
TEMP
SYMBOL
PARAMETER
.
;
SWITCH
Analog Signal Range C
ON Resistance"
rOS(ON)
rOS(ON) Match
Between Channels f
rOS(ON)
t:..
Source OFF
Leakage Current
1,2,3
VANALOG
DG900
13
-13
13
V
600
900
600
900
.0.
10
10
%
Vo =±10 V, VAL = 0.0 V
10 = -100J1A
1
2,3
Vs = 0 V, 10 = -100J1A
1
5
Vs= ±10 V
VO= +10 V
1
2,3
0.02
-0.5
-50
0.5
50
-0.5
-50
0.5
50
Vo= ±10 V
Vs= +10 V
1
2,3
0.02
-1
-lOP
1
100
-1
-100
1
100
Vo= ±10 V
Vs= +10 V
1
2,S
0.04
-0.5
-50
0.5
50
-0.5
-50
0.5
50
1
2,3
0.1
-2
-100
2
100
-2
-100
2
100
1
2,3
0.05
-1
-50
1
50
-1
-50
1
50
V+ = V- = VEN = Vo = 0 V
VA=OV, Vs=±25V
1
1
2
5
Vs= ±25 V
VO= ±10 V
1
1
2
10
0.0
0.0
Is (OFF)
Drain OFF
Leakage Current
-13
VEN = 0 V
10(OFF)
DG909
DG908
Drain ON
Leakage Current
10(ON)
DG909
Sequence Each Switch ON
VAL = 0.0 V, V AH = 2.4 V
Vs =Vo=±10 V
nA
FAULT PROTECTION
Is with Power OFF
IS(OFF) with Overvoltage
J1A
INPUT
Input LOW Threshold
VAL
1,2,3
Input HIGH Threshold
V AH
1,2,3
2.4
1
2,3
-1
-30
V
Logic Input Current
IA
V A =2.4VorO.OV
2.4
1
30
-1
-30
1
30
J1A
O.S
J1S
DYNAMIC
SWitching Time of
Multiplexer
tTRANS
1
tOPEN
1
Enable Tum ON Time
tON(EN)
1
0.6
0.6'
Enable Tum OFF Time
tOFF(EN)
1
0.3
O:S
Break-Before-Make
Interval
0.3
40
40
ns
J1S
5-416
Preliminary
DG90S/909
W7' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
A
0
2=125,85·C
SUFFIX
SUFFIX
V+ = 15 V, V- = -15 V
3=-55,-40·C
-55
to
125°C
-40
to
85°C
GND = 0 V
VAL = 0.8 V, VAH =2.4V
b
b
TEMP TYpd MIN MAXb MIN MAXt UNIT
SYMBOL
PARAMETER
DYNAMIC
.
(Cont'd)
Settling Time
0.1 %
1
1
0.01%
1
3
VEN = 0 V, RL = 200.0.
CL = 3 pF, Vs= 3 VRMS
f = 500 kHz
1
60
1
5
1
25
1
12
1
0.1
1
30
1
17
JJ,S
ts
OFF Isolation
Source OFF Capacitance
VEN = 0 V
f = 140 kHz
DG90B
Drain OFF
Capacitance
Vs = 0 V
CS(OFF)
CO(OFF)
dB
Vo= 0 V
DG909
pF
Input to Output Capacitance
CDS(OFF)
DG908
ON State Input
Capacitance
..
CS(ON)
DG909
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
1,2
3
0.4
0.6
0.4
0.6
mA
VEN=OV, VA=OV
1,2
3
-0.4
-0.6
-0.4
-0.6
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Sequence each switch ON.
_ (rOS(ON) MAX - rOS(ON) MIN)
f. A rOS(ON) rOS(ON) AVE
Preliminary
5-417
DG90S/909
...... Siliconix
incorporated
~
TRUTH TABLES
00908
00909
A2
Al
Ao
EN
SW9.f'CH
Al
Ao
EN
~.f'CH
X
X
X
0
NONE
X
X
0
NONE
0
0
0
1
1
0
0
1
1
0
0
1
1
2
0
1
1
2
0
1
0
1
3
1
0
1
3
0
1
1
1
4
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
Logic '0" = VAL S 0.8 V, Logic "1" = VAH l!: 2.4 V
5-418
Preliminary
G118
IrF Siliconix
~
incorporated
Monolithic 6-Channel
Enhancement-type MOSFET Switch
FEATURES
BENEFITS
APPLICATIONS
•
Internal Zener Diode
Protects the Gate
•
•
Switching Analog Signals
•
Multiplexing
•
Six Switches Per Chip
•
Designed to Operate with
0125,0129 and 0139
Reduces External
Component Requirements
DESCRIPTION
The G118 contains six enhancement-mode Pchannel MOSFETs designed to function as analog
switches. In the ON state each switch will conduct
current equally well in either direction, and in the
OFF state each switch will block voltages up to 20 V
peak-to-peak. The switches are integrated on a
common substrate (body). They have a common
drain terminal (D) which will function equally well as
a common source; likewise, the source terminals
will function as drains.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
..
Flat Package
G1~~14
G2
G3
G4
2
3
4
13
12
11
G5
5
ro
G6
6
9
B(V+)"
o
I
I
Top View
Order Number: G118AL
Dual-In-Llne Package
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
I
I ~
I
I
I
I
I
I
I
I
I
I
I
I
6
6
I
I
I
I
I
I
~
I~.L-
I
I
I
o o
I
I
I
6
Order Numbers: G118AP or G118BP
W
Common to Substrate and Base of Package
Not Recommended for New Designs
5-419
G118
.... Siliconix
Incorporated
~
ABSOLUTE MAXIMUM RATINGS
VStoVB •...••...•...•••.•••••••.•••..•..•••.. 2V
VBtoVS ...•.....••..•.•••••.•••.•.........•. 30V
VD toVB ..•••••••••••.•.•...•...••.••••••..... 2 V
VB toVD •..••.••••••...••.•••....•.••••.••••• 30 V
±30 V
VD toYs
Vs toVD . " : " . " •. " .•. " . " •. " .. " " " ... ±30 V
VBtoVG ••••••••••.•....•..•....•..•••......• 35V
Is.ID .•.•.•.•..•••.••.•••......•...•...••.. 100 rnA
IG •...•...••..•••.••..•••..•.••..••.•..••.••. 5mA
Storage Temperature .•..••.••.•..•.•.••. -65 to 150°C
Operating Temperature (A Suffix) .•...•... -55 to 125°C
(8 Suffix) •.•••••••• -25 to 85°C
Power Dissipation'
Flat Package" ••...•.••••••..••..•••.•••... 750 mW
14-Pln DIP'" .•...•..•••.••....•..••••••.•• 825 mW
All leads soldered or welded to PC board.
•• Derate 10 mW/oC above 75°C.
••• Derate 11 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
Test ConditIons
Unless Otherwise Specified:
VOB" 0 V
VPB = 0 V
PARAMETER
SYMBOL
LIMITS
1=25°C
A
B
2=125,85'C
SUFFIX
SUFFIX
3=-55,-25'C -55 to 125°C -25 to 85°C
TEMP TYpd MINb MAX' MINbMAX t
STATIC
Drain-Source
ON Resistance
..
rOS(ON)
Is=-1mA
VOB = 0 V
VGo= -30 V
1,3
2
100
125
125
150
VOB = -10 V
V Go =-20V
1,3
2
200
250
250
300
V OB = -20 V
VGo= -10 V
1,3
2
450
600
500
600
Source OFF
Leakage Current
IS(OFF)
Vso = -20 V
VGo= 0 V
1
2
-0.5
-500
-0.5
-500
Drain OFF
Leakage Current
10(OFF)
Vos= -20 V, VGo= 0 V
VS B = 0 V
1
2
-3
-3000
-10
-1000
Gate-Channel
Leakage Current
IGSS
VGB = -20 V
1
2
-0.5
-500
-5
-500
VGS(th)
10 " -10AA, VOG = 0 V
VSB = a V
1,2,3
-4
Drain-Source
Breakdown Voltage V(BR)OSS
10" -50AA, VGS = a V
VSB = 0 V
1,2,3
-30
-30
Source-Drain
Breakdown Voltage
V(BR)SOS
Is = -10AA, VGO = a V
1,2,3
-30
-30
Gate-Body
Breakdown Voltage
V(BR)GBS
IG= -10AA
1,2,3
Gate-Source
Threshold Voltage
UNIT
-1.5
-4
.0.
nA
-1.5
V
-90
-35
-90
-35
DYNAMIC
Gate-Source
Capacitance
Cgo
Gate-Drain
Capacitance
Cgd
Drain-Source
OFF Capacitance
5-420
Cds (off)
VGB = a V
f = 1 MHz
VOB =VSB = 0
Body Guarded
Drain Guarded
1
0.9
Source Guarded
1
0.9
Gate Guarded
1
0.4
pF
Not Recommended for New Designs
G118
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V OB = 0 V
VPB = 0 V
PARAMETER
SYMBOL
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55,-25°C -55 to 125°C -25 to 85°C
TEMP TYpd MINb MA>f MINbMAX t
UNIT
DVNAMIC (Conl'd)
Source-Body
Capacitance
Csb
V OB = 0, V SB = -5 V
Drain and Gate Guarded
Drain-Body
Capacitance
Cdb
VSB = 0, V OB = -5V
Gate and Source Guarded
1
2.0
1
12
pF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design. not sublect to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
..
Not Recommended for New Designs
5-421
..... Siliconix
incorporated
G119
~
Monolithic 6-Channel
Enhancement-type MOSFET Switch
FEATURES
BENEFITS
APPLICATIONS
•
•
•
Differential Input Analog
Signal Switching
•
Multiplexing
•
Designed to Operate with
0125. 0129 and 0139
Integrated MOSFET for
Each Gate to Provide
"Pull-UP" Current for
Gate-Driver Circuit
Reduces External
Component Requirements
e Internal Zener Diode
Protects the Gate
•
Six Switches Per Chip
•
Low rOS(ON) (100 n)
DESCRIPTION
The G119 contains six enhancement-mode
P-channel MOSFETs designed to function as analog
switches. In the ON state each switch will conduct
current equally well in either direction. and in the
OFF state each switch will block voltages up to 30 V
peak-to-peak. The switches are integrated onto a
silicon substrate (body) and are internally
connected into two groups of three switches per
group. This arrangement facilitates the switching or
multiplexing of differential analog signals. Each
group has a common drain terminal (01 and 02)
which will function equally well as a common
source. Each gate terminal (G) controls a pair of
switches and is provided with a normally-OFF
"pull-up" MOSFET which may be turned ON to
provide a current source to the gate-driving circuit.
The pull-ups are turned ON or OFF by connecting
the .. P" terminal to a negative supply or to the .. B"
terminal respectively.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
G1
Flat Package
D1
P
G1
G3
G5
B(V+)W
1
2
3
4
5
6
14
13
12
11
10
9
D2
Sl
S:3
S5
S6
S4
S2
NO
Top View
pO
S10
S3 0
S5 0
Order Numbers:
G119AL or Gl19BL
• Common to Substrate and Base of Package
5-422
S6 0
Gs
c~ cU rU
I
I
""1--!
I
I
I
I
S 2 o----o-...L...!
S4 0
G3
I
I
+
I
I
I
"'*
o
B(V+)
I
0° 1
1
I
~
I
:I
o.J.....:
I
I
o
02
Not Recommended for New Designs·
G119
ft'Y' Siliconix
~
incorporated
ABSOLUTE MAXIMUM RATINGS
VB to Vs ................................. -2 to 30 V
Ip ........•................................ 100 JJ.A
VB to Vo ................................. -2 to 30 V
Storage Temperature .................... -65 to 150°C
Vo toYs ..................................... ±30 V
Operating Temperature (A Suffix) .....•... -55 to 125°C
(B Suffix) .....•.... -25 to 85°C
VB toV G, VB toVp ............................. 35 V
Power Dissipation' .......................... 750 mW
Is,lo ...................................... 100 mA
I G ············································5mA
All leads soldered or welded to PC board.
Derate 10 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V OB = 0 V
VpB = 0 V
PARAMETER
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -25 ° C -55 to 125°C
TEMP TYpd
SYMBOL
MINb MAX'
B
SUFFIX
-25 to 85°C
MINb MAXb UNIT
STATIC
Drain-Source
ON Resistance
rOS(ON)
Is=-1mA
VOB = 0 V
VGO= -30 V
1,3
2
100
125
125
150
V OB = -10 V
VGo= -20 V
1,3
2
200
250
250
300
V OB = -20 V
VGO = -10 V
1,3
2
450
600
500
600
Source OFF
Leakage Current
IS(OFF)
Vso = -20 V
V GO = 0 V
1
2
-0.5
-500
-5
-500
Drain OFF
Leakage Current
I o (OFF)
VOS = -20 V, VGO= 0 V
V SB = 0 V
1
2
-1.5
-1500
-10
-1000
Gate ON Currents
IG(ON)
V GB = -30 V
V PB = -30 V
1
-2.4
IGSS
V GB = -20 V
1
2
-0.5
-500
Gate-Source
Threshold Voltage
VGS(th)
10=-10JJ.A,VOG =OV
V SB = 0 V
1,2,3
-4
Drain-Source
Breakdown Voltage
V(BR)OSS
10 = -50JJ.A, VGs= 0 V
V SB = 0 V
1,2,3
-30
-30
Source-Drain
Breakdown Voltage
V(BR)SOS
Is= -1 oJJ.A , VGo= 0 V
1,2,3
-30
-30
Gate-Body
Breakdown Voltage
V(BR)GBS
IG= -10JJ.A
1,2,3
-90
-35
-90
-35
Pull-Up Gate-Body
Breakdown Voltage
V(BR)PBS
I p =-10JJ.A
V GB = 0 V
1,2,3
-90
-35
-90
-35
Gate-Channel
Leakage Current
-0.8
-2.4
nA
-0.8
-5
-500
-1.5
-4
.0.
mA
nA
-1.5
V
Not Recommended for New Designs
5-423
~
G119
~
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
VOB = 0 V
VpB = 0 V
PARAMETER
SYMBOL
LIMITS
1=2S·C
A
B
2=12S.8S·C
SUFFIX
SUFFIX
3=-SS.-2S·C -S5 to 125°C -25 to 85°C
TEMP TYpd MIN b MA>f MINb MAXt UNIT
DVNAM1Ce
Gate-Source
Capacitance
Gate-Drain
Capacitance
Drain-Source
OFF Capacitance
Cgs
Cgd
Cds (off)
VaB = 0 V
f = 1 MHz
VOB =VSB = 0
Body Guarded
Drain Guarded
1
1.8
Source Guarded
1
1.8
Gate Guarded
1
0.4
Source-BodY
Capacitance
CBb
V OB = O. V SB = -5 V
Drain and Gate Guarded
1
2.0
Drain-Body
Capacitance
Cdb
V SB = O. V OB = -5V
Gate and Source Guarded
1
6.0
pF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. VaB = 0 V. f = 1 MHz.
5-424
Not Recommended for New Designs
Si3002
Monolithic SPOT MOS
Switch with Driver
..... Siliconix
incorporated
~
APPLICATIONS
BENEFITS
FEATURES
•
Internal Gate Protection
Zener Diodes
•
TIL and Compatible
Input
•
Reduces External
Component
Requirements
•
Easily Interfaced
•
Switching Analog
Signals
DESCRIPTION
"0" at the driver input, a common drain (D) is
connected through an ON switch to source (S 1) .
With logic "1 " at the input, "D" is connected to S 2 •
Switch action is make-before-break.
The Si3002 contains two P-channel MOS field-effect
transistors designed to function as single-pole
double-throw analog switches. A level-shifting
driver enables a lOW-level input (0.8 to 2 V) to
control the ON-OFF state of the switches. In the ON
state, each switch will conduct current equally well
in either direction. In the OFF state the switches will
block voltages up to 20 V peak-to-peak. With logic
The Si3002 is available in 10-pin metal can and
14-pin side braze DIP for operation over the
military, A suffix (-55 to 125°C) and the industrial,
a suffix (-25 to 85°C) temperature ranges.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Metal Can Package
Top View
v+
NC:~:D
NC3W.7S1
IN4
5
6 V_ (SUBSTRATE AND CASE)
VA
Order Number:Sl3002AA
Dual-ln-L1ne Package
NC
NC
VA
IN
v-
v+
NC
One SPOT Switch per Package'
NC
S2
Top View
'Switches Shown for Logic "1" Input
Order Numbers: SI3002AP, SI3002BP
Not Recommended for New Designs
5-425
tI"P'
Si3002
~
Siliconix
incorporated
ABSOLUTE MAXIMUM RATINGS
V+ to V- .....••....................•......... 36 V
Storage Temperature .................... -65 to 150·C
V+ toYs orVo ................................ 25 V
Operating Temperature (A Suffix) ..•...... -55 to 125·C
(8 Suffix) ..•....... -25 to 85·C
V+ toVR orVIN
........•..........•........... 12 V
Vo to V- ••.••................................. 36 V
Vs to V- .........•...•........................ 36 V
VotoVs .............•......•................ ±25V
VIN toVR .•.........•..•.....................•. 6 V
CURRENT, (Any Terminal) ..................... 30 mA
Power Dissipation (Package)"
Metal Can"" ....................•........•.. 450 mW
14-Pln DIP""" .....•......•................. 825 mW
Device mounted with all leads soldered or welded to PC
board.
Derate 6 mW/·C above 75·C.
""" Derate 11 mW/·C above 75·C.
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
Analog Signal Range
C
LIMITS
Test Conditions
1=25·C
A
B
Unless Otherwise Specified:
2=125,85·C
SUFFIX
SUFFIX
V+ = 10 V
3=-55,-25·C
-55
to
125°C
-25
to
85°C
V- = -20 V
VR= 0 V
b
TEMP TYpd MIN MA>f MINbMAX t
1,2,3
VANALOG
Vo = 10 V
Drain-Source ON
Resistance
rOS(ON)
Vo=OV
Is = -1 mA
V INL = 0.8 V
VINH = 2.0 V
Vo= -10 V
Source OFF Leakage
Current
IS(OFF)
Channel ON Leakage
Current
IO(ON) +
IS(ON)
Vs= -10 V
Vo = 10 V
Vo= -10 V
Is = 0
VINL = 0.8 V
VINH = 2.0 V
-10
10
-10
10
1,3
2
100
150
100
150
1,3
2
150
250
150
250
1,3
2
400
500
400
500
1
2,3
-1
-1000
-5
-100
1
2,3
-2
-2000
-10
-200
-0.8
-0.6
-1.0
-0.8
-0.8
-1.0
UNIT
V
.n
nA
INPUT
I~ut Current
( oltage LOW)
IINL
VIN = 0 (SW10N)
1
2
3
I~ut Current
( oltage HIGH)
IINH
VIN = 0 (SW 2 ON)
1,3
2
0.1
10
0.1
10
1
1
1
1
1.5
1.5
mA
J.lA
DYNAMIC
Turn-ON Time
tON
See Switching Time
Test Circuit
Turn-OFF Time
Source OFF Capacitance
5-426
tOFF
CS(OFF)
V s =0,f=1 MHz
J.ls
1
6
pF
Not Recommended for New Designs
Si3002
...,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a (Cont'd)
PARAMETER
SYMBOL
Positive Supply Current
1+
Negative Supply Current
1-
LIMITS
Test Conditions
1=25·C
A
B
Unless Otherwise Specified:
2=125,85·C
SUFFIX
SUFFIX
V+ = 10 V
3=-55,-40·C -55 to 125°C -25 to 85°C
V- = -20 V
VR = 0 V
TEMP TYpd MINb MAX' MINb MAXt UNIT
1
3.5
1
-3.0
-3.0
I REF
1
-0.1
-0.1
Positive Supply Current
1+
1
Negative Supply Current
1-
Reference Supply Current
VIN=OV
3.0
mA
Reference Supply Current
V1N =5V
I REF
3.0
3.5
1
-3.0
-3.0
1
-1.5
-1.5
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, Is used in
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant
with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo
is the steady state output with switch on.
Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output
waveform.
tOFF: Vs= -10 V
tON: Vs= +10 V
t r < 10 ns
tf<10ns
LOGIC
INPUT 0 V
S1
SWITCH
INPUT
10 V
r-----~
D
SWITCH
OUTPUT
o-t----O-;""---.,.-+-<>--t--~VOUT
S2
Sf~~~~ Vs ==::j:==~~=~q==~-;:=
SWITCH
OUTPUT 0 V
---t---..../
VOUT =V s
Not Recommended for New Designs
RL
R L+ r DS(ON)
5-427
Data Conversion . .
~
~
SlIIconix
Incorporated
TABLE OF CONTENTS
Introduction ....•••.•..•.•.••.•..•......•.•..••.........•....••••••••••••••••...•... 6-1
LD11 01111 A: 3 1I2-Dlglt AID Converter Set •..•.••.•.....••..•••.•.•.••..•........•...... 6-4
LD120/121A: 4 1/2-Dlglt AID Converter Set ............................................. 6-10
LD122/121A: 4 1I2-Dlglt AID Converter Set ..•....••..•...........•...•.•..••.......••.. 6-16
512504: 12-Blt CMOS SAR •••..•.....•.....•..•••••.••....•...•....•....•...•... : .•.. 6-22
S17135: Precision 4 1/2-Dlglt Single Chip CMOS AID Converter •.........•....••.••.••.••.. 6-31
S17240: 12-Bit CMOS Voltage-Output DAC .............................................. 6-43
S17533: CMOS 10-Blt Multiplying DAC .................................................. 6-51
S17541: CMOS 12-Blt Multiplying DAC .................................................. 6-58
S17541A: CMOS 12-Blt Multiplying DAC ................................................. 6-67
SI7542: Microprocessor-Compatible 12-Bit CMOS Multiplying DAC •.••.•.....•.•........•... 6-76
Si7543: CM05 12-Bit Serial Input DAC ................................................. 6-90
517545: CMOS 12-Blt Buffered Multiplying DAC ......................................... 6-104
517820: CMOS Subranging 8-Bit AID Converter .•....•.•..•....•...•.•...•..••.•..•...•. 6-120
Si8601/03: 8-Blt Data Acquisition Systems .........•..•...•.•.•.•...........•.......... 6-130
S18602/04: 8-Blt Data Acquisition Systems ..•.••.••..•..•................•.....•..•...• 6-141
..w" Siliconix
.,/1;11 incorporated
DATA CONVERSION
INTRODUCTION
Siliconix manufactures a variety of data conversion devices, including 12-bit digital-to-analog converters (DACs,
or D/As) , 8-bit data acquisition systems (DASs), high resolution integrating analog-to-digital converters (ADCs,
or AIDs), and a high speed 12-bit successive approximation register (SAR). This section of the data book
includes the complete spectrum of Siliconix data conversion components.
Digital-to-Analog Converters
Siliconix offers the industry-standard Si75XX family of 10- and 12-bit CMOS multiplying DACs, including the
Si7533, Si7240, Si7541, Si7541 A, Si7542, Si7543 and Si7545 devices. This family is based on the Siliconix
proprietary PolyMOS·· process, utilizing highly stable thin-film resistors which are laser-trimmed for excellent
accuracy. Each of these devices features improved dynamic performance over the industry-standard products
in this family, having been designed for reduced glitch impulse, reduced propagation delay, and improved
settling time.
Data Acquisition Systems and Analog-to-Digital Converters
The Siliconix proprietary Si860X family are 8-bit data acquisition systems with 25 microsecond conversion times.
The Si8601 is an 8-bit 8-channel system intended for 5 V single-supply operation, with a 5 Volt analog range.
The Si8602 is the 15 V version of the Si8601, intended for military applications and other systems that need a
10 Volt signal range. The Si8603 and Si8604 are low-cost single-channel versions of the Si8601 and Si8602
respectively. Each of these data acquisition systems and AIDs contain on-board sample and hold functions and
microprocessor interfaces to simplify design and reduce board space and component count .
The Si2504 is a high-speed, low-power successive approximation register which is used as a building block in
custom and hybrid high-performance 12-bit AID converters. It features improved clock rate (to 40 MHz, compared with the 25 MHz industry-standard), and reduced supply current (10 mA, compared to the industry-standard 100 mAl to allow faster and more efficient custom AID converter design.
High Resolution AID Converter Systems
Siliconix pioneered the development of monolithic AID converters for display applications in the early 1970's
with the LD110/111 quantized feedback 3 1/2-digit AID converter chip set. Today, Siliconix offers improved
resolution and accuracy in display converters up to the 4 1I2-digit (approximately 15 bit) level, with the
LD120/121A, LD122/121A chip sets and the single-chip Si7135. The Si7135 is the premium monolithic 41/2-digit
converter available, offering improved linearity and reduced rollover error compared to the generic 7135 converter.
6-1
..
~
~
Siliconix
incorporated
GLOSSARY OF TERMS
Accuracy
May be specified in absolute and/or relative terms.
Absolute accuracy is interpreted as a measure of the
total error of the converter, and is expressed in
terms of the difference between the actual analog
output and the output expected for a given input digital code. Relative accuracy, on the other hand, is
more an interpretation of the non-linearity of the converter and is specified in terms of the difference between the actual analog output and t~e output expected (based on the relative, or actual full scale
output of the converter) for a given input code.
Absolute accuracy measurements should be made
under a set of standard conditions, with the signal
sources and measuring equipment traceable to
some acceptable standard. The error is specified in
LSB or percent of full scale range.
Compliance Voltage
For a current output D/A converter, this is the maximum voltage range on the output terminal over which
the current output of a DAC can vary for the DAC to
meet an absolute accuracy as specified (usually
±1/2 LSB).
Differential Linearity (DNl)
The measured difference in output between any two
adjacent digital codes should be exactly 1 LSB (or
F.S. X 2-n for an n-bit converter.) Any deviation
from the ideal difference is called differential nonlinearity, and is expressed in submultiples of an ~SB.
Differential linearity errors greater than 1 LSB can result in non-monotonic performance in a D/ A converter, and missing codes in an A/D converter.
Feedthrough
An AC specification for a multiplying DAC which defines the frequency at which a specified peak-to-peak
AC signal is seen at the DAC output with all bits in the
OFF state. It is usually specified as %, ppm, or fractions of an LSB for a given set of input conditions.
Four Quadrant
For a multiplying D/A converter, "four quadrant"
means that both the reference signal and the number
6-2
represented by the digital input signal may be of
either polarity. The converter is expected to obey the
rules of multiplication for algebraic sign.
Gain
The gain of the converter is the analog scale factor
that describes the nominal conversion relationship
between the converter's full scale output and its analog (or reference) input. The gain is generally adjustable by the user (externally) to full scale X (1-2- n )
with all bits ON. For bipolar operation adjust output to
F.S. [1_2-(-n-1)] with all bits ON.
least Significant Bit (lSB)
In a binary numerical system, the LSB is the bit that
represents the least, or smallest, value. For example, in the natural binary number 1101 (decimal 13,
or 23 + 22 + 01 + 20), the right-most digit is the
LSB. It thus represents the smallest analog change
that can be resolved in an n-bit converter and is
equal to the full scale output range divided by 2n
where n = number of bits, LSB = FS/2 n .
Linearity
Linearity error of a converter, which implies the integral linearity error, is the deviation of the analog output from an ideal straight line, and is usually specified in % or ppm of the Full Scale range or submultiples of 1 LSB. The straight line can be either a "best
straight line", or "end point". The former is derived
empirically by manipulating the offset and/or gain of
the converter to minimize the deviations of the actual
analog output from the manipulated best line. The
latter assumes the idealized line passes through the
"end points" of the converter after it has been calibrated (zero and full scale).
Monotonicity
A D/ A converter is said to be monotonic if the output
either increases or remains constant with increasing
digital input codes. The statement monotonic (over
temperature) is sometimes substituted for a differential non-linearity specification as a DNL specification
of 1 LSB is not a sufficient condition for monotonic
behavior.
111'7' Siliconix
.J/JII Incorporated
Most-Significant Bit (MSB)
Stability
In a binary numerical system, the MSB is the bit that
represents the largest value, or weight. For example,
in the natural binary number 1101 (decimal 13, or 23
+ 22 + 01 + 20), the leftmost digit (or" 1") is the
MSB. Its analog weight, relative to full scale, is FS/2.
In bipolar applications the MSB also indicates the polarity of the number represented by the rest of the
bits.
The stability of a converter is usually related to
changes in its characteristics as a function of temperature and time. While such measurements are
difficult and time consuming, those related to temperature are often sufficiently critical to warrant their
inclusion in the characteristic data. (See also Temperature Coefficient.)
Switching Time (Propagation Delay)
Offset (Zero Scale Error)
The measured analog output when the digital input
code corresponds to an analog value of zero. Generally expressed as a percentage of Full Scale range
but is also expressed in ppm, LSB's or in units of
current or voltage.
In a O/A converter the switching time is the time it
takes for the logic and switches to change from one
state (ON or OFF) to the other. It includes delay and
rise time, but does not include settling time, and is
measured from the 50% point of the logic input to the
50% point of the changing analog ouput signal.
Temperature Coefficient
Resolution
The number of states (2") that the Full Scale range
may be divided into or resolved, where n = number
of bits. This is usually expressed as a number of
bits (n).
Settling Time
The elapsed time for the analog output to reach its
final value within a specified error band after the corresponding digital input code has been changed. It is
usually specified as a Full Scale range change and
measured from the 50% point of the digital input
code change to the time the output reaches the final
value within the specified error band.
In general, temperature coefficients are expressed
as fractions of an LSB/oC and then over the rated
temperature range. The temperature coefficient (or
T.C.) can then be defined as the change in the parameter divided by the corresponding temperature
change, and is usually specified for gain, offset and
linearity parameters.
-~
Zero and Gain-Adjustment Principles
For unipolar applications first adjust the 01 A converter for zero output with all bits OFF. Then with all bits
ON, adjust the output for full scale - 1 LSB.
For bipolar applications, in offset binary, adjust the
O/A converter's "zero" for negative full scale with all
bits OFF. Then with all bits ON set the gain for full
scale - 2 LSB.
6-3
LD110/111A
..,. Siliconix
,,1;11 incorporated
3 1/2-Digit AID Converter Set
FEATURES
BENEFITS
APPLICATIONS
• Buffered Reference Input
• High Gain Stability
• High Performance Digital
Voltmeters
• MOSFET Input
• Reduced Signal Loading
• Auto-Zero System
• Reduced Offset and Drift
Over Temperature
• Auto-Polarity
• Over and Under Range
Signals
• Reduced External
Parts Count
• Easily Interfaced
• Digital Panel Meters
• Digital Instrumentation
Readouts
• ~P AID Interface
Subsystem
• Auto-Zeroed Microvolt or
Strain Gauge Systems
DESCRIPTION
The LD11 0 and LD111 A form a precision 3 1/2 digit
AID converter system for use in display and
microprocessor based data acquisition applications. Based on Siliconix's "Quantized Feedback"
technique, intrinsic features include auto-polarity,
auto-zero, and ratiometric operation. Except for a
stable reference, no critical components are
required to achieve rated performance. The
technique used offers superior linearity, normal
mode rejection, and stability due to the
simultaneous integration of the unknown input and
the reference voltages. Unlike other conversion
techniques, the integrator output voltage never
represents more than 100 counts. Thus, critical,
high resolution performance is not required of
either the integrator or the comparator.
The monolithic LD111 A high performance analog
processor contains a bipolar comparator, a bipolar
integrating amplifier, a bipolar reference amplifier,
two MOSFET Input unity gain amplifiers, several
P-channel enhancement mode analog switches and
the necessary level shifting drivers to allow the
analog and digital processors to be directly
interfaced. The high impedance input and
reference buffer amplifiers eliminate source loading
errors and provide the outstanding temperature
coefficient inherent in this system. Break-beforemake switch action ensures that neither the analog
input nor the reference voltages will be shorted to
ground at any time.
function of the analog processor. Seventeen static
latches store the 3 1/2 digits of BCD data as well as
overrange, underrange and polarity information.
Nine push-pull output buffers (capable of driving
one standard TTL load each) provide the sign, digit
strobe and multiplexed BCD data outputs, all of
which are active high. The digit scan is an
interlaced format of digits 1, 3, 2, and 4.
Both devices are supplied in the 16-pin plastic DIP,
and are specified for operation over the
commercial, C suffix (0 to 70DC) temperature
range.
PIN CONFIGURATION
Dual-In-Llne Package
Top View
0 1
B1
O2
B2
0 3 3
04
B3
B4
SIGN
GND
11
M/Z
Order Number: LDll0CJ
Dual-In-Llne Package
Top View
BUFF OUT
1
V1
VIN
AZIN
u/D
AZ FILTER
COMP
The PMOS LD110 synchronous digital processor
combines the counting, storage and data
multiplexing functions with the random logic necessary to control the quantized charge-balancing
6-4
v2
AZ OUT
v2
INT OUT
ANALOG GND
VREFIN
9
INTIN
Order Number: LDlllACJ
Not Recommended for New Designs
trY'
~
LD110/111A
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
BCD OUTPUTS
6, B2 B3 B~
DIGIT STROBES
I
I
I
I
I
I
I
I
I
IL _____________ _
LOlllA
V2
GND
ANALOG
GND
CLOCK IN
SWITCH STATES ARE FOR A LOGIC "0" AT U/D AND M/Z INPUTS
ABSOLUTE MAXIMUM RATINGS
liN (Pin 15, 2) ............................... ±1 mA
V REF •..................•..................••..•. V,
V,-V2 (LOll1A) ............................... 30V
Operating Temperature ..................•.. 0 to 70°C
VSS
.......................................... 6 V
Vss -V2 (LD110) ............................... 20 V
V On Any Pin Relative toVss (LOll0) .... 0.3 V to -20 V
Storage Temperature ............•....... -65 to 125·C
Power Dissipation (Package)" •..........••.... 750 mW
• Device mounted with all leads welded or soldered to PC
Board. Derate 6.3 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V, = 12 V, V2= -12 V
Vss = 5 V
VREF= 8.2 V
R, = 100 k.n.
LIMITS:
TYP d
TA=25°C
MIN b MAX b
UNIT
SYSTEM
Analog Input Range
-2
VANALOG
Linearity
Noise
Noise apparent when going from
one steady reading to another.
Not Recommended for New Designs
2
V
0.02
% rdg
0.1
LSB p_p
6-5
WY'Siliconix
incorporated
LD110/111A
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
Vl = 12 V, V2= -12 V
Vss = 5 V
VREF= 8.2 V
Rl = 100 k.o.
LIMITS:
TVP d
T A =25°C
MIN b MAXb
UNIT
SVSTEM (Cont'd)
Gain T.C.
5
ppm/DC
dB
NMR
fNOISE = 60 Hz
40
Clock Frequency
fin
50 % Duty Cycle
30.7
ON Resistance
Auto Zero SWitch
rOS(ON)
V AZ(IN) = -4.0 V
Is = -30JlA
6
Clock Input Current LOW
ICL
VCLOCK(IN) = 0.4 V
Input Bias Current
liN
COMP, LDll0
IINL
Normal Mode Rejection
2
250
kHz
20
k.o.
INPUT
-500
JlA
4
VIN = -12 V
-700
pA
-1500
-50
JlA
AMPLIFIER
Reference Buffer
AZ Buffer
I SOURCE
VINL(UlO) = 0.8 V
-800
I SINK
VAz=-4V
800
I SINK'
VIN=-2V
800
VIN=2V
-100
-400
JlA
VOUT= 0 V
400
Input Buffer
I SOURCE
AZ Buffer
-50
-100
VOS
100
mV
"
OUTPUT
Measure/Zero
Voltage, Low
VOLl
IOL=150JlA
Measure/Zero
Voltage, High
VOHl
IOH = -200 JlA
Up/Down Logic
Voltage, Low
VOL2
IOL = 250 JlA
Up/Down LO~IC
Voltage, Hlg
V OH2
I OH = -200 JlA
2.4
Analog Comparator Voltage
VOH3
IOH= -100 JlA
2.4
6-6
0.6
2.4
0.6
V
Not Recommended for New Designs
LD110/111A
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V1 = 12 V, V2 = -12 V
Vss = 5 V
VREF= 8.2 V
R1 = 100 kfi
LIMITS:
TYP d
T A =25°C
MIN b MAX b
UNIT
OUTPUT (Cant'd)
Digits, Bits Voltage, Low
0.6
V01.3
IOL=1.6mA
Sign Voltage, Low
0.65
VOL4
V
Data Bits Voltage, High
VOH4
I OH = -200 .uA
2.4
Digits, Sign Voltage, High
VOHS
I OH = -800 .uA
2.4
SUPPLY
V 1 Supply Current LDlllA
11
2.2
V2 Supply Current LDlllA
12A
-1.8
-4
V2 Supply Current LD110
120
-17
-23
Vss Supply Current LDll0
Iss
17.4
Power Supply Rejection Ratio, V 1
PSRR 1
85
80
Power Supply Rejection Ratio. V2
PSRR 2
65
60
4
mA
24
dB
Reference Voltage Rejection
RREF= R2 = 100 k!l.
VIN =2V
1
%4rdg
per
4VREF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebralo convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Not Recommended for New Designs
6-7
...... Siliconix
incorporated
LD110/111A
~
FUNCTIONAL OPERATION
BCO OUTPUTS
.
OIGIT STROBES
81 B2B3B~
I
I
I
I
I
I
I
I
I
IL _____________ _
1.0111 A
7
ANALOG
GNO
GNO
CLOCK IN
SWITCH STATES ARE FOR A LOGIC '0· AT U/O ANO M/Z INPUTS
011111110111111101 ••• ,110 ••• 11
tiD
01111111011,.11.0.1111 •• 0.1.,11.0
III1IUUUUlJ1IUl
Il/IJIIIIIJIIlI
M/Z
M/Z
.1.
OVRO
--+- AUTO ZERO
~::~A~z::~.I~'-----------MEASUR.~E----------.
AZ
AZ
UJO
U/O
J-A..J- B-1- B-+-A-oj.-B--I-B
COMPARATOR
OUTPUT
COMPARATOR
OUTPUT
/'\V / \VV
A"VV
/\1
/VAZ
INTEGRATOR
OUTPUT
6-8
INTEGRATOR
OUTPUT
yv
\/?'
V
Not Recommended for New Designs
LD110/111A
W7' Siliconix
~
incorporated
FUNCTIONAL OPERATION (Cont'd)
a
16
8
24
32
48
40
56
64
CLOCK
BIll
I
I
1
111
1 11
111
1
2
212
2
2
2
4
4
4
414
4
4
8
8
8
81 8
8
8
B2
J
2
2
B3
4
4
B4
8
8
01
J
I
I
2
02
03
041
Rll
loon
R12
F
+1
-I.
MAN4630
rK
~
g ~g +-~g
r---r----
fl:lL~
r----
10
""
• rtf-!..!-
r----
•
~
MAN4610
~
MAN4610
~
C:!.
~
--1g.
c
-Ts- ~
:::a
~
3
9374 A2
..1Rg
4.3 k.O.
Al .L
7
AO
gf
RIO
sIn
L-
V
07
MPSA13
03
-<04
-<05
~SAI3
-::-
.---- 1
I-f!
565
!
5
~
:
C4::!:
O.OO22JLFT
-<06
MPSA13
1 LOll0 16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
02
+BV
•
MAN4610
3 8
A .l!....-
-::-
--
R5
-
L
R8
12 k.O.
f--
C5
O.OIJLF
I--I--
~
-12 V
1
2
3
4
5
6
7
-
C3 ' V
o. 022 JLF
LOlllA
1 6 1 - - ,R4
15 I160 kn
14
13 I - 12
11
10 f-C2 Cl
;~
~ ~:1 R~~1
k
L€;75 k:n. 10
N/C
--r.I.
R2
10 k.O.
lMn~
NATIONAL
2N4274
0.1 0.0082
JJ.F JLF
n
01
-::-
c:>
+12V
Not Recommended for New Designs
6-9
LD120/121A
4 1/2-Digit AID Converter Set
. . . Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• 0.005% ±1 Count Accuracy
• High System Performance
• ± 200.0 mV and ±2.000 V
Ranges
• Single Resistor
Programming
• High Accuracy Digital
Voltmeters and
Panel Meters
• Auto-zero
• Nulls Out Offsets
• Auto-polarity
• Single Reference
• Over and Under Range
Outputs
• Easily Interfaced
• Digital Scales
and Thermometers
• J.l.P Data Acquisition
Systems
• Scientific Instrumentation
DESCRIPTION
The LD120 and LD121 A form a precision 4 1/2 digit
A/D converter system for use in display and
microprocessor based data acquisition applications. Based on Siliconix's "Quantized Feedback"
technique, intrinsic features include auto-polarity,
auto-zero, and ratlometrlc operation. Except for a
stable reference, no critical components are
required to achieve rated performance. The
technique used offers superior linearity, normal
mode rejection, and stability due to the
simultaneous integration of the unknown input and
the reference voltages. Unlike other conversion
techniques, the integrator output voltage never
represents more than 100 counts. Thus, critical,
high resolution performance is not required of
either the integrator or the comparator.
The LD120 analog processor is fabricated with a
unique PMOS/Bipolar process. It contains all the
necessary amplifiers, MOSFET switches, and switch
driver circuits for the system. The reference
voltage input is fully buffered in the LD120 to
eliminate the reference switch resistance as a
source of error. All the amplifiers are internally
compensated. The LD120 directly interfaces to the
LD121 A digital processor with no additional active
components required.
The LD121 A synchronous processor contains all the
digital circuitry for the quantized feedback system.
Device outputs supply two overrange signals,
underrange, sign and 4-1/2 digits of multiplexed
BCD data. (All outputs are TIL compatible.)
Overrange is also indicated by blinking digit strobes
above 20,000 counts. An input is provided to inhibit
this feature at user option. Microprocessor
controlled operation is simplified by a start
conversion input that allows conversion-oncommand.
Both devices are supplied in space saving 300 mil
dual-in-line plastic packages for operation in the
commercial, C suffix (0 to 70°C) temperature
range.
PIN CONFIGURATION
Dual-In-Llne Package
BUFF OUT
1
HI-Q GNO
M/Z
Dual-I,n-Llne Package
Top View
Top View,
V+
03
VIN
04
AZIN
05
AZ ALTER
VOO
COMP
AZOUT
vss
v-
INT OUT
ANALOGGNO
VREFIN
B3
INTIN
B2
U/O
RE'bUT
4
SIGN/OR/UR
B1
Order Number: LD120CJ
6-10
Order Number: LD121ACJ
Not Recommended for New Designs
...r Siliconix
incorporated
LD120/121A
~
FUNCTIONAL BLOCK DIAGRAM
~~/~TART
OR CONVERT
BCD OUTPUTS
B1 B2 B;
.
DIGIT STROBES
Bo
I
I
I
I
I
I
I
I
I
IL _________ _
V-
V+
CLK
ANALOG AZ FILTER
GND
LD120 Analog Processor
VSS
VDD
GND
LD 121 A Synchronous Digital Processor
SWITCH STATES ARE FOR A LOGIO "0" AT U/D AND M/Z INPUTS.
ABSOLUTE MAXIMUM RATINGS
VIN
(Pin 15,2 LD120l .................. V- f UNIT
INPUTS
1
4
Input Voltage HIGH
V1NH
Input Voltage lOW
V 1NL
Input Current/
Input Voltage HIGH
IINH
V1N =5V
(Slgn/OR/UR I )
1
170
IINL
VIN=OV
(Start Convert, Clock)
1
-150
cornfLarator Infrut
Sign UR/OR/BI nk I
Start, ClK IN
V
0.5
1
300
P,A
Input Current/
Input Voltage lOW
-400
OUTPUTS
Output Voltage HIGH
VOH
Output Voltage LOW
VOL
Output Voltage HIGH
VOH
Bit lines
sIHn/OR/UR
Dig tal Strobes
IOH= -40 P,A
1
IOL=1.&rnA
1
IOH= -150P,A
1
IOL= 0.8 rnA
1
2.4
0.&
4
M/Z
Output Voltage LOW
VOL
Output Voltage HIGH
VOH
V
0.&
IOH=-0.5P,A
4
U/D
Output Voltage LOW
0.&
IOL= 0.8 rnA
VOL
DYNAMIC
Start Convert J
Clock Frequency
tp
fCLOCK
Rep. Rate (Strobes)
50% Duty Cycle
fCLOCK
+
640
1
20
1
50
250
kHz
1
78
470
Hz
4.5
5.5
p,s
SUPPLY
Positive Supply Voltage
Vss
1
5
Range Over Which
Functionality Is Guaranteed
V
Negative Supply Voltage
Voo
1
-12
Positive Supply Current k
Iss
1
14
Negative Supply Current
100
1
-14
-13.2 -10.8
25
rnA
6-14
-25
Not Recommended for New Designs
~
~
Siliconix
incorporated
LD120/121A
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. System parameters not directly tested.
f. Bit width over which reading Is stable 95% of the time.
g. VSTRG must be more positive than -4 V.
h. Reference source Impedance must be less than 10 k.O. .
I. Pin characteristic only during D4 strobe time.
J. Minimum positive going pulse width to Initiate conversion.
k. All outputs disconnected.
Not Recommended for New Designs
6-15
LD1221121A
4 1/2-Digit AID Converter Set
trr' Siliconix
~
FEATURES
BENEFITS
APPLICATIONS
• 0.005% ±1 Count Accuracy
• High System Performance
• Two Ranges
• Single Resistor
Programming
• High Accuracy Digital
Voltmeters and
Panel Meters
• Auto-zero
• Auto-polarity
• Nulls Out Offsets
• Over and Under Range
Outputs
• Single Reference
• Easily Interfaced
incorporated
• Digital Scales
and Thermometers
• liP Data Acquisition
Systems
• Scientific Instrumentation
DESCRIPTION
The LD122 and LD121 A form a precision 4 1f2 digit
AfD converter system for use in display and
microprocessor based data acquisition applications. Based on Siliconix's "Quantized Feedback"
technique, intrinsic features include auto-polarity,
auto-zero, and ratiometric operation.
The LD122fLD121A combination is used to extend
system resolution beyond the 10 IiV maximum
available from the LD120fLD121 A system. By
adding a user selected low noise input amplifier and
appropriate filter, any input resolution can be
achieved. Except for this added buffer and a stable
reference, no critical components are required to
achieve rated performance. The technique used
offers superior linearity, normal mode rejection,
and stability due to the simultaneous integration of
the unknown input and the reference voltages.
Unlike other conversion techniques, the integrator
output voltage never represents more than 100
counts. Thus, critical, high resolution performance
is not required of either the integrator or the
comparator.
The LD122 analog processor is fabricated with a
unique combined PMOSfBipolar process. It contains
all the necessary amplifiers, MOSFET switches, and
switch driver circuits for the system. The reference
voltage input is fully buffered on the LD122 to
eliminate the reference switch resistance as a
source of error. All the amplifiers are internally
compensated. The LD122 directly interfaces the
LD121 A digital processor with no additional active
components required.
The LD121 A synchronous processor contains all the
digital circuitry for the quantized feedback system.
Device outputs supply two overrange signals,
underrange, sign and 4-1 f2 digits of multiplexed
BCD data. (All outputs are TTL compatible.)
Overrange is also indicated by blinking digit strobes
above 20,000 counts. An input is provided to inhibit
this feature at user's option. Microprocessor
controlled operation is simplified by a start
conversion input that allows converison-oncommand.
Both devices are supplied in space saving 300 mil
dual-in-line
plastic
packages
and
in
the
commercial, C suffix (0 to 70 c C) temperature
range.
PIN CONFIGURATION
Top View
Top View
BUFF IN
1
HI-Q GNO
v+
O2
03
VIN
01
04
05
AZIN
U/O
AZ FilTER
COMP
AZOUT
v-
INT OUT
ANALOG GNO
VREFIN
REFOUT
B
--"'_--1-
INTIN
Order Number: LD122CJ
6-16
COMP 3
M/Z
GNO
VOO
U/O
VSS
SIGN/OR/UR
START
ClK
B1
Order Number: LD121ACJ
Not Recommended for New Designs
~
~
LD1221121A
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
BCD OUTPUTS
.
DIGIT STROBES
BUFF IN
HIGH
QUALITY
GND
I
I
I
I
I
I
I
I
I
I
L ________ _
v-
v+
ClK
ANALOG AZ FilTER
GND
VSS
VDO
GNO
LD121A Synchronous Digital Processor
LD122 Analog Processor
SWITCH STATES ARE FOR A lOGIC "0" AT UfO AND MfZ INPUTS.
..
ABSOLUTE MAXIMUM RATINGS
.................. V- f UNIT
SYSTEM~
2 V Scale
1
±X
-1
1
200 mV Scale
1
±~
-2
2
2 V Scale
1
~
1
200 mV Scale
1
~
2
1
40
1
00
1
5
15
ppm/oC
1
1
5
Count
Linearity
Count
Noise!
fCLOCK = 163.04 kHz
VREF = 6.0 V
Normal Mode
Rejection Ratio
NMRR
Power SUPFl:IY
Rejection atlo
PSRR
fL= 50 Hz
or 60 Hz
Gain T.C.
C STRG =lJ1.F
RIN!S 100 k.G.
Zero Drift
dB
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LD122 (LINEAR CIRCUIT)
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = Voo= -12 V
Vss= 5 V
LIMITS
C
SUFFIX
1=25°C
TEMP TYpd MINb MA>f UNIT
INPUT BUFFER
Analog Input Voltage
VANALOG
ON Resistance
VIN or HI-Q Switches
rOS(ON)
Leakage Current
Switch ON or OFF
Input Currentl
Input Voltage HIGH
I LEAKAGE
1
-3
VA= 1 V
1
5.5
VA= -1 V
1
0
VIN= ±2.0 V
1
VIN = 2.0 V
IIH
6-18
IlL
V
k.G.
2
pA
20
1
M/Z, U/D Inputs
Input Currentl
Input Voltage LOW
3
Jl.A
VIN = 0.0 V
1
-100
Not Recommended for New Designs
H
LD1221121A
Siliconix
incorporated
LD122 (LINEAR CIRCUIT) (Cont'd)
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = Voo= -12 V
Vss= 5 V
LIMITS
C
SUFFIX
1=25°C
TEMP TYpd
MINb MAX' UNIT
AZ BUFFER
I SOURCE
1
-100
Output Sink Current
ISINK
1
800
Offset Voltage
Vas
VOUT= 0 V
1
On Reslstanceg
rOSION)
V STRa = -4 V
los = 30.uA
1
Reference Buffer
Source Current
I SOURCE
VIN (U/O IN) = 0.8 V
Va = 0 V
Reference Buffer
Sink Current
I SINK
Output Source Current
.uA
-50
50
mV
6
20
kn
1
-800
-400
VIN (U/O IN) = 0.2 V
Va = 2 V
1
100
I SOURCE
VIN (INT. IN) = -100 mV
Va = 0 V
1
-100
I SINK
VIN (INT. IN) = 100 mV
Va = 0 V
1
800
REFERENCE BUFFER
.uA
INTEGRATOR
Integrator Source Current
h
-50
.uA
Integrator Sink Current
h
Output Swing
400
1
-10
1
-5
-5
5
10
V
COMPARATOR
Comparator Output Swing
V OUT
Comparator Offset Voltage
Vas
1
Positive Supply Voltage
V+
1
12
9
15
Negative Supply Voltage
V-
1
-12
-15
-9
Positive Supply Current
1+
1
Negative Supply Current
1-
1
RL = 10 k to 5 V
AZ Filter IN = 100 mV
Integrator OUT = 0 V
V
mV
SUPPLY
V
Ground Current
laN~
M/Z, UfO = 2.4 V
Not Recommended for New Designs
3.5
-3
mA
-2
6-19
trY' Siliconix '
~
LD121 (DIGITAL CIRCUIT)
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
incorporated
Test Conditions
Unless Otherwise Specified:
V+ = 12 V
V- = Voo= -12 V
Vss= S V
LIMITS
C
SUFFIX
1=2S·C
TEMP TYpd MINb MA>f UNIT
INPUTS
1
4
Input Voltage HIGH
VINH
Input Voltage LOW
VINL
Input Currentl
Input Voltage HIGH
IINH
VIN=SV
(Slgn/OR/UR I )
1
170
Input Currentl
Input Voltage LOW
IINL
VIN = 0 V
(Start Convert, Clock)
1
-lS0
cornxarator Inrrut
Sign UR/OR/BI nk I
Start, ClK IN
V
O.S
1
300
,I.lA
-400
OUTPUTS
Output Voltage HIGH
V OH
Output Voltage LOW
VOL
Output Voltage HIGH
V OH
Bit Lines
Slgn/OR/UR
Digital Strobes
IOH= -40,l.lA
1
IOL= 1.6 rnA
1
IOH= -lS0,l.lA
1
IOL= 0.8 rnA
1
2.4
0.6
4
V
M/Z
Output Voltage LOW
VOL
Output Voltage HIGH
V OH
0.6
4
IOH= -O.S,I.lA
U/D
Output Voltage LOW
0.6
IOL= 0.8 rnA
VOL
DYNAMIC
Start Convert J
Clock Frequency
tp
fCLOCK
Rep. Rate (Strobes)
SO% Duty Cycle
fCLOCK
+
640
,I.ls
1
20
1
50
250
kHz
1
78
470
Hz
4.S
5.5
SUPPL.Y
Positive Supply Voltage
Vss
1
S
Range Over Which
Functionality Is Guaranteed
V
Negative Supply Voltage
Voo
1
-12
Positive Supply Current k
Iss
1
14
Negative Supply Current
100
1
-14
-13.2 -10.8
25
rnA
6-20
-25
Not Recommended for New Designs
fI"lI' Siliconix
incorporated
~
LD1221121A
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. System parameters not directly tested.
f. Bit width over which reading Is stable 95% of the time.
g. VSTAG must be more positive than -4 V.
h. Reference source Impedance must be less than 10 k.n..
I. Pin characteristic only during 04 strobe time.
J. Minimum positive going pulse width to Initiate conversion.
k. All outputs disconnected.
Not Recommended for New Designs
6-21
Si2504"
. " , Siliconix
Incorporated
~
High Speed
12·Bit SAR
FEATURES
BENEFITS
APPLICATIONS
• High Speed (40 MHz typ.)
• Reduced Conversion Time
• High-Speed AID Converters
• Low Quiescent Power
(Icc < 10j.l.A)
• Reduced Power Consumption
• Low-Power Data Acquisition
Systems
• Three-State Outputs
c Expandable Via Cascading
• Can Be Short-Cycled
• Allows In-Circuit
Trims
c Facilitates Higher
Resolution AID Converters
• Optimizes Conversion Time
• Laser-Trimmed AID
Converters
• High Resolution AID
Converters
• Variable-Resolution
Systems
DESCRIPTION
The 5i2504 is a high-speed, low power CMOS 12-Bit
SAR (successive approximation register) that
contains all of the necessary digital control and
storage to build a 12-Bit successive-approximation
AID converter when combined with a 12-Bit 01 A
converter and a comparator. The register can be
cascaded for applications requiring more than
12 bits of resolution, and may be short-cycled to
reduce the conversion time In lower-resolution
applications. Applications include custom and lor
hybrid AID converters with resolutions from 8 to
12 bits, and up to 24 bits when cascading two
devices. The 12 data outputs have 3-state output
buffers, allowing the SAR to be placed in a
high-Impedance mode, allowing the DIA converter
in an AID system to be trimmed without contending
with the output of the SAR.
The 5i2504 Is built in a 2 micron silicon-gate CMOS
process, alowing high speed operation at reduced
power, with TTL-compatible data inputs and
outputs. It is available in a 0.600" wide 24-pln
plastic DIP for operation over the commercial, C
suffix (0 to 70°C) temperature range. The Si2504 is
also available in die form, inspected to
MIL-STD-883, method 2010, visual B.
6-22
PIN CONFIGURATION
Dual-In-Una Packaga
Ql0
Q9
Q8
Q7
Q6
NO
OE
GND
OF'
Order Numbers:
SI2504CJ
Plastic DIP
SI2504 Dice
Si2504
.... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
DO
a11
a10
a9-a1
o
e
O-~:>------+
a11
ao
ee
• Cell logIc Is repeated for stages Q9 to Q1.
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND
Vee •.•..••....................••....•. -0.3 V to 7 V
Storage Temperature ...•........••...... -65 to 125·C
OperatIng Temperature ••....••••.••..•.••.. 0 to 70·C
Voltage Applied to Outputs •...... -0.3 V to Vee + 0.3 V
Output Current ...................•........•.. 10 mA
Input Voltage .........•........• -0.3 V to Vee + 0.3 V
Input Current ....•.•..•....•.•.......••.. -30 to 5 mA
Power DIssIpatIon (Package)·
24-Pln PlastIc DIp·· .......•.........•...... 1000 mW
All leads welded or soldered to PC board.
Derate 11.0 mW'·C above 2S·C.
6-23
Si2504
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Speolfled:
Vee = 5 V ±10%
PARAMETER
LIMITS
1=25 ·C
2=70·C
3=0·C
TEMP
SYMBOL
C
SUFFIX
TYP c
MIN b MAXb
UNIT
STATIC
High Level Output Voltage
VOH
10H = -2 mA
1,2,3
Low Level Output Voltage
VOL
IOL=6mA
1,2,3
3
0.4
V
High Level Input Voltage
VINH
Vee = 5.5 V
1,2,3
Low Level Input Voltage
VINL
Vee= 4.5 V
1,2,3
Pull-Up Reslstanoe (OE only)
Rpup
1,2,3
2.4
0.6
500
100
900
Input Leakage Current
(exoept OE)
liN
V IH = Vee, V IL = GND
Vee= 5.5 V
1,2,3
-1
1
Output OFF Statl!J,eakage
Current (exeept CCI
loz
OE = 0 V, V OUT = Vee or GND
Vee= 5.5 V
1,2,3
-1
1
Statio Supply Current
10
10H = 10L= 0 A
1,2,3
Output Short Clroult d
Current
Ise
Vee= 5.5 V, V OUT = 0 V
1,2,3
Supply Current
lee
V IN =OVor5V
feLoeK = 16.67 MHz
1,2,3
kfi
JJ.A
10
-30
mA
17
DYNAMIC
Turn OFF Delay
CP to Output LOW
Turn OFF Delay
CP to Output HIGH
tpD +
Data Setup Time
tS(D)
Start Input Setup Time
tS(S)
E to 011
Turn OFF Delay
HIGH
tpD+(E)
Turn ON Delay
LOW
tpD- (E)
E to 011
Bus Release Time
OE to Outputs High
Impedance
Bus Aooess Time
OE to Outputs V IH or V IL
6-24
Outputs 011, 011
1
22
44
Outputs Exoept
011, 011
1
15
44
1
15
44
1
4
-10
10
1
16
0
25
1
10
44
1
30
44
1
40
44
1
22
44
tpD -
C L = 15 pF
CP = HIGH
S= LOW
tOER
R L =3k!l.
tOEA
ns
Si2504
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Vee= 5 V ±10%
LIMITS
1=25 ·C
2=70·C
3=0·C
C
SUFFIX
MIN b MAXb
SYMBOL
TEMP
TYP c
Minimum Low Clock Pulse
tpWL(ep)
1
23
30
Minimum High Clock Pulse
tpWH(ep)
1
10
30
1
40
PARAMETER
DYNAMIC
UNIT
(Cont~d)
ns
Maximum Clock Frequency
f MAX
16.67
MHz
DIE SORT LIMITS
LIMITS
Test Conditions
Unless Otherwise Specified:
Vee= 5 V ±10%
PARAMETER
SYMBOL
C
SUFFIX
1=25 ·C
TEMP
TYP c
MIN b MAXb
UNIT
STATIC
High Level Output Voltage
V OH
IOH = -2 mA
1
Low Level Output VOltlige
VOL
IOL=6mA
1
High Level Input Voltage
V INH
Vee= 5.5 V
1
Low Level Input Voltage
VINL
Vee= 4.5 V
1
Pull-Up Resistance (OE only)
Rpup
3
0.4
V
1
2.4
0.6
500
100
900
Input Leakage Current
(except OE)
liN
VIH = Vee, VIL = GND
Vee= 5.5 V
1
-1.0
1.0
Output OFF State.J,eakage
Current (except CC)
loz
OE = 0 V, VOUT = Vee or GND
Vee= 5.5 V
1
-1.0
1.0
Static Supply Current
10
IOH=loL=OV
1
Output Short Circuit d
Current
Ise
Vee= Max, V OUT = 0 V
1
k.O.
jJ.A
10.0
-30
mA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. ih~; 3~~:b!~~Cefonventlon whereby the most negative value Is a minimum and the most positive a maximum, Is used In
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. No more than one output should be short circuited at one time. Duration of short circuit should be less than 1 s.
6-25
Si2504
DIE
..... Siliconix
incorporated
~
TOPOGRA~HY
140 mils
18171615
21 2019
~' 141
000 • • • 0000 • • • •
o
23 •
24 , •
0'
o
'0
o
Si2504
o
•
117 mils
0,
0:,
:0
o
2: •
•
13
0,
•
'12
0'
a
gao . 0 • • • 0000 • • • 0 .
3
7 8 9
456
11
TRUTH TABLE
TIME
H
6-26
INPUTS
OUTPUTS
Q8
~
Q6
Q5
Q4
Q3
Q2
Q1
~
CC
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
010 011 010 L
H
H
H
H
H
H
H
H
H
H
L
H
09
011 010 09
L
H
H
H
H
H
H
H
H
H
L
H
08
011 010 09
08
L
H
H
H
H
H
H
H
H
H
L
H
07
011 010 09
08
07
L
H
H
H
H
H
H
H
H
L
H
06
011 010 09
08
07
06
L
H
H
H
H
H
H
H
L
H
05
011 010 09
08
07
06
05
L
H
H
H
H
H
03
H
L
H
04
011 010 09
08
07
06
05
04
L
H
H
H
H
10
02
H
L
H
03
011 010 09
08
07
06
05
04
03
L
H
H
H
11
01
H
L
H
02
011 010 09
08
07
06
05
04
03
02
L
H
H
12
00
H
L
H
01
011 010 09
08
07
06
05
04
03
02
01
L
H
13
X
H
L
H
00
011 010 09
08
07
06
05
04
03
02
01
00
L
14
X
X
L
H
X
011 010 09
08
07
06
05
04
03
02
01
00
L
X
X
X
X
H
H
L
X
Z
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NC
NC
tn
0
0
1
DO Q11 Q10 ~
S
E
OE
X
L
L
H
X
X
X
011
H
L
H
X
L
H
2
010
H
L
H
011 011 L
3
09
H
L
4
08
H
5
07
H
6
06
7
05
8
04
9
X
=HIGH Voltage Level, L =LOW Voltage Level, X = Oon't Care,
NC
=No Change, Z =HIGH Impedance
Si2504
. . . Siliconix
incorporated
~
SWITCHING TIME WAVEFORMS
AT LEAST
CP
------.., ~tPWl(cPr- ~~~~;6~;'"
-
tS(S)MAX- ~
~
1.5V
~ tS(S)MIN
'/ '//
'////
:x
1.5V
tS(O)MAX
tS(S)MIN_ ~
-I
o
4-
tS(O)MAX
tS(O)MIN
4-
r
tpo- MAX
tS(O)MI N
1.5V
tpO+MAX
1.5 V
al 1
1
tpO+MAX
al a
I
lpO- MAX
//A/
///./1
:I
~
tPO+MAX-H
DO
tpo-MAX
~
~I
~
1.5V
I.SV
E::::::::::::::j~~::::::::::::::::::::::~~~::::::::::::::::::::1'5V
ENABLE TO all
t
all
t
~
Jool----t-
+ (ih MAX
tpo -
eE) MAX
======~~~~~S;;27~0~*~=po======::::::ss~~~~~~;:::====::
=
CP=HWHEN
ENABLE CHANGES
1.5 v
APPLIES ONLY WHEN
START-SIGNAL
APPLIED DURING
PREVIOUS CLOCK
PERIOD
SWITCHING TIME WAVEFORMS (OUTPUT ENABLE)
OUTPUT:::::::::::::~~k::::::::::::::::::::::::7¥V~::::::::::::::::::::::::=
ENABLE
1\_~~~~~~~~~___/1
1.5 v
axx HIGH
--------+---.1
Lr----------
90%
~~______________4_--~7!-----------------2.4V
~~I:~:~~R---------t~-t-0-EA-:-:~J\:::::::::::::::::::::0.4V
-0
axxLOW
Vee
TEST CONDITIONS:
VOH to HIGH - Z or
HIGH - Z to \bH
axxo--4----~
3k
n
J
3 kn
15 pF
VOL to HIGH - Z or
HIGH - Z to \bL
axxo-------{
I
15PF
6-27
Si2504
.... Siliconix
incorporated
~
DEFINITIONS
tpD WAVEFORM
INPUTS
OUTPUTS
tpD +
MUST BE
STEADY
WILL BE
STEADY
tpD - (E)
tpD+ (E)
•
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
KEY TO TIMING DIAGRAM
tS(D)
ts{S)
The propagation delay from the clock signal
LOW --> HIGH transition to an output signal
HIGH --> LOW transition.
The propagation delay from the clock
signal LOW --> HIGH transition to an
output signal LOW --> HIGH transition.
The propagation delay from the Enable signal
HIGH --> LOW transition to the 011 output
signal HIGH --> LOW transition.
The propagation delay from the Enable signal
LOW --> HIGH transition to the 011 output
signal LOW --> HIGH transition.
The set-up time required for the logic level to
be present at the data Input prior to the clock
transition from LOW to HIGH In order for the
register to respond. The data Input should
remain steady between ts max and ts min
before the clock.
The set-up time required for a LOW level to be
present at the"S" Input prior to the clock transition
from LOW to HIGH In order for the register to be
reset, or the time required for a HIGH level to be
present on "S" before the HIGH to LOW clock
transition to prevent resetting.
tpw(CP)
The minimum clock pulse width (LOW or
HIGH) required for proper register operation •
tOER
The delay from OE to a 10% change In
the outputs when loaded with 3 k.n and
15 pF.
tOEA
The delay from OE to an output crossing 2.4 V
or 0.4 V when loaded with 3 k.n and 15 pF.
OPERATION
The registers consist of a set of master latches that
act as the control elements in the device and
change state when the input clock changes from
HIGH-to-LOW, and a set of slave latches, that hold
the register data and change on the input clock
LOW-to-HIGH transition. Externally the device acts
as a special purpose serial-to-parallel converter. It
accepts data at the 0 input of the register and
sends the data to the appropriate slave latch. This
data appears at the register output and the DO
output on the Si2504 when the clock goes from
LOW-to-HIGH. There are no restrictions on the data
input; it can change state at any time except during
the set-up time just prior to the clock transition. At
the same time that data enters the register bit the
next less significant bit is set to a LOW, ready for
the next iteration and so on for each successive bit
conversion cycle.
6-28
The register is reset by holding the S (Start) signal
LOW during a full clock LOW-to-HIGH transition. The
register synchronously resets the state 011 LOW,
and all the remaining register outputs HIGH. The CC
(Conversion Complete) signal is also set HIGH at
this time. After the clock has gone HIGH resetting
the register, the S signal must be removed. On the
next clock LOW-to-HIGH transition the data on the 0
input is set into the Q11 register bit. The Q10
register bit is set to a LOW ready for the next clock
cycle. On the next clock LOW-to-HIGH transition
data enters the Q10 register bit and Q9 is set to a
LOW. This operation is repeated for each register
bit in turn until the register has been filled. When
the data goes into QO, the CC signal goes LOW,
and the register is inhibited from further change
until reset by a Start signal.
..or
~
Si2504
Siliconix
incorporated
OPERATION (Cont'd)
In order to allow one's or two's complement
conversion, the complementary output of the most
significant register bit is made available.
An active LOW enable input (E) allows devices to
be cascaded together to form a longer ~gister.
This is done by paralleling the clock, D and S inputs
and connecting the CC output to the E input of the
next less significant device. When the Start signal
resets the registers, the CC and E signals go HIGH,
starting conversion in the MS Device and inhibiting
the next less significant device from accepting data
until the previous device is full an'!, its CC goes
LOW. If only one device is used the E input should
be held at a LOW logic level. If all the bits are not
required, the register may be truncated and
conversion time saved by ~ing a register output
going LOW rather than the CC signal to indicate the
end of conversion.
The Q and DO outputs may be forced into a high
impedance state by bringing OE LOW. This allows
busing on common microprocessor buses or laser
trimming of hybrid circuits without damaging the
Si25D4.
APPLICATION HINTS
1. The register can be used with current switches
that require either a LOW voltage level or a HIGH
voltage level to turn the switch on. If current
switches are used which turn on with a LOW
logic level, the resulting digital output from the
register is active LOW. That is, a logic "1" is
represented as a low voltage level. If current
switches are used that turn on with a HIGH logic
level then the digital output is active HIGH; a
logic "1 " is represented as a HIGH voltage level.
2. For a maximum digital error of ±1/2 LSB the
comparator must be biased. If current switches
that require a LOW logic level to turn ON are
used, the comparator should be biased +1/2
LSB and if the current switches require a HIGH
logic level to turn ON then the comparator must
be biased -1/2 LSB.
3. The register, by suitable selection of resistor
ladder network, can be used to perform either
binary or BCD conversion. Additional data input
gating should be used to eliminate the possibility
of false BCD coding.
4. The register can be used to perform 2's
complement conversion by offsetting the
comparator 1/2 full range +1/2 LSB and using
Qll as the sign bit.
5. If the register is truncated and operated in the
continuous conversion mode a lock-up condition
may occur on power-on. This situation can be
overcome by making the Start input the OR
function of CC and the appropriate register
output.
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
E
2
DO
3
4-9
DESCRIPTION
Register ENABLE. This input is used to expand the length of the register
and when HIGH forces the Qll register output HIGH and inhibits
conversion. When not used for expansion the enable is held at a LOW
logic level (GND).
The serial DATA OUTPUT.
CONVERSION COMPLETE output. This output remains HIGH during
conversion and goes LOW when a conversion is complete.
QD-Q5
Register OUTPUTS. The six least significant bits of the register.
QD is the LSB.
6-29
..
Si2504
. . . Siliconix
incorporated
~
PIN DESCRIPTION (Cont'd)
PIN
NUMBER
SYMBOL
DESCRIPTION
10
NC
No connection.
11
D
12
GND
13
CP
CLOCK PULSE Input.
14
S
START input. Holding this input LOW for at least one clock period will
reset the register to 011 = LOW and 00 - 010 = HIGH. A LOW of one clock
period is not necessary if it meets the set-up time requirements of the
S Input.
15
OE
OUTPUT ENABLE input. A LOW on this input will disable the 011 - 00, 011
outputs putting them in a HIGH IMPEDANCE state. This input has an internal
pull-up and needs no connection for normal operation.
16-21
06-011
Serial DATA Input.
Ground.
Register OUTPUTS. The six most significant bits of the register.
011 is the MSB.
6-30
22
NC
No Connection.
23
on
Complementary output of the MSB register.
24
VCC
Positive power supply input.
Si7135
Precision 4 1/2-Digit
Single Chip CMOS AID Converter
..... Siliconix
Jl;;JI incorporated
•
•
APPLICATIONS
BENEFITS
FEATURES
Accuracy ±1 Count in
±20,OOO Counts
GI
Improves System Accuracy
•
•
Reduced Loading of High
Impedance Sources
High Resolution Data
Acquisition (15 bit)
•
No External Zero Adjust
Direct Measurement of
High Impedance Signals
1 pA Input Current
•
Auto Zero
•
•
Differential Input
(CMRR = 86 dB typ.)
•
Improved Common-Mode
Signal Rejection
•
Precision DMM and
DVM's
•
15 mW Power
Consumption
•
Battery Operation
•
Temperature Measuring
Instruments
•
Simplifies Display
Interfacing
•
Remote Data Measurement
•
Panel Meters
•
Multiplexed BCD Outputs
DESCRIPTION
The Si7135 is a precision 4 1/2 digit integrating AID
converter system for use in display and microprocessor based data acquisition applications. Based
on the reliable dual slope conversion technique,
intrinsic features include 2.0000 V full scale range,
differential inputs, auto-polarity, auto-zero, and
ratio metric operation to achieve a high level of
versatility for the systems designer. The multiplexed BCD outputs, when connected to display
drivers, make the Si7135 an ideal solution for visual
display DVMIDPM applications.
Manufactured on the Siliconix proprietary PolyMOS
process, the Si7135 exhibits improved linearity over
the industry-standard ICL7135, eliminating the
linearizing components required by the generic
devices. An epitaxial layer prevents latchup.
Package options include the 28-pin plastic DIP,
CerDIP, and PLCC packages. All are rated for
performance over the commercial, C suffix (0 to
70°C) temperature range.
For more information on the Si7135, please refer to
Silica nix Application Note AN83-14.
PIN CONFIGURATION
PLCC-28 Package
Dual-In-Line Package
A
U
N R
N 0
A E
2
UNDERRANGE
2
OVERRANGE
2
STROBE
INT OUT
2
R/H
AZ IN
2
DIGITAL GND
D V
L FEE
o ERR
G R
R R
E
A A
C N
o C
N N
G G
r:'1r~~\rE~2,r~",-~:~r2:¥.:Elr.2"" STROBE
•
BUFF OUT
R/H
REF. CAP.REF. CAP.+
DIGITAL GND
BUSY
IN LO
2
IN HI
POL
CLOCK IN
D, (LSD)
D2
,
BUSY
9
D2
D3
,
D4
(MSB) Ba
~~____________~
84
(LSD) D,
v+ "
,,,,,,,
MLBBMDD
S824843
Order Numbers:
CerDIP: SI7135CK
Plastic: SI7135CJ
D B
B
D
B
B
5'
a
Order Number:
SI7135CN
6-31
Si7135
.... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
BUFFER
AUTO
ZERO
.--I
INT
INTEGRATOR
I
REF HI o-~-------+,
IN HI o-~---o~~~~~~~~t-------4--Q9--------------r~~------------i
INPUT
LOW
c~~~g2 O--r------~~~--1-------~
L---------------r ------ 1-----------
INLO O-4-~INT~X}--~~--~~~~~~~------------------~
v-
DIGITAL
GND
CLOCK
IN
RUNI
m5l!l
OVER
RANGE
v+
UNDER
RANGE
STROBE
BUSY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
V+ ...........••..............•..•........... 6V
V- .......••••.•.........•••..•............. -9 V
Power Dissipation •
Ceramic Package ..........•............... 1000 mW
Plastic Package ............................. 800 mW
PLCC ...................................... 450 mW
Analog Input Voltage (either Input)d ........•.. V+ to V-
Operating Temperature ....•..•.•.........•• 0 to 70·C
Reference Input Voltage (either Input) ......•.. V+ to V-
Lead Temperature (Soldering. 10 s) .......•.•... 300·C
Storage Temperature ......••.•........•. -65 to 125·C
Clock Input ...•................•..•....... GND to V+
6-32
Dissipation rating assumes device Is mounted with all
leads soldered to printed circuit board.
Si7135
rY'Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 5 V, V- =-5
f clock= 120 kHz
Full Scale = 2.0000 V
LIMITS
1=25· C
2=70·C
3=0·C
TEMP
C
SUFFIX
TYpc
MINb
MAXb
UNIT
-2
2
V
ANALOG
Analog Input Range
1
VINPUT
Zero Input Reading
See Figure 1
VIN=OV
1
± 0.0000
-0.0000
0.0000
Ratlometrlc Reading
See Figure 1
VIN = VREF
1
0.9999
0.9998
1.0000
1
0.5
1
0.01
1
1
3
10
linearity Error e
INL
Differential Non-linearity f
DNL
See Figure 1
-2VSVIN S2V
Rollover Error 9
Input Leakage Current
Nolse h
I ILK
VIN=OV
1
1
eN
See Figure 1
VIN=OV
1
15
Digital
Reading
1.5
Counts
(LSB)
pA
JJ,V
DIGITAL INPUTS
Input HIGH Voltage
VINH
1
2.2
Input LOW Voltage
V INL
1
1.6
0.8
Input HIGH Current
IINH
V IN =5V
1
0.02
0.1
mA
Input LOW Current
IINL
VIN=OV
1
0.1
10
J.lA
IOL=1.6mA
1
0.25
0.4
Pins 12-20
IOH=-1 mA
1
4.2
2.4
Pins 21,23,26, 27, 28
IOH = -10J.lA
1
4.99
4.9
V+
1
5
4
V-
1
-5
2.8
V
See Figure 2
CLOCK IN,
RUN/HOLD
DIGITAL OUTPUTS
Output Voltage LOW
Output Voltage HIGH
VOL
V
V OH
SUPPLY
+5 V Supply Range
6
V
-5 V Supply Range
6-33
Si7135
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
SYMBOL
PARAMETER
V+ = 5 V, V- = -5
f clock= 120 kHz
Full Scale = 2.0000 V
LIMITS
1=25 ·C
2=70·C
3=0·C
C
SUFFIX
TEMP
TYpO
1
1.1
MINb
MAX'
UNIT
SUPPLY (Cont'd)
+ 5 V Supply Current
1+
3
mA
- 5 V Supply Current
1-
1
0.8
1
120
3
DYNAMIC
Clock Frequency I
dc
200
kHz
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor sublect to production testing.
d. Input voltages may exceed the supply voltages provided the Input current Is limited to 100J1A.
e. Error of reading from best straight line.
f. Difference between worst case step of adjacent counts and Ideal step.
g. Difference In reading for equal positive and negative readings near full scale.
h. Peak-to-peak value not exceeding 95% of the time.
I. The temperature range can be extended beyond 70·C as long as the auto-zero and reference capacitors are Increased
to absorb the higher leakage of the S17135.
J. This speCification relates to the clock frequency range over which the SI7135 will correctly perform Its various functions.
See tlie MAXIMUM CLOCK FREQUENCY section of the description for limitations on the clock frequency range In a system.
DIE TOPOGRAPHY
Pad
No.
:1
12
13
14
28
; ; ' -__
CSAA
50
43
15
10
6-34
N-Channel Transistors
P-Channel Transistors
Resistors
Capacitors
~~~ ~
___
_ _ _ _ _ _ _ _ _"":"..1
2DX
~I'"
Function
1
V-
2
3
4
5
6
7
8
Reference
Analog Common
INT Out
AZ In
Buff Out
Ref. Cap.Ref. Cap.+
In Lo
In HI
V + (substrate)
(MSD)Ds
(LSB) B1
B2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
El4
(MSB) B8
D4
D3
D2
(LSD) D1
Busy
Clock In
POL
DI@aIGND
R/H
Strobe
Overrange
Underrange
Si7135
..w" Siliconix
~
incorporated
TEST CIRCUITS
1
-5V
VREF= 1.000 V
OV
24
.?+_ _--!2'-j REFER~~c~IG~~~~ ~~ .......6_Jl"00",,k.n.~~
0.4711F
SIGNAL
INPUT
o.JVv\,--4>--.!:"-I IN HI
V+
DIGITALGND
CLOCK IN
L----ll~~2~2~~~-A
100 k.n.
+5 V
CLOCK IN
120 kHz
Figure 1. SI7135 Test Circuit
Figure 2. Logic Input Circuit
DETAILED DESCRIPTION
.---
CREF+
1
_______
c.£!~
8
12
REF HI o-~~---+~
•
IN HI
INPUT
LOW
ct~~~g~ o-~~--~~~-~----~
INLO o-~~~xr-~~~~~~~~----------------------~
L~~-------------t------l--------------V-
Figure 3.
V+
V+
Analog Section of the SI7135
V+
6.8 k.o.
SI7135
REF. HI
6.8 V
ZENER
SI7135
!
COMMON
Iz
REF. HI
1.2 V
REFERENCE
COMMON
VFigure 4.
Generating External References
6-35
Si7135
.... Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
V+
POLARITY
___ t __
11
23
B1
B2
B4
~~--~~~~~~~TT~~~~ ._,
ANALOG
SECTION
DIGITAL
GND
CLOCK
IN
mlliI
HOLD
OVER
RANGE
UNDER
RANGE
-
B8
BUSY
Figure 5. Digital Section
ANALOG SECTION
Figure 3 shows the block diagram of the analog
section for the Si7135, figure 5 shows the digital
section, and figure 6 shows the timing diagram.
Each measurement cycle is divided into four
phases. They are (1) AUTO-ZERO (AZ), (2) SIGNAL
INTEGRATE (SI) , (3) REFERENCE INTEGRATE (RI)
and (4) ZERO INTEGRATOR (ZI).
within a common mode range which is specified
from 0.5 V below the positive supply to 1.0 V
above the negative supply. If the input signal
has no return with respect to the converter
power supply, IN LO can be tied to analog
COMMON to establish the correct commonmode voltage. At the end of this phase, the
polarity of the integrated signal is latched into
the Polarity flip flop.
3. REFERENCE INTEGRATE (RI) PHASE: IN LO is
internally connected across the previously
charged reference capacitor. Circuitry within
the chip ensures that the capacitor will be
connected with the correct polarity to cause the
integrator output to return to zero. The time
required for the output to return to zero is
proportional to the value of input signal.
Specifically the digital reading displayed is
1. AUTO-ZERO (AZ) PHASE: First, input high and
low are disconnected from the pins and
Internally shorted to analog COMMON. Second,
the reference capacitor is charged to the
reference voltage. Third, a feedback loop is
closed around the system to charge the
auto-zero capacitor C AZ to compensate for
offset voltages in the buffer amplifier,
Since the
integrator,
and comparator.
comparator is included in the loop, the AZ
accuracy is limited only by the noise of the
system. In any case, the offset referred to the
Input is less than 10 JlV.
4. ZERO INTEGRATOR (ZI) PHASE: First, IN LO is
2. SIGNAL INTEGRATE (SI) PHASE: During this
phase, the auto-zero loop is opened, the
internal short is removed, and the internal input
high and input low nodes are connected to the
external pins. The converter then integrates the
differential voltage between IN HI and IN LO for
a fixed time. This differential voltage can be
shorted to analog COMMON. Second, a
feedback loop is closed around the system to
IN HI to cause the integrator output to return to
zero. Under normal condition, this phase lasts
from 100 to 200 clock pulses, but after an
overrange conversion, it is extended to 6200
clock pulses.
6-36
10,000
VIN
Si7135
. . . Siliconix
incorporated
~
DETAILED DESCRIPTION (Cent'd)
DIFFERENTIAL INPUT
The input can accept differential voltages anywhere
within the common mode range of the input
amplifier; or specifically from 0.5 V below the
positive supply to 1.0 V above the negative supply.
In this range the system has a typical CMRR of
86 dB. However, since the integrator also swings
with the common mode voltage, care must be
taken to insure that the integrator output does not
saturate. A worst case condition would be a large
positive common mode voltage with a near full
scale negative differential input voltage. The
negative input signal drives the integrator positive
when most of its swing has been used up by the
positive common mode voltage. For these critical
applications the integrator swing can be reduced to
less than the recommended 4 V full scale swing
with some loss of accuracy. The integrator output
can swing within 0.3 V of either supply without loss
of linearity.
ANALOG COMMON
Analog COMMON is used as the input low return
during AUTO-ZERO and REFERENCE INTEGRATE. If
IN LO is different from analog COMMON, a common
mode voltage exists in the system and is taken care
of by the excellent CMRR of the converter.
However, in most applications IN LO will be set at a
fixed known voltage (power supply common for
instance). In this application, analog COMMON
should be tied to the same point, thus removing the
common mode voltage from the converter. The
reference voltage is referenced to analog
COMMON.
REFERENCE
The reference input must be generated as a
positive voltage with respect to COMMON, as
shown in Figure 4.
DIGITAL SECTION
Figure 5 shows the digital section of the Si7135.
The Si7135 includes several pins which allow it to
operate conveniently in more sophisticated
systems. These include:
1. RUN/HOLD (R/H'> (Pin 25): When high (or open)
the Si7135 will free-run with equally spaced
measurement cycles every 40,002 clock
pulses. If taken low, the Si7135 will continue the
full measurement cycle and then hold this
reading as long as R/H is held low. A short
positive pulse (greater than 300 ns) will now
initiate a new measurement cycle, beginning
with between 1 and 10,001 counts of
AUTO-ZERO. If the pulse occurs before the full
measurement cycle (40,002 counts) is
completed, it will not be recognized and the
converter will simply complete the measurement it is doing. An external indication that a full
measurement cycle has been completed is that
the first strobe pulse (see below) will occur 101
counts after the end of this cycle. Thus, if R/H
is low and has been low for at least 101 counts,
the converter is holding and ready to start a
new measurement when pulsed high.
2.
STROBE (Pin 26): This is a negative-going
output pulse that aids in transferring the BCD
data to external latches for UARTs or
microprocessors. There are 5 negative-going
STROBE pulses that occur in the center of each
of the digit drive pulses and occur once and
only once for each measurement cycle starting
101 pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at
the end of the measurement cycle and stays on
for 201 counts. In the center of this digit pulse
(to avoid race conditions between changing
BCD and digit drives) the first STROBE pulse
goes negative for 1/2 clock pulse width.
Similarly, after digit 5, digit 4 goes high (for 200
clock pulses) and 100 pulses later the STROBE
pulse is sent. The digit drive will continue to
scan (unless the previous signal was
overrange) but no additional STROBE pulses will
be sent until a new measurement is available.
3. BUSY (Pin 21): BUSY goes high at the beginning
of signal integration and stays high until the first
clock pulse after zero-crossing (or after end of
measurement in the case of an overrange).
The internal latches are loaded during the first
clock pulse after BUSY goes high and are
latched at the end of this clock pulse. The
circuit automatically reverts to AUTO-ZERO
when not BUSY, so it may also be considered a
(ZI + AZ) signal. A very simple means for
transmitting the data down a single wire pair
from a remote location would be to AND BUSY
with CLOCK and subtract 10,001 counts from
the number of pulses received -- as mentioned
previously there is one "no-count" pulse in
each REFERENCE INTEGRATE cycle.
6-37
Si7135
frY' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
4. OVER-RANGE (Pin 27): This pin goes positive
when the input signal exceeds the range
(20,000) of the converter. The output is set at
the end of BUSY and is reset to zero at the
beginning of REFERENCE INTEGRATE in the next
measurement cycle.
5. UNDER-RANGE (Pin 28): This pin goes positive
when the reading is 9% of range or less. The
output flip-flop is set at the end of BUSY (if the
new reading is 1800 or less) and is reset at the
beginning of SIGNAL INTEGRATE of the next
reading.
6. POLARITY (POL) (Pin 23): This pin is positive for
a positive input signal. It is valid even for a zero
reading. In other words, +0000 means the
signal is positive but less than the least
significant bit. The converter can be used as a
null detector by forcing equal frequency of (+)
and (-) readings. The null at this point should
be less than 0.1 LSB. This output becomes
valid at the beginning of reference integrate
and remains correct until it is revalidated for the
next measurement.
7. DIGIT DRIVES (Pins 12, 17, 18, 19 and 20):
Each digit drive is a positive-going signal that
lasts for 200 clock pulses. The scan sequence
is Ds (MSD) , D4, D3, D2 and D1 (LSD). All five
digits are scanned and this scan is continuous
unless an overrange occurs. Then all digit
drives are blanked from the end of the strobe
sequence until the beginning of Reference
integrate when Ds will start the scan again. This
can give a blinking display as a visual indication
of overrange.
8. BCD (Pins 13, 14, 15 and 16): The binary'
coded decimal bits B8, B4, B2 and B1 are
positive logic Signals that go on simultaneously
with the digit driver signal.
COMPONENT VALUE SELECTION
For optimum performance of the analog section,
care must be taken in the selection of values for the
integrator capacitor and resistor, auto-zero
capacitor, reference voltage, and conversion rate.
4 V full scale integrator swing is fine, and 0.47 Jl.F is
nominal. In general, the value of CINT is given by:
CINT
=
CINT
=
INTEGRATING RESISTOR
The integrating resistor is determined by the full
scale input voltage and the output current of the
buffer used to charge the integrator capacitor. Both
the buffer amplifier and the integrator have a class
A output stage with 100 Jl.A of quiescent current.
They can supply 20 Jl.A of drive current with
negligible non-linearity. Values of 5 to 40 Jl.A give
good results. with nominal of 20 Jl.A, and the exact
value of integrating resistor may be chosen by:
RINT =
full scale voltage
20 J1.A
INTEGRATING CAPACITOR
The product of integrating resistor and capacitor
should be selected to give the maximum voltage
swing which ensures that the tolerance build-up will
not saturate the integrator swing (approximately
0.3 V from either supply.) For ±5 V supplies and
analog COMMON tied to supply ground. a ±3.5 to
6-38
(10,000) x (clock period) x liNT
integrator output voltage swing
(10,000) x (clock period) x (20 Jl.A)
integrator output voltage swing
A very important characteristic of the integrating
capacitor is that is has low dielectric absorption to
prevent roll-over or ratiometric errors. A good test
for dielectric absorption is to use the capacitor with
the input tied to the reference.
This ratiometric condition should read half scale
0.9999, and any deviation is probably due to
dielectric absorption. Polypropylene capacitors give
undetectable errors at reasonable cost. Polystyrene
and polycarbonate capacitors may also be used in
less critical applications.
AUTO-ZERO AND REFERENCE CAPACITOR
The size of the auto-zero capacitor has some
influence on the noise of the system. e.g. a large
capacitor reduces noise. The reference capacitor
should be large enough such that stray capacitance
to ground from its nodes is negligible.
Si7135
WY'Siliconix
,,6;JI incorporated
COMPONENT VALUE SELECTION (Cont'd)
The dielectric absorption of the reference and
auto-zero capacitors are only important at
power-on or when the circuit is recovering from an
overload. Thus, smaller or cheaper capacitors can
be used here if accurate readings are not required
for the first few seconds of recovery.
REFERENCE VOLTAGE
The analog input voltage (YIN) required to generate
a full-scale output is: VIN = 2 VREF.
The stability of the reference voltage is a major
factor in the overall absolute accuracy of the
converter. For this reason, it is recommended that
a high quality reference be used where
high-accuracy absolute measurements are being
made.
MAXIMUM CLOCK FREQUENCY
The maximum conversion rate of most dual-slope
AID converters is limited by the frequency
response of the comparator. The comparator in this
circuit follows the integrator ramp with a 3 I1S delay,
and at a clock frequency of 160 kHz (6 I1S period)
half of the first reference integrate clock period is
lost in delay. This means that the meter reading will
change from 0 to 1 with a 50 I1V input, 1 to 2 with
150 I1V, 2 to 3 at 250 I1V, etc. This transition at
mid-point is considered desirable by most users;
however, if the clock frequency is increased
appreciably above 160 kHz, the instrument will flash
"1" on noise peaks even when the input is shorted.
For many dedicated applications where the input
signal is always of one polarity, the delay of the
comparator need not be a limitation. Since the
non-linearity and noise do not increase substantially
with frequency, clock rates of up to 1 MHz may be
used. For a fixed clock frequency, the extra count
or counts caused by comparator delay will be a
constant and can be subtracted out digitally.
The clock frequency may be extended above
160 kHz without this error, however, by using a low
value resistor in series with the integrating
capacitor. The effect of the resistor is to introduce
a small pedestal voltage onto the integrator output
at the beginning of the REFERENCE INTEGRATE
phase. By careful selection of the ratio between this
resistor and the integrating resistor (a few tens of
ohms in the recommended circuit), the comparator
delay can be compensated and the maximum clock
frequency extended by approximately a factor of 3.
At higher frequencies, ringing and second order
breaks will cause significant nonlinearities in the
first few counts of the instrument.
The minimum clock frequency is established by
leakage on the auto-zero and reference capacitors.
With most devices, measurement cycles as long as
10 seconds give no measurable leakage error.
To achieve maximum rejection of 60 Hz pickup, the
SIGNAL INTEGRATE cycle should be a multiple of
60 Hz. Oscillator frequencies of 300 kHz, 200 kHz,
150 kHz, 120 kHz, 100 kHz, 40 kHz, 33 1/3 kHz,
etc. should be selected. For 50 Hz rejection,
oscillator frequencies of 250 kHz, 166 2/3 kHz,
125 kHz, 100 kHz, etc. would be suitable. Note that
100 kHz (2.5 readings/seconds) will reject both 50
and 60 Hz.
The clock used should be free from significant
phase or frequency jitter. Several suitable low-cost
oscillators are shown in the Applications section. If
the multiplexed output display takes significant
current from the logic supply, the clock should have
good PSRR.
ZERO-CROSSING FLIP-FLOP
The flip-flop interrogates the data once every clock
pulse after the transients of the previous clock
pulse and half-clock pulse have decayed. False
zero-crossings caused by clock pulses are not
recognized.
The flip-flop delays the true
zero-crossing by up to one count in every instance,
and if a correction were not made, the display
would always be one count too high. Therefore, the
counter is disabled for one clock pulse at the
beginning of phase 3. This one-count delay
compensates for the delay of the zero-crossing
flip-flop, and allows the correct number to be
latched into the display. Similarly, a one-count
delay at the beginning of phase 1 gives an overload
display of 0000 instead of 0001. No delay occurs
during phase 2, so that true ratiometric readings
result.
EVALUATING THE ERROR SOURCES
Errors from the "ideal" cycle are caused by:
1. Capacitor voltage droop due to leakage.
2. Capacitor voltage change due to charge
"drain-off" (the reverse of charge injection)
when the switches turn off.
3. Non-linearity of buffer and integrator.
6-39
iii
Si7135
.... 8i1iconix
incorporated
~
COMPONENT VALUE SELECTION (Cont'd)
4.
Charge lost by C REF in charging C STRAY.
Extreme care must be taken to avoid ground loops
in the layout of 8i7135 circuits. especially in
high-sensitivity circuits. It is most Important that
return currents from digital loads are not fed into
the analog ground line.
Charge lost by C AZ
POWER SUPPLIES
5. Integrating capacitor
dielectric absorption.
6.
7.
ANALOG AND DIGITAL GROUNDS
High-frequency limitations of buffer. integrator
and comparator.
non-linearity
due
to
and C INT to charge
CSTRAY·
The 8i7135 is designed to work from ±5 V supplies.
However. in selected applications. no negative
supply is required. The conditions to use a single
+5 V supply are:
NOISE
The
peak-to-peak
noise
around
zero
is
approximately 15 Jl.V (peak-to-peak value not
exceeded 95% of the time.) Near full scale. this
value increases to approximately 30 Jl.V. Much of
the noise originates in the auto-zero loop. and is
proportional to the ratio of the input signal to the
reference.
1. The input signal can be referenced to center of
the common mode range of the converter.
2. The signal is less than ±1.5 V.
8ee .. DIFFERENTIAL INPUT" for a discussion of the
effects this will have on the integrator swing without
loss of linearity.
TIMING DIAGRAM
INTEGRATOR
OUTPUT
I
AUTO
ZERO
10.0011
COUNTS
SIGNAL
INT.
10.0001
I
COUNTS
REFERENCE
INTEGRATE
20.001
COUNTS MAX.
FULL MEASUREMENT CYCLE
40,002 COUNTS
BUSY
OVER-RANGE
WHEN APPUCABLE
UNDER-RANGE
WHEN APPLICABLE
EXPANDED SCALE BELOW
DIGIT SCAN
FOR OVER-RANGE
~D5
~D4
~D3
~D2
~Dl
~C6~~T~1
STROBE
I I I I I
!1:-AUTO ZERO
DIGrr SCAN
FOR OVER-RANGE
~'"
• ARST Os OF AZ AND REF INT ONE COUNT LONGER
Figure 6. Timing Diagram
6-40
_
Si7135
..... Siliconix
incorporated
~
APPLICATIONS
The popular LCD displays can be interfaced to the
output of the Si7135 with suitable display drivers,
such as shown in Figure 7. A standard CMOS 4000
series LCD driver circuit is used for displaying the
1/2 digit, the polarity, and an 'overrange' flag. Of
-5 V +5 V
CLOCK IN
27
OR
23
POL
05 12
04 17
ANALOG
COMMON
-
INT OUT
ANALOG
GNO
Sl7135
03
02
01 20
Ba 16
BUF OUT
01
9
2a SEGMENTS
DG412
+5 V
VOO
Bl
Bl 13
lJl.F
t-----------'
91
B3
B2
B4 15
B214
INPUT HI
a~
:
04
03 1a
02 19
AZIN
INPUT
course, another full driver circuit could be ganged
to the one shown, if required. This would be useful
if additional annunciators were needed. The Figure
shows the complete circuit for a 4-1/2 digit
(±2.0000 V) AID.
BO
L.,..;;;;..
VSS _ _ _O;.;S;.;C;..! 200
RC+
a
~
Figure 7. Driving LCD Display
INTERFACING WITH MICROPROCESSORS
Circuits to interface the Si7135 directly with two
popular microprocessors are shown in Figures 8
and 9. The 8080/8048 and the MC6800 families with
8-bit words need to have polarity, overrange and
underrange multiplexed onto the digit 5 word. In
each case the microprocessor can instruct the ADC
when to begin a measurement and when to hold
this measurement.
The Si7135 is designed to work from ±5 V supplies.
However, if a negative supply is not available, it can
be generated using 2 capacitors, and an
inexpensive Si7660 or Si7661 IC (Figure 10).
~
r-
EN
S
E
L
E
C
lB 2B 3B T
lV
PAO
2V
PAl
lA 2A 3A 3V
PA2
74C157
::..
MC680X
I IIIIII
U 05 Ba B4 B2 Bl
N
01
L
0
E
02
SI7135
R
03
RUNI
0
4
HOLD STROBE
V
E
R
I
MCS650X
MC6820
P
°°
OR
PA3
PA4
PAS
PA6
PA7
CAl
I
CA2
I
Figure 8. Interface to 680X and 650X Families
6-41
Si7135
Siliconix
incorporated
APPLICATIONS (Cont'd)
.e.
~
-
EN
1Y
S
E
74C157 2Y
L
E
C
lB 2B 3B T lA 2A 3A 3Y
I e IIIII I
L
PAl
INTEL
PA2
BOBO
BOB5
PA3
ETC.
B255
(MODE 1)
~ 05 B8 B4 B2 Bl
P
0
0
E
R
RUNI
E
R
SI7135
Fi5t5 S'i'I'lOBE
01
02
03
04
I
~
PAD
PA4
PAS
PAS
PA7
PC4
PC6
I
J
Figure 9. Interface to 8080 Family
+5V
1 k.O.
2
10JlF
8
16 k.O. ...-----t--'II\l\r---+
+5V
SI7660
OR
0.22 JlF
120 kHz
CLOCK OUT
SI7661
3
5
VOUT= -5 V
39k.O.
-=-
+I
1OJlF
16 k.O.
'----,-----1
-=-
390 pF
Figure 10. Generating a -5 V Supply From a +5 V Supply
11 k.O.
Figure 11. Comparator Clock Circuit
11 k.O.
120 kHz
CLOCK OUT
C04069 INVERTERS
Figure 12.
6-42
R - C Clock Circuit
Si7240
12·Bit CMOS
Voltage-Output DAC
W'F' Siliconix
~
incorporated
FEATURES
BENEFITS
APPLICATIONS
• Fast Voltage Settling
Time: 550 ns to 0.01%
• Improved Data Throughput
• High Speed AID
Converters
• Total Unadjusted Error:
1 LSB Max
• Reduced Power Supply
• Improved Accuracy
• Eliminates Instability
In Servo Loops
• Low Power SingleSupply Operation (30 mW)
" Programmable Gain
Amplifiers
• Battery-Powered
Instrumentation
• Head Positioning Servos
• Excellent Differential
Nonlinearity: 1/2 LSB
Max over Temperature
DESCRIPTION
The Si7240 is a fast settling (550 ns typically to
1/2 LSB) 12-bit voltage-output digital-to-analog
converter. The Si7240 operates with a single +15 V
VDD supply and exhibits exceptionally fast settling
times due to the small (and code independent)
value of capacitance at the output of the DAC. The
Si7240 features 1 LSB total unadjusted error,
allowing fixed reference operation without the need
for external trims. All grades are guaranteed
monotonic to 12 bits over all temperature ranges,
in both the voltage mode and the current mode.
references, and digital servo systems. Its low
power consumption and single-supply operation
makes it ideal for battery operated and remote
instrumentation applications.
Built on the Siliconix PolyMOS process, the Si7240
uses highly stable thin film resistors which are
laser-trimmed for excellent accuracy. An epitaxial
layer prevents latchup.
Applications for the Si7240 include high-speed AID
converters, digitally-controlled power supplies and
The Si7240 is available in 18-pin plastic
commercial, J, K suffix (0 to 70°C), industrial, A, B
suffix (-40 to 85°C), and military, S, T suffix (-55
to 125°C) temperature range.
PIN CONFIGURATION
FUNCTION BLOCK DIAGRAM
Dual-In-Llne Package
Top View
R BIAS
AGND
DGND
V OUT
V DD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 4
BITS
BIT 9
BIT B
- '_ _ _.-- BIT 7
DGND
BIT 1
(MSB)
BIT 12
(LSB)
ORDERING INFORMATION
Total Unadjusted Error
Plastic
CerDIP
Side Brazed Ceramic
TA = TMIN to TMAX
o to 70°C
-40 to 85°C
-55 to 125°C
+1/2, -2 LSB
+114, -1 1/2 LSB
SI7240JN
SI7240KN
SI7240AQ
Si7240BQ
SI7240SD
SI7240TD
Preliminary
6-43
..
WY'Siliconix
incorporated
Si7240
~
ABSOLUTE MAXIMUM RATINGS
Voo to DGND .................•....... -0.3 V, +17 V
Digital Input Voltage to DGND .............. -0.3V, Voo
Power Dissipation (Any Package) to 75·C ...... 450 mW
Derates above 75·C ......•................. 6 mW/·C
VBIAS, VO UT to DGND •........................ ±25 V
Operating Temperature (J, K Suffix) ......... 0 to 70·C
(A, B, Suffix) ...... -40 to 85°C
(S, T Suffix) •..... -55 to 125·C
V REF to DGND ........•................ -0.3 V, Voo
Storage Temperature .................... -65 to 150·C
AGND to DGND ......................•.. -0.3V, voo
Lead Temperature (Soldering, 10 seconds) ....... 300·C
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
K,B,T
J,A,S
2=125,85,70·C
SUFFIX
SUFFIX
Voo= 15 V, VREF= 1.23 V
3=-55,-40,0 ·C
AGND = DGND = RBIAS = 0 V
TEMP TYpd MINb MAX' MIN b MAxt UNIT
SYMBOL
PARAMETER
ACCURACY
Resolution
Total Unadjusted Errore,
Relative Accuracye,
f
f
Full Scale (Gain) Error e,
f
N
1,2,3
12
ET
1
2,3
-1.0
-1.5
0.5
0.5
-1.25
-2.0
0.5
0.5
INL
1
2,3
-1.0
-1.5
0.5
0.5
-1.25
-2.0
0.5
0.5
GE
1
2,3
-0.5
-0.5
0.5
0.5
-1.25
-2.0
0.5
0.5
1,2,3
-1.2
1.2
-6
6
1
2,3
-0.5
-0.5
0.125
0.25
-0.5
-0.5
0.25
0.5
-0.5
0.5
-0.5
0.5
Full Scale (Gain) C
Tempco
TC GE
Zero Code (Offset)
Error e, f
Vas
fl Full Scale I fl Temperature
12
Bits
LSB
ppml
·C
LSB
DNL
Monotonic to 12-Blts
1,2,3
PSRR
Voo= 15.5 V to 14.5 V
All Digital Inputs HIGH
1
2,3
Input Resistance
(Pin 1)
RREF
Approximately 0.67 X RLAOOER
1,2,3
All Digital Inputs LOW
1,2,3
40
40
Input Capacltance C
(Pin 1)
CREF
All Digital Inputs HIGH
1,2,3
100
100
Differential Non-linearitye,
Power SUP~IY
Rejection atlo
f
-0.005 0.005 0.005 0.005
-0.01 0.01 -0.01 0.01
%
per
%
REFERENCE INPUT
4.7
4.7
k.o.
pF
DIGITAL INPUT
Input HIGH Voltage
VINH
1,2,3
Input LOW Voltage
V 1NL
1,2,3
2.4
2.4
V
6-44
0.8
0.8
Preliminary
Si7240
IfF Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
K,B,T
J,A,S
2=125,85,70 oC
SUFFIX
SUFFIX
Voo= 15 V, VREF= 1.23 V
3=-55,-40,OoC
AGND = DGND =RBIAS = 0 V
TEMP TYpd MINb MAX' MIN b MAXt
SYMBOL
UNIT
DIGITAL INPUTS (Cent1d)
1,2,3
-1
Input Leakage Current
liN
Input Capacitance
C IN
1,2,3
Output Capacltance C
(Pin 17)
COUT
1,2,3
Output Resistance
(Pin 17)
ROUT
1,2,3
12
Output Resistance Tempco
TC RO
1,2,3
-300
Bias Resistor
RBIAS
1,2,3
12
1,2,3
0.1
VIN = 0 V or 15 V
1
-1
1
JlA
8
8
pF
2.8
2.8
pF
15
IQl.
ANALOG OUTPUT
Bias and Ladder
Resistor Matching
7
15
7
ppm I
°C
7
15
7
15
IQl.
%
DYNAMIC
Propagation Delay c, g
tpo
Voltage Settlln~
Time c, g, h, I,
Measured From 50% of Digital
Input to 10% of Final Analog
Output
1,2,3
To 0.01% of FSR For All O's
to Alil's or alil's to All O's
1,2,3
550
To 0.04% of FSR For All O's
to Alil's or all1's to All O's
1,2,3
470
To 0.2% of FSR For All O's
to Alil's or alil's to All O's
1,2,3
400
100
100
900
900
ns
Voltage Settling Time
(J, K Grades)
t.
45
Glitch Impulse g
nV-s
POWER SUPPL.Y
Voo Range
Voo
Supply Current
100
Preliminary
Accuracy Is Guaranteed At
Voo= 15 V
1.2,3
All Digital Inputs VIL or VIH
1,2,3
All Digital Inputs 0 V orVoo
1,2,3
5
16
5
16
V
2
2
mA
100
100
JlA
6-45
Si7240
~
~
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. 1 LSB ='VREF/4096.
f. DAC Load RL >10 10.0. •
g. Input logic levels 0 V and 5 V.
h. External load = 2.8 pF.
I. Side braze versions exhibit 10% longer settling times than plastic versions.
J. FSR = Full Scale Range.
CAUTION
ESD (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are zener protected;
however, permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The foam should be
discharged to the destination socket before devices
are removed.
DEFINTION OF TERMS
TOTAL UNADJUSTED ERROR
This is a comprehensive specification which
includes gain error, relative accuracy and zero
code offset when configured as shown in Figure 5.
Absolute full'scale is VREF -1 LSB (IDEAL) where 1
LSB (IDEAL) is
V~EF
4096
Note: "ERROR" defined is ACTUAL VALUE - IDEAL
VALUE.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB max over the
operating temperature range ensures monotonicity.
DETAILED DESCRIPTION
CIRCUIT INFORMATION
Analog Section
RBIAS
v REF
The Si7240 12-bit voltage DAC consists of a highly
stable thin film R-2R ladder and twelve high speed N
MOS single pole double throw switches.
AGND
BIT 12
(LSB)
BIT 3
I
I
?---------?
BIT 2
BIT 1
(MSB)
?I
?I
I
The Si7240 has low capacitance at the VOUT
terminal, and hence exhibits fast output voltage
settling times.
The simplified circuit diagram of the DIA converter
is shown in Figure 1.
6-46
V OLIT
Figure 1. SI7240 Funtlonal Diagram (Inputs High)
Preliminary
Si7240
...... Siliconix
incorporated
~
DETAILED DESCRIPTION
.....
Digital Section
The 12 digital inputs are designed to be both TTL
and 5 V CMOS compatible when VDD equals +15 V.
All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. Internal
input protection is achieved by an on-chip
distributed diode from GND to each MOS gate. To
minimize power supply current, it is recommended
that the digital input voltages be driven as close to
the supply rails (VDD and GND) as practically
possible.
J•
1~:!4
a..;:.,;.J
p;:
~
II
•
;;;
..
...
'-
.~~
DYNAMIC PERFORMANCE
- ••
..
.1
•
~
~
Figure 2. SI7240 Transient Response Waveform
Output Impedance
When operated in the voltage switching mode the
Si7240 exhibits code independent (fixed) output
capacitance and output resistance. _This means that
settling time of the Si7240 is virtually the same for
all code changes when operated as per Figure 4.
In contrast, the output impedance and thus the
settling time of current mode DACs is code
dependent. Moreover, with a current mode CMOS
DAC the large output capacitance places a
limitation on the realizable settling time, even when
using a fast output op amp.
The low values of output capacitance of the Si7240
ensure very fast voltage settling when configured
with a high speed follower.
Figure 3 shows the glitch energy waveform for the
major transition. Figure 10 shows the circuit used to
achieve the waveforms shown in Figures 8 and 9.
..
~ ~ III[ §..
11
~
iiiiiiiii
..
rn ..
i
l
IJ I:!!
11
••
= IJ
Settling Time
L.;. ~
l~
II
III
=
•
Figure 3. SI7240 Major Transition Glitch
The time taken for voltage settling of the Si7240 to
less than 1/2 LSB is given by the approximation:
voo= +15 V
• Settling Time - tpD + 9R (COUT + CEXT)
t PD
- Logic Propagation Delay
R
- DAC Ladder Resistance
COUT
- DAC Output Capacitance
- Capacitance due to External Circuit .
• Assuming very high load impedance.
Figure 2 shows the output voltage transient
response waveform for the transition resulting when
all digital inputs change from 0 to +5 V.
Preliminary
c 1 = 10J.LF TANT
O2 = 0.01 J.LF OER
Figure 4. Dynamic Performance Test Circuit
6-47
Si7240
...... 5i1iconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
VOLTAGE REFERENCE
The input impedance at the VREF pin of the 8i7240
is code dependent and can vary from 7 k.O. up to
infinity. The nodal capacitance at the reference
terminal is also code dependent and typically varies
from 40 pF to 90 pF. Therefore it is essential that
the reference be adequately decoupled at pin 1 of
the 8i7240 in order to present a low output
impedance and thus maintain full accuracy under
changing load conditions.
APPLICATIONS
Figure 5 shows the equivalent circuit of the output
of the 8i7240.
LOAD IMPEDANCE
The 8i7240 equivalent output circuit of Figure 5
shows a Thevenin voltage source VREFD with a fixed
output resistance and capacitance of Rand C OUT
respectively. 0 is a fractional representation of the
digital input word N I.e. 0 = N/4096.
R
Resistive loading at pin 17 of the 8i7240 causes
scale factor error. Op amp bias current through the
DAC output impedance (12 k.O. nominal) Introduces
an offset term.
For example, a 60 M.o. load resistance on pin 17
introduces a 1 L5B scale factor error at pin 17. Op
amp bias current of 25 nA introduces a 1 L8B offset
term. Effects of amplifier bias current can be
minimized by ensuring the parallel combination of
R1 and R2 (Figure 6) Is equal to the DAC's output
Impedance at pin 17 (nominally 12 k.O.). If the
amplifier circuit (of Figure 6) is configured to
provide a gain of +1, resistor R2 should be Included
and should equal 12 k.O. to minimize output error
due to bias current.
C OUT
~----------~--~AGND
R - DAC LADDER RESISTANCE (12 kA TYP)
CO UT - DAC OUTPUT CAPACITANCE (2.8 pF MAX)
- THEVENIN VOLTAGE SOURCE (0 s D S 4095/4096)
VRE~
Figure S. Equivalent Output Circuit of Sl7240
The 5i7240 can operate in several different modes.
Each mode has its own particular characteristics.
These are summarized below and discussed in
detail in the paragraphs following.
OPERATION MODES
VOLTAGE SWITCHING MODE
The circuit in Figure 6 shows the 5i7240 connected
In the voltage switching mode. 8ince V OUT is the
same polarity as VREF, this configuration allows
single supply operation. Note that the voltage VREF
must always be positive with respect to DGND in
order to prevent parasitic transistor turn-on.
Figure 6. SI7240 In Single Supply Voltage Switching
6-48
Preliminary
Si7240
..... Siliconix
incorporated
~
OPERATION MODES (Cent'd)
To maintain linearity, the voltages at VREF and
AGND should remain within 2.0 volts of each other
for a VDD of +15 V. IfVDD is reduced from 15 V or
the differential voltage between VREF and AGND is
increased to more than 2.0 volts, the accuracy of
the DAC will be degraded. Note that the output
voltage range has been extended by using a
noninverting gain stage.
The output
Your
is expressed as:
Where D is a fractional representation of the digital
input word (O!:: D !:: 4095/4096).
Fastest settling can be achieved by using a dual
supply op amp.
VOLTAGE SWITCHING MODE WITH AGND BIAS
VOLTAGE
AGND can be biased above DGND to provide an
offset "zero" analog output voltage level. Figure 7
shows this circuit configuration. As in Figure 6, the
output voltage range has been extended by using a
noninverting gain stage to buffer the DAC.
The output voltage
Your
is expressed as:
Where VIN !:: +2.0 V, and where D is a fractional
representation of the digital input word (0 !:: D
!:: 4095/4096).
The effect of R BIAS on total unadjusted error and
differential nonlinearity will be the same as reducing
VDD by the amount of the offset.
VOLTAGE SWITCHING MODE - OFFSET BINARY
OPERATION
Figure 8 shows a circuit used to implement offset
binary coding in the voltage switching mode.
Mismatch between R 1 and R2 causes both offset
and full scale error, therefore, these resistors must
match (to within 0.01 %) and track over
temperature.
Table 1 shows the digital code vs. output voltage
relationship for Figure 8.
Table 1
Offset Binary Code Table for
Figure 8 with R1 = R2
Digital Input
Analog Output
1111
1111
1111
+VREF • -047
2048 )
1 000
0000
0000
0000
0000
0000
e
OV
-VREF
Figure 7. SI7240 In Single SliPply Voltage Switching
Mode with AGND Bias Voltage
Preliminary
6-49
..
Si7240
W7" Siliconix
,,6;JI incorporated
OPERATION MODES (Cont'd)
Figure 8. 517240 In Offset-Blnal'll
Voltage-Switching Moae
6-50
Preliminary
Si7533
CMOS 10-Bit
Multiplying DAC
..... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Full Four Quadrant
Multiplication
• Allows AC Attenuation
Without Biasing
• Programmable Gain
Amplifiers
• 1/2 LSB INL
• True 10-Bit Linearity
• Low Gain Drift
« ±0.1 % over temp)
• Reduced Calibration
• Digitally Controlled
Attenuators And
Amplifiers
• Simplified Logic
Interface
• Remote Systems
• TTL/CMOS Compatible
• Motion Control Systems
• Programmable Power
Supplies
DESCRIPTION
The Si7533 is a CMOS multiplying digital-to-analog
converter which provides 10 bit accuracy and full
four-quadrant multiplication. It is pin- and
function-compatible with Analog Devices' AD7533
and AD7520, and is recommended for updating
existing AD7520 applications.
Built on the Siliconix proprietary PolyMOS'"
process, the Si7533 uses laser-trimmed thin film
resistors to provide full 1a-bit linearity, 1.4%
maximum gain error, and less than 0.1% gain drift
over the full range of temperatures. An epitaxial
layer prevents latchup.
Applications include digitally-controlled attenuators,
filters, amplifiers and power supplies, disk drive
head positioning. servo loops. industrial controllers
and avionic systems.
The Si7533 is available in 16-pin Plastic DIP. CerDIP,
and Side Braze packages for operation over the
commercial, J, K. L suffix (0 to 70°C). industrial.
A. B. C suffix (-40 to 85°C) and military. S. T, U
suffix (-55 to 125°C) temperature ranges.
respectively. For surface mount applications. the
Si7533 is available in the 20-pin PLCC for
commercial and LCC for military applications.
PIN CONFIGURATION
Dual-In-Llne Package
RFB
V REF
VDD
Bit 10 (LSB)
LCC Package
Bit 9
Bit 8
Bit 7
PLCC Package
OUTI
0UT21
NC
'"1.::""_;.r Bit 6
8 VDD
GND 4
(MSB) Bit 1 5
NC 6
7 Bit 10 (LSB)
6 NC
Bit 38
9 10111213
Bit 4
I I
NC
Bit 5
Bit 7
Bit 6
Preliminary
Top Views
Not to Scale
6-51
Si7533
..... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
10 k
10 k
10 k
-----vv-~-----,
20 k
OUT2
OUT1
I
I
6
6
BIT 1
BIT 2
R FEEDBACK
BIT 3
BIT 10
(LSB)
(MSB)
ORDERING INFORMATION
Relative
Accuracy
Tmln
Tmax
-
± 0.05%
± 0.1%
± 0.2%
Temperature Range and Package
DIP
Plastic
0 to 70·C
PLCC
o
to 70·C
CerDIP
Side
Brazed
Ceramic
LCC
-40 to 85 ·C
-55 to 125·C
-55 to 125·C
SI7533LN
SI7533LP
SI7533CQ
SI7S33UD
SI7533UE
SI7S33KN
SI7533JN
SI7S33KP
SI7533JP
SI7S33BQ
SI7533AQ
SI7533TD
SI7S33SD
SI7S33TE
SI7533SE
ABSOLUTE MAXIMUM RATINGS
VDD to GND ........••.••..•.••.•••.••. -0.3 V. +17 V
VREF to GND .................•.•••.••..•••..• ±2S V
VRFB to GND . . . . . . . • . • . . . • . • • • • • • . • • . . . . . . . .. ±2S V
Digital Input Voltage to GND •••.••..••... -0.3 V to VDD
V OUT1 • VOUT2 to GND ....•..•.••....... -0.3 V toVDD
Storage Temperature (D. E. Q Suffix) ..••• -65 to 150·C
(N. P Suffix) .•..... -65 to 125·C
Operating Temperature (D. E Suffix) ...... -55 to 12S·C
(Q Suffix) ••....... -40 to 8S·C
(N. P Suffix) ••..••... 0 to 70·C
Power
16-Pln
16-Pln
16-Pln
20-Pln
Dissipation (Package)·
Plastic DIp·· •.....••.••••..•.........
Ceramic Side Brazed··· ...............
CerDIP··· •....................•.•.••
PLCC···· .......................•.••
470
900
900
4S0
mW
mW
mW
mW
All leads welded or soldered to PC Board.
Derate 6.5 mW'·C above 25·C.
Derate 12 mW'·C above 7S·C.
•••• Derate 10 mW'·C above 25·C.
CAUTION
ESD (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are diode protected;
however. permanent damage may occur on
unconnected devices subject to high energy
6-52
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
Preliminary
Si7533
flY' Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Vee = 15 V, V REF = 10 V
V OUT1 =VOUT2 = 0 V
Output Amplifier = OP-07
LIMITS
1=25°C
2=125,85,70oC
3=-55,-40,OoC
TEMP
TYP d
ALL
GRADES
MIN b MAX b
UNIT
ACCURACY
Resolution
Relative Accuracye,
Gain Error e,
1,2,3
10
J, A, S Grades
1,2,3
-0.2
0.2
K, B, T Grades
1,2,3
-0.1
0.1
L, C, U Grades
1,2,3
-0.05
0.05
1
2,3
-1.4
-1.5
1.4
1.5
1,2,3
-0.1
0.1
All Digital
Inputs =VIL
1
2,3
-50
-200
50
200
All Digital
Inputs =VIH
1
2,3
-50
-200
50
200
5
20
N
h
INL
G FSE
h
Bits
% FSR
Measured Using Internal R FB
Gain Drlft C , e,
h
IOUT1(OFF)
Output Leakage Current
VREF = ±10 V
IOUT2(OFF)
nA
REFERENCE INPUT
Reference Input Resistance f
RREF
1,2,3
Input HIGH Voltage
VIH
1,2,3
Input LOW Voltage
V IL
1,2,3
Input Leakage Current
liN
10
I4l.
LOGIC INPUT
2.4
V
1,2,3
0.8
-1
1
J1A
5
pF
Digital Inputs = 0 V or Vee
Input Capacltance c
C IN
1,2,3
SUPP1.Y
AGain IAVee
Vee = 14 to 17 V
Power Supply Rejection
1
2,3
-0.005
-0.008
5
Vee Range C
Vee
+15 V for Rated Accuracy
1,2,3
Supply Current
Icc
All Digital Inputs V IL or VIH
1,2,3
Preliminary
0.005
% per %
0.008
16
V
2
mA
6-53
Si7533
~
~
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Voo = 15 V, VREF= 10 V
VOUTl =VOUT2 = 0 V
Output Amplifier = OP-07
LIMITS
1=25·C
ALL
2=125,85,70·C
GRADES
3=-55,-40,O·C
TEMP TYP d MIN b MAX
b
UNIT
DVNAMIC ACCURACV
Feedthrough Error c, I
(VREF to OUT1 )
Output Current Settling
Tlme c , g
ts
Digital Inputs =VIL
VREF=±10 V, 100 kHz Sine Wave
1
2,3
To 0.05% of FSR
OUT 1 Load = 100.0.
1
2,3
600
800
OUT1
1,2,3
80
OUT2
1,2,3
40
1.4
2.8
% FSR
ns
Digital Inputs = VIH
Output Capacltance c
pF
COUT
OUT1
1,2,3
40
OUT2
1,2,3
80
Digital Inputs = VIL
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. FSR = Full Scale Range = - (V REF )('023/'024) In unipolar mode.
f. Absolute TC for RREF Is apllroxlmately -300 ppm/·C.
g. Digital Inputs =VIH toVIL or VIL toVIH .
h. 0.1% FSR = 1 LSB = 1 mY.
I. Feed through for Side Braze package versions Is Improved to typically 0.4% FSR.
DETAILED DESCRIPTION
The Si7533 is a 10-bit multiplying Digital-to-Analog
Converter consisting of a highly stable thin film R-2R
ladder network and ten single-pole double-throw
current steering NMOS analog switches on a
monolithic chip. The binarily weighted CMOS level
shifters provide low power TTL/CMOS compatible
operation. An external voltage or current reference
and an operational amplifier are all that is required
for most applications.
The binary weighted currents are switched between
the OUT1 and OUT2 bus lines, thus maintaining a
constant current in each leg of the ladder
regardless of switch states.
The input resistance at VREF (Figure 1) is always
equal to the value "RREF" and is the R-2R ladder
characteristic resistance. Since RREF at the VREF
pin is constant, the reference terminal can be
driven by a reference voltage or a reference
current, be it positive, negative or AC. If a current
6-54
source is used, a low TC external feedback resistor
RFB is recommended to define the scale factor.
10 k
10 k
'--I-+.....--oOUT2
'--0-;....,.--0
OUT1
I
I
b
BIT 1
(MSB)
b
BIT 2
BIT 3
~L~~~
RFEEOBACK
= 10 k.n.
Figure 1. SI7533 Functional Diagram
(All Inputs HIGH)
Figure 2 illustrates the typical NMOS SPDT switch
with its associated CMOS level shifter/driver.
Preliminary
Si7533
trY' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cant'd)
v+
inputs LOW. All reference current is switched to
OUT2. The current sources I LEAKAGE are
composed of surface and junction leakages to the
substrate. The 1/1024 current source represents
the constant 1 LSB current drain through the ladder
termination resistor. The output capacitance on
OUT2 (with all its switches ON) is 80 pF, whereas on
OUT1 it is only 40 pF.
o-------~------~----~
POLY
RESISTOR
The output capacitances are dependent upon the
digital input code and vary between the LOW and
HIGH values.
Figure 2. Simplified Schematic
Single SPOT Switch
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for all digital
Analysis of the circuit for all digital inputs HIGH, as
shown in in Figure 4 is similar to Figure 3; however
the "ON" switches are now on OUT1, hence the 80
pF at that terminal.
.--_ _R.QFEEDBACK
.---_ _OR FEEDBACK
R=
10 kn.
IOUT1
IR~
vREF
R = 10 kn.
-
R
~ R= 10kn.
1/1024
t
-
ILEAKAGE
I
= 1~ k.n.
IOUT1
BOPF
IOUT2
+
-
IREF
-
IOUT2
-
Figure 3. 517533 Equivalent Circuit
(All Inputs LOW)
Figure 4. 517533 Equivalent Circuit
(All Inputs HIGH)
APPLICATIONS
APPLICATIONS HINTS
Static linearity of the Si7533 depends upon the
potential of OUT1 and OUT2 (pins 1 and 2) being
exactly equal to GND (pin 3). In most applications
the DAC is connected to an external output op amp
with its non-inverting input tied to ground, which
converts its current output into a voltage output
signal. The op amp selected should have a low
input bias current (typically less than 75 nA) and
low drift over the operating temperature range. The
Preliminary
amplifier's input offset voltage should be nulled to
less than 10% of 1 LSB. The non-inverting input
should be connected directly to GND without the
usual input bias current compensation resistor. This
resistor can cause variable offsets which would
create errors. Ground loops should be avoided by
taking all pins going to GND to a common point.
The Voo power supply should have a low noise level
and not have transients greater than +17 V.
6-55
W'1I' Siliconix
Si7533
~
incorporated
APPLICATIONS (Cont'd)
Unused digital inputs must be grounded or taken to
VDD. It is also recommended that all digital inputs
be taken to ground via a high value (1 MIl) resistor
to prevent the accumulation of static charges
whenever the PC board is not connected to the
system.
OUTPUT OFFSET: CMOS DACs exhibit a code
dependent output resistance which can cause a
code dependent error voltage at the output of the
amplifier. The maximum value of this error is
0.67 Vas, where Vas is the amplifier input offset
voltage.
To maintain monotonlcity it is recommended that
Vas be no greater than (100 x10(-6)) VREF over the
operating temperature range. It is also important
that Vas be nulled, either by using the op amp's
nulling pins or an external network.
DIGITAL GLITCHES: One cause of glitches is
capacitive coupling from the digital lines to the
OUT1 and OUT2 terminals. This can be minimized
by guarding the analog pins of the Si7533 (pins 1,
2, 15, 16) from the digital input pins by a ground
track run between pins 2 and 3 and between pins
14 and 15. Note that the analog pins are at one end
of the package separated from the digital inputs by
VDD and GND to aid guarding.
OUTPUT AMPLIFIER: For low speed applications the
AC specifications of the op amp are not critical. In
high-speed applications, however, slew rate,
settling time, open-loop gain, gain/phase margin
specifications of the amplifier should be selected
for the desired performance. As mentioned before,
the usual bias current compensation resistor at the
inverting input of the op amp should not be used.
Instead, the amplifier should have a low input bias
current over the operating temperature range.
multiplication (digitally controlled attenuation). The
reference input voltage can range between -20 V
and +20 V due to the ability of VREF to exceed VDD.
Table 1 shows the digital code input analog voltage
~:--~"I R FEEDBACK
BIT 1 O--,.-IM
(MSB)
DIGITAL
INPUT
Brr 10Io---L-IM
2 IOUT2
(LSB)
L--+_..1
Figure 5. UnIpolar BInary OperatIon
(2 - Quadrant)
correspondence. R1 provides full-scale trimming
(load the DAC with 1111111111 , adjust R1 fOrVOUT
= -VREF (1 023/1 024)). Full-scale can also be
adjusted by omitting R1 and R2 and trimming the
magnitude of VREF.
TABLE 1.
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT
(VOUT )
1111111111
-(1023/1024) VIN
1000000000
-(51211024) VIN
0000000001
-(1/1024) VIN
0000000000
OV
UnIpolar BInary Code Table for CIrcuIt
of FIgure 5
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
BIPOLAR BINARY OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 shows the circuit configuration required for
unipolar binary (2-quadrant multiplication) operation. With a DC voltage or current-reference
(positive or negative) applied at pin 15, the circuit
is a unipolar Digital-to-Analog converter. With an AC
reference
this
circuit
provides
2-quadrant
Figure 6 illustrates the recommended circuit for
bipolar operation. With a DC reference of either
polarity the circuit provides offset binary operation.
With an AC reference, the nine LSBs provide
digitally controlled attenuation of the
reference
input while the MSB provides polarity control.
6-56
Preliminary
Si7533
..,... 8i1iconix
incorporated
~
APPLICATIONS (Cont'd)
SINGLE SUPPLY OPERATION
The circuit of Figure 7 shows the 8i7533 connected
in a voltage switching configuration. The reference
voltage is applied to OUT1 and OUT2 is connected
to ground. The DAC output is available at pin 15
(VREF pin) and has a constant output impedance
equal to RREF. The internal feedback resistor (pin
16) is not used. For better linearity in the voltage
switching mode, the 8i7240 should be specified.
DIGITAL
GROUND
ANALOG
GROUND
VDD=+15 V
Figure 6. Bipolar Operation
(4 - Quadrant Multiplication)
14
151---1
With the DAC loaded to 1000000000. adjust R1 for
VOUT =0 V (alternatively. R1 and R2 can be omitted
and the ratio of R3 to R4 can be adjusted forVOUT
o V). Full-scale trimming can be performed by
adjusting VREF or by adjusting the value of R5.
VREF
<2.5 V
VOUT
=
As in unipolar operation the amplifiers must be
chosen for low input offset voltage and low input
bias current. The input offset voltage of both
amplifiers should be adjusted to less than 0.4 mV
and be better than 2 mV over the operating temperature range of interest. R3, R4 and R5 must be
matched. Mismatches of R5 to R4 and (2 X R3)
cause full-scale error. Mismatch of (2 X R3) to R4
causes both offset and full-scale errors.
Table 2 illustrates the relationship between the
offset binary digital codes and the analog output
voltage.
TABLE 2.
DIGITAL INPUT
MSB
LSB
1111111111
ANALOG OUTPUT (VOUT)
1000000000
VIN
+(11512) VIN
OV
0111111111
-(1/512)
0000000000
-VIN
1000000001
+(511/512)
VIN
Bipolar Binary Code Table for Circuit
of Figure 6
Preliminary
BITS 1 - 10
SYSTEM
______~--------+_--__+___~G~ROUND
C1 = 10Jl,F ELECTROLYTIC
C2 = 0.1J1,F CERAMIC
R1
II R2 = 10 k.n.
Figure 7. Single Supply Operation
Using Voltage Switching
The reference voltage must always be positive in
the voltage switching mode. If pin 1 goes below
-0.3 V an internal diode will be turned on. If not
limited a large current will flow and may cause
device damage. 8ince the 8i7533 is protected for
8CR latch-up. removing the abnormally negative
reference voltage will restore normal operation
provided the maximum current handling capacity
(20 mAl has not been exceeded.
Loading on the reference voltage source is code
dependent and the response time of the circuit is
often determined by the ability of the reference
voltage source to handle the changing load
conditions. For this reason bypassing of the
reference source is required. To maintain linearity
the reference voltage at pin 1 should remain within
2.5 V of GND, for aVDD = 15 V. IfVDD is reduced or
the reference voltage increased. the DAC's
linearity and differential nonlinearity will be
degraded.
6-57
W'F' Siliconix
Si7541
CMOS 12-Bit
Multiplying DAC
~
BENEFITS
APPLICATIONS
• 12-Blt Linearity
(INL < 1/2 LSB)
• Improves System
Absolute Accuracy
• ATE Systems
• Four Quadrant
Multiplication
• Allows Bipolar
Reference Inputs
• Fast Settling (600 ns)
• Increases Data Throughput
• Monotonic (DNL < 1/2 LSB)
• Closed-Loop Servo
Stability
FEATURES
• TTL/CMOS Compatible
incorporated
• Digitally Controlled
Gain/ Attenuation
• Function Generators
• Closed-Loop Servo
Systems
• Hybrid/Custom
A/D Converters
• Simplifies Logic
Interfacing
DESCRIPTION
chip for low drift over temperature and time. These
are laser-trimmed to achieve 1/2 LSB integral
nonlinearity (INL) and reduced gain error. An
epitaxial layer prevents latch up.
The Si7541 is a 12-Bit multiplying digital-to-analog
converter which features true 12-bit integral
linearity and monotonicity, fast settling time
(600 ns), TTL-compatible logic inputs, and low gain
drift of 5 ppm/oC (max). The 1/2 LSB differential
nonlinearity specification guarantees monotonicity,
thus eliminating instability in closed-loop systems.
The Si7541 is available in 18-pin PDIP, CerDIP and
side braze DIP packages for commercial, J, K suffix
(0 to 70°C), industrial, A, B suffix (-40 to 85°C)
and military, S, T suffix (-55 to 125°C) operation,
respectively. For surface mount applications, the
Si7541 is available in the PLCC-20 (0 to 70°C) and
the hermetic LCC-20 (-55 to 125°C) . Each
package and temperature range is available in two
linearity grades.
Multiplying applications for the Si7541 include
digitally controlled amplifiers, attenuators, filters
and power supplies. The fast settling time makes
the Si7541 ideal for high speed data conversion and
hybrid or custom A/D converters.
The Si7541 is built using the Siliconix advanced
5-mlcron CMOS process known as PolyMOS no ,
allowing fast settling time and low glitch impulse.
Highly-stable thin film resistors are included on the
For more information on the Si7541, please refer to
Siliconix Application Note AN87-3.
PIN CONFIGURATION & ORDERING INFORMATION
PLCC Package
,
GNO ~
BIT 1 (MSB) ~
BIT2 ~
OUT1
OUT2
GNO
Top View
BIT 9
BIT 5 9 1 11 21P3 BIT 8
BIT 6 NO BIT 7
INL
Tmln - Tmax
(LSB)
:!: 1
:!: 1/2
6-58
RFB
V REF
VOO
GND
BIT 12 (LSB)
BIT 1 (MSB)
BIT 11
BIT 2
BIT 10
voo
BIT 12 (LSB) BIT 1 (MSB)
BIT 2
BIT 11
BIT 3
BIT 10
BIT3 ~
BIT 4 8
GAIN
ERROR
Ta = 25°C
(LSB)
:!:
:!:
12.5
12.5
LCC Package
Dual-ln-L1ne Package
OUT 1 NORFB
OUT 2 311 211111201"9 vREF
voo
BIT 12 (LSB)
BIT 11
BIT 4
BIT 9
BIT 3
BIT 10
BIT 5
BIT 6
BIT 8
BIT 7
BIT 4
BIT 9
BIT 5 BIT 6 N
Top View
0
BIT 7
BIT 8
TEMPERATURE RANGE AND PACKAGE
PLCC
o to 700C
SI7541JP
SI7541KP
PDIP
o to 700C
SI7541JN
SI7541KN
CerDIP
-40 to 85"C
SI7541AQ
SI7541BQ
SIDE BRAZE
-55 to 125°C
SI7541SO
S17541TD
LCC
-55 to 125°C
SI7541SE
S17541TE
Si7541
trr' Siliconix
~
incorporated
FUNCTION BLOCK DIAGRAM
10 kO.
10 kO.
OUT2
OUT1
I
6
BIT 1
(MSB)
RFEEOBACK
BIT 3
BIT 2
BIT 12
(LSB)
DEFINITION OF TERMS
GAIN ERROR
OUTPUT CURRENT SETTLING TIME
Gain error or full-scale error is a measure of thE!
difference between an ideal DAC's and the actual
device output.
For the Si7541, ideal full-scale
output is -(4095/4096). (VREF).
Gain error is
adjustable to zero using external trims as shown in
Figures 5 and 6.
This is the time required for the output current of
the DAC to settle to within 1/2 LSB into 100 .n, and
is specified for a zero to full scale digital input
change.
OUTPUT LEAKAGE CURRENT
This is the current that appears at OUT1 with the
DAC loaded to all Os or at OUT2 with the DAC
loaded to all 1s.
MULTIPLYING FEEDTHROUGH ERROR
This is the AC error due to capacitive feedthrough
from \/ftEF to OUT1 with DAC loaded to all O's.
PROPAGATION DELAY
This is a measure of the internal circuit delay from
the time a digital input changes to the point when
the analog output at OUT1 reaches 90% of its final
value.
DIGITAL TO ANALOG GLITCH IMPULSE
This is a measure of the area of the impulse
injected to the analog outputs when the digital
inputs change state. It is usually specified as the
area of the impulse in nV-secs. It is measured with
VREF GND and an LH0032 as the output op
amp, and phase compensation capacitor 0 pF.
=
=
ABSOLUTE MAXIMUM RATINGS
Voo to GND .................................. 17 V
VREF to GND
25 V
VRFB to GND
25 V
Digital Input Voltage to GND ............. -0.3 V to Voo
VOUT1 ,VOUT2 to GND ....•.••....•... -0.3 V to Voo
Storage Temperature (0, Q, E Suffix) ..... -65 to 150°C
(N, P Suffix) ....... -65 to 125°C
Operating Temperature (S, T Suffix) .....• -55 to 125°C
(A, B Suffix) ...••.• -40 to 85°C
(J, K Suffix) ••...•...• 0 to 70°C
Power Dissipation (Package)·
N, P Suffixes •• ............................ 470 mW
D, E, Q Suffixes ••• ....•..•.....•.......••• 900 mW
All leads welded or soldered to PC board.
•• Derate 6.5 mW/oC above 25°C
••• Derate 12 mW/oC above 75°C
6-59
..
Si7541
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
~nless Otherwise Specified:
Vee = +15 V, V REF = +10 V
VOUTl =VOUT2= OV
SYMBOL
Output Ampllfler: OP-07
LIMITS
1=25°C
2=125,85,70·C
3=-55,-40,O·C
TEMP
TYpd
B, K, T
GRADE
MINb MAXI
A,J,S
GRADE
MIN b MAXt UNIT
ACCURACY
Resolution
N
1,2,3
12
1,2,3
-1/2
112
-1
1
1,2,3
-112
1/2
-1
1
-12.5
-16.7
12.5
16.7
-12.5
-16.7
12.5
16.7
-5
5
-5
5
-5
5
-5
5
10
10
200
A: -10
J: -10
S: -200
10
10
200
5
-5
5
A: -10
-10
S: -200
10
10
200
Relative Accuracy
(Integral Non-Linearity)
INL
Differential Nonlinearity
DNL
Gain Error
GFSE
Measured Using Internal RFB
1
2,3
TCG FS
.6. Gain 1.6. Temperature
1,2,3
(1LSB = 0.024% of Full Scale)
12
LSB
Gain Temp CoefflclentC
2
1
IOUTl
All Digital
Inputs = 0 V
B: -10
K: -10
T: -200
2,3
Output Leakage Current
VREF= ±10 V
IOUT2
All Digital
Inputs = Vee
-5
1
B: -10
K: -10
T: -200
2,3
10
10
200
nA
,
REFERENCE
Reference Input
Resistance
(Pin 17 to GND)
J:
ppm/·C
RREF
1,2,3
Input HIGH Voltage
V IH
1,2,3
Input LOW Voltage
VIL
1,2,3
Input Current
liN
1,2,3
Input CapacltanceC
CIN
VIN=OV
PSRR
.6.Galn 1.6. Vee • .6. Vee = ±5%
10
7
18
7
18
k.o.
INPUT
2.4
2.4
V
0.8
-1
1
0.8
-1
8
1
.I1A
8
pF
SUPPLY
Power Supply ReJection
Veil. RangeS
6-60
1
2,3
-0.01
-0.02
0.01
0.02
-0.01
-0.02
1,2,3
5
18
5
0.01
0.02 %per%
16
V
Si7541
trY" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
~nless Otherwise Specified:
Voo = +15 V, VREF = +10 V
VOUT1 = VOUT2 = OV
SYMBOL
Output Amplifier: OP-07
LIMITS
1=25·C
2=125,85,70·C
3=-55,-40,O·C
TEMP
TYpd
B, K, T
GRADE
MINb MA>f
A,J,S
GRADE
MIN b MAXt UNIT
SUPPl.V (Cont'd)
All Digital Inputs V1L or V 1H
1,2,3
2
2
mA
All Digital Inputs 0 V orVoo
1
2,3
100
500
100
500
J.LA
tpo
From 50% of Digital Input to
90% of Final Analog Output
OUTl load = 100!!.
C EXT = 13 pF
Digital Inputs = 0 V toVoo
orVoo to OV
1
100
ns
Dlgltal-to-Analog Glitch
Impulse
Is
Output Amplifier: LH0032
V REF = 0 V, C F = 0 pF
Digital Inputs = 0 V toVoo
orVoo to OV
1
1000
nV-s
MUltlPI(,ng Feedthrou~h
Error VREFtO OUTl
MFER
V REF = 20 Vp-p , Sinewave
@ 10 kHz
1
1
mV
p-p
ts
To 0.01% of Full Scale Range
OUT1 load = 100!!.
C EXT = 13 pF
Digital Inputs = 0 V toVoo
orVoo to OV
1
0.6
J.LS
Digital Inputs = V1H
V1L
1,2,3
Supply Current
100
DYNAMIC
Propagation Delay
Output Current Settling
Time
C OUT1
Output Capacltance c
C OUT2
200
70
200
70
70
200
70
200
pF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Accuracy Is not guaranteed over this range.
6-61
Si7541
~
~
Siliconix
incorporated
DIE TOPOGRAPHY
Pad Function
No.
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
11
18
10
I
78 mils
8
2
!
Out 1
Out 2
GND
Bit 1 (MSB) ,
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12 (LSB)
V DO (substrate)
V REF
RFB
CSAK-IB
48 PMOS Transistors
68 NMOS Transistors
12 NPN Transistors
7 Polysilicon Resistors
12 400 N+ Resistors
10 10 kn Thin Film Resistors
13 20 kn Thin Film Resistors
CAUTION
ESD (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are diode protected;
however, permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
DETAILED DESCRIPTION
The Si7541 is a 12-bit multiplying Digital-to-Analog
Converter consisting of a highly stable thin film R-2R
ladder network and twelve single-pole double-throw
current steering NMOS analog switches on a
monolithic chip. The binarily weighted CMOS level
shifters provide low power TTL/CMOS compatible'
operation. An external voltage or current reference
and an operational amplifier are all that is required
for most applications.
The binary weighted currents are switched between
the OUT1 and OUT2 bus lines, thus maintaining a
constant current in each leg of the ladder
regardless of switch states.
The input resistance at VREF (Figure 1) is always
equal to the value "RREF" and is the R-2R ladder
characteristic resistance. Since RREF at the VREF
pin is constant, the reference terminal can be
6-62
driven by a reference voltage or a reference
current, be it positive, negative or AC. If a current
source is used, a low TC external feedback.resistor
RFB is recommended to define the scale factor.
VREF
10 kA
10 kA
---1--+---0 OUT2
---'-+...,---() OUT1
I
b
BIT 1
(MSB)
BIT 2
Figure 1.
BIT 3
BIT 12
(LSB)
RFEEDBACK
= 10 kA
SI7541 Functional Diagram
(All Inputs HIGH)
Si7541
Ir'Y' Siliconix
~
incorporated
DETAILED DESCRIPTION
Figure 2 illustrates the typical NMOS SPOT switch
with its associated CMOS level shifter/driver.
v+
o----~----..----,
DTLITTL
CMOS INPUT
POLY
RESISTOR
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for all digital
inputs LOW. All reference current is switched to
OUT2. The current sources I LEAKAGE are
composed of surface and junction leakages to the
substrate. The 1/4096 current source represents
the constant 1 LSB current drain through the ladder
termination resistor. The output capacitance on
OUT2 (with all its switches ON) is 200 pF, whereas
on OUT1 it is only 70 pF.
The output capacitances are dependent upon the
digital input code and vary between the LOW and
HIGH values.
Analysis of the circuit for all digital inputs HIGH, as
shown in Figure 4 is similar to Figure 3; however the
" ON" switches are now on OUT1, hence the 200 pF
at that terminal.
Figure 2. Simplified Schematic
Single SPOT Switch
....--_ _ORFEEDBACK
R
ILEAKAGE
IR~
= 10
I
70 pF
I
200 pF
kA
....--_ _R.QFEEDBACK
IR~
R=10kA
R = 10 kA
IOUTl
loun
R= 10 kA
ILEAKAGE
Figure 3.
SI7541 Equivalent Circuit
(All Inputs LOW)
t~rl-LE-A-KA-G-E-~~-7-0-PF-~~U~
Figure 4. SI7541 Equivalent Circuit
(All Inputs HIGH)
APPLICATIONS
APPLICATIONS HINTS
Static linearity of the Si7541 depends upon the
potential of OUT1 and OUT2 (pins 1 and 2) being
exactly equal to GNO (pin 3). In most applications
the DAC is connected to an external output op amp
with its non-inverting input tied to ground, which
converts its current output into a voltage output
signal. The op amp selected should have a low
input bias current (typically less than 75 nA) and
low drift over the operating temperature range. The
amplifier's input offset voltage should be nulled to
less than 10% of 1 LSB (typically less than
±200 J.lV) . The non-inverting input should be
connected directly to GNO without the usual input
bias current compensation resistor. This resistor
can cause variable offsets which would create
6-63
Si7541
..... Siliconix
incorporated
~
APPLICATIONS (Cont'd)
errors. Ground loops should be avoided by taking
aJi pins going to GND to a common point.
The VDD power supply should have a low noise level
and not have transients greater than +17 V.
Unused digital inputs must be grounded or taken to
VDD. It is also recommended that aJi digital inputs
be taken to ground via a high value (1 Mil) resistor
to prevent the accumulation of static charges
whenever the PC board is not connected to the
system.
OUTPUT OFFSET: CMOS DACs exhibit a code
dependent output resistance which can cause a
code dependent error voltage at the output of the
amplifier. The maximum value of this error is
0.67Vos, where Vos is the amplifier input offset
voltage.
To maintain monotonicity it is recommended that
Vos be no greater than (25 x10- 6 ) (VREF) over the
operating temperature range. It is also important
that Vos be nulled, either by using the op amp's
nulling pins or an external network.
DIGITAL GLITCHES: One cause of glitches is
capacitive coupling from the digital lines to the
OUT1 and OUT2 terminals. This can be minimized
by guarding the analog pins of the Si7541 (pins 1,
2, 17, 18) from the digital input pins by a ground
track run between pins 2 and 3 and between pins
16 and 17. Note that the analog pins are at one end
of the package separated from the digital inputs by
VDD and GND to aid guarding.
TEMPERATURE COEFFICIENTS: The Gain temperature coefficient of the Si7541 has a maximum value
of 5 ppm/oC and a typical of 2 ppm/oC. This
corresponds to worst case gain shifts of 2 LSBs and
0.8 LSBs respectively over a 100°C temperature
range. When trim resistors R1 and R2 are required
to adjust full scale range, low temperature
coefficient (approximately 50 ppm/oC) resistors or
trim-pots should be selected.
OUTPUT AMPLIFIER: For low speed applications the
AC specifications of the op amp are not critical. In
high-speed applications, however, slew rate,
settling time, open-loop gain, gain/phase margin
specifications of the amplifier shouid be selected
for the desired performance. As mentioned before,
the usual bias current compensation resistor at the
inverting input of the op amp should not be used.
6-64
Instead, the amplifier should have a low input bias
current over the operating temperature range.
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 5 shows the circuit configuration required for
unipolar binary (2-quadrant multiplication) operation. With a DC voltage or current-reference
(positive or negative) applied at pin 17, the circuit
is a unipolar Digital-to-Analog converter. With an AC
reference this
circuit
provides
2-quadrant
multiplication (digitally controlled attenuation). The
reference input voltage can range between -20 V
and +20 V due to the ability of VREF to exceed VDD.
Rl
'r-:!:---:::"1
R FEEDBACK
~lJsk)·O--,-~
DIGITAL
INPUT
Brr 12:o---'--I~
(LSB)
-f_...
.....
Figure 5. Unipolar Binary Operation
(2 - Quadrant)
Table 1 shows the digital code input analog voltage
correspondence. R1 provides full-scale trimming
(load the DAC with 1111 1111 1111 , adjust R1 for
VOUT = -VREF (4095/4096). Full-scale can also be
adjusted by omitting R1 and R2 and trimming the
magnitude of VREF.
TABLE 1
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT (VOUT)
1111 1111 1111
-(4095/4096) VIN
1000 0000 0000
-(2048/4096) VIN
0000 0000 0001
-(114096) VIN
0000 0000 0000
OV
Unipolar Binary Code Table for Circuit
of Figure 5
~
~
Si7541
Siliconix
incorporated
APPLICATIONS (Cont'd)
TABLE
BIPOLAR BINARY OPERATION
(4-QUADRANT MULTIPLICATION)
DIGITAL INPUT
MSB
LSB
Figure 6 illustrates the recommended circuit for
bipolar operation. With a DC reference of either
polarity the circuit provides offset binary operation.
With an AC reference, the eleven LSBs provide
digitally controlled attenuation of the reference
input while the MSB provides polarity control.
2
ANALOG OUTPUT
(VOUT)
1111 1111 1111
+(2047/2048) VIN
1000 0000 0001
+(1/2048) VIN
1000 0000 0000
OV
0111 1111 1111
-(1/2048)V
0000 0000 0000
-VIN
Bipolar Binary Code Table for Circuit
of Figure 6
SINGLE SUPPLY OPERATION
DIGITAL
GROUND
ANALOG
GROUND
The circuit of Figure 7 shows the Si7541 connected
in a voltage switching configuration. The reference
voltage is applied to oun and OUT2 is connected
to ground. The DAC output is available at pin 17
(VREF pin) and has a constant output impedance
equal to RREF. The internal feedback resistor (pin
18) is not used. For better linearity in the voltage
switching mode. the Si7240 should be specified.
Figure 6. Bipolar Operation
(4 - Quadrant Multiplication)
VDD= +15 V
16
171---1
With the DAC loaded to 10000000 DODO, adjust R1
for VOUT = 0 V (alternatively, R1 and R2 can be
omitted and the ratio of R3 to R4 can be adjusted
for VOUT = 0 V). Full-scale trimming can be
performed by adjusting VREF or by adjusting the
value of RS.
VREF
<2.5 V
R2
R1
BITS 1 - 12
SYSTEM
_ _ _ _~----~____~____G~ROUND
As in unipolar operation the amplifiers must be
chosen for low input offset voltage and low input
bias current. The input offset voltage of both
amplifiers should be adjusted to less than 0.1 mV
and be better than 0.5 mV over the operating
temperature range of interest. R3, R4 and RS must
be matched. Mismatches of R5 to R4 and (2 X R3)
cause full-scale error. Mismatch of (2 X R3) to R4
causes both offset and full-scale errors.
Table 2 illustrates the relationship between the
offset binary digital codes and the analog output
voltage.
C1 = 10Jl,F ELECTROLYTIC
C2 = 0.1 Jl,F CERAMIC
Figure 7.
R1
II R2 = 10 k.n.
Single Supply Operation
Using Voltage Switching
The reference voltage must always be positive in
the voltage switching mode. If pin 1 goes below
-0.3 V an internal diode will be turned on. If not
limited a large current will flow and may cause
device damage. Since the Si7541 is protected for
SCR latch-up. removing the abnormally negative
reference voltage will restore normal operation
6-65
Si7541
tnr'" Siliconix
,,6;11 incorporated
APPLICATIONS (Cont'd)
provided the maximum current handling capacity
(20 rnA) has not been exceeded.
loading on the reference voltage source is code
dependent and the response time of the circuit is
often determined by the ability of the reference
voltage source to handle the changing load
conditions. For this reason bypassing of the
reference source is required. To maintain linearity
the reference voltage at pin 1 should remain within
2.5 V of GND, for aVoo = 15 V. IfVoo is reduced or
the reference voltage increased, the DAC's
linearity and differential nonlinearity will be
degraded.
PIN DESCRIPTION
PIN NUMBER
1
2
3
4
5
6
7
8
9
DESCRIPTION
PIN NUMBER
Current OUTPUT 1
Current OUTPUT 2
Digital Ground
Digital Input (Bit 1) (MSB)
Digital Input (Bit 2)
Digital Input (Bit 3)
Digital Input (Sit 4)
Digital Input (Bit 5)
Digital Input (Bit 6)
10
11
12
DESCRIPTION
Digital Input (Bit 7)
Digital Input (Bit 8)
Digital Input (Bit 9)
Digital Input (Bit 10)
Digital Input (Bit 11)
Digital Input (Bit 12) (lSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
13
14
15
16
17
18
BURN-IN CIRCUITS
+15 V
.,b.
,
I.
3112111
10V
~Il
1 k.o.
4
+16 V
~a
7f---<
at----<
~f---<
~8
4t----<
9 1 Ulll 2111
1
6-66
Si7541A
...... Siliconix
incorporated
~
CMOS 12-Bit
Multiplying DAC
FEATURES
BENEFITS
APPLICATIONS
• 12-Bit Linearity
(INL < 1/2 LSB)
• Improves System
Absolute Accuracy
• ATE Systems
• Four Quadrant
Multiplication
• Allows Bipolar
Reference Inputs
• Gain Error < 1 LSB
• Reduces Trims
• Fast Settling (300 ns typ.)
• Increases Data Throughput
• Monotonic (DNL < 1/2 LSB)
• No Seek Errors in Servos
• TIL/CMOS Compatible
• Simplifies Logic
Interfacing
• Digitally Controlled
Gain/ Attenuation
• Function Generators
• Closed-Loop Servo
Systems
• Hybrid/Custom
A/D Converters
DESCRIPTION
Highly-stable thin film resistors are included on the
chip for low drift over temperature and time. These
are laser-trimmed to achieve 1/2 LSB integral
nonlinearity (INL) and reduced gain error. The
epitaxial layer prevents latch up.
The Si7541 A is a 12-Bit multiplying digital-to-analog
converter which features true 12-bit integral
linearity and monotonicity, low gain error (1 LSB) ,
fast settling time (300 ns typ.) , TIL-compatible
logic inputs, and low gain drift of 5 ppm/DC. The
low gain error reduces trim requirements in the
system, and the 1/2 LSB differential nonlinearity
specification
guarantees
monotonicity,
thus
eliminating instability in closed-loop systems.
The Si7541A is available in 18-pin PDIP, CerDIP and
side braze DIP packages for commercial, J, K suffix
(0 to 70°C), industrial, A, B suffix (-40 to 85°C)
and military, S, T suffix (-55 to 125°C) operation,
respectively. For surface mount applications, the
Si7541A is available in the PLCC-20 (0 to 70°C) and
the hermetic LCC-20 (-55 to 125°C) . Each
package and temperature range is available in two
linearity grades.
Multiplying applications for the Si7541 A include
digitally controlled amplifiers, attenuators, filters
and power supplies. The fast settling time makes
the Si7541 A ideal for high speed data conversion
and hybrid or custom AID converters.
The Si7541A is built using the Siliconix advanced
5-micron CMOS process known as PolyMOS 1M ,
allowing fast settling time and low glitch impulse.
For more information on the Si7541 A, please refer
to Siliconix Application Note AN87-3.
PIN CONFIGURATION & ORDERING INFORMATION
PLCC Package
Dual-ln-L1ne Package
OUT 1 NCRFB
OUT 2 311 211111201119 VREF
oun
GND
GND 4
BIT 1 (MSB)
~
~
~
~
BIT 2 ~
Top View
BIT 3 ~
BIT 4 8
~4
VDD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 5 9I1HlI1111121113 BIT 8
BIT 6 NO BIT 7
INL
Tmln - Tmax
(LSB)
:!: 1
:!: 1/2
RFB
v REF
V DD
OUT2
,/
GAIN
ERROR
Ta=25°C
(LSB)
:!: 6
+1
BIT 5
GND
BIT 12 (LSB) BIT 1 (MSB)
BIT 11
BIT 2
BIT 10
BIT 3
BIT 9
BIT 4
BIT 8
BIT 6
BIT 7
BIT 1
BIT 2
BIT 3
BIT 4
VDD
BIT 12 (LSBI
BIT 11
BIT 10
BIT 9
BIT 5 BIT 6 NO BIT 7
BIT 8
TEMPERATURE RANGE AND PACKAGE
PLCC
o to 700C
PDIP
o to 70°C
CerDIP
-40 to 85"C
SIDE BRAZE
-55 to 125°C
LCC
-55 to 125°C
SI7541AJP
SI7541AJN
SI7541AAQ
SI7541ASD
SI7541ASE
SI7541AKP
SI7541AKN
SI7541ABQ
SI7541ATD"
SI7541 ATE
6-67
Si7541A
..... Siliconix
incorporated
~
FUNCTION BLOCK DIAGRAM
10 k.O.
10 k.O.
OUT2
OUT1
I
I
6
6
BIT 1
(MSB)
BIT 2
RFEEDBACK
BIT 3
BIT 12
(LSB)
DEFINITION OF TERMS
MULTIPLYING DAC
Digital-to-Analog Converters (DACs) are devices
that convert digital data into analog values. A
multiplying DAC is a device capable of handling
variable reference sources. Its output is the product
of two variables: the number represented by the
digital input code and the analog reference voltage.
RESOLUTION
Resolution indicates the number of digital input bits.
A 12-bit DAC resolves the full-scale range (FSR)
into 212 4096 states.
=
LSB
Value of the Least Significant Bit. For example, a
12-bit unipolar converter has a 1 LSB step value
equal to 'lREF/212 or 'lREF/4096 (Volts).
RELATIVE ACCURACY
Relative accuracy or end-point nonlinearity is a
measure of the maximum deviation from a straight
line passing through the end points of the DAC
transfer function. It is measured after adjusting for
zero and full scale errors and is expressed in % of
full scale range or (sub)multiples of 1 LSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB max over the
operating temperature range ensures monotonicity.
GAIN ERROR
Gain error or full-scale error is a measure of the
difference between an ideal DAC's and the actual
6-68
device output. For the Si7541A, ideal full-scale
output is -(4095/4096). ('lREF). Gain error is
adjustable to zero using external trims as shown in
Figures 5 and 6.
OUTPUT LEAKAGE CURRENT
This is the current that appears at OUT1 with the
DAC loaded to all Os or at OUT2 with the DAC
loaded to all 1s.
MULTIPLYING FEEDTHROUGH ERROR
This is the AC error due to capacitive feedthrough
fl"Om 'lREF to OUT1 with DAC loaded to all O's.
OUTPUT CURRENT SETTLING TIME
This is the time required for the output current of
the DAC to settle to within 1/2 LSB into 100 n, and
is specified for a zero to full scale digital input
change.
PROPAGATION DELAY
This is a measure of the internal circuit delay from
the time a digital input changes to the pOint when
the analog output at OUT1 reaches 90% of its final
value.
DIGITAL TO ANALOG GLITCH IMPULSE
This is a measure of the area of the impulse
injected to the analog outputs when the digital
inputs change state. It is usually specified as the
area of the impulse in nV-secs. It is measured with
'lREF = GND and an LH0032 as the output op amp,
and phase compensation capacitor 0 pF.
=
Si7541A
.... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
Voo to GND •..................•.............. 17 V
V REF to GND
25 V
VRFB to GND
25 V
Digital Input Voltage to GND .•........... -0.3 V to Voo
VOUT' ,VOUT2 to GND .......•....•... -0.3 V to Voo
Storage Temperature (0, Q, E Suffix) ..... -65 to 150·0
(N, P Suffix) ....•.. -65 to 125·0
Operating Temperature (S, T Suffix) ..••.. -55 to 125·0
(A, B Suffix) ..•••.. -40 to 85·0
(J, K Suffix) .••.••.... 0 to 70·0
Power Dissipation (Package)·
N, P Suffixes·· ............................ 470 mW
0, E, Q Suffixes ••• .........•.•.•.....••... 900 mW
All leads welded or soldered to PO board.
Derate 6.5 mW/·O above 25·0
••• Derate 12 mW/·O above 75·0
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
~nless Otherwise Specified:
Voo,,+15V, V REF ,,+10V
Voun "VOUT2 " OV
SYMBOL
Output Amplifier: OP-07
LIMITS
1,,25·C
2,,125,85,70·C
3,,-55,-40,O·C
TEMP
TYpd
B, K, T
GRADE
MIN b MAXb
A,J,S
GRADE
MIN b MAXb UNIT
ACCURACY
Resolution
N
1,2,3
12
1,2,3
-1/2
112
-1
1
1,2,3
-1/2
112
-1
1
-1
-3
1
3
-6
-8
6
8
-5
5
-5
5
-5
5
-5
5
10
10
200
A: -10
J: -10
10
10
200
Relative Accuracy
(Integral Non-Linearity)
INL
Differential Nonlinearity
DNL
Gain Error
GFSE
Measured Using Internal R FB
1
2,3
TOG FS
~ Gain 1~ Temperature
1,2,3
(1LSB " 0.024% of Full Scale)
12
LSB
Gain Temp Ooefflclent C
2
1
All Digital
Inputs" 0 V
lOUT'
-10
-10
T -200
B
K
2,3
Output Leakage Ourrent
VREF" ±10 V
IOUT2
All Digital
Inputs" Voo
1
-5
B -10
K -10
T -200
2,3
5
S: -200
-5
A: -10
ppm/·O
nA
5
10
10
200
J: -10
S: -200
10
10
200
18
7
18
REFERENCE
Reference Input
Resistance
(Pin 17 to GND)
RREF
1,2,3
Input HIGH Voltage
V 1H
1,2,3
Input LOW Voltage
V1L
1,2,3
10
7
k.Cl
INPUT
2.4
2.4
V
0.8
0.8
6-69
Siliconix
incorporated
Si7541A
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V DD = +15 V, V REF = +10 V
V OUT1 = V OUT2 = OV
SYMBOL
Output Amplifier: OP-07
PARAMETER
LIMITS
1_25°C
2=125,85,70°C
3=-55,-40,O°C
TEMP
TYpd
B, K, T
GRADE
MIN b MAX
A,J, S
GRADE
MIN b MAXt
UNIT
INPUT (Coot'd)
-1
1,2,3
Input Current
liN
Input CapacltanceC
CIN
V IN = 0 V
PSRR
ll.Galn Ill. V DD , ll. VDD = ±5%
1
-1
8
1
JlA
8
pF
SUPPLY
Power Supply Rejection
VDD Range e
1
2,3
-0.01
-0.02
0.01
0.02
-0.01
-0.02
0.01
0.02
%per%
1,2,3
5
16
5
16
V
All Digital Inputs V IL or V IH
1,2,3
2
2
mA
All Digital Inputs 0 V orVDD
1
2,3
100
500
100
500
JlA
tpD
From 50% of Digital Input to
90% of Final Analog Output
OUT1 load = 100.0.
C EXT =13pF
Digital Inputs = 0 V toVDD
orV DD to OV
1
100
ns
Dlgltal-to-Analog GlItch
Impulse
Is
Output Amplifier: LH0032
V REF = 0 V, C F = 0 pF
Digital Inputs = 0 V toV DD
orVDD to OV
1
1000
nV-s
Multiplying Feedthrough
Error ( V REF to OUT1)
MFER
V REF = 20 V p _p , Sinewave
@ 10 kHz
1
1
mV
p-p
ts
To 0.01 % of Full Scale Range
OUT1 load = 100.0.
CEXT= 13 pF
Digital Inputs = 0 V toVDD
orV DD to OV
1
0.3
Jls
IDD
Supply Current
DYNAMIC
Propagation Delay
Output Current Settling
Time
"OUT1
Output Capacitance
C
C OUT2
Digital Inputs = V IH
V IL
200
70
200
70
70
200
70
200
1,2,3
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Accuracy Is not guaranteed over this range.
6-70
pF
Si7541A
..,.. Siliconix
,.1;11 incorporated
DIE TOPOGRAPHY
Pad Function
No.
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
11
r
18
10
9 78 mils
3
2
1
Out 1
Out 2
GND
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12 (LSB)
V oo(substrate)
VREF
RFB
CSAK-IB
48 PMOS Transistors
68 NMOS Transistors
12 NPN Transistors
7 Polyslllcon Resistors
12 400 N+ Resistors
10 10 kn Thin Film Resistors
13 20 k!l Thin Film Resistors
CAUTION
ESDS (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are diode protected;
however, permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
DETAILED DESCRIPTION
The Si7541 A is a 12-bit multiplying Digital-to-Analog
Converter consisting of a highly stable ',hin film R-2R
ladder network and twelve single-pole double-throw
current steering NMOS analog switches on a
monolithic chip. The binarily weighted CMOS level
shifters provide low power TTL/CMOS compatible
operation. An external voltage or current reference
and an operational amplifier are all that is required
for most applications.
The binary weighted currents are switched between
the OUTl and OUT2 bus lines, thus maintaining a
constant current in each leg of the ladder
regardless of switch states.
driven by a reference voltage or a reference
current, be it positive, negative or AC. If a current
source is used, a low TC external feedback resistor
RFB is recommended to define the scale factor.
VREF
10
10
k.Cl.
10 k.Cl.
--1-+.....- - 0 OUT2
----l....-;.....,---O oun
I
o
BIT
The input resistance at VREF (Figure 1) is always
equal to the value "RREF" and is the R-2R ladder
characteristic resistance. Since RREF at the VREF
pin is constant, the reference terminal can be
k.Cl.
U-~"I'~~"I'\r-~----JV\r
I
o
BIT 2
(MSE.)
Figure 1.
RFEEOBACK
BIT 3
BIT 12
(LSB)
= 10 k.Cl.
SI7541A Functional Diagram
(All Inputs HIGH)
6-71
..,. Siliconix
incorporated
Si7541A
~
DETAILED DESCRIPTION
Figure 2 illustrates the typical NMOS SPDT switch
with its associated CMOS level shifter/driver.
v+
O----~----t'----,
DTLITTL
CMOS INPUT
POLY
RESISTOR
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for all digital
inputs LOW. All reference current is switched to
OUT2. The current sources I LEAKAGE are
composed of surface and junction leakages to the
substrate. The 1/4096 current source represents
the constant 1 LSB current drain through the ladder
termination resistor. The output capacitance on
OUT2 (with all its switches ON) is 200 pF, whereas
on oun it is only 70 pF.
The output capacitances are dependent upon the
digital input code and vary between the LOW and
HIGH values.
Analysis of the circuit for all digital inputs HIGH, as
shown in Figure 4 is similar to Figure 3; however the
.. ON" switches are now on OUTl , hence the 200 pF
at that terminal.
FIgure 2. SImplified SchematIc
SIngle SPOT SwItch
.--_ _ROFEEDBACK
.--_ _OR FEEDBACK
R
= 10 k.n.
R=10~
IOUT1
IR~ R = 10 k.n.
IOUT2
VREF
+
-
IOUT1
-
FIgure 3. SI7541 A EquIvalent CIrcuIt
(All Inputs LOW)
1
t~EAKAGE
,....---::L...---~O
~a
70 pF
IOUT2
FIgure 4. SI7541A EquIvalent CIrcuIt
(All Inputs HIGH)
APPLICATIONS
APPLICATIONS HINTS
Static linearity of the Si7541 A depends upon the
potential of oun and OUT2 (pins 1 and 2) being
exactly equal to GND (pin 3). In most applications
the DAC is connected to an external output op amp
with its non-inverting input tied to ground, which
converts its current output into a voltage output
signal. The op amp selected should have a low
6-72
input bias current (typically less than 75 nA) and
low drift over the operating temperature range. The
amplifier's input offset voltage should be nulled to
less than 10% of 1 LSB (typically less than
±200 J.l.V) . The non-inverting input should be
connected directly to GND without the usual input
bias current compensation resistor. This resistor
can cause variable offsets which would create
Si7541A
IIY" Siliconix
~
incorporated
APPLICATIONS (Cont'd)
errors. Ground loops should be avoided by taking
all pins going to GND to a common point.
TheVDD power supply should have a low noise level
and not have transients greater than +17 V.
Unused digital inputs must be grounded or taken to
VDD. It is also recommended that all digital inputs
be taken to ground via a high value (1 Mil) resistor
to prevent the accumulation of static charges
whenever the PC board is not connected to the
system.
OUTPUT OFFSET: CMOS DACs exhibit a code
dependent output resistance which can cause a
code dependent error voltage at the output of the
amplifier. The maximum value of this error is
0.67Vos, where Vos is the amplifier input offset
voltage.
To maintain monotonicity it is recommended that
Vos be no greater than (25 x10- 6 ) (VREF) over the
operating temperature range. It is also important
that Vos be nulled, either by using the op amp's
nulling pins or an external network.
DIGITAL GLITCHES: One cause of glitches is
capacitive coupling from the digital lines to the
OUT1 and OUT2 terminals. This can be minimized
by guarding the analog pins of the Si7541 A (pins 1,
2, 17, 18) from the digital input pins by a ground
track run between pins 2 and 3 and between pins
16 and 17. Note that the analog pins are at one end
of the package separated from the digital inputs by
VDD and GND to aid guarding.
TEMPERATURE COEFFICIENTS: The Gain temperature coefficient of the Si7541 A has a maximum
value of 5 ppm/oC an'd a typical of 2 ppm/oC This
corresponds to worst case gain shifts of 2 LSBs and
0.8 LSBs respectively over a 100°C temperature
range. When trim resistors R1 and R2 are required
to adjust full scale range, low temperature
coefficient (approximately 50 ppm/°C) resistors or
trim-pots should be selected.
OUTPUT AMPLIFIER: For low speed applications the
AC specifications of the op amp are not critical. In
high-speed applications, however, slew rate,
settling time, open-loop gain, gain/phase margin
specifications of the amplifier should be selected
for the desired performance. As mentioned before,
the usual bias current compensation resistor at the
inverting input of the op amp should not be used.
Instead, the amplifier should have a low input bias
current over the operating temperature range.
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 5 shows the circuit configuration required for
unipolar binary (2-quadrant multiplication) operation. With a DC voltage or current-reference
(positive or negative) applied at pin 17, the circuit
is a unipolar Digital-to-Analog converter. With an AC
reference
this
circuit
provides
2-quadrant
multiplication (digitally controlled attenuation). The
reference input voltage can range between -20 V
and +20 V due to the ability of VREF to exceed VDD.
RFEEDBACK
17
4
BIT 1
(MSB)
DIGITAL
INPUT
R2
SI7541A
1
47.n.
IOUTl
2
BIT 12
(LSB)
-
-
Figure 5. Unipolar Binary Operation
(2 - Quadrant)
Table 1 shows the digital code input analog voltage
correspondence. R1 provides full-scale trimming
(load the DAC with 1111 1111 1111 , adjust R1 for
VOUT = -VREF(4095/4096). Full-scale can also be
adjusted by omitting R1 and R2 and trimming the
magnitude of VREF.
TABLE 1
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT (VOUT)
1111 1111 1111
-(4095/4096) VIN
1000 0000 0000
-(2048/4096) VIN
0000 0000 0001
-(114096) VIN
0000 0000 0000
OV
Unipolar Binary Code Table for Circuit
of Figure 5
6-73
Si7541A
W7" Siliconix
~
incorporated
APPLICATIONS (Cont'd)
BIPOLAR BINARY OPERATION
(4-QUADRANT MULTIPLICATION)
TABLE 2
DIGITAL INPUT
MSB
LSB
Figure 6 illustrates the recommended circuit for
bipolar operation. With a DC reference of either
polarity the circuit provides offset binary operation.
With an AC reference, the eleven LSBs provide
digitally controlled attenuation of the reference
input while the MSB provides polarity control.
ANALOG OUTPUT (VOLrr )
1111 1111 1111
+(2047/2048)
VIN
+(1/2048) VIN
1000 0000 0001
OV
1000 0000 0000
0111 1111 1111
-(1/2048)V
0000 0000 0000
-VIN
Bipolar Binary Code Table for Circuit
of Figure 6
SINGLE SUPPLY OPERATION
DIGrrAL
GROUND
ANALOG
GROUND
The circuit of Figure 7 shows the Si7541A
connected in a voltage switching configuration. The
reference voltage is applied to OUT1 and OUT2 is
connected to ground. The DAC output is available
at pin 17 tvREF pin) and has a constant output
impedance equal to RREF. The internal feedback
resistor (pin 18) is not used. For better linearity in
the voltage switching mode, the Si7240 should be
specified.
Figure 6. Bipolar Operation
(4 - Quadrant Multiplication)
VDD= +15 V
16
171---1
With the DAC loaded to 1000 0000 0000, adjust R1
for VOUT = a v (alternatively, R1 and R2 can be
omitted and the ratio of R3 to R4 can be adjusted
for VOUT = a V) . Full-scale trimming can be
performed by adjusting VREF or by adjusting the
value of R5.
As in unipolar operation the amplifiers must be
chosen for low input offset voltage and low input
bias current. The input offset voltage of both
amplifiers should be adjusted to less than 0.1 mV
and be better than 0.5 mV over the operating
temperature range of interest. R3, R4 and R5 must
be matched. Mismatches of R5 to R4 and (2 X R3)
cause full-scale error. Mismatch of (2 X R3) to R4
causes both offset and full-scale errors.
Table 2 illustrates the relationship between the
offset binary digital codes and the analog output
voltage.
6-74
VREF
VOUT
<2.5 V
BITS 1 - 12
SYSTEM
_ _ _ _~----~--~_~G~ROUND
Cl
C2
= 10 p.F ELECTROLYTIC
= 0.1 p.F CERAMIC
Rl
1\ R2 = 10 k.n
Figure 7. Single Supply Operation
Using Voltage Switching
The reference voltage must always be positive in
the voltage switching mode. If pin 1 goes below
-0.3 V an internal diode will be turned on. If not
limited a large current will flow and may cause
device damage. Since the Si7541A is protected for
SCR latch-up, removing the abnormally negative
reference voltage will restore normal operation
Si7541A
..... Siliconix
incorporated
~
APPLICATIONS (Cont'd)
conditions. For this reason bypassing of the
reference source is required. To maintain linearity
the reference voltage at pin 1 should remain within
2.5 V of GND, for a Voo = 15 V. If Voo is reduced or
the reference voltage increased, the DAC's
linearity and differential nonlinearity will be
degraded.
provided the maximum current handling capacity
(20 mAl has not been exceeded.
Loading on the reference voltage source is code
dependent and the response time of the circuit is
often determined by the ability of the reference
voltage source to handle the changing load
PIN DESCRIPTION (DIP)
PIN NUMBER
1
2
3
4
5
6
7
8
9
DESCRIPTION
PIN NUMBER
Current OUTPUT 1
Current OUTPUT 2
Digital Ground
Digital Input (Bit 1) (MSB)
Digital Input (Bit 2)
Digital Input (Bit 3)
Digital Input (Bit 4)
Digital Input (Bit 5)
Digital Input (Bit 6)
DESCRIPTION
Digital Input (Bit 7)
Digital Input (Bit 8)
Digital Input (Bit 9)
Digital Input (Bit 10)
Digital Input (Bit 11)
Digital Input (Bit 12) (LSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
10
11
12
13
14
15
16
17
18
BURN-IN CIRCUITS
,1---+'--0 +10V
1 kfi
+15 V
10 V
.b
,
.
3112111 2
191
1 k.n
~5
8
+15 V
~6
~
~8
~4
9JL1 IJlllll 2111:31
1
6-75
Si7542
Microprocessor-Compatible 12-Bit
CMOS Multiplying DAC
. , . Siliconix
,,1;11 incorporated
FEATURES
BENEFITS
APPLICATIONS
• Double-Buffered 4-Bit
TTL-Compatible Latches
• Simplified Microprocessor
Interface
• 4 and 8-Bit Microprocessor
Controlled Systems
• True 12-Bit Linearity
(INL < 1/2 LSB)
• Improved System Accuracy
• ATE
• Instrumentation
• Reduced Calibration
Requirements
• Low Gain Drift:
(5 ppm/oC max)
• Digitally-Controlled
Attenuators
e Allows AC Attenuation
Without Biasing
• Full 4-quadrant
Multiplication
• Avionics
• Reduced Power Consumption
• Single +5 Volt
Supply Operation
DESCRIPTION
The Si7542 is a precision 12-bit CMOS multiplying
DAC designed for direct interface to 4- or 8-bit
microprocessors.
The Si7542 consists of three 4-bit data registers, a
12-bit DAC register, address decoding logic and a
12-bit CMOS multiplying DAC. Data is loaded into
the data registers in three 4-bit bytes, and
subsequently transferred to the 12-bit DAC register.
All data loading or data transfer operations are
identical to the WRITE cycle of a static RAM. A
Clear input allows the DAC register to be easily
reset to all zeros when powering up the device.
The Si7542 is manufactured using the Siliconix
PolyMOS™ process with thin film resistors, which
are laser trimmed for high accuracy. Multiplying
capability, 12-bit linearity, low power dissipation,
+5 V operation, small size and easy J.LP interface
make the Si7542 ideal for many instrumentation,
industrial control and avionics applications. An
epitaxial layer prevents latchup.
The Si7542 is available in the following packages
and temperature ranges: 16-pin plastic DIP and
PLCC-20 for commercial, J, K suffix (0 to 70°C)
operation, 16-pin CerDIP for industrial, A, B suffix
(-40 to 85°C) operation, 16-pin Side Braze and
LCC-20 for military, S, T suffix (-55 to 125°C)
operation.
PIN CONFIGURATION
PLce Package
Lce Package
Top View
Top View
Dual-In-Llne Package
o 0
V
U U
R R
'TTNFE
2 1 0 B F
Top View
T
2
3112111112al19
RFB
VREF
0
U
./
~ VOO
VOO
~ OLR
'OCR
~ NO
~ OGNO
OGNO
4 A1
9111a1111112111:31
gg~'f{~
6-76
V
R R
T N F E
1 0 B F
0
U
AGNO
03
~
VOO
OLR
NO
OGNO
01
A1
NO
O-N - A
o
g 0 'f{o
Preliminary
Si7542
W'fI" Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
VREF
DGND
v DD
(DIP PIN NUMBERS)
16
RFB
OUT 1
2
3
OUT 2
AGND
4-BIT DATA INPUT
ORDERING INFORMATION
INL
Tmln - Tmax
(LSB)
:!: 1
:!: 1/2
:!: 1/2
GAIN
ERROR
Ta" 25'C
(LSB)
:!: 12.3
:!: 12.3
:!: 1
TEMPERATURE RANGE AND PACKAGE
PLASTIC
o to 7rJ'C
PLCC-20
o to 70'C
CerDIP
-40 to 6SOC
SIDE BRAZE
-55 to 125'C
LCC-20
-55 to 125'C
SI7542JN
SI7542JP
SI7542AQ
SI7542SD
SI7542KN
SI7542KP
SI7542BQ
SI7542TD
SI7542TE
SI7542GKN
SI7542GKP
SI7542GBQ
SI7542GTD
SI7542GTE
SI7542SE
ABSOLUTE MAXIMUM RATINGS*
V DD to AGND ....•..................... -0.3 V. +17 V
(D. E Suffix) ..•...•.....•....•.•....... -55 to 125'C
V DD to DGND .......................... -0.3 V. +17 V
VREF to AGND ............................... ±25 V
V RFB to AGND .•.............••.•............. ±25 V
Digital Input Voltage to DGND ......... -0.3 V. +15.3 V
V OUT1 • V OUT2 to AGND ............... -0.3 V. +15.3 V
AGND to DGND
Dissipation (Package)"
Plastic DIP'" .............•...•.••...
Ceramic Side Braze···· .•.............
Plastic Leaded Chip Carrier • • . . . . . . . . . ..
LCC···· . . . . . . . . . . . . . . . . . . . . . . . • . . • •.
470
900
450
900
mW
mW
mW
mW
-0.3 V toVD D
DGND to AGND ....................... -0.3 V to V DD
Storage Temperature ................... -65 to 150'C
Operating Temperature:
(N. P Suffix) .............................. 0 to 70'C
(Q Suffix) ....•..•........•.............. -40 to 65'C
Preliminary
Power
16-Pln
16-Pln
20-Pln
20-Pln
Stress ratings only. Exposure to absolute max rating
conditions for extended periods may affect device
reliability.
All leads welded or soldered to PC Board.
Derate 6.5 mW/'C above 25·C.
Derate 12 mW/'C above 75·C.
6-77
Si7542
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Voo = +5 V, VREF = +10 V
VOUT1=VOUT2= 0 V
Output Amplifier: OP-07
LIMITS
1=25·C
ALL GRADES
2=125,85,70·C
EXCEPT AS
NOTED
3=-55,-40,0 ·C
TEMP
TYP d
MIN b MAX
UNIT
ACCURACY
Resolution
1,2,3
12
All Other Grades
1,2,3
-0.5
0.5
A, J, S Grades
1,2,3
-1
1
Monotonic to 12-Blts
1,2,3
-1
1
A, J, S Grades
1,2,3
-2
2
GB, GK, GT Grades
1
2,3
-1
-2
1
2
J, K Grades
1
2,3
-12.3
-13.5
12.3
13.5
A, B, S, T Grades
1
2,3
-12.3
-14.5
12.3
14.5
~ Gain I ~ Temperature
1,2,3
-5
5
ppm I
·C
~Galn I~ Voo
Voo=±5%
1
2,3
-0.005
-0.01
0.005
0.01
%
per
%
DAC Loaded with All Zeros: IOUT1
DAC Loaded with All Ones: IOUT2
1
2,3
-1
-200
1
200
J, K, GK Grades
1
2,3
-1
-10
1
10
N
Relative Accuracy
(Integral Non-Linearity)
INL
Differential Nonlinearity
Bits
(lLSB = 0.024%
of Full Scale)
DNL
GFSE
Gain Errore
Gain Temp CoefflclentD
TCGFS
Power Supply Rejection
PSRR
Output Leakage
Current
IOUT1,
IOUT2
2
LSB
nA
DYNAMIC.
Current Settling TimeD,
Multiplying Feedthrough
Error D, g
f
1,2,3
2
J.Ls
VREF = ±10 V
10kHz Sine Wave
1,2,3
2.5
mVp-p
DAC Loaded to All Zeros
1,2,3
70
DAC Loaded to All Ones
1,2,3
200
DAC Loaded to All Zeros
1,2,3
200
DAC Loaded to All Ones
1,2,3
70
ts
FT
C OUT1
Output Capacltance D
pF
COUT2
6-78
Preliminary
Si7542
.... Siliconix
,LII incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo = +5 V, VREF = +10 V
Voun=VouT2= 0 V
Output Amplifier: OP-07
LIMITS
1=25°C
2=125,85,70°C
3=-55,-40,O°C
TEMP
TYP
RREF
1,2,3
10
Logic HIGH Voltage
V IH
1,2,3
Logic LOW Voltage
V IL
1,2,3
Input Current
liN
VIN = 0 V orVoo
1,2,3
Input CapacltanceC
C IN
VIN=OV
1,2,3
SYMBOL
PARAMETER
ALL GRADES
EXCEPT AS
NOTED
d
MIN b MAXb
UNIT
REFERENCE
Reference Input Resistance
8
25
k.O.
LOGIC INPUTS
3
V
0.8
0.001
-1
1
'uA
8
pF
TIMING h
WRITE Pulse Width
tWR
1,2,3
120
220
Address to WRITE Hold Time
tAWH
1,2,3
50
65
Chip Select to WRITE Hold
Time
tCWH
1,2,3
50
100
CLEAR Pulse
tCLR
1,2,3
200
300
Chip Select to WRITE
Setup Time
tcws
1,2,3
60
130
Address Valid to
WRITE Setup Time
tAWS
1,2,3
60
160
Data Setup Time
tos
1,2,3
50
65
Data Hold Time
tOH
1,2,3
50
65
tcws
1,2,3
60
150
tAWS
1,2,3
120
240
Chip Select to WRITE
Setup Time
Address Valid to
WRITE Setup Time
See Timing Diagram
(Figure 7)
ns
Byte
Loading
DAC
Loading
SUPPLY
Supply Voltage
Voo
Supply Current
100
Preliminary
5 V ±5% for Specified Performance
Digital Inputs = VIH or V IL
1,2,3
1,2,3
4.5
16.5
V
2.5
mA
6-79
Si7542
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a (Cont'd.)
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. Gain error Is measured using Internal RFB only. Gain error can be trimmed to zero using circuits of Figures 5 and 6.
f. Measured to '/ 2 LSB. oun Load = 100
DAC output measured from failing edge of WR .
g. Feedthrough error may be reduced by connecting the metal lid on the side braze package to DGND.
h. Sample tested at 25°C to ensure complianoe.
.n..
CAUTION
ESDS (Electro-Static-Discharge-Sensit,ve) device.
The digital control inputs are diode protected;
however, permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
DIE TOPOGRAPHY
96 mils
Pad
No.
Funotlon
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Out 1
Out 2
AGND
D3
D2
D1
14
4
13
r
" 1
:'®
12
5
88 mils
6
7
8
9
Ilo
CS
WR
Ao
A1
DGND
ern
V oolSubstrate)
V REF
RFB
20X
CSARA
276 PMOS Transistors
309 NMOS Transistors
1 NPN Transistor
1 Zener Diode
18 Diodes
9 400 n N+ Resistors
6-80
1 3 kn N+ Resistor
13 10 kn Thin Film Resistors
13 20 kn Thin Film Resistors
11170 n Poly silicon Resistors
8 340 n Polysilicon Resistors
Preliminary
Si7542
...... Siliconix
incorporated
~
DEFINITION OF TERMS
GAIN ERROR
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation from a straight
line passing through the endpoints of the DAC
transfer function. It is measured after adjusting for
zero and full scale and is expressed in % or ppm of
full scale range or (sub) multiples of 1 LSB.
Gain error or full-scale error is a measure of the
difference between an ideal DAC's and the actual
device output. For the Si7542, ideal full-scale
output is -(4095/4096). ('4IEF). Gain error is
adjustable to zero using external trims as shown in
Figures 5 and 6.
OUTPUT LEAKAGE CURRENT
Current which appears at OUTl with the DAC
register loaded to all O's or at OUT2 with the DAC
register loaded to all l's.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB max over the
operating temperature range insures monotonicity.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VREF
terminal to OUT1 with DAC register loaded to all
O's.
DETAILED DESCRIPTION
GENERAL CIRCUIT INFORMATION
The Si7542, a 12-bit multiplying D/A converter,
consists of a highly stable thin-film R-2R ladder and
twelve N-channel current switches on a monolithic
chip. Most applications require the addition of only
an output operational amplifier and a voltage or
current reference.
41
TO R-2R
RESISTOR
LADDER
CONTROL
FROM
LOGIC
---------.J
..-----,
OUT2
The simplified DI A circuit is shown in Figure 1. An
inverted R-2R ladder structure is used, that is, the
binarily weighted currents are switched between the
OUT1 and OUT2 bus lines, thus maintaining a
constant current in each ladder leg independent of
the switch state.
'--j-I--+-H.....-lr-H......- - O OUT2
1---1
I
I
DAC REGISTER
I
i--H---i
OUTI
RFB
OUT1
Figure 2. Simplified Schematic, Single SPOT Switch
One of the current switches is shown in Figure 2.
The input resistance at VREF (Figure 1) is always
equal to R LOR (R LOR is the R-2R ladder
characteristic resistance and is equal to value
"RREF")' Since RREF at the VREF pin is constant,
the reference terminal can be driven by a reference
voltage or a reference current, AC or DC, of
positive or negative polarity. (If a current source is
used, a low temperature coefficient external RFB is
recommended to define scale factor.)
10k.!},
(LSBI
.
Figure 1. SI7542 Functional Diagram (All Inputs HIGH)
Preliminary
6-81
Si7542
flY'Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and
all digital inputs HIGH are shown in Figures 3 and 4.
In Figure 3 with all digital inputs LOW, the reference
current is switched to OUT2. The current source
I LEAKAGE is composed of surface and junction
leakages to the substrate, while the 114096 current
source represents a constant 1-bit current drain
through the termination resistor on the R-2R ladder.
The .. ON " capacitance of the output N-channel
switch is 200 pF, as shown on the OUT2 terminal.
The .. OFF" switch capacitance is 70 pF, as shown
on the OUT1 terminal. Analysis of the circuit for all
digital inputs HIGH, as shown in Figure 4, is similar
to Figure 3; however, the "ON" switches are now
on terminal OUT1, hence the 200 pF at that
terminal.
R=10k.o.
1RE!+ R = 10 k.o.
VREF
1/4096
t
OUT1
1200PF
IlEAKAGE
t~
"'----'--::L-----,.0
70 pF
OUT2
ILEAKAGE
I
Figure 4. SI7542 Equivalent Clroult (All Inputs HIGH)
....-_ _ORFB
R = 10 k.o.
ILEAKAGE
I
R~
R = 10 k.o.
-=-
I-
70 pF
OUT1
Figure 3. 517542 Equivalent Clroult (All Inputs LOW)
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 5 shows the analog circuit ccnnections
required for unipolar binary (2-quadrant multiplication) operation. The logic inputs are omitted for
clarity. With a DC reference vcltage .or current
(positive,or negative polarity) applied at pin 15, the
circuit is a unipolar D/A converter. With an AC
reference voltage or current the circuit provides
2-quadrant
multiplicaticn
(digitally controlled
attenuaticn). The input/cutput relationship is shown
in Table 1.
6-82
Figure 6. Unipolar Binary Operation (2 - Quadrant)
Preliminary
Si7542
W'r' Siliconix
~
incorporated
APPLICATIONS (Cont'd)
TABLE 1.
DIGITAL INPUT
LSB
MSB
1111 1111 1111
ANALOG OUTPUT
(VOUT )
-(4095/4096) V REF
1000 0000 0000
-(1/2) V REF
0000 0000 0001
-(1/4096) V REF
0000 0000 0000
OV
Unipolar Binary Code Table for Circuit
of Figure 5
Figure 6.
Bipolar Operation (4 - Quadrant Multiplication)
TABLE 2.
DIGITAL INPUT
MSB
LSB
R1 provides full scale trim capability, i.e. load the
DAC register to 1111 1111 1111, adjust R1 forVoUT
(4095/4096) (-VREF). Alternatively, full scale can
be adjusted by, omitting R1 and R2 and trimming the
reference voltage magnitude.
=
ANALOG OUTPUT (VOUT )
1111 1111 1111
+(2047/2048) V REF
1000 0000 0001
+(1/2048) VREF
1000 0000 0000
OV
0111 1111 1111
-(1/2048) VREF
0000 0000 0000
C1 phase compensation (10 to 25 pF) may be
required for stability when using a high speed
amplifier. (C1 is used to cancel the pole formed by
the DAC internal feedback resistance and the
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to
provideVos <10% of the voltage resolution atVOUT.
Additionally, the amplifier should exhibit a bias
current which is low over the temperature range of
interest (bias current causes output offset at VOUT
equal to I B times R FB; R FB is nominally 10 kIl).
-VREF
Bipolar Binary Code Table for Circuit
of Figure 6
With the DAC register ,loaded to 1000 0000 0000,
adjust R1 for VOUT
(alternatively, one can
omit R1 and R2 arid adjust the ratio of R3 to R4 for
VOUT = 0 V). Full scale trimming can be
accomplished by adjusting the amplitude of VREF or
by varying the value of R5.
=a v
As in unipolar operation, A 1 must be chosen for low
Vos and low lB. R3, R4 and R5 must be selected for
matching and tracking. Mismatch of 2R3 to R4
causes both offset and Full Scale error. Mismatch
of R5 to R4 or 2R3 causes Full Scale error. C1
phase compensation (10 pF to 25 pF) may be
required for stability.
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 6 and Table 2 illustrate the circuitry and code
relationship for bipolar operation. With a DC
reference (positive or negative polarity) the circuit
provides offset binary operation. With an AC
reference, the eleven LSBs provide digitally
controlled attenuation of the AC reference while the
MSB provides polarity control.
Preliminary
INTERFACE LOGIC INFORMATION
The Si7542 is designed to
memory-mapped output device.
interface
as
a
A typical system configuration is shown in Figure B.
CS is the decoded device address, and is derived
by decoding the three higher order address bits. AO
and A1 are the operation address, and are
decoded internally in the Si7542 to point to the
desired loading operation (i.e., load high byte,
6-83
Si7542
..,. 8i1iconix
incorporated
~
APPLICATIONS (Cont'd)
middle byte, low byte or DAC register). Table 3
shows the 8i7542 truth table.
All data loading operations are identical to the write
cycle of a RAM as shown in Figure 7.
.
IN SUMMARY:
1. The
8i7542
DAC
register
can
be
asynchronously cleared with the CLR input.
2.
Each 8i7542 requires four locations in memory.
3. Performing any of the four basic loading
operations (i.e., load low byte data register,
middle byte data register, high
byte data
register or 12-bit DAC register) is accomplished
by executing a memory WRITE operation to the
applicable address location for the required
DAC operation.
Additionally, the CLR input allows the 8i7542 DAC
register to be cleared asynchronously to 0000 0000
0000. When operating the 8i7542 in a unipolar
mode (Figure 5), a CLEAR causes the DAC output
to assume V. In the bipolar mode (Figure 6), a
CLEAR causes the DAC output to go to -VREF.
a
TABLE 3. SI7542 Truth Table
SI7542 Control Inputs 1
SI7542 Operation
A1
AO
-CS
X
X
X
X
0
Resets DAC 12-Blt Register
to Code 0000 0000 0000
X
X
1
X
1
No Operation
Device Not Selected
0
0
0
1f'
1
Load LOW-Byte4
Data Register
0
1
0
1f'
1
Load MIDDLE-Byte4
Data Register
1
0
0
'U'
1
Load HIGH-BytEI'
Data Register
1
1
0
1r
1
Load 12-Blt DAC Register with Data In
LOW-Byte, MIDDLE-Byte and HIGH-Byte
Data Registers
WR 2 ,3 CLR
Load Applicable
Data Register with
Data at 00-03
Notes:
1.1 Indicates logic HIGH, 0 Indicates logic LOW, X Indicates don't care.
2. This control signal Is level triggered.
3. 1f' Indicates register latches are transparent when WR = 0, data are stored on edge shown.
4. (MSB) XXXX
HIGHByte
6-84
XXXX
MIDDLEByte
XXXX (LSB)
LOW. Byte
Preliminary
Si7542
"..,. Siliconix
incorporated
~
APPLICATIONS (Cont'd)
~I.~::::::::~A~D~D:R~E~S~S~B~U~S~V~A~L:ID~-=-=-=-=-=-=-=-=~~~~
(Pllts°l~~_l_l_)_ _JX,"_~::;:~____________"""",,::---JX," _____
I
I tAWH I
~
CS
(PIN 8)
I'"
tAWS
WR
(PIN 8)
03-00
(PINS 4-7)
r
'-'::"tc-w-s-------..l...---:----'
'I"
I
tCWH
I.
.1
I
tWR
~
>t~:~
_ _ _ _ _ _ _ _ _ _ _ _- - J
I
I
-,
X
X
I~~--JI
'------
I- DATA BUS ·1
VALID
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS VIH; V1L
Figure 7. SI7542 TIming Diagram
APPLICATION HINTS
The Si7542 is a precision 12-bit multiplying DAC
designed for system interface. To ensure system
performance consistent with Si7542 specifications,
careful attention must be given to the following:
1.
2.
Ground Management: Voltage differences
between the Si7542 AGND and DGND cause
loss of accuracy. (DC voltage difference
between the grounds introduces gain error. AC
or transient voltages between the grounds
cause noise injection into the analog output.)
The simplest method of ensuring that voltages
at AGND and DGND are equal is to tie AGND
and DGND together at the Si7542. In more
complex systems where the AGND-DGND
connection is at a distant place, it is
recommended that diodes be connected in
inverse parallel between the Si7542 AGND and
DGND pins (1 N914 or equivalent).
Output Amplifier Offset: CMOS DACs exhibit a
code-dependent output resistance which in turn
causes a code-dependent amplifier noise gain.
The effect is a differential nonlinearity term at
the amplifier output which depends on Vas CVas
is amplifier input offset voltage). This
differential nonlinearity term adds to the R-2R
differential nonlinearity. To maintain monotonic
operation, it is recommended that amplifier Vas
Preliminary
be no greater than 10% of the DAC's output
resolution over the temperature range of
interest (output resolution = VREF/4096).
3. High Frequency Considerations: Si7542 output
capacitance works in conjunction with the
amplifier feedback resistance to add a pole to
the open loop response. This not only reduces
closed loop bandwidth, but can also cause
ringing or oscillation if the spurious pole
frequency is less than the amplifier's 0 dB
crossover frequency. Stability can be restored
by adding a phase compensation capacitor in
parallel with the feedback resistor.
4. Gain Temperature Coefficients: The gain
temperature coefficient of the Si7542 has a
maximum value of 5 ppm/oC and a typical
value of 2 ppm/oC. This corresponds to gain
shifts of 2.0 LSBs and 0.82 LSBs respectively
over a 100°C temperature range. When trim
resistors are used to adjust full-scale range as
shown in Figures 5 and 6 the temperature
coefficient of R1 and R2 should be taken into
account. It may be shown that the additional
gain temperature coefficients introduced by R1
and R2 may be approximately expressed as
follows:
6-85
Si7542
..... Siliconix
incorporated
~
APPLICATION HINTS (Cont'd)
T. C. Contribution = - ~ ('Y 1 + 300)
due to R1
RREF
T. C. Contribution = + RR2 ('Y2 + 300)
due to R2
REF
standard Si7542 gain error specification of ±12.3
LSBs it is recommended that R1 = 120 0, and R2 =
60 0,. With 'Y = 50, these values result in an overall
maximum gain error temperature coefficient of:
5 ppm/DC +....§QlL (50 + 300)
10 ko,
Where 'Y1 and 'Y2 are the temperature coefficients
in ppm/oC of R1 and R2 respectively and R REF is
the DAC input R REF resistance at the VREF
terminal. For high quality wire-wound resistors and
trimming potentiometers 'Y is of the the order of 50
ppm/DC. It will be seen that if R1 and R2 are small
compared with R REF their contribution to gain
temperature coefficient will also be small. For the
= 6.5 ppm/DC
However, if the Si7542GTD is used which has a
specified gain error of ±1 LSB, then with R1 = 10 0,
and R2 = 5 0, the maximum gain temperature
coefficient is increased by only 0.17 ppm/DC.
Where possible R1 should be a select-on-test fixed
resistor since the resulting gain temperature
coefficient will be tighter in all cases.
INTERFACING
Si7542 INTERFACE TO MC6BOO
four addresses. Table 4 gives a sample loading
subroutine.
A typical 6800 system configuration is shown in
Figure 8. Since the Si7542 contains four registers,
each Si7542 is assigned four locations in memory.
AO and A 1 provide the operational addresses and
are decoded internally to point to the desired
register. Register loading is accomplished by
executing a memory WRITE instruction to one of the
Choosing an arbitrary start address of 7542,
locations 7558, 7559 and 755A select the low,
middle and high byte registers respectively while
address 755B selects the 12-bit DAC register. The
12-bit data to be passed to the subroutine is stored
in 4-bit bytes in the lower halves of locations 755C,
755D and 755E.
00-07
FROM
SYSTEM---~
RESET
MC6BOO
RiWt-------I
AO-A15
ADDRESS BUS
Figure 8. Interfacing the SI7542 to an MC6BOO Microprocessor
6-86
Preliminary
.-F Siliconix
~
Si7542
Incorporated
INTERFACING
TABLE 4.
Sample Subroutine for S17542-MC6800 Interface
1.QQ
~
~
XXXX
XXXV
XXXZ
BD
75
42
B6
75
5C
B7
75
58
B6
75
50
B7
75
59
B6
75
5E
B7
75
5A
B7
75
5B
39
JSR
REMARKS
Jump to subroutine
LOA
Low-Byte Data -> A
STA
Load Low-Byte register
LOA
Med-Byte data -> A
STA
Load Med-Byte register
LOA
High-Byte data -> A
STA
Load High-Byte register
STA
DAC register loaded
RTS
Return from subroutine
Low-Byte register address
Med-Byte register address
High-Byte register address
DAC register address
Low-Byte data
Med-Byte data
High-Byte data
7542
7543
7544
7545
7546
7547
7548
7549
754A
754B
754C
7540
754E
754F
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
755A
755B
755C
7550
755E
8i7542 INTERFACE TO 808SA
The typical SOS5A system configuration is shown in
Figure 9. The Si7542 CS input is decoded from the
three high order address lines A13-A 15. The SOS5A
WR output is directly connected to the WR input of
the Si7542. Table 5 gives a sample loading
subroutine. The 12-bit data to be passed to the
subroutine is stored in locations 7550 and 755E.
The four most significant data bits are assumed to
occupy the lower half of 755E. Locations 7559.
755A. 7558 and 755C select the low byte. middle
byte. high byte and OAC registers respectively.
..
A8-15 1-----7'
ALE
808SA
ADO-7
ADDRESS/DATA BUS
Figure 9. Interfacing the SI7542 to an 8085 Microprocessor
Preliminary
6-S7
Si7542
.-JP'"
~
Siliconix
incorporated
INTERFACING
TABLES.
Sample Subroutine for S17542-8085A Interface
.l.QQ
~
.MI.!::!fM
XXXX
CO
75
42
3A
CAL
XXXV
XXXZ
7542
7543
7544
7545
7546
7547
7548
7549
754A
754B
754C
7540
754E
754F
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
755A
755B
755C
7550
755E
75
50
32
75
59
1F
1F
1F
1F
32
75
5A
3A
75
5E
32
75
5B
32
75
5C
C9
REMARKS
Call subroutine
LOA
Low- and Med- Byte
data -> A
STA
Load Low-Byte register
RAR
RAR
RAR
RAR
STA
Rotate right (4 times)
LDA
High-Byte data -> A
STA
Load High-Byte register
STA
Load DAC register
RET
Return
Low-Byte register address
Med-Byte register address
High-Byte register address
OAC register address
Low- and Med-Byte data
High-Bite data
Load Med-Byte register
PIN DESCRIPTION (DIP)
PIN
NUMBER
PIN
NUMBER
SYMBOL
DESCRIPTION
SYMBOL
DESCRIPTION
OUT1
Current Output 1
9
WR
WRITE Input
2
OUT2
Current Output 2
10
AO
Address Bus Input
3
AGND
Analog Ground
11
A1
Address Bus Input
4
03
Data Input (MSB)
12
DGND
Digital Ground
5
02
Data Input
13
CLR
Clear Input
6
01
Data Input
14
VOO
+V Supply Input
7
DO
Data Input (LSB)
15
VREF
Reference Input
8
CS
Chip Select Input
16
RFB
DAC Feedback Resistor
6-88
Preliminary
Si7542
Ir7" Siliconix
.r;;#I incorporated
BURN-IN DIAGRAMS
+15 V
Dual-In-Llne Package
+15 V
......,,,, --rt+5 V
PLCC-20 Package
+5 V
NOTE: All resistors are 1 k.o..
Preliminary
6-89
Si7543
CMOS 12·Bit
Serial Input DAC
.... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Serial Load On Positive
Or Negative Strobe
• Reduced Pin Count and
Board Space
• Industrial Process
Control
• Nonlinearity: ± 1/2 LSB
Tmin to Tmax
• Improved Accuracy
• Instrumentation
• Reduced Calibration
• Digital Attenuation
• Low Gain Drift:
2 ppm/DC Typ.
5 ppm/DC Max.
• Simplified Interface
• Analog Multiplication
o Reduced Power
&I
Remote Sensing
• Full 4-Quadrant
Multiplication
• Single +5 Volt Supply
Op'eration
DESCRIPTION
The Si7543 is a precision CMOS 12-bit multiplying
DAC. Its serial data input reduces the number of
input data lines required, resulting in a smaller
package.
The Si7543 includes two registers and a multiplying
DAC. Register A is a serial-to-parallel shift register.
The data is clocked from the SRI pin into this
register on the edge of the strobe input; either the
rising or the falling edge can be selected. After
Register A is full the contents are transferred to
Register B, a separate DAC register, by using the
load inputs. Register B can be reset at any time by
use of the CLR (clear) input.
True 12-bit linearity (1/2 LSB) , low gain tempco
(5 ppm/oC), and low gain error (1 LSB) eliminate
the need for DAC calibration and improve system
accuracy. The full 4-quadrant multiplying capability
facilitates digitally-controlled attenuation and control of ac signals without requiring a dc bias.
Applications include serial interface control loops,
remote data acquisition and conversion, avionics,
and portable instrumentation.
Built on the Siliconix PolyMOS'" process, the Si7543
uses highly-stable thin film resistors which are
laser-trimmed for high accuracy. An epitaxial layer
prevents latchup.
Packaging options include the 16-pin side braze DIP
and LCC-20 for military, S, T suffix (-55 to 125°C)
operation, 16-pin CerDIP for industrial, A, B suffix
(-40 to 85°C) operation, the 16-pin plastic DIP and
PLCC-20 for commercial, J, K suffix (0 to 70°C)
operation.
PIN CONFIGURATION
PLCC Package
LCC Package
Top View
Dual-In-Llne Package
Top View
o
o
0
V
U U
R R
T TN F E
210 B F
Top View
U
~
3112111112~1191
RFB
VREF
AGND~
STB1~
OCR
~~
STB4
T~
V
R R
~ ~
/
VDD
DGND
0
U
LD1~
NO 8
8 VDD
~OCR
6 NO
~
DGND
4 STB4
AGND
VDD
STB1
OCR
NO
TIii
NO
DGND
NO
STB4
Si'ii3
STB2
--..._ _..r-
S
S N
~ ~
2
6-90
0
L S
~ ~
3
Si7543
WY'Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
RFB
OUT 1
V REF
OUT 2
AGND
CLR
TI5i
LD2
STBl
SRI
STB4
Vee
STB3
DGND
STB2
ORDERING INFORMATION
INL
Tmln - Tmax
(LSB)
:!: 1
:!: 1/2
:!: 1/2
GAIN
ERROR
Ta = 25°C
(LSB)
:!: 12.3
:!: 12.3
:!: 1
TEMPERATURE RANGE AND PACKAGE
PLASTIC
o to 70°C
PLCC-20
o to 700C
CerDIP
-40 to 85°C
SIDE BRAZE
-55 to 125°C
LCC
-55 to 125°C
SI7543JN
SI7543JP
SI7543AO
SI7543SD
SI7543KN
SI7543KP
SI7543BO
SI7543TD
SI7543SE
SI7543TE
SI7543GKN
SI7543GKP
SI7543GBO
SI7543GTD
SI7543GTE
ABSOLUTE MAXIMUM RATINGS'
Vee to AGND ............•.•............. -0.3, +17 V
Vee to DGND ............................ -0.3, +17 V
VREF to AGND .....••..•..................... ±25 V
V RFB to AGND ............•................... ±25 V
Digital Input Voltage to DGND ...•..... -0.3 V, +15.3 V
VOUTl, VOUT2 to AGND ............... -0.3 V, +15.3 V
AGND to DGND .............................•.. Vee
DGND to AGND ..............................•• Vee
Storage Temperature .•................. -65 to 150°C
Operating Temperature (N, P Suffix) •..•.••.• 0 to 70°C
(0 Suffix) .......... -40 to 85°C
(D, E Suffix) ...... -55 to 125°C
Power
16-Pln
16-Pin
20-Pln
20-Pln
Dissipation (Package)"
Plastic DIP'" ........................
Ceramic Side Braze' '" ..•............
Plastic Leaded Chip Carrier'" ..........
LCC"" . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
470
900
450
900
mW
mW
mW
mW
Stress ratings only. Exposure to absolute max rating
conditions for extended periods may affect device
reliability.
All leads welded or soldered to PC Board.
'" Derate 6.5 mW/oC above 25°C.
'" 'Derate 12 mW/oC above 75°C.
6-91
Si7543
..... Siliconix
.,,1;11 incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Voo= 5 V,VREF = +10 V
VOUT1=V0UT2= 0 V
Output Amplifier: OP-07
LIMITS
1=25·C
2=125,85,70·C
3=-55,-40,0 ·C
ALL GRADES
EXCEPT AS
NOTED
TEMP
TYP d MIN b MAXt
UNIT
1,2,3
12
Bits
A, J, S Grades
1,2,3
-1
1
All Other Grades
1,2,3
-0.5
0.5
A, J, S Grades
1,2,3
-2
2
All Other Grades
1,2,3
-1
1
G Grade
1
-1
1
All Other Grades
1
-12.3
12.3
GB, GK Grades
2,3
-1
1
GT Grade
2,3
-2
2
J, K Grades
2,3
-13.5
13.5
S, T, Grades
2,3
-14.5
14.5
A, B Grades
2,3
-13.5
13.5
~ Gain I~ Temperature
1,2,3
-5
5
ppml
·C
~Galn I~ Voo
Voo=±5%
1
2,3
-0.005
-0.01
0.005
0.01
%
per
%
DAC Loaded with All Zeros: loun
DAC Loaded with All Ones: IOUT2
1
-5
5
J, K, GK Grades
2,3
-10
10
All Other Grades
2,3
-200
200
ACCURACY
Resolution
Relative Accuracy
(Integral Non-Linearity)
Differential Nonlinearity
Gain Errors
N
INL
(1LSB = 0.024%
of Full Scale)
DNL
GFSE
Gain Temp Coefficient"
TC GFS
Power Supply Rejection
PSRR
Output Leakage Current
jPln 4 = OUT11
Pin 5 = OUT2
IOUT1,
IOUT2
2
LSB
nA
DYNAMIC
Current Settling Time c, 9
ts
Multiplying Feedthrough
Error c, 9
FT
6-92
VREF= ±10 V
10kHz Sine Wave
1,2,3
2
p,s
1,2,3
2.5
mVp-p
...w"
~
Si7543
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V DD = 5 V,VREF = +10 V
Voun=VouT2= 0 V
Output Amplifier: OP-07
LIMITS
1=25·C
2=125,85,70·C
3=-55,-40,0 ·C
TEMP
TYP d
1,2,3
10
ALL GRADES
EXCEPT AS
NOTED
MIN b MAXb
UNIT
DYNAMIC (Cont'd)
Reference Input Resistance
(Pin 15)
RREF
8
25
DAC Loaded to All Zeros
1,2,3
70
DAC Loaded to All Ones
1,2,3
200
DAC Loaded to All Zeros
1,2,3
200
DAC Loaded to All Ones
1,2,3
70
k!l.
Coun
Output Capacltance c
pF
C OUT2
LOGIC INPUTS
Logic HIGH Voltage
V IH
1,2,3
Logic LOW Voltage
V IL
1,2,3
Input Current
liN
Input Capacltancec
CIN
3
V
VIN = 0 V orVDD
0.8
1
JJ.A
1,2,3
8
pF
1,2,3
<0.001
-1
TIMINGi'!
tDS1
STB 1 Used as a Strobe
1
2,3
50
100
tDS4
STB4 Used as a Strobe
1,2,3
0
tDS3
S'i"e3 Used as a Strobe
1 ,2,3
0
tDS2
STB2 used as a Strobe
1
2,3
20
40
tDH1
STBl Used as a Strobe
1
2,3
30
60
tDH4
STB4 Used as a Strobe
1
2,3
80
160
tDH3
STB3 Used as a Strobe
1
2,3
80
160
tDH2
STB2 used as a Strobe
1
2,3
60
120
Serial Inrrut to Strobe
Setup Tme
ns
Serial Input to Strobe
Hold Time
6-93
Si7543
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Voo = 5 V, VREF = +10 V
VOUT1=VOUT2= 0 V
Output Amplifier: OP-07
LIMITS
1=25°C
2=125,85,70 0 C
3=-55,-40,0 ·C
TEMP
TYP d
ALL GRADES
EXCEPT AS
NOTED
MIN b MAXt
UNIT
TIMING h (Cont'd)
tSRI
1
2,3
80
160
STB1 Pulse Width
tSTB1
1
2,3
80
160
STB4 Pulse Width
tSTB4
1
2,3
100
200
STB3 Pulse Width
tSTB3
1
2,3
100
200
STB2 Pulse Width
tSTB2
1
2,3
80
160
Load Pulse Width
LD1 ,
tlO2
1
2,3
150
300
Min. Time Between Strobing
LSB Into Re~lster A and
Loading Reg ster B
tAsB
1,2,3
0
CLR Pulse Width
tClR
1
2,3
200
400
Supply Voltage
Voo
1,2,3
Supply Current
100
SRI Data Pulse Width
ns
SUPPLY
--
Digital Inputs = VIH or VIL
1,2,3
5
V
2.5
mA
NOTES:
a. Refer to PRoCEss OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Galh error Is measured using Internal RFB only. Gain error can be trimmed to zero using cIrcuits of Figures 6 and 7_
f. Measured to ' 12 LSB. OUT1 Load = 100 .n., DAC output measured from failing edge of LDl and LD2 .
g. Feedthrough error may be reduced by connecting the metal lid on the side braze package to DGND.
h. Sample tested at 25°C to ensure compliance.
CAUTION
ESDS (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are diode protected;
however, permanent damage may occur on
unconnected devices subject to high energy
6-94
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
Si7543
..... Siliconix
incorporated
~
DIE TOPOGRAPHY
817543
Pad Function
No.
--I
.....1 - - - - - 96 mils - - - - _ I I..
1
3
4
1
5
BB mils
6
1O(®
7
B
1
1
2
3
4
5
1JST
6
N/C
7
B
9
10
11
12
13
14
15
16
SRI
STB2
LD2
STB3
STB4
DGND
CLR
VDD (Substrate)
VREF
RFB
OUT1
OUT2
AGND
STB1
9
20X
CSARB
276 PMOS Transistors
309 NMOS Transistors
1 NPN Transistor
1 Zener Diode
1B Diodes
9 400 .n N+ Resistors
13k .n N+ Resistor
13 10k .n Thin Film Resistors
13 20 k .n Thin Film Resistors
11 170.n Potysillcon Resistors
8 340 .n Polyslllcon Resistors
DEFINITION OF TERMS
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation from a straight
line passing through the endpoints of the DAC
transfer function. It is measured after adjusting for
zero and full scale and is expressed in % or ppm of
full scale range or (sub) multiples of 1 LSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified
differential nonlinearity of ±1 L8B max over the
operating temperature range insures monotonicity.
GAIN ERROR
Gain error or full-scale error is a measure of the
difference between an ideal DAC's and the actual
device output. For the 8i7543, ideal full-scale
output is -(4095/4096). (VREF)' Gain error is
adjustable to zero using external trims as shown in
Figures 6 and 7.
OUTPUT LEAKAGE CURRENT
Current which appears at OUT1 with the DAC
register loaded to all O's or at OUT2 with the DAC
register loaded to all 1 'so
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VREF
terminal to OUT1 with DAC register loaded to all
O's.
6-95
Si7543
..... Siliconix
,1;11 incorporated
DETAILED DESCRIPTION
The Si7543 includes two registers and a 12-bit DAe.
The DAe circuit consists of an R-2R resistor array
as shown in Figure 1. Thin-film resistors are used,
which are laser-trimmed for accuracy. Depending
upon the status of each input bit, the binarily
weighted currents are switched to either OUT1 or
OUT2. This maintains a constant current through
each ladder leg regardless of the switch state. A
typical NMOS current switch is shown in Figure 2.
When all digital inputs are LOW, the equivalent
circuit appears as shown in Figure 3. There are two
current components shown: I REF and I LEAKAGE.
The I REF f4096 current source is actually the 1 LSB
current which flows through the ladder termination
resistor to GND. The ILEAKAGE current sources
represent surface and junction leakages to the
substrate.
I~
~~+-~-r4-~i~---r~+---OO~
'-l----~i----~I__--jl---+-~p___O
OUT1
RFB
DAC REGISTER B
Figure 1. SI7543 Functional Diagram (All Inputs HIGH)
TO LADDER
FROM
INTERFACE
LOGIC
O~
OUT1
Figure 2. Simplified Schematic, Single SPOT Switch
The output current is a function of VREF and the
digital input code. (Hence the term multiplyIng
DAe.) The input resistance at VREF is equal to
value "R" and does not change with input code.
VREF can be either a fixed or time varying voltage
or current, of positive or negative polarity. If a
current source is used for the reference input, then
a low temperature coefficient resistor should be
used for R FB to minimize gain variation with
temperature.
R =10 kn.
O~
VREF
+
-
-
Figure 3. SI7543 Equivalent Circuit (All Inputs LOW)
The 70 pF capacitor on OUT1 represents the OFF
capacitance of the output switch. The 200 pF
capacitor on OUT2 represents the switch ON
capacitance.
A similar analysis holds when all digital inputs are
HIGH, as shown in Figure 4. Notice that in this case,
the 200 pF is on OUT1 and the 70 pF is on OUT2.
This capacitance is code-dependent and is a
function of the number of ON switches which are
connected to a specific output.
oun
r-------:t:4--------0
t.9
..l.LEAKAGE
EQUIVALENT CIRCUIT ANALYSIS
Figures 3 and 4 show the equivalent circuits for the
R-2R ladder when all digital inputs are LOW or HIGH
respectively.
6-96
1
ou~
70PF
Figure 4. SI7543 Equivalent Circuit (All Inputs HIGH)
Si7543
trY" Siliconix
.J;;II incorporated
DETAILED DESCRIPTION
INTERFACE LOGIC
As previously stated, the Si7543 includes two
registers. The timing diagram is shown in Figure 5
and the truth table in Table 1. Register A is a
serial-to-parallel shift register. The data is clocked
from the SRI pin into this register on the rising edge
of STB1, STB2, or STB4 or on the falling edge of
STB3.
TABLE 1. 517543 Truth Table
517543 Control Inputs
Register A Control Inputs Register B Control Inputs
STB4 STB3 STB2 STB1
a
a
a
S
a
s
S
a
1:.
a
a
1
a
a
1
1
1
X
X
X
X
a
x
x
X
X
X
1
CLR
LD2
LD1
x
x
x
x
x
x
x
x
x
SI7543 Operation
X
Data Appearing at SRI Strobe Into Register A
2, 3
x
X
No Operation (Register A)
a
Notes
X
X
1
1
X
1
X
1
1
a
a
Clear Register B to Code 0000 0000 0000
(Asynchronous Operation)
3
1,3
No Operation (Register B)
3
Load Register B With The Contents of Register A
3
NOTES:
1. CLR = a asynchronously resets Register B to 0000 0000 000, but has no effect on Register A.
2. Serial data Is loaded Into Register A MSB first, on edges shown S Is positive edge 1:. Is negative edge.
3. a = Logic LOW, 1 = Logic HIGH, X = Don't Care.
4. (MSB) XXXX
XXXX
XXXX (LSB)
HIGHByte
MIDDLEByte
LOWByte
After Register A is full the contents are transferred
to Register B, a separate DAC register, by bringing
LD1 and LD2 momentarily LOW. Register B can be
reset (0000 0000 0000) at any time by bringing CLR
momentarily LOW. This can be used to initialize the
Si7543 at power up, or to rapidly bring the DAC
output to a known state. When operating in the
unipolar mode (Figure 6), a CLEAR sends the DAC
output voltage to a V. When in the bipolar mode
(Figure 7), a CLEAR sends the DAC output to
-VREF.
6-97
Si7543
trY" Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
=x
' - - t SRI ----.I
SRI
I
t DS1 ' t DS2 , t DS4
...!.I
I
I
~1~
k __B_IT_2_~>qP<
M
__
BI_T_11_..JX,---=E;::;!rB:...12_..JX'--_ __
I
STROBE INPUT
(STBt,STB2, STB411
(NOT,,)
1
tDH1' tDH2, tDH4
I
I
I
.
--~--'
f - - - - - - - - - LOADING REGISTER A ---------~.I
Li5i
AND LD2
NOTE:
STROBE WAVEFORM IS INVERTED IF
S'fli3 IS USED TO STROBE SERIAL DATA
BITS INTO REGISTER A.
LOADING REGISTER B . - - - ' "
WITH CONTENTS OF REGISTER A
Figure 5.
Sl7543 Timing Diagram
APPLICATIONS INFORMATION
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
TABLE 2.
Figure 6 shows the simplest Si7543 configuration.
The logic inputs are omitted for clarity. The input to
VREF can be either positive or negative; with a dc
reference voltage or current the circuit is a unipolar
01 A converter. With an ac reference voltage or
current the circuit provides 2-quadrant reference
multiplication (digitally controlled attenuation). The
inputloutput relationship is shown in Table 2.
+10 V
V REF
ANALOG OUTPUT (VOUT )
1111 1111 1111
-(4095/4096) V REF
1000 0000 0000
-(1/2) VREF
0000 0000 0001
-(1/4096) V REF
0000 0000 0000
OV
Unipolar Binary Code Table for Circuit
of Figure 6
-to V
V DD
V OUT
DGND AGND
Figure 6.
6-98
DIGITAL INPUT
MSB
LSB
Unipolar Binary Operation
(2 - Quadrant Multiplication)
R1 can be used to provide full-scale trim capability.
(Load the OAC register to 1111 1111 1111 and
for VOUT
-VREF (4095/4096).)
adjust R1
Alternatively, the full scale can be adjusted by
omitting R1 and R2 and trimming the VREF
magnitude. (See also the Application Hint "Gain
Temperature Coefficients".)
C1 (10 to 25 pF) is used for phase compensation
and may be required for stability when using a high
speed amplifier. (See the Application Hint "High
Frequency Considerations".)
~
~
Si7543
Siliconix
incorporated
APPLICATIONS INFORMATION
For amplifier A1 considerations,
Application Hint .. Output Offset".
refer to the
+10 V
VREF
~--+--------------------,
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The circuit for bipolar operation is shown in Figure
7, accompanied by the input/output relationship in
Table 3. With a positive or negative dc reference,
the circuit provides offset binary operation. With an
ac reference, the eleven LSBs provide digitally
controlled attenuation of the reference while the
MSB provides polarity control.
TABLE 3.
DIGITAL INPUT
MSB
LSB
ANALOG OUTPUT (VOUT )
1111 1111 1111
+(2047/2048) V REF
1000 0000 0001
+(1/2048) V REF
1000 0000 0000
0111 1111 1111
0000 0000 0000
OV
DGND AGND
Figure 7.
Bipolar Operation (4 - Quadrant Multiplication)
Unlike the unipolar circuit of Figure 6, the 0 V level
as well as the full-scale must be trimmed in this
circuit. To trim the 0 V level, load the DAC register
with 10000000 DODO, and adjust R1 forVOUT = 0 V.
Alternatively, R1 and R2 can be omitted and the
ratio of R3 to R4 adjusted fOrVOUT = 0 V. Full scale
can be trimmed by adjusting the amplitude of VREF
or by varying the value of R5.
-(1/2048) VREF
-VREF
Bipolar Binary Code Table for Circuli
of Figure 7
APPLICATIONS HINTS
GROUND MANAGEMENT
Voltage differences between the Si7543 AGND and
DGND cause loss of accuracy (dc voltage
difference between the grounds introduces gain
error. AC or transient voltages between the
grounds cause noise injection into the analog
output). The simplest method of ensuring that
voltages at AGND and DGND are equal is to tie
AGND and DGND together at the Si7543. In more
complex
systems
where
the
AGND-DGND
connection is at a distant point, it is recommended
that diodes be connected in inverse parallel
between the Si7543 AGND and DGND pins (1N914
or equivalent).
OUTPUT OFFSET
CMOS DACs exhibit a code-dependent output
resistance which in turn causes a code-dependent
error voltage at the output of the amplifier. The
maximum amplitude of this offset, which adds to
the D/A converter nonlinearity, is 0.67· Vos where
Vos is the amplifier input offset voltage. It is
recommended thatVos be no greater than 0.1 LSB
over the operating temperature range. The bias
current causes an output offset at VOUT equal to
IB • RFB.
HIGH FREQUENCY CONSIDERATIONS
The Si7543 output capacitance and the amplifier
feedback resistance combine to add a pole to the
open loop response. This reduces the closed loop
bandwidth, and may also cause ringing or
oscillation if the pole frequency is less than the
amplifier's 0 dB crossover frequency. Adding a
phase compensation capacitor in parallel with the
feedback resistor can restore stability to the circuit.
6-99
Si7543
.... 5i1iconix
incorporated
~
APPLICATIONS HINTS
TEMPERATURE COEFFICIENTS
The gain temperature coefficient of the 5i7543 has
a maximum value of 5 ppm/oC and a typical value
of 2 ppm/DC. This corresponds to gain shifts of 2
L5Bs and 0.8 L5B, respectively, over a 100°C
temperature range. When trim resistors R1 and R2
are used to adjust full-scale range, the temperature
coefficient of R1 and R2 should also be taken into
account. Resistors with temperature coefficients of
50 ppm/DC will usually give acceptable results. For
the standard 5i7543 with a maximum gain error of
±12.3 L5Bs, suitable values for R1 and R2 are
120 nand 60 n, respectively. This results in a
maximum additional gain error temperature
coefficient of approximately 3 ppm/DC.
However, if the 5i7543 GTO is used (max gain error
= 1 L5B) , then with R1 = 10 nand R2 = 5 n the
additional gain error temperature coefficient is only
0.25 ppm/DC maximum.
INTERFACING
Si7543 INTERFACE TO MC6800
The circuit in Figure 8 and the sample subroutine
shown in Table 4 demonstrate one method of
interfacing the 5i7543 to an MC6800 microprocessor. If the starting address for the subroutine is
7543 (Hex), then the data can be stored at the end
of the listing in locations 7550 (middle and lower
bytes) and 755E (high byte), as follows:
7550: 76543210
755E: BA98XXXX
where .. B" is bit 11 (M5B), .. 0" is bit 0 (L5B) , and
so on.
Data line D7 from the 6800 is used as the serial
input to the 5i7543 5RI pin. Starting with the MSB,
the data is strobed one bit at a time into Register A.
After all 12 data bits have been sent to the Si7543,
they are then loaded into Register B. Address bits
13, 14, and 15 of the 6800 are used to determine
STB3 (AOOO) and LD2 (BODO).
ADDRESS BUS (16)
AO-IS
ADRRESS (16)
I-lR:l!/-.l!lW~_ _ _ _ _ _--dEl
6800
"'q,r..2==--_______--IE3
8205
DECODER
Dol-----....::;~-==I=+==--A
DATA BUS (8)
L-__~D~7r_---lr----t__t-----y
DATA (8)
FROM SYSTEM R E S E T - - - - - - = = - - - - - - - - - I
Figure 8. Interfacing the SI7543 to an MC6800 Microprocessor
6-100
Si7543
flY' Siliconix
~
incorporated
INTERFACING (Cont'd)
TABLE 4.
Sample Subroutine for S17543-MC6800 Interface
~
7543
SEND
MNEMONIC
LDA
BSR
LDA
BSR
BSR
STA
RTS
LDA
STA
ROL
DEC
BNE
RTS
OPERANP
A.755E
SEND
A.755D
SEND
SEND
A,BOOO
COMMENT
Put upper 4 bits In Acc A
Send bits 11 through 8 to SI7543
Put lower 8 bits In Acc A
Send bits 7 through 4
Send bits 3 through 0
Load data Into S17543 Register B
B,#04
A,ADOO
A
B
SEND
Send 4 bits
Strobe data Into SI7543
Move next bit Into position
8i7543 INTERFACE TO SOS5A
Figure 9 and Table 5 show how the Si7543 can be
interfaced to the 8085. In this example, it is
assumed that the data to be sent is present in the H
and L registers as follows:
Register H: XXXXBA98
Register L: 786543210
where "B" is bit 11 (MSB), "0" is bit 0 (LSB) , and
so on.
Since bit 7 of the Accumulator will be used for the
serial data bit, the data is first left-justified in
(8)
Repeat until 4 bits sent
Registers Hand L. Bit 6 of the Accumulator is the
Serial Output Enable bit, and must be set before
the SIM instruction is used. The ORA instruction
puts the next data bit into bit 7 of the Accumulator,
keeping SOE asserted at the same time. The AI
instruction masks out all bits except 6 and 7,
insuring that no flags are inadvertantly reset.
Address bits 13, 14, and 15 are used to determine
STB3 and LD2. The data is strobed into the Si7543
by writing to location AOOO. After all 12 bits have
been sent, writing to location BOOO loads the data
into Register B of the Si7543.
ADDRESS BUS (16)
AO-1S
ADRRESS (16)
ALE
8205
8085
DECODER
WRr-----+-~r-------~~
(8) ADO-7
DATA (8)
SODr---------------~
FROM SYSTEM RESET~-----------------------I
Figure 9.
Interfacing the S17543 to an 8085 Microprocessor
6-101
Si7543
.... Siliconix
incorporated
~
INTERFACING (Cont'd)
TABLE 5.
Sample Subroutine for S17543-8085A Interface
J.Aa.E.L.
7543
SEND
MNEMONIC
MVI
DAD
DCR
JNZ
MVI
MVI
ORA
ANI
SIM
STA
DAD
DCR
JNZ
STA
RET
COMMENT
Left-Justify data
by shifting Hand L
left four times
OPERAND
B,04
H
B
7543
B,OC
A,70
H
CO
Counter for 12 bits
Enable Serial Output (SOD)
Preserve SOE and data bit
Don't reset flags
Latch data bit Into SOD FF
Strobe data Into SI7543
Shift next bit Into D7 of H
AOOO
H
B
SEND
BODO
Repeat until 12 bits sent
Load Register B of SI7543
PIN DESCRIPTION (DIP)
PIN
NUMBER
SYMBOL
DESCRIPTION
1
OUT1
DAC current output bus.
Normally terminated at
op amp virtual ground.
2
OUT2
DAC current output bus.
Normally terminated at
AGND.
3
AGND
Analog Ground
4
STB1
Register A Strobe 1
input, see Table 2.
5
LD1
DAC Register B Load 1
input. When LD1 and
LD2 go low the contents
of Register A are loaded
into DAC Register B.
6
NfC
No Connection.
7
SRI
Serial Data Input to
Register A.
8
STB2
Register A Strobe 2
input, see Table 2.
6-102
PIN
NUMBER
9
SYMBOL
LD2
10
STB3
11
STB4
12
13
DGND
CLR
14
15
VDD
VREF
16
RFB
DESCRIPTION
DAC Register B Load
2 input. When LD1 and
LD2 go low the contents
of Register A are loaded
into DAC Register B.
Register A Strobe 3
input, see Table 2.
Register A Strobe 4
input, see Table 2.
Digital Ground.
Register B CLEAR input
(active LOW) can be
used to asynchronously
reset Register B to
0000 0000 0000
+5 V Supply Input
Reference input. Can
be positive or negative
dc voltage or ac signal.
DAC Feedback Resistor.
Si7543
W'F Siliconix
~
incorporated
BURN-IN DIAGRAMS
+15 V
Dual-In-Llne Package
PLCC-20 Package
+15 V
+-----14
+5 V
NOTE: All resistors are 1 k.o. .
6-103
Si7545
CMOS 12-Bit
Buffered Multiplying DAC
frlT Siliconix
~
FEATURES
BENEFITS
APPLICATIONS
• On-Board Latches
• Simplified Microprocessor
Interface
• Microprocessor
Controlled Systems
• Low Gain TC: 2 ppm/oC
• True 12-Bit Linearity
• ATE Systems
• Four Quadrant
Multiplication
• Improved Stability
Over Temperature
• Power Supplies
• INL < 112 LSB
Q
• Low Gain Error
(G FSE < 1 LSB)
incorporated
• J.LP Controlled
Gainl Attenuation
Accepts Bipolar
Reference Inputs
• Function Generators
• Reduced System
Calibration
DESCRIPTION
The Si7545 is a monolithic 12-Bit CMOS digital-toanalog converter with an on-board 12-Bit wide latch
to simplify the interface to a data bus. The R-2R
ladder DAC allows four-quadrant multiplication for
ac attenuation applications. The Si7545 allows
flexibility in supply voltage and logic levels, being
specified for TTL-compatible operation when used
with a single 5 V power supply. CMOS logic
c~mpatibility is specified when operated from a
single 15 V supply.
The Si7545 is ideal for microprocessor-controlled
data conversion applications such as function
generation, power supplies, ATE systems, and
process control. As a four-quadrant multiplying
DAC, the Si7545 has applications in gain control,
attenuation,
filtering
and
programmable
references.
The Si7545 is built on the Siliconix proprietary
advanced 5-micron CMOS process known as
PolyMOS"'. Highly stable thin-film resistors are
used to provide superior matching and stability over
both temperature and time. Laser trimming is used
to achieve true 12-Bit linearity and low gain error.
An epitaxial layer prevents latchup.
The Si7545 is available in the 20-lead PDIP and
PLCC packages for operation over the commercial,
J, K, L suffix (0 to 70°C) temperature range, the
20-lead CerDIP for industrial, A, B, C suffix (-40 to
85°C) operation, and the 20-lead side braze and
LCC packages for military, S, T, U suffix (-55 to
125°C) temperature range operation. Four
accuracy grades are available
for each
temperature range.
PIN CONFIGURATION
Dual In LIne Package
PLee Package
o
,
OB11 (MSB)
OB10
DB9
OBB
OB7
A
G G 0
N N U
DDT
0
G
N
0
R R
F E
B F
3112111112Cl~9
A
G
N
0
0 R
U F
T B
V
R
E
F
0
~
~
~
4 WR
Os
~ OBO
(MSB)
VOO
~
~B
~4
9111QI111n21n3
o ODD 0
B B B B B
66432
6-104
Lee Package
v
OB1
DB11 (MSB)
VOO
OB10
WR
Os
DB9
(LSB)
OBB
OBO (LSB)
DB7
DB1
0 0
B B
6 5
0 0
B B
4 3
0
B
2
Si7545
.... Siliconix
incorporated
~
ORDERING INFORMATION
INL
Tmln - Tmax
(LSB)
GAIN
ERROR
Ta = 25°C
(LSB)
TEMPERATURE RANGE AND PACKAGE
PLCC
o to 700C
PDIP
o to 70°C
CerDIP
-40 to 85°C
SIDE BRAZE
-55 to 125°C
LCC
-55 to 125°C
:!: 2
:!:20
SI7545JP
SI7545JN
SI7545AQ
SI7545SD
SI7545SE
:!: 1
:!: 1/2
:!:10
SI7545KP
SI7545KN
SI7545BQ
SI7545TD
SI7545TE
:!:5
Sl7545LP
SI7545LN
SI7545CQ
SI7545UD
SI7545UE
:!: 1/2
:!:1
Sl7545GLP
SI7545GLN
SI7545GCQ
SI7545GUD
SI7545GUE
FUNCTIONAL BLOCK DIAGRAM
v REFo-J----j
........-t-OOUT
~~~:;;:~~~-t--oAGND
VDD
DGND
WR
Cs
DEFINITION OF TERMS
MULTIPLYING DAC
Digital-to-Analog Converters (DACs) are devices
that convert digital data into analog values. A
multiplying DAC is a device capable of handling
variable reference sources. Its output is the product
of two variables: the number represented by the
digital input code and the analog reference voltage.
RESOLUTION
Resolution indicates the number of digital input bits.
A 12-bit DAC resolves the full-scale range (FSR)
into 212 = 4096 states.
transfer function. It is measured after adjusting for
zero and full scale errors and is expressed in % of
full scale range or (sub)multiples of 1 LSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB max over the
operating temperature range ensures monotonicity.
GAIN ERROR
Value of the Least Significant Bit. For example, a
12-bit unipolar converter has a 1 LSB step value
equal to 'iREFI 212 or VREF/4096 (Volts).
Gain error or full-scale error is a measure of the
difference between an ideal DAC's and the actual
device output. For the Si7545, ideal full-scale
output is -(4095/4096) (VREF). Gain error is adjustable to zero using external trims as shown in
Figures 4 and 5.
RELATIVE ACCURACY (INL)
OUTPUT LEAKAGE CURRENT
Relative accuracy or end-point nonlinearity is a
measure of the maximum deviation from a straight
line passing through the end points of the DAC
This is the current that appears at OUTl with the
DAC loaded to all Os or at OUT2 with the DAC
loaded to all 1s.
LSB
6-105
Si7545
..... Siliconix
incorporated
~
DEFINITION OF TERMS (Cont'd)
the analog output at OUT1 reaches 90% of its final
OUTPUT CURRENT SETTLING TIME
This is the time required for the output current of
the DAC to settle to within 1/2 LSB into 100 n, and
is specified for a zero to full scale digital input
change.
PROPAGATION DELAY
This is a measure of the internal circuit delay from
the time a digital input changes to the point when
value.
DIGITAL TO ANALOG GLITCH IMPULSE
This is a measure of the area of the impulse
injected to the analog outputs when the digital
inputs change state. It is usually specified as the
area of the impulse in nV-secs. It is measured with
VREF = GND and an LH0032 as the output op amp,
and phase compensation capacitor
=0
pF.
ABSOLUTE MAXIMUM RATINGS*
Voo to DGND ........................... -0.3 V, 17 V
VREF to DGND ...............................
VRFB to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
± 25 v
± 25 V
Digital Input Voltage to DGND ........... -0.3 V to Voo
V OUT to DGND ......................... -0.3 V to Voo
VAGNO to DGND ....................... -0.3 V toVoo
Storage Temperature (D, Q, E Suffix) ..... -65 to 150·C
(N, P Suffix)
-65 to 125·C
Power Dissipation (Package)··
20-Pln Plastic DIP and PLCC··· .............. 470 mW
20-Pln CerDIP···· .............•............ 900 mW
20-Pln Ceramic Side Braze···· ......•........ 900 mW
20-Pln LCC···· . . . . . . . . .. . . . . . . . . . .. . . . . . ... 900 mW
Operating Temperature:
Commercial Grades (J, K, L, GL) ............ 0 to 70·C
Industrial Grades (A, B, C, GC) ........... -40 to 85·C
Extended Grades (S, T, U, GU) .......... -55 to 125·C
Stress rating only. Exposure to absolute max
rating conditions for extended periods may
affect device reliability.
All leads welded or soldered to PC board.
.,. Derate 6.5 mW/·C above 25·C.
•••• Derate 12 mW/·C above 75·C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
Voo = +5 V, V REF = +10 V
VOUT= 0 V, AGND = DGND
SYMBOL
Output Amplifier: OP-07
1=25·C
2=125,B5,70·C
3=-55,-40,0·C
~EMP
MIN b
MAXb
N
INL
Differential Nonlinearity
DNL
6-106
MIN b
MAXb UNIT
GFSE
(1LSB = 0.024% of Full Scale)
Measured Using Internal R FB
DAC Register Loaded With:
1111 1111 1111
1,2,3
12
1,2,3
-0.5
0.5
B,K,T:-1
A,J,S:-2
1
2
1,2,3
-1
1
B,K,T:-1
A,J,S:-4
1
4
12
1
2,3
GC,GL,GU:
GC,GL,GU:
-1
-2
1
2
1
2,3
C,L,U:
C,L,U:
-5
-6
5
6
1,2,3
Gain Temp Coefflclenf
A,J, S
. B,K,T
GRADE
,
Relative Accuracy
(Integral Non-Linearity)
Gain Errore
LIMITS
C,L,U
GC, GL,GU
GRADE
TVpd
ACCURACY
Resolution
(5 Volt Operation)
,
TCBFS
b.. Gain I b.. Temperature
1,2,3
2
-5
5
Bits
LSB
B,K,T:-10
A,J,S:-20
10
20
-5
5
ppml
·C
Si7545
WY'Siliconix
incorporated
~
(5 Volt Operation)
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo = +5 V, VREF = +10 V
VOUT= 0 V, AGND = DGND
SYMBOL
Output Amplifier: OP-07
PARAMETER
LIMITS
1=25°C
2=125,85,70°C
3=-55,-40,0°C
C,L,U
GC, GL,GU
GRADE
A,J, S
B,K,T
GRADE
MIN b
MAXb
MIN b
1
2,3
-0.015
-0.03
0.015
0.03
-0.015
-0.03
0.015
0.03
1
-10
10
-10
10
2,3
C,GC: -50
L,GL: -50
U,GU:-200
50
50
200
A,B: -50
J,K: -50
S,T: -200
50
50
200
TEMP TYpd
MAXb UNIT
ACCURACY (Cont'd)
PSRR
DC Supply Rejection
Output Leakage
Current
IOUT(OFF
~Galn I~ Voo
V oD =±5%
All Digital Inputs = 0 V
%
per
%
nA
DYNAMIC
Current Settling Tlme c
ts
To 0.5 LSB, Load = 100.!1.
f
CEXT= 13 pF, CS = 0 V
Measured From Failing
Edge of WR.
1,2,3
1
1
~s
Propagation Delay C
tpo
Load = 100.n, C EXT = 13 pF f
1
300
300
ns
Dlgltal-to-Analog
Glitch Impulse
Is
VREF= AGND
Output Amplifier: LH0032 f
1
400
nVsec
AC Feedthrough at
OUTg
FT
VREF = ±10 V
10kHz Sinewave
1,2,3
1
mV
p-p
RREF
1
10
RREFTC
1,2,3
-300
REFERENCE
Reference Input
Resistance
(Pin 19 to GND)
RREFTC
7
25
7
25
k.!1.
ppml
°C
OUTPUT
Output Capacltancec
INPUT
COUT
WR = 0 ~I DBO-DBll = 0 V
CS = 0 V DBO-DBll =V oo
70
150
70
150
1,2,3
pF
<
Input HIGH Voltage
VIH
1,2,3
Input LOW Voltage
V IL
1,2,3
Input Current h
liN
Input Capacltancec
e lN
2.4
2.4
V
VIN = 0 V orVoo
VIN=OV
1
2,3
0.8
-1
-10
1
10
O.B
-1
-10
1
10
DBO-DB11
1,2,3
5
5
WR,eS
1,2,3
20
20
~A
pF
6-107
..
Si7545
~
~
(5 Volt Operation)
ELECTRICAL CHARACTERISTICS a
PARAMETER
Siliconix
, incorporated
Test Conditions
Unless Otherwise Specified:
Voo = +5 V, VREF = +10 V
VOUT= 0 V, AGND = DGND
SYMBOL
Output Amplifier: OP-07
LIMITS
1=25°C
2=125,85,70°C
3--55,-40,O°C
c,LLU
GC, G ,GU
GRADE
TEMP TYpd
MIN b
A,J, S
B,K,T
GRADE
MAXb
MIN b
MAXt UNIT
TIMING
Chip Select to Write
Setup Time
tos
Chip Select to Write
Hold Time
tOH
Write Pulse Width
tWR
Data Setup Time
Data Hold Time
See Timing Diagram
Figure 1
1
2,3
200
270
1,2,3
280
380
280
380
0
0
1
2,3
175
280
250
400
250
400
tos
1
2,3
100
150
140
210
140
210
tOH
1,2,3
10
10
Voo
1,2,3
4.5
tos :!: tWR, tOH:!: 0
ns
SUPPLY
Voo Rangel
Supply Current
100
All Digital Inputs
VIH or VIL
1,2,3
All Digital Input
o V or Voo
1
2,3
16.5
16.5
2
2
0.1
0.5
0.1
0.5
V
mA
0.01
0.01
(15 Volt Operation)
ELECTRICAL CHARACTERISTICS a
PARAMETER
4.5
Test Conditions
1=25°C
Unless Otherwise Specified:
2=125,85,70 oC
Voo = +15 V, VREF = +10 V 3=-55,-40,O°C
VOUT= 0 V, AGND = DGND
EMP TYpd
SYMBOL
Output Amplifier: OP-07
LIMITS
C,L,U
GC, GL,GU
GRADE
MIN b
MAXb
A,J, S
B,K,T
GRADE
MIN b
MAXb UNIT
ACCURACY
Resolution
1,2,3
N
Relative Accuracy
(Integral Non-Linearity)
INL
(lLSB = 0.024% of Full Scale) 1,2,3
Differential Nonlinearity
DNL
1,2,3
1
2,3
Gain Errore
GFSE
Measured Using Internal R FB
DAC Register Loaded With:
1111 1111 1111
12
0.5
B,K,T:-l
A,J,S:-2
1
2
-1
1
B,K,T:-l
A,J,S:-4
1
4
-6
-7
C,L,U: -10
6
7
6-108
TCBFS
~ Gain I ~ Temperature
1,2,3
2
-10
LSB
10
1,2,3
Gain Temp Coefflclenf
Bits
-0.5
GC,GL,GU:
GC,GL,GU:
1,2,3
12
10
B,K,T:-15
A,J,S:-25
15
25
-10
10
ppml
°C
Si7545
..,. Siliconix
incorporated
~
(15 Volt Operation)
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
Voo = +15 V, VREF = +10 V
VOUT= 0 V, AGND = DGND
SYMBOL
Output Amplifier: OP-07
LIMITS
1=25'C
2=125,85,70'C
3=-55,-40,O'C
A,J, S
B,K,T
GRADE
C,L,U
GC, GL,GU
GRADE
MIN b
MAXb
MIN b
1
2,3
-0.01
-0.02
0.01
0.02
-0.01
-0.02
0.01
0.02
1
-10
10
-10
10
2,3
C,GC: -50
L,GL: -50
U,GU:-200
50
50
200
A,B: -50
J,K: -50
S,T: -200
50
50
200
TEMP TYpd
MAXb UNIT
ACCURACY (Cont'd)
DC Supply Rejection
Output Leakage
Current
PSRR
AGain Ill. Voo
Voo =±5%
IOUT(OFF)
All Digital Inputs = 0 V
DYNAMIC
%
per
%
nA
,
Current Settling Tlmeo
ts
To 0.5 LSB, Load = 100 n.
f
C EXT = 13 pF, CS = 0 V
Measured From Failing
Edge of WR.
1.2,3
2
2
).Ls
Propagation Delay C
tpo
Load = lOOn., CEXT= 13 pF'
1
250
250
ns
Dlgltal-to-Analog
Glitch Impulse
Is
V REF = AGND
Output Amplifier: LH0032 '
1
250
nVsec
AC Feedthrough at
OUTg
FT
VREF = ±10 V
10kHz Sinewave
1,2,3
1
mV
p-p
RREF
1
10
RREFTC
1,2,3
-300
REFERENCE
Reference Input
Resistance
(Pin 19 to GND)
RREFTC
7
25
7
25
kn.
ppml
'C'
OUTPUT
Output CapacltanceC
C OUT
VA
~I
=0
CS = 0 V
DBO-DBll = 0 V
DBO-DB11 =Voo
70
150
1,2,3
70
150
pF
JNPUT
/ Input HIGH Voltage
V IH
1,2,3
Input LOW Voltage
V IL
1,2,3
Input Current h
liN
13.5
13.5
V
Input Capacltanceo
CIN
VIN = 0 V orVoo
1
2,3
1.5
-1
-10
1
10
1.5
-1
-10
1
10
DBO-DBll
1,2,3
5
5
WR,CS
1,2,3
20
20
VIN=OV
).LA
pF
6-109
•
Si7545
. . . Siliconix
incorporated
~
(15 Volt Operation)
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified
Voo = +15 V, VREF = +10 V
VOUT= 0 V, AGND = DGND
SYMBOL
Output Amplifier: OP-07
LIMITS
1=25·C
2=125,85,70·C
3=-55,-40,0 ·C
c,LLU
GC,G ,GU
GRADE'
TEMP TYpd
MIN b
MAXb
A,J,S
:Fi~iJE
MIN b
MAXb UNIT
TIMING
Chip Select to Write
Setup Time
tes
Chip Select to Write
Hold Time
teH
Write Pulse Width
tWR
Data Setup Time
Data Hold Time
See Timing Diagram
Figure 1
1
2,3
120
150
1,2,3
180
?OO
180
200
0
0
1
2,3
100
170
160
240
160
240
tos
1
2,3
60
80
90
120
90
120
tOH
1,2,3
10
10
Voo
1,2,3
4.5
tes i!: tWR' teH i!: 0
ns
SUPPLY
Voo Rangel
Supply Current
All Digital Inputs
VIH or V IL
1,2,3
All Digital Input
o Vor Voo
1
2,3
16.5
4.5
16.5
2
2
0.1
0.5
0.1
0.5
mA
100
0.01
0.01
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebralo convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. This Includes the effect of 5 ppm max Gain TC.
f. DBO-DB11 = OVtoVooorVooto OV.
g. Feedthrough can be further reduced by connecting the metal lid on the side braze package (Suffix OJ to DGND.
h. LogiC Inputs are MOS gates. Typical Input current (+25 ·C) Is less than 1 nA.
I. Accuracy Is not guaranteed over this range.
6-110
V
~
~
Si7545
Siliconix
incorporated
DIE TOPOGRAPHY
Pad
No.
1--
~
96 mils
18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
:~ 1
19
13
20
88 mils
11
2
10
1
3
4
5
7
6
8
9
2DX
CSAPB
232 P-Channel Enhancement Mosfet
264 N-Channel Enhancement Mosfet
75 Resistors
29 Diodes
1 Bipolar Junction Transistor (NPN)
Function
Out
Analog GND
Digital GND
DBll (MSB)
D B10
D BS
DBB
DB7
D B6
Des
064
DB3
DB2
DBl
~o (LSB)
CS
WR
V DO (Substrate)
V AEF
RFB
TYPICAL CHARACTERISTICS
NONLINEARITY ERROR vs. DIGITAL CODE
1.00
'in
g}
0.75
0.50
0::
0
!2
w
0.25
~
0
i5
z
:::J
z
0
z
I.WIIJII
I'11III1'
~
J.lhill
~m'
••
~ r,m'
.•1,1.
......
III ....
lWItVo\I.
""...
-0.25
TA - +25°C
VOD = +15 V
VREF = +10 V
-0.50
-0.75
-1.00
o
1024
2048
3072
4095
DIGrrAL INPUT CDDE (DECIMA[J
6-111
Si7545
Siliconix
incorporated
H
TYPICAL CHARACTERISTICS (Cont'd)
PSRR vs. FREQUENCY
0.0015
./
0.0012
~
V
I-
m
c.
a:
~
't;
~
0.0009
0.0006
./
./
0.0003
./
oV
o
"
""
. . .V
160
80
./
V
240
320
400
FREQUENCY (Hz)
FEEDTHROUGH ERROR vs. FREQUENCY
12.0
l " - TA +25 ·C
I " - VDD = +15 V
1:
!a:
VREF
= 20 Vpp
I " - INPUT CODE: 0
0
~
w
:J:
V
6.0
If
t!l
::l
0
a:
i!:
0
w
~
-
V
.."
V
i"""'
0.0
1k
10 k
100 k
FREQUENCY (Hz)
WRITE CYCLE TIMING DIAGRAM
~~,-'
____________
~_lc_S___________-<_·~I....·_t~C~H~--I·I~
VOOO
CHIP SELECT
"
/
MODE SELECTION:
WRITE MOOE:
HOLO MOOE:
Os and WR
Ellher
or WR high, dala
bus (OBO-OBll) Is locked oUI:
DAC holds last data present
low, OAC
responds to data bus
~----------
(OBO-OBll) Inputs.
VOO
o
~------- VOO
OATAVALIO
when WR or
high state.
NOTES:
Voo= +5 Vi
OATAIN
(OBO-0811)
Os
CS assumed
t r = t f= 20 ns
VOO= +15 V: I r = I f = 40 ns
All Input signal rise and fall times are measured from 10% to
90% of VOO.
Timing measurement reference level Is (VIH + V IL) 12.
CAUTION
ESD (Electro-Static-Discharge-Sensitive) device.
The digital control inputs are diode protected;
however. permanent damage may occur on
unconnected devices subject to high energy
6-112
electrostatic fields. Unused devices must be stored
in conductive foam or shunts. The protective foam
should be discharged to the destination socket
before devices are removed.
~
~
Si7545
Siliconix
incorporated
DETAILED DESCRIPTION
D/A Converter Section
Figure 1 shows a simplified circuit of the O/A
converter section of the Si7545 and Figure 2 gives
an approximate equivalent circuit. Note that the
ladder termination resistor is connected to AGNO. R
is typically 10 kil.
or negative polarity. (If a current source is used, a
low temperature coefficient external RFB is
recommended to define scale factor.)
to ladder
FROM
INTERFACE
LOGIC
o--j
R
R
AGNO
Figure 2.
OUT
n-channel Current Steering Switch
--~-+~~-oAGNO
r-------c. TO
AGNO
SWITCH
---I-j-,----O OUT
I
b
OBll
(MSB)
RFB
OB10
Figure 1.
OB9
TO OUT
SWITCH
OBO
(LSB)
Simplified D/A Circuit of SI7545
The binary weighted currents are switched between
the OUT bus line and AGNO by n-channel SPOT
analog switches, thus maintaining a constant
current in each ladder leg independent of switch
states.
The capacitance at the OUT bus line, COUT, is code
dependent and varies from 70 pF (all switches to
AGNO) to 150 pF (all switches to OUT).
One of the current switches is shown in Figure 2.
The input resistance at VREF (Figure 1) is always
equal to RREF (RREF is the R-2R ladder
characteristic resistance and is equal to "R").
Since RREF at the VREF pin is constant, the
reference terminal can be driven by a reference
voltage or a reference current ac or dc, of positive
CONTROL
Figure 3.
Digital Input Structure
The input buffers are simple CMOS inverters
designed such that when the Si7545 is operated
with VDD 5 V, the buffers convert TIL input levels
(2.4 V and 0.8 V) into CMOS logic levels. WhenVIN
is in the region of 2.0 to 3.5 V the input buffers
operate in their linear region and draw current from
the power supply. To minimize power supply
currents it is recommended that the digital input
voltages be as close to the supply rails f'/DD and
OGNO) as is practically possible.
=
The Si7545 may be operated with any supply
voltage in the range 4.5 V
-2.0
Figure 7. Voltage Switching Mode
The loading of the reference voltage source is code
dependent and the response time of the circuit is
often determined by the behavior of the reference
voltage to the changing load conditions. Good
results can be obtained by decoupling VREF with a
10 Jl.F tantalum capacitor in parallel with a 0.01 Jl.F
ceramic.
To maintain linearity the voltages at OUT and AGND
should remain within 2.5 volts of each other, for a
VDD of 15 V. If VDD is reduced from 15 V or the
differential voltage between OUT and AGND is
increased to more than 2.5 V, the differential
nonlinearity of the DAC will increase and the
linearity of the DAC will be degraded. Figures 8 and
9 show typical curves illustrating this effect for
various values of reference voltage and VDD. If the
output voltage is required to be offset from ground
by some value, then OUT and AGND may be biased
up. The effect on linearity and differential
nonlinearity will be the same as reducing VDD by the
amount of the offset.
6-116
+5
+10
VREF(V)
Differential NonLinearity vs. VDD for Figure 7 Circuit.
Reference voltage = 15. V. Shaded area shows the
range of values that typically occur for the Land U
grades.
Figure 9.
The circuits of Figures 4, 5 and 6 can all be
converted to single supply operation by biasing
AGND to some voltage between VDD and DGND.
Figure 10 shows the 2's complement bipolar circuit
of Figure 5 modified to give a range from 2 V to 8 V
about a "Pseudo-analog ground" of 5 V.
This voltage range would allow operation from a
simple VDD of 10 V to 15 V. The LM136A-5.0
voltage reference fixes AGND at 5 V. VIN is set at
2 V by means of the series resistors R1 and R2.
There is no need to buffer the VREF input to the
Si7545 with an amplifier because the input
impedance of the DAC is constant. Note however,
that since the temperature coefficient of the
D/ A reference input resistance is typically
-300 ppm/oC, applications which experience wide
temperature variations may require a buffer
amplifier to generate the 2.0 V at the VREF pin.
Other output voltage ranges can be obtained by
Si7545
fr"1I" 8i1iconix
~
incorporated
APPLICATION HINTS (Cont'd)
VDD = +10 V 10 +15 V
Rl
10 k
VOUT
CMOS DATA BUS
VDD = +10 V 10 +15 V
Figure 10. Single Supply "Bipolar" 2's Complement DAC
changing R4 to shift the zero point and (R1 + R2) to
change the slope, or gain of the D/A transfer
function. VDD must be kept at least 4.5 V about OUT
to ensure that linearity is preserved.
MICROPROCESSOR INTERFACING
The 8i7545 can interface directly to either 8- or
16-bit microprocessors via its 12-bit wide data latch
using standard C8 and WR control signals.
A typical interface circuit for an 8-bit processor is
shown in Figure 11. This arrangement uses two
memory addresses, one for the lower 8-bits of data
and one for the upper 4-bits of data into the DAC
via the latch.
Figure 12 shows an alternative approach for use
with 8-bit processors which have a full 16-bit wide
address bus such as 6800, 8080, Z80. This
technique uses the 12 lower address lines of the
processor's address bus to supply data to the
DAC, thus each 8i7545 connected in this way uses
4 k bytes of address locations, Data is written to the
DAC using a single memory write instruction. The
address field of the instruction is organized so that
the lower 12-bits contain the data for the DAC and
the upper 4-bits contain the address of the 4k block
at which the DAC resides.
16-BIT ADDRESS BUS
16-BIT ADDRESS BUS
DBll
080
SI7545
CPU
CPU
WRP------,
WR
'------lOs
P - - - - - - - - - I WR
D7r---------------~,
071-----.1
DOr--=_ _ _8~-~B~IT~D~A~T~A~B~U~S~_ _ _ _- , /
8-BIT DATA BUS
D0r----------------,/
• 00 = DECODED ADDRESS FOR DAC
·00 = DECODED ADDRESS FOR LATCH
Figure 12.
Connecting the SI7545 to an a-Bit
Microprocessor via the Address Bus
Figure 11. a-Bit Processor to SI7545 Interface
6-117
iii
Si7545
.... Siliconix
incorporated
~
PIN DESCRIPTION
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
SYMBOL
Current Output
Analog Ground
Digital Ground
Digital Input (Bit 11 MSB)
Digital Input (Bit 10)
Digital Input (Bit 9)
Digital Input (Bit 8)
Digital Input (Bit 7)
Digital Input (Bit 6)
Digital Input (Bit 5)
Digital Input (Bit 5)
digital Input (Bit 3)
Digital Input (Bit 2)
Digital Input (Bit 1)
Digital Input (Bit 0)
Chip Select Input
Write Input
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
OUT
AGND
DGND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
CS
WR
VDD
VREF
RFB
BURN-IN CIRCUIT
Dual-In-Llne Packages
+15 V
+5 V
Note: All Resistors are 1 k
6-118
n
unless otherwise specified
Si7545
.... Siliconix
incorporated
~
BURN-IN CIRCUIT (Cont'd)
PLCC Package
.
3 2111112cJ\1
/
9\\11:1\11\\12\\1
+15 V
Note: All resistors are 1 k!l unless otherwise specified
6-119
Si7820
CMOS Subranging
8-Bit AID Converter
.,.. Siliconlx
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Fast Conversion Time
1 .34 I1s Maximum
• Increased Data Throughput
• Digital Signal Processing
• No Accuracy Trims
Required
• High Speed Data Acquisition
• Single +5 V Supply
• Simplified Power Supply
Requirements
• I1P Controlled Servos
eOn-Board I1P Interface
o Simplified I1P Interface
• 1/2 LSB Total Unadjusted
Error
• 5 Volt Systems
DESCRIPTIOtJ
The 8i7820 is a high speed, microprocessor
compatible, 8-bit analog-to-digital converter which
uses a subranging (half-flash) technique to achieve
a conversion time of 1.34 I1s. The converter has a
V to +5 V analog input range and uses a single
+5 V supply.
o
Applications include high speed data acquisition,
real-time digital signal processing, FAX communications systems, oversampled audio digitizing, and
digital servo systems such as head positioning for
disk drives.
The SI7820 will easily interface with microprocessors by appearing as a memory location or 1/0 port
without the need for external interfacing logic. The
data outputs use latched, three-state buffers to
allow direct connection to a microprocessor data
bus or system input port. An over-flow output is
provided for cascading devices to achieve higher
resolution. The Si7820 is pin compatible with the
industry-standard AD7820 and ADC0820 devices.
The Si7820 is built using the Siliconix proprietary
PolyMOS process, allowing a mix of high density
fast digital logic with high performance analog
ciruitry. An epitaxial layer prevents latchup. It is
available in the 20-pin PDIP and PLCC-20 for
operation over the commercial K, L suffix (0 to
70°C), 20-pin CerDIP for industrial, B, C suffix (-40
to 85°C) temperature range, and for military, T, U
suffix (-55 to 125°C) temperature operation.
PIN CONFIGURATION
Dual-In-Llne Package
PLCC Package
Top View
Top View
, .
V DD
D~
N/C
OFL
7 DB7(MSB)
DBS
-----....--~
Order Number:
SI7820
6-120
_
DB4
MO~ ~
RD
+
REF-
N/C
DB3 ~
WR/RDY ~
REF
v DD
311 211111201119
DB2 ~
DBS
Cs
DBO V IN
B
91110111111121113
INT GNDREF REF
ps
Order Number:
SI7820
Preliminary
Si7820
..". Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
OBO- 08r
OATAOUT
PIN~!!175,
16
WR/ROY
ORDERING INFORMATION
PART
TEMP. RANGE
PACKAGE*
ERROR
Si7820KP
o to 70°C
o to 70°C
o to 70°C
o to 70°C
Si7820CQ
-40 to 85°C
CerDIP
+1/2 LSB
Si7820BQ
-40 to 85°C
CerDIP
+1 LSB
Si7820UQ
-55 to 125°C
CerDIP
+1/2 LSB
Si7820TQ
-55 to 125°C
CerDIP
+1 LSB
Si7820LN
Si7820KN
Si7820LP
Plastic DIP
+1/2 LSB
Plastic DIP
+1 LSB
PLCC
PLCC
+1/2 LSB
+1 LSB
• All devices -- 20 lead packages .
•• Consult factory for dice specifications.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Voo to GND ....•............ 0 V, 10 V
Voltage at any other pins
(Pins 1-9, 11-18) ............. GND -0.3 V, VOO +0.3 V
Operating Temperature Ranges
SI7820LN/KN/LP/KP ........................ 0 to 70·C
SI7820BQ/CQ ............................ -40 to 85·C
SI7820TQ/UQ ........................... -55 to 125·C
Storage Temperature Range .......•.•.... -65 to 160·C
Power Dissipation (Any Package) to 75·C .. ' ... 450 mW
Derate Above 75·C by .....•.....•.....•..... 6mW/·C
Preliminary
Lead Temperature (Soldering 10 seconds) ....•... 300·C
6-121
Si7820
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Voo = 5 V, V REF+= 5 V
VREF-= a V, RD-Mode
GND = a V
LIMITS
1=25·C
T, U
2=125,85,70·C
SUFFIX
3=-55,-40,0 ·c -55 to 125·C
TEMP
TYpd
B, C, K, L
SUFFIX
MIN b MAXb MIN b MA>f UNIT
ACCURACY
Resolution
No Missing Codes
1,2,3
8
L, C, U Grades
1,2,3
_1/_
1/_
-1/_
'/_
B, K, T Grades
1,2,3
-1
1
-1
1
1.4
1.25
4.0
4.0
1.4
1.25
4.0
4.0
8
Bits
LSB
Total Unadjusted Error e
REFERENCE INPUT
Reference Input Resistance
1
2,3
RIN
2.2
VREF+ Input Voltage Range
1,2,3
a
5.1
a
5.1
VREF- Input Voltage Range
1,2,3
-0.1
5.1
-0.1
5.1
-0.1
5.1
-0.1
5.1
kCl
V
ANALOG INPUT
Analog Input Range,
VINR
1,2,3
Analog Input Capacitance
C YIN
1
Analog Input Current
Slew Rate!
I YIN
VIN =
a V to 5 V
SR
45
1
2,3
1
V
pF
-0.3
-3
0.2
0.3
3
-0.3
-3
0.1
0.3
3
~A
0.1
V/~s
LOGIC INPUTS
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
-CS, WR, RD Inputs
1,2,3
2.4
2.4
Mode. Input
1,2,3
3.5
3.5
-CS, WR,RD Inputs
1,2,3
0.8
0.8
Mode Input
1,2,3
1.5
1.5
-CS, RD
- Inputs
1
2,3
0.3
1.0
0.3
1.0
1
2,3
0.3
3.0
0.3
3.0
150
200
150
200
VINH
V INL
IINH
-WR
Input
Mode Input
6-122
V
1
2,3
50
~A
Preliminary
..or Siliconix
~
Si7820
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
T, U
2=125,85,70·C
Voo = 5 V, VREF+= 5 V
SUFFIX
3=-55,-40,0 ·C -55 to 125·C
VREF-= 0 V, RD-Mode
PARAMETER
SYMBOL
GND = 0 V
TEMP
TYpd
B,C, K,L
SUFFIX
MIN b MAXb MIN b MAX' UNIT
LOGIC INPUTS (Cont'd)
Input LOW Current
IINL
Input CapacltanceC
C IN
-CS, WR, RD Mode Inputs
1
2,3
1,2,3
-0.3
-1.0
-0.3
-1.0
B
5
J.lA
B
pF
LOGIC OUTPUTS
Output HIGH Voltage
DBO-DB7, OFL, INT Output
Voo= 4.75 V
Output LOW Voltage
DBO-DB7, OFL, INT RDY
lOUT = -360 J.lA
1,2,3
4.0
4.0
lOUT = -10J.lA
1,2,3
4.5
4.5
lOUT = 1.6 mA
1,2,3
VOH
VOL
0.4
-0.3
-3.0
1
2,3
Three-State Current
DBO-DB7, RDY
0.3
3.0
V
0.4
-0.3
-3.0
Output Source Current
DBO-DB7, OFL, INT
ISRO
VOUT= 0
1,2,3
-25
-10
-10
Output Sink Current
DBO-DB7, OFL, INT RDY
I SINK
VOUT=VOO
1,2,3
40
15
15
Output CapacltanceC
DBO-DB7, OFL, INT RDY
COUT
1,2,3
5
0.3
3.0
J.lA
mA
8
8
pF
5.25
V
10
15
mA
POWER SUPPLY
Supply Voltage
Voo
Supply Current
100
5 V ±5% for
Specified Performance
1,2,3
4.75
1
2,3
5
1
25
1,2,3
±'/'8
5.25
4.75
10
15
CS= WR =RD = 0
Power Dissipation
Power Supply Sensitivity
PSS
Voo=5V±5%
mW
-'I.
'/.
-'I.
'I.
LSB
TIMINGt,g
-CS
-
-CS
to RDY Delay
to RD, WR
Setup Timing
tess
1,2,3
0
0
to RD, WR
Hold Time
--
tesH
1,2,3
0
0
-CS
-
tROY
Conversion Time
(RD Mode)
tORO
Preliminary
CL= 50 pF, R = 3 k.[l.
ns
1
2,3
35
70
100
70
90
1
2,3
1.2
1.6
2.5
1.6
2.0
J.ls
6-123
Si7820
..... Siliconix
.1;11 incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified: 1=25·C
2=125,85,70·C
Voo = 5 V, VREF+= 5 V
3=-66,-40,0 ·C
VREF-= 0 V, RD-Mode
PARAMETER
SYMBOL
GND = 0 V
TEMP
TVpd
LIMITS
T, U
SUFFIX
-66 to 126·C
MIN b
MAXb
B, C, K, L
SUFFIX
MIN b
MAX' UNIT
TIMING f,9 (Cont'd)
Data Access Tlmeh
(RD Mode)
tACCO
See Figure 4
1
2,3
tCRo+10
tCRo+20
tCRo+50
tCRo+20
tCRo+35
RD to INT Delay
(RD Mode)
tlNTH
C L = 50 pF
1
2,3
60
125
225
125
175
Data Hold Tlme l
tOH
1
2,3
40
60
100
60
80
tp
1
2,3
500
600
Write Pulse Width
tWR
1,2,3
0.6
Conversion Time
(WR IRD Mode)
tCWR-RO
1
2,3
1.34
1.53
1.34
1.50
Delay Be~een
WR and RD Pulses
tRO
1
2,3
600
700
600
700
Data Access Time
(WR/RD Mode)h
tACC1
ns
Delay Time Between
Conversions
500
600
50
0.6
50
j.l.s
tRO < tlNTL
See Figure 6
1
2,3
110
160
250
160
225
RD to INT Delay
tRI
1
2,3
100
140
225
140
200
WR to INT Delay
tlNTL
1
2,3
600
1000
1700
1000
1400
Data Access Time
(WR/RD Mode)h
tACC2
tRO> tlNTL
See Figure 5
1
2,3
60
70
110
70
90
WR to INT Delay
(Stand-Alone)
tlHWR
CL= 50 pF
1
2,3
70
100
150
100
130
10
50
75
50
65
Data Access Time
After INT
tiD
ns
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Total unadjusted error Includes offset, full-scale and linearity errors.
f. Sample tested at 25"C to ensure compliance.
g. All Input control signals are specified with t R = t F = 20 ns (10% to 90% of 5 V).
h. Measured with load circuits of Figure 1 and defined as the time required for an output to cross O.B V or 2.4 V.
I Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
6-124
Preliminary
Si7820
.... SlIIconix
incorporated
~
SWITCHING TIME TEST CIRCUITS
DBN •
3~I I
DBN3k.n.
Il00PF
'1
•
I10PF
-=- DGND-=A. VOH to HIGH-Z
-=- DGND-=A. HIGH-Z toVOH
1
+5 V
3k.n.
3 k.n.
DBN •
II
-
DBN .---------~------~
I100PF
10PF
I
-=- DGND
B,VOL to HIGH-Z
-=- DGND
B. HIGH-Z to VOL
Figure 1. Load Circuits for Data Access Time Test
Figure 2. Load Circuits for Data Hold Time Test
CAUTION
Stresses above those listed under " Absolute
Maximum Ratings" may cause permanent damage
to the device. These are stress ratings only, and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of the specification is not
implied. Exposure to absolute maximum ratings
conditions for extended periods may affect the
device reliability.
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
DESCRIPTION
VIN
DBO
Three-state data output, bit 0 (LSB).
3
DB1
Three-state data output, bit 1.
4
DB2
Three-state data output, bit 2.
5
DB3
Three-state data output, bit 3.
6
7
WR/RDY
WRITE control input/READY status output. See Digital Interlace section.
MODE
Mode selection input. This input is internally pulled low with a
50 jl.A current source.
RD Mode: MODE low/open.
WR-RD Mode: MODE high.
1
2
Analog input; range = GND < VIN < VDD.
8
READ input. RD must be low to access data. See Digital Interlace section.
9
INTERRUPT output. INT going low indicates the completion of a conversion.
See Digital Interface section.
10
Ground.
11
Lower limit of reference span. Sets the zero code voltage.
Range: GND to VREF+.
Preliminary
6-125
Si7820
~
~
Siliconix
incorporated
PIN DESCRIPTION (Cont'd)
PIN
NUMBER
SYMBOL
DESCRIPTION
12
VREF+
Upper limit of reference span. Sets the Full Scale Input voltage.
Range: VREF- to Voo.
13
CS
CHIP-SELECT input. CS must be low for the device to recognize
WR or RD inputs.
14
DB4
Three-state data output, bit 4.
15
DB5
Three-state data output, bit 5.
16
DB6
Three-state data output, bit 6.
17
DB7
Three-state data output, bit 7 (MSB).
18
OFL
Overflow Output. If the analog input is greater than VREF+,
OFL will be high at the end of the conversion. It can be used to
cascade two or more devices to increase resolution.
19
NC
No Connection.
Voo
Power supply voltage, +5 V.
20
DETAILED DESCRIPTION
Converter Operation
The Si7820 uses a "half-flash" conversion
technique (see Functional Block Diagram). Two
4-bit flash AID converter sections are used to
achieve an 8-bit result. Using 15 comparators, the
upper 4-bit MS (most significant) flash AID
compares the unknown Input voltage to the
reference ladder and provides the upper four data
bits.
An internal DAC uses the MS bits to generate the
analog result from the first flash conversion, and
generates a residue voltage which is the difference
of the unknown input and the DAC voltage. The
residue Is then compared to the reference ladder
using 15 LS (least significant) flash comparators to
obtain the lower four bits of the output. An
additional overrange comparator detects if the
analog Input is greater than the reference voltage.
Operating Sequence
The operating sequence for the WR-RD Mode is
shown In Figure 3. The conversion is initiated by a
falling edge of WR. The comparator inputs track the
analog input voltage for the duration of WR low. A
minimum of 600 ns is re~ed for the input voltage
to be acquired. When WR returns high, the MS
flash result is latched into the output buffers and the
LS conversion begins. INT goes low approximately
6-126
600 ns later, indicating end of conversion, and that
the lower 4 data bits are latched into the output
buffers. RD going low then accesses the data.
iN'r GOING LOW
500n /
SET UP TIME REQUIRED
1
6
~6J~~~~t~~~A~RIOR TO
STARTING CONVERSION
.
VIN IS TRACKED
BY INTERNAL
COMPARATORS
n
60 n \
INDICATES THAT
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
VIN IS SAMPLED>'-+"'-"-AND THE MSB·S
ARE LATCHED
Ro BROUGHT LOW HERE LATCHES
THE 4 LSBS AND ACCESSES
DATA ON DBa - DB 7
Figure 3. Operating Sequence (WR-RO Mode)
If an externally controlled conversion time is
required, the RD line can be brought low as soon as
600 ns after WR goes high. This will latch the lower
4 data bits and output the conversion result on
DBO-DB7. At least 500 ns setup time is required
from INT ~g low to the start of another
conversion (WR going low).
Preliminary
Si7820
Ir'Il'" Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
Digital Interface
The Si7820 has two basic interface modes which
are set by the status of the MODE input pin. When
this pin is low, the converter is in the RD mode,
when this pin is high the converter is set up for the
WR-RD mode.
RD Mode
In RD mode, conversion control and data access is
controlled by the RD input (s~ Figur~4). The
conversion is initiated by taking RD low. RD is then
kept low until output data appears. This mode is
useful for microprocessors which can be forced
into a WAIT state. The processor can start a
conversion, wait, and then read data with a single
READ instruction.
conversion is initiated on the falling edge of WR.
Several options exist for reading the data from the
converter.
Using Internal Delay
!!!...!he first of these options the processor waits for
INT output...!2.. go low before reading the data
(Figure 5). INT typically goes low 600 ns after the
rising edge of WR, indicating that the conversion is
complete and the result is available in the output
latch. With CS low, data outputs DBO-DB7 can be
accessed by pulling RD low. INT is then reset by the
rising edge of CS or RD.
Pin 6 (WR IRDY) is configured as a status output
(RDY) in RD mode. This output can be used to drive
the READ or WAIT input of a processor. ROY is an
open drain output (with no internal pull-up device)
which goes low after the falling edge of CS and
goes high impedance at the end of the conversion.
An INT output is also provided which goes low at
the end of the conversion and returns high on the
rising edge of CS or RD.
os
\
'--AD
\.-
Figure 5. WR-RD Mode Timing ( tRD
> tlNTL )
Reading Before Delay
DBO- DB7
Figure 4. RD Mode Timing
WR-RD Mode
In the WR-RO mode, pin 6 (WR/ROY) is configured
as the WRITE input for the converter. With CS low, a
Preliminary
An alternative option can be used to externally
control the conversion time (see Figure 6). The
internally generated 600 ns delay varies somewhat
with temperature and supply voltage (see Typical
Operating Characteristics) and can be overridden
with RD. To ~chieve this, the status of INT is
ignored and RO is broug~w as soon as 600 ns
after the rising edge of WR. This completes the
conversion and enables the output buffers,
DBO-DB7, which contain the conversion ~ult. INT
also goes low after the falling edge of RD and is
reset on the rising edge of RD or CS.
6-127
Si7820
fIlY' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
~
_ _ _---L_ _ _ _ _ _
tp
and a conversion is initiated by pulling WS low.
Output data is ~alid approximately 600 ns after the
rising edge of WR.
--It\......./
INT----~
DBO- DB7
Figure 6. WR-RD Mode Timing ( tRD > tlNTL )
Pipelined Operation
In addition to the two standard WR-RD mode
options, • pipe-lined· operation can be achieved by
tying WR and RD together (see Figure 7). With CS
low, WR and RD going low initiates a conversion,
and reads the result of the previous conversion at
the same time.
~}----
)-
DBO- DB7
Figure 8. WR-RD Mode Stand-Alone Timing CS
= RD = 0
Analog Considerat!ons
The VREF+ and VREF- input set the full-scale and
zero input voltages of the AID. In other words, the
voltage at VREF- defines the input which produces
an output code of all zeroes and the voltage at
VREF+ defines the input which produces an output
code of all ones (see Figure 9).
OUTPUT
CODE
+
l1111111T
11111110"t
11111101+
I
I
I
I
I
00000011 "t
00000010+
00000001
Figure 7. WR-RD Mode Pipe-Lined Timing WR = RD
Stand·Alone Operation
The converter can also be used in a stand-alone
operation (see Figure 8). CS and RD are tied low
6-128
.+
V REF (+)
I
+ -+ -)- - - - - --I-I-~'"
FS
V IN INPUT VOLTAGE
(IN TERMS OF LSB's)
FS - lLSB
Figure 9. Transfer Function
Preliminary
frl!' Siliconix
~
Si7820
incorporated
DETAILED DESCRIPTION (Cont'd)
VIN(+)
VIN
GNO
GND
+5V
VDD
SI7820
II
o-.--.......- ......----::-:-:~ voo
SI7820
~V\f\r....--t VREF(+)
VREF(+)
11
+5V
VREF(-)
-=-
W
Figure 10a. Power Supply as Reference
Current path must
stili exist from
VIN(_) to GND.
Figure 10b. Input Not Referenced to GND
0 - -....--"'"1 GND
+5 v 0-.---......- -.......---""'1 vOD
SI7820
VREF(+)
'--.....-'-'-1 VREF(-)
Figure 100. External Reference 2.5 V Full-Scale
Preliminary
6-129
Si8601/8603
..... Siliconix
incorporated
~
8-Bit Data Acquisition Systems
FEATURES
BENEFITS
APPLICATIONS
• Total Unadjusted Error
< 1/2 LSB (Si8603)
• Eliminates External Trims
• J.lP fPC-Based Data
Acquisition Systems
• Fast Conversion Time
(25 J.ls maximum)
• Reduced System Power
Consumption
• Low Power (2.5 mW)
• Reduced Aperture Error
• Audio Digitizing
• ElimInates Additional
Supplies
• Remote Data Acquisition
fi
• Increased Data Throughput
On-Chip S/H Function
• On-Board 8-Channel
Multiplexer (Si8601)
• Microprocessor Interface
• Voice/Telecom Systems
• Battery-Operated Systems
• High Density Systems
• Reduced Board Space and
Component Count
DESCRIPTION
The Si8601 and Si86Q3 are 8-bit data acquisition
systems which include an A/D converter,
sample-and-hold function, and a microprocessor
interface on one monolithic chip. The Si8603 is a
single-cl1annel version, while the Si8601 includes an
on-board 8-channel analog multiplexer and decode
logic to form a complete 8-channel data acquisition
system. The Si8601 and Si8603 are designed for
5 V single-supply operation and TTL-level logic
interfacing. For 15 V operation, refer to the
Si8602/8q04 data sheet.
Built in the Siliconix proprietary PolyMOS T. process,
the Si8601/8603 use a capacitive-ladder AID
conversion technique to achieve low power, high
speed and less than 1/2 LSB total unadjusted error
without the need for thin film resistors or laser
trimming. The capacitive ladder architecture
creates an on-board sample/hold function,
reducing the aperture time of the converter to less
than 90 ns. This facilitates digitizing rapidly-slewing
analog signals with a minimum of error.
An
epitaxial layer prevents latchup.
The total unadjusted error specification of 1/2 LSB
(Si8603) eliminates the need for any external trims
or adjustments, further reducIng system cost and
enhancing overall reliability.
The Si8601 is available in 28-pin plastic and ceramic
DIP. The Si8603 is available in 16-pin plastic and
ceramic DIP. Both are available in industrial, D suffix
(-40 to 85°C) and military, A suffix (-55 to 125°C)
temperature ranges and in /883 versions as well.
For surface mount applications, the Si8601 is
available in tl')e PLCC-28. and the Si8603 in the
PLCC-20. For more information on the Si8601,
please refer to Siliconix application Note AN83-13.
PIN CONFIGURATION
PLCC-20 Package
o V
Dual-In-Llne Package
07
05
03
01
Top View
Order Numbers:
CerDIP: SI8603DJ
PlastIc: S18603AK, SI8603DK
6-130
°
LON S
K 00 0 7
so
3112 1112011191
~
~
~
~8
•
"
~
~
Top View
~
~
91110111111121113
o
G N I R
E NON E
°
F
+
Order Number:
SI8603DN
Si8601/8603
W'F Siliconix
~
incorporated
PIN CONFIGURATION (Cont'd)
Dual-In-Llne Package
PLCC-28 Package
eVG
1411
~ ~ (MSB)
?II'II?BI?7II?61
~
02 5
4 03
Order Numbers:
~II
/
05
Eoe
REF+
CerDIP:SI8601AK
SI8601DK
Plastic: SI8601DJ
Rg ~
~ ~
GNO
se
0 7 (MSB)
(LSB) DO ~
OE ~
~
REF- ~
i
§!
INl 9
IN2
IN3
~
~
'f.
05
03
0,
Eoe
REF+
ALe
AO
12111jI14111E111E111711181
I I I I I A A
NNNNN21
4
Top
5 6
7 8
View
Order Number:
SI8601DN
Top
View
FUNCTIONAL BLOCK DIAGRAM
r------------------,I
B
ANALOG
INPUTS
I
I
I
I
ADDRESS LOAD CONTROL
AID
B
OUTPUTS
CONVERTER
TIMING
LOGIC
I
CLK
I
L __________________
Si8601 ONLY
I
~
ABSOLUTE MAXIMUM RATINGS
Reference Input Voltage Range,
VREF- ............................... -0.3 V to VREF+
Reference Input Voltage Range, VREF+
•...••..•.••.••.•...•.•••.•...... VREF- to Vee +0.3 V
Supply Voltage, Vee .•..•••.•......•............ 6.5 V
Input Voltage Range, All Inputs .... -0.3 V to Vee +0.3 V
Storage Temperature (K Suffix) ..•....... -65 to 150°C
(J, N Suffix) •••.•.. -65 to 150°C
Operating Temperature (A Suffix) ....••... -55 to 125°C
(0 Suffix) ....••.... -40 to 85°C
Power
28-Pln
16-Pln
28-Pln
16-Pln
28-Pln
20-Pln
Dissipation (Package)'
Ceramic DIP" . . . . . . . . . . . . . . . . . . . . . .. 1046
Ceramic DIP'" ••......••••.......•.. 900
Plastic Dip···· •.•.•......•••..•..... 1046
Plastic Dip····· ...................... 900
PLCC····· .••••..•.....•.........••. 900
PLCC····· ............ "............ 900
mW
mW
mW
mW
mW
mW
All leads welded or soldered on PC Board.
Derate 6.5 mW/oC above 25°C.
Derate 12 mW/oC above 75°C.
Derate 6.5 mW/oC above 25°C.
Derate 12 mW/oC above 75°C.
6-131
Si8601/8603
...... Siliconix
,,6;11 incorporated
ELECTRICAL CHARACTERISTICS a, rn, n
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
Vcc = 5 V
f CLOCK = 1.04 MHz
LIMITS
1=25 ·C
All
2=125,85·C
Grades
3=-55,-40· C
TEMP
TYP
d
MIN b MAXb
UNIT
INPUT
Input Channel ON State
CurrentS
JJ.A
VIN = 2.5 V
1
VIN=SV
1
VIN = 0 V
1
VIN=SV
2,3
VIN =OV
2,3
-1000
VANALOG
1,2,3
VREF-
High Level Input Voltage
V IH
1,2,3
V c c-1.S
Low Level Input Voltage
VIL
1,2,3
l.S
High Level Input Current f
IIH
VIN=SV
1,2,3
1
Low Level Input Current f
IlL
VIN = 0 V
1,2,3
-1
1,2,3
4
Input Channel OFF State
Current f
Analog Input Voltage9
10N(PEAK)
-5
200
-200
nA
I OFF
1000
VREF+
V
JJ.A
OUTPUT
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
OFF State Output Current q
10 = -360).LA
Data
Outputs
1,2,3
0.4
End Of
Conversion
1,2,3
0.4
VREF = S V
1,2,3
1
VBUS= 0 V
1,2,3
V
10=1.6rnA
JJ.A
los
-1
SUPPLY
Supply Current h
Supply Current Plus
Reference Current h
Supply Voltage l, c
6-132
Icc
VREF+ Is open, VREF- = 0 V
VIL = 0 V, V IH = S V
1
2,3
Icc+ IREF
Vcc= S V
V IL = 0 V, VIH = S V
1
Vcc
Refer to 'Operatlng Range" Graph
1,2,3
10
10
3
SO
200
JJ.A
1
rnA
6.S
V
~
~
Si8601/8603
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a, m, n
Test Conditions
Unless Otherwise Specified:
LIMITS
1=25 ·C
2=125,85 ·C
3=-55, -40 • C
All
Grades
SYMBOL
Vcc= 5 V
f CLOCK = 1.04 MHz
TEMP
Positive R~ference
Voltage g,
VREF+
Refer to "Operating Range" Graph
1
3c
Vcc
Negative Reference
Voltage g, c
VREF-
1
a
0.3 c
Voltage BetweenVc c
and VREF+ Terminals I
VccVREF+
PARAMETER
TYP d
MIN b MAXb
UNIT
SUPPLV (Cont'd)
Refer to "Operating Range" Graph
1
a
V
DYNAMIC
Control Input Capacitance
C1
1,2,3
2.5
Data Output Capacitance
Co
1,2,3
5.5
Supply Voltage Sensitivity
PSR
1,2,3
0.05
Zero Error J
ZE
1,2,3
0.25
Linearity Error J
INL
1,2,3
0.25
0.25
pF
Vcc = 4.75 V & 5.25 V
fCLOCK = 1.04 MHz
Total Unadjusted Error J
E TOT
1
2,3
Differential Nonlinearity
DNL
1,2,3
%IV
-0.50
-0.75
0.50
0.75
-0.5
0.5
LSB
TIMING
Vcc = 3 V
Clock Frequency I
100
kHz
fCLOCK
Vcc = 5 V
1,2,3
1040
Start Pulse Width
tsc
1
100
Address Load Control
Pulse Width
tALC
1
200
Address Set Up Time
tsu
1
50
Address Hold Time
tH
1
50
Input Voltage Stable I
tiS
1
8
ns
SI86010NLY
Clock
Periods
6-133
Si8601/8603
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a, m, n
PARAMETER
SYMBOL.
Test Conditions
Unless Otherwise Specified:
Vcc= 4.75 V to 5.25 V
VREF+ = V cc , VREF- = 0 V
fCLOCK = 1.04 MHz
LIMITS
1=25 ·C
2=125,85 ·C
3=-55,-40· C
TEMP
TYP
All
Grades
d
MIN b MAXb
UNIT
TIMING (Cont'd)
End of Conversion
Delay Time
tDEC
Conversion Time k
tCONV
f CLOCK = 1.04 MHz
tsc=100ns
1,2,3
Output Enable Time
tOE
C L = 50 pF
1
100
250
Output Disable Time
too
CL= 10 pF
RL= 10 kfi
1
100
250
1
0
200
ns
25
.Ils
ns
NOTES:
a. Refer to PROCESS OPTION FL.OWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONL.Y, not guaranteed nor subject to production testing.
e. Decays exponentially during first clock high period.
f. Channel addressed with clock OFF.
g. Analog Input voltage greater than V REF+ converts as all ones and less than VREF- as all zeros.
h. Current Increases linearly with frequency of the clock at a rate of approximately 10% per 100 kHz.
I. For proper operation the maximum clock rate must be lowered as the voltage across the reference terminals
Is lowered below 4.75 V. The maximum clock rate must be lowered by 0.68 fCLOCKlvolt multiplication factor.
VREF+ must be above 3.0 V or Vcc - 1.0 V, whichever Is higher.
J. All errors are measured with reference to an Ideal straight-line transfer curve from 1/2 L.SB to ( Vec - 1/2 L.SB).
k. Source resistance < 1 kfi .
m. All voltage values are with respect to ground terminal.
n. All dc parameters are 100% tested at 25 oC. L.ots are sample tested for ac parameters and high and low temperature
limits to assure conformance with specifications.
q. Veus Is the voltage applied to the output pins when the digital outputs are In OFF state.
DIE TOPOGRAPHY
11
Pad Function
No.
12
13
Si8601
114 mils
27
18 19
20 21 22 23 24 25 26
CSAD
493 P-Channel Enhancement MOSFETs
477 N-Channel Enhancement MOSFETs
6-134
20X
13 Capacitors
7 Resistors
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vcc
CL.K
D6
D4
D2
Do
OE
REFIN1
IN2
IN3
IN4
INs
INs
Pad Function
No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IN7
INa
A2
A1
Ao
AL.C
REF+
EOC
D1
D3
Ds
D7
SC
GND
Si8601/8603
.... Siliconix
incorporated
~
DIE TOPOGRAPHY (Cont'd)
Si8603
1...........- 6 - - - - -123 mlls-5--4--3--··~ 1
Pad
No.
7
1
2
3
4
5
6
114 mils
B
9
10
16
7
B
9
10
11
12
13
14
15
16
Function
Vee
ClK
06
04
02
Do
OE
GNO
IN
REF+
EOC
01
03
05
07
SC
~::::~::11::::::::::::~12::1:3~1:4::1::5::~
20X
CSSD
13 Capacitors
7 Resistors
425 P-Channel Enhancement MOSFETs
409 N-Channel Enhancement MOSFETs
OPERATING RANGE OF VREF+
~
w
6
t!J
Z
~
t!J
z
5
Guaranteed Test Points
~
W
!l..
CJ
4
t
>
L..
3
3
5
4
Vee
6
(V)
6-135
Si8601/8603
...... Siliconix
incorporated
~
TIMING
CLOCK
Sl8601
'Only
I
START
SEE DETAIL A
ALC
SEE DETAIL A
ADDRESS
ANALOG IN
H
___ __________________________________
~
==::x
SEE DETAIL A
Sf
~:ff
f-----y---Hf-----
I~~---------------tl-s------------~~~s
r-
- - - , SEE DETAIL A
sf------J
!
EOC
tCONV
----------~~I
OLrrPUTCONTROL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--irff--___~
~TCHOLrrPUTS
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~rS-E-E-D-ET-Al-L-B~1~
Sf
DETAIL. A
START _ _ _ _ _ _ _ _ _ _ _J1~50%
.
;%~
t8C-+I·---------
I
EOC
SI8601
Only
I
60%}~___________
I+-tDEC-+t
ADDRESS
DETAIL.B
OUTPLrr CONTROL
==x
I..
1
f,...t-60-%----
ALC ________
'---- ---+lb}..1
r
60%Xr--------------tALC
60%
I.-
tH
1
I
~ts~
_ ________________~~150%
~1
.
500/,,,------
C :=rf.
90
1 1%
-------+1-<·
~TCHED OLrrPLrrS - - - - - - -__
HI Z STATE
1
~
1~10%
tOE
I 1
--I
0
%
~%
too
DETAILED DESCRIPTION
PRINCIPLES OF OPERATION
Si8601 with On-chip Eight Channel MUX:
The analog multiplexer selects 1 of 8 single-ended
input channels as determined by the input address
code. The Address Load Control (ALC) transfers
and latches the code into the address decoder on
the positive edge of the ALC signal. The output
latch is reset by the positive edge of the Start
6-136
Conversion (SC) pulse. Sampling starts with the
positive edge of the SC pulse and lasts for 8 clock
periods from its falling edge. The conversion
process can be interrupted by a new SC pulse
before the end of 24 clock periods. Continuous
conversion may be accomplished by connecting
the End of Conversion (EOC) output to the start
input. If used in this mode an external pulse should
be applied after power up to assure start up.
Si8601/8603
tI7' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
begins identifying bits by identifying the charge on
each capacitor relative to the reference voltage. In
the switching sequence, all eight capacitors are
examined separately until all 8 bits are identified,
and then the charge-convert sequence is repeated.
In the first step of the conversion phase, the
cqmparator looks at the first capacitor (binary
weight = 128). One pole of this capacitor is
switched to the reference voltage, and the
equivalent poles of all the other capacitors on the
ladder are switched to ground. If the voltage at the
summing node is grater than the trip-point of the
comparator (approximately one-half the reference
voltage), a bit is placed in the output register, and
the 128-weight capacitor is switched to ground. If
the voltage at the summing node is less than the
trip-point of the comparator, this 128-weight
capacitor remains connected to the reference input
through the remainder of the capacitor-sampling
(bit-counting) process. The process is repeated for
the 64-weight capacitor, the 32-weight capacitor,
and so forth down the line, until all bits are tested.
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS
A2 A1 Ao
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
ADDRESS LOAD
CONTROL
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
1
1
1
1
to
to
to
to
to
to
to
to
SELECTED
ANALOG
CHANNEL
1
2
3
4
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
5
6
7
8
SWITCHED CAPACITOR AID CONVERTER
The CMOS comparator in the (SAR) successive-approximation system determines each bit by examining the charge on a series of binary-weighted
capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by
closing switch SC and all ST switches, and by
simultaneously charging all the capacitors to the
input voltage.
As can be seen, with each step of the capacitorsampling process, the initial charge is redistributed
among the capacitors. The conversion process is
successive-approximation, but relies on charge
shifting rather than the traditional successiveapproximation register and reference DfA to count
and weigh the bits from MSB to LSB.
In the next phase of the conversion process, all ST
and SC switches are opened and the comparator
128
64
32
16
4
2
rrrrrrrrr
-
-
-
-
Figure 1.
-
-
Simplified Successive Approximation Register
6-137
Si8601/8603
. . . Siliconix
incorporated
~
DETAILED DESCRIPTION (Cant'd)
VREF(+)
2.6k
INx
I~4
58 pF
o------t\i\i\,-t---..--.. . . . .
faOO4
I
Figure 2.
28.8 pF
I
28.8 pF
Equivalent Input Impedances
APPLICATIONS
The Si8601 and Si8603 are CMOS Converters using
charge redistribution to achieve AID conversion.
This
allows
ratiometric
conversion.
In
a
single-supply system, VREF- will be connected to
ground and VREF+ will be connected to Vee. The
output will then be a simple proportional ratio
between analog input voltage and Vee (Figure 3).
The general relationship is:
(VREF+) - (VREF-)
Digital Output
Analog Input
Positive Reference Potential
Negative Reference Potential
Where DOUT
VIN
VREF+
VREF-
TRANSFER
FUNCTION
BINARY
OUTPllT
CODE
11111111
vcc
vcc
GND
100 KHz
ClK
SC
06
07
DATA
BUS
I
D4
D2
SI8601
Do
OllTPllT ENABLE
OE
VREF-
TRANSDUCER
ANALOG
INPUTS
05
03
01
EOC
l~"
10000000
BUS
0000000
0
VREF+
INl
ALC
1N2
AO
1N3
Al
1N4
A2
INS
INS
INS
1N7
Figure 3.
6-138
START
PULSE
ANALOG LATCH
CONTROL
}
INPllT
ADDRESS
}
ANALOG
INPUTS
Ratlometrlc System
INPUT VOLTAGE - VOLTS
VCC=5V
VREF= 5 V
GND = VREF _= 0 v
RESOLUTION = 19.5 mV
RSOURCE S 1 k.n.
Si8601/8603
flY' Siliconix
~
incorporated
APPLICATIONS (Cont'd)
MEMORY MAPPED OPERATION
When operating in the memory mapped mode, the
data outputs and address input are tied directly to
their corresponding busses. The OC, START, and
ALC lines are used to tri-state the digital outputs
when appropriate. Figure 4 shows the schematic
diagram of the memory mapped data acquisition
system. Note the A15 is the only address decoding
line used for this example. To eliminate memory
map redundancy, a more sophisticated address
decoding circuit would be needed. The NOR gates
of the 4001 combine the address decoding, READ
and WRITE signals to control the data acquisition
system. The EOC pin is tied to the RST 6.5 of the
8085 to notify the microprocessor when the
conversion has been completed and when the data
outputs are ready to be read.
+15 V
4.9 k.n.
Si86011
Si8603
+5V
07
07
°6
°6
Os
Os
°4
°4
°3
°3
°2
°2
°1
°1
°0
°0
Vee
TO 8065
BUS SYSTEM
REF+
3~-~--O----I
555
eLK
GNO
REFse ALe
Eoe
RST 6.5
OE
r-------IREAO
\:-------lWRITE
3/44001
Figure 4.
Schematic Diagram of a Memory Mapped Interface
6-139
..
Si8601/8603
WF'Siliconix
incorporated
~
PIN CONFIGURATION (Si8601 8-CHANNEl DATA ACQUISITION SYSTEM)
PIN
NUMBER
SYMBOL
2
Vee
ClK
3-6
7
06,04,
02, DO
OE
8
REF-
9-16
IN1-IN8
17-19
A2-AO
20
AlC
21
22
23-26
REF+
EOC
01,03,
05,07
27
28
SC
GND
DESCRIPTION
Input for the positive supply voltage.
Input for the CLOCK. The clock amplitude must conform to the VIH and VIL of
the specifications and the rise time should be > 10 ns.
Digital DATA OUTPUTS, Bit 0 (Pin 6) is the LSB.
Logic input for OUTPUT ENABLE. Connects the three-state output latches to
the microprocessor BUS.
Input for the most negative voltage of the reference. It is normally grounded
unless compressed mode operation is desired.
ANALOG INPUTS of the 8-channel multiplexer (channel 1-Pin 9, channel
a-Pin 16).
The three ADDRESS INPUTS that select the one-of-eight analog inputs to be
converted.
ADDRESS LOAD CONTROL input that latches the input address into the
multiplexer.
Input for the most positive voltage of the reference.
END OF CONVERSION output that goes high at the end of conversion.
Digital DATA OUTPUTS. Bit 7 (Pin 26) is the MSB.
START CONVERSION input that initiates the conversion process.
Power supply and analog GROUND.
PIN CONFIGURATION (Si8603 8-BIT DATA ACQUISITION SYSTEM, DIP VERSION)
PIN
NUMBER
1
2
SYMBOL
DESCRIPTION
Vee
CLK
Input for the positive supply voltage.
Input for the CLOCK. The clock amplitude must conform to the VIH and VIL of
the specifications and the rise time should be > 10 ns.
Digital DATA OUTPUTS, Bit 0 (Pin 6) is the LSB.
3-6
06,04,
02, DO
7
OE
Logic input for OUTPUT ENABLE. Connects the three-state output latches to
the microprocessor BUS.
8
GND
9
10
IN
REF+
EOC
01,03,
05,07
Power supply and analog ground.
ANALOG INPUT
Input for the positive reference voltage.
11
12,13,14,15
16
SC
END OF CONVERSION output that goes high at the end of conversion.
Digital DATA OUTPUTS. Bit 7 (Pin 15) is the MSB.
START CONVERSION input that initiates the conversion process.
GENERAL PRECAUTIONS (For All Applications)
1. VREF+ must NEVER exceed Vee by more than 50 mV.
2. VREF- must NEVER be more negative than GND by more than 50 mV.
3. Under no condition should any voltage be applied to any pin before Vee (prevents latch-up).
6-140
Si8602l8604
tI"F' Siliconix
~
incorporated
8-Bit Data Acquisition Systems
FEATURES
BENEFITS
" Total Unadjusted Error
< 1/2 LSB (Si8604)
II
APPLICATIONS
Eliminates External Trims
• Increased Data Throughput
• J.LP IPC-Based Data
Acquisition Systems
• Fast Conversion Time
(25 J.Lsmaximum)
• Reduced System Power
Consumption
• Battery-Operated Systems
• Low Power (9 mW typ.)
• Reduced Aperture Error
• On-Chip S/H Function
• Single Supply Operation
• On-Board 8-Channel
Multiplexer (Si8602)
&I
g
VoicelTelecom Systems
• Audio Digitizing
15 V Military Systems
• Remote Data Acquisition
• High Density Systems
• Reduced Board Space and
Component Count
e Microprocessor Interface
DESCRIPTION
The Si8602 and Si8604 are 8-bit data acquisition
systems which include an AID converter,
sample-and-hold function, and a microprocessor
interface on one monolithic chip. The Si8604 is a
single-channel version, while the Si8602 includes an
on-board 8-channel analog multiplexer and decode
logic to form a complete 8-channel data acquisition
system. The Si8602 and Si8604 are designed for
15 V single-supply operation, 0 to 10 V Analog
Range and CMOS logic interfacing.
Built in the Siliconix proprietary PolyMOS'M process,
the Si8602/8604 use a capacitive-ladder AID
conversion technique to achieve low power, high
speed and less than 112 LSB total unadjusted error
without the need for thin film resistors or laser
trimming. The capacitive ladder architecture
creates an on-board samplelhold function,
reducing the aperture time of the converter to less
than 90 ns. This facilitates digitizing rapidly-slewing
An
analog signals with a minimum of error.
epitaxial layer prevents latchup.
The Si8602 is available in 28-pin plastic and ceramic
DIP. The Si8604 is available in 16-pin plastic and
ceramic DIP. Both are available in industrial, D suffix
(-40 to 85°C) and military, A suffix (-55 to 125°C)
temperature ranges and in 1883 versions as well.
For surface mount applications, the Si8602 is
available in the PLCC-28, and the Si8604 in the
PLCC-20. For more information on the Si8602,
please refer to Siliconix application Note AN83-13.
PIN CONFIGURATION
Dual-In-Llne Package
PLCC-20 Package
C V
L C N S D
K C C C 7
3112 1112011191
/
•
D6 4
D4
Fs
NC ~
D2~
Top View
Top View
CerDIP: SI8604DJ
Plastic: S18604AK, SI8604DK
~
J4
DO 8
Order Numbers:
~
~
DS
D3
NC
D1
EOC
91110111111121113
o G N I R
E N C N E
D
F
+
Order Number:
SI8604DN
6-141
Si8602l8604
.... Siliconix
incorporated
~
PIN CONFIGURATION (Cont'd)
Dual-In-Llne Package
PLCC-28 Package
~
e v
G
RRg ~ g ~ (MSB)
6 0 7 (MSB)
05
02
05
03
(LSB) Do 6
01
Order Numbers:
CerDIP:SI8602AK
SI8602DK
Plastic: SI8602DJ
1
Eoe
1 REF+
REF+
ALe
ALe
Ao
Al
1
A2
-;~--~T~ap~V~I~&W----r-
4
1
~~~~~~t
IN 8
4
IN 7
5 6 7 8
Tap View
Order Number:
SI8602DN
FUNCTIONAL BLOCK DIAGRAM
r------------------,
I
I
I
8
ANALOG
INPUTS
I
ADDRESS {
ADDRESS LOAD CONTROL
I
I
I
L __________________ ~
Si8602 ONLY
I
ABSOLUTE MAXIMUM RATINGS
Reference Input Voltage Range,
VREF-' •...•.....•.....••••..••...•••. -0.3 V to VREF+
Reference Input Voltage Range, VREF+
••..•..••...•........•...•••..••• VREF- to Vee +0.3 V
Supply Voltage, Vee ..•..•.........•.....•....• 16.5 V
Input Voltage Range, All Inputs .... -0.3 V to Vee +0.3 V
Storage Temperature (K Suffix) .......... -65 to 150'C
(J, N Suffix) ..•••.. -65 to 150'C
Operating Temperature (A Suffix) ...•••... -55 to 125'C
(0 Suffix) ...••..... -40 to 85'C
6-142
Power
28-Pln
l6-Pln
28-Pln
l6-Pln
28-Pln
20-Pln
Dissipation (Package)·
Ceramic DIp·· ....................... 1046
Ceramic DIp··· ...................... 900
Plastic Dip···· .•••.••....•••.•••..•. 1046
Plastic Dip····· ..••.....•...•.•...... 900
PLCC····· ••••..••..•.••.•••........ 900
PLCC····· .......................... 900
All leads welded or soldered on PC Board.
Derate 6.5 mW/'C above 25'C.
Derate 12 mW/'C above 75'C.
Derate 6.5 mW/'C above 25'C.
Derate 12 mW/'C above 75'C.
mW
mW
mW
mW
mW
mW
Si8602l8604
..w'" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a, m, n
Test Conditions
Unless Otherwise Specified:
PARAMETER
LIMITS
1=25 ·C
2=125,85·C
3=-55, -40· C
All
Grades
SYMBOL
Vcc= 15 V
f CLOCK = 1.04 MHz
TEMP
I ON (PEAK)
VIN =5V
1
VIN = 15 V
1
VIN =OV
1
VIN = 15 V
2,3
VIN =OV
2,3
-1000
1,2,3
VREF-
1,2,3
Vee -l.5
TVP
d
MIN b MAXb
UNIT
INPUT
Input Channel ON State
Current 9
Input Channel OFF State
Current f
Analog Input Voltageg
JlA
-5
200
-200
nA
I OFF
VANALOG
,
1000
VREF+
High Level Input Voltage
VIH
V
Low Level Input Voltage
VIL
1,2,3
1.5
High Level Input Current f
IIH
1,2,3
1
Low Level Input Current f
IlL
JlA
VIN=OV
1,2,3
-1
1,2,3
14
1,2,3
9
OUTPUT
High Level Output Voltage
VOH
10 = -360 JlA
V
Low Level Output Voltage
OFF State Output Current q
VOL
Data
Outputs
1,2,3
0.4
End Of
Conversion
1,2,3
0.4
Veus= 15 V
1,2,3
1
Veus = 0 V
1,2,3
10= 1.6mA
JlA
los
-1
SUPPLY
Supply Current h
Icc
VREF+ Is open, V REF- = 0 V
VIL = 0 V, V IH = 15 V
1,2,3
0.6
2
mA
6-143
Si8602l8604
trY'Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a, m, n
Test CondItIons
Unless OtherwIse SpecIfied:
SYMBOL
PARAMETER
Vcc= 15 V
f CLOCK = 1.04 MHz
LIMITS
1=25 ·C
2=125,85·C
3=-55, -40 • C
TEMP
TYP
All
Grades
d
MIN b MAXb
UNIT
SUPPLV (COrtt'd)
Supply Voltage I, c
Vcc
Refer to • Operating Range" Graph
1,2,3
Positive R~ference
Voltage g,
VREF+
Refer to ·Operatlng Range" Graph
1
60
10
1
0
0.3 c
10.8
16.5
V
Negative Reference
Voltage g
VREF-
Voltage BetweenVcc
and VREF+ Terminals
V cc VREF+
Refer to • Operating Range" Graph
1
0
DYNAMIC
Control Input Capacitance
C1
1,2,3
2.5
Data Output Capacitance
Co
1,2,3
5.5
Supply Voltage Sensitivity
PSR
1,2,3
0.05
ZE
1,2,3
0.25
-0.5
0.5
1,2,3
0.25
-0.75
0.75
pF
Zero Error J
Full Scale Error
Vcc= 16.5 V & 10.6 V
fCLOCK = 1.04 MHz
%/V
LSB
Relative NonlinearIty
INL
1,2,3
0.25
-0.5
0.5
DifferentIal NonlinearIty
DNL
1,2,3
0.25
-0.5
0.5
fCLOCK
1,2,3
Start Pulse WIdth
tsc
1
100
Address Load Control
Pulse WIdth
tALC
1
200
Address Set Up Time
tsu
1
50
Address Hold TIme
tH
1
50
Input Voltage Stable I
tiS
1
6
tOEC
1
0
TIMING
Clock Frequency I,
0
1.5
MHz
ns
End of Conversion
Delay TIme
6-144
SI6602 ONLY
Clock
Periods
200
ns
H
Si8602l8604
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a, m, n
PARAMETER
LIMITS
SYMBOL
Test Conditions
Unless Otherwise Specified:
Vcc= 10.8 V to 16.5 V
VREF+ = 10 V, VREF- = 0 V
fCLO CK = 1.04 MHz
TEMP
tcoNV
tsc= 100 ns
1,2,3
1=25 ·C
2=125,B5·C
3=-55,-40· C
TYP
All
Grades
d
MIN b MAXb
UNIT
TIMING (Cont'd)
Conversion Time k
25
Output Enable Time
tOE
C L = 50 pF
1
100
200
Output Disable Time
too
C L = 10 pF
R L = 10 k.Cl.
1
100
200
.I1s
ns
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Decays exponentially during first clock high period.
f. Channel addressed with clock OFF.
g. Analog Input voltage greater than VREF+ converts as all ones and less than VREF- as all zeros.
h. Current Increases linearly with frequency of the clock at a rate of approximately 10% per 100 kHz.
I. For proper operation the maximum clock rate must be lowered as the voltage across the reference terminals
Is lowered below 10 V. The maximum clock rate must be lowered by 0.68 f CLOCK Ivolt multiplication factor.
VREF+ must be above 3.0 V or Vcc - 1.0 V, whichever Is higher.
J. All errors are measured with reference to an Ideal straight-line transfer curve from 1/2 LSB to ( Vcc - 1/2 LSB).
k. Source resistance < 1 k.Cl. .
m. All voltage values are with respect to ground terminal.
n. All dc parameters are 100% tested at 25 oC. Lots are sample tested for ac parameters and high and low temperature
limits to assure conformance with specifications.
q. Vaus Is the voltage applied to the output pins when the digital outputs are In the OFF state.
DIE TOPOGRAPHY
.....f - - - - - - -
123
mlls-------I~
11
2
12
13
Si8602
28114 mils
14
15
16
27
17
18 19
Pin
No.
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vce
CLK
Ds
D4
D2
Do
OE
REFIN,
IN2
IN3
IN4
INs
INs
Pin
No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
IN7
INa
A2
A,
Ao
ALC
REF+
EOC
D,
03
Ds
D7
SC
GND
20 21 22 23 24 25 26
CSAD
493 P-Channel Enhancement MOSFETs
477 N-Channel Enhancement MOSFETs
13 Capacitors
7 Resistors
6-145
..... Siliconix
incorporated
Si8602l8604
~
DIE TOPOGRAPHY (Cont'd)
Si8604
I'"
123 mils
5
6
4
3
~I
Pad
No.
7
1
2
3
4
5
6
7
8
114 mils
9
10
11
12
13
14
15
16
8
9
10
16
Function
Vee (Substrate)
CLK
06
04
O2
Do
OE
GND
IN
REF+
EOC
0,
03
05
07
~::::::~11::::::::::~~12~13~1~4~1~5:::!J
20X
CSBD
425 P-Channel Enhancement MOSFETs
409 N-Channel Enhancement MOSFETs
13 Capacitors
7 Resistors
OPERATING RANGE OF VREF+ AND Vee
Guaranteed Test Points
10
,/,/
-----------~~~7~·-
___________
8
J""
/"A/-:%
/.,....".
off,f
~~~~~d_
I
I
I
I
I
I
I
I
I
I
Vee
6-146
SC
Si8602l8604
..... Siliconix
incorporated
~
TIMING
I--lll..j
2
4
3
5
8
7
6
9
25
26
CLOCK
SI8602\
Only
START
SEE DETAIL A
ALC
SEE DETAIL A
HI-----
--~-------------------------;Hr_-----
ADDRESS
ANALOG IN
EOC
__ ~________________________
--;:rr
SEE DETAIL A
f----
~
v---fr~-----
1~·--------t-ls--------------~~~1
r-
- - - - - , SEE DETAIL A
"
S~
tcoNV
-----------~~~I
OLrrPUTCONTROL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~frr---~LATCH OUTPUTS
SEE DETAIL
BI
-----------------------------~Hr-----~"
DETAIL A
START _ _ _ _ _ _ _ _ _ _ _~1. 50%
~\_ _ _ _ __
t6C----./"
I
EOC
60%}~_ _ _ _ _ _ __
I+-tDEC--t
SI8602\
Only
ALC _ _ _ _ _
---Jf,1oI1~1-60-%-----
1
tALC
ADDRESS
~ 50%
1
DETAILB
OLrrPLrr CONTROL
I.-tH . . . .
_
--------..!~r~---------
6O%Xr - - - - - - - - - - - - - - -
1
tS~
_ _ _
------J~150%
"~
I~
1(:90%~O%
LATCHED OLrrPUTS - - - - - - -_______=------~IH"
HIZ STATE
1
1
--.I 1.10%
tOE
I 1
- - ' ~%
too
DETAILED DESCRIPTION
PRINCIPLES OF OPERATION
Si8602 with On-chip Eight Channel MUX:
The analog multiplexer selects 1 of 8 single-ended
input channels as determined by the input address
code. The Address Load Control (ALC) transfers
and latches the code into the address decoder on
the positive edge of the ALC signal. The output
latch is reset by the positive edge of the Start
Conversion (SC) pulse. Sampling starts with the
positive edge of the SC pulse and lasts for 8 clock
periods from its falling edge. The conversion
process can be interrupted by a new SC pulse
before the end of 24 clock periods. Continuous
conversion may be accomplished by connecting
the End of Conversion (EOC) output to the start
input. If used in this mode an external pulse should
be applied after power up to assure start up.
6-147
Si8602l8604
..,. Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
MULTIPLEXER FUNCTION TABLE
INPUTS
ADDRESS
A2 Al Ao
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
ADDRESS LOAD
CONTROL
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
to
to
to
to
to
to
to
to
SELECTED
ANALOG
CHANNEL
1
2
3
4
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
5
6
7
8
SWITCHED CAPACITOR AID CONVERTER
The CMOS comparator in the (SAR) successive-approximation system determines each bit by examining the charge on a series of binary-weighted
capacitors (Figure 1). In the first phase of the
conversion process, the analog input is sampled by
closing switch SC and all ST switches, and by
simultaneously charging all the capacitors to the
input voltage.
In the next phase of the conversion process, all ST
and SC switches are opened and the comparator
Figure 1.
6-148
begins identifying bits by identifying the charge on
each capacitor relative to the reference voltage. In
the switching sequence, all eight capacitors are
examined separately until all 8 bits are identified,
and then the charge-convert sequence is repeated.
In the first step of the conversion phase, the
comparator looks at the first capacitor (binary
weight = 128). One pole of this capacitor is
switched to the reference voltage, and the
equivalent poles of all the other capacitors on the
ladder are switched to ground. If the voltage at the
summing node is grater than the trip-point of the
comparator (approximately one-half the reference
voltage), a bit is placed in the output register, and
the 128-weight capacitor is switched to ground. If
the voltage at the summing node is less than the
trip-point of the comparator, this 128-weight
capacitor remains connected to the reference input
through the remainder of the capacitor-sampling
(bit-counting) process. The process is repeated for
the 64-weight capacitor, the 32-weight capacitor,
and so forth down the line, until all bits are tested.
As can be seen, with each step of the capacitorsampling process, the initial charge is redistributed
among the capacitors. The conversion process is
successive-approximation, but relies on charge
shifting rather than the traditional successiveapproximation register and reference DI A to count
and weigh the bits from MSB to LSB.
Simplified Successive Approximation Register ,
Si8602l8604
..,. Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
V REF (+)
2.6k
IN x
58 pF
o------"\iV\.- 1---..--.........
I
--
--
28.8 pF
Figure 2. Equivalent Input Impedanoes
I"on
l~o4
I
28.8 pF
APPLICATIONS
The 8i8602 and 8i8604 are CM08 Converters using
charge redistribution to achieve AID conversion.
This
allows
ratiometric
conversion.
In
a
single-supply system. VREF- will be connected to
ground and VREF+ will be connected to Vee. The
output will then be a simple proportional ratio
between analog input voltage and Vee (Figure 3).
The general relationship is:
Digital Output (0 to 255)
Analog Input
Positive Referenoe Potential
Negative Referenoe Potential
Where DOUT
VIN
VREF+
VREF-
BINARY
OUTPUT
CODE
TRANSFER
FUNCTION
11111111
VCC
GND
100 KHz
DATA
BUS
1
CLK
SC
De
D7
04
O2
SI8602
Do
OUTPUT ENABLE
OE
VREF-
iANSOUCER
05
03
jP::::
10000000
BUS
01
EOC
VREF+
.>4H--------:lIN1
ALe
1N2
AO
1N3
A1
1N4
A2
ANALOG
INPUTS
START
INS
INS
INS
IN?
1-----1
AN~g:rR't~CH
}
}
A6~fss
ANALOG
INPUTS
INPUT VOLTAGE - VOLTS
Vce= 15V
VREF= 10 V
GND = VREF _= 0 v
RESOLUTION = 39.1 mV
RSOURCE S 1 k.n.
Figure 3. Ratlometrlc System
6-149
Si8602l8604
...... Siliconix
incorporated
~
PIN CONFIGURATION (Si8602 8-CHANNEL DATA ACQUISITION SYSTEM)
PIN
NUMBER
SYMBOL
2
Vee
CLK
3-6
7
06.04.
02. DO
OE
8
REF-
9-16
IN1-IN8
17-19
A2-AO
20
ALC
21
22
23-26
REF+
EOC
01.03.
05.07
SC
GND
27
28
DESCRIPTION
Input for the positive supply voltage.
Input for the CLOCK. The clock amplitude must conform to the VIH and VIL of
the specifications and the rise time should be > 10 ns.
Digital DATA OUTPUTS. Bit 0 (Pin 6) is the LSB.
Logic input for OUTPUT ENABLE. Connects the three-state output latches to
the microprocessor BUS.
Input for the most negative voltage of the reference. It is normally grounded
unless compressed mode operation is desired.
ANALOG INPUTS of the 8-channel multiplexer (channel 1-Pin 9. channel
8-Pin 16).
The three ADDRESS INPUTS that select the one-of-eight analog inputs to be
converted.
ADDRESS LOAD CONTROL input that latches the input address into the
multiplexer.
Input for the most positive voltage of the reference.
END OF CONVERSION output that goes high at the end of conversion.
Digital DATA OUTPUTS. Bit 7 (Pin 26) is the MSB.
START CONVERSION input that initiates the conversion process.
Power supply and analog GROUND.
PIN CONFIGURATION (Si8604 8-BIT DATA ACQUISITION SYSTEM. DIP VERSION)
PIN
NUMBER
SYMBOL
1
2
Vee
CLK
3-6
06.04.
02. DO
OE
7
8
9
10
11
12.13.14.15
16
GND
IN
REF+
EOC
01.03.
05.07
SC
DESCRIPTION
Input for the positive supply voltage.
Input for the CLOCK. The clock amplitude must conform to the VIH and VIL of
the specifications and the rise time should be> 10 ns.
Digital DATA OUTPUTS. Bit 0 (Pin 6) is the LSB.
Logic input for OUTPUT ENABLE. Connects the three-state output latches to
the microprocessor BUS.
Power supply and analog ground.
ANALOG INPUT
Input for the positive reference voltage.
END OF CONVERSION output that goes high at the end of conversion.
Digital DATA OUTPUTS. Bit 7 (Pin 15) is the MSB.
START CONVERSION input that initiates the conversion process.
GENERAL PRECAUTIONS (For All Applications)
1. VREF+ must NEVER exceed Vee by more than 50 mV.
2. VREF- must NEVER be more negative than GND by more than 50 mV.
3. Under no condition should any voltage be applied to any pin before Vee (prevents latch-up).
6-150
WidebandNideo . .
~
~
Siliconix
incorporated
TABLE OF CONTENTS
Introduction .•..•..•.••......••...............................•..................... 7-1
DG534: 4-ChannellDual 2-Channel WidebandlVideo Multiplexer .......•.•.•.................. 7-3
DG535: 16-Channel WidebandlVldeo Multiplexer ••.•.................••...............•.. 7-21
DG536: 16-Channel WidebandlVideo Multiplexer •.......•...........•......•............. 7-34
DG538: 8-Channel/Dual 4-Channel WidebandlVideo Multiplexer ..........................•.. 7-47
DG540: Quad SPST WidebandlVideo "T" Switch ........................................ 7-65
DG541: Quad SPST WidebandlVideo "T" Switch ...•....................•.....•......... 7-70
DG542: Dual SPDT WidebandlVideo "T" Switch ......•...•.............................. 7-75
SD5000/5001/5002: DMOS FET Quad Analog Switch Arrays •.............................. 7-81
SD5400/5401/5402: DMOS FET Quad Analog Switch Arrays ......•.....•.................. 7-88
~
~
Siliconix
incorporated
WIDEBANDNIDEO
INTRODUCTION
Siliconix manufactures analog switches and multiplexers for wideband/video applications using Double Diffused
MOS (DMOS) technology. DMOS FETs are n-channel enhancement-mode MOSFET's which exhibit very low
capacitance and ON resistance, compared to conventional CMOS devices. The result is wide bandwidth
switches, from discretes such as the SD210 and SD5000 families, through D/CMOS "T" switches and mUltiplexers which feature crosstalk and off isolation performance as high as 100 dB at 5 MHz and 3 dB bandwidths in
excess of 500 MHz. These devices are ideal for broadcast video, digital data routing, high end workstation
networks and imaging applications from medical to military.
DMOS Switch Arrays
The SD500X and SD540Xs are monolithic arrays of four DMOS FETs without drivers. Their low capacitance and
low ON resistance make them ideal for high speed wide band switching and sampling applications.
D/CMOS "T" Switches
The DG54X family of wideband/video "T" switches includes the DG540, DG541 and DG542 switches. The DG540
and DG541 are quad SPST switches, and the DG542 is a dual SPDT (or dual changeover) function. The DG540
employs interstitial ground lines between adjacent channels to achieve improved isolation and reduced
crosstalk. The DG541 uses the standard DG201A pin-out, hence has slightly inferior performance than the
DG540, but is available in a lower cost, smaller package. Each of these switches uses DMOS "T" switches for
fast switching, wide bandwidths and excellent isolation.
D/CMOS WidebandlVideo Multiplexers
The DG535 and DG536 are 16-channel wideband/video multiplexers which use the Siliconix D/CMOS process to
combine wide band DMOS "T" switches with high density, high speed CMOS logic and switch drivers to form
complete monolithic wideband/video multiplexing systems. These devices include on-board latches to hold the
address selection data and all of the necessary control logic to facilitate connection into larger arrays, matrices
and multiplexers. The DG534 and DG538 are 4- and 8-channel wideband/video multiplexers which, like the
DG535 and DG536, feature address latches and control logic with the addition of data read back and TTL-compatibility. They make excellent wideband/video crosspoints, routers, and multiplexers, reducing board space,
power dissipation, component count and cost while simplifying system design and improving reliability.
For detailed information on these products please refer to their individual data sheets and to application notes
AN85-3, AN86-1, and AN88-2.
.
GLOSSARY OF TERMS
Bandwidth
Crosstalk
The "3 dB down" point of the frequency response
characteristic.
A measure of how much of an unwanted signal appears on a given analog channel due to spurious capacitive or inductive coupling from another channel.
Crosspoint Switch
A two-dimensional array of analog switches or analog
multiplexers that allows for the routing of signals from
any input to any output.
D/CMOS
Semiconductor process that combines DMOS FETs
and CMOS logic on a monolithic chip.
7-1
..
W'I' Siliconix
~
incorporated
Differential Gain
Output Buffer
Expressed as a percentage. this is a form of distortion that appears as changes in the amplitude of the
chrominance (color) signal as a function of luminance (brightness) amplitude.
An amplifier. typically with a gain of two. which is normally used at the output of a video multiplexer to
drive a length of double terminated coaxial cable.
Output Capacitance
Differential Multiplexer
Analog multiplexer that selects both the high and the
low side of each signal. It can be thought of as two
single-ended multiplexers operating in tandem.
Differential Phase
Measured in degrees is the phase shift of the color
subcarries resulting from changes in luminance level.
DMOS
(Double Diffused MaS) Type of field effect transistor
featuring low rOS(ON) and low capacitance.
Capacitive load that the output of an OFF switch adds
to the output node.
PLCC Package
Plastic leaded chip carrier. Surface mount package
characterized for its small size and reliable lead-toprinted circuit board mechanical interface.
Readback
Feature that allows for the inspection of the control
latch contents in a multiplexer.
Single Ended Multiplexers
Input Capacitance
Array of analog switches that selects one of several
analog input signals.
Capacitive load that the input terminal of an analog
switch presents to the signal source. It is specified
both with the switch ON or OFF.
"T" Switch
Insertion Loss
Analog switch configuration consisting of two series
switches and a shunt switch to ground. It is used to
dramatically improve the off-isolation of the array.
Expressed in dB. is a measure of the signal loss
caused by the impedance of the analog switch at a
given frequency.
'
Video
Off Isolation
Video Buffer
A measure of how much of the signal applied to an
"open" switch appears at its output due to parasitic
components such as gate-to-channel capacitance
and lead inductances.
An amplifier whose function is to reduce the capacitive loading effect of several video multiplexer inputs
on a common signal source. This is normally a unity
gain buffer.
ON-Resistance
Wideband
DC input-to-output resistance of an analog switch
channel when the switch is turned ON.
A relative term. as used in this book it refers to a
frequency spectrum at least more than 2 MHz wide.
7-2
Electrical signals carrying dynamic visual information.
~
~
DG534
4·Channel/Dual 2·Channel
WidebandNideo Multiplexer
Siliconix
incorporated
APPLICATIONS
BENEFITS
FEATURES
•
Wide band Signal Routing
and Multiplexing
• Wide Bandwidth (500 MHz)
•
Improved System Bandwidth
•
Very Low Crosstalk
(-97 dB @ 5 MHz)
•
Improved Channel Off-isolation
•
High-end Video Systems
On-Board TTL-compatible
Latches with Readback
Simplified Logic
Interfacing
•
•
•
J.lP-controlied Systems
•
Direct Coupled Systems
Optional Negative
Supply Input
Allows Bipolar
Signal Swings
•
•
•
ATE Systems
•
Reduced Insertion Loss
•
Allows Differential
Signal Switching
n
•
Low rDS(ON) (90
•
Single-ended 4-channel or
Dual 2-channel Operation
max)
•
ESDS Protection >
±4000
V
DESCRIPTION
The DG534 is a digitally selectable 4-channel or
dual 2-channel analog multiplexer designed for
wideband operation.
On-chip TTL-compatible
address decoding logic and latches with data
read back are included to simplify the interface to a
microprocessor data bus. The low ON resistance
and low capacitance of the DG534 make it ideal for
wide band data multiplexing and video and audio
signal routing in channel selectors and crosspoint
arrays. An optional negative supply pin allows the
handling of bipolar signals without DC biasing.
low-power CMOS control logic, drivers and latches.
The low-capacitance DMOS FETs are in a "T"
configuration to achieve extremely high levels of
OFF isolation. Crosstalk is reduced to -97 dB at
5 MHz on the DG534 by including a ground line
between each adjacent signal path.
The DG534 is built on a D/CMOS process that
combines n-channel DMOS switching FETs with
For more information please refer to Siliconix
Applications Note AN88-2.
The DG534 is available in 20-pin plastic DIP and
PLCC packages for operation over the industrial, D
suffix (-40 to 85°C) temperature range.
The
20-iead side braze DiP is available for military, A
suffix (-55 to 125°C) temperature range operation.
PIN CONFIGURATION
Dual-In-Llne Package
PLCC Package
Top View
Top View
NO
DS
v-
Sa1
GND
GND
8e2
vL
, .
v+ 311 2111112a1191 v-
~
~
~
~8
~
~
~
~4
iio
WR
Order Numbers:
Side Braze: DG534AP,
Plastic: DG534DJ
Preliminary
9111'11111112111:31
iio
Order Number:
DG534DN
7-3
DG534
Siliconix
incorporated
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
VL
SA'
S A2
V+
GND
V-
\~r--------------o-r&------,
~_"'-1i--I-o
\-i
~ I
I
I
I
SB' 0 - + - - - - " 1 .....i-
-i----t--rj-
SB2
O-+---'T ....
-+1- - - 1 0 - - - I
"'""i
l
DA
I
4/2 o-t-+-----r-~,_I_--__t_-...I
r---~~r__t__t--__. ~
DECODE LOGIC, ADDRESS
LATCHES, 1/0 CONTROL
X
x
.r
1
,
ON SWITCH
X
X
X
X
X
X
0
X
Nona (latches cleared)
X
X
X
0
1
None
0
0
0
1
0
,
0
0
,
,
X
0
,
0
0
1
0
1
0
1
0
0
1
1
1
0
0
X
0
,
0
0
1
1
0
X
1
1
0
1
1
~~n~~Te?
SA2
eK1ernaliv
SBI
Transparent
SB2
SAl &SBI
SA2 & SB2
1
1
1
'Note
1
DB
t---+ORS
LOGIC
As 412
X
1/0 Al Ao EN WR
All four Input switches are "T" switches.
1--'-NOTE
1
0
Maintains previous state
\
~'I
0
l~-
r-2--
~
Logic" 1 • : VAH
~
2.0 V
Logic" 0 • : VAL
::s;;
0.8 V
1. 4/2 can be either H or L but should not change
during these operations.
2. In this condition the pins Ao and Aj become
outputs and reflect the contents Of the latches.
Please see timing waveforms for more detail.
3. EN must be latched HIGH to allow proper address
data readback operation.
i/o
WR
EN
Ao
Al
ABSOLUTE MAXIMUM RATINGS
V+ to GND
V+ to VV- to GND
........................... -0.3 V to +22 V
Power Dissipation (Package)"
.•.•••.•.•..••••••......... -0.3 V to +22 V
•.•••...•...•.•••........•. -10 V to +0.3 V
20-Pln Plastic DIP""
Digital Inputs ...... (V- minus 0.3 V) to (V+ plus 0.3 V)
or 20 mA, whichever occurs first
Vs ,Vo
625 mW
20-Pln Side Braze DIP"""
20-Fln Quad J Lead Plastic""""
1200 mW
450mW
•••........ (V- minus 0.3 V) to (V- plus 14 V)
or 20 mA, whichever occurs first
CURRENT (any terminal) Continuous........... 20 mA
CURRENT (S or D) Pulsed 1 ms 10% duty ..... 40 mA
" All leads welded or soldered to PC board.
Derate 8.3 mW/"O above 75"0
Storage Temperature
(A Suffix) •.... -65 to 150"0
(D Suffix) ..... -65 to 125"0
Derate 16 mW/"O above 75"0
Derate 6 mW1"0 above 75"0
Operating Temperature (A Suffix) ..... -55 to 125"0
(D Suffix) ..... -40 to 85"0
7-4
Preliminary
H
DG534
~iliconix
Incorporated
CONTROL
SAl ~S~--------=======-
CIRCU~IT~R~Y~==-----------
~~40~ ?9
DA
~T~
-,
r--
I
I
I
I
I
I
I
I
I
I
L
,
I
I
I
I
I
LATCH
I
I
I
I
I
I
I
_ _ _ .J
..
r-
I
'
I TRI-STA TE I
I TTL BUFFER I
'I
Ao
Preliminary
7-5
DG534
WY'Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
LIMITS
1=2S·C
A
2=12S,8S·C
SUFFIX
3=-SS,-40·C -55 to 12SoC
0
SYMBOL
V+ = 15 V, V- = -3 V
VL= +5 V, GND = 0 V
WR = 0.8 V
RS, EN = 2 V
VANALOG
V- = -5 V
1
Drain - Source
ON Resistance
rOS(ON)
I s =-10mA, Vs=OV
1,3
2
Resistance Match
Between Channels
rOS(ON)
tJ..
VAIL = O.B V, V AlH = 2 V
Sequence each switch ON
1
Source OFF
Leakage Current
IS(OFF)
V s =8V, Vo=OV
EN = O.B V
1,3
2
-5
-50
5
50
-5
-50
5
50
Drain OFF
Leakage Curr.ent
IO(OFF)
Vs = 0 V, Vo = 8 V
EN = 0.8 V
1,3
2
-20
-500
20
500
-20
-500
20
500
Total SWitch ON
Leakage Current
IO(ON)+
IS(ON)
Vs = Vo = 8 V
1,3
2
-10
-1000
10
1000
-10
-100
10
100
VAO = 2.7 V
1,2,3
-400
VAO = 0.4 V
1,2,3
PARAMETER
TEMP TYpd
SUFFIX
-40 to 85°C
MIN b MAXb MINbMAX t
UNIT
SWlTCH
Analog Signal Range e
-5
45
8
-5
8
90
120
90
120
9
9
V
.0.
nA
INPUT
Address Output Current
Input Voltage High
-400
IJ.A
lAO
VAIH
400
1,2,3
2
400
2
See Figure 13
Note 1
Input Voltage Low
Address Input Current
IAI
V
1,2,3
VAIL
VAl;' 0 V or 2 V or 15 V
0.8
1,3
2
0.1
-1
-10
1
10
0.8
-1
-10
1
10
~A
DYNAMIC
ON State Input Cap!'
CS(ON)
See Figure 11
PLCC
DIP
1
1
23
27
35
30
35
OFF State Input Cap.c
CS(OFF)
See Figure 12
PLCC
DIP
1
1
2
3
5
4
5
OFF State Output·Cap.c
Co (OFF)
See Figure 12
PLCC
DIP
1
1
4
10
8
10
Multiplexer Switching Time
tTRANS
See Figure 4
1,3
2
300
500
300
500
tOPEN
See Figure 4
1,2,3
EN, WR Tum on Time
tON
See Figures 2 & 3
1,3
2
300
500
300
EN, Tum OFF Time
tOFF
See Figure 2
1,3
2
150
300
150
300
Break-Belore-Make
Interval
6
50
pF
50
ns
7-6
5~0
Preliminary
DG534
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V, V- = -3 V
VL=+5V, GND=OV
WR = O.B V
RS, EN = 2 V
Q
See Figure 5
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40°C -55 to 125°C
TEMP TYpd
D
SUFFIX
-40 to 85°C
MIN b MAXb MIN b MAXt
UNIT
DYNAMIC (Cont'd)
Charge Injection
Chip Disabled Crosstalk
(See Figure 8)
Adjacent Input Crosstalk
(See Figure 9)
All Hostile Crosstalk
(See Figure 7)
Differential Crosstalk
(See Figure 10)
Bandwidth
XTALK(co)
XTALK (AI)
XTALK(AH)
XTALK
(OIFF)
BW
RL = 75.0.
f = 5 MHz
EN = 0.8 V
RIN = 10.0.
RL = 10 kn
f = 5 MHz
RIN = 75.0.
RL = 75.0.
f = 5 MHz
R IN -l0n
RL = 10 kn
f = 5 MHz
RIN - 75.0.
RL = 75.0.
f - 5 MHz
RIN = 10.0.
RL = 10 kn
f = 5 MHz
RIN = 75.0.
RL = 75.0.
f = 5 MHz
1
-70
PLCC
DIP
1
1
-75
-65
PLCC
DIP
1
1
-97
-87
PLCC
DIP
1
1
-80
-70
PLCC
DIP
1
1
-77
-72
PLCC
DIP
1
1
-77
-72
PLCC
DIP
1
1
-84
-84
PLCC
DIP
1
1
-84
-84
1
500
1,2
3
0.6
1,2
3
0.6
RL = son, See Figure 6
pC
dB
MHz
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
Any One Channel Selected
With Address Inputs at GND
or V+
V+ to VOperating Supply
Voltage Range
V- to GND
See Figure 13
Functional Test Only
V+ to GND
Logic Supply Current
2
5
mA
-l.B
-2
-l.B
-2
1,2,3
10
21
10
21
1,2,3
-5.5
a
-5.5
a
1,2,3
10
21
10
21
1,2,3
IL
2
5
150
500
500
V
I1A
TIMING
Reset to Write
WR, Rs Minimum pulse
Width
tRW
See Figure 1
1,2,3
50
50
t MPW
See Figure 1
1,2,3
200
200
tow
See Figure 1
1,2,3
100
100
ns
Ao, A 1 , EN
Data Valid To Strobe
Preliminary
7-7
DG534
W1P" Sillconlx
~
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
LIMITS
Unless Otherwise Specified:
1=26'C
A
D
V+ = 15 V. V- = -3 V
2=125.85·C
SUFFIX
SUFFIX
VL=~' GND=OV
3=-55.-40·C -55 to 125°C -40 to 85°C
WR = 0.8 V
RS. EN = 2 V
SYMBOL
TEMP TYpd MIN b MAXt MIN b MAxt UNIT
PARAMETER
TIMING (¢ont'd)
Ao. A1' EN
Data Valid After Strobe
two
See Figure 1
1.2.3
Address Bus Tristate
tAZ
See Figure 1
1
Address Bus Output
tAO
See Figure 1
tAl
See Figure 1
50
50
1
200
200
1
200
200
50
ns
Address Bus Input
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLV at 25·C. not guaranteed nor subject to production testing.
e. Analog signal range Is measured from the GND pin to ttie designated Source (Input) pin. and Indicates the limits of
functionality. Performance limits are only guaranteed for stated test conditions.
TYPICAL CHARACTERISTICS
Address Output Current vs. Temperature
2
lAO
(mA)
o
-1
-2
-I"- r-
r-
-
100
SI~k
I 1_
VIN = 0.4 V
V+ = 15 V
V- = -3 V
-f- VL = 5 V
III
-f-Source
Vlr =2.7V
I I
-40 -20 0 20 40 60 80100120
Temperature ('C)
7-8
Logic/Address Input Current vs. Temperature
10
IAI
(nA)
.1
.01
-40 -20 0 20 40 60 80100120
Temperature ('e)
Preliminary
DG534
...... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
Supply Currents vs. Temperature
1.0
l~A
i'
'-
.8
I
(mA)
Leakage vs. Temperature
.6
~~~~-r~~~~~-n
100
"- "-
10
I
(nA)
........ ,~+I=ll-I
.4
i'" .......
.2
1 nA
100
IL
10
1 pA
0
-40 -20
0 20 40 60 80100120
Temperature (·e)
-40 -20
reStON) vs. Drain Voltage
200
180
160
V+! 15
V- = -3 V
VL = 5 V
Is = -10 mA
140
res (ON)
(.0. )
125oe.---I
120
60
'..JJ
-55 oe;7j
"1
V ./ I
~~ /'
80
--- -
60
20
I
-/1
25oe~
100
40
reStON) vs. V-; V+ Constant
70
J
-
-
a
-2
reStON)
(.0. )
50
r-
2
4
ve (V)
30
6
8
10
-6
40
-4
-3
V- (V)
-2
-1
0
120
"-f'i'o. . . .
.....
80
60
-5
Adjacent Input Crosstalk
See Figure 9
120
XTALK(AI)
(-dB)
..
40
Adjacent Input Crosstalk
See Figure 9
100
0 20 40 60 80100120
Temperature (·e)
100
"
V+ = 15 V
V- = -3 V
VL = 5 V
RIN = 10 .0.
RLr
lr ill
1 MHz
~G534DN
"
40
.....
IIDG5~4Dr
10 MHz
80
60
r..... .....
Frequency
Preliminary
XTALK(AI)
(-dB)
20
100 MHz
1 MHz
10 MHz
100 MHz
Frequency
7-9
DG534
..w'" Siliconix
~
incorporated
TYPICAL CHARACTERISTICS (Cont'd)
All Hostile Crosstalk
See Figure 7
Differential Crosstalk
See Figure 10
100
120
~ f'....1'
80
100
DG534DN
XTALK(AH)
(-dB)
XTALK(OIFF)
t:".....
60
DG534AP
=15 V
=-5 V
V+
V-
VL;~~
20
1 MHz
i
I'-t-All Package,a
i'-. ....
(-dB)
........ ~i'
40
"
80
60
I""
I'40
-
534D
r
20
10 MHz
V+ = 15 V
V- = -5 V
VL = ~ V
1 MHz
100 MHz
10 MHz
Frequency
100 MHz
Frequency
Insertion Loss
See Figure 6
ON State Capacitance
See Figure 11
0
40
35
-4
IL
r-
(-dB)
CS(ON)
(pF)
30
-8
V+
V-
=15 V
=-3 V
lL~
-12
1 MHz
10 MHz
25
1/
Ilil"j Pi'
100 MHz
20
4
1 GHz
Frequency
6
8
10
Vo - v(V)
Chip Disabled Crosstalk
See Figure 8
Switching Times vs. Temperature
100
XTALK(CO)
80
350
~~
.........
(-dB)
60
r--I'
300
250
"
40
1 MHz
7-10
(ns)
i'-. . .
lllliJ "
10 MHz
Frequency
rF
t
DG534DN
DG534AP
DG534DJ
V+ = 15 V
V- = -\tV
V L =5
Rl = 1 k
Cl =45
200
150
'I'-
ton
V
.",. ~
100
50
100 MHz
1.,..-0
-40 -20
V
/
VI"'"
tOIl
~~
~
,
~
tBBM
0 20 40 60 80 100120
Temperature (OC)
Preliminary
DG534
...... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cent'd)
rOS(ON) vs. V+: V- Constant
70
60
rOS(ON)
(.Cl.)
50
40
30
20
10
11
12 13
14 15 16
17 18
V+ (V)
INPUT TIMING REQUIRMENTS
~."~two~
3V
WR
OV
t t ow -
AD. AI
3V
OV
DON'T CARE
X
WRITE DATA
X
DON'T CARE
Writing Data to Device
..
__ 3 V - - - - - - - - - - - - - - - " " WR OV
------------------------r,
DON'T CARE
-----------------------r./
-3V---------,.
AD, AI
3V
oV
NEW DATA
DON'T CARE
RS 0 V
tMPW--+l_
Delay Time Required after Reset before Write
__ 3V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WR OV
AD' AI
_
3V
oV
DRIVEN BUS
---------..../
HIZ
DEVICE DATA' OUT
HI Z
DRIVEN BUS
3V
1/0 0 V - - - - - - - - - - - : - - - . . . . /
~tAZ
• Enable must be latched" High" to read back data, otherwise
BUS Is high Z.
Reading Data From Device
Figure 1
Preliminary
7-11
.-r
DG534
~
Siliconix
incorporated
EN TURN ON/OFF TIME TEST CIRCUIT
+15 V
LOGIC INPUT
tr < 20 ns
3V
tf < 20 ns
50%
+
10.l1F
+5 V
OV
SA2
SAl
V+
4/21---+---.::>--;
1/0
WR
0.9 VOUT
LOGIC
INPUT
...----0-; EN
L-~GiN~D~1V~-==::;~=::=~-T-]~ VOUT
SWITCH
OUTPUT
Figure 2
WR TURN ON TIME TEST CIRCUIT
+15 V
+
WR+"""'3=-V""----'
10.l1Fl
fEE~N~,V~L~.lRR:SS-~V~+~SS~A7l~----o+1V
~
Ao +3 V
SA2l---o-...,
4/2
lhru
1/0
SB2
OV
OV
(WR)
VOUT
(
~~------------~
1-
0.9 VOUT
LOGIC INPUT
tr < 20 ns
tf < 20 ns
ADDRESS INPUT
tr < 20 ns
tf < 20 ns
-3 V
Flgure 3
7-12
Preliminary
~
~
DG534
Siliconix
incorporated
TRANSITION TIME and BREAK-BEFORE-MAKE INTERVAL TEST CIRCUIT
+15 V
+
10.ll.Fl
+5 V
EN
VL
RS
+1 V
~--------Ao,
50%
V OUT
SA2
thru t - - o - - - ,
SSI
+--<>--1 Al
Al
OV
SAl
SS21---<:>---'
V+
r-- 200 MHz Bandwidth
o Reduced Insertion
Loss at High Frequencies
o Wideband Signal
Multiplexing
.. Allows Formation
of Large Matrices
o Crosspoint Arrays
" 3 pF Input Capacitance
" 9 pF Output Capacitance
" Low Power (75 J.l.w)
• 90
.n
(max) rDS(ON)
• J.l.P Interface Latches
o Fast Switching (300 ns)
Video Switching/Routing
• High Speed Data Routing
" Minimizes System Power
" Precision Data
Acquisition
• Simplifies J.l.P Interface
e FUR Systems
o Improves Data Throughput
o J.l.P-Based Systems
• ESDS Protection > ±4000 V
DESCRIPTION
The DG535 is a 16-channel multiplexer designed for
routing one of 16 wideband analog or digital input
signals to a single output. It features low input and
output capacitance, low ON resistance, and
n-channel DMOS "T" switches, resulting in wide
bandwidth, low crosstalk and high "OFF" isolation.
The switch FETs were designed to pass signals in
either direction, allowing the DG535 to be used as a
demultiplexer as well as a multiplexer.
The DG535 includes on-board data latches and
decode logic, facilitating a simplified microprocessor interface. Additional Chip Select and Enable
inputs simplify addressing in larger matrices. The
fast transition time of 300 ns (max) and low ON
resistance 90 .n (max) makes the DG535 ideal for
multiplexing high speed signals through precision
data acquisition systems. Single-supply operation
and a low 75 J.l.w power dissipation allow operation
in battery powered systems and in multi-channel
cross points and multiplexers with vastly reduced
power supply requirements.
The technology used in the DG535 is called
D/CMOS. This process combines low-capacitance
DMOS FETs on the same substrate with dense,
high-speed, low-power CMOS. The DMOS FETs are
configured as "T" switches to improve OFF
isolation and reduce crosstalk. The CMOS devices
form all of the latches, decode logic and switch
driver circuitry, resulting in a combination of high
performance and high functional integration.
The DG535 is available in the plastic 28-lead DIP for
the industrial, D suffix (-40 to 85°C), and the
28-lead side braze DIP for military, A suffix (-55 to
125°C) temperature range operations. For surface
mount versions, see the DG536 data sheet.
For more information on the DG535, please refer to
Siliconix Application Note AN86-1.
PIN CONFIGURATION
-
Dual-In-Llne Package
GND
1
Sa
S12
4 S13
S4
S14
S3
S15
S2
1 S16
S1
0
v+
DIS
ST
OS
A3
EN
Ao
A1
Top View
Ordering Information:
DG535AP
DG535DJ
Plastic DIP
DG535AP/883
Side Braze DIP
7-21
DG535
..... Siliconix
incorporated
~
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
EN C8 C8 8T A3
81
82
83
84
85
8S
87
8a
8g
810
811
812
813
814
815
0
X
X
X
0
X
X
X
1
1
1
0
1
1
I
I
I
I
II
O-+---.-«,,-n-Tr-Tr-Tr-Tr-lT---+
r-'-'-'-~- -
Disable
Output
NONE
HIGHZ
Al
Ao
X
X
X
X
0
0
0
0
81
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
S2
S3
0
0
1
1
0
1
1
0
S5
8S
87
0
1
1
0
1
0
1
0
88
89
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
810
811
812
1
1
1
0
1
1
1
1
1
1
0
X
X
X
54
-1
018
EN C8 C8
X
X
X
0
LOWZ
813
814
815
816
1
Maintains
~6~~~~~~~~ ..JI
--'
Input Channel
8elected
kJ.
prevIous
X
switch
condition
LogIc· 1 • : VAH
~
10.5 V
LogIc· 0 • : VAL
::s;;
4.5 V
HIGHZ
or
LOWZ
1. LOW Z, HIGH Z = Impedance of DIsable Output to
GND. DIsable output Is current sInk when any
channel Is selected.
2. Strobe Input (ST) Is level trIggered.
ABSOLUTE MAXIMUM RATINGS
V+ to GND ••.•••••••.•..••.••••••.... -0.3 V to +18 V
DIgItal Inputs •.••.••.... (GND - 0.3 V) to (V+ plus 2 V)
.••.•.••••.••.•••.•..• or 20 mA, whIchever occurs fIrst
Storage Temperature (A Suffix) •...••••..• -65 to 150°C
(0 Suffix) .......... -65 to 125°C
OperatIng Temperature (A Suffix) .•••••••. -55 to 125°C
(0 Suffix) .••••.•••• -40 to 85°C
V 8 ,VO ••••••••••••••••• (GND - 0.3 V) to (V+ plus 2 V)
••..•••••.••...••.••••. or 20 mA, whIchever occurs first
Power DIssIpatIon (Package)·
28-Pln PlastIc DIp·· ••••.•••••••••..•••••••.• 625 mW
28-Pln SIde Braze DIp··· .•••.••.•...••••••.. 1200 mW
Current (any termInal) ContInuous ..........••..• 20 mA
All leads welded or soldered to PC board.
•• Derate 8.3 mW'oC above 75°C
••• Derate 16 mW'oC above 75°C
Current (S or D) Pulsed 1 ms 10% duty cycle •••• 40 mA
7-22
H
DG535
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+=15V,GND=OV
ST, CS = 10.5 V
CS = 4.5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40° C -55 to 125°C
TEMP TYpe
D
SUFFIX
-40 to 85°C
MIN b MAXb MIN b MAXb UNIT
SWITCH
Analog Signal Range d
Drain' - Source
ON Resistance
Resistance Match
Between Channels
rDS(ON)
.6.
rDS(ON)
a
1
VANALOG
Is=-l rnA, VD =3V
V AH =4.5V, V AL =10.5V
Sequence Each Switch ON
EN = 10.5 V
1,3
2
55
1
10
a
10
90
120
90
120
9
9
Source OFF
Leakage Current
IS(OFF)
Vs = 3 V, V D=
EN = 4.5 V
aV
1
2
-10
-100
10
100
-10
-100
10
100
Drain OFF
Leakage Current
ID(OFF)
Vs =OV'VD =3V
EN = 4.5 V
1
2
-10
-500
10
500
-10
-100
10
100
Total Switch ON
Leakage Current
ID(ON)
1
2
-10
-1000
10
1000
-10
-100
10
100
Disable Output
RDISABLE
V S = VD = 3 V
EN = 10.5 V
I DISABLE = 1 rnA
EN = 10.5 V
1,3
2
100
200
250
200
250
V
.n.
nA
.n.
INPUT
Input Voltage High
VAIH
1,2,3
Input Voltage Low
VAIL
1,2,3
10.5
10.5
V
Address Input Current
IAI
VAl =
a Vor
15 V
4.5
1,3
2
<0.01
-10
-100
10
100
4.5
-10
-100
10
100
nA
DYNAMIC
ON State Input Cap.
CS(ON)
V D = Vs = 3 V
1
40
OFF State Input Cap.
CS(OFF)
Vs = 3 V
1
3
OFF State Output Cap.
CD(OFF)
VD = 3 V
1
9
Multiplexer Switching Time
tTRANS
See Figure 4
1
2,3
tOPEN
See Figure 4
1
2,3
EN, CS, CS, ST Turn ON
Time
tON
See Figures 2 & 3
1
2,3
300
300
300
EN, CS, CS Turn OFF
Time
tOFF
See Figure 2
1
2,3
150
150
150
Q
See Figure 5
1
Break-Belore-Make
Interval
pF
300
300
25
25
300
25
ns
Charge Injection
-35
pC
7-23
CGS3S
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V. GND = 0 V
ST. CS = 10.5 V
CS = 4.5 V
LIMITS
1=25°C
A
2=125.85°C
SUFFIX
3=-55.-40°C -55 to 125°C
D
SUFFIX
-40 to 85°C
TEMP TYpe MIN b MAXb MIN b MAXt
UNIT
DYNAMIC (Conttd)
Single-Channel Crosstalk
XTALK (SO)
R IN = 75.0.. RL = 75.0.
f = 5 MHz
See Floure 9
1
-83
Chip Disabled Crosstalk
(See Figure 8)
XTALK(OO)
RL = 75 k.o.. f = 5 MHz
EN = 0.8 V
1
-60
Adjacent Input Crosstalk
(See Figure 10)
XTALK (AI)
1
-72
All Hostile Crosstalk
(See Figure 7)
XTALK(AH)
1
-60
Bandwidth
dB
RIN = 10.0.. RL = 10 k.o.
f = 5 MHz
BW
RL = 75 k.o.. See Figure 6
1
>200
1+
Any One Channel Selected
With Address Inputs at GND
or V+
1.3
2
5
MHz
SUPPLY
Positive Supply Current
operatln~
Voltage
Supply
ange
V+ to GND
50
100
1.2.3
10
16.5
10
50
100
J.LA
16.5
V
MINIMUM INPUT TIMING REQUIREMENTS
Strobe Pulse Width
tsw
See Figure 1
1.2.3
200
200
Ao. A1. A2. A3• CS. CS.
EN Data Valid To Strobe
tow
See Figure 1
1.2.3
100
100
Ao. A 1• A2 • A3. CS. CS.
EN Data Valid After Strobe
two
See Figure 1
1.2.3
50
50
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
d. Analog signal range Is measured from the GND pin to the designated Source (Input) pin.
7-24
ns
DG535
..,. Siliconix
incorporated
~
DIE TOPOGRAPHY
Pad
No.
.......- - - - - - 1 2 7
1
26
25
24
mlls-------I~~I
23
22
21
20 19
27
18
17
28
16
15
1
84 mils
:~~::l
4
5
6
7
8
9
10
1
2
3
4
GND
Sa
5
S5
20X
S4
7
S3
8
9
10
11
S2
12
13
14
15
16
S 1
DIS
CS
CS
EN
Ao
AI
A2
A3
ST
19
20
V+
D
21
S 16
22
23
24
SIS
25
S12
LNDG
26
695 Transistors
16 Diodes
27
427, N-Channel
268, P-Channel
S7
S6
6
17
18
11
Function
28
S14
S13
SII
S10
S9
INPUT TIMING REQUIREMENTS
15 V
ST
\
;(.5 V
.~~
OV
I.
tow
two
15 V
10.5 V
CS, A o,
10.5V
AI, A 2, A3
CS, EN
4.5
v
4.5V
OV
Figure 1
7-25
DG535
Siliconix
incorporated
EN, CS, CS, TURN ON/OFF TIME TEST CIRCUIT
LOGIC INPUT
tr < 20 ns
If < 20 ns
+IS V
+15 V
ISV -
-
-
""
7.5V
CS
OV---J
SWITCH
I
'::.::..!!l~_..2.It-4:-"f"-OOUTPUT
VOUT
SWITCH
OUTPUT
~
0.1 V OUT
--+_....
L -_ _
Figure 2
STROBE (ST) TURN ON TIME TEST CIRCUIT
+1SV
+1SV
LOGIC INPUT
tr < 20 ns
If < 20 ns
ADDRESS INPUT
tr < 20 ns
I, < 20 ns
+15 V
0 V
+15 V - - - - - - " " "
'--t--------/1
ov
10N(ST)~
VOUT
0.9 V OUT
o V _ _ _ _ _ _ _ _ _ _ _ _J
SWITCH
OUTPUT
Figure 3
TRANSITION TIME and BREAK-BEFORE-MAKE INTERVAL TEST CIRCUIT
ADDRESS
LOGIC INPUT
tr < 20 ns
If < 20 ns
+15 V
7.S V
OV
SWITCH
OUTPUT
SWITCH
OUTPUT
VOUT
mRNING
OFF-4--+~
TRANSInON TIME
(ITRANS)
Figure 4
7-26
DG535
.... Siliconix
incorporated
~
BANDWIDTH TEST CIRCUIT
CHARGE INJECTION TEST CIRCUIT
+15 V
+15 V
+15 V
.0. V OUT Is the measurad voltage
error due to charge InJection.
The charge Injection In Coulombs Is
C5~
Q
= CL x
.o.VOUT
+15 V
51GNAL
GENERATOR
(75.0.)
~v
VOUT--q0UT
Figure 6
Figure 5
ALL HOSTILE CROSSTALK - X TALK (AH)
CHANNEL 51 ON
[--5i2fE~~~~~~~~
ALL CHANNEL5 OFF
52
53
S4
54
55
56
57
as
56
57
58
58
59
510
511
512
59
510
511§~
512
513
514
515
516
515
513
S14
516
SIGNAL
..... V
GENERATOR
(75.0.)
(CD)
51
53
RIN
CHIP DISABLED CROSSTALK - X TALK
V OUT
X TALK (AH) = 20 LOG 10 - V -
51GNAL
GENERATOR
(75.0. )
..... V
Figure 7
Figure 8
SINGLE CHANNEL CROSSTALK - X TALK (SC)
ADJACENT INPUT CROSSTALK - X TALK (AI)
CHANNEL 51 ON
I
...AA~
-L
.v..
-=- v 10.0.
A
!I - 5n-l
I
I
Sn
-=-
NOTE5:
1. Any IndivIdual channel between S2 and 816 can be selected
V OUT
2. X TALK(5C) = Average value of 20 LOG 10-VIs scanned sequentially from 52 10 516
Figure
9
51GNAL
GENERATOR
(75.0. )
X TALK(AI) = 20 LOG 10
V5n- l
V
5n
or 20 LOG 10
V5n+l
V
5n
Figure 10
7-27
-
DG535
Siliconix
incorporated
BURN-IN CIRCUIT
+15 V
27nl----+
210----;
14
Note: All Resistors are 10 k.n. unless otherwise specified
PIN DESCRIPTION
PIN NUMBER
SYMBOL
2
3
4
5
6
7
8
9
10
GND
58
57
56
55
54
53
52
51
DI5
11,12,13
C5,C5,EN
14 - 17
Ao - A3
18
19
20
V+
21
22
23
24
25
26
27
28
516
515
514
513
512
511
510
59
7-28
5T
D
DESCRIPTION
Analog 51gnal Ground and Most Negative Potential
Channel 8 Analog Input
Channel 7 Analog Input
Channel 6 Analog Input
Channel 5 Analog Input
Channel 4 Analog Input
Channel 3 Analog Input
Channel ,2 Analog Input
Channel 1 Analog Input
Open drain high Impedance output when DG535 Is disabled (all channels OFF). When
DG535 Is enabled (any channel selected) this output Is current sink to Analog GND.
Logic Inputs to select required Multlplexer(s) when using several Multiplexers In a
system
Four binary address Inputs that determine which one of the sixteen channels Is
selected.
5trobe Input that latches Ao, Al, A2, A3, CS ,C5, EN
Positive supply voltage
Analog output of Multiplexer or Analog Input If device used In Demultiplexer
configuration.
Channel 16 Analog Input
Channel 15 Analog Input
Channel 14 Analog Input
Channel 13 Analog Input
Channel 12 Analog Input
Channel 11 Analog Input
Channel 10 Analog Input
Channel 9 Analog Input
CGS3S
..,. Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
rOS(ON) VS. Vo and
Power Supply Voltage
rOS(ON) vs. Voand
Temperature
Iii'
:!:
::t:
B
Z'
B
(fI
0
<-
400
360
320
280
240
200
160
120
80
40
o
300
270
240 210
180
~V+
+15~L
GND = 0 V
+125 0
~
Ff1
§.
Z'
"'0
..-' ~oc'l
150
<-
5toC-
I
2
4
6
./
I GND-OV}
I T A = 25°C
o
10
Vo - DRAIN VOLTAGE (VOLTS)
2
4
6
14r-~~~~r-~-1
Supply Current vs.
Supply Voltage and Temperature
14
12
~
12
!zw
If
::J
10
~
6
Dl
4
±
2
~
11 GND = 0 VI
L
+125°C
8
V
U
c..
c..
/-
2~--+---~--~---+--~
O~
__
8
1000
~
Z'
B
100
~
__
~
10
__
~
14
12
__
16
~
~
0
18
10 11
.&'5°C
l/ k' Ll
II::V
I""'" V r o
r-
~ t:.---
12
13 14
IO(ON) + IS(ON) vs.
Temperature
IO(OFF) and I SCOFF) vs.
Temperature
H
V+ = +15 V I
GND = 0 V
Vo=Vs =3vl
./
V'
10
/
0.1
_0
0.01
l/
V
/
l/
V
0.001
-55 -35 -15 5
E
8~
w ~
~~
(fie:
"Ce:
c: ::J
.,
u
Et!:l
8~
Y
..
15 16 17 18
V+ - SUPPLY VOLTAGE (VOLTS)
+
Z'
__
V~
V+ - SUPPLY VOLTAGE (VOLTS)
_(fI
B
~
10
8
Vo - DRAIN VOLTAGE (VOLTS)
Logic Input Switching Threshold
VS. Supply voltage (V+)
I
L
./
.-'. I'" .... 1'"
-'
o
8
/
'I'
1
/
60
30
1
J
B 120
~ 90
. / //
o
~8V r- +1~ V 1-1+15 V
0.1
6~ 0.01
~
0
25 45 65 85 105125
TEMPERATURE (0C)
0.0011.-.......I... . .--I._.l...-..J.............--I
-55 -35 -15 5 25 45 65 85 105125
TEMPERATURE (0C)
7-29
DG535
. , . Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
S
Adjacent Input Crosstalk
vs. Frequency
-100
-3 dB Bandwidth
(Insertion Loss vs. F'requency)
+4
~
~
ffi
~
.......
-80
RIN = 10.0.
-60
-40
IIIII
TEST CIRCUIT
See Figure 10
UIIL
0.1
~
ffi
5o
~
~
o
9
~
111111
o
~
Ul
Ul
r- RL = 10 k.o.
-20 I -
S
0
~
u
;;
S
I
-'111111
1
10
FREQUENCY (MHz)
-...
-80
-70
-60
-50
-40
~
w
::E
F
CJ
z
...
I
TEST CIRCUIT
See Figure 8
11111
10
100
:f
~
==
Ul
-
.,.....
- -"""" ""
-+
-...-
TEMPERAlURE ("C)
7-30
100
FREQUENCY (MHz)
200
180 ~ TEST CIRCUIT
I
See Figures 2. 3, 4
160
tON
140
-"......
120
~
100
80
..
60
~REtK-~EFfREiM'lKE
40
20
OFF
0
-55 -35 -15 5 25 45 65 85 105125
......
1000
.......
-80
-70
-60
Single Channel Crosstalk
vs. Frequency
tON, tOFF and Break-Before-Make
vs. Temperature
'iii'
100
All Hostile Crosstalk
vs. Frequency
FREQUENCY (MHz)
.s
I 11111111
10
-50 rR1N = 10.0.
......
-40 I--RL = 10 k.o.
,III
-30·
11111
-20 r-TEST CIRCUIT
See Figure 7
-10 I-11111
I UllI
o
0.1
10
11111111
11111
1111
111111
-90
~
0.1
r--
-16
""'
TEST CIRCUIT
See Figure 6
FREQUENCY (MHz)
t"'-..
o
dB POINt / '
1111
-20
100
RL = 75.0.
-30
-20 r--10 I--
1'~3
Ul
~
.......
RL= 50.0.
-8
z0
~ -12
w
Chip Disabled Crosstalk
vs. Frequency
-90
-4
-80
- -...
-60
r-
S -100
~
-40
-20 I--
o
0.1
'
RIN = 75.0.
RL = 75.0.
11111
I
11111
I
....
TEST CIRCUIT
See Figure 9
11111
1
II
WlI
10
FREQUENCY (MHz)
100
DG535
..... Siliconix
incorporated
~
DETAILED DESCRIPTION
The DG535 is a 16-channel single-ended multiplexer
with on-chip address logic and control latches.
connected via two series switches (second level) to
a common DRAIN output.
The circuit connects one of sixteen inputs (S1,
S2, ... S16) to a common output (D) under the
control of a 4 bit binary address (Ao to As). The
specific input channel selected for each address is
given in the Truth Table.
In order to improve crosstalk all sixteen first level
switches are configured as "T" switches (see
Figure 12).
All four address inputs have on-Chip data latches
which are controlled by the Strobe (ST) input.
These latches are transparent when Strobe is high
but they maintain the chosen address when Strobe
goes low. To facilitate easy microprocessor control
in large matrices a choice of 3 independent logic
With this method SW2 operates out of phase with
SW1 and SW3. In the ON condition SW1 and SW3
are closed with SW2 open whereas in the OFF
condition SW1 and SW3 are open and SW2 closed.
In the OFF condition the input to SW3 is effectively
the isolation leakage of SW1 working into the ON
resistance of SW2 (typically 200 0.).
inputs (EN, CS and CS) are provided on chip.
These inputs are gated together (see Figure 11)
and only when EN =CS = 1 and CS = 0 is true can
an output switch be selected by the appropriate
address input (Ao to A3). This necessary logic
condition can then be latched by Strobe (ST) going
low.
SIGNALGND
o
E
Figure 12.
-
• T • Switch Arrangement
C
o
o
E
L
o
G
c
ST
1----------'
FIgure 11.
OS,
The two second level series switches further
improve crosstalk and help to minimize output
capacitance.
The DIS output (Pin 7) can be used to signal
external circuitry. DIS is a high impedance to GND
when no channel is selected and a low impedance
to GND when anyone channel is selected.
CS, EN, ST Control Logic
Break-before-make switching is included to prevent
momentary shorting of an input channel when
changing from one input to another.
The device features a two-level switch arrangement
whereby two banks of eight switches (first level) are
The DG535 has extensive applications where any
high frequency video, audio or digital Signals are
switched or routed. Exceptional crosstalk and
bandwidth performance is achieved by using N
channel DMOS FETs for the "T" and series
switches.
A cross section of a switch is shown in Figure 13.
7-31
..
DG535
~
~
Siliconix
incorporated
DETAILED DESCRIPTION (Cont'd)
is necessary. Biasing is not required, however, in
applications where signals are always positive with
respect to the GND or substrate connection, or in
applications involving multiplexing of low level (up to
± 200 mY) signals, where forward biasing of the PN
substrate-source/drain terminals would not occur.
GND
Biasing can be accomplished in a number of ways,
the simplest of which is a resistive potential divider
and a few dc blocking capacitors as shown in Figure
14.
+15 V
Figure 13.
Cross-Section of a Single
DMOS Switch
+ (
It can clearly be seen from Figure 13 that there
exists a PN junction between the substrate and the
drain/source terminals.
Should a signal which is negative with respect to the
substrate (GND pin) be connected to a source or
drain terminal, then the PN junction will become
forward biased and current will flow between the
signal source and GND. This effective shorting of
the signal source to GND will not necessarily cause
any damage to the device, provided that the total
current flowing is less than the maximum rating,
(i.e. 20 mAl.
Since no PN junctions exist between the signal path
and V+, positive overvoltages are not a problem,
unless the breakdown voltage of the DMOS source
terminal (see Figure 13) (+18 V) is exceeded.
Positive overvoltage conditions must not exceed
+ 18 V with respect to the GND pin. If this condition
is possible (e.g. transients in the signal), then a
diode or Zener clamp may be used to prevent
breakdown occuring.
The overvoltage conditions described may exist if
the supplies are collapsed while a signal is present
on the inputs. If this condition is unavoidable, then
the necessary steps outlined above should be taken
to protect the device
100 jJ.F/16 V
TANTALUM
DG535
GND
Figure 14.
D
_
\c;'
ANALOG
SIGNAL
OUT
100 jJ.F/16 V
TANTALUM
Simple Bias Circuit
R1 and R2 are chosen to suit the appropriate
biasing requirements. For video applicatiDns,
approximately 3 V of bias is required for optimal
differential gain and phase performance. Capacitor
C1 blocks the DC bias voltage from being coupled
back to the analog signal source and C2 blocks the
DC bias from the output signal. Both C1 and C2
should be tantalum or ceramic disc type capacitors
in order to operate efficiently at high frequencies.
Active bias circuits are recommended if rapid
switching time between channels is required.
An alternative method would be to offset the supply
voltages (see Figure 15).
DC BIASING
Decoupling would have to be applied to the
negative eupply to ensure that the substrate is well
referenced to Signal ground. Again the capacitors
should be of a type offering good high frequency
characteristics.
To avoid negative overvoltage conditions and
subsequent distortion of analog signals, dc biasing
Level shifting of the logic signals may be necessary
using this offset supply arrangement.
7-32
DG535
.... 8i1iconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
+12 V
ANALOG
SIGNAL
IN
v+
0-----15
ANALOG
SIGNAL
OUT
CG535 D
the PC board and/or connecting leads will
considerably degrade the A.C. performance.
Hence, signal paths must be kept as short as
practically possible, with extensive ground planes
separating signal tracks.
GND
a-CHANNEL VIDEO MULTIPLEXING
DECOUPLING
CAPACITORS
CIRCUIT LAYOUT
If only 8 channels are needed, the crosstalk can be
further reduced by using inputs from the top and
bottom halves of the DG535 two-level switching
architecture and grounding alternating signal input
pins. For example, use 81, 83, 85, 87, 89, 811,
813, and 815 for the signal paths and ground the
remaining inputs 82, 84, ... 816 and provide a logic
"0" to Ao. This will provide additional shielding
between channels for reduced crosstalk, and the
eight signal channels will be addressed via the three
addressing M8Bs (Figure 16).
Good circuit board layout and extensive shielding is
essential for optimizing the high frequency
performance of the DG535. 8tray capacitances on
For higher frequency applications or applications
where even lower levels of crosstalk are required,
the 8i1iconix DG536 is recommended.
' - - - - - - -3V
Figure 15.
DG535 With Offset Supply
Note: TTL to CM08 level shifting is easily obtained
by using a MC14504B.
Truth Table
EN cs
Os
0
X
X
X
0
X
X
X
ST Aa A2 AI AO
1
X
X
X
Input Channel
X
Pinout
Disable
Selected
Output
NONE
HIGH Z
1
GND
57
1
1
0
1
0
0
0
0
51
0
0
1
0
sa
0
1
0
0
55
0
1
1
1
0
57
0
0
0
59
1
0
1
0
511
GND
1
1
0
0
513
51
1
1
1
0
SIS
GND
55
GND
LOWZ
X
X
0
X
HIGH Z
or
LOWZ
previous
X
X
X
switch
condition
~
10.5 V
Logic" 0 • : VAL::::;;
4.5 V
Logic" 1 • : VAH
53
SIS
v+
Maintains
X
GND
511
Figure 16.
ST
CS
GND
A3
AI
The DG535 as an 8-Channel Video Multiplexer
7-33
DG536
16-Channel
WidebandNideo Multiplexer
~
~
Siliconix
incorporated
BENEFITS
APPLICATIONS
• Improved OFF Isolation
• Video Switching/Routing
• Reduced Insertion
Loss at High Frequencies
• High Speed Data Routing
• 300 MHz Bandwidth
• 4 pF (max) Input and 12 pF
Output Capacitance
• Reduced Input Buffer
Requirements
• Low Power (75/J.W)
• Minimizes System Power
• Precision Data
Acquisition
• Reduced Noise
• Crosspoint Arrays
• Simplifies Bus Interface
• FUR Systems
FEATURES
• -100 dB Single Channel
Crosstalk at 5 MHz
.90
n
(max)
• j.LP Interface Latches
• ESOS Protection > ± 4000
• Wideband Signal
Multiplexing
• Audio Switching
DESCRIPTION
The DG536 is a 16-Channel multiplexer designed for
routing one of 16 wldeband analog or digital input
signals to a single output. It features low input and
output capacitance, low ON resistance, and
n-channel DMOS "T" switches, resulting in wide
bandwidth, low crosstalk and high "OFF" isolation.
The switch FETs were deSigned to pass signals in
either direction, allowing the DG536 to be used as a
demultiplexer as well as a multiplexer.
The DG536 is available in the plastic PLCC-44 for
Industrial, D suffix (-40 to 85°C), and the 44-lead
ceramic J-Iead hermetic package for military, A
suffix (-55 to 125°C) temperature ranges. For
through-hole (DIP) versions, see the DG535 data
sheet.
For more information on the DG536, please refer to
Siliconix Application Note AN86-1.
PIN CONFIGURATION
The DG536 includes on-board data latches and
decode logic, facilitating a simplified microprocessor interface. Additional Chip Select and Enable
inputs simplify addressing in larger matrices. The
fast transition time of 300 ns' (max) and low ON
resistance 90 n (max) makes the DG536 ideal for
multiplexing high speed signals through fast data
acquisition systems. Single-supply operation and a
low 75 j.LW power dissipation allows operation in
battery powered systems and in multi-channel
cross points and multiplexers with vastly reduced
power supply requirements.
The technology used in the DG536 is called
D/CMOS. This process combines low-capacitance
DMOS FETs on the same substrate with dense,
high-speed, low-power CMOS.
7-34
6 5 4
3 2
14443424140
GS1
S3G
S4G
S5 G
N__ GS2
N__ G
N__
N__
N__
N
7
8
9
10
11
12
13
14
15
16
17
DISD
00
0
00
DS6
PLCC-44, J LEAD
PLASTIC PACKAGE
Top View
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
Order Number:
DG536DN
W'1P'"
~
DG536
Siliconix
incorporated
PIN CONFIGURATION (Cont'd)
6 5 4
3 2
1 44434241 40
7
39
8
38
37
9
10
36
CLCC - 44
44-PIN J LEAD
CERAMIC PACKAGE
11
12
35
34
Top View
13
33
Pin Circle same as
Plastic Package
14
15
32
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 2B
Order Number:
DG536AM/883
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
EN C8 C8 8T 1':3 A2 Al
81
82
83
84
85
86
87
88
89
810 o-+-i-i-i-i-i-;...or,;,ti-~
~1 o-+-.-i-i-i-~~n-ti-~
0
X
X
X
0
X
X
X
1
1
1--1-<> D
~2o-~-'~-r-r~~~n-1
1
o-+-,........;r-;-O;-li'l'iT-;,-n-n-+-~If""'"
~4 o--I--.-i-Oili'l'iT-Tr-irir-ri4
I
8 15 o-+--r~,"'iT-rr-Tr-rr"1T""rr--+
I I
8 16 G-t;::!!ii:ric:iJ::i:cric:u:::;
I I
813
1
0
1
:l_.J
;::::::=;--;::n:oo:::=,- --1
DI8
X
X
X
AO
X
Input Channel
Selected
Disable
Output
NONE
HIGH Z
0
0
0
0
81
0
0
0
1
82
0
0
0
0
1
1
0
83
1
84
0
1
0
0
85
0
1
0
1
66
0
1
0
1
1
1
0
1
8B
1
0
0
0
89
1
0
0
1
810
1
0
1
0
811
1
0
1
1
812
1
1
0
0
813
1
1
0
1
814
1
1
1
0
815
1
1
1
1
87
816
Maintains
X
X
X
0
X
X
X
X
LOWZ
previous
switch
HIGHZ
or
LOWZ
condition
Logic· 1 " : VAH ~ 10.5 V
Logic· 0 " : VAL ~ 4.5 V
1. LOW Z, HIGH Z = Impedance of Disable Output to
GND. Disable output Is current sink when any
channel Is selected.
2. Strobe Input (ST) Is level triggered.
7-35
.-F' Siliconix
DG536
~
incorporated
ABSOLUTE MAXIMUM RATINGS
V+ to GND ........................... -0.3 V to +18 V
Storage Temperature (A Suffix) ........... -65 to 150·C
(0 Suffix) ..•......• -65 to 125·C
Digital Inputs ........... (GND - 0.3 V) to (V+ plus 2 V)
•.•................... or 20 mA, whlohever ooours first
Operating Temperature (A Suffix) ......... -55 to 125·C
(0 Suffix) .......... -40 to 85·C
VS,YO .................. (GND - 0.3 V) to V+ plus 2 V)
.•.................•.. or 20 mA, whlohever occurs first
Power Dissipation (Package)·
44-Pln J Lead Ceramic·· ..................... 825 mW
44-Pln J Lead Plastic··· ...........•......... 450 mW
Current (any terminal) Continuous ............... 20 mA
All leads welded or soldered to PC board.
•• Derate 11 mW'·C above 75·C
••• Derate 6 mW'·C above 75·C
Current (S or D) Pulsed 1 ms 10% duty cycle .... 40 mA
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V, GND = 0 V
ST, CS = 10.5 V
CS = 4.5 V
LIMITS
1=2S·C
A
2=12S,85·C
SUFFIX
3=-55,-40·C -55 to 125°C
D
SUFFIX
-40 to 85°C
TEMP TYpd MIN b MAXb MIN b MAX
UNIT
SWITCH
Analog Signal Range e
1
VANALOG
Drain - Souroe
ON Resistance
rOS(ON)
Reslstanoe Match
Between Channels
rOS(ON)
f:J.
Is = 1 mA, Vo = 3 V
V AH =4.5V, V AL =10.5V
Sequenoe Eaoh Swltoh ON
EN = 10.5 V
1,3
2
0
55
10
0
10
90
120
90
120
9
9
.0.
1
Souroe OFF
Leakage Current
IS(OFF)
Vs =3V, Vo=OV
EN = 4.5 V
1
2
-10
-100
10
100
-10
-100
10
100
Drain OFF
Leakage Current
IO(OFF)
Vs = 0 V, Vo = 3 V
EN = 4.5 V
1
2
-10
-500
10
500
-10
-100
10
100
Total Switch ON
Leakage Current
IO(ON)
Vs= Vo=3V
EN = 10.5 V
1
2
-10
-1000
10
1000
-10
-100
10
100
ROISABLE
IOISABLE = 1 mA
EN = 10.5 V
Disable Output
V
1,3
2
100
200
250
200
250
nA
.0.
INPUT
Input Voltage High
VAIH
1,2,3
Input Voltage Low
VAIL
1,2,3
10.5
10.5
V
4.5
IAI
VA = GND or V+
1
2
<0.01
ON State Input Cap7
CS(ON)
Vo = Vs = 3 V
1
32
45
45
OFF State Input Cap!'
cS(OFF)
Vs = 3 V
1
2
4
4
OFF State Output Cap.c
Co (OFF)
Vo
=3 V
1
8
12
12
Address Input Current
-10
-100
10
100
4.5
-10
-100
10
100
JJ.A
DYNAMIC
7-36
pF
DG536
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+=15V,GND=OV
ST, CS = 10.5 V
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40°C -55 to 125°C
D
SUFFIX
-40 to 85°C
SYMBOL
CS = 4.5 V
tTRANS
See Figure 4
1
2,3
tOPEN
See Figure 4
1
2,3
tON
See Figures 2 & 3
1
2,3
300
300
300
tOFF
See Figure 2
1
2,3
150
150
150
Q
See Figure 5
1
-35
Single-Channel Crosstalk
XTALK (SO)
R IN = 75.n, RL = 75.n
1=5 MHz
See Flaure 9
1
-100
Chip Disabled Crosstalk
(See Figure 8)
XTALK(OO)
R IN = RL = 75 .n, I = 5 MHz
EN = 4.5 V
1
-85
PARAMETER
TEMP TYpd
MIN b MAXb MIN b MAXt UNIT
DYNAMIC (Cont'd)
Multiplexer Switching Time
Break-Belore-Make
Interval
300
300
300
25
25
25
ns
EN, CS, CS, ST Turn ON
Time
EN, CS,
Time
Cs Turn
OFF
Charge Injection
pC
dB
Adjacent Input Crosstalk
(See Figure 10)
XTALK
All Hostile Crosstalk C
(See Figure 7)
XTALK(AH)
Bandwidth
(AI)
1
-92
1
-74
RIN = 10.n, RL = 10 k.n
1=5 MHz
BW
RL = 50.n, See Figure 6
1
300
Supply Current
1+
Any One Channel Selected
With Address Inputs at GND
or V+
1,3
2
5
Voltage Current
V+
-60
-60
MHz
SUPPLY
50
100
1,2,3
10
16.5
10
50
100
J.LA
16.5
V
MINIMUM INPUT TIMING REQUIREMENTS
Strobe Pulse Width
tsw
See Figure 1
1,2,3
200
200
AD, AI, A 2 , A 3 , CS. CS.
EN Data Valid To Strobe
tow
See Figure 1
1,2,3
100
100
AD, AI, A 2 , A 3 , CS, CS,
EN Data Valid Alter Strobe
two
See Figure 1
1,2,3
50
50
ns
NOTES:
a. Reier to PROCESS OPTION FLOWCHART lor additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
o. Guaranteed by design, not subject to production test.
d. Typical values are lor DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Analog signal range Is measured Irom the GND pin to the designated Source (Input) pin.
7-37
•
DG536
...... Siliconix
incorporated
~
DIE TOPOGRAPHY
9
u
38
10
36
Pad Function
No.
1
S3
2
GND
3
S2
4
GND
5
Sl
6
GND
7
DIS
r
11
35
12
34 84 mils
8
9
~ ~::;:~::~::~:;~~~~~~~~:: 1
17 18 19 20 21 22 23 24 25 26 27 28 29 30
20X
LNDG
695 Transistors
16 Diodes
427. N-Channel
268. P-Channel
INPUT TIMING REQUIREMENTS
15V
ST
OV
f'V
\
.~~
tow
two
15V
10.5 V
10.5 V
4.5V
4.5 V
CS.
Ao. Al. A2. A3
CS. EN
OV
Figure 1
7-38
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CS
CS
EN
AO
A1
A2
A3
ST
V+
D
GND
S16
GND
S15
GND
S14
GND
S13
GND
S12
GND
S11
GND
Pad
No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
S10
GND
S9
GND
S8
GND
57
GND
56
GND
S5
GND
S4
GND
~
~
DG536
Siliconix
incorporated
EN, CS, CS, TURN ON/OFF TIME TEST CIRCUIT
+151,1
LOGIC INPLrr
tr < 20 ns
If < 20 ns
+15 V
15 V -
-
-
""'"
~
Os
----
7.5 V
EN or OS
OV---J '-------'
SWITCH
1t__~__~OLrrPUT
VOLrr
1~~~__-J~__
~
SWITCH
OUTPUT
0.1VOUT
L--_ _
+---'
Figure 2
STROBE (ST) TURN ON TIME TEST CIRCUIT
+15 V
+15 V
LOGIC INPUT
tr < 20 ns
If <20 ns
ADDRESS INPUT
tr < 20 ns
If < 20 ns
+15 V
0 V
+15 V - - - - - - - - - - - - ,
'-+-------------
01,1
VOUT
ION(ST)~
{I
0.9VOUT
OV------------------------~
Figure 3
TRANSITION TIME and BREAK-BEFORE-MAKE INTERVAL TEST CIRCUIT
ADDRESS
LOGIC INPUT
tr < 20 ns
If < 20 ns
+15 V
7.5 V
01,1
SWITCH
OUTPUT
~~RNING
SWITCH
OUTPUT
VOUT
OFF-t----joO-\
TRANSITION TIME
(ITRANS)
Figure 4
7-39
frY' Siliconix
CG536
~
BANDWIDTH TEST CIRCUIT
CHARGE INJECTION TEST CIRCUIT
+15 V
incorporated
+15 V
+15 V
+15 V
SWITCH
OUTPUT
l:!. VOUT Is the measured voltage
error due to charge InJection.
CS~
The charge Injection In Coulombs Is
Q=CLxl:!.VOUT
SIGNAL
GENERATOR
(75.0. )
~V
V O U T - - - q OUT
Figure 6
Figure 6
ALL HOSTILE CROSSTALK - X TALK (AH)
CHIP DISABLED CROSSTALK - X TALK (CD)
ALL CHANNELS OFF
CHANNEL Sl ON
S2
53
S4
S5
S6
S7
S8
59
S10
Sll
S12
S13
S14
ii£:::~::~~~i::--:l
S4
~
S6
S7
58
S9
S10
511
S12
513
514
515
S16
t-:::::=:::::::t:::::t
S15
S16+SIGNAL
GENERATOR
(75.0.)
:.....--
S5
v
VOUT
X TALK (AH) = 20 LOG 10 - V -
SIGNAL
GENERATOR
(75.0.)
_v
Figure 7
Figure 8
SINGLE CHANNEL CROSSTALK - X TALK(SC)
ADJACENT INPUT CROSSTALK - X TALK (AI)
CHANNEL Sl ON
I
...AA~
v,~ .0.
: - Sn-l
'*'
I
I
Sn
SIGNAL-=GENERATOR
(75.0.)
NOTES:
1. Any Individual channal between S2 and S16 can be selected
V OUT
2. X TALK(SC) = Average value of 20 LOG 10-VIs scanned sequentially from S2 to S16
Figure 9
7-40
X TALK
(AI)
VSn 1
=20 LOG 10---VSn
Figure 10
or
20 LOG
10
VSn+l
VSn
DG536
..,. Siliconix
incorporated
~
BURN-IN CIRCUIT
Note: All Resistors are 10k.n unless otherwise specified
PIN DESCRIPTION
PIN NUMBER
SYMBOL
3
5
7
S3
82
81
DI8
8,9,10
CS ,CS,EN
11 - 14
15
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2,4,6,18,20,
22,24,26,28,
30,32,34,36,
38,40,42,44
Ao - A3
8T
V+
D
816
815
814
813
812
811
810
89
88
87
86
85
84
GND
DESCRIPTION
Channel 3 Analog Input
Channel 2 Analog Input
Channel 1 Analog Input
Open drain Impedance output when the DG536 Is disabled (all channels OFF). When the
DG536 Is enabled (any channel selected) this output Is current sink to Analog GND.
Logic Inputs to select required Multlplexer(s) when using several Multiplexers
In a system.
Four binary address Inputs that determine which one of the sixteen channels
Is selected.
8trobe Input that latches AO, AI, A2, A3, CS ,C8, EN
Positive supply voltage
Analog output of Multiplexer or Analog Input If device used In Demultiplexer
configuration.
Channel 16 Analog Input
Channel 15 Analog Input
Channel 14 Analog Input
Channel 13 Analog Input
Channel 12 Analog Input
Channel 11 Analog Input
Channel 10 Analog Input
Channel 9 Analog Input
Channel 8 Analog Input
Channel 7 Analog Input
Channel 6 Analog Input
Channel 5 Analog Input
Channel 4 Analog Input
Analog signal ground and most negative potential.
All pins should be connected externally to ensure dynamic performance.
7-41
..
DG536
.... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
400
H
360
320
tii'
rOS(ON) vs. Vo and
rOS(ON) vs. Vo and
Temperature
Power Supply Voltage
300
:c
9.
:::E
240
200
2
9.
CIl
2
9.
CIl
I"JL
. / //
160
120
rP
:c
9.
+125· C-/-;,
0
c:::
+25·C~~
............
80
40
2
4
120
/
90
....".
14
F
12
o
I
8
6
I
2
0
10
12
14
16
10
H
V+=+15 V
GNO=OV
Vo =Vs =3V
L
I
V
~~
+
9.
10
61--+--+--+--+--.II'--~--,f--I
10
0.01
13
14
15
16
17
18
It
9. ~
~~
1000
r-""I"--'~'T'""':"'--r-""I"--'r--'T'"""
100
10
1!!5
u
OJ
/'
_0
12
CIlc:::
...V
0.1
11
V+ - SUPPLY VOLTAGE (\IOLTS)
IO(OFF) and I S(OFF) VS.
Temperature
l
.J!l
2
8
6
8r--+--t--r--r---r~~~~
18
1000
2
4
2
10r--+--+--+--+-
IO(ON) + IS(ON) vs.
Temperature
9.
F
12
V+ - SUPPLY VOLTAGE (\IOLTS)
100
I GNO-O~
±
8
~
L
......
14
~
10
/
-'
Supply Current vs.
Supply Voltage and Temperature
:i:'j!%
~~
If
/
J
Vo - DRAIN VOLTAGE (\IOLTS)
CJ
~~
/
1/
I TA=25C
10
c:::
Z
J
~
30
Logic Input Switching Threshold
VS. Supply voltage (V+)
ffi
I
J
150
Vo - DRAIN VOLTAGE (\IOLTS)
90
1--1 +15 v
+1! V
0
8
6
I--
J
180
I
0
-
210
60
~-ts·c-
0
1+8 V
f----
240
tii'
280
:::E
II
270
I
V+=+15V
GNO = 0 V
0.01
[LV
0.00 1
-55 -35 -15
7-42
5
25 45
65
65
105 125
0.001 ..........L......L_..L........_ ..........L......L_..L........I
-55 -35 -15 5
25 45 65 85 105 125
DG536
WY'Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
iii'
Adjacent Input Crosstalk
vs. Frequency
-120
"'r--
3
~
-100
IIIRIN II U
...
= 10.(}
r-... ...
-60
I"L
-40
I1I1
II
11111
o
9
Z
0
-4
I
1111-3 dB POINJ: /
15
-12
:;!!;
-16
Ul
II 11111
0.1
TEST CIRCUIT
See Figure 6
-
11111
-20
10
100
Chip Disabled Crosstalk
vs. Frequenoy
All Hostile Crosstalk
vs. Frequenoy
iii'
-160
~
RL
RL =50.(}
i-
11111
3
-160
i
-140
Iii!
=75.n~
,,"I
TEST CIRCUIT
See Figure 8
r-
I
-80
~
-80
::J:
~
III
-120
0;;:
-100
U
~
0
10
-40
-20
-RIN = 10.(}
-RL = 10k.(}
~
180
I!:J
Z
Z
~
160
I=t
iii'
120
--
,.,.
100
80
60
-
~
~ I"""
~ r-
.- I-~
~
BfEA~ BEjOR1 M,!E
40
20
0
-55 -35 -15
tOFF
5
25
45
65
~
I
11111
10
100
FREQUENCY (MH71
TEST CIRCUIT
See Figures 2, 3, 4 t-tON
140
TEST CIRCUIT
See Figure 7
0.1
tON, tOFFand Break-Betore-Make
vs. Temperature
200
~
1111
11111
o
100
RIN =75.(}
RL = 75.(}
o;;::::~
FREQUENCY (MHll
:E
F
1000
-180
IlIfi
w
100
FREQUENCY (MH71
-180
...
:g
I
II 11111
10
FREQUENCY (MH71
iii'
;s
i"'~
RL = 50.(}
-8
0
TEST CIRCUIT
See Figure 10
i-
-20
Ul
Ul
i""-.~
RIN =75.(}
iii'
-3 dB Bandwidth
(Insertion Loss vs. Frequency)
3
.....
-80
+4
85 105 125
3
~
~
Single Channel Crosstalk
vs. Frequency
-180
-160
-140
Ul
-120
5
-100
!i::l
-80
0
Z
~
-60
U
-40
I!:J
~
Z
-20
!i'i
0
'
...
RIN =76.(}
RL = 76.(}
m.:....
III
-
TEST CIRCUIT
See Figure 9
11111
0.1
II 11111
10
100
FREQUENCY (MH71
7-43
DG536
~
~
Siliconix
incorporated
DETAILED DESCRIPTION
The DG536 is a 16-channel single-ended multiplexer
with on-chip address logic and control latches.
connected via two series switches (second level) to
a common DRAIN output.
The circuit connects one of sixteen inputs (S1,
S2, ... S16) to a common output (D) under the
control of a 4 bit binary address (Ao to A3). The
specific input channel selected for each address is
given in the Truth Table.
In order to improve crosstalk all sixteen first level
switches are configured as "T" switches (see
Figure 12).
All four address inputs have on-chip data latches
which are controlled by the Strobe (ST) input.
These latches are transparent when Strobe is high
but they maintain the chosen address when Strobe
goes low. To facilitate easy microprocessor control
in large matrices a choice of 3 independent logic
With this method SW2 operates out of phase with
SW1 and SW3. In the ON condition SW1 and SW3
are closed with SW2 open where as in the OFF
condition SW1 and SW3 are open and SW2 closed.
In the OFF condition the input to SW3 is effectively
the isolation leakage of SW1 working into the ON
resistance of SW2 (typically 200 a).
inputs (EN, CS and CS) are provided on chip.
These inputs are gated together (see Figure 11)
and only when EN = CS = 1 and CS = 0 is true can
an output switch be selected by the appropriate
address input (Ao to A3)' This necessary logic
condition can then be latched by Stroba (ST) going
low.
A - SIGNAL
OUT
SIGNAL GND
D
E
Figure 12.
"T' Switch Arrangement
C
o
D
E
o
G
c
Figure 11.
The DIS output (Pin 7) can be used to signal
external circuitry. DIS is a high impedance to GND
when no channel is selected and a low impedance
to GND when anyone channel is selected.
CS. CS. EN. ST Control Logic
Break-before-make switching is included to prevent
momentary shorting of an input channel when
changing from one input to another.
The device features a two-level switch arrangement
whereby two banks of eight switches (first level) are
7-44
The two second level series switches further
improve crosstalk and help to minimize output
capacitance.
The DG536 has extensive applications where any
high frequency video, audio or digital signals are
switched or routed. Exceptional crosstalk and
bandwidth performance is achieved by using N
channel DMOS FETs for the "T" and series
switches.
A cross section of a switch is shown in Figure 13.
DG536
tI'7' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
however, in applications where signals are always
positive with respect to the GND or substrate
connection, or in applications involving multiplexing
of low level (up to ± 200 mY) signals, where forward
biasing of the PN substrate-source/drain terminals
would not occur.
SUBSTRATE
GND
Biasing can be accomplished in a number of ways,
the simplest of which is a resistive potential divider
and a few dc blocking capacitors as shown in Figure
14.
Figure 13.
+15 V
Cross-Section of a Single
DMOS Switch
It can clearly be seen from Figure 13 that there
exists a PN junction between the substrate and the
drain/source terminals.
Should a signal which is negative with respect to the
substrate (GND pin) be connected to a source or
drain terminal, then the PN junction will become
forward biased and current will flow between the
signal source and GND. This effective shorting of
the signal source to GND will not necessarily cause
any damage to the device, provided that the total
current flowing is less than the maximum rating,
(i.e. 20 mA).
Since no PN junctions exist between the signal path
and V+, positive overvoltages are not a problem,
unless the breakdown voltage of the DMOS source
terminal (see Figure 13) (+18 V) is exceeded.
Positive overvoltage conditions must not exceed
+18 V with respect to the GND pin. If this condition
is possible (e.g. transients in the signal), then a
diode or Zener clamp may be used to prevent
breakdown occuring.
The overvoltage conditions described may exist if
the supplies are collapsed while a signal is present
on the inputs. If this condition is unavoidable, then
the necessary steps outlined above should be taken
to protect the device
DC BIASING
To avoid negative overvoltage conditions and
subsequent distortion of ac analog signals, dc
biasing Is necessary. Biasing is not required,
+ (
100 }JoFI16 V
TANTALUM
OG536
GND
Figure 14.
0
_
\C2"
ANALOG
SIGNAL
OUT
100 }JoF/16 V
TANTALUM
Simple Bias Circuit
R1 and R2 are chosen to suit the appropriate
biasing requirements. For video applications,
approximately 3 V of bias is required for optimal
differential gain and phase performance. Capacitor
C1 blocks the DC bias voltage from being coupled
back to the analog signal source and C2 blocks the
DC bias from the output signal. Both C1 and C2
should be tantalum or ceramic disc type capacitors
in order to operate efficiently at high frequencies.
Active bias circuits are recommended if rapid
switching time between channels is required.
An alternative method would be to offset the supply
voltages (see Figure 15).
Decoupling would have to be applied to the
negative supply to ensure that the substrate is well
referenced to signal ground. Again the capacitors
should be of a type offering good high frequency
characteristics.
Level shifting of the logic signals may be necessary
using this offset supply arrangement.
7-45
DG536
...... Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
TTL to CMOS level shifting is easily obtained by
using a MC14504B.
+12 V
ANALOG
SIGNAL
IN
S
v+
DG536 D
GND
DECOUPLING
CAPACITORS
~v
Figure 15.
7-46
DG536 With Offset Supply
ANALOG
SIGNAL
OUT
CIRCUIT LAYOUT
Good circuit board layout and extensive shielding is
essential for optimizing the high frequency
performance of the DG536. Stray capacitances on
the PC board and/or connecting leads will
considerably degrade the ac performance. Hence,
signal paths must be kept as short as practically
possible, with extensive ground planes separating
signal tracks.
DG538
8-Channel/Dual 4-Channel
WidebandNideo Multiplexer
tI"F Siliconix
~
incorporated
BENEFITS
FEATURES
APPLICATIONS
•
Wide Bandwidth (500 MHz)
•
Improved System Bandwidth
•
Very Low Crosstalk
(-97 dB @ 5 MHz)
•
Improved Channel Off-isolation
•
Simplified Logic
Interfacing
o High-end Video Systems
•
Allows Bipolar
Signal Swings
•
Direct Coupled Systems
•
ATE Systems
•
On-Board TTL-compatible
Latches with Readback
•
•
•
Optional Negative
Supply Input
•
Reduced Insertion Loss
•
Low rDS(ON) (90.n max)
•
•
Single-ended 8-channel or
Dual 4-channel operation
Allows Differential
Signal Switching
•
ESDS Protection> ±4000 V
Wideband Signal Routing
and Multiplexing
Jl.P-controlied Systems
DESCRIPTION
The DG538 is an electrically-selectable 8-channel or
dual 4-channel analog multiplexer clesigned for
wide band operation.
On-chip TTL-compatible
address decoding logic and latches with data
read back are included to simplify the interface to a
microprocessor data bus. The low ON resistance
and low capacitance of the DG538 makes it ideal for
wideband data multiplexing and video and audio
Signal routing in channel selectors and crosspoint
arrays. An optional negative supply pin allows the
handling of bipolar signals without DC biasing.
The DG538 is built on a D/CMOS process that
combines n-channel DMOS switching FETs with
low-power CMOS control logic, drivers and latches.
The low-capacitance DMOS FETs are in a "T"
configuration to achieve extremely high levels of
OFF isolation. Crosstalk is reduced to -97 dB at
5 MHz on the DG538 by including a ground line
between each adjacent signal path.
The DG538 is available In 28-pin plastic DIP and
PLCC packages for operation over the industrial, D
suffix (-40 to 85°C) temperature range. The
28-lead side braze DIP is available for military, A
suffix (-55 to 125°C)
temperature range
operation.
PIN CONFIGURATION
v+
DA
v-
v+
SBI
DA GND DB
v-
SBI
GND
GND
Dual-in-line Package GND
Order Numbers:
Side Braze: DG538AP
Plasllc: DG538DJ
SA2
GND
SB2
SB2
GND
GND
Order Number:
SB3
DG538DN
Quad J Lead
Plastic Chip Carrier
SB3
GND
SB4
VL
iNA
A2
AI
AO
EN
iio
7-47
..
DG538
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
1/0 A2 A1 Ao EN WR
X
X
X X
X S
All eight Input switches are "T" switches.
V+
V-
GND
SA1
SA2
--:----t_..-a..L DA
_-!---!--+--ll ~
SA3
SA4 o-+---<>-"""! ....
SB1
SB2
0-11----+_--1>...,
SB4
...l...r::::?==it:::?==it:::?==it::?=~:::::J
8/4
1
1
Maintains previous state
ON SWITCH
X
X
X
X
X
0
X
None (latches cleared)
X
X
X
X
0
0
None
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
SA1
SA2
SA3
SM
SB1
SB2
SB3
SB4
SA1
SA2
SA3
SA4
0
0
0
0
0
0
1
1
1
1
0
DB
Rs
X
0
a.-r----ir-+_~
S~ o-II----~~,~_+-~+-~~
8/4
Siliconix
incorporated
H
1
0
0
0
1
1
1
0
1
0
X
0
0
0
X
0
1
1
1
0
0
X
0
X
1
NOTE 2,3
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
~:c~n~~crac:r
externally
Latches
Transparent
SB1
SB2
& SB3
& SB4
&
&
'NOte
1
r--
EN
I---+ORS
WR
Logic" 1 " : VAH
1/0
~
2.0 V
Logic" 0 " : VAL ::; O.B V
1. 8/4 can be either H or L but should not change
during these operations.
Ao
2. In this condition the pins A o, A 1 and A2 become
outputs and reflect the contents of the latches.
Please see timing waveforms for more detail.
3. EN must be latched HIGH to allow proper address
data readback operation.
ABSOLUTE MAXIMUM RATINGS
V+ to GND
........................... -0.3 V to +22 V
Power Dissipation (Package)·
V+ to VV- to GND
•.......................... -0.3 V to +22 V
........................... -10 V to +0.3 V
2B-pln Plastic DIp··
Digital Inputs ...... (V- minus 0.3 V) to (V+ plus 0.3 V)
or 20 mA, whichever occurs first
Vs , Vo
2B-pln Side Braze DIP"·
625 mW
.................. 1200 mW
2B-pln Quad J Lead Plastic····
CURRENT (any terminal) Continuous........... 20 mA
CURRENT (S or D) Pulsed 1 ms 10% duty ..... 40 mA
• All leads welded or soldered to PC board.
Derate B.3 mW/oC above 75°C
Storage Temperature
(A Suffix) ..... -65 to 150°C
Derate 16 mW/oC above 750C
(D Suffix) ..... -65 to 125°C
Derate 6 mW/oC above 750C
Operating Temperature (A Suffix) ..... -55 to 1250C
(D Suffix) ..... -40 to B50C
7-48
...........
........... (V- minus 0.3 V) to (V- plus 14 V)
or 20 mA, whichever occurs first
450 mW
H
DG538
~i1iconix
Incorporated
CONTROL
CIRCU~IT~R~Y~=----------
r--
I
I
I
I
I
I
I
I
L
Ao
Note', V REF Is Internali y generated fr omVl
7-49
DG538
fI"'lI" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 1S V, V- = -3 V
V L= +S V, GND = 0 V
WR = 0.8 V
RS, EN = 2 V
LIMITS
1=2S·C
2=125,8S·C
DGS38AP
3=-SS,-40·C -S5 to 125°C
TEMP TYpd
MIN b MAXb MIN b MAXb UNIT
SWITCH
Analog Signal Range e
Drain - Source
ON Resistance
DG538DN
DGS38DJ
-40 to 85°C
:
VANALOG
V- = -5 V
1
rOS(ON)
I s =-10mA, Vs=OV
1,3
2
-5
45
8
-5
8
90
120
90
120
9
9
Resistance Match
Between Channels
t:.
rOS(ON)
VAIL = 0.8 V, V AIH = 2 V
Sequence each switch ON
1
Source OFF
Leakage Current
IS(OFF)
V s =8V, Vo=OV
EN = O.B V
1,3
2
-5
-50
5
50
-5
-50
5
50
Drain OFF
Leakage Current
I o (OFF)
Vs = 0 V, Vo = 8 V
EN = 0.8 V
1,3
2
-20
-500
20
500
-20
-500
20
500
Total Switch ON
Leakage Current
IO(ON)+
Is(oN)
Vs = Vo = 8 V
1,3
2
-10
-1000
10
1000
-10
-100
10
100
1,2,3
-400
V
.n.
nA
INPUT
VAO = 2.7 V
Address Output Current
IlA
VAO = 0.4 V
Input Voltage High
-400
lAO
1,2,3
VAIH
400
1,2,3
2
400
2
See Figure 13
Note 1
Input Voltage Low
Address Input Current
IAI
V
1,2,3
VAIL
VAl = 0 V or 2 V or 15 V
0.8
1,3
2
0.1
-1
-10
1
10
0.8
-1
-10
1
10
IlA
DYNAMIC
ON State Input Cap~
cS(ON)
See Figure 11
PLCC
DIP
1
1
23
27
35
30
35
OFF State Input Cap.o
CS(OFF)
See Figure 12
PLCC
DIP
1
1
2
3
5
4
5
OFF State Output Cap.o
Co (OFF)
See Figure 12
PLCC
DIP
1
1
4
10
8
10
Multiplexer Switching Time
tTRANS
See Figure 4
1,3
2
300
500
300
SOD
tOPEN
See Figure 4
1,2,3
EN, WR Turn on Time
tON
See Figures 2 & 3
1,3
2
300
SOO
300
500
EN, Turn OFF Time
tOFF
See Figure 2
1,3
2
lS0
300
1S0
300
Break-Before-Make
Interval
6
SO
pF
SO
ns
7-50
H
DG538
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
SYMBOL
V+ = 15 V, V- = -3 V
VL=+5V, GND=OV
WR = 0.8 V
RS, EN = 2 V
Q
See Figure 5
LIMITS
1=25°C
2=125,85°C
DG538AP
3=-55, -40 ° C -55 to 125°C
DG538DN
DG538DJ
-40 to 85°C
MIN b MAXb MIN b MAXb UNIT
TEMP TYpd
DYNAMIC (Cont'd)
Charge Injection
Chip Disabled Crosstalk
(See Figure 8)
Adjacent Input Crosstalk
(See Figure 9)
All Hostile Crosstalk
(See Figure 7)
Differential Crosstalk
(See Figure 10)
Bandwidth
XTALK(co)
XTALK (AI)
XTALK(AH)
XTALK
(OIFF)
BW
RL = 75.0.
f = 5 MHz
EN = 0.6 V
RIN = 10.0.
RL = 10 k.o.
f = 5 MHz
RIN = 75.0.
RL = 75.0.
f - 5 MHz
RIN = 10.0.
RL = 10 k.o.
f = 5 MHz
RIN =75.0.
RL = 75.0.
f = 5 MHz
RIN -10.0.
RL = 10 k.o.
f = 5 MHz
RIN = 75.0.
RL = 75.0.
f = 5 MHz
1
-70
PLCC
DIP
1
1
-75
-65
PLCC
DIP
1
1
-97
-67
PLCC
DIP
1
1
-60
-70
PLCC
DIP
1
1
-77
PLCC
DIP
1
1
-77
PLCC
DIP
1
1
-84
-64
PLCC
DIP
1
1
-84
-64
1
500
1,2
3
0.6
1,2
3
0.6
RL = 50.0., See Figure 6
pC
dB
-72
-72
MHz
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
Any One Channel Selected
With Address Inputs at GND
or V+
V+ to VOperating Supply
Voltage Range
V- to GND
See Figure 13
Functional Test Only
V+ to GND
Logic Supply Current
mA
-1.6
-2.0
-1.6
-2.0
1,2,3
10
21
10
21
1,2,3
-5.5
0
-5.5
0
1,2,3
10
21
10
21
1,2,3
IL
2
5
2
5
150
500
500
V
IlA
,
TIMING
Reset to Write
WR, RS Minimum pulse
Width
tRW
See Figure 1
1,2,3
50
50
t MPW
See Figure 1
1,2,3
200
200
tow
See Figure 1
1,2,3
100
100
ns
Ao, Al, A2, EN
Data Valid To Strobe
7-51
DG538
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
V+ = 15 V. V- = -3 V
VL = +5 V. GND = 0 V
WR = 0.8 V
RS. EN = 2 V
SYMBOL
PARAMETER
LIMITS
1=25°C
DG538DN
2=125.85°C
DG538DJ
DG538AP
3=-55.-40 0 C -55 to 125°C -40 to 85°C
TEMP TYpd MIN b MAXb MIN b MAXt UNIT
TIMING (Coot'd)
Ao. Al. A2. EN
Data Valid After Strobe
two
See Figure 1
1.2.3
Address Bus Tristate
tAZ
See Figure 1
1
tAO
See Figure 1
tAl
See Figure 1
50
50
1
200
200
1
200
200
50
ns
Address Bus Output
Address Bus Input
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum ant! the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY at 25"C. not guaranteed nor subject to production testing.
e. Analog signal range Is measured from the GND pin to the designated Source (Input) pin. and Indicates the limits of
functionality. Performance limits are only guaranteed for stated test conditions.
DIE TOPOGRAPHY
13
14
1 89 mils
15
16
17
20 21 22 23 24 25 26
20X
LNDPA
222 PMOS Transistors
243 NMOS Transistors
1 NPN Transistor
7-52
3 P+ Resistors
18 Diodes
Pad
no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
GND
DA
V+
SAl
GND
SA2
GND
SA3
eND
SA4
3.L4
RS
WR
A2
Al
AO
EN
I/O
VL
SB4
GND
SB3
GND
SB2
GND
SBl
VDB
DG538
..... Siliconix
incorporated
~
INPUT TIMING REQUIRMENTS
~tMPW~
3V
WR
OV
ttow =+twoj
--D-O-N-'T-C-A-R-E---"X
WRITE DATA
X"--D-O-N-'-T-C-A-R-E-
Writing Data to Device
_ 3 V - - - - - - - - - - - - - - -.......
WR OV
Ao, Al, A 23 V - - - - - - - - - - - - - - - - - / - "
OV
DON'T CARE
---------------+--/
- 3 V -------.
RS 0 V
Delay Time Required after Reset before Write
_3V
WR OV
A o , Al' A 2 3 V
DRIVEN BUS
HIZ
DEVICE DATA" OUT
OV
_
HIZ
DRIVEN BUS
3V
1/0 0 V - - - - - - - - - - - : - - - - /
!.-tAZ
• Enable must be latched" High" to read back data, otherwise BUS Is high Z.
Reading Data From Device
..
Figure 1
EN TURN ON/OFF TIME TEST CIRCUIT
+15 V
LOGIC INPUT
t, < 20 ns
3V
tj < 20 ns
50%
+5 V
EN
OV
SB4
SAl - SB3
8/41--+-0--,
TIO
WR
0.9 VOUT
RS
....----c>-l EN
SWITCH
OUTPUT
-3 V
Figure 2
7-53
DG538
..... Siliconix
incorporated
~
WR TURN ON TIME TEST CIRCUIT
+15 V
+
10J,lF
l
WR -+3-V---""
OV
~ENN~.V~L~.lRR:SS-~V~+~SS~A7t~----o+lV
At' A2
SA2I---o-,
8/4
thru
i/o
SB4
Ao +3 V
OV
(WR)
14-
-'f
_vO;:,.u:..;T'--_ _ _ _ _ _ _ _ _ _
0.9 VOUT
LOGIC INPUT
tr < 20 ns
tf
< 20 ns
ADDRESS INPUT
tr < 20 ns
< 20 ns
t,
-3 V
Figure 3
TRANSITION TIME and BREAK-BE FORE-MAKE INTERVAL TEST CIRCUIT
ADDRESS INPUT
LOGIC INPUT
tr < 20 ns
+15 V
+
+5 V
10J,lF
V+
l
+1 V
tf
< 20 ns
V
50% ~ ; - - - - - - - - -
OV
SAt
SB4 1---<)----'
SA2
thru 1----<:>----,
SB3
Figure 4
7-54
+3
Ao. At. A2
~
~
DG538
Siliconix
incorporated
-3 dB BANDWIDTH TEST CIRCUIT
CHARGE INJECTION TEST CIRCUIT
iSV
+15 V
iSV
iSV
+
OV
10JJ.FJ
SWITCH
OUTPUT
EN~
to;~
I!.v 0 Is the measured voltage
error due to charge InJection.
The charge Injection In Coulombs Is
Q=CLx I!.vo
V~O
o
-,-
J
100 nF
Jl00nF
-3V
Figure 5
Figure 6
ALL HOSTILE CROSSTALK - X TALK (AH)
(C~)
CHIP DISABLED CROSSTALK - X TALK
SAl
8/4 = LOGIC' O·
~
SB2
SB3
SB4
V
"
T
SAl
SA2
1
RIN
x
V OUT
TALK (AH) = 20 LOG 10--V-
Note: SA1 on or any other one channel on.
Figure 7
~h~
SA3
V OUT
RL
SA4
SBl
SB2
DB
DAAND DB
CONNECTED EXTERNALLY
SIGNAL
GENERATOR
§-(M
ALL CHANNELS OFF
DA
SB3
SB4
DB
...
V
DAAND DB
CONNECTED EXTERNALLY
SIGNAL
GENERATOR
V OUT
X TALK(CD)= 20 LOG 10 - V ~=
75.n.
Figure 8
7-55
..
DG538
W1P'" Siliconix
~
ADJACENT INPUT CROSSTALK - X TALK (AI)
incorporated
DIFFERENTIAL CROSSTALK - XTALK(DIFF)
CHANNELS SA1 AND SB10N
8/4
RIN
I
-=-
I
I
I
=LOGIC "1"
..r:..AA~
v v- .
! - Sn-1
SB1 r-----~-..,
SB2+-_ _
Sn
~
SB3+---~
SB4+---~
SIGNAL-=GENERATOR
v
=20 LOG 10 V SnVSn
-1
X TALK (AI)
or 20 LOG 10
VSn+1
VSn
SIGNAL
GENERATOR
Figure 10
Figure 9
ON STATE INPUT CAPACITANCE
OFF STATE INPUT/OUTPUT CAPACITANCE
+15V
+15 V
OUTPUT
+5V
+5V
SA1
OV,
2.0 V
VL
As
As
EN
8/4
/
SAa
SA4
I
I
\
AO
\
A1
SB3
A2
,
SB4
-3V
Figure 11
-3V
METER
HP4192A
IMPEDANCE
ANALYZER OR
EQUIVALENT
':'
7-56
SA1
SA2
V+
VL
METER
HP4192A
IMPEDANCE
ANALYZER OR
EQUIVALENT
Figure 12
DG538
...... Siliconix
incorporated
~
OPERATING VOLTAGE RANGE
22
21
20
19
18
17
16
15
14
OPERATING
VOLTAGE
AREA
(NOTE 2)
POSITIVE SUPPLY VOLTAGE
v+ (VOLTS)
13
12
11
10
7
6
5
4
3
2
-5.5
-2
-4
NEGATIVE SUPPLY VOLTAGE
(VOLTS)
-1
v-
Note:
1. Both V+ and V- must have decoupllng capacitors mounted as close as possible to the device pins.
Typical decoupllng capacitors would be 10j1F tantalum bead In parallel with 100 nF ceramic disc.
2. Production tested with V+ 15 V and V- -3.0 V
3. At VL= 5 V ± 10%,0.8/2.0 V TTL compatibility is maintained over the entire operating voltage range.
=
=
Figure 13
-
BURN-IN CIRCUIT - 2S-LEAD DUAL-IN-LiNE
10 k,o,
-5 V
+15 V
+15 V
+5 V
7-57
W'1P" Siliconix
CG53S
~
incorporated
BURN-IN CIRCUIT - 28-LEAD PLCC
-5 V
+15 V
10 k.O.
9
+5 V
PIN DESCRIPTION
PIN NUMBER
SYMBOL
2
3
11
12
13
DA
8/4
RS
WR
Analog output
Positive supply voltage (must be decoupled)
8 by 1 or 4 by 2 select
Reset
Write command that latches Ao, Al, A2, EN
14
15
16
A2
Al
Ao
Binary address inputs that determine
which input channel(s) is connected to the
output(s)
17
EN
18
19
27
28
i/o
DB
Input to activate multiplexer
Pin to read from or write to the address latches
Logic supply voltage
Negative supply voltage (must be decoupled)
Analog output
4
6
SAl
SA2
SA3
SA4
SB4
SB3
SB2
SBl
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
GND
Analog and digital ground.
All GND pins should be connected externally to
optimize dynamic performance.
8
10
20
22
24
26
1,5,7,9
21, 23, 25
7-58
v+
DESCRIPTION
VL
V-
input
input
Input
input
input
input
input
input
DG538
..... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
Address Output Current vs. Temperature
2
lAO
(rnA)
o
-1
- -
....
SI~k
r- r-
I
100
1-
VIN= 4V
10
V+ = 15 V
V- = -3 V
-f- V L = 5 V
IAI
(rnA)
III
-
Logic/Address Input Current vs. Temperature
Source
VIN = 2.7 V
.1
"i
-2
.01
-40 -20
0 20 40 60 80100120
Temperature (·C)
-40 -20
Supply Currents vs. Temperature
1.0
,
~+!
151V
V-=-3V_
~
.8
"-
.6
I
(rnA)
.4
"
Leakage vs. Temperature
l~A
-
10
~II+I=II-I
I
(nA)
...... ......
.2
r-~~~~--~~~~--"
100
VLrl
I'
1 nA
100
IL
1 pA
-40 -20
0 20 40 60 80100120
Temperature (·C)
-40 -20
rOS(ON) vs. Drain Voltage
200
160
-
140
rOS(ON)
(.0. )
rOS(ON)
VS.
-5
-4
V-; V+ Constant
.7J r--I
60
rOS(ON)
(.0.)
50
- 55 ° C
80
-- --
/. ./ V
60
20
I
flJ
25°C .---iWI
125°C:----o
100
0 20 40 60 80100120
Tempsrature (·C)
70
J
V+! 15
V- = -3 V
VL = 5 V
Is = -10 rnA
120
40
..
10
0
180
0 20 40 60 80100120
Temperature (·C)
-r-2
--:... ...- . /
0
2
4
Vo (V)
40
30
6
8
10
-6
-3
V- (V)
-2
-1
0
7-59
DG538
.... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
Adjacent Input Crosstalk
See Figure 9
Adjacent Input Crosstalk
See Figure 9
120
120
'"
100
XTAl.KCAI)
(dB)
80
~"
""
100
r--.~
~G538DN
V+ = 15 V
V- = -3 V
VL= 5 V
RIN = 10 .0.
60
RLr 1r
40
~
"
"
100 MHz
IDGI5dalN
~
111?iG53a
20
1 MHz
pJ~i'
10 MHz
Frequency
100 MHz
Frequency
All Hostile Crosstalk
See Figure 7
Differential Crosstalk
See Figure 10
100
120
100
80
r-...
r'--",
DG538DN
XTAl.KCAH)
(-dB)
IV~I~ 15
I I I
V- = -3 V
VL= 5 V
RIN = RL= 75.0.
40
IIIDG5~8Dt
10 MHz
~ r"-"
80
60
~ r'\r--.
III
1 MHz
XTALKCAI)
(dB)
V
"-
XTALKCOIFFI
(-dB)
60
ao
All Package
60
r"-~
40
40
t- V+ = 15 V
20
20
Vl=~Y'
1 MHz
10 MHz
V- = -5 V
1 MHz
100 MHz
10 MHz
Frequency
100 MHz
Frequency
Insertion Loss
See Figure 6
ON State Capacitance
See Figure 11
o
40
35
-4
r-
(-dB)
CS(ON)
(pF)
30
-a
V+ = 15 V
V- = -3 V
~LI=I~I~II
-12
1 MHz
10 MHz
1111111
I
100 MHz
Frequency
7-60
25
1.1
-3 dB pt.
20
1 GHz
0
2
4
6
Vo - VCVI
a
10
DG538
...... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
Switching Times vs. Temperature
Chip Disabled Crosstalk
See Figure 8
100
80
XTALK(CO)
350
,
"'.........
60
OG538AP
OG5380J
40
\ \\\\\
1 MHz
"'"'
DG53BON
'I"-
(-dB)
250
V+ = 15 V
V- =-~V
VL= 5
Rl = 1 k
Cl =45rF
200
Ion
300
I
(ns)
....
150
'I'
100
./
.,~ "'""" ~~
i--""
50
-
toll
~
.....
IBBM
-40 -20 0 20 40 60 80 100120
Temperature (·C)
100 MHz
10 MHz
Frequency
.".
~i"'"
rOS(ON) vs. V+i V- Constant
70
60 ~+---+-t-+--
rOS(ON)
50
(.0. )
40
30
..
20
10
11
12 13
14 15 16
V+ (V)
17 18
APPLICATIONS
Device Description
The DG538 D/CMOS wideband multiplexer offers
8-channel single-ended or dual 4-channel functions.
An 8/4 logic input pin selects the single-ended or
dual mode.
To meet the high dynamic performance demands of
video, high definition TV, digital data routing (in excess of 100 Mb/s) , etc., the DG538 is ~abricated with
DMOS transistors configured in 'r arrangements
with second level 'L' configurations (see Functional
Block Diagram).
Use of DMOS technology yields devices with very low
capacitance and low rOSION)' This directly relates to
improved high frequency signal handling, higher
switching speeds, while maintaining low insertion loss
figures. 'T' and 'L' switch configurations further improve dynamic performance by greatly reducing hostile crosstalk and output node capacitance.
Frequency Response
A single multiplexer on-channel exhibits both resistance (rOSION) and capacitance (CSION). This RC
combination causes a frequency dependent attenuation of the analog signal. The -3 dB bandwidth of
7-61
DG538
fI"Y' Siliconix
~
incorporated
APPLICATIONS (Cont'd)
the DGS38 is typically SOO MHz (into SO .0). This figure of SOO MHz illustrates that the switch-channel
cannot be represented by a simple RC combination.
The ON capacitance of the channel Is distributed
along the ON resistance, and hence becomes a
more complex multi-stage network of R's and C's
making up the total rOS(ON) and CS(ON).
b.
They should be mounted as close as possible
to the device pins.
c.
Capacitors should have good frequency characteristics - tantalum bead and/or ceramic
disc types are suitable.
Recommended decoupling capacitors are 1 to
10 fJ.F tantalum bead, plus 10 to 100 nF ceramic or polyester ..
Power Supplies and Decoupllng
A useful feature of the DGS38 is its power supply
flexibility. It can be operated from dual supply, or a
single positive supply (V- connected to 0 V) if required. Recommended operating voltage range is
shown in Figure 13.
d.
Additional high frequency protection may be
provided by S1 .0 carbon film resistors connected in series with the power supply pins
(see Figure 14).
Note that the analog signal must not exceed V- by
more than -0.3 V (see absolute maximum ratings).
However, the addition of a V- pin has a number of
advantages:
1.
2.
+5 V +15 V
It allows flexibility in analog signal handling, i.e.
with V- = -S V and V+ = 15 V, up to ±S V ac
signals can be accepted.
51.0.
+
The value of ON capacitance (CS(ON) may be
reduced by increasing the reverse bias across
the internal FET body to source junction. For
more information see curve of C S(ON) versus
t-'o minus V-) voltage in typical characteristic
data section. V+ has no effect on CS(ON).
C:!..I.
OA
It is useful to note that tests indicate that optimum video differential phase and gain occur
when V- is -3 V.
3.
V- eliminates the need to bias the analog signal using potential dividers and large coupling
capacitors.
It is established rf design practice to incorporate
sufficient bypass capacitors in the circuit to
decouple the power supplies to all active devices in
the circuit.
The dynamic performance of the
DGS38 is adversely affected by poor decoupling of
power supply pins. Also, since the substrate of the
device is connected to the negative supply, proper
decoupling of this pin is essential.
Rules:
a.
7-62
Decoupling capacitors should be incorporated
on all power supply pins (V+, V-, Vd.
,TI:l
DG538
DB
SB4
V-
-3 V
Cl = 10 fJ.F Tantalum
C:! = 100 nF Polyester
Figure 14. OG538 Power Supply Oecoupllng
DG538
trY' Siliconix
",1;11 incorporated
APPLICATIONS (Cont'd)
Board Layout
PCB layout rules for good high frequency performance must also be observed to achieve the performance boasted by the DG538. Some tips for minimizing stray effects are:
i.
Use extensive ground planes on double sided
pcb separating adjacent signal paths. Multilayer
pcb is even better.
ii.
Keep signal paths as short as practically possible
with all-channel paths of near equal length.
Slight improvements in performance can be obtained
by using DG538DN parts in preference to DG538DJ.
The stray effects of the quad PLCC package are better than those of the 28-pin dual-in-line package.
Interfacing
Logic interfacing is easily accomplished with the
DG538.
Comprehensive addressing and control
functions are incorporated in the design.
The addition of a VL pin permits interface to various
logic types. The device is primarily designed to be
TTL logic compatible with +5 V applied to VL. The
DG538 actual switching threshold can be raised simply be increasing VL.
A typical DG538 switching threshold versus VL is
shown in Figure 15.
8
7
6
5
./
Vth 4
(V)
3
/"
V
/""
2
/"
o //
o 2 4
V
6
8
10
12
14
16
18
VL (V)
Figure 15.
DG538 Switching Threshold Voltage vs. VL
The device features an address read back (Tally) facility, whereby the last address written to the device
may be output to the system. This allows improved
status monitoring and handshaking without additional
external components.
This function is controlled by the 1/0 pin, which directly addresses the tri-state buffers applied to the
address inputs (Ao-A2). Address inputs can be assigned to accept data (when 1/0 = 0; WR = 0;
RS = 1) or output data (when 1/0 = 1; WR = 1;
RS = 1) or reflect a high impedance and latched
1; RS
1).
state (when 1/0 0; WR
=
=
=
NOTE: (EN) must have been latched HIGH to allow
proper readback,' otherwise readback is supressed.
When the 1/0 assigns the address output condition,
the address output can sink or source current for
logic low and high respectively. Note that VL is the
logic high output condition. This point must be respected if VL is varied for input logic threshold shifting.
Note: VL must not exceed V+ by more than +0.3 V.
This must also apply when the power supply is turned
on, i.e. V+ must rise ahead of VL.
Further control pins facilitate easy microprocessor interface. On chip address, data latches are activated
by WR, which serves as a strobe type function eliminating the need for peripheral latch or memory 1/0
port devices. Also, for ease of interface, a direct
reset function (RS) allows all latches to be cleared
and switches opened. Reset should be used during
power up, etc., to avoid spurious switch action. See
Figure 16.
Channel address data can only be entered during WR
low, when the address latches are transparent and
1/0 is low. Similarly data read back is only operational
when WR and 1/0 are high.
Multiplexer output buffers are recommended to reduce insertion loss and transmission errors caused
by ON resistance modulation effects. For low power
power routing applications, a Siliconix 2N59111
2N5912 JFET may be employed in a source-follower
circuit as shown below.
Note: For additional information please refer to
AN88-2.
7-63
..
DG538
H
APPLICATIONS (Cont'd)
DATA BUS
,::':::
RS
,',
WR
t----------j'::~,
110
t ___________-;',,'"
:"",,'
R E S E l } - - - - - - - - - - - - - t ",
WR
,':'
ADDRESS BUS
ADDRESS
DECODER
7sJl
1/0
VIDEO DATA
BUS
BUS
Figure 16. DGS38 In a Video Matrix
V+
2NS911/12
VFigure 17. Discrete Video Buffer
7-64
Siliconix
incorporated
DG540
Quad SPST Wideband/
Video "T" Switch
..... Siliconix
.,1;11 incorporated
FEATURES
BENEFITS
o Wide Bandwidth
(500 MHz)
GLow Insertion Loss
C)
o Very Low Crosstalk ( -85 dB)
and High OFF Isolation
(-75 dB) at 5 MHz
Q
o"T" Switch
Configuration
APPLICATIONS
Improved Data Throughput
"Video Switching
o High Frequency
Crosspoints
Improved System
Performance
• Reduced Board Space
o Local and Wide
Area Networks
o Reduced Power Consumption
o Video Routing
o Fast Data Acquisition
• TTL Compatible
o ATE
o Fast Switching (t ON < 70 ns)
±4000
o ESDS Protection >
GLow rDS(ON) < 75
Q
Radar/FUR Systems
V
n
DESCRIPTION
The DG540 is a very high performance monolithic
quad SPST wide band/video switch designed for
switching wide bandwidth analog and digital signals.
By utilizing "T" switching techniques on each
channel this device gives exceptionally low
crosstalk and high OFF isolation. The crosstalk and
OFF isolation are further improved by the
introduction of GND pins between signal pins.
To achieve TTL compatibility with superior switching
performance, the DG540 was built on the Siliconix
proprietary D/CMOS process. Each switch conducts
equally well in both directions when ON.
Capacitance has been minimized to ensure fast
switching.
Packaging
and PLCC
military, A
suffix (-40
includes the 20-pin side braze, plastic,
options. Performance grades include
suffix (-55 to 125°C) and industrial, D
to 85°C) temperature ranges.
PIN CONFIGURATION
PLCC Package
Dual-In-Llne Package
Top View
IN2
31121111120111!li
/
0
GNO
GNO
52
~ v+
~ GND
~4 53
~
D:!
GNO
~
~
~
~B
52
v+
GNO
53
GNO
54
GNO
911101111111211131
0 4 IN41N303 GNO
-...
__....
03
IN3
Top View
Order Number:
DG540DN
Order Numbers:
Side Braze: DG540AP
Plastic: DG540DJ
Preliminary
7-65
W'F' Siliconix
DG540
~
incorporated
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SWITCH
0
OFF
1
ON
Logic "0" ~ 0.8 V
Logic "1" ~ 2.0 V
ABSOLUTE MAXIMUM RATINGS
V+ to V- ............................. -0.3 V to 19 V
V+ to GND ........................... -0.3 V to +19 V
V- to GND ........................... -19 V to +0.3 V
Digital Inputs .............. (V-) -0.3 V to (V+) +0.3 V
or 20 mA, whichever occurs first
V S, VD' .................... (V-) -0.3 V to (V-) +19 V
or 20 mA, whichever occurs first
Continuous Current (Any Terminal) .............. 20 mA
Current, S or 0 (Pulsed 1 ms, 10% duty
cycle max) .........•......................... 40 mA
Storage Temperature (A Suffix) ........... -65 to 150°C
(0 Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(0 Suffix) .......... -40 to 85°C
Power
20-Pin
20-Pin
16-Pln
Dissipation (Package)·
Size Braze DIp·· ....................... 900 mW
Plastic DIp··· ........................ 800 mW
PLCC···· ........................... 800 mW
All leads welded or soldered to PC board.
Derate 12 mW/oC above 75°C.
Derate 7 mW/oC above 25°C.
•••• Derate 10 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
V+ = 15 V, V- = -3 V
SUFFIX
SUFFIX
3=-55,-40°C
-55
to
125°C
-40
to
85°C
GND = 0 V
V 1NH = 2 V, VINL = 0.8 V e
b
b
TYpd
TEMP
MIN MAX' MIN MAXt UNIT
SWITCH
Analog Signal Range
Drain - Source
ON Resistance
C
VANALOG
V- = -5 V
rDS(ON)
I s =-10mA, VD=OV
1,2,3
-5
8
-5
8
1,3
2
40
60
100
60
75
1
2
6
6
Resistance Match
Between Channels
rDS(ON)
Source OFF
Leakage Current
IS(OFF)
Vs = 0 V, VD = 10 V
1
2
-0.05
-10
-500
10
500
-10
-100
10
100
Drain OFF
Leakage Current
Vs =10V, VD=OV
1
2
-0.05
ID(OFF)
-10
-500
10
500
-10
-100
10
100
Total Switch ON
Leakage Current
ID(ON)+
IS(ON)
VS=VD=OV
1
2
-0.07
-10
-1000
10
1000
-10
-100
10
100
7-66
A.
V
.n
nA
Preliminary
DG540
..... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25·C
A
0
2=125,B5·C
SUFFIX
SUFFIX
V+ = 15 V, V- = -3 V
3=-55,-40·C
-55 to 125°C -40 to B5°C
GND = 0 V
VINH = 2 V, VINL= 0.8 VB
TEMP TYpd MINb MA>f MINb MAXt UNIT
INPUT
Input Voltage High
\fNH
1
2,3
\fNL
1
2,3
2
2
2
2
V
Input Voltage Low
O.B
O.B
-1
-20
O.B
O.B
-1
-20
liN
VIN = GND or V+
1
2,3
0.05
OFF State Input Cap.o
CS(OFF)
Vs= 0 V
1
2
4
4
OFF State Output Cap.o
Co (OFF)
Vo= 0 V
1
2
4
4
ON State Input Cap~
CS(ON)
Vs=Vo=OV
1
14
20
20
Bandwidth
BW
RL = 50.0.
See Bandwidth Test Circuit
1
500
Turn ON Time
tON
1
2,3
45
70
110
70
110
1
2,3
20
50
85
50
85
1
25
-75
Input Current
1
20
1
20
J1A
DYNAMIC
Turn OFF Time
tOFF
Charge Injection
Q
RL= 1 k.o.
CL = 35 pF, 50% to 90%
See Switching Time
Test Circuit
C L =1000pF. Vo=OV
See Test Circuit
MHz
ns
OFF Isolation
RIN = 75.0., RL = 75.0.
f = 5 MHz, See Test Circuit
1
All Hostile CrosstalkC
RIN = 10.0., RL= 75.0.
f = 5 MHz, See Test Circuit
1
-85
1
2,3
2.7
1
2,3
2.3
XTALK(AH)
pF
pC
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
5
7
5
7
mA
All Channels ON or OFF
-5
-7
-5
-7
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
Preliminary
7-67
•
W7' Siliconix
DG540
~
incorporated
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform .
• LOGIC "1" = SW ON
LOGIC'
INPUT
3V
SWITCH
INPUT S1
t r < 20 ns
V S =..:!
tf< 20 ns
v o-!l----a1 &...lro-......- .....--o
LOGIC
INPUT
-15 V
(REPEAT TEST FOR IN2 .INa ANO IN 4 )
CHARGE INJECTION TEST CIRCUIT
t:. Vo
Vo
IN X
~
/
Vo
ON
t
\
F
OFF
t:. Vo =MEASURED VOLTAGE ERROR DUE TO CHARGE INJECTION
THE CHARGE INJECTION IN COULOMBS IS Q = C L" t:. Vo
OFF ISOLATION TEST CIRCUIT
o-__",,::S-I--o' "----4_----<1" '"-+0....._--0
VOUT
R
SIGNAL
GENERATOR
7s.n.
7s.n. OFF ISOLATION = 20 LOG 10
V~UT
ALL HOSTILE CROSSTALK - X TALK (AH)
S1
r--~~----~~~-------~-~
VOUT
S2
1M
Sa
-
S4
R L= 7s.n.
XTALK(AH)= 20 LOG 10
7-68
V~UT
Preliminary
..or Siliconix
DG540
.ell incorporated
BANDWIDTH TEST CIRCUIT
r----i--<~"--t--...,...--o VOUT
OPERATING SUPPLY VOLTAGE RANGE
20
18
16
OPERATING
VOLTAGE
AREA
14
12
POSITIVE SUPPLY VOLTAGE
V+ (VOLTS)
~----------+-10
8
4
2
-5
-4
-3
-2
..
-1
NEGATIVE SUPPLY VOLTAGE
V- (VOLTS)
Note:
1. Both V+ and V- must have decoupllng capacitors mounted as close as possible to the device pins.
Typical decoupllng capacitors would be 10J1F tantalum bead In parallel with 100 nF ceramic disc.
2. Production tested with V+
= 15 V and V- = -3.0 V
PIN DESCRIPTION
SYMBOL
DESCRIPTION
S
An Analog Channel Input or Output
D
An Analog Channel Output or Input
IN
Logic Control Input
V+
Positive Supply voltage
V-
Negative Supply Voltage
GND
Analog and Digital Ground
Preliminary
7-69
DG541
Quad SPST Wideband/
Video "T" Switch
..,.. Siliconix
Incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Wide Bandwidth
(350 MHz)
• Improved Data Throughput
• Video Switching
• Easily Interfaced
.Very Low Crosstalk
(-85 dB at 5 MHz)
• Low Insertion Loss
• High Frequency
Crosspolnts
."T" Switch
Configuration
• TIL Compatible
~ Fast
Switching (t ON < 70 ns)
• ESDS Protection >
• Low rDS(ON) < 75
.Improved System
Performance
• Local and Wide
Area Networks
• Reduced Board Space
• Video Routing
• Reduced Power Consumption
• Fast Data Acquisition
• ATE
±4000 V
.n
• Radar/FLiR Systems
• DG201 A Pinout
DESCRIPTION
The DG541 Is a high performance monolithic quad
SPST wide band/video switch designed for switching
wide bandwidth analog and digital signals. By
utilizing "T" switching techniques on each channel
this device gives exceptionally low crosstalk and
high OFF Isolation. Also, the DG541 is pin
compatible with the industry standard DG201 A
analog switch.
To achieve TIL compatibility with superior switching
performance, the DG541 was built on the Siiiconix
proprietary D/CMOS process. Each switch conducts
equally well in both directions when ON.
Capacitance has been minimized to ensure fast
switching.
Packaging includes 16-pin side braze, plastic, and
small outline options. Performance grades include
military, A suffix (-55 to 125°C) and industrial, D
suffix (-40 to 85°C) temperature ranges.
PIN CONFIGURATION
Dual-In-Llne Package
IN1
D1
81
IN2
D2
82
1
v+
v-
GND
GND
84
(Same pinout as DIP)
1 2 3 4 5 6 7 B
S3
D4
D3
IN3
TopVIBW
Order Numbers:
Side Braze: DG541AP, DG541AP/883
Plastic: DG541DJ
7-70
SO Package
Top View
Order Number:
DG541DY
Preliminary
DG541
4I"JP" Siliconix
~
incorporated
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SWITCH
0
OFF
1
ON
Logic "0"
Logic "1"
~
~
0.8 V
2.0 V
ABSOLUTE MAXIMUM RATINGS
V+ to V- ............................. -0.3 V to 19 V
V+ to GlND ........................... -0.3 V to +19 V
V- to GlND ..•........................ -19 V to +0.3 V
Digital Inputs •..•.......... (V-) -0.3 V to (V+) +0.3 V
or 20 mAo whichever occurs first
VS, Vo.................... (V-) -0.3 V to (V-) + 19 V
or 20 mA, whichever occurs first
Continuous Current (Any Terminal) .............. 20 mA
Current, S or D (Pulsed 1 ms, 10% duty
cycle max) ..•••.•........•.•••••••.••........ 40 mA
Storage Temperature (A Suffix) ........... -65 to 150°C
(D Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ........• -55 to 125°C
(D Suffix) .......•.. -40 to 85°C
Power
16-Pln
16-Pln
16-Pln
Dissipation (Package)"
Side Braze"" ......................... 900 mW
Plastic DIP""" ........................ 450 mW
SO .................................. 600 mW
All leads welded or soldered to PC board.
Derate 12 mW/oC above 75°C.
Derate 6 mW/oC above 75°C.
"""" Derate 7.6 mW/oC above 75°C.
ELECTRICAL CHARACTER!STICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
V+ = 15 V, V- = -3 V
SUFFIX
SUFFIX
3=-55,-40°C
-55
to
125°C
-40
to
85°C
GlND = 0 V
V1NH = 2 V, VINL = 0.8 Va
b
b
TVpd
TEMP
MIN MA>f MIN MAXb UNIT
SWITCH
Analog Signal Range C
Drain - Source
ON Resistance
VANALOG
V- = -5V
rOS(ON)
I s =-10mA, Vo=OV
1,2,3
-5
1,3
2
40
1
2
8
-5
8
60
100
60
75
6
6
Resistance Match
Between Channels
rOS(ON)
Source OFF
Leakage Current
IS(OFF)
Vs =OV,Vo =10V
1
2
-0.05
-10
-500
10
500
-10
-100
10
100
Drain OFF
Leakage Current
I o (OFF)
Vs =10V,Vo =OV
1
2
-0.05
-10
-500
10
500
-10
-100
10
100
Total Switch ON
Leakage Current
IO(ON)+
IS(ON)
Vs = VO= 0 V
1
2
-0.07
-10
-1000
10
1000
-10
-100
10
100
Preliminary
t::..
V
.n
nA
7-71
..
DG541
. . . Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
0
A
2=125,85°C
SUFFIX
SUFFIX
V+ = 15 V, V- = -3 V
o C -55 to 125°C -40 to 85°C
3=-55,-40
GND = 0 V
VINH = 2 V, VINL = 0.8 Va
TEMP TYpd MINb MA>f MINb MAXt UNIT
INPUT
Input Voltage High
\fNH
1
2,3
\fNL
1
2,3
2
2
2
2
V
Input Voltage Low
0.8
0.8
liN
VIN = GND or V+
1
2
0.05
OFF State Input Cap.c
CS(OFF)
Vs= 0 V
1
2
4
4
OFF State Output Cap.c
CO(OFF)
Vo= 0 V
1
2
4
4
ON State Input Cap7
CS(ON)
Vs=Vo=OV
1
14
20
20
Bandwidth
BW
RL = 50.0.
See Figure 6
1
350
Turn ON Time
tON
1
2,3
45
70
140
70
140
Turn OFF Time
tOFF
RL = 1 k.o.
C L = 35 pF, 50% to 90%
See Switching Time
Test Circuit
1
2,3
20
50
85
50
85
Charge Injection
Q
1
25
RIN = 75.0., RL = 75.0.
1=5 MHz, See Test Circuit
1
-58
RIN = 10.0., RL = 75.0.
1= 5 MHz, See Test Circuit
1
-85
1,2
3
2.7
1,2
3
2.3
Input Current
-1
-20
1
20
0.8
0.8
-1
-20
1
20
J,lA
DYNAMIC
OFF Isolation
C L = 1000 pF, Vo= 0 V
See Test Circuit
pF
MHz
ns
pC
dB
All Hostile Crosstalkc
XTALK(AHI
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
5
7
5
7
mA
All Channels ON or OFF
-5
-7
-5
-7
NOTES:
a. ReIer to PROCESS OPTION FLOWCHART lor addltlonallnlormatlon.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are lor DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper lunctlon.
7-72
Preliminary
DG541
II"lI'" Siliconix
.IJJP incorporated
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
LOGIC "1" ; SW ON
LOGIC·
INPUT
SWITCH
INPUT
S1
V S ; +2 V 0-1----0"1
3 V
t r <20ns
t f < 20 ns
LOGIC
INPUT
""--Ik>-:e--_-o
IN1
...--0--1--<1
-15 V
(REPEAT TEST FOR IN2 .IN 3 AND IN 4 )
CHARGE INJECTION
TE~h
CIRCUIT
Avo
V
GEN
Vo
1
IN X
.l..
t
L
I
vo
ON
\
F
OFF
= MEASURED VOLTAGE ERROR DUE TO CHARGE INJECTION
THE CHARGE INJECTION IN COULOMBS IS Q ; C L" AVo
OFF ISOLATION TEST CIRCUIT
o-__~S-I--O" 4----<>-----d'
4-+=0_ _- 0 VOUT
R
SIGNAL
GENERATOR
7s.n.
7s.n.
OFF ISOLATION; 20 LOG 10
V~UT
ALL HOSTILE CROSSTALK - X TALK (AH)
SIGNAL
GENERATOR
XTALK(AH); 20 LOG 10
V~UT
7sn.
Preliminary
7-73
DG541
..,.. Siliconix
incorporated
~
BANDWIDTH TEST CIRCUIT
GE~~~~OR
'\J
76ll.
OPERATING SUPPLY VOLTAGE RANGE
20
18
16
OPERATING
VOLTAGE
AREA
14
12
POSITIVE SUPPLY VOLTAGE
V+ (VOLTS)
10
8
6
4
2
-S
-4
-3
-2
-1
NEGATIVE SUPPLY VOLTAGE
V- (VOLTS)
Note:
1. Both V+ and V- must have decoupllng capacitors mounted as close as possible to the device pins.
Typical decoupllng capacitors would tie 10J,lF tantalum bead In parallel with 100 nF ceramic disc.
2. Production tested with V+
= 15 V and V- = -3.0 V
PIN DESCRIPTION
SYMBOL
DESCRIPTION
S
An Analog Channel Input or Output
D
An Analog Channel Output or Input
IN
Logic Control Input
V+
Positive Supply voltage
V-
Negative Supply Voltage
GND
Analog and Digital Ground
7-74
Preliminary
DG542
Dual SPOT Wideband/
Video "T" Switch
...r'Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Wide Bandwidth (500 MHz)
• Improved Data Throughput
• Video Switching
• Very Low Crosstalk ( -85 dB)
and High OFF Isolation
(-75 dB) at 5 MHz
• Easily Interfaced
• High Frequency
Crosspoints
• TIL Compatible
• Low rDS(ON) < 75
• Low Insertion Loss
• Improved System Performance
• Reduced Board Space
n
• Reduced Power Consumption
• "T" Switching
Configuration
• Local and Wide
Area Networks
• Video Routing
• Fast Data Acquisition
• ATE
• ESDS Protection >
±4000
V
• Radar/FUR Systems
• Fast Switching (t ON < 100 ns)
• Break-Before-Make
Switching
DESCRIPTION
The DG542 is a very high performance monolithic
dual SPDT wideband/video switch designed for
switching wide bandwidth analog and digital signals.
By utilizing "T" switching techniques on each
channel this device gives exceptionally low
crosstalk and high OFF isolation. The crosstalk and
OFF isolation are further improved by the
introduction of GND pins between signal pins.
To achieve TIL compatibility with superior switching
performance, the DG542 was built on the Siliconix
proprietary D/CMOS process. Each switch conducts
equally well in both directions when ON.
Capacitance has been minimized to ensure fast
switching.
Packaging includes the 16-pin side braze, plastic,
and small outline options. Performance grades
include military, A suffix (-55 to 125°C) and
industrial, D suffix (-40 to 85°C) temperature
ranges.
PIN CONFIGURATION
Dual-ln-L1ne Package
IN2
O2
GNO
INI
01
GNO
51
52
V-
V+
53
GNO
Top View
Order Numbers:
Side Braze: DG542AP. DG542AP/883
Plastic: DG542DJ
Preliminary
SO Package
Top View
Order Number:
DG542DY
7-75
DG542
...... Siliconix
incorporated
~
TRUTH TABLE
FUNCTIONAL BLOCK DIAGRAM
Truth Table'
LOGIC
SW1
SW2
SW3
SW4
0
OFF
ON
1
ON
OFF
Logic "O":S 0.8 V
Logic "1" ~ 2.0 V
• All Switches shown for logic "1· Input
ABSOLUTE MAXIMUM RATINGS
V+ to V- ........•.................... -0.3 V to 19 V
V+ to GND ........................... -0.3 V to +19 V
V- to GND ........................... -19 V to +0.3 V
Digital Inputs •.....•....... (V-) -0.3 V to (V+) +0.3 V
or 20 mAo whichever occurs first
VS. VO..... ... ......... ..• (V-) -0.3 V to (V-) + 19 V
or 20 mAo whichever occurs .flrst
Continuous Current (Any Terminal) .............. 20 mA
Current. S or D (Pulsed 1 ms. 10% duty
cycle max) ..•.•.....•.•.....•....•.•......... 40 mA
Storage Temperature (A Suffix) ........... -65 to 150°C
(D Suffix) .......... -65 to 125°C
Operating Temperature (A Suffix) ......... -SS to 12SoC
(0 Suffix) .......... -40 to 85°C
Power
16-Pln
16-Pin
16-Pln
Dissipation (Package)·
Side Braze·· ......................... 900 mW
Plastic DIp··· ........................ 4S0 mW
SO···· .............................. 600 mW
All leads welded or soldered to PC board.
Derate 12 mW/oC above 75°C.
Derate 6 mW/OC above 75°C.
•••• Derate 7.6 mW/oC above 75°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
0
2=125,85°C
SUFFIX
SUFFIX
V+=lSV.V-=-3V
3=-55,-40°C -55 to 125°C -40 to 85°C
GND = 0 V
V1NH = 2 V, VINL = 0.8 VO
TEMP TYpd MINb MAX' MINb MAX~ UNIT
SWITCH
Analog Signal Range
C
VANALOG
Drain - Source
ON Resistance
rOS(ON)
Resistance Match
Between Channels
/:;.
rOS(ON)
V- = -S V
1,2,3
-S
8
-S
8
1,3
2
40
60
100
60
7S
1
2
6
6
I s =-10mA, Vo=OV
Source OFF
Leakage Current
IS(OFF)
Vs = 0 V, Vo = 10 V
1
2
-O.OS
-10
-SOO
10
SOO
-10
-100
10
100
Drain OFF
Leakage Current
IO(OFF)
Vs =10V,Vo =OV
1
2
-O.OS
-10
-SOO
10
SOO
-10
-100
10
100
Total Switch ON
Leakage Current
IO(ON)+
IS(ON)
Vs=Vo=OV
1
2
-0.07
-10
-1000
10
1000
-10
-100
10
100
7-76
V
.n
nA
Preliminary
DG542
. . . Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
D
2=125,85°C
SUFFIX
SUFFIX
V+ = 15 V, V- = -3 V
3=-55,-40°C
-55
to
125°C
-40
to
85°C
GND = 0 V
V INH = 2 V, V INL = 0.8 Va
b
b
TYpd
TEMP
MIN MAX' MIN MAXt UNIT
INPUT
Input Voltage HIGH
'{NH
1
2,3
Input Voltage LOW
'{NL
1
2,3
2
2
2
2
V
0.8
0.8
0.8
0.8
-1
-20
1
20
-1
-20
liN
VIN = GND or V+
1
2,3
0.05
OFF State Input Cap.c
cS(OFF)
VS= 0 V
1
2
4
4
OFF State Output Cap.c
Co (OFF)
Vo= 0 V
1
2
4
4
ON State Input Cap!'
CS(ON)
Vs=Vo=OV
1
14
20
20
BW
RL = 50.0.
See Test Circuit
1
500
Break-Before-Make Interval
t OPEN
RL - 1 k.o.
C L = 35 pF, 50% to 90%
See Test Circuit
1
Turn ON Time
tON
RL=1 k.o.
C L = 35 pF, 50% to 90%
Turn OFF Time
tOFF
See Test Circuit
Charge Injection
Q
Input Current
1
20
.IlA
DYNAMIC
Bandwidth
OFF Isolation
All Hostile Crosstalk
XTALK(AH)
MHz
10
10
1
2,3
65
100
140
100
140
1
2,3
25
60
85
60
85
1
25
RIN = 75.0., RL = 75.0.
f = 5 MHz, See Test Circuit
1
-75
RIN =10.o., R L =75.o.
f = 5 MHz, See Test Circuit
1
-85
1
2,3
2.7
1
2,3
2.3
C L = 1000 pF, Vo= 0 V
See Test Circuit
pF
ns
pC
dB
SUPPLY
Positive Supply Current
1+
Negative Supply Current
1-
5
7
5
7
mA
All Channels ON or OFF
-5
-7
-5
-7
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. VIN = Input voltage to perform proper function.
Preliminary
7-77
DG542
~
~
Siliconix
incorporated
SWITCHING TIME TEST CIRCUIT
Switch output waveform shown for Vs = constant with logic input waveform as shown. Note that Vs
may be + or - as per switching time test circuit. Vo is the steady state output with switch ON.
Feedthrough via gate capacitance may result in spikes at leading and trailing edge of output waveform.
VO= Vs
SWITCH
INPUT S1
V S = +2 v
LOGIC
INPUT
_--.:.R:J.L~_
RL + rDS(on)
0-1----0'1 A-ll-o-+--_-o
Vo
IN1
..-.o-i- SUBSTRATE
7-88
S 05400/540 115402
trY' Siliconix
~
incorporated
ABSOLUTE MAXIMUM RATINGS
SD5401
SD5400
SD5402
SD5401
SD5402
Vos ............. 20 V
10V
15 V
Vao ..........• 30/-25 V .... 25/-15 V ..... 30/-22.5 V
Vsoe ............ 20 V
10 V
15 V
10 .......................................... 50 mA
V OB ............. 25 V
15 V
22.5 V
Operating Temperature
VSB ............. 25 V
15 V
22.5 V
Storage Temperature
SD5400
Vas ........... 30/-25 V .... 25/-15 V .... 30/-22.5 V
VaB ........... 30/-0.3 V '"
25/-0.3 V ..... 30/-0.3 V
.................... 0 to 70·C
.................. -55 to 150·C
Power Dissipation (Package) f ••••••••••••••••• 640 mW
(Each Device) .............. 300 mW
ELECTRICAL CHARACTERISTICS a
TA
=
25°C
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
DEVICE
TYpd
MIN b MAX b UNIT
STATIC
Analog Signal Range C
Drain-Source Breakdown
Voltage
Source-Drain Breakdown
Voltage
Drain-Substrate Breakdown
Voltage
Source-Substrate Breakdown
Voltage
VANALOG
BVos
BVso
BVDB
BVSB
Vas = VBS = -5 V
10=10nA
Vao = V BO = -5 V
Is=10nA
V a B=OV,l o =10nA
Source Open
V a B=OV,l s =10)J.A
Drain Open
SD5400
-10
10
SD5401
-5
5
SD5402
-7.5
7.5
SD5400
25
20
SD5401
25
10
SD5402
25
15
SD5400
20
SD5401
10
SD5402
15
SD5400
25
SD5401
15
SD5402
22.5
SD5400
25
SD5401
15
SD5402
22.5
V
7-89
-
.... Siliconix
incorporated
505400/5401/5402
~
TA= 25°C
ELECTRICAL CHARACTERISTICS a
LIMITS
PARAMETER
SYMBOL
DEVICE
TYpd
MINb MAXb UNIT
Vos = 20 V
SD5400
1
10
Vos = 10 V
SD5401
1
10
Vos=15V
SD5402
1
10
VSO = 20 V
SD5400
1
10
VSO = 10 V
SD5401
1
10
SD5402
1
10
TEST CONDITIONS
STATIC (Cont'd)
Drain-Source Leakage
Current
10S(OFF)
Vas =V BS = -5 V
nA
Source-Drain Leakage
Current
I SO (OFF)
Vao= V BO = -5 V
VSO = 15 V
Gate Leakage Current
Threshold Voltage
laBs
VT
VOB =VSB= 0 V
VaB = 30 V
SD5400
1
V aB = 25 V
SD5401
1
V aB = 30 V
SD5402
1
VOS = Vas=VT
10=1J.J.A,VSB=OV
1.0
Vas= 5 V
50
Resistance Match C
rOS(ON)
l!.rOS(ON)
10 = 1 rnA
V SB = 0 V
2.0
V
70
30
Vas = 10 V
Drain-Source ON Resistance
0.1
J.J.A
All
.n
Vas= 15 V
23
Vas = 20 V
19
Vas = 5 V
1
5
2.4
3.5
1.3
2
DYNAMIC
Gate Node Capacitance
Ca
Drain Node Capacitance
Co
Source Node Capacitance
Cs
Reverse Transfer Capacitance
Coa
7-90
Vos=10V
Vas =VBS = -15 V
f = 1 MHz
All
pF
3.5
6
0.3
0.5
505400/5401/5402
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
TA= 25°C
LIMITS
PARAMETER
DYNAMIC
DEVICE
SYMBOL
TEST CONDITIONS
gl.
Vos = 10 V. 10= 20 mA
Vss= 0 V. f = 1 kHz
TVpd
MI~ MAXb
UNIT
(Cont'd)
Forward Transconductance
Crosstalk
15
See Test Circuits 1 and 2
f = 3 kHz
XTALK
10
mS
All
-107
dB
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. Refer to test conditions specified In Electrical Characteristics Tables.
f. Derate 5mW/oC above 25°C.
TYPICAL CHARACTERSITICS
Draln-to-Source Resistance vs.
Source-to-Substrate and
Gate-to-Source Voltage
Maximum Power Dissipation
vs. Temperature
1000
150
900
135
800
120
700
105
......
600
Po
(mW)
500
.........
400
rOS(ON)
(n)
..............
300
100
0
o
20
I
I
40
60
80
TEMPERATURE (OC)
o
100
I
10
,\~15
60
15
L
\
75
30
I
5-,!
~
45
200
I
SOURCE-TO-SUBSTRATE
_ (VSS) (V)
~
90
.... 1'
~
... __
DRAIN-TO-SOU~CE CURRENT = 5 mA-
AMBIENT TEMPERATURE (T A) = 25°C
o
Draln-to-Source Res!stance
vs. Temperature
4
8
12
16
20
GATE-TO-SOURCE VOLTAGE (VGsl (V)
Source-to-Draln Leakage
Current VS. Temperature
100
100M
90
GATE-TO-DRAIN VOLTAGE r.tGo) = 0 V
10M
80
70
VG~=
.--r
60
rOS(ON)
(n)
5V
50
VGs= 10 V __ ..
40
---t-:-::
.l
V~~_
30
1M
....... ' .
20
lOOK
Iso
(pA)
GATE-TO-SUBSTRATE VOLTAGE
VGS = 0 V
SOURCE-TO-DRAIN VOLTAGE
Vso = 10 V
10K
lK ~~~4-----~-----+~~~
100
10
1 GATE-TO-DRAIN VOLTAGE
10
0
o
25
50
75
100
AMBIENT TEMPERATURE (T A) °C
25
r.t 0) = -5 V
40
56
70
AMBIENT TEMPERATURE (T A) °C
85
7-91
..
~
~
505400/5401/5402
Siliconix
incorporated
TYPICAL CHARACTERSITICS
Source-to-Substrate Leakage
Current vs. Temperature
Oraln-to-Source Leakage
Current vs. Temperature
lOOK
SOURCE-TO-SUBSTRATE VOLTAGE
V SB = 0 V
GATE-TO-SOURCE VOLTAGE VGs= 0 V
ORAIN-TO-SOURCE VOLTAGE
Vos = 10 V '
10K
lK
los
(pA)
100
~
V
10
-"" V
V
--
SOURCE-TO-SUBSTRATE VOLTAGE
VSB=-5V
GATE-TO-SOURCE VOLTAGE
V GS = -5 V DRAIN OPEN
-
100
10
~
ISB
(nA)
~
35
45
55
65
75
85
AMBIENT TEMPERATURE (T A) ·C
.01
25
ORAIN-TO-SOURCE VOLTAGEVos = 0
SOURCE-TO-SUBSTRATE VOLTAGE
VSB = 0
GATE-TO-SOURCE VOLTAGE
VGs= 10 V
10,K
lK
.--10
-- --
-:.....-
:.....-
Crosstalk vs. Frequency
-120
....
-110
-100
-90
XTALK-80
(dB) -70
....
VIN = lV (RMS)
"
......
i'o...
"""'- .......
"
-60
-50
-40
1
25
~~
35
45
55
65
75
85
AMBIENT TEMPERATURE (T A) ·C
Gate Leakage Current vs. Temperature
lOOK
--~
.1
1
25
1000
35
45
55
65
75
85
AMBIENT TEMPERATURE (T A) ·C
TEST CIRCUIT
-30
100
1k
10 k
100 k
FREQUENCY (Hz)
~
1M
"
10 M
SWITCHING TEST CIRCUIT
TO SCOPE
CROSSTALK MEASUREMENT
Quad Switch
S05400/S05401/S05402
+Voo
'--..(Q~O VOUT
TO SCOPE
T
VOUT
600
51
600
V.
Crosstalk = 20 log,:Q!l[V
IN
Where VIN = 1 V RMS at 3kHz
7-92
600
INPUT PULSE
t r , tf < 1 ns
Pulse Width = 100 ns
Rep Rate = 1 MHz
SAMPLE SCOPE
tr < 350 ps
RIN = 1 M.n
CIN = 2 pF
805400/5401/5402
.... Siliconix
incorporated
~
SWITCHING CHARACTERISTICS
SWITCHING WAVEFORMS
tr (ns)
td(on)(ns)
OV
+Voo - - - "
*toFF(ns)
voo
RL
TYP
MAX
TYP
MAX
TYP MAX
5
6BO
0.6
1.0
0.7
1.0
10
6BO
0.7
0.8
9.0
15
1k
0.9
1.0
14.0
9.0
* tOFF Is dependent on RL and does not depend
on the device characteristics.
THEORY OF OPERATION
The S05400 series consists of four SPST switches
with analog signal capability of ±10 V for the
S05400, ±5 V for the S05401 and ±7.5 V for the
S05402. Each switch of the array is a OMOS
N-channel field-effect transistor of the enhancement-mode type; that is, the device is normally
OFF when gate-to-source voltage ('IGs) is 0 V.
When VGS exceeds the threshold voltage, VT, the
FET switch starts to turn ON. With VGS in excess of
+10 V, a low resistance path (typically 30 n) exists
between input and output of the switch. Figure 1
shows the normal mode of operation of a single
switch of the array for ±5 V analog signal
processing. Note that the source is recommended
for the input since feedback or reverse transfer
capacitance is lower when drain is used as the
ouput. When analog signals are routed from one
point to another the important factors are isolation,
crosstalk between switches, feedthrough and
feedback transients, insertion loss and speed of
operation.
The S05400 series offers superior
performance in all these areas (Figure 1).
n
Isolation. ON resistance is typically 30
and OFF
resistance is typically 1010 n, which results in an
OFF to ON resistance ratio in excess of 108
Isolation from output to input from 3 kHz analog
signals is typically -107 dB, and at 1MHz the
isolation is typically 60 dB.
Feedback and feed through transients are kept to a
minimum because of the very low feedback and
feedthrough capacitances.
This means that
"glitches" are minimized, resulting in "clean"
signals at the output.
Insertion loss depends upon the source and load
impedances involved. As an example, for 600 n
source impedance the insertion loss for voice
signals (1 VRMS @ 3 kHz) is less than 0.3 dB. Thus
the S05400 series makes good telephone
cross-point switches.
Speed. Because of the low ON resistance and low
input capacitance, the S05400 switches turn ON at
subnanosecond speeds. They are also capable of
handling very high frequency analog signals and still
maintain excellent isolation (20-30 dB @ 1 GHz).
+5
INPUT
-5
+10
D
'--f-t-~-o
GATE
OUTPUT
(±5 VI
-10
+5
OUTPUT
-5
Figure 1
7-93
•
S05400/5401/5402
..... 8i1iconix
incorporated
~
APPLICATION
Figure 2 shows an 805402 configured for operation
as an audio crosspoint switch. For more detailed
information on this application, see AN83-7.
LEFT INPUT
SUMMING
NODE FROM
OTHER SWITCHES
75 kn
INPUT
CHANNEL 1
RA 76kn
o-:IN~PU.;:.:.T....:N.:.:O::D:.:E:""':'.AJ\RI\Sr--_-+~-O'jI"E-...o:..T-_-+
10 knRG
LEFT INPUT BUS
IG
I
LF347
I
~_..JI
':"
_~
(+V)
INPUT NODE
o-o""""&....1...f-G- . ,
RS
I
>-+~6'V:'V:nlr-'---o ~~~N~~:UT
I siD I
CHANNELl O-:~~~~~I\I\r----+~~"E-...o:..+-~
RIGHT INPUT BUS
76 kn
I
':"
RS
RO
soon
SUMMING AMP
I
I
I
RA
CHANNEL 2 o-::IN,::,Pi-UT:..:....:.N::O;,:D:.:E,--,,75Mkn
_ _-+I.l2s'---~6'Vo'Vo"n-"'-O ~~~~~T
I
CHANNEL 2 o-::IN",PfUT"-,N""O""D,,,E"-.AJ\RS"""_ _+"S'- 19 V
• Fast Level Shifting
• Fast Switching
(tOFF < 1.5 Ils)
DESCRIPTION
The 0125 contains six drivers, designed to perform
the level-shifting and amplification needed to
interface low-level logic outputs and field-effect
transistor switches (MOSFET or JFET). With the
input logic supply, (vd, at 5 V, the driver output
reference, (V-) may be set between -1 and -25 V.
Each output is designed to sink 5 mA of current in
the ON condition, and to hold off up to 30 V in the
OFF condition. The input stage is a base-input PNP
transistor, with the emitter returned to theVL supply
through a resistor. To turn the driver ON, the logic
stage driving it must be capable of sinking 0.7 mAo
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Package options include the 14-pin side braze and
flatpack packages. Performance grades include
both the industrial, B suffix (-25 to 85°C) and
military, A suffix (-55 to 125°C) temperature
ranges.
Flat Package
v-*
2
3
4
S
6
7
IN1
IN2
IN3
IN4
INS
IN6
ENABLE (Vd
OUT1
OUT2
OUT3
OUT4
OUTS
OUTs
14
13
12
11
10
9
8
OUT1
VL
Top View
Order Numbers: D12SAL/883
OUT2
• Common to Substate and Base of Package
IN 3 o--t----Q
OUT3
Dual-In-Llne Package
V-
OUT1
IN1
OUT2
OUT 4
OUT3
11
OUT4
OUTS
INS
OUTS
INs
OUTs
INS
IN6
~--~Top View
Order Numbers:
D12SAP, D12SBP
Not Recommended for New Designs
8-3
iii
0125
~
Siliconix
.£II incorporated
ABSOL.UTE MAXIMUM RATINGS
Vo to V- ..................................... 36 V
V L to V- ...................................... 30 V
30 V
±6 V
Current, (Any Terminal) ....................... 30 mA
Storage Temperature ................... -65 to 150°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(9 Suffix) .......... -25 to 85°C
Power dlsslpatlon*
Flat Package* * ............................. 750 mW
14-Pln DIp·· * .............................. 825 mW
All leads soldered or welded to PC board.
** Derate 10 mW/oC above 75°C.
* ** Derate 11 mW/oC above 75°C.
EL.ECTRICAL. CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
A
B
Unless Otherwise Specified:
2=125,8S oC
SUFFIX
SUFFIX
V- = 20 V
3=-55, -25 ° C -55 to 125°C -25 to 85°C
V L= 5 V
TEMP TYpd MINb MA>f MINb MAXt UNIT
SYMBOL
OUTPUT
Output Voltage LOW
VOL
10= 5 mA, VL= 4.5 V
VIN = 0.5 V
1,3
2
-19.8
-19.6
-19.5
-19.6
-19.5
V
Output Current HIGH
IOH
Vo = 10 V
V IN = 4.6 V
1,3
2
0.005
0.1
10
0.1
10
JlA
Input Current Voltage HIGH
'INH
VIN = 4.6 V
1,3
2
0.001
1
20
JlA
Input Current Voltage LOW
'INL
V IN = 0
INPUT
1,2,3 -0.15
-1
-10
1
10
-0.7
-1
'-20
-1
mA
DYNAMIC
Turn-ON Time
tON
1
0.11
0.5
0.5
1
1.05
1.2
1.5
1,2,3
-1.5
1,2,3
1.6
1,3
2
-0.09
1,3
2
0.09
See Switching Time
Test Circuit
Turn-OFF Time
tOFF
JlS
SUPPL.Y
Negative Supply Current
1-
-2,5
-2.5
VIN1 = 0
All OtherVIN = 4.6 V
Logic Supply Current
IL
Negative Supply Current
1-
mA
2.5
-2
-200
2.5
-2
-100
AIIVIN = 4.6 V
Logic Supply Current
IL
JJ.A
1
100
2
100
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet,
c, Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
8-4
Not Recommended for New Designs
~
~
0125
Siliconix
incorporated
DIE TOPOGRAPHY
Pad
No.
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
_55mIlS~
7654321
,,-
-j
C® 8~~~~~~~...I~mIlS
9
10 11 12 13 14
20X
Function
V - (Substrate)
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
VL
Output 6
Output 5
Output 4
Output 3
Output 2
Output 1
IBAF
12 Resistors
6 PNP bipolar Transistors
6 NPN Bipolar Transistors
SWITCHING TIME TEST CIRCUIT
t r -< 100 ns
tf<100ns
lOUT
2 rnA
.xH---t---(J V OUT
I35
+
(90%)
COUT
PF
V-
Not Recommended for New Designs
8-5
0129
4-Channel MOSFET
Switch Driver with Decode
..... Siliconix
incorporated
~
APPLICATIONS
BENEFITS
FEATURES
•
TTL Compatible
•
4 Independent Drivers
•
Output Sink Current to
10 mA
•
DC Level Shifts to >19 V
•
Reduces System
Component Requirements
•
Fast Level Shifting
•
Interfacing Low Level
Logic to MOSFETs
or JFETs
•
Designed to Interface
with G118 and G119
DESCRIPTION
The D129 is a four-channel driver designed to
provide the DC level-shifting and amplification
functions needed to interface low-level logic
outputs (0.7 to 2.2 V) and field-effect transistor
switch inputs (up to 50 V peak-to-peak). With an
Input logic supply of 5 V, the output transistor
emitter, (V-), may be set at any voltage between
-5 and -30 V. In the ON state, the output collector
will sink up to 1.0 mA of current, and in the OFF
state will hold off voltages up to 50 V above V-.
Each of the four drivers has a 3-input logic gate,
and the driver will be ON when each of the inputs
PIN CONFIGURATION
are either open or at positive logic "1".
With any of the inputs either grounded or at positive
logic "0", the driver will be OFF. Some of the logic
inputs to the four gates are internally connected to
facilitate decoding from a binary counter, however,
'one input to each gate provides a means for
independent operation of each driver, if desired.
Package options include the 14-pin side braze and
flatpack packages. Performance grades include
both the industrial, B suffix (-25 to 85°C) and
military, A suffix (-55 to 125°C) temperature
ranges.
FUNCTIONAL BLOCK DIAGRAM
Flat Package
INI
IN2
IN3
IN4
INS
INe
IN7
1
2
3
4
S
e
7
vL
14
13
12
11
10
9
8
OLrr 1
OLrr2
OLrrs
OUT4
v- •
vR
INI
IN2
OUT 1
IN3
OUT2
Top View
Order Number: D129AL
• Common to Substrate and Base of Package
N··O·",
IN4
Dual-In-Une Package
IN22
IN3 3
IN4 4
INS S
INee
IN7 7
13 OUT 1
12 OUT2
11 OLrr 3
10 OLrr 4
9V8 vR
INs
INs
IN7
OUT3
OUT4
Top View
Order Numbers:
D129AP or D129BP
8-6
Not Recommended for New Designs
~
~
0129
Siliconix
incorporated
ABSOLUTE MAXIMUM RATINGS
Operating Temperature (A Suffix) .......•. -55 to 125°C
(8 Suffix) .......... -25 to 85°C
Power Dissipation"
Flatpack"" ................................. 750 mW
14-Pln DIP""" ......•...................•... 825 mW
Vo to V- (A Suffix) .......•..••................ 50 V
Vo to V- (8 Suffix) .••.•..........•...•........ 36 V
V R to V- (A Suffix) • . . . . . . • • • . . • • . . . . . . . . . . . • . .• 33 V
VR to V- (8 Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24 V
VL toVR ..•..............•..................... 8 V
VIN toVR .•.•...........•.............••.•.... ±6 V
VIN to VIN (Any Other VIN Terminals) . . . . . . . . . . . .. 6 V
Current, (Any Terminal) ...............•....... 30 mA
Storage Temperature ................... -65 to 150°C
All leads soldered or welded to PC board.
Derate 10 mW'oC above 75°C.
""" Derate 11 mW'oC above 75°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
VL= 5 V
V- = -20 V
VR= 0 V
SYMBOL
LIMITS
1=25°C
A
B
2=125,85°C
SUFFIX
SUFFIX
3=-55,-25°C -55 to 125°C -25 TO 85°C
TEMP TYpe
MINb MA>f MINb MAXb UNIT
OUTPUT
Output Voltage, LOW
Output Current, HIGH
VOL
VIN = 2.2 V
VL = 4.5 V
lOUT = 10 mA
1,3
2
-19.8
-19.3
-19.0
lOUT = 1 mA
1
-19.75
-19.8
0.005
0.1
20
0.2
10
0.25
5
1
5
IOH
Vo= 10 V
V IN =0.7V
1,3
2
IINH
VIN = 5 V, Input Under Test
VIN = 0 V, All Other Inputs
1,3
2
-19.25
-19.0
V
JJ.A
INPUT
Input Current, Voltage HIGH
Input Current, Voltage LOW
IINL
VIN = 0 V, VL = 5.5 V
tON
See Switching Time
Test Circuit
(CL= 35 pF)
1
2
3
-0.2
1
0.22
-200
-160
-250
JJ.A
-225
-200
-250
DYNAMIC
Turn-ON Time
Turn-OFF Time
tOFF
0.3
0.3
JJ.s
1
1.16
1
-1.5
1
2.2
1
-0.01
1
0.46
1.5
1.5
SUPPLY
Negative Supply Current
1-
-2
-2.25
One Channel
ON
Logic Supply Current
IL
Negative Supply Current
1-
Logic Supply Current
IL
V- = -20 V
VL = 5.5 V
AIIVIN=OV
All Channels
OFF
mA
3
-10
3.3
-25
0.75
JJ.A
1
mA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Not Recommended for New Designs
8-7
iii
0129
DI~
.... Siliconix
incorporated
~
TOPOGRAPJ:lY _
1. .
mllsl---··1
1 - - - - - 76
543
2
,~mils
7
60
B
9
10
11 12
13
~
Pad
No.
Function
1
2
3
4
5
6
7
B
9
10
11
12
13
14
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
VR
V- (Substrate)
Output 4
Output 3
Output 2
Output 1
VL
20X
IBADA
10 PNP Bipolar Transistors
2 NPN Bipolar Transistors
3 Diodes
4 Capaoltors
9 Resistors
4 N-channel depletion JFET
SWITCHING TIME AND TEST CIRCUIT
tf
tr
V+
= +5 V
tpw
+10 V
r
f
~>--Jt--t'-o()
V- = -20 V
8-8
p
< 100 ns
< 100 ns
= 1J1.s
= 100 kHz
OUT
,
OUT
+10 V - - - - - - - .
0 V ' - - - - - -......I
_20V------~1~7~V-~~9~0~%~--J
Not Recommended for New Designs
..or Siliconix
~
0139
Monolithic 2-Channel
FET Switch Driver
incorporated
FEATURES
BENEFITS
APPLICATIONS
•
•
•
•
•
•
•
•
•
Interfaces Low Level
Signal to FET Switches
•
•
TIL to CMOS
•
Double-throw Switch
Control
Complementary Outputs
150 ns Propagation Time
30 V Output Swing
Versatile
Minimizes Switching Time
Easily Interfaced
Current Source Coupling
TIL Compatible
TIL to PROM Logic Levels
DESCRIPTION
power supplies allow wide flexibility in the actual
output voltage levels.
Complementary outputs
permit maximum application versatility, allowing
functions such a double-throw analog switch
control. A positive logic" 1 " at the input provides a
" 1" at OUT and a .. 0" at OUT.
The D139 is a dual low level to high level voltage
Uses
translator with complementary outputs.
include bipolar to MOS logic interface and bipolar
logic to FET analog switch control. The following
characteristics of the input circuit provide an ideal
interface to the common logic forms TIL, CMOS,
and DTL: light loading (-113 TIL load) to "0" inputs,
a 1.2 V trip point, and high input impedance with
high breakdown to "1" inputs. The output can drive
up to 30 V peak-to-peak into pure capacitive loads
or moderate resistive loads:
Current source
coupling between the input and output and split
The D139 is offered in 1o-pin metal can, plus 14-pin
PDIP, side braze and flat pack packages.
Performance grades include military, A suffix (-55
to 125 DC) and commercial, C suffix (0 to 7oDC)
temperature range.
PIN CONFIGURATION
TO-100
Top View
Dual-ln-L1ne Package
NO
NO
Flat Package
NO~~14
NO
OUTI
OUTI
2
3
4
13
12
11
IN,
5
6
10
9
v+
vL
NO
NO
OUT2
OUT2
IN2
v-
VR
Top View
Order Number: D139AA 1883
* Common to Substrate and Case
Order Number:
Side Braze: D139AP/883
Plastic: D139CJ
Not Recommended for New Designs
Order Number:
D139ALl883
8-9
..
0139
~
~
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
LOGIC
OUT
0
V-
V+
1
V+
V-
L..---o OUT 1
OUT
.----oOUT 2
Logic "0" :$ 0.8 V
Logic "1" ~ 2.0V
ABSOLUTE MAXIMUM RATINGS
V+ to V- ....•.....•.......................... 36 V
V+ tOVR •..........•........•••......•....•... 36 V
V+toVo ••....•.....•.....•....••.......•..•• 36V
VltoVR .........•••..••••....•••..•.•.....•... 8V
VIN tOVR ••..•••.•.•.••....••.................. 8 V
VR to V- •••.•.•........................•••.... 36 V
Vl to V- ••...•.•........................••...• 36 V
Vo to V- •.•..•.••...••••..•......•••......... 36 V
Vl toVIN ••....•.••..•.•...••••.•..•••....•..•. 8 V
CURRENT, (Any Terminal) DC ...••..••......•• 12 mA
Peak Current (Any Terminal)
(200 JJ,s pulse width, 100 pps) ....•••••...•••.• 100 mA
Operating Temperature (A Suffix) ...•....• -55 to 125°C
(C Suffix) ........•... 0 to 70°C
Storage Temperature (A Suffix) ••••...•• -65 to 150°C
(C Suffix) .......... -65 to 125°C
Power Dissipation' (L Package)" ••••...••••.. 900 mW
(P Package)'" . . . . • . . . . . .. 825 mW
(A Package)···· .......... 450 mW
Thermal Resistance (e JA , J Package) ..•... 0.16°C/mW
All leads soldered or welded to PC board.
Derate 10 mW/oC above 75°C.
Derate 11 mW/oC above 75°C.
•••• Derate 6 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
C
A
Unless Otherwise Specified:
2=125,700C
SUFFIX
SUFFIX
V+ = 10 V, Vl = 5 V
o to 70 0 C
3=-55 O°C -55 to 125 0 C
V- = -20 V, VR = 0 V
SYMBOL
TEMP TYpd MINb MA>f MINbMAX t UNIT
OUTPUT
1
2
3
0.6
0.9
0.7
1.1
0.9
0.7
1.1
lOUT = -2 mA
1,2,3
0.82
1.5
1.5
1
2
3
0.52
lOUT = 10J1A
1.1
0.9
1.3
1.1
0.9
1.3
IOUT=2mA
1,2,3
1.5
1.5
10
20
10
20
IOUT=-10JJ,A
Output Voltage HIGH
V+toVo
Output Voltage LOW
Vo to V-
VOH,
VCiH
VOL'
VOL.
VIH=2V
forVOH
Vil = 0.8
for VOL
V
INPUT
Input Current Voltage HIGH
IINH
VIN=5V
1
2
0.003
Input Current Voltage LOW
IINl
VIN=OV
1,2
3
-18
JJ,A
8-10
-500
-600
-500
-600
Not Recommended for New Designs
0139
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
1=25·C
A
Unless Otherwise Specified:
2=125, 70·C
SUFFIX
V+=10V, V L = 5 V
-55 to 125 0 C
3=-55, O·C
V- = -20 V, VR = 0 V
SYMBOL
TEMP TYpd MINb MA~
PARAMETER
C
SUFFIX
o to 70·C
MINb MAXb UNIT
DYNAMIC
Switching Time LOW to
High, Delay Plus Rise Time
t
SWltchln~
t(_)
Time HIGH to
Low, De ay Plus Fall Time
(+)
See Switching Time
Test Circuit
C L = 35 pF
1
65
170
170
1
90
200
200
1
0.01
0.1
0.1
1
2.2
4
4
1
-1.6
-3
-3
ns
SUPPLY
Positive Supply Current
1+
Logic Supply Current
IL
Negative Supply Current
1-
VIN = 0 or 5 V
mA
Reference Supply Current
Input Voltage HIGH
IRH
V IN1 =VIN2 = 5 V
1
-0.66
-1.6
-1.6
Reference Supply Current
Input Voltage LOW
IRL
V IN1 =VIN2 =
aV
1
-0.63
-1.1
-1.1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. All dc parameters are 100% tested at 25°C. Lots are sample-tested for ac parameters and HIGH and LOW temperature
limits to assure conformance with specifications.
DIE TOPOGRAPHY
:-r
43 mils
L..---------I_!
9
Pad
No.
3
4
5
6
7
8
9
10
11
12
Function
Out 1
Out 1
Input 1
V+
VL
VR
V- (Substrate)
Input 2
Out 2
\Ji:in
CMOA
4 Diodes
4 Capacitors
11 Resistors
4 P-channel enhancement MOSFET
10 PNP Bipolar Transistors
12 NPN Bipolar Transistors
Not Recommended for New Designs
8-11
0139
. . . Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUIT
LOGIC INPUT
tr < 20 ns
tf < 20 ns
5 V
VL
10 V
V+
.---+---t----o V OUT
L..,.._-,-":::::li-T-o V OUT
(VOUT IS THE COMPLEMENT OF V OUT)
8-12
Not Recommended for New Designs
0169
...... Siliconix
incorporated
~
Dual High-Voltage Driver
FEATURES
BENEFITS
APPLICATIONS
• 33 V Output at ±40 mA
• Wide Output Swing
• Analog Multiplexing
• Variable Input Threshold
• Logic Family Flexibility
• 70 ns Delay Time
• Fast Switching
• Interface Logic to
MOS Power
• Complementary Outputs
• Drive Coupler H Bridge
Power Circuit
• Logic Level Translation
• Driver for PIN Diodes
and FET Switches
• Line Driver
DESCRIPTION
The D169 is a versatile high-voltage dual driver
designed with complementary outputs making it
excellent for driving capacitive loads. By combining
a wide output voltage swing (33 V) with fast
switching (100 ns delay) make this device well
suited for driving power MOSFET configurations.
A differential input stage with adjustable threshold
provides high input impedance and easy interfacing
to low level logic or analog inputs. Current-source
coupling to the output stage allows flexibility in
output voltage levels, while the complementary
emitter-follower outputs can source and sink
currents of up to ±40 mAo Each channel of the
D169 has 2 separate outputs that are com pie menPIN CONFIGURATION
OOT,
tary (OUT and OUT) allowing easier driving of
MOSPOWER devices. The output can be operated
by single or split supplies.
The D169 is especially adept in driving capacitive
loads such as power MOSFETS, long cables, timing
capacitors, and PIN diodes. Analog mulitplexing is
simplified by the wide range of interface logic levels
accepted, and wide output voltage swing.
Packaging for this device includes 14-pin sidebraze, CerDIP, and plastic DIP options. Performance grades include military, A suffix (-55 to
125°C) and commercial, C suffix (0 to 70°C)
temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
3
OUT,
IN,
v-
v+
V L ---'I.-_ _.s-
Top View
Order Numbers:
Side Braze: D169AP, D169AP/BB3
CerDIP:
D169AK, D169AK/BB3
Plastic:
D169CJ
LOGIC
OUT
OUT
0
VV+
V+
V-
1
Logic "0"
S 0.8 V
Logic "1"
~2.0V
8-13
0169
...... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
V+ to
v-,
V+ toV R, V+ toVo ................... 36 V
VL toVR, VIN toVR, andVL toVIN ............... 10 V
VRtoV-,VL toV-, andVotoV- ................ 36V
Current (Any Terminal) DC ..................... 40 mA
Peak (Pulsed 1 ms, 10% Duty Cycle) ........... 150 mA
Operating Temperature (A Suffix) ......... -55 to 125°C
(C Suffix) ........... 0 to 70°C
Storage Temperature (A Suffix) .......... -65 to 150°C
(C Suffix) ........... -65 to 125°C
Power
14-Pln
14-Pln
14-Pln
Dissipation·
Side braze DIp··
825 mW
CerDIP··· ........................... 825 mW
Plastic Dip···· ....................... 470 mW
Thermal Resistance (
BJA •
J Package) .... 0.16°C ImW
All leads soldered or welded to PC board.
Derate 11 mW/OC above 75°C.
Derate 11 mW/oC above 75°C.
•••• Derate 6.5 mW 1°C above 25°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
A
C
Unless Otherwise Specified:
2=125,70 o C
SUFFIX
SUFFIX
V+=15V,VL=5V
-55 to 125 0 C o TO 70 0 C
3=-55, O°C
V- = -15 V, VR = 0 V
SYMBOL
TEMP TYpe MIN b MAX> MINb MAXt
UNIT
OUTPUT
Output Voltage HIGH
(V+ toVO)
1,2
3
0.7
1
1.1
1
1.1
IOUT= 40 mA
1,3
2
1.5
2.5
3.1
2.5
3.1
IOUT= 1 mA
1,2,3
-0.75
-1.2
-1.2
1,3
2
-2.2
-3
-4
-3
-4
VoH/VOP.
V IH = 2.0 V
or
V IL = 0.8
Output Voltage LOW
rio to V-I
IOUT= 1 mA
V
VOL/VOL
lOUT = 40 mA
INPUT
Input Current Voltage HIGH
IINH
VIN = 3 V
1
2
1
Input Current Voltage LOW
IINL
VIN=OV
1,2
3
-25
1
80
170
170
1
90
200
200
5
5000
-50
-100
5
5000
-50
-100
nA
J.LA
DYNAMIC
Switching Time Low to
High, Delay Plus Rise Time
t
SWltchln~
t (_)
Time High to
Low. De ay Plus Fall Time
8-14
(+)
See Switching Time
Test Circuit
(C L = 35 pF)
ns
0169
..,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
1=25°C
A
C
Unless Otherwise Specified:
2=125,70°C
SUFFIX
SUFFIX
V+ = 15 V, VL = 5 V
0
3=-55, O°C
-55 to 125 C o TO 70 0 C
V-=-15V, VR=OV
SYMBOL
TEMP TYpe MINb MAX' MINb MAX' UNIT
PARAMETER
SUPPLY
Switching Crossover Level
V xo
Positive Supply Current
1+
Logic Supply Current
IL
Negative Supply Current
1-
Reference Supply Current
IR
C L = 200 pF
1
0.9
V
1
V1N1 =VIN2 = 0 V
No Load
1
3.2
1
-2.2
1
1.0
0.1
0.1
4
4
mA
-3.0
-3.0
1.5
1.5
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
DIE TOPOGRAPHY
' .....,...6---68 mllS's---..... ,
Pad
No.
Function
3
OuT 1
4
OUT1
IN1
V+
VL
VR
V - (Substrate)
IN2
OUT2
OUT2
5
6
7
8
7
43 mils
8
9
10
11
12
20X
CMOS
4 Diodes
4 Capacitors
7 Resistors
4 P-Channel Enhancement MOSFETs
10 PNP Bipolar Transistors
8 NPN Bipolar Transistors
8-15
III
0169
..... Siliconix
incorporated
~
SCHEMATIC DIAGRAM (One Channel)
LEVEL DETECTOR
f
A
COMPLEMENTARY
FOLLOWER OUTPUTS
LEVEL SHIFTER
,
A
A
f
,
VL
V+
01
05
02
R2
3.2 kJl
07
IN
OUT
03
08
04
09
VR
OUT
010
03
R3
R4
5.1 kJl
5.1 kJl
04
V-
8-16
0169
..... Siliconix
incorporated
~
SWITCHING TIME TEST CIRCUITS
~~~o-~~OVOUT
VIN
TEST
#
VL
VR
V+
V-
1
5V
0.7 V
10V
0
200
2
5V
0.7 V
15V
0
0
510n
pF
pF
200 pF
1000 pF
-
CL
3
5V
0.7V
10 V
0
4
6V
0.7V
10V
0
6
5V
0
15V
-15 V
6
5V
0
15V
-15V
pF
200
1000
VIL
VIH
-
1V
3.5V
A
v
3.5V
B
1
1V
3.5V
B
1V
3.5V
B
0
3.5V
B
0
3.5V
B
-
RL
WAVEFORMS
RL
~!.!.i-;':"""o-~~OV OUT
RL
--rs.J
~,e
a
Test Conditions
VR
V-
Test Circuit
0~1.~0~V==~~__________-+~====~
o
_~V~I~L::~+-______________~::::::::::;:
Waveforms A
Waveforms B
Test 2
Tests 5 & 6
V+
=15 V,
V-
Tests 3 & 4
=-15 V
Capacitive Load
V+
=15 V,
V-
=0 V
Capacitive Load
Resistive
10 25 mA
200 pF
1000 pF
200 pF
Delay Time, to+
70
95
220
110
230
ns
Rise Time, tR+
35
60
240
55
200
ns
Parameter
=
1000 pF
Units
Low-to-Hlgh
Hlgh-to-Low
Delay Time, to-
50
50
80
55
80
ns
Fall Time, tF-
25
110
400
80
275
ns
Typical Switching Times
8-17
0169
W1P" Siliconix
~
incorporated
TYPICAL CHARACTERSITICS
Effect of Temperature on
Supply Currents
Supply Current Variation with
Logic Supply
7
4.0
r----r---~---r---.,
SEE TEST #5
NO LOAD
6
I-,I R
IL
(mA)
=
3.0 t----!-....;::"""'......
5
. /V
IL
4
3
./
2
. /V
/
~
o
~
1-
V
"IR
6
7
./
I-,I R
I L 2.0
(mA)
V V
2
3
4
5
8
9
10
1----+---+---'==-.....=::----1
0 .....- - " " - - -.......- - - - " - -........
-55
-15
+25
+65
+125
T - TEMPERATURE (OC)
11
(\1. - VR}-LOGIC SUPPLY VOLTAGE (VOLTS)
Logic Input Current VB. Logic
Input Voltage
-100
Switching Times with Resistive Load
1000
700
500
I
\1.=5V_
VR = 0 V
-80
V+~+10v'
}
tR+ , /
V- = -10 V
V
300
V
200
-60
!IN
tsw
(ns) 100
70
50
(J.LA)
-40
"'\
-20
30
to+
V vV'
tF
~
./
~
V
L
IL
~
to
20
\
o
YiN -
2
3
4
5
LOGIC INPUT VOLTAGE (VOLTS)
2
4 6 10
20
40
+10- OUTPUT CURRENT (mA)
Effect of Load Capacitance on
Crossover Time
1000
SEE TEST #1
500
5.0
300
--
200
txo
(ns)
Effect of Load Capacitance on
Crossover Level
10
SEE TEST #1
100
100
50
../
~
2.0
~
.".,.,.. V
Vxo 1.0
...,. oC
51-----boo..,e::;.-:::;oI"c..--~"""---___1
,
tR-
20
SEE TEST #2
o~----~----~----~--~
10
15
20
25
o
30
20
30
10
10 - LOAD CURRENT (rnA)
IV+I+IV-I - OUTPUT SWING (VOLTS)
Fall Time with Capacitive Load
Switching Times with
Capacltlve Load
2000
2000
1000
1000
700
500
tsw 200
(ns)
l,.......---" ~
to+
100
70
50
30
20
tR/
~
1..00"": ___ 1"""
..... .....
50
100
~
V/
500
1000
30
20
5000
. / "/"
,. :;.....-0"'"
50
100
CL - LOAD CAPACITANCE (pF)
Output • Low" Characteristics
PULSED: 80 /Ls, 2%
RA~ED 6c
CURRENT -
V OL- V- 4
(V) 3
~V
I.
V+ -VOH
(V)
dc -
4
V+ = +15 V
V- = 0
L~ ~
3
2
",.
20
30
40
5000
RJED
CUrEN[ -
5
k::: :,....--
V+ = +15 V
V- = -15 V
I
I
~
10
2000
I
6
~
...... V "
o
1000
PULSED: 80 /LB, 2%
5
V
500
Output "High" Characteristics
7
2
200
CL - LOAD CAPACITANCE (pF)
7
6
rL
./
~ /V-=OV
100
70
50
2000
/
./
//
tF 200
(ns)
to200
V- = -15 V
300
/'
, ...,
L
700
500
./
/.
V+ = 10 V to 30 V
SEE TEST #3
SEE TEST #3
300
40
50
60
70
10L - OUTPUT "LOW· CURRENT (rnA)
80
o
10
20
30
40
50
60
70
80
10H - OUTPUT "HIGH" CURRENT (rnA)
8-19
0169
WY'Siliconix
incorporated
~
OPERATING GUIDELINES
40 mA LOAD, V+ = 20 V, VSwitching Waveform
=0 V
+40 mA LOAD, V+ = 10 V, V- = -10 V
Switching Waveform
For proper performance of the 0169 circuit, certain guidelines must be followed for the power supply and Input terminals.
These are listed below.
TERMINAL
ALLOWABLE CONDITIONS
I
V+ !Pln 61
V- Pin 9
Any positive voltage
Any negative voltage or
zero volts
V R (Pin 8)
VL (Pin 7)
IN1L, IN2L (Pins 5, 10)
IN1H, IN2H (Pins 5, 10)
l!: V EE + 1 V (Input Threshold = VR + 1.4 V)
V L - V R l!: 4 V
l!:VEE + 1 V
l!:VEE + 3 V
10 VS V+ - V-S 36 V
CIRCUIT OPERATION
The D169 circuit has three sections: (1) an input
level detector, (2) a level shifter, and (3) a pair of
complementary emitter-follower outputs. This
arrangement provides a high input impedance. high
output drive capability. and compatibility with a wide
range of power supply levels. The input threshold
level can be easily varied to accept various logic
levels. Output swing is set by the V+ and V- power
supply levels.
Level Detector
Transistors Oland 02 form a differential input pair.
Transistor 00. resistor R1. and diodes D1 and D2
form a current source of about 1 mA which drives
8-20
the common emitter connection. The voltage
between supply levels V L and V R determines the
trip point where the circuit changes state. With V R
grounded. the trip point is about 1.4 volts.
depending somewhat on the voltage V L. The input
characteristics are shown in Figure 5.
Level Shifter
Schottky-clamped transistors 03 and 04 along with
P-channel MOSFETs 05 and 06 form a complementary-coupled switching stage. This configuration draws no idle current and permits a change of
state within 100 ns after the input signal passes the
trip point. The circuit delays are such that the
.-r Siliconix
incorporated
0169
~
CIRCUIT OPERATION (Cont'd)
that the switching action approaches a "break-before-make" sequence as shown in Figure 15. The
response times are essentially independent of the
input signal level and rise time.
The time measured from the input signal step to
where the output waveforms from OUT and OUT
c,oss is called cross-over time. The voltage level at
that time with respect to V- is called crossover
voltage. This point is of importance when driving
certain loads where a break-before-make action is
necessary to avoid high current surges. The
crossover time is essentially independent of output
voltage swing, but is affected by the load capacitance as shown in Figure 7. The delay time of the
negative going waveform from OUT and OUT is not
significantly affected by load capacitance; however
the delay time of the positive going waveform
experiences a delay which is fairly sensitive to load
capacitance. This feature reduces the dependence
of crossover voltage on the load capacitance as
shown in Figure 8. However, the output voltage
swing does exert considerable influence upon
crossover level as indicated in Figure 9.
In order to provide adequate drive to Q3 and Q4,
the voltage at the collector of the differential pair
must be more positive than the V- level plus the
base emitter drop of the schottky transistors. This
dictates that the "low" level of V IN should exceed
V- by at least one volt.
APPLICATIONS
Totem-Pole Driver with Bootstrapping
When driving MOSPOWER in a totem-pole output
configuration (see Figure 17), it is necessary to
have the gate voltage 10 to 15 voits positive with
respect to the source in order to handle load
currents near the MOSPOWER maximum ratings.
The 0169 lends itself to bootstrapping because of
its high voltage ratings.
+15 V
+5 V
In the circuit shown, the voltage on the 2000 pF
bootstrap capacitors is applied via diode .. OR"
gates to the V+ terminal; therefore, regardless of
which output is high, 30 V is present at V+.
Maximum switching frequency is determined by the
input capacitance of the MOSPOWER transistors
used.
0-------------,....------,....-----,
0--,....-......---,
TTL or
CMOS
INPUTS
I
I
.VRB
. --":19-..1
Vi
Figure 17. Totem-Pole Driver with Bootstrapping
8-21
0169
W7' Siliconix
~
incorporated
APPLICATIONS (Cont'd)
Voltage-to-Frequency Converter
A simple, low-cost VFC can be designed using the
0169 and a single op amp (see figure 18). The
0169 serves as a level detector and provides
complementary outputs. The op amp is used to
integrate the input signal VIN with a time constant of
R1C1. The input, which must be negative, causes a
positive ramp at the output of the integrator which
is then summed with a negative zener voltage.
When the ramp is positive enough to cause the
D169 input (pin 10) to exceed the logic threshold of
1.4 V, then the 0169 outputs change state and
OUT 2 flips from negative to positive. This positive
output of approximately 11 V puts transistor Q 1 into
saturation which then resets the integrator to near
zero. The integrator peak differential voltage t:.. V will
be approximately 9.2 V. The output frequency f 0,
neglecting the short reset interval, will be
The pulse repetition rate. fo. is directly proportional
to the negative input voltage VIN.
+5 V
r
5
+12 V
16
7-_._.,
1 '"
1
3
'--1--11-"---0 OUT 1
112
r---1"":::"-O
CiIT'f"2
1
1
'----1..!1.:...1~O OUT 2
3 k.n.
-1-.J
8
-=-
9
-12 V
Figure 18. 0169 Used as a Voltage-to-Frequency Converter
H-BRIDGE SWITCH APPLICATION
+5 V
V+
IN~J~ o--1~--f--lI--lI""""o.....;::=-+,---,
t----~-ItL
Figure 19. Driver for MOSPOWER H-Swltch
8-22
0469
...... Siliconix
incorporated
~
Quad High-Current
Power Driver
FEATURES
BENEFITS
APPLICATIONS
• High Current Drive
(Up to 1A)
• Efficient Drive For Large
MOSPOWER FETs
• H-Bridge Drives
• Single Power-Supply
• Low Standby Power
Consumption
• Motor Drives
• TTLICMOS Compatible
Inputs
• Complementary
Switching
• Easily Interfaced
DESCRIPTION
The D469 is a quad high current driver designed to
interface low current logic to power MOSFETs in
motor
controls
and
other
power control
applications. This 4-channel power driver can
source or sink up to 1 A at 2% duty cycles or
±250 mA continuously.
is built on the Siliconix PolyMOS'" process. An
epitaxial layer prevents latchup.
To achieve high current driving capability, the D469
The D469 is available in 14-pin side braze and
plastic packages. Performance grades include the
military, A suffix (-55 to 125°C), industrial, B suffix
(-25 to 85°C), and commercial, C suffix (0 to
70°C) temperature ranges. For further information
please refer to application note AN88-1.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
Dual-In-Llne Package
v+
GND
IN,oiN, o--+--a
IN 2 0--+---;
iN2o--+--a
Top View
Order Numbers:
Side Braze: D469AP, D469AP/883.
D469BP
Plastic: D469CJ
Truth Table
IN X
INx
0
0
1
1
0
1
0
1
OUTx
IN 3 0--+-----1
iN 3 o--+--a
IN 4 0--+---;
iN 4 o---+---{]
GND
GND
VDD
GND
8-23
0469
..... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
P Package
Ambient Temperature Under
Bias . . . . . . • • . . • . . • . . . . . • . . • . . . . . . . . . . .• -55 to 125·C
Storage Temperature ...•.......••...... -65 to 150·C
Voltage on Any Pin with Respect
to Ground ............••......•... , -0.3 to Voo +0.3 V
J Package
Operating Temperature .. -55 to 125·C ...... 0 to 70·C
Junction Temperature. . . . . • • . .. 1S0·C ....••••• 12S·C
Power Dissipation ......•.•.. 82S mW ....... 62S mW
Supply Voltage, Voo .....•••.•.•.••....... -0.3 to 14 V
Continuous Output Current .•....••....•...... ±2S0 mA
Peak Output Current (Pulsed at 1 ms,
2% Duty Cycle) ................•.....•.......
±1 A
Derating ............••.•. 11 mW/·C ... 6.2S mW/·C
. . . . . . . . • . • • • . . . . . . . . .. above 7S·C .... above 2S·C
8JA
•••••••••••••••••••••••• 91·C/W ...... 160·C/W
.........•...•..•...... (No Airflow) .... (No Airflow)
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo = 12 V
PARAMETER
LIMITS
1=25·C
2=12S,8S·C
3=-55,-40·C
TEMP
SYMBOL
TYP c
A,B,C
SUFFIX
MIN b MAXb
UNIT
INPUT
Input Voltage HIGH
V INH
1,2,3
Input Voltage LOW
VINL
1,2,3
Input Current with
Input Voltage HIGH
IINH
VIN =Voo
1,2
0.001
Input Current with
Input Voltage LOW
IINL
VIN = 0 V
1, 2
0.001
-10
lOUT = -100 mA
One Output at a Time
1,2,3
11.1
10
lOUT = -10 mA
1,2,3
11.9
11.8
3
V
0.8
10
)lA
OUTPUT
Output Voltage HIGH
VOUTH
V
Output Voltage LOW
VOUTL
lOUT = 100 mA
One Output at a Time
1,2,3
0.6
2
lOUT = 10 mA
1,2,3
0.07
0.2
Output Source Current
108+
Vo = 0 V, 2% Duty Cycle
1
1
Output Sink Current
108-
Vo = 12 V, 2% Duty Cycle
1
-1
A
8-24
~
~
0469
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo = 12 V
SYMBOL
PARAMETER
LIMITS
1=25·C
2=125,85° C
3=_55,_40 0 C
TEMP
TYP c
1
2
60
1
25
A,B,C
SUFFIX
MINb MAXb
UNIT
DYNAMIC
100
150
Propagation Delay
tpx
Rise Time
tr
Fall Time
tf
1
30
C 1n
1
5
1
2
3
7.5
10
1,2
3
10
20
30
1
2
7
20
20
Input Capacitance
C L = 500 pF
ns
pF
SUPPLY
INx = iNx = 0 V, Voo= 12.6 V
Supply Current
100
IN x =
iN x
= 3 V, Voo = 12.6 V
f = 100 kHz, Voo = 12.6 V
C L = 500 pF
One Output at a Time
mA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
..
AC TESTING CONDITIONS
----------3V
iN x
(IN x = H)
'--,--- -----ov
OUTX---~~
----------3V
'--,-,..-- - - - - - o V
OUTX---':":":::.JT·
8-25
0469
. . , . Siliconix
incorporated
~
DIE TOPOGRAPHY
..
136 mils
14
14
2
~I
Pad Function
No.
13
INl
~~
3
4
2
INl
3
IN2
4
IN2
5
IN3
6
7
IN3
GND
8
IN4
9
10
IN4
OUT 4
119 mils
11
OUT 3
12
OUT 2
13
OUT 1
14
V+
20X
CSACA
8 Resistors
28 P-channel enhancement MOSFETs
44 N-channel enhancement MOSFETs
8 NPN Bipolar Transistors
TYPICAL CHARACTERISTICS
Supply Current vs. Supply Voltage
Input Logic Threshold vs. Supply Voltage
3
4
-
Nb LoAD
TA = 25°C
3
2~-+--~--~-+--+~~~,--~
........ ~,,'
ONE CHANNEL ON..,... V
(V IN1 =VDD)
IDD
(mA) 2
1----+---t----I7'~
/
V
/
2
4
6
8
10
12
V DD - SUPPLY VOLTAGE ,V)
8-26
' / l / I""
V"
. / "/
ALL CHANNELS OFF
~ V" ( V IN (ALL) = 0 V)
./
14
o
o
2
4
6
8
10
12
VDD- SUPPLY VOLTAGE (V)
14
tI"F
~
0469
Siliconix
incorporated
TYPICAL CHARACTERISTICS (Cont'd)
Supply Current vs. Supply Voltage
10~~f-IN~=~10~0~k-H-Z~--~--~--~---'
VIN = 0 V, 5 V
C L = 5000 pF
T A = 25°C
8 ONE INPUT TOGGLED,
ALL OTHERS GROUNDED.
Supply Current vs Input Voltage
80~~~~~~~~~~~--~
~
_ Voo 12 V I_-I-_-I-_-+_-t
T A = 25°C
60 - NO LOAD
100
100
(rnA)
40~--+----r--~_;H-t---~---i
6~--+---+---+---~~+---1---~
2000 pF
I
1000 pF
(rnA)
4
500 pF
100 pF
20~--+----r--~_;~t---~---i
o
2
VIN - INPUT VOLTAGE (V)
2
3
10
8
100
(rnA)
6
fiN = 100 kHz
VIN = 0 V, 5 V
T A = 25°C
FOUR INPUTS (iN x)
TOGGLED
SIMULT ANEOIJ.§,
ALL OTHERS IN x
GROUNDED.
FOUR OUTPUTS
PARALLELED
35
C L = 5000 pF
30
25
Voo= 12 V
T A = 25°C
VIN = 0 V, 5 V
ONE INPUT TOGGLED,
ALL OTHERS
GROUNDED.
20
100
(rnA)
15
4
10
-"...."
f = 400 kHz
2
I
I
I,
VI
"..
5 r--200 kHz
V
-
20 kHz
2
4
6
8
10
12
V oo - SUPPLY VOLTAGE (V)
10
14
Supply Current vs. Capacitive Load
50
100
40
(rnA) 30
20
10
10
Voo= 12 V
TA = 25°C
V IN = 0 V, 5 V
FOUR INPUTS IN x TOGGLED
SIMULTANEOUS, ALL
IN x GROUNDED
FOUR OUTPUTS
PARALLELED.
I
f = 400 kHz
200 kHz
20kHzr-----~------_+----_;
100
1000
10000
C - CAPACITIVE LOAD (pF)
14
Supply Current vs. Capacitive Load
Supply Current vs. Supply Voltage
12
8
10
12
4
6
V oo - SUPPLY VOLTAGE (V)
100
1000
C - CAPACITIVE LOAD (pF)
..
10000
Supply Current vs. Switching Frequency
35
30
25
100
C L = 500 pF
T A = 25°C
VIN = 0 V, 5 V
ONE INPUT TOGGLED,
ALL OTHERS
GROUNDED.
20
I
h
(rnA)
15
1/1
10
5
'6o=12V
./
~~
10
10V
8V
5V
~/J
--'l
100
1000
f - SWITCHING FREQUENCY (kHz)
8-27
0469
.... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS (Cont'd)
Supply Current
70
VB.
Switching Frequency
=
=
=
CL
500 pF
TA
25°C
VIN
0 V,S V
FOUR INPUTS (IN )
TOGGLED SIMUL1?.NEOUS,
ALL OTHER (IN x )
GROUNDED.
FOUR OUTPUTS
PARALLELED
60
50
100
(rnA) 40
J
30
VDD
=12 V
10 V
8V
/h
20
~..;
10
5V
~~
1000
10
100
f - SWITCHING FREQUENCY (kHz)
OUTPUT STRUCTURE
INPUT STRUCTURE
SWITCHING TIME TEST CIRCUIT
C = 10JlF 110.01 ~F
CHIP CAPACITORS
VDD
C~
INPUT
~500 pF
INx = Voo TO TEST iN x '
TEST REPEATED FOR ALL INPUTS.
BURN·IN DIAGRAM
GNO
0--4--_-1
L-=:==~~
PIN DESCRIPTION
SYMBOL
8-28
DESCRIPTION
INX
Non-Inverting Logic Control Input
INx
Inverting Logic Control Input
GND
Ground
OUT
Buffered Output
VDD
Positive Supply Voltage
...... Siliconix
incorporated
~
0470
Low-Power - High-Speed
Octal CMOS Driver with Serial Interface
FEATURES
BENEFITS
APPLICATIONS
• up to ± 22 Volt Output
Range
• Devices Can Be Chained
For System Expansion
• Automotive and Avionics
Systems
• Low Propagation Delays
« 200 ns)
• Any combination of B
Outputs
• Master Reset To All
Drivers
• ATE
• Serial Data Acquisition
and Process control
• TTL and CMOS Compatible
• Independent Output
Voltages
• ESDS Protection >
• Simple Interfacing
• Reduced Parts Count
• Increased Versatility
• Communication Systems
• Display Drivers
±4000 V
DESCRIPTION
The D470 is a CMOS driver array configured as
eight power buffers for use in serial input
applications. By combining high output current
capability (I OPEAK = 200 mAl and low propagation
delays (tPR < 150 ns) the D470 is ideally suited for
driving discrete devices in automotive, ATE, and
process control applications.
This device loads data serially into the input shift
register with each clock pulse. The state of the shift
register can be latched via LOAD (LD) at any point
into an address register which holds the logic bits to
control each individual driver. A RS pin resets all
the latches which in turn reset the power buffers. A
serial data output terminal DOUT allows chaining of
power drivers for larger matrix systems. The output
voltages may be made independent or equal to V+
and V- for added flexibility.
The 0470 is built on Siliconix' high voltage silicon
gate process to achieve high voltage ratings and
high output current capability. An epitaxial layer
prevents latchup.
Packaging for the 0470 consists of the 2B-pin
CerDIP, plastic DIP, and PLCC. Performance grades
available are military, A suffix (-55 to 125°C) and
industrial, D suffix (-40 to B5°C) .
PIN CONFIGURATION
PLCC Package
Dual-In-Llne Package
o
U v
_ G V
TPNLRNP
44CDSDS
As
GND
2
Vps
OUTS
411 311 211 11128112711261
,/
OUT3
v P2-3
OUT2
V Nl -2
Top View
9
OUT 1 1
v p1
v-
1:21113111411151116111711181
DOUT
VDCDVN
+ 1 L 0 - C
Order Numbers:
CerDIP: D470AK, D470AK/883
Plastic: D470DJ
Preliminary
N K U
T
Order Number: D470DN
B-29
..
H
0470
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
v+
GND
v-
VP1
L..1_
DIN
OUT1
VNl-2
L~_
OUT2
VP2-3
CLK
LJ!._
OUTs
VN3-4
L4
OUT4
VP4
SHIFT
REGISTER
Vps
L.§.._
OUTs
VN5-6
L.§.._
OUTs
V pS _7
L1.._
OUT7
VN7-8
DOUT
L.§.._
OUT8
VP8
RS
LD
TRUTH TABLE
RS
1
1
CLK"
f
f
OUTPUT STRUCTURE
DIN
D1
Dn
0
0
Dn-1
1
1
Dn-1
1
~
X
D1
D (NO CHANGE)
0
X
X
0
0
LD"
f
f
~
D1
L1
OUT 1
0
1
VNl-2
1
0
VP1
D1
II
(NO CHANGE)
" ClK and lD are level sensitive Inputs.
8-30
Preliminary
0470
WY'Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
V+ to V- ....••.•..•...........•••.....•...... 44 V
GND to V- . . . . . . . . • • . . • . . • • • . . . . . . . . . . • • . . . . .• 25 V
Digital Inputs, VPX_y, V NX_y 1 ... (V-) -2 V to (V+) + 2 V
or 30 mA, whichever occurs first
Continuous Current (Any Terminal) .........••.•. 30 mA
Current, 106 (Pulsed 1 ms 10% duty cycle) ..... 200 mA
Storage Temperature
Power
28-Pln
28-Pln
28-Pln
Dissipation (Package)·
CerDIP·· ......••.••.........•...... 1200 mW
Plastic··· .........•...•..•..••..•..•• 625 mW
PLCC .. •• ..••••...................•. 450 mW
All leads welded or soldered to PC Board.
Derate 16 mW/oC above 75°C.
... Derate 8.3 mW/oC above 75°C.
.... Derate 6 mW/oC above 75°C.
(A Suffix) ......... -65 to 150°C
(D Suffix) ........ -65 to 125°C
Operating Temperature (A Suffix) ......•.• -55 to 125°C
(D Suffix) ......•.•• -40 to 85°C
Signals exceeding V+ or V- will be clamped by Internal
diodes. Limit forward diode current to maximum current
ratings.
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
0
2=125,85°C
V+ = 15 V, V- = -15 V
SUFFIX
SUFFIX
3=-55,-40°C
-55
to
125°C
-40
to
85°C
GND = 0 V
PARAMETER
SYMBOL
VIN = 2.4 V, 0.8 Vd
TEMP TYpo MIN' MA>f MINb MAXb UNIT
DRIVER
Output Voltage HIGH
Output Voltage LOW
Output Source Current
10 = -5 rnA
1,3
2
14.6
14.4
14.6
14.4
10=-30mA
1,3
2
11
11
10 = 5 mA
1,3
2
-14.6
-14.4
-14.6
-14.4
10=30mA
1,3
2
-11
-11
-9
-9
Vo = -15 V Pulsed
1,3
2
200
150
200
150
Vo = 0 V Pulsed
1,3
2
175
125
175
125
Vo = 15 V Pulsed
1,3
2
-125
-100
-125
-100
Vo = 0 V Pulsed
1,3
2
-125
-100
-125
-100
VOH
9
9
V
..
VOL
106+
mA
Output Sink Current
106-
LOGIC INPUT
Input Current with
VIN LOW
IlL
VIN Under Test = 0.8 V
All Other = 2.4 V
1,2
-1
1
-1
1
Input Current with
VIN HIGH
IIH
VIN Under Test = 2.4 V
All Other = 0.8 V
1,2
-1
1
-1
1
J.lA
Preliminary
8-31
0470
tIY" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
2=125,85°C
V+ = 15 V, V- = -15 V
SUFFIX
3=-55, -40 ° C -55 to 125°C
GND = 0 V
PARAMETER
SYMBOL.
VIN = 2.4 V, O.B Vd
TEMP TYp c
D
SUFFIX
-40 to 85°C
MINb MAX' MINb MAXb UNIT
LOGIC OUTPUT
Output Voltage lOW (DoUT)
VOL
lo=3.2mA
1,2
Output Voltage HIGH (DOUT)
V OH
lo=-BOJ.lA
1,2
2.4
2.4
tLOGIC
(CJN ' lD, ClK, RS)
1
2
BO
150
80
150
0.4
0.4
V
DYNAMIC
Pulse Width for logic
Inputs
Propagation Delay (Rise)
tpR
VIN = lD, CL = 500 pF
50% of VIN to 50% of Vo
1
2
150
200
250
200
200
250
200
250
Propagation Delay (Fall)
tpF
1
2
Data Setup Time
tow
1,2
Positive Supply Current
1+
1,2
Negative Supply
Current
1-
Ground Current
IGNO
50
ns
50
SUPPL.Y
V+ = 16.5 V, V- = -16.5 V
VIN = 0 or 5 V
100
100
1,2
-1
-1
1,2
-100
-100
J.lA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. V IN = Input voltage to perform proper function.
INPUT TIMING REQUIRMENTS
\'--q, = for ClK and lD Inputs of the same frequency
The recommended phase delay of lD from ClK
Is 1/2 t LOGIC to t LOGIC
t LOGIC(MIN) : BO ns at 25°C
150 ns at 125°C
8-32
~~ ~ ~1~ ~
GND =
aV
Preliminary
..-F'
0470
Siliconix
incorporated
~
INPUT TIMING REQUIRMENTS (Cent'd)
SHIFT REGISTER SETUP
DAT_A
________
~)(~______~--------I
/I
As
I
---'lr----
I
I'
I
I
CLK__________I'-.'____
CLK
DATA TO CLK t 30 ns at 25°C
50 ns at 125°0
Rst TO CLK t 30 ns at 25°C
50 ns at 125°0
SHIFT REGISTER HOLD
¥'----
DATA
I,
II
J
-----'I
DATA FROM CLKt 30 ns at 25°C
50 ns at 125°C
ADDRESS REGISTER SETUP
CLK
1
RS
\
I,.,----------,~I
LD
yr---
I _ _ _ _-JI
_____
~I,======:::::j"'I---
---------f.----
LD ___________
1
As
CLK t TO LOt 30 ns at 25°C
50 ns at 125°0
'TO LOt 30 ns at 25°C
50 ns at 125°0
ADDRESS REGISTER ENABLE
CLK
1
1;--\
--------~ I,
LD
-------'
,I
1'----
CLK t TO LD' 100 ns at 25°C
150 ns at 125°C
RS
\
I,
LD
'1
I /
RS' TO LD' 100 ns at 25°C
150 ns at 125°0
V+ = +15 V, V- = - 15 V, GND = 0 V
INPUTS ARE 0 V TO 3 V
Preliminary
8-33
0470
.... Siliconix
incorporated
~
TIMING DIAGRAM
u
-1
R8
DIN
eLK
LD
81
82
L -______~~_ _ _ _ _ __
83
84
85
------~------~-------~~----
_____-'r-
86
87
________
~rJ~
_________
~
8a
Do~ -----------------~
81- 8 a and Do~ are expected output with the drain connected high.
The sources require pull-downs of 1 k.o. .
PIN DESCRIPTION
SYMBOL
lD
NC
VPX-V
OUTX
V NX-V
V+
DIN
ClK
DOUT
VGND
RS
8-34
DESCRIPTION
logic lOAD DATA Input. When HIGH it loads the contents of the shift register into the octal
latch.
No Connection
Positive power supply voltage common to buffers X and Y.
Buffer X output
Negative Power Supply Voltage, common to buffers X and Y.
Positive Supply Voltage
Serial Data Input. TTL Compatible for V+ = +4.5 V up to +22 V.
Clock. The d-type master-slave flip-flops that make the shift register are updated during the
positive transitions of the clock.
Serial Data Output. TTL compatible output levels. Can be used to chain several devices.
Negative Supply Voltage.
Digital Ground.
RESET. When LOW this input clears the contents of the shift register to an all zeroes state.
Preliminary
L144
Low-Power Triple
Operational Amplifier
tI'1P'" Siliconix
JI;II incorporated
•
Three Amplifiers in One
Package
o Low Power Consumption
•
•
•
APPLICATIONS
BENEFITS
FEATURES
Programmable Supply
Current
Operates From
±1.5 to ±15 V
Drives Large Capacitive
Loads « 1000 pF)
•
Reduces Board Space and
Parts Count
o Reduces System Power
Supply Requirements
•
Easily Tailored to
Optimize Circuit Performance
•
Eliminates Additional
Supply Voltages
•
Increases System Stability
•
Instrumentation Amplifiers
•
Battery-Powered Systems
•
Remote Data Sensing
•
Voltage Comparators
•
Active Filters
DESCRIPTION
The Siliconix L144 is a low cost triple operational
amplifier designed for general purpose applications
where low power is a primary consideration.
Features include operation with supply voltages as
low as ±1.5 VDC, programmable supply current
(with single resistor), and internal compensation to
ensure stability under all conditions of resistive
feedback. The L144 will drive capacitive loads to
1000 pF, and the output stages are short-circuit
protected.
The programmable supply current of the L144
allows the user to minimize the effects of the
speed-power trade-offs associated with all op
amps. The three amplifier architecture is excellent
for instrumentation-amplifier configurations. The
unity-gain stable internal compensation allows
simplified operation in buffer, active filter, and gain
stage applications.
The L 144 is built in a standard bipolar process,
allowing low-drift operation over a wide range of
power supply voltages and temperatures. Package
options include the popular 14-pin side braze and
plastic DIP, and the flat pack. The L144 device is
specified for operation over the military, A suffix
(-55 to 125°C), industrial, B suffix (-25 to 85°C),
and the commercial, C suffix (0 to 70°C)
temperature ranges.
For more information on the L144, please refer to
Siliconix Application Note AN73-S.
PIN CONFIGURATION
Flat Package
Dual-ln-Une Package
+Vs
-IN 1
+INl
OUT2
-Vs
OUT3
NO
Top View
Order Numbers: L144AL 1883
Top View
Order Numbers:
Side Braze: L144AP, L144AP/883
L144BP, L 144BP/883
Plastic: L144CJ
8-35
".,. Siliconix
incorporated
L144
~
FUNCTIONAL BLOCK DIAGRAM
+Vs
-IN
RS
SOO.!}.
+INo---I--I---'
.:::rr----+--o SET CURRENT
RS
1 k.D.
IL
-Vs
1 k.Il
_ _Rg
__
____ _
aUT
ABSOLUTE MAXIMUM RATINGS
Supply voltage •..•.•. . . . . . . . . . . . . . . . . . . . . . . • .. ± 18 V
Lead Temperature (Soldering 60 s) .............. 300°C
Differential Input Voltage . . . . . • . . . . . . . . . . . . . • • .. ±30 V
Power DiSSipation (Package)"""
Flat Package ....•.........•....•..•••...•.. 750 mW
14-Pln Ceramic DIP. . . . . . . . . . . . . . • . . . . • . . . • .. 825 mW
Plastic DIP ...........•..............•.•..•. 470 mW
Input Voltage" (A. B Suffix) ..•..•••..•.••..••.. ±18 V
(C Suffix) ....................... ±15 V
Output Short Circuit Duration"" .••............ Indefinite
Operating Temperature (A Suffix) .••.••... -55 to 125°C
(B Suffix) .•........ -25 to 85°C
(C Suffix) ..•........ 0 to 70°C
Storage Temperature (A and B Suffix) ..... -65 to 150°C
(C Suffix) .......•••. -65 to 125°C
For supply voltages < ±18 V, maximum Input voltage Is
equal to the supply voltage.
Continuous short circuit Is allowed for case temperatures to +125°C and ambient temperature to +70°C.
" "" All leads welded or soldered to P. C. board. Derate
10 mW/oC for the flat package, 11 mW/oC for the
14-pln DIP above +75°C and 6.3 mW/oC above 25°C
for the plastic DIP.
ELECTRICAL CHARACTERISTICS a, e
Test Conditions d
1=25°C
Unless OtherwIse SpecIfIed:
2=125,85,70°C
3=-SS,-2S,O °c
Vs = ± 15V, RL= 50 k.n
PARAMETER
SYMBOL
RSET= 3 M.n (Pin 1 to 14)
Vas
RsS SOk.n
1
2,3
1
TCvas
RsSSOk.n
1
3.3
LIMITS
A/B
SUFFIX
C
SUFFIX
TEMP TYpe MINb MA>f MINb MAXb UNIT
INPUT
Input Offset Voltage
Offset Voltage Tempco
8-36
5
6
10
mV
)lV/oC
L144
...... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a, e
Test Conditions d
1=25·C
Unless Otherwise Specified:
2=125,85,70·C
3=-55,-25,0 ·C
Vs = ±15V, RL=50k.n
PARAMETER
SYMBOL
RSET = 3 M.n (Pin 1 to 14)
LIMITS
AlB
SUFFIX
C
SUFFIX
TEMP TYpe MINb MAX' MINb MAXb UNIT
INPUT (Cont'd)
50
70
los
1
2
ISlAS
1,2
-100
-200
Output Voltage Swing
V OUT
1
±14
-10
Output Voltage Swing
V OUT
1
±0.5
1
1.5
AVOL
1,2,3
30
Slew Rate
SR
1
0.4
V/)J.s
Unity Gain
Bandwidth
GBW
1
0.6
MHz
f=100Hz
1
-100
VIN = ±12 V
1
90
80
70
1
90
80
80
dB
350
400
)J.A
Input Offset Current
nA
Input Bias Current
-250
OUTPUT
10
-10
10
V
Output Short
Circuit Current
Iso
Vs= ±1.5 V, RSET = 120 k.n
RL = O.n
15
15
mA
DYNAMIC
DC Open Loop
Voltage Gain
Crosstalk
3
1
V/mV
dB
Common Mode
Rejection Ratio
CMRR
SUPPI.Y
Power Supply
Rejection Ratio
PSRR
Supply Current
Is
Unity Gain, VIN = 0 V
On All Amplifiers
1
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
o. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. I SET Is adJustable. See typical characteristics.
e. All dc parameters are 100% tested at 25·C. Lots are sample-tested for ac parameters and high and low temperature
limits to assure conformance with specifications.
8-37
WY'Siliconix
incorporated
L144
~
TYPICAL CHARACTERSITICS
Gain-Bandwidth Product vs.
Supply Current
Open Loop Gain VS. Frequency
100
1.4
r--
1.2
80
r-...
~
1.0
60
Av
(dB)
r-...
40
GBW
(MHz)
"
20
10
100
10 3
10 4
V
0.4
r-...
0.2
1
~
0.6
o
-20
V
0.8
10 6
10 5
,..,.
~
10.uA
100.uA
f - FREQUENCY (Hz)
10mA
1 mA
I SUPPLY
DC Open Loop Gain vs. Temperature
Slew Rate vs. Supply Current
105
10~~.
~:tl.5--+15 V
95
Av
(dB)
SR
(V/.us)
O.lmJJIIMIII
75
65
1000
-60
-20
10
R~·=Ylif
60
~i'-
85
/
V
vlUI
~
Av
(dB)
75
/
6
:t15 V
:tl0 V
+ 5V
RSET
(M.o. )
4
65
2
55
0
/
I SUPPLY
1 mA
V
",
--
I/:,.V ..... /
~
100.uA
140
:t5
:tl0
l{olA-
"
/" ~~.uA
~
'I'
10.uA
100
Supply Current vs. Set
Resistor and Supply Voltage
8
95
8-38
20
T - TEMPERATURE (DC)
DC Open Loop Gain vs. Supply Current
105
-
85
55
100
I SUPPLY (.uA)
- ...
/"
-
......r
.". "",.",
250.uA
-s;tA-
:t15
SUPPLY VOLTAGE (V)
I
:t18
L144
...... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS
Input Bias Current vs. Supply Current
Supply Current vs. Temperature
1000
320
280
Vs = ±1.5 V
Ie
(nA)
A~
100
240
~I'"
Is
(~A)
200
160
120
1.;';'-
Vs = ±15 V
80
,&'fI'
~
40
10
100
0
1000
-60
-20
20
60
100
TEMPERATURE (OC)
I SUPPLY (~A)
Voltage Follower
Small Signal Pulse Rsaponse
0.8
Phase Response vs. Frequency
225
r'\.
rlil
0.6
Vo
(V)
0.4
180
Phase
135
(%)
0.2
~
90
n
0
-0.2
140
o
10
20
40
t - TIME U!.s)
45
60
80
o
1
10
100
10 3
10 4
10 5
10 6
FREQUENCY (Hz)
8-39
Siliconix
incorporated
H
L144
APPLICATIONS
Active Filter
Instrumentation Amplifier
_
VOUT
......_...r>
~1.6VP-P
VREF
750
~~~~--~V0~---o
k.n
PO =7.5mW
SAND
PASS
(GNOo,
VOSNULL)
AV= 1 +
fo=1kHz
0=26
Po = 135Jlw
~R~
Ho= 26
VOS(TYP) RTI = 0.45 mV
Q
A
max .....--o-VOUT
VIN
VOUT
1/3
L144
1/3
L144
+VOUT
PO =7.5 mW
VOUT
""YiN=
Po
VOUT= "LOW" WHEN:
VHIGH> VIN > V LOW
DIRECT CMOS OUTPUT
= 290JlW
R2+ R 1
--R-1-
V- = -10 V
500 Hz Tcne Detector
Bandpass Filter
32
LET
THEN
VOUT
0, 10 , C
THEN
C =C3=C4
1 < K< 10
R 7= RS for convenience
k.n
R - __
0_S- 21f; oC
RS= R6= K RS
R1=~
Ho
R1= __R_S_ _
Ho+ 1
02- - K - -
8-40
Schmitt Trigger
k.n
R6320
GIVEN
Detector
?ofor~~~~lIk
~~o~hosen
component value
VHIGH =
V,ef R s+ 14 RA
RA+RS
convenience,
IN THIS CIRCUIT
Ho= 10
fo=SOOHz
0=25
VLOW= V,ef R S- 14R A
RA+RS
L161
Micropower Quad
Comparator
tr'F Siliconix
~
incorporated
FEATURES
APPLICATIONS
BENEFITS
• Programmable Supply
Current
• Allows User to Program
Speed/Power Trade-Off
• Ultra-Low Power
Consumption
• Minimizes System Power
Requirements
• Four Comparators on
Single Chip
• Reduces Board Space
• Smart Munitions
• Battery-Operated
Systems
• Miniaturized Systems
• CMOS Logic Systems
• Simplifies Logic
Interface
• Direct CMOS Logic
Compatibility
ct
• Input Sensing Near Ground
• Level Detectors
• Window Comparators
Simplifies SingleSupply Operation
• Oscillators and Ramp
Generators
DESCRIPTION
The L161 is a monolithic quad comparator featuring
control of both DC and AC parameters with a single
power-supply current setting resistor. Operation at
very low supply current levels with power dissipation
typically in the microwatt region makes the L 161
ideally suited
for
battery
operation.
The
programmable supply current feature allows the
user to optimize the speed-power trade-off to the
specific application, truly minimizing system power
dissipation. The L 161 is fabricated in a standard
bipolar process, resulting in a wide range of
operating supply voltages and currents, and
allowing low-drift operation over the entire military
temperature range. The L161 is available in the
16-pin plastic DIP. Performance grades include a
military, A suffix (-55 to 125°C), industrial, B suffix
(-25 to 85°C), and commercial, C suffix (0 to
70°C) operation.
For more information on the L161, please refer to
Siliconix Application Note AN76-7 .
PIN CONFIGURATION
Dual-ln-L1ne Package
Flat Package
+IN1~1!V+
-IN 1
+IN2
- IN 2
- IN 3
+IN 3
- IN 4
~4
2
3
4
5
1
14
1
1
11
1
ISET
NO
OUT1
OUT2
OUT3
OUT4
~
+IN1
v+
-IN 1
ISET
+IN2
NO
OUT1
OUT2
OUT3
OUT4
Top View
Order Numbers: L161ALl883
v-
Order Numbers:
Side Braze: L161AP. L161BP
Plastic: L161CJ
8-41
..
~ Siliconix
,.1;11 incorporated
L161
SCHEMATIC DIAGRAM (ONE COMPARATOR)
(ONE COMPARATOR)
OUTPUT
r--------,
r------------------------------4----------1-~~B~IA~S~N~E=nN~O~R~K---+-OV+
(COMMON TO
ALL FOUR
COMPARATORS)
~------~_oISET
(-)
(+)O-~~------~----------~------~--~
L--------+--------~~
______+_------------~~----~--+_----~--~----+_OvL ________ J
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................... ±16 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .. ±30 V
Input Voltage" ................................ ±16 V
Output Short Circuit Duration"" ............... Indefinite
Operating Temperature
(A Suffix) ......................... -55 to +125°C
(B Suffix) .......................... -25 to +65°C
(C Suffix) ............................ 0 to +70°C
Storage Temperature
(A and B Suffix) .................... -65 to 150°C
(C Suffix) .......................... -65 to 125°C
Power Dissipation (Package)"""
Flat Package ........................... 750 mW
16-pln DIP (Side braze) .................. 900 mW
16-pln Plastic DIP ....................... 470 mW
For supply voltages < ±16 V, maximum Input voltage Is
equal to the supply voltage.
Continuous short circuit current Is allowed for case
temperature to +125°C and ambient temperature to
+70°C.
""" All leads welded or soldered to PC board. Derate
10 mW/oC above 75°C for the flat package, 12 mW/oC
above 75°C for the side braze DIP and 6.3 mW/oC
above 25°C for the plastic DIP.
LOW POWER ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1_25°C
A
B,C
Unless Otherwise Specified:
2=125,65,70°C
SUFFIX
SUFFIX
Vs = ±3 V, ISET= 10jJ.A
3=-25 _550°C
RL = 10 M.n
SYMBOL
TEMP TYpo MII'f MA>f MIN b MA>f UNIT
INPUT
Input Offset Voltage
VOS
1
2,3
1
1
3
5
6
Input Offset Current
los
1
1
20
25
1
20
100
200
mV
nA
Input Bias Current
8-42
IBT
L161
Siliconix
incorporated
LOW POWER ELECTRICAL CHARACTERISTICS a
Test Conditions
1_25°C
Unless Otherwise Specified:
2=125,85,70°C
Vs = ±3 V, ISET= 10.uA
3=-25 _550°C
PARAMETER
SYMBOL
RL = 10 M.n.
TEMP
TYp c
1,2
3
30
30
1
-2.95
LIMITS
A
SUFFIX
B,C
SUFFIX
MIrJ' MAX' MINb MAX'
UNIT
OUTPUT
DC Open Loop
Voltage Gain
AVOL
Low Output Voltage d
VOL
RL = 20 k.n.
10
5
20
10
-2.6
VlmV
-2.6
V
High Output
Voltaged
V OH
RL = 200 k.n.
1
2.9
2.5
2.5
CMR
Positive Limit
Negative Limit
1
1.3
-3.0
V
Response Time
t
100 mV Overdrive
C L = 10 pF
1
5
.us
Common Mode
Rejection Ratio
CMRR
VIN = CMR
1
90
75
75
dB
1
80
65
65
dB
1
2,3
210
210
DYNAMIC
Common Mode Range
SUPPLY
Power Supply
Rejection Ratio
Supply Current e
PSRR
Is
All Outputs Low
RL = 00
325
325
325
350
.uA
HIGH POWER ELECTRICAL CAHRACTERISTICS a
PARAMETER
LIMITS
Test Conditions d
1=25°C
A
Unless Otherwise Specified:
2=125,85,70°C
SUFFIX
Vs = ± 15 V,I SET = 100.uA
3=-25 -550°C
RL = 2 M.n.
SYMBOL
TEMP TYp c MIrJ' MAX'
B,C
SUFFIX
MIN b MAX'
UNIT
INPUT
Input Offset Voltage
Vas
1
2,3
1.5
1.5
3
6
6
Input Offset Current
los
1
5
60
90
1ST
1
2,3
100
100
400
500
800
mV
nA
Input Bias Current
8-43
L161
..... Siliconix
incorporated
~
HIGH POWER ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
B,C
A
Unless Otherwise Specified:
2=125,85,70°C
SUFFIX
SUFFIX
Vs = t15 V, I SET = 100 ~A 3=-25 _550°C
RL= 2 M.o.
TEMP TYpe MIN b MAX' MINbMAX t UNIT
SYMBOL
OUTPUT
DC Open Loop
Voltage Gain
AVOL
1,2
3
100
100
50
25
30
15
V/mV
Low Output Voltaged
VOL
RL = 20 k.o.
1
-14.9
High Output Voltaged
VOH
RL = 200 k.o.
1
14.9
Positive Limit
1
13
Negative Limit
1
-15
100 mV Overdrive
CL = 10 pF
1
1
1
90
75
75
dB
1
80
65
65
dB
1
2,3
2.1
2.1
-14.6
-14.6
V
14.5
14.5
DYNAMIC
Common Mode Range
CMR
Response Time
t
Common Mode
Rejection Ratio
CMRR
V
VIN
= CMR
~s
SUPPLY
Power Supply
Rejection Ratio
PSRR
Supply CurrentS
Is
All Outputs Low
RL = co
3.75
4.0
3.75
4.0
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteBd nor subject to production testing.
d. The output current drive of the L 161 Is non-symmetrical. This facilitates the wlre-ORlng of two comparator outputs.
e. The output pull-down current Is typically 75-100 times the pull-up current.
Set current ( I SET) and supply current ( I SUPPLY) can be determined by the following formulas:
I SET = [ (Y+) - (2VBE) - (V-) [
RSET
I SUPPLY = 21 X I SET
8-44
mA
l161
..... Siliconix
incorporated
~
DIE TOPOGRAPHY
Pad
No.
IBAJA
2
3
4
5
6
7
8
9
10
11
12
13
15
16
20X
20 PNP Transistors
11 NPN Transistors
1 Epl FET
Function
+IN,
-IN,
+IN2
-IN2
- IN 3
+IN 3
-IN4
+IN4
V- (substrate)
OUT 4
OUT 3
OUT 2
OUT,
ISET
V+
TYPICAL CHARACTERSITICS
Input Bias Current vs. Supply Current
Supply Current vs. Temperature
1k
100
Vs = ±15 V
800
~
''')3\/
10
600
Ie
(nA)
Is
(JJ.A) 400
I.
200
0.1
~
(l
1
10
100
lK
o
-40
10K
ISUPPLY - SUPPLY CURRENT U1A)
R SET vs. V SUPPLY for
Various I SUPPLIES
10
--
= 10JJ.A ......
IfuPf'L
6
RSET 4
(M.o. )
2
0.8
0.4
0
,
V
I'
i...o"
"'"
L
~
V
//
,/ /.. ~±2
±5
i...o"
....
i.-
,.
NEGATIVE
160 I-- TRANSITION
1..0"
--,.
140
(v7~;)
I
I
...1-1'"'"
1 rnA
40
20
,/
Vs - SUPPLY VOLTAGE (V)
±15
o
o
i/
V
./ POSITIVE
/
/
60
V
,."
...... 10'
/
100
80
"10dJJ.A
±10
..., i-"""
/
120
2JOJA
10
V
180
~
120
Slew Rate vs. Supply Current
1/ 100JJ.A
.vi"
...,
80
200
/1
50JJ.A
8
40
T - TEMPERATURE (OC)
/
TRANSITION
9
8
7
6
5
SR+
(V/JJ.s)
4
I- 3
Vs = ±1J V I
VIN = ±100 mVp
2
RL = 10 M.o.
l0
iL =l
1 1- 1
r
200
400
600
800
Is - SUPPLY CURRENT U1A)
o
1000
NOTE: The output current drive of each comparator In the L 161 Is non-symmetrical. The pull-up current Is typically
2[V+ - 1 - (V-)/RSETI and the pull-down current capability Is typically from 75 to 150 times the pull-up current.
8-45
L161
...... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS (Cont'd)
Voltage Gain VS. Supply Curent
Voltage Gain VS. Temperature
120
220
Vs =± 15 V
Is = 1 mA
'"
V s =±15V
100
180
.JI' ....
80
Av
140
(V/mV)
100
60
,.,.. ,.,..
-
I...... .......
--
Av
(V/mV)
...... 1-
60
/
""
Vs = ±3 V
40
20
20
40
80
120
o
T - TEMPERATURE (OC)
-40
100
10
Rise Time vs. Supply Current
with One CMOS Load
Transfer Characteristic
+15
+10
1000
! I I I .I• .I
-VSUPPLY = ±15 V
_TA = 25°C
",.
+5
VOUT
(V)
0
/
-5
"
/
I SUPPLY 100
(JiA)
;/
-10
I
-15
-200
-100
0
100
10
200
10
1
Response Time vs. Input Overdrive
Negative Transition
1000
200
VIN 100
(mV) 0
-100
""
Vs - ±15 V, Is = 1 mA
100 mV
20 mV
~
5mV
:
15
10
I SUPPLY
(JiA)
\.
VOUT 5
(V)
0
"'\.
'\...
RL = 10 M.n._
.......... CL=10pF
-5
r\
1
100
RISE TIME 10% TO 90% (JJ.s)
Fall Time vs. Supply Current
with One CMOS Load
10
"
IL
VIN - DIFFERENTIAL (JiV)
100
10 k
1k
Is - SUPPLY CURRENT !J1A)
10
FALL TIME 90% TO 10% (JJ.s)
-10 -100(mv
100
-15
o
t
20
jV
-M
V -
2
3
TIME (JJ.s)
NOTE: The output current drive of each comparator In the L 161 Is non-symmetrical. The pull-up current Is typically'
2[(V+) -1 -(V-Ii RSETI and the pull-down current capability Is typically from 75 to 150 times the pull-up current.
8-46
L161
..... Siliconix
.1,;11 incorporated
TYPICAL CHARACTERSITICS (Cont'd)
Response Time vs. Input Overdrive
Positive Transition
200
I
It
= ±15 V
100 trVS
Is = 1 mA
-5 mV
o
20 mv
100 mV 20 mV -100 mY::
-100::
VIN 15
(mV) 10
/'/
J/
//
5
o
/V
5
//
-10
-15
5mV
RL = 10 M.(l_
C L = 10 pF
~
o
2
3
4
5
6
TIME Uls)
NOTE: The output current drive of each comparator in the L161 is non-symmetrical. The pull-up current is typically
2[(V+) -1 -(V-)/RSETI and the pull-down current capability is typically from 75 to 150 times the pull-up current.
APPLICATIONS
The L 161 is a monolithic quad micropower
comparator with an external control for varying its
AC and DC characteristics. The variation of a
single programming resistor will simultaneously
alter parameters such as supply current, input bias
current, slew rate, output drive capability, and gain.
By making this resistor large, operation at very
small supply current levels and power dissipations
-- typically in the low microwatt region -- is
possible. The L161 is therefore ideal for systems
requIring minimum
power drain,
such as
battery-powered instrumentation, aerospace systems, CMOS designs, and remote security
systems.
The L161
is fabricated using standard bipolar
processing. The circuit (Figure 1) is composed of
five majcr blocks -- four comparators and a
common bias network. 01 - 06 and 01 form a
darlington differential amplifier with double-to-single
ended conversion. 06 is a dual current source
whose outputs are exactly twice the current flowing
through 08.
The collector current of 08 is a
function of the current supplied externally to 09 010, which in turn is known as the set current or
I SET. This set current is established by a resistor
connected between the I SET terminal and a voltage
source, most commonly the positive supply. 011
prevents excessive current from flowing through 09
and 010 in the event the I SET terminal is shorted to
the positive supply; it has no effect on circuit
operation under normal conditions.
r--------,
r------------------------------------------r~~B~IA~S~C~IR~C~U=IT~--~-O+V
(COMMON TO
ALL FOUR
AMPLIFIERS)
...-:----....1--0
ISET
+IN
-IN o---1r----------i-----------r--------i---'
~----4----~~---~--------~--~-~--~~~--+--o_v
'- _ _ _ _ _ _ _ _ .J
Figure 1. Schematic of One Channel of the L161 Plus the Common Bias Network
8-47
-
Il'Y" Siliconix
L161
~
incorporated
APPLICATIONS (Cont'd)
SETTING THE SET CURRENT
INPUT BIAS CURRENT
The set current can be expressed as:
ISET
=
Input bias current is a function of the betas of input
«V+) - (2 VBE) - (V-»
RSET
(1 )
where V+ is the voltage to which the control resistor
is connected, V- is the negative supply voltage,
VBE is the base emitter drop of 09 or 010 (about
0.7 V), and R SET is the value of the external control
resistor or set resistor. Equation 1 is simply a
derivative of Ohms Law. There is also an analytical
This is difficult to
devices 01 - 02 and I SET.
express analytically because f3 varies greatly with
both processing and collector current; however it is
roughly proportional to the set current and can
easily be determined experimentally (see Figure 2).
Figure 2. Input Bias Current vs. Supply
Current
100
relationship between I SET and the total supply
current:
""'±3:V
= (I SET
(current sourced by 06 to 08)
16
+2 ISET (current sourced to the differential
amplifier by 06)
(nA)
II
1=
t-
+2 ISET (current sourced to the comparator
output by 06»
X 4 (the total number of comparators)
0.1
+1 SET (current sourced through 011, 010,
and 09 to V-)
= (I SET
= 21
10
100
1k
SUPPLY CURRENT
10 k
UJ,A)
+ 2 I SET + 2 I SET ) X 4 + I SET
ISET
the high output drive current, (IOH), which allows
wire-ORing the outputs. 10H is simply the current
sourced by 06:
=2
X ISET
(3)
10L is found by multiplying the current sourced by
the
collector
of
06
by
the
gain
07:
(4)
The beta of 07 is about 75-150.
8-48
V
1
I SUPPLY -
The output current pulldown capability (101.) of the
L 161 is about 2 orders of magnitude greater than
10H
j
10
(2)
I SUPPLY
E
GAIN
Gain varies logarithmically with changes in supply
voltage and linearly with changes in set current.
Primary causes are the decrease in output
impedance of 07 with decreasing supply voltage
and an increase in transistor betas with increasing
set current. Other AC parameters such as slew
rate and transition time are also effected by set
current; however, current dependent parameters
such as beta and chip capacitances make
mathematical
expressions
imprecise.
These
relationships have been determined empirically and
are presented in Figure 3 and 4.
L161
..... Siliconix
incorporated
~
APPLICATIONS (Cent'd)
Figure 3. Slew Rate vs. Supply Current
,
200
160
140
120
/
(V~~~ )100
60
,
20
o
I'
/
..... V
POSITIVE
TRANSITION
/
V
I SUPPLY -
RISE TIME
"
7
5 SR+
(V/JJ,s)
~
4
ISUPPLY 100
(JJ,A)
;"
3
/
200
9
6
6
I'
/
I
40
V
,,/
......
/
60
o
-'"
/
1000
V
NEGATIVE
TRANSITION
160
Figure 4. Rise and Fall Times vs. Supply
Current With One CMOS Load
10
Vs
VIN
RL
CL
400
= ±15 V
= ±100 mVp
= 10 M.O.
= 10 ~F
600
2
o
600
1000
SUPPLY CURRENT U1A)
The designer's ability to program the key
parameters of the L161 enables him to program
just enough supply current to meet his design
objectives.
This coupled with the L161 's
performance using only microwatts of power makes
"~
FALL TIME
lWlli
10
1
~
10
100
RISE TIME 10% TO 90% (JJ,s)
it ideal for any micropower or battery-powered
system, as well as a replacement for existing higher
power comparators.
The following applications
illustrate the flexibility and unique capabilities of the
L161.
..
RSET
10 M.D.
Po
= 30
JJ,W
V-
Zero Crossing Detector
Voltage Level Detector
8-49
L161
Siliconix
incorporated
H
APPLICATIONS (Cent'd)
V+
+5 V
I SUPPLY = BOOjl.A
RSET
UPPER LIMIT
Rl
100 k.rl
VOUT
OJ
2
T·
'v
OUT
Enable Input
LOWER LIMIT
For V = ±5 V
P D =60jl.W
CMOS Line Receiver
Double Ended limit Detector
+15 V
+5 V
RSET
100 k.o.
RS
IS k.o.
VIN
2
Cl
470 pF
RSET
1,2 M.o.
16
13
VOUT
.I
-=-1
R2
Rl
-12 V@SmA
A Regulated DC to DC Converter
8-50
220 k.o.
2.2 k.o.
CCOMP
lo.001.1lF
The L 161 as an X100 Operational Amplifier
H
L161
Siliconix
incorporated
APPLICATIONS (Cont'd)
+9 V
ISUPPLY
= 10JlA
+10 V
RSET
16
R1
100 k.o.
300 k.o.
13
R2
300 k.o.
R3
100 k.o.
A Low Battery Indicator
I SUPPLY
Square Wave Oscillator
= 350 JlA
250 k.o.
R3
50 k.o.
10VlLJl
CLOCK 0 V
II
cj>1
CLOCK
10 V,...,
,...,
OV.J
L-....J L
cj>2
A Versatile 2 cj> Pulse Generator
8-51
trJr' Siliconix
Si7250
Bubble Memory
Power Driver
~
FEATURES
BENEFITS
APPLICATIONS
• TIL Compatible Inputs
• Very Low Standby Power
• Bubble Memory
Coil Pre-Driver
• Transition Time < 25 ns
with 5pO pF Load
• Easy To Interface
incorporated
• Protection of Bubble
Memories
• Power Fail Reset
• Single Voltage Power
Supply
DESCRIPTION
The Si7250 is a low power coil predriver for direct
use with the Siliconix VQ7254 quad MOSPOWER
array to drive magnetic bubble memory coils. Its
high speed (tTRANS < 25 ns with 500 pF load), TIL
compatible inputs and complementary outputs
make this device ideal for driving high gate
capacitance MOSPOWER devices.
The Si7250 is built on the Siliconix proprietary
PolyMOS process, allowing superior current
handling capabilities. A power fail reset pin protects
memory contents in the event of power failure.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAlVI
X+ IN
CS
Packaging options include the 16-pin CerDIP for
commercial, C suffix (0 to 70°C) temperature
operation.
X+ OUT
Voo
CS
X+ OUT
RESET
X+ OUT
X+ IN
X+ OUT
X- IN
X- OUT
Y+ IN
X- OUT
X- OUT
Y-IN
Y+OUT
Y+ OUT
Y- OUT
Y+ OUT
GND
Y- OUT
X-IN
RESET
x:ou;=
Y+ OUT
Y+IN
V-OUT
Top View
Order Number: SI7250CK
V-OUT
Y-IN
8-52
Not Recommended for New Designs
Si7250
W'fl" Siliconix
~
incorporated
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under
Bias • . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .. -20 to 80·C
Output Current .......................•..... 250 rnA
................•.. (One Output @ 100% Duty Cycle)
Storage Temperature ................... -65 to 150·C
Maximum Operating Junction Temperature 150·C
9JC = 25·C/W
9JA = 75·C/W (No Airflow)
Voltage On Any Pin with
Respect to Ground ................ -0.5 to Voo + 0.5 V
Supply Voltage, Voo ..................... -0.5 to +14 V
Operating Temperature ...........•......... 0 to 70·C
Storage Temperature ...••....•..••...... -65 to 150·C
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo = 12 V ±10%
PARAMETER
LIMITS
1=25 ·C
2=70·C
3=0·C
TEMP
SYMBOL
C
SUFFIX
o to 70°C
TYP C MIN b MAXb
UNIT
INPUT
Input Current
!lIN I
Low Level
Input Voltage
High Level
Input Voltage
VI = 0.8 V
1,2,3
10
VIL
1,2,3
0.8
VIH
1,2,3
JJ.A
V
2.2
OUTPUT
V OL1
IOL= 100 rnA
1,2,3
1.45
2
V OL2
IOL=10mA
1,2,3
0.1
0.2
V OH1
IOH = -100 rnA
1,2,3
Voo
-1.4
Voo
-2
Voo
-0.1
Voo
-0.2
Output Low Voltage
V
Output High Voltage
Output Sink Current
VOH2
IOH = -10 rnA
1,2,3
IOL
VOL = 2 V, 30% Duty Cycle
1,2,3
100
lIoHI
VOH =Voo - 2 V, 30% Duty Cycle
1,2,3
100
rnA
Output Source Current
DYNAMIC
Propagation Delay from
X+ IN, X- IN, Y+ IN, Y- IN
tp
Propagation Delay from
CS or RESET
tp
Rise Time (10% to 90%)
tr
500 pF Load
Not Recommended for New Designs
1,2,3
55
100
1,2,3
90
150
1,2,3
25
45
ns
8-53
II
Si7250
.... Siliconix
.,1;11 incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Voo= ±10%
PARAMETER
SYMBOL
LIMITS
1=25 ·C
2=70·C
3=0·C
C
SUFFIX
o to 70 c C
MIN b MAXb
TEMP
TYP c
1,2,3
25
45
10
20
UNIT
DYNAMIC (Cont'd)
Fall Time (90% to 10%)
tj
500 pF Load
ns
Skew Between an
Output and Its Complement
ts
1,2,3
Input Capacitance
C 1n
1,2,3
10
pF
SUPPLY
Supply Current
1000
_ Chip Deslected
CS =VIH, Voo= 12.6 V
1,2,3
1001
1= 100 kHz, Voo= 12.6 V
Output Unloaded
1,2,3
75
1002
1= 200 kHz, Voo= 12.6 V
Output Unloaded
1,2,3
90
1
4,5
mA
NOTES:
a. ReIer to PROCESS OPTION FLOWCHART lor addltlonallnlormatlon.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are lor DESIGN AID ONLY, not guaranteed nor subject to production testing.
AC TEST CONDITIONS
INPUT
-
OUTPUT
~
------f--tPJ:
------------
_______________________
-
-
8-54
-~:~~
-
0V
50%
--.,J-t
OUTPUT
-
s
~
...5_0_%_ __
Not Recommended for New Designs
Si7250
...... Siliconix
,.1;11 incorporated
PIN DESCRIPTION
X- OUT, X- OUT, X+ OUT, X+ OUT (Pins 12-15)
High current outputs and their complements for
driving the gates of the VQ7254 QUAD MOSPOWER
FETs which in turn drive the X coils of the bubble
memory.
CS (Pin 1)
Chip select is active low.
When high, chip is
deselected and I DD is significantly reduced. Chip
Select is most commonly used for system
expansion.
Y+ IN, Y- IN (Pins 5, 6)
Active low inputs from controller which turn on the
high current Y outputs.
RESET (Pin 2)
Active low input from RESET .OUT of the controller
results in removal of power from the chip so that
bubble memory is protected in the event of power
supply failure.
Y- OUT, Y+ OUT, Y+ OUT, Y- OUT (Pins 9-11
and 7)
High current outputs and their complements for
driving the gates of the VQ7254 QUAD MOSPOWER
FETs which in turn drive the Y coils of the bubble
memory.
X+ IN, X- IN (Pins 3, 4)
Active low inputs from controller which turn ON the
high current X outputs.
TRUTH TABLE
INPUT PINS
1
CS
2
R
1
X
X
3
4
x:;:- X-
OUTPUT PINS
5
6
V;
7
y-
y-
X
X
0
1
0
1
9
10
11
12
V;
X-
0
1
0
1
Y- y+
13
-X-
14
15
X+
X+
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
1
1
1
0
1
0
0
1
0
1
0
1
8 INPUT STATES DECODED
The 8 remaining Input states are not decoded resulting In a reset output condition.
This Is to prevent the Inadvertent shorting of any power drivers directly across the
supplies In a standard bubble memory configuration.
0
1
0
0
I 0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1·
0
1
0
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
Not Recommended for New Designs
8-55
Si7652
Chopper-Stabilized
Operational Amplifier
~
~
Siliconix
incorporated
FEATURES
BENEFITS
APPLICATIONS
• Ultra-Low Input Offset
Voltage (Vos < 5 JLV)
• Improved System Accuracy
• Precision Amplifiers
• Reduces Loading of High Z
Sources
• High Impedance Transducer
Amplifiers
• Eliminates Trims for
Offset and Drift
• Remote High Resolution
Systems
• Improves Input Resolution
• Integrating AID
Preamplifiers
• Low Input Bias Current
(Ie < 30 pAl
• Low Drift
(TCyos< 50 pV/°C)
• Low Noise
(en < 0.2 JL V p_p )
• Reduces Linearity Errors
in High Gain Designs
• Low Level Signal Sensing
• High Open-Loop Gain
(AYOL > 120 dB)
DESCRIPTION
The Si7652 is a chopper-stabilized operational
amplifier designed to achieve virtually zero change
in voltage offset (Vos) with both temperature and
time. By freeing the design from costly
potentiometer adjustments, overall circuit reliability
and performance are greatly enhanced.
There are two versions of the Si7652. The 8-lead
versions rely on the internal 400 Hz oscillator to run
the chopper, while the 14-lead versions allow the
user to connect an external oscillator for
specialized applications where synchronization may
be desirable. The 14-lead version also allows for
the connection of an output voltage clamp circuit to
minimize overload recovery time.
With a low maximum input offset voltage of 5 ~V
and a low drift of 50 pV/oC (maximum) .. the Si7652
is ideal for high-resolution signal conditioning. Its
low drift over time and temperature benefits remote
systems where recalibration is difficult and/or
costly.
Built on the Siliconix proprietary PolyMOS T'
process, 8i7652 also features low bias and offset
current errors, and has been designed to minimize
the charge injection errors normally associated with
chopper designs.
Package options include the 8-lead metal can and
MINIDIP, and the 14-lead plastic and ceramic DIP.
Operation is specified over the industrial, D suffix
(-40 to 85°C) temperature range.
For more information on the 8i7652, please refer to
Siliconix Application Note AN87-4.
PIN CONFIGURATION
C EXTB 1
INT/EXT
CEXTA 2
EXT/CLKIN
NC(GUARD)
3
NC(GUARD)
6
INT/C~KOUT
C E X T A O S C EXTB
-INPUT 2
7 v+
+INPUT 3
6 OUTPUT
OUTPUT
9
Order Numbers:
CerDIP:
Plastic:
8-56
v- 4
OUTPUT CLAMP
Sl7652DK
Sl7652DJ
Order Number:
Sl7652DA
5
Order Number:
SI7652DH
CRETN
Si7652
. . . . Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
PERIODS
OSCILLATOR
:HASES
~
1(1)1
10(
+
(2)
(4)
I (3) I
+ +
I (1) I
~
~I
A
+IN o----
(deg)
I
10
100
1k
90
....
'"
"-
I'\.
10 k 100 k 1 M
FREQUENCY (Hz)
180
~
~
Si7652
Siliconix
incorporated
TYPICAL CHARACTERSITICS
Input Offset Voltage Change
Supply Voltage
I1Vos
(jJ.V)
8
3
6
2
4
-k:
~~
l?
" ~
0
-1
~
6
4
L...,...oo-"
10
12
14
VS.
~
---
VOUT = V-
0
......
-20
-30
-40
-50
-60
8
i---"'"
I'
2
10
(mA)
-2
-3
Maximum Output Current
Supply Voltage
VB.
16
i'-.....
---
VOUT= V+
I
2
TOTAL SUPPLY VOLTAGE V+ TO V- (V)
I
4
6
8
10
12
14
16
TOTAL SUPPLY VOLTAGE V+ TO V- (V)
Supply Current
Supply Current vs. Supply Voltage
VS.
Temperature
2.5
2.0
~
1.5
Is
(mA)
1.0
0.5
/
y ...
/
3
V
Is
(mA)
V
--
2
~
-1
0
4
-55
6
8
10
12
14
16
TOTAL SUPPLY VOLTAGE V+ TO V- (V)
Input Offset Voltage vs. Chopping
Frequency
DC to 10 Hz P-P Noise Voltage
Chopping Frequency
12
6
10
5
125
VS.
4
8
Vos
(jJ.V)
-25
0
25
50
75 100
AMBIENT TEMPERATURE T A(OC)
en
(jJ.V)
6
4
3
~
2
\,
2
o
0
10
100
1k
CHOPPING FREQUENCY (Hz)
10 k
10
-
100
1k
CHOPPING FREQUENCY (Hz)
10 k
8-61
..
Si7652
trY" Siliconix
~
incorporated
TYPICAL CHARACTERSITICS
Common Mode Rejection Ratio
vs. Frequency
Power Supply Rejection Ratio (PSRR)
vs. Frequency
0
-10
-20
-30
-40
-50
PSRR
(dB)
-60
-70
-80
-90
-100
-110
-120
/
/
/'
PSRR-
/
V/,
I'
~ V pSRR+ _
~
A
I'"
.Ai"
~
1
10
100
1k
FREQUENCY (Hz)
10 k
100 k
130
120
110
100
90
80
CMRR 70
(dB)
60
50
40
30
20
10
0
0.1
1'00.
10
100
1k
FREQUENCY (Hz)
TEST CIRCUIT
OUTPUT
O.lJLF EACH
Figure 1.
DETAILED DESCRIPTION
Circuit Operation
A block diagram of the chopper stabilized amplifier
is shown in Figure 2. The main amplifier is
connected directly to the output. The nulling
amplifier, which is controlled by the oscillator/clock
circuit, alternates between nulling itself and the
main amplifier. The nulling potentials are stored in
the external nulling capacitors. The nulling circuitry
8-62
works independent of signal level, and functions
over the entire power supply and common mode
range.
Charge injection at the
by careful design
Feedthrough injection,
chopping spikes in the
input terminals is minimized
in the input switches.
which is the main cause of
output, is also minimized.
Si7652
IrJP" Siliconix
.£1/1 incorporated
DETAILED DESCRIPTION (Cent'd)
PERIODS
OSCILLATOR
:HASES
+IN
0-_,---------1 .....
~
1(1)1
1<1
t
(2)
I (3) I
t
t
(4)
I (1) I
'I
~I
A
-IN o--t-~------__l
C
INT/EXT
CLKIN
CLK OUT
Figure 2. Functional Block Diagram
Output Clamp
Overload recovery can be a significant problem in
chopper stabilized designs. This is because the
time constant of the filter at the output of the nulling
amplifier can be measured in minutes. If the output
goes to either of the supply rails, the inputs are no
longer at "virtual ground". The nulling amplifier
sees the differential voltage at the input as an error
and tries to correct it, saturating the nulling circuit.
Therefore, it is appropriate to clamp the output of
the main amplifier to insure that there is a low
impedance current feedback path to the summing
(inverting) input of the amplifier before the output
reaches either supply rail. For best results, the
clamp resistance should be greater than 100 k!l.
Output clamping does reduce the output swing
slightly. Figure 3 shows the Si7652 in inverting and
noninverting clamped amplifier circuits.
INPUT>--'V\I\r-.......---t
0>--_
OUTPUT
(R 111 R2) ~ 100 k.n.
FOR FULL CLAMP EFFECT
Figure 3(a). Inverting Amplifier with Clamp
INPUT>-----I
NOTE:Rlll R21NDICATES
THE PARALLEL
COMBINATION
OFRI AND R2
C>-~--
OUTPUT
R3 + (RIll R2) ~ 100 k.n.
FOR FULL CLAMP EFFECT
Figure 3(b). Non-Inverting Amplifier with Clamp
8-63
Si7652
W7' Siliconix
~
incorporated
DETAILED DESCRIPTION (Cont'd)
Clock
The nomimal operating frequency of the internal
clock/oscillator is 400 Hz. Although the clock is not
adjustable on the 8-pin versions of the Si7652. the
14-pin versions allow selection of either internal or
external clocking. The INT/ EXT pin should be left
floating for use with the internal clock, or tied to Vif an external clock Signal is applied to the EXT ClK
IN pin. The duty cycle of the external clock is not
important at lower frequencies because the internal
oscillator circuitry provides a 50% switching duty
cycle. When operating at frequencies above 500
Hz. a 50% to 80% positive duty cycle is preferred
because the nulling capacitors are charged only
when EXT ClK IN is high. The external clock can
swing between either V+ and GND or V+ and Vsince the logiC threshold is approximately 2.5 V
below V+.
To avoid capacitor imbalance during an overload. a
strobe signal may be applied to EXT ClK IN. Neither
capacitor will be charged if the strobe signal is low
during the time that the overload is applied.
Component Selection
The only external components required by the
Si7652 are two nulling capacitors. The correct value
for the capacitors when using the internal 400 Hz
oscillator can be anywhere between 0.1 and 1 /J.F.
Capacitors toward the 1 /J.F value will allow
minimum clock noise in broadband applications.
while capacitors toward the 0.1 /J.F value will
provide lower offset in limited bandwidth
applications. When using an external clock, the
capacitors should be scaled proportionally to the
relationship of the chopping frequency to the nulling
time constant.
low grade capacitors such as ceramic are
satisfactory for most applications. However, film
capacitors are preferred. low dielectric absorption
capacitors such as polypropylene will yield the
lowest settling at turn-on. Ceramic capacitors may
take as long as several seconds to settle to within
1/J.V .
APPLICATIONS
Output Loading
The Si7652 is similar to a transconductance
amplifier in that the open loop gain is proportional
to load resistance. This phenomenon becomes
important when the load impedance is lower than
the typical 18 kO output impedance of the device.
For example, the open loop gain will be 17 dB lower
with a 1 kO load than with a 10 kO load. This has
little importance if the amplifier is used only in DC
applications. since the DC gain is typically better
than 120 dB even with a 1 kO load. However. the
best wideband frequency response will occur with a
load resistor of 10 kO or higher. The response will
be 20 dB per decade from 0.1 Hz to 500 kHz. with
phase shifts of less than 2 degrees in the transition
region where the main amplifier takes over from the
null amplifier.
Thermo-Electric Effects
Thermo-electric effects developed in thermocouple
junctions of dissimilar materials ultimately limit
precision DC measurements. Unless all junctions
are at the same temperature. thermoelectric
voltage from 0.1 to as high as 20-30 Jl.V /oC will be
generated. In order to realize the extremely low
8-64
offset voltages that the Si7652 can provide it is
essential to take special precautions to avoid
temperature gradients. All components should be
shielded from air movement. especially that caused
by power dissipating elements. Power supply
voltages and power dissipation shoul~ be kept to a
minimum. and low thermo-electric coefficient
connections should be used where possible.
Separation from surrounding heat dissipating
elements is advised. and high impedance loads are
preferable.
Latch-up
A parasitic four-layer SCR structure is a
characteristic of all junction-isolated CMOS
devices. SCR action can occur under certain
circumstances. drawing excessive supply current
and possibly destroying the device. To avoid this
condition. no voltages greater than 0.3 V beyond
the supply rails should be applied to any pin. The
power supplies should be established either at the
same time as or before any input signals are
applied. If this is not possible. the input current
must be limited to less than 1 mA to avoid latch-up
during the fault condition.
IrF' 8i1iconix
~
Si7652
incorporated
APPLICATIONS (Cont'd)
Input Guarding
To fully realize the low leakage inputs of the 8i7652,
special care must be taken in layout and
preparation of the printed circuit board. All
contamination must be cleaned away with alcohol
or TCE and compressed air, and the assembled
board should be sealed to prevent recontamination
in the future.
Even proper cleaning cannot stop all leakages since
the inputs of the amplifier are adjacent to terminals
that carry supply potentials. This can be reduced by
placing a guard ring around the input terminals. The
14-pin package has the pins on either side of the
inputs unconnected to ease the layout of the guard.
An 8-pin metal can should be laid out using a 10-pin
socket pattern. The two extra pins are situated one
on each side of the inputs to facilitate guarding
(see Figure 4 (a». The guard ring should be
connected to a low-impedance point that is roughly
the same voltage as the inputs. Leakages from the
adjacent pins are absorbed by the guard. Figure
4(b) gives typical guarding connections.
INPUT o--'V\I\r-,-----'\/VIv----,
C>-~--O OUTPUT
INVERTING AMP
C>~>----O OUTPUT
INPUT
w
G--e---1
USE R3 TO COMPENSATE FOR LARGE
SOURCE RESISTANCES,
OR FOR
CLAMP OPERATION (SEE FIGURE 3)
FOLLOWER
External
.1"
Output_S
C>~~--o OUTPUT
.!!.l..!!.z..
NOTE: R
1+
R
2
SHOULD BE LOW
IMPEDANCE FOR
OPTIMUM GUARDING
NON-INVERTING AMPLIFIER
Figure 4 (b). Typical Guarding Connections
Bottom View
Board layout for Input guarding with TO-99 package.
Figure 4 (a). Board layout for Input guarding
with TO-99 package
Pin Compatibility
The 8-pin versions of the 8i7652 have been laid out
to correspond with the pin-out of industry standard
8-pin devices. The only difference is the connection
of the nulling capacitors to pins 1 and 8, normally
used for offset nulling on other op amps.
OP-05 and OP-07 op amp circuits can also be
converted to the 8i7652. This is done by replacing
the offset-null potentiometer between pins 1, 8,
and V+ by two capacitors from those pins to V-.
For LM 108 substitution, the compensation capacitor
is replaced by the external nulling capacitors.
Typical Applications
The 8i7652 will find use wherever improved offset
and bias current are required. In basic inverting
(Figure 5) and noninverting (Figure 6) configurations, the only limitations are the supply voltage
(±8 V max.) and the output drive capability (10 k
load min). These limitations can be bypassed by
the use of an output boost circuit as shown in
Figure 7.
8-65
Si7652
W'JP" Siliconix
~
incorporated
APPLICATIONS (Cont'd)
Because the combination of the two op amps form
a composite amplifier, the loop gain stability should
be checked carefully when the feedback network is
added.
+7.5 V
OUTPUT
INPUT>-"'\Af\r-......- - i
C>--"-_ OUTPUT
Figure 7. Using the 741 to Boost the Output
of the 517652
Figure 5. Inverting Amplifier
>-~--"'VOUT
100 k.n.
INPUT
(>~-
__ OUTPUT
Figure 6. Non-Inverting Amplifier
8-66
Figure 8. Nulling a High Speed Op-Amp
Si8901
..... 8i1iconix
incorporated
~
Ring Demodulator/
Balanced Mixer
FEATURES
BENEFITS
APPLICATIONS
• Low ON Resistance
• Usable to 250 MHz
• RF Mixers
• < 2% Device Matching
• Low Harmonic Distortion
• CATV Encoders and
Decoders
Error
• Wide Dynamic Range
• High Third Order
Intercept Point (+35 dB)
• Modulators
• Demodulators
• Phase Sensitive
Detectors
• Pagers
DESCRIPTION
The 8i8901 Ring Demodulator/Balanced Mixer offers
significant improvements for RF mixer "applications
where low third order harmonic distortion has been
a problem. Combining matching with very low
junction capacitance, « 3 pF), low ON resistance
(30 .0) and very high OFF resistance (> 109 .0), the
8i8901 accepts an RF and a local oscillator (LO)
input and provides a high fidelity IF output with
typical conversion loss of -8 dB at frequencies up
to 200 MHz. Available in an 8-pin TO-78 and 80-8
package, this device is specified over -25 to 85°C
temperature range.
PIN CONFIGURATION
FUNCTION BLOCK DIAGRAM
Malal Can
RFo!
SO Package
SUBSTRATE
",:~'o.o,
..
~
~
RFVcOl
SUBSTRATE
Top View
Top View
(Same plneul as Malal Can)
Order Number:
Sl8901A (TO-78)
Order Number:
Sl8901Y (SO-8)
IFl SUBSTRATE
PERFORMANCE COMPARISON
40
3rd Order Input
Intercept Point
(+dBM)
30
20
10
Sl 901
~
.. ~
5
t
~
~350 1,..00---
........:
~NG
.....
I
-----
10
15
20
25
30
Power Local Osc. (+dBm)
35
8-67
Si8901
Siliconix
incorporated
ABSOLUTE MAXIMUM RATINGS
VOS Drain to Source........ ... ................
15 V
VOB Drain to Substrate ..•....................• 22.5 V
VSB Source to Substrate ••.................. ,' .• 22.5 V
VGS Gate to Source ................... -22.5 V to 30 V
VGB Gate to Substrate ....•............. -0.3 V to 30 V
VGO Gate to Drain ...................• -22.5 V to 30 V
10 Drain Current ............•.........•..•... 50 mA
Operating ,Temperature ................... -25 to 85·C
Storage Temperature •................... -65 to 150·C
Power Dissipation (A Package)' ....... . . . . • . .. 640 mW
• Derate 5 mW/·C above 25·C·
ELECTRICAL CHARACTERISTICS a
TA
= 25°C
LIMITS
TEMP
TYP d
MIN b MAX b
SYMBOL
TEST CONDITIONS
Drain-Source
Breakdown Voltage
V(BR)OS
V GS =VSB = -5 V
Is=10nA
Source-Drain
Breakdown Voltage
V(BR)SO
VGO =VOB = -5 V
lo=10nA
15
Drain-Substrate
Breakdown Voltage
V(BR)OB
Source Open
VGB=OV,1 0 =10nA
22.5
Source-Substrate
Breakdown Voltage
V(BR)SB
Drain Open
VGB= 0 V, 10 = 10 nA
22.5
Threshold Voltage
VT
VOS =VGS =VT
Is=1J1A, VSB=OV
PARAMETER
UNIT
STATIC
Drain-Source
"ON" Resistance
Resistance Matching
25
1
VGS= 5 V
50
VGs= 10 V
30
VGs= 15 V
23
VGs ='20 V
19
VGs= 5 V
3
15
0.1
V
2.0
75 _
rOS(ON)
10=10mA
VSB = 0 V
.Il.rOS(ON)
.0.
7
DYNAMIC
L0 1 - L02 Capacitance
Cgg
Conversion Loss
Lc
Vos= 0 V, V BS = -5.5 V
V GS = 4 V
4.4
8
See Figure 1, P LO = +17 dBm
dB
Third Order Intercept c
IMD3
+35
Maximum Operation
Frequency
fMAX
250
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
'
c. Guaranteed by design, not subject to production test.
.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
8-68
pF
MHz
Si8901
trY' Siliconix
~
incorporated
APPLICATION HINTS
Schematic of the basic commutation-type HF double-balanced mixer using resonant-gate excitation.
Recommended reading is AN85-2 .. A Commutation Double-Balanced MOSFET Mixer of High Dynamic Range. "
Sl8901
SIGNAL
LOW-PASS
IMAGE TERMINATING
FILTER
(OPTIONAL)
T
6BOpF
- t
u
r---o-
vu
16BOPF
Figure 1.
ID(ma)
/I'
IIi
rt V
BV
II rL
II
10.00
/DIV
)v
ov
~
~~
1/
f
./
/.
I I
f
-50.00
-5.000
Figure 2.
..
16V J li 12V
50.00
'I I
I I I.
VDS
0
1.000/DIV
(V)
5.000
First and Third Quadrand I-E Characteristics Showing Effect of
Gate Voltage Leading to Large-Signal Overload Distortion
8-69
Display Drivers . .
..,. Siliconix
incorporated
~
TABLE OF CONTENTS
Introduction .•••...•...•.....•..••..•.....................•.•...........•.•..••...•. 9-1
DF412: 4-Digit LCD Decoder/Driver ..............................................••..... 9-2
Si9551/9552: Electroluminescent Row Drivers ...•.......•...•.•...•......•.....•.....•.. 9-12
8i9553/9554/9555/9556: Electroluminescent Column Drivers ......•.........•...•.•..••..•. 9-18
8i9560: Electroluminescent Symmetric Row Driver ....•............................•...•. 9-27
WY' 8i1iconix
~
incorporated
DISPLAY DRIVERS
INTRODUCTION
Ever since the invention of the CRT, designers have looked for smaller, more rugged alternatives. Today, many
flat panel technologies are gaining a significant share of the information display market with their compactness
(often less than .5 inches thick), their rugged, solid-state construction, and their low power consumption.
These display technologies are of particular interest to the military and portable computer markets, where the
above criteria are most important.
8i1iconix began its association with flat-panel displays by supplying 7-segment LCD drivers for use with digital
panel meters. More recently, 8i1iconix has used its high-voltage D/CM08 power IC process to supply display
drivers to Electroluminescent (EL) display manufacturers. Rowand column drivers for flat panel displays are
supplied for a wide range of applications from commercial desktop computers to military avionics control panels. 8i1iconix drivers are also specified in plasma, vacuum fluorescent, and LCD applications due to their high
performance characteristics.
The 8i9551 and 8i9552 are first-generation open-drain row drivers designed for driving the row electrodes of
electroluminescent graphics display panels. When combined with either the 8i9553 and 8i9554 (60 V), or the
8i9555 and 8i9556 (80 V) column drivers, they provide the interface between logic-level video control circuitry
and the high-voltage display panel.
The 8i9560 is a second-generation row driver designed to give higher performance and longer life to AC TFEL
(Thin Film EL) panels. It features a bi-directional shift register so that only one part is required for both sides of
the panel, and 225 V, 100 mA push-pull outputs to maximize brightness and minimize latent imaging.
The DF412 is a four digit liquid crystal display decoder/driver IC containing all of the necessary circuitry to
decode up to four digits of multiplexed BCD information and derive the ac signals required to directly drive a
four-digit seven-segment liquid crystal display.
9-1
DF412
...... Siliconix
incorporated
~
4-Digit LCD Decoder/Driver
FEATURES
BENEFITS
APPLICATIONS
• Decodes up to 4
7-segment BCD Digits
• Reduces Complexity
• Driving Liquid Crystal
Displays
• Interfaces with Most
Logic Families
• Eliminates DC Bias Levels
That Shorten Display
Lifetime
e On Chip Oscillator
e One External Component
• Low Power Consumption
(1.5 mW typ.)
• No Display Buffering
Required
• Digital Multimeters
• Flowmeter Digital
Readouts
e Portable Instruments
• Digit Blanking
DESCRIPTION
The DF412 4-digit LCD Decoder Driver is a CMOS
Monolithic device employing multiple~ed BCD to
LCD Decoding. A single DF412 contains all of the
circuitry needed to decode up to 4 digits of
multiplexed BCD information and derive the AC
signals needed to directly drive a 4-digit LCD
display. To eliminate leading zeroes, a BCD input
of 1111 blanks a digit.
segment. In this manner, the net DC potential
applied between segment and backplane is zero, a
necessary requirement for long display life.
Digital input levels are defined as input voltages
> 4 V being a logic" 1" and input voltages < 0.8 V
being a logiC "0" with VDD
BCD input data is decoded into 7-segment form
using an on board ROM. The 7-segment data is
then latched into the appropriate static latches via
the digit strobe inputs and control logic.
An internal oscillator, its frequency being controlled
by an external capacitor, develops a backplane
signal (BP) that is a square wave swinging between
ground (Vss) and the positive supply (VDD).
Segment drivers supply square waves of the same
frequency as the backplane but either in phase for
an OFF segment or out of phase for an ON
The pinout of the DF412 allows easy PC board
interface to dual-in-line LCDs as well as edge
connecting types of displays.
The DF412 is
available in the PLCC-44 package for industrial, D
suffix (-40 to 85°C) temperature range operation.
PIN CONFIGURATION
v
B f
0
g eON deb a S
P 1 1 1 0 ell lIe
6 5
4
3 2
1 4443 42 41 40
o
PLCC-44. J LEAD
PLASTIC PACKAGE
18 19 20 21 222324252627 28
9-2
= 5 V.
Order Number:
DF412DN
DF412
tI"!r 8iJiconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
t
t
SWITCH (7)
SWITCH (7)
I
Bo v
B1
B2
I
(LSB)
B3
,..,
EN
(MSB)
II
I
CONTROL LOGIC
D
FLlPFLOPS
,..,
~
~
STATIC
E~ATCH (7)
(7 SEG
DATA BUS)
BCD TO 7
SEGMENT ROM
~
I
STATIC
LATCH (7)
EN
I
II
J
I
I
ONE
I-SHOTS
EN
STATIC
LATCH (7)
I
SWITCH (7)
SWITCH (7)
~
Y
fc LOCK
I
I
INHIBIT
LOADING
OSC
RESET
-:- 512
I
I
1=I-
J
8.j - g4
iT
I
I
I
STATIC
EN
LATCH (7)
h
a3 - g3
~
I
I
B,.e
~
ABSOLUTE MAXIMUM RATINGS
V DD - Vss .............................. -0.3 V to 8 V
Storage Temperature .................... -65 to 125°C
Voltage on Any Pin ........... Vss -0.3 V to V DD +0.3 V
Power Dlsslpatlon* .......................... 450 mW
Current at Any Pin ............................ 10 mA
Operating Temperature (D suffix) .......... -40 to 85°C
* Device mounted with all leads welded or soldered to PC
board. Derate 6.3 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
V DD = 5 V
Vss= 0 V
Cosc = 200 pF
LIMITS
1 = 25°C
2 = 85°C
3 = _40°C
TEMP
TYpc
D
SUFFIX
-40 to 85°C
MIN b MAXb
UNIT
INPUT
Digital Input Leakage Current
I IN (DIGITS)
Oscillator Input Current
IIN(fCLK)
VIN =5
V
1
0.01
VIN =5
V
1
350
VIN = a v
1
-350
1
jJ.A
9-3
DF412
.... Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified:
VDD= 5 V
Vss= 0 V
Case = 200 pF
TEMP
BCD and DS Inputs
1
0.8
Clock Input
1
0.5
BCD and DS Inputs
1
4
Clock Input
1
4.5
I OL = 250 J.LA
1
0.3
IOL= 25J.LA
1
0.03
I OH = -250 J.LA
1
4.7
I OH = -25 J.LA
1
4.97
IOL= 5 mA
1
0.3
IOL= 0.5 mA
1
0.03
IOH=-5mA
1
4.7
IOH = -0.5 mA
1
4.97
1
1
1 = 25°C
2 = 85°C
3 = _40°C
0
SUFFIX
-40 to 8S oC
TYpo
MINb MAXb
UNIT
INPUT (Cont'd)
Digital Input
Logic LOW Voltage
V 1NL
V
Digital Input
Logic HIGH Voltage
V 1NH
OUTPUT
seftment Output
Vo tage In '0" State
seftment Output
Vo tage In "1" State
0.7
VOL
(Segment)
4.3
VOH
(Segment)
V
Backplane Output
Voltage In • 0" State
Backplane Output
Voltage In "1" State
0.7
VOL
(Backplane)
4.3
VOH
(Backplane)
DYNAMIC
Segment Output Rise Time
tr
(Segments)
C LOAD = 200 pF
Segment Output Fall Time
tf
(Segments)
1
1
Backplane Output Rise Time
tr
(Backplane)
1
0.8
1
0.8
1
30
J.LS
C LOAD = 3900 pF
Backplane Output Fall Time
Backplane Frequency
Minimum LCD
tf
(Backplane)
fBPI
Cose = 3800 pF
Hz
Backplane Frequency
Maximum LCD
9-4
fBP2
Case = 1000 pF
1
100
DF412
WY'Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
Voo= 5 V
Vss= 0 V
Case = 200 pF
100
See Figure 2
100
See Figure 3
LIMITS
1 = 25·C
2 = 85·C
3 = -40·C
SUFFIX
-40 to 85°C
TEMP TYpd
MINb MAXb
0
UNIT
SUPPLY
Supply Current
Digital Inputs Static
Current
Dlglta Inputs Dynamic
SUPPI~
Operating Supply Voltage d
1
140
400
)J.A
Voo
1
155
1
5
3.5
6
V
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for addlt1onallnformatlon.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Operation over the supply voltage range Is functionally tested. The dc and ac parametric testing Is performed only at
specific test conditions.
PIN FUNCTION DESCRIPTION
OSC (Oscillator) -- A capacitor connected between
the oscillator (OSC) and ground completes the
integral clock generator. The frequency of the
clock generator (f osc) is determined by the
capacitance value and the VDD voltage, as seen in
Figure 4. For driving LCDs with a 30 Hz to 100 Hz
backplane frequency range, the typical oscillator
5 V).
capacitor is 1000 pF to 3S00 pF (for VDD
The oscillator pin can also be driven with an
external clock whose output swings within 10% of
VDD andVss. This is useful when synchronization of
more than one DF412 is necessary, such as when
driving displays of more than 4 digits on a single
backplane.
=
BP (Backplane) -- The backplane of the liquid
crystal display is driven by this pin whose output is a
squarewave swinging between VDD and Vss. The
frequency of the backplane signal is fosc/512.
Most LCDs require backplane frequencies of
between 30 Hz and 100 Hz.
See Figure 4 for a
graph of oscillator capacitance vs. backplane
frequency.
Digit Strobes 01-04 and BCD Inputs B3, B2, B1 and
Bo -- Multiplexed BCD information is entered into
the DF412 by presenting the appropriate BCD code
to the inputs B3, B2, B1 and Bo and by pulsing the
appropriate digit strobe input D1, D2, D3, or D4with
positive true logic i.e. VINH > (O.S XVDD for logic 1,
VINL < O.S V for logic O. The minimum pulse width
of a digit strobe should be not less than one period
of the oscillator frequency. Information presented
at the BCD inputs (B3, B2, B" Bo) must be valid
during the digit strobe pulse.
See the timing
requirements in Figure 1.
The digit strobe inputs are shaped by the input logic
shown in Figure Sa. This logic causes a strobe
signal which is a signal clock period wide. The
active time of this data load strobe (shown in Figure
Sb) enables the BCD to 7-segment decoding ROM,
which brings the new 7-segment data to the output
latches. Delay time for data to get from BCD input
to the segment outputs in typically 2 I1s - 3 I1S.
The end of the data load strobe is triggered by the
second negative clock edge following the digit
strobe going high.
At this edge, the segment
outputs are latched, storing the 7-segment
information for this digit. This input structure is the
basis for the timing requirements of the DF412,
shown in Figure 1.
The digit strobe input structure can actually load
more than one digit at a time from the same BCD
input. The loading of multiple digits can save time
for microprocessor applications, such as for
zeroes, or blanks. However, all four digits cannot
be simultanenously loaded due to a special decode
of D1· D2· D3· D4 which causes a reset of the
9-5
..
DF412
..... Siliconix
incorporated
~
PIN FUNCTION DESCRIPTION (Cont'd)
backplane divider and inhibits loading of the BCD
data.
Unused Digit Strobes should be tied to
ground. to avoid them floating to a logic 1 condition
which could cause an inadvertent reset condition.
The reset condition stops the backplane square
wave. putting the DF412 drive in a steady voltage
state which would degrade the LCD when used in a
long term application.
When ganging more than one DF412 together. it is
necessary to synchronize the individual backplane
signals to insure proper segment-backplane signal
phase relationships. This is easily accomplished by
initially pulling all digit strobe inputs high and by
then driving the ganged DF412s with a common
oscillator. By comparing the individual backplane
TRUTH TABLE
B3 B2 B, Bo
0 0 0 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
signals of two DF412s with an exclusive OR gate
(see Figure 9) a continual checking of the
backplane phase relationships can be accomplished. Should the individual backplane signals
become out of phase an automatic reset will occur
and proper phase will once again be established.
Segment Outputs -- Segments are driven with the
DF412 segment outputs which generate square
waves that are either in phase with the backplane
for an OFF segment or out of phase with the
backplane for an ON segment. Output swings of
the drivers are between VDD and VSS. The CMOS
output drivers provide matched resistance to both
VDD and ground. eliminating any net DC voltage
component on the LCD thus maximizing display life.
TIMING WAVEFORMS AND DEFINITIONS
tosw
Display Character
0
2
3
I
'-I
5
5
7
B·
g
2
3
L
tOSL
OIGIT
STROBE INPUT
BCO
OATAINPUT
tOBl
~--~--- to~ --------~
Recommended Drive Conditions·
Min
Max
65 jJ.s··
tcp
Clock Period
19.5 jJ.s··
tosw
Digit Strobe Pulse Width
tcp+ ljJ.s
tOSL
Digit Strobe Low Time
2 tcp
tOBl
Digit Strobe to BCD Setup Time
-CD
to~
Digit Strobe to BCD Hold Time
L
'f
BLANK
2 tcp +2 jJ.s .
tcp -2 jJ.s
CD
• These minimum/maximum conditions Indicate the necessary conditions
to Insure operation. They are based on design structure (shown In
Figure 8a) with sufficient guardband to allow for propagation delay
changes. They are not tested nor guaranteed .
•• The min-max clock periods correspond to a 30 Hz-l00 Hz LCD
backplane frequency range.
Figure 1
9-6
~
~
DF412
Siliconix
incorporated
TEST CIRCUITS
+5V
1
11
ALL SEGMENT DRIVERS TIED
......___..+____...,THROUGH 200pF TO GND
+5 V
B3
B2
Bl
Bo
B3
B2
Bl
Q
111
I
.
VDD
8.1
DF412
CK
TOGGLE
FLIP-FLOP
a
DF412
.
8.11----.
Bo
01 0 2
ALL
SEGr-.:ENTS
OPEN
g·4
VDD
BP
-
200
pF
-
Figure 2.
BACKPLANE
OPEN
CKln
1=25 Hz
Static Supply Current Test Setup
Figure 3.
CK
Dynamic Supply Current Test Setup
INPUT-OUTPUT SCHEMATICS
INPUT
~
"'--...-'VV\r-
DATA IN 0------1
32
BIT
SIR
VSSo-----~~~----------------~
~----------------------------------_oDATAOUT
TRUTH TABLE
CONTROL INPUTS
FUNCTION
LOAD
ENABLE
CLOCK
ENABLE
STROBE
"'1z...
X
X
Not...
X
X
L
H
X
X
H
H
X
X
L
STROBE
INTERNAL
SHIFT REGISTER
QOUTPUTS
(Serial output Is always enabled)
Qn-Qn+ 1
No Change
Determined by ENABLE
and STROBE
All off
Determined by
CLOCK
Data out
All on
ABSOLUTE MAXIMUM RATINGS
VL •........•............•...........•...•.••. 18 V
Operating Temperature (A Suffix) ......... -55 to 125°C
(C Suffix) ............ 0 to 70°C
Input Voltage ..................... -0.3 V to V L +0.3 V
Q Output Voltage ............................. 225 V
Power Dissipation (Package) *
Plastic Quad Package** ...............•..... 1700 mW
Ceramic Quad Package*** .................. 2000 mW
Vss Terminal Current ........................... 1.5 A
Storage Temperature (A Suffix)
(C Suffix)
-65 to 150°C
-65 to 125°C
All leads welded or soldered to PC board.
Derate 13.6 mW 1°C above 25°C.
*** Derate 16 mW 1°C above 25°C.
9-13
tnP"
Si9551 19552
~
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
PARAMETER
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
A
C
2=125,70°C
SUFFIX
SUFFIX
VL = 12 V
3=-55,OoC
Vss= 0 V
TEMP TYpd MINb MAX' MIN b MAXt UNIT
INPUT
VL= 10.8 V
1
8.1
8.1
VL=15V
1
11.25
11.25
V L= 10.8 V
1
2.7
2.7
VL =15V
1
3.75
3.75
V IH
High Level Input Voltage
V
Low Level Input Voltage
VIL
High Level Input Current
IIH
V IN = 12 V
1,2,3
1
1
Low Level Input Current
IlL
V IN = 0 V
1,2,3
-1
-1
V L= 10.8 V
1
80
80
VL=15V
1
90
90
.I1A
Q OUTPUT e
1
Low Level Output Current
mA
IOLQ
Low Level Output Voltage
VOLQ
IOQ=80mA
1,2,3
30
30
V
Off-State Output Current
IO(OFF)
VOQ = 200 V
1,2,3
10
10
.I1A
1
-45
-45
mA
Clamp Current
10K
SERIAL OUTPUT
High Level Output Voltage
V OHS
IOHS = -100.l1A
1,2,3
Low Level Output Voltage
VOLS
IOLS = 100.l1A
1,2,3
11.5
11.5
V
0.5
0.5
DYNAMIC
Clock Frequency
fCLOCK
1,2,3
0
Pulse Duration
Clock High or Low
tw
1
125
125
Data setur, Time
before Rls ng Clock
tsu
1
100
100
Data Hold Time
after Rising Clock
tH
1
100
100
9-14
4
0
4
MHz
ns
Si9551 19552
..,. Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
LIMITS
Test Conditions
Unless Otherwise Specified: 1=25°C
2=125,70°C
VL = 12 V
3=-55,O°C
Vss= 0 V
TEMP TYpd
A
SUFFIX
C
SUFFIX
MINb MAX' MIN b MAXt
UNIT
DYNAMIC (Cont'd)
Delay Time
High to Low Level
Serial Output from Clock
tOHL
Delay Time
Low to High Level
Serial Output from Clock
tOLH
Tunr-On Time
Q Outputs fro Enable
tON
1
150
150
1
200
200
1
500
500
CL=10pFtoVss
IOL = 50 mA
R L = 2 k!l. to 130 V Supply
ns
SUPPLY
VL Supply Voltage
VL
1,2,3
V L Supply Current
IL
1,2,3
10.8
15
10.8
0.5
15
V
0.5
mA
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Output current measurements pulse duration =300 J,lS, duty cycle = 2 %.
TYPICAL CHARACTERSITICS
IL
8
7 I--Vol = 12
vs. Clock Frequency
t;
100
T A = 25°C
/
4
3
oV
o
80
/'"
5
2
90
./
6
IL
(mA)
~
V
I L vs. Temperature
110
./
V'
-
Voo - 12 V;
f eLK = 0
70
"
(~A)
60
50
40
V
~
1/
/'
""",
, V
30
/'
20
10
o
2
3
4
5
CLOCK FREQUENCY (MHz)
6
-60 -40 -20
0
20
40
60
80 100 120 140
TEMPERATURE (OC)
9-15
Si9551/9552
..... Siliconix
incorporated
~
SCHEMATIC DIAGRAMS
TYPICAl OF SERIAL OUTPUT
TYPICAL OF AlL Q OUTPUTS
EQUIVALENT OF EACH INPUT
VL
INPUT .....'11\1\1"'1'""""""
--~~----~----OUTPUT
VL
J
OUTPUT
--..,.........___- - - -....-
VSS - -__--f MIN b MAXt UNIT
Q OUTPUT e
High Level Output Current
IOHQ
1,2,3
-15
-15
Low Level Output Current
IOLQ
1,2,3
15
15
10K
1,2,3
Clamp Current
High Level Output Voltage
V OHQ
IOHQ = -15 mA
1,2,3
Low Level Output Voltage
VOLQ
IOLQ = 15 mA
1,2,3
High Level Output Voltage
VOHS
IOHS = -100 JLA
1,2,3
Low Level Output Voltage
VOLS
IOLS = 100JLA
1,2,3
20
70
mA
20
72
V
10
8
SERIAL OUTPUT
11.5
11.5
V
0.5
0.5
DYNAMIC
Clock Frequency
fCLOCK
1,2,3
Pulse Duration
Clock High or Low
tw
1
50
50
Data setur, Time
before Ris ng Clock
tsu
1
25
25
tH
1
25
25
Data Hold Time
after Rising Clock
Delay Time
High to Low Level
Serial Output from Clock
tOHL
Delay Time
Low to High Level
Serial Output from Clock
tOLH
Propogatlon Dela~ Time
High to Low Leve
Q Outputs from LE
tpHL
Propogatlon Delar Time
Low to High Leve
Q Outputs from LE
tpLH
12
0
8
0
10
ns
1
75
75
1
75
75
RL = 3.8 J4'l, toVoo
IOL=15mA
1
500
500
RL = 3.8 J4'l, toVss
IOL = -15 mA
1
500
500
CL= 10 pF to Vss
See Delay Time
Waveforms
MHz
ns
SUPPLY
VL Supply Voltage
VL
1,2,3
Voo
1,2,3
10.8
15
10.8
15
V
Voo Supply Voltage
9-22
0
80
0
80
SI9553/9554/9555/9556
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
Si9555/9556
LIMITS
Test Conditions
Unless Otherwise Specified: 1_25°C
A
C
2=125,70°C
SUFFIX
SUFFIX
V DD = 80 V, V L = 12 V
3=-55,0°C
-55 to 125°C
o to 70°C
Vss = 0 V
TEMP TYpd MINb MAX' MIN b MAXb UNIT
SYMBOL
SUPPLY (Cont'd)
V L Supply Current
fCLOCK = 0
1
1
0.5
All Outputs High
1,2,3
5
5
All Outputs Low
1,2,3
2
2
IL
V DD Supply Current
mA
IDD
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Output current measurements pulse duration = 300 .us, duty cycle = 2 %
TYPICAL CHARACTERSITICS
I DD vs. FOE
I L vs. Temperature
100
7~--~--~--~--~--~~~
J
L = \2)
f CLOCK = 0
I
10
.1
V
./
- ""
V L = 12 V;
TA = 25°C
6
/
V
5
V
I
Si9555/6 V DD = 80 V 7'-'--+---1
IDD
(mA)
V
~
.01
-60 -40 -20
0
20
40 60 80 100120140
o~--~--~--~--~--~~~
o
20
TEMPERATURE (OC)
40
I L vs. Clock Frequency
200
4500
/
1500
500
o 1/
o
V
;-":,~
120
V;
=112
V DD = 60 V
140
L
2000
100
160
./
3000
1000
180
)~
3500
IL
(.uA) 2500
80
I DD vs. Temperature
5000
V~ = J2 vI
4000 r-- T A = 25°C
60
OE FREQUENCY (kHz)
1/
I
120
IDD
(.uA) 100
./
II
80
/
60
/
40
'-
./
20
o
2
3
4
5
6
7
8
CLOCK FREQUENCY (MHz)
9
10
-60 -40 -20
0 20 40 60 80 100 120 140
TEMPERATURE (OC)
9-23
Si9553/9554/9555/9556
..,. Siliconix
incorporated
~
TRUTH TABLE
FUNCTION
LATCH
ENABLE
OUTPUT
ENABLE
INTERNAL
SHIFT REGISTER
LATCHES
...F
X
X
Shift Data
Determined
N.2.t
X
X
No Change
X
L
X
X
H
X
Determined by
X
X
L
CLOCK
CLOCK
LOAD
Q OUTPUTS
(Serial output Is always enabled)
by Latch
Determined
Enable
by Output
Enable
LATCH
OUTPUT
ENABLE
Hold
New Data
Determined
All Q outputs low
by Latch
X
X
H
Data Out
Enable
SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUT
VCC------~------~~--
INPUT ~Wlr-+--+
COMMON
}---
----I""1-;-r---5J--+--+-
TYPICAL OF SERIAL OUTPUT
VDD
VL
OUTPUT
OUTPUT
- - - - . , - - -....- 1 - - VSS
-;-
TYPICAL OPERATING SEQUENCE
LATCH ENABLE_ _ _ _ _ _ _ _
LATCH
CONTENTS
OUTPUT
ENABLE
Q OUTPUTS
9-24
~n,~-------------'nL...-----
P_R_EV_I_O_US_L-I.Y~lTORED
____________
DATA
X
NEW DATA VALID
------------------------l{rl--------------------------------~~~------
II
VALID
Si9553/9554/9555/9556
. " , Siliconix
incorporated
~
TYPICAL WAVEFORMS
CLOCK
DATA
IN
INPUT TIMING
i
\'----------------------------
50%
CLOCK _ _ _ _ _ _ _.....
I
;~~~~~
______________
:
~i~~r5--0%----------------------------------_--_:::
--I ,-- tOLH
---I
SERIAL
OUTPUT
t-- tOHL
~~:--------------%H
VOL
DELAY TIMES:
CLOCK TO SERIAL OUTPUT
LE
_ _ i- '\-----------v.
I
-.I
I
t-- tpLH
"iL
i ~-9-5%~-------------------- V
OH
Q
OUTPUT
_______________~I....J
I
_ _ _ _ _ _ _ _11.-.
Q
OUTPUT
: \
I
--,
- - - - - - - - - - - - - - - - VOL
------------------V
VOLIMAX)
I
r-
tpHL
OH
VOL
PROPAGATION DELAY TIMES:
LATCH ENABLE TO Q OUTPUTS
9-25
Si9553/9554/9555/9556
.... Siliconix
incorporated
~
BURN-IN DIAGRAM
1k
+15 V
'-I1-4-t--'VVIr() VL
'--t---1t--' 114 W
1k
1/4 W
NOTE:
1. For 819553/819554 use +60 V
For 819555/819556 use +80 V
9-26
H
Si9560
Electroluminescent
Symmetric Row Driver
Siliconix
incorporated
APPLICATIONS
FEATURES
ClI
o Flat Panel Displays
230 V Push-Pull Outputs
o High-Voltage Line
Drivers
o 100 mA Source/Sink
Current
13
34 Outputs Per Device
G
Right/Left Shift Pin
13
Polarity Output Gating
Non-Impact Printers
13
DESCRIPTION
The Si9560 is a monolithic D/CMOS integrated
circuit designed to interface video controllers to the
high-voltage row electrodes of AC thin-film
electroluminescent (ACTFEL) flat panel displays.
The Si9560 features 34 push-pull outputs and shift
register steering for easier use with large area
(640 X 200/400) displays.
The shift register steering is controlled by the R/L
shift pin which can be tied to Vss for clockwise, or
to VL for counterclockwise operation. The outputs
are controlled by the OUTPUT ENABLE and
POLARITY pins. New data is shifted on the falling
edge of CLOCK. If OE is high, a logic high data bit
will turn on the output as determined by POLARITY.
POLARITY high pulls the output up to VDD, while
POLARITY low pulls the output down to Vss.
The Si9560 is available in 44-lead plastic or ceramic
J-Iead quad packages, and is specified over the
commercial, C suffix (0 to 70°C) and industrial, D
suffix (-40 to 85°C) temperature ranges.
PIN CONFIGURATION
J-Iead Quad Package
Top View
QQQQQQQQQQQ
1314 151617 18 192021 22 23
6 5
Q12
Ql1
010
09
08
4
3 2
14443424140
0
Q24
025
026
Q27
028
07
029
06
05
030
031
04
03
032
Order Numbers:
Plastic:
Sl9560CN
Ceramic:
Sl9560DM
Q33
Q34
02
1819202122232425262728
0
1
Preliminary
DOC V R V P D V N
A U L S L LOA D C
T T 0 S
LTD
APe
AA
U K
R
J J
o T
U
TN
T E
Y
N
A
8
L
E
9-27
Si9560
~
~
Siliconlx
incorporated
FUNCTIONAL BLOCK DIAGRAM
Voo
"1L '
~-.------.-.-.--.,
POLARITY
IiI
OE
CLOCK
RIL
DATA IN
-
0-110-
III
Ill....
L..._ _
SIR
··
-··
I
I
I
_. __ •
-'-'11
__
_
·
( Q 3 through Q 33 not shown
1I
r- ..
Vss
I[
L_~
....__._-_. -_._---. ._-
-
Tr
Q1
~
I~
Lr-_.'\I
. .__. _._ . ._.__..J
BIT
I
I
I
__
,
'_._.-------_.__._.__.__._,
I
~ .. H
I
-.
34
0-
:--..
DATA OUT
TRUTH TABLES
FUNCTION
RIL
SHIFT REGISTER
DATA OUT
L
Q n - Q n +1
Q34
1.
H
Q n - Qn-1
Q1
NOt.
X
No Change
No Change
CLOCK
t.
LOAD
DATA
POL
OUTPUT
X
L
X
All OFF
H
H
H
H
H
H
L
L
L
H
X
OFF
L
9-28
ENABLE
=Logic 0,
H
=Logic 1, X =Don't Care
Preliminary
Si9560
..... Siliconix
incorporated
~
ABSOLUTE MAXIMUM RATINGS
Operating Temperature (0 Suffix) .......... -40 to 85·C
(C Suffix) ............ 0 to 70·C
Voltages Referenced to V 55
Voo ....•.................................... 240 V
V L .......................................... 16.5 V
Logic Inputs ...................... -0.3 V to VL +0.3 V
(CK, RIL, DATA IN, POLARITY, OE)
I SS (Pulsed) ................................. 1.0 A
Storage Temperature (0, C Suffix) ....... -65 to 125·C
Power dissipation (Package)"
44-Pln Plastic Quad"" .... . . . . . . . . . . . . . . . . . .. 1700 mW
44-Pln Ceramic Quad""" .......••....•...... 2000 mW
Device mounted with all leads soldered or welded
to PC board.
Derate 13.6 mW/·C above 25·C.
""" Derate 16 mW/·C above 25·C.
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
Voo = 225 Va
VL = 12 V
V55 = 0 V
SYMBOL
LIMITS
1=25·C
2=85,70·C
3=-40,O·C
TEMP TYpd
0
SUFFIX
C
SUFFIX
MINb MA>f MIN b MAXt UNIT
INPUT
High Level Input Voltage
VL= 10.8 V
1
8.1
8.1
VL= 13.2 V
1
9.9
9.9
VL= 10.8 V
1
2.7
2.7
VL= 13.2 V
1
3.3
3.3
ViH
V
Low Level Input Voltage
VIL
High Level Input Current
IIH
VI = 12 V
1,2,3
1
1
Low Level Input Current
IlL
VI = 0 V
1,2,3
-1
-1
Voo =Vo = 230 V
1,2,3
20
20
Voo= 230 V, Vo= 0 V
1,2,3
-20
-20
195
195
J1A
Q OUTPUTS
Off State Output Current
J1A
IO(OFF)
~1~Llr~Jr~ Output Voltage
VOHQ
lo=-70mA
1,2,3
Low Level Output Voltage
Q Outputs
VOLQ
lo=70mA
1,2,3
Low Level Q Output
Current
IOLQ
High Level Q Output
Current
Output Clamp Current
V
30
30
1
100
100
IOHQ
1
-100
-100
10K
1,2,3
-100
V L= 10.8 V to 13.2 V
Preliminary
100
-100
mA
100
9-29
Siliconix
incorporated
Si9560
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
Voo= 225 Ve
VL = 12 V
Vss = 0 V
SYMBOL
LIMITS
1=25°C
2=B5,70°C
3--40,O°C
TEMP TYpd
D
SUFFIX
MINb
MA~
C
SUFFIX
MIN b MAX
UNIT
SERIAL. OUTPUT
High Level Output Voltage
Serial Output
VOHS
10 = -100p.A
1,2,3
Low Level Output Voltage
Serial Output
VOLS
10 = 100p.A
1,2,3
11
11
V
1
1
DYNAMIC
4
0
4
fCLOCK
1
0
Pulse Duration
Clock High or Low
Iw
1
125
125
~:Igr~e~~~n~lrgrock
tsud
1
100
100
Data Setup Time
After Failing Clock
thd
1
100
100
Setu~ Time
~Ioc Lo~ Before
tsuc
1
300
300
Setup. Time
Enatile H~h Before
Voot or ss.
tsue
1
300
300
Setup. Time
Polarity High or Low Before
Voot or VSS+
'
tsup
1
300
300
Hold Time
Clock HI~ After
Voo+ or sst
the
1
500
500
Hold Time
Enable H~h After
VOO+ or sst
the
1
300
300
Hold Time
Polarity High or Low After
VOO + or Vsst
thp
1
300
300
Delay Time
High to Low Level
Output from Clock
tdHL
1
150
150
Dela~ Time,
Low 0 High Level
Output from Clock
tdLH
1
200
200
Transition Time
High to Low Level
Serial Output
ttHL
1
200
200
Transition Time
Low to High Level
Serial Output
ttLH
1
100
100
~1~u~~~rJ Trtg"r9.-~~ab'l~e
tanH
I OH = -50 mA, VOH = 195 V
RL = 2 k!l to 95 V
1
SOD
SOD
Low Level Turn-on Time
Q Outputs from Enable
tonL
I OL = 50 mA, VOL = 30 V
RL= 2 k!l to 130 V
1
500
500
Clock Frequency
~Ot
9-30
or ss+
MHz
ns
See Inp.ut Timing
Voltage Waveforms
ns
CL = 10 pF to
Ground
Preliminary
Si9560
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
Unless Otherwise Specified:
V DD = 225 VO
V L = 12 V
Vss = 0 V
SYMBOL
LIMITS
1=25°C
2=85,70°C
3=-40,0°C
TEMP TYpd
C
SUFFIX
D
SUFFIX
MINb MAX' MIN b MAXb UNIT
DYNAMIC (Cont'd)
High Level Turn-off Time
Q Outputs from Enable
toffH
I OH = -50 rnA, V OH = 195 V
R L = 2 k.O. to 95 V
1
1500
1500
Low Level Turn-off Time
Q Outputs from Enable
toffL
I OL = 50 rnA, VOL = 30 V
R L = 2 k.O. to 130 V
1
500
500
With One Active Output Driving
a 4.7 nF Load to V DD or V ss
1
45
45
Slew Rate, VDD or Vss
V/JJ.s
SUPPLY
Logic Supply Voltage
VL
1,2,3
10.8
15
10.8
15
VDD Supply VoltageO
VOD
1,2,3
a
230
a
230
V
a
1,2,3
0.5
0.5
f CLOCK = 16 kHz, 1 Output ON
1
2
2
All Outputs OFF
1,2,3
8
5
1 Output ON
1,2,3
15
10
fCLOCK =
Logic Supply Current
IL
rnA
VOO Supply Current
100
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Voo must be < 60 V above Vss during switch transitions. Slew rate of V DD orVss should be kept below 45 V/JJ.s.
f. Output current measurements pulse duration = 300 JJ.s, duty cycle = 2%.
SCHEMATIC DIAGRAMS
VL
--..,------r--
--.....,.----,---,-- vDO
V L ------,----,-----
+--+---
Input
+--1--
Output
Q Output
To
Control
LogIc
Vss
Typical
of Each Input
Vss
---1'0
------..1----..1----Typical
of So,Iai Output
- - - 4 - - - - 4 - - 4 - - VSS
Typical
Preliminary
of Each
Q Output
9-31
Power Conversion
II!II
~
~
5i1iconix
incorporated
TABLE OF CONTENTS
Introduction ............•.......•....•............•....................•...•....... 10-1
517660: Monolithic CM05 Voltage Converter ••.......................................... 10-2
517661: Monolithic CM05 Voltage Converter ........•...•............................... 10-9
5i9100/9101: 1-Watt. High-Voltage 5witchmode Regulators ............................... 10-16
519102: 1-Watt. High-Voltage 5witchmode Regulator .................................... 10-26
5i911 0/9111: High-Voltage 5witchmode Controllers ..................................... 10-35
5i9115/9116: OFF-Line 5witchmode Controllers .•.........•..................•......... 10-43
fIl"Jt" 8i1iconix
JI;II incorporated
!POWER CONVERSION
INTRODUCTION
Virtually every piece of electronic equipment in the world requires a dc power supply. This supply converts
power from a battery or an ac line (or sometimes both) into voltages and currents which are useful to the
specific piece of electronic equipment it serves. Usually, the outputs must remain constant despite changes in
input voltage, output load, and ambient temperature. In addition, the supply should have high conversion efficiency; inject a minimum of noise, ripple, or distortion onto its input or output; be small in volume, light in
weight, and low in cost.
8iliconix power conversion circuits bring effective solutions to the problems of supplying power to electronic
systems, while meeting the above criteria. 8i1iconix presently supplies three types of power conversion circuits:
high-voltage switchmode regulators, high-voltage switchmode controllers, and charge pump voltage converters.
The high-voltage switchmode regulators and controllers made by 8i1iconix employ high-performance D/CM08
power IC technology to combine CM08 current-mode controllers with high-voltage input regulation and output
switching. This design allows 8i1iconix to build extremely high efficiency switch mode power supply circuits that
can run directly from high-voltage inputs such as PBX or 18DN phone lines, or 110 VAC power lines.
The 8i9100, 8i9101, and 8i9102 are switch mode regulators which include an integrated 5 !l output M08FET
capable of supplying up to 5 Watt loads. They can be configured in single-ended converter topologies, and can
be run directly from input voltages as high as 120 V. The major applications for these devices are in telecommunications equipment such as PBX feature phones, 18DN terminals, line-powered modems, and central office
electronic equipment.
The 8i911 0 and 8i9111 are switchmode controllers with the same features as the switch mode regulators, except
that a push-pull output driver is utilized for driving an external M08FET switch for higher power applications.
These devices are generally used in telecommunications power supply applications greater than 5 Watts, as well
as for general purpose dc/dc power converters.
The 8i9115 and 8i9116 are switch mode controllers designed to run directly from the rectified 110 Volt ac power
line. Typical applications are in power supplies for electronic controls in appliances, small computers, and
high-voltage avionics systems.
Our family of low-cost CM08 charge pump voltage converters are used in applications where a single dc supply
is available. These monolithic products feature high conversion efficiency, minimum noise and distortion, and
minimum space requirements. They can be configured for voltage inversion or voltage doubling, and require
only a few external components (typicCllly 2 electrolytic capacitors). A typical application would be negative rail
generation in a circuit with a battery upply.
The 8i7660 is a charge pump converter that inverts or doubles input voltages from 1.5 Volts to 10 Volts. It
features power conversion efficiencies up to 98%. The 8i7661 is a higher-voltage version of the 8i7660 intended
for input voltages from 7.5 Volts to 20 Volts.
10-1
.....
~
Si7660
Monolithic CMOS
Voltage Converter
.... Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Improved - No External
Diode Required
• Conversion of +5 V Logic
Supply to ±5 V Supplies
• 99.7% Typical Open Circuit
Voltage Conversion
Efficiency
• Inexpensive Negative
Supply from Positive
Supply
• On Board Negative
Supply for Dynamic RAMs
• Localized J.1-Processor
(8080 Type) Negative
Supplies
• Inexpensive Negative
Supplies for Analog Switches
• Data Acquisition Systems
•
•
e
•
Easy to Use
Minimum Parts Count
Small Size
No Diode Drop at Output
• 95% Typical Power
Efficiency
• Operating Voltage Range
of 1.5 V to 10.0 V
• Requires Only 2 Capacitors
DESCRIPTION
The Siliconix Si7660 is a monolithic CMOS power
supply circuit which offers unique performance
advantages over previously available devices. The
Si7660 performs a supply voltage conversion from
positive to negative for an input range of +1.5 V to
+10.0 V, resulting in a complementary output
voltage of -1.5 V to -10.0 V with the addition of
only 2 capacitors.
ensures that the output N-channel switch substrates
are not forward-biased. The epitaxial layer prevents
latch up.
Typical applications for the Si7660 are data
acquisition and microprocessor based systems
where a +5 V supply is available for the digital
functions, and an additional -5 V supply is required
for the analog functions. The Si7660 is also ideally
suited for providing low current, -5 V body bias
supply for dynamic RAMs.
The "LV" terminal may be tied to GROUND to
bypass the internal regulator and improve low
voltage (LV) operation. At high voltages (+3.5 to
+10 V), the "LV" pin should be left disconnected.
Contained on the chip are a voltage regulator, RC
oscillator, voltage level translator, four power MOS
switches, and a logic network. This logic network
senses the most negative voltage in the device and
The oscillator, when unloaded, oscillates at a
nominal frequency of 12 kHz for an input supply
voltage of 1.5 to 10 V. The ·OSC" terminal may be
connected to an external capacitor to lower the
frequency or it may be driven by an external clock.
Packaging for this device includes the 8-pin metal
can, plastic miniDIP, and SO options. Performance
grades include military, A suffix (-55 to 125°C),
industrial, 0 suffix (-40 to 85°C), and commercial,
C suffix (0 to 70°C) temperature ranges. For
additional information please refer to Applications
Note AN84-2.
PIN CONFIGURATION
SO Package
(Same pinout as DIP)
Top View
NcOav+
CAP+
GND 3
OSC
6 LV
CAP-
5
vOUT
10-2
(AND CASE)
~
~
Top View
Order Number:
Plastlo: SI7660CJ
v+
Order Number:
SI7660DY
LV
CAP-
Order Number:
S17660M, S17660AA/883, S17660BA, SI7660CA
~
Si7660
Siliconix
.6;11 incorporated
FUNCTIONAL BLOCK DIAGRAM
~--------------~----------------~----~------------------------~
v+
,...----------------------0 CAP+
,...--------0 CAP-
L..-__.--oVOUT
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .........................•...... 11 V
Oscillator Input Voltage
...•........•..... -0.3 V to (V+ +0.3 V) for V+ < 5.5 V
............ (V+ -5.5 V) to (V+ +0.3 V) for V+ > 5.5 V
LV •..........•.......... No connection for V+ > 3.5 V
Storage Temperature (A & B Suffix) ....... -65 to 150°C
(C & 0 Suffix) .•.... -65 to 125°C
Operating Temperature (A
(B
(C
(0
Suffix)
Suffix)
Suffix)
Suffix)
Power Dissipation:'
8-Pln Metal Can" ........... . . .. .. .. . . . . .. .. 500 mW
8-Pln Plastic DIP'" ......................... 300 mW
SO-8'" ..•.................•....•....•.... 300 mW
All leads welded or soldered to PC board.
Derate 6 mW/oC above 75°C.
... Derate 10 mW/oC above 75°C.
......... -55 to 125°C
.......... -25 to 85°C
........... 0 to 70°C
.....•... , -40 to 85°C
ELECTRICAL CHARACTERISTICS a
PARAMETER
LIMITS
Test Conditions
1=25°C
A
B,C,D
Unless Otherwise Specified:
2=125,85°C
SUFFIX
SUFFIX
V+ = 5 V
3=-55,-40,-20,O°C
Coso = Od
TYpo
SYMBOL
TEMP
MINb MAX' MINbMAX t UNIT
INPUT
SUWIY Voltage Range
LO
V+ L
RL= 10 kn, LV = GND
1,2,3
1.5
3.5
1.5
3.5
V+ H
RL = 10 kn, LV = NC
1,2,3
3
10
3
10
1+
RL=IXl, LV = OPEN
1,2,3
V
SUp~y
HIG
Voltage Range
Supply Current
100
500
500
)J.A
10-3
W7" Siliconix
Si7660
~
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
PARAMETER
V+ = 5V
Cosc =Od
LIMITS
1=25°C
2=125,85°C
3=-55,-40,-20,0°C
A
SUFFIX
B,C,D
SUFFIX
MINb MA>f MIN b MAXI UNIT
TEMP
TYp c
V+ = 5 V, LV= OPEN
10 = 20 mA
1
3
2
55
V+ = 2 V, LV = GND
10= 3 mA
1,2,3
PEl
RL = 5 k.n.
1
98
95
95
VOUTEl
RL=cc
1
99.9
97
97
1
12
kHz
V+ = 2 V, LV= GND
1
1
M.n.
V+ = 5 V
1
100
kO.
SYMBOL
OUTPUT
out~ut
Source
Res stance
Power Conversion
Efficiency
ROUT
100
120
150
100
120
120
300
300
.n.
%
Voltage Conversion
Efficiency
DYNAMIC
Oscillator Frequency d
fose
Oscillator Impedance
Zose
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. For C osc > 1000 pF, C 1 and C 2 should be Increased to 100 jJ. F . C 1 = Pump Capacitor, C 2 = Reservoir Capacitor.
DIE TOPOGRAPHY
Pad
No.
r
64 mils
CSABA
~~--~--~--~
2 Resistors
1 Zener Diode
40 P-channel enhancement MOSFETs
1 Diode
3 Capacitors
48 N-channel enhancement MOSFETs
10-4
J
2
3
4
5
6
7
8
Function
CAP+
GND
CAPVOUT
LV
OSC
V+
Si7660
..... Siliconix
incorporated
~
TYPICAL CHARACTERSITICS
Figure 1. Operating Voltage as a
Function of Temperature
Figure 2. Output Source Resistance as
a Function of Supply Voltage
1000
500
1
200
\
ROUT
16
(nA)
(.0.) 100
50
20
I
I
I
25
I
-55
I
I
I I
85
10
125
o
2
4
TA (OC)
I-I~=~m~
200
.JIll'
ROUT
(.0.)
,1.~
0 I- V! =
~
150
V
~ i""
.......
100 l - I--
I'
-1
V+ = 2 V
VOUT
(V)
-2
2
f-- V+ 1=
-5
1/
V
...". V"
i,.....--'" i""'"
~
f
~
L
I""""
V
V
JIll' I '
,..
,.
-2 ioo'"
....
I.---"
./
.... .-- ~
."
,,"" .,.,./..... 1.,..00"
,,. ..,.. ~
..,.. .....
./
,.".
i""
-~
o
20
.JIll'
./
.",..
40
i"""
10
20
3.0
40
Figure 6. Typical Supply Current vs.
Temperature
140
I~
~
JIll'
~
,/
'"
o
OUTPUT CURRENT (mA)
3.~ - 4~ - 5vl _ 16v'~
0
-10
1
3.5 V
-4
Figure 5. Typical SI7660 Output LV OPEN
-8
10
V+ - 5 V
o
-6
]5~ -
r--
I'
L
,.".
-60 -40 -20 0 20 40 60 80 100120 140
T A - TEMPERATURE (OC)
VOUT -4
(V)
V
II
lL
-3
I-
..-
50
8
Figure 4. Typical SI7660 Output
LV = GND
Figure 3. Output Source Resistance vs.
Temperature
250
6
INPUT VOLTAGE (V)
V
,..
.;'
.... 1----'"
V
JIll'
7V
120
8V
100
9V
10 V
I SUPPLY
(jlA)
"" r-...
~
80
..,.. ./
........ ....
~
V+ = 5 RL = co
60
60
80
OUTPUT CURRENT (mA)
100
40
-60 -40 -20
0 20
40 60
80 100 120140
T A - TEMPERATURE (OC)
10-5
Si7660
tI"r' Siliconix
~
incorporated
TYPICAL CHARACTERSITICS (Cont'd)
Figure 7. Oscillation Frequency as a
Function of External OSC.
Capacitance
10000
Figure 8. Unloaded Oscillator Frequency
as a function of Temperature
30
~"
1000
25
'"
V+ = 5 V SUPPLY _
"""-.
fosc
(Hz)
-
V+ = 2 V SUPPLY
100
,
\
20
15
"'\."
fosc
(kHz)
10
,~
"........
5
""
10
100
1000
INPUT VOLTAGE (V)
Figure 9.
100
80
Power Conversion Efficiency
as a Function of OSC.
Frequency
/'
60
(%)
I"'"
IL= 1 mA
~
,
IL= 15 mA
Efflc.
~
40
20
L
/
~
Vi =1
o
100
200
500
1000
2000
1J
5
5000 10000
FREQUENCY (Hz)
SWITCHING TIME TEST CIRCUIT
_ _ _ _ _ -,C080
~+
... l-
10-6
I
I
--
-60 -40 -20 0 20 40 60 80 100 120 140
T A - TEMPERATURE (OC)
lWt
/
.......
r--.. r-.... .......
I
o
1000
r--.... ........
2 V SUPPLY
'\.'\.
10
1.0
5 V SUPPLY
IL
Si7660
...... Siliconix
.£II incorporated
PIN DESCRIPTION
Symbol
Pin Description
NC
No connection.
2
CAP+
Positive terminal connection for pump capacitor.
Pin
Number
3
GND
Input and/or output ground reference.
4
CAP-
Negative terminal connection for pump capacitor.
5
VOUT
Output of the voltage converter.
6
LV
Low Voltage. Connection to ground shorts out internal power supply regulator for
operation below 3.5 V.
7
OSC
Oscillator input. External clock input to this pin will override the internal oscillator. The
internal oscillator frequency can be slowed by connecting an external capacitor
between this pi~ and ground. (See Figure 8.)
8
V+
Input voltage connection.
APPLICATIONS
.
The Siliconix Si7660 is a VOLTAGE source, not a
CURRENT source. Therefore, any heavy load
current will either greatly reduce the output voltage
(possibly out of the desired range) or cause the
device to go into power shutdown. To avoid
problems, keep the VOLTAGE conversion concept
in mind.
The 8i7660 is intended for use as a voltage
inverter. However, with a few added components,
the inverter circuit can be rearranged to provide
many different voltage levels. 80me of the
possibilities include voltage inversion, voltage
multiplication, and even simultaneous inversion and
multiplication. For more information refer to
Application Note AN84-2.
There are many applications where a low current
negative supply made with an 5i7660 would do just
as well as a full conventional negative sllpply or
dc-to-dc converter module. Some examples are
I'!egative power supplies for microprocessors,
dynamic RAMs, or data acquisition systems.
If the output ripple of the Si7660 is too great for a
particular application, the value of the pump (C1,
Fig. 10) and reservoir (~, Fig. 10) capacitors can
be increased to reduce this effect. However, it is
important to note that increasing the capacitor size
can lead to surge currents at turn-on. If the current
is too great, the power dissipation of the device can
be exceeded, causing destruction of the device.
The maximum recommended capacitor size is
1000 jJ.F.
The previous version of the Si7660 required a diode
in series with pin 5 when operating above 6.5 V.
The improved 8i7660 does not require this diode.
The improved version will work in existing circuits
which have the diode.
8
.---12
7
817660
3
6
4
5
Figure 10.
Basic Voltage Inverter Circuit
Figure 11 shows a circuit that will produce two
output voltages utilizing both of the 8i7660 features
(i.e. inversion and doubling). The combined output
current must be limited so the maximum device
dissipation is not exceeded.
Two 8i7660's can be paralleled to reduce the
effective output resistance of the converter. The
output voltage at a given current is increased since
the voltage drop is halved when the devices are
connected as shown in Figure 12.
10-7
Siliconix
incorporated
Si7660
APPLICATIONS (Cent'd)
v+
8
...----12
7
3
617660
6
+
5
Figure 11.
Combination Inverter/Multiplier Circuit
v+
8
,..----12
7
3
617660
6
8
r----i2
7
Sl7660
Figure 12.
3
6
4
5
Paralleling Two SI7660's to Reduce the Effective Output Resistance
BURN-IN DIAGRAM
.-----~Ar--_o-5V
+5 V 0 - - - - ' \
GND
DEVICE
PIN
1
2
3
4
5
6
7
6
10-8
BIAS
NC
NC
GND
NC
R2to -5 V
NC
NC
R 1 to +5 V
GND
Si7661
Monolithic CMOS
Voltage Converter
..,. Siliconix
incorporated
~
FEATURES
BENEFITS
APPLICATIONS
• Conversion of +4.5 V to
+20 V Logic Supply to
-4.5 V to -20 V Supplies
• Inexpensive Negative
Supply Generation
• On board Negative
Supply for Dynamic RAMs
• Easy to Use, Requires
Only 2 External
Capacitors
• Localized Il-Processor
(8080 Type) Negative
Supplies
• Minimum Parts Count
• Small Size
• Inexpensive Negative
Supplies for Analog Switches
• Voltage Multiplication
(Vour = H nVIN )
• 99.7% Typical Open Circuit
Voltage Conversion
Efficiency
• 95% Typical Power
Efficiency
• Data Acquisition Systems
• Up to -20 V for Op Amps,
and other Linear Circuits
DESCRIPTION
The Siliconix Si7661 is a monolithic CMOS power
supply circuit which offers unique performance
advantages over previously available devices. The
Si7661 performs a supply voltage conversion from
positive to negative for an input range of +4.5 V to
+20 V, resulting in a complementary output voltage
of -4.5 V to -20 V with the addition of only 2
capacitors.
Typical applications for the Si7661 are data
acquisition and microprocessor based systems,
where a +4.5 to +20 V supply is available for the
digital functions, and an additional -5 to -20 V
supply Is required for analog devices, such as op
amps. The Si7661 is also ideally suited for providing
low current, -5 V body bias supply for dynamic
RAMs.
Contained on the chip are a voltage regulator, RC
oscillator, voltage level translator, four power MOS
switches, and a logic network. This logic network
senses the most negative voltage in the device and
ensures that the output N-channel switch substrates
are not forward-biased. An epitaxial layer prevents
latchup.
The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply
voltage of 4.5 to 20 V. The "OSC" terminal may be
connected to an external capacitor to lower the
frequency or it may be driven by an external clock.
The " LV" terminal may be tied to GROUND to
bypass the internal regulator and improve low
voltage (LV) operation. At high voltages (+8 to
+20 V), the "LV" pin should be left disconnected.
Packaging for this device includes a-pin metal can
and plastic MiniDIP options. Performance grades
include military, A suffix (-55 to 125°C), industrial,
D suffix (-40 to 85°C), and commercial, C suffix (0
to 70°C) temperature ranges.
For more
information refer to AN84-2.
PIN CONFIGURATION
V+ (AND CASE)
CAP-
Order Numbers:
SI7661AA, SI7661BA, SI7661CA
NcOav+
Top View
CAP+ 2
7
OSC
GND 3
6
LV
CAP- 4
5
VOUT
Order Number:
Plastic: SI7661CJ
10-9
WY'Siliconix
incorporated
Si7661
~
FUNCTIONAL BLOCK DIAGRAM
r---------------~----------------~~----~--------------------------o V+
r------------------------oCAP+
.----------------() CAP-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................ 22 V
Oscillator Input Voltage ............................. .
.... .. . .. . .. . .. ..... -0.3 V to (V+ +0.3 V) for V+ <6 V
.. , ............. (V+ -6 V) to (V+ +0.2 V) for V+ >6 V
LV ........................ No Connection for V+ >9 V
Storage Temperature (A & 8 Suffix) ....... -65 to 150°C
(C Suffix) ........... -65 to 125°C
Operating Temperature (A Suffix) ......... -55 to 125°C
(8 Suffix) .......... -25 to 65°C
(C Suffix) ............ 0 to 70°C
Power Dissipation'
6-Pln Metal Can" .. . . . . . . . . . . . . . . . . . . . . . . . .. 500 mW
6-Pln Plastic DIP'" ......................... 500 mW
All leads welded or soldered to PC board.
•• Derate 6 mW/oC above 75°C.
••• Derate 6.6 mW/oC above 25°C.
ELECTRICAL CHARACTERISTICS a
Test Conditions
Unless Otherwise Specified:
Cosc = 0 9
PARAMETER
SYMBOL
LIMITS
1=25°C
2=125,85,70 0 (
3=-55,-25,0 °c
TEMP
TYP d
A,B,C
SUFFIX
MIN b 'MAXb
UNIT
INPUT
Supply Voltage Range (LV)
V+ LV
RL = 10 kn., LV = 0 V
1,2,3
4.5
9
Supply Voltage Range
V+
RL = 10 kn., LV OPEN
1,2,3
6
20
V
Supply Current
10-10
V+ = 4.5 V, RL=oo, LV = 0 V
1
100
500
JJ.A
V+ = 15 V, RL = 00, LV OPEN
1
0.7
2
mA
1+
H
Si7661
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
LIMITS
Test Conditions
Unless Otherwise Specified:
1_25°C
2=125,85,70 o(
3=-55,-25,0 °c
Cose = 0 9
TEMP
TYP d
V+ = 4.5 V, LV = 0 V
10 = 3 mA
1
75
V+ = 15 V, LV OPEN
10 = 20 mA
1,3
2
55
1
92
SYMBOL
PARAMETER
A,B,C
SUFFIX
MIN b MAXb
UNIT
OUTPUT
Output Source Resistance
ROUT
Power Conversion Efficiency
PEl
n.
V+ = 15 V,
RL =2kn.
100
120
%
Voltage Conversion Efficiency
V ouT E l
V+ = 15 V, RL=oo
1
99.7
fose
V+ = 15 V
1
10
kHz
V+ = 4.5 V, LV = 0 V
1
1
Mn.
V+ = 15 V
1
100
kn.
97
DYNAMIC
Oscillator Frequency
9
Oscillator Impedance
Zose
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. ForCos e > 1000 pF, C l and C 2 should be Increased to 100J,lF ,C l = Pump Capacltor,C 2 = Reservoir Capacitor.
DIE TOPOGRAPHY
5
20X
8
i
94 mils
Pad
No.
Function
2
3
4
5
6
7
8
CAP+
GND
CAPVOUT
VL
OSC
V+
ID
4
1
CSHA
3 Capacitors
1 Resistor
1 Zener Diode
47 N-Channei Enhancement Mosfets
40 P-Channei Enhancement Mosfets
10-11
W'JP'" Siliconix
Si7661
~
incorporated
TYPICAL CHARACTERSITICS
FIgure 1.
140
120
100
\~
130
o
4
V+ = 5 V ~
ROUT 110
(.0.)
'"
60
40
\
150
~
80
Output Source ResIstance as a
FunctIon of Temperature
170
\
ROUT
(.0.)
FIgure 2.
Output Source ResIstance as a
FunctIon of Supply Voltage
IL= 3 mA
............
8
-
70
IL= 20 mA
-~
f.--"
50
-55
20
16
12
./"
90
5
-25
0
VOUT
(V)
-4
-6
-8
-10
5V
6V
7V
,1/
-2
~ ./
""
.,,- "" "
V"
l/
"".,,- ,
../
o
,.,,.,
~
/
./
../
~
~
/
~v
10'
VOUT
(V) -10
80
-20
100
OUTPUT CURRENT (mA)
FIgure 5.
Supply Current
100
90
80
~ I"'""
~ I""'""
o
20
50
40
-25
"
~ I--'
I-- ~
....
FIgure 6.
Temperature
--
5
35
65
TEMPERATURE (OC)
~~
40
1~~
-*
--
~ """'12 V
~
~
18";:'
2~
J
I
60
80
100
Frequency of OscillatIon as a
FunctIon of External Oscillator CapacItance
10000
.......
~
1000
\\
60
-55
~~
LV = GND
V+ = 4.5 V-
~
II
OUTPUT CURRENT (mA)
RL=~
I SUPPLY
(J1A) 70
10-12
VS.
125
/1
.,.I'"
.......
----------- ------- ---------.-
60
95
V+ = 8 V
~ I"'""
40
65
TypIcal SI7661 Output
LV = OPEN
~
i"""
20
35
/
./
~
I
o
8V
/
/
'/
~
FIgure 4.
TypIcal SI7661 Output
LV = GND
_I v+ 14.1 V
~ I""'"V+ = 15 V
TEMPERATURE (OC)
SUPPLY VOLTAGE (V)
FIgure 3.
--
V
fosc
(HZ)
~
95
100
~
=
=
I
10
125
V+-15V
TA - +25°C
I
1
10
100
Cose (pF)
1000
10000
Si7661
~ Siliconix
.,I;lI incorporated
TYPICAL CHARACTERSITICS
Figure 7.
Figure 8.
Unloaded Oscillator Frequency
as a Function of Temperature
100
16
I\.
14
12
10
fosc
(kHz)
8
" '"
6
V+
95
"-
"...
" i'...
= 15 V
-r--
-25
o
1\
Efflc.
(%)
r--
85
r- V+
80
~C1 rCi =1 111
2
-55
~
90
4
o
SI7661 Power Efficiency vs.
Oscillator Frequency
= 15 V
T A = +25°C
RL =2 K.O.
~
1
75
25
50
75
100
125
1
TEMPERATURE (OC)
5
2
10
20
50
100
OSCILLATOR FREQUENCY f osc (kHz)
SWITCHING TIME TEST CIRCUIT
8
,----12
7
517661
3
6
4
5
_____ -,Cosc
IS
IL
V+
""-:L+
.,L.
~
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
PIN DESCRIPTION
NC
No connection.
2
CAP+
Positive terminal connection for pump capacitor.
Input and/or output ground reference.
3
GND
4
CAP-
Negative terminal connection for pump capacitor.
5
VOUT
Output of the voltage converter.
6
LV
Low Voltage. Connection to ground shorts out internal power supply
regulator for operation below 9.0 volts.
7
OSC
Oscillator input. External clock input to this pin will override the internal
oscillator. The internal oscillator frequency can be slowed by connecting
an external capacitor between this pin and ground. (See figure 6.)
8
V+
Input voltage connection.
10-13
Si7661
..... Siliconix
.,1;11 incorporated
APPLICATION HINTS
The Siliconix Si7661 device is a VOLTAGE source,
not a CURRENT source. Therefore, any heavy load
current will either greatly reduce the output voltage
(possibly out of the desired range) or will cause the
device to go into power shutdown. To avoid
problems, keep the VOLTAGE conversion concept
in mind.
The Si7661 is intended for use as a voltage
inverter. However, with a few added components,
the inverter circuit can be rearranged to provide
many different voltage levels. Some of the
possibilities include voltage inversion, voltage
multiplication, and even simultaneous inversion and
multiplication. For more information refer to
Application Note AN84-2.
There are many applications where a low current
negative supply made with an Si7661 would do just
as well as a full conventional negative supply or
DC-to-DC converter module. Some examples are
negative power supplies for microprocessors,
dynamic RAMs, or data acquisition systems.
When an external clock is used to drive the Si7661
a 1000 n resistor should be used between the
clock source and the OSC input (pin 7) as shown in
Figure 10.
V+
V+
6
1 k.O.
7r-----~~~--~
r-----;2
517661
3
CMOS
GATE
6
'--....:....-t.;4!..........:5!..t----:-~---o
VOUT
Figure 10. Driving the 817661 with an External Clock
Figure 11 shows a regulator that will operate with
much less than 1 volt drop between V+ andVOuT at
large output currents. Most three terminal voltage
regulators would exhibit a drop of a volt or more
under these conditions.
In addition, the extended input voltage range of the
Si7661 lends itself for use as a negative generator
for most op-amp applications.
If the output ripple of the Si7661 is too great for a
particular application, the value of the pump (Cl,
figure 9) and reservoir (C2) capacitors can be
increased to reduce this effect. However, it is
important to note that increasing the capacitor size
can lead to surge currents at turn-on. If the current
is too great, the power dissipation of the device can
be exceeded, causing destruction of the device.
The maximum recommended capacitor size is
1000 jJ.F.
V+
r-----; 2
6
7
517661
3
6
5
V+
10jl.F +
C1
10 jI. F L..-----':..--t..!_~
-r
• The Zener Voltage sets the output
of the regulator,
Figure 9. Basic Inverter Circuit
10-14
Figure 11. Low Loss Regulator Circuit
VN0300
VOUT
Si7661
.... Siliconix
incorporated
~
BURN-IN DIAGRAM
R1
R2
+15 V
-15 V
8
R l' R2
7
6
5
DEVICE
PIN
= 1 k,O.
GND
1
2
3
4
5
6
7
8
BIAS
NC
NC
GND
NC
R 2 to -15 V
NC
NC
R 1to +15V
10-15
Si91 00/91 01
1-Watt, High-Voltage
Switchmode Regulators
APPLICATIONS
FEATURES
• 10 to 70 V Input Range
• ISDN Terminals
• Current-mode Control
• PBX Equipment
• On chip 150 V, 5
MOSFET Switch
WY'Siliconix
.,1;11 incorporated
n
• Modems
• Feature Telephones
• Reference Selection
Si9100 - ± 1%
Si9101 - ±10%
• DCIDC Converters
• Distributed Power Systems
• High Efficiency Operation
(> 80%)
• Internal Start-up Circuit
• Internal Oscillator
(up to 1 MHz)
DESCRIPTION
The
Si91 00/Si91 01
high-voltage
switchmode
regulators are monolithic D/CMOS integrated
circuits which contain, most of the components
necessary to implement a 1-watt, high-efficiency dc
to dc converter. They can either be operated from
a low-voltage dc supply, or directly from a 10 to
70 V unregulated dc power source.
SHUTDOWN and RESET logic inputs, and external
clock synchronization. This device may be used
with an appropriate transformer to implement most
single ended isolated power converter topologies
(i. e., flyback and forward), or by using an external
reference can generate a +5 V non-isolated output
from a -48 V source.
The switch mode regulator subsystem includes
high-voltage start-up circuitry, oscillator, voltage
reference, current-mode PWM circuitry and a
high-speed, 150 V, 5 n MOSFET switch. Additional
features
include
primary
current
sense,
The Si9100/Si9101 is available in 14-pin plastic,
CerDIP and PLCC 20-pin packages, and is specified
over the military, A suffix (-55 to 125°C) afld
industrial, 0 suffix (-40 to 85°C) temperature
ranges.
PIN CONFIGURATION
Dual-ln-Llne Package
PLCC Package
3
2
1
FUNCTION
20 19
14
BIAS
2
13
4
18
3
12
5
17
4
11
6
16
5
10
7
15
6
9
8
14
7
8
+VIN
DRAIN
SOURCE
TopVlew ,
Order Numbers:
CerDIP:
S19100AK. SI9101AK
Plastlo:
S19100DJ. SI9101DJ
10-16
-VIN
vcc
OSC OUT
OSC IN
DISCHARGE
9
10
11
12 13
Top View
Order Number:
S19100DN.
SI~10IDN
VREF
SHUTDOWN
RESET
COMP
FB
14-pln DIP
Pin #
PLCC-20'
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
3
5
7
8
9
10
11
12
14
16
17
18
20
• Pins 1. 4. 6. 13. 15 and 19 = N/C
~
~
Si91 00/91 01
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
FB
COMP
Error
Amplifier
V REF
0--------11'--1
a
DRAIN
0
1.2V
BlAB
-V IN
(BODY)
To
Internal
Circuits
'-------------+--+---------''----0
SOURCE
VCC
v cc 0-------+
Undervoltage
Comparator
a
S
SHUTDOWN
R
RESET
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN
VCC ......................................... 15.0 V
+VIN
......................................... 70 V
VDS ......................................... 150 V
ID (Peak) (Note 1) ............................. 2.5 A
lo(rms)
•••.......•......................... 350 mA
Logic Inputs (RESET,
SHUTDOWN, OSC IN) ........... -0.3 V to Vcc + 0.3 V
LInear Inputs
(FEEDBACK, SOURCE) ............... -0.3 V to 7.0 V
Operating Temperature (A Suffix) ......... -55 to 125°C
(D Suffix) .......... -40 to 85°C
Junction Temperature (T J) ..................... 150°C
Power
14-Pln
14-Pln
20-Pln
Dissipation (Package)'
Ceramic DIP (K Suffix)" ..•••..••.••.. 1000 mW
Plastic DIP (J Suffix)'" ...••...••.•.•• 750 mW
PLCC (N Suffix)···· ......•......•... 1400 mW
Thermal Impedance (8JA )
14-Pln Ceramic DiP ......................... 100°C/W
14-Pln Plastic DIP .......................... 167°C/W
20-Pln PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .. 90°C/W
HV Preregulator Input Current (continuous) ........ 3 mA
Note 1: 300 J1S pulse, 2% duty cycle
Storage Temperature (A Suffix) .......... -65 to 150°C
(D Suffix) ........... -65 to 125°C
Device mounted with all leads soldered or welded
to PC board.
Derate 10 mW/oC above 50°C
Derate 6 mW/oC above 25°C
•••• Derate 11 mW/oC above 25°C
10-17
Si91 00/91 01
. . . . Siliconix
incorporated
~
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
DISCHARGE = -YIN = 0 V
Vee= 10 V, +VIN = 48 V
RBJAS = 390 ~
Rose= 330 ~
VR
RL = 10 M.o.
(See Detailed Description)
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55, -40 ° C -55 to '125°C
D
SUFFIX
-40 to 85°C
TEMP TYpd MINb MAX' MIN b MAXt UNIT
REFERENCe
Output Voltage
Output Impedance
ZOUT
V REF = -VIN
Short Circuit Current
Temperature Stability
1
4.0
V
1
30
~
1
100
.I1A
2,3
1
mV/OC
,
OSCILLATOR
Maximum Frequency
fose
Initial Accuracy
Voltage Stability
Vose
1
MHz
Rose= 0
1
3
1
See Note e
1
100
80
9.5 V $ Vee $ = 13.5 V
1
±3
%
2,3
500
ppm/oC
Temperature Coefficient
120
80
120
kHz
ERROR AMPLIFIER
Feedback Input Voltage
VFB
Input BIAS Current
Open Loop Voltage Gain
FB Tied to COMP
SI91 00
1
4.00
3.96
4.04
3.96
4.04
See
Detailed Description
Reference Section
SI9101
1
4.00
3.60
4.40
3.60
4.40
1
25
1
80
1
1
MHz
1
50
~
Source
VFB= 3.4 V
1
2.0
1.4
1.4
Sink
VFB = 4.5 V
1
0.15
.12
.12
9.5 V S Vee S = 13.5 V
1
70
V
VFB= 4.0 V
AVOL
Unity Gain Bandwidth
Output Impedance
Output Current
Power Supply Rejection
10-18
ZOUT
500
60
500
60
lOUT
PSRR
nA
dB
mA
dB
H
Si91 00/91 01
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
LIMITS
Unless Otherwise Specified:
1=25°C
A
D
DISCHARGE = -VIN = a v
2=125.85°C
SUFFIX
SUFFIX
V cc =10V.+VIN =46V
3=-55.-40°C -55 to 125°C -40 to 8SoC
R SIAS = 390 kn
Rosc= 330 kn
SYMBOL
TEMP TYpd MINb MAX' MIN b MAXt
UNIT
CURRENT LIMIT
VSOURCE
RL = lOOn from DRAIN toVcc
V FS = a V
1
1.2
td
R L = 100.0. from DRAIN toV cc
V SOURCE = 1.4 V. See Figure 1
1
150
Input Voltage
+VIN
liN = 100 JJ.A
Input Leakage Current
+IIN
Threshold Voltage
1.4
V
200
200
ns
1
70
70
V
Vcc 2: 9.4 V
1
10
10
JJ.A
I PREREGULATOR = 10 JJ.A
1
6.6
9.4
9.4
R L = 100.0. from DRAIN toV cc
(See Detailed Description)
1
6.1
6.9
6.9
Icc
1
0.6
1.0
1.0
ISlAS
1
15
1
50
Delay to Output
1.0
1.4
1.0
PREREGULATORISTARTUP
V cc Preregulator Turn-OFF
Threshold Voltage
V
Undervoltage Lockout
SUPPLY
Supply Current
Bias Current
mA
./.I.A
LO~IC
SHUTDOWN Delay
tSD
SHUTDOWN Pulse Width
tsw
VSOURCE = -VIN
See Figure 2
1
100
50
100
50
ns
RESET Pulse Width
tRw
Latching Pulse Width
SHUTDOWN and RESET
LOW
See Figure 3
1
50
50
tLW
1
25
25
Input LOW Voltage
V IL
1
Input HIGH Voltage
V IH
1
Input Current
Input Voltage HIGH
IIH
VIN = 10 V
1
1
5
5
Input Current
Input Voltage LOW
IlL
VIN=OV
1
-25
-35
-35
2.0
2.0
V
6.0
8.0
./.I.A
10-19
Si91 00/91 01
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
DISCHARGE = -VIN = 0 V
VCc= 10 V. +VIN = 48 V
R BIAS = 390 k.O.
R OSC = 330 k.O.
LIMITS
1=25·C
A
2=125.85·C
SUFFIX
3=-55.-40·C -55 to 125°C
0
SUFFIX
-40 to 85°C
TEMP TYpd MINb MAX' MIN b MAXt
UNIT
MOSFET SWITCH
Breakdown Voltage
V(BR)DSS
V SOURCE = V SHUTDOWN = 0 V
I DRAIN = 100 J1A
2.3
180
~~~\~t:~~~fe ON
rDS(ON)
VSOURCE= 0 V
I DRAIN = 100 mA
1
3
Drain OFF Leakage Current
loss
V SOURCE = V SHUTDOWN = 0 V
V DRAIN = 100 V
1
Drain Capacitance
CDS
V SOURCE = V SHUTDOWN = 0 V
1
150
150
V
5
5
.0.
10
10
J1A
250
pF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design. not subject to production test.
d. Typical values are for DESIGN AID ONLY. not guaranteed nor subject to production testing.
e. CSTRAY Pin 8 = 0 pF.
f. Temperature coefficient of rDS(ON) Is 0.75% per ·C. typical.
TIMING WAVEFORMS
1.4 VSOURCE
VCC
SHUTDOWN
o
o
~
o
10%
SD
10%
Figure 2
Figure 1
VCC--_ _.....
S"'H7.U";:;T""D""OW:":'::"N·
oVCC _ _ _ _ _ __
RESET
o-
Figure 3
10-20
~
VCC DRAIN
VCC DRAIN
~
~
Si91 00/91 01
Siliconix
incorporated
TYPICAL CHARACTERSITICS
Output Switching Frequency vs. Oscillator
Resistance
+VIN vs. +IIN at Startup
140
1M
120
.....
I
1/
VCC- -YIN
100
80
+VIN
~
(Hz)
V
40
V
./
20
o
fOUT 100 K
J
(V) 60
1- ~
10
15
+IIN (rnA)
10 K
10 k
20
100 k
1M
rDS(ON)
(.0. )
Figure 5
Figure 4
DETAILED DESCRIPTION
PREREGULATORISTARTUP SECTION
Due to the low quiescent current requirement of the
Si9100 control circuitry, bias power can be supplied
from the unregulated input power source, from an
external regulated low-voltage supply, or from an
auxiliary" bootstrap" winding on the output inductor
or transformer.
When power is first applied during startup, +VIN
(pin 2) will draw a constant current. The magnitude
of this current is determined by a high-voltage
depletion MOSFET device which is connected
between +VIN and Vee (pin 6). This startup circuitry
provides initial power to the Ie by charging an
external bypass capacitance connected to the Vee
pin. The constant current is disabled when Vee
exceeds 8.6 V. If Vee is not forced to exceed the
8.6 V threshold, then Vee will be regulated to a
nominal value of 8.6 V by the preregulator circuit.
As the supply voltage rises toward the normal
operating conditions, an internal undervoltage (UV)
lockout circuit keeps the output MOSFET disabled
until Vee exceeds the undervoltage lockout
threshold (typically 8.1 V). This guarantees that the
control logic will be functioning properly and that
sufficient gate drive voltage is available before the
MOSFET tu~ns ON. The design of the Ie is such that
the undervo~age lockout threshold will not exceed
the preregulator turn-off voltage. Power dissipation
can be minimized by providing an external power
source to Vee such that the constant current source
is always disabled.
NOTE: During startup or when Vee drops below
8.6 V the startup circuit is capable of sourcing up to
20 mAo This may lead to a high level of power
dissipation in the Ie (for a 48 V input, approximately
1 W). Excessive start up time can result in device
damage. See Figure 4 for calculation of power
dissipation during start up.
BIAS
To properly set the bias for the Si91 ~O, a 390 k!l
resistor should be tied from BIAS (pin 1) to -VIN
(pin 5). This determines the magnitude of bias
current in all of the analog sections and the pull-up
current for the SHUTDOWN and RESET pins. The
current flowing in the bias resistor is nominally
15 J..lA.
REFERENCE SECTION
The reference section of the Si9100 consists of a
temperature compensated buried zener and
trimmable divider network. The output of the
reference section is connected internally to the
non-inverting input of the error amplifier. Nominal
reference output voltage is 4.0 V. This
automatically compensates for the input offset
voltage in the error amplifier.
10-21
Si91 00/91 01
.... Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont"d)
The output impedance of the reference section has
been purposely made high so that a low impedance
external voltage source can be used to override the
internal voltage source, if desired, without
otherwise altering the performance of the device.
the logiC section limits switch duty cycle to S50% by
locking the switching frequency to one half of the
oscillator frequency.
Remote synchronization pulse into the OSC IN (pin
8) terminal. For a 5 V pulse amplitude, typical
values would be 1000 pF in series with 10 kn to
pin 8.
Applications which use a separate exteranl
reference,
such as non-isolated converter
topologies and circuits employing optical coupling
in the feedback loop, do not require a trimmed
voltage reference with 1% accuracy. The Si9101
accommodates the requirements of these
applications at alower cost, by leaving the
reference voltage untrimmed. The 10% accurate
reference thus provided is sufficient to establish a
dc bias point for the error amplifier.
SHUTDOWN AND RESET'
SHUTDOWN (pin 11) and RESET (pin 12) are
intended for overriding the output MOSFET switch
via external control logic. The two inputs are fed
through a latch preceding the output switch.
Depending on the logic state of RESET.
SHUTDOWN can be either a latched of unlatched
input. The output is OFF whenever SHUTDOWN is
low. By simultaneously having SHUTDOWN and
RESET low, the latch is set and SHUTDOWN has no
effect until RESET goes high. The truth table for
these inputs is given in Table 1.
ERROR AMPLIFIER
Closed-loop regulation is provided by the error
amplifier, which is intended for use with
"around-the-amplifier" compensation. AMOS
differential input stage provides for low input
current. The non inverting input to the error amplifier
(VREF) is internally connected to the output of the
reference supply and should be bypassed with a
small capacitor to ground.
Both pins have internal current source pull-ups and·
can' be left disconnected when not in use. An
added feature of the current sources is the ability to
connect a capacitor and an open-collector driver to
the SHUTDOWN or RESET pins to provide variable
shutdown time.
OSCILLATOR SECTION
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch.
Frequency is set by an external resistor between
the OSC IN and OSC OUT pins. (See Figure 5 for
details of resistor value vs. frequency.) The
DISCHARGE pin should be tied to -YIN for normal
internal oscillator operation. A frequency divider in
OUTPUT SWITCH
The output switch is a 5 n, 150 V lateral DMOS
device. Like discrete MOSFETs, the switch contains
an intrinsic body-drain diode. However, the body
contact in the Si91 00 is connected internally to -VIN
and is independent of the SOURCE.
Table 1. Truth Table for the SHUTDOWN
and RESET Pins.
SHUTDOWN
H
H
10-22
RESET
H
L
OUTPUT
Normal Operation
Normal Operation
(No Change)
L
H
L
L
OFF (Latched)
..r
L
OFF (Latched)
(No Change)
OFF (Not Latched)
Si91 00/91 01
..,. Sillconix
incorporated
~
APPLICATIONS
BUCK-BOOST
NON-ISOLATED 1 W SUPPLY
GND
Ll
150 I1H
C5
220 j.lF
10 V
=--_@..0.2ADC
_ _..Lo2
C6
0.1 I1F
3
C2
0.1
I1F
Cl
2Ol1F
C3
1.011F
6
R4
3.3 k
Si9101
R8
10 k
1%
R9
10 k
1%
CRl
+5 V
200 mA
Rl0
5k
R5
01
MPSA93
Ul
300 k
C7
0.1
j.l.F
10
R2
10
1/2W
C8
0.1
j.l.F
TL
431C
U2
R6
10 k
4
-48 V
NON-ISOLATED 1 W SUPPLY (BUCK)
GND
2
C5
220 ~F
10
lN5806
CRl
C6
0.1 j.l.F
Ll
R3
150 k
C2
0.1
j.l.F
Cl
2Ol1F
6
C3
1.0 j.l.F
Si9101
R4
3.3 k
Ul
-48 V
10
C8
0.1
I1F
R9
10 k
1%
150 j.l.H
@0.2ADC
14
C7
0.1
j.l.F
R8
10 k
1%
Rl0
5k
R5
III
01
MPSA93
300 k
4
9
-5 V
200 mA
R2
10
1/2W
R6
10 k
TL
431C
U2
-=-
10-23
Si91 00/91 01
...... Siliconlx
incorporated
~
APPLICATIONS (Cant'd)
ONE WATT FLYBACK CONVERTER FOR TELECOMMUNICATIONS POWER SUPPLIES
GND-
~
1.
2
1N5819
.
+5 V
3
0.1 J.l.F
150 J.l.H
20 J.l.F
1
4
5
100 J.l.F
GND
7
0.1 J.l.F
18 k,n
).
1
14
c1
13
tll
..........3.
>390 k,n
4
Si9100
...
" I
240 k,n 0.022 J.l.F
.
-5 V
fll
1N5819
10
5
---.§
9
7
-.JI
=i= 1 J.l.F
== 0.1
1,n
1J2W
8
J.l.F
12 k,n
~~ 1N4148
150 k,n
!
-VIN (-48 VDC)
• For additional information on using the SI9100 in telecommunications and ISDN
power supplies, see AN87-1 and AN87-2.
DUAL-IN-LINE BURN-IN CIRCUIT
+70 V
+120 V
+10
10-24
v o-----1I--'W.......-I
NOTES:
22 J.l.F
1.
2.
3.
4.
5.
6.
=
R1 390 k.o.. 1/4W
R 2 & R 3 = 1 k.o. , 2 W
R4 = 100.0.. 114 W
R5=330k.o.. 1/4W
F 1 • F2 = 1/16 A
C1
0.1 JLF. 50 V
=
Si91 00/91 01
..... Siliconix
incorporated
~
PLCC BURN-IN CIRCUIT
70 V
NOTES:
120 V
1. R 1 = 390 kn • 1/4 W
2. R 2 & R 3 = 1 kn , 2 W
3.R4=100n.1I4W
4. R5=330kn.1/4W
5. Fl' F2 = 1/16 A
6. C 1 =0.lJ.1.F,50V
10 V
10-25
W'JP'" Siliconix
Si9102
1-Watt, High-Voltage
Switch mode Regulator
~
FEATURES
APPLICATIONS
• 10 to 120 V Input Range
• ISDN Terminals
• Current-mode Control
• PBX Equipment
• On chip 200 V, 7.n
· MOSFET Switch
• Modems
,
• Feature Telephones
• SHUTDOWN and RESET
Function
• DC/DC Converters
incorporated
• Distributed Power Systems
• High Efficiency Operation
(> 80%)
• Internal Start-up Circuit
• Internal Oscillator
(up to 1 MHz)
DESCRIPTION
The Si9102 high-voltage switchmode regulator is a
monolithic D/CMOS integrated circuit which
contains most of the components necessary to
implement a 1-watt, high-efficiency dc to dc
converter. It can either be operated from a
low-voltage dc supply, or directly from a 10 to
1'20 V unregulated dc power source.
SHUTDOWN and RESET logic inputs, and external
clock synchronization. This device may be used
with an appropriate transformer to implement most
single ended isolated power converter topologies
(i.e., flyback and forward), or by using an external
reference can generate a +5 V non-isolated output
from a -10 to -96 V source.
The switchmode regulator subsystem includes
high-voltage start-up circuitry, oscillator, voltage
reference, current-mode PWM circuitry and a
high-speed, 200 V, 7 .n MOSFET switch. Additional
features
include
primary
current
sense,
The Si9102 is available in 14-pin plastic, CerDIP and
20-pin PLCC packages, and is specified over the
military, A suffix (-55 to 125°C) and industrial, 0
suffix (-40 to 85°C) temperature ranges.
PIN CONFIGURATION
PLCC Package
Dual-In-Llne Package
3
2
1
20
FUNCTION
19
14
2
13
4
18
3
12
5
17
4
11
S
lS
5
10
7
15
6
9
8
14
7
8
9
TopVlaw
Order Numbers:
Plastic: 519102AJ
CerDIP: 519102DK
10-26
10
11
12
13
Top View
Order Number:
Plastic: 519102DN
14-pln DIP
Pin #
PLCC-20'
Pin #
BIAS
+VIN
DRAIN
SOURCE
-VIN
vcc
OSC OUT
OSCIN
DISCHARGE
vREF
SHUTDOWN
RESET
COMP
FB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
• Pins 1, 4, 6, 13, 15 and 19
2
3
5
7
8
9
10
11
12
14
16
17
18
20
= N/C
Si91 02
W'W'" Siliconix
~
incorporated
FUNCTIONAL BLOCK DIAGRAM
FB
eOMP
Error
Amplifier
Q
S
1.2V
To
BIAS
Internal
Circuits
Vee
L------------+--+------------f
MINbMA~
UNIT
REFERENCE
Output Voltage
Output Impedance
1
4.0
V
1
30
k.O.
1
100
.I1A
2,3
1
mV'·C
Rose = 0
1
3
1
See Note e
1
100
80
9.5 V S Vee S = 13.5 V
1
±3
0/0
2,3
500
ppm'·C
FB Tied to COMP
(See Detailed Description
Reference Section)
1
4.00
VFS= 4.0 V
1
25
1
80
1
1
M,Hz
1
50
k.O.
Source
VFS= 3.4 V
1
2.0
1.4
1.4
Sink
V FS = 4.5 V
1
0.15
.12
.12
9.5 V S VeeS = 13.5 V
1
70
ZOUT
Short Circuit Current
VREF= -VIN
Temperature Stability
OSCILLATOR
Maximum Frequency
fose
Initial Accuracy
Voltage Stability
Vase
Temperature Coefficient
1
120
80
MHz
120
kHz
ERROR AMPLIFIER
Feedback Input Voltage
VFB
Input BIAS Current
Open Loop Voltage Gain
AVOL
Unity Gain Bandwidth
Output Impedance
Output Current
Power Supply Rejection
10-28
ZOUT
3.96
4.04
3.96
500
60
60
V
500
nA
dB
mA
lOUT
PSRR
4.04
dB
~
~
Si91 02
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
Test Conditions
LIMITS
Unless Otherwise Specified:
1=25·C
A
D
DISCHARGE = -VIN = 0 V
2=125,85·C
SUFFIX
SUFFIX
Vcc= 10 V, +VIN = 48 V
3=-55,-40·C -55 to 125°C -40 to 85°C
RBIAS = 390 k.O.
Rose = 330 k.O.
TEMP TYpd MINb MAX' MIN b MAXi UNIT
SYMBOL
CURRENT LIMIT
VSOURCE
RL= 100.0. from DRAIN toVcc
VFB= 0 V
1
1.2
td
RL= 100.0. from DRAIN toVcc
V SOURCE = 1.4 V, See Figure 1
1
150
Input Voltage
+VIN
liN = 100JJ.A
Input Leakage Current
+IIN
Threshold Voltage
Delay to Output
1.0
1.4
1.0
1.4
V
200
200
ns
1
120
120
V
Vcc l!: 9.4 V
1
10
10
JJ.A
I PREREGuLATOR = 10 JJ.A
1
8.6
9.4
9.4
RL = 100.0. from DRAIN toVcc
(See Detailed Description)
1
8.1
8.9
8.9
Icc
1
0.6
1.0
1.0
I BIAS
1
15
1
50
PREREGULATORISTARTUP
Vcc Preregulator Turn-OFF
Threshold Voltage
V
Undervoltage Lockout
SUPPLY
Supply Current
Bias Current
rnA
JJ.A
LOGIC
SHUTDOWN Delay
tSD
SHUTDOWN Pulse Width
tsw
VSOURCE = -VIN
See Figure 2
1
100
50
100
50
ns
RESET Pulse Width
tRW
Latching Pulse Width
SHUTDOWN and RESET
LOW
1
50
50
tLW
1
25
25
Input LOW Voltage
VIL
1
Input HIGH Voltage
VIH
1
Input Current
Input Voltage HIGH
IIH
VIN = 10 V
1
1
5
5
Input Current
Input Voltage LOW
IlL
VIN=OV
1
-25
-35
-35
See Figure 3
2.0
2.0
V
8.0
8.0
JJ.A
10-29
Si9102
.... Siliconix
.,6;/1 incorporated
El.ECTRICAl. CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
DISCHARGE = -VIN = 0 V
Vcc= 10V, +VIN =48V
R BIAS = 390 k.O.
ROSC = 330 k.O.
LIMITS
1=25·C
A
2=125,85·C
SUFFIX
3=-55,-40·C -55 to 125°C
0
SUFFIX
-40 to 85°C
TEMP TYpd MINb MAX' MIN b MAXI UNIT
MOSFET SWITCH
Breakdown Voltage
V(BR)DSS
V SOURCE = V SHUTDOWN = 0 V
I DRAIN = 100 J1A
2,3
220
Drain-Source ON
ResistanceS
rDS(ON)
VSOURCE= 0 V
I DRAIN = 100 mA
1
5
Drain OFF Leakage Current
IDSS
V SOURCE = V SHUTDOWN = 0 V
V DRAIN = 100 V
1
Drain Capacitance
CDS
V SOURCE = V SHUTDOWN = 0 V
1
200
200
V
7
7
.0.
10
10
J1A
250
pF
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum, Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Temperature coefficient of rDS(ON) Is 0.75% per ·C, typical.
f. CSTRAY Pin 8 = 0 pF.
TIMING WAVEFORMS
1.4 VSOURCE
VCC
SHUTDOWN
o
VC~~
DRAIN
o
~
Vcc DRAIN
o
10%
SD
10%
Figure 2
Figure 1
VCC---_
S::::H'::'U~T=DO""W=-N'
oVCC _ _ _ _ _ _ ___
RESET
o-
Figure 3
10-30
tF s 10 ns
o-
Si9102
..... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
Output Switching Frequency vs. Oscillator
Resistance
+VIN vs. +IIN at Startup
140
1M
120
Vee = -YIN
1'0.
I
100
I
80
+VIN
(V) 60
(Hz)
I
40
1/
20
o
fOUT 100 K
J
'"
V
i -~ ~
10 K
10
15
10 k
20
+IIN (mA)
100 k
1M
rOS(ON)
(.0.)
Figure 5
FIgure 4
DETAILED DESCRIPTION
PREREGULATORISTARTUP SECTION
Due to the low quiescent current requirement of the
Si9102 control circuitry, bias power can be supplied
from the unregulated input power source, from an
external regulated low-voltage supply, or from an
auxiliary "bootstrap" winding on the output inductor
or transformer.
When power is first applied during startup, +YIN
(pin 2) will draw a constant current. The magnitude
of this current is determined by a high-voltage
depletion MOSFET device which is connected
between +YIN and Vee (pin 6). This startup circuitry
provides initial power to the Ie by charging an
external bypass capacitance connected to the Vee
pin. The constant' current is disabled when'Vee
exceeds 8.6 V. If Vee is not forced to exceed the
8.6 V threshold, then Vee will be regulated to a
nominal value of 8.6 V by the preregulator circuit.
As the supply voltage rises toward the normal
operating conditions, an internal undervoltage (UV)
lockout circuit keeps the output MOSFET disabled
until Vee exceeds the undervoltage lockout
threshold (typically 8.1 V). This guarantees that the
control logic will be functioning properly and that
sufficient gate drive voltage is available before the
MOSFET turns ON. The design of the Ie is such that
the undervoltage lockout threshold will not exceed
the preregulator turn-off voltage. Power dissipation
can be minimized by providing an external power
source to Vee such that the constant current source
is always disabled.
NOTE: During startup or when Vee drops below
8.6 V the startup circuit is capable of sourcing up to
20 rnA. This may lead to a high level of power
dissipation in the Ie (for a '96 V input, approximately'
2 W). Excessive start u'p time can result in device
damage. See Figure 4 for calculation of power
dissipation during start up.
BIAS
To properly set the bias for the Si9102, a 390 kll
resistor should be tied from BIAS (pin 1) to -VIN
(pin 5). This determines the magnitude of bias
current in all of the analog sections and the pull-up
current for the SHUTDOWN and RESET pins. The
current flowing in the bias resistor is nominally
15/lA.
REFERENCE SECTION
The reference section of the Si9102 consists of a
temperature compensated buried zener and
trimmable divider network. The output of the
10-31
Si9102
..... Siliconix
incorporated
~
DETAILED DESCRIPTION
reference section is connected internally to the
non-inverting input of the error amplifier. Nominal
reference output voltage is 4.0 V. The trimming
procedure that is used on the Si9102 brings the
output of the error amplifier (which is configured for
unity gain during trimming) to within ±1% of 4.0 V.
This automatically compensates for the input offset
voltage in the error amplifier.
The output impedance of the reference section has
been purposely made high so that a low impedance
external voltage source can be used to override the
internal voltage source, if desired, without
otherwise altering the performance of the device.
ERROR AMPLIFIER
Closed-loop regulation is provided by the error
amplifier, which is intended for use with
"around-the-amplifier" compensation. AMOS
differential input stage provides for low input
current. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the
reference supply and should be bypassed with a
small capacitor to ground.
SHUTDOWN AND RESET
SHUTDOWN (pin 11) and RESET (pin 12) are
intended for overriding the output MOSFET switch
via external control logic. The two inputs are fed
through a latch preceding the output switch.
Depending on the logic state of RESET.
SHUTDOWN can be either a latched of unlatched
input. The output is OFF whenever SHUTDOWN is
low. By simultaneously having SHUTDOWN and
RESET low, the latch is set and SHUTDOWN has no
effect until RESET goes high. The truth table for
these inputs is given in Table 1.
80th pins have internal current source pull-ups and
can be left disconnected when not in use. An
added feature of the current sources is the ability to
connect a capacitor and an open-collector driver to
the SHUTDOWN or RESET pins to provide variable
shutdown time.
Table 1. Truth Table for the SHUTDOWN
and RESET Pins.
SHUTDOWN
RESET
H
H
OUTPUT
OSCILLATOR SECTION
Normal Operation
The oscillator consists of a ring of CMOS Inverters,
capacitors, and a capacitor discharge switch.
Frequency is set by an external resistor between
the OSC IN and OSC OUT pins. (See Figure 5 for
details of resistor value vs. frequency.) The
DISCHARGE pin should be tied to -VIN for normal
internal oscillator operation. A frequency divider in
the logic section limits switch duty cycle to S50% by
locking the switching frequency to one half of the
oscillator frequency.
OUTPUT SWITCH
Remote synchronization can be accomplished by
capacitive coupling of a SYNCHRONIZATION pulse
into the OSC IN (pin 8) terminal. For a 5 V pulse
amplitude, typical values would be 1000 pF in series
with 10 kn to pin 8.
The output switch is a 7 n, 200 V lateral DMOS
device. Like discrete MOSFETs, the switch contains
a~ intrinsic body-drain diode. However, the body
contact in the Si9102 is connected internally to -VIN
and is independent of the SOURCE.
10-32
H
L
Normal Operation
(No Change)
L
H
OFF (Not Latched)
L
L
OFF (Latched)
L
OFF (Latched)
(No Change)
S
Si9102
tI'Y' Siliconix
~
incorporated
APPLICATIONS
FLYBACK CONVERTER FOR DOUBLE BATTERY TELECOMMUNICATIONS POWER SUPPLIES
+VIN
GND
lN5819
100 J1.H
+5 V
2l.
20 J1.F
0.1 J1.F
300 J1.H
1
r
4
5
100 J1.F
GND
7l
0.1 J1.F
18 k,(l
~
390 k,(l
1
14
~
13
----..3.
ell
Si9102
4
•
.. I
240 k,(l 0.022 J1.F
.
11
5
10
~
9
1-
rJI
-5 V
lN5819
:= 1 J1.F
:1= 0.1
1,(l
1f2W
8
22 J1.F
J1.F
12 k,(l
2~ lN4148
150 k,(l
!
-VIN (-96 VDC)
DUAL-IN-LINE BURN-IN CIRCUIT
TopVlaw
120 V
200 V
NOTES:
R 1 = 390 k.o.. 1/4 W
R2
= 1 k.o..
2W
R3 = 1 k.o.. 2 W
10
v O---I--'W.......-I
R4
= 100 .0..
1/4 W
Rs = 330 k.o.. 1/4 W
C 1 = 0.1 J1F. 50 V
10-33
Si91 02
..... Siliconix
.,6;/1 incorporated
PLCC BURN-IN CIRCUIT
120 V
NOTES:
R1
R2
R3
200 V
R4
R5
= 390 k.n.. 1/4 W
= 1 k.n.. 2 W
= 1 k.n.. 2 W
= 100 .0.. 1/4 W
= 330 k.n. • 114 W
C 1 = O.l.11F. 50 V
10V
10-34
tI"F'
~
Si9110/9111
High-voltage
Switchmode Controllers
Siliconix
incorporated
FEATURES
II
APPLICATIONS
10 to 120 V Input Range
• Current-mode Control
II
High-Speed, Source-Sink
Output Drive
• High Efficiency Operation
(> 80%)
• DC/DC Converters
• Distributed Power Systems
• ISDN Equipment
• PBX Equipment
• Modems
• Internal Start-up Circuit
• Internal Oscillator
(up to 1 MHz)
ClI
Reference Selection
Si9110 - ±1%
Si9111 - ±10%
DESCRIPTION
The Si9110/9111 are D/CMOS integrated circuits
designed for use as high-performance switchmode
controllers. A high-voltage DMOS input allows the
controller to work over a wide range of input
voltages (10- to 120-VDC). Current-mode PWM
control circuitry is implemented in CMOS to reduce
internal power consumption to less than 10 mW.
time for fault protection. A push-pull output driver
provides high-speed switching for MOSPOWER
devices large enough to supply 50 W of output
power. When combined with an output MOSFET and
transformer, the Si911 0 or Si9111 can be used to
implement most single-ended power converter
topologies (i.e., flyback and forward).
The on-chip oscillator frequency is set by an
external resistor, and can be easily synchronized to
an external system clock. SHUTDOWN and RESET
inputs allow external logic control, and these inputs
can also be used to provide a variable shutdown
The Si9110 and Si9111 are available in 14-pin
plastic, SO-IC and CerDIP packages, and are
specified over the military, A suffix (-55 to 125°C)
and industrial, 0 suffix (-40 to 85°C) temperature
ranges.
PIN CONFIGURATION
Dual-In-Line Package
SO Package
14
13
12
11
10
9
8
(Same pinout as Dual-in-Line)
1234567
Top View
Order Numbers:
Top View
Order Numbers:
81911 OOY, 5191110Y
CerOIP: 519110AK, 519111AK
Plastic: 51911 OOJ. 519111DJ
10-35
Si9110/9111
.... Siliconix
incorporated
~
FUNCTIONAL BLOCK DIAGRAM
FB
eOMP
ose
OUT
'l$
13
14
ose
IN
DISCHARGE
Error
Amplifier
VREF
ose)
To
Vee
Q
OUTPUT
s
-V IN
1.2V
To
BIAS
Vee
Internal
3
SENSE
6
Undervoltage
Comparator
+VIN
11
12
SHUTDOWN
RESET
Pre-regulator/Startup
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN
Junction Temperature (T J) ••..•.•.•.....••••... 150·C
Vee •.•..•••..•......••••...••.........•....• 15.0 V
Power
14-Pln
14-Pln
14-Pln
+VIN •....•.•...••.••.........••••..•...••..• 120 V
Logic Inputs (RESET,
SHUTDOWN, OSC IN) •.....•.•.. -0.3 V to Vee + 0.3 V
Linear Inputs
(FEEDBACK, SENSE) ................. -0.3 V to 7.0 V
HV Preregulator Input Current (continuous) ......•. 3 mA
Storage Temperature (A, 0 Suffix) ...•.... -65 to 150·C
Operating Temperature (A Suffix) ......... -55 to 125·C
(0 Suffix) .......... -40 to 85·C
10-36
Dissipation (Package)"
Ceramic DIP (K Suffix)"" ••...••••..••. 1000 mW
Plastic DIP (J Suffix)""" .•............. 750 mW
SO-IC (V Suffix)"""" ••...•..•.....•... 800 mW
Thermal Impedance (8JA )
14-Pln Ceramic DiP •..•.•...•..••........... 100·C/W
14-Pln Plastic DIP .•.........•.•....•....... 167·C/W
14-Pln SO-IC ...•..•.........•.•••....•••.. 140·C/W
Device mounted with all leads soldered or welded
to PC board.
Derate 10 mW/·C above 50·C
Derate 6 mW/·C above 25·C
"""" Derate 7 mW/·C above 25·C
Si9110/9111
trY" Siliconix
~
incorporated
ELECTRICAL CHARACTERISTICS a
PARAMETER
SYMBOL
Test Conditions
Unless Otherwise Specified:
DISCHARGE = -VIN = 0 V,
Vcc=10V,+V IN=4BV
R BIAS = 390 k.rl.
Rose= 330 k.rl.
VR
RL = 10 Mn.
(See Detailed Description)
LIMITS
1=25°C
A
2=125,85°C
SUFFIX
3=-55,-40°C -55 to 125°C
0
SUFFIX
-40 to 85°C
TEMP TYpd MINb MAX' MIN b MAxt
UNIT
REFERENCE
Output Voltage
Output Impedance
1
4.0
V
1
30
k.rl.
1
100
J,LA
2,3
1
mV/OC
Rose = 0
1
3
1
See Note e
1
100
BO
9.5 V S Vee S = 13.5 V
1
±3
%
2,3
500
ppm/DC
1
4.00
ZOUT
Short Circuit Current
V REF = -VIN
Temperature Stability
OSCILLATOR
Maximum Frequeney
fose
Initial Accuracy
Voltage Stability
Vase
Temperature Coefficient
1
120
BO
MHz
120
kHz
ERROR AMPLIFIER
FB Tied to COMP
Feedback Input Voltage
V FB
SI9110
Output Current
Power Supply Rejection
4.04
3.96
4.00
1
25
1
BO
1
1
MHz
1
50
k.rl.
Source
V FB = 3.4 V
1
2.0
1.4
1.4
Sink
V FB = 4.5 V
1
0.15
.12
.12
9.5 V S VeeS = 13.5 V
1
70
AvoL
ZOUT
3.60
4.40
3.60
500
60
4.40
500
60
nA
dB
mA
lOUT
PSRR
4.04
1
SI9111
Unity Gain Bandwidth
Output Impedance
3.96
V
V FB = 4.0 V
Input BIAS Current
Open Loop Voltage Gain
See
Detailed Description
Reference Section
dB
10-37
~
~
Si9110/9111
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
Test Conditions
LIMITS
Unless Otherwise Specified:
1=25°C
D
A
DISCHARGE -¥IN 0 V
2=125,85°C
SUFFIX
SUFFIX
Vec= 10 V, +VIN = 48 V
3=-55,-40 o C -55 to 125°C -40 to 85°C
RBIAS = 390 k.O.
Rosc = 330 k.O.
TEMP TYpd MINb MA>f MINb MAX
SYMBOL
=
PARAMETER
=
UNIT
CURFlENT' LIMIT
Threshold Voltage
VFB= 0 V
VSOURCE
Delay to Output
td
VSENSE
=1.4 V, See Figure 1
1.4
V
150
150
ns
1
120
120
V
10
10
J.lA
1
1.2
1
100
1.0
1.4
1.0
PREREGULATORfSTARTUP
=10J1A
Input Voltage
+VIN
liN
Input LeakagB Current
+IIN
Vcc 2: 9.4 V
1
I PREREGULATOR = 10 J.lA
1
8.6
9.4
9.4
I OUTPUT = 1 rnA
(See Detailed Description)
1
8.1
8.9
8.9
Icc
1
0.6
1.0
1.0
ISlAS
1
15
1
50
Vcc Preregulator Turn-OFF
Threshold Voltage
V
Undervoltage Lockout
SUPPLY
Supply Current
Bias Current
mA
J.lA
LOGIC
SHUTDOWN Delay
tSD
SHUTDOWN Pulse Width
tsw
RESET Pulse Width
tRW
Latching Pulse Width
SHUTDOWN and RESET
LOW
C L=500pF
VSENSE = -VIN
See Figure 2
100
100
1
50
50
1
50
50
tLW
1
25
25
Input LOW Voltage
V IL
1
Input HIGH Voltage
VIH
1
Input Current
,Input Voltage HIGH
IIH
VIN = 10 V
1
1
5
5
'Input Current
Input Voltage LOW
IlL
VIN = 0 V
1
-25
-35
-35
ns
See Figure 3
2.0
2.0
V
8.0
8.0
J.lA
10-38
Si9110/9111
Siliconix
incorporated
ELECTRICAL CHARACTERISTICS a
SYMBOL
Test Conditions
Unless Otherwise Specified:
DISCHARGE = -VIN = 0 V
Vee= 10 V. +VIN = 48 V
R BIAS = 390 k.O.
Rose = 330 k.O.
Output HIGH Voltage
VOH
IOUT=lmA
1
2,3
Output LOW Voltage
VOL
lOUT = -1 mA
1
2,3
PARAMETER
LIMITS
1_25°C
A.
2=125.85°C
SUFFix
3=-55.-40°C -55 to 125°C
TEMP TYpd
D
SUFFIX
-40 to 85°C
MINb MAX' MIN b MAXt UNIT
OUTPUT
9.90
9.75
9.90
9.75
V
Ouput Resistance
ROUT
Rise Time
tr
0.10
0.25
0.10
0.25
1
2,3
20
25
30
50
30
35
1
40
75
75
1
40
75
75
CL = 500 pF
Fall Time
.n.
ns
tf
NOTES:
a. Refer to PROCESS OPTION FLOWCHART for additional Information.
b. The algebraic convention whereby the most negative value Is a minimum and the most positive a maximum. Is used In
this data sheet.
c. Guaranteed by design, not subject to production test.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. CSTRAY Pin 8 = 0 pF.
TIMING WAVEFORMS
1.4 V-
Vee
""S""H""U""T""D""O""W"""N
SENSE
o
0-
Vee-----..t
Vee-----..J
OUTPUT
OUTPUT
0-
0Figure 1
Figure 2
Isw
V e e - -_ _"'"
SHUTDOWN
o-
50%
50%
Vee _ _ _ _ _ _ _....
RESET
o-
50%
Figure 3
10-39
Si9110/9111
..... Siliconix
incorporated
~
TYPICAL CHARACTERISTICS
+V IN
VS.
Output Switching Frequency vs. Oscillator
Resistance
+IIN at Startup
140
1M
120
Vcc- -VIN
100
~
80
+VIN
fOUT 100 K
J
(V) 60
(Hz)
V
40
20
o
,
II
1- ~ ~
10
V
15
+IIN (rnA)
""
10 K
10 k
20
"
100 k
1M
rOS(ON)
(.0.)
Figure 5
Figure 4
DETAILED DESCRIPTION
PREREGULATORISTARTUP SECTION
Due to the low quiescent current requirement of the
Si9110fSi9111 control circuitry, bias power can be
supplied from the unregulated input power source,
from an external regulated low-voltage supply, or
from an auxiliary .. bootstrap" winding on the output
inductor or transformer.
When power is first' applied during startup, +YIN
(pin 2) will draw a constant current. The magnitude
of this current is determined by a high-voltage
depletion MOSFET device which is connected
between +VIN and Vee (pin 6). This startup circuitry
provides initial power to the Ie by charging an
external bypass capacitance connected to the Vee
pin. The constant current is disabled when Vee
exceeds 8.6 V. If Vee is not forced to exceed the
8.6 V threshold, then Vee will be regulated to a
nominal value of 8.6 V by the preregulator circuit.
As the supply voltage rises toward the normal
operating conditions, an internal undervoltage (UV)
lockout circuit keeps the output MOSFET disabled
until Vee exceeds the undervoltage lockout
threshold (typically 8.1 V). This guarantees that the
control logic will be functioning properly and that
sufficient gate drive voltage is available before the
10-40
MOSFET turns ON. The design of the Ie is such that
the undervoltage lockout threshold will not exceed
the preregulator turn-off voltage. Power dissipation
can be minimized by providing an external power
source to Vee such that the constant current source
is always disabled.
NOTE: During startup or when Vee drops below
8.6 V the startup circuit is capable of sourcing up to
20 mAo This may lead to a high level of power
dissipation in the Ie (for a 48 V input, approximately
1 W). Excessive start up time can result in device
damage. See Figure 4 for calculation of power
dissipation during start up.
.
BIAS
To properly set the bias for the Si911 OfSi9111, a
390 kll resistor should be tied from BIAS (pin 1) to
-VIN (pin 5). This determines the magnitude of bias
current in all of the analog sections and the pull-up
current for the SHUTDOWN and RESET pins. The
current flowing in the bias resistor is nominally
15 )J.A.
REFERENCE SECTION
The reference section of the Si911 0 consists of a
temperature compensated buried zener and
trimmable divider network. The output of the
Si9110/9111
...... Siliconix
incorporated
~
DETAILED DESCRIPTION (Cont'd)
reference section is connected internally to the
non-inverting input of the error amplifier. Nominal
reference output voltage is 4.0 V. The trimming
procedure that is used on the Si9110 brings the
output of the error amplifier (which is configured for
unity gain during trimming) to within ±1% of 4.0 V.
this automatically compensates for input offset
voltage in the error amplifier.
The output impedance of the reference section has
been purposely made high so that a low impedance
external voltage source can be used to override the
internal voltage source, if desired, without
otherwise altering the performance of the device.
Applications which use a separate exteranl
reference,
such
as
non-isolated converter
topologies and circuits employing optical coupling
in the feedback loop, do not require a trimmed
voltage reference with 1% accuracy. The Si9101
accommodates the requirements
of these
applications at alower cost, by leaving the
reference voltage untrimmed. The 10% accurate
reference thus provided is sufficient to establish a
DC bias point for the error amplifier.
ERROR AMPLIFIER
Closed-loop regulation is provided by the error
amplifier, which is intended for use with
"around-the-amplifier" compensation. AMOS
differential input stage provides for low input
current. The noninverting input to the error amplifier
(VREF) is internally connected to the output of the
reference supply and should be bypassed with a
small capacitor to ground.
OSCILLATOR SECTION
The oscillator consists of a ring of CMOS inverters,
capacitors, and a capacitor discharge switch.
Frequency is set by an external resistor between
the OSC IN and OSC OUT pins. (See Figure 5 for
details of resistor value vs. frequency.) The
DISCHARGE pin should be tied to -VIN for normal
internal oscillator operation. A frequency divider in
the logic section limits switch duty cycle to :550% by
locking the switching frequency to one half of the
oscillator frequency.
Remote synchronization pulse into the OSC IN (pin
8) terminal. For a 5 V pulse amplitude, typical
values would be 1000 pF in series with 10 kn to
pin 8.
SHUTDOWN AND RESET
SHUTDOWN (pin 11) and RESET (pin 12) are
intended for overriding the output MOSFET switch
via external control logic. The two inputs are fed
through a latch preceding the output switch.
Depending on the logic state of RESET.
SHUTDOWN can be either a latched of unlatched
input. The output is OFF whenever SHUTDOWN is
low. By simultaneously having SHUTDOWN and
RESET low, the latch is set and SHUTDOWN has no
effect until RESET goes high. The truth table for
these inputs is given in Table 1.
Both pins have internal current source pull-ups and
can be left disconnected when not in use. An
added feature of the current sources is the ability to
connect a capacitor and an open-collector driver to
the SHUTDOWN or RESET pins to provide variable
shutdown time.
Table 1. Truth Table for the SHUTDOWN
and RESET Pins.
RESET
OUTPUT
H
H
Normal Operation
H
"l....
Normal Operation
(No Change)
L
H
OFF (Not Latched)
L
L
OFF (Latched)
L
OFF (Latched)
(No Change)
SHUTDOWN
S
OUTPUT SWITCH
The push-pull driver output has a typical ON
resistance of 20 n. Maximum switching times are
specified at 75 ns for a 500 pF load. This is
sufficient to directly drive MOSFETs such as the
2N7oo4, 2N7oo5, IRFD120 and IRFD22o. Larger
devices can be driven, but switching times will be
longer, re:}ulting in higher switching losses. In order
to drive large MOSPOWER devices, it is necessary
to use an external driver IC, such as the Siliconix
D469. the D469 can switch very large devices such
as the SMM20N5o (500 V, 0.3 .11) in approximately
100 ns.
10-41
'!:Si9110/9111
tr'F' Siliconix
,,1;11 incorporated
APPLICATIONS
5-WATT POWER SUPPLY FOR TELECOM APPLICATIONS
1N5822
r·~----~~------~----<>~V
GNDo-----~------------------------~----------------__,
@0.75A
OSC SYNC
PULSE
::rro
220J,LF
l
1000 pF
0.1
•
J,LF
1N5819
' - - - - - : M - - - - 4 - - - 0 -5 V
@0.25 A
6
Si9110
4
2N7004
r __*'__1"____-,-"10'-V"-l~ TO PIN 6
18 k
1J,LF
3
0.1
J,LF
9
12 k
1.n.
1/2 W
-48 V
BURN-IN CIRCUIT
+120 V
NOTES:
+10
v
o-----+-'\J'Vv-l
R1 = 390 k.n.. 1/4 W
R2 =lk.n.,2W
R3 =lk.n.,2W
R4 = 100.n., 1/4 W
R5 = 330 k.n.. 1/4 W
C 1 =0.1J.LF,50V
10-42
FEEDBACK
TO PIN 14
Si911S/9116
Off-Line
Switchmode Controllers
...... Siliconix
incorporated
~
FEATURES
APPLICATIONS
• 10 to 300 V Input Range
• Off-Line Switch mode Power
Supplies
• Current-Mode Control
• High-Speed, Source-Sink
Output Drive
• Housekeeping Power
Supplies
• SHUTDOWN and RESET
Functions
• Distrubuted Power Systems
• High Efficiency Operation
(> 80%)
• Internal Start-Up-Circuit
II
Internal Oscillator
(Up to 1 MHz)
DESCRIPTION
The Si9115 and Si9116 are D/CMOS integrated
circuits designed for use as high-performance
switch mode controllers. High-voltage DMOS inputs
allow the controllers to work over a wide range of
input voltages (10 to 300 VDC). Current-mode PWM
control circuitry is implemented in CMOS to reduce
quiescent current to less than 1 mAo
The on-chip oscillator frequency is set by an
external resistor, and can easily be synchronized to
an external system clock. SHUTDOWN and RESET
inputs allow external logic control, and these inputs
can also be used to provide a variable shutdown
time for fault protection. A push-pull output driver
provides high-speed switching for MOSPOWER
devices large enough to supply 50 W of output
power. These devices, when combined with an
output MOSFET and transformer, can be used to
implement most single-ended power converter
topologies (i.e., flyback and forward).
The Si9116 provides an inverted polarity output to '
facilitate interfacing to a high current MOSFEt
driver stage.
The Si9115 and Si9116 are available in 16-pin
plastic DIP and SOIC packages, and are specified
over the industrial, D suffix (-40 to 85°C)
temperature range.
PIN CONFIGURATION
Dual-In-Llne Package
BIAS
SO Package
FB
COMP
RESET
SHUTDOWN
DISCHARGE
Top View
(Same pinout as DIP)
1 2 3 4 5 678
Top View
Order Numbers:
S19115DY, SI9116DY
Order Numbers:
Plastic: Si9115DJ, SI9116DJ
Preliminary
10-43
Si9115/9116
Siliconix
incorporated
FUNCTIONAL BLOCK DIAGRAM
To
Vee
eOMP
FB
14
15
ose ose
IN
OUT
~ S19116
I
Error
I
I
I
I
I
I
I
Amplifier
OUTPUT
6
-V IN
Sl9115
OUTPUT
6
BIAS
16
To
Internal
elrcull. ~--------------------t-~r---------~~------~4~SENSE
Vee
7
b--
1-----
D
tpdHL
t pdLH
11-6
8 ns
2.8 ns
tpdHL
t pdLH
6 ns
6.8 ns
XQ
~
~
IS05
Silicon Ix
incorporated
IS05 TYPICAL MACROS* (Cont'd)
Inverting Balanced Output Buffer
Schmitt Trigger with TTL Input
-----I~>--- o
o
t pdHL
t pdLH
* Fanout
=
=
t pdHL = 3.5 ns
t pdLH
13.5 ns
1.0 ns
1.5 ns
=
=0
IS05 MACRO LIBRARY
MACRO
NAME
FUNCTION
# OF NA2
EQUIVALENTS
GATES
NA2
NA3
NA4
NA5
NA6
N02
N03
N04
XO
XOS
XN
XNS
2-lnput NAND Gate
3-lnput NAND Gate
4-lnput NAND Gate
5-lnput NAND Gate
6-lnput NAND Gate
2-lnput NOR Gate
3-lnput NOR Gate
4-lnput NOR Gate
Exclusive OR
Exclusive OR with SAB Structure
Exclusive NOR
Exclusive NOR with SAB Structure
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
1.5
2.5
1.5
COMPLEX GATES
AN1
AN2
AN3
AN4
AN5
AN6
ON1
ON2
ON3
ON4
ON5
ON6
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
OR-NAND
OR-NAND
OR-NAND
OR-NAND
OR-NAND
OR-NAND
2/1
2/2
2/111
3/2
3/3
2/2/2
2/1
2/2
2/111
3/2
3/3
2/2/2
1.5
2.0
2.0
2.5
3.0
3.0
1.5
2.0
2.0
2.5
3.0
3.0
Single Inverter
Double Inverter
Triple Inverter
FUNCTION
IN4
IN5
IN6
IN7
IN8
IN9
101
102
Four Inverters
Five Inverters
Six Inverters
Seven Inverters
Eight Inverters
Nine Inverters
Delay Inverter
Delay Inverter
# OF NA2
EQUIVALENTS
2.0
2.5
3.0
3.5
4.0
4.5
1.5
3.0
FLIP/FLOPS/LATCHES
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF9
FF10
T2
L1
L2
L3
o Flip Flop
(OFF)
OFF with XRESET
OFF with RESET
OFF with XSET
OFF with SET
OFF with XSET & XRESET
OFF with SET & RESET
OFF with XSET. XRESET1 & XRESET2
OFF with XRESET1. XSET1 & XSET2
Toggle FF with XRESET
D-Latch
D-Latch with XRESET
D-Latch with SET
6.0
6.0
6.0
6.0
6.0
7.5
7.5
9.0
9.0
6.0
3.0
3.0
3.0
TRANSMISSION GATES
TGC
TGIO
Transmission Gate Core Cell
Transmission Gate I/O Cell
1.5
110
SINGLE TRANSISTOR DEVICES
INVERTERS
IN1
IN2
IN3
MACRO
NAME
0.5
1.0
1.5
NCHC
NCHIO
PCHC
PCHIO
N-Channel Transistor 55/5
N-Channel Transistor 275/5
P-Channel Transistor 55/5
P-Channel Transistor 275/5
1.0
110
1.0
110
11-7
DI
IS05
Siliconix
incorporated
IS05 MACRO LIBRARY (Cont'd)
MACRO
NAME
# OF NA2
EQUIVALENTS
FUNCTION
INTERFACEISCHMITT TRIGGERS
6.0 + 1/0
lS.0 + 1/0
1 + 1/0
3.0 + 1/0
4.S + 1/0
3.0 + 1/0
S.O + 1/0
4.0 + 1/0
Input Upward Level Shifter CMOS
Input Upward Level Shifter TTL
Output Downward Level Shifter
Schmitt Trigger with TTL Input
Schmitt Trigger w/CMOS Input
Schmitt Trigger w/CMOS Input
Schmitt Trigger w/CMOS Input
Schmitt Trigger w/CMOS Input
LSIUCl
LSIUTl
LSODCl
STl
ST2
ST3
ST4
STS
FUNCTION
OB 1
OB2
OB3
OB4
TSl
TS2
TS3
TS4
Inverting Balanced Output Buffer
Trl-State Output Buffer
Open Draln-N Output Buffer
Open Draln-P Output Buffer
Internal Inverting Trl-State w/Enable
Internal Inverting Trl-State wi Enable Bar
3-State Output Buffer Driver wi Enable
3-State Output Buffer Driver wi Enable Bar
l.S
1.S
4.S
4.S
1.S + 1/0
1/0
1.S + 1/0
1/0
1/0
1.S + 1/0
1.S + 1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1.S
2 to 1 Multiplexer
SAB
Balanced CMOS Input Inv Buffer Core
Balanced CMOS Input Inv Buffer 1/0
Inverter with 6N/lP Ratio
Input Buffer with 6N/lP Ratio
Input Buffer with 3N/l P Ratio
Inverter with 3N/l P Ratio
Inverter with SN/l P Ratio
Input Protection
Input Protection
Input Protection (Corner Device)
Input Protection (Corner Device)
Input Protection (Corner Device)
InputlOutput Buffer
Bidirectional 1/0
Inverting Output Buffer
1/0
1/0
1/0
1/0
MULTIPLEXERS
1/0
IBCl
IBIOl
IPl
IP2
IP3
IP4
IPS
IP
IPB
IPC
IPCA
IPCB
10Bl
10BA
OB
# OF NA2
EQUIVALENTS
MACRO
NAME
OSCILLATORS
OSCQSP
OSCQLP
OSCRC
OSCRCXE
Standard Power Quartz Oscillator
Low Power Quartz Oscillator
RC Oscillator
RC Oscillator with XENABLE
4.S
6.0
3.0
4.S
ANALOG CELLS
ASl
COMPl
OPAMPl
DIFFl
Analog Switch
Comparator
Operational Amplifier
Differential Amplifier
1/0
lS.0
lS.0
9.0
MEMORY CELLS
RAMl
Random Access Memory
3.0
TYPICAL CHARACTERISTICS
MEASURING CIRCUIT
SO
. / -~
40
!
...J
30
I
20
Cl
10
o
0
/
!
Cl
VDD - S V ~
V
-20
ITA= 2S oC
\.
-10
::z: -15
J
o
-S
HV
~
...J
w
0
o
(VOLTS)
SO
~
D..
i.o"~1
pLH
30
,
20
10
Cl
0::
D..
II
III
I
i-"-r;1
~
~r.--'
I
0
o
40
80
120
~
I
rt
160 200
CAPACITANCE - (pC)
11-8
CL
r--....
O.S 1.0 1.S 2.0 2.S 3.0
(VOO-VOH ) - (VOLTS)
III
40
Z
0
......
DD - 5 V I
TA= 25 °c I
PROPAGATION DELAY
vs CAPACITANCE
,s
I
=
-25
O.S 1.0 1.S 2.0 2.S 3.0
VOL -
';;;'
"-~
VIN = VDD IOH
VIN
VSS IOL
RISE & FALL TIME
vs CAPACITANCE
50
';;;'
,s
I
w
::E
F
::l
~
all
w
III
40
30
~ .....
20
IV
10
ii:
0
I~i.o"
o
~
40
II
...
~
IL
... 80
ti
Ll...
t
rall
120 160 200
CAPACITANCE - (pC)
MEASURING CIRCUIT
TA = 25°C
VDD= 5 V
tr ,tt = 1.0 ns
CL
..r Siliconix
~
IS05
incorporated
TYPICAL CHARACTERISTICS
TIMING OIAGRAM
PROPAGATION DELAY
vs SUPPLY VOLTAGE
~
I!:.
I
~
~
15
~
~
a..
200
180
160
140
120
100
80
60
40
20
\
TA= 25 0 C
\
~
\
o
2
4
~
I
~
......
o
PROPAGATION DELAY
vs TEMPERATURE
6
--
c
z
c
~c..
c
a..
0:::
180
160
VDD = 5 V
140
1/
120
;I'
100
",.
80
60 I"'~
40
20
0
d
8 10 12 14 16
-40
Voo - (VO LTS)
0
40
80
TEMPERATURE -
10%
,
1 90 %
I
:
10.5 V
-:tfall l -
I
I
I
:
1- tpHL-1
120
fe)
ANALOG CIRCUITS
OPERATIONAL AMPLIFIER - (OPAMP1)
Typical Electrical Characteristics:
Functional Block Diagram:
0
Test Conditions: VOO= 12 V,TA = 25 C
Parameter
+ INPUT
OUTPUT
-INPUT
Value
Unity Gain Bandwidth
DC Offset
DC Gain
Power Consumption (no signal, no load)
Typical Operating Frequency Range
Typical Supply Voltage Range
Maximum Output Current: Sink (loll
Source (lOH)
Slew Rate
<
8 MHz
15mV
>70 dB
1200 p.W
o to 1 MHz
2.4 to 14 V
1 mA
1 mA
35 VI p's
DIFFERENTIAL AMPLIFIER - (DIFF1)
Functional Block Diagram:
l1li
Typical Electrical Characteristics:
Test Conditions: VOO= 12 V,TA = 25°C
Parameter
+ INPUT
OUTPUT
-INPUT
Value
Maximum operating frequency
8 MHz
DC Offset
15 mV
Power Consumption (no signal, no load)
< 1200 p.W
Typical Supply Voltage Range
2.4 to 14 V
Slew Rate
35 VI p's
11-9
IS05
.... Siliconix
incorporated
~
ANALOG CIRCUITS (Cont'd)
COMPARATOR - (COMP1)
Typical Electrical Characteristics:
Functional Block Diagram:
Test Conditions: VDD= 12 V, TA = 25 0 C
Parameter
Value
VREF
OUTPUT
INPUT
Maximum operating frequency
8 MHz
DC Offset
15mV
Power Consumption (no signal. no load)
< 1200 p.W
Typical Supply Voltage Range
2.4 to 14 V
35 V/p.s
Slew Rate
ANALOG SWITCH - (AS1)
Functional Block Diagram:
Typical Performance Characteristics:
ON RESISTANCE vs DRAIN VOLTAGE
INPUT
OUTPUT
270
ENABLE--
240
rJf'
-
210 .......
~
:c
Q,
180
I
L.J
~
~
z
a
150
--
120
-
90
60
30
o
o
A.
IDS = 1 mA
A:TA = 125°C
B:TA= +25 0 C
C:TA= _55°C
2
I ~
I
I" ~
/ I,...... . /~J / r'
. / 'V/
--"
4
V
6
8
10
DRAIN VOLTAGE - (VOLTS)
11-10
12
14
wr Siliconix
incorporated
1505
~
MEMORY CELLS
MEMORY CELL - (RAM1)
Typical Electrical Characteristics:
0
Test Conditions: VOO= 12 V,TA = 25 C
Functional Block Diagram:
Parameter
INPUT
WS
RAM 1
OUTPUT
Value
Write Settling Time
20 ns
Read-out Time
20 ns
I
•
WS
=Write Select
RS = Read Select
RS
TIMERS - PRECISION TIMER - (555)
Circuit Description:
This precision timer is capable of producing
accurate time delays or frequencies. It is ideal for
applications that require excellent frequency
stability and high supply voltage rejection. In
addition, this timer can be used as a precision
Schmitt trigger or threshold detection circuit.
The threshold levels are set by three external
resistors, R. To achieve minimum voltage
dependency,
the
voltage
supply
of
the
resistor-ladder has been connected to the voltage
supply of the timer. The reset pin, when enabled,
discharges the capacitor and disables the charging
process.
Typical Electrical Characteristics:
0
Test Conditions: Voo= 12 V,TA = 25 C
Parameter
Value
Typical Operating Frequency
o to 4 MHz
Typical Supply Voltage Range
2.4 to 14 V
l:!. f over Operating Range
DC Current, 100
(INl and IN2 at VSS without load)
Operating Temperature Range
<:!:5 %
300 pA to 900 pA
-55 to +125 0 C
11-11
WY'Siliconix
incorporated
1505
~
TIMERS (Cont'd)
FUNCTIONAL BLOCK DIAGRAM
RESET
--,
R1
I
OUTPUT
I
I
I
I
I
I
I
I
R2
C
I
L
-1
VSS
EQUIVALENT GATE COUNT FOR APPROXIMATION OF ARRAY SIZE
DEVICE CELLS
DESCRIPTION
DEVICE CELLS
DESCRIPTION
4000
4001
4002
4006
4007
4008
4011
4012
4013
4014
Dual 3-lnput NOR Gatellnv
Quad 2-lnput NOR Gate
Dual 4-lnput NOR Gate
18-Bit Static Shift Register
Dual Pair + Inverter
4-Bit Full Adder (O.C.)
Quad 2-lnput NAND Gate
Dual 4-lnput NAND Gate
Dual Type D FF Gate
8-Bit Static Shift Reaister
4015
4016
4017
4018
4020
4021
4022
4023
4024
4025
Dual 4-Bit Static Shift Register
Dual Analog Switch/Quad Mult.
Decade Johnson Counter/Divider
Presettable Divide by N Counter
14-Bit Binary Counter
8-Bit Static Shift Register
Octal Counter/Divider
Triple 3-lnput NAND Gate
Seven Stage Ripple Counter
11-12
4
4
3
100
51
4
3
18
53
42
6
34
40
139
80
30
3
45
3
Triele 3-lneut NOR Gate
H
IS05
Siliconix
incorporated
EQUIVALENT GATE COUNT FOR APPROXIMATION OF ARRAY SIZE (Cont'd)
DEVICE CELLS
DESCRIPTION
DEVICE CELLS
4027
4028
24
24
4029
4032
4034
4035
4038
4042
4043
4044
4046
4049
4050
4051
4052
4053
4066
4068
4069
4070
4071
4072
4073
4075
4076
4077
4078
4081
55
46
145
43
45
40
16
16
10
Dual J-K Flip Flop
BCD to Decimal Decoder
Binary/Decade UplDown Counter
Triple Serial Adder (Positive)
8-Bit Universal Bus Register
4-Stage Shift Register
Triple Serial Adder (Negative)
Quad Latch Coder/Driver
Quad NOR R-S Latch
Quad NAND R-S Latch
Phase Locked Loop
Hex Inverter/Buffer
Hex Buffer
8-Channel Analog Multiplexer
4510
4512
4513
4514
4515
4516
74
25
64
68
78
147
4518
4519
4520
4522
4526
4528
70
23
64
74
74
26
Dual BCD Up Counter
4-Bit AND/OR Selector
Dual Binary Up Counter
BCD Divide-by-N Counter
Binary Divide-by-N Counter
Dual Monostable Multivibrator
4529
7400
Dual 4-Channel Analog Multiplexer
Triple 3-Channel Analog Mult.
Quad Bilateral Switch
8-lnput NAND Gate
Hex Inverter
Quad Exclusive OR Gate
7401
7402
7403
7404
7405
7408
7409
7410
7411
7412
38
3
3
4
4
3
3
4
4
3
5
3
Dual 4-Channel Multiplexer
Quad 2-NAND Gate
Quad 2-NAND Gate (O.C.)
Quad 2-NOR Gate
Quad 2-NAND Gate (O.C.)
Hex Inverter
Dual Schmitt Trigger
Hex Schmitt Trigger
3-AND Gate (O.C.)
4082
4093
4094
4099
40160
40161
40162
40163
12
9
93
65
74
74
74
76
40174
40175
86
24
40194
4502
129
8
4503
4504
4508
6
10
33
65
105
24
12
4
8
13
13
15
15
40
8
12
14
6
5
17
DESCRIPTION
BCD UplDown Counter
8-Channel Data Selector
BCD to 7 Seg. LatchlDec.lDriver
4/16 Line Decoder (High)
4/16 Line Decoder (Low)
Binary Up/Down Counter
Hex Inverter
Quad 2-AND Gate
Quad 2-AND Gate (O.C.)
Triple 3-NAND Gate
Triple 3-AND Gate
Triple 3-NAND Gate (O.C.)
Quad 2-lnput OR Gate
Dual 4-lnput OR Gate
Triple 3-lnput AND Gate
Triple 3-lnput OR Gate
Quad D-Type Register
Quad Exclusive NOR Gate
8-lnput NOR Gate
Quad 2-lnput AND Gate
7413
7414
8
24
7415
7420
Dual 4-lnput AND Gate
Quad 2-1 and Schmitt Trigger
8-Stage Shift/Store Register
8-Bit Addressable Latch
7421
7422
7426
7427
5
3
4
3
4
3
Decade Counter
Binary Counter
Decade Counter
Binary Counter
Hex D Flip Flop
7430
7432
7437
7438
3
4
3
3
Quad D Flip Flop
7440
7442
3
26
4-Bit Univ. Shift Register
Strobed Hex Inverter/Buffer
7447
7448
48
51
BCD to Decimal Decoder
BCD/7-Segment Decoder/Driver
BCD/7-Segment DecoderlDriver
Hex Three-State Buffer
Hex Level Shifter
7451
7454
10
9
Dual 2-AND-OR-INV Gate
Quad 2-AND-OR-INV Gate
Dual 4-Bit Latch
7455
5
Dual 4-NAND Gate
Dual 4-AND Gate
Dual 4-NAND Gate (O.C.)
High Volt Quad 2-NAND Gate
Triple 3-NOR Gate
8-lnput NAND Gate •
Quad 2-0R Gate
Quad 2-NAND Buffer
Quad 2-NAND Buffer (O.C.)
Dual 4-NAND Buffer
Dual 4-lnput Gate
11-13
ID
H
1505
Siliconix
incorporated
EQUIVALENT GATE COUNT FOR APPROXIMATION OF ARRAY SIZE (Cont'd)
DEVICE CELLS
DESCRIPTION
7473
7474
7475
7476
7477
7478
7483
7585
7486
74107
74109
74112
74113
74114
74125
74126
74132
74138
74139
74151
74153
74154
74155
74156
74157
74158
74160
74161
74162
74163
Low Power-Schottky Dual J-K FF
Dual D Flip Flop
Quad Latch
Dual J-K Flip Flop
Quad Latch
Dual J-K W/Pre Co
4-Bit Full Adder
4-Bit Magnitude Comparator
Quad Exclusive OR Gate
Dual J-K Flip Flop
Dual J-K Flip Flop
J-K Flip Flop (Negative)
Dual J-K Flip Flop
Dual J-K Flip Flop
Tri-State Quad Buffer
Tri-State Quad Buffer
Quad Schmitt Trigger
Expandable 3/8 Decoder
Expandable Dual 2/4 Decoder
8-lnput Multiplexer
Dual 4-lnput Multiplexer
4-Line to 16-Line Decoder""
Dual 2/4 Demultiplexer
Dual J-K Flip Flop
Quad 2/1 Multiplexer
Quad 2/1 Multiplexer (Inv Out)
Preset Decade Counter
Preset Binary Counter
Preset Decade Counter (Syn-Cir)
Preset Binary Counter (Syn-Cir)
11-14
24
16
29
28
32
28
47
111
8
24
24
28
24
28
8
8
16
24
18
86
24
130
20
20
32
32
87
91
90
93
DEVICE CELLS
DESCRIPTION
74164
74168
74169
74173
74174
74175
74190
74191
74192
74193
74196
74197
74247
74248
74249
74253
74257
74266
74279
74283
74353
74365
74366
74367
74368
74373
8-Bit Shift Register
Decade Up/Down Counter
Binary Up/Down Counter
Tri-State Quad D Register
Hex 0 Flip Flop
Quad D Flip Flop
Up/Down Decade Counter
Up/Down Binary Counter
Up/Down Decade Counter
Up/Down Binary Counter
Presettable Decade Counter
Presettable Binary Counter
BCD/7-Segment Decoder/Driver
BCD/7-Segment Decoder/Driver
BCD/7-Segment Decoder/Driver
Dual 4-lnput Multiplexer""
Quad 2-lnput Multiplexer"""
Quad Exclusive NOR Gate
Quad Set-Reset Latch
4-Bit Full Adder
Tri-State Dual 4-Bit Mux (Inv Out)
Tri-State Hex Buffer
Tri-State Hex Inverter
Tri-State Hex Buffer
Tri-State Hex Buffer
Tri-State Octal D Flip Flop
Quad Exclusive OR Gate
7438~
35
105
87
56
36
24
108
109
104
105
80
77
48
48
40
48
12
8
12
53
24
33
29
21
16
64
8
Do not use except for slow speeds
"" Simpler using tr!lnsmission gates
" " "Use transmission gates and decode
IS05
.... Siliconix
incorporated
~
IS05 INTERFACE OPTIONS
SILlcbNix
DAISY~
SUPPORTED
CAD SYSTEM
PERSONAL LOGICIAN
LOGICIAN
DAISY~
PERSONAL LOGICIAN
LOGICIAN
FULL DESIGN
NETLIST
SIMULATED NETLIST
SCHEMATIC
ELECTRICAL
SPECS
SIMULATION
VECTORS
..
I
[P[1.t!l@l
..
.[il[11D@l
PACKAGE
SELECTION
ID
PARAMETRIC
SIMULATION
11-15
Packaging
lEI
...,. Siliconix
incorporated
~
TABLE OF CONTENTS
Plastic DIP (J. N Suffix). 8-16 Leads .......................................•..•.....••. 12-1
Plastic DIP (J. N Suffix). 24-48 Leads ................................•................. 12-2
Plastic DIP (J. N Suffix). 24 Leads. 0.3" Narrow Body .....•....................•......... 12-3
CerDIP (K. Q Suffix). 14-20 Leads .................................................... 12-4
CerDIP (K. Q Suffix). 24-40 Leads. 0.6" Wide Body .............................•....... 12-5
Side Braze DIP (P. D Suffix). 14-24 Leads ....•..............•....................•....• 12-6
Side Braze DIP (P. R. D Suffix) 24-48 Leads. 0.6" Wide Body .....................•....... 12-7
SO Package (Y Suffix). 8-16 Leads ..................................•.•..•..••..•..•. 12-8
SO Package (Y Suffix). 16-28 Leads. Wide Body ........................................ 12-9
PLCC Package (N. P Suffix). 20-84 Leads . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 12-10
CerQuad Package (M Suffix). 28 & 44 Leads ...................................•...... 12-11
CLCC Package (M Suffix). 44 Lead ...........•...............................•...... 12-12
LCC Package (Z. E Suffix). 20 & 28 Leads .•..............•..•..•.•................... 12-13
Flat Package (L Suffix). 14 Lead. Obsolete Version ..................................... 12-14
Flat Package (L Suffix). 14 & 16 Leads ............................................... 12-15
MO-002AG (Formerly TO-78) .............................•..•...................•.. 12-16
MO-002AK (Formerly TO-99) ...............•....................•.....•.....••..•.. 12-17
MO-006AD (Formerly TO-100) .........•..•......................•...........•...... 12-18
....,. Siliconix
incorporated
~
Plastic DIP (J, N Suffix), 8·16 Leads
MILLIMETERS
MIN
MAX
3.81
5.08
1.27
.38
.38
.51
.89
1.65
.20
.30
9.65
11.68
17.27
19.30
18.93
21.33
22.35
24.38
24.89
26.92
7.62
8.26
5.59
7.11
2.29
2.79
7.37
7.87
3.175
3.81
1.27
2.03
1.02
2.03
1.02
2.03
.38
1.52
1.02
2.03
1.02
2.03
OIM.
m
16;==;==r==v/ I;=o=r==;===;=
TI
A
A(1)
8
8(1)
C
0-8
0-14
0-16
0-18
0-20
E
E(1)
e(1)
e(A)
L
Q(1)
S-8
S-14
S-16
S-18
S-20
,
I
l '\
J
""
It
o
INCHES
MIN
MAX
.150
.200
.015
.050
.015
.020
.035
.065
.008
.012
.460
.380
.6BO
.760
.745
.840
.8BO
.960
.980
1.060
.325
.300
.220
.280
.090
.110
.290
.310
.125
.150
.050
.080
.040
.080
.040
.080
.015
.060
.040
.080
.040
.080
"\\
\\
~
t.(A)-J..~K
MAX
12-1
WY'Siliconix
incorporated
~
Plastic DIP (J, N Suffix), 24·48 Leads
rn
=;=:;=;=;=;=;I\;=r:;=r=;=;: ~I
2
11.;=;=;1i"i"i"i
I
II
II
-JL~
I ./
c
e(A) ---1
15 0
MAX
DIM.
A
A(1)
8
8(1)
C
0-24
0-28
D-40
D-48
E
E(1)
e(1)
e(A)
L
Q(1)
S
12-2
MILLIMETERS
MIN
MAX
3.81
5.08
.38
1.27
.38
.51
.89
1.65
.20
.30
29.97
33.02
35.05
38.10
50.29
53.34
60.45
63.50
15.24
15.88
13.21
14.73
2.29
2.79
14.99
15.49
3.175
5.08
1.27
2.03
1.02
2.54
INCHES
MIN
MAX
.150
.200
.015
.050
.015
.020
.035
.065
.008
.012
1.300
1.180
1.380
1.500
1.980
2.100
2.380
2.500
.600
.625
.520
.580
.110
.090
.590
.610
.200
.125
.050
.080
.040
.100
tI"JP'"
~
Siliconix
incorporated
Plastic DIP (J, N Suffix), 24 Leads,
0.3" Narrow Body
m
E(1)
E
=;=;==;==;==;=;==;=;==;==;=;==r===;:=r=;==;=:;==;==;=,Lbi
1A:;==:;=:;==;=2
1+-------- D -------+1
-I
rDIM.
A
A(1)
8
8(1)
C
D
E
E(1)
e(1)
~.
L
Q(1)
S
e(1)
MILLIMETERS
MIN
MAX
3.B1
5.0B
.3B
1.27
.3B
.51
.B9
1.65
.20
.30
29.97
32.00
7.62
B.26
INCHES
MIN
MAX
.150
.200
.015
.050
.015
.020
.035
.065
.OOB
.012
1.1BO
1.260
.300
.325
5.59
2.29
7.37
.220
.090
.290
.125
.050
.040
3.175
1.27
1.02
7.11
2.79
7.B7
3.B1
2.03
2.03
.2BO
.110
.310
.150
.OBO
.OBO
III
12-3
..... Siliconix
incorporated
~
CerDIP (K, Q Suffix), 14·20 Leads
11
~~=2~=-~-==-~~~=r~~~ 1') I
------~~I
D
Q(1)
A
L
OIM.
A
A(1)
8
8(1)
C
0-14
0-16
0-18
"0-20
E
E(1)
e(1)
e(A)
L
L(1 )
Q(1)
S-14
5-16
5-18
5-20
Q
12-4
MILLIMETERS
MIN
MAX
4.06
5.08
.51
1.14
.51
.38
1.14
1.65
.20
.30
19.05
19.56
19.05
19.56
22.35
22.86
23.88
24.38
7.62
8.26
6.60
7.62
2.54 8SC
7.628SC
3.18
3.81
3.81
5.08
1.27
2.16
1.65
2.41
.38
1.14
.76
1.52
.25
1.02
0°
15°
INCHES
MIN
MAX
.160
.200
.020
.045
.015
.020
.045
.065
.008
.012
.750
.770
.750
.770
.880
.900
.940
.960
.300
.325
.300
.260
.1008SC
.3008SC
.125
.150
.150
.200
.050
.085
.065
.095
.015
.045
.030
.060
.010
.040
o°
15°
Ir'F' Siliconix
~
incorporated
CerDIP (K, Q Suffix), 24-40 Leads,
0.6" Wide Body
s~
~I
D
Q(l)
~~~A
L(lr_~VVII UUUU[~JjL
B(l)~ ~ -+l I+- e(l)
DIM.
A
A(l)
B
B(l)
C
D-24
D-28
D-40
e(l)
e(A)
E
El
L
Ll
Ql
S
O!
B-II-
MILLIMETERS
MIN
MAX
4.06
5.0B
.51
1.14
.3B
.51
1.14
1.65
.20
.30
31.50
32.00
36.58
37.08
INCHES
MAX
MIN
.200
.160
.045
.020
.015
.020
.045
.065
.012
.OOB
1.240
1.260
1.440
1.460
51.82
52.32
2.54 BSC
15.24 BSC
15.BB
15.24
2.040
2.060
.100 BSC
.600 BSC
.625
.600
12.95
3.1B
3.Bl
13.46
3.Bl
5.0B
.510
.125
.150
.530
.150
.200
1.27
2.16
.050
.OB5
1.52
0°
2.29
15°
.060
0°
.090
15°
12-5
..... Siliconix
incorporated
~
Side Braze DIP (P, D Suffix), 14-24 Leads
-I
I-S(l)
m
II
2
D
T
L(l)
L
~
B(l) ....
H
e(l)
DIM.
A
A(l)
8
8(1)
C
0-14
0-16
0-18
0-20
0-24
E
E(l)
e(l)
e(A)
L
Q(l)
S-14
S-16
S-18
S-20
S-24
12-6
LJ
A
~t:- e(A)- l
B~~
MILLIMETERS
MIN
MAX
2.67
4.44
.64
1.39
.38
.53
.97
1.52
.20
.30
17.53
19.55
19.56
21.08
22.36
23.62
24.89
26.16
29.97
31.24
7.37
8.25
7.12
7.87
2.548SC
7.628SC
3.18
4.44
.25
.77
2.41
.51
1.65
.77
1.65
.77
1.65
.77
2.41
INCHES
MIN
MAX
.105
.175
.025
.055
.015
.021
.038
.060
.012
.008
.690
.770
.770
.830
.930
.880
1.030
.980
1.180
1.230
.290
.325
.280
.310
.1008SC
.3008SC
.125
.175
.010
.095
.030
.020
.065
.030
.065
.030
.065
.030
.095
-
..... Siliconix
incorporated
~
Side Braze DIP (P, R, D Suffix) 24-48 Leads,
0.6" Wide Body
ITT
~1~2~~d~~h=~Jl I
s-l4
[nm
d'
L(1)
8(1)
D
I
I
j.H.l
I
e(1)
Q(1)
+ VA
A(1)
L
-II. 8
A
A(1)
B
B(1)
C
0-24
MILLIMETERS
MIN
MAX
2.16
4.83
.51
1.78
.38
.58
.97
1.52
.20
.30
29.98
30.98
INCHES
MIN
MAX
.085
.190
.020
.070
.015
.023
.038
.060
.008
.012
1.220
1.180
0-28
35.06
36.22
1.380
1.430
0-40
0-48
E
E(1)
50.30
60.45
15.12
51.56
61.72
15.87
1.980
2.380
.595
2.030
2.430
.625
OIM.
e(1)
elAl
L
Q(1)
S
14.73
15.49
2.54 BSC
15.24 BSC
3.18
4.45
.25
.76
1.65
-
.580
.610
.100 BSC
.600 BSC
.125
.175
.010
.030
.065
lEI
12-7
~
~
SO Package (Y Suffix), 8·16 Leads
DIM.
A
A(1)
S
C
0-8
0-14
0-16
E
e
H
L
e
12-8
MILLIMETERS
MIN
MAX
1.75
1.35
.10
.20
.35
.45
.18
.23
4.60
5.20
8.35
8.95
10.20
9.60
INCHES
MIN
MAX
.053
.069
.004
.008
.014
.018
.007
.009
.181
.205
.329
.352
.378
.402
3.55
4.05
1.27 SSC
5.70
6.30
.60
.80
0°
8°
.140
.160
.050 SSC
.224
.248
.024
.031
8°
0°
Siliconix
incorporated
..... Siliconix
incorporated
~
SO Package (y Suffix), 16-28 Leads, Wide Body
1
~2~J
OIM.
A
A(1)
B
C
0-16
0-18
0-20
0-24
0-28
E
e
H
L
e
MILLIMETERS
MIN
MAX
2.15
2.90
.10
.30
.35
.45
.23
.28
10.75
9.95
11.25
12.45
12.50
13.30
15.05
17.60
7.25
1.27
9.80
.60
0°
15.85
18.40
8.00
BSC
10.60
1.00
8°
INCHES
MIN
MAX
.085
.114
.. 004
.012
.014
.018
.009
.011
.423
.392
.443
.490
.492
.524
.593
.624
.693
.724
.285
.315
.050 BSC
.386
.417
.024
.039
°
8°
o
12-9
".". Siliconix
,.6;11 incorporated
PLCC Package (N, P Suffix), 20-84 Leads
11'-
DIM.
A
A(1)
A(2)
B
B(1)
0-20
0-28
0-44
0-52
0-68
0-84
0(1)-20
0(1 )-28
0(1)-44
0(1)-52
0(1)-68
0(1)-84
0(2)-20
0(2)-28
0(2)-44
0(2)-52
0(2)-68
0(2)-84
e(1)
12-10
MILLIMETERS
MIN
MAX
4.20
4.57
2.29
3.04
.51
.553
.331
.812
.661
10.03
9.78
12.32
12.57
17.65
17.40
19.94
20.19
25.02
25.57
30.10
30.35
8.890
9.042
11.430 11.582
16.510 16.662
19.050 19.202
24.130 24.330
29.210 29.413
7.37
8.38
9.91
10.92
14.99
16.00
18.54
17.53
22.61
23.62
27.69
28.70
1.27 BSC
INCHES
MAX
MIN
.180
.165
.120
.090
.020
.013
.021
.026
.032
.385
.395
.485
.495
.685
.695
.785
.795
.985
.995
1.195
1.185
.350
.356
.450
.456
.650
.656
.750
.756
.950
.958
1.150
1.158
.290
.330
.390
.430
.590
.630
.730
.690
.890
.930
1.090
1.130
.050 BSC
A(2)
W'F' Siliconix
~
incorporated
CerQuad Package (M Suffix), 28 & 44 Leads
1....1 - - - - 0 - SQUARE----..!
0(1) - SQUARE::::.:=:]
I-'--"'-L.._
T
0 (2)
e(1)
DIM.
A
A(1)
A(2)
B
B(1)
0-28
0-44
D(1)-28
0(1)-44
0(2)-28
0(2)-44
e(1)
MILLIMETERS
MIN
MAX
4.20
4.83
2.29
3.04
.51
.46
.56
.81
.66
INCHES
MIN
MAX
.165
.190
.090
.120
.020
.018
.022
.032
.026
12.57
.495
.485
.685
.695
.442
.458
.642
.658
.390
.430
.590
.630
.050 BSC
12.32
17.40
11.23
16.31
9.91
14.99
1.27
17.65
11.63
16.71
10.92
16.00
BSC
12-11
..,. Siliconix
incorporated
~
CLCC Package (M Suffix), 44 Lead·
8(1)
L
"'--r-'
0(2)
1 + - - - - - D - SQUARE - - - - - - + 1
DIM.
A
A(l)
A(2)
B
B(l)
D
D(l)
D(2)
e
12-12
MILLIMETERS
MIN
MAX
2.54
3.43
2.03
3.30
.64
.58
.33
.51
.81
17.27
17.78
15.95
16.81
INCHES
MIN
MAX
.100
.135
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Applications
l1li
. . . Siliconix
incorporated
~
TABLE OF CONTENTS
AN88-2: Microprocessor Compatible Multiplexers Facilitate
Video Switching Designs .••.....................•...•....................••...... 13-1
AN88-1: Applications For the D469 - A High Current Power Driver ....••...•............•. 13-24
AN87-4: Improve System Precision with the Si7652 Chopper-Stabilized
Optional Amplifier .......•.............•................................. '. . . • . . . . 13-29
AN87-3: The Si7541A 12-8it CMOS Multiplying DAC Theory and Applications ..........•..... 13-41
AN87-2: Efficient ISDN Power Converters Using the Si9100 ...•........................... 13-67
AN87-1: A 1-Watt Flyback Converter Using the Si9100 .................................. 13-74
AN86-1: The DG535/536 Wideband Multiplexer Suits a Wide Variety
of Applications .......•.••.........................•..•........................ 13-85
AN84-2: Theory and Applications of the Si7660 and Si7661 Voltage Converters ............. 13-102
AN83-14: A Simple Approach to Si7135/8085 Interfacing .•.......•...................... 13-114
AN83-13: Si8601 Data Acquisition System Interfaces for I/O or
Memory Mapped Operation ..........................•..•.....•.•.•....•......•• 13-122
AN83-7: A High Quality Audio Crosspoint Switch .........•............................. 13-128
AN83-6: A System Solution to HP-IL Equipment Interface ..........••........•....•..... 13-131
AN83-4: Improved System Performance Using Microprocessor
Compatible Multiplexers .....................•.......•.•.........•.....••......• 13-138
AN83-3: A Microprocessor Compatible Analog Switch Makes Interfacing Easy •............. 13-151
AN8~-1: The DG308A Digitally Switches Analog Signals • . • • . . . . . . • . . . . . . . . • . . . . . . . . . . . . . 13-157
AN76-7: Function/Application of the L161 Micropower Comparator ...........••.•...•.... 13-165
AN76-6: DG300A Series Analog Switch Applications .........•...........•...•.•......•• 13-173
AN75-1: CMOS Analog Switches - A Powerful Design Tool ..•.•........•.••............. 13-189
AN74-2: Analog Switches in Sample and Hold Circuits ...••............................. 13-206
AN73-6: Function/Application of the L144 Programmable Micropower
Triple Op Amp ..................................•............................. 13-214
AN73-2: IC Multiplexer Increases Analog Switching Speeds .........•........•........... 13-221
TA87-1: Eliminate the Guesswork in Your Analog Switching Error Analysis ...•.•........... 13-227
TA73-1: Multiplexer Adds Efficiency to 32-Channel Telephone System .......•.•.....•..... 13-232
~
~
AN88-2
Siliconix
incorporated
MICROPROCESSOR - COMPATIBLE MULTIPLEXERS
FACILITATE VIDEO SWITCHING DESIGNS
Gareth Powell
February 1988
For many new communications systems - such as
ISDN (Integrated Services Digital Network). cable TV.
and local area networks (LANs) - traditional switching
techniques have become inadequate. To meet the
demands of these applications. semiconductor
switching devices must now handle wider bandwidths
and offer more on-chip features to achieve low chipcount solutions. Higher integration. smaller packages. easier device paralleling/combining. and improved dynamic performance are essential features
for designing large-capacity switching systems.
Analog video information is frequently digitized for
processing in frame grabbers. TV standard converter
(e.g .• NTSC to PAL). time-base correction. special
effects. or merely as a means of reducing noise levels and enhancing resolution. However. the price
paid for the advantages of the digital technique is the
substantially wider bandwidth occupied by the digitized signal. Thus. in a typical 8-bit conversion. the
sampling rate must be at least three times the
chrominance subcarrier frequency of 4.43 MHz: that
is. 13.3 MHz. Thus. the bit rate is 8 x 13.3 = 106.44
Mbps. This bandwidth requirement precludes the use
of a majority of components and switching techniques commonly employed in video systems.
Video switching applications. such as high-definition
TV. digital video equipment. and broadcast studio
switches have forced improvements in semiconductor switch performance. The Siliconix DG534 and
DG538 are members of a fast growing family of mUltiplexer/demultiplexer devices with performance characteristics optimized for wideband switching applications. This application note presents the benefits of
the DG534 and DG538 in a diverse range of wideband
switching applications. highlighting the devices' performance features and providing useful circuit design
techniques.
All eight DG538 Input switches are "T· switches.
All four DG534 Input switches are "T" switches.
V+
GND
V-
V+
GND
V-
SA1
SA1
SA2
SA2
I~
.,.. I
DA
DA
SA3
SM
I
11
SB1
SB2
DB
:"-1
4/2
8/4
EN
WR
DECODE LOGIC, ADDRESS
LATCHES, I/O CONTROL
LOGIC
DB
EN
RS
1----I-oRS
WR
III
i/o
Ao
A,
Ao
Figure 1. DG534 and DG538 Functional Schematics
13-1
H
AN88-2
Device Description
The DG538 is a wideband single-ended 8-to-1 or differential 4-channel multiplexer. Several DG538s can
easily be configured to create a more complex matrix
or to handle crosspoint functions. The DG534, similar
to the DG538 with half the number of channels, is a
4-to-1 single-ended or a 2-to-1 differential multiplexer.
D/CMOS processing enables these devices to be optimized for high-frequency Signal handling with low
ON-resistance while on-chip CMOS circuitry provides
all the level shifting, logic interfacing, and latching
functions that permit easy system design. The switch
structure utilizes lateral n-channel DMOS transistors
configured in a "T" arrangement, as shown in Figure
1. The "T" switches are arranged into two groups.
Each group is selected by the second-stage "L"
switches. This two-level switching configuration minimizes' channel capacitance and off-state signal
crosstalk (maximizes OFF-isolation).
For comparison, Figure 2 shows the single-channel
crosstalk characteristics of the DG538 video multiplexer and the industry-standard DG508A. Note the
35-dB performance improvement of the DG538 versus the standard CMOS 8-channel multiplexer.
The DG538 data sheet specifies all-hostile crosstalk.
This is a much more rigorous test specification than
single-channel crosstalk since it requires all seven
"off" channels to be tied together. More crosstalk
signal is seen at the switch under these test conditions because there are seven parallel paths, as opposed to only one, and the crosstalk contribution of
the package and the PC board are also more apparent. Nevertheless, the all-hostile crosstalk of the
DG534 and DG538 approaches -70 dB at 5 MHz, easily meeting most video switching requirements.
It is not merely the "T" and "L" configurations that
give improved crosstalk. Careful on-chip layout and
optimum device sizing were also required. A small
device exhibits low intrinsic capacitances, but has
greater ON-resistance and, hence, will give a greater
insertion loss. However, by employing DMOS (double
diffused MOS) FETs for the switches, an excellent
compromise between rDS(ON) and intrinsic capacitances is achieved.
Figure 3 shows a cross section of an n-channel device made with the D/CMOS process, incorporating
DMOS and PMOS transistors. The fabrication of the
"T" switch is shown. The short-channel feature of the
DMOS devices offers 8 to 10 times less channel capacitance than a conventional lateral NMOS transistor
for a given rDS(ON). Figure 3 also shows the n- and
p-channel devices that form the CMOS logic interface, level shifting, and latches.
-120
c-...
-110
r--."
-100
-90
-.....
-BO
i'
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-70
-60
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C~~~~~~[K
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-50
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-30
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-20
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- -- ---=100k
~:'
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1' ....
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I I I """" I UlIlllill1M 1 I I" """
10M
100 M
FREQUENCY (Hz)
Figure 2. DG538/DG508A Single-Channel Crosstalk
13-2
Siliconix
incorporated
VS.
Frequency
AN88·2
...,. Sillconix
incorporated
~
FROM
DRIVER
CIRCUIT
I
I
I
P-- SUBSTRATE
I
N - CHANNEL
DMOS 'T' SWITCH
N - CHANNEL
PMOS FET
DMOS FET
I
I,
/
--------------~-------------COMPLEMENTARY MOS
f /,.f" '1- METAL (AL)
1IlIIIIIIIIIIII- GATE OXIDE (SI02)
_ - POLYSILICON GATE
[:::J - AELD OXIDE
Figure 3, Cross Section of the D/CMOS Process
The cross section shows many pn junctions which
would become forward biased if signals applied to
the device were more negative than the "p" substrate, For this reason, when handling ac signals, the
substrate is connected to a negative voltage (V-) to
allow signals to swing below ground.
ased with overvoltage transients, thus eliminating
fault current flow.
40
Using a negative supply also optimizes device capacitances. The body effect on DMOS devices
causes the ON-state capacitance to change as a
function of V-. For a fixed analog signal, CON reduces exponentially as the source-to-substrate voltage increases (see Figure 4). Other performance
benefits can be attained by choosing a particular V(see Figure 19).
In the event of an overvoltage (analog Signal gOing
more than a diode drop beyond V-), the pn junction
between the source or drain and the substrate will
forward bias, causing a large current to flow. This
fault current will not damage the device as long as
the current flow is less than 20 mAo However, low-impedance source circuitry is typical of many applications; for example, the output impedance of a video
buffer amplifier is 75 n. Thus, a means of current
limiting should be employed in circuits where overvoltage transients are possible. Figure 5 shows a transient protection scheme that uses a diode in V-, This
diode (normally forward biased) becomes reverse bi-
~\.
\.
I"
30
,
l'..
....
ON-STATE
INPUT
CAPACITANCE
......
(pF)
20
10
.......
DG538DJ
........
-10...
DG538DN
o
2
3
4
I"--
5
6
---7
8
9
10
V SOURCE TO SUBSTRATE (V)
Figure 4.
DG538 ON-state Input Capacitance vs.
Source-to-Substrate Voltage
Positive overvoltages (> V+) are a different problem.
The switch will merely turn OFF (no enhancement) if
Signals approach or exceed V+. The DMOS drain diffusion has a fairly high breakdown voltage (typically
> 30 V) . Large avalanche currents can flow during
13-3
III
.... Sillconix
incorporated
AN88·2
~
breakdown, therefore, either the signals must be externally clamped to avoid exceeding breakdown voltage, or a means of external fault current limiting
should be adopted. Since the source diffusion will
only develop a voltage during the switch "ON" state,
under normal supply conditions this breakdown
(source-to-substrate) is unlikely to occur due to'the
device turning OFF when the source voltage, Vs, approaches V+. Therefore, external positive overvoltage protection is only required when transients or
overvoltages are expected to be in excess of +30 V.
6
5
./
4
.",-
vT
(V)
3
.",-
2
1
0
".
..,""2
../
4
.",
6
8
10
12
14
16
18
VL (VOLTS)
Figure 6. DG538 Switching Threshold vs.
Logic Supply Voltage (vL )
S1a
INPUTS
••
•
•••
The DG538 and DG534 have tri-state latches on their
address pins, allowing three modes of operation:
Da
OUTPUT
Dt,
S4b
1. Input Data. In this mode, the multiplel-
26
32
AoVt
WR--'RE
DalDb EI\
-
•
••
f- DalDb RS
V- EN
VIDEO OUTPUT' 0 - -
L ....
RESET
~
f-
.:.
~:----tWR
.---------tl/O
+5V
ADORES
BUS
+15 V
6S00
-3V
s1a
: VIDEO INPUTS
DATA BUS
S4b
AS
Da/Db
OUT
1/0
VL
+5V
+15 V
-3 V
Figure S. Other Microprocessor Interfaces
V+
DATA BUS
Z80
DG53S/4
+15 V
r--~~---t +5 V
PSU
r------...,.J~-___1 WR
OV
-3V
...--------liio
R
VDD
Figure 9. Using
RS
Characteristics
The DG538 and DG534 data sheets include detailed
operating characteristics. typical parameters. and
limit values. The important dynamic characteristics.
such as crosstalk and bandwidth. are plotted against
frequency (to 100 MHz) to help designers predict
system performance. since these parameters are
as a Power-up Failsafe
measures of the ON-state and OFF-state multiplexer
performance.
Specialized video specifications not included on the
data sheet are presented here to provide a better
understanding of the devices' performance and suitability for a wide range of video and general
wide band switching applications.
13-7
III
AN88-2
~
~
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IIN~E~~W~iW-1II1II1
Siliconix
incorporated
IR~~I~!~I
PHASE------
-2
~
IN~~~]ON
~
(dB)
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1' ....
.... I'~
-20·
"
-8
PHASE
(deg)
-40·
-10
~O·
-12
1M
10M
FREQUENCY
~:
100 M
00illI
1000M
(Hz)
Figure 10. OG538 Bandwidth and Phase Response
Bandwidth Is a measure of the ON-state performance and is defined as the frequency at which the
signal falls -3 dB from the low-frequency insertion
loss figure. Figure 10 shows the typical frequency
characteristics of the OG538 measured on an
HP8573A network analyzer.
Since a multiplexer channel exhibits ON-resistance.
rOS(ON). and ON-state capacitance. C (ON). increasing signal frequencies are progressively attenuated.
However. It Is a common misconception that 'the
bandwidth can be calculated from the rOS(ON) and
C (ON) specifications given on the data sheet.
The -3 dB frequency for the model shown In Figure
11 is given by the formula:
-3 dB
= -------:.-----,=-[ RL X rOS(ON)] C
RL + rOS(ON)
(ON)
Substituting RL = 50
n.
rOS(ON) = 50
CION) = 23 pF gives an f -3 dB ~
n.
A SPICE simulation of the model shown in Figure 12
gave a 510 MHz -3 dB point. which is much closer to
the measured value (see Figure 13).
r--------.,
DG53B
I
I
Sx I
rOS(ON)
lox
I
I
I
I
I
I
VIN:
(R gen = 0) I
CS(ON)r : :
I
I
I
I
I
I
I
-
"'--------..1 '
and
310 MHz
The measured frequency response for the
same 50 n load (Figure 10) shows a -3 dB point of
13-8
over 500 MHz. This apparent discrepancy results because the rOS(ON) and CION) are distributed among
the five OMOS FETs that form the "T" and "L"
switches.
INSERTION LOSS (dB)
= 20 log
VOUT
VIN
Figure 11. Erroneous Model for Frequency
Response Calculations
VOUT
AN88·2
Silica nix
incorporated
r -- - --- - - I
Rl
R2
---rDS(ON)- - - - - - - - - - ---,
R3
R4
Rs
I
, -_ _ _--J\
---.----0 V OUT
\ ,.....
.......
R 1 to
Rs
C l to
Cs
\
, /.....
........ \ I ....._ ......
....... ~?
C(ON)
= an (Since rDS(ON) = 40.0. )
=4.6 pF (Since C S(ON) =23 pF
)
Figure 12. Five-Stage RC Model
-4
-s
INSERTION
LOSS
~ittt1tttltITrrmt::::::~E!:-rTofitj#;t;!;!jI- 5 STAGE RC MODEL
r-~v:
0
+10
0
0
I
-6
+20
0
-10
0
20
0
-30
0
-40
0
-50
0
-60
0
(dB)
PHASE
-8
SINGLE STAGE RC MODEL
r, I'
-10
(deg)
-12
1M
Figure 13.
10 M
100 M
FREQUENCY (Hz)
1000 M
Bandwidth and Phase Response for the Models of Figures 11 and 12
Note that the equivalent five-stage RC circuit shown
in Figure 12 is not a complete model of the OG538
transmission path. However. it does illustrate the effect of distributed parameters. An actual model
would be far more complex. with other reactive elements that incorporate package capacitances. inductances. etc.
In the absence of a better model. the circuit shown in
Figure 12 is useful for predicting bandwidths in
crosspoint systems where the frequency response
will be affected by paralleling devices (Figure 14).
A 10 n source impedance is included in Figure 14.
This source impedance simulates the low-output impedance of a video buffer amplifier generally employed at the input to the matrix. The simulation results of the circuit. using single-stage and five-stage
models for different numbers of parallel channels.
are shown in Table 2.
13-9
~
a-=-
~
AN88·2
~
Table 2
-3 dB Bandwidth (20 LOG VOUT)
Number of
Parallel
Channels
V IN
Single R-C Stage
(Figure 11)
5 Stage R-C
(Figure 12)
1
280 MHz
400 MHz
2
250 MHz
340 MHz
4
225 MHz
260 MHz
8
185 MHz
200 MHz
16
170 MHz
160 MHz
The "flat" response over the bandwidth of interest is
an important requirement for video applications. The
Independent Television Companies Association
(ITCA) specifies the following gain/frequency limits
for a video switching matrix.
Mid- to high-frequency response:
±0.1 dB between 100 kHz and 5.5 MHz
±0.25 dB between 5.5 MHz and 8 MHz
Siliconix
incorporated
High-definition TV has much tighter tolerances since
it requires bandwidths to 25 MHz. The 0 to 30 MHz
frequency response of the DG538 and DG534, shown
in Figure 15, is well within the required limits.
Group Delay, sometimes called envelope delay or
deviation from linear phase, is the phase-shift rate of
change through a circuit or equipment with respect
to frequency, or alternatively, non-linearity of the
group frequency response. In a transient waveform
which has a continuous spectrum, the group delay
becomes the transmission time of a packet of spectral components. It follows, therefore, that if the
group delay is constant for all the required
bandwidth, there will be no difference in the arrival
times of the various spectral components which
make up the bandwidth.
Because many different frequency components
make up a video waveform, this parameter is of particular relevance in video applications. The measured
group delay response of the DG538 is shown in Figure 15. It satisfies the most demanding video requirements. The plot shows less than 500 ps over a
30 MHz frequency range.
Above 8 MHz:
+0.2
"Response shall fall continuously and smoothly"
Although this specification
tems used in the United
specification and similar to
NTSC and sequential color
is for 625-line PAL sysKingdom, it is a typical
other standards, such as
and memory (SECAM).
~
________~-oVOUT
san.
~---
-<1.4
--- --- --- --- -r--
---
~
-<1.6
RL= SO.n.
+0.5
-<1.5
-
--o
--- -
15
30
FREQUENCY MHz
san.
Figure 15. DG538/DG534 Group Delay and
Normalized Insertion Loss Response to 30 MHz
Non-Linearity Distortions
5O.n.
Figure 14. Equivalent Diagram of an 8 X N Crosspoint
Using DG538s when one VIN Is seleoted
to All Outputs
13-10
Color video can be divided into two groups: component video [separate red (R), green (G). and blue
(B) signals] and composite video, which contains
color and brightness (chroma and luma) information
in a single waveform.
AN88-2
WY'Siliconix
incorporated
~
0.7 V
WHITE-
::::'~'.':,"::'J"'.--- COLOR (OR CHROMINANCE)
.
...
y •••••••
l
,".:.t~c:c :'''i
L......::........ N.w. ••• :: ..
j ....\
OV
-0.3 V
~
___
i\. .
{
'~I~U
j;,LOR BURST
~SYNC PULSES
-I
~1·~-------------64~s
Figure 16. Basic Composite TV Signal
Composite video has various specifications that relate to the interaction of chroma and luma. In particular. differential gain and differential phase must be
specified for video components or systems. To illustrate these distortions. consider the basic composite
TV signal. Figure 16 shows a typical color TV signal.
The sync pulses. occurring every 64 Ils. synchronize
horizontal line deflection. The color signal contains
both luminance and chrominance. When this signal is
processed by a domestic TV receiver. the red.
green. and blue components are recovered and
used to modulate three individual electron beams.
Frequency related phase shifts (as opposed to
differential phase) will cause no change in picture
quality since both color burst and chrominance
are equally shifted.
•
Differential Gain. Expressed as a percentage.
this is a form of distortion resulting from changes
in the amplitude of the chrominance signal as a
function of luminance amplitude.
The effect on NTSC and PAL pictures is a change
in color saturation with changing luminance level.
The eye is fairly tolerant to differential gain since
the resulting picture changes are fairly subtle.
For instance. a brightly colored car traveling from
a sunny area of the picture to a shaded area
would appear as though its body color intensity
had suddenly changed.
The amplitude of the chroma contains the color intensity (color saturation). and its phase difference
with respect to the color burst determines the blend
(hue) of color.
•
Differential Phase. Measured in degrees. this is
the phase shift of the color subcarrier resulting
from a change in the amplitude of the associated
luminance component. Differential phase shows
up in NTSC pictures as a change in hue. a color
change more noticeable in a shaded area of the
picture.
Specialized equipment is employed to measure differential phase and gain. Specifications. such as
ITCA. require standard test signals and dedicated
test equipment and techniques. Recognized standard test waveforms are shown in Figure 17.
E.B.U. INTERNATIONAL
TEST LINE SIGNAL C
BRITISH NATIONAL
TEST LINE SIGNAL A
.
2T
~ ro~
62
0.14 V
\.
5~. ;"f~:
26
2T
.J
{.;: .~.,' ~
48 ":- V+,),
will become forward biased. Under these conditions,
large currents may flow and damage the device. To
avoid this condition, the power-up sequence should
ensure that VL does not come up before V+. Normally, this will not present a problem if V+ and VL are
derived from the same power supply.
.::;0.1 0
O~--"~~~~~--+~1~1--~+1~3---+~15~-+~17
v+ (VOLTS)
Figure 21. DG538 Supply Ranges to Maintain
< 0.1 % and 0.1 0 Differential Gain and
Phase
Handling Precautions
All MOS devices can be damaged by the presence of
excessively high electric fields in the gate-oxide region. Such fields can cause the gate oxide to rupture, rendering the device unusable. Mishandling
MOS devices may cause catastrophic damage from
the build-up of static electricity in the human body,
which can reach many thousands of volts.
To reduce electrostatic discharge (ESO) susceptibility in the OG534/oG538, all logic inputs are protected
by the circuit shown in Figure 22.
v+
AO,Al,A2I EN,
TO INTERNAL LOGIC
INPUT STAGE OF DEVICE
AS, iiiiR ,8/4 ,"i/0
__~____-Clv-
(SUBSTRATE)
Figure 22. ESD Protection Circuit
Printed Circuit Board (PCB) Layout and
Oecoupling
Selecting components optimized for high-frequency
signals does not guarantee adequate circuit performance. Good layout techniques are also very important. At high frequencies, stray capacitance between
long adjacent signal lines can provide low impedance
paths that couple with one another. Power supply
lines can couple rf signals from one circuit to another. Components or sockets that protrude on a
PCB surface may act as small antennas which pick
up or radiate rf signals. To avoid these problems, be
sure signal paths between components are as short
as possible and make extensive use of ground planes
and shielding between adjacent signal paths.
The OG534 and OG538 have ground pins isolating adjacent channels. These, when connected to
grounded shielding paths, give excellent ac performance.
Power supplies should be bypassed by the use of
decoupling capacitors mounted as close to the device supply pins as possible. This is of particular importance for the OG534/0G538 since the device substrate connects directly to V-. Two capacitors on
each power supply are recommended. A ceramic
capacitor of 0.01 to 0.1 J.lF, provides high-frequency
signal bypassing, and a tantalum capacitor (1 to
10 J.lF) is adequate to bypass low frequencies. Further decoupling can be achieved by adding a lowvalue series resistor (e.g. 51 0.) in the supply line.
13-13
~
...::.
...... Siliconix
incorporated
AN88-2
~
frared (FLlR) detectors (night vision systems), CAT
(computer aided tomography) scanners, and NMR
(nuclear magnetic resonance) medical imaging.
Components should be assembled on a PCB in a low
profile. The DG538, for example, is available as a
28-pin quad surface-mount package or a 28-pin dualin-line package. The latter has poorer crosstalk performance because it has a larger lead frame and because the device pins are connected through the
board. Using sockets should be avoided because
they degrade device performance significantly.
Figure 23 shows the DG538 as an 8-to-1 video source
selector. This circuit has many applications in industrial process monitoring systems or in security systems where eight separate video cameras connect to
a single monitor in a sequence. The circuit uses
three bits to automatically select each source in turn.
An override feature can be incorporated to disable
the counter and provide manual channel selection.
Applications
Applications for the DG538 and DG534 are many and
varied, ranging from high-frequency signal switching
to lower-frequency, low-level signal routing.
An example of a differential configuration application
is shown in Figure 24. This circuit may be used in
component video systems such as TV camera signal
routing. Two devices are required for routing four
separate RGB sources and their corresponding
audio, sync, or timecode signals. Note that the channel select or address bus is common to all devices.
Video Systems
The DG534 and DG538 multiplexers are ideal for
many wideband switching applications, such as highresolution financial data networks, forward-looking in-
+5 V
~
75.0.
+15 V
VL
V+
S1a
I
I
I
8 VIDEO CAMERAS I
I
~
Da
VIDEO
MONITOR
DG538
Db
AO
A1
A2
+5 V
Vee
-3V
40248
Figure 23. Baslo Closed-Clroult TV System
13-14
tI"F
~
AN88-2
Siliconix
incorporated
R
SOURCE G
1
B
S1a
RED
S4a
L - S1b
RSOURCE G
2
B
00538
I
S4b
AO
A1
EN
RS
4RGB
SOURCES
RI--SOURCE G
3
B
R
SOURCE G
4
B
r--
'---
.------
GREEN
iY
OUTPUTS
S1a
BLUE
S4a
S1b
00538
S4b
AO
A1
EN
4 TIMECODE,
SYNC OR
AUDIO
l
Rsl'r
'--
4 TIMECODE, {
SYNC OR
AUDIO
CHANNELS
SOURCE SELECT
Figure 24. An RGB Plus Tlmecode, Sync, or Audio Switching System
A majority of video applications require crosspoint
configurations, where a number of inputs must be
switched to a number of outputs. Applications requiring this type of matrix switching (both analog and
digital) range from PCM (Pulse Code Modulation) or
telecommunications data switching to financial information routing. A basic crosspoint configuration (8 x
4) is shown in Figure 25. The data-write control
strobes address information to each DG538. In turn.
the actual address data (for the required route) is
present on the address or route-assign bus. Video
output buffers are normally used to drive lengths of
75 0 coax cable.
In Figure 25. the loading of switch capacitances and
buffer input impedances on a given video source will
vary. depending on the number of outputs. For example. when a single source is switched to all four
outputs. it is loaded by 4 XCS(ON) (~92 pF) plus 4 x
Cln of buffer. This increased loading affects the frequency response and phase shift of the output signal.
Figure 26 illustrates this effect by showing the frequency response of a single output signal for an increasing number of channels connected to the
source. Additional channels (2. 3. and 4) are loaded
with 10 kO to simulate the input impedance of video
buffers.
13-15
AN88-2
IN1
IN2
a
INs
VIDEO IN4
INPUTS INS
IN6
IN7
INa
Siliconix
incorporated
H
·
·
S1a
~
:
•
•
D
:
Db
a
• DG538
-::
I\--
WR
I
··
··•
·
~
~
AV=2
1/
S4b
~
~
_
OUT 1
-
S1a
•
Da
DG538
Db
n
~
~
..
AV=2
1/
S4b
I
OUT 2
-
1\
WR
_
VIDEO
OUTPUTS
~
S1a
·
•
•
D
:
Db
• DG538
a
•
n
~
~
AV=2
1/
S4b
I
OUTS
-
\
WR
_
' - - - S1a
··
····
•
Da
DG538
Db
S4b
WR
~
-t
Kyo--
I
ADDRESS
ROUTE
ASSIGN
Figure 25. An 8 X 4 Crosspoint Switch
13-16
~
AV=2
_
-
~JJJ
DATA WRITE
CONTROL
OUT4
~ Siliconix
.&;II incorporated
o
.......
.... ......
-1
- .....
......... t-.- r- r-r-.
r-...;:: ~
-2
GAIN
(dB)
-
i-..
.......
t- ~
i'r-.
,
~ ~~
-3
r\
- -- \
r-r-1\ \
1-
i\
2
~
-s
1\ 1\
\ \
\
r\ \
0.3 M
1\
100 M
10M
FREQUENCY (Hz)
1M
-3 dB Lovel
\
700 M
Figure 26. Frequency Response of B X 4 Matrix
Figure 27 shows the measured frequency response
of any of four DG538s connected to a common signal
source. In this circuit. an EL2020 wideband op amp
(with its input resistance padded down to 1 1(0 to
improve switch bandwidth) was used as a buffer. The
dotted line shows the frequency characteristics of
the EL2020 alone. The gain response meets the
±O.1 MHz to 5.5 MHz requirement of ITeA systems.
Better performance can be achieved using an improved video buffer. such as an OPA633.
if an increased number of outputs is required. input
buffers may be used to avoid performance degradation below tolerable limits. Thus. to maintain the performance shown in Figure 27. no more than four
DG538s should be connected to a given input buffer.
.... 1"-
....r--
-2
-4
4 X DG538
GAIN
(dB)
-6
EL2020
"
11k
~
.".
~
11k
11k
0.3M
.... ,
"
I"-.''''r,
""
"
....PHASE
'\
-T- r y,OiY
LONE
10M
1M
O·
,
!> -20·
1\
-40.
\
"
",
1k
IN
!V
.... ....
"
r-..... ....... "I ..
~
-8
...
R.: -.. -
VOUT
-10
"
GAIN
0
PHASE
(deg)
-so·
\
\
30 M
FREQUENCY (Hz)
Figure 27.
Frequency Response of Four DG53Bs Buffered with EL2020s
13-17
AN88-2
".,. Siliconix
incorporated
~
Since each input buffer drives only four switch impedances and their corresponding output buffer input
impedances, no major output power is required (unlike the output buffers which must drive up to 2 V into
each 75 .0 cable). Therefore, it is sufficient to employ inexpensive and simple discrete buffers, such as
source or emitter follower circuits that require only a
transistor (FET or bipolar) plus a resistor. Because
simple input buffer designs (Figures 28 and 29) are
inexpensive, they are feasible for buffering every input in demanding, high-definition applications.
Some applications might demand a dc-coupled system that retains all the dc contents of the signal applied to the buffer. For these applications, the follower circuit shown in Figure 29 may be used. This
circuit, which exhibits a low dc offset of <40 mY,
uses a Siliconix U440 dual FET to maintain simplicity
and efficient use of board space. Lower offsets can
be accomplished by using a dual FET with better
matching characteristics (e.g., U232).
In the circuit shown in Figure 28, L3dB ~ 300 MHz for
Rgen = 75 .0 , while offering a low input capacitance.
The output signal for this circuit has some dc offset;
however, this is not usually a problem because the
output of the matrix is frequently ac coupled with a
dc restoration (black-level clamp) circuit employed
at a later stage. Figure 30 shows a simple black-level
clamp circuit that employs a DG271 high-speed analog switch.
Figure 31 shows a large 32 x 4 crosspoint matrix. It is
frequently better, in terms of system flexibility, to use
a smaller crosspoint card (e.g., 8 x 4) as the basic
building block. This 8 x 4 card must be designed to
allow expansion of the total number of inputs or outputs required by the system.
YIN
+15 V
AV
~------~-------oVOUT
3k.o
Rs
T
2 5PF
.
-15 V
Figure 28. Single FET Source Follower
GAIN = 0.99
dc offset < 40 mV
1/2 U440
vINO----t-l-__.-----.
~----~~----~VOUT
180.0
-15 V
Figure 29. FET Buffer Uses Matched JFETs
for Low DC Offset
I
o-------.J
~
Figure 30. Simple Black-Level Clamp Circuit
13-18
gfs x Rs
1 +gfs x Rs
J300
o----~-_.,._+-----'\
(DER1J€DCfRNJ~9;'vNC)
=
W7'
AN88-2
Siliconix
.6;11 incorporated
ANALOG VIDEO BUS
4
VIDEO
OUTPUTS
1
2
3
4
1
8X4
~
1....4 X DG53B
1
2
3
4
5
6
7
8
I~
n
~
I::'I~
I::'
Iv
I ...
..
/,,-
~ I-
'r---1 ....
~V
I::'
1::I~
IV
-
I ...
I~
32
~
~
I::'
I~
I~
l1li
IV
Figure 31. 32 X 4 Crosspoint with Bus Isolation
13-19
AN88 ..2
fIllY' Siliconix
.,!!;lI!J incorporated
Assuming each card has eight input buffers and four
output buffers as shown, expansion of system outputs is easily accomplished by paralleling the inputs
to the switch cards. Since each card has all its inputs
buffered, many cards may be connected to provide
multiple outputs without producing significant loading
on the signal sources. However, expanding the number of system inputs is more difficult. Each card output has a low-impedance video buffer that prevents
simple paralleling, which would greatly overload the
analog video bus. By using DG534 devices in a 4-to-1
mode as a submultiplexing configuration, as shown in
Figure 35, each line of the video bus sees only one
card output at a time.
not available or in hazardous industrial environments
where mains-derived power supplies are not permitted. Alternatively, this technique could be adopted in
a cable TV application, where the channel switcher or
selector could be powered from the incoming video
lines. The dc power is coupled to the video coax lines
using a 1 mH choke, and it is isolated or removed
from the video signal using the capacitors (C1, C2,
and C3).
Figure 32 shows a method for transmitting dc power
down the video coax. This system can be adopted in
remote switching locations where a power source is
Figure 33 shows a DG538 in a dual 4-by-1 arrangement designed to switch four video sources while
providing level compensation and/or gain for each.
Another popular video-signal manipulation application
is digitally controlled gain or attenuation circuits. For
example, digitally controlled gain may be required for
level trimming different video channels to be
switched to a single processing path.
SENDING END
r--VIDEO
OUT
lmH
1 2 3 4 5 6 7 8
8 VIDEO SOURCES
RECEIVING END
Figure 32. Phantom-Powered Remote Video Switch
13-20
H
AN88·2
Siliconix
incorporated
+15 V
{
4 VIDEO SOURCES
0:========1
o
S1a
S4a
.------------1 S1b
DG538
Da
1--------1
Figure 33. Programmable Gain Video Selector
Data Acquisition Front-End Applications
A typical data acquisition system comprises frontend sensor stages followed by signal conditioning
stages. The analog sensor signal, after being amplified and filtered, is sampled and digitized using a
sample-and-hold circuit and an analog-to-digital converter. The digitized signal is then processed, usually
under microprocessor control.
Usually, many analog channels must be processed.
Due to the high cost of signal-conditioning, fast sam-
ple-and-hold, and flash analog-to-digital converter
components, it is more feasible to employ a frontend multiplexer so that each channel can be processed in turn.
The circuit shown in Figure 34 uses a wide band multiplexer for accurate manipulation of the high-frequency input signals. The "user friendly" control and
microprocessor-interface features of the OG538,
combined with its proven high-frequency signal handling, make it ideal for this circuit.
+15 V
o-----I
8 ANALOG •
VIDEO
•
cH~M~LS •
S 1a
DG538
SIGNAL
CONDITIONING
SAMPLE
HOLD
VIDEO
ADC
•
DIGITAL
VIDEO
OUTPUT
SC
-3 V
SYSTEM CONTROL
(eg·.l1Fl
Figure 34. A Basic Multichannel Video/rf Processing Circuit
13-21
AN88-2
.... Siliconix
incorporated
~
INSTRUMENTATION AMPLIFIER
S1b
S2a
LOW
LEVEL
TRANSDUCERS
°al------I
OG538
S2b
S3a
Db
SAMPLE
HOLD
ADC
1------1
Figure 35. A High-Accuracy Low-Level Signal Processing System
The DG534 and DG538 are also effective devices for
switching low-level signals. Commonly, data acquisition systems monitor a number of sensor signals that
could be the output of various temperature, pressure, or vibration transducers. Generally, these are
low-frequency (often dc), low-level signals. Thermocouples, for example, typically have millivolt outputs
with tens of JJ.V /oC resolution. To accurately monitor
small temperature changes, the multiplexer must not
introduce any dc offset or noise. Since the circuitry
must handle small signal levels that are prone to
noise/mains pickup, digital crosstalk, etc., apply the
same layout rules used for high-frequency deSigns,
such as sufficient grounding and shielding.
The DG538, with its interchannel ground pin and symmetrical on-chip layout, improves circuit accuracy. A
differential signal handling system is an established
means of low-level transducer interfacing. This system rejects noise pickup, switching transients, and
metallic junction dc offsets as common-mode signals. A highly accurate low-level transducer interface
circuit using a DG538 in its differential mode is shown
in Figure 35.
Data Acquisition System Signal Conditioning
Before sampling and digitizing, an analog signal frequently requires "cleaning up" and ranging, a process known as signal conditioning. System front ends
will invariably pick up unwanted signals. Signal carry-
13-22
ing leads often pass areas that superimpose mains
hum, radio-frequency interference, or digital noise
on the analog signal to be processed. A well-designed and balanced differential twisted-pair system,
such as the one illustrated in Figure 35, will minimize
these common-mode signals.
Filtering
Filter circuits are widely used in the signal conditioning stage. Most often, they take the form of lowpass, high-pass, or band-pass configurations that remove unwanted signals outside the required
bandwidth. Figure 36 shows a general configuration
for an active first-order all-pass circuit that can be
used for providing a digitally controlled variablephase shift, where the phase shift is given by
13 (w)
= 2 tan-1
and the delay is found from
wRC
t d = _---::.2...:..R:.:::C__
(wRC) 2 + 1
Note: -wC = 1/RC = cut-off frequency. For constant
delay, w < 0.1 RC.
The circuit shown in Figure 36 may be employed as a
phase correction system to equalize phase delays
associated with different signal paths. A video
crosspoint, for example, will exhibit a varying phase
delay due to changing load capacitance on the transmission path when a single input connects to between 1 and n outputs (Figure 25).
AN88-2
Siliconix
incorporated
A. LEADING PHASE SHIFT
> ......- - - 0 VOLrr
V I N o - - - -....
CONTROL
LOGIC
B. LAGGING PHASE SHIFT
10 k.n.
> ......---cVOUT
R
CONTROL
LOGIC
Figure 36. A Digitally Controlled Phase Shifter
Conclusion
This application note has provided information for
video, audio, and data acquisition switching system
designers. Using the DG534 and DG538 microprocessor-compatible multiplexers from Siliconix simplifies
the design task and improves system performance.
III
13-23
AN88-1
. , . Siliconix
incorporated
~
APPLICATIONS FOR THE 0469
A HIGH CURRENT POWER
DRIVER
James A. Harnden
January 1988
INTRODUCTION
Many applications operate MOSPOWER devices as
ON/OFF switches. In applications where device
switching speed is of less concern and the
MOSPOWER device' =? gate capacitance (C Iss) is sufficiently low, they may be driven directly by logic devices such as CMOS or TTL with a pull-up resistor.
The prime advantages that encourage use of
MOSPOWER devices over bipolar transistors however', is the efficiency gained from reduced rDS(ON)
voltage drop and increased switching speeds. The
gate of a MOSPOWER device is capacitive (C Isal. The
value of C Iss is directly related to the devices size
and switching speed is directly proportional to the
gate driver's output impedance (R/C). To take advantage of the increased switching speed of larger
MOSPOWER devices, a more robust driver than simple logic devices is requireq.
The 0469 was designed as an optimized driver for
MOSPOWER devices. It contains four independent
drive channels, and each channel can be configured
as a logically inverting or non-inverting driver. Since
the 0469 is a CMOS device it is compatible with low
power CMOS logic and microprocessors and draws
minimal quiescent current (2.5 rnA). The 0469
switching times (typically 25 ns) are specified with a
500 pF load, but higher capacitive loads may be
driven at the penalty of proportionally increased transition times. Output impedance of the 0469 (both
pull-up and pull-down) is typically less than B n, permitting peak (transient) charging currents of approximately 1.2 amps (at low duty-cycl~s) .
Applications Of The 0469 Quad Driver
The 0469 quad driver is well suited to applications
such as motor drives. Motors ranging from fractiol1al
to integral horsepower can be driven directly with
MOSPOWER devices. The 0469 provides optimized
gate drive signals and simplifies interface to the logic
level control circuitry.
100 V
0469
1"----,
. . _--_..1
Figure 1.
13-24
Unipolar MOSPOWER Stepper Motor Drive
trr
~
AN88·1
Siliconix
incorporated
Figure 1 illustrates a "unipolar" configuration widely
used in stepper motor drives. In this application the
MOSPOWER devices are operated as "low side"
switches with their sources, and the 0469 gate
driver, referenced directly to ground. Oiodes 01 - 04
protect the MOSPOWER devices from overvoltage as
a result of flyback voltage generated by the motor
winding when a MOSPOWER device is turned off.
MOSPOWER devices offer distinct advantages in lowvoltage motor drive applications. Mobile, battery
powered applications such as automotive, aircraft,
boats, satellites, missiles and mobile robotics are improved by the efficiency of MOSPOWER devices.
Power consumed during transition decreases motor
performance and increases heat that must be dissipated. New low ON resistance MOSPOWER geometries increase current handling capability for a given
heat sink or decrease heat sink requirements at any
given current level. Using an efficient gate driver like
the 0469 can further increase efficiency by minimizing quiescent current and transition times as well as
providing sufficient gate voltage to minimize the
MOSPOWER devices rOS(ON} voltage drop.
12V
1
P-channel MOSPOWER devices are now available with
breakdown voltages up to 500 V. As figure 3 illustrates, driving the gates of P-channel high-side devices in a high voltage bridge is slightly more complex than the previous low voltage applications, but
still considerably less complex than when n-channel
high-side switches are used. Although P-channel devices typically cost more then N-channel devices for
a given rOS(ON} rating, the added device cost is
often offset by the inexpensive gate-drive circuitry.
In figure 3 a depletion mode device is used as a series linear regulator to create a power supply 12 V
below the bridge power supply, to power the 0469
MOSPOWER gate driver. Current through the series
regulator can be calculated based on the average
current needed to drive the total gate capacitance at
the percentage of the total duty cycle, plus the quiescent current of the 0469. Capacitor C1 supplies
the peak current needed for transient (gate drive)
conditions.
One particular advantage inherent to this drive technique is that it holds the P-channel upper devices
"normally OFF". Absence of a gate drive signal results in the gate-source of Q1 clamped in a safe (low
impedance) state. This gate drive technique provides
a safe "power-up" condition, as well as additional
failure protection should the low supply voltage be
interrupted during operation.
The "All N-Channel" Half-Bridge
Figure 2. Low-voltage Complementary
MOSPOWER H-brldge
In figure 2 a low voltage H-bridge configuration is
demonstrated which provides the motor with bidirectional (bipolar) current drive capability. This arrangement works particularly well in applications that
use a single 12 volt battery to power the motor and
electronics. By using N-channel MOSPOWER devices
as "low-side" switches (sources referenced to
ground) and P-channel MOSPOWER devices as
"high-side" switches (sources referenced to the battery voltage) the gates of all four devices can be
driven directly by one 0469 quad MOSPOWER driver.
Bridges using N-channel devices in both the upper
and lower switch locations always offer advantages
when pushing the "state-of-the-art". The lowest
rOS(ON} and highest breakdown voltage MOSPOWER
devices in the marketplace will always be N-channel.
N- channel material offers more than twice the current-carrying efficiency (carrier mobility) of P-channel material, per unit area. A P-channel device of
comparable current, voltage, and rOS(ON} ratings,
constructed with comparable cell density, will be
more than twice the die area of its N-channel complement.
Using N-channel devices in the upper quadrants of
the H-bridge complicates gate drive. The gate of the
N-channel device must be 10 to 12 V positive (with
reference to its source) to turn the device fully ON. In
a half-bridge, the high-side N-channel device's
source may be at any voltage between a diode
13-25
III
AN88-1
..,. Siliconix
incorporated
~
drop below ground and a diode drop above the motor
drive voltage. To drive the gate properly, a separate
voltage must be generated that is referenced to the
high-side N-channel device's source and capable of
going at least 10 volts above the motor voltage.
In Figure 4, a JFET (03) is used to provide the Pchannel power MOSFET with low gate-source impedance when turned OFF. The J107 has an rOSION) rat-
ing of less than 10 .n when the gate-source voltage is
less than 4.0 V (minimum cutoff-voltage). Zener diode 01 protects the P-channel power MOSFET gatesource from excessive voltage. Zener diode 03 protects the gate-source of JFET 03 from excessive voltage when 04/05 are ON. The CR100 (02) is a constant-current (1.0 rnA) diode used to turn the JFET
(03) ON when 05 is turned OFF.
200 V
l2V
~
1. _ _ _ _ .1
Figure 3. High-Voltage Complementary MOSPOWER H-brldge
500 V
02
CR100
l2V
Y--,
r--
r ~05
ct.D-t>: 1R31!9r9
I
t
~I
LOGIC
INPUTS
R1
'r
07Fj
~~--------------~~----~
I
I
I-=-
Figure 4. "JFET Clamp· for High-side P-Channel Gate Drive
13-26
AN88·1
...... Siliconix
.£II incorporated
04,
Qs, R 1, R 2, R3 and C1 form a bi-Ievel current
source used to drive the JFET clamp (Q3) and upper
P-channel power MOSFET (Q1). When Q4 and Qs are
driven on by the preceding logic, they initially source
current at a level set by R 1 and R 2. The gate D3
drives the P-channel gate to a voltage level clamped
by diode D1, turning the power MOSFET (Q1) ON. After the power MOSFET is turned ON the current
source value is reduced by approximately an order or
magnitude to maintain the power MOSFET's enhancement voltage. Peak current timing is set by the
time constant of R3 and C1 and the maintenance current level is set by the value of R 2 .
When the current source driver is turned OFF, constant current diode D2 pulls the gate of JFET Q3 to
the high voltage rail, turning Q1 OFF. The P-channel
devices gate is driven OFF at essentially the same
rate as the rise of Q3'S gate, and held securely OFF
by the low impedance of Q3. JFETs (or N-channel depletion mode power MOSFETs which could also be
used in this circuit) can easily provide ON resistance
low enough to prevent transients on the MOSFETs
drain (dv/dt) from generating enough voltage at the
gate to allow spurious turn-ON.
In Figure 5, a high frequency oscillator (100 kHz) and
a small bi-filar wound pulse transformer are used to
form floating 12 V power supplies, referenced to the
source of each upper N-channel device. The value of
supply capacitors C1 and ~ are chosen based on
capacitance values of the N-channe,1 gates being
driven, the duty-cycle and the quiescent current of
100.0.
the floating opto-coupler buffer and emitter follower
output buffer stage. Diodes D1 and D2 are added to
protect the power MOSFETs gate from overvoltage
conditions. An opto-coupler is used to isolate gate
drive signals, and the emitter follower output stage
provides low impedance gate drive.
The high-side drive configuration in Figure 5 allows
"static" operation. The high-side N-channel devices
can be held ON in a steady-state condition, providing
a switching range from dc to the maximum bridge
operating frequency. The oscillator operates continuously to provide power for the two floating gate-drive
supplies. In this arrangement, the pulse transformer
can be driven at a much higher frequency than the
modulation frequency, making the transformer
smaller and less critical than in configurations that
drive the gate directly through a pulse transformer.
A dynamic "bootstrap" gate drive isolation technique
is demonstrated in Figure 6. Dynamic isolation is
compatible with several styles of motor drive and
current control that result in continuous modulation. If
dynamic gate drive techniques can be applied they
often result in reduced cost by eliminating high cost
items such as high performance opto-isolators. This
configuration of isolation has one other inherent feature when compared to the floating power supply
technique discussed previously. When the upper
MOSPOWER device is turned OFF, its gate is
clamped to the source (by low-impedance P-channel
device Q2) to prevent spurious dv/dt turn-ON (See
Siliconix MOSPOWER Applications Handbook - dVDS/
dt Turn-ON in MOSFETs).
100.0.
II
LOGIO
INPUTS
II~
Figure
s.
All N-channel Bridge with Opto-Coupled Logic Signal
13-27
AN88-1
. , . Silica nix
incorporated
~
500 V
R3
R1
06
C2
Q6-f
LOGIC
INPUTS
Figure 6. Bootstrap High-side N-channel Gate Drive Isolation
In operation, when 01 is turned ON, the P-channel
clamp (02) assures the gate-source of 04 remains
shorted. While 01 is ON, 05 (the lower output
MOSPOWER device) will be turned ON. The bootstrap
capacitor is then charged from the low-voltage supply, via D1 and 05. When 01 is turned OFF, 02 is
also turned OFF releasing the clamp across 04'S
gate-source. R1 is allowed to pull the gate of. 03
high, turning it ON. This switches current into the capacitive gate of 04, via D 1, 03 and D3. As 04 begins
to turn ON, voltage at the source begins to rise toward the positive motor drive voltage. As it rises it
carries with it the reference (low) end of the bootstrap capacitor. D 1 (which has to be a fast recovery
diode) reverses, protecting the bootstrap capacitor's
charge. Above this point, remaining gate charge
must be supplied by the bootstrap capacitor, which
must be at least an order of magnitude larger than
the MOSPOWER gate capacitance (04) being driven.
When the upper MOSPOWER device (04) is fully enhanced, the source will be an rDS(ON) drop below the
motor drive voltage and its source will be held at the
voltage potential remaining in the bootstrap capacitor, minus voltage drops of 03 and D3. The leakage
current of MOSPOWER device (04) will limit the
amount of time a high level can be maintained without allowing the stored capacitor voltage to "droop"
13-28
to a dangerous voltage level. As a general rule, 8
volts is a reasonable (absolute minimum) gate drive
voltage droop to allow. With less than 8 volts of gate
drive, the rDS(ON) of 04 will increase rapidly, increasing power dissipation and motor drive voltage
losses.
Summary
Designing a power MOSFET bridge for a motor drive
application requires, as with any power circuit, an understanding of economic and performance requirements. Both design requirements will impact the selection of an "optimized" gate drive technique for the
MOSPOWER devices. Some methods of isolating the
high-side gate drive are advantagous at low voltages
but become inefficient or otherwise unsatisfactory at
higher voltages. Other isolation techniques work well
over a wide range of voltages but are less economical. Still others provide economic advantages but are
incompatible with the controller's modulation
scheme. Each isolated high-side gate drive technique will be well suited to a range of applications
and less than the optimum choice in others. As demonstrated in this applications note, most of these
gate drive circuits can benefit from a flexible and
economical integrated circuit such as the D469
CMOS quad driver.
5a,',) Siliconix
incorporated
~M~ROVE SVS1TEM IPREC~S~ON
\i\f~TH THE S~1652 CHOPPER·STAB~UZED
OIPERAT~ONAl AMPUF~ER
By Carl Jones and Steve Moore
June 1987
Conventional Op Amp Limitations
The performance of standard operational amplifier
circuits is significantly limited when operating with
low-level dc signals. These limitations are caused by
the relatively large voltage and current offsets of
conventional op amps. The most significant source
of error is the input offset voltage, Vas. Even a lowoffset op amp, such as the OP-05, has a typical Vas
of 70 /lV. This offset voltage produces an output error of 70 mV with a circuit gain of 1000. To reduce
this error, most standard op amps offer offset nulling
terminals. Offset nulling is accomplished by connecting a potentiometer across the nulling terminals and
trimming the offset to an acceptable value. This procedure is time consuming and expensive because
the potentiometer for each op amp must be individually adjusted.
Figure 1. An Operational Amplifier In an
Inverting Configuration - Equivalent Circuit
Another problem associated with op amps operating
with dc signals is offset drift. Because Vas drifts over
time, the potentiometers must be periodically re-adjusted. This re-adjustment is both expensive and inconvenient, especially with remotely located circuits.
Vas also drifts with changes in temperature, and in
some cases, the drift can be hundreds of /lV/DC.
This temperature drift is a major limitation when amplifying low-level dc signals in an unstable temperature environment.
In addition to the input offset voltage, there are also
offset currents which induce errors at the output. The
difference in these currents is called the input offset
current (Ios)and the mean los value is called the
input bias current (I B). The output offset caused by
these small currents depends on the feedback elements and input drive impedance. Figures 1 and 2
show the relationship between the previously discussed input offsets, the feedback network, and the
resulting output errors.
TOTAL OLrrPUT OFFSET
~
( 1+
~
) {VOS+ lOS x Ra }
Figure 2. An Operational Amplifier In a NonInverting Configuration - Equivalent
Circuit
13-29
~
~
AN87·4
The SI7652 Solution for Precision Performance
The 8i7652 is designed specifically for low-level dc
applications. With a maximum input offset voltage of
5 JJ.V (0.7 JJ.V typical), the 8i7652 offers designers
dramatically improved Input resolution. Also, both
the temperature and the time drifts in Vos are virtually eliminated. Thus, the external trim potentiometer
and the costly and Inconvenient periodic adjustments
are unnecessary.
To achieve these performance features, the 817652
utilizes a differential "chopper-stabilized" approach.
However, unlike previous chopper amplifiers, the
main amplifier Is always connected to the output of
the device. This allows the 8i7652 to operate without
the large output glitches that occur with traditional
chopper amplifier designs. Careful design of the
switching circuitry has minimized the charge Injection
errors that are normally associated with chopper designs. The design used for the 8i7652 has excellent
common-mode rejection ratio (CMRR) and power
supply rejection ratio (P8RR) ratings, which are both
typically 130 dB.
Built with the 8i1iconix PolyM08 process, the M08FET
input devices of the 8i7652 require extremely low
bias currents and have low Input offset currents,
thereby minimizing another potential source of error.
Additionally, the 8i7652 has extremely low noise. The
input 1/f noise (low frequency) is typically less than
0.2 JJ.V (p-p). The input noise current is a negligible
0.01 pA/.J'Hz .
8i1iconix
incorporated
Another valuable feature of the 8i7652 is its very high
open-loop voltage gain (AvOL), specified at a minimum of 120 dB (typically 150 dB).
The Si7652 Chopper Operation
The very low input offset voltage of the 8i7652 is
achieved by using an internal nulling amplifier which
alternately nulls itself and the main amplifier. A diagram for the basic procedure is shown in Figure 3,
and the operating sequence is explained below.
Period 1: Initially, switch A is closed and switch A is
opened, thus short-circuiting the inputs of the nulling
amplifier. Any dc voltage at the output of this amplifier is due to offsets within the amplifier.
Period 2: After allowing the output of the nulling amplifier to settle, switch B is closed. The appropriate
nulling potential is then applied to the nulling amplifier. The external capacitor, CEXT A, stores this potential for the second half of the complete cycle.
Period 3: 8witches A and B open, and switch A
closes. This connects the inputs of the nulling amplifier across the inputs of the main amplifier. Since the
offsets of the nulling amplifier have already been corrected, the output is now due to the main amplifier
offsets.
Period 4: By now, the output of the nulling amplifier
has settled. 8witch C is now closed and a correcting
potential is applied to the main amplifier. This potential is stored on CEXT B while the procedure is repeated.
PERIODS
os~'tlsO~
Y
P
+IN
o_-,.--------1
(2)
I (3) I
(4)
I (1) I
~1.~I~--t~~t--~t~.1
rl~I~--~
OUTPUT A-
1>-1-+-0
~No__+~~------I~
I (1) I
r~~--~
I
t
A-jI-i-~
TiEXT
CLKIN
I
CLKOUT
C-
Figure 3. Functional Block Diagram
13-30
H"'--__ _
" , - I_ _ _ _ _
AN87-4
..,. Siliconix
incorporated
~
All logic signals required to drive the switches are
derived from an internal, 400-Hz, oscillator. The
14-pin version of the Si7652 provides the option of
using an external clock. The external clock input may
be used to synchronize the 8i7652, switching to the
system clock to reduce the effects of the input
switching glitch.
VBla.2
Clamp Circuit Prevents Overload
Recovery Delays
The basic inverting amplifier configuration is shown
In Figure 4. If the input signal is within the correct
operating range (determined by the supplies and the
gain), then the differential input at the 8i7652 inputs
(IIdlff) is virtually zero. However, during an overload
condition, the amplifier output stage saturates and
can no longer drive the feedback network which
maintains accuracy. For example, consider a case
where R1 = 1K, R2 = 100K (this gives a closed-loop
voltage gain (Av) = -100), and supply rails of ±5 V.
An input voltage (II I) of 100 mV will result in an output voltage of 100 mV x -100 = -10 V. This voltage,
however, is beyond the range of the power supplies,
and the output saturates at -5 V. The feedback network applies a voltage which is less than the voltage
required to malntainVdlff at zero. The nulling amplifier
can only interpret this voltage as an offset, and when
it attempts to correct for the offset, the external capacitor, CEXT B, is charged to the supply rail. When
the amplifier comes out of saturation, it may take
several seconds to discharge the external capacitor
and restore operation of the chopper.
INPUT
mentary MOSFETs in parallel. The common sources
of the parallel M08FETs are tied to the output, and
their common drains are brought out via the clamp
pin.
-\~
>---+------i-oOUTPUT
t-----t--o
VBla.' - \
Figure 5.
CLAMP
14--
The Use of Complementary MOS
to Implement an Output Clamp
The gate threshold voltages are set so that one of
the MOSFETs turns on when the output swings within
a few hundred millivolts of a supply rail.
If the clamp pin is connected to the summing point of
the amplifier, the MOSFETs are effectively in parallel
with the feedback resistor (R2). As the output approaches one of the rails, the clamp MOSFETs can
be considered variable resistors, reducing the gain of
the amplifier (see Figure 6). The effect of using the
clamp on the overload recovery time is shown in Figures 7a and 7b.
R,
V IN o--WIr-I'-I
OUTPUT
>--+-'-'too·Vo
ros
>--4--0Vo
Vdllf
= \b. R, + VI' fl2
RJ+fl2
III
D.' J.LF
Figure 4. Basic Inverting Amplifier
Figure 6.
Reduction of Gain Resulting From
the Clamp Connection
To overcome the overload recovery problem, the
14-pin version of the Si7652 includes an output clamp
circuit (Figure 5). This consists of the two comple-
13-31
W1P" Siliconix
AN87·4
~
Input
5 mV/dlv.
Output
2 V/dlv.
5 ms/dlv.
incorporated
semiconductors are connected, a small potential difference, or EMF, is produced across the junction.
This EMF increases as the temperature increases.
Thermal EMFs can be as large as a few /lV, a significant value for low-level signals. Also, these EMFs
can vary by as much as a few /lV/oC, causing additional drift errors. To avoid offset errors due to thermal EMFs, it may be necessary to add junctions.
Since the amplifier is differential, the number of junctions must be equal before each input. An example
of this design is shown in Figure 8.
An Oscillograph Showing the
Overload Recovery Time
Without Clamp
Flguro 7a.
Vo
.. ;'
. ",: :.:'"
.
.;'
"
:: J.':':;":':' ';" . :i:,·:: .. '
,:.. :::~.
..... .. .. " .
·.d .. ..
,
,
Input
5 mV/dlv.
Output
2 V/dlv.
:;.:,' :":,'
~
t .. ' , '
,
.,,'
'
5 ms/dlv.
Figure 7b.
An Oscillograph Showing the
Overload Reoovery Time With
Clamp
The clamp circuit has already been discussed as a
means of minimizing the overload recovery time of
the capacitors. Another method is to inhibit capacitor
charging during an overload. In the Si7652, this
charging is inhibited by detecting the overload conditions and applying a low strobe signal to EXT ClK IN
for the duration of the overload.
o - Resistor Lead/Solder/Copper Junction
o - Copper/l\<>lder/I.C. Lead Junction
o
- Junction Introduced for Thermal Balance
Figure B. Using Junctions to Equalize
Thermal EMF's
To balance the temperature effects apparent at the
inputs, it is important to design a symmetrical circuit.
lead lengths on components ahead of the inputs
should also be equal. Figure 9 shows a test circuit
which illustrates these design features.
50 k.o.
0.1 JiF
Tips for Ensuring Precision Operation
In systems that resolve microvolts, errors that are
often ignored must be taken into consideration.
Three of the most common error sources are: thermally generated error voltages [thermal electromotive force (EMF)]. leakage currents, and transformer
fields.
Thermal EMF is usually the main error source in lowlevel signal applications. Whenever two metals or
13-32
>_---1 VOS x 1000
Figure 9. A Thermally Balanced Test Circuit
AN87·4
a"F' Siliconix
~
incorporated
Placing high-power dissipative (Le., hot) circuit elements away from the chopper-stabilized amplifier is
one precaution. Fans are another source which create large temperature gradients. If cooling is necessary, another method should be employed.
Leakage Effects
Leakages from circuit elements such as diodes and
capacitors must be carefully considered in high-impedance systems. Additionally, leakage from contaminated PC boards and sockets can cause unforeseen errors at the microvolt level. Input guarding, as
shown in Figure 10, may be necessary.
consideration when using a chopper-stabilized amplifier. The wideband frequency of the device deteriorates when the load impedance is less than the typical output impedance of 18 K. Therefore, load impedances should be greater than 18 K. In this case,
the open-loop response will be 20 dB per decade
from 0.1 Hz to 500 Hz with phase shifts less than 2°
in the transition region where the main amplifier takes
over from the nulling amplifier. No problem occurs
with dc input signals, since the dc gain is typically
greater than 120 dB even with the load impedance of
only 1 K.
Latch-Up-Free Operation
External
Il(~
8'
1
Output
IIBI:> 6
Bottom View
All junction-isolated CMOS devices inherently contain
parasitiC SCR pnpn structures. If the SCR is turned
on, excessive supply current may be drawn, thus destroying the device. However, if no voltage exceeds
any supply voltage by more than 0.3 V, excessive
supply current is not drawn. In addition, the power
supplies should reach their operating voltages either
before or at the same time as the input signals. If
one of these fault conditions occurs, the input current must be limited to less than 1 mA to avoid latchup.
Simple Application Circuits
Board layout for Input guarding with T0-99 package.
Figure 10.
Guarding the Input From
Board Leakages
Figures 11 and 12 show the Si7652 in the basic inverting and non-inverting amplifier configurations.
The connections for the optional clamp circuit are
also shown.
Transformer Fields
Electromagnetic fields are another source of error
when dealing with low-level signals. If possible, transformers should be placed on a different board than
the chopper-stabilized amplifier. If space restrictions
or high-quality grounding requires that a transformer
be mounted near the amplifier, use a shielded transformer. If shielded transformers are too costly, careful layout can often produce acceptable results.
INPUT
Q-'1I\I\~~-I
~~--I~ OUTPUT
1 =100k.n.
For Full Clamp Effect
It is also advisable to keep low-level signal paths as
short as possible and to keep high-energy circuitry
away from the low-level signal path.
Output Loading Considerations
Because the open-loop gain is proportional to the
output load, output loading is an important practical
(R t /R 2
0.1 J1F
Figure 11. The SI7652 Configured as
an Inverting Amplifier
13-33
AN87-4
WY'Siliconix
incorporated
~
0.1 J.lF
Increasing the Output Range
INPUT
0----1
>--1~~ OUTPUT
A simple circuit used to boost the Si7652 output is
shown in Figures 13 and 14. These figures show
both the inverting and non-inverting configurations.
To ensure stability, it may be necessary to use a
small capacitor (10 nF), as illustrated. With these
configurations, the precision input characteristics of
the Si7652 are maintained while achieving the output
voltage and current range of the output op amp.
R3 + ( Rl I R2 ) = 100 k.n.
For Full Clamp Effect
Figure 12. The 517652 Configured as
a Non-Inverting Amplifier
+5V
-11INPUT
+15 V
o-'l/lJ\~--I
>-1--- OUTPUT
-15 V
0.1 J.lF
Figure 13. An Output Boost Circuit for The 517652 (Inverting configuration)
13-34
~
~
AN87·4
Siliconix
incorporated
tSV
INPUT 0-----1
C>---..._---. OUTPUT
-15 V
0.1 J.LF
-11- -
_I
C
Figure 14.
An Output Boost Circuit for The 517652 (non-Inverting configuration)
Figure 15 shows the use of analog switches with the
Si7652 to allow a number of inputs and lor gains to be
digitally selected. A variation of this concept may
also be used to produce a programmable precision
voltage reference suitable for A/O and 01 A converters. A circuit for this application is shown in Figure
16.
+15 V
12
VIN1
VIN2
CH1
DG200A
10
5
+15 V
14
13
CH2
DG201A
7
RF3
100 k,o,
15
-15 V
10
GAIN = RF
+ RG
7
RG
GAIN 1 (X1)
GAIN 2 (X10)
GAIN 3 (X100)
GAIN 4 (X1000)
III
Ol--------.!~----_---1r-________..:;10, INPUT HI
INPUT LO
Bl
99 k,o,
2.2 AF
1.0 AF
Figure 17. The Sl7652 as a Pre-amplifier For an AID Converter
v-
v+
GND
0.1 AF
51
52
INPUTS
53
54
55
Si7541A
56
DIA CONVERTER
87
Sa
DIGITAL
I OUTPUT
DATA
A2
Al
AO
512504
EN
DGSoaA
a-CHANNEL SINGLE ENDED MULnPLEXER
SUCCESSIVE
'------l~ APPROXIMATION
REGISTER
Figure 18. Data Aqulsltlon System
The Si7652 has an input impedance of 10 12 and an
input bias current maximum of 30 pA. The Si7652
may be used as a unity-gain buffer between the multiplexer output and the AID converter input. This configuration reduces system sensitivity to variations in
the multiplexer's on-resistance to the point where
those variations contribute a negligible error.
Sample-and-Hold Applications
In the same data acquisition system, if the input sig-
nal varies during the AID conversion, an error, which
is dependent upon both the speed of the AID converter and the slew rate of the incoming signal, is
generated. A sample-and-hold circuit, shown in Figure 19, reduces this error by taking a sample of the
input signal and holding it constant during the AID
conversion. The sample-and-hold performance is determined by the speed of the analog switch, the
charge injection of the switch, the size of the hold
capacitor, and the input bias current and offset voltage of the op amp.
13-37
~
__
AN87·4
~
~
leakage. Better droop rate can be achieved with a
slight loss in acquisition speed, using the OGP201A
precision analog switch in place of the OG271.
0.1 JLF
r-------,
INPUT
8i1iconix
incorporated
~-"'tl--t-_-I
L ___ +__ .J
By offsetting the supplies of the 8i7652 as shown, Y,N
will range from 0 to 12 V.
OUTPUT
TTL--------J
Low Offset Maintains D/A Linearity
Figure 19.
Basic Sample-and-Hold Circuit
The output amplifier performance often limits the D/A
converter accuracy. The popular CM08 0/ A converters show an output impedance which is code-dependent, and thus, any offset voltage generated by
the O/A output amplifier results in a combination of
system offset and nonlinearity which Is Impossible to
trim out. Figure 21 shows the 8i7652 used as an output amplifier that performs the current-to-voltage
conversion for an 8i7541 A 12-bit 0/ A converter. The
low offset voltage of the 8i7652 is critical to maintaining system linearity.
Precision Sample-and-Hold Amplifier
The precision sample-and-hold circuit shown in Figure 20 uses a OG271 analog switch in conjunction
with the 8i7652. The OG271 is a high-speed switch
(t on/off < 75 ns) with very low charge injection (typically 9 pC). Also, to further reduce the effects of
charge injection, a capacitor (C1) is added to cancel
the charge-induced offsets (pedestal errors). This
system keeps pedestal error below 5 mV. If greater
accuracy is needed, the capacitor (C2) can be adjusted to totally cancel the coupled charge offsets.
The size of the hold capacitor is based on a compromise between input tracking time and droop rate. Aperture time is approximately 100 ns, and the acquisition time is less than 20 lIS. The measured droop
rate (1 mV/sec.) Is largely due to the analog switch
To demonstrate the importance of a low-offset, lowdrift output amplifier, consider the effect of using a
biFET op amp in place of the 8i7652. The high slew
rate and low noise of the industry-standard OP-15
make it useful as an output amplifier for the 8i7541A.
The top-grade offset voltage of the OP-15 is 250 fJ.V
at 25°C, and it shows considerable drift over the 0 to
70°C temperature range, reaching a worst-case
300 pF
r-----£~-----------
I
1 nF
81
DG271
VIN o-_-'8::102f-_ _-c....-;
a..-r--t--=---1--I
LOGIC
IN
LOW = 8AMPLE
HIGH = HOLD
0.1 JLF
Figure 20. A Practical Sample and Hold Circuit
13-38
AN87·4
trY" Siliconix
~
incorporated
2 k R1
VREF
voo= +15 V
BIT 1
MSB
18
4
loun
VOUT
10 k.o.
Si7541
0.1 JlF
500.0.
IOUT2
BIT 12
LSB
2
-
10 k.o.
Figure 21. The 817652 Used as a DAC Output Amplifier
value of 10 mV. A 10-mV offset equals 16 LSB in a
12-bit system with a 2.5-V full-scale range. The
linearity error introduced is calculated by dividing the
offset by the deviation in the 01 A output resistance;
the resulting error current is a fraction of the fullscale O/A converter current. The output resistance of
the Si7541 A can vary as much as 5 k!l over the 01 A
converter range. Therefore, with a 10-mV offset from
the op amp, the error current could reach
10 mV/5 kO = 2 I1A. With a 250 I1A full-scale O/A
converter current, the LSB is 250 I1A/4096 61 nA.
Thus, the linearity error introduced is 2 I1A/61 nA,
which equals 33 LSB.
=
The total offset of the Si7652 over temperature is
less than 10 11V, three orders of magnitude lower
than the 10 mV offset using the OP-15. Hence, significant reductions in offset and nonlinearity are
made using the Si7652.
Differential Thermocouple Amplifier
The circuit shown in Figure 22 is designed to measure the low-level outputs of a thermocouple. Thermocouples usually exhibit a thermal EMF between 7 and
75 I1V/oC. These low-level signals require the use of
an amplifier with a low offset voltage and low input
bias current. Also, using the standard instrumentation amplifier ensures high input impedance operation. The Si7652 has a maximum input bias current of
30 pA and an input impedance of 10 12 . Thus, the
measurement error is dominated by the contribution
of the analog switch leakage and on-resistance, in
addition to thermal EMFs as previously discussed.
These errors can be eliminated by using a differential
measuring technique and by carefully balancing the
thermal EMFs in each branch of the differential amplifier configuration. Figure 23 shows how unwanted
thermal EMFs cancel in a differential system. Another
advantage of using a differential system is that other
common-mode errors (e.g., ac noise, leakage offsets, and switching transients) are also rejected. A
temperature reference is also included to provide a
zero reading at the reference temperature (often
O°C). The temp- ature reference subtracts a voltage,
equal in magnitude to the EMF, which would be generated by the thermocouple. There are various methods of obtaining a temperature reference, including
using an ice bath, ice point cells, and electronic coldjunction compensators. Figure 23 shows the effect of
using a temperature reference.
13-39
--=~
AN87-4
..... Siliconix
.r;;;lI incorporated
CH-SELECT
DG403
THERMOCOUPLES
I
_...1
--,
I
L------I--+------!''---h REFERENCE
'---+------"""r--H
JUNCTION
oOC
Figure 22. Differential Measurement of Low Level Thermocouple Outputs
CHROMEL
TYPE K
+
ALUMEL
oOC
Metal Junction
Thermocouple Potentials
Chromel: Alumel
el
Chromel: Gold
rfl.
e3
Alumel:
Gold
The total thermocouple potential seen by the Instrumentation amplifier Is:
- e2 + e2 + el -e3 + e3 -ell
O°C
= el - ell
O°C
Figure 23. Simple Model to Illustrate the Differential Cancellation of Thermal EMFs
13-40
.... Siliconix
incorporated
~
THE Si7541 A 12·BIT CMOS MULTIPLVING DAC
THEORY AND APPLICATIONS
By Jack ArmlJos and Carl Jones
August 1987
INTRODUCTION
Basic DAC Circuit
This application note provides the information
needed to understand CMOS digital-to-analog converter (DAC) operation and to implement successful
designs using the Si7541 A 12-bit DAC. The basic
principles of DACs and their main error sources are
presented. In addition, a detailed description of the
Si7541 A 12-bit DAC and the results of a comparative
study with respect to other presently available alternate sources is provided. A series of application circuits with practical recommendations is then presented. This note ends with and an appendix covering voltage references and resistance ladders.
A basic DAC can be built using a voltage reference, a
set of binary weighted resistors, and a set of
switches (Figure 2). An output amplifier converts
current to voltage and provides a low-impedance
voltage output. In this example, the op amp holds
one end of all switches at 0 V. The currents flowing
through the resistors are binary-weighted. Each
switch is operated by a digital bit, open for a zero
and closed for a .. one ".
BASIC DAC PRINCIPLES
Some of the basic concepts and definitions associated with DACs are best understood by first understanding the function of a simple DAC.
Definition
A DAC is essentially a digitally controlled potentiometer that produces an analog output (voltage or current) that is a fraction of the full-scale setting. The
full scale setting or value is determined by the magnitude of the reference voltage chosen. If the reference changes, the DAC output changes. Therefore,
to improve system accuracy, a precision reference
must be used.
A DAC translates digital data from a data processor
into an analog waveform containing infomation that
can be used in the .. real world". Figure 1 shows a
simplified block diagram illustrating the use of a DAC
to make a computer talk.
Each switch that closes adds a binary-weighted current increment to the summing node connected to
the amplifier's inverting input. The negative output
voltage is proportional to the total current and, thUS,
to the binary value represented by the digital input
code.
For resolutions exceeding 4 bits, this scheme is not
practical. For example, in 8-bit conversion, the required resistance ratio is 128: 1 (e.g., 1.28 MO to
10 kO). If discrete resistors are used, cost and size
are increased, and temperature tracking, matching,
and parasitic impedances become a problem.
/
/'"
COMPUTER
DATA 1,0.1,0
DAC
/'
BLA, BLA, BLA
:--.....
SPEAKER'\
DIGITAL WORLD
ANALOG
...........
(REAL WORLD)
Figure 1. A Basic DAC Application
13-41
B
AN87·3
Bit 1
Bit 2
I
I
Bit n
?
?
?
-1,:
+10 V
I
I
I
VREF
Siliconix
incorporated
I
I
I
0
0
1
mA~
10 k.o.
.5mA
~
20 k.o. _1_ mA ~
2 n-l
VOUT
Figure 2. A Simple DAC Using Binary-weighted Resistors
Typical Specifications
DAC performance is measured in several areas: accuracy (both absolute and with respect to full scale) ,
linearity (both integral and differential), offset, noise,
conversion time, and output transients (glitch Impulse). Also of importance are the long-term stability
of these parameters as well as their sensitivity to
temperature variations.
Transfer function. figure 3 is the transfer function of
an Ideal unipolar 3-bit DAC. It consists of a set of
discrete points, corresponding to all the digital codes
that can be input to the device. A 12-bit DAC, for
example, will have 212 = 4096 points. The ideal DAC
has a linear transfer function; that is, all points fall on
a straight line.
The transfer function can be unipolar (output values
have only one polarity) or bipolar (the output can be
either positive or negative), depending on how the
DAC is configured. Sometimes the reference quantity is a variable input signal. This produces a multiplying DAC since the output becomes the product of
two variables: the analog reference voltage and the
number represented by the digital input code. Both
variables may vary from zero to full scale and have
positive or negative values.
13-42
- - - -- - -
-- - --
I
I
7/8
~ 3/4
1 LSBI
I
I
I
I
I- 5/8
o~
I
I
I
I
1/2
9 3/8
I
,~ 114
I
I
118
I
o
000 001 010 011
100 101 110 111
DIGITAL INPUT
Figure 3. Unipolar Transfer Function
for an Ideal 3-blt DAC
figure 4 shows the transfer function of a bipolar 3-bit
DAC. The digital coding used can be offset binary or
two's complement [the most significant bit (MSB) is
complemented.] In the bipolar mode, the maximum
output value is still 1 least significant bit (LSB) below
full scale (fS), but an LSB is twice as large as it is in
the unipolar mode because the total output swing is
now (2 FS - 1 LSB).
AN87-3
.... Siliconix
incorporated
~
-- ----
- - - - "'j
3/4
1---1--+--/--+--1---1---..-.....
~ 3/4
1/4
5
-1/4
5/8
CI
112
~z
1---+--/--~--1--+-+--I---,
.:
~ -1/2 1---11-.....----+-+-+-+-+_---'
-3/4
~
1Lal
,
,,
D
ol---lf---I---+--+-+-+-+--~
9
-
~ 7/8
~ 1/2
~
- --
c
--r
OFFSET
ERROR
I---'----+--/--+--I---t--+---,
3/8
,,
1/4
,
,
1/8
...L
o
-1~~--~~--~--~~--~~000 001 010 011 100 101 110 111
100 101 110 111 000 001 010 0114---+...,
,
,
,,
,,
,
~
,,
I
I
- - ,- ..
,,
,
I
I
,
I
I
I
I
I
I
I
I
IDFAL
I
I
I
I
000 001 010 011 100 101 110 111
DIGITAL INPUT
DIGITAL INPUT
Figure 5. An Offset Error of +2 LSB
Figure 4. Bipolar DAC Transfer Function
Resolution. Resolution refers to the number of different output voltage levels that the DAC can produce.
It also indicates the number of digital input bits.
(Twelve-bit DACs resolve the full-scale range into
4096 states.)
Monotonicitv. The output of a monotonic DAC is one
that either increases or remains constant for increasing input so that the output will always be a single-valued function of the input. This is an important specification, especially in automatic control applications.
Gain Error. Figure 6 shows the effect of gain error. In
this case, the slope of the transfer function differs
from the ideal DAC. Gain error or full-scale error is
measured with an all ones input code.
-- ---- - -- -
I EAL..
~
7/8
I-
3/4
I-
5/8
~
::J
1 Ls1
c
I!I
9
.:
Z
c
112
3/8
1/4
Accuracy. The absolute static accuracy of a DAC
refers to how closely its transfer function follows the
transfer function of an ideal DAC. Three types of
error are used to quantify the accuracy of a DAC:
offset, gain, and integral (non-)linearity errors.
1/8
o
,
,
,,
,
,,
,
,
,,
,
,,
,
,,
- - - ,- ,
,~'
I
I
I
I
T
GAIN
'ERROR
I
I
I
I
.-l
I
I
I
I
I
000 001
010
011
100 101 110 111
DIGITAL INPUT
Figure 6. A Gain Error of -3 LSB
In many applications, adjustments can be made to
trim out or compensate for the offset and gain errors
by providing endpoint auto calibration. On the other
hand, it is usually impractical to compensate for
linearity errors.
Offset Error. Figure 5 shows the result of offset error. The transfer function is parallel to the ideal but
offset by 2 LSBs. (For a unipolar 12-bit converter,
1 LSB =VREF 14096).
Relative Accuracy. This term is also known as integral non-linearity, integral linearity error, or endpoint
linearity. Relative accuracy is the maximum deviation
from a straight line drawn through zero and full-scale
at any point in the transfer function. It is measured
after adjusting for zero and full-scale errors, and can
be expressed as a percentage of full-scale range or
(sub) multiples of 1 LSB. Figure 7 illustrates non-symmetrical integral linearity errors.
13-43
III
AN87·3
FS
.",. Siliconix
incorporated
~
-- -
~I~E;~ ~N~L;~~ ~~
- -
71 8
NONLINEARITY
> 1/2 LSB
14
18
12
18
14
I~V
NO 1
OFFSET
0
./
• /'/
V
000 001
~
010
~
",
FULL-SCALE
CALIBR ATION
~~
~
,,
,
,
,
,
,
,
011 100 101 110 111
DIGITAL INPUT
Gain Trim Circuit. One may compensate for gain error and the ideal full-scale value may be restored by
using a fixed resistor and a trim potentiometer, as
shown in Figure 8.
The maximum values for Rl and R2 may be calculated using
21el Rmax
Rl max -'-"'--'-:-=--100
e
Gain Temperature Coefficient (Gain TC). Most modern CMOS DACs have gain TCs on the order of
±5 ppm/oC. This specification is used to determine
the worst-case gain variation caused by temperature
variations and the difference between TCs of the
feedback resistor and the R-2R ladder. The worstcase corresponds to a 10°C segment of the total
temperature range. For a temperature variation from
-25 to 125°C, the average TC is generally better
than ±3 ppm/oC. However, for worst-case analysis, it
is often assumed that the worst-case gain TC applies
over the whole operating temperature range.
R2
DATA
Figure 8. Gain Trim Circuit for CMOS DACs
13-44
= gain error
(%)
The TCs of the DAC, of the external resistors R1 and
R2, and of the operational amplifier cause variations
In the full-scale output with temperature. The TCs of
the R-2R ladder and the feedback resistor are approximately -300 ppm/oC; however, careful design
allows their ratio to track so the total effect is better
than a ±5 ppm/oC TC.
The worst-case additional TCs due to Rl and R2 are
-21el Rmax
100 R min
Rl
R2
=
+Iel Rmax
100 Rmin
('Y 1 - 'Y)
('Y 2
-
'Y)
where Y = TC of the DAC resistor material
in ppm/oC Yl and Y2 = TCs of R1 and R2,
respectively, in ppm/oC
If Rl and R2 have the same TCs, the overall additional TC is given by
additional TC
R1
max
2
where R max = maximum specific
value of the R-2R ladder (VREF max)
Figure 7. Non-symmetrical Integral LInearity Errors
pifferential Non-linearity. Also known as differential
linearity error, differential non-linearity is the maximum deviation of any analog output step between
adjacent input codes, from the Ideal step value of
1 LSB. Differential non-linearity is a quantitative
measure of monotonlcity. It is also a measure of the
maximum step size. A specified differential nonlinearity of ±1 LSB maximum over the operating temperature range guarantees monotoniclty.
= Rl
R2 max
= R2 R- Rl
The potentiometer's TC usually varies with setting,
making it difficult to match the TC of the fixed resistor. Therefore, it is advisable to use "select-on-test"
fixed resistors for R1. To minimize the additional TC
.-r Siliconix
~
AN87-3
incorporated
introduced by the trim components, it is preferable to
use devices with an improved figure of merit.
figure of merit =
Leakage from VDD produces a parallel shift; whereas,
leakage from the analog switches tends to produce a
rotation of the transfer function.
lei R max
Rmin
For instance, selected 12-bit DACs specify gain errors of ±1 LSB at 25°C. This represents more than a
twelvefold improvement in the figure of merit. For
most applications, this tight specification either eliminates the need for gain trimming or makes R1 and R2
so small that the additional TC becomes negligible.
Leakage Effects on Gain. In precision applications,
gain error shifts with temperature can also be caused
by op amp offset and input bias drifts, changes in
VREF, and leakage currents.
VOUT
NEGATIVE
SHIFT
INCREASES
WITH
TEMPERATURE
POSITIVE
Figure 10. Gain Shift Due to OFF-switch Leakage
The lOUT leakage current effect on gain is negligible
at and below room temperatures, but above 100°C,
the effect of leakage on gain Is considerable. Leakage has two main sources:
1. Leakage which is fairly constant and independent
of input code, comes from the VDD supply.
2. In the off state, leakage comes through switches
from the R-2R ladder. For an all-zeros input code,
this leakage has a maximum effect because all
switches are off; however, when there are all ones at
the input, a minimum effect results. The leakage current magnitude is a direct consequence of fabrication
process, chip layout, and operating temperature.
Although exaggerated, Figures 9 and 10 illustrate the
gain shifts produced by the two types of leakage and
for the two polarities of VREF.
VOUT
SHIFT
INCREASES
WITH
TEMPERATURE
With a negative VREF, the two leakage effects tend to
cancel each other near zero and give a net gain decrease at full scale. However, the trim resistors R1
and R2 introduce a positive TC; the combined result
is a reduction in gain variation with temperature.
For positive values of VREF, the two leakage effects
and the TC of R1 and R2 are added, producing more
gain variation with temperature than occur with negative reference applications.
Leakages can also be caused by film residues from
cleaning solvents used during printed circuit board
manufacture. Therefore, such residues should be
avoided for precision DAC applications.
Multiplying Feedthrough Error. Multiplying feedthrough error is an ac error that results from capacitive feedthrough from VREF to OUT1 with the DAC
loaded to all zeros.
Output Current Settling Time. The time required for
the output current of the DAC to settle to within
1/2 LSB for a zero to full-scale digital input stimulus is
known as output current settling time. It is measured
with an RL = 100.0, CEXT = 15 pF.
Digital-to-Analog (DIAl Glitch Impulse. D/A glitch impulse is a measure of the area of the impulse injected to the analog outputs when the digital inputs
change state. It is usually specified as the area of the
impulse in nY-so It is measured with VREF GND and
an LH0032 as the output op amp and the phase-compensation capacitor = 0 pF.
=
Figure 9. Gain Shift Due to Leakage From VDD
13-45
--=~
AN87-3
...... Siliconix
incorporated
~
DETAILED DESCRIPTION OF THE Si7541A
The Si7541 A is a 12-bit multiplying OAC consisting of
a highly stable thin-film R-2R ladder network and 12
single-pole double-throw (SPOT) current steering
NMOS analog switches on a monolithic chip. The binary weighted CMOS level shifters provide low power
TTL/CMOS-compatible operation. An external voltage
or current reference and an op amp are required for
most applications.
The binary weighted currents are switched between
the OUT1 and OUT2 bus lines. thus maintaining a
constant current in each leg of the ladder. regardless
of switch states.
The input resistance at VREF (Figure 11) is always
equal to the "RREF" and is the R-2R ladder characteristic resistance. Since RREF at the VREF pin is constant. the reference terminal can be driven by a reference voltage or a reference current. either positive. negative. or ac. If a current source is used. a
low value TC external feedback resistor RFB is recommended to define the scale factor.
10 k
Figure 12. Simplified Schematic of One SPOT Switch
EQUIVALENT CIRCUIT ANALYSIS
Figure 13 shows the equivalent circuit for all digital
inputs low. All reference current is switched to OUT2.
The current sources I LEAKAGE are composed of surface and junction leakages to the substrate. The
1/4096 current source represents the constant 1 LSB
current drain through the ladder termination resistor.
For the industry-standard 7541A. the output capacitance on OUT2 (with all its switches turned on) is
typically 200 pF. whereas on OUT1. it is typically
70 pF.
10 k
10 k
__. -___ JV\r
n---~F\_--~n,
IREF
~ R
= 10 k.o. -
-
VREF
:=:t~:::~
I
I
6
BIT 1
(MSB)
BIT 2
I
I
I
~-------+6
BIT 3
+
OUT2
OUT1
FFEEDBACK
BIT 12
(LSB)
Figure 11. SI7541 A Functional Diagram
(All Inputs HIGH)
Figure 12 illustrates the typical NMOS SPOT switch
with its associated CMOS level shifter/driver.
13-46
IOUT2
-
-
-
Figure 13. SI7541A Equivalent Circuit
(All Inputs LOW)
The output capacitances are dependent on the digital
input code and vary between the low and high values.
Analysis of the circuit for all digital inputs high. as
shown in Figure 14. is similar to Figure 13; however.
the on-state switches are now on OUT1. resulting in
200 pF at that terminal.
AN87-3
Siliconix
incorporated
H
fications in the industry-standard data sheet. Several
areas showed considerable improvement.
RFEEDBACK
IR~
Bench tests conducted in the Siliconix applications
lab showed that the Siliconix Si7541 A can drop into
sockets using any other manufacturer's devices.
Tests also demonstrated that several improvements,
presented in Table 1, resulted. The highlights from
this table are given below.
,-------1------0
IOUT2
1.
Input/Output Capacitances. The Si7541 A has the
lowest input and output capacitances (considerably lower than the data sheet specification).
This translates into better dynamic performance
(more speed), as seen later.
2.
Input Resistance. The Si7541 A devices showed
the least unit-to-unit variation (± 1%). Low variation helps to reduce gain error over temperature. The vendor A's AD7541ABQ showed the
highest variation of ±8%.
Figure 14. SI7541 A Equivalent Circuit (All Inputs HIGH)
COMPARATIVE ANALYSIS
A comparative study was conducted to verify the
achievement of design goals. Devices from three
other manufacturers were tested against the
Si7541 A. The Si7541 A met or exceeded all the speci-
Table 1. Comparative Chart
Siliconix
Sl7541ASD
8642
Manufacturer
Part Number
Date Code
Input Capacitance:
Max Cln
Output Capacitances:
All zeros:
Cl
C2
All Ones:
(pI)
7
(1)
BEST
(1)
BEST
(1)
(1)
(pI)
(pI)
C2
(pI)
Vendor I
AD7541BD
8625
8.5
(2)
BETTER
(1)
BEST
BEST
106
(4)
BEST
(3)
GOOD
187
GOOD
48
(pI)
Cl
Vendor A
AD7541ABQ
8614
9.3
(4)
GOOD
(3)
GOOD
(3)
BETTER
(4)
WORST
GOOD
160
(2)
BETTER
198
(2)
BETTER
47
(4)
WORST
50
185
42
8.3
(1)
48
77
Vendor P
PM7541EX
8520
98
170
40
148
38
BEST
! 1.5%
(2)
BETTER
9.5 !
0.5%
(2)
BETTER
11 !
8%
(4)
GOOD
8.5 !
0.5%
(1)
(1)
BEST
1.16
(4)
WORST
1.64
(3)
GOOD
1.5
(2)
BETTER
(1)
BETTER
42
(2)
GOOD
88
(2)
GOOD
136
(2)
GOOD
95
(1)
BEST
819
BEST
640
(3)
GOOD
2778
GOOD
1035
(2)
WORST
1030
BETTER
750
(4)
(1)
BEST
NO
(3)
GOOD
(2)
(4)
(1)
GOOD
(1)
NO
GOOD
BETTER
YES
BETTER
3990
WORST
1360
WORST
(4)
BAD
(1)
NO
GOOD
Overvoltage
(1)
BEST
(2)
GOOD
(4)
WORST
(3)
BAD
OVERALL RATING
"(1)"
BEST
(2)
BETTER
(3)
GOOD
(3)
GOOD
Input Res [stance
(k,o,)
Logic Threshold
(V)
Prop. Delay Ip
Ip (ns)
Gilich Impulse
(nV-s)
(1)
Settling Time
(100.01%)
Needs Prot. Schottky
(n)
= Competitive
(ns)
(2)
(4)
15
1.64
(3)
l1li
place
"Disclaimer: Tests were conducted using a limited number of devices. However, the results were consistent for each
manufacturer's parts. and therefore. they are considered truly representative of typical performance.
13-47
AN87-3
3.
4.
..... 8i1iconix
..,!!;lI incorporated
6. Glitch Impulse. The 8i7541A shows the smallest
glitch impulse areas. Figure 16 shows a comparison of glitch impulses between the 8i1iconix and
vendor A's parts.
Input Logic Threshold. All parts tested were TTL
compatible.for V+ = +15 V, and CM08 compatible for lower values of V+. The 8i7541 A showed
a logic threshold of 1.16 V vs. 1.5 V to 1.64V for
other vendors. This guarantees the best noise
immunity for military (O.8-V and 2.0-V) applications.
7. Dynamic Performance. With a slow output op amp
(OP-07) , there is no appreciable difference
among the four manufacturers tested (Figure
17). However, with a faster op amp (OP-27). the
8i1iconix parts produce the smallest overshoots
and settling times (Figure 18). This improves
precise operation and allows higher conversion
rates.
Propagation Delay. The lower input/output capacitances of 8i1iconix DACs allow from 2 to 8
times shorter delays than the DACs made by the
other manufacturers (Figure 15).
5. 8ettlina Time. The 8i7541 A devices settle faster,
more than twice as fast as the slowest device
tested.
+15V
+10 V
~~-----+--~-oVOUT
100
.n.
;
VOUT
AD7541A
SI7541A
Figure 15. Propagation Delay and Settling Time Comparison
13-48
.
fIllY' Siliconix
~
incorporated
+15V
+15 V
SI7541A
AD7541A
Figure 16. Glitch Impulse Comparison
8. Overvoltage. Vendor I's data sheet recommends
Schottky protection diodes at the DAC output and
contains a warning to avoid overvoltages at the
logic inputs which could lead to latchup and device destruction. None of the four parts tested
latched up; nevertheless, Siliconix devices displayed a superior overvoltage resistance on the
digital input pins, resulting from improved input
stage design. Vendor P's parts showed some
parasitic transistor action (a tendency to
latchup). Vendor I's parts were the most vulnerable with an apparent parasitic diode turning on
for both plus and minus polarities.
13-49
AN87-3
H
Siliconix
incorporated
R1
Iiiiiiiiiii
Iiiiiiiiiii iiiiiiiiiiii
ri =~
VA
l1
rJ= i1
fA
~
rJ
~
~,
:;;;;;;;
~
rJ
~
·Iiiiiiiii
-~~~
rJ
~
~,
~,
r~
rj
1,;= :.I
rJ
~,
~,
ILii
•
ro: iiiiiiiiiiii-·
ri =~
VA
l1
~
ILoii
~,
~
rJ
l'1,;:= rJ
:.I
Vendor I
Sillconix
Figure 17. Similar Dynamic Performance with OP-07. C
13-50
~
r~
rJ-- i1
fA ~
~
l'
Vendor P
iiiiiiii
~~-
Ji =~
VA
l1
~
1;; ...
Scales: 10 V
2V
5 J.l.S
Vendor A
iiiiiiiiiiii
l' iii!rj
Ioiiii
•
VA
~,
~,
l' iii iiirJ
rJ-- i1
fA ~
II
fA
~
Ji
i1
=
=0
~,
ILoii
AN87-3
Siliconix
incorporated
;;:::
rj
rJ
~1 -
U
,.rA
11
III
~1
l'
•
rJ
II
~1
l1
II
I
'j
Vendor P
Vendor A
Scales: 10 V
2V
5 jJ.S
=
~
U"
II
~,
II
II
.1
l1
IIII
'I- e,rSh.c,' ~. I
Vendor I
rA
,j
rJ
,j
~,
II
~1
l1I
Sillconix
III
Figure 18. Dynamic Performance with OP-27 C = 22 pF
13-51
AN87-3
.... Siliconix
incorporated
~
TYPICAL APPLICATIONS
Current Steering Mode
Unipolar Binary Operation. The circuit shown in Figure
19 is the basic building block for many DAC applications. A fixed reference voltage is applied and a
12-bit digital word controls the output current, which
is converted into a voltage by a suitable buffer amplifier. The output can be selected to a resolution of 12
bits (i.e. 4096 steps) between 0 V and -(4095/4096)
VIN.
For best results, the output amplifier should have
very low input offset voltage ~os < 25 X 1O-6VIN )
and low input bias currents QB < 100 nA). Resistors
R1 and R2 can be used to set up the correct fullscale output VIN (i.e. -(4095/4096) for a digital input
of 111111111111).
R2 should be selected according to
R2
= (MAX GAIN
ERROR IN %) . R REF Max
100
R1 can then be varied to produce the correct fullscale output. (R1 will be less than twice R2). R1 and
R2 must have low, well-matched TCs; therefore, precision metal-film or wire-wound resistors with a TC of
50 ppm/DC are recommended. Also, since the TC of
potentiometers vary with wiper position, a fixed value
resistor (or two in series) should be selected for R1 .
An alternative method is to adjust the magnitude of
VIN , thus avoiding any TC mismatch between the external and the on-chip resistors.
The capacitor, C, used for phase compensation affects the overshoot and settling time of the system.
The optimum value for C is dependent on the output
capacitance of the Si7541 A (which is code dependent) , the value of the feedback resistor RFB , and the
unity gain-bandwidth product of the output amplifier.
A good approximation for the Si7541 A is given by
C
1n -7
= -1..!L.JGBW
where GBW = the gain-bandwidth product
of the output amplifier
Figures 20 and 21 show the effect of different value
compensation capacitors with two popular amplifiers.
Although the OP-27 gives a more accurate reSUlt, it
has a relatively slow slew rate when compared to the
faster-slew rate FET-input op amps such as the
TL071. The effect of this on the rise and fall times is
apparent in these photographs (f = 20 kHz).
Figure 19. Unipolar Binary (current steering mode)
13-52
AN87-3
Siliconix
incorporated
10, riS
lITo, i1
0
,
;
=
"""""~
OV
(::
';:: =
:=
(a) No Compensation Capacitor
(2 V/dlv)
(a)No Compensation Capacitor
(2 V/dlv)
r; 00;;
~~
"
r'~
, ';""1
:::::;;
~
OV
(b) Compensation Capacitor
(2 V/dlv)
OV
= 15 pF
I!!:=
I':
I~ ~
(b) Compensation Capacitor
(2 V/dlv)
'!: ~
[;I
OV
(c) Compensation Capacitor
(2 V/dlv)
= 39 pF
Figure 20, Unipolar Binary Operation Using OP-27
(Slew Rate = 2,8 VI JLs)
=
= 15 pF
r1i,i .;';
"
OV
"
=
OV
:~~
(c) Compensation Capacitor
(2 V/dlv)
=39 pF
III
Figure 21, Unipolar Binary Operation Using TL071
(Slew Rate = 13 V/JLs)
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A disadvantage of unipolar current-steering DAC circuits is the requirement for opposite polarities of the
reference voltage and the output. An advantage,
however, is the low component count, which means
the circuit is simpler and cheaper than a bipolar system.
Bjpolar Binary Operation. There are three different
coding possibilities for DACs in the bipolar mode: offset binary, two's complement, and sign and magnitude. In all of these systems, the MSB indicates the
polarity. This design limits the resolution to 11 bits
(i.e., 1 LSB is equivalent to (1/2048) VIN).
Offset Binary Operation. The relationship between the
offset binary codes and the analog output is shown in
Table 2. To calibrate the circuit shown in Figure 22,
the digital Inputs are first set to 0000 0000 0000. R1
may need to be adjusted to give the required output,
VO = -YIN. Next, the inputs are set to 1111 1111
1111, and R2 is adjusted for an output of VO =
(2047/2048) VIN. For best performance, R1 and R2
should be precision metal-film or wire-wound resistors with matched TCs (50 ppm/oC give best results
as R1, R2, and R3). This circuit has two main disadvantages: a 2-step calibration procedure must be
performed and the resolution is reduced to 11 bits.
Table 2. Offset Binary Code
Digital Input
Analog Output
1111 1111 1111
+(2047/2048)VIN
1000 0000 0001
+(1/2048)VIN
1000 0000 0000
OV
0111 1111 1111
-(1I2048)VIN
0000 0000 0000
-VIN
Two's Complement. The two's complement is essentially the same as the offset binary coding, with
the exception of the MSB, which is inverted. As
shown in Figure 23, R1 is adjusted to give an output
of VO = -YIN for an input of 1000 0000 0000. R2 is
then adjusted for VO = (2047/2048) VIN with a digital
word of 0111 1111 1111. This circuit has the same
disadvantages as the offset binary bipolar circuit,
that is, an 11-bit resolution limitation and a 2-step
calibration procedure. Table 3 shows the relationship
between the two's complement binary codes and the
analog output voltages.
Rl
R3
20 k.n.
Figure 22. Offset Binary Configuration
13-54
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~
AN87-3
Siliconix
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Table 3. Two's Complement Binary Codes
Digital Input
Analog Output
0000 0000 0000
-v IN
1000 0000 0000
OV
1111 1111 1111
2047/2048 VIN
Rl
20 k.n.
R3
20 k.n.
>-.....-oVO
Figure 23. 2's Complement Bipolar Configuration
Sign and Magnitude. With this method of coding, the
MSB is used to control an analog switch which selects either a positive or negative reference. The
switch output must be buffered to ensure that any
change in the rDS(ON) of the switch does not affect
the calibrated system (Figure 24).
calibration step (i.e. selection of R1). This step is the
same as described f!lr unipolar binary operation.
Also, since the references are buffered, more than
one DAC can be driven without a reference for each
DAC. One disadvantage, of course, is that systems
using a single DAC now need both a positive and a
negative reference.
For the circuit shown in Figure 24, there is only one
DG18S
+v
REF
-v
REF
VOUT
-
DIGITAL INPUTS
Figure 24. Sign and Magnitude Configuration
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Voltage Switching Mode
A disadvantage of the current-steering mode is that
the output impedance (capacitance and resistance)
is a function of the digital word input. As mentioned
earlier, a compensating capacitor is needed to ensure stability of the op amp. The value of this capacitor depends on the output Impedance of the DAC
which varies with digital Input. The compensation capacitor must, therefore, aliow for the worst-case, resulting in increased settling time and reduced
bandwidth. In the voltage-switching configuration
(Figure 25), this problem is avoided by using the
VREF pin as the output. The impedance seen at this
pin Is constant and independent of digital input.
VDD
input voltage must be limited to approximately 2.5 V
for a +15 V supply and 0.7 V for a +5 V supply.
+1
......""'"
VIN = 1.22 V
TA = +25-C
l-
ii:
c
...
:z
::;
I
:z
co
:z
+0.6
...
c
i=
is
0
It""Ci
_0.5-jol:...t:...l~~L.4.~=~--+----+-.
VRE
SI7641A
Figure 26. SI7541A In Voltage Switching Mode
The output of the Si7541 A in the voltage-switching
mode is a voltage of the same polarity as the reference. This mode enables a DAC system to operate
from a single power supply, however, the DAC loses
its multiplying abilities. The input VIN must not fall
more than 0.3 V below OUT2; otherwise, an internal
diode will become forward biased. If not current limited, a large flow of current could result and the
device could be destroyed.
Figure 26 shows the effect of supply voltage on differential non-linearity. The best results are obtained
with higher supply voltages. The input voltage, YiN ,
also affects the differential non-linearity (DNL) significantly because OUT1 and OUT2 are no longer at the
same potential. As VIN (OUT1) increases, the available VGS for the NMOS switches connected to OUT1
is reduced, thus increasing the on-resistance of the
switch. Since OUT1 and OUT2 are no longer at the
same potential, the two NMOS switches in each 2R
branch have a different on-resistance. The amount of
current flowing in each branch now depends on the
switch that is selected (i.e., the digital Input), thus
degrading the linearity. To minimize this effect, the
13-56
o
10
5
15
Figure 26. Differential Non-linearity
VB. Supply Voltage
Output glitches due to digital switching are reduced
for a DAC in this mode since OUT1 and OUT2 are
connected to low Impedance points and any parasitic
capacitances will be discharged through these paths.
RFB is not used In this configuration, and the RFB pin
is usually tied to OUT1 to reduce any noise pickup.
Figure 27 shdws a practical voltage switching DAC
circuit. A buffer amplifier is needed between the reference and OUT1 to eliminate any variation In reference from the changing input resistance of the DAC.
Gain is usually Introduced at the output amplifier to
achieve the desired full-scale output.
16
17
OUT 1
Sl7541A
V REF < 2.5V
OUT 2
R2
2
R1
10 k
SYSTEM GND
Figure 27. Operating the Sl7541A from a
Single Supply
AN87-3
Ir"F Siliconix
,4;11 incorporated
In Figure 27, the negative supply for the op amp is
connected to ground, and the output of the DAC
ranges between 0 V and (4095/4096) RREF . It is
necessary, therefore, to use an amplifier which has a
common-mode input range which includes the negative rail (in this case ground). Suitable amplifiers include the LM324, CA3130, and TL091.
In some applications, it is possible to offset zero for
single-supply operation, as shown in Figure 28. The
V2
and
output
can
be
varied
between
[(4095/4096)V1 + (1/4096) V2).
voo
the DAC, since the attenuating network consists of
well-matched thin-film resistors. Figure 29 shows a
digitally controlled attenuator circuit.
The digital inputs can be used to select the amount
of attenuation between (4095/4096) VIN and 0 V. The
maximum attenuation available is 4096:1 or 72 dB.
Due to the current-to-voltage buffer, the output will
be an inverted version of the input.
The low noise and distortion of this circuit makes it
attractive for audio applications. The output amplifier, rather than the DAC, limits the frequency response, slew rate and amplitude of signal which can
be passed. Table 4 shows the slew rate and frequency response for two different precision op
amps.
VOUT
Table 4. Slew Rate and Frequency Response
OP-AMP SLEW RATE
OP07
OP27
0.17 V/JJ,s
2.S VJJ,s
MAX FREQ
-SVto+SV -2.S V to +2.SV
10 kHz
> 120 kHz
S kHz
> 60 kHz
Figure 28. Offsetting Zero for
Single Supply Operation
Multiplication/Attenuation. The Si7541A is useful as
an analog multiplier or attenuator element. A signal
applied at RREF can be multiplied by a 12-bit digital
fraction. Very little noise or distortion is introduced by
This attenuator circuit can be easily converted into a
multiplier by using the output amplifier configuration
shown in Figure 30. If the input and output must remain in phase, another inverting amplifier must be
added to the output.
v+
VOUT
= -0 x V IN
DIGITAL
FRAOTION 0
III
Figure 29. Attenuator Circuit
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FIgure 30. Multiplier Circuit
Triangle Wave Generator. In the triangle waveform
generator circuit shown in Figure 31, a 12-bit counter
is used to produce the digital inputs for the Si7541A.
The MSB of the counter is used as a direction bit.
When this bit is 0, the exclusive OR gates allow the
other 11 outputs of the counter through to the DAC
inputs. This condition gives a ramp of positive gradi-
ent from 0 V to +2047/2048 RREF (assuming a negative reference) at the output of IC1. When the MSB =
1 , the exclusive OR gates will invert the outputs of the
counter, thus producing a ramp with negative gradient. Since the MSB is used as a direction indicator,
this system has a resolution of 11 bits.
v+
CD4070DB
EX-OR
6
9
CD4070DB
EX-OR
6
9
v-
6
CD4070DB
EX-OR
v+ =+5 V
9
13
10
Q1
CD4040B 12-BIT COUNTER
Q12
MBB
CLOCK
11
Figure 31. Triangle Wave Generator
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to + 15 V
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incorporated
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~
+v
LOAD
(lOOn.
-v
I
IN
(5 V)
N-CHANNEL
FIgure 32. Programmable Current Sink
The frequency of the triangular wave is controlled
simply by the clock frequency. and the amplitude of
the signal is (1 - 2 -11) VREF. IC2 can be used to both
invert the polarity and to adjust the dc offset of the
triangle if. for example. it must be symmetrical about
zero.
Programmable Current Sink. A simple. yet accurate.
programmable current sink can be obtained by using
a small-signal MOSFET and a single resistor. as
shown in Figure 32. The voltage. Vs. is determined
by the product of the digital input fraction and the
reference voltage (i.e. Vs =-0 XVIN). Also. RFB is in
parallel with R1. since OUT1 is held at GNO potential
by the virtual ground of the output buffer amplifier.
Voltage Vs is across this parallel resistance; therefore. the current drawn through the load is given by
1= Vs (R1 + VREF )/(R1 x VREF). Rewriting this in
terms of VIN.
I
=0
VIN
R1
(1 +
..BL)
RFB
This equation can be approximated to 1 = (0 x
VIN)/R1. provided that R1 is small compared to RFB .
The ratio of R1IRFB determines the offset to this approximation. The maximum available current is limited by the potential drops across R1. the MOSFET.
and the load. For example. the circuit shown in Figure 32 is capable of 0 to 50 mA in steps of 12.2 ).I.A
with a load of 100 .0.
Programmable Current Source. Figure 33 shows a
circuit for a programmable current source which is
virtually a mirror image of the current sink circuit.
P-CHANNEL
VPO 300L
+VIN
l1li
-v
Figure 33. Programmable Current Source
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AN87-3
~
Programmable Gain Element. The Si7541A can be
configured as the feedback element of an op amp,
as shown in Figure 34. In this circuit, the effective
feedback resistance can be controlled by a 12-bit
digital word. The output voltage is given by Va =
-VIN/D, where D is a digital fraction. Therefore, the
digital word 0000 0000 0000 is not permissible because it implies infinite gain. Care must be taken not
to saturate the op amp when the digital input is small.
At the other extreme, a 1111 1111 1111 input results
in Va = -(4096/4095) VIN.
Figure 34. SI7541A as a Programmable Gain Element
ANALOG
INPUT
Analog-to-Digital Converters. Several types of analog-to-digital converters (ADCs) can be easily implemented by using a DAC, a comparator, and a few
logic components. The simplest is the counter ADC.
This circuit uses a binary counter as the input to the
DAC. A comparator compares the DAC output with
the analog input signal and stops the counter when
both reach the same level. The counter outputs
constitute the digital word.
An improved ADC circuit is shown in Figure 35. The
up/down counter controls the DAC. Based on the
comparator output, the clock pulses increase or decrease the DAC output to reach the appropriate analog input voltage level.
Another popular converter is the successive approximation AID. This circuit achieves conversion in 12
steps. The process begins by comparing the output
produced by the MSB with the analog input. If it is
less than VANALOG, the next bit is also turned on. If it
is more, the MSB is turned off before the next bit is
turned on. This process continues until all 12 bits
have been weighted. In Figure 36 an Si2504 successive approximation register (SAR) controls the DAC.
After 12 comparisons have been made, the digital
output of the SAR produces the desired digital code.
Figure 37 shows the Si7541 A output during a typical
conversion.
0-----,
Si7541A
DIGITAL
OUTPUT
DATA
TRACK/HOLD
0-----t===:::;:=1
UP
UP/DOWN
COUNTER
DOWN
Figure 35. A 12-blt Tracking AID Converter
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incorporated
Si7541A
VANALOG
DIGITAL
OUTPUT
DATA
SI2504
SUCCESSIVE
APPROXIMATION
REGISTER
CLOCK
Figure 36. Successive Approximation AID Converter
;!FS
4
o
1 (MSB)
2
4
3
5
6
7
8 ...
CLOCK PERIODS
Figure 37. SI7541A Output for 12-81t Successive Approximation Conversion
CONCLUSION
The general DAC operation theory presented in this
application note is intended to support successful designs using the Si7541 A 12-bit CMOS multiplying
DAC. The capabilities of these designs will be enhanced by the improvements shown for the Siliconix
Si7541A over similar products, especially in speed
and dynamic performance. Example circuits and design hints have also been presented to assist the designer in using the Si7541A 12-bit DAC.
REFERENCES
Dooley, Daniel. Data Conversion Integrated Circuits.
New York IEEE Press, Wiley (1980).
Loriferene, Bernard. Analog-Digital and'Digital-Analog Conversion. London. Heyden & Sons Ltd. (1982).
Analog-Digital Conversion Handbook, Third Edition.
Analog Devices (1986).
Burton, Phil. CMOS DAC Application Guide, Second
Edition. Analog Devices (1986).
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APPENDIX: OTHER BASIC DAC PRINCIPLES
noisy and very sensitive to changes in current and
temperature.
Voltage References
The voltage reference provides an accurate voltage
for generating binary-weighted currents. Any reference error reduces the overall system accuracy;
therefore, the ideal references are characterized by
accurate output voltages, low temperature drift, precise load and line regulation, and long-term stability.
Zener References. The least expensive reference devices are Zener diodes. Zener diodes produce a constant voltage drop when passing a constant current
derived from a higher voltage. The active portion of a
Zener diode is a reverse-biased p-n junction. In the
forward-biased region, the diode acts much like a
high-conductance silicon diode (Figure A 1). In the
reverse-biased region, little current flows if V is less
than Vz, the breakdown voltage. The small leakage
current that flows is relatively insensitive to the magnitude of reverse voltage for fixed temperatures.
VZ
REVERSE BIAS
BREAKDOWN
VOLTAGE
Zener diodes that breakdown in the 6-V range exhibit
the best performance with very low TCs (+2 mV/oCl
and relatively low sensitivity to current changes. They
can be compensated by a VREF (-2 mV/°C) , as
shown in Figure A2.
IC References. Monolithic ICs provide a more accurate reference (Figure A2). These devices usually include a temperature-compensated Zener diode
driven by a constant-current source or a bandgap
reference and a buffer output amplifier. These references provide an accurate output voltage that is virtually independent of input voltage, load current,
temperature, and time. They provide voltage capabilities from 1.22 to 15 V with voltage tolerances from
0.05% to 5%, drifts of 0.5 to 100 ppm/oC, and current ranges from 400 I1A to 200 rnA.
For most of these integrated circuits, the output voltage has been established by trimming ultrastable,
low-temperature drift thin-film resistors under circuit
operating conditions. These devices are usuaily
short-circuit protected in both the current-sourcing
and sinking directions. Table A 1 illustrates some of
the most popular reference voltages available.
~
Table A1: Typical Reference Output Voltages
Reverse Breakdown Voltage -- VR (volts)
1.22
1.235
2.49
2.5
CATHODE
FORWARD
REVERSE
~
+
ANODE
+
Figure A1. Zener Diode I-V Characteristic
As the reverse voltage approaches Vz, the current
increases rapidly. Therefore, Zener diodes are generaily used in series with a resistor to limit the current
or driven by a constant current source. These diodes
provide voltage capabilities from 2 to 200 V with tolerances of 1% to 10% and power dissipations from
1/4 to 50 W.
Attractive as they seem as general-purpose voltage
references, Zener diodes have many shortcomings.
The voltage tolerance is generally poor, and they are
13-62
5.0
6.2
6.9
6.95
7.50
10.00
10.24
1.24 to 5.3,
5 to 15,
-5 to -15,
Adjustable
Adjustable
Adjustable
Band Gap References. A popular voltage reference
for monolithic circuitry is the "band gap" reference,
which is based on an inherent physical property of
the base-emitter voltage in a forward-biased silicon
transistor. The VBE of a silicon transistor at absolute
zero (-273°C) is 1.205 V. This value is the band gap
voltage of silicon at 0 OK. By amplifying the difference between the VBE values of similar transistors
operating at different current densities, it is possible
to obtain a constant 1.205 V at any temperature.
Bandgap reference circuits are based on the circuit
shown in Figure A3. For the proper ratio, R1/R2 Vz =
1.205 V. This, in turn, is amplified by the ratio
(R4/R5 + 1) to give the desired output voltage. LowTC thin-film resistors may be laser or zener-zap
trimmed to increase accuracy.
H
AN87·3
Silica nix
incorporated
R3
IC
REF
v OUT
1---0
-2.2 mV/oC
+2.2 mV/oC
02
01
R1
Iz
...
R2
3 terminal reference
Equivalent circuit
Figure A2. IC Reference
8A
}--..:;,.:--3--r-------...f __ v z
= 1.205 V
T
AVBE
1
COM
o------~---~----~-----o
Figure A3. Bandgap Reference Regulator
Bandgap references operate from low-voltage supplies (typically VOUT
+2 V) and have an order of
magnitude lower output impedances than low-voltage
Zener diodes. Bandgap references are low cost, but
their output voltage usually must be buffered. In this
case, the offset voltage drift of the buffer op amp
must also be considered.
=
Buried Zener Diodes. Zeners have been produced in
ICs using the reverse-biased breakdown voltage of
the base-emitter junction of a vertical NPN transistor.
This pn junction occurs at the surface of the device
where breakdown may be affected by crystal imperfections, mobile charges in the oxide, and other
forms of contamination. These effects cause noise
and long-term stability problems.
13-63
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·AN87·3
~
In a buried Zener, breakdown occurs well below the
surface, thus avoiding surface effects. Long-term
stability of 50 ppm/year are achieved. However, because the diffusion process is less controlled under
the surface, there is a greater spread in breakdown
values and TCs. Therefore, the circuits are generally
designed to allow trimming. Typical accuracies better
than 0.1% and TCs in the order of +10 ppm/oC are
achieved.
Temperature-compensated buried-Zener references
usually have lower noise than bandgap references
and are recommended for high-resolution applications.
Temperature-Stabilized References. To improve temperature stability in IC references, on-board heaters
may be used to hold the reference elements at a
constant, elevated temperature. With this approach,
+ 1/2 ppm/oC TCs are attainable. The heater can
draw hundreds of mA, making this type of device incompatible with low power systems.
Forming DACs with Resistance Ladders
To reduce the number of resistors and their resistance range, a configuration may be used that pro-
vides a suitable attenuation, such as the one shown
in Figure A4. The Si7541A is implemented using an
R-2R resistance ladder.
This circuit consists of four binary-scaled resistor values for each group of 4 bits, with an attenuation of
16: 1 to each successive quad. This scheme can be
used for BCD conversion by using a 10: 1 attenuation
between quads. Furthermore, this approach can be
used to design the R-2R ladder circuit illustrated in
Figure A5. Most CMOS DACs are based on this circuit. The feedback resistor is integrated on-chip to
track the resistance of the ladder independently of
ambient temperature changes.
When only the MSB is turned on, the current contributed to the summing node, by the MSB switch, is 11 =
VREF/2R. The output voltage isVOUT = -(R/2R)VREF.
For the second bit, 12 = VREF/4R, and if only bit 2 is
on, VOUT= (-R/4R)VREF' Continuing down the ladder,
each 2R resistor passes one-half of the current. The
output voltage is proportional to the sum of all the
binary-weighted currents that are switched to the
OUT1 node.
5 k.n.
80 k.n. (BINARY)
48 k.n. (BCD)
Summing Node
Figure A4. 8-Blt DAC using two equal-resistance quads
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r--------------------------------------~
1
v REF
I
R
R
R
R
R
2R 1/641
-
Vc
"-jt----~-----jt----~----jt-----~-----j~
Lse
Mse
DIGITAL INPUTS
Figure AS. Current-steering DAC Using an R-2R Ladder
Lse
DIGITAL INPUTS
Mse
!----~---~---~---~----~--~~-'
R1
R2
L ________________________________ J
Figure A6. DAC In the Voltage SWitching Mode
In CMOS DACs, the analog switches are always very
close to the ground potential (within the Vos of the
amplifier) and the thin-film resistors are isolated from
the substrate. Therefore, VREF can be either positive
or negative, and the device can be used with ac input
signals. This operation is called mUltiplying.
The R-2R ladder can also be used to produce a noninverted output voltage by swapping the VREF and
OUT1 terminals as shown in Figure A6.
The OUT1 terminal is driven by a low-impedance reference voltage source, and the VREF terminal is connected to a high-impedance load, such as the input
to an operational amplifier. The reference voltage
source must be bypassed to minimize the variable
load and charge injection effects introduced by the
DAC switches. RLOAD should be more than 4096 x
ROUT to prevent a 0.5 LSB full-scale error.
13-65
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AN87-3
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~
down by switch capacitances, and glitches are created from charge injection coupling from the switch
drivers.
The output of this circuit follows the equation:
where
D
= Bl/2 + B2/4 +
In the voltage-switching mode (Figure A6) , the ladder
is used as aggresistive attenuator, and the switches
alternate between a low impedance reference voltage source and ground. The currents flowing through
each switch change with the input codes. Their magnitude is not as important as the reference source
ability for maintaining a fixed input voltage as the
codes change. In mpst cases, it is necessary to
decouple the reference with the parallel combination
of a 10 IJ.F tantalum and a 0.01 IJ.F ceramic capacitors (see Figure A7).
..... + Bn/2n
The numerator of each partial fraction is the value
"0" or "1" corresponding to the logic state of each
digital input. Generally, the magnitude OfVREF is limited due to the nature of the switching elements
used. The reference voltage must be less than 2.S V
to reduce the effect of unequal VGS applied to the
OUTl vs. the OUT2 switches (rOS(ON) variations).
Switching
The constant resistance seen by the op amp input
eliminates linearity errors caused by modulation of
the amplifier's offset voltage. Additionally, since the
output capacitance is less and the switch transients
are coupled to low impedance points, the voltagemode circuit results in cleaner and faster response to
digital code input changes. Since the output voltage
has the same polarity as the reference, it is possible
to operate the whole circuit from a single power supply. Finally, only a single operational amplifier is
needed for bipolar digital-offset binary or two's complement operation. The accuracy is satisfactory for
low values of VREF, but since the rOS(ON) of the
MOSFET switches is modulated by the magnitude of
the reference voltage. large values of VREF can produce considerable linearity errors. Additionally,
negative voltage references are not allowed in the
voltage mode because a parasitic pn junction to
ground will be activated. leading to possible destruction of the DAC if current is not limited.
Switching may be performed in either voltage or current modes. The analog switches can be bipolar,
CMOS, or NMOS, depending on the technology used.
Each technology has advantages and limitations. Important switch characteristics that affect DAC performance are switching speed, charge injection, onresistance, and parasitic capacitances. These characteristics play a role in determining performance
such as conversion speed, accuracy, and glitching.
In the current mode (Figure AS), each leg of the ladder conducts the same current regardless of switch
position. The current output is changed to a voltage
output by the external operational amplifier. This circuit is simple, its constant input resistance facilitates
good performance of the reference source, and it
can be used for 4-quadrant multiplication. However,
it can present linearity problems due to modulation of
the op amp offsets caused by the code dependent
output resistance. The dynamic response is slowed
0--...,...------.,---0
V DD = +15 V
16
17
<2.5 V
C2
>-...--0
V OUT
Si7541A
R2
o-~--+---jH
2
Rl
BITS 1 - 12
0-----<1-----+---+----0
C1 = 10 mF TANTALUM
C2
=0.1
mF CERAMIC
R111R2
SYSTEM GROUND
= 10 k.n
Figure A7. Single Supply Operation Using Voltage Switching
13-66
AN87-2
(I"'JP'" Siliconix
JIJI incorporated
EFFICIENT ISDN POWER CONVERTERS
USING THE Si91 00
By James Blanc
June 15. 1987
One of the latest technology revolutions, an integrated worldwide telecommunications network, will
be accompanied by another advance in power conversion technology. The integrated services digital
network (ISDN) will allow different forms of information (voice, computer data, video, facsimile, etc.) to
be transmitted over the telephone network. The International Consultative Committee for Telephone and
Telegraph (CCln) has proposed standards for the
interfaces required to implement ISDN. Although the
standards have yet to be formally adopted, telecommunications companies are moving ahead with pilot
test programs, and semiconductor makers are developing chip sets to build ISDN hardware. Every network terminator (NT), signal regenerator (RG) , and
terminal equipment (TE) unit used for the implementation of ISDN will require a power converter. [1)
A major requirement of these telecom applications
(due to the need for emergency-mode operation
from a high-impedance source) is high-efficiency energy conversion at fractional-watt power levels. Minimization of parts count, another key factor' for the
design of these power converters, is sought to simultaneously achieve low cost and high reliability.
D/CMOS integrated circuit technology is ideally suited
for the power requirements of ISDN. The analog and
digital logic functions needed for pulse-width modulation can be implemented in CMOS to minimize quiescent current to the controller. DMOS transistors provide high-voltage power switching with both very low
dynamic and gate drive losses. Integration of the
CMOS controller on the DMOS power device yields
the best overall performance at the lowest cost and
component count.
Design Objectives
While some differences exist between designs, there
are several requirements in addition to efficiency
which are common to ISDN power converter applications. These include:
o reliable start-up and operation from the high
source impedance of telephone subscriber
lines (U-interface only)
II
current limiting to prevent failure of other network terminals when one power converter output is shorted (S-interface only)
II
a free-running internal oscillator for start-up as
well as independent operation, which can be
synchronized to an external clock signal
•
electromagnetic interference (EMI) filtering to
limit conducted emissions during both start-up
and normal operation, as well as during equipment connections and disconnections.
The Si91 00 power IC facilitates compliance with these
design requirements with a minimum number of external parts. To illustrate this capability, a discontinuous conduction mode (DCM) flyback converter was
built and tested. Measured efficiency was greater
than 80% for a wide range of loads, and 60% efficiency was achieved with only a 15-mW load. Before
describing the circuit concepts in detail, it is instructive to note the main features of the ISDN powerfeeding concept which has been endorsed by the
cCln.
ISDN Power Feeding
Figure 1 is a block diagram of the ISDN basic access
configuration. The two-wire transmission line defined
at the U-interface provides a 192k-bits-per-second
(bps) digital data path which connects subscriber
equipment to the local telephone exchange. Although
ISDN permits many new services to be offered, the
basic service of voice transmission remains a vital
function. Therefore, the network power feeding from
batteries in the local telephone exchange remains an
essential part of modern telephone system planning.
The network terminal (NT) connects the local loop,
called the S-bus, to the U-interface at the customer's
premises. ISDN-compatible terminals (TE1) communicate at a standard 64k-bps rate over the four-wire
S-bus. Non-ISDN-compatible terminal equipment
(TE2) , such as analog phones, must connect to the
S-bus via a terminal adapter (TA).
To minimize noise-coupling problems, the S-bus
must be galvanically isolated from the two-wire U-interface. The cCln recommendations call for an offline power converter in the NT to supply 4 W at 40 V
13-67
~
...:.
AN87-2
..,. 8i1iconix
incorporated
~
110/220 VAC
+
TEl
TEl
Battery Voltage
(48 or 60 V typlcally)
100/220 VAC
Needed only
for IOn] loops
It
S-Bus
S
I
I
.R
TE2
H-
TA
Customer
Premises
U
U
NT
H-
I
IL
I
I
..-...l
I
RG
HI
.. I
I
I
I
I
...
Transmission
Line
Central
Office
Switch
Local
Telephon e
Exchang e
Figure 1. ISDN Basic Access Configuration
nominal to the 8-bus during normal operation (for up
to four telephones with full features). Other terminal
equipment (e.g., fax terminals) would be fed solely
from local ac power lines. In the event of a power
outage, one telephone at the customer premises
must be fed from the central office battery. This procedure Is accomplished by reversing the voltage polarity on the 8-bus. Non-priority terminals have a diode Input which isolates them during emergencymode operation. A single telephone terminal is fed
via a full diode bridge, allowing it to operate during
the emergency.
A signal regenerator may be required for long loops
(U-interface). The Deutsche Bundespost (DBP) proposes to increase the feeding voltage from 60 V to
93 V to compensate for voltage drops on long lines
requiring signal regeneration. The standard telephone line voltage used in many other parts of the
world is 48 V. Whatever the voltage, the problem for
power converters connected to telephone subscriber
lines remains the same--they are fed from a high-impedance source.
Source Impedance Effects
The impedance of telephone subscriber lines limits
the amount of power that can be supplied to the
load. Referring to Figure 2, for a battery voltage, Vs,
and line resistance, Rs, the maximum power to the
converter is given by Equation 1, since the power
13-68
limit occurs when source and load impedances are
equal.
-
V/
Re
-
(Vs/2 ) 2 VS2
Re
=-
(1 )
4Re
R e is defined as the effective low-frequency input impedance of the power converter.
For a flyback converter, with waveforms as shown in
Figure 3, the calculation of the low-frequency input
impedance is straightforward. The coupled inductor
is designed to ensure operation in the discontinuous
conduction mode (OeM). This operation requires
that the core flux be reset to zero during each cycle.
The current is zero at turn-on and ramps up at a rate
given by dildt =V l/Lp. The maximum value of the
peak primary current, Ipk' is
Ipk =
di
Cit
Vl
(tON(maX)) = Lp
ts
2"
(2)
The 50% maximum duty ratio imposed by the 8i91 00
controller limits the • on " time of 01 to one-half of the
switching period. The average value of the current
waveform in Figure 3 is the dc current in the inductor, L1. The current ripple in L1 is small, and the average inductor current, I DC, during start-up is onefourth the peak current value, as given by
AN87-2
flY' Siliconix
~
incorporated
+5 V
Rs
loc
--..
L1
Ro-1
VI
C1
-1
Central
Office (CO) I
Battery
Subscriber
Line
~~----~y----~' ~~-------------------~,
Flyback
Converter
Input
Filter
I
U-Interface
Figure 2. Power Converter with High Source Impedance
0< 0.5 (After Start-up)
Figure 3. Primary Side Current Waveforms
Substituting this result into Equation 2 gives Rein
terms of the primary inductance. Lp. and switching
frequency. f S (f S = 11f s).
(4)
L p effectively acts as a current limiter during startuP. thus eliminating the need for active current limiting circuitry. The value of Lp must be chosen between a minimum value. which sufficiently limits
start-up current. and a maximum value. which permits the rated throughput power to the load. Assume. for example. the maximum load condition
given in Table 1. [2] The input power to the converter
is the output power divided by the efficiency.
0.650
PIN =Po/h = 0.80 =0.813 W
(5)
Worst-case efficiency at maximum load is assumed
to be equal to 80%. The input power to the converter
is given by
P IN
As seen from
duced by half.
portion to L p.
analysis of the
=1/2 L p I pk 2 f S
(6)
Figure 3. if L p is doubled. I pk is reTherefore. P IN varies in inverse proReferring again to Figure 1. the dc
input characteristics gives
V1
= Vs
- locRs
(7)
13-69
.... Siliconix
.,1;11 incorporated
AN87·2
Table 1. ISDN Power Requirements
LOAD
CURRENT
CURRENT
-5 V
OUTPUT
POWER
100 mA
SO mA
650mW
87%
Normal -- Power Down
11 mA
SmA
70mW
79%
Emergency -- Active
55 mA
9mA
S20mW
BB%
SmA
OmA
15mW
60%
+5 V
OPERATING MODE
Normal -- Active
Emergency -- Power Down
Equations 2. 6. and 7 can be combined to give a
quadratic equation which yields the maximum and
minimum values for L p. A graphical approach. however. gives the same answer and. at the same time.
provides more insight into system behavior. After
start-up has occurred. the power converter no longer
presents a constant impedance at the input terminals. Instead. a constant power characteristic pertains. given by
PIN = (V1) (loC> = constant
(8)
The demonstration flyback converter was designed
to operate from a battery voltage of 48 V and a maximum line resistance of 600 .n. The constant power
MEASURED
EFFICIENCY
curve for (V1) OOC) = 0.813. with the load line defined by Vs = 48 V and Rs = 600 .n. are plotted in
Figure 4. The intersection of the load line with the
constant power curve determines two operating
points. A and B. which occur at (V" I dc)
(14.6 V.
55.7 mA) and (33.4 V. 24.3 mA). IfVs is slowly increased from zero. V1 and IDC increase along the
line. whose slope is Re. from the origin to the constant power curve. This analysis is an oversimplification since a step increase in voltage is more likely to
occur at power-up. However. worst-case start-up
conditions occur at maximum Rs. which guarantees
that the input filter is heavily overdamped. Therefore.
the increase inV1 is monotonic. and the results of the
simplified analysis are valid.
=
BO
70
\
60
50
V1
In Volts
40
~
SO
o
~
\
--.......'\
A
20
10
constaJ Power cuJe
IV1' I DC = 0.B1S)
/
~.......
~ -.........
/ ' MaximumRe.L p
~
o
B
I
I
10
20
---=-
I-Minimum R e. Lp
SO
40
IDcln mA
50
Figure 4. Flyback Converter Operating States
13-70
A
--......
I-----
60
70
BO
~
~
AN87-2
Siliconix
incorporated
L2 (RM8PA630 -397 core)
GND
+5 V
N/C N/C
Cl
20J.lF
100 V
Cl0
.1 J.lF
3
6
7
(ORJlonal)
S NC
INPUT 1000 pF
~C9
-5 V
Si9100
4
R7
Np
lN4148
CRl
5
-48 V
Figure 5.
ISDN Flyback Converter
The lines from the origin to points A and B define the
minimum and maximum values for Re , and with
Equation 4, also determine the limits for L p.
Re (min) = 14.6/0.0557 = 263 .0
Re (max) = 33.4/0.0243 = 1.37 k.o
For a switching frequency design value equal to
20 kHz, Equation 4 gives
=
Lp(mln)
1.64 mH
Lp(max) = 8.65 mH
L p may be chosen near the upper end of the permissible range for maximum start-up current limiting, or
it may be chosen for maximum power transfer on a
high-resistance line. Setting Re Rs 600 .0 for maximum power transfer gives
= =
L
= 77 turns
Nsl = 18 turns
N s2 = 18 turns
N s3 = 35 turns
the 60% efficiency at a load of only 15 mW, which is
allowed by the low quiescent current requirement of
the CMOS control circuitry in the Si9100. Although
power converters can operate at much higher frequencies, the dynamic losses incurred reduce the efficiency during the power-down state. The switching
speed (30 ns typical) of the DMOS output transistor
in the Si9100 permits operation above audible frequencies with very low dynamic and drive losses.
Such performance cannot be achieved with bipolar
transistors. A single resistor, R3, sets the oscillator
frequency at approximately 34 kHz. A positive sync
pulse (5 V amplitude and 0.5 J.Ls pulse width) at
40 kHz was fed through R7 and C9 to pin 8 to demonstrate the principle of synchronization with an external clock. Typically, the free-running frequency
should be set at 10 to 20% below the external clock
frequency (note that the switching frequency is 1/2
of the oscillator frequency).
600
- 3 75 H
- R /8f p- e
S - (8) (20,OOO) - .
m
The latter approach was chosen for the demonstration converter (see schematic in Figure 5). The
Si9100 functional diagram is given in Figure 6 for reference.
Converter Performance
Measured efficiency data for the flyback converter is
given in the last column of Table 1. Most notable is
Start-up characteristics were verified by connecting a
600-.0 resistance from a dc power supply to the converter input terminals. Reliable start-up was demonstrated at maximum load for supply voltages as low
as 44 V. With zero source resistance inserted in the
line, the converter maintained regulation down to an
input voltage of 23 V. In both cases, the maximum
operating voltage is 70 V for the Si9100 . The inductor, L 1 , was wound with 540 turns of #32 magnet wire
13-71
III
AN87-2
...... Siliconix
incorporated
~
Feedback
CompensatIon DIscharge
14
13
OSC OSC
In
Out
9
Error
AmplifIer
VREF C>-"10><--_ _ _t__-I
DraIn
40
»-Uf---..:.
rr===L_~
BIas
Body
(-VIN)
To
Internal
CIrcuIts L - - - - - - - - - - - I f - - - f - - - - - . . . . . , . , : - - -......--'s,,-O Source
o-!.----J
--+
VCC 0...:6:...-_ _
Undervoltage Comparator
O-~-4__~11~ SO
1-_ _ _-..:.12=-0 Reset
FIgure 6. SI9100 FunctIonal DIagram
on a #55206 molypermalloy powder core. The relatively high series resistance of this inductor (6 .0)
provides series damping of the input filter. This
damping reduces peaking of the filter output impedance. preventing degradation of the control loop response at the filter resol1ant frequency when the supply is operated from a low-resistance source.
Measured ripple on both outputs was less than 50 mV
peak to pea~. and regulation was better than 5% over
line and load. The -5-V' output increases from
-5.05 V to -5.75 V when totally unloaded.
The current-mode controller of the Si9100 provides
fast current-limiting response in the event of a
shorted output. With either output shorted to ground.
the measured value of short-circuit current drawn at
the converter input was 30 rnA. Any output terminal
can be shorted for an indefinite period with no resulting high stress condition on the Si9100. Normal operation resumes when the short circuit is removed.
13-72
The input filtering provided by L1 and C1 provides a
calculated attenuation of 68 dB at the fundamental of
the switching frequency. This allows compliance with
FCC Class Band VDE-0871/B requirements; however. conformance testing to these specifications
was not performed. Common-mode noise coupling is
minimized by the Si9100 since the MOSFET drain is
electrically isolated from the package case (a 14-pin
DIP). Therefore. very little parasitic capacitance exists from drain to ground. Since the Si9100 places
both the driver and MOSFET on the same chip. gate
driver lead lengths are reduced from a few centimeters for discrete designs to a few hundred microns.
The 5-mAI Jl.s dynamic current limit re~uired during
connection of equipment to the S-bus 3] is met by
selecting a suitably high value. 20 mH. for L1. Since
several ohms of series resistance is desired. a'small
wire gauge is used and the inductor is not prohibitively large. A smaller value may be chosen for L1
where the EMI requirements are less critical.
AN87-2
...... Siliconix
incorporated
~
Summary
D/CMOS power IC technology is ideally suited for the
requirements of low-power dc/dc converters, such
as those required for the implementation of ISDN. A
circuit design for an 850/0-efficient power converter
using the Si9100 SMARTPOWER IC has been presented here. Measured performance data is given,
along with a graphical analysis method for ensuring
reliable start-up when power is fed from a high-impedance source.
References
1. Rosenbaum, D. and K.H. Stolp. "The Feeding
Conception of the ISDN Basic Access," IEEE
INTELEC Conference Proceedings, Munich,
FRG, Oct. 14-17, 1985,505-512.
2. Sigloch, R. "Requirements for Small High Efficiency DCIDC Converters in Complex Communication Networks," IEEE INTELEC Conference
Proceedings, Toronto, Canada, Oct 19-22,
1986, 197-202.
3. Krautkramer, W. and B. Schickling. "Remote
Power Feeding of ISDN-Terminals at the Basic
Access," IEEE INTELEC Conference Proceedings, Munich, FRG, Oct. 14-17, 1985,513-519.
III
13-73
AN87-1
..... Siliconix
incorporated
~
A 1·WATT
FLYBACK CONVERTER
USING THE Si9100
James Blanc
March 1987
The Si91 00 is a monolithic D/CMOS SMARTPOWER IC
which combines high-efficiency CMOS logic, a highvoltage switching transistor and high-voltage preregulator on a single die. It is the first low-cost, high
efficiency regulator designed to operate directly from
unregulated high-voltage DC power sources in areas
such as telecommunications and avionics. The primary application will be in feature phones and ISDN
terminals to power the logic components without
exceeding the load limits set by the telecommunications industry. Power integrated circuit technology
allows low-power CMOS control circuits to be combined with DMOS power transistors in the Si9100. The
resulting reduced parts count decreases system
cost, improves reliability, and simplifies circuit design.
The flyback converter presented here uses the
Si9100 to provide an isolated ±5 V supply rated at
1 W. Specifications for this supply are as follows:
Input Voltage
....... 15 to 70 VDC
Output Voltages
Maximum load
+5V@167mA,
-5 V @ 33 mA
+5 V @ 32 mA,
-5V@8mA
Minimum load
Regulation .......... ±5%
100 mV p-p
Maximum Ripple
Switching Frequency.. 100 kHz
Efficiency
.......... 80% min for 1.0 W load
75% min for 0.2 W load
A schematic for the flyback converter is found in Figure 1, with a parts list provided in Appendix B. However, before discussing the details of the power supply design, it is instructive to review the functions of
the Si9100 integrated circuit.
CR2
1NS819
L1
~No----rrr~------~------------------~----------~
•
100J1H
C1
20J1F
N/C
2
R3
1S0 k.fl.
8
7
N/C
12
....----110
C3
0.1 J1F
11
C2
0.1 J1F
Np = 21
1S0 J1H
+
C6
0.1 J1F
3~----------4---------~
CRI
1N4148
SI9100
OUTPUT
6~----------4---~--~~
14 \------=:--1
R4
CS
13
1-"---1--4
240 k.fl.
1 J1F
0.022 J1 F
R6
4
12k
R2
+
L--W~+-----+----o
1.n.
INPUT GND
(GND PLANE)
13-74
C9
20 J1F
.........,vv.. . . . . .
O.SW
Figure 1.
C7
100 J1F
Schematic Diagram of the SI9100 Discontinuous Flyback Converter Circuit
-5 V
AN87·1
...... Siliconix
incorporated
~
FB
COMP
Error
Amplifier
VREF
O-----r--I
BIAS
0----1
VCC
0------+
SOURCE
Undervoltage
Comparator
1>-~--1I----o SHUTDOWN
RESET
FIgure 2.
SI9100 Simplified Block Diagram
Si9100 DESCRIPTION
As shown in the block diagram of Figure 2, the
Si9100 combines an oscillator, pre-regulatorlstart-up
circuit, precision voltage reference, error amplifier,
current-mode controller, and a MOSFET switching
transistor into one 14-pin dual-in-line package. Overcurrent protection, undervoltage lockout, and logic
inputs for both latched and unlatched shutdown
modes are also included.
Start-up/Preregulator Circuit
A unique start-up/preregulator circuit, which is shown
in Figure 3, permits the Si9100 to operate over a
wide input voltage range (10 to 70 V). The input voltage for the device is connected between the +VIN
(pin 2) and -VIN (pin 5) terminals. The high-voltage
depletion-mode (normally ON) MOSFET acts as a
current source during start-up, charging the capacitance at the Vee terminal (pin 6) directly from the
input source. When Vee exceeds the 8.1 V undervoltage threshold, the output switch is enabled to provide well-defined start-up characteristics. Vee is then
regulated to 8.6 V by the pre-regulator circuit. If an
external voltage source greater than 8.6 V is fed to
the Vee terminal, the depletion-mode MOSFET is shut
off to reduce power drain from the input power
source.
+VIN 0---------,
8.6 V
Veeo-~~~----~
'----------+---o-VIN
Figure 3. Schematic Diagram of the startup section of the SI9100
Oscillator
The oscillator requires a single resistor to set its frequency. The requirements of flux reset in singleended converters generally dictates a maximum duty
cycle of 50%. With the oscillator frequency set at two
times the desired switching frequency, a flip-flop divides the clock signal by two, and the logic disables
the output during every other clock cycle.
13-75
~
__
tI'7"
AN87-1
MOSFET Switch
The MOSFET switching transistor has typical rOS(ON)
and \1BR)OSS characteristics of 4 0 and 180 V, respectively. Worst case specifications are 5 0 and
150 V. The device is a lateral DMOS structure which
has external connections for tHe DRAIN (pin 3) and
SOU ROE (pin 4). The body of the MOSFET is internally tied to the -VIN terminai, which must be connected to the most negative input potential in the circuit.
~
Siliconix
incorporated
threshold (8.1 V), then transistor switching begins.
The 4.0 V reference and the voltage divider ratio
formed by Rs and R6 cause the feedback winding.
N S3, to be regulated to +10 V. After start-up is complete the feedback voltage trips the comparator to
turn off the pre-regulator circuit. and the Si9100 derives its bias power from the feedback winding. The
power saved by this bootstrap technique is equal to
the product of the 10 bias current times the difference between VIN and VFB:
Power Saved
= (600
j.LA) (48 V - 10 V)
= 23 mW
Error Amplifier
The error amplifier permits compensation of control
loops for stable regulator operation. The amplifier
uses PMOS Input transistors to provide high input impedance (2 MO minimum), and is internally compensated for unity gain stability, with 1 MHz (typical)
bandwidth and 60 0 phase margin.
Protection
In addition to the undervoltage lockout function ,already described, the Si9100 provides overcurrent
protection and inputs for external logic control. With
a sense resistor (typically 10) connected from the
MOSFET source to the -VIN terminal, the voltage at
pin 4 is proportional to the output current. When this
voltage exceeds a 1.2 V reference the overcurrent
comparator disables the output MOSFET. The shutdown delay is typically 100 ns (200 ns maximum).
Logic inputs SHUTDOWN (pin 11) and RESET (pin
12) permit the use of latched or unlatched shutdown
modes. Internal current source pull-ups normally hold
both logic pins high. If the SHUTDOWN pin is pulled
low while the RESET is high, then the output switch
will be disabled until the SHUTDOWN pin is again allowed to go high. This is the unlatched shutdown
mode. If, however. the RESET pin is pulled low while
the SHUTDOWN pin is also pulled low. then the converter will be latched off until RESET goes high again.
While this is not a great deal of power. it does represent 2.3% of the output for a 1 W supply. Integrated
Services Digital Network (ISDN) applications require
such techniques for bias power minimization in order
to meet emergency-mode limits for the power-down
state.
Flyback Operation
Flyback converter operation is illustrated by the basic
waveforms shown in Figure 4. When the MOSFET
switch is turned on. current will ramp up in the primary at a rate given by:
V
di
dt
I
L
=~
tON
.J/1. ._____
pr,A_'_Pk-,-__
-I
tON
to-
FLVBACK CONVERTER OPERATION
Start-up
Applying input voltage to the circuit initiates charging
of capacitor, 010 through the filter inductor. L 1. The
depletion7mode MOSFET, as described above. l?upplies current to capacitor 05 through the Vee terminal
of the 10. When Vee reaches the undervoltage
13-76
Figure 4. Flyback converter waveforms
AN87-1
trY" Siliconix
~
incorporated
Stored energy, given by 1/2Lp IPk2 , is present in L2
at the time the MOSFET is switched off. This energy
is released to the secondary windings, N Sl through
N S3, during the off time, as shown by the total secondary current, Isee, in Figure 4. This is the flyback
principle in its simplest terms. A transformer is designed to transfer energy directly from the primary to
the secondary, with as little stored energy as possible. A flyback inductor receives energy during one
interval of the switching cycle, then releases this
stored energy at a later interval of the switching cycle.
During the time that the secondaries are conducting,
shown as tree' the magnetic flux recovers, or "resets" to zero, and the MOSFET must block the sum
of the reflected voltage from the secondary and the
input voltage. This requires a worst case blocking
voltage of:
good coupling between output and sense windings in
order to maintain better than 5% regulation over the
0.2 W to 1 W load range. Design details for the coupled inductor are included in Appendix A.
To analyze the system closed loop response, begin
by reflecting the filter capacitance and load resistance from each output winding to the feedback
winding.
Ceff =CS+
(~::r
C7+ C 9
2
6)
= 1 J.lF + ( 18
(100 J.lF + 20 J.lF) = 31 J.lF
The effective load resistance, Reff, can be found by
assuming that the entire 1 W load is connected
across the sense winding output:
Np
V pk = VIN + - - (Vo + Vo )
NS1
Re!!
= 70
21
+ -8- (5.0 + 0.5)
= 85 V
A leakage inductance spike appears at the leading
edge of the Vos waveform. The spike is less than the
150 V minimum \1SR)OSS, and no snubber network Is
required. Since the flux is reset to zero before the
end of each switching cycle, current flow through the
secondary is discontinuous. Consequently, this circuit is called a discontinuous-conduction-mode
(DCM) flyback converter.
VS 2
Po
V/ = 100 .n
1W
(10
The effective load impedance is determined at low
frequency by the 100 ohm resistance and at high frequency by the capacitive reactance given by Xc =
1/ c£ elf. The control-to-output transfer function thus
has a pole at:
fp
=
Regulator Control Loop
The function of the regulator control loop is to maintain the output voltages constant as either the input
line voltage or load current vary. These are termed
"line regulation" and "load regulation", respectively.
A sense winding has been chosen to close the regulator loop and provide output isolation. Since the secondary windings are coupled on a common core, the
volts/turn ratio is the same for N Sl, N S2 and N S3 .
The resulting secondary voltages will track each
other quite closely. There is, however, some degradation in load regulation due to leakage (uncoupled)
inductance between the ±5 V output windings and the
sense winding. This effect becomes progressively
worse as the switching frequency is increased. The
coupled inductor used here has been designed for
51 Hz
2'11" (100) (31'10 -6)
To calculate the low frequency gain of the power
stage, assume a 1 mV change in the error voltage,
Ve , at the output of the error amplifier, and calculate
the voltage Change, /lVs, which results at the feedback winding. Then combine the power stage gain
with the error amplifier gain (including the voltage divider) to yield the total loop response. Assume for
these calculations that the converter efficiency remains constant at 83.33%.
Po
1W
11
0.8333
= 1.2 W
13-77
III
AN87·1
WY'Siliconix
incorporated
~
The power input to the converter is the product of the
stored inductive energy times the switching frequency.
The solid line in Figure 5 represents the transfer function of the converter power stage at full load. The
corresponding curve at a 20% load is shown in figure
6. To complete the analysis of the control loop requires accounting for the resistive voltage divider and
the error amplifier. The resistor Rs sets the DC bias
condition, but does not enter into the samll signal
analysis.
Rearranging to solve for Ipk gives:
~
At high frequencies the gain is R4/R5, with a zero
occurring in the transfer function at
2 (1.2)
= 0.4 A
(150 J.l.H) 10 5
fz
Since the current sense resistor, R2, equals 1 n, a 1
mV change in the error voltage (at pin 13) will result
in a 1 mA change in the peak inductor current, i.e.,
Alpk = t:Ne. A 1 mA increase in Ipk causes PIN to
increase to:
'
1
2'"
. 150
~
• 10
(0.400 + 0.001)
2
'10
5
= 1.206 W
- - - - - - - = 30 Hz
= -211'-(240
kn) (.022 J.l.F)
The error amplifier response is shown in Figures 5
and 6 as dashed lines. The error amplifier response
times the power stage gain gives the total loop gain,
which is shown as the gray line for full load in Figure 5
and light load in Figure 6. Actual measurements of
loop gain and phase yielded a loop bandwidth of 14
kHz with 68 degrees phase margin. Figure 7 is an
oscilloscope photograph of the +5 V output as the
load is stepped between 20% and 100% of full load.
Response time is under 200 J.l.s with no overshoot.
Assuming efficiency remains constant,
Po = (.833) • PIN = 1.005 W
80
This translates to an increase in the sense voltage to:
60
Vs
=~ Po
'Reff
=
~ (100
' 1.005) = 10.025 V
40
co
3
The gain is given by:
z:
=<
t!J
IlVs
10.025 V - 10 V
1 mV
= 25
At full load the low frequency gain of the power stage
is 25 (28 dB), with a single pole in the transfer function at 51 Hz. Performing a similar calculation at the
20 % load condition yields a gain of 56 (35 dB) with a
pole at 10 Hz. There will also be a zero in the transfer
function at approximately 30 kHz due to capacitor
ESR.
13-78
20
0
-20
-40
100
10
1k
10 k 100 k
FREQUENCY (Hz)
FIgure 5.
Loop gaIn at 100% load
trr
~
AN87-1
Siliconix
incorporated
80
nal equipment (TE) meet the limits outlined in Table 11.
60
Table I. ISDN power requirements
40
Operating mode
IlJ
..:s
z
<
t!J
Maximum
input power
to TE
efficiency
target
20
Normal-active
900 mW
100 mW
Normal-power down
Emergency-active
400 mW
Emergency-power down
25 mW
0
70
60
70
40
%
%
%
%
-20
-40
1
100
10
1k
10k lOOk
FREQUENCY (Hz)
Figure 6.
Loop gain at 20% load
The 25 mW limit during emergency power-down
mode operation may be especially troublesome2 • In
order to supply 10 mW to the TE for such functions
as memory back-up, total converter losses must be
less than 15 mW. Under such light load conditions
the major power loss is in the PWM controller. Only
controllers implemented in CMOS can presently be
expected to meet this requirement.
Although the converter circuit of Figure 1 was not designed specifically for use in ISDN terminals, with
some modifications it can be used in these applications. Since CMOS logiC circuits consume power only
during switching transitions, the first modification
which is recommended is to decrease the switching
frequency. The coupled inductor, L2, can be operated at 40 to 50 kHz (change R3 from 150 kn to
390 kn) without a redesign. Decreasing the frequency further requires a larger core size.
Figure 7.
Step load response
ISDN APPLICATIONS
Integrated Services Digital Networks (ISDNs) pose
some unique problems to telecom systems design
engineers. Standards proposed by the International
Telephone and Telegraph Consultative Committee
(CCITT) recommend that input power to ISDN term i-
A second circuit modification which is recommended
is to increase the resistances used in the voltage divider network (R sand Rs). The values used in the
1 W converter will dissipate (10)2 / (18 kn + 12 kn) =
3.33 mW. This loss is negligible for the 1 W converter, but it is nearly one forth of the budgeted
power loss for the ISDN supply during the emergency
power-down state. Setting Rs = 51.1 kn and Rs =
34.0 kn reduces the voltage divider dissipation to 1.2
mW. With these two minor changes the flyback converter meets the efficiency specifications of Table I.
Figure 8 illustrates the efficiency improvement at light
load levels which results from the circuit changes
outlined above.
13-79
AN87·1
. . . 8i1iconix
incorporated
~
100
80
'ii
........
45 kHz
f/
//
II
/100 kHz
40 ,
...........
""
most appropriate type of application--Iow power converters. The device is not, however, limited to 1 W
designs. Figure 9 shows the maximum achievable
output power as a function of minimum Input voltage
for several types of converters, two of which are discussed below.
>- 60
w
Z
I..&J
W
G:
I..&...
I..&J
CCM Flyback Converter
20
.2
.4
.6
.8
OUTPUT POWER (W)
Figure 8. Efficiency VB. load curves
for the flyback converter
Other SI9100 Applications Circuits
The 8i9100 has been called a "One Watt High-Voltage 8witchmode Regulator" in order to describe its
By redesigning the magnetics for continuous conduction, the flyback circuit of Figure 1 can be made to
provide 3 W of output power. Operation in the continuous conduction mode (CCM) Introduces a righthalf-plane (RHP) zero into the control-to-output transfer function of the power stage. The RHP zero incurs
a phase lag without the corresponding gain rolloff
caused by left-half-plane poles, and lead compensation cannot be used. Instead, the gain must be rolled
off to unity (0 dB) below the RHP zero frequency. The
continuous-mode flyback will, therefore, have a
slower dynamic response than the DCM flyback.
Also, to maintain the same output ripple for the 3 W
converter, it is necessary to increase the size of the
output filter capacitors.
10
8
i
a=
~
6
c
a..
I:::I
a..
I-
4
:::I
C
2
0
0
10
20
40
50
INPUT VOLTAGE (V)
Figure 9. Maximum output power
13-80
VB.
minimum Input voltage
60
AN87·1
..... Siliconix
incorporated
~
Toroidal cores were used for both the transformer
and the coupled output inductor to achieve very low
leakage inductance. The transformer winding data is
as follows:
Forward Converter
Forward converters are not normally used for power
supplies rated under 100 W. due to the additional
cost of the output filter chokes. However. for 2 to
4 W converter applications requiring ultra-low ripple.
the cost of the additional inductor may be warranted.
One such application is low power instrumentation for
avionics.
Core - Ferroxcube #768T188-3C8
Windings - N1 = 31 turns (AWG26)
N2 31 turns (AWG34)
N3 22 turns (AWG32)
N4 64 turns (AWG32)
N5 43 turns (AWG34)
=
=
=
=
The forward converter of Figure 10 was designed to
operate from 28 V aircraft power (MIL-STD-704D) to
provide 2.5 W at 80% efficiency. A single core with
multiple windings has been used to decrease cost
and board space required for the output filter inductors. The input voltage range is 18 to 32 VDC; regulation is 5%; and the switching frequency is 100 kHz.
Measured peak-to-peak voltage ripple was 8 mV for
the +15 V output. 4 mV for the -15 V output. and
13 mV for the +5 V output. at maximum load.
The primary and clamp windings are placed on the
core first. wound bifilar to minimize leakage inductance. The +5 V output is wound next. followed by
the ±15 V outputs wound bifilar. The 10 V winding
was placed on the outside. Each winding is spread
over the entire circumference of the toroidal core for
optimum magnetic coupling.
T1
(768T188-3C8 CORE)
L2 (MAGNETICS 55120 CORE)
1N4148
N2
51<.0.
L1
5()J1.H
+28 V
o-_ _ _ _ _rY'rrrr'-_-:-~-_-.......-~
(MIL-STD-704)
~--~~-nnrrrrL-J~~-J--o~rN
~-4N-~-:--nnrrrrL-4~-+-~-o+15V
15 1<.0.
~--~~--~--~~-~-o15V
lSmN
'L-I__~-:--nnrrrn....-J~~-.L.::o
-15 V
GI
Figure 10. 2.5 W forward converter using the 819100
13-81
AN87-1
WY'Siliconix
incorporated
~
Coupled inductors must have the same turns ratios
as the transformer secondaries or high circulating
currents result in very high output ripple. The coupled
inductor. L2. is a molypermalloy powder (MPP)
toroid (Magnetics #55120) with three times the number of turns as each of the T1 secondaries. The inductor winding data is as follows:
+5 V -+15 V --15 V -+10 V --
66 turns (AWG30)
192 turns (AWG30)
192 turns (AWG34)
129 turns (AWG34)
It should be mentioned here that MIL-STD-461 EMI
testing was not performed for this supply. To meet
CE03 and CS01 limits. some input filter redesign is
required. Although current-mode control exhibits excellent aUdio-susceptibility performance. it is still
necessary to damp the input filter to reduce peaking
of its output impedance at the resonant frequency
(Reference 3 provides useful design information regarding these requirements) .
References
1) Rosenbaum. D. and Stolp. K. H.• "The Feeding
Conception of the ISDN Basic Access." IEEE
Intelec Conference. Munich. FRG. Oct 14-17.
1985. pp. 505-512.
2) Krautkramer. W. and Schickling. B.• "Remote
Power Feeding of ISDN Terminals at the Basic
Access." IEEE Intelec Conference. Munich.
FRG. Oct 14-17.1985. pp. 513-519.
3) Middlebrook. R. D•• "Input Filter Considerations
in Design and Application of Switching Regulators." IEEE Industry Applications Society Annual
Meeting. Oct. 11-14. 1976.
APPENDIX A
FLYBACK INDUCTOR DESIGN
Inductance Calculation
1W
=---
1)
0.8
=+
dt
Lp (Ipk
f . fs
Ipk :!O
min
=
• (0.45 Ts)
LP(max)
=i
=i
=i
:. LP(max) =
1
I
VIN(mln)
LP(max)
If a maximum duty ratio of 0.45 is assumed. then the
minimum current peak is given by:
13-82
or
VIN(mln)
Combining equations 2 and 3 gives:
The minimum primary current slope occurs at the
minimum input voltage condition.
di
min • (0.45 Ts)
3)
PIN(max)
PIN
I
= 1.25 W
Input power is also equal to the product of the stored
energy in the magnetic field times the switching frequency:
2)
di
dt
IPk :!O
The first step Is to calculate the maximum primary
inductance for discontinuous conduction at maximum
load. Input power to the coupled inductor is approximately:
='2
LP(max)l pk(m1n)2. fs
LP(max) (VIN(mln) )2(0.45 Ts)2 fs
LP(max)
V
IN(mln)
LP(max)
i
V
2
(0.45 Ts)
2
2
fs
IN(mln) (0.45 Ts)
PIN (max)
(15) 2
1.25
2
2 5
(0.45 TS) 10
fs
182ILH
To allow for component tolerances choose a nominal
primary inductance of 150 ILH. Equation 2 then gives
IPk S>:$ 0.4 A.
AN87·1
11'7' Siliconix
~
incorporated
APPENDIX A (Cont'd)
Core Selection
Core A L Value Determination
The area product method was used to determine the
inductor core size. Refer to "Magnetic Core Selection for Transformers and Inductors" by McLyman,
for more information on magnetics design methods
(Marcel Dekker, Inc., 1982).
The number of primary turns is found from:
Ap
(
2 ( E ) " 104
)1.14
Np 8 m AC
Ipk
Ipk
Limiting the peak flux density to 0.15 Tesla gives:
8 m ' Ku • KJ
Np
where:
E
Np cIl
L=
= Core energy storage requirement
8 m = Maximum flux density
__ Lplpk
(150"10- 6 )(.4) "10 4
BmAc
(0.15)(0.195 cm 2)
= 20.5 turns "'" 21 turns
Ku = Window utilization factor
KJ
= Current density coefficient
This gives the following value for AL:
2
1
E=TLpl pk
2
AL = (1000)
21
(150"10- 6 ) = 340 mH
per 1000 turns
Let 8 m = 1500, gauss = .15 tesla, and Ku = 0.10
Secondary Turns Calculation
Ap
=(
2(+.150" 10-6 (.4)2) " 10 4 )1.14
0.15(0.10) (433)
= 0.0233 cm4
Since the empirical equation given above applies for
the area product of simple one-winding inductors,
multiply by 2 for a coupled inductor. All of the secondaries combined will handle the same energy as the
primary, and can therefore be allotted equal portions
of the window area. The area product requirement is
thus:
Ap = 2 " 0.0233 crA = 0.0466 cm4
The EP-13 core has an area product of 0.049 cm4 ,
which meets this requirement. Also, this EP core can
be tube-loaded for automatic insertion in high volume
manufacturing applications, and is available from
multiple sources (Siemens, TDK, and Amperex Ferroxcube).
The core flux is reset to zero during the off time for
each switching cycle. To guarantee discontinuous
conduction mode at the maximum load condition, it
is necessary to limit the inductance of the secondary
windings to some maximum value. Worst case conditions occur at the maximum switching frequency
(110kHz) and maximum AL value (374 mH/l000
turns for 10 % tolerance). The voltage across N Sl
during the diode conduction interval is Vo + VD = 5.0
+ 0.5 = 5.5 V, and the negative current slope is
~=~
dt
Vo +VD
tree
LS1
where IS1 is the peak current in the N Sl winding, tree
is the conduction time of CR2, and LS1 is the inductance of N Sl. The rectifier conduction duty ratio is
defined as:
d r = tree
TS
13-83
III
~
~
AN87·1
The load current is related to the peak secondary
current and duty ratio by the equation:
( N Sl )2
1000
NSI
Combining these equations solves for the rectifier
conduction duty ratio in terms of load current, inductance, and output voltage.
Use NSI
=NS2
(0.374)
S
Siliconix
incorporated
<
-
30.3 J.lH
9 turns
= 8 turns:
NS3 = (10 V + 0.7 V)
= 15.6 turns
~
NSI
5.5 V
16turns
dr
Winding Order
Setting the duty ratio < 0.45 gives:
2(.167)· LSI
I - - - - - S .45
5.5(9.09)
Therefore, LSI < 30.3 J.lH. Since ALMAX
mH/1000 turns,
374
The primary winding (1-2) is placed first over the
bobbin using one strand of AWG31 magnet wire (21
turns). The highest current secondary (3-4) is wound
over the primary using two strands of AWG31 (8
turns). The 10 V sense winding (7-8) is put down
next, using one strand of AWG36 (16 turns). The -5
V output (5-6) is wound last using one strand of
AWG31 wire (8 turns).
APPENDIX B
Si9100 FLYBACK CONVERTER PARTS LIST
Ul
Ll
L2
Cl
C2, C3, Cs, C8
C4
C7
C9
Cs
CR1
CR2, CR3
Rl
R2
R3
R4
Rs
Rs
SI9100
Inductor, 100 J.lH @ 75 mA DC
Coupled Inductor, GFS Mfg. # 85-787-4"
20 J.lF, 100 V, Alumin.um Electrolytic, Sprague # 30D+TE1409
0.1 J.lF ceramic
.022 'J.lF ceramic
100 J.lF, 10 V, tantalum, Sprague # 196D107X9010P
20 J.lF, 10 V, tantalum, Sprague # 196D226X9010J
1 J.lF, 50 V, WIMA MKS2
1N4148
1N5819, Schottky rectifier
390 kn, 1/4 W Carbon
1 .0, 1/2 W Carbon
150 kn, 1/4 W Carbon
240 k!l, 1/4 W Carbon
18 kn, 1/4 W Carbon
12 kn, 1/4 W Carbon
" GFS Manufacturing Company, 21 Crosby Road,
Dover, NH, USA 03820-1409
13-84
AN86·1
tI'7' Siliconix
~
incorporated
THE DG535/536 WIDEBAND MULTIPLEXER SUITS
A WIDE VARIETY OF APPLICATIONS
Gareth Powell
Revised February 1988
INTRODUCTION
Analog switch IC's traditionally have found limited
use in applications involving high-frequency analog or
digital signals. Degradation of switch performance
and intolerable signal cross-talk between channels
has undoubtedly forced many designers to use bulky
electromechanical switches or costly discrete designs.
At best. analog switch ICs configured in L or T arrangements (see Siliconix Application Note AN83-15)
could be adopted. However. increased board space
and layout complexity became major problems in
configuring systems with high channel density.
The DG535/536 are compact l6-channel. singleended multiplexer ICs. primarily designed as a costeffective solution to video and wide band switching
problems. Other applications that benefit from the
devices' superior performance characteristics are:
available on' the chip. The DG536 is housed in a
small. 44-pin J-Iead package. thus minimizing board
size requirements. The DG535 is packaged in a
28-pin DIP. Chip select pins (CS and CS) permit easy
stacking of devices for multichannel multiplexing systems (see Applications Section. Figure 19).
v+
Digital switching
Audio Switching
PCM routing networks
ATE systems
II
High-channel-density multiplexing or demultiplexing systems
High-speed multiplexing systems
Low-level signal multiplexing
..
o
PRODUCT DESCRIPTION
A functional block diagram of the DG535/536 is
shown in Figure 1 and the switch configuration is
shown in Figure 2. The device is fabricated using
self-isolated. silicon-gate D/CMOS technology. This
process enables the logic interface and driver circuitry. the gating and latching stages. and the
switching elements to be combined in a monolithic
structure.
y
l-
51
52
53
oA.-
55
56
57
58
u-
-I
!;~
/.. ......."'t
.,.
~
;.. ~
Os 0-
I:
ri
ADDRESS
LATCHES
GATING
LOGIC
DIS
E-~,,:lJ =
DECODE LOGIC
~
5T
bb b
A3A2 Al AO
Figure 1.
DG535/536 Functional Block Diagram
O"""liL
/J;W2 !:{
SW1
51
SW3
1
C>--O"""#
'T'SWITCH
CONFIGURATION
8
DRAIN
OIP
{SW4
59
SW5
to
~
S15
I
I
\
d:
IL __________
-b
"__I
~L
Ease of design for large switching matrices and interface with microprocessors is accomplished with
comprehensive logic gating and latching functions
-0 D
I I . r r-<>
~.
II
EN
r=~
A-
59
510
511
512
513
514
515
516
I
/.
54
C5
..
..
•
..
GND
y
1st level
Figure 2.
~
2nd level
DG535/536 Switch Configuration
13-85
AN86·1
...... Siliconix
incorporated
~
An additional feature, a DIS pin, is an open drain terminal with the source tied to the device substrate.
The DIS terminal represents a high Impedance to the
substrate (normally ground) when the DG535/536 is
disabled and a low impedance to ground when the
DG535/536 is enabled. This output can be used to
indicate which device in a large matrix has been enabled (see Figure 18), or it can be used to switch off
circuitry following the multiplexer stages.
of the multiplexer. These series switches serve several functions:
•
•
•
MINIMIZING PARASITIC EFFECTS
The insertion loss and bandwidth of the switch are
Improved with DMOS transistors that offer a low onresistance and low intrinsic capacitance (see
Siliconlx SD5000 data sheets). On the DG536 channel-to-channel crosstalk is minimized by physically
separat-ing each input channel with a GND pin which
extends to the device substrate. This, in conjunction
with careful PC board layout (see Figure 11), can
yield channel-to-channel crosstalk figures better than
-92 dB at 5 MHz.
Further ac performance benefits are obtained
through the n-channel DMOS transistor T configurations (Figure 2). This maximizes the off-isolation,
since SW2 provides a shunt path to ground for any
signals fed through the parasitic capacitance associated with SW1. SW3 (working in phase with SW1)
provides an extra stage of off-isolation and prevents
the shunt switch (SW2) from affecting consecutive
channels.
TWO-LEVEL SWITCHING
The two-level switching system of the DG535/536
(SW4 and SW5) works in antiphase, effectively isolatIng half of the switch outputs from the drain (output)
They provide an extra stage of off-isolation.
They reduce the drain output capacitance significantly and increase the multiplexing transition speed.
They reduce the off-leakage current, which
reduces the offset voltage that develops
from the total off-leakage current flowing
through the load resistance and/or switch
ON-resistance. This enables lower analog
signal levels to be handled accurately.
SILICON GATE
Polysilicon is used as the transistor gate material for
the DG535/536, as opposed to more conventional
metal-gate designs. This technology minimizes the
charge coupling of the control-logic signals to the
switch output due to the self-aligning properties of
the process. Metal-gate technology relies on
photolithographically aligning the gate metal with the
channel diffusions, resulting in greater overlap tolerances.
As shown in Figure 3, a PN junction exists between
the p-type substrate and then n-type channel diffusions. This junction should not become forward biased by the analog signal going more negative than
the substrate potential (normally ground).
Device damage could result from the current flow
through the forward biased substrate-channel junction, exceeding the aluminum current handling capacity (i.e. 20 mA). Analog signal DC biasing or offsetting the device power supplies can prevent this
problem. These methods are discussed in the applications section of this paper (Figure 12 and Figure
13) .
SOURCE/BODY
S~RCEIJ~IN
SYMBOL
P-SUBSTRATE
Figure 3.
13-86
Cross-section of an N-channel, Silicon-gate DMOS Transistor
D
-ALUMINUM
~
- GATE OXIDE
•
- POLYSILICON
EJ -
FIELD OXIDE
AN86·1
f6Y' Siliconix
~
incorporated
DG535/536 DC CHARACTERISTICS
Leakage Current
ON-resistance
The DG535/536 features low OFF and ON leakage
currents, reducing low switching errors.
ON-resistance must be low to ensure low insertion
loss, especially when the switch drives low load resistances. As shown in Figure 3, the ON-resistance remains low and fairly constant over the usable analog
signal range. This makes the DG535/536 useful for
audio applications that require low harmonic distortion.
rOS(ON) vs.
Drain Voltage and Temperature
400
15
V~ = Vi
360 I- GND = 0 V
320
Until now, most available video multiplexers or digital
crosspoint switches relied on high-level supply currents for operation. The DG535/536 requires a total
supply current of only 5 I1A, typical. This feature
makes the DG535/536 ideal for systems with high
channel density, such as 32-channel crosspoint matrices used in vidio mixing consoles or as ECl digital
crosspoint replacements in large data transmission
systems.
The total supply current for a 32-channel crosspoint
system using the DG535/536 is approximately
320 I1A, much lower than other video multiplexers.
280
240
rOS(ON)
200
(.0.)
+8S0~ -
160
120
+2SoC
~ ~...w
\
80
o
o
il
2
3
4
5
6
7
8
9
DG536 AC CHARACTERISTICS
(Refer to the DG535 data sheet for the 28-pin DIP
performance. )
-~O°C _
40
Bandwidth
10
V o - DRAIN VOLTAGE (V)
Figure 4.
Power Supply Current Consumption
ON-resistance vs. Analog Signal Characteristics
of the DGS35/536
This "ON" frequency response, as shown in Figure 6,
is expressed as the frequency at which the insertion
loss (at dc) increases by 3-dB. The measured
bandwidth of the DG536 is greater than 300 MHz.
Crosstalk
NOMINAL rOS(ON)= 50.0.
r-------~~r-----~----~VO~
~rOS(ON)
s
2.0.
600.0.
Crosstalk is the amount of unwanted signal apparent
at a particular node due to the parasitic capacitance
of the device. As the most important parameter for
many applications, crosstalk is specified in a number
of ways.
1 V pk/pk
1.
V
INSERTION LOSS = 20 LOG10 VOUT
IN
Single-channel crosstalk (Figure 7) is the ratio of the signal seen at the drain (output) to
the signal applied to a single OFF-channel input. This is expressed by
VOUT
Figure 5.
600.0. Audio System
In a 600-ohm audio system, such as the one represented in Figure 5, the percentage of ON-resistance
change relative to the load resistance is only 0.33%.
The insertion loss due to the switch ON-resistance is
0.7dB.
XTAlK(sc) (dB) = 20 lOG 10 - V
IN
Most conventional multiplexers specify this parameter on the data sheet as off-isolation. This
value for the DG536 is more than twice as good
as other 16-channel analog multiplexer ICs,
proving the effectiveness of the T switch.
13-87
~
__
AN86-1
..,. Siliconix
incorporated
~
-3 dB Bandwidth
(Insertion Loss vs. Frequency)
-4
+15 V
+15 V
0
RL = ~o~"
-4
Loss
(dB)
13IJBI~~:~
-8
V+
S2
THRU
S16
EN
CS
ST
H:>-_-O SWITCH
AO
"':-'-'---0-1 Sl
-12
OUTPUT
VOLrr
-16
-20
10
100
FREQUENCY (MHz)
1
Figure 6.
1000
Bandwidth of the DG536. Please refer to the DG535 Data Sheet for 28-pln DIP performance
Single Channel Crosstalk vs. Frequency
180
160
I
140
XTALK
(dB)
120
100
51
Q52
~
I" S3cc;>------o~
54. _ _ _ __
TEST CIRCUIT
See Figure 1~
.....
'f
IIIRIN = 75.0.
I
I
I
RL= 75.0.
,
r-......
80
SWEEP
,
GENERATOR
(75.0. )
'" V
60
40
20
o
0.1
10
100
FREQUENCY (MHz)
Figure 7.
56 0 _ _ _- 0
57 00_ _ __
58 0 _ _ _-0
51°00
59
5110
512 0
513 0
, 5140
, 0 515
~ 516
0...-:.
~~
~
~
~
~
RL
-
~
~
NOTES:
1. Channel Sl on.
2. Any Individual channel between S2 and S16 can be selected.
3. XTALK (50)= Average value of 20 LOG 10 VOUT Is scanned
Sequentially from S2 to S16.
V
Single-channel Crosstalk vs. Frequency Graph and Test Circuit (DG536)
2.
All hostile crosstalk (Figure 8) is the ratio of the
signal measured at the drain to the signal applied simultaneously to all 15 channels (i. e. ,
with one channel ON).
3.
Chip-disabled crosstalk is the drain output to
signal input ratio. The input signal is applied to
all 16 off channels simultaneously.
13-88
00
55 0 - 0 - - - - - 0
4.
Adjacent input crosstalk (Figure 10) is the ratio
of the signal applied to a source (input) to the
signal measured at any adjacent source. A low
adjacent input crosstalk is required for video applications to avoid ghosting effects that may appear on video monitors or TV screens.
AN86-1
trY' Siliconix
~
incorporated
All Hostile Crosstalk vs. Frequency
180
81
160
E~l--D---o"
140
120
XTALK
(dB)
RIN = 75.0.
;'L = 75.0.
....
100
80
60
""-6--.__.
86~---o----~'~1
87~---o----~'~~
88~---o----~-~~
~b
RIN = 10.0.
RL= 10k.o.
CHANNEL S1 ON
89~-"""'--"""'"
810 ~---o-----o"'"
811 p..----o-----o"'"
812 ~---o----~.
II!!..
~1iIIII
813 ~---o-----o"'"
40
20
o
0.1
100
10
FREQUENCY (MHz)
Figure 8.
SWEEP
GENERATOR"'" V
(75.0.)
ALL HOSTILE
VOUT
CROSSTALK = 20 LOG10--V-
All Hostile Crosstalk vs. Frequency Graph and Test Circuit (DG536)
Chip Disabled Crosstalk VS. Frequency
180
TEST CIRCUIT
See Figure 14
160
81
82
S3
S4
S5
S6
140
120
~~.
XTALK
(dB)
100
87
88
89
81 0
81 1
RL = 50
80
RL =
60
75.o.~
40
~
81 3
81 4
81 5
81 6
0.1
10
FREQUENCY (MHz)
Figure 9.
....,
....,
....,
A
....,
81 2
~
20
o
A
....,
100
SWEEP
GENERATOR
(75.0)
....-:l
....-:l
""V
XTALK(CO) = 20 LOG10
VOUT
--v-
Chip-Disabled· Crosstalk vs. Frequency Graph and Test Circuit (DG536)
Switching Time
The DG535/536 switching time enables use of the device at high multiplexing rates. The low transition
times (toN = 300 ns maximum and tOFF = 150 ns
maximum) make it ideal for fast multi-channel analog
or digital mUltiplexing.
True break=before-make (88M) switching action is
guaranteed by design. This prevents shorting
(crosstalk) of time adjacent input channels during
transition.
Capacitance
Capacitance determines the loading effect of the
multiplexer on signal sources and affects transition
times, as well as system bandwidth.
1.
OFF-state input capacitance gives the loading
of the device (in the OFF state) to a signal
source. With a typical value of 2 pF, this allows
efficient paralleling of many device channels in
multichannel crosspoint matrices with negligible loading effects.
13-89
III
AN86·1
..... Siliconix
incorporated
~
I
VSn-l l
Adjacent Input Crosstalk vs. Frequency
-120
r'"
-100
XTALK
.......
~r--.
I - RIN = 75.0.
-80
(dB)
~
-L
RIN
:
<>n-1
,~!l = til
..t.
..........
-60
-
I
Vsn I
Sn
..... i"o
r-..
-40
-20
SWEEP
GENERATOR
(75.0)
o
1
10
FREQUENCY (MHz)
0.1
100
INPUT CROSSTALK
=20
Vsn-l
LOG10 Vsn
Vsn+l
or 20 LOG10 Vsn
FIgure 10. Adjacent Input Crosstalk vs. Frequency Graph and Test CIrcuIt (DG536)
2.
ON-state Input capacitance also determines
the loading effects of the device ON signal
sources and limits the number of parallel on
channels allowed ,in a large matrix. In large matrixes buffering of the input signals is recommended.
3.
OFF-state output capacitance affects the transition speed of the multiplexer. The output capacitance must be charged and discharged in
turning on and off a device; thus. a low value of
capacitance enables rapid transition times. Table 1 shows a comparison of DG536 capacitance to comparable 16-channel multiplexers.
5MB-PCB MOUNTING
SOCKETS
. E2l ,!l, ~::.:: [GROUND PlAN"
+
L
BOTTOM SIDE
DG536
MOUNTED
ON UNDERSIDE
OF PCB
CIRCUIT BOARD LAYOUT
To optimize the high-frequency characteristics of the
DG536. care must be taken in circuit board layout
and interconnections. Parasitic stray capacitances
caused by poor layout could degrade performance
significantly. As shown in Figure 11. use of guard
planes and traces between signal paths is a good layout practice. Other layout considerations include:
•
short signal paths
•
sufficient power supply decoupling
•
coaxial interconnect of leads. plugs. and
sockets.
•
sockets should be avoided
13-90
FIgure 11. CIrcuIt Board Layout for OptImal Performance
(DG536)
~
AN86-1
Siliconix
,JI;JII incorporated
TABLE 1. Capacitance Value for 16-Channel Multiplexers
DG526
Parameter
DG506A
DG508A
CD4051 12/3
DG536
CS(off) (pF)
10
6
5
10
2
CD(off) (pF)
35
45
50
60
8
NOTE: These are typical values taken from data sheets.
APPLICATIONS
arrangement is useful for providing impedance
matching and greater drive for transmission stages.
Many applications for the DG535/536 will be in video
related systems. Some examples of circuit configurations are included in this section.
VIDEO
The DG536 was
broadcast quality
ance is achieved
+3 V. Differential
level.
designed primarily for handling
video signals. Optimum performwith a bias between +2.5 V and
phase linearity is best at this bias
A general-purpose 16-channel video multiplexer is
shown in Figure 12. DC biasing is achieved with the
divider network R1 and R2. A differential video buffer
amplifier (NE5539) removes the DC level and enables greater multiplexing rates than achieved with
capacitive decoupling. The unity gain buffer amplifier
Alternatively, the device supplies can be offset to
eliminate the need for 16 separate bias circuits. Such
an arrangement, shown in Figure 13, could be used
in a security system or in a remote industrial monitoring system. The DG535/536 positive supply and
ground pins (at -3 V) should be heavily decoupled to
the video camera ground connections.
The switching threshold of the device at a supply voltage of + 15 V is approximately between +6 V and
+8.5 V above the substrate potential (Figure 14).
Since the substrate is held at -3 V, the effective
switching threshold referenced to ground is between
+3 V and +5.5 V. Thus, the device can still be controlled from CMOS logic signals (provided that the
logic 0 ry AL) is less than 3 V and logic 1 ry AHl is
greater than +5.5 V).
..
r--\l--\l--------1--------1 A3
V REF
I I
(+1.5 V)
v-
Figure 15. Using the L161 Quad Comparator for Address Logic Level Shifting
v+
1
R1 toRs
R1
= 100 k.o.
A1
TTL 4-BIT
{
BINARY ADDRESS
A2
A3
~~
i--
-o----t>-~ I--o----t>-~ I-..--. -I'>}
~
":'
":'
v+
DG271
Ao
1 1
R2 R3 R4
DG535/536
Ao
A1
A2
A3
v!: 'L I--
-=
b
v-
11
Figure 16. Using the DG271 for Address Logic Level Shifting
Another technique for achieving high-speed level
translation at a reasonably low cost uses 0169 dual
driver ICs (see Figure 17). The 0169 driver can drive
up to +40 mA continuously and is therefore extremely
suitable for applications where many OG535/536s are
to be driven from a single address bus, such as in
multichannel cross points or large switching matrices.
For single supply applications, TTL to CMOS level
shifting can be easily accomplished using inexpensive CMOS level shifters such as the C04504 or
C040109.
13-93
III
AN86·1
.... Siliconix
incorporated
~
+5 V 0 - - -......- - ,
V+
DG535/536
L-----------IAo
TTL
~----------iAl
ADDRESS
~----------iA2
r----------~A3
VJ,f
0169
VFigure 17. Level Translation using 0169 Dual Driver les
CROSSPOINT SWITCHING
Many analog and digital systems. such as a central
router used in a video studio console (Figure 14).
require crosspoint switching functions. In this application. many channels route signals to many different outputs. Due to its small outline PLCC package
and low power consumption. the DG536 leads itself
easily to multichannel crosspoint functions.
Figure 18 illustrates how the DIS (disable) pin can be
used to indicate which output is selected. When logic
1 is applied to output select. device 1 is enabled and
device 2 is disabled. With device 1 enabled. the DIS
pin is connected to signal ground. thus turning LED 1
on. With device 2 disabled (due to CS being 1). its
DIS pin represents a high impedence to ground and
LED 2 is off.
Anyone of sixteen inputs can be connected to either
output. This is achieved by applying the appropriate
13-94
CMOS logic address to the address inputs (AO to A3)
and applying the appropriate logic level to output select simultaneously.
The circuit in Figure 18 also illustrates how the chip
select inputs can be used. As shown in Figure 19. a
32-channel single-ended multiplexer can be configured without external chip select circuits. This circuit
makes use of the CS and CS inputs which allow device selection from a single control line.
The basic circuit shown in Figure 18 can be extended
and elaborated to give a 16 X 16 matrix for video
crosspoint applications such as central routers used
in video studios. This circuit. shown in Figure 20. allows source (or video input) to be connected to any
video output (or any number of outputs). The strobe
input (ST) on each device is used to latch the appropriate address into that particular device. By strobing
the required address into each device sequentially.
any crosspoint connection can be made.
AN86-1
..... Siliconix
incorporated
~
r-~--~------o+5V
s,V+ENST
,
,
,
,
~~"
LED,
R,
LED2
R2
, DG535/536
,
#1
DIS 1--+---'
SIGNAL
INPUTS
CSf-, Ao to Aa
S'6
GNDCS
1'1
'-- s,
-,
,
-,
'---
~
V+ EN
~~J
D I----IH-+--+---o OUTPUT 2
, DG535/536
,
#2
DIS I---H-+----'
S'6
Ao to Aa GND
It *
OUTPUT
SELECT
'+-+----0
( '1' =O/P, SELECTED)
'0' = 0/P2 SELECTED
~AEg~fgs
Figure 18. The DG535/536 as a 16 x 2 Matrix Switch
The DG535/536 makes an excellent digital switch due
to its low channel-to-channel crosstralk, high off-isolation, and wide bandwidth specifications. In digital
data transmission systems. the DG535/536 can easily handle data rates in excess of 100 Mbps.
The circuit shown in Figure 20 can be used as a digital cross-point to replace expensive, power consuming ECl crosspoint ICs. Besides handling raw digital
data. the DG535/536 can also be used for other
forms of data transmission, such as FSK and PCM
systems.
FSK
Frequency shift keying (FSK). commonly used in
data transmission networks. relies on representing
the digital code with frequency sine wave bursts. An
FSK multiplexing system block diagram is shown in
Figure 21. Each digital level has a specific signal frequency. The DG535/536 can be used to multiplex 16
different digital channels into a single transmission
line or into a transmitter. Similarly. a DG535/536 may
be used to demultiplex the data at the receiving end.
Since the device can manipulate higher frequency
sine waves. data can be transmitted at a higher rate
than with a conventional multiplexer.
13-95
W1P" Siliconix
AN86·1
~
+1 5V
PCM
A more commonly used and faster form of digital
data transmission is known as PCM (pulse coded
modulation). Used in telecommunications systems.
PCM converts analog speech signals into 8-bit digital
words for serial transmission. The data transfer rate
used (for 4 kHz bandwidth voice signals) is 'up to
274.176 Mbps.
{~'
~
VIDEO
IN PUT
CHANNELS
I
I
STV-
~1
75.n.
···
i5S
GNDS
• DG535/536
~
I
CH16
-
~
LADDRESS BUS
RZ (returns to zero) PCM data consists of three discrete (ternary) levels to overcome long periods of
zeroes (Figure 18). Digital signals can degrade beyond legibility after only a few hundred yards of travel
down a transmission line. Therefore. the PCM signals
must be regenerated at regular distances to avoid
excessive distortion.
R
01-
,
EN
CS AntoA
ENABLE
DEVICE
SELECT
The DG535/536 can be used to route PCM signals in
main telephone exchanges. replacing bulky hardwired distribution frames. PCM highways can thus be
rerouted remotely. under computer control. rather
than manually.
VIDEO
INPUT
CHANNELS
incorporated
·,,
01-
S16
GNDS
AntoA"
75.n.
~
I
h
Figure 19. 32-Channel Multiplexer
01
S16
VIDEO OUTPUTS
Slo-~~-+----,~-+~
S20-H~~1-
VIDEO OUTPUTS
}
I
I
I
VIDEO I
'INPUTS I
I
I
I
VIDEO
OUTPUT
SELECT
Figure 20. 16 x 16 Video Crosspoint Circuit
13-96
st6~ I I ~ I
II I
AN86-1
.... Siliconix
incorporated
~
Figure 23 shows the architecture of a conventional
binary distribution frame in a telephone exchange.
Signal regeneration is applied to handle degradation
during transmission and routing. Code converters are
required to change the ternary PCM into binary PCM
for routing within the distribution frame. Similarly.
code converters are required to reconvert the binary
PCM into ternary PCM for transmission.
_
BINARY
PCM
(a) Analog voice signal converted to digital signal
using 8 bits per sample
_
TERNARY
PCM
(b) Digital signal transmitted and clock regenerated
from digital signal to get synchronization
Figure 22.
OUTPUT
TO TRANSMISSION
LINE OR
TRANSMITTER
INPUT
STAGE
D
DIGITAL
INPUT
CHANNELS
Unlike digital switches which require specific digital
signals. using the OG535/536 in the distribution frame
(Figure 24) eliminates the need for code conversion
and meticulous regenera-tion because it can handle
analog signals.
PROGRAMMABLE GAIN VIDEO AMPI-IFIER
'--_ _ _ ADDRESS
BUS
Figure 21. FSK Multiplexing System Block Diagram
The circuit shown in Figure 25 uses the OG535/536
video frequency handling capability to switch feedback resistors in a precision-programmable gainvideo amplifier circuit.
G~,n of the op amp is set by
R1
AV=
+ R Feedback
R1
Central office or main telephone exchange
/
r----------------------------,
PCM Highway from
codecs within main
exchange
REMOTE
EXCHANGE/
SWITCH
OR
DIGITAL PBX OR
CONCENTRATOR
REMOTE
EXCHANGE/
SWITCH
OR
DIGITAL PBX OR
CONCENTRATOR
Couple hundred yards/different floor
~---------------------------Figure 23. Binary PCM Routing Network
13-97
AN86·1
WY'Siliconix
incorporated
~
Central office or main telephone exchange
/
r-------------------------,
PCM Highway from
codacs within main
exchange
PCM Highway
REMOTE
EXCHANGEI
SWITCH
OR
DIGITAL PBX OR
CONCENTRATOR
\.
II
I
DG535/536
CROSSPOINT
..
I
I
REMOTE
EXCHANGEI
SWITCH
OR
DIGITAL pax OR
CONCENTRATOR
~------------------------Figure 24. DG536 PCM Distribution Frame
For example, when R1
= 1 kn,
v+
the results are
TABLE 2. Gains for the Circuit of Figure 25
Logic Input
0000
0001
R Feedback
on
1 kn = (RA)
VIDEO OUT
Gain (Av)
v-
S1
S
RA
2
S3
Ra
S4
0010
2 kn = (RB)
3
0011
3 kn = (RC)
4
S5
S6
The low and fairly constant ON-resistance of the
DG535/536 gives good gain stability, and the resistor
tolerances determine the gain error of the circuit.
The accuracy of the circuit is, therefore, limited by
the op amp CMRR and offset, and the gain of the
circuit is limited by the analog signal range of the
DG535/536.
RF
S
RG
S
S10
S11
S12
R1
RD
RE
S
D
Rc
S13
S
RH
R1
R3
RK
RL
RM
S
~~~~~~~-.RN
L....<:"..-+S:..J.!!6-J1,_ _ _~ Ro
RFEEDBACK
LOGIC---......J
INPUT --::~:-::==-'
Figure 25. Precision Programmable Gain Video Amplifier
13-98
AN86-1
W'r' Siliconix
~
incorporated
ATE
MICROPROCESSOR INTERFACE CIRCUITS
A simple but accurate ATE system, as shown in Figure 26, can be designed for testing digital processing
boards.
On-chip data latches in the DGS3S/S36 simplify interface with a microprocessor data bus. This eliminates
the need for peripheral memory devices (such as 110
ports or D-type latch ICs) to maintain switch addressing while the processor uses its data bus for other
functions.
The propagation delay time for each of the 16 digital
signal paths can be tested individually, with negligible
errors due to the very small propagation delay
through the DGS3S/S36. Also, the variation of delay
times from channel to channel is less than 0.2S ns.
DIGITAL SIGNAL
PROCESSING BOARD UNDER TEST
The data latches are activated by the DGS3S/S36
strobe input (ST). The latch is transparent when ST=
logic 1, thus the device responds to changes of data
at the address inputs. When ST = logic 0, the previous data is latched into the device, regardless of new
data appearing at the address inputs.
The DGS3S/S36 timing arrangements meet the requirements of popular microprocessors, such as the
80BSA, 6800, and ZBO. The BOBSA to DGS3S/S36 interface is shown in Figure 27, and Table 3 illustrates
the timing compatibility of the DGS3S/S36 with the
BOBSA and the faster 80BSA-2 devices.
16 BIT DATA BUS
Figure 24 shows the complete 6800 to DGS36 interface circuit. In order to have a data valid signal, it is
necessary to nand the R IW ICS gate output with the
~2 clock (usually connected to the DBE pin). This
makes the interface circuit functionally compatible
with the 808SA interface shown in Figure 27.
Figure 26. ATE Applications
+15 V
Rl
R2 R3 R4 RS
t::l
.--
r
DATA BUS
-1\
-V
Ao v+ CS
Al
A2
A3
EN
to
+15 V
S16
.,{
t>Cirno7
SOS5A
R6
.uP
SYSTEM
BUS
WR
ADDRESS
BUS
~
AD:ESS
DECODER
I
-'..,
lSI
I
I
). Sl 6
DG535/536
ST
GNDs
D
1'1
D
eS'
~
III
Figure 27. SOS5A to DG535/536 Interface
13-99
AN86-1
..... Siliconix
incorporated
~
TABLE 3.
Timing Compatibility of the DG535/536
with Popular Microprocessors
Specification
SOSSA
SOSSA-2
DGS36
ns/mln.
ns/mln.
ns/mln.
t sw (strobe pulse width)
400
230
200
t ow
(data valid to strobe)
420
230
100
two
(data valid after
strobe)
100
60
50
trasound transducer multiplexing) because the device exhibits inherently low noise and offset voltages.
Two factors affect offset voltage:
1.
Thermoelectric offset voltage is produced by
the incidental thermocouples that exist within
the integrated circuit. There are many intermetallic junctions within an IC. These junctions
act as individual thermocouple has an identical
reversed counterpart. That is. from source to
drain. we have gold-aluminum/aluminum/aluminum-silicon and silicon-aluminum/~luminum
gold. Therefore, if the temperature surrounding
each junction is constant and equal. the thermal
EMFs cancel each other. giving a zero net offset voltage. Since a thermal gradient always exists across the chip, then there is always a net
thermoelectric offset voltage.
For
the
DG535/536. the thermal EMFs produced on chip
are small since the device exhibits a low power
consumption (75 I1W). producing a low temperature on the die.
'2.
Leakage current offset is caused by leakage
current flowing through the rOS of an ON switch
and/or the load resistance. The offset voltage
developed due to leakage current is negligible
since the device has very low leakage currents
(a benefit incurred by the two-level system)
coupled with very low ON-resistance.
Note that open collector gates and buffers could be
used to level shift the TTL logic levels from the microprocessor -to the CMOS levels required by the
DG535/536 logic Inputs.
To achieve the correct ST signal in a Z80 processor
system, the WR and MREQ signals must be gated
with the standard CS signal. as shown in Figure 29.
LOW ANALOG SIGNAL SWITCHING/MULTIPLEXING
The DG535/536 has several uses in handling low-level
analog slgn~ls (such as in medical equipment or ul-
6800
112
jJ.p
SYSTEM
BUS
CONTROL
= OBE
p .....---IST
01-------00
GNOs CS"
BUS
Rl toR6
Figure 28. 6800 to OG535/536 Interface
13-100
= 100k.o.
AN86·1
..,. Siliconix
incorporated
~
zao
,Ilp
SYSTEM
BUS
Figure 29.
zao to OG536 Interface
For example:
V (offset) = IOION) x rOSION)
= ±100 pA (typical @ 25°C)
x 55.n (typical)
= ± 5.5 nV (typically)
The circuit shown in Figure 30 can be used to
remotely monitor up to 16 different thermocouples with high accuracy. The output of the thermocouples is in the form of a small dc voltage,
on the order of millivolts, with typical voltage
changes on the order of tens of microvolts per
°C. Thus, voltage offset developed by the
switching devices can frequently limit system
accuracy.
Using the differential multiplexing technique shown in
Figure 30, high resolution can be achieved since the
thermal EMFs produced by each DG535/536 are canceled as common mode voltages at the Instrumentation amplifier inputs. To minimi;ze pick-up and noise
effects, the same PC board layout rules apply for this
type of circuit. Best accuracy is achieved by ensuring
that the multiplexers are kept close together in a
thermally stable environment.
THERMOCOUPLES
Ix 16)
vo
DIFFERENTIAL
INSTRUMENTATION
AMPUFIER
1..-____
CHANNEL
SELECT
Figure 30. Thermocouple Multiplexing System
III
13-101
W1P" 8i1iconix
AN84·2
~
incorporated
THEORY AND APPLICATIONS
OF THE Si7660 AND Si7661
VOLTAGE CONVERTERS
Doyle L. Slack
Revised February 1988
INTRODUCTION
Many times a simple digital circuit design can be
greatly complicated by the needs of just one or two
of the on board devices. For example, analog devices
often used along with digital circuits (such as op
amps and data acquisition systems) are notorious for
negative voltage requirements of -5, -10 or -15 V
when everything else in the circuit needs only positive voltages. Until recently, the only answer was to
either buy a dc to dc converter module (expensive)
or redesign the power supply to generate the negative voltages (expensive and wasteful in parts count
and space). This Application Note presents the best
alternative to this problem: the 8i7660 and 8i7661
monolithic voltage converters. With the 8i7660 and
8i7661, negative voltages from 1.5 to 20 V can be
generated from a positive supply with minimum parts
count and minimum cost.
~
1
VIN
52
I
I
I
+
01
I
I
I
C2
+
-
~-VIN
an oscillator/toggle circuit, providing charge and
transfer cycles of equal length.
During the charge cycle, 8, and 83 are closed, and
current flows into C" charging it to the value of VIN.
The oscillator toggle then changes state, and the
transfer cycle begins. 8, and 83 are opened while 82
and 84 are closed, allowing C, to dump charge into
C2 until the potential across them has equalized. The
oscillator/toggle then switches again, and the process starts over.
For no load conditions, the voltage inversion will be
virtually perfect since the amount of charge that must
be transferred from C, to C2 will be limited to losses
due to leakage from C2 and any parasitic capacitances. As the load increases, C, must transfer
more and more charge to make up for the depletion
of C2 as it supplies current to the output during the
charge cycle. This action causes the output voltage
to drop, making the circuit appear to be a perfect
inverter in series with an output resistor that varies in
magnitude with the input voltage. Figure 2 shows this
concept in a two port diagram of the device, and Figure 3 illustrates the typical output characteristics of
both devices configured in the inverter mode.
r-------------,
I
Theory Of Operation
The basic theory behind the 8i7660 and 8i7661 is the
same and is based on the ideal voltage doubler
shown in Figure 1. Capacitor C, is the pump capacitor, and C2 is the reservoir capacitor. The pairs of
switches (81 with 83, and 82 with 84) are driven by
13-102
Ro~
/
FIgure ,. The Ideal Voltage Doubler
\
I
o--!__R_ln4_ _
~---.lJ.-V-ln--_T_-O
IL ____________ -.II
FIgure 2. Two-Port Diagram of the Voltage
Converter Circuit
\
Jut
AN84-2
.... Siliconix
.c;II incorporated
2
4t -
v+'= 3 ~10'
V
-
o
-2
~
~
V OUT -4
,/
.",
.",
I' ~
~ ~
(V)
....
-6
~
I ' I,..;"
-8
I" t.....
I"
-10
o
~
,
5V'-'6V I ~
"....
.",
~
~
.-" I '
- -,,-
~
20
~
./
./
~
-- ---
A
~
~
40
./
./
V'
~
~
"..
V
V
7V
8V
9V
10 V
"....
60
80
Figure 3 (a). Output Characteristic of
the 517660 Voltage Converter.
V+
0
-4
VOUT -8
(V)
-12
-16
-20
- ---- --------------- -~
~
,,-
...-
f-'"
...... f-
i.--~
~
f~
~
20
40
------- -~
k--"
,,- ....
-~
o
=8 V I
/
".. ~
60
The oscillator supplies the signal to the divider section which in turn drives the rest of the circuit. The
OSC input has an input impedance of approximately
1 M n. This allows the internal oscillator to be overridden by an external clock or to be slowed down by the
addition of an external capacitor.
100
OUTPUT CURRENT (rnA)
2
are very similar. description of the operation of the
Si7660 and Si7661 is combined. The internal sections
of the circuit are the oscillator. divider. regulator.
level translator. and substrate logic. Figure 4 shows a
block diagram of the internal sections of the inverter
circuit .
10 V
12 V
The internal regulator is a series voltage regulator
with a zener reference to insure that low voltage
components of the circuit are provided with no more
than 5 V when the input voltage is greater than 5 V. It
also provides current limiting for the oscillator and
divider circuits. When the input voltage is less than
3.5 V for the Si7660 (less than 9.0 V for the Si7661).
the LV pin is grounded. bypassing the internal regulator. However. when the Si7660 is operated above
3.5 V. the LV pin must be left open to provide
latchup protection. For the Si7661. LV should be left
open above 9.0 V for proper operation.
14V
16 V
18 V
20 V
80
100
OUTPUT CURRENT (rnA)
Figure 3 (b). Output Characteristic of the
517661 Voltage Converter.
Circuit Operation
With the Si7660 and Si7661. the only parts of the
doubler not included inside the package are the
pump and reservoir capacitors.
The internal
switches are made with P-channel and N-channel
MOSFETs. The main difference between the Si7660
and Si7761 is the breakdown voltage of the MOSFETs
which in turn dictates the maximum input voltage.
Also. the design of the Si7661 offers a much greater
resistance to device latchup. which is discussed
later. Since the internal sections of the two devices
Figure 4. Block Diagram of the Voltage Converter Circuit
The divider is simply a divide-by-two counter that provides complementary outputs. Q and Q drive the inputs of the level translators. which in turn provide
the necessary switching voltages to drive the
MOSPOWER switches. The bUilt-in delay of the translators guarantee that break-before-make action occurs.
13-103
l1li
AN84·2
.... Siliconix
.JI;II incorporated
The substrate logic network insures that two things
happen. First, it makes sure that the substratesource/drain junctions of 03 and 04 are never forward biased, and that the ON resistance of each of
the output transistors will be as low as possible for all
operating conditions. Second, the network determines the most negative voltage in the device and
uses it to supply power to the level translator.
Figure 5 gives the pin configuration of the Si7660 and
Si7661. These devices are pin compatible with competitive products. Functionally, the SI7660 is an exact
replacement of the industry standard voltage converter competition while the Si7661 provides the advantage of greater voltage range at the expense of
slightly higher output resistance.
NCOBV+
CAP+ 2
7 OSC
CAP+ 2
GROUND 3
6
LV
CAP- 4
6
VOUT
vice to latch up. As Figure 6 shows, the source of
the N-channel device becomes the SCR cathode; the
source of the P-channelis the anode; and either
drain can act as a gate. Since an SCR does not trigger until certain conditions occur, It can sometimes
cause no problems at all, yet sometimes it may be
fatal to the CMOS device.
The intrinsic SCR needs three conditions to cause
latchup. First, the current gain products (betas) of
the two parasitic bipolar transistors must be greater
than one. Second, the current flowing through the
channels of the devices must be greater than the
holding current of the SCR. Finally, some kind of
pulse must be applied to one of the gates to trigger
the SCR action.
The trigger pulse can come from several different
sources. The power-up sequence of the CMOS device may cause problems if the SCR gate receives
power before the other terminals. Another possible
trigger source is a high slew rate across the intrinsic
SCR. When the SCR is triggered, the CMOS devices
are suddenly shorted out by the SCR, and the output
impedance of the device becomes very low.
04 of the Si7660 can sometimes experience the conFigure 6. Pin Diagrams of the TO-99 and 8-Pln DIP
Packages for the SI7660 and SI7661
Figure 6. IntrinSiC SCR Superimposed on a
CMOS Gate Structure
Latchup
Because of the basic internal four-layer geometry of
CMOS devices, an SCR action can sometimes occur.
Figure 6 depicts the SCR structure. This SCR action
can, under certain conditions, cause the Si7660 de-
13-104
ditions to cause SCR latchup when operating at the
upper end of the Input voltage range. The nearby Pchannel substrate logic transistors form the complementary part of the Intrinsic SCR. When the SCR action does occur, the circuit suddenly appears to be a
short circuit betweenVIN andVouT. The reservoir capacitor (~) rapidly discharges through this path. After ~ has discharged, the current through 04 drops
below the SCR holding value, and the circuit resets. If
the conditions that originally caused the SCR action
remain present, the device will latch up repeatedly. If
the circuit input is not current limited, this action can
sometimes dissipate too much power through 04 and
the substrate logic, resulting in damage to the device.
To prevent damage to the Si7660 when conditions for
latchup occur, older versions required a diode In ~e
ries with the VOUT pin to block the discharge of ~
and keep the current below the holding value of the
SCR. This diode was used whenever the input voltage
could exceed 6.5 V at room temperature. Figure 7
shows the operating range of the improved Si7660.
AN84-2
..... 8i1iconix
JI;;II incorporated
v+
I
8
3
Ie
(nA)
4
Figure 8. Schematic Diagram of the Basic
Inverter Circuit
-55
25
85
2
125
0
TA (OC)
Figure 7. Range of Input Voltage and Operating
Temperature for the 517660
-4
VOUT
(V)
The 8i7661 is a higher voltage device than the
8i7660, and is designed on a different process. This
high voltage silicon gate process reduces the parasitic betas in 04 to a value that makes it extremely
difficult to produce the conditions for latchup. Because of this, the series diode is not needed for
proper operation.
-8
.A-'
...,.. -~176~0
--
V+
-.......s';Sl1t
-12
-16
-20
I-- f-""
o
=5 V
Vi
20
=
40
i-'" I-'"
V
SO
80
100
OUTPUT CURRENT (mA)
General Applications
The 8i7660 and 8i7661 are intended for use as voltage inverters. However, with a few added components, the inverter circuit can be rearranged to provide many different voltage levels. In some configurations, they can even provide more than one voltage output at the same time. The possibilities include
voltage inversion, voltage multiplication, and even simultaneous inversion and multiplication.
Figure 9 (a). Variation of Output Voltage as a
Function of Output Current
2000
1000
500
\
200
\
ROUT
(.n. )
100
517661
V+-15 V
50
vrr
Basic Voltage Inversion
517660
20
With no load, the output voltage magnitude of the
basic voltage inverter circuit shown in Figure 8 will
typically be within 0.1% of the V+ (input voltage)
magnitude for the 8i7660 and within 0.3% of the input
voltage magnitude for the 8i7661. As the load current increases, the output will drop as shown in Figure 9 (a). The effective output resistance will vary
with input voltage as given in Figure 9 (b). Once the
load current reaches its limit (30-40 mA for the 5 V
case), the inverter can no longer regulate the voltage
properly and shuts down to protect itself from extreme power dissipation.
=
=
10
o
10
INPUT VOLTAGE (V)
20
Figure 9 (b). Variation of Output Resistance as a
Function of Input Voltage.
CAUTION: At higher input voltages (for either device), the output maximum limit can cause the power
dissipation to exceed the maximum rating of the
package (especially plastic). Always calculate the
maximum power dissipation for your design.
13-105
l1li
AN84·2
.... 5i1iconix
incorporated
~
TABLE 1
Effect of Varying the Pump and Reservoir Capacitor 5ize on Output Ripple Noise.
Capacitors
(J.1F)
VOUT
(V)
VR
(mvp_p )
5i7660
Inverter Mode
(see Figure 8)
V+ = +5 V
lOUT = 10 mA
10
22
47
100
470
1000
-3.838
-3.862
-3.873
-3.874
-3.879
-3.880
150
75
30
26
10
5
5i7661
Inverter Mode
(see Figure 8)
V+ = +15 V
lOUT = 10 mA
10
22
47
100
470
1000
-13.849
-13.872
-13.882
-13.883
-13.885
-13.890
175
80
38
29
10
5
The output ripple of the Inverter is a function of the
oscillator frequency as well as the size of the pump
and reservoir capacitors. The nominal oscillator frequency is 12 kHz for the 5i7660 and 10kHz for the
5i7661. Because the output ripple is important in
some linear applications where supply noise is critical, Table 1 provides ripple values for different pump
and reservoir capacitor values.
It is important to note that increasing the capacitor
size can lead to other difficulties. The main problem
is that the large capacitors may draw excessive
amounts of current at turn-ON. If the current is too
great, the power disSipation of the device can be exceeded causing destruction of the converter. Even
when the device is running, the charge transfer under heavy loads can push the switches to their limits.
As stated before, the LV pin shorts out the internal
regulator at low voltages when it is tied to ground.
The LV pin should be grounded for operation below
3.5 V for the 5i7660 and 9.0 V for the 5i7661. However, it is necessary to leave the LV pin floating for
high voltage operation, as shown in Figure 10. Failure
to do so could permanently damage the device. Figure 11 shows the Inverter configured for low voltage
operations.
v+
8
VOUT
2
10JlF
3
6
4
6
v+
8
2
°1+
10JlF
817660
--I::"()
-=-
Figure 11. Inverter Circuit Connections for
Low Voltage Operation
7
3
6
.::c.
4
6
-
°2
10JlF
Figure 10. Inverter Circuit Connections for
High Voltage Operation
13-106
VOUT
Voltage Multiplication
5ince the inverter design is based on the ideal voltage doubler, it is easy to convert the 5i7660 and
5i7661 devices to provide doubling of the input voltage. Figure 12 gives the schematic diagram of the
AN84·2
tI'7' Siliconix
~
incorporated
voltage doubler. This circuit requires only two additional diodes and will provide positive voltage multiplication at the expense of the voltage drops of the two
diodes in series with the output. This means the positive multiplier will not be able to provide the near perfect output function like the basic inverter circuit
does. The output voltage of the multiplier will be:
=2
VOUT
v+
.-----12
3
8
C
-
7
3
6
4
V+
(2)
(V+) -2 Vdlode
2
resistance, providing a smaller output voltage drop
for a given current. This circuit will also expand the
operating output current ranges slightly. Each device
must have its own pump capacitor, but the reservoir
capacitor is shared between all of the devices.
°1
°2
+
VOUT
+
5
-=-
-I-
c
Figure 13. Combination Inverter/Multiplier Clroult
Figure 12. Voltage Doubler Schematic Diagram
The circuit of Figure 12 can also be used as a Negative-to-Positive voltage converter. To do so, set pin 8
to Ground and pins 3 and 5 to the negative input voltage, V-. The output voltage will then be:
VOUT
= I V- I -
2 Vdlode
v+
(3)
Simultaneous Inversion And Multiplication
The circuit shown in Figure 13 will provide both positive multiplication and inversion at the same time.
The output voltages will be the same as those given
in equations 1 and 2. This configuration is limited by
the load current that can be drawn out of either output before the circuit becomes overloaded.
Parallel Connection
Although a single Si7660 and Si7661 cannot supply
very large amounts of current, higher currents can
be provided when several devices are connected in
parallel. As shown in Figure 14, two or more inverter
circuits can be paralleled to provide a lower output
Figure 14. Paralleling Multiple Voltage Converters for
Increased Current Capability
When two or more devices are paralleled, the output
noise (ripple) will contain not only components at
frequencies of each of the oscillators, but also at
sum and difference frequencies due to a mixing action at the inverter outputs. If such noise cannot be
tolerated, the OSC pin of one of the devices can be
driven by an exclusive NOR gate that compares the
oscillator frequencies of the two devices as shown in
Figure 15. This forces the two devices to alternate
their charge and transfer cycles, which will not only
reduce output noise but also maximize efficiency.
13-107
AN84-2
.... 8i1iconix
,Jl;II incorporated
caded devices increases, the effective output resistance also increases which will severely reduce the
output voltage for a given current level when compared to a single inverter. This effect can be reduced
by paralleling devices in the first stages, though the
cost in parts increases twofold for every added
stage.
v+
+5V
SUPPLY
3 IL + 310
v+
LOAD =
31L +210
GND
Vs
IIII
31L + 310
OV
41L+ 31 0
6 IL + 510
2 IL + 210
v+
1----,.........-0
20~F
=:G
VOUT
(-5 V)
LOAD =
21L + 10
°1
vOUT
GND
4 IL + 310
v+
Figure 15. Synchronizing Two SI7660's or SI7661's
with a Single Exclusive NOR Gate
When high voltage inversion is desired, inverter circuits can be placed in series to produce voltage outside of the operating range of a single 8i7660 or
8i7661. Figure 16 shows two inverters cascaded to
double the input voltage magnitude while inverting
the voltage at the same time.
RL
IL + 10
LOAD =
IL
GND
Series Connection
IL
°2
2 IL + 10
V
21L + 10
03
VOUT
IL
IL
V01= Vs-RO (3IL+210) VOUT=- [ 3VS-RO (14IL+ 81 0)1
V02= vs- Ro (51L +310)
VC3= Vs-RO (6IL+ 31 0)
Figure 17. Current Model of Cascaded
Voltage Converters
Changing The Oscillator Frequency
The typical oscillator frequencies were given in the
description of the basic inverter circuit. However,
Figure 18 (a) shows that the maximum power efficiency is not achieved at the typical oscillator frequency. If maximum power efficiency is desired, an
external capacitor can be connected between the
08C pin and ground. Figure 18(b) illustrates the effect of added capacitance on the oscillator frequency.
Figure 16. Cascading Devices for Greater Output
Voltage Range
When cascading devices, however, the power dissipation of each device must be considered. As each
new stage is added, the previous stages will be subjected to more and more load current, from both the
quiescent current of the new stage and the multiplying action of the load current through each of the
stages, as shown in Figure 17. As the number of cas-
13-108
If synchronization with an external driver or clock is
needed, the 08C pin can be driven either by a TTL or
CM08 logic gate. Figure 19 provides the proper circuits for interfacing to either logic standard. Note
that the TTL interface can only be directly connected
to the 08C pin if the circuit is using a 5 V supply. If
the input voltage is other than 5 V, some type of
buffer circuit will be required. The charge/transfer
transitions will occur on each rising edge of the
clock.
AN84·2
fIf"fl" Siliconix
~
incorporated
100
95
90
Efflc.
(%)
SI~660
V+ = 5 V
~
..............
..........
,
There are many places where a low current negative
supply made with an Si7660 or Si7661 would do just
as well as a full conventional negative supply or dcto-dc converter module. Some examples of possible
uses are power sources for operational amplifiers,
dynamic RAM's, microprocessors, and data conversion products. Several examples of these systems
are given below.
_
""
85
SU~1=
80
\
15 V
V+
75
v+
v+
70
10
20
2
5
OSCILLATOR FREQUENCY (kHz)
50
1K
Figure 18(a). Graph of Efficiency Versus
Oscillator Frequency
-=
2
7
3
6
4
5
CMOS
GATE
vOUT
20,000
10,000
==
........
SI7661
V+ - 1 5 V -
~
""
1000
fosc
(Hz)
SI7660
V+ = 5 V
v+
8
"-
100
'\ "\.
10
100
1000
4.7 K
1K
2
"-
20
1
v+
v+
-=
TTL
GATE
7
3
6
4
5
-
Jil0 F
vOUT
JL
10,000
Cos c (pf)
Figure 18(b). Graph of Oscillator Frequency Versus
Added Capacitance
Specific Applications
When looking at possible applications for the Si7660
and Si7661, it must be remembered that these devices are VOLTAGE sources, not CURRENT sources.
Therefore, any heavy load will either greatly reduce
output voltage (possibly out of the desired range) or
cause the device to go into power shutdown. If the
concept of VOLTAGE conversion is kept in mind,
many problems will be avoided.
Figure 19(b). TTL Drive Circuit for the SI7660
or SI7661 (5 volt Input only)
Memories
Several different memory manufacturers produce
16K x 1 dynamic RAM's that have a need for a -5 V
low current supply to provide substrate biasing. The
National MM5290, AMD AM9016, and THOMSON
MK4116 all use this type of arrangement. Table 2
gives the -5 V supply current requirements for each
of these devices.
13-109
~
__
AN84·2
..... Siliconix
incorporated
~
TABLE 2
Current Requirements of Several Different Dynamic RAMs.
Operating Current
Standby Current
Refresh Current
!lI.A)
(/l.A)
(/l.A)
MM5290 (0 to 70°C)
200
100
AM9016 (0 to 70°C)
200
100
200
200
AM9016 (-55 to 85°C)
400
200
400
MK4116 (0 to 70°C)
200
100
200
Device
The only constraint in using the Si7660 or Si7661 for
this application is when calculating the voltage fluctuations that will occur when a location is read from
or written to. Make sure that the ABSOLUTE MAXIMUM current is considered so that the negative supply for the dynamic RAM will not be pulled down more
than 5% (below 4.75 V) during a memory read or
write. Even with the maximum current taken into account, the Si7660 or Si7661 could easily provide the
negative supply voltage supply for an entire 16K x 8
dynamic memory bank.
Figure 20 shows the Si7661 supplying the negative
voltage to a 741 op amp configured as an inverting
amplifier. As the current drain through the negative
supply terminal of the op amp increases, the output
voltage of the Si7661 will decrease. However, this
will not affect the output capability of the op amp at
its rated output current. Figure 21 illustrates this with
a photograph of the input and output of the circuit in
Figure 20 when a 1 kn. load was placed on the amplifier output. The output was undistorted to 26 V peakto-peak.
Op Amps
The output ripple of the Si7661 must be taken into
consideration when using it as an op amp supply.
Some op amps do not have adequate power supply
rejection to withstand the ripple noise level of the
Si7661. The pump and reservoir capacitors can be
chosen to minimize this noise condition (see Table
1). The ripple should be measured at the maximum
negative supply current (i.e., rated load) to determine if the Si7661 can be used to supply the op amp.
Operational amplifiers are one of the most commonly
used integrated circuits and often use negative supply voltages. Although some op amps can supply
high current loads, more often the current requirements involved are well within the capabilities of the
Si7661.
+15 V
Figure 21. Output of the 741 Inverting Amplifier
at Maximum Undlstorted Output
r.
~
::.."I
!:
IIIiii
ri1
!'=
r.
ri1
~
IIiiiiII
IiIIiiiI
~
1DDJ1F
~
rJ
11
L!J
1DDJ1F
Figure 20. Using the 517661 to Generate the
Negative Rail for a 741 Op-amp
13-110
I'L!J
500 J1 5/DIV.
I.!,j
':i
100:
5 V/DIV.
H
AN84·2
Siliconix
incorporated
MIC
+12 V
20 k.D.
1 k.D.
-
I
v+
6anF
+12 V
DG305A
J;n
13
12
SPKR (VOX)
-
+12 V
I
I 10
I
9
J
Va
5
a
25176617
3
6
4
5
l.l1F
11
1 k.D. +
HANDSET
I
+12 V
14
10 k.D.
-
10 k.D.
2
555
7
3
6
4
5
1nF
2
3
13
4013
12
4
11
5
10
1
6
9
-
7
a
Figure 22. Using the SI7661 to Supply a Low-current Analog Switch Current
Analog Switches
Although in most cases the Si7660 or Si7661 cannot
supply sufficient current for analog switch applications, there are some exceptions. For example, Figure 22 gives the schematic diagram of a circuit that
was used to interface a Northern Telecom telephone
set to an ICOM 2AT2-meter amateur radio transceiver. New designs should use the silicon-gate
DG402 SPDT switch.
microprocessor is a good example of this. It is an
inexpensive 8-bit CPU that has many different support chips available. To provide the negative supply
voltage (-5 V), a basic inverter circuit (such as in
Figure 8) using an Si7660 is connected to pin 11 of
the microprocessor. The 8080 negative supply draws
a maximum current of 1 mA which will not pull down
the supply voltage to any great degree.
Data Conversion
The analog switch provides isolation for the microphone and speaker connections of the transceiver
since the telephone set uses a single path for both
transmission and reception. The telephone was operated at 12 V for direct interface to the DG305A, and
the supply current from the Si7661 was < 1 mAo
Microprocessors
Some of the older standard microprocessors need a
negative supply for substrate biasing. The Intel 8080
Data conversion and acquisition products often have
the same problem as op amps, in that noisy supply
voltages can cause operational problems. However,
the problems caused here can have a much greater
impact on the operation of an AID or DI A converter.
Since power supply stability can be an important factor in specifying nonlinearity for data conversion
products, it is easy to understand that slight fluctuations in supply voltage could be disastrous to a precision measurement system.
13-111
--=~
AN84·2
WY'Siliconix
incorporated
~
The Siliconix Si7135 is a 4-1/2 digit integrating AID
converter that requires a negative supply when operating over a ± input voltage range. Figure 23 gives
the schematic diagram of a DVM circuit using the
Si7661 to supply the negative voltage for the Si7135.
Regulator Circuits
This section discusses some of the possible methods
for using the Si7660 or Si7661 in constant-voltage
output circuits over a given output current range. For
low current inverter applications, the circuit shown in
Figure 24 can be used. The output impedance of the
circuit can be as low as 5 .n with regulation up to
approximately 20 mAo Note that if converters are par-
alleled on the output of this circuit, they should be
synchronized to minimize output voltage fluctuations
and output noise.
Another regulator application uses the Si7660 or
Si7661 in a positive voltage regulator. Conventional
three terminal voltage regulators have a voltage drop
of greater than 1 volt between the input and output
when operating with fairly heavy load currents. The
circuit given in Figure 25 uses an Si7660 or Si7661
voltage converter to double the voltage which is then
regulated by the op-amp and FET. This configuration
allows regulation without the voltage drop as long as
the input voltage does not drop below the Zener voltage plus the product of 10 times rOS(ON).
-5 V
+5 V
~/oooo
-/-/UUUU
B
....----12
7
SI7661
3
6
'--_ _-14
5
BP
+5 V
100,ILF
+5 V
tr:::
OF412
C04054
4
INPUT
4
CLOCK
-5 V
Figure 23. SI7661 Used In a DVM Circuit
13-112
AN84·2
.-F' Siliconix
~
incorporated
V+
7 to 8 V
56 k.n.
V OUT
-5 V
910 k.n.
8
50 k.n.
.-----12
z
V
1.5 V
Sl7661
7
3
6
L----l4
5
100.lJ.F
CONCLUSION
"i
Figure 24. Low Current Inverting Regulator Circuit
V+
1
Therefore, as long as the input voltage does not drop
below 5.26 V, the input is guaranteed to be regulated
as close to the zener voltage as can be attained by
the common mode offset voltage of the op-amp. By
selecting the correct zener diode, this circuit can
supply more than 100 mA and can be adjusted for
varying voltage outputs up to the input voltage limit of
the voltage converter.
The Si7660 and Si7661 can be inexpensive alternatives to full negative supplies in many different low
cost applications. Although they are designed for
generation of negative voltages, many different voltage levels can be generated with a few additional
parts. The Si7660 and Si7661 are pin compatible to
competitive products and function as well or better
than the competition in every operating specification.
The examples given here are only a few of the many
possible applications that could utilize the benefits of
reduced board space and cost that the Si7660 and
Si7661 provide.
8
617660
2
7
or
617661
-
3
6
4
5
-
+
10.lJ.F
10.lJ.F
+
1
V
1K
z
For ID
L---l------+.-o V OUT
-
= 50
mA:
VIN > Vz + (I D X rDS(ON))
VIN > 5.2 V+ (50 mA X 1.2.0)
VIN > 5.26 V
III
Figure 25. Schematic Diagram of the Positive
Regulator Circuit
13-113
tI'7' 8i1iconix
AN83·14
~
incorporated
A SIMPLE APPROACH TO
Si7135/8085 INTERFACING
By Doyle L. Slack
December 1983
INTRODUCTION
vREFERENCE
Many AID conversion designs in use today are both
complex and confusing, and for these reasons they
are often overlooked for use in more simple applications. Up to now, many Analog-to-Digital (AID) converter chips have not been microprocessor compatible; the interfacing schemes to make them so have
been unnecessarily complicated. But now a simple,
straightforward AID converter can be constructed using only the 8i1iconix 8i7135 and one other IC. It can
be easily interfaced to most machine level or high
level language computer systems using 1/0 ports.
This system would be ideal for remotelfield monitoring or storage of slowly changing conditions with
minimum maintenance requirements.
CIRCUIT COMPONENTS
The 8i1iconix 8i7135 IC is a 4 1/2 digit integrating AID
converter intended for use as a digital volt meter
(DVM) chip. Using the dual slope method of conversion, it can achieve an accuracy of ±1 count in
20,000. 80me of the other features are overrange,
underrange, and polarity indications, allowing
autoranging and a measurement range of -1.9999
volts to +1.9999 volts. At the optimum clock rate of
120 kHz, approximately 3 conversions per second
are possible. Figure 1 gives the pin diagram of the
8i7135.
The other half of the A/D system is the Intel 8085
microprocessor -- an inexpensive 8-bit general purpose Central Processing Unit (CPU) that can be operated with a minimum of peripheral devices. With its
internal clock circuitry, the only external devices
needed to make a working system are address
de multiplexing , 1/0 ports, and memory. The latter
two are supplied by the Intel 8155 RAM-I/O and 8755
EPROM-I/O chips. By connecting the data and control
lines of the 8i7135 AID system to the 1/0 lines of the
microprocessor system, the data can be read and
processed in whatever way the user chooses via
software.
13-114
ANALOG COMMON
INT OUT
AZ IN
BUFF OUT
REF. CAP. REF. CAP.
+
IN LO
UNDERRANGE
OVERRANGE
S'i'ROiiE
R/H
DIGITAL GND
POL
CLOCK IN
BUSY
(LSD) 01
IN HI
02
v+
D3
(MSD) 05
D4
(LSB) B1
B2
(MSB) B8
B4
Figure 1. Pin Diagram of the Sl7135
4 1/2 Digit AID Converter
CIRCUIT DESCRIPTION
Figure 2 shows the schematic diagram of the 8i7135
AID converter circuit connections to an Intel 8085 microprocessor system. The 8i7135 outputs are
straightforward in their functions. The OVERRANGE
output goes to a logic 1 when an overrange condition
(down count exceeds 20,000) has occurred on the
previous measurement. The UNDERRANGE output
goes to a logic 1 when the input measurement is less
than 10% of full scale. The POLARITY output goes
high for positive readings and goes low for negative
signals. RUN/HOLD is the only control signal from the
microprocessor and can be used to stop the measurement cycle of the 8i7135 and hold the last reading
for as long as the line is held low. The other direct
outputs from the 8i7135 are the data lines which provide the data in BCD format for each of the 5 digits.
The tricky part of the interface is the digit strobe decoding circuitry between the AID converter and the
microprocessor.
Figure 3 gives a simplified timing diagram of the AID
system. When the 8i7135 BU8Y line (PA7) goes high,
either the data from the last reading is valid or the
OVERRANGE line (PBO) is high. If an overrange is indicated, the microprocessor displays OL and waits
for the next reading. If the data is valid, each of the
AN83-14
..... Siliconix
incorporated
~
taining both status and data information is decoded.
and the port is read again to verify the data for the
particular digit being input. After the entire voltage
reading has been input. the POLARITY line (PB1) is
checked. and the reading and polarity are displayed
by the microprocessor. The system then waits for the
next conversion. For more details on how the microprocessor handles the data. see SOFTWARE.
digit drive signals from the Si7135 goes high one at a
time. sequencing from D5 to D1 repeatedly. The
4532 priority encoder condenses the 5 digit drive signals into 3 bits (PA4-PA6) which are combined with
BUSY to make up the upper nibble of the input data.
The BCD data lines (PAO-PA3) make up the lower
nibble. and the BCD data presented corresponds to
the digit drive that is high at the time. This byte. con-
PBl
PBO
1 I
O.l,1l~
IN-
I
100 K
AGND
~
4532
11 23 27 21
16
PA7
10
12
2
6
PA6
9
17
1
7
PAS
2
18
13
9
PM
19
12
8 :...--
PA3
3
P' . ::R
SI7135
20
22
r-og~~~~)
::
l,1lF
II--
I
yV
V
100 K
IN+
5
11
10
PA2
4 :...-3
f-INTEL
8155
DATA
BUS
INTEL
8085
I--
r - - - PAl
-
I I
II
PAO
--:i=-
6
100 K
7
R
.4
1
~~ l-~-5V
l,1lF DGND
Figure 2. Schematic Diagram of the SI7135 to 8085 System Interface
BUSY
I
05
n
D4
I
D3
n
n
n
n
n
IL
I
BUSY
-.J
L
OVERRANGE
..
COUNTER
Figure 3. Timing Diagram of the SI7135 AID Conversion System
13-115
WY' Siliconix
,./1;11 incorporated
AN83·14
MULTIPLEXING Si7135 SYSTEMS
It would be desirable to be able to monitor more than
one analog signal at a time, since often several different events or conditions of interest occur simultaneously. Since the conversion time of integrating
converters is relatively slow, the outputs of several
AID converters can be multiplexed without the loss of
time that multiplexing the inputs of a single AID converter entails. The Si7135 system lends itself to this
type of use very easily without typing up a large number of additional 110 lines. By multiplexing the outputs
of each of the AID converters, many inputs can be
monitored with little additional hardware.
Figure 4(a) shows how the AID converter systems
can be multiplexed quite simply by using tri-state
buffers. The RUNIHOLD line of the desired converter
is pulled low when a reading is needed from that particular AID system. The buffers for that system are
then enabled, and the data from the Si7135 is read in
the same manner as before. The RUNIHOLD line is
then sent high, and the other converters are read
sequentially in the same way. This method uses only
two extra 110 lines and two 4503 buffer chips for each
additional AID converter added to the system. Figure
4(b) shows a detailed schematic of 1/3 of the mUltiplexed system. Each section that is added to the system is wired identically and connected to the 1/0 bus.
P8s
P80
IN2
SDK-85
SYSTEM
POo
P13
P10
FIgure 4(a). SchematIc DIagram of the MultIplexed SI7135 AID Converter System
13-116
~
AN83-14
Siliconix
.IIJJI incorporated
P85
~f 1.-------,
16
11
1
~ '3~0
TO TIMING
AND POWER
(SAME AS
FIGURE 2)
25 21
::
...
~
4
tSVO
I 453U
16
19
12
8(--
20
11
4-
~
~
10
7
16
8
15
:
28
23
I'
31---+----1 P05
51---+----1 P04
,----1
:0
71---+----1 P03
9~--~--~
1=
P02
1
8
TO 8155
1/0 BUS
4503
3
I 1
P82
-~
l
v
2~: p,- ':._=_~_-_=_: : _-_=_: : _-_=_: : _-_=_: : _-_=_: : _-_=_: : _-_=_: : _. . J_=_ =_~____~~:
lL----------------------------------t
I
P07
131---1---1 P06
r-------------j 2
1------1:, :~
~ 6
11~--~--~
14
~5~=
~
15
~------------------------------_;12
I
l' l'
15 11 1-__+
IL-__________________________-I 14
2
'------------------;4
L-------------------i6
1_ 1
108
__--1 PO 1
13
POo
3.~--~--__I P13
5 1 - - - + - - - 1 P12
7~--~--~
P11
19~--~--~P10
4503
Figure 4(b). Schematic Diagram of 1/3 of the Multiplexed AID System Shown In
Figure 4(a). Including Pin Diagrams of the Components
SOFTWARE
The software used to read the data from the Si7135
system is shown in Table 1 along with comments on
what each command does. This software was written
for the Intel SDK85 monitor. The UPDAD and UPDDT
subroutines display the data by writing to the 8279
display controller. The OUTPT subroutine outputs the
data stored at the location pointed to by the Hand L
registers. Only minor changes or additions to the
software shown here would be required to store large
amounts of readings or read several different inputs
simultaneously. Also, this program does not utilize
the RUN/HOLD or UNDERRANGE lines.
This program was written to run by itself on the Intel
SDK85 ~ystem. However. if the A/D converter routine
is to be used as a subroutine of another program. the
starting address of the subroutine should be changed
to 2003H, or NO-OPs (00) should be placed in locations 2000-2002H to eliminate unintentional resetting
of the stack pointer. Also, RET (C9) should replace
the JUMP instructions at address locations 2037H and
207FH. The instructions at locations 202EH through
2037H should be deleted.
If multiple AID units are to be connected to the microprocessor, a routine like the one shown in Table 2
would work well. The program shown in Figure 5 has
been modified and named READ for this example,
and ports 0, 1. and 8 of the SDK85 system are used
for the data transfer.
13-117
...... Siliconix
incorporated
AN83·14
~
TABLE 1
Program for reading in and displaying the data frorn the SI7135 AID converter system.
COMMENTS
ADDRESS
MNEMONIC
OP-CODE
2000
LXI SP. 20C2H
31
C2 20
Load stack pointer
2003
2005
2007
2009
MVI A. OOH
OUT 02
MVI A. OBH
OUT 03
3E
03
3E
D3
00
02
OB
03
Set up data direction register for 1/0 ports
200B
200D
200F
2011
IN 00
ANI BOH
SUI BOH
JNZ 200BH
DB
E6
D6
C2
00
BO
BO
OB 20
Check for BUSY. If not. walt
2014
2016
2017
IN 01
RRC
JNC 203AH
DB 01
OF
D2 3A 20
201A
201C
201E
2021
2024
2026
2028
202B
MVI A. 01H
MVI B, OOH
LXI H, 20B2H
CALLOUTPT
MVI A, OOH
MVI B, OOH
LXI H, 20B4H
CALL OUTPT
3E
06
21
CD
3E
06
21
CD
01
00
82
B7
00
00
B4
B7
202E
2030
2032
2034
IN 00
ANI80H
SUI80H
JZ 202EH
DB
E6
D6
CA
00
80
80
2E 20
2037
JMP 200BH
C3 OB 20
203A
MVI B, ODOH
06
203C
203F
CALL DIGIT
MOV D, A
CD AO 20
57
Get first digit and put It In the proper register
2040
MVI B, OCOH
06
Set pointer to value of second strobe
2042
2045
2046
2047
2048
2049
CALL DIGIT
RLC
RLC
RLC
RLC
MOV E, A
CD AO 20
07
07
07
07
5F
Check for OVERRANGE. If not. continue with reading
Output OL to display
20
02
20
02
DO
Walt for next measurement cycle
Return
Set pointer to value of first strobe
CO
BO
Get second digit and put It In the proper register
204A
MVI B, OBOH
06
204C
204F
2050
CALL DIGIT
ADD E
MOV E, A
CD AO 20
83
5F
Set pointer to value of third strobe
2051
MVI B, OAOH
06
2053
2056
2057
2058
2059
205A
CALL DIGIT
RLC
RLC
RLC
RLC
MOVC, A
CD AO 20
07
07
07
07
4F
Get fourth digit and put It In the proper
register
205B
MVI B, 90H
06
Set pointer to value of fifth strobe
2050
2060
2061
CALL DIGIT
ADDC
PUSH PSW
CD AO 20
81
F5
Get third digit and put It with the second digit
Set pointer to value of fourth strobe
AO
90
Display the upper three digits
2062
CALL UPDAD
CD 63
2065
POP PSW
F1
Restore the lowest two digits
2066
CALL UPDDT
CD 6E 03
Display the lowest two digits
13-118
03
Get fifth digit and put It with the fourth digit
Save the lowest two digits
H
AN83-14
Siliconix
incorporated
TABLE 1 (Cont'd)
COMMENTS
ADDRESS
MNEMONIC
OP-CODE
2069
206B
206D
206F
2072
2074
2077
IN 01
ANI02H
SUI02H
JNZ 207AH
MVI A, OFFH
STA 1800H
JMP 202EH
DB
E6
D6
C2
3E
32
C3
MVI A, OFBH
STA 1800H
JMP 202EH
data
data
data
data
data
data
3E FB
32 00 18
C3 2E 20
00
11
15
15
15
15
Put a minus sign In the polarity position
IN 00
ANIOFOH
SUB B
JNZ 20AOH
IN 00
ANIOFH
RET
DB
E6
90
C2
DB
E6
C9
Read port
Mask lower byte of data
Compare byte to pointer, If not equal then walt
207A
207C
207F
2082
2083
2084
2085
2086
2087
01
02
02
7A 20
FF
00 18
2E 20
Check polarity bit for positive or negative sign
Blank the polarity position
Return
Return
Subroutine DIGIT
20AO
20A2
20A4
20AS
20A8
20AA
20AC
00
FO
AO 20
00
OF
Read port
Mask upper byte of data
Return
TABLE 2
ADDRESS
MNEMONIC
OP-CODE
COMMENTS
2080
LXI SP, 20C2H
31
C2 20
Load stack
2083
2085
2087
2089
208B
208D
MVI A, OFFH
OUT OA
OUT 08
MVI A, OOH
OUT 02
OUT 03
3E
D3
D3
3E
D3
D3
FF
OA
08
00
02
03
Set up data direction register for 1/0 ports
208F
2091
2093
MVI A, ODFH
MVIB,ODBH
OUT 08
3E DF
06 DB
DB 08
Hold present AID Converter
2095
RRC
OF
Set pointer to next AID Converter
2096
PUSH PSW
F5
2097
209A
LXI D, A700H
CALL DELAY
11 00
CD F1
2090
209E
MOV A, B
OUT 08
78
D3 08
Enable Buffers
20AO
20A1
RRC
MOV B, A
OF
47
Set Enable to next AI D Converter
20A2
PUSH B
C5
20A3
CALL READ
CD 00
20AS
POP B
C1
Restore Enable Data
20A7
20A8
20A9
RLC
RRC
JC 20BOH
07
OF
DA BO
Check If ali AID Converters have been read
20AC
POP PSW
F1
20AD
20BO
20B1
JMP 208FH
POP PSW
JMP 2093H
C3 8F
F1
C3 93
Save pointer data
A7
05
Delay for 1/3 second
Save Enable Data
20
Read Data from AID Converter
III
20
Restore Pointer Data
20
20
Return
Clear the Stack
Start Over
13-119
H
AN83·14
Siliconix
incorporated
TABLE 2 (Cont'd)
MNEMONIC
OP-CODE
COMMENTS
IN 01
DB 01
Check for OVERRANGE. If not, continue
with reading
2002
2003
RRC
JNC 201AH
0
02 1A 20
2006
2008
200A
2000
2010
2012
2014
2017
MVI A, 01H
MVI B, OOH
LXI H, 2062H
CALLOUTPT
MVI A, OOH
MVI B, OOH
LXI H, 2064H
CALL OUTPT
3E
06
21
CD
3E
06
21
CD
01
00
62
B7
00
00
64
B7
DO
ADDRESS
Subroutine READ
2000
201A
MVI B, ODOH
06
201C
201F
CALL DIGIT
MOV D, A
CD 70
57
2020
MVI B, OCOH
06
2022
2025
2026
2027
2028
2029
CALL DIGIT
RLC
RLC
RLC
RLC
MOV E, A
CD 70
07
07
07
07
5F
Output OL to display
20
02
20
02
Set pointer to value of first strobe
20
Set pointer to value of second strobe
CO
202A
MVI B, OBOH
06
202C
202F
2030
CALL DIGIT
ADD E
MOV E, A
CD 70
83
5F
20
Get second digit and put It In the proper
register
20
Get third digit and put It with second digit
20
Get fourth digit and put It In the proper
register
20
Get fifth digit and put It with the fourth digit
Set pointer to value to third strobe
BO
2031
MVI B, OAOH
06
2033
CALL DIGIT
CD 70
2036
2037
2038
2039
203A
RLC
RLC
RLC
RLC
MOV C, A
07
07
07
07
4F
Set pointer to value of fourth strobe
AO
203B
MVI B, 90H
06
203D
2040
CALL DIGIT
ADDC
CD 70
81
Get first digit and put It In the proper register
90
Set pointer to value of fifth strobe
2041
PUSH PSW
F5
2042
CALL UPDAD
CD 63
2045
POP PSW
F1
Restore the lowest two digits
2046
CALL UPDDT
CD 6E 03
Display the lowest two digits
2049
204B
204D
204F
IN 01
ANI02H
SUI02H
JNZ 205AH
DB
E6
D6
C2
Check polarity bit for positive or negative
sign
2052
2054
MVI A, OFFH
STA 1800H
3E FF
32 00 18
Blank the polarity position
7
Save the lowest two digits
03
01
02
02
5A 20
Display the upper three digits
205
RET
C9
Return
2058
205C
MVI A, OFBH
S:rA 1800H
3E FB
32 00 18
Put a minus sign In the polarity posltllon
205F
2062
2063
2064
2065
2066
2067
RET
data
data
data
data
data
data
C9
00
11
15
15
15
15
Return
13-120
AN83-14
..... Siliconix
incorporated
~
TABLE 2 (Cont'd)
ADDRESS
MNEMONIC
Subroutine DIGIT
IN 00
2070
OP-CODE
COMMENTS
DB 00
Read port
Mask lower byte of data
Compare byte to pointer, If not equal then
walt
2072
ANIOFOH
E6 FO
2074
SUB B
90
2075
JNZ 2070H
C2 70 20
2076
IN 00
DB 00
Read port
207A
ANIOFH
E6 OF
Mask upper byte of data
207C
RET
C9
Return
CONCLUSION
The Siliconix Si7135 is an inexpensive, simple integrated circuit that can solve the problems associated
with a design that seems far too complex for the job
it is intended to do. Note that the Intel 8085 is not the
only microprocessor one could interface to the
Si7135. This scheme is easily adaptable to other mi-
croprocessor architectures. However it is also important to know that the comparatively slow conversion
time makes multiplexing of several Si7135's to one
microprocessor more practical than multiplexing the
inputs to a single Si7135. With multiplexed converters, a fast, easy method of data acquisition can be
achieved for a reasonable price.
13-121
..... Siliconix
incorporated
AN83·13
~
Si8601 DATA ACQUISITION
SYSTEM INTERFACES FOR 110
OR MEMORY MAPPED OPERATION
By Doyle L. Slack
Revised January. 1988
interfacing hardware and associated software for
both schemes are presented here.
INTRODUCTION
The Siliconix Si8601 is an 8 channel. 8-bit silicon gate
CMOS Data Acquisition System containing an 8 channel multiplexer. an 8-bit AID converter. and an output
latching circuit. The AID converter uses a binaryweighted capacitor successive approximation technique allowing fast conversion time and a true sample and hold function with low power consumption.
The 8 channel multiplexer offers great flexibility by
providing multi-channel data collection with only one
AID converter. However. the outstanding advantage
of this device is its ease of interfacing to microprocessor systems. Both the address inputs and data
outputs are latchable which minimizes the time that
the microprocessor and the data acquisition system
must dedicate to data transfer. The outputs are tristate. allowing direct connection to the system data
bus for memory mapping. Since the Si8601 is easily
wired for either 110 or memory mapped operation.
~
REF+
The Si8601 can be easily interfaced to the Intel 8085.
an inexpensive 8-bit microprocessor with many available peripheral devices. The 8085 was chosen for
interfacing because it makes a good example for wiring to anyone of the several other similar microprocessor architectures.
The Intel 8155 RAM-liD and 8755 EPROM-liD chips
provide both memory and 110 ports for the 8085 system and can be used to interface the Si8601 and the
8085. If the AID converter output of the Si8601 is to
be monitored at an 110 port. it can be left running
constantly. The port can be sampled whenever a
reading is desired. On the other hand. the memory
mapped data acquisition system costs less to build
because there is no need for an 110 port.
"I
A/DCoNVERTER -
I REFI
2N - WEIGHTED
CAPACITORS
SWITCH
MATRIX
8
ANALOG
INPUTS
ADDRESS A
3-STATE
OUTPUT
LATCH
ANALOG
MULTIPLEXER
_r-------.
CONTROL
AND
TIMING
8
OUTPUTS
END OF
CONVERSION
ADDRESS B
ADDRESS C -1..-_ _..,..._........
ADDRESS LOAD CONTROL _ _ _ _...3
CLOCK _ _ _ _ _ _ _ _ _ _......J
START CONVERSION - - - - - - - - - - - - - - '
OUTPUTCONTROL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
Figure 1. Block Diagram of the 518601 Data Conversion System
13-122
AN83·13
.... Siliconix
incorporated
~
CIRCUIT DESCRIPTION
Figure 1 shows a block diagram of the Si8601. Address Inputs Ao. Al. and A2 allow selection of the 8
channels of the multiplexer. Since the multiplexer
works asynchronously with respect to the AID converter section. care must be exercised not to change
input channels during the first 9 clock cycles (sampling phase) after the SC (start conversion) pulse.
Each channel has a single-ended input which has an
analog range from -REF to +REF. giving a conversion
range from 3 to 6.5 V. Note that only a 5 V Vee and
+REF will allow TTL compatibility. The -REF input allows separation of analog and digital grounds which
helps to keep noise spikes that might be present on
the digital system ground from affecting the accuracy
of the analog input to the Si8601. The eight tri-state
data outputs provide the data to the microprocesosr.
A square wave signal is needed for the CLOCK input.
Maximum clock frequencies of 1.4 MHz are possible.
Clock duty cycle can be anywhere from 20 to 80%.
The OUTPUT CONTROL (OC). START CONVERSION
(START). and ADDRESS LOAD CONTROL (ALC) provide the means for the microprocessor to control the
Si8601 . The END OF CONVERSION (EOC) output
\+111--1 1
2
3
4
goes high when the conversion is finished and when
the output is available at the data pins. Figure 2(a}
shows the pin diagram of the Si8601 • and Figure 2 (b)
gives the relationship of the input and output signals
of the data acquisition system.
Dual-ln-L1ne Package
GND
SC
07
05
03
01
OE
EOC
REF-
REF +
AlC
IN1
AO
A1
A2
IN 8
IN7
Figure 2 (a). Pin Diagram of the SI8601 8-channel
Data Acquisition System
5
6
8
7
ALC
ADDRESS
26
$IUL
CLOCK
START
25
9
SEE DETAIL A
--~~--------------------------------~H~-----SEE DETAIL A
Hl----
---.---------------------------------1:11
SEE DETAIL A
--~~----------------------------------{~-------
ANALOG
v---if
---v
IN-----A~___________________________________~/~---------
- . SEE DETAIL A
~TCHOUTPUTS
rI
$r------J
!
EOC
OUTPUT CONTROL
$;
I
________________________________________________i!rS-E-E-D-ET-A-IL-B,1_
DETAIL A
Sf
START
/
\'----
--------'
\'------
EOC
-II
AlC ________
ADDRESS
====x~
.
\'----
________~X~____________________________
,----If---.
~
DETAIL B
OUTPUT CONTROL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - /
~TCHED
OUTPUTS
------------------------------~c:~
r--/
HI Z STATE
Figure 2(b). Timing Diagram of the SI8601 Data Acquisition System
13-123
...... Siliconix
incorporated
AN83·13
~
+5 V
4.9 k.O.
26
3
25
4
24
5
23
6
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO
17
PA6
PA5
PA4
818601
+5
18
19
PORT 1
TO 8155
110 PORT
PORT 0
PA7
5
Figure 3. Schematic Diagram of the 110 Version of the 818601 Interface
1/0 OPERATION
SOFTWARE
In the I/O mode, the Si8601 is in a free-running loop;
the data outputs of the AID converter are always enabled. The data outputs and address inputs of the
data acquisition system are connected to the I/O
port, and the START input is tied to the EOe line so
that the system is constantly measuring the selected
input channel (see Figure 3). The data handling is
then accomplished by a machine language program
that reads in the converted data and processes it in
whatever way desired by the user. The data transfer
is verified in the program by checking the EOe pin for
data stability before accepting the next input.
The software shown here was written for use with the
Intel SDK-85 development system monitor with the 8
channels of the Si8601 memory mapped at
8000H-8007H and I/O mapped through ports 0 and 1.
The UPDDT and UPDAD routines are used to display
the contents of the A, D, and E registers. Both programs are written in subroutine form so they can be
utilized by more than one calling program. If data
storage or comparison is desired, minor changes or
additions to the software shown here will be necessary. The I/O oriented programs are shown in Tables
1 (a) and 1 (b). Table 1 (a) shows a simple routine
that reads in and displays a single channel selected
by the data stored at location 20AOH. The program
in Table 1 (b) reads each of the channels and displays them for approximately 1/3 second each.
Since the I/O system is constantly running, the EOe
pin is monitored by the program, and data is only
taken if EOe is high (data is valid).
MEMORY MAPPED OPERATION
When operating in the memory mapped mode, the
data outputs and address inputs are tied directly to
their corresponding busses. The oe, START, and
ALe lines are used to tri-state the Si8601 when appropriate. Figure 4 shows the schematic diagram of
the memory mapped data acquisition system. Note
that A15 Is the only address decoding line used for
this example. To eliminate memory map redundancy, a more sophisticated address decoding circuit would be needed. The NOR gates of the 4001
combine the address decoding, READ, and WRITE
signals to control the data acquisition system. The
EOe pin is tied to RST 6.5 of the 8085 to notify the
microprocessor when the conversion has been completed and when the data outputs are ready to be
read.
13-124
The memory mapped system must be started when
a reading is desired. This is done in Tables 2(a) and
2(b) by writing to the desired memory location, which
starts the conversion. The EOe line signals an interrupt for the microprocessor, making it jump to the
READ subroutine and then returning back to the main
program. Table 2(a) uses the Hand L registers to
point to the desired channel and then displays the
reading from that channel. Table 2(b) reads all 8
channels and displays each one for approximately
1/3 second.
AN83·13
IrF Siliconix
~
incorporated
+5 V
1-------107
1-------106
1 - - - - - - - 1 05
1-------104
1 - - - - - - - 1 03
1-------102
1-------101
1 - - - - - - - 1 Do
4.9 k.o.
TO 8085
1-_ _ _ _ _-1 A2 BUS SYSTEM
+5 V
1 - - - - - - - 1 A1
t - - - - - - ; AO
555
J..5.l~-----I
RST 6.5
READ
A15
~----I
WRITE
3/44001
Figure 4. Schematic Diagram of the Memory Mapped Version of the SI8601 Interface
Note the asterisks in tables 1 (a) and 2 (a) . These
mark the locations where the desired input channel is
selected. Figure 5 gives the locations of the channels in both the 110 and memory mapped configurations.
CONCLUSION
The Si8601 Data Acquisition System features built-in
INPUT
CHANNEL
0
1
2
3
4
5
6
7
110 LOCATION
00
10
20
30
40
50
60
70
multi-channel capability with easy interface to most
microprocessor systems. The 8085 Is just one example of how this system can be constructed using
only an external clock circuit and the Si8601. It has a
25 fJ.s conversion time and extremely low power consumption which makes it ideal for battery powered
monitoring of multiple parameters or conditions in the
field.
MEMORY MAPPED
LOCATION
8000H
8001H
8002H
8003H
8004H
8005H
8006H
8007H
FIGURE 5. Channel locations for the SI8601 In both I/O and memory mapped configurations
13-125
AN83-13
..... Siliconix
incorporated
~
TABLE 1 (a)
Program for reading one channel of the Si8601 In the 1/0 configuration
MNEMONIC
OP-CODE
COMMENTS
LXI SP, 20C2H
LXI H, 20AOH
MVI M, DOH
MVI A, DOH
OUT 03
MVI A, 7FH
OUT 02
CALL READ
JMP 2003H
31
21
36
3E
D3
3E
03
CD
C3
20
20
Load stack pointer
Reserve location for channel selector
Load channel selector with desired Input
Set up data direction registers for 110 ports
20
20
Read the 110 port
Start over
2016
2017
2019
MOVA, M
OUT 00
IN 00
7E
D3 00
DB 00
201B
201C
201F
2021
2024
RLC
JNC 2019H
IN 01
CALL UPDDT
RET
07
D2 19 20
DB 01
CD 6E 03
C9
ADDRESS
Calling Program
2000
2003
'2006
2008
200A
200C
200E
2010
2013
C2
AD
00
00
03
7F
02
16
03
Subroutine READ
Start conversion
Check to see If conversion Is finished, If done,
read In data
Read In data
Display data
Return
TABLE 1 (b)
Program for reading all 8-channels of the SI8601 In the 1/0 configuration
ADDRESS
MNEMONIC
OP-CODE
COMMENTS
LXI SP, 20C2H
LXI H, 20AOH
MVI M, DOH
MVI A, DOH
OUT 03
MVI A, 7FH
OUT 02
CALL READ
JMP 2003H
31
21
36
3E
D3
3E
D3
CD
C3
Load stack pointer
Reserve location for channel selector
Load channel selector with desired Input
Set up data direction registers for 1/0 ports
2010
2011
2012
MOVA, M
PUSH PSW
OUT 00
7E
F5
D3 00
2014
2016
2017
201A
201C
201F
2020
IN 00
RLC
JNC 2014H
IN 01
CALL UPDDT
POP PSW
SUI70H
DB
07
D2
DB
CD
Fl
D6
2022
2025
2026
2029
JZ 2029H
INRM
JMP 2010H
RET
CA 29
34
C3 10
C9
Calling Program
2000
2003
2006
2008
200A
200C
200E
2010
2013
C2 20
AD 20
00
00
03
7F
02
16 20
03 20
Read the 110 port
Start over
Subroutine READ
13-126
Start conversion
Check to see If conversion Is finished, If done,
read-In data
00
14 20
01
6E 03
70
Read-In data
Display data
Restore channel selector
Check to see If all channels have been read,
If not, keep going
20
20
Increment channel selector
Read next channel
Return
.-r Siliconix
~
AN83-13
incorporated
TABLE 2 (a)
Program for reading one channel of the Si8601 In the memory mapped configuration
ADDRESS
MNEMONIC
OP-CODE
COMMENTS
Subroutine BGNCNVSN
Start conversion
2000
MOV M, A
77
2001
MVI A, OCH
3E
2003
SIM
30
2004
FB
2005
EI
EXID, FFFFH
CALL DELAY
11 FF FF
CD F1 05
Delay while conversion takes place
2008
200B
RET
C9
Return
2010
MOVA, M
7E
2011
CALL UPDDT
CD 6E
2014
RET
C9
Enable the Interrupt system
OC
Subroutine READ
Read-In results of the conversion
03
Display the results
Return
Calling Program
Load stack pointer
LXI SP, 20C2H
31
C2 20
*2023
2026
LXI H, 8000H
21
80
Load channel selector
20
Start conversion
2029
LXI D, FFFFH
11
202C
CALL DELAY
CD F1
05
1/3 second
202F
JMP 2023H
C3 23
20
Repeat
2020
CALL BGNCNVSN
00
CD 00
FF FF
Delay between readings for approximately
TABLE 2 (b)
Program for reading all 8 channels of the Si8601 in the memory mapped configuration
ADDRESS
MNEMONIC
Subroutine BGNCNVSN
OP-CODE
COMMENTS
Start conversion
2000
MOV M, A
77
2001
MVI A, OCH
3E
2003
SIM
30
2004
EI
FB
2005
LXI D, FFFFH
11
2008
CALL DELAY
CD F1
200B
RET
C9
MOVA, M
CALL UPDDT
RET
7E
CD 6E
C9
LXI SP, 20C2H
LXI H, 8000H
PUSH H
CALL BGNCNVSN
POP H
MOV A, L
SUI 07H
JZ 2023H
INR L
JMP 2026H
31
21
E5
CD
E1
7D
D6
CA
2C
C3
OC
Enable the Interrupt system
FF FF
Delay while conversion takes place
05
Return
Subroutine READ
2010
2011
2014
Calling Program
2020
2023
2026
2027
202A
202B
202C
202E
2031
2032
03
C2 20
00 80
00
20
07
23
20
26
20
Read-In results of the conversion
Display the results
Return
Load Stack pointer
Load channel selector
Save channel selector
Start conversion
Restore channel selector
Check to see If all channels have
been read, If they have, start over
Increment channel selector
Go to next channel for a reading
• =Location where desired Input channel Is selected.
13-127
..... Siliconix
incorporated
AN83·7
~
A HIGH QUALITY AUDIO CROSSPOINT SWITCH
By Bob Zavrel
Revised January 1988
8.
9.
10.
11.
INTRODUCTION
Recent advances in analog switch integrated circuits
have made superior audio switch specifications possible. A crosspoint switch for the most demanding
audio applications is described here. Although this
switch may be used in recording studio and radio
broadcast mixers where little compromise is acceptable, the low cost and small size makes this switch
ideal for a much more diverse range of applications.
Such applications can include audio crosspoint
switches found in video systems, audio synthesizers,
high quality multiplexers, and home entertainment
systems.
The size of a complex audio switching array can be
greatly reduced by using IC analog switches. The
prototype array is an 8x2 stereo crosspoint switch
mounted on a 4x7 inch board. Other switch configurations may be fabricated with little effect on the
switch characteristics. This single board can replace
a score of rotary switches and the bundles of audio
cable often found in audio mixers. Furthermore,
ground loop problems are reduced by eliminating the
cable bundles.
A high quality audio frequency switch should have the
following features:
1.
2.
3.
4.
5.
6.
7.
Siliconix 805002s were chosen because of low ON
resistance, low switch capacitance, and very fast
switching times. The LF347 quad op amp was chosen
for its excellent audio characteristics in a quad package. Two LF347s are used in this switch providing a
summing and output amplifier for each of four channels. Since the 805002s switch into virtual grounds,
they are held "normally open" by applying
Reasonable cost
Unity or variable gain
Very low harmonic distortion « 0.01%)
Flat response (DC to > 1 MHz)
Low crosstalk
High OFF Isolation
Excellent phase linearity
SUMMING
NODE FROM
6 OTHER LEFT swrrCHES
r----'
LEFT INPUT BUS
RS
75kA
RL
CHANNEL 1
± 15 v
41 S
61G
RIGHT INPUT BUS
011
SUMMING AMP
RA
I I
UIl..-'
0--{ j _
High speed switching
Freedom from switch "popping"
Small size
Use of DC coupling only
i
600.n
RD
RS
75kA
CHANNEL A
LEFT OUTPUT
RO
6oo.n
S05002
LEFT INPUT_B-U,..S----'V\R;;;.S-"'t"--'
RL
CHANNEL 2
116
•. n
75 ....
141G -'I
±15 v 0--{ 1Rs
VII>
75kA
I t---4-I
ll1G'i
I
121s •
0 9
I
I
I
I
1. _ _ _ _
I
I
SUMMING NODE FROM
_
6 OTHER RIGHT swrrCHES
SUBSTRATEO V-
J2
Figure 1
13-128
6oo.n
.~~~RVD~~ ~~~~NgbtPUT
RO
6oo.n
AN83-7
.... 8i1iconix
incorporated
~
, -15 V the switch gates. To turn them on it is sufficient to apply a V+ level to the gates. For any switch
configuration, the appropriate switch(es) are closed
by biasing the appropriate gate(s) to the positive
voltage supply. In this circuit pairs of switches are
controlled together to affect the left and right channels of a stereo input simultaneously. This is accomplished simply by tying the applicable switch gates
together and using a common bias.
Figure 1 shows how a single 8D5002 is configured as
a 2x1 stereo switch. Figure 2 shows how the circuit
can be expanded into a switch matrix. Eight 8D5002s
are required to construct the 8x2 stereo matrix array.
One RL is required for each channel input for termination while four R S 's are employed to feed the signal from the swiitches to the amplifiers. Input buses
are consequently formed in front of these resistors.
75 kll.
RS
GOOn.
CHl
R
O---~--------4r-+--O-~---+----,
CHA
75kll.
8
GOOn.
Lo---~----~--r-+--a'
STEREO
INPUTS
R
R
OUTPUT
0-..,....--...,...+-+-1-0" ....--1---+
o-~R-L
I
I
I
I
I
2
STEREO
OUTPUTS
...--+--+--+--+--a':
i I
75 kll.
RS
CHB
OUTPUT
RS
GOOn.
>-~"""'V\r--o() R
III
Figure 2. A High Quality 8x2 Stereo Crosspoint Switch
13-129
AN83·7
.... Siliconix
incorporated
~
The SD5002 drains are connected to these input
buses. A larger array will cause reduced system performance due to longer lead lengths and increased
circuit capacitance. Nevertheless, large matrices can
be configured with little performance compromise
because of the low initial switch capacitance. RL'S
value should reflect the value of the source impedance. Deletion of RL will seriously degrade crosstalk
and off isolation performance while lower values of RL
will improve these specifications. Rc may be adjusted
for a wide range of system gain while a value of
about 150 kn will set the circuit to unity gain. Rosets
the value of the output impedance and if the switch is
to feed a high impedance load, Ro should be included to maintain system performance.
Electrolytic and mica capacitors are used on the cir-
cuit board for bypassing the two power supply voltages. Supply voltage bypassing will reduce both high
and low frequency noise and help stabilize the system. The entire circuit should be well shielded particularly if it will be exposed to strong rf or power line
fields. Conductors carrying high current should be
kept away from the circuit. Double sided PC board
should be used creating a ground plane on the component side as an additional precautionary measure.
Table 1 shows the switch performance of the 8x2
crosspoint configuration. RL was set to 10 k n, reflecting the high impedance of the test oscillator's
output. Regulated power supply voltages of plus and
minus 9 to 15 volts may be used. The Signal voltages
should be kept under about 3.5 Vp_p to maintain
switch performance.
TABLE 1
Frequency
(Hz)
50
100
200
500
1
2
5
10
20
50
100
Signal voltages: 3 Vp-p
Supply voltages: ±12 volts
13-130
Crosstalk
(dB)
-74
-74
-74
-74
-74
-73
-70
-67
-62
-55
-50
"Off" Isolation
(dB)
THO
-75
-75
-75
-75
-75
-74
-71
-68
-62
-55
-49
0.006
0.005
0.004
0.003
0.003
0.003
0.003
0.004
0.006
0.020
0.045
trr
~
AN83-6
Siliconix
incorporated
A SYSTEM SOLUTION TO HP-IL EQUIPMENT
INTERFACE
Robert J. Zavrel Jr.
December 1983
INTRODUCTION
Siliconix manufactures several high performance
components which lend themselves nicely to portable equipment. For a 4-1/2 digit HP-IL compatible
DVM, Siliconix now offers a "systems solution" to the
designer of such a device. With the exception of a
few standard 4000 series CMOS ICs, all the special
integrated circuits are offered by Siliconix. The DVM
is based on the Si7135, a high-quality, single chip,
dual-slope integrating AID converter. The prototype
circuit used to interface the Si7135 to the HP-IL contained 23 standard 4000 series CMOS ICs. This hardware interface solution may be simplified to a custom
28 pin DIP Interface IC "gate array". This interface
allows direct connection to the Hewlett-Packard HP-IL
standard "GPIO". Additionally, Siliconix offers three
devices which complete the specialized DVM IC requirement. The DF412 provides a local LCD driver
which allows the DVM to operate as a stand-alone
device. Two SD5002 analog switches are arranged to
provide an analog input multiplexer which boasts over
100 dB channel-to-channel isolation. Finally, an
Si7661 voltage converter eliminates the need for a
negative power supply, thus a single 5 V supply is all
that is necessary.
The HP-IL "interface loop" is a data communication
system designed as a portable, low cost, and high
quality instrument controller. It is quite suitable for
lab environments where easy programming is desirable. The powerful and popular HP-41 handheld computer or the HP-75C portable computer can be used
as controllers for up to 31 "HP-IL devices" in the
loop. Hewlett-Packard manufactures a wide variety of
HP-IL compatible devices including a printer, timer,
video interface, and DVM (Reference 1). For convenience the HP-41 will be used as the controller in this
paper. A detailed description of HP-IL is beyond the
scope of the paper, but a basic understanding of HPIL is necessary to render this interface technique
meaningful.
HP-IL INTERFACE CIRCUIT/INTERFACE IC
HANDSHAKING
Care must be taken to avoid confusion of terms. The
HP-IL interface circuit contains two basic ICs. It is this
circuit which takes the serial IL pulses and routes the
data to the two-way data bus, the appropriate handshake and other control pins. Taken together this assemblage of data and control pins is called "GPIO" or
"general purpose input/output". Hewlett-Packard offers four approaches to realizing the HP-IL interface
circuit. Details of these approaches are available
from Hewlett-Packard. The "Interface IC" interfaces
the Si7135 digital outputs to the GPIO bus. (Figure 1)
Contained within the HP-IL interface circuit are the 28
pin DIP ILB3-0003 from Hewlett-Packard and the Mostek 1820-281040 pin single chip microcomputer. The
ILB3-0003 contains multiple registers and extensive
circuitry for the HP-IL interface. The microcomputer
acts as an HP-IL device controller and provides the
GPIO data and control pins, later to be discussed in
detail. This Mostek microcomputer is made with a
special mask for HP-IL and must be purchased from
Hewlett-Packard. These ICs are arranged around two
8-bit data busses labeled as DA and DB. In the DVM
and multiplexer circuits, the DB bus is used only for
data transfers between the 1820-2810 and the
ILB3-0003. The DA is used as the bi-directional bus
between the 1820-2810 and the DVM. Because ASCII
characters are seven-bit words, the eighth bit of the
eight-bit bus should be held low when ASCII is being
transmitted. The circuits described here link the GPIO
standard interface to the specialized data and control
pins of the Si7135 4-1/2 digit DVM chip and a multiplexer. The multiplexer circuit is also relatively simple, needing only a few standard CMOS ICs.
ASCII characters are used for all data transfer in HPIL. Data transfer can flow to an external device such
as a printer or from an external device such as a
DVM. Two device modes are consequently defined
13-131
III
AN83-6
~
~
Siliconix
incorporated
DVM BOARD
ANALOG
INPUTS -+---7
'---.--.r
+5 V 0---+---1
I
I
I
I
I
L _______ .-_
HP-IL
INTERFACE
+5 V
HP 82165A
HP82166B or
Equivalent Circuit
HP 41
Figure 1. HP-IL Multiplexer/DVM System
as listener and talker. Data transfer between an HP-IL
station and its corresponding peripheral device can
utilize six "handshake" and additional command pins
located on GPIO. Three handshake pins are used for
the listener mode. and three are used for the talker
mode. The two handshake modes are very similar.
When listener is ready to accept data. a "Ready" pin
is taken,low (logic true). The talker may respond at
this point if it has data to send with an ASCII character on the data bus and a low "Data Valid" pin. Finally. if the listener regeives the data. it sets the
"Data Confirmed" pin low. completing the handshake sequence.
Several levels of handshaking are possible using the
three handshake pins in different combinations. For
the Siliconix DVM. the talker handshaking is very simple. "bata confirmed" is not used. and the "Ready"
13-132
and "Data Valid" pins are hardwired together.
"Ready" and "Data Valid" correspond to the RDVO
and DAVI pins for the talker handshake. In addition.
the GETO pin is used to initialize a reading which is
fed to the controller. The GETO pin is set low by a
"TRIGGER" command in the computer software program. The "IND" command is used after the "TRIGGER" command to actually read in decimal data from
the HP-IL device. The low GETO pin sets a latch in
the interface IC in turn allowing a counter to sequence seven ASCII characters to the HP-IL. The
counter is sequenced as the RDVO pin is set low if
three conditions are met. Sequencing is prevented
during the GETO pulse by the first of three conditional "AND" gates controlling the counter. The second gate is activated by the "TRIGGER" latch. In addition. an optional third gate is provided by the "Interface IC' s" .ENABLE pin (to be discussed later).
AN83-6
fI'7" Siliconix
.,1;;11 incorporated
(+V)
Table 1. ATD Program
01
14
02
4069
03
04
05
06
07
LBL DVM1
LBL 01
TRIGGER
IND
VIEW X
GTO 01
END
1N 4148 or Similar
INTERFACE IC
ENABLE
STROBE
from SI7135
Figure 2. Optional Condition Circuit
v-
UNDERRANGE
REFERENCE
OVERRANGE
ANALOG COMMON
3
STROBE
RIH
DIGITAL GND
POL
REF. CAP.-
7
517135
CLOCK IN
BUSY
(LSD) 01
IN HI
02
v+
03
os
04
(MSD)
(LSB) B1
(MSB) B8
B4
B2
Figure 3. 517135 Pin Out
The seven ASCII characters provide for a polarity
character. five digits. and a hardwired ASCII "LF"
command. This character is recognized by the controller as an "End of Data" statement. The counter is
allowed to sequence one more step after the "LF"
command which resets itself and the "TRIGGER"
latch. The read cycle is now complete. and the interface IC is ready to send another reading. A very simple seven line program in the HP-41 will initialize the
DVM. read in the data. display the data. and loop
back to take another reading. This ATD program is
shown in Table 1.
Figure 1 shows a functional block diagram of the system that contains several levels of asynchronism.
The HP-41 is asynchronous to HP-IL; HP-IL is asynchronous to the interface IC: and the "Interface IC"
is asynchronous to the Si7135. The "Interface IC"
must account for random events at all three levels
and convert the polarity and strobed BCD outputs to
the proper ASCII characters. A subtle but desirable
trait of the interface is that it should not allow a reading by the HP-IL while the Si7135 is latching in new
data. Additionally. the interface should not allow the
latching of data while the HP-IL is reading. Either condition would result in an invalid entry. The ENABLE pin
when used with the circuit in Figure 2 will prevent the
counter from sequencing the ASCII characters. The
result will be a repetition of a single character which
will fill the HP-41 X Register. In turn. this may be
checked with HP-41 software. and the data will be
deleted preventing an HP-IL read during a latch
change. Alternatively. this gate may be held high if
an occasional invalid reading is permissible. With this
configuration. about 3% of the readings will be invalid. "Invalid" is used here to describe the condition of
reading in the five digit number from two separate
Si7135 writings. For example. if the Si7135 latches in
new data to the interface IC while the HP-IL is reading. perhaps the first two digits may be from the old
voltage reading while three would be from new data.
The other invalid condition is prevented by stopping
the Si7135 with the "TRIGGER" activated latch. This
is accomplished by setting the RUN/HOLD pin low
and thus stopping the Si7135 cycle until the reading
is complete.
Si7135/"INTERFACE IC" HANDSHAKING
Data is latched into the "Interface IC" from the
Si7135 by means of the four BCD data lines (Figure
4). They are routed to the proper character latch by
the digit strobe pins. The polarity and most significant
13-133
~
II.1:II
..,. Siliconix
incorporated
AN83·6
~
"LF" command, are hardwired. These latches and
hard wires feed tri-state buffers which are sequentially activated by the counter and consequently present their data to the ASCII output bus (DA) on GPIO.
digit are simultaneously latched with Digit Strobe
One. The STRoBE pin, which should not be confused
with the five digit strobe pins, goes low five times
after each voltage measurement In tandem with the
sequencing five digit strobes. Thus, the latching of
SI7135 data into the interface Ie occurs only once
during each measurement cycle as a condition of the
Digit Strobe pins and the STROBE pin. There is one
latch for each variable bit of the six variable ASCII
characters. Non-variable bits, Including the entire
--
....
~~
VI
V
0
DATA
(+v)
_
~Q
Autoranging or multiple input select functions can be
Implemented using similar straightforward programming techniques. The under-range and over-range
pins of the Si7135 are connected to the most significant digit buffer.
Enable
-
~
DType
Flip/
i
L J
Q~
RESET
Q8
Q2 Q3
}-
CLOCK
DECADE COUNTER
Q1
--
Optional Condition
Q4
Q5
CLOCK EN
Q6
Q7 QO
T
II~~TE
BUFFER
...
I J.-
f--
2 ASCII M. S. BITS
a-BIT DATA
BUS(DA)
,
HEX
TRI-sTATE
BUFFERS
QUAD "0"
LATCHES
II
lEN
6 ASCII L.S. BITS
I
EN
EN
I
I
EN
EN
I
II
I
I
EN
~
EN
EN
EN
I
I
BCD DATA BUS
(1
(
(1
,
(
~
4
01
STROBE 02
D3
SI7135
Figure 4. Simplified Circuit of Interface IC
D4
1
HARDWIRED
"LF"
EN
ENI
I
I
I
RUN/HoLD
I
I
POLARITY
13-134
lrl
I
EN
EN
05
..-F' Siliconix
~
incorporated
Valid readings on the Si7135 range from -19999 to
+19999. The under-range and over-range pins on the
Si7135 are tied to the second and third bits of the
most significant digit latch. Thus, during underrange, a numerical value slightly greater than or
equal to 20,000 will be read, and 40,000 will be read
during an over-range condition. These values along
with the full register condition of the invalid reading
discussed earlier can be checked by software. In the
case of over or under-range, a subroutine can be
called selecting an appropriately higher or lower
scale. The scale called can also indicate the proper
coefficient for correct numerical display and decimal
placement. Therefore, meter calibration may take
place in software if the sensor cannot be adjusted.
Under and over-range as well as other Si7135 functions are optionally used by the designer. The "Interface IC" was designed to allow customizing the interface for a given set of functions and applications.
The "Interface IC" is also useful with other A/O converters including the Siliconix "LO" family. Additionally, the great flexibility afforded by the software allows special readings such as dBm, dB gain, and radian measure, etc. Indeed, applications of this system seem infinite (bfd).
HP-ILIMULTIPLEXER INTERFACE
In the case of input selection, autoranging and function select, etc., the circuit in Figure 5 may be used.
Here, eight inputs are used to feed the Si7135. When
the multiplexer is receiving instructions, it actually
becomes a listener. A relatively simple circuit is required for the interface between the S05002s and the
HP-IL; furthermore, this S05002 circuit may be used
as a stand-alone circuit for a wide range of analog
switching functions. S05002s can be configured into
superior video, audio, or RF switching circuits featuring excellent cross-talk and low-distortion performance (Ref. 2 & 3). Additionally, Siliconix offers a wide
range of analog switches and multiplexers to suit any
application. Power control is possible with up to 650
volt power FETs and simple standard control circuits.
Thus, Siliconix can be a single supplier of specialized
components from the HP-IL "Interface IC" to HP-IL
controlled high voltage FETsl
Three 4000 series CMOS ICs are required to interface
data from HP-IL to the switch control gates. A sepa-
AN83-6
rate Si7661 is shown on the multiplexer circuit in case
the multiplexer is built independently of the DVM.
(Figure 1) If it is built independently, a higher supply
voltage can be used. This will allow higher analog
voltages to be switched. Siliconix also manufactures
the S0210 series which are discrete switch devices;
these may be used if superior channel isolation is required and/or higher signal voltages must be
switched.
HP-ILlmultiplexer handshaking is very straightforward. The OAVO pin is used to enable a CMOS latch
which stores the last three bits of the transmitted ASCII character. The ROVO pin is not used while the
OACI pin is tied to ground. This is the simplest handshake scheme possible with HP-IL.
In the multiplexer, the three least significant bits of
the ASCII character taken from the OA bus are used
to select one of the eight analog inputs. The "OUTA"
command in HP-41 software sends the contents of
the Alpha Register to the IL device. The very simple
hardware interface requires some special compensation in software. The most important constraint with
this circuit is to send only one ASCII character at a
time. This will prevent "glitches" and false data from
being latched. In its normal operations mode, the
HP-41 will automatically send an "End of Data· ASCII
character at the end of an alpha string. The last ASCII
character sent is the one which is latched into the
multiplexer. For this reason, the "End of Data" character must be restrained. This is accomplished by
setting Flag 17 "SF17" in the software. A more complex problem involves mathematical manipulations of
numbers specifying the multiplexer channel. Such
manipulations must take place with digital information
- not alpha characters. Since HP-IL can only send
data from the Alpha Register, these digital characters
must be sent to the Alpha Register for transmission
to the multiplexer. A problem arises because a decimal point "rides along" with the number to the Alpha
Register. The decimal point is consequently read by
the IL interface and sent as an ASCII character to the
multiplexer causing a "glitch" or an invalid latch. This
problem can be solved by clearing Flag 29 "CF29"
and not displaying fraction data "FIXO". With these
two additional simple commands, the desired numeric ASCII character will be latched into the mUltiplexer.
13-135
AN83-6
..... Siliconix
incorporated
~
GPIO BUS
NO
DAO
DAOI
DA1
DA2
+5V
+5V
DAVO
14
14 1312
5
16
4076
4584
ALL RESISTORS 20 k.O.
+5V
9
10
11
4051
13 14
15 12
(-V)
3
6
14 11
S05002
4
S05002
5
ANALOG INPUTS
ANALOG OUTPUT
TO 517135
ANALOG INPUTS
Figure 6. Multiplexer Schematic Diagram
SOFTWARE EXAMPLE
Table 2 shows a simple program which will sequence
the eight input multiplexer, display the input channel
number, read In the voltage, display the voltage, and
loop back. It is included to provide a sample program
to get the system working and illustrate how the necessary commands can be arranged. The power of
the HP-IL system may be appreciated when one sees
only 29 lines of programming I The user will in most
instances modify or rewrite programs to meet individual needs.
Details of HP software are contained in the literature
provided with the applicable HP devices. The
13-136
HP82166C Interface Kit includes a very comprehensive system description of HP-IL contained in multiple
volumes. One word of caution to the hardware designer; there are numerous errors and misleading
diagrams in the HP booklet entitled" HP 82166A HP-IL
Converter Technical Manual" (Nov. 81). The corrections to these errors are in a follow-up booklet "HPILIGPIO Interface HP-IL Converter Manual Supplement".
In conclusion, Siliconix offers the necessary integrated circuits to easily facilitate HP-IL interface to a
low cost DVM design. This solution reduces the problem of such an interface to an easy layout task.
.-r Siliconix
incorporated
AN83-6
~
Table 2
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
LBL DVM1
0
STO 01
LBL 02
VIEW X
TRIGGER
IND
.0001
.
FIX 4
VIEW X
FIX 0
CF 29
RCL 01
7
16
17
18
19
20
21
22
23
24
25
26
27
28
29
-
REFERENCES:
=
X 07
GTO 03
RCL 01
1
+
LBL 03
STO 01
CLA
ARCL 01
SF 17
OUTA
GTO 02
END
1. Electronic Design, Parzybok, Hanson, Dec. 24,
1981.
2. Siliconix Application Note: • A High Performance
Video Switch", Zavrel.
3.
Siliconix Application Note: • A High Quality Audio
Crosspoint Switch", Zavrel.
13-137
..... Siliconix
incorporated
AN83·4
~
IMPROVED SYSTEM PERFORMANCE USING
MICROPROCESSOR COMPATIBLE MULTIPLEXERS
Brian Wadsworth
Walt Helnzer
Revised January. 1988
INTRODUCTION
These Siliconix CMOS multiplexers, the DG526,
DG527, DG528 and DG529 , feature the excellent
characteristics of the DG506A-DG509A series with a
bonus: latching logic. Microprocessor based systems are rapidly taking on more control tasks in electronic equipment. On-chip latching logic in a multiplexer does therefore greatly simplify the microprocessor interlace design and improves system performance.
When the microprocessor is used in the "real world"
of analog signals, it is often used in conjunction with
analog multiplexers. Until recently, to interface the
microprocessor to the multiplexer has meant the use
of some external memory device. These methods
sometimes impaired system performance by compromising processor speed and always meant an increased component count. Two of these methods
are illustrated in Figure 1.
With the introduction of these new multiplexers, the
method of interlace has been simplified. These devices have the latch function incorporated into the
control circuitry of the multiplexer. Figure 2 illustrates functional diagrams of these multiplexers.
To examine the mode of operation, let us consider
the DG528. The addition of the data latches on-chip
has meant that two new control lines had to be introduced, i.e. WR and RS. Figure 3 shows a detailed
diagram of these input latches.
MICROPROCESSOR
PERIPHERAL INTERFACE
ADAPTER
POARTt~~~~~~~::=l
..E!IA
DG508A
EN
ANALOG
INPUT
SIGNALS
.------< SERIAL CONTROL INPUT
CHIP ENABLE
PORT
B
SI
SIP
~~=f-:::l
~
USING SERIAL TO PARALLEL
REGISTERS TO MAINTAIN
SWITCH CLOSURE
Figure 1. Traditional Methods of Driving the DG508 MUX/DMUX with a Memory Device
13-138
ANALOG
INPUTS
&
OUTPUTS
AN83-4
Siliconix
incorporated
v-
v+
v-
GND
51~~--------~r1
52~q_---------a1
53~+_-----~r1&~-L_i
53a'o-''r-----a'1 &--+--"-_+
54 ~'t-----~1 ~-I--7---7---i
55 ().l>'I-----o'1 &....£-!--+-+--i
560-"'1----9"'1 '"'-!-+-+--i--i--t
57 ()..!.If---o''1 &..Jf--i--r--,.-;--t---+
58
54a~~-~r~-~--~--~4
D
Da
51b~~-~~--r--~-~
52bc>"'t---+----;~-o,
&--.---+
53b~4_-~--2 clock (often directly connected to the
DBE) with R/W line. The gating of the chip select
with the 11>2. R/W combination is functionally identical to the 8080 connection.
The Z80 to multiplexer interface is shown in Figure 7.
Simply by gating the WR and MREQ signals with the
standard es signal allows the correct WR signal for
the multiplexer to be achieved.
+15V
DATA BUS
PROCESSOR
SYSTEM
BUS
RESET 0 - - - - - - 1
+5V
ADDRESS
~~~~~
1 OF 8
v-15 V
Figure 5. Complete 8085 MIcroprocessor to DG528 Interface
13-142
ANALOG
OUTPUT
H
AN83·4
Siliconix
incorporated
+15 V
AO
A1
A2
EN
DATA BUS
DG529
RESET
Da
AS
Db
CONTROL
BUS
WR
ANALOG INPUTS
v-15V
FIGURE 6. Complete 6800 Microprocessor Bus to DG529 Interfaoe
DATA BUS
AS
AO
A1
A2
EN
v+
AS
Z80
SYSTEM
BUS
DG528
WR
WR
MREQ
v-
l1li
ADD BUS
Figure 7. Z80 TO DG528 Interface
13-143
AN83-4
...... Siliconix
incorporated
~
Another important improvement achieved on the
PLUS 40 process was the introduction of an ion-implantation technique. This technique allows much
greater process control which results in very uniform,
repeatable device parameters. In the case of analog
multiplexers, for example, we achieve better matching characteristics switch to switch.
The Process
These devices have been constructed using a high
voltage CMOS process called PLUS 40. This process
was designed to provide a more rugged device while
at the same time offer performance improvements
over the original CMOS process. Basically, two features improve the ruggedness of the device:
(a)
(b)
CHARACTERISTICS
The gate oxides of the MOS transistors have
been thickened, improving the DC rupture voltage by 33%. Combining this benefit with the
improved input protection circuits and body
clamped switch design results in improved
static voltage immunity.
Having discussed the performance of the device, we
can now look at some of the important characteristics involved:
1. First, the most critical specification of the device
is its microprocessor timing arrangements. As
was mentioned earlier, the timing of these devices was designed to be compatible with the
SOS5A. In actual fact the timing is such that the
SOS5A-2 can be operated on its maximum 5 MHz
clock rate. The waveforms shown in Figure S illustrate the timing specifications for the DG52X
series.
The process maximum rating has been increased. PLUS 40 CMOS devices have an absolute maximum rating of 44 V between supply
rails. This means that devices can be operated
at ±15 V supplies and still be within 75% of
their maximum ratings.
Minimum Input Timing Requirements
tww WRITE Pulse Width
tow
Min Umlts
over full temp. Unit
range
Measured
Terminal
Parameter
WR
300
A. EN Oata Valid to WRITE
AO. A1. (A2),
(Stabilization Time)
WR
AI EN Data Valid after
WRITE 3 (Hold Time)
WR
En
180
ns
two
tRS
RESET Pulse Width
RS
AO. A1. (A2).
En
500
RS
1.5Vf
3V~
OV
tRS~
Vo
SWITCH
OUTPUT
tOFF(RS)::iO.BVO
OV
FIgure 8. Timing Diagrams
13-144
AN83-4
...... Siliconix
incorporated
~
2.
Another parameter of importance, especially in
such applications as sample and hold, is that of
charge injection. The graph shown in Figure 9
shows a typical curve for this parameter. In fact
all PLUS 40 devices have compensation on the
output switches to reduce switching errors due to
charge injection.
2
1/
j
8
"I
QI
(pC)
61-"
!"o
" r--I- )'"
... "
"4
2
-16
-12 -8 -4
-14 -10 -6 -2
2
4
6
8
12 16
10' 14
VSOURCE
Figure 9. Charge Injection
VB.
3.
Much simpler power supply requirements are facilitated due to the on-chip regulator and the
PLUS 40 construction.
4. Its PLUS 40 construction also means a more reliable, high performance device.
.n.
RSOURCE= 0
Chold = 200 pF
0
2. Because the timing arrangements are fully microprocessor compatible, then a more efficient system performance is obtainable.
Analog Signal
3. TheVERRoR figure of merit is sometimes used as
a parameter for evaluating switch performance.
This parameter is the product of rOS(ON) and
IO(ON) switch leakage current. It is a primary
contributor to switch voltages errors when switching very low level signals such as thermo-couple
voltages. The DG528 has a worst case specified
VERROR of 100 IJ.V at 125 D C, while at room temperature this figure reduces to 4 IJ.V maximum.
APPLICATIONS
Temperature Monitoring
In these systems, an array of transducers are
switched one at a time to an analog-to-digital converter. Figure 10 illustrates the necessary steps in
designing the front-end system.
This system assumes that the transducers generate small differential signals upon which fairly large common-mode
noise is superimposed. This common-mode signal
can be assumed to be 50 or 60 Hz power line pickup. Transducers with this type of characteristic
would be thermistors wired in a bridge configuration.
To calculate the errors introduced by the multiplexer,
assumptions about the range of the differential signal, Vdiff, need to be made. A weighted thermistor
bridge will easily have an output voltage swing of 0 to
100 mV, representing an input temperature range of
o to 100 D C. The second assumption is that the common mode noise pick-up is approximately 2 V p-p.
Finally, a measurement accuracy of 1%, or 1DC is
required from a bridge with nominal output impedance of 500 n.
There are basically two sources of errors to analyze:
(a)
DC errors contributed by the multiplexer. Figure 11 shows the steady-state differentiai voltage input path for one switch closed. As can
be seen, the primary error source is the product of leakage currents in the signal path resistances. These leakage currents generate additional system offset voltages which, Eilven
though the bridge presents an unbalanced resistance, are acceptable.
(b)
Common-mode voltage becoming a differential error due to the resistively unbalanced signal paths. This is the major contributor toward
system error.
SUMMARY
We are now in a position to analyze this information to identify user benefits. These benefits can
be itemized as shown below:
1. The ease of interfacing means that component
count is reduced. This has the obvious benefit
that overheads are reduced because component, inventory, manufacturing and production
costs are reduced. Also, because component
count is reduced, the systems reliability is increased.
13-145
~
~
..,. Siliconix
incorporated
AN83·4
~
THERMISTORS
0G529
i5V
o
R2
R4
Rl
R3
SYSTEM BUS
Figure 10.
1------1
+
I
I
Vdlff I
I
I
I
OIFF
INPUT
AID
vCMI
I
I ":'"
IL______ ..JI
It is worth pointing out at this point that if the bridge
resistances were balanced, i.e. RS1 = RS2 = 500 .n,
then the multiplexer would only contribute a 0.024%
error (assuming a 2% match for switch on-resistance). The dynamic characteristics of the switches
are relatively unimportant in this application since
temperature is a slowly varying signal.
Figure 11. Steady State Errors
The total error voltage due to the DG529 Is calculated as:
V error
= I O(ON) X (rOS(ON)a + SOO)
- I O(ON) X (rOS(ON)b
+ 100)
=10 nA X (306 + 500) -10 nA X (300 + 100) =4.06 JJ,V
Thus the multiplexer contributes negligible offset error.
The differential Input AID would contribute an additional offset of:
Verror
= I BIAS (+) X (rOS(ON)a + 500) - I BIAS (-) X(rOS(ON)b + 100)
13-146
Figure 12 shows how the common-mode voltage directly adds to the differential signal representing
temperature. The net result is a 50 Hz differential
error signal, superimposed on the DC temperature
signal, of 1.6 mV p-p. This represents an error of
2°C which can be eliminated using an integrating AID
sampling at an integer multiple of the 50 Hz noise
frequency.
AN83-4
...... Siliconix
incorporated
~
and capacitances. Leakage currents limit the maximum measurable resistances while capacitance increases the measurement settling time.
Switch leakage currents should be 10% of measured
current to enable 100 Mil resistances to be measured. Therefore maximum leakage should be:
assume
2 VOLTS
HERE
10
100
Vdlff
100
I1A
The DG528 has a
of 10 nA at +25°C.
Figure 12.
roh~h~~~~1~~~S t~:1:~ ~C~~~W'ln~!h:olrf~~ 1~: the AID
X 10
due
= (500
k I (500 + 306 + 500 k) - 500 k I (100 + 300 + 500 k»
X2=1,6mV
The 1.6 mV adds to the thermistor output voltage signal as a
sur:rlmpoSed 50 Hz normal mode voltage. This signal can be
re ected by using an Int~ratlng AID converter sampling at an
In ager multiple of the St------fI
FORCE NODE
v-
0-_---1
FORCE NODE
DG528
Figure 14. Simplified Circuit Highlighting the Insulation Test
13-148
Figure 15. Simplified Circuit Highlighting the
Continuity Test Using Kelvin (4
wire )Senslng
AN83-4
..... Siliconix
incorporated
~
can then condition these signals for the input requirements of the AID converter.
DATA ACQUISITION
The circuit shown in Figure 16 is intended to highlight
the benefits of the microprocessor compatibility of
the DG526-8. Note that this circuit also contains
DG221 analog switches. The DG221 is a quad SPST
switch with the same microprocessor timing arrangements and compatibility as the DG528 (with the exception of RS).
The adaptive gain software control algorithms available for process control systems make microprocessor based systems very attractive in these applications. Now, with the advent of the DG528, complete
data acquisition systems can be simply interfaced to
the processor. The software can then be written to
maximize the efficiency of the system by managing
the system organization.
All the components used in this circuit have been selected due to their microprocessor compatibility.
Because the gain of the sample and hold amplifier is
programmable, the DG528 can multiplex signals of
various magnitudes. The sample and hold amplifier
Conversely, the 'back-end' system utilized the
DG528 as a demultiplexer where signal outputs from
the D/A can be used for various functions. For example, it may be a corrective signal to a controller to
reduce system error or simply a signal for an analog
display.
PROCESS CONTROL
Figure 17 illustrates a novel use of the DG527. Differential multiplexers are generally used in process control applications to eliminate errors due to common
mode signals. In this circuit however, advantage is
taken of the dual multiplexing capability of the switch.
This is achieved by using the multiplexer to select
pairs of RC networks to control the pulse width of the
multivibrator. This can be a particularly useful feature in process control applications where there is a
requirement for a variable width sample "window· for
different control signals.
MICROPROCESSOR CONTROLLED DATA ACQUISITION SYSTEM
~~~EJld
~i
DATA BUS
BUS
I/F
D
A
T
A
B
U
S
OUT
B
U
S
ADDRESS
B 1---r----1I--h
U
S
BUS
FIgure 16. Enhanced System Performance using DG221, DG526 & DG528
13-149
trY' Siliconix
AN83·4
~
incorporated
EXAMPLE PROGRAM
Hex Add.
Description
Assembler Code
Hex Code
(20)00
01
02
31
LXI SP. 20BOH
Initialize stack pointer.
MVI A. cPA
Set Interrupt register value.
Set Interrupt mask (loads Interrupt register from
accumulator).
Enable Interrupt at this point (when Interrupt key
Is pressed, program runs until this point).
BcP
2cP
03
04
3E
05
3cP
SIM
OB
FB
EI
07
OB
09
OA
DB
3E
MVIA. cPF
cPF
32
STA, B400H
cPA
Load the aooumulator with the
value cPF Hex (this represents "enable" swltoh B).
Store the aooumulator value memory looatlon
(B400H Is the location of the 52B In this
application .)
cPcP
84
OC
00
OE
OF
10
11
12
13
CE
CF
DO
Example Program
3E
Load acoumulator with the value
cPB Hex (this represents "enable" for swltoh 1).
Store the acoumulator value
at memory looatlon B400 Hex.
MVI A, cPB
STA, B400H
32
00
B4
Jump (loop)baok to the enable
JMP,200BH
C3
Interrupt at location 2006 Hex
DB
and start again.
20
When Interrupt (VECT INT) key
EI
FB
Is pressed, the monitor transfers
7B
HLT
control to looation 20CE Hex.
C9
RET
Run In the Clroult Setup of Figure lB with the SDK-B5 Development System.
v+
i i
V-
voo
A1
R2
EN
A3
A4
AS
AO
DATA BUS
p-
A1
A6
A7
A8
A2
DG527
Da
Db
GND
[
I
;--11
C2 II
I
C4 I I
C3
I I C5
~I 06
I
I I 07
08 I I
HI
As
AS
WR
ADD BUS
.
.
WR
DEOODE
I
I
I
DJ
I
Q
Oex! Aex!
~L
I
f----o
GND
A
74123
OLA
B
I
r
VOO
Figure 17. Jlf' Selected Pulse Width Control
13-150
I
11 01
----11
1
OLK
f---oQ
AN83-3
...,. Siliconix
incorporated
~
A MICROPROCESSOR COMPATIBLE ANALOG SWITCH
MAKES INTERFACING EASY
Brian Wadsworth
Revised January, 1988
INTRODUCTION
The advances made over recent years in the field of
microprocessor programming have made the microprocessor a very attractive tool for systems designers. Not only does the processor significantly reduce
systems component count, but the increasingly complex algorithms developed give the microprocessor
greater flexibility especially for the measurement or
control of analog signals.
Until recently, to interface the digital world of the microprocessor to the "real world" of analog switches
has meant the use of some type of memory device.
If these memory devices are not used then the processor data bus had to remain tied to the logic inputs
of the analog switch. This memory function employed
one of the following devices: A shift register, a flipflop, or a special peripheral interface adapter. Some
of these methods are shown in Figure 1.
DG221 is functionally identical to the popular DG201A
to which it is also pin compatible, except for pin 12
which is used for the WR input. The logic truth table
and pin configuration for the DG221 are shown in Figure 2.
Circuit Details
The circuit shown in Figure 3 is a simplified schematic of a single channel. It shows the logic interface
circuitry, coupled with input protection, followed by
D-type latches, level shift and driver circuitry, and finally the CMOS output switch.
The DG221 quad latching analog switch combines
both functions on a single chip. These latches eliminate the requirement of "WAIT STATES" used to accommodate slower 110 functions which compromise
processor speed. This simplifies the interface methods and facilitates more efficient microprocessor
performance.
The logic interface circuit has been designed to
make microprocessor interfacing as simple as possible. The digital inputs, due to their CMOS construction, draw negligible current and provide extremely
low capacitive loads ( 5 pF typ.). Full TIL input compatibility is guaranteed without the external pull-up resistor. These features combine to ensure that the
DG221 can be driven directly from the microprocessor data bus without overloading the bus. The input
protection circuitry consists of internal diodes to both
supply rails which forward bias to discharge any
static energy into the supply rails. A series resistor is
included to limit the current to the forward biased diodes.
The data latches are activated by the WR (active
low) input. These latches become transparent whenever WR is driven to a logic O. At this time, the
The D-type latches are driven from the WR input and
in its normal high state will isolate the output switches
from excursions as the processor data change.
cs
D
ClK
D
DATA
BUS
r--
Q
ClK
DUAL
D-TYPE
LATCH
A
IN1
IN2
ClK
D
ClK
D
Q
IN3
D
G
2
0
1
'---
a-BIT A
110
PORT
r--
IN4
DUAL
D-TYPE
lATCH
A. USING EXTERNAL LATCHES TO
MAINTAIN SWITCH CLOSURE
DG
201A
B
DG
201A
'--B. USING 1/0 PORT AS GATED BUFFER
Figure 1. Traditional Methods of Interfacing using Memory Devices
13-151
AN83-3
~
~
INX WR . SWITCH
ON
0
0
1
0
OFF
1
MAINTAINS
PREVIOUS
STATE
X
v+
WR
LOGIC "1" VIN 2: 2.4V
LOGIC '0' VIN S O.BV
S3
WR INPUT IS LEVEL
SENSITIVE (NOT
EDGE-TRIGGERED)
FIgura 2. Pin Configuration
The level shift and driver circuitry enables a full ±15
volt analog signal to be switched by the CMOS output
switch. The switch uses body snatcher transistors in
its construction to Improve switching performance by
snatching the body of the N-channel MOSFET to different potentials, depending on the switch state. In
the OFF-state, the body is snatched to the negative
rail which improves OFF-isolation by providing a low
impedance path for high-frequency signals. In the
ON-state, the body and source of the N-channel
MOSFET are shorted, which reduces the threshold
value.
A measure of switch performance is the error voltages introduced by the switching element, often referred to as the VERROR figure of merit. This error is
the product of rOS(ON) and IO(ON) maximum leakage
quoted for the device. The extremely low leakage of
5 nA max. (10 pA typ.), combined with the low ON
resistance of 90 .n max. (60 .n typ.) of the DG221 ,
combine to give an error voltage of 0.45 Jl.V maximum at room temperature. A signal level of 4.5 mV
would remain 99% accurate. This switch is very suitable for low level signal switching applications.
Finally, the regulator used for the DG221 is a feature
which is unique to the data latch analog switch range
produced by Siliconix. It is used to maintain a constant internal reference voltage for defining digital input switching thresholds at 1.4 V, allowing the device
to maintain its TTL input compatibility over large
power supply variations. The regulator has also been
deSigned to reduce the effects of temperature on parameters such as switching threshold and switching
speed, thus minimizing drift due to ambient conditions over the full military temperature range of -55
to 125°C.
Interfacing The DG221
The latch timing arrangements have been designed
to be fully compatible with the more popular NMOS
microprocessors, e.g. 8085A, 6800, Z80. The timing
arrangements for DG221 are given in Figure 4. The
timing requirements of the 8085A have also been included for comparison to illustrate the full microprocessor compatibility of the DG221.
v+o-------~~--~--------------------------_4r_--------,
GND 0 - - - - - - / - - '
IN x
o-------!-JoNII-.+-+-I
WR 0--'V',fY-.....- t - - - - I
v-o---~--+_
___________+__ _ _
~
____
~
______
Figura 3. Functional Schematic (single channel shown)
13-152
Siliconix
incorporated
~
..or
~
AN83·3
Siliconix
incorporated
Although the DG221 was designed primarily to be
compatible with the 8085A, it can also be used in
conjunction with the MC6800 series and Z80 family of
processors, as the interface circuits shown in Figures
5, 6 and 7 illustrate.
v+
ADDRESS
RMi
V
*-- tww ---.I
WR
(221)~
230nS
I
I
I.. t DW.,J
I
~
ADO-AD7
GND
180 ns
I
!+ tDW~
tWD
30 ns
v-
Figure 6. 6800 Interface
I
j4-
v+
~
I
V
WR(~P)~
14===
tWD j+
MREa
tcc~
ADDRESS
BUS
Figure 4.
Figure 7. Z80 Interface
tww Width of Control Low (WR)
tDW Data Valid to Trailing Edge of Write
tWD Data Valid after Trailing Edge of Write
SOBSA
400 (min)
420 (min)
100 (min)
BOBSA-2
DG211
400 (min)
420 (min)
60 (min)
400 (min)
420 (min)
30 (min)
This also Illustrates how the DG221 more than meets the
timing requirements of the faster 8085A-2.
All times are In nano seconds.
v+
INl
1N2
1N3
1N4
WR
I
ADDRESS
BUS
l-
GND
Figure 5. 8085-221 Interface
v-
Typical Applications
The DG221 is intended for use in microprocessor applications where the data latch facility can be of great
benefit. The circuits included in this article are intended to highlight the benefits offered by the
DG221 , while at the same time generating some
ideas for design engineers.
Figure 8 shows the use of the DG221 in an alarm system. The low loading offered by the DG221 to processor outputs enables several DG221 's to be operated in parallel without overloading the processor
outputs. A lower component count results by using
the DG221 as a Mux in the alarm sensor circuit.
The amplifier shown in Figure 9 has processor-controlled gain and inputs enabling analog signals of
varying magnitudes to be switched to a common amplifier. This is achieved by ensuring the amplifier has
the appropriate value of feedback resistance for the
correct output level. The DG221 looks into the high
input impedance of the op amp so the effects of
rDS(ON) are negligible. Furthermore, since the
DG221 can handle positive and negative signals, the
unity gain connection on the op amp is possible.
13-153
~
--
AN83-3
..... Siliconix
incorporated
~
COMPARATOR
S~
o-t----i----~~
A-+__~
SP3 o-++---i----~l'f
.A-t---+
O/PTO
ALARM
CIRCUITRY
+-+-----01" 1&...-1-_- BEARING TEMP.
SP4
+-+---(YI
I " - i f - _ OIL PRESSURE
t-i----O'!
1&...+_- STATOR TEMP.
'--+---(rr
1............_ 1 - MOTOR SPEED
CONTROL BUS
ADDRESS BUS
Figure 8.
Jl,P Controlled Alarm Monitor
VAl
Vo
VM
Figure 10 highlights the combined use of the DG221
and DG528 in a 32-channel MUX system. Because
the timing arrangements for theses devices are identical. they can readily be used together. The reset
facility on the DGg28 is particularly useful for synchronization of channel 1 during "power up" condition. The 2-level system has several advantages over
a single-level system. These are:
(i) reduced output capacitance.
(ii) reduced output leakage current.
(iii) much faster switching speed. thus higher data
transmission rates.
The switching of intensity and position in a CRT video
display is simplified by using the DG221 in a processor-based system. as is illustrated in Figure 11. This
circuit can also be adapted for radar multiplexing because the DG221 allows both the radar trace and a
marker to be displayed simultaneously since it can
be "programmed" to have more than one switch
closed at anyone instant.
~
DATA BUS
RMI
Figure 9.
13-154
Jl,P Controlled Variable Gain-Amplifier
The final circuit shown in Figure 12 shows the use of
the DG221 and the DG528 in a remote. processorcontrolled measurement system.
~
~
AN83·3
Siliconix
incorporated
The DG221 Is used to condition the Input signals to
suit the input requirements of the AID, allowing the
system to be used to measure signals of various
magnitudes.
The typical area where this may be use is in automatic test equipment. In this application, the DG528
can be used as a demultiplexer to effect the illumination of the required status lamp to indicate the test
result.
As was mentioned earlier, these are only example
applications. Other application areas for the DG221
include: communication systems, home security,
avionics, instrumentation, data acquisition, etc.
AS
ADDRESS
BUS
Figure 10. 2-Level 32 Channel Mux System
GRAPHIC
INPUTS
DATA BUS
>~==~~
III
ADDRESS BUS
FIgure 11. Simple Multiplexing
13-155
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incorporated
AN83·3
~
GAIN
SELECT
~
IEEE 488
BUS
==D
..
DATA BUS
~.~
DG221
.llP
.A .A
I CSO
DDRESS BUS; ADDRESS _
DECODE CS,
.....
I
RS
WR
~
CONTROL BUS
tJ,
I
WR 2
D-MUX
DG528
WRITE WR1
DECODE I
WR
DATA OUT
A/D
LD120
LD121A
LD122
-L<~
D.U. T.
STATUS
LAMPS
Figure 12. Remote/Processor Controlled Measurement System
CONCLUSION
The DG221 quad switch is an extremely reliable and
rugged analog switch designed primarily for microprocessor applications. The on board latches have
been designed to simplify microprocessor interfacing
techniques while at the same time allowing more efficient processor use.
The on board regulator gives much greater stability
against circuit and ambient conditions, while switch
performance achieves very low switching errors.
the gate oxides were made thicker to increase the dc
rupture voltage by 33%. When this is combined with
the logic input protection and CMOS switch bodyclamping diodes, an overall improvement in static
damage immunity is achieved. Secondly, the increased voltage rating means normal operation is accommodated with less stress to the device; thus, the
PLUS 40 process improves reliability as well as the
immunity to static damage.
THE PROCESS
To achieve this increase in process maximum breakdown voltage, an ion-implantation technique is used.
This technique has the benefit of allowing greater
process control to be achieved which enables very
uniform repeatable device parameters to be realized.
One example of this is that switch-to-switch ON resistance variation has been improved to less than 2%.
The DG221 is fabricated on our high voltage CMOS
process developed by Siliconix called PLUS 40. This
process continues to use the buried layer technique
for prevention of CMOS latch-up. This new process
was originally designed to provide a more rugged device in transient environments. To achieve this, first
Finally, due to its PLUS 40 CMOS structure and on
board regulator, a much simpler power supply design
has been facilitated. The 44 V rating allows a greater
margin for overvoltage while the on board regulator
allows for large power supply variations.
In short, the DG221 is synonymous with high performance, real-world microprocessor applications.
13-156
AN83·1
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~
The DQ308A Digitally Switches
.
Analog Signals
Walt Helnzer
September 1983
INTRODUCTION
The latch proof CMOS DG30BA interfaces easily to
system power supplies since it operates from ±5 V to
±15 V. or it operates with a single supply from +5 V
to +25 V. all CMOS logic compatible. Additionally. the
DG30BA consumes negligible standby power and can
switch in less than 200 ns. To minimize analog signal
error the DG30BA has a maximum rDS(ON) of 100 .n
over the full analog signal range which extends to the
positive and negative power supply. at the same time
OFF state signal errors are kept small by low leakage
currents.
More About The DG308A:
sistance plotted as a leakage current in Figure 3.
combined with the ON resistance characteristic of
Figure 2. guarantees full ON/OFF operation between
the V+ and V- (±15 V) power supply rails.
150
120
A: ±5 V Supplies
B: ±7,5 V
A
C: ±10 V
D: ±15 V
I
E: ±20 V
-
r--.,B...I'
/0
30
o
TA
Is
= 25'C
= -10 mA
II
90
60
One channel of the four channel DG30BA is shown in
Figure 1 which displays the input protection. logic interface. internal level shifting and switch contact circuitry. With V+ = 15 V and V- = - 15 V. a logic "1"
control input (VIH = 11 V minimum) will close the
switch. and a logic "0" (VIL = 3.5 V maximum) will
open the switch. The ON resistance of the switch
over the analog signal range has the characteristic
double peaked curve shown in Figure 2. The OFF re-
I
-20
C
D
"""
--'
-
i-"'"E
~
-10
o
10
20
VO- DRAIN VOLTAGE (V)
FIGURE 2. rOS(ON) vs. Vo and Power Supply Voltage
V+
SOURCE
CONTROL <>",'J"'___
IN
GND
DRAIN
V-
"-----v----J '--___________- - - - - - - . / '--___________------...J
INPUT
PROTECTION
LOGIC INTERFACE
AND SWITCH DRIVERS
ANALOG SWITCH
Figure 1. CMOS Schematic Diagram
13-157
H
AN83-1
the power consumption increases in proportion to the
increasing toggle frequency, Figure 4 shows the increase in power dissipation as toggling rate increases.
When VANALOG exceeds
power supply switch
substrate diodes
I. 1 1
begin to conduct.
1-1 o (OFF)-
80
I I I
pA
..... i--'" I-"'"
IO(ON)
-80
-
_i--'"
o -IS(OFF)
vl J5 V, V- = -15 V
-120
I I T( ,21"CI I I
5
10
15
-15 -10
-5
o
VANALOG - ANALOG VOLTAGE (V)
Figure 3, DG308A: I O(OFF) & I O(ON)vs. Vo
100
10
/
::
01
/
::
=
:
-
::
=
:
-
::
=
:
V
10 100 1 k 10 k 100 k 1 M
LOGIC SWITCHING FREQUENCY
(Hz) 50% DUTY CYCLE
Figure 4, DG308A: Device Power Dissipation
vs. Switching Frequency
Only residual leakage current flows when the circuit is
either ON or OFF resulting in a power dissipation of
less than 10 mW. However, as the switch toggles,
The actual switching time to turn ON (tON) and turn
OFF (tOFF) the switch consists of two distinct intervals: propagation delay and switch actuation, During
the propagation delay interval, the CMOS logic input
control signal amplifies, level shifts and begins to
drive the output FET switch contacts. Switch actuation occurs rapidly as current through the switch begins or is interrupted generally occurring within 20%
of the total switching time (see Figure 5). To a first
approximation the turn ON time (tON) is independent
of the external circuit characteristics; however, turn
OFF time (tOFF) depends on external circuit time
constants. The (90% - 10%) settling time portion of
switch turn off calculates as:
tsettling
= 2.2 RL
[CL
+ CD(OFF) 1
from 90% to 10% of Vo (see Figure 6), For the load
conditions RL = 1 kn and CL = 35 pF:
tsettling
= 2.2
x 1 kn x (35 + 8) pF
20 ns
+15 V
V+
50%
Vs = 3 V
S
o---t----------<~:
I
_...1
90%
Vo
V 1NH = 15 V
V 1NL = 0 V
GND
Figure 5, Switching Time Test Circuit
13-158
ns
The turn ON time exceeds the turn OFF time over the
full temperature and analog signal range by design,
This approach results in guaranteed break-beforemake switch operation in multiplexing applications,
LOGIC INPUT
tf<
= 95
In order to minimize the external loading effects on
the tOFF parameter, the DG308A specification measures between 50% of the logic control input and 90%
of the output voltage V 0 (Figure 5), thus only a portion of the settling time (70% of one time constant) is
included in the tOFF measurement. The additional
settling time to the 50% point of Vo is 29 ns,
LOGIC "1"= SWITCH ON
t r < 20 ns
Siliconix
incorporated
AN83·1
fl'Y' Siliconix
~
incorporated
I I
10
LOGIC
INPUT
!oJ.
5
0
A
1__
Bf-
10
OUTPUT
VOLTAGE
(Vo)
~
Cr-
j.-
Dr-
f4
90%
I
5
OFF
A Four Channel Analog Multiplexer:
v+ = 15 V
V-=-15V
VI'l=+10V
I
'....
ON
I I
10%
0
I-
The four channel input multiplexer (Figure 7) displays
the characteristic dead time achievable between
channel selections resulting from tON being longer
than t OFF. This desirable dead time (break-beforemake operation) prevents transducer signal sources
from being momentarily shorted together during
channel selection.
I ~
OFF
TIME (ns)
LEGEND
A - TURN ON PROPAGATION DELAY
B - TURN ON SWITCH ACTUATION
A+B - TOTAL SPECIFIED TURN ON TIME
C - TURN OFF PROPAGATION DELAY
o -1.<&T~f SPECIFIED TURN OFF TIMEt OFF 90%
E - TURN OFF RC DELAY DUE TO RLx (CD(OFFtcL)
Figure 6. Switching Time
+15 V -15 V
lV~+-~L-
__~==~
While looking at multiplexing applications of the quad
switch array, a few important comments apply to signals occurring outside of the normal analog signal
range of V+ to V-. Often analog multiplexers receive
their input signals from sources located far away.
The signal sources sometimes pickup transient signals which exceed the V+ and V- power rails. Under
this condition the DG308A acts as a voltage clamp
which can shunt transients up to 30 mA to the V+ or
V- power supplies. Figure 8 gives a working model of
the transient clamping diodes during both switch ON
and OFF states. Remember, the DG308A is constructed with a latch proof CMOS process (Reference
1) •
______-h
2 V'o-+--!---3Vo-~~--~-~
~....,.-... VO
A....---IH
4Vo-~-r--r_--+_-~
10 kO
SOURCEo-~---"
INI
I I r - -......--o DRAIN
--...,ONLY PRESENT
WHEN SWITCH
IS OFF
B.B.M. INTERNAL (DEAD TIME)
Vo ~
(VoltS)~
~~~~~~~~~-
RCHANNEL = 100.n Max whenlNx = "1"
RCHANNEL = 100> 1000 Meg Ohm whenlNx = "0"
Figure 8. Typical Single Channel Overvoltage Model
IN2
+------'
IN3
+ ____---l
IN4 +---------'
Figure 7. Four Channel Analog Multiplexer
When transient signals exceed the capability of the
DG308A's clamping diodes, external protection circuits are required. One of the most often used and
effective protection circuits are clamped series input
resistors (Figure 9). This circuit has some important
subtleties worth mentioning. First, the series resistor
combined with the switch input capacitance of 7 pF
13-159
--=~
..,. Siliconix
incorporated
AN83·1
~
provides a low pass filter action that rapidly attenuates very large fast transient voltages e.g., electrostatic discharge. Second, the series connection of
diodes (Zeners) tends to balance the individual leakage currents which could become a serious problem
when the circuit operates at high ambient temperatures. Diode leakage current doubles with every 1Q°C
increase in temperature. The diode leakage current
flowing in the signal path generates undesirable temperature sensitive offset voltages. These offsets
cause problems with low level voltage switching applications, e.g. thermocouples. The Zener diodes
perform the initial voltage clamping of a transient signal. It turns out that very fast transients, like ESD, are
more effectively clamped by zeners than by forward
biased diodes. Regarding placement of 8-bit and
12-bit AID converters (0.2% and 0.01 %), let's look
at the accuracies attainable in programmable gain
amplifiers.
Actual switch gain calculation: rOS(ON) = 100
AV(X50)
n
Rf1
+1 =
2450K +1
RIHOS(ON)
50K + 100
= 49.9021
(X50) Gain Error =
(50-49.9) 100
50
= 0.2% error
AV (X5)
2450K I (217.78K + 100) =4.99374
5K + 100
(X5) Gain Error =
5-4.99374
5
x 100 = 0.12 error
OG308A
SERIES INDUCTOR
v+
v+
I
.L.-CS(OFF)
OG308A
1011
ALTERNATE
20 v
ZENER
RSERIES
1021
ALTERNATE
20V
ZENER
I
Figure 9. Series Resistance Diode Clamped
Overvoltage Protection Circuit
Figure 10. Series Inductance Overvoltage
Protection Circuit
The low rOS(ON) of the DG308A allows us to meet the
0.2% accuracy requirement imposed by the 8-bit
AID converter. Note that the percent error in gain
accuracy is larger in the high gain (X50) rather than
the low gain mode (X5).
Figure 11 shows a common switch able gain amplifier.
This circuit has two gain states X5 and X50. If the
The circuit of Figure 11 also h~s a dummy switch
(SW1), which is always closed to provide some temperature tracking between the feedback resistors
and input resistors. The rOS(ON) of most analog
switches has a positive temperature coefficient of
0.7% per degree centigrade. The rOS(ON) will double
if the temperature increases by 140°C.
analog switch had 0 n ON resistance (rOS(ON)), the
given values of Rf1 , Rf2 and RI would produce the
circuit gains of X5 Y'hen switch 2 was closed and X50
when switch 2 was open. The rOS(ON) of the analog
switch produces a gain error of 0.19%.
In order to achieve the 0.01% accuracy requirement
of a 12-bit AID converter measuring system, the programmable gain circuit can be rearranged which almost eliminates the rOS(ON) gain sensitivity. The circuit of Figure 12 achieves the required 0.01 % gain
13-160
~
~
AN83-1
Siliconix
incorporated
accuracy by placing the analog switch in series with
the high input impedance of the FET op amp. In this
circuit gain accuracy is determined by the resistor
ratios, which can be chosen to properly track over
the operating temperature range. It turns out the
weak component of the circuit (Figure 12) becomes
rOS(ON) the op amp due to its input offset and CMR
capability.
The circuit (Figure 12) also provides high input impedance and non-inverting operation. Additionally,
using suitable wide band-width clamping Zener diodes between the series resistor and analog switch is
not preferred since this would increase offset error
generation due to the differential diode leakage flowing across the series resistor causing an Ixr offset
error voltage.
capacitance of the analog switch provide a very effective damped two-pole low-pass filter. Basically,
the inductor blocks the high voltage transient from
passing to the analog switch. Additionally, the lagging current passing through the inductor to a first
approximation integrates according to:
i L = transient time VIN - Vswltch
F;$
0 dt.
So far we have been discussing the transient handling capability of the DG308A at the source or drain
terminals. The logic inputs ONx) have protection circuits shown in Figure 1. The protection circuit will
stand off input voltage transients going positive to
22 V or negative to 44 V with respect to the V+ power
supply terminal. The power supply terminals will handle 44 V transients from V+ to V-, which translates to
22 V for a dual supply application.
Rfl
Rf2
SW2
~------~-------------oVO~
1/4DG308A
1I40G308A
AV=~
VIN
R1
+-!
90 k.o. AV= R,
R2
"'-----1---+
+ R. + R. + R4
= 100
R.
A-__
5 k.o.
WITH SW 4 CLOSED
4 k.o.
GAIN ERROR DETERMINED
BY RESISTOR TOLERANCE
1 k.o.
OP AMP OFFSET AND
SW4
R4
L.._ _ _....
2~b'6'~b'* ~rtIJIRCUIT,
Figure 11. Programmable Gain Amplifier
One disadvantage of the series input resistor protection circuit, in Figure 9, is the increased total resistance in the signal path which will increase system
noise pickup, thus degrading effective transducer
signal-to-noise ratio. An alternate fast transient protection circuit shown in Figure 10 does not increase
total transducer resistance but still dampens fast
transients. Taking advantage of the basic properties
of lossy inductance, the ferrite bead allows signal frequencies generally close to D.C. (e.g. thermal couple) to pass through the system to the amplifier. The
low frequency resistance of the ferrite bead surrounding the signal lead is very low which minimizes
the additional resistive contribution to the transducer
signal-to-noise ratio. The high frequency operation of
the series lossy inductance combined with the input
Figure 12. Precision Weighted Resistor Programmable
Gain Amplifier
Important Applications Of The DG308A
The quad single-pole single-throw DG308A is a generalized building block found in several types of electronic test equipment. Some of the electronic equipment using analog switches include intelligent instruments, computer peripheral equipment, and automatic test equipment.
We will be looking at some of the basic circuits found
in these applications including programmable gain
amplifiers, peak detection, velocity integrators, remote switching, and programmable filters.
13-161
--=I'I!II
AN83·1
..... Siliconix
incorporated
~
Programmable Gain Circuits:
One of the most important analog circuits found in
intelligent instruments and automatic test equipment
are the programmable amplifiers and programmable
attenuators. The programmable gain amplifier scales
the measured signal into the full-scale range of the
instruments analog-to-digltal converter. Consequently, the programmable gain amplifier should
have better accuracy than one-half of the least significant bit of the system's AID converter. For an
8-bit AID converter, 1/2 LSB represents 0.2% of fullscale.
For a 12-bit AID converter, 1/2 LSB represents
0.01% of full-scale. Keeping in mind the accuracy requirements, op amp frequency response and settling
time can be easily optimized. In this circuit design it
was not necessary to make rOS(ON) small compared
to the gain setting resistor values. Consequently, the
gain setting resistor values can be reduced until the
op amp can no longer drive the total resistive load.
Constructing Figure 13 (only resistor values change
from Figure 12) proved that not only settling time improved, but so was the magnitude of the ever present charge Injection of the analog switch. Figure 14a
to 14b shows the improvement in settling time when
the total divider resistance is decreased by an order
of magnitude. We quantify the magnitude of charge
injection originating from the analog switch in terms
of Q (pico-Coulombs). The DG308A injects approximately 35 pC of charge during every switch transition.
If the amplitude of the charge injection caused transients is still objectionable, the addition of an extra
buffer amplifier results in the charge compensated
circuit of Figure 15.
v1
R.
Vo
1/40G308A
R3
k.o.
6.2 k.n.
R,
= 610 k.o.
1
1I40G308A
14b
6518.0.
613.0.
60.0.
::.J
LOGIC TIMING ,.-_ _ _ _ _- - ,
~
Figure 13. Precision Programmable Amplifier
13-162
+ LF356
14a
AV"10
AV" 100
= 65
R.
40~ec
~~
_______
Figure 14. Logic Timing
+ LF357
AN83·1
Siliconix
incorporated
GAIN
GAIN
=
RIA
RIA
= RIB
RIB
o--~-
I
I
I
>---1-----0 V OUT
0- -, -
I
{~-
CHARGE COMPENSATING
SWITCHES
-::Figure 15. Charge Compensated Inverting Programmable Gain Amplifier
Peak Detector Applications:
Integrators:
The basic peak detector circuit shown in Figure 16
utilizes the DG308A as a zero-offset reset switch.
That is. no voltage will be left on the capacitor after
reset. A maximum of ±10 V may be discharged directly by the DG308A since it has a maximum switch
current rating of 100 mA for 1 ms. Capacitor values
up to 10 j.I.F maximum are allowed. This peak detector circuit is commonly found in computer disk and
tape drive equipment.
Velocity integration used in motor head pOSitioning
circuits takes advantage of settable time integrators
such as Figure 17. This circuit results in precise linear integration since the set point is determined by
the set voltage and RsIR2 ratio.
R.
SET
INPUTQ_ _
ANALOG
Vs INPUT
R,
-,\R",'/Iv-~-I-~~
.....H-.p......
OUTPUT
Vo
">11-_4>_--_4----0 VOUT
T
CMOS
INPUTS
RESET CONTROL
-::-
Figure 16. Basic Peak Detector
LOGIN INPUTS
FEATURES
• MINIMAL INTEGRATION ERROR
DUE TO LOW CHARGE FEED THROUGH
• LOW LEAKAGE
Figure 17. Three Mode Integrator
13-163
..... Siliconix
.r;;;JI incorporated
AN83·1
Programmable Filters:
An active filter is sometimes used at the front end of
programmable test equipment. The first order active
filter shown in Figure 18 can digitally select four different break frequencies. In order to minimize the effect of switch capacitance on frequency response,the DG308A is located between the low output impedance of the op amp and the frequency determining feedback capacitors.
The 100 .n rDS(ON) of the DG308A results in an outside of selected frequency range maximum attenuation of 40 dB.
REFERENCE:
1. Analog Switches and Their Applications, June
1980, AN75-1, pg. 7-57.
+ 16V
160
120
fea
SELECT o-I--;:,-==~""""'H
- ....
........
80
CMOS
CONTROL
LM101A
.... OPEN LOOP GAIN -
.... "I
Av
(dB)
fC2
SELECT 0-1---,::-:;;=-.1.1'1-1
40
fCl
SELECT 0-1----'+-1
o
-40
1ea
1~"" ....
.......... .......... :......... - ........
" " ..........
L-
lt~ 1~ ~~
l'
lMA
1C2
1Cl
10
1~ ....
~
="'.
........... ........... ...........
"
100
1k
10 k
FREQUENCY (Hz)
100 k
1M
AL (VOLTAGE GAIN BELOW BREAK FREQUENCY)
>-------_-0
VOUT
= :~ = 100 (40 dB)
1c(BREAK FREQUENCY)
R.
10kA
30 pF
= 2'lT~3CX
1L (UTILITY GAIN FREQUENCY)
= 2'lT~
Cx
MAX ATTENUATION = rOS(ON) = -40 dB
10 k
FI!lure 18. ActIve Low Pass Filter wIth DIgItally Selected
Break Frequency
13-164
AN76-7
.... Siliconix
.1;11 incorporated
FUNCTION/APPLICATION OF THE
L161 MICROPOWER COMPARATOR
INTRODUCTION
The L161 is a monolithic quad micropower comparator with an external control for varying its AC and
DC characteristics. The variation of a single programming resistor will simultaneously alter parameters such as supply current, input bias current, slew
rate. output drive capability, and gain. By making
this resistor large, operation at very small supply current levels and power dissipations - typically in the
low microwatt region - is possible. The L161 is
therefore ideal for systems requiring minimum power
drain, such as battery-powered instrumentation,
aerospace systems, CMOS designs, and remote security systems.
Description
The L161 is fabricated using standard bipolar processing. The circuit (Figure 1) is composed of five
major blocks - four comparators and a common bias
network. 01 - 06 and Dl form a Darlington differential amplifier with double-to-single ended conversion.
06 is a dual current source whose outputs are exactly twice the current flowing through 08. The collector current of 08 is a function of the current supplied externally to 09-010, which in turn is known as
the set current or I SET. This set current is established by a resistor connected between the I SET terminal and a voltage source, most commonly the
positive supply. 011 prevents excessive current
from flowing through 09 and 010 in the event the
I SET terminal is shorted to the positive supply; it has
no effect on circuit operation under normal conditions.
The set current can be expressed as:
ISET
[(+V) - (2VBE) - (-V)]
(1 )
RSET
where +V is the voltage to which the control resistor
is connected, -V is the negative supply voltage, VBE
is the base emitter drop of 09 or 010 (about 0.7 V),
and RSET is the value of the external control resistor
or set resistor. Equation 1 is simply a derivative of
Ohms law. There is also an analytical relationship
between ISET and the total supply current:
ISUPPLY
= [ISET
(current sourced by 06 to 08)
+2IsET (current sourced to the differential amplifier by 06)
+2 I SET (current sourced to the comparator output by 06]
X 4 (the total numbers of comparators)
+ ISET (current sourced through 011,
010, and 09 to -V)
[ISET + 21SET + 2ISET] x 4 + ISET
= 21 ISET
=
r--------,
r---------------------------------------~~B~IA~S-C~I~RC~U~IT-----+-O+v
(COMMON TO
ALL FOUR
AMPLIFIERS)
+IN
-IN 0-_+--------+---------1-------......,1---'
L-------~--------~~------~------------~~----4_--+_-----4--------+_0-v
L. _ _ _ _ _ _ _ _ .J
Figure 1. Schematic of One Channel of the L161 Plus the Common Bias Network
13-165
.-F' Siliconix
,,6;;11 incorporated
AN76-7
The output current pulldown capability ~ od of the
L161 is about 2 orders of magnitude greater than the
high output drive current, ~ OH), which allows wireDRing the outputs. IOH is simply the current sourced
by Os:
(3)
IOH = 2 XISET
IOL is found by multiplying the current sourced by the
collector of 06 by the gain of 07:
The designer's ability to program the key parameters
of the L161 enables him to program just enough supply current to meet his design objectives. This coupled with the L161's performance using only
mlcrowatts of power makes it ideal for any
micropower or battery-powered system, as well as a
replacement for existing higher power comparators.
The following applications illustrate the flexibility and
unique capabilities of the L161.
200
NEhATlvE I
180
TRANSITION
fSR160
(4)
140
The beta of 07 Is about 75-150.
Input bias current is a function of the betas of input
devices 01-02 and ISET. This is difficult to express
analytically because 13 varies greatly with both processing and collector current; however it is roughly
proportional to the set current and can easily be determined experimentally (see Figure 2).
V
60
I
40
,/
20
o
7
6 SR+
I
/
I
J.l.s)
4
I-
Vs = ±15 V
VIN = ±100 mVp
RL = 10 M.o.
CL = 10 pF
/
I II
200
5 (VI
TRANSITION
SR+
/
V
8
/ I'pOSITIVE
/
80
9
/
II""
/
(VI 100
J.l.s)
V
i"'"
~
/
SR- 120
10
".,.
I--
600
400
3
2
I 1- o
800
1000
I SUPPLY - SUPPLY CURRENT (J.l.A)
100
Figure 3. Slew Rate vs. Supply Current
, ..... t3'V
"l'
10
1000
Ie
(nA)
" \.
~
0.1
Is 100
(J.l.A)
~
1
=
10
100
lK
10K
ISUPPLY - SUPPLY CURRENT (J.l.A)
10
13-166
~
"
FALL TIME
"'\.
Figure 2. Input Bias Current vs. Supply
Current
Gain varies logarithmically with changes in supply
voltage and linearly with changes in set current. Primary causes are the decrease in output impedance
of 07 with decreasing supply voltage and an increase
in transistor betas with increasing set current. Other
AC parameters such as slew rate and transition time
are also affected by set current; however current dependent parameters such as beta and chip capacitances make mathematical expressions imprecise.
These relationships have been determined empirically and are presented in Figures 3 and 4.
RISE TIME
1\
1
10
RISE TIME 10% TO 90% Ols)
100
Figure 4. Rise and Fall Times VB. Supply
Current With One CMOS Load
Micropower Applications
A classic comparator application is the doubleended limit detector or window comparator shown in
Figure 5. VOUT is high whenever the input voltage is
within the two limits. Because the Darlington input
stage extends the common-mode input range below
AN76-7
trW" Siliconix
~
incorporated
the negative supply, the lower limit may be as low as
-0.4 V with the V- terminal at ground. A comparison
about ground is therefore possible with only one supply.
+5V
Output
Ground
or Null
FIgure 6. Zero CrossIng Detector
VOUT
The circuit in Figure 6 may be modified to produce a
line receiver (Figure 7). The trip point is set half way
between the supplies by R 1 and R 2; R3 provides over
200 mV of hysteresis to increase noise immunity.
With 800 IlA of quiescent supply current the maximum frequency of operation is about 300 kHz. If response to TTL levels is desired, change R2 to 39 kil.
The trip pOint is now centered at 1.4 V.
+5 V
FIgure 5. Double-Ended LImIt Comparator
wIth WIre OR'd Outputs
I SUPPLy = BOO J1A
Rl
100 k.n.
The L161 is especially suited for this application because of its wire-OR capability; low output on either
comparator will pull both outputs to ground. For this
example a supply current of 90 IlA was chosen to
provide a slew rate of about 5 V/IlS. If greater output
drive current or decreased transition times are
needed, lower RSET.
3
2
Output
Enable Input
R2
100 k.n.
The zero crossing detector shown in Figure 6 is useful in sine wave squaring circuits and AID converters.
This circuit also takes advantage of the L161's ability
to detect signals below its negative rail, so only a
positive supply is needed. The positive input may
either be grounded or connected to a nulling voltage
which cancels input offsets and enables accuracy to
within microvolts of ground. The CMOS output will
switch to within a few millivolts of either rail for an
input voltage change of less than 200 Ils.
FIgure 7. CMOS LIne ReceIver
Mating the L161 with CMOS logic is natural since the
L161 draws microamps from a single 5 V supply.
However, the L161 will also drive TTL when a suitable
pull-up resistor is provided. Figure 8 shows this combination. Total power drain of the circuit is much
heavier due to the presence of the 7401. Propagation delays through the circuit are about 1 Il s .
13-167
~
..
AN76-7
. . " Siliconix
incorporated
~
-t5V
+v
RPULLUP
10 Idl.
1N914
HIGH = NORMAL
LOW = STANDBY
Figure 8. Driving TTL
In many situations further power savings can be
achieved by reducing or eliminating I SET during part
of the operating time. This is desirable, for example,
when a system is multiplexed at a low duty cycle.
The L161 may be strobed off completely by reducing
ISET to zero as shown in Figure 9. The 3N163 Pchannel MOSFET is OFF when the strobe input is high
so no set current flows into the L 161 . For a low
strobe input, the 3N163 turns ON, pullingRsET to the
positive supply and turning on the comparator. The
drain-source resistance of the 3N163 (250 0) is negligible compared to RSET. If the negative supply terminal of the L 161 is returned to ground, the 3N 163
may be eliminated and RSET connected directly to
the output of a CMOS gate. When the L161 is
strobed OFF, its outputs assume a high-impedance
state; this "three state" operation facilitates the connection of many outputs to a single bus.
The diode blocks current when the output of Al is
HIGH, and operation of the other three comparators
is normal. WhE!n the output goes low, however, the
IN914 conducts most of ISET to the negative supply.
IOL is therefore nearly equal to I RSET, and (from
Equations 2 and 4),
ISUPPLY = 21 ISET (actual)
(5)
_ ~ _ ISET
2B
10
-
+v
STROBE INPUT
+v = OFF
GROUND = ON
-v
Figure 9. Strobing the L161 ON and OFF
The L 161 will switch itself into a standby mode if one
of its outputs is connected to the I SET terminal as
illustrated in Figure 10.
13-168
Figure 10. Switching the L161 to a Low Current
"Standby' Mode
if a f3 of 105 is assumed. Equation (5) states that
the supply current of the L161 is reduced from 21 x
I Rl (normal operation) to I Rl/1 0, a factor of 210 (or
twice whatever f3 of 07 is). Total supply drain is simply the current through RSET. This circuit has an important advantage over the previous strobe circuit:
even though the L 161 is operating at a greatly reduced supply current, it is still ON and continues to
function. If a lesser' reduction in supply current is
desired, connect a resistor in series with the diode.
Figure 11 shows an L161 low battery indicator which
flashes an LED when the battery voltage drops below
a certain threshold. The 2N4274 emitter-base junction serves as a zener which establishes about 6 V on
the L161's positive input. As the battery dies, the
voltage at the negative input drops more quickly;
when the low battery threshold (typically 7.5 V) is
AN76-7
Ir'F Siliconix
~
incorporated
reached, the L 161 output goes HIGH. This turns on
the FETlington, which discharges Cl through the
LED. The interval between flashes is roughly equal to
R 1Cl, which in this case is 2 seconds. By flashing
the LED at a very low duty cycle, this circuit gives a
low battery warning with only 10 j.l.A average power
drain.
ages down to +5 V; below that the charging rate of
Cl in the positive direction is determined by IOH and
not R4. For lower voltage operation, increase R4
(and lower C accordingly) or decrease RSET.
O.ljJ.F
+9 V
ISUPPLY
0.01 jJ.F
= 10llA
•
.....
Cl
RSET
16
Rl
1 M.!l.
0.001 jJ.F
22 M.!l.
R2
5 M.!l.
TRIP ADJUST
'"
100 pF
10 pF
10
R3
400 k.!l.
2N4274
(6 V Zener)
100
1K
lOOK
f - FREQUENCY (Hz)
Figure 13. Frequency vs. the Value of
for the Squarewave Oscillator
Figure 11. A Low Battery Indicator
+10V
16
To generate pulses the positive and negative charging rates of the capacitor must be unequal. Figure
14 illustrates a method using diodes and unequal resistors. The duty cycle of the output pulse is equal to
R4/ (R4 + Rs) X 100%. For duty cycles of more than
50%, Dl can be eliminated and the duty cycle set
according to the formula,
duty cycle = R4 + Rs
R4 + 2Rs
RSET
100 k.!l.
13
JlSL
Figure 12. Squarewave Oscillator
Waveform Generators
Figure 12 is a square wave generator which is operable to over 100 kHz while Figure 13 depicts the typical frequency vs capacitance performance of the circuit. The low frequency limit is determined only by
the size of Cl. Frequency is constant for supply volt-
(6)
A similar analysis could be made for eliminating D2
when t < 50%. Figure 13 may be used to determine
frequency (= 1/period) if 1/2 (R4 + Rs) = 100 kn.
The versatile two phase clock generator of Figure 15
uses two L161's to generate pulses of adjustable
widths and phase relationships. ICl is the heart of a
ramp generator which feeds two variable window
comparators formed by IC2A -IC2B and IC2C -IC2D
respectively. The voltage on pin 1 of IC2A ramps up
as Cl charges through R 1· When this voltage exceeds approximately 5 V (the potential on pin 2 of
IC 1N , the output of IC 1A goes HIGH, forcing IC 1Band
IC1C LOW. Cl is quickly discharged by IOL of IC1B,
and the comparators reset to their normal state QC1A
LOW, IC1B and IC1C HIGH).
13-169
III
AN76-7
..... Siliconix
incorporated
~
+10 V
Dl
lN914
~
lN914
16
R5
550 k
Cl
RSET
100
2
k.n
>",13,+--oJlJl
..:::r:.. 0.001J1~
I
I
100J1s lms
As the ramp rises. its value passes through the two
windows defined by the differences between the voltages on R4 and Rs in the case of Pulse Generator
13-170
10V.,
.,
OV.J L-J L
~
~
AN76·7
Silica nix
incorporated
REFERENCE PIN 2 IC 1
CAPACITOR
VOLTAGE
RAMP
~~=---+-------::::II~~-Ir----- ~m~6N2CE
REFERENCE
~P~IN~1~I~C2~:j::t=::~2f~~-+
_ _~_~~~~~_ _ _~_~~~r_
REFERENCE
PIN 41C2
REFERENCE
PIN 61C2
CLOCK
cp1
CLOCK
cp2
350 Jisec
t=O
Figure 16. Waveforms of the Two Phase Pulse Generator
+5V
RSET
100 k.tl
-12 V@5mA
R3
560 k.!l.
Figure 17. A Regulated DC to DC Converter
Figure 17 is a low power DC to DC converter obtained
by adding a flyback circuit to the square wave oscillator. Operating frequency is 20 kHz to minimize the
size of L 1 and C2. Regulation is achieved by zener
diode D2; when the output is less than -12 V, the
zener breaks down and discharges C1 slightly which
reduces the duty cycle of the oscillator below 50%.
Maximum current available before the converter
drops out of regulation is 5.5 mA at an overall efficiency of 71 %. With no load the converter draws
590 IJ.A.
Operational Amplifiers
While designed primarily as a comparator, the L161
will perform as an op-amp if proper compensation is
applied. Figure 18 is a simple gain of 100 amplifier
with a gain-bandwidth product of 20 MHz I The primary limitation in the performance is the low slew
rate (0.3 V/lJ.s) imposed by IOH charging CCOMP.
The effects of slew rate and compensation are shown
in Figure 19.
13-171
AN76-7
..... Siliconix
incorporated
~
+15 V
16
RSET
1.2 M
RS
n.
lS kn.
13
>---+--OVOUT
A lower gain amplifier requires a larger C COMP ,
which in turn further reduces slew rate. For this reason it may actually be advantageous in certain cases
to lower the gain by placing a resistive divider at the
input rather than raising R1. Figure 20 shows a 700
microwatt X10 op amp whose slew rate is 0.02 V/l1s
and is 3 dB down at 100 kHz.
+3V
1.
CCOMP
O.OOl,IJ.F
RSET
1.2 M
n.
RS
15 kn.
~13~---+---oVOUT
Figure 18. The L161 as an X100
Operational Amplilier
100
Rl 910 kn.
100 kn.
1.
CCOMP
O.003,IJ.F
..........MAX P-P'OUT
10
Figure 20. A Mlcropower X10 Op Amp
Vo
,
(V)
~VOUT FOR 0.005 V P-P IN
0.1
1K
10K
100K
I - FREQUENCY (Hz)
Figure 19. Frequency Response and
Maximum Output lor the
X 100 Op Amp
13-172
1M
AN7S-S
WY'Siliconix
incorporated
~
DG300A Series Analog
Switch Applications
Thomas J. Mroz
Revised December 1984
INTRODUCTION
To round out its analog switch line, Siliconix has introduced the DG300A to DG307A analog switch family.
The DG300A to DG307 A switches were designed to
approach the industry standard DG180 family of JFET
switches in performance while keeping the economy
and low power of CMOS circuitry, and offer fast
switching (typically < 150 ns) and low ON resistance
« 50 n). Four switch functions, (dual SPST, SPDT,
dual DPST, dual SPDT) are offered with TTL or CMOS
compatible logic input options. The low ON resistance, fast switching speed and low power of these
switches makes the DG300A family an excellent
choice for sample and hold, digital-to-analog converters, and multiplexing elements as well as other
applications requiring low offsets, fast charging of
capacitors and fast switching of analog signals. The
SPDT functions offer break-before-make action which
aids in simplification of system design.
DG300A Family Switch Structure
Figure 1 shows a partial schematic of a DG300A
switch.
Device Q1 along with the Zener diode provide the input protection. This is accomplished by Q1 being
turned off whenever the input voltage exceeds the
positive supply (V+) and by the Zener breakdown
whenever the input goes more negative than
V+ -VZENER' Q2 and Q3 form the first input buffer
and are designed to set the proper input threshold.
The DG300A to DG303A thresholds are typically between 1.5 and 2.5 V and are designed to interface
with TTL gates employing pull ups to +5 V. These
switches can also be driven from CMOS gates using
5 to 15 V supplies. If 15 V CMOS drive is available,
faster switching can be accomplished by using the
CMOS input DG304A to DG307A switches.
DG304A to DG307 A switch inputs have thresholds
typically between 4 V and 6 V with ±15 V supplies and
are designed to interface with inputs switching between ground and the +15 V supply. Q4 through Q15
form additional buffers and create the necessary
driving voltages for the switch devices, Q16 and Q19.
Q17 and Q18 are referred to as being body snatchers, not because of midnight escapades, but because they connect the body of Q19 to either its
source or the negative supply. This reduces the ON
resistance and the OFF leakage of this device.
V+
SOURCE
CONTROL
IN
GND o-~------~----~
DRAIN
VINPUT
PROTECTION
LOGIC INTERFACE
AND SWITCH DRIVERS
III
ANALOG SWITCH
Figure 1.
13-173
....,. Siliconix
incorporated
AN76·6
~
PERFORMANCE CHARACTERISTICS
Switching Time
In measuring switching time it is important to remember that the turn-off time as seen at the load is highly
dependent on the load time constant. The switching
time test circuit is shown in Figure 2 below.
a high impedance. high capacitance load such as
that shown in Figure 3. which is the input of a summing amplifier having some noise filtering. it may be
necessary to add a second switch (Figure 4) for
rapid discharge of the filter capacitor thus preventing
offsets from occurring at the summing amplifier output.
IC,
LOGIC "1"= SWITCH ON
LOGIC INPUT
~~~~~~~~~
t r < 20 ns
t,< 20 ns
O V - - - -J
VA 2
VOUT
OG300A
OR
OG304A
~------_t--~~4=~----90%
SWITCH
OUTPUT
-SW.
R.
10%
OV - - - - - t - . . J
tON
Figure 3. Summing Amplifier
+15 V
v+
SWITCH
OUTPUT
S
I
I
I
_oJ
D
vo
RL
300n.
35pF
I!L
VOUT
GND
2X OG303A OR OG307A
Figure 2. Switching Time Test Circuit
Figure 4. Improving Summing Ampllfler
Turn-on time in the circuit shown in Figure 2 is governed primarily by the logic delay path and the
rOS(ON) of the switch. The rOS(ON). CLOAO time constant is normally shorter than the RL CL time constant. The two time constants are:
rOS(ON) x RL
------'=rOS(ON) + RL
xCL for tON and RLxCL for tOFF
These two time constants determine rise and fall
times of the analog switch. When the switch is driving
13-174
Channel ON Resistance
Another important specification of an analog switch is
the channel ON resistance. rOS(ON). The rOS(ON) of
the DG300A family of switches is typically below 40 n
over the operating temperature range.
The two figures below show variations of rOS(ON) with
respect to temperature (Figure 5) and supply voltage
applied to the switches (Figure 6).
~
~
AN76-6
Siliconix
incorporated
60
V+ = ~1S V
V- = -15 V
A: 125°C
B: 25°C
C: -55°C
50
rOS(ON) 40
30
20
---
~ ...........
10
-15
Figure 5.
130
110
90
............
..........
-10
A: V+
B: V+
C: V+
0: V+
E: V+
F: V+
The variation of rOS(ON) with respect to the analog
voltage is due to the variation in the gate-source voltage of the "ON" switches as shown in Figure 7.
-
~
--
~
-
B
.............
~
0
Vo(V)
5
~
10
15
rOS(ON) vs.V o and Temperature
=
=
=
=
=
=
SV,
8 V,
10 V,
12 V,
15 V,
20 V,
V-=- SV
V- = - 8 V
V- = -10 V
V- = -12 V
V- = -15 V
V- = -20 V
-15
-10
Figure 7.
AI\.
VV
50
10
-25
~
-5
rOS(ON) 70
.0.
30
devices is determined by the supply voltages. Thus
the change in rOS(ON) is proportional to the change
in supply voltage.
T A = 25°C
~ ~ 0~o
- ....
......... 1-
-15
-5
E-
'/"" .....E
0
5
15
25
VO(V)
Figure 6. rOS(ON) vs. Vo and Power Supply Voltage
As shown by Figure 5, rOS(ON) increases as temperature increases. This is a typical FET characteristic due to the decreasing conductivity of silicon as
temperature increases. This decrease in conductivity
is due to the shortening of the mean free path seen
by the majority carriers of the device. The change of
switch resistance with respect to temperature is approximately 0.1 ruoe.
Figure 6 also shows rOS(ON) variations with respect
to analog signal voltage as a function of supply voltages. Supply variations are important because the
maximum gate drive available for the switch output
-5
0
+5
+10
SOURCE VOLTAGE (V)
+15
Resistance vs. Source Voltage
of P-Channel and N-Channel FETs
In Figure 8, the complementary output pair (for illustrative purposes) is shown in a very basic schematic.
When the switch is ON, G1 is tied to the negative
supply and G2 is tied to the positive supply. V01 =
VS1 =VS1 =VS2 . In order to understand the variation of rOS(ON) with respect to analog voltage, the
complementary pair will be broken apart and the
rOS(ON) of each device with respect to analog voltage examined.
P-CHANNEL
III
N-CHANNEL
Figure 8. Complimentary Output Oevlces (Simplified)
13-175
WY'Siliconi\(
incorporated
AN76·6
As Figure 7 indicates. the N-channel device with Its
gate tied to +15 V. begins to turn ON as its source
voltage drops a threshold voltage below +15 V. Thus
as the analog voltage decreases from +15 V to
-15 V. VGS increases from 0 V to 30 V. thus increasing the channel conductivity. The P-channel device
has its gate tied to -15 V. thus as the analog signal
increase from -15 V to +15 V. itsVGS goes from 0 V
to -30 V. This results in a decreasing channel resistance. The switch resistance is the parallel combination of these two devices and the bottom curve in
Figure 7 results.
~
RUMIT
CHA
... ~RAG~E.ArL-~~______~
V+O
CHARGING
DISCHARGING
CAPACITORl
RL
DISCHARGE
DISCHARGE
(TTL INPUT)
CHARGE
(TTL INPUT)
APPLICATIONS
Figure 9. Using Current Limiting Resistors In Capacitive
charge/Discharge Circuits
The DG300A series of analog switches. having fast
switching and low rDS(ON). lend themselves to applications such as sample and hold and high speed
multiplexing. Low rDS(ON) also means small offsets
when switching integrators or amplifiers. Nearly constant ON resistance also means lower distortion when
switching into lower impedance loads.
r~RESET
C
-15 V
10
Charging and Discharging Capacitors
VO= 1/RCIVINdt
I
~
When charging or discharging capacitors. it is important not to exceed maximum ratings of the switch.
Current through the switch must be limited to 30 mA
continuous or a 100 mA pulse for 1 millisecond or
less having a 10% duty cycle. Exceeding maximum
ratings could mean poorer reliability than could otherwise be expected. One method of preventing excessive current is by using current limiting resistors in
series with the switch as shown in Figure 9. If voltage
differentials between the switch input and the capacitor are small. these resistors may not be necessary
because the switch resistance itself would be sufficient to limit current.
In the integrator of Figure 10. RL controls the discharge rate of the capacitor. During reset to zero V.
the reset switch is closed and the start/stop switch is
open. Opening the start/stop switch with the reset
open will hold the output of the integrator at its present value.
13-176
START/STOP
R
s
50
< RL < 100 FOR 15 VOLT OUTPUT SWINGS
50.0.
Figure 10. Integrator with Analog Reset and
Start/ Stop Capability
Charge Cancellation
Figure 11 shows a sample and hold circuit using the
DG303A dual SPDT switch. Any analog switch when
opened will inject charge into the source and drain
nodes due to gate to source and gate to drain capacitance. This charge when injected into a sample
and hold capacitor will create offset errors in the
sample and hold output during hold. This error can
be eliminated using another switch to Inject charge
into a small storage capacitor (200 pF) during the
same period which is then subtracted off during the
hold period.
H
AN7S-S
Siliconix
incorporated
~G~C ~C
-15 V
+15 V
-15 V
D~S\....3b
\.VA
A
BOTTOM VIEW
#-J""""t--.--\-------t--",,10"'--0 VOUT
DG307A
7
+
LOGIC
CONTROL
LOGIC 1 = CHANNEL 2
LOGIC 0 = CHANNEL 1
Figure 12. Basic Switched Differential Amp
13-177
AN76-6
...... Siliconix
incorporated
~
+15 V
+
-15 V
+15 V
75 k.o.
75 k.o.
+15 V
-15 V
+15V
75
k.O.
75
k.O.
DG307A
+15 V
7
30 pF
+
13
2
POSITION 2
~ ~1"V--1--4"61-~
i
15
'-ir-f-'-'11_+
I
..J
-15V
:
k.O.
512+
POSITION 1
30 pF
-15 V
DG305A
7
CK
Figure 13. 2-Channel to 1-Channel Chopping Differential Amplifier With Position Adjustment
The high switching speed of the DG304A is taken advantage of in the 64-channel two level multiplex system of Figure 14. This circuit employs 4 each
DG506A 16-channel multiplexers as the first MUX
level and uses the high speed DG304A's in the second level to switch between DG506A outputs. CMOS
digital logic forms the address logic for the multiplexers as well as the DG304's.
As one multiplexer is being sampled at the output,
the other multiplexers are being switched to the next
address line. This allows the overall system transition
time to be shortened from 1.5 /-ls to 0.25 /-ls. The
two level system also lowers output node capacitance and output leakage (refer to Reference 5 for
details).
13-178
Battery or Low Power Applications
The DG300A series of switches are inherently low
power and are ideal candidates for applications using
battery supplies. Figure 15 shows the variation of device power dissipation versus the switching frequency of the switch. It can be seen that in low frequency switching the power dissipation is negligible.
One application for which this switch is ideal is in
autoranging circuits for battery operated Digital Volt
Meters.
Figure 16 is the schematic of a binary addressed amplifier in which the gain increases by decades as the
binary input decreases from 1,1 to 0,0. Its minimum
gain, as shown in the table, is 1 and its maximum
gain is 1000. Since the switch is static in this type of
amplifier the power dissipation of the switch will be
less than a tenth of a milliwatt.
AN76-6
Siliconix
incorporated
H
+15 V
S
A COMPARISON OF 1 LEVEL vs 2 LEVEL
54-CHANNEL MULTIPLEX SCHEMES
1 LEVEL
1.5jJ.S
160 pF
40 nA
TRANSITION TIME
OUTPUT CAPACITANCE
OUTPUT LEAKAGE
12j1,.113 127
o.ll!
S,
2 LEVEL
0.25jJ.S
120 pF
16 nA
+l
1
JV
14
INVERTERS~
C04009
EN
'l
+15V
.3
1~2
' 1
-2
y
V
CLOC~
I~
~
J
A
0,
O2 5
0,
I.
RESET
I
+lY ,j1,.Ni
V
1 12 ':' 13 27
V, GNOVREF V2
VSE
S:~
1
I
+lr
~
....
9
~f"4
0.1..-
CLOCK
IN
~
r-
O.
O.
17
S.~
14
.~
G.
12
y
0,
3
MUXl
OGS06A
--r-
1 CLOCK
IN
6
AD A, A2 A, EN
117r6 15 14~
0,
~ RESET
VSS
'["8
+l
.,JLJL
ON
ON
1/4 C04001
13
9~
'4
J;'
6
8
-15 V
J~l~t:V
13 27
s.0f2
y
~EN
.2~
".~
~ 1L
+lY
1 12 ':'
MUXl
OG506A
1
CLOCK PHASES TO OG300
LOGIC INPUT
ON
ON
~11
IN
0G304A
.~
•••• .,,02
11 S2'"
V2
GNO
s.~ v, GNovREF v.
1
ON
2
(DIP PINOUT SHOWN)
02
1/2 C04520
'3
.,----...fLON
0,
0,
10
7
S63~
4 S,
6 -..;:
INY •••••
9
4
I
16
2 EN VOO OD
7
14
V,
28
1
V
1/4 C04001
+lr
V, GNOVREF V 2
1
6
-15 V
OUT
V
+lY,rilJ
1 12'" 13 27
2
.,!,.
RESET (HIGH)
ENABLE (LOW) 11
1'8
1:
--0
1
+l
~
'4
,<>f!!
a
~
1~
S7
RESET
:t>....~
11T615 14~
,.
1/2 C04520
RESET
28
IN, OG304A
IN2
2~ 9
11 S2
'.i
GNO
V.
An A, A. A. EN
0 0 11
0,
6_ 4
02
S62~
~EN
1/4 C04001
.f
1/21~4027
CLOCK
IN
MUXl
OG506A
1
O~
+lr
14
0,
V,
.... ....•:
t;V
4 S,
1>-6
1
-
SET
EN
1514~
S.
.L" r-
.....§. K
A
A
11T6
00 3
.,!,.8
13 CLOCK
IN
112 C04027
9
SET
11
Q
K
RESET VSS
112
'-r-2
S61oJ.j
1/2 C04520
r-
~J
o,~
MUXl
OG506A
I
16
VOO
+lr
116
VOO
1
1
1
1 CLOCK
IN
2~
V, GNOVREF V2
S~~
INPUTS
(1-64)
1/4 C04001
NC -15 V
....
9 CLOCK
IN
..... 10
D.
~ I-
1
V
S64
OD
I
0U Ao
-r
A, A2 A3 EN
1T615 14~
0,
O2
III
0,
L...-...1.§ 1/2 C04520
RESET
, TO INl-4 OF 0G304' s
FIgure 14. 64-Channel 2-Level Multiplex System Using DG304A as High Speed Switches
13-179
~
~
Siliconix
incorporated
100
10
I=V+
'r-v'r-T A
'r-Vs
R
f-- -
I-
-
- +15 V
- -15 V
= 25°C
= 15 V
=2K.o.
,
I
D~300A-303A.
'I'
0.1
1
10
100
~L
If
DG304A-307A I
I
J
1 k 10 k 100 k 1 M
LOGIC SWITCHING FREQUENCY (Hz)
50% DUTY CYCLE
Figure 15. Device Power Dissipation vs.
Switching Frequency
10kA
10kA
10kA
100kA
1M.n.
DG304A
BINARY INPUT
GAIN
11
10
01
00
10
100
1000
1
7
AO
Figure 16. Low Power Binary to 10 n Gain Low Frequency Amplifier
The low power of the DG307A also makes it ideal for
use with the low power programmable triple op amp,
the L144, in an active filter. Figure 17 shows the use
of the DG307A in a switch able center frequency ac-
13-180
tive filter, allowing a decade change in center frequency. Additional information on the L144 and the
active filter circuit can be found in References 6 and
7.
AN76-6
...... Siliconix
.J;lI incorporated
RF2
201dl.
HIGH PASS
OUTPUT
C1
O.OOBJiF
+15 V
-15 V
LOW
PASS
OUTPUT
+v
+15 V
1/2 DG307A
1/2 DG307A
7
CMOS LOGIC DIGITAL INPUT
HIGH = 7 kHz
LOW =700 Hz
750 Idl.
Q = 26, H 0= 26,
F 0 HIGH= 7kHz,
F 0 LOW = 700 Hz
QUIESCENT POWER DISSIPATION
DG307A = 120JiW
L144
= 18 mW
BAND PASS
OUTPUT
Figure 17. Low Power Active Filter with Digitally Selectable Center Frequency
Table 1
Design Procedure for the State Variable Active filter
Given: f 0 (Resonant Frequency).
H 0 (Gain at the Resonant Frequency) and Q 0
STANDARD DESIGN
(Assumes Infinite Op-Amp Gain)
1.
Chose Cl = C2 = C, A CONVENIENT VALUE
IF HO IS UNIMPORTANT (i.e., GAIN CAN BE
ADDED BEFORE ANDIOR AFTER THE FILTER).
CHOOSE K 1
=
=
5.
3.
THEN R
4.
CHOOSE Rll
2'IT
X
= R12 = KR.
WHERE R11. R12 = A CONVENIENT VALUE
AND K
=
HO
QO
LET R 01
= A CONVENIENT VALUE
fO x c
6.
ROl
THEN R02
= --:-::(2:-+---:-:K::-)"":x:":'Q=-0---1-
=
A ( fO )
THE NOMINAL OP AMP GAIN AT
THE RESONANT FREQUENCY.
=
GBWP THE NOMINAL GAIN-BANDWIDTH
PRODUCT OF THE OPERATIONAL AMPLIFIER
13-181
AN76-6
...... Siliconix
incorporated
~
+15V
-15V
.----_~
-15 V
OG304A
TO
307A
SERIES
SWITCH
+
14V -=-Bt
l
14 V-=- B.
~
7
B t • B. - MALLORY RM411
14 V 160 MAH
Figure 18. Long Term Supply Standby
+15 V
-15 V
TO
I
100,ll.F
307A
SERIES
SWITCH
7
aV=5VOLTS
TYPICAL TIME = 5 MIN
Figure 19. Short Term Supply Standby
An advantage of the DG304A to DG307A family of
switqhes, due to their low power consumption, is the
13-182
Battery lifetime should be well over 1 year with continuous standby.
Thermocouple Applications
Because silicon in contact with aluminum creates a
thermocouple, low power dissipation by the integrated analog switch will mean lower offset voltages
added to thermocouple voltage. Thus, lower power
dissipation translates into better potential accuracy.
The DG300A series of analog switches do quite well
in this type of application. Figure 20 shows a typical
schematic of a thermocouple switching circuit. It is
necessary to switch the thermocouples differentially
in order to cancel any thermal offsets due to the
switch.
Single Supply Operation
OG304A
+
ability to use batteries or capacitors to supply
standby power to the switch. In this way errors at
analog output and shorting of signals can be avoided
when supply power fails. This method would also prevent loading of the analog signal by the switch which
could prevent the use of the signal in other portions
of a system. Figure 18 and 19 show methods of implementing standby power.
The DG300A series of analog switches will switch
positive analog signals while using a single positive
supply. This will allow use in many applications where
only one supply is available. The trade-offs (or performance given up) while using single supplies are:
1) Increased rOS(ON); 2) slower switching speed.
Typical curves for aid in designing with single supplies are supplied in Figures 21 to 23. As stated in
the absolute maximum ratings section of the data
sheet, the analog voltage should not go above or below the supply voltages which in single supply operation are V+ and 0 V.
AN76-6
Siliconix
incorporated
MATERIAL B
TCI
PIN 14 -+15 V
PIN B --15 V
PIN 7 - GNO
DG306A's
'-~~-/.'---------------------,
MATERIAL A
DG306A
MATERIAL A
MATERIAL B
-4______+-____________-'
TC3'-~~~~__~______________
MATERIAL A
REFERENCE
JUNCTION
oOC
+15 V
MATERIALB
CKo
CK,
CK.
Figure 20. Thermocouple Multiplexing
5
170
150
II
130
rOS(ON)
.n.
110
VI
h
T A = 25°C
...
~
11
-UN
~
50
30
10
-"
o
2
.....
4
B
10
1
\
1
II
1
r-r-
YI-rrl6
4
2
=+10V
~
V 2 =OV
TA = 25°C-
3
V+=+jI
90
70
~OV
12
14
"
o
VA - ANALOG VOLTAGE (V)
Figure 21. rOS(ON) vs. Analog and Positive
Supply Voltage With V- = 0 V
- '1
tON
tOFF
5
10
15
POSITIVE/NEGATIVE SUPPLIES (V)
Figure 22.
Switching Time vs. Power Supply Voltage
13-183
AN76-6
..-r' Siliconix
~
V- = 0 V
6 T A = 25·C
+--:1--+--:1""
Single Supply Range:
(V- = GND)
V+: +5 V to +25 V
Analog Signal Range:
V- :s; V ANALOG :s; V+
51--1--+--+--~
VT
(V)
incorporated
41---1--+----:""
31--1--1
o
5
15
10
V + - POSITIVE SUPPLY VOLT AGE (V)
Figure 23.
Input Threshold Voltage vs. Positive Supply
AMPLIFIER 2
r';;-sv"715vl
I
I
I
I
II
I
I
I
I _
+15 V
t-tl-------t~~~~
I
I
I
I
OUTPUT
AMPLIAER
r----.,
2
I
+15 V
_ I
1..----.1
VOUTI
1-t--r..
VIN1o-jl-------7
I
I
I
I
I -
-
1..----.1
AMPLIFIER 1
+5V
+5 V
I
I
-=+5V
TTL
INPUT 1
4idl.
4
114 SN7402
Figure 24. Switching Single Supply Amplifiers Using the DG300A
13-184
I
I
I
I
I
I
I
5
6
TTL
INPUT 2
AN76·6
trY' Siliconix
~
incorporated
+15 V
50k.O.
VAl (AC) O---"IM,..-+-..,
VOUT
5k.O.
vA2(AC) o---"IM,..-+-.......
3
10 k.O.
Figure 25. Single Supply Op Amp Switching
As shown in Figure 26 when switching capacitor-coupled analog signals. the coupling capacitor should
appear either before or after but not on both sides of
the switch. This is necessary to keep a positive bias
on the switch drain and source when the switch is
turned on.
OUTPUT AMPLIFIER
r';:;5V~15VI
I
I
I
I
I
I
I
I
I
I
I
1
__
L. _ _ _ _ _ ..1
AMPLIFIER 1
r-~;V-+151
I
I
I
I
I
VIN1o-f1
I
I
IL. _ _ _ _ _ ..1
.----+""'6'1---D_
7
8
Cc
_
+15 V
CKo------'
DG304A
3
CK ~-,-,,-,-.-..-'
I
I
...J
AMPLIFIER 2
r-----'
I +15 V +15 vI
I
I
I
I
t---+-+I-f
I
I
I
I
I
13
IL. ':_ _ _ _ _ ..1
L<~~---+-OCK
Figure 26. Proper Methods for Interfacing Capacitive Coupled Outputs to Analog Switches
13-185
AN76-6
Siliconix
incorporated
+1S V
CMOS LOGIC
GAIN SELECT
HIGH = 10K
GND
180 kll.
20 kll.
Figure 27. Low Power Non-Inverting Amplifier with Digitally Selectable Inputs and Gain
20 kll.
200kll.
10K
1K
+1SV
VOUT
-1SV
+15 V
8
4
2
11
13
6
-15 V
-
DG301A
+5V
7
1 kll.
TTL LOGIC
GAIN SELECT
LOW = 1K
Figure 28. Low Power Inverting Amplifier with Digitally Selectable Gain
13-186
AN76·6
Siliconix
incorporated
-15 V
+15 V
VIN
o-.....-----::-I---()... ...-+':""
RSE
3M
>-+--oVOUT
DOO03A
7
TTL LOGIC
DIGITAL INPUT
LOW = NON-INVERTING
Figure 29. Polarity Reversing Low Power Amplifier
+lSV
+15 V
-15 V
2
DIFF. INA
5
Av = 10.4
Av
CMOS LOGIC
INPUT
SELECT
HIGH
DIFFERENCE
INB
=
=101
4
2
RS
11
7SkA
13
6
DOO05A
7
1/3 L 144
GND
VOS
+15 V
RS
7SkA
1/4 C04001
CMOS LOGIC GAIN SELECT
HIGH = AV = 101
00005
00006
Ll44
-lSV
= 60p,W
-lSV
= 120p,W
=7.5mW
R SET programs L144 power dissipation, gain-bandwidth product.
Refer to AN73-6 and the L144 data sheet
III
Voltage gain of the Instrumentation amplifier Is:
Av
Figure 30.
=1 +
2R2
Rl
(In the circuit shown, AVl
= 10.4,
AV2
= 101)
Low Power Instrumentation Ampllfle Digitally Selectable Inputs and Gain
13-187
..,. Siliconix
incorporated
AN76-6
REFERENCES
1. Lee Shaeffer, "CMOS Analog Switches - A
Powerful Design Tool,· Siliconix Application
Note AN75-1, July 1975.
~
4.
"Siliconix Analog Switch Data Book", June
1976.
5. J. Jenkins, "IC Multiplexer Increases Analog
Switching Speeds", Siliconix Application Note
AN73-2, April 1976.
2. Gary Dixon, "Analog Switches in Sample and
Hold Circuits," Siliconix Application Note
AN74-2, Jan. 1976.
6. Marvin K. Vander Kooi, "L144 Programmable
Micro-Power Triple Op Amp", Siliconix Application Note AN73-6, Jan. 1975.
3. Gary Grandbois, "Build an Autoranging DMM
with the LD130 AID Converter," Siliconix Design
Aid DA76-3, June 1976.
7. Lee Shaeffer, "Op Amp Active Filters - Simple
to Design Once You Know the Game", EDN
Magazine, April 20, 1976.
13-1138
AN75·1
fI"F' Siliconix
~
incorporated
CMOS ANALOG SWITCHES A POWERFUL DESIGN TOOL
Revised January 1988
INTRODUCTION
thresholds the peaks will not be symmetrical. As the
switch heats up the resistance increases 0.5%/ o C.
Siliconix CMOS analog switches combine large voltage handling capability, low power dissipation, low
leakage, and direct TTLICMOS interface capability for
maximum design flexibility. In addition, a family of
multiplexers is available which provides binary decoding on the chip for system simplicity. This application
note describes the Siliconix CMOS DG20X switch
family and DG50X multiplexers. It offers circuits
which illustrate their capabilities.
I
I
\
This problem is overcome by connecting an N-channel FET in parallel with the P-channel device. The Nchannel gate is tied to the positive supply, and the
FET is turned on hardest when the source is most
negative. The resistance curve of the P-channel and
N-channel FETs in parallel is shown in Figure 1.
The resistance curve is nearly flat for V- :::;; Vs :::;; V+
(only CMOS is capable of this) but some resistance
variation is normal. 20% peaking is typical for ±15 V
power supplies, with greater peaking at lower supply
voltages. If the P- and N-channel FETs have different
-15
o
vo-J :r
....
+15
to
\
vo-Jll :
tol
sl
0
I
\
\ RESISTANCE
"
,
/
(n.)
-
/
;'
........
;'
' .....
_-1--_-==--- ---
Properties of CMOS
CMOS (Complementary Metal-Oxide-Semiconductor)
combines P-channel and N-channel enhancementmode FETs in a common substrate. P-channel enhancement-mode FETs have a negative threshold
voltage (the gate must be several volts more negative than the source or drain in order for current to
flow between the source and the drain), while Nchannel FETs have a positive threshold (Figure 1).
When a P-channel FET is used as a switch (standard
PMOS devices), the gate is held at the negative supply when in the ON condition, and the FET conducts
for most voltages applied to the source. However,
when the source voltage approaches the negative
supply, the resistance approaches infinity. The result
is a dead-band equal to the threshold voltage of the
FET.
N-CHANNEL
P-CHANNEL
S
Vth
(P)
~I
-15
-10
",
j
I
-5
0
+5
~N)
j
+10
+15
SOURCE VOLTAGE (VOLTS)
Figure 1. Resistance vs. Source Voltage of P-Channel
and N-Channel FETs
Because the gates of the P- and N-channel FETs are
internally switched to opposite supply voltages, one
would expect that leakage currents and switching
glitches would cancel whenVs = O. This would indeed
be true if the FETs were identical except for polarity.
However, because the conductance of the N-doped
silicon is 2.5 times greater than that of equally doped
P-type silicon, it is a practical impossibility to make
the leakage currents and capacitances equal for
FETs of equal resistance (the P-channel is physically
2.5 times larger than the N-channel). Therefore, cancellation takes place at some intermediate voltage.
Because the measured leakage is the P-channel
leakage minus the N-channelleakage, small variation
in the absolute value of either can make a large
change in the difference. Since small amounts of impurities can greatly influence the leakage, both the
magnitude and polarity of the leakage measured at
the source or drain will vary greatly from unit to unit,
and will depend on the analog voltage and the temperature. Even though the leakage is unpredictable,
it is still less than a comparable PMOS or bipolar
switch.
13-189
III
..r Siliconix
incorporated
AN75·1
~
jV
IN
~f
output is tied to the negative supply through rDS(ON)
of the N-channel FET, while the P-channel device
draws no current. If the input is changed to a negative voltage the state of the FET is reversed, pulling
the output high. When a CMOS device is turned ON,
the load is turned OFF; this overcomes a major disadvantage of PMOS structures, where the load is ON
at all times and considerable power is drawn when
the FET is ON.
P-CHANNEL
OUT
N-CHANNEL
-v
The DG201 A circuit can be divided into 6 sections.
There is the input comparator, the bias circuit and
voltage reference, the level shifter, buffer and inverter and the switch circuit. Figure 3 is the DG201A circuit.
Figure 2. A CMOS Inverter
In addition to a large analog voltage capability, a second advantage of CMOS is low power dissipation.
Figure 2 shows a digital inverter with virtually no static
power dissipation. When the input is pulled high, the
N-channel turns ON and the P-channel OFF. Thus the
V REF CIRCUIT
GATE BIAS CIRCUIT
v+
VR
~~
>
~
AA
v
.--GND
I
==
I
v-
L--
INPUT, SWITCHING CIRCUIT
6L
c:
,t"
IN1
-¥
=*=
I
~V~
V
'\
I 1
'i-
-----:.-
-i'
r.~
-
-:-!,
I,!=;
f' '4
~J- ~,
f-i'
G~
I
kJ Y~ Y~
Figure 3. Schematic of a Typical CMOS Switch Channel (DG200A and DG201A)
13-190
Sl
L:-!I
r=;'
IC
'i-
'i-
I..:-l,
~~
r~ ~~
01
AN75-1
.... Siliconix
incorporated
~
The input comparator is a differential amplifier whose
threshold is set by the voltage reference, a 10 to 1
voltage divider, which is further stabilized by the
"bias circuit". The threshold voltage is derived from
a voltage divider and varies as V+ varies. Several
feedback schemes are used to sharpen the switching
point.
The level shifter buffer and inverter are CMOS and
consume virtually no power. The inverter is necessary to drive the parallel connected CMOS switch.
In the switch two transistors are used to drive the
body of the N-channel MOSFET . When ON, the body
is tied to the N-channel source and when OFF, it is
tied to V-. This eliminates any modulation of ON
switch resistance and when OFF, reduces leakage.
Because only the voltage divider and comparator differential amplifier draw any current other than leakage, the circuit consumes very little current.
All of the multiplexers (DG50XA, DG52X, etc.) contain decode circuitry enabling a binary logic input to
select one of 4, 8, or 16 channels. Each multiplexer
also contains an ENABLE-INHIBIT control, which shuts
the device OFF when in the INHIBIT mode. This allows
the common connection (drains) of several multiplexers to be paralleled, and the units can then be
enabled one at a time. This is useful when more than
16 channels are involved. Also, when the device is
inhibited, its power dissipation is typically less than
1·?.'l'!·j
OXIDE
k~/;1
METAL
one-fourth the normal dissipation, for low total system power dissipation.
Latch-Proof Operation
Latchup was a thorny problem in first-generation
CMOS switches. A cross section of two CMOS FETs
(Figure 4) shows both a PNP and an NPN structure,
which is connected as an SCR (PNPN). Under abnormal conditions, one or more of the PN junctions becomes forward biased, activating the bipolar transistor. This in turn activates the SCR, which appears as
a short between the substrate (positive supply) and
ground or V-. Since the product of of the NPN and
PNP betas is often greater than 1000, this short
would persist until power was removed or until the
device burned up. When 200 ohm resistors were
placed in series with the power supply leads, device
destruction was prevented; however, only removal of
the power supply would return the circuit to normal
operation.
By using a .. buried layer" configuration (Figure 5),
Siliconix has reduced the product of the NPN and PNP
betas to less than one, making latch-up impossible
under any normal circumstance. The switches retain
their desirable features such as low leakage, high
OFF isolation, and high breakdown voltage. In addition, the latch-proof switches now have a much
higher current capability (20 rnA continuous, up to
100 rnA peak of the DG200A).
V+
V+
V-
P-CHANNEL FET
B
N-CHANNEL FET
D
G
S
LP~
P-WELL
__ y_J
L~+J
I
I
L _________ L _____
N- SUBSTRATE
I
R2
I
~---~
VEQUIVALENT
CIRCUIT
Figure 4. A Cross Section of Two CMOS FETs Showing the Parasitic Transistors and Equivalent Circuit
13-191
W'JP'" Siliconix
AN75·1
~
incorporated
OXIOE
METAL
v-
P-CHANNEL FET
N-CHANNEL FET
v+
N- SUBSTRATE
Figure 5. A Cross Section of the Sillconix "Buried Layer"
General Switching Applications
One of the significant advantages of the CMOS structure is its ability to handle large analog voltages,
since only CMOS can allow signal swings to the
power supplies. A logical application is switching the
outputs of operational amplifiers. The entire system
can be run on ±15 V, and the full output of the op
amps (typically ±14 V) can be used. In most cases it
is advantageous to switch at the relative low impedance output of an op amp rather than at the summing
junction, to minimize the effects of switch capacitance and leakage.
Figure 6 shows a novel multiplexing application. It is
an adapter that allows 4 inputs to be displayed simultaneously on a single trace scope. For low frequency
signals «500 Hz) the adapter is used in the "chop"
mode at a frequency of 50 kHz. The clock may be
run faster, but switching glitches and the actual
switching time of the DG201 A limit the maximum frequency to 200 kHz. High frequencies are best viewed
in the alternate mode, with a clock frequency of
200 Hz. When the clock is below 100 Hz, trace flicker
becomes objectionable. One of the 4 inputs is used
to trigger the horizontal trace of the scope.
Figure 7 shows a variable low-pass filter with break
frequencies at 1, 10, 100 and 1 kHz. The break frequency is expressed in (1):
13-192
fc
211 Rs Cx
(1)
The low frequency gain is
AL
= -Rs = 100 (40 dB)
R1
(2)
A second break frequency (zero) is introduced by
rOS(ON) of the DG201A, causing the minimum gain to
be
AMIN -
rOS(ON) = 100 n = 0.01
R1
10kn
(3)
a maximum attenuation of 40 dB (80 dB relative to
the low frequency gain).
The amplifier shown in Figure 8 has digitally-programmable gain and inputs. The DG200A "looks" into the
high input impedance of the op amp, so the effects
of rOS(ON) are negligible. The DG201A is also connected in series with rlN and is not included in the
feedback dividers, thus contributing negligible error
to the overall gain. Because the DG200A and
DG201A can handle ±15 V, the unity gain follower
connection (x1) is capable of the full op-amp output
range (±12 V).
H
AN75-1
Siliconix
incorporated
+15 V
+5 V
13
Vl
DG201A
S 1 3
Sl
1/274C73
1I674C04
a
J
14
Dl 2
14
R
S2
S2
D2 15
11
ALTERNATE
120 k!l.
O.022J1F
200 Hz
S3
S3
D3 10
7
5
6
S4
10
6
-
11
-
-15 V
-
r------------------,I
+15 V
CHANNEL 1 AMPLIFLIER
(IDENTICAL TO 2,3,4)
I
I
I
~~~------------------_r----oTOSl
+15 V
+1!5V
i
lM.o. I
POSITION:
R
-15
(SEE BELOW)
-15 V
v
I
I
I
I
------------------~
Al IS OP AMP WITH SUITABLE BANDWIDTH, SLEW RATE, ETC., FOR DESIRED SIGNALS.
R IS ADDED FOR EXTRA GAIN ACCORDING TO FORMULA VOLTAGE GAIN = 2 + 100 k.o.
R
III
Figure 6, The "Scope Extender" Which Displays Four Channels Simultaneously on a Single Trace Scope
13-193
Siliconix
incorporated
AN75·1
+15V
V1
C4= 150 pF
160
DG201A
7
120
104
SELECT
10
80
-- ......
Av
(dB)
103
SELECT
~ .L~ LJf~ ~
0
.......... ..........
2
1
10
1'7:4'"
............ :..........
""
-40
lC1
SELECT
...~~L-
........... ............ ........... ............
CONTROL
lC2
SELECT
I
....
103 104 .......
102
fCl
40
15
TTL
LM101A
OPEN LOOP GAIN -
...... J
100
1 k
10 k
FREQUENCY - Hz
~
100 kIM
AL(Voltage Gain Below Break Frequency)
=
lM.n.
~~6~
10kA
:~
= 100 (40dB)
1c (Break Frequency)
________________
1
= 2'ITR 3C X
~~VOLrr
1L (Unity Gain Frequency)
8
= r~~(~
Max Attenuation
Figure 7. Active Low Pass Filter with Digitally Selected Break Frequency
+15 V
DG200A
VI
6
+15V
CHl
-15 V .-_1:;3~_ _==~
CH2 2
V2
6
-15 V
GND
3
-::'
GAIN 1(Xl)
GAIN = RF+RG
RG
_______..,
2
3
15
14
10
11
7
6
O-------"ii--- 100 kHz),
some knowledge of the OFF characteristics are helpful. Figure 14 shows the equivalent OFF circuit of a
DG200A and the accompanying graph gives the isolation under the conditions specified. 40 dB isolation
at 6 MHz is good for general purpose video switching. A DG200A can achieve this easily, using the circuit shown in Figure 15 (assuming careful P.C. board
layout). When greater isolation is needed, the circuit
shown in Figure 16 is recommended. The "T" configuration provides over 40 dB more OFF isolation
with only a slight increase in ON insertion loss.
State of Switches
after Command
Command
A2
A1
S2
S1
0
o (normal)
same
same
0
1
OFF
ON
1
0
ON
OFF
1
1
INDETERMINATE
Figure 13.
100
0.1 pF
(S)
2.5pF
2.5pF
(G)
III
Til
IF_
(D)
80
['\.. 75.n.
60
Vs
4.2 K
0.9pF
I
1.3
I~
Vo
I
i'o...
40
....
1-'111 =+15V, V2=-15V
20 I-~GNO= 0
CLOAO= 15 pF, RL = 75.n.
f-i tii IIIi I I
S
1=
MS
1111111
10 6
10 7
f - FREQUENCY (Hz)
100
........
III III
RL = 1 k.o.
80
0.13pF
s<>---tip~p~
60
(SIMPUFIEO)
40
~
....
.
....
~
RL = 10
M.o.
.
.1 11111111
rll1 = +15 V, Vp -15 V
20 I- VGNO = 0, VEN = 0
III
~L?AIOI~ 111~IPF'Y~=1 ~ ~~~S
1111111
1111111
10 5
10 6
f - FREQUENCY (Hz)
Figure 14. Equivalent "OFF" Circuits and OFF Isolations of the DG200 and DG506A
13-197
.... Siliconix
incorporated
AN75·1
~
+15 V
10
.46 dB ISOLATION AT 10 MHz OFF CAMERA
TO ON CAMERA
.40 dB ISOLATION AT 10 MHz, LOAD FROM
EACH CAMERA WHEN BOTH ARE OFF
• 0.5 dB ON INSERTION LOSS
-15 V
NOTE: PIN CONNECTIONS SHOWN ARE FOR METAL CAN PACKAGE.
Figure 16. General Purpose Video SWitch (f = DC to 10 MHz)
DG200A
DG200A
.84 dB ISOlATION AT 10 MHz OFF
CAMERA TO ON CAMERA
• 80 dB ISOLATION AT 10 MHz LOAD
FROM EACH CAMERA WHEN BOTH
CAMERAS ARE OFF
.1.0 dB ON INSERTION LOSS
'--------t------;-- CAMERA 1 SELECT
CAMERA 2 SELECT
DG200A
4
75
n.
Figure 16. Video Switch with Very High OFF Isolation
Figure 14 also shows the high frequency characteristics of the DG506A and a simplified OFF equivalent
circuit. The DG506A has OFF isolation which is constant when working into a capacitive load, allowing
the designer to model the OFF DG506A as a capacitor of nominal value 1.13 pF. Not all sources have
equal OFF isolation, however. 59 has the greatest
isolation, while Sa is worse due to its proximity to the
13-198
drain. Grounding the metal lid on the package (it normally floats) increases the isolation an average of
3 dB.
An in-depth study of switching high frequency Signals
is presented in Siliconix applications note AN73-3,
"Switching High Frequency Signals with FET Integrated Circuits."
AN7S-1
.-y" Siliconix
~
incorporated
Multiplexing
Multiplexing allows a number of signals to be processed simultaneously through a single cable, amplifier, and data conversion system. Numerous industrial
and commercial uses include factories and warehouses where conditions at remote parts of a building can be monitored and sent to a central control
point over a single cable. Airplanes take great advantage of multiplex systems, both receiving and transmitting information from central points with a minimum of wire. Many hotels and motels pipe up to 16
channels of music to each room. The music desired
is selected by the guest in the room. When digitizing
information , the economies are readily apparent between using a $50 multiplex system and a single A to
D converter, as compared to employing a separate
expensive A to D converter for each of several channels.
Figure 19 shows a typical multiplex system intended
to carry one of 8 inputs into a remote location. A 5 V
pulse train is sent down a separate channel to perform timing and synchronizing functions. A 15 V reset pulse is superimposed on the 5 V clock, which is
detected by the MM74COO in the receiver. Using this
system, many remote pOints can be monitored, one
at a time, at any of several locations.
Signal source and the current sink capability of the
power supply are each greater than 20 mA, a resistor
should be connected in series with source to limit the
current.
+15 V
-15 V
DG50BA
LOGIC
OUTPUT
HIGH = SAMPLE
LOW = HOLD
Figure 17. A One of 8-channel Sample and Hold
SOURCE
DRAIN
Often information is multiplexed into a conversion
system which has a relatively slow processing time,
necessitating a sample-and-hold after the multiplexer. Using the DG508A as a sample-and-hold
switch combines both functions, as shown in the
"one of eight sample-and-hold" circuit (Figure 17).
Overvoltage
V1
(POSITIVE SUPPLY)
+
GATE
A number of signals may be sent between two points
simultaneously by making a slight modification in the
receiver circuit (Figure 20). A second DG508A is
used as a demultiplexer, allowing all 8 channels to be
monitored continuously.
DI-S,,---J,,'V'v-'?""'I
+
16V 15 V
~
CURRENT
FLOW
N - SUBSTRATE
CROSS SECTION OF P-CHANNEL FET
r-------------~-----oD
~------------~----_oS
EQUIVALENT CIRCUIT
In certain applications the analog signal may exceed
+15 V, or be present when the power supplies are
off. This is a condition known as overvoltage, and it
can present problems unless certain precautions are
taken.
When the analog voltage exceeds the supply voltage,
the source-body junction will forward bias, as shown
in Figure 18. Current will flow from the signal source
into the supply. If the current source capability of the
Figure 18. Current Paths During An
Overvoltage Condition
If the analog signal is present when the supplies are
off, diodes in series with the supplies will allow the
supply pins to float and prevent excessive current
from flowing. A DG508A with full overvoltage protection is shown in Figures 21 a and 21 b.
13-199
l1li
»
z
...
t.>
~
8
~•
......
TO OTHER
RECEIVERS
+15 V
-15 V
1N914
i5
~.~vn
.....J
7
n
I
GNriJ lnruuumnf lrL
I
IL _________ _
10 kll
'-----'------.J
08 0102030405060708 01
-::"
I
I
TRANSMITTER- - - - - - - -
-
--'-- -- -- -
I
I
-
- - - - - RECEIVER - - -
Figure 19_ A One of 8-channel Transmission System
-
-- -
-
-- -- --
J
~
:j"cn
00·
0=
-'0
"0:::]
~x·
!!.
(D-
a.
~
5'(/)
0=
00'
.... 0
'0:)
QX·
III
r0-
o.
+15V
-15 V
II
+15 V
(,~
u
+15 V
81
-15 V
°
OG508A
+5 V
+15 V
IN914
I
IL _________ _
~ ~7
.,'V
10
k.n
~N~
Os 0102030405 0S070S 01
I
I
TRANSMITTER- - - - - - - - - - - ' - - - - - - - - - - - - - RECEIVER - - - - - - - - - - -
Figure 20. An 8-channel Mux/Demux System
I
-
--
J
»z
~•
......
~
If
I\l
~
iii
rJf" Siliconix
AN75-1
~
+15 V
-16 V
+lSV
incorporated
-16 V
OUT
OUT
•
R 1THROUGH R 8
EXAMPLE: R = 260
=
EXPECTED OVERVOLTAGE -15 V
20 rnA
.n. WHEN
(8) A DG50BA Protected Against Analog Voltages
Being Present When the Power Supplies are OFF
VS(MAX) = 20 V
(A) A DG50BA Protected Against Analog
Signals Which Exceed 15 V
Figure 21.
Overvoltage Protection (shown for DG50BA) Is Normally Used Only When the Analog Voltage
Exceeds the Power Supply Voltages, and the Signal Source Is Capable of Generating Greater
than 20 mAo
2-Level Multiplexing
When a large number of channels are multiplexed,
the outputs of two or more multiplexers can be connected together and each multiplexer sequentially
enabled. In the INHIBIT mode the multiplexer draws
less power and its output and inputs act as open circuits. Theoretically, an infinite number of channels
can be accommodated in this way; in practice the
accumulated output capacitance and leakage of
many paralleled multiplexers limits the speed and accuracy of the system. A much better method is the
two level multiplex system, shown in Figure 22. The
two level system has a bank of high speed switches
at the output which sequentially switch between the 4
DG506A's. Each DG506A is able to switch during the
time the other 3 are being interrogated, and they
contribute leakage and capacitance at the output
only when they are switched on by the DG181 (1/4 of
the time). This circuit has several important advantages over a mUlti-unit single-level system, such as:
1.
The switching speed of the system is dependent
on the DG181, which is a high speed 2-channel
SPST (tON - 150 ns). The slower switching time
13-202
of the DG506A (- 1 I1S) is not important because this switching transition can take place
while the other DG506A's are being interrogated. In this way a very fast multiplex system
can be made with a large number of low cost,
moderate speed multi-channel multiplexers and
several high speed SPST switches.
2.
The output capacitance of the 2-level system is
much lower than that of the single level. It consists of a single DG506A (40 pF) and several
DG1B1's (6 pF OFF, 15 pF ON) which is much
less than several DG506A's in parallel. If 64
channels are multiplexed, for instance, COUT of
the 2-level system would be 72 pF, vs 160 pF
for the single-level system.
3.
The output leakage current is reduced by a
similar amount. (From ±40 nA to ±10 nA in a
64-channel system).
The two level multiplex system is very useful in communications links, high speed interfacing with comparators, or wherever a large number of channels
must be multiplexed at high speeds. 1
AN75·1
Siliconix
incorporated
H
+15 V
-15 V
S12~
S,
o-li
s~of
I
I
I
I
I
INPUTS
(1-64)
+r
INVERTERS
OM7404
+5 V
L
14'2
1
14
~7
BIN
0
1
0-
VOO
J
+1YJ~
1 12
,~
3 K
CLEAR
r-
W
7
Q 1 I-
Gnd
J,."
2
a
J
9
1/20M7473
5 CLOCK
IN
~
P--Lr-2
W[>
14
10
-deY
VCC
CLEAR
6
6
~
RESET (LOW)
ENABLE (HIGH)
A
A
VCC
OG181
....
2~ ~,02
28
2
14 S2
'){
V"
V ••
EN
~
14~
~
6
9
-15 V
B
C 8
AIN
11
+1~1~'~
1 1
Y~7
V2
28
S70f9
03
-15 V
OM7493
I
I
I
I
I
+r
! s ol..1
5
VCC
BIN
MUX3
OG506A
I
63
A :2
3>--f
~J0,
4~
,2
~~O
~
14 S2
V"
A
1
A
11
A
A
16 15
~
EN
1~
~UT
+:r
VL
VCC
S OG181
4
,
S3o-1J1 V, GNO
~
~
+5y~
~
'01 '02 GNO
~
An A
+:r
~j 0,
1~
O2
117116 15
Q~
WK
1 S,
A.:2
0
~~3
--7
__ 4
BIN
IVL
MUX2
OG506A
,IS64~
5
27
V2
V, GNO
I
I
I
I
I
+r
--
~
SET
o-li
S:~
11~1
1
1/20M7473
1 CLOCK
IN
S2
+5?~
-y5 V
~
~
~
~F'-4
1
4
OG181s
a 12
1~
1,
'01 '02 GNO
2
~:"
CL OCK
IN
F!--
EN
A A
T1j615
12
0,
AI9
B
C 8
AIN
TO
MUX1
OGS06A
!IS61~A
VCC
OM7493
OM7400
127
V2
V, GNO
V ••
2
tE
6
9
-15 V
B
~6
14
C
AIN
0
8
11
+1Y2~
1 12
OM7493
S4~
~~
I
I
I
I
I
1 !l S64~
5
BIN
VCC
V, GNO
s.e>f9
V
~
A
TV
27
V2
~
'01 '02 GNO
:2
MUX4
OGS06A
A
A
A
A
-T1T6 15
04 ~
-
EN
1~
B
14
44
AIN
C
0
8
III
11
OM7493
'01 '02 GNO
L2J~
Figure 22. 64-Channel 2-Level Multiplex System
13-203
..... 8i1iconix
.,1;11 incorporated
AN75·1
Low Level Multiplexing
When multiplexing low level signals, extra care must
be used because the signal may be masked by ac
noise pickup and dc voltages generated by thermocouple effects at the connections of dissimilar metals. Much greater accuracy is obtained if the signal is
handled differentially, so that ac noise and dc thermocouple effects appear as common-mode signals
which can eventually be rejected. For this reason a
line of differential multiplexers is available which allows improved thermal tracking and differential cancellation of leakage and switching glitches.
Figure 23 shows a thermocouple representation of a
typical multiplexer mounted in a socket. If connection
J1S is at the same temperature as connection J 10 ,
then V1S =V10. If all "8" junctions are at the same
temperature as the corresponding "0" junctions, the
total voltage across the multiplexer is zero. Conversely, if a temperature imbalance exists between
side "8" and side "0" then the voltages will not exactly cancel and a net error voltage will appear. For
this reason the multiplexer and associated connections should be mounted in a thermally-stable environment, away from hot components and with as few
drafts around the chip as possible. When a OG509A
is mounted in a thermally-stable environment, the
VSS
V1S
so
t
-11+
J1S
WIRE OR
P.C. STRIP
DO
+
V2S
t
-11+
SOCKET
LEAD
J1D
-'1+
V1D
t
-11+
I.C.
LEAD
-1+
~+
+
V4S
V3S
t
BOND
WIRE
t-
CHIP
METALIZATION
:4:'
~ -'I + + -'1+ +
-'+
V2D
V3D
V4D
V5D
rDS(on)
(SOUtCE)
SEMICONDUCTOR
MATERIAL
(DRfN)
P-CHANNEL
+
N-CHANNEL
Figure 23. Thermocouple Representation of a Typical Multiplexer SWitch (73)
MATERIAL "A"
TCl
4
MATERIAL "B"
SlA
S:!A
TC2
6
TC3
S3A
TC4
S4A
13
12
DGS09A
DB
SlB
S2B
or
r--.J.--,
I
S:lB
0
S4B
~
:
1
I
I
"A"
2
"B"
¥
LOGIC
INPUT
I
IL
I
D _ _ .J
___
CONSTANT
TEMPERATURE
Figure 24. A Thermocouple Multiplex System (73)
13-204
COPPER
COPPER
H
AN75·1
Siliconix
incorporated
typical error developed across the switch is about
±3 fJ..V over the operating temperature range of the
device. In free air, with random room drafts, it can
be as high as 7 to 10 fJ..V. When heated with a thermal
probe at 85°C (resulting in uneven temperature
across the device) the absolute voltage across a
switch is about 100 fJ..V with a 30 fJ..V differential error.
IC multiplexers are therefore ideal in low level applications if care is exercised to insure an even temperature.
Figure 24 shows a DG509A thermocouple multiplexer. To decouple the sensors from the meter amplifier, either a reference junction a O°C or a bucking
voltage set at room temperature may be used. The
latter method is simpler, but is sensitive to changes
in ambient temperature. Table I shows the output of
several common types of thermocouples versus
temperature. 2
80
IE
70
II
60
50
I
40
II)
J
..i
V
IV /
30
IIIV
20
..&
K
,
G*
A!I~ P
C*
o
o
II. ~
1000
--
J.O.M. Jenkins, "IC Multiplexer Increases Analog Switching Speeds," Siliconix Application
Note AN73-2, February 1973.
(2)
The Omega Temperature Measurement Handbook(1975), Omega Engineering, Inc., Stamford, Conn.
ANSI SYMBOL
T
Copper vs Constantan
E
Chromel vs Constantan
Jiron vs Constantan
K
Chromel vs Alumel
G" Tungsten vs Tungsten 26% Rhenium
C" Tungsten 5% Rhenium vs Tungsten 26% Rhe
nium
R Platinum vs Platinum 13% Rhodium
S
Platinum vs Platinum 10% Rhodium
B
Platinum 6% Rhodium vs Platinum 30% Rho
dium
"Not ANSI Symbol
10-"""
2000
3000
4000
5000
TEMPERATURE (FAHRENHEIT)
Table 1.
(1)
R
l~T~ ~ ~ ~ ~~
10
REFERENCES
Used with permission of Omega Engineering, Inc.,
Stamford, Conn. 06907
Output Voltage vs. Temperature of Several Common Thermocouples
13-205
...... Siliconix
incorporated
AN74·2
~
ANALOG SWITCHES IN SAMPLE·
AND·HOLD CIRCUITS
Gary Dixon
Revised January 1988
INTRODUCTION
In many cases the designers of sample-and-hold circuitry have relied upon "cut-and-try" methods to
achieve good circuit performance. This Application
Note provides analytic design information regarding
sample-and-hold circuitry and practical design examples.
FET analog switches will meet the basic performance
requirements for sample-and-hold circuitry. The criteria for choosing a given FET analog switch may
seem rather simple since many of the dc data sheet
parameters are similar from one switch or from one
technology (JFET, PMOS, or CMOS) to another.
However, the dynamic features of a switch are the
primary characteristics that must be examined. This
task is not easy since any measurement assumes a
given set of conditions and circuitry. This Application
Note will consider two major characteristics of FET
analog switches. The first area is that of the large
current-handling characteristics of various switches,
which can have a pronounced effect on circuit settling times. The second subject involves the offset
characteristics of sample-and-hold circuits which
may affect the basic accuracy of system design.
ily determined high current characteristics. Figure 1
illustrates that the DG181, a 30 .n device, typically
enters I DSS limiting at 80 mAo Further investigation
indicates the DG182, a 75 .n device, typically encounters current limiting at 30 mAo If we compare the
DG181 with a CMOS device, the DG200A, we will find
the DG200A has a somewhat more resistive characteristic. The DG411 series of silicon gate analog
switches rivals JFET's low ON resistance and fast
speeds plus offering a full ±15 V input signal range
with very low power dissipation.
Figure 2 shows the resistance characteristics of a
PMOS switch, the DG172. The average ON resistance
for settling purposes may be assumed to be between
the minimum resistance at the most positive signal
excursion and the maximum ON resistance at the
most negative excursion.
100 rnA
TYPOG181
TYP 0G200A
NORMAL
For high speed sample-and-hold circuits, the large
current handling capabilities of the switch can play an
important role in determining settling time. As a rule,
the data sheet specifications for switch ON resistance are made at low current levels, such as those
found in analog signal coupling circuits. When an
analog switch is required to charge a capacitor, the
switch may be required to handle large instantaneous
currents and voltages. The switch dynamic characteristics will vary depending upon the type of switch
and the drive circuitry used.
Of the many JFET switches, the DG181-191 series is
recommended for its low ON resistances and its eas-
13-206
t
RESlsnvE
CHARACTERISTIC
TYPOG182
VOS10V
TEST CIRCUIT
CURVE TRACER
-10 V
.. ----,I
I
I
1IoIl;I.I=.I1Q
- I
":" I
':.r.- - - ..
-100 rnA
Figure 1.
Current Characteristics of JFET
Analog Switches (DG181 and DG182)
and a CMOS Switch the DG200A
H
AN74·2
Siliconix
incorporated
Charge transfer characteristics will vary to quite an
extent, depending upon various switch and circuit
configurations. To provide a method of comparison
for various switches, the preferred terminology is
charge transfer presented in pico coulombs.
+150 mA
+
IDS
Charge transfer (Pico Coulombs)
Hold capacitance (Pico Farads).
"r - - _.
-150 mA
Figure 2. Characteristics of a PMOS Analog Switch
Figure 2 is based on a negative supply voltage to the
DG172 of -20 V. If the supply were -15 V, the currents through the switch would decrease, which is a
disadvantage of PMOS. The DG181 current is independent of supply voltage, while the DG200A is designed to work with ±15 V supplies.
Let us now turn to the second subject to be covered,
that of switch charge transfer or charge injection. In
the past, this subject has been called switching transients, "glitches", and various other names. Switching transients affect the intrinsic accuracy of any
sample-and-hold design. During the sample interval,
the capacitor charges to the sample voltage. Then
during the transition from sample to hold, an offset
voltage is introduced into the charged capacitor. The
major phenomenon is that of a capacitive voltage divider formed by the capacitive coupling between the
control gate with its associated switch terminals and
the storage capacitor, as shown in Figure 3.
offset x
The DG181 series of JFET switches provides very
good transient coupling characteristics. One of the
reasons for this performance is the decrease in gate
voltage swing, because the FET gate is initially
clamped at the analog voltage. The JFET construction also provides an optimization of low coupling capacitance along with low ON resistance. If we now
compare a PMOS switch with the JFET characteristic
we are able to see a major difference.
As may be seen from the two curves of Figures 4 and
5, the charge transfer characteristics for the DG181
and DG172 are similar at CL = 100 pF and Rs = O. It
should be noted, however, that the DG172 has a typical ON resistance of 200 n, an increase in ON resistance of 6 times more than that of the DG181. For
values of capacitance greater than 100 pF, the
charge transfer characteristics of the DG172 are
seen to be inferior to those of the DG181. The major
factor which causes the storage capacitance to be
value-dependent is the large distributed gate-tochannel capacitance, plus the related circuit time
constants.
100 pC
40 pC
TEST CIRCUIT
rs- - fiI SCOPE
Rs~11:L
20 pc
rDS(ON)
= Voltage
!~:A:OGJ
D
~~~~--~~~c-~ A'--I~I,----,ovouT
-10 V
Cgd
~--4--'------~
~CSTORAGE
CONTROL
GATE
Figure 3. Equivalent Switch Circuit
5V
o
VANALOG (V)
Figure 4.
+5
V
+10 V
NOTE:
CHARGE TRANSFER
IS INDEPENDENT OF
C LFROM 100 pF TO
10,000 pF
Typical Charge Transfer Characteristic of the DG181 JFET Switch
13-207
...... Siliconix
incorporated
AN74·2
~
ries comes in a distant third, with its somewhat
slower switching speed (1000 ns) and higher ON resistance.
Inverting DG181 Sample-and-Hold Circuit
RS=
r-E::::::::I;:so-;;;;----
on
C L = 10,000 pF
RS=
C L = 1000 pF
on
RS=
on
CL=100pF
-10
o
-5
+5
+10
VANALOG (V)
Figure 5, Typical Charge Transfer Characteristics of the OG172 PMOS Switch
CMOS devices provide an improvement over the
JFET and PMOS devices since two gates with complementary control signals are involved. The two resulting "glitches" tend to cancel each other. The
transient is therefore greatly reduced but is not eliminated due to design compromises. This is shown in
Figure 6.
The inverting sample-and-hold circuit has several inherent advantages over the other design approaches. The switch operates at a constant voltage
each time, thus reducing the aperture time jitter considerably. The input configuration reduces surge currents that are usually supplied by the signal source. A
slight disadvantage of this circuit is the requirement
that the two feedback resistors be matched to obtain
reasonable accuracy. The feedback resistance value
must be carefully chosen so that the amplifier output
does not enter a current-limiting mode. General purpose amplifiers with a 20 mA limit will operate with a
5 kO feedback network. The linear time response of
the circuit is determined by the time constant (R f + 2
Rsw Cl). In this example, Rsw < Rfl; therefore, the
settling time is determined by the feedback resistance. This circuit is current-limited by the amplifier
and the feedback resistance, so the large current
characteristics of the switch are of little importance.
The circuit is also limited by the slew rate of the amplifier. If a 1500 pF storage capacitor is used, the
amplifier slew rate should be greater than 2.7 V/l!s.
If, as shown in Figure 7, an LM101A op amp is used
(with a slew rate of 0.5 VII! s, an additional 25 I! s will
be required during slew rate limiting. For the circuit
shown, an acquisition time of 98 I!S was measured
for a swing of 20 V settling into a 1 mV error band. If
we now turn the task of determining the sample-tohold offset, we must first examine the charge transfer characteristics of the switch. Since the source resistance is 5 kO; which is much greater than the
30 0 rOS(ON), we must examine the characteristics
near the high impedance curves (Rs
100 kO) on
the charge transfer chart of Figure 4. The DG181 provides an offset voltage of 43 mV. The DG200A may
be used in this circuit with a voltage jump of 18 mV. If
a DG172 switch is used a 91 mV jump should be expected.
=
-15
-10
-5
o
5
10
15
VANALOG (V)
Figure 6. CMOS Charge Transfer Characteristics
When the various tradeoffs are considered, the
DG181-191 family and DG411 series of analog
switches provide the best overall performance for
critical sample-and-hold designs. This is due in large
part to their fast (150 ns) switching speeds, which
allows a fast aperture time. The CMOS DG200A se-
13-208
Improved DG181 Inverting Sample-and-Hold
Circuit
If these foregoing charge transfer errors are too
large for practical use, several methods of reducing
the charge transfer are possible. The first method involves increasing the capacitor size which improves
the droop rate, but also requires a direct trade-off of
accuracy versus speed. A second method involves
AN74-2
.... Siliconix
incorporated
~
The compensation circuit shown in Figure 8 employs
three additional components (R3, C2 and C3) to provide total offset errors which are adjustable to much
less than 1 mY. One feature that the OG181 device
offers is a 20% larger charge transfer from the 02
terminal. This actually makes compensation much
easier since only one side of the network must be
adjusted. With other switches (such as the OG200A)
parameter variations may require that hold capacitors of two different sizes be used to provide adjustability. An added feature of this circuit configuration
of Figure 8 is a net reduction in the system droop due
to a balancing effect of the leakage currents.
reducing the size of the switching FET, which also
decreases charge transfer but increases the ON resistance. This method also requires that a trade-off
be made due to the relationship of speed versus accuracy. A third and more practical method is to compensate for the charge transfer. Many circuits have
been proposed in the past which vary from simple
capacitors in logic circuitry to rather complex systems. The inverting sample-and-hold circuit is rather
easy to compensate since it operates at a single voltage level. The basic concept involves an equal but
opposite direction of the FET gate voltage. A rather
unique circuit using this principle uses the two
switches normally found in analog switch packages.
1.500 pF
1' ...
I ......
12N5545
I (DUAL)
I
I
R 1 S1
......
......
+15
...
30 pF
eln ().J\""".....,'I-----"..-I4--jI-::'.I..---t~_
......
...
Ttl.!.'
......
M,...-----!~'_O eOUT
5
""
58k " ,
LOGIC
IN
,
"
FET INPUT
AMPLIFIER
Figure 7. Inverting Sample & Hold Circuit
k.O.
5
C1
r--------4~-------~
1.500 pF
1' ...
I ......
12N5545
I(DUAL)
......
......
I
I
.........
eln ().J\M~'-----<1"1.'-f~--~--T-!:::;==rJj.!.'
...
......
I,...----~~~
e OUT
",
RS
1,500 pF
,~:."
-15 V
III
"
FET INPUT
AMPLIFIER
Figure B. Improved Inverting Sample and Hold Circuit
13-209
W'Jr Siliconix
.,6;11 incorporated
AN74·2
r-...
I
......
12N5545
......
I(DUAL)
......
I
I
.........
......
.....----...~.......-o
eln o---='f------6--+-----0 VOUT
02 17
-15 V
-15 V
III
Figure 11. Fast Sample and Hold
13-211
AN74-2
..... Siliconix
incorporated
~
Figure 13 is a charge injection compensated sampleand-hold with less than ±5 pC of charge transfer
« 5 mV offset when CL= 1,000 pF).
In Figure 12 the switching transients are attenuated
by synchronizing the turn-ON and turn-OFF times of
one switch with those of another.
SIGNAL
IN
+15V
.---~Q)
2
5
-=10
-=-
-15 V
Figure 12. Attenuating Switching Transients
+15V
+5V
LOGIC
CONTROL
HIGH
= HOLD
-,
3 pF
I
VINo---f----<~·L--+-..,...~---_I
Figure 13. Charge Compensated Sample-and-Hold
13-212
10 kll.
AN74-2
.... Siliconix
,.1;11 incorporated
DG201A
VANALOG
D
INx
~S~
o-----,----It::::=_..J
____~~____~____~
Cc
CD40106
R
C~
Figure 14. Simplified Compensation Method
Figure 14 is another inexpensive charge injection
compensation circuit that can be tailored to get a
good first order compensation. The values of Rand C
are chosen to obtain the proper timing. Cc is sized
to dump the proper amount of compensation charge
onto the hold capacitor.
REFERENCES
(1) Lee Shaeffer, "CMOS Analog Switches - A
Powerful Design Tool," Siliconix Application
Note AN75-1, July 1975.
13-213
trY' Siliconix
AN73·6
~
incorporated
FUNCTION!APPLICATION OF
THE L144 PROGRAMMABLE
MICROPOWER TRIPLE
OPAMP
INTRODUCTION
The L144 is a monolithic triple operational amplifier
circuit with an external programming feature for
power dissipation and input bias current control. It
finds application in RC active filters, amplifiers,
micropower comparators, and numerous general signal processing circuits. The L144 is a practical op
amp wherever low current drain, low voltage, low
power, or very small physical size are the controlling
criteria.
This Application Note describes the L144, how to program it, what the effects of slew rate limiting are, and
some practical circuit applications.
The L144 has three operational amplifiers programmed by one external current setting resistor. It
operates from power supplies ranging from ±18 V to
as low as ±1.5 V with quiescent supply currents from
10 J.LA to greater than 1 mA independent of supply
voltage. The schematic shown in Figure 1 reveals a
general-purpose PNP input transistor op amp with an
outstanding difference. The master bias current is
not set by an internal resistor strung from V+ to V-,
but is brought out to an external pin. This allows the
user to determine the operating currents of each
stage through a system of current mirrors. Of special interest to the designer are the equal collector
currents of Ql and Q2, which are derived from the
output of Q4. These collector currents, divided by a
beta of approximately 50, determine the input bias
currents for each amplifier. The ratio between the
set current and the collector current of Q4 is unity,
which allows one to program the input bias current
simply by changing the set current input of the device.
Input Bias Current and Supply Current
The relationship between supply current, supply voltage, and the setting resistor is shown in the graph
and set current model of Figure 2. The two diodes of
the set current model correspond to the base-emitter
junctions of Q16 and Q17.
BIAS NETWORK, COMMON,
TO THREE AMPLIFIERS
ONE AMPLIFIER
+vs
r------,
I
I
r-4---~--+_--~----r_.
-iN
+IN
o--t=-1==-~ 1-+_-;_-[,
I
I
I
I
I
I
I
I
I
I
I
QJ--~I--+-i--f-ff--- vlN > vLOW
DIRECT CMOS OUTPUT
Figure 14. Double-Ended Limit Detector
1'"
100
V
AN73-2
..-F' Siliconix
~
incorporated
IC MULTIPLEXER INCREASES ANALOG
SWITCHING SPEEDS
J. o. M. Jenkins
Revised March 1988
INTRODUCTION
A two-level IC multiplexing system, that has significant advantages over conventional single-level systems, can improve effective switching speeds of
analog systems by approximately one order of magnitude.
Analog multiplexing is the simultaneous transmission
of two or more analog signals on to a single transmission line. Time-division multiplexing is widely used,
each analog input being sampled sequentially and
conveyed into a common output line. The signals can
be transmitted directly in their analog form or they
can be digitally coded by means of AID converters
and then transmitted. The latter method is used in
applications requiring a very high degree of transmission accuracy.
which rapid sampling of analog signals is required. In
any application in which it is necessary to sample
analog signals and convey them at maximum transmission rates, the ratio of t 1: t 2 must be as small as
possible (where t 1 represents the time between
samples and t 2 the sample duration time).
Applications requiring microsecond sample times
clearly present considerable difficulty, because IC
multiplexers which are commercially available have
tON and tOFF times in the region of 1-2 J.l.s. When
used in the conventional single-level mode, a substantial loss in transmission efficiency results. Figure
1 shows a simple single-level system for analog mUltiplexing.
v-
v+
y
In a system having 'n' analog inputs, a multiplexingl
demultiplexing system will generally require 1/n of
the total transmitting and receiving circuitry of a nonmultiplexed system. Hence, system cost is reduced
drastically in the former case.
Present-day requirements for analog multiplexers
have necessitated the development of special circuits. These incorporate multichannel FET mUltiplexers which are now available in integrated-circuit
form, and which possess numerous advantages over
their discrete counterparts:
The use of IC's introduces a higher degree of
circuit reliability;
(2)
Switch for switch, IC's are much more compact;
(3)
System layout cost is less;
(4)
Lower cost per switch.
Single-level Multiplexing System
Fast IC multiplexers, having rapid open and close
switch times, are required in many applications in
y
A
..il
...iIT
... 1 T I
...il
_I
.... 1
..... 1
~I
....il
f-<> o
.... 1
....i l
_I
.... 1
U"
v-
(1)
GND
y
.... 1
?-"I
I
1
1
1
1
DG506A CMOS DECODE LOGIC
b b b b b
Figure 1.
DG506A Used as a Single-Level
Multiplex System
With a single-level system one can obtain either (a)
the wave-forms shown in Figure 2 (a), and be faced
with inter-channel interference due to overlapping
samples or, (b) the waveforms of Figure 2(b) which
result in delayed channel switching, in order to eliminate interference between channels.
13-221
..
..
...... Siliconix
incorporated
AN73·2
~
L. t 2 .J
I
I
I
I
I
:
t1
3
s
(2)
l..-
I~ ...o----I..I_
I
I
I
I
I
I
I
I
CHANNEL 1 STARTS TO OPEN
_
I
--.l1.2J1Sr-J1~1'2J1S~t2.1
I
:
I
I
I
t1
r---
TIME (t)
I
I~:
L3J1S~
r- i ~,----
--V
I
LO~g g~~NM~~~ -.I
AND CLOSE CH 2
I
I--
'--
CHANNEL 2 FIJLLY CLOSED
I
The common node output capacitance increases with the total number of analog channels being multiplexed. With 64 channels (i.e.,
4 x 16 channel DG506A), the common node
output capacitance will be typically 180 pF.
The charging time (t 1) necessary for the analog signal to reach 0.25% of its final value (six time constants) will then be approximately
6
x COUT(rDS(ON)
+ RANALOG
SOURC8
(1 )
If the source resistance is f k!l, t 1 will be
CHANNEL 2 BEGINS TO CLOSE
6 x (180 X 10-12 F) x (400 !l + 1 k!l)
Figure 2(a). Overlapping Channels
=1.51 }.Ls
(2)
This decreases the effective switching speed of the
multiplexer.
-
nME (t)
I
--I
COMMAND
I
LOGIC
TO CLOSE CHANNEL 2--1
Figure 2 (b). Delayed Channel Switching
If the analog sample time needed is 3 IJ.S, for example, system 2(a) would not be a practical proposition. System 2(b) would certainly be practical but
would introduce a large wastage of transmission time
due to the large ratio of t 1:t 2 (Figure 2 (b). in fact,
indicates a 50% loss in transmission efficiency).
This problem is manifest in all commercially available
IC multiplexers used in single-level systems. Other
problems that result from using a single-level system
are:
(1')
With a large number of separate :lnalog inputs,
the leakage currents through the OFF switches
can introduce an appreciable percentage voltage error into the common output line. This is
important if the analog signal iJeinging conveyed through the closed switch is in the millivolt range.
13-222
Two-Level Multiplexing System
These problems can be overcome if a two-level multiplexer is used, which inherently provides a much
faster switching system. Figure 3 shows an example
of a two-level system capable of 32 channels. The
first level consists of 16-channel DG506A mUltiplexers, the use of which offers the advantages
stated in the introduction. The second level consists
of two or more single channels of a DG181; this has
switch 0P:!I1 and close times of, typically, 100 ns,
and has a break-before-make switching action. The
DG181 is available in a dual-in-line package.
The two-level system uses the bank of high speed
DG181 switches at the output to sequentially switch
between the outputs of the DG506A's. Each DG506A
is able to switch channels during the time the others
are being interrogated. It contributes capacitance
and leakage at the output only when it is switched
into the output bus by a DG181.
The use of the two-level system achieves the following:
(1)
Effectively reduces the common output node
capacitance of the system. It will consist of a
single multiplexer output, DG506A (45 pF) and
sevmalDG181's (6pFOFF,14pFON). Fora
64-channel 2-level system, for example, the
outP'Jt capacitance is reduced to 77 pF, compared to 180 pF of the single-level system.
~
~
AN73·2
Siliconix .
incorporated
32-CHANNEL
ANALOG
INPUTS
••
DG506A (Al
CH29·
DG181
SWITCH A
CLOCKD-f---+-----'~::::--='---==---f
INPUTS
(1 -64)
G
INVERTERS,
DM7404
+r
VCC
1
DM7493
13.1412
14
AIN
~
A
VCC
CLOCK ~
INoCLOCK
IN
13
12
QrJE-
14
Tr
10_
11
.....
1....
~
G
10
Q
CLEAR
Is
,:2
DM7493
AIN
r01 r02
l
l
ENABLE (HIGH)
5...
S3~
S7'T,
,,
,
V
J
15
VCC
Q.
I
I
I
,
:2
S
14
AIN
E.I
,
Q4~
I
I
l
l
A, EN
14~
J1TT5
12
AIN
'0 '02
D4~ r-
MUX4
DG50SA
I
2L SS4~
BIN
V2
S4~ V, GND
SBar,
,,
,
9
B
60
A
A
J 1T SI1 5
6.
EN
14 ~
I
J
11
GND
~y
Figure S. 54-Channel 2-Level Multiplex System
13-226
+11 V
DG181
po
Vce
rA.01
101py~02
19
V
5
VCC
14
-V
3~
MUX3
DG50SA
A
VL
1 S1
~
-t~ V
+1Y2~
1 12 .".
27
GND
DM7493
3 ...
V2
D.
11
~y
I
I
-rv f-o
+y
DM7493
Q~
i
ON
t
V, GND
SS301-1 An A
BIN
'01 '02
,
14~
+1Y 2[11 12 ~
GND
4 CLOCK PHASES TO DG1B1
LOGIC INPUT
Q'~
ON
VEE
.J,.B
OUT
~y
ruo....
-y"
......
02
11
fL
RESE~(LOW)
A, EN
J1JS 15
P-
;J--.o...,..,- E
8
_3
rb,.4
IN
14
VCC
14 S2
VR
O2 2
A
g
01
IN
10
An A
DG181 VCC
>"(~
po
1~
MUX2
DG50SA
JSS2~
L£
BIN
VL
1 S1
-15 V
1/2 DM7473
....§. CLOCK
2
V2
I
8
.J,.
Q
,,I
,
+1f
+Sf
~
S:f
Ss
+r
Q~
.J.QK
14~
21-l- -t~27V
+1Y
1 12
DG1B1s
IClFAR
J
A,EN
8
11
*
IL...Y-r+2
...2
A
, 1TS 15
2y
~~1-4
1/2 DM7473
J
A
D,~
V, GND
r-J
P
JSS1~A
GND
'01 '02
:r
MUX1
DG50SA
:2
BIN
+SV
I
I
I
I
I
14 S2
VR
.J,.8
"'":-:-VEE
b
P~
9
-15 V
.... Siliconix
incorporated
~
TA87-1
ELIMINATE THE GUESSWORK
IN YOUR ANALOG SWITCHING
ERROR ANALYSIS
By Steve Moore and Van Brolllni
September 1987
The "DGP" Philosophy
To design a precision analog system, errors must be
identified and reduced to levels within the guard
bands dictated by the overall system accuracy requirements. For worst-case design with analog
switches and multiplexers, one must rely on data
sheet minimum and maximum limits to determine the
error contribution of a given channel. Many devices,
however, do not have 100% tested limits for parameters critical for precision such as charge injection,
variations in on-resistance, and variations in switching time. Furthermore, other parameter limits are
specified on a "not tested, guaranteed-by-design"
basis. Therefore, precision system designers must
screen incoming devices, living with uncertainty
about the actual performance of their system, or
compensate by adding circuitry or selecting other expensive components.
The "DGP" family of analog switches and mUltiplexers brings new levels of precision to monolithic
devices. This family embodies a new philosophy for
the specification and testing of analog ICs. In contrast to "typical" or "guaranteed by design" specifications, all limits on the DGP family data sheet are
100% tested. Superior CMOS processing tightens the
limits for leakage and extends the analog range beyond anything previously available. Devices are
tested with 10% guard bands on the power supplies
at the most commonly used voltages. Using new
analog test capabilities, charge injection, variations
in on-resistance, and switching times are also 100%
tested.
Eliminating Data Sheet Guesswork
When designing a precision data acquisition system
with existing analog switch and multiplexer families,
the errors introduced by these switches can be the
major source of system inaccuracy. The limits for
switch on-resistance and leakage currents have always had well-defined data sheet limits--even over
temperature. However, it has been impossible to find
tested limits for the variations in on-resistance as the
power supply, drain, or source voltages are varied.
So while it is easy to predict the offsets caused by
"ON"-resistance under nominal conditions, the designer must guess what effect varying supply and input levels will have. With the new DGP family of
switches and multiplexers, these variations are specified to within 5% over a wide range of supply and
analog voltage ranges. Therefore, it is now possible
to design a fully guard-banded system.
What happens to an analog switch when the power
supply voltage is varied from +13.5 V to +16.5 V (a
typical ±10% tolerance in a nominally +15 V supply)?
With the previous generation of switches, the designer either characterized the device or used the
manufacturer's typical performance curves to estimate the guard bands required to ensure system accuracy under all rated conditions. Switch "ON"-resistance could vary as much as 20% between channels
and with changes in supply voltage and analog input
voltage. These variations translate directly into nonlinearity and gain errors. The DGP devices are tested
at worst-case supply voltages to define firm design
limits for operation with ±10% variations in nominally
±12 V, ±15 V, and ±20 V systems.
The change in "ON"-resistance from switch to switch
in multiple switches and multiplexers can limit a system's channel-matching and common-mode rejection. This change has never been specified below
10%, and it is usually listed as a "typical" value, not
a tested one. Variations from switch to switch are
included in the DGP family tests for on-resistance
variation. For example, a total of 24 supply voltage
combinations and analog voltages are tested across
the four channels of the DGP201A to determine
changes in on-resistance specified with less than 5%
total variation.
Leakage current at the source or drain can result in
significant errors in sample-and-hold amplifiers and
high-impedance systems. While other switch families
offer leakages as low as 1 nA, the DGP family offers
13-227
TA87-1
tr'P' Siliconix
,LII incorporated
a factor of four times improvement in leakage performance (down to 250 pA). Additionally, tight limits
are established for the most adverse leakage conditions--that is, the worst-case extremes of the temperature and voltage ranges.
Most analog switch/multiplexer families for precision
applications operate with ±15 V supplies. CMOS
technology, which allows an analog signal swing from
rail to rail, provides operation with up to ±15 V. The
enhanced metal-gate CMOS technology used for the
DGP family (see "Process Evolution" below) allows
operation with supplies up to ±22 V supplies, with
"ON" -resistance and leakage specifications tested
for those supply levels. Therefore, a wider signal
range is achieved, resulting in greater system headroom and better dynamic range. These features are
essential for high-resolution applications such as precision data acquisition and professional audio equipment.
Improved AC Performance
In today's world of high-speed data acquisition, the
requirements of precision systems extend into the
realm of the dynamic accuracy as well as the traditionally specified dc parameters. Switch and mUltiplexer specifications of particular importance are
charge injection (or charge transfer) and switching
speed (or transition time). Charge injection occurs
when the parasitic FET switch capacitance transfers
a charge into a channel that is being switched on or
off. Seen as a glitch which accompanies all onloff
transitions, charge injection is a major source of inaccuracy in sample-and-hold amplifiers as the
charge is dumped into the hold capacitor (see Figure
1). Because testing this parameter in production is
difficult, the tested maximum limits for charge injection have never been specified on analog switch and
multiplexer data sheets. However, the DGP201A is
fully tested for charge injection with a maximum limit
of 50 pC (at Vs = OV). The maximum error contribution of charge injection to a sample-and-hold circuit
can be calculated using:
A",
Using this formula, the maximum voltage error for a
10,000-pF hold capacitor is 5 mY.
Switching speed can vary from channel to channel.
These variations can create sampling errors, resulting in system dynamic channel mismatch. The DGP
13-228
family uses advanced ac test capability to specify a
maximum variation in switching time of 50 ns.
1/4DGP201A
VIN Of------- - - - - - - - 1
Figure 1.
T_
Cti
Simple Sample-and-Hold Circuit
Full Range of Standard Functions
With the DGP family, Siliconix is offering the most
commonly used analog switch and multiplexer configurations. These parts are all pin-for-pin replacements for existing devices, making it easy to upgrade
system precision and quality. For example, the
DGP201A may be used for quad switch applications,
the DGP303A for dual SPDTs, the DGP508A for
8-channel multiplexers, and the DGP509A for dual
4-channel systems.
Process Evolution
The DGP family is built using a mature metal-gate
CMOS technology. Since its introduction in the early
1970s, this process has been significantly enhanced,
improving to the point where today the breakdown
voltage is consistently above 50 V without trade-ofts
for leakage or on-resistance performance. This extremely well-controlled process specification results
in leakages typically below 50 pA, allowing vastly improved maximum leakage limits.
Improved Sample-and-Hold Performance
A precision sample-and-hold amplifier can be built
with the DGP201A quad analog switch. Figure 2
shows a practical sample-and-hold amplifier that
uses buffering at the input and output. This circuit
includes charge cancellation circuitry to minimize
pedestal error due to switch charge injection.
During the sampling phase (logic input low), SW2
and SW4 are on, while SW1 and SW3 are off. This
design forms a closed-loop amplifier that charges the
hold capacitor, C2, through the on-state switch,
SW4. C2 is charged to the value of the input voltage
TA87·1
Ififjff' Siliconix
,./LB incorporated
+15V
13
v1
SW2
15
16
4
LOGIC
INPUT
LOW= SAMPLE
HIGH = HOLD
-15V
-15V
Figure 2. High Performance Sample-and-Hold Circuit with
Reduced Pedestal Error and Droop Rate
being sampled. During the hold phase (logic input
high), SW2 and SW4 are open, while SW1 and SW3
are closed. This configuration opens the overall loop,
so the output of the sample-and-hold circuit remains
fixed at the voltage stored on the hold capacitor.
Closing SW3 keeps the input buffer at unity gain in
the absence of overall negative feedback. Closing
SW1 transfers a charge, which is equal and opposite
in magnitude to the amount injected by SW4. This
charge would otherwise feed into the hold capacitor
and appear at the output as a pedestal (or range dependent offset) error in the sample. Using the
DGP201A, with its maximum charge injection of
50 pC, the value of the charge compensation can be
intelligently selected to achieve the desired level of
precision.
Differential Data Acquisition System
The extremely low leakage of the DGP201 A and the
JFET input buffer gives .this sample-and-hold function
an excellent droop rate. Worst-case droop rate is
calculated by
Precision Gain Switching Differential Amplifier
A VIA t
=A
IIC
where I is the sum of leakage from the switch
(250 pA maximum) and the JFET (250 pA maximum), and C is the value of the hold capacitor.
In this circuit,
500 pA/1000 pF
the
maximum
= 0.5 Vlsec.
droop
rate
is
Figure 3 shows a 4-channel 4 1/2-digit differential
data acquisition system. The Si7135 AID converter
uses a 2.0 V full-scale range, resolving 20,000
counts which translates into a 100 jJ.V step size. Typical leakage currents of most multiplexers can seriously degrade system accuracy, especially with highimpedance sources such as strain gauges and
transducer bridges. The DGP509A, with its 2 nA
maximum leakage, contributes a maximum 100 jJ.V
error (1 LSB) with a 50 k!l source impedance. Using
the DGP509A, 4-channel precision differential mUltiplexing is accomplished without degrading commonmode rejection or without additional decode logic.
Figure 4 shows an instrumentation amplifier which
uses an OP-07 precision op amp and a DGP303A to
digitally select one of two gain settings. This circuit
features low noise, excellent common-mode rejection, low drift, and well-defined limits for gain accuracy. Analyzing this circuit using the original DG303A
and comparing it to the performance using the new
DGP303A illustrates the dramatic improvement possible by upgrading to the DGP family without redesigning the circuit.
13-229
~
..
.... Siliconix
incorporated
TA87·1
~
ANALOG
GND
Os
SI7135
+1SV
04
~
Differential
Analog
Inputs
02
BP
17
1S
19
04
a1
~
g1
:
D2
01
01
BS 16
B3
OF412
B4 1S
VDD
B2
B2 14
DB
9
9
INPllT LO
Bl
2S SEGMENTS
+5V
Bl
13
eo
:;;1;0.1)1 F
200 pF
VSS
1 )IF
-::-
·~Enabl.
osc
~
Address
Select
Figure 3. 4112 Digit Differential Data Aqulsltlon System
The most dramatic improvement is seen at the industrial temperature range maximum (85°C) . The
DGP303A switches are modeled using a resistor
(rOSION)) in parallel with a current source (IOION))
for an on-state switch. For the off-state condition, the
switches are modeled only as a current source
QSIOFF) ).
In this example, the gain selection is unity for logic
high at the logic input, and a gain of 10 is selected
for a logic low. The sources for error (at maximum
over temperature of -40 to +85°C) under consideration are:
Ie (OP-07A)
=4 nA
I OION) (DG303AB) = 200 nA;
I OION) (DGP303A) = 2 nA
13-230
ISIOFF) or IOIOFF) (DG303A) = 100 nA;
ISIOFF) or IOIOFF) (DGP303A) = 1 nA
= 75 n
= R3 = 10 k; R2 = 100 k
rOSION)
R1
The input error voltage (Verti) caused by switch leakages can be approximated by:
Vertl
= 10 k
(IOION) +ISIOFF) +Ie)
For the DG303A,
Using the DGP303A precision analog switch, the error
is:
Vertl = 10 k x (1 nA + 2 nA + 4 nA) = 70 )J.V
These calculations show that with the DGP switch, the
error is dominated by the OP-07 bias current.
TA87-1
Siliconix
incorporated
-------82
---,
I
1/20GP303A
V OUT
R2+ r08(ON)
1/20GP303A
10
R1
R'2 + r08(ON)
Logic Input
1 = gain of 10
o = gain of 1
R1
Figure 4. Precision Gain-Selectable Differential Amplifier
III
13-231
~
~
TA73-1
Siliconix
incorporated
MULTIPLEXER ADDS
EFFICIENCY TO 32-CHANNEL
TELEPHONE SYSTEM
by John A. Roberts and J.O.M. Jenkins
Revised January 1988
Time-division multiplexing has gained wide acceptance in recent years as a means of combining multiple telephone channels on two-wire-pair transmission
lines that previously accommodated only one channel. Combined with pulse-code-modulation (PCM)
circuitry to convert the sampled signals to a digital
format, the multiplexing techniques have generally
reduced size, power consumption, and costs of plant
equipment.
To achieve minimum signal loss and distortion in
such systems, much effort has been directed toward
building multiplexers that switch from channel to
channel with minimum output rise and fall times.
Such a multiplexer design, recently built and tested,
provides 150 ns switching time, an order of magnitude faster than presently available circuits.
mum frequency of f L can be accurately reconstructed from periodic samples taken at a rate as
slow as 2fL.
TIME- DIVISION
MULTIPLEXER
PULSE-CODE
MODULATED
OUTPUT
Problems In overcrowding of wire-pair telephone-transmission lines are lessened by using analog tlmedivision multiplexers followed by AID converters.
Figure 1. Telephone's Answer
This high speed switching is achieved by applying
biphase control logic to a two-level multiplexer arrangement that takes advantage of the fast rise
times and the break-before-make action of newly developed intergrated circuit multiplexers.
Telephone System Requirements
A generalized system used to time-division multiplex
voice signals is shown in Figure 1. After the signals
on each of analog channels have been sampled,
each sample is quantized and coded into a PCM format. The new design focuses on the analog multiplexer, which feeds the analog-to-digital converter.
The sampling rate for each of the incoming channels
is determined by the desired bandwidth of the voice
Signals being sampled, while sampling dwell time is
fixed by the number of channels that must be sampled. Nyquist's sampling theory 1,2 states that any
transmitted waveform that is band-limited to a maxi-
13-232
In practice, however, filters do not provide ideal cutoff at fL' and a somewhat higher sampling rate must
be tolerated. For example, to achieve less than 1%
error in reconstruction accuracy, the sampling rate
must be at least twice the frequency at which the
unwanted signals above cutoff are reduced by
40 dB.2.3 Thus, to relax difficult filtering requirements at the input-to-sampling circuitry, a voice
bandwidth that is nominally limited to about 2.3 kHz is
usually sampled at an 8 kHz rate, or once every
125 j.ls.
Single-Level Multiplexers
The standard configurations of today's telephone
systems dictate that a fundamental group of
32-channels be multiplexed onto one line.
Therefore, with a sample frame time of 125 j.ls each
of 32 multiplexed channels is sampled for 125/32 or
3.906 j.ls, as Figure 2 indicates.
~
~
TA73-1
Siliconix
incorporated
-:::::::1""''''''-
r-r--
-- 1-1-
t-
-
~-------
--- ---
32 I 2
,..-3.906JJ.s
-~
l32 I
SAMPLING OF
CHANNEL 32
f.f-
SAMPLING OF
CHANNEL I
f-
SAMPLING OF
CHANNEL 2
t--
SE-AMPLITUDE
~ ~~DULATED
OUPUT
OF MULTIPLEXER
125JJ.s_
For accurate reconstruction of a 3.3 kHz telephone signal.
It must be sampled at a rate of about 8 kHz. or once
every 125).Ls. The hierarchy of today's telephone system
makes It highly desirable to multiplex 32 speech channels
during this period.
Figure 2. Tight Fit
Conventional multiplexing networks can be implemented with either discrete components or integrated circuits. such as the Silica nix DG508A (see
table). This circuit multiplexes eight input channels
with a switching time between channels of 1 to
1.5 j.Ls. A 32-channel multiplexer is constructed simply by paralleling four DG508A's. Thus, in single-level
switching, each of the 32 analog input channels is
multiplexed through a single switching bank.
CIRCUIT CHARACTERISTICS TABLE
DGSOBA: B-CHANNEL
ANALOG MULTIPLEXER
2o=
23
rn
4 w
5 6 m
7 B,..'
CONTRO{
INPUTS
~~~JNELS
2'
2"
SINGLE OUTPUT
DGIBI: 2-CHANNEL
ANALOG MULTIPLEXER
CONTROL{
INPUTS
DG508A
450.0.
1.5JJ.s
25 pI
INPUT
2 _ _ CHANNELS
I
'-n--tl
~
2
OUTPUTS
SERIES RESISTANCE (ON CHANNEL)
SWITCHING TIME
OUTPUT CAPACITANCE
DG181
30.0.
150JJ.s
20 pi
The problem with such a system stems from the relatively slow 1-1.5 j.Ls switching times between channels. Depending on the design of the particular multi-
plexer, there can either be an overlap or "aliasing"
between sampling pulses, which leads to crosstalk
between channels, or a large separation between
samples, which reduces the sampling time of a particular channel. The reduced sampling time results in
lower multiplexer efficiency.
Added to the 1-1.5 j.Ls switching time is a delay associated with the increased output-node capacitance
when multiple channels are combined. For four
DG508A's (32 channels), the added delay is about
200 ns. These delays further reduce the effective
sampling time and bring some uncertainty into the
timing strobe for the AID converter. The node-capacitance problem can be lessened to some extent
by a high performance sample-and-hold circuit between the multiplexer and the AID converter. However, the 1-1.5 j.Ls switching times remain, and this
problem becomes acute for signals obtained from
sources with output impedances of 2 k n and above.
Two-Level Multiplexing
System response time can be improved by reducing
the output-node capacitance. This is achieved by using a two-level multiplexing system as shown in Figure 3. 4 Here, circuits with lower output capacitance
(such as the DG181, with performance shown in the
table) are placed in the second multiplexing level,
which feeds the AID converter.
The DG181 can switch at a speed of 150 ns. The full
advantages of these speeds, however, are not realized, since interchannel sampling time is still limited
by the 1-1.5 j.Ls rise times of the DG508A's.
A timing sequence that makes maximum use of
switching rise times of the DG181 s (and therefore results in extremely high sampling efficiency) can be
achieved by applying control logic to the two-level
multiplexer in a manner which will give the sampling
sequence shown in Figure 4. The faster switching
speed and the break-before-make action of the
DG181 virtually removes the possibility of overlap.
The problems caused by the relatively slow switching
time of the DG508A are eliminated by ensuring that
the first channels of multiplexer switches 1A and 2A
(Figure 3) are already fully closed when 28 and 38,
respectively, are closed. This sequence is then repeated for each of the eight channels of the
DG508A's, and the complete cycle is again repeated.
13-233
III
TA73-1
2
4
Siliconix
incorporated
6
8
10
FIRST-LEVEL
} DGS08A's
' - - - - 1 - - -.......
}
26
16
46
36
SECOND-LEVEL
DG181'.
OUTPUT TO A-D CONVERTER
Output-node capacitance Is significantly reduced when a second level of multiplexers Is added. Interchannel
switching time; however, Is stili determined primarily by the speed of the first-level switches.
Figure 3. Two-level Multiplexing
CHANNELS
8, 16 CLOSED
CHANNELS
1,9 CLOSED
CHANNELS
3,11 CLOSED
CHANNELS
2,10 CLOSED
}
CHANNEL-CLOSURE
TIMES FOR
lAAND2A
}
CHANNEL-CLOSURE
TIMES FOR
3A AND 4A
}
OUTPUT CHANNEL
SEQUENCE
--
c~6~~ ~: - - - - i i - - - I
OPEN 36
26
CLOSE
----I==:I=~:i
CHANNELS
18, 26 CLOSED
;=:t::;::;:+::;;I:=:..
c~6~~~:-----+---+--~-~
c~6~~i:-----+---+--4---+-~
24
32
9
17
25
2
10
18
26
3
- - - - L - -...
-LI--LI...
--L--S-AM-L-PL-IN-G-LP-E-R-IO-DL-=-3-.9-0~6-~-S-~-~--~-----
By adding two-phase control logic to the two-level multiplexer of Figure 3, the full advantage of the 150 ns switching
speed of the DG181 circuits Is realized. Channel numbers correspond with those In Figure 3.
Figure 4. Phase II timing
13-234
a"1I'"
~
TA73-1
Siliconix
incorporated
CGSOBA
+5 V ......- - - - - - - - ,
A
:::C:::LO~C~K~_H J-K
o
o
o
o
~ lB
t
~2B
ON
SWITCH
x
o
NONE
1
2
3
o
o
o
1
1
o
1
4
S
6
1
7
B
1
o
o
o
r
o
1
1
~3B
AB
EN
x
x
OG181
SWITCHES
K
Ao
t
~
+5V-.-----.-----,
J
J
J-K
J-K
K
4B
+5V
J-K
K
K
J
L---~====~~~~--t------+------+-------~J~
XAB
K
J
J-K
K
J
J-K
K
(A) LOGIC
-U- k[-U-
-_f--
'--
r--3.906JI S
~ U- beU- beU- ~ s J
"'-
--
r-I'--
F=
=
--Lf
=r--
~
r
L
r
~
4)
AB - LOGIC 1 CLOSES 3B
~AS - LOGIC 1 CLOSES 2B
-
r--
r
B
-
r--
I'--
r--
A (-:- 2)
- - AB - LOGIC 1 CLOSES 4B
r--
I'--
X CLOCK
AE! - LOGIC 1 CLOSES lB
r
L
r
XAB
L
XAB - INPUT TO 1ST -:- 8 COUNTER
...
.. ~.~ . • .L . - ~~ --. ...
,,'~'l?~
.
• .
"
x..a
-INPUT TO 2ND -:-8 COUNTER
OGS08A NOS. lA, 2A,
01
• - l" ""
... '",-y"':' '
.• 'j" .
(B) TIMING
OGS08A NOS. 3A, 4A
TTL control circuits (a) Implement timing (bj required In two-phase, two-level multiplexing system. First-level DG50BA switches
are MaS circuits, and JFET technology gives the faster switching times needed In the DG18l second-level switches.
Figure S. Logic hardware
13-235
TA73·1
trW'" Siliconix
,JI;II incorporated
~~
waveforms are combined to give AB, AB, AB and A B
which are needed to close the DG181 gates sequentially. Functions XAB and XAB then clock two 3-bit
asynchronous counters. A delay of two clock periods
exists between XAB and XAB so that the count sequence applied to the second and third multiplexer is
suitably delayed.
~
IiIII1!
~
.~
~
~
IiIII1!
Ill!
(a) 20J,ls/DIV
A prototype multiplexer with two-phase control logic
has been constructed and successfully tested. Series 7400 TTL circuitry is used to implement the timing and control logic. First-level DG508A switches are
MOS circuits, while JFET technology gives the faster
switching times needed in the DG181 second-level
switches.
To simulate all 32 analog inputs to the multiplexer, a
voltage-divider network of series resistors is connected across a +3 V supply. Thus, 32 dc voltage
levels are consecutively tapped off the network and
applied to the multiplexer input. The multiplexer output is displayed on the OSCilloscope, as shown in Figure 6a. As can be seen, the largest transition is from
-3 to +3 V. In Figure 6b, this 6 V transition is demonstrated as being accomplished in less than 100 ns.
ai':
(b) 200 ns/DIV
Thirty-two dc levels are sampled In a prototype
multiplexer to demonstrate switching speed of
the two-level two-phase design. Largest single
transition, from -3 to +3 V Is expanded In the
lower trace. Verticil! scale for both traces:
2 V per division.
Figure 6. Quick Switch
Two-Phase Control Logic
The timing requirement and logic control layout for
the complete circuit are shown in Figures 5a and 5b.
Waveforms A and B are obtained from the input clock
waveform by an asynchronous divider. The A and B
13-236
If low-power TTL or diode-transistor logiC is used in
the control circuits, synchronous counters may be
necessary to eliminate cumulative flip-flop delays. Although the system shown is deSigned for negativeedge-triggered J-K flip-flops, the circuitry can be rearranged quite simply for almost any bistable logic
element.
References
1. Schwartz, M., "Information Transmission Modulation and Noise," 2nd ed. p. 174, McGraw-Hili
Book Co. 1970.
2. Shannon, C., "A Mathematical Theory of Communications," Bell System Technical Journal. pp
379-423, July 1948 and pp 623656, October
1948.
3. English, M., "Multiple systems" Electronic Products pp 28-31, May 1969.
4. Yoder, D., "Two-Level Multiplexing for Data-Acquisition Systems," pp 67-72, EEE July 1970.
Publications Index
III
I
WF Siliconix
~
incorporated
PUBLICATIONS INDEX
Siliconix Incorporated wants to keep you informed about our available technical literature.
The listing that follows shows publication year and section contents for each book. For complimentary copies,
please contact your local Siliconix sales office. A listing of sales offices is included at the end of this book.
We are interested in your comments and suggestions about our technical literature. Please send them to
Siliconix Incorporated
Attn: Technical Literature Dept. MIS 05
2201 Laurelwood Road
Santa Clara, CA 95054
or give us a call at (800)554-5565.
INTEGRATED CIRCUITS DATA BOOK - 1988
Introduction. Quality And Reliability. Process Option Flows. Analog Switches and Multiplexers. Digital To
Analog Converters. Analog To Digital Converters. WidebandlVideo Switches And Multiplexers. Operational
Amplifiers, Comparators. FET Drivers. Display Drivers. Voltage Converters. Switch mode Controllers, Regulators. Application specific IC's (ASIC). Application Notes.
FET DATA BOOK - 1986
Introduction. Process Option Flows. Design Alternatives. Junction FETS. Current Regulator Diodes. Pico Amp
Diodes. Double Diffused (OM OS) FETs. Low Power N & P channel MOSFETs. Application Notes.
MOSPOWER DATA BOOK - 1988
Process flows. Selector Guide. N & P Channel Power MOSFETs. Switching Regulator and Controller ICs.
Technical Information on Ratings and Characteristics, ESD Sensitivity, Gate Drive and Thermal Considerations.
OEM PRICE LIST WITH CROSS REFERENCE
SILICONIX SHORT FORM CATALOG
MOSPOWER APPLICATIONS HANDBOOK - 1985
Rudy Severns et ai, Siliconix Incorporated. Introduction to MOSPOWER FETs. Power MOSFET Structures.
MOSFET Electrical Characteristics. Thermal Design And SOA. Practical Design Considerations. Applications
Information. MOSFET Testing and Reliability Appendices. (This handbook contains over 70 articles and application notes written by 31 experts in power processing. Hardbound. 488 p.p.)
DESIGNING WITH FIELD-EFFECT TRANSISTORS - 1981
Edited by Arthur D. Evans. Available at your technical bookstore or write to Suite 26-1; McGraw Hill Book Co,
1221 Avenue of the Americas; New York, NY 10020.
POWER FETS AND THEIR APPLICATIONS - 1982
Edwin S. Oxner, Staff Engineer, Siliconix, Inc. Available at your technical bookstore or write to: Mail Order
billing, Prentice-Hall ,Inc. , Tappan Road, Old Tappan, NJ 07675.
RELIABILITY REPORTS
Siliconix is dedicated to the manufacture of high quality, reliable products that meet the needs defined by our
customers. Reliability Reports exist for most of our products and new reports are continuously being generated
as new data becomes available. Customers that require reliability reports for specific devices are encouraged to
request them by calling (800) 554-5505.
14-1
III
:.II
..... Siliconix
incorporated
~
APPLICATION NOTES & TECHNICAL ARTICLES
KEY
•
•
•
•
=
=
=
IC 1988 Integrated Circuits Data Book
F 1986 FET Data Book
M 1988 MOSPOWER Data Book
MAH = 1985 MOSPOWER Applications Handbook
CATALOG
DOCUMENT
(SEE KEY)
NUMBER
TITLE
APPLICATION NOTES
F
F
F
IC
F
IC
F
IC
F
IC
IC
IC
MAH
MAH
F
MAH
IC
MAH
AN70-2
AN72-1
AN73-1
AN73-2
AN73-4
AN73-6
AN73-7
AN74-2
AN74-4
AN75-1
AN76-6
AN76-7
AN79-1
AN79-6
AN81-3
AN82-1
AN83-1
AN83-2
IC
IC
AN83-3
AN83-4
MAH
IC
F
MAH
MAH
MAH
IC
AN83-5
AN83-6
AN83-7
AN83-8
AN83-10
AN83-11
AN83-13
IC
F
F
IC
F
F
AN83-14
AN83-15
AN84-1
AN84-2
AN85-2
AN85-3
14-2
FETs for Video Amplifiers
FETs in Balanced Mixers
FETs as Voltage-Controlled Resistors
IC Multiplexer Increases Analog Switching Speeds
FETs in Balanced Mixers
Functionl Application of the L144 Programmable Micro-power Triple Op Amp
An Introduction to FETs
Analog Switches in Sample and Hold Circuits
Audio-Frequency Noise Characteristics of Junction FETs
CMOS Analog Switches - A Powerful Design Tool
DG300A Series Analog Switch Applications
Functionl Application of the L161 Micropower Comparator
A 500 kHz Switching Inverter for 12 V Systems
Using VMOS Transistors to Interface from IC Logic to High Power Loads
Composite Op Amp for High Performance
Solving the Stepper Motor Interface Problems
The DG308A Digitally Switches Analog Signals
Applying 240 Volt MOSPOWER Transistors and Current Limiting Diodes to
Electronic Pulse Dialer Circuits
A Microprocessor Compatible Analog Switch Makes Interfacing Easy
Improved System Performance Using Microprocessor Compatible Multliplexers
Boost OP-AMP Output Power with Complementary Power MOSFETS
A System solution to HP-IL Equipment Interface
A High-Quality Audio Crosspoint Switch
Frequency Response Analysis of the MOSFET Source-Follower
Safe Operating Area and Thermal Design for MOSPOWER Transistors
The D469: An Optimized CMOS Quad Driver for MOSPOWER FET Switches
Si8601 Data Acquisition System Interfaces for I/O or Memory Mapped
Operation
A Simple Approach to Si7135/8085 Interface
A High Performance Video Switch Using the SD5002
Applications for Si1000 Series JFET Amplifier
Theory and Applications of the Si7660 and Si7661 Voltage Converters
Designing a Super High Dynamic Range Double-Balanced Mixer
DMOS FET Analog Switches and Switch Arrays
.... Siliconix
incorporated
~
APPLICATION NOTES (Cont'd)
The DG536 Wide Band Multiplexer Suites a Wide Variety of Applications.
IC, M
IC, M
ANS6-1
ANS6-2
ANS7-1
ANS7-2
IC
IC
ANS7-3
ANS7-4
IC
ANSS-1
12 Bit CMOS Multiplying DAC
Improve System Precision with the Si7652 Chopper-Stablized Operational
Amplifier
Application for the 0469 MOSPOWER Driver
IC
ANSS-2
Microprocessor Compatible Multiplexers Facilitate Video Switching Designs
DASO-1
A Low Cost Regulator for Microprocessor Applications
IC
MOSPOWER in Motor Drives
A 1-Watt Flyback Converter Using the Si9100
Efficient ISDN Power Converters Using the Si9100
DESIGN AIDS
MAH
DESIGN IDEAS
DIS5-1
Designing a One Cell NiCd Powered VHF Oscillator
F
0171-1
The FET Constant Current Source
F
F
0171-9
0173-2
Wideband UHF Amplifier with High Performance FETs
High Performance FETs in Low-Noise VHF Oscillators
TECHNICAL ARTICLES
TA
TA
TA
A Monolithic High Voltage ACTFEL Row Driver for Symmetric Drive Schemes
Monolithic Video Multiplexer Directs 300 MHz Data in 300 ns.
TA
A High Efficiency Power MOSFET used as the Control Element in an SOO V
Switch
The Use of MOSFETs in High Dose Rate Radiation Environments
TA
TA
TA
TA
A 01 and JI Compatible Monolithic High Voltage Mux
Using the Si9100 for Design of 1 Watt Power Supply
What Do We Think Of The 6" Wafer
Special Features of Power MOSFETs in High Frequency Switching Circuits
F
IC
MAH
TA70-2
TA73-1
MAH
MAH
TAS3-2
TAS3-3
MAH
TAS4-1
MAH
MAH
TAS4-2
TAS4-3
Correlating the Charge-Transfer Characteristics of Power MOSFETS with
Switching Speed
Understanding MOSPOWER Transistor Characteristics Minimizes Incoming
Testing Requirements
MOSFETs Move in on Low Voltage Rectification
Power MOSFETs and Radiation Environments
MAH
TAS4-4
dV Ds/dt Turn-on in MOSFETs
MAH
TAS4-5
Parallel Operation of Power MOSFETs
IC
TAS7-1
Eliminate the Guess Work in Your Analog Switch Error Analysis
TAS3-1
FET Biasing
Multiplexer Adds Efficiency to 32-channel Telephone System
Using Power MOSFETs as High-Efficiency Synchronous and Bridge Rectifiers
in Switch-Mode Power Supplies
Controlling Oscillation in Parallel Power MOSFETS
14-3
Worldwide Sales Offices and Distributors
III
H
Siliconix
incorporated
U.S. Sales Representatives
ALABAMA
J..PAI::I.Q
MISSISSIPPI
See Washington
See Alabama
NORTH CAROLINA
Charlotte (28212)
Rep. Inc.
~cfrr~I~~T: ~J~r Cta;.k 425
1l04) 563-5554
F~:"n~64~~~~~g7
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See Washington
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See Washington
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Inc,
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ARKANSAS
~~1 g;~~J1664
Wilson Technical Sales, Inc.
P.O. Box 68t038
8752 Robbins Rd.
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NEBRASKA
NORTH PAKOTA
See Missouri
See Iowa
NEVAPA (Northern)
See California (Northern)
See Texas
NEVAPA (Clark County)
CALIFORNIA (Southern)
See Arizona
Tustin (92680)
Silicon lx, Inc.
17821 East 17th Street
Suite 240
11141 544-637818275
See Massachusetts
F~~tg~~~l:'~~~~
CALIFORNIA (Northern)
;~~~I~~ \:~14)
21710 Stevens Creek Blvd. I #100
~~1 ~~~~7682
NEW HAMPSHIRE
NEW JERSEY (Northern)
~
Wayne (07470)
lenexa (66219)
1479 Route
OKLAHOMA
Astrorep Incorporated
23
Sea Texas (Grand Prairie)
Midwest Technical Sales
~~1 ~g~j~~97
~~18t~~~_1103
NEW JERSEY (Southern)
~~::t ~~~lcal Sales
rf.~~W~ A~~=Jtes
15301 W. 87th Pkwy.
Suite 200
21901 La Vista
(316) 794-8585
OREGON
See Indiana
CONNECTICUT
LOUISIANA
See Texas
PENNSYLVANIA (Eastern)
~'l1:
See New Jersey (Southern)
NEW MEXICO
See Ohio
Albuquerque (87111)
PUERTO RICO
~W:II
PENNSYLVANIA (Western)
Quatra Associates, Inc.
9704 Admiral Dewey NE
See Massachusetts
PELAWARE
MARYLANP
See New Jersey (Southern)
Columbia (21046)
fLORIPA
~~~rr~~l~ ~~~~!t~~7~1).
657 Maitland Avenue
-IW~: ~6~-0321
FAX: 407-631-2844
Ft. lauderdale (33309)
g:~t~~:rh~~crJ3~~SStl~;at
~~1 ~~~~1019
tl~oR&~h:g~ci Road
w{'1l: Wo?::i-ll862
~~16~~6:~054
NEW YORK (Upstate)
Endwell (13760)
RHOPE ISLANP
~~~~1~~61~~5
607-7~557
See Massachusetts
3215 E. Main Street
MASSACHUSETTS
6836 E. Genesee Street
~~1~~~~110
~~r-~~~II~~ah1~g~I~S.
SOUTH CAROLINA
Inc.
¥u'~1: ~f~11-ll604
FAX: 315-446-3047
Fishkill (12524)
Trl-Tech Electronics, Inc.
14 Westview Drive
~~1411~:r~~1k05
F~:
914-897-5611 (Manual Receive)
E.
T
45)
Ics. Inc.
MINNESOTA
F~:II~~~=~~~
Burnsville (55337)
.I:I&lAII.
See California (Northern)
SOUTH PAKOTA
See Iowa
TENNESSEE
Jefferson City (37760)
Rep. Inc.
P. O. Bo 728
113 So.
~~1%~~~
Avenue
IE.KM
Suite 1
~4041 938-4358
Sea North Carolina
FAX: 61
GEORGIA
Tucker (30084)
~ ~~hlake Parkway
Inc.
~~1 ~8~~~gt~1
Trl-Tech Electronics, Inc.
FAX:
Pro Comp Associates, Inc.
1049 East Street
~:~t~~rc(~~~~lates.
Marcantll Plaza Bldg.
Suite 816
~~:lIg~\2:1~'lIl~
Tewksbury (01876)
Crown Electronic Sales
17020 S. W. Upper Boones Ferry Rd.
~~1~g~023
Evesham Commons
525 Route 73
Suite 1
KENTUCKY
Portland (97224)
Electromec Sales, Inc.
1601 East Highway 13
Suite 200
n~1: 8:;'~~~-ll232
FAX: 612-894-9352
NEW YORK (Metro/Long
Austin (78759)
.lm.DsIl.
IfG7:1S~!::~h IgTvd .
~~~~:p ~~b~~~rated
~~1 ~J~I~7254
103 Cooper Street
Suite 100, BI~. A
~!::~OO
FAX: 516-422-2504
15-1
H
Siliconix
incorporated
u.s. Sales Representatives (Cont'd)
TEXAS (Cool'd)
Grand Prairie (75050)
~~mi~~:re!T"
~2141 647-82.25
F~: In~i4~~9
Houston (77014-1696)
Ion Associates, Inc.
lmr-M~m'7 Chase Blvd.
FAX: 713-&7~612
!.!IAI:I.
WASHINGTON
Bait Lake City (64115)
Bellevua (98007)
WISCONSIN
~: : : ' : Main Street
Crown Electronic Sales
~~1 'W'i~W~52
~~1 ~:n~?s861
VERMONT
WEST VIRGINIA
WYOMING
see Massachusetts
Sea Ohio
See Colorado
14400 Bal-Rad Road, Sts. 108
VIRGINIA
PISTRICT OF COLUMBIA
See Maryland
See Maryland
Canadian Sales Representatives
North Gower, Ontario (M9B6E3)
Pipe Thompson, L.td.
(613) 258-4067
Chip Distributor
FLORIPA
Orlando (32810)
P!ll~ Supply, Inc.
7725 N. ora~ Blossom Trail
¥&~: r,~0~103
FAX:
305-29~164
u.S. Distributors
ALABAMA
~':~':,"!lle (35801)
~)'i1:~~parkWay South
FAX: 205-881-1490
Huntsvilia (35805)
Pioneer Huntsville
1~) ~~U Square
FAX: 205-837-9358
Huntsvilia (35816)
~s'Illlltrnr=~u"ara
Sta. #2D
~~1 roH:k~~o
ARIZONA
Chandler (85226)
Hamlltan/Avnet, N04
?~i ~,~I'OYI Ave.
TWX:
91D-95~77
Calabazas (91302)
Irvlna (92715)
ra,~r ~ci-9~ra Road
mlro Teller Ava.
San Diego (92123)
Wyle Laboratorles-EMG
9525 ChesaBrake Drive
Chatsworth (91311)
Hamilton Electro Sales,
#71 & 8
9650
Milpitas (95035)
Marshall
San Jose (95131)
~I. Laboratorl8s~MG
w,,~:
Chatsworth (91311)
Marshall
9710 DeSoto Avanua
~~1 :~L1~
X~~:: ~rJ:C~)
Marshall
~~) S41~&\rae1, Ste. B121
FAX: 602-893-11029
Phoenix (850231
~Laborator as-EMG
lJ021 ~= Canyon Hwy.
TWX: 910-1151-4282
CALIFORNIA
!\gaura Hills (91301)
~&=!m:.
~~1 ~~~464
15-2
Coches
2-4600
1D-339-9298
8-262-1224
w"'
ll: ~~~'590
FAX: 619-l;65-11171
f~ 8~~::r:.r::~ Road
~~1 :8:-1J~!oo85
Santa Clara (95052)
~1r i~~~~:n~~OUP
tW'~: ~~~~g~80
FAX: 408-727-2500, X303
350 McCormick Avenue
w",il: ~~~~~'928
)
on ~~te
10950
~~12 -837-9446
~a~c:i,T ~~~~lt.
9674 Telstar Avenue
~~1 :,;g~?s231
=~ Salas, #01
'6" W. 190th Streat
FAX: 602-1161-4555
Phoenix (85044)
TWX: 910-950-1946
1l~1 ¥il~1lfl-8366
a
217-8700
. 91(h'j40-8364
~!~:hl:lf1'8)
17rmrg~9~050
TWX:
~~~nloa~1A~~~6J03
1175 Bordeaux Avenue
~~:~1&~~
Yorba Linda (92686)
Zeus Components
WT~ ~~~anch Pkwy.
FAX: 714 -921-2715
COLORA pO
910~95-1969
Irvlna (92714/
m'r2~:n~::~~G
w",il:
m:g~'572
FAX: 714-863-D473
Thornton (80241)
Marshall
12351 N. Grant St.
Sta.l08
W~1 ~ga~~899
Siliconix
incorporated
u.s. Distributors (Continued)
Norcross (30071)
Future Electronics
3000 Northwoods Parkway
Suite 295
~~I :g.:~r~7580
Norcross (30093)
Marshall
5300
Pkwy .. Ste.240
tw~:
969
FAX: 404
743
Norcross (30071)
Ploneer/GA
3100 F Northwoods Place
(404) 448-1711
FAX: 404-446-5270
J.I.LI..IiQ.l.!
~:~~:~')Ay~~t~O:lo
1130 Thorndale Avenue
ru,~: g~g:~~~060
MASSACHUSETTS
Lexington (02173)
Pioneer
44 Hartwell Ave.
~~I ~~j:g~~1547
Lexington (02173)
Zeus
429 Marrett Road
~"i:~~~~1 (07006)
~~~}X~~:P)ElectronICS
n1l:
~f~~~7052
FAX: 201-882-0095
100 Centennial Drive
&~~\I~"'6~'l?,~Jf7aleS)
(01581)
nics
ad
~~~~~~~aB~'ya
ru,~: ~~~~1834
380 S. Northlake Blvd. I
Suite 1048
INDIANA
2215 29th Street S. E. A-5
#2B
~~Irg:~~:m
~W.13'W'~921
Altamonte Springs (32701)
Marshall
Indianapolis (46278)
380 S. Northlake Blvd. ,Sto.1024
~~lm~~916
~:~~~T~r;~"~s (32701)
221 North Lake Blvd.
~~:m~~177
FAX: 407-834-0865
201-575~54
MICHIGAN
~:~,T~~1~e:l,
Marshall
~~'l1'lI,':l:.';\~reJ87123)
~~lmjm028
~~:2jfo3i~
A:::"'~:;~~2l12~
Grand Rapids (49508)
Pioneer
4505 Broadmoor Ave. SE
~~I ~f~:J8~1831
':f~) ~C:~~ Drive
FAX: 317-297-2787
Indianapolis (46250)
~~¥) C::~~f~ Drive
TWX: 810-260-1794
FAX: 317-842-5998
derdale (33309)
n/Avnet, 1117
Way
• 510-956~097
FAX: 305-971-6420
Ovalda (00700)
Zeus
ts
1750
~~I
~g09r-m~~J6r.
Summit, Inc.
916
6
treat
-28001692
FAX
866
East Syracuse (13206)
-lUt
~
kf;~~~lf66214)
8321 Melrose Drive
(913)
492~121
Overland Park (66215)
Hamllton/Avnet. #58
9219 Qulvlra Road
Hamllton/Avnat
Unlverslt~
Blvd.
FAX: 407-678-1878
GEORGIA
~~fI~~~/~~:~)
#15
5825 Peachtree Comers E-O
tw~: :1~:~~g~2
FAX: 404-447-7526
893o-A Route 108
~~18gr:JJ.l~9764
Gaithersburg (20877)
Marshall
~df) Hg!i!l'~S Court
TWX: 710-628-9748
FAX: 301-840-6538
w"'ll: r,J..~~166
~:~N) 1~~~~~
~~~~~:tfe (11788)
275 Oser Avenue
MISSOURI
i\'~::,sh'::ll City (13790)
Lane
FAX: 612-559-6321
Zeus Components
~r~~7/~~h~~\er
840 Falrri'rt Park
11;:'1 7~6~~~~95S
~:::\l?t~~~~J~~1.8~ko
Marshall
Columbia (21045)
~G3"{!~~~/~~1~tb:I~:
ru,3l:
~~~~1560
FAX: 315-432-0740
933 Motor Parkway
Plymouth (55Ml)
~~:mjgg~74
~~:~~~~~22
Pioneer/Twin CIties
I:fi,~~'ang'e Dr.,Sle. G
TWX: 910-576-2738
FAX: 612-944~794
MARYLAND
St. Petersburg (33702)
6947
MINNESOTA
Eden Prairie (55344)
¥V.,~: ~J:~~~OO5
Hamliton/Avnet, #25
3197 Tech Drive No.
FAX: 813-577-6004
Wlntar Park (32792)
TWX: 910-989-0614
FAX: 605-243-1395
TWX: 610-252-0893
FAX: 607-722-9562
Buffalo (14202)
Pioneer Electronics
9~ ~21rJ8
~) ':S~~~~o'ive S.E.
NEW YORK
Deerfield Baach (33441)
Ft
11728 Linn N. E.
Binghamton (13904)
Pioneer IBlnghamton
Pioneer Indiana
~~I grti:l~7600
674 S. Mlllta[¥ Trail
NEW MEXICO
~~~rwt~~~~e\~S:3/)
Clearwater (34620)
Future Electronics
4900 N. Creekside Drive
n3i:
~~g~~~9653
FAX: 305-481-2950
~~: ~~~~g~~I!1'64)
n1l:
~rg~~82
FAX:
ru,~: ~~0~~~6
485 Gradle Drive
Marshall
158 Gaither Drive
I~~~! 234-9100 (NJ.l.
45 Route 46
1261 WII'/r. Road. #F
(32701)
Mt. Laurel (08054)
FAX: 609-778-1819
Marshall
FLORIDA
101 Fairfield Road
~lg~~~r058)
FAX: 312-437-0551
Schaumburg (60195)
~~,~:o~l:Cffci~rJl:
jl~O~I~tJ~fg;~~~~88
IFAX:
201-862-0095
~~I ~~:ggg?a807
FAX: 312-660-6530
Elk Grove Village (60007)
FAX: 312-490-0569
Fairfield 07006)
Hamllto
vnet, 619
~:::'7It~~YA~S;a'r.5J05
13743 Shoreline Court
ru,j/: m:j~~606
~~1 ~r~~~~775
129 Brown Street
-\W~: ~~g:~~!oI94
FAX: 607-797-7031
Port Chester (10523)
Zeus Components
100 Midland Avenule
~~I ~r~~~2553
~~ft~~erA~~~~3J61
333 Metro Park
-IUt'll: ~rg~~70
15-3
H
Siliconix
incorporated
u.s. Distributors (Continued)
NEW yoRK (Conl'd)
II:XM.
Rochester (14624)
Addison (75001)
Richardson (75081)
QUalilleCom~ents
Marshall
tr,Il
1250 Scottsville Road
~:r,g~
7~~allrcle
TWX: 910-860-5459
FAX: 214-250-0216
Austin (78758)
Hamllton/Avnet, 1126
1807A W. Braker Lane
Ronkonkoma (11779)
[~fS =~cr.:t~V8.
W~ll~~~~o
ru,~: f,I~~J~t319
Westbury (11690)
Hamllton/Avnet, 1r39
1065 Old C
Road
~':.~~~alr8754 )
ru,~: ~~~
8504 Cross Park Dr.
6
6
FAX: 516
Woodbury (11797)
ru,~: f,I~~8~1196
Plonoor/[ong Island
131if".Mf.!r'oJ'ark W.
FAX: 516-92H!143
~~!~iWo°
Austin
(918) 664-8812
(512) 834-9957
Carrollton (75006)
m~ ~~~r~~e~:'~~parkWay
Suite 600
~~: 81gjgg~03
~~~I1?=~8\~7m)
6024 S. W. Jean Road
~~ggi C6:!s~Mr6 to
TWX: 910~56-8179
PENNSYLVANIA
(214) 233-5200
Dallas (75240)
IDalias
1
29Z'~~:oad
• 214~90-8419
Houston (77040)
~~~:ll'~~At~~43
~~1 ~?~~J~?a662
15238)h
West Valley City (64119)
~ ~~or~~S-EMG
Ste. E
~~1 ~~t.:g~-2524
WASHINGTON
Bellevue (98007)
Marshall
14102 N.E. 21st St.
~~1 ~~::J~~2657
~~~S:~/~~~:~
w.,~: g~~~1606
~:~~s\~~~rJn
WISCONSIN
(713) 879-9953
Milwaukee (53214)
2111 W. Walnut Hili Lane
2800 Liberty Avenue, Bldg. E.
Salt Lake City (84115)
Marshall
466 Lawndale Dr., 8te. #0
5853 Point West Drive
w..~: ~~a~~778
215-674~107
1585 West 2100 South
¥t\!.1l:9lf~018
Marshall
11001 8. Wllcr.st, 8te.l00
FAX:
Salt Lake City (64119)
W~8) L:sl1l'_~oo
Horsham (19044)
Pioneer/HOrsham
261 Gibraltar Aoad
~~1 ~t8~988
~~1 ~~:J~!o936
\787581
~~~ ~~I~Ur~~~r Lane
Marshall
2045 Chenault St.
Hillsboro (97123)
Quality Components
1005 Ihdustrlal Boulevard
At Bournawood
HamlltonlAvnet, #09
~~~~t C~~~t~~e
Ste N 274
w.,~: 2:~o-lljl-5523
Sugarland (77478)
YIAIi
Austin (78758)
Tulsa (74129)
4850 wrl$'t Road 190
1826 Kramer Lane
~~1 m::gg~9829
g,u6-J1~. ~'II$'Il:'~~n.l.~.,
w..~: ~rg~g~~422
~~~ft'~nl~~~! N11
Austin (78758)
PioneerJAustin
OKLAHOMA
f:8S ~~~r:~v'm~S Drive
8ulte 120
~~~It'cr~~~et,
Marsh Electronics, Inc.
#16
W:W~~~929
Richardson (75083)
Wyle Distribution
1810 N. Greenville Avenue
w..~: ~0:8~7683
1563 South 101st Street
~~:~rg~~~1
FAX: 414-771-2847
New Berlin (53151~
~3.ffiIl~r~:~tR!.~
~~: ~ro~~118
Waukesha (53186)
Bell Industries
W227N913 W. Mound Dr.
~~lftI~~~7
Canadian Distributors
~:~~~n(~~:f:S~60
190 Colonade Road
(M3J 123)
ronlCB
Crescent N.
71
1-1470
(L4V 1M5)
6J:
exwood t
:
15-4
677-7432
61~92-8867
~!~mO
Pointe Claire (H9R 5C7)
~~t~~aE\~t~:;.'
237 Hymus Boulevard
1050 Baxter Road
(613) 820-8313
FAX:
Baxter Centre
Future Electronics ,
ru,~: ~~-.m~1
614-695~707
St. Laurent (H45 1P8)
ALBERTA
~:~ft~~~~~J68
2816 21st Street N. E.
(403) 250-9380
Hamllton/Avnet, #65
~~) R!M.~I83O"
TWX: 610~21~731
Siliconix
incorporated
H
European RepresentativesIDistributors
~
GERMANY
NETHERLANDS
UNITED KINGDOM
Bacher Electronics GmbH
Rotenmuhlgasse 26
Dltronlc GmbH
Jullus-Hoelder Str. 42
Koning en Hartman
Elektrotechnlek BV
P.O. Box 125
Abacus Electronics Ltd.
Abacus House
Bone Lane
A-1120 Wlen
TEL: (0222) 835645-0
TLX: 131532
FAX: (0222) 834275
BELGIUM
7000 StuttGart 70
f&:: ~'¥s11la~20010
FAX: (0711) 7200132
EBV Elektronlk GmbH
Obe
0-80
rhaching
J.P. lemaire S.A.
TEL:
TLX:
FAX:
+[~:: ~~~1~50-OS-S0
EBV Elektronik GmbH
Welmarstr 48
Av. Limburg Stlrum 243
6-1810 Wemmel
FAX: (02) 450-00-271
DENMARK
Delco A.S.
~~r~GggAll~rod
~Th': %2J) Wi!!?~
EIRE ClRELANPl
Hili Electronics
Klymore Park North
E~~W"e~rsot
TEL: 265299
TLX: 90708
FINLAND
Instrumentarium Elektronllkka
P.O.
BOK
64
~~L~2~J) i~3~
TLX: \24426 HAVUL SF
FAX: (90) 502 1073
105-1
105-230
7000 Stuttj\art 1
f&\ ~~'1161910-o
FAX: (0711) 613750
EBV Elektronlk GmbH
Vlersener Strasse 24
4040 Neuss
+&:: II!;l~~~f30072
FAX: 02101-593087
EBV Elektronlk GmbH
Klebltzraln 18
3006 Bur~edel 1 Hannover
f&:: ~~6~ 80 870
EBV Elektronlk GmbH
Schenckstr 99
6000 Frankfurt M. 90
t&\ i~~9685037
FAX: (059) 7894458
Ing. Buro Rainer KOnig
KOnlgsbergerstrasse 16A
D. 1000 Berlin
TEL: 030-772-8009
TLX: 184707
Buro K. H. Dreyer
hweitzer-Rlng 36
bUJ~9b~7
Almex
~~p~ur~e L' Aubeplne
92164 Antony Cedex
f&:: ~1l0~g765.21.12
84
Ing. Bure K. H. Dreyer
Flensburger Strasse 3
2380 SChleswla,
FAX: (1) 46.66.60.28
f&:: ~~
C. G. E. Compasants
32 Rue Grange Dame Rose
92360 Maudon La Foret
Ultratronlk GmbH
Gewerbestr, 4
8036 Herrschln~
TEL: (1) 46.30.24.25
FAX: (1) 46.30.01.29
Feutrler
5 Rue Jean Zay
42271 St. Priest En Jarez Cedex
f&:: &1?0~i93.40.40
FAX: (1) 77.93.26.31
I. T. T. Multlcomposants
Z.I. de Courtaboeuf
Avenue des Andes
4055
t&:: l&~~2J 3 09-0
NORWAY
~v~e ~~~\I~~:~~ 20
Dott Ing. Giuseppe De Mlco
S.P.A.
.
20060 Casslna de Pecchl
Via Vittorio Veneto 8
Milano
91940 Les Ulls
t&:. ~1l8~g·20.551
FAX: (02) 9522227
~~bu~e~fiG14 5SF
FAX: (0635) 38670
TLX: 847589
Abercorn Electronics Ltd.
Suite lA
17 Waterloo Place
!f~lr:b~t~S:f~t~~2d EH1 3BG
P.O. Box 27
N-2001 Llllestr¢m
TLX: 727229
FAX: 031-556-7246
FAX: (02) 831455
~~~f'SU~:~:'R~~~~'P~
t&\ \~or-02-20
PORTUGAL
Crlstalonica Lda.
Rua Bernardlm Ribeiro
25 ric Dto.e. Esq.
1100 Llsboa
t&:: ~1~631. 540314, 561755
~
Redlslogar S. A.
Corazon de Marla, No. 7
28002 Madrid
t&:: ~1J6~13 91 11
FAX: (91) 416 19 71
~~~~~cfB~2fo
Barcelona 11
TEL: (93) 254 90 48
SWEDEN
Komponentbolaget NAXAB
Box 4115
S-171-D4 Solna
TEL: 08-985140
TLX: 17912 KOMP
FAX: 08-7645451
SWITZERLAND
Abalec A.G.
Grabenstrasse 9
8952 Schlieren
TEL: 01-730-0455
TLX: 829070
FAX: 01-730-9801
FAX: (08152) 5183
.IIA.LY
FAX: (1) 64.46.95.95
SCAIB
f[~:: ~~i46.02.00
2600 AC Delft
TEL: 015-609906
TLX: 38250
FAX: 015-619194
Turkelek Electronic Co. Ltd .
Hatay Sokak No. 8
Ankara
TEL: (4) 11894 83
TLX: 44580
Barlec-Rlchfleld Ltd.
TEL: 0403-51881
TLX: 877222
FAX: 0403-41746
Farnell Electronic
Components Ltd.
Canal Road
Leeds LS12 2TU
TEL: 0532-636311
~~;:~~04
Hartech Ltd.
7 West Pall ant
Chichester
West
TEL:
TLX:
FAX:
P019 lTD
3511
9196
HB Electronics Ltd.
Lever Street
Bolton BL3 6BJ
t&:: ~~J 386361
FAX: (0204) 384911
Hili Electronics
290 Antrim Road
Belfast, N. Ireland
TEL: 755611
TLX: 747103
Macro-Marketing Ltd.
Burnham Lane
¥k"C':g?06~~~~s 4422
TLX: 947945
FAX: (05286) 56873
Semiconductor Specialists
b'!~)oht~ouse
~:s~'8~a~i~~et
Middlesex UB7 7XB
~~~~5J 445522, 446415
FAX: 0895-422044
t&\
YUGOSLAYIA
Contact: Belram S.A.
83 Avenue des Mimosas
8-1150 Brussels, Belgium
TEL. 734-33-32. 734-26-19
TLX: 21790
80 Rue d' Arcuel!
94523 Run~IS Cedex
t&:: ~11~7.j~7.23.13
FAX: (1) 45.60.55.49
15-5
H
Siliconix
incorporated
Rest of World RepresentativeslDistributors
ARGENTINA
Oodwell Industrial
8/F Tal Yau Bldg.
181 Johnston Road
YEL S.R.L.
~1~~g:I~.1~1
Wanchal
TEL: 5-8616200
TLX: 66623GILND HX
CABLE: GILMAN
FAX: 5-8934220
1037 Buenos Aires
TEL: 46-2211
TLX: 18605
AUSTRALIA
J..MQJA
Anltech
1-5 Carter Street
¥~E~~~~~So"8'1'
Orlol Services &
Consultants Pvt. Ltd.
2141
TLX: AA73780
FAX: 02_8-5964
P. B. No. 9275
4, Kurla Industrial Estate
Nara~an Na~ar. L.B.S. Marg.
e..BAZJ..L.
TLX: 011-72102
~
04571 Brooklin
Sao Paulo
Telsys Ltd.
Atldum Ind. Park, Bldg. 3
Dvora HaneYla St.
TEL: ~55-111 531-9355
TLX: 011) 53288
FAX: 55-11) 61-3nO
Authorized U. S. Agent
Neve Sharet
Tel-Aviv 61431
:::&:: W2~8~001
Etek ElectronIcs Corp.
1490 N. W. 79th Ave.
Miami. FL 33126
FAX: (3) 497407
~~~J83-1188
.IAfA.!::i
FAX: (305) 593-1762
HONG KONG
Array Electronics Ltd.
~~:~~Oh~S~,~:~~~~:atre
Tsusn Wan
NT
TEL: 0-4110083
61fsL~Y~~R~-:lLHK
~214) 647-8225
F~~:I1~~~~91s..~~~
NEW ZEALANP
Unit B, 192 Walrau Rd.
Glenfield
TEL: (09) 444 2645
Blnanda
Man1la
:::&:: W4gg2cr.~H
SINGAPORE
Carter Semiconductor (8) PTE Ltd.
~~p~~~a~~a~entre
¥~~:
1-1 Uchlsalwai-Cho, 2-Chorne
TO~~O 100
8
79
TLX: 36443 CARSIN
FAX: 734-2449
DOS Electronics PTE Ltd.
80 Gantlng Lane
KQBI;A
¥bn~:a~;J12
FAX: (02) 7847702
Tong Baek Trading Co. Ltd.
Rm. H201 New Hanll Bldg.
~,':.~tM~ ~~~~,¥~yc 9~du;~~lal
TEr,(021 7166625
TLX: K28569 TBTRACO
FAX: (02) 7190818
TEL: 3-521833
TWX: 37119 ATEK HX
FAX: 3-7644782
No. 02-09 Gentlng Block
Ruby Ind. C~'ex
.
R.O.S.
TLX: RS 35382 DOS
FAX: 743-7435
~:-1 ~~S~~r~~l
Ctr.
No. 19, Lam Hlng Street
0 HX
812 Elcano Street
TLX:
FAX:
~~~~~m
Kowloon Bay,
Kowloon
PHILIPPINES
Alexan Commercial
m\ W1Mf~WFigco
ConiC Investment Bldg.
13 Hoi< Yuen St.
~
~~,n ~~.S:ill~sXI ~~r~4
MALAYSIA
Lane 251
Nanking East Road
GE IndUstries SON BHD
Taipei
J;(:k
S~~:; :J?~man
KL 50000
~~I:a (~\"~M~-1703
TLX: MA 32149 PLAZAM
Sec. 5
m:: 1~~Tsg~'lJgb6
CABLE: DONBC TAIPEI
FAX: (02) 763-1241
J7~~~~~~erprlses Co. Ltd.
2 Wu Fu One Street
~~E~sig9~ 2517791
15-6
m:: 1&~5~9~vm~up
CABLE: DYNASUPPLY
VENEZUELA
P. Benavides S.R.L.
Avllanas a Rio Ediflcio
Rio Caribs, Local 9
Caracas
~r~a~~2~.F R.O.S.
Bldg.
35 Voldo-Dong Youngdeungpc:rKu
Seoul
~X~~:c;l;gUP~I.YO. P.
12 Sol Psana 1 Ekaml
Sukhumvlt 63
Bangkok 10110
Warburton - Frankie
Tomen ElectronIcs CorP9ratlon
~~~rr~~~.~?~:
FAX: 0-4995803
Atek Electronics Co. Ltd.
Unit 1009, 10lF
TEL: 3-7
TLX: 51226
FAX: 3-79988
CABLE: CEN
THAILANP
Grand PraIrie, Texas (75050)
Ion Associates Inc.
1504 1Q9th Street
¥~t~ gf:~d"J~a{'l~g~~86
Hltech
Av. Eng. Lulz Carlos 8errlnl
801 ConJ. 111/121
m::
~
TEL: 52-92-97
TLX: 21801 PBTH
H
Siliconix
incorporated
U. S. Sales Offices
EASTERN
CENTRAL
NORTHWESTERN
SOUTHWESTERN
511100nlx Inc.
31 Bailey Avenue
Ridgefield, CT 06877
Slllconlx Inc.
Silicon Ix Inc,
21710 Stevens Creek Blvd., #100
Cupertino, CA 95014
511100nlx Inc.
17821 E. 17th Steet
Suite 240
Tustin, CA 92680
(203) 431-3535
~~~:lIn~63~~~~~g~2
Slllconlx Inc.
460 Totten Pond Road, 2nd Floor
Waltham, MA 02154
(617) 890-7180
Easyllnk: 62914276
FAX: 617-890-0902
Slliconlx Inc.
Cranes Roost Office Park
6~~n~~;n8:~~e7're60~~~'
(312)
210
960-0106
Easyllnk: 62905249
FAX: 312-960-0329
Sillconlx Inc.
Two King James South
24650 Center Ridge Road, 5te.143
Westlake, OH 44145
(408) 252-4620
FAX: 408-255-7682
Sillconix Inc,
7476 E. Long Circle
Englewood, CO 80112
(714)
544-5378/7275
Easyllnk: 62912908
FAX: 714-731-0605
(303) 771-6886
FAX: 303-771-6887
(216)
835-4470
Easyllnk: 62910985
FAX:
216-835-9336
407 Whooping Loop, Ste.1647
Altamonte Springs, FL 32701
(407) 831-3644
Easyllnk: 62915200
FAX: 305-831-1321
SlIIconix Inc,
4020 Me Ewen
Suite 116
Dallas, TX. 75244
(214) 385-4046/4047
Easyllnk: 62897938
FAX: 214-385-0390
APPLICATIONS ASSISTANCE
Siliconix Inc.
2201 Laurelwood Road
Santa Clara, CA 95054
(408) 970-5393
TWX: 910-338-0227
FAX: 408-727-5414
Europe Sales Offices
UNITED KINGDOM
WEST GERMANY
FRANCE
ITALY
Siliconix Ltd.
3 London Road
Newbury, Berks, RG13 1JL
SllIconlx GmbH
Johannesstrasse 27. Postfach 1340
D-7024 Fllderstadt-l
Siliconix SARL
Centre Commercial de I' Echat
Place de I' Europe
F-94019 Cretell Cedex
tE~\ gbJ?g77.07.87
FAX: (1) 43.39.11. 71
Slliconlx SRL
Via Bartolomeo 0' AMano 18
20146 Milano
TEL: (02) 473661, 4228026
TLX: 331 837 "Pis Fwd
to SlIIconlx"
FAX: (02) 412.07.54
f&::
!~~~~~ 30905
fE~:: ~~~ml30002-o
FAX:
(0635) 34805
FAX:
SCANDINAVIA
Slllconlx Ltd.
~~~7~O~1 Jarfalla
Sweden
TEL: 08-795 93 90
TLX: 16404
FAX: 08-795 82 99
(0711) 70002-37
SllIconlx GmbH
Putzbrunner Strasse 19
8012 Ottobrunn
fE~:: ~~~~bg097835
FAX:
(089) 6095117
APPLICATIONS ASSISTANCE
Slilconlx Ltd.
Morriston! Swansea! SAG 6NE
TEL:
011-44-792-310100
FAX:
011-44-792-31040t
Far East Sales Offices
HONG KONG
JAPAN
APPLICATIONS ASSISTANCE
Slllconlx (H.K.) Ltd.
5th Floor
Liven House
61-63 King Yip Street
Kwun Tong! Kowloon
TEL:
3-427151
TLX:
44449SILXHX
FAX:
3-7978011
CABLE: Sillconlx
T~r~~~~d~Fw~I~g~~o~~xcl~~me
Slliconlx (H. K.) Ltd.
5th Floor
liven House
61-63 King Yip Street
Kwun Tong, Kowloon t Hong Kong
TEL:
3-427151
TLX:
44449SILXHX
FAX:
3-7559066
CABLE: Sillconix
Chlyoda-Ku, Tokyo 100
TEL:
03-506-3490
TLX:
J-23548
FAX:
03-506-3497
Manufacturing Locations
UNITED STATES
UNITED KINGDOM
HONG KONG
TAIWAN
Sillconix Incorporated
2201 Laurelwood Road
Santa Clara! CA 95054
SlIIconlx Ltd.
Morriston, Swansea SAS SNE
Slliconlx (H. K.) Ltd.
5/6/7/8th Floors
Liven House
61-63 King Yip Street
Kwun Tong! Kowloon
Slliconlx (Taiwan) Ltd.
Nantze Export Processing Zone
Kaohslung
15-7
ERRATA
The data sheets for the devices listed below contain a typographical error in the electrical tables. You will notice
we have incorporated into one test table the room temperature and minImax temperature parameter limits.
Some of the tables incorrectly show the minimum temperature limits for ON resistance and leakages to be the
same as the 25°C room temperature specifications. This should be changed so that the minimum temperature
limits match the 125°C limits.
The corrections required are to change the minimum temperature test (referenced as test #2) to be on the
same line as the maximum temperature test (referenced test #3).
Example:
Incorrect
Drain-Source ON
Resistance
I s =-10mA, V o =±8.5V
V+ = 13.5 V, V- = -13.5 V
Correct
Drain-Source ON
Resistance
Is = -10 rnA, Vo = ± 8.5 V
V+ = 13.5 V, V- = -13.5 V
The data sheets affected are:
D125
D129
D169
D470
DG123
DG125
DG221
DG243
DG300A/301 A/302A/303A
DGP303A
DG172
DG304A/305A/306A/307 A
DG308A/309
DG381 A/384A/387 A/390A
DG411/412/413
DG421 14231425
DG441 1442
DG444/445
DG180/181/182
DG183/184/185
DG186/187/188
DG189/190/191
DG480
DG485
DG501
DG503
DG200A
DGP201A
DGP508A
DG126/129/140
DG133/134/141
DG139/142/145
DG143/144/146
DG506A/507A
DG508A/509A
DG526/527
DG528/529
DG534
DG535
DG536
DG538
DG540
DG541
DG542
DG5040-5045
DG601
G118
G119
Si3002
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